[
  {
    "path": ".gitignore",
    "content": "*~\n*.pyc\n*.o\nlextab.py\nparselog.txt\nparser.out\nparsetab.py\n*.bo\n*.so\n*.ba\n*.cmd\n*.mod.c\n*.ko\nModule.symvers\n*.jou\n*.log\n.build\nmk*.cxx\nmk*.h\n*.bspec\nmodel_*.cxx\nmodel_*.h\nmk*.sched\nmk*.v\nmodules.order\nxilinx/pcie_7x_v2_1\nexamples/*/ac701\nexamples/*/kc705\nexamples/*/vc707\nexamples/*/zc702\nexamples/*/zc706\nexamples/*/de5\nexamples/*/htg4\nexamples/*/zedboard\nexamples/*/zybo\ngenerated/xilinx/*\ndkms.conf.out\n*.vcd\nbluesim\nxsim\nvc709\nvc707\nvc707g2\nusage_statistics_webtalk.*\nvivado_pid*\nnfsume\n.cache\nubuntu.exe\n*signature_file.h\n.tmp_versions\n.Xil\n*.mcs\nverilator\nzc706\n*.png\n*.bit\n*.prm\nzedboard\nminiitx100\n*.pb\nkc705g2\nac701g2\n*.ltx\nzedboard_ubuntu\n"
  },
  {
    "path": ".travis.yml",
    "content": "language: cpp\ncache:\n  directories:\nbefore_script:\n- if [ -d Bluespec-2018.10.beta1 ] ; then echo bluespec cached; else curl http://buildbot.connectal.org/downloads/Bluespec-2018.10.beta1.tar.gz | tar -zxf - ; fi\n- mkdir -p lib\n- ln -s /usr/lib/x86_64-linux-gnu/libgmp.so.10 lib/libgmp.so.3\n- if [ \"$CONNECTAL_ARCH\" == \"cvc\" ]; then if [ -d open-src-cvc-700c-1 ] ; then echo cvc cached; else curl -L https://github.com/cambridgehackers/open-src-cvc/archive/700c-1.tar.gz | tar -zxf - ; (cd open-src-cvc-700c-1/src; make -j4 -f makefile.cvc64); fi; fi\n- (if [ \"$CONNECTAL_ARCH\" == \"verilator\" ]; then curl -L http://www.veripool.org/ftp/verilator-3.888.tgz | tar -zxf -; cd verilator-3.888/; ./configure --prefix=`dirname $PWD`/verilator; make -j4;  make install; fi)\n- curl http://www.dabeaz.com/ply/ply-3.9.tar.gz | tar -zxf -\n- ln -s ../ply-3.9/ply scripts\n- ls -l scripts/ply\nenv:\n  global:\n    - BLUESPECDIR=$PWD/Bluespec-2018.10.beta1/lib\n    - PATH=$PATH:$PWD/Bluespec-2018.10.beta1/bin:$PWD/open-src-cvc-700c-1/src:$PWD/verilator/bin\n    - LD_LIBRARY_PATH=$PWD/lib\n  matrix:\n    - CONNECTAL_TEST=examples/echo CONNECTAL_ARCH=verilator\n    - CONNECTAL_TEST=examples/echopy CONNECTAL_ARCH=verilator\n    - CONNECTAL_TEST=examples/echo CONNECTAL_ARCH=cvc\n    - CONNECTAL_TEST=examples/echopy CONNECTAL_ARCH=cvc\n    - CONNECTAL_TEST=examples/echoslow CONNECTAL_ARCH=verilator\n    - CONNECTAL_TEST=examples/echoslow CONNECTAL_ARCH=cvc\n    - CONNECTAL_TEST=examples/simple CONNECTAL_ARCH=bluesim\n    - CONNECTAL_TEST=examples/simple CONNECTAL_ARCH=verilator\n    - CONNECTAL_TEST=examples/simple CONNECTAL_ARCH=cvc\n    - CONNECTAL_TEST=examples/memcpy CONNECTAL_ARCH=bluesim\n    - CONNECTAL_TEST=examples/memcpy CONNECTAL_ARCH=verilator\n    - CONNECTAL_TEST=examples/memcpy CONNECTAL_ARCH=cvc\n    - CONNECTAL_TEST=examples/strstr CONNECTAL_ARCH=bluesim\n    - CONNECTAL_TEST=tests/memserver_write128 CONNECTAL_ARCH=verilator\n    - CONNECTAL_TEST=tests/memserver_copy128 CONNECTAL_ARCH=verilator\nscript:\n- export PYTHONPATH=$PWD/scripts; make scripts/syntax/parsetab.py; cd $CONNECTAL_TEST; make build.$CONNECTAL_ARCH run.$CONNECTAL_ARCH\nsudo: no\ndist: trusty\nos:\n- linux\naddons:\n  apt:\n    sources:\n    - sourceline: 'ppa:jamey-hicks/connectal'\n    packages:\n    - python-dev\n    - libgmp10\n    - libjsoncpp-dev\n    - flex\n    - bison\nnotifications:\n  email: false\n  irc:\n    channels:\n    - chat.freenode.net#connectal\n\n  slack:\n    secure: mQApKri2F2TZEyLEs530x+snMA8aDdL6o0e/HCVqk3t4pfSfj2OfPQ5edVrvIh+dsFjhX1GNDk94LSmZTS6AVCQ4+VPXORN1VjvB+xIeyP/PsIjSUoWqvS2V0t8CYV5K+5HRJq2H7tNmY4wxZYQnPAAGplsrKgJBxjccMhSqO30=\n"
  },
  {
    "path": "LICENSE.txt",
    "content": "Copyright (c) 2012 Nokia, Inc.\nCopyright (c) 2013-2015 Quanta Research Cambridge, Inc.\n\nPermission is hereby granted, free of charge, to any person\nobtaining a copy of this software and associated documentation\nfiles (the \"Software\"), to deal in the Software without\nrestriction, including without limitation the rights to use, copy,\nmodify, merge, publish, distribute, sublicense, and/or sell copies\nof the Software, and to permit persons to whom the Software is\nfurnished to do so, subject to the following conditions:\n\nThe above copyright notice and this permission notice shall be\nincluded in all copies or substantial portions of the Software.\n\nTHE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\nEXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\nMERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\nNONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\nBE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\nACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\nCONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\nSOFTWARE.\n"
  },
  {
    "path": "Makefile",
    "content": "# Copyright (c) 2014 Quanta Research Cambridge, Inc\n#\n# Permission is hereby granted, free of charge, to any person obtaining a\n# copy of this software and associated documentation files (the \"Software\"),\n# to deal in the Software without restriction, including without limitation\n# the rights to use, copy, modify, merge, publish, distribute, sublicense,\n# and/or sell copies of the Software, and to permit persons to whom the\n# Software is furnished to do so, subject to the following conditions:\n#\n# The above copyright notice and this permission notice shall be included\n# in all copies or substantial portions of the Software.\n#\n# THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n# OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n# DEALINGS IN THE SOFTWARE.\n#\n\ninclude Makefile.version\n\nexport UDEV_RULES_DIR=/etc/udev/rules.d\nUDEV_RULES=$(shell ls etc/udev/rules.d)\nMODULES_LOAD_D_DIR=/etc/modules-load.d\n\nall: pciedrivers scripts/syntax/parsetab.py\n\techo version \"$(VERSION)\"\n\npciedrivers:\n\t(cd drivers/pcieportal; make)\n\tmake -C pcie\n\npciedrivers-clean:\n\t(cd drivers/pcieportal; make clean)\n\tmake -C pcie clean\n\nifneq (\"$(DESTDIR)\", \"\")\nINSTALL_SHARED = install-shared\nendif\n\ninstall: $(INSTALL_SHARED)\n\tinstall -d -m755 $(DESTDIR)/$(UDEV_RULES_DIR) $(DESTDIR)/etc/modules-load.d\n\tif [ -d $(DESTDIR)/$(MODULES_LOAD_D_DIR) ]; then \\\n\t    for fname in ./$(MODULES_LOAD_D_DIR)/* ; do \\\n\t\tinstall -m644 $$fname $(DESTDIR)$(MODULES_LOAD_D_DIR) ; \\\n\t    done; \\\n\tfi\n\techo 'Installing from' $(CURDIR)\n\t(cd drivers/pcieportal; CONNECTALDIR=$(CURDIR) make install)\n\tinstall -m644 etc/modules-load.d/connectal.conf $(DESTDIR)/etc/modules-load.d\n\tmake -C pcie install\n\tinstall -d -m755 $(DESTDIR)$(UDEV_RULES_DIR)\n\tfor fname in $(UDEV_RULES) ; do \\\n\t    install -m644 etc/udev/rules.d/$$fname $(DESTDIR)$(UDEV_RULES_DIR) ; \\\n\tdone\nifeq ( _$(DESTDIR), _)\n\tservice udev restart;\n\trmmod portalmem;\n\trmmod pcieportal;\n\tmodprobe portalmem;\n\tmodprobe pcieportal;\nendif\n\nINSTALL_DIRS = $(shell ls | grep -v debian)\n\ninstall-shared:\n\tfind $(INSTALL_DIRS) -type d -exec install -d -m755 $(DESTDIR)/usr/share/connectal/{} \\; -print\n\tfind $(INSTALL_DIRS) -type f -exec install -m644 {} $(DESTDIR)/usr/share/connectal/{} \\; -print\n\tchmod agu+rx $(DESTDIR)/usr/share/connectal/scripts/*\n\nuninstall:\n\tfor fname in ./$(MODULES_LOAD_D_DIR)/* ; do \\\n\t    rm -vf $(MODULES_LOAD_D_DIR)/`basename $$fname` ; \\\n\tdone;\n\t(cd drivers/pcieportal; make uninstall)\n\tmake -C pcie/connectalutil uninstall\n\tfor fname in $(UDEV_RULES) ; do \\\n\t    rm -f $(UDEV_RULES_DIR)/$$fname ; \\\n\tdone\n\tservice udev restart\n\ndocs:\n\tdoxygen scripts/Doxyfile\n\nspkg:\n\tgit clean -fdx\n\tgit checkout debian\n\tsed -i s/precise/precise/g debian/changelog\n\tgbp buildpackage --git-upstream-branch=master --git-debian-branch=ubuntu --git-ignore-new -S -tc '--git-upstream-tag=v%(version)s'\n\tgit checkout debian\n\tsed -i s/precise/trusty/g debian/changelog\n\tgbp buildpackage --git-upstream-branch=master --git-debian-branch=ubuntu --git-ignore-new -S -tc '--git-upstream-tag=v%(version)s'\n\tgit checkout debian\n\tsed -i s/precise/xenial/g debian/changelog\n\tgbp buildpackage --git-upstream-branch=master --git-debian-branch=ubuntu --git-ignore-new -S -tc '--git-upstream-tag=v%(version)s'\n\tgit checkout debian\n\tsed -i s/precise/artful/g debian/changelog\n\tgbp buildpackage --git-upstream-branch=master --git-debian-branch=ubuntu --git-ignore-new -S -tc '--git-upstream-tag=v%(version)s'\n\tgit checkout debian\n\nupload:\n\tgit push origin v$(VERSION)\n\t(cd  ../obs/home:jameyhicks:connectaldeb/connectal/; osc rm * || true)\n\tcp -v ../connectal_$(VERSION)*stable*.diff.gz ../connectal_$(VERSION)*stable*.dsc ../connectal_$(VERSION)*.orig.tar.gz ../obs/home:jameyhicks:connectaldeb/connectal/\n\trm -fv ../connectal_$(VERSION)*stable*\n\tdput ppa:jamey-hicks/connectal ../connectal_$(VERSION)-*_source.changes\n\t(cd ../obs/home:jameyhicks:connectaldeb/connectal/; osc add *; osc commit -m $(VERSION) )\n\t(cd ../obs/home:jameyhicks:connectal/connectal; sed -i \"s/>v.....</>v$(VERSION)</\" _service; osc commit -m \"v$(VERSION)\" )\n\n## PLY's home is http://www.dabeaz.com/ply/\ninstall-dependencies: install-dependences\n\ninstall-dependences:\nifeq ($(shell uname), Darwin)\n\tport install asciidoc\n\teasy_install ply\nelse\n\tif [ -f /usr/bin/yum ] ; then yum install gmp strace python-argparse python-ply python-gevent; else apt-get install libgmp10 strace python-ply python-gevent; fi\n\tif [ -f /usr/lib/x86_64-linux-gnu/libgmp.so ] ; then ln -sf /usr/lib/x86_64-linux-gnu/libgmp.so /usr/lib/x86_64-linux-gnu/libgmp.so.3 ; fi\n\tif [ ! -f /usr/lib64/libgmp.so.3 ] && [ -f /usr/lib64/libgmp.so.10 ] ; then ln -s /usr/lib64/libgmp.so.10 /usr/lib64/libgmp.so.3; fi\nendif\n\ninstall-python-example-dependences:\n\tsudo apt-get install python-dev\n\ninstall-doc-dependences:\n\tapt-get install asciidoc python-setuptools\n\teasy_install blockdiag seqdiag actdiag nwdiag libusb1\n\twget https://asciidoc-diag-filter.googlecode.com/files/diag_filter.zip\n\tasciidoc --filter install diag_filter.zip\n\twget http://laurent-laville.org/asciidoc/bootstrap/bootstrap-3.3.0.zip\n\tasciidoc --backend install bootstrap-3.3.0.zip\n\nBOARD=zedboard\n\nscripts/syntax/parsetab.py: scripts/syntax.py\n\t[ -e out ] || mkdir out\n\tpython3 scripts/syntax.py\n\nallarchlist = ac701 zedboard zc702 zc706 kc705 vc707 zynq100 v2000t bluesim miniitx100 de5 htg4 vsim parallella xsim zybo kc705g2 vc707g2\n\n#################################################################################################\n\nKROOT_ZYNQ := $(PWD)/../linux-xlnx/\n\nzynqdrivers:\n\t(cd drivers/zynqportal/; KROOT=$(KROOT_ZYNQ) make zynqportal.ko)\n\t(cd drivers/portalmem/;  KROOT=$(KROOT_ZYNQ) make portalmem.ko)\n\nzynqdrivers-clean:\n\t(cd drivers/zynqportal/; KROOT=$(KROOT_ZYNQ) make clean)\n\t(cd drivers/portalmem/;  KROOT=$(KROOT_ZYNQ) make clean)\n\nzynqdrivers-install:\n\tinstall -d -m755 $(DESTDIR)/usr/share/connectal-zynqdrivers/\n\tinstall -m644 drivers/zynqportal/zynqportal.ko drivers/portalmem/portalmem.ko $(DESTDIR)/usr/share/connectal-zynqdrivers/\n\n# For the parallella build to work, the cross compilers need to be in your path\n# and the parallella kernel needs to be parallel to connectal and built\nKROOT_PAR  := $(PWD)/../parallella-linux/\nparallelladrivers:\n\t(cd drivers/zynqportal/; CROSS_COMPILE=arm-linux-gnueabihf- KROOT=$(KROOT_PAR) make parallellazynqportal.ko)\n\t(cd drivers/portalmem/; CROSS_COMPILE=arm-linux-gnueabihf- KROOT=$(KROOT_PAR) make parallellaportalmem.ko)\n\nparallelladrivers-clean:\n\t(cd drivers/zynqportal/;  CROSS_COMPILE=arm-linux-gnueabihf- KROOT=$(KROOT_ZYNQ) make clean)\n\t(cd drivers/portalmem/;   CROSS_COMPILE=arm-linux-gnueabihf- KROOT=$(KROOT_ZYNQ) make clean)\n\nRUNPARAMTEMP=$(subst :, ,$(RUNPARAM):5555)\nRUNIP=$(wordlist 1,1,$(RUNPARAMTEMP))\nRUNPORT=$(wordlist 2,2,$(RUNPARAMTEMP))\n\nzynqdrivers-adb:\n\tadb connect $(RUNPARAM)\n\tadb -s $(RUNIP):$(RUNPORT) shell pwd || true\n\tadb connect $(RUNPARAM)\n\tadb -s $(RUNIP):$(RUNPORT) root || true\n\tsleep 1\n\tadb connect $(RUNPARAM)\n\tadb -s $(RUNIP):$(RUNPORT) push drivers/zynqportal/zynqportal.ko /mnt/sdcard\n\tadb -s $(RUNIP):$(RUNPORT) push drivers/portalmem/portalmem.ko /mnt/sdcard\n\tadb -s $(RUNIP):$(RUNPORT) shell rmmod zynqportal\n\tadb -s $(RUNIP):$(RUNPORT) shell rmmod portalmem\n\tadb -s $(RUNIP):$(RUNPORT) shell insmod /mnt/sdcard/zynqportal.ko\n\tadb -s $(RUNIP):$(RUNPORT) shell insmod /mnt/sdcard/portalmem.ko\n\nconnectalspi-clean:\n\t(cd drivers/connectalspi/; KROOT=$(KROOT_ZYNQ) make clean)\n\nconnectalspi:\n\t(cd drivers/connectalspi/; KROOT=$(KROOT_ZYNQ) make connectalspi.ko)\n\nconnectalspi-adb: \n\tadb connect $(RUNPARAM)\n\tadb -s $(RUNIP):$(RUNPORT) shell pwd || true\n\tadb connect $(RUNPARAM)\n\tadb -s $(RUNIP):$(RUNPORT) root || true\n\tsleep 1\n\tadb connect $(RUNPARAM)\n\tadb -s $(RUNIP):$(RUNPORT) push drivers/connectalspi/connectalspi.ko /mnt/sdcard\n\tadb -s $(RUNIP):$(RUNPORT) shell rmmod connectalspi\n\tadb -s $(RUNIP):$(RUNPORT) shell insmod /mnt/sdcard/connectalspi.ko\n\tadb -s $(RUNIP):$(RUNPORT) shell chmod 777 /dev/spi*\n\ndistclean: pciedrivers-clean\n\tfor archname in $(allarchlist) ; do  \\\n\t   rm -rf examples/*/\"$$archname\" tests/*/\"$$archname\"; \\\n\tdone\n\trm -rf pcie/connectalutil/connectalutil tests/memread_manual/kernel/bsim_relay\n\trm -rf out/ exit.status cpp/*.o scripts/*.pyc\n\trm -rf tests/*/train-images-idx3-ubyte examples/*/train-images-idx3-ubyte\n\trm -rf doc/library/build/ examples/rbm/datasets/\n\trm -f doc/library/source/devguide/connectalbuild-1.png\n\trm -rf tests/partial/variant2\n"
  },
  {
    "path": "Makefile.connectal",
    "content": "# Copyright (c) 2014 Quanta Research Cambridge, Inc\n#\n# Permission is hereby granted, free of charge, to any person obtaining a\n# copy of this software and associated documentation files (the \"Software\"),\n# to deal in the Software without restriction, including without limitation\n# the rights to use, copy, modify, merge, publish, distribute, sublicense,\n# and/or sell copies of the Software, and to permit persons to whom the\n# Software is furnished to do so, subject to the following conditions:\n#\n# The above copyright notice and this permission notice shall be included\n# in all copies or substantial portions of the Software.\n#\n# THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n# OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n# DEALINGS IN THE SOFTWARE.\n#\n\nCONNECTALDIR=$(shell dirname $(realpath $(lastword $(MAKEFILE_LIST))))\ninclude $(CONNECTALDIR)/Makefile.version\n\nV?=0\nifeq ($(V),0)\nQ=@\nVERBOSE_SWITCH=\nelse\nQ=\nVERBOSE_SWITCH=--verbose\nendif\n\n#PROJECTDIR?=$(BOARD)\n\nbozotarget:\n\t@echo \"Makefile.connectal: please invoke with make gen.boardname\"\n\nVARIANT_PROJECTS := $(foreach item,$(VARIANT_LIST),variantgen.$(item))\n#\n## use \"make gen.board\" to generate the build directory\ngen.%:\nifeq ($(BOARD),)\n\t$(eval BOARD := $*)\nendif\nifeq ($(PROJECTDIR),)\n\t$(eval PROJECTDIR := $*)\nendif\n\t+BOARD=$(BOARD) PROJECTDIR=$(PROJECTDIR) $(MAKE) --no-print-directory gentarget prebuild $(VARIANT_PROJECTS)\n\nvariantgen.%:\n\tBOARD=$(BOARD) PROJECTDIR=variant$* \\\n\t    VARIANT=$* PRTOP_FILE=../$(BOARD)/Impl/TopDown/top-post-route.dcp \\\n\t    $(MAKE) --no-print-directory gentarget prebuild\n\nbuild.%: gen.%\n\t$(MAKE) -C $(PROJECTDIR) --no-print-directory all\n\nverilog.%: gen.%\n\t$(MAKE) -C $(PROJECTDIR) --no-print-directory verilog\nexe.%: gen.%\n\t$(MAKE) -C $(PROJECTDIR) --no-print-directory exe\nbits.%: verilog.%\n\t$(MAKE) -C $(PROJECTDIR) --no-print-directory bits\n\nrun.%:\nifeq ($(PROJECTDIR),)\n\t$(eval PROJECTDIR := $*)\nendif\n\t$(MAKE) -C $(PROJECTDIR) --no-print-directory run\n\nIPDIR?=$(CONNECTALDIR)/out\nNUMBER_OF_USER_TILES?=1\nSLAVE_DATA_BUS_WIDTH?=32\nSLAVE_CONTROL_ADDR_WIDTH?=5\nPLATFORM_NUMBER_OF_MASTERS?=1\nPIN_TYPE?=Empty\nPIN_TYPE_INCLUDE?=Misc\n#need to import into HostInterface, can't use HostInterface\n\nifndef BURST_LEN_SIZE\nBURST_LEN_SIZE=10\nendif\n\nCONNECTALFLAGS += -D ConnectalVersion=$(VERSION)\nCONNECTALFLAGS += -D NumberOfMasters=$(PLATFORM_NUMBER_OF_MASTERS) -D PinType=$(PIN_TYPE) -D PinTypeInclude=$(PIN_TYPE_INCLUDE)\nCONNECTALFLAGS += -D NumberOfUserTiles=$(NUMBER_OF_USER_TILES)\nCONNECTALFLAGS += -D SlaveDataBusWidth=$(SLAVE_DATA_BUS_WIDTH)\nCONNECTALFLAGS += -D SlaveControlAddrWidth=$(SLAVE_CONTROL_ADDR_WIDTH)\nCONNECTALFLAGS += -D BurstLenSize=$(BURST_LEN_SIZE)\nCONNECTALFLAGS += --ipdir=$(IPDIR)\nCNOC?=$(shell grep -q CnocTop $(CONNECTALDIR)/boardinfo/$(BOARD).json && echo --cnoc)\nUSE_CNOC?=$(shell grep -q SIMULATION $(CONNECTALDIR)/boardinfo/$(BOARD).json && echo cnoc)\nifneq ($(AUTOTOP),)\nUSE_AUTOTOP = 1\nendif\nifneq ($(S2H_INTERFACES),)\nUSE_AUTOTOP = 1\nendif\nifneq ($(H2S_INTERFACES),)\nUSE_AUTOTOP = 1\nendif\nifneq ($(MEM_INTERFACES),)\n$(error Convert use of MEM_INTERFACES into MEM_READ_INTERFACES and MEM_WRITE_INTERFACES)\nendif\nifneq ($(MEM_READ_INTERFACES),)\nUSE_AUTOTOP = 1\nendif\nifneq ($(MEM_WRITE_INTERFACES),)\nUSE_AUTOTOP = 1\nendif\n\nINTERFACES += MemServerRequest MMURequest MemServerIndication MMUIndication\nBSVFILES += $(CONNECTALDIR)/bsv/ConnectalMemory.bsv\nifneq ($(NUMBER_OF_MASTERS), 0)\nCPPFILES += $(CONNECTALDIR)/cpp/dmaManager.c $(CONNECTALDIR)/cpp/platformMemory.cpp\nCPPFILES2_dma = $(CONNECTALDIR)/cpp/dmaManager.c $(CONNECTALDIR)/cpp/platformMemory.cpp\nendif\n\nINTERFACES_cnoc = XsimMsgRequest XsimMsgIndication\nCPPFILES_cnoc   = $(CONNECTALDIR)/cpp/transportXsim.c\nBSVFILES_cnoc   = $(CONNECTALDIR)/bsv/XsimIF.bsv\nCPPFILES2_cnoc  = $(CONNECTALDIR)/cpp/transportXsim.c\n\nINTERFACES += $(INTERFACES_$(USE_CNOC))\nCPPFILES   += $(CPPFILES_$(USE_CNOC))\nBSVFILES   += $(BSVFILES_$(USE_CNOC))\n\nifneq ($(PYFILES),)\nCONNECTALFLAGS += --shared -D PORTAL_JSON\nCPPFILES += $(CONNECTALDIR)/cpp/portalPython.cpp\nCPPFILES2 = $(CONNECTALDIR)/cpp/runpython.cpp\nifneq ($(BOARD),zedboard)\nifneq ($(BOARD),zedboard_ubuntu)\nCONNECTALFLAGS += -ljsoncpp\nendif\nendif\n\nifeq ($(BOARD),zedboard)\n## git clone git://github.com/cambridgehackers/python-for-android-sdk\nPYTHON_FOR_ANDROID ?= $(CONNECTALDIR)/../python-for-android-sdk\nCONNECTALFLAGS += -I$(PYTHON_FOR_ANDROID)/include/ -I.\nCONNECTALFLAGS += -L$(PYTHON_FOR_ANDROID)/lib -lpython2.7\nCONNECTALFLAGS += --stl=gnustl_static --cxxflags=-fexceptions --android-toolchain=4.8\n\nCPPFILES  += jsoncpp/dist/jsoncpp.cpp\nCPPFILES2 += jsoncpp/dist/jsoncpp.cpp\n\nprebuild::\n\t[ -d jsoncpp ] || git clone git://github.com/open-source-parsers/jsoncpp\n\tcd jsoncpp; python3 amalgamate.py; mkdir -p json; cd json; ln -sf ../dist/json/*.h .\nendif #zedboard\n\nifeq ($(BOARD),zedboard_ubuntu)\nCONNECTALFLAGS += --cxxflags=-std=c++11\nCONNECTALFLAGS += -I usr/include\nCONNECTALFLAGS += -L usr/lib/arm-linux-gnueabihf -lpython2.7\n\nCPPFILES  += jsoncpp/dist/jsoncpp.cpp\nCPPFILES2 += jsoncpp/dist/jsoncpp.cpp\n\nprebuild::\n\t[ -d jsoncpp ] || git clone git://github.com/open-source-parsers/jsoncpp\n\tcd jsoncpp; python3 amalgamate.py; mkdir -p json; cd json; ln -sf ../dist/json/*.h .\nendif # zedboard_ubuntu\nendif # PYFILES\n\nifneq ($(CPPFILES2),)\nALL_CPPFILES2 = $(CPPFILES2) $(CPPFILES2_$(USE_CNOC)) $(CPPFILES2_dma)\nendif\n\nall bits verilog implementation bsim xsim vsim xsimrun: gentarget prebuild\n\t+make -C $(PROJECTDIR) --no-print-directory $@\n\nandroid.exe bsim_exe ubuntu.exe exe: gentarget\n\t+make -C $(PROJECTDIR) --no-print-directory $@\n\nZYNQ_MPSOC=$(shell jq -r .options.ZYNQ_MPSOC < $(CONNECTALDIR)/boardinfo/$(BOARD).json)\nPCIEGEN=$(shell jq -r .options.need_pcie < $(CONNECTALDIR)/boardinfo/$(BOARD).json | sed 's/.*gen\\([123]\\).*/\\1/')\nNEED_XILINX_PCIE_ac701=$(PCIEGEN)\nNEED_XILINX_PCIE_ac701g2=$(PCIEGEN)\nNEED_XILINX_PCIE_kc160g2=$(PCIEGEN)\nNEED_XILINX_PCIE_kc705g2=$(PCIEGEN)\nNEED_XILINX_PCIE_vc707g2=$(PCIEGEN)\nNEED_XILINX_PCIE_kc705=$(PCIEGEN)\nNEED_XILINX_PCIE_vc707=$(PCIEGEN)\nNEED_XILINX_PCIE_kcu105=3u\nNEED_XILINX_PCIE_vcu108=3u\nNEED_XILINX_PCIE_zcu102=3u\nNEED_XILINX_PCIE_nfsume=3\nNEED_XILINX_PCIE_vc709=3\nNEED_XILINX_PCIE_v2000t=1\nNEED_XILINX_PCIE_vcu118=3u_plus\n\nNEED_ALTERA_PCIE_de5=1\nNEED_ALTERA_PCIE_htg4=1\n\nNEED_ALTERA_ETH_de5=1\nNEED_ALTERA_ETH_htg4=1\nQUARTUS_SH=$(shell which quartus_sh)\n\nifeq ($(NEED_XILINX_PCIE_$(BOARD)),1)\n#    FPGAMAKE_CONNECTALFLAGS += -P mkPcieEndpointX7 -P mkPcieHost\n    CONNECTALFLAGS += --xci=$(IPDIR)/$(BOARD)/pcie_7x_0/pcie_7x_0.xci\n    CONNECTALFLAGS += --bscflags=\"+RTS -K46777216 -RTS\"\nendif\nifeq ($(PCIEGEN),2)\n    FPGAMAKE_CONNECTALFLAGS += -P mkPcieHost\n    CONNECTALFLAGS += --xci=$(IPDIR)/$(BOARD)/pcie2_7x_0/pcie2_7x_0.xci\n    CONNECTALFLAGS += --bscflags=\"+RTS -K46777216 -RTS\"\nendif\n\nifeq ($(NEED_XILINX_PCIE_$(BOARD)),3)\n    FPGAMAKE_CONNECTALFLAGS += -P mkPcieHost\n    CONNECTALFLAGS += --xci=$(IPDIR)/$(BOARD)/pcie3_7x_0/pcie3_7x_0.xci\n    CONNECTALFLAGS += --bscflags=\"+RTS -K46777216 -RTS\"\nendif\nifeq ($(NEED_XILINX_PCIE_$(BOARD)),3u)\n    CONNECTALFLAGS += --xci=$(IPDIR)/$(BOARD)/pcie3_ultrascale_0/pcie3_ultrascale_0.xci\n    CONNECTALFLAGS += --bscflags=\"+RTS -K46777216 -RTS\"\nendif\nifeq ($(NEED_XILINX_PCIE_$(BOARD)),3u_plus)\n    CONNECTALFLAGS += --xci=$(IPDIR)/$(BOARD)/pcie_uscale_plus_0/pcie_uscale_plus_0.xci\n    CONNECTALFLAGS += --bscflags=\"+RTS -K46777216 -RTS\"\nendif\n\nifeq ($(NEED_ALTERA_PCIE_$(BOARD)),1)\n\tFPGAMAKE_CONNECTALFLAGS += --xci=$(IPDIR)/$(BOARD)/synthesis/altera_pcie_reconfig_driver_wrapper/altera_pcie_reconfig_driver_wrapper.qip\n\tFPGAMAKE_CONNECTALFLAGS += --xci=$(IPDIR)/$(BOARD)/synthesis/altera_pcie_sv_hip_ast_wrapper/altera_pcie_sv_hip_ast_wrapper.qip\n\tFPGAMAKE_CONNECTALFLAGS += --xci=$(IPDIR)/$(BOARD)/synthesis/alt_xcvr_reconfig_wrapper/alt_xcvr_reconfig_wrapper.qip\n\t#FPGAMAKE_CONNECTALFLAGS += --xci=$(IPDIR)/$(BOARD)/siv_gen2x8/siv_gen2x8.qip\n\tFPGAMAKE_CONNECTALFLAGS += --tcl=$(PROJECTDIR)/generatedbsv/$(BOARD).qsf\n\tFPGAMAKE_CONNECTALFLAGS += --tcl=$(CONNECTALDIR)/constraints/altera/$(BOARD).sdc\n\tCONNECTALFLAGS += --bscflags=\"+RTS -K46777216 -RTS -demote-errors G0066:G0045 -suppress-warnings G0046:G0020:S0015:S0080:S0039\"\nendif\nifeq ($(ZYNQ_MPSOC),zynq_ultra_ps_e)\n    CONNECTALFLAGS += --xci=$(IPDIR)/$(BOARD)/zynq_ultra_ps_e_0/zynq_ultra_ps_e_0.xci\nendif\n\nCONNECTALFLAGS += $(FPGAMAKE_CONNECTALFLAGS)\nifeq ($(USE_BUILDCACHE),1)\nBUILDCACHE?=$(CONNECTALDIR)/../buildcache/buildcache\nBUILDCACHE_CACHEDIR?=$(CONNECTALDIR)/../fpgamake-cache/$(shell basename `/bin/pwd`)/$(PROJECTDIR)\nCONNECTALFLAGS += --cache=$(BUILDCACHE_CACHEDIR)\nendif\n\nCONNECTALFLAGS += $(EXTRA_CONNECTALFLAGS)\n\nifeq ($(USE_PRINTF),1)\nPRINTF_EXTRA=$(PROJECTDIR)/generatedbsv/DisplayInd.bsv\nelse\nPRINTF_EXTRA=$(CONNECTALDIR)/bsv/DisplayInd.bsv\nendif\n\nifneq ($(USE_AUTOTOP),)\nGPROJ = $(PROJECTDIR)/generatedbsv\nGENTOP = $(GPROJ)/IfcNames.bsv\nendif\n\ncomma := ,\ngentarget:: process_autotop generate_altera_custom\n\t@[ -e $(CONNECTALDIR)/scripts/syntax/parsetab.py ] || make -C $(CONNECTALDIR) scripts/syntax/parsetab.py\nifeq ($(USE_PRINTF),1)\n\t$(CONNECTALDIR)/scripts/preprocess_trace.py $(PROJECTDIR) $(BSVFILES)\nendif\n\t$(Q)$(CONNECTALDIR)/scripts/makefilegen.py -B$(BOARD) --project-dir $(PROJECTDIR) \\\n\t$(foreach interfaces, $(INTERFACES), -interfaces $(interfaces)) \\\n\t$(foreach f, $(CPPFILES), --source $f) \\\n\t$(foreach f, $(ALL_CPPFILES2), --source2 $f) \\\n\t$(foreach f, $(BSVPATH), --bsvpath $f) \\\n\t$(foreach f, $(PINOUT_FILE), --pinout $f) \\\n\t$(foreach f, $(PIN_BINDINGS), --pin-binding $f) \\\n\t$(foreach f, $(PRTOP_FILE), --prtop $f) \\\n\t$(foreach f, $(VARIANT_LIST), --prvariant $f) \\\n\t$(foreach f, $(RECONFIG_MODULE), --reconfig $f) \\\n\t$(foreach f, $(S2H_INTERFACES), -interfaces $(word 1, $(subst /,, $(subst :, , $f)))) \\\n\t$(foreach f, $(H2S_INTERFACES), $(foreach g, $(subst $(comma), , $(word 2, $(subst :, , $f))), -interfaces $g)) \\\n\t$(foreach f, $(PORTAL_DUMP_MAP), --dump_map $f) \\\n        $(CONNECTALFLAGS) $(BSVFILES) $(GENTOP) $(PRINTF_EXTRA) $(VERBOSE_SWITCH)\n\nprocess_autotop::\n\t$(Q)[ -e $(PROJECTDIR) ] || mkdir -p $(PROJECTDIR)\n\ttouch $(PROJECTDIR)/Makefile.autotop\nifneq ($(USE_AUTOTOP),)\n\t$(Q)[ -e $(GPROJ) ] || mkdir -p $(GPROJ)\n\t$(Q)$(CONNECTALDIR)/scripts/topgen.py --project-dir $(GPROJ) $(AUTOTOP) $(CNOC) \\\n\t    $(foreach f, $(S2H_INTERFACES), --wrapper $f) \\\n\t    $(foreach f, $(H2S_INTERFACES), --proxy $f)   \\\n\t    $(foreach f, $(MEM_READ_INTERFACES), --memread $f)   \\\n\t    $(foreach f, $(MEM_WRITE_INTERFACES), --memwrite $f)\nendif\n\ngenerate_altera_custom::\nifneq ($(PIN_BINDINGS), )\nifneq ($(filter $(BOARD), de5 htg4), )\n\t$(Q)[ -e $(PROJECTDIR)/generatedbsv ] || mkdir -p $(PROJECTDIR)/generatedbsv\n\t$(CONNECTALDIR)/scripts/generate-constraints.py -f altera \\\n\t\t$(foreach f, $(PIN_BINDINGS), -b $f) \\\n\t\t-o $(PROJECTDIR)/generatedbsv/$(BOARD).qsf \\\n\t\t--boardfile $(CONNECTALDIR)/boardinfo/$(BOARD).json --pinoutfile $(PINOUT_FILE)\nendif\nelse\n\t$(Q) if [ -e $(CONNECTALDIR)/constraints/altera/$(BOARD).qsf ]; then cp $(CONNECTALDIR)/constraints/altera/$(BOARD).qsf $(PROJECTDIR)/generatedbsv/$(BOARD).qsf; fi\nendif\n\nprebuild::\n\t@# additional steps needed before making verilog etc\nifneq ($(NEED_XILINX_PCIE_$(BOARD)),)\n\t@echo \"building ... $(BOARD) PCIe gen$(PCIEGEN)\"\n\t$(Q)[ -e $(IPDIR) ] || mkdir -p $(IPDIR)\n\tcd $(PROJECTDIR); BUILDCACHE_CACHEDIR=$(BUILDCACHE_CACHEDIR) $(BUILDCACHE) vivado -notrace -mode batch -source $(shell cd $(CONNECTALDIR); /bin/pwd)/scripts/connectal-synth-pcie.tcl\nendif\nifeq ($(ZYNQ_MPSOC),zynq_ultra_ps_e)\n\t@echo \"building ... $(BOARD) Zynq MPSOC core\"\n\t$(Q)[ -e $(IPDIR) ] || mkdir -p $(IPDIR)\n\tcd $(PROJECTDIR); BUILDCACHE_CACHEDIR=$(BUILDCACHE_CACHEDIR) $(BUILDCACHE) vivado -notrace -mode batch -source $(shell cd $(CONNECTALDIR); /bin/pwd)/scripts/connectal-synth-zynq-mpsoc.tcl\nendif\n\nifneq (, $(QUARTUS_SH))\n# Synthesis Altera PCIe Core and PLL\nifeq ($(NEED_ALTERA_PCIE_$(BOARD)),1)\n\tcd $(PROJECTDIR); BUILDCACHE_CACHEDIR=$(BUILDCACHE_CACHEDIR) $(BUILDCACHE) $(QUARTUS_SH) -t $(shell cd $(CONNECTALDIR); /bin/pwd)/scripts/connectal-synth-pcie.tcl\nendif\n\n# Synthesize Altera Ethernet Core\nifeq ($(NEED_ALTERA_ETH_$(BOARD)), 1)\n\tcd $(PROJECTDIR); BUILDCACHE_CACHEDIR=$(BUILDCACHE_CACHEDIR) $(BUILDCACHE) $(QUARTUS_SH) -t $(shell cd $(CONNECTALDIR); /bin/pwd)/scripts/connectal-synth-eth.tcl\nendif\nendif\n\n"
  },
  {
    "path": "Makefile.version",
    "content": "VERSION=22.05.23b\n"
  },
  {
    "path": "README.md",
    "content": "Connectal\n====\n\n\nConnectal provides a hardware-software interface for applications split\nbetween user mode code and custom hardware in an FPGA.  Portal can\nautomatically build the software and hardware glue for a message based\ninterface and also provides for configuring and using shared memory\nbetween applications and hardware. Communications between hardware and\nsoftware are provided by a bidirectional flow of events and regions of\nmemory shared between hardware and software.  Events from software to\nhardware are called requests and events from hardware to software are\ncalled indications, but in fact they are symmetric.\n\nA logical request/indication pair is referred to as a portal\".  An\napplication can make use of multiple portals, which may be specified\nindependently. A portal is specified by a BSV interface declaration,\nfrom which `connectalgen` generates BSV and C++ wrappers and\nproxies.\n\nConnectal has a mailing list:\n   https://groups.google.com/forum/#!forum/connectal\n\nSee the documentation for more details:\n   http://www.connectal.org/doc/current/ref/\n\nSupported Platforms\n-------------------\n\nConnectal supports Android on Zynq platforms, including zedboard and zc702.\n\nConnectal supports Linux on x86 with PCIe-attached Virtex and Kintex boards (vc707, kc705).\n\nConnectal supports bluesim as a simulated hardware platform. \n\n\nInstallation\n------------\n\n1. Install the Bluespec compiler. Connectal is known to work with 2014.07.A and 2015.05.beta1\n\nInstall the bluespec compiler. Make sure the BLUESPECDIR environment\nvariable is set appropriately:\n\n    export BLUESPECDIR=~/bluespec/Bluespec-2014.07.A/lib\n\n2. Install Vivado 2015.2 or 2015.4\n\n3. Install Connectal\n\n       sudo add-apt-repository -y ppa:jamey-hicks/connectal\n       sudo apt-get update\n       sudo apt-get -y install connectal\n\nBuilding from Source\n--------------------\n\n1. Checkout out the following from github:\n\n       git clone git://github.com/cambridgehackers/connectal\n\n   If you are generating code for an FPGA, check out fpgamake:\n\n       git clone git://github.com/cambridgehackers/fpgamake\n\n   It appears that this requires buildcache to be checked out also:\n\n       git clone git://github.com/cambridgehackers/buildcache\n\n   Add `USE_BUILDCACHE=1` to your calls to make to enable it to cache, otherwise it will rerun all compilation steps.\n\n2. Install connectal dependences. This installs ubuntu packages used by connectal or during compilation:\n\n       cd connectal;\n       sudo make install-dependences\n\n3. If you are using an FPGA attached to your machine, install the drivers:\n\n       make all\n       sudo make install\n\n\nPreparation for Zynq\n--------------------\n\n0. Get [http://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/vivado-design-tools/2015-2.html](Vivado 2015.2)\n\n\n1. Download the Android Native Development Kit (NDK) from: \n     http://developer.android.com/tools/sdk/ndk/index.html\n     (actual file might be:\n         http://dl.google.com/android/ndk/android-ndk-r10e-linux-x86_64.tar.bz2\n     )\n\n   Connectal uses NDK to compile code to run on Zynq platforms.\n\n   Add the NDK to your PATH.\n\n       URL=http://dl.google.com/android/ndk/android-ndk-r10e-linux-x86_64.tar.bz2\n       curl -O `basename $URL` $URL\n       tar -jxvf `basename $URL`\n       PATH=$PATH:/scratch/android-ndk-r10e/\n\n2. Download and install ADB from the Android Development Tools.\n\n   The Android Debug Bridge (adb) is packaged in platform-tools. Connectal\n   uses [adb](http://developer.android.com/tools/help/adb.html) to\n   transfer files to and from the Zedboard over ethernet and to run\n   commands on the Zedboard.\n\n   User your browser to accept the conditions and download the SDK installation tarball:\n\n       http://dl.google.com/android/android-sdk_r22.6.2-linux.tgz\n\n   Unpack the installation tarball:\n\n       tar -zxvf android-sdk_r22.6.2-linux.tgz\n\n   Run the `android` tool to install SDK components\n\n       ./android-sdk-linux/tools/android\n\n   Deselect all components except for \"Android SDK Platform-Tools\" [(screenshot)](doc/android-sdk-screenshots/android-sdk-manager.png) and\n   then click the \"Install ... package\" button to install [(screenshot)](doc/android-sdk-screenshots/android-sdk-license.png) and then\n   accept the license. [(screenshot)](doc/android-sdk-screenshots/android-sdk-manager-log.png)\n\n   Add adb to your path:\n\n       PATH=$PATH:$PWD/android-sdk-linux/platform-tools\n\n3. Create/obtain a boot.bin and SD card image for your board\n\nFollow the instructions at https://github.com/cambridgehackers/zynq-boot\n\nCopy the files to the SD card, eject the card from the PC, and plug it into the zedboard/zc702/zc706 and boot.\n\n\nPreparation for Kintex and Virtex boards\n----------------------------------------\n\n0. Get [http://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/vivado-design-tools/2013-2.html](Vivado 2013.2)\n\n1. Install the drivers\n\n       make\n       sudo make install\n       sudo modprobe portalmem\n\n2. Get fpgajtag\n\n       git clone git://github.com/cambridgehackers/fpgajtag\n       cd fpgajtag\n       make all && sudo make install\n\nExamples\n--------\n\nGenerally cd to the project directory, then type\n\n    cd examples/examplename\n    make build.<target>\n    make run.<target>\n\nwhere target is\n\nCommand suffix | Function\n--------------|----------\nbluesim | compile for simulation\nzedboard| compile for zedboard\nzybo| compile for zybo\nzc702| compile for zc702 board\nzc706| compile for zc706 board\nkc705| compile for kc705 board\nvc707| compile for vc707 board\nvc709| compile for vc709 board\nnfsume| compile for NetFPGA-SUME board\n\nTo turn on more verbosity for debugging when running make,\nadd V=1 to command line, as\n\n    make examples/examplename.<something> V=1\nor\n\n    V=1 make examples/examplename.<something>\n\nTo run the example on a machine different than the build machine, use RUNPARAM=hostname-or-addr:\n\n    make RUNPARAM=zedtest run.zedboard\n    make RUNPARAM=192.168.1.123 run.vc707\n\n### Bitstream Packaging\n\n\nThe FPGA bitstream is included in the application executable, and the\nFPGA is automatically programmed when the application is run:\n\n    cd examples/echo\n    make build.vc707\n    ./vc707/bin/ubuntu.exe\n\nWe are running Android on the Zynq devices and so the application\nexecutable is called android.exe.\n\n### Echo Example\n\n\n    ## this has only been tested with the Vivado 2013.2 release\n    . Xilinx/Vivado/2013.2/settings64.sh\n\n    make -C examples/echo build..zedboard\nor\n\n    make -C examples/echo build.zc702\nor\n\n    make -C examples/echo build.kc705\nor\n\n    make -C examples/echo build.vc707\n\nTo run on a zedboard with IP address aa.bb.cc.dd:\n\n    RUNPARAM=aa.bb.cc.dd make -C examples/echo run.zedboard\n\n### Memcpy Example\n\n    make -C examples/memcpy build.vc707\n\n\n[![Analytics](https://ga-beacon.appspot.com/UA-15845210-3/connectal/README.md)](https://github.com/igrigorik/ga-beacon)\n"
  },
  {
    "path": "boardinfo/ac701.json",
    "content": "{\n    \"options\": {\n        \"bsvdefines\" : [\"XILINX=1\", \"Artix7\",  \"PCIE\", \"PCIE1\", \"PcieHostInterface\", \"PhysAddrWidth=40\", \"PcieLanes=4\",\n\t\t       \t\"CONNECTAL_BITS_DEPENDENCES=hw/mkTop.bit\", \"CONNECTAL_RUN_SCRIPT=$(CONNECTALDIR)/scripts/run.pcietest\"],\n        \"os\" : \"ubuntu\",\n        \"partname\" : \"xc7a200tfbg676-2\",\n        \"need_pcie\" : \"x7_gen1x8\",\n        \"TOP\" : \"PcieTop\",\n        \"constraints\": [],\n        \"implconstraints\": [\"constraints/xilinx/ac701.xdc\", \"constraints/xilinx/pcie-clocks.xdc\"],\n        \"runscript\" : \"run.pcietest\",\n        \"CONNECTALFLAGS\" : [\"--mainclockperiod=8\", \"--derivedclockperiod=4\", \"--pcieclockperiod=8\"],\n        \"rewireclockstring\" : \"\"\n    },\n    \"uart\": {\n\t\t\"d_in\": {\n\t\t\t\"PACKAGE_PIN\": \"T19\",\n\t\t\t\"IOSTANDARD\": \"LVCMOS25\",\n\t\t\t\"PIO_DIRECTION\": \"INPUT\"\n\t\t},\n\t\t\"d_out\": {\n\t\t\t\"PACKAGE_PIN\": \"U19\",\n\t\t\t\"IOSTANDARD\": \"LVCMOS25\",\n\t\t\t\"PIO_DIRECTION\": \"OUTPUT\"\n\t\t},\n\t\t\"rts\": {\n\t\t\t\"PACKAGE_PIN\": \"V19\",\n\t\t\t\"IOSTANDARD\": \"LVCMOS25\",\n\t\t\t\"PIO_DIRECTION\": \"INPUT\"\n\t\t},\n\t\t\"cts\": {\n\t\t\t\"PACKAGE_PIN\": \"W19\",\n\t\t\t\"IOSTANDARD\": \"LVCMOS25\",\n\t\t\t\"PIO_DIRECTION\": \"OUTPUT\"\n\t\t}\n    },\n    \"sdio\": {\n        \"dat0\": {\n            \"PACKAGE_PIN\": \"P19\",\n            \"IOSTANDARD\": \"LVCMOS25\",\n            \"PIO_DIRECTION\": \"BIDIR\"\n        },\n        \"dat1\": {\n            \"PACKAGE_PIN\": \"N19\",\n            \"IOSTANDARD\": \"LVCMOS25\",\n            \"PIO_DIRECTION\": \"BIDIR\"\n        },\n        \"dat2\": {\n            \"PACKAGE_PIN\": \"P23\",\n            \"IOSTANDARD\": \"LVCMOS25\",\n            \"PIO_DIRECTION\": \"BIDIR\"\n        },\n        \"cd_dat3\": {\n            \"PACKAGE_PIN\": \"P21\",\n            \"IOSTANDARD\": \"LVCMOS25\",\n            \"PIO_DIRECTION\": \"BIDIR\"\n        },\n        \"clk\": {\n            \"PACKAGE_PIN\": \"N24\",\n            \"IOSTANDARD\": \"LVCMOS25\",\n            \"PIO_DIRECTION\": \"OUTPUT\"\n        },\n        \"cmd\": {\n            \"PACKAGE_PIN\": \"N23\",\n            \"IOSTANDARD\": \"LVCMOS25\",\n            \"PIO_DIRECTION\": \"BIDIR\"\n        },\n        \"sddet\": {\n            \"PACKAGE_PIN\": \"P24\",\n            \"IOSTANDARD\": \"LVCMOS25\",\n            \"PIO_DIRECTION\": \"INPUT\"\n        },\n        \"sdwp\": {\n            \"PACKAGE_PIN\": \"R20\",\n            \"IOSTANDARD\": \"LVCMOS25\",\n            \"PIO_DIRECTION\": \"INPUT\"\n        }\n    },\n    \"fmc\": {\n    }\n}\n"
  },
  {
    "path": "boardinfo/ac701_untethered.json",
    "content": "{\n    \"options\": {\n        \"bsvdefines\" : [\"XILINX=1\", \"Artix7\", \"PhysAddrWidth=40\", \"PcieLanes=4\", \"UNTETHERED=1\",\n\t\t       \t\"CONNECTAL_BITS_DEPENDENCES=hw/mkTop.bit\", \"CONNECTAL_RUN_SCRIPT=$(CONNECTALDIR)/scripts/run.pcietest\"],\n        \"os\" : \"ubuntu\",\n        \"partname\" : \"xc7a200tfbg676-2\",\n        \"TOP\" : \"UntetheredTop\",\n        \"constraints\": [],\n        \"implconstraints\": [\"constraints/xilinx/ac701.xdc\", \"constraints/xilinx/pcie-clocks.xdc\"],\n        \"runscript\" : \"run.pcietest\",\n        \"CONNECTALFLAGS\" : [\"--mainclockperiod=8\", \"--derivedclockperiod=4\", \"--pcieclockperiod=8\"],\n        \"rewireclockstring\" : \"\"\n    },\n    \"uart\": {\n\t\t\"d_in\": {\n\t\t\t\"PACKAGE_PIN\": \"T19\",\n\t\t\t\"IOSTANDARD\": \"LVCMOS25\",\n\t\t\t\"PIO_DIRECTION\": \"INPUT\"\n\t\t},\n\t\t\"d_out\": {\n\t\t\t\"PACKAGE_PIN\": \"U19\",\n\t\t\t\"IOSTANDARD\": \"LVCMOS25\",\n\t\t\t\"PIO_DIRECTION\": \"OUTPUT\"\n\t\t},\n\t\t\"rts\": {\n\t\t\t\"PACKAGE_PIN\": \"V19\",\n\t\t\t\"IOSTANDARD\": \"LVCMOS25\",\n\t\t\t\"PIO_DIRECTION\": \"INPUT\"\n\t\t},\n\t\t\"cts\": {\n\t\t\t\"PACKAGE_PIN\": \"W19\",\n\t\t\t\"IOSTANDARD\": \"LVCMOS25\",\n\t\t\t\"PIO_DIRECTION\": \"OUTPUT\"\n\t\t}\n    },\n    \"sdio\": {\n        \"dat0\": {\n            \"PACKAGE_PIN\": \"P19\",\n            \"IOSTANDARD\": \"LVCMOS25\",\n            \"PIO_DIRECTION\": \"BIDIR\"\n        },\n        \"dat1\": {\n            \"PACKAGE_PIN\": \"N19\",\n            \"IOSTANDARD\": \"LVCMOS25\",\n            \"PIO_DIRECTION\": \"BIDIR\"\n        },\n        \"dat2\": {\n            \"PACKAGE_PIN\": \"P23\",\n            \"IOSTANDARD\": \"LVCMOS25\",\n            \"PIO_DIRECTION\": \"BIDIR\"\n        },\n        \"cd_dat3\": {\n            \"PACKAGE_PIN\": \"P21\",\n            \"IOSTANDARD\": \"LVCMOS25\",\n            \"PIO_DIRECTION\": \"BIDIR\"\n        },\n        \"clk\": {\n            \"PACKAGE_PIN\": \"N24\",\n            \"IOSTANDARD\": \"LVCMOS25\",\n            \"PIO_DIRECTION\": \"OUTPUT\"\n        },\n        \"cmd\": {\n            \"PACKAGE_PIN\": \"N23\",\n            \"IOSTANDARD\": \"LVCMOS25\",\n            \"PIO_DIRECTION\": \"BIDIR\"\n        },\n        \"sddet\": {\n            \"PACKAGE_PIN\": \"P24\",\n            \"IOSTANDARD\": \"LVCMOS25\",\n            \"PIO_DIRECTION\": \"INPUT\"\n        },\n        \"sdwp\": {\n            \"PACKAGE_PIN\": \"R20\",\n            \"IOSTANDARD\": \"LVCMOS25\",\n            \"PIO_DIRECTION\": \"INPUT\"\n        }\n    },\n    \"fmc\": {\n    },\n    \"pins\": {\n\t\"cpu_reset\": {\n\t    \"PACKAGE_PIN\": \"U4\",\n\t    \"IOSTANDARD\": \"LVCMOS15\",\n\t    \"PIO_DIRECTION\": \"INPUT\"\n\t}\n    }\t\n}\n"
  },
  {
    "path": "boardinfo/ac701g2.json",
    "content": "{\n    \"options\": {\n        \"bsvdefines\" : [\"XILINX=1\", \"Artix7\",  \"PCIE\", \"PCIE2\", \"PcieHostInterface\", \"PhysAddrWidth=40\", \"PcieLanes=4\",\n\t\t       \t\"CONNECTAL_BITS_DEPENDENCES=hw/mkTop.bit\", \"CONNECTAL_RUN_SCRIPT=$(CONNECTALDIR)/scripts/run.pcietest\"],\n        \"os\" : \"ubuntu\",\n        \"partname\" : \"xc7a200tfbg676-2\",\n        \"need_pcie\" : \"x7_gen2x8\",\n        \"TOP\" : \"PcieTop\",\n        \"constraints\": [\"constraints/xilinx/ac701.xdc\", \"constraints/xilinx/pcie-clocks.xdc\"],\n        \"implconstraints\": [\"constraints/xilinx/ac701.xdc\", \"constraints/xilinx/pcie-clocks.xdc\"],\n        \"runscript\" : \"run.pcietest\",\n        \"CONNECTALFLAGS\" : [\"--mainclockperiod=4\", \"--derivedclockperiod=4\", \"--pcieclockperiod=4\"],\n        \"rewireclockstring\" : \"\"\n    },\n    \"fmc\": {\n    }\n}\n"
  },
  {
    "path": "boardinfo/asic.json",
    "content": "{\n    \"options\": {\n        \"os\" : \"ubuntu\",\n        \"partname\" : \"asic\",\n\t\"rewireclockstring\" : \"\",\n        \"TOP\" : \"AsicTop\",\n\t\"bsvdefines\": [\"ASIC\", \"CnocTop\", \"XsimHostInterface\", \"PhysAddrWidth=32\"],\n        \"CONNECTALFLAGS\" : [\"--mainclockperiod=20\", \"--derivedclockperiod=10\"],\n        \"need_pcie\" : \"unused\"\n    }\n}\n\n\n"
  },
  {
    "path": "boardinfo/awsf1.json",
    "content": "{\n    \"options\": {\n        \"bsvdefines\" : [\"XILINX=1\", \"VirtexUltrascale\", \"PhysAddrWidth=40\", \"DataBusWidth=512\", \"XsimHostInterface\", \"AWSF1=1\",\n\t\t\t\"MemTagSize=16\", \"MemServerTags=8\",\n\t\t\t\"DEFAULT_NOPROGRAM=1\",\n\t\t       \t\"CONNECTAL_BITS_DEPENDENCES=build/checkpoints/to_aws/mkTop.SH_CL_routed.dcp\", \"CONNECTAL_RUN_SCRIPT=$(CONNECTALDIR)/scripts/run.aws\"],\n        \"os\" : \"ubuntu\",\n        \"partname\" : \"xcvu9p-flgb2104-2-i\",\n        \"TOP\" : \"AwsF1Top\",\n        \"constraints\": [\"constraints/xilinx/awsf1.xdc\"],\n        \"implconstraints\": [\"constraints/xilinx/awsf1.xdc\"],\n        \"runscript\" : \"run.pcietest\",\n        \"CONNECTALFLAGS\" : [\"--mainclockperiod=8\", \"--derivedclockperiod=8\", \"--pcieclockperiod=8\"],\n        \"rewireclockstring\" : \"\"\n    },\n    \"pins\": {\n\t}\n}\n\n\n"
  },
  {
    "path": "boardinfo/bluesim.json",
    "content": "{\n    \"options\": {\n        \"os\" : \"ubuntu\",\n        \"partname\" : \"xc7z020clg484-1\",\n        \"rewireclockstring\" : \"tclzynqrewireclock\",\n        \"TOP\" : \"XsimTop\",\n\t\"bsvdefines\": [\"CnocTop\", \"XsimHostInterface\", \"PhysAddrWidth=40\", \"SIMULATION\",\n\t\t       \t\"CONNECTAL_BITS_DEPENDENCES=bsim\"],\n        \"CONNECTALFLAGS\" : [\"--mainclockperiod=20\", \"--derivedclockperiod=10\"],\n        \"need_pcie\" : \"unused\"\n    },\n    \"fmc\": {\n    \"CLK0_M2C_n\": { \"LOC\": \"ZZZ\", \"IOSTANDARD\": \"YY\" },\n    \"CLK0_M2C_p\": { \"LOC\": \"ZZZ\", \"IOSTANDARD\": \"YY\" },\n    \"LA00_n_CC\": { \"LOC\": \"ZZZ\", \"IOSTANDARD\": \"YY\" },\n    \"LA00_p_CC\": { \"LOC\": \"ZZZ\", \"IOSTANDARD\": \"YY\" },\n    \"LA01_n_CC\": { \"LOC\": \"ZZZ\", \"IOSTANDARD\": \"YY\" },\n    \"LA05_n\": { \"LOC\": \"ZZZ\", \"IOSTANDARD\": \"YY\" },\n    \"LA05_p\": { \"LOC\": \"ZZZ\", \"IOSTANDARD\": \"YY\" },\n    \"LA07_n\": { \"LOC\": \"ZZZ\", \"IOSTANDARD\": \"YY\" },\n    \"LA07_p\": { \"LOC\": \"ZZZ\", \"IOSTANDARD\": \"YY\" },\n    \"LA08_n\": { \"LOC\": \"ZZZ\", \"IOSTANDARD\": \"YY\" },\n    \"LA08_p\": { \"LOC\": \"ZZZ\", \"IOSTANDARD\": \"YY\" },\n    \"LA09_n\": { \"LOC\": \"ZZZ\", \"IOSTANDARD\": \"YY\" },\n    \"LA09_p\": { \"LOC\": \"ZZZ\", \"IOSTANDARD\": \"YY\" },\n    \"LA10_n\": { \"LOC\": \"ZZZ\", \"IOSTANDARD\": \"YY\" },\n    \"LA10_p\": { \"LOC\": \"ZZZ\", \"IOSTANDARD\": \"YY\" },\n    \"LA11_n\": { \"LOC\": \"ZZZ\", \"IOSTANDARD\": \"YY\" },\n    \"LA11_p\": { \"LOC\": \"ZZZ\", \"IOSTANDARD\": \"YY\" },\n    \"LA12_n\": { \"LOC\": \"ZZZ\", \"IOSTANDARD\": \"YY\" },\n    \"LA12_p\": { \"LOC\": \"ZZZ\", \"IOSTANDARD\": \"YY\" },\n    \"LA13_n\": { \"LOC\": \"ZZZ\", \"IOSTANDARD\": \"YY\" },\n    \"LA13_p\": { \"LOC\": \"ZZZ\", \"IOSTANDARD\": \"YY\" },\n    \"LA14_n\": { \"LOC\": \"ZZZ\", \"IOSTANDARD\": \"YY\" },\n    \"LA14_p\": { \"LOC\": \"ZZZ\", \"IOSTANDARD\": \"YY\" },\n    \"LA15_n\": { \"LOC\": \"ZZZ\", \"IOSTANDARD\": \"YY\" },\n    \"LA15_p\": { \"LOC\": \"ZZZ\", \"IOSTANDARD\": \"YY\" },\n    \"LA16_n\": { \"LOC\": \"ZZZ\", \"IOSTANDARD\": \"YY\" },\n    \"LA16_p\": { \"LOC\": \"ZZZ\", \"IOSTANDARD\": \"YY\" }\n    },\n    \"pins\": {\n    \"GPIO_sw_left\":   {\"PACKAGE_PIN\": \"XXXX\",\"IOSTANDARD\": \"YYYY\",\"slew\": \"ZZZZ\",\"PIO_DIRECTION\": \"INPUT\"},\n    \"GPIO_sw_center\": {\"PACKAGE_PIN\": \"XXXX\",\"IOSTANDARD\": \"YYYY\",\"slew\": \"ZZZZ\",\"PIO_DIRECTION\": \"INPUT\"},\n    \"GPIO_sw_right\":  {\"PACKAGE_PIN\": \"XXXX\",\"IOSTANDARD\": \"YYYY\",\"slew\": \"ZZZZ\",\"PIO_DIRECTION\": \"INPUT\"},\n    \"GPIO_sw_down\":   {\"PACKAGE_PIN\": \"XXXX\",\"IOSTANDARD\": \"YYYY\",\"slew\": \"ZZZZ\",\"PIO_DIRECTION\": \"INPUT\"},\n    \"GPIO_sw_up\":     {\"PACKAGE_PIN\": \"XXXX\",\"IOSTANDARD\": \"YYYY\",\"slew\": \"ZZZZ\",\"PIO_DIRECTION\": \"INPUT\"}\n    },\n    \"pmoda\" : {\n        \"J1\" : { \"LOC\" : \"XX\", \"IOSTANDARD\" : \"YY\"},\n        \"J2\" : { \"LOC\" : \"XX\", \"IOSTANDARD\" : \"YY\"},\n        \"J3\" : { \"LOC\" : \"XX\", \"IOSTANDARD\" : \"YY\"},\n        \"J4\" : { \"LOC\" : \"XX\", \"IOSTANDARD\" : \"YY\"},\n        \"J7\" : { \"LOC\" : \"XX\", \"IOSTANDARD\" : \"YY\"},\n        \"J8\" : { \"LOC\" : \"XX\", \"IOSTANDARD\" : \"YY\"},\n        \"J9\" : { \"LOC\" : \"XX\", \"IOSTANDARD\" : \"YY\"},\n        \"J10\" : { \"LOC\" : \"XX\", \"IOSTANDARD\" : \"YY\"}\n    },\n    \"pmodb\" : {\n        \"J1\" : { \"LOC\" : \"XX\", \"IOSTANDARD\" : \"YY\"},\n        \"J2\" : { \"LOC\" : \"XX\", \"IOSTANDARD\" : \"YY\"},\n        \"J3\" : { \"LOC\" : \"XX\", \"IOSTANDARD\" : \"YY\"},\n        \"J4\" : { \"LOC\" : \"XX\", \"IOSTANDARD\" : \"YY\"},\n        \"J7\" : { \"LOC\" : \"XX\", \"IOSTANDARD\" : \"YY\"},\n        \"J8\" : { \"LOC\" : \"XX\", \"IOSTANDARD\" : \"YY\"},\n        \"J9\" : { \"LOC\" : \"XX\", \"IOSTANDARD\" : \"YY\"},\n        \"J10\" : { \"LOC\" : \"XX\", \"IOSTANDARD\" : \"YY\"}\n    },\n    \"pmodc\" : {\n        \"J1\" : { \"LOC\" : \"XX\", \"IOSTANDARD\" : \"YY\"},\n        \"J2\" : { \"LOC\" : \"XX\", \"IOSTANDARD\" : \"YY\"},\n        \"J3\" : { \"LOC\" : \"XX\", \"IOSTANDARD\" : \"YY\"},\n        \"J4\" : { \"LOC\" : \"XX\", \"IOSTANDARD\" : \"YY\"},\n        \"J7\" : { \"LOC\" : \"XX\", \"IOSTANDARD\" : \"YY\"},\n        \"J8\" : { \"LOC\" : \"XX\", \"IOSTANDARD\" : \"YY\"},\n        \"J9\" : { \"LOC\" : \"XX\", \"IOSTANDARD\" : \"YY\"},\n        \"J10\" : { \"LOC\" : \"XX\", \"IOSTANDARD\" : \"YY\"}\n    },\n    \"pmodd\" : {\n        \"J1\" : { \"LOC\" : \"XX\", \"IOSTANDARD\" : \"YY\"},\n        \"J2\" : { \"LOC\" : \"XX\", \"IOSTANDARD\" : \"YY\"},\n        \"J3\" : { \"LOC\" : \"XX\", \"IOSTANDARD\" : \"YY\"},\n        \"J4\" : { \"LOC\" : \"XX\", \"IOSTANDARD\" : \"YY\"},\n        \"J7\" : { \"LOC\" : \"XX\", \"IOSTANDARD\" : \"YY\"},\n        \"J8\" : { \"LOC\" : \"XX\", \"IOSTANDARD\" : \"YY\"},\n        \"J9\" : { \"LOC\" : \"XX\", \"IOSTANDARD\" : \"YY\"},\n        \"J10\" : { \"LOC\" : \"XX\", \"IOSTANDARD\" : \"YY\"}\n    },\n    \"pmode\" : {\n        \"J1\" : { \"LOC\" : \"XX\", \"IOSTANDARD\" : \"YY\"},\n        \"J2\" : { \"LOC\" : \"XX\", \"IOSTANDARD\" : \"YY\"},\n        \"J3\" : { \"LOC\" : \"XX\", \"IOSTANDARD\" : \"YY\"},\n        \"J4\" : { \"LOC\" : \"XX\", \"IOSTANDARD\" : \"YY\"},\n        \"J7\" : { \"LOC\" : \"XX\", \"IOSTANDARD\" : \"YY\"},\n        \"J8\" : { \"LOC\" : \"XX\", \"IOSTANDARD\" : \"YY\"},\n        \"J9\" : { \"LOC\" : \"XX\", \"IOSTANDARD\" : \"YY\"},\n        \"J10\" : { \"LOC\" : \"XX\", \"IOSTANDARD\" : \"YY\"}\n    },\n    \"leds\" : {\n    \t\"L0\" : {\n\t     \"LOC\" : \"XX\",\n             \"IOSTANDARD\" : \"YY\",\n\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t     },\n    \t\"L1\" : {\n\t     \"LOC\" : \"XX\",\n             \"IOSTANDARD\" : \"YY\",\n\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t     },\n    \t\"L2\" : {\n\t     \"LOC\" : \"XX\",\n             \"IOSTANDARD\" : \"YY\",\n\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t     },\n    \t\"L3\" : {\n\t     \"LOC\" : \"XX\",\n             \"IOSTANDARD\" : \"YY\",\n\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t     },\n    \t\"L4\" : {\n\t     \"LOC\" : \"XX\",\n             \"IOSTANDARD\" : \"YY\",\n\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t     },\n    \t\"L5\" : {\n\t     \"LOC\" : \"XX\",\n             \"IOSTANDARD\" : \"YY\",\n\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t     },\n    \t\"L6\" : {\n\t     \"LOC\" : \"XX\",\n             \"IOSTANDARD\" : \"YY\",\n\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t     },\n    \t\"L7\" : {\n\t     \"LOC\" : \"XX\",\n             \"IOSTANDARD\" : \"YY\",\n\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t     }\n    }\n}\n\n\n"
  },
  {
    "path": "boardinfo/cvc.json",
    "content": "{\n    \"options\": {\n        \"os\" : \"ubuntu\",\n        \"partname\" : \"xc7z020clg484-1\",\n        \"rewireclockstring\" : \"tclzynqrewireclock\",\n        \"TOP\" : \"XsimTop\",\n\t\"bsvdefines\": [\"CnocTop\", \"XsimHostInterface\", \"PhysAddrWidth=40\", \"SIMULATION\", \"SVDPI\",\n\t\t       \t\"CONNECTAL_BITS_DEPENDENCES=cvcsim\"],\n        \"CONNECTALFLAGS\" : [\"--mainclockperiod=20\", \"--derivedclockperiod=10\"],\n        \"need_pcie\" : \"unused\"\n    }\n}\n\n\n"
  },
  {
    "path": "boardinfo/de5.json",
    "content": "{\n    \"options\": {\n        \"bsvdefines\" : [\"ALTERA=1\", \"StratixV\", \"PCIE\", \"PCIE_NO_BSCAN\", \"PcieHostInterface\", \"PhysAddrWidth=40\", \"NUMBER_OF_LEDS=4\", \"NUMBER_OF_10G_PORTS=4\", \"SYNTHESIS\", \"PcieLanes=8\", \"DEFAULT_NOPROGRAM=1\",\n\t\t       \t\"CONNECTAL_BITS_DEPENDENCES=hw/mkTop.bit\", \"CONNECTAL_RUN_SCRIPT=$(CONNECTALDIR)/scripts/run.pcietest.altera\"],\n        \"os\" : \"ubuntu\",\n        \"partname\" : \"5SGXEA7N2F45C2\",\n        \"need_pcie\" : \"s5_gen2x8\",\n        \"TOP\" : \"PcieTop\",\n        \"constraints\": [\"constraints/altera/de5.sdc\"],\n        \"runscript\" : \"run.pcietest.altera\",\n        \"CONNECTALFLAGS\" : [\"--mainclockperiod=8\", \"--derivedclockperiod=4\", \"--pcieclockperiod=8\"],\n        \"rewireclockstring\" : \"\"\n    },\n    \"BUTTON\": {\n        \"BUTTON[0]\": {\n            \"PIO_DIRECTION\": \"INPUT\",\n            \"IO_STANDARD\": \"2.5 V\", \n            \"LOC\": \"PIN_AK15\"\n        }, \n        \"BUTTON[1]\": {\n            \"PIO_DIRECTION\": \"INPUT\",\n            \"IO_STANDARD\": \"2.5 V\", \n            \"LOC\": \"PIN_AK14\"\n        }, \n        \"BUTTON[2]\": {\n            \"PIO_DIRECTION\": \"INPUT\",\n            \"IO_STANDARD\": \"2.5 V\", \n            \"LOC\": \"PIN_AL14\"\n        }, \n        \"BUTTON[3]\": {\n            \"PIO_DIRECTION\": \"INPUT\",\n            \"IO_STANDARD\": \"2.5 V\", \n            \"LOC\": \"PIN_AL15\"\n        }\n    }, \n    \"I2C\": {\n        \"CLOCK_SCL\": {\n            \"PIO_DIRECTION\": \"INPUT\",\n            \"IO_STANDARD\": \"2.5 V\", \n            \"LOC\": \"PIN_AE15\"\n        }, \n        \"CLOCK_SDA\": {\n            \"PIO_DIRECTION\": \"BIDIR\",\n            \"IO_STANDARD\": \"2.5 V\", \n            \"LOC\": \"PIN_AE16\"\n        }\n    }, \n    \"CPU\": {\n        \"CPU_RESET_n\": {\n            \"IO_STANDARD\": \"2.5 V\", \n            \"LOC\": \"PIN_BC37\"\n        }\n    }, \n    \"DDR3A\": {\n        \"DDR3A_A[0]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_M39\"\n        }, \n        \"DDR3A_A[10]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_M38\"\n        }, \n        \"DDR3A_A[11]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_C37\"\n        }, \n        \"DDR3A_A[12]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_K36\"\n        }, \n        \"DDR3A_A[13]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_M33\"\n        }, \n        \"DDR3A_A[14]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_K34\"\n        }, \n        \"DDR3A_A[15]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_B38\"\n        }, \n        \"DDR3A_A[1]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_L35\"\n        }, \n        \"DDR3A_A[2]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_N38\"\n        }, \n        \"DDR3A_A[3]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_L36\"\n        }, \n        \"DDR3A_A[4]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_H36\"\n        }, \n        \"DDR3A_A[5]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_K29\"\n        }, \n        \"DDR3A_A[6]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_D37\"\n        }, \n        \"DDR3A_A[7]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_K35\"\n        }, \n        \"DDR3A_A[8]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_K32\"\n        }, \n        \"DDR3A_A[9]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_K37\"\n        }, \n        \"DDR3A_BA[0]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_M37\"\n        }, \n        \"DDR3A_BA[1]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_P39\"\n        }, \n        \"DDR3A_BA[2]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_J36\"\n        }, \n        \"DDR3A_CAS_n\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_M36\"\n        }, \n        \"DDR3A_CKE[0]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_E36\"\n        }, \n        \"DDR3A_CKE[1]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_B35\"\n        }, \n        \"DDR3A_CK[0]\": {\n            \"IO_STANDARD\": \"DIFFERENTIAL 1.5-V SSTL CLASS I\", \n            \"LOC\": \"PIN_G37\"\n        }, \n        \"DDR3A_CK[1]\": {\n            \"IO_STANDARD\": \"DIFFERENTIAL 1.5-V SSTL CLASS I\", \n            \"LOC\": \"PIN_J37\"\n        }, \n        \"DDR3A_CK_n[0]\": {\n            \"IO_STANDARD\": \"DIFFERENTIAL 1.5-V SSTL CLASS I\", \n            \"LOC\": \"PIN_F36\"\n        }, \n        \"DDR3A_CK_n[1]\": {\n            \"IO_STANDARD\": \"DIFFERENTIAL 1.5-V SSTL CLASS I\", \n            \"LOC\": \"PIN_H37\"\n        }, \n        \"DDR3A_CS_n[0]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_P36\"\n        }, \n        \"DDR3A_CS_n[1]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_R28\"\n        }, \n        \"DDR3A_DM[0]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_C36\"\n        }, \n        \"DDR3A_DM[1]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_E32\"\n        }, \n        \"DDR3A_DM[2]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_H34\"\n        }, \n        \"DDR3A_DM[3]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_L32\"\n        }, \n        \"DDR3A_DM[4]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_N32\"\n        }, \n        \"DDR3A_DM[5]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_W32\"\n        }, \n        \"DDR3A_DM[6]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_K30\"\n        }, \n        \"DDR3A_DM[7]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_T28\"\n        }, \n        \"DDR3A_DQS[0]\": {\n            \"IO_STANDARD\": \"DIFFERENTIAL 1.5-V SSTL CLASS I\", \n            \"LOC\": \"PIN_C34\"\n        }, \n        \"DDR3A_DQS[1]\": {\n            \"IO_STANDARD\": \"DIFFERENTIAL 1.5-V SSTL CLASS I\", \n            \"LOC\": \"PIN_C31\"\n        }, \n        \"DDR3A_DQS[2]\": {\n            \"IO_STANDARD\": \"DIFFERENTIAL 1.5-V SSTL CLASS I\", \n            \"LOC\": \"PIN_H35\"\n        }, \n        \"DDR3A_DQS[3]\": {\n            \"IO_STANDARD\": \"DIFFERENTIAL 1.5-V SSTL CLASS I\", \n            \"LOC\": \"PIN_U35\"\n        }, \n        \"DDR3A_DQS[4]\": {\n            \"IO_STANDARD\": \"DIFFERENTIAL 1.5-V SSTL CLASS I\", \n            \"LOC\": \"PIN_T33\"\n        }, \n        \"DDR3A_DQS[5]\": {\n            \"IO_STANDARD\": \"DIFFERENTIAL 1.5-V SSTL CLASS I\", \n            \"LOC\": \"PIN_T30\"\n        }, \n        \"DDR3A_DQS[6]\": {\n            \"IO_STANDARD\": \"DIFFERENTIAL 1.5-V SSTL CLASS I\", \n            \"LOC\": \"PIN_J30\"\n        }, \n        \"DDR3A_DQS[7]\": {\n            \"IO_STANDARD\": \"DIFFERENTIAL 1.5-V SSTL CLASS I\", \n            \"LOC\": \"PIN_Y30\"\n        }, \n        \"DDR3A_DQS_n[0]\": {\n            \"IO_STANDARD\": \"DIFFERENTIAL 1.5-V SSTL CLASS I\", \n            \"LOC\": \"PIN_B34\"\n        }, \n        \"DDR3A_DQS_n[1]\": {\n            \"IO_STANDARD\": \"DIFFERENTIAL 1.5-V SSTL CLASS I\", \n            \"LOC\": \"PIN_B31\"\n        }, \n        \"DDR3A_DQS_n[2]\": {\n            \"IO_STANDARD\": \"DIFFERENTIAL 1.5-V SSTL CLASS I\", \n            \"LOC\": \"PIN_G35\"\n        }, \n        \"DDR3A_DQS_n[3]\": {\n            \"IO_STANDARD\": \"DIFFERENTIAL 1.5-V SSTL CLASS I\", \n            \"LOC\": \"PIN_T35\"\n        }, \n        \"DDR3A_DQS_n[4]\": {\n            \"IO_STANDARD\": \"DIFFERENTIAL 1.5-V SSTL CLASS I\", \n            \"LOC\": \"PIN_T32\"\n        }, \n        \"DDR3A_DQS_n[5]\": {\n            \"IO_STANDARD\": \"DIFFERENTIAL 1.5-V SSTL CLASS I\", \n            \"LOC\": \"PIN_R30\"\n        }, \n        \"DDR3A_DQS_n[6]\": {\n            \"IO_STANDARD\": \"DIFFERENTIAL 1.5-V SSTL CLASS I\", \n            \"LOC\": \"PIN_H30\"\n        }, \n        \"DDR3A_DQS_n[7]\": {\n            \"IO_STANDARD\": \"DIFFERENTIAL 1.5-V SSTL CLASS I\", \n            \"LOC\": \"PIN_Y29\"\n        }, \n        \"DDR3A_DQ[0]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_A35\"\n        }, \n        \"DDR3A_DQ[10]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_C30\"\n        }, \n        \"DDR3A_DQ[11]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_D30\"\n        }, \n        \"DDR3A_DQ[12]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_B29\"\n        }, \n        \"DDR3A_DQ[13]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_E30\"\n        }, \n        \"DDR3A_DQ[14]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_F31\"\n        }, \n        \"DDR3A_DQ[15]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_G31\"\n        }, \n        \"DDR3A_DQ[16]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_F35\"\n        }, \n        \"DDR3A_DQ[17]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_G34\"\n        }, \n        \"DDR3A_DQ[18]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_J33\"\n        }, \n        \"DDR3A_DQ[19]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_J34\"\n        }, \n        \"DDR3A_DQ[1]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_A34\"\n        }, \n        \"DDR3A_DQ[20]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_F34\"\n        }, \n        \"DDR3A_DQ[21]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_E35\"\n        }, \n        \"DDR3A_DQ[22]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_J31\"\n        }, \n        \"DDR3A_DQ[23]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_K31\"\n        }, \n        \"DDR3A_DQ[24]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_P34\"\n        }, \n        \"DDR3A_DQ[25]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_R33\"\n        }, \n        \"DDR3A_DQ[26]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_M34\"\n        }, \n        \"DDR3A_DQ[27]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_L33\"\n        }, \n        \"DDR3A_DQ[28]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_R34\"\n        }, \n        \"DDR3A_DQ[29]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_T34\"\n        }, \n        \"DDR3A_DQ[2]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_D36\"\n        }, \n        \"DDR3A_DQ[30]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_W34\"\n        }, \n        \"DDR3A_DQ[31]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_V35\"\n        }, \n        \"DDR3A_DQ[32]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_P33\"\n        }, \n        \"DDR3A_DQ[33]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_P32\"\n        }, \n        \"DDR3A_DQ[34]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_V33\"\n        }, \n        \"DDR3A_DQ[35]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_V34\"\n        }, \n        \"DDR3A_DQ[36]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_N31\"\n        }, \n        \"DDR3A_DQ[37]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_M31\"\n        }, \n        \"DDR3A_DQ[38]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_U32\"\n        }, \n        \"DDR3A_DQ[39]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_U33\"\n        }, \n        \"DDR3A_DQ[3]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_C33\"\n        }, \n        \"DDR3A_DQ[40]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_R31\"\n        }, \n        \"DDR3A_DQ[41]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_W31\"\n        }, \n        \"DDR3A_DQ[42]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_U30\"\n        }, \n        \"DDR3A_DQ[43]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_P31\"\n        }, \n        \"DDR3A_DQ[44]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_T31\"\n        }, \n        \"DDR3A_DQ[45]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_Y32\"\n        }, \n        \"DDR3A_DQ[46]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_T29\"\n        }, \n        \"DDR3A_DQ[47]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_P30\"\n        }, \n        \"DDR3A_DQ[48]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_H32\"\n        }, \n        \"DDR3A_DQ[49]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_H31\"\n        }, \n        \"DDR3A_DQ[4]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_B32\"\n        }, \n        \"DDR3A_DQ[50]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_L30\"\n        }, \n        \"DDR3A_DQ[51]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_L29\"\n        }, \n        \"DDR3A_DQ[52]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_F32\"\n        }, \n        \"DDR3A_DQ[53]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_G32\"\n        }, \n        \"DDR3A_DQ[54]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_M30\"\n        }, \n        \"DDR3A_DQ[55]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_N29\"\n        }, \n        \"DDR3A_DQ[56]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_U29\"\n        }, \n        \"DDR3A_DQ[57]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_V28\"\n        }, \n        \"DDR3A_DQ[58]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_Y28\"\n        }, \n        \"DDR3A_DQ[59]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_W29\"\n        }, \n        \"DDR3A_DQ[5]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_D35\"\n        }, \n        \"DDR3A_DQ[60]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_V30\"\n        }, \n        \"DDR3A_DQ[61]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_V29\"\n        }, \n        \"DDR3A_DQ[62]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_W28\"\n        }, \n        \"DDR3A_DQ[63]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_Y27\"\n        }, \n        \"DDR3A_DQ[6]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_D33\"\n        }, \n        \"DDR3A_DQ[7]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_E33\"\n        }, \n        \"DDR3A_DQ[8]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_A32\"\n        }, \n        \"DDR3A_DQ[9]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_A31\"\n        }, \n        \"DDR3A_EVENT_n\": {\n            \"IO_STANDARD\": \"1.5 V\", \n            \"LOC\": \"PIN_K19\"\n        }, \n        \"DDR3A_ODT[0]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_V36\"\n        }, \n        \"DDR3A_ODT[1]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_W35\"\n        }, \n        \"DDR3A_RAS_n\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_P38\"\n        }, \n        \"DDR3A_RESET_n\": {\n            \"IO_STANDARD\": \"1.5 V\", \n            \"LOC\": \"PIN_H33\"\n        }, \n        \"DDR3A_SCL\": {\n            \"IO_STANDARD\": \"1.5 V\", \n            \"LOC\": \"PIN_C15\"\n        }, \n        \"DDR3A_SDA\": {\n            \"IO_STANDARD\": \"1.5 V\", \n            \"LOC\": \"PIN_P15\"\n        }, \n        \"DDR3A_WE_n\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_N37\"\n        }\n    }, \n    \"DDR3B\": {\n        \"DDR3B_A[0]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_G17\"\n        }, \n        \"DDR3B_A[10]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_C19\"\n        }, \n        \"DDR3B_A[11]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_R18\"\n        }, \n        \"DDR3B_A[12]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_K18\"\n        }, \n        \"DDR3B_A[13]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_E18\"\n        }, \n        \"DDR3B_A[14]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_T19\"\n        }, \n        \"DDR3B_A[15]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_R19\"\n        }, \n        \"DDR3B_A[1]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_F17\"\n        }, \n        \"DDR3B_A[2]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_N17\"\n        }, \n        \"DDR3B_A[3]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_F19\"\n        }, \n        \"DDR3B_A[4]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_N19\"\n        }, \n        \"DDR3B_A[5]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_H16\"\n        }, \n        \"DDR3B_A[6]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_M17\"\n        }, \n        \"DDR3B_A[7]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_T18\"\n        }, \n        \"DDR3B_A[8]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_H17\"\n        }, \n        \"DDR3B_A[9]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_J19\"\n        }, \n        \"DDR3B_BA[0]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_C18\"\n        }, \n        \"DDR3B_BA[1]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_G19\"\n        }, \n        \"DDR3B_BA[2]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_M20\"\n        }, \n        \"DDR3B_CAS_n\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_A17\"\n        }, \n        \"DDR3B_CKE[0]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_P17\"\n        }, \n        \"DDR3B_CKE[1]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_V18\"\n        }, \n        \"DDR3B_CK[0]\": {\n            \"IO_STANDARD\": \"DIFFERENTIAL 1.5-V SSTL CLASS I\", \n            \"LOC\": \"PIN_B16\"\n        }, \n        \"DDR3B_CK[1]\": {\n            \"IO_STANDARD\": \"DIFFERENTIAL 1.5-V SSTL CLASS I\", \n            \"LOC\": \"PIN_E17\"\n        }, \n        \"DDR3B_CK_n[0]\": {\n            \"IO_STANDARD\": \"DIFFERENTIAL 1.5-V SSTL CLASS I\", \n            \"LOC\": \"PIN_A16\"\n        }, \n        \"DDR3B_CK_n[1]\": {\n            \"IO_STANDARD\": \"DIFFERENTIAL 1.5-V SSTL CLASS I\", \n            \"LOC\": \"PIN_D17\"\n        }, \n        \"DDR3B_CS_n[0]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_B19\"\n        }, \n        \"DDR3B_CS_n[1]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_B17\"\n        }, \n        \"DDR3B_DM[0]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_R15\"\n        }, \n        \"DDR3B_DM[1]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_K15\"\n        }, \n        \"DDR3B_DM[2]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_V12\"\n        }, \n        \"DDR3B_DM[3]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_G10\"\n        }, \n        \"DDR3B_DM[4]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_T12\"\n        }, \n        \"DDR3B_DM[5]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_C16\"\n        }, \n        \"DDR3B_DM[6]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_H15\"\n        }, \n        \"DDR3B_DM[7]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_B11\"\n        }, \n        \"DDR3B_DQS[0]\": {\n            \"IO_STANDARD\": \"DIFFERENTIAL 1.5-V SSTL CLASS I\", \n            \"LOC\": \"PIN_Y16\"\n        }, \n        \"DDR3B_DQS[1]\": {\n            \"IO_STANDARD\": \"DIFFERENTIAL 1.5-V SSTL CLASS I\", \n            \"LOC\": \"PIN_V17\"\n        }, \n        \"DDR3B_DQS[2]\": {\n            \"IO_STANDARD\": \"DIFFERENTIAL 1.5-V SSTL CLASS I\", \n            \"LOC\": \"PIN_P14\"\n        }, \n        \"DDR3B_DQS[3]\": {\n            \"IO_STANDARD\": \"DIFFERENTIAL 1.5-V SSTL CLASS I\", \n            \"LOC\": \"PIN_K11\"\n        }, \n        \"DDR3B_DQS[4]\": {\n            \"IO_STANDARD\": \"DIFFERENTIAL 1.5-V SSTL CLASS I\", \n            \"LOC\": \"PIN_U9\"\n        }, \n        \"DDR3B_DQS[5]\": {\n            \"IO_STANDARD\": \"DIFFERENTIAL 1.5-V SSTL CLASS I\", \n            \"LOC\": \"PIN_E15\"\n        }, \n        \"DDR3B_DQS[6]\": {\n            \"IO_STANDARD\": \"DIFFERENTIAL 1.5-V SSTL CLASS I\", \n            \"LOC\": \"PIN_L15\"\n        }, \n        \"DDR3B_DQS[7]\": {\n            \"IO_STANDARD\": \"DIFFERENTIAL 1.5-V SSTL CLASS I\", \n            \"LOC\": \"PIN_D12\"\n        }, \n        \"DDR3B_DQS_n[0]\": {\n            \"IO_STANDARD\": \"DIFFERENTIAL 1.5-V SSTL CLASS I\", \n            \"LOC\": \"PIN_W16\"\n        }, \n        \"DDR3B_DQS_n[1]\": {\n            \"IO_STANDARD\": \"DIFFERENTIAL 1.5-V SSTL CLASS I\", \n            \"LOC\": \"PIN_U17\"\n        }, \n        \"DDR3B_DQS_n[2]\": {\n            \"IO_STANDARD\": \"DIFFERENTIAL 1.5-V SSTL CLASS I\", \n            \"LOC\": \"PIN_N14\"\n        }, \n        \"DDR3B_DQS_n[3]\": {\n            \"IO_STANDARD\": \"DIFFERENTIAL 1.5-V SSTL CLASS I\", \n            \"LOC\": \"PIN_L11\"\n        }, \n        \"DDR3B_DQS_n[4]\": {\n            \"IO_STANDARD\": \"DIFFERENTIAL 1.5-V SSTL CLASS I\", \n            \"LOC\": \"PIN_T9\"\n        }, \n        \"DDR3B_DQS_n[5]\": {\n            \"IO_STANDARD\": \"DIFFERENTIAL 1.5-V SSTL CLASS I\", \n            \"LOC\": \"PIN_D15\"\n        }, \n        \"DDR3B_DQS_n[6]\": {\n            \"IO_STANDARD\": \"DIFFERENTIAL 1.5-V SSTL CLASS I\", \n            \"LOC\": \"PIN_K14\"\n        }, \n        \"DDR3B_DQS_n[7]\": {\n            \"IO_STANDARD\": \"DIFFERENTIAL 1.5-V SSTL CLASS I\", \n            \"LOC\": \"PIN_C12\"\n        }, \n        \"DDR3B_DQ[0]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_Y17\"\n        }, \n        \"DDR3B_DQ[10]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_R16\"\n        }, \n        \"DDR3B_DQ[11]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_P16\"\n        }, \n        \"DDR3B_DQ[12]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_N16\"\n        }, \n        \"DDR3B_DQ[13]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_M15\"\n        }, \n        \"DDR3B_DQ[14]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_M14\"\n        }, \n        \"DDR3B_DQ[15]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_L14\"\n        }, \n        \"DDR3B_DQ[16]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_T14\"\n        }, \n        \"DDR3B_DQ[17]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_U14\"\n        }, \n        \"DDR3B_DQ[18]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_U11\"\n        }, \n        \"DDR3B_DQ[19]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_T13\"\n        }, \n        \"DDR3B_DQ[1]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_W17\"\n        }, \n        \"DDR3B_DQ[20]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_U12\"\n        }, \n        \"DDR3B_DQ[21]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_R13\"\n        }, \n        \"DDR3B_DQ[22]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_P13\"\n        }, \n        \"DDR3B_DQ[23]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_N13\"\n        }, \n        \"DDR3B_DQ[24]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_K12\"\n        }, \n        \"DDR3B_DQ[25]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_J12\"\n        }, \n        \"DDR3B_DQ[26]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_J10\"\n        }, \n        \"DDR3B_DQ[27]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_H12\"\n        }, \n        \"DDR3B_DQ[28]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_N11\"\n        }, \n        \"DDR3B_DQ[29]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_M11\"\n        }, \n        \"DDR3B_DQ[2]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_V15\"\n        }, \n        \"DDR3B_DQ[30]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_H10\"\n        }, \n        \"DDR3B_DQ[31]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_H11\"\n        }, \n        \"DDR3B_DQ[32]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_T10\"\n        }, \n        \"DDR3B_DQ[33]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_R10\"\n        }, \n        \"DDR3B_DQ[34]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_M12\"\n        }, \n        \"DDR3B_DQ[35]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_L12\"\n        }, \n        \"DDR3B_DQ[36]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_V10\"\n        }, \n        \"DDR3B_DQ[37]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_V9\"\n        }, \n        \"DDR3B_DQ[38]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_R12\"\n        }, \n        \"DDR3B_DQ[39]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_P12\"\n        }, \n        \"DDR3B_DQ[3]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_T15\"\n        }, \n        \"DDR3B_DQ[40]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_D14\"\n        }, \n        \"DDR3B_DQ[41]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_C13\"\n        }, \n        \"DDR3B_DQ[42]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_B14\"\n        }, \n        \"DDR3B_DQ[43]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_B13\"\n        }, \n        \"DDR3B_DQ[44]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_E14\"\n        }, \n        \"DDR3B_DQ[45]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_F14\"\n        }, \n        \"DDR3B_DQ[46]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_A14\"\n        }, \n        \"DDR3B_DQ[47]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_A13\"\n        }, \n        \"DDR3B_DQ[48]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_K13\"\n        }, \n        \"DDR3B_DQ[49]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_K16\"\n        }, \n        \"DDR3B_DQ[4]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_V13\"\n        }, \n        \"DDR3B_DQ[50]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_H13\"\n        }, \n        \"DDR3B_DQ[51]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_H14\"\n        }, \n        \"DDR3B_DQ[52]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_J13\"\n        }, \n        \"DDR3B_DQ[53]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_J16\"\n        }, \n        \"DDR3B_DQ[54]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_G13\"\n        }, \n        \"DDR3B_DQ[55]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_F13\"\n        }, \n        \"DDR3B_DQ[56]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_D11\"\n        }, \n        \"DDR3B_DQ[57]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_C10\"\n        }, \n        \"DDR3B_DQ[58]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_A10\"\n        }, \n        \"DDR3B_DQ[59]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_B10\"\n        }, \n        \"DDR3B_DQ[5]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_V16\"\n        }, \n        \"DDR3B_DQ[60]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_G11\"\n        }, \n        \"DDR3B_DQ[61]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_F11\"\n        }, \n        \"DDR3B_DQ[62]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_E11\"\n        }, \n        \"DDR3B_DQ[63]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_E12\"\n        }, \n        \"DDR3B_DQ[6]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_W14\"\n        }, \n        \"DDR3B_DQ[7]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_U15\"\n        }, \n        \"DDR3B_DQ[8]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_T17\"\n        }, \n        \"DDR3B_DQ[9]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_T16\"\n        }, \n        \"DDR3B_EVENT_n\": {\n            \"IO_STANDARD\": \"1.5 V\", \n            \"LOC\": \"PIN_K17\"\n        }, \n        \"DDR3B_ODT[0]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_M18\"\n        }, \n        \"DDR3B_ODT[1]\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_A19\"\n        }, \n        \"DDR3B_RAS_n\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_H19\"\n        }, \n        \"DDR3B_RESET_n\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_T20\"\n        }, \n        \"DDR3B_SCL\": {\n            \"IO_STANDARD\": \"1.5 V\", \n            \"LOC\": \"PIN_P18\"\n        }, \n        \"DDR3B_SDA\": {\n            \"IO_STANDARD\": \"1.5 V\", \n            \"LOC\": \"PIN_P19\"\n        }, \n        \"DDR3B_WE_n\": {\n            \"IO_STANDARD\": \"SSTL-15 CLASS I\", \n            \"LOC\": \"PIN_D18\"\n        }\n    }, \n    \"FAN\": {\n        \"FAN_CTRL\": {\n            \"IO_STANDARD\": \"2.5 V\", \n            \"LOC\": \"PIN_AR32\"\n        }\n    }, \n    \"FLASH\": {\n        \"FLASH_ADV_n\": {\n            \"IO_STANDARD\": \"2.5 V\", \n            \"LOC\": \"PIN_AK29\"\n        }, \n        \"FLASH_CE_n[0]\": {\n            \"IO_STANDARD\": \"2.5 V\", \n            \"LOC\": \"PIN_AE27\"\n        }, \n        \"FLASH_CE_n[1]\": {\n            \"IO_STANDARD\": \"2.5 V\", \n            \"LOC\": \"PIN_BA31\"\n        }, \n        \"FLASH_CLK\": {\n            \"IO_STANDARD\": \"2.5 V\", \n            \"LOC\": \"PIN_AL29\"\n        }, \n        \"FLASH_OE_n\": {\n            \"IO_STANDARD\": \"2.5 V\", \n            \"LOC\": \"PIN_AY30\"\n        }, \n        \"FLASH_RDY_BSY_n[0]\": {\n            \"IO_STANDARD\": \"2.5 V\", \n            \"LOC\": \"PIN_BA29\"\n        }, \n        \"FLASH_RDY_BSY_n[1]\": {\n            \"IO_STANDARD\": \"2.5 V\", \n            \"LOC\": \"PIN_BB32\"\n        }, \n        \"FLASH_RESET_n\": {\n            \"IO_STANDARD\": \"2.5 V\", \n            \"LOC\": \"PIN_AE28\"\n        }, \n        \"FLASH_WE_n\": {\n            \"IO_STANDARD\": \"2.5 V\", \n            \"LOC\": \"PIN_AR31\"\n        }\n    }, \n    \"FSM\": {\n        \"FSM_A[0]\": {\n            \"IO_STANDARD\": \"2.5 V\", \n            \"LOC\": \"PIN_AU32\"\n        }, \n        \"FSM_A[10]\": {\n            \"IO_STANDARD\": \"2.5 V\", \n            \"LOC\": \"PIN_AN30\"\n        }, \n        \"FSM_A[11]\": {\n            \"IO_STANDARD\": \"2.5 V\", \n            \"LOC\": \"PIN_AH33\"\n        }, \n        \"FSM_A[12]\": {\n            \"IO_STANDARD\": \"2.5 V\", \n            \"LOC\": \"PIN_AK32\"\n        }, \n        \"FSM_A[13]\": {\n            \"IO_STANDARD\": \"2.5 V\", \n            \"LOC\": \"PIN_AM32\"\n        }, \n        \"FSM_A[14]\": {\n            \"IO_STANDARD\": \"2.5 V\", \n            \"LOC\": \"PIN_AM31\"\n        }, \n        \"FSM_A[15]\": {\n            \"IO_STANDARD\": \"2.5 V\", \n            \"LOC\": \"PIN_AL31\"\n        }, \n        \"FSM_A[16]\": {\n            \"IO_STANDARD\": \"2.5 V\", \n            \"LOC\": \"PIN_AN33\"\n        }, \n        \"FSM_A[17]\": {\n            \"IO_STANDARD\": \"2.5 V\", \n            \"LOC\": \"PIN_AP33\"\n        }, \n        \"FSM_A[18]\": {\n            \"IO_STANDARD\": \"2.5 V\", \n            \"LOC\": \"PIN_AT32\"\n        }, \n        \"FSM_A[19]\": {\n            \"IO_STANDARD\": \"2.5 V\", \n            \"LOC\": \"PIN_AT29\"\n        }, \n        \"FSM_A[1]\": {\n            \"IO_STANDARD\": \"2.5 V\", \n            \"LOC\": \"PIN_AH30\"\n        }, \n        \"FSM_A[20]\": {\n            \"IO_STANDARD\": \"2.5 V\", \n            \"LOC\": \"PIN_AP31\"\n        }, \n        \"FSM_A[21]\": {\n            \"IO_STANDARD\": \"2.5 V\", \n            \"LOC\": \"PIN_AR30\"\n        }, \n        \"FSM_A[22]\": {\n            \"IO_STANDARD\": \"2.5 V\", \n            \"LOC\": \"PIN_AU30\"\n        }, \n        \"FSM_A[23]\": {\n            \"IO_STANDARD\": \"2.5 V\", \n            \"LOC\": \"PIN_AJ31\"\n        }, \n        \"FSM_A[24]\": {\n            \"IO_STANDARD\": \"2.5 V\", \n            \"LOC\": \"PIN_AP30\"\n        }, \n        \"FSM_A[25]\": {\n            \"IO_STANDARD\": \"2.5 V\", \n            \"LOC\": \"PIN_AN31\"\n        }, \n        \"FSM_A[26]\": {\n            \"IO_STANDARD\": \"2.5 V\", \n            \"LOC\": \"PIN_AT30\"\n        }, \n        \"FSM_A[2]\": {\n            \"IO_STANDARD\": \"2.5 V\", \n            \"LOC\": \"PIN_AJ30\"\n        }, \n        \"FSM_A[3]\": {\n            \"IO_STANDARD\": \"2.5 V\", \n            \"LOC\": \"PIN_AH31\"\n        }, \n        \"FSM_A[4]\": {\n            \"IO_STANDARD\": \"2.5 V\", \n            \"LOC\": \"PIN_AK30\"\n        }, \n        \"FSM_A[5]\": {\n            \"IO_STANDARD\": \"2.5 V\", \n            \"LOC\": \"PIN_AJ32\"\n        }, \n        \"FSM_A[6]\": {\n            \"IO_STANDARD\": \"2.5 V\", \n            \"LOC\": \"PIN_AG33\"\n        }, \n        \"FSM_A[7]\": {\n            \"IO_STANDARD\": \"2.5 V\", \n            \"LOC\": \"PIN_AL30\"\n        }, \n        \"FSM_A[8]\": {\n            \"IO_STANDARD\": \"2.5 V\", \n            \"LOC\": \"PIN_AK33\"\n        }, \n        \"FSM_A[9]\": {\n            \"IO_STANDARD\": \"2.5 V\", \n            \"LOC\": \"PIN_AJ33\"\n        }, \n        \"FSM_D[0]\": {\n            \"IO_STANDARD\": \"2.5 V\", \n            \"LOC\": \"PIN_AG26\"\n        }, \n        \"FSM_D[10]\": {\n            \"IO_STANDARD\": \"2.5 V\", \n            \"LOC\": \"PIN_AE33\"\n        }, \n        \"FSM_D[11]\": {\n            \"IO_STANDARD\": \"2.5 V\", \n            \"LOC\": \"PIN_AE31\"\n        }, \n        \"FSM_D[12]\": {\n            \"IO_STANDARD\": \"2.5 V\", \n            \"LOC\": \"PIN_AF28\"\n        }, \n        \"FSM_D[13]\": {\n            \"IO_STANDARD\": \"2.5 V\", \n            \"LOC\": \"PIN_AE30\"\n        }, \n        \"FSM_D[14]\": {\n            \"IO_STANDARD\": \"2.5 V\", \n            \"LOC\": \"PIN_AG29\"\n        }, \n        \"FSM_D[15]\": {\n            \"IO_STANDARD\": \"2.5 V\", \n            \"LOC\": \"PIN_AG27\"\n        }, \n        \"FSM_D[16]\": {\n            \"IO_STANDARD\": \"2.5 V\", \n            \"LOC\": \"PIN_AP28\"\n        }, \n        \"FSM_D[17]\": {\n            \"IO_STANDARD\": \"2.5 V\", \n            \"LOC\": \"PIN_AN28\"\n        }, \n        \"FSM_D[18]\": {\n            \"IO_STANDARD\": \"2.5 V\", \n            \"LOC\": \"PIN_AU31\"\n        }, \n        \"FSM_D[19]\": {\n            \"IO_STANDARD\": \"2.5 V\", \n            \"LOC\": \"PIN_AW32\"\n        }, \n        \"FSM_D[1]\": {\n            \"IO_STANDARD\": \"2.5 V\", \n            \"LOC\": \"PIN_AD33\"\n        }, \n        \"FSM_D[20]\": {\n            \"IO_STANDARD\": \"2.5 V\", \n            \"LOC\": \"PIN_BD32\"\n        }, \n        \"FSM_D[21]\": {\n            \"IO_STANDARD\": \"2.5 V\", \n            \"LOC\": \"PIN_AY31\"\n        }, \n        \"FSM_D[22]\": {\n            \"IO_STANDARD\": \"2.5 V\", \n            \"LOC\": \"PIN_BA30\"\n        }, \n        \"FSM_D[23]\": {\n            \"IO_STANDARD\": \"2.5 V\", \n            \"LOC\": \"PIN_BB30\"\n        }, \n        \"FSM_D[24]\": {\n            \"IO_STANDARD\": \"2.5 V\", \n            \"LOC\": \"PIN_AM29\"\n        }, \n        \"FSM_D[25]\": {\n            \"IO_STANDARD\": \"2.5 V\", \n            \"LOC\": \"PIN_AR29\"\n        }, \n        \"FSM_D[26]\": {\n            \"IO_STANDARD\": \"2.5 V\", \n            \"LOC\": \"PIN_AV31\"\n        }, \n        \"FSM_D[27]\": {\n            \"IO_STANDARD\": \"2.5 V\", \n            \"LOC\": \"PIN_AV32\"\n        }, \n        \"FSM_D[28]\": {\n            \"IO_STANDARD\": \"2.5 V\", \n            \"LOC\": \"PIN_BC31\"\n        }, \n        \"FSM_D[29]\": {\n            \"IO_STANDARD\": \"2.5 V\", \n            \"LOC\": \"PIN_AW30\"\n        }, \n        \"FSM_D[2]\": {\n            \"IO_STANDARD\": \"2.5 V\", \n            \"LOC\": \"PIN_AE34\"\n        }, \n        \"FSM_D[30]\": {\n            \"IO_STANDARD\": \"2.5 V\", \n            \"LOC\": \"PIN_BC32\"\n        }, \n        \"FSM_D[31]\": {\n            \"IO_STANDARD\": \"2.5 V\", \n            \"LOC\": \"PIN_BD31\"\n        }, \n        \"FSM_D[3]\": {\n            \"IO_STANDARD\": \"2.5 V\", \n            \"LOC\": \"PIN_AF31\"\n        }, \n        \"FSM_D[4]\": {\n            \"IO_STANDARD\": \"2.5 V\", \n            \"LOC\": \"PIN_AG28\"\n        }, \n        \"FSM_D[5]\": {\n            \"IO_STANDARD\": \"2.5 V\", \n            \"LOC\": \"PIN_AG30\"\n        }, \n        \"FSM_D[6]\": {\n            \"IO_STANDARD\": \"2.5 V\", \n            \"LOC\": \"PIN_AF29\"\n        }, \n        \"FSM_D[7]\": {\n            \"IO_STANDARD\": \"2.5 V\", \n            \"LOC\": \"PIN_AE29\"\n        }, \n        \"FSM_D[8]\": {\n            \"IO_STANDARD\": \"2.5 V\", \n            \"LOC\": \"PIN_AG25\"\n        }, \n        \"FSM_D[9]\": {\n            \"IO_STANDARD\": \"2.5 V\", \n            \"LOC\": \"PIN_AF34\"\n        }\n    }, \n    \"HEX0\": {\n        \"HEX0_DP\": {\n            \"IO_STANDARD\": \"1.5 V\", \n            \"LOC\": \"PIN_P8\"\n        }, \n        \"HEX0_D[0]\": {\n            \"IO_STANDARD\": \"1.5 V\", \n            \"LOC\": \"PIN_G8\"\n        }, \n        \"HEX0_D[1]\": {\n            \"IO_STANDARD\": \"1.5 V\", \n            \"LOC\": \"PIN_H8\"\n        }, \n        \"HEX0_D[2]\": {\n            \"IO_STANDARD\": \"1.5 V\", \n            \"LOC\": \"PIN_J9\"\n        }, \n        \"HEX0_D[3]\": {\n            \"IO_STANDARD\": \"1.5 V\", \n            \"LOC\": \"PIN_K10\"\n        }, \n        \"HEX0_D[4]\": {\n            \"IO_STANDARD\": \"1.5 V\", \n            \"LOC\": \"PIN_K8\"\n        }, \n        \"HEX0_D[5]\": {\n            \"IO_STANDARD\": \"1.5 V\", \n            \"LOC\": \"PIN_K9\"\n        }, \n        \"HEX0_D[6]\": {\n            \"IO_STANDARD\": \"1.5 V\", \n            \"LOC\": \"PIN_N8\"\n        }\n    }, \n    \"HEX1\": {\n        \"HEX1_DP\": {\n            \"IO_STANDARD\": \"1.5 V\", \n            \"LOC\": \"PIN_E9\"\n        }, \n        \"HEX1_D[0]\": {\n            \"IO_STANDARD\": \"1.5 V\", \n            \"LOC\": \"PIN_H18\"\n        }, \n        \"HEX1_D[1]\": {\n            \"IO_STANDARD\": \"1.5 V\", \n            \"LOC\": \"PIN_G16\"\n        }, \n        \"HEX1_D[2]\": {\n            \"IO_STANDARD\": \"1.5 V\", \n            \"LOC\": \"PIN_F16\"\n        }, \n        \"HEX1_D[3]\": {\n            \"IO_STANDARD\": \"1.5 V\", \n            \"LOC\": \"PIN_A7\"\n        }, \n        \"HEX1_D[4]\": {\n            \"IO_STANDARD\": \"1.5 V\", \n            \"LOC\": \"PIN_B7\"\n        }, \n        \"HEX1_D[5]\": {\n            \"IO_STANDARD\": \"1.5 V\", \n            \"LOC\": \"PIN_C9\"\n        }, \n        \"HEX1_D[6]\": {\n            \"IO_STANDARD\": \"1.5 V\", \n            \"LOC\": \"PIN_D10\"\n        }\n    }, \n    \"LED\": {\n        \"LED[0]\": {\n            \"PIO_DIRECTION\": \"OUTPUT\",\n            \"IO_STANDARD\": \"2.5 V\", \n            \"LOC\": \"PIN_AW37\"\n        }, \n        \"LED[1]\": {\n            \"PIO_DIRECTION\": \"OUTPUT\",\n            \"IO_STANDARD\": \"2.5 V\", \n            \"LOC\": \"PIN_AV37\"\n        }, \n        \"LED[2]\": {\n            \"PIO_DIRECTION\": \"OUTPUT\",\n            \"IO_STANDARD\": \"2.5 V\", \n            \"LOC\": \"PIN_BB36\"\n        }, \n        \"LED[3]\": {\n            \"PIO_DIRECTION\": \"OUTPUT\",\n            \"IO_STANDARD\": \"2.5 V\", \n            \"LOC\": \"PIN_BB39\"\n        }, \n        \"LED_BRACKET[0]\": {\n            \"PIO_DIRECTION\": \"OUTPUT\",\n            \"IO_STANDARD\": \"2.5 V\", \n            \"LOC\": \"PIN_AH15\"\n        }, \n        \"LED_BRACKET[1]\": {\n            \"PIO_DIRECTION\": \"OUTPUT\",\n            \"IO_STANDARD\": \"2.5 V\", \n            \"LOC\": \"PIN_AH13\"\n        }, \n        \"LED_BRACKET[2]\": {\n            \"PIO_DIRECTION\": \"OUTPUT\",\n            \"IO_STANDARD\": \"2.5 V\", \n            \"LOC\": \"PIN_AJ13\"\n        }, \n        \"LED_BRACKET[3]\": {\n            \"PIO_DIRECTION\": \"OUTPUT\",\n            \"IO_STANDARD\": \"2.5 V\", \n            \"LOC\": \"PIN_AJ14\"\n        }, \n        \"LED_RJ45_L\": {\n            \"IO_STANDARD\": \"2.5 V\", \n            \"LOC\": \"PIN_AG15\"\n        }, \n        \"LED_RJ45_R\": {\n            \"IO_STANDARD\": \"2.5 V\", \n            \"LOC\": \"PIN_AG16\"\n        }\n    }, \n    \"OSC\": {\n        \"OSC_50_B3B\": {\n            \"PIO_DIRECTION\": \"INPUT\",\n            \"IO_STANDARD\": \"2.5 V\", \n            \"LOC\": \"PIN_AW35\"\n        }, \n        \"OSC_50_B3D\": {\n            \"PIO_DIRECTION\": \"INPUT\",\n            \"IO_STANDARD\": \"1.8 V\", \n            \"LOC\": \"PIN_BC28\"\n        }, \n        \"OSC_50_B4A\": {\n            \"PIO_DIRECTION\": \"INPUT\",\n            \"IO_STANDARD\": \"1.8 V\", \n            \"LOC\": \"PIN_AP10\"\n        }, \n        \"OSC_50_B4D\": {\n            \"PIO_DIRECTION\": \"INPUT\",\n            \"IO_STANDARD\": \"1.8 V\", \n            \"LOC\": \"PIN_AY18\"\n        }, \n        \"OSC_50_B7A\": {\n            \"PIO_DIRECTION\": \"INPUT\",\n            \"IO_STANDARD\": \"1.5 V\", \n            \"LOC\": \"PIN_M8\"\n        }, \n        \"OSC_50_B7D\": {\n            \"PIO_DIRECTION\": \"INPUT\",\n            \"IO_STANDARD\": \"1.5 V\", \n            \"LOC\": \"PIN_J18\"\n        }, \n        \"OSC_50_B8A\": {\n            \"PIO_DIRECTION\": \"INPUT\",\n            \"IO_STANDARD\": \"1.5 V\", \n            \"LOC\": \"PIN_R36\"\n        }, \n        \"OSC_50_B8D\": {\n            \"PIO_DIRECTION\": \"INPUT\",\n            \"IO_STANDARD\": \"1.8 V\", \n            \"LOC\": \"PIN_R25\"\n        }\n    }, \n    \"PCIE\": {\n        \"PCIE_PERST_n\": {\n            \"PIO_DIRECTION\": \"INPUT\",\n            \"IO_STANDARD\": \"2.5 V\", \n            \"LOC\": \"PIN_AU33\"\n        }, \n        \"PCIE_REFCLK_p\": {\n            \"PIO_DIRECTION\": \"INPUT\",\n            \"IO_STANDARD\": \"HCSL\", \n            \"LOC\": \"PIN_AK38\"\n        }, \n        \"PCIE_RX_p[0]\": {\n            \"IO_STANDARD\": \"1.4-V PCML\", \n            \"LOC\": \"PIN_BB43\"\n        }, \n        \"PCIE_RX_p[1]\": {\n            \"IO_STANDARD\": \"1.4-V PCML\", \n            \"LOC\": \"PIN_BA41\"\n        }, \n        \"PCIE_RX_p[2]\": {\n            \"IO_STANDARD\": \"1.4-V PCML\", \n            \"LOC\": \"PIN_AW41\"\n        }, \n        \"PCIE_RX_p[3]\": {\n            \"IO_STANDARD\": \"1.4-V PCML\", \n            \"LOC\": \"PIN_AY43\"\n        }, \n        \"PCIE_RX_p[4]\": {\n            \"IO_STANDARD\": \"1.4-V PCML\", \n            \"LOC\": \"PIN_AT43\"\n        }, \n        \"PCIE_RX_p[5]\": {\n            \"IO_STANDARD\": \"1.4-V PCML\", \n            \"LOC\": \"PIN_AP43\"\n        }, \n        \"PCIE_RX_p[6]\": {\n            \"IO_STANDARD\": \"1.4-V PCML\", \n            \"LOC\": \"PIN_AM43\"\n        }, \n        \"PCIE_RX_p[7]\": {\n            \"IO_STANDARD\": \"1.4-V PCML\", \n            \"LOC\": \"PIN_AK43\"\n        }, \n        \"PCIE_SMBCLK\": {\n            \"IO_STANDARD\": \"2.5 V\", \n            \"LOC\": \"PIN_BD34\"\n        }, \n        \"PCIE_SMBDAT\": {\n            \"IO_STANDARD\": \"2.5 V\", \n            \"LOC\": \"PIN_AT33\"\n        }, \n        \"PCIE_TX_p[0]\": {\n            \"PIO_DIRECTION\": \"OUTPUT\",\n            \"IO_STANDARD\": \"1.4-V PCML\", \n            \"LOC\": \"PIN_AY39\"\n        }, \n        \"PCIE_TX_p[1]\": {\n            \"PIO_DIRECTION\": \"OUTPUT\",\n            \"IO_STANDARD\": \"1.4-V PCML\", \n            \"LOC\": \"PIN_AV39\"\n        }, \n        \"PCIE_TX_p[2]\": {\n            \"PIO_DIRECTION\": \"OUTPUT\",\n            \"IO_STANDARD\": \"1.4-V PCML\", \n            \"LOC\": \"PIN_AT39\"\n        }, \n        \"PCIE_TX_p[3]\": {\n            \"PIO_DIRECTION\": \"OUTPUT\",\n            \"IO_STANDARD\": \"1.4-V PCML\", \n            \"LOC\": \"PIN_AU41\"\n        }, \n        \"PCIE_TX_p[4]\": {\n            \"PIO_DIRECTION\": \"OUTPUT\",\n            \"IO_STANDARD\": \"1.4-V PCML\", \n            \"LOC\": \"PIN_AN41\"\n        }, \n        \"PCIE_TX_p[5]\": {\n            \"PIO_DIRECTION\": \"OUTPUT\",\n            \"IO_STANDARD\": \"1.4-V PCML\", \n            \"LOC\": \"PIN_AL41\"\n        }, \n        \"PCIE_TX_p[6]\": {\n            \"PIO_DIRECTION\": \"OUTPUT\",\n            \"IO_STANDARD\": \"1.4-V PCML\", \n            \"LOC\": \"PIN_AJ41\"\n        }, \n        \"PCIE_TX_p[7]\": {\n            \"PIO_DIRECTION\": \"OUTPUT\",\n            \"IO_STANDARD\": \"1.4-V PCML\", \n            \"LOC\": \"PIN_AG41\"\n        }, \n        \"PCIE_WAKE_n\": {\n            \"IO_STANDARD\": \"2.5 V\", \n            \"LOC\": \"PIN_BD35\"\n        },\n        \"PCIE_REFCLK_p(n)\": {\n            \"IO_STANDARD\": \"HCSL\", \n            \"LOC\": \"PIN_AK39\"\n        }, \n        \"PCIE_RX_p[0](n)\": {\n            \"PIO_DIRECTION\": \"INPUT\",\n            \"IO_STANDARD\": \"1.4-V PCML\", \n            \"LOC\": \"PIN_BB44\"\n        }, \n        \"PCIE_RX_p[1](n)\": {\n            \"PIO_DIRECTION\": \"INPUT\",\n            \"IO_STANDARD\": \"1.4-V PCML\", \n            \"LOC\": \"PIN_BA42\"\n        }, \n        \"PCIE_RX_p[2](n)\": {\n            \"PIO_DIRECTION\": \"INPUT\",\n            \"IO_STANDARD\": \"1.4-V PCML\", \n            \"LOC\": \"PIN_AW42\"\n        }, \n        \"PCIE_RX_p[3](n)\": {\n            \"PIO_DIRECTION\": \"INPUT\",\n            \"IO_STANDARD\": \"1.4-V PCML\", \n            \"LOC\": \"PIN_AY44\"\n        }, \n        \"PCIE_RX_p[4](n)\": {\n            \"PIO_DIRECTION\": \"INPUT\",\n            \"IO_STANDARD\": \"1.4-V PCML\", \n            \"LOC\": \"PIN_AT44\"\n        }, \n        \"PCIE_RX_p[5](n)\": {\n            \"PIO_DIRECTION\": \"INPUT\",\n            \"IO_STANDARD\": \"1.4-V PCML\", \n            \"LOC\": \"PIN_AP44\"\n        }, \n        \"PCIE_RX_p[6](n)\": {\n            \"PIO_DIRECTION\": \"INPUT\",\n            \"IO_STANDARD\": \"1.4-V PCML\", \n            \"LOC\": \"PIN_AM44\"\n        }, \n        \"PCIE_RX_p[7](n)\": {\n            \"PIO_DIRECTION\": \"INPUT\",\n            \"IO_STANDARD\": \"1.4-V PCML\", \n            \"LOC\": \"PIN_AK44\"\n        }, \n        \"PCIE_TX_p[0](n)\": {\n            \"IO_STANDARD\": \"1.4-V PCML\", \n            \"LOC\": \"PIN_AY40\"\n        }, \n        \"PCIE_TX_p[1](n)\": {\n            \"IO_STANDARD\": \"1.4-V PCML\", \n            \"LOC\": \"PIN_AV40\"\n        }, \n        \"PCIE_TX_p[2](n)\": {\n            \"IO_STANDARD\": \"1.4-V PCML\", \n            \"LOC\": \"PIN_AT40\"\n        }, \n        \"PCIE_TX_p[3](n)\": {\n            \"IO_STANDARD\": \"1.4-V PCML\", \n            \"LOC\": \"PIN_AU42\"\n        }, \n        \"PCIE_TX_p[4](n)\": {\n            \"IO_STANDARD\": \"1.4-V PCML\", \n            \"LOC\": \"PIN_AN42\"\n        }, \n        \"PCIE_TX_p[5](n)\": {\n            \"IO_STANDARD\": \"1.4-V PCML\", \n            \"LOC\": \"PIN_AL42\"\n        }, \n        \"PCIE_TX_p[6](n)\": {\n            \"IO_STANDARD\": \"1.4-V PCML\", \n            \"LOC\": \"PIN_AJ42\"\n        }, \n        \"PCIE_TX_p[7](n)\": {\n            \"IO_STANDARD\": \"1.4-V PCML\", \n            \"LOC\": \"PIN_AG42\"\n        }\n    }, \n    \"SATA\": {\n        \"SATA_DEVICE_REFCLK_p(n)\": {\n            \"IO_STANDARD\": \"HCSL\", \n            \"LOC\": \"PIN_V40\"\n        }, \n        \"SATA_DEVICE_RX_p[0](n)\": {\n            \"IO_STANDARD\": \"1.4-V PCML\", \n            \"LOC\": \"PIN_K44\"\n        }, \n        \"SATA_DEVICE_RX_p[1](n)\": {\n            \"IO_STANDARD\": \"1.4-V PCML\", \n            \"LOC\": \"PIN_H44\"\n        }, \n        \"SATA_DEVICE_TX_p[0](n)\": {\n            \"IO_STANDARD\": \"1.4-V PCML\", \n            \"LOC\": \"PIN_K40\"\n        }, \n        \"SATA_DEVICE_TX_p[1](n)\": {\n            \"IO_STANDARD\": \"1.4-V PCML\", \n            \"LOC\": \"PIN_H40\"\n        }, \n        \"SATA_HOST_REFCLK_p(n)\": {\n            \"IO_STANDARD\": \"HCSL\", \n            \"LOC\": \"PIN_V5\"\n        }, \n        \"SATA_HOST_RX_p[0](n)\": {\n            \"IO_STANDARD\": \"1.4-V PCML\", \n            \"LOC\": \"PIN_K1\"\n        }, \n        \"SATA_HOST_RX_p[1](n)\": {\n            \"IO_STANDARD\": \"1.4-V PCML\", \n            \"LOC\": \"PIN_H1\"\n        }, \n        \"SATA_HOST_TX_p[0](n)\": {\n            \"IO_STANDARD\": \"1.4-V PCML\", \n            \"LOC\": \"PIN_K5\"\n        }, \n        \"SATA_HOST_TX_p[1](n)\": {\n            \"IO_STANDARD\": \"1.4-V PCML\", \n            \"LOC\": \"PIN_H5\"\n        }\n    }, \n    \"SFP\": {\n        \"SFP1G_REFCLK_p\": {\n            \"PIO_DIRECTION\": \"INPUT\",\n            \"IO_STANDARD\": \"HCSL\", \n            \"LOC\": \"PIN_AH6\"\n        },\n        \"SFP1G_REFCLK_p(n)\": {\n            \"PIO_DIRECTION\": \"INPUT\",\n            \"IO_STANDARD\": \"HCSL\", \n            \"LOC\": \"PIN_AH5\"\n        }, \n        \"SFP_REFCLK_p(n)\": {\n            \"PIO_DIRECTION\": \"INPUT\",\n            \"IO_STANDARD\": \"HCSL\", \n            \"LOC\": \"PIN_AK6\"\n        },\n        \"SFP_REFCLK_p\": {\n            \"PIO_DIRECTION\": \"INPUT\",\n            \"IO_STANDARD\": \"HCSL\", \n            \"LOC\": \"PIN_AK7\"\n        }\n    }, \n    \"PLL\": {\n        \"PLL_SCL\": {\n            \"IO_STANDARD\": \"2.5 V\", \n            \"LOC\": \"PIN_AF32\"\n        }, \n        \"PLL_SDA\": {\n            \"IO_STANDARD\": \"2.5 V\", \n            \"LOC\": \"PIN_AG32\"\n        } \n    }, \n    \"QDRIIA\": {\n        \"QDRIIA_A[0]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_AU29\"\n        }, \n        \"QDRIIA_A[10]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_AW27\"\n        }, \n        \"QDRIIA_A[11]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_AY28\"\n        }, \n        \"QDRIIA_A[12]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_BD28\"\n        }, \n        \"QDRIIA_A[13]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_AV29\"\n        }, \n        \"QDRIIA_A[14]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_AW29\"\n        }, \n        \"QDRIIA_A[15]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_BB29\"\n        }, \n        \"QDRIIA_A[16]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_BD29\"\n        }, \n        \"QDRIIA_A[17]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_AL27\"\n        }, \n        \"QDRIIA_A[18]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_AR27\"\n        }, \n        \"QDRIIA_A[19]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_AL28\"\n        }, \n        \"QDRIIA_A[1]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_BA28\"\n        }, \n        \"QDRIIA_A[20]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_AR28\"\n        }, \n        \"QDRIIA_A[2]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_AP27\"\n        }, \n        \"QDRIIA_A[3]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_AK27\"\n        }, \n        \"QDRIIA_A[4]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_AN27\"\n        }, \n        \"QDRIIA_A[5]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_AM28\"\n        }, \n        \"QDRIIA_A[6]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_AV28\"\n        }, \n        \"QDRIIA_A[7]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_AY27\"\n        }, \n        \"QDRIIA_A[8]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_BC29\"\n        }, \n        \"QDRIIA_A[9]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_AU28\"\n        }, \n        \"QDRIIA_BWS_n[0]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_AJ24\"\n        }, \n        \"QDRIIA_BWS_n[1]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_AT27\"\n        }, \n        \"QDRIIA_CQ_n\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_BA25\"\n        }, \n        \"QDRIIA_CQ_p\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_AH22\"\n        }, \n        \"QDRIIA_DOFF_n\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_AR23\"\n        }, \n        \"QDRIIA_D[0]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_AH28\"\n        }, \n        \"QDRIIA_D[10]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_AM26\"\n        }, \n        \"QDRIIA_D[11]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_AM25\"\n        }, \n        \"QDRIIA_D[12]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_AL26\"\n        }, \n        \"QDRIIA_D[13]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_AK26\"\n        }, \n        \"QDRIIA_D[14]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_AU27\"\n        }, \n        \"QDRIIA_D[15]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_AU26\"\n        }, \n        \"QDRIIA_D[16]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_AV26\"\n        }, \n        \"QDRIIA_D[17]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_AW26\"\n        }, \n        \"QDRIIA_D[1]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_AH27\"\n        }, \n        \"QDRIIA_D[2]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_AH25\"\n        }, \n        \"QDRIIA_D[3]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_AJ28\"\n        }, \n        \"QDRIIA_D[4]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_AJ27\"\n        }, \n        \"QDRIIA_D[5]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_AJ26\"\n        }, \n        \"QDRIIA_D[6]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_AJ25\"\n        }, \n        \"QDRIIA_D[7]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_AL25\"\n        }, \n        \"QDRIIA_D[8]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_AH24\"\n        }, \n        \"QDRIIA_D[9]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_AN25\"\n        }, \n        \"QDRIIA_K_n\": {\n            \"IO_STANDARD\": \"DIFFERENTIAL 1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_AR26\"\n        }, \n        \"QDRIIA_K_p\": {\n            \"IO_STANDARD\": \"DIFFERENTIAL 1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_AP25\"\n        }, \n        \"QDRIIA_ODT\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_AN23\"\n        }, \n        \"QDRIIA_QVLD\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_AM23\"\n        }, \n        \"QDRIIA_Q[0]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_AK23\"\n        }, \n        \"QDRIIA_Q[10]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_BC26\"\n        }, \n        \"QDRIIA_Q[11]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_AY25\"\n        }, \n        \"QDRIIA_Q[12]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_AU24\"\n        }, \n        \"QDRIIA_Q[13]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_AV25\"\n        }, \n        \"QDRIIA_Q[14]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_AU25\"\n        }, \n        \"QDRIIA_Q[15]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_AR25\"\n        }, \n        \"QDRIIA_Q[16]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_AP24\"\n        }, \n        \"QDRIIA_Q[17]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_AL24\"\n        }, \n        \"QDRIIA_Q[1]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_BB26\"\n        }, \n        \"QDRIIA_Q[2]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_BD26\"\n        }, \n        \"QDRIIA_Q[3]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_BA24\"\n        }, \n        \"QDRIIA_Q[4]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_AL23\"\n        }, \n        \"QDRIIA_Q[5]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_AJ23\"\n        }, \n        \"QDRIIA_Q[6]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_AL21\"\n        }, \n        \"QDRIIA_Q[7]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_AK21\"\n        }, \n        \"QDRIIA_Q[8]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_AJ22\"\n        }, \n        \"QDRIIA_Q[9]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_AW24\"\n        }, \n        \"QDRIIA_RPS_n\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_AT26\"\n        }, \n        \"QDRIIA_WPS_n\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_AK24\"\n        }\n    }, \n    \"QDRIIB\": {\n        \"QDRIIB_A[0]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_AR24\"\n        }, \n        \"QDRIIB_A[10]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_AJ20\"\n        }, \n        \"QDRIIB_A[11]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_AG20\"\n        }, \n        \"QDRIIB_A[12]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_AW23\"\n        }, \n        \"QDRIIB_A[13]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_BB24\"\n        }, \n        \"QDRIIB_A[14]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_AY24\"\n        }, \n        \"QDRIIB_A[15]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_BD23\"\n        }, \n        \"QDRIIB_A[16]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_BC23\"\n        }, \n        \"QDRIIB_A[17]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_AG21\"\n        }, \n        \"QDRIIB_A[18]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_AM20\"\n        }, \n        \"QDRIIB_A[19]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_AK18\"\n        }, \n        \"QDRIIB_A[1]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_BB23\"\n        }, \n        \"QDRIIB_A[20]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_AN22\"\n        }, \n        \"QDRIIB_A[2]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_AK20\"\n        }, \n        \"QDRIIB_A[3]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_AJ19\"\n        }, \n        \"QDRIIB_A[4]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_AL20\"\n        }, \n        \"QDRIIB_A[5]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_AG19\"\n        }, \n        \"QDRIIB_A[6]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_AT23\"\n        }, \n        \"QDRIIB_A[7]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_AU23\"\n        }, \n        \"QDRIIB_A[8]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_AV23\"\n        }, \n        \"QDRIIB_A[9]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_AM22\"\n        }, \n        \"QDRIIB_BWS_n[0]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_AV20\"\n        }, \n        \"QDRIIB_BWS_n[1]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_AU21\"\n        }, \n        \"QDRIIB_CQ_n\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_AP18\"\n        }, \n        \"QDRIIB_CQ_p\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_AJ15\"\n        }, \n        \"QDRIIB_DOFF_n\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_AH19\"\n        }, \n        \"QDRIIB_D[0]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_BB21\"\n        }, \n        \"QDRIIB_D[10]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_AR21\"\n        }, \n        \"QDRIIB_D[11]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_AP21\"\n        }, \n        \"QDRIIB_D[12]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_BD22\"\n        }, \n        \"QDRIIB_D[13]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_BC22\"\n        }, \n        \"QDRIIB_D[14]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_BA22\"\n        }, \n        \"QDRIIB_D[15]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_AV22\"\n        }, \n        \"QDRIIB_D[16]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_AY22\"\n        }, \n        \"QDRIIB_D[17]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_AW22\"\n        }, \n        \"QDRIIB_D[1]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_BD20\"\n        }, \n        \"QDRIIB_D[2]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_BC20\"\n        }, \n        \"QDRIIB_D[3]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_AR22\"\n        }, \n        \"QDRIIB_D[4]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_BB20\"\n        }, \n        \"QDRIIB_D[5]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_AU22\"\n        }, \n        \"QDRIIB_D[6]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_BA21\"\n        }, \n        \"QDRIIB_D[7]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_AY21\"\n        }, \n        \"QDRIIB_D[8]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_AW21\"\n        }, \n        \"QDRIIB_D[9]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_AT21\"\n        }, \n        \"QDRIIB_K_n\": {\n            \"IO_STANDARD\": \"DIFFERENTIAL 1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_AT20\"\n        }, \n        \"QDRIIB_K_p\": {\n            \"IO_STANDARD\": \"DIFFERENTIAL 1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_AR20\"\n        }, \n        \"QDRIIB_ODT\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_AH18\"\n        }, \n        \"QDRIIB_QVLD\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_AJ16\"\n        }, \n        \"QDRIIB_Q[0]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_AR19\"\n        }, \n        \"QDRIIB_Q[10]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_AJ18\"\n        }, \n        \"QDRIIB_Q[11]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_AJ17\"\n        }, \n        \"QDRIIB_Q[12]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_AG18\"\n        }, \n        \"QDRIIB_Q[13]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_AU19\"\n        }, \n        \"QDRIIB_Q[14]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_AW19\"\n        }, \n        \"QDRIIB_Q[15]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_AV19\"\n        }, \n        \"QDRIIB_Q[16]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_AP19\"\n        }, \n        \"QDRIIB_Q[17]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_AN20\"\n        }, \n        \"QDRIIB_Q[1]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_AM19\"\n        }, \n        \"QDRIIB_Q[2]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_AL19\"\n        }, \n        \"QDRIIB_Q[3]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_AM17\"\n        }, \n        \"QDRIIB_Q[4]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_AL18\"\n        }, \n        \"QDRIIB_Q[5]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_AN19\"\n        }, \n        \"QDRIIB_Q[6]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_AU18\"\n        }, \n        \"QDRIIB_Q[7]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_AK17\"\n        }, \n        \"QDRIIB_Q[8]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_AL17\"\n        }, \n        \"QDRIIB_Q[9]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_AG17\"\n        }, \n        \"QDRIIB_RPS_n\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_AW20\"\n        }, \n        \"QDRIIB_WPS_n\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_AU20\"\n        }\n    }, \n    \"QDRIIC\": {\n        \"QDRIIC_A[0]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_AV16\"\n        }, \n        \"QDRIIC_A[10]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_AH21\"\n        }, \n        \"QDRIIC_A[11]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_AU17\"\n        }, \n        \"QDRIIC_A[12]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_AU16\"\n        }, \n        \"QDRIIC_A[13]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_BB8\"\n        }, \n        \"QDRIIC_A[14]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_AT18\"\n        }, \n        \"QDRIIC_A[15]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_AW17\"\n        }, \n        \"QDRIIC_A[16]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_AV17\"\n        }, \n        \"QDRIIC_A[17]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_AU8\"\n        }, \n        \"QDRIIC_A[18]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_AT9\"\n        }, \n        \"QDRIIC_A[19]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_AV8\"\n        }, \n        \"QDRIIC_A[1]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_AW16\"\n        }, \n        \"QDRIIC_A[20]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_AN17\"\n        }, \n        \"QDRIIC_A[2]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_AP16\"\n        }, \n        \"QDRIIC_A[3]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_AW9\"\n        }, \n        \"QDRIIC_A[4]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_BD7\"\n        }, \n        \"QDRIIC_A[5]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_BC7\"\n        }, \n        \"QDRIIC_A[6]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_AR17\"\n        }, \n        \"QDRIIC_A[7]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_AR18\"\n        }, \n        \"QDRIIC_A[8]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_AT17\"\n        }, \n        \"QDRIIC_A[9]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_BB9\"\n        }, \n        \"QDRIIC_BWS_n[0]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_AJ11\"\n        }, \n        \"QDRIIC_BWS_n[1]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_AJ10\"\n        }, \n        \"QDRIIC_CQ_n\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_AF13\"\n        }, \n        \"QDRIIC_CQ_p\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_BC11\"\n        }, \n        \"QDRIIC_DOFF_n\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_AE14\"\n        }, \n        \"QDRIIC_D[0]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_AG9\"\n        }, \n        \"QDRIIC_D[10]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_AM13\"\n        }, \n        \"QDRIIC_D[11]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_AR12\"\n        }, \n        \"QDRIIC_D[12]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_AR13\"\n        }, \n        \"QDRIIC_D[13]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_AU9\"\n        }, \n        \"QDRIIC_D[14]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_AU10\"\n        }, \n        \"QDRIIC_D[15]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_AU11\"\n        }, \n        \"QDRIIC_D[16]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_AV11\"\n        }, \n        \"QDRIIC_D[17]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_AT12\"\n        }, \n        \"QDRIIC_D[1]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_AG10\"\n        }, \n        \"QDRIIC_D[2]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_AG12\"\n        }, \n        \"QDRIIC_D[3]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_AG11\"\n        }, \n        \"QDRIIC_D[4]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_AV10\"\n        }, \n        \"QDRIIC_D[5]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_AH12\"\n        }, \n        \"QDRIIC_D[6]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_AK12\"\n        }, \n        \"QDRIIC_D[7]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_AL12\"\n        }, \n        \"QDRIIC_D[8]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_AJ12\"\n        }, \n        \"QDRIIC_D[9]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_AN12\"\n        }, \n        \"QDRIIC_K_n\": {\n            \"IO_STANDARD\": \"DIFFERENTIAL 1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_AP13\"\n        }, \n        \"QDRIIC_K_p\": {\n            \"IO_STANDARD\": \"DIFFERENTIAL 1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_AP12\"\n        }, \n        \"QDRIIC_ODT\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_BD10\"\n        }, \n        \"QDRIIC_QVLD\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_BD11\"\n        }, \n        \"QDRIIC_Q[0]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_BA12\"\n        }, \n        \"QDRIIC_Q[10]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_AW11\"\n        }, \n        \"QDRIIC_Q[11]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_AF10\"\n        }, \n        \"QDRIIC_Q[12]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_AY12\"\n        }, \n        \"QDRIIC_Q[13]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_AW10\"\n        }, \n        \"QDRIIC_Q[14]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_AY10\"\n        }, \n        \"QDRIIC_Q[15]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_BB12\"\n        }, \n        \"QDRIIC_Q[16]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_BC10\"\n        }, \n        \"QDRIIC_Q[17]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_BA10\"\n        }, \n        \"QDRIIC_Q[1]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_AF14\"\n        }, \n        \"QDRIIC_Q[2]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_AE13\"\n        }, \n        \"QDRIIC_Q[3]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_AD14\"\n        }, \n        \"QDRIIC_Q[4]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_AE12\"\n        }, \n        \"QDRIIC_Q[5]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_AF11\"\n        }, \n        \"QDRIIC_Q[6]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_AE11\"\n        }, \n        \"QDRIIC_Q[7]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_AE10\"\n        }, \n        \"QDRIIC_Q[8]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_AE9\"\n        }, \n        \"QDRIIC_Q[9]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_BB11\"\n        }, \n        \"QDRIIC_RPS_n\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_AH10\"\n        }, \n        \"QDRIIC_WPS_n\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_AL11\"\n        }\n    }, \n    \"QDRIID\": {\n        \"QDRIID_A[0]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_N26\"\n        }, \n        \"QDRIID_A[10]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_U27\"\n        }, \n        \"QDRIID_A[11]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_R27\"\n        }, \n        \"QDRIID_A[12]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_P27\"\n        }, \n        \"QDRIID_A[13]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_V25\"\n        }, \n        \"QDRIID_A[14]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_V26\"\n        }, \n        \"QDRIID_A[15]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_T25\"\n        }, \n        \"QDRIID_A[16]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_P26\"\n        }, \n        \"QDRIID_A[17]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_M27\"\n        }, \n        \"QDRIID_A[18]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_M28\"\n        }, \n        \"QDRIID_A[19]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_P29\"\n        }, \n        \"QDRIID_A[1]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_P28\"\n        }, \n        \"QDRIID_A[20]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_D29\"\n        }, \n        \"QDRIID_A[2]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_N28\"\n        }, \n        \"QDRIID_A[3]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_L26\"\n        }, \n        \"QDRIID_A[4]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_K27\"\n        }, \n        \"QDRIID_A[5]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_L27\"\n        }, \n        \"QDRIID_A[6]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_U26\"\n        }, \n        \"QDRIID_A[7]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_T26\"\n        }, \n        \"QDRIID_A[8]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_T27\"\n        }, \n        \"QDRIID_A[9]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_V27\"\n        }, \n        \"QDRIID_BWS_n[0]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_E26\"\n        }, \n        \"QDRIID_BWS_n[1]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_K26\"\n        }, \n        \"QDRIID_CQ_n\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_H27\"\n        }, \n        \"QDRIID_CQ_p\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_E29\"\n        }, \n        \"QDRIID_DOFF_n\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_E27\"\n        }, \n        \"QDRIID_D[0]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_H25\"\n        }, \n        \"QDRIID_D[10]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_P24\"\n        }, \n        \"QDRIID_D[11]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_P23\"\n        }, \n        \"QDRIID_D[12]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_L24\"\n        }, \n        \"QDRIID_D[13]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_R24\"\n        }, \n        \"QDRIID_D[14]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_U23\"\n        }, \n        \"QDRIID_D[15]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_U24\"\n        }, \n        \"QDRIID_D[16]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_T24\"\n        }, \n        \"QDRIID_D[17]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_T23\"\n        }, \n        \"QDRIID_D[1]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_H24\"\n        }, \n        \"QDRIID_D[2]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_H23\"\n        }, \n        \"QDRIID_D[3]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_J25\"\n        }, \n        \"QDRIID_D[4]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_J24\"\n        }, \n        \"QDRIID_D[5]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_K25\"\n        }, \n        \"QDRIID_D[6]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_D26\"\n        }, \n        \"QDRIID_D[7]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_F25\"\n        }, \n        \"QDRIID_D[8]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_G25\"\n        }, \n        \"QDRIID_D[9]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_N23\"\n        }, \n        \"QDRIID_K_n\": {\n            \"IO_STANDARD\": \"DIFFERENTIAL 1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_K24\"\n        }, \n        \"QDRIID_K_p\": {\n            \"IO_STANDARD\": \"DIFFERENTIAL 1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_L23\"\n        }, \n        \"QDRIID_ODT\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_H26\"\n        }, \n        \"QDRIID_QVLD\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_J27\"\n        }, \n        \"QDRIID_Q[0]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_C27\"\n        }, \n        \"QDRIID_Q[10]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_F28\"\n        }, \n        \"QDRIID_Q[11]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_D27\"\n        }, \n        \"QDRIID_Q[12]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_G29\"\n        }, \n        \"QDRIID_Q[13]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_F29\"\n        }, \n        \"QDRIID_Q[14]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_H28\"\n        }, \n        \"QDRIID_Q[15]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_K28\"\n        }, \n        \"QDRIID_Q[16]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_J28\"\n        }, \n        \"QDRIID_Q[17]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_H29\"\n        }, \n        \"QDRIID_Q[1]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_A26\"\n        }, \n        \"QDRIID_Q[2]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_B26\"\n        }, \n        \"QDRIID_Q[3]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_F26\"\n        }, \n        \"QDRIID_Q[4]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_G26\"\n        }, \n        \"QDRIID_Q[5]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_C28\"\n        }, \n        \"QDRIID_Q[6]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_A29\"\n        }, \n        \"QDRIID_Q[7]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_A28\"\n        }, \n        \"QDRIID_Q[8]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_B28\"\n        }, \n        \"QDRIID_Q[9]\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_G28\"\n        }, \n        \"QDRIID_RPS_n\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_F24\"\n        }, \n        \"QDRIID_WPS_n\": {\n            \"IO_STANDARD\": \"1.8-V HSTL CLASS I\", \n            \"LOC\": \"PIN_M23\"\n        }\n    }, \n    \"RS422\": {\n        \"RS422_DE\": {\n            \"IO_STANDARD\": \"2.5 V\", \n            \"LOC\": \"PIN_AG14\"\n        }, \n        \"RS422_DIN\": {\n            \"IO_STANDARD\": \"2.5 V\", \n            \"LOC\": \"PIN_AE18\"\n        }, \n        \"RS422_DOUT\": {\n            \"IO_STANDARD\": \"2.5 V\", \n            \"LOC\": \"PIN_AE17\"\n        }, \n        \"RS422_RE_n\": {\n            \"IO_STANDARD\": \"2.5 V\", \n            \"LOC\": \"PIN_AF17\"\n        }, \n        \"RS422_TE\": {\n            \"IO_STANDARD\": \"2.5 V\", \n            \"LOC\": \"PIN_AF16\"\n        }\n    }, \n    \"RZQ\": {\n        \"RZQ_0\": {\n            \"PIO_DIRECTION\": \"INPUT\",\n            \"IO_STANDARD\": \"2.5 V\", \n            \"LOC\": \"PIN_BA36\"\n        }, \n        \"RZQ_1\": {\n            \"PIO_DIRECTION\": \"INPUT\",\n            \"IO_STANDARD\": \"1.8 V\", \n            \"LOC\": \"PIN_AR8\"\n        }, \n        \"RZQ_4\": {\n            \"PIO_DIRECTION\": \"INPUT\",\n            \"IO_STANDARD\": \"1.5 V\", \n            \"LOC\": \"PIN_H9\"\n        }, \n        \"RZQ_5\": {\n            \"PIO_DIRECTION\": \"INPUT\",\n            \"IO_STANDARD\": \"1.5 V\", \n            \"LOC\": \"PIN_P35\"\n        }\n    }, \n    \"SATA\": {\n        \"SATA_DEVICE_REFCLK_p\": {\n            \"IO_STANDARD\": \"HCSL\", \n            \"LOC\": \"PIN_V39\"\n        }, \n        \"SATA_DEVICE_RX_p[0]\": {\n            \"IO_STANDARD\": \"1.4-V PCML\", \n            \"LOC\": \"PIN_K43\"\n        }, \n        \"SATA_DEVICE_RX_p[1]\": {\n            \"IO_STANDARD\": \"1.4-V PCML\", \n            \"LOC\": \"PIN_H43\"\n        }, \n        \"SATA_DEVICE_TX_p[0]\": {\n            \"IO_STANDARD\": \"1.4-V PCML\", \n            \"LOC\": \"PIN_K39\"\n        }, \n        \"SATA_DEVICE_TX_p[1]\": {\n            \"IO_STANDARD\": \"1.4-V PCML\", \n            \"LOC\": \"PIN_H39\"\n        }, \n        \"SATA_HOST_REFCLK_p\": {\n            \"IO_STANDARD\": \"HCSL\", \n            \"LOC\": \"PIN_V6\"\n        }, \n        \"SATA_HOST_RX_p[0]\": {\n            \"IO_STANDARD\": \"1.4-V PCML\", \n            \"LOC\": \"PIN_K2\"\n        }, \n        \"SATA_HOST_RX_p[1]\": {\n            \"IO_STANDARD\": \"1.4-V PCML\", \n            \"LOC\": \"PIN_H2\"\n        }, \n        \"SATA_HOST_TX_p[0]\": {\n            \"IO_STANDARD\": \"1.4-V PCML\", \n            \"LOC\": \"PIN_K6\"\n        }, \n        \"SATA_HOST_TX_p[1]\": {\n            \"IO_STANDARD\": \"1.4-V PCML\", \n            \"LOC\": \"PIN_H6\"\n        }\n    }, \n    \"SFPA\": {\n        \"SFPA_LOS\": {\n            \"PIO_DIRECTION\": \"INPUT\",\n            \"IO_STANDARD\": \"2.5 V\", \n            \"LOC\": \"PIN_F22\"\n        }, \n        \"SFPA_MOD0_PRSNT_n\": {\n            \"PIO_DIRECTION\": \"INPUT\",\n            \"IO_STANDARD\": \"2.5 V\", \n            \"LOC\": \"PIN_E21\"\n        }, \n        \"SFPA_MOD1_SCL\": {\n            \"IO_STANDARD\": \"2.5 V\", \n            \"LOC\": \"PIN_B20\"\n        }, \n        \"SFPA_MOD2_SDA\": {\n            \"IO_STANDARD\": \"2.5 V\", \n            \"LOC\": \"PIN_A20\"\n        }, \n        \"SFPA_RATESEL[0]\": {\n            \"PIO_DIRECTION\": \"OUTPUT\",\n            \"IO_STANDARD\": \"2.5 V\", \n            \"LOC\": \"PIN_E20\"\n        }, \n        \"SFPA_RATESEL[1]\": {\n            \"PIO_DIRECTION\": \"OUTPUT\",\n            \"IO_STANDARD\": \"2.5 V\", \n            \"LOC\": \"PIN_G22\"\n        }, \n        \"SFPA_RX_p\": {\n            \"PIO_DIRECTION\": \"INPUT\",\n            \"IO_STANDARD\": \"1.4-V PCML\", \n            \"LOC\": \"PIN_AK2\"\n        }, \n        \"SFPA_TXDISABLE\": {\n            \"PIO_DIRECTION\": \"OUTPUT\",\n            \"IO_STANDARD\": \"2.5 V\", \n            \"LOC\": \"PIN_B22\"\n        }, \n        \"SFPA_TXFAULT\": {\n            \"PIO_DIRECTION\": \"INPUT\",\n            \"IO_STANDARD\": \"2.5 V\", \n            \"LOC\": \"PIN_A22\"\n        }, \n        \"SFPA_TX_p\": {\n            \"PIO_DIRECTION\": \"OUTPUT\",\n            \"IO_STANDARD\": \"1.4-V PCML\", \n            \"LOC\": \"PIN_AG4\"\n        },\n        \"SFPA_RX_p(n)\": {\n            \"IO_STANDARD\": \"1.4-V PCML\", \n            \"LOC\": \"PIN_AK1\"\n        }, \n        \"SFPA_TX_p(n)\": {\n            \"IO_STANDARD\": \"1.4-V PCML\", \n            \"LOC\": \"PIN_AG3\"\n        } \n    }, \n    \"SFPB\": {\n        \"SFPB_LOS\": {\n            \"PIO_DIRECTION\": \"INPUT\",\n            \"IO_STANDARD\": \"2.5 V\", \n            \"LOC\": \"PIN_R22\"\n        }, \n        \"SFPB_MOD0_PRSNT_n\": {\n            \"PIO_DIRECTION\": \"INPUT\",\n            \"IO_STANDARD\": \"2.5 V\", \n            \"LOC\": \"PIN_K22\"\n        }, \n        \"SFPB_MOD1_SCL\": {\n            \"IO_STANDARD\": \"2.5 V\", \n            \"LOC\": \"PIN_K21\"\n        }, \n        \"SFPB_MOD2_SDA\": {\n            \"IO_STANDARD\": \"2.5 V\", \n            \"LOC\": \"PIN_K20\"\n        }, \n        \"SFPB_RATESEL[0]\": {\n            \"PIO_DIRECTION\": \"OUTPUT\",\n            \"IO_STANDARD\": \"2.5 V\", \n            \"LOC\": \"PIN_R21\"\n        }, \n        \"SFPB_RATESEL[1]\": {\n            \"PIO_DIRECTION\": \"OUTPUT\",\n            \"IO_STANDARD\": \"2.5 V\", \n            \"LOC\": \"PIN_T22\"\n        }, \n        \"SFPB_RX_p\": {\n            \"PIO_DIRECTION\": \"INPUT\",\n            \"IO_STANDARD\": \"1.4-V PCML\", \n            \"LOC\": \"PIN_AP2\"\n        }, \n        \"SFPB_TXDISABLE\": {\n            \"PIO_DIRECTION\": \"OUTPUT\",\n            \"IO_STANDARD\": \"2.5 V\", \n            \"LOC\": \"PIN_H22\"\n        }, \n        \"SFPB_TXFAULT\": {\n            \"PIO_DIRECTION\": \"INPUT\",\n            \"IO_STANDARD\": \"2.5 V\", \n            \"LOC\": \"PIN_H20\"\n        }, \n        \"SFPB_TX_p\": {\n            \"PIO_DIRECTION\": \"OUTPUT\",\n            \"IO_STANDARD\": \"1.4-V PCML\", \n            \"LOC\": \"PIN_AL4\"\n        },\n        \"SFPB_RX_p(n)\": {\n            \"PIO_DIRECTION\": \"INPUT\",\n            \"IO_STANDARD\": \"1.4-V PCML\", \n            \"LOC\": \"PIN_AP1\"\n        }, \n        \"SFPB_TX_p(n)\": {\n            \"PIO_DIRECTION\": \"OUTPUT\",\n            \"IO_STANDARD\": \"1.4-V PCML\", \n            \"LOC\": \"PIN_AL3\"\n        } \n    }, \n    \"SFPC\": {\n        \"SFPC_LOS\": {\n            \"PIO_DIRECTION\": \"INPUT\",\n            \"IO_STANDARD\": \"2.5 V\", \n            \"LOC\": \"PIN_L21\"\n        }, \n        \"SFPC_MOD0_PRSNT_n\": {\n            \"PIO_DIRECTION\": \"INPUT\",\n            \"IO_STANDARD\": \"2.5 V\", \n            \"LOC\": \"PIN_J21\"\n        }, \n        \"SFPC_MOD1_SCL\": {\n            \"IO_STANDARD\": \"2.5 V\", \n            \"LOC\": \"PIN_H21\"\n        }, \n        \"SFPC_MOD2_SDA\": {\n            \"IO_STANDARD\": \"2.5 V\", \n            \"LOC\": \"PIN_G20\"\n        }, \n        \"SFPC_RATESEL[0]\": {\n            \"PIO_DIRECTION\": \"OUTPUT\",\n            \"IO_STANDARD\": \"2.5 V\", \n            \"LOC\": \"PIN_J22\"\n        }, \n        \"SFPC_RATESEL[1]\": {\n            \"PIO_DIRECTION\": \"OUTPUT\",\n            \"IO_STANDARD\": \"2.5 V\", \n            \"LOC\": \"PIN_P21\"\n        }, \n        \"SFPC_RX_p\": {\n            \"PIO_DIRECTION\": \"INPUT\",\n            \"IO_STANDARD\": \"1.4-V PCML\", \n            \"LOC\": \"PIN_AW4\"\n        }, \n        \"SFPC_TXDISABLE\": {\n            \"PIO_DIRECTION\": \"OUTPUT\",\n            \"IO_STANDARD\": \"2.5 V\", \n            \"LOC\": \"PIN_F21\"\n        }, \n        \"SFPC_TXFAULT\": {\n            \"PIO_DIRECTION\": \"INPUT\",\n            \"IO_STANDARD\": \"2.5 V\", \n            \"LOC\": \"PIN_F20\"\n        }, \n        \"SFPC_TX_p\": {\n            \"PIO_DIRECTION\": \"OUTPUT\",\n            \"IO_STANDARD\": \"1.4-V PCML\", \n            \"LOC\": \"PIN_AT6\"\n        },\n        \"SFPC_RX_p(n)\": {\n            \"PIO_DIRECTION\": \"INPUT\",\n            \"IO_STANDARD\": \"1.4-V PCML\", \n            \"LOC\": \"PIN_AW3\"\n        }, \n        \"SFPC_TX_p(n)\": {\n            \"PIO_DIRECTION\": \"OUTPUT\",\n            \"IO_STANDARD\": \"1.4-V PCML\", \n            \"LOC\": \"PIN_AT5\"\n        }\n    }, \n    \"SFPD\": {\n        \"SFPD_LOS\": {\n            \"PIO_DIRECTION\": \"INPUT\",\n            \"IO_STANDARD\": \"2.5 V\", \n            \"LOC\": \"PIN_N22\"\n        }, \n        \"SFPD_MOD0_PRSNT_n\": {\n            \"PIO_DIRECTION\": \"INPUT\",\n            \"IO_STANDARD\": \"2.5 V\", \n            \"LOC\": \"PIN_V20\"\n        }, \n        \"SFPD_MOD1_SCL\": {\n            \"IO_STANDARD\": \"2.5 V\", \n            \"LOC\": \"PIN_U21\"\n        }, \n        \"SFPD_MOD2_SDA\": {\n            \"IO_STANDARD\": \"2.5 V\", \n            \"LOC\": \"PIN_V19\"\n        }, \n        \"SFPD_RATESEL[0]\": {\n            \"PIO_DIRECTION\": \"OUTPUT\",\n            \"IO_STANDARD\": \"2.5 V\", \n            \"LOC\": \"PIN_V21\"\n        }, \n        \"SFPD_RATESEL[1]\": {\n            \"PIO_DIRECTION\": \"OUTPUT\",\n            \"IO_STANDARD\": \"2.5 V\", \n            \"LOC\": \"PIN_M22\"\n        }, \n        \"SFPD_RX_p\": {\n            \"PIO_DIRECTION\": \"INPUT\",\n            \"IO_STANDARD\": \"1.4-V PCML\", \n            \"LOC\": \"PIN_BB2\"\n        }, \n        \"SFPD_TXDISABLE\": {\n            \"PIO_DIRECTION\": \"OUTPUT\",\n            \"IO_STANDARD\": \"2.5 V\", \n            \"LOC\": \"PIN_U20\"\n        }, \n        \"SFPD_TXFAULT\": {\n            \"PIO_DIRECTION\": \"INPUT\",\n            \"IO_STANDARD\": \"2.5 V\", \n            \"LOC\": \"PIN_T21\"\n        }, \n        \"SFPD_TX_p\": {\n            \"PIO_DIRECTION\": \"OUTPUT\",\n            \"IO_STANDARD\": \"1.4-V PCML\", \n            \"LOC\": \"PIN_AY6\"\n        }, \n        \"SFPD_RX_p(n)\": {\n            \"PIO_DIRECTION\": \"INPUT\",\n            \"IO_STANDARD\": \"1.4-V PCML\", \n            \"LOC\": \"PIN_BB1\"\n        }, \n        \"SFPD_TX_p(n)\": {\n            \"PIO_DIRECTION\": \"OUTPUT\",\n            \"IO_STANDARD\": \"1.4-V PCML\", \n            \"LOC\": \"PIN_AY5\"\n        }\n    }, \n    \"SMA\": {\n        \"SMA_CLKIN\": {\n            \"IO_STANDARD\": \"2.5 V\", \n            \"LOC\": \"PIN_BB33\"\n        }, \n        \"SMA_CLKOUT\": {\n            \"IO_STANDARD\": \"2.5 V\", \n            \"LOC\": \"PIN_AV34\"\n        }\n    }, \n    \"SW\": {\n        \"SW[0]\": {\n            \"PIO_DIRECTION\": \"INPUT\",\n            \"IO_STANDARD\": \"1.8 V\", \n            \"LOC\": \"PIN_B25\"\n        }, \n        \"SW[1]\": {\n            \"PIO_DIRECTION\": \"INPUT\",\n            \"IO_STANDARD\": \"1.8 V\", \n            \"LOC\": \"PIN_A25\"\n        }, \n        \"SW[2]\": {\n            \"PIO_DIRECTION\": \"INPUT\",\n            \"IO_STANDARD\": \"1.8 V\", \n            \"LOC\": \"PIN_B23\"\n        }, \n        \"SW[3]\": {\n            \"PIO_DIRECTION\": \"INPUT\",\n            \"IO_STANDARD\": \"1.8 V\", \n            \"LOC\": \"PIN_A23\"\n        }\n    }, \n    \"TEMP\": {\n        \"TEMP_CLK\": {\n            \"IO_STANDARD\": \"2.5 V\", \n            \"LOC\": \"PIN_D21\"\n        }, \n        \"TEMP_DATA\": {\n            \"IO_STANDARD\": \"2.5 V\", \n            \"LOC\": \"PIN_D20\"\n        }, \n        \"TEMP_INT_n\": {\n            \"IO_STANDARD\": \"2.5 V\", \n            \"LOC\": \"PIN_C21\"\n        }, \n        \"TEMP_OVERT_n\": {\n            \"IO_STANDARD\": \"2.5 V\", \n            \"LOC\": \"PIN_C22\"\n        }\n    }\n\n}\n\n\n"
  },
  {
    "path": "boardinfo/htg4.json",
    "content": "{\n    \"options\": {\n        \"bsvdefines\" : [\"ALTERA=1\", \"StratixIV\", \"PCIE\", \"PCIE_NO_BSCAN\", \"PcieHostInterface\", \"PhysAddrWidth=40\", \"NUMBER_OF_LEDS=4\", \"NUMBER_OF_10G_PORTS=2\", \"PcieLanes=8\", \"DEFAULT_NOPROGRAM=1\",\n\t\t       \t\"CONNECTAL_BITS_DEPENDENCES=hw/mkTop.bit\", \"CONNECTAL_RUN_SCRIPT=$(CONNECTALDIR)/scripts/run.pcietest.altera\"],\n        \"os\" : \"ubuntu\",\n        \"partname\" : \"EP4S100G2F40I2\",\n        \"need_pcie\" : \"s4_gen2x8\",\n        \"TOP\" : \"PcieTop\",\n        \"constraints\": [\"constraints/altera/htg4.xdc\"],\n        \"runscript\" : \"run.pcietest.altera\",\n        \"CONNECTALFLAGS\" : [\"--mainclockperiod=8\", \"--derivedclockperiod=4\", \"--pcieclockperiod=8\"],\n        \"rewireclockstring\" : \"\"\n    },\n    \"PCIE\": {\n        \"PCIE_PERST_n\": {\n            \"IOSTANDARD\": \"2.5 V\", \n            \"LOC\": \"PIN_AG24\"\n        }, \n        \"PCIE_REFCLK_p\": {\n            \"IOSTANDARD\": \"DIFFERENTIAL LVPECL\", \n            \"LOC\": \"PIN_AA38\"\n        }, \n        \"PCIE_RX_p[0]\": {\n            \"IOSTANDARD\": \"1.4-V PCML\", \n            \"LOC\": \"PIN_AU38\"\n        }, \n        \"PCIE_RX_p[1]\": {\n            \"IOSTANDARD\": \"1.4-V PCML\", \n            \"LOC\": \"PIN_AR38\"\n        }, \n        \"PCIE_RX_p[2]\": {\n            \"IOSTANDARD\": \"1.4-V PCML\", \n            \"LOC\": \"PIN_AJ38\"\n        }, \n        \"PCIE_RX_p[3]\": {\n            \"IOSTANDARD\": \"1.4-V PCML\", \n            \"LOC\": \"PIN_AG38\"\n        }, \n        \"PCIE_RX_p[4]\": {\n            \"IOSTANDARD\": \"1.4-V PCML\", \n            \"LOC\": \"PIN_AE38\"\n        }, \n        \"PCIE_RX_p[5]\": {\n            \"IOSTANDARD\": \"1.4-V PCML\", \n            \"LOC\": \"PIN_AC38\"\n        }, \n        \"PCIE_RX_p[6]\": {\n            \"IOSTANDARD\": \"1.4-V PCML\", \n            \"LOC\": \"PIN_U38\"\n        }, \n        \"PCIE_RX_p[7]\": {\n            \"IOSTANDARD\": \"1.4-V PCML\", \n            \"LOC\": \"PIN_R38\"\n        }, \n        \"PCIE_SMBCLK\": {\n            \"IOSTANDARD\": \"2.5 V\", \n            \"LOC\": \"PIN_W35\"\n        }, \n        \"PCIE_SMBDAT\": {\n            \"IOSTANDARD\": \"2.5 V\", \n            \"LOC\": \"PIN_W34\"\n        }, \n        \"PCIE_TX_p[0]\": {\n            \"IOSTANDARD\": \"1.4-V PCML\", \n            \"LOC\": \"PIN_AT36\"\n        }, \n        \"PCIE_TX_p[1]\": {\n            \"IOSTANDARD\": \"1.4-V PCML\", \n            \"LOC\": \"PIN_AP36\"\n        }, \n        \"PCIE_TX_p[2]\": {\n            \"IOSTANDARD\": \"1.4-V PCML\", \n            \"LOC\": \"PIN_AH36\"\n        }, \n        \"PCIE_TX_p[3]\": {\n            \"IOSTANDARD\": \"1.4-V PCML\", \n            \"LOC\": \"PIN_AF36\"\n        }, \n        \"PCIE_TX_p[4]\": {\n            \"IOSTANDARD\": \"1.4-V PCML\", \n            \"LOC\": \"PIN_AD36\"\n        }, \n        \"PCIE_TX_p[5]\": {\n            \"IOSTANDARD\": \"1.4-V PCML\", \n            \"LOC\": \"PIN_AB36\"\n        }, \n        \"PCIE_TX_p[6]\": {\n            \"IOSTANDARD\": \"1.4-V PCML\", \n            \"LOC\": \"PIN_T36\"\n        }, \n        \"PCIE_TX_p[7]\": {\n            \"IOSTANDARD\": \"1.4-V PCML\", \n            \"LOC\": \"PIN_P36\"\n        }, \n        \"PCIE_WAKE_n\": {\n            \"IOSTANDARD\": \"2.5 V\", \n            \"LOC\": \"PIN_R33\"\n        },\n        \"PCIE_REFCLK_p(n)\": {\n            \"IOSTANDARD\": \"HCSL\", \n            \"LOC\": \"PIN_AA39\"\n        }, \n        \"PCIE_RX_p[0](n)\": {\n            \"IOSTANDARD\": \"1.4-V PCML\", \n            \"LOC\": \"PIN_AU39\"\n        }, \n        \"PCIE_RX_p[1](n)\": {\n            \"IOSTANDARD\": \"1.4-V PCML\", \n            \"LOC\": \"PIN_AR39\"\n        }, \n        \"PCIE_RX_p[2](n)\": {\n            \"IOSTANDARD\": \"1.4-V PCML\", \n            \"LOC\": \"PIN_AJ39\"\n        }, \n        \"PCIE_RX_p[3](n)\": {\n            \"IOSTANDARD\": \"1.4-V PCML\", \n            \"LOC\": \"PIN_AG39\"\n        }, \n        \"PCIE_RX_p[4](n)\": {\n            \"IOSTANDARD\": \"1.4-V PCML\", \n            \"LOC\": \"PIN_AE39\"\n        }, \n        \"PCIE_RX_p[5](n)\": {\n            \"IOSTANDARD\": \"1.4-V PCML\", \n            \"LOC\": \"PIN_AC39\"\n        }, \n        \"PCIE_RX_p[6](n)\": {\n            \"IOSTANDARD\": \"1.4-V PCML\", \n            \"LOC\": \"PIN_U39\"\n        }, \n        \"PCIE_RX_p[7](n)\": {\n            \"IOSTANDARD\": \"1.4-V PCML\", \n            \"LOC\": \"PIN_R39\"\n        }, \n        \"PCIE_TX_p[0](n)\": {\n            \"IOSTANDARD\": \"1.4-V PCML\", \n            \"LOC\": \"PIN_AT37\"\n        }, \n        \"PCIE_TX_p[1](n)\": {\n            \"IOSTANDARD\": \"1.4-V PCML\", \n            \"LOC\": \"PIN_AP37\"\n        }, \n        \"PCIE_TX_p[2](n)\": {\n            \"IOSTANDARD\": \"1.4-V PCML\", \n            \"LOC\": \"PIN_AH37\"\n        }, \n        \"PCIE_TX_p[3](n)\": {\n            \"IOSTANDARD\": \"1.4-V PCML\", \n            \"LOC\": \"PIN_AF37\"\n        }, \n        \"PCIE_TX_p[4](n)\": {\n            \"IOSTANDARD\": \"1.4-V PCML\", \n            \"LOC\": \"PIN_AO37\"\n        }, \n        \"PCIE_TX_p[5](n)\": {\n            \"IOSTANDARD\": \"1.4-V PCML\", \n            \"LOC\": \"PIN_AB37\"\n        }, \n        \"PCIE_TX_p[6](n)\": {\n            \"IOSTANDARD\": \"1.4-V PCML\", \n            \"LOC\": \"PIN_T37\"\n        }, \n        \"PCIE_TX_p[7](n)\": {\n            \"IOSTANDARD\": \"1.4-V PCML\", \n            \"LOC\": \"PIN_P37\"\n        }\n    },\n    \"LED\": {\n        \"LED[0]\": {\n            \"IOSTANDARD\": \"2.5 V\", \n            \"LOC\": \"PIN_D33\"\n        }, \n        \"LED[1]\": {\n            \"IOSTANDARD\": \"2.5 V\", \n            \"LOC\": \"PIN_C34\"\n        }, \n        \"LED[2]\": {\n            \"IOSTANDARD\": \"2.5 V\", \n            \"LOC\": \"PIN_M28\"\n        }, \n        \"LED[3]\": {\n            \"IOSTANDARD\": \"2.5 V\", \n            \"LOC\": \"PIN_D34\"\n        },\n        \"LED[4]\": {\n            \"IOSTANDARD\": \"2.5 V\", \n            \"LOC\": \"PIN_E34\"\n        }, \n        \"LED[5]\": {\n            \"IOSTANDARD\": \"2.5 V\", \n            \"LOC\": \"PIN_R27\"\n        }, \n        \"LED[6]\": {\n            \"IOSTANDARD\": \"2.5 V\", \n            \"LOC\": \"PIN_F34\"\n        }, \n        \"LED[7]\": {\n            \"IOSTANDARD\": \"2.5 V\", \n            \"LOC\": \"PIN_N28\"\n        } \n\t},\n    \"OSC\": {\n        \"CLK200\": {\n            \"IOSTANDARD\": \"LVDS\", \n            \"LOC\": \"PIN_K34\"\n        }, \n        \"CLK644\": {\n            \"IOSTANDARD\": \"DIFFERENTIAL LVPECL\", \n            \"LOC\": \"PIN_J2\"\n        },\n        \"CLK100\": {\n            \"IOSTANDARD\": \"DIFFERENTIAL LVPECL\", \n            \"LOC\": \"PIN_J2\"\n        }\n\t}\n}\n"
  },
  {
    "path": "boardinfo/kc160g2.json",
    "content": "{\n    \"options\": {\n        \"bsvdefines\" : [\"XILINX=1\", \"Kintex7\", \"PCIE\", \"PCIE2\", \"PcieHostInterface\", \"PhysAddrWidth=40\", \"PcieLanes=8\",\n\t\t       \t\"CONNECTAL_BITS_DEPENDENCES=hw/mkTop.bit\", \"CONNECTAL_RUN_SCRIPT=$(CONNECTALDIR)/scripts/run.pcietest\"],\n        \"os\" : \"ubuntu\",\n        \"partname\" : \"xc7k160tffg676-2\",\n        \"need_pcie\" : \"x7_gen2x8\",\n        \"TOP\" : \"PcieTop\",\n        \"constraints\": [],\n        \"implconstraints\": [\"constraints/xilinx/kc160g2.xdc\"],\n        \"runscript\" : \"run.pcietest\",\n        \"CONNECTALFLAGS\" : [\"--mainclockperiod=4\", \"--derivedclockperiod=4\", \"--pcieclockperiod=4\"],\n        \"rewireclockstring\" : \"\"\n    }\n}\n"
  },
  {
    "path": "boardinfo/kc705.json",
    "content": "{\n    \"options\": {\n        \"bsvdefines\" : [\"XILINX=1\", \"Kintex7\", \"PCIE\", \"PCIE1\", \"PcieHostInterface\", \"PhysAddrWidth=40\", \"PcieLanes=8\",\n\t\t       \t\"CONNECTAL_BITS_DEPENDENCES=hw/mkTop.bit\", \"CONNECTAL_RUN_SCRIPT=$(CONNECTALDIR)/scripts/run.pcietest\"],\n        \"os\" : \"ubuntu\",\n        \"partname\" : \"xc7k325tffg900-2\",\n        \"need_pcie\" : \"x7_gen1x8\",\n        \"TOP\" : \"PcieTop\",\n        \"constraints\": [\"constraints/xilinx/kc705.xdc\"],\n        \"implconstraints\": [\"constraints/xilinx/kc705.xdc\", \"constraints/xilinx/pcie-clocks.xdc\"],\n        \"runscript\" : \"run.pcietest\",\n        \"CONNECTALFLAGS\" : [\"--mainclockperiod=8\", \"--derivedclockperiod=4\", \"--pcieclockperiod=8\"],\n        \"rewireclockstring\" : \"\"\n    },\n    \"fmc1\": {\n    \"LA00_p_CC\": {\n        \"LOC\": \"C25\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA00_n_CC\": {\n        \"LOC\": \"B25\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA01_p_CC\": {\n        \"LOC\": \"D26\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA01_n_CC\": {\n        \"LOC\": \"C26\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA02_p\": {\n        \"LOC\": \"H24\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA02_n\": {\n        \"LOC\": \"H25\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA03_p\": {\n        \"LOC\": \"H26\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA03_n\": {\n        \"LOC\": \"H27\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA04_p\": {\n        \"LOC\": \"G28\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA04_n\": {\n        \"LOC\": \"F28\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA05_p\": {\n        \"LOC\": \"G29\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA05_n\": {\n        \"LOC\": \"H30\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA06_p\": {\n        \"LOC\": \"H30\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA06_n\": {\n        \"LOC\": \"G30\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA07_p\": {\n        \"LOC\": \"E28\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA07_n\": {\n        \"LOC\": \"D28\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA08_p\": {\n        \"LOC\": \"E29\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA08_n\": {\n        \"LOC\": \"E30\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA09_p\": {\n        \"LOC\": \"B30\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA09_n\": {\n        \"LOC\": \"A30\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA10_p\": {\n        \"LOC\": \"D29\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA10_n\": {\n        \"LOC\": \"C30\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA11_p\": {\n        \"LOC\": \"G27\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA11_n\": {\n        \"LOC\": \"F27\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA12_p\": {\n        \"LOC\": \"C29\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA12_n\": {\n        \"LOC\": \"C29\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA13_p\": {\n        \"LOC\": \"A25\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA13_n\": {\n        \"LOC\": \"A26\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA14_p\": {\n        \"LOC\": \"B28\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA14_n\": {\n        \"LOC\": \"A28\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA15_p\": {\n        \"LOC\": \"C24\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA15_n\": {\n        \"LOC\": \"B24\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA16_p\": {\n        \"LOC\": \"B27\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA16_n\": {\n        \"LOC\": \"A27\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA17_p_CC\": {\n        \"LOC\": \"AB27\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA17_n_CC\": {\n        \"LOC\": \"AC27\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA18_p_CC\": {\n        \"LOC\": \"AD27\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA18_n_CC\": {\n        \"LOC\": \"AD28\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA19_p\": {\n        \"LOC\": \"AJ26\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA19_n\": {\n        \"LOC\": \"AK26\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"CLK0_M2C_p\": {\n        \"LOC\": \"bogus\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"CLK0_M2C_n\": {\n        \"LOC\": \"bogus\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        }\n    },\n    \"uart\": {\n\t\t\"d_in\": {\n\t\t\t\"PACKAGE_PIN\": \"M19\",\n\t\t\t\"IOSTANDARD\": \"LVCMOS25\",\n\t\t\t\"PIO_DIRECTION\": \"INPUT\"\n\t\t},\n\t\t\"d_out\": {\n\t\t\t\"PACKAGE_PIN\": \"K24\",\n\t\t\t\"IOSTANDARD\": \"LVCMOS25\",\n\t\t\t\"PIO_DIRECTION\": \"OUTPUT\"\n\t\t},\n\t\t\"rts\": {\n\t\t\t\"PACKAGE_PIN\": \"K23\",\n\t\t\t\"IOSTANDARD\": \"LVCMOS25\",\n\t\t\t\"PIO_DIRECTION\": \"INPUT\"\n\t\t},\n\t\t\"cts\": {\n\t\t\t\"PACKAGE_PIN\": \"L27\",\n\t\t\t\"IOSTANDARD\": \"LVCMOS25\",\n\t\t\t\"PIO_DIRECTION\": \"OUTPUT\"\n\t\t}\n    },\n    \"sdio\": {\n        \"dat0\": {\n            \"PACKAGE_PIN\": \"AC20\",\n            \"IOSTANDARD\": \"LVCMOS25\",\n            \"PIO_DIRECTION\": \"BIDIR\"\n        },\n        \"dat1\": {\n            \"PACKAGE_PIN\": \"AA23\",\n            \"IOSTANDARD\": \"LVCMOS25\",\n            \"PIO_DIRECTION\": \"BIDIR\"\n        },\n        \"dat2\": {\n            \"PACKAGE_PIN\": \"AA22\",\n            \"IOSTANDARD\": \"LVCMOS25\",\n            \"PIO_DIRECTION\": \"BIDIR\"\n        },\n        \"cd_dat3\": {\n            \"PACKAGE_PIN\": \"AC21\",\n            \"IOSTANDARD\": \"LVCMOS25\",\n            \"PIO_DIRECTION\": \"BIDIR\"\n        },\n        \"clk\": {\n            \"PACKAGE_PIN\": \"AB23\",\n            \"IOSTANDARD\": \"LVCMOS25\",\n            \"PIO_DIRECTION\": \"OUTPUT\"\n        },\n        \"cmd\": {\n            \"PACKAGE_PIN\": \"AB22\",\n            \"IOSTANDARD\": \"LVCMOS25\",\n            \"PIO_DIRECTION\": \"BIDIR\"\n        },\n        \"sddet\": {\n            \"PACKAGE_PIN\": \"AA21\",\n            \"IOSTANDARD\": \"LVCMOS25\",\n            \"PIO_DIRECTION\": \"INPUT\"\n        },\n        \"sdwp\": {\n            \"PACKAGE_PIN\": \"Y21\",\n            \"IOSTANDARD\": \"LVCMOS25\",\n            \"PIO_DIRECTION\": \"INPUT\"\n        }\n    },\n    \"pins\": {\n\t\"userClk_p\": {\n\t    \"PACKAGE_PIN\": \"K29\",\n\t    \"IOSTANDARD\": \"LVDS_25\",\n\t    \"DIFF_TERM\": \"TRUE\",\n\t    \"PIO_DIRECTION\": \"INPUT\"\n\t},\n\t\"userClk_n\": {\n\t    \"PACKAGE_PIN\": \"K28\",\n\t    \"IOSTANDARD\": \"LVDS_25\",\n\t    \"DIFF_TERM\": \"TRUE\",\n\t    \"PIO_DIRECTION\": \"INPUT\"\n\t},\n\t\"smaUserClk_p\": {\n\t    \"PACKAGE_PIN\": \"L25\",\n\t    \"IOSTANDARD\": \"LVDS_25\",\n\t    \"DIFF_TERM\": \"TRUE\",\n\t    \"PIO_DIRECTION\": \"OUTPUT\"\n\t},\n\t\"smaUserClk_n\": {\n\t    \"PACKAGE_PIN\": \"K25\",\n\t    \"IOSTANDARD\": \"LVDS_25\",\n\t    \"DIFF_TERM\": \"TRUE\",\n\t    \"PIO_DIRECTION\": \"OUTPUT\"\n\t},\n\t\"mgtRefClk_p\": {\n\t    \"PACKAGE_PIN\": \"J8\",\n\t    \"IOSTANDARD\": \"LVDS_25\",\n\t    \"DIFF_TERM\": \"TRUE\",\n\t    \"PIO_DIRECTION\": \"INPUT\"\n\t},\n\t\"mgtRefClk_n\": {\n\t    \"PACKAGE_PIN\": \"J7\",\n\t    \"IOSTANDARD\": \"LVDS_25\",\n\t    \"DIFF_TERM\": \"TRUE\",\n\t    \"PIO_DIRECTION\": \"INPUT\"\n\t},\n\t\"mgtRx_p\": {\n\t    \"PACKAGE_PIN\": \"K6\",\n\t    \"DIFF_TERM\": \"TRUE\",\n\t    \"PIO_DIRECTION\": \"INPUT\"\n\t},\n\t\"mgtRx_n\": {\n\t    \"PACKAGE_PIN\": \"K5\",\n\t    \"DIFF_TERM\": \"TRUE\",\n\t    \"PIO_DIRECTION\": \"INPUT\"\n\t},\n\t\"mgtTx_p\": {\n\t    \"PACKAGE_PIN\": \"K2\",\n\t    \"DIFF_TERM\": \"TRUE\",\n\t    \"PIO_DIRECTION\": \"OUTPUT\"\n\t},\n\t\"mgtTx_n\": {\n\t    \"PACKAGE_PIN\": \"K1\",\n\t    \"DIFF_TERM\": \"TRUE\",\n\t    \"PIO_DIRECTION\": \"OUTPUT\"\n\t},\n\t\"uart_d_in\": {\n\t    \"PACKAGE_PIN\": \"M19\",\n\t    \"IOSTANDARD\": \"LVCMOS25\",\n\t    \"PIO_DIRECTION\": \"INPUT\"\n\t},\n\t\"uart_d_out\": {\n\t    \"PACKAGE_PIN\": \"K24\",\n\t    \"IOSTANDARD\": \"LVCMOS25\",\n\t    \"PIO_DIRECTION\": \"OUTPUT\"\n\t}\n    }\n}\n"
  },
  {
    "path": "boardinfo/kc705_untethered.json",
    "content": "{\n    \"options\": {\n        \"bsvdefines\" : [\"XILINX=1\", \"Kintex7\", \"PhysAddrWidth=40\", \"PcieLanes=8\", \"UNTETHERED=1\",\n\t\t       \t\"CONNECTAL_BITS_DEPENDENCES=hw/mkTop.bit\", \"CONNECTAL_RUN_SCRIPT=$(CONNECTALDIR)/scripts/run.pcietest\"],\n        \"os\" : \"ubuntu\",\n        \"partname\" : \"xc7k325tffg900-2\",\n        \"TOP\" : \"UntetheredTop\",\n        \"constraints\":     [\"constraints/xilinx/kc705g2.xdc\", \"constraints/xilinx/pcie-clocks.xdc\"],\n        \"implconstraints\": [\"constraints/xilinx/kc705g2.xdc\", \"constraints/xilinx/pcie-clocks.xdc\"],\n        \"runscript\" : \"run.pcietest\",\n        \"CONNECTALFLAGS\" : [\"--mainclockperiod=4\", \"--derivedclockperiod=4\", \"--pcieclockperiod=4\"],\n        \"rewireclockstring\" : \"\"\n    },\n    \"fmc1\": {\n    \"LA00_p_CC\": {\n        \"PACKAGE_PIN\": \"C25\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA00_n_CC\": {\n        \"PACKAGE_PIN\": \"B25\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA01_p_CC\": {\n        \"PACKAGE_PIN\": \"D26\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA01_n_CC\": {\n        \"PACKAGE_PIN\": \"C26\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA02_p\": {\n        \"PACKAGE_PIN\": \"H24\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA02_n\": {\n        \"PACKAGE_PIN\": \"H25\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA03_p\": {\n        \"PACKAGE_PIN\": \"H26\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA03_n\": {\n        \"PACKAGE_PIN\": \"H27\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA04_p\": {\n        \"PACKAGE_PIN\": \"G28\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA04_n\": {\n        \"PACKAGE_PIN\": \"F28\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA05_p\": {\n        \"PACKAGE_PIN\": \"G29\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA05_n\": {\n        \"PACKAGE_PIN\": \"H30\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA06_p\": {\n        \"PACKAGE_PIN\": \"H30\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA06_n\": {\n        \"PACKAGE_PIN\": \"G30\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA07_p\": {\n        \"PACKAGE_PIN\": \"E28\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA07_n\": {\n        \"PACKAGE_PIN\": \"D28\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA08_p\": {\n        \"PACKAGE_PIN\": \"E29\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA08_n\": {\n        \"PACKAGE_PIN\": \"E30\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA09_p\": {\n        \"PACKAGE_PIN\": \"B30\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA09_n\": {\n        \"PACKAGE_PIN\": \"A30\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA10_p\": {\n        \"PACKAGE_PIN\": \"D29\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA10_n\": {\n        \"PACKAGE_PIN\": \"C30\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA11_p\": {\n        \"PACKAGE_PIN\": \"G27\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA11_n\": {\n        \"PACKAGE_PIN\": \"F27\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA12_p\": {\n        \"PACKAGE_PIN\": \"C29\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA12_n\": {\n        \"PACKAGE_PIN\": \"C29\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA13_p\": {\n        \"PACKAGE_PIN\": \"A25\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA13_n\": {\n        \"PACKAGE_PIN\": \"A26\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA14_p\": {\n        \"PACKAGE_PIN\": \"B28\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA14_n\": {\n        \"PACKAGE_PIN\": \"A28\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA15_p\": {\n        \"PACKAGE_PIN\": \"C24\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA15_n\": {\n        \"PACKAGE_PIN\": \"B24\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA16_p\": {\n        \"PACKAGE_PIN\": \"B27\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA16_n\": {\n        \"PACKAGE_PIN\": \"A27\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA17_p_CC\": {\n        \"PACKAGE_PIN\": \"AB27\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA17_n_CC\": {\n        \"PACKAGE_PIN\": \"AC27\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA18_p_CC\": {\n        \"PACKAGE_PIN\": \"AD27\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA18_n_CC\": {\n        \"PACKAGE_PIN\": \"AD28\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA19_p\": {\n        \"PACKAGE_PIN\": \"AJ26\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA19_n\": {\n        \"PACKAGE_PIN\": \"AK26\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"CLK0_M2C_p\": {\n        \"PACKAGE_PIN\": \"bogus\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"CLK0_M2C_n\": {\n        \"PACKAGE_PIN\": \"bogus\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        }\n    },\n    \"uart\": {\n\t\t\"d_in\": {\n\t\t\t\"PACKAGE_PIN\": \"M19\",\n\t\t\t\"IOSTANDARD\": \"LVCMOS25\",\n\t\t\t\"PIO_DIRECTION\": \"INPUT\"\n\t\t},\n\t\t\"d_out\": {\n\t\t\t\"PACKAGE_PIN\": \"K24\",\n\t\t\t\"IOSTANDARD\": \"LVCMOS25\",\n\t\t\t\"PIO_DIRECTION\": \"OUTPUT\"\n\t\t},\n\t\t\"rts\": {\n\t\t\t\"PACKAGE_PIN\": \"K23\",\n\t\t\t\"IOSTANDARD\": \"LVCMOS25\",\n\t\t\t\"PIO_DIRECTION\": \"INPUT\"\n\t\t},\n\t\t\"cts\": {\n\t\t\t\"PACKAGE_PIN\": \"L27\",\n\t\t\t\"IOSTANDARD\": \"LVCMOS25\",\n\t\t\t\"PIO_DIRECTION\": \"OUTPUT\"\n\t\t}\n    },\n    \"sdio\": {\n        \"dat0\": {\n            \"PACKAGE_PIN\": \"AC20\",\n            \"IOSTANDARD\": \"LVCMOS25\",\n            \"PIO_DIRECTION\": \"BIDIR\"\n        },\n        \"dat1\": {\n            \"PACKAGE_PIN\": \"AA23\",\n            \"IOSTANDARD\": \"LVCMOS25\",\n            \"PIO_DIRECTION\": \"BIDIR\"\n        },\n        \"dat2\": {\n            \"PACKAGE_PIN\": \"AA22\",\n            \"IOSTANDARD\": \"LVCMOS25\",\n            \"PIO_DIRECTION\": \"BIDIR\"\n        },\n        \"cd_dat3\": {\n            \"PACKAGE_PIN\": \"AC21\",\n            \"IOSTANDARD\": \"LVCMOS25\",\n            \"PIO_DIRECTION\": \"BIDIR\"\n        },\n        \"clk\": {\n            \"PACKAGE_PIN\": \"AB23\",\n            \"IOSTANDARD\": \"LVCMOS25\",\n            \"PIO_DIRECTION\": \"OUTPUT\"\n        },\n        \"cmd\": {\n            \"PACKAGE_PIN\": \"AB22\",\n            \"IOSTANDARD\": \"LVCMOS25\",\n            \"PIO_DIRECTION\": \"BIDIR\"\n        },\n        \"sddet\": {\n            \"PACKAGE_PIN\": \"AA21\",\n            \"IOSTANDARD\": \"LVCMOS25\",\n            \"PIO_DIRECTION\": \"INPUT\"\n        },\n        \"sdwp\": {\n            \"PACKAGE_PIN\": \"Y21\",\n            \"IOSTANDARD\": \"LVCMOS25\",\n            \"PIO_DIRECTION\": \"INPUT\"\n        }\n    },\n    \"pins\": {\n\t\"cpu_reset\": {\n\t    \"PACKAGE_PIN\": \"\",\n\t    \"IOSTANDARD\": \"LVCMOS15\",\n\t    \"PIO_DIRECTION\": \"INPUT\"\n\t},\n\t\"userClk_p\": {\n\t    \"PACKAGE_PIN\": \"K29\",\n\t    \"IOSTANDARD\": \"LVDS_25\",\n\t    \"DIFF_TERM\": \"TRUE\",\n\t    \"PIO_DIRECTION\": \"INPUT\"\n\t},\n\t\"userClk_n\": {\n\t    \"PACKAGE_PIN\": \"K28\",\n\t    \"IOSTANDARD\": \"LVDS_25\",\n\t    \"DIFF_TERM\": \"TRUE\",\n\t    \"PIO_DIRECTION\": \"INPUT\"\n\t},\n\t\"smaUserClk_p\": {\n\t    \"PACKAGE_PIN\": \"L25\",\n\t    \"IOSTANDARD\": \"LVDS_25\",\n\t    \"DIFF_TERM\": \"TRUE\",\n\t    \"PIO_DIRECTION\": \"OUTPUT\"\n\t},\n\t\"smaUserClk_n\": {\n\t    \"PACKAGE_PIN\": \"K25\",\n\t    \"IOSTANDARD\": \"LVDS_25\",\n\t    \"DIFF_TERM\": \"TRUE\",\n\t    \"PIO_DIRECTION\": \"OUTPUT\"\n\t},\n\t\"mgtRefClk_p\": {\n\t    \"PACKAGE_PIN\": \"J8\",\n\t    \"IOSTANDARD\": \"LVDS_25\",\n\t    \"DIFF_TERM\": \"TRUE\",\n\t    \"PIO_DIRECTION\": \"INPUT\"\n\t},\n\t\"mgtRefClk_n\": {\n\t    \"PACKAGE_PIN\": \"J7\",\n\t    \"IOSTANDARD\": \"LVDS_25\",\n\t    \"DIFF_TERM\": \"TRUE\",\n\t    \"PIO_DIRECTION\": \"INPUT\"\n\t},\n\t\"mgtRx_p\": {\n\t    \"PACKAGE_PIN\": \"K6\",\n\t    \"DIFF_TERM\": \"TRUE\",\n\t    \"PIO_DIRECTION\": \"INPUT\"\n\t},\n\t\"mgtRx_n\": {\n\t    \"PACKAGE_PIN\": \"K5\",\n\t    \"DIFF_TERM\": \"TRUE\",\n\t    \"PIO_DIRECTION\": \"INPUT\"\n\t},\n\t\"mgtTx_p\": {\n\t    \"PACKAGE_PIN\": \"K2\",\n\t    \"DIFF_TERM\": \"TRUE\",\n\t    \"PIO_DIRECTION\": \"OUTPUT\"\n\t},\n\t\"mgtTx_n\": {\n\t    \"PACKAGE_PIN\": \"K1\",\n\t    \"DIFF_TERM\": \"TRUE\",\n\t    \"PIO_DIRECTION\": \"OUTPUT\"\n\t},\n\t\"uart_d_in\": {\n\t    \"PACKAGE_PIN\": \"M19\",\n\t    \"IOSTANDARD\": \"LVCMOS25\",\n\t    \"PIO_DIRECTION\": \"INPUT\"\n\t},\n\t\"uart_d_out\": {\n\t    \"PACKAGE_PIN\": \"K24\",\n\t    \"IOSTANDARD\": \"LVCMOS25\",\n\t    \"PIO_DIRECTION\": \"OUTPUT\"\n\t}\n    }\n}\n"
  },
  {
    "path": "boardinfo/kc705g1.json",
    "content": "{\n    \"options\": {\n        \"bsvdefines\" : [\"XILINX=1\", \"Kintex7\", \"PCIE\", \"PCIE1\", \"PcieHostInterface\", \"PhysAddrWidth=40\", \"PcieLanes=8\",\n\t\t       \t\"CONNECTAL_BITS_DEPENDENCES=hw/mkTop.bit\", \"CONNECTAL_RUN_SCRIPT=$(CONNECTALDIR)/scripts/run.pcietest\"],\n        \"os\" : \"ubuntu\",\n        \"partname\" : \"xc7k325tffg900-2\",\n        \"need_pcie\" : \"x7_gen1x8\",\n        \"TOP\" : \"PcieTop\",\n        \"constraints\": [\"constraints/xilinx/kc705.xdc\"],\n        \"implconstraints\": [\"constraints/xilinx/kc705.xdc\", \"constraints/xilinx/pcie-clocks.xdc\"],\n        \"runscript\" : \"run.pcietest\",\n        \"CONNECTALFLAGS\" : [\"--mainclockperiod=8\", \"--derivedclockperiod=4\", \"--pcieclockperiod=8\"],\n        \"rewireclockstring\" : \"\"\n    },\n    \"fmc1\": {\n    \"LA00_p_CC\": {\n        \"LOC\": \"C25\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA00_n_CC\": {\n        \"LOC\": \"B25\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA01_p_CC\": {\n        \"LOC\": \"D26\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA01_n_CC\": {\n        \"LOC\": \"C26\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA02_p\": {\n        \"LOC\": \"H24\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA02_n\": {\n        \"LOC\": \"H25\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA03_p\": {\n        \"LOC\": \"H26\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA03_n\": {\n        \"LOC\": \"H27\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA04_p\": {\n        \"LOC\": \"G28\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA04_n\": {\n        \"LOC\": \"F28\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA05_p\": {\n        \"LOC\": \"G29\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA05_n\": {\n        \"LOC\": \"H30\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA06_p\": {\n        \"LOC\": \"H30\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA06_n\": {\n        \"LOC\": \"G30\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA07_p\": {\n        \"LOC\": \"E28\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA07_n\": {\n        \"LOC\": \"D28\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA08_p\": {\n        \"LOC\": \"E29\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA08_n\": {\n        \"LOC\": \"E30\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA09_p\": {\n        \"LOC\": \"B30\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA09_n\": {\n        \"LOC\": \"A30\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA10_p\": {\n        \"LOC\": \"D29\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA10_n\": {\n        \"LOC\": \"C30\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA11_p\": {\n        \"LOC\": \"G27\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA11_n\": {\n        \"LOC\": \"F27\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA12_p\": {\n        \"LOC\": \"C29\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA12_n\": {\n        \"LOC\": \"C29\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA13_p\": {\n        \"LOC\": \"A25\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA13_n\": {\n        \"LOC\": \"A26\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA14_p\": {\n        \"LOC\": \"B28\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA14_n\": {\n        \"LOC\": \"A28\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA15_p\": {\n        \"LOC\": \"C24\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA15_n\": {\n        \"LOC\": \"B24\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA16_p\": {\n        \"LOC\": \"B27\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA16_n\": {\n        \"LOC\": \"A27\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA17_p_CC\": {\n        \"LOC\": \"AB27\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA17_n_CC\": {\n        \"LOC\": \"AC27\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA18_p_CC\": {\n        \"LOC\": \"AD27\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA18_n_CC\": {\n        \"LOC\": \"AD28\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA19_p\": {\n        \"LOC\": \"AJ26\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA19_n\": {\n        \"LOC\": \"AK26\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"CLK0_M2C_p\": {\n        \"LOC\": \"bogus\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"CLK0_M2C_n\": {\n        \"LOC\": \"bogus\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        }\n    },\n    \"uart\": {\n\t\t\"d_in\": {\n\t\t\t\"PACKAGE_PIN\": \"M19\",\n\t\t\t\"IOSTANDARD\": \"LVCMOS25\",\n\t\t\t\"PIO_DIRECTION\": \"INPUT\"\n\t\t},\n\t\t\"d_out\": {\n\t\t\t\"PACKAGE_PIN\": \"K24\",\n\t\t\t\"IOSTANDARD\": \"LVCMOS25\",\n\t\t\t\"PIO_DIRECTION\": \"OUTPUT\"\n\t\t},\n\t\t\"rts\": {\n\t\t\t\"PACKAGE_PIN\": \"K23\",\n\t\t\t\"IOSTANDARD\": \"LVCMOS25\",\n\t\t\t\"PIO_DIRECTION\": \"INPUT\"\n\t\t},\n\t\t\"cts\": {\n\t\t\t\"PACKAGE_PIN\": \"L27\",\n\t\t\t\"IOSTANDARD\": \"LVCMOS25\",\n\t\t\t\"PIO_DIRECTION\": \"OUTPUT\"\n\t\t}\n    },\n    \"sdio\": {\n        \"dat0\": {\n            \"PACKAGE_PIN\": \"AC20\",\n            \"IOSTANDARD\": \"LVCMOS25\",\n            \"PIO_DIRECTION\": \"BIDIR\"\n        },\n        \"dat1\": {\n            \"PACKAGE_PIN\": \"AA23\",\n            \"IOSTANDARD\": \"LVCMOS25\",\n            \"PIO_DIRECTION\": \"BIDIR\"\n        },\n        \"dat2\": {\n            \"PACKAGE_PIN\": \"AA22\",\n            \"IOSTANDARD\": \"LVCMOS25\",\n            \"PIO_DIRECTION\": \"BIDIR\"\n        },\n        \"cd_dat3\": {\n            \"PACKAGE_PIN\": \"AC21\",\n            \"IOSTANDARD\": \"LVCMOS25\",\n            \"PIO_DIRECTION\": \"BIDIR\"\n        },\n        \"clk\": {\n            \"PACKAGE_PIN\": \"AB23\",\n            \"IOSTANDARD\": \"LVCMOS25\",\n            \"PIO_DIRECTION\": \"OUTPUT\"\n        },\n        \"cmd\": {\n            \"PACKAGE_PIN\": \"AB22\",\n            \"IOSTANDARD\": \"LVCMOS25\",\n            \"PIO_DIRECTION\": \"BIDIR\"\n        },\n        \"sddet\": {\n            \"PACKAGE_PIN\": \"AA21\",\n            \"IOSTANDARD\": \"LVCMOS25\",\n            \"PIO_DIRECTION\": \"INPUT\"\n        },\n        \"sdwp\": {\n            \"PACKAGE_PIN\": \"Y21\",\n            \"IOSTANDARD\": \"LVCMOS25\",\n            \"PIO_DIRECTION\": \"INPUT\"\n        }\n    },\n    \"pins\": {\n\t\"userClk_p\": {\n\t    \"PACKAGE_PIN\": \"K29\",\n\t    \"IOSTANDARD\": \"LVDS_25\",\n\t    \"DIFF_TERM\": \"TRUE\",\n\t    \"PIO_DIRECTION\": \"INPUT\"\n\t},\n\t\"userClk_n\": {\n\t    \"PACKAGE_PIN\": \"K28\",\n\t    \"IOSTANDARD\": \"LVDS_25\",\n\t    \"DIFF_TERM\": \"TRUE\",\n\t    \"PIO_DIRECTION\": \"INPUT\"\n\t},\n\t\"smaUserClk_p\": {\n\t    \"PACKAGE_PIN\": \"L25\",\n\t    \"IOSTANDARD\": \"LVDS_25\",\n\t    \"DIFF_TERM\": \"TRUE\",\n\t    \"PIO_DIRECTION\": \"OUTPUT\"\n\t},\n\t\"smaUserClk_n\": {\n\t    \"PACKAGE_PIN\": \"K25\",\n\t    \"IOSTANDARD\": \"LVDS_25\",\n\t    \"DIFF_TERM\": \"TRUE\",\n\t    \"PIO_DIRECTION\": \"OUTPUT\"\n\t},\n\t\"mgtRefClk_p\": {\n\t    \"PACKAGE_PIN\": \"J8\",\n\t    \"IOSTANDARD\": \"LVDS_25\",\n\t    \"DIFF_TERM\": \"TRUE\",\n\t    \"PIO_DIRECTION\": \"INPUT\"\n\t},\n\t\"mgtRefClk_n\": {\n\t    \"PACKAGE_PIN\": \"J7\",\n\t    \"IOSTANDARD\": \"LVDS_25\",\n\t    \"DIFF_TERM\": \"TRUE\",\n\t    \"PIO_DIRECTION\": \"INPUT\"\n\t},\n\t\"mgtRx_p\": {\n\t    \"PACKAGE_PIN\": \"K6\",\n\t    \"DIFF_TERM\": \"TRUE\",\n\t    \"PIO_DIRECTION\": \"INPUT\"\n\t},\n\t\"mgtRx_n\": {\n\t    \"PACKAGE_PIN\": \"K5\",\n\t    \"DIFF_TERM\": \"TRUE\",\n\t    \"PIO_DIRECTION\": \"INPUT\"\n\t},\n\t\"mgtTx_p\": {\n\t    \"PACKAGE_PIN\": \"K2\",\n\t    \"DIFF_TERM\": \"TRUE\",\n\t    \"PIO_DIRECTION\": \"OUTPUT\"\n\t},\n\t\"mgtTx_n\": {\n\t    \"PACKAGE_PIN\": \"K1\",\n\t    \"DIFF_TERM\": \"TRUE\",\n\t    \"PIO_DIRECTION\": \"OUTPUT\"\n\t},\n\t\"uart_d_in\": {\n\t    \"PACKAGE_PIN\": \"M19\",\n\t    \"IOSTANDARD\": \"LVCMOS25\",\n\t    \"PIO_DIRECTION\": \"INPUT\"\n\t},\n\t\"uart_d_out\": {\n\t    \"PACKAGE_PIN\": \"K24\",\n\t    \"IOSTANDARD\": \"LVCMOS25\",\n\t    \"PIO_DIRECTION\": \"OUTPUT\"\n\t}\n    }\n}\n"
  },
  {
    "path": "boardinfo/kc705g2.json",
    "content": "{\n    \"options\": {\n        \"bsvdefines\" : [\"XILINX=1\", \"Kintex7\", \"PCIE\", \"PCIE2\", \"PcieHostInterface\", \"PhysAddrWidth=40\", \"PcieLanes=8\",\n\t\t       \t\"CONNECTAL_BITS_DEPENDENCES=hw/mkTop.bit\", \"CONNECTAL_RUN_SCRIPT=$(CONNECTALDIR)/scripts/run.pcietest\"],\n        \"os\" : \"ubuntu\",\n        \"partname\" : \"xc7k325tffg900-2\",\n        \"need_pcie\" : \"x7_gen2x8\",\n        \"TOP\" : \"PcieTop\",\n        \"constraints\":     [\"constraints/xilinx/kc705g2.xdc\", \"constraints/xilinx/pcie-clocks.xdc\"],\n        \"implconstraints\": [\"constraints/xilinx/kc705g2.xdc\", \"constraints/xilinx/pcie-clocks.xdc\"],\n        \"runscript\" : \"run.pcietest\",\n        \"CONNECTALFLAGS\" : [\"--mainclockperiod=4\", \"--derivedclockperiod=4\", \"--pcieclockperiod=4\"],\n        \"rewireclockstring\" : \"\"\n    },\n    \"fmc1\": {\n    \"LA00_p_CC\": {\n        \"PACKAGE_PIN\": \"C25\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA00_n_CC\": {\n        \"PACKAGE_PIN\": \"B25\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA01_p_CC\": {\n        \"PACKAGE_PIN\": \"D26\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA01_n_CC\": {\n        \"PACKAGE_PIN\": \"C26\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA02_p\": {\n        \"PACKAGE_PIN\": \"H24\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA02_n\": {\n        \"PACKAGE_PIN\": \"H25\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA03_p\": {\n        \"PACKAGE_PIN\": \"H26\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA03_n\": {\n        \"PACKAGE_PIN\": \"H27\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA04_p\": {\n        \"PACKAGE_PIN\": \"G28\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA04_n\": {\n        \"PACKAGE_PIN\": \"F28\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA05_p\": {\n        \"PACKAGE_PIN\": \"G29\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA05_n\": {\n        \"PACKAGE_PIN\": \"H30\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA06_p\": {\n        \"PACKAGE_PIN\": \"H30\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA06_n\": {\n        \"PACKAGE_PIN\": \"G30\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA07_p\": {\n        \"PACKAGE_PIN\": \"E28\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA07_n\": {\n        \"PACKAGE_PIN\": \"D28\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA08_p\": {\n        \"PACKAGE_PIN\": \"E29\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA08_n\": {\n        \"PACKAGE_PIN\": \"E30\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA09_p\": {\n        \"PACKAGE_PIN\": \"B30\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA09_n\": {\n        \"PACKAGE_PIN\": \"A30\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA10_p\": {\n        \"PACKAGE_PIN\": \"D29\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA10_n\": {\n        \"PACKAGE_PIN\": \"C30\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA11_p\": {\n        \"PACKAGE_PIN\": \"G27\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA11_n\": {\n        \"PACKAGE_PIN\": \"F27\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA12_p\": {\n        \"PACKAGE_PIN\": \"C29\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA12_n\": {\n        \"PACKAGE_PIN\": \"C29\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA13_p\": {\n        \"PACKAGE_PIN\": \"A25\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA13_n\": {\n        \"PACKAGE_PIN\": \"A26\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA14_p\": {\n        \"PACKAGE_PIN\": \"B28\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA14_n\": {\n        \"PACKAGE_PIN\": \"A28\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA15_p\": {\n        \"PACKAGE_PIN\": \"C24\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA15_n\": {\n        \"PACKAGE_PIN\": \"B24\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA16_p\": {\n        \"PACKAGE_PIN\": \"B27\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA16_n\": {\n        \"PACKAGE_PIN\": \"A27\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA17_p_CC\": {\n        \"PACKAGE_PIN\": \"AB27\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA17_n_CC\": {\n        \"PACKAGE_PIN\": \"AC27\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA18_p_CC\": {\n        \"PACKAGE_PIN\": \"AD27\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA18_n_CC\": {\n        \"PACKAGE_PIN\": \"AD28\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA19_p\": {\n        \"PACKAGE_PIN\": \"AJ26\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA19_n\": {\n        \"PACKAGE_PIN\": \"AK26\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"CLK0_M2C_p\": {\n        \"PACKAGE_PIN\": \"bogus\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"CLK0_M2C_n\": {\n        \"PACKAGE_PIN\": \"bogus\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        }\n    },\n    \"uart\": {\n\t\t\"d_in\": {\n\t\t\t\"PACKAGE_PIN\": \"M19\",\n\t\t\t\"IOSTANDARD\": \"LVCMOS25\",\n\t\t\t\"PIO_DIRECTION\": \"INPUT\"\n\t\t},\n\t\t\"d_out\": {\n\t\t\t\"PACKAGE_PIN\": \"K24\",\n\t\t\t\"IOSTANDARD\": \"LVCMOS25\",\n\t\t\t\"PIO_DIRECTION\": \"OUTPUT\"\n\t\t},\n\t\t\"rts\": {\n\t\t\t\"PACKAGE_PIN\": \"K23\",\n\t\t\t\"IOSTANDARD\": \"LVCMOS25\",\n\t\t\t\"PIO_DIRECTION\": \"INPUT\"\n\t\t},\n\t\t\"cts\": {\n\t\t\t\"PACKAGE_PIN\": \"L27\",\n\t\t\t\"IOSTANDARD\": \"LVCMOS25\",\n\t\t\t\"PIO_DIRECTION\": \"OUTPUT\"\n\t\t}\n    },\n    \"sdio\": {\n        \"dat0\": {\n            \"PACKAGE_PIN\": \"AC20\",\n            \"IOSTANDARD\": \"LVCMOS25\",\n            \"PIO_DIRECTION\": \"BIDIR\"\n        },\n        \"dat1\": {\n            \"PACKAGE_PIN\": \"AA23\",\n            \"IOSTANDARD\": \"LVCMOS25\",\n            \"PIO_DIRECTION\": \"BIDIR\"\n        },\n        \"dat2\": {\n            \"PACKAGE_PIN\": \"AA22\",\n            \"IOSTANDARD\": \"LVCMOS25\",\n            \"PIO_DIRECTION\": \"BIDIR\"\n        },\n        \"cd_dat3\": {\n            \"PACKAGE_PIN\": \"AC21\",\n            \"IOSTANDARD\": \"LVCMOS25\",\n            \"PIO_DIRECTION\": \"BIDIR\"\n        },\n        \"clk\": {\n            \"PACKAGE_PIN\": \"AB23\",\n            \"IOSTANDARD\": \"LVCMOS25\",\n            \"PIO_DIRECTION\": \"OUTPUT\"\n        },\n        \"cmd\": {\n            \"PACKAGE_PIN\": \"AB22\",\n            \"IOSTANDARD\": \"LVCMOS25\",\n            \"PIO_DIRECTION\": \"BIDIR\"\n        },\n        \"sddet\": {\n            \"PACKAGE_PIN\": \"AA21\",\n            \"IOSTANDARD\": \"LVCMOS25\",\n            \"PIO_DIRECTION\": \"INPUT\"\n        },\n        \"sdwp\": {\n            \"PACKAGE_PIN\": \"Y21\",\n            \"IOSTANDARD\": \"LVCMOS25\",\n            \"PIO_DIRECTION\": \"INPUT\"\n        }\n    },\n    \"pins\": {\n\t\"userClk_p\": {\n\t    \"PACKAGE_PIN\": \"K29\",\n\t    \"IOSTANDARD\": \"LVDS_25\",\n\t    \"DIFF_TERM\": \"TRUE\",\n\t    \"PIO_DIRECTION\": \"INPUT\"\n\t},\n\t\"userClk_n\": {\n\t    \"PACKAGE_PIN\": \"K28\",\n\t    \"IOSTANDARD\": \"LVDS_25\",\n\t    \"DIFF_TERM\": \"TRUE\",\n\t    \"PIO_DIRECTION\": \"INPUT\"\n\t},\n\t\"smaUserClk_p\": {\n\t    \"PACKAGE_PIN\": \"L25\",\n\t    \"IOSTANDARD\": \"LVDS_25\",\n\t    \"DIFF_TERM\": \"TRUE\",\n\t    \"PIO_DIRECTION\": \"OUTPUT\"\n\t},\n\t\"smaUserClk_n\": {\n\t    \"PACKAGE_PIN\": \"K25\",\n\t    \"IOSTANDARD\": \"LVDS_25\",\n\t    \"DIFF_TERM\": \"TRUE\",\n\t    \"PIO_DIRECTION\": \"OUTPUT\"\n\t},\n\t\"mgtRefClk_p\": {\n\t    \"PACKAGE_PIN\": \"J8\",\n\t    \"IOSTANDARD\": \"LVDS_25\",\n\t    \"DIFF_TERM\": \"TRUE\",\n\t    \"PIO_DIRECTION\": \"INPUT\"\n\t},\n\t\"mgtRefClk_n\": {\n\t    \"PACKAGE_PIN\": \"J7\",\n\t    \"IOSTANDARD\": \"LVDS_25\",\n\t    \"DIFF_TERM\": \"TRUE\",\n\t    \"PIO_DIRECTION\": \"INPUT\"\n\t},\n\t\"mgtRx_p\": {\n\t    \"PACKAGE_PIN\": \"K6\",\n\t    \"DIFF_TERM\": \"TRUE\",\n\t    \"PIO_DIRECTION\": \"INPUT\"\n\t},\n\t\"mgtRx_n\": {\n\t    \"PACKAGE_PIN\": \"K5\",\n\t    \"DIFF_TERM\": \"TRUE\",\n\t    \"PIO_DIRECTION\": \"INPUT\"\n\t},\n\t\"mgtTx_p\": {\n\t    \"PACKAGE_PIN\": \"K2\",\n\t    \"DIFF_TERM\": \"TRUE\",\n\t    \"PIO_DIRECTION\": \"OUTPUT\"\n\t},\n\t\"mgtTx_n\": {\n\t    \"PACKAGE_PIN\": \"K1\",\n\t    \"DIFF_TERM\": \"TRUE\",\n\t    \"PIO_DIRECTION\": \"OUTPUT\"\n\t},\n\t\"uart_d_in\": {\n\t    \"PACKAGE_PIN\": \"M19\",\n\t    \"IOSTANDARD\": \"LVCMOS25\",\n\t    \"PIO_DIRECTION\": \"INPUT\"\n\t},\n\t\"uart_d_out\": {\n\t    \"PACKAGE_PIN\": \"K24\",\n\t    \"IOSTANDARD\": \"LVCMOS25\",\n\t    \"PIO_DIRECTION\": \"OUTPUT\"\n\t}\n    }\n}\n"
  },
  {
    "path": "boardinfo/kcu105.json",
    "content": "{\n    \"options\": {\n        \"bsvdefines\" : [\"XILINX=1\", \"Virtex7\", \"PCIE\", \"PCIE3\", \"PcieHostInterface\", \"PhysAddrWidth=40\", \"NUMBER_OF_LEDS=8\", \"PcieLanes=8\",\n\t\t       \t\"CONNECTAL_BITS_DEPENDENCES=hw/mkTop.bit\", \"CONNECTAL_RUN_SCRIPT=$(CONNECTALDIR)/scripts/run.pcietest\"],\n        \"os\" : \"ubuntu\",\n        \"partname\" : \"XCKU040-2FFVA1156E\",\n        \"need_pcie\" : \"x7_gen3x8\",\n        \"TOP\" : \"PcieTop\",\n        \"constraints\": [],\n        \"implconstraints\": [\"constraints/xilinx/kcu105.xdc\", \"constraints/xilinx/pcie-clocks.xdc\"],\n        \"runscript\" : \"run.pcietest\",\n        \"CONNECTALFLAGS\" : [\"--mainclockperiod=4\", \"--derivedclockperiod=4\", \"--pcieclockperiod=4\"],\n        \"rewireclockstring\" : \"\"\n    },\n    \"leds\" : {\n\t\t\"L0\" : {\n\t\t \"LOC\" : \"bogus\",\n\t\t \"IOSTANDARD\" : \"LVCMOS15\",\n\t\t \"PIO_DIRECTION\" : \"OUTPUT\"\n\t\t },\n\t\t\"L1\" : {\n\t\t \"LOC\" : \"bogus\",\n\t\t \"IOSTANDARD\" : \"LVCMOS15\",\n\t\t \"PIO_DIRECTION\" : \"OUTPUT\"\n\t\t },\n\t\t\"L2\" : {\n\t\t \"LOC\" : \"bogus\",\n\t\t \"IOSTANDARD\" : \"LVCMOS15\",\n\t\t \"PIO_DIRECTION\" : \"OUTPUT\"\n\t\t },\n\t\t\"L3\" : {\n\t\t \"LOC\" : \"bogus\",\n\t\t \"IOSTANDARD\" : \"LVCMOS15\",\n\t\t \"PIO_DIRECTION\" : \"OUTPUT\"\n\t\t },\n\t\t\"L4\" : {\n\t\t \"LOC\" : \"bogus\",\n\t\t \"IOSTANDARD\" : \"LVCMOS15\",\n\t\t \"PIO_DIRECTION\" : \"OUTPUT\"\n\t\t },\n\t\t\"L5\" : {\n\t\t \"LOC\" : \"bogus\",\n\t\t \"IOSTANDARD\" : \"LVCMOS15\",\n\t\t \"PIO_DIRECTION\" : \"OUTPUT\"\n\t\t },\n\t\t\"L6\" : {\n\t\t \"LOC\" : \"bogus\",\n\t\t \"IOSTANDARD\" : \"LVCMOS15\",\n\t\t \"PIO_DIRECTION\" : \"OUTPUT\"\n\t\t },\n\t\t\"L7\" : {\n\t\t \"LOC\" : \"bogus\",\n\t\t \"IOSTANDARD\" : \"LVCMOS15\",\n\t\t \"PIO_DIRECTION\" : \"OUTPUT\"\n\t\t }\n\t},\n    \"sfp1\": {\n\t\t \"rxp\" : {\n\t\t\t     \"LOC\" : \"bogus\",\n\t\t\t     \"PIO_DIRECTION\" : \"INPUT\"\n\t\t },\n\t\t \"rxn\" : {\n\t\t\t     \"LOC\" : \"bogus\",\n\t\t\t     \"PIO_DIRECTION\" : \"INPUT\"\n\t\t },\n\t\t \"txp\" : {\n\t\t\t     \"LOC\" : \"bogus\",\n\t\t\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t\t },\n\t\t \"txn\" : {\n\t\t\t     \"LOC\" : \"bogus\",\n\t\t\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t\t }\n    },\n    \"sfp2\": {\n\t\t \"rxp\" : {\n\t\t\t     \"LOC\" : \"bogus\",\n\t\t\t     \"PIO_DIRECTION\" : \"INPUT\"\n\t\t },\n\t\t \"rxn\" : {\n\t\t\t     \"LOC\" : \"bogus\",\n\t\t\t     \"PIO_DIRECTION\" : \"INPUT\"\n\t\t },\n\t\t \"txp\" : {\n\t\t\t     \"LOC\" : \"bogus\",\n\t\t\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t\t },\n\t\t \"txn\" : {\n\t\t\t     \"LOC\" : \"bogus\",\n\t\t\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t\t }\n    },\n    \"sfp3\": {\n\t\t \"rxp\" : {\n\t\t\t     \"LOC\" : \"bogus\",\n\t\t\t     \"PIO_DIRECTION\" : \"INPUT\"\n\t\t },\n\t\t \"rxn\" : {\n\t\t\t     \"LOC\" : \"bogus\",\n\t\t\t     \"PIO_DIRECTION\" : \"INPUT\"\n\t\t },\n\t\t \"txp\" : {\n\t\t\t     \"LOC\" : \"bogus\",\n\t\t\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t\t },\n\t\t \"txn\" : {\n\t\t\t     \"LOC\" : \"bogus\",\n\t\t\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t\t }\n    },\n    \"sfp4\": {\n\t\t \"rxp\" : {\n\t\t\t     \"LOC\" : \"bogus\",\n\t\t\t     \"PIO_DIRECTION\" : \"INPUT\"\n\t\t },\n\t\t \"rxn\" : {\n\t\t\t     \"LOC\" : \"bogus\",\n\t\t\t     \"PIO_DIRECTION\" : \"INPUT\"\n\t\t },\n\t\t \"txp\" : {\n\t\t\t     \"LOC\" : \"bogus\",\n\t\t\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t\t },\n\t\t \"txn\" : {\n\t\t\t     \"LOC\" : \"bogus\",\n\t\t\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t\t }\n    },\n    \"uart\": {\n\t\t\"d_in\": {\n\t\t\t\"LOC\": \"bogus\",\n\t\t\t\"IOSTANDARD\": \"LVCMOS18\",\n\t\t\t\"PIO_DIRECTION\": \"INPUT\"\n\t\t},\n\t\t\"d_out\": {\n\t\t\t\"LOC\": \"bogus\",\n\t\t\t\"IOSTANDARD\": \"LVCMOS18\",\n\t\t\t\"PIO_DIRECTION\": \"OUTPUT\"\n\t\t},\n\t\t\"rts\": {\n\t\t\t\"LOC\": \"bogus\",\n\t\t\t\"IOSTANDARD\": \"LVCMOS18\",\n\t\t\t\"PIO_DIRECTION\": \"INPUT\"\n\t\t},\n\t\t\"cts\": {\n\t\t\t\"LOC\": \"bogus\",\n\t\t\t\"IOSTANDARD\": \"LVCMOS18\",\n\t\t\t\"PIO_DIRECTION\": \"OUTPUT\"\n\t\t}\n    },\n    \"iic_main\": {\n\t\t\"sda\": {\n\t\t\t\"LOC\": \"bogus\",\n\t\t\t\"IOSTANDARD\": \"LVCMOS18\",\n\t\t\t\"PIO_DIRECTION\": \"BIDIR\"\n\t\t},\n\t\t\"scl\": {\n\t\t\t\"LOC\": \"bogus\",\n\t\t\t\"IOSTANDARD\": \"LVCMOS18\",\n\t\t\t\"PIO_DIRECTION\": \"BIDIR\"\n\t\t}\n    },\n    \"pins\": {\n\t\t\"userClk_p\": {\n\t\t\t\"LOC\": \"bogus\",\n\t\t\t\"IOSTANDARD\": \"LVDS_25\",\n\t\t\t\"DIFF_TERM\": \"TRUE\",\n\t\t\t\"PIO_DIRECTION\": \"INPUT\"\n\t\t},\n\t\t\"userClk_n\": {\n\t\t\t\"LOC\": \"bogus\",\n\t\t\t\"IOSTANDARD\": \"LVDS_25\",\n\t\t\t\"DIFF_TERM\": \"TRUE\",\n\t\t\t\"PIO_DIRECTION\": \"INPUT\"\n\t\t},\n\t\t\"smaUserClk_p\": {\n\t\t\t\"LOC\": \"bogus\",\n\t\t\t\"IOSTANDARD\": \"LVDS_25\",\n\t\t\t\"DIFF_TERM\": \"TRUE\",\n\t\t\t\"PIO_DIRECTION\": \"OUTPUT\"\n\t\t},\n\t\t\"smaUserClk_n\": {\n\t\t\t\"LOC\": \"bogus\",\n\t\t\t\"IOSTANDARD\": \"LVDS_25\",\n\t\t\t\"DIFF_TERM\": \"TRUE\",\n\t\t\t\"PIO_DIRECTION\": \"OUTPUT\"\n\t\t},\n\t        \"sys_clk_p\": {\n\t\t\t\"LOC\": \"bogus\",\n\t\t\t\"IOSTANDARD\": \"LVDS_25\",\n\t\t\t\"DIFF_TERM\": \"TRUE\",\n\t\t\t\"PIO_DIRECTION\": \"INPUT\"\n\t\t},\n\t        \"sys_clk_n\": {\n\t\t\t\"LOC\": \"bogus\",\n\t\t\t\"IOSTANDARD\": \"LVDS_25\",\n\t\t\t\"DIFF_TERM\": \"TRUE\",\n\t\t\t\"PIO_DIRECTION\": \"INPUT\"\n\t\t},\n\t        \"si5324_clk_p\": {\n\t\t\t\"LOC\": \"bogus\",\n\t\t\t\"DIFF_TERM\": \"TRUE\",\n\t\t\t\"PIO_DIRECTION\": \"INPUT\"\n\t\t},\n\t        \"si5324_clk_n\": {\n\t\t\t\"LOC\": \"bogus\",\n\t\t\t\"DIFF_TERM\": \"TRUE\",\n\t\t\t\"PIO_DIRECTION\": \"INPUT\"\n\t\t},\n\t\t\"mgtRefClk_p\": {\n\t\t\t\"LOC\": \"bogus\",\n\t\t\t\"IOSTANDARD\": \"LVDS_25\",\n\t\t\t\"DIFF_TERM\": \"TRUE\",\n\t\t\t\"PIO_DIRECTION\": \"INPUT\"\n\t\t},\n\t\t\"mgtRefClk_n\": {\n\t\t\t\"LOC\": \"bogus\",\n\t\t\t\"IOSTANDARD\": \"LVDS_25\",\n\t\t\t\"DIFF_TERM\": \"TRUE\",\n\t\t\t\"PIO_DIRECTION\": \"INPUT\"\n\t\t},\n\t\t\"mgtRx_p\": {\n\t\t\t\"LOC\": \"bogus\",\n\t\t\t\"DIFF_TERM\": \"TRUE\",\n\t\t\t\"PIO_DIRECTION\": \"INPUT\"\n\t\t},\n\t\t\"mgtRx_n\": {\n\t\t\t\"LOC\": \"bogus\",\n\t\t\t\"DIFF_TERM\": \"TRUE\",\n\t\t\t\"PIO_DIRECTION\": \"INPUT\"\n\t\t},\n\t\t\"mgtTx_p\": {\n\t\t\t\"LOC\": \"bogus\",\n\t\t\t\"DIFF_TERM\": \"TRUE\",\n\t\t\t\"PIO_DIRECTION\": \"OUTPUT\"\n\t\t},\n\t\t\"mgtTx_n\": {\n\t\t\t\"LOC\": \"bogus\",\n\t\t\t\"DIFF_TERM\": \"TRUE\",\n\t\t\t\"PIO_DIRECTION\": \"OUTPUT\"\n\t\t},\n\t\t\"si5324_rst_n\": {\n\t\t\t\"LOC\": \"bogus\",\n\t\t\t\"IOSTANDARD\": \"LVCMOS18\",\n\t\t\t\"PIO_DIRECTION\": \"OUTPUT\"\n\t\t}\n    }\n}\n\n\n"
  },
  {
    "path": "boardinfo/miniitx100.json",
    "content": "{\n    \"options\": {\n        \"os\" : \"android\",\n        \"partname\" : \"xc7z100ffg900-2\",\n        \"rewireclockstring\" : \"tclzynqrewireclock\",\n        \"constraints\": [\"constraints/xilinx/xc7z100ffg900.xdc\", \"constraints/xilinx/miniitx100.xdc\"],\n        \"implconstraints\": [\"constraints/xilinx/xc7z100ffg900.xdc\", \"constraints/xilinx/miniitx100.xdc\"],\n        \"TOP\" : \"ZynqTop\",\n        \"runscript\" : \"run.android\",\n        \"bsvdefines\" : [\"XILINX=1\", \"ZYNQ\", \"ZynqHostInterface\", \"PhysAddrWidth=32\", \"NUMBER_OF_LEDS=8\", \"PcieLanes=4\",\n\t\t\t\"CONNECTAL_BITS_DEPENDENCES=hw/mkTop.bit\", \"CONNECTAL_RUN_SCRIPT=$(CONNECTALDIR)/scripts/run.android\",\n\t\t\t\"CONNECTAL_EXENAME=android.exe\", \"CONNECTAL_EXENAME2=android.exe2\"],\n\t\"CONNECTALFLAGS\": [\"--mainclockperiod=5\", \"--derivedclockperiod=2.5\"],\n        \"need_pcie\" : \"unused\"\n    },\n    \"uart\": {\n        \"d_out\": {\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PIO_DIRECTION\": \"OUTPUT\",\n            \"LOC\": \"C19\"\n        },\n        \"d_in\": {\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PIO_DIRECTION\": \"INPUT\",\n            \"LOC\": \"D18\"\n        }\n    },\n    \"i2c_main\": {\n        \"scl\": {\n            \"PIO_DIRECTION\": \"BIDIR\",\n            \"IOSTANDARD\": \"LVCMOS18\",\n            \"LOC\": \"A19\"\n        },\n        \"sda\": {\n            \"PIO_DIRECTION\": \"BIDIR\",\n            \"IOSTANDARD\": \"LVCMOS18\",\n            \"LOC\": \"F19\"\n        },\n        \"mux_reset\": {\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PIO_DIRECTION\": \"OUTPUT\",\n            \"LOC\": \"F20\"\n        }\n    },\n    \"pcie\": {\n        \"sys_clk_p\": {\n            \"IOSTANDARD\": \"DIFF_SSTL15\",\n            \"PIO_DIRECTION\": \"OUTPUT\",\n            \"LOC\": \"N8\"\n        },\n        \"sys_clk_n\": {\n            \"IOSTANDARD\": \"DIFF_SSTL15\",\n            \"PIO_DIRECTION\": \"OUTPUT\",\n            \"LOC\": \"N7\"\n        },\n        \"sys_reset_n\": {\n            \"IOSTANDARD\": \"LVCMOS25\",\n            \"PIO_DIRECTION\": \"OUTPUT\",\n            \"LOC\": \"AC18\"\n        }\n    },\n    \"sfp1\": {\n        \"mod_def0\": {\n            \"IOSTANDARD\": \"LVCMOS25\",\n            \"LOC\": \"AB20\"\n        },\n        \"mod_def1\": {\n            \"IOSTANDARD\": \"LVCMOS25\",\n            \"LOC\": \"AB19\"\n        },\n        \"mod_def2\": {\n            \"IOSTANDARD\": \"LVCMOS25\",\n            \"LOC\": \"AA19\"\n        },\n        \"rx_los\": {\n            \"PIO_DIRECTION\": \"INPUT\",\n            \"IOSTANDARD\": \"LVCMOS25\",\n            \"LOC\": \"AE20\"\n        },\n        \"tx_disable\": {\n            \"PIO_DIRECTION\": \"OUTPUT\",\n            \"IOSTANDARD\": \"LVCMOS25\",\n            \"LOC\": \"AA18\"\n        },\n        \"tx_fault\": {\n            \"PIO_DIRECTION\": \"INPUT\",\n            \"IOSTANDARD\": \"LVCMOS25\",\n            \"LOC\": \"AD19\"\n        },\n        \"rxp\": {\n            \"PIO_DIRECTION\": \"INPUT\",\n            \"LOC\": \"AC4\"\n        },\n        \"rxn\": {\n            \"PIO_DIRECTION\": \"INPUT\",\n            \"LOC\": \"AC3\"\n        },\n        \"txp\": {\n            \"PIO_DIRECTION\": \"OUTPUT\",\n            \"LOC\": \"AB2\"\n        },\n        \"txn\": {\n            \"PIO_DIRECTION\": \"OUTPUT\",\n            \"LOC\": \"AB1\"\n        }\n    }\n}\n"
  },
  {
    "path": "boardinfo/ncverilog.json",
    "content": "{\n    \"options\": {\n        \"os\" : \"ubuntu\",\n        \"partname\" : \"xc7z020clg484-1\",\n        \"TOP\" : \"XsimTop\",\n\t\"bsvdefines\": [\"CnocTop\", \"XsimHostInterface\", \"PhysAddrWidth=40\", \"SIMULATION\", \"SVDPI\",\n\t\t       \t\"CONNECTAL_BITS_DEPENDENCES=ncverilogsim\"],\n        \"CONNECTALFLAGS\" : [\"--mainclockperiod=20\", \"--derivedclockperiod=10\"],\n        \"need_pcie\" : \"unused\"\n    }\n}\n\n\n"
  },
  {
    "path": "boardinfo/nfsume.json",
    "content": "{\n    \"options\": {\n        \"bsvdefines\" : [\"XILINX=1\", \"Virtex7\", \"PCIE\", \"PCIE3\", \"PcieHostInterface\", \"PhysAddrWidth=40\", \"NUMBER_OF_LEDS=2\", \"PcieLanes=8\",\n\t\t       \t\"CONNECTAL_BITS_DEPENDENCES=hw/mkTop.bit\", \"CONNECTAL_RUN_SCRIPT=$(CONNECTALDIR)/scripts/run.pcietest\"],\n        \"os\" : \"ubuntu\",\n        \"partname\" : \"xc7vx690tffg1761-3\",\n        \"need_pcie\" : \"x7_gen3x8\",\n        \"TOP\" : \"PcieTop\",\n        \"constraints\": [\"constraints/xilinx/nfsume.xdc\"],\n        \"implconstraints\": [\"constraints/xilinx/nfsume.xdc\", \"constraints/xilinx/pcie-clocks.xdc\"],\n        \"runscript\" : \"run.pcietest\",\n        \"CONNECTALFLAGS\" : [\"--mainclockperiod=4\", \"--derivedclockperiod=4\", \"--pcieclockperiod=4\"],\n        \"rewireclockstring\" : \"\"\n    },\n    \"BTN\": {\n        \"BTN[0]\": {\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"AR13\"\n        },\n        \"BTN[1]\": {\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"BB12\"\n        }\n    },\n    \"CLK\": {\n        \"FPGA_SYSCLK_N\": {\n            \"PIO_DIRECTION\": \"INPUT\",\n            \"IOSTANDARD\": \"LVDS\",\n\t\t\t\"DIFF_TERM\": \"TRUE\",\n            \"PACKAGE_PIN\": \"G18\"\n        },\n        \"FPGA_SYSCLK_P\": {\n            \"PIO_DIRECTION\": \"INPUT\",\n            \"IOSTANDARD\": \"LVDS\",\n\t\t\t\"DIFF_TERM\": \"TRUE\",\n            \"PACKAGE_PIN\": \"H19\"\n        }\n    },\n    \"CPLD\": {\n        \"CPLD_IMGSEL[0]\": {\n            \"IOSTANDARD\": \"LVCMOS18\",\n            \"PACKAGE_PIN\": \"AP31\"\n        },\n        \"CPLD_IMGSEL[1]\": {\n            \"IOSTANDARD\": \"LVCMOS18\",\n            \"PACKAGE_PIN\": \"AP33\"\n        },\n        \"CPLD_IMGSEL[2]\": {\n            \"IOSTANDARD\": \"LVCMOS18\",\n            \"PACKAGE_PIN\": \"AR33\"\n        },\n        \"CPLD_RECONFIG\": {\n            \"IOSTANDARD\": \"LVCMOS18\",\n            \"PACKAGE_PIN\": \"AK32\"\n        }\n    },\n    \"DDR\": {\n        \"DDR3_SYSCLK_N\": {\n            \"IOSTANDARD\": \"LVDS\",\n\t\t\t\"DIFF_TERM\": \"TRUE\",\n            \"PACKAGE_PIN\": \"E35\"\n        },\n        \"DDR3_SYSCLK_P\": {\n            \"IOSTANDARD\": \"LVDS\",\n\t\t\t\"DIFF_TERM\": \"TRUE\",\n            \"PACKAGE_PIN\": \"E34\"\n        }\n    },\n    \"FMC\": {\n\t\"FMC_GBTCLK_P[00]\": {\n\t    \"DIFF_TERM\": \"TRUE\",\n            \"PACKAGE_PIN\": \"AT8\"\n\t},\n\t\"FMC_GBTCLK_N[00]\": {\n\t    \"DIFF_TERM\": \"TRUE\",\n            \"PACKAGE_PIN\": \"AT7\"\n\t},\n        \"FMC_CLK0_M2C_N\": {\n            \"IOSTANDARD\": \"LVDS\",\n\t    \"DIFF_TERM\": \"TRUE\",\n            \"PACKAGE_PIN\": \"AT27\"\n        },\n        \"FMC_CLK0_M2C_P\": {\n            \"IOSTANDARD\": \"LVDS\",\n\t\t\t\"DIFF_TERM\": \"TRUE\",\n            \"PACKAGE_PIN\": \"AR27\"\n        },\n        \"FMC_CLK1_M2C_N\": {\n            \"IOSTANDARD\": \"LVDS\",\n\t\t\t\"DIFF_TERM\": \"TRUE\",\n            \"PACKAGE_PIN\": \"AV35\"\n        },\n        \"FMC_CLK1_M2C_P\": {\n            \"IOSTANDARD\": \"LVDS\",\n\t\t\t\"DIFF_TERM\": \"TRUE\",\n            \"PACKAGE_PIN\": \"AV34\"\n        },\n        \"FMC_LA_N[00]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"AV28\"\n        },\n        \"FMC_LA_N[01]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"AR28\"\n        },\n        \"FMC_LA_N[02]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"AT29\"\n        },\n        \"FMC_LA_N[03]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"BB27\"\n        },\n        \"FMC_LA_N[04]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"BB29\"\n        },\n        \"FMC_LA_N[05]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"AV26\"\n        },\n        \"FMC_LA_N[06]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"BA27\"\n        },\n        \"FMC_LA_N[07]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"AY28\"\n        },\n        \"FMC_LA_N[08]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"AP28\"\n        },\n        \"FMC_LA_N[09]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"AR25\"\n        },\n        \"FMC_LA_N[10]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"AW26\"\n        },\n        \"FMC_LA_N[11]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"AT26\"\n        },\n        \"FMC_LA_N[12]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"AV29\"\n        },\n        \"FMC_LA_N[13]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"AW28\"\n        },\n        \"FMC_LA_N[14]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"AN26\"\n        },\n        \"FMC_LA_N[15]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"AM27\"\n        },\n        \"FMC_LA_N[16]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"AL27\"\n        },\n        \"FMC_LA_N[17]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"AY33\"\n        },\n        \"FMC_LA_N[18]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"AV33\"\n        },\n        \"FMC_LA_N[19]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"AW31\"\n        },\n        \"FMC_LA_N[20]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"AY30\"\n        },\n        \"FMC_LA_N[21]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"BB31\"\n        },\n        \"FMC_LA_N[22]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"BA32\"\n        },\n        \"FMC_LA_N[23]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"BB34\"\n        },\n        \"FMC_LA_N[24]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"AU34\"\n        },\n        \"FMC_LA_N[25]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"AU33\"\n        },\n        \"FMC_LA_N[26]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"BB33\"\n        },\n        \"FMC_LA_N[27]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"AV31\"\n        },\n        \"FMC_LA_N[28]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"AT35\"\n        },\n        \"FMC_LA_N[29]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"BB36\"\n        },\n        \"FMC_LA_N[30]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"BA35\"\n        },\n        \"FMC_LA_N[31]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"AP30\"\n        },\n        \"FMC_LA_N[32]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"AW36\"\n        },\n        \"FMC_LA_N[33]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"AU36\"\n        },\n        \"FMC_LA_P[00]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"AU28\"\n        },\n        \"FMC_LA_P[01]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"AP27\"\n        },\n        \"FMC_LA_P[02]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"AR29\"\n        },\n        \"FMC_LA_P[03]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"BB26\"\n        },\n        \"FMC_LA_P[04]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"BB28\"\n        },\n        \"FMC_LA_P[05]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"AV25\"\n        },\n        \"FMC_LA_P[06]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"BA26\"\n        },\n        \"FMC_LA_P[07]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"AY27\"\n        },\n        \"FMC_LA_P[08]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"AN28\"\n        },\n        \"FMC_LA_P[09]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"AP25\"\n        },\n        \"FMC_LA_P[10]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"AW25\"\n        },\n        \"FMC_LA_P[11]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"AT25\"\n        },\n        \"FMC_LA_P[12]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"AU29\"\n        },\n        \"FMC_LA_P[13]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"AW27\"\n        },\n        \"FMC_LA_P[14]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"AN25\"\n        },\n        \"FMC_LA_P[15]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"AM26\"\n        },\n        \"FMC_LA_P[16]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"AK27\"\n        },\n        \"FMC_LA_P[17]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"AY32\"\n        },\n        \"FMC_LA_P[18]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"AU32\"\n        },\n        \"FMC_LA_P[19]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"AV30\"\n        },\n        \"FMC_LA_P[20]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"AW30\"\n        },\n        \"FMC_LA_P[21]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"BA30\"\n        },\n        \"FMC_LA_P[22]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"BA31\"\n        },\n        \"FMC_LA_P[23]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"BA34\"\n        },\n        \"FMC_LA_P[24]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"AT34\"\n        },\n        \"FMC_LA_P[25]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"AT32\"\n        },\n        \"FMC_LA_P[26]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"BB32\"\n        },\n        \"FMC_LA_P[27]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"AU31\"\n        },\n        \"FMC_LA_P[28]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"AR34\"\n        },\n        \"FMC_LA_P[29]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"BA36\"\n        },\n        \"FMC_LA_P[30]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"AY34\"\n        },\n        \"FMC_LA_P[31]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"AN30\"\n        },\n        \"FMC_LA_P[32]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"AV36\"\n        },\n        \"FMC_LA_P[33]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"AT36\"\n        },\n        \"FMC_PRSNT_LS\": {\n            \"IOSTANDARD\": \"LVCMOS18\",\n            \"PACKAGE_PIN\": \"AR30\"\n        }\n    },\n    \"Fan\": {\n        \"FAN_PWM\": {\n            \"IOSTANDARD\": \"LVCMOS18\",\n            \"PACKAGE_PIN\": \"AN34\"\n        },\n        \"FAN_TACH\": {\n            \"IOSTANDARD\": \"LVCMOS18\",\n            \"PACKAGE_PIN\": \"AP32\"\n        }\n    },\n    \"I2C\": {\n        \"I2C_FPGA_SCL\": {\n            \"PIO_DIRECTION\": \"INPUT\",\n            \"IOSTANDARD\": \"LVCMOS18\",\n            \"PACKAGE_PIN\": \"AK24\"\n        },\n        \"I2C_FPGA_SDA\": {\n            \"PIO_DIRECTION\": \"BIDIR\",\n            \"IOSTANDARD\": \"LVCMOS18\",\n            \"PACKAGE_PIN\": \"AK25\"\n        },\n        \"I2C_MUX_RESET\": {\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"AM39\"\n        }\n    },\n    \"sdio\": {\n        \"cmd\": {\n            \"PIO_DIRECTION\": \"BIDIR\",\n            \"IOSTANDARD\": \"LVCMOS18\",\n            \"PACKAGE_PIN\": \"AJ26\"\n        },\n        \"clk\": {\n            \"PIO_DIRECTION\": \"BIDIR\",\n            \"IOSTANDARD\": \"LVCMOS18\",\n            \"PACKAGE_PIN\": \"AJ25\"\n        },\n        \"cd\": {\n            \"PIO_DIRECTION\": \"BIDIR\",\n            \"IOSTANDARD\": \"LVCMOS18\",\n            \"PACKAGE_PIN\": \"AW35\"\n        },\n        \"d0\": {\n            \"PIO_DIRECTION\": \"BIDIR\",\n            \"IOSTANDARD\": \"LVCMOS18\",\n            \"PACKAGE_PIN\": \"AY29\"\n        },\n        \"d1\": {\n            \"PIO_DIRECTION\": \"BIDIR\",\n            \"IOSTANDARD\": \"LVCMOS18\",\n            \"PACKAGE_PIN\": \"AM28\"\n        },\n        \"d2\": {\n            \"PIO_DIRECTION\": \"BIDIR\",\n            \"IOSTANDARD\": \"LVCMOS18\",\n            \"PACKAGE_PIN\": \"AL25\"\n        },\n        \"d3\": {\n            \"PIO_DIRECTION\": \"BIDIR\",\n            \"IOSTANDARD\": \"LVCMOS18\",\n            \"PACKAGE_PIN\": \"AL26\"\n        }\n    },\n    \"LED\": {\n        \"LED[0]\": {\n            \"PIO_DIRECTION\": \"OUTPUT\",\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"AR22\"\n        },\n        \"LED[1]\": {\n            \"PIO_DIRECTION\": \"OUTPUT\",\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"AR23\"\n        }\n    },\n    \"PCIE\": {\n        \"PCIE_SYS_RESETN\": {\n            \"IOSTANDARD\": \"LVCMOS18\",\n            \"PACKAGE_PIN\": \"AY35\"\n        },\n        \"PCIE_PRSNT_B_LS\": {\n            \"IOSTANDARD\": \"LVCMOS18\",\n            \"PACKAGE_PIN\": \"AR35\"\n        },\n        \"PCIE_WAKE\": {\n            \"IOSTANDARD\": \"LVCMOS18\",\n            \"PACKAGE_PIN\": \"AT31\"\n        },\n        \"PCIE_SYSCLK_N\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"AB8\"\n        },\n        \"PCIE_SYSCLK_P\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"AB7\"\n        }\n    },\n    \"PMODCTRL\": {\n        \"DIR_JA[0]\": {\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"AT16\"\n        },\n        \"DIR_JA[1]\": {\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"AU16\"\n        },\n        \"DIR_JA[2]\": {\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"BB19\"\n        },\n        \"DIR_JA[3]\": {\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"AV20\"\n        },\n        \"DIR_JA[4]\": {\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"AW20\"\n        },\n        \"DIR_JA[5]\": {\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"BA17\"\n        },\n        \"DIR_JA[6]\": {\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"BB17\"\n        },\n        \"DIR_JA[7]\": {\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"AY20\"\n        },\n        \"PMOD_OE_B\": {\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"C40\"\n        }\n    },\n    \"PMODData\": {\n        \"JA_FPGA[0]\": {\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"AW18\"\n        },\n        \"JA_FPGA[1]\": {\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"AW17\"\n        },\n        \"JA_FPGA[2]\": {\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"AU19\"\n        },\n        \"JA_FPGA[3]\": {\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"AV19\"\n        },\n        \"JA_FPGA[4]\": {\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"AT20\"\n        },\n        \"JA_FPGA[5]\": {\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"AT19\"\n        },\n        \"JA_FPGA[6]\": {\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"AV16\"\n        },\n        \"JA_FPGA[7]\": {\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"AW16\"\n        }\n    },\n    \"POWER\": {\n        \"PCON_ALERT_B\": {\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"J41\"\n        },\n        \"PCON_AUXFAULT_B\": {\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"M41\"\n        },\n        \"PCON_FAULT\": {\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"N40\"\n        },\n        \"PWR_SNS\": {\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"AW42\"\n        }\n    },\n    \"QDRIIA\": {\n        \"QDRII_SYSCLK_N\": {\n            \"IOSTANDARD\": \"LVDS\",\n\t\t\t\"DIFF_TERM\": \"TRUE\",\n            \"PACKAGE_PIN\": \"AD33\"\n        },\n        \"QDRII_SYSCLK_P\": {\n            \"IOSTANDARD\": \"LVDS\",\n\t\t\t\"DIFF_TERM\": \"TRUE\",\n            \"PACKAGE_PIN\": \"AD32\"\n        }\n    },\n    \"QDRIIC\": {\n        \"QDRIIC_SYSCLK_N\": {\n            \"IOSTANDARD\": \"LVDS\",\n\t\t\t\"DIFF_TERM\": \"TRUE\",\n            \"PACKAGE_PIN\": \"AU13\"\n        },\n        \"QDRIIC_SYSCLK_P\": {\n            \"IOSTANDARD\": \"LVDS\",\n\t\t\t\"DIFF_TERM\": \"TRUE\",\n            \"PACKAGE_PIN\": \"AU14\"\n        }\n    },\n    \"MICRO_SD\": {\n        \"SD_CCLK\": {\n            \"IOSTANDARD\": \"LVCMOS18\",\n            \"PACKAGE_PIN\": \"AJ25\"\n        },\n        \"SD_CD\": {\n            \"IOSTANDARD\": \"LVCMOS18\",\n            \"PACKAGE_PIN\": \"AW35\"\n        },\n        \"SD_CMD\": {\n            \"IOSTANDARD\": \"LVCMOS18\",\n            \"PACKAGE_PIN\": \"AJ26\"\n        },\n        \"SD_D[0]\": {\n            \"IOSTANDARD\": \"LVCMOS18\",\n            \"PACKAGE_PIN\": \"AY29\"\n        },\n        \"SD_D[1]\": {\n            \"IOSTANDARD\": \"LVCMOS18\",\n            \"PACKAGE_PIN\": \"AM28\"\n        },\n        \"SD_D[2]\": {\n            \"IOSTANDARD\": \"LVCMOS18\",\n            \"PACKAGE_PIN\": \"AL25\"\n        },\n        \"SD_D[3]\": {\n            \"IOSTANDARD\": \"LVCMOS18\",\n            \"PACKAGE_PIN\": \"AL26\"\n        }\n    },\n    \"SFPCLK\": {\n        \"SFP_CLK_ALARM_B\": {\n            \"PIO_DIRECTION\": \"INPUT\",\n            \"IOSTANDARD\": \"LVCMOS18\",\n            \"PACKAGE_PIN\": \"AM29\"\n        },\n        \"SFP_CLK_RST\": {\n            \"PIO_DIRECTION\": \"INPUT\",\n            \"IOSTANDARD\": \"LVCMOS18\",\n            \"PACKAGE_PIN\": \"BA29\"\n        }\n    },\n    \"SFP\": {\n        \"SFP_REFCLK_N\": {\n            \"PIO_DIRECTION\": \"INPUT\",\n            \"PACKAGE_PIN\": \"E9\"\n        },\n        \"SFP_REFCLK_P\": {\n            \"PIO_DIRECTION\": \"INPUT\",\n            \"PACKAGE_PIN\": \"E10\"\n        }\n    },\n    \"SFPA\": {\n        \"ETH1_LED[0]\": {\n            \"PIO_DIRECTION\": \"OUTPUT\",\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"G13\"\n        },\n        \"ETH1_LED[1]\": {\n            \"PIO_DIRECTION\": \"OUTPUT\",\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"L15\"\n        },\n        \"ETH1_MOD_DETECT\": {\n            \"PIO_DIRECTION\": \"INPUT\",\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"N18\"\n        },\n        \"ETH1_RS[0]\": {\n            \"PIO_DIRECTION\": \"OUTPUT\",\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"N19\"\n        },\n        \"ETH1_RS[1]\": {\n            \"PIO_DIRECTION\": \"OUTPUT\",\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"P18\"\n        },\n        \"ETH1_RX_LOS\": {\n            \"PIO_DIRECTION\": \"INPUT\",\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"L17\"\n        },\n        \"ETH1_TX_DISABLE\": {\n            \"PIO_DIRECTION\": \"OUTPUT\",\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"M18\"\n        },\n        \"ETH1_TX_FAULT\": {\n            \"PIO_DIRECTION\": \"INPUT\",\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"M19\"\n        },\n        \"ETH1_RX_p\": {\n            \"PIO_DIRECTION\": \"INPUT\",\n            \"PACKAGE_PIN\": \"A6\"\n        },\n        \"ETH1_RX_n\": {\n            \"PIO_DIRECTION\": \"INPUT\",\n            \"PACKAGE_PIN\": \"A5\"\n        },\n        \"ETH1_TX_p\": {\n            \"PIO_DIRECTION\": \"OUTPUT\",\n            \"PACKAGE_PIN\": \"B4\"\n        },\n        \"ETH1_TX_n\": {\n            \"PIO_DIRECTION\": \"OUTPUT\",\n            \"PACKAGE_PIN\": \"B3\"\n        }\n    },\n    \"SFPB\": {\n        \"ETH2_LED[0]\": {\n            \"PIO_DIRECTION\": \"OUTPUT\",\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"AL22\"\n        },\n        \"ETH2_LED[1]\": {\n            \"PIO_DIRECTION\": \"OUTPUT\",\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"BA20\"\n        },\n        \"ETH2_MOD_DETECT\": {\n            \"PIO_DIRECTION\": \"INPUT\",\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"L19\"\n        },\n        \"ETH2_RS[0]\": {\n            \"PIO_DIRECTION\": \"OUTPUT\",\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"P20\"\n        },\n        \"ETH2_RS[1]\": {\n            \"PIO_DIRECTION\": \"OUTPUT\",\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"N20\"\n        },\n        \"ETH2_RX_LOS\": {\n            \"PIO_DIRECTION\": \"INPUT\",\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"L20\"\n        },\n        \"ETH2_TX_DISABLE\": {\n            \"PIO_DIRECTION\": \"OUTPUT\",\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"B31\"\n        },\n        \"ETH2_TX_FAULT\": {\n            \"PIO_DIRECTION\": \"INPUT\",\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"C26\"\n        },\n        \"ETH2_RX_p\": {\n            \"PIO_DIRECTION\": \"INPUT\",\n            \"PACKAGE_PIN\": \"B8\"\n        },\n        \"ETH2_RX_n\": {\n            \"PIO_DIRECTION\": \"INPUT\",\n            \"PACKAGE_PIN\": \"B7\"\n        },\n        \"ETH2_TX_p\": {\n            \"PIO_DIRECTION\": \"OUTPUT\",\n            \"PACKAGE_PIN\": \"C2\"\n        },\n        \"ETH2_TX_n\": {\n            \"PIO_DIRECTION\": \"OUTPUT\",\n            \"PACKAGE_PIN\": \"C1\"\n        }\n    },\n    \"SFPC\": {\n        \"ETH3_LED[0]\": {\n            \"PIO_DIRECTION\": \"OUTPUT\",\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"AY18\"\n        },\n        \"ETH3_LED[1]\": {\n            \"PIO_DIRECTION\": \"OUTPUT\",\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"AY17\"\n        },\n        \"ETH3_MOD_DETECT\": {\n            \"PIO_DIRECTION\": \"INPUT\",\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"J37\"\n        },\n        \"ETH3_RS[0]\": {\n            \"PIO_DIRECTION\": \"OUTPUT\",\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"F39\"\n        },\n        \"ETH3_RS[1]\": {\n            \"PIO_DIRECTION\": \"OUTPUT\",\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"G36\"\n        },\n        \"ETH3_RX_LOS\": {\n            \"PIO_DIRECTION\": \"INPUT\",\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"G37\"\n        },\n        \"ETH3_TX_DISABLE\": {\n            \"PIO_DIRECTION\": \"OUTPUT\",\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"J38\"\n        },\n        \"ETH3_TX_FAULT\": {\n            \"PIO_DIRECTION\": \"INPUT\",\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"E39\"\n        },\n        \"ETH3_RX_p\": {\n            \"PIO_DIRECTION\": \"INPUT\",\n            \"PACKAGE_PIN\": \"C6\"\n        },\n        \"ETH3_RX_n\": {\n            \"PIO_DIRECTION\": \"INPUT\",\n            \"PACKAGE_PIN\": \"C5\"\n        },\n        \"ETH3_TX_p\": {\n            \"PIO_DIRECTION\": \"OUTPUT\",\n            \"PACKAGE_PIN\": \"D4\"\n        },\n        \"ETH3_TX_n\": {\n            \"PIO_DIRECTION\": \"OUTPUT\",\n            \"PACKAGE_PIN\": \"D3\"\n        }\n    },\n    \"SFPD\": {\n        \"ETH4_LED[0]\": {\n            \"PIO_DIRECTION\": \"OUTPUT\",\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"P31\"\n        },\n        \"ETH4_LED[1]\": {\n            \"PIO_DIRECTION\": \"OUTPUT\",\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"K32\"\n        },\n        \"ETH4_MOD_DETECT\": {\n            \"PIO_DIRECTION\": \"INPUT\",\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"H36\"\n        },\n        \"ETH4_RS[0]\": {\n            \"PIO_DIRECTION\": \"OUTPUT\",\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"H38\"\n        },\n        \"ETH4_RS[1]\": {\n            \"PIO_DIRECTION\": \"OUTPUT\",\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"G38\"\n        },\n        \"ETH4_RX_LOS\": {\n            \"PIO_DIRECTION\": \"INPUT\",\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"J36\"\n        },\n        \"ETH4_TX_DISABLE\": {\n            \"PIO_DIRECTION\": \"OUTPUT\",\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"L21\"\n        },\n        \"ETH4_TX_FAULT\": {\n            \"PIO_DIRECTION\": \"INPUT\",\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"J26\"\n        },\n        \"ETH4_RX_p\": {\n            \"PIO_DIRECTION\": \"INPUT\",\n            \"PACKAGE_PIN\": \"D8\"\n        },\n        \"ETH4_RX_n\": {\n            \"PIO_DIRECTION\": \"INPUT\",\n            \"PACKAGE_PIN\": \"D7\"\n        },\n        \"ETH4_TX_p\": {\n            \"PIO_DIRECTION\": \"OUTPUT\",\n            \"PACKAGE_PIN\": \"E2\"\n        },\n        \"ETH4_TX_n\": {\n            \"PIO_DIRECTION\": \"OUTPUT\",\n            \"PACKAGE_PIN\": \"E1\"\n        }\n    },\n    \"SI570\": {\n        \"USERCLK_N\": {\n            \"PIO_DIRECTION\": \"INPUT\",\n            \"IOSTANDARD\": \"LVDS\",\n\t\t\t\"DIFF_TERM\": \"TRUE\",\n            \"PACKAGE_PIN\": \"AU27\"\n        },\n        \"USERCLK_P\": {\n            \"PIO_DIRECTION\": \"INPUT\",\n            \"IOSTANDARD\": \"LVDS\",\n\t\t\t\"DIFF_TERM\": \"TRUE\",\n            \"PACKAGE_PIN\": \"AU26\"\n        }\n    },\n    \"uart\": {\n        \"UART_CTS\": {\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"BA16\"\n        },\n        \"UART_RTS\": {\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"BB16\"\n        },\n        \"d_out\": {\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"BA19\",\n\t    \"PIO_DIRECTION\": \"OUTPUT\"\n        },\n        \"d_in\": {\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"AY19\",\n\t    \"PIO_DIRECTION\": \"INPUT\"\n        }\n    },\n    \"pins\": {\n        \"userClk_p\": {\n            \"PACKAGE_PIN\": \"bogus\",\n            \"IOSTANDARD\": \"LVDS_25\",\n            \"DIFF_TERM\": \"TRUE\",\n            \"PIO_DIRECTION\": \"INPUT\"\n        },\n        \"userClk_n\": {\n            \"PACKAGE_PIN\": \"bogus\",\n            \"IOSTANDARD\": \"LVDS_25\",\n            \"DIFF_TERM\": \"TRUE\",\n            \"PIO_DIRECTION\": \"INPUT\"\n        },\n        \"smaUserClk_p\": {\n            \"PACKAGE_PIN\": \"bogus\",\n            \"IOSTANDARD\": \"LVDS_25\",\n            \"DIFF_TERM\": \"TRUE\",\n            \"PIO_DIRECTION\": \"OUTPUT\"\n        },\n        \"smaUserClk_n\": {\n            \"PACKAGE_PIN\": \"bogus\",\n            \"IOSTANDARD\": \"LVDS_25\",\n            \"DIFF_TERM\": \"TRUE\",\n            \"PIO_DIRECTION\": \"OUTPUT\"\n        },\n        \"mgtRefClk_p\": {\n            \"PACKAGE_PIN\": \"bogus\",\n            \"IOSTANDARD\": \"LVDS_25\",\n            \"DIFF_TERM\": \"TRUE\",\n            \"PIO_DIRECTION\": \"INPUT\"\n        },\n        \"mgtRefClk_n\": {\n            \"PACKAGE_PIN\": \"bogus\",\n            \"IOSTANDARD\": \"LVDS_25\",\n            \"DIFF_TERM\": \"TRUE\",\n            \"PIO_DIRECTION\": \"INPUT\"\n        },\n        \"mgtRx_p\": {\n            \"PACKAGE_PIN\": \"bogus\",\n            \"DIFF_TERM\": \"TRUE\",\n            \"PIO_DIRECTION\": \"INPUT\"\n        },\n        \"mgtRx_n\": {\n            \"PACKAGE_PIN\": \"bogus\",\n            \"DIFF_TERM\": \"TRUE\",\n            \"PIO_DIRECTION\": \"INPUT\"\n        },\n        \"mgtTx_p\": {\n            \"PACKAGE_PIN\": \"bogus\",\n            \"DIFF_TERM\": \"TRUE\",\n            \"PIO_DIRECTION\": \"OUTPUT\"\n        },\n        \"mgtTx_n\": {\n            \"PACKAGE_PIN\": \"bogus\",\n            \"DIFF_TERM\": \"TRUE\",\n            \"PIO_DIRECTION\": \"OUTPUT\"\n        },\n        \"uart_d_in\": {\n            \"PACKAGE_PIN\": \"bogus\",\n            \"IOSTANDARD\": \"LVCMOS25\",\n            \"PIO_DIRECTION\": \"INPUT\"\n        },\n        \"uart_d_out\": {\n            \"PACKAGE_PIN\": \"bogus\",\n            \"IOSTANDARD\": \"LVCMOS25\",\n            \"PIO_DIRECTION\": \"OUTPUT\"\n        }\n    }\n}\n\n\n"
  },
  {
    "path": "boardinfo/parallella.json",
    "content": "{\n    \"options\": {\n        \"bsvdefines\" : [\"XILINX=1\", \"ZYNQ\", \"ZynqHostInterface\", \"PhysAddrWidth=32\",\n\t\t\t\"CONNECTAL_BITS_DEPENDENCES=hw/mkTop.bit\", \"CONNECTAL_RUN_SCRIPT=$(CONNECTALDIR)/scripts/run.android\",\n\t\t\t\"CONNECTAL_EXENAME=android.exe\", \"CONNECTAL_EXENAME2=android.exe2\"],\n        \"os\" : \"ubuntu\",\n        \"partname\" : \"xc7z020clg400-1\",\n        \"constraints\": [],\n        \"implconstraints\": [\"constraints/xilinx/zc7z020clg400.xdc\", \"constraints/xilinx/parallella.xdc\"],\n        \"rewireclockstring\" : \"tclzynqrewireclock\",\n        \"TOP\" : \"ZynqTop\",\n        \"runscript\" : \"run.android\",\n        \"CONNECTALFLAGS\" : [],\n        \"need_pcie\" : \"unused\"\n    }\n}\n"
  },
  {
    "path": "boardinfo/ultra96.json",
    "content": "{\n    \"options\": {\n        \"bsvdefines\" : [\"XILINX=1\", \"ZYNQ\", \"ZynqUltrascale\", \"ZynqHostInterface\", \"PhysAddrWidth=40\",\n\t\t\t\"CONNECTAL_BITS_DEPENDENCES=hw/mkTop.bit\", \"CONNECTAL_RUN_SCRIPT=$(CONNECTALDIR)/scripts/run.pcietest\",\n\t\t\t\"CONNECTAL_EXENAME=ubuntu.exe\", \"CONNECTAL_EXENAME2=ubuntu.exe2\"],\n        \"os\" : \"ubuntu\",\n\t\"arch\" : \"arm64\",\n\t\"toolchain\" : \"aarch64-linux-gnu-\",\n        \"partname\" : \"xczu3eg-sbva484-1-i\",\n        \"rewireclockstring\" : \"tclzynqrewireclock\",\n        \"constraints\": [],\n        \"implconstraints\": [\"constraints/xilinx/zcu102.xdc\"],\n        \"TOP\" : \"ZynqUltraTop\",\n        \"runscript\" : \"run.pcietest\",\n        \"CONNECTALFLAGS\" : [\"--mainclockperiod=5\", \"--derivedclockperiod=2.5\"],\n\t\"ZYNQ_MPSOC\": \"zynq_ultra_ps_e\"\n    },\n    \"fmc1\": {\n\t\"LA00_p_CC\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n        },\n\t\"LA00_n_CC\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n        },\n\t\"LA01_p_CC\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n        },\n\t\"LA01_n_CC\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n        },\n\t\"LA02_p\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n        },\n\t\"LA02_n\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n        },\n\t\"LA03_p\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n        },\n\t\"LA03_n\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n        },\n\t\"LA04_p\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n        },\n\t\"LA04_n\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n        },\n\t\"LA05_p\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n        },\n\t\"LA05_n\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n        },\n\t\"LA06_p\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n        },\n\t\"LA06_n\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n        },\n\t\"LA07_p\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n        },\n\t\"LA07_n\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n        },\n\t\"LA08_p\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n        },\n\t\"LA08_n\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n        },\n\t\"LA09_p\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n        },\n\t\"LA09_n\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n        },\n\t\"LA10_p\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n        },\n\t\"LA10_n\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n        },\n\t\"LA11_p\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n        },\n\t\"LA11_n\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n        },\n\t\"LA12_p\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n        },\n\t\"LA12_n\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n        },\n\t\"LA13_p\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n        },\n\t\"LA13_n\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n        },\n\t\"LA14_p\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n        },\n\t\"LA14_n\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n        },\n\t\"LA15_p\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n        },\n\t\"LA15_n\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n        },\n\t\"LA16_p\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n        },\n\t\"LA16_n\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n        },\n\t\"LA17_p_CC\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n        },\n\t\"LA17_n_CC\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n        },\n\t\"LA18_p_CC\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n        },\n\t\"LA18_n_CC\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n        },\n\t\"LA19_p\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n        },\n\t\"LA19_n\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n        },\n\t\"CLK0_M2C_p\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n        },\n\t\"CLK0_M2C_n\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n        }\n    },\n    \"fmc2\": {\n\t\"LA00_p_CC\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n\t},\n\t\"LA00_n_CC\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n\t},\n\t\"LA01_p_CC\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n\t},\n\t\"LA01_n_CC\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n\t},\n\t\"LA02_p\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n\t},\n\t\"LA02_n\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n\t},\n\t\"LA03_p\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n\t},\n\t\"LA03_n\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n\t},\n\t\"LA04_p\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n\t},\n\t\"LA04_n\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n\t},\n\t\"LA05_p\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n\t},\n\t\"LA05_n\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n\t},\n\t\"LA06_p\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n\t},\n\t\"LA06_n\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n\t},\n\t\"LA07_p\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n\t},\n\t\"LA07_n\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n\t},\n\t\"LA08_p\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n\t},\n\t\"LA08_n\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n\t},\n\t\"LA09_p\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n\t},\n\t\"LA09_n\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n\t},\n\t\"LA10_p\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n\t},\n\t\"LA10_n\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n\t},\n\t\"LA11_p\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n\t},\n\t\"LA11_n\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n\t},\n\t\"LA12_p\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n\t},\n\t\"LA12_n\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n\t},\n\t\"LA13_p\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n\t},\n\t\"LA13_n\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n\t},\n\t\"LA14_p\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n\t},\n\t\"LA14_n\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n\t},\n\t\"LA15_p\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n\t},\n\t\"LA15_n\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n\t},\n\t\"LA16_p\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n\t},\n\t\"LA16_n\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n\t},\n\t\"LA17_p_CC\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n\t},\n\t\"LA17_n_CC\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n\t},\n\t\"LA18_p_CC\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n\t},\n\t\"LA18_n_CC\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n\t},\n\t\"LA19_p\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n\t},\n\t\"LA19_n\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n\t},\n\t\"CLK0_M2C_p\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n\t},\n\t\"CLK0_M2C_n\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n\t}\n    },\n    \"leds\" : {\n    \t\"L0\" : {\n\t     \"PACKAGE_PIN\" : \"TBD\",\n             \"IOSTANDARD\" : \"LVCMOS25\",\n\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t     },\n    \t\"L1\" : {\n\t     \"PACKAGE_PIN\" : \"TBD\",\n             \"IOSTANDARD\" : \"LVCMOS25\",\n\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t     },\n    \t\"L2\" : {\n\t     \"PACKAGE_PIN\" : \"TBD\",\n             \"IOSTANDARD\" : \"LVCMOS25\",\n\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t     },\n    \t\"L3\" : {\n\t     \"PACKAGE_PIN\" : \"TBD\",\n             \"IOSTANDARD\" : \"LVCMOS25\",\n\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t     },\n    \t\"L4\" : {\n\t     \"PACKAGE_PIN\" : \"TBD\",\n             \"IOSTANDARD\" : \"LVCMOS25\",\n\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t     },\n    \t\"L5\" : {\n\t     \"PACKAGE_PIN\" : \"TBD\",\n             \"IOSTANDARD\" : \"LVCMOS25\",\n\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t     },\n    \t\"L6\" : {\n\t     \"PACKAGE_PIN\" : \"TBD\",\n             \"IOSTANDARD\" : \"LVCMOS25\",\n\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t     },\n    \t\"L7\" : {\n\t     \"PACKAGE_PIN\" : \"TBD\",\n             \"IOSTANDARD\" : \"LVCMOS25\",\n\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t     }\n    },  \n    \"xadc\" : {\n    \t\"L0\" : {\n\t     \"PACKAGE_PIN\" : \"TBD\",\n             \"IOSTANDARD\" : \"LVCMOS25\",\n\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t     },\n    \t\"L1\" : {\n\t     \"PACKAGE_PIN\" : \"TBD\",\n             \"IOSTANDARD\" : \"LVCMOS25\",\n\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t     },\n    \t\"L2\" : {\n\t     \"PACKAGE_PIN\" : \"TBD\",\n             \"IOSTANDARD\" : \"LVCMOS25\",\n\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t     },\n    \t\"L3\" : {\n\t     \"PACKAGE_PIN\" : \"TBD\",\n             \"IOSTANDARD\" : \"LVCMOS25\",\n\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t     }\n    },\n    \"hdmi\" : {\n        \"clock\" : {\n             \"PACKAGE_PIN\" : \"TBD\",\n\t     \"IOSTANDARD\" : \"LVCMOS25\",\n             \"PIO_DIRECTION\": \"OUTPUT\"\n\t     },\n        \"hsync\" : {\n             \"PACKAGE_PIN\" : \"TBD\",\n\t     \"IOSTANDARD\" : \"LVCMOS25\",\n             \"PIO_DIRECTION\": \"OUTPUT\"\n\t     },\n        \"vsync\" : {\n             \"PACKAGE_PIN\" : \"TBD\",\n\t     \"IOSTANDARD\" : \"LVCMOS25\",\n             \"PIO_DIRECTION\": \"OUTPUT\"\n\t     },\n        \"de\" : {\n             \"PACKAGE_PIN\" : \"TBD\",\n\t     \"IOSTANDARD\" : \"LVCMOS25\",\n             \"PIO_DIRECTION\": \"OUTPUT\"\n\t     },\n        \"data[0]\" : {\n             \"PACKAGE_PIN\" : \"TBD\",\n\t     \"IOSTANDARD\" : \"LVCMOS25\",\n             \"PIO_DIRECTION\": \"OUTPUT\"\n\t     },\n        \"data[1]\" : {\n             \"PACKAGE_PIN\" : \"TBD\",\n\t     \"IOSTANDARD\" : \"LVCMOS25\",\n             \"PIO_DIRECTION\": \"OUTPUT\"\n\t     },\n        \"data[2]\" : {\n             \"PACKAGE_PIN\" : \"TBD\",\n\t     \"IOSTANDARD\" : \"LVCMOS25\",\n             \"PIO_DIRECTION\": \"OUTPUT\"\n\t     },\n        \"data[3]\" : {\n             \"PACKAGE_PIN\" : \"TBD\",\n\t     \"IOSTANDARD\" : \"LVCMOS25\",\n             \"PIO_DIRECTION\": \"OUTPUT\"\n\t     },\n        \"data[4]\" : {\n             \"PACKAGE_PIN\" : \"TBD\",\n\t     \"IOSTANDARD\" : \"LVCMOS25\",\n             \"PIO_DIRECTION\": \"OUTPUT\"\n\t     },\n        \"data[5]\" : {\n             \"PACKAGE_PIN\" : \"TBD\",\n\t     \"IOSTANDARD\" : \"LVCMOS25\",\n             \"PIO_DIRECTION\": \"OUTPUT\"\n\t     },\n        \"data[6]\" : {\n             \"PACKAGE_PIN\" : \"TBD\",\n\t     \"IOSTANDARD\" : \"LVCMOS25\",\n             \"PIO_DIRECTION\": \"OUTPUT\"\n\t     },\n        \"data[7]\" : {\n             \"PACKAGE_PIN\" : \"TBD\",\n\t     \"IOSTANDARD\" : \"LVCMOS25\",\n             \"PIO_DIRECTION\": \"OUTPUT\"\n\t     },\n        \"data[8]\" : {\n             \"PACKAGE_PIN\" : \"TBD\",\n\t     \"IOSTANDARD\" : \"LVCMOS25\",\n             \"PIO_DIRECTION\": \"OUTPUT\"\n\t     },\n        \"data[9]\" : {\n             \"PACKAGE_PIN\" : \"TBD\",\n\t     \"IOSTANDARD\" : \"LVCMOS25\",\n             \"PIO_DIRECTION\": \"OUTPUT\"\n\t     },\n        \"data[10]\" : {\n             \"PACKAGE_PIN\" : \"TBD\",\n\t     \"IOSTANDARD\" : \"LVCMOS25\",\n             \"PIO_DIRECTION\": \"OUTPUT\"\n\t     },\n        \"data[11]\" : {\n             \"PACKAGE_PIN\" : \"TBD\",\n\t     \"IOSTANDARD\" : \"LVCMOS25\",\n             \"PIO_DIRECTION\": \"OUTPUT\"\n\t     },\n        \"data[12]\" : {\n             \"PACKAGE_PIN\" : \"TBD\",\n\t     \"IOSTANDARD\" : \"LVCMOS25\",\n             \"PIO_DIRECTION\": \"OUTPUT\"\n\t     },\n        \"data[13]\" : {\n             \"PACKAGE_PIN\" : \"TBD\",\n\t     \"IOSTANDARD\" : \"LVCMOS25\",\n             \"PIO_DIRECTION\": \"OUTPUT\"\n\t     },\n        \"data[14]\" : {\n             \"PACKAGE_PIN\" : \"TBD\",\n\t     \"IOSTANDARD\" : \"LVCMOS25\",\n             \"PIO_DIRECTION\": \"OUTPUT\"\n\t     },\n        \"data[15]\" : {\n             \"PACKAGE_PIN\" : \"TBD\",\n\t     \"IOSTANDARD\" : \"LVCMOS25\",\n             \"PIO_DIRECTION\": \"OUTPUT\"\n\t     }\n    }\n}\n"
  },
  {
    "path": "boardinfo/v2000t.json",
    "content": "{\n    \"options\": {\n        \"bsvdefines\" : [\"XILINX=1\", \"Virtex7\", \"PCIE\", \"PcieHostInterface\", \"PhysAddrWidth=40\",\n\t\t       \t\"CONNECTAL_BITS_DEPENDENCES=hw/mkTop.bit\", \"CONNECTAL_RUN_SCRIPT=$(CONNECTALDIR)/scripts/run.pcietest\"],\n        \"os\" : \"ubuntu\",\n        \"partname\" : \"xc7v2000tflg1925-2\",\n        \"need_pcie\" : \"x7_gen1x8\",\n        \"TOP\" : \"PcieTop\",\n        \"constraints\": [],\n        \"implconstraints\": [\"constraints/xilinx/v2000t.xdc\"],\n        \"runscript\" : \"run.pcietest\",\n        \"CONNECTALFLAGS\" : [],\n        \"rewireclockstring\" : \"\"\n    },\n    \"fmc\": {\n    }\n}\n"
  },
  {
    "path": "boardinfo/vc707.json",
    "content": "{\n    \"options\": {\n        \"bsvdefines\" : [\"XILINX=1\", \"Virtex7\", \"PCIE\", \"PCIE1\", \"PcieHostInterface\", \"PhysAddrWidth=40\", \"PcieLanes=8\",\n\t\t       \t\"CONNECTAL_BITS_DEPENDENCES=hw/mkTop.bit\", \"CONNECTAL_RUN_SCRIPT=$(CONNECTALDIR)/scripts/run.pcietest\"],\n        \"os\" : \"ubuntu\",\n        \"partname\" : \"xc7vx485tffg1761-2\",\n        \"need_pcie\" : \"x7_gen1x8\",\n        \"TOP\" : \"PcieTop\",\n        \"constraints\": [\"constraints/xilinx/vc707.xdc\"],\n        \"implconstraints\": [\"constraints/xilinx/vc707.xdc\", \"constraints/xilinx/pcie-clocks.xdc\"],\n        \"runscript\" : \"run.pcietest\",\n        \"CONNECTALFLAGS\" : [\"--mainclockperiod=8\", \"--derivedclockperiod=4\", \"--pcieclockperiod=8\"],\n        \"rewireclockstring\" : \"\"\n    },\n    \"fmc\": {\n    },\n    \"bpi_flash\": {\n\t\t \"data[0]\" : {\n\t\t\t     \"LOC\" : \"AM36\",\n\t\t\t     \"IOSTANDARD\" : \"LVCMOS18\",\n\t\t\t     \"PIO_DIRECTION\" : \"BIDIR\"\n\t\t },\n\t\t \"data[1]\" : {\n\t\t\t     \"LOC\" : \"AN36\",\n\t\t\t     \"IOSTANDARD\" : \"LVCMOS18\",\n\t\t\t     \"PIO_DIRECTION\" : \"BIDIR\"\n\t\t },\n\t\t \"data[2]\" : {\n\t\t\t     \"LOC\" : \"AJ36\",\n\t\t\t     \"IOSTANDARD\" : \"LVCMOS18\",\n\t\t\t     \"PIO_DIRECTION\" : \"BIDIR\"\n\t\t },\n\t\t \"data[3]\" : {\n\t\t\t     \"LOC\" : \"AJ37\",\n\t\t\t     \"IOSTANDARD\" : \"LVCMOS18\",\n\t\t\t     \"PIO_DIRECTION\" : \"BIDIR\"\n\t\t },\n\t\t \"data[4]\" : {\n\t\t\t     \"LOC\" : \"AK37\",\n\t\t\t     \"IOSTANDARD\" : \"LVCMOS18\",\n\t\t\t     \"PIO_DIRECTION\" : \"BIDIR\"\n\t\t },\n\t\t \"data[5]\" : {\n\t\t\t     \"LOC\" : \"AL37\",\n\t\t\t     \"IOSTANDARD\" : \"LVCMOS18\",\n\t\t\t     \"PIO_DIRECTION\" : \"BIDIR\"\n\t\t },\n\t\t \"data[6]\" : {\n\t\t\t     \"LOC\" : \"AN35\",\n\t\t\t     \"IOSTANDARD\" : \"LVCMOS18\",\n\t\t\t     \"PIO_DIRECTION\" : \"BIDIR\"\n\t\t },\n\t\t \"data[7]\" : {\n\t\t\t     \"LOC\" : \"AP35\",\n\t\t\t     \"IOSTANDARD\" : \"LVCMOS18\",\n\t\t\t     \"PIO_DIRECTION\" : \"BIDIR\"\n\t\t },\n\t\t \"data[8]\" : {\n\t\t\t     \"LOC\" : \"AM37\",\n\t\t\t     \"IOSTANDARD\" : \"LVCMOS18\",\n\t\t\t     \"PIO_DIRECTION\" : \"BIDIR\"\n\t\t },\n\t\t \"data[9]\" : {\n\t\t\t     \"LOC\" : \"AG33\",\n\t\t\t     \"IOSTANDARD\" : \"LVCMOS18\",\n\t\t\t     \"PIO_DIRECTION\" : \"BIDIR\"\n\t\t },\n\t\t \"data[10]\" : {\n\t\t\t     \"LOC\" : \"AH33\",\n\t\t\t     \"IOSTANDARD\" : \"LVCMOS18\",\n\t\t\t     \"PIO_DIRECTION\" : \"BIDIR\"\n\t\t },\n\t\t \"data[11]\" : {\n\t\t\t     \"LOC\" : \"AK35\",\n\t\t\t     \"IOSTANDARD\" : \"LVCMOS18\",\n\t\t\t     \"PIO_DIRECTION\" : \"BIDIR\"\n\t\t },\n\t\t \"data[12]\" : {\n\t\t\t     \"LOC\" : \"AL35\",\n\t\t\t     \"IOSTANDARD\" : \"LVCMOS18\",\n\t\t\t     \"PIO_DIRECTION\" : \"BIDIR\"\n\t\t },\n\t\t \"data[13]\" : {\n\t\t\t     \"LOC\" : \"AJ31\",\n\t\t\t     \"IOSTANDARD\" : \"LVCMOS18\",\n\t\t\t     \"PIO_DIRECTION\" : \"BIDIR\"\n\t\t },\n\t\t \"data[14]\" : {\n\t\t\t     \"LOC\" : \"AH34\",\n\t\t\t     \"IOSTANDARD\" : \"LVCMOS18\",\n\t\t\t     \"PIO_DIRECTION\" : \"BIDIR\"\n\t\t },\n\t\t \"data[15]\" : {\n\t\t\t     \"LOC\" : \"AJ35\",\n\t\t\t     \"IOSTANDARD\" : \"LVCMOS18\",\n\t\t\t     \"PIO_DIRECTION\" : \"BIDIR\"\n\t\t },\n\t\t \"addr[0]\" : {\n\t\t\t     \"LOC\" : \"AJ28\",\n\t\t\t     \"IOSTANDARD\" : \"LVCMOS18\",\n\t\t\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t\t },\n\t\t \"addr[1]\" : {\n\t\t\t     \"LOC\" : \"AH28\",\n\t\t\t     \"IOSTANDARD\" : \"LVCMOS18\",\n\t\t\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t\t },\n\t\t \"addr[2]\" : {\n\t\t\t     \"LOC\" : \"AG31\",\n\t\t\t     \"IOSTANDARD\" : \"LVCMOS18\",\n\t\t\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t\t },\n\t\t \"addr[3]\" : {\n\t\t\t     \"LOC\" : \"AF30\",\n\t\t\t     \"IOSTANDARD\" : \"LVCMOS18\",\n\t\t\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t\t },\n\t\t \"addr[4]\" : {\n\t\t\t     \"LOC\" : \"AK29\",\n\t\t\t     \"IOSTANDARD\" : \"LVCMOS18\",\n\t\t\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t\t },\n\t\t \"addr[5]\" : {\n\t\t\t     \"LOC\" : \"AK28\",\n\t\t\t     \"IOSTANDARD\" : \"LVCMOS18\",\n\t\t\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t\t },\n\t\t \"addr[6]\" : {\n\t\t\t     \"LOC\" : \"AG29\",\n\t\t\t     \"IOSTANDARD\" : \"LVCMOS18\",\n\t\t\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t\t },\n\t\t \"addr[7]\" : {\n\t\t\t     \"LOC\" : \"AK30\",\n\t\t\t     \"IOSTANDARD\" : \"LVCMOS18\",\n\t\t\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t\t },\n\t\t \"addr[8]\" : {\n\t\t\t     \"LOC\" : \"AJ30\",\n\t\t\t     \"IOSTANDARD\" : \"LVCMOS18\",\n\t\t\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t\t },\n\t\t \"addr[9]\" : {\n\t\t\t     \"LOC\" : \"AH30\",\n\t\t\t     \"IOSTANDARD\" : \"LVCMOS18\",\n\t\t\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t\t },\n\t\t \"addr[10]\" : {\n\t\t\t     \"LOC\" : \"AH29\",\n\t\t\t     \"IOSTANDARD\" : \"LVCMOS18\",\n\t\t\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t\t },\n\t\t \"addr[11]\" : {\n\t\t\t     \"LOC\" : \"AL30\",\n\t\t\t     \"IOSTANDARD\" : \"LVCMOS18\",\n\t\t\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t\t },\n\t\t \"addr[12]\" : {\n\t\t\t     \"LOC\" : \"AL29\",\n\t\t\t     \"IOSTANDARD\" : \"LVCMOS18\",\n\t\t\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t\t },\n\t\t \"addr[13]\" : {\n\t\t\t     \"LOC\" : \"AN33\",\n\t\t\t     \"IOSTANDARD\" : \"LVCMOS18\",\n\t\t\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t\t },\n\t\t \"addr[14]\" : {\n\t\t\t     \"LOC\" : \"AM33\",\n\t\t\t     \"IOSTANDARD\" : \"LVCMOS18\",\n\t\t\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t\t },\n\t\t \"addr[15]\" : {\n\t\t\t     \"LOC\" : \"AM32\",\n\t\t\t     \"IOSTANDARD\" : \"LVCMOS18\",\n\t\t\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t\t },\n\t\t \"addr[16]\" : {\n\t\t\t     \"LOC\" : \"AV41\",\n\t\t\t     \"IOSTANDARD\" : \"LVCMOS18\",\n\t\t\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t\t },\n\t\t \"addr[17]\" : {\n\t\t\t     \"LOC\" : \"AU41\",\n\t\t\t     \"IOSTANDARD\" : \"LVCMOS18\",\n\t\t\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t\t },\n\t\t \"addr[18]\" : {\n\t\t\t     \"LOC\" : \"BA42\",\n\t\t\t     \"IOSTANDARD\" : \"LVCMOS18\",\n\t\t\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t\t },\n\t\t \"addr[19]\" : {\n\t\t\t     \"LOC\" : \"AU42\",\n\t\t\t     \"IOSTANDARD\" : \"LVCMOS18\",\n\t\t\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t\t },\n\t\t \"addr[20]\" : {\n\t\t\t     \"LOC\" : \"AT41\",\n\t\t\t     \"IOSTANDARD\" : \"LVCMOS18\",\n\t\t\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t\t },\n\t\t \"addr[21]\" : {\n\t\t\t     \"LOC\" : \"BA40\",\n\t\t\t     \"IOSTANDARD\" : \"LVCMOS18\",\n\t\t\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t\t },\n\t\t \"addr[22]\" : {\n\t\t\t     \"LOC\" : \"BA39\",\n\t\t\t     \"IOSTANDARD\" : \"LVCMOS18\",\n\t\t\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t\t },\n\t\t \"addr[23]\" : {\n\t\t\t     \"LOC\" : \"BB39\",\n\t\t\t     \"IOSTANDARD\" : \"LVCMOS18\",\n\t\t\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t\t },\n\t\t \"addr[24]\" : {\n\t\t\t     \"LOC\" : \"AW42\",\n\t\t\t     \"IOSTANDARD\" : \"LVCMOS18\",\n\t\t\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t\t },\n\t\t \"addr[25]\" : {\n\t\t\t     \"LOC\" : \"AW41\",\n\t\t\t     \"IOSTANDARD\" : \"LVCMOS18\",\n\t\t\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t\t },\n\t\t \"wait_in_b\" : {\n\t\t\t     \"LOC\" : \"AM34\",\n\t\t\t     \"IOSTANDARD\" : \"LVCMOS18\",\n\t\t\t     \"PIO_DIRECTION\" : \"INPUT\",\n\t\t\t     \"PULLUP\" : \"TRUE\"\n\t\t },\n\t\t \"rst\" : {\n\t\t\t     \"LOC\" : \"_not_usable\",\n\t\t\t     \"IOSTANDARD\" : \"LVCMOS18\",\n\t\t\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t\t },\n\t\t \"oe_b\" : {\n\t\t\t     \"LOC\" : \"BA41\",\n\t\t\t     \"IOSTANDARD\" : \"LVCMOS18\",\n\t\t\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t\t },\n\t\t \"ce_b\" : {\n\t\t\t     \"LOC\" : \"AL36\",\n\t\t\t     \"IOSTANDARD\" : \"LVCMOS18\",\n\t\t\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t\t },\n\t\t \"we_b\" : {\n\t\t\t     \"LOC\" : \"BB41\",\n\t\t\t     \"IOSTANDARD\" : \"LVCMOS18\",\n\t\t\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t\t },\n\t\t \"adv_b\" : {\n\t\t\t     \"LOC\" : \"AY37\",\n\t\t\t     \"IOSTANDARD\" : \"LVCMOS18\",\n\t\t\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t\t }\n    },\t\n    \"uart\": {\n\t\t\"d_in\": {\n\t\t\t\"LOC\": \"AU33\",\n\t\t\t\"IOSTANDARD\": \"LVCMOS18\",\n\t\t\t\"PIO_DIRECTION\": \"INPUT\"\n\t\t},\n\t\t\"d_out\": {\n\t\t\t\"LOC\": \"AU36\",\n\t\t\t\"IOSTANDARD\": \"LVCMOS18\",\n\t\t\t\"PIO_DIRECTION\": \"OUTPUT\"\n\t\t},\n\t\t\"rts\": {\n\t\t\t\"LOC\": \"AR34\",\n\t\t\t\"IOSTANDARD\": \"LVCMOS18\",\n\t\t\t\"PIO_DIRECTION\": \"INPUT\"\n\t\t},\n\t\t\"cts\": {\n\t\t\t\"LOC\": \"AT32\",\n\t\t\t\"IOSTANDARD\": \"LVCMOS18\",\n\t\t\t\"PIO_DIRECTION\": \"OUTPUT\"\n\t\t}\n    },\n    \"sdio\": {\n        \"dat0\": {\n            \"PACKAGE_PIN\": \"AR30\",\n            \"IOSTANDARD\": \"LVCMOS18\",\n            \"PIO_DIRECTION\": \"BIDIR\"\n        },\n        \"dat1\": {\n            \"PACKAGE_PIN\": \"AU31\",\n            \"IOSTANDARD\": \"LVCMOS18\",\n            \"PIO_DIRECTION\": \"BIDIR\"\n        },\n        \"dat2\": {\n            \"PACKAGE_PIN\": \"AV31\",\n            \"IOSTANDARD\": \"LVCMOS18\",\n            \"PIO_DIRECTION\": \"BIDIR\"\n        },\n        \"cd_dat3\": {\n            \"PACKAGE_PIN\": \"AT30\",\n            \"IOSTANDARD\": \"LVCMOS18\",\n            \"PIO_DIRECTION\": \"BIDIR\"\n        },\n        \"clk\": {\n            \"PACKAGE_PIN\": \"AN30\",\n            \"IOSTANDARD\": \"LVCMOS18\",\n            \"PIO_DIRECTION\": \"OUTPUT\"\n        },\n        \"cmd\": {\n            \"PACKAGE_PIN\": \"AP30\",\n            \"IOSTANDARD\": \"LVCMOS18\",\n            \"PIO_DIRECTION\": \"BIDIR\"\n        },\n        \"sddet\": {\n            \"PACKAGE_PIN\": \"AP32\",\n            \"IOSTANDARD\": \"LVCMOS18\",\n            \"PIO_DIRECTION\": \"INPUT\"\n        },\n        \"sdwp\": {\n            \"PACKAGE_PIN\": \"AR32\",\n            \"IOSTANDARD\": \"LVCMOS18\",\n            \"PIO_DIRECTION\": \"INPUT\"\n        }\n    },\n    \"iic_main\": {\n\t\t\"sda\": {\n\t\t\t\"LOC\": \"AU32\",\n\t\t\t\"IOSTANDARD\": \"LVCMOS18\",\n\t\t\t\"PIO_DIRECTION\": \"BIDIR\"\n\t\t},\n\t\t\"scl\": {\n\t\t\t\"LOC\": \"AT35\",\n\t\t\t\"IOSTANDARD\": \"LVCMOS18\",\n\t\t\t\"PIO_DIRECTION\": \"BIDIR\"\n\t\t}\n    },\n    \"pins\": {\n\t        \"si5324_clk_p\": {\n\t\t\t\"LOC\": \"AD8\",\n\t\t\t\"DIFF_TERM\": \"TRUE\",\n\t\t\t\"PIO_DIRECTION\": \"INPUT\"\n\t\t},\n\t        \"si5324_clk_n\": {\n\t\t\t\"LOC\": \"AD7\",\n\t\t\t\"DIFF_TERM\": \"TRUE\",\n\t\t\t\"PIO_DIRECTION\": \"INPUT\"\n\t\t},\n\t\t\"si5324_rst_n\": {\n\t\t\t\"LOC\": \"AT36\",\n\t\t\t\"IOSTANDARD\": \"LVCMOS18\",\n\t\t\t\"PIO_DIRECTION\": \"OUTPUT\"\n\t\t},\n\t        \"sgmii_clk_p\": {\n\t\t\t\"LOC\": \"AH8\",\n\t\t\t\"DIFF_TERM\": \"TRUE\",\n\t\t\t\"PIO_DIRECTION\": \"INPUT\"\n\t\t},\n\t        \"sgmii_clk_n\": {\n\t\t\t\"LOC\": \"AH7\",\n\t\t\t\"DIFF_TERM\": \"TRUE\",\n\t\t\t\"PIO_DIRECTION\": \"INPUT\"\n\t\t}\n\t}\n}\n\n\n"
  },
  {
    "path": "boardinfo/vc707g2.json",
    "content": "{\n    \"options\": {\n        \"bsvdefines\" : [\"XILINX=1\", \"Virtex7\", \"PCIE\", \"PCIE2\", \"PcieHostInterface\", \"PhysAddrWidth=40\", \"PcieLanes=8\",\n\t\t       \t\"CONNECTAL_BITS_DEPENDENCES=hw/mkTop.bit\", \"CONNECTAL_RUN_SCRIPT=$(CONNECTALDIR)/scripts/run.pcietest\"],\n        \"os\" : \"ubuntu\",\n        \"partname\" : \"xc7vx485tffg1761-2\",\n        \"need_pcie\" : \"x7_gen2x8\",\n        \"TOP\" : \"PcieTop\",\n        \"constraints\":     [\"constraints/xilinx/vc707g2.xdc\", \"constraints/xilinx/pcie-clocks.xdc\"],\n        \"implconstraints\": [\"constraints/xilinx/vc707g2.xdc\", \"constraints/xilinx/pcie-clocks.xdc\"],\n        \"runscript\" : \"run.pcietest\",\n        \"CONNECTALFLAGS\" : [\"--mainclockperiod=4\", \"--derivedclockperiod=4\", \"--pcieclockperiod=4\"],\n        \"rewireclockstring\" : \"\"\n    },\n    \"sfp1\" : {\n\t\t \"rxp\" : {\n\t\t\t     \"LOC\" : \"AL6\",\n\t\t\t     \"PIO_DIRECTION\" : \"INPUT\"\n\t\t },\n\t\t \"rxn\" : {\n\t\t\t     \"LOC\" : \"AL5\",\n\t\t\t     \"PIO_DIRECTION\" : \"INPUT\"\n\t\t },\n\t\t \"txp\" : {\n\t\t\t     \"LOC\" : \"AM4\",\n\t\t\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t\t },\n\t\t \"txn\" : {\n\t\t\t     \"LOC\" : \"AM3\",\n\t\t\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t\t }\n    },\n    \"fmc\": {\n    },\n    \"bpi_flash\": {\n\t\t \"data[0]\" : {\n\t\t\t     \"LOC\" : \"AM36\",\n\t\t\t     \"IOSTANDARD\" : \"LVCMOS18\",\n\t\t\t     \"PIO_DIRECTION\" : \"BIDIR\"\n\t\t },\n\t\t \"data[1]\" : {\n\t\t\t     \"LOC\" : \"AN36\",\n\t\t\t     \"IOSTANDARD\" : \"LVCMOS18\",\n\t\t\t     \"PIO_DIRECTION\" : \"BIDIR\"\n\t\t },\n\t\t \"data[2]\" : {\n\t\t\t     \"LOC\" : \"AJ36\",\n\t\t\t     \"IOSTANDARD\" : \"LVCMOS18\",\n\t\t\t     \"PIO_DIRECTION\" : \"BIDIR\"\n\t\t },\n\t\t \"data[3]\" : {\n\t\t\t     \"LOC\" : \"AJ37\",\n\t\t\t     \"IOSTANDARD\" : \"LVCMOS18\",\n\t\t\t     \"PIO_DIRECTION\" : \"BIDIR\"\n\t\t },\n\t\t \"data[4]\" : {\n\t\t\t     \"LOC\" : \"AK37\",\n\t\t\t     \"IOSTANDARD\" : \"LVCMOS18\",\n\t\t\t     \"PIO_DIRECTION\" : \"BIDIR\"\n\t\t },\n\t\t \"data[5]\" : {\n\t\t\t     \"LOC\" : \"AL37\",\n\t\t\t     \"IOSTANDARD\" : \"LVCMOS18\",\n\t\t\t     \"PIO_DIRECTION\" : \"BIDIR\"\n\t\t },\n\t\t \"data[6]\" : {\n\t\t\t     \"LOC\" : \"AN35\",\n\t\t\t     \"IOSTANDARD\" : \"LVCMOS18\",\n\t\t\t     \"PIO_DIRECTION\" : \"BIDIR\"\n\t\t },\n\t\t \"data[7]\" : {\n\t\t\t     \"LOC\" : \"AP35\",\n\t\t\t     \"IOSTANDARD\" : \"LVCMOS18\",\n\t\t\t     \"PIO_DIRECTION\" : \"BIDIR\"\n\t\t },\n\t\t \"data[8]\" : {\n\t\t\t     \"LOC\" : \"AM37\",\n\t\t\t     \"IOSTANDARD\" : \"LVCMOS18\",\n\t\t\t     \"PIO_DIRECTION\" : \"BIDIR\"\n\t\t },\n\t\t \"data[9]\" : {\n\t\t\t     \"LOC\" : \"AG33\",\n\t\t\t     \"IOSTANDARD\" : \"LVCMOS18\",\n\t\t\t     \"PIO_DIRECTION\" : \"BIDIR\"\n\t\t },\n\t\t \"data[10]\" : {\n\t\t\t     \"LOC\" : \"AH33\",\n\t\t\t     \"IOSTANDARD\" : \"LVCMOS18\",\n\t\t\t     \"PIO_DIRECTION\" : \"BIDIR\"\n\t\t },\n\t\t \"data[11]\" : {\n\t\t\t     \"LOC\" : \"AK35\",\n\t\t\t     \"IOSTANDARD\" : \"LVCMOS18\",\n\t\t\t     \"PIO_DIRECTION\" : \"BIDIR\"\n\t\t },\n\t\t \"data[12]\" : {\n\t\t\t     \"LOC\" : \"AL35\",\n\t\t\t     \"IOSTANDARD\" : \"LVCMOS18\",\n\t\t\t     \"PIO_DIRECTION\" : \"BIDIR\"\n\t\t },\n\t\t \"data[13]\" : {\n\t\t\t     \"LOC\" : \"AJ31\",\n\t\t\t     \"IOSTANDARD\" : \"LVCMOS18\",\n\t\t\t     \"PIO_DIRECTION\" : \"BIDIR\"\n\t\t },\n\t\t \"data[14]\" : {\n\t\t\t     \"LOC\" : \"AH34\",\n\t\t\t     \"IOSTANDARD\" : \"LVCMOS18\",\n\t\t\t     \"PIO_DIRECTION\" : \"BIDIR\"\n\t\t },\n\t\t \"data[15]\" : {\n\t\t\t     \"LOC\" : \"AJ35\",\n\t\t\t     \"IOSTANDARD\" : \"LVCMOS18\",\n\t\t\t     \"PIO_DIRECTION\" : \"BIDIR\"\n\t\t },\n\t\t \"addr[0]\" : {\n\t\t\t     \"LOC\" : \"AJ28\",\n\t\t\t     \"IOSTANDARD\" : \"LVCMOS18\",\n\t\t\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t\t },\n\t\t \"addr[1]\" : {\n\t\t\t     \"LOC\" : \"AH28\",\n\t\t\t     \"IOSTANDARD\" : \"LVCMOS18\",\n\t\t\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t\t },\n\t\t \"addr[2]\" : {\n\t\t\t     \"LOC\" : \"AG31\",\n\t\t\t     \"IOSTANDARD\" : \"LVCMOS18\",\n\t\t\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t\t },\n\t\t \"addr[3]\" : {\n\t\t\t     \"LOC\" : \"AF30\",\n\t\t\t     \"IOSTANDARD\" : \"LVCMOS18\",\n\t\t\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t\t },\n\t\t \"addr[4]\" : {\n\t\t\t     \"LOC\" : \"AK29\",\n\t\t\t     \"IOSTANDARD\" : \"LVCMOS18\",\n\t\t\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t\t },\n\t\t \"addr[5]\" : {\n\t\t\t     \"LOC\" : \"AK28\",\n\t\t\t     \"IOSTANDARD\" : \"LVCMOS18\",\n\t\t\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t\t },\n\t\t \"addr[6]\" : {\n\t\t\t     \"LOC\" : \"AG29\",\n\t\t\t     \"IOSTANDARD\" : \"LVCMOS18\",\n\t\t\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t\t },\n\t\t \"addr[7]\" : {\n\t\t\t     \"LOC\" : \"AK30\",\n\t\t\t     \"IOSTANDARD\" : \"LVCMOS18\",\n\t\t\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t\t },\n\t\t \"addr[8]\" : {\n\t\t\t     \"LOC\" : \"AJ30\",\n\t\t\t     \"IOSTANDARD\" : \"LVCMOS18\",\n\t\t\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t\t },\n\t\t \"addr[9]\" : {\n\t\t\t     \"LOC\" : \"AH30\",\n\t\t\t     \"IOSTANDARD\" : \"LVCMOS18\",\n\t\t\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t\t },\n\t\t \"addr[10]\" : {\n\t\t\t     \"LOC\" : \"AH29\",\n\t\t\t     \"IOSTANDARD\" : \"LVCMOS18\",\n\t\t\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t\t },\n\t\t \"addr[11]\" : {\n\t\t\t     \"LOC\" : \"AL30\",\n\t\t\t     \"IOSTANDARD\" : \"LVCMOS18\",\n\t\t\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t\t },\n\t\t \"addr[12]\" : {\n\t\t\t     \"LOC\" : \"AL29\",\n\t\t\t     \"IOSTANDARD\" : \"LVCMOS18\",\n\t\t\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t\t },\n\t\t \"addr[13]\" : {\n\t\t\t     \"LOC\" : \"AN33\",\n\t\t\t     \"IOSTANDARD\" : \"LVCMOS18\",\n\t\t\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t\t },\n\t\t \"addr[14]\" : {\n\t\t\t     \"LOC\" : \"AM33\",\n\t\t\t     \"IOSTANDARD\" : \"LVCMOS18\",\n\t\t\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t\t },\n\t\t \"addr[15]\" : {\n\t\t\t     \"LOC\" : \"AM32\",\n\t\t\t     \"IOSTANDARD\" : \"LVCMOS18\",\n\t\t\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t\t },\n\t\t \"addr[16]\" : {\n\t\t\t     \"LOC\" : \"AV41\",\n\t\t\t     \"IOSTANDARD\" : \"LVCMOS18\",\n\t\t\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t\t },\n\t\t \"addr[17]\" : {\n\t\t\t     \"LOC\" : \"AU41\",\n\t\t\t     \"IOSTANDARD\" : \"LVCMOS18\",\n\t\t\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t\t },\n\t\t \"addr[18]\" : {\n\t\t\t     \"LOC\" : \"BA42\",\n\t\t\t     \"IOSTANDARD\" : \"LVCMOS18\",\n\t\t\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t\t },\n\t\t \"addr[19]\" : {\n\t\t\t     \"LOC\" : \"AU42\",\n\t\t\t     \"IOSTANDARD\" : \"LVCMOS18\",\n\t\t\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t\t },\n\t\t \"addr[20]\" : {\n\t\t\t     \"LOC\" : \"AT41\",\n\t\t\t     \"IOSTANDARD\" : \"LVCMOS18\",\n\t\t\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t\t },\n\t\t \"addr[21]\" : {\n\t\t\t     \"LOC\" : \"BA40\",\n\t\t\t     \"IOSTANDARD\" : \"LVCMOS18\",\n\t\t\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t\t },\n\t\t \"addr[22]\" : {\n\t\t\t     \"LOC\" : \"BA39\",\n\t\t\t     \"IOSTANDARD\" : \"LVCMOS18\",\n\t\t\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t\t },\n\t\t \"addr[23]\" : {\n\t\t\t     \"LOC\" : \"BB39\",\n\t\t\t     \"IOSTANDARD\" : \"LVCMOS18\",\n\t\t\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t\t },\n\t\t \"addr[24]\" : {\n\t\t\t     \"LOC\" : \"AW42\",\n\t\t\t     \"IOSTANDARD\" : \"LVCMOS18\",\n\t\t\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t\t },\n\t\t \"addr[25]\" : {\n\t\t\t     \"LOC\" : \"AW41\",\n\t\t\t     \"IOSTANDARD\" : \"LVCMOS18\",\n\t\t\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t\t },\n\t\t \"wait_in_b\" : {\n\t\t\t     \"LOC\" : \"AM34\",\n\t\t\t     \"IOSTANDARD\" : \"LVCMOS18\",\n\t\t\t     \"PIO_DIRECTION\" : \"INPUT\",\n\t\t\t     \"PULLUP\" : \"TRUE\"\n\t\t },\n\t\t \"rst\" : {\n\t\t\t     \"LOC\" : \"_not_usable\",\n\t\t\t     \"IOSTANDARD\" : \"LVCMOS18\",\n\t\t\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t\t },\n\t\t \"oe_b\" : {\n\t\t\t     \"LOC\" : \"BA41\",\n\t\t\t     \"IOSTANDARD\" : \"LVCMOS18\",\n\t\t\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t\t },\n\t\t \"ce_b\" : {\n\t\t\t     \"LOC\" : \"AL36\",\n\t\t\t     \"IOSTANDARD\" : \"LVCMOS18\",\n\t\t\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t\t },\n\t\t \"we_b\" : {\n\t\t\t     \"LOC\" : \"BB41\",\n\t\t\t     \"IOSTANDARD\" : \"LVCMOS18\",\n\t\t\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t\t },\n\t\t \"adv_b\" : {\n\t\t\t     \"LOC\" : \"AY37\",\n\t\t\t     \"IOSTANDARD\" : \"LVCMOS18\",\n\t\t\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t\t }\n    },\t\n    \"uart\": {\n\t\t\"d_in\": {\n\t\t\t\"LOC\": \"AU33\",\n\t\t\t\"IOSTANDARD\": \"LVCMOS18\",\n\t\t\t\"PIO_DIRECTION\": \"INPUT\"\n\t\t},\n\t\t\"d_out\": {\n\t\t\t\"LOC\": \"AU36\",\n\t\t\t\"IOSTANDARD\": \"LVCMOS18\",\n\t\t\t\"PIO_DIRECTION\": \"OUTPUT\"\n\t\t},\n\t\t\"rts\": {\n\t\t\t\"LOC\": \"AR34\",\n\t\t\t\"IOSTANDARD\": \"LVCMOS18\",\n\t\t\t\"PIO_DIRECTION\": \"INPUT\"\n\t\t},\n\t\t\"cts\": {\n\t\t\t\"LOC\": \"AT32\",\n\t\t\t\"IOSTANDARD\": \"LVCMOS18\",\n\t\t\t\"PIO_DIRECTION\": \"OUTPUT\"\n\t\t}\n    },\n    \"sdio\": {\n        \"dat0\": {\n            \"PACKAGE_PIN\": \"AR30\",\n            \"IOSTANDARD\": \"LVCMOS18\",\n            \"PIO_DIRECTION\": \"BIDIR\"\n        },\n        \"dat1\": {\n            \"PACKAGE_PIN\": \"AU31\",\n            \"IOSTANDARD\": \"LVCMOS18\",\n            \"PIO_DIRECTION\": \"BIDIR\"\n        },\n        \"dat2\": {\n            \"PACKAGE_PIN\": \"AV31\",\n            \"IOSTANDARD\": \"LVCMOS18\",\n            \"PIO_DIRECTION\": \"BIDIR\"\n        },\n        \"cd_dat3\": {\n            \"PACKAGE_PIN\": \"AT30\",\n            \"IOSTANDARD\": \"LVCMOS18\",\n            \"PIO_DIRECTION\": \"BIDIR\"\n        },\n        \"clk\": {\n            \"PACKAGE_PIN\": \"AN30\",\n            \"IOSTANDARD\": \"LVCMOS18\",\n            \"PIO_DIRECTION\": \"OUTPUT\"\n        },\n        \"cmd\": {\n            \"PACKAGE_PIN\": \"AP30\",\n            \"IOSTANDARD\": \"LVCMOS18\",\n            \"PIO_DIRECTION\": \"BIDIR\"\n        },\n        \"sddet\": {\n            \"PACKAGE_PIN\": \"AP32\",\n            \"IOSTANDARD\": \"LVCMOS18\",\n            \"PIO_DIRECTION\": \"INPUT\"\n        },\n        \"sdwp\": {\n            \"PACKAGE_PIN\": \"AR32\",\n            \"IOSTANDARD\": \"LVCMOS18\",\n            \"PIO_DIRECTION\": \"INPUT\"\n        }\n    },\n    \"iic_main\": {\n\t\t\"sda\": {\n\t\t\t\"LOC\": \"AU32\",\n\t\t\t\"IOSTANDARD\": \"LVCMOS18\",\n\t\t\t\"PIO_DIRECTION\": \"BIDIR\"\n\t\t},\n\t\t\"scl\": {\n\t\t\t\"LOC\": \"AT35\",\n\t\t\t\"IOSTANDARD\": \"LVCMOS18\",\n\t\t\t\"PIO_DIRECTION\": \"BIDIR\"\n\t\t}\n    },\n    \"pins\": {\n\t        \"si5324_clk_p\": {\n\t\t\t\"LOC\": \"AD8\",\n\t\t\t\"DIFF_TERM\": \"TRUE\",\n\t\t\t\"PIO_DIRECTION\": \"INPUT\"\n\t\t},\n\t        \"si5324_clk_n\": {\n\t\t\t\"LOC\": \"AD7\",\n\t\t\t\"DIFF_TERM\": \"TRUE\",\n\t\t\t\"PIO_DIRECTION\": \"INPUT\"\n\t\t},\n\t\t\"si5324_rst_n\": {\n\t\t\t\"LOC\": \"AT36\",\n\t\t\t\"IOSTANDARD\": \"LVCMOS18\",\n\t\t\t\"PIO_DIRECTION\": \"OUTPUT\"\n\t\t},\n\t        \"sgmii_clk_p\": {\n\t\t\t\"LOC\": \"AH8\",\n\t\t\t\"DIFF_TERM\": \"TRUE\",\n\t\t\t\"PIO_DIRECTION\": \"INPUT\"\n\t\t},\n\t        \"sgmii_clk_n\": {\n\t\t\t\"LOC\": \"AH7\",\n\t\t\t\"DIFF_TERM\": \"TRUE\",\n\t\t\t\"PIO_DIRECTION\": \"INPUT\"\n\t\t}\n\t}\n}\n\n\n"
  },
  {
    "path": "boardinfo/vc709.json",
    "content": "{\n    \"options\": {\n        \"bsvdefines\" : [\"XILINX=1\", \"Virtex7\", \"PCIE\", \"PCIE3\", \"PcieHostInterface\", \"PhysAddrWidth=40\", \"NUMBER_OF_LEDS=8\", \"PcieLanes=8\",\n\t\t       \t\"CONNECTAL_BITS_DEPENDENCES=hw/mkTop.bit\", \"CONNECTAL_RUN_SCRIPT=$(CONNECTALDIR)/scripts/run.pcietest\"],\n        \"os\" : \"ubuntu\",\n        \"partname\" : \"xc7vx690tffg1761-2\",\n        \"need_pcie\" : \"x7_gen3x8\",\n        \"TOP\" : \"PcieTop\",\n        \"constraints\": [],\n        \"implconstraints\": [\"constraints/xilinx/vc709.xdc\", \"constraints/xilinx/pcie-clocks.xdc\"],\n        \"runscript\" : \"run.pcietest\",\n        \"CONNECTALFLAGS\" : [\"--mainclockperiod=4\", \"--derivedclockperiod=4\", \"--pcieclockperiod=4\"],\n        \"rewireclockstring\" : \"\"\n    },\n    \"leds\" : {\n\t\t\"L0\" : {\n\t\t \"LOC\" : \"AM39\",\n\t\t \"IOSTANDARD\" : \"LVCMOS15\",\n\t\t \"PIO_DIRECTION\" : \"OUTPUT\"\n\t\t },\n\t\t\"L1\" : {\n\t\t \"LOC\" : \"AN39\",\n\t\t \"IOSTANDARD\" : \"LVCMOS15\",\n\t\t \"PIO_DIRECTION\" : \"OUTPUT\"\n\t\t },\n\t\t\"L2\" : {\n\t\t \"LOC\" : \"AR37\",\n\t\t \"IOSTANDARD\" : \"LVCMOS15\",\n\t\t \"PIO_DIRECTION\" : \"OUTPUT\"\n\t\t },\n\t\t\"L3\" : {\n\t\t \"LOC\" : \"AT37\",\n\t\t \"IOSTANDARD\" : \"LVCMOS15\",\n\t\t \"PIO_DIRECTION\" : \"OUTPUT\"\n\t\t },\n\t\t\"L4\" : {\n\t\t \"LOC\" : \"AR35\",\n\t\t \"IOSTANDARD\" : \"LVCMOS15\",\n\t\t \"PIO_DIRECTION\" : \"OUTPUT\"\n\t\t },\n\t\t\"L5\" : {\n\t\t \"LOC\" : \"AP41\",\n\t\t \"IOSTANDARD\" : \"LVCMOS15\",\n\t\t \"PIO_DIRECTION\" : \"OUTPUT\"\n\t\t },\n\t\t\"L6\" : {\n\t\t \"LOC\" : \"AP42\",\n\t\t \"IOSTANDARD\" : \"LVCMOS15\",\n\t\t \"PIO_DIRECTION\" : \"OUTPUT\"\n\t\t },\n\t\t\"L7\" : {\n\t\t \"LOC\" : \"AU39\",\n\t\t \"IOSTANDARD\" : \"LVCMOS15\",\n\t\t \"PIO_DIRECTION\" : \"OUTPUT\"\n\t\t }\n\t},\n    \"sfp1\": {\n\t\t \"rxp\" : {\n\t\t\t     \"LOC\" : \"AN6\",\n\t\t\t     \"PIO_DIRECTION\" : \"INPUT\"\n\t\t },\n\t\t \"rxn\" : {\n\t\t\t     \"LOC\" : \"AN5\",\n\t\t\t     \"PIO_DIRECTION\" : \"INPUT\"\n\t\t },\n\t\t \"txp\" : {\n\t\t\t     \"LOC\" : \"AP4\",\n\t\t\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t\t },\n\t\t \"txn\" : {\n\t\t\t     \"LOC\" : \"AP3\",\n\t\t\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t\t }\n    },\n    \"sfp2\": {\n\t\t \"rxp\" : {\n\t\t\t     \"LOC\" : \"AM8\",\n\t\t\t     \"PIO_DIRECTION\" : \"INPUT\"\n\t\t },\n\t\t \"rxn\" : {\n\t\t\t     \"LOC\" : \"AM7\",\n\t\t\t     \"PIO_DIRECTION\" : \"INPUT\"\n\t\t },\n\t\t \"txp\" : {\n\t\t\t     \"LOC\" : \"AN2\",\n\t\t\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t\t },\n\t\t \"txn\" : {\n\t\t\t     \"LOC\" : \"AN1\",\n\t\t\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t\t }\n    },\n    \"sfp3\": {\n\t\t \"rxp\" : {\n\t\t\t     \"LOC\" : \"AL6\",\n\t\t\t     \"PIO_DIRECTION\" : \"INPUT\"\n\t\t },\n\t\t \"rxn\" : {\n\t\t\t     \"LOC\" : \"AL5\",\n\t\t\t     \"PIO_DIRECTION\" : \"INPUT\"\n\t\t },\n\t\t \"txp\" : {\n\t\t\t     \"LOC\" : \"AM4\",\n\t\t\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t\t },\n\t\t \"txn\" : {\n\t\t\t     \"LOC\" : \"AM3\",\n\t\t\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t\t }\n    },\n    \"sfp4\": {\n\t\t \"rxp\" : {\n\t\t\t     \"LOC\" : \"AJ6\",\n\t\t\t     \"PIO_DIRECTION\" : \"INPUT\"\n\t\t },\n\t\t \"rxn\" : {\n\t\t\t     \"LOC\" : \"AJ5\",\n\t\t\t     \"PIO_DIRECTION\" : \"INPUT\"\n\t\t },\n\t\t \"txp\" : {\n\t\t\t     \"LOC\" : \"AL2\",\n\t\t\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t\t },\n\t\t \"txn\" : {\n\t\t\t     \"LOC\" : \"AL1\",\n\t\t\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t\t }\n    },\n    \"bpi_flash\": {\n\t\t \"data[0]\" : {\n\t\t\t     \"LOC\" : \"AM36\",\n\t\t\t     \"IOSTANDARD\" : \"LVCMOS18\",\n\t\t\t     \"PIO_DIRECTION\" : \"BIDIR\"\n\t\t },\n\t\t \"data[1]\" : {\n\t\t\t     \"LOC\" : \"AN36\",\n\t\t\t     \"IOSTANDARD\" : \"LVCMOS18\",\n\t\t\t     \"PIO_DIRECTION\" : \"BIDIR\"\n\t\t },\n\t\t \"data[2]\" : {\n\t\t\t     \"LOC\" : \"AJ36\",\n\t\t\t     \"IOSTANDARD\" : \"LVCMOS18\",\n\t\t\t     \"PIO_DIRECTION\" : \"BIDIR\"\n\t\t },\n\t\t \"data[3]\" : {\n\t\t\t     \"LOC\" : \"AJ37\",\n\t\t\t     \"IOSTANDARD\" : \"LVCMOS18\",\n\t\t\t     \"PIO_DIRECTION\" : \"BIDIR\"\n\t\t },\n\t\t \"data[4]\" : {\n\t\t\t     \"LOC\" : \"AK37\",\n\t\t\t     \"IOSTANDARD\" : \"LVCMOS18\",\n\t\t\t     \"PIO_DIRECTION\" : \"BIDIR\"\n\t\t },\n\t\t \"data[5]\" : {\n\t\t\t     \"LOC\" : \"AL37\",\n\t\t\t     \"IOSTANDARD\" : \"LVCMOS18\",\n\t\t\t     \"PIO_DIRECTION\" : \"BIDIR\"\n\t\t },\n\t\t \"data[6]\" : {\n\t\t\t     \"LOC\" : \"AN35\",\n\t\t\t     \"IOSTANDARD\" : \"LVCMOS18\",\n\t\t\t     \"PIO_DIRECTION\" : \"BIDIR\"\n\t\t },\n\t\t \"data[7]\" : {\n\t\t\t     \"LOC\" : \"AP35\",\n\t\t\t     \"IOSTANDARD\" : \"LVCMOS18\",\n\t\t\t     \"PIO_DIRECTION\" : \"BIDIR\"\n\t\t },\n\t\t \"data[8]\" : {\n\t\t\t     \"LOC\" : \"AM37\",\n\t\t\t     \"IOSTANDARD\" : \"LVCMOS18\",\n\t\t\t     \"PIO_DIRECTION\" : \"BIDIR\"\n\t\t },\n\t\t \"data[9]\" : {\n\t\t\t     \"LOC\" : \"AG33\",\n\t\t\t     \"IOSTANDARD\" : \"LVCMOS18\",\n\t\t\t     \"PIO_DIRECTION\" : \"BIDIR\"\n\t\t },\n\t\t \"data[10]\" : {\n\t\t\t     \"LOC\" : \"AH33\",\n\t\t\t     \"IOSTANDARD\" : \"LVCMOS18\",\n\t\t\t     \"PIO_DIRECTION\" : \"BIDIR\"\n\t\t },\n\t\t \"data[11]\" : {\n\t\t\t     \"LOC\" : \"AK35\",\n\t\t\t     \"IOSTANDARD\" : \"LVCMOS18\",\n\t\t\t     \"PIO_DIRECTION\" : \"BIDIR\"\n\t\t },\n\t\t \"data[12]\" : {\n\t\t\t     \"LOC\" : \"AL35\",\n\t\t\t     \"IOSTANDARD\" : \"LVCMOS18\",\n\t\t\t     \"PIO_DIRECTION\" : \"BIDIR\"\n\t\t },\n\t\t \"data[13]\" : {\n\t\t\t     \"LOC\" : \"AJ31\",\n\t\t\t     \"IOSTANDARD\" : \"LVCMOS18\",\n\t\t\t     \"PIO_DIRECTION\" : \"BIDIR\"\n\t\t },\n\t\t \"data[14]\" : {\n\t\t\t     \"LOC\" : \"AH34\",\n\t\t\t     \"IOSTANDARD\" : \"LVCMOS18\",\n\t\t\t     \"PIO_DIRECTION\" : \"BIDIR\"\n\t\t },\n\t\t \"data[15]\" : {\n\t\t\t     \"LOC\" : \"AJ35\",\n\t\t\t     \"IOSTANDARD\" : \"LVCMOS18\",\n\t\t\t     \"PIO_DIRECTION\" : \"BIDIR\"\n\t\t },\n\t\t \"addr[0]\" : {\n\t\t\t     \"LOC\" : \"AJ28\",\n\t\t\t     \"IOSTANDARD\" : \"LVCMOS18\",\n\t\t\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t\t },\n\t\t \"addr[1]\" : {\n\t\t\t     \"LOC\" : \"AH28\",\n\t\t\t     \"IOSTANDARD\" : \"LVCMOS18\",\n\t\t\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t\t },\n\t\t \"addr[2]\" : {\n\t\t\t     \"LOC\" : \"AG31\",\n\t\t\t     \"IOSTANDARD\" : \"LVCMOS18\",\n\t\t\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t\t },\n\t\t \"addr[3]\" : {\n\t\t\t     \"LOC\" : \"AF30\",\n\t\t\t     \"IOSTANDARD\" : \"LVCMOS18\",\n\t\t\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t\t },\n\t\t \"addr[4]\" : {\n\t\t\t     \"LOC\" : \"AK29\",\n\t\t\t     \"IOSTANDARD\" : \"LVCMOS18\",\n\t\t\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t\t },\n\t\t \"addr[5]\" : {\n\t\t\t     \"LOC\" : \"AK28\",\n\t\t\t     \"IOSTANDARD\" : \"LVCMOS18\",\n\t\t\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t\t },\n\t\t \"addr[6]\" : {\n\t\t\t     \"LOC\" : \"AG29\",\n\t\t\t     \"IOSTANDARD\" : \"LVCMOS18\",\n\t\t\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t\t },\n\t\t \"addr[7]\" : {\n\t\t\t     \"LOC\" : \"AK30\",\n\t\t\t     \"IOSTANDARD\" : \"LVCMOS18\",\n\t\t\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t\t },\n\t\t \"addr[8]\" : {\n\t\t\t     \"LOC\" : \"AJ30\",\n\t\t\t     \"IOSTANDARD\" : \"LVCMOS18\",\n\t\t\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t\t },\n\t\t \"addr[9]\" : {\n\t\t\t     \"LOC\" : \"AH30\",\n\t\t\t     \"IOSTANDARD\" : \"LVCMOS18\",\n\t\t\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t\t },\n\t\t \"addr[10]\" : {\n\t\t\t     \"LOC\" : \"AH29\",\n\t\t\t     \"IOSTANDARD\" : \"LVCMOS18\",\n\t\t\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t\t },\n\t\t \"addr[11]\" : {\n\t\t\t     \"LOC\" : \"AL30\",\n\t\t\t     \"IOSTANDARD\" : \"LVCMOS18\",\n\t\t\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t\t },\n\t\t \"addr[12]\" : {\n\t\t\t     \"LOC\" : \"AL29\",\n\t\t\t     \"IOSTANDARD\" : \"LVCMOS18\",\n\t\t\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t\t },\n\t\t \"addr[13]\" : {\n\t\t\t     \"LOC\" : \"AN33\",\n\t\t\t     \"IOSTANDARD\" : \"LVCMOS18\",\n\t\t\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t\t },\n\t\t \"addr[14]\" : {\n\t\t\t     \"LOC\" : \"AM33\",\n\t\t\t     \"IOSTANDARD\" : \"LVCMOS18\",\n\t\t\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t\t },\n\t\t \"addr[15]\" : {\n\t\t\t     \"LOC\" : \"AM32\",\n\t\t\t     \"IOSTANDARD\" : \"LVCMOS18\",\n\t\t\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t\t },\n\t\t \"addr[16]\" : {\n\t\t\t     \"LOC\" : \"AV41\",\n\t\t\t     \"IOSTANDARD\" : \"LVCMOS18\",\n\t\t\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t\t },\n\t\t \"addr[17]\" : {\n\t\t\t     \"LOC\" : \"AU41\",\n\t\t\t     \"IOSTANDARD\" : \"LVCMOS18\",\n\t\t\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t\t },\n\t\t \"addr[18]\" : {\n\t\t\t     \"LOC\" : \"BA42\",\n\t\t\t     \"IOSTANDARD\" : \"LVCMOS18\",\n\t\t\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t\t },\n\t\t \"addr[19]\" : {\n\t\t\t     \"LOC\" : \"AU42\",\n\t\t\t     \"IOSTANDARD\" : \"LVCMOS18\",\n\t\t\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t\t },\n\t\t \"addr[20]\" : {\n\t\t\t     \"LOC\" : \"AT41\",\n\t\t\t     \"IOSTANDARD\" : \"LVCMOS18\",\n\t\t\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t\t },\n\t\t \"addr[21]\" : {\n\t\t\t     \"LOC\" : \"BA40\",\n\t\t\t     \"IOSTANDARD\" : \"LVCMOS18\",\n\t\t\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t\t },\n\t\t \"addr[22]\" : {\n\t\t\t     \"LOC\" : \"BA39\",\n\t\t\t     \"IOSTANDARD\" : \"LVCMOS18\",\n\t\t\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t\t },\n\t\t \"addr[23]\" : {\n\t\t\t     \"LOC\" : \"BB39\",\n\t\t\t     \"IOSTANDARD\" : \"LVCMOS18\",\n\t\t\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t\t },\n\t\t \"addr[24]\" : {\n\t\t\t     \"LOC\" : \"AW42\",\n\t\t\t     \"IOSTANDARD\" : \"LVCMOS18\",\n\t\t\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t\t },\n\t\t \"addr[25]\" : {\n\t\t\t     \"LOC\" : \"AW41\",\n\t\t\t     \"IOSTANDARD\" : \"LVCMOS18\",\n\t\t\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t\t },\n\t\t \"wait_in_b\" : {\n\t\t\t     \"LOC\" : \"AM34\",\n\t\t\t     \"IOSTANDARD\" : \"LVCMOS18\",\n\t\t\t     \"PIO_DIRECTION\" : \"INPUT\",\n\t\t\t     \"PULLUP\" : \"TRUE\"\n\t\t },\n\t\t \"rst\" : {\n\t\t\t     \"LOC\" : \"AG11_not_usable\",\n\t\t\t     \"IOSTANDARD\" : \"LVCMOS18\",\n\t\t\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t\t },\n\t\t \"oe_b\" : {\n\t\t\t     \"LOC\" : \"BA41\",\n\t\t\t     \"IOSTANDARD\" : \"LVCMOS18\",\n\t\t\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t\t },\n\t\t \"ce_b\" : {\n\t\t\t     \"LOC\" : \"AL36\",\n\t\t\t     \"IOSTANDARD\" : \"LVCMOS18\",\n\t\t\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t\t },\n\t\t \"we_b\" : {\n\t\t\t     \"LOC\" : \"BB41\",\n\t\t\t     \"IOSTANDARD\" : \"LVCMOS18\",\n\t\t\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t\t },\n\t\t \"adv_b\" : {\n\t\t\t     \"LOC\" : \"AY37\",\n\t\t\t     \"IOSTANDARD\" : \"LVCMOS18\",\n\t\t\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t\t }\n    },\t\n    \"uart\": {\n\t\t\"d_in\": {\n\t\t\t\"LOC\": \"AU33\",\n\t\t\t\"IOSTANDARD\": \"LVCMOS18\",\n\t\t\t\"PIO_DIRECTION\": \"INPUT\"\n\t\t},\n\t\t\"d_out\": {\n\t\t\t\"LOC\": \"AU36\",\n\t\t\t\"IOSTANDARD\": \"LVCMOS18\",\n\t\t\t\"PIO_DIRECTION\": \"OUTPUT\"\n\t\t},\n\t\t\"rts\": {\n\t\t\t\"LOC\": \"AR34\",\n\t\t\t\"IOSTANDARD\": \"LVCMOS18\",\n\t\t\t\"PIO_DIRECTION\": \"INPUT\"\n\t\t},\n\t\t\"cts\": {\n\t\t\t\"LOC\": \"AT32\",\n\t\t\t\"IOSTANDARD\": \"LVCMOS18\",\n\t\t\t\"PIO_DIRECTION\": \"OUTPUT\"\n\t\t}\n    },\n    \"iic_main\": {\n\t\t\"sda\": {\n\t\t\t\"LOC\": \"AU32\",\n\t\t\t\"IOSTANDARD\": \"LVCMOS18\",\n\t\t\t\"PIO_DIRECTION\": \"BIDIR\"\n\t\t},\n\t\t\"scl\": {\n\t\t\t\"LOC\": \"AT35\",\n\t\t\t\"IOSTANDARD\": \"LVCMOS18\",\n\t\t\t\"PIO_DIRECTION\": \"BIDIR\"\n\t\t}\n    },\n    \"pins\": {\n\t\t\"userClk_p\": {\n\t\t\t\"LOC\": \"bogus\",\n\t\t\t\"IOSTANDARD\": \"LVDS_25\",\n\t\t\t\"DIFF_TERM\": \"TRUE\",\n\t\t\t\"PIO_DIRECTION\": \"INPUT\"\n\t\t},\n\t\t\"userClk_n\": {\n\t\t\t\"LOC\": \"bogus\",\n\t\t\t\"IOSTANDARD\": \"LVDS_25\",\n\t\t\t\"DIFF_TERM\": \"TRUE\",\n\t\t\t\"PIO_DIRECTION\": \"INPUT\"\n\t\t},\n\t\t\"smaUserClk_p\": {\n\t\t\t\"LOC\": \"bogus\",\n\t\t\t\"IOSTANDARD\": \"LVDS_25\",\n\t\t\t\"DIFF_TERM\": \"TRUE\",\n\t\t\t\"PIO_DIRECTION\": \"OUTPUT\"\n\t\t},\n\t\t\"smaUserClk_n\": {\n\t\t\t\"LOC\": \"bogus\",\n\t\t\t\"IOSTANDARD\": \"LVDS_25\",\n\t\t\t\"DIFF_TERM\": \"TRUE\",\n\t\t\t\"PIO_DIRECTION\": \"OUTPUT\"\n\t\t},\n\t        \"sys_clk_p\": {\n\t\t\t\"LOC\": \"H19\",\n\t\t\t\"IOSTANDARD\": \"LVDS_25\",\n\t\t\t\"DIFF_TERM\": \"TRUE\",\n\t\t\t\"PIO_DIRECTION\": \"INPUT\"\n\t\t},\n\t        \"sys_clk_n\": {\n\t\t\t\"LOC\": \"G18\",\n\t\t\t\"IOSTANDARD\": \"LVDS_25\",\n\t\t\t\"DIFF_TERM\": \"TRUE\",\n\t\t\t\"PIO_DIRECTION\": \"INPUT\"\n\t\t},\n\t        \"si5324_clk_p\": {\n\t\t\t\"LOC\": \"AH8\",\n\t\t\t\"DIFF_TERM\": \"TRUE\",\n\t\t\t\"PIO_DIRECTION\": \"INPUT\"\n\t\t},\n\t        \"si5324_clk_n\": {\n\t\t\t\"LOC\": \"AH7\",\n\t\t\t\"DIFF_TERM\": \"TRUE\",\n\t\t\t\"PIO_DIRECTION\": \"INPUT\"\n\t\t},\n\t\t\"mgtRefClk_p\": {\n\t\t\t\"LOC\": \"bogus\",\n\t\t\t\"IOSTANDARD\": \"LVDS_25\",\n\t\t\t\"DIFF_TERM\": \"TRUE\",\n\t\t\t\"PIO_DIRECTION\": \"INPUT\"\n\t\t},\n\t\t\"mgtRefClk_n\": {\n\t\t\t\"LOC\": \"bogus\",\n\t\t\t\"IOSTANDARD\": \"LVDS_25\",\n\t\t\t\"DIFF_TERM\": \"TRUE\",\n\t\t\t\"PIO_DIRECTION\": \"INPUT\"\n\t\t},\n\t\t\"mgtRx_p\": {\n\t\t\t\"LOC\": \"bogus\",\n\t\t\t\"DIFF_TERM\": \"TRUE\",\n\t\t\t\"PIO_DIRECTION\": \"INPUT\"\n\t\t},\n\t\t\"mgtRx_n\": {\n\t\t\t\"LOC\": \"bogus\",\n\t\t\t\"DIFF_TERM\": \"TRUE\",\n\t\t\t\"PIO_DIRECTION\": \"INPUT\"\n\t\t},\n\t\t\"mgtTx_p\": {\n\t\t\t\"LOC\": \"bogus\",\n\t\t\t\"DIFF_TERM\": \"TRUE\",\n\t\t\t\"PIO_DIRECTION\": \"OUTPUT\"\n\t\t},\n\t\t\"mgtTx_n\": {\n\t\t\t\"LOC\": \"bogus\",\n\t\t\t\"DIFF_TERM\": \"TRUE\",\n\t\t\t\"PIO_DIRECTION\": \"OUTPUT\"\n\t\t},\n\t\t\"si5324_rst_n\": {\n\t\t\t\"LOC\": \"AT36\",\n\t\t\t\"IOSTANDARD\": \"LVCMOS18\",\n\t\t\t\"PIO_DIRECTION\": \"OUTPUT\"\n\t\t}\n    }\n}\n\n\n"
  },
  {
    "path": "boardinfo/vcs.json",
    "content": "{\n    \"options\": {\n        \"os\" : \"ubuntu\",\n        \"partname\" : \"xc7z020clg484-1\",\n        \"TOP\" : \"XsimTop\",\n\t\"bsvdefines\": [\"CnocTop\", \"XsimHostInterface\", \"PhysAddrWidth=40\", \"SIMULATION\", \"SVDPI\",\n\t\t       \t\"CONNECTAL_BITS_DEPENDENCES=vcssim\"],\n        \"CONNECTALFLAGS\" : [\"--mainclockperiod=20\", \"--derivedclockperiod=10\"],\n        \"need_pcie\" : \"unused\"\n    }\n}\n\n\n"
  },
  {
    "path": "boardinfo/vcu108.json",
    "content": "{\n    \"options\": {\n        \"bsvdefines\" : [\"XILINX=1\", \"VirtexUltrascale\", \"XilinxUltrascale\", \"PCIE\", \"PCIE3\", \"PcieHostInterface\", \"PhysAddrWidth=40\", \"NUMBER_OF_LEDS=2\", \"PcieLanes=8\",\n\t\t       \t\"CONNECTAL_BITS_DEPENDENCES=hw/mkTop.bit\", \"CONNECTAL_RUN_SCRIPT=$(CONNECTALDIR)/scripts/run.pcietest\"],\n        \"os\" : \"ubuntu\",\n        \"partname\" : \"xcvu095-ffva2104-2-e\",\n        \"need_pcie\" : \"xu_gen3x8\",\n        \"TOP\" : \"PcieTop\",\n        \"constraints\": [\"constraints/xilinx/vcu108.xdc\"],\n        \"implconstraints\": [\"constraints/xilinx/vcu108.xdc\", \"constraints/xilinx/pcie-clocks.xdc\"],\n        \"runscript\" : \"run.pcietest\",\n        \"CONNECTALFLAGS\" : [\"--mainclockperiod=4\", \"--derivedclockperiod=4\", \"--pcieclockperiod=4\"],\n        \"rewireclockstring\" : \"\"\n    },\n    \"BTN\": {\n        \"BTN[0]\": {\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"BTN[1]\": {\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"TBD\"\n        }\n    },\n    \"CLK\": {\n        \"FPGA_SYSCLK_N\": {\n            \"PIO_DIRECTION\": \"INPUT\",\n            \"IOSTANDARD\": \"LVDS\",\n\t\t\t\"DIFF_TERM\": \"TRUE\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"FPGA_SYSCLK_P\": {\n            \"PIO_DIRECTION\": \"INPUT\",\n            \"IOSTANDARD\": \"LVDS\",\n\t\t\t\"DIFF_TERM\": \"TRUE\",\n            \"PACKAGE_PIN\": \"TBD\"\n        }\n    },\n    \"CPLD\": {\n        \"CPLD_IMGSEL[0]\": {\n            \"IOSTANDARD\": \"LVCMOS18\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"CPLD_IMGSEL[1]\": {\n            \"IOSTANDARD\": \"LVCMOS18\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"CPLD_IMGSEL[2]\": {\n            \"IOSTANDARD\": \"LVCMOS18\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"CPLD_RECONFIG\": {\n            \"IOSTANDARD\": \"LVCMOS18\",\n            \"PACKAGE_PIN\": \"TBD\"\n        }\n    },\n    \"DDR\": {\n        \"DDR3_SYSCLK_N\": {\n            \"IOSTANDARD\": \"LVDS\",\n\t\t\t\"DIFF_TERM\": \"TRUE\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"DDR3_SYSCLK_P\": {\n            \"IOSTANDARD\": \"LVDS\",\n\t\t\t\"DIFF_TERM\": \"TRUE\",\n            \"PACKAGE_PIN\": \"TBD\"\n        }\n    },\n    \"FMC\": {\n\t\"FMC_GBTCLK_P[00]\": {\n\t    \"DIFF_TERM\": \"TRUE\",\n            \"PACKAGE_PIN\": \"TBD\"\n\t},\n\t\"FMC_GBTCLK_N[00]\": {\n\t    \"DIFF_TERM\": \"TRUE\",\n            \"PACKAGE_PIN\": \"TBD\"\n\t},\n        \"FMC_CLK0_M2C_N\": {\n            \"IOSTANDARD\": \"LVDS\",\n\t    \"DIFF_TERM\": \"TRUE\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"FMC_CLK0_M2C_P\": {\n            \"IOSTANDARD\": \"LVDS\",\n\t\t\t\"DIFF_TERM\": \"TRUE\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"FMC_CLK1_M2C_N\": {\n            \"IOSTANDARD\": \"LVDS\",\n\t\t\t\"DIFF_TERM\": \"TRUE\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"FMC_CLK1_M2C_P\": {\n            \"IOSTANDARD\": \"LVDS\",\n\t\t\t\"DIFF_TERM\": \"TRUE\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"FMC_LA_N[00]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"FMC_LA_N[01]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"FMC_LA_N[02]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"FMC_LA_N[03]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"FMC_LA_N[04]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"FMC_LA_N[05]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"FMC_LA_N[06]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"FMC_LA_N[07]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"FMC_LA_N[08]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"FMC_LA_N[09]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"FMC_LA_N[10]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"FMC_LA_N[11]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"FMC_LA_N[12]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"FMC_LA_N[13]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"FMC_LA_N[14]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"FMC_LA_N[15]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"FMC_LA_N[16]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"FMC_LA_N[17]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"FMC_LA_N[18]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"FMC_LA_N[19]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"FMC_LA_N[20]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"FMC_LA_N[21]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"FMC_LA_N[22]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"FMC_LA_N[23]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"FMC_LA_N[24]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"FMC_LA_N[25]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"FMC_LA_N[26]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"FMC_LA_N[27]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"FMC_LA_N[28]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"FMC_LA_N[29]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"FMC_LA_N[30]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"FMC_LA_N[31]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"FMC_LA_N[32]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"FMC_LA_N[33]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"FMC_LA_P[00]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"FMC_LA_P[01]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"FMC_LA_P[02]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"FMC_LA_P[03]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"FMC_LA_P[04]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"FMC_LA_P[05]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"FMC_LA_P[06]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"FMC_LA_P[07]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"FMC_LA_P[08]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"FMC_LA_P[09]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"FMC_LA_P[10]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"FMC_LA_P[11]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"FMC_LA_P[12]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"FMC_LA_P[13]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"FMC_LA_P[14]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"FMC_LA_P[15]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"FMC_LA_P[16]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"FMC_LA_P[17]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"FMC_LA_P[18]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"FMC_LA_P[19]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"FMC_LA_P[20]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"FMC_LA_P[21]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"FMC_LA_P[22]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"FMC_LA_P[23]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"FMC_LA_P[24]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"FMC_LA_P[25]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"FMC_LA_P[26]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"FMC_LA_P[27]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"FMC_LA_P[28]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"FMC_LA_P[29]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"FMC_LA_P[30]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"FMC_LA_P[31]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"FMC_LA_P[32]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"FMC_LA_P[33]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"FMC_PRSNT_LS\": {\n            \"IOSTANDARD\": \"LVCMOS18\",\n            \"PACKAGE_PIN\": \"TBD\"\n        }\n    },\n    \"Fan\": {\n        \"FAN_PWM\": {\n            \"IOSTANDARD\": \"LVCMOS18\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"FAN_TACH\": {\n            \"IOSTANDARD\": \"LVCMOS18\",\n            \"PACKAGE_PIN\": \"TBD\"\n        }\n    },\n    \"I2C\": {\n        \"I2C_FPGA_SCL\": {\n            \"PIO_DIRECTION\": \"INPUT\",\n            \"IOSTANDARD\": \"LVCMOS18\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"I2C_FPGA_SDA\": {\n            \"PIO_DIRECTION\": \"BIDIR\",\n            \"IOSTANDARD\": \"LVCMOS18\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"I2C_MUX_RESET\": {\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"TBD\"\n        }\n    },\n    \"sdio\": {\n        \"cmd\": {\n            \"PIO_DIRECTION\": \"BIDIR\",\n            \"IOSTANDARD\": \"LVCMOS18\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"clk\": {\n            \"PIO_DIRECTION\": \"BIDIR\",\n            \"IOSTANDARD\": \"LVCMOS18\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"cd\": {\n            \"PIO_DIRECTION\": \"BIDIR\",\n            \"IOSTANDARD\": \"LVCMOS18\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"d0\": {\n            \"PIO_DIRECTION\": \"BIDIR\",\n            \"IOSTANDARD\": \"LVCMOS18\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"d1\": {\n            \"PIO_DIRECTION\": \"BIDIR\",\n            \"IOSTANDARD\": \"LVCMOS18\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"d2\": {\n            \"PIO_DIRECTION\": \"BIDIR\",\n            \"IOSTANDARD\": \"LVCMOS18\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"d3\": {\n            \"PIO_DIRECTION\": \"BIDIR\",\n            \"IOSTANDARD\": \"LVCMOS18\",\n            \"PACKAGE_PIN\": \"TBD\"\n        }\n    },\n    \"LED\": {\n        \"LED[0]\": {\n            \"PIO_DIRECTION\": \"OUTPUT\",\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"LED[1]\": {\n            \"PIO_DIRECTION\": \"OUTPUT\",\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"TBD\"\n        }\n    },\n    \"PCIE\": {\n        \"RST_N_pci_sys_reset_n\": {\n            \"IOSTANDARD\": \"LVCMOS18\",\n            \"PACKAGE_PIN\": \"AM17\"\n        },\n        \"PCIE_PRSNT_B_LS\": {\n            \"IOSTANDARD\": \"LVCMOS18\",\n            \"PACKAGE_PIN\": \"NOTCONNECTED\"\n        },\n        \"PCIE_WAKE\": {\n            \"IOSTANDARD\": \"LVCMOS18\",\n            \"PACKAGE_PIN\": \"AY17\"\n        },\n        \"CLK_pci_sys_clk_n\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"AL8\"\n        },\n        \"CLK_pci_sys_clk_p\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"AL9\"\n        }\n    },\n    \"PMODCTRL\": {\n        \"DIR_JA[0]\": {\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"DIR_JA[1]\": {\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"DIR_JA[2]\": {\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"DIR_JA[3]\": {\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"DIR_JA[4]\": {\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"DIR_JA[5]\": {\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"DIR_JA[6]\": {\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"DIR_JA[7]\": {\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"PMOD_OE_B\": {\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"TBD\"\n        }\n    },\n    \"PMODData\": {\n        \"JA_FPGA[0]\": {\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"JA_FPGA[1]\": {\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"JA_FPGA[2]\": {\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"JA_FPGA[3]\": {\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"JA_FPGA[4]\": {\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"JA_FPGA[5]\": {\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"JA_FPGA[6]\": {\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"JA_FPGA[7]\": {\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"TBD\"\n        }\n    },\n    \"POWER\": {\n        \"PCON_ALERT_B\": {\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"PCON_AUXFAULT_B\": {\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"PCON_FAULT\": {\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"PWR_SNS\": {\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"TBD\"\n        }\n    },\n    \"QDRIIA\": {\n        \"QDRII_SYSCLK_N\": {\n            \"IOSTANDARD\": \"LVDS\",\n\t\t\t\"DIFF_TERM\": \"TRUE\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"QDRII_SYSCLK_P\": {\n            \"IOSTANDARD\": \"LVDS\",\n\t\t\t\"DIFF_TERM\": \"TRUE\",\n            \"PACKAGE_PIN\": \"TBD\"\n        }\n    },\n    \"QDRIIC\": {\n        \"QDRIIC_SYSCLK_N\": {\n            \"IOSTANDARD\": \"LVDS\",\n\t\t\t\"DIFF_TERM\": \"TRUE\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"QDRIIC_SYSCLK_P\": {\n            \"IOSTANDARD\": \"LVDS\",\n\t\t\t\"DIFF_TERM\": \"TRUE\",\n            \"PACKAGE_PIN\": \"TBD\"\n        }\n    },\n    \"MICRO_SD\": {\n        \"SD_CCLK\": {\n            \"IOSTANDARD\": \"LVCMOS18\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"SD_CD\": {\n            \"IOSTANDARD\": \"LVCMOS18\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"SD_CMD\": {\n            \"IOSTANDARD\": \"LVCMOS18\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"SD_D[0]\": {\n            \"IOSTANDARD\": \"LVCMOS18\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"SD_D[1]\": {\n            \"IOSTANDARD\": \"LVCMOS18\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"SD_D[2]\": {\n            \"IOSTANDARD\": \"LVCMOS18\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"SD_D[3]\": {\n            \"IOSTANDARD\": \"LVCMOS18\",\n            \"PACKAGE_PIN\": \"TBD\"\n        }\n    },\n    \"SFPCLK\": {\n        \"SFP_CLK_ALARM_B\": {\n            \"PIO_DIRECTION\": \"INPUT\",\n            \"IOSTANDARD\": \"LVCMOS18\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"SFP_CLK_RST\": {\n            \"PIO_DIRECTION\": \"INPUT\",\n            \"IOSTANDARD\": \"LVCMOS18\",\n            \"PACKAGE_PIN\": \"TBD\"\n        }\n    },\n    \"SFP\": {\n        \"SFP_REFCLK_N\": {\n            \"PIO_DIRECTION\": \"INPUT\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"SFP_REFCLK_P\": {\n            \"PIO_DIRECTION\": \"INPUT\",\n            \"PACKAGE_PIN\": \"TBD\"\n        }\n    },\n    \"SFPA\": {\n        \"ETH1_LED[0]\": {\n            \"PIO_DIRECTION\": \"OUTPUT\",\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"ETH1_LED[1]\": {\n            \"PIO_DIRECTION\": \"OUTPUT\",\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"ETH1_MOD_DETECT\": {\n            \"PIO_DIRECTION\": \"INPUT\",\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"ETH1_RS[0]\": {\n            \"PIO_DIRECTION\": \"OUTPUT\",\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"ETH1_RS[1]\": {\n            \"PIO_DIRECTION\": \"OUTPUT\",\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"ETH1_RX_LOS\": {\n            \"PIO_DIRECTION\": \"INPUT\",\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"ETH1_TX_DISABLE\": {\n            \"PIO_DIRECTION\": \"OUTPUT\",\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"ETH1_TX_FAULT\": {\n            \"PIO_DIRECTION\": \"INPUT\",\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"ETH1_RX_p\": {\n            \"PIO_DIRECTION\": \"INPUT\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"ETH1_RX_n\": {\n            \"PIO_DIRECTION\": \"INPUT\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"ETH1_TX_p\": {\n            \"PIO_DIRECTION\": \"OUTPUT\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"ETH1_TX_n\": {\n            \"PIO_DIRECTION\": \"OUTPUT\",\n            \"PACKAGE_PIN\": \"TBD\"\n        }\n    },\n    \"SFPB\": {\n        \"ETH2_LED[0]\": {\n            \"PIO_DIRECTION\": \"OUTPUT\",\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"ETH2_LED[1]\": {\n            \"PIO_DIRECTION\": \"OUTPUT\",\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"ETH2_MOD_DETECT\": {\n            \"PIO_DIRECTION\": \"INPUT\",\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"ETH2_RS[0]\": {\n            \"PIO_DIRECTION\": \"OUTPUT\",\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"ETH2_RS[1]\": {\n            \"PIO_DIRECTION\": \"OUTPUT\",\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"ETH2_RX_LOS\": {\n            \"PIO_DIRECTION\": \"INPUT\",\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"ETH2_TX_DISABLE\": {\n            \"PIO_DIRECTION\": \"OUTPUT\",\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"ETH2_TX_FAULT\": {\n            \"PIO_DIRECTION\": \"INPUT\",\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"ETH2_RX_p\": {\n            \"PIO_DIRECTION\": \"INPUT\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"ETH2_RX_n\": {\n            \"PIO_DIRECTION\": \"INPUT\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"ETH2_TX_p\": {\n            \"PIO_DIRECTION\": \"OUTPUT\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"ETH2_TX_n\": {\n            \"PIO_DIRECTION\": \"OUTPUT\",\n            \"PACKAGE_PIN\": \"TBD\"\n        }\n    },\n    \"SFPC\": {\n        \"ETH3_LED[0]\": {\n            \"PIO_DIRECTION\": \"OUTPUT\",\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"ETH3_LED[1]\": {\n            \"PIO_DIRECTION\": \"OUTPUT\",\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"ETH3_MOD_DETECT\": {\n            \"PIO_DIRECTION\": \"INPUT\",\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"ETH3_RS[0]\": {\n            \"PIO_DIRECTION\": \"OUTPUT\",\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"ETH3_RS[1]\": {\n            \"PIO_DIRECTION\": \"OUTPUT\",\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"ETH3_RX_LOS\": {\n            \"PIO_DIRECTION\": \"INPUT\",\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"ETH3_TX_DISABLE\": {\n            \"PIO_DIRECTION\": \"OUTPUT\",\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"ETH3_TX_FAULT\": {\n            \"PIO_DIRECTION\": \"INPUT\",\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"ETH3_RX_p\": {\n            \"PIO_DIRECTION\": \"INPUT\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"ETH3_RX_n\": {\n            \"PIO_DIRECTION\": \"INPUT\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"ETH3_TX_p\": {\n            \"PIO_DIRECTION\": \"OUTPUT\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"ETH3_TX_n\": {\n            \"PIO_DIRECTION\": \"OUTPUT\",\n            \"PACKAGE_PIN\": \"TBD\"\n        }\n    },\n    \"SFPD\": {\n        \"ETH4_LED[0]\": {\n            \"PIO_DIRECTION\": \"OUTPUT\",\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"ETH4_LED[1]\": {\n            \"PIO_DIRECTION\": \"OUTPUT\",\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"ETH4_MOD_DETECT\": {\n            \"PIO_DIRECTION\": \"INPUT\",\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"ETH4_RS[0]\": {\n            \"PIO_DIRECTION\": \"OUTPUT\",\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"ETH4_RS[1]\": {\n            \"PIO_DIRECTION\": \"OUTPUT\",\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"ETH4_RX_LOS\": {\n            \"PIO_DIRECTION\": \"INPUT\",\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"ETH4_TX_DISABLE\": {\n            \"PIO_DIRECTION\": \"OUTPUT\",\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"ETH4_TX_FAULT\": {\n            \"PIO_DIRECTION\": \"INPUT\",\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"ETH4_RX_p\": {\n            \"PIO_DIRECTION\": \"INPUT\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"ETH4_RX_n\": {\n            \"PIO_DIRECTION\": \"INPUT\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"ETH4_TX_p\": {\n            \"PIO_DIRECTION\": \"OUTPUT\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"ETH4_TX_n\": {\n            \"PIO_DIRECTION\": \"OUTPUT\",\n            \"PACKAGE_PIN\": \"TBD\"\n        }\n    },\n    \"SI570\": {\n        \"USERCLK_N\": {\n            \"PIO_DIRECTION\": \"INPUT\",\n            \"IOSTANDARD\": \"LVDS\",\n\t\t\t\"DIFF_TERM\": \"TRUE\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"USERCLK_P\": {\n            \"PIO_DIRECTION\": \"INPUT\",\n            \"IOSTANDARD\": \"LVDS\",\n\t\t\t\"DIFF_TERM\": \"TRUE\",\n            \"PACKAGE_PIN\": \"TBD\"\n        }\n    },\n    \"UART\": {\n        \"UART_CTS\": {\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"UART_RTS\": {\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"UART_RXD_OUT\": {\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"UART_TXD_IN\": {\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"TBD\"\n        }\n    },\n    \"pins\": {\n        \"userClk_p\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVDS_25\",\n            \"DIFF_TERM\": \"TRUE\",\n            \"PIO_DIRECTION\": \"INPUT\"\n        },\n        \"userClk_n\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVDS_25\",\n            \"DIFF_TERM\": \"TRUE\",\n            \"PIO_DIRECTION\": \"INPUT\"\n        },\n        \"smaUserClk_p\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVDS_25\",\n            \"DIFF_TERM\": \"TRUE\",\n            \"PIO_DIRECTION\": \"OUTPUT\"\n        },\n        \"smaUserClk_n\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVDS_25\",\n            \"DIFF_TERM\": \"TRUE\",\n            \"PIO_DIRECTION\": \"OUTPUT\"\n        },\n        \"mgtRefClk_p\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVDS_25\",\n            \"DIFF_TERM\": \"TRUE\",\n            \"PIO_DIRECTION\": \"INPUT\"\n        },\n        \"mgtRefClk_n\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVDS_25\",\n            \"DIFF_TERM\": \"TRUE\",\n            \"PIO_DIRECTION\": \"INPUT\"\n        },\n        \"mgtRx_p\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"DIFF_TERM\": \"TRUE\",\n            \"PIO_DIRECTION\": \"INPUT\"\n        },\n        \"mgtRx_n\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"DIFF_TERM\": \"TRUE\",\n            \"PIO_DIRECTION\": \"INPUT\"\n        },\n        \"mgtTx_p\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"DIFF_TERM\": \"TRUE\",\n            \"PIO_DIRECTION\": \"OUTPUT\"\n        },\n        \"mgtTx_n\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"DIFF_TERM\": \"TRUE\",\n            \"PIO_DIRECTION\": \"OUTPUT\"\n        },\n        \"uart_d_in\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\",\n            \"PIO_DIRECTION\": \"INPUT\"\n        },\n        \"uart_d_out\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\",\n            \"PIO_DIRECTION\": \"OUTPUT\"\n        }\n    }\n}\n\n\n"
  },
  {
    "path": "boardinfo/vcu118.json",
    "content": "{\n    \"options\": {\n        \"bsvdefines\" : [\"XILINX=1\", \"VirtexUltrascalePlus\", \"VirtexUltrascale\", \"XilinxUltrascalePlus\", \"XilinxUltrascale\", \"PCIE\", \"PCIE3\", \"PcieHostInterface\", \"PhysAddrWidth=40\", \"NUMBER_OF_LEDS=2\", \"PcieLanes=8\",\n\t\t       \t\"CONNECTAL_BITS_DEPENDENCES=hw/mkTop.bit\", \"CONNECTAL_RUN_SCRIPT=$(CONNECTALDIR)/scripts/run.pcietest\"],\n        \"os\" : \"ubuntu\",\n        \"partname\" : \"xcvu9p-flga2104-2L-e\",\n        \"need_pcie\" : \"xuplus_gen3x8\",\n        \"TOP\" : \"PcieTop\",\n        \"constraints\": [\"constraints/xilinx/vcu118.xdc\"],\n        \"implconstraints\": [\"constraints/xilinx/vcu118.xdc\", \"constraints/xilinx/pcie-clocks.xdc\"],\n        \"runscript\" : \"run.pcietest\",\n        \"CONNECTALFLAGS\" : [\"--mainclockperiod=4\", \"--derivedclockperiod=4\", \"--pcieclockperiod=4\"],\n        \"rewireclockstring\" : \"\"\n    },\n    \"BTN\": {\n        \"BTN[0]\": {\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"BTN[1]\": {\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"TBD\"\n        }\n    },\n    \"CLK\": {\n        \"FPGA_SYSCLK_N\": {\n            \"PIO_DIRECTION\": \"INPUT\",\n            \"IOSTANDARD\": \"LVDS\",\n\t\t\t\"DIFF_TERM\": \"TRUE\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"FPGA_SYSCLK_P\": {\n            \"PIO_DIRECTION\": \"INPUT\",\n            \"IOSTANDARD\": \"LVDS\",\n\t\t\t\"DIFF_TERM\": \"TRUE\",\n            \"PACKAGE_PIN\": \"TBD\"\n        }\n    },\n    \"CPLD\": {\n        \"CPLD_IMGSEL[0]\": {\n            \"IOSTANDARD\": \"LVCMOS18\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"CPLD_IMGSEL[1]\": {\n            \"IOSTANDARD\": \"LVCMOS18\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"CPLD_IMGSEL[2]\": {\n            \"IOSTANDARD\": \"LVCMOS18\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"CPLD_RECONFIG\": {\n            \"IOSTANDARD\": \"LVCMOS18\",\n            \"PACKAGE_PIN\": \"TBD\"\n        }\n    },\n    \"DDR\": {\n        \"DDR3_SYSCLK_N\": {\n            \"IOSTANDARD\": \"LVDS\",\n\t\t\t\"DIFF_TERM\": \"TRUE\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"DDR3_SYSCLK_P\": {\n            \"IOSTANDARD\": \"LVDS\",\n\t\t\t\"DIFF_TERM\": \"TRUE\",\n            \"PACKAGE_PIN\": \"TBD\"\n        }\n    },\n    \"FMC\": {\n\t\"FMC_GBTCLK_P[00]\": {\n\t    \"DIFF_TERM\": \"TRUE\",\n            \"PACKAGE_PIN\": \"TBD\"\n\t},\n\t\"FMC_GBTCLK_N[00]\": {\n\t    \"DIFF_TERM\": \"TRUE\",\n            \"PACKAGE_PIN\": \"TBD\"\n\t},\n        \"FMC_CLK0_M2C_N\": {\n            \"IOSTANDARD\": \"LVDS\",\n\t    \"DIFF_TERM\": \"TRUE\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"FMC_CLK0_M2C_P\": {\n            \"IOSTANDARD\": \"LVDS\",\n\t\t\t\"DIFF_TERM\": \"TRUE\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"FMC_CLK1_M2C_N\": {\n            \"IOSTANDARD\": \"LVDS\",\n\t\t\t\"DIFF_TERM\": \"TRUE\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"FMC_CLK1_M2C_P\": {\n            \"IOSTANDARD\": \"LVDS\",\n\t\t\t\"DIFF_TERM\": \"TRUE\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"FMC_LA_N[00]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"FMC_LA_N[01]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"FMC_LA_N[02]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"FMC_LA_N[03]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"FMC_LA_N[04]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"FMC_LA_N[05]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"FMC_LA_N[06]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"FMC_LA_N[07]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"FMC_LA_N[08]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"FMC_LA_N[09]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"FMC_LA_N[10]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"FMC_LA_N[11]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"FMC_LA_N[12]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"FMC_LA_N[13]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"FMC_LA_N[14]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"FMC_LA_N[15]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"FMC_LA_N[16]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"FMC_LA_N[17]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"FMC_LA_N[18]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"FMC_LA_N[19]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"FMC_LA_N[20]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"FMC_LA_N[21]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"FMC_LA_N[22]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"FMC_LA_N[23]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"FMC_LA_N[24]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"FMC_LA_N[25]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"FMC_LA_N[26]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"FMC_LA_N[27]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"FMC_LA_N[28]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"FMC_LA_N[29]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"FMC_LA_N[30]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"FMC_LA_N[31]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"FMC_LA_N[32]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"FMC_LA_N[33]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"FMC_LA_P[00]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"FMC_LA_P[01]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"FMC_LA_P[02]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"FMC_LA_P[03]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"FMC_LA_P[04]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"FMC_LA_P[05]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"FMC_LA_P[06]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"FMC_LA_P[07]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"FMC_LA_P[08]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"FMC_LA_P[09]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"FMC_LA_P[10]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"FMC_LA_P[11]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"FMC_LA_P[12]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"FMC_LA_P[13]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"FMC_LA_P[14]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"FMC_LA_P[15]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"FMC_LA_P[16]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"FMC_LA_P[17]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"FMC_LA_P[18]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"FMC_LA_P[19]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"FMC_LA_P[20]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"FMC_LA_P[21]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"FMC_LA_P[22]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"FMC_LA_P[23]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"FMC_LA_P[24]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"FMC_LA_P[25]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"FMC_LA_P[26]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"FMC_LA_P[27]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"FMC_LA_P[28]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"FMC_LA_P[29]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"FMC_LA_P[30]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"FMC_LA_P[31]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"FMC_LA_P[32]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"FMC_LA_P[33]\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"FMC_PRSNT_LS\": {\n            \"IOSTANDARD\": \"LVCMOS18\",\n            \"PACKAGE_PIN\": \"TBD\"\n        }\n    },\n    \"Fan\": {\n        \"FAN_PWM\": {\n            \"IOSTANDARD\": \"LVCMOS18\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"FAN_TACH\": {\n            \"IOSTANDARD\": \"LVCMOS18\",\n            \"PACKAGE_PIN\": \"TBD\"\n        }\n    },\n    \"I2C\": {\n        \"I2C_FPGA_SCL\": {\n            \"PIO_DIRECTION\": \"INPUT\",\n            \"IOSTANDARD\": \"LVCMOS18\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"I2C_FPGA_SDA\": {\n            \"PIO_DIRECTION\": \"BIDIR\",\n            \"IOSTANDARD\": \"LVCMOS18\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"I2C_MUX_RESET\": {\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"TBD\"\n        }\n    },\n    \"sdio\": {\n        \"cmd\": {\n            \"PIO_DIRECTION\": \"BIDIR\",\n            \"IOSTANDARD\": \"LVCMOS18\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"clk\": {\n            \"PIO_DIRECTION\": \"BIDIR\",\n            \"IOSTANDARD\": \"LVCMOS18\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"cd\": {\n            \"PIO_DIRECTION\": \"BIDIR\",\n            \"IOSTANDARD\": \"LVCMOS18\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"d0\": {\n            \"PIO_DIRECTION\": \"BIDIR\",\n            \"IOSTANDARD\": \"LVCMOS18\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"d1\": {\n            \"PIO_DIRECTION\": \"BIDIR\",\n            \"IOSTANDARD\": \"LVCMOS18\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"d2\": {\n            \"PIO_DIRECTION\": \"BIDIR\",\n            \"IOSTANDARD\": \"LVCMOS18\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"d3\": {\n            \"PIO_DIRECTION\": \"BIDIR\",\n            \"IOSTANDARD\": \"LVCMOS18\",\n            \"PACKAGE_PIN\": \"TBD\"\n        }\n    },\n    \"LED\": {\n        \"LED[0]\": {\n            \"PIO_DIRECTION\": \"OUTPUT\",\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"LED[1]\": {\n            \"PIO_DIRECTION\": \"OUTPUT\",\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"TBD\"\n        }\n    },\n    \"PCIE\": {\n        \"RST_N_pci_sys_reset_n\": {\n            \"IOSTANDARD\": \"LVCMOS18\",\n            \"PACKAGE_PIN\": \"AM17\"\n        },\n        \"PCIE_PRSNT_B_LS\": {\n            \"IOSTANDARD\": \"LVCMOS18\",\n            \"PACKAGE_PIN\": \"NOTCONNECTED\"\n        },\n        \"PCIE_WAKE\": {\n            \"IOSTANDARD\": \"LVCMOS18\",\n            \"PACKAGE_PIN\": \"AY17\"\n        },\n        \"CLK_pci_sys_clk_n\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"AL8\"\n        },\n        \"CLK_pci_sys_clk_p\": {\n            \"IOSTANDARD\": \"LVDS\",\n            \"PACKAGE_PIN\": \"AL9\"\n        }\n    },\n    \"PMODCTRL\": {\n        \"DIR_JA[0]\": {\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"DIR_JA[1]\": {\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"DIR_JA[2]\": {\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"DIR_JA[3]\": {\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"DIR_JA[4]\": {\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"DIR_JA[5]\": {\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"DIR_JA[6]\": {\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"DIR_JA[7]\": {\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"PMOD_OE_B\": {\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"TBD\"\n        }\n    },\n    \"PMODData\": {\n        \"JA_FPGA[0]\": {\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"JA_FPGA[1]\": {\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"JA_FPGA[2]\": {\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"JA_FPGA[3]\": {\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"JA_FPGA[4]\": {\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"JA_FPGA[5]\": {\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"JA_FPGA[6]\": {\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"JA_FPGA[7]\": {\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"TBD\"\n        }\n    },\n    \"POWER\": {\n        \"PCON_ALERT_B\": {\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"PCON_AUXFAULT_B\": {\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"PCON_FAULT\": {\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"PWR_SNS\": {\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"TBD\"\n        }\n    },\n    \"QDRIIA\": {\n        \"QDRII_SYSCLK_N\": {\n            \"IOSTANDARD\": \"LVDS\",\n\t\t\t\"DIFF_TERM\": \"TRUE\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"QDRII_SYSCLK_P\": {\n            \"IOSTANDARD\": \"LVDS\",\n\t\t\t\"DIFF_TERM\": \"TRUE\",\n            \"PACKAGE_PIN\": \"TBD\"\n        }\n    },\n    \"QDRIIC\": {\n        \"QDRIIC_SYSCLK_N\": {\n            \"IOSTANDARD\": \"LVDS\",\n\t\t\t\"DIFF_TERM\": \"TRUE\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"QDRIIC_SYSCLK_P\": {\n            \"IOSTANDARD\": \"LVDS\",\n\t\t\t\"DIFF_TERM\": \"TRUE\",\n            \"PACKAGE_PIN\": \"TBD\"\n        }\n    },\n    \"MICRO_SD\": {\n        \"SD_CCLK\": {\n            \"IOSTANDARD\": \"LVCMOS18\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"SD_CD\": {\n            \"IOSTANDARD\": \"LVCMOS18\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"SD_CMD\": {\n            \"IOSTANDARD\": \"LVCMOS18\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"SD_D[0]\": {\n            \"IOSTANDARD\": \"LVCMOS18\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"SD_D[1]\": {\n            \"IOSTANDARD\": \"LVCMOS18\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"SD_D[2]\": {\n            \"IOSTANDARD\": \"LVCMOS18\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"SD_D[3]\": {\n            \"IOSTANDARD\": \"LVCMOS18\",\n            \"PACKAGE_PIN\": \"TBD\"\n        }\n    },\n    \"SFPCLK\": {\n        \"SFP_CLK_ALARM_B\": {\n            \"PIO_DIRECTION\": \"INPUT\",\n            \"IOSTANDARD\": \"LVCMOS18\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"SFP_CLK_RST\": {\n            \"PIO_DIRECTION\": \"INPUT\",\n            \"IOSTANDARD\": \"LVCMOS18\",\n            \"PACKAGE_PIN\": \"TBD\"\n        }\n    },\n    \"SFP\": {\n        \"SFP_REFCLK_N\": {\n            \"PIO_DIRECTION\": \"INPUT\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"SFP_REFCLK_P\": {\n            \"PIO_DIRECTION\": \"INPUT\",\n            \"PACKAGE_PIN\": \"TBD\"\n        }\n    },\n    \"SFPA\": {\n        \"ETH1_LED[0]\": {\n            \"PIO_DIRECTION\": \"OUTPUT\",\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"ETH1_LED[1]\": {\n            \"PIO_DIRECTION\": \"OUTPUT\",\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"ETH1_MOD_DETECT\": {\n            \"PIO_DIRECTION\": \"INPUT\",\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"ETH1_RS[0]\": {\n            \"PIO_DIRECTION\": \"OUTPUT\",\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"ETH1_RS[1]\": {\n            \"PIO_DIRECTION\": \"OUTPUT\",\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"ETH1_RX_LOS\": {\n            \"PIO_DIRECTION\": \"INPUT\",\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"ETH1_TX_DISABLE\": {\n            \"PIO_DIRECTION\": \"OUTPUT\",\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"ETH1_TX_FAULT\": {\n            \"PIO_DIRECTION\": \"INPUT\",\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"ETH1_RX_p\": {\n            \"PIO_DIRECTION\": \"INPUT\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"ETH1_RX_n\": {\n            \"PIO_DIRECTION\": \"INPUT\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"ETH1_TX_p\": {\n            \"PIO_DIRECTION\": \"OUTPUT\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"ETH1_TX_n\": {\n            \"PIO_DIRECTION\": \"OUTPUT\",\n            \"PACKAGE_PIN\": \"TBD\"\n        }\n    },\n    \"SFPB\": {\n        \"ETH2_LED[0]\": {\n            \"PIO_DIRECTION\": \"OUTPUT\",\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"ETH2_LED[1]\": {\n            \"PIO_DIRECTION\": \"OUTPUT\",\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"ETH2_MOD_DETECT\": {\n            \"PIO_DIRECTION\": \"INPUT\",\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"ETH2_RS[0]\": {\n            \"PIO_DIRECTION\": \"OUTPUT\",\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"ETH2_RS[1]\": {\n            \"PIO_DIRECTION\": \"OUTPUT\",\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"ETH2_RX_LOS\": {\n            \"PIO_DIRECTION\": \"INPUT\",\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"ETH2_TX_DISABLE\": {\n            \"PIO_DIRECTION\": \"OUTPUT\",\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"ETH2_TX_FAULT\": {\n            \"PIO_DIRECTION\": \"INPUT\",\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"ETH2_RX_p\": {\n            \"PIO_DIRECTION\": \"INPUT\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"ETH2_RX_n\": {\n            \"PIO_DIRECTION\": \"INPUT\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"ETH2_TX_p\": {\n            \"PIO_DIRECTION\": \"OUTPUT\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"ETH2_TX_n\": {\n            \"PIO_DIRECTION\": \"OUTPUT\",\n            \"PACKAGE_PIN\": \"TBD\"\n        }\n    },\n    \"SFPC\": {\n        \"ETH3_LED[0]\": {\n            \"PIO_DIRECTION\": \"OUTPUT\",\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"ETH3_LED[1]\": {\n            \"PIO_DIRECTION\": \"OUTPUT\",\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"ETH3_MOD_DETECT\": {\n            \"PIO_DIRECTION\": \"INPUT\",\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"ETH3_RS[0]\": {\n            \"PIO_DIRECTION\": \"OUTPUT\",\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"ETH3_RS[1]\": {\n            \"PIO_DIRECTION\": \"OUTPUT\",\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"ETH3_RX_LOS\": {\n            \"PIO_DIRECTION\": \"INPUT\",\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"ETH3_TX_DISABLE\": {\n            \"PIO_DIRECTION\": \"OUTPUT\",\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"ETH3_TX_FAULT\": {\n            \"PIO_DIRECTION\": \"INPUT\",\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"ETH3_RX_p\": {\n            \"PIO_DIRECTION\": \"INPUT\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"ETH3_RX_n\": {\n            \"PIO_DIRECTION\": \"INPUT\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"ETH3_TX_p\": {\n            \"PIO_DIRECTION\": \"OUTPUT\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"ETH3_TX_n\": {\n            \"PIO_DIRECTION\": \"OUTPUT\",\n            \"PACKAGE_PIN\": \"TBD\"\n        }\n    },\n    \"SFPD\": {\n        \"ETH4_LED[0]\": {\n            \"PIO_DIRECTION\": \"OUTPUT\",\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"ETH4_LED[1]\": {\n            \"PIO_DIRECTION\": \"OUTPUT\",\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"ETH4_MOD_DETECT\": {\n            \"PIO_DIRECTION\": \"INPUT\",\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"ETH4_RS[0]\": {\n            \"PIO_DIRECTION\": \"OUTPUT\",\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"ETH4_RS[1]\": {\n            \"PIO_DIRECTION\": \"OUTPUT\",\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"ETH4_RX_LOS\": {\n            \"PIO_DIRECTION\": \"INPUT\",\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"ETH4_TX_DISABLE\": {\n            \"PIO_DIRECTION\": \"OUTPUT\",\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"ETH4_TX_FAULT\": {\n            \"PIO_DIRECTION\": \"INPUT\",\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"ETH4_RX_p\": {\n            \"PIO_DIRECTION\": \"INPUT\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"ETH4_RX_n\": {\n            \"PIO_DIRECTION\": \"INPUT\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"ETH4_TX_p\": {\n            \"PIO_DIRECTION\": \"OUTPUT\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"ETH4_TX_n\": {\n            \"PIO_DIRECTION\": \"OUTPUT\",\n            \"PACKAGE_PIN\": \"TBD\"\n        }\n    },\n    \"SI570\": {\n        \"USERCLK_N\": {\n            \"PIO_DIRECTION\": \"INPUT\",\n            \"IOSTANDARD\": \"LVDS\",\n\t\t\t\"DIFF_TERM\": \"TRUE\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"USERCLK_P\": {\n            \"PIO_DIRECTION\": \"INPUT\",\n            \"IOSTANDARD\": \"LVDS\",\n\t\t\t\"DIFF_TERM\": \"TRUE\",\n            \"PACKAGE_PIN\": \"TBD\"\n        }\n    },\n    \"UART\": {\n        \"UART_CTS\": {\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"UART_RTS\": {\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"UART_RXD_OUT\": {\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"TBD\"\n        },\n        \"UART_TXD_IN\": {\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"PACKAGE_PIN\": \"TBD\"\n        }\n    },\n    \"pins\": {\n        \"userClk_p\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVDS_25\",\n            \"DIFF_TERM\": \"TRUE\",\n            \"PIO_DIRECTION\": \"INPUT\"\n        },\n        \"userClk_n\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVDS_25\",\n            \"DIFF_TERM\": \"TRUE\",\n            \"PIO_DIRECTION\": \"INPUT\"\n        },\n        \"smaUserClk_p\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVDS_25\",\n            \"DIFF_TERM\": \"TRUE\",\n            \"PIO_DIRECTION\": \"OUTPUT\"\n        },\n        \"smaUserClk_n\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVDS_25\",\n            \"DIFF_TERM\": \"TRUE\",\n            \"PIO_DIRECTION\": \"OUTPUT\"\n        },\n        \"mgtRefClk_p\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVDS_25\",\n            \"DIFF_TERM\": \"TRUE\",\n            \"PIO_DIRECTION\": \"INPUT\"\n        },\n        \"mgtRefClk_n\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVDS_25\",\n            \"DIFF_TERM\": \"TRUE\",\n            \"PIO_DIRECTION\": \"INPUT\"\n        },\n        \"mgtRx_p\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"DIFF_TERM\": \"TRUE\",\n            \"PIO_DIRECTION\": \"INPUT\"\n        },\n        \"mgtRx_n\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"DIFF_TERM\": \"TRUE\",\n            \"PIO_DIRECTION\": \"INPUT\"\n        },\n        \"mgtTx_p\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"DIFF_TERM\": \"TRUE\",\n            \"PIO_DIRECTION\": \"OUTPUT\"\n        },\n        \"mgtTx_n\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"DIFF_TERM\": \"TRUE\",\n            \"PIO_DIRECTION\": \"OUTPUT\"\n        },\n        \"uart_d_in\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\",\n            \"PIO_DIRECTION\": \"INPUT\"\n        },\n        \"uart_d_out\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\",\n            \"PIO_DIRECTION\": \"OUTPUT\"\n        }\n    }\n}\n\n\n"
  },
  {
    "path": "boardinfo/verilator.json",
    "content": "{\n    \"options\": {\n        \"os\" : \"ubuntu\",\n        \"partname\" : \"xc7z020clg484-1\",\n        \"rewireclockstring\" : \"tclzynqrewireclock\",\n        \"TOP\" : \"XsimTop\",\n\t\"bsvdefines\": [\"CnocTop\", \"XsimHostInterface\", \"PhysAddrWidth=40\", \"SIMULATION\", \"SVDPI\",\n\t\t       \t\"CONNECTAL_BITS_DEPENDENCES=vlsim\"],\n        \"CONNECTALFLAGS\" : [\"--mainclockperiod=20\", \"--derivedclockperiod=10\"],\n        \"need_pcie\" : \"unused\"\n    }\n}\n\n\n"
  },
  {
    "path": "boardinfo/vsim.json",
    "content": "{\n    \"options\": {\n        \"os\" : \"ubuntu\",\n        \"partname\" : \"5SGXEA7N2F45C2\",\n        \"rewireclockstring\" : \"tclzynqrewireclock\",\n        \"TOP\" : \"XsimTop\",\n\t\"bsvdefines\": [\"MODELSIM=1\", \"CnocTop\", \"XsimHostInterface\", \"PhysAddrWidth=40\", \"XSIM\", \"SIMULATION\", \"SVDPI\", \"PcieLanes=8\",\n\t\t       \t\"CONNECTAL_BITS_DEPENDENCES=vsim\"],\n        \"CONNECTALFLAGS\" : [\"--mainclockperiod=20\", \"--derivedclockperiod=10\"],\n        \"need_pcie\" : \"unused\"\n    }\n}\n\n\n"
  },
  {
    "path": "boardinfo/xsim.json",
    "content": "{\n    \"options\": {\n        \"os\" : \"ubuntu\",\n        \"partname\" : \"xc7z020clg484-1\",\n        \"rewireclockstring\" : \"tclzynqrewireclock\",\n        \"TOP\" : \"XsimTop\",\n\t\"bsvdefines\": [\"XILINX=1\", \"CnocTop\", \"XsimHostInterface\", \"PhysAddrWidth=40\", \"XSIM\", \"SIMULATION\", \"SVDPI\", \"PcieLanes=8\",\n\t\t       \t\"CONNECTAL_BITS_DEPENDENCES=xsim\"],\n        \"CONNECTALFLAGS\" : [\"--mainclockperiod=20\", \"--derivedclockperiod=10\"],\n        \"need_pcie\" : \"unused\"\n    }\n}\n\n\n"
  },
  {
    "path": "boardinfo/zc702.json",
    "content": "{\n    \"options\": {\n        \"bsvdefines\" : [\"XILINX=1\", \"ZYNQ\", \"ZynqHostInterface\", \"PhysAddrWidth=32\",\n\t\t\t\"CONNECTAL_BITS_DEPENDENCES=hw/mkTop.bit\", \"CONNECTAL_RUN_SCRIPT=$(CONNECTALDIR)/scripts/run.android\",\n\t\t\t\"CONNECTAL_EXENAME=android.exe\", \"CONNECTAL_EXENAME2=android.exe2\"],\n        \"os\" : \"android\",\n        \"partname\" : \"xc7z020clg484-1\",\n        \"rewireclockstring\" : \"tclzynqrewireclock\",\n        \"constraints\": [],\n        \"implconstraints\": [\"constraints/xilinx/zc7z020clg484.xdc\"],\n        \"TOP\" : \"ZynqTop\",\n        \"runscript\" : \"run.android\",\n        \"CONNECTALFLAGS\" : [\"--mainclockperiod=10\", \"--derivedclockperiod=5\"],\n        \"need_pcie\" : \"unused\"\n    },\n    \"fmc1\": {\n\t\"LA00_p_CC\": {\n            \"LOC\": \"K19\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n        },\n\t\"LA00_n_CC\": {\n            \"LOC\": \"K20\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n        },\n\t\"LA01_p_CC\": {\n            \"LOC\": \"N19\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n        },\n\t\"LA01_n_CC\": {\n            \"LOC\": \"N20\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n        },\n\t\"LA02_p\": {\n            \"LOC\": \"L21\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n        },\n\t\"LA02_n\": {\n            \"LOC\": \"L22\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n        },\n\t\"LA03_p\": {\n            \"LOC\": \"J20\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n        },\n\t\"LA03_n\": {\n            \"LOC\": \"K21\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n        },\n\t\"LA04_p\": {\n            \"LOC\": \"M21\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n        },\n\t\"LA04_n\": {\n            \"LOC\": \"M22\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n        },\n\t\"LA05_p\": {\n            \"LOC\": \"N17\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n        },\n\t\"LA05_n\": {\n            \"LOC\": \"N18\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n        },\n\t\"LA06_p\": {\n            \"LOC\": \"J18\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n        },\n\t\"LA06_n\": {\n            \"LOC\": \"K18\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n        },\n\t\"LA07_p\": {\n            \"LOC\": \"J15\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n        },\n\t\"LA07_n\": {\n            \"LOC\": \"K15\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n        },\n\t\"LA08_p\": {\n            \"LOC\": \"J21\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n        },\n\t\"LA08_n\": {\n            \"LOC\": \"J22\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n        },\n\t\"LA09_p\": {\n            \"LOC\": \"M15\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n        },\n\t\"LA09_n\": {\n            \"LOC\": \"M16\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n        },\n\t\"LA10_p\": {\n            \"LOC\": \"L17\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n        },\n\t\"LA10_n\": {\n            \"LOC\": \"M17\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n        },\n\t\"LA11_p\": {\n            \"LOC\": \"R20\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n        },\n\t\"LA11_n\": {\n            \"LOC\": \"R21\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n        },\n\t\"LA12_p\": {\n            \"LOC\": \"N22\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n        },\n\t\"LA12_n\": {\n            \"LOC\": \"P22\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n        },\n\t\"LA13_p\": {\n            \"LOC\": \"P16\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n        },\n\t\"LA13_n\": {\n            \"LOC\": \"R16\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n        },\n\t\"LA14_p\": {\n            \"LOC\": \"J16\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n        },\n\t\"LA14_n\": {\n            \"LOC\": \"J17\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n        },\n\t\"LA15_p\": {\n            \"LOC\": \"P20\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n        },\n\t\"LA15_n\": {\n            \"LOC\": \"P21\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n        },\n\t\"LA16_p\": {\n            \"LOC\": \"N15\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n        },\n\t\"LA16_n\": {\n            \"LOC\": \"P15\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n        },\n\t\"LA17_p_CC\": {\n            \"LOC\": \"B19\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n        },\n\t\"LA17_n_CC\": {\n            \"LOC\": \"B20\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n        },\n\t\"LA18_p_CC\": {\n            \"LOC\": \"D20\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n        },\n\t\"LA18_n_CC\": {\n            \"LOC\": \"C20\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n        },\n\t\"LA19_p\": {\n            \"LOC\": \"E19\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n        },\n\t\"LA19_n\": {\n            \"LOC\": \"E20\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n        },\n\t\"CLK0_M2C_p\": {\n            \"LOC\": \"L18\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n        },\n\t\"CLK0_M2C_n\": {\n            \"LOC\": \"L19\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n        }\n    },\n    \"fmc2\": {\n\t\"LA00_p_CC\": {\n            \"LOC\": \"Y19\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n\t},\n\t\"LA00_n_CC\": {\n            \"LOC\": \"AA19\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n\t},\n\t\"LA01_p_CC\": {\n            \"LOC\": \"W16\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n\t},\n\t\"LA01_n_CC\": {\n            \"LOC\": \"Y16\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n\t},\n\t\"LA02_p\": {\n            \"LOC\": \"V14\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n\t},\n\t\"LA02_n\": {\n            \"LOC\": \"V15\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n\t},\n\t\"LA03_p\": {\n            \"LOC\": \"AA16\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n\t},\n\t\"LA03_n\": {\n            \"LOC\": \"AB16\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n\t},\n\t\"LA04_p\": {\n            \"LOC\": \"V13\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n\t},\n\t\"LA04_n\": {\n            \"LOC\": \"W13\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n\t},\n\t\"LA05_p\": {\n            \"LOC\": \"AB19\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n\t},\n\t\"LA05_n\": {\n            \"LOC\": \"AB20\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n\t},\n\t\"LA06_p\": {\n            \"LOC\": \"U17\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n\t},\n\t\"LA06_n\": {\n            \"LOC\": \"V17\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n\t},\n\t\"LA07_p\": {\n            \"LOC\": \"T21\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n\t},\n\t\"LA07_n\": {\n            \"LOC\": \"U21\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n\t},\n\t\"LA08_p\": {\n            \"LOC\": \"AA17\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n\t},\n\t\"LA08_n\": {\n            \"LOC\": \"AB17\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n\t},\n\t\"LA09_p\": {\n            \"LOC\": \"U15\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n\t},\n\t\"LA09_n\": {\n            \"LOC\": \"U16\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n\t},\n\t\"LA10_p\": {\n            \"LOC\": \"Y20\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n\t},\n\t\"LA10_n\": {\n            \"LOC\": \"Y21\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n\t},\n\t\"LA11_p\": {\n            \"LOC\": \"Y14\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n\t},\n\t\"LA11_n\": {\n            \"LOC\": \"AA14\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n\t},\n\t\"LA12_p\": {\n            \"LOC\": \"W15\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n\t},\n\t\"LA12_n\": {\n            \"LOC\": \"Y15\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n\t},\n\t\"LA13_p\": {\n            \"LOC\": \"V22\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n\t},\n\t\"LA13_n\": {\n            \"LOC\": \"W22\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n\t},\n\t\"LA14_p\": {\n            \"LOC\": \"T22\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n\t},\n\t\"LA14_n\": {\n            \"LOC\": \"U22\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n\t},\n\t\"LA15_p\": {\n            \"LOC\": \"Y13\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n\t},\n\t\"LA15_n\": {\n            \"LOC\": \"AA13\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n\t},\n\t\"LA16_p\": {\n            \"LOC\": \"AB14\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n\t},\n\t\"LA16_n\": {\n            \"LOC\": \"AB15\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n\t},\n\t\"LA17_p_CC\": {\n            \"LOC\": \"AA7\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n\t},\n\t\"LA17_n_CC\": {\n            \"LOC\": \"AA6\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n\t},\n\t\"LA18_p_CC\": {\n            \"LOC\": \"AA9\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n\t},\n\t\"LA18_n_CC\": {\n            \"LOC\": \"AA8\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n\t},\n\t\"LA19_p\": {\n            \"LOC\": \"R6\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n\t},\n\t\"LA19_n\": {\n            \"LOC\": \"T6\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n\t},\n\t\"CLK0_M2C_p\": {\n            \"LOC\": \"Y18\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n\t},\n\t\"CLK0_M2C_n\": {\n            \"LOC\": \"AA18\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n\t}\n    },\n    \"leds\" : {\n    \t\"L0\" : {\n\t     \"LOC\" : \"E15\",\n             \"IOSTANDARD\" : \"LVCMOS25\",\n\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t     },\n    \t\"L1\" : {\n\t     \"LOC\" : \"D15\",\n             \"IOSTANDARD\" : \"LVCMOS25\",\n\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t     },\n    \t\"L2\" : {\n\t     \"LOC\" : \"W17\",\n             \"IOSTANDARD\" : \"LVCMOS25\",\n\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t     },\n    \t\"L3\" : {\n\t     \"LOC\" : \"W5\",\n             \"IOSTANDARD\" : \"LVCMOS25\",\n\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t     },\n    \t\"L4\" : {\n\t     \"LOC\" : \"V7\",\n             \"IOSTANDARD\" : \"LVCMOS25\",\n\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t     },\n    \t\"L5\" : {\n\t     \"LOC\" : \"W10\",\n             \"IOSTANDARD\" : \"LVCMOS25\",\n\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t     },\n    \t\"L6\" : {\n\t     \"LOC\" : \"P18\",\n             \"IOSTANDARD\" : \"LVCMOS25\",\n\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t     },\n    \t\"L7\" : {\n\t     \"LOC\" : \"P17\",\n             \"IOSTANDARD\" : \"LVCMOS25\",\n\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t     }\n    },  \n    \"xadc\" : {\n    \t\"L0\" : {\n\t     \"LOC\" : \"H17\",\n             \"IOSTANDARD\" : \"LVCMOS25\",\n\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t     },\n    \t\"L1\" : {\n\t     \"LOC\" : \"H22\",\n             \"IOSTANDARD\" : \"LVCMOS25\",\n\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t     },\n    \t\"L2\" : {\n\t     \"LOC\" : \"G22\",\n             \"IOSTANDARD\" : \"LVCMOS25\",\n\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t     },\n    \t\"L3\" : {\n\t     \"LOC\" : \"H18\",\n             \"IOSTANDARD\" : \"LVCMOS25\",\n\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t     }\n    },\n    \"hdmi\" : {\n        \"clock\" : {\n             \"LOC\" : \"L16\",\n\t     \"IOSTANDARD\" : \"LVCMOS25\",\n             \"PIO_DIRECTION\": \"OUTPUT\"\n\t     },\n        \"hsync\" : {\n             \"LOC\" : \"R18\",\n\t     \"IOSTANDARD\" : \"LVCMOS25\",\n             \"PIO_DIRECTION\": \"OUTPUT\"\n\t     },\n        \"vsync\" : {\n             \"LOC\" : \"H15\",\n\t     \"IOSTANDARD\" : \"LVCMOS25\",\n             \"PIO_DIRECTION\": \"OUTPUT\"\n\t     },\n        \"de\" : {\n             \"LOC\" : \"T18\",\n\t     \"IOSTANDARD\" : \"LVCMOS25\",\n             \"PIO_DIRECTION\": \"OUTPUT\"\n\t     },\n        \"data[0]\" : {\n             \"LOC\" : \"AB21\",\n\t     \"IOSTANDARD\" : \"LVCMOS25\",\n             \"PIO_DIRECTION\": \"OUTPUT\"\n\t     },\n        \"data[1]\" : {\n             \"LOC\" : \"AA21\",\n\t     \"IOSTANDARD\" : \"LVCMOS25\",\n             \"PIO_DIRECTION\": \"OUTPUT\"\n\t     },\n        \"data[2]\" : {\n             \"LOC\" : \"AB22\",\n\t     \"IOSTANDARD\" : \"LVCMOS25\",\n             \"PIO_DIRECTION\": \"OUTPUT\"\n\t     },\n        \"data[3]\" : {\n             \"LOC\" : \"AA22\",\n\t     \"IOSTANDARD\" : \"LVCMOS25\",\n             \"PIO_DIRECTION\": \"OUTPUT\"\n\t     },\n        \"data[4]\" : {\n             \"LOC\" : \"V19\",\n\t     \"IOSTANDARD\" : \"LVCMOS25\",\n             \"PIO_DIRECTION\": \"OUTPUT\"\n\t     },\n        \"data[5]\" : {\n             \"LOC\" : \"V18\",\n\t     \"IOSTANDARD\" : \"LVCMOS25\",\n             \"PIO_DIRECTION\": \"OUTPUT\"\n\t     },\n        \"data[6]\" : {\n             \"LOC\" : \"V20\",\n\t     \"IOSTANDARD\" : \"LVCMOS25\",\n             \"PIO_DIRECTION\": \"OUTPUT\"\n\t     },\n        \"data[7]\" : {\n             \"LOC\" : \"U20\",\n\t     \"IOSTANDARD\" : \"LVCMOS25\",\n             \"PIO_DIRECTION\": \"OUTPUT\"\n\t     },\n        \"data[8]\" : {\n             \"LOC\" : \"W21\",\n\t     \"IOSTANDARD\" : \"LVCMOS25\",\n             \"PIO_DIRECTION\": \"OUTPUT\"\n\t     },\n        \"data[9]\" : {\n             \"LOC\" : \"W20\",\n\t     \"IOSTANDARD\" : \"LVCMOS25\",\n             \"PIO_DIRECTION\": \"OUTPUT\"\n\t     },\n        \"data[10]\" : {\n             \"LOC\" : \"W18\",\n\t     \"IOSTANDARD\" : \"LVCMOS25\",\n             \"PIO_DIRECTION\": \"OUTPUT\"\n\t     },\n        \"data[11]\" : {\n             \"LOC\" : \"T19\",\n\t     \"IOSTANDARD\" : \"LVCMOS25\",\n             \"PIO_DIRECTION\": \"OUTPUT\"\n\t     },\n        \"data[12]\" : {\n             \"LOC\" : \"U19\",\n\t     \"IOSTANDARD\" : \"LVCMOS25\",\n             \"PIO_DIRECTION\": \"OUTPUT\"\n\t     },\n        \"data[13]\" : {\n             \"LOC\" : \"R19\",\n\t     \"IOSTANDARD\" : \"LVCMOS25\",\n             \"PIO_DIRECTION\": \"OUTPUT\"\n\t     },\n        \"data[14]\" : {\n             \"LOC\" : \"T17\",\n\t     \"IOSTANDARD\" : \"LVCMOS25\",\n             \"PIO_DIRECTION\": \"OUTPUT\"\n\t     },\n        \"data[15]\" : {\n             \"LOC\" : \"T16\",\n\t     \"IOSTANDARD\" : \"LVCMOS25\",\n             \"PIO_DIRECTION\": \"OUTPUT\"\n\t     }\n    }\n}\n"
  },
  {
    "path": "boardinfo/zc706.json",
    "content": "{\n    \"options\": {\n        \"os\" : \"android\",\n        \"partname\" : \"xc7z045ffg900-2\",\n        \"rewireclockstring\" : \"tclzynqrewireclock\",\n        \"constraints\": [\"constraints/xilinx/xc7z045ffg900.xdc\", \"constraints/xilinx/zc706.xdc\"],\n        \"implconstraints\": [\"constraints/xilinx/xc7z045ffg900.xdc\", \"constraints/xilinx/zc706.xdc\"],\n        \"TOP\" : \"ZynqTop\",\n        \"runscript\" : \"run.android\",\n        \"bsvdefines\" : [\"XILINX=1\", \"ZYNQ\", \"ZynqHostInterface\", \"PhysAddrWidth=32\", \"NUMBER_OF_LEDS=4\", \"PcieLanes=4\",\n\t\t\t\"CONNECTAL_BITS_DEPENDENCES=hw/mkTop.bit\", \"CONNECTAL_RUN_SCRIPT=$(CONNECTALDIR)/scripts/run.android\",\n\t\t\t\"CONNECTAL_EXENAME=android.exe\", \"CONNECTAL_EXENAME2=android.exe2\"],\n        \"CONNECTALFLAGS\": [\"--mainclockperiod=5\", \"--derivedclockperiod=2.5\"],\n        \"need_pcie\" : \"unused\"\n    },\n    \"sfp1\": {\n        \"mod_def0\": {\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"LOC\": \"AB20\"\n        },\n        \"mod_def1\": {\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"LOC\": \"AB19\"\n        },\n        \"mod_def2\": {\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"LOC\": \"AA19\"\n        },\n        \"rx_los\": {\n            \"PIO_DIRECTION\": \"INPUT\",\n            \"IOSTANDARD\": \"LVCMOS25\",\n            \"LOC\": \"AE20\"\n        },\n        \"tx_disable\": {\n            \"PIO_DIRECTION\": \"OUTPUT\",\n            \"IOSTANDARD\": \"LVCMOS25\",\n            \"LOC\": \"AA18\"\n        },\n        \"tx_fault\": {\n            \"PIO_DIRECTION\": \"INPUT\",\n            \"IOSTANDARD\": \"LVCMOS25\",\n            \"LOC\": \"AD19\"\n        },\n        \"rxp\": {\n            \"PIO_DIRECTION\": \"INPUT\",\n            \"LOC\": \"AC4\"\n        },\n        \"rxn\": {\n            \"PIO_DIRECTION\": \"INPUT\",\n            \"LOC\": \"AC3\"\n        },\n        \"txp\": {\n            \"PIO_DIRECTION\": \"OUTPUT\",\n            \"LOC\": \"AB2\"\n        },\n        \"txn\": {\n            \"PIO_DIRECTION\": \"OUTPUT\",\n            \"LOC\": \"AB1\"\n        }\n    },\n    \"lpcfmc\": {\n\t\"CLK0_M2C_N\": {\n\t    \"IOSTANDARD\": \"LVCMOS25\",\n\t    \"PACKAGE_PIN\": \"AG16\"\n\t},\n\t\"CLK0_M2C_P\": {\n\t    \"IOSTANDARD\": \"LVCMOS25\",\n\t    \"PACKAGE_PIN\": \"AG17\"\n\t},\n\t\"CLK1_M2C_N\": {\n\t    \"IOSTANDARD\": \"LVCMOS25\",\n\t    \"PACKAGE_PIN\": \"AD28\"\n\t},\n\t\"CLK1_M2C_P\": {\n\t    \"IOSTANDARD\": \"LVCMOS25\",\n\t    \"PACKAGE_PIN\": \"AC28\"\n\t},\n\t\"LA00_CC_N\": {\n\t    \"IOSTANDARD\": \"LVCMOS25\",\n\t    \"PACKAGE_PIN\": \"AF13\"\n\t},\n\t\"LA00_CC_P\": {\n\t    \"IOSTANDARD\": \"LVCMOS25\",\n\t    \"PACKAGE_PIN\": \"AE13\"\n\t},\n\t\"LA01_CC_N\": {\n\t    \"IOSTANDARD\": \"LVCMOS25\",\n\t    \"PACKAGE_PIN\": \"AG15\"\n\t},\n\t\"LA01_CC_P\": {\n\t    \"IOSTANDARD\": \"LVCMOS25\",\n\t    \"PACKAGE_PIN\": \"AF15\"\n\t},\n\t\"LA02_N\": {\n\t    \"IOSTANDARD\": \"LVCMOS25\",\n\t    \"PACKAGE_PIN\": \"AF12\"\n\t},\n\t\"LA02_P\": {\n\t    \"IOSTANDARD\": \"LVCMOS25\",\n\t    \"PACKAGE_PIN\": \"AE12\"\n\t},\n\t\"LA03_N\": {\n\t    \"IOSTANDARD\": \"LVCMOS25\",\n\t    \"PACKAGE_PIN\": \"AH12\"\n\t},\n\t\"LA03_P\": {\n\t    \"IOSTANDARD\": \"LVCMOS25\",\n\t    \"PACKAGE_PIN\": \"AG12\"\n\t},\n\t\"LA04_N\": {\n\t    \"IOSTANDARD\": \"LVCMOS25\",\n\t    \"PACKAGE_PIN\": \"AK15\"\n\t},\n\t\"LA04_P\": {\n\t    \"IOSTANDARD\": \"LVCMOS25\",\n\t    \"PACKAGE_PIN\": \"AJ15\"\n\t},\n\t\"LA05_N\": {\n\t    \"IOSTANDARD\": \"LVCMOS25\",\n\t    \"PACKAGE_PIN\": \"AE15\"\n\t},\n\t\"LA05_P\": {\n\t    \"IOSTANDARD\": \"LVCMOS25\",\n\t    \"PACKAGE_PIN\": \"AE16\"\n\t},\n\t\"LA06_N\": {\n\t    \"IOSTANDARD\": \"LVCMOS25\",\n\t    \"PACKAGE_PIN\": \"AC12\"\n\t},\n\t\"LA06_P\": {\n\t    \"IOSTANDARD\": \"LVCMOS25\",\n\t    \"PACKAGE_PIN\": \"AB12\"\n\t},\n\t\"LA07_N\": {\n\t    \"IOSTANDARD\": \"LVCMOS25\",\n\t    \"PACKAGE_PIN\": \"AA14\"\n\t},\n\t\"LA07_P\": {\n\t    \"IOSTANDARD\": \"LVCMOS25\",\n\t    \"PACKAGE_PIN\": \"AA15\"\n\t},\n\t\"LA08_N\": {\n\t    \"IOSTANDARD\": \"LVCMOS25\",\n\t    \"PACKAGE_PIN\": \"AD13\"\n\t},\n\t\"LA08_P\": {\n\t    \"IOSTANDARD\": \"LVCMOS25\",\n\t    \"PACKAGE_PIN\": \"AD14\"\n\t},\n\t\"LA09_N\": {\n\t    \"IOSTANDARD\": \"LVCMOS25\",\n\t    \"PACKAGE_PIN\": \"AH13\"\n\t},\n\t\"LA09_P\": {\n\t    \"IOSTANDARD\": \"LVCMOS25\",\n\t    \"PACKAGE_PIN\": \"AH14\"\n\t},\n\t\"LA10_N\": {\n\t    \"IOSTANDARD\": \"LVCMOS25\",\n\t    \"PACKAGE_PIN\": \"AC13\"\n\t},\n\t\"LA10_P\": {\n\t    \"IOSTANDARD\": \"LVCMOS25\",\n\t    \"PACKAGE_PIN\": \"AC14\"\n\t},\n\t\"LA11_N\": {\n\t    \"IOSTANDARD\": \"LVCMOS25\",\n\t    \"PACKAGE_PIN\": \"AK16\"\n\t},\n\t\"LA11_P\": {\n\t    \"IOSTANDARD\": \"LVCMOS25\",\n\t    \"PACKAGE_PIN\": \"AJ16\"\n\t},\n\t\"LA12_N\": {\n\t    \"IOSTANDARD\": \"LVCMOS25\",\n\t    \"PACKAGE_PIN\": \"AD15\"\n\t},\n\t\"LA12_P\": {\n\t    \"IOSTANDARD\": \"LVCMOS25\",\n\t    \"PACKAGE_PIN\": \"AD16\"\n\t},\n\t\"LA13_N\": {\n\t    \"IOSTANDARD\": \"LVCMOS25\",\n\t    \"PACKAGE_PIN\": \"AH16\"\n\t},\n\t\"LA13_P\": {\n\t    \"IOSTANDARD\": \"LVCMOS25\",\n\t    \"PACKAGE_PIN\": \"AH17\"\n\t},\n\t\"LA14_N\": {\n\t    \"IOSTANDARD\": \"LVCMOS25\",\n\t    \"PACKAGE_PIN\": \"AF17\"\n\t},\n\t\"LA14_P\": {\n\t    \"IOSTANDARD\": \"LVCMOS25\",\n\t    \"PACKAGE_PIN\": \"AF18\"\n\t},\n\t\"LA15_N\": {\n\t    \"IOSTANDARD\": \"LVCMOS25\",\n\t    \"PACKAGE_PIN\": \"AB14\"\n\t},\n\t\"LA15_P\": {\n\t    \"IOSTANDARD\": \"LVCMOS25\",\n\t    \"PACKAGE_PIN\": \"AB15\"\n\t},\n\t\"LA16_N\": {\n\t    \"IOSTANDARD\": \"LVCMOS25\",\n\t    \"PACKAGE_PIN\": \"AE17\"\n\t},\n\t\"LA16_P\": {\n\t    \"IOSTANDARD\": \"LVCMOS25\",\n\t    \"PACKAGE_PIN\": \"AE18\"\n\t},\n\t\"LA17_CC_N\": {\n\t    \"IOSTANDARD\": \"LVCMOS25\",\n\t    \"PACKAGE_PIN\": \"AC27\"\n\t},\n\t\"LA17_CC_P\": {\n\t    \"IOSTANDARD\": \"LVCMOS25\",\n\t    \"PACKAGE_PIN\": \"AB27\"\n\t},\n\t\"LA18_CC_N\": {\n\t    \"IOSTANDARD\": \"LVCMOS25\",\n\t    \"PACKAGE_PIN\": \"AF27\"\n\t},\n\t\"LA18_CC_P\": {\n\t    \"IOSTANDARD\": \"LVCMOS25\",\n\t    \"PACKAGE_PIN\": \"AE27\"\n\t},\n\t\"LA19_N\": {\n\t    \"IOSTANDARD\": \"LVCMOS25\",\n\t    \"PACKAGE_PIN\": \"AH27\"\n\t},\n\t\"LA19_P\": {\n\t    \"IOSTANDARD\": \"LVCMOS25\",\n\t    \"PACKAGE_PIN\": \"AH26\"\n\t},\n\t\"LA20_N\": {\n\t    \"IOSTANDARD\": \"LVCMOS25\",\n\t    \"PACKAGE_PIN\": \"AG27\"\n\t},\n\t\"LA20_P\": {\n\t    \"IOSTANDARD\": \"LVCMOS25\",\n\t    \"PACKAGE_PIN\": \"AG26\"\n\t},\n\t\"LA21_N\": {\n\t    \"IOSTANDARD\": \"LVCMOS25\",\n\t    \"PACKAGE_PIN\": \"AH29\"\n\t},\n\t\"LA21_P\": {\n\t    \"IOSTANDARD\": \"LVCMOS25\",\n\t    \"PACKAGE_PIN\": \"AH28\"\n\t},\n\t\"LA22_N\": {\n\t    \"IOSTANDARD\": \"LVCMOS25\",\n\t    \"PACKAGE_PIN\": \"AK28\"\n\t},\n\t\"LA22_P\": {\n\t    \"IOSTANDARD\": \"LVCMOS25\",\n\t    \"PACKAGE_PIN\": \"AK27\"\n\t},\n\t\"LA23_N\": {\n\t    \"IOSTANDARD\": \"LVCMOS25\",\n\t    \"PACKAGE_PIN\": \"AK26\"\n\t},\n\t\"LA23_P\": {\n\t    \"IOSTANDARD\": \"LVCMOS25\",\n\t    \"PACKAGE_PIN\": \"AJ26\"\n\t},\n\t\"LA24_N\": {\n\t    \"IOSTANDARD\": \"LVCMOS25\",\n\t    \"PACKAGE_PIN\": \"AG30\"\n\t},\n\t\"LA24_P\": {\n\t    \"IOSTANDARD\": \"LVCMOS25\",\n\t    \"PACKAGE_PIN\": \"AF30\"\n\t},\n\t\"LA25_N\": {\n\t    \"IOSTANDARD\": \"LVCMOS25\",\n\t    \"PACKAGE_PIN\": \"AG29\"\n\t},\n\t\"LA25_P\": {\n\t    \"IOSTANDARD\": \"LVCMOS25\",\n\t    \"PACKAGE_PIN\": \"AF29\"\n\t},\n\t\"LA26_N\": {\n\t    \"IOSTANDARD\": \"LVCMOS25\",\n\t    \"PACKAGE_PIN\": \"AK30\"\n\t},\n\t\"LA26_P\": {\n\t    \"IOSTANDARD\": \"LVCMOS25\",\n\t    \"PACKAGE_PIN\": \"AJ30\"\n\t},\n\t\"LA27_N\": {\n\t    \"IOSTANDARD\": \"LVCMOS25\",\n\t    \"PACKAGE_PIN\": \"AJ29\"\n\t},\n\t\"LA27_P\": {\n\t    \"IOSTANDARD\": \"LVCMOS25\",\n\t    \"PACKAGE_PIN\": \"AJ28\"\n\t},\n\t\"LA28_N\": {\n\t    \"IOSTANDARD\": \"LVCMOS25\",\n\t    \"PACKAGE_PIN\": \"AE26\"\n\t},\n\t\"LA28_P\": {\n\t    \"IOSTANDARD\": \"LVCMOS25\",\n\t    \"PACKAGE_PIN\": \"AD25\"\n\t},\n\t\"LA29_N\": {\n\t    \"IOSTANDARD\": \"LVCMOS25\",\n\t    \"PACKAGE_PIN\": \"AF25\"\n\t},\n\t\"LA29_P\": {\n\t    \"IOSTANDARD\": \"LVCMOS25\",\n\t    \"PACKAGE_PIN\": \"AE25\"\n\t},\n\t\"LA30_N\": {\n\t    \"IOSTANDARD\": \"LVCMOS25\",\n\t    \"PACKAGE_PIN\": \"AB30\"\n\t},\n\t\"LA30_P\": {\n\t    \"IOSTANDARD\": \"LVCMOS25\",\n\t    \"PACKAGE_PIN\": \"AB29\"\n\t},\n\t\"LA31_N\": {\n\t    \"IOSTANDARD\": \"LVCMOS25\",\n\t    \"PACKAGE_PIN\": \"AD29\"\n\t},\n\t\"LA31_P\": {\n\t    \"IOSTANDARD\": \"LVCMOS25\",\n\t    \"PACKAGE_PIN\": \"AC29\"\n\t},\n\t\"LA32_N\": {\n\t    \"IOSTANDARD\": \"LVCMOS25\",\n\t    \"PACKAGE_PIN\": \"Y27\"\n\t},\n\t\"LA32_P\": {\n\t    \"IOSTANDARD\": \"LVCMOS25\",\n\t    \"PACKAGE_PIN\": \"Y26\"\n\t},\n\t\"LA33_N\": {\n\t    \"IOSTANDARD\": \"LVCMOS25\",\n\t    \"PACKAGE_PIN\": \"AA30\"\n\t},\n\t\"LA33_P\": {\n\t    \"IOSTANDARD\": \"LVCMOS25\",\n\t    \"PACKAGE_PIN\": \"Y30\"\n\t},\n\t\"DP0_C2M_N\": {\n\t    \"PACKAGE_PIN\": \"AB1\"\n\t},\n\t\"DP0_C2M_P\": {\n\t    \"PACKAGE_PIN\": \"AB2\"\n\t},\n\t\"DP0_M2C_N\": {\n\t    \"PACKAGE_PIN\": \"AC3\"\n\t},\n\t\"DP0_M2C_P\": {\n\t    \"PACKAGE_PIN\": \"AC4\"\n\t},\n\t\"GBTCLK0_M2C_C_N\": {\n\t    \"PACKAGE_PIN\": \"U7\"\n\t},\n\t\"GBTCLK0_M2C_C_P\": {\n\t    \"PACKAGE_PIN\": \"U8\"\n\t}\n    },\n    \"hpcfmc\": {\n\t\"CLK0_M2C_N\": {\n\t    \"IOSTANDARD\": \"LVCMOS25\",\n\t    \"PACKAGE_PIN\": \"AF22\"\n\t},\n\t\"CLK0_M2C_P\": {\n\t    \"IOSTANDARD\": \"LVCMOS25\",\n\t    \"PACKAGE_PIN\": \"AE22\"\n\t},\n\t\"CLK1_M2C_N\": {\n\t    \"IOSTANDARD\": \"LVCMOS25\",\n\t    \"PACKAGE_PIN\": \"U27\"\n\t},\n\t\"CLK1_M2C_P\": {\n\t    \"IOSTANDARD\": \"LVCMOS25\",\n\t    \"PACKAGE_PIN\": \"U26\"\n\t},\n\t\"LA00_CC_N\": {\n\t    \"IOSTANDARD\": \"LVCMOS25\",\n\t    \"PACKAGE_PIN\": \"AG20\"\n\t},\n\t\"LA00_CC_P\": {\n\t    \"IOSTANDARD\": \"LVCMOS25\",\n\t    \"PACKAGE_PIN\": \"AF20\"\n\t},\n\t\"LA01_CC_N\": {\n\t    \"IOSTANDARD\": \"LVCMOS25\",\n\t    \"PACKAGE_PIN\": \"AH21\"\n\t},\n\t\"LA01_CC_P\": {\n\t    \"IOSTANDARD\": \"LVCMOS25\",\n\t    \"PACKAGE_PIN\": \"AG21\"\n\t},\n\t\"LA02_N\": {\n\t    \"IOSTANDARD\": \"LVCMOS25\",\n\t    \"PACKAGE_PIN\": \"AK18\"\n\t},\n\t\"LA02_P\": {\n\t    \"IOSTANDARD\": \"LVCMOS25\",\n\t    \"PACKAGE_PIN\": \"AK17\"\n\t},\n\t\"LA03_N\": {\n\t    \"IOSTANDARD\": \"LVCMOS25\",\n\t    \"PACKAGE_PIN\": \"AJ19\"\n\t},\n\t\"LA03_P\": {\n\t    \"IOSTANDARD\": \"LVCMOS25\",\n\t    \"PACKAGE_PIN\": \"AH19\"\n\t},\n\t\"LA04_N\": {\n\t    \"IOSTANDARD\": \"LVCMOS25\",\n\t    \"PACKAGE_PIN\": \"AK20\"\n\t},\n\t\"LA04_P\": {\n\t    \"IOSTANDARD\": \"LVCMOS25\",\n\t    \"PACKAGE_PIN\": \"AJ20\"\n\t},\n\t\"LA05_N\": {\n\t    \"IOSTANDARD\": \"LVCMOS25\",\n\t    \"PACKAGE_PIN\": \"AH24\"\n\t},\n\t\"LA05_P\": {\n\t    \"IOSTANDARD\": \"LVCMOS25\",\n\t    \"PACKAGE_PIN\": \"AH23\"\n\t},\n\t\"LA06_N\": {\n\t    \"IOSTANDARD\": \"LVCMOS25\",\n\t    \"PACKAGE_PIN\": \"AH22\"\n\t},\n\t\"LA06_P\": {\n\t    \"IOSTANDARD\": \"LVCMOS25\",\n\t    \"PACKAGE_PIN\": \"AG22\"\n\t},\n\t\"LA07_N\": {\n\t    \"IOSTANDARD\": \"LVCMOS25\",\n\t    \"PACKAGE_PIN\": \"AJ24\"\n\t},\n\t\"LA07_P\": {\n\t    \"IOSTANDARD\": \"LVCMOS25\",\n\t    \"PACKAGE_PIN\": \"AJ23\"\n\t},\n\t\"LA08_N\": {\n\t    \"IOSTANDARD\": \"LVCMOS25\",\n\t    \"PACKAGE_PIN\": \"AG19\"\n\t},\n\t\"LA08_P\": {\n\t    \"IOSTANDARD\": \"LVCMOS25\",\n\t    \"PACKAGE_PIN\": \"AF19\"\n\t},\n\t\"LA09_N\": {\n\t    \"IOSTANDARD\": \"LVCMOS25\",\n\t    \"PACKAGE_PIN\": \"AE21\"\n\t},\n\t\"LA09_P\": {\n\t    \"IOSTANDARD\": \"LVCMOS25\",\n\t    \"PACKAGE_PIN\": \"AD21\"\n\t},\n\t\"LA10_N\": {\n\t    \"IOSTANDARD\": \"LVCMOS25\",\n\t    \"PACKAGE_PIN\": \"AG25\"\n\t},\n\t\"LA10_P\": {\n\t    \"IOSTANDARD\": \"LVCMOS25\",\n\t    \"PACKAGE_PIN\": \"AG24\"\n\t},\n\t\"LA11_N\": {\n\t    \"IOSTANDARD\": \"LVCMOS25\",\n\t    \"PACKAGE_PIN\": \"AE23\"\n\t},\n\t\"LA11_P\": {\n\t    \"IOSTANDARD\": \"LVCMOS25\",\n\t    \"PACKAGE_PIN\": \"AD23\"\n\t},\n\t\"LA12_N\": {\n\t    \"IOSTANDARD\": \"LVCMOS25\",\n\t    \"PACKAGE_PIN\": \"AF24\"\n\t},\n\t\"LA12_P\": {\n\t    \"IOSTANDARD\": \"LVCMOS25\",\n\t    \"PACKAGE_PIN\": \"AF23\"\n\t},\n\t\"LA13_N\": {\n\t    \"IOSTANDARD\": \"LVCMOS25\",\n\t    \"PACKAGE_PIN\": \"AA23\"\n\t},\n\t\"LA13_P\": {\n\t    \"IOSTANDARD\": \"LVCMOS25\",\n\t    \"PACKAGE_PIN\": \"AA22\"\n\t},\n\t\"LA14_N\": {\n\t    \"IOSTANDARD\": \"LVCMOS25\",\n\t    \"PACKAGE_PIN\": \"AD24\"\n\t},\n\t\"LA14_P\": {\n\t    \"IOSTANDARD\": \"LVCMOS25\",\n\t    \"PACKAGE_PIN\": \"AC24\"\n\t},\n\t\"LA15_N\": {\n\t    \"IOSTANDARD\": \"LVCMOS25\",\n\t    \"PACKAGE_PIN\": \"Y23\"\n\t},\n\t\"LA15_P\": {\n\t    \"IOSTANDARD\": \"LVCMOS25\",\n\t    \"PACKAGE_PIN\": \"Y22\"\n\t},\n\t\"LA16_N\": {\n\t    \"IOSTANDARD\": \"LVCMOS25\",\n\t    \"PACKAGE_PIN\": \"AB24\"\n\t},\n\t\"LA16_P\": {\n\t    \"IOSTANDARD\": \"LVCMOS25\",\n\t    \"PACKAGE_PIN\": \"AA24\"\n\t},\n\t\"LA17_CC_N\": {\n\t    \"IOSTANDARD\": \"LVCMOS25\",\n\t    \"PACKAGE_PIN\": \"W24\"\n\t},\n\t\"LA17_CC_P\": {\n\t    \"IOSTANDARD\": \"LVCMOS25\",\n\t    \"PACKAGE_PIN\": \"V23\"\n\t},\n\t\"LA18_CC_N\": {\n\t    \"IOSTANDARD\": \"LVCMOS25\",\n\t    \"PACKAGE_PIN\": \"W26\"\n\t},\n\t\"LA18_CC_P\": {\n\t    \"IOSTANDARD\": \"LVCMOS25\",\n\t    \"PACKAGE_PIN\": \"W25\"\n\t},\n\t\"LA19_N\": {\n\t    \"IOSTANDARD\": \"LVCMOS25\",\n\t    \"PACKAGE_PIN\": \"T25\"\n\t},\n\t\"LA19_P\": {\n\t    \"IOSTANDARD\": \"LVCMOS25\",\n\t    \"PACKAGE_PIN\": \"T24\"\n\t},\n\t\"LA20_N\": {\n\t    \"IOSTANDARD\": \"LVCMOS25\",\n\t    \"PACKAGE_PIN\": \"V26\"\n\t},\n\t\"LA20_P\": {\n\t    \"IOSTANDARD\": \"LVCMOS25\",\n\t    \"PACKAGE_PIN\": \"U25\"\n\t},\n\t\"LA21_N\": {\n\t    \"IOSTANDARD\": \"LVCMOS25\",\n\t    \"PACKAGE_PIN\": \"W30\"\n\t},\n\t\"LA21_P\": {\n\t    \"IOSTANDARD\": \"LVCMOS25\",\n\t    \"PACKAGE_PIN\": \"W29\"\n\t},\n\t\"LA22_N\": {\n\t    \"IOSTANDARD\": \"LVCMOS25\",\n\t    \"PACKAGE_PIN\": \"W28\"\n\t},\n\t\"LA22_P\": {\n\t    \"IOSTANDARD\": \"LVCMOS25\",\n\t    \"PACKAGE_PIN\": \"V27\"\n\t},\n\t\"LA23_N\": {\n\t    \"IOSTANDARD\": \"LVCMOS25\",\n\t    \"PACKAGE_PIN\": \"P26\"\n\t},\n\t\"LA23_P\": {\n\t    \"IOSTANDARD\": \"LVCMOS25\",\n\t    \"PACKAGE_PIN\": \"P25\"\n\t},\n\t\"LA24_N\": {\n\t    \"IOSTANDARD\": \"LVCMOS25\",\n\t    \"PACKAGE_PIN\": \"U30\"\n\t},\n\t\"LA24_P\": {\n\t    \"IOSTANDARD\": \"LVCMOS25\",\n\t    \"PACKAGE_PIN\": \"T30\"\n\t},\n\t\"LA25_N\": {\n\t    \"IOSTANDARD\": \"LVCMOS25\",\n\t    \"PACKAGE_PIN\": \"U29\"\n\t},\n\t\"LA25_P\": {\n\t    \"IOSTANDARD\": \"LVCMOS25\",\n\t    \"PACKAGE_PIN\": \"T29\"\n\t},\n\t\"LA26_N\": {\n\t    \"IOSTANDARD\": \"LVCMOS25\",\n\t    \"PACKAGE_PIN\": \"T28\"\n\t},\n\t\"LA26_P\": {\n\t    \"IOSTANDARD\": \"LVCMOS25\",\n\t    \"PACKAGE_PIN\": \"R28\"\n\t},\n\t\"LA27_N\": {\n\t    \"IOSTANDARD\": \"LVCMOS25\",\n\t    \"PACKAGE_PIN\": \"V29\"\n\t},\n\t\"LA27_P\": {\n\t    \"IOSTANDARD\": \"LVCMOS25\",\n\t    \"PACKAGE_PIN\": \"V28\"\n\t},\n\t\"LA28_N\": {\n\t    \"IOSTANDARD\": \"LVCMOS25\",\n\t    \"PACKAGE_PIN\": \"R30\"\n\t},\n\t\"LA28_P\": {\n\t    \"IOSTANDARD\": \"LVCMOS25\",\n\t    \"PACKAGE_PIN\": \"P30\"\n\t},\n\t\"LA29_N\": {\n\t    \"IOSTANDARD\": \"LVCMOS25\",\n\t    \"PACKAGE_PIN\": \"R26\"\n\t},\n\t\"LA29_P\": {\n\t    \"IOSTANDARD\": \"LVCMOS25\",\n\t    \"PACKAGE_PIN\": \"R25\"\n\t},\n\t\"LA30_N\": {\n\t    \"IOSTANDARD\": \"LVCMOS25\",\n\t    \"PACKAGE_PIN\": \"P24\"\n\t},\n\t\"LA30_P\": {\n\t    \"IOSTANDARD\": \"LVCMOS25\",\n\t    \"PACKAGE_PIN\": \"P23\"\n\t},\n\t\"LA31_N\": {\n\t    \"IOSTANDARD\": \"LVCMOS25\",\n\t    \"PACKAGE_PIN\": \"P29\"\n\t},\n\t\"LA31_P\": {\n\t    \"IOSTANDARD\": \"LVCMOS25\",\n\t    \"PACKAGE_PIN\": \"N29\"\n\t},\n\t\"LA32_N\": {\n\t    \"IOSTANDARD\": \"LVCMOS25\",\n\t    \"PACKAGE_PIN\": \"R21\"\n\t},\n\t\"LA32_P\": {\n\t    \"IOSTANDARD\": \"LVCMOS25\",\n\t    \"PACKAGE_PIN\": \"P21\"\n\t},\n\t\"LA33_N\": {\n\t    \"IOSTANDARD\": \"LVCMOS25\",\n\t    \"PACKAGE_PIN\": \"N27\"\n\t},\n\t\"LA33_P\": {\n\t    \"IOSTANDARD\": \"LVCMOS25\",\n\t    \"PACKAGE_PIN\": \"N26\"\n\t},\n\t\"DP0_C2M_N\": {\n\t    \"PACKAGE_PIN\": \"AK9\"\n\t},\n\t\"DP0_C2M_P\": {\n\t    \"PACKAGE_PIN\": \"AK10\"\n\t},\n\t\"DP0_M2C_N\": {\n\t    \"PACKAGE_PIN\": \"AH9\"\n\t},\n\t\"DP0_M2C_P\": {\n\t    \"PACKAGE_PIN\": \"AH10\"\n\t},\n\t\"DP1_C2M_N\": {\n\t    \"PACKAGE_PIN\": \"AK5\"\n\t},\n\t\"DP1_C2M_P\": {\n\t    \"PACKAGE_PIN\": \"AK6\"\n\t},\n\t\"DP1_M2C_N\": {\n\t    \"PACKAGE_PIN\": \"AJ7\"\n\t},\n\t\"DP1_M2C_P\": {\n\t    \"PACKAGE_PIN\": \"AJ8\"\n\t},\n\t\"DP2_C2M_N\": {\n\t    \"PACKAGE_PIN\": \"AJ3\"\n\t},\n\t\"DP2_C2M_P\": {\n\t    \"PACKAGE_PIN\": \"AJ4\"\n\t},\n\t\"DP2_M2C_N\": {\n\t    \"PACKAGE_PIN\": \"AG7\"\n\t},\n\t\"DP2_M2C_P\": {\n\t    \"PACKAGE_PIN\": \"AG8\"\n\t},\n\t\"DP3_C2M_N\": {\n\t    \"PACKAGE_PIN\": \"AK1\"\n\t},\n\t\"DP3_C2M_P\": {\n\t    \"PACKAGE_PIN\": \"AK2\"\n\t},\n\t\"DP3_M2C_N\": {\n\t    \"PACKAGE_PIN\": \"AE7\"\n\t},\n\t\"DP3_M2C_P\": {\n\t    \"PACKAGE_PIN\": \"AE8\"\n\t},\n\t\"DP4_C2M_N\": {\n\t    \"PACKAGE_PIN\": \"AH1\"\n\t},\n\t\"DP4_C2M_P\": {\n\t    \"PACKAGE_PIN\": \"AH2\"\n\t},\n\t\"DP4_M2C_N\": {\n\t    \"PACKAGE_PIN\": \"AH5\"\n\t},\n\t\"DP4_M2C_P\": {\n\t    \"PACKAGE_PIN\": \"AH6\"\n\t},\n\t\"DP5_C2M_N\": {\n\t    \"PACKAGE_PIN\": \"AF1\"\n\t},\n\t\"DP5_C2M_P\": {\n\t    \"PACKAGE_PIN\": \"AF2\"\n\t},\n\t\"DP5_M2C_N\": {\n\t    \"PACKAGE_PIN\": \"AG3\"\n\t},\n\t\"DP5_M2C_P\": {\n\t    \"PACKAGE_PIN\": \"AG4\"\n\t},\n\t\"DP6_C2M_N\": {\n\t    \"PACKAGE_PIN\": \"AE3\"\n\t},\n\t\"DP6_C2M_P\": {\n\t    \"PACKAGE_PIN\": \"AE4\"\n\t},\n\t\"DP6_M2C_N\": {\n\t    \"PACKAGE_PIN\": \"AF5\"\n\t},\n\t\"DP6_M2C_P\": {\n\t    \"PACKAGE_PIN\": \"AF6\"\n\t},\n\t\"DP7_C2M_N\": {\n\t    \"PACKAGE_PIN\": \"AD1\"\n\t},\n\t\"DP7_C2M_P\": {\n\t    \"PACKAGE_PIN\": \"AD2\"\n\t},\n\t\"DP7_M2C_N\": {\n\t    \"PACKAGE_PIN\": \"AD5\"\n\t},\n\t\"DP7_M2C_P\": {\n\t    \"PACKAGE_PIN\": \"AD6\"\n\t},\n\t\"GBTCLK0_M2C_C_N\": {\n\t    \"PACKAGE_PIN\": \"AD9\"\n\t},\n\t\"GBTCLK0_M2C_C_P\": {\n\t    \"PACKAGE_PIN\": \"AD10\"\n\t},\n\t\"GBTCLK1_M2C_C_N\": {\n\t    \"PACKAGE_PIN\": \"AA7\"\n\t},\n\t\"GBTCLK1_M2C_C_P\": {\n\t    \"PACKAGE_PIN\": \"AA8\"\n\t}\n    },\n    \"pins\": {\n\t\"GPIO_LEDS[0]\": {\n\t    \"PACKAGE_PIN\": \"A17\",\n\t    \"IOSTANDARD\": \"LVCMOS15\",\n\t    \"slew\": \"SLOW\",\n\t    \"PIO_DIRECTION\": \"OUTPUT\"\n\t},\n\t\"GPIO_LEDS[1]\": {\n\t    \"PACKAGE_PIN\": \"W21\",\n\t    \"IOSTANDARD\": \"LVCMOS25\",\n\t    \"slew\": \"SLOW\",\n\t    \"PIO_DIRECTION\": \"OUTPUT\"\n\t},\n\t\"GPIO_LEDS[2]\": {\n\t    \"PACKAGE_PIN\": \"G2\",\n\t    \"IOSTANDARD\": \"LVCMOS15\",\n\t    \"slew\": \"SLOW\",\n\t    \"PIO_DIRECTION\": \"OUTPUT\"\n\t},\n\t\"GPIO_LEDS[3]\": {\n\t    \"PACKAGE_PIN\": \"Y21\",\n\t    \"IOSTANDARD\": \"LVCMOS25\",\n\t    \"slew\": \"SLOW\",\n\t    \"PIO_DIRECTION\": \"OUTPUT\"\n\t},\n\t\"GPIO_sw_left\": {\n\t    \"PACKAGE_PIN\": \"AK25\",\n\t    \"IOSTANDARD\": \"LVCMOS18\",\n\t    \"slew\": \"SLOW\",\n\t    \"PIO_DIRECTION\": \"INPUT\"\n\t},\n\t\"GPIO_sw_center\": {\n\t    \"PACKAGE_PIN\": \"K15\",\n\t    \"IOSTANDARD\": \"LVCMOS18\",\n\t    \"slew\": \"SLOW\",\n\t    \"PIO_DIRECTION\": \"INPUT\"\n\t},\n\t\"GPIO_sw_right\": {\n\t    \"PACKAGE_PIN\": \"R27\",\n\t    \"IOSTANDARD\": \"LVCMOS18\",\n\t    \"slew\": \"SLOW\",\n\t    \"PIO_DIRECTION\": \"INPUT\"\n\t},\n\t\"pl_cpu_reset\": {\n\t    \"PACKAGE_PIN\": \"A8\",\n\t    \"IOSTANDARD\": \"LVCMOS15\",\n\t    \"slew\": \"SLOW\",\n\t    \"PIO_DIRECTION\": \"INPUT\"\n\t},\n\n\t\"userClk_p\": {\n\t    \"PACKAGE_PIN\": \"AF14\",\n\t    \"IOSTANDARD\": \"LVDS_25\",\n\t    \"DIFF_TERM\": \"TRUE\",\n\t    \"PIO_DIRECTION\": \"INPUT\"\n\t},\n\t\"userClk_n\": {\n\t    \"PACKAGE_PIN\": \"AG14\",\n\t    \"IOSTANDARD\": \"LVDS_25\",\n\t    \"DIFF_TERM\": \"TRUE\",\n\t    \"PIO_DIRECTION\": \"INPUT\"\n\t},\n\t\"smaUserClk_p\": {\n\t    \"PACKAGE_PIN\": \"AD18\",\n\t    \"IOSTANDARD\": \"LVDS_25\",\n\t    \"DIFF_TERM\": \"TRUE\",\n\t    \"PIO_DIRECTION\": \"OUTPUT\"\n\t},\n\t\"smaUserClk_n\": {\n\t    \"PACKAGE_PIN\": \"AD19\",\n\t    \"IOSTANDARD\": \"LVDS_25\",\n\t    \"DIFF_TERM\": \"TRUE\",\n\t    \"PIO_DIRECTION\": \"OUTPUT\"\n\t},\n\t\"mgtRefClk_p\": {\n\t    \"PACKAGE_PIN\": \"W8\",\n\t    \"IOSTANDARD\": \"LVDS_25\",\n\t    \"DIFF_TERM\": \"TRUE\",\n\t    \"PIO_DIRECTION\": \"INPUT\"\n\t},\n\t\"mgtRefClk_n\": {\n\t    \"PACKAGE_PIN\": \"W7\",\n\t    \"IOSTANDARD\": \"LVDS_25\",\n\t    \"DIFF_TERM\": \"TRUE\",\n\t    \"PIO_DIRECTION\": \"INPUT\"\n\t},\n\t\"mgtRx_p\": {\n\t    \"PACKAGE_PIN\": \"AB6\",\n\t    \"DIFF_TERM\": \"TRUE\",\n\t    \"PIO_DIRECTION\": \"INPUT\"\n\t},\n\t\"mgtRx_n\": {\n\t    \"PACKAGE_PIN\": \"AB5\",\n\t    \"DIFF_TERM\": \"TRUE\",\n\t    \"PIO_DIRECTION\": \"INPUT\"\n\t},\n\t\"mgtTx_p\": {\n\t    \"PACKAGE_PIN\": \"Y2\",\n\t    \"DIFF_TERM\": \"TRUE\",\n\t    \"PIO_DIRECTION\": \"OUTPUT\"\n\t},\n\t\"mgtTx_n\": {\n\t    \"PACKAGE_PIN\": \"Y1\",\n\t    \"DIFF_TERM\": \"TRUE\",\n\t    \"PIO_DIRECTION\": \"OUTPUT\"\n\t}\n    },\n    \"pcie\": {\n\t\"PCIE_clk_q0_p\": {\n\t    \"PACKAGE_PIN\": \"N8\",\n\t    \"DIFF_TERM\": \"TRUE\",\n\t    \"IOSTANDARD\": \"LVDS_25\",\n\t    \"PIO_DIRECTION\": \"INPUT\"\n\t},\n\t\"PCIE_clk_q0_n\": {\n\t    \"PACKAGE_PIN\": \"N7\",\n\t    \"DIFF_TERM\": \"TRUE\",\n\t    \"IOSTANDARD\": \"LVDS_25\",\n\t    \"PIO_DIRECTION\": \"INPUT\"\n\t},\n\t\"PCIE_tx0_p\": {\n\t    \"PACKAGE_PIN\": \"N4\",\n\t    \"DIFF_TERM\": \"TRUE\",\n\t    \"IOSTANDARD\": \"LVDS_25\",\n\t    \"PIO_DIRECTION\": \"OUTPUT\"\n\t},\n\t\"PCIE_tx0_n\": {\n\t    \"PACKAGE_PIN\": \"N3\",\n\t    \"DIFF_TERM\": \"TRUE\",\n\t    \"IOSTANDARD\": \"LVDS_25\",\n\t    \"PIO_DIRECTION\": \"OUTPUT\"\n\t},\n\t\"PCIE_tx1_p\": {\n\t    \"PACKAGE_PIN\": \"P2\",\n\t    \"DIFF_TERM\": \"TRUE\",\n\t    \"IOSTANDARD\": \"LVDS_25\",\n\t    \"PIO_DIRECTION\": \"OUTPUT\"\n\t},\n\t\"PCIE_tx1_n\": {\n\t    \"PACKAGE_PIN\": \"P1\",\n\t    \"DIFF_TERM\": \"TRUE\",\n\t    \"IOSTANDARD\": \"LVDS_25\",\n\t    \"PIO_DIRECTION\": \"OUTPUT\"\n\t},\n\t\"PCIE_tx2_p\": {\n\t    \"PACKAGE_PIN\": \"R4\",\n\t    \"DIFF_TERM\": \"TRUE\",\n\t    \"IOSTANDARD\": \"LVDS_25\",\n\t    \"PIO_DIRECTION\": \"OUTPUT\"\n\t},\n\t\"PCIE_tx2_n\": {\n\t    \"PACKAGE_PIN\": \"R3\",\n\t    \"DIFF_TERM\": \"TRUE\",\n\t    \"IOSTANDARD\": \"LVDS_25\",\n\t    \"PIO_DIRECTION\": \"OUTPUT\"\n\t},\n\t\"PCIE_tx3_p\": {\n\t    \"PACKAGE_PIN\": \"T2\",\n\t    \"DIFF_TERM\": \"TRUE\",\n\t    \"IOSTANDARD\": \"LVDS_25\",\n\t    \"PIO_DIRECTION\": \"OUTPUT\"\n\t},\n\t\"PCIE_tx3_n\": {\n\t    \"PACKAGE_PIN\": \"T1\",\n\t    \"DIFF_TERM\": \"TRUE\",\n\t    \"IOSTANDARD\": \"LVDS_25\",\n\t    \"PIO_DIRECTION\": \"OUTPUT\"\n\t},\n\t\"PCIE_rx0_p\": {\n\t    \"PACKAGE_PIN\": \"P6\",\n\t    \"DIFF_TERM\": \"TRUE\",\n\t    \"IOSTANDARD\": \"LVDS_25\",\n\t    \"PIO_DIRECTION\": \"INPUT\"\n\t},\n\t\"PCIE_rx0_n\": {\n\t    \"PACKAGE_PIN\": \"P5\",\n\t    \"DIFF_TERM\": \"TRUE\",\n\t    \"IOSTANDARD\": \"LVDS_25\",\n\t    \"PIO_DIRECTION\": \"INPUT\"\n\t},\n\t\"PCIE_rx1_p\": {\n\t    \"PACKAGE_PIN\": \"T6\",\n\t    \"DIFF_TERM\": \"TRUE\",\n\t    \"IOSTANDARD\": \"LVDS_25\",\n\t    \"PIO_DIRECTION\": \"INPUT\"\n\t},\n\t\"PCIE_rx1_n\": {\n\t    \"PACKAGE_PIN\": \"T5\",\n\t    \"DIFF_TERM\": \"TRUE\",\n\t    \"IOSTANDARD\": \"LVDS_25\",\n\t    \"PIO_DIRECTION\": \"INPUT\"\n\t},\n\t\"PCIE_rx2_p\": {\n\t    \"PACKAGE_PIN\": \"U4\",\n\t    \"DIFF_TERM\": \"TRUE\",\n\t    \"IOSTANDARD\": \"LVDS_25\",\n\t    \"PIO_DIRECTION\": \"INPUT\"\n\t},\n\t\"PCIE_rx2_n\": {\n\t    \"PACKAGE_PIN\": \"U3\",\n\t    \"DIFF_TERM\": \"TRUE\",\n\t    \"IOSTANDARD\": \"LVDS_25\",\n\t    \"PIO_DIRECTION\": \"INPUT\"\n\t},\n\t\"PCIE_rx3_p\": {\n\t    \"PACKAGE_PIN\": \"V6\",\n\t    \"DIFF_TERM\": \"TRUE\",\n\t    \"IOSTANDARD\": \"LVDS_25\",\n\t    \"PIO_DIRECTION\": \"INPUT\"\n\t},\n\t\"PCIE_rx3_n\": {\n\t    \"PACKAGE_PIN\": \"V5\",\n\t    \"DIFF_TERM\": \"TRUE\",\n\t    \"IOSTANDARD\": \"LVDS_25\",\n\t    \"PIO_DIRECTION\": \"INPUT\"\n\t},\n\t\"PCIE_perst\": {\n\t    \"PACKAGE_PIN\": \"AK23\",\n\t    \"IOSTANDARD\": \"LVCMOS18\",\n\t    \"PIO_DIRECTION\": \"INPUT\"\n\t},\n\t\"PCIE_wake_b\": {\n\t    \"PACKAGE_PIN\": \"AK22\",\n\t    \"IOSTANDARD\": \"LVCMOS18\",\n\t    \"PIO_DIRECTION\": \"INPUT\"\n\t}\n    }\n}\n"
  },
  {
    "path": "boardinfo/zc706_ubuntu.json",
    "content": "{\n    \"options\": {\n        \"os\" : \"ubuntu\",\n\t\"arch\" : \"arm\",\n\t\"toolchain\" : \"arm-linux-gnueabihf-\",\n        \"partname\" : \"xc7z045ffg900-2\",\n        \"rewireclockstring\" : \"tclzynqrewireclock\",\n        \"constraints\": [\"constraints/xilinx/xc7z045ffg900.xdc\", \"constraints/xilinx/zc706.xdc\"],\n        \"implconstraints\": [\"constraints/xilinx/xc7z045ffg900.xdc\", \"constraints/xilinx/zc706.xdc\"],\n        \"TOP\" : \"ZynqTop\",\n        \"runscript\" : \"run.ubuntu\",\n        \"bsvdefines\" : [\"XILINX=1\", \"ZYNQ\", \"ZynqHostInterface\", \"PhysAddrWidth=32\", \"NUMBER_OF_LEDS=4\", \"PcieLanes=4\",\n\t\t\t\"CONNECTAL_BITS_DEPENDENCES=hw/mkTop.bit\", \"CONNECTAL_RUN_SCRIPT=$(CONNECTALDIR)/scripts/run.ubuntu\",\n\t\t\t\"CONNECTAL_EXENAME=ubuntu.exe\", \"CONNECTAL_EXENAME2=ubuntu.exe2\"],\n        \"CONNECTALFLAGS\": [\"--mainclockperiod=5\", \"--derivedclockperiod=2.5\"],\n        \"need_pcie\" : \"unused\"\n    },\n    \"sfp1\": {\n        \"mod_def0\": {\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"LOC\": \"AB20\"\n        },\n        \"mod_def1\": {\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"LOC\": \"AB19\"\n        },\n        \"mod_def2\": {\n            \"IOSTANDARD\": \"LVCMOS15\",\n            \"LOC\": \"AA19\"\n        },\n        \"rx_los\": {\n            \"PIO_DIRECTION\": \"INPUT\",\n            \"IOSTANDARD\": \"LVCMOS25\",\n            \"LOC\": \"AE20\"\n        },\n        \"tx_disable\": {\n            \"PIO_DIRECTION\": \"OUTPUT\",\n            \"IOSTANDARD\": \"LVCMOS25\",\n            \"LOC\": \"AA18\"\n        },\n        \"tx_fault\": {\n            \"PIO_DIRECTION\": \"INPUT\",\n            \"IOSTANDARD\": \"LVCMOS25\",\n            \"LOC\": \"AD19\"\n        },\n        \"rxp\": {\n            \"PIO_DIRECTION\": \"INPUT\",\n            \"LOC\": \"AC4\"\n        },\n        \"rxn\": {\n            \"PIO_DIRECTION\": \"INPUT\",\n            \"LOC\": \"AC3\"\n        },\n        \"txp\": {\n            \"PIO_DIRECTION\": \"OUTPUT\",\n            \"LOC\": \"AB2\"\n        },\n        \"txn\": {\n            \"PIO_DIRECTION\": \"OUTPUT\",\n            \"LOC\": \"AB1\"\n        }\n    },\n    \"fmc1\": {\n    \"LA00_p_CC\": {\n        \"PACKAGE_PIN\": \"\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA00_n_CC\": {\n        \"PACKAGE_PIN\": \"\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA01_p_CC\": {\n        \"PACKAGE_PIN\": \"\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA01_n_CC\": {\n        \"PACKAGE_PIN\": \"\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA02_p\": {\n        \"PACKAGE_PIN\": \"\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA02_n\": {\n        \"PACKAGE_PIN\": \"\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA03_p\": {\n        \"PACKAGE_PIN\": \"\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA03_n\": {\n        \"PACKAGE_PIN\": \"\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA04_p\": {\n        \"PACKAGE_PIN\": \"\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA04_n\": {\n        \"PACKAGE_PIN\": \"\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA05_p\": {\n        \"PACKAGE_PIN\": \"\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA05_n\": {\n        \"PACKAGE_PIN\": \"\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA06_p\": {\n        \"PACKAGE_PIN\": \"\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA06_n\": {\n        \"PACKAGE_PIN\": \"\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA07_p\": {\n        \"PACKAGE_PIN\": \"\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA07_n\": {\n        \"PACKAGE_PIN\": \"\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA08_p\": {\n        \"PACKAGE_PIN\": \"\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA08_n\": {\n        \"PACKAGE_PIN\": \"\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA09_p\": {\n        \"PACKAGE_PIN\": \"\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA09_n\": {\n        \"PACKAGE_PIN\": \"\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA10_p\": {\n        \"PACKAGE_PIN\": \"\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA10_n\": {\n        \"PACKAGE_PIN\": \"\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA11_p\": {\n        \"PACKAGE_PIN\": \"\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA11_n\": {\n        \"PACKAGE_PIN\": \"\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA12_p\": {\n        \"PACKAGE_PIN\": \"\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA12_n\": {\n        \"PACKAGE_PIN\": \"\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA13_p\": {\n        \"PACKAGE_PIN\": \"\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA13_n\": {\n        \"PACKAGE_PIN\": \"\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA14_p\": {\n        \"PACKAGE_PIN\": \"\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA14_n\": {\n        \"PACKAGE_PIN\": \"\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA15_p\": {\n        \"PACKAGE_PIN\": \"\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA15_n\": {\n        \"PACKAGE_PIN\": \"\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA16_p\": {\n        \"PACKAGE_PIN\": \"\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA16_n\": {\n        \"PACKAGE_PIN\": \"\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA17_p_CC\": {\n        \"PACKAGE_PIN\": \"\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA17_n_CC\": {\n        \"PACKAGE_PIN\": \"\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA18_p_CC\": {\n        \"PACKAGE_PIN\": \"\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA18_n_CC\": {\n        \"PACKAGE_PIN\": \"\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA19_p\": {\n        \"PACKAGE_PIN\": \"\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA19_n\": {\n        \"PACKAGE_PIN\": \"\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        }\n    },\n    \"pins\": {\n\t\"GPIO_leds[0]\": {\n\t    \"PACKAGE_PIN\": \"A17\",\n\t    \"IOSTANDARD\": \"LVCMOS15\",\n\t    \"slew\": \"SLOW\",\n\t    \"PIO_DIRECTION\": \"OUTPUT\"\n\t},\n\t\"GPIO_leds[1]\": {\n\t    \"PACKAGE_PIN\": \"W21\",\n\t    \"IOSTANDARD\": \"LVCMOS25\",\n\t    \"slew\": \"SLOW\",\n\t    \"PIO_DIRECTION\": \"OUTPUT\"\n\t},\n\t\"GPIO_leds[2]\": {\n\t    \"PACKAGE_PIN\": \"G2\",\n\t    \"IOSTANDARD\": \"LVCMOS15\",\n\t    \"slew\": \"SLOW\",\n\t    \"PIO_DIRECTION\": \"OUTPUT\"\n\t},\n\t\"GPIO_leds[3]\": {\n\t    \"PACKAGE_PIN\": \"Y21\",\n\t    \"IOSTANDARD\": \"LVCMOS25\",\n\t    \"slew\": \"SLOW\",\n\t    \"PIO_DIRECTION\": \"OUTPUT\"\n\t},\n\t\"GPIO_sw_left\": {\n\t    \"PACKAGE_PIN\": \"AK25\",\n\t    \"IOSTANDARD\": \"LVCMOS18\",\n\t    \"slew\": \"SLOW\",\n\t    \"PIO_DIRECTION\": \"INPUT\"\n\t},\n\t\"GPIO_sw_center\": {\n\t    \"PACKAGE_PIN\": \"K15\",\n\t    \"IOSTANDARD\": \"LVCMOS18\",\n\t    \"slew\": \"SLOW\",\n\t    \"PIO_DIRECTION\": \"INPUT\"\n\t},\n\t\"GPIO_sw_right\": {\n\t    \"PACKAGE_PIN\": \"R27\",\n\t    \"IOSTANDARD\": \"LVCMOS18\",\n\t    \"slew\": \"SLOW\",\n\t    \"PIO_DIRECTION\": \"INPUT\"\n\t},\n\t\"pl_cpu_reset\": {\n\t    \"PACKAGE_PIN\": \"A8\",\n\t    \"IOSTANDARD\": \"LVCMOS15\",\n\t    \"slew\": \"SLOW\",\n\t    \"PIO_DIRECTION\": \"INPUT\"\n\t},\n\n\t\"userClk_p\": {\n\t    \"PACKAGE_PIN\": \"AF14\",\n\t    \"IOSTANDARD\": \"LVDS_25\",\n\t    \"DIFF_TERM\": \"TRUE\",\n\t    \"PIO_DIRECTION\": \"INPUT\"\n\t},\n\t\"userClk_n\": {\n\t    \"PACKAGE_PIN\": \"AG14\",\n\t    \"IOSTANDARD\": \"LVDS_25\",\n\t    \"DIFF_TERM\": \"TRUE\",\n\t    \"PIO_DIRECTION\": \"INPUT\"\n\t},\n\t\"smaUserClk_p\": {\n\t    \"PACKAGE_PIN\": \"AD18\",\n\t    \"IOSTANDARD\": \"LVDS_25\",\n\t    \"DIFF_TERM\": \"TRUE\",\n\t    \"PIO_DIRECTION\": \"OUTPUT\"\n\t},\n\t\"smaUserClk_n\": {\n\t    \"PACKAGE_PIN\": \"AD19\",\n\t    \"IOSTANDARD\": \"LVDS_25\",\n\t    \"DIFF_TERM\": \"TRUE\",\n\t    \"PIO_DIRECTION\": \"OUTPUT\"\n\t},\n\t\"mgtRefClk_p\": {\n\t    \"PACKAGE_PIN\": \"W8\",\n\t    \"IOSTANDARD\": \"LVDS_25\",\n\t    \"DIFF_TERM\": \"TRUE\",\n\t    \"PIO_DIRECTION\": \"INPUT\"\n\t},\n\t\"mgtRefClk_n\": {\n\t    \"PACKAGE_PIN\": \"W7\",\n\t    \"IOSTANDARD\": \"LVDS_25\",\n\t    \"DIFF_TERM\": \"TRUE\",\n\t    \"PIO_DIRECTION\": \"INPUT\"\n\t},\n\t\"mgtRx_p\": {\n\t    \"PACKAGE_PIN\": \"AB6\",\n\t    \"DIFF_TERM\": \"TRUE\",\n\t    \"PIO_DIRECTION\": \"INPUT\"\n\t},\n\t\"mgtRx_n\": {\n\t    \"PACKAGE_PIN\": \"AB5\",\n\t    \"DIFF_TERM\": \"TRUE\",\n\t    \"PIO_DIRECTION\": \"INPUT\"\n\t},\n\t\"mgtTx_p\": {\n\t    \"PACKAGE_PIN\": \"Y2\",\n\t    \"DIFF_TERM\": \"TRUE\",\n\t    \"PIO_DIRECTION\": \"OUTPUT\"\n\t},\n\t\"mgtTx_n\": {\n\t    \"PACKAGE_PIN\": \"Y1\",\n\t    \"DIFF_TERM\": \"TRUE\",\n\t    \"PIO_DIRECTION\": \"OUTPUT\"\n\t}\n    },\n    \"pcie\": {\n\t\"PCIE_clk_q0_p\": {\n\t    \"PACKAGE_PIN\": \"N8\",\n\t    \"DIFF_TERM\": \"TRUE\",\n\t    \"IOSTANDARD\": \"LVDS_25\",\n\t    \"PIO_DIRECTION\": \"INPUT\"\n\t},\n\t\"PCIE_clk_q0_n\": {\n\t    \"PACKAGE_PIN\": \"N7\",\n\t    \"DIFF_TERM\": \"TRUE\",\n\t    \"IOSTANDARD\": \"LVDS_25\",\n\t    \"PIO_DIRECTION\": \"INPUT\"\n\t},\n\t\"PCIE_tx0_p\": {\n\t    \"PACKAGE_PIN\": \"N4\",\n\t    \"DIFF_TERM\": \"TRUE\",\n\t    \"IOSTANDARD\": \"LVDS_25\",\n\t    \"PIO_DIRECTION\": \"OUTPUT\"\n\t},\n\t\"PCIE_tx0_n\": {\n\t    \"PACKAGE_PIN\": \"N3\",\n\t    \"DIFF_TERM\": \"TRUE\",\n\t    \"IOSTANDARD\": \"LVDS_25\",\n\t    \"PIO_DIRECTION\": \"OUTPUT\"\n\t},\n\t\"PCIE_tx1_p\": {\n\t    \"PACKAGE_PIN\": \"P2\",\n\t    \"DIFF_TERM\": \"TRUE\",\n\t    \"IOSTANDARD\": \"LVDS_25\",\n\t    \"PIO_DIRECTION\": \"OUTPUT\"\n\t},\n\t\"PCIE_tx1_n\": {\n\t    \"PACKAGE_PIN\": \"P1\",\n\t    \"DIFF_TERM\": \"TRUE\",\n\t    \"IOSTANDARD\": \"LVDS_25\",\n\t    \"PIO_DIRECTION\": \"OUTPUT\"\n\t},\n\t\"PCIE_tx2_p\": {\n\t    \"PACKAGE_PIN\": \"R4\",\n\t    \"DIFF_TERM\": \"TRUE\",\n\t    \"IOSTANDARD\": \"LVDS_25\",\n\t    \"PIO_DIRECTION\": \"OUTPUT\"\n\t},\n\t\"PCIE_tx2_n\": {\n\t    \"PACKAGE_PIN\": \"R3\",\n\t    \"DIFF_TERM\": \"TRUE\",\n\t    \"IOSTANDARD\": \"LVDS_25\",\n\t    \"PIO_DIRECTION\": \"OUTPUT\"\n\t},\n\t\"PCIE_tx3_p\": {\n\t    \"PACKAGE_PIN\": \"T2\",\n\t    \"DIFF_TERM\": \"TRUE\",\n\t    \"IOSTANDARD\": \"LVDS_25\",\n\t    \"PIO_DIRECTION\": \"OUTPUT\"\n\t},\n\t\"PCIE_tx3_n\": {\n\t    \"PACKAGE_PIN\": \"T1\",\n\t    \"DIFF_TERM\": \"TRUE\",\n\t    \"IOSTANDARD\": \"LVDS_25\",\n\t    \"PIO_DIRECTION\": \"OUTPUT\"\n\t},\n\t\"PCIE_rx0_p\": {\n\t    \"PACKAGE_PIN\": \"P6\",\n\t    \"DIFF_TERM\": \"TRUE\",\n\t    \"IOSTANDARD\": \"LVDS_25\",\n\t    \"PIO_DIRECTION\": \"INPUT\"\n\t},\n\t\"PCIE_rx0_n\": {\n\t    \"PACKAGE_PIN\": \"P5\",\n\t    \"DIFF_TERM\": \"TRUE\",\n\t    \"IOSTANDARD\": \"LVDS_25\",\n\t    \"PIO_DIRECTION\": \"INPUT\"\n\t},\n\t\"PCIE_rx1_p\": {\n\t    \"PACKAGE_PIN\": \"T6\",\n\t    \"DIFF_TERM\": \"TRUE\",\n\t    \"IOSTANDARD\": \"LVDS_25\",\n\t    \"PIO_DIRECTION\": \"INPUT\"\n\t},\n\t\"PCIE_rx1_n\": {\n\t    \"PACKAGE_PIN\": \"T5\",\n\t    \"DIFF_TERM\": \"TRUE\",\n\t    \"IOSTANDARD\": \"LVDS_25\",\n\t    \"PIO_DIRECTION\": \"INPUT\"\n\t},\n\t\"PCIE_rx2_p\": {\n\t    \"PACKAGE_PIN\": \"U4\",\n\t    \"DIFF_TERM\": \"TRUE\",\n\t    \"IOSTANDARD\": \"LVDS_25\",\n\t    \"PIO_DIRECTION\": \"INPUT\"\n\t},\n\t\"PCIE_rx2_n\": {\n\t    \"PACKAGE_PIN\": \"U3\",\n\t    \"DIFF_TERM\": \"TRUE\",\n\t    \"IOSTANDARD\": \"LVDS_25\",\n\t    \"PIO_DIRECTION\": \"INPUT\"\n\t},\n\t\"PCIE_rx3_p\": {\n\t    \"PACKAGE_PIN\": \"V6\",\n\t    \"DIFF_TERM\": \"TRUE\",\n\t    \"IOSTANDARD\": \"LVDS_25\",\n\t    \"PIO_DIRECTION\": \"INPUT\"\n\t},\n\t\"PCIE_rx3_n\": {\n\t    \"PACKAGE_PIN\": \"V5\",\n\t    \"DIFF_TERM\": \"TRUE\",\n\t    \"IOSTANDARD\": \"LVDS_25\",\n\t    \"PIO_DIRECTION\": \"INPUT\"\n\t},\n\t\"PCIE_perst\": {\n\t    \"PACKAGE_PIN\": \"AK23\",\n\t    \"IOSTANDARD\": \"LVCMOS18\",\n\t    \"PIO_DIRECTION\": \"INPUT\"\n\t},\n\t\"PCIE_wake_b\": {\n\t    \"PACKAGE_PIN\": \"AK22\",\n\t    \"IOSTANDARD\": \"LVCMOS18\",\n\t    \"PIO_DIRECTION\": \"INPUT\"\n\t}\n    }\n}\n"
  },
  {
    "path": "boardinfo/zcu102.json",
    "content": "{\n    \"options\": {\n        \"bsvdefines\" : [\"XILINX=1\", \"ZYNQ\", \"ZynqUltrascale\", \"ZynqHostInterface\", \"PhysAddrWidth=40\",\n\t\t\t\"CONNECTAL_BITS_DEPENDENCES=hw/mkTop.bit\", \"CONNECTAL_RUN_SCRIPT=$(CONNECTALDIR)/scripts/run.pcietest\",\n\t\t\t\"CONNECTAL_EXENAME=ubuntu.exe\", \"CONNECTAL_EXENAME2=ubuntu.exe2\"],\n        \"os\" : \"ubuntu\",\n\t\"arch\" : \"arm64\",\n\t\"toolchain\" : \"aarch64-linux-gnu-\",\n        \"partname\" : \"xczu9eg-ffvb1156-2-i-es2\",\n        \"rewireclockstring\" : \"tclzynqrewireclock\",\n        \"constraints\": [],\n        \"implconstraints\": [\"constraints/xilinx/zcu102.xdc\"],\n        \"TOP\" : \"ZynqUltraTop\",\n        \"runscript\" : \"run.pcietest\",\n        \"CONNECTALFLAGS\" : [\"--mainclockperiod=5\", \"--derivedclockperiod=2.5\"],\n\t\"ZYNQ_MPSOC\": \"zynq_ultra_ps_e\"\n    },\n    \"fmc1\": {\n\t\"LA00_p_CC\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n        },\n\t\"LA00_n_CC\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n        },\n\t\"LA01_p_CC\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n        },\n\t\"LA01_n_CC\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n        },\n\t\"LA02_p\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n        },\n\t\"LA02_n\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n        },\n\t\"LA03_p\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n        },\n\t\"LA03_n\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n        },\n\t\"LA04_p\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n        },\n\t\"LA04_n\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n        },\n\t\"LA05_p\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n        },\n\t\"LA05_n\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n        },\n\t\"LA06_p\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n        },\n\t\"LA06_n\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n        },\n\t\"LA07_p\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n        },\n\t\"LA07_n\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n        },\n\t\"LA08_p\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n        },\n\t\"LA08_n\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n        },\n\t\"LA09_p\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n        },\n\t\"LA09_n\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n        },\n\t\"LA10_p\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n        },\n\t\"LA10_n\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n        },\n\t\"LA11_p\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n        },\n\t\"LA11_n\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n        },\n\t\"LA12_p\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n        },\n\t\"LA12_n\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n        },\n\t\"LA13_p\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n        },\n\t\"LA13_n\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n        },\n\t\"LA14_p\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n        },\n\t\"LA14_n\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n        },\n\t\"LA15_p\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n        },\n\t\"LA15_n\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n        },\n\t\"LA16_p\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n        },\n\t\"LA16_n\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n        },\n\t\"LA17_p_CC\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n        },\n\t\"LA17_n_CC\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n        },\n\t\"LA18_p_CC\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n        },\n\t\"LA18_n_CC\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n        },\n\t\"LA19_p\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n        },\n\t\"LA19_n\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n        },\n\t\"CLK0_M2C_p\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n        },\n\t\"CLK0_M2C_n\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n        }\n    },\n    \"fmc2\": {\n\t\"LA00_p_CC\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n\t},\n\t\"LA00_n_CC\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n\t},\n\t\"LA01_p_CC\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n\t},\n\t\"LA01_n_CC\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n\t},\n\t\"LA02_p\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n\t},\n\t\"LA02_n\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n\t},\n\t\"LA03_p\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n\t},\n\t\"LA03_n\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n\t},\n\t\"LA04_p\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n\t},\n\t\"LA04_n\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n\t},\n\t\"LA05_p\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n\t},\n\t\"LA05_n\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n\t},\n\t\"LA06_p\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n\t},\n\t\"LA06_n\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n\t},\n\t\"LA07_p\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n\t},\n\t\"LA07_n\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n\t},\n\t\"LA08_p\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n\t},\n\t\"LA08_n\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n\t},\n\t\"LA09_p\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n\t},\n\t\"LA09_n\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n\t},\n\t\"LA10_p\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n\t},\n\t\"LA10_n\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n\t},\n\t\"LA11_p\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n\t},\n\t\"LA11_n\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n\t},\n\t\"LA12_p\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n\t},\n\t\"LA12_n\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n\t},\n\t\"LA13_p\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n\t},\n\t\"LA13_n\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n\t},\n\t\"LA14_p\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n\t},\n\t\"LA14_n\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n\t},\n\t\"LA15_p\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n\t},\n\t\"LA15_n\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n\t},\n\t\"LA16_p\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n\t},\n\t\"LA16_n\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n\t},\n\t\"LA17_p_CC\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n\t},\n\t\"LA17_n_CC\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n\t},\n\t\"LA18_p_CC\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n\t},\n\t\"LA18_n_CC\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n\t},\n\t\"LA19_p\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n\t},\n\t\"LA19_n\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n\t},\n\t\"CLK0_M2C_p\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n\t},\n\t\"CLK0_M2C_n\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n\t}\n    },\n    \"leds\" : {\n    \t\"L0\" : {\n\t     \"PACKAGE_PIN\" : \"TBD\",\n             \"IOSTANDARD\" : \"LVCMOS25\",\n\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t     },\n    \t\"L1\" : {\n\t     \"PACKAGE_PIN\" : \"TBD\",\n             \"IOSTANDARD\" : \"LVCMOS25\",\n\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t     },\n    \t\"L2\" : {\n\t     \"PACKAGE_PIN\" : \"TBD\",\n             \"IOSTANDARD\" : \"LVCMOS25\",\n\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t     },\n    \t\"L3\" : {\n\t     \"PACKAGE_PIN\" : \"TBD\",\n             \"IOSTANDARD\" : \"LVCMOS25\",\n\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t     },\n    \t\"L4\" : {\n\t     \"PACKAGE_PIN\" : \"TBD\",\n             \"IOSTANDARD\" : \"LVCMOS25\",\n\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t     },\n    \t\"L5\" : {\n\t     \"PACKAGE_PIN\" : \"TBD\",\n             \"IOSTANDARD\" : \"LVCMOS25\",\n\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t     },\n    \t\"L6\" : {\n\t     \"PACKAGE_PIN\" : \"TBD\",\n             \"IOSTANDARD\" : \"LVCMOS25\",\n\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t     },\n    \t\"L7\" : {\n\t     \"PACKAGE_PIN\" : \"TBD\",\n             \"IOSTANDARD\" : \"LVCMOS25\",\n\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t     }\n    },  \n    \"xadc\" : {\n    \t\"L0\" : {\n\t     \"PACKAGE_PIN\" : \"TBD\",\n             \"IOSTANDARD\" : \"LVCMOS25\",\n\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t     },\n    \t\"L1\" : {\n\t     \"PACKAGE_PIN\" : \"TBD\",\n             \"IOSTANDARD\" : \"LVCMOS25\",\n\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t     },\n    \t\"L2\" : {\n\t     \"PACKAGE_PIN\" : \"TBD\",\n             \"IOSTANDARD\" : \"LVCMOS25\",\n\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t     },\n    \t\"L3\" : {\n\t     \"PACKAGE_PIN\" : \"TBD\",\n             \"IOSTANDARD\" : \"LVCMOS25\",\n\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t     }\n    },\n    \"hdmi\" : {\n        \"clock\" : {\n             \"PACKAGE_PIN\" : \"TBD\",\n\t     \"IOSTANDARD\" : \"LVCMOS25\",\n             \"PIO_DIRECTION\": \"OUTPUT\"\n\t     },\n        \"hsync\" : {\n             \"PACKAGE_PIN\" : \"TBD\",\n\t     \"IOSTANDARD\" : \"LVCMOS25\",\n             \"PIO_DIRECTION\": \"OUTPUT\"\n\t     },\n        \"vsync\" : {\n             \"PACKAGE_PIN\" : \"TBD\",\n\t     \"IOSTANDARD\" : \"LVCMOS25\",\n             \"PIO_DIRECTION\": \"OUTPUT\"\n\t     },\n        \"de\" : {\n             \"PACKAGE_PIN\" : \"TBD\",\n\t     \"IOSTANDARD\" : \"LVCMOS25\",\n             \"PIO_DIRECTION\": \"OUTPUT\"\n\t     },\n        \"data[0]\" : {\n             \"PACKAGE_PIN\" : \"TBD\",\n\t     \"IOSTANDARD\" : \"LVCMOS25\",\n             \"PIO_DIRECTION\": \"OUTPUT\"\n\t     },\n        \"data[1]\" : {\n             \"PACKAGE_PIN\" : \"TBD\",\n\t     \"IOSTANDARD\" : \"LVCMOS25\",\n             \"PIO_DIRECTION\": \"OUTPUT\"\n\t     },\n        \"data[2]\" : {\n             \"PACKAGE_PIN\" : \"TBD\",\n\t     \"IOSTANDARD\" : \"LVCMOS25\",\n             \"PIO_DIRECTION\": \"OUTPUT\"\n\t     },\n        \"data[3]\" : {\n             \"PACKAGE_PIN\" : \"TBD\",\n\t     \"IOSTANDARD\" : \"LVCMOS25\",\n             \"PIO_DIRECTION\": \"OUTPUT\"\n\t     },\n        \"data[4]\" : {\n             \"PACKAGE_PIN\" : \"TBD\",\n\t     \"IOSTANDARD\" : \"LVCMOS25\",\n             \"PIO_DIRECTION\": \"OUTPUT\"\n\t     },\n        \"data[5]\" : {\n             \"PACKAGE_PIN\" : \"TBD\",\n\t     \"IOSTANDARD\" : \"LVCMOS25\",\n             \"PIO_DIRECTION\": \"OUTPUT\"\n\t     },\n        \"data[6]\" : {\n             \"PACKAGE_PIN\" : \"TBD\",\n\t     \"IOSTANDARD\" : \"LVCMOS25\",\n             \"PIO_DIRECTION\": \"OUTPUT\"\n\t     },\n        \"data[7]\" : {\n             \"PACKAGE_PIN\" : \"TBD\",\n\t     \"IOSTANDARD\" : \"LVCMOS25\",\n             \"PIO_DIRECTION\": \"OUTPUT\"\n\t     },\n        \"data[8]\" : {\n             \"PACKAGE_PIN\" : \"TBD\",\n\t     \"IOSTANDARD\" : \"LVCMOS25\",\n             \"PIO_DIRECTION\": \"OUTPUT\"\n\t     },\n        \"data[9]\" : {\n             \"PACKAGE_PIN\" : \"TBD\",\n\t     \"IOSTANDARD\" : \"LVCMOS25\",\n             \"PIO_DIRECTION\": \"OUTPUT\"\n\t     },\n        \"data[10]\" : {\n             \"PACKAGE_PIN\" : \"TBD\",\n\t     \"IOSTANDARD\" : \"LVCMOS25\",\n             \"PIO_DIRECTION\": \"OUTPUT\"\n\t     },\n        \"data[11]\" : {\n             \"PACKAGE_PIN\" : \"TBD\",\n\t     \"IOSTANDARD\" : \"LVCMOS25\",\n             \"PIO_DIRECTION\": \"OUTPUT\"\n\t     },\n        \"data[12]\" : {\n             \"PACKAGE_PIN\" : \"TBD\",\n\t     \"IOSTANDARD\" : \"LVCMOS25\",\n             \"PIO_DIRECTION\": \"OUTPUT\"\n\t     },\n        \"data[13]\" : {\n             \"PACKAGE_PIN\" : \"TBD\",\n\t     \"IOSTANDARD\" : \"LVCMOS25\",\n             \"PIO_DIRECTION\": \"OUTPUT\"\n\t     },\n        \"data[14]\" : {\n             \"PACKAGE_PIN\" : \"TBD\",\n\t     \"IOSTANDARD\" : \"LVCMOS25\",\n             \"PIO_DIRECTION\": \"OUTPUT\"\n\t     },\n        \"data[15]\" : {\n             \"PACKAGE_PIN\" : \"TBD\",\n\t     \"IOSTANDARD\" : \"LVCMOS25\",\n             \"PIO_DIRECTION\": \"OUTPUT\"\n\t     }\n    }\n}\n"
  },
  {
    "path": "boardinfo/zcu111.json",
    "content": "{\n    \"options\": {\n        \"bsvdefines\" : [\"XILINX=1\", \"ZYNQ\", \"ZynqUltrascale\", \"ZynqHostInterface\", \"PhysAddrWidth=40\",\n\t\t\t\"CONNECTAL_BITS_DEPENDENCES=hw/mkTop.bit\", \"CONNECTAL_RUN_SCRIPT=$(CONNECTALDIR)/scripts/run.pcietest\",\n\t\t\t\"CONNECTAL_EXENAME=ubuntu.exe\", \"CONNECTAL_EXENAME2=ubuntu.exe2\"],\n        \"os\" : \"ubuntu\",\n\t\"arch\" : \"arm64\",\n\t\"toolchain\" : \"aarch64-linux-gnu-\",\n        \"partname\" : \"xczu28dr-ffvg1517-2-e\",\n        \"rewireclockstring\" : \"tclzynqrewireclock\",\n        \"constraints\": [],\n        \"implconstraints\": [\"constraints/xilinx/zcu111.xdc\"],\n        \"TOP\" : \"ZynqUltraTop\",\n        \"runscript\" : \"run.pcietest\",\n        \"CONNECTALFLAGS\" : [\"--mainclockperiod=5\", \"--derivedclockperiod=2.5\"],\n        \"ZYNQ_MPSOC\" : \"zynq_ultra_ps_e\"\n    },\n    \"fmc1\": {\n\t\"LA00_p_CC\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n        },\n\t\"LA00_n_CC\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n        },\n\t\"LA01_p_CC\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n        },\n\t\"LA01_n_CC\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n        },\n\t\"LA02_p\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n        },\n\t\"LA02_n\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n        },\n\t\"LA03_p\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n        },\n\t\"LA03_n\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n        },\n\t\"LA04_p\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n        },\n\t\"LA04_n\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n        },\n\t\"LA05_p\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n        },\n\t\"LA05_n\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n        },\n\t\"LA06_p\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n        },\n\t\"LA06_n\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n        },\n\t\"LA07_p\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n        },\n\t\"LA07_n\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n        },\n\t\"LA08_p\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n        },\n\t\"LA08_n\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n        },\n\t\"LA09_p\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n        },\n\t\"LA09_n\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n        },\n\t\"LA10_p\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n        },\n\t\"LA10_n\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n        },\n\t\"LA11_p\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n        },\n\t\"LA11_n\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n        },\n\t\"LA12_p\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n        },\n\t\"LA12_n\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n        },\n\t\"LA13_p\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n        },\n\t\"LA13_n\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n        },\n\t\"LA14_p\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n        },\n\t\"LA14_n\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n        },\n\t\"LA15_p\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n        },\n\t\"LA15_n\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n        },\n\t\"LA16_p\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n        },\n\t\"LA16_n\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n        },\n\t\"LA17_p_CC\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n        },\n\t\"LA17_n_CC\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n        },\n\t\"LA18_p_CC\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n        },\n\t\"LA18_n_CC\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n        },\n\t\"LA19_p\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n        },\n\t\"LA19_n\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n        },\n\t\"CLK0_M2C_p\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n        },\n\t\"CLK0_M2C_n\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n        }\n    },\n    \"fmc2\": {\n\t\"LA00_p_CC\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n\t},\n\t\"LA00_n_CC\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n\t},\n\t\"LA01_p_CC\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n\t},\n\t\"LA01_n_CC\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n\t},\n\t\"LA02_p\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n\t},\n\t\"LA02_n\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n\t},\n\t\"LA03_p\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n\t},\n\t\"LA03_n\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n\t},\n\t\"LA04_p\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n\t},\n\t\"LA04_n\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n\t},\n\t\"LA05_p\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n\t},\n\t\"LA05_n\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n\t},\n\t\"LA06_p\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n\t},\n\t\"LA06_n\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n\t},\n\t\"LA07_p\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n\t},\n\t\"LA07_n\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n\t},\n\t\"LA08_p\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n\t},\n\t\"LA08_n\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n\t},\n\t\"LA09_p\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n\t},\n\t\"LA09_n\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n\t},\n\t\"LA10_p\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n\t},\n\t\"LA10_n\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n\t},\n\t\"LA11_p\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n\t},\n\t\"LA11_n\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n\t},\n\t\"LA12_p\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n\t},\n\t\"LA12_n\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n\t},\n\t\"LA13_p\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n\t},\n\t\"LA13_n\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n\t},\n\t\"LA14_p\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n\t},\n\t\"LA14_n\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n\t},\n\t\"LA15_p\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n\t},\n\t\"LA15_n\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n\t},\n\t\"LA16_p\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n\t},\n\t\"LA16_n\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n\t},\n\t\"LA17_p_CC\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n\t},\n\t\"LA17_n_CC\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n\t},\n\t\"LA18_p_CC\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n\t},\n\t\"LA18_n_CC\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n\t},\n\t\"LA19_p\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n\t},\n\t\"LA19_n\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n\t},\n\t\"CLK0_M2C_p\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n\t},\n\t\"CLK0_M2C_n\": {\n            \"PACKAGE_PIN\": \"TBD\",\n            \"IOSTANDARD\": \"LVCMOS25\"\n\t}\n    },\n    \"leds\" : {\n    \t\"L0\" : {\n\t     \"PACKAGE_PIN\" : \"TBD\",\n             \"IOSTANDARD\" : \"LVCMOS25\",\n\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t     },\n    \t\"L1\" : {\n\t     \"PACKAGE_PIN\" : \"TBD\",\n             \"IOSTANDARD\" : \"LVCMOS25\",\n\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t     },\n    \t\"L2\" : {\n\t     \"PACKAGE_PIN\" : \"TBD\",\n             \"IOSTANDARD\" : \"LVCMOS25\",\n\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t     },\n    \t\"L3\" : {\n\t     \"PACKAGE_PIN\" : \"TBD\",\n             \"IOSTANDARD\" : \"LVCMOS25\",\n\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t     },\n    \t\"L4\" : {\n\t     \"PACKAGE_PIN\" : \"TBD\",\n             \"IOSTANDARD\" : \"LVCMOS25\",\n\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t     },\n    \t\"L5\" : {\n\t     \"PACKAGE_PIN\" : \"TBD\",\n             \"IOSTANDARD\" : \"LVCMOS25\",\n\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t     },\n    \t\"L6\" : {\n\t     \"PACKAGE_PIN\" : \"TBD\",\n             \"IOSTANDARD\" : \"LVCMOS25\",\n\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t     },\n    \t\"L7\" : {\n\t     \"PACKAGE_PIN\" : \"TBD\",\n             \"IOSTANDARD\" : \"LVCMOS25\",\n\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t     }\n    },  \n    \"xadc\" : {\n    \t\"L0\" : {\n\t     \"PACKAGE_PIN\" : \"TBD\",\n             \"IOSTANDARD\" : \"LVCMOS25\",\n\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t     },\n    \t\"L1\" : {\n\t     \"PACKAGE_PIN\" : \"TBD\",\n             \"IOSTANDARD\" : \"LVCMOS25\",\n\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t     },\n    \t\"L2\" : {\n\t     \"PACKAGE_PIN\" : \"TBD\",\n             \"IOSTANDARD\" : \"LVCMOS25\",\n\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t     },\n    \t\"L3\" : {\n\t     \"PACKAGE_PIN\" : \"TBD\",\n             \"IOSTANDARD\" : \"LVCMOS25\",\n\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t     }\n    },\n    \"hdmi\" : {\n        \"clock\" : {\n             \"PACKAGE_PIN\" : \"TBD\",\n\t     \"IOSTANDARD\" : \"LVCMOS25\",\n             \"PIO_DIRECTION\": \"OUTPUT\"\n\t     },\n        \"hsync\" : {\n             \"PACKAGE_PIN\" : \"TBD\",\n\t     \"IOSTANDARD\" : \"LVCMOS25\",\n             \"PIO_DIRECTION\": \"OUTPUT\"\n\t     },\n        \"vsync\" : {\n             \"PACKAGE_PIN\" : \"TBD\",\n\t     \"IOSTANDARD\" : \"LVCMOS25\",\n             \"PIO_DIRECTION\": \"OUTPUT\"\n\t     },\n        \"de\" : {\n             \"PACKAGE_PIN\" : \"TBD\",\n\t     \"IOSTANDARD\" : \"LVCMOS25\",\n             \"PIO_DIRECTION\": \"OUTPUT\"\n\t     },\n        \"data[0]\" : {\n             \"PACKAGE_PIN\" : \"TBD\",\n\t     \"IOSTANDARD\" : \"LVCMOS25\",\n             \"PIO_DIRECTION\": \"OUTPUT\"\n\t     },\n        \"data[1]\" : {\n             \"PACKAGE_PIN\" : \"TBD\",\n\t     \"IOSTANDARD\" : \"LVCMOS25\",\n             \"PIO_DIRECTION\": \"OUTPUT\"\n\t     },\n        \"data[2]\" : {\n             \"PACKAGE_PIN\" : \"TBD\",\n\t     \"IOSTANDARD\" : \"LVCMOS25\",\n             \"PIO_DIRECTION\": \"OUTPUT\"\n\t     },\n        \"data[3]\" : {\n             \"PACKAGE_PIN\" : \"TBD\",\n\t     \"IOSTANDARD\" : \"LVCMOS25\",\n             \"PIO_DIRECTION\": \"OUTPUT\"\n\t     },\n        \"data[4]\" : {\n             \"PACKAGE_PIN\" : \"TBD\",\n\t     \"IOSTANDARD\" : \"LVCMOS25\",\n             \"PIO_DIRECTION\": \"OUTPUT\"\n\t     },\n        \"data[5]\" : {\n             \"PACKAGE_PIN\" : \"TBD\",\n\t     \"IOSTANDARD\" : \"LVCMOS25\",\n             \"PIO_DIRECTION\": \"OUTPUT\"\n\t     },\n        \"data[6]\" : {\n             \"PACKAGE_PIN\" : \"TBD\",\n\t     \"IOSTANDARD\" : \"LVCMOS25\",\n             \"PIO_DIRECTION\": \"OUTPUT\"\n\t     },\n        \"data[7]\" : {\n             \"PACKAGE_PIN\" : \"TBD\",\n\t     \"IOSTANDARD\" : \"LVCMOS25\",\n             \"PIO_DIRECTION\": \"OUTPUT\"\n\t     },\n        \"data[8]\" : {\n             \"PACKAGE_PIN\" : \"TBD\",\n\t     \"IOSTANDARD\" : \"LVCMOS25\",\n             \"PIO_DIRECTION\": \"OUTPUT\"\n\t     },\n        \"data[9]\" : {\n             \"PACKAGE_PIN\" : \"TBD\",\n\t     \"IOSTANDARD\" : \"LVCMOS25\",\n             \"PIO_DIRECTION\": \"OUTPUT\"\n\t     },\n        \"data[10]\" : {\n             \"PACKAGE_PIN\" : \"TBD\",\n\t     \"IOSTANDARD\" : \"LVCMOS25\",\n             \"PIO_DIRECTION\": \"OUTPUT\"\n\t     },\n        \"data[11]\" : {\n             \"PACKAGE_PIN\" : \"TBD\",\n\t     \"IOSTANDARD\" : \"LVCMOS25\",\n             \"PIO_DIRECTION\": \"OUTPUT\"\n\t     },\n        \"data[12]\" : {\n             \"PACKAGE_PIN\" : \"TBD\",\n\t     \"IOSTANDARD\" : \"LVCMOS25\",\n             \"PIO_DIRECTION\": \"OUTPUT\"\n\t     },\n        \"data[13]\" : {\n             \"PACKAGE_PIN\" : \"TBD\",\n\t     \"IOSTANDARD\" : \"LVCMOS25\",\n             \"PIO_DIRECTION\": \"OUTPUT\"\n\t     },\n        \"data[14]\" : {\n             \"PACKAGE_PIN\" : \"TBD\",\n\t     \"IOSTANDARD\" : \"LVCMOS25\",\n             \"PIO_DIRECTION\": \"OUTPUT\"\n\t     },\n        \"data[15]\" : {\n             \"PACKAGE_PIN\" : \"TBD\",\n\t     \"IOSTANDARD\" : \"LVCMOS25\",\n             \"PIO_DIRECTION\": \"OUTPUT\"\n\t     }\n    }\n}\n"
  },
  {
    "path": "boardinfo/zedboard.json",
    "content": "{\n    \"options\": {\n        \"bsvdefines\" : [\"XILINX=1\", \"ZYNQ\", \"ZynqHostInterface\", \"PhysAddrWidth=32\", \"CFGBVS=VCCO\", \"CONFIG_VOLTAGE=3.3\",\n\t\t\t\"CONNECTAL_BITS_DEPENDENCES=hw/mkTop.bit\", \"CONNECTAL_RUN_SCRIPT=$(CONNECTALDIR)/scripts/run.android\",\n\t\t\t\"CONNECTAL_EXENAME=android.exe\", \"CONNECTAL_EXENAME2=android.exe2\"\n\t\t       ],\n        \"os\" : \"android\",\n        \"partname\" : \"xc7z020clg484-1\",\n        \"rewireclockstring\" : \"tclzynqrewireclock\",\n        \"constraints\": [],\n        \"implconstraints\": [\"constraints/xilinx/zc7z020clg484.xdc\"],\n        \"TOP\" : \"ZynqTop\",\n        \"runscript\" : \"run.android\",\n        \"CONNECTALFLAGS\" : [\"--mainclockperiod=10\", \"--derivedclockperiod=5\"],\n        \"need_pcie\" : \"unused\"\n    },\n    \"fmc1\": {\n    \"LA00_CC_P\": {\n        \"PACKAGE_PIN\": \"M19\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA00_CC_N\": {\n        \"PACKAGE_PIN\": \"M20\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA01_CC_P\": {\n        \"PACKAGE_PIN\": \"N19\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA01_CC_N\": {\n        \"PACKAGE_PIN\": \"N20\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA02_P\": {\n        \"PACKAGE_PIN\": \"P17\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA02_N\": {\n        \"PACKAGE_PIN\": \"P18\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA03_P\": {\n        \"PACKAGE_PIN\": \"N22\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA03_N\": {\n        \"PACKAGE_PIN\": \"P22\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA04_P\": {\n        \"PACKAGE_PIN\": \"M21\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA04_N\": {\n        \"PACKAGE_PIN\": \"M22\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA05_P\": {\n        \"PACKAGE_PIN\": \"J18\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA05_N\": {\n        \"PACKAGE_PIN\": \"K18\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA06_P\": {\n        \"PACKAGE_PIN\": \"L21\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA06_N\": {\n        \"PACKAGE_PIN\": \"L22\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA07_P\": {\n        \"PACKAGE_PIN\": \"T16\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA07_N\": {\n        \"PACKAGE_PIN\": \"T17\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA08_P\": {\n        \"PACKAGE_PIN\": \"J21\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA08_N\": {\n        \"PACKAGE_PIN\": \"J22\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA09_P\": {\n        \"PACKAGE_PIN\": \"R20\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA09_N\": {\n        \"PACKAGE_PIN\": \"R21\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA10_P\": {\n        \"PACKAGE_PIN\": \"R19\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA10_N\": {\n        \"PACKAGE_PIN\": \"T19\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA11_P\": {\n        \"PACKAGE_PIN\": \"N17\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA11_N\": {\n        \"PACKAGE_PIN\": \"N18\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA12_P\": {\n        \"PACKAGE_PIN\": \"P20\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA12_N\": {\n        \"PACKAGE_PIN\": \"P21\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA13_P\": {\n        \"PACKAGE_PIN\": \"L17\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA13_N\": {\n        \"PACKAGE_PIN\": \"M17\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA14_P\": {\n        \"PACKAGE_PIN\": \"K19\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA14_N\": {\n        \"PACKAGE_PIN\": \"K20\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA15_P\": {\n        \"PACKAGE_PIN\": \"J16\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA15_N\": {\n        \"PACKAGE_PIN\": \"J17\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA16_P\": {\n        \"PACKAGE_PIN\": \"J20\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA16_N\": {\n        \"PACKAGE_PIN\": \"K21\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA17_CC_P\": {\n        \"PACKAGE_PIN\": \"B19\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA17_CC_N\": {\n        \"PACKAGE_PIN\": \"B20\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA18_CC_P\": {\n        \"PACKAGE_PIN\": \"D20\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA18_CC_N\": {\n        \"PACKAGE_PIN\": \"C20\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA19_P\": {\n        \"PACKAGE_PIN\": \"G15\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA19_N\": {\n        \"PACKAGE_PIN\": \"G16\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA20_P\": {\n        \"PACKAGE_PIN\": \"G20\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA20_N\": {\n        \"PACKAGE_PIN\": \"G21\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA21_P\": {\n        \"PACKAGE_PIN\": \"E19\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA21_N\": {\n        \"PACKAGE_PIN\": \"E20\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA22_P\": {\n        \"PACKAGE_PIN\": \"G19\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA22_N\": {\n        \"PACKAGE_PIN\": \"F19\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA23_P\": {\n        \"PACKAGE_PIN\": \"E15\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA23_N\": {\n        \"PACKAGE_PIN\": \"D15\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA24_P\": {\n        \"PACKAGE_PIN\": \"A18\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA24_N\": {\n        \"PACKAGE_PIN\": \"A19\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA25_P\": {\n        \"PACKAGE_PIN\": \"D22\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA25_N\": {\n        \"PACKAGE_PIN\": \"C22\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA26_P\": {\n        \"PACKAGE_PIN\": \"F18\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA26_N\": {\n        \"PACKAGE_PIN\": \"E18\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA27_P\": {\n        \"PACKAGE_PIN\": \"E21\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA27_N\": {\n        \"PACKAGE_PIN\": \"D21\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA28_P\": {\n        \"PACKAGE_PIN\": \"A16\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA28_N\": {\n        \"PACKAGE_PIN\": \"A17\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA29_P\": {\n        \"PACKAGE_PIN\": \"C17\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA29_N\": {\n        \"PACKAGE_PIN\": \"C18\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA30_P\": {\n        \"PACKAGE_PIN\": \"C15\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA30_N\": {\n        \"PACKAGE_PIN\": \"B15\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA31_P\": {\n        \"PACKAGE_PIN\": \"B16\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA31_N\": {\n        \"PACKAGE_PIN\": \"B17\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA32_P\": {\n        \"PACKAGE_PIN\": \"A21\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA32_N\": {\n        \"PACKAGE_PIN\": \"A22\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA33_P\": {\n        \"PACKAGE_PIN\": \"B21\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA33_N\": {\n        \"PACKAGE_PIN\": \"B22\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"CLK0_M2C_P\": {\n        \"PACKAGE_PIN\": \"L18\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"CLK0_M2C_N\": {\n        \"PACKAGE_PIN\": \"L19\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"CLK1_M2C_P\": {\n        \"PACKAGE_PIN\": \"D18\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"CLK1_M2C_N\": {\n        \"PACKAGE_PIN\": \"C19\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"SDA\": {\n        \"PACKAGE_PIN\": \"U7\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"SCL\": {\n        \"PACKAGE_PIN\": \"R7\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        }\n    },\n    \"pins\": {\n\t\"GPIO_sw_left\": {\n\t    \"PACKAGE_PIN\": \"N15\",\n\t    \"IOSTANDARD\": \"LVCMOS18\",\n\t    \"slew\": \"SLOW\",\n\t    \"PIO_DIRECTION\": \"INPUT\"\n\t},\n\t\"GPIO_sw_center\": {\n\t    \"PACKAGE_PIN\": \"P16\",\n\t    \"IOSTANDARD\": \"LVCMOS18\",\n\t    \"slew\": \"SLOW\",\n\t    \"PIO_DIRECTION\": \"INPUT\"\n\t},\n\t\"GPIO_sw_right\": {\n\t    \"PACKAGE_PIN\": \"R18\",\n\t    \"IOSTANDARD\": \"LVCMOS18\",\n\t    \"slew\": \"SLOW\",\n\t    \"PIO_DIRECTION\": \"INPUT\"\n\t},\n\t\"GPIO_sw_down\": {\n\t    \"PACKAGE_PIN\": \"R16\",\n\t    \"IOSTANDARD\": \"LVCMOS18\",\n\t    \"slew\": \"SLOW\",\n\t    \"PIO_DIRECTION\": \"INPUT\"\n\t},\n\t\"GPIO_sw_up\": {\n\t    \"PACKAGE_PIN\": \"T18\",\n\t    \"IOSTANDARD\": \"LVCMOS18\",\n\t    \"slew\": \"SLOW\",\n\t    \"PIO_DIRECTION\": \"INPUT\"\n\t}\n    },\n    \"pmoda\" : {\n        \"J1\" : {\n             \"PACKAGE_PIN\" : \"Y11\",\n\t     \"IOSTANDARD\" : \"LVCMOS33\"\n\t     },\n        \"J2\" : {\n             \"PACKAGE_PIN\" : \"AA11\",\n\t     \"IOSTANDARD\" : \"LVCMOS33\"\n\t     },\n        \"J3\" : {\n             \"PACKAGE_PIN\" : \"Y10\",\n\t     \"IOSTANDARD\" : \"LVCMOS33\"\n\t     },\n        \"J4\" : {\n             \"PACKAGE_PIN\" : \"AA9\",\n\t     \"IOSTANDARD\" : \"LVCMOS33\"\n\t     },\n        \"J7\" : {\n             \"PACKAGE_PIN\" : \"AB11\",\n\t     \"IOSTANDARD\" : \"LVCMOS33\"\n\t     },\n        \"J8\" : {\n             \"PACKAGE_PIN\" : \"AB10\",\n\t     \"IOSTANDARD\" : \"LVCMOS33\"\n\t     },\n        \"J9\" : {\n             \"PACKAGE_PIN\" : \"AB9\",\n\t     \"IOSTANDARD\" : \"LVCMOS33\"\n\t     },\n        \"J10\" : {\n             \"PACKAGE_PIN\" : \"AA8\",\n\t     \"IOSTANDARD\" : \"LVCMOS33\"\n\t     }\t \n    },\n    \"pmodb\" : {\n        \"J1\" : {\n             \"PACKAGE_PIN\" : \"W12\",\n\t     \"IOSTANDARD\" : \"LVCMOS33\"\n\t     },\n        \"J2\" : {\n             \"PACKAGE_PIN\" : \"W11\",\n\t     \"IOSTANDARD\" : \"LVCMOS33\"\n\t     },\n        \"J3\" : {\n             \"PACKAGE_PIN\" : \"V10\",\n\t     \"IOSTANDARD\" : \"LVCMOS33\"\n\t     },\n        \"J4\" : {\n             \"PACKAGE_PIN\" : \"W8\",\n\t     \"IOSTANDARD\" : \"LVCMOS33\"\n\t     },\n        \"J7\" : {\n             \"PACKAGE_PIN\" : \"V12\",\n\t     \"IOSTANDARD\" : \"LVCMOS33\"\n\t     },\n        \"J8\" : {\n             \"PACKAGE_PIN\" : \"W10\",\n\t     \"IOSTANDARD\" : \"LVCMOS33\"\n\t     },\n        \"J9\" : {\n             \"PACKAGE_PIN\" : \"V9\",\n\t     \"IOSTANDARD\" : \"LVCMOS33\"\n\t     },\n        \"J10\" : {\n             \"PACKAGE_PIN\" : \"V8\",\n\t     \"IOSTANDARD\" : \"LVCMOS33\"\n\t     }\t \n    },\n    \"pmodc\" : {\n        \"J1\" : {\n             \"PACKAGE_PIN\" : \"AB7\",\n\t     \"IOSTANDARD\" : \"LVCMOS33\"\n\t     },\n        \"J2\" : {\n             \"PACKAGE_PIN\" : \"AB6\",\n\t     \"IOSTANDARD\" : \"LVCMOS33\"\n\t     },\n        \"J3\" : {\n             \"PACKAGE_PIN\" : \"Y4\",\n\t     \"IOSTANDARD\" : \"LVCMOS33\"\n\t     },\n        \"J4\" : {\n             \"PACKAGE_PIN\" : \"AA4\",\n\t     \"IOSTANDARD\" : \"LVCMOS33\"\n\t     },\n        \"J7\" : {\n             \"PACKAGE_PIN\" : \"R6\",\n\t     \"IOSTANDARD\" : \"LVCMOS33\"\n\t     },\n        \"J8\" : {\n             \"PACKAGE_PIN\" : \"T6\",\n\t     \"IOSTANDARD\" : \"LVCMOS33\"\n\t     },\n        \"J9\" : {\n             \"PACKAGE_PIN\" : \"T4\",\n\t     \"IOSTANDARD\" : \"LVCMOS33\"\n\t     },\n        \"J10\" : {\n             \"PACKAGE_PIN\" : \"U4\",\n\t     \"IOSTANDARD\" : \"LVCMOS33\"\n\t     }\t \n    },\n    \"pmodd\" : {\n        \"J1\" : {\n             \"PACKAGE_PIN\" : \"V7\",\n\t     \"IOSTANDARD\" : \"LVCMOS33\"\n\t     },\n        \"J2\" : {\n             \"PACKAGE_PIN\" : \"W7\",\n\t     \"IOSTANDARD\" : \"LVCMOS33\"\n\t     },\n        \"J3\" : {\n             \"PACKAGE_PIN\" : \"V5\",\n\t     \"IOSTANDARD\" : \"LVCMOS33\"\n\t     },\n        \"J4\" : {\n             \"PACKAGE_PIN\" : \"V4\",\n\t     \"IOSTANDARD\" : \"LVCMOS33\"\n\t     },\n        \"J7\" : {\n             \"PACKAGE_PIN\" : \"W6\",\n\t     \"IOSTANDARD\" : \"LVCMOS33\"\n\t     },\n        \"J8\" : {\n             \"PACKAGE_PIN\" : \"W5\",\n\t     \"IOSTANDARD\" : \"LVCMOS33\"\n\t     },\n        \"J9\" : {\n             \"PACKAGE_PIN\" : \"U6\",\n\t     \"IOSTANDARD\" : \"LVCMOS33\"\n\t     },\n        \"J10\" : {\n             \"PACKAGE_PIN\" : \"U5\",\n\t     \"IOSTANDARD\" : \"LVCMOS33\"\n\t     }\t \n    },\n    \"pmode_documentation_only;cannot use from PL\" : {\n        \"MIO13\" : {\n             \"PACKAGE_PIN\" : \"A6\",\n\t     \"CONNECTORPIN\" : \"JE1\"\n\t     },\n        \"MIO10\" : {\n             \"PACKAGE_PIN\" : \"G7\",\n\t     \"CONNECTORPIN\" : \"JE2\"\n\t     },\n        \"MIO11\" : {\n             \"PACKAGE_PIN\" : \"B4\",\n\t     \"CONNECTORPIN\" : \"JE3\"\n\t     },\n        \"MIO12\" : {\n             \"PACKAGE_PIN\" : \"C5\",\n\t     \"CONNECTORPIN\" : \"JE4\"\n\t     },\n        \"MIO0\" : {\n             \"PACKAGE_PIN\" : \"G6\",\n\t     \"CONNECTORPIN\" : \"JE7\"\n\t     },\n        \"MIO9\" : {\n             \"PACKAGE_PIN\" : \"C4\",\n\t     \"CONNECTORPIN\" : \"JE8\"\n\t     },\n        \"MIO14\" : {\n             \"PACKAGE_PIN\" : \"B6\",\n\t     \"CONNECTORPIN\" : \"JE9\"\n\t     },\n        \"MIO15\" : {\n             \"PACKAGE_PIN\" : \"E6\",\n\t     \"CONNECTORPIN\" : \"JE10\"\n\t     }\n    },\n    \"pins\": {\n    \t\"GPIO_LEDS[0]\" : {\n\t     \"PACKAGE_PIN\" : \"T22\",\n             \"IOSTANDARD\" : \"LVCMOS25\",\n\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t     },\n    \t\"GPIO_LEDS[1]\" : {\n\t     \"PACKAGE_PIN\" : \"T21\",\n             \"IOSTANDARD\" : \"LVCMOS25\",\n\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t     },\n    \t\"GPIO_LEDS[2]\" : {\n\t     \"PACKAGE_PIN\" : \"U22\",\n             \"IOSTANDARD\" : \"LVCMOS25\",\n\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t     },\n    \t\"GPIO_LEDS[3]\" : {\n\t     \"PACKAGE_PIN\" : \"U21\",\n             \"IOSTANDARD\" : \"LVCMOS25\",\n\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t     },\n    \t\"GPIO_LEDS[4]\" : {\n\t     \"PACKAGE_PIN\" : \"V22\",\n             \"IOSTANDARD\" : \"LVCMOS25\",\n\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t     },\n    \t\"GPIO_LEDS[5]\" : {\n\t     \"PACKAGE_PIN\" : \"W22\",\n             \"IOSTANDARD\" : \"LVCMOS25\",\n\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t     },\n    \t\"GPIO_LEDS[6]\" : {\n\t     \"PACKAGE_PIN\" : \"U19\",\n             \"IOSTANDARD\" : \"LVCMOS25\",\n\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t     },\n    \t\"GPIO_LEDS[7]\" : {\n\t     \"PACKAGE_PIN\" : \"U14\",\n             \"IOSTANDARD\" : \"LVCMOS25\",\n\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t     }\n    },  \n    \"i2c0\" : {\n        \"scl\" : {\n             \"PACKAGE_PIN\" : \"AA18\",\n\t     \"IOSTANDARD\" : \"LVCMOS25\",\n\t     \"PIO_DIRECTION\": \"BIDIR\"\n\t     },\n        \"sda\" : {\n             \"PACKAGE_PIN\" : \"Y16\",\n\t     \"IOSTANDARD\" : \"LVCMOS25\",\n\t     \"PIO_DIRECTION\": \"BIDIR\"\n\t     }\t \n    },\n    \"hdmi\" : {\n        \"clock\" : {\n             \"PACKAGE_PIN\" : \"W18\",\n\t     \"IOSTANDARD\" : \"LVCMOS25\",\n             \"PIO_DIRECTION\": \"OUTPUT\"\n\t     },\n        \"hsync\" : {\n             \"PACKAGE_PIN\" : \"V17\",\n\t     \"IOSTANDARD\" : \"LVCMOS25\",\n             \"PIO_DIRECTION\": \"OUTPUT\"\n\t     },\n        \"vsync\" : {\n             \"PACKAGE_PIN\" : \"W17\",\n\t     \"IOSTANDARD\" : \"LVCMOS25\",\n             \"PIO_DIRECTION\": \"OUTPUT\"\n\t     },\n        \"de\" : {\n             \"PACKAGE_PIN\" : \"U16\",\n\t     \"IOSTANDARD\" : \"LVCMOS25\",\n             \"PIO_DIRECTION\": \"OUTPUT\"\n\t     },\n        \"data[0]\" : {\n             \"PACKAGE_PIN\" : \"Y13\",\n\t     \"IOSTANDARD\" : \"LVCMOS25\",\n             \"PIO_DIRECTION\": \"OUTPUT\"\n\t     },\n        \"data[1]\" : {\n             \"PACKAGE_PIN\" : \"AA13\",\n\t     \"IOSTANDARD\" : \"LVCMOS25\",\n             \"PIO_DIRECTION\": \"OUTPUT\"\n\t     },\n        \"data[2]\" : {\n             \"PACKAGE_PIN\" : \"AA14\",\n\t     \"IOSTANDARD\" : \"LVCMOS25\",\n             \"PIO_DIRECTION\": \"OUTPUT\"\n\t     },\n        \"data[3]\" : {\n             \"PACKAGE_PIN\" : \"Y14\",\n\t     \"IOSTANDARD\" : \"LVCMOS25\",\n             \"PIO_DIRECTION\": \"OUTPUT\"\n\t     },\n        \"data[4]\" : {\n             \"PACKAGE_PIN\" : \"AB15\",\n\t     \"IOSTANDARD\" : \"LVCMOS25\",\n             \"PIO_DIRECTION\": \"OUTPUT\"\n\t     },\n        \"data[5]\" : {\n             \"PACKAGE_PIN\" : \"AB16\",\n\t     \"IOSTANDARD\" : \"LVCMOS25\",\n             \"PIO_DIRECTION\": \"OUTPUT\"\n\t     },\n        \"data[6]\" : {\n             \"PACKAGE_PIN\" : \"AA16\",\n\t     \"IOSTANDARD\" : \"LVCMOS25\",\n             \"PIO_DIRECTION\": \"OUTPUT\"\n\t     },\n        \"data[7]\" : {\n             \"PACKAGE_PIN\" : \"AB17\",\n\t     \"IOSTANDARD\" : \"LVCMOS25\",\n             \"PIO_DIRECTION\": \"OUTPUT\"\n\t     },\n        \"data[8]\" : {\n             \"PACKAGE_PIN\" : \"AA17\",\n\t     \"IOSTANDARD\" : \"LVCMOS25\",\n             \"PIO_DIRECTION\": \"OUTPUT\"\n\t     },\n        \"data[9]\" : {\n             \"PACKAGE_PIN\" : \"Y15\",\n\t     \"IOSTANDARD\" : \"LVCMOS25\",\n             \"PIO_DIRECTION\": \"OUTPUT\"\n\t     },\n        \"data[10]\" : {\n             \"PACKAGE_PIN\" : \"W13\",\n\t     \"IOSTANDARD\" : \"LVCMOS25\",\n             \"PIO_DIRECTION\": \"OUTPUT\"\n\t     },\n        \"data[11]\" : {\n             \"PACKAGE_PIN\" : \"W15\",\n\t     \"IOSTANDARD\" : \"LVCMOS25\",\n             \"PIO_DIRECTION\": \"OUTPUT\"\n\t     },\n        \"data[12]\" : {\n             \"PACKAGE_PIN\" : \"V15\",\n\t     \"IOSTANDARD\" : \"LVCMOS25\",\n             \"PIO_DIRECTION\": \"OUTPUT\"\n\t     },\n        \"data[13]\" : {\n             \"PACKAGE_PIN\" : \"U17\",\n\t     \"IOSTANDARD\" : \"LVCMOS25\",\n             \"PIO_DIRECTION\": \"OUTPUT\"\n\t     },\n        \"data[14]\" : {\n             \"PACKAGE_PIN\" : \"V14\",\n\t     \"IOSTANDARD\" : \"LVCMOS25\",\n             \"PIO_DIRECTION\": \"OUTPUT\"\n\t     },\n        \"data[15]\" : {\n             \"PACKAGE_PIN\" : \"V13\",\n\t     \"IOSTANDARD\" : \"LVCMOS25\",\n             \"PIO_DIRECTION\": \"OUTPUT\"\n\t     }\n    }\n}\n"
  },
  {
    "path": "boardinfo/zedboard_ubuntu.json",
    "content": "{\n    \"options\": {\n        \"bsvdefines\" : [\"XILINX=1\", \"ZYNQ\", \"ZynqHostInterface\", \"PhysAddrWidth=32\", \"CFGBVS=VCCO\", \"CONFIG_VOLTAGE=3.3\",\n\t\t\t\"CONNECTAL_BITS_DEPENDENCES=hw/mkTop.bit\", \"CONNECTAL_RUN_SCRIPT=$(CONNECTALDIR)/scripts/run.pcietest\",\n\t\t\t\"CONNECTAL_EXENAME=ubuntu.exe\", \"CONNECTAL_EXENAME2=ubuntu.exe2\"\n\t\t       ],\n        \"os\" : \"ubuntu\",\n\t\"arch\" : \"arm\",\n\t\"toolchain\" : \"arm-linux-gnueabihf-\",\n        \"partname\" : \"xc7z020clg484-1\",\n        \"rewireclockstring\" : \"tclzynqrewireclock\",\n        \"constraints\": [],\n        \"implconstraints\": [\"constraints/xilinx/zc7z020clg484.xdc\"],\n        \"TOP\" : \"ZynqTop\",\n        \"runscript\" : \"run.pcietest\",\n        \"CONNECTALFLAGS\" : [\"--mainclockperiod=10\", \"--derivedclockperiod=5\"],\n        \"need_pcie\" : \"unused\"\n    },\n    \"fmc1\": {\n    \"LA00_CC_P\": {\n        \"PACKAGE_PIN\": \"M19\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA00_CC_N\": {\n        \"PACKAGE_PIN\": \"M20\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA01_CC_P\": {\n        \"PACKAGE_PIN\": \"N19\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA01_CC_N\": {\n        \"PACKAGE_PIN\": \"N20\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA02_P\": {\n        \"PACKAGE_PIN\": \"P17\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA02_N\": {\n        \"PACKAGE_PIN\": \"P18\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA03_P\": {\n        \"PACKAGE_PIN\": \"N22\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA03_N\": {\n        \"PACKAGE_PIN\": \"P22\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA04_P\": {\n        \"PACKAGE_PIN\": \"M21\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA04_N\": {\n        \"PACKAGE_PIN\": \"M22\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA05_P\": {\n        \"PACKAGE_PIN\": \"J18\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA05_N\": {\n        \"PACKAGE_PIN\": \"K18\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA06_P\": {\n        \"PACKAGE_PIN\": \"L21\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA06_N\": {\n        \"PACKAGE_PIN\": \"L22\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA07_P\": {\n        \"PACKAGE_PIN\": \"T16\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA07_N\": {\n        \"PACKAGE_PIN\": \"T17\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA08_P\": {\n        \"PACKAGE_PIN\": \"J21\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA08_N\": {\n        \"PACKAGE_PIN\": \"J22\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA09_P\": {\n        \"PACKAGE_PIN\": \"R20\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA09_N\": {\n        \"PACKAGE_PIN\": \"R21\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA10_P\": {\n        \"PACKAGE_PIN\": \"R19\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA10_N\": {\n        \"PACKAGE_PIN\": \"T19\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA11_P\": {\n        \"PACKAGE_PIN\": \"N17\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA11_N\": {\n        \"PACKAGE_PIN\": \"N18\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA12_P\": {\n        \"PACKAGE_PIN\": \"P20\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA12_N\": {\n        \"PACKAGE_PIN\": \"P21\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA13_P\": {\n        \"PACKAGE_PIN\": \"L17\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA13_N\": {\n        \"PACKAGE_PIN\": \"M17\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA14_P\": {\n        \"PACKAGE_PIN\": \"K19\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA14_N\": {\n        \"PACKAGE_PIN\": \"K20\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA15_P\": {\n        \"PACKAGE_PIN\": \"J16\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA15_N\": {\n        \"PACKAGE_PIN\": \"J17\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA16_P\": {\n        \"PACKAGE_PIN\": \"J20\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA16_N\": {\n        \"PACKAGE_PIN\": \"K21\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA17_CC_P\": {\n        \"PACKAGE_PIN\": \"B19\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA17_CC_N\": {\n        \"PACKAGE_PIN\": \"B20\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA18_CC_P\": {\n        \"PACKAGE_PIN\": \"D20\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA18_CC_N\": {\n        \"PACKAGE_PIN\": \"C20\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA19_P\": {\n        \"PACKAGE_PIN\": \"G15\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA19_N\": {\n        \"PACKAGE_PIN\": \"G16\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA20_P\": {\n        \"PACKAGE_PIN\": \"G20\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA20_N\": {\n        \"PACKAGE_PIN\": \"G21\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA21_P\": {\n        \"PACKAGE_PIN\": \"E19\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA21_N\": {\n        \"PACKAGE_PIN\": \"E20\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA22_P\": {\n        \"PACKAGE_PIN\": \"G19\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA22_N\": {\n        \"PACKAGE_PIN\": \"F19\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA23_P\": {\n        \"PACKAGE_PIN\": \"E15\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA23_N\": {\n        \"PACKAGE_PIN\": \"D15\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA24_P\": {\n        \"PACKAGE_PIN\": \"A18\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA24_N\": {\n        \"PACKAGE_PIN\": \"A19\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA25_P\": {\n        \"PACKAGE_PIN\": \"D22\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA25_N\": {\n        \"PACKAGE_PIN\": \"C22\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA26_P\": {\n        \"PACKAGE_PIN\": \"F18\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA26_N\": {\n        \"PACKAGE_PIN\": \"E18\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA27_P\": {\n        \"PACKAGE_PIN\": \"E21\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA27_N\": {\n        \"PACKAGE_PIN\": \"D21\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA28_P\": {\n        \"PACKAGE_PIN\": \"A16\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA28_N\": {\n        \"PACKAGE_PIN\": \"A17\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA29_P\": {\n        \"PACKAGE_PIN\": \"C17\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA29_N\": {\n        \"PACKAGE_PIN\": \"C18\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA30_P\": {\n        \"PACKAGE_PIN\": \"C15\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA30_N\": {\n        \"PACKAGE_PIN\": \"B15\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA31_P\": {\n        \"PACKAGE_PIN\": \"B16\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA31_N\": {\n        \"PACKAGE_PIN\": \"B17\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA32_P\": {\n        \"PACKAGE_PIN\": \"A21\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA32_N\": {\n        \"PACKAGE_PIN\": \"A22\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA33_P\": {\n        \"PACKAGE_PIN\": \"B21\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"LA33_N\": {\n        \"PACKAGE_PIN\": \"B22\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"CLK0_M2C_P\": {\n        \"PACKAGE_PIN\": \"L18\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"CLK0_M2C_N\": {\n        \"PACKAGE_PIN\": \"L19\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"CLK1_M2C_P\": {\n        \"PACKAGE_PIN\": \"D18\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"CLK1_M2C_N\": {\n        \"PACKAGE_PIN\": \"C19\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"SDA\": {\n        \"PACKAGE_PIN\": \"U7\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        },\n    \"SCL\": {\n        \"PACKAGE_PIN\": \"R7\",\n        \"IOSTANDARD\": \"LVCMOS25\"\n        }\n    },\n    \"pins\": {\n\t\"GPIO_sw_left\": {\n\t    \"PACKAGE_PIN\": \"N15\",\n\t    \"IOSTANDARD\": \"LVCMOS18\",\n\t    \"slew\": \"SLOW\",\n\t    \"PIO_DIRECTION\": \"INPUT\"\n\t},\n\t\"GPIO_sw_center\": {\n\t    \"PACKAGE_PIN\": \"P16\",\n\t    \"IOSTANDARD\": \"LVCMOS18\",\n\t    \"slew\": \"SLOW\",\n\t    \"PIO_DIRECTION\": \"INPUT\"\n\t},\n\t\"GPIO_sw_right\": {\n\t    \"PACKAGE_PIN\": \"R18\",\n\t    \"IOSTANDARD\": \"LVCMOS18\",\n\t    \"slew\": \"SLOW\",\n\t    \"PIO_DIRECTION\": \"INPUT\"\n\t},\n\t\"GPIO_sw_down\": {\n\t    \"PACKAGE_PIN\": \"R16\",\n\t    \"IOSTANDARD\": \"LVCMOS18\",\n\t    \"slew\": \"SLOW\",\n\t    \"PIO_DIRECTION\": \"INPUT\"\n\t},\n\t\"GPIO_sw_up\": {\n\t    \"PACKAGE_PIN\": \"T18\",\n\t    \"IOSTANDARD\": \"LVCMOS18\",\n\t    \"slew\": \"SLOW\",\n\t    \"PIO_DIRECTION\": \"INPUT\"\n\t}\n    },\n    \"pmoda\" : {\n        \"J1\" : {\n             \"PACKAGE_PIN\" : \"Y11\",\n\t     \"IOSTANDARD\" : \"LVCMOS33\"\n\t     },\n        \"J2\" : {\n             \"PACKAGE_PIN\" : \"AA11\",\n\t     \"IOSTANDARD\" : \"LVCMOS33\"\n\t     },\n        \"J3\" : {\n             \"PACKAGE_PIN\" : \"Y10\",\n\t     \"IOSTANDARD\" : \"LVCMOS33\"\n\t     },\n        \"J4\" : {\n             \"PACKAGE_PIN\" : \"AA9\",\n\t     \"IOSTANDARD\" : \"LVCMOS33\"\n\t     },\n        \"J7\" : {\n             \"PACKAGE_PIN\" : \"AB11\",\n\t     \"IOSTANDARD\" : \"LVCMOS33\"\n\t     },\n        \"J8\" : {\n             \"PACKAGE_PIN\" : \"AB10\",\n\t     \"IOSTANDARD\" : \"LVCMOS33\"\n\t     },\n        \"J9\" : {\n             \"PACKAGE_PIN\" : \"AB9\",\n\t     \"IOSTANDARD\" : \"LVCMOS33\"\n\t     },\n        \"J10\" : {\n             \"PACKAGE_PIN\" : \"AA8\",\n\t     \"IOSTANDARD\" : \"LVCMOS33\"\n\t     }\t \n    },\n    \"pmodb\" : {\n        \"J1\" : {\n             \"PACKAGE_PIN\" : \"W12\",\n\t     \"IOSTANDARD\" : \"LVCMOS33\"\n\t     },\n        \"J2\" : {\n             \"PACKAGE_PIN\" : \"W11\",\n\t     \"IOSTANDARD\" : \"LVCMOS33\"\n\t     },\n        \"J3\" : {\n             \"PACKAGE_PIN\" : \"V10\",\n\t     \"IOSTANDARD\" : \"LVCMOS33\"\n\t     },\n        \"J4\" : {\n             \"PACKAGE_PIN\" : \"W8\",\n\t     \"IOSTANDARD\" : \"LVCMOS33\"\n\t     },\n        \"J7\" : {\n             \"PACKAGE_PIN\" : \"V12\",\n\t     \"IOSTANDARD\" : \"LVCMOS33\"\n\t     },\n        \"J8\" : {\n             \"PACKAGE_PIN\" : \"W10\",\n\t     \"IOSTANDARD\" : \"LVCMOS33\"\n\t     },\n        \"J9\" : {\n             \"PACKAGE_PIN\" : \"V9\",\n\t     \"IOSTANDARD\" : \"LVCMOS33\"\n\t     },\n        \"J10\" : {\n             \"PACKAGE_PIN\" : \"V8\",\n\t     \"IOSTANDARD\" : \"LVCMOS33\"\n\t     }\t \n    },\n    \"pmodc\" : {\n        \"J1\" : {\n             \"PACKAGE_PIN\" : \"AB7\",\n\t     \"IOSTANDARD\" : \"LVCMOS33\"\n\t     },\n        \"J2\" : {\n             \"PACKAGE_PIN\" : \"AB6\",\n\t     \"IOSTANDARD\" : \"LVCMOS33\"\n\t     },\n        \"J3\" : {\n             \"PACKAGE_PIN\" : \"Y4\",\n\t     \"IOSTANDARD\" : \"LVCMOS33\"\n\t     },\n        \"J4\" : {\n             \"PACKAGE_PIN\" : \"AA4\",\n\t     \"IOSTANDARD\" : \"LVCMOS33\"\n\t     },\n        \"J7\" : {\n             \"PACKAGE_PIN\" : \"R6\",\n\t     \"IOSTANDARD\" : \"LVCMOS33\"\n\t     },\n        \"J8\" : {\n             \"PACKAGE_PIN\" : \"T6\",\n\t     \"IOSTANDARD\" : \"LVCMOS33\"\n\t     },\n        \"J9\" : {\n             \"PACKAGE_PIN\" : \"T4\",\n\t     \"IOSTANDARD\" : \"LVCMOS33\"\n\t     },\n        \"J10\" : {\n             \"PACKAGE_PIN\" : \"U4\",\n\t     \"IOSTANDARD\" : \"LVCMOS33\"\n\t     }\t \n    },\n    \"pmodd\" : {\n        \"J1\" : {\n             \"PACKAGE_PIN\" : \"V7\",\n\t     \"IOSTANDARD\" : \"LVCMOS33\"\n\t     },\n        \"J2\" : {\n             \"PACKAGE_PIN\" : \"W7\",\n\t     \"IOSTANDARD\" : \"LVCMOS33\"\n\t     },\n        \"J3\" : {\n             \"PACKAGE_PIN\" : \"V5\",\n\t     \"IOSTANDARD\" : \"LVCMOS33\"\n\t     },\n        \"J4\" : {\n             \"PACKAGE_PIN\" : \"V4\",\n\t     \"IOSTANDARD\" : \"LVCMOS33\"\n\t     },\n        \"J7\" : {\n             \"PACKAGE_PIN\" : \"W6\",\n\t     \"IOSTANDARD\" : \"LVCMOS33\"\n\t     },\n        \"J8\" : {\n             \"PACKAGE_PIN\" : \"W5\",\n\t     \"IOSTANDARD\" : \"LVCMOS33\"\n\t     },\n        \"J9\" : {\n             \"PACKAGE_PIN\" : \"U6\",\n\t     \"IOSTANDARD\" : \"LVCMOS33\"\n\t     },\n        \"J10\" : {\n             \"PACKAGE_PIN\" : \"U5\",\n\t     \"IOSTANDARD\" : \"LVCMOS33\"\n\t     }\t \n    },\n    \"pmode_documentation_only;cannot use from PL\" : {\n        \"MIO13\" : {\n             \"PACKAGE_PIN\" : \"A6\",\n\t     \"CONNECTORPIN\" : \"JE1\"\n\t     },\n        \"MIO10\" : {\n             \"PACKAGE_PIN\" : \"G7\",\n\t     \"CONNECTORPIN\" : \"JE2\"\n\t     },\n        \"MIO11\" : {\n             \"PACKAGE_PIN\" : \"B4\",\n\t     \"CONNECTORPIN\" : \"JE3\"\n\t     },\n        \"MIO12\" : {\n             \"PACKAGE_PIN\" : \"C5\",\n\t     \"CONNECTORPIN\" : \"JE4\"\n\t     },\n        \"MIO0\" : {\n             \"PACKAGE_PIN\" : \"G6\",\n\t     \"CONNECTORPIN\" : \"JE7\"\n\t     },\n        \"MIO9\" : {\n             \"PACKAGE_PIN\" : \"C4\",\n\t     \"CONNECTORPIN\" : \"JE8\"\n\t     },\n        \"MIO14\" : {\n             \"PACKAGE_PIN\" : \"B6\",\n\t     \"CONNECTORPIN\" : \"JE9\"\n\t     },\n        \"MIO15\" : {\n             \"PACKAGE_PIN\" : \"E6\",\n\t     \"CONNECTORPIN\" : \"JE10\"\n\t     }\n    },\n    \"leds\" : {\n    \t\"L0\" : {\n\t     \"PACKAGE_PIN\" : \"T22\",\n             \"IOSTANDARD\" : \"LVCMOS25\",\n\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t     },\n    \t\"L1\" : {\n\t     \"PACKAGE_PIN\" : \"T21\",\n             \"IOSTANDARD\" : \"LVCMOS25\",\n\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t     },\n    \t\"L2\" : {\n\t     \"PACKAGE_PIN\" : \"U22\",\n             \"IOSTANDARD\" : \"LVCMOS25\",\n\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t     },\n    \t\"L3\" : {\n\t     \"PACKAGE_PIN\" : \"U21\",\n             \"IOSTANDARD\" : \"LVCMOS25\",\n\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t     },\n    \t\"L4\" : {\n\t     \"PACKAGE_PIN\" : \"V22\",\n             \"IOSTANDARD\" : \"LVCMOS25\",\n\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t     },\n    \t\"L5\" : {\n\t     \"PACKAGE_PIN\" : \"W22\",\n             \"IOSTANDARD\" : \"LVCMOS25\",\n\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t     },\n    \t\"L6\" : {\n\t     \"PACKAGE_PIN\" : \"U19\",\n             \"IOSTANDARD\" : \"LVCMOS25\",\n\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t     },\n    \t\"L7\" : {\n\t     \"PACKAGE_PIN\" : \"U14\",\n             \"IOSTANDARD\" : \"LVCMOS25\",\n\t     \"PIO_DIRECTION\" : \"OUTPUT\"\n\t     }\n    },  \n    \"i2c0\" : {\n        \"scl\" : {\n             \"PACKAGE_PIN\" : \"AA18\",\n\t     \"IOSTANDARD\" : \"LVCMOS25\",\n\t     \"PIO_DIRECTION\": \"BIDIR\"\n\t     },\n        \"sda\" : {\n             \"PACKAGE_PIN\" : \"Y16\",\n\t     \"IOSTANDARD\" : \"LVCMOS25\",\n\t     \"PIO_DIRECTION\": \"BIDIR\"\n\t     }\t \n    },\n    \"hdmi\" : {\n        \"clock\" : {\n             \"PACKAGE_PIN\" : \"W18\",\n\t     \"IOSTANDARD\" : \"LVCMOS25\",\n             \"PIO_DIRECTION\": \"OUTPUT\"\n\t     },\n        \"hsync\" : {\n             \"PACKAGE_PIN\" : \"V17\",\n\t     \"IOSTANDARD\" : \"LVCMOS25\",\n             \"PIO_DIRECTION\": \"OUTPUT\"\n\t     },\n        \"vsync\" : {\n             \"PACKAGE_PIN\" : \"W17\",\n\t     \"IOSTANDARD\" : \"LVCMOS25\",\n             \"PIO_DIRECTION\": \"OUTPUT\"\n\t     },\n        \"de\" : {\n             \"PACKAGE_PIN\" : \"U16\",\n\t     \"IOSTANDARD\" : \"LVCMOS25\",\n             \"PIO_DIRECTION\": \"OUTPUT\"\n\t     },\n        \"data[0]\" : {\n             \"PACKAGE_PIN\" : \"Y13\",\n\t     \"IOSTANDARD\" : \"LVCMOS25\",\n             \"PIO_DIRECTION\": \"OUTPUT\"\n\t     },\n        \"data[1]\" : {\n             \"PACKAGE_PIN\" : \"AA13\",\n\t     \"IOSTANDARD\" : \"LVCMOS25\",\n             \"PIO_DIRECTION\": \"OUTPUT\"\n\t     },\n        \"data[2]\" : {\n             \"PACKAGE_PIN\" : \"AA14\",\n\t     \"IOSTANDARD\" : \"LVCMOS25\",\n             \"PIO_DIRECTION\": \"OUTPUT\"\n\t     },\n        \"data[3]\" : {\n             \"PACKAGE_PIN\" : \"Y14\",\n\t     \"IOSTANDARD\" : \"LVCMOS25\",\n             \"PIO_DIRECTION\": \"OUTPUT\"\n\t     },\n        \"data[4]\" : {\n             \"PACKAGE_PIN\" : \"AB15\",\n\t     \"IOSTANDARD\" : \"LVCMOS25\",\n             \"PIO_DIRECTION\": \"OUTPUT\"\n\t     },\n        \"data[5]\" : {\n             \"PACKAGE_PIN\" : \"AB16\",\n\t     \"IOSTANDARD\" : \"LVCMOS25\",\n             \"PIO_DIRECTION\": \"OUTPUT\"\n\t     },\n        \"data[6]\" : {\n             \"PACKAGE_PIN\" : \"AA16\",\n\t     \"IOSTANDARD\" : \"LVCMOS25\",\n             \"PIO_DIRECTION\": \"OUTPUT\"\n\t     },\n        \"data[7]\" : {\n             \"PACKAGE_PIN\" : \"AB17\",\n\t     \"IOSTANDARD\" : \"LVCMOS25\",\n             \"PIO_DIRECTION\": \"OUTPUT\"\n\t     },\n        \"data[8]\" : {\n             \"PACKAGE_PIN\" : \"AA17\",\n\t     \"IOSTANDARD\" : \"LVCMOS25\",\n             \"PIO_DIRECTION\": \"OUTPUT\"\n\t     },\n        \"data[9]\" : {\n             \"PACKAGE_PIN\" : \"Y15\",\n\t     \"IOSTANDARD\" : \"LVCMOS25\",\n             \"PIO_DIRECTION\": \"OUTPUT\"\n\t     },\n        \"data[10]\" : {\n             \"PACKAGE_PIN\" : \"W13\",\n\t     \"IOSTANDARD\" : \"LVCMOS25\",\n             \"PIO_DIRECTION\": \"OUTPUT\"\n\t     },\n        \"data[11]\" : {\n             \"PACKAGE_PIN\" : \"W15\",\n\t     \"IOSTANDARD\" : \"LVCMOS25\",\n             \"PIO_DIRECTION\": \"OUTPUT\"\n\t     },\n        \"data[12]\" : {\n             \"PACKAGE_PIN\" : \"V15\",\n\t     \"IOSTANDARD\" : \"LVCMOS25\",\n             \"PIO_DIRECTION\": \"OUTPUT\"\n\t     },\n        \"data[13]\" : {\n             \"PACKAGE_PIN\" : \"U17\",\n\t     \"IOSTANDARD\" : \"LVCMOS25\",\n             \"PIO_DIRECTION\": \"OUTPUT\"\n\t     },\n        \"data[14]\" : {\n             \"PACKAGE_PIN\" : \"V14\",\n\t     \"IOSTANDARD\" : \"LVCMOS25\",\n             \"PIO_DIRECTION\": \"OUTPUT\"\n\t     },\n        \"data[15]\" : {\n             \"PACKAGE_PIN\" : \"V13\",\n\t     \"IOSTANDARD\" : \"LVCMOS25\",\n             \"PIO_DIRECTION\": \"OUTPUT\"\n\t     }\n    }\n}\n"
  },
  {
    "path": "boardinfo/zybo.json",
    "content": "{\n    \"options\": {\n        \"bsvdefines\" : [\"XILINX=1\", \"ZYNQ\", \"ZynqHostInterface\", \"PhysAddrWidth=32\", \"NUMBER_OF_LEDS=4\",\n\t\t\t\"CONNECTAL_BITS_DEPENDENCES=hw/mkTop.bit\", \"CONNECTAL_RUN_SCRIPT=$(CONNECTALDIR)/scripts/run.android\",\n\t\t\t\"CONNECTAL_EXENAME=android.exe\", \"CONNECTAL_EXENAME2=android.exe2\"],\n        \"os\" : \"android\",\n        \"partname\" : \"xc7z010clg400-1\",\n        \"rewireclockstring\" : \"tclzynqrewireclock\",\n        \"constraints\": [],\n        \"implconstraints\": [\"constraints/xilinx/xc7z010clg400.xdc\", \"constraints/xilinx/zybo.xdc\"],\n        \"TOP\" : \"ZynqTop\",\n        \"runscript\" : \"run.android\",\n        \"CONNECTALFLAGS\" : [\"--mainclockperiod=10\", \"--derivedclockperiod=5\"],\n        \"need_pcie\" : \"unused\"\n    },\n    \"pins\": {\n\t\"GPIO_sw_left\": {\n\t    \"PACKAGE_PIN\": \"R18\",\n\t    \"IOSTANDARD\": \"LVCMOS18\",\n\t    \"slew\": \"SLOW\",\n\t    \"PIO_DIRECTION\": \"INPUT\"\n\t},\n\t\"GPIO_sw_center\": {\n\t    \"PACKAGE_PIN\": \"P16\",\n\t    \"IOSTANDARD\": \"LVCMOS18\",\n\t    \"slew\": \"SLOW\",\n\t    \"PIO_DIRECTION\": \"INPUT\"\n\t},\n\t\"GPIO_sw_right\": {\n\t    \"PACKAGE_PIN\": \"V16\",\n\t    \"IOSTANDARD\": \"LVCMOS18\",\n\t    \"slew\": \"SLOW\",\n\t    \"PIO_DIRECTION\": \"INPUT\"\n\t},\n\t\"GPIO_sw_down\": {\n\t    \"PACKAGE_PIN\": \"Y16\",\n\t    \"IOSTANDARD\": \"LVCMOS18\",\n\t    \"slew\": \"SLOW\",\n\t    \"PIO_DIRECTION\": \"INPUT\"\n\t},\n\t\"GPIO_sw_up\": {\n\t    \"PACKAGE_PIN\": \"T18\",\n\t    \"IOSTANDARD\": \"LVCMOS18\",\n\t    \"slew\": \"SLOW\",\n\t    \"PIO_DIRECTION\": \"INPUT\"\n\t}\n    },\n    \"pmoda\" : {\n        \"J1\" : {\n             \"LOC\" : \"N15\",\n\t     \"IOSTANDARD\" : \"LVCMOS33\"\n\t     },\n        \"J2\" : {\n             \"LOC\" : \"L14\",\n\t     \"IOSTANDARD\" : \"LVCMOS33\"\n\t     },\n        \"J3\" : {\n             \"LOC\" : \"K16\",\n\t     \"IOSTANDARD\" : \"LVCMOS33\"\n\t     },\n        \"J4\" : {\n             \"LOC\" : \"K14\",\n\t     \"IOSTANDARD\" : \"LVCMOS33\"\n\t     },\n        \"J7\" : {\n             \"LOC\" : \"N16\",\n\t     \"IOSTANDARD\" : \"LVCMOS33\"\n\t     },\n        \"J8\" : {\n             \"LOC\" : \"L15\",\n\t     \"IOSTANDARD\" : \"LVCMOS33\"\n\t     },\n        \"J9\" : {\n             \"LOC\" : \"J16\",\n\t     \"IOSTANDARD\" : \"LVCMOS33\"\n\t     },\n        \"J10\" : {\n             \"LOC\" : \"J14\",\n\t     \"IOSTANDARD\" : \"LVCMOS33\"\n\t     }\n    },\n    \"pmodb\" : {\n        \"J1\" : {\n             \"LOC\" : \"T20\",\n\t     \"IOSTANDARD\" : \"LVCMOS33\"\n\t     },\n        \"J2\" : {\n             \"LOC\" : \"U20\",\n\t     \"IOSTANDARD\" : \"LVCMOS33\"\n\t     },\n        \"J3\" : {\n             \"LOC\" : \"V20\",\n\t     \"IOSTANDARD\" : \"LVCMOS33\"\n\t     },\n        \"J4\" : {\n             \"LOC\" : \"W20\",\n\t     \"IOSTANDARD\" : \"LVCMOS33\"\n\t     },\n        \"J7\" : {\n             \"LOC\" : \"Y18\",\n\t     \"IOSTANDARD\" : \"LVCMOS33\"\n\t     },\n        \"J8\" : {\n             \"LOC\" : \"Y19\",\n\t     \"IOSTANDARD\" : \"LVCMOS33\"\n\t     },\n        \"J9\" : {\n             \"LOC\" : \"W18\",\n\t     \"IOSTANDARD\" : \"LVCMOS33\"\n\t     },\n        \"J10\" : {\n             \"LOC\" : \"W19\",\n\t     \"IOSTANDARD\" : \"LVCMOS33\"\n\t     }\n    },\n    \"pmodc\" : {\n        \"J1\" : {\n             \"LOC\" : \"V15\",\n\t     \"IOSTANDARD\" : \"LVCMOS33\"\n\t     },\n        \"J2\" : {\n             \"LOC\" : \"W15\",\n\t     \"IOSTANDARD\" : \"LVCMOS33\"\n\t     },\n        \"J3\" : {\n             \"LOC\" : \"T11\",\n\t     \"IOSTANDARD\" : \"LVCMOS33\"\n\t     },\n        \"J4\" : {\n             \"LOC\" : \"T10\",\n\t     \"IOSTANDARD\" : \"LVCMOS33\"\n\t     },\n        \"J7\" : {\n             \"LOC\" : \"W14\",\n\t     \"IOSTANDARD\" : \"LVCMOS33\"\n\t     },\n        \"J8\" : {\n             \"LOC\" : \"Y14\",\n\t     \"IOSTANDARD\" : \"LVCMOS33\"\n\t     },\n        \"J9\" : {\n             \"LOC\" : \"T12\",\n\t     \"IOSTANDARD\" : \"LVCMOS33\"\n\t     },\n        \"J10\" : {\n             \"LOC\" : \"U12\",\n\t     \"IOSTANDARD\" : \"LVCMOS33\"\n\t     }\n    },\n    \"pmodd\" : {\n        \"J1\" : {\n             \"LOC\" : \"T14\",\n\t     \"IOSTANDARD\" : \"LVCMOS33\"\n\t     },\n        \"J2\" : {\n             \"LOC\" : \"T15\",\n\t     \"IOSTANDARD\" : \"LVCMOS33\"\n\t     },\n        \"J3\" : {\n             \"LOC\" : \"P14\",\n\t     \"IOSTANDARD\" : \"LVCMOS33\"\n\t     },\n        \"J4\" : {\n             \"LOC\" : \"R14\",\n\t     \"IOSTANDARD\" : \"LVCMOS33\"\n\t     },\n        \"J7\" : {\n             \"LOC\" : \"U14\",\n\t     \"IOSTANDARD\" : \"LVCMOS33\"\n\t     },\n        \"J8\" : {\n             \"LOC\" : \"U15\",\n\t     \"IOSTANDARD\" : \"LVCMOS33\"\n\t     },\n        \"J9\" : {\n             \"LOC\" : \"V17\",\n\t     \"IOSTANDARD\" : \"LVCMOS33\"\n\t     },\n        \"J10\" : {\n             \"LOC\" : \"V18\",\n\t     \"IOSTANDARD\" : \"LVCMOS33\"\n\t     }\n    },\n    \"pmode\" : {\n        \"J1\" : {\n             \"LOC\" : \"V12\",\n\t     \"IOSTANDARD\" : \"LVCMOS33\"\n\t     },\n        \"J2\" : {\n             \"LOC\" : \"W16\",\n\t     \"IOSTANDARD\" : \"LVCMOS33\"\n\t     },\n        \"J3\" : {\n             \"LOC\" : \"J15\",\n\t     \"IOSTANDARD\" : \"LVCMOS33\"\n\t     },\n        \"J4\" : {\n             \"LOC\" : \"H15\",\n\t     \"IOSTANDARD\" : \"LVCMOS33\"\n\t     },\n        \"J7\" : {\n             \"LOC\" : \"V13\",\n\t     \"IOSTANDARD\" : \"LVCMOS33\"\n\t     },\n        \"J8\" : {\n             \"LOC\" : \"U17\",\n\t     \"IOSTANDARD\" : \"LVCMOS33\"\n\t     },\n        \"J9\" : {\n             \"LOC\" : \"T17\",\n\t     \"IOSTANDARD\" : \"LVCMOS33\"\n\t     },\n        \"J10\" : {\n             \"LOC\" : \"Y17\",\n\t     \"IOSTANDARD\" : \"LVCMOS33\"\n\t     }\n    },\n    \"pmodf_mio_documentation\" : {\n        \"J1\" : {\n             \"LOC\" : \"E8\",\n\t     \"MIO\" : \"MIO13\"\n\t     },\n        \"J2\" : {\n             \"LOC\" : \"E9\",\n\t     \"MIO\" : \"MIO10\"\n\t     },\n        \"J3\" : {\n             \"LOC\" : \"C6\",\n\t     \"MIO\" : \"MIO11\"\n\t     },\n        \"J4\" : {\n             \"LOC\" : \"D9\",\n\t     \"MIO\" : \"MIO12\"\n\t     },\n        \"J7\" : {\n             \"LOC\" : \"E6\",\n\t     \"MIO\" : \"MIO0\"\n\t     },\n        \"J8\" : {\n             \"LOC\" : \"B5\",\n\t     \"MIO\" : \"MIO9\"\n\t     },\n        \"J9\" : {\n             \"LOC\" : \"C5\",\n\t     \"MIO\" : \"MIO14\"\n\t     },\n        \"J10\" : {\n             \"LOC\" : \"C8\",\n\t     \"MIO\" : \"MIO15\"\n\t     }\n    }\n}\n"
  },
  {
    "path": "boardinfo/zynq100.json",
    "content": "{\n    \"options\": {\n        \"os\" : \"android\",\n        \"partname\" : \"xc7z100ffg900-2\",\n        \"rewireclockstring\" : \"tclzynqrewireclock\",\n        \"constraints\": [],\n        \"implconstraints\": [\"constraints/xilinx/xc7z045ffg900.xdc\", \"constraints/xilinx/zynq100.xdc\",\n\t\t\t\"CONNECTAL_BITS_DEPENDENCES=hw/mkTop.bit\", \"CONNECTAL_RUN_SCRIPT=$(CONNECTALDIR)/scripts/run.android\",\n\t\t\t\"CONNECTAL_EXENAME=android.exe\", \"CONNECTAL_EXENAME2=android.exe2\"],\n        \"TOP\" : \"ZynqTop\",\n        \"runscript\" : \"run.android\",\n        \"bsvdefines\" : [\"XILINX=1\", \"ZYNQ\", \"ZynqHostInterface\", \"PhysAddrWidth=40\"],\n\t\"CONNECTALFLAGS\" : [],\n        \"need_pcie\" : \"unused\"\n    },\n    \"fmc\": {\n    }\n}\n"
  },
  {
    "path": "bsv/Adapter.bsv",
    "content": "\n// Copyright (c) 2012 MIT\n// Copyright (c) 2012 Nokia, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\nimport GetPut         ::*;\nimport FIFOF          ::*;\nimport SpecialFIFOs   ::*;\nimport StmtFSM        ::*;\nimport Assert         ::*;\nimport Pipe           ::*;\n\nfunction Bit#(a) rtruncate(Bit#(b) x) provisos(Add#(k,a,b));\n   match {.v,.*} = split(x);\n   return v;\nendfunction\n\ninterface AdapterToBus#(numeric type n, type a);\n   interface PipeIn#(a) in;\n   interface PipeOut#(Bit#(n)) out;\nendinterface\n   \ninterface AdapterFromBus#(numeric type n, type a);\n   interface PipeIn#(Bit#(n)) in;\n   interface PipeOut#(a) out;\nendinterface\n\nmodule mkAdapterToBus(AdapterToBus#(n,a))\n   provisos(Bits#(a,asz),\n            Add#(1, z, asz),\n            Div#(asz,n,nwords),\n            Mul#(n,nwords,aszn),\n            Add#(n,a__,aszn),\n            Add#(asz,paddingsz,aszn));\n   \n   Bit#(TLog#(nwords)) max  = fromInteger(valueOf(nwords) - 1);\n   Bit#(paddingsz) padding = 0;\n\n   Reg#(Bool) notEmptyReg <- mkReg(False);\n   Reg#(Bit#(aszn)) bits <- mkReg(0);\n   Reg#(Bit#(TLog#(nwords)))   count <- mkReg(0);\n   Reg#(Bit#(TAdd#(TLog#(asz),1)))   shift <- mkReg(0);\n\n   interface PipeIn in;\n      method Action enq(a val) if (!notEmptyReg);\n         bits <= {padding,pack(val)};\n\t notEmptyReg <= True;\n      endmethod\n      method notFull = !notEmptyReg;\n   endinterface\n   interface PipeOut out;\n      method Bit#(n) first() if (notEmptyReg);\n         return rtruncate(bits);\n      endmethod\n      method Action deq() if (notEmptyReg);\n         if (count == max)\n            begin \n               count <= 0;\n\t       notEmptyReg <= False;\n            end\n         else\n            begin\n               count <= count + 1;\n\t       shift <= shift + fromInteger(valueOf(n));\n\t       bits <= (bits << valueOf(n));\n            end   \n      endmethod\n      method notEmpty = notEmptyReg;\n   endinterface\nendmodule\n\nmodule mkAdapterFromBus(AdapterFromBus#(n,a))\n   provisos(Bits#(a,asz),\n            Add#(1,z,asz),\n            Div#(asz,n,nwords),\n            Mul#(n,nwords,aszn),\n            Add#(n,a__,aszn),\n            Add#(asz,paddingsz,aszn));\n\n   Bit#(TLog#(nwords)) max    = fromInteger(valueOf(nwords)-1);\n\n   Reg#(Bit#(aszn)) fbnbuff <- mkReg(0);\n   Reg#(Bit#(TLog#(nwords)))    count <- mkReg(0);\n   FIFOF#(Bit#(asz)) fifo <- mkFIFOF1;\n\n   interface PipeIn in;\n      method Action enq(Bit#(n) x) if (count < max || fifo.notFull);\n         Bit#(aszn) newbuff = truncate({fbnbuff,x});\n         fbnbuff <= newbuff;\n         if (count == max)\n            begin\n               count <= 0;\n               fifo.enq(truncate(newbuff));\n            end\n         else\n            begin\n               count <= count+1;\n            end\n      endmethod\n      method notFull = fifo.notFull;\n   endinterface\n   interface PipeOut out;\n      method first = unpack(fifo.first);\n      method deq = fifo.deq;\n      method notEmpty = fifo.notEmpty;\n   endinterface\nendmodule\n\ninterface AdapterIndication;\n   method Action done();\nendinterface\n\ninterface AdapterTb;\n   method Action start();\nendinterface\n\nmodule mkAdapterTb#(AdapterIndication indication)(AdapterTb);\n   AdapterToBus#(32,Bit#(72)) tb32_72 <- mkAdapterToBus();\n   AdapterToBus#(32,Bit#(17)) tb32_17 <- mkAdapterToBus();\n   AdapterFromBus#(32,Bit#(72)) fb32_72 <- mkAdapterFromBus();\n   AdapterFromBus#(32,Bit#(17)) fb32_17 <- mkAdapterFromBus();\n   \n   Reg#(Bit#(10)) timer <- mkReg(0);\n   rule timeout;\n       timer <= timer+1;\n       dynamicAssert(timer < 128, \"Timeout\");\n   endrule\n\n   let fsm <- mkFSM(\n      seq\n       // test to bit-32\n       tb32_72.in.enq(72'h090807060504030201);\n       dynamicAssert(tb32_72.out.notEmpty, \"Adapter not empty\");\n       dynamicAssert(!tb32_72.in.notFull, \"Adapter full\");\n       $display(\"tb32_72 notEmpty %d notFull %d\", tb32_72.out.notEmpty, tb32_72.in.notFull);\n       $display(\"tb32_72 word 0 %h\", tb32_72.out.first());\n       dynamicAssert(tb32_72.out.first == 32'h00000009, \"expecting 00000009\");\n       tb32_72.out.deq;\n       $display(\"tb32_72 word 1 %h\", tb32_72.out.first());\n       dynamicAssert(tb32_72.out.first == 32'h08070605, \"expecting 08070605\");\n       tb32_72.out.deq;\n       $display(\"tb32_72 word 2 %h\", tb32_72.out.first());\n       dynamicAssert(tb32_72.out.first == 32'h04030201, \"expecting 04030201\");\n       tb32_72.out.deq;\n       dynamicAssert(!tb32_72.out.notEmpty && tb32_72.in.notFull, \"Adapter empty and not full\");\n       $display(\"tb32_72 notEmpty %d notFull %d\", tb32_72.out.notEmpty, tb32_72.in.notFull);\n       dynamicAssert(!tb32_17.out.notEmpty, \"tb32_17 empty\");\n       dynamicAssert(tb32_17.in.notFull, \"tb32_17 !full\");\n       tb32_17.in.enq(17'h10203);\n       dynamicAssert(tb32_17.out.notEmpty, \"tb32_17 not empty\");\n       dynamicAssert(!tb32_17.in.notFull, \"tb32_17 full\");\n       $display(\"tb32_17.out.first %h\", tb32_17.out.first);\n       dynamicAssert(tb32_17.out.first == (32'h00010203), \"Expected 00010203\");\n       tb32_17.out.deq;\n       dynamicAssert(!tb32_17.out.notEmpty, \"tb32_17 empty\");\n       dynamicAssert(tb32_17.in.notFull, \"tb32_17 !full\");\n\n       //test from bit-32\n       dynamicAssert(!fb32_72.out.notEmpty, \"Adapter empty\");\n       dynamicAssert(fb32_72.in.notFull, \"Adapter not full\");\n       $display(\"fb32_72 notEmpty %d notFull %d\", fb32_72.out.notEmpty, fb32_72.in.notFull);\n       fb32_72.in.enq(32'h00000009);\n       fb32_72.in.enq(32'h08070605);\n       fb32_72.in.enq(32'h04030201);\n       $display(\"fb32_72.out.first %h\", fb32_72.out.first);\n       dynamicAssert(fb32_72.out.first == 72'h090807060504030201, \"Expected 090807060504030201\");\n       fb32_72.out.deq;\n       fb32_72.in.enq(32'h09080706);\n       dynamicAssert(!fb32_72.out.notEmpty, \"Adapter not empty\");\n       dynamicAssert(fb32_72.in.notFull, \"Adapter not full\");\n       fb32_72.in.enq(32'h05040302);\n       fb32_72.in.enq(32'h01000000);\n       dynamicAssert(fb32_72.out.notEmpty, \"Adapter not empty\");\n       dynamicAssert(!fb32_72.in.notFull, \"Adapter full\");\n       $display(\"fb32_72.out.first %h\", fb32_72.out.first);\n       dynamicAssert(fb32_72.out.first == 72'h060504030201000000, \"Expected 060504030201000000\");\n       fb32_72.out.deq;\n       $display(\"fb32_72 notEmpty %d notFull %d\", fb32_72.out.notEmpty, fb32_72.in.notFull);\n       dynamicAssert(!fb32_72.out.notEmpty, \"Adapter empty\");\n       dynamicAssert(fb32_72.in.notFull, \"Adapter not full\");\n       fb32_17.in.enq(32'h10203);\n       dynamicAssert(fb32_17.out.notEmpty, \"Adapter not empty\");\n       dynamicAssert(!fb32_17.in.notFull, \"Adapter full\");\n       $display(\"fb32_17.out.first %h\", fb32_17.out.first);\n       dynamicAssert(fb32_17.out.first == 17'h10203, \"Expected 10203\");\n       fb32_17.out.deq;\n       dynamicAssert(!fb32_17.out.notEmpty, \"Adapter empty\");\n       dynamicAssert(fb32_17.in.notFull, \"Adapter not full\");\n\n\n       // they should be duals\n       tb32_72.in.enq(72'h090807060504030201);\n       fb32_72.in.enq(tb32_72.out.first);\n       tb32_72.out.deq;\n       fb32_72.in.enq(tb32_72.out.first);\n       tb32_72.out.deq;\n       fb32_72.in.enq(tb32_72.out.first);\n       tb32_72.out.deq;\n       dynamicAssert(fb32_72.out.first == 72'h090807060504030201, \"Expected 090807060504030201\");\n       fb32_72.out.deq;\n             \n       tb32_17.in.enq(17'h10203);\n       fb32_17.in.enq(tb32_17.out.first);\n       tb32_17.out.deq;\n       dynamicAssert(fb32_17.out.first == 17'h10203, \"Expected 10203\");\n       fb32_17.out.deq;\n       \t     \n       indication.done();\n   endseq\n   );\n\n   method Action start();\n       fsm.start();\n   endmethod\nendmodule\n"
  },
  {
    "path": "bsv/AddressGenerator.bsv",
    "content": "// Copyright (c) 2013 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\nimport FIFOF::*;\nimport FIFO::*;\nimport GetPut::*;\nimport Connectable::*;\nimport RegFile::*;\nimport ConnectalMemTypes::*;\nimport ConnectalConfig::*;\n\ntypedef struct {\n   Bit#(addrWidth) addr;\n   Bit#(BurstLenSize) bc;\n   Bit#(MemTagSize) tag;\n   Bool    last;\n   } AddrBeat#(numeric type addrWidth) deriving (Bits);\n\ninterface AddressGenerator#(numeric type addrWidth, numeric type dataWidth);\n   interface Put#(PhysMemRequest#(addrWidth,dataWidth)) request;\n   interface Get#(AddrBeat#(addrWidth)) addrBeat;\nendinterface\n\nmodule mkAddressGenerator(AddressGenerator#(addrWidth, dataWidth))\n   provisos (Div#(dataWidth,8,dataWidthBytes),\n\t     Log#(dataWidthBytes,beatShift));\n   FIFOF#(PhysMemRequest#(addrWidth,dataWidth)) requestFifo <- mkFIFOF1();\n   FIFOF#(AddrBeat#(addrWidth)) addrBeatFifo <- mkFIFOF();\n   Reg#(Bit#(addrWidth)) addrReg <- mkReg(0);\n   Reg#(Bit#(BurstLenSize)) burstCountReg <- mkReg(0);\n   Reg#(Bool) isFirstReg <- mkReg(True);\n   Reg#(Bool) isLastReg <- mkReg(False);\n\n   rule addrBeatRule;\n      let req = requestFifo.first();\n      let addr = addrReg;\n      let burstCount = burstCountReg;\n      let isLast = isLastReg;\n      if (isFirstReg) begin\n\t addr = req.addr;\n\t burstCount = req.burstLen >> valueOf(beatShift);\n\t isLast = (req.burstLen == fromInteger(valueOf(dataWidthBytes)));\n         //$display(\"addr=%h, burstCount=%h, isLast=%h\", addr, burstCount, isLast);\n      end\n\n      let nextIsLast = burstCount == 2;\n      let nextBurstCount = burstCount - 1;\n\n      addrReg <= addr + fromInteger(valueOf(dataWidthBytes));\n      burstCountReg <= nextBurstCount;\n      isLastReg <= nextIsLast;\n      Bool nextIsFirst = False;\n      if (isLast) begin\n\t requestFifo.deq();\n\t nextIsFirst = True;\n      end\n      isFirstReg <= nextIsFirst;\n\n      //$display(\"addr=%h, burstCount=%h, isLast=%h\", addr, burstCount, isLast);\n      addrBeatFifo.enq(AddrBeat { addr: addr, bc: burstCount, last: isLast, tag: req.tag});\n   endrule\n\n   interface Put request;\n      method Action put(PhysMemRequest#(addrWidth,dataWidth) req);\n\t requestFifo.enq(req);\n      endmethod\n   endinterface\n   interface Get addrBeat;\n      method ActionValue#(AddrBeat#(addrWidth)) get();\n\t addrBeatFifo.deq();\n\t return addrBeatFifo.first();\n      endmethod\n   endinterface\nendmodule\n\n\n"
  },
  {
    "path": "bsv/AsicTop.bsv",
    "content": "// Copyright (c) 2015 Connectal Project\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\nimport ConnectalConfig::*;\nimport Vector            :: *;\nimport GetPut::*;\nimport Connectable::*;\nimport Portal            :: *;\nimport Top               :: *;\nimport HostInterface     :: *;\nimport Pipe::*;\nimport CnocPortal::*;\nimport ConnectalMemTypes:: *;\nimport ConnectalMMU:: *;\nimport MemServer:: *;\nimport MMURequest::*;\nimport MMUIndication::*;\nimport MemServerIndication::*;\nimport MemServerRequest::*;\nimport SimDma::*;\nimport IfcNames::*;\nimport BuildVector::*;\nimport Top::*;\n\n`include \"ConnectalProjectConfig.bsv\"\n\ninterface AsicTop;\n   interface Vector#(TAdd#(2,NumberOfRequests), PortalMsgRequest) requests;\n   interface Vector#(TAdd#(2,NumberOfIndications), PortalMsgIndication) indications;\nendinterface\n\nmodule mkAsicTop#(Clock derivedClock, Reset derivedReset)(AsicTop);\n\n   Reg#(Bool) dumpstarted <- mkReg(False);\n   rule startdump if (!dumpstarted);\n      //$dumpfile(\"dump.vcd\");\n      //$dumpvars;\n      $display(\"AsicTop starting\");\n      dumpstarted <= True;\n   endrule\n   XsimHost host <- mkXsimHost(derivedClock, derivedReset);\n   let top <- mkCnocTop(\n`ifdef IMPORT_HOSTIF\n       host\n`else\n`ifdef IMPORT_HOST_CLOCKS // enables synthesis boundary\n       derivedClock, derivedReset\n`else\n// otherwise no params\n`endif\n`endif\n       );\n\n   MMUIndicationOutput lMMUIndicationOutput <- mkMMUIndicationOutput;\n   MMURequestInput lMMURequestInput <- mkMMURequestInput;\n   MMU#(PhysAddrWidth) lMMU <- mkMMU(0,True, lMMUIndicationOutput.ifc);\n   mkConnection(lMMURequestInput.pipes, lMMU.request);\n\n   MemServerIndicationOutput lMemServerIndicationOutput <- mkMemServerIndicationOutput;\n   MemServerRequestInput lMemServerRequestInput <- mkMemServerRequestInput;\n   MemServer#(PhysAddrWidth,DataBusWidth,NumberOfMasters) lMemServer <- mkMemServer(top.readers, top.writers, cons(lMMU,nil), lMemServerIndicationOutput.ifc);\n   mkConnection(lMemServerRequestInput.pipes, lMemServer.request);\n\n   let lMMUIndicationOutputNoc <- mkPortalMsgIndication(extend(pack(PlatformIfcNames_MMUIndicationH2S)), lMMUIndicationOutput.portalIfc.indications, lMMUIndicationOutput.portalIfc.messageSize);\n   let lMMURequestInputNoc <- mkPortalMsgRequest(extend(pack(PlatformIfcNames_MMURequestS2H)), lMMURequestInput.portalIfc.requests);\n   let lMemServerIndicationOutputNoc <- mkPortalMsgIndication(extend(pack(PlatformIfcNames_MemServerIndicationH2S)), lMemServerIndicationOutput.portalIfc.indications, lMemServerIndicationOutput.portalIfc.messageSize);\n   let lMemServerRequestInputNoc <- mkPortalMsgRequest(extend(pack(PlatformIfcNames_MemServerRequestS2H)), lMemServerRequestInput.portalIfc.requests);\n\n   interface requests = append(top.requests, vec(lMMURequestInputNoc, lMemServerRequestInputNoc));\n   interface indications = append(top.indications, vec(lMMUIndicationOutputNoc, lMemServerIndicationOutputNoc));\n   //  mapM_(mkAsicMemoryConnection, lMemServer.masters);\nendmodule\n"
  },
  {
    "path": "bsv/AvalonBits.bsv",
    "content": "// Copyright (c) 2015 Connectal Project.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\nimport Vector::*;\nimport Connectable::*;\n\ninterface AvalonMMasterBits#(numeric type addrWidth, numeric type dataWidth);\n    method Bit#(addrWidth) address();\n    method Bit#(4)     burstcount();\n    method Bit#(4)     byteenable();\n    method Bit#(1)     read();\n    method Action      readdata(Bit#(dataWidth) v);\n    method Action      readdatavalid(Bit#(1) v);\n    method Action      waitrequest(Bit#(1) v);\n    method Bit#(1)     write();\n    method Bit#(dataWidth) writedata();\nendinterface\n\ninterface AvalonMSlaveBits#(numeric type addrWidth, numeric type dataWidth);\n    method Action      address(Bit#(addrWidth) v);\n    method Action      burstcount(Bit#(4) v);\n    method Action      byteenable(Bit#(4) v);\n    method Action      read(Bit#(1) v);\n    method Bit#(dataWidth) readdata();\n    method Bit#(1)     readdatavalid();\n    method Bit#(1)     waitrequest();\n    method Action      write(Bit#(1) v);\n    method Action      writedata(Bit#(dataWidth) v);\nendinterface\n\ninstance Connectable#(AvalonMMasterBits#(addrWidth, dataWidth), AvalonMSlaveBits#(addrWidth, dataWidth));\n   module mkConnection#(AvalonMMasterBits#(addrWidth, dataWidth) m, AvalonMSlaveBits#(addrWidth, dataWidth) s)(Empty);\n      mkConnection(s.address, m.address);\n      mkConnection(s.burstcount, m.burstcount);\n      mkConnection(s.byteenable, m.byteenable);\n      mkConnection(s.read, m.read);\n      mkConnection(s.write, m.write);\n      mkConnection(s.writedata, m.writedata);\n      mkConnection(m.readdata, s.readdata);\n      mkConnection(m.readdatavalid, s.readdatavalid);\n      mkConnection(m.waitrequest, s.waitrequest);\n   endmodule\nendinstance\n"
  },
  {
    "path": "bsv/AvalonDdr3Controller.bsv",
    "content": "// Copyright (c) 2015 Connectal Project\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\nimport Clocks          ::*;\nimport GetPut          ::*;\nimport ClientServer    ::*;\nimport ConnectalClocks ::*;\nimport ALTERA_DDR3_WRAPPER::*;\n`include \"ConnectalProjectConfig.bsv\"\n\ntypedef 25 Ddr3AddrWidth;\ntypedef 512 Ddr3DataWidth;\n\ninterface Ddr3Pins;\n   (* prefix=\"\" *)\n   interface Ddr3 ddr3;\n   method Action osc_50(Bit#(1) b3d, Bit#(1) b4a, Bit#(1) b4d, Bit#(1) b7a, Bit#(1) b7d, Bit#(1) b8a, Bit#(1) b8d);\nendinterface\n\ninterface Ddr3;\n   interface Avalonddr3Mem ddr3b;\n   (* prefix=\"\" *)\n   interface Avalonddr3Oct rzq_4;\n   interface Clock sysclk_deleteme_unused_clock;\n   interface Reset sysrst_deleteme_unused_reset;\nendinterface\n\n(* synthesize *)\nmodule mkDdr3#(Clock clk50)(Ddr3);\n   let clock <- exposeCurrentClock();\n   let reset <- exposeCurrentReset();\n\n   Reset rst50 <- mkAsyncReset( 10, reset, clk50 );\n\n   AvalonDdr3 mc <- mkAvalonDdr3(clk50, reset, noReset);\n\n   interface ddr3b = mc.mem;\n   interface rzq_4 = mc.oct;\n   interface sysclk_deleteme_unused_clock = clock; //fixme\n   interface sysrst_deleteme_unused_reset = reset; //fixme\nendmodule\n"
  },
  {
    "path": "bsv/AvalonDma.bsv",
    "content": "// Copyright (c) 2015 Connectal Project.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n`include \"ConnectalProjectConfig.bsv\"\nimport ConnectalConfig::*;\nimport FIFO::*;\nimport GetPut::*;\nimport Vector::*;\nimport ClientServer::*;\nimport ConnectalMemTypes::*;\nimport ConnectalMemory::*;\nimport AvalonMasterSlave::*;\nimport AvalonBits::*;\nimport AddressGenerator::*;\nimport AvalonSplitter::*;\nimport Connectable::*;\n\nmodule mkAvalonDmaMaster#(PhysMemMaster#(addrWidth,dataWidth) master)(AvalonMMaster#(addrWidth,dataWidth));\n\n   let verbose = True;\n   Wire#(Bool) avalonWait <- mkDWire(False);\n   Wire#(Bool) avalonRead <- mkDWire(False);\n   Wire#(Bool) avalonWrite <- mkDWire(False);\n   Wire#(Bit#(4)) burstcount <- mkDWire(0);\n   Wire#(Bit#(4)) byteEnable <- mkDWire(0);\n   Wire#(Bit#(dataWidth)) avalonReadData <- mkDWire(0);\n   Wire#(Bool) avalonReadDataValid <- mkDWire(False);\n   Wire#(Bit#(addrWidth)) avalonAddress <- mkDWire(0);\n   Wire#(Bit#(dataWidth)) avalonWriteData <- mkDWire(0);\n\n   Reg#(Bit#(addrWidth)) writeAddress <- mkReg(0);\n   Reg#(Bit#(4)) writeBurstLen <- mkReg(0);\n   Reg#(Bit#(4)) writeBurstCount <- mkReg(0);\n\n   AddressGenerator#(addrWidth, dataWidth) readAddrGenerator <- mkAddressGenerator();\n\n   Reg#(Bit#(32)) cycles <- mkReg(0);\n   rule count;\n      cycles <= cycles + 1;\n   endrule\n\n   AvalonArbiter#(addrWidth, dataWidth) arbiter <- mkAvalonArbiter();\n   Vector#(2, FIFO#(AvalonMMRequest#(addrWidth, dataWidth))) req_fifo <- replicateM(mkFIFO);\n   mapM(uncurry(mkConnection), zip(map(toGet, req_fifo), arbiter.in));\n\n   FIFO#(AvalonMMData#(dataWidth)) resp_fifo <- mkFIFO;\n\n   rule deq_dispatcher;\n      let req <- toGet(resp_fifo).get;\n      $display(\"%d: dispatcher to avalon %h\", cycles, req.readdata);\n   endrule\n\n   rule read_req;\n      let req <- master.read_client.readReq.get;\n      AvalonMMRequest#(addrWidth, dataWidth) readReq;\n      readReq.address = req.addr;\n      readReq.data = ?;\n      readReq.write = False;\n      readReq.burstcount = truncate(req.burstLen >> 2);\n      readReq.sof = True;\n      readReq.eof = True;\n      req_fifo[0].enq(readReq);\n      if (verbose) $display(\"%d read_address %h bc %d\", cycles, req.addr, req.burstLen);\n   endrule\n\n   rule read_data if (avalonReadDataValid);\n      master.read_client.readData.put(MemData{data: avalonReadData, tag: 0, last: True});\n   endrule\n\n   rule write_req;\n      let req <- master.write_client.writeReq.get();\n      writeAddress <= req.addr;\n      writeBurstLen <= truncate(req.burstLen);\n      writeBurstCount <= truncate(req.burstLen >> 2);\n      if (verbose) $display(\"%d write_addr %h bc %d\", cycles, req.addr, req.burstLen);\n   endrule\n\n   rule write_data;\n      let data <- master.write_client.writeData.get();\n      AvalonMMRequest#(addrWidth, dataWidth) writeReq;\n      writeReq.address = writeAddress;\n      writeReq.data = data.data;\n      writeReq.write = True;\n      writeReq.burstcount = writeBurstLen;\n      writeReq.sof = (writeBurstLen == writeBurstCount) ? True : False;\n      writeReq.eof = (writeBurstCount == 0) ? True : False;\n      writeBurstCount <= writeBurstCount - 1;\n      req_fifo[1].enq(writeReq);\n      if (verbose) $display(\"%d write_data %h write_address %h bc %d\", cycles, data.data, writeAddress, writeBurstCount);\n   endrule\n\n   interface Get request = arbiter.toAvalon;\n   interface Put response = toPut(resp_fifo);\nendmodule\n\n"
  },
  {
    "path": "bsv/AvalonGather.bsv",
    "content": "// Copyright (c) 2015 Connectal Project.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\nimport FIFO::*;\nimport GetPut::*;\nimport ClientServer::*;\nimport AvalonBits::*;\nimport AvalonMasterSlave::*;\n\nmodule mkAvalonMSlaveGather#(AvalonMSlaveBits#(addrWidth, dataWidth) slave) (AvalonMSlave#(addrWidth, dataWidth));\n   Wire#(Bit#(addrWidth)) address <- mkDWire(0);\n   Wire#(Bit#(dataWidth)) readdata <- mkDWire(0);\n   Wire#(Bit#(dataWidth)) writedata <- mkDWire(0);\n   Wire#(Bit#(1)) read <- mkDWire(0);\n   Wire#(Bit#(1)) write <- mkDWire(0);\n   Wire#(Bit#(1)) readdatavalid <- mkDWire(0);\n   Wire#(Bit#(4)) burstcount <- mkDWire(0);\n   Wire#(Bit#(4)) byteenable <- mkDWire(0);\n   Wire#(Bit#(1)) waitrequest <- mkDWire(0);\n\n   FIFO#(AvalonMMRequest#(addrWidth, dataWidth)) req_fifo <- mkFIFO;\n\n   let verbose = True;\n\n   Reg#(Bit#(32)) cycles <- mkReg(0);\n   rule count if (verbose);\n      cycles <= cycles + 1;\n   endrule\n\n   rule handshake0;\n      let req = req_fifo.first;\n      address <= req.address;\n      read <= pack(!req.write);\n      write <= pack(req.write);\n      writedata <= req.data;\n      burstcount <= req.burstcount;\n      if (slave.waitrequest() == 0)\n         req_fifo.deq;\n   endrule\n\n   rule handshake1;\n      slave.address(address);\n      slave.read(read);\n      slave.write(write);\n      slave.writedata(writedata);\n      slave.burstcount(burstcount);\n   endrule\n\n   interface Put request = toPut(req_fifo);\n   interface Get response;\n      method ActionValue#(AvalonMMData#(dataWidth)) get() if (slave.readdatavalid == 1);\n         AvalonMMData#(dataWidth) d;\n         d.readdata = slave.readdata();\n         return d;\n      endmethod\n   endinterface\nendmodule\n"
  },
  {
    "path": "bsv/AvalonMasterSlave.bsv",
    "content": "// Copyright (c) 2015 Connectal Project.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\nimport GetPut::*;\nimport Connectable::*;\n\ntypedef struct {\n   Bit#(addrWidth) address;\n   Bit#(dataWidth) data;\n   Bit#(4)         burstcount;\n   Bool            write;\n   Bool            sof;\n   Bool            eof;\n} AvalonMMRequest#(numeric type addrWidth, numeric type dataWidth) deriving (Bits);\n\ntypedef struct {\n   Bit#(dataWidth) readdata;\n} AvalonMMData#(numeric type dataWidth) deriving (Bits);\n\ninterface AvalonMMaster#(numeric type addrWidth, numeric type busWidth);\n   interface Get#(AvalonMMRequest#(addrWidth, busWidth)) request;\n   interface Put#(AvalonMMData#(busWidth)) response;\nendinterface\n\ninterface AvalonMSlave#(numeric type addrWidth, numeric type busWidth);\n   interface Put#(AvalonMMRequest#(addrWidth, busWidth)) request;\n   interface Get#(AvalonMMData#(busWidth)) response;\nendinterface\n\ninstance Connectable#(AvalonMMaster#(addrWidth, dataWidth), AvalonMSlave#(addrWidth, dataWidth));\n   module mkConnection#(AvalonMMaster#(addrWidth, dataWidth) m, AvalonMSlave#(addrWidth, dataWidth) s)(Empty);\n      mkConnection(m.request, s.request);\n      mkConnection(s.response, m.response);\n   endmodule\nendinstance\n"
  },
  {
    "path": "bsv/AvalonSplitter.bsv",
    "content": "// Copyright (c) 2015 Connectal Project.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\nimport FIFO::*;\nimport FIFOF::*;\nimport GetPut::*;\nimport Vector::*;\nimport AvalonMasterSlave::*;\n\n// AvalonMM interface is shared between read and write operations.\n// There is an arbiter to control which operation get access to the Avalon Bus\n\ninterface AvalonArbiter#(numeric type addrWidth, numeric type dataWidth);\n   interface Get#(AvalonMMRequest#(addrWidth, dataWidth)) toAvalon;\n   interface Vector#(2, Put#(AvalonMMRequest#(addrWidth, dataWidth))) in;\nendinterface\n\nmodule mkAvalonArbiter(AvalonArbiter#(addrWidth, dataWidth));\n   FIFO#(AvalonMMRequest#(addrWidth, dataWidth)) req_out_fifo <- mkFIFO();\n   Vector#(2, FIFOF#(AvalonMMRequest#(addrWidth, dataWidth))) req_in_fifo <- replicateM(mkGFIFOF(False, True));\n   Reg#(Maybe#(Bit#(1))) routeFrom <- mkReg(tagged Invalid);\n\n   (* fire_when_enabled *)\n   rule arbitrate_outgoing_request;\n      if (routeFrom matches tagged Valid .port) begin\n         if (req_in_fifo[port].notEmpty()) begin\n            AvalonMMRequest#(addrWidth, dataWidth) req <- toGet(req_in_fifo[port]).get;\n            req_out_fifo.enq(req);\n            if (req.eof)\n               routeFrom <= tagged Invalid;\n         end\n      end\n      else begin\n         Bool sentOne = False;\n         for (Integer port=0; port<2; port=port+1) begin\n            if (!sentOne && req_in_fifo[port].notEmpty()) begin\n               AvalonMMRequest#(addrWidth, dataWidth) req <- toGet(req_in_fifo[port]).get;\n               sentOne = True;\n               if (req.sof) begin\n                  req_out_fifo.enq(req);\n                  if (!req.eof) begin\n                     routeFrom <= tagged Valid fromInteger(port);\n                  end\n               end\n            end\n         end\n      end\n   endrule: arbitrate_outgoing_request\n   Vector#(2, Put#(AvalonMMRequest#(addrWidth, dataWidth))) intemp;\n   for (Integer i=0; i<2; i=i+1)\n      intemp[i] = toPut(req_in_fifo[i]);\n   interface in = intemp;\n   interface Get toAvalon = toGet(req_out_fifo);\nendmodule\n\n"
  },
  {
    "path": "bsv/AwsF1Top.bsv",
    "content": "// Copyright (c) 2017 Connectal Project\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\nimport ConnectalConfig::*;\nimport Vector            :: *;\nimport GetPut::*;\nimport Connectable::*;\nimport Portal            :: *;\nimport Platform          :: *;\nimport Top               :: *;\nimport HostInterface     :: *;\nimport Pipe::*;\nimport CnocPortal::*;\nimport ConnectalMemTypes:: *;\nimport ConnectalMMU:: *;\nimport MemServer:: *;\nimport MMURequest::*;\nimport MMUIndication::*;\nimport MemServerIndication::*;\nimport MemServerRequest::*;\nimport Platform          :: *;\nimport Vector            :: *;\nimport SimDma::*;\nimport IfcNames::*;\nimport BuildVector::*;\nimport Axi4MasterSlave::*;\nimport AxiBits::*;\nimport AxiDma::*;\nimport FIFOF::*;\nimport ConnectalFIFO::*;\nimport Clocks::*;\n\n`include \"ConnectalProjectConfig.bsv\"\n\n`ifdef PinTypeInclude\nimport `PinTypeInclude::*;\n`endif\n`ifdef PinType\ntypedef `PinType PinType;\n`else\ntypedef Empty PinType;\n`endif\n\n(* always_enabled, always_ready *)\ninterface AwsF1ClSh;\n   method Bit#(1) flr_done();\n   method Bit#(32) status0();\n   method Bit#(32) status1();\n   method Bit#(32) id0();\n   method Bit#(32) id1();\n   method Bit#(16) status_vled();\nendinterface\n\n(* always_enabled, always_ready *)\ninterface AwsF1ShCl;\n   (* prefix=\"\" *)\n   method Action flr_assert(Bit#(1) flr_assert);\n   (* prefix=\"\" *)\n   method Action ctl0(Bit#(32) ctl0);\n   (* prefix=\"\" *)\n   method Action ctl1(Bit#(32) ctl1);\n   (* prefix=\"\" *)\n   method Action status_vdip(Bit#(16) status_vdip);\n   (* prefix=\"\" *)\n   method Action pwr_state(Bit#(2) pwr_state);\nendinterface\n\n(* always_ready, always_enabled *)\ninterface AwsF1Interrupt;\n   (* prefix=\"\" *)\n   method Bit#(16) apppf_irq_req();\n   method Action apppf_irq_ack(Bit#(16) ack);\nendinterface\n\nmodule mkAwsF1Interrupt#(Platform platform)(AwsF1Interrupt);\n   Vector#(NumberOfTiles, Reg#(Bool)) intrRegs <- replicateM(mkReg(False));\n   Vector#(NumberOfTiles, Reg#(Bool)) readyRegs <- replicateM(mkReg(True));\n   Vector#(NumberOfTiles, Wire#(Bool)) ackWires <- replicateM(mkDWire(False));\n   \n   for (Integer i = 0; i < valueOf(NumberOfTiles); i = i + 1) begin\n      rule intr_rule if (!intrRegs[i]);\n\t if (platform.interrupt[i] && readyRegs[i]) begin\n\t    intrRegs[i] <= True;\n\t    readyRegs[i] <= False;\n\t end\n      endrule\n      rule ack_rule if (intrRegs[i]);\n\t if  (ackWires[i]) begin\n\t    intrRegs[i] <= False;\n\t end\n      endrule\n      rule ready_rule if (!platform.interrupt[i]);\n\t readyRegs[i] <= True;\n      endrule\n   end\n   method Bit#(16) apppf_irq_req();\n      Bit#(16) bits = 0;\n      for (Integer i = 0; i < valueOf(NumberOfTiles); i = i + 1)\n\t bits[i] = pack(intrRegs[i]);\n      return bits;\n   endmethod\n   method Action apppf_irq_ack(Bit#(16) ack);\n      for (Integer i = 0; i < valueOf(NumberOfTiles); i = i + 1)\n\t ackWires[i] <= unpack(ack[i]);\n   endmethod\nendmodule\n\n(* always_ready, always_enabled *)\ninterface AwsF1Top;\n   interface PinType pins;\n   interface AwsF1ShCl sh_cl;\n   interface AwsF1ClSh cl_sh;\n   interface AwsF1Interrupt interrupt;\n   //interface Axi4SlaveBits#(64,512,6,Empty) dmasink;\n   interface Axi4SlaveLiteBits#(32,32) ocl;\n   //interface Axi4SlaveLiteBits#(32,32) sda;\n   //interface Axi4SlaveLiteBits#(32,32) bar1;\n   interface Axi4MasterBits#(PhysAddrWidth,512,16,AwsF1Extra) pcim;\nendinterface\n\nmodule mkAxi4SlaveLiteBitsFromPhysMemSlave#(PhysMemSlave#(addrWidth,dataWidth) slave)\n       (Axi4SlaveLiteBits#(axiaddrWidth,dataWidth)) provisos (Div#(dataWidth,8,burstLen),Add#(addrWidth,a__,axiaddrWidth));\n\n    let burstLen = fromInteger(valueOf(burstLen));\n\n    Wire#(Bit#(addrWidth)) araddrWire <- mkDWire(0);\n    Wire#(Bit#(1)) arvalidWire <- mkDWire(0);\n    Wire#(Bit#(1)) rreadyWire <- mkDWire(0);\n    Wire#(Bit#(dataWidth)) rdataWire <- mkDWire(0);\n\n    Wire#(Bit#(addrWidth)) awaddrWire <- mkDWire(0);\n    Wire#(Bit#(1)) awvalidWire <- mkDWire(0);\n    Wire#(Bit#(1)) wvalidWire <- mkDWire(0);\n    Wire#(Bit#(dataWidth)) wdataWire <- mkDWire(0);\n    Wire#(Bit#(1)) breadyWire <- mkDWire(0);\n\n    FIFOF#(PhysMemRequest#(addrWidth,dataWidth)) arFifo <- mkCFFIFOF();\n    FIFOF#(PhysMemRequest#(addrWidth,dataWidth)) awFifo <- mkCFFIFOF();\n    FIFOF#(MemData#(dataWidth)) rdataFifo <- mkCFFIFOF();\n    FIFOF#(MemData#(dataWidth)) wdataFifo <- mkCFFIFOF();\n    FIFOF#(Bit#(MemTagSize)) brespFifo <- mkCFFIFOF();\n\n    rule ar_rule if (arvalidWire == 1 && arFifo.notFull());\n       let req = PhysMemRequest {addr: araddrWire, burstLen: burstLen, tag: 0 };\n       arFifo.enq(req);\n    endrule\n    rule ar_to_slave;\n       let req <- toGet(arFifo).get();\n       slave.read_server.readReq.put(req);\n    endrule\n\n    rule aw_rule if (awvalidWire == 1 && awFifo.notFull());\n       let req = PhysMemRequest {addr: awaddrWire, burstLen: burstLen, tag: 0 };\n       awFifo.enq(req);\n    endrule\n    rule aw_to_slave;\n       let req <- toGet(awFifo).get();\n       slave.write_server.writeReq.put(req);\n    endrule\n\n    rule r_rule if (rreadyWire == 1 && rdataFifo.notEmpty());\n       rdataFifo.deq();\n    endrule\n    rule rdata_rule;\n       rdataWire <= rdataFifo.first.data;\n    endrule\n    rule rdata_from_slave;\n       let mdata <- slave.read_server.readData.get();\n       rdataFifo.enq(mdata);\n    endrule\n\n    rule wdata_rule if (wvalidWire == 1 && wdataFifo.notFull());\n       wdataFifo.enq(MemData { data: wdataWire, tag: 0, last: True });\n    endrule\n    rule wdata_to_slave;\n       let mdata <- toGet(wdataFifo).get();\n       slave.write_server.writeData.put(mdata);\n    endrule\n\n    rule b_rule if (breadyWire == 1 && brespFifo.notEmpty());\n       brespFifo.deq();\n    endrule\n    rule bresp_from_slave;\n       let done <- slave.write_server.writeDone.get();\n       brespFifo.enq(done);\n    endrule\n\n    method Action      araddr(Bit#(axiaddrWidth) v);\n       araddrWire <= truncate(v);\n    endmethod\n    method Bit#(1)     arready();\n       return pack(arFifo.notFull());\n    endmethod\n    method Action      arvalid(Bit#(1) v);\n       arvalidWire <= v;\n    endmethod\n    method Action      awaddr(Bit#(axiaddrWidth) v);\n       awaddrWire <= truncate(v);\n    endmethod\n    method Bit#(1)     awready();\n       return pack(awFifo.notFull());\n    endmethod\n    method Action      awvalid(Bit#(1) v);\n       awvalidWire <= v;\n    endmethod\n    method Action      bready(Bit#(1) v);\n       breadyWire <= v;\n    endmethod\n    method Bit#(2)     bresp();\n       return 0; // brespFifo.first();\n    endmethod\n    method Bit#(1)     bvalid();\n       return pack(brespFifo.notEmpty());\n    endmethod\n    method Bit#(dataWidth)     rdata();\n       return rdataWire;\n    endmethod\n    method Action      rready(Bit#(1) v);\n       rreadyWire <= v;\n    endmethod\n    method Bit#(2)     rresp();\n       return 0;\n    endmethod\n    method Bit#(1)     rvalid();\n      return pack(rdataFifo.notEmpty);\n    endmethod\n    method Action      wdata(Bit#(dataWidth) v);\n       wdataWire <= v;\n    endmethod\n    method Bit#(1)     wready();\n       return pack(wdataFifo.notFull());\n    endmethod\n    method Action      wvalid(Bit#(1) v);\n       wvalidWire <= v;\n    endmethod\nendmodule\n\n(* no_default_clock, no_default_reset, clock_prefix=\"\", reset_prefix=\"\" *)\nmodule mkAwsF1Top#(Clock clk_main_a0, Clock clk_extra_a1, Clock clk_extra_a2, Clock clk_extra_a3,\n       Clock  clk_extra_b0, Clock clk_extra_b1, Clock clk_extra_c0, Clock clk_extra_c1,\n       Reset kernel_rst_n, Reset rst_main_n\n       )(AwsF1Top);\n\n   Clock defaultClock = clk_main_a0;\n   Reset defaultReset = rst_main_n;\n`ifdef AWSF1_DERIVED_CLOCK\n   Clock derivedClock = `AWSF1_DERIVED_CLOCK;\n   Reset derivedReset <- mkAsyncReset(5, rst_main_n, derivedClock);\n`else\n   Clock derivedClock = clk_main_a0;\n   Reset derivedReset = rst_main_n;\n`endif\n\n   XsimHost host <- mkXsimHost(derivedClock, derivedReset, defaultClock);\n   let top <- mkConnectalTop(\n`ifdef IMPORT_HOSTIF\n       host,\n`else\n`ifdef IMPORT_HOST_CLOCKS // enables synthesis boundary\n       derivedClock, derivedReset,\n`else\n// otherwise no params\n`endif\n`endif\n\tclocked_by defaultClock, reset_by defaultReset\n       );\n\n   let platform <- mkPlatform(vec(top), clocked_by defaultClock, reset_by defaultReset);\n\n   Axi4SlaveLiteBits#(32,32) oclSlave <- mkAxi4SlaveLiteBitsFromPhysMemSlave(platform.slave, clocked_by defaultClock, reset_by defaultReset);\n\n   Vector#(NumberOfMasters, Axi4Master#(PhysAddrWidth,DataBusWidth,MemTagSize)) axiMasters\n       <- mapM(mkAxi4DmaMaster, platform.masters, clocked_by defaultClock, reset_by defaultReset);\n   Axi4MasterBits#(PhysAddrWidth,512,16,AwsF1Extra) masterBits\n       <- mkAxi4MasterBits(axiMasters[0], clocked_by defaultClock, reset_by defaultReset);\n\n   let awsF1Interrupt <- mkAwsF1Interrupt(platform, clocked_by defaultClock, reset_by defaultReset);\n\n   interface AwsF1ClSh cl_sh;\n      method id0 = 32'hF000_1D0F; // 32'hc100_1be7;\n      method id1 = 32'h1D51_FEDD; // 32'hc101_1be7;\n   endinterface\n\n   interface ocl = oclSlave;\n   interface pcim = masterBits;\n   interface interrupt = awsF1Interrupt;\n\n`ifdef PinType\n   interface pins = top.pins;\n`endif\nendmodule\n"
  },
  {
    "path": "bsv/Axi4MasterSlave.bsv",
    "content": "// Copyright (c) 2013 Quanta Research Cambridge, Inc.\n// Copyright (c) 2015 Connectal Project\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\nimport FIFOF::*;\nimport FIFO::*;\nimport GetPut::*;\nimport Connectable::*;\nimport RegFile::*;\nimport ConnectalMemTypes::*; // null_get, null_put\n\ntypedef struct {\n   Bit#(addrWidth) address;\n   Bit#(8) len;\n   Bit#(3) size; // assume matches bus width of Axi4Master\n   Bit#(2) burst;  // drive with 2'b01\n   Bit#(3) prot; // drive with 3'b000\n   Bit#(4) cache; // drive with 4'b0011\n   Bit#(idWidth) id;\n   Bit#(2) lock;\n   Bit#(4) qos;\n} Axi4ReadRequest#(numeric type addrWidth, numeric type idWidth) deriving (Bits);\n\nfunction Bit#(3) axiBusSize(busWidthType busWidth) provisos (Eq#(busWidthType),Literal#(busWidthType));\n   if (busWidth == 16)\n      return 3'b001;\n   else if (busWidth == 32)\n      return 3'b010;\n   else if (busWidth == 64)\n      return 3'b011;\n   else if (busWidth == 128)\n      return 3'b100;\n   else if (busWidth == 256)\n      return 3'b101;\n   else if (busWidth == 512)\n      return 3'b110;\n   else if (busWidth == 1024)\n      return 3'b111;\n   else\n      return 3'b000;\nendfunction\n\nfunction Bit#(3) axiBusSizeBytes(busWidthType busWidth) provisos (Eq#(busWidthType),Literal#(busWidthType),Arith#(busWidthType));\n   return axiBusSize(8*busWidth);\nendfunction\n\ntypedef struct {\n   Bit#(busWidth) data;\n   Bit#(2) resp;\n   Bit#(1) last;\n   Bit#(idWidth) id;\n} Axi4ReadResponse#(numeric type busWidth, numeric type idWidth) deriving (Bits);\n\ntypedef struct {\n   Bit#(addrWidth) address;\n   Bit#(8) len;\n   Bit#(3) size; // assume matches bus width of Axi4Master\n   Bit#(2) burst;  // drive with 2'b01\n   Bit#(3) prot; // drive with 3'b000\n   Bit#(4) cache; // drive with 4'b0011\n   Bit#(idWidth) id;\n   Bit#(2) lock;\n   Bit#(4) qos;\n} Axi4WriteRequest#(numeric type addrWidth, numeric type idWidth) deriving (Bits);\n\ntypedef struct {\n    Bit#(busWidth) data;\n    Bit#(TDiv#(busWidth,8)) byteEnable;\n    Bit#(1)        last;\n    Bit#(idWidth) id;\n} Axi4WriteData#(numeric type busWidth, numeric type idWidth) deriving (Bits);\n\ntypedef struct {\n    Bit#(2) resp;\n    Bit#(idWidth) id;\n} Axi4WriteResponse#(numeric type idWidth) deriving (Bits);\n\ninterface Axi4Master#(numeric type addrWidth, numeric type busWidth, numeric type idWidth);\n   interface Get#(Axi4ReadRequest#(addrWidth, idWidth)) req_ar;\n   interface Put#(Axi4ReadResponse#(busWidth, idWidth)) resp_read;\n   interface Get#(Axi4WriteRequest#(addrWidth, idWidth)) req_aw;\n   interface Get#(Axi4WriteData#(busWidth, idWidth)) resp_write;\n   interface Put#(Axi4WriteResponse#(idWidth)) resp_b;\nendinterface\n\ninterface Axi4Slave#(numeric type addrWidth, numeric type busWidth, numeric type idWidth);\n   interface Put#(Axi4ReadRequest#(addrWidth, idWidth)) req_ar;\n   interface Get#(Axi4ReadResponse#(busWidth, idWidth)) resp_read;\n   interface Put#(Axi4WriteRequest#(addrWidth, idWidth)) req_aw;\n   interface Put#(Axi4WriteData#(busWidth, idWidth)) resp_write;\n   interface Get#(Axi4WriteResponse#(idWidth)) resp_b;\nendinterface\n\nfunction  Axi4Master#(addrWidth, busWidth, idWidth) null_axi_master();\n   return (interface Axi4Master;\n\t      interface Get req_ar = null_get;\n\t      interface Put resp_read = null_put;\n\t      interface Get req_aw = null_get;\n\t      interface Get resp_write = null_get;\n\t      interface Put resp_b = null_put;\n\t   endinterface);\nendfunction\n\ninstance Connectable#(Axi4Master#(addrWidth, busWidth,idWidth), Axi4Slave#(addrWidth, busWidth,idWidth));\n   module mkConnection#(Axi4Master#(addrWidth, busWidth,idWidth) m, Axi4Slave#(addrWidth, busWidth,idWidth) s)(Empty);\n\n      mkConnection(m.req_ar, s.req_ar);\n      mkConnection(s.resp_read, m.resp_read);\n\n      mkConnection(m.req_aw, s.req_aw);\n      mkConnection(m.resp_write, s.resp_write);\n      mkConnection(s.resp_b, m.resp_b);\n\n   endmodule\nendinstance\n\nfunction Axi4ReadRequest#(axiAddrWidth,idWidth) toAxi4ReadRequest(PhysMemRequest#(addrWidth,dataBusWidth) req)\n   provisos (Add#(axiAddrWidth,a__,addrWidth)\n\t     ,Add#(b__, idWidth, MemTagSize));\n   Axi4ReadRequest#(axiAddrWidth,idWidth) axireq  = unpack(0);\n   axireq.address = truncate(req.addr);\n   axireq.id   = truncate(req.tag);\n   let dataWidthBytes = valueOf(TDiv#(dataBusWidth,8));\n   let dataSizeMask = dataWidthBytes-1;\n   let size = req.burstLen & fromInteger(dataSizeMask);\n   let beats = (req.burstLen + fromInteger(dataWidthBytes-1)) / fromInteger(dataWidthBytes);\n   axireq.len = truncate(beats-1);\n   //axireq.size = (beats == 1) ? axiBusSizeBytes(size) : axiBusSizeBytes(dataWidthBytes);\n   axireq.size = axiBusSizeBytes(dataWidthBytes);\n   axireq.burst = 2'b01;\n   axireq.cache = 4'b1111;\n   return axireq;\nendfunction\nfunction Axi4WriteRequest#(axiAddrWidth,idWidth) toAxi4WriteRequest(PhysMemRequest#(addrWidth,dataBusWidth) req)\n   provisos (Add#(axiAddrWidth,a__,addrWidth)\n\t     ,Add#(b__, idWidth, MemTagSize));\n   Axi4WriteRequest#(axiAddrWidth,idWidth) axireq  = unpack(0);\n   axireq.address = truncate(req.addr);\n   axireq.id   = truncate(req.tag);\n   let dataWidthBytes = valueOf(TDiv#(dataBusWidth,8));\n   let dataSizeMask = dataWidthBytes-1;\n   let size = req.burstLen & fromInteger(dataSizeMask);\n   let beats = (req.burstLen + fromInteger(dataWidthBytes-1)) / fromInteger(dataWidthBytes);\n   axireq.len = truncate(beats-1);\n   //axireq.size = (beats == 1) ? axiBusSizeBytes(size) : axiBusSizeBytes(dataWidthBytes);\n   axireq.size = axiBusSizeBytes(dataWidthBytes);\n   axireq.burst = 2'b01;\n   axireq.cache = 4'b1111;\n   return axireq;\nendfunction\n\ninstance MkPhysMemSlave#(Axi4Slave#(axiAddrWidth,dataWidth,idWidth),addrWidth,dataWidth)\n      provisos (Add#(axiAddrWidth,a__,addrWidth),Add#(b__, idWidth, MemTagSize));\n   module mkPhysMemSlave#(Axi4Slave#(axiAddrWidth,dataWidth,idWidth) axiSlave)(PhysMemSlave#(addrWidth,dataWidth));\n      FIFOF#(PhysMemRequest#(addrWidth,dataWidth)) arfifo <- mkFIFOF();\n      FIFOF#(MemData#(dataWidth)) rfifo <- mkFIFOF();\n      FIFOF#(PhysMemRequest#(addrWidth,dataWidth)) awfifo <- mkFIFOF();\n      FIFOF#(MemData#(dataWidth)) wfifo <- mkFIFOF();\n      FIFOF#(Bit#(MemTagSize)) bfifo <- mkFIFOF();\n      FIFOF#(Bit#(MemTagSize)) rtagfifo <- mkFIFOF();\n      FIFOF#(Bit#(MemTagSize)) wtagfifo <- mkFIFOF();\n\n      rule rl_arfifo;\n\t let req <- toGet(arfifo).get();\n\t Axi4ReadRequest#(axiAddrWidth,idWidth) axireq = toAxi4ReadRequest(req);\n\t axiSlave.req_ar.put(axireq);\n      endrule\n      rule rl_rdata;\n\t let rdata <- axiSlave.resp_read.get();\n\t rfifo.enq(MemData { data: rdata.data, tag: extend(rdata.id) } );\n      endrule\n\n      rule rl_awfifo;\n\t let req <- toGet(awfifo).get();\n\t Axi4WriteRequest#(axiAddrWidth,idWidth) axireq = toAxi4WriteRequest(req);\n\t axiSlave.req_aw.put(axireq);\n      endrule\n      rule rl_wdata;\n\t let md <- toGet(wfifo).get();\n\t //FIXME byteEnable\n\t axiSlave.resp_write.put(Axi4WriteData {data: md.data, byteEnable:maxBound, last:pack(md.last), id:truncate(md.tag)});\n      endrule\n      rule rl_done;\n\t let b <- axiSlave.resp_b.get();\n\t bfifo.enq(extend(b.id));\n      endrule\n\n      interface PhysMemReadServer read_server;\n\t interface Put readReq = toPut(arfifo);\n\t interface Get readData = toGet(rfifo);\n      endinterface\n      interface PhysMemWriteServer write_server;\n\t interface Put writeReq = toPut(awfifo);\n\t interface Put writeData = toPut(wfifo);\n\t interface Get writeDone = toGet(bfifo);\n      endinterface\n   endmodule\nendinstance\n"
  },
  {
    "path": "bsv/AxiBits.bsv",
    "content": "// Copyright (c) 2015 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n`include \"ConnectalProjectConfig.bsv\"\nimport Vector::*;\nimport Clocks::*;\nimport FIFOF::*;\nimport ConnectalFIFO::*;\nimport GetPut::*;\nimport Probe::*;\nimport ConnectalMemTypes::*;\nimport ConnectalEHR::*;\nimport Axi4MasterSlave::*;\nimport Connectable::*;\nimport ConnectalBramFifo::*;\n\ninterface AxiMasterBits#(numeric type addrWidth, numeric type dataWidth, numeric type tagWidth, type extraType);\n    method Bit#(addrWidth)     araddr();\n    method Bit#(2)     arburst();\n    method Bit#(4)     arcache();\n    method Bit#(1)     aresetn();\n    method Bit#(tagWidth)     arid();\n    method Bit#(4)     arlen();\n    method Bit#(2)     arlock();\n    method Bit#(3)     arprot();\n    method Bit#(4)     arqos();\n    method Action      arready(Bit#(1) v);\n    method Bit#(2)     arsize();\n    method Bit#(1)     arvalid();\n    method Bit#(addrWidth)     awaddr();\n    method Bit#(2)     awburst();\n    method Bit#(4)     awcache();\n    method Bit#(tagWidth)     awid();\n    method Bit#(4)     awlen();\n    method Bit#(2)     awlock();\n    method Bit#(3)     awprot();\n    method Bit#(4)     awqos();\n    method Action      awready(Bit#(1) v);\n    method Bit#(2)     awsize();\n    method Bit#(1)     awvalid();\n    method Action      bid(Bit#(tagWidth) v);\n    method Bit#(1)     bready();\n    method Action      bresp(Bit#(2) v);\n    method Action      bvalid(Bit#(1) v);\n    method Action      rdata(Bit#(dataWidth) v);\n    method Action      rid(Bit#(tagWidth) v);\n    method Action      rlast(Bit#(1) v);\n    method Bit#(1)     rready();\n    method Action      rresp(Bit#(2) v);\n    method Action      rvalid(Bit#(1) v);\n    method Bit#(dataWidth)     wdata();\n    method Bit#(tagWidth)     wid();\n    method Bit#(1)     wlast();\n    method Action      wready(Bit#(1) v);\n    method Bit#(TDiv#(dataWidth,8))     wstrb();\n    method Bit#(1)     wvalid();\n    interface extraType   extra;\nendinterface\n\ninterface HPType;\n    method Bit#(3)     racount();\n    method Bit#(8)     rcount();\n    method Action      rdissuecap1en(Bit#(1) v);\n    method Bit#(6)     wacount();\n    method Bit#(8)     wcount();\n    method Action      wrissuecap1en(Bit#(1) v);\nendinterface\n\ninterface ACPType;\n    method Action      aruser(Bit#(5) v);\n    method Action      awuser(Bit#(5) v);\nendinterface\n\ninterface AxiSlaveBits#(numeric type addrWidth, numeric type dataWidth, numeric type tagWidth, type extraType);\n    method Action      araddr(Bit#(addrWidth) v);\n    method Action      arburst(Bit#(2) v);\n    method Action      arcache(Bit#(4) v);\n    method Bit#(1)     aresetn();\n    method Action      arid(Bit#(tagWidth) v);\n    method Action      arlen(Bit#(4) v);\n    method Action      arlock(Bit#(2) v);\n    method Action      arprot(Bit#(3) v);\n    method Action      arqos(Bit#(4) v);\n    method Bit#(1)     arready();\n    method Action      arsize(Bit#(2) v);\n    method Action      arvalid(Bit#(1) v);\n    method Action      awaddr(Bit#(addrWidth) v);\n    method Action      awburst(Bit#(2) v);\n    method Action      awcache(Bit#(4) v);\n    method Action      awid(Bit#(tagWidth) v);\n    method Action      awlen(Bit#(4) v);\n    method Action      awlock(Bit#(2) v);\n    method Action      awprot(Bit#(3) v);\n    method Action      awqos(Bit#(4) v);\n    method Bit#(1)     awready();\n    method Action      awsize(Bit#(2) v);\n    method Action      awvalid(Bit#(1) v);\n    method Bit#(tagWidth)     bid();\n    method Action      bready(Bit#(1) v);\n    method Bit#(2)     bresp();\n    method Bit#(1)     bvalid();\n    method Bit#(dataWidth)     rdata();\n    method Bit#(1)     rlast();\n    method Action      rready(Bit#(1) v);\n    method Bit#(2)     rresp();\n    method Bit#(1)     rvalid();\n    method Action      wdata(Bit#(dataWidth) v);\n    method Action      wid(Bit#(tagWidth) v);\n    method Action      wlast(Bit#(1) v);\n    method Bit#(1)     wready();\n    method Action      wstrb(Bit#(TDiv#(dataWidth,8)) v);\n    method Action      wvalid(Bit#(1) v);\n    method Bit#(tagWidth)     rid();\n    interface extraType   extra;\nendinterface\n\ninterface Axi4MasterBits#(numeric type addrWidth, numeric type dataWidth, numeric type tagWidth, type extraType);\n    method Bit#(addrWidth)     araddr();\n    method Bit#(2)     arburst();\n    method Bit#(4)     arcache();\n    method Bit#(1)     aresetn();\n    method Bit#(tagWidth)     arid();\n    method Bit#(8)     arlen();\n    method Bit#(2)     arlock();\n    method Bit#(3)     arprot();\n    method Bit#(4)     arqos();\n    method Action      arready(Bit#(1) v);\n    method Bit#(3)     arsize();\n    method Bit#(1)     arvalid();\n    method Bit#(addrWidth)     awaddr();\n    method Bit#(2)     awburst();\n    method Bit#(4)     awcache();\n    method Bit#(tagWidth)     awid();\n    method Bit#(8)     awlen();\n    method Bit#(2)     awlock();\n    method Bit#(3)     awprot();\n    method Bit#(4)     awqos();\n    method Action      awready(Bit#(1) v);\n    method Bit#(3)     awsize();\n    method Bit#(1)     awvalid();\n    method Action      bid(Bit#(tagWidth) v);\n    method Bit#(1)     bready();\n    method Action      bresp(Bit#(2) v);\n    method Action      bvalid(Bit#(1) v);\n    method Action      rdata(Bit#(dataWidth) v);\n    method Action      rid(Bit#(tagWidth) v);\n    method Action      rlast(Bit#(1) v);\n    method Bit#(1)     rready();\n    method Action      rresp(Bit#(2) v);\n    method Action      rvalid(Bit#(1) v);\n    method Bit#(dataWidth)     wdata();\n    method Bit#(tagWidth)     wid();\n    method Bit#(1)     wlast();\n    method Action      wready(Bit#(1) v);\n    method Bit#(TDiv#(dataWidth,8))     wstrb();\n    method Bit#(1)     wvalid();\n    interface extraType   extra;\nendinterface\n\ninterface Axi4MasterUntaggedBits#(numeric type addrWidth, numeric type dataWidth);\n    method Bit#(addrWidth)     araddr();\n    method Bit#(2)     arburst();\n    method Bit#(4)     arcache();\n    method Bit#(8)     arlen();\n    //method Bit#(2)     arlock();\n    method Bit#(3)     arprot();\n    //method Bit#(4)     arqos();\n    method Action      arready(Bit#(1) v);\n    method Bit#(3)     arsize();\n    method Bit#(1)     arvalid();\n    method Bit#(addrWidth)     awaddr();\n    method Bit#(2)     awburst();\n    method Bit#(4)     awcache();\n    method Bit#(8)     awlen();\n    //method Bit#(2)     awlock();\n    method Bit#(3)     awprot();\n    //method Bit#(4)     awqos();\n    method Action      awready(Bit#(1) v);\n    method Bit#(3)     awsize();\n    method Bit#(1)     awvalid();\n    method Bit#(1)     bready();\n    method Action      bresp(Bit#(2) v);\n    method Action      bvalid(Bit#(1) v);\n    method Action      rdata(Bit#(dataWidth) v);\n    method Action      rlast(Bit#(1) v);\n    method Bit#(1)     rready();\n    method Action      rresp(Bit#(2) v);\n    method Action      rvalid(Bit#(1) v);\n    method Bit#(dataWidth)     wdata();\n    method Bit#(1)     wlast();\n    method Action      wready(Bit#(1) v);\n    method Bit#(TDiv#(dataWidth,8))     wstrb();\n    method Bit#(1)     wvalid();\nendinterface\n\ntypeclass ToAxi4MasterBits#(type atype, type btype);\n   function atype toAxi4MasterBits(btype b);\nendtypeclass\n\ninstance ToAxi4MasterBits#(Axi4MasterBits#(addrWidth,dataWidth,tagWidth,Empty), Axi4MasterUntaggedBits#(addrWidth,dataWidth));\nfunction Axi4MasterBits#(addrWidth,dataWidth,tagWidth,Empty) toAxi4MasterBits(Axi4MasterUntaggedBits#(addrWidth,dataWidth) m);\n   return (interface Axi4MasterBits#(addrWidth,dataWidth,tagWidth,Empty);\n    method araddr = m.araddr;\n      method arburst = m.arburst;\n      method arcache = m.arcache;\n      //method aresetn = no_reset;\n      method Bit#(tagWidth)     arid(); return 0; endmethod\n      method arlen = m.arlen;\n      //method arlock = m.arlock;\n      method arprot = m.arprot;\n      //method arqos = m.arqos;\n      method arready = m.arready;\n      method arsize = m.arsize;\n      method arvalid = m.arvalid;\n      method awaddr = m.awaddr;\n      method awburst = m.awburst;\n      method awcache = m.awcache;\n      method Bit#(tagWidth)     awid(); return 0; endmethod\n      method awlen = m.awlen;\n      //method awlock = m.awlock;\n      method awprot = m.awprot;\n      //method awqos = m.awqos;\n      method awready = m.awready;\n      method awsize = m.awsize;\n      method awvalid = m.awvalid;\n      method Action      bid(Bit#(tagWidth) v); endmethod\n      method bready = m.bready;\n      method bresp = m.bresp;\n      method bvalid = m.bvalid;\n      method rdata = m.rdata;\n      method Action      rid(Bit#(tagWidth) v); endmethod\n      method rlast = m.rlast;\n      method rready = m.rready;\n      method rresp = m.rresp;\n      method rvalid = m.rvalid;\n      method wdata = m.wdata;\n      method Bit#(tagWidth)     wid(); return 0; endmethod\n      method wlast = m.wlast;\n      method wready = m.wready;\n      method wstrb = m.wstrb;\n      method wvalid = m.wvalid;\n      interface extra = ?;   \n      endinterface);\nendfunction\nendinstance\n\n(* always_ready, always_enabled *)\ninterface AwsF1Extra;\n    //10:0 Length in DW of the transaction\n    //14:11 are the byte-enable for the first DW (bit value 1 mean byte is enable, i.e. not masked)\n    //18:15 are the byte-enable for the last DW (bit value 1 mean byte is enable, i.e. not masked)\n    method Bit#(19) awuser;\n    // 10:0 Length in DW of the transaction\n    // 18:11 Must be set to 0xFF, could be ignored in next release\n    method Bit#(19) aruser;\nendinterface\n\nmodule mkAxi4MasterBits#(Axi4Master#(addrWidth,dataWidth,tagWidth) m)(Axi4MasterBits#(addrWidth,busDataWidth,busTagWidth,AwsF1Extra))\n    provisos (Add#(dataWidth,d__,busDataWidth),\n              Div#(dataWidth,32,dataWidthWords),\n    \t      Add#(tagWidth,t__,busTagWidth),\n    \t      Add#(a__, TDiv#(dataWidth, 8), TDiv#(busDataWidth, 8)));\n\t    let arfifo <- mkCFFIFOF();\n\t    let araddrWire <- mkDWire(0);\n\t    let arburstWire <- mkDWire(0);\n\t    let arcacheWire <- mkDWire(0);\n\t    let aridWire <- mkDWire(0);\n\t    let arreadyWire <- mkDWire(False);\n\t    let arprotWire <- mkDWire(0);\n\t    let arlenWire <- mkDWire(0);\n\t    let arsizeWire <- mkDWire(0);\n\t    let aruserWire <- mkDWire(0);\n\n\t    let awfifo <- mkCFFIFOF();\n\t    let awaddrWire <- mkDWire(0);\n\t    let awburstWire <- mkDWire(0);\n\t    let awcacheWire <- mkDWire(0);\n\t    let awidWire <- mkDWire(0);\n\t    let awreadyWire <- mkDWire(False);\n\t    let awprotWire <- mkDWire(0);\n\t    let awlenWire <- mkDWire(0);\n\t    let awsizeWire <- mkDWire(0);\n\t    let awuserWire <- mkDWire(0);\n\n\t    let rfifo <- mkCFFIFOF();\n\t    let rdataWire <- mkDWire(0);\n\t    let rrespWire <- mkDWire(0);\n\t    let rlastWire <- mkDWire(0);\n\t    let ridWire <- mkDWire(0);\t    \n\t    let rvalidWire <- mkDWire(False);\n\n\t    let wfifo <- mkCFFIFOF();\n\t    let wdataWire <- mkDWire(0);\n\t    let widWire <- mkDWire(0);\n\t    let wstrbWire <- mkDWire(0);\n\t    let wlastWire <- mkDWire(0);\n\t    let wreadyWire <- mkDWire(False);\n\n\t    let bfifo <- mkCFFIFOF();\n\t    let bidWire <- mkDWire(0);\n\t    let brespWire <- mkDWire(0);\n\t    let bvalidWire <- mkDWire(False);\n\n\t    rule arfifo_enq;\n\t       let req <- m.req_ar.get();\n\t       arfifo.enq(req);\n\t    endrule\n\n\t    rule arwire_rule;\n\t       araddrWire <= arfifo.first.address;\n\t       arlenWire <= arfifo.first.len;\n\t       Bit#(11) dwlen = extend(arfifo.first.len) / fromInteger(valueOf(dataWidthWords));\n\t       Bit#(8) mustbeone = 8'hf;\n\t       aruserWire <= { mustbeone, dwlen };\n\t       arsizeWire <= arfifo.first.size;\n\t       arburstWire <= 2'b01; //arfifo.first.burst;\n\t       arprotWire <= 3'b000; //arfifo.first.prot;\n\t       arcacheWire <= 4'b0011; // arfifo.first.cache;\n\t       aridWire <= arfifo.first.id;\n\t    endrule\n\n\t    rule ar_handshake if (arreadyWire);\n\t      arfifo.deq();\n\t    endrule\n\n\t    rule awfifo_enq;\n\t       let req <- m.req_aw.get();\n\t       awfifo.enq(req);\n\t    endrule\n\n\t    rule awwire_rule;\n\t       awaddrWire <= awfifo.first.address;\n\t       let lenbytes = awfifo.first.len;\n\t       awlenWire <= lenbytes;\n\t       Bit#(11) dwlen = extend(lenbytes) / fromInteger(valueOf(dataWidthWords));\n\t       Bit#(4) firstBE = 4'hf;\n\t       Bit#(4) lastBE = (lenbytes > 4) ? 4'hf : 0;\n\t       awuserWire <= { lastBE, firstBE, dwlen };\n\t       awsizeWire <= awfifo.first.size;\n\t       awburstWire <= 2'b01; //awfifo.first.burst;\n\t       awprotWire <= 3'b000; //awfifo.first.prot;\n\t       awcacheWire <= 4'b0011; // awfifo.first.cache;\n\t       awidWire <= awfifo.first.id;\n\t    endrule\n\n\t    rule aw_handshake if (awreadyWire);\n\t      awfifo.deq();\n\t    endrule\n\n\t    rule rdata_put;\n\t       let data <- toGet(rfifo).get();\n\t       m.resp_read.put(data); \n\t    endrule\n\n\t    rule r_handshake if (rvalidWire);\n\t      rfifo.enq(Axi4ReadResponse {data: truncate(rdataWire),\n\t      \t\t\t\t  resp: rrespWire,\n\t\t\t\t\t  last: rlastWire,\n\t\t\t\t\t  id: ridWire });\n\t    endrule\n\n\t    rule wdata_get;\n\t       let data <- m.resp_write.get();\n\t       wfifo.enq(data);\n\t    endrule\n\n\t    rule w_handshake if (wreadyWire);\n\t      let data <- toGet(wfifo).get();\n\t      wdataWire <= extend(data.data);\n\t      wlastWire <= pack(data.last);\n\t      wstrbWire <= data.byteEnable;\n\t      widWire <= data.id;\n\t    endrule\n\n\t    rule bresp_put;\n\t       let resp <- toGet(bfifo).get();\n\t       m.resp_b.put(resp); \n\t    endrule\n\n\t    rule b_handshake if (bvalidWire);\n\t      bfifo.enq(Axi4WriteResponse {resp: brespWire,\n\t\t\t\t\t  id: bidWire });\n\t    endrule\n\n\t    interface AwsF1Extra extra;\n\t       method aruser = aruserWire;\n\t       method awuser = awuserWire;\n\t    endinterface\n\n\t    method araddr = araddrWire;\n\t    method arburst = arburstWire;\n\t    method arcache = arcacheWire;\n\t    method aresetn = 1;\n\t    method arid = extend(aridWire);\n\t    method arlen = arlenWire;\n\t    // method Bit#(2)     arlock();\n\t    method arprot = arprotWire;\n\t    // method Bit#(4)     arqos();\n\t    method Action      arready(Bit#(1) v); arreadyWire <= unpack(v); endmethod\n\t    method arsize = arsizeWire;\n\t    method arvalid = pack(arfifo.notEmpty);\n\n\t    method awaddr = awaddrWire;\n\t    method awburst = awburstWire;\n\t    method awcache = awcacheWire;\n\t    method awid = extend(awidWire);\n\t    method awlen = awlenWire;\n\t    //method awlock = awlockWire;\n\t    method awprot = awprotWire;\n\t    // method Bit#(4)     awqos();\n\t    method Action      awready(Bit#(1) v); awreadyWire <= unpack(v); endmethod\n\t    method awsize = awsizeWire;\n\t    method awvalid = pack(awfifo.notEmpty);\n\n\t    method Action      bid(Bit#(busTagWidth) v); bidWire <= truncate(v); endmethod\n\t    method bready = pack(bfifo.notFull());\n\t    method Action      bresp(Bit#(2) v); brespWire <= v; endmethod\n\t    method Action      bvalid(Bit#(1) v); bvalidWire <= unpack(v); endmethod\n\n\t    method Action      rdata(Bit#(busDataWidth) v); rdataWire <= v; endmethod\n\t    method Action      rid(Bit#(busTagWidth) v); ridWire <= truncate(v); endmethod\n\t    method Action      rlast(Bit#(1) v); rlastWire <= unpack(v); endmethod\n\t    method rready = pack(rfifo.notFull());\n\t    method Action      rresp(Bit#(2) v); rrespWire <= v; endmethod\n\t    method Action      rvalid(Bit#(1) v); rvalidWire <= unpack(v); endmethod\n\n\t    method wdata = wdataWire;\n\t    method wid = extend(widWire);\n\t    method wlast = wlastWire;\n\t    method Action      wready(Bit#(1) v); wreadyWire <= unpack(v); endmethod\n\t    method wstrb = extend(wstrbWire);\n\t    method wvalid = pack(wfifo.notEmpty);\n\nendmodule\n\ninterface Axi4SlaveBits#(numeric type addrWidth, numeric type dataWidth, numeric type tagWidth, type extraType);\n    method Action      araddr(Bit#(addrWidth) v);\n    method Action      arburst(Bit#(2) v);\n    method Action      arcache(Bit#(4) v);\n    method Bit#(1)     aresetn();\n    method Action      arid(Bit#(tagWidth) v);\n    method Action      arlen(Bit#(8) v);\n    method Action      arlock(Bit#(2) v);\n    method Action      arprot(Bit#(3) v);\n    method Action      arqos(Bit#(4) v);\n    method Bit#(1)     arready();\n    method Action      arsize(Bit#(3) v);\n    method Action      arvalid(Bit#(1) v);\n    method Action      awaddr(Bit#(addrWidth) v);\n    method Action      awburst(Bit#(2) v);\n    method Action      awcache(Bit#(4) v);\n    method Action      awid(Bit#(tagWidth) v);\n    method Action      awlen(Bit#(8) v);\n    method Action      awlock(Bit#(2) v);\n    method Action      awprot(Bit#(3) v);\n    method Action      awqos(Bit#(4) v);\n    method Bit#(1)     awready();\n    method Action      awsize(Bit#(3) v);\n    method Action      awvalid(Bit#(1) v);\n    method Bit#(tagWidth)     bid();\n    method Action      bready(Bit#(1) v);\n    method Bit#(2)     bresp();\n    method Bit#(1)     bvalid();\n    method Bit#(dataWidth)     rdata();\n    method Bit#(1)     rlast();\n    method Action      rready(Bit#(1) v);\n    method Bit#(2)     rresp();\n    method Bit#(1)     rvalid();\n    method Action      wdata(Bit#(dataWidth) v);\n    method Action      wid(Bit#(tagWidth) v);\n    method Action      wlast(Bit#(1) v);\n    method Bit#(1)     wready();\n    method Action      wstrb(Bit#(TDiv#(dataWidth,8)) v);\n    method Action      wvalid(Bit#(1) v);\n    method Bit#(tagWidth)     rid();\n    interface extraType   extra;\nendinterface\n\ninterface Axi4SlaveLiteBits#(numeric type addrWidth, numeric type dataWidth);\n    method Action      araddr(Bit#(addrWidth) v);\n    method Bit#(1)     arready();\n    method Action      arvalid(Bit#(1) v);\n    method Action      awaddr(Bit#(addrWidth) v);\n    method Bit#(1)     awready();\n    method Action      awvalid(Bit#(1) v);\n    method Action      bready(Bit#(1) v);\n    method Bit#(2)     bresp();\n    method Bit#(1)     bvalid();\n    method Bit#(dataWidth)     rdata();\n    method Action      rready(Bit#(1) v);\n    method Bit#(2)     rresp();\n    method Bit#(1)     rvalid();\n    method Action      wdata(Bit#(dataWidth) v);\n    method Bit#(1)     wready();\n    method Action      wvalid(Bit#(1) v);\nendinterface\n\ntypeclass ToAxi4SlaveBits#(type atype, type btype);\n   function atype toAxi4SlaveBits(btype b);\nendtypeclass\n\nmodule mkAxiFifoF(FIFOF#(t)) provisos(Bits#(t, tSz));\n  Ehr#(2, t) da <- mkEhr(?);\n  Ehr#(2, Bool) va <- mkEhr(False);\n  Ehr#(2, t) db <- mkEhr(?);\n  Ehr#(2, Bool) vb <- mkEhr(False);\n\n  rule canon if(vb[1] && !va[1]);\n    da[1] <= db[1];\n    va[1] <= True;\n    vb[1] <= False;\n  endrule\n\n  method Bool notFull = !vb[0]; // technically, canEnqueue\n\n  method Action enq(t x) if(!vb[0]);\n    db[0] <= x;\n    vb[0] <= True;\n  endmethod\n\n  method Bool notEmpty = va[0]; // technically, canDequeue\n\n  method Action deq if (va[0]);\n    va[0] <= False;\n  endmethod\n\n  method t first if (va[0]);\n    return da[0];\n  endmethod\n\n  // conflicts with enq, deq, but we do not call it   \n  method Action clear;\n    vb[0] <= False;\n    va[0] <= False;\n  endmethod\nendmodule\n\ntypedef 40 MpsocMAxiAddrWidth; // MAXI:40bit SAXI:49bit\ntypedef 128 MpsocAxiDataWidth;\ntypedef 16 MpsocMAxiIdWidth;   // MAXI:16bit SAXI: 6bit\ntypedef 32 PhysMemDataWidth;\ntypedef 32 PhysMemAddrWidth;\ninstance MkPhysMemMaster#(Axi4MasterBits#(MpsocMAxiAddrWidth,MpsocAxiDataWidth,MpsocMAxiIdWidth,extra),PhysMemAddrWidth,PhysMemDataWidth)\n      provisos (Add#(PhysMemAddrWidth,a__,MpsocMAxiAddrWidth),\n\t\tAdd#(c__, 6, MpsocMAxiIdWidth)\n\t\t);\n   module mkPhysMemMaster#(Axi4MasterBits#(MpsocMAxiAddrWidth,MpsocAxiDataWidth,MpsocMAxiIdWidth,extra) axiMaster)(PhysMemMaster#(PhysMemAddrWidth,PhysMemDataWidth));\n      FIFOF#(PhysMemRequest#(PhysMemAddrWidth,PhysMemDataWidth)) arfifo <- mkAxiFifoF();\n      FIFOF#(MemData#(PhysMemDataWidth)) rfifo <- mkAxiFifoF();\n      FIFOF#(PhysMemRequest#(PhysMemAddrWidth,PhysMemDataWidth)) awfifo <- mkAxiFifoF();\n      FIFOF#(MemData#(PhysMemDataWidth)) wfifo <- mkAxiFifoF();\n      FIFOF#(Bit#(MemTagSize)) bfifo <- mkAxiFifoF();\n      FIFOF#(Bit#(MpsocMAxiIdWidth)) rtagfifo <- mkAxiFifoF();\n      FIFOF#(Tuple2#(Bit#(MpsocMAxiIdWidth),Bit#(2))) awtagfifo <- mkAxiFifoF();\n      FIFOF#(Bit#(MpsocMAxiIdWidth)) wtagfifo <- mkAxiFifoF();\n\n   let beatShift = fromInteger(valueOf(TLog#(TDiv#(PhysMemDataWidth,8))));\n// req_ar (M=>S)\n      let arreadyProbe <- mkProbe();\n      rule rl_arready;\n\t let arready = pack(arfifo.notFull && rtagfifo.notFull);\n\t arreadyProbe <= arready;\n\t axiMaster.arready(arready);\n      endrule\n      rule rl_arfifo if (axiMaster.arvalid() == 1);\n\t let addr = truncate(axiMaster.araddr());\n\t let burstLen = extend(axiMaster.arlen+1) << beatShift; // calculate burstLen\n\t arfifo.enq(PhysMemRequest{ addr: addr, burstLen: burstLen, tag: 0 } ); // burstlen corrected\n\t rtagfifo.enq(axiMaster.arid()); // what if the single request with multiple transfer\n      endrule\n\n// resp_read (S=>M)\n      let rvalidProbe <- mkProbe();\n      rule rl_rvalid;\n\t let rvalid = pack(rfifo.notEmpty && rtagfifo.notEmpty);\n\t rvalidProbe <= rvalid;\n\t axiMaster.rvalid(rvalid);\n      endrule\n      rule rl_rdata if (axiMaster.rready() == 1);\n\t //let rtag <- toGet(rtagfifo).get();\n\t let rtag = rtagfifo.first();\n\t let rdata <- toGet(rfifo).get();\n\n\t if (rdata.last) begin\n\t\t rtagfifo.deq(); // deq rtagfifo only if last beat\n\t end\n\t \n\t axiMaster.rresp(0); //okay\n\t Vector#(4,Bit#(32)) words = replicate(rdata.data);\n\t axiMaster.rdata(pack(words));\n\t axiMaster.rid(extend(rtag));\n\t axiMaster.rlast(rdata.last?1:0); // added\n      endrule\n\n// req_aw (M=>S)\n      let awreadyProbe <- mkProbe();\n      rule rl_awvalid_awaddr;\n\t let awready = pack(awfifo.notFull && awtagfifo.notFull);\n\t awreadyProbe <= awready;\n\t axiMaster.awready(awready);\n      endrule\n      rule rl_awfifo if (axiMaster.awvalid() == 1);\n\t Bit#(PhysMemAddrWidth) addr = truncate(axiMaster.awaddr());\n\t let burstLen = extend(axiMaster.awlen+1) << beatShift; // calculate burstLen\n\t let tag = axiMaster.awid();\n\t awfifo.enq(PhysMemRequest{ addr: addr, tag: truncate(tag), burstLen: burstLen }); // burstlen corrected\n\t awtagfifo.enq(tuple2(tag, addr[3:2])); // what if the single request with multiple transfer??\n      endrule\n\n// resp_wr (M=>S) sending data\n      let wreadyProbe <- mkProbe();\n      rule rl_wready;\n\t let wready = pack(wfifo.notFull && awtagfifo.notEmpty && wtagfifo.notFull);\n\t wreadyProbe <= wready;\n\t axiMaster.wready(wready);\n      endrule\n      rule rl_wdata if (axiMaster.wvalid() == 1);\n\t let last = axiMaster.wlast == 1;\n\t match { .tag, .lane } = awtagfifo.first;\n\t Vector#(4, Bit#(PhysMemDataWidth)) words = unpack(axiMaster.wdata());\n\t wfifo.enq(MemData { data: words[lane], tag: truncate(tag), last: last});\n\t if (last) begin\n\t    awtagfifo.deq();\n\t    wtagfifo.enq(tag);\n\t end\n      endrule\n\n// resp_b (S=>M) \n      let bvalidProbe <- mkProbe();\n      rule rl_bvalid;\n\t let bvalid = pack(wtagfifo.notEmpty && bfifo.notEmpty);\n\t bvalidProbe <= bvalid;\n\t axiMaster.bvalid(bvalid);\n      endrule\n      rule rl_done if (axiMaster.bready() == 1);\n\t let tag <- toGet(bfifo).get();\n\t let awtag <- toGet(wtagfifo).get();\n\t axiMaster.bid(awtag);\n\t axiMaster.bresp(0); //okay\n\t // where is b_resp?\n      endrule\n\n      interface PhysMemReadClient read_client;\n\t interface Get readReq = toGet(arfifo);\n\t interface Put readData = toPut(rfifo);\n      endinterface\n      interface PhysMemWriteClient write_client;\n\t interface Get writeReq = toGet(awfifo);\n\t interface Get writeData = toGet(wfifo);\n\t interface Put writeDone = toPut(bfifo);\n      endinterface\n   endmodule\nendinstance: MkPhysMemMaster\n\ninstance MkPhysMemSlave#(Axi4SlaveLiteBits#(axiAddrWidth,dataWidth),addrWidth,dataWidth)\n      provisos (Add#(axiAddrWidth,a__,addrWidth));\n   module mkPhysMemSlave#(Axi4SlaveLiteBits#(axiAddrWidth,dataWidth) axiSlave)(PhysMemSlave#(addrWidth,dataWidth));\n      FIFOF#(PhysMemRequest#(addrWidth,dataWidth)) arfifo <- mkAxiFifoF();\n      FIFOF#(MemData#(dataWidth)) rfifo <- mkAxiFifoF();\n      FIFOF#(PhysMemRequest#(addrWidth,dataWidth)) awfifo <- mkAxiFifoF();\n      FIFOF#(MemData#(dataWidth)) wfifo <- mkAxiFifoF();\n      FIFOF#(Bit#(MemTagSize)) bfifo <- mkAxiFifoF();\n      FIFOF#(Bit#(MemTagSize)) rtagfifo <- mkAxiFifoF();\n      FIFOF#(Bit#(MemTagSize)) wtagfifo <- mkAxiFifoF();\n\n      rule rl_arvalid_araddr;\n\t axiSlave.arvalid(pack(arfifo.notEmpty && rtagfifo.notFull));\n\t let addr = 0;\n\t if (arfifo.notEmpty)\n\t    addr = truncate(arfifo.first.addr);\n\t axiSlave.araddr(addr);\n      endrule\n      rule rl_arfifo if (axiSlave.arready() == 1);\n\t let req <- toGet(arfifo).get();\n\t rtagfifo.enq(req.tag);\n      endrule\n      rule rl_rready;\n\t axiSlave.rready(pack(rfifo.notFull && rtagfifo.notEmpty));\n      endrule\n      rule rl_rdata if (axiSlave.rvalid() == 1);\n\t let rtag <- toGet(rtagfifo).get();\n\t rfifo.enq(MemData { data: axiSlave.rdata(), tag: rtag } );\n      endrule\n\n      rule rl_awvalid_awaddr;\n\t axiSlave.awvalid(pack(awfifo.notEmpty && wtagfifo.notFull));\n\t let addr = 0;\n\t if (awfifo.notEmpty)\n\t    addr = truncate(awfifo.first.addr);\n\t axiSlave.awaddr(addr);\n      endrule\n      rule rl_awfifo if (axiSlave.awready() == 1);\n\t let req <- toGet(awfifo).get();\n\t wtagfifo.enq(req.tag);\n      endrule\n      rule rl_wvalid;\n\t axiSlave.wvalid(pack(wfifo.notEmpty));\n      endrule\n      rule rl_wdata if (axiSlave.wready() == 1);\n\t let wdata = wfifo.first.data;\n\t wfifo.deq();\n\t axiSlave.wdata(wdata);\n      endrule\n      rule rl_bready;\n\t axiSlave.bready(pack(wtagfifo.notEmpty && bfifo.notFull));\n      endrule\n      rule rl_done if (axiSlave.bvalid() == 1);\n\t let tag <- toGet(wtagfifo).get();\n\t bfifo.enq(tag);\n      endrule\n\n      interface PhysMemReadServer read_server;\n\t interface Put readReq = toPut(arfifo);\n\t interface Get readData = toGet(rfifo);\n      endinterface\n      interface PhysMemWriteServer write_server;\n\t interface Put writeReq = toPut(awfifo);\n\t interface Put writeData = toPut(wfifo);\n\t interface Get writeDone = toGet(bfifo);\n      endinterface\n   endmodule\nendinstance\n\n`ifdef BLUECHECK\nimport BlueCheck::*;\nimport StmtFSM::*;\n\nmodule [BlueCheck] mkPhysMemSlaveSpec();\n   /* This function allows us to make assertions in the properties */\n   Ensure ensure <- getEnsure;\n   Ensure ensure1 <- getEnsure;\n   Bit#(BurstLenSize) bytesPerBeat = 16;\n   let dataSizeMask = bytesPerBeat-1;\n\n   function Stmt checkLen(Bit#(8) burstLen8) =\n   seq\n      action\n\t Bit#(BurstLenSize) burstLen = extend(burstLen8);\n\t PhysMemRequest#(16,128) pmr = PhysMemRequest { addr: 0, burstLen: burstLen };\n\t Axi4ReadRequest#(16,6) amr = toAxi4ReadRequest(pmr);\n\t Bit#(8) expectedValue = truncate((burstLen + dataSizeMask) / bytesPerBeat - 1);\n\t //$display(\"burstLen=%d arm.len=%x bytesPerBeat=%x dataSizeMask=%x expectedValue=%x\", burstLen, amr.len, bytesPerBeat, dataSizeMask, expectedValue);\n\t ensure(extend(amr.len) == expectedValue);\n\t ensure1 ((burstLen == 0) || ((extend(amr.len)+1) * bytesPerBeat >= burstLen));\n      endaction\n   endseq;\n\n   function Stmt checkSize(Bit#(8) burstLen8) =\n   seq\n      action\n\t Bit#(BurstLenSize) burstLen = extend(burstLen8);\n\t PhysMemRequest#(16,128) pmr = PhysMemRequest { addr: 0, burstLen: burstLen };\n\t Axi4ReadRequest#(16,6) amr = toAxi4ReadRequest(pmr);\n\t Bit#(3) expectedValue = axiBusSizeBytes(16);\n\t //$display(\"burstLen=%d amr.size=%x expectedValue=%x\", burstLen, amr.size, expectedValue);\n\t ensure((burstLen == 0) || (extend(amr.size) == expectedValue));\n      endaction\n   endseq;\n\n   prop(\"checkLen\", checkLen);\n   prop(\"checkSize\", checkSize);\nendmodule\n\nmodule [Module] mkMkPhysMemSlaveChecker();\n   blueCheck(mkPhysMemSlaveSpec);\nendmodule\n\n`endif\n\n\n`ifdef FOOBAR\n//FIXME burst transfers\ninstance MkPhysMemSlave#(Axi4SlaveBits#(axiAddrWidth,dataWidth,tagWidth,Empty),addrWidth,dataWidth)\n      provisos (Add#(axiAddrWidth,a__,addrWidth),\n\t\tAdd#(b__, tagWidth, 6));\n   module mkPhysMemSlave#(Axi4SlaveBits#(axiAddrWidth,dataWidth,tagWidth,Empty) axiSlave)(PhysMemSlave#(addrWidth,dataWidth));\n      FIFOF#(PhysMemRequest#(addrWidth,dataWidth)) arfifo <- mkAxiFifoF();\n      FIFOF#(MemData#(dataWidth)) rfifo <- mkAxiFifoF();\n      FIFOF#(PhysMemRequest#(addrWidth,dataWidth)) awfifo <- mkAxiFifoF();\n      FIFOF#(MemData#(dataWidth)) wfifo <- mkAxiFifoF();\n      FIFOF#(Bit#(TDiv#(dataWidth,8))) wstrbfifo <- mkAxiFifoF();\n      FIFOF#(Bit#(MemTagSize)) bfifo <- mkAxiFifoF();\n      FIFOF#(Bit#(MemTagSize)) rtagfifo <- mkAxiFifoF();\n      FIFOF#(Bit#(MemTagSize)) wtagfifo <- mkAxiFifoF();\n\n      let dataWidthBytes = valueOf(TDiv#(dataWidth,8));\n      let dataSizeMask = dataWidthBytes-1;\n\n      rule rl_arvalid;\n\t axiSlave.arvalid(pack(arfifo.notEmpty && rtagfifo.notFull));\n      endrule\n      rule rl_araddr if (arfifo.notEmpty);\n\t let req = arfifo.first;\n\t Axi4ReadRequest#(axiAddrWidth,tagWidth) axireq = toAxi4ReadRequest(req);\n\t axiSlave.araddr(axireq.address);\n\t axiSlave.arid(axireq.id);\n\t axiSlave.arlen(axireq.len);\n\t axiSlave.arsize(axireq.size);\n\t axiSlave.arburst(2'b01);\n\t axiSlave.arprot(3'b000);\n\t axiSlave.arcache(4'b1111); // was 4'b0011\n      endrule\n      rule rl_arfifo if (axiSlave.arready() == 1);\n\t let req <- toGet(arfifo).get();\n\n\t rtagfifo.enq(req.tag);\n      endrule\n      rule rl_rready;\n\t axiSlave.rready(pack(rfifo.notFull && rtagfifo.notEmpty));\n      endrule   \n      rule rl_rdata if (axiSlave.rvalid() == 1);\n\t let rtag <- toGet(rtagfifo).get();\n\t rfifo.enq(MemData { data: axiSlave.rdata(), tag: rtag } );\n      endrule\n\n      rule rl_awvalid;\n\t axiSlave.awvalid(pack(awfifo.notEmpty && wtagfifo.notFull));\n      endrule\n      rule rl_awaddr if (awfifo.notEmpty);\n\t let req = awfifo.first;\n\n\t let dataWidthBytes = valueOf(TDiv#(dataWidth,8));\n\t let dataSizeMask = dataWidthBytes-1;\n\t let reqsize = req.burstLen & fromInteger(dataSizeMask);\n\t Axi4WriteRequest#(axiAddrWidth,tagWidth) axireq = toAxi4WriteRequest(req);\n\t axiSlave.awaddr(axireq.address);\n\t axiSlave.awid(axireq.id);\n\t axiSlave.awlen(axireq.len);\n\t axiSlave.awsize(axireq.size);\n\t axiSlave.awburst(2'b01);\n\t axiSlave.awprot(3'b000);\n\t axiSlave.awcache(4'b0011);\n\t //FIXME should go in toAxi4WriteRequest\n\t Bit#(TDiv#(dataWidth,8)) wstrb = (1 << reqsize) - 1;\n\t wstrbfifo.enq(wstrb);\n      endrule   \n      rule rl_awfifo if (axiSlave.awready() == 1);\n\t let req <- toGet(awfifo).get();\n\t wtagfifo.enq(req.tag);\n      endrule\n      rule rl_wvalid;\n\t axiSlave.wvalid(pack(wfifo.notEmpty));\n      endrule\n      rule rl_wdata if (axiSlave.wready() == 1);\n\t let md <- toGet(wfifo).get();\n\t let wdata = md.data;\n\t axiSlave.wdata(wdata);\n\t axiSlave.wlast(pack(wfifo.first.last));\n\t axiSlave.wstrb(wstrbfifo.first);\n\t if (wfifo.first.last)\n\t    wstrbfifo.deq();\n      endrule\n      rule rl_bready;\n\t axiSlave.bready(pack(wtagfifo.notEmpty && bfifo.notFull));\n      endrule   \n      rule rl_done if (axiSlave.bvalid() == 1);\n\t let tag <- toGet(wtagfifo).get();\n\t bfifo.enq(extend(axiSlave.bid()));\n      endrule\n\n      interface PhysMemReadServer read_server;\n\t interface Put readReq = toPut(arfifo);\n\t interface Get readData = toGet(rfifo);\n      endinterface   \n      interface PhysMemWriteServer write_server;\n\t interface Put writeReq = toPut(awfifo);\n\t interface Put writeData = toPut(wfifo);\n\t interface Get writeDone = toGet(bfifo);\n      endinterface   \n   endmodule   \nendinstance\n`endif // FOOBAR\n\ntypeclass PhysMemSlaveExtra#(type extraType);\n   function Action extra_r(extraType ex);\n   function Action extra_w(extraType ex);\nendtypeclass\n\ninstance MkPhysMemSlave#(Axi4SlaveBits#(axiAddrWidth,128,idWidth,extraType),addrWidth,dataBusWidth)\n      provisos (Add#(addrWidth,a__,axiAddrWidth)\n\t\t, Add#(b__, idWidth, MemTagSize)\n\t\t, Add#(dw__, dataBusWidth, 128)\n\t\t, PhysMemSlaveExtra#(extraType));\n   module mkPhysMemSlave#(Axi4SlaveBits#(axiAddrWidth,128,idWidth,extraType) axiSlave)(PhysMemSlave#(addrWidth,dataBusWidth));\n      FIFOF#(PhysMemRequest#(addrWidth,dataBusWidth)) arfifo <- mkAxiFifoF();\n      FIFOF#(MemData#(dataBusWidth)) rfifo <- mkAxiFifoF();\n      FIFOF#(PhysMemRequest#(addrWidth,dataBusWidth)) awfifo <- mkAxiFifoF();\n      FIFOF#(MemData#(dataBusWidth)) wfifo <- mkAxiFifoF();\n      FIFOF#(Bit#(MemTagSize)) bfifo <- mkAxiFifoF();\n\n      FIFOF#(Bool) arInFlight <- mkSizedFIFOF(valueOf(TExp#(MemTagSize)));\n      FIFOF#(Bool) awInFlight <- mkSizedFIFOF(valueOf(TExp#(MemTagSize)));\n\n\tProbe#(Bit#(1)) arNF <- mkProbe();\n\tProbe#(Bit#(1)) arNE <- mkProbe();\n\tProbe#(Bit#(1)) rNF <- mkProbe();\n\tProbe#(Bit#(1)) rNE <- mkProbe();\n\tProbe#(Bit#(1)) awNF <- mkProbe();\n\tProbe#(Bit#(1)) awNE <- mkProbe();\n\tProbe#(Bit#(1)) wNF <- mkProbe();\n\tProbe#(Bit#(1)) wNE <- mkProbe();\n\tProbe#(Bit#(1)) bNF <- mkProbe();\n\tProbe#(Bit#(1)) bNE <- mkProbe();\n\tProbe#(Bit#(1)) arInFlightNF <- mkProbe();\n\tProbe#(Bit#(1)) arInFlightNE <- mkProbe();\n\tProbe#(Bit#(1)) awInFlightNF <- mkProbe();\n\tProbe#(Bit#(1)) awInFlightNE <- mkProbe();\n\n\trule probe_val;\n\t\tarNF <= pack(arfifo.notFull());\n\t\tarNE <= pack(arfifo.notEmpty());\n\t\trNF <= pack(rfifo.notFull());\n\t\trNE <= pack(rfifo.notEmpty());\n\t\tawNF <= pack(awfifo.notFull());\n\t\tawNE <= pack(awfifo.notEmpty());\n\t\twNF <= pack(wfifo.notFull());\n\t\twNE <= pack(wfifo.notEmpty());\n\t\tbNF <= pack(bfifo.notFull());\n\t\tbNE <= pack(bfifo.notEmpty());\n\t\t\n\t\tarInFlightNF <= pack(arInFlight.notFull());\n\t\tarInFlightNE <= pack(arInFlight.notEmpty());\n\t\tawInFlightNF <= pack(awInFlight.notFull());\n\t\tawInFlightNE <= pack(awInFlight.notEmpty());\n\tendrule\n\n      rule rl_arvalid_araddr;\n\t axiSlave.arvalid(pack(arfifo.notEmpty && arInFlight.notFull));\n      endrule\n      rule rl_arfifo if (axiSlave.arready() == 1);\n\t let req <- toGet(arfifo).get();\n\t Axi4ReadRequest#(addrWidth,idWidth) axireq = toAxi4ReadRequest(req);\n\t axiSlave.araddr(extend(axireq.address));\n\t axiSlave.arid(axireq.id);\n\t axiSlave.arsize(axireq.size);\n\t axiSlave.arlen(axireq.len);\n\t axiSlave.arburst(2'b01);     // burst: INCR\n\t axiSlave.arcache(4'b0011);   // FIXME: 0011? 1111?\n\t axiSlave.arlock(2'b0);       // normal access\n\t axiSlave.arprot(3'b0);       // unprevileged, protected, data access\n\t axiSlave.arqos(4'b0);        // unused - default 0\n\t extra_r(axiSlave.extra); // unused\n\t arInFlight.enq(True);\n      endrule\n      rule rl_rready;\n\t axiSlave.rready(pack(rfifo.notFull && arInFlight.notEmpty));\n      endrule\n      rule rl_rdata if (axiSlave.rvalid() == 1);\n\t let dummy = arInFlight.first; // implicit guard (arInFlight should not be empty to fire this rule)\n\t let last = axiSlave.rlast == 1;\n\t if (last) arInFlight.deq;\n\n\t rfifo.enq(MemData { data: truncate(axiSlave.rdata()), tag: extend(axiSlave.rid()), last: last } );\n      endrule\n\n      rule rl_awvalid_awaddr;\n\t axiSlave.awvalid(pack(awfifo.notEmpty && awInFlight.notFull));\n      endrule\n      rule rl_awfifo if (axiSlave.awready() == 1);\n\t let req <- toGet(awfifo).get();\n\t Axi4WriteRequest#(addrWidth,idWidth) axireq = toAxi4WriteRequest(req);\n\t axiSlave.awaddr(extend(axireq.address));\n\t axiSlave.awid(axireq.id);\n\t axiSlave.awsize(axireq.size);\n\t axiSlave.awlen(axireq.len);\n\t axiSlave.awburst(2'b01);     // burst: INCR\n\t axiSlave.awcache(4'b0011);   // FIXME: 0011? 1111?\n\t axiSlave.awlock(2'b0);       // normal access \n\t axiSlave.awprot(3'b0);       // unprevileged, protedted, data access\n\t axiSlave.awqos(4'b0);        // unused - default 0\n\t extra_w(axiSlave.extra);\n\t awInFlight.enq(True);\n      endrule\n      rule rl_wvalid;\n\t axiSlave.wvalid(pack(wfifo.notEmpty));\n      endrule\n      rule rl_wdata if (axiSlave.wready() == 1);\n\t let wdata = wfifo.first.data;\n\t let last = wfifo.first.last;\n\t wfifo.deq();\n\t axiSlave.wdata(extend(wdata));\n\t axiSlave.wlast(pack(last));\n\t axiSlave.wstrb(16'hFFFF); // using full 128-bit\n\t // wid deprecated; the master must issue the data in the same order in which it issued the write address (aw_req)\n      endrule\n      rule rl_bready;\n\t axiSlave.bready(pack(awInFlight.notEmpty && bfifo.notFull));\n      endrule\n      rule rl_done if (axiSlave.bvalid() == 1);\n\t let tag <- toGet(awInFlight).get();\n\t bfifo.enq(extend(axiSlave.bid()));\n      endrule\n\n      interface PhysMemReadServer read_server;\n\t interface Put readReq = toPut(arfifo);\n\t interface Get readData = toGet(rfifo);\n      endinterface\n      interface PhysMemWriteServer write_server;\n\t interface Put writeReq = toPut(awfifo);\n\t interface Put writeData = toPut(wfifo);\n\t interface Get writeDone = toGet(bfifo);\n      endinterface\n   endmodule\nendinstance\n\n\ntypeclass AxiToMemReadClient#(type objIdType, numeric type axiAddrWidth, numeric type dataWidth);\n   module mkMemReadClient#(objIdType objId, Axi4MasterBits#(axiAddrWidth,dataWidth,MemTagSize,Empty) m)(MemReadClient#(dataWidth));\n   module mkMemWriteClient#(objIdType objId, Axi4MasterBits#(axiAddrWidth,dataWidth,MemTagSize,Empty) m)(MemWriteClient#(dataWidth));\nendtypeclass\ntypeclass AxiToPhysMemReadClient#(numeric type axiAddrWidth, numeric type dataWidth, numeric type idWidth, type extra);\n   module mkPhysMemReadClient#(Axi4MasterBits#(axiAddrWidth,dataWidth,idWidth,extra) m)(PhysMemReadClient#(axiAddrWidth,dataWidth));\n   module mkPhysMemWriteClient#(Axi4MasterBits#(axiAddrWidth,dataWidth,idWidth,extra) m)(PhysMemWriteClient#(axiAaddrWidth,dataWidth));\nendtypeclass\n\ninstance AxiToMemReadClient#(Bit#(32),32,dataWidth);\n   module mkMemReadClient#(Bit#(32) objId, Axi4MasterBits#(32,dataWidth,MemTagSize,Empty) m)(MemReadClient#(dataWidth));\n\n      let clock <- exposeCurrentClock();\n      let mClock = clockOf(m);\n      let reset <- exposeCurrentReset();\n      let mReset = resetOf(m);\n\n      Wire#(Bit#(1)) arready <- mkDWire(0, clocked_by mClock, reset_by mReset);\n      Wire#(Bit#(1)) rvalid <- mkDWire(0, clocked_by mClock, reset_by mReset);\n      Wire#(Bit#(MemTagSize)) rid <- mkDWire(0, clocked_by mClock, reset_by mReset);\n      Wire#(Bit#(2)) rresp <- mkDWire(0, clocked_by mClock, reset_by mReset);\n      Wire#(Bit#(dataWidth)) rdata <- mkDWire(0, clocked_by mClock, reset_by mReset);\n      Wire#(Bit#(1)) rlast <- mkDWire(0, clocked_by mClock, reset_by mReset);\n\n      FIFOF#(MemRequest)          arfifo;\n      FIFOF#(MemData#(dataWidth))  rfifo;\n      if ( isAncestor(clock, mClock)) begin\n\t arfifo <- mkCFFIFOF();\n\t rfifo  <- mkCFFIFOF();\n      end\n      else begin\n\t arfifo <- mkDualClockBramFIFOF(mClock, mReset, clock, reset);\n\t rfifo  <- mkDualClockBramFIFOF(clock, reset, mClock, mReset);\n      end\n\n      rule rl_araddr if (m.arvalid() == 1);\n\t let addr = m.araddr();   \n\t let burstLenBytes = (extend(m.arlen())+1)*fromInteger(valueOf(TDiv#(dataWidth,8)));\n\t arfifo.enq(MemRequest { sglId: objId, offset: extend(addr), burstLen: burstLenBytes, tag: extend(m.arid()) });\n      endrule\n      rule handshake_ar;\n\t   m.arready(pack(arfifo.notFull()));\n      endrule\n\n      rule rl_rdata if (m.rready() == 1);\n\t let md <- toGet(rfifo).get();\n\t rdata <= md.data;\n\t rlast <= pack(md.last);\n\t rresp <= 0;\n\t rid <= truncate(md.tag);\n      endrule\n      rule handshake_rdata;\n\t m.rvalid(pack(rfifo.notEmpty()));\n\t m.rid(rid);\n\t m.rresp(rresp);\n\t m.rdata(rdata);\n\t m.rlast(rlast);\n      endrule\n\n      interface Get readReq = toGet(arfifo);\n      interface Put readData = toPut(rfifo);\n   endmodule\n\n   module mkMemWriteClient#(Bit#(32) objId, Axi4MasterBits#(32,dataWidth,MemTagSize,Empty) m)(MemWriteClient#(dataWidth));\n\n      let clock <- exposeCurrentClock();\n      let mClock = clockOf(m);\n      let reset <- exposeCurrentReset();\n      let mReset = resetOf(m);\n\n      Wire#(Bit#(1)) awready <- mkDWire(0, clocked_by mClock, reset_by mReset);\n      Wire#(Bit#(1)) wready <- mkDWire(0, clocked_by mClock, reset_by mReset);\n      Wire#(Bit#(1)) bvalid <- mkDWire(0, clocked_by mClock, reset_by mReset);\n      Wire#(Bit#(MemTagSize)) bid <- mkDWire(0, clocked_by mClock, reset_by mReset);\n      Wire#(Bit#(2)) bresp <- mkDWire(0, clocked_by mClock, reset_by mReset);\n\n      FIFOF#(MemRequest)       awfifo;\n      FIFOF#(MemData#(dataWidth)) wfifo;\n      FIFOF#(Bit#(MemTagSize))    bfifo;\n      if ( isAncestor(clock, mClock)) begin\n\t awfifo   <- mkCFFIFOF();\n\t wfifo <- mkCFFIFOF();\n\t bfifo <- mkCFFIFOF();\n      end\n      else begin\n\t awfifo   <- mkDualClockBramFIFOF(mClock, mReset, clock, reset);\n\t wfifo <- mkDualClockBramFIFOF(mClock, mReset, clock, reset);\n\t bfifo <- mkDualClockBramFIFOF(clock, reset, mClock, mReset);\n      end\n\n      rule rl_awaddr if (m.awvalid() == 1);\n\t let addr = m.awaddr();\n\t let burstLenBytes = (extend(m.awlen())+1)*fromInteger(valueOf(TDiv#(dataWidth,8)));\n\t awfifo.enq(MemRequest { sglId: objId, offset: extend(addr), burstLen: burstLenBytes, tag: extend(m.awid()) });\n      endrule\n      rule handshake_awaddr;\n\t m.awready(pack(awfifo.notFull()));\n      endrule\n\n      rule rl_wdata if (m.wvalid() == 1);\n\t wfifo.enq(MemData { data: m.wdata(), last: unpack(m.wlast()), tag: extend(m.wid()) });\n      endrule\n      rule handshake_wdata;\n\t m.wready(pack(wfifo.notFull()));\n      endrule\n\n      rule rl_bresp if (m.bready() == 1);\n\t let tag <- toGet(bfifo).get();\n\t bresp <= 0;\n\t bid <= truncate(tag);\n      endrule\n      rule handshake_b;\n\t   m.bvalid(pack(bfifo.notEmpty()));\n\t   m.bid(bid);\n\t   m.bresp(bresp);\n      endrule\n\n      interface Get writeReq = toGet(awfifo);\n      interface Get writeData = toGet(wfifo);\n      interface Put writeDone = toPut(bfifo);\n   endmodule\nendinstance\n\ninterface GetObjId#(numeric type addrWidth);\n   method SGLId objId(Bit#(addrWidth) axiAddr);\n   method Bit#(MemOffsetSize) addr(Bit#(addrWidth) axiAddr);\nendinterface\ninstance AxiToMemReadClient#(GetObjId#(32),32,dataWidth);\n   module mkMemReadClient#(GetObjId#(32) objId, Axi4MasterBits#(32,dataWidth,MemTagSize,Empty) m)(MemReadClient#(dataWidth));\n\n      let clock <- exposeCurrentClock();\n      let mClock = clockOf(m);\n      let reset <- exposeCurrentReset();\n      let mReset = resetOf(m);\n\n      Wire#(Bit#(1)) arready <- mkDWire(0, clocked_by mClock, reset_by mReset);\n      Wire#(Bit#(1)) rvalid <- mkDWire(0, clocked_by mClock, reset_by mReset);\n      Wire#(Bit#(MemTagSize)) rid <- mkDWire(0, clocked_by mClock, reset_by mReset);\n      Wire#(Bit#(2)) rresp <- mkDWire(0, clocked_by mClock, reset_by mReset);\n      Wire#(Bit#(dataWidth)) rdata <- mkDWire(0, clocked_by mClock, reset_by mReset);\n      Wire#(Bit#(1)) rlast <- mkDWire(0, clocked_by mClock, reset_by mReset);\n\n      FIFOF#(MemRequest)          arfifo;\n      FIFOF#(MemData#(dataWidth))  rfifo;\n      if ( isAncestor(clock, mClock)) begin\n\t arfifo <- mkCFFIFOF();\n\t rfifo  <- mkCFFIFOF();\n      end\n      else begin\n\t arfifo <- mkDualClockBramFIFOF(mClock, mReset, clock, reset);\n\t rfifo  <- mkDualClockBramFIFOF(clock, reset, mClock, mReset);\n      end\n\n      rule rl_araddr if (m.arvalid() == 1);\n\t let addr = m.araddr();\n\t let burstLenBytes = (extend(m.arlen())+1)*fromInteger(valueOf(TDiv#(dataWidth,8)));\n\t arfifo.enq(MemRequest { sglId: objId.objId(addr), offset: objId.addr(addr), burstLen: burstLenBytes, tag: extend(m.arid()) });\n      endrule\n      rule handshake_ar;\n\t   m.arready(pack(arfifo.notFull()));\n      endrule\n\n      rule rl_rdata if (m.rready() == 1);\n\t let md <- toGet(rfifo).get();\n\t rdata <= md.data;\n\t rlast <= pack(md.last);\n\t rresp <= 0;\n\t rid <= truncate(md.tag);\n      endrule\n      rule handshake_rdata;\n\t m.rvalid(pack(rfifo.notEmpty()));\n\t m.rid(rid);\n\t m.rresp(rresp);\n\t m.rdata(rdata);\n\t m.rlast(rlast);\n      endrule\n\n      interface Get readReq = toGet(arfifo);\n      interface Put readData = toPut(rfifo);\n   endmodule\n\n   module mkMemWriteClient#(GetObjId#(32) objId, Axi4MasterBits#(32,dataWidth,MemTagSize,Empty) m)(MemWriteClient#(dataWidth));\n\n      let clock <- exposeCurrentClock();\n      let mClock = clockOf(m);\n      let reset <- exposeCurrentReset();\n      let mReset = resetOf(m);\n\n      Wire#(Bit#(1)) awready <- mkDWire(0, clocked_by mClock, reset_by mReset);\n      Wire#(Bit#(1)) wready <- mkDWire(0, clocked_by mClock, reset_by mReset);\n      Wire#(Bit#(1)) bvalid <- mkDWire(0, clocked_by mClock, reset_by mReset);\n      Wire#(Bit#(MemTagSize)) bid <- mkDWire(0, clocked_by mClock, reset_by mReset);\n      Wire#(Bit#(2)) bresp <- mkDWire(0, clocked_by mClock, reset_by mReset);\n\n      FIFOF#(MemRequest)       awfifo;\n      FIFOF#(MemData#(dataWidth)) wfifo;\n      FIFOF#(Bit#(MemTagSize))    bfifo;\n      if ( isAncestor(clock, mClock)) begin\n\t awfifo   <- mkCFFIFOF();\n\t wfifo <- mkCFFIFOF();\n\t bfifo <- mkCFFIFOF();\n      end\n      else begin\n\t awfifo   <- mkDualClockBramFIFOF(mClock, mReset, clock, reset);\n\t wfifo <- mkDualClockBramFIFOF(mClock, mReset, clock, reset);\n\t bfifo <- mkDualClockBramFIFOF(clock, reset, mClock, mReset);\n      end\n\n      rule rl_awaddr if (m.awvalid() == 1);\n\t let addr = m.awaddr();\n\t let burstLenBytes = (extend(m.awlen())+1)*fromInteger(valueOf(TDiv#(dataWidth,8)));\n\t awfifo.enq(MemRequest { sglId: objId.objId(addr), offset: objId.addr(addr), burstLen: burstLenBytes, tag: extend(m.awid()) });\n      endrule\n      rule handshake_awaddr;\n\t m.awready(pack(awfifo.notFull()));\n      endrule\n\n      rule rl_wdata if (m.wvalid() == 1);\n\t wfifo.enq(MemData { data: m.wdata(), last: unpack(m.wlast()), tag: extend(m.wid()) });\n      endrule\n      rule handshake_wdata;\n\t m.wready(pack(wfifo.notFull()));\n      endrule\n\n      rule rl_bresp if (m.bready() == 1);\n\t let tag <- toGet(bfifo).get();\n\t bresp <= 0;\n\t bid <= truncate(tag);\n      endrule\n      rule handshake_b;\n\t   m.bvalid(pack(bfifo.notEmpty()));\n\t   m.bid(bid);\n\t   m.bresp(bresp);\n      endrule\n\n      interface Get writeReq = toGet(awfifo);\n      interface Get writeData = toGet(wfifo);\n      interface Put writeDone = toPut(bfifo);\n   endmodule\nendinstance\n\ntypedef AxiMasterBits#(32,32,12,Empty) Pps7Maxigp;\ntypedef AxiSlaveBits#(32,32,6,Empty) Pps7Saxigp;\ntypedef AxiSlaveBits#(32,64,6,HPType) Pps7Saxihp;\ntypedef AxiSlaveBits#(32,64,3,ACPType) Pps7Saxiacp;\n"
  },
  {
    "path": "bsv/AxiDdr3Controller.bsv",
    "content": "// Copyright (c) 2015 Connectal Project\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\nimport Clocks          ::*;\nimport GetPut          ::*;\nimport ClientServer    ::*;\nimport AxiDdr3Wrapper  ::*;\nimport AxiBits         ::*;\nimport AxiGather       ::*;\nimport Axi4MasterSlave ::*;\nimport ConnectalClocks ::*;\n`include \"ConnectalProjectConfig.bsv\"\n\ntypedef 30 Ddr3AddrWidth;\ntypedef 512 Ddr3DataWidth;\n\ninterface Ddr3Pins;\n   interface AxiDdr3Ddr3 ddr3;\n   interface Clock sysclk_deleteme_unused_clock;\n   interface Reset sysrst_deleteme_unused_reset;\nendinterface\n\ninterface Ddr3;\n   interface Axi4Slave#(Ddr3AddrWidth,Ddr3DataWidth,6) slave;\n   interface Ddr3Pins ddr3; // pins\n   interface Clock uiClock;\n   interface Reset uiReset;\nendinterface\n\nfunction Axi4SlaveBits#(Ddr3AddrWidth,Ddr3DataWidth,6,Empty) toAxiSlaveBits(AxiDdr3S_axi s_axi);\n   return (interface Axi4SlaveBits;\n      method araddr = s_axi.araddr;\n      method arburst = s_axi.arburst;\n      method arcache = s_axi.arcache;\n      method Bit#(1) aresetn(); return 1; endmethod\n      method arid = s_axi.arid;\n      method arlen = s_axi.arlen;\n      method Action arlock(Bit#(2) l); s_axi.arlock(truncate(l)); endmethod //unused\n      method arprot = s_axi.arprot;\n      method arqos = s_axi.arqos;\n      method arready = s_axi.arready;\n      method arsize = s_axi.arsize;\n      method arvalid = s_axi.arvalid;\n      method awaddr = s_axi.awaddr;\n      method awburst = s_axi.awburst;\n      method awcache = s_axi.awcache;\n      method awid = s_axi.awid;\n      method awlen = s_axi.awlen;\n      method Action awlock(Bit#(2) l); s_axi.awlock(truncate(l)); endmethod //unused\n      method awprot = s_axi.awprot;\n      method awqos = s_axi.awqos;\n      method awready = s_axi.awready;\n      method awsize = s_axi.awsize;\n      method awvalid = s_axi.awvalid;\n      method bid = s_axi.bid;\n      method bready = s_axi.bready;\n      method bresp = s_axi.bresp;\n      method bvalid = s_axi.bvalid;\n      method rdata = s_axi.rdata;\n      method rlast = s_axi.rlast;\n      method rready = s_axi.rready;\n      method rresp = s_axi.rresp;\n      method rvalid = s_axi.rvalid;\n      method wdata = s_axi.wdata;\n      method Action wid(Bit#(6) tag); /* no wid method */ endmethod\n      method wlast = s_axi.wlast;\n      method wready = s_axi.wready;\n      method wstrb = s_axi.wstrb;\n      method wvalid = s_axi.wvalid;\n      method rid = s_axi.rid;\n      interface Empty extra; endinterface\n      endinterface);\nendfunction\n\n(* synthesize *)\nmodule mkDdr3#(Clock clk200)(Ddr3);\n   let clock <- exposeCurrentClock();\n   let reset <- exposeCurrentReset();\n\n   Reset rst200 <- mkSyncReset( 10, reset, clk200 );\n\n`ifndef BSV_POSITIVE_RESET\n   let mcReset = rst200;\n`else\n   // fixme later\n`endif\n\n   //fixme mc.aresetn\n\n\n   let aresetn        <- mkB2R(clocked_by clk200, reset_by mcReset);\n   AxiDdr3     mc <- mkAxiDdr3(clk200, mcReset, aresetn.r);\n   let ui_reset_n <- mkResetInverter(mc.ui_clk_sync_rst, clocked_by mc.ui_clk);\n   let ui_reset_b <- mkR2B(ui_reset_n);\n   rule rl_aresetn;\n         aresetn.inputreset(ui_reset_b.o);\n   endrule\n   let axiBits = toAxiSlaveBits(mc.s_axi);\n   Axi4SlaveCommon#(Ddr3AddrWidth,Ddr3DataWidth,6,Empty) axiSlaveCommon <- mkAxi4SlaveGather(axiBits, clocked_by mc.ui_clk, reset_by ui_reset_n);\n\n   rule misc_pins;\n      mc.app.ref_req(0);\n      mc.app.sr_req(0);\n      mc.app.zq_req(0);\n   endrule\n\n   interface slave = axiSlaveCommon.server;\n   interface Ddr3Pins ddr3;\n      interface AxiDdr3Ddr3 ddr3 = mc.ddr3;\n      interface Clock sysclk_deleteme_unused_clock = clock; //fixme\n      interface Reset sysrst_deleteme_unused_reset = reset; //fixme\n   endinterface\n   interface Clock uiClock = mc.ui_clk;\n   interface Reset uiReset = ui_reset_n;\nendmodule\n\nexport Ddr3AddrWidth;\nexport Ddr3DataWidth;\nexport Ddr3Pins(..);\nexport Ddr3(..);\nexport AxiDdr3Ddr3(..);\nexport mkDdr3;\n"
  },
  {
    "path": "bsv/AxiDma.bsv",
    "content": "// Copyright (c) 2013 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n`include \"ConnectalProjectConfig.bsv\"\nimport ConnectalConfig::*;\nimport FIFO::*;\nimport GetPut::*;\nimport ClientServer::*;\nimport AxiMasterSlave::*;\nimport Axi4MasterSlave::*;\nimport ConnectalMemTypes::*;\nimport ConnectalMemory::*;\n\nmodule mkAxiDmaSlave#(PhysMemSlave#(addrWidth,dataWidth) slave) (Axi3Slave#(addrWidth,dataWidth,axiIdSize))\n       provisos (Add#(MemTagSize, sz__, axiIdSize));\n   let beatShift = fromInteger(valueOf(TLog#(TDiv#(dataWidth,8))));\n   interface Put req_ar;\n      method Action put((Axi3ReadRequest#(addrWidth, axiIdSize)) req);\n\t let burstLen = extend(req.len+1) << beatShift;\n\t slave.read_server.readReq.put(PhysMemRequest{addr:req.address, burstLen:burstLen,  tag:truncate(req.id)\n`ifdef BYTE_ENABLES\n\t\t\t\t\t\t      , firstbe: maxBound, lastbe: maxBound\n`endif\n\t\t\t\t\t\t      });\n      endmethod\n   endinterface\n   interface Get resp_read;\n      method ActionValue#(Axi3ReadResponse#(dataWidth, axiIdSize)) get;\n\t let resp <- slave.read_server.readData.get;\n\t return Axi3ReadResponse{data:resp.data, resp:0, last:1, id:extend(resp.tag)};\n      endmethod\n   endinterface\n   interface Put req_aw;\n      method Action put(Axi3WriteRequest#(addrWidth, axiIdSize) req);\n\t let burstLen = extend(req.len+1) << beatShift;\n\t slave.write_server.writeReq.put(PhysMemRequest{addr:req.address, burstLen:burstLen, tag:truncate(req.id)\n`ifdef BYTE_ENABLES\n\t\t\t\t\t\t\t, firstbe: maxBound, lastbe: maxBound\n`endif\n\t\t\t\t\t\t\t});\n      endmethod\n   endinterface\n   interface Put resp_write;\n      method Action put(Axi3WriteData#(dataWidth, axiIdSize) resp);\n\t slave.write_server.writeData.put(MemData{data:resp.data, tag:truncate(resp.id), last: resp.last == 1});\n      endmethod\n   endinterface\n   interface Get resp_b;\n      method ActionValue#(Axi3WriteResponse#(axiIdSize)) get;\n\t let rv <- slave.write_server.writeDone.get;\n\t return Axi3WriteResponse{resp:0, id:extend(rv)};\n      endmethod\n   endinterface\nendmodule\n\nmodule mkAxiDmaMaster#(PhysMemMaster#(addrWidth,dataWidth) master) (Axi3Master#(addrWidth,dataWidth,tagWidth))\n   \n   provisos(Div#(dataWidth,8,dataWidthBytes),\n\t    Mul#(dataWidthBytes,8,dataWidth),\n\t    Log#(dataWidthBytes,beatShift),\n\t    Add#(tagWidth,a__,MemTagSize),\n\t    Add#(TDiv#(dataWidth,8),b__,dataWidthBytes),\n\t    Bits#(Tuple3#(Bit#(8),Bit#(TDiv#(dataWidth,8)),Bit#(TDiv#(dataWidth,8))),c__));\n\n   Reg#(Bit#(8))  burstReg <- mkReg(0);\n   FIFO#(Tuple3#(Bit#(8),Bit#(TDiv#(dataWidth,8)),Bit#(TDiv#(dataWidth,8)))) reqs <- mkSizedFIFO(32);\n   Reg#(Bit#(dataWidthBytes)) lastbeReg <- mkReg(maxBound);\n   \n   let beat_shift = fromInteger(valueOf(beatShift));\n\n   interface Get req_aw;\n      method ActionValue#(Axi3WriteRequest#(addrWidth,tagWidth)) get();\n\t let req <- master.write_client.writeReq.get;\n\t reqs.enq(tuple3(truncate(req.burstLen),reqFirstByteEnable(req),reqLastByteEnable(req)));\n\t return Axi3WriteRequest{address:req.addr, len:truncate((req.burstLen>>beat_shift)-1), id:truncate(req.tag), size: axiBusSize(valueOf(dataWidth)), burst: 1, prot: 0, cache: 15, lock:0, qos:0};\n      endmethod\n   endinterface\n   interface Get resp_write;\n      method ActionValue#(Axi3WriteData#(dataWidth,tagWidth)) get();\n\t let tagdata <- master.write_client.writeData.get();\n\t let burstLen = burstReg;\n\t Bit#(dataWidthBytes) byteEnable = extend((burstLen == 1) ? lastbeReg : maxBound);\n\t if (burstLen == 0) begin\n\t    match { .bl, .firstbe, .lastbe } = reqs.first;\n\t    burstLen = bl >> beat_shift;\n\t    reqs.deq;\n`ifdef BYTE_ENABLES\n\t    byteEnable = extend(firstbe);\n\t    lastbeReg <= lastbe;\n`endif\n\t end\n\t burstReg <= burstLen-1;\n\t Bit#(1) last = burstLen == 1 ? 1'b1 : 1'b0;\n\n\t return Axi3WriteData { data: tagdata.data, byteEnable: byteEnable, last: last, id: truncate(tagdata.tag) };\n      endmethod\n   endinterface\n   interface Put resp_b;\n      method Action put(Axi3WriteResponse#(tagWidth) resp);\n\t master.write_client.writeDone.put(extend(resp.id));\n      endmethod\n   endinterface\n   interface Get req_ar;\n      method ActionValue#(Axi3ReadRequest#(addrWidth,tagWidth)) get();\n\t let req <- master.read_client.readReq.get;\n\t //$display(\"req_ar %h\", req.tag);\n\t return Axi3ReadRequest{address:req.addr, len:truncate((req.burstLen>>beat_shift)-1), id:truncate(req.tag), size: axiBusSize(valueOf(dataWidth)), burst: 1, prot: 0, cache: 15, lock:0, qos:0};\n      endmethod\n   endinterface\n   interface Put resp_read;\n      method Action put(Axi3ReadResponse#(dataWidth,tagWidth) response);\n\t //$display(\"resp_read %h %h\", response.data, response.id);\n\t master.read_client.readData.put(MemData { data: response.data, tag: extend(response.id), last: response.last == 1 });\n      endmethod\n   endinterface\n\nendmodule\n\nmodule mkAxi4DmaSlave#(PhysMemSlave#(addrWidth,dataWidth) slave) (Axi4Slave#(addrWidth,dataWidth,axiIdSize))\n       provisos (Add#(MemTagSize, sz__, axiIdSize));\n   let beatShift = fromInteger(valueOf(TLog#(TDiv#(dataWidth,8))));\n   interface Put req_ar;\n      method Action put((Axi4ReadRequest#(addrWidth, axiIdSize)) req);\n\t let burstLen = extend(req.len+1) << beatShift;\n\t slave.read_server.readReq.put(PhysMemRequest{addr:req.address, burstLen:burstLen,  tag:truncate(req.id)\n`ifdef BYTE_ENABLES\n\t\t\t\t\t\t      , firstbe: maxBound, lastbe: maxBound\n`endif\n\t\t\t\t\t\t      });\n      endmethod\n   endinterface\n   interface Get resp_read;\n      method ActionValue#(Axi4ReadResponse#(dataWidth, axiIdSize)) get;\n\t let resp <- slave.read_server.readData.get;\n\t return Axi4ReadResponse{data:resp.data, resp:0, last:1, id:extend(resp.tag)};\n      endmethod\n   endinterface\n   interface Put req_aw;\n      method Action put(Axi4WriteRequest#(addrWidth, axiIdSize) req);\n\t let burstLen = extend(req.len+1) << beatShift;\n\t slave.write_server.writeReq.put(PhysMemRequest{addr:req.address, burstLen:burstLen, tag:truncate(req.id)\n`ifdef BYTE_ENABLES\n\t\t\t\t\t\t\t, firstbe: maxBound, lastbe: maxBound\n`endif\n\t\t\t\t\t\t\t});\n      endmethod\n   endinterface\n   interface Put resp_write;\n      method Action put(Axi4WriteData#(dataWidth, axiIdSize) resp);\n\t slave.write_server.writeData.put(MemData{data:resp.data, tag:truncate(resp.id), last: resp.last == 1});\n      endmethod\n   endinterface\n   interface Get resp_b;\n      method ActionValue#(Axi4WriteResponse#(axiIdSize)) get;\n\t let rv <- slave.write_server.writeDone.get;\n\t return Axi4WriteResponse{resp:0, id:extend(rv)};\n      endmethod\n   endinterface\nendmodule\n\nmodule mkAxi4DmaMaster#(PhysMemMaster#(addrWidth,dataWidth) master) (Axi4Master#(addrWidth,dataWidth,tagWidth))\n   \n   provisos(Div#(dataWidth,8,dataWidthBytes),\n\t    Mul#(dataWidthBytes,8,dataWidth),\n\t    Log#(dataWidthBytes,beatShift),\n\t    Add#(tagWidth,a__,MemTagSize),\n\t    Add#(TDiv#(dataWidth,8),b__,dataWidthBytes),\n\t    Bits#(Tuple3#(Bit#(8),Bit#(TDiv#(dataWidth,8)),Bit#(TDiv#(dataWidth,8))),c__));\n\n   Reg#(Bit#(8))  burstReg <- mkReg(0);\n   FIFO#(Tuple3#(Bit#(8),Bit#(TDiv#(dataWidth,8)),Bit#(TDiv#(dataWidth,8)))) reqs <- mkSizedFIFO(32);\n   Reg#(Bit#(dataWidthBytes)) lastbeReg <- mkReg(maxBound);\n   \n   let beat_shift = fromInteger(valueOf(beatShift));\n\n   interface Get req_aw;\n      method ActionValue#(Axi4WriteRequest#(addrWidth,tagWidth)) get();\n\t let req <- master.write_client.writeReq.get;\n\t reqs.enq(tuple3(truncate(req.burstLen),reqFirstByteEnable(req),reqLastByteEnable(req)));\n\t return Axi4WriteRequest{address:req.addr, len:truncate((req.burstLen>>beat_shift)-1), id:truncate(req.tag), size: axiBusSize(valueOf(dataWidth)), burst: 1, prot: 0, cache: 15, lock:0, qos:0};\n      endmethod\n   endinterface\n   interface Get resp_write;\n      method ActionValue#(Axi4WriteData#(dataWidth,tagWidth)) get();\n\t let tagdata <- master.write_client.writeData.get();\n\t let burstLen = burstReg;\n\t Bit#(dataWidthBytes) byteEnable = extend((burstLen == 1) ? lastbeReg : maxBound);\n\t if (burstLen == 0) begin\n\t    match { .bl, .firstbe, .lastbe } = reqs.first;\n\t    burstLen = bl >> beat_shift;\n\t    reqs.deq;\n`ifdef BYTE_ENABLES\n\t    byteEnable = extend(firstbe);\n\t    lastbeReg <= lastbe;\n`endif\n\t end\n\t burstReg <= burstLen-1;\n\t Bit#(1) last = burstLen == 1 ? 1'b1 : 1'b0;\n\n\t return Axi4WriteData { data: tagdata.data, byteEnable: byteEnable, last: last, id: truncate(tagdata.tag) };\n      endmethod\n   endinterface\n   interface Put resp_b;\n      method Action put(Axi4WriteResponse#(tagWidth) resp);\n\t master.write_client.writeDone.put(extend(resp.id));\n      endmethod\n   endinterface\n   interface Get req_ar;\n      method ActionValue#(Axi4ReadRequest#(addrWidth,tagWidth)) get();\n\t let req <- master.read_client.readReq.get;\n\t //$display(\"req_ar %h\", req.tag);\n\t return Axi4ReadRequest{address:req.addr, len:truncate((req.burstLen>>beat_shift)-1), id:truncate(req.tag), size: axiBusSize(valueOf(dataWidth)), burst: 1, prot: 0, cache: 15, lock:0, qos:0};\n      endmethod\n   endinterface\n   interface Put resp_read;\n      method Action put(Axi4ReadResponse#(dataWidth,tagWidth) response);\n\t //$display(\"resp_read %h %h\", response.data, response.id);\n\t master.read_client.readData.put(MemData { data: response.data, tag: extend(response.id), last: response.last == 1 });\n      endmethod\n   endinterface\n\nendmodule\n\n"
  },
  {
    "path": "bsv/AxiGather.bsv",
    "content": "// Copyright (c) 2015 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\nimport GetPut::*;\nimport Vector::*;\nimport PPS7LIB::*;\nimport AxiMasterSlave::*;\nimport Axi4MasterSlave::*;\nimport AxiBits::*;\nimport GetPutM::*;\nimport FIFOF::*;\n\ninstance ToPutM#(AxiMasterBits#(addrWidth,dataWidth,tagWidth,Empty), Axi3ReadResponse#(dataWidth, tagWidth));\n   module toPutM#(AxiMasterBits#(addrWidth, dataWidth, tagWidth, Empty) m)(Put#(Axi3ReadResponse#(dataWidth, tagWidth)));\n      FIFOF#(Axi3ReadResponse#(dataWidth, tagWidth)) dfifo <- mkFIFOF();\n\n      rule handshake;\n          m.rvalid(pack(dfifo.notEmpty()));\n      endrule\n\n      rule deq if (unpack(m.rready()));\n          let d = dfifo.first;\n          m.rid(d.id);\n          m.rresp(d.resp);\n          m.rdata(d.data);\n          m.rlast(d.last);\n          dfifo.deq;\n      endrule\n\n      return toPut(dfifo);\n   endmodule\nendinstance\n\ninstance ToPutM#(AxiMasterBits#(addrWidth,dataWidth,tagWidth,Empty), Axi3WriteResponse#(tagWidth));\n   module toPutM#(AxiMasterBits#(addrWidth, dataWidth, tagWidth, Empty) m)(Put#(Axi3WriteResponse#(tagWidth)));\n      FIFOF#(Axi3WriteResponse#(tagWidth)) dfifo <- mkFIFOF();\n\n      rule handshake;\n          m.bvalid(pack(dfifo.notEmpty()));\n      endrule\n\n      rule deq if (unpack(m.rready()));\n          let d = dfifo.first;\n          m.bid(d.id);\n          m.bresp(d.resp);\n          dfifo.deq;\n      endrule\n\n      return toPut(dfifo);\n   endmodule\nendinstance\n\ninterface AxiMasterCommon#(numeric type addrWidth, numeric type dataWidth, numeric type tagWidth);\n    method Bit#(1)            aresetn();\n    interface Axi3Master#(addrWidth,dataWidth,tagWidth) client;\nendinterface\n\ninterface AxiSlaveCommon#(numeric type addrWidth, numeric type dataWidth, numeric type tagWidth, type extraType);\n    method Bit#(1)            aresetn();\n    interface Axi3Slave#(addrWidth,dataWidth,tagWidth) server;\n    interface extraType   extra;\nendinterface\n\ninterface Axi4SlaveCommon#(numeric type addrWidth, numeric type dataWidth, numeric type tagWidth, type extraType);\n    method Bit#(1)            aresetn();\n    interface Axi4Slave#(addrWidth,dataWidth,tagWidth) server;\n    interface extraType   extra;\nendinterface\n\nmodule mkAxi3MasterGather#(AxiMasterBits#(addrWidth, dataWidth, tagWidth, Empty) axiWires)(AxiMasterCommon#(addrWidth, dataWidth, tagWidth));\n   Wire#(Bit#(1)) arready <- mkDWire(0);\n   Wire#(Bit#(1)) awready <- mkDWire(0);\n   Wire#(Bit#(1)) rvalid <- mkDWire(0);\n   Wire#(Bit#(1)) wready <- mkDWire(0);\n   Wire#(Bit#(tagWidth)) rid <- mkDWire(0);\n   Wire#(Bit#(2)) rresp <- mkDWire(0);\n   Wire#(Bit#(dataWidth)) rdata <- mkDWire(0);\n   Wire#(Bit#(1)) rlast <- mkDWire(0);\n   Wire#(Bit#(1)) bvalid <- mkDWire(0);\n   Wire#(Bit#(tagWidth)) bid <- mkDWire(0);\n   Wire#(Bit#(2)) bresp <- mkDWire(0);\n\n   rule handshake1;\n        axiWires.arready(arready);\n   endrule\n   rule handshake2;\n        axiWires.awready(awready);\n   endrule\n   rule handshake4;\n        axiWires.wready(wready);\n   endrule\n\n   // rule handshake 3 & 5 done in toPutM modules\n   Put#(Axi3ReadResponse#(dataWidth, tagWidth)) resp_read_put <- toPutM(axiWires);\n   Put#(Axi3WriteResponse#(tagWidth)) resp_b_put <- toPutM(axiWires);\n\n   interface Axi3Master client;\n        interface Get req_ar;\n             method ActionValue#(Axi3ReadRequest#(addrWidth,tagWidth)) get() if (axiWires.arvalid() != 0);\n                 Axi3ReadRequest#(addrWidth,tagWidth) v;\n                 v.address = axiWires.araddr();\n                 v.burst = axiWires.arburst();\n                 v.cache = axiWires.arcache();\n                 v.id = axiWires.arid();\n                 v.len = axiWires.arlen();\n                 v.lock = axiWires.arlock();\n                 v.prot = axiWires.arprot();\n                 v.qos = axiWires.arqos();\n                 v.size = {0, axiWires.arsize()};\n\n                arready <= 1;\n                return v;\n            endmethod\n        endinterface\n        interface Get req_aw;\n            method ActionValue#(Axi3WriteRequest#(addrWidth,tagWidth)) get() if (axiWires.awvalid() != 0);\n                Axi3WriteRequest#(addrWidth,tagWidth) v;\n                v.address = axiWires.awaddr();\n                v.burst = axiWires.awburst();\n                v.cache = axiWires.awcache();\n                v.id = axiWires.awid();\n                v.len = axiWires.awlen();\n                v.lock = axiWires.awlock();\n                v.prot = axiWires.awprot();\n                v.qos = axiWires.awqos();\n                v.size = {0, axiWires.awsize()};\n\n                awready <= 1;\n                return v;\n           endmethod\n        endinterface\n        interface Put resp_read = resp_read_put;\n        interface Get resp_write;\n            method ActionValue#(Axi3WriteData#(dataWidth,tagWidth)) get() if (axiWires.wvalid() != 0);\n                Axi3WriteData#(dataWidth,tagWidth) v;\n                v.id = axiWires.wid();\n                v.byteEnable = axiWires.wstrb();\n                v.data = axiWires.wdata();\n                v.last = axiWires.wlast();\n\n                wready <= 1;\n                return v;\n            endmethod\n        endinterface\n        interface Put resp_b = resp_b_put;\n    endinterface\n    method aresetn = axiWires.aresetn;\nendmodule\n\nmodule mkAxi3SlaveGather#(AxiSlaveBits#(addrWidth, dataWidth, tagWidth,\n    extraType) axiWires)(AxiSlaveCommon#(addrWidth, dataWidth,tagWidth,extraType));\n    Wire#(Bit#(addrWidth)) araddr <- mkDWire(0);\n    Wire#(Bit#(2)) arburst <- mkDWire(0);\n    Wire#(Bit#(4)) arcache <- mkDWire(0);\n    Wire#(Bit#(tagWidth)) arid <- mkDWire(0);\n    Wire#(Bit#(4)) arlen <- mkDWire(0);\n    Wire#(Bit#(2)) arlock <- mkDWire(0);\n    Wire#(Bit#(3)) arprot <- mkDWire(0);\n    Wire#(Bit#(4)) arqos <- mkDWire(0);\n    Wire#(Bit#(2)) arsize <- mkDWire(0);\n    Wire#(Bit#(1)) arvalid <- mkDWire(0);\n\n    Wire#(Bit#(addrWidth)) awaddr <- mkDWire(0);\n    Wire#(Bit#(2)) awburst <- mkDWire(0);\n    Wire#(Bit#(4)) awcache <- mkDWire(0);\n    Wire#(Bit#(tagWidth)) awid <- mkDWire(0);\n    Wire#(Bit#(4)) awlen <- mkDWire(0);\n    Wire#(Bit#(2)) awlock <- mkDWire(0);\n    Wire#(Bit#(3)) awprot <- mkDWire(0);\n    Wire#(Bit#(4)) awqos <- mkDWire(0);\n    Wire#(Bit#(2)) awsize <- mkDWire(0);\n    Wire#(Bit#(1)) awvalid <- mkDWire(0);\n\n    Wire#(Bit#(1)) rready <- mkDWire(0);\n    Wire#(Bit#(tagWidth)) wid <- mkDWire(0);\n    Wire#(Bit#(TDiv#(dataWidth,8))) wstrb <- mkDWire(0);\n    Wire#(Bit#(dataWidth)) wdata <- mkDWire(0);\n    Wire#(Bit#(1)) wlast <- mkDWire(0);\n    Wire#(Bit#(1)) wvalid <- mkDWire(0);\n    Wire#(Bit#(1)) bready <- mkDWire(0);\n\n    rule handshake1;\n          axiWires.araddr(araddr);\n          axiWires.arburst(arburst);\n          axiWires.arcache(arcache);\n          axiWires.arid(arid);\n          axiWires.arlen(arlen);\n          axiWires.arlock(arlock);\n          axiWires.arprot(arprot);\n          axiWires.arqos(arqos);\n          axiWires.arsize(arsize);\n          axiWires.arvalid(arvalid);\n    endrule\n    rule handshake2;\n          axiWires.awaddr(awaddr);\n          axiWires.awburst(awburst);\n          axiWires.awcache(awcache);\n          axiWires.awid(awid);\n          axiWires.awlen(awlen);\n          axiWires.awlock(awlock);\n          axiWires.awprot(awprot);\n          axiWires.awqos(awqos);\n          axiWires.awsize(awsize);\n          axiWires.awvalid(awvalid);\n    endrule\n    rule handshake3;\n         axiWires.rready(rready);\n    endrule\n    rule handshake4;\n          axiWires.wid(wid);\n          axiWires.wstrb(wstrb);\n          axiWires.wdata(wdata);\n          axiWires.wlast(wlast);\n          axiWires.wvalid(wvalid);\n    endrule\n    rule handshake5;\n         axiWires.bready(bready);\n    endrule\n    interface Axi3Slave server;\n    interface Put req_ar;\n        method Action put(Axi3ReadRequest#(addrWidth,tagWidth) v) if (axiWires.arready() != 0);\n           araddr <= v.address;\n           arburst <= v.burst;\n           arcache <= v.cache;\n           arid <= v.id;\n           arlen <= v.len;\n           arlock <= v.lock;\n           arprot <= v.prot;\n           arqos <= v.qos;\n           arsize <= v.size[1:0];\n\n           arvalid <= 1;\n        endmethod\n    endinterface\n    interface Put req_aw;\n        method Action put(Axi3WriteRequest#(addrWidth,tagWidth) v) if (axiWires.awready() != 0);\n           awaddr <= v.address;\n           awburst <= v.burst;\n           awcache <= v.cache;\n           awid <= v.id;\n           awlen <= v.len;\n           awlock <= v.lock;\n           awprot <= v.prot;\n           awqos <= v.qos;\n           awsize <= v.size[1:0];\n\n           awvalid <= 1;\n        endmethod\n    endinterface\n    interface Put resp_write;\n        method Action put(Axi3WriteData#(dataWidth,tagWidth) v) if (axiWires.wready() != 0);\n           wid <= v.id;\n           wstrb <= v.byteEnable;\n           wdata <= v.data;\n           wlast <= v.last;\n\n           wvalid <= 1;\n        endmethod\n    endinterface\n    interface Get resp_read;\n        method ActionValue#(Axi3ReadResponse#(dataWidth, tagWidth)) get() if (axiWires.rvalid() != 0);\n            Axi3ReadResponse#(dataWidth, tagWidth) v;\n            v.id = axiWires.rid();\n            v.resp = axiWires.rresp();\n            v.data = axiWires.rdata();\n            v.last = axiWires.rlast();\n\n            rready <= 1;\n            return v;\n        endmethod\n         endinterface\n    interface Get resp_b;\n        method ActionValue#(Axi3WriteResponse#(tagWidth)) get() if (axiWires.bvalid() != 0);\n            Axi3WriteResponse#(tagWidth) v;\n            v.id = axiWires.bid();\n            v.resp = axiWires.bresp();\n\n            bready <= 1;\n            return v;\n        endmethod\n     endinterface\n     endinterface\n     interface extra = axiWires.extra;\n     method aresetn = axiWires.aresetn;\nendmodule\n\nmodule mkAxi4SlaveGather#(Axi4SlaveBits#(addrWidth, dataWidth, tagWidth, extraType) axiWires)\n   (Axi4SlaveCommon#(addrWidth, dataWidth,tagWidth,extraType));\n    Wire#(Bit#(addrWidth)) araddr <- mkDWire(0);\n    Wire#(Bit#(2)) arburst <- mkDWire(0);\n    Wire#(Bit#(4)) arcache <- mkDWire(0);\n    Wire#(Bit#(tagWidth)) arid <- mkDWire(0);\n    Wire#(Bit#(8)) arlen <- mkDWire(0);\n    Wire#(Bit#(2)) arlock <- mkDWire(0);\n    Wire#(Bit#(3)) arprot <- mkDWire(0);\n    Wire#(Bit#(4)) arqos <- mkDWire(0);\n    Wire#(Bit#(3)) arsize <- mkDWire(0);\n    Wire#(Bit#(1)) arvalid <- mkDWire(0);\n\n    Wire#(Bit#(addrWidth)) awaddr <- mkDWire(0);\n    Wire#(Bit#(2)) awburst <- mkDWire(0);\n    Wire#(Bit#(4)) awcache <- mkDWire(0);\n    Wire#(Bit#(tagWidth)) awid <- mkDWire(0);\n    Wire#(Bit#(8)) awlen <- mkDWire(0);\n    Wire#(Bit#(2)) awlock <- mkDWire(0);\n    Wire#(Bit#(3)) awprot <- mkDWire(0);\n    Wire#(Bit#(4)) awqos <- mkDWire(0);\n    Wire#(Bit#(3)) awsize <- mkDWire(0);\n    Wire#(Bit#(1)) awvalid <- mkDWire(0);\n\n    Wire#(Bit#(1)) rready <- mkDWire(0);\n    Wire#(Bit#(tagWidth)) wid <- mkDWire(0);\n    Wire#(Bit#(TDiv#(dataWidth,8))) wstrb <- mkDWire(0);\n    Wire#(Bit#(dataWidth)) wdata <- mkDWire(0);\n    Wire#(Bit#(1)) wlast <- mkDWire(0);\n    Wire#(Bit#(1)) wvalid <- mkDWire(0);\n    Wire#(Bit#(1)) bready <- mkDWire(0);\n\n    rule handshake1;\n          axiWires.araddr(araddr);\n          axiWires.arburst(arburst);\n          axiWires.arcache(arcache);\n          axiWires.arid(arid);\n          axiWires.arlen(arlen);\n          axiWires.arlock(arlock);\n          axiWires.arprot(arprot);\n          axiWires.arqos(arqos);\n          axiWires.arsize(arsize);\n          axiWires.arvalid(arvalid);\n    endrule\n    rule handshake2;\n          axiWires.awaddr(awaddr);\n          axiWires.awburst(awburst);\n          axiWires.awcache(awcache);\n          axiWires.awid(awid);\n          axiWires.awlen(awlen);\n          axiWires.awlock(awlock);\n          axiWires.awprot(awprot);\n          axiWires.awqos(awqos);\n          axiWires.awsize(awsize);\n          axiWires.awvalid(awvalid);\n    endrule\n    rule handshake3;\n         axiWires.rready(rready);\n    endrule\n    rule handshake4;\n          axiWires.wid(wid);\n          axiWires.wstrb(wstrb);\n          axiWires.wdata(wdata);\n          axiWires.wlast(wlast);\n          axiWires.wvalid(wvalid);\n    endrule\n    rule handshake5;\n         axiWires.bready(bready);\n    endrule\n    interface Axi4Slave server;\n    interface Put req_ar;\n        method Action put(Axi4ReadRequest#(addrWidth,tagWidth) v) if (axiWires.arready() != 0);\n           araddr <= v.address;\n           arburst <= v.burst;\n           arcache <= v.cache;\n           arid <= v.id;\n           arlen <= v.len;\n           arlock <= v.lock;\n           arprot <= v.prot;\n           arqos <= v.qos;\n           arsize <= v.size;\n\n           arvalid <= 1;\n        endmethod\n    endinterface\n    interface Put req_aw;\n        method Action put(Axi4WriteRequest#(addrWidth,tagWidth) v) if (axiWires.awready() != 0);\n           awaddr <= v.address;\n           awburst <= v.burst;\n           awcache <= v.cache;\n           awid <= v.id;\n           awlen <= v.len;\n           awlock <= v.lock;\n           awprot <= v.prot;\n           awqos <= v.qos;\n           awsize <= v.size;\n\n           awvalid <= 1;\n        endmethod\n    endinterface\n    interface Put resp_write;\n        method Action put(Axi4WriteData#(dataWidth,tagWidth) v) if (axiWires.wready() != 0);\n           wid <= v.id;\n           wstrb <= v.byteEnable;\n           wdata <= v.data;\n           wlast <= v.last;\n\n           wvalid <= 1;\n        endmethod\n    endinterface\n    interface Get resp_read;\n        method ActionValue#(Axi4ReadResponse#(dataWidth, tagWidth)) get() if (axiWires.rvalid() != 0);\n            Axi4ReadResponse#(dataWidth, tagWidth) v;\n            v.id = axiWires.rid();\n            v.resp = axiWires.rresp();\n            v.data = axiWires.rdata();\n            v.last = axiWires.rlast();\n\n            rready <= 1;\n            return v;\n        endmethod\n         endinterface\n    interface Get resp_b;\n        method ActionValue#(Axi4WriteResponse#(tagWidth)) get() if (axiWires.bvalid() != 0);\n            Axi4WriteResponse#(tagWidth) v;\n            v.id = axiWires.bid();\n            v.resp = axiWires.bresp();\n\n            bready <= 1;\n            return v;\n        endmethod\n     endinterface\n     endinterface\n     interface extra = axiWires.extra;\n     method aresetn = axiWires.aresetn;\nendmodule\n"
  },
  {
    "path": "bsv/AxiMasterSlave.bsv",
    "content": "// Copyright (c) 2013 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\nimport FIFOF::*;\nimport FIFO::*;\nimport GetPut::*;\nimport GetPutWithClocks::*;\nimport Connectable::*;\nimport RegFile::*;\n\n\ntypeclass RegToWriteOnly#(type a);\n   function WriteOnly#(a) regToWriteOnly(Reg#(a) x);\nendtypeclass\n\ninstance RegToWriteOnly#(a);\n   function WriteOnly#(a) regToWriteOnly(Reg#(a) x);\n      return (interface WriteOnly;\n\t\t method Action _write(a v);\n\t\t    x._write(v);\n\t\t endmethod\n\t      endinterface);\n   endfunction\nendinstance\n\ntypedef struct {\n   Bit#(addrWidth) address;\n   Bit#(4) len;\n   Bit#(3) size; // assume matches bus width of Axi3Master\n   Bit#(2) burst;  // drive with 2'b01\n   Bit#(3) prot; // drive with 3'b000\n   Bit#(4) cache; // drive with 4'b0011\n   Bit#(idWidth) id;\n   Bit#(2) lock;\n   Bit#(4) qos;\n} Axi3ReadRequest#(numeric type addrWidth, numeric type idWidth) deriving (Bits);\n\nfunction Bit#(3) axiBusSize(Integer busWidth);\n   if (busWidth == 16)\n      return 3'b001;\n   else if (busWidth == 32)\n      return 3'b010;\n   else if (busWidth == 64)\n      return 3'b011;\n   else if (busWidth == 128)\n      return 3'b100;\n   else if (busWidth == 256)\n      return 3'b101;\n   else if (busWidth == 512)\n      return 3'b110;\n   else if (busWidth == 1024)\n      return 3'b111;\n   else\n      return 3'b000;\nendfunction\n\ntypedef struct {\n   Bit#(busWidth) data;\n   Bit#(2) resp;\n   Bit#(1) last;\n   Bit#(idWidth) id;\n} Axi3ReadResponse#(numeric type busWidth, numeric type idWidth) deriving (Bits);\n\ntypedef struct {\n   Bit#(addrWidth) address;\n   Bit#(4) len;\n   Bit#(3) size; // assume matches bus width of Axi3Master\n   Bit#(2) burst;  // drive with 2'b01\n   Bit#(3) prot; // drive with 3'b000\n   Bit#(4) cache; // drive with 4'b0011\n   Bit#(idWidth) id;\n   Bit#(2) lock;\n   Bit#(4) qos;\n} Axi3WriteRequest#(numeric type addrWidth, numeric type idWidth) deriving (Bits);\n\ntypedef struct {\n    Bit#(busWidth) data;\n    Bit#(TDiv#(busWidth,8)) byteEnable;\n    Bit#(1)        last;\n    Bit#(idWidth) id;\n} Axi3WriteData#(numeric type busWidth, numeric type idWidth) deriving (Bits);\n\ntypedef struct {\n    Bit#(2) resp;\n    Bit#(idWidth) id;\n} Axi3WriteResponse#(numeric type idWidth) deriving (Bits);\n\nfunction Get#(Axi3ReadResponse#(_b,_c)) get_resp_read(Axi3Slave#(_a,_b,_c) x);\n   return x.resp_read;\nendfunction\n\nfunction Get#(Axi3WriteResponse#(_c)) get_resp_b(Axi3Slave#(_a,_b,_c) x);\n   return x.resp_b;\nendfunction\n\ninterface Axi3Master#(numeric type addrWidth, numeric type busWidth, numeric type idWidth);\n   interface Get#(Axi3ReadRequest#(addrWidth, idWidth)) req_ar;\n   interface Put#(Axi3ReadResponse#(busWidth, idWidth)) resp_read;\n   interface Get#(Axi3WriteRequest#(addrWidth, idWidth)) req_aw;\n   interface Get#(Axi3WriteData#(busWidth, idWidth)) resp_write;\n   interface Put#(Axi3WriteResponse#(idWidth)) resp_b;\nendinterface\n\ninterface Axi3Slave#(numeric type addrWidth, numeric type busWidth, numeric type idWidth);\n   interface Put#(Axi3ReadRequest#(addrWidth, idWidth)) req_ar;\n   interface Get#(Axi3ReadResponse#(busWidth, idWidth)) resp_read;\n   interface Put#(Axi3WriteRequest#(addrWidth, idWidth)) req_aw;\n   interface Put#(Axi3WriteData#(busWidth, idWidth)) resp_write;\n   interface Get#(Axi3WriteResponse#(idWidth)) resp_b;\nendinterface\n\nfunction Put#(t) null_put();\n   return (interface Put;\n\t      method Action put(t x) if (False);\n\t\t noAction;\n\t      endmethod\n\t   endinterface);\nendfunction\n\nfunction Get#(t) null_get();\n   return (interface Get;\n\t      method ActionValue#(t) get() if (False);\n\t\t return ?;\n\t      endmethod\n\t   endinterface);\nendfunction\n      \nfunction  Axi3Master#(addrWidth, busWidth, idWidth) null_axi_master();\n   return (interface Axi3Master;\n\t      interface Get req_ar = null_get;\n\t      interface Put resp_read = null_put;\n\t      interface Get req_aw = null_get;\n\t      interface Get resp_write = null_get;\n\t      interface Put resp_b = null_put;\n\t   endinterface);\nendfunction\n\ninstance Connectable#(Axi3Master#(addrWidth, busWidth,idWidth), Axi3Slave#(addrWidth, busWidth,idWidth));\n   module mkConnection#(Axi3Master#(addrWidth, busWidth,idWidth) m, Axi3Slave#(addrWidth, busWidth,idWidth) s)(Empty);\n\n      mkConnection(m.req_ar, s.req_ar);\n      mkConnection(s.resp_read, m.resp_read);\n\n      mkConnection(m.req_aw, s.req_aw);\n      mkConnection(m.resp_write, s.resp_write);\n      mkConnection(s.resp_b, m.resp_b);\n\n   endmodule\nendinstance\n\n\ninstance ConnectableWithClocks#(Axi3Master#(addrWidth, busWidth,idWidth), Axi3Slave#(addrWidth, busWidth,idWidth))\n   provisos (ConnectableWithClocks#(Get#(Axi3ReadRequest#(addrWidth, idWidth)), Put#(Axi3ReadRequest#(addrWidth, idWidth)))\n\t     ,ConnectableWithClocks#(Get#(Axi3ReadResponse#(busWidth, idWidth)), Put#(Axi3ReadResponse#(busWidth, idWidth)))\n\t     ,ConnectableWithClocks#(Get#(Axi3WriteRequest#(addrWidth, idWidth)), Put#(Axi3WriteRequest#(addrWidth, idWidth)))\n\t     ,ConnectableWithClocks#(Get#(Axi3WriteData#(busWidth, idWidth)), Put#(Axi3WriteData#(busWidth, idWidth)))\n\t     ,ConnectableWithClocks#(Get#(Axi3WriteResponse#(idWidth)), Put#(Axi3WriteResponse#(idWidth)))\n\t     );\n\n   module mkConnectionWithClocks2#(Axi3Master#(addrWidth, busWidth,idWidth) m, Axi3Slave#(addrWidth, busWidth,idWidth) s)(Empty);\n      mkConnectionWithClocks(clockOf(m), resetOf(m), clockOf(s), resetOf(s), m, s);\n   endmodule\n\n   module mkConnectionWithClocks#(Clock mClock, Reset mReset, Clock sClock, Reset sReset,\n\t\t\t\t  Axi3Master#(addrWidth, busWidth,idWidth) m, Axi3Slave#(addrWidth, busWidth,idWidth) s)(Empty);\n\n      mkConnectionWithClocks(mClock, mReset, sClock, sReset, m.req_ar, s.req_ar);\n      mkConnectionWithClocks(sClock, sReset, mClock, mReset, s.resp_read, m.resp_read);\n\n      mkConnectionWithClocks(mClock, mReset, sClock, sReset, m.req_aw, s.req_aw);\n      mkConnectionWithClocks(mClock, mReset, sClock, sReset, m.resp_write, s.resp_write);\n      mkConnectionWithClocks(sClock, sReset, mClock, mReset, s.resp_b, m.resp_b);\n\n   endmodule\nendinstance\n"
  },
  {
    "path": "bsv/AxiStream.bsv",
    "content": "// Copyright (c) 2016 Connectal Project\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\nimport Connectable::*;\nimport FIFOF::*;\nimport GetPut::*;\nimport GetPutM::*;\nimport Probe::*;\n`include \"ConnectalProjectConfig.bsv\"\n\n(* always_ready, always_enabled *)\ninterface AxiStreamMaster#(numeric type dsz);\n    method Bit#(dsz)              tdata();\n    method Bit#(TDiv#(dsz,8))     tkeep();\n    method Bit#(1)                tlast();\n    (* prefix = \"\" *)method Action                 tready((* port=\"tready\" *) Bit#(1) v);\n    method Bit#(1)                tvalid();\nendinterface\n\n(* always_ready, always_enabled *)\ninterface AxiStreamSlave#(numeric type dsz);\n    (* prefix = \"\" *)\n    method Action      tdata((* port = \"tdata\" *) Bit#(dsz) v);\n    (* prefix = \"\" *)\n    method Action      tkeep((* port = \"tkeep\" *) Bit#(TDiv#(dsz,8)) v);\n    (* prefix = \"\" *)\n    method Action      tlast((* port = \"tlast\" *) Bit#(1) v);\n    method Bit#(1)     tready();\n    (* prefix = \"\" *)\n    method Action      tvalid((* port = \"tvalid\" *)Bit#(1) v);\nendinterface\n\ninstance Connectable#(AxiStreamMaster#(dataWidth), AxiStreamSlave#(dataWidth));\n   module mkConnection#(AxiStreamMaster#(dataWidth) from, AxiStreamSlave#(dataWidth) to)(Empty);\n`ifdef GET_PUT_WITH_CLOCKS_USE_XILINX_FIFO\n      let cnxProbe <- mkProbe;\n      rule rl_probe if (from.tvalid() == 1 && to.tready() == 1);\n\t cnxProbe <= from.tdata();\n      endrule\n`endif\n      rule rl_axi_stream;\n\t to.tdata(from.tdata());\n\t to.tkeep(from.tkeep());\n\t to.tlast(from.tlast());\n\t to.tvalid(from.tvalid());\n\t from.tready(to.tready());\n      endrule\n   endmodule\nendinstance\n\ninstance Connectable#(AxiStreamMaster#(dataWidth), Put#(dtype))\n   provisos (Bits#(dtype, dataWidth));\n   module mkConnection#(AxiStreamMaster#(dataWidth) from, Put#(dtype) to)(Empty);\n      FIFOF#(Bit#(dataWidth)) asputfifo <- mkFIFOF();\n`ifdef GET_PUT_WITH_CLOCKS_USE_XILINX_FIFO\n      let getProbe <- mkProbe;\n      let putProbe <- mkProbe;\n`endif\n      rule rl_ready;\n\t from.tready(pack(asputfifo.notFull));\n      endrule\n      rule rl_enq if (from.tvalid == 1);\n`ifdef GET_PUT_WITH_CLOCKS_USE_XILINX_FIFO\n\t getProbe <= from.tdata;\n`endif\n\t asputfifo.enq(from.tdata);\n      endrule\n      rule rl_put;\n\t let v <- toGet(asputfifo).get();\n`ifdef GET_PUT_WITH_CLOCKS_USE_XILINX_FIFO\n\t putProbe <= v;\n`endif\n\t to.put(unpack(v));\n      endrule\n   endmodule\nendinstance\n\ninstance Connectable#(Get#(dtype), AxiStreamSlave#(dataWidth))\n   provisos (Bits#(dtype, dataWidth));\n   module mkConnection#(Get#(dtype) from, AxiStreamSlave#(dataWidth) to)(Empty);\n      FIFOF#(Bit#(dataWidth)) asgetfifo <- mkFIFOF();\n`ifdef GET_PUT_WITH_CLOCKS_USE_XILINX_FIFO\n      let getProbe <- mkProbe();\n      let putProbe <- mkProbe();\n`endif\n      rule rl_get;\n\t let v <- from.get();\n`ifdef GET_PUT_WITH_CLOCKS_USE_XILINX_FIFO\n\t getProbe <= v;\n`endif\n\t asgetfifo.enq(pack(v));\n      endrule\n      rule rl_axi_stream;\n\t to.tdata(asgetfifo.first);\n\t to.tkeep(maxBound);\n\t to.tlast(0);\n      endrule\n      rule rl_tvalid;\n\t to.tvalid(pack(asgetfifo.notEmpty));\n      endrule\n      rule rl_deq if (to.tready == 1);\n`ifdef GET_PUT_WITH_CLOCKS_USE_XILINX_FIFO\n\t putProbe <= asgetfifo.first();\n`endif\n\t asgetfifo.deq();\n      endrule\n   endmodule\nendinstance\n\n////////////////////////////////////////////////////////////\n\ninstance ToGetM#(AxiStreamMaster#(asz), Bit#(asz));\n   module toGetM#(AxiStreamMaster#(asz) m)(Get#(Bit#(asz)));\n      FIFOF#(Bit#(asz)) tmpfifo <- mkFIFOF();\n\n      rule handshake;\n         m.tready(pack(tmpfifo.notFull));\n      endrule\n      rule enq if (unpack(m.tvalid));\n\t tmpfifo.enq(m.tdata());\n      endrule\n\n      return toGet(tmpfifo);\n   endmodule\nendinstance\n\ninstance ToPutM#(AxiStreamSlave#(asz), Bit#(asz));\n   module toPutM#(AxiStreamSlave#(asz) m)(Put#(Bit#(asz)));\n      FIFOF#(Bit#(asz)) tmpfifo <- mkFIFOF();\n\n      rule handshake;\n\t m.tvalid(pack(tmpfifo.notEmpty()));\n      endrule\n      rule deq if (unpack(m.tready()));\n\t m.tdata(tmpfifo.first());\n\t m.tkeep(maxBound);\n\t m.tlast(1);\n\t tmpfifo.deq();\n      endrule\n\n      return toPut(tmpfifo);\n   endmodule\nendinstance\n\n////////////////////////////////////////////////////////////\ntypeclass ToAxiStream#(type atype, type btype);\n   function atype toAxiStream(btype b);\nendtypeclass\ntypeclass MkAxiStream#(type atype, type btype);\n   module mkAxiStream#(btype b)(atype);\nendtypeclass\n\ninstance MkAxiStream#(AxiStreamMaster#(dsize), FIFOF#(Bit#(dsize)));\n   module mkAxiStream#(FIFOF#(Bit#(dsize)) f)(AxiStreamMaster#(dsize));\n      Wire#(Bool) readyWire <- mkDWire(False);\n      Wire#(Bit#(dsize)) dataWire <- mkDWire(0);\n      rule rl_data if (f.notEmpty());\n\t dataWire <= f.first();\n      endrule\n      rule rl_deq if (readyWire && f.notEmpty);\n\t f.deq();\n      endrule\n     method Bit#(dsize)              tdata();\n\treturn dataWire;\n     endmethod\n     method Bit#(TDiv#(dsize,8))     tkeep(); return maxBound; endmethod\n     method Bit#(1)                tlast(); return pack(False); endmethod\n     method Action                 tready(Bit#(1) v);\n\treadyWire <= unpack(v);\n     endmethod\n     method Bit#(1)                tvalid(); return pack(f.notEmpty()); endmethod\n   endmodule\nendinstance\n\ninstance MkAxiStream#(AxiStreamSlave#(dsize), FIFOF#(Bit#(dsize)));\n   module mkAxiStream#(FIFOF#(Bit#(dsize)) f)(AxiStreamSlave#(dsize));\n      Wire#(Bit#(dsize)) dataWire <- mkDWire(unpack(0));\n      Wire#(Bool) validWire <- mkDWire(False);\n      rule enq if (validWire && f.notFull());\n\t f.enq(dataWire);\n      endrule\n      method Action      tdata(Bit#(dsize) v);\n\t dataWire <= v;\n      endmethod\n      method Action      tkeep(Bit#(TDiv#(dsize,8)) v); endmethod\n      method Action      tlast(Bit#(1) v); endmethod\n      method Bit#(1)     tready(); return pack(f.notFull()); endmethod\n      method Action      tvalid(Bit#(1) v);\n\t validWire <= unpack(v);\n      endmethod\n   endmodule\nendinstance\n"
  },
  {
    "path": "bsv/BpiFlash.bsv",
    "content": "\n`include \"ConnectalProjectConfig.bsv\"\nimport Vector::*;\nimport Clocks::*;\nimport Connectable::*;\nimport GetPut::*;\nimport FIFOF::*;\nimport BRAM::*;\nimport Probe::*;\nimport StmtFSM::*;\nimport TriState::*;\nimport Vector::*;\nimport ConnectalXilinxCells::*;\n\n`ifdef SIMULATION\nimport I28F512P33::*;\n`endif\n\n// interface to BPI Flash (PC28F00AG18FE)\n\n(* always_ready, always_enabled *)\ninterface BpiFlashPins;\n   interface Clock deleteme_unused_clock;\n//   interface Reset rst;\n   interface Vector#(16,Inout#(Bit#(1))) data;\n   method Bit#(26) addr();\n   method Bit#(1) adv_b();\n   method Bit#(1) ce_b();\n   method Bit#(1) oe_b();\n   method Bit#(1) we_b();\n`ifdef BPI_HAS_WP\n   method Bit#(1) wp_b();\n`endif\n`ifdef BPI_HAS_VPP\n   method Bit#(1) vpp();\n`endif\n   method Action wait_in(Bit#(1) b);\nendinterface\n\ninterface BpiPins;\n   interface BpiFlashPins flash;\nendinterface\n\ninterface BpiFlash;\n   interface BpiFlashPins flash;\n   method Action setParameters(Bit#(16) cycles, Bool stallOnWaitIn);\n   interface Server#(BRAMRequest#(Bit#(26),Bit#(16)),Bit#(16)) server;\nendinterface\n\nmodule mkBpiFlash(BpiFlash);\n   let clock <- exposeCurrentClock();\n   let reset <- exposeCurrentReset();\n\n   Reg#(Bit#(1)) rst_o <- mkReg(0);\n   Reg#(Bit#(1)) ce <- mkReg(1);\n   Reg#(Bit#(1)) we <- mkReg(1);\n   Reg#(Bit#(1)) oe <- mkReg(1);\n   Reg#(Bit#(1)) adv <- mkReg(1);\n   Reg#(Bit#(16)) data_o <- mkReg(0);\n   Reg#(Bit#(26)) addr_o <- mkReg(0);\n   Reg#(Bit#(16)) delayReg <- mkReg(10);\n   Reg#(Bool)     stallOnWaitReg  <- mkReg(False);\n   Reg#(BRAMRequest#(Bit#(26),Bit#(16))) reqReg <- mkReg(unpack(0));\n   FIFOF#(BRAMRequest#(Bit#(26),Bit#(16))) reqFifo <- mkFIFOF();\n   FIFOF#(Bit#(16)) dataFifo <- mkFIFOF();\n\n`ifndef SIMULATION\n   Wire#(Bit#(1)) wait_in_b <- mkDWire(0);\n   module mkDataIobuf#(Integer i)(IOBUF);\n      (* hide *)\n      let iobuf <- mkIOBUF(we, data_o[i]);\n      return iobuf;\n   endmodule\n   function Inout#(Bit#(1)) iobuf_io(IOBUF iobuf); return iobuf.io; endfunction\n   function Bit#(1) iobuf_o(IOBUF iobuf); return iobuf.o; endfunction\n   Vector#(16, IOBUF) iobuf <- genWithM(mkDataIobuf);\n   let dataIn = pack(map(iobuf_o, iobuf));\n`endif\n\n`ifdef SIMULATION\n   let flash <- mkI28f512p33Load(\"flash.hex\");\n   let dataTristate <- mkTriState(oe == 1, data_o);\n   mkConnection(dataTristate.io, flash.dq);\n   let wait_in_b = flash.waitout();\n   let dataIn = dataTristate;\n   rule rl_flash_inputs;\n      flash.addr(addr_o);\n      flash.advneg(adv);\n      flash.ceneg(ce);\n      flash.oeneg(oe);\n      flash.weneg(we);\n      flash.wpneg(1);\n      flash.vpp(0);\n   endrule\n`endif\n\n   Reg#(Bit#(10)) i <- mkReg(0);\n\n   let readFsm <- mkAutoFSM(seq\n\t\t\twhile (True) seq\n\t\t\t   action\n\n\t\t\t      reqFifo.deq();\n\t\t\t      let req = reqFifo.first();\n\t\t\t      reqReg <= req;\n\t\t\t      addr_o <= req.address;\n\t\t\t      data_o <= req.datain;\n\t\t\t      adv <= 0;\n\t\t\t      ce <= 0;\n\t\t\t   endaction\n\t\t\t   delay(delayReg);\n\t\t\t   adv <= 1;\n\t\t\t   delay(delayReg);\n\t\t\t   action\n\t\t\t      if (reqReg.write)\n\t\t\t\t we <= 0;\n\t\t\t      else\n\t\t\t\t oe <= 0;\n\t\t\t   endaction\n\t\t\t   delay(delayReg);\n      $display(\"addr_o=%x\\n\", addr_o);\n      $display(\"wait_in_b=%d dataIn=%x\", wait_in_b, dataIn);\n\t\t\t   if (reqReg.write)\n\t\t\t      we <= 1;\n\t\t\t   if (!reqReg.write && stallOnWaitReg) await (wait_in_b == 1);\n      $display(\"wait_in_b=%d dataIn=%x\", wait_in_b, dataIn);\n\t\t\t   if (!reqReg.write || reqReg.responseOnWrite)\n\t\t\t      dataFifo.enq(dataIn);\n\t\t\t   delay(delayReg);\n\t\t\t   ce <= 1;\n\t\t\t   oe <= 1;\n\t\t\t   delay(delayReg);\n\t\t\t   endseq\n\t\t\tendseq);\n\n   method Action setParameters(Bit#(16) cycles, Bool stallOnWaitIn);\n      delayReg <= cycles;\n      stallOnWaitReg <= stallOnWaitIn;\n   endmethod\n   interface Server server;\n      interface request = toPut(reqFifo);\n      interface response = toGet(dataFifo);\n   endinterface\n`ifndef SIMULATION\n   interface BpiFlashPins flash;\n      interface deleteme_unused_clock = clock;\n//          interface rst = defaultReset;\n      interface data = map(iobuf_io, iobuf);\n      method Bit#(26) addr = addr_o;\n      method Bit#(1) adv_b = adv;\n      method Bit#(1) ce_b = ce;\n      method Bit#(1) oe_b = oe;\n      method Bit#(1) we_b = we;\n`ifdef BPI_HAS_WP\n      method Bit#(1) wp_b = 1;\n`endif\n`ifdef BPI_HAS_VPP\n      method Bit#(1) vpp = 0;\n`endif\n      method Action wait_in(Bit#(1) b);\n\t wait_in_b <= b;\n      endmethod\n   endinterface\n`endif\nendmodule\n"
  },
  {
    "path": "bsv/BramMux.bsv",
    "content": "\n// Copyright (c) 2014 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\nimport ClientServer ::*;\nimport BRAM         ::*;\nimport Vector       ::*;\nimport FIFO         ::*;\nimport SpecialFIFOs :: *;\n\ninterface BramServerMux#(numeric type aszn, type dtype);\n   interface BRAMServer#(Bit#(aszn), dtype) bramServer;\nendinterface\n\nmodule mkBramServerMux#(Vector#(numServers, BRAMServer#(Bit#(asz),dtype)) bramServers)(BramServerMux#(aszn,dtype))\n   provisos (Add#(1,a__,numServers),\n\t     Log#(numServers,csz),\n\t     Add#(asz,csz,aszn),\n\t     Bits#(dtype,dsz),\n\t     Bits#(Tuple2#(Bit#(csz), BRAM::BRAMRequest#(Bit#(asz), dtype)), c__)\n\t     );\n   let numServers = valueOf(numServers);\n   FIFO#(dtype) responseFifo <- mkPipelineFIFO();\n   for (Integer i = 0; i < numServers; i = i + 1) begin\n      (* descending_urgency = \"respond\" *)\n      rule respond;\n         let response <- bramServers[i].response.get();\n         responseFifo.enq(response);\n      endrule\n   end\n   interface BRAMServer bramServer;\n      interface Put request;\n\t method Action put(BRAMRequest#(Bit#(aszn), dtype) request);\n\t    Bit#(csz) clientNumber = request.address[valueOf(aszn)-1:valueOf(asz)];\n            bramServers[clientNumber].request.put( BRAMRequest {\n\t\t\t\t\t    write: request.write,\n\t\t\t\t\t    responseOnWrite: request.responseOnWrite,\n\t\t\t\t\t    address: truncate(request.address),\n\t\t\t\t\t    datain: request.datain });\n\t endmethod\n      endinterface\n      interface Get response;\n\t method ActionValue#(dtype) get();\n\t    responseFifo.deq();\n\t    return responseFifo.first();\n\t endmethod\n      endinterface\n   endinterface\nendmodule\n\nmodule mkGatedBramServerMux#(Reg#(Bool) gate, Vector#(numServers, BRAMServer#(Bit#(asz),dtype)) bramServers)(BramServerMux#(aszn,dtype))\n   provisos (Add#(1,a__,numServers),\n\t     Log#(numServers,csz),\n\t     Add#(asz,csz,aszn),\n\t     Bits#(dtype,dsz),\n\t     Bits#(Tuple2#(Bit#(csz), BRAM::BRAMRequest#(Bit#(asz), dtype)), c__)\n\t     );\n   let numServers = valueOf(numServers);\n   FIFO#(dtype) responseFifo <- mkPipelineFIFO();\n   for (Integer i = 0; i < numServers; i = i + 1) begin\n      (* descending_urgency = \"respond\" *)\n      rule respond if (gate);\n         let response <- bramServers[i].response.get();\n         responseFifo.enq(response);\n      endrule\n   end\n   interface BRAMServer bramServer;\n      interface Put request;\n\t method Action put(BRAMRequest#(Bit#(aszn), dtype) request) if (gate);\n\t    Bit#(csz) clientNumber = request.address[valueOf(aszn)-1:valueOf(asz)];\n            bramServers[clientNumber].request.put( BRAMRequest {\n\t\t\t\t\t    write: request.write,\n\t\t\t\t\t    responseOnWrite: request.responseOnWrite,\n\t\t\t\t\t    address: truncate(request.address),\n\t\t\t\t\t    datain: request.datain });\n\t endmethod\n      endinterface\n      interface Get response;\n\t method ActionValue#(dtype) get();\n\t    responseFifo.deq();\n\t    return responseFifo.first();\n\t endmethod\n      endinterface\n   endinterface\nendmodule\n"
  },
  {
    "path": "bsv/CnocPortal.bsv",
    "content": "// Copyright (c) 2013 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\nimport ConnectalConfig::*;\nimport FIFOF::*;\nimport Vector::*;\nimport ConnectalMemTypes::*;\nimport Pipe::*;\nimport Portal::*;\nimport HostInterface::*;\n\ntypedef enum {\n   BpHeader,\n   BpMessage\n   } CnocPortalState deriving (Bits,Eq);\n\ninterface PortalMsgRequest;\n   method Bit#(SlaveDataBusWidth) id();\n   interface PipeIn#(Bit#(32)) message;\nendinterface\n\ninterface PortalMsgIndication;\n   method Bit#(SlaveDataBusWidth) id();\n   interface PipeOut#(Bit#(32)) message;\nendinterface\n\ninterface CnocTop#(numeric type numRequests, numeric type numIndications,\n\t\t   numeric type addrWidth, numeric type dataWidth, type pins, numeric type numMasters\n\t\t   );\n   interface Vector#(numRequests, PortalMsgRequest) requests;\n   interface Vector#(numIndications, PortalMsgIndication) indications;\n   interface Vector#(NumReadClients,MemReadClient#(DataBusWidth)) readers;\n   interface Vector#(NumWriteClients,MemWriteClient#(DataBusWidth)) writers;\n   interface pins pins;\nendinterface\n\nmodule mkPortalMsgRequest#(Bit#(SlaveDataBusWidth) portalId, Vector#(numRequests, PipeIn#(Bit#(32))) portal)(PortalMsgRequest);\n   Reg#(Bit#(8)) messageWordsReg <- mkReg(0);\n   Reg#(Bit#(8)) methodIdReg <- mkReg(0);\n   Reg#(CnocPortalState) bpState <- mkReg(BpHeader);\n   FIFOF#(Bit#(32)) fifoMsgSink <- mkFIFOF();\n   Bool verbose = False;\n\n   rule receiveMessageHeader if (bpState == BpHeader);\n      let hdr = fifoMsgSink.first();\n      fifoMsgSink.deq();\n      let methodId = hdr[23:16];\n      Bit#(8) messageWords = hdr[7:0] - 1;\n      if (messageWords == 0)\n          messageWords = 1;\n      methodIdReg <= methodId;\n      if (verbose)\n\t $display(\"receiveMessageHeader portal=%d hdr=%x methodId=%x messageWords=%d\", portalId, hdr, methodId, messageWords);\n      messageWordsReg <= messageWords;\n      if (messageWords != 0)\n\t bpState <= BpMessage;\n   endrule\n   rule receiveMessage if (bpState == BpMessage);\n      let data = fifoMsgSink.first();\n      fifoMsgSink.deq();\n      if (verbose)\n\t $display(\"receiveMessage portal=%d id=%d data=%x messageWords=%d\", portalId, methodIdReg, data, messageWordsReg);\n      portal[methodIdReg].enq(data);\n      messageWordsReg <= messageWordsReg - 1;\n      if (messageWordsReg == 1)\n\t bpState <= BpHeader;\n   endrule\n   method Bit#(SlaveDataBusWidth) id();\n       return portalId;\n   endmethod\n   interface message = toPipeIn(fifoMsgSink);\nendmodule\n\nmodule mkPortalMsgIndication#(Bit#(SlaveDataBusWidth) portalId, Vector#(numIndications, PipeOut#(Bit#(32))) portal, PortalSize messageSize)(PortalMsgIndication);\n   Reg#(Bit#(16)) messageWordsReg <- mkReg(0);\n   Reg#(Bit#(8)) methodIdReg <- mkReg(0);\n   Reg#(CnocPortalState) bpState <- mkReg(BpHeader);\n   Vector#(numIndications, Bool) readyBits = map(pipeOutNotEmpty, portal);\n   Bool      interruptStatus = False;\n   Bit#(8)  readyChannel = -1;\n   FIFOF#(Bit#(32)) fifoMsgSource <- mkFIFOF();\n   function Bool pipeOutNotEmpty(PipeOut#(a) po); return po.notEmpty(); endfunction\n   let verbose = False;\n\n   for (Integer i = valueOf(numIndications) - 1; i >= 0; i = i - 1) begin\n      if (readyBits[i]) begin\n         interruptStatus = True;\n         readyChannel = fromInteger(i);\n      end\n   end\n\n   rule sendHeader if (bpState == BpHeader && interruptStatus);\n      Bit#(16) messageBits = messageSize.size(extend(readyChannel));\n      Bit#(16) roundup = messageBits[4:0] == 0 ? 0 : 1;\n      Bit#(16) numWords = (messageBits >> 5) + roundup;\n      Bit#(32) hdr = extend(readyChannel) << 16 | extend(numWords+1);\n      if (verbose) $display(\"sendHeader portal=%d hdr=%h messageBits=%d numWords=%d\", portalId, hdr, messageBits, numWords);\n      messageWordsReg <= numWords;\n      methodIdReg <= readyChannel;\n      fifoMsgSource.enq(hdr);\n      bpState <= BpMessage;\n   endrule\n   rule sendMessage if (bpState == BpMessage);\n      messageWordsReg <= messageWordsReg - 1;\n      let v = portal[methodIdReg].first;\n      portal[methodIdReg].deq();\n      fifoMsgSource.enq(v);\n      if (verbose) $display(\"sendMessage portal=%d id=%d data=%h messageWords=%d\", portalId, methodIdReg, v, messageWordsReg);\n      if (messageWordsReg == 1) begin\n\t bpState <= BpHeader;\n      end\n   endrule\n   method Bit#(SlaveDataBusWidth) id();\n      return portalId;\n   endmethod\n   interface message = toPipeOut(fifoMsgSource);\nendmodule\n"
  },
  {
    "path": "bsv/ConnectableWithTrace.bsv",
    "content": "// Copyright (c) 2014-2015 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\n`include \"ConnectalProjectConfig.bsv\"\n\nimport AxiMasterSlave::*;\nimport Connectable::*;\nimport BRAM::*;\nimport Bscan::*;\nimport Vector::*;\nimport FIFOF::*;\n\ntypeclass ConnectableWithTrace#(type a, type b, type c);\n   module mkConnectionWithTrace#(a x1, b x2, c x3)(Empty);\nendtypeclass\n\n//`define TRACE_AXI\n//`define AXI_READ_TIMING\n//`define AXI_WRITE_TIMING\n`define TRACE_ADDR_WIDTH 12 //8\n`define TRACE_ADDR_SIZE  4096 //256\n\ninstance ConnectableWithTrace#(Axi3Master#(addrWidth, busWidth,idWidth), Axi3Slave#(addrWidth, busWidth,idWidth), BscanTop)\n   provisos(Add#(0,addrWidth,32));\n   module mkConnectionWithTrace#(Axi3Master#(addrWidth, busWidth,idWidth) m, Axi3Slave#(addrWidth, busWidth,idWidth) s, BscanTop bscan)(Empty);\n\n`ifndef TRACE_AXI\n   mkConnection(m, s);\n`else\n\n   Clock defaultClock <- exposeCurrentClock();\n   Reset defaultReset <- exposeCurrentReset();\n   Reg#(Bit#(`TRACE_ADDR_WIDTH)) addrReg <- mkReg(9);\n   BscanBram#(Bit#(`TRACE_ADDR_WIDTH), Bit#(64)) bscanBram <- mkBscanBram(127, addrReg, bscan);\n   BRAM_Configure bramCfg = defaultValue;\n   bramCfg.memorySize = `TRACE_ADDR_SIZE;\n   bramCfg.latency = 1;\n   BRAM2Port#(Bit#(`TRACE_ADDR_WIDTH), Bit#(64)) traceBram <- mkBRAM2Server(bramCfg);\n   mkConnection(bscanBram.bramClient, traceBram.portB);\n   rule tdorule;\n      bscan.tdo(bscanBram.data_out());\n   endrule\n\n   Vector#(5, FIFOF#(Bit#(64))) bscan_fifos <- replicateM(mkFIFOF);\n\n   let interrupt_bit = 1'b0;\n   rule write_bscanBram;\n      Bit#(64) data = ?;\n      if (bscan_fifos[0].notEmpty) begin\n\t data = bscan_fifos[0].first;\n\t bscan_fifos[0].deq;\n      end\n      else if (bscan_fifos[1].notEmpty) begin\n\t data = bscan_fifos[1].first;\n\t bscan_fifos[1].deq;\n      end\n      else if (bscan_fifos[2].notEmpty) begin\n\t data = bscan_fifos[2].first;\n\t bscan_fifos[2].deq;\n      end\n      else if (bscan_fifos[3].notEmpty) begin\n\t data = bscan_fifos[3].first;\n\t bscan_fifos[3].deq;\n      end\n      else begin\n\t data = bscan_fifos[4].first;\n\t bscan_fifos[4].deq;\n      end\n      traceBram.portA.request.put(BRAMRequest {write:True, responseOnWrite:False, address:addrReg, datain:data});\n      addrReg <= addrReg + 1;\n   endrule\n\n   Reg#(Bit#(16)) seqCounter <- mkReg(0);\n   (* fire_when_enabled *)\n   rule seqinc;\n       seqCounter <= seqCounter + 1;\n   endrule\n\n   // AXI trace for JTAG\n   //mkConnection(m.req_ar, s.req_ar);\n   rule connect_req_ar;\n       let req <- m.req_ar.get();\n       s.req_ar.put(req);\n       bscan_fifos[0].enq(\n\t   {3'h1, interrupt_bit, 6'h0, req.id[5:0],\n`ifdef AXI_READ_TIMING\n\t    seqCounter,\n`else\n\t    req.len, req.cache, req.prot, req.size,\n\t    pack(req.burst == 2'b01), pack(req.lock == 0 && req.qos == 0),\n`endif\n\t    req.address});\n   endrule\n   //mkConnection(s.resp_read, m.resp_read);\n   rule connect_resp_read;\n       let resp <- s.resp_read.get();\n       m.resp_read.put(resp);\n       bscan_fifos[1].enq(\n           {3'h2, interrupt_bit, 6'h0, resp.id[5:0],\n`ifdef AXI_READ_TIMING\n\t    seqCounter,\n`else\n\t    resp.resp, resp.last, 13'b0,\n`endif\n\t    resp.data[31:0]});\n   endrule\n   //mkConnection(m.req_aw, s.req_aw);\n   rule connect_req_aw;\n       let req <- m.req_aw.get();\n       s.req_aw.put(req);\n       bscan_fifos[2].enq(\n           {3'h3, interrupt_bit, 6'h0, req.id[5:0],\n`ifdef AXI_WRITE_TIMING\n\t    seqCounter,\n`else\n\t    req.len, req.cache, req.prot, req.size,\n\t    pack(req.burst == 2'b01), pack(req.lock == 0 && req.qos == 0),\n`endif\n\t    req.address});\n   endrule\n   //mkConnection(m.resp_write, s.resp_write);\n   rule connect_resp_write;\n       let resp <- m.resp_write.get();\n       s.resp_write.put(resp);\n       bscan_fifos[3].enq(\n           {3'h4, interrupt_bit, 6'h0, resp.id[5:0],\n`ifdef AXI_WRITE_TIMING\n\t    seqCounter,\n`else\n\t    resp.last, resp.byteEnable[3:0], 11'b0,\n`endif\n\t    resp.data[31:0]});\n   endrule\n   //mkConnection(s.resp_b, m.resp_b);\n   rule connect_resp_b;\n       let resp <- s.resp_b.get();\n       m.resp_b.put(resp);\n       bscan_fifos[4].enq(\n           {3'h5, interrupt_bit, 6'h0, resp.id[5:0], resp.resp, 46'b0});\n   endrule\n`endif\n   endmodule\nendinstance\n\ninterface TraceReadout;\n   interface BRAMClient#(Bit#(`TRACE_ADDR_WIDTH),Bit#(64)) bramClient;\nendinterface\n\ninstance ConnectableWithTrace#(Axi3Master#(addrWidth, busWidth,idWidth), Axi3Slave#(addrWidth, busWidth,idWidth), TraceReadout)\n   provisos(Add#(0,addrWidth,32));\n   module mkConnectionWithTrace#(Axi3Master#(addrWidth, busWidth,idWidth) m, Axi3Slave#(addrWidth, busWidth,idWidth) s, TraceReadout readout)(Empty);\n\n   Reg#(Bit#(`TRACE_ADDR_WIDTH)) addrReg <- mkReg(9);\n   BRAM_Configure bramCfg = defaultValue;\n   bramCfg.memorySize = `TRACE_ADDR_SIZE;\n   bramCfg.latency = 1;\n   BRAM2Port#(Bit#(`TRACE_ADDR_WIDTH), Bit#(64)) traceBram <- mkBRAM2Server(bramCfg);\n   mkConnection(readout.bramClient, traceBram.portB);\n\n   Vector#(5, FIFOF#(Bit#(64))) bscan_fifos <- replicateM(mkFIFOF);\n\n   let interrupt_bit = 1'b0;\n   rule write_bscanBram;\n      Bit#(64) data = ?;\n      if (bscan_fifos[0].notEmpty) begin\n\t data = bscan_fifos[0].first;\n\t bscan_fifos[0].deq;\n      end\n      else if (bscan_fifos[1].notEmpty) begin\n\t data = bscan_fifos[1].first;\n\t bscan_fifos[1].deq;\n      end\n      else if (bscan_fifos[2].notEmpty) begin\n\t data = bscan_fifos[2].first;\n\t bscan_fifos[2].deq;\n      end\n      else if (bscan_fifos[3].notEmpty) begin\n\t data = bscan_fifos[3].first;\n\t bscan_fifos[3].deq;\n      end\n      else begin\n\t data = bscan_fifos[4].first;\n\t bscan_fifos[4].deq;\n      end\n      traceBram.portA.request.put(BRAMRequest {write:True, responseOnWrite:False, address:addrReg, datain:data});\n      addrReg <= addrReg + 1;\n   endrule\n\n   Reg#(Bit#(16)) seqCounter <- mkReg(0);\n   (* fire_when_enabled *)\n   rule seqinc;\n       seqCounter <= seqCounter + 1;\n   endrule\n\n   // AXI trace for JTAG\n   //mkConnection(m.req_ar, s.req_ar);\n   rule connect_req_ar;\n       let req <- m.req_ar.get();\n       s.req_ar.put(req);\n       bscan_fifos[0].enq(\n\t   {3'h1, interrupt_bit, 6'h0, req.id[5:0],\n`ifdef AXI_READ_TIMING\n\t    seqCounter,\n`else\n\t    req.len, req.cache, req.prot, req.size,\n\t    pack(req.burst == 2'b01), pack(req.lock == 0 && req.qos == 0),\n`endif\n\t    req.address});\n   endrule\n   //mkConnection(s.resp_read, m.resp_read);\n   rule connect_resp_read;\n       let resp <- s.resp_read.get();\n       m.resp_read.put(resp);\n       bscan_fifos[1].enq(\n           {3'h2, interrupt_bit, 6'h0, resp.id[5:0],\n`ifdef AXI_READ_TIMING\n\t    seqCounter,\n`else\n\t    resp.resp, resp.last, 13'b0,\n`endif\n\t    resp.data[31:0]});\n   endrule\n   //mkConnection(m.req_aw, s.req_aw);\n   rule connect_req_aw;\n       let req <- m.req_aw.get();\n       s.req_aw.put(req);\n       bscan_fifos[2].enq(\n           {3'h3, interrupt_bit, 6'h0, req.id[5:0],\n`ifdef AXI_WRITE_TIMING\n\t    seqCounter,\n`else\n\t    req.len, req.cache, req.prot, req.size,\n\t    pack(req.burst == 2'b01), pack(req.lock == 0 && req.qos == 0),\n`endif\n\t    req.address});\n   endrule\n   //mkConnection(m.resp_write, s.resp_write);\n   rule connect_resp_write;\n       let resp <- m.resp_write.get();\n       s.resp_write.put(resp);\n       bscan_fifos[3].enq(\n           {3'h4, interrupt_bit, 6'h0, resp.id[5:0],\n`ifdef AXI_WRITE_TIMING\n\t    seqCounter,\n`else\n\t    resp.last, resp.byteEnable[3:0], 11'b0,\n`endif\n\t    resp.data[31:0]});\n   endrule\n   //mkConnection(s.resp_b, m.resp_b);\n   rule connect_resp_b;\n       let resp <- s.resp_b.get();\n       m.resp_b.put(resp);\n       bscan_fifos[4].enq(\n           {3'h5, interrupt_bit, 6'h0, resp.id[5:0], resp.resp, 46'b0});\n   endrule\n   endmodule\nendinstance\n"
  },
  {
    "path": "bsv/ConnectalAlteraCells.bsv",
    "content": "\n// Copyright (c) 2014 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\nimport Clocks       :: *;\nimport DefaultValue :: *;\nimport Vector       :: *;\nimport ConnectalClocks ::*;\n\n"
  },
  {
    "path": "bsv/ConnectalBram.bsv",
    "content": "// Copyright (c) 2015 Connectal Project\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\nimport FIFO::*;\nimport FIFOF::*;\nimport Vector::*;\nimport BRAM::*;\nimport BRAMCore::*;\nimport GetPut::*;\nimport ClientServer::*;\nimport OldEHR::*;\nimport ConfigCounter::*;\n\ninterface BRAMServers#(numeric type numServers, type addr, type data);\n   interface Vector#(numServers, BRAM1Port#(addr,data)) ports;\nendinterface\n\nmodule mkBRAMServers#(BRAM_Configure bramConfig)(BRAMServers#(numServers, addr, data))\n   provisos (Bits#(addr,asz),\n\t     Bits#(data,dsz));\n   let memorySize = bramConfig.memorySize == 0 ? 2**valueOf(asz) : bramConfig.memorySize;\n   BRAM_DUAL_PORT#(addr,data) bram <- mkBRAMCore2(memorySize, True); // latency 2\n   Vector#(2, FIFOF#(data)) responseFifo <- replicateM(mkSizedFIFOF(2));\n   // EHR did not work here, CReg doesn't seem to go into a vector, so using Wire. -Jamey\n   Vector#(2, Wire#(Maybe#(Tuple2#(Bool,data)))) data0 <- replicateM(mkDWire(tagged Invalid));\n   Vector#(2, Reg#(Maybe#(Tuple2#(Bool,data)))) data1 <- replicateM(mkReg(tagged Invalid));\n   Vector#(2, Reg#(Maybe#(Tuple2#(Bool,data)))) data2 <- replicateM(mkReg(tagged Invalid));\n   Vector#(2, ConfigCounter#(2)) counter <- replicateM(mkConfigCounter(2));\n\n   let verbose = False;\n\n   function BRAM_PORT#(addr, data) portsel(Integer port);\n      return (port == 0) ? bram.a : bram.b;\n   endfunction\n   \n   for (Integer i = 0; i < 2; i = i + 1) begin\n      rule bramRule;\n\t // zeroth stage\n\t let d0 = data0[i];\n\t data1[i] <= d0;\n\n\t // first stage // address register\n\t let d1 = data1[i];\n\t data2[i] <= d1;\n\n\t // second stage\n\t let d2 = data2[i];\n\t if (d2 matches tagged Valid .tpl) begin\n\t    match { .write, .data } = tpl;\n\t    if (!write)\n\t       data = portsel(i).read();\n\t    if (responseFifo[i].notFull())\n\t       responseFifo[i].enq(data);\n\t    else\n\t       $display(\"Error: responseFifo is unexpectedly full\");\n\t end\n      endrule\n   end\n\n   Reg#(Bit#(32)) cycles <- mkReg(0);\n   rule cyclesRule if (verbose);\n      cycles <= cycles + 1;\n   endrule\n\n   function BRAM1Port#(addr,data) server(Integer i);\n      return (interface BRAM1Port#(addr,data);\n\t interface BRAMServer portA;\n\t interface Put request;\n\t    method Action put(BRAMRequest#(addr,data) req) if (counter[i].positive());\n\t      if (verbose) $display(\"%d %d addr %h data %h write %d counter %d\", memorySize, cycles, req.address, req.datain, req.write, counter[i].read());\n\t      portsel(i).put(req.write, req.address, req.datain);\n\t      if (!req.write || req.responseOnWrite) begin\n\t\t counter[i].decrement(1);\n\t\t data0[i] <= tagged Valid tuple2(req.write, req.datain);\n\t      end\n\t    endmethod\n\t endinterface\n\t interface Get response;\n\t    method ActionValue#(data) get();\n\t      let v <- toGet(responseFifo[i]).get();\n\t      if (verbose) $display(\"%d %d data %h counter %d\", memorySize, cycles, v, counter[i].read());\n\t      counter[i].increment(1);\n\t      return v;\n\t    endmethod\n\t endinterface: response\n\t endinterface: portA\n\t      method Action portAClear();\n\t\t //FIXME\n\t      endmethod\n\t endinterface);\n   endfunction\n\n   interface ports = genWith(server);\nendmodule\n\nmodule mkBRAM2Server#(BRAM_Configure bramConfig)(BRAM2Port#(addr, data))\n   provisos (Bits#(addr, a__),\n\t     Bits#(data, b__));\n   BRAMServers#(2,addr,data) cbram <- mkBRAMServers(bramConfig);\n   \n   interface portA = cbram.ports[0].portA;\n   interface portB = cbram.ports[1].portA;\n   method portAClear = cbram.ports[0].portAClear;\n   method portBClear = cbram.ports[1].portAClear;\nendmodule\n\nmodule mkBRAM1Server#(BRAM_Configure bramConfig)(BRAM1Port#(addr, data))\n   provisos (Bits#(addr, a__),\n\t     Bits#(data, b__));\n   BRAMServers#(1,addr,data) cbram <- mkBRAMServers(bramConfig);\n   \n   interface portA = cbram.ports[0].portA;\n   method portAClear = cbram.ports[0].portAClear;\nendmodule\n\nexport mkBRAM1Server;\nexport mkBRAM2Server;"
  },
  {
    "path": "bsv/ConnectalBramFifo.bsv",
    "content": "// Copyright (c) 2015 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\nimport Clocks::*;\nimport Vector::*;\nimport FIFO::*;\nimport FIFOF::*;\nimport BRAMFIFO::*;\nimport CBus::*; // extendNP and truncateNP\n\n`include \"ConnectalProjectConfig.bsv\"\nimport Arith::*;\nimport ConnectalClocks::*;\n\n`ifdef SIMULATION\n`ifdef BOARD_xsim\n`define USE_XILINX_MACRO\n`endif // xsim\n`else // not SIMULATION\n`ifdef XILINX\n`define USE_XILINX_MACRO\n`endif // XILINX\n`endif // not SIMULATION\n\n`ifdef USE_XILINX_MACRO\n(* always_ready, always_enabled *)\ninterface X7FifoSyncMacro#(numeric type data_width);\n   method Bit#(1) empty();\n   method Bit#(1) full();\n   method Action din(Bit#(data_width) v);\n   method Action wren(Bit#(1) wren);\n   method Bit#(data_width) dout();\n   method Action rden(Bit#(1) rden);\n   method Bit#(9) wrcount();\n   method Bit#(9) rdcount();\nendinterface\n\nimport \"BVI\" FIFO_DUALCLOCK_MACRO =\nmodule  vmkBramFifo#(String fifo_size, Clock wrClock, Reset wrReset, Clock rdClock, Reset rdReset)(X7FifoSyncMacro#(data_width));\n`ifndef BSV_POSITIVE_RESET\n   let rdReset1 <- mkSyncReset(10, rdReset, wrClock);\n   let eitherReset <- mkResetEither(wrReset, rdReset1, clocked_by wrClock);\n   let positiveReset <- mkPositiveReset(10, eitherReset, wrClock);\n   // rst must be asserted for 5 read and write clock cycles\n   let fifoReset = positiveReset.positiveReset;\n`else\n   let fifoReset = wrReset;\n`endif\n`ifdef XilinxUltrascale\n   parameter DEVICE = \"ULTRASCALE\";\n`else\n   parameter DEVICE = \"7SERIES\";\n`endif\n   parameter DATA_WIDTH = valueOf(data_width);\n   parameter FIFO_SIZE = fifo_size;\n`ifndef SIMULATION\n   parameter FIRST_WORD_FALL_THROUGH = \"TRUE\"; // not supported by xsim\n`else\n   parameter FIRST_WORD_FALL_THROUGH = True;\n`endif\n   default_clock wrClock(WRCLK) = wrClock;\n   no_reset;\n   // RST is asynchronous\n   input_reset wrReset(RST) clocked_by(no_clock) = fifoReset;\n   input_clock rdClock(RDCLK) = rdClock;\n   method EMPTY empty() clocked_by (rdClock) reset_by (wrReset);\n   method FULL full() clocked_by (wrClock) reset_by (wrReset);\n   method din(DI) enable ((*inhigh*)EN_di) clocked_by (wrClock) reset_by (wrReset);\n   method wren(WREN) enable ((*inhigh*)EN_wren) clocked_by (wrClock) reset_by (wrReset);\n   method DO dout() clocked_by (rdClock) reset_by (wrReset);\n   method rden(RDEN) enable ((*inhigh*)EN_rden) clocked_by (rdClock) reset_by (wrReset);\n   // wrcount and rdcount ports are needed for xsim\n   method WRCOUNT wrcount() clocked_by (wrClock) reset_by (wrReset);\n   method RDCOUNT rdcount() clocked_by (rdClock) reset_by (wrReset);\n   schedule (empty, full, dout, din, wren, rden, wrcount, rdcount) CF (empty, full, dout, din, wren, rden, wrcount, rdcount);\nendmodule\n\nmodule mkDualClockBramFIFOF#(Clock srcClock, Reset srcReset, Clock dstClock, Reset dstReset)(FIFOF#(t))\n   provisos (Bits#(t,sizet),\n\t     Add#(1,a__,sizet));\n   String fifo_size = \"18Kb\";\n   Vector#(TDiv#(sizet,36),X7FifoSyncMacro#(36)) fifos <- replicateM(vmkBramFifo(fifo_size, srcClock, srcReset, dstClock, dstReset));\n   Wire#(Bit#(1)) rdenWire <- mkDWire(0, clocked_by dstClock, reset_by dstReset);\n   Wire#(Bit#(1)) wrenWire <- mkDWire(0, clocked_by srcClock, reset_by srcReset);\n   Vector#(TDiv#(sizet,36),Wire#(Bit#(36))) dinWires <- replicateM(mkDWire(0, clocked_by srcClock, reset_by srcReset));\n\n   for (Integer i = 0; i < valueOf(TDiv#(sizet,36)); i = i+1) begin\n      Reg#(Bit#(9)) rdcount <- mkReg(0, clocked_by dstClock, reset_by dstReset);\n      Reg#(Bit#(9)) wrcount <- mkReg(0, clocked_by srcClock, reset_by srcReset);\n      rule rdenRule;\n\t fifos[i].rden(rdenWire);\n      endrule\n      rule wrenRule;\n\t fifos[i].wren(wrenWire);\n      endrule\n      rule inputs;\n\t fifos[i].din(dinWires[i]);\n      endrule\n      rule countrds;\n\t rdcount <= fifos[i].rdcount();\n      endrule\n      rule countwrs;\n\t wrcount <= fifos[i].wrcount();\n      endrule\n   end\n\n   function Bool fifoNotEmpty(X7FifoSyncMacro#(36) f); return f.empty == 0; endfunction\n   function Bool fifoNotFull(X7FifoSyncMacro#(36) f); return f.full == 0; endfunction\n\n   method t first() if (all(fifoNotEmpty, fifos));\n      function Bit#(36) fifoFirst(Integer i); return fifos[i].dout(); endfunction\n      Vector#(TDiv#(sizet,36), Bit#(36)) v = genWith(fifoFirst);\n      return unpack(truncateNP(pack(v)));\n   endmethod\n   method Action deq() if (all(fifoNotEmpty, fifos));\n      rdenWire <= 1;\n   endmethod\n   method notEmpty = all(fifoNotEmpty, fifos);\n   method Action enq(t v) if (all(fifoNotFull, fifos));\n      Vector#(TDiv#(sizet,36), Bit#(36)) vs = unpack(extendNP(pack(v)));\n      Vector#(TDiv#(sizet,36), Integer) indices = genVector();\n      function Action fifoEnq(Integer i); action dinWires[i] <= vs[i]; endaction endfunction\n      mapM_(fifoEnq, indices);\n      wrenWire <= 1;\n   endmethod\n   method notFull = all(fifoNotEmpty, fifos);\nendmodule\n\nmodule mkDualClockBramFIFO#(Clock srcClock, Reset srcReset, Clock dstClock, Reset dstReset)(FIFO#(t))\n   provisos (Bits#(t,sizet),\n\t     Add#(1,a__,sizet));\n   \n   let syncFifo <- mkDualClockBramFIFOF(srcClock, srcReset, dstClock, dstReset);\n   method enq = syncFifo.enq;\n   method deq = syncFifo.deq;\n   method first = syncFifo.first;\nendmodule\n\n`else // compatibility mode\nmodule mkDualClockBramFIFOF#(Clock srcClock, Reset srcReset, Clock dstClock, Reset dstReset)(FIFOF#(t))\n   provisos (Bits#(t,sizet),\n\t     Add#(1,a__,sizet));\n   let syncFifo <- mkSyncFIFO(512, srcClock, srcReset, dstClock);\n   method enq = syncFifo.enq;\n   method deq = syncFifo.deq;\n   method first = syncFifo.first;\n   method notFull = syncFifo.notFull;\n   method notEmpty = syncFifo.notEmpty;\nendmodule\nmodule mkDualClockBramFIFO#(Clock srcClock, Reset srcReset, Clock dstClock, Reset dstReset)(FIFO#(t))\n   provisos (Bits#(t,sizet),\n\t     Add#(1,a__,sizet));\n   \n   let syncFifo <- mkSyncFIFO(512, srcClock, srcReset, dstClock);\n   method enq = syncFifo.enq;\n   method deq = syncFifo.deq;\n   method first = syncFifo.first;\nendmodule\n`endif\n"
  },
  {
    "path": "bsv/ConnectalClocks.bsv",
    "content": "// Copyright (c) 2014 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\nimport Clocks::*;\n\n`include \"ConnectalProjectConfig.bsv\"\n\n`ifdef PcieClockPeriod\nReal pcieClockPeriod = `PcieClockPeriod;\n`endif\n\nReal mainClockPeriod = `MainClockPeriod;\nReal derivedClockPeriod =`DerivedClockPeriod;\n\n(* always_ready, always_enabled *)\ninterface B2C;\n    interface Clock c;\n    interface Reset r;\n    method Action inputclock(Bit#(1) v);\n    method Action inputreset(Bit#(1) v);\nendinterface\nimport \"BVI\" CONNECTNET2 =\nmodule mkB2C(B2C);\n    default_clock no_clock;\n    default_reset no_reset;\n    output_clock c(OUT1);\n    output_reset r(OUT2);\n    method inputclock(IN1) enable((*inhigh*) en_inputclock) clocked_by(c);\n    method inputreset(IN2) enable((*inhigh*) en_inputreset) clocked_by(c);\n    schedule ( inputclock, inputreset) CF ( inputclock, inputreset);\nendmodule\n\n(* always_ready, always_enabled *)\ninterface B2C1;\n    interface Clock c;\n    method Action inputclock(Bit#(1) v);\nendinterface\nimport \"BVI\" CONNECTNET =\nmodule mkB2C1(B2C1);\n    default_clock clk();\n    default_reset rst();\n    output_clock c(OUT);\n    // method inputclock(IN) enable((*inhigh*) en_inputclock);\n   method inputclock(IN) enable((*inhigh*) en_inputclock) clocked_by(c);\n    schedule ( inputclock) CF ( inputclock);\nendmodule\n\n(* always_ready, always_enabled *)\ninterface C2B;\n    method Bit#(1) o();\nendinterface\nimport \"BVI\" CONNECTNET =\nmodule mkC2B#(Clock c)(C2B);\n    default_clock clk();\n    default_reset no_reset;\n    //default_reset rst();\n    input_clock ck(IN) = c;\n    method OUT o();\n    schedule ( o) CF ( o);\nendmodule\n\n(* always_ready, always_enabled *)\ninterface B2R;\n    interface Reset r;\n    method Action inputreset(Bit#(1) v);\nendinterface\nimport \"BVI\" CONNECTNET =\nmodule mkB2R(B2R);\n    default_clock clk();\n    default_reset rst();\n    output_reset r(OUT);\n    method inputreset(IN) enable((*inhigh*) en_inputclock);\n    schedule ( inputreset) CF ( inputreset);\nendmodule\n\n(* always_ready, always_enabled *)\ninterface R2B;\n    method Bit#(1) o();\nendinterface\nimport \"BVI\" CONNECTNET =\nmodule mkR2B#(Reset r)(C2B);\n    default_clock no_clock;\n    default_reset no_reset;\n    //default_reset rst();\n    input_reset rst(IN) = r;\n    method OUT o();\n    schedule ( o) CF ( o);\nendmodule\n\ninterface PositiveReset;\n   interface Reset positiveReset;\nendinterface\n\nimport \"BVI\" PositiveReset =\nmodule mkPositiveReset#(Integer resetDelay, Reset reset, Clock clock)(PositiveReset);\n   parameter RSTDELAY = resetDelay;\n   default_clock clock(CLK) = clock;\n   default_reset reset(IN_RST) clocked_by (no_clock) = reset;\n   output_reset positiveReset(OUT_RST);\nendmodule\n\ninterface FpgaReset;\n   interface Reset fpgaReset;\nendinterface\n\nimport \"BVI\" FpgaReset =\nmodule exposeFpgaReset#(Integer resetDelay, Clock clock)(FpgaReset);\n   parameter RSTDELAY = resetDelay;\n   default_clock clock(CLK) = clock;\n   no_reset;\n   output_reset fpgaReset(OUT_RST);\nendmodule\n"
  },
  {
    "path": "bsv/ConnectalCompletionBuffer.bsv",
    "content": "// Copyright (c) 2013 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\n// BSV Libraries\nimport BRAMFIFO::*;\nimport FIFO::*;\nimport FIFOF::*;\nimport Vector::*;\nimport GetPut::*;\nimport ClientServer::*;\nimport Assert::*;\nimport BRAM::*;\nimport RegFile::*;\n\n// CONNECTAL Libraries\nimport ConnectalMemTypes::*;\nimport ConnectalMemory::*;\nimport ConfigCounter::*;\n\ninterface TagGen#(numeric type numTags);\n   method ActionValue#(Bit#(TLog#(numTags))) getTag;\n   method Action returnTag(Bit#(TLog#(numTags)) tag);\n   method ActionValue#(Bit#(TLog#(numTags))) complete;\nendinterface\n\nmodule mkTagGen(TagGen#(numTags))\n   provisos(Log#(numTags,tsz));\n   \n   BRAM_Configure cfg = defaultValue;\n   cfg.outFIFODepth = 1;\n   //BRAM2Port#(Bit#(tsz),Bool) tags <- mkBRAM2Server(cfg);\n   //Vector#(numTags, Reg#(Bool)) tags <- replicateM(mkReg(False));\n   Reg#(Bit#(numTags))     tags[2] <- mkCReg(2, 0);\n   Reg#(Bit#(tsz))        head_ptr <- mkReg(0);\n   Reg#(Bit#(tsz))        tail_ptr <- mkReg(0);\n   Reg#(Bool)               inited <- mkReg(False);\n   FIFO#(Bit#(tsz))      comp_fifo <- mkFIFO;\n   Reg#(Bit#(numTags))  comp_state <- mkReg(0);\n   ConfigCounter#(TAdd#(tsz,1)) counter <- mkConfigCounter(fromInteger(valueOf(numTags)));\n   \n   let retFifo <- mkFIFO;\n   let tagFifo <- mkFIFO;\n\n   //rule complete_rule0 (comp_state[0] != 0);\n      //tags.portB.request.put(BRAMRequest{write:False, address:tail_ptr, datain: ?, responseOnWrite: ?});\n   //endrule\n\n   rule complete_rule1 (comp_state[0] != 0);\n      //let rv <- tags.portB.response.get;\n      //let rv = tags[tail_ptr];\n      let rv = tags[1][tail_ptr] == 1;\n      if (!rv) begin\n\t tail_ptr <= tail_ptr+1;\n\t counter.increment(1);\n\t comp_state <= comp_state >> 1;\n\t comp_fifo.enq(tail_ptr);\n      end\n   endrule\n   \n   // this used to be in the body of returnTag, but form some reason bsc does not\n   // consider access to portA and portB to be conflict free **sigh** \n   (* descending_urgency = \"ret_rule, complete_rule1\" *)\n   rule ret_rule;\n      let tag <- toGet(retFifo).get;\n      //tags.portB.request.put(BRAMRequest{write:True, responseOnWrite:False, address:tag, datain:False});\n      //tags[tag] <= False;\n      begin\n\t let t = tags[0];\n\t t[tag] = 0;\n\t tags[0] <= t;\n      end\n      comp_state <= 1 | (comp_state << 1);\n   endrule\n\n   rule init_rule(!inited);\n      //tags.portA.request.put(BRAMRequest{write:True,address:head_ptr,responseOnWrite:False,datain:False});\n      //Not needed: tags[head_ptr] <= False;\n      head_ptr <= head_ptr+1;\n      inited <= head_ptr+1==0;\n   endrule\n   \n   rule tag_rule if (inited && counter.positive);\n      //tags.portA.request.put(BRAMRequest{write:True, responseOnWrite:False, address:head_ptr, datain:True});\n      //tags[head_ptr] <= True;\n      begin\n\t let t = tags[1];\n\t t[head_ptr] = 1;\n\t tags[1] <= t;\n      end\n      head_ptr <= head_ptr+1;\n      tagFifo.enq(head_ptr);\n      counter.decrement(1);\n   endrule\n\n   method ActionValue#(Bit#(tsz)) getTag();\n      let tag <- toGet(tagFifo).get();\n      return tag;\n   endmethod\n\n   method Action returnTag(Bit#(tsz) tag) if (inited);\n      retFifo.enq(tag);\n   endmethod\n   \n   method ActionValue#(Bit#(tsz)) complete;\n      comp_fifo.deq;\n      return comp_fifo.first;\n   endmethod\n   \nendmodule\n"
  },
  {
    "path": "bsv/ConnectalConfig.bsv",
    "content": "// Copyright (c) 2015 Connectal Project\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\n`include \"ConnectalProjectConfig.bsv\"\n\n`ifndef DataBusWidth\n`define DataBusWidth 64\n`endif\n\n// typedef TDiv#(TMax#(128,DataBusWidth),8) TlpDataBytes;\n// typedef TDiv#(TMax#(128,DataBusWidth),32) TlpDataWords;\n\ntypedef TDiv#(128,8) TlpDataBytes;\ntypedef TDiv#(128,32) TlpDataWords;\n\n\ntypedef `PhysAddrWidth PhysAddrWidth;\ntypedef `SlaveDataBusWidth SlaveDataBusWidth;\ntypedef `DataBusWidth DataBusWidth;\ntypedef `NumberOfMasters NumberOfMasters;\ntypedef `SlaveControlAddrWidth SlaveControlAddrWidth;\ntypedef `NumberOfUserTiles NumberOfUserTiles;\ntypedef TAdd#(`NumberOfUserTiles,1) NumberOfTiles;\n`ifndef NumReadClients\ntypedef 2 NumReadClients;\n`else\ntypedef `NumReadClients NumReadClients;\n`endif\n`ifndef NumWriteClients\ntypedef 2 NumWriteClients;\n`else\ntypedef `NumWriteClients NumWriteClients;\n`endif\n//typedef `PinType TileExtType;\n//typedef `PinType PinType;\ntypedef 16 MaxNumberOfPortals;\n`ifdef PcieLanes\ntypedef `PcieLanes PcieLanes;\n`endif\n"
  },
  {
    "path": "bsv/ConnectalEHR.bsv",
    "content": "\n// Copyright (C) 2012 Muralidaran Vijayaraghavan <vmurali@csail.mit.edu>\n\n// Permission is hereby granted, free of charge, to any person obtaining\n// a copy of this software and associated documentation files (the\n// \"Software\"), to deal in the Software without restriction, including\n// without limitation the rights to use, copy, modify, merge, publish,\n// distribute, sublicense, and/or sell copies of the Software, and to\n// permit persons to whom the Software is furnished to do so, subject to\n// the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE\n// LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION\n// OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION\n// WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n\n\n/*\nComments: This EHR design generates the following scheduling constraints (forall i):\nforall j >= i, r[i] < w[j]\nforall j < i, r[i] > w[j]\nforall j > i, w[i] < w[j]\nw[i] conflicts with w[i]\nforall j, r[i] is conflict free with r[j]\n*/\n\nimport Vector::*;\nimport RWire::*;\n\ntypedef  Vector#(n, Reg#(t)) Ehr#(numeric type n, type t);\n\nmodule mkEhr#(t init)(Ehr#(n, t)) provisos(Bits#(t, tSz));\n  Vector#(n, RWire#(t)) lat <- replicateM(mkUnsafeRWire);\n\n  Vector#(n, Reg#(Bool)) dummy2 <- replicateM(mkReg(True));\n\n  Reg#(t) rl <- mkReg(init);\n\n  rule canon;\n    t upd = rl;\n    for(Integer i = 0; i < valueOf(n); i = i + 1)\n      if(lat[i].wget matches tagged Valid .x)\n        upd = x;\n    rl <= upd;\n  endrule\n\n   function Reg#(t) genEhr(Integer i);\n      return (interface Reg;\n\t method Action _write(t x);\n\t    lat[i].wset(x);\n\t    dummy2[i] <= True;\n         endmethod\n\n\t method t _read;\n\t    t upd = rl;\n\t    Bool yes = True;\n\t    for(Integer j = i; j < valueOf(n); j = j + 1)\n\t       yes = yes && dummy2[j];\n\t    for(Integer j = 0; j < i; j = j + 1)\n\t       begin\n                  if(lat[j].wget matches tagged Valid .x)\n                     upd = x;\n\t       end\n\t    return yes? upd : ?;\n         endmethod\n\t endinterface);\n   endfunction\n   \n   Ehr#(n, t) r = genWith(genEhr);\n\n   return r;\nendmodule\n\n"
  },
  {
    "path": "bsv/ConnectalFIFO.bsv",
    "content": "\n// Copyright (C) 2012\n\n// Arvind <arvind@csail.mit.edu>\n// Muralidaran Vijayaraghavan <vmurali@csail.mit.edu>\n// Jamey Hicks <jamey@csail.mit.edu> changed interface to FIFOF\n\n// Permission is hereby granted, free of charge, to any person obtaining\n// a copy of this software and associated documentation files (the\n// \"Software\"), to deal in the Software without restriction, including\n// without limitation the rights to use, copy, modify, merge, publish,\n// distribute, sublicense, and/or sell copies of the Software, and to\n// permit persons to whom the Software is furnished to do so, subject to\n// the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE\n// LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION\n// OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION\n// WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n\nimport FIFOF::*;\nimport ConnectalEHR::*;\n\n// This Fifo2 <- mkCFFifo generates a two element FIFO where enq and deq are conflict free\n// {notEmpty, first} < deq < clear < canon\n// notFull < enq < clear < canon\n// deq conflict free with enq\n\nmodule mkCFFIFOF(FIFOF#(t)) provisos(Bits#(t, tSz));\n  Ehr#(3, t) da <- mkEhr(?);\n  Ehr#(3, Bool) va <- mkEhr(False);\n  Ehr#(3, t) db <- mkEhr(?);\n  Ehr#(3, Bool) vb <- mkEhr(False);\n\n  rule canon if(vb[2] && !va[2]);\n    da[2] <= db[2];\n    va[2] <= True;\n    vb[2] <= False;\n  endrule\n\n  method Bool notFull = !vb[0];\n\n  method Action enq(t x) if(!vb[0]);\n    db[0] <= x;\n    vb[0] <= True;\n  endmethod\n\n  method Bool notEmpty = va[0];\n\n  method Action deq if (va[0]);\n    va[0] <= False;\n  endmethod\n\n  method t first if(va[0]);\n    return da[0];\n  endmethod\n\n  method Action clear;\n    vb[1] <= False;\n    va[1] <= False;\n  endmethod\nendmodule\n\n"
  },
  {
    "path": "bsv/ConnectalMMU.bsv",
    "content": "// Copyright (c) 2013 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\n// BSV Libraries\nimport RegFile::*;\nimport FIFO::*;\nimport FIFOF::*;\nimport Vector::*;\nimport GetPut::*;\nimport Connectable::*;\nimport BRAMFIFO::*;\nimport BRAM::*;\nimport Probe::*;\n\nimport ConnectalBram::*;\nimport ConnectalMemTypes::*;\nimport StmtFSM::*;\nimport ClientServer::*;\nimport ConnectalConfig::*;\nimport ConnectalMemory::*;\nimport ConnectalCompletionBuffer::*;\nimport Pipe::*;\nimport SimDma::*;\n\n`include \"ConnectalProjectConfig.bsv\"\n\ntypedef 32 MaxNumSGLists;\ntypedef Bit#(TLog#(MaxNumSGLists)) SGListId;\ntypedef 12 SGListPageShift0;\ntypedef 16 SGListPageShift4;\ntypedef 20 SGListPageShift8;\ntypedef 24 SGListPageShift12;\ntypedef Bit#(TLog#(MaxNumSGLists)) RegionsIdx;\n\ntypedef 8 IndexWidth;\n\ntypedef struct {\n   SGListId             id;\n   Bit#(MemOffsetSize) off;\n} AddrTransRequest deriving (Eq,Bits,FShow);\n\ntypedef struct {\n   DmaErrorType    error;\n   Bit#(addrWidth) physAddr;\n} AddrTransResponse#(numeric type addrWidth) deriving (Eq,Bits,FShow);\n\ninterface MMU#(numeric type addrWidth);\n   interface MMURequest request;\n   interface Vector#(2,Server#(AddrTransRequest,AddrTransResponse#(addrWidth))) addr;\nendinterface\n\nmodule mkSimpleMMU#(Bit#(4) mmuid, Bool hostMapped, MMUIndication mmuIndication)(MMU#(addrWidth))\n   provisos (Add#(b__,8,addrWidth)\n\t     ,Add#(c__,24,addrWidth)\n\t     ,Bits#(AddrTransResponse#(addrWidth),d__)\n\t     );\n   Vector#(2,FIFOF#(AddrTransRequest)) reqFifos <- replicateM(mkFIFOF());\n   Vector#(2,FIFOF#(AddrTransResponse#(addrWidth))) respFifos <- replicateM(mkFIFOF());\n\n   let probePhysAddr <- mkProbe();\n\n   for (Integer i = 0; i < 2; i = i + 1) begin\n      rule rl_process_req;\n\t let req <- toGet(reqFifos[i]).get();\n\t Bit#(addrWidth) physAddr = extend(req.off[23:0]);\n\t physAddr[31:24] = extend(req.id);\n\t probePhysAddr <= physAddr;\n\t respFifos[i].enq(AddrTransResponse { error: DmaErrorNone, physAddr: physAddr });\n      endrule\n   end\n\n   function Server#(AddrTransRequest,AddrTransResponse#(addrWidth)) genServer(Integer i);\n      return (interface Server#(AddrTransRequest,AddrTransResponse#(addrWidth));\n\t\t interface request = toPut(reqFifos[i]);\n\t interface response = toGet(respFifos[i]);\n\t endinterface);\n   endfunction\n\n   interface MMURequest request;\n      method Action idRequest(SpecialTypeForSendingFd fd);\n\t mmuIndication.idResponse(0);\n      endmethod\n      method Action idReturn(Bit#(32) sglId);\n\t mmuIndication.idResponse(sglId);\n      endmethod\n      method Action region(Bit#(32) pointer, Bit#(64) barr12, Bit#(32) index12, Bit#(64) barr8, Bit#(32) index8, Bit#(64) barr4, Bit#(32) index4, Bit#(64) barr0, Bit#(32) index0);\n\t mmuIndication.configResp(extend(pointer));\n      endmethod\n      method Action sglist(Bit#(32) pointer, Bit#(32) pointerIndex, Bit#(64) addr,  Bit#(32) len);\n\t // no response\n      endmethod\n      method Action setInterface(Bit#(32) interfaceId, Bit#(32) sglId);\n\t /* this method is only implemented in s/w responders */\n      endmethod\n   endinterface\n   interface Vector addr = genWith(genServer);\nendmodule\n\ntypedef struct {\n   DmaErrorType error;\n   Bit#(3) pageSize;\n   Bit#(SGListPageShift12) value;\n} Offset deriving (Eq,Bits,FShow);\n\ntypedef Bit#(TSub#(MemOffsetSize,SGListPageShift0)) Page0;\ntypedef Bit#(TSub#(MemOffsetSize,SGListPageShift4)) Page4;\ntypedef Bit#(TSub#(MemOffsetSize,SGListPageShift8)) Page8;\ntypedef Bit#(TSub#(MemOffsetSize,SGListPageShift12)) Page12;\n\ntypedef struct {\n   Bit#(TSub#(MemOffsetSize,SGListPageShift0)) barrier;\n   Bit#(IndexWidth) idxOffset;\n   } SingleRegion deriving (Eq,Bits,FShow);\n\ntypedef struct {\n   SingleRegion reg12;\n   SingleRegion reg8;\n   SingleRegion reg4;\n   SingleRegion reg0;\n   } Region deriving (Eq,Bits,FShow);\n\ntypedef struct {DmaErrorType errorType;\n\t\tBit#(32) pref;\n\t\tBit#(MemOffsetSize) off;\n   } DmaError deriving (Bits);\n\ntypedef struct {\n   Bool cond12;\n   Bool cond8;\n   Bool cond4;\n   Bool cond0;\n   Bit#(IndexWidth) idxOffset12;\n   Bit#(IndexWidth) idxOffset8;\n   Bit#(IndexWidth) idxOffset4;\n   Bit#(IndexWidth) idxOffset0;\n   AddrTransRequest req;\n   } Stage3Params deriving (Bits);\n\ntypedef struct {\n   Offset off;\n   Bit#(IndexWidth) pbase;\n   Bit#(IndexWidth) idxOffset;\n   SGListId ptr;\n   } Stage4Params deriving (Bits);\n\n// the address translation servers (addr[0], addr[1]) have a latency of 8 and are fully pipelined\nmodule mkMMU#(Bit#(4) mmuid, Bool hostMapped, MMUIndication mmuIndication)(MMU#(PhysAddrWidth))\n   provisos(Log#(MaxNumSGLists, listIdxSize),\n\t    Add#(listIdxSize,8, entryIdxSize));\n   let mmu <- mkMMUSynth(mmuid, hostMapped);\n   rule rl_idResponse;\n      let sglId <- toGet(mmu.idResponsePipe).get();\n      mmuIndication.idResponse(extend(sglId));\n   endrule\n   rule rl_configResp;\n      let sglId <- toGet(mmu.configResponsePipe).get();\n      mmuIndication.configResp(extend(sglId));\n   endrule\n   rule dmaError;\n      let error <- toGet(mmu.errorPipe).get();\n      mmuIndication.error(extend(pack(error.errorType)), error.pref, extend(error.off), extend(mmuid));\n   endrule\n   interface request = mmu.request;\n   interface addr    = mmu.addr;\nendmodule\n\ninterface MMUSynth#(numeric type addrWidth);\n   interface MMURequest request;\n   interface PipeOut#(SGListId) idResponsePipe;\n   interface PipeOut#(SGListId) configResponsePipe;\n   interface PipeOut#(DmaError) errorPipe;\n   interface Vector#(2,Server#(AddrTransRequest,AddrTransResponse#(addrWidth))) addr;\nendinterface\n\n(* synthesize *)\nmodule mkMMUSynth#(Bit#(4) mmuid, Bool hostMapped)(MMUSynth#(PhysAddrWidth));\n\t    \n   let verbose = False;\n   TagGen#(MaxNumSGLists) sglId_gen <- mkTagGen();\n   rule complete_sglId_gen;\n      let __x <- sglId_gen.complete;\n   endrule\n   \n   // for simulators\n   SimDma#(32) simDma <- mkSimDma();\n\n   // stage 0 (latency == 1)\n   Vector#(2, FIFO#(AddrTransRequest)) incomingReqs <- replicateM(mkFIFO);\n\n   // stage 1 (latency == 2)\n   BRAM_Configure bramConfig = defaultValue;\n   bramConfig.latency        = 2;\n   BRAM2Port#(RegionsIdx, Maybe#(Region)) regall <- ConnectalBram::mkBRAM2Server(bramConfig);\n   Vector#(2,FIFOF#(AddrTransRequest))          reqs0 <- replicateM(mkSizedFIFOF(3));\n   \n   // stage 2 (latency == 1)\n   Vector#(2, FIFOF#(Stage3Params)) stage3Params <- replicateM(mkFIFOF);\n\n   // stage 3 (latency == 1)\n   Vector#(2, FIFOF#(Stage4Params)) stage4Params <- replicateM(mkFIFOF);\n\n   // stage 4 (latency == 2)\n   BRAM2Port#(Bit#(TAdd#(TLog#(MaxNumSGLists),8)),Page0) translationTable <- ConnectalBram::mkBRAM2Server(bramConfig);\n   Vector#(2,FIFOF#(Offset))           offs1 <- replicateM(mkSizedFIFOF(3));\n\n   // stage 4 (latnecy == 1)\n   Vector#(2,FIFOF#(AddrTransResponse#(PhysAddrWidth))) pageResponseFifos <- replicateM(mkFIFOF);\n      \n   FIFOF#(DmaError) dmaErrorFifo <- mkFIFOF1();\n   Vector#(2,FIFO#(DmaError)) dmaErrorFifos <- replicateM(mkFIFO1());\n   for (Integer i = 0; i < 2; i = i + 1)\n      mkConnection(toGet(dmaErrorFifos[i]), toPut(dmaErrorFifo));\n\n   let page_shift0 = fromInteger(valueOf(SGListPageShift0));\n   let page_shift4 = fromInteger(valueOf(SGListPageShift4));\n   let page_shift8 = fromInteger(valueOf(SGListPageShift8));\n   let page_shift12 = fromInteger(valueOf(SGListPageShift12));\n   \n   function BRAMServer#(a,b) portsel(BRAM2Port#(a,b) x, Integer i);\n      if(i==0) return x.portA;\n      else return x.portB;\n   endfunction\n   \n   for (Integer i = 0; i < 2; i=i+1) begin\n      rule stage1;  // first read in the address cutoff values between regions\n\t AddrTransRequest req <- toGet(incomingReqs[i]).get();\n\t portsel(regall, i).request.put(BRAMRequest{write:False, responseOnWrite:False,\n            address:truncate(req.id), datain:?});\n\t reqs0[i].enq(req);\n      endrule\n\n      // pipeline the address lookup\n      rule stage2; // Now compare address cutoffs with requested offset\n\t AddrTransRequest req <- toGet(reqs0[i]).get;\n\t Maybe#(Region) m_regionall <- portsel(regall,i).response.get;\n\t \n\t case (m_regionall) matches \n\t    tagged Valid .regionall: begin\n               Page0 off0 = truncate(req.off >> valueOf(SGListPageShift0));\n               Page4 off4 = truncate(req.off >> valueOf(SGListPageShift4));\n               Page8 off8 = truncate(req.off >> valueOf(SGListPageShift8));\n               Page12 off12 = truncate(req.off >> valueOf(SGListPageShift12));\n\t       let cond12 = off12 < truncate(regionall.reg12.barrier);\n\t       let cond8 = off8 < truncate(regionall.reg8.barrier);\n\t       let cond4 = off4 < truncate(regionall.reg4.barrier);\n\t       let cond0 = off0 < regionall.reg0.barrier;\n\t       \n\t       if (verbose) $display(\"mkMMU::stage2: id=%d off=%h (%h %h %h) (%h %h %h)\", req.id, req.off, \n\t\t\t\t     regionall.reg8.barrier, regionall.reg4.barrier, regionall.reg0.barrier,\n\t\t\t\t     off8, off4, off0);\n\t       \n\t       stage3Params[i].enq(Stage3Params {cond12: cond12, cond8: cond8, cond4: cond4, cond0: cond0,\n\t\t\t\t\t\t idxOffset12: regionall.reg12.idxOffset,idxOffset8: regionall.reg8.idxOffset,\n\t\t\t\t\t\t idxOffset4: regionall.reg4.idxOffset, idxOffset0: regionall.reg0.idxOffset,\n\t\t\t\t\t\t req: req });\n\t    end\n\t    tagged Invalid:\n\t       dmaErrorFifos[0].enq(DmaError { errorType: DmaErrorSGLIdInvalid, pref: extend(req.id), off:req.off });\n\t endcase\n      endrule\n      rule stage3; // Based on results of comparision, select a region, putting it into 'o.pageSize'.  idxOffset holds offset in sglist table of relevant entry\n\t let params <- toGet(stage3Params[i]).get();\n\t AddrTransRequest req = params.req;\n\t Offset o = Offset { error: DmaErrorNone, pageSize: 0, value: truncate(req.off)};\n\t Bit#(IndexWidth) pbase = 0;\n\t Bit#(IndexWidth) idxOffset = 0;\n\n\t if (params.cond12) begin\n\t    if (verbose) $display(\"mkMMU::request: req.id=%h req.off=%h\", req.id, req.off);\n\t    o.pageSize = 4;\n\t    pbase = truncate(req.off>>page_shift12);\n\t    idxOffset = params.idxOffset12;\n\t end\n\t else if (params.cond8) begin\n\t    if (verbose) $display(\"mkMMU::request: req.id=%h req.off=%h\", req.id, req.off);\n\t    o.pageSize = 3;\n\t    pbase = truncate(req.off>>page_shift8);\n\t    idxOffset = params.idxOffset8;\n\t end\n\t else if (params.cond4) begin\n\t    if (verbose) $display(\"mkMMU::request: req.id=%h req.off=%h\", req.id, req.off);\n\t    o.pageSize = 2;\n\t    pbase = truncate(req.off>>page_shift4);\n\t    idxOffset = params.idxOffset4;\n\t end\n\t else if (params.cond0) begin\n\t    if (verbose) $display(\"mkMMU::request: req.id=%h req.off=%h\", req.id, req.off);\n\t    o.pageSize = 1;\n\t    pbase = truncate(req.off>>page_shift0);\n\t    idxOffset = params.idxOffset0;\n\t end\n\t stage4Params[i].enq(Stage4Params { off: o, pbase: pbase, idxOffset: idxOffset, ptr: req.id });\n      endrule\n      (* descending_urgency = \"stage2, stage4\" *)\n      rule stage4; // Read relevant sglist entry\n\t let params <- toGet(stage4Params[i]).get();\n\t let off = params.off;\n\t let pbase = params.pbase;\n\t let idxOffset = params.idxOffset;\n\t let ptr = params.ptr;\n\t Bit#(IndexWidth) p = pbase + idxOffset;\n\t if (off.pageSize == 0) begin\n\t    if (verbose) $display(\"mkMMU::addr[%d].request.put: ERROR   ptr=%h off=%h\\n\", i, ptr, off);\n\t    dmaErrorFifos[1].enq(DmaError { errorType: DmaErrorOffsetOutOfRange, pref: extend(ptr), off:extend(off.value) });\n\t    off.error = DmaErrorOffsetOutOfRange;\n\t    p         = 0; // FIXME\n\t end\n\n\t if (verbose) $display(\"mkMMU::translationTable[%d].read %h\", i, {ptr,p});\n\t portsel(translationTable, i).request.put(BRAMRequest{write:False, responseOnWrite:False,\n\t\t\t\t\t\t\t      address:{ptr,p}, datain:?});\n\t offs1[i].enq(off);\n\n      endrule\n      rule stage5; // Concatenate page base address from sglist entry with LSB offset bits from request and return\n\t Page0 page <- portsel(translationTable, i).response.get;\n\t let offset <- toGet(offs1[i]).get();\n\t if (verbose) $display(\"mkMMU::p ages[%d].response page=%h offset=%h\", i, page, offset);\n\t Bit#(PhysAddrWidth) rv = ?;\n\t Page4 b4 = truncate(page);\n\t Page8 b8 = truncate(page);\n\t Page12 b12 = truncate(page);\n\t case (offset.pageSize) \n\t    1: rv = {page,truncate(offset.value)};\n\t    2: rv = {b4,truncate(offset.value)};\n\t    3: rv = {b8,truncate(offset.value)};\n\t    4: rv = {b12,truncate(offset.value)};\n\t endcase\n\t pageResponseFifos[i].enq(AddrTransResponse { error: offset.error, physAddr: truncate(rv) });\n      endrule\n   end\n\n   FIFOF#(SGListId) idResponseFifo <- mkFIFOF1;\n   FIFOF#(SGListId) configResponseFifo <- mkFIFOF1;\n   \n   // given that the BRAM is faster than the connection from software, I see no need for a SizedBRAMFIFOF here. -Jamey\n   FIFOF#(Bit#(32)) idReturnFifo <- mkFIFOF();\n   rule idReturnRule;\n      let sglId <- toGet(idReturnFifo).get;\n      sglId_gen.returnTag(truncate(sglId));\n      portsel(regall, 1).request.put(BRAMRequest{write:True, responseOnWrite:False, address: truncate(sglId), datain: tagged Invalid });\n      $display(\"idReturn %d\", sglId);\n   endrule\n   \n   function Server#(AddrTransRequest,AddrTransResponse#(PhysAddrWidth)) addrServer(Integer i);\n   return\n      (interface Server#(AddrTransRequest,Bit#(PhysAddrWidth));\n\t  interface Put request;\n\t     method Action put(AddrTransRequest req);\n\t\tincomingReqs[i].enq(req);\n\t     endmethod\n\t  endinterface\n\t  interface Get response;\n\t     method ActionValue#(AddrTransResponse#(PhysAddrWidth)) get();\n\t\tlet rv <- toGet(pageResponseFifos[i]).get();\n`ifdef SIMULATION\n\t\trv.physAddr = rv.physAddr | (extend(mmuid)<<valueOf(PhysAddrWidth)-3);\n`endif\n\t\treturn rv;\n\t     endmethod\n\t  endinterface\n       endinterface);\n   endfunction\n      \n   interface MMURequest request;\n   method Action idRequest(SpecialTypeForSendingFd fd);\n      let nextId <- sglId_gen.getTag;\n      let resp = (extend(mmuid) << 16) | extend(nextId);\n      if (verbose) $display(\"mkMMU::idRequest %d\", fd);\n      if (hostMapped) begin\n\t let va <- simDma.initfd(resp, fd);\n      end\n      idResponseFifo.enq(resp);\n   endmethod\n   method Action idReturn(Bit#(32) sglId);\n      idReturnFifo.enq(sglId);\n      if (hostMapped)\n\t simDma.idreturn(sglId);\n   endmethod\n   method Action region(Bit#(32) pointer, Bit#(64) barr12, Bit#(32) index12, Bit#(64) barr8, Bit#(32) index8, Bit#(64) barr4, Bit#(32) index4, Bit#(64) barr0, Bit#(32) index0);\n      portsel(regall, 1).request.put(BRAMRequest{write:True, responseOnWrite:False,\n          address: truncate(pointer), datain: tagged Valid Region{\n             reg12: SingleRegion{barrier: truncate(barr12), idxOffset: truncate(index12)},\n             reg8: SingleRegion{barrier: truncate(barr8), idxOffset: truncate(index8)},\n             reg4: SingleRegion{barrier: truncate(barr4), idxOffset: truncate(index4)},\n             reg0: SingleRegion{barrier: truncate(barr0), idxOffset: truncate(index0)}} });\n      if (verbose) $display(\"mkMMU::region pointer=%d barr12=%h barr8=%h barr4=%h barr0=%h\", pointer, barr12, barr8, barr4, barr0);\n      configResponseFifo.enq(truncate(pointer));\n   endmethod\n\n   method Action sglist(Bit#(32) pointer, Bit#(32) pointerIndex, Bit#(64) addr,  Bit#(32) len);\n         if (extend(mmuid) != pointer[31:16]) begin\n\t    $display(\"mkMMU::sglist ERROR\");\n\t    $finish();\n\t end\n\t if(hostMapped)\n\t    let va <- simDma.init({0,pointer[31:16]}, {0,pointer[15:0]}, len);\n         Bit#(IndexWidth) ind = truncate(pointerIndex);\n\t portsel(translationTable, 0).request.put(BRAMRequest{write:True, responseOnWrite:False,\n             address:{truncate(pointer),ind}, datain:truncate(addr)});\n         if (verbose) $display(\"mkMMU::sglist pointer=%d pointerIndex=%d addr=%d len=%d\", pointer, pointerIndex, addr, len);\n   endmethod\n   method Action setInterface(Bit#(32) interfaceId, Bit#(32) sglId);\n       /* this method is only implemented in s/w responders */\n   endmethod\n   endinterface\n   interface addr = genWith(addrServer);\n\n   interface idResponsePipe     = toPipeOut(idResponseFifo);\n   interface configResponsePipe = toPipeOut(configResponseFifo);\n   interface errorPipe          = toPipeOut(dmaErrorFifo);\nendmodule\n\ninterface ArbitratedMMU#(numeric type addrWidth, numeric type numServers);\n   interface Vector#(numServers,Server#(AddrTransRequest,AddrTransResponse#(addrWidth))) servers;\nendinterface\n\nmodule mkArbitratedMMU#(Server#(AddrTransRequest,AddrTransResponse#(addrWidth)) server) (ArbitratedMMU#(addrWidth,numServers));\n   \n   FIFOF#(Bit#(TAdd#(1,TLog#(numServers)))) tokFifo <- mkSizedFIFOF(9);\n   Reg#(Bit#(TLog#(numServers))) arb <- mkReg(0);\n\n   // this is a very crude arbiter.  something more sophisticated may be required (mdk)\n   rule inc_arb;\n      arb <= arb+1;\n   endrule\n   \n   function Server#(AddrTransRequest,AddrTransResponse#(addrWidth)) arbitratedServer(Integer i);\n   return\n      (interface Server#(AddrTransRequest,AddrTransResponse#(addrWidth));\n\t  interface Put request;\n\t     method Action put(AddrTransRequest req) if (arb == fromInteger(i));\n\t\ttokFifo.enq(fromInteger(i));\n\t\tserver.request.put(req);\n\t     endmethod\n\t  endinterface\n\t  interface Get response;\n\t     method ActionValue#(AddrTransResponse#(addrWidth)) get() if (tokFifo.first == fromInteger(i));\n\t\ttokFifo.deq;\n\t\tlet rv <- server.response.get;\n\t\treturn rv;\n\t     endmethod\n\t  endinterface\n       endinterface);\n   endfunction\n\n   interface servers = genWith(arbitratedServer);\n\nendmodule\n"
  },
  {
    "path": "bsv/ConnectalMemTypes.bsv",
    "content": "// Copyright (c) 2013 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\nimport FIFOF::*;\nimport Adapter::*;\nimport Vector::*;\nimport Connectable::*;\nimport BRAMFIFO::*;\nimport GetPut::*;\nimport ClientServer::*;\n\nimport ConnectalConfig::*;\nimport Pipe::*;\nimport ConnectalMemory::*;\nimport DefaultValue::*;\nimport AxiStream::*;\n\n`include \"ConnectalProjectConfig.bsv\"\n\ntypedef Bit#(32) SGLId;\n`ifndef ZYNQ\ntypedef 40 MemOffsetSize; // must be at least as large as PhysAddrSize\n`else\n`ifdef ZynqUltrascale\ntypedef 40 MemOffsetSize; // ZynqUltrascale PhysAddrWidth=40\n`else\ntypedef 32 MemOffsetSize;\n`endif\n`endif\n`ifdef MemTagSize\ntypedef `MemTagSize MemTagSize;\n`else\ntypedef 6 MemTagSize;\n`endif\ntypedef `BurstLenSize BurstLenSize;\n\n\n`ifdef MemServerTags\n    typedef `MemServerTags MemServerTags;\n`else\n\n    `ifndef USE_ACP\n\t`ifdef PCIE3\n\t// as configured, the Xilinx gen3 PCIe core supports 5 bit tags, and\n\t// we need to use unique tags for all transactions in flight. Since\n\t// MemServer uses the same tag numbers for reads and writes, we use\n\t// tag[4] to distinguish the two, leaving 4 bits for unique tags.\n\t// TODO: There is an option for longer tags in the gen3 core.\n\ttypedef 16 MemServerTags;\n\t`else\n\ttypedef 32 MemServerTags;\n\t`endif\n    `else\n\ttypedef 8 MemServerTags;\n    `endif\n`endif // MemServerTags\n\n`ifdef DataBusWidth\ntypedef TDiv#(`DataBusWidth,8) ByteEnableSize;\n`else\ntypedef TDiv#(64,8) ByteEnableSize;\n`endif\n\n// memory request with physical addresses.\n// these can be transmitted directly to the bus master\ntypedef struct {\n   Bit#(addrWidth) addr;\n   Bit#(BurstLenSize) burstLen;\n   Bit#(MemTagSize) tag;\n`ifdef BYTE_ENABLES\n   Bit#(TDiv#(dataBusWidth,8)) firstbe; // maybe we only need lastbe\n   Bit#(TDiv#(dataBusWidth,8)) lastbe;\n`endif\n   } PhysMemRequest#(numeric type addrWidth, numeric type dataBusWidth) deriving (Bits, Eq, FShow);\n\ninstance DefaultValue#(PhysMemRequest#(addrWidth,dataBusWidth));\n   defaultValue = PhysMemRequest { addr: 0, burstLen: 0, tag: 0\n`ifdef BYTE_ENABLES\n\t\t\t\t  , firstbe: maxBound, lastbe: maxBound\n`endif\n      };\nendinstance\n\n// memory request with \"virtual\" addresses.\n// these need to be translated before they can be send to the bus\ntypedef struct {\n   SGLId sglId;\n   Bit#(MemOffsetSize) offset;\n   Bit#(BurstLenSize) burstLen;\n   Bit#(MemTagSize)  tag;\n`ifdef BYTE_ENABLES\n   Bit#(ByteEnableSize) firstbe; // maybe we only need lastbe\n   Bit#(ByteEnableSize) lastbe;\n`endif\n   } MemRequest deriving (Bits, FShow);\n\ninstance DefaultValue#(MemRequest);\n   defaultValue = MemRequest {\n      sglId: 0, offset: 0, burstLen: 0, tag: 0\n`ifdef BYTE_ENABLES\n      , firstbe: maxBound, lastbe: maxBound\n`endif\n      };\nendinstance\n\n// memory payload\ntypedef struct {\n   Bit#(dsz) data;\n   Bit#(MemTagSize) tag;\n   Bool last;\n`ifdef BYTE_ENABLES_MEM_DATA\n   Bit#(TDiv#(dsz, 8)) byte_enables; // maybe we only need lastbe\n`endif\n   } MemData#(numeric type dsz) deriving (Bits, Eq, FShow);\n\nfunction Bit#(dsz) memDataData(MemData#(dsz) md); return md.data; endfunction\nfunction Bit#(TDiv#(dsz,8)) memDataByteEnable(MemData#(dsz) md);\n`ifdef BYTE_ENABLES_MEM_DATA\n   return md.byte_enables;\n`else\n   return maxBound;\n`endif\nendfunction\n\ntypeclass ReqByteEnables#(type t, numeric type besz);\n   function Bit#(besz) reqFirstByteEnable(t req);\n   function Bit#(besz) reqLastByteEnable(t req);\nendtypeclass\ninstance ReqByteEnables#(PhysMemRequest#(addrWidth,dataBusWidth),TDiv#(dataBusWidth,8));\n`ifdef BYTE_ENABLES\n   function Bit#(TDiv#(dataBusWidth,8)) reqFirstByteEnable(PhysMemRequest#(addrWidth,dataBusWidth) req); return req.firstbe; endfunction\n   function Bit#(TDiv#(dataBusWidth,8)) reqLastByteEnable(PhysMemRequest#(addrWidth,dataBusWidth) req); return req.lastbe; endfunction\n`else\n   function Bit#(TDiv#(dataBusWidth,8)) reqFirstByteEnable(PhysMemRequest#(addrWidth,dataBusWidth) req); return maxBound; endfunction\n   function Bit#(TDiv#(dataBusWidth,8)) reqLastByteEnable(PhysMemRequest#(addrWidth,dataBusWidth) req); return maxBound; endfunction\n`endif\nendinstance\ninstance ReqByteEnables#(MemRequest,ByteEnableSize);\n`ifdef BYTE_ENABLES\n   function Bit#(ByteEnableSize) reqFirstByteEnable(MemRequest req); return req.firstbe; endfunction\n   function Bit#(ByteEnableSize) reqLastByteEnable(MemRequest req); return req.lastbe; endfunction\n`else\n   function Bit#(ByteEnableSize) reqFirstByteEnable(MemRequest req); return maxBound; endfunction\n   function Bit#(ByteEnableSize) reqLastByteEnable(MemRequest req); return maxBound; endfunction\n`endif\nendinstance\n\n///////////////////////////////////////////////////////////////////////////////////\n//\n\ntypedef struct {SGLId sglId;\n\t\tBit#(32) base;\n\t\tBit#(BurstLenSize) burstLen;\n\t\tBit#(32) len;\n\t\tBit#(MemTagSize) tag;\n\t\t} MemengineCmd deriving (Eq,Bits);\n\ninterface MemWriteEngineServer#(numeric type userWidth);\n   interface Put#(MemengineCmd)       request;\n   interface Get#(Bool)               done;\n   interface PipeIn#(Bit#(userWidth)) data;\n   interface PipeOut#(MemRequestCycles)     requestCycles;\nendinterface\n\ninterface MemWriteEngine#(numeric type busWidth, numeric type userWidth, numeric type cmdQDepth, numeric type numServers);\n   interface MemWriteClient#(busWidth) dmaClient;\n   interface Vector#(numServers, MemWriteEngineServer#(userWidth)) writeServers;\nendinterface\n\ntypedef struct {\n   Bit#(dsz) data;\n   Bit#(MemTagSize) tag;\n   Bool first;\n   Bool last;\n   } MemDataF#(numeric type dsz) deriving (Bits);\n\ntypedef struct {\n   Bit#(MemTagSize) tag;\n   Bit#(32)         cycles;\n   } MemRequestCycles deriving (Bits);\n\ninterface MemReadEngineServer#(numeric type userWidth);\n   interface Put#(MemengineCmd)             request;\n   interface PipeOut#(MemDataF#(userWidth)) data;\n   interface PipeOut#(MemRequestCycles)     requestCycles;\nendinterface\n\ninterface MemReadEngine#(numeric type busWidth, numeric type userWidth, numeric type cmdQDepth, numeric type numServers);\n   interface MemReadClient#(busWidth) dmaClient;\n   interface Vector#(numServers, MemReadEngineServer#(userWidth)) readServers;\nendinterface\n\n//\n///////////////////////////////////////////////////////////////////////////////////\n\n\n///////////////////////////////////////////////////////////////////////////////////\n//\n\ninterface MemReadClient#(numeric type dsz);\n   interface Get#(MemRequest)    readReq;\n   interface Put#(MemData#(dsz)) readData;\nendinterface\n\ninterface MemWriteClient#(numeric type dsz);\n   interface Get#(MemRequest)    writeReq;\n   interface Get#(MemData#(dsz)) writeData;\n   interface Put#(Bit#(MemTagSize))       writeDone;\nendinterface\n\ninterface MemClient#(numeric type dsz);\n   interface MemReadClient#(dsz) readClient;\n   interface MemWriteClient#(dsz) writeClient;\nendinterface\n\ninterface MemReadServer#(numeric type dsz);\n   interface Put#(MemRequest) readReq;\n   interface Get#(MemData#(dsz))     readData;\nendinterface\n\ninterface MemWriteServer#(numeric type dsz);\n   interface Put#(MemRequest) writeReq;\n   interface Put#(MemData#(dsz))     writeData;\n   interface Get#(Bit#(MemTagSize))           writeDone;\nendinterface\n\ninterface MemServer#(numeric type dataWidth);\n   interface MemReadServer#(dataWidth) readServer;\n   interface MemWriteServer#(dataWidth) writeServer;\nendinterface\n\n//\n///////////////////////////////////////////////////////////////////////////////////\n//\n\ninterface PhysMemSlave#(numeric type addrWidth, numeric type dataWidth);\n   interface PhysMemReadServer#(addrWidth, dataWidth) read_server;\n   interface PhysMemWriteServer#(addrWidth, dataWidth) write_server;\nendinterface\n\ninterface PhysMemMaster#(numeric type addrWidth, numeric type dataWidth);\n   interface PhysMemReadClient#(addrWidth, dataWidth) read_client;\n   interface PhysMemWriteClient#(addrWidth, dataWidth) write_client;\nendinterface\n\ninterface PhysMemReadClient#(numeric type asz, numeric type dsz);\n   interface Get#(PhysMemRequest#(asz,dsz))    readReq;\n   interface Put#(MemData#(dsz)) readData;\nendinterface\n\ninterface PhysMemWriteClient#(numeric type asz, numeric type dsz);\n   interface Get#(PhysMemRequest#(asz,dsz))    writeReq;\n   interface Get#(MemData#(dsz)) writeData;\n   interface Put#(Bit#(MemTagSize))       writeDone;\nendinterface\n\ninterface PhysMemReadServer#(numeric type asz, numeric type dsz);\n   interface Put#(PhysMemRequest#(asz,dsz)) readReq;\n   interface Get#(MemData#(dsz))     readData;\nendinterface\n\ninterface PhysMemWriteServer#(numeric type asz, numeric type dsz);\n   interface Put#(PhysMemRequest#(asz,dsz)) writeReq;\n   interface Put#(MemData#(dsz))     writeData;\n   interface Get#(Bit#(MemTagSize))           writeDone;\nendinterface\n\n//\n///////////////////////////////////////////////////////////////////////////////////\n\ninstance Connectable#(MemReadClient#(dsz), MemReadServer#(dsz));\n   module mkConnection#(MemReadClient#(dsz) source, MemReadServer#(dsz) sink)(Empty);\n      rule mr_request;\n\t let req <- source.readReq.get();\n\t sink.readReq.put(req);\n      endrule\n      rule mr_response;\n\t let resp <- sink.readData.get();\n\t source.readData.put(resp);\n      endrule\n   endmodule\nendinstance\n\ninstance Connectable#(MemWriteClient#(dsz), MemWriteServer#(dsz));\n   module mkConnection#(MemWriteClient#(dsz) source, MemWriteServer#(dsz) sink)(Empty);\n      rule mw_request;\n\t let req <- source.writeReq.get();\n\t sink.writeReq.put(req);\n      endrule\n      rule mw_response;\n\t let resp <- source.writeData.get();\n\t sink.writeData.put(resp);\n      endrule\n      rule mw_done;\n\t let resp <- sink.writeDone.get();\n\t source.writeDone.put(resp);\n      endrule\n   endmodule\nendinstance\n\ninstance Connectable#(MemClient#(dsz), MemServer#(dsz));\n   module mkConnection#(MemClient#(dsz) source, MemServer#(dsz) sink)(Empty);\n      mkConnection(source.readClient, sink.readServer);\n      mkConnection(source.writeClient, sink.writeServer);\n   endmodule\nendinstance\n\ninstance Connectable#(PhysMemMaster#(addrWidth, busWidth), PhysMemSlave#(addrWidth, busWidth));\n   module mkConnection#(PhysMemMaster#(addrWidth, busWidth) m, PhysMemSlave#(addrWidth, busWidth) s)(Empty);\n      mkConnection(m.read_client.readReq, s.read_server.readReq);\n      mkConnection(s.read_server.readData, m.read_client.readData);\n      mkConnection(m.write_client.writeReq, s.write_server.writeReq);\n      mkConnection(m.write_client.writeData, s.write_server.writeData);\n      mkConnection(s.write_server.writeDone, m.write_client.writeDone);\n   endmodule\nendinstance\n\n// this is used for debugging MemToPcie/PcieToMem in BsimTop.bsv\ninstance Connectable#(PhysMemMaster#(32, busWidth), PhysMemSlave#(40, busWidth));\n   module mkConnection#(PhysMemMaster#(32, busWidth) m, PhysMemSlave#(40, busWidth) s)(Empty);\n      //mkConnection(m.read_client.readReq, s.read_server.readReq);\n      rule readreq;\n\t let req <- m.read_client.readReq.get();\n\t s.read_server.readReq.put(PhysMemRequest { addr: extend(req.addr), burstLen: req.burstLen, tag: req.tag\n`ifdef BYTE_ENABLES\n\t\t\t\t\t\t   , firstbe: req.firstbe, lastbe: req.lastbe\n`endif\n\t    });\n      endrule\n\n      mkConnection(s.read_server.readData, m.read_client.readData);\n      //mkConnection(m.write_client.writeReq, s.write_server.writeReq);\n      rule writereq;\n\t let req <- m.write_client.writeReq.get();\n\t s.write_server.writeReq.put(PhysMemRequest { addr: extend(req.addr), burstLen: req.burstLen, tag: req.tag\n`ifdef BYTE_ENABLES\n\t\t\t\t\t\t     , firstbe: req.firstbe, lastbe: req.lastbe\n`endif\n });\n      endrule\n      mkConnection(m.write_client.writeData, s.write_server.writeData);\n      mkConnection(s.write_server.writeDone, m.write_client.writeDone);\n   endmodule\nendinstance\n\nfunction Bool isQuadWordAligned(Bit#(7) lower_addr);\n   return (lower_addr[2:0]==3'b0);\nendfunction\n\nfunction Put#(t) null_put();\n   return (interface Put;\n              method Action put(t x) if (False);\n                 noAction;\n              endmethod\n           endinterface);\nendfunction\n\nfunction Get#(t) null_get();\n   return (interface Get;\n              method ActionValue#(t) get() if (False);\n                 return ?;\n              endmethod\n           endinterface);\nendfunction\n\nfunction  PhysMemWriteClient#(addrWidth, busWidth) null_phys_mem_write_client();\n   return (interface PhysMemWriteClient;\n              interface Get writeReq = null_get;\n              interface Get writeData = null_get;\n              interface Put writeDone = null_put;\n           endinterface);\nendfunction\n\nfunction  PhysMemReadClient#(addrWidth, busWidth) null_phys_mem_read_client();\n   return (interface PhysMemReadClient;\n              interface Get readReq = null_get;\n              interface Put readData = null_put;\n           endinterface);\nendfunction\n\nfunction  MemWriteClient#(busWidth) null_mem_write_client();\n   return (interface MemWriteClient;\n              interface Get writeReq = null_get;\n              interface Get writeData = null_get;\n              interface Put writeDone = null_put;\n           endinterface);\nendfunction\n\nfunction  MemReadClient#(busWidth) null_mem_read_client();\n   return (interface MemReadClient;\n              interface Get readReq = null_get;\n              interface Put readData = null_put;\n           endinterface);\nendfunction\n\ninstance MkAxiStream#(AxiStreamMaster#(dsize), FIFOF#(MemData#(dsize)));\n   module mkAxiStream#(FIFOF#(MemData#(dsize)) f)(AxiStreamMaster#(dsize));\n      Wire#(Bool) readyWire <- mkDWire(False);\n      Wire#(MemData#(dsize)) dataWire <- mkDWire(unpack(0));\n      rule rl_data if (f.notEmpty());\n\t dataWire <= f.first();\n      endrule\n      rule rl_deq if (readyWire && f.notEmpty);\n\t f.deq();\n      endrule\n     method Bit#(dsize)              tdata();\n\treturn dataWire.data;\n     endmethod\n     method Bit#(TDiv#(dsize,8))     tkeep(); return maxBound; endmethod\n     method Bit#(1)                tlast(); return pack(dataWire.last); endmethod\n     method Action                 tready(Bit#(1) v);\n\treadyWire <= unpack(v);\n     endmethod\n     method Bit#(1)                tvalid(); return pack(f.notEmpty()); endmethod\n   endmodule\nendinstance\n\ninstance MkAxiStream#(AxiStreamSlave#(dsize), FIFOF#(MemData#(dsize)));\n   module mkAxiStream#(FIFOF#(MemData#(dsize)) f)(AxiStreamSlave#(dsize));\n      Wire#(Bit#(dsize)) dataWire <- mkDWire(unpack(0));\n      Wire#(Bit#(1))     lastWire <- mkDWire(unpack(0));\n      Wire#(Bool) validWire <- mkDWire(False);\n      rule enq if (validWire && f.notFull());\n\t f.enq(MemData { data: dataWire, last: unpack(lastWire), tag: 0 });\n      endrule\n      method Action      tdata(Bit#(dsize) v);\n\t dataWire <= v;\n      endmethod\n      method Action      tkeep(Bit#(TDiv#(dsize,8)) v); endmethod\n      method Action      tlast(Bit#(1) v); endmethod\n      method Bit#(1)     tready(); return pack(f.notFull()); endmethod\n      method Action      tvalid(Bit#(1) v);\n\t validWire <= unpack(v);\n      endmethod\n   endmodule\nendinstance\n\ninstance MkAxiStream#(AxiStreamMaster#(dsize), FIFOF#(MemDataF#(dsize)));\n   module mkAxiStream#(FIFOF#(MemDataF#(dsize)) f)(AxiStreamMaster#(dsize));\n      Wire#(Bool) readyWire <- mkDWire(False);\n      Wire#(Bool) lastWire <- mkDWire(False);\n      rule rl_deq if (readyWire && f.notEmpty);\n\t f.deq();\n\t lastWire <= f.first().last;\n      endrule\n     method Bit#(dsize)              tdata();\n\tif (f.notEmpty())\n\t  return f.first().data;\n\telse\n\t  return 0;\n     endmethod\n     method Bit#(TDiv#(dsize,8))     tkeep(); return maxBound; endmethod\n     method Bit#(1)                tlast(); return pack(lastWire); endmethod\n     method Action                 tready(Bit#(1) v);\n\treadyWire <= unpack(v);\n     endmethod\n     method Bit#(1)                tvalid(); return pack(f.notEmpty()); endmethod\n   endmodule\nendinstance\n\ninstance MkAxiStream#(AxiStreamSlave#(dsize), FIFOF#(MemDataF#(dsize)));\n   module mkAxiStream#(FIFOF#(MemDataF#(dsize)) f)(AxiStreamSlave#(dsize));\n      Reg#(Bool) first <- mkReg(True);\n      Wire#(Bit#(dsize)) dataWire <- mkDWire(unpack(0));\n      Wire#(Bool) validWire <- mkDWire(False);\n      Wire#(Bool) lastWire <- mkDWire(False);\n      rule enq if (validWire && f.notFull());\n\t f.enq(MemDataF { data: dataWire, last: lastWire, first: first, tag: 0 });\n\t first <= lastWire;\n      endrule\n      method Action      tdata(Bit#(dsize) v);\n\t dataWire <= v;\n      endmethod\n      method Action      tkeep(Bit#(TDiv#(dsize,8)) v); endmethod\n      method Action      tlast(Bit#(1) v); lastWire <= unpack(v); endmethod\n      method Bit#(1)     tready(); return pack(f.notFull()); endmethod\n      method Action      tvalid(Bit#(1) v);\n\t validWire <= unpack(v);\n      endmethod\n   endmodule\nendinstance\n\ninstance MkAxiStream#(AxiStreamMaster#(dsize), PipeOut#(MemDataF#(dsize)));\n   module mkAxiStream#(PipeOut#(MemDataF#(dsize)) f)(AxiStreamMaster#(dsize));\n      Wire#(Bool) readyWire <- mkDWire(False);\n      Wire#(Bool) lastWire <- mkDWire(False);\n      Wire#(Bit#(dsize)) dataWire <- mkDWire(0);\n      rule rl_data if (f.notEmpty());\n\t dataWire <= f.first().data;\n\t lastWire <= f.first().last;\n      endrule\n      rule rl_deq if (readyWire && f.notEmpty);\n\t f.deq();\n      endrule\n     method Bit#(dsize)              tdata();\n\treturn dataWire;\n     endmethod\n     method Bit#(TDiv#(dsize,8))     tkeep(); return maxBound; endmethod\n     method Bit#(1)                tlast(); return pack(lastWire); endmethod\n     method Action                 tready(Bit#(1) v);\n\treadyWire <= unpack(v);\n     endmethod\n     method Bit#(1)                tvalid(); return pack(f.notEmpty()); endmethod\n   endmodule\nendinstance\n\ninstance MkAxiStream#(AxiStreamSlave#(dsize), PipeIn#(MemDataF#(dsize)));\n   module mkAxiStream#(PipeIn#(MemDataF#(dsize)) f)(AxiStreamSlave#(dsize));\n      Reg#(Bool) first <- mkReg(True);\n      Wire#(Bit#(dsize)) dataWire <- mkDWire(unpack(0));\n      Wire#(Bool) validWire <- mkDWire(False);\n      Wire#(Bool) lastWire <- mkDWire(False);\n      rule enq if (validWire && f.notFull());\n\t f.enq(MemDataF { data: dataWire, last: lastWire, first: first, tag: 0 });\n\t first <= lastWire;\n      endrule\n      method Action      tdata(Bit#(dsize) v);\n\t dataWire <= v;\n      endmethod\n      method Action      tkeep(Bit#(TDiv#(dsize,8)) v); endmethod\n      method Action      tlast(Bit#(1) v); lastWire <= unpack(v); endmethod\n      method Bit#(1)     tready(); return pack(f.notFull()); endmethod\n      method Action      tvalid(Bit#(1) v);\n\t validWire <= unpack(v);\n      endmethod\n   endmodule\nendinstance\n\ninstance MkAxiStream#(AxiStreamMaster#(dsize), PipeOut#(MemData#(dsize)));\n   module mkAxiStream#(PipeOut#(MemData#(dsize)) f)(AxiStreamMaster#(dsize));\n      Wire#(Bool) readyWire <- mkDWire(False);\n      Wire#(Bool) lastWire <- mkDWire(False);\n      Wire#(Bit#(dsize)) dataWire <- mkDWire(0);\n      rule rl_data if (f.notEmpty());\n\t dataWire <= f.first().data;\n\t lastWire <= f.first().last;\n      endrule\n      rule rl_deq if (readyWire && f.notEmpty);\n\t f.deq();\n      endrule\n     method Bit#(dsize)              tdata();\n\treturn dataWire;\n     endmethod\n     method Bit#(TDiv#(dsize,8))     tkeep(); return maxBound; endmethod\n     method Bit#(1)                tlast(); return pack(lastWire); endmethod\n     method Action                 tready(Bit#(1) v);\n\treadyWire <= unpack(v);\n     endmethod\n     method Bit#(1)                tvalid(); return pack(f.notEmpty()); endmethod\n   endmodule\nendinstance\n\ninstance MkAxiStream#(AxiStreamSlave#(dsize), PipeIn#(MemData#(dsize)));\n   module mkAxiStream#(PipeIn#(MemData#(dsize)) f)(AxiStreamSlave#(dsize));\n      Wire#(Bit#(dsize)) dataWire <- mkDWire(unpack(0));\n      Wire#(Bool) validWire <- mkDWire(False);\n      Wire#(Bool) lastWire <- mkDWire(False);\n      rule enq if (validWire && f.notFull());\n\t f.enq(MemData { data: dataWire, last: lastWire, tag: 0 });\n      endrule\n      method Action      tdata(Bit#(dsize) v);\n\t dataWire <= v;\n      endmethod\n      method Action      tkeep(Bit#(TDiv#(dsize,8)) v); endmethod\n      method Action      tlast(Bit#(1) v); lastWire <= unpack(v); endmethod\n      method Bit#(1)     tready(); return pack(f.notFull()); endmethod\n      method Action      tvalid(Bit#(1) v);\n\t validWire <= unpack(v);\n      endmethod\n   endmodule\nendinstance\n\ntypeclass MkPhysMemSlave#(type srctype, numeric type addrWidth, numeric type dataWidth);\n   module mkPhysMemSlave#(srctype axiSlave)(PhysMemSlave#(addrWidth,dataWidth));\nendtypeclass\ntypeclass MkPhysMemMaster#(type srctype, numeric type addrWidth, numeric type dataWidth);\n   module mkPhysMemMaster#(srctype axiSlave)(PhysMemMaster#(addrWidth,dataWidth));\nendtypeclass\n\n"
  },
  {
    "path": "bsv/ConnectalMemUtils.bsv",
    "content": "// Copyright (c) 2013 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\n\n`include \"ConnectalProjectConfig.bsv\"\nimport BRAM::*;\nimport BRAMFIFO::*;\nimport FIFO::*;\nimport Vector::*;\nimport Gearbox::*;\nimport FIFOF::*;\nimport SpecialFIFOs::*;\nimport GetPut::*;\n\nimport ConnectalConfig::*;\nimport ConnectalMemTypes::*;\nimport ConfigCounter::*;\nimport BRAMFIFOFLevel::*;\n\ninterface MemReader#(numeric type dataWidth);\n   interface MemReadServer #(dataWidth) readServer;\n   interface MemReadClient#(dataWidth) readClient;\nendinterface\n\nmodule mkMemReader(MemReader#(dataWidth))\n   provisos(Div#(dataWidth,8,dataWidthBytes),\n\t    Mul#(dataWidthBytes,8,dataWidth),\n\t    Log#(dataWidthBytes,beatShift));\n\n   FIFOF#(MemData#(dataWidth)) readBuffer <- mkFIFOF;\n   FIFOF#(MemRequest)           reqBuffer <- mkFIFOF;\n\n   interface MemReadServer readServer;\n      interface Put readReq = toPut(reqBuffer);\n      interface Get readData = toGet(readBuffer);\n   endinterface\n   interface MemReadClient readClient;\n      interface Get readReq = toGet(reqBuffer);\n      interface Put readData = toPut(readBuffer);\n   endinterface\nendmodule\n\ninterface MemReaderBuff#(numeric type dataWidth, numeric type bufferDepth);\n   interface MemReadServer #(dataWidth) readServer;\n   interface MemReadClient#(dataWidth) readClient;\nendinterface\n\nmodule mkMemReaderBuff(MemReaderBuff#(dataWidth, bufferDepth))\n   provisos(Div#(dataWidth,8,dataWidthBytes)\n\t    ,Mul#(dataWidthBytes,8,dataWidth)\n\t    ,Log#(dataWidthBytes,beatShift)\n\t    ,Log#(bufferDepth,bufferDepthWidth)\n\t    ,Max#(TAdd#(bufferDepthWidth,1),BurstLenSize,availableWidth)\n\t    ,Add#(a__,BurstLenSize,availableWidth)\n\t    );\n\n   FIFOF#(MemData#(dataWidth))   readBuffer <- mkSizedBRAMFIFOF(valueOf(bufferDepth));\n   FIFOF#(MemRequest)        reqOutstanding <- mkFIFOF();\n   FIFOF#(MemRequest)          reqCommitted <- mkFIFOF();\n   ConfigCounter#(availableWidth) unfulfilled <- mkConfigCounter(0);\n   let beat_shift = fromInteger(valueOf(beatShift));\n   \n   // only issue the readRequest when sufficient buffering is available.  This includes the bufering we have already comitted.\n   rule commitReq if (unpack(extend(reqOutstanding.first.burstLen>>beat_shift)) + unfulfilled.read() < fromInteger(valueOf(bufferDepth)));\n      let req <- toGet(reqOutstanding).get();\n      unfulfilled.increment(unpack(extend(req.burstLen>>beat_shift)));\n      reqCommitted.enq(req);\n   endrule\n\n   interface MemReadServer readServer;\n      interface Put readReq = toPut(reqOutstanding);\n      interface Get readData;\n\t method ActionValue#(MemData#(dataWidth)) get();\n\t    let v <- toGet(readBuffer).get();\n\t    unfulfilled.decrement(1);\n\t    return v;\n\t endmethod\n      endinterface: readData\n   endinterface\n   interface MemReadClient readClient;\n      interface Get readReq = toGet(reqCommitted);\n      interface Put readData;\n   \t method Action put(MemData#(dataWidth) x);\n\t    readBuffer.enq(x);\n   \t endmethod\n      endinterface\n   endinterface\nendmodule\n\n\ninterface MemWriter#(numeric type dataWidth);\n   interface MemWriteServer#(dataWidth) writeServer;\n   interface MemWriteClient#(dataWidth) writeClient;\nendinterface\n\n\nmodule mkMemWriter(MemWriter#(dataWidth))\n   provisos(Div#(dataWidth,8,dataWidthBytes),\n\t    Mul#(dataWidthBytes,8,dataWidth),\n\t    Log#(dataWidthBytes,beatShift));\n\n   FIFOF#(MemData#(dataWidth)) writeBuffer <- mkFIFOF;\n   FIFOF#(MemRequest)       reqOutstanding <- mkFIFOF;\n   FIFOF#(Bit#(MemTagSize))       doneTags <- mkFIFOF();\n\n   interface MemWriteServer writeServer;\n      interface Put writeReq = toPut(reqOutstanding);\n      interface Put writeData = toPut(writeBuffer);\n      interface Get writeDone = toGet(doneTags);\n   endinterface\n   interface MemWriteClient writeClient;\n      interface Get writeReq = toGet(reqOutstanding);\n      interface Get writeData = toGet(writeBuffer);\n      interface Put writeDone = toPut(doneTags);\n   endinterface\n\nendmodule\n\n\ninterface MemWriterBuff#(numeric type dataWidth, numeric type bufferDepth);\n   interface MemWriteServer#(dataWidth) writeServer;\n   interface MemWriteClient#(dataWidth) writeClient;\nendinterface\n\nmodule mkMemWriterBuff(MemWriterBuff#(dataWidth, bufferDepth))\n   provisos(Log#(bufferDepth,bufferDepthWidth),\n\t    Max#(TAdd#(bufferDepthWidth,1),BurstLenSize,availableWidth),\n\t    Add#(a__,BurstLenSize,availableWidth),\n\t    Div#(dataWidth,8,dataWidthBytes),\n\t    Mul#(dataWidthBytes,8,dataWidth),\n\t    Log#(dataWidthBytes,beatShift));\n\n   FIFOF#(MemData#(dataWidth))  writeBuffer <- mkSizedBRAMFIFOF(valueOf(bufferDepth));\n   FIFOF#(MemRequest)        reqOutstanding <- mkFIFOF();\n   FIFOF#(MemRequest)          reqCommitted <- mkFIFOF();\n   FIFOF#(Bit#(MemTagSize))        doneTags <- mkFIFOF();\n   ConfigCounter#(availableWidth) available <- mkConfigCounter(0);\n   let beat_shift = fromInteger(valueOf(beatShift));\n   \n   // only issue the writeRequest when sufficient data is available.  This includes the data we have already comitted.\n   rule commitReq if (unpack(extend(reqOutstanding.first.burstLen>>beat_shift)) <= available.read());\n      let req <- toGet(reqOutstanding).get();\n      available.decrement(unpack(extend(req.burstLen>>beat_shift)));\n      reqCommitted.enq(req);\n   endrule\n\n   interface MemWriteServer writeServer;\n      interface Put writeReq = toPut(reqOutstanding);\n      interface Put writeData;\n\t method Action put(MemData#(dataWidth) d);\n\t    writeBuffer.enq(d);\n\t    available.increment(1);\n\t endmethod\n      endinterface: writeData\n      interface Get writeDone = toGet(doneTags);\n   endinterface\n   interface MemWriteClient writeClient;\n      interface Get writeReq = toGet(reqCommitted);\n      interface Get writeData;\n\t method ActionValue#(MemData#(dataWidth)) get();\n\t    writeBuffer.deq;\n\t    return writeBuffer.first;\n\t endmethod\n      endinterface\n      interface Put writeDone = toPut(doneTags);\n   endinterface\nendmodule\n\ninterface UGBramFifos#(numeric type numFifos, numeric type fifoDepth, type a);\n   method Action enq(Bit#(TLog#(numFifos)) idx, a v);\n   method Action first_req(Bit#(TLog#(numFifos)) idx);\n   method ActionValue#(a) first_resp();\n   method Action deq(Bit#(TLog#(numFifos)) idx);\n   method Action upd_head(Bit#(TLog#(numFifos)) idx, a v);\nendinterface\n\n\nmodule mkUGBramFifos(UGBramFifos#(numFifos,fifoDepth,a))\n   provisos(Mul#(fifoDepth,numFifos,buffSz),\n\t    Log#(buffSz, buffAddrSz),\n\t    Add#(a__, TLog#(numFifos), TAdd#(1, buffAddrSz)),\n\t    Bits#(a,b__));\n   \n   function Bit#(buffAddrSz) hf(Integer i) = fromInteger(i*valueOf(fifoDepth));\n   Vector#(numFifos, Reg#(Bit#(buffAddrSz))) head <- mapM(mkReg, genWith(hf));\n   Vector#(numFifos, Reg#(Bit#(buffAddrSz))) tail <- mapM(mkReg, genWith(hf));\n   BRAM2Port#(Bit#(buffAddrSz),a)    buff <- mkBRAM2Server(defaultValue);\n   let fifo_depth = fromInteger(valueOf(fifoDepth));\n      \n   method Action enq(Bit#(TLog#(numFifos)) idx, a v);\n      buff.portB.request.put(BRAMRequest{write:True, responseOnWrite:False, address:tail[idx], datain:v});\n      Bit#(TAdd#(1,buffAddrSz)) nt = extend(tail[idx])+1;\n      Bit#(TAdd#(1,buffAddrSz)) li = (extend(idx)+1)*fifo_depth;\n      Bit#(TAdd#(1,buffAddrSz)) rs = (extend(idx)+0)*fifo_depth;\n      if (nt >= li) \n\t nt = rs;\n      tail[idx] <= truncate(nt);\n   endmethod\n\n   method Action first_req(Bit#(TLog#(numFifos)) idx);\n      buff.portA.request.put(BRAMRequest{write:False, responseOnWrite:False, address:head[idx], datain:?});\n   endmethod\n   \n   method ActionValue#(a) first_resp();\n      let v <- buff.portA.response.get;\n      return v;\n   endmethod\n\n   method Action deq(Bit#(TLog#(numFifos)) idx);\n      Bit#(TAdd#(1,buffAddrSz)) nt = extend(head[idx])+1;\n      Bit#(TAdd#(1,buffAddrSz)) li = (extend(idx)+1)*fifo_depth;\n      Bit#(TAdd#(1,buffAddrSz)) rs = (extend(idx)+0)*fifo_depth;\n      if (nt >= li) \n\t nt = rs;\n      head[idx] <= truncate(nt);\n   endmethod\n\n   method Action upd_head(Bit#(TLog#(numFifos)) idx, a v);\n      buff.portA.request.put(BRAMRequest{write:True, responseOnWrite:False, address:head[idx], datain:v});\n   endmethod\n\nendmodule\n\n`ifndef BYTE_ENABLES\nmodule mkMemServerFromPhysMemSlave#(PhysMemSlave#(addrWidth,dataWidth) ms)(MemServer#(dataWidth))\n   provisos (Add#(a__, addrWidth, MemOffsetSize));\n   interface MemReadServer readServer;\n      interface Put readReq;\n\t method Action put(MemRequest req);\n\t    ms.read_server.readReq.put(PhysMemRequest { addr: truncate(req.offset), burstLen: req.burstLen,\n`ifdef BYTE_ENABLES\n\t       firstbe: reqFirstByteEnable(req),\n\t       lastbe: reqLastByteEnable(req),\n`endif\n\t       tag: req.tag\n\t       });\n\t endmethod\n      endinterface\n      interface Get readData = ms.read_server.readData;\n   endinterface\n   interface MemWriteServer writeServer;\n      interface Put writeReq;\n\t method Action put(MemRequest req);\n\t    ms.write_server.writeReq.put(PhysMemRequest { addr: truncate(req.offset), burstLen: req.burstLen,\n`ifdef BYTE_ENABLES\n\t       firstbe: reqFirstByteEnable(req),\n\t       lastbe: reqLastByteEnable(req),\n`endif\n\t       tag: req.tag\n\t       });\n\t endmethod\n      endinterface\n      interface Put           writeData = ms.write_server.writeData;\n      interface Get           writeDone = ms.write_server.writeDone;\n   endinterface\nendmodule\n`endif // not BYTE_ENABLES\n"
  },
  {
    "path": "bsv/ConnectalMemory.bsv",
    "content": "// Copyright (c) 2013 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\nimport GetPut::*;\nimport Vector::*;\n\n//\n// Dma channel type\n//\ntypedef enum {\n   ChannelType_Read, ChannelType_Write\n   } ChannelType deriving (Bits,Eq,FShow);\n\n//\n// @brief Channel Identifier\n//\n//typedef Bit#(16) DmaChannelId;\n\ntypedef struct {\n   Bit#(32) x;\n   Bit#(32) y;\n   Bit#(32) z;\n   Bit#(32) w;\n   } DmaDbgRec deriving(Bits);\n\ntypedef enum {\n   DmaErrorNone,\n   DmaErrorSGLIdOutOfRange_r,\n   DmaErrorSGLIdOutOfRange_w,\n   DmaErrorMMUOutOfRange_r,\n   DmaErrorMMUOutOfRange_w,\n   DmaErrorOffsetOutOfRange,\n   DmaErrorSGLIdInvalid,\n   DmaErrorTileTagOutOfRange\n   } DmaErrorType deriving (Bits,Eq,FShow);\n\n//\n// @brief Events sent from a Dma engine\n//\ninterface MemServerIndication;\n   method Action addrResponse(Bit#(64) physAddr);\n   method Action reportStateDbg(DmaDbgRec rec);\n   method Action reportMemoryTraffic(Bit#(64) words);\n   method Action error(Bit#(32) code, Bit#(32) sglId, Bit#(64) offset, Bit#(64) extra);\nendinterface\n\n//\n// @brief Events sent from a MMU\n//\ninterface MMUIndication;\n   method Action idResponse(Bit#(32) sglId);\n   method Action configResp(Bit#(32) sglId);\n   method Action error(Bit#(32) code, Bit#(32) sglId, Bit#(64) offset, Bit#(64) extra);\nendinterface\n\ntypedef Bit#(32) SpecialTypeForSendingFd;\n//\n// @brief Configuration interface to an MMU\n//\ninterface MMURequest;\n   //\n   // @brief Adds an address translation entry to the scatter-gather list for an object\n   //\n   // @param sglId Specifies the object to be translated\n   // @param addr Physical address of the segment\n   // @param len Length of the segment\n   //\n   method Action sglist(Bit#(32) sglId, Bit#(32) sglIndex, Bit#(64) addr,  Bit#(32) len);\n   method Action region(Bit#(32) sglId, Bit#(64) barr12, Bit#(32) index12, Bit#(64) barr8, Bit#(32) index8, Bit#(64) barr4, Bit#(32) index4, Bit#(64) barr0, Bit#(32) index0);\n   method Action idRequest(SpecialTypeForSendingFd fd);\n   method Action idReturn(Bit#(32) sglId);\n   method Action setInterface(Bit#(32) interfaceId, Bit#(32) sglId);\nendinterface\n\ntypedef enum {\n   Idle, Stopped, Running\n   } TileState deriving (Bits,Eq);\n\ntypedef struct {\n   Bit#(2) tile;\n   TileState state;\n   } TileControl deriving (Bits);\n\n//\n// @brief Control interface to Dma engine\n//\ninterface MemServerRequest;\n   // @brief Requests an address translation\n   //\n   method Action addrTrans(Bit#(32) sglId, Bit#(32) offset);\n\n   // @brief Changes tile status\n   //\n   method Action setTileState(TileControl tc);\n   //\n   // @brief Requests debug info for the specified channel type\n   //\n   method Action stateDbg(ChannelType rc);\n   method Action memoryTraffic(ChannelType rc);\nendinterface\n"
  },
  {
    "path": "bsv/ConnectalMimo.bsv",
    "content": "////////////////////////////////////////////////////////////////////////////////\n// Copyright (c) 2012  Bluespec, Inc.  ALL RIGHTS RESERVED.\n// $Revision: 32844 $\n// $Date: 2013-12-16 16:39:44 +0000 (Mon, 16 Dec 2013) $\n////////////////////////////////////////////////////////////////////////////////\n//  Filename      : MIMO.bsv\n//  Description   : Multiple-In Multiple-Out\n////////////////////////////////////////////////////////////////////////////////\npackage ConnectalMimo;\n\n// Notes :\n// - This module works like a FIFO, but for arbitrary amounts of the base object type.\n// - The clear method overrides the effects of enq and deq.\n\n////////////////////////////////////////////////////////////////////////////////\n/// Imports\n////////////////////////////////////////////////////////////////////////////////\nimport Vector            ::*;\nimport DefaultValue      ::*;\nimport BUtils            ::*;\nimport FIFO              ::*;\nimport FIFOF             ::*;\nimport BRAMFIFO          ::*;\nimport Counter           ::*;\nimport Clocks            ::*;\nimport MIMO              ::*;\n\nimport ConnectalBramFifo ::*;\n\n////////////////////////////////////////////////////////////////////////////////\n////////////////////////////////////////////////////////////////////////////////\n///\n/// Implementation of BRAM based version\n///\n////////////////////////////////////////////////////////////////////////////////\n////////////////////////////////////////////////////////////////////////////////\nmodule mkMIMOBram#(MIMOConfiguration cfg)(MIMO#(max_in, max_out, size, t))\n   provisos (  Bits#(t, st)               // object must have bit representation\n\t     , Add#(__f, 1, st)           // object is at least 1 byte in size\n\t     , Add#(2, __a, size)         // must have at least 2 elements of storage\n\t     , Add#(__b, max_in, size)    // the max enqueued amount must be less than or equal to the full storage\n\t     , Add#(__c, max_out, size)   // the max dequeued amount must be less than or equal to the full storage\n             , Mul#(st, size, total)      // total bits of storage\n             , Mul#(st, max_in, intot)    // total bits to be enqueued\n             , Mul#(st, max_out, outtot)  // total bits to be dequeued\n             , Add#(__d, outtot, total)   // make sure the number of dequeue bits is not larger than the total storage\n\t     , Max#(max_in, max_out, max) // calculate the max width of the memories\n\t     , Div#(size, max, em1)       // calculate the number of entries for each memory required\n\t     , Add#(em1, 1, e)\n\t     , Add#(__e, max_out, max)\n             );\n   \n   ////////////////////////////////////////////////////////////////////////////////\n   /// Design Elements\n   ////////////////////////////////////////////////////////////////////////////////\n   let clock <- exposeCurrentClock();\n   let reset <- exposeCurrentReset();\n   Vector#(max, FIFOF#(t))         vfStorage           <- replicateM(mkDualClockBramFIFOF(clock, reset, clock, reset));\n   Counter#(32)                    rDataCount          <- mkCounter(0);\n   \n   Reg#(LUInt#(max))               rWriteIndex         <- mkReg(0);\n   Reg#(LUInt#(max))               rReadIndex          <- mkReg(0);\n   \n   Vector#(max, RWire#(Bool))      vrwDeqFifo          <- replicateM(mkRWire);\n   Vector#(max, RWire#(t))         vrwEnqFifo          <- replicateM(mkRWire);\n \n   RWire#(LUInt#(size))            rwDeqCount          <- mkRWire;\n   RWire#(LUInt#(size))            rwEnqCount          <- mkRWire;\n   RWire#(Bit#(intot))             rwEnqData           <- mkRWire;\n   PulseWire                       pwClear             <- mkPulseWire;\n   \n   ////////////////////////////////////////////////////////////////////////////////\n   /// Functions\n   ////////////////////////////////////////////////////////////////////////////////\n   function t getFirst(FIFOF#(t) ifc);\n      return ifc.first();\n   endfunction\n\n   function Action doEnq(Bool doit, FIFOF#(t) ifc, t datain);\n      action\n\t if (doit) ifc.enq(datain);\n      endaction\n   endfunction\n\n   function Action doDeq(Bool doit, FIFOF#(t) ifc);\n      action\n\t if (doit) ifc.deq();\n      endaction\n   endfunction\n   \n   function Vector#(max, Bool) createMask(LUInt#(max) count);\n      Bit#(max) v = (1 << count) - 1;\n      return unpack(v);\n   endfunction\n   \n   function Vector#(v, el) rotateRBy(Vector#(v, el) vect, UInt#(logv) n)\n      provisos(Log#(v, logv));\n      return reverse(rotateBy(reverse(vect), n));\n   endfunction\n   \n   ////////////////////////////////////////////////////////////////////////////////\n   /// Rules\n   ////////////////////////////////////////////////////////////////////////////////\n   Rules d = \n   rules\n      (* aggressive_implicit_conditions *)\n      rule dequeue if (rwDeqCount.wget matches tagged Valid .dcount);\n\t Vector#(max, Bool) deqDoIt = rotateBy(createMask(cExtend(dcount)), cExtend(rReadIndex));\n\t for(Integer i = 0; i < valueOf(max); i = i + 1) begin\n\t    if (deqDoIt[i]) vrwDeqFifo[i].wset(True);\n\t end\n\t \n\t rDataCount.dec(cExtend(dcount));\n\t \n\t UInt#(32) ridx = cExtend(rReadIndex);\n\t UInt#(32) dcnt = cExtend(dcount);\n\t if ((ridx + dcnt) >= fromInteger(valueOf(max))) \n\t    rReadIndex <= rReadIndex - fromInteger(valueOf(max)) + cExtend(dcount);\n\t else\n\t    rReadIndex <= rReadIndex + cExtend(dcount);\n      endrule\n      \n      (* aggressive_implicit_conditions *)\n      rule enqueue if (rwEnqCount.wget matches tagged Valid .ecount &&& \n\t\t      rwEnqData.wget matches tagged Valid .edata\n\t\t      );\n\t Vector#(max, t)    enqData = rotateBy(unpack(cExtend(edata)), cExtend(rWriteIndex));\n\t Vector#(max, Bool) enqDoIt = rotateBy(createMask(cExtend(ecount)), cExtend(rWriteIndex));\n\t \n\t for(Integer i = 0; i < valueOf(max); i = i + 1) begin\n\t    if (enqDoIt[i]) vrwEnqFifo[i].wset(enqData[i]);\n\t end\n\t \n\t rDataCount.inc(cExtend(ecount));\n\t \n\t UInt#(32) widx = cExtend(rWriteIndex);\n\t UInt#(32) ecnt = cExtend(ecount);\n\t if ((widx + ecnt) >= fromInteger(valueOf(max))) \n\t    rWriteIndex <= rWriteIndex - fromInteger(valueOf(max)) + cExtend(ecount);\n\t else\n\t    rWriteIndex <= rWriteIndex + cExtend(ecount);\n      endrule\n   endrules;\n\n   Rules re = emptyRules;\n   for(Integer i = 0; i < valueOf(max); i = i + 1) begin\n      re = rJoinConflictFree(re, \n\t rules\n\t    rule enqueue_fifo if (vrwEnqFifo[i].wget matches tagged Valid .enqdata);\n\t       vfStorage[i].enq(enqdata);\n\t    endrule\n\t endrules\n\t );\n   end\n   \n   Rules rd = emptyRules;\n   for(Integer i = 0; i < valueOf(max); i = i + 1) begin\n      rd = rJoinConflictFree(rd, \n\t rules\n\t    rule dequeue_fifo if (vrwDeqFifo[i].wget matches tagged Valid .*);\n\t       vfStorage[i].deq();\n\t    endrule\n\t endrules\n\t );\n   end\n   \n   Rules r = rJoinConflictFree(rd, re);\n   r = rJoin(d, r);\n   r = rJoinPreempts(\n\t\t     rules\n\t\t\t(* fire_when_enabled *)\n\t\t\trule clear if (pwClear);\n\t\t\t   function Action getClear(FIFOF#(t) ifc) = ifc.clear();\n\t\t\t   rDataCount.setF(0);\n\t\t\t   rWriteIndex <= 0;\n\t\t\t   rReadIndex <= 0;\n\t\t\t   joinActions(map(getClear, vfStorage));\n\t\t\tendrule\n\t\t     endrules, r);\n   \n   addRules(r);\n   \n   \n   ////////////////////////////////////////////////////////////////////////////////\n   /// Interface Connections / Methods\n   ////////////////////////////////////////////////////////////////////////////////\n   method Action enq(LUInt#(max_in) count, Vector#(max_in, t) data) if (cfg.unguarded || (rDataCount.value() < fromInteger(valueOf(size))));\n      rwEnqCount.wset(cExtend(count));\n      rwEnqData.wset(pack(data));\n   endmethod\n   \n   method Vector#(max_out, t) first() if (cfg.unguarded || (rDataCount.value() > 0));\n      Vector#(max, t) v = newVector;\n      for(Integer i = 0; i < valueOf(max); i = i + 1) begin\n\t if (vfStorage[i].notEmpty()) v[i] = vfStorage[i].first();\n\t else                         v[i] = ?;\n      end\n      return take(rotateRBy(v, cExtend(rReadIndex)));\n   endmethod\n      \n   method Action deq(LUInt#(max_out) count) if (cfg.unguarded || (rDataCount.value() > 0));\n      LUInt#(size) szcount = cExtend(count);\n      rwDeqCount.wset(szcount);\n   endmethod\n         \n   method Bool enqReady();\n      return rDataCount.value < fromInteger(valueOf(size));\n   endmethod\n   \n   method Bool enqReadyN(LUInt#(max_in) count);\n      return (rDataCount.value() + cExtend(count)) <= fromInteger(valueOf(size));\n   endmethod\n      \n   method Bool deqReady();\n      return rDataCount.value() > 0;\n   endmethod\n   \n   method Bool deqReadyN(LUInt#(max_out) count);\n      return rDataCount.value() >= cExtend(count);\n   endmethod\n   \n   method LUInt#(size) count();\n      return cExtend(rDataCount.value());\n   endmethod\n   \n   method Action clear();\n      pwClear.send();\n   endmethod\nendmodule: mkMIMOBram\nendpackage: ConnectalMimo\n\n"
  },
  {
    "path": "bsv/ConnectalPrelude.bsv",
    "content": "// Copyright (c) 2015 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\n\ntypedef struct {\n   t1 tpl_1;\n   t2 tpl_2;\n   } Tuple2#(type t1, type t2);\n\ntypedef struct {\n   t1 tpl_1;\n   t2 tpl_2;\n   t3 tpl_3;\n   } Tuple3#(type t1, type t2, type t3);\n\ntypedef struct {\n   t1 tpl_1;\n   t2 tpl_2;\n   t3 tpl_3;\n   t4 tpl_4;\n   } Tuple4#(type t1, type t2, type t3, type t4);\n\ntypedef struct {\n   t1 tpl_1;\n   t2 tpl_2;\n   t3 tpl_3;\n   t4 tpl_4;\n   t5 tpl_5;\n   } Tuple5#(type t1, type t2, type t3, type t4, type t5);\n\n"
  },
  {
    "path": "bsv/ConnectalXilinxCells.bsv",
    "content": "\n// Copyright (c) 2013 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\nimport Clocks       :: *;\nimport DefaultValue :: *;\nimport XilinxCells  :: *;\nimport Vector       :: *;\n\n`include \"ConnectalProjectConfig.bsv\"\n\n// interface ResetIBUF;\n//    interface Reset reset;\n// endinterface\n\nimport \"BVI\" IBUF =\nmodule mkResetIBUF#(Reset inReset)(ResetGenIfc);// provisos(Bits#(one_bit,1));\n   // default_clock clk();\n   // default_reset rstn();\n   default_clock no_clock;\n   // default_reset no_reset;\n   input_reset inReset(I) = inReset;\n   output_reset gen_rst(O) clocked_by(no_clock);\n\n   // port I = i;\n   // method O    _read;\n\n   // path(I, O);\n   // // path(IB, O);\n\n   // schedule _read  CF _read;\n\nendmodule: mkResetIBUF\n\n\n\nimport \"BVI\" IBUFDS =\nmodule mkIBUFDS#(Wire#(one_bit) i, Wire#(one_bit) ib)(ReadOnly#(one_bit)) provisos(Bits#(one_bit,1));\n   default_clock clk();\n   default_reset rstn();\n\n   parameter CAPACITANCE = \"DONT_CARE\";\n   parameter DIFF_TERM = 1;\n   parameter IBUF_DELAY_VALUE = 0;\n   parameter IFD_DELAY_VALUE = \"AUTO\";\n   parameter IOSTANDARD = \"DEFAULT\";\n\n   port I = i;\n   port IB = ib;\n   method O    _read;\n\n   path(I, O);\n   path(IB, O);\n\n   schedule _read  CF _read;\n\nendmodule: mkIBUFDS\n\nimport \"BVI\" IBUFDS =\nmodule vMkConnectalClockIBUFDS#(Wire#(one_bit) i, Wire#(one_bit) ib)(ClockGenIfc) provisos(Bits#(one_bit,1));\n   default_clock clk();\n   default_reset rstn();\n   parameter CAPACITANCE = \"DONT_CARE\";\n   parameter DIFF_TERM = 1;\n   parameter IBUF_DELAY_VALUE = 0;\n   parameter IFD_DELAY_VALUE = \"AUTO\";\n   parameter IOSTANDARD = \"DEFAULT\";\n   port I = i;\n   port IB = ib;\n   //method O    _read;\n   output_clock gen_clk(O);\n   path(I, O);\n   path(IB, O);\n   //schedule _read  CF _read;\nendmodule: vMkConnectalClockIBUFDS\n\nmodule mkConnectalClockIBUFDS#(Wire#(one_bit) i, Wire#(one_bit) ib)(Clock) provisos(Bits#(one_bit,1));\n   let _m <- vMkConnectalClockIBUFDS(i, ib);\n   return _m.gen_clk;\nendmodule: mkConnectalClockIBUFDS\n\ninterface DiffPair;\n   method Bit#(1) p;\n   method Bit#(1) n;\nendinterface\n\nimport \"BVI\" OBUFDS =\nmodule vMkOBUFDS#(Bit#(1) i)(DiffPair);\n   default_clock clk();\n   default_reset reset();\n\n   port I = i;\n\n   method O p;\n   method OB n;\n\n   path(I, O);\n   path(I, OB);\n\n   schedule (p, n) CF (p, n);\n\nendmodule: vMkOBUFDS\n\nmodule mkOBUFDS#(Bit#(1) i)(DiffPair);\n   let _m <- vMkOBUFDS(i);\n   return _m;\nendmodule: mkOBUFDS\n\nimport \"BVI\" IBUFDS_GTE2 =\nmodule vMkConnectalClockIBUFDS_GTE2#(Bool enable, Wire#(one_bit) i, Wire#(one_bit) ib)(ClockGenIfc) provisos(Bits#(one_bit,1));\n   default_clock clk();\n   default_reset rstn();\n   port CEB = pack(!enable);\n   port I = i;\n   port IB = ib;\n   //method O    _read;\n   output_clock gen_clk(O);\n   //output_clock gen_clk2(ODIV2);\n   path(I, O);\n   path(IB, O);\n   //path(I, ODIV2);\n   //path(IB, ODIV2);\nendmodule: vMkConnectalClockIBUFDS_GTE2\n\nmodule mkConnectalClockIBUFDS_GTE2#(Bool enable, Wire#(one_bit) i, Wire#(one_bit) ib)(Clock) provisos(Bits#(one_bit,1));\n   let _m <- vMkConnectalClockIBUFDS_GTE2(enable, i, ib);\n   return _m.gen_clk;\nendmodule: mkConnectalClockIBUFDS_GTE2\n\ninterface GTE2ClockGenIfc;\n   interface Clock gen_clk;\n   interface Clock gen_clk2;\nendinterface\n\nimport \"BVI\" IBUFDS_GTE2 =\nmodule vMkClockIBUFDS_GTE2#(IBUFDS_GTE2Params params, Bool enable, Clock clk_p, Clock clk_n)(GTE2ClockGenIfc);\n   default_clock no_clock;\n   default_reset no_reset;\n\n   input_clock clk_p(I)  = clk_p;\n   input_clock clk_n(IB) = clk_n;\n\n   port CEB = pack(!enable);\n\n   output_clock gen_clk(O);\n   output_clock gen_clk2(ODIV2);\n\n   parameter CLKCM_CFG      = params.clkcm_cfg;\n   parameter CLKRCV_TRST    = params.clkrcv_trst;\n   parameter CLKSWING_CFG   = (Bit#(2))'(params.clkswing_cfg);\n\n   path(I,  O);\n   path(IB, O);\n   path(I,  ODIV2);\n   path(IB, ODIV2);\n\n   same_family(clk_p, gen_clk);\nendmodule: vMkClockIBUFDS_GTE2\n\nimport \"BVI\" IBUFDS_GTE3 =\nmodule vMkClockIBUFDS_GTE3#(IBUFDS_GTE2Params params, Bool enable, Clock clk_p, Clock clk_n)(GTE2ClockGenIfc);\n   default_clock no_clock;\n   default_reset no_reset;\n\n   parameter REFCLK_HROW_CK_SEL = 0; // choose ODIV2 output same as O\n\n   input_clock clk_p(I)  = clk_p;\n   input_clock clk_n(IB) = clk_n;\n\n   port CEB = pack(!enable);\n\n   output_clock gen_clk(O);\n   output_clock gen_clk2(ODIV2);\n\n   path(I,  O);\n   path(IB, O);\n   path(I,  ODIV2);\n   path(IB, ODIV2);\n\n   same_family(clk_p, gen_clk);\n   same_family(clk_p, gen_clk2);\nendmodule: vMkClockIBUFDS_GTE3\n\n\nimport \"BVI\" IBUFDS_GTE4 =\nmodule vMkClockIBUFDS_GTE4#(IBUFDS_GTE2Params params, Bool enable, Clock clk_p, Clock clk_n)(GTE2ClockGenIfc);\n   default_clock no_clock;\n   default_reset no_reset;\n\n   parameter REFCLK_HROW_CK_SEL = 0; // choose ODIV2 output same as O\n\n   input_clock clk_p(I)  = clk_p;\n   input_clock clk_n(IB) = clk_n;\n\n   port CEB = pack(!enable);\n\n   output_clock gen_clk(O);\n   output_clock gen_clk2(ODIV2);\n\n   path(I,  O);\n   path(IB, O);\n   path(I,  ODIV2);\n   path(IB, ODIV2);\n\n   same_family(clk_p, gen_clk);\n   same_family(clk_p, gen_clk2);\nendmodule: vMkClockIBUFDS_GTE4\n\nmodule mkClockIBUFDS_GTE#(IBUFDS_GTE2Params params, Bool enable, Clock clk_p, Clock clk_n)(GTE2ClockGenIfc);\n`ifdef XilinxUltrascalePlus\n   let _m <- vMkClockIBUFDS_GTE4(params, enable, clk_p, clk_n);\n`else\n  `ifdef XilinxUltrascale\n   let _m <- vMkClockIBUFDS_GTE3(params, enable, clk_p, clk_n);\n  `else\n   let _m <- vMkClockIBUFDS_GTE2(params, enable, clk_p, clk_n);\n  `endif\n`endif\n   return _m;\nendmodule: mkClockIBUFDS_GTE\n\n\nimport \"BVI\" OBUFT =\nmodule mkOBUFT#(ReadOnly#(one_bit) i, ReadOnly#(oneb_bit) t)(ReadOnly#(onec_bit)) provisos(Bits#(one_bit,1), Bits#(oneb_bit,1), Bits#(onec_bit,1));\n   default_clock clk();\n   default_reset rstn();\n\n   port I = i;\n   port T = t;\n   method O    _read;\n\n   path(I, O);\n   path(T, O);\n\n   schedule _read  CF _read;\n\nendmodule: mkOBUFT\n\ntypedef struct {\n   String cinvctrl_sel;           // \"TRUE\" to enable dynamic clock inversion, \"FALSE\" otherwise\n   String delay_src;              // \"IDATAIN\" or \"DATAIN\"\n   String high_performance_mode;  // \"TRUE\" to reduce jitter, \"FALSE\" to reduce power\n   String idelay_type;            // \"FIXED\", \"VAR_LOAD\", or \"VAR_LOAD_PIPE\"\n   Integer idelay_value;          // 0-31 input delay tap setting\n   String pipe_sel;               // \"TRUE\" to select pipelined mode\n   Integer refclk_frequency;      // idelayctrl clock input freq in MHz\n   String signal_pattern;         // \"DATA\" or \"CLOCK\" input signal\n}  IDELAYE2_Config;\n\ninstance DefaultValue#(IDELAYE2_Config);\n   defaultValue =\n   IDELAYE2_Config {\n      cinvctrl_sel: \"FALSE\",\n      delay_src: \"IDATAIN\",\n      high_performance_mode: \"FALSE\",\n      idelay_type: \"FIXED\",\n      idelay_value: 0,\n      pipe_sel: \"FALSE\",\n      refclk_frequency: 200,\n      signal_pattern: \"DATA\"\n      };\nendinstance\n\n(* always_ready, always_enabled *)\ninterface IdelayE2;\n   method Bit#(5) cntvalueout();\n   method Action cinvctrl(Bit#(1) v);\n   method Action cntvaluein(Bit#(5) v);\n   method Action ld(Bit#(1) v);\n   method Action ldpipeen(Bit#(1) v);\n   method Action inc(Bool inc);\n   method Action ce(Bit#(1) v);\n   method Action datain(Bit#(1) v);\n   method Action idatain(Bit#(1) v);\n   method Action reset(Bit#(1) v);\n   method Bit#(1) dataout();\nendinterface\n\nimport \"BVI\" IDELAYE2 =\nmodule mkIDELAYE2#(IDELAYE2_Config cfg, Clock serdes_clock)(IdelayE2);\n   default_clock clk(C);\n   //default_reset rst(REGRST);\n   no_reset;\n   input_clock serdes ()= serdes_clock;\n\n   parameter CINVCTRL_SEL = cfg.cinvctrl_sel;\n   parameter DELAY_SRC = cfg.delay_src;\n   parameter HIGH_PERFORMANCE_MODE = cfg.high_performance_mode;\n   parameter IDELAY_TYPE = cfg.idelay_type;\n   parameter IDELAY_VALUE = cfg.idelay_value;\n   parameter PIPE_SEL = cfg.pipe_sel;\n   parameter REFCLK_FREQUENCY = cfg.refclk_frequency;\n   parameter SIGNAL_PATTERN = cfg.signal_pattern;\n\n   method CNTVALUEOUT cntvalueout();\n   method cinvctrl(CINVCTRL) enable((*inhigh*) en0);\n   method cntvaluein(CNTVALUEIN) enable((*inhigh*) en1);\n\n   method ld(LD) enable((*inhigh*) en20);\n\n   // is LDPIPEEN the enable for DATAIN?\n   method ldpipeen(LDPIPEEN) enable((*inhigh*) en21);\n\n   method DATAOUT dataout();\n   method inc(INC) enable((*inhigh*) en5);\n   method ce(CE) enable((*inhigh*) en4);\n   method reset(REGRST) enable((*inhigh*) en7);\n   method datain(DATAIN) enable((*inhigh*) en2);\n   method idatain(IDATAIN) enable((*inhigh*) en3) clocked_by(serdes);\n\n   schedule (datain, idatain, inc, ce) CF (datain, idatain, inc, ce);\n   schedule (reset, cntvalueout, dataout, ld, datain, ldpipeen, inc, cinvctrl, cntvaluein, ce, idatain) CF (reset, cntvalueout, dataout, ld, datain, ldpipeen, inc, cinvctrl, cntvaluein, ce, idatain);\nendmodule\n\n////////////////////////////////////////////////////////////\ntypedef struct {\n   String data_rate;\n   Integer data_width;\n   String dyn_clk_inv_en;\n   String dyn_clkdiv_inv_en;\n   Integer init_q1;\n   Integer init_q2;\n   Integer init_q3;\n   Integer init_q4;\n   String interface_type;\n   String iobdelay;\n   Integer num_ce;\n   String ofb_used;\n   String serdes_mode;\n   Integer srval_q1;\n   Integer srval_q2;\n   Integer srval_q3;\n   Integer srval_q4;\n}  ISERDESE2_Config;\n\ninstance DefaultValue#(ISERDESE2_Config);\n   defaultValue =\n   ISERDESE2_Config {\n      data_rate: \"DDR\",\n      data_width: 8,\n      dyn_clk_inv_en: \"FALSE\",\n      dyn_clkdiv_inv_en: \"FALSE\",\n      init_q1: 0,\n      init_q2: 0,\n      init_q3: 0,\n      init_q4: 0,\n      interface_type: \"NETWORKING\",\n      iobdelay: \"IBUF\",\n      num_ce: 1,\n      ofb_used: \"FALSE\",\n      serdes_mode: \"MASTER\",\n      srval_q1: 0,\n      srval_q2: 0,\n      srval_q3: 0,\n      srval_q4: 0\n      };\nendinstance\n\n(* always_ready, always_enabled *)\ninterface IserdesE2;\n   (* prefix = \"\" *)\n   method Action d(Bit#(1) d);\n   method Bit#(1) o();\n   method Action bitslip(Bit#(1) bitslip);\n   method Action ce1(Bit#(1) ce1);\n   method Action ce2(Bit#(1) ce2);\n   method Action ddly(Bit#(1) ddly);\n   method Action shiftin1(Bit#(1) shiftin1);\n   method Action shiftin2(Bit#(1) shiftin2);\n   method Bit#(1) q1();\n   method Bit#(1) q2();\n   method Bit#(1) q3();\n   method Bit#(1) q4();\n   method Bit#(1) q5();\n   method Bit#(1) q6();\n   method Bit#(1) q7();\n   method Bit#(1) q8();\n   method Bit#(1) shiftout1();\n   method Bit#(1) shiftout2();\n   method Action ofb(Bit#(1) ofb);\n   method Action dynclkdivsel(Bit#(1) dynclkdivsel);\n   method Action dynclksel(Bit#(1) dynclksel);\n   method Action oclk(Bit#(1) v);\n   method Action oclkb(Bit#(1) v);\n   method Action reset(Bit#(1) d);\nendinterface\n\nimport \"BVI\" ISERDESE2 =\nmodule mkISERDESE2#(ISERDESE2_Config cfg, Clock clk, Clock clkb)(IserdesE2);\n   input_clock clk(CLK) = clk;\n   input_clock clkb(CLKB) = clkb;\n   default_clock clkdiv(CLKDIV);\n   no_reset;\n\n   parameter DATA_RATE = cfg.data_rate;\n   parameter DATA_WIDTH = cfg.data_width;\n   parameter DYN_CLK_INV_EN = cfg.dyn_clk_inv_en;\n   parameter DYN_CLKDIV_INV_EN = cfg.dyn_clkdiv_inv_en;\n   parameter INIT_Q1 = cfg.init_q1;\n   parameter INIT_Q2 = cfg.init_q2;\n   parameter INIT_Q3 = cfg.init_q3;\n   parameter INIT_Q4 = cfg.init_q4;\n   parameter INTERFACE_TYPE = cfg.interface_type;\n   parameter IOBDELAY = cfg.iobdelay;\n   parameter NUM_CE = cfg.num_ce;\n   parameter OFB_USED = cfg.ofb_used;\n   parameter SERDES_MODE = cfg.serdes_mode;\n   parameter SRVAL_Q1 = cfg.srval_q1;\n   parameter SRVAL_Q2 = cfg.srval_q2;\n   parameter SRVAL_Q3 = cfg.srval_q3;\n   parameter SRVAL_Q4 = cfg.srval_q4;\n\n   port CLKDIVP = 0; // unused\n   path (D, O);\n\n   method d(D) enable ((*inhigh*) en0);\n   method O o();\n   method bitslip(BITSLIP) enable ((*inhigh*)enbitslip);\n   method ce1(CE1) enable ((*inhigh*) en1);\n   method ce2(CE2) enable ((*inhigh*) en2);\n   method ddly(DDLY) enable ((*inhigh*) en3);\n   method shiftin1(SHIFTIN1) enable ((*inhigh*) en4);\n   method shiftin2(SHIFTIN2) enable ((*inhigh*) en5);\n   method Q1 q1();\n   method Q2 q2();\n   method Q3 q3();\n   method Q4 q4();\n   method Q5 q5();\n   method Q6 q6();\n   method Q7 q7();\n   method Q8 q8();\n   method SHIFTOUT1 shiftout1();\n   method SHIFTOUT2 shiftout2();\n   method ofb(OFB) enable ((*inhigh*) en6);\n   method oclk(OCLK) enable ((*inhigh*) en10);\n   method oclkb(OCLKB) enable ((*inhigh*) en11);\n   method dynclkdivsel(DYNCLKDIVSEL) enable ((*inhigh*) en7);\n   method dynclksel(DYNCLKSEL) enable ((*inhigh*) en8);\n   method reset(RST) enable ((*inhigh*) en14);\n\n   schedule (reset, o, q1, q2, q3, q4, q5, q6, q7, q8, shiftout1, shiftout2, d, bitslip, ce1, ce2, ddly, shiftin1, shiftin2, ofb, dynclkdivsel, dynclksel, oclk, oclkb)\n         CF (reset, o, q1, q2, q3, q4, q5, q6, q7, q8, shiftout1, shiftout2, d, bitslip, ce1, ce2, ddly, shiftin1, shiftin2, ofb, dynclkdivsel, dynclksel, oclk, oclkb);\nendmodule\n\nimport \"BVI\" BUFR =\nmodule mkBUFR5#(Clock clk)(ClockGenIfc);\n   default_clock clkunused();\n   default_reset rstn();\n  \n   parameter BUFR_DIVIDE = \"5\";\n  \n   input_clock clk(I) = clk;\n   output_clock gen_clk(O);\n   port   CE = True;\n   port   CLR = False;\n   path(I, O);\nendmodule\n\nimport \"BVI\" BUFIO =\nmodule mkBUFIO#(Clock clk)(ClockGenIfc);\n   default_clock clkunused();\n   default_reset rstn();\n   input_clock clk(I) = clk;\n   output_clock gen_clk(O);\n   path(I, O);\nendmodule\n\n(* always_ready, always_enabled *)\ninterface ConnectalODDR#(type a);\n   method    a            q();\n   method    Action       s(Bool i);\n   method    Action       ce(Bool i);\n   method    Action       d1(a i);\n   method    Action       d2(a i);\nendinterface: ConnectalODDR\n\nimport \"BVI\" ODDR =\nmodule mkConnectalODDR#(ODDRParams#(a) params)(ConnectalODDR#(a))\n   provisos(Bits#(a, 1), DefaultValue#(a));\n\n   if (params.srtype != \"SYNC\" &&\n       params.srtype != \"ASYNC\")\n      error(\"There are only two modes of reset of the ODDR cell SYNC and ASYNC.  Please specify one of those.\");\n\n   if (params.ddr_clk_edge != \"OPPOSITE_EDGE\" &&\n       params.ddr_clk_edge != \"SAME_EDGE\")\n      error(\"There are only two modes of operation of the ODDR cell OPPOSITE_EDGE and SAME_EDGE.  Please specify one of those.\");\n\n   no_reset;\n   default_clock clk(C);\n   //default_reset rst(R);\n   port R = 0;\n\n   parameter DDR_CLK_EDGE = params.ddr_clk_edge;\n   parameter INIT         = pack(params.init);\n   parameter SRTYPE       = params.srtype;\n\n   method Q   q reset_by(no_reset);\n   method     s(S)     enable((*inhigh*)en0) reset_by(no_reset);\n   method     ce(CE)   enable((*inhigh*)en1) reset_by(no_reset);\n   method     d1(D1)   enable((*inhigh*)en2) reset_by(no_reset);\n   method     d2(D2)   enable((*inhigh*)en3) reset_by(no_reset);\n\n   schedule (q)      SB (d1, d2);\n   schedule (d1)     CF (d2);\n   schedule (d1)     C  (d1);\n   schedule (d2)     C  (d2);\n   schedule (q)      CF (q);\n   schedule (ce, s)  CF (ce, s);\n   schedule (ce, s)  SB (d1, d2, q);\nendmodule: mkConnectalODDR\n\n////////////////////////////////////////////////////////////////////////////////\n/// ClockGenerator Xilinx 7 Adv\n////////////////////////////////////////////////////////////////////////////////\ntypedef struct {\n   String      bandwidth;\n   String      compensation;\n   Bool        clkin_buffer;\n   Real        clkin1_period;\n   Real        clkin2_period;\n   Integer     reset_stages;\n   Real        clkfbout_mult_f;\n   Real        clkfbout_phase;\n   Integer     divclk_divide;\n   Bool        clkout0_buffer;\n   Bool        clkout0n_buffer;\n   Real        clkout0_divide_f;\n   Real        clkout0_duty_cycle;\n   Real        clkout0_phase;\n   Bool        clkout1_buffer;\n   Bool        clkout1n_buffer;\n   Integer     clkout1_divide;\n   Real        clkout1_duty_cycle;\n   Real        clkout1_phase;\n   Bool        clkout2_buffer;\n   Bool        clkout2n_buffer;\n   Integer     clkout2_divide;\n   Real        clkout2_duty_cycle;\n   Real        clkout2_phase;\n   Bool        clkout3_buffer;\n   Bool        clkout3n_buffer;\n   Integer     clkout3_divide;\n   Real        clkout3_duty_cycle;\n   Real        clkout3_phase;\n   Bool        clkout4_buffer;\n   Integer     clkout4_divide;\n   Real        clkout4_duty_cycle;\n   Real        clkout4_phase;\n   Bool        clkout5_buffer;\n   Integer     clkout5_divide;\n   Real        clkout5_duty_cycle;\n   Real        clkout5_phase;\n   Bool        clkout6_buffer;\n   Integer     clkout6_divide;\n   Real        clkout6_duty_cycle;\n   Real        clkout6_phase;\n   Real        ref_jitter1;\n   Real        ref_jitter2;\n   Bool        use_same_family;\n} ClockGenerator7AdvParams deriving (Bits, Eq);\n\ninstance DefaultValue#(ClockGenerator7AdvParams);\n   defaultValue = ClockGenerator7AdvParams {\n      bandwidth:          \"OPTIMIZED\",\n      compensation:       \"ZHOLD\",\n      clkin_buffer:       True,\n      clkin1_period:      5.000,\n      clkin2_period:      0.000,\n      reset_stages:       3,\n      clkfbout_mult_f:    1.000,\n      clkfbout_phase:     0.000,\n      divclk_divide:      1,\n      clkout0_buffer:     True,\n      clkout0n_buffer:    True,\n      clkout0_divide_f:   1.000,\n      clkout0_duty_cycle: 0.500,\n      clkout0_phase:      0.000,\n      clkout1_buffer:     True,\n      clkout1n_buffer:    True,\n      clkout1_divide:     1,\n      clkout1_duty_cycle: 0.500,\n      clkout1_phase:      0.000,\n      clkout2_buffer:     True,\n      clkout2n_buffer:    True,\n      clkout2_divide:     1,\n      clkout2_duty_cycle: 0.500,\n      clkout2_phase:      0.000,\n      clkout3_buffer:     True,\n      clkout3n_buffer:    True,\n      clkout3_divide:     1,\n      clkout3_duty_cycle: 0.500,\n      clkout3_phase:      0.000,\n      clkout4_buffer:     True,\n      clkout4_divide:     1,\n      clkout4_duty_cycle: 0.500,\n      clkout4_phase:      0.000,\n      clkout5_buffer:     True,\n      clkout5_divide:     1,\n      clkout5_duty_cycle: 0.500,\n      clkout5_phase:      0.000,\n      clkout6_buffer:     True,\n      clkout6_divide:     1,\n      clkout6_duty_cycle: 0.500,\n      clkout6_phase:      0.000,\n      ref_jitter1:        0.010,\n      ref_jitter2:        0.010,\n      use_same_family:    False\n      };\nendinstance\n\ninterface XVMMCME2;\n   interface Clock     clkout0;\n   interface Clock     clkout0_n;\n   interface Clock     clkout1;\n   interface Clock     clkout1_n;\n   interface Clock     clkout2;\n   interface Clock     clkout2_n;\n   interface Clock     clkout3;\n   interface Clock     clkout3_n;\n   interface Clock     clkout4;\n   interface Clock     clkout5;\n   interface Clock     clkout6;\n   interface Clock     clkfbout;\n   interface Clock     clkfbout_n;\n   (* always_ready, always_enabled *)\n   method    Bool      locked;\n   (* always_ready, always_enabled *)\n   method    Action    clkfbin(Bit#(1) clk);\nendinterface\n\nimport \"BVI\" MMCME2_ADV =\nmodule vMkXMMCME2_ADV#(MMCMParams params)(XVMMCME2);\n   Reset reset <- invertCurrentReset;\n   \n   default_clock clk1(CLKIN1);\n   default_reset rst(RST) = reset;\n   \n   parameter BANDWIDTH            = params.bandwidth;\n   parameter CLKFBOUT_USE_FINE_PS = params.clkfbout_use_fine_ps;\n   parameter CLKOUT0_USE_FINE_PS  = params.clkout0_use_fine_ps;\n   parameter CLKOUT1_USE_FINE_PS  = params.clkout1_use_fine_ps;\n   parameter CLKOUT2_USE_FINE_PS  = params.clkout2_use_fine_ps;\n   parameter CLKOUT3_USE_FINE_PS  = params.clkout3_use_fine_ps;\n   parameter CLKOUT4_CASCADE      = params.clkout4_cascade;\n   parameter CLKOUT4_USE_FINE_PS  = params.clkout4_use_fine_ps;\n   parameter CLKOUT5_USE_FINE_PS  = params.clkout5_use_fine_ps;\n   parameter CLKOUT6_USE_FINE_PS  = params.clkout6_use_fine_ps;\n   parameter COMPENSATION         = params.compensation;\n   parameter STARTUP_WAIT         = params.startup_wait;\n   parameter CLKFBOUT_MULT_F      = params.clkfbout_mult_f;\n   parameter CLKFBOUT_PHASE       = params.clkfbout_phase;\n   parameter CLKIN1_PERIOD        = params.clkin1_period;\n   parameter CLKIN2_PERIOD        = params.clkin2_period;\n   parameter DIVCLK_DIVIDE        = params.divclk_divide;\n   parameter CLKOUT0_DIVIDE_F     = params.clkout0_divide_f;\n   parameter CLKOUT0_DUTY_CYCLE   = params.clkout0_duty_cycle;\n   parameter CLKOUT0_PHASE        = params.clkout0_phase;\n   parameter CLKOUT1_DIVIDE       = params.clkout1_divide;\n   parameter CLKOUT1_DUTY_CYCLE   = params.clkout1_duty_cycle;\n   parameter CLKOUT1_PHASE        = params.clkout1_phase;\n   parameter CLKOUT2_DIVIDE       = params.clkout2_divide;\n   parameter CLKOUT2_DUTY_CYCLE   = params.clkout2_duty_cycle;\n   parameter CLKOUT2_PHASE        = params.clkout2_phase;\n   parameter CLKOUT3_DIVIDE       = params.clkout3_divide;\n   parameter CLKOUT3_DUTY_CYCLE   = params.clkout3_duty_cycle;\n   parameter CLKOUT3_PHASE        = params.clkout3_phase;\n   parameter CLKOUT4_DIVIDE       = params.clkout4_divide;\n   parameter CLKOUT4_DUTY_CYCLE   = params.clkout4_duty_cycle;\n   parameter CLKOUT4_PHASE        = params.clkout4_phase;\n   parameter CLKOUT5_DIVIDE       = params.clkout5_divide;\n   parameter CLKOUT5_DUTY_CYCLE   = params.clkout5_duty_cycle;\n   parameter CLKOUT5_PHASE        = params.clkout5_phase;\n   parameter CLKOUT6_DIVIDE       = params.clkout6_divide;\n   parameter CLKOUT6_DUTY_CYCLE   = params.clkout6_duty_cycle;\n   parameter CLKOUT6_PHASE        = params.clkout6_phase;\n   parameter REF_JITTER1          = params.ref_jitter1;\n   parameter REF_JITTER2          = params.ref_jitter2;\n   \n   port CLKIN2       = Bit#(1)'(0);\n   port CLKINSEL     = Bit#(1)'(1);\n   port DADDR        = Bit#(7)'(0);\n   port DCLK         = Bit#(1)'(0);\n   port DEN          = Bit#(1)'(0);\n   port DI           = Bit#(16)'(0);\n   port DWE          = Bit#(1)'(0);\n   port PSCLK        = Bit#(1)'(0);\n   port PSEN         = Bit#(1)'(0);\n   port PSINCDEC     = Bit#(1)'(0);\n   port PWRDWN       = Bit#(1)'(0);\n   \n   output_clock clkfbout(CLKFBOUT);\n   output_clock clkfbout_n(CLKFBOUTB);\n   output_clock clkout0(CLKOUT0);\n   output_clock clkout0_n(CLKOUT0B);\n   output_clock clkout1(CLKOUT1);\n   output_clock clkout1_n(CLKOUT1B);\n   output_clock clkout2(CLKOUT2);\n   output_clock clkout2_n(CLKOUT2B);\n   output_clock clkout3(CLKOUT3);\n   output_clock clkout3_n(CLKOUT3B);\n   output_clock clkout4(CLKOUT4);\n   output_clock clkout5(CLKOUT5);\n   output_clock clkout6(CLKOUT6);\n   \n   method LOCKED     locked()     clocked_by(no_clock) reset_by(no_reset);\n   method            clkfbin(CLKFBIN) enable((*inhigh*)en1) clocked_by(clkfbout) reset_by(no_reset);\n      \n   schedule clkfbin C clkfbin;\n   schedule locked CF (clkfbin, locked);\nendmodule\n\ninterface XClockGenerator7;\n   interface Clock        clkout0;\n   interface Clock        clkout0_n;\n   interface Clock        clkout1;\n   interface Clock        clkout1_n;\n   interface Clock        clkout2;\n   interface Clock        clkout2_n;\n   interface Clock        clkout3;\n   interface Clock        clkout3_n;\n   interface Clock        clkout4;\n   interface Clock        clkout5;\n   interface Clock        clkout6;\n   interface Clock     clkfbout;\n   (* always_ready *)\n   method    Bool         locked;\n   (* always_ready, always_enabled *)\n   method    Action    clkfbin(Bit#(1) clk);\nendinterface\n\nmodule mkClockGenerator7Adv#(ClockGenerator7AdvParams params)(XClockGenerator7);\n\n   ////////////////////////////////////////////////////////////////////////////////\n   /// Clocks & Resets\n   ////////////////////////////////////////////////////////////////////////////////\n   Clock                                     clk                 <- exposeCurrentClock;\n   Clock                                     clk_buffered         = ?;\n\n   if (params.clkin_buffer) begin\n      Clock inbuffer <- mkClockIBUFG\n`ifdef ClockDefaultParam\n          (defaultValue)\n`endif\n          ;\n      clk_buffered = inbuffer;\n   end\n   else begin\n      clk_buffered = clk;\n   end\n\n   //Reset                                     rst_n               <- mkSyncResetFromCR(params.reset_stages, clk_buffered);\n   //Reset                                     rst                 <- mkResetInverter(rst_n);\n\n   ////////////////////////////////////////////////////////////////////////////////\n   /// Design Elements\n   ////////////////////////////////////////////////////////////////////////////////\n   MMCMParams                                clkgen_params        = defaultValue;\n   clkgen_params.bandwidth          = params.bandwidth;\n   clkgen_params.compensation       = params.compensation;\n   clkgen_params.clkin1_period      = params.clkin1_period;\n   clkgen_params.clkin2_period      = params.clkin2_period;\n   clkgen_params.clkfbout_mult_f    = params.clkfbout_mult_f;\n   clkgen_params.clkfbout_phase     = params.clkfbout_phase;\n   clkgen_params.divclk_divide      = params.divclk_divide;\n   clkgen_params.clkout0_divide_f   = params.clkout0_divide_f;\n   clkgen_params.clkout0_duty_cycle = params.clkout0_duty_cycle;\n   clkgen_params.clkout0_phase      = params.clkout0_phase;\n   clkgen_params.clkout1_divide     = params.clkout1_divide;\n   clkgen_params.clkout1_duty_cycle = params.clkout1_duty_cycle;\n   clkgen_params.clkout1_phase      = params.clkout1_phase;\n   clkgen_params.clkout2_divide     = params.clkout2_divide;\n   clkgen_params.clkout2_duty_cycle = params.clkout2_duty_cycle;\n   clkgen_params.clkout2_phase      = params.clkout2_phase;\n   clkgen_params.clkout3_divide     = params.clkout3_divide;\n   clkgen_params.clkout3_duty_cycle = params.clkout3_duty_cycle;\n   clkgen_params.clkout3_phase      = params.clkout3_phase;\n   clkgen_params.clkout4_divide     = params.clkout4_divide;\n   clkgen_params.clkout4_duty_cycle = params.clkout4_duty_cycle;\n   clkgen_params.clkout4_phase      = params.clkout4_phase;\n   clkgen_params.clkout5_divide     = params.clkout5_divide;\n   clkgen_params.clkout5_duty_cycle = params.clkout5_duty_cycle;\n   clkgen_params.clkout5_phase      = params.clkout5_phase;\n   clkgen_params.clkout6_divide     = params.clkout6_divide;\n   clkgen_params.clkout6_duty_cycle = params.clkout6_duty_cycle;\n   clkgen_params.clkout6_phase      = params.clkout6_phase;\n   clkgen_params.ref_jitter1        = params.ref_jitter1;\n   clkgen_params.ref_jitter2        = params.ref_jitter2;\n   clkgen_params.use_same_family    = params.use_same_family;\n\n   XVMMCME2 pll <- vMkXMMCME2_ADV(clkgen_params);\n\n   //(* fire_when_enabled, no_implicit_conditions *)\n   //rule connect_feedback;\n      //pll.clkfbin( pll.clkfbout);\n   //endrule\n\n   Clock                                     clkout0_buf          = ?;\n   Clock                                     clkout0n_buf         = ?;\n   Clock                                     clkout1_buf          = ?;\n   Clock                                     clkout1n_buf         = ?;\n   Clock                                     clkout2_buf          = ?;\n   Clock                                     clkout2n_buf         = ?;\n   Clock                                     clkout3_buf          = ?;\n   Clock                                     clkout3n_buf         = ?;\n   Clock                                     clkout4_buf          = ?;\n   Clock                                     clkout5_buf          = ?;\n   Clock                                     clkout6_buf          = ?;\n\n   if (params.clkout0_buffer) begin\n      Clock clkout0buffer <- mkClockBUFG(clocked_by pll.clkout0);\n      clkout0_buf = clkout0buffer;\n   end\n   else begin\n      clkout0_buf = pll.clkout0;\n   end\n\n   if (params.clkout0n_buffer) begin\n      Clock clkout0nbuffer <- mkClockBUFG(clocked_by pll.clkout0_n);\n      clkout0n_buf = clkout0nbuffer;\n   end\n   else begin\n      clkout0n_buf = pll.clkout0_n;\n   end\n\n   if (params.clkout1_buffer) begin\n      Clock clkout1buffer <- mkClockBUFG(clocked_by pll.clkout1);\n      clkout1_buf = clkout1buffer;\n   end\n   else begin\n      clkout1_buf = pll.clkout1;\n   end\n\n   if (params.clkout1n_buffer) begin\n      Clock clkout1nbuffer <- mkClockBUFG(clocked_by pll.clkout1_n);\n      clkout1n_buf = clkout1nbuffer;\n   end\n   else begin\n      clkout1n_buf = pll.clkout1_n;\n   end\n\n   if (params.clkout2_buffer) begin\n      Clock clkout2buffer <- mkClockBUFG(clocked_by pll.clkout2);\n      clkout2_buf = clkout2buffer;\n   end\n   else begin\n      clkout2_buf = pll.clkout2;\n   end\n\n   if (params.clkout2n_buffer) begin\n      Clock clkout2nbuffer <- mkClockBUFG(clocked_by pll.clkout2_n);\n      clkout2n_buf = clkout2nbuffer;\n   end\n   else begin\n      clkout2n_buf = pll.clkout2_n;\n   end\n\n   if (params.clkout3_buffer) begin\n      Clock clkout3buffer <- mkClockBUFG(clocked_by pll.clkout3);\n      clkout3_buf = clkout3buffer;\n   end\n   else begin\n      clkout3_buf = pll.clkout3;\n   end\n\n   if (params.clkout3n_buffer) begin\n      Clock clkout3nbuffer <- mkClockBUFG(clocked_by pll.clkout3_n);\n      clkout3n_buf = clkout3nbuffer;\n   end\n   else begin\n      clkout3n_buf = pll.clkout3_n;\n   end\n\n   if (params.clkout4_buffer) begin\n      Clock clkout4buffer <- mkClockBUFG(clocked_by pll.clkout4);\n      clkout4_buf = clkout4buffer;\n   end\n   else begin\n      clkout4_buf = pll.clkout4;\n   end\n\n   if (params.clkout5_buffer) begin\n      Clock clkout5buffer <- mkClockBUFG(clocked_by pll.clkout5);\n      clkout5_buf = clkout5buffer;\n   end\n   else begin\n      clkout5_buf = pll.clkout5;\n   end\n\n   if (params.clkout6_buffer) begin\n      Clock clkout6buffer <- mkClockBUFG(clocked_by pll.clkout6);\n      clkout6_buf = clkout6buffer;\n   end\n   else begin\n      clkout6_buf = pll.clkout6;\n   end\n\n   ////////////////////////////////////////////////////////////////////////////////\n   /// Interface Connections / Methods\n   ////////////////////////////////////////////////////////////////////////////////\n\n   interface Clock        clkout0   = clkout0_buf;\n   interface Clock        clkout0_n = clkout0n_buf;\n   interface Clock        clkout1   = clkout1_buf;\n   interface Clock        clkout1_n = clkout1n_buf;\n   interface Clock        clkout2   = clkout2_buf;\n   interface Clock        clkout2_n = clkout2n_buf;\n   interface Clock        clkout3   = clkout3_buf;\n   interface Clock        clkout3_n = clkout3n_buf;\n   interface Clock        clkout4   = clkout4_buf;\n   interface Clock        clkout5   = clkout5_buf;\n   interface Clock        clkout6   = clkout6_buf;\n   method    Bool         locked    = pll.locked;\n   interface Clock        clkfbout = pll.clkfbout;\n   method                 clkfbin = pll.clkfbin;\nendmodule: mkClockGenerator7Adv\n\n////////////////////////////////////////////////////////////\n\n(* always_ready, always_enabled *)\ninterface IbufdsTest;\n   (* prefix=\"\" *)\t  \n   method Action in(Bit#(1) i, Bit#(1) ib);\n   interface ReadOnly#(Bit#(1)) o;\nendinterface\n\nmodule mkIbufdsTest(IbufdsTest);\n   Wire#(Bit#(1)) i_w <- mkDWire(0);\n   Wire#(Bit#(1)) ib_w <- mkDWire(0);\n   ReadOnly#(Bit#(1)) ibufds <- mkIBUFDS(i_w, ib_w);\n\n   method Action in(Bit#(1) i, Bit#(1) ib);\n       i_w <= i;\n       ib_w <= ib;\n   endmethod\n   interface ReadOnly o = ibufds;\nendmodule\n\n(* always_ready, always_enabled *)\ninterface BIBUF#(numeric type sa);\n    interface Inout#(Bit#(sa))     pad;\nendinterface\nimport \"BVI\" GenBIBUF =\nmodule mkBIBUF#(Inout#(a) v)(BIBUF#(sa)) provisos(Bits#(a, sa));\n    let sa = fromInteger(valueOf(sa));\n    parameter SIZE=sa;\n    default_clock clk();\n    default_reset rst();\n    inout IO = v;\n    ifc_inout pad(PAD);\nendmodule\n\n(* always_ready, always_enabled *)\ninterface IOBUF;\n    method Bit#(1)            o();\n    interface Inout#(Bit#(1)) io;\nendinterface\nimport \"BVI\" IOBUF =\nmodule mkIOBUF#(Bit#(1) t, Bit#(1) i)(IOBUF);\n    default_clock clk();\n    default_reset rst();\n    port I = i;\n    port T = t;\n    method O o();\n    ifc_inout io(IO);\n    schedule (o) CF (o);\nendmodule\n\n"
  },
  {
    "path": "bsv/CtrlMux.bsv",
    "content": "\n// Copyright (c) 2012 Nokia, Inc.\n// Copyright (c) 2013 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\nimport Vector::*;\nimport GetPut::*;\nimport FIFOF::*;\nimport SpecialFIFOs::*;\nimport FIFO::*;\n\n`include \"ConnectalProjectConfig.bsv\"\nimport ConnectalConfig::*;\nimport HostInterface::*;\nimport Connectable::*;\nimport AddressGenerator::*;\n\nimport Portal::*;\nimport ConnectalMemTypes::*;\nimport Arith::*;\nimport Pipe::*;\n\ninterface PortalCtrl#(numeric type addrWidth, numeric type dataWidth);\n   method ActionValue#(Bit#(dataWidth)) read(Bit#(addrWidth) addr);\n   method Action write(Bit#(addrWidth) addr, Bit#(dataWidth) v);\nendinterface\n\ninterface PortalCtrlMemSlave#(numeric type addrWidth, numeric type dataWidth);\n   interface PortalCtrl#(addrWidth, dataWidth)  memSlave;\n   interface ReadOnly#(Bool)                    interrupt;\n   interface WriteOnly#(Bit#(dataWidth))        num_portals;\nendinterface\n\nmodule mkInterruptMux#(Vector#(numPortals,ReadOnly#(Bool)) inputs) (ReadOnly#(Bool))\n   provisos(Add#(nz, TLog#(numPortals), 4),\n\t    Add#(1, a__, numPortals));\n   function Bool my_read(ReadOnly#(Bool) x);\n      return x._read;\n   endfunction\n   method Bool _read;\n      return fold(boolor,map(my_read,inputs));\n   endmethod\nendmodule\n\nmodule mkPortalInterrupt#(Vector#(numIndications, PipeOut#(Bit#(dataWidth))) indicationPipes)\n   (PortalInterrupt#(dataWidth));\n   Bool      interruptStatus = False;\n   function Bool pipeOutNotEmpty(PipeOut#(a) po); return po.notEmpty(); endfunction\n   Vector#(numIndications, Bool) readyBits = map(pipeOutNotEmpty, indicationPipes);\n   \n   Bit#(dataWidth)  readyChannel = -1;\n   for (Integer i = valueOf(numIndications) - 1; i >= 0; i = i - 1) begin\n      if (readyBits[i]) begin\n         interruptStatus = True;\n         readyChannel = fromInteger(i);\n      end\n   end\n   method Bool status();\n      return interruptStatus;\n   endmethod\n   method Bit#(dataWidth) channel();\n      return readyChannel;\n   endmethod\nendmodule\n\nmodule mkPortalCtrlMemSlave#(Bit#(dataWidth) ifcId, PortalInterrupt#(dataWidth) intr)\n   (PortalCtrlMemSlave#(addrWidth, dataWidth))\n   provisos(Add#(d__, dataWidth, TMul#(dataWidth, 2)));\n   Reg#(Bit#(dataWidth)) num_portals_reg <- mkReg(0);\n   Reg#(Bool) interruptEnableReg <- mkReg(False);\n   Reg#(Bit#(TMul#(dataWidth,2))) cycle_count <- mkReg(0);\n   Reg#(Bit#(dataWidth))    snapshot <- mkReg(0);\n   let verbose = False;\n   \n   rule count;\n      cycle_count <= cycle_count+1;\n   endrule\n   \n   interface PortalCtrl memSlave;\n   method Action write(Bit#(addrWidth) addr, Bit#(dataWidth) v);\n      if (addr == 4)\n\t interruptEnableReg <= v[0] == 1'd1;\n   endmethod\n\n   method ActionValue#(Bit#(dataWidth)) read(Bit#(addrWidth) addr);\n\t       let v = 'h05a05a0;\n\t       if (addr == 0)\n\t\t  v = intr.status() ? 1 : 0;\n\t       if (addr == 4)\n\t\t  v = interruptEnableReg ? 1 : 0;\n\t       if (addr == 8)\n\t\t  v = fromInteger(valueOf(NumberOfTiles));\n               if (addr == 'h00C) begin\n\t\t  if (intr.status())\n\t\t     v = intr.channel()+1;\n\t\t  else \n\t\t     v = 0;\n               end\n\t       if (addr == 'h010)\n\t\t  v = ifcId;\n\t       if (addr == 'h014)\n\t\t  v = num_portals_reg;\n\t       if (addr == 'h018) begin\n\t\t  snapshot <= truncate(cycle_count);\n\t\t  v = truncate(cycle_count>>valueOf(dataWidth));\n\t       end\n\t       if (addr == 'h01C)\n\t\t  v = snapshot;\n\t       return v;\n   endmethod\n   endinterface\n   interface ReadOnly interrupt;\n      method Bool _read();\n\t return intr.status() && interruptEnableReg;\n      endmethod\n   endinterface\n   interface WriteOnly num_portals;\n      method Action _write(Bit#(dataWidth) v);\n\t num_portals_reg <= v;\n      endmethod\n   endinterface\nendmodule   \n\nmodule mkMemMethodMuxIn#(PortalCtrl#(aw,dataWidth) ctrl, Vector#(numRequests, PipeIn#(Bit#(dataWidth))) requests\n        )(PhysMemSlave#(addrWidth,dataWidth))\n   provisos(Add#(selWidth,aw,addrWidth)\n\t    , Add#(a__, TLog#(numRequests), selWidth)\n            , Add#(1, b__, dataWidth)\n      );\n   AddressGenerator#(aw,dataWidth) fifoReadAddrGenerator  <- mkAddressGenerator();\n   AddressGenerator#(aw,dataWidth) fifoWriteAddrGenerator <- mkAddressGenerator();\n   FIFO#(Bit#(MemTagSize))                fifoWriteDoneFifo <- mkFIFO();\n   let port_sel_low = valueOf(aw);\n   let port_sel_high = valueOf(TSub#(addrWidth,1));\n   function Bit#(selWidth) psel(Bit#(addrWidth) a);\n      Bit#(selWidth) v = a[port_sel_high:port_sel_low];\n      return v - 1;\n   endfunction\n   function Bool pselCtrl(Bit#(addrWidth) a);\n      Bit#(selWidth) v = a[port_sel_high:port_sel_low];\n      return v == 0;\n   endfunction\n   function Bit#(aw) asel(Bit#(addrWidth) a);\n      return a[(port_sel_low-1):0];\n   endfunction\n\n   FIFO#(Bit#(MemTagSize)) doneFifo          <- mkFIFO1();\n   FIFO#(PhysMemRequest#(aw,dataWidth)) req_ars <- mkFIFO1();\n   FIFO#(Bit#(TLog#(numRequests))) rs <- mkFIFO1();\n   FIFO#(Bool)                   rsCtrl <- mkFIFO1();\n   FIFO#(PhysMemRequest#(aw,dataWidth)) req_aws <- mkFIFO1();\n   FIFO#(Bit#(TLog#(numRequests))) ws <- mkFIFO1();\n   FIFO#(Bool)                   wsCtrl <- mkFIFO1();\n\n   rule write_done;\n      let rv <- toGet(fifoWriteDoneFifo).get();\n      ws.deq();\n      wsCtrl.deq();\n      doneFifo.enq(rv);\n   endrule\n\n   rule req_aw;\n      let req <- toGet(req_aws).get;\n      fifoWriteAddrGenerator.request.put(req);\n   endrule\n\n   rule req_ar;\n      let req <- toGet(req_ars).get;\n      fifoReadAddrGenerator.request.put(req);\n   endrule\n\n   FIFO#(MemData#(dataWidth)) writeDataFifo <- mkFIFO();\n   rule writeDataRule;\n      let wdata <- toGet(writeDataFifo).get();\n      //$display(\"mkMemMethodMux.writeData aw=%d ws=%d data=%h\", valueOf(aw), ws.first, wdata.data);\n      let b <- fifoWriteAddrGenerator.addrBeat.get();\n      //$display(\"mkPipeInMemSlave.writeData.put addr=%h data=%h\", b.addr, wdata.data);\n      if (b.last)\n\t fifoWriteDoneFifo.enq(b.tag);\n      if (wsCtrl.first)\n\t ctrl.write(b.addr, wdata.data);\n      else begin\n\t requests[ws.first].enq(wdata.data);\n\t // this used to be where we triggered putFailed\n      end\n   endrule\n\n   FIFO#(MemData#(dataWidth)) rvFifo <- mkFIFO;\n   rule rvrule;\n\t let v = 0;\n      let b <- fifoReadAddrGenerator.addrBeat.get();\n      if (rsCtrl.first) begin\n\t let vr <- ctrl.read(b.addr);\n         v = vr;\n      end\n      else begin\n\t if (b.addr == 4)\n\t    v = extend(pack(requests[rs.first].notFull()));\n      end\n      rvFifo.enq(MemData { data: v, tag: b.tag, last: b.last });\n      //$display(\"mkMemMethodMux.readData aw=%d rs=%d data=%h\", valueOf(aw), rs.first, rv.data);\n      if (b.last) begin\n\t rs.deq();\n\t rsCtrl.deq();\n      end\n   endrule\n\n   interface PhysMemWriteServer write_server;\n      interface Put writeReq;\n\t method Action put(PhysMemRequest#(addrWidth,dataWidth) req);\n\t    req_aws.enq(PhysMemRequest{addr:asel(req.addr), burstLen:req.burstLen, tag:req.tag\n`ifdef BYTE_ENABLES\n\t\t\t\t       , firstbe: req.firstbe, lastbe: req.lastbe\n`endif\n\t\t\t\t       });\n\t    if (req.burstLen > 4) $display(\"**** \\n\\n mkMemMethodMux.writeReq len=%d \\n\\n ****\", req.burstLen);\n\t    //$display(\"mkMemMethodMux.writeReq addr=%h selWidth=%d aw=%d psel=%h pselCtrl=%x\", req.addr, valueOf(selWidth), valueOf(aw), psel(req.addr), pselCtrl(req.addr));\n\t    ws.enq(truncate(psel(req.addr)));\n            wsCtrl.enq(pselCtrl(req.addr));\n\t endmethod\n      endinterface\n      interface Put writeData;\n\t method Action put(MemData#(dataWidth) wdata);\n\t    writeDataFifo.enq(wdata);\n\t endmethod\n      endinterface\n      interface Get writeDone;\n\t method ActionValue#(Bit#(MemTagSize)) get();\n\t    let rv <- toGet(doneFifo).get();\n\t    return rv;\n\t endmethod\n      endinterface\n   endinterface\n   interface PhysMemReadServer read_server;\n      interface Put readReq;\n\t method Action put(PhysMemRequest#(addrWidth,dataWidth) req);\n\t    req_ars.enq(PhysMemRequest{addr:asel(req.addr), burstLen:req.burstLen, tag:req.tag\n`ifdef BYTE_ENABLES\n\t\t\t\t       , firstbe: req.firstbe, lastbe: req.lastbe\n`endif\n\t       });\n\t    //$display(\"mkMemMethodMux.readReq addr=%h aw=%d psel=%h pselCtrl=%x\", req.addr, valueOf(aw), psel(req.addr), pselCtrl(req.addr));\n\t    if (req.burstLen > 4) $display(\"**** \\n\\n mkMemMethodMux.readReq len=%d \\n\\n ****\", req.burstLen);\n\t    rs.enq(truncate(psel(req.addr)));\n            rsCtrl.enq(pselCtrl(req.addr));\n\t endmethod\n      endinterface\n      interface Get readData;\n\t method ActionValue#(MemData#(dataWidth)) get();\n\t    let rv <- toGet(rvFifo).get();\n\t    return rv;\n\t endmethod\n      endinterface\n   endinterface\nendmodule\n\nmodule mkMemMethodMuxOut#(PortalCtrl#(aw,dataWidth) ctrl, Vector#(numIndications, PipeOut#(Bit#(dataWidth))) indications)(PhysMemSlave#(addrWidth,dataWidth))\n   provisos(Add#(selWidth,aw,addrWidth)\n\t    , Add#(a__, TLog#(numIndications), selWidth)\n            , Add#(1, b__, dataWidth)\n      );\n   AddressGenerator#(aw,dataWidth) fifoReadAddrGenerator <- mkAddressGenerator();\n   AddressGenerator#(aw,dataWidth) fifoWriteAddrGenerator <- mkAddressGenerator();\n   FIFO#(Bit#(MemTagSize))                fifoWriteDoneFifo <- mkFIFO();\n   let port_sel_low = valueOf(aw);\n   let port_sel_high = valueOf(TSub#(addrWidth,1));\n   function Bit#(selWidth) psel(Bit#(addrWidth) a);\n      Bit#(selWidth) v = a[port_sel_high:port_sel_low];\n      return v - 1;\n   endfunction\n   function Bool pselCtrl(Bit#(addrWidth) a);\n      Bit#(selWidth) v = a[port_sel_high:port_sel_low];\n      return v == 0;\n   endfunction\n   function Bit#(aw) asel(Bit#(addrWidth) a);\n      return a[(port_sel_low-1):0];\n   endfunction\n\n   FIFO#(Bit#(MemTagSize)) doneFifo          <- mkFIFO1();\n   FIFO#(PhysMemRequest#(aw,dataWidth)) req_ars <- mkFIFO1();\n   FIFO#(Bit#(TLog#(numIndications))) rs <- mkFIFO1();\n   FIFO#(Bool)                   rsCtrl <- mkFIFO1();\n   FIFO#(PhysMemRequest#(aw,dataWidth)) req_aws <- mkFIFO1();\n   FIFO#(Bit#(TLog#(numIndications))) ws <- mkFIFO1();\n   FIFO#(Bool)                   wsCtrl <- mkFIFO1();\n\n   rule write_done;\n      let rv <- toGet(fifoWriteDoneFifo).get();\n      ws.deq();\n      wsCtrl.deq();\n      doneFifo.enq(rv);\n   endrule\n\n   rule req_aw;\n      let req <- toGet(req_aws).get;\n      fifoWriteAddrGenerator.request.put(req);\n   endrule\n\n   rule req_ar;\n      let req <- toGet(req_ars).get;\n      fifoReadAddrGenerator.request.put(req);\n   endrule\n\n   FIFO#(MemData#(dataWidth)) rvFifo <- mkFIFO;\n   rule rvrule;\n      let b <- fifoReadAddrGenerator.addrBeat.get();\n      let rv = MemData { data: 0, tag: b.tag, last: b.last };\n      if (rsCtrl.first) begin\n\t let vr <- ctrl.read(b.addr);\n         rv.data = vr;\n      end\n      else begin\n\t if (b.addr == 0)\n\t    rv.data <- toGet(indications[rs.first]).get();\n\t else if (b.addr == 4)\n\t    rv.data = extend(pack(indications[rs.first].notEmpty()));\n      end\n      rvFifo.enq(rv);\n      //$display(\"mkMemMethodMux.readData aw=%d rs=%d data=%h\", valueOf(aw), rs.first, rv.data);\n      rs.deq();\n      rsCtrl.deq();\n   endrule\n\n   interface PhysMemWriteServer write_server;\n      interface Put writeReq;\n\t method Action put(PhysMemRequest#(addrWidth,dataWidth) req);\n\t    req_aws.enq(PhysMemRequest{addr:asel(req.addr), burstLen:req.burstLen, tag:req.tag\n`ifdef BYTE_ENABLES\n\t       , firstbe: req.firstbe, lastbe: req.lastbe\n`endif\n\t       });\n\t    if (req.burstLen > 4) $display(\"**** \\n\\n mkMemMethodMux.writeReq len=%d \\n\\n ****\", req.burstLen);\n\t    //$display(\"mkMemMethodMux.writeReq addr=%h selWidth=%d aw=%d psel=%h pselCtrl=%x\", req.addr, valueOf(selWidth), valueOf(aw), psel(req.addr), pselCtrl(req.addr));\n\t    ws.enq(truncate(psel(req.addr)));\n            wsCtrl.enq(pselCtrl(req.addr));\n\t endmethod\n      endinterface\n      interface Put writeData;\n\t method Action put(MemData#(dataWidth) wdata);\n\t    //$display(\"mkMemMethodMux.writeData aw=%d ws=%d data=%h\", valueOf(aw), ws.first, wdata.data);\n\t    let b <- fifoWriteAddrGenerator.addrBeat.get();\n            if (wsCtrl.first)\n\t       ctrl.write(b.addr, wdata.data);\n\t       //$display(\"mkPipeOutMemSlave.writeData.put addr=%h data=%h\", b.addr, d.data);\n\t       if (b.last)\n\t          fifoWriteDoneFifo.enq(b.tag);\n\t endmethod\n      endinterface\n      interface Get writeDone;\n\t method ActionValue#(Bit#(MemTagSize)) get();\n\t    let rv <- toGet(doneFifo).get();\n\t    return rv;\n\t endmethod\n      endinterface\n   endinterface\n   interface PhysMemReadServer read_server;\n      interface Put readReq;\n\t method Action put(PhysMemRequest#(addrWidth,dataWidth) req);\n\t    req_ars.enq(PhysMemRequest{addr:asel(req.addr), burstLen:req.burstLen, tag:req.tag\n`ifdef BYTE_ENABLES\n\t       , firstbe: req.firstbe, lastbe: req.lastbe\n`endif\n\t       });\n\t    //$display(\"mkMemMethodMux.readReq addr=%h aw=%d psel=%h pselCtrl=%x\", req.addr, valueOf(aw), psel(req.addr), pselCtrl(req.addr));\n\t    if (req.burstLen > 4) $display(\"**** \\n\\n mkMemMethodMux.readReq len=%d \\n\\n ****\", req.burstLen);\n\t    rs.enq(truncate(psel(req.addr)));\n            rsCtrl.enq(pselCtrl(req.addr));\n\t endmethod\n      endinterface\n      interface Get readData;\n\t method ActionValue#(MemData#(dataWidth)) get();\n\t    let rv <- toGet(rvFifo).get();\n\t    return rv;\n\t endmethod\n      endinterface\n   endinterface\nendmodule\n\nmodule mkPhysMemSlaveMux#(Vector#(numSlaves,PhysMemSlave#(aw,dataWidth)) slaves) (PhysMemSlave#(addrWidth,dataWidth))\n   provisos(Add#(selWidth,aw,addrWidth)\n\t    ,Add#(a__, TLog#(numSlaves), selWidth)\n\t    ,Min#(4,TLog#(numSlaves),bpc)\n\t    ,Pipe::FunnelPipesPipelined#(1, numSlaves, ConnectalMemTypes::MemData#(dataWidth),bpc)\n\t    );\n   let port_sel_low = valueOf(aw);\n   let port_sel_high = valueOf(TSub#(addrWidth,1));\n   function Bit#(selWidth) psel(Bit#(addrWidth) a);\n      return a[port_sel_high:port_sel_low];\n   endfunction\n   function Bit#(aw) asel(Bit#(addrWidth) a);\n      return a[(port_sel_low-1):0];\n   endfunction\n   function Get#(MemData#(dataWidth)) getMemPortalReadData(PhysMemSlave#(aw,dataWidth) x) = x.read_server.readData;\n   function Put#(MemData#(dataWidth)) getMemPortalWriteData(PhysMemSlave#(aw,dataWidth) x) = x.write_server.writeData;\n   \n   Reg#(Bool) lastWriteDataSeen <- mkReg(False);\n   FIFO#(Bit#(MemTagSize))        doneFifo <- mkFIFO1();\n   FIFO#(PhysMemRequest#(aw,dataWidth)) req_ars <- mkSizedFIFO(1);\n   FIFO#(Bit#(TLog#(numSlaves))) rs <- mkFIFO1();\n   Vector#(numSlaves, PipeOut#(MemData#(dataWidth))) readDataPipes <- mapM(mkPipeOut, map(getMemPortalReadData,slaves));\n   FunnelPipe#(1, numSlaves, MemData#(dataWidth), bpc) read_data_funnel <- mkFunnelPipesPipelined(readDataPipes);\n      \n   FIFO#(PhysMemRequest#(aw,dataWidth)) req_aws <- mkFIFO1();\n   FIFO#(Bit#(TLog#(numSlaves))) ws <- mkFIFO1();\n   FIFOF#(Tuple2#(Bit#(TLog#(numSlaves)), MemData#(dataWidth))) write_data <- mkFIFOF;\n   UnFunnelPipe#(1, numSlaves, MemData#(dataWidth), bpc) write_data_unfunnel <- mkUnFunnelPipesPipelined(cons(toPipeOut(write_data),nil));\n   Vector#(numSlaves, PipeIn#(MemData#(dataWidth))) writeDataPipes <- mapM(mkPipeIn, map(getMemPortalWriteData,slaves));\n   zipWithM_(mkConnection, write_data_unfunnel, writeDataPipes);\n   let verbose = False;\n \n   rule req_aw;\n      let req <- toGet(req_aws).get;\n      slaves[ws.first].write_server.writeReq.put(req);\n   endrule\n         \n   rule req_ar;\n      let req <- toGet(req_ars).get;\n      slaves[rs.first].read_server.readReq.put(req);\n   endrule\n   \n   rule write_done_rule;\n      let rv <- slaves[ws.first].write_server.writeDone.get();\n      ws.deq();\n      doneFifo.enq(rv);\n   endrule\n\n   interface PhysMemWriteServer write_server;\n      interface Put writeReq;\n\t method Action put(PhysMemRequest#(addrWidth,dataWidth) req);\n\t    req_aws.enq(PhysMemRequest{addr:asel(req.addr), burstLen:req.burstLen, tag:req.tag\n`ifdef BYTE_ENABLES\n\t       , firstbe: req.firstbe, lastbe: req.lastbe\n`endif\n\t       });\n\t    if (req.burstLen > 4) $display(\"**** \\n\\n mkPhysMemSlaveMux.writeReq len=%d \\n\\n ****\", req.burstLen);\n\t    ws.enq(truncate(psel(req.addr)));\n\t    lastWriteDataSeen <= False;\n\t    if(verbose) $display(\"mkPhysMemSlaveMux.writeReq addr=%h aw=%d psel=%h\", req.addr, valueOf(aw), psel(req.addr));\n\t endmethod\n      endinterface\n      interface Put writeData;\n\t method Action put(MemData#(dataWidth) wdata) if (!lastWriteDataSeen);\n\t    write_data.enq(tuple2(ws.first,wdata));\n\t    if (wdata.last) begin\n\t       lastWriteDataSeen <= True;\n\t    end\n\t    if(verbose) $display(\"mkPhysMemSlaveMux.writeData dst=%h wdata=%h\", ws.first,wdata);\n\t endmethod\n      endinterface\n      interface Get writeDone;\n\t method ActionValue#(Bit#(MemTagSize)) get();\n\t    let rv <- toGet(doneFifo).get();\n\t    return rv;\n\t endmethod\n      endinterface\n   endinterface\n   interface PhysMemReadServer read_server;\n      interface Put readReq;\n\t method Action put(PhysMemRequest#(addrWidth,dataWidth) req);\n\t    req_ars.enq(PhysMemRequest{addr:asel(req.addr), burstLen:req.burstLen, tag:req.tag\n`ifdef BYTE_ENABLES\n\t\t\t\t       , firstbe: req.firstbe, lastbe: req.lastbe\n`endif\n\t       });\n\t    rs.enq(truncate(psel(req.addr)));\n\t    if (req.burstLen > 4) $display(\"**** \\n\\n mkPhysMemSlaveMux.readReq len=%d \\n\\n ****\", req.burstLen);\n\t    if(verbose) $display(\"mkPhysMemSlaveMux.readReq addr=%h aw=%d psel=%h\", req.addr, valueOf(aw), psel(req.addr));\n\t endmethod\n      endinterface\n      interface Get readData;\n\t method ActionValue#(MemData#(dataWidth)) get();\n\t    let rv <- toGet(read_data_funnel[0]).get;\n\t    rs.deq();\n\t    if(verbose) $display(\"mkPhysMemSlaveMux.readData rs=%d data=%h\", rs.first, rv.data);\n\t    return rv;\n\t endmethod\n      endinterface\n   endinterface\nendmodule\n\nmodule mkSlaveMux#(Vector#(numPortals,MemPortal#(aw,dataWidth)) portals) (PhysMemSlave#(addrWidth,dataWidth))\n   provisos(Add#(selWidth,aw,addrWidth)\n\t    ,Add#(a__, TLog#(numPortals), selWidth)\n\t    ,FunnelPipesPipelined#(1, numPortals, MemData#(dataWidth),TMin#(4, TLog#(numPortals)))\n\t    );\n   function PhysMemSlave#(_a,_d) getSlave(MemPortal#(_a,_d) p);\n      return p.slave;\n   endfunction\n   Vector#(numPortals, PhysMemSlave#(aw,dataWidth)) slaves = map(getSlave, portals);\n   for(Integer i = 0; i < valueOf(numPortals); i=i+1)\n      rule writeTop;\n\t portals[i].num_portals <= fromInteger(valueOf(numPortals));\n      endrule\n   let rv <- mkPhysMemSlaveMux(slaves);\n   return rv;\nendmodule\n"
  },
  {
    "path": "bsv/DisplayInd.bsv",
    "content": "// Copyright (c) 2014 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\ninterface DisplayInd;\nendinterface\n"
  },
  {
    "path": "bsv/Dsp48E1.bsv",
    "content": "import GetPut::*;\nimport FIFO::*;\nimport FIFOF::*;\nimport Clocks::*;\nimport ConnectalClocks::*;\n`include \"ConnectalProjectConfig.bsv\"\n\ninterface Dsp48E1;\n   method Bool     notEmpty();\n   method Bit#(48) p();\n   method Action deq();\n// Control: 4-bit (each) input: Control Inputs/Status Bits\n   method Action alumode(Bit#(4) v);\t\t// 4-bit input: ALU control input\n   method Action carryinsel(Bit#(3) v);\t\t// 3-bit input: Carry select input\n   method Action inmode(Bit#(5) v);\t\t// 5-bit input: INMODE control input\n   method Action opmode(Bit#(7) v);\t\t// 7-bit input: Operation mode input\n   method Action a(Bit#(30) v);\n   method Action b(Bit#(18) v);\n   method Action c(Bit#(48) v);\n   method Action d(Bit#(25) v);\n   method Action last(Bit#(1) v);\nendinterface\n\n`ifndef SIMULATION //fixme xsim\n(* always_ready, always_enabled *)\ninterface PRIM_DSP48E1;\n   method Bit#(48) p();\n// Control: 4-bit (each) input: Control Inputs/Status Bits\n   method Action alumode(Bit#(4) v);\t\t// 4-bit input: ALU control input\n   method Action carryinsel(Bit#(3) v);\t\t// 3-bit input: Carry select input\n   method Action inmode(Bit#(5) v);\t\t// 5-bit input: INMODE control input\n   method Action opmode(Bit#(7) v);\t\t// 7-bit input: Operation mode input\n   method Action a(Bit#(30) v);\n   method Action b(Bit#(18) v);\n   method Action c(Bit#(48) v);\n   method Action d(Bit#(25) v);\n   method Action acin(Bit#(30) v);\n   method Action bcin(Bit#(18) v);\n   method Action carrycascin(Bit#(1) v);\n   method Action carryin(Bit#(1) v);\n   method Action multsignin(Bit#(1) v);\n   method Action pcin(Bit#(48) v);\n\n   method Action cea1(Bit#(1) en);\t\t// 1-bit input: Clock enable input for 1st stage AREG\n   method Action cea2(Bit#(1) en);\t\t// 1-bit input: Clock enable input for 2nd stage AREG\n   method Action cead(Bit#(1) en);\t\t// 1-bit input: Clock enable input for ADREG\n   method Action ceb1(Bit#(1) en);\t\t// 1-bit input: Clock enable input for 1st stage BREG\n   method Action ceb2(Bit#(1) en);\t\t// 1-bit input: Clock enable input for 2nd stage BREG\n   method Action cealumode(Bit#(1) en);\t\t// 1-bit input: Clock enable input for ALUMODE\n   method Action cec(Bit#(1) en);\t\t// 1-bit input: Clock enable input for CREG\n   method Action cecarryin(Bit#(1) en);\t\t// 1-bit input: Clock enable input for CARRYINREG\n   method Action cectrl(Bit#(1) en);\t\t// 1-bit input: Clock enable input for OPMODEREG and CARRYINSELREG\n   method Action ced(Bit#(1) en);\t\t// 1-bit input: Clock enable input for DREG\n   method Action ceinmode(Bit#(1) en);\t\t// 1-bit input: Clock enable input for INMODEREG\n   method Action cem(Bit#(1) en);\t\t// 1-bit input: Clock enable input for MREG\n   method Action cep(Bit#(1) en);\t\t// 1-bit input: Clock enable input for PREG\nendinterface\n\nimport \"BVI\" DSP48E1 =\nmodule vmkDSP48E1(PRIM_DSP48E1);\n   let currentClock <- exposeCurrentClock;\n   let currentReset <- exposeCurrentReset;\n`ifndef BSV_POSITIVE_RESET\n   let positiveReset <- mkPositiveReset(10, currentReset, currentClock);\n   let dspReset = positiveReset.positiveReset;\n`else\n   let dspReset = currentReset;\n`endif\n   default_clock clk(CLK);\n\n   default_reset rsta(RSTA) = dspReset;\n   input_reset rstb(RSTB) = dspReset;\n   input_reset rstc(RSTC) = dspReset;\n   input_reset rstd(RSTD) = dspReset;\n   input_reset rstallcarryin(RSTALLCARRYIN) = dspReset;\n   input_reset rstalumode(RSTALUMODE) = dspReset;\n   input_reset rstctrl(RSTCTRL) = dspReset;\n   input_reset rstinmode(RSTINMODE) = dspReset;\n   input_reset rstm(RSTM) = dspReset;\n   input_reset rstp(RSTP) = dspReset;\n\n   method P p();\n   method alumode(ALUMODE) enable ((*inhigh*)EN_alumode);\n   method carryinsel(CARRYINSEL) enable ((*inhigh*)EN_carryinsel);\n   method inmode(INMODE) enable ((*inhigh*)EN_inmode);\n   method opmode(OPMODE) enable ((*inhigh*)EN_opmode);\n   method a(A) enable ((*inhigh*)EN_a);\n   method b(B) enable ((*inhigh*)EN_b);\n   method c(C) enable ((*inhigh*)EN_c);\n   method d(D) enable ((*inhigh*)EN_d);\n   method acin(ACIN) enable ((*inhigh*)EN_acin);\n   method bcin(BCIN) enable ((*inhigh*)EN_bcin);\n   method carrycascin(CARRYCASCIN) enable ((*inhigh*)EN_carrycascin);\n   method carryin(CARRYIN) enable ((*inhigh*)EN_carryin);\n   method multsignin(MULTSIGNIN) enable ((*inhigh*)EN_multsignin);\n   method pcin(PCIN) enable ((*inhigh*)EN_pcin);\n\n   method cea1(CEA1) enable ((*inhigh*)EN_cea1);\n   method cea2(CEA2) enable ((*inhigh*)EN_cea2);\n   method cead(CEAD) enable ((*inhigh*)EN_cead);\n   method ceb1(CEB1) enable ((*inhigh*)EN_ceb1);\n   method ceb2(CEB2) enable ((*inhigh*)EN_ceb2);\n   method cealumode(CEALUMODE) enable ((*inhigh*)EN_cealumode);\n   method cec(CEC) enable ((*inhigh*)EN_cec);\n   method cecarryin(CECARRYIN) enable ((*inhigh*)EN_cecarryin);\n   method cectrl(CECTRL) enable ((*inhigh*)EN_cectrl);\n   method ced(CED) enable ((*inhigh*)EN_ced);\n   method ceinmode(CEINMODE) enable ((*inhigh*)EN_ceinmode);\n   method cem(CEM) enable ((*inhigh*)EN_cem);\n   method cep(CEP) enable ((*inhigh*)EN_cep);\n   schedule (alumode,carryinsel,inmode,opmode,a,b,c,d,acin,bcin,carrycascin,carryin,multsignin,pcin,cea1,cea2,cead,ceb1,ceb2,cealumode,cec,cecarryin,cectrl,ced,ceinmode,cem,cep,p)\n      CF (alumode,carryinsel,inmode,opmode,a,b,c,d,acin,bcin,carrycascin,carryin,multsignin,pcin,cea1,cea2,cead,ceb1,ceb2,cealumode,cec,cecarryin,cectrl,ced,ceinmode,cem,cep,p);\nendmodule\n\n(* synthesize *)\nmodule mkDsp48E1(Dsp48E1);\n   let dsp <- vmkDSP48E1();\n   let defaultReset <- exposeCurrentReset;\n   let optionalReset = defaultReset; // noReset\n   Wire#(Bit#(4)) alumodeWire <- mkDWire(0);\n   Reg#(Bit#(4)) alumodeReg <- mkReg(0);\n   Wire#(Bit#(3)) carryinselWire <- mkDWire(0);\n   Wire#(Bit#(5)) inmodeWire <- mkDWire(0);\n   Wire#(Bit#(7)) opmodeWire <- mkDWire(7'h20);\n   Reg#(Bit#(7)) opmode1Reg <- mkReg(0);\n   Reg#(Bit#(7)) opmode2Reg <- mkReg(0);\n   Reg#(Bit#(7)) opmode3Reg <- mkReg(0);\n   Reg#(Bit#(7)) opmode4Reg <- mkReg(0);\n\n   Wire#(Bit#(30)) aWire <- mkDWire(0);\n   Wire#(Bit#(18)) bWire <- mkDWire(0);\n   Wire#(Bit#(48)) cWire <- mkDWire(0);\n   Wire#(Bit#(25)) dWire <- mkDWire(0);\n   Reg#(Bit#(48))  c1Reg <- mkReg(0);\n   Reg#(Bit#(48))  c2Reg <- mkReg(0);\n   Reg#(Bit#(48))  c3Reg <- mkReg(0);\n\n   Wire#(Bit#(1)) ce1Wire <- mkDWire(0);\n   Reg#(Bit#(1)) ce2Reg <- mkReg(0, reset_by optionalReset);\n   Reg#(Bit#(1)) cepReg <- mkReg(0, reset_by optionalReset);\n   Wire#(Bit#(1)) lastWire <- mkDWire(0);\n   Reg#(Bit#(1))  last1Reg  <- mkReg(0, reset_by optionalReset);\n   Reg#(Bit#(1))  last2Reg  <- mkReg(0, reset_by optionalReset);\n   Reg#(Bit#(1))  last3Reg  <- mkReg(0, reset_by optionalReset);\n   Reg#(Bit#(1))  last4Reg  <- mkReg(0, reset_by optionalReset);\n   Reg#(Bit#(1))  last5Reg  <- mkReg(0, reset_by optionalReset);\n\n   Reg#(Bit#(32)) cycles <- mkReg(0);\n   rule cyclesRule;\n      cycles <= cycles+1;\n   endrule\n\n   rule clock_enable_and_reset;\n      ce2Reg <= ce1Wire;\n      cepReg <= ce2Reg;\n\n      last1Reg <= lastWire;\n      last2Reg <= last1Reg;\n      last3Reg <= last2Reg;\n      last4Reg <= last3Reg;\n      last5Reg <= last4Reg;\n\n      dsp.cea1(1); // (ce1Wire);\n      dsp.cea2(1); // (ce2Reg);\n      dsp.cead(1);\n      dsp.ceb1(1); // (ce1Wire);\n      dsp.ceb2(1); // (ce2Reg);\n      dsp.cealumode(1); // (ce1Wire);\n      dsp.cec(1);\n      dsp.cecarryin(1);\n      dsp.cectrl(1);\n      dsp.ced(1);\n      dsp.ceinmode(1);\n      dsp.cem(1);\n      dsp.cep(1); // (cepReg);\n\n   endrule\n\n   rule driveInputs;\n      opmode1Reg <= opmodeWire;\n      opmode2Reg <= opmode1Reg;\n      opmode3Reg <= opmode2Reg;\n      opmode4Reg <= opmode3Reg;\n\n      alumodeReg <= alumodeWire;\n\n      c1Reg <= cWire;\n      c2Reg <= c1Reg;\n      c3Reg <= c2Reg;\n\n      if (False)\n      if (lastWire == 1 || last1Reg == 1 || last2Reg == 1 || last3Reg == 1 || last4Reg == 1 || last5Reg == 1)\n\t $display(\"%d: a=%h b=%h c=%h p=%h lastWire=%d\", cycles, aWire, bWire, c3Reg, dsp.p(), lastWire);\n\n      dsp.alumode(alumodeReg);\n      dsp.carryinsel(carryinselWire);\n      dsp.inmode(inmodeWire);\n      dsp.opmode(opmode1Reg);\n      dsp.a(aWire);\n      dsp.b(bWire);\n      dsp.c(c1Reg);\n      //dsp.d(dWire);\n\n      dsp.acin(0);\n      dsp.bcin(0);\n      dsp.carrycascin(0);\n      dsp.carryin(0);\n      dsp.pcin(0);\n   endrule\n\n   method Action alumode(Bit#(4) v);\n      alumodeWire <= v;\n   endmethod\n   method Action carryinsel(Bit#(3) v);\n      carryinselWire <= v;\n   endmethod\n   method Action inmode(Bit#(5) v);\n      inmodeWire <= v;\n   endmethod\n   method Action opmode(Bit#(7) v);\n      opmodeWire <= v;\n   endmethod\n   method Action a(Bit#(30) v);\n      ce1Wire <= 1;\n      aWire <= v;\n   endmethod\n   method Action b(Bit#(18) v);\n      bWire <= v;\n   endmethod\n   method Action c(Bit#(48) v);\n      cWire <= v;\n   endmethod\n   method Action d(Bit#(25) v);\n      dsp.d(v);\n   endmethod\n   method Bool notEmpty();\n      return last5Reg == 1;\n   endmethod\n   method Bit#(48) p() if (last5Reg == 1);\n      return dsp.p();\n   endmethod\n   method Action deq() if (last5Reg == 1);\n   endmethod\n   method Action last(Bit#(1) v);\n      lastWire <= v;\n   endmethod\nendmodule\n`else\nmodule mkDsp48E1(Dsp48E1);\n   let defaultReset <- exposeCurrentReset;\n   let optionalReset = defaultReset; // noReset\n\n   Reg#(Bit#(48)) accumReg <- mkReg(0);\n   FIFO#(Bool) lastFifo <- mkSizedFIFO(3);\n   FIFO#(Bit#(7)) opmodeFifo <- mkSizedFIFO(3);\n   FIFOF#(Bit#(48)) pFifo <- mkSizedFIFOF(3);\n   FIFO#(Bit#(30)) aFifo <- mkSizedFIFO(3);\n   FIFO#(Bit#(18)) bFifo <- mkSizedFIFO(3);\n   FIFO#(Bit#(48)) abFifo <- mkSizedFIFO(3);\n   FIFO#(Bit#(48)) cFifo <- mkSizedFIFO(3);\n   FIFO#(Bit#(25)) dFifo <- mkSizedFIFO(3);\n\n   rule prod;\n      let a <- toGet(aFifo).get();\n      let b <- toGet(bFifo).get();\n      abFifo.enq(extend(a)*extend(b));\n   endrule\n   rule accum;\n      let last <- toGet(lastFifo).get();\n      let opmode <- toGet(opmodeFifo).get();\n      let ab <- toGet(abFifo).get();\n      let c <- toGet(cFifo).get();\n      let d <- toGet(dFifo).get();\n      \n      let accum = accumReg;\n      if (opmode == 7'h05)\n\t accum = 0;\n      if (opmode != 0)\n\t accum = accum + ab;\n      accumReg <= accum;\n      if (last)\n\t pFifo.enq(accum);\n   endrule\n\n   method Action alumode(Bit#(4) v);\n   endmethod\n   method Action carryinsel(Bit#(3) v);\n   endmethod\n   method Action inmode(Bit#(5) v);\n   endmethod\n   method Action opmode(Bit#(7) v);\n      opmodeFifo.enq(v);\n   endmethod\n   method Action a(Bit#(30) v);\n      aFifo.enq(v);\n   endmethod\n   method Action b(Bit#(18) v);\n      bFifo.enq(v);\n   endmethod\n   method Action c(Bit#(48) v);\n      cFifo.enq(v);\n   endmethod\n   method Action d(Bit#(25) v);\n      dFifo.enq(v);\n   endmethod\n   method Bool notEmpty();\n      return pFifo.notEmpty();\n   endmethod\n   method Action last(Bit#(1) v);\n      lastFifo.enq(unpack(v));\n   endmethod\n\n   method Bit#(48) p() if (pFifo.notEmpty());\n      return pFifo.first;\n   endmethod\n   method Action deq();\n      pFifo.deq();\n   endmethod\nendmodule\n`endif\n"
  },
  {
    "path": "bsv/GearboxGetPut.bsv",
    "content": "// Copyright (c) 2015 Connectal Project.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\nimport Vector::*;\nimport BuildVector::*;\nimport GetPut::*;\nimport Gearbox::*;\n\ninstance ToGet #(Gearbox #(m, 1, a), a);\n   function Get #(a) toGet (Gearbox #(m, 1, a) gb);\n      return (interface Get;\n                 method ActionValue #(a) get ();\n                    gb.deq ();\n                    return gb.first ()[0];\n                 endmethod\n              endinterface);\n   endfunction\nendinstance\n\ninstance ToGet #(Gearbox #(m, n, a), Vector#(n, a));\n   function Get #(Vector#(n,a)) toGet (Gearbox #(m, n, a) gb);\n      return (interface Get;\n                 method ActionValue #(Vector#(n,a)) get ();\n                    gb.deq ();\n                    return gb.first ();\n                 endmethod\n              endinterface);\n   endfunction\nendinstance\n\ninstance ToPut #(Gearbox #(m, n, a), Vector#(m, a));\n   function Put #(Vector#(m,a)) toPut (Gearbox #(m,n,a) gb);\n      return (interface Put;\n\t\t method Action put(Vector#(m,a) v);\n                    gb.enq (v);\n                 endmethod\n              endinterface);\n   endfunction\nendinstance\n\ninstance ToPut #(Gearbox #(1, n, a), a);\n   function Put #(a) toPut (Gearbox #(1,n,a) gb);\n      return (interface Put;\n\t\t method Action put(a v);\n                    gb.enq (vec(v));\n                 endmethod\n              endinterface);\n   endfunction\nendinstance\n"
  },
  {
    "path": "bsv/GetPutM.bsv",
    "content": "// Copyright (c) 2016 Connectal Project\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\nimport GetPut::*;\n\ntypeclass ToGetM#(type atype, type btype);\n   module toGetM#(atype m)(Get#(btype));\nendtypeclass\ntypeclass ToPutM#(type atype, type btype);\n   module toPutM#(atype m)(Put#(btype));\nendtypeclass\n"
  },
  {
    "path": "bsv/GetPutWithClocks.bsv",
    "content": "\n// Copyright (c) 2013,2014 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\nimport GetPut :: *;\nimport Connectable :: *;\nimport ClientServer :: *;\nimport Clocks :: *;\nimport ConnectalMemTypes :: *;\nimport FIFOF :: *;\nimport ConnectalBramFifo::*;\nimport Pipe :: *;\nimport Probe::*;\nimport SyncAxisFifo32x8::*;\nimport AxiStream :: *;\nimport Vector::*;\n`include \"ConnectalProjectConfig.bsv\"\n\n////////////////////////////////////////////////////////////////////////////////\n/// Typeclass Definition\n////////////////////////////////////////////////////////////////////////////////\ntypeclass ConnectableWithClocks#(type a, type b);\n   module mkConnectionWithClocks2#(a x1, b x2)(Empty);\n   module mkConnectionWithClocks#(Clock inClock, Reset inReset, Clock outClock, Reset outReset, a x1, b x2)(Empty);\nendtypeclass\n\ninstance ConnectableWithClocks#(Get#(a), Put#(a)) provisos (\n\t\t\t\t\t\t\t    Bits#(a, awidth),\n\t\t\t\t\t\t\t    Add#(1, a__, awidth),\n    Add#(b__, awidth, TMul#(TDiv#(awidth, 32), 32)),\n    Add#(c__, TDiv#(awidth, 8), TDiv#(TMul#(TDiv#(awidth, 32), 32), 8)),\n    Mul#(TDiv#(awidth, 32), 4, TDiv#(TMul#(TDiv#(awidth, 32), 32), 8))\n   );\n   module mkConnectionWithClocks#(Clock inClock, Reset inReset, Clock outClock, Reset outReset, Get#(a) in, Put#(a) out)(Empty) provisos (Bits#(a, awidth), Add#(1, a__, awidth));\n`ifndef GET_PUT_WITH_CLOCKS_USE_XILINX_FIFO\n      SyncFIFOIfc#(a) synchronizer <- mkSyncFIFO(32, inClock, inReset, outClock);\n      //FIFOF#(a) synchronizer <- mkDualClockBramFIFOF(inClock, inReset, outClock, outReset);\n      let getProbe <- mkProbe(clocked_by inClock, reset_by inReset);\n      let putProbe <- mkProbe(clocked_by outClock, reset_by outReset);\n       rule mcwc_doGet;\n           let v <- in.get();\n\t   getProbe <= v;\n\t   synchronizer.enq(v);\n       endrule\n       rule mcwc_doPut;\n\t  let v = synchronizer.first;\n\t  putProbe <= v;\n\t  synchronizer.deq;\n\t  out.put(v);\n       endrule\n`else\n      SyncAxisFifo8#(awidth) fifo <- mkSyncAxisFifo8(inClock, inReset, outClock, outReset);\n      mkConnection(in, fifo.s_axis, clocked_by inClock, reset_by inReset);\n      mkConnection(fifo.m_axis, out, clocked_by outClock, reset_by outReset);\n`endif\n   endmodule\n\n   module mkConnectionWithClocks2#(Get#(a) in, Put#(a) out)(Empty) provisos (Bits#(a, awidth), Add#(1, a__, awidth));\n      Clock inClock = clockOf(in);\n      Reset inReset = resetOf(in);\n      Clock outClock = clockOf(out);\n      Reset outReset = resetOf(out);\n\n      mkConnectionWithClocks(inClock, inReset, outClock, outReset, in, out);\n   endmodule: mkConnectionWithClocks2\nendinstance: ConnectableWithClocks\n\ninstance ConnectableWithClocks#(PipeOut#(a), Put#(a)) provisos (\n\t\t\t\t\t\t\t    Bits#(a, awidth),\n\t\t\t\t\t\t\t    Add#(1, a__, awidth),\n    Add#(b__, awidth, TMul#(TDiv#(awidth, 32), 32)),\n    Add#(c__, TDiv#(awidth, 8), TDiv#(TMul#(TDiv#(awidth, 32), 32), 8)),\n    Mul#(TDiv#(awidth, 32), 4, TDiv#(TMul#(TDiv#(awidth, 32), 32), 8))\n   );\n   module mkConnectionWithClocks#(Clock inClock, Reset inReset, Clock outClock, Reset outReset, PipeOut#(a) in, Put#(a) out)(Empty) provisos (Bits#(a, awidth), Add#(1, a__, awidth));\n`ifndef GET_PUT_WITH_CLOCKS_USE_XILINX_FIFO\n      SyncFIFOIfc#(a) synchronizer <- mkSyncFIFO(8, inClock, inReset, outClock);\n      //FIFOF#(a) synchronizer <- mkDualClockBramFIFOF(inClock, inReset, outClock, outReset);\n      let deqProbe <- mkProbe(clocked_by inClock, reset_by inReset);\n      let enqProbe <- mkProbe(clocked_by outClock, reset_by outReset);\n       rule mcwc_doGet;\n          let v = in.first;\n\t  in.deq();\n\t  deqProbe <= v;\n\t   synchronizer.enq(v);\n       endrule\n       rule mcwc_doPut;\n\t  let v = synchronizer.first;\n\t  enqProbe <= v;\n\t  synchronizer.deq;\n\t  out.put(v);\n       endrule\n`else\n      SyncAxisFifo8#(awidth) fifo <- mkSyncAxisFifo8(inClock, inReset, outClock, outReset);\n      mkConnection(in, fifo.s_axis, clocked_by inClock, reset_by inReset);\n      mkConnection(fifo.m_axis, out, clocked_by outClock, reset_by outReset);\n`endif\n   endmodule\n\n   module mkConnectionWithClocks2#(PipeOut#(a) in, Put#(a) out)(Empty) provisos (Bits#(a, awidth), Add#(1, a__, awidth));\n      Clock inClock = clockOf(in);\n      Reset inReset = resetOf(in);\n      Clock outClock = clockOf(out);\n      Reset outReset = resetOf(out);\n\n      mkConnectionWithClocks(inClock, inReset, outClock, outReset, in, out);\n   endmodule: mkConnectionWithClocks2\nendinstance: ConnectableWithClocks\n\ninstance ConnectableWithClocks#(Get#(a), PipeIn#(a)) provisos (\n\t\t\t\t\t\t\t    Bits#(a, awidth),\n\t\t\t\t\t\t\t    Add#(1, a__, awidth),\n    Add#(b__, awidth, TMul#(TDiv#(awidth, 32), 32)),\n    Add#(c__, TDiv#(awidth, 8), TDiv#(TMul#(TDiv#(awidth, 32), 32), 8)),\n    Mul#(TDiv#(awidth, 32), 4, TDiv#(TMul#(TDiv#(awidth, 32), 32), 8))\n   );\n   module mkConnectionWithClocks#(Clock inClock, Reset inReset, Clock outClock, Reset outReset, Get#(a) in, PipeIn#(a) out)(Empty) provisos (Bits#(a, awidth), Add#(1, a__, awidth));\n`ifndef GET_PUT_WITH_CLOCKS_USE_XILINX_FIFO\n      SyncFIFOIfc#(a) synchronizer <- mkSyncFIFO(8, inClock, inReset, outClock);\n      //FIFOF#(a) synchronizer <- mkDualClockBramFIFOF(inClock, inReset, outClock, outReset);\n      let getProbe <- mkProbe(clocked_by inClock, reset_by inReset);\n      let putProbe <- mkProbe(clocked_by outClock, reset_by outReset);\n       rule mcwc_doGet;\n           let v <- in.get();\n\t  getProbe <= v;\n\t   synchronizer.enq(v);\n       endrule\n       rule mcwc_doEnq;\n\t  let v = synchronizer.first;\n\t  synchronizer.deq;\n\t  putProbe <= v;\n\t  out.enq(v);\n       endrule\n`else\n      SyncAxisFifo8#(awidth) fifo <- mkSyncAxisFifo8(inClock, inReset, outClock, outReset);\n      mkConnection(in, fifo.s_axis, clocked_by inClock, reset_by inReset);\n      mkConnection(fifo.m_axis, out, clocked_by outClock, reset_by outReset);\n`endif\n   endmodule\n\n   module mkConnectionWithClocks2#(Get#(a) in, PipeIn#(a) out)(Empty) provisos (Bits#(a, awidth), Add#(1, a__, awidth));\n      Clock inClock = clockOf(in);\n      Reset inReset = resetOf(in);\n      Clock outClock = clockOf(out);\n      Reset outReset = resetOf(out);\n\n      mkConnectionWithClocks(inClock, inReset, outClock, outReset, in, out);\n   endmodule: mkConnectionWithClocks2\nendinstance: ConnectableWithClocks\n\ninstance ConnectableWithClocks#(Client#(a,b), Server#(a,b))\n   provisos (Bits#(a, awidth),\n      Bits#(b, bwidth),\n      Add#(1, a__, awidth),\n      Add#(1, b__, bwidth),\n\n      Add#(c__, TDiv#(awidth, 8), TDiv#(TMul#(TDiv#(awidth, 32), 32), 8)),\n      Add#(d__, TDiv#(bwidth, 8), TDiv#(TMul#(TDiv#(bwidth, 32), 32), 8)),\n      Add#(e__, awidth, TMul#(TDiv#(awidth, 32), 32)),\n      Add#(f__, bwidth, TMul#(TDiv#(bwidth, 32), 32)),\n      Mul#(TDiv#(awidth, 32), 4, TDiv#(TMul#(TDiv#(awidth, 32), 32), 8)),\n      Mul#(TDiv#(bwidth, 32), 4, TDiv#(TMul#(TDiv#(bwidth, 32), 32), 8))\n      );\n   module mkConnectionWithClocks#(Clock inClock, Reset inReset, Clock outClock, Reset outReset, Client#(a,b) client, Server#(a,b) server)(Empty)\n      provisos (ConnectableWithClocks#(Get#(a), Put#(a)),\n\t\tConnectableWithClocks#(Get#(b), Put#(b)),\n\t\tBits#(a, awidth),\n\t\tBits#(b, bwidth));\n      let reqCnx <- mkConnectionWithClocks(inClock, inReset, outClock, outReset, client.request, server.request);\n      let respCnx <- mkConnectionWithClocks(outClock, outReset, inClock, inReset, server.response, client.response);\n   endmodule\n   module mkConnectionWithClocks2#(Client#(a,b) client, Server#(a,b) server)(Empty)\n      provisos (ConnectableWithClocks#(Get#(a), Put#(a)),\n\t\tConnectableWithClocks#(Get#(b), Put#(b)),\n\t\tBits#(a, awidth),\n\t\tBits#(b, bwidth));\n      Clock inClock = clockOf(client);\n      Reset inReset = resetOf(client);\n      Clock outClock = clockOf(server);\n      Reset outReset = resetOf(server);\n\n      mkConnectionWithClocks(inClock, inReset, outClock, outReset, client, server);\n   endmodule\nendinstance\n\ninstance ConnectableWithClocks#(PhysMemReadClient#(addrWidth, dataWidth),\n\t\t\t\tPhysMemReadServer#(addrWidth, dataWidth))\n   provisos (\n      ConnectableWithClocks#(Get#(PhysMemRequest#(addrWidth,dataWidth)),Put#(PhysMemRequest#(addrWidth,dataWidth))),\n      ConnectableWithClocks#(Get#(MemData#(dataWidth)),Put#(MemData#(dataWidth)))\n      );\n   module mkConnectionWithClocks#(Clock inClock, Reset inReset, Clock outClock, Reset outReset,\n\t\t\t\t   PhysMemReadClient#(addrWidth, dataWidth) client,\n\t\t\t\t   PhysMemReadServer#(addrWidth, dataWidth) server)(Empty);\n      let reqCnx <- mkConnectionWithClocks(inClock, inReset, outClock, outReset, client.readReq, server.readReq);\n      let dataCnx <- mkConnectionWithClocks(outClock, outReset, inClock, inReset, server.readData, client.readData);\n   endmodule\n   module mkConnectionWithClocks2#(PhysMemReadClient#(addrWidth, dataWidth) client,\n\t\t\t\t  PhysMemReadServer#(addrWidth, dataWidth) server)(Empty);\n      Clock inClock = clockOf(client);\n      Reset inReset = resetOf(client);\n      Clock outClock = clockOf(server);\n      Reset outReset = resetOf(server);\n      mkConnectionWithClocks(inClock, inReset, outClock, outReset, client, server);\n   endmodule\nendinstance\n\ninstance ConnectableWithClocks#(PhysMemWriteClient#(addrWidth, dataWidth),\n\t\t\t\tPhysMemWriteServer#(addrWidth, dataWidth))\n   provisos (\n    ConnectableWithClocks#(Get#(PhysMemRequest#(addrWidth, dataWidth)), Put#(PhysMemRequest#(addrWidth, dataWidth))),\n    ConnectableWithClocks#(Get#(MemData#(dataWidth)),Put#(MemData#(dataWidth)))\n      );\n\n   module mkConnectionWithClocks#(Clock inClock, Reset inReset, Clock outClock, Reset outReset, \n\t\t\t\t   PhysMemWriteClient#(addrWidth, dataWidth) client,\n\t\t\t\t   PhysMemWriteServer#(addrWidth, dataWidth) server)(Empty);\n      let reqCnx <- mkConnectionWithClocks(inClock, inReset, outClock, outReset, client.writeReq, server.writeReq);\n      let dataCnx <- mkConnectionWithClocks(inClock, inReset, outClock, outReset, client.writeData, server.writeData);\n      let doneCnx <- mkConnectionWithClocks(outClock, outReset, inClock, inReset, server.writeDone, client.writeDone);\n   endmodule\n   module mkConnectionWithClocks2#(PhysMemWriteClient#(addrWidth, dataWidth) client,\n\t\t\t\t  PhysMemWriteServer#(addrWidth, dataWidth) server)(Empty);\n      Clock inClock = clockOf(client);\n      Reset inReset = resetOf(client);\n      Clock outClock = clockOf(server);\n      Reset outReset = resetOf(server);\n      mkConnectionWithClocks(inClock, inReset, outClock, outReset, client, server);\n   endmodule\nendinstance\n\ninstance ConnectableWithClocks#(PhysMemMaster#(addrWidth, dataWidth), PhysMemSlave#(addrWidth, dataWidth))\n   provisos (\n    ConnectableWithClocks#(PhysMemWriteClient#(addrWidth,dataWidth),PhysMemWriteServer#(addrWidth,dataWidth))\n      );\n   module mkConnectionWithClocks#(Clock inClock, Reset inReset, Clock outClock, Reset outReset, \n\t\t\t\t   PhysMemMaster#(addrWidth, dataWidth) client,\n\t\t\t\t   PhysMemSlave#(addrWidth, dataWidth) server)(Empty);\n      let readCnx <- mkConnectionWithClocks(inClock, inReset, outClock, outReset, client.read_client, server.read_server);\n      let writeCnx <- mkConnectionWithClocks(inClock, inReset, outClock, outReset, client.write_client, server.write_server);\n   endmodule\n   module mkConnectionWithClocks2#(PhysMemMaster#(addrWidth, dataWidth) client,\n\t\t\t\t  PhysMemSlave#(addrWidth, dataWidth) server)(Empty);\n      Clock inClock = clockOf(client);\n      Reset inReset = resetOf(client);\n      Clock outClock = clockOf(server);\n      Reset outReset = resetOf(server);\n      mkConnectionWithClocks(inClock, inReset, outClock, outReset, client, server);\n   endmodule\nendinstance\n\nmodule mkClockBinder#(a ifc) (a);\n   return ifc;\nendmodule\n\n\ntypeclass ConnectableWithGearbox#(type a, type b);\n   module mkConnectionWithGearbox#(Clock inClock, Reset inReset, Clock outClock, Reset outReset, a x1, b x2)(Empty);\nendtypeclass\n\n\ninstance ConnectableWithGearbox#(PhysMemMaster#(addrWidth, masterdw), PhysMemSlave#(addrWidth, slavedw))\n   provisos (\n      Add#(a__, slavedw, masterdw), // master is wider than slave, i.e. master is at slower clock freq\n      // Div#(slavedw, 32, slavedw),\n      // Div#(masterdw, 32, masterdw),\n      // Add#(TMul#(slavewords, 32), 0, slaveword), // 32-bit word aligned\n      // Add#(TMul#(masterwords, 32), 0, masterword), // 32-bit word aligned\n      // Div#(masterdw, slavedw, ratio),\n      // Add#(0, TMul#(ratio, slavedw), masterdw), // ratio is integer      \n      // Add#(0, TExp#(TLog#(ratio)), ratio), // ratio is power of two\n      Bits#(Vector#(ratio, Bit#(slavedw)), masterdw),\n      ConnectableWithClocks#(Get#(PhysMemRequest#(addrWidth, slavedw)), Put#(PhysMemRequest#(addrWidth,slavedw))),\n      ConnectableWithClocks#(Get#(PhysMemRequest#(addrWidth, masterdw)), Put#(PhysMemRequest#(addrWidth,masterdw))),\n      ConnectableWithClocks#(Get#(MemData#(masterdw)), Put#(MemData#(masterdw))),\n      ConnectableWithClocks#(Get#(MemData#(slavedw)), Put#(MemData#(slavedw)))\n      );\n   \n   module mkConnectionWithGearbox#(Clock inClock, Reset inReset, Clock outClock, Reset outReset,\n                                   PhysMemMaster#(addrWidth, masterdw) client,\n                                   PhysMemSlave#(addrWidth, slavedw) server)(Empty);\n   \n\n      // Gearbox#(1, ratio, Bit#(slavedw)) readGB <- mk1toNGearbox(outClock, outReset, inClock, inReset);\n      // Gearbox#(ratio, 1, Bit#(slavedw)) writeGB <- mkNto1Gearbox(inClock, inReset, outClock, outReset);\n\n      \n      `ifndef BYTE_ENABLES\n      let rdReqGet = (interface Get#(PhysMemRequest#(addrWidth,slavedw));\n                         method ActionValue#(PhysMemRequest#(addrWidth,slavedw)) get;\n                            let req <- client.read_client.readReq.get;\n                            return PhysMemRequest{addr: req.addr, burstLen: req.burstLen, tag: req.tag};\n                         endmethod\n                      endinterface);\n   \n      let wrReqGet = (interface Get#(PhysMemRequest#(addrWidth,slavedw));\n                         method ActionValue#(PhysMemRequest#(addrWidth,slavedw)) get;\n                            let req <- client.write_client.writeReq.get;\n                            return PhysMemRequest{addr: req.addr, burstLen: req.burstLen, tag: req.tag};\n                         endmethod\n                      endinterface);\n   \n      `endif\n   \n      Reg#(Bit#(TLog#(ratio))) rdBeats <- mkReg(0,  clocked_by inClock, reset_by inReset);\n      FIFOF#(MemData#(slavedw)) rdDataQ <- mkFIFOF(clocked_by inClock, reset_by inReset);\n      \n      Reg#(Bit#(masterdw)) rdData <- mkRegU(clocked_by inClock, reset_by inReset);\n   \n      rule doRdData;\n         rdBeats <= rdBeats + 1;\n         \n         let rdPayload <- toGet(rdDataQ).get;\n         \n         let newReadData = truncateLSB({rdPayload.data,rdData});\n         \n         rdData <= newReadData;\n         \n         if ( rdBeats == -1 ) \n            client.read_client.readData.put(MemData{data:newReadData, tag: rdPayload.tag, last:rdPayload.last});\n      endrule\n   \n      Reg#(Bit#(TLog#(ratio))) wrBeats <- mkReg(0, clocked_by outClock, reset_by outReset);\n      FIFOF#(MemData#(masterdw)) wrDataQ <- mkFIFOF(clocked_by outClock, reset_by outReset);\n      \n      //Reg#(MemData#(masterdw)) wrData <- mkRegU(clocked_by outClock, reset_by outReset);\n   \n   \n      rule doWrData;\n         wrBeats <= wrBeats + 1;\n         \n         let currMemData = wrDataQ.first;\n         if ( wrBeats == -1 ) begin\n            wrDataQ.deq;\n         end\n         \n         Vector#(ratio, Bit#(slavedw)) payload = unpack(currMemData.data);\n         \n         server.write_server.writeData.put(MemData{data:payload[wrBeats], tag: currMemData.tag, last: currMemData.last && wrBeats == -1});\n      endrule\n   \n\n\n      GetPutWithClocks::mkConnectionWithClocks(inClock, inReset, outClock, outReset,\n                             client.write_client.writeData, toPut(wrDataQ));\n\n      GetPutWithClocks::mkConnectionWithClocks(outClock, outReset, inClock, inReset,\n                             server.read_server.readData, toPut(rdDataQ));\n\n\n      GetPutWithClocks::mkConnectionWithClocks(inClock, inReset, outClock, outReset,\n                             rdReqGet, server.read_server.readReq);\n      GetPutWithClocks::mkConnectionWithClocks(inClock, inReset, outClock, outReset,\n                             wrReqGet, server.write_server.writeReq);\n      GetPutWithClocks::mkConnectionWithClocks(outClock, outReset, inClock, inReset, \n                             server.write_server.writeDone, client.write_client.writeDone);\n   \n   \n      // rule doReadDataEnq;\n      //    let v <- server.read_server.readData.get;\n      //    readGB.enq(unpack(v));\n      // endrule\n   \n      // rule doReadDataDeq;\n      //    let v = readGB.first;\n      //    readGB.deq;\n      //    client.read_client.readData.put(pack(v));\n      // endrule\n\n      // rule doWriteDataEnq;\n      //    let v <- client.write_client.writeData.get;\n      //    writeGB.enq(unpack(v));\n      // endrule\n   \n      // rule doWriteDataDeq;\n      //    let v = writeGB.first;\n      //    writeGB.deq;\n      //    server.write_server.writeData.put(pack(v));\n      // endrule\n   endmodule\n   \nendinstance\n"
  },
  {
    "path": "bsv/HostInterface.bsv",
    "content": "// Copyright (c) 2014 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\nimport ConnectalConfig::*;\n`include \"ConnectalProjectConfig.bsv\"\n\n////////////////////////////// common /////////////////////////////////\n\n\n////////////////////////////// Bsim /////////////////////////////////\n`ifdef BsimHostInterface\n\nimport Vector            :: *;\nimport AxiMasterSlave    :: *;\nimport ConnectalMemTypes          :: *;\n\n// this interface should allow for different master and slave bus paraters;\t\t \ninterface BsimHost#(numeric type clientAddrWidth, numeric type clientBusWidth, numeric type clientIdWidth,  \n\t\t    numeric type serverAddrWidth, numeric type serverBusWidth, numeric type serverIdWidth,\n\t\t    numeric type nSlaves);\n   interface PhysMemMaster#(clientAddrWidth, clientBusWidth)  mem_client;\n   interface Vector#(nSlaves,PhysMemSlave#(serverAddrWidth,  serverBusWidth))  mem_servers;\n   interface Clock derivedClock;\n   interface Reset derivedReset;\nendinterface\n\ntypedef BsimHost#(32,32,12,40,DataBusWidth,6,NumberOfMasters) HostInterface;\n`endif\n\n////////////////////////////// Xsim /////////////////////////////////\n`ifdef XsimHostInterface\n\nimport Vector            :: *;\nimport AxiMasterSlave    :: *;\nimport ConnectalMemTypes          :: *;\n\n// this interface should allow for different master and slave bus paraters;\ninterface XsimHost;\n   interface Clock derivedClock;\n   interface Reset derivedReset;\n   interface Clock tsys_clk_200mhz_buf;\nendinterface\n\nmodule  mkXsimHost#(Clock derivedClock, Reset derivedReset, Clock sys_clk)(XsimHost);\n   interface derivedClock = derivedClock;\n   interface derivedReset = derivedReset;\n   interface tsys_clk_200mhz_buf = sys_clk;\nendmodule\n\ntypedef XsimHost HostInterface;\n`endif\n\n////////////////////////////// PciE /////////////////////////////////\n`ifndef PcieHostIF\n`ifdef PcieHostInterface\n`define PcieHostIF\n`endif\n`endif\n\n`ifdef PcieHostIF\n\n`ifdef PCIE3\ntypedef TMin#(DataBusWidth, 128) PcieDataBusWidth;\n`else\ntypedef TMin#(DataBusWidth, 128) PcieDataBusWidth;\n`endif\n\n\nimport Vector            :: *;\nimport GetPut            :: *;\nimport ClientServer      :: *;\nimport BRAM              :: *;\nimport PCIE              :: *;\nimport Bscan             :: *;\nimport PcieCsr           :: *;\nimport PcieTracer        :: *;\nimport ConnectalMemTypes          :: *;\nimport Pipe              :: *;\n`ifndef SIMULATION\n`ifdef XILINX\n`ifdef PCIE1\nimport PCIEWRAPPER       :: *;\nimport Pcie1EndpointX7   :: *;\n`endif // pcie1\n`ifdef PCIE2\nimport PCIEWRAPPER2       :: *;\nimport Pcie2EndpointX7 :: *;\n`endif // pcie2\n`ifdef PCIE3\n`ifdef XilinxUltrascale\nimport PCIEWRAPPER3u     ::*;\n`else\nimport PCIEWRAPPER3      :: *;\n`endif\nimport Pcie3EndpointX7   :: *;\n`endif\n`endif\n`ifdef ALTERA\nimport PcieEndpointS5    :: *;\n`endif\n`endif\ntypedef 40 PciePhysAddrWidth;\ninterface PcieHost#(numeric type dsz, numeric type nSlaves);\n   interface Vector#(16,ReadOnly_MSIX_Entry)     msixEntry;\n   interface PhysMemMaster#(32,32)                   master;\n   interface Vector#(nSlaves,PhysMemSlave#(PciePhysAddrWidth,dsz))  slave;\n   interface Put#(Tuple2#(Bit#(64),Bit#(32)))    interruptRequest;\n`ifdef PCIE3\n   interface Client#(TLPData#(16), TLPData#(16)) pcir;\n   interface Client#(TLPData#(16), TLPData#(16)) pcic;\n   interface PipeIn#(Bit#(64)) changes;\n`else\n   interface Client#(TLPData#(16), TLPData#(16)) pci;\n   interface PipeIn#(Bit#(64)) changes;\n`endif\n   interface Put#(TimestampedTlpData) trace;\n`ifdef PCIE_BSCAN\n   interface BscanTop bscanif;\n`else\n`ifdef PCIE_TRACE_PORT\n   interface BRAMServer#(Bit#(TAdd#(TlpTraceAddrSize,1)), TimestampedTlpData) traceBramServer;\n`endif\n`endif\nendinterface\n\ninterface PcieHostTop;\n   interface PcieHost#(PcieDataBusWidth, NumberOfMasters) tpciehost;\n`ifdef PCIE_CHANGES_HOSTIF\n   interface PipeOut#(Bit#(64)) tchanges;\n`endif\n`ifdef XILINX\n`ifdef XILINX_SYS_CLK\n   interface Clock tsys_clk_200mhz;\n   interface Clock tsys_clk_200mhz_buf;\n`ifdef VirtexUltrascalePlus\n   interface Clock tsys_clk_300mhz;\n   interface Clock tsys_clk_300mhz_buf;\n   interface Clock tsys_clk1_250mhz;\n   interface Clock tsys_clk1_250mhz_buf;\n   interface Clock tsys_clk2_250mhz;\n   interface Clock tsys_clk2_250mhz_buf;\n`else\n`ifdef VirtexUltrascale\n   interface Clock tsys_clk1_300mhz;\n   interface Clock tsys_clk1_300mhz_buf;\n   interface Clock tsys_clk2_300mhz;\n   interface Clock tsys_clk2_300mhz_buf;\n`endif\n`endif\n`endif\n   interface Clock tpci_clk_100mhz_buf;\n   interface PcieEndpointX7#(PcieLanes) tep7;\n`endif\n`ifdef ALTERA\n   interface PcieEndpointS5#(PcieLanes) tep7;\n`endif\n   interface Clock pcieClock;\n   interface Reset pcieReset;\n   interface Clock portalClock;\n   interface Reset portalReset;\n   interface Clock derivedClock;\n   interface Reset derivedReset;\nendinterface\n`endif\n\n`ifdef PcieHostInterface\ntypedef PcieHostTop HostInterface;\n`endif\n\n////////////////////////////// Zynq /////////////////////////////////\n`ifdef ZynqHostInterface\nimport PS7LIB::*;\nimport Bscan::*;\n\ninterface HostInterface;\n    interface PS7 ps7;\n    interface Clock portalClock;\n    interface Reset portalReset;\n    interface Clock derivedClock;\n    interface Reset derivedReset;\n    interface BscanTop bscan;\n`ifdef XILINX_SYS_CLK\n   interface Clock tsys_clk_200mhz;\n   interface Clock tsys_clk_200mhz_buf;\n`ifdef VirtexUltrascale\n   interface Clock tsys_clk1_300mhz;\n   interface Clock tsys_clk1_300mhz_buf;\n   interface Clock tsys_clk2_300mhz;\n   interface Clock tsys_clk2_300mhz_buf;\n`endif\n`endif\nendinterface\n\n//export PS7LIB::*;\n//export BscanTop;\n//export HostInterface;\n//export DataBusWidth;\n//export NumberOfMasters;\n//export PhysAddrWidth;\n`endif\n"
  },
  {
    "path": "bsv/LinkerLib.bsv",
    "content": "// Copyright (c) 2015 The Connectal Project\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\nimport GetPut::*;\n// Generic definitions that should go in a shared library.\n//typeclass InverseIFC#(type a, type b)\n  //dependencies (a determines b,\n                //b determines a);\n//endtypeclass\n\ninterface GetInverter#(type a);\n   interface Get#(a) mod;\n   interface Put#(a) inverse;\nendinterface\n\ninterface PutInverter#(type a);\n   interface Put#(a) mod;\n   interface Get#(a) inverse;\nendinterface\ninterface LinkInverter#(type a);\n   interface Put#(a) mod;\n   interface Get#(a) inverse;\n   method Bool modReady();\n   method Bool inverseReady();\nendinterface\n\nimport \"BVI\" GetInverter =\nmodule mkGetInverterBvi(GetInverter#(Bit#(asz)));\n   let asz = valueOf(asz);\n   parameter DATA_WIDTH = asz;\n   default_clock (CLK);\n   default_reset (RST);\n   interface Get mod;\n      method get get() enable(EN_get) ready (RDY_get);\n   endinterface\n   interface Put inverse;\n      method put(put) enable (EN_put) ready (RDY_put);\n   endinterface\n   schedule (mod.get, inverse.put) CF (mod.get, inverse.put);\nendmodule\nmodule mkGetInverter(GetInverter#(a)) provisos (Bits#(a, asz));\n   let inverter <- mkGetInverterBvi();\n   interface Get mod;\n      method ActionValue#(a) get();\n\t let v <- inverter.mod.get();\n\t return unpack(v);\n      endmethod\n   endinterface\n   interface Put inverse;\n      method Action put(a v);\n\t inverter.inverse.put(pack(v));\n      endmethod\n   endinterface\nendmodule\n\nimport \"BVI\" PutInverter =\nmodule mkPutInverterBvi(PutInverter#(Bit#(asz)));\n   let asz = valueOf(asz);\n   parameter DATA_WIDTH = asz;\n   default_clock (CLK);\n   default_reset (RST);\n   interface Put mod;\n      method put(put) enable(EN_put) ready (RDY_put);\n   endinterface\n   interface Get inverse;\n      method get get() enable (EN_get) ready (RDY_get);\n   endinterface\n   schedule (mod.put, inverse.get) CF (mod.put, inverse.get);\nendmodule\nmodule mkPutInverter(PutInverter#(a)) provisos (Bits#(a, asz));\n   let inverter <- mkPutInverterBvi();\n   interface Put mod;\n      method Action put(a v);\n\t inverter.mod.put(pack(v));\n      endmethod\n   endinterface\n   interface Get inverse;\n      method ActionValue#(a) get();\n\t let v <- inverter.inverse.get();\n\t return unpack(v);\n      endmethod\n   endinterface\nendmodule\n\nimport \"BVI\" LinkInverter =\nmodule mkLinkInverterBvi(LinkInverter#(Bit#(asz)));\n   let asz = valueOf(asz);\n   parameter DATA_WIDTH = asz;\n   default_clock (CLK);\n   default_reset (RST);\n   interface Put mod;\n      method put(put) enable(EN_put) ready (RDY_put);\n   endinterface\n   interface Get inverse;\n      method get get() enable (EN_get) ready (RDY_get);\n   endinterface\n   method modReady modReady();\n   method inverseReady inverseReady();\n   schedule (mod.put, inverse.get, modReady, inverseReady) CF (mod.put, inverse.get, modReady, inverseReady);\nendmodule\nmodule mkLinkInverter(LinkInverter#(a)) provisos (Bits#(a, asz));\n   let inverter <- mkLinkInverterBvi();\n   interface Put mod;\n      method Action put(a v);\n\t inverter.mod.put(pack(v));\n      endmethod\n   endinterface\n   interface Get inverse;\n      method ActionValue#(a) get();\n\t let v <- inverter.inverse.get();\n\t return unpack(v);\n      endmethod\n   endinterface\n   method Bool modReady();\n      return inverter.modReady();\n   endmethod\n   method Bool inverseReady();\n      return inverter.inverseReady();\n   endmethod\nendmodule\n"
  },
  {
    "path": "bsv/MIFO.bsv",
    "content": "\n// Copyright (c) 2014 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\nimport Vector::*;\nimport Arith ::*;\nimport FIFOF ::*;\nimport GetPut::*;\nimport Pipe  ::*;\nimport MIMO  ::*; //LUInt\n\ninterface MIFO#(numeric type max_in, numeric type n_out, numeric type size, type t);\n   method    Action                      enq(LUInt#(max_in) count, Vector#(max_in, t) data);\n   method    Vector#(n_out, t)           first();\n   method    Action                      deq();\n      \n   (* always_ready *)\n   method    Bool                        enqReady();\n   (* always_ready *)\n   method    Bool                        deqReady();\nendinterface\n   \ninstance ToGet #(MIFO #(max_in, n_out, size, a), Vector#(n_out, a));\n   function Get #(Vector#(n_out, a)) toGet (MIFO #(max_in, n_out, size, a) mifo);\n      return (interface Get;\n                 method ActionValue #(Vector#(n_out, a)) get ();\n                    mifo.deq ();\n                    return mifo.first ();\n                 endmethod\n              endinterface);\n   endfunction\nendinstance\n\nmodule mkMIFO(MIFO#(max_in, n_out, size, t))\n   provisos (Log#(max_in, max_in_sz),\n\t     Log#(n_out, n_out_sz),\n\t     Add#(n_out, a__, max_in),\n\t     Add#(1, b__, n_out),\n\t     Bits#(t, c__),\n\t     Bits#(Vector#(max_in, t), d__),\n\t     Add#(e__, max_in_sz, TLog#(TAdd#(max_in, 1))),\n      Add#(f__, 2, max_in_sz)\n      );\n   FIFOF#(Vector#(max_in, t))     inFifo <- mkFIFOF();\n   FIFOF#(UInt#(max_in_sz))      posFifo <- mkFIFOF();\n   FIFOF#(LUInt#(max_in))    inCountFifo <- mkFIFOF();\n   FIFOF#(Bit#(max_in))           weFifo <- mkFIFOF();\n   Vector#(max_in, FIFOF#(t)) fifos      <- replicateM(mkSizedFIFOF(valueOf(size)));\n\n   Reg#(UInt#(max_in_sz))            inPos <- mkReg(0);\n   Reg#(UInt#(max_in_sz))            outPos <- mkReg(0);\n\n   LUInt#(max_in) i_max_in = fromInteger(valueOf(max_in));\n\n   let verbose = False;\n\n   function a fifoFirst(FIFOF#(a) fifo); if (fifo.notEmpty()) return fifo.first(); else return ?; endfunction\n   function Bool fifoNotEmpty(FIFOF#(a) fifo); return fifo.notEmpty(); endfunction\n   function Bool fifoNotFull(FIFOF#(a) fifo); return fifo.notFull(); endfunction\n\n   FIFOF#(Bool) checkInFifo <- mkFIFOF();\n   rule checkin if (verbose);\n      let v <- toGet(checkInFifo).get();\n      $display(\"checkIn: inPos=%d outPos=%d notEmpties: %h notFulls: %h values: %h\",\n\t       inPos, outPos, map(fifoNotEmpty, fifos), map(fifoNotFull, fifos), map(fifoFirst, fifos));\n   endrule\n\n   rule tofifos;\n      let values = inFifo.first;\n      let count  = inCountFifo.first;\n      let pos    = posFifo.first;\n      let we     = weFifo.first;\n\n\n      Bool ready = True;\n      // for (Integer i = 0; i < valueOf(max_in); i = i+1) begin\n      // \t if (we[i] == 1)\n      // \t    ready = ready && fifos[i].notFull();\n      // end\n      if (ready) begin\n\t for (Integer i = 0; i < valueOf(max_in); i = i+1) begin\n\t    if (we[i] == 1)\n\t       fifos[i].enq(values[i]);\n\t end\n\t inFifo.deq();\n\t inCountFifo.deq();\n\t weFifo.deq();\n\t posFifo.deq();\n\n\t if (verbose) begin\n\t    $display(\"tofifos: pos=%d count=%d we=%h\", pos, count, we, \" values: %h notFull: %h\", values, map(fifoNotFull, fifos));\n\t    checkInFifo.enq(True);\n\t end\n      end\n   endrule\n\n   function Bool deqReadyInternal();\n      LUInt#(max_in) rot = i_max_in - extend(outPos);\n      Vector#(n_out, Bool) notEmpties = take(rotateBy(map(fifoNotEmpty, fifos), truncate(rot)));\n      return fold(booland, notEmpties);\n   endfunction\n\n   FIFOF#(Bool) checkFifo <- mkFIFOF();\n   rule check if (verbose);\n      let v <- toGet(checkFifo).get();\n      LUInt#(max_in) rot = i_max_in - extend(outPos);\n      Vector#(max_in, Bool) allNotEmpties = map(fifoNotEmpty, fifos);\n      Vector#(max_in, Bool) notEmpties = rotateBy(map(fifoNotEmpty, fifos), truncate(rot));\n      Vector#(4, Bool) testv = replicate(False);\n      testv[outPos] = True;\n      UInt#(2) testpos = 3 - truncate(outPos);\n      Vector#(4, Bool) rotatedTestv = rotateBy(testv, 1);\n      if (verbose)\n      $display(\"check outPos: \", outPos, \" notEmpty: \", fifos[outPos].notEmpty(),\n\t \" notEmpties: \", notEmpties, \" allNotEmpties: %h\", allNotEmpties);\n   endrule\n\n   method    Action                      enq(LUInt#(max_in) count, Vector#(max_in, t) data);\n      function Bool lessThanCount(Integer i); return fromInteger(i) < count; endfunction\n      Vector#(max_in, Bool) we = genWith(lessThanCount);\n      inFifo.enq(rotateBy(data, inPos));\n      inCountFifo.enq(count);\n      weFifo.enq(pack(rotateBy(we, inPos)));\n      posFifo.enq(inPos);\n      inPos <= truncate((extend(inPos) + count) % i_max_in);\n\n      if (verbose) $display(\"enq: inPos=%d we=%h\", inPos, we);\n   endmethod\n\n   method    Vector#(n_out, t)           first if (deqReadyInternal());\n      function t firstN(Integer i);\n\t return fifos[(extend(outPos) + fromInteger(i)) % i_max_in].first;\n      endfunction\n      return genWith(firstN);\n   endmethod\n\n   method    Action                      deq() if (deqReadyInternal());\n      function t firstN(Integer i);\n\t return fifos[(extend(outPos) + fromInteger(i)) % i_max_in].first;\n      endfunction\n      for (Integer i = 0; i < valueOf(n_out); i = i+1)\n\t fifos[(extend(outPos) + fromInteger(i)) % i_max_in].deq();\n      UInt#(max_in_sz) nextOutPos = truncate((extend(outPos) + fromInteger(valueOf(n_out))) % i_max_in);\n      outPos <= nextOutPos;\n\n      if (verbose) begin\n\t LUInt#(max_in) rot = i_max_in - extend(outPos);\n\t Vector#(n_out, t) v = genWith(firstN);\n\t Vector#(max_in, Bool) allNotEmpties = rotateBy(map(fifoNotEmpty, fifos), truncate(rot));\n\t Vector#(n_out, Bool) notEmpties = take(map(fifoNotEmpty, rotateBy(fifos, truncate(rot))));\n\t $display(\"first: \", v, \" outPos: \", outPos, \" nextOutPos: \", nextOutPos, \" nextNotEmpty: \", fifos[nextOutPos].notEmpty(),\n\t    \" notEmpties: \", notEmpties, \" allNotEmpties: %h\", allNotEmpties);\n\t checkFifo.enq(True);\n      end\n   endmethod\n      \n   method    Bool                        enqReady = inFifo.notFull;\n\n   method    Bool                        deqReady = deqReadyInternal;\n\nendmodule\n\n\ninterface FIMO#(numeric type n_in, numeric type max_out, numeric type size, type t);\n   interface PipeIn#(Vector#(n_in, t)) in;\n   interface Vector#(TAdd#(max_out,1), PipeOut#(Vector#(max_out, t))) out;\nendinterface\n\nmodule mkFIMO(FIMO#(n_in, max_out, size, t))\n   provisos (Log#(n_in, n_in_sz),\n\t     Log#(max_out, max_out_sz),\n\t     Add#(n_in, a__, max_out),\n\t     Add#(1, b__, max_out),\n\t     Bits#(t, c__),\n\t     Add#(d__, max_out_sz, TLog#(TAdd#(max_out, 1)))\n      );\n   FIFOF#(Vector#(max_out, t))     inFifo <- mkFIFOF();\n   FIFOF#(UInt#(max_out_sz))      posFifo <- mkFIFOF();\n   FIFOF#(Bit#(max_out))           weFifo <- mkFIFOF();\n   Vector#(max_out, FIFOF#(t))      fifos <- replicateM(mkFIFOF());\n\n   Reg#(UInt#(max_out_sz))            inPos <- mkReg(0);\n   Reg#(UInt#(max_out_sz))            outPos <- mkReg(0);\n\n   LUInt#(max_out) i_n_in = fromInteger(valueOf(n_in));\n   LUInt#(max_out) i_max_out = fromInteger(valueOf(max_out));\n\n   let verbose = False;\n\n   function a fifoFirst(FIFOF#(a) fifo); if (fifo.notEmpty()) return fifo.first(); else return ?; endfunction\n   function Bool fifoNotEmpty(FIFOF#(a) fifo); return fifo.notEmpty(); endfunction\n   function Bool fifoNotFull(FIFOF#(a) fifo); return fifo.notFull(); endfunction\n\n   FIFOF#(Bool) checkInFifo <- mkFIFOF();\n   rule checkin if (verbose);\n      let v <- toGet(checkInFifo).get();\n      $display(\"checkIn: inPos=%d outPos=%d notEmpties: %h notFulls: %h values: %h\",\n\t       inPos, outPos, map(fifoNotEmpty, fifos), map(fifoNotFull, fifos), map(fifoFirst, fifos));\n   endrule\n\n   rule tofifos;\n      let values = inFifo.first;\n      let pos    = posFifo.first;\n      let we     = weFifo.first;\n\n\n      Bool ready = True;\n      // for (Integer i = 0; i < valueOf(max_out); i = i+1) begin\n      // \t if (we[i] == 1)\n      // \t    ready = ready && fifos[i].notFull();\n      // end\n      $display(\"tofifos: we=%h\", we);\n      if (ready) begin\n\t for (Integer i = 0; i < valueOf(max_out); i = i+1) begin\n\t    if (we[i] == 1)\n\t       fifos[i].enq(values[i]);\n\t end\n\t inFifo.deq();\n\t weFifo.deq();\n\t posFifo.deq();\n\n\t if (verbose) begin\n\t    $display(\"tofifos: pos=%d we=%h\", pos, we, \" values: %h notFull: %h\", values, map(fifoNotFull, fifos));\n\t    checkInFifo.enq(True);\n\t end\n      end\n   endrule\n\n   function Bool deqReadyInternal(Integer n_out);\n      LUInt#(max_out) rot = i_max_out - extend(outPos);\n      Vector#(max_out, Bool) notEmpties = rotateBy(map(fifoNotEmpty, fifos), truncate(rot));\n\n      function Bool n_notEmpty(Integer i); if (i < n_out) return notEmpties[i]; else return True; endfunction\n      Vector#(max_out, Bool) n_notEmpties = genWith(n_notEmpty);\n\n      return fold(booland, n_notEmpties);\n   endfunction\n\n   FIFOF#(Bool) checkFifo <- mkFIFOF();\n   rule check if (verbose);\n      let v <- toGet(checkFifo).get();\n      LUInt#(max_out) rot = i_max_out - extend(outPos);\n      Vector#(max_out, Bool) allNotEmpties = map(fifoNotEmpty, fifos);\n      Vector#(max_out, Bool) notEmpties = rotateBy(map(fifoNotEmpty, fifos), truncate(rot));\n      if (verbose)\n      $display(\"check outPos: \", outPos, \" notEmpty: \", fifos[outPos].notEmpty(),\n\t \" notEmpties: \", notEmpties, \" allNotEmpties: %h\", allNotEmpties);\n   endrule\n\n   function PipeIn#(Vector#(n_in, t)) genInPipe(Integer i);\n      return (interface PipeIn#(Vector#(n_in, t))\n\t\t method Action enq(Vector#(n_in, t) data);\n\t\t    function Bool lessThanCount(Integer i); return fromInteger(i) < i_n_in; endfunction\n\t\t    Vector#(max_out, Bool) we = genWith(lessThanCount);\n\t\t    Vector#(max_out, t) wdata = append(data, replicate(?));\n\t\t    inFifo.enq(rotateBy(wdata, inPos));\n\t\t    posFifo.enq(inPos);\n\t\t    weFifo.enq(pack(rotateBy(we, inPos)));\n\t\t    inPos <= truncate((extend(inPos) + extend(i_n_in)) % i_max_out);\n\n\t\t    if (verbose) begin\n\t\t       $display(\"enq: inPos=%d we=%h\", inPos, we);\n\t\t    end\n\t\t endmethod\n\t\t method notFull = inFifo.notFull;\n\t      endinterface);\n   endfunction\n\n   function PipeOut#(Vector#(max_out, t)) genOutPipe(Integer n_out);\n      function t firstN(Integer i);\n\t if (i < n_out)\n\t    return fifos[(extend(outPos) + fromInteger(i)) % i_max_out].first;\n\t else\n\t    return ?;\n      endfunction\n\n      PipeOut#(Vector#(max_out, t)) pipeOut =\n        (interface PipeOut#(Vector#(max_out, t))\n\t    method    Vector#(max_out, t)           first if (deqReadyInternal(n_out));\n\t       return genWith(firstN);\n\t    endmethod\n\n\t    method    Action                      deq() if (deqReadyInternal(n_out));\n\t       for (Integer i = 0; i < n_out; i = i+1)\n\t\t  fifos[(extend(outPos) + fromInteger(i)) % i_max_out].deq();\n\t       UInt#(max_out_sz) nextOutPos = truncate((extend(outPos) + fromInteger(valueOf(max_out))) % i_max_out);\n\t       outPos <= nextOutPos;\n\n\t       if (verbose) begin\n\t\t  LUInt#(max_out) rot = i_max_out - extend(outPos);\n\t\t  Vector#(max_out, t) v = genWith(firstN);\n\t\t  Vector#(max_out, Bool) allNotEmpties = rotateBy(map(fifoNotEmpty, fifos), truncate(rot));\n\t\t  Vector#(max_out, Bool) notEmpties = map(fifoNotEmpty, rotateBy(fifos, truncate(rot)));\n\t\t  $display(\"first: \", v, \" outPos: \", outPos, \" nextOutPos: \", nextOutPos, \" nextNotEmpty: \", fifos[nextOutPos].notEmpty(),\n\t\t     \" notEmpties: \", notEmpties, \" allNotEmpties: %h\", allNotEmpties);\n\t\t  checkFifo.enq(True);\n\t       end\n\t    endmethod\n      \n\t    method notEmpty  = deqReadyInternal(n_out);\n\t endinterface);\n      return pipeOut;\n   endfunction\n\n   interface Vector in = genInPipe(0);\n   interface Vector out = genWith(genOutPipe);\nendmodule\n"
  },
  {
    "path": "bsv/MemPipe.bsv",
    "content": "// Copyright (c) 2015 Connectal Project.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\nimport FIFO::*;\nimport FIFOF::*;\nimport GetPut::*;\nimport ClientServer::*;\nimport BRAM::*;\nimport Vector::*;\nimport Probe::*;\n\nimport ConnectalMemTypes::*;\nimport Pipe::*;\nimport ConfigCounter::*;\n\ninterface MemReaderPipe#(numeric type dsz);\n   interface PipeOut#(MemData#(dsz)) data;\n   interface MemReadClient#(dsz) readClient;\nendinterface\n\nmodule mkMemReaderPipe#(Reg#(SGLId) ptrReg,\n\t\t\tIteratorIfc#(Bit#(addrsz)) addrIterator,\n\t\t\tBit#(BurstLenSize) burstLen)(MemReaderPipe#(dsz))\n   provisos (Add#(a__, addrsz, MemOffsetSize),\n\t     Add#(b__, BurstLenSize, addrsz));\n\n   let verbose = False;\n\n   ConfigCounter#(addrsz)              counter <- mkConfigCounter(0); \n   FIFO#(MemRequest) readReqFifo <- mkFIFO();\n   FIFOF#(MemData#(dsz)) readDataFifo <- mkSizedFIFOF(8);\n   Reg#(Bit#(MemTagSize)) tagReg <- mkReg(0);\n\n   // 8+1 outstanding reads\n   rule startReadReqRule if (counter.read() <= (extend(unpack(burstLen)) << 3));\n      counter.increment(extend(unpack(burstLen)));\n      let offset <- toGet(addrIterator.pipe).get();\n      let tag = tagReg;\n      if (addrIterator.isFirst())\n\t tag = 0;\n      if (verbose) $display(\"startReadReqRule: offset=%d counter=%d\", offset, counter.read() + (extend(unpack(burstLen)) << 3));\n      readReqFifo.enq(MemRequest { sglId: ptrReg, offset: extend(offset), burstLen: burstLen, tag: extend(tag) });\n      tagReg <= tag + 1;\n   endrule\n\n   interface data = toPipeOut(readDataFifo);\n   interface MemReadClient readClient;\n      interface Get readReq = toGet(readReqFifo);\n      interface Put readData;\n\t method Action put(MemData#(dsz) md);\n\t    readDataFifo.enq(md);\n\t    counter.decrement(fromInteger(valueOf(TDiv#(dsz,8))));\n\t    if (verbose) $display(\"memreader.readData counter.read() %d\", counter.read());\n\t endmethod\n      endinterface\n   endinterface\nendmodule\n\ninterface MemWriterPipe#(numeric type dsz);\n   interface PipeOut#(Bool) lastPipe;\n   interface MemWriteClient#(dsz) writeClient;\nendinterface\n\nmodule mkMemWriterPipe#(Reg#(SGLId) ptrReg,\n\t\t\tIteratorIfc#(Bit#(addrsz)) addrIterator,\n\t\t\tPipeOut#(dtype) dataPipe,\n\t\t\tBit#(BurstLenSize) burstLen)(MemWriterPipe#(dsz))\n   provisos (Bits#(dtype, dsz),\n\t     Add#(a__, addrsz, MemOffsetSize),\n\t     Add#(b__, BurstLenSize, addrsz));\n\n   ConfigCounter#(addrsz)              counter <- mkConfigCounter(0); \n   FIFO#(MemRequest)                   reqFifo <- mkSizedFIFO(4);\n   FIFO#(MemRequest)              writeReqFifo <- mkFIFO();\n   FIFOF#(MemData#(dsz))         writeDataFifo <- mkSizedFIFOF(4);\n   FIFO#(Bit#(MemTagSize))       writeDoneFifo <- mkSizedFIFO(4);\n   FIFOF#(Bool)                       lastFifo <- mkSizedFIFOF(4);\n   FIFOF#(Bool)                       doneFifo <- mkSizedFIFOF(4);\n\n   rule writeReqRule;\n      let offset <- toGet(addrIterator.pipe).get();\n      let tag = 22;\n      $display(\"writeReqRule: offset=%h burstLen=%d addrIterator.isLast %d\", offset, burstLen, addrIterator.isLast());\n      reqFifo.enq(MemRequest { sglId: ptrReg, offset: extend(offset), burstLen: burstLen, tag: tag });\n      lastFifo.enq(addrIterator.isLast());\n   endrule\n   rule writeReqReadyRule if (counter.read() >= extend(unpack(burstLen)));\n      let req <- toGet(reqFifo).get();\n      writeReqFifo.enq(req);\n      counter.decrement(extend(unpack(burstLen)));\n   endrule\n   rule writeDataRule;\n      let tag = 22;\n      let v <- toGet(dataPipe).get();\n      //$display(\"MemWriterPipe.writeDataRule: data=%h\", v);\n      writeDataFifo.enq(MemData { data: pack(v), tag: tag, last: False });\n      counter.increment(fromInteger(valueOf(TDiv#(dsz,8))));\n   endrule\n   rule writeDone;\n      let last <- toGet(lastFifo).get();\n      let tag <- toGet(writeDoneFifo).get();\n      doneFifo.enq(last);\n   endrule\n   interface PipeOut lastPipe = toPipeOut(doneFifo);\n   interface MemWriteClient writeClient;\n      interface Get writeReq = toGet(writeReqFifo);\n      interface Get writeData = toGet(writeDataFifo);\n      interface Put writeDone = toPut(writeDoneFifo);\n   endinterface\nendmodule\n\nmodule mkMemWriterPipe2#(Bool lastOnly,\n\t\t\t Reg#(SGLId) ptrReg,\n\t\t\t IteratorWithContext#(Bit#(addrsz),Bit#(MemTagSize)) addrIterator,\n\t\t\t PipeOut#(dtype) dataPipe,\n\t\t\t Bit#(BurstLenSize) burstLen)(MemWriterPipe#(dsz))\n   provisos (Bits#(dtype, dsz),\n\t     Add#(a__, addrsz, MemOffsetSize),\n\t     Add#(b__, BurstLenSize, addrsz));\n\n   ConfigCounter#(addrsz)              counter <- mkConfigCounter(0); \n   FIFO#(MemRequest)                   reqFifo <- mkSizedFIFO(4);\n   FIFO#(MemRequest)              writeReqFifo <- mkFIFO();\n   FIFOF#(MemData#(dsz))         writeDataFifo <- mkSizedFIFOF(4);\n   FIFO#(Bit#(MemTagSize))       writeDoneFifo <- mkSizedFIFO(4);\n   FIFOF#(Bool)                       lastFifo <- mkSizedFIFOF(4);\n   FIFOF#(Bool)                       doneFifo <- mkFIFOF();\n\n   rule writeReqRule;\n      let iv <- toGet(addrIterator.ivpipe).get();\n      let offset = iv.value;\n      let tag = 22;\n      $display(\"MemWriterPipe2.writeReqRule: offset=%h burstLen=%d addrIterator.isLast %d\", offset, burstLen, addrIterator.isLast());\n      reqFifo.enq(MemRequest { sglId: ptrReg, offset: extend(offset), burstLen: burstLen, tag: tag });\n      lastFifo.enq(iv.last);\n   endrule\n   rule writeReqReadyRule if (counter.read() >= extend(unpack(burstLen)));\n      let req <- toGet(reqFifo).get();\n      writeReqFifo.enq(req);\n      counter.decrement(extend(unpack(burstLen)));\n   endrule\n   rule writeDataRule;\n      let tag = 22;\n      let v <- toGet(dataPipe).get();\n      $display(\"MemWriterPipe2.writeDataRule: data=%h\", v);\n      writeDataFifo.enq(MemData { data: pack(v), tag: tag, last: False });\n      counter.increment(fromInteger(valueOf(TDiv#(dsz,8))));\n   endrule\n   rule writeDone;\n      let last <- toGet(lastFifo).get();\n      let tag <- toGet(writeDoneFifo).get();\n      if (!lastOnly || last) begin\n\t $display(\"writeDone lastOnly=%d last=%d\", lastOnly, last);\n\t doneFifo.enq(last);\n      end\n   endrule\n   interface PipeOut lastPipe = toPipeOut(doneFifo);\n   interface MemWriteClient writeClient;\n      interface Get writeReq = toGet(writeReqFifo);\n      interface Get writeData = toGet(writeDataFifo);\n      interface Put writeDone = toPut(writeDoneFifo);\n   endinterface\nendmodule\n\n\nmodule mkBramReaderPipe#(BRAMServer#(Bit#(addrsz), dataType) bramServer,\n\t\t\t PipeOut#(IteratorValue#(Bit#(addrsz),void)) addrIterator)(PipeOut#(IteratorValue#(dataType,void)))\n   provisos (Add#(a__, addrsz, MemOffsetSize),\n\t     Bits#(dataType,dsz));\n\n   FIFOF#(Tuple2#(Bool,Bool)) firstlastFifo <- mkFIFOF();\n   FIFOF#(IteratorValue#(dataType,void)) readDataFifo <- mkFIFOF();\n\n   let verbose = False;\n\n   rule issueBramReadRequest;\n      let item <- toGet(addrIterator).get();\n      bramServer.request.put(BRAMRequest{write: False, responseOnWrite: False, address: item.value, datain: unpack(0)});\n      firstlastFifo.enq(tuple2(item.first, item.last));\n      if (verbose) $display(\"issueBramReadRequest addr=%h first=%d last=%d\", item.value, item.first, item.last);\n   endrule\n\n   rule readData;\n      let v <- bramServer.response.get();\n      match { .first, .last } <- toGet(firstlastFifo).get();\n      readDataFifo.enq(IteratorValue { value: v, first: first, last: last });\n   endrule\n   return toPipeOut(readDataFifo);\nendmodule\n\nmodule mkBramReaderPipeV#(Vector#(n, BRAMServer#(Bit#(addrsz), dataType)) bramServer,\n\t\t\t  PipeOut#(IteratorValue#(Bit#(addrsz),void)) addrIterator)(PipeOut#(IteratorValue#(Vector#(n,dataType),void)))\n   provisos (Add#(a__, addrsz, MemOffsetSize),\n\t     Bits#(dataType,dsz));\n\n   FIFOF#(Tuple2#(Bool,Bool)) firstlastFifo <- mkFIFOF();\n   FIFOF#(IteratorValue#(Vector#(n,dataType),void)) readDataFifo <- mkFIFOF();\n\n   let verbose = False;\n\n   rule issueBramReadRequest;\n      let item <- toGet(addrIterator).get();\n      for (Integer i = 0; i < valueOf(n); i = i + 1)\n\t bramServer[i].request.put(BRAMRequest{write: False, responseOnWrite: False, address: item.value, datain: unpack(0)});\n      firstlastFifo.enq(tuple2(item.first, item.last));\n      if (verbose) $display(\"issueBramReadRequest addr=%h first=%d last=%d\", item.value, item.first, item.last);\n   endrule\n\n   rule readData;\n      Vector#(n, dataType) vs = unpack(0);\n      for (Integer i = 0; i < valueOf(n); i = i + 1)\n\t vs[i] <- bramServer[i].response.get();\n      match { .first, .last } <- toGet(firstlastFifo).get();\n      readDataFifo.enq(IteratorValue { value: vs, first: first, last: last });\n   endrule\n   return toPipeOut(readDataFifo);\nendmodule\n\ninterface BramWriterPipe#(numeric type dsz);\n   interface PipeOut#(Bool) lastPipe;\nendinterface\n\nmodule mkBramWriterPipe#(BRAMServer#(Bit#(addrsz), dtype) bramServer,\n\t\t\tIteratorIfc#(Bit#(addrsz)) addrIterator,\n\t\t\tPipeOut#(dtype) dataPipe)(BramWriterPipe#(dsz))\n   provisos (Bits#(dtype, dsz),\n\t     Add#(a__, addrsz, MemOffsetSize));\n\n   FIFOF#(Bool)                       lastFifo <- mkFIFOF();\n   FIFOF#(Bool)                       doneFifo <- mkFIFOF();\n\n   Reg#(Bit#(32)) wrrCount <- mkReg(0);\n   Reg#(Bit#(32)) wdoneCount <- mkReg(0);\n   rule writeReqRule;\n      let offset <- toGet(addrIterator.pipe).get();\n      let v <- toGet(dataPipe).get();\n      wrrCount <= wrrCount + 1;\n      //$display(\"BramWriter.writeReqRule: offset=%h addrIterator.isLast %d wrr %d\", offset, addrIterator.isLast(), wrrCount);\n      bramServer.request.put(BRAMRequest { write: True, responseOnWrite: False, address: offset, datain: v });\n      lastFifo.enq(addrIterator.isLast());\n   endrule\n   rule writeDone;\n      let last <- toGet(lastFifo).get();\n      //$display(\"writeDone: wdoneCount=%d last=%d\", wdoneCount, last);\n      wdoneCount <= wdoneCount + 1;\n      doneFifo.enq(last);\n   endrule\n   interface PipeOut lastPipe = toPipeOut(doneFifo);\nendmodule\n"
  },
  {
    "path": "bsv/MemReadEngine.bsv",
    "content": "// Copyright (c) 2013 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\nimport Vector::*;\nimport BuildVector::*;\nimport Cntrs::*;\nimport FIFOF::*;\nimport FIFO::*;\nimport GetPut::*;\nimport Assert::*;\nimport ClientServer::*;\nimport BRAM::*;\nimport BRAMFIFO::*;\nimport ConfigCounter::*;\nimport Connectable::*;\nimport ConnectalMemory::*;\nimport ConnectalBramFifo::*;\nimport ConnectalMemTypes::*;\nimport Pipe::*;\nimport ConnectalMemUtils::*;\nimport ConnectalConfig::*;\n\n`include \"ConnectalProjectConfig.bsv\"\n\ntypedef 2 MemReadFunnelBPC;\n\nmodule mkMemReadEngine(MemReadEngine#(busWidth, userWidth, cmdQDepth, numServers))\n   provisos( Mul#(TDiv#(busWidth, 8), 8, busWidth)\n\t    ,Add#(1, a__, numServers)\n\t    ,Add#(busWidth, 0, userWidth)\n//\t     ,Min#(MemReadFunnelBPC, TLog#(numServers), bpc)\n\t     ,Add#(0,MemReadFunnelBPC,bpc)\n\t    ,FunnelPipesPipelined#(1, numServers, ConnectalMemTypes::MemData#(userWidth), bpc)\n\t    ,Pipe::FunnelPipesPipelined#(1, numServers, ConnectalMemTypes::MemRequest, bpc)\n\t    ,Add#(b__, TLog#(numServers), MemTagSize)\n      \t    );\n   let rv <- mkMemReadEngineBuff(valueOf(cmdQDepth) * valueOf(TExp#(BurstLenSize)));\n   return rv;\nendmodule\n\ntypedef struct {\n    Bit#(BurstLenSize) len;\n    Bool               last;\n} NextReq deriving (Bits, Eq);\n\nfunction NextReq getNext(Bit#(32) len, Bit#(BurstLenSize) burst);\n   NextReq v;\n   v.last = (len <= extend(burst));\n   v.len = v.last ? truncate(len) : burst;\n   return v;\nendfunction\n\ninterface MemReadChannel#(numeric type busWidth, numeric type userWidth, numeric type cmdQDepth);\n   interface PipeOut#(MemRequest)        readReq;\n   interface PipeIn#(MemData#(busWidth)) readData;\n   interface MemReadEngineServer#(userWidth) readServer;\nendinterface\n\nmodule mkMemReadChannel#(Integer bufferSizeBytes, Integer channelNumber, PipeOut#(MemData#(userWidth)) dataPipe)\n   (MemReadChannel#(busWidth, userWidth, cmdQDepth))\n   provisos (Div#(busWidth,8,busWidthBytes),\n\t     Mul#(busWidthBytes,8,busWidth),\n\t     Log#(busWidthBytes,beatShift),\n\t     Log#(cmdQDepth,logCmdQDepth),\n\t     Add#(busWidth, 0, userWidth),\n\t     Add#(1,logCmdQDepth, outCntSz));\n   let verbose = False;\n   let beatShift = fromInteger(valueOf(beatShift));\n\n   let clock <- exposeCurrentClock();\n   let reset <- exposeCurrentReset();\n\n   Integer bufferSizeBeats = bufferSizeBytes/valueOf(busWidthBytes);\n   Reg#(Bool)          clientInFlight <- mkReg(False);\n   ConfigCounter#(16)  clientAvail <- mkConfigCounter(fromInteger(bufferSizeBeats));\n   Reg#(MemengineCmd)  clientCommand <- mkReg(unpack(0));\n`ifdef USE_DUAL_CLOCK_FIFOF\n   FIFOF#(MemDataF#(userWidth)) clientDataFifo <- mkDualClockBramFIFOF(clock, reset, clock, reset);\n`else\n   FIFOF#(MemDataF#(userWidth)) clientDataFifo <- mkSizedBRAMFIFOF(bufferSizeBeats);\n`endif\n   FIFO#(MemengineCmd) clientRequest <- mkFIFO();\n   Reg#(Bit#(32))      clientLen <- mkReg(unpack(0));\n   Reg#(Bit#(32))      clientBase <- mkReg(unpack(0));\n   Reg#(NextReq)       clientNext <- mkReg(unpack(0));\n   Count#(Bit#(32))    clientCycles <- mkCount(0);\n   FIFOF#(MemRequestCycles) clientCyclesFifo <- mkFIFOF();\n   \n   FIFO#(Tuple3#(Bool,Bool,Bit#(BurstLenSize))) serverCheckAvail <- mkSizedFIFO(1);\n   FIFOF#(MemRequest)                          dmaRequest <- mkSizedFIFOF(valueOf(cmdQDepth));\n   FIFO#(Tuple3#(Bit#(BurstLenSize),Bit#(MemTagSize),Bool)) serverProcessing <- mkSizedFIFO(valueOf(cmdQDepth));\n   FIFOF#(MemData#(busWidth))                       serverDataFifo <- mkFIFOF;\n\n   Reg#(Bit#(BurstLenSize))                    respCnt <- mkReg(0);\n   Reg#(Bit#(32)) counter <- mkReg(0);\n\n   rule incCounter;\n      counter <= counter + 1;\n   endrule\n         \n   rule rule_cycles;\n      clientCycles.incr(1);\n   endrule\n   rule rule_startNew if (!clientInFlight);\n      let cmd <- toGet(clientRequest).get();\n      clientInFlight <= True;\n      clientCommand <= cmd;\n      clientLen <= cmd.len - extend(cmd.burstLen);\n      clientBase <= cmd.base;\n      clientNext <= getNext(cmd.len, cmd.burstLen);\n      clientCycles <= 0;\n      if (verbose) $display(\"mkMemReadEngineBuff::%d rule_startNew %d\", counter, clientAvail.read);\n   endrule\n   rule rule_checkAvail if (clientInFlight);\n      let cmd_len = clientNext.len;\n      let last_burst = clientNext.last;\n      let cond0 <- clientAvail.maybeDecrement(unpack(extend(cmd_len>>beatShift)));\n      serverCheckAvail.enq(tuple3(cond0,last_burst,cmd_len));\n      if (verbose) $display(\"mkMemReadEngineBuff::%d chan=%d rule_checkAvail avail %d burstLen %d cond0 %d last_burst %d\", counter, channelNumber, clientAvail.read(), cmd_len>>beatShift, cond0, last_burst);\n   endrule\n\n   rule rule_requestServer if (clientInFlight);\n      match {.cond0,.last_burst,.cmd_len} <- toGet(serverCheckAvail).get;\n      if  (cond0) begin\n\t if (verbose) $display(\"mkMemReadEngineBuff::%d chan=%d rule_requestServer clientLen %d cond0 %d last_burst %d\",\n\t\t\t       counter, channelNumber, clientLen, cond0, last_burst);\n\t serverProcessing.enq(tuple3(truncate(cmd_len>>beatShift), clientCommand.tag, last_burst));\n\t if (verbose) $display(\"MemReadEngine::%d chan=%d readReq idx %d offset %h burstLenBytes %h last %d\", \n\t    counter, channelNumber, 0, clientBase, cmd_len, last_burst);\n\n\t dmaRequest.enq(MemRequest { sglId: clientCommand.sglId, offset: extend(clientBase),\n\t    burstLen:cmd_len, tag: fromInteger(channelNumber)\n\t    `ifdef BYTE_ENABLES\n\t\t\t\t    , firstbe: maxBound, lastbe: maxBound\n\t    `endif\n\t    });\n         clientBase <= clientBase + extend(cmd_len);\n         clientLen <= clientLen - extend(cmd_len);\n         clientNext <= getNext(clientLen, clientCommand.burstLen);\n\t if (last_burst) begin\n\t    if (verbose) $display(\"mkMemReadEngineBuff::%d chan=%d rule_requestServer last_burst %d\", counter, channelNumber, last_burst);\n\t    clientInFlight <= False;\n\t    `ifdef MEMENGINE_REQUEST_CYCLES\n\t    $display(\"clientCycles = %d\", clientCycles);\n\t    clientCyclesFifo.enq(MemRequestCycles { tag:clientCommand.tag, cycles: clientCycles });\n\t    `endif\n\t end\n      end\n   endrule\n\n   rule read_data_rule;\n      let d <- toGet(dataPipe).get();\n      match {.rc, .tag, .last_burst} = serverProcessing.first;\n      let new_respCnt = respCnt+1;\n      let l = False;\n      if (verbose) $display(\"mkMemReadEngineBuff::%d chan=%d data %h new_respCnt %d rc %d last_burst %d tag %d clientInFlight %d eob %d\",\n\t counter, channelNumber, d.data, new_respCnt, rc, last_burst, tag, clientInFlight, d.last);\n      if (new_respCnt == rc) begin\n\t respCnt <= 0;\n\t serverProcessing.deq;\n\t l = last_burst;\n      end\n      else begin\n\t respCnt <= new_respCnt;\n      end\n      clientDataFifo.enq(MemDataF { data: d.data, tag: d.tag, first: (respCnt == 0), last: l});\n   endrule\n\n   MemReadEngineServer#(userWidth) rs = (interface MemReadEngineServer#(userWidth);\n\t\t  interface Put request;\n\t\t     method Action put(MemengineCmd cmd);\n`ifdef SIMULATION\n\t\t\tBit#(32) bsb = fromInteger(bufferSizeBytes);\n\t\t\tBit#(32) dw = fromInteger(valueOf(busWidthBytes));\n\t\t\tlet mdw = ((cmd.len)/dw)*dw != cmd.len;\n\t\t\tlet bbl = extend(cmd.burstLen) > bsb;\n\t\t\tif(bbl || mdw) begin\n\t\t\t   if (bbl)\n\t\t\t      $display(\"XXXXXXXXXX mkMemReadEngineBuff::unsupported burstLen %d %d\", bsb, cmd.burstLen);\n\t\t\t   if (mdw)\n\t\t\t      $display(\"XXXXXXXXXX mkMemReadEngineBuff::unsupported len %d\", cmd.len);\n\t\t\tend\n\t\t\telse\n`endif\n                           begin\n\t\t\t   clientRequest.enq(cmd);\n\t\t\t   end\n \t\t     endmethod\n\t\t  endinterface\n                  interface data = interface PipeOut;\n\t             method MemDataF#(userWidth) first;\n\t                return clientDataFifo.first;\n\t             endmethod\n\t             method Action deq;\n\t                if (verbose) $display(\"mkMemReadEngineBuff::check_out: chan=%d data %h clientAvail %d eob %d\", \n\t\t\t\t\t      channelNumber, clientDataFifo.first.data, clientAvail.read(), clientDataFifo.first.last);\n\t                clientDataFifo.deq;\n\t                clientAvail.increment(1);\n\t             endmethod\n\t             method Bool notEmpty = clientDataFifo.notEmpty;\n                  endinterface;\n\t       interface requestCycles = toPipeOut(clientCyclesFifo);\n               endinterface);\n   interface readServer = rs;\n   interface PipeOut readReq = toPipeOut(dmaRequest);\nendmodule\n\nmodule mkUnfunnelDataPipes#(PipeOut#(MemData#(busWidth)) inPipe)(Vector#(numServers, PipeOut#(MemData#(busWidth))))\n   provisos (Log#(numServers,serverIndexSize),\n\t     Add#(serverIndexSize,a__,MemTagSize));\n   Vector#(numServers, FIFOF#(MemData#(busWidth))) dataFifos <- replicateM(mkFIFOF());\n   rule unfunnel;\n      let md <- toGet(inPipe).get();\n      let tag = md.tag;\n      Bit#(serverIndexSize) fifoNumber = truncate(tag);\n      dataFifos[fifoNumber].enq(md);\n   endrule\n   return map(toPipeOut, dataFifos);\nendmodule\n\nmodule mkMemReadEngineBuff#(Integer bufferSizeBytes) (MemReadEngine#(busWidth, userWidth, cmdQDepth, numServers))\n   provisos (Div#(busWidth,8,busWidthBytes),\n\t     Mul#(busWidthBytes,8,busWidth),\n\t     Add#(busWidth, 0, userWidth),\n//\t     Min#(MemReadFunnelBPC, TLog#(numServers), bpc),\n\t     Add#(0,MemReadFunnelBPC,bpc),\n\t     FunnelPipesPipelined#(1, numServers, ConnectalMemTypes::MemData#(userWidth), bpc),\n\t     FunnelPipesPipelined#(1, numServers, ConnectalMemTypes::MemRequest, bpc),\n\t     Add#(a__, TLog#(numServers), MemTagSize)\n      );\n   let verbose = False;\n\n   let clock <- exposeCurrentClock();\n   let reset <- exposeCurrentReset();\n\n   Integer bufferSizeBeats = bufferSizeBytes/valueOf(busWidthBytes);\n\n   FIFOF#(MemData#(busWidth)) readDataFifo <- mkFIFOF();\n   Vector#(numServers, PipeOut#(MemData#(busWidth))) dataPipes <- mkUnfunnelDataPipes(toPipeOut(readDataFifo));\n\n   Vector#(numServers, MemReadChannel#(busWidth,userWidth,cmdQDepth)) readChannels <- zipWithM(mkMemReadChannel(bufferSizeBytes),\n\t\t\t\t\t\t\t\t\t\t\t       genVector(), dataPipes);\n   Vector#(numServers, FIFOF#(Bit#(MemTagSize))) readtagFifos <- replicateM(mkSizedFIFOF(valueOf(cmdQDepth)));\n   function PipeOut#(MemRequest) readChannelDmaReadReq(Integer i);\n      return readChannels[i].readReq;\n   endfunction\n   function MemReadEngineServer#(userWidth) readChannelServer(Integer i);\n      return readChannels[i].readServer;\n   endfunction\n\n   FIFOF#(MemRequest) reqFifo <- mkFIFOF();\n   FunnelPipe#(1,numServers,MemRequest,bpc) reqFunnel <- mkFunnelPipesPipelined(genWith(readChannelDmaReadReq));\n\n   interface Vector  readServers = genWith(readChannelServer);\n   interface MemReadClient dmaClient;\n      interface Get    readReq = toGet(reqFunnel[0]);\n      interface Put   readData = toPut(readDataFifo);\n   endinterface\n\nendmodule\n"
  },
  {
    "path": "bsv/MemServer.bsv",
    "content": "// Copyright (c) 2013 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\nimport FIFO::*;\nimport Vector::*;\nimport List::*;\nimport GetPut::*;\nimport ClientServer::*;\nimport Assert::*;\nimport StmtFSM::*;\nimport SpecialFIFOs::*;\nimport Connectable::*;\nimport HostInterface::*;\nimport ConnectalMemTypes::*;\nimport ConnectalConfig::*;\nimport ConnectalMemory::*;\nimport ConnectalMMU::*;\nimport MemServerInternal::*;\n\ninterface MemServer#(numeric type addrWidth, numeric type busWidth, numeric type nMasters);\n   interface MemServerRequest request;\n   interface Vector#(nMasters,PhysMemMaster#(addrWidth, busWidth)) masters;\nendinterface\t\t\n\ninterface MemServerWithMMU#(numeric type addrWidth, numeric type busWidth, numeric type nMasters);\n   interface MemServerRequest memServerRequest;\n   interface Vector#(nMasters,PhysMemMaster#(addrWidth, busWidth)) masters;\n   interface MMURequest mmuRequest;\nendinterface\n\ninterface MemServerRead#(numeric type addrWidth, numeric type busWidth, numeric type numClients, numeric type numServers);\n   interface MemServerRequest request;\n   interface Vector#(numClients, PhysMemReadClient#(addrWidth,busWidth)) clients;\n   interface Vector#(numServers, MemReadServer#(busWidth)) servers;\nendinterface\n\ninterface MemServerWrite#(numeric type addrWidth, numeric type busWidth, numeric type numClients, numeric type numServers);\n   interface MemServerRequest request;\n   interface Vector#(numClients, PhysMemWriteClient#(addrWidth,busWidth)) clients;\n   interface Vector#(numServers, MemWriteServer#(busWidth)) servers;\nendinterface\n   \ntypedef struct {\n   DmaErrorType errorType;\n   Bit#(32) pref;\n   } DmaError deriving (Bits);\n\nmodule mkMemServer#(Vector#(numReadClients, MemReadClient#(busWidth)) readClients,\n\t\t    Vector#(numWriteClients, MemWriteClient#(busWidth)) writeClients,\n\t\t    Vector#(numMMUs,MMU#(addrWidth)) mmus,\n\t\t    MemServerIndication indication)  \n   (MemServer#(addrWidth, busWidth, nMasters))\n   provisos(Mul#(TDiv#(numWriteClients, nMasters),nMasters,nws)\n\t    ,Mul#(TDiv#(numReadClients, nMasters),nMasters,nrs)\n\t    ,Add#(TLog#(TDiv#(busWidth, 8)), a__, 8)\n\t    ,Add#(TLog#(TDiv#(busWidth, 8)), b__, BurstLenSize)\n\t    ,Add#(c__, addrWidth, 64)\n\t    ,Add#(numWriteClients, d__, nws)\n\t    ,Add#(numReadClients, e__, nrs)\n\t    ,Add#(f__, TDiv#(busWidth, 8), ByteEnableSize)\n\t    );\n   \n   MemServerRead#(addrWidth,busWidth,nMasters,nrs)  reader <- mkMemServerRead(indication, mmus);\n   MemServerWrite#(addrWidth,busWidth,nMasters,nws) writer <- mkMemServerWrite(indication, mmus);\n   \n   zipWithM_(mkConnection,readClients,take(reader.servers));\n   zipWithM_(mkConnection,writeClients,take(writer.servers));\n   \n   function PhysMemMaster#(addrWidth,busWidth) mkm(Integer i) = (interface PhysMemMaster#(addrWidth,busWidth);\n\t\t     interface PhysMemReadClient read_client = reader.clients[i];\n\t\t     interface PhysMemWriteClient write_client = writer.clients[i];\n\t\t  endinterface);\n\n   interface MemServerRequest request;\n      method Action setTileState(TileControl tc);\n\t reader.request.setTileState(tc);\n\t writer.request.setTileState(tc);\n      endmethod\n      method Action stateDbg(ChannelType rc);\n\t if (rc == ChannelType_Read)\n\t    reader.request.stateDbg(rc);\n\t else\n\t    writer.request.stateDbg(rc);\n      endmethod\n      method Action memoryTraffic(ChannelType rc);\n\t if (rc == ChannelType_Read) \n\t    reader.request.memoryTraffic(rc);\n\t else \n\t    writer.request.memoryTraffic(rc);\n      endmethod\n      method Action addrTrans(Bit#(32) pointer, Bit#(32) offset);\n\t writer.request.addrTrans(pointer,offset);\n      endmethod\n   endinterface\n   interface masters = map(mkm,genVector);\nendmodule\n\nmodule mkMemServerRead#(MemServerIndication indication,\n\t\t\tVector#(numMMUs,MMU#(addrWidth)) mmus)\n   (MemServerRead#(addrWidth, busWidth, numClients, numServers))\n   provisos(Mul#(nrc, numClients, numServers)\n\t    ,Add#(a__, addrWidth, 64)\n\t    ,Add#(TLog#(TDiv#(busWidth, 8)), b__, 8)\n\t    ,Add#(TLog#(TDiv#(busWidth, 8)), c__, BurstLenSize)\n\t    ,Add#(d__, TDiv#(busWidth, 8), ByteEnableSize)\n\t    );\n\n   FIFO#(Bit#(32))   addrReqFifo <- mkFIFO;\n   Reg#(Bit#(8)) dbgPtr <- mkReg(0);\n   Reg#(Bit#(8)) trafficPtr <- mkReg(0);\n   Reg#(Bit#(64)) trafficAccum <- mkReg(0);\n   \n   function Server#(AddrTransRequest,AddrTransResponse#(addrWidth)) selectMMUPort(Integer i);\n      return mmus[i].addr[0];\n   endfunction\n   Vector#(numMMUs,ArbitratedMMU#(addrWidth,numClients)) mmu_servers <- mapM(mkArbitratedMMU,map(selectMMUPort,genVector));\n   Vector#(numClients,MemReadInternal#(addrWidth,busWidth,MemServerTags,nrc)) readers;\n   Vector#(numClients, PhysMemReadClient#(addrWidth,busWidth)) read_clients;\n   Vector#(numServers, MemReadServer#(busWidth)) read_servers;\n\n   for(Integer i = 0; i < valueOf(numClients); i = i+1) begin\n      Vector#(numMMUs,Server#(AddrTransRequest,AddrTransResponse#(addrWidth))) ss;\n      for(Integer j = 0; j < valueOf(numMMUs); j=j+1)\n\t ss[j] = mmu_servers[j].servers[i];\n      readers[i] <- mkMemReadInternal(indication,ss);\n      read_clients[i] = readers[i].client;\n      for(Integer j = 0; j < valueOf(nrc); j=j+1)\n\t read_servers[i*valueOf(nrc)+j] = readers[i].servers[j];\n   end\n   \n   rule mmuEntry;\n      addrReqFifo.deq;\n      let addrTransResponse <- mmus[addrReqFifo.first[31:16]].addr[0].response.get;\n      indication.addrResponse(zeroExtend(addrTransResponse.physAddr));\n   endrule\n   \n   Stmt dbgStmt = \n   seq\n      for(dbgPtr <= 0; dbgPtr < fromInteger(valueOf(numClients)); dbgPtr <= dbgPtr+1)\n\t (action\n\t     let rv <- readers[dbgPtr].dbg.dbg;\n\t     indication.reportStateDbg(rv);\n\t  endaction);\n   endseq;\n   FSM dbgFSM <- mkFSM(dbgStmt);\n\n   Stmt trafficStmt = \n   seq\n      trafficAccum <= 0;\n      for(trafficPtr <= 0; trafficPtr < fromInteger(valueOf(numClients)); trafficPtr <= trafficPtr+1)\n\t (action\n\t     let rv <- readers[trafficPtr].dbg.getMemoryTraffic();\n\t     trafficAccum <= trafficAccum + rv;\n\t  endaction);\n      indication.reportMemoryTraffic(trafficAccum);\n   endseq;\n   FSM trafficFSM <- mkFSM(trafficStmt);\n      \n   interface servers = read_servers;\n   interface clients = read_clients;\n   interface MemServerRequest request;\n      method Action setTileState(TileControl tc);\n\t for(Integer i = 0; i < valueOf(numClients); i=i+1)\n\t    readers[i].tileControl.put(tc);\n      endmethod\n      method Action stateDbg(ChannelType rc);\n\t if (rc == ChannelType_Read)\n\t    dbgFSM.start;\n      endmethod\n      method Action memoryTraffic(ChannelType rc);\n\t if (rc == ChannelType_Read)\n\t    trafficFSM.start;\n      endmethod\n      method Action addrTrans(Bit#(32) pointer, Bit#(32) offset);\n\t addrReqFifo.enq(pointer);\n\t mmus[pointer[31:16]].addr[0].request.put(AddrTransRequest{id:truncate(pointer), off:extend(offset)});\n      endmethod\n   endinterface\nendmodule\n\t\nmodule mkMemServerWrite#(MemServerIndication indication,\n\t\t     Vector#(numMMUs,MMU#(addrWidth)) mmus)\n   (MemServerWrite#(addrWidth, busWidth, numClients, numServers))\n   provisos(Mul#(nwc, numClients, numServers)\n\t    ,Add#(a__, addrWidth, 64)\n\t    ,Add#(TLog#(TDiv#(busWidth, 8)), b__, 8)\n\t    ,Add#(TLog#(TDiv#(busWidth, 8)), c__, BurstLenSize)\n\t    ,Add#(d__, TDiv#(busWidth, 8), ByteEnableSize)\n\t    );\n   \n   FIFO#(Bit#(32))   addrReqFifo <- mkFIFO;\n   Reg#(Bit#(8)) dbgPtr <- mkReg(0);\n   Reg#(Bit#(8)) trafficPtr <- mkReg(0);\n   Reg#(Bit#(64)) trafficAccum <- mkReg(0);\n   \n   function Server#(AddrTransRequest,AddrTransResponse#(addrWidth)) selectMMUPort(Integer i);\n      return mmus[i].addr[1];\n   endfunction\n   Vector#(numMMUs,ArbitratedMMU#(addrWidth,numClients)) mmu_servers <- mapM(mkArbitratedMMU,map(selectMMUPort,genVector));\n   Vector#(numClients,MemWriteInternal#(addrWidth,busWidth,MemServerTags,nwc)) writers;\n   Vector#(numClients, PhysMemWriteClient#(addrWidth,busWidth)) write_clients;\n   Vector#(numServers, MemWriteServer#(busWidth)) write_servers;\n\n   for(Integer i = 0; i < valueOf(numClients); i = i+1) begin\n      Vector#(numMMUs,Server#(AddrTransRequest,AddrTransResponse#(addrWidth))) ss;\n      for(Integer j = 0; j < valueOf(numMMUs); j=j+1)\n\t ss[j] = mmu_servers[j].servers[i];\n      writers[i] <- mkMemWriteInternal(indication, ss);\n      write_clients[i] = writers[i].client;\n      for(Integer j = 0; j < valueOf(nwc); j=j+1)\n\t write_servers[i*valueOf(nwc)+j] = writers[i].servers[j];\n   end\n   \n   rule mmuEntry;\n      addrReqFifo.deq;\n      let addrTransResponse <- mmus[addrReqFifo.first[31:16]].addr[1].response.get;\n      let physAddr = addrTransResponse.physAddr;\n      indication.addrResponse(zeroExtend(physAddr));\n   endrule\n\n   Stmt dbgStmt = \n   seq\n      for(dbgPtr <= 0; dbgPtr < fromInteger(valueOf(numClients)); dbgPtr <= dbgPtr+1)\n\t (action\n\t     let rv <- writers[dbgPtr].dbg.dbg;\n\t     indication.reportStateDbg(rv);\n\t  endaction);\n   endseq;\n   FSM dbgFSM <- mkFSM(dbgStmt);\n\n   Stmt trafficStmt = \n   seq\n      trafficAccum <= 0;\n      for(trafficPtr <= 0; trafficPtr < fromInteger(valueOf(numClients)); trafficPtr <= trafficPtr+1)\n\t (action\n\t     let rv <- writers[trafficPtr].dbg.getMemoryTraffic();\n\t     trafficAccum <= trafficAccum + rv;\n\t  endaction);\n      indication.reportMemoryTraffic(trafficAccum);\n   endseq;\n   FSM trafficFSM <- mkFSM(trafficStmt);\n   \n   interface servers = write_servers;\n   interface clients = write_clients;\n   interface MemServerRequest request;\n      method Action setTileState(TileControl tc);\n\t for(Integer i = 0; i < valueOf(numClients); i=i+1)\n\t    writers[i].tileControl.put(tc);\n      endmethod\n      method Action stateDbg(ChannelType rc);\n\t if (rc == ChannelType_Write)\n\t    dbgFSM.start;\n      endmethod\n      method Action memoryTraffic(ChannelType rc);\n\t if (rc == ChannelType_Write) \n\t    trafficFSM.start;\n      endmethod\n      method Action addrTrans(Bit#(32) pointer, Bit#(32) offset);\n\t addrReqFifo.enq(pointer);\n\t mmus[pointer[31:16]].addr[1].request.put(AddrTransRequest{id:truncate(pointer), off:extend(offset)});\n      endmethod\n   endinterface\nendmodule\n\nmodule mkMemServerWithMMU#(Vector#(numReadClients, MemReadClient#(busWidth)) readClients,\n\t\t\t  Vector#(numWriteClients, MemWriteClient#(busWidth)) writeClients,\n\t\t\t  MemServerIndication indication,\n\t\t\t  MMUIndication mmuIndication)(MemServerWithMMU#(PhysAddrWidth, busWidth,nMasters))\n\n   provisos(Add#(TLog#(TDiv#(busWidth, 8)), e__, 8)\n\t    ,Add#(TLog#(TDiv#(busWidth, 8)), f__, BurstLenSize)\n\t    ,Add#(c__, PhysAddrWidth, 64)\n\t    ,Add#(d__, PhysAddrWidth, MemOffsetSize)\n\t    ,Add#(numWriteClients, a__, TMul#(TDiv#(numWriteClients, nMasters),nMasters))\n\t    ,Add#(numReadClients, b__, TMul#(TDiv#(numReadClients, nMasters),nMasters))\n\t    ,Add#(g__, TDiv#(busWidth, 8), ByteEnableSize)\n\t    );\n\n   \n   MMU#(PhysAddrWidth) hostMMU <- mkMMU(0, True, mmuIndication);\n   MemServer#(PhysAddrWidth,busWidth,nMasters) dma <- mkMemServer(readClients, writeClients, cons(hostMMU,nil), indication);\n\n   interface MemServerRequest memServerRequest = dma.request;\n   interface MMURequest mmuRequest = hostMMU.request;\n   interface Vector masters = dma.masters;\nendmodule\n"
  },
  {
    "path": "bsv/MemServerInternal.bsv",
    "content": "// Copyright (c) 2013 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\n// BSV Libraries\nimport BRAMFIFO::*;\nimport FIFO::*;\nimport FIFOF::*;\nimport Vector::*;\nimport GetPut::*;\nimport ClientServer::*;\nimport Assert::*;\nimport BRAM::*;\nimport DefaultValue::*;\n\n// CONNECTAL Libraries\nimport ConnectalMemTypes::*;\nimport ConnectalMemory::*;\nimport ConnectalClocks::*;\nimport ConnectalMMU::*;\nimport ConnectalCompletionBuffer::*;\nimport ConnectalConfig::*;\n`include \"ConnectalProjectConfig.bsv\"\n\ntypedef 32 BeatCountSize;\n\ntypedef 9 MMU_PIPELINE_DEPTH;\n\ninterface DmaDbg;\n   method ActionValue#(Bit#(64)) getMemoryTraffic();\n   method ActionValue#(DmaDbgRec) dbg();\nendinterface\n\ninterface MemWriteInternal#(numeric type addrWidth, numeric type busWidth, numeric type numTags, numeric type numServers);\n   interface DmaDbg dbg;\n   interface Put#(TileControl) tileControl;\n   interface PhysMemWriteClient#(addrWidth,busWidth) client;\n   interface Vector#(numServers, MemWriteServer#(busWidth)) servers;\nendinterface\n\ninterface MemReadInternal#(numeric type addrWidth, numeric type busWidth, numeric type numTags, numeric type numServers);\n   interface DmaDbg dbg;\n   interface Put#(TileControl) tileControl;\n   interface PhysMemReadClient#(addrWidth,busWidth) client;\n   interface Vector#(numServers, MemReadServer#(busWidth)) servers;\nendinterface\n\nfunction Bool sglid_outofrange(SGLId p);\n   return ((p[15:0]) >= fromInteger(valueOf(MaxNumSGLists)));\nendfunction\n\nimport RegFile::*;\n\ntypedef struct {MemRequest req;\n\t\tBit#(TLog#(TMax#(1,numClients))) client; } LRec#(numeric type numClients, numeric type addrWidth) deriving(Bits);\n\ntypedef struct {MemRequest req;\n\t\tBit#(addrWidth) pa;\n\t\tBit#(MemTagSize) rename_tag;\n\t\tBit#(TLog#(TMax#(1,numClients))) client; } RRec#(numeric type numClients, numeric type addrWidth) deriving(Bits);\n\ntypedef struct {Bit#(MemTagSize) req_tag;\n\t\tBit#(BurstLenSize) req_burstLen;\n\t\tBit#(MemTagSize) rename_tag;\n\t\tBit#(TLog#(TMax#(1,numClients))) client;\n\t\tBool last;\n   } DRec#(numeric type numClients, numeric type addrWidth) deriving(Bits);\n\ntypedef struct {Bit#(MemTagSize) orig_tag;\n\t\tBit#(TLog#(TMax#(1,numClients))) client; } RResp#(numeric type numClients, numeric type addrWidth) deriving(Bits);\n\ntypedef struct {DmaErrorType errorType;\n\t\tBit#(32) pref; } DmaError deriving (Bits);\n\nmodule mkMemReadInternal#(MemServerIndication ind,\n\t\t\t  Vector#(numMMUs,Server#(AddrTransRequest,AddrTransResponse#(addrWidth))) mmus) \n   (MemReadInternal#(addrWidth, busWidth, numTags, numServers))\n   provisos(Log#(busWidthBytes,beatShift)\n\t    ,Div#(busWidth,8,busWidthBytes)\n\t    ,Add#(beatShift, a__, 8)\n\t    ,Add#(b__, TLog#(numTags), MemTagSize)\n\t    ,Add#(beatShift, c__, BurstLenSize)\n\t    ,Add#(d__, TDiv#(busWidth, 8), ByteEnableSize)\n\t    );\n   \n   // stopping/killing infra\n   Vector#(4,Reg#(Bool)) killv <- replicateM(mkReg(False));\n   Vector#(4,Reg#(Bool)) stopv <- replicateM(mkReg(False));\n   \n   // stage 0: address translation (latency = MMU_PIPELINE_DEPTH)\n   FIFO#(LRec#(numServers,addrWidth)) clientRequest <- mkSizedFIFO(valueOf(MMU_PIPELINE_DEPTH));\n   // stage 1: address validation (latency = 1)\n   FIFO#(RRec#(numServers,addrWidth))  serverRequest <- mkFIFO;\n   // stage 2: read commands\n   BRAM_Configure bramConfig = defaultValue;\n   if (mainClockPeriod < 8)\n      bramConfig.latency = 2;\n   BRAM2Port#(Bit#(TLog#(numTags)), DRec#(numServers,addrWidth)) serverProcessing <- mkBRAM2Server(bramConfig);\n   BRAM2Port#(Bit#(TAdd#(TLog#(numTags),TSub#(BurstLenSize,beatShift))), MemData#(busWidth)) clientData <- mkBRAM2Server(bramConfig);\n   // stage 3: read data \n   FIFO#(MemData#(busWidth)) serverData <- mkFIFO;\n   \n   let verbose = False;\n   \n   RegFile#(Bit#(TLog#(numTags)),Tuple2#(Bool,Bit#(BurstLenSize))) clientBurstLen <- mkRegFileFull();\n   Reg#(Bit#(BurstLenSize)) burstReg <- mkReg(0);\n   Reg#(Bool)               firstReg <- mkReg(True);\n         \n   Reg#(Bit#(32))  beatCount <- mkReg(0);\n   let beat_shift = fromInteger(valueOf(beatShift));\n   TagGen#(numTags) tag_gen <- mkTagGen;\n\n   Reg#(Bit#(BurstLenSize))      compCountReg <- mkReg(0);\n   Reg#(Bit#(TLog#(numTags)))    compTagReg <- mkReg(0);\n   Reg#(Bit#(TLog#(TMax#(1,numServers)))) compClientReg <- mkReg(0);\n   Reg#(Bit#(2))                 compTileReg <- mkReg(0);\n   FIFO#(Bit#(TAdd#(1,TLog#(TMax#(1,numServers))))) clientSelect <- mkFIFO;\n   FIFO#(Bit#(TLog#(numTags)))   serverTag <- mkFIFO;\n   \n   // performance analytics \n   Reg#(Bit#(64)) cycle_cnt <- mkReg(0);\n   Reg#(Bit#(64)) last_loadClient <- mkReg(0);\n   Reg#(Bit#(64)) last_mmuResp <- mkReg(0);\n   Reg#(Bit#(64)) last_comp <- mkReg(0);\n   Reg#(Bit#(64)) last_readReq <- mkReg(0);\n   Reg#(Bit#(64)) last_readData <- mkReg(0);\n   (* fire_when_enabled *)\n   rule cycle;\n      cycle_cnt <= cycle_cnt+1;\n   endrule\n         \n   FIFO#(DmaError) dmaErrorFifo <- mkFIFO();\n   rule dmaError;\n      let error <- toGet(dmaErrorFifo).get();\n      ind.error(extend(pack(error.errorType)), error.pref, 0, 0);\n   endrule\n         \n   rule checkMmuResp;\n      let request <- toGet(clientRequest).get();\n      let addrTransResponse <- mmus[request.req.sglId[31:16]].response.get;\n      let physAddr = addrTransResponse.physAddr;\n      let rename_tag <- tag_gen.getTag;\n      let burstLenBeats = request.req.burstLen >> beat_shift;\n      clientBurstLen.upd(truncate(rename_tag), tuple2(burstLenBeats == 1, burstLenBeats));\n      \n      serverRequest.enq(RRec{req:request.req, pa:physAddr, client:request.client, rename_tag:extend(rename_tag)});\n      if (verbose) $display(\"mkMemReadInternal::checkMmuResp: client=%d, tag=%d rename_tag=%d burstLen=%d\", request.client, request.req.tag, rename_tag, burstLenBeats);\n      if (verbose) $display(\"mkMemReadInternal::mmuResp %d %d\", request.client, cycle_cnt-last_mmuResp);\n      last_mmuResp <= cycle_cnt;\n   endrule\n   \n   rule read_data;\n      let response <- toGet(serverData).get();\n      let drq <- serverProcessing.portA.response.get;\n      let tag = drq.req_tag;\n      match { .last, .burstLen } = clientBurstLen.sub(truncate(response.tag));\n      let first   = firstReg;\n      if (first) begin\n\t dynamicAssert(last == (burstLen==1), \"Last incorrect\");\n      end\n      if (last && burstLen != 1)\n\t $display(\"rename_tag=%d tag=%d burstLen=%d last=%d\", response.tag, tag, burstLen, last);\n      Bit#(TLog#(numTags)) tt = truncate(response.tag);\n      clientData.portA.request.put(BRAMRequest{write:True, responseOnWrite:False, datain:MemData{data: response.data, tag: tag, last: last},\n\t\t\t\t\t       address:{tt,truncate(burstLen)}});\n      if (last) begin\n\t tag_gen.returnTag(truncate(response.tag));\n      end\n      last_readData <= cycle_cnt;\n      if (verbose) $display(\"mkMemReadInternal::read_data cyclediff %d\", cycle_cnt-last_readData);\n      clientBurstLen.upd(truncate(response.tag), tuple2((burstLen-1 == 1),burstLen-1));\n      firstReg <= response.last;\n   endrule\n\n   rule tag_completed;\n      let tag <- tag_gen.complete;\n      serverProcessing.portB.request.put(BRAMRequest{write:False, address:tag, datain: ?, responseOnWrite: ?});\n      serverTag.enq(tag);\n      if(verbose) $display(\"mkMemReadInternal::complete_burst0 %h\", tag);\n   endrule\n   \n   rule complete_burst1a if (compCountReg==0);\n      let drq <- serverProcessing.portB.response.get;\n      let req_burstLen = drq.req_burstLen;\n      let client = drq.client;\n      let cnt = req_burstLen >> beat_shift;\n      let tag <- toGet(serverTag).get;\n      if(killv[drq.req_tag[5:4]] == False) begin\n\t clientSelect.enq(extend(client));\n\t clientData.portB.request.put(BRAMRequest{write:False, address:{tag,truncate(cnt)}, datain: ?, responseOnWrite: ?});\n      end\n      compCountReg <= cnt-1;\n      compTagReg <= tag;\n      compClientReg <= client;\n      compTileReg <= drq.req_tag[5:4];\n      if(verbose) $display(\"mkMemReadInternal::complete_burst1a %h\", client);\n   endrule\n\n   rule burst_remainder if (compCountReg > 0);\n      let cnt = compCountReg;\n      let tag = compTagReg;\n      let client = compClientReg;\n      if(killv[compTileReg] == False) begin\n\t clientSelect.enq(extend(client));\n\t clientData.portB.request.put(BRAMRequest{write:False, address:{tag,truncate(cnt)}, datain: ?, responseOnWrite: ?});\n      end\n      compCountReg <= cnt-1;\n      if(verbose) $display(\"mkMemReadInternal::complete_burst1b count %h\", compCountReg);\n   endrule\n   \n   Vector#(numServers, MemReadServer#(busWidth)) sv = newVector;\n   for(Integer i = 0; i < valueOf(numServers); i=i+1) \n      sv[i] = (interface MemReadServer;\n\t\t  interface Put readReq;\n\t\t     method Action put(MemRequest req);\n\t\t\tlast_loadClient <= cycle_cnt;\n\t\t\tlet mmusel = req.sglId[31:16];\n      \t\t\tif (verbose) $display(\"mkMemReadInternal::loadClient server %d mmusel %d burstLen %d tag %d cycle %d\",\n\t\t\t   i, mmusel, req.burstLen >> beat_shift, req.tag, cycle_cnt-last_loadClient);\n\t\t\tif (mmusel >= fromInteger(valueOf(numMMUs)))\n\t\t\t   dmaErrorFifo.enq(DmaError { errorType: DmaErrorMMUOutOfRange_r, pref: req.sglId });\n   \t\t\telse if (sglid_outofrange(req.sglId))\n\t\t\t   dmaErrorFifo.enq(DmaError { errorType: DmaErrorSGLIdOutOfRange_r, pref: req.sglId });\n   \t\t\telse if (stopv[req.tag[5:4]] == False) begin\n   \t\t\t   clientRequest.enq(LRec{req:req, client:fromInteger(i)});\n   \t\t\t   mmus[mmusel].request.put(AddrTransRequest{id:truncate(req.sglId),off:req.offset});\n   \t\t\tend\n\t\t     endmethod\n\t\t  endinterface\n\t\t  interface Get readData;\n\t\t     method ActionValue#(MemData#(busWidth)) get if (clientSelect.first == fromInteger(i));\n\t\t\tclientSelect.deq;\n\t\t\tlet data <- clientData.portB.response.get;\n\t\t\tif (verbose) $display(\"mkMemReadInternal::comp server %d data %x cycle %d\", i, data.data, cycle_cnt-last_comp);\n\t\t\tlast_comp <= cycle_cnt;\n\t\t\treturn data;\n\t\t     endmethod\n\t\t  endinterface\n\t       endinterface);\n   \n   interface servers = sv;\n   interface PhysMemReadClient client;\n      interface Get readReq;\n\t method ActionValue#(PhysMemRequest#(addrWidth,busWidth)) get();\n\t    let request <- toGet(serverRequest).get;\n\t    let req = request.req;\n\t    if (False && request.pa[31:24] != 0)\n\t       $display(\"mkMemReadInternal::req_ar: funny physAddr req.sglId=%d req.offset=%h physAddr=%h\", req.sglId, req.offset, request.pa);\n\t    serverProcessing.portB.request.put(BRAMRequest{write:True, responseOnWrite:False, address:truncate(request.rename_tag),\n\t\t\t\t\t\t   datain:DRec{req_tag:req.tag, req_burstLen: req.burstLen, client:request.client, rename_tag:request.rename_tag, last:(req.burstLen == fromInteger(valueOf(busWidthBytes)))}});\n\t    //$display(\"mkMemReadInternal::readReq: client=%d, rename_tag=%d, physAddr=%h req.burstLen=%d beat_shift=%d last=%d\", request.client,request.rename_tag,request.pa, req.burstLen, beat_shift, req.burstLen == beat_shift);\n\t    if (verbose) $display(\"mkMemReadInternal::read_client.readReq %d\", cycle_cnt-last_readReq);\n\t    last_readReq <= cycle_cnt;\n\t    return PhysMemRequest{addr:request.pa, burstLen:req.burstLen, tag:request.rename_tag\n`ifdef BYTE_ENABLES\n\t\t\t\t  , firstbe: truncate(request.req.firstbe), lastbe: truncate(request.req.lastbe)\n`endif\n\t       };\n\t endmethod\n      endinterface\n      interface Put readData;\n\t method Action put(MemData#(busWidth) response);\n\t    serverData.enq(response);\n\t    serverProcessing.portA.request.put(BRAMRequest{write:False, address:truncate(response.tag), datain: ?, responseOnWrite: ?});\n\t    beatCount <= beatCount+1;\n\t endmethod\n      endinterface\n   endinterface\n   interface Put tileControl;\n      method Action put(TileControl tc);\n\t let tile = tc.tile;\n\t let kv = True;\n\t let sv = True;\n\t if (tc.state == Running || tc.state == Stopped)\n\t    kv = False;\n\t if (tc.state == Running)\n\t    sv = False;\n\t killv[tile] <= kv;\n\t stopv[tile] <= sv;\n      endmethod\n   endinterface\n   interface DmaDbg dbg;\n      method ActionValue#(DmaDbgRec) dbg();\n\t return DmaDbgRec{x:0, y:0, z:0, w:0};\n      endmethod\n      method ActionValue#(Bit#(64)) getMemoryTraffic();\n\t return extend(beatCount);\n      endmethod\n   endinterface\nendmodule\n\nmodule mkMemWriteInternal#(MemServerIndication ind, \n\t\t\t   Vector#(numMMUs,Server#(AddrTransRequest,AddrTransResponse#(addrWidth))) mmus)\n   (MemWriteInternal#(addrWidth, busWidth, numTags, numServers))\n   provisos(Log#(busWidthBytes,beatShift)\n\t    ,Div#(busWidth,8,busWidthBytes)\n\t    ,Add#(beatShift, a__, 8)\n\t    ,Add#(b__, TLog#(numTags), MemTagSize)\n\t    ,Add#(beatShift, c__, BurstLenSize)\n            ,Add#(d__, TDiv#(busWidth, 8), ByteEnableSize)\n\t    );\n   \n   let verbose = False;\n\n   // stopping/killing infra\n   Vector#(4,Reg#(Bool)) killv <- replicateM(mkReg(False));\n   Vector#(4,Reg#(Bool)) stopv <- replicateM(mkReg(False));\n\n   // stage 0: address translation (latency = MMU_PIPELINE_DEPTH)\n   FIFO#(LRec#(numServers,addrWidth)) clientRequest <- mkSizedFIFO(valueOf(MMU_PIPELINE_DEPTH));\n   // stage 1: address validation (latency = 1)\n   FIFO#(RRec#(numServers,addrWidth))  serverRequest <- mkFIFO;\n   // stage 2: write commands\n   FIFO#(DRec#(numServers, addrWidth)) serverProcessing <- mkSizedFIFO(valueOf(numTags));\n   // stage 3: write data \n   BRAM2Port#(Bit#(TLog#(numTags)), RResp#(numServers,addrWidth)) respFifos <- mkBRAM2Server(defaultValue);\n   TagGen#(numTags) tag_gen <- mkTagGen;\n   FIFO#(RResp#(numServers,addrWidth)) clientResponse <- mkFIFO;\n\n   Reg#(Bit#(BurstLenSize)) burstReg <- mkReg(0);\n   Reg#(Bool)               firstReg <- mkReg(True);\n   Reg#(Bool)               lastReg <- mkReg(False);\n   Reg#(Bit#(BeatCountSize)) beatCount <- mkReg(0);\n   let beat_shift = fromInteger(valueOf(beatShift));\n\n   Reg#(Bit#(64)) cycle_cnt <- mkReg(0);\n   Reg#(Bit#(64)) last_loadClient <- mkReg(0);\n   Reg#(Bit#(64)) last_mmuResp <- mkReg(0);\n\n   (* fire_when_enabled *)\n   rule cycle;\n      cycle_cnt <= cycle_cnt+1;\n   endrule\n   \n   FIFO#(DmaError) dmaErrorFifo <- mkFIFO();\n   rule dmaError;\n      let error <- toGet(dmaErrorFifo).get();\n      ind.error(extend(pack(error.errorType)), error.pref, 0, 0);\n   endrule\n\n   rule checkMmuResp;\n      let request <- toGet(clientRequest).get;\n      let req = request.req;\n      let client = request.client;\n      let addrTransResponse <- mmus[req.sglId[31:16]].response.get;\n      let physAddr = addrTransResponse.physAddr;\n      let rename_tag <- tag_gen.getTag;\n      serverRequest.enq(RRec{req:req, pa:physAddr, client:client, rename_tag:extend(rename_tag)});\n      //if (verbose) $display(\"mkMemWriteInternal::checkMmuResp: client=%d, rename_tag=%d\", client,rename_tag);\n      if (verbose) $display(\"mkMemWriteInternal::mmuResp %d %d\", client, cycle_cnt-last_mmuResp);\n      last_mmuResp <= cycle_cnt;\n   endrule\n   \n   rule writeDoneComp0;\n      let tag <- tag_gen.complete;\n      respFifos.portB.request.put(BRAMRequest{write:False, address:tag, datain: ?, responseOnWrite: ?});\n   endrule\n      \n   FIFO#(MemData#(busWidth)) memDataFifo <- mkFIFO();\n   Vector#(numServers, FIFO#(MemData#(busWidth))) clientWriteData <- replicateM(mkFIFO);\n   \n   if(valueOf(numServers) > 0)\n      rule memdata;\n\t let drq = serverProcessing.first;\n\t let req_tag = drq.req_tag;\n\t let req_burstLen = drq.req_burstLen;\n\t let rename_tag = drq.rename_tag;\n\t let client = drq.client;\n\t MemData#(busWidth) tagdata = unpack(0);\n\t if (killv[req_tag[5:4]] == False) begin\n\t    tagdata = clientWriteData[client].first;\n\t    clientWriteData[client].deq;\n\t end\n\t let burstLen = burstReg;\n\t let first    = firstReg;\n\t let last     = lastReg;\n\t if (first) begin\n\t    burstLen = req_burstLen >> beat_shift;\n\t    last     = serverProcessing.first.last;\n\t    respFifos.portA.request.put(BRAMRequest{write:True,responseOnWrite:False, address:truncate(rename_tag), datain:RResp{orig_tag:req_tag, client:client}});\n\t end\n\t burstReg <= burstLen-1;\n\t firstReg <= (burstLen-1 == 0);\n\t lastReg  <= (burstLen-1 == 1);\n\t beatCount <= beatCount+1;\n\t if (last)\n\t    serverProcessing.deq();\n\t //$display(\"mkMemWriteInternal::writeData: client=%d, rename_tag=%d\", client, rename_tag);\n\t memDataFifo.enq(MemData { data: tagdata.data,\n`ifdef BYTE_ENABLES_MEM_DATA\n\t \t\t\t   byte_enables: tagdata.byte_enables,\n`endif\n\t\t\t\t   tag:extend(rename_tag),\n\t\t\t\t   last: last });\n      endrule\n   \n   rule fill_clientResponse;\n      let rv <- respFifos.portB.response.get;\n      clientResponse.enq(rv);\n   endrule\n   \n   Vector#(numServers, MemWriteServer#(busWidth)) sv = newVector;\n   for(Integer i = 0; i < valueOf(numServers); i=i+1) \n      sv[i] = (interface MemWriteServer;\n\t\t  interface Put writeReq;\n\t\t     method Action put(MemRequest req);\n      \t\t\tif (verbose) $display(\"mkMemWriteInternal::loadClient %d %d\", i, cycle_cnt-last_loadClient);\n\t\t\tlast_loadClient <= cycle_cnt;\n\t\t\tlet mmusel = req.sglId[31:16];\n\t\t\tif (mmusel >= fromInteger(valueOf(numMMUs)))\n\t\t\t   dmaErrorFifo.enq(DmaError { errorType: DmaErrorMMUOutOfRange_w, pref: req.sglId });\n   \t\t\telse if (sglid_outofrange(req.sglId))\n\t\t\t   dmaErrorFifo.enq(DmaError { errorType: DmaErrorSGLIdOutOfRange_w, pref: req.sglId });\n   \t\t\telse if (stopv[req.tag[5:4]] == False) begin\n   \t\t\t   clientRequest.enq(LRec{req:req, client:fromInteger(i)});\n   \t\t\t   mmus[mmusel].request.put(AddrTransRequest{id:truncate(req.sglId),off:req.offset});\n   \t\t\tend\n\t\t     endmethod\n\t\t  endinterface\n\t\t  interface Put writeData = toPut(clientWriteData[i]);\n\t\t  interface Get writeDone;\n\t\t     method ActionValue#(Bit#(MemTagSize)) get if (clientResponse.first.client == fromInteger(i));\n\t\t\tclientResponse.deq;\n\t\t\treturn clientResponse.first.orig_tag;\n\t\t     endmethod\n\t\t  endinterface\n\t       endinterface);\n   \n   interface servers = sv;\n   interface PhysMemWriteClient client;\n      interface Get writeReq;\n\t method ActionValue#(PhysMemRequest#(addrWidth,busWidth)) get();\n\t    let request <- toGet(serverRequest).get();\n\t    let req = request.req;\n\t    let physAddr = request.pa;\n\t    let client = request.client;\n\t    let rename_tag = request.rename_tag;\n\t    serverProcessing.enq(DRec{req_tag:req.tag, req_burstLen: req.burstLen, client:client, rename_tag:rename_tag, last: (req.burstLen == fromInteger(valueOf(busWidthBytes))) });\n\t    //$display(\"mkMemWriteInternal::writeReq: client=%d, rename_tag=%d\", client,rename_tag);\n\t    return PhysMemRequest{addr:physAddr, burstLen:req.burstLen, tag:extend(rename_tag)\n`ifdef BYTE_ENABLES\n\t\t\t\t  , firstbe: truncate(req.firstbe), lastbe: truncate(req.lastbe)\n`endif\n};\n\t endmethod\n      endinterface\n      interface Get writeData = toGet(memDataFifo);\n      interface Put writeDone;\n\t method Action put(Bit#(MemTagSize) resp);\n\t    tag_gen.returnTag(truncate(resp));\n\t    if (verbose) $display(\"mkMemWriteInternal::writeDone: resp=%d\", resp);\n\t endmethod\n      endinterface\n   endinterface\n   interface Put tileControl;\n      method Action put(TileControl tc);\n\t let tile = tc.tile;\n\t let kv = True;\n\t let sv = True;\n\t if (tc.state == Running || tc.state == Stopped)\n\t    kv = False;\n\t if (tc.state == Running)\n\t    sv = False;\n\t killv[tile] <= kv;\n\t stopv[tile] <= sv;\n      endmethod\n   endinterface\n   interface DmaDbg dbg;\n      method ActionValue#(DmaDbgRec) dbg();\n\t return DmaDbgRec{x:fromInteger(valueOf(numServers)), y:?, z:?, w:?};\n      endmethod\n      method ActionValue#(Bit#(64)) getMemoryTraffic();\n\t return extend(beatCount);\n      endmethod\n   endinterface\nendmodule\n\n\n"
  },
  {
    "path": "bsv/MemServerPortal.bsv",
    "content": "// Copyright (c) 2016 Connectal Project\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\nimport Connectable::*;\nimport GetPut::*;\nimport FIFOF::*;\nimport ConfigCounter::*;\nimport ConnectalFIFO::*;\n\nimport ConnectalConfig::*;\nimport ConnectalMemTypes::*;\n\n//\n// provides softare ability to read/write a PhysMemSlave or MemServer\n//\ninterface MemServerPortalRequest;\n   method Action read32(Bit#(32) addr);\n   method Action write32(Bit#(32) addr, Bit#(32) data);\n   method Action read64(Bit#(32) addr);\n   method Action write64(Bit#(32) addr, Bit#(64) data);\nendinterface\n\ninterface MemServerPortalResponse;\n   method Action read32Done(Bit#(32) data);\n   method Action read64Done(Bit#(64) data);\n   method Action writeDone();\nendinterface\n\ninterface MemServerPortal;\n   interface MemServerPortalRequest request;\nendinterface\n\nmodule mkPhysMemSlavePortal#(PhysMemSlave#(addrWidth,dataBusWidth) ms, MemServerPortalResponse ind)(MemServerPortal)\n   provisos (Add#(dataBusWidth,7,a__)\n\t     ,Add#(b__,addrWidth,32)\n\t     ,Add#(c__, dataBusWidth, 128)\n\t     ,Bits#(ConnectalMemTypes::MemData#(dataBusWidth), a__));\n\n   FIFOF#(PhysMemRequest#(addrWidth,dataBusWidth)) araddrFifo <- mkFIFOF();\n   FIFOF#(PhysMemRequest#(addrWidth,dataBusWidth)) awaddrFifo <- mkFIFOF();\n   FIFOF#(MemData#(dataBusWidth))           rdataFifo <- mkCFFIFOF();\n   FIFOF#(MemData#(dataBusWidth))           wdataFifo <- mkCFFIFOF();\n   FIFOF#(Bit#(6))                doneFifo <- mkFIFOF();\n   FIFOF#(Bit#(8))                        readLenFifo <- mkCFFIFOF();\n\n   let araddrCnx <- mkConnection(toGet(araddrFifo), ms.read_server.readReq);\n   let awaddrCnx <- mkConnection(toGet(awaddrFifo), ms.write_server.writeReq);\n   let rdataCnx  <- mkConnection(ms.read_server.readData, toPut(rdataFifo));\n   let wdataCnx  <- mkConnection(toGet(wdataFifo), ms.write_server.writeData);\n   let doneCnx   <- mkConnection(ms.write_server.writeDone, toPut(doneFifo));\n\n   ConfigCounter#(16) timeoutCounter <- mkConfigCounter(0);\n   rule rl_timeout if (readLenFifo.notEmpty() && !rdataFifo.notEmpty());\n      timeoutCounter.increment(1);\n      UInt#(16) timeout = 10;\n      if (timeoutCounter.read() == timeout)\n\t $display(\"read timeout %d cycles\", timeout);\n   endrule\n\n   Reg#(Bit#(32)) readDataCount <- mkReg(0);\n   rule rl_rdata32 if (readLenFifo.first == 32);\n      let rdata <- toGet(rdataFifo).get();\n      readLenFifo.deq();\n      Bit#(128) data = extend(rdata.data);\n      if (True) $display(\"read32done data=%h count=%d\", data[31:0], readDataCount);\n      readDataCount <= readDataCount + 1;\n      ind.read32Done(truncate(data));\n   endrule\n   rule rl_rdata64 if (readLenFifo.first == 64);\n      let rdata <- toGet(rdataFifo).get();\n      readLenFifo.deq();\n      Bit#(128) data = extend(rdata.data);\n      ind.read64Done(truncate(data));\n   endrule\n\n   rule rl_writeDone;\n      let tag <- toGet(doneFifo).get();\n      ind.writeDone();\n   endrule\n\n   Reg#(Bit#(32)) readCount <- mkReg(0);\n   interface MemServerPortalRequest request;\n      method Action read32(Bit#(32) addr);\n\t if (True) $display(\"MemServerPortal.read32 addr=%h count=%d\", addr, readCount);\n\t readCount <= readCount + 1;\n\t araddrFifo.enq(PhysMemRequest { addr: truncate(addr), burstLen: fromInteger(valueOf(TDiv#(32,8))), tag: 0 });\n\t readLenFifo.enq(32);\n\t timeoutCounter.decrement(timeoutCounter.read());\n      endmethod\n      method Action write32(Bit#(32) addr, Bit#(32) value);\n\t awaddrFifo.enq(PhysMemRequest { addr: truncate(addr), burstLen: fromInteger(valueOf(TDiv#(32,8))), tag: 0 });\n\t Bit#(128) data = extend(value);\n\t wdataFifo.enq(MemData {data: truncate(data), tag: 0, last: True});\n      endmethod\n\n      method Action read64(Bit#(32) addr);\n\t araddrFifo.enq(PhysMemRequest { addr: truncate(addr), burstLen: fromInteger(valueOf(TDiv#(64,8))), tag: 0 });\n\t readLenFifo.enq(64);\n\t timeoutCounter.decrement(timeoutCounter.read());\n      endmethod\n      method Action write64(Bit#(32) addr, Bit#(64) value);\n\t awaddrFifo.enq(PhysMemRequest { addr: truncate(addr), burstLen: fromInteger(valueOf(TDiv#(64,8))), tag: 0 });\n\t Bit#(128) data = extend(value);\n\t wdataFifo.enq(MemData {data: truncate(data), tag: 0, last: True});\n      endmethod\n   endinterface\nendmodule\n"
  },
  {
    "path": "bsv/MemToPcie.bsv",
    "content": "// Copyright (c) 2013 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\nimport FIFO         :: *;\nimport FIFOF        :: *;\nimport GetPut       :: *;\nimport Connectable  :: *;\nimport PCIE         :: *;\nimport DefaultValue :: *;\nimport Vector       :: *;\nimport ClientServer :: *;\nimport MIMO         :: *;\nimport Probe        :: *;\n\nimport ConnectalMimo :: *;\nimport MIFO         :: *;\nimport ConnectalMemTypes     :: *;\nimport ConfigCounter ::*;\nimport ConnectalConfig::*;\n\n`include \"ConnectalProjectConfig.bsv\"\n\ntypedef struct {\n   TLPData#(TlpDataBytes) tlp;\n   TLPLength    dwCount;\n   Bool         is3dw;\n   Bool         isHeaderOnly;\n   } TlpWriteHeaderInfo deriving (Bits);\n\ninterface MemToPcie#(numeric type buswidth);\n    interface Client#(TLPData#(TlpDataBytes), TLPData#(TlpDataBytes)) tlp;\n    interface PhysMemSlave#(40,buswidth) slave;\n    method Bool tlpOutFifoNotEmpty();\n    interface Reg#(Bool) use4dw;\nendinterface: MemToPcie\n\n`ifdef XILINX\n   `define AXI\n`elsif SIMULATION\n   `define AXI\n`elsif ALTERA\n   `define AVALON\n`endif\n\n`ifdef PCIE3\ntypedef 1024 WriteDataBurstLen; // max payload size is 1024 bytes\n`else\n// typedef 256 WriteDataBurstLen; // max payload size is 256 bytes for Xilinx gen2 core\ntypedef 512 WriteDataBurstLen; // max payload size is 256 bytes for Xilinx gen2 core\n`endif\ntypedef TDiv#(WriteDataBurstLen,4) WriteDataMimoSize; // number of words to hold in the MIMO\ntypedef BurstLenSize WriteDataBurstLenSize;\nmodule mkMemToPcie#(PciId my_id)(MemToPcie#(buswidth))\n   provisos (Div#(buswidth, 8, busWidthBytes),\n\t     Div#(buswidth, 32, busWidthWords),\n\t     Bits#(Vector#(busWidthWords, Bit#(32)), buswidth),\n\t     Log#(busWidthBytes,beatShift),\n\t     Add#(aaa, 32, buswidth),\n\t     Add#(bbb, buswidth, 256),\n\t     Add#(ccc, TMul#(8, busWidthWords), 64),\n\t     Add#(ddd, TMul#(32, busWidthWords), 256),\n\t     Add#(eee, busWidthWords, 8),\n\t     Add#(1, a__, busWidthWords),\n\t     Add#(b__, busWidthWords, TlpDataWords),\n\t     Add#(c__, busWidthWords, WriteDataMimoSize),\n\t     Add#(0,16,TlpDataBytes)\n\t     );\n\n    let verbose = False;\n    let beat_shift = fromInteger(valueOf(beatShift));\n\n    FIFOF#(TLPData#(TlpDataBytes)) tlpOutFifo <- mkFIFOF;\n    FIFOF#(TLPData#(TlpDataBytes)) tlpInFifo <- mkFIFOF;\n    FIFOF#(TlpWriteHeaderInfo) tlpWriteHeaderFifo <- mkFIFOF;\n   FIFOF#(Bool) writeReadyFifo <- mkFIFOF();\n\n    Reg#(Bit#(7)) hitReg <- mkReg(0);\n    Reg#(Bool) use4dwReg <- mkReg(True);\n\n    // default configuration for MIMO is for guarded enq() and deq().\n    // However, the implicit guard only checks for space for 1 element for enq(), and availability of 1 element for deq().\n    MIMOConfiguration mimoCfg = defaultValue;\n   MIFO#(TlpDataWords,busWidthWords,16,Bit#(32)) completionMimo <- mkMIFO();\n   MIFO#(TlpDataWords,busWidthWords,16,Tuple2#(TLPTag,Bool)) completionTagMimo <- mkMIFO(); // tag, last beat of burst\n\n   mimoCfg.bram_based = True;\n   mimoCfg.unguarded = True;\n    MIMO#(busWidthWords,TlpDataWords,WriteDataMimoSize,Bit#(32)) writeDataMimo <- MIMO::mkMIMO(mimoCfg);\n    ConfigCounter#(8) writeDataCnt <- mkConfigCounter(0);\n    Reg#(Bit#(WriteDataBurstLenSize)) writeBurstCount <- mkReg(0);\n    FIFO#(Bit#(WriteDataBurstLenSize)) writeBurstCountFifo <- mkFIFO();\n    Reg#(TLPLength)  writeDwCount <- mkReg(0); // how many 4 byte (double) words to send\n    Reg#(LUInt#(TlpDataWords)) tlpDwCount <- mkReg(0); // how many to send in the next tlp (at most 4)\n    Reg#(Bool)            lastTlp <- mkReg(False); // if the next tlp sent is the last one\n    Reg#(Bool)    writeInProgress <- mkReg(False);\n    FIFOF#(TLPTag) writeTag <- mkSizedFIFOF(16);\n    FIFOF#(TLPTag) doneTag <- mkSizedFIFOF(16);\n\n    Reg#(Bool) quadAlignedTlpHandled <- mkReg(True);\n\n   Wire#(Bool) writeHeaderTlpWire <- mkDWire(False);\n   Wire#(Bool) writeDataMimoEnqWire <- mkDWire(False);\n\n   Reg#(Bool) writeDataMimoHasRoom <- mkReg(False);\n   rule updateWriteDataMimoHasRoom;\n      writeDataMimoHasRoom <= (writeDataCnt.read <= fromInteger(valueOf(WriteDataMimoSize) - valueOf(busWidthWords)));\n   endrule\n   // guard: (writeDataCnt.read >= truncate(unpack(tlpWriteHeaderFifo.first.dwCount)))\n   rule writeHeaderTlp if (!writeInProgress);\n      // update for next cycle\n      let ready <- toGet(writeReadyFifo).get();\n\n      writeHeaderTlpWire <= True;\n      let info <- toGet(tlpWriteHeaderFifo).get();\n      let tlp     = info.tlp;\n      let dwCount = info.dwCount;\n      let is3dw   = info.is3dw;\n      let isHeaderOnly = info.isHeaderOnly;\n\n      TLPMemory4DWHeader hdr_4dw = unpack(truncate(tlp.data));\n\n      TLPMemoryIO3DWHeader hdr_3dw = unpack(truncate(tlp.data));\n      if (is3dw) begin\n\t if (hdr_3dw.format != MEM_WRITE_3DW_DATA)\n\t    $display(\"MemToPcie: expecting MEM_WRITE_3DW_DATA, got %d\", hdr_3dw.format);\n\t Vector#(TlpDataWords, Bit#(32)) v = unpack(0);\n         tlp.sof = True;\n`ifdef AXI\n         v = writeDataMimo.first();\n\t writeDataMimo.deq(1);\n\t hdr_3dw.data = byteSwap(v[0]);\n\t //FIXME: assert deqReadyN here\n         tlp.eof = (dwCount == 1) ? True : False;\n         dwCount = dwCount - 1;\n         writeDataCnt.decrement(1);\n`elsif AVALON\n         let quadWordAligned = isQuadWordAligned(getLowerAddr(hdr_3dw.addr, hdr_3dw.firstbe));\n         // if quad-word aligned, insert bubble.\n         if (!quadWordAligned) begin\n            v = writeDataMimo.first();\n            writeDataMimo.deq(1);\n            hdr_3dw.data = v[0];\n         end\n         else begin\n            hdr_3dw.data = unpack(0);\n         end\n         tlp.eof = (dwCount == 1 && !quadWordAligned) ? True : False;\n         if (!quadWordAligned) begin\n            dwCount = dwCount - 1;\n            writeDataCnt.decrement(1);\n         end\n`endif\n\t tlp.be = 'hffff;\n\t tlp.data = extend(pack(hdr_3dw));\n      end\n      else begin\n         quadAlignedTlpHandled <= isQuadWordAligned(getLowerAddr(truncate(unpack(hdr_4dw.addr)), hdr_4dw.firstbe));\n\t tlp.be = 'hffff;\n      end\n\n      tlpOutFifo.enq(tlp);\n      writeDwCount <= dwCount;\n      tlpDwCount <= truncate(min(fromInteger(valueOf(TlpDataWords)),unpack(dwCount)));\n      lastTlp <= (dwCount <= fromInteger(valueOf(TlpDataWords)));\n      writeInProgress <= (dwCount != 0);\n      if (isHeaderOnly) begin\n\t doneTag.enq(writeTag.first());\n\t writeTag.deq();\n      end\n\n   endrule\n\n   rule writeTlps if (writeInProgress); // already verified  writeDataMimo.deqReadyN(tlpDwCount)) for this transaction\n      TLPData#(TlpDataBytes) tlp = defaultValue;\n      tlp.sof = False;\n      Vector#(TlpDataWords, Bit#(32)) v = unpack(0);\n      Integer currDwCount = valueOf(TlpDataWords);\n\n`ifdef AVALON\n      if (!quadAlignedTlpHandled) begin\n         currDwCount = 3; // 3 Data Dwords in this cycle.\n         quadAlignedTlpHandled <= True;\n      end\n`endif\n\n      // The MIMO implicit guard only checks for availability of 1 element\n      // so we explicitly check for the number of elements required\n      writeDataMimo.deq(tlpDwCount);\n      v = writeDataMimo.first();\n      let dwCount = writeDwCount - extend(pack(tlpDwCount));\n      writeDwCount <= dwCount;\n      tlpDwCount <= truncate(min(fromInteger(currDwCount),unpack(dwCount)));\n      writeDataCnt.decrement(unpack(extend(pack(tlpDwCount))));\n      lastTlp <= (dwCount <= fromInteger(valueOf(TlpDataWords)));\n      tlp.be = maxBound << (4*(fromInteger(valueOf(TlpDataWords))-tlpDwCount));\n      tlp.eof = lastTlp;\n      if (lastTlp) begin\n\t writeInProgress <= False;\n\t doneTag.enq(writeTag.first());\n\t writeTag.deq();\n\t $display(\"writeDwCount=%d will be zero\", writeDwCount);\n      end\n\n      for (Integer i = 0; i < currDwCount; i = i + 1) begin\n`ifdef AXI\n`ifdef PCIE3\n\t tlp.data[(i+1)*32-1:i*32] = v[i];\n`else\n\t tlp.data[(i+1)*32-1:i*32] = byteSwap(v[(currDwCount-1)-i]);\n`endif\n`elsif AVALON\n\t tlp.data[(i+1)*32-1:i*32] = v[(currDwCount-1)-i];\n`endif\n      end\n\n      tlpOutFifo.enq(tlp);\n   endrule: writeTlps\n\n   Reg#(TLPTag) lastTag <- mkReg(0);\n   FIFOF#(TLPData#(TlpDataBytes)) tlpDecodeFifo <- mkFIFOF();\n   Reg#(TLPLength) wordCountReg <- mkReg(0);\n   rule tlpInRule;\n      let tlp <- toGet(tlpInFifo).get();\n      tlpDecodeFifo.enq(tlp);\n   endrule\n\n   rule handleTlpRule;\n      let tlp = tlpDecodeFifo.first;\n      Bool handled = False;\n      TLPMemoryIO3DWHeader h = unpack(truncate(tlp.data));\n      hitReg <= tlp.hit;\n      TLPMemoryIO3DWHeader hdr_3dw = unpack(truncate(tlp.data));\n      TLPCompletionHeader hdr_completion = unpack(truncate(tlp.data));\n      Vector#(TlpDataWords, Bit#(32)) vec = unpack(0);\n      Vector#(TlpDataWords, Bit#(32)) tlpvec = unpack(tlp.data);\n      let wordCount = wordCountReg;\n`ifdef AXI\n      let dataInSecondTlp = False;\n`elsif AVALON\n      let quadWordAligned = isQuadWordAligned(getLowerAddr(hdr_3dw.addr, hdr_3dw.firstbe));\n      let dataInSecondTlp = quadWordAligned;\n`endif\n      if (!tlp.sof) begin\n`ifdef PCIE3\n\t vec = tlpvec;\n`else\n\t vec = reverse(tlpvec);\n`endif\n\t // The MIMO implicit guard only checks for space to enqueue 1 element\n\t // so we explicitly check for the number of elements required\n\t // otherwise elements in the queue will be overwritten.\n\t if (completionMimo.enqReady()\n\t    && completionTagMimo.enqReady())\n\t    begin\n\t       LUInt#(TlpDataWords) count = fromInteger(valueOf(TlpDataWords));\n\t       if (tlp.eof) begin\n\t\t  count = truncate(unpack(wordCountReg));\n\t       end\n\t       wordCount = wordCountReg - extend(pack(count));\n\t       completionMimo.enq(count, vec);\n\t       function Tuple2#(TLPTag,Bool) taglast(Integer i); return tuple2(lastTag, (fromInteger(i) == (count-1)) ? tlp.eof : False); endfunction\n\t       Vector#(TlpDataWords, Tuple2#(TLPTag,Bool)) tagvec = genWith(taglast);\n\t       completionTagMimo.enq(count, tagvec);\n\t       handled = True;\n\t    end\n      end\n      else if (hdr_3dw.format == MEM_WRITE_3DW_DATA\n\t       && hdr_3dw.pkttype == COMPLETION\n\t       && completionMimo.enqReady()\n\t       && completionTagMimo.enqReady()) begin\n            TLPTag tag = hdr_completion.tag;\n            lastTag <= tag;\n            if (!dataInSecondTlp) begin\n               vec[0] = hdr_3dw.data;\n               wordCount = hdr_3dw.length - 1;\n               completionMimo.enq(1, vec);\n               completionTagMimo.enq(1, replicate(tuple2(tag,tlp.eof)));\n            end\n            else begin\n               wordCount = hdr_3dw.length;\n            end\n\t    handled = True;\n      end\n      wordCountReg <= wordCount;\n      if (verbose) $display(\"tlpIn handled=%d tlp=%h\", handled, tlp);\n      if (handled) begin\n\t tlpDecodeFifo.deq();\n      end\n   endrule\n\n   FIFO#(PhysMemRequest#(40,buswidth)) readReqFifo <- mkFIFO();\n   rule readReqRule if (!writeInProgress); // && !writeDataMimo.deqReady());\n      let req <- toGet(readReqFifo).get();\n      let burstLen = req.burstLen >> beat_shift;\n      let addr = req.addr;\n      let arid = req.tag;\n\n      TLPData#(TlpDataBytes) tlp = defaultValue;\n      tlp.sof = True;\n      tlp.eof = True;\n      tlp.hit = 7'h00;\n      TLPLength tlplen = fromInteger(valueOf(busWidthWords))*truncate(burstLen);\n      if (addr[39:32] != 0) begin\n\t TLPMemory4DWHeader hdr_4dw = defaultValue;\n\t hdr_4dw.format = MEM_READ_4DW_NO_DATA;\n\t hdr_4dw.tag = extend(arid);\n\t hdr_4dw.reqid = my_id;\n\t hdr_4dw.nosnoop = SNOOPING_REQD;\n\t hdr_4dw.addr = addr[40-1:2];\n\t hdr_4dw.length = tlplen;\n\t Bit#(TDiv#(buswidth,8)) firstbe = reqFirstByteEnable(req);\n\t Bit#(TDiv#(buswidth,8)) lastbe = reqLastByteEnable(req);\n\t hdr_4dw.firstbe = firstbe[3:0];\n\t hdr_4dw.lastbe = (tlplen > 1) ? lastbe[valueOf(busWidthBytes)-1:valueOf(busWidthBytes)-4] : 0;\n\t tlp.data = extend(pack(hdr_4dw));\n\t tlp.be = 'hffff;\n      end\n      else begin\n\t TLPMemoryIO3DWHeader hdr_3dw = defaultValue;\n\t hdr_3dw.format = MEM_READ_3DW_NO_DATA;\n\t hdr_3dw.tag = extend(arid);\n\t hdr_3dw.reqid = my_id;\n\t hdr_3dw.nosnoop = SNOOPING_REQD;\n\t hdr_3dw.addr = addr[32-1:2];\n\t hdr_3dw.length = tlplen;\n\t Bit#(TDiv#(buswidth,8)) firstbe = reqFirstByteEnable(req);\n\t Bit#(TDiv#(buswidth,8)) lastbe = reqLastByteEnable(req);\n\t hdr_3dw.firstbe = firstbe[3:0];\n\t hdr_3dw.lastbe = (tlplen > 1) ? lastbe[valueOf(busWidthBytes)-1:valueOf(busWidthBytes)-4] : 0;\n\t tlp.data = extend(pack(hdr_3dw));\n\t tlp.be = 'hfff0;\n      end\n      tlpOutFifo.enq(tlp);\n   endrule\n\n    interface Client        tlp;\n        interface request = toGet(tlpOutFifo);\n        interface response = toPut(tlpInFifo);\n    endinterface\n    interface PhysMemSlave slave;\n   interface PhysMemWriteServer write_server; \n      interface Put writeReq;\n         method Action put(PhysMemRequest#(40,buswidth) req); // if (writeBurstCount == 0);\n\t    Bit#(WriteDataBurstLenSize) burstLen = truncate(req.burstLen >> beat_shift);\n\t    let addr = req.addr;\n\t    let awid = req.tag;\n\t    let writeIs3dw = False;\n\t    let use3dw = True;\n`ifdef PCIE3\n\t    awid = awid | (1 << (valueOf(MemTagSize)-1));\n\t    use3dw = False;\n`endif\n\t    TLPLength tlplen = fromInteger(valueOf(busWidthWords))*truncate(burstLen);\n\t    TLPData#(TlpDataBytes) tlp = defaultValue;\n\t    tlp.sof = True;\n\t    tlp.eof = False;\n\t    tlp.hit = 7'h00;\n\t    tlp.be = 'hffff;\n\n\t    if (verbose) $display(\"slave.writeAddr tlplen=%d burstLen=%d\", tlplen, burstLen);\n\t    if ((addr >> 32) != 0 || !use3dw) begin\n\t       TLPMemory4DWHeader hdr_4dw = defaultValue;\n\t       hdr_4dw.format = MEM_WRITE_4DW_DATA;\n\t       hdr_4dw.tag = extend(awid);\n\t       hdr_4dw.reqid = my_id;\n\t       hdr_4dw.nosnoop = SNOOPING_REQD;\n\t       hdr_4dw.addr = addr[40-1:2];\n\t       hdr_4dw.length = tlplen;\n\t       Bit#(TDiv#(buswidth,8)) firstbe = reqFirstByteEnable(req);\n\t       Bit#(TDiv#(buswidth,8)) lastbe = reqLastByteEnable(req);\n\t       hdr_4dw.firstbe = firstbe[3:0];\n\t       hdr_4dw.lastbe = (tlplen > 1) ? lastbe[valueOf(busWidthBytes)-1:valueOf(busWidthBytes)-4] : 0;\n\t       tlp.data = extend(pack(hdr_4dw));\n\t    end\n\t    else begin\n\t       writeIs3dw = True;\n\t       TLPMemoryIO3DWHeader hdr_3dw = defaultValue;\n\t       hdr_3dw.format = MEM_WRITE_3DW_DATA;\n\t       hdr_3dw.tag = extend(awid);\n\t       hdr_3dw.reqid = my_id;\n\t       hdr_3dw.nosnoop = SNOOPING_REQD;\n\t       hdr_3dw.addr = addr[32-1:2];\n\t       hdr_3dw.length = tlplen;\n\t       Bit#(TDiv#(buswidth,8)) firstbe = reqFirstByteEnable(req);\n\t       Bit#(TDiv#(buswidth,8)) lastbe = reqLastByteEnable(req);\n\t       hdr_3dw.firstbe = firstbe[3:0];\n\t       hdr_3dw.lastbe = (tlplen > 1) ? lastbe[valueOf(busWidthBytes)-1:valueOf(busWidthBytes)-4] : 0;\n\t       tlp.be = 'hfff0; // no data word in this TLP\n\n\t       tlp.data = extend(pack(hdr_3dw));\n\t    end\n\t    tlpWriteHeaderFifo.enq(TlpWriteHeaderInfo {tlp: tlp, dwCount: tlplen, is3dw: writeIs3dw, isHeaderOnly: (writeIs3dw && tlplen == 1) });\n\t    writeBurstCountFifo.enq(burstLen);\n\t    writeTag.enq(extend(awid));\n         endmethod\n\tendinterface\n      interface Put writeData;\n         method Action put(MemData#(buswidth) wdata)\n\t    provisos (Bits#(Vector#(busWidthWords, Bit#(32)), busWidth)) if (writeDataMimoHasRoom); //.enqReadyN(fromInteger(valueOf(busWidthWords))));\n\n\t    let burstLen = writeBurstCount;\n\t    if (burstLen == 0) begin\n\t       burstLen <- toGet(writeBurstCountFifo).get();\n\t    end\n\t    if (burstLen == 1) begin\n\t       writeReadyFifo.enq(True);\n\t    end\n\t    writeBurstCount <= extend(burstLen-1);\n\n\t    Vector#(busWidthWords, Bit#(32)) v = unpack(wdata.data);\n\t    $display(\"writeData.put %h tag %h v %h writeDataCnt\", wdata.data, wdata.tag, v, writeDataCnt.read);\n\t    writeDataMimo.enq(fromInteger(valueOf(busWidthWords)), v);\n            writeDataCnt.increment(fromInteger(valueOf(busWidthWords)));\n\t    writeDataMimoEnqWire <= True;\n         endmethod\n       endinterface\n      interface Get writeDone;\n         method ActionValue#(Bit#(MemTagSize)) get();\n\t      let tag = doneTag.first();\n\t      doneTag.deq();\n\t      return truncate(tag);\n           endmethod\n\tendinterface\n   endinterface\n   interface PhysMemReadServer read_server;\n      interface Put readReq;\n         method Action put(PhysMemRequest#(40,buswidth) req);\n\t    readReqFifo.enq(req);\n         endmethod\n       endinterface\n      interface Get     readData;\n         method ActionValue#(MemData#(buswidth)) get() if (completionMimo.deqReady()\n\t\t\t\t\t\t\t   && completionTagMimo.deqReady());\n\t      let data_v = completionMimo.first;\n\t      let tag_last_v = completionTagMimo.first;\n\t      match { .tag, .last } = tag_last_v[fromInteger(valueOf(busWidthWords))-1];\n\t      completionMimo.deq();\n\t      completionTagMimo.deq();\n              Bit#(buswidth) v = 0;\n              for (Integer i = 0; i < valueOf(busWidthWords); i = i+1) begin\n`ifdef AXI\n`ifdef PCIE3\n\t\t v[(i+1)*32-1:i*32] = data_v[i];\n`else\n\t\t v[(i+1)*32-1:i*32] = byteSwap(data_v[i]);\n`endif\n`elsif AVALON\n\t\t v[(i+1)*32-1:i*32] = data_v[i];\n`endif\n              end\n\t      return MemData { data: v, tag: truncate(tag), last: last}; // last beat of this response burst\n           endmethod\n\tendinterface\n   endinterface\n    endinterface: slave\n   method Bool tlpOutFifoNotEmpty() = tlpOutFifo.notEmpty;\n   interface Reg use4dw = use4dwReg;\nendmodule: mkMemToPcie\n\n"
  },
  {
    "path": "bsv/MemWriteEngine.bsv",
    "content": "// Copyright (c) 2013 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\nimport Vector::*;\nimport BuildVector::*;\nimport Cntrs::*;\nimport FIFOF::*;\nimport FIFO::*;\nimport GetPut::*;\nimport Connectable::*;\nimport BRAMFIFO::*;\nimport ConfigCounter::*;\nimport ConnectalMemTypes::*;\nimport Pipe::*;\nimport ConnectalConfig::*;\n\n`include \"ConnectalProjectConfig.bsv\"\n\nmodule mkMemWriteEngine(MemWriteEngine#(busWidth, userWidth, cmdQDepth, numServers))\n   provisos( Add#(1, d__, busWidth)\n\t    ,Add#(1, d__, userWidth)\n\t    ,Add#(e__, TLog#(numServers), MemTagSize)\n\t    ,FunnelPipesPipelined#(1, numServers, MemData#(userWidth), 2)\n\t    ,FunnelPipesPipelined#(1, numServers, MemRequest, 2)\n\t    ,FunnelPipesPipelined#(1, numServers, Bit#(MemTagSize), 2)\n\t    );\n   let rv <- mkMemWriteEngineBuff(valueOf(TExp#(BurstLenSize)));\n   return rv;\nendmodule\n\ninterface MemWriteChannel#(numeric type busWidth, numeric type userWidth, numeric type cmdQDepth);\n   interface PipeIn#(Bit#(MemTagSize))        writeGnt; // grants request\n   interface PipeOut#(MemRequest)             writeReq;\n   interface PipeOut#(MemData#(userWidth))    writeData;\n   interface PipeIn#(Bit#(MemTagSize))        writeDone;\n   interface MemWriteEngineServer#(userWidth) writeServer;\nendinterface\n\nmodule mkMemWriteChannel#(Integer bufferSizeBytes, Integer channelNumber,\n\t\t\t  PipeOut#(Bit#(MemTagSize)) writeGntPipe, PipeOut#(Bit#(MemTagSize)) writeDonePipe)\n   (MemWriteChannel#(busWidth, userWidth, cmdQDepth))\n   provisos ( Div#(busWidth,8,busWidthBytes)\n\t     ,Log#(busWidthBytes,beatShift)\n\t     ,Add#(1, d__, userWidth)\n\t     ,Add#(userWidth, 0, busWidth)\n\t     );\n\n   Integer bufferSizeBeats = bufferSizeBytes/valueOf(busWidthBytes);\n   Reg#(Bool) load_in_progress <- mkReg(False);\n   FIFO#(Tuple3#(MemengineCmd,Bool,Bool))       serverCond <- mkFIFO1();\n   FIFO#(Tuple2#(Bit#(MemTagSize),MemengineCmd)) serverReq <- mkSizedFIFO(valueOf(cmdQDepth));\n   FIFO#(Tuple3#(Bit#(BurstLenSize),Bit#(MemTagSize),Bool))inProgress <- mkSizedFIFO(valueOf(cmdQDepth));\n   FIFO#(Tuple3#(Bit#(MemTagSize),Bit#(MemTagSize),Bool)) serverDone <- mkSizedFIFO(valueOf(cmdQDepth));\n   FIFOF#(MemRequest)           writeReqFifo <- mkFIFOF();\n   FIFOF#(MemData#(userWidth)) writeDataFifo <- mkFIFOF();\n\n   Reg#(Bool)              clientInFlight <- mkReg(False);\n   Reg#(Bool)              clientBursts <- mkReg(False);\n   ConfigCounter#(16)      clientAvail <- mkConfigCounter(0);\n   Reg#(MemengineCmd)      clientStart <- mkReg(unpack(0));\n   FIFO#(Bool)             clientFinished <- mkSizedFIFO(1);\n   FIFOF#(MemengineCmd)    clientCommand <- mkSizedFIFOF(1);\n   Count#(Bit#(32))        clientCycles     <- mkCount(0);\n   FIFOF#(MemRequestCycles) clientCyclesFifo <- mkFIFOF();\n   FIFOF#(Bit#(userWidth)) dataBuffer <- mkSizedBRAMFIFOF(bufferSizeBeats);\n   Reg#(Bit#(32)) cycles <- mkReg(0);\n   rule rl_cycles;\n      cycles <= cycles + 1;\n   endrule\n   \n   Reg#(Bit#(BurstLenSize))                    respCnt <- mkReg(0);\n   let beat_shift = fromInteger(valueOf(beatShift));\n\n   rule store_cmd if (!clientInFlight);\n      let cmd <- toGet(clientCommand).get();\n      clientInFlight <= True;\n      clientBursts <= True;\n      clientStart <= cmd;\n      $display(\"cycles %d starting request %d bytes %d\", cycles, cmd.tag, cmd.len);\n      clientCycles <= 0;\n   endrule\n   rule rule_request_cycles;\n      clientCycles.incr(1);\n   endrule\n\n   rule load_ctxt_a if (!load_in_progress);\n      if (clientBursts) begin\n\t     load_in_progress <= True;\n\t     let cmd = clientStart;\n\t     let cond1 = cmd.len <= extend(cmd.burstLen);\n         Bool cond0 = False;\n         if (cond1) begin\n            cond0 <- clientAvail.maybeDecrement(unpack(truncate(cmd.len>>beat_shift)));\n         end\n         else begin\n            cond0 <- clientAvail.maybeDecrement(unpack(extend(cmd.burstLen>>beat_shift)));\n         end\n\t     serverCond.enq(tuple3(cmd,cond0,cond1));\n      end\n   endrule\n\n   rule load_ctxt_b if (load_in_progress);\n      load_in_progress <= False;\n      match {.cmd,.cond0,.cond1} <- toGet(serverCond).get;\n      if  (cond0) begin\n\t     //$display(\"load_ctxt_b cycles %d %h\", cycles, cmd.base);\n\t     serverReq.enq(tuple2(0,cmd));\n\t     if (cond1) begin\n\t        clientBursts <= False;\n\t     end\n\t     else begin\n\t        clientStart <= MemengineCmd{sglId:cmd.sglId, base:cmd.base+extend(cmd.burstLen),\n                                        burstLen:cmd.burstLen, len:cmd.len-extend(cmd.burstLen), tag:cmd.tag};\n\t     end\n      end\n   endrule\n\n   rule rlWriteReq;\n      match {.idx, .cmd} <- toGet(serverReq).get;\n      Bit#(BurstLenSize) bl = cmd.burstLen;\n      Bool last = False;\n      if (cmd.len <= extend(bl)) begin\n\t     last = True;\n\t     bl = truncate(cmd.len);\n      end\n      inProgress.enq(tuple3(truncate(bl>>beat_shift), cmd.tag, last));\n      //$display(\"writeReq %d, %h %h %h\", channelNumber, cmd.base, bl, last);\n      writeReqFifo.enq(MemRequest { sglId: cmd.sglId, offset: extend(cmd.base), burstLen:bl, tag: fromInteger(channelNumber)});\n   endrule      \n\n   rule rlWriteData;\n      match {.rc, .client_tag, .last} = inProgress.first;\n      //let gnt = writeGntPipe.first;\n      let new_respCnt = respCnt+1;\n      let lastBeat = False;\n      if (new_respCnt == rc) begin\n\t respCnt <= 0;\n\t inProgress.deq();\n\t //writeGntPipe.deq();\n\t serverDone.enq(tuple3(0,client_tag,last));\n\t lastBeat = True;\n      end\n      else begin\n\t respCnt <= new_respCnt;\n      end\n      let wd <- toGet(dataBuffer).get();\n      writeDataFifo.enq(MemData{data:wd, tag:fromInteger(channelNumber), last:lastBeat});\n   endrule      \n\n   rule rlWriteDone;\n      let tag <- toGet(writeDonePipe).get();\n      match {.idx, .req_tag, .last} <- toGet(serverDone).get;\n      if (last) begin\n\t clientInFlight <= False;\n\t clientFinished.enq(True);\n`ifdef MEMENGINE_REQUEST_CYCLES\n\t $display(\"cycles %d req_tag %d clientCycles = %d\", cycles, req_tag, clientCycles);\n\t clientCyclesFifo.enq(MemRequestCycles { tag: req_tag, cycles: clientCycles });\n`endif\n      end\n      //$display(\"writeDone %d %d\", channelNumber, last);\n   endrule\n\n   MemWriteEngineServer#(userWidth) ws = (interface MemWriteEngineServer#(userWidth);\n      interface Put request;\n\t method Action put(MemengineCmd cmd);\n\t    Bit#(32) bsb = fromInteger(bufferSizeBytes);\n      `ifdef SIMULATION\n\t    Bit#(32) dw = fromInteger(valueOf(busWidthBytes));\n\t    Bit#(32) bl = extend(cmd.burstLen);\n\t    // this is because bsc lifts the divide operation (below)\n\t    // and on startup the simulator gets a floating-point exception\n\t    if (bl ==0)\n\t       bl = 1;\n\t    let mdw1 = ((cmd.len)/dw)*dw != cmd.len;\n\t    let bbl = extend(cmd.burstLen) > bsb;\n\t    if(bbl || mdw1 || cmd.len == 0) begin\n\t       if (bbl)\n\t\t\t\t\t  $display(\"XXXXXXXXXX mkMemWriteEngineBuff::unsupported burstLen %d %d\", bsb, cmd.burstLen);\n\t       if (mdw1 || cmd.len == 0)\n\t\t\t\t\t  $display(\"XXXXXXXXXX mkMemWriteEngineBuff::unsupported len %h mdw1=%d\", cmd.len, mdw1);\n\t    end\n\t    else\n      `endif\n\t       begin\n\t\t  clientCommand.enq(cmd);\n\t\t  $display(\"(%d) %h %h %h\", channelNumber, cmd.base, cmd.len, cmd.burstLen);\n\t       end\n\t endmethod\n      endinterface\n      interface Get done;\n\t method ActionValue#(Bool) get = toGet(clientFinished).get;\n      endinterface\n      interface PipeIn data = interface PipeIn;\n\t\t\t\t method Bool notFull = dataBuffer.notFull;\n   \t\t\t\t method Action enq(Bit#(userWidth) v);\n\t\t\t\t    dataBuffer.enq(v);\n\t\t\t\t    clientAvail.increment(1);\n\t\t\t\t endmethod\n\t\t\t      endinterface;\n\t interface PipeOut requestCycles = toPipeOut(clientCyclesFifo);\n\t endinterface);\n   interface writeServer = ws;\n   interface writeReq = toPipeOut(writeReqFifo);\n   interface writeData = toPipeOut(writeDataFifo);\nendmodule\n\nmodule mkMemWriteChannelPipelined#(Integer bufferSizeBytes, Integer channelNumber,\n                                   PipeOut#(Bit#(MemTagSize)) writeGntPipe, \n                                   PipeOut#(Bit#(MemTagSize)) writeDonePipe)\n   (MemWriteChannel#(busWidth, userWidth, cmdQDepth))\n   provisos ( Div#(busWidth,8,busWidthBytes)\n             ,Log#(busWidthBytes,beatShift)\n             ,Add#(1, d__, userWidth)\n             ,Add#(uqserWidth, 0, busWidth)\n             );\n\n   Integer bufferSizeBeats = bufferSizeBytes/valueOf(busWidthBytes);\n   // Reg#(Bool) load_in_progress <- mkReg(False);\n   // FIFO#(Tuple3#(MemengineCmd,Bool,Bool))       serverCond <- mkFIFO1();\n   // FIFO#(Tuple2#(Bit#(MemTagSize),MemengineCmd)) serverReq <- mkSizedFIFO(valueOf(cmdQDepth));\n   FIFO#(Tuple3#(Bit#(BurstLenSize),Bit#(MemTagSize),Bool)) inProgress <- mkSizedFIFO(valueOf(cmdQDepth));\n   FIFO#(Tuple3#(Bit#(MemTagSize),Bit#(MemTagSize),Bool)) serverDone <- mkSizedFIFO(valueOf(cmdQDepth));\n   FIFOF#(MemRequest)           writeReqFifo <- mkFIFOF();\n   FIFOF#(MemData#(userWidth)) writeDataFifo <- mkFIFOF();\n\n   // Reg#(Bool)              clientInFlight <- mkReg(False);\n   // Reg#(Bool)              clientBursts <- mkReg(False);\n   ConfigCounter#(16)      clientAvail <- mkConfigCounter(0);\n   // Reg#(MemengineCmd)      clientStart <- mkReg(unpack(0));\n   FIFOF#(Bool)             clientFinished <- mkSizedFIFOF(valueOf(cmdQDepth));\n   FIFOF#(MemengineCmd)    clientCommand <- mkSizedFIFOF(valueOf(cmdQDepth));\n   // Count#(Bit#(32))        clientCycles     <- mkCount(0);\n   FIFOF#(Bit#(32)) clientCyclesFifoStart <- mkSizedFIFOF(valueOf(cmdQDepth));\n   FIFOF#(MemRequestCycles) clientCyclesFifo <- mkFIFOF();\n   FIFOF#(Bit#(userWidth)) dataBuffer <- mkSizedBRAMFIFOF(bufferSizeBeats);\n   Reg#(Bit#(32)) cycles <- mkReg(0);\n   rule rl_cycles;\n      cycles <= cycles + 1;\n   endrule\n   \n   Reg#(Bit#(BurstLenSize))                    respCnt <- mkReg(0);\n   let beat_shift = fromInteger(valueOf(beatShift));\n\n   // rule store_cmd if (!clientInFlight);\n   //    let cmd <- toGet(clientCommand).get();\n   //    clientInFlight <= True;\n   //    clientBursts <= True;\n   //    clientStart <= cmd;\n   //    $display(\"cycles %d starting request %d bytes %d\", cycles, cmd.tag, cmd.len);\n   //    clientCycles <= 0;\n   // endrule\n   // rule rule_request_cycles;\n   //    clientCycles.incr(1);\n   // endrule\n\n   // rule load_ctxt_a if (!load_in_progress);\n   //    if (clientBursts) begin\n   //       load_in_progress <= True;\n   //       let cmd = clientStart;\n   //       let cond1 = cmd.len <= extend(cmd.burstLen);\n   //       Bool cond0 = False;\n   //       if (cond1) begin\n   //          cond0 <- clientAvail.maybeDecrement(unpack(truncate(cmd.len>>beat_shift)));\n   //       end\n   //       else begin\n   //          cond0 <- clientAvail.maybeDecrement(unpack(extend(cmd.burstLen>>beat_shift)));\n   //       end\n   //       serverCond.enq(tuple3(cmd,cond0,cond1));\n   //    end\n   // endrule\n\n   // rule load_ctxt_b if (load_in_progress);\n   //    load_in_progress <= False;\n   //    match {.cmd,.cond0,.cond1} <- toGet(serverCond).get;\n   //    if  (cond0) begin\n   //       //$display(\"load_ctxt_b cycles %d %h\", cycles, cmd.base);\n   //       serverReq.enq(tuple2(0,cmd));\n   //       if (cond1) begin\n   //          clientBursts <= False;\n   //       end\n   //       else begin\n   //          clientStart <= MemengineCmd{sglId:cmd.sglId, base:cmd.base+extend(cmd.burstLen),\n   //                                      burstLen:cmd.burstLen, len:cmd.len-extend(cmd.burstLen), tag:cmd.tag};\n   //       end\n   //    end\n   // endrule\n/*   \n   rule fullReqQ (!clientCommand.notFull);\n      $display(\"**WARNING** %m clientCommand Channel Num = %d is FULL...\", channelNumber);\n   endrule\n   \n   rule fullDataQ (!dataBuffer.notFull);\n      $display(\"**WARNING** %m writeData Channel Num = %d is FULL...\", channelNumber);\n   endrule\n   \n   rule fullRespQ (!clientFinished.notFull);\n      $display(\"**WARNING** %m clientFinished Channel Num = %d is FULL... (@ %t)\", channelNumber, $time);\n   endrule\n\n   \n   rule fullOutReqQ (!writeReqFifo.notFull);\n      $display(\"**WARNING** %m writeReqFifo Channel Num = %d is FULL... (@ %t)\", channelNumber, $time);\n   endrule\n   \n   rule fullOutDataQ (!writeDataFifo.notFull);\n      $display(\"**WARNING** %m writeDataFifo Channel Num = %d is FULL... (@ %t)\", channelNumber, $time);\n   endrule\n */\n   \n   // rule emptyReqQ (!clientCommand.notEmpty);\n   //    $display(\"**WARNING** %m clientCommand is EMPTY...\");\n   // endrule\n   \n   // rule emptyDataQ (!dataBuffer.notEmpty);\n   //    $display(\"**WARNING** %m writeData is EMPTY...\");\n   // endrule\n   \n   // rule emptyRespQ (!clientFinished.notEmpty);\n   //    $display(\"**WARNING** %m clientFinished is EMPTY...\");\n   // endrule\n\n\n   \n   Reg#(Bit#(32)) lenCnt <- mkReg(0);\n   rule rlWriteReq;\n      let cmd = clientCommand.first;\n            \n      let last = lenCnt + extend(cmd.burstLen) >= cmd.len;\n      \n      Bit#(BurstLenSize) bl = last ? truncate(cmd.len - lenCnt): cmd.burstLen;\n      \n      \n      // this is to make sure we had enough data to burst\n      // let actFlag <- clientAvail.maybeDecrement(unpack(extend(bl>>beat_shift)));\n      \n      // if ( actFlag ) begin\n         \n         lenCnt <= last ? 0 : lenCnt + extend(cmd.burstLen);\n         \n         if ( last ) begin\n            clientCommand.deq;\n         end\n         \n         $display(\"%m writeReq %d, %h %h %h (@ %t)\", channelNumber, cmd.base, bl, last, $time);\n         inProgress.enq(tuple3(truncate(bl>>beat_shift), cmd.tag, last));\n         writeReqFifo.enq(MemRequest { sglId: cmd.sglId, offset: extend(cmd.base+lenCnt), burstLen:bl, tag: fromInteger(channelNumber)});\n         \n      // end\n\n   endrule      \n\n   rule rlWriteData;\n      match {.rc, .client_tag, .last} = inProgress.first;\n      let new_respCnt = respCnt+1;\n      let lastBeat = False;\n      if (new_respCnt == rc) begin\n\t     respCnt <= 0;\n\t     inProgress.deq();\n\t     serverDone.enq(tuple3(0,client_tag,last));\n\t     lastBeat = True;\n      end\n      else begin\n\t     respCnt <= new_respCnt;\n      end\n      let wd <- toGet(dataBuffer).get();\n      $display(\"%m writeData channel = %d, data:%h, last: %d (@%t)\", channelNumber, wd, lastBeat, $time);\n      writeDataFifo.enq(MemData{data:wd, tag:fromInteger(channelNumber), last:lastBeat});\n   endrule      \n\n   rule rlWriteDone;\n      let tag <- toGet(writeDonePipe).get();\n      match {.idx, .req_tag, .last} <- toGet(serverDone).get;\n      $display(\"%m writeDone idx: %d, req_tag: %d, last: %d (@ %t) \", idx, req_tag, last, $time);\n      if (last) begin\n         let startCycle <- toGet(clientCyclesFifoStart).get;\n\t     // clientInFlight <= False;\n\t     clientFinished.enq(True);\n         `ifdef MEMENGINE_REQUEST_CYCLES\n\t     $display(\"cycles %d req_tag %d clientCycles = %d\", cycles-startCycle, req_tag, clientCycles);\n\t     clientCyclesFifo.enq(MemRequestCycles { tag: req_tag, cycles: cyles - startCycle});\n         `endif\n      end\n      //$display(\"writeDone %d %d\", channelNumber, last);\n   endrule\n\n   MemWriteEngineServer#(userWidth) ws = (interface MemWriteEngineServer#(userWidth);\n      interface Put request;\n         method Action put(MemengineCmd cmd);\n\t        Bit#(32) bsb = fromInteger(bufferSizeBytes);\n            `ifdef SIMULATION\n\t        Bit#(32) dw = fromInteger(valueOf(busWidthBytes));\n\t        Bit#(32) bl = extend(cmd.burstLen);\n            // this is because bsc lifts the divide operation (below)\n            // and on startup the simulator gets a floating-point exception\n\t        if (bl ==0)\n\t           bl = 1;\n\t        let mdw1 = ((cmd.len)/dw)*dw != cmd.len;\n\t        let bbl = extend(cmd.burstLen) > bsb;\n\t        if(bbl || mdw1 || cmd.len == 0) begin\n\t           if (bbl)\n\t              $display(\"XXXXXXXXXX mkMemWriteEngineBuff::unsupported burstLen %d %d\", bsb, cmd.burstLen);\n\t           if (mdw1 || cmd.len == 0)\n\t\t\t      $display(\"XXXXXXXXXX mkMemWriteEngineBuff::unsupported len %h mdw1=%d\", cmd.len, mdw1);\n\t        end\n\t        else\n               `endif\n\t           begin\n\t              clientCommand.enq(cmd);\n                  // dataBeatQ.enq(cmd.len >> beat_shift);\n\t              $display(\"(%d) %h %h %h\", channelNumber, cmd.base, cmd.len, cmd.burstLen);\n                  clientCyclesFifoStart.enq(cycles);\n\t           end\n\t     endmethod\n      endinterface\n      interface Get done;\n         method ActionValue#(Bool) get = toGet(clientFinished).get;\n      endinterface\n      interface PipeIn data = interface PipeIn;\n            method Bool notFull = dataBuffer.notFull;\n            method Action enq(Bit#(userWidth) v);\n               dataBuffer.enq(v);\n               // clientAvail.increment(1);\n            endmethod\n         endinterface;\n      interface PipeOut requestCycles = toPipeOut(clientCyclesFifo);\n      endinterface);\n   \n   interface writeServer = ws;\n   interface writeReq = toPipeOut(writeReqFifo);\n   interface writeData = toPipeOut(writeDataFifo);\nendmodule\n\n\nmodule mkMemWriteEngineBuff#(Integer bufferSizeBytes)(MemWriteEngine#(busWidth, userWidth, cmdQDepth, numServers))\n   provisos ( Div#(busWidth,8,busWidthBytes)\n\t     ,Log#(busWidthBytes,beatShift)\n\t     ,Add#(1, a__, userWidth)\n\t     ,Add#(userWidth, 0, busWidth)\n\t     ,Add#(b__, TLog#(numServers), MemTagSize)\n             ,FunnelPipesPipelined#(1, numServers, MemData#(userWidth), 2)\n             ,FunnelPipesPipelined#(1, numServers, MemRequest, 2)\n             ,FunnelPipesPipelined#(1, numServers, Bit#(MemTagSize), 2)\n\t     );\n\n   FIFOF#(Bit#(MemTagSize)) writeDoneFifo <- mkFIFOF();\n   function Tuple2#(Bit#(TLog#(numServers)),Bit#(MemTagSize)) tagDone(Bit#(MemTagSize) tag);\n      return tuple2(truncate(tag), tag);\n   endfunction\n`ifdef ARB_FUNNEL\n   FIFOF#(Bit#(MemTagSize))       arbFifo <- mkFIFOF1();\n   UnFunnelPipe#(1,numServers,Bit#(MemTagSize),2) arbPipes <- mkUnFunnelPipesPipelined(vec(mapPipe(tagDone, toPipeOut(arbFifo))));\n   UnFunnelPipe#(1,numServers,Bit#(MemTagSize),2) donePipes <- mkUnFunnelPipesPipelined(vec(mapPipe(tagDone, toPipeOut(writeDoneFifo))));\n`else\n   Vector#(numServers, FIFOF#(Bit#(MemTagSize)))   arbFifos <- replicateM(mkFIFOF);\n   Vector#(numServers, PipeOut#(Bit#(MemTagSize))) arbPipes = map(toPipeOut, arbFifos);\n   Vector#(numServers, FIFOF#(Bit#(MemTagSize)))   doneFifos <- replicateM(mkFIFOF);\n   Vector#(numServers, PipeOut#(Bit#(MemTagSize))) donePipes = map(toPipeOut, doneFifos);\n`endif\n   // Vector#(numServers, MemWriteChannel#(busWidth,userWidth,cmdQDepth)) writeChannels <- zipWith3M(mkMemWriteChannel(bufferSizeBytes),\n   //  \t\t\t\t\t\t\t\t\t\t\t  genVector(),\n   //  \t\t\t\t\t\t\t\t\t\t\t  arbPipes,\n   //  \t\t\t\t\t\t\t\t\t\t\t  donePipes);\n   Vector#(numServers, MemWriteChannel#(busWidth,userWidth,cmdQDepth)) writeChannels <- zipWith3M(mkMemWriteChannelPipelined(bufferSizeBytes),\n                                                                                                  genVector(),\n                                                                                                  arbPipes,\n                                                                                                  donePipes);\n\n   function PipeOut#(MemRequest) writeChannelDmaWriteReq(Integer i);\n      return writeChannels[i].writeReq;\n   endfunction\n   function PipeOut#(MemData#(userWidth)) writeChannelDmaWriteData(Integer i);\n      return writeChannels[i].writeData;\n   endfunction\n   function MemWriteEngineServer#(userWidth) writeChannelServer(Integer i);\n      return writeChannels[i].writeServer;\n   endfunction\n\n   Reg#(Bool)         reqInFlight <- mkReg(False);\n   Reg#(Bool)         reqNotDone  <- mkReg(False);\n   Reg#(Bit#(TLog#(numServers))) currentChannel <- mkReg(0);\n   FIFOF#(MemRequest)          writeReqFifo <- mkFIFOF();\n   FIFOF#(MemData#(userWidth)) writeDataFifo <- mkSizedFIFOF(16);\n   // FunnelPipe#(1,numServers,MemRequest,2) reqFunnel <- mkFunnelPipesPipelinedRR(genWith(writeChannelDmaWriteReq), 1);\n   FunnelPipe#(1,numServers,MemRequest,2) reqFunnel <- mkFunnelPipesPipelined(genWith(writeChannelDmaWriteReq));\n//   FunnelPipe#(1,numServers,MemData#(userWidth),2) dataFunnel <- mkFunnelPipesPipelined(genWith(writeChannelDmaWriteData));\n   \n   FIFO#(Bit#(TLog#(numServers))) channelQ <- mkSizedFIFO(valueOf(cmdQDepth)*valueOf(numServers));\n\n   rule rl_arbitration;// if (!reqInFlight );// && !reqNotDone);\n      let req <- toGet(reqFunnel[0]).get();\n      // tag is channel number\n      // currentChannel <= truncate(req.tag);\n      // reqNotDone  <= True;\n      writeReqFifo.enq(req);\n      // reqInFlight <= True;\n      channelQ.enq(truncate(req.tag));\n   endrule\n   rule rl_writeData;// if (reqInFlight);\n      let currChannel = channelQ.first;\n      MemData#(userWidth) md <- toGet(writeChannels[currChannel].writeData).get();\n      // MemData#(userWidth) md <- toGet(writeChannels[currentChannel].writeData).get();\n      if (md.last)\n         channelQ.deq;\n\t     // reqInFlight <= False;\n      writeDataFifo.enq(md);\n   endrule\n\n   rule rl_writeDone;\n      let tag <- toGet(writeDoneFifo).get();\n      doneFifos[tag].enq(tag);\n      // reqNotDone  <= False;\n   endrule\n\n   interface writeServers = genWith(writeChannelServer);\n   interface MemWriteClient dmaClient;\n      interface writeReq = toGet(writeReqFifo);\n      interface writeData = toGet(writeDataFifo);\n      interface writeDone = toPut(writeDoneFifo);\n   endinterface: dmaClient\n\nendmodule\n \n"
  },
  {
    "path": "bsv/OldEHR.bsv",
    "content": "//----------------------------------------------------------------------//\n// The MIT License \n// \n// Copyright (c) 2008 Myron King, Nirav Dave\n// \n// Permission is hereby granted, free of charge, to any person \n// obtaining a copy of this software and associated documentation \n// files (the \"Software\"), to deal in the Software without \n// restriction, including without limitation the rights to use,\n// copy, modify, merge, publish, distribute, sublicense, and/or sell\n// copies of the Software, and to permit persons to whom the\n// Software is furnished to do so, subject to the following conditions:\n// \n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n// \n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES\n// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT\n// HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\n// WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n// FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR\n// OTHER DEALINGS IN THE SOFTWARE.\n//----------------------------------------------------------------------//\n\n//\n// Neither of these two modules (mkEHR or mkEHRF) should be used\n// without being enclosed immediately in a synthesize boundry.\n// This is due to bug in the Bluespec compiler which really\n// screws things up.  Finding this out was painful.  Avoid the\n// pain and follow this warning.  (I'm not sure if this is still\n// the case (mdk))\n//\n// Second point: These two EHR implementations are close to what\n// Dan Rosenband outlined in his thesis.  What they lack is\n// scheduling constraints between read/write pairs.  That is to\n// say that read_1 and write_1 are conflict free whereas they\n// should be FORCED to schedule read_1 < write_1 ...\n\nimport Vector ::*;\nimport RWire  ::*;\nimport Probe  ::*;\n\ntypedef  Vector#(n_sz, Reg#(alpha)) EHR#(type n_sz, type alpha);\n\n/*********************************************************************/\n// mkVirtualReg adds one level of ephemeralness to 'base'.  'state'\n// is the concrete interface underlying the virtual register (the \n// register itself).  With state and base as input, mkVirtualReg \n// connects them with Rwires and probes so as to enforce the proper \n// rule scheduling and behavior:\n//             ... < read_n < write_n < read_n+1 < write_n+1 < ...\n/*********************************************************************/\n\nmodule mkVirtualReg#(Reg#(alpha) state, Reg#(alpha) base) \n   (Tuple2#(Reg#(alpha), Reg#(alpha))) provisos(Bits#(alpha,asz));\n\n   // enforce ordering and data forewarding using wires and probes\n   RWire#(alpha) w  <- mkRWire(); \n   Probe#(alpha) probe <- mkProbe; \n\n   Reg#(alpha) i0 = interface Reg\n\t\t       method _read();\n\t\t\t  return base._read();\n                       endmethod\n\t\t       method Action _write(x);\n\t\t\t  w.wset(x);\n\t\t\t  probe <= base._read();\n                       endmethod\n\t\t    endinterface;\n\n   Reg#(alpha) i1 = interface Reg\n\t\t       method _read() = fromMaybe(base._read, w.wget());\n                       method _write(x) = noAction; // never used\n\t\t    endinterface;   \n\n   return (tuple2(i0,i1));\n\nendmodule\n\n/*********************************************************************/\n// Creates an EHR module by layering virtual registers\n// .idx[i] holds read_i and write_i methods.  reg.read_n\n// is expressec as reg[n]._read();\n/*********************************************************************/\n\nmodule mkEHRF#(alpha init)(EHR#(n,alpha)) provisos(Bits#(alpha, asz),\n\t\t\t\t\t\t   Add#(li, 1, n));\n\n   Reg#(alpha) r <- mkReg(init);\n\n   Vector#(n,Reg#(alpha)) vidx = newVector();\n\n   // 'old' is a placeholder which also ensures that the last-written value \n   // won't get dropped since r and old are both the initial register during \n   // the first iteration of the 'for' loop.\n   Reg #(alpha) old = r;\n   Tuple2#(Reg#(alpha),Reg#(alpha)) tinf;\n   \n   // make interfaces\n   for(Integer i = 0; i < valueOf(n); i = i + 1)\n      begin\n\t tinf <- mkVirtualReg(r,old);\n\t vidx[i] = tinf.fst();\n\t old = tinf.snd();\n      end   \n   \n   rule do_stuff(True);\n      r <= tinf.snd._read();\n   endrule\n   \n   return vidx;      \n\nendmodule\n\n/*********************************************************************/\n// alternate implementation, not quite as cool as the functional \n// version, but less code and possibly easier to understand\n/*********************************************************************/\n\nmodule mkEHR#(alpha init) (EHR#(n,alpha)) provisos(Bits#(alpha, asz),\n\t\t\t\t\t\t   Add#(li, 1, n));\n   \n   Reg#(alpha)  r <- mkReg(init);\n   Vector#(n, RWire#(alpha)) wires  <- replicateM(mkRWire);\n   Vector#(n, RWire#(alpha)) probes <- replicateM(mkRWire);\n   Vector#(n, Reg#(alpha)) vidx = newVector();\n   Vector#(n, alpha) chain = newVector();\n   \n   for(Integer i = 0; i < valueOf(n); i = i + 1)\n      begin\n\t if(i==0) chain[i] = r;\n\t else chain[i] = fromMaybe(chain[i-1], wires[i-1].wget());\n      end\n   \n   for(Integer j = 0; j < valueOf(n); j = j + 1)\n      begin\n\t vidx[j] = interface Reg\n\t\t      method _read();\n\t\t\t return chain[j];\n\t\t      endmethod\n\t\t      method Action _write(x);\n\t\t\t wires[j].wset(x);\n\t\t\t probes[j].wset(chain[j]);\n\t\t      endmethod\n\t\t   endinterface;\n      end\n   \n   \n   (*fire_when_enabled, no_implicit_conditions *)\n   rule do_stuff(True);\n      r <= fromMaybe(chain[valueOf(li)], wires[valueOf(li)].wget());\n   endrule\n   \n   return  vidx;\n   \nendmodule\n\ninterface EHR2BSV#(type t);\n   interface Reg#(t) r1;\n   interface Reg#(t) r2;\nendinterface\n\n(* synthesize *)\nmodule mkEHR2BSV (EHR2BSV#(Bit#(32)));\n   EHR#(2,Bit#(32)) ehr <- mkEHR(0);\n   interface r1 = ehr[0];\n   interface r2 = ehr[1];\nendmodule\n"
  },
  {
    "path": "bsv/PS4LIB.bsv",
    "content": "\n// Copyright (c) 2014 Quanta Research Cambridge, Inc.\n// Copyright (c) 2014 Cornell Univeristy.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\n// Stratix IV PCIe Wrapper.\nimport Clocks        ::*;\nimport Vector        ::*;\nimport Connectable   ::*;\nimport ConnectalAlteraCells ::*;\nimport ConnectalClocks      ::*;\n\nimport ALTERA_PCIE_SIV_WRAPPER                 ::*;\n\n(* always_ready, always_enabled *)\ninterface PcieLmi#(numeric type address_width, numeric type data_width);\n   method Action           rden(Bit#(1) rden);\n   method Action           wren(Bit#(1) wren);\n   method Action           addr(Bit#(address_width) addr);\n   method Action           din(Bit#(data_width) din);\n   method Bit#(data_width) dout();\n   method Bit#(1)          ack();\nendinterface\n\n(* always_ready, always_enabled *)\ninterface PcieRxSt#(numeric type data_width);\n   method Bit#(1)          sop   ;\n   method Bit#(1)          eop   ;\n   method Bit#(data_width) data  ;\n   method Bit#(1)          valid ;\n   method Bit#(1)          err   ;\n   method Bit#(1)          empty ;\n   method Bit#(8)          bar   ;\n   method Bit#(16)         be    ;\n   method Action           ready(Bit#(1) ready) ;\n   method Action           mask(Bit#(1) mask)   ;\nendinterface\n\n(* always_ready, always_enabled *)\ninterface PcieTxSt#(numeric type data_width);\n   method Action           sop(Bit#(1) sop);\n   method Action           eop(Bit#(1) eop);\n   method Action           valid(Bit#(1) valid);\n   method Action           err(Bit#(1) err);\n   method Action           empty(Bit#(1) empty);\n   method Bit#(1)          ready;\n   method Action           data(Bit#(data_width) data);\nendinterface\n\n(* always_ready, always_enabled *)\ninterface PcieMsi;\n   method Bit#(1)  int_ack();\n   method Action   int_sts (Bit#(1) int_sts);\n   method Bit#(1)  msi_ack();\n   method Action   msi_num(Bit#(5)num);\n   method Action   msi_req(Bit#(1)req);\n   method Action   msi_tc(Bit#(3)tc);\n   method Action   pex_msi_num(Bit#(5) pex_msi_num);\nendinterface\n\n(* always_ready, always_enabled *)\ninterface PcieTlCfg;\n   method Bit#(4)  add();\n   method Bit#(32) ctl();\n   method Bit#(1)  ctl_wr();\n   method Bit#(53) sts();\n   method Bit#(1)  sts_wr();\n   method Action   cpl_pending(Bit#(1) cpl_pending);\n   method Action   cpl_err(Bit#(7) cpl_err);\nendinterface\n\n(* always_ready, always_enabled *)\ninterface PcieHipRst;\n   method Bit#(1) serdes_pll_locked();\n   method Action  reconfig_clk_locked(Bit#(1) locked);\nendinterface\n\n(* always_ready, always_enabled *)\ninterface PcieTxCred;\n   method Bit#(36) cred();\nendinterface\n\n(* always_ready, always_enabled *)\ninterface PcieRxin;\n(* prefix=\"\", result=\"in\" *)   method Action in((* port=\"in\" *) Vector#(8, Bit#(1)) a);\nendinterface\n\n(* always_ready, always_enabled *)\ninterface PcieTxout;\n   method Vector#(8, Bit#(1)) out();\nendinterface\n\ninterface PcieHipSerial;\n   interface PcieRxin rx;\n   interface PcieTxout tx;\nendinterface\n\ninterface PcieHipPipe;\n(* prefix=\"\", result=\"rxdata\" *)     method Action     rxdata    (Vector#(8, Bit#(8)) rxdata);\n(* prefix=\"\", result=\"rxdatak\" *)    method Action     rxdatak   ((* port=\"rxdatak\" *) Vector#(8, Bit#(1)) rxdatak);\n(* prefix=\"\", result=\"rxelecidle\" *) method Action     rxelecidle(Vector#(8, Bit#(1)) rxelecidle);\n(* prefix=\"\", result=\"rxstatus\" *)   method Action     rxstatus  (Vector#(8, Bit#(3)) rxstatus);\n(* prefix=\"\", result=\"rxvalid\" *)    method Action     rxvalid   (Vector#(8, Bit#(1)) rxvalid);\n(* prefix=\"\", result=\"phystatus\" *)  method Action     phystatus (Vector#(1, Bit#(1)) phystatus);\n(* prefix=\"\", result=\"sim_pipe_pclk_in\" *) method Action sim_pipe_pclk_in(Bit#(1) sim_pipe_pclk_in);\n    method Vector#(8, Bit#(1))    rxpolarity();\n    method Vector#(8, Bit#(1))    txcompl();\n(* prefix=\"\", result=\"txdata\" *)     method Vector#(8, Bit#(8))    txdata();\n    method Vector#(8, Bit#(1))    txdatak();\n    method Vector#(1, Bit#(1))    txdetectrx();\n    method Vector#(8, Bit#(1))    txelecidle();\n    method Vector#(1, Bit#(2))    powerdown();\n    method Bit#(5)    sim_ltssmstate();\n    method Bit#(1)    sim_pipe_rate();\nendinterface\n\n(* always_ready, always_enabled *)\ninterface PcieHipCtrl;\n(* prefix=\"\", result=\"test_in\" *)        method Action test_in(Bit#(40) test_in);\n(* prefix=\"\", result=\"simu_mode_pipe\" *) method Action simu_mode_pipe(Bit#(1) simu_mode_pipe);\nendinterface\n\n(* always_ready, always_enabled *)\ninterface PcieWrap#(numeric type address_width, numeric type data_width, numeric type app_width);\n   interface PcieLmi#(address_width, data_width) lmi;\n   interface PcieRxSt#(app_width) rx_st;\n   interface PcieTxSt#(app_width) tx_st;\n   interface PcieMsi msi;\n   interface PcieTlCfg tl_cfg;\n   interface PcieHipRst hip_rst;\n   interface PcieTxCred tx_cred;\n   interface PcieRxin rx;\n   interface PcieTxout tx;\n   interface PcieHipPipe hip_pipe;\n   interface PcieHipCtrl hip_ctrl;\n   interface Clock coreclkout_hip;\n   interface Reset core_reset;\nendinterface\n\n//(* synthesize *)\nmodule mkPcieS4Wrap#(Clock refclk, Clock reconfig_clk, Clock serdes_clk, Reset pcie_rstn, Reset local_rstn)(PcieWrap#(12, 32, 128));\n\n   Vector#(8, Wire#(Bit#(1))) rx_in_wires <- replicateM(mkDWire(0));\n   Vector#(8, Wire#(Bit#(8))) rxdata_wires <- replicateM(mkDWire(0));\n   Vector#(8, Wire#(Bit#(1))) rxdatak_wires <- replicateM(mkDWire(0));\n   Vector#(8, Wire#(Bit#(1))) rxelecidle_wires <- replicateM(mkDWire(0));\n   Vector#(8, Wire#(Bit#(3))) rxstatus_wires  <- replicateM(mkDWire(0));\n   Vector#(8, Wire#(Bit#(1))) rxvalid_wires   <- replicateM(mkDWire(0));\n   Vector#(1, Wire#(Bit#(1))) phystatus_wires <- replicateM(mkDWire(0));\n   Clock default_clock <- exposeCurrentClock;\n   Reset default_reset <- exposeCurrentReset;\n   Reset reset_high <- invertCurrentReset;\n\n   PcieS4Wrap pcie <- mkPPS4Wrap(refclk, reconfig_clk, serdes_clk, pcie_rstn, local_rstn);\n\n   Clock coreclk = pcie.core.clk_out;\n   Reset corerst <- mkSyncReset(1, pcie.sr.stn, coreclk);\n\n   (* no_implicit_conditions *)\n   rule pcie_rx;\n      pcie.rx.in0(rx_in_wires[0]);\n      pcie.rx.in1(rx_in_wires[1]);\n      pcie.rx.in2(rx_in_wires[2]);\n      pcie.rx.in3(rx_in_wires[3]);\n      pcie.rx.in4(rx_in_wires[4]);\n      pcie.rx.in5(rx_in_wires[5]);\n      pcie.rx.in6(rx_in_wires[6]);\n      pcie.rx.in7(rx_in_wires[7]);\n   endrule\n\n   (* no_implicit_conditions *)\n   rule pcie_rxdata;\n      pcie.rx.data0_ext(rxdata_wires[0]);\n      pcie.rx.data1_ext(rxdata_wires[1]);\n      pcie.rx.data2_ext(rxdata_wires[2]);\n      pcie.rx.data3_ext(rxdata_wires[3]);\n      pcie.rx.data4_ext(rxdata_wires[4]);\n      pcie.rx.data5_ext(rxdata_wires[5]);\n      pcie.rx.data6_ext(rxdata_wires[6]);\n      pcie.rx.data7_ext(rxdata_wires[7]);\n   endrule\n\n   (* no_implicit_conditions *)\n   rule pcie_rxdatak;\n      pcie.rx.datak0_ext(rxdatak_wires[0]);\n      pcie.rx.datak1_ext(rxdatak_wires[1]);\n      pcie.rx.datak2_ext(rxdatak_wires[2]);\n      pcie.rx.datak3_ext(rxdatak_wires[3]);\n      pcie.rx.datak4_ext(rxdatak_wires[4]);\n      pcie.rx.datak5_ext(rxdatak_wires[5]);\n      pcie.rx.datak6_ext(rxdatak_wires[6]);\n      pcie.rx.datak7_ext(rxdatak_wires[7]);\n   endrule\n\n   (* no_implicit_conditions *)\n   rule pcie_rxelecidle;\n      pcie.rx.elecidle0_ext(rxelecidle_wires[0]);\n      pcie.rx.elecidle1_ext(rxelecidle_wires[1]);\n      pcie.rx.elecidle2_ext(rxelecidle_wires[2]);\n      pcie.rx.elecidle3_ext(rxelecidle_wires[3]);\n      pcie.rx.elecidle4_ext(rxelecidle_wires[4]);\n      pcie.rx.elecidle5_ext(rxelecidle_wires[5]);\n      pcie.rx.elecidle6_ext(rxelecidle_wires[6]);\n      pcie.rx.elecidle7_ext(rxelecidle_wires[7]);\n   endrule\n\n   (* no_implicit_conditions *)\n   rule pcie_rxstatus;\n      pcie.rx.status0_ext(rxstatus_wires[0]);\n      pcie.rx.status1_ext(rxstatus_wires[1]);\n      pcie.rx.status2_ext(rxstatus_wires[2]);\n      pcie.rx.status3_ext(rxstatus_wires[3]);\n      pcie.rx.status4_ext(rxstatus_wires[4]);\n      pcie.rx.status5_ext(rxstatus_wires[5]);\n      pcie.rx.status6_ext(rxstatus_wires[6]);\n      pcie.rx.status7_ext(rxstatus_wires[7]);\n   endrule\n\n   (* no_implicit_conditions *)\n   rule pcie_rxvalid;\n      pcie.rx.valid0_ext(rxvalid_wires[0]);\n      pcie.rx.valid1_ext(rxvalid_wires[1]);\n      pcie.rx.valid2_ext(rxvalid_wires[2]);\n      pcie.rx.valid3_ext(rxvalid_wires[3]);\n      pcie.rx.valid4_ext(rxvalid_wires[4]);\n      pcie.rx.valid5_ext(rxvalid_wires[5]);\n      pcie.rx.valid6_ext(rxvalid_wires[6]);\n      pcie.rx.valid7_ext(rxvalid_wires[7]);\n   endrule\n\n   (* no_implicit_conditions *)\n   rule pcie_phystatus;\n      pcie.phystatus.ext(phystatus_wires[0]);\n   endrule\n\n   (* no_implicit_conditions *)\n   rule power_mgmt;\n      pcie.pm.auxpwr(0);\n      pcie.pm.data(10'b0);\n      pcie.pm_e.vent(0);\n      pcie.pm.e_to_cr(0);\n   endrule\n\n   C2B c2b <- mkC2B(coreclk);\n   rule pld_clk_rule;\n      pcie.pld.clk(c2b.o());\n   endrule\n\n   method Clock coreclkout_hip;\n      return coreclk;\n   endmethod\n\n   method Reset core_reset;\n      return corerst;\n   endmethod\n\n   interface PcieLmi lmi;\n      method Bit#(32) dout();\n         return pcie.lmi.dout;\n      endmethod\n\n      method Bit#(1) ack ();\n         return pcie.lmi.ack;\n      endmethod\n\n      method rden = pcie.lmi.rden;\n      method wren = pcie.lmi.wren;\n      method addr = pcie.lmi.addr;\n      method din = pcie.lmi.din;\n   endinterface\n\n   interface PcieMsi msi;\n      method Bit#(1) int_ack;\n         return pcie.app.int_ack;\n      endmethod\n      method Bit#(1) msi_ack;\n         return pcie.app.msi_ack;\n      endmethod\n      method msi_num = pcie.app.msi_num;\n      method msi_req = pcie.app.msi_req;\n      method msi_tc  = pcie.app.msi_tc;\n      method int_sts = pcie.app.int_sts;\n      method pex_msi_num = pcie.pex_msi.num;\n   endinterface\n\n   interface PcieTlCfg tl_cfg;\n      method Bit#(4) add();\n         return pcie.tl_cfg.add;\n      endmethod\n      method Bit#(32) ctl();\n         return pcie.tl_cfg.ctl;\n      endmethod\n      method Bit#(1) ctl_wr();\n         return pcie.tl_cfg.ctl_wr;\n      endmethod\n      method Bit#(53) sts();\n         return pcie.tl_cfg.sts;\n      endmethod\n      method Bit#(1) sts_wr();\n         return pcie.tl_cfg.sts_wr;\n      endmethod\n      method cpl_pending = pcie.cpl.pending;\n      method cpl_err = pcie.cpl.err;\n   endinterface\n\n   interface PcieRxSt rx_st;\n      method Bit#(1)   sop();   return pcie.rx_st.sop0;   endmethod\n      method Bit#(1)   eop();   return pcie.rx_st.eop0;   endmethod\n      method Bit#(128) data();  return pcie.rx_st.data0;  endmethod\n      method Bit#(1)   valid(); return pcie.rx_st.valid0; endmethod\n      method Bit#(1)   err();   return pcie.rx_st.err0;   endmethod\n      method Bit#(1)   empty(); return pcie.rx_st.empty0; endmethod\n      method Bit#(8)   bar();   return pcie.rx_st.bardec0; endmethod\n      method Bit#(16)  be();    return pcie.rx_st.be0; endmethod\n      method ready = pcie.rx_st.ready0;\n      method mask = pcie.rx_st.mask0;\n   endinterface\n\n   interface PcieTxSt tx_st;\n      method Bit#(1) ready (); return pcie.tx_st.ready0; endmethod\n      method sop   = pcie.tx_st.sop0    ;\n      method eop   = pcie.tx_st.eop0    ;\n      method valid = pcie.tx_st.valid0  ;\n      method err   = pcie.tx_st.err0    ;\n      method empty = pcie.tx_st.empty0  ;\n      method data  = pcie.tx_st.data0   ;\n   endinterface\n\n   interface PcieRxin rx;\n      method Action in(Vector#(8, Bit#(1)) a);\n         writeVReg(rx_in_wires, a);\n      endmethod\n   endinterface\n\n   interface PcieTxout tx;\n      method Vector#(8, Bit#(1)) out();\n         Vector#(8, Bit#(1)) ret_val;\n         ret_val[0] = pcie.tx.out0;\n         ret_val[1] = pcie.tx.out1;\n         ret_val[2] = pcie.tx.out2;\n         ret_val[3] = pcie.tx.out3;\n         ret_val[4] = pcie.tx.out4;\n         ret_val[5] = pcie.tx.out5;\n         ret_val[6] = pcie.tx.out6;\n         ret_val[7] = pcie.tx.out7;\n         return ret_val;\n      endmethod\n   endinterface\n\n   interface PcieHipPipe hip_pipe;\n      method Action rxdata(Vector#(8, Bit#(8)) a);\n         writeVReg(rxdata_wires, a);\n      endmethod\n\n      method Action rxdatak(Vector#(8, Bit#(1)) a);\n         writeVReg(rxdatak_wires, a);\n      endmethod\n\n      method Action rxelecidle(Vector#(8, Bit#(1)) a);\n         writeVReg(rxelecidle_wires, a);\n      endmethod\n\n      method Action rxstatus(Vector#(8, Bit#(3)) a);\n         writeVReg(rxstatus_wires, a);\n      endmethod\n\n      method Action rxvalid(Vector#(8, Bit#(1)) a);\n         writeVReg(rxvalid_wires, a);\n      endmethod\n\n      method Action phystatus(Vector#(1, Bit#(1)) a);\n         writeVReg(phystatus_wires, a);\n      endmethod\n\n      method rxpolarity();\n         Vector#(8, Bit#(1)) retval;\n         retval = unpack({pcie.rx.polarity7_ext,\n                          pcie.rx.polarity6_ext,\n                          pcie.rx.polarity5_ext,\n                          pcie.rx.polarity4_ext,\n                          pcie.rx.polarity3_ext,\n                          pcie.rx.polarity2_ext,\n                          pcie.rx.polarity1_ext,\n                          pcie.rx.polarity0_ext});\n         return retval;\n      endmethod\n\n      method txcompl();\n         Vector#(8, Bit#(1)) retval;\n         retval = unpack({pcie.tx.compl7_ext,\n                          pcie.tx.compl6_ext,\n                          pcie.tx.compl5_ext,\n                          pcie.tx.compl4_ext,\n                          pcie.tx.compl3_ext,\n                          pcie.tx.compl2_ext,\n                          pcie.tx.compl1_ext,\n                          pcie.tx.compl0_ext});\n         return retval;\n      endmethod\n\n      method txdata();\n         Vector#(8, Bit#(8)) retval;\n         retval = unpack({pcie.tx.data7_ext,\n                          pcie.tx.data6_ext,\n                          pcie.tx.data5_ext,\n                          pcie.tx.data4_ext,\n                          pcie.tx.data3_ext,\n                          pcie.tx.data2_ext,\n                          pcie.tx.data1_ext,\n                          pcie.tx.data0_ext});\n         return retval;\n      endmethod\n\n      method txdatak();\n         Vector#(8, Bit#(1)) retval;\n         retval = unpack({pcie.tx.datak7_ext,\n                          pcie.tx.datak6_ext,\n                          pcie.tx.datak5_ext,\n                          pcie.tx.datak4_ext,\n                          pcie.tx.datak3_ext,\n                          pcie.tx.datak2_ext,\n                          pcie.tx.datak1_ext,\n                          pcie.tx.datak0_ext});\n         return retval;\n      endmethod\n\n      method txdetectrx();\n         Vector#(1, Bit#(1)) retval;\n         retval = unpack(pcie.tx.detectrx_ext);\n         return retval;\n      endmethod\n\n      method txelecidle();\n         Vector#(8, Bit#(1)) retval;\n         retval = unpack({pcie.tx.elecidle7_ext,\n                          pcie.tx.elecidle6_ext,\n                          pcie.tx.elecidle5_ext,\n                          pcie.tx.elecidle4_ext,\n                          pcie.tx.elecidle3_ext,\n                          pcie.tx.elecidle2_ext,\n                          pcie.tx.elecidle1_ext,\n                          pcie.tx.elecidle0_ext});\n         return retval;\n      endmethod\n\n      method powerdown();\n         Vector#(1, Bit#(2)) retval;\n         retval = unpack(pcie.powerdown.ext);\n         return retval;\n      endmethod\n\n      method sim_pipe_pclk_in = pcie.pclk.in;\n\n      method sim_ltssmstate();\n         return pcie.lts.sm;\n      endmethod\n\n      method sim_pipe_rate();\n         return pcie.rate.ext;\n      endmethod\n   endinterface\n\n   interface PcieHipCtrl hip_ctrl;\n      method test_in = pcie.test.in;\n      method simu_mode_pipe = pcie.pipe.mode;\n   endinterface\n\n   interface PcieHipRst hip_rst;\n      method Bit#(1) serdes_pll_locked;\n         return pcie.rc_pll.locked;\n      endmethod\n\n      method reconfig_clk_locked = pcie.reconfig.clk_locked;\n   endinterface\n\n   interface PcieTxCred tx_cred;\n      method cred();\n         return pcie.tx.cred0;\n      endmethod\n   endinterface\n\nendmodule\n"
  },
  {
    "path": "bsv/PS5LIB.bsv",
    "content": "\n// Copyright (c) 2014 Quanta Research Cambridge, Inc.\n// Copyright (c) 2014 Cornell Univeristy.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\n// Stratix V PCIe Wrapper\nimport Clocks        ::*;\nimport Vector        ::*;\nimport Connectable   ::*;\nimport ConnectalAlteraCells ::*;\nimport ConnectalClocks      ::*;\n\nimport ALTERA_XCVR_RECONFIG_WRAPPER        ::*;\nimport ALTERA_PCIE_RECONFIG_DRIVER_WRAPPER ::*;\nimport ALTERA_PCIE_SV_WRAPPER              ::*;\n//import ALTERA_PLL_WRAPPER                  ::*;\n\n(* always_ready, always_enabled *)\ninterface PcieRxSt#(numeric type data_width);\n   method Bit#(1)          sop;\n   method Bit#(1)          eop;\n   method Bit#(data_width) data;\n   method Action           ready(Bit#(1) ready);\n   method Bit#(1)          valid;\n   method Bit#(1)          err;\n   method Bit#(2)          empty;\n   method Action           mask(Bit#(1) mask);\n   method Bit#(8)          bar();\n   method Bit#(16)         be();\nendinterface\n\n(* always_ready, always_enabled *)\ninterface PcieTxSt#(numeric type data_width);\n   method Action           sop(Bit#(1) sop);\n   method Action           eop(Bit#(1) eop);\n   method Action           valid(Bit#(1) valid);\n   method Action           err(Bit#(1) err);\n   method Action           empty(Bit#(2) empty);\n   method Bit#(1)          ready;\n   method Action           data(Bit#(data_width) data);\nendinterface\n\n(* always_ready, always_enabled *)\ninterface PcieMsi;\n   method Bit#(1)  int_ack();\n   method Action   int_sts (Bit#(1) int_sts);\n   method Bit#(1)  msi_ack();\n   method Action   msi_num(Bit#(5)num);\n   method Action   msi_req(Bit#(1)req);\n   method Action   msi_tc(Bit#(3)tc);\nendinterface\n\n(* always_ready, always_enabled *)\ninterface PcieTlCfg;\n   method Bit#(8)  bus_number;\n   method Bit#(5)  dev_number;\n   method Action   cpl_pending(Bit#(1) cpl_pending);\n   method Action   cpl_err(Bit#(7) cpl_err);\nendinterface\n\n(* always_ready, always_enabled *)\ninterface PcieHipRst;\n   method Bit#(1) serdes_pll_locked();\n   method Bit#(1) pld_clk_inuse();\n   method Action  core_ready(Bit#(1) core_ready);\nendinterface\n\n(* always_ready, always_enabled *)\ninterface PcieTxCred;\n   method Bit#(12) datafccp();\n   method Bit#(12) datafcnp();\n   method Bit#(12) datafcp();\n   method Bit#(8)  hdrfccp();\n   method Bit#(8)  hdrfcnp();\n   method Bit#(8)  hdrfcp();\n   method Bit#(6)  fchipcons();\n   method Bit#(6)  fcinfinite();\nendinterface\n\n(* always_ready, always_enabled *)\ninterface PcieRxin;\n(* prefix=\"\", result=\"in\" *)   method Action in(Vector#(8, Bit#(1)) a);\nendinterface\n\n(* always_ready, always_enabled *)\ninterface PcieTxout;\n   method Vector#(8, Bit#(1)) out();\nendinterface\n\n(* always_ready, always_enabled *)\ninterface PcieHipStatus;\n   method Bit#(1) cor_ext_rcv;\n   method Bit#(1) cor_ext_rpl;\n   method Bit#(1) rpl;\n   method Bit#(1) dlup;\n   method Bit#(1) dlup_exit;\n   method Bit#(1) ev128ns;\n   method Bit#(1) ev1us;\n   method Bit#(1) hotrst;\n   method Bit#(4) int_status;\n   method Bit#(1) l2_exit;\n   method Bit#(4) lane_act;\n   method Bit#(5) ltssmstate;\n   method Bit#(1) rx_par_err;\n   method Bit#(2) tx_par_err;\n (* prefix=\"\", result=\"cfg_par_err\" *)  method Bit#(1) cfg_par_err;\n   method Bit#(12) ko_cpl_spc_data;\n   method Bit#(8) ko_cpl_spc_header;\nendinterface\n\ninterface PcieHipSerial;\n   interface PcieRxin rx;\n   interface PcieTxout tx;\nendinterface\n\ninterface PcieHipPipe;\n(* prefix=\"\", result=\"rxdata\" *)     method Action     rxdata    (Vector#(8, Bit#(8)) rxdata);\n(* prefix=\"\", result=\"rxdatak\" *)    method Action     rxdatak   (Vector#(8, Bit#(1)) rxdatak);\n(* prefix=\"\", result=\"rxelecidle\" *) method Action     rxelecidle(Vector#(8, Bit#(1)) rxelecidle);\n(* prefix=\"\", result=\"rxstatus\" *)   method Action     rxstatus  (Vector#(8, Bit#(3)) rxstatus);\n(* prefix=\"\", result=\"rxvalid\" *)    method Action     rxvalid   (Vector#(8, Bit#(1)) rxvalid);\n(* prefix=\"\", result=\"phystatus\" *)  method Action     phystatus (Vector#(8, Bit#(1)) phystatus);\n    method Vector#(8, Bit#(1))    rxpolarity();\n    method Vector#(8, Bit#(1))    txcompl();\n    method Vector#(8, Bit#(8))    txdata();\n    method Vector#(8, Bit#(1))    txdatak();\n    method Vector#(8, Bit#(1))    txdeemph();\n    method Vector#(8, Bit#(1))    txdetectrx();\n    method Vector#(8, Bit#(1))    txelecidle();\n    method Vector#(8, Bit#(3))    txmargin();\n    method Vector#(8, Bit#(1))    txswing();\n    method Vector#(8, Bit#(2))    powerdown();\n    method Vector#(8, Bit#(3))    eidleinfersel();\n    method Bit#(5)    sim_ltssmstate();\n    method Bit#(2)    sim_pipe_rate();\nendinterface\n\n(* always_ready, always_enabled *)\ninterface PcieHipCtrl;\n(* prefix=\"\", result=\"test_in\" *)        method Action test_in(Bit#(32) test_in);\nendinterface\n\n(* always_ready, always_enabled *)\ninterface PcieWrap#(numeric type address_width, numeric type data_width, numeric type app_width);\n   interface PcieRxSt#(app_width) rx_st;\n   interface PcieTxSt#(app_width) tx_st;\n   interface PcieMsi msi;\n   interface PcieTlCfg tl_cfg;\n   interface PcieHipRst hip_rst;\n   interface PcieTxCred tx_cred;\n   interface PcieRxin rx;\n   interface PcieTxout tx;\n   interface PcieHipStatus hip_status;\n   interface PcieHipPipe hip_pipe;\n   interface PcieHipCtrl hip_ctrl;\n   interface Clock coreclkout_hip;\n   interface Reset core_reset;\nendinterface\n\n//(* synthesize *)\nmodule mkPcieS5Wrap#(Clock clk_100Mhz, Clock clk_50Mhz, Reset npor, Reset pin_perst)(PcieWrap#(12, 32, 128));\n\n   Vector#(8, Wire#(Bit#(1))) rx_in_wires <- replicateM(mkDWire(0));\n   Vector#(8, Wire#(Bit#(8))) rxdata_wires <- replicateM(mkDWire(0));\n   Vector#(8, Wire#(Bit#(1))) rxdatak_wires <- replicateM(mkDWire(0));\n   Vector#(8, Wire#(Bit#(1))) rxelecidle_wires <- replicateM(mkDWire(0));\n   Vector#(8, Wire#(Bit#(3))) rxstatus_wires  <- replicateM(mkDWire(0));\n   Vector#(8, Wire#(Bit#(1))) rxvalid_wires   <- replicateM(mkDWire(0));\n   Vector#(8, Wire#(Bit#(1))) phystatus_wires <- replicateM(mkDWire(0));\n\n   Clock default_clock <- exposeCurrentClock;\n   Reset default_reset <- exposeCurrentReset;\n   Reset reset_high <- invertCurrentReset;\n\n   PcieS5Wrap         pcie     <- mkPPS5Wrap(clk_100Mhz, npor, pin_perst, reset_high);\n\n   Clock coreclk = pcie.coreclkout.hip;\n   Reset corerst <- mkSyncReset(1, pcie.reset.status, coreclk);\n\n   Reset core_resetn <- mkResetInverter(corerst, clocked_by coreclk);\n   AlteraPcieHipRs  hip_rs   <- mkAlteraPcieHipRs(coreclk, core_resetn);\n\n   PcieReconfigWrap pcie_cfg <- mkPcieReconfigWrap(coreclk, clk_50Mhz, npor, reset_high, reset_high);\n   XcvrReconfigWrap xcvr_cfg <- mkXcvrReconfigWrap(clk_50Mhz, reset_high, reset_high);\n\n   Reg#(Bit#(8)) bus_number_reg <- mkReg(0, clocked_by coreclk, reset_by core_resetn);\n   Reg#(Bit#(5)) dev_number_reg <- mkReg(0, clocked_by coreclk, reset_by core_resetn);\n\n   rule pertick1;\n      pcie.pld.core_ready(pcie.serdes.pll_locked);\n   endrule\n\n   rule pertick3;\n      hip_rs.dlup_exit(pcie.dl.up_exit);\n      hip_rs.hotrst_exit(pcie.hotrst.exit);\n      hip_rs.l2_exit(pcie.l2.exit);\n      hip_rs.ltssm(pcie.ltssm.state);\n   endrule\n\n   (* no_implicit_conditions *)\n   rule connectReconfigMgmt;\n      xcvr_cfg.reconfig_mgmt.read(pcie_cfg.reconfig_mgmt.read);\n      xcvr_cfg.reconfig_mgmt.write(pcie_cfg.reconfig_mgmt.write);\n      xcvr_cfg.reconfig_mgmt.address(pcie_cfg.reconfig_mgmt.address);\n      xcvr_cfg.reconfig_mgmt.writedata(pcie_cfg.reconfig_mgmt.writedata);\n      pcie_cfg.reconfig_mgmt.readdata(xcvr_cfg.reconfig_mgmt.readdata);\n      pcie_cfg.reconfig_mgmt.waitrequest(xcvr_cfg.reconfig_mgmt.waitrequest);\n   endrule\n\n   (* no_implicit_conditions *)\n   rule connectCurrentSpeed;\n      pcie_cfg.current.speed(pcie.current.speed);\n   endrule\n\n   (* no_implicit_conditions *)\n   rule connect_xcvr_reconfig;\n      pcie.reconfig.to_xcvr(xcvr_cfg.reconfig.to_xcvr);\n      xcvr_cfg.reconfig.from_xcvr(pcie.reconfig.from_xcvr);\n   endrule\n\n   (* no_implicit_conditions *)\n   rule connectBusy;\n      pcie_cfg.reconfig_b.usy(xcvr_cfg.reconfig.busy);\n   endrule\n\n   (* no_implicit_conditions *)\n   rule connectHipStatus;\n      pcie_cfg.derr.cor_ext_rcv_drv(pcie.derr.cor_ext_rcv);\n      pcie_cfg.derr.cor_ext_rpl_drv(pcie.derr.cor_ext_rpl);\n      pcie_cfg.derr.rpl_drv(pcie.derr.rpl);\n      pcie_cfg.dlup.drv(pcie.dl.up);\n      pcie_cfg.dlup.exit_drv(pcie.dl.up_exit);\n      pcie_cfg.ev128ns.drv(pcie.ev128.ns);\n      pcie_cfg.ev1us.drv(pcie.ev1.us);\n      pcie_cfg.hotrst.exit_drv(pcie.hotrst.exit);\n      pcie_cfg.int_s.tatus_drv(pcie.int_s.tatus);\n      pcie_cfg.lane.act_drv(pcie.lane.act);\n      pcie_cfg.l2.exit_drv(pcie.l2.exit);\n      pcie_cfg.ltssmstate.drv(pcie.ltssm.state);\n      pcie_cfg.tx.par_err_drv(pcie.tx_par.err);\n      pcie_cfg.rx.par_err_drv(pcie.rx_par.err);\n      pcie_cfg.cfg.par_err_drv(pcie.cfg_par.err);\n      pcie_cfg.ko.cpl_spc_data_drv(pcie.ko.cpl_spc_data);\n      pcie_cfg.ko.cpl_spc_header_drv(pcie.ko.cpl_spc_header);\n   endrule\n\n   (* no_implicit_conditions *)\n   rule power_mgmt;\n      pcie.pm.auxpwr(0);\n      pcie.pm.data(10'b0);\n      pcie.pm_e.vent(0);\n      pcie.pme.to_cr(0);\n      pcie.hpg.ctrler(5'b0);\n   endrule\n\n   C2B c2b <- mkC2B(pcie.coreclkout.hip);\n   rule pld_clk_rule;\n      pcie.pld.clk(c2b.o());\n   endrule\n\n   (* no_implicit_conditions *)\n   rule pcie_rx;\n      pcie.rx.in0(rx_in_wires[0]);\n      pcie.rx.in1(rx_in_wires[1]);\n      pcie.rx.in2(rx_in_wires[2]);\n      pcie.rx.in3(rx_in_wires[3]);\n      pcie.rx.in4(rx_in_wires[4]);\n      pcie.rx.in5(rx_in_wires[5]);\n      pcie.rx.in6(rx_in_wires[6]);\n      pcie.rx.in7(rx_in_wires[7]);\n   endrule\n\n   (* no_implicit_conditions *)\n   rule pcie_rxdata;\n      pcie.rx.data0(rxdata_wires[0]);\n      pcie.rx.data1(rxdata_wires[1]);\n      pcie.rx.data2(rxdata_wires[2]);\n      pcie.rx.data3(rxdata_wires[3]);\n      pcie.rx.data4(rxdata_wires[4]);\n      pcie.rx.data5(rxdata_wires[5]);\n      pcie.rx.data6(rxdata_wires[6]);\n      pcie.rx.data7(rxdata_wires[7]);\n   endrule\n\n   (* no_implicit_conditions *)\n   rule pcie_rxdatak;\n      pcie.rx.datak0(rxdatak_wires[0]);\n      pcie.rx.datak1(rxdatak_wires[1]);\n      pcie.rx.datak2(rxdatak_wires[2]);\n      pcie.rx.datak3(rxdatak_wires[3]);\n      pcie.rx.datak4(rxdatak_wires[4]);\n      pcie.rx.datak5(rxdatak_wires[5]);\n      pcie.rx.datak6(rxdatak_wires[6]);\n      pcie.rx.datak7(rxdatak_wires[7]);\n   endrule\n\n   (* no_implicit_conditions *)\n   rule pcie_rxelecidle;\n      pcie.rx.elecidle0(rxelecidle_wires[0]);\n      pcie.rx.elecidle1(rxelecidle_wires[1]);\n      pcie.rx.elecidle2(rxelecidle_wires[2]);\n      pcie.rx.elecidle3(rxelecidle_wires[3]);\n      pcie.rx.elecidle4(rxelecidle_wires[4]);\n      pcie.rx.elecidle5(rxelecidle_wires[5]);\n      pcie.rx.elecidle6(rxelecidle_wires[6]);\n      pcie.rx.elecidle7(rxelecidle_wires[7]);\n   endrule\n\n   (* no_implicit_conditions *)\n   rule pcie_rxstatus;\n      pcie.rx.status0(rxstatus_wires[0]);\n      pcie.rx.status1(rxstatus_wires[1]);\n      pcie.rx.status2(rxstatus_wires[2]);\n      pcie.rx.status3(rxstatus_wires[3]);\n      pcie.rx.status4(rxstatus_wires[4]);\n      pcie.rx.status5(rxstatus_wires[5]);\n      pcie.rx.status6(rxstatus_wires[6]);\n      pcie.rx.status7(rxstatus_wires[7]);\n   endrule\n\n   (* no_implicit_conditions *)\n   rule pcie_rxvalid;\n      pcie.rx.valid0(rxvalid_wires[0]);\n      pcie.rx.valid1(rxvalid_wires[1]);\n      pcie.rx.valid2(rxvalid_wires[2]);\n      pcie.rx.valid3(rxvalid_wires[3]);\n      pcie.rx.valid4(rxvalid_wires[4]);\n      pcie.rx.valid5(rxvalid_wires[5]);\n      pcie.rx.valid6(rxvalid_wires[6]);\n      pcie.rx.valid7(rxvalid_wires[7]);\n   endrule\n\n   (* no_implicit_conditions *)\n   rule pcie_phystatus;\n      pcie.phy.status0(phystatus_wires[0]);\n      pcie.phy.status1(phystatus_wires[1]);\n      pcie.phy.status2(phystatus_wires[2]);\n      pcie.phy.status3(phystatus_wires[3]);\n      pcie.phy.status4(phystatus_wires[4]);\n      pcie.phy.status5(phystatus_wires[5]);\n      pcie.phy.status6(phystatus_wires[6]);\n      pcie.phy.status7(phystatus_wires[7]);\n   endrule\n\n   rule capture_deviceid(pcie.tl.cfg_add == 4'hF);\n      bus_number_reg <= pcie.tl.cfg_ctl[12:5];\n      dev_number_reg <= pcie.tl.cfg_ctl[4:0];\n   endrule\n\n   method Clock coreclkout_hip;\n      return pcie.coreclkout.hip;\n   endmethod\n\n   method Reset core_reset;\n      return corerst;\n   endmethod\n\n   interface PcieTlCfg tl_cfg;\n      method Bit#(8) bus_number();\n         return bus_number_reg;\n      endmethod\n      method Bit#(5) dev_number();\n         return dev_number_reg;\n      endmethod\n      method cpl_pending = pcie.cpl.pending;\n      method cpl_err = pcie.cpl.err;\n   endinterface\n\n   interface PcieRxSt rx_st;\n      method Bit#(1)   sop();   return pcie.rx_st.sop0;   endmethod\n      method Bit#(1)   eop();   return pcie.rx_st.eop0;   endmethod\n      method Bit#(128) data();  return pcie.rx_st.data0;  endmethod\n      method Bit#(1)   valid(); return pcie.rx_st.valid0; endmethod\n      method Bit#(1)   err();   return pcie.rx_st.err0;   endmethod\n      method Bit#(2)   empty(); return pcie.rx_st.empty0; endmethod\n      method Bit#(8)   bar ();  return pcie.rx_st.bar0; endmethod\n      method Bit#(16)  be();    return pcie.rx_st.be0;  endmethod\n      method ready = pcie.rx_st.ready0;\n      method mask  = pcie.rx_st.mask0;\n   endinterface\n\n   interface PcieTxSt tx_st;\n      method Bit#(1) ready (); return pcie.tx_st.ready0; endmethod\n      method sop   = pcie.tx_st.sop0    ;\n      method eop   = pcie.tx_st.eop0    ;\n      method valid = pcie.tx_st.valid0  ;\n      method err   = pcie.tx_st.err0    ;\n      method empty = pcie.tx_st.empty0  ;\n      method data  = pcie.tx_st.data0   ;\n   endinterface\n\n   interface PcieMsi msi;\n      method Bit#(1) int_ack(); return pcie.app.int_ack; endmethod\n      method Bit#(1) msi_ack(); return pcie.app.msi_ack; endmethod\n\n      method int_sts = pcie.app.int_sts;\n      method msi_num = pcie.app.msi_num;\n      method msi_req = pcie.app.msi_req;\n      method msi_tc = pcie.app.msi_tc;\n   endinterface\n\n   interface PcieHipRst hip_rst;\n      method Bit#(1) serdes_pll_locked(); return pcie.serdes.pll_locked; endmethod\n      method Bit#(1) pld_clk_inuse(); return pcie.pld.clk_inuse; endmethod\n      method core_ready = pcie.pld.core_ready;\n   endinterface\n\n   interface PcieTxCred tx_cred;\n      method Bit#(12) datafccp(); return pcie.tx_cred.datafccp; endmethod\n      method Bit#(12) datafcnp(); return pcie.tx_cred.datafcnp; endmethod\n      method Bit#(12) datafcp();  return pcie.tx_cred.datafcp;  endmethod\n      method Bit#(8) hdrfccp();   return pcie.tx_cred.hdrfccp;  endmethod\n      method Bit#(8) hdrfcnp();   return pcie.tx_cred.hdrfcnp;  endmethod\n      method Bit#(8) hdrfcp();    return pcie.tx_cred.hdrfcp;   endmethod\n      method Bit#(6) fchipcons(); return pcie.tx_cred.fchipcons; endmethod\n      method Bit#(6) fcinfinite();return pcie.tx_cred.fcinfinite;endmethod\n   endinterface\n\n   interface PcieRxin rx;\n      method Action in(Vector#(8, Bit#(1)) a);\n         writeVReg(rx_in_wires, a);\n      endmethod\n   endinterface\n\n   interface PcieTxout tx;\n      method Vector#(8, Bit#(1)) out();\n         Vector#(8, Bit#(1)) ret_val;\n         ret_val[0] = pcie.tx.out0;\n         ret_val[1] = pcie.tx.out1;\n         ret_val[2] = pcie.tx.out2;\n         ret_val[3] = pcie.tx.out3;\n         ret_val[4] = pcie.tx.out4;\n         ret_val[5] = pcie.tx.out5;\n         ret_val[6] = pcie.tx.out6;\n         ret_val[7] = pcie.tx.out7;\n         return ret_val;\n      endmethod\n   endinterface\n\n   interface PcieHipStatus hip_status;\n      method Bit#(1) cor_ext_rcv; return pcie.derr.cor_ext_rcv; endmethod\n      method Bit#(1) cor_ext_rpl; return pcie.derr.cor_ext_rpl; endmethod\n      method Bit#(1) rpl;         return pcie.derr.rpl;         endmethod\n      method Bit#(1) dlup;        return pcie.dl.up;            endmethod\n      method Bit#(1) dlup_exit;   return pcie.dl.up_exit;       endmethod\n      method Bit#(1) ev128ns;     return pcie.ev128.ns;         endmethod\n      method Bit#(1) ev1us;       return pcie.ev1.us;           endmethod\n      method Bit#(1) hotrst;      return pcie.hotrst.exit;      endmethod\n      method Bit#(4) int_status;  return pcie.int_s.tatus;      endmethod\n      method Bit#(1) l2_exit;     return pcie.l2.exit;          endmethod\n      method Bit#(4) lane_act;    return pcie.lane.act;         endmethod\n      method Bit#(5) ltssmstate;  return pcie.ltssm.state;      endmethod\n      method Bit#(1) rx_par_err;  return pcie.rx_par.err;       endmethod\n      method Bit#(2) tx_par_err;  return pcie.tx_par.err;       endmethod\n      method Bit#(1) cfg_par_err; return pcie.cfg_par.err;      endmethod\n      method Bit#(12) ko_cpl_spc_data; return pcie.ko.cpl_spc_data; endmethod\n      method Bit#(8) ko_cpl_spc_header;return pcie.ko.cpl_spc_header;endmethod\n   endinterface\n\n   interface PcieHipPipe hip_pipe;\n      method Action rxdata(Vector#(8, Bit#(8)) a);\n         writeVReg(rxdata_wires, a);\n      endmethod\n\n      method Action rxdatak(Vector#(8, Bit#(1)) a);\n         writeVReg(rxdatak_wires, a);\n      endmethod\n\n      method Action rxelecidle(Vector#(8, Bit#(1)) a);\n         writeVReg(rxelecidle_wires, a);\n      endmethod\n\n      method Action rxstatus(Vector#(8, Bit#(3)) a);\n         writeVReg(rxstatus_wires, a);\n      endmethod\n\n      method Action rxvalid(Vector#(8, Bit#(1)) a);\n         writeVReg(rxvalid_wires, a);\n      endmethod\n\n      method Action phystatus(Vector#(8, Bit#(1)) a);\n         writeVReg(phystatus_wires, a);\n      endmethod\n\n      method rxpolarity();\n         Vector#(8, Bit#(1)) retval;\n         retval = unpack({pcie.rx.polarity7,\n                          pcie.rx.polarity6,\n                          pcie.rx.polarity5,\n                          pcie.rx.polarity4,\n                          pcie.rx.polarity3,\n                          pcie.rx.polarity2,\n                          pcie.rx.polarity1,\n                          pcie.rx.polarity0});\n         return retval;\n      endmethod\n\n      method txcompl();\n         Vector#(8, Bit#(1)) retval;\n         retval = unpack({pcie.tx.compl7,\n                          pcie.tx.compl6,\n                          pcie.tx.compl5,\n                          pcie.tx.compl4,\n                          pcie.tx.compl3,\n                          pcie.tx.compl2,\n                          pcie.tx.compl1,\n                          pcie.tx.compl0});\n         return retval;\n      endmethod\n\n      method txdata();\n         Vector#(8, Bit#(8)) retval;\n         retval = unpack({pcie.tx.data7,\n                          pcie.tx.data6,\n                          pcie.tx.data5,\n                          pcie.tx.data4,\n                          pcie.tx.data3,\n                          pcie.tx.data2,\n                          pcie.tx.data1,\n                          pcie.tx.data0});\n         return retval;\n      endmethod\n\n      method txdatak();\n         Vector#(8, Bit#(1)) retval;\n         retval = unpack({pcie.tx.datak7,\n                          pcie.tx.datak6,\n                          pcie.tx.datak5,\n                          pcie.tx.datak4,\n                          pcie.tx.datak3,\n                          pcie.tx.datak2,\n                          pcie.tx.datak1,\n                          pcie.tx.datak0});\n         return retval;\n      endmethod\n\n      method txdeemph();\n         Vector#(8, Bit#(1)) retval;\n         retval = unpack({pcie.tx.deemph7,\n                          pcie.tx.deemph6,\n                          pcie.tx.deemph5,\n                          pcie.tx.deemph4,\n                          pcie.tx.deemph3,\n                          pcie.tx.deemph2,\n                          pcie.tx.deemph1,\n                          pcie.tx.deemph0});\n         return retval;\n      endmethod\n\n      method txdetectrx();\n         Vector#(8, Bit#(1)) retval;\n         retval = unpack({pcie.tx.detectrx7,\n                          pcie.tx.detectrx6,\n                          pcie.tx.detectrx5,\n                          pcie.tx.detectrx4,\n                          pcie.tx.detectrx3,\n                          pcie.tx.detectrx2,\n                          pcie.tx.detectrx1,\n                          pcie.tx.detectrx0});\n         return retval;\n      endmethod\n\n      method txelecidle();\n         Vector#(8, Bit#(1)) retval;\n         retval = unpack({pcie.tx.elecidle7,\n                          pcie.tx.elecidle6,\n                          pcie.tx.elecidle5,\n                          pcie.tx.elecidle4,\n                          pcie.tx.elecidle3,\n                          pcie.tx.elecidle2,\n                          pcie.tx.elecidle1,\n                          pcie.tx.elecidle0});\n         return retval;\n      endmethod\n\n      method txmargin();\n         Vector#(8, Bit#(3)) retval;\n         retval = unpack({pcie.tx.margin7,\n                          pcie.tx.margin6,\n                          pcie.tx.margin5,\n                          pcie.tx.margin4,\n                          pcie.tx.margin3,\n                          pcie.tx.margin2,\n                          pcie.tx.margin1,\n                          pcie.tx.margin0});\n         return retval;\n      endmethod\n\n      method txswing();\n         Vector#(8, Bit#(1)) retval;\n         retval = unpack({pcie.tx.swing7,\n                          pcie.tx.swing6,\n                          pcie.tx.swing5,\n                          pcie.tx.swing4,\n                          pcie.tx.swing3,\n                          pcie.tx.swing2,\n                          pcie.tx.swing1,\n                          pcie.tx.swing0});\n         return retval;\n      endmethod\n\n      method powerdown();\n         Vector#(8, Bit#(2)) retval;\n         retval = unpack({pcie.power.down7,\n                          pcie.power.down6,\n                          pcie.power.down5,\n                          pcie.power.down4,\n                          pcie.power.down3,\n                          pcie.power.down2,\n                          pcie.power.down1,\n                          pcie.power.down0});\n         return retval;\n      endmethod\n\n      method eidleinfersel();\n         Vector#(8, Bit#(3)) retval;\n         retval = unpack({pcie.eidle.infersel7,\n                          pcie.eidle.infersel6,\n                          pcie.eidle.infersel5,\n                          pcie.eidle.infersel4,\n                          pcie.eidle.infersel3,\n                          pcie.eidle.infersel2,\n                          pcie.eidle.infersel1,\n                          pcie.eidle.infersel0});\n         return retval;\n      endmethod\n\n      method sim_ltssmstate();\n         return pcie.sim.ltssmstate;\n      endmethod\n\n      method sim_pipe_rate();\n         return pcie.sim.pipe_rate;\n      endmethod\n   endinterface\n\n   interface PcieHipCtrl hip_ctrl;\n      method test_in = pcie.test.in;\n   endinterface\nendmodule\n\n// Altera PCIe HIP Reset\n\n(* always_ready, always_enabled *)\ninterface AlteraPcieHipRs;\n(* prefix=\"\", result=\"dlup_exit\" *)   method Action dlup_exit(Bit#(1) dlup_exit);\n(* prefix=\"\", result=\"hotrst_exit\" *) method Action hotrst_exit(Bit#(1) hotrst_exit);\n(* prefix=\"\", result=\"l2_exit\" *)     method Action l2_exit(Bit#(1) l2_exit);\n(* prefix=\"\", result=\"ltssm\" *)       method Action ltssm(Bit#(5) ltssm);\n   method Reset app_rstn;\nendinterface\n\ntypedef enum {\n   LTSSM_POL = 5'b00010,\n   LTSSM_CPL = 5'b00011,\n   LTSSM_DET = 5'b00000,\n   LTSSM_RCV = 5'b01100,\n   LTSSM_DIS = 5'b10000\n} LTSSM deriving (Bits, Eq);\n\ntypedef enum {\n   RCV_TIMEOUT = 23'd6000000\n} TIMEOUT deriving (Bits, Eq);\n\ntypedef enum {\n   RSTN_CNT_MAX = 11'h400,\n   RSTN_CTN_MAX_SIM = 11'h20\n} RSTN_CNT deriving (Bits, Eq);\n\n//(* synthesize, no_default_clock, no_default_reset, clock_prefix=\"\", reset_prefix=\"\" *)\n(* synthesize *)\n(* always_ready, always_enabled, no_default_clock, no_default_reset, clock_prefix=\"\", reset_prefix=\"\" *)\nmodule mkAlteraPcieHipRs#(Clock pld_clk, Reset npor)(AlteraPcieHipRs);\n   Reset npor_sync_pld_clk          <- mkAsyncReset(3, npor, pld_clk);\n   Reg #(Bit#(5)) ltssm_r           <- mkReg(0, clocked_by(pld_clk), reset_by(npor_sync_pld_clk));\n   Reg #(Bit#(1)) dlup_exit_r       <- mkReg(1, clocked_by(pld_clk), reset_by(npor_sync_pld_clk));\n   Reg #(Bit#(1)) hotrst_exit_r     <- mkReg(1, clocked_by(pld_clk), reset_by(npor_sync_pld_clk));\n   Reg #(Bit#(1)) l2_exit_r         <- mkReg(1, clocked_by(pld_clk), reset_by(npor_sync_pld_clk));\n   Reg #(Bit#(11)) rsnt_cntn        <- mkReg(0, clocked_by(pld_clk), reset_by(npor_sync_pld_clk));\n   Reg #(Bit#(23)) recovery_cnt     <- mkReg(0, clocked_by(pld_clk), reset_by(npor_sync_pld_clk));\n   Reg #(Bit#(1)) recovery_rst      <- mkReg(0, clocked_by(pld_clk), reset_by(npor_sync_pld_clk));\n   Reg #(Bit#(1)) exits_r           <- mkReg(0, clocked_by(pld_clk), reset_by(npor_sync_pld_clk));\n\n   let app_rstn_out <- mkReset(0, True, pld_clk, clocked_by(pld_clk), reset_by(npor_sync_pld_clk));\n\n   rule exit_v ((l2_exit_r == 1'b0) || (hotrst_exit_r == 1'b0) || (dlup_exit_r == 1'b0) || (ltssm_r == pack(LTSSM_DIS)) || (recovery_rst == 1'b1));\n      exits_r <= 1'b1;\n   endrule\n\n   //Delay HIP reset upon npor\n   rule delay_hip0 if (exits_r == 1'b1);\n      rsnt_cntn <= 11'h3f0;\n   endrule\n\n   rule delay_hip1 if (exits_r != 1'b1);\n      rsnt_cntn <= rsnt_cntn + 11'h1;\n   endrule\n\n   rule delay_hip2 if ((exits_r != 1'b1) && (rsnt_cntn == pack(RSTN_CNT_MAX)));\n      app_rstn_out.assertReset;\n   endrule\n\n   // Monitor if LTSSM is frozen in RECOVERY state\n   // Issue reset if timeout RCV_TIMEOUT\n   rule recovery_cnt0 ((recovery_cnt != pack(RCV_TIMEOUT)) && (ltssm_r != pack(LTSSM_RCV)));\n      recovery_cnt <= 23'b0;\n   endrule\n\n   rule recovery_cnt1 ((recovery_cnt == pack(RCV_TIMEOUT)) && (ltssm_r == pack(LTSSM_RCV)));\n      recovery_cnt <= recovery_cnt;\n   endrule\n\n   rule recovery_cnt2 ((recovery_cnt != pack(RCV_TIMEOUT)) && (ltssm_r == pack(LTSSM_RCV)));\n      recovery_cnt <= recovery_cnt + 23'h1;\n   endrule\n\n   rule recovery_rst0 (recovery_cnt == pack(RCV_TIMEOUT));\n      recovery_rst <= 1'b1;\n   endrule\n\n   rule recovery_rst1 (ltssm_r != pack(LTSSM_RCV) && recovery_cnt != pack(RCV_TIMEOUT));\n      recovery_rst <= 1'b0;\n   endrule\n\n   // interface\n   method Action dlup_exit(Bit#(1) v);\n      dlup_exit_r <= v;\n   endmethod\n\n   method Action ltssm(Bit#(5) v);\n      ltssm_r <= v;\n   endmethod\n\n   method Action l2_exit(Bit#(1) v);\n      l2_exit_r <= v;\n   endmethod\n\n   method Action hotrst_exit(Bit#(1) v);\n      hotrst_exit_r <= v;\n   endmethod\n\n   method app_rstn;\n      return app_rstn_out.new_rst;\n   endmethod\nendmodule\n\n"
  },
  {
    "path": "bsv/PS7LIB.bsv",
    "content": "\n// Copyright (c) 2013 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n`include \"ConnectalProjectConfig.bsv\"\nimport BuildVector::*;\nimport Clocks::*;\nimport DefaultValue::*;\nimport GetPut::*;\nimport Connectable::*;\nimport ConnectableWithTrace::*;\nimport Bscan::*;\nimport Vector::*;\nimport PPS7LIB::*;\nimport AxiMasterSlave::*;\nimport AxiDma::*;\nimport XilinxCells::*;\nimport ConnectalXilinxCells::*;\nimport ConnectalClocks::*;\nimport AxiBits::*;\nimport AxiGather::*;\n\n(* always_ready, always_enabled *)\ninterface Bidir#(numeric type data_width);\n    method Action             i(Bit#(data_width) v);\n    method Bit#(data_width)   o();\n    method Bit#(data_width)   t();\nendinterface\n\ninterface PS7LIB;\n`ifdef PS7EXTENDED\n    interface Vector#(2, Pps7Emiocan)  can;\n    interface Vector#(4, Pps7Dma)  dma;\n    interface Vector#(2, Pps7Emioenet) enet;\n    interface Pps7Event            event_;\n//    interface Vector#(4,Pps7Fclk_clktrig)fclk_clktrig;\n//    interface Pps7Fpga             fpga;\n    interface Pps7Ftmd             ftmd;\n    interface Pps7Ftmt             ftmt;\n    interface Pps7Emiopjtag            pjtag;\n    interface Vector#(2, Pps7Emiosdio) sdio;\n    interface Vector#(2, Pps7Emiospi)  spi;\n//    interface Pps7Sram             sram;\n    interface Pps7Emiotrace            trace;\n    interface Vector#(2, Pps7Emiottc)  ttc;\n    interface Vector#(2, Pps7Emiouart) uart;\n    interface Vector#(2, Pps7Emiousb)  usb;\n    interface Pps7Emiowdt              wdt;\n`endif\n    interface Pps7Ddr              ddr;\n    method Bit#(4)     fclkclk();\n    method Action      fclkclktrign(Bit#(4) v);\n    method Bit#(4)     fclkresetn();\n    method Action      fpgaidlen(Bit#(1) v);\n    interface Pps7Emiogpio             gpio;\n    interface Vector#(2, Pps7Emioi2c)  i2c;\n    interface Pps7Irq              irq;\n    interface Inout#(Bit#(54))     mio;\n    interface Pps7Ps               ps;\n\n    interface Vector#(2, AxiMasterCommon#(32,32,12)) m_axi_gp;\n    interface Vector#(2, AxiSlaveCommon#(32,32,6,Empty)) s_axi_gp;\n    interface Vector#(4, AxiSlaveCommon#(32,64,6,HPType)) s_axi_hp;\n    interface AxiSlaveCommon#(32,64,3,ACPType) s_axi_acp;\nendinterface\n\nmodule mkPS7LIB#(Clock axi_clock, Reset axi_reset)(PS7LIB);\n    PPS7LIB foo <- mkPPS7LIB(\n        axi_clock, axi_clock, axi_clock, axi_clock, axi_clock, axi_clock, axi_clock, axi_clock,\n        axi_clock, axi_reset, axi_reset, axi_reset, axi_reset, axi_reset, axi_reset, axi_reset,\n        axi_reset, axi_reset);\n`ifdef PS7EXTENDED\n    Vector#(2, Pps7Emiocan)     vcan;\n    Vector#(4, Pps7Dma)     vdma;\n    Vector#(2, Pps7Emioenet)     venet;\n    Vector#(2, Pps7Emiosdio)     vsdio;\n    Vector#(2, Pps7Emiospi)     vspi;\n    Vector#(2, Pps7Emiottc)     vttc;\n    Vector#(2, Pps7Emiouart)     vuart;\n    Vector#(2, Pps7Emiousb)     vusb;\n`endif\n    Vector#(2, Pps7Emioi2c)     vi2c;\n    Vector#(2, AxiMasterCommon#(32,32,12)) vtopm_axi_gp;\n    Vector#(2, AxiSlaveCommon#(32,32,6,Empty)) vtops_axi_gp;\n    Vector#(1, AxiSlaveCommon#(32,64,3,ACPType)) vtops_axi_acp;\n    Vector#(4, AxiSlaveCommon#(32,64,6,HPType)) vtops_axi_hp;\n\n`ifdef PS7EXTENDED\n    vcan[0] = foo.emiocan0;\n    vcan[1] = foo.emiocan1;\n    vdma[0] = foo.dma0;\n    vdma[1] = foo.dma1;\n    vdma[2] = foo.dma2;\n    vdma[3] = foo.dma3;\n    venet[0] = foo.emioenet0;\n    venet[1] = foo.emioenet1;\n    vsdio[0] = foo.emiosdio0;\n    vsdio[1] = foo.emiosdio1;\n    vspi[0] = foo.emiospi0;\n    vspi[1] = foo.emiospi1;\n    vttc[0] = foo.emiottc0;\n    vttc[1] = foo.emiottc1;\n    vuart[0] = foo.emiouart0;\n    vuart[1] = foo.emiouart1;\n    vusb[0] = foo.emiousb0;\n    vusb[1] = foo.emiousb1;\n`endif\n    vi2c[0] = foo.emioi2c0;\n    vi2c[1] = foo.emioi2c1;\n    vtopm_axi_gp[0] <- mkAxi3MasterGather(foo.maxigp0, clocked_by axi_clock, reset_by axi_reset);\n    vtopm_axi_gp[1] <- mkAxi3MasterGather(foo.maxigp1, clocked_by axi_clock, reset_by axi_reset);\n    vtops_axi_gp[0] <- mkAxi3SlaveGather(foo.saxigp0, clocked_by axi_clock, reset_by axi_reset);\n    vtops_axi_gp[1] <- mkAxi3SlaveGather(foo.saxigp1, clocked_by axi_clock, reset_by axi_reset);\n    vtops_axi_acp[0] <- mkAxi3SlaveGather(foo.saxiacp, clocked_by axi_clock, reset_by axi_reset);\n    vtops_axi_hp[0] <- mkAxi3SlaveGather(foo.saxihp0, clocked_by axi_clock, reset_by axi_reset);\n    vtops_axi_hp[1] <- mkAxi3SlaveGather(foo.saxihp1, clocked_by axi_clock, reset_by axi_reset);\n    vtops_axi_hp[2] <- mkAxi3SlaveGather(foo.saxihp2, clocked_by axi_clock, reset_by axi_reset);\n    vtops_axi_hp[3] <- mkAxi3SlaveGather(foo.saxihp3, clocked_by axi_clock, reset_by axi_reset);\n    Wire#(Bit#(1)) fpgaidlenw <- mkDWire(1);\n    rule fpgaidle;\n       foo.fpgaidlen(fpgaidlenw);\n    endrule\n    rule misc;\n       foo.emiosramintin(0);\n       // UG585 \"fclkclktrign is currently not supported and must be tied to ground\"\n       foo.fclkclktrign(0);\n    endrule\n\n`ifdef PS7EXTENDED\n    interface Pps7Can can = vcan;\n    interface Pps7Dma     dma = vdma;\n    interface Pps7Enet     enet = venet;\n    interface Pps7Sdio    sdio = vsdio;\n    interface Pps7Spi    spi = vspi;\n    interface Pps7Ttc    ttc = vttc;\n    interface Pps7Uart    uart = vuart;\n    interface Pps7Usb    usb = vusb;\n    interface Pps7Event     event_ = foo.event_;\n//    interface Pps7Fpga     fpga = foo.fpga;\n    interface Pps7Ftmd     ftmd = foo.ftmd;\n    interface Pps7Ftmt     ftmt = foo.ftmt;\n    interface Pps7Pjtag     pjtag = foo.emiopjtag;\n//    interface Pps7Sram     sram = foo.sram;\n    interface Pps7Emiotrace     trace = foo.emiotrace;\n    interface Pps7Wdt     wdt = foo.emiowdt;\n`endif\n    interface i2c = vi2c;\n    interface ddr = foo.ddr;\n    interface fclkclk = foo.fclkclk;\n    interface fclkresetn = foo.fclkresetn;\n    method Action      fclkclktrign(Bit#(4) v);\n        foo.fclkclktrign(v);\n    endmethod\n    method Action      fpgaidlen(Bit#(1) v);\n       fpgaidlenw <= v;\n    endmethod\n    interface gpio = foo.emiogpio;\n    interface irq = foo.irq;\n    interface mio = foo.mio;\n    interface ps = foo.ps;\n\n    interface m_axi_gp = vtopm_axi_gp;\n    interface s_axi_gp = vtops_axi_gp;\n    interface s_axi_hp = vtops_axi_hp;\n    interface s_axi_acp = vtops_axi_acp[0];\nendmodule\n\ninterface ZynqPins;\n    (* prefix=\"DDR_Addr\" *) interface Inout#(Bit#(15))     a;\n    (* prefix=\"DDR_BankAddr\" *) interface Inout#(Bit#(3))     ba;\n    (* prefix=\"DDR_CAS_n\" *) interface Inout#(Bit#(1))     casb;\n    (* prefix=\"DDR_CKE\" *) interface Inout#(Bit#(1))     cke;\n    (* prefix=\"DDR_CS_n\" *) interface Inout#(Bit#(1))     csb;\n    (* prefix=\"DDR_Clk_n\" *) interface Inout#(Bit#(1))     ckn;\n    (* prefix=\"DDR_Clk_p\" *) interface Inout#(Bit#(1))     ck;\n    (* prefix=\"DDR_DM\" *) interface Inout#(Bit#(4))     dm;\n    (* prefix=\"DDR_DQ\" *) interface Inout#(Bit#(32))     dq;\n    (* prefix=\"DDR_DQS_n\" *) interface Inout#(Bit#(4))     dqsn;\n    (* prefix=\"DDR_DQS_p\" *) interface Inout#(Bit#(4))     dqs;\n    (* prefix=\"DDR_DRSTB\" *) interface Inout#(Bit#(1))     drstb;\n    (* prefix=\"DDR_ODT\" *) interface Inout#(Bit#(1))     odt;\n    (* prefix=\"DDR_RAS_n\" *) interface Inout#(Bit#(1))     rasb;\n    (* prefix=\"FIXED_IO_ddr_vrn\" *) interface Inout#(Bit#(1))     vrn;\n    (* prefix=\"FIXED_IO_ddr_vrp\" *) interface Inout#(Bit#(1))     vrp;\n    (* prefix=\"DDR_WEB\" *) interface Inout#(Bit#(1))     web;\n    (* prefix=\"MIO\" *)\n    interface Inout#(Bit#(54))       mio;\n    (* prefix=\"FIXED_IO_ps\" *)\n    interface Pps7Ps ps;\nendinterface\n\ninterface PS7;\n    (* prefix=\"\" *)\n    interface ZynqPins pins;\n    interface Vector#(2, AxiMasterCommon#(32,32,12))     m_axi_gp;\n    interface Vector#(2, AxiSlaveCommon#(32,32,6,Empty)) s_axi_gp;\n    interface Vector#(4, AxiSlaveCommon#(32,64,6,HPType))   s_axi_hp;\n    interface Vector#(1, AxiSlaveCommon#(32,64,3,ACPType))   s_axi_acp;\n    method Action                             interrupt(Bit#(1) v);\n    interface Vector#(4, Clock) fclkclk;\n    interface Vector#(4, Reset) fclkreset;\n    interface Vector#(2, Pps7Emioi2c)  i2c;\n    interface Clock portalClock;\n    interface Reset portalReset;\n    interface Clock derivedClock;\n    interface Reset derivedReset;\n`ifdef PS7EXTENDED      \n    interface Pps7Emiosdio emiosdio1;   \n    interface Pps7Emiospi  emiospi0;\n`endif\nendinterface\n\nmodule mkPS7#(Clock axiClock)(PS7);\n   // B2C converts a bit to a clock, enabling us to break the apparent cycle\n   Vector#(4, B2C) b2c <- replicateM(mkB2C());\n\n   // need the bufg here to reduce clock skew\n   module mkBufferedClock#(Integer i)(Clock); let c <- mkClockBUFG(clocked_by b2c[i].c); return c; endmodule\n   module mkBufferedReset#(Integer i)(Reset); let r <- mkResetBUFG(clocked_by b2c[i].c, reset_by b2c[i].r); return r; endmodule\n   Vector#(4, Clock) fclk <- genWithM(mkBufferedClock);\n   Vector#(4, Reset) freset <- genWithM(mkBufferedReset);\n\n`ifndef TOP_SOURCES_PORTAL_CLOCK\n   Clock single_clock = fclk[0];\n`ifdef ZYNQ_NO_RESET\n   freset[0]          = noReset;\n`endif\n   let single_reset   = freset[0];\n`else\n   //Clock axiClockBuf <- mkClockBUFG(clocked_by axiClock);\n   Clock axiClockBuf = axiClock;\n   Clock single_clock = axiClockBuf;\n   Reset axiResetUnbuffered <- mkSyncReset(10, freset[0], single_clock);\n   Reset axiReset <- mkResetBUFG(clocked_by axiClockBuf, reset_by axiResetUnbuffered);\n   let single_reset   = axiReset;\n`endif\n\n   ClockGenerator7Params clockParams = defaultValue;\n   // input clock 200MHz for speed grade -2, 100MHz for speed grade -1\n   // fpll needs to be in the range 600MHz - 1200MHz for either input clock\n   //\n   // fclkin = 1e9 / mainClockPeriod\n   // fpll = 1e9 = mult_f * 1e9 / mainClockPeriod\n   // mult_f = mainClockPeriod\n   //\n   // fclkout0 = 1e9 / divide_f = 1e9 / derivedClockPeriod\n   // divide_f = derivedClockPeriod\n   //\n   clockParams.clkfbout_mult_f       = mainClockPeriod;\n   clockParams.clkfbout_phase     = 0.0;\n   clockParams.clkfbout_phase     = 0.0;\n   clockParams.clkin1_period      = mainClockPeriod;\n   clockParams.clkout0_divide_f   = derivedClockPeriod;\n   clockParams.clkout0_duty_cycle = 0.5;\n   clockParams.clkout0_phase      = 0.0000;\n   clockParams.clkout0_buffer     = True;\n   clockParams.clkin_buffer = False;\n   ClockGenerator7   clockGen <- mkClockGenerator7(clockParams, clocked_by single_clock, reset_by single_reset);\n   let derived_clock = clockGen.clkout0;\n   let derived_reset_unbuffered <- mkSyncReset(10, single_reset, derived_clock);\n   let derived_reset <- mkResetBUFG(clocked_by derived_clock, reset_by derived_reset_unbuffered);\n\n   PS7LIB ps7 <- mkPS7LIB(single_clock, single_reset, clocked_by single_clock, reset_by single_reset);\n\n   // this rule connects the fclkclk wires to the clock net via B2C\n   for (Integer i = 0; i < 4; i = i + 1) begin\n      ReadOnly#(Bit#(4)) fclkb;\n      ReadOnly#(Bit#(4)) fclkresetnb;\n      fclkb       <- mkNullCrossingWire(b2c[i].c, ps7.fclkclk);\n      fclkresetnb <- mkNullCrossingWire(b2c[i].c, ps7.fclkresetn);\n`ifndef BSV_POSITIVE_RESET\n      let resetValue = 0;\n`else\n      let resetValue = 1;\n`endif\n      rule b2c_rule1;\n\t b2c[i].inputclock(fclkb[i]);\n\t b2c[i].inputreset(fclkresetnb[i] == 0 ? resetValue : ~resetValue);\n      endrule\n      rule issue_rule;\n         ps7.s_axi_hp[i].extra.rdissuecap1en(0);\n         ps7.s_axi_hp[i].extra.wrissuecap1en(0);\n      endrule\n   end\n\n   IDELAYCTRL idel <- mkIDELAYCTRL(2, clocked_by fclk[3], reset_by freset[0]);\n\n    rule arb_rule;\n        ps7.ddr.arb(4'b0);\n    endrule\n\n`ifdef PS7EXTENDED         \n    interface Pps7Emiosdio emiosdio1 = ps7.sdio[1];\n    interface Pps7Emiospi  emiospi0  = ps7.spi[0];\n`endif      \n    interface ZynqPins pins;\n    interface a = ps7.ddr.a;\n    interface ba = ps7.ddr.ba;\n    interface casb = ps7.ddr.casb;\n    interface cke = ps7.ddr.cke;\n    interface csb = ps7.ddr.csb;\n    interface ckn = ps7.ddr.ckn;\n    interface ck = ps7.ddr.ckp;\n    interface dm = ps7.ddr.dm;\n    interface dq = ps7.ddr.dq;\n    interface dqsn = ps7.ddr.dqsn;\n    interface dqs = ps7.ddr.dqsp;\n    interface drstb = ps7.ddr.drstb;\n    interface odt = ps7.ddr.odt;\n    interface rasb = ps7.ddr.rasb;\n    interface vrn = ps7.ddr.vrn;\n    interface vrp = ps7.ddr.vrp;\n    interface web = ps7.ddr.web;\n    interface mio = ps7.mio;\n    interface ps = ps7.ps;\n    endinterface\n    interface m_axi_gp = ps7.m_axi_gp;\n    interface s_axi_gp = ps7.s_axi_gp;\n    interface s_axi_hp = ps7.s_axi_hp;\n    interface fclkclk = fclk;\n    interface fclkreset = freset;\n`ifndef TOP_SOURCES_PORTAL_CLOCK\n    interface portalClock = fclk[0];\n    interface portalReset = freset[0];\n`else\n    interface portalClock = axiClockBuf;\n    interface portalReset = axiReset;\n`endif\n    interface derivedClock = derived_clock;\n    interface derivedReset = derived_reset;\n    method Action interrupt(Bit#(1) v);\n        ps7.irq.f2p({19'b0, v});\n    endmethod\n    interface i2c = ps7.i2c;\n   interface s_axi_acp = vec(ps7.s_axi_acp);\nendmodule\n"
  },
  {
    "path": "bsv/PS7Trace.bsv",
    "content": "// Copyright (c) 2013 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\nimport ConnectalConfig::*;\nimport Connectable::*;\nimport ConnectableWithTrace::*;\nimport Vector::*;\nimport HostInterface::*;\nimport PS7LIB::*;\nimport Portal::*;\nimport AxiMasterSlave::*;\nimport AxiDma::*;\nimport AxiBits::*;\nimport AxiGather::*;\nimport Platform::*;\n\n`include \"ConnectalProjectConfig.bsv\"\n\n`ifdef USE_ACP\ntypedef 1 NumAcp;\n`else\ntypedef 0 NumAcp;\n`endif\n\ninstance ConnectableWithTrace#(PS7, Platform, traceType)\n   provisos (ConnectableWithTrace::ConnectableWithTrace#(AxiMasterSlave::Axi3Master#(32,64,6),AxiMasterSlave::Axi3Slave#(32, 64, 6),traceType),\n             ConnectableWithTrace::ConnectableWithTrace#(AxiMasterSlave::Axi3Master#(32,32,12),AxiMasterSlave::Axi3Slave#(32,32,12),traceType));\n   module mkConnectionWithTrace#(PS7 ps7, Platform top, traceType readout)(Empty)\n      provisos (ConnectableWithTrace#(Axi3Master#(32,64,6), Axi3Slave#(32,64,6),traceType));\n\n      Axi3Slave#(32,32,12) ctrl <- mkAxiDmaSlave(top.slave);\n      mkConnectionWithTrace(ps7.m_axi_gp[0].client, ctrl, readout);\n\n`ifdef USE_ACP\n      begin\n\t Axi3Master#(32,64,3) acp_m_axi <- mkAxiDmaMaster(top.masters[0]);\n\t mkConnection(acp_m_axi, ps7.s_axi_acp[0].server);\n      end\n      rule acp_aruser;\n\t ps7.s_axi_acp[0].extra.aruser(5'h1f);\n      endrule\n      rule acp_awuser;\n\t ps7.s_axi_acp[0].extra.awuser(5'h1f);\n      endrule\n`endif\n      module mkAxiMasterConnection#(Integer i)(Axi3Master#(32,64,6));\n\t let m_axi <- mkAxiDmaMaster(top.masters[i+valueOf(NumAcp)]);\n\t mkConnection(m_axi, ps7.s_axi_hp[i].server);\n\t return m_axi;\n      endmodule\n      Vector#(TSub#(NumberOfMasters,NumAcp), Axi3Master#(32,64,6)) m_axis <- genWithM(mkAxiMasterConnection);\n   endmodule\nendinstance\n"
  },
  {
    "path": "bsv/PS8LIB.bsv",
    "content": "\n// Copyright (c) 2013 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n`include \"ConnectalProjectConfig.bsv\"\nimport ConnectalConfig::*;\nimport BuildVector::*;\nimport Clocks::*;\nimport DefaultValue::*;\nimport FIFOF::*;\nimport GetPut::*;\nimport Connectable::*;\nimport ConnectableWithTrace::*;\nimport Bscan::*;\nimport Vector::*;\nimport XilinxCells::*;\nimport ConnectalXilinxCells::*;\nimport ConnectalClocks::*;\nimport AxiMasterSlave::*;\nimport Axi4MasterSlave::*;\nimport AxiDma::*;\nimport AxiBits::*;\nimport ConnectalMemTypes::*;\nimport Platform::*;\nimport ZYNQ_ULTRA::*;\nimport Probe::*;\n\n(* always_ready, always_enabled *)\ninterface Bidir#(numeric type data_width);\n    method Action             i(Bit#(data_width) v);\n    method Bit#(data_width)   o();\n    method Bit#(data_width)   t();\nendinterface\n\ninterface ZynqPins;\nendinterface\n\ninterface PS8LIB;\n    (* prefix=\"\" *)\n    interface Vector#(1, Ps8Maxigp)     m_axi_gp;\n    interface Vector#(7, Ps8Saxigp)     s_axi_gp;\n    interface Vector#(1, Ps8Saxiacp)     s_axi_acp;\n    method Action                             interrupt(Bit#(1) v);\n    interface Vector#(4, Clock) plclk;\n    interface Clock portalClock;\n    interface Reset portalReset;\n    interface Clock derivedClock;\n    interface Reset derivedReset;\nendinterface\n\nmodule mkPS8LIB#(Clock axiClock)(PS8LIB);\n   // B2C converts a bit to a clock, enabling us to break the apparent cycle\n   Vector#(4, B2C) b2c <- replicateM(mkB2C());\n\n   // need the bufg here to reduce clock skew\n   module mkBufferedClock#(Integer i)(Clock); let c <- mkClockBUFG(clocked_by b2c[i].c); return c; endmodule\n   module mkBufferedReset#(Integer i)(Reset); let r <- mkResetBUFG(clocked_by b2c[i].c, reset_by b2c[i].r); return r; endmodule\n   Vector#(4, Clock) fclk <- genWithM(mkBufferedClock);\n   Vector#(4, Reset) freset <- genWithM(mkBufferedReset);\n\n`ifndef TOP_SOURCES_PORTAL_CLOCK\n   Clock single_clock = fclk[0];\n`ifdef ZYNQ_NO_RESET\n   freset[0]          = noReset;\n`endif\n   let single_reset   = freset[0];\n`else\n   //Clock axiClockBuf <- mkClockBUFG(clocked_by axiClock);\n   Clock axiClockBuf = axiClock;\n   Clock single_clock = axiClockBuf;\n   Reset axiResetUnbuffered <- mkSyncReset(10, freset[0], single_clock);\n   Reset axiReset <- mkResetBUFG(clocked_by axiClockBuf, reset_by axiResetUnbuffered);\n   let single_reset   = axiReset;\n`endif\n\n   ClockGenerator7Params clockParams = defaultValue;\n   // input clock 200MHz for speed grade -2, 100MHz for speed grade -1\n   // fpll needs to be in the range 600MHz - 1200MHz for either input clock\n   //\n   // fclkin = 1e9 / mainClockPeriod\n   // fpll = 1e9 = mult_f * 1e9 / mainClockPeriod\n   // mult_f = mainClockPeriod\n   //\n   // fclkout0 = 1e9 / divide_f = 1e9 / derivedClockPeriod\n   // divide_f = derivedClockPeriod\n   //\n   clockParams.clkfbout_mult_f       = mainClockPeriod;\n   clockParams.clkfbout_phase     = 0.0;\n   clockParams.clkfbout_phase     = 0.0;\n   clockParams.clkin1_period      = mainClockPeriod;\n   clockParams.clkout0_divide_f   = derivedClockPeriod;\n   clockParams.clkout0_duty_cycle = 0.5;\n   clockParams.clkout0_phase      = 0.0000;\n   clockParams.clkout0_buffer     = True;\n   clockParams.clkin_buffer = False;\n   ClockGenerator7   clockGen <- mkClockGenerator7(clockParams, clocked_by single_clock, reset_by single_reset);\n   let derived_clock = clockGen.clkout0;\n   let derived_reset_unbuffered <- mkSyncReset(10, single_reset, derived_clock);\n   let derived_reset <- mkResetBUFG(clocked_by derived_clock, reset_by derived_reset_unbuffered);\n\n   // FIXME: enable multiple clock domains\n   ZYNQ_ULTRA::PS8 psu <- ZYNQ_ULTRA::mkPS8(single_clock, single_clock, single_clock, single_clock, single_clock, single_clock, single_clock, single_clock, single_clock, single_clock, single_clock);\n\n   // this rule connects the pl_clk wires to the clock net via B2C\n   for (Integer i = 0; i < 1; i = i + 1) begin\n      ReadOnly#(Bit#(1)) fclkb;\n      ReadOnly#(Bit#(1)) fclkresetnb;\n      fclkb       <- mkNullCrossingWire(b2c[i].c, psu.pl.clk0);\n      fclkresetnb <- mkNullCrossingWire(b2c[i].c, psu.pl.resetn0);\n`ifndef BSV_POSITIVE_RESET\n      let resetValue = 0;\n`else\n      let resetValue = 1;\n`endif\n      rule b2c_rule1;\n\t b2c[i].inputclock(fclkb[i]);\n\t b2c[i].inputreset(fclkresetnb[i] == 0 ? resetValue : ~resetValue);\n      endrule\n   end\n\n    interface m_axi_gp = vec(psu.maxigp0);\n    interface s_axi_gp = vec(psu.saxigp0, psu.saxigp1, psu.saxigp2, psu.saxigp3, psu.saxigp4, psu.saxigp5, psu.saxigp6);\n    interface s_axi_acp = vec(psu.saxiacp);\n    interface plclk = fclk;\n`ifndef TOP_SOURCES_PORTAL_CLOCK\n    interface portalClock = fclk[0];\n    interface portalReset = freset[0];\n`else\n    interface portalClock = axiClockBuf;\n    interface portalReset = axiReset;\n`endif\n    interface derivedClock = derived_clock;\n    interface derivedReset = derived_reset;\n    method Action interrupt(Bit#(1) v);\n       psu.pl.ps_irq0(v);\n    endmethod\nendmodule\n\ninterface Ps8MaxigpExtra;\n    method Bit#(16) aruser();\n    method Bit#(16) awuser();\nendinterface\n\ninterface Ps8SaxigpExtra;\n    method Action aruser(Bit#(1) v);\n    method Action awuser(Bit#(1) v);\nendinterface\ninterface Ps8SaxiacpExtra;\n    method Action aruser(Bit#(2) v);\n    method Action awuser(Bit#(2) v);\nendinterface\n\ninstance ToAxi4MasterBits#(Axi4MasterBits#(40,128,16,Ps8MaxigpExtra), Ps8Maxigp);\nfunction Axi4MasterBits#(40,128,16,Ps8MaxigpExtra) toAxi4MasterBits(Ps8Maxigp m);\n   return (interface Axi4MasterBits#(40,128,16,Ps8MaxigpExtra);\n      method araddr = m.araddr;\n\t   method arburst = m.arburst;\n\t   method arcache = m.arcache;\n           method aresetn = 1;\n\t   method arid = m.arid;\n\t   method arlen = m.arlen;\n\t   method arlock = extend(m.arlock);\n\t   method arprot = m.arprot;\n\t   method arqos = m.arqos;\n\t   method arready = m.arready;\n\t   method arsize = m.arsize;\n\t   method arvalid = m.arvalid;\n\t   method awaddr = m.awaddr;\n\t   method awburst = m.awburst;\n\t   method awcache = m.awcache;\n\t   method awid = m.awid;\n\t   method awlen = m.awlen;\n\t   method awlock = extend(m.awlock);\n\t   method awprot = m.awprot;\n\t   method awqos = m.awqos;\n\t   method awready = m.awready;\n\t   method awsize = m.awsize;\n\t   method awvalid = m.awvalid;\n\t   method bid = m.bid;\n\t   method bready = m.bready;\n\t   method bresp = m.bresp;\n\t   method bvalid = m.bvalid;\n\t   method rdata = m.rdata;\n\t   method rid = m.rid;\n\t   method rlast = m.rlast;\n\t   method rready = m.rready;\n\t   method rresp = m.rresp;\n\t   method rvalid = m.rvalid;\n\t   method wdata = m.wdata;\n\t   //method wid = m.wid;\n\t   method wlast = m.wlast;\n\t   method wready = m.wready;\n\t   method wstrb = m.wstrb;\n\t   method wvalid = m.wvalid;\n\t interface extra = ?;   \n\t endinterface);\n   endfunction: toAxi4MasterBits\nendinstance\n\ninstance ToAxi4SlaveBits#(Axi4SlaveBits#(49,128,6,Ps8SaxigpExtra), Ps8Saxigp);\n   function Axi4SlaveBits#(49,128,6,Ps8SaxigpExtra) toAxi4SlaveBits(Ps8Saxigp s);\n      return (interface Axi4SlaveBits#(49,128,6,Ps8SaxigpExtra);\n\t method araddr = s.araddr;\n\t method arburst = s.arburst;\n\t method arcache = s.arcache;\n\t //method aresetn = 1; //no aresetn port in zcu\n\t method arid = s.arid;\n\t method arlen = s.arlen;\n\t method arlock = compose(s.arlock, truncate);\n\t method arprot = s.arprot;\n\t method arqos = s.arqos;\n\t method arready = s.arready;\n\t method arsize = s.arsize;\n\t method arvalid = s.arvalid;\n\t \n\t method awaddr = s.awaddr;\n\t method awburst = s.awburst;\n\t method awcache = s.awcache;\n\t method awid = s.awid;\n\t method awlen = s.awlen;\n\t method awlock = compose(s.awlock, truncate);\n\t method awprot = s.awprot;\n\t method awqos = s.awqos;\n\t method awready = s.awready;\n\t method awsize = s.awsize;\n\t method awvalid = s.awvalid;\n\n\t method bid = s.bid;\n\t method bready = s.bready;\n\t method bresp = s.bresp;\n\t method bvalid = s.bvalid;\n\t method rdata = s.rdata;\n\t method rid = s.rid;\n\t method rlast = s.rlast;\n\t method rready = s.rready;\n\t method rresp = s.rresp;\n\t method rvalid = s.rvalid;\n\t method wdata = s.wdata;\n\t //method wid = s.wid; //wid not present in Axi4\n\t method wlast = s.wlast;\n\t method wready = s.wready;\n\t method wvalid = s.wvalid;\n\t method wstrb = s.wstrb;\n\t interface Ps8SaxigpExtra extra;\n\t\t method aruser = s.aruser;\n\t\t method awuser = s.awuser;\n\t endinterface\n\t endinterface);\n   endfunction\nendinstance\n\ninstance ToAxi4SlaveBits#(Axi4SlaveBits#(40,128,5,Ps8SaxiacpExtra), Ps8Saxiacp);\n   function Axi4SlaveBits#(40,128,5,Ps8SaxiacpExtra) toAxi4SlaveBits(Ps8Saxiacp s);\n      return (interface Axi4SlaveBits#(40,128,5,Ps8SaxiacpExtra);\n\t method araddr = s.araddr;\n\t method arburst = s.arburst;\n\t method arcache = s.arcache;\n\t //method aresetn = 1; //no aresetn port in zcu\n\t method arid = s.arid;\n\t method arlen = s.arlen;\n\t method arlock = compose(s.arlock, truncate);\n\t method arprot = s.arprot;\n\t method arqos = s.arqos;\n\t method arready = s.arready;\n\t method arsize = s.arsize;\n\t method arvalid = s.arvalid;\n\t \n\t method awaddr = s.awaddr;\n\t method awburst = s.awburst;\n\t method awcache = s.awcache;\n\t method awid = s.awid;\n\t method awlen = s.awlen;\n\t method awlock = compose(s.awlock, truncate);\n\t method awprot = s.awprot;\n\t method awqos = s.awqos;\n\t method awready = s.awready;\n\t method awsize = s.awsize;\n\t method awvalid = s.awvalid;\n\n\t method bid = s.bid;\n\t method bready = s.bready;\n\t method bresp = s.bresp;\n\t method bvalid = s.bvalid;\n\t method rdata = s.rdata;\n\t method rid = s.rid;\n\t method rlast = s.rlast;\n\t method rready = s.rready;\n\t method rresp = s.rresp;\n\t method rvalid = s.rvalid;\n\t method wdata = s.wdata;\n\t //method wid = s.wid; //wid not present in Axi4\n\t method wlast = s.wlast;\n\t method wready = s.wready;\n\t method wvalid = s.wvalid;\n\t method wstrb = s.wstrb;\n\t interface Ps8SaxiacpExtra extra;\n\t\t method aruser = s.aruser;\n\t\t method awuser = s.awuser;\n\t endinterface\n\t endinterface);\n   endfunction\nendinstance\n\ninstance PhysMemSlaveExtra#(Empty);\n   function Action extra_r(Empty ex);\n      action endaction\n   endfunction\n   function Action extra_w(Empty ex);\n      action endaction\n   endfunction\nendinstance\n\ninstance PhysMemSlaveExtra#(Ps8SaxigpExtra);\n   function Action extra_r(Ps8SaxigpExtra ex);\n      action\n\t ex.aruser(1'b0);\n      endaction\n   endfunction\n   function Action extra_w(Ps8SaxigpExtra ex);\n      action\n\t ex.awuser(1'b0);\n      endaction\n   endfunction\nendinstance\n\ninstance PhysMemSlaveExtra#(Ps8SaxiacpExtra);\n   function Action extra_r(Ps8SaxiacpExtra ex);\n      action\n\t // inner shareable\n\t ex.aruser(2'b01);\n      endaction\n   endfunction\n   function Action extra_w(Ps8SaxiacpExtra ex);\n      action\n\t // inner shareable\n\t ex.awuser(2'b01);\n      endaction\n   endfunction\nendinstance\n\ninstance ConnectableWithTrace#(PS8LIB, Platform, traceType);\n   module mkConnectionWithTrace#(PS8LIB psu, Platform top, traceType readout)(Empty);\n      Axi4MasterBits#(40,128,16,Ps8MaxigpExtra) master = toAxi4MasterBits(psu.m_axi_gp[0]);\n      PhysMemMaster#(32,32) physMemMaster <- mkPhysMemMaster(master);\n      mkConnection(physMemMaster, top.slave);\n\n`ifdef USE_ACP\n      Axi4SlaveBits#(40,128,5,Ps8SaxiacpExtra) slave = toAxi4SlaveBits(psu.s_axi_acp[0]);\n      PhysMemSlave#(40,DataBusWidth) physMemSlaveAcp <- mkPhysMemSlave(slave);\n`endif // USE_ACP\n      Vector#(7, Axi4SlaveBits#(49,128,6,Ps8SaxigpExtra)) slaves = map(toAxi4SlaveBits, psu.s_axi_gp);\n      Vector#(7, PhysMemSlave#(40,DataBusWidth)) physMemSlaves <- mapM(mkPhysMemSlave, slaves);\n`ifdef USE_ACP\n      physMemSlaves[0] = physMemSlaveAcp;\n`endif      \n      // makes NumberOfMasters connections\n      zipWithM(mkConnection, top.masters, take(physMemSlaves));\n   endmodule\nendinstance\n"
  },
  {
    "path": "bsv/ParallellaTop.bsv",
    "content": "// Copyright (c) 2014 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\n// Initially, this is a copy of ZynqTop\n// The plan for changes:\n// Use ps7.s_axi_hp[3] to connect to the Parallella verilog dma master\n//   restrict the Connectal stuff to 3 masters, so that [3] will be free\n// Use psy.m_axi_gp[1] to connect to the Parallella verilog axi slave\n//   verify this leave the addressing unchanged, or make matching changes\n//   the address ranges for the two _gp ports are explained in the\n//   zynq TRM.  You also have to set these to match in the device tree\n//   The device drivers <should> use the values in the DTB, but confirm this\n//   Since both parallella and connectal use gp[0] to start, one has to change\n//   but if this is done right the software shouldn't have to change\n// Establish pin connections for the ELink to the epiphany chip\n// Establish pin connections for the GPIO\n// establish I2C 0 connections\n\n// make clock connections (see parallella_z7_top.v\n// tie off HDMI signals\nimport Clocks :: *;\nimport Vector            :: *;\nimport Connectable       :: *;\nimport ConnectableWithTrace::*;\nimport Portal            :: *;\nimport ConnectalMemTypes          :: *;\nimport AxiMasterSlave    :: *;\nimport XilinxCells       :: *;\nimport ConnectalXilinxCells   :: *;\nimport PS7LIB::*;\nimport PS7Trace::*;\nimport PPS7LIB::*;\nimport CtrlMux::*;\nimport AxiDma            :: *;\nimport Top               :: *;\nimport Bscan             :: *;\nimport HostInterface::*;\n`include \"ConnectalProjectConfig.bsv\"\nimport `PinTypeInclude::*;\n\ninterface I2C_Pins;\n   interface Inout#(Bit#(1)) scl;\n   interface Inout#(Bit#(1)) sda;\nendinterface\n\n(* always_ready, always_enabled *)\ninterface ZynqTop;\n   (* prefix=\"\" *)\n   interface ZynqPins zynq;\n`ifdef USE_I2C0\n   (* prefix=\"I2C0\" *)\n   interface I2C_Pins         i2c0;\n`endif\n`ifdef USE_I2C1\n   (* prefix=\"I2C1\" *)\n   interface I2C_Pins         i2c1;\n`endif\n   (* prefix=\"\" *)\n   interface `PinType          pins;\n   interface Vector#(4, Clock) deleteme_unused_clock;\n   interface Vector#(4, Reset) deleteme_unused_reset;\nendinterface\n\nmodule mkZynqTop(ZynqTop);\n   PS7 ps7 <- mkPS7();\n   Clock mainclock = ps7.fclkclk[0];\n   Reset mainreset = ps7.fclkreset[0];\n\n`ifdef USE_I2C0\n   let tscl0 <- mkIOBUF(~ps7.i2c[0].scltn, ps7.i2c[0].sclo, clocked_by mainclock, reset_by mainreset);\n   let tsda0 <- mkIOBUF(~ps7.i2c[0].sdatn, ps7.i2c[0].sdao, clocked_by mainclock, reset_by mainreset);\n   rule sdai0;\n      ps7.i2c[0].sdai(tsda0.o);\n      ps7.i2c[0].scli(tscl0.o);\n   endrule\n`endif\n\n`ifdef USE_I2C1\n   let tscl1 <- mkIOBUF(~ps7.i2c[1].scltn, ps7.i2c[1].sclo, clocked_by mainclock, reset_by mainreset);\n   let tsda1 <- mkIOBUF(~ps7.i2c[1].sdatn, ps7.i2c[1].sdao, clocked_by mainclock, reset_by mainreset);\n   rule sdai1;\n      ps7.i2c[1].sdai(tsda1.o);\n      ps7.i2c[1].scli(tscl1.o);\n   endrule\n`endif\n\n   BscanTop bscan <- mkBscanTop(3, clocked_by mainclock, reset_by mainreset); // Use USER3  (JTAG IDCODE address 0x22)\n   BscanLocal lbscan <- mkBscanLocal(bscan, clocked_by bscan.tck, reset_by bscan.rst);\n`ifdef IMPORT_HOSTIF\n   let top <- mkConnectalTop(\n      (interface HostInterface;\n          interface ps7 = ps7;\n\t  interface portalClock = mainclock;\n\t  interface portalReset = mainreset;\n\t  interface derivedClock = ps7.derivedClock;\n\t  interface derivedReset = ps7.derivedReset;\n          interface bscan = lbscan.loc[0];\n      endinterface), clocked_by mainclock, reset_by mainreset);\n`else\n   let top <- mkConnectalTop(clocked_by mainclock, reset_by mainreset);\n`endif\n   mkConnectionWithTrace(ps7, top, lbscan.loc[1], clocked_by mainclock, reset_by mainreset);\n\n   let intr_mux <- mkInterruptMux(top.interrupt);\n   rule send_int_rule;\n      ps7.interrupt(pack(intr_mux));\n   endrule\n\n   module bufferClock#(Integer i)(Clock); let bc <- mkClockBUFG(clocked_by ps7.fclkclk[i]); return bc; endmodule\n   module bufferReset#(Integer i)(Reset); let rc <- mkSyncReset(5, ps7.fclkreset[i], ps7.fclkclk[0]); return rc; endmodule\n   Vector#(4, Clock) unused_clock <- genWithM(bufferClock);\n   Vector#(4, Reset) unused_reset <- genWithM(bufferReset);\n\n   interface zynq = ps7.pins;\n`ifdef USE_I2C0\n   interface I2C_Pins i2c0;\n      interface Inout scl = tscl0.io;\n      interface Inout sda = tsda0.io;\n   endinterface\n`endif\n`ifdef USE_I2C1\n   interface I2C_Pins i2c1;\n      interface Inout scl = tscl1.io;\n      interface Inout sda = tsda1.io;\n   endinterface\n`endif\n   interface pins = top.pins;\n   interface deleteme_unused_clock = unused_clock;\n   interface deleteme_unused_reset = unused_reset;\nendmodule\n"
  },
  {
    "path": "bsv/Pcie1EndpointX7.bsv",
    "content": "////////////////////////////////////////////////////////////////////////////////\n// Copyright (c) 2012  Bluespec, Inc.  ALL RIGHTS RESERVED.\n////////////////////////////////////////////////////////////////////////////////\n//  Filename      : ConnectalXilinx7PCIE.bsv\n//  Description   :\n////////////////////////////////////////////////////////////////////////////////\n\nimport ConnectalConfig   ::*;\nimport Clocks            ::*;\nimport Vector            ::*;\nimport Connectable       ::*;\nimport GetPut            ::*;\nimport Reserved          ::*;\nimport TieOff            ::*;\nimport DefaultValue      ::*;\nimport DReg              ::*;\nimport Gearbox           ::*;\nimport FIFO              ::*;\nimport FIFOF             ::*;\nimport SpecialFIFOs      ::*;\nimport ClientServer      ::*;\nimport Real              ::*;\n\nimport ConnectalClocks   ::*;\nimport ConnectalXilinxCells   ::*;\nimport XilinxCells       ::*;\nimport PCIE              ::*;\nimport PCIEWRAPPER       ::*;\nimport Bufgctrl           ::*;\nimport PcieGearbox       :: *;\nimport PcieStateChanges  ::*;\nimport Pipe              :: *;\n\n`include \"ConnectalProjectConfig.bsv\"\n\n(* always_ready, always_enabled *)\ninterface PCIE_X7#(numeric type lanes);\n   interface PciewrapPci_exp#(lanes)   pcie;\n   interface PciewrapUser#(lanes)      user;\n   interface PciewrapFc#(lanes)        fc;\n   interface PciewrapTx#(lanes)        tx;\n   interface PciewrapS_axis_tx#(lanes) s_axis_tx;\n   interface PciewrapM_axis_rx#(lanes) m_axis_rx;\n   interface PciewrapRx#(lanes)        rx;\n   interface PciewrapCfg#(lanes)       cfg;\n   method    Action                    cfg_dsn(Bit#(64) i);\n   interface Clock                     pipe_txoutclk_out;\n   method    Action                    pipe_mmcm_lock_in(Bit#(1) v);\n   method    Bit#(lanes)               pipe_pclk_sel_out();\nendinterface\n\nimport \"BVI\" pcie_7x_0 =\nmodule vMkXilinx7PCIExpress#(PCIEParams params, Clock clk_125mhz, Clock pipe_userclk1_in, Clock pclk_in)(PCIE_X7#(lanes))\n   provisos( Add#(1, z, lanes));\n   let sys_rst_n <- exposeCurrentReset;\n\n   default_clock clk(sys_clk); // 100 MHz refclk\n   default_reset rstn(sys_rst_n) = sys_rst_n;\n   input_clock clk_125mhz(pipe_dclk_in) = clk_125mhz;\n   input_clock clk_oobclk_in(pipe_oobclk_in) = clk_125mhz;\n   input_clock pipe_userclk1_in(pipe_userclk1_in) = pipe_userclk1_in;\n   input_clock pipe_userclk2_in(pipe_userclk2_in) = pipe_userclk1_in;\n   input_clock pclk_in(pipe_pclk_in) = pclk_in;\n   input_clock pclk_usrin(pipe_rxusrclk_in) = pclk_in;\n   method pipe_mmcm_lock_in(pipe_mmcm_lock_in) enable((*inhigh*)en_pipe_mmcm_lock_in);\n   method pipe_pclk_sel_out pipe_pclk_sel_out   clocked_by(pclk_in);\n\n   interface PciewrapPci_exp pcie;\n      method                  rxp(pci_exp_rxp) enable((*inhigh*)en0)    reset_by(no_reset);\n      method                  rxn(pci_exp_rxn) enable((*inhigh*)en1)    reset_by(no_reset);\n      method pci_exp_txp      txp    reset_by(no_reset);\n      method pci_exp_txn      txn    reset_by(no_reset);\n   endinterface\n\n   interface PciewrapUser     user;\n      output_clock            clk_out(user_clk_out);\n      output_reset            reset_out(user_reset_out);\n      method user_lnk_up      lnk_up   clocked_by(no_clock) reset_by(no_reset); /* semi-static */\n      method user_app_rdy     app_rdy   clocked_by(no_clock) reset_by(no_reset);\n   endinterface\n    interface PciewrapFc     fc;\n      method fc_ph            ph   clocked_by(user_clk_out)    reset_by(no_reset);\n      method fc_pd            pd   clocked_by(user_clk_out)    reset_by(no_reset);\n      method fc_nph           nph   clocked_by(user_clk_out)    reset_by(no_reset);\n      method fc_npd           npd   clocked_by(user_clk_out)    reset_by(no_reset);\n      method fc_cplh          cplh   clocked_by(user_clk_out)    reset_by(no_reset);\n      method fc_cpld          cpld   clocked_by(user_clk_out)    reset_by(no_reset);\n      method                  sel(fc_sel)    enable((*inhigh*)en01)   clocked_by(user_clk_out)    reset_by(no_reset);\n   endinterface\n\n   interface PciewrapTx     tx;\n      method tx_buf_av        buf_av   clocked_by(user_clk_out)    reset_by(no_reset);\n      method tx_err_drop      err_drop   clocked_by(user_clk_out)    reset_by(no_reset);\n      method tx_cfg_req       cfg_req   clocked_by(user_clk_out)    reset_by(no_reset);\n      method                  cfg_gnt(tx_cfg_gnt)    enable((*inhigh*)en07)   clocked_by(user_clk_out)    reset_by(no_reset);\n   endinterface\n\n    interface PciewrapS_axis_tx     s_axis_tx;\n      method                  tlast(s_axis_tx_tlast)    enable((*inhigh*)en02)   clocked_by(user_clk_out)    reset_by(no_reset);\n      method                  tdata(s_axis_tx_tdata)    enable((*inhigh*)en03)   clocked_by(user_clk_out)    reset_by(no_reset);\n      method                  tkeep(s_axis_tx_tkeep)    enable((*inhigh*)en04)   clocked_by(user_clk_out)    reset_by(no_reset);\n      method                  tvalid(s_axis_tx_tvalid)    enable((*inhigh*)en05)   clocked_by(user_clk_out)    reset_by(no_reset);\n      method                  tuser(s_axis_tx_tuser)    enable((*inhigh*)en06)   clocked_by(user_clk_out)    reset_by(no_reset);\n      method s_axis_tx_tready tready   clocked_by(user_clk_out)    reset_by(no_reset);\n   endinterface\n\n    interface PciewrapM_axis_rx     m_axis_rx;\n      method m_axis_rx_tlast  tlast   clocked_by(user_clk_out)    reset_by(no_reset);\n      method m_axis_rx_tdata  tdata   clocked_by(user_clk_out)    reset_by(no_reset);\n      method m_axis_rx_tkeep  tkeep   clocked_by(user_clk_out)    reset_by(no_reset);\n      method m_axis_rx_tuser  tuser   clocked_by(user_clk_out)    reset_by(no_reset);\n      method m_axis_rx_tvalid tvalid   clocked_by(user_clk_out)    reset_by(no_reset);\n      method                  tready(m_axis_rx_tready)    enable((*inhigh*)en08)   clocked_by(user_clk_out)    reset_by(no_reset);\n   endinterface\n   interface PciewrapRx     rx;\n      method                  np_ok(rx_np_ok)    enable((*inhigh*)en09)   clocked_by(user_clk_out)    reset_by(no_reset);\n      method                  np_req(rx_np_req)    enable((*inhigh*)en10)   clocked_by(user_clk_out)    reset_by(no_reset);\n   endinterface\n\n   method                    cfg_dsn(cfg_dsn)    enable((*inhigh*)en25)   clocked_by(user_clk_out);\n\n   interface PciewrapCfg     cfg;\n      method cfg_bus_number      bus_number   clocked_by(no_clock) reset_by(no_reset);\n      method cfg_device_number   device_number   clocked_by(no_clock) reset_by(no_reset);\n      method cfg_function_number function_number   clocked_by(no_clock) reset_by(no_reset);\n      method cfg_lcommand        lcommand   clocked_by(user_clk_out) reset_by(no_reset);\n      method                     interrupt(cfg_interrupt)    enable((*inhigh*)en32)   clocked_by(user_clk_out) reset_by(no_reset);\n\n      method cfg_bridge_serr_en bridge_serr_en();\n      method cfg_command command();\n      method cfg_dcommand dcommand();\n      method cfg_dcommand2 dcommand2();\n      method cfg_lstatus lstatus();\n      method cfg_pcie_link_state pcie_link_state();\n      method pciecap_interrupt_msgnum(cfg_pciecap_interrupt_msgnum) enable((*inhigh*) EN_cfg_pciecap_interrupt_msgnum);\n      method cfg_received_func_lvl_rst received_func_lvl_rst();\n      method cfg_slot_control_electromech_il_ctl_pulse slot_control_electromech_il_ctl_pulse();\n      method cfg_status status();\n      method cfg_to_turnoff to_turnoff();\n      method trn_pending(cfg_trn_pending) enable((*inhigh*) EN_cfg_trn_pending);\n      method turnoff_ok(cfg_turnoff_ok) enable((*inhigh*) EN_cfg_turnoff_ok);\n      method cfg_vc_tcvc_map vc_tcvc_map();\n   endinterface\n\n   output_clock pipe_txoutclk_out(pipe_txoutclk_out);\n\n   schedule (user_lnk_up, user_app_rdy, fc_ph, fc_pd, fc_nph, fc_npd, fc_cplh, fc_cpld, fc_sel, s_axis_tx_tlast,\n\t     s_axis_tx_tdata, s_axis_tx_tkeep, s_axis_tx_tvalid, s_axis_tx_tready, s_axis_tx_tuser, tx_buf_av, tx_err_drop,\n\t     tx_cfg_req, tx_cfg_gnt, m_axis_rx_tlast, m_axis_rx_tdata, m_axis_rx_tkeep, m_axis_rx_tuser, m_axis_rx_tvalid,\n\t     m_axis_rx_tready, rx_np_ok, rx_np_req,\n\t     cfg_bus_number, cfg_device_number, cfg_function_number, cfg_lcommand,\ncfg_command, cfg_dcommand, cfg_dcommand2, cfg_lstatus, cfg_pcie_link_state, cfg_received_func_lvl_rst, cfg_status, cfg_to_turnoff, cfg_vc_tcvc_map,\ncfg_bridge_serr_en, cfg_slot_control_electromech_il_ctl_pulse,\ncfg_pciecap_interrupt_msgnum, cfg_trn_pending, cfg_turnoff_ok,\ncfg_interrupt, cfg_dsn,\n\t     pcie_txp, pcie_txn, pcie_rxp, pcie_rxn, pipe_mmcm_lock_in, pipe_pclk_sel_out\n\t     ) CF\n            (user_lnk_up, user_app_rdy, fc_ph, fc_pd, fc_nph, fc_npd, fc_cplh, fc_cpld, fc_sel, s_axis_tx_tlast,\n\t     s_axis_tx_tdata, s_axis_tx_tkeep, s_axis_tx_tvalid, s_axis_tx_tready, s_axis_tx_tuser, tx_buf_av, tx_err_drop,\n\t     tx_cfg_req, tx_cfg_gnt, m_axis_rx_tlast, m_axis_rx_tdata, m_axis_rx_tkeep, m_axis_rx_tuser, m_axis_rx_tvalid,\n\t     m_axis_rx_tready, rx_np_ok, rx_np_req,\n\t     cfg_bus_number, cfg_device_number, cfg_function_number, cfg_lcommand,\ncfg_command, cfg_dcommand, cfg_dcommand2, cfg_lstatus, cfg_pcie_link_state, cfg_received_func_lvl_rst, cfg_status, cfg_to_turnoff, cfg_vc_tcvc_map,\ncfg_bridge_serr_en, cfg_slot_control_electromech_il_ctl_pulse,\ncfg_pciecap_interrupt_msgnum, cfg_trn_pending, cfg_turnoff_ok,\ncfg_interrupt, cfg_dsn,\n\t     pcie_txp, pcie_txn, pcie_rxp, pcie_rxn, pipe_mmcm_lock_in, pipe_pclk_sel_out\n             );\n\nendmodule: vMkXilinx7PCIExpress\n\n////////////////////////////////////////////////////////////////////////////////\n/// Interfaces\n////////////////////////////////////////////////////////////////////////////////\n\ninterface PcieEndpointX7#(numeric type lanes);\n   interface PciewrapPci_exp#(lanes)   pcie;\n   interface PciewrapUser#(lanes)      user;\n   interface PciewrapCfg#(lanes)       cfg;\n   interface Server#(TLPData#(16), TLPData#(16)) tlp;\n   interface PipeOut#(Bit#(64)) regChanges;\n   interface Clock epPcieClock;\n   interface Reset epPcieReset;\n   interface Clock epPortalClock;\n   interface Reset epPortalReset;\n   interface Clock epDerivedClock;\n   interface Reset epDerivedReset;\nendinterface\n\ntypedef struct {\n   Bit#(22)      user;\n   Bit#(1)       last;\n   Bit#(8)       keep;\n   Bit#(64)      data;\n} AxiRx deriving (Bits, Eq);\n\ntypedef struct {\n   Bit#(1)       last;\n   Bit#(8)       keep;\n   Bit#(64)      data;\n} AxiTx deriving (Bits, Eq);\n\n(* synthesize *)\nmodule mkPcieEndpointX7(PcieEndpointX7#(PcieLanes));\n\n   PCIEParams params = defaultValue;\n\n   ////////////////////////////////////////////////////////////////////////////////\n   /// Design Elements\n   ////////////////////////////////////////////////////////////////////////////////\n   B2C1 b2c <- mkB2C1();\n   ClockGenerator7AdvParams   clockParams = defaultValue;\n   clockParams.bandwidth          = \"OPTIMIZED\";\n   clockParams.compensation       = \"INTERNAL\";\n   clockParams.clkfbout_mult_f    = 10.000;\n   clockParams.clkfbout_phase     = 0.0;\n   clockParams.clkin1_period      = 10.000;\n   clockParams.clkout0_divide_f   = 8.000;\n   clockParams.clkout0_duty_cycle = 0.5;\n   clockParams.clkout0_phase      = 0.0000;\n   clockParams.clkout1_divide     = 4;\n   clockParams.clkout1_duty_cycle = 0.5;\n   clockParams.clkout1_phase      = 0.0000;\n   clockParams.clkout2_divide     = 4;\n   clockParams.clkout2_duty_cycle = 0.5;\n   clockParams.clkout2_phase      = 0.0000;\n   clockParams.divclk_divide      = 1;\n   clockParams.ref_jitter1        = 0.010;\n   clockParams.clkin_buffer = False;\n   XClockGenerator7   clockGen <- mkClockGenerator7Adv(clockParams, clocked_by b2c.c);\n   C2B c2b_fb <- mkC2B(clockGen.clkfbout, clocked_by clockGen.clkfbout);\n   rule txoutrule5;\n      clockGen.clkfbin(c2b_fb.o());\n   endrule\n\n   Reset defaultReset <- exposeCurrentReset();\n   Bufgctrl bbufc <- mkBufgctrl(clockGen.clkout0, defaultReset, clockGen.clkout1, defaultReset);\n   Reset rsto <- mkSyncReset(5, defaultReset, bbufc.o);\n   Reg#(Bit#(1)) pclk_sel <- mkReg(0, clocked_by bbufc.o, reset_by rsto);\n   Reg#(Bit#(PcieLanes)) pclk_sel_reg1 <- mkReg(0, clocked_by bbufc.o, reset_by rsto);\n   Reg#(Bit#(PcieLanes)) pclk_sel_reg2 <- mkReg(0, clocked_by bbufc.o, reset_by rsto);\n\n   rule bufcruleinit;\n      bbufc.ce0(1);\n      bbufc.ce1(1);\n      bbufc.ignore0(0);\n      bbufc.ignore1(0);\n   endrule\n   rule bufcrule;\n      bbufc.s0(~pclk_sel);\n      bbufc.s1(pclk_sel);\n   endrule\n\n   PCIE_X7#(PcieLanes) pcie_ep <- vMkXilinx7PCIExpress(params, clockGen.clkout0, clockGen.clkout2, bbufc.o);\n   //new PcieWrap#(PcieLanes)  pciew <- mkPcieWrap();\n\n   FIFOF#(AxiTx)             fAxiTx              <- mkBypassFIFOF(clocked_by pcie_ep.user.clk_out, reset_by noReset);\n   FIFOF#(AxiRx)             fAxiRx              <- mkBypassFIFOF(clocked_by pcie_ep.user.clk_out, reset_by noReset);\n\n   (* fire_when_enabled, no_implicit_conditions *)\n   rule every1;\n      pcie_ep.fc.sel(0 /*RECEIVE_BUFFER_AVAILABLE_SPACE*/);\n      pcie_ep.cfg_dsn({ 32'h0000_0001, {{ 8'h1 } , 24'h000A35 }});\n      pcie_ep.rx.np_ok(1);\n      pcie_ep.rx.np_req(1);\n      pcie_ep.tx.cfg_gnt(1);\n      pcie_ep.s_axis_tx.tuser(4'b0);\n      pcie_ep.m_axis_rx.tready(pack(fAxiRx.notFull));\n   endrule\n   rule every2;\n      pcie_ep.pipe_mmcm_lock_in(pack(clockGen.locked));\n   endrule\n   rule every3;\n      pclk_sel_reg1 <= pcie_ep.pipe_pclk_sel_out();\n   endrule\n\n   Clock txoutclk_buf <- mkClockBUFG(clocked_by pcie_ep.pipe_txoutclk_out);\n\n   C2B c2b <- mkC2B(txoutclk_buf);\n   rule txoutrule;\n      b2c.inputclock(c2b.o());\n   endrule\n\n   rule update_psel;\n       let ps = pclk_sel;\n       pclk_sel_reg2 <= pclk_sel_reg1;\n       if ((~pclk_sel_reg2) == 0)\n           ps = 1;\n       else if (pclk_sel_reg2 == 0)\n           ps = 0;\n       pclk_sel <= ps;\n   endrule\n\n   let txready = (pcie_ep.s_axis_tx.tready != 0 && fAxiTx.notEmpty);\n\n   //(* fire_when_enabled, no_implicit_conditions *)\n   rule drive_axi_tx if (txready);\n      let info = fAxiTx.first; fAxiTx.deq;\n      pcie_ep.s_axis_tx.tvalid(1);\n      pcie_ep.s_axis_tx.tlast(info.last);\n      pcie_ep.s_axis_tx.tdata(info.data);\n      pcie_ep.s_axis_tx.tkeep(info.keep);\n   endrule\n\n   (* fire_when_enabled, no_implicit_conditions *)\n   rule drive_axi_tx2 if (!txready);\n      pcie_ep.s_axis_tx.tvalid(0);\n      pcie_ep.s_axis_tx.tlast(0);\n      pcie_ep.s_axis_tx.tdata(0);\n      pcie_ep.s_axis_tx.tkeep(0);\n   endrule\n\n   (* fire_when_enabled *)\n   rule sink_axi_rx if (pcie_ep.m_axis_rx.tvalid != 0);\n      fAxiRx.enq(AxiRx {user: pcie_ep.m_axis_rx.tuser,\n                        last: pcie_ep.m_axis_rx.tlast,\n                        keep: pcie_ep.m_axis_rx.tkeep,\n                        data: pcie_ep.m_axis_rx.tdata });\n   endrule\n\n   // The PCIe endpoint exports full (250MHz) and half-speed (125MHz) clocks\n   Clock clock250 = pcie_ep.user.clk_out;\n   Reset user_reset_n <- mkResetInverter(pcie_ep.user.reset_out, clocked_by clock250);\n   Reset reset250 <- mkSyncReset(5, user_reset_n, clock250);\n\n   ClockGenerator7Params     clkgenParams = defaultValue;\n   clkgenParams.clkin1_period    = 4.000; //  250MHz\n   clkgenParams.clkin1_period    = 4.000;\n   clkgenParams.clkin_buffer     = False;\n   clkgenParams.clkfbout_mult_f  = 4.000; // 1000MHz\n   clkgenParams.clkout0_divide_f = derivedClockPeriod;\n   clkgenParams.clkout1_divide     = round(mainClockPeriod); // defaults to 125MHz;\n   clkgenParams.clkout1_duty_cycle = 0.5;\n   clkgenParams.clkout1_phase      = 0.0000;\n   ClockGenerator7           clkgen <- mkClockGenerator7(clkgenParams, clocked_by clock250, reset_by user_reset_n);\n   Clock clock125 = clkgen.clkout1; /* 125MHz user_clk */\n   Reset reset125 <- mkSyncReset(5, user_reset_n, clock125);\n   Clock derivedClock = clkgen.clkout0;\n   Reset derivedReset <- mkSyncReset(5, user_reset_n, derivedClock);\n\n   FIFOF#(RegChange) changeFifo <- mkFIFOF(clocked_by clock125, reset_by reset125); //mkSizedBRAMFIFOF(128, clocked_by clock125, reset_by reset125);\n\n   Server#(TLPData#(8), TLPData#(8)) tlp8 = (interface Server;\n\t\t\t\t\t\tinterface Put request;\n\t\t\t\t\t\t   method Action put(TLPData#(8) data);\n\t\t\t\t\t\t      fAxiTx.enq(AxiTx {last: pack(data.eof),\n\t\t\t\t\t\t\t\t\tkeep: dwordSwap64BE(data.be), data: dwordSwap64(data.data) });\n\t\t\t\t\t\t   endmethod\n\t\t\t\t\t\tendinterface\n\t\t\t\t\t\tinterface Get response;\n\t\t\t\t\t\t   method ActionValue#(TLPData#(8)) get();\n\t\t\t\t\t\t      let info <- toGet(fAxiRx).get;\n\t\t\t\t\t\t      TLPData#(8) retval = defaultValue;\n\t\t\t\t\t\t      retval.sof  = (info.user[14] == 1);\n\t\t\t\t\t\t      retval.eof  = info.last != 0;\n\t\t\t\t\t\t      retval.hit  = info.user[8:2];\n\t\t\t\t\t\t      retval.be= dwordSwap64BE(info.keep);\n\t\t\t\t\t\t      retval.data = dwordSwap64(info.data);\n\t\t\t\t\t\t      return retval;\n\t\t\t\t\t\t   endmethod\n\t\t\t\t\t\tendinterface\n\t\t\t\t\t     endinterface);\n\n`ifdef PCIE_250MHZ\n   Clock portalClock = clock250;\n   Reset portalReset = reset250;\n`else\n   Clock portalClock = clock125;\n   Reset portalReset = reset125;\n`endif\n   // The PCIE endpoint is processing TLPData#(8)s at 250MHz.  The\n   // AXI bridge is accepting TLPData#(16)s at 125 MHz. The\n   // connection between the endpoint and the AXI contains GearBox\n   // instances for the TLPData#(8)@250 <--> TLPData#(16)@125\n   // conversion.\n   PcieGearbox gb <- mkPcieGearbox(clock250, reset250, portalClock, portalReset);\n   mkConnection(tlp8, gb.tlp, clocked_by portalClock, reset_by portalReset);\n\n   interface tlp = gb.pci;\n   interface pcie    = pcie_ep.pcie;\n   interface PciewrapUser user = pcie_ep.user;\n   interface PciewrapCfg cfg = pcie_ep.cfg;\n   interface regChanges = mapPipe(pack, toPipeOut(changeFifo));\n   interface Clock epPcieClock = clock125;\n   interface Reset epPcieReset = reset125;\n   interface Clock epPortalClock = portalClock;\n   interface Reset epPortalReset = portalReset;\n   interface Clock epDerivedClock = derivedClock;\n   interface Reset epDerivedReset = derivedReset;\nendmodule: mkPcieEndpointX7\n\n"
  },
  {
    "path": "bsv/Pcie2EndpointX7.bsv",
    "content": "// Copyright (c) 2012-2013 Nokia, Inc.\n// Copyright (c) 2014-2015 Quanta Research Cambridge, Inc.\n// Copyright (c) 2015 Connectal Project\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\npackage Pcie2EndpointX7;\n\n`include \"ConnectalProjectConfig.bsv\"\nimport ConnectalConfig   ::*;\nimport BRAMFIFO          ::*;\nimport Clocks            ::*;\nimport Vector            ::*;\nimport BuildVector       ::*;\nimport Connectable       ::*;\nimport GetPut            ::*;\nimport Reserved          ::*;\nimport TieOff            ::*;\nimport DefaultValue      ::*;\nimport DReg              ::*;\nimport Gearbox           ::*;\nimport FIFO              ::*;\nimport FIFOF             ::*;\nimport SpecialFIFOs      ::*;\nimport ClientServer      ::*;\nimport Real              ::*;\n\nimport ConnectalClocks   ::*;\nimport ConnectalXilinxCells   ::*;\nimport XilinxCells       ::*;\nimport PCIE              ::*;\nimport PCIEWRAPPER2      ::*;\nimport Pipe              ::*;\nimport PcieStateChanges  ::*;\nimport Bufgctrl           ::*;\n\n\n////////////////////////////////////////////////////////////////////////////////\n/// Interfaces\n////////////////////////////////////////////////////////////////////////////////\n\ninterface PcieEndpointX7#(numeric type lanes);\n   interface PciewrapPci_exp#(lanes)   pcie;\n   interface PciewrapUser#(lanes)      user;\n   interface PciewrapCfg#(lanes)       cfg;\n   interface Server#(TLPData#(16), TLPData#(16)) tlp;\n   interface PipeOut#(Bit#(64)) regChanges;\n   interface Clock epPcieClock;\n   interface Reset epPcieReset;\n   interface Clock epPortalClock;\n   interface Reset epPortalReset;\n   interface Clock epDerivedClock;\n   interface Reset epDerivedReset;\nendinterface\n\ntypedef struct {\n   Bit#(22)      user;\n   Bit#(1)       last;\n   Bit#(16)      keep;\n   Bit#(128)     data;\n} AxiRx deriving (Bits, Eq);\n\ntypedef struct {\n   Bit#(1)       last;\n   Bit#(16)      keep;\n   Bit#(128)     data;\n} AxiTx deriving (Bits, Eq);\n\n(* synthesize *)\nmodule mkPcieEndpointX7(PcieEndpointX7#(PcieLanes));\n\n   Clock defaultClock <- exposeCurrentClock();\n   Reset defaultReset <- exposeCurrentReset();\n\n   PcieWrap#(PcieLanes) pcie_ep <- mkPcieWrap(defaultClock, defaultReset);\n\n   Clock user_clk = pcie_ep.user_clk_out;\n   Reset user_reset_n <- mkResetInverter(pcie_ep.user_reset_out, clocked_by user_clk);\n\n   FIFOF#(AxiTx)             fAxiTx              <- mkFIFOF(clocked_by user_clk, reset_by user_reset_n);\n   FIFOF#(AxiRx)             fAxiRx              <- mkFIFOF(clocked_by user_clk, reset_by user_reset_n);\n\n   (* fire_when_enabled, no_implicit_conditions *)\n   rule every1;\n      pcie_ep.fc.sel(0 /*RECEIVE_BUFFER_AVAILABLE_SPACE*/);\n      pcie_ep.cfg_dsn({ 32'h0000_0001, {{ 8'h1 } , 24'h000A35 }});\n      pcie_ep.rx.np_ok(1);\n      pcie_ep.rx.np_req(1);\n      pcie_ep.tx.cfg_gnt(1);\n      pcie_ep.s_axis_tx.tuser(4'b0);\n      pcie_ep.m_axis_rx.tready(pack(fAxiRx.notFull));\n   endrule\n   rule every_cfg_err;\n      pcie_ep.cfg_err.acs(0);\n      pcie_ep.cfg_err.aer_headerlog(0);\n      pcie_ep.cfg_err.atomic_egress_blocked(0);\n      pcie_ep.cfg_err.cor(0);\n      pcie_ep.cfg_err.cpl_abort(0);\n      pcie_ep.cfg_err.cpl_timeout(0);\n      pcie_ep.cfg_err.cpl_unexpect(0);\n      pcie_ep.cfg_err.ecrc(0);\n      pcie_ep.cfg_err.internal_cor(0);\n      pcie_ep.cfg_err.internal_uncor(0);\n      pcie_ep.cfg_err.locked(0);\n      pcie_ep.cfg_err.malformed(0);\n      pcie_ep.cfg_err.mc_blocked(0);\n      pcie_ep.cfg_err.norecovery(0);\n      pcie_ep.cfg_err.poisoned(0);\n      pcie_ep.cfg_err.posted(0);\n      pcie_ep.cfg_err.tlp_cpl_header(0);\n      pcie_ep.cfg_err.ur(0);\n   endrule\n   rule every_interrupt;\n      pcie_ep.cfg_interrupt.zzassert(0);\n      pcie_ep.cfg_interrupt.di(0);\n      pcie_ep.cfg_interrupt.stat(0);\n   endrule\n   rule every_mgmt;\n      pcie_ep.cfg_mgmt.byte_en(0);\n      pcie_ep.cfg_mgmt.di(0);\n      pcie_ep.cfg_mgmt.dwaddr(0);\n      pcie_ep.cfg_mgmt.rd_en(0);\n      pcie_ep.cfg_mgmt.wr_en(0);\n      pcie_ep.cfg_mgmt.wr_readonly(0);\n   endrule\n   rule every_pm;\n      pcie_ep.cfg_pm.force_state(0);\n      pcie_ep.cfg_pm.force_state_en(0);\n      pcie_ep.cfg_pm.halt_aspm_l0s(0);\n      pcie_ep.cfg_pm.halt_aspm_l1(0);\n      pcie_ep.cfg_pm.send_pme_to(0);\n      pcie_ep.cfg_pm.wake(0);\n   endrule\n   rule every_pl;\n      pcie_ep.pl.directed_link_auton(0);\n      pcie_ep.pl.directed_link_change(0);\n      pcie_ep.pl.directed_link_speed(0);\n      pcie_ep.pl.directed_link_width(0);\n      pcie_ep.pl.downstream_deemph_source(0);\n      pcie_ep.pl.transmit_hot_rst(0);\n      pcie_ep.pl.upstream_prefer_deemph(1);\n   endrule\n\n   Reg#(Bit#(32)) cyclesReg <- mkReg(0, clocked_by user_clk, reset_by user_reset_n);\n   rule rl_cycles;\n      cyclesReg <= cyclesReg + 1;\n   endrule\n`ifdef DebugPcieStateMachine\n   Vector#(17,Tuple2#(PcieCfgType,Bit#(24))) changeValues = vec(\n      //tuple2(PcieCfg_initial_link_width, extend(pcie_ep.pl.initial_link_width)),\n      //tuple2(PcieCfg_lane_reversal_mode, extend(pcie_ep.pl.lane_reversal_mode)),\n      tuple2(PcieCfg_ltssm_state, extend(pcie_ep.pl.ltssm_state)),\n      tuple2(PcieCfg_phy_link_up, extend(pcie_ep.pl.phy_lnk_up)),\n      tuple2(PcieCfg_received_hot_rst, extend(pcie_ep.pl.received_hot_rst)),\n      //tuple2(PcieCfg_rx_pm_state, extend(pcie_ep.pl.rx_pm_state)),\n      tuple2(PcieCfg_sel_lnk_rate, extend(pcie_ep.pl.sel_lnk_rate)),\n      //tuple2(PcieCfg_negotiated_width, extend(pcie_ep.pl.sel_lnk_width)),\n      //tuple2(PcieCfg_tx_pm_state, extend(pcie_ep.pl.tx_pm_state)),\n      tuple2(PcieCfg_link_up, extend(pcie_ep.user.lnk_up)),\n      tuple2(PcieCfg_link_gen2_cap, extend(pcie_ep.pl_link_gen2_cap)),\n      tuple2(PcieCfg_link_partner_gen2_supported, extend(pcie_ep.pl_link_partner_gen2_supported)),\n      tuple2(unpack(50), extend(pcie_ep.cfg.pcie_link_state)),\n      tuple2(unpack(51), extend(pcie_ep.cfg_aer.rooterr_corr_err_received)),\n      tuple2(unpack(52), extend(pcie_ep.cfg_aer.rooterr_fatal_err_received)),\n      tuple2(unpack(53), extend(pcie_ep.cfg_msg.received)),\n      tuple2(unpack(54), extend(pcie_ep.cfg_msg.received_err_cor)),\n      tuple2(unpack(55), extend(pcie_ep.cfg_msg.received_err_fatal)),\n      tuple2(unpack(56), extend(pcie_ep.cfg_msg.received_err_non_fatal)),\n      tuple2(unpack(57), extend(pcie_ep.cfg_pmcsr.pme_en)),\n      tuple2(unpack(58), extend(pcie_ep.cfg_pmcsr.pme_status)),\n      tuple2(unpack(59), extend(pcie_ep.cfg_pmcsr.powerstate)));\n   let change_pipes <- mapM(mkChangeSource(cyclesReg), changeValues, clocked_by user_clk, reset_by user_reset_n);\n   FunnelPipe#(1,17,RegChange,3) changePipe <- mkFunnelPipesPipelined(change_pipes, clocked_by user_clk, reset_by user_reset_n);\n   FIFOF#(RegChange) changeFifo <- mkSizedBRAMFIFOF(128, clocked_by user_clk, reset_by user_reset_n);\n   mkConnection(changePipe[0], toPipeIn(changeFifo), clocked_by user_clk, reset_by user_reset_n);\n`else\n   FIFOF#(RegChange) changeFifo <- mkFIFOF(clocked_by user_clk, reset_by user_reset_n);\n`endif\n\n   let txready = (pcie_ep.s_axis_tx.tready == 1 && fAxiTx.notEmpty);\n\n   (* fire_when_enabled *)\n   rule drive_axi_tx if (txready);\n      let info = unpack(0);\n      if (fAxiTx.notEmpty) begin\n\t info <- toGet(fAxiTx).get();\n      end\n      pcie_ep.s_axis_tx.tlast(info.last);\n      pcie_ep.s_axis_tx.tdata(info.data);\n      pcie_ep.s_axis_tx.tkeep(info.keep);\n   endrule\n   (* fire_when_enabled, no_implicit_conditions *)\n   rule drive_axi_txvalid if (fAxiTx.notEmpty);\n      pcie_ep.s_axis_tx.tvalid(1);\n   endrule\n   (* fire_when_enabled, no_implicit_conditions *)\n   rule drive_axi_tx2 if (!fAxiTx.notEmpty);\n      pcie_ep.s_axis_tx.tvalid(0);\n      pcie_ep.s_axis_tx.tlast(0);\n      pcie_ep.s_axis_tx.tdata(0);\n      pcie_ep.s_axis_tx.tkeep(0);\n   endrule\n\n   (* fire_when_enabled *)\n   rule sink_axi_rx if (pcie_ep.m_axis_rx.tvalid == 1);\n      fAxiRx.enq(AxiRx {user: pcie_ep.m_axis_rx.tuser,\n                        last: pcie_ep.m_axis_rx.tlast,\n                        keep: pcie_ep.m_axis_rx.tkeep,\n                        data: pcie_ep.m_axis_rx.tdata });\n   endrule\n\n   ClockGenerator7Params     clkgenParams = defaultValue;\n   clkgenParams.clkin1_period    = 4.000; //  250MHz\n   clkgenParams.clkin_buffer     = False;\n   clkgenParams.clkfbout_mult_f  = 4.000; // 1000MHz\n   clkgenParams.clkout0_divide_f = derivedClockPeriod;\n   clkgenParams.clkout1_divide     = round(mainClockPeriod);\n   clkgenParams.clkout1_duty_cycle = 0.5;\n   clkgenParams.clkout1_phase      = 0.0000;\n   clkgenParams.clkout2_divide     = 4; // 250MHz\n   clkgenParams.clkout2_duty_cycle = 0.5;\n   clkgenParams.clkout2_phase      = 0.0000;\n   ClockGenerator7           clkgen <- mkClockGenerator7(clkgenParams, clocked_by user_clk, reset_by user_reset_n);\n   Clock portalClock;\n   Reset portalReset;\n   if (mainClockPeriod == pcieClockPeriod) begin\n      portalClock = user_clk;\n      portalReset = user_reset_n;\n   end\n   else begin\n      portalClock = clkgen.clkout1;\n      portalReset <- mkSyncReset(5, user_reset_n, portalClock);\n   end\n   Clock derivedClock = clkgen.clkout0;\n   Reset derivedReset <- mkSyncReset(5, user_reset_n, derivedClock);\n\n   Server#(TLPData#(16), TLPData#(16)) tlp16 = (interface Server;\n\t\t\t\t\t\tinterface Put request;\n\t\t\t\t\t\t   method Action put(TLPData#(16) data);\n\t\t\t\t\t\t      fAxiTx.enq(AxiTx {last: pack(data.eof),\n\t\t\t\t\t\t\t\t\tkeep: dwordSwap128BE(data.be), data: dwordSwap128(data.data) });\n\t\t\t\t\t\t   endmethod\n\t\t\t\t\t\tendinterface\n\t\t\t\t\t\tinterface Get response;\n\t\t\t\t\t\t   method ActionValue#(TLPData#(16)) get();\n\t\t\t\t\t\t      let info <- toGet(fAxiRx).get;\n\t\t\t\t\t\t      TLPData#(16) retval = defaultValue;\n\t\t\t\t\t\t      retval.sof  = (info.user[14] == 1);\n\t\t\t\t\t\t      retval.eof  = (info.user[21] == 1); // 128-bit interface uses tuser bits instead of tlast to indicate EOF\n\t\t\t\t\t\t      retval.hit  = info.user[8:2];\n\t\t\t\t\t\t      retval.be= dwordSwap128BE(info.keep);\n\t\t\t\t\t\t      retval.data = dwordSwap128(info.data);\n\t\t\t\t\t\t      return retval;\n\t\t\t\t\t\t   endmethod\n\t\t\t\t\t\tendinterface\n\t\t\t\t\t     endinterface);\n\n   interface tlp = tlp16;\n   interface pcie    = pcie_ep.pci_exp;\n   interface PciewrapUser user = pcie_ep.user;\n   interface PciewrapCfg cfg = pcie_ep.cfg;\n   interface regChanges = mapPipe(pack, toPipeOut(changeFifo));\n   interface Clock epPcieClock = user_clk;\n   interface Reset epPcieReset = user_reset_n;\n   interface Clock epPortalClock = portalClock;\n   interface Reset epPortalReset = portalReset;\n   interface Clock epDerivedClock = derivedClock;\n   interface Reset epDerivedReset = derivedReset;\nendmodule: mkPcieEndpointX7\n\nendpackage: Pcie2EndpointX7\n"
  },
  {
    "path": "bsv/Pcie3EndpointX7.bsv",
    "content": "// Copyright (c) 2014-2015 Quanta Research Cambridge, Inc.\n// Copyright (c) 2015 Connectal Project\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\npackage Pcie3EndpointX7;\n\n`include \"ConnectalProjectConfig.bsv\"\nimport BRAMFIFO          ::*;\nimport Clocks            ::*;\nimport Vector            ::*;\nimport BuildVector       ::*;\nimport Connectable       ::*;\nimport GetPut            ::*;\nimport Reserved          ::*;\nimport TieOff            ::*;\nimport DefaultValue      ::*;\nimport DReg              ::*;\nimport Gearbox           ::*;\nimport FIFO              ::*;\nimport FIFOF             ::*;\nimport ConnectalFIFO     ::*;\nimport SpecialFIFOs      ::*;\nimport ClientServer      ::*;\nimport Real              ::*;\nimport XilinxVirtex7PCIE ::*;\nimport BUtils            ::*;\nimport Probe             ::*;\n\nimport ConnectalConfig::*;\nimport ConnectalClocks   ::*;\nimport ConnectalXilinxCells   ::*;\nimport XilinxCells       ::*;\nimport PCIE              ::*;\n`ifdef VirtexUltrascalePlus\nimport PCIEWRAPPER3uplus ::*;\n`else\n  `ifdef XilinxUltrascale\nimport PCIEWRAPPER3u     ::*;\n  `else\nimport PCIEWRAPPER3      ::*;\n  `endif\n`endif\nimport Bufgctrl           ::*;\nimport PcieGearbox       :: *;\nimport Pipe              :: *;\n\ninterface PcieEndpointX7#(numeric type lanes);\n   interface PciewrapPci_exp#(lanes)           pcie;\n   interface PciewrapUser#(lanes)              user;\n   interface Server#(TLPData#(16), TLPData#(16)) tlpr;\n   interface Server#(TLPData#(16), TLPData#(16)) tlpc;\n   interface Put#(Tuple2#(Bit#(64),Bit#(32)))  interruptRequest;\n   interface PipeOut#(Bit#(64)) regChanges;\n   interface Clock epPcieClock;\n   interface Reset epPcieReset;\n   interface Clock epPortalClock;\n   interface Reset epPortalReset;\n   interface Clock epDerivedClock;\n   interface Reset epDerivedReset;\nendinterface\n\ntypedef struct {\n   Bit #(256)     data;\n   Bool          sop;\n   Bool          eop;\n   Bit #(8)      keep;\n   TLPFirstDWBE  first_be;\n   TLPFirstDWBE  last_be;\n} AxiStCq deriving (Bits, Eq);\n\ntypedef struct {\n   Bit #(256)     data;\n   Bit #(8)      keep;\n   Bool          last;\n} AxiStCc deriving (Bits, Eq);\n\ntypedef struct {\n   Bit #(256)     data;\n   Bool          last;\n   Bit #(8)      keep;\n   Bit #(4)      first_be;\n   Bit #(4)      last_be;\n} AxiStRq deriving (Bits, Eq);\n\ntypedef struct {\n   Bit #(256)     data;\n   Bool          sop;\n   Bool          eop;\n   Bit #(8)      keep;\n   Bit #(8)      be;\n} AxiStRc deriving (Bits, Eq);\n\nfunction TLPData#(16) convertCQDescriptorToTLP16(CQDescriptor desc, Bit#(32) data, TLPFirstDWBE first, TLPLastDWBE last);\n   TLPMemoryIO3DWHeader header = defaultValue;\n   header.format     = tpl_1(convertCQReqTypeToTLPFmtType(desc.reqtype));\n   header.pkttype    = tpl_2(convertCQReqTypeToTLPFmtType(desc.reqtype));\n   header.tclass     = desc.tclass;\n   header.relaxed    = desc.relaxed;\n   header.nosnoop    = desc.nosnoop;\n   header.length     = (desc.dwcount == 1024) ? 0 : truncate(desc.dwcount);\n   header.reqid      = desc.reqid;\n   header.tag        = desc.tag;\n   header.lastbe     = last;\n   header.firstbe    = first;\n   header.addr       = truncate(desc.address);\n   header.data       = convertDW(data);\n   \n   Bool is3DW = isReadReqType(desc.reqtype);\n   Bool is3Or4DW = isReadReqType(desc.reqtype) || (desc.dwcount == 1);\n\n   TLPData#(16) retval = defaultValue;\n   retval.sof   = True;\n   retval.eof   = is3Or4DW;\n   retval.hit   = (1 << pack(desc.barid));\n   retval.data  = pack(header);\n   retval.be    = (is3DW ? 16'hFFF0 : 16'hFFFF);\n   \n   return retval;\nendfunction\n\nfunction TLPData#(16) convertRCDescriptorToTLP16(RCDescriptor desc, Bit#(32) data);\n   TLPCompletionHeader header = defaultValue;\n   header.tclass    = desc.tclass;\n   header.relaxed   = desc.relaxed;\n   header.nosnoop   = desc.nosnoop;\n   header.cmplid    = desc.complid;\n   header.tag       = desc.tag;\n   header.reqid     = desc.reqid;\n   header.poison    = desc.poisoned;\n   header.cstatus   = desc.status;\n   header.length    = (desc.dwcount == 1024) ? 0 : truncate(desc.dwcount);\n   header.bytecount = (desc.bytecount == 4096) ? 0 : truncate(desc.bytecount);\n   header.loweraddr = truncate(desc.loweraddr);\n   header.data      = convertDW(data);\n\n   Bool is3DW = (desc.dwcount == 0);\n   Bool is3Or4DW = (desc.dwcount == 0) || (desc.dwcount == 1);\n   TLPData#(16) retval = defaultValue;\n   retval.sof   = True;\n   retval.eof   = is3Or4DW;\n   retval.hit   = 1; // XXX\n   retval.data  = pack(header);\n   retval.be    = (is3DW ? 16'hFFF0 : 16'hFFFF);\n   \n   return retval;\nendfunction\n\ntypedef struct {\n   Bit#(32) timestamp;\n   Bit#(8) src;\n   Bit#(24) value;\n} RegChange deriving (Bits);\n\ntypedef enum {\n   Pcie3Cfg_none,\n   Pcie3Cfg_current_speed,\n   Pcie3Cfg_dpa_substate_change,\n   Pcie3Cfg_err_cor_out,\n   Pcie3Cfg_err_fatal_out,\n   Pcie3Cfg_err_nonfatal_out,\n   Pcie3Cfg_flr_in_process,\n   Pcie3Cfg_function_power_state,\n   Pcie3Cfg_function_status,\n   Pcie3Cfg_hot_reset_out,\n   Pcie3Cfg_link_power_state,\n   Pcie3Cfg_ltr_enable,\n   Pcie3Cfg_ltssm_state,\n   Pcie3Cfg_max_payload,\n   Pcie3Cfg_max_read_req,\n   Pcie3Cfg_negotiated_width,\n   Pcie3Cfg_obff_enable,\n   Pcie3Cfg_phy_link_down,\n   Pcie3Cfg_phy_link_status,\n   Pcie3Cfg_pl_status_change,\n   Pcie3Cfg_power_state_change_interrupt,\n   Pcie3Cfg_rcb_status,\n   Pcie3Cfg_rq_backpressure\n   } Pcie3CfgType deriving (Bits,Eq);\n\n(* synthesize *)\nmodule mkPcieEndpointX7#(Clock pcie_sys_clk_gt)(PcieEndpointX7#(PcieLanes));\n\n   PCIEParams params = defaultValue;\n   Clock defaultClock <- exposeCurrentClock();\n   Reset defaultReset <- exposeCurrentReset();\n   Reset defaultResetInverted <- mkResetInverter(defaultReset, clocked_by defaultClock);\n   PcieWrap#(PcieLanes) pcie_ep <- mkPcieWrap(defaultClock,\n`ifdef XilinxUltrascale\n      pcie_sys_clk_gt, defaultReset\n`else\n      defaultResetInverted\n`endif\n);\n\n   // The PCIe endpoint exports full (250MHz) and half-speed (125MHz) clocks\n   Clock pcieClock250 = pcie_ep.user_clk;\n   Reset user_reset_n <- mkResetInverter(pcie_ep.user_reset, clocked_by pcie_ep.user_clk);\n   Reset pcieReset250 <- mkSyncReset(5, user_reset_n, pcieClock250);\n\n   ClockGenerator7Params     clkgenParams = defaultValue;\n   clkgenParams.clkin1_period    = 4.000; //  250MHz\n   clkgenParams.clkin1_period    = 4.000;\n   clkgenParams.clkin_buffer     = False;\n   clkgenParams.clkfbout_mult_f  = 4.000; // 1000MHz\n   clkgenParams.clkout0_divide_f = derivedClockPeriod;\n   clkgenParams.clkout1_divide     = round(mainClockPeriod);\n   clkgenParams.clkout1_duty_cycle = 0.5;\n   clkgenParams.clkout1_phase      = 0.0000;\n   ClockGenerator7           clkgen <- mkClockGenerator7(clkgenParams, clocked_by pcieClock250, reset_by pcieReset250);\n   Clock mainClock = clkgen.clkout1;\n   Reset mainReset <- mkSyncReset(10, pcieReset250, mainClock);\n   Clock derivedClock = clkgen.clkout0;\n   Reset derivedReset <- mkSyncReset(5, pcieReset250, derivedClock);\n   Reset user_reset <- mkSyncReset(5, pcie_ep.user_reset, pcie_ep.user_clk);\n\n   // FIFOS\n   FIFOF#(AxiStCq) fAxiCq <- mkFIFOF(clocked_by pcie_ep.user_clk, reset_by user_reset_n);\n   FIFOF#(AxiStRc) fAxiRc <- mkCFFIFOF(clocked_by pcie_ep.user_clk, reset_by user_reset_n);\n\n   FIFOF#(AxiStRq) fAxiRq <- mkCFFIFOF(clocked_by pcie_ep.user_clk, reset_by user_reset_n);\n   FIFOF#(AxiStCc) fAxiCc <- mkFIFOF(clocked_by pcie_ep.user_clk, reset_by user_reset_n);\n\n   FIFOF#(TLPData#(16)) fcq <- mkFIFOF(clocked_by pcie_ep.user_clk, reset_by user_reset_n);\n   FIFOF#(TLPData#(16)) frc <- mkFIFOF(clocked_by pcie_ep.user_clk, reset_by user_reset_n);\n   FIFOF#(TLPData#(16)) fcc <- mkFIFOF(clocked_by pcie_ep.user_clk, reset_by user_reset_n);\n   FIFOF#(TLPData#(16)) frq <- mkFIFOF(clocked_by pcie_ep.user_clk, reset_by user_reset_n);\n\n   FIFOF#(Tuple2#(Bit#(64),Bit#(32))) intrFifo <- mkFIFOF(clocked_by pcie_ep.user_clk, reset_by user_reset_n);\n\n   // Drive s_axis_rq\n   let rq_txready = (pcie_ep.s_axis_rq.tready != 0 && fAxiRq.notEmpty);\n\n   //(* fire_when_enabled, no_implicit_conditions *)\n   rule drive_axi_rq;\n      let tvalid = 0;\n      let tlast = 0;\n      let tdata = 0;\n      let tkeep = 0;\n      let tuser = 0;\n      if (rq_txready) begin\n\t let info = fAxiRq.first; fAxiRq.deq;\n\t tvalid = 1;\n\t tlast = pack(info.last);\n\t tdata = info.data;\n\t tkeep = info.keep;\n\t tuser = {0, info.last_be, info.first_be};\n      end\n\n      pcie_ep.s_axis_rq.tvalid(tvalid);\n      pcie_ep.s_axis_rq.tlast(tlast);\n      pcie_ep.s_axis_rq.tdata(tdata);\n      pcie_ep.s_axis_rq.tkeep(tkeep);\n      pcie_ep.s_axis_rq.tuser(tuser);\n   endrule\n\n   Reg#(Bit#(16)) rqBackpressureCycles <- mkReg(0, clocked_by pcie_ep.user_clk, reset_by user_reset_n);\n   Reg#(Bit#(16)) rqBackpressureCount <- mkReg(0, clocked_by pcie_ep.user_clk, reset_by user_reset_n);\n   Reg#(Bool)     rqBackpressure       <- mkReg(False, clocked_by pcie_ep.user_clk, reset_by user_reset_n);\n   Reg#(Bit#(32)) rqBackpressureCountSum <- mkReg(0, clocked_by pcie_ep.user_clk, reset_by user_reset_n);\n   Reg#(Bit#(32)) rqBackpressureEvents   <- mkReg(0, clocked_by pcie_ep.user_clk, reset_by user_reset_n);\n   rule rlBackpressureEnter if (!rqBackpressure);\n      if (pcie_ep.s_axis_rq.tready == 0 && fAxiRq.notEmpty) begin\n\t rqBackpressure <= True;\n\t rqBackpressureCycles <= 0;\n      end\n   endrule\n   rule rlBackpressureExit if (rqBackpressure);\n      rqBackpressureCycles <= rqBackpressureCycles + 1;\n      if (pcie_ep.s_axis_rq.tready != 0 || !fAxiRq.notEmpty) begin\n\t rqBackpressure <= False;\n\t let count = rqBackpressureCycles;\n\t count[15] = ~rqBackpressureCount[15];\n\t if (count > 5)\n\t    rqBackpressureCount <= count;\n\t rqBackpressureCountSum <= rqBackpressureCountSum + extend(count);\n\t rqBackpressureEvents <= rqBackpressureEvents + 1;\n      end\n   endrule\n\n   // Drive s_axis_cc\n   let cc_txready = (pcie_ep.s_axis_cc.tready != 0 && fAxiCc.notEmpty);\n\n   //(* fire_when_enabled, no_implicit_conditions *)\n   rule drive_axi_cc if (cc_txready);\n      let info = fAxiCc.first; fAxiCc.deq;\n      $display(\"drive axi_cc, data: %h, keep: %h, last: %h\", info.data, info.keep, info.last);\n      pcie_ep.s_axis_cc.tvalid(1);\n      pcie_ep.s_axis_cc.tlast(pack(info.last));\n      pcie_ep.s_axis_cc.tdata(info.data);\n      pcie_ep.s_axis_cc.tkeep(info.keep);\n      pcie_ep.s_axis_cc.tuser(0);\n   endrule\n\n   (* fire_when_enabled, no_implicit_conditions *)\n   rule drive_axi_cc2 if (!cc_txready);\n      pcie_ep.s_axis_cc.tvalid(0);\n      pcie_ep.s_axis_cc.tlast(0);\n      pcie_ep.s_axis_cc.tdata(0);\n      pcie_ep.s_axis_cc.tkeep(0);\n      pcie_ep.s_axis_cc.tuser(0);\n   endrule\n\n   (* fire_when_enabled, no_implicit_conditions *)\n   rule drive_axi_rc_ready;\n      pcie_ep.m_axis_rc.tready (duplicate (pack (fAxiRc.notFull)));\n   endrule\n \n   // Drive m_axis_rc\n   (* fire_when_enabled *)\n   rule sink_axi_rc if (pcie_ep.m_axis_rc.tvalid != 0 && fAxiRc.notFull);\n      let rc = AxiStRc {data:pcie_ep.m_axis_rc.tdata,\n\t\t\tsop: unpack (pcie_ep.m_axis_rc.tuser [32]),         // tuser.is_sof_0\n\t\t\teop: unpack (pcie_ep.m_axis_rc.tlast),\n\t\t\tkeep:pcie_ep.m_axis_rc.tkeep,\n\t\t\tbe:  truncate (pcie_ep.m_axis_rc.tuser [31:0])};    // tuser.byte_en\n      fAxiRc.enq (rc);\n   endrule\n\n   (* fire_when_enabled, no_implicit_conditions *)\n   rule drive_axi_cq_ready;\n      pcie_ep.m_axis_cq.tready (duplicate (pack (fAxiCq.notFull)));\n   endrule\n\n   (* fire_when_enabled *)\n   rule sink_axi_cq if (pcie_ep.m_axis_cq.tvalid != 0 && fAxiCq.notFull);\n      let cq = AxiStCq {data:     pcie_ep.m_axis_cq.tdata,\n\t\t\tsop:      unpack (pcie_ep.m_axis_cq.tuser [40]),  // tuser.sop\n\t\t\teop:      unpack (pcie_ep.m_axis_cq.tlast),\n\t\t\tkeep:     pcie_ep.m_axis_cq.tkeep,\n\t\t\tfirst_be: pcie_ep.m_axis_cq.tuser [3:0],    // tuser.first_be,\n\t\t\tlast_be:  pcie_ep.m_axis_cq.tuser [7:4]};   // tuser.last_be\n      fAxiCq.enq (cq);\n   endrule\n\n   // CQ.\n   CQDescriptor cq_desc = unpack(fAxiCq.first.data [127:0]);\n\n   rule rl_cq_wr_header (fAxiCq.first.sop && ((cq_desc.reqtype == MEMORY_WRITE) || (cq_desc.reqtype == IO_WRITE)));\n      Bit#(32) data = fAxiCq.first.data[159:128];\n      // get data;\n      TLPData#(16) tlp16 = convertCQDescriptorToTLP16(cq_desc, data, fAxiCq.first.first_be, fAxiCq.first.last_be);\n      $display(\"cq_desc.reqtype=%h\", cq_desc.reqtype);\n      // enqueue?\n      fcq.enq(tlp16);\n      fAxiCq.deq;\n   endrule\n\n   // Write data payload, no data remaining\n   rule rl_cq_wr_payload((!fAxiCq.first.sop));\n      fAxiCq.deq;\n   endrule\n\n   // Write data payload, 1 to 3 DWs remaining\n   // Write data payload, 4 or more DWs remaining\n\n   rule rl_cq_rd_header (fAxiCq.first.sop && ((cq_desc.reqtype == MEMORY_READ) || (cq_desc.reqtype == IO_READ)));\n      Bit#(32) data = 0;\n      TLPData#(16) tlp16 = convertCQDescriptorToTLP16(cq_desc, data, fAxiCq.first.first_be, fAxiCq.first.last_be);\n      $display(\"rl_cq_rd_header: cq_desc = %16x\", cq_desc);\n      fcq.enq(tlp16);\n      fAxiCq.deq;\n   endrule\n\n   // RC.\n   Reg#(DWCount) rc_dwcount <- mkRegU(clocked_by pcie_ep.user_clk, reset_by user_reset_n);\n   Reg#(Bool) rc_even <- mkReg(True, clocked_by pcie_ep.user_clk, reset_by user_reset_n);\n\n   rule rl_rc_header (fAxiRc.first.sop && rc_even);\n      RCDescriptor rc_desc = unpack(fAxiRc.first.data [95:0]);\n      // RC descriptor always 96 bytes with first data word in bits 127:96                                                                                            \n      Bit#(32) data = byteSwap(fAxiRc.first.data[127:96]);\n      TLPData#(16) tlp16 = convertRCDescriptorToTLP16(rc_desc, data);\n      rc_dwcount <= (rc_desc.dwcount == 0) ? 0 : rc_desc.dwcount - 1;\n      frc.enq(tlp16);\n      let even = False;\n      if (rc_desc.dwcount == 0 || rc_desc.dwcount == 1) begin\n        fAxiRc.deq;\n        even = True;\n      end\n      rc_even <= even;\n   endrule\n\n   rule rl_rc_data ((!rc_even || !(fAxiRc.first.sop)) && (rc_dwcount != 0));\n      Bit#(16) be16;\n      case (rc_dwcount)\n         1: be16 = 16'hF000;\n         2: be16 = 16'hFF00;\n         3: be16 = 16'hFFF0;\n         default: be16 = 16'hFFFF;\n      endcase\n      let last = (rc_dwcount <= 4);\n      let dwcount = rc_dwcount - 4;\n      if (last) dwcount = 0;\n      let data = (rc_even) ? fAxiRc.first.data[127:0]: fAxiRc.first.data[255:128];\n      TLPData#(16) tlp16 = TLPData{sof: False,\n                                   eof: last,\n                                   hit: 0,\n                                   be: be16,\n                                   data: pack(data)};\n      frc.enq(tlp16);\n      if (last || !rc_even) begin\n         fAxiRc.deq;\n      end\n      rc_dwcount <= dwcount;\n      rc_even <= (last) ? True : !rc_even;\n   endrule\n\n   Reg#(DWCount) cc_dwcount <- mkReg(0, clocked_by pcie_ep.user_clk, reset_by user_reset_n);\n   FIFOF#(TLPData#(16)) fcc_tlps <- mkFIFOF (clocked_by pcie_ep.user_clk, reset_by user_reset_n);\n   // CC.\n   rule get_cc_tlps;\n      let tlp <- toGet(fcc).get;\n      fcc_tlps.enq(tlp);\n   endrule\n\n   rule rl_cc_header(fcc_tlps.first.sof);\n      match { .cc_desc, .dw} = convertTLP16ToCCDescriptor(fcc_tlps.first);\n      cc_dwcount <= cc_desc.dwcount - 1;\n      fAxiCc.enq(AxiStCc {data: zeroExtend({dw, pack(cc_desc)[95:0]}),\n                       last: fcc_tlps.first.eof,\n                       keep: 8'h0F});\n      fcc_tlps.deq;\n   endrule\n\n   rule rl_cc_data((!fcc_tlps.first.sof) && (cc_dwcount != 0));\n      Bit#(256) x = zeroExtend(fcc_tlps.first.data); //FIXME\n      fAxiCc.enq(AxiStCc {data: {x},\n                       last: cc_dwcount <= 4,\n                       keep: (cc_dwcount == 3) ? 8'h0F : 8'hFF});\n      fcc_tlps.deq;\n   endrule\n\n   // RQ.\n   FIFOF#(TLPData#(16)) frq_tlps <- mkFIFOF (clocked_by pcie_ep.user_clk, reset_by user_reset_n);\n   Reg#(Bit#(4)) rq_first_be <- mkReg(0, clocked_by pcie_ep.user_clk, reset_by user_reset_n);\n   Reg#(Bit#(4)) rq_last_be <- mkReg(0, clocked_by pcie_ep.user_clk, reset_by user_reset_n);\n   Reg#(Bool)    rq_even    <- mkRegU(clocked_by pcie_ep.user_clk, reset_by user_reset_n);\n   Reg#(DWCount) rq_dwcount <- mkReg(0, clocked_by pcie_ep.user_clk, reset_by user_reset_n);\n   Reg#(AxiStRq) rq_rq <- mkRegU(clocked_by pcie_ep.user_clk, reset_by user_reset_n);\n\n   rule rl_rq_tlps;\n      let tlp <- toGet(frq).get;\n      frq_tlps.enq(tlp);\n   endrule\n\n   rule rl_rq_header if (frq_tlps.first.sof);\n      TLPData#(16) tlp <- toGet(frq_tlps).get();\n      match { .rq_desc, .first_be, .last_be, .mdata} = convertTLP16ToRQDescriptor(tlp);\n\n      let dwcount = ((rq_desc.reqtype == MEMORY_WRITE) ? rq_desc.dwcount : 0);\n      rq_dwcount <= dwcount;\n      rq_even <= False;\n      rq_first_be <= first_be;\n      rq_last_be <= last_be;\n      let last = (rq_desc.reqtype == MEMORY_WRITE) ? (dwcount <= 4) : True;\n      let rq = AxiStRq {data: zeroExtend(pack(rq_desc)), //FIXME:\n\t\t\tlast: last,\n\t\t\tkeep: 8'h0F,\n\t\t\tfirst_be: first_be,\n\t\t\tlast_be: last_be};\n      if (rq_desc.reqtype == MEMORY_WRITE)\n\t rq_rq <= rq;\n      else\n\t fAxiRq.enq(rq);\n   endrule\n\n   // more data\n   rule rl_rq_data if (rq_dwcount != 0);\n      TLPData#(16) tlp <- toGet(frq_tlps).get();\n      let rq = rq_rq;\n      let last = (rq_dwcount <= 4);\n      let dwcount = rq_dwcount - 4;\n      Bit#(8) keep;\n      if (last)\n\tdwcount = 0;\n      if (rq_even) begin\n\t rq.data[127:0] = tlp.data;\n\tcase (rq_dwcount)\n\t   1: keep = 8'h01;\n\t   2: keep = 8'h03;\n\t   3: keep = 8'h07;\n\t   default: keep = 8'h0f;\n\tendcase\n      end\n      else begin\n\trq.data[255:128] = tlp.data;\n\tcase (rq_dwcount)\n\t   1: keep = 8'h1f;\n\t   2: keep = 8'h3f;\n\t   3: keep = 8'h7f;\n\t   default: keep = 8'hff;\n\tendcase\n      end\n      rq.last = last;\n      rq.first_be = rq_first_be;\n      rq.last_be = rq_last_be;\n      rq.keep = keep;\n\n      if (!rq_even || last)\n\t fAxiRq.enq(rq);\n      if (rq_even)\n\trq_rq <= rq;\n      rq_dwcount <= dwcount;\n      rq_even <= (last) ? False : !rq_even;\n   endrule\n\n   FIFO#(Bool) intrMutex <- mkFIFO1(clocked_by pcie_ep.user_clk, reset_by user_reset_n);\n   Wire#(Bool) msix_int_enable <- mkDWire(False, clocked_by pcie_ep.user_clk, reset_by user_reset_n);\n\n   rule rl_intr;\n      if (pcie_ep.cfg.interrupt_msix_enable[0] == 1) begin\n\t match { .addr, .data } <- toGet(intrFifo).get();\n\t pcie_ep.cfg.interrupt_msix_address(addr);\n\t pcie_ep.cfg.interrupt_msix_data(data);\n\t msix_int_enable <= True;\n\t intrMutex.enq(True);\n      end\n   endrule: rl_intr\n   rule rl_intr_enable;\n      pcie_ep.cfg.interrupt_msix_int(pack(msix_int_enable));\n   endrule\n\n\n   rule rl_intr_sent if (\n`ifdef VirtexUltrascalePlus\n      // both MSI and MSI-X use these ports on Ultrascale Plus\n      pcie_ep.cfg.interrupt_msi_sent() == 1|| pcie_ep.cfg.interrupt_msi_fail() == 1\n`else\n      pcie_ep.cfg.interrupt_msix_sent() == 1|| pcie_ep.cfg.interrupt_msix_fail() == 1\n`endif\n      );\n      intrMutex.deq();\n   endrule\n\n   Reg#(Bit#(32)) cyclesReg <- mkReg(0, clocked_by pcie_ep.user_clk, reset_by user_reset_n);\n   rule rl_cycles;\n      cyclesReg <= cyclesReg + 1;\n   endrule\n\n   module mkChangeSource#(Tuple2#(Pcie3CfgType,Bit#(24)) tpl)(PipeOut#(RegChange));\n      match { .src, .v } = tpl;\n      let snapshot <- mkReg(0);\n      let changeFifo <- mkFIFOF1();\n      rule rl_update if (v != snapshot);\n\t if (changeFifo.notFull) begin\n\t    changeFifo.enq(RegChange { timestamp: cyclesReg, src: extend(pack(src)), value: extend(v) });\n\t    snapshot <= v;\n\t end\n      endrule\n      return toPipeOut(changeFifo);\n   endmodule\n\n   // let phy_link_status_probe <- mkProbe(clocked_by pcie_ep.user_clk, reset_by pcie_ep.user_reset);\n   // let ltssm_state_probe <- mkProbe(clocked_by pcie_ep.user_clk, reset_by pcie_ep.user_reset);\n   // rule probe_phy_link_status;\n   //    phy_link_status_probe <= pcie_ep.cfg.phy_link_status;\n   //    ltssm_state_probe <= pcie_ep.cfg.ltssm_state;\n   // endrule\n\n`ifdef DebugPcieStateMachine\n   Vector#(20,Tuple2#(Pcie3CfgType,Bit#(24))) changeValues = vec(\n      tuple2(Pcie3Cfg_rq_backpressure, extend(rqBackpressureCount)),\n      tuple2(Pcie3Cfg_current_speed, extend(pcie_ep.cfg.current_speed)),\n//      tuple2(Pcie3Cfg_dpa_substate_change, extend(pcie_ep.cfg.dpa_substate_change)),\n      tuple2(Pcie3Cfg_err_cor_out, extend(pcie_ep.cfg.err_cor_out)),\n      tuple2(Pcie3Cfg_err_fatal_out, extend(pcie_ep.cfg.err_fatal_out)),\n      tuple2(Pcie3Cfg_err_nonfatal_out, extend(pcie_ep.cfg.err_nonfatal_out)),\n      tuple2(Pcie3Cfg_flr_in_process, extend(pcie_ep.cfg.flr_in_process)),\n      tuple2(Pcie3Cfg_function_power_state, extend(pcie_ep.cfg.function_power_state)),\n      tuple2(Pcie3Cfg_function_status, extend(pcie_ep.cfg.function_status)),\n      tuple2(Pcie3Cfg_hot_reset_out, extend(pcie_ep.cfg.hot_reset_out)),\n      tuple2(Pcie3Cfg_link_power_state, extend(pcie_ep.cfg.link_power_state)),\n//      tuple2(Pcie3Cfg_ltr_enable, extend(pcie_ep.cfg.ltr_enable)),\n      tuple2(Pcie3Cfg_ltssm_state, extend(pcie_ep.cfg.ltssm_state)),\n      tuple2(Pcie3Cfg_max_payload, extend(pcie_ep.cfg.max_payload)),\n      tuple2(Pcie3Cfg_max_read_req, extend(pcie_ep.cfg.max_read_req)),\n      tuple2(Pcie3Cfg_negotiated_width, extend(pcie_ep.cfg.negotiated_width)),\n      tuple2(Pcie3Cfg_obff_enable, extend(pcie_ep.cfg.obff_enable)),\n      tuple2(Pcie3Cfg_phy_link_down, extend(pcie_ep.cfg.phy_link_down)),\n      tuple2(Pcie3Cfg_phy_link_status, extend(pcie_ep.cfg.phy_link_status)),\n      tuple2(Pcie3Cfg_pl_status_change, extend(pcie_ep.cfg.pl_status_change)),\n      tuple2(Pcie3Cfg_power_state_change_interrupt, extend(pcie_ep.cfg.power_state_change_interrupt)),\n      tuple2(Pcie3Cfg_rcb_status, extend(pcie_ep.cfg.rcb_status)));\n   let change_pipes <- mapM(mkChangeSource, changeValues, clocked_by pcie_ep.user_clk, reset_by user_reset_n);\n\n   FunnelPipe#(1,20,RegChange,3) changePipe <- mkFunnelPipesPipelined(change_pipes, clocked_by pcie_ep.user_clk, reset_by user_reset_n);\n   FIFOF#(RegChange) changeFifo <- mkSizedBRAMFIFOF(128, clocked_by pcie_ep.user_clk, reset_by user_reset_n);\n   mkConnection(changePipe[0], toPipeIn(changeFifo), clocked_by pcie_ep.user_clk, reset_by user_reset_n);\n`else\n   let cs <- mkChangeSource(tuple2(Pcie3Cfg_rq_backpressure, extend(rqBackpressureCount)), clocked_by pcie_ep.user_clk, reset_by user_reset_n);\n   FIFOF#(RegChange) changeFifo <- mkFIFOF(clocked_by pcie_ep.user_clk, reset_by user_reset_n);\n   mkConnection(cs, toPipeIn(changeFifo), clocked_by pcie_ep.user_clk, reset_by user_reset_n);\n`endif\n\n   rule rl_drive_cfg_status_if;\n      pcie_ep.cfg.config_space_enable(1);\n      pcie_ep.cfg.dsn(64'hf001ba7700000000);\n      pcie_ep.cfg.ds_bus_number(0);\n      pcie_ep.cfg.ds_device_number(0);\n      pcie_ep.cfg.ds_port_number(0);\n      pcie_ep.cfg.err_cor_in(0);\n      pcie_ep.cfg.err_uncor_in(0);\n      pcie_ep.cfg.flr_done(0);\n      pcie_ep.cfg.hot_reset_in(0);\n      pcie_ep.cfg.link_training_enable(1);\n`ifndef VirtexUltrascalePlus\n      pcie_ep.cfg.per_function_number(0);\n      pcie_ep.cfg.per_function_output_request(0);\n      pcie_ep.cfg.subsys_vend_id(16'h1be8);\n`endif\n`ifdef VirtexUltrascalePlus      \n      pcie_ep.cfg.pm_aspm_l1_entry_reject(0);\n      pcie_ep.cfg.pm_aspm_tx_l0s_entry_disable(1);\n`endif\n      pcie_ep.cfg.power_state_change_ack(1);\n      pcie_ep.cfg.vf_flr_done(0);\n\n      pcie_ep.pcie.cq_np_req(1);\n\n      pcie_ep.cfg_req_pm_transition.l23_ready(0);\n   endrule\n\n   // The PCIE endpoint is processing Gen3 descriptors at 250MHz. The\n   // AXI bridge is accepting TLPData#(16)s at 250 MHz. The\n   // conversion uses half of Gen3 descriptor.\n   //mkConnection(tlp8, gb.tlp, clocked_by portalClock, reset_by portalReset);\n\n   let portalClock = (mainClockPeriod == pcieClockPeriod) ? pcieClock250 : mainClock;\n   let portalReset = (mainClockPeriod == pcieClockPeriod) ? pcieReset250 : mainReset;\n\n   interface Server tlpr;\n      interface request = toPut(frq);\n      interface response = toGet(frc);\n   endinterface\n   // Requests from other PCIe devices\n   interface Server tlpc;\n      interface request = toPut(fcc);\n      interface response = toGet(fcq);\n   endinterface\n   interface interruptRequest = toPut(intrFifo);\n   interface pcie    = pcie_ep.pci_exp;\n   interface Pcie3wrapUser user = pcie_ep.user;\n   interface regChanges = mapPipe(pack, toPipeOut(changeFifo));\n   interface Clock epPcieClock = pcieClock250;\n   interface Reset epPcieReset = pcieReset250;\n   interface Clock epPortalClock = portalClock;\n   interface Reset epPortalReset = portalReset;\n   interface Clock epDerivedClock = derivedClock;\n   interface Reset epDerivedReset = derivedReset;\nendmodule: mkPcieEndpointX7\n\nendpackage: Pcie3EndpointX7\n"
  },
  {
    "path": "bsv/Pcie3RootPortX7.bsv",
    "content": "// Copyright (c) 2014-2015 Quanta Research Cambridge, Inc.\n// Copyright (c) 2015 Connectal Project\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\npackage Pcie3RootPortX7;\n\n`include \"ConnectalProjectConfig.bsv\"\nimport BRAMFIFO          ::*;\nimport Clocks            ::*;\nimport Vector            ::*;\nimport BuildVector       ::*;\nimport Connectable       ::*;\nimport GetPut            ::*;\nimport Reserved          ::*;\nimport TieOff            ::*;\nimport DefaultValue      ::*;\nimport DReg              ::*;\nimport Gearbox           ::*;\nimport FIFO              ::*;\nimport FIFOF             ::*;\nimport CFFIFO            ::*;\nimport SpecialFIFOs      ::*;\nimport ClientServer      ::*;\nimport Real              ::*;\nimport XilinxVirtex7PCIE ::*;\nimport BUtils            ::*;\nimport Probe             ::*;\n\nimport ConnectalConfig::*;\nimport ConnectalClocks   ::*;\nimport ConnectalXilinxCells   ::*;\nimport XilinxCells       ::*;\nimport PCIE              ::*;\nimport ROOTPCIEWRAPPER3  ::*;\nimport Bufgctrl           ::*;\nimport PcieGearbox       :: *;\nimport Pipe              :: *;\n\ninterface PcieRootPortX7#(numeric type lanes);\n   interface PcieRpPci_exp#(lanes)           pcie;\n   interface PcieRpUser#(lanes)              user;\n   interface PcieRpPipe#(lanes)              pipe;\n   interface PcieRpCommon#(lanes)            common;\n   interface Server#(TLPData#(16), TLPData#(16)) tlpr;\n   interface Server#(TLPData#(16), TLPData#(16)) tlpc;\n   interface Put#(Tuple2#(Bit#(64),Bit#(32)))  interruptRequest;\n   interface PipeOut#(Bit#(64)) regChanges;\n   interface Clock epPcieClock;\n   interface Reset epPcieReset;\n   interface Clock epPortalClock;\n   interface Reset epPortalReset;\n   interface Clock epDerivedClock;\n   interface Reset epDerivedReset;\nendinterface\n\ntypedef struct {\n   Bit #(256)     data;\n   Bool          sop;\n   Bool          eop;\n   Bit #(8)      keep;\n   TLPFirstDWBE  first_be;\n   TLPFirstDWBE  last_be;\n} AxiStCq deriving (Bits, Eq);\n\ntypedef struct {\n   Bit #(256)     data;\n   Bit #(8)      keep;\n   Bool          last;\n} AxiStCc deriving (Bits, Eq);\n\ntypedef struct {\n   Bit #(256)     data;\n   Bool          last;\n   Bit #(8)      keep;\n   Bit #(4)      first_be;\n   Bit #(4)      last_be;\n} AxiStRq deriving (Bits, Eq);\n\ntypedef struct {\n   Bit #(256)     data;\n   Bool          sop;\n   Bool          eop;\n   Bit #(8)      keep;\n   Bit #(8)      be;\n} AxiStRc deriving (Bits, Eq);\n\nfunction TLPData#(16) convertCQDescriptorToTLP16(CQDescriptor desc, Bit#(32) data, TLPFirstDWBE first, TLPLastDWBE last);\n   TLPMemoryIO3DWHeader header = defaultValue;\n   header.format     = tpl_1(convertCQReqTypeToTLPFmtType(desc.reqtype));\n   header.pkttype    = tpl_2(convertCQReqTypeToTLPFmtType(desc.reqtype));\n   header.tclass     = desc.tclass;\n   header.relaxed    = desc.relaxed;\n   header.nosnoop    = desc.nosnoop;\n   header.length     = (desc.dwcount == 1024) ? 0 : truncate(desc.dwcount);\n   header.reqid      = desc.reqid;\n   header.tag        = desc.tag;\n   header.lastbe     = last;\n   header.firstbe    = first;\n   header.addr       = truncate(desc.address);\n   header.data       = convertDW(data);\n   \n   Bool is3DW = isReadReqType(desc.reqtype);\n   Bool is3Or4DW = isReadReqType(desc.reqtype) || (desc.dwcount == 1);\n\n   TLPData#(16) retval = defaultValue;\n   retval.sof   = True;\n   retval.eof   = is3Or4DW;\n   retval.hit   = (1 << pack(desc.barid));\n   retval.data  = pack(header);\n   retval.be    = (is3DW ? 16'hFFF0 : 16'hFFFF);\n   \n   return retval;\nendfunction\n\nfunction TLPData#(16) convertRCDescriptorToTLP16(RCDescriptor desc, Bit#(32) data);\n   TLPCompletionHeader header = defaultValue;\n   header.tclass    = desc.tclass;\n   header.relaxed   = desc.relaxed;\n   header.nosnoop   = desc.nosnoop;\n   header.cmplid    = desc.complid;\n   header.tag       = desc.tag;\n   header.reqid     = desc.reqid;\n   header.poison    = desc.poisoned;\n   header.cstatus   = desc.status;\n   header.length    = (desc.dwcount == 1024) ? 0 : truncate(desc.dwcount);\n   header.bytecount = (desc.bytecount == 4096) ? 0 : truncate(desc.bytecount);\n   header.loweraddr = truncate(desc.loweraddr);\n   header.data      = convertDW(data);\n\n   Bool is3DW = (desc.dwcount == 0);\n   Bool is3Or4DW = (desc.dwcount == 0) || (desc.dwcount == 1);\n   TLPData#(16) retval = defaultValue;\n   retval.sof   = True;\n   retval.eof   = is3Or4DW;\n   retval.hit   = 1; // XXX\n   retval.data  = pack(header);\n   retval.be    = (is3DW ? 16'hFFF0 : 16'hFFFF);\n   \n   return retval;\nendfunction\n\ntypedef struct {\n   Bit#(32) timestamp;\n   Bit#(8) src;\n   Bit#(24) value;\n} RegChange deriving (Bits);\n\ntypedef enum {\n   Pcie3Cfg_none,\n   Pcie3Cfg_current_speed,\n   Pcie3Cfg_dpa_substate_change,\n   Pcie3Cfg_err_cor_out,\n   Pcie3Cfg_err_fatal_out,\n   Pcie3Cfg_err_nonfatal_out,\n   Pcie3Cfg_flr_in_process,\n   Pcie3Cfg_function_power_state,\n   Pcie3Cfg_function_status,\n   Pcie3Cfg_hot_reset_out,\n   Pcie3Cfg_link_power_state,\n   Pcie3Cfg_ltr_enable,\n   Pcie3Cfg_ltssm_state,\n   Pcie3Cfg_max_payload,\n   Pcie3Cfg_max_read_req,\n   Pcie3Cfg_negotiated_width,\n   Pcie3Cfg_obff_enable,\n   Pcie3Cfg_phy_link_down,\n   Pcie3Cfg_phy_link_status,\n   Pcie3Cfg_pl_status_change,\n   Pcie3Cfg_power_state_change_interrupt,\n   Pcie3Cfg_rcb_status,\n   Pcie3Cfg_rq_backpressure\n   } Pcie3CfgType deriving (Bits,Eq);\n\n(* synthesize *)\nmodule mkPcieRootPortX7(PcieRootPortX7#(PcieLanes));\n\n   PCIEParams params = defaultValue;\n   Clock defaultClock <- exposeCurrentClock();\n   Reset defaultReset <- exposeCurrentReset();\n   Reset defaultResetInverted <- mkResetInverter(defaultReset, clocked_by defaultClock);\n   PcieRp#(PcieLanes) pcie_rp <- mkPcieRp(defaultClock, defaultResetInverted);\n\n   // The PCIe rootport exports full (250MHz) and half-speed (125MHz) clocks\n   Clock pcieClock250 = pcie_rp.user_clk;\n   Reset user_reset_n <- mkResetInverter(pcie_rp.user_reset, clocked_by pcie_rp.user_clk);\n   Reset pcieReset250 <- mkSyncReset(5, user_reset_n, pcieClock250);\n\n   ClockGenerator7Params     clkgenParams = defaultValue;\n   clkgenParams.clkin1_period    = 4.000; //  250MHz\n   clkgenParams.clkin1_period    = 4.000;\n   clkgenParams.clkin_buffer     = False;\n   clkgenParams.clkfbout_mult_f  = 4.000; // 1000MHz\n   clkgenParams.clkout0_divide_f = derivedClockPeriod;\n   clkgenParams.clkout1_divide     = round(mainClockPeriod);\n   clkgenParams.clkout1_duty_cycle = 0.5;\n   clkgenParams.clkout1_phase      = 0.0000;\n   ClockGenerator7           clkgen <- mkClockGenerator7(clkgenParams, clocked_by pcieClock250, reset_by pcieReset250);\n   Clock mainClock = clkgen.clkout1;\n   Reset mainReset <- mkSyncReset(5, pcieReset250, mainClock);\n   Clock derivedClock = clkgen.clkout0;\n   Reset derivedReset <- mkSyncReset(5, pcieReset250, derivedClock);\n   Reset user_reset <- mkSyncReset(5, pcie_rp.user_reset, pcie_rp.user_clk);\n\n   // FIFOS\n   FIFOF#(AxiStCq) fAxiCq <- mkFIFOF(clocked_by pcie_rp.user_clk, reset_by user_reset_n);\n   FIFOF#(AxiStRc) fAxiRc <- mkCFFIFOF(clocked_by pcie_rp.user_clk, reset_by user_reset_n);\n\n   FIFOF#(AxiStRq) fAxiRq <- mkCFFIFOF(clocked_by pcie_rp.user_clk, reset_by user_reset_n);\n   FIFOF#(AxiStCc) fAxiCc <- mkFIFOF(clocked_by pcie_rp.user_clk, reset_by user_reset_n);\n\n   FIFOF#(TLPData#(16)) fcq <- mkFIFOF(clocked_by pcie_rp.user_clk, reset_by user_reset_n);\n   FIFOF#(TLPData#(16)) frc <- mkFIFOF(clocked_by pcie_rp.user_clk, reset_by user_reset_n);\n   FIFOF#(TLPData#(16)) fcc <- mkFIFOF(clocked_by pcie_rp.user_clk, reset_by user_reset_n);\n   FIFOF#(TLPData#(16)) frq <- mkFIFOF(clocked_by pcie_rp.user_clk, reset_by user_reset_n);\n\n   FIFOF#(Tuple2#(Bit#(64),Bit#(32))) intrFifo <- mkFIFOF(clocked_by pcie_rp.user_clk, reset_by user_reset_n);\n\n   // Drive s_axis_rq\n   let rq_txready = (pcie_rp.s_axis_rq.tready != 0 && fAxiRq.notEmpty);\n\n   //(* fire_when_enabled, no_implicit_conditions *)\n   rule drive_axi_rq if (rq_txready);\n      let info = fAxiRq.first; fAxiRq.deq;\n      pcie_rp.s_axis_rq.tvalid(1);\n      pcie_rp.s_axis_rq.tlast(pack(info.last));\n      pcie_rp.s_axis_rq.tdata(info.data);\n      pcie_rp.s_axis_rq.tkeep(info.keep);\n      pcie_rp.s_axis_rq.tuser({0, info.last_be, info.first_be});\n   endrule\n\n   (* fire_when_enabled, no_implicit_conditions *)\n   rule drive_axi_rq2 if (!rq_txready);\n      pcie_rp.s_axis_rq.tvalid(0);\n      pcie_rp.s_axis_rq.tlast(0);\n      pcie_rp.s_axis_rq.tdata(0);\n      pcie_rp.s_axis_rq.tkeep(0);\n      pcie_rp.s_axis_rq.tuser(0);\n   endrule\n\n   Reg#(Bit#(16)) rqBackpressureCycles <- mkReg(0, clocked_by pcie_rp.user_clk, reset_by user_reset_n);\n   Reg#(Bit#(16)) rqBackpressureCount <- mkReg(0, clocked_by pcie_rp.user_clk, reset_by user_reset_n);\n   Reg#(Bool)     rqBackpressure       <- mkReg(False, clocked_by pcie_rp.user_clk, reset_by user_reset_n);\n   Reg#(Bit#(32)) rqBackpressureCountSum <- mkReg(0, clocked_by pcie_rp.user_clk, reset_by user_reset_n);\n   Reg#(Bit#(32)) rqBackpressureEvents   <- mkReg(0, clocked_by pcie_rp.user_clk, reset_by user_reset_n);\n   let probe_rqBackpressureCycles <- mkProbe(clocked_by pcie_rp.user_clk, reset_by user_reset_n);\n   let probe_rqBackpressureCount <- mkProbe(clocked_by pcie_rp.user_clk, reset_by user_reset_n);\n   let probe_rqBackpressure       <- mkProbe(clocked_by pcie_rp.user_clk, reset_by user_reset_n);\n   Probe#(Bit#(32)) probe_rqBackpressureCountSum <- mkProbe(clocked_by pcie_rp.user_clk, reset_by user_reset_n);\n   Probe#(Bit#(32)) probe_rqBackpressureEvents   <- mkProbe(clocked_by pcie_rp.user_clk, reset_by user_reset_n);\n   let probe_fAxiRqNotEmpty       <- mkProbe(clocked_by pcie_rp.user_clk, reset_by user_reset_n);\n   let probe_SAxsiRqTReady        <- mkProbe(clocked_by pcie_rp.user_clk, reset_by user_reset_n);\n   rule rltready;\n      probe_fAxiRqNotEmpty <= fAxiRq.notEmpty();\n      probe_SAxsiRqTReady <= pcie_rp.s_axis_rq.tready;\n   endrule\n   rule rlBackpressureEnter if (!rqBackpressure);\n      if (pcie_rp.s_axis_rq.tready == 0 && fAxiRq.notEmpty) begin\n\t rqBackpressure <= True;\n\t rqBackpressureCycles <= 0;\n\t probe_rqBackpressure <= True;\n\t probe_rqBackpressureCycles <= 0;\n      end\n   endrule\n   rule rlBackpressureExit if (rqBackpressure);\n      rqBackpressureCycles <= rqBackpressureCycles + 1;\n      probe_rqBackpressureCycles <= rqBackpressureCycles + 1;\n      if (pcie_rp.s_axis_rq.tready != 0 || !fAxiRq.notEmpty) begin\n\t rqBackpressure <= False;\n\t let count = rqBackpressureCycles;\n\t count[15] = ~rqBackpressureCount[15];\n\t if (count > 5)\n\t    rqBackpressureCount <= count;\n\t rqBackpressureCountSum <= rqBackpressureCountSum + extend(count);\n\t rqBackpressureEvents <= rqBackpressureEvents + 1;\n\t probe_rqBackpressure <= False;\n\t probe_rqBackpressureCount <= count;\n\t probe_rqBackpressureCountSum <= rqBackpressureCountSum + extend(count);\n\t probe_rqBackpressureEvents <= rqBackpressureEvents + 1;\n      end\n      else begin\n\t probe_rqBackpressure <= True;\n      end\n   endrule\n\n   // Drive s_axis_cc\n   let cc_txready = (pcie_rp.s_axis_cc.tready != 0 && fAxiCc.notEmpty);\n\n   //(* fire_when_enabled, no_implicit_conditions *)\n   rule drive_axi_cc if (cc_txready);\n      let info = fAxiCc.first; fAxiCc.deq;\n      $display(\"drive axi_cc, data: %h, keep: %h, last: %h\", info.data, info.keep, info.last);\n      pcie_rp.s_axis_cc.tvalid(1);\n      pcie_rp.s_axis_cc.tlast(pack(info.last));\n      pcie_rp.s_axis_cc.tdata(info.data);\n      pcie_rp.s_axis_cc.tkeep(info.keep);\n      pcie_rp.s_axis_cc.tuser(0);\n   endrule\n\n   (* fire_when_enabled, no_implicit_conditions *)\n   rule drive_axi_cc2 if (!cc_txready);\n      pcie_rp.s_axis_cc.tvalid(0);\n      pcie_rp.s_axis_cc.tlast(0);\n      pcie_rp.s_axis_cc.tdata(0);\n      pcie_rp.s_axis_cc.tkeep(0);\n      pcie_rp.s_axis_cc.tuser(0);\n   endrule\n\n   (* fire_when_enabled, no_implicit_conditions *)\n   rule drive_axi_rc_ready;\n      pcie_rp.m_axis_rc.tready (duplicate (pack (fAxiRc.notFull)));\n   endrule\n \n   // Drive m_axis_rc\n   (* fire_when_enabled *)\n   rule sink_axi_rc if (pcie_rp.m_axis_rc.tvalid != 0 && fAxiRc.notFull);\n      let rc = AxiStRc {data:pcie_rp.m_axis_rc.tdata,\n\t\t\tsop: unpack (pcie_rp.m_axis_rc.tuser [32]),         // tuser.is_sof_0\n\t\t\teop: unpack (pcie_rp.m_axis_rc.tlast),\n\t\t\tkeep:pcie_rp.m_axis_rc.tkeep,\n\t\t\tbe:  truncate (pcie_rp.m_axis_rc.tuser [31:0])};    // tuser.byte_en\n      fAxiRc.enq (rc);\n   endrule\n\n   (* fire_when_enabled, no_implicit_conditions *)\n   rule drive_axi_cq_ready;\n      pcie_rp.m_axis_cq.tready (duplicate (pack (fAxiCq.notFull)));\n   endrule\n\n   (* fire_when_enabled *)\n   rule sink_axi_cq if (pcie_rp.m_axis_cq.tvalid != 0 && fAxiCq.notFull);\n      let cq = AxiStCq {data:     pcie_rp.m_axis_cq.tdata,\n\t\t\tsop:      unpack (pcie_rp.m_axis_cq.tuser [40]),  // tuser.sop\n\t\t\teop:      unpack (pcie_rp.m_axis_cq.tlast),\n\t\t\tkeep:     pcie_rp.m_axis_cq.tkeep,\n\t\t\tfirst_be: pcie_rp.m_axis_cq.tuser [3:0],    // tuser.first_be,\n\t\t\tlast_be:  pcie_rp.m_axis_cq.tuser [7:4]};   // tuser.last_be\n      fAxiCq.enq (cq);\n   endrule\n\n   // CQ.\n   CQDescriptor cq_desc = unpack(fAxiCq.first.data [127:0]);\n\n   rule rl_cq_wr_header (fAxiCq.first.sop && ((cq_desc.reqtype == MEMORY_WRITE) || (cq_desc.reqtype == IO_WRITE)));\n      Bit#(32) data = fAxiCq.first.data[159:128];\n      // get data;\n      TLPData#(16) tlp16 = convertCQDescriptorToTLP16(cq_desc, data, fAxiCq.first.first_be, fAxiCq.first.last_be);\n      $display(\"cq_desc.reqtype=%h\", cq_desc.reqtype);\n      // enqueue?\n      fcq.enq(tlp16);\n      fAxiCq.deq;\n   endrule\n\n   // Write data payload, no data remaining\n   rule rl_cq_wr_payload((!fAxiCq.first.sop));\n      fAxiCq.deq;\n   endrule\n\n   // Write data payload, 1 to 3 DWs remaining\n   // Write data payload, 4 or more DWs remaining\n\n   rule rl_cq_rd_header (fAxiCq.first.sop && ((cq_desc.reqtype == MEMORY_READ) || (cq_desc.reqtype == IO_READ)));\n      Bit#(32) data = 0;\n      TLPData#(16) tlp16 = convertCQDescriptorToTLP16(cq_desc, data, fAxiCq.first.first_be, fAxiCq.first.last_be);\n      $display(\"rl_cq_rd_header: cq_desc = %16x\", cq_desc);\n      fcq.enq(tlp16);\n      fAxiCq.deq;\n   endrule\n\n   // RC.\n   Reg#(DWCount) rc_dwcount <- mkRegU(clocked_by pcie_rp.user_clk, reset_by user_reset_n);\n   Reg#(Bool) rc_even <- mkReg(True, clocked_by pcie_rp.user_clk, reset_by user_reset_n);\n\n   rule rl_rc_header (fAxiRc.first.sop && rc_even);\n      RCDescriptor rc_desc = unpack(fAxiRc.first.data [95:0]);\n      // RC descriptor always 96 bytes with first data word in bits 127:96                                                                                            \n      Bit#(32) data = byteSwap(fAxiRc.first.data[127:96]);\n      TLPData#(16) tlp16 = convertRCDescriptorToTLP16(rc_desc, data);\n      rc_dwcount <= (rc_desc.dwcount == 0) ? 0 : rc_desc.dwcount - 1;\n      frc.enq(tlp16);\n      let even = False;\n      if (rc_desc.dwcount == 0 || rc_desc.dwcount == 1) begin\n        fAxiRc.deq;\n        even = True;\n      end\n      rc_even <= even;\n   endrule\n\n   rule rl_rc_data ((!rc_even || !(fAxiRc.first.sop)) && (rc_dwcount != 0));\n      Bit#(16) be16;\n      case (rc_dwcount)\n         1: be16 = 16'hF000;\n         2: be16 = 16'hFF00;\n         3: be16 = 16'hFFF0;\n         default: be16 = 16'hFFFF;\n      endcase\n      let last = (rc_dwcount <= 4);\n      let dwcount = rc_dwcount - 4;\n      if (last) dwcount = 0;\n      let data = (rc_even) ? fAxiRc.first.data[127:0]: fAxiRc.first.data[255:128];\n      TLPData#(16) tlp16 = TLPData{sof: False,\n                                   eof: last,\n                                   hit: 0,\n                                   be: be16,\n                                   data: pack(data)};\n      frc.enq(tlp16);\n      if (last || !rc_even) begin\n         fAxiRc.deq;\n      end\n      rc_dwcount <= dwcount;\n      rc_even <= (last) ? True : !rc_even;\n   endrule\n\n   Reg#(DWCount) cc_dwcount <- mkReg(0, clocked_by pcie_rp.user_clk, reset_by user_reset_n);\n   FIFOF#(TLPData#(16)) fcc_tlps <- mkFIFOF (clocked_by pcie_rp.user_clk, reset_by user_reset_n);\n   // CC.\n   rule get_cc_tlps;\n      let tlp <- toGet(fcc).get;\n      fcc_tlps.enq(tlp);\n   endrule\n\n   rule rl_cc_header(fcc_tlps.first.sof);\n      match { .cc_desc, .dw} = convertTLP16ToCCDescriptor(fcc_tlps.first);\n      cc_dwcount <= cc_desc.dwcount - 1;\n      fAxiCc.enq(AxiStCc {data: zeroExtend({dw, pack(cc_desc)[95:0]}),\n                       last: fcc_tlps.first.eof,\n                       keep: 8'h0F});\n      fcc_tlps.deq;\n   endrule\n\n   rule rl_cc_data((!fcc_tlps.first.sof) && (cc_dwcount != 0));\n      Bit#(256) x = zeroExtend(fcc_tlps.first.data); //FIXME\n      fAxiCc.enq(AxiStCc {data: {x},\n                       last: cc_dwcount <= 4,\n                       keep: (cc_dwcount == 3) ? 8'h0F : 8'hFF});\n      fcc_tlps.deq;\n   endrule\n\n   // RQ.\n   FIFOF#(TLPData#(16)) frq_tlps <- mkFIFOF (clocked_by pcie_rp.user_clk, reset_by user_reset_n);\n   Reg#(Bit#(4)) rq_first_be <- mkReg(0, clocked_by pcie_rp.user_clk, reset_by user_reset_n);\n   Reg#(Bit#(4)) rq_last_be <- mkReg(0, clocked_by pcie_rp.user_clk, reset_by user_reset_n);\n   Reg#(Bool)    rq_even    <- mkRegU(clocked_by pcie_rp.user_clk, reset_by user_reset_n);\n   Reg#(DWCount) rq_dwcount <- mkReg(0, clocked_by pcie_rp.user_clk, reset_by user_reset_n);\n   Reg#(AxiStRq) rq_rq <- mkRegU(clocked_by pcie_rp.user_clk, reset_by user_reset_n);\n   rule rl_rq_tlps;\n      let tlp <- toGet(frq).get;\n      frq_tlps.enq(tlp);\n   endrule\n\n   rule rl_rq_header if (frq_tlps.first.sof);\n      TLPData#(16) tlp <- toGet(frq_tlps).get();\n      match { .rq_desc, .first_be, .last_be, .mdata} = convertTLP16ToRQDescriptor(tlp);\n\n      let dwcount = ((rq_desc.reqtype == MEMORY_WRITE) ? rq_desc.dwcount : 0);\n      rq_dwcount <= dwcount;\n      rq_even <= False;\n      rq_first_be <= first_be;\n      rq_last_be <= last_be;\n      let last = (rq_desc.reqtype == MEMORY_WRITE) ? (dwcount <= 4) : True;\n      let rq = AxiStRq {data: zeroExtend(pack(rq_desc)), //FIXME:\n\t\t\tlast: last,\n\t\t\tkeep: 8'h0F,\n\t\t\tfirst_be: first_be,\n\t\t\tlast_be: last_be};\n      if (rq_desc.reqtype == MEMORY_WRITE)\n\t rq_rq <= rq;\n      else\n\t fAxiRq.enq(rq);\n   endrule\n\n   // more data\n   rule rl_rq_data if (rq_dwcount != 0);\n      TLPData#(16) tlp <- toGet(frq_tlps).get();\n      let rq = rq_rq;\n      let last = (rq_dwcount <= 4);\n      let dwcount = rq_dwcount - 4;\n      Bit#(8) keep;\n      if (last)\n\tdwcount = 0;\n      if (rq_even) begin\n\t rq.data[127:0] = tlp.data;\n\tcase (rq_dwcount)\n\t   1: keep = 8'h01;\n\t   2: keep = 8'h03;\n\t   3: keep = 8'h07;\n\t   default: keep = 8'h0f;\n\tendcase\n      end\n      else begin\n\trq.data[255:128] = tlp.data;\n\tcase (rq_dwcount)\n\t   1: keep = 8'h1f;\n\t   2: keep = 8'h3f;\n\t   3: keep = 8'h7f;\n\t   default: keep = 8'hff;\n\tendcase\n      end\n      rq.last = last;\n      rq.first_be = rq_first_be;\n      rq.last_be = rq_last_be;\n      rq.keep = keep;\n      if (!rq_even || last)\n\t fAxiRq.enq(rq);\n      if (rq_even)\n\trq_rq <= rq;\n      rq_dwcount <= dwcount;\n      rq_even <= (last) ? False : !rq_even;\n   endrule\n\n   FIFO#(Bool) intrMutex <- mkFIFO1(clocked_by pcie_rp.user_clk, reset_by user_reset_n);\n\n   let probe_current_speed <- mkProbe(clocked_by pcie_rp.user_clk, reset_by user_reset_n);\n   let probe_dpa_substate_change <- mkProbe(clocked_by pcie_rp.user_clk, reset_by user_reset_n);\n   let probe_err_cor_out <- mkProbe(clocked_by pcie_rp.user_clk, reset_by user_reset_n);\n   let probe_err_fatal_out <- mkProbe(clocked_by pcie_rp.user_clk, reset_by user_reset_n);\n   let probe_err_nonfatal_out <- mkProbe(clocked_by pcie_rp.user_clk, reset_by user_reset_n);\n   let probe_flr_in_process <- mkProbe(clocked_by pcie_rp.user_clk, reset_by user_reset_n);\n   let probe_function_power_state <- mkProbe(clocked_by pcie_rp.user_clk, reset_by user_reset_n);\n   let probe_function_status <- mkProbe(clocked_by pcie_rp.user_clk, reset_by user_reset_n);\n   let probe_hot_reset_out <- mkProbe(clocked_by pcie_rp.user_clk, reset_by user_reset_n);\n   let probe_link_power_state <- mkProbe(clocked_by pcie_rp.user_clk, reset_by user_reset_n);\n   let probe_ltr_enable <- mkProbe(clocked_by pcie_rp.user_clk, reset_by user_reset_n);\n   let probe_ltssm_state <- mkProbe(clocked_by pcie_rp.user_clk, reset_by user_reset_n);\n   let probe_max_payload <- mkProbe(clocked_by pcie_rp.user_clk, reset_by user_reset_n);\n   let probe_max_read_req <- mkProbe(clocked_by pcie_rp.user_clk, reset_by user_reset_n);\n   let probe_negotiated_width <- mkProbe(clocked_by pcie_rp.user_clk, reset_by user_reset_n);\n   let probe_obff_enable <- mkProbe(clocked_by pcie_rp.user_clk, reset_by user_reset_n);\n   let probe_phy_link_down <- mkProbe(clocked_by pcie_rp.user_clk, reset_by user_reset_n);\n   let probe_phy_link_status <- mkProbe(clocked_by pcie_rp.user_clk, reset_by user_reset_n);\n   let probe_pl_status_change <- mkProbe(clocked_by pcie_rp.user_clk, reset_by user_reset_n);\n   let probe_power_state_change_interrupt <- mkProbe(clocked_by pcie_rp.user_clk, reset_by user_reset_n);\n   let probe_rcb_status <- mkProbe(clocked_by pcie_rp.user_clk, reset_by user_reset_n);\n   let probe_tph_requester_enable <- mkProbe(clocked_by pcie_rp.user_clk, reset_by user_reset_n);\n   let probe_tph_st_mode <- mkProbe(clocked_by pcie_rp.user_clk, reset_by user_reset_n);\n   let probe_rq_seq_num <- mkProbe(clocked_by pcie_rp.user_clk, reset_by user_reset_n);\n   let probe_rq_seq_num_vld <- mkProbe(clocked_by pcie_rp.user_clk, reset_by user_reset_n);\n   rule rl_drive_probes;\n      probe_current_speed <= pcie_rp.cfg.current_speed;\n      probe_dpa_substate_change <= pcie_rp.cfg.dpa_substate_change;\n      probe_err_cor_out <= pcie_rp.cfg.err_cor_out;\n      probe_err_fatal_out <= pcie_rp.cfg.err_fatal_out;\n      probe_err_nonfatal_out <= pcie_rp.cfg.err_nonfatal_out;\n      probe_flr_in_process <= pcie_rp.cfg.flr_in_process;\n      probe_function_power_state <= pcie_rp.cfg.function_power_state;\n      probe_function_status <= pcie_rp.cfg.function_status;\n      probe_hot_reset_out <= pcie_rp.cfg.hot_reset_out;\n      probe_link_power_state <= pcie_rp.cfg.link_power_state;\n      probe_ltr_enable <= pcie_rp.cfg.ltr_enable;\n      probe_ltssm_state <= pcie_rp.cfg.ltssm_state;\n      probe_max_payload <= pcie_rp.cfg.max_payload;\n      probe_max_read_req <= pcie_rp.cfg.max_read_req;\n      probe_negotiated_width <= pcie_rp.cfg.negotiated_width;\n      probe_obff_enable <= pcie_rp.cfg.obff_enable;\n      probe_phy_link_down <= pcie_rp.cfg.phy_link_down;\n      probe_phy_link_status <= pcie_rp.cfg.phy_link_status;\n      probe_pl_status_change <= pcie_rp.cfg.pl_status_change;\n      probe_power_state_change_interrupt <= pcie_rp.cfg.power_state_change_interrupt;\n      probe_rcb_status <= pcie_rp.cfg.rcb_status;\n      probe_tph_requester_enable <= pcie_rp.cfg.tph_requester_enable;\n      probe_tph_st_mode <= pcie_rp.cfg.tph_st_mode;\n\n      probe_rq_seq_num <= pcie_rp.pcie.rq_seq_num;\n      probe_rq_seq_num_vld <= pcie_rp.pcie.rq_seq_num_vld;\n   endrule\n\n   Reg#(Bit#(32)) cyclesReg <- mkReg(0, clocked_by pcie_rp.user_clk, reset_by user_reset_n);\n   rule rl_cycles;\n      cyclesReg <= cyclesReg + 1;\n   endrule\n\n   module mkChangeSource#(Tuple2#(Pcie3CfgType,Bit#(24)) tpl)(PipeOut#(RegChange));\n      match { .src, .v } = tpl;\n      let snapshot <- mkReg(0);\n      let changeFifo <- mkFIFOF1();\n      let probe_snapshot <- mkProbe();\n      rule rl_update if (v != snapshot);\n\t if (changeFifo.notFull) begin\n\t    changeFifo.enq(RegChange { timestamp: cyclesReg, src: extend(pack(src)), value: extend(v) });\n\t    snapshot <= v;\n\t    probe_snapshot <= v;\n\t end\n      endrule\n      return toPipeOut(changeFifo);\n   endmodule\n\n`ifndef FOO\n   Vector#(22,Tuple2#(Pcie3CfgType,Bit#(24))) changeValues = vec(tuple2(Pcie3Cfg_current_speed, extend(pcie_rp.cfg.current_speed)),\n      tuple2(Pcie3Cfg_dpa_substate_change, extend(pcie_rp.cfg.dpa_substate_change)),\n      tuple2(Pcie3Cfg_err_cor_out, extend(pcie_rp.cfg.err_cor_out)),\n      tuple2(Pcie3Cfg_err_fatal_out, extend(pcie_rp.cfg.err_fatal_out)),\n      tuple2(Pcie3Cfg_err_nonfatal_out, extend(pcie_rp.cfg.err_nonfatal_out)),\n      tuple2(Pcie3Cfg_flr_in_process, extend(pcie_rp.cfg.flr_in_process)),\n      tuple2(Pcie3Cfg_function_power_state, extend(pcie_rp.cfg.function_power_state)),\n      tuple2(Pcie3Cfg_function_status, extend(pcie_rp.cfg.function_status)),\n      tuple2(Pcie3Cfg_hot_reset_out, extend(pcie_rp.cfg.hot_reset_out)),\n      tuple2(Pcie3Cfg_link_power_state, extend(pcie_rp.cfg.link_power_state)),\n      tuple2(Pcie3Cfg_ltr_enable, extend(pcie_rp.cfg.ltr_enable)),\n      tuple2(Pcie3Cfg_ltssm_state, extend(pcie_rp.cfg.ltssm_state)),\n      tuple2(Pcie3Cfg_max_payload, extend(pcie_rp.cfg.max_payload)),\n      tuple2(Pcie3Cfg_max_read_req, extend(pcie_rp.cfg.max_read_req)),\n      tuple2(Pcie3Cfg_negotiated_width, extend(pcie_rp.cfg.negotiated_width)),\n      tuple2(Pcie3Cfg_obff_enable, extend(pcie_rp.cfg.obff_enable)),\n      tuple2(Pcie3Cfg_phy_link_down, extend(pcie_rp.cfg.phy_link_down)),\n      tuple2(Pcie3Cfg_phy_link_status, extend(pcie_rp.cfg.phy_link_status)),\n      tuple2(Pcie3Cfg_pl_status_change, extend(pcie_rp.cfg.pl_status_change)),\n      tuple2(Pcie3Cfg_power_state_change_interrupt, extend(pcie_rp.cfg.power_state_change_interrupt)),\n      tuple2(Pcie3Cfg_rcb_status, extend(pcie_rp.cfg.rcb_status)),\n      tuple2(Pcie3Cfg_rq_backpressure, extend(rqBackpressureCount)));\n   let change_pipes <- mapM(mkChangeSource, changeValues, clocked_by pcie_rp.user_clk, reset_by user_reset_n);\n\n   FunnelPipe#(1,22,RegChange,3) changePipe <- mkFunnelPipesPipelined(change_pipes, clocked_by pcie_rp.user_clk, reset_by user_reset_n);\n   FIFOF#(RegChange) changeFifo <- mkSizedBRAMFIFOF(128, clocked_by pcie_rp.user_clk, reset_by user_reset_n);\n   mkConnection(changePipe[0], toPipeIn(changeFifo), clocked_by pcie_rp.user_clk, reset_by user_reset_n);\n`else\n   let cs <- mkChangeSource(tuple2(Pcie3Cfg_rq_backpressure, extend(rqBackpressureCount)), clocked_by pcie_rp.user_clk, reset_by user_reset_n);\n   FIFOF#(RegChange) changeFifo <- mkSizedBRAMFIFOF(128, clocked_by pcie_rp.user_clk, reset_by user_reset_n);\n   mkConnection(cs, toPipeIn(changeFifo), clocked_by pcie_rp.user_clk, reset_by user_reset_n);\n`endif\n\n   rule rl_drive_cfg_status_if;\n      pcie_rp.cfg.config_space_enable(1);\n      pcie_rp.cfg.dsn(64'hf001ba7700000000);\n      pcie_rp.cfg.ds_bus_number(0);\n      pcie_rp.cfg.ds_device_number(0);\n      pcie_rp.cfg.ds_port_number(0);\n      pcie_rp.cfg.err_cor_in(0);\n      pcie_rp.cfg.err_uncor_in(0);\n      pcie_rp.cfg.flr_done(0);\n      pcie_rp.cfg.hot_reset_in(0);\n      pcie_rp.cfg.link_training_enable(1);\n      pcie_rp.cfg.per_function_number(0);\n      pcie_rp.cfg.per_function_output_request(0);\n      pcie_rp.cfg.power_state_change_ack(0);\n      pcie_rp.cfg.subsys_vend_id(16'h1be8);\n      pcie_rp.cfg.vf_flr_done(0);\n\n      pcie_rp.pcie.cq_np_req(1);\n\n      pcie_rp.cfg_req_pm_transition.l23_ready(0);\n   endrule\n\n   // The PCIE rootport is processing Gen3 descriptors at 250MHz. The\n   // AXI bridge is accepting TLPData#(16)s at 250 MHz. The\n   // conversion uses half of Gen3 descriptor.\n   //mkConnection(tlp8, gb.tlp, clocked_by portalClock, reset_by portalReset);\n\n   let portalClock = (mainClockPeriod == pcieClockPeriod) ? pcieClock250 : mainClock;\n   let portalReset = (mainClockPeriod == pcieClockPeriod) ? pcieReset250 : mainReset;\n\n   interface Server tlpr;\n      interface request = toPut(frq);\n      interface response = toGet(frc);\n   endinterface\n   // Requests from other PCIe devices\n   interface Server tlpc;\n      interface request = toPut(fcc);\n      interface response = toGet(fcq);\n   endinterface\n   interface interruptRequest = toPut(intrFifo);\n   interface pcie    = pcie_rp.pci_exp;\n   interface Pcie3wrapUser user = pcie_rp.user;\n   interface PcieRpPipe pipe = pcie_rp.pipe;\n   interface PcieRpCommon common= pcie_rp.common;\n   interface regChanges = mapPipe(pack, toPipeOut(changeFifo));\n   interface Clock epPcieClock = pcieClock250;\n   interface Reset epPcieReset = pcieReset250;\n   interface Clock epPortalClock = portalClock;\n   interface Reset epPortalReset = portalReset;\n   interface Clock epDerivedClock = derivedClock;\n   interface Reset epDerivedReset = derivedReset;\nendmodule: mkPcieRootPortX7\n\nendpackage: Pcie3RootPortX7\n"
  },
  {
    "path": "bsv/PcieCsr.bsv",
    "content": "// Copyright (c) 2014 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\nimport Vector         :: *;\nimport BRAM           :: *;\nimport FIFOF          :: *;\nimport BRAMFIFO       :: *;\nimport GetPut         :: *;\nimport Connectable    :: *;\nimport PCIE           :: *;\nimport Clocks         :: *;\nimport PcieTracer     :: *;\nimport ConnectalMemTypes       :: *;\nimport AddressGenerator::*;\nimport Pipe           :: *;\n\n`include \"ConnectalProjectConfig.bsv\"\n\n// starting word of MSIX config registers\n`define msix_base 1024\n\n// An MSIX table entry, as defined in the PCIe spec\ninterface MSIX_Entry;\n   interface Reg#(Bit#(32)) addr_lo;\n   interface Reg#(Bit#(32)) addr_hi;\n   interface Reg#(Bit#(32)) msg_data;\n   interface Reg#(Bool)     masked;\nendinterface\n\ninterface ReadOnly_MSIX_Entry;\n   interface ReadOnly#(Bit#(32)) addr_lo;\n   interface ReadOnly#(Bit#(32)) addr_hi;\n   interface ReadOnly#(Bit#(32)) msg_data;\n   interface ReadOnly#(Bool)     masked;\nendinterface\n\nfunction ReadOnly_MSIX_Entry toReadOnlyMsixEntry(MSIX_Entry msix);\n   return (interface ReadOnly_MSIX_Entry;\n\t   interface ReadOnly addr_lo = regToReadOnly(msix.addr_lo);\n\t   interface ReadOnly addr_hi = regToReadOnly(msix.addr_hi);\n\t   interface ReadOnly msg_data = regToReadOnly(msix.msg_data);\n\t   interface ReadOnly masked = regToReadOnly(msix.masked);\n\t   endinterface);\nendfunction\n\n// control and status registers accessed from PCIe\ninterface PcieControlAndStatusRegs;\n   interface PhysMemSlave#(32,32) memSlave;\n   interface Vector#(16,ReadOnly_MSIX_Entry) msixEntry;\n   interface PipeIn#(Bit#(64)) changes;\n   interface TlpTraceClient traceClient;\nendinterface: PcieControlAndStatusRegs\n\n// This module encapsulates all of the logic for instantiating and\n// accessing the control and status registers. It defines the\n// registers, the address map, and how the registers respond to reads\n// and writes.\n(* synthesize *)\nmodule mkPcieControlAndStatusRegs(PcieControlAndStatusRegs);\n\n   // Utility for module creating all of the storage for a single MSIX\n   // table entry\n   module mkMSIXEntry(MSIX_Entry);\n      Reg#(Bit#(32)) _addr_lo  <- mkReg(0);\n      Reg#(Bit#(32)) _addr_hi  <- mkReg(0);\n      Reg#(Bit#(32)) _msg_data <- mkReg(0);\n      Reg#(Bool)     _masked   <- mkReg(True);\n\n      interface addr_lo  = _addr_lo;\n      interface addr_hi  = _addr_hi;\n      interface msg_data = _msg_data;\n      interface masked   = _masked;\n   endmodule: mkMSIXEntry\n\n   // Registers and their default values\n   Vector#(16,MSIX_Entry) msix_entry              <- replicateM(mkMSIXEntry);\n   Reg#(TimestampedTlpData) pcieTraceBramResponse <- mkReg(unpack(0));\n\n   // Function to return a one-word slice of the tlpTraceBramResponse\n   function Bit#(32) tlpTraceBramResponseSlice(Reg#(TimestampedTlpData) data, Integer i);\n       Bit#(8) i8 = fromInteger(i);\n       begin\n           Bit#(TMul#(12,32)) v = extend(pack(data));\n           return v[31 + (i8*32) : 0 + (i8*32)];\n       end\n   endfunction\n\n   FIFOF#(BRAMRequest#(Bit#(TAdd#(TlpTraceAddrSize,1)),TimestampedTlpData)) bramRequestFifo <- mkFIFOF();\n   FIFOF#(TimestampedTlpData)                                               bramResponseFifo <- mkFIFOF();\n   Reg#(Bool)                   tlpTracingReg                <- mkReg(True);\n   Reg#(Bit#(TlpTraceAddrSize)) tlpTraceLimitReg             <- mkReg(0);\n   Reg#(Bit#(TlpTraceAddrSize)) tlpTraceBramWrAddrReg        <- mkReg(0);\n   FIFOF#(Bit#(64))             changeFifo                   <- mkSizedBRAMFIFOF(256);\n\n   // State used to actually service read and write requests\n   rule brmMuxResponse;\n       let v <- toGet(bramResponseFifo).get();\n       pcieTraceBramResponse <= v;\n   endrule\n\n   AddressGenerator#(16,32)           csrRag <- mkAddressGenerator;\n   AddressGenerator#(16,32)           csrWag <- mkAddressGenerator;\n   FIFOF#(MemData#(32))     readResponseFifo <- mkFIFOF();\n   FIFOF#(MemData#(32))        writeDataFifo <- mkFIFOF();\n   FIFOF#(Bit#(MemTagSize)) writeDoneFifo <- mkFIFOF();\n\n   FIFOF#(AddrBeat#(16)) csrRagBeatFifo <- mkFIFOF();\n   FIFOF#(Bool)       csrIsMsixAddrFifo <- mkFIFOF();\n   FIFOF#(Bit#(2))     csrOneHotFifo000 <- mkFIFOF();\n   FIFOF#(Bit#(29))    csrOneHotFifo774 <- mkFIFOF();\n   FIFOF#(Bit#(2))     csrOneHotFifo992 <- mkFIFOF();\n\n   FIFOF#(AddrBeat#(16)) csrWagBeatFifo <- mkFIFOF();\n   FIFOF#(Bool)       csrWagIsMsixAddrFifo <- mkFIFOF();\n   FIFOF#(Bit#(8))     csrWagOneHotFifo768 <- mkFIFOF();\n   FIFOF#(Bit#(3))     csrWagOneHotFifo792 <- mkFIFOF();\n\n   rule readDataRule;\n      let beat <- csrRag.addrBeat.get();\n      let addr = beat.addr >> 2; // word address\n      Bit#(32) data = 0;\n      let modaddr = (addr % 8192);\n      let msixaddr = modaddr - `msix_base;\n\n      csrRagBeatFifo.enq(beat);\n      csrIsMsixAddrFifo.enq(msixaddr >= 0 && msixaddr <= 63);\n      Bit#(1024) onehot = (1 << addr[9:0]);\n      csrOneHotFifo000.enq(onehot[1:0]);\n      csrOneHotFifo774.enq(onehot[802:774]);\n      csrOneHotFifo992.enq(onehot[993:992]);\n   endrule\n   rule readDataRule2;\n      let beat       <- toGet(csrRagBeatFifo).get();\n      let isMsixAddr <- toGet(csrIsMsixAddrFifo).get();\n      let addr = beat.addr >> 2; // word address\n      Bit#(32) data = 32'hbad0add0;\n      let modaddr = (addr % 8192);\n      let msix_base = `msix_base;\n      let msixaddr = modaddr - msix_base;\n      let oneHotDecode000 <- toGet(csrOneHotFifo000).get();\n      let oneHotDecode774 <- toGet(csrOneHotFifo774).get();\n      let oneHotDecode992 <- toGet(csrOneHotFifo992).get();\n\n      if (isMsixAddr) begin\n         begin\n            let groupaddr = (msixaddr / 4);\n            //******************************** msix_base has to match CONFIG.MXIx_Table_Offset in scripts/connectal-synth-pcie.tcl\n            case (msixaddr % 4)\n               0: data = msix_entry[groupaddr].addr_lo;\n               1: data = msix_entry[groupaddr].addr_hi;\n               2: data = msix_entry[groupaddr].msg_data;\n               3: data = {'0, pack(msix_entry[groupaddr].masked)}; // vector control\n               default: data = 32'hbad0add0;\n\t  //******************************** end of MSIX Table\n            endcase\n         end\n      end\n      else begin\n\t  // board identification\n\t  if (oneHotDecode000[0] == 1) data = 32'h65756c42; // Blue\n\t  if (oneHotDecode000[1] == 1) data = 32'h63657073; // spec\n\n\t  if (oneHotDecode774[774-774] == 1) data = fromInteger(2**valueOf(TAdd#(TlpTraceAddrSize,1)));\n\t  if (oneHotDecode774[775-774] == 1) data = (tlpTracingReg ? 1 : 0);\n\t  if (oneHotDecode774[776-774] == 1) data = tlpTraceBramResponseSlice(pcieTraceBramResponse, 0);\n\t  if (oneHotDecode774[777-774] == 1) data = tlpTraceBramResponseSlice(pcieTraceBramResponse, 1);\n\t  if (oneHotDecode774[778-774] == 1) data = tlpTraceBramResponseSlice(pcieTraceBramResponse, 2);\n\t  if (oneHotDecode774[779-774] == 1) data = tlpTraceBramResponseSlice(pcieTraceBramResponse, 3);\n\t  if (oneHotDecode774[780-774] == 1) data = tlpTraceBramResponseSlice(pcieTraceBramResponse, 4);\n\t  if (oneHotDecode774[781-774] == 1) data = tlpTraceBramResponseSlice(pcieTraceBramResponse, 5);\n\t  if (oneHotDecode774[792-774] == 1) data = extend(tlpTraceBramWrAddrReg);\n\t  if (oneHotDecode774[794-774] == 1) data = extend(tlpTraceLimitReg);\n\t  if (oneHotDecode774[795-774] == 1) data = tlpTraceBramResponseSlice(pcieTraceBramResponse, 6);\n\t  if (oneHotDecode774[796-774] == 1) data = tlpTraceBramResponseSlice(pcieTraceBramResponse, 7);\n\t  if (oneHotDecode774[797-774] == 1) data = tlpTraceBramResponseSlice(pcieTraceBramResponse, 8);\n\t  if (oneHotDecode774[798-774] == 1) data = tlpTraceBramResponseSlice(pcieTraceBramResponse, 9);\n\t  if (oneHotDecode774[799-774] == 1) data = tlpTraceBramResponseSlice(pcieTraceBramResponse, 10);\n\t  if (oneHotDecode774[800-774] == 1) data = tlpTraceBramResponseSlice(pcieTraceBramResponse, 11);\n   \t  if (oneHotDecode774[801-774] == 1) data = (changeFifo.notEmpty()) ? (changeFifo.first()[31:0]) : 0;\n   \t  if (oneHotDecode774[802-774] == 1) data = (changeFifo.notEmpty()) ? (changeFifo.first()[63:32]) : 0;\n\n         //******************************** msix_base has to match CONFIG.MXIx_PBA_Offset in scripts/connectal-synth-pcie.tcl\n\t  // 16-bit MSIx pending bit field\n\t  if (oneHotDecode992[992-992] == 1) data = '0;                               // PBA structure (low)\n\t  if (oneHotDecode992[993-992] == 1) data = '0;                               // PBA structure (high)\n\t  //******************************** end of PBA Table\n      end\n      if (oneHotDecode774[802-774] == 1 && changeFifo.notEmpty())\n\t changeFifo.deq();\n      readResponseFifo.enq(MemData { data: data, tag: beat.tag, last: beat.last });\n   endrule\n\n   rule writeDataRule;\n      let beat <- csrWag.addrBeat.get();\n      let addr = beat.addr >> 2; // word address\n\n      let modaddr = (addr % 8192);\n      let msixaddr = modaddr - `msix_base;\n\n      csrWagBeatFifo.enq(beat);\n      csrWagIsMsixAddrFifo.enq(msixaddr >= 0 && msixaddr <= 63);\n      Bit#(1024) onehot = (1 << addr[9:0]);\n      $display(\"addr: %h\", addr);\n      csrWagOneHotFifo768.enq(onehot[775:768]);\n      csrWagOneHotFifo792.enq(onehot[794:792]);\n   endrule\n\n   rule writeDataRule2;\n      let memData <- toGet(writeDataFifo).get();\n      let dword = memData.data;\n\n      $display(\"data: %h, last: %h, tag: %h\", dword, memData.last, memData.tag);\n      let beat       <- toGet(csrWagBeatFifo).get();\n      let isMsixAddr <- toGet(csrWagIsMsixAddrFifo).get();\n      let addr = beat.addr >> 2; // word address\n      let modaddr = (addr % 8192);\n      let msix_base = `msix_base;\n      let msixaddr = modaddr - msix_base;\n      let oneHotDecode768 <- toGet(csrWagOneHotFifo768).get();\n      let oneHotDecode792 <- toGet(csrWagOneHotFifo792).get();\n\n      if (isMsixAddr)\n         begin\n            let groupaddr = (msixaddr / 4);\n            //******************************** area referenced from xilinx_x7_pcie_wrapper.v\n            case (msixaddr % 4)\n               0: msix_entry[groupaddr].addr_lo  <= (dword & 32'hfffffffc);\n               1: msix_entry[groupaddr].addr_hi  <= dword;\n               2: msix_entry[groupaddr].msg_data <= dword;\n               3: msix_entry[groupaddr].masked <= unpack(dword[0]);\n            endcase\n         end\n      else begin\n\t if (oneHotDecode768[775-768] == 1) tlpTracingReg <= (dword != 0) ? True : False;\n\t if (oneHotDecode768[768-768] == 1)\n\t     bramRequestFifo.enq(BRAMRequest{ write: False, responseOnWrite: False, address: truncate(dword), datain: ?});\n\t if (oneHotDecode792[792-792] == 1) tlpTraceBramWrAddrReg <= truncate(dword);\n\t if (oneHotDecode792[794-792] == 1) tlpTraceLimitReg <= truncate(dword);\n      end\n      if (beat.last)\n\t writeDoneFifo.enq(beat.tag);\n   endrule\n\n   interface PhysMemSlave memSlave;\n      interface PhysMemReadServer read_server;\n\t interface Put readReq;\n\t    method Action put(PhysMemRequest#(32,32) req);\n\t       csrRag.request.put(PhysMemRequest { addr: truncate(req.addr), burstLen: req.burstLen, tag: req.tag\n`ifdef BYTE_ENABLES\n\t\t\t\t\t\t  , firstbe: req.firstbe, lastbe: req.lastbe\n`endif\n\t\t\t\t\t\t  });\n\t    endmethod\n\t endinterface\n\t interface Get readData = toGet(readResponseFifo);\n   endinterface: read_server\n\n  interface PhysMemWriteServer write_server; \n\t interface Put writeReq;\n\t    method Action put(PhysMemRequest#(32,32) req);\n               $display(\"csrWag Request, addr=%h, burstLen=%h, tag=%h\", req.addr, req.burstLen, req.tag);\n\t       csrWag.request.put(PhysMemRequest { addr: truncate(req.addr), burstLen: req.burstLen, tag: req.tag\n`ifdef BYTE_ENABLES\n\t\t\t\t\t\t  , firstbe: req.firstbe, lastbe: req.lastbe\n`endif\n\t\t\t\t\t\t  });\n\t    endmethod\n\t endinterface\n     interface Put writeData = toPut(writeDataFifo);\n     interface Get writeDone = toGet(writeDoneFifo);\n   endinterface: write_server\n   endinterface\n   interface changes = toPipeIn(changeFifo);\n   interface TlpTraceClient traceClient;\n      interface Reg tlpTracing = tlpTracingReg;\n      interface Reg tlpTraceLimit = tlpTraceLimitReg;\n      interface Reg tlpTraceBramWrAddr = tlpTraceBramWrAddrReg;\n      interface BRAMClient bramClient;\n         interface Get request = toGet(bramRequestFifo);\n\t interface Put response = toPut(bramResponseFifo);\n      endinterface: bramClient\n   endinterface: traceClient\n   interface Vector msixEntry = map(toReadOnlyMsixEntry, msix_entry);\nendmodule: mkPcieControlAndStatusRegs\n"
  },
  {
    "path": "bsv/PcieEndpointS5.bsv",
    "content": "// Copyright (c) 2014 Cornell University\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\npackage PcieEndpointS5;\n\nimport ConnectalConfig   ::*;\nimport Clocks            ::*;\nimport Vector            ::*;\nimport Connectable       ::*;\nimport GetPut            ::*;\nimport Reserved          ::*;\nimport TieOff            ::*;\nimport DefaultValue      ::*;\nimport DReg              ::*;\nimport Gearbox           ::*;\nimport FIFO              ::*;\nimport FIFOF             ::*;\nimport SpecialFIFOs      ::*;\nimport ClientServer      ::*;\nimport Real              ::*;\n\nimport PCIE              ::*;\n\n`include \"ConnectalProjectConfig.bsv\"\n\n`ifdef BOARD_de5\nimport PS5LIB            ::*;\n`elsif BOARD_htg4\nimport PS4LIB            ::*;\n`endif\n\n(* always_ready, always_enabled *)\ninterface PciewrapPci_exp#(numeric type lanes);\n(* prefix=\"\", result=\"tx_p\" *) method Bit#(lanes) tx_p();\n(* prefix=\"\", result=\"rx_p\" *) method Action rx_p(Bit#(lanes) rx_p);\nendinterface\n\n(* always_ready, always_enabled *)\ninterface PciewrapUser#(numeric type lanes);\n   interface Clock clk_out;\nendinterface\n\n(* always_ready, always_enabled *)\ninterface PciewrapCfg#(numeric type lanes);\n   method Bit#(8) bus_number();\n   method Bit#(5) device_number();\n   method Bit#(3) function_number();\nendinterface\n\n////////////////////////////////////////////////////////////////////////////////\n/// Interfaces\n////////////////////////////////////////////////////////////////////////////////\n\ninterface PcieEndpointS5#(numeric type lanes);\n   interface PciewrapPci_exp#(lanes)   pcie;\n   interface PciewrapUser#(lanes)      user;\n   interface Server#(TLPData#(16), TLPData#(16)) tlp;\n   interface Clock epPcieClock;\n   interface Reset epPcieReset;\n   interface Clock epPortalClock;\n   interface Reset epPortalReset;\n   interface Clock epDerivedClock;\n   interface Reset epDerivedReset;\n   method PciId device;\nendinterface\n\ntypedef struct {\n   Bit#(1)               sop;\n   Bit#(1)               eop;\n   Bit#(7)               hit;\n   Bit#(bytes)           be;\n   Bit#(TMul#(bytes, 8)) data;\n} AvalonStRx#(type bytes) deriving (Bits, Eq);\n\ntypedef struct {\n   Bit#(1)               sop;\n   Bit#(1)               eop;\n   Bit#(bytes)           be;\n   Bit#(TMul#(bytes, 8)) data;\n} AvalonStTx#(type bytes) deriving (Bits, Eq);\n\n(* synthesize *)\nmodule mkPcieEndpointS5#(Clock clk_100MHz, Clock clk_50MHz, Reset perst_n)(PcieEndpointS5#(PcieLanes));\n\n   PCIEParams params = defaultValue;\n\n   Clock default_clock <- exposeCurrentClock;\n   Reset default_reset <- exposeCurrentReset;\n   Reset reset_high <- invertCurrentReset;\n   Reset npor = perst_n; //No soft reset signal from Application\n\n`ifdef BOARD_de5\n   PcieWrap#(12, 32, 128) pcie_ep <- mkPcieS5Wrap(clk_100MHz, clk_50MHz, npor, perst_n);\n`elsif BOARD_htg4\n   PcieWrap#(12, 32, 128) pcie_ep <- mkPcieS4Wrap(clk_100MHz, clk_50MHz, clk_100MHz, npor, perst_n);\n`endif\n\n   Clock core_clk = pcie_ep.coreclkout_hip;\n   Reset core_reset = pcie_ep.core_reset;\n   Reset core_resetn <- mkResetInverter(pcie_ep.core_reset, clocked_by core_clk);\n\n   Reg#(PciId) deviceReg <- mkReg(defaultValue, clocked_by core_clk, reset_by noReset);\n\n   FIFOF#(AvalonStTx#(16)) fAvalonStTx <- mkBypassFIFOF(clocked_by core_clk, reset_by noReset);\n   FIFOF#(AvalonStRx#(16)) fAvalonStRx <- mkBypassFIFOF(clocked_by core_clk, reset_by noReset);\n\n   let txready = (pcie_ep.tx_st.ready != 0 && fAvalonStTx.notEmpty);\n\n   function Bit#(2) getTxStEmpty (Bit#(16) be);\n      if (be == 16'h000f || be == 16'h00ff) begin\n         return 2'b1;\n      end\n      else begin\n         return 2'b0;\n      end\n   endfunction\n\n   rule drive_avalon_tx if (txready);\n      let info = fAvalonStTx.first; fAvalonStTx.deq;\n      pcie_ep.tx_st.valid(1);\n      pcie_ep.tx_st.sop(info.sop);\n      pcie_ep.tx_st.eop(info.eop);\n      let txStEmpty = getTxStEmpty(info.be);\n`ifdef BOARD_de5\n      pcie_ep.tx_st.empty(txStEmpty);\n`elsif BOARD_htg4\n      pcie_ep.tx_st.empty(txStEmpty[0]);\n`endif\n      pcie_ep.tx_st.err(0);\n      pcie_ep.tx_st.data(info.data);\n   endrule\n\n   (* fire_when_enabled, no_implicit_conditions *)\n   rule drive_avalon_tx2 if (!txready);\n      pcie_ep.tx_st.valid(0);\n      pcie_ep.tx_st.sop(0);\n      pcie_ep.tx_st.eop(0);\n      pcie_ep.tx_st.empty(0);\n      pcie_ep.tx_st.err(0);\n      pcie_ep.tx_st.data(0);\n   endrule\n\n   (* fire_when_enabled *)\n   rule sink_avalon_rx if (pcie_ep.rx_st.valid != 0);\n      AvalonStRx#(16) beat;\n      beat.sop = pcie_ep.rx_st.sop;\n      beat.eop = pcie_ep.rx_st.eop;\n      beat.be  = pcie_ep.rx_st.be;\n      // bar[7] is reserved for endpoints.\n      beat.hit = pcie_ep.rx_st.bar[6:0];\n\n      // 128-bit interface\n      // when rx_st_empty==1, rx_st_data[63:0] are valid\n      if (pcie_ep.rx_st.empty[0] == 1 && pcie_ep.rx_st.eop == 1) begin\n         if (pcie_ep.rx_st.be == 16'h000f) begin\n            beat.data = {96'h0, pcie_ep.rx_st.data[31:0]};\n         end\n         else if (pcie_ep.rx_st.be == 16'h00ff) begin\n            beat.data = {64'h0, pcie_ep.rx_st.data[63:0]};\n         end\n         else begin\n            beat.data = pcie_ep.rx_st.data;\n         end\n      end\n      // else, rx_st_data[127:0] are valid\n      else begin\n         beat.data = pcie_ep.rx_st.data;\n      end\n      // 256-bit interface requires a more complex decoder.\n      fAvalonStRx.enq(beat);\n   endrule\n\n   rule pertick1;\n      pcie_ep.rx_st.ready(pack(fAvalonStRx.notFull));\n      pcie_ep.hip_rst.core_ready(pcie_ep.hip_rst.serdes_pll_locked);\n   endrule\n\n   rule every1;\n      pcie_ep.hip_ctrl.test_in({26'h2, 1'b1, 5'b01000});\n   endrule\n\n   rule capture_deviceid;\n      deviceReg <= PciId {bus: pcie_ep.tl_cfg.bus_number,\n                          dev: pcie_ep.tl_cfg.dev_number,\n                          func: 0};\n   endrule\n\n   rule pulldown_msi;\n      pcie_ep.msi.msi_num(0);\n      pcie_ep.msi.msi_req(0);\n      pcie_ep.msi.msi_tc(0);\n      pcie_ep.msi.int_sts(0);\n   endrule\n\n   rule pulldown_cpl;\n      pcie_ep.tl_cfg.cpl_pending(0);\n      pcie_ep.tl_cfg.cpl_err(0);\n   endrule\n\n   rule unused_non_posted_signal;\n      pcie_ep.rx_st.mask(0);\n   endrule\n\n   // The PCIE endpoint is processing TLPData#(16)s at 125MHz.  The\n   // AXI bridge is accepting TLPData#(16)s at 125 MHz. For gen1 and\n   // gen2, there is no need for gearbox conversion.\n   // coreclkout_hip depends on link width, data rate and width of APP/TL interface\n   // Link Width  |  Link Rate  |   Avalon Interface Width  |  coreclkout_hip\n   //     x8            gen1                128 bit               125 Mhz\n   //     x8            gen2                128 bit               250 Mhz\n   //     x8            gen3                256 bit               250 Mhz\n   Server#(TLPData#(16), TLPData#(16)) tlp16 = (interface Server;\n      interface Put request;\n         method Action put(TLPData#(16) data);\n            fAvalonStTx.enq(AvalonStTx {\n               eop: pack(data.eof),\n               sop: pack(data.sof),\n               be:  dwordSwap128BE(data.be),\n               data: dwordSwap128(data.data)\n            });\n         endmethod\n      endinterface\n      interface Get response;\n         method ActionValue#(TLPData#(16)) get();\n            let info <- toGet(fAvalonStRx).get;\n            TLPData#(16) retval = defaultValue;\n            retval.sof = (info.sop == 1);\n            retval.eof = (info.eop == 1);\n            retval.be  = dwordSwap128BE(info.be);\n            retval.hit = info.hit;\n            retval.data = dwordSwap128(info.data);\n            return retval;\n         endmethod\n      endinterface\n   endinterface);\n\n   method PciId device = deviceReg;\n\n   interface PciewrapUser user;\n      method Clock clk_out();\n         return core_clk;\n      endmethod\n   endinterface\n\n   interface PciewrapPci_exp pcie;\n      Bit#(PcieLanes) vt = pack(pcie_ep.tx.out);\n      method Bit#(PcieLanes) tx_p();\n         return vt;\n      endmethod\n      method Action rx_p(Bit#(PcieLanes) v);\n         action\n            pcie_ep.rx.in(unpack(v));\n         endaction\n      endmethod\n   endinterface\n\n\n   interface tlp = tlp16;\n   interface Clock epPcieClock = core_clk;\n   interface Reset epPcieReset = core_resetn;\n   interface Clock epPortalClock = core_clk;\n   interface Reset epPortalReset = core_resetn;\n   interface Clock epDerivedClock = core_clk;\n   interface Reset epDerivedReset = core_resetn;\n\nendmodule: mkPcieEndpointS5\n\nendpackage: PcieEndpointS5\n"
  },
  {
    "path": "bsv/PcieEndpointS5Test.bsv",
    "content": "\n// Copyright (c) 2014 Quanta Research Cambridge, Inc.\n// Copyright (c) 2014 Cornell Univeristy.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\nimport Clocks        ::*;\nimport Connectable   ::*;\nimport ConnectalAlteraCells   ::*;\n\nimport ALTERA_PCIE_ED_WRAPPER ::*;\nimport PS5LIB ::*;\n\n`include \"ConnectalProjectConfig.bsv\"\n\n// Default Pcie Application\n\n(* always_ready, always_enabled *)\ninterface PcieS5AppRxSt#(numeric type data_width);\n   method Action           sop(Bit#(1) sop);\n   method Action           eop(Bit#(1) eop);\n   method Action           data(Bit#(data_width) data);\n   method Action           valid(Bit#(1) valid);\n   method Action           empty(Bit#(2) empty);\n   method Action           err(Bit#(1) err);\n   method Bit#(1)          ready;\nendinterface\n\n(* always_ready, always_enabled *)\ninterface PcieS5AppRxBar;\n   method Action           bar(Bit#(8) bar);\n   method Bit#(1)          mask;\nendinterface\n\n(* always_ready, always_enabled *)\ninterface PcieS5AppTxSt#(numeric type data_width);\n   method Bit#(1)          sop;\n   method Bit#(1)          eop;\n   method Bit#(1)          valid;\n   method Bit#(1)          err;\n   method Bit#(2)          empty;\n   method Bit#(data_width) data;\n   method Action           ready(Bit#(1) ready);\nendinterface\n\n(* always_ready, always_enabled *)\ninterface PcieS5AppTxCred;\n   method Action           datafccp(Bit#(12) datafccp);\n   method Action           datafcnp(Bit#(12) datafcnp);\n   method Action           datafcp(Bit#(12) datafcp);\n   method Action           fchipcons(Bit#(6) fchipcons);\n   method Action           fcinfinite(Bit#(6) fcinfinite);\n   method Action           hdrfccp(Bit#(8) hdrfccp);\n   method Action           hdrfcnp(Bit#(8) hdrfcnp);\n   method Action           hdrfcp(Bit#(8) hdrfcp);\nendinterface\n\n(* always_ready, always_enabled *)\ninterface PcieS5AppHipRst;\n   method Action  serdes_pll_locked(Bit#(1) serdes_pll_locked);\n   method Action  pld_clk_inuse(Bit#(1) pld_clk_inuse);\n   method Bit#(1) core_ready;\nendinterface\n\n(* always_ready, always_enabled *)\ninterface PcieS5AppMsi;\n   method Action      int_ack(Bit#(1) int_ack);\n   method Bit#(1)     int_sts();\n   method Action      msi_ack(Bit#(1) msi_ack);\n   method Bit#(5)     msi_num();\n   method Bit#(1)     msi_req();\n   method Bit#(3)     msi_tc();\nendinterface\n\n(* always_ready, always_enabled *)\ninterface PcieS5AppHipStatus;\n   method Action      cor_ext_rcv(Bit#(1) cor_ext_rcv);\n   method Action      cor_ext_rpl(Bit#(1) cor_ext_rpl);\n   method Action      rpl        (Bit#(1) rpl);\n   method Action      dlup       (Bit#(1) dlup);\n   method Action      dlup_exit  (Bit#(1) dlup_exit);\n   method Action      ev128ns    (Bit#(1) ev128ns);\n   method Action      ev1us      (Bit#(1) ev1us);\n   method Action      hotrst     (Bit#(1) hotrstexit);\n   method Action      int_status (Bit#(4) int_status);\n   method Action      l2_exit    (Bit#(1) l2_exit);\n   method Action      lane_act   (Bit#(4) lane_act);\n   method Action      ltssmstate (Bit#(5) ltssmstate);\n   method Action      rx_par_err (Bit#(1) rx_par_err);\n   method Action      tx_par_err (Bit#(2) tx_par_err);\n   method Action      cfg_par_err (Bit#(1) cfg_par_err);\n   method Action      ko_cpl_spc_data (Bit#(12) ko_cpl_spc_data);\n   method Action      ko_cpl_spc_header (Bit#(8) ko_cpl_spc_header);\nendinterface\n\n(* always_ready, always_enabled *)\ninterface PcieS5AppTlCfg;\n   method Action      cfg_add(Bit#(4) cfg_add);\n   method Action      cfg_ctl(Bit#(32) cfg_ctl);\n   method Action      cfg_sts(Bit#(53) cfg_sts);\n   method Bit#(1)     cpl_pending;\n   method Bit#(7)     cpl_err;\nendinterface\n\n(* always_ready, always_enabled *)\ninterface PcieS5AppLmi;\n   method Action      ack(Bit#(1) ack);\n   method Bit#(12)    addr();\n   method Bit#(32)    din();\n   method Action      dout(Bit#(32) dout);\n   method Bit#(1)     rden();\n   method Bit#(1)     wren();\nendinterface\n\ninterface PcieS5App;\n   interface PcieS5AppRxSt#(128) rx_st;\n   interface PcieS5AppRxBar      rx_bar;\n   interface PcieS5AppTxSt#(128) tx_st;\n   interface PcieS5AppTxCred     tx_cred;\n   interface PcieS5AppHipRst     hip_rst;\n   interface PcieS5AppMsi        msi;\n   interface PcieS5AppHipStatus  hip_status;\n   interface PcieS5AppTlCfg      tl;\n   interface PcieS5AppLmi        lmi;\nendinterface\n\ninstance Connectable#(PcieS5App, PcieS5Wrap#(12, 32, 128));\n   module mkConnection#(PcieS5App a, PcieS5Wrap#(12, 32, 128) b)(Empty);\n      (* fire_when_enabled, no_implicit_conditions *)\n      rule rx_st;\n         a.rx_st.sop(b.rx_st.sop);\n         a.rx_st.eop(b.rx_st.eop);\n         a.rx_st.data(b.rx_st.data);\n         a.rx_st.valid(b.rx_st.valid);\n         a.rx_st.empty(b.rx_st.empty);\n         a.rx_st.err(b.rx_st.err);\n         b.rx_st.ready(a.rx_st.ready);\n      endrule\n\n      rule tx_st;\n         b.tx_st.sop(a.tx_st.sop);\n         b.tx_st.eop(a.tx_st.eop);\n         b.tx_st.data(a.tx_st.data);\n         b.tx_st.valid(a.tx_st.valid);\n         b.tx_st.empty(a.tx_st.empty);\n         b.tx_st.err(a.tx_st.err);\n         a.tx_st.ready(b.tx_st.ready);\n      endrule\n\n      rule rx_bar;\n         a.rx_bar.bar(b.rx_specific.bar);\n         b.rx_specific.mask(a.rx_bar.mask);\n      endrule\n\n      rule tx_cred;\n         a.tx_cred.datafccp(b.tx_cred.datafccp);\n         a.tx_cred.datafcnp(b.tx_cred.datafcnp);\n         a.tx_cred.datafcp(b.tx_cred.datafcp);\n         a.tx_cred.hdrfccp(b.tx_cred.hdrfccp);\n         a.tx_cred.hdrfcnp(b.tx_cred.hdrfcnp);\n         a.tx_cred.hdrfcp(b.tx_cred.hdrfcp);\n         a.tx_cred.fchipcons(b.tx_cred.fchipcons);\n         a.tx_cred.fcinfinite(b.tx_cred.fcinfinite);\n      endrule\n\n      rule hip_rst;\n         a.hip_rst.serdes_pll_locked(b.hip_rst.serdes_pll_locked);\n         a.hip_rst.pld_clk_inuse(b.hip_rst.pld_clk_inuse);\n         b.hip_rst.core_ready(a.hip_rst.core_ready);\n      endrule\n\n      rule msi;\n         a.msi.int_ack(b.msi.int_ack);\n         a.msi.msi_ack(b.msi.msi_ack);\n         b.msi.int_sts(a.msi.int_sts);\n         b.msi.msi_num(a.msi.msi_num);\n         b.msi.msi_req(a.msi.msi_req);\n         b.msi.msi_tc(a.msi.msi_tc);\n      endrule\n\n      rule tl;\n         a.tl.cfg_add(b.tl.cfg_add);\n         a.tl.cfg_ctl(b.tl.cfg_ctl);\n         a.tl.cfg_sts(b.tl.cfg_sts);\n         b.tl.cpl_pending(a.tl.cpl_pending);\n         b.tl.cpl_err(a.tl.cpl_err);\n      endrule\n\n      rule lmi;\n         a.lmi.ack(b.lmi.ack);\n         a.lmi.dout(b.lmi.dout);\n         b.lmi.addr(a.lmi.addr);\n         b.lmi.din(a.lmi.din);\n         b.lmi.rden(a.lmi.rden);\n         b.lmi.wren(a.lmi.wren);\n      endrule\n\n      rule hipstatus;\n         a.hip_status.cor_ext_rcv(b.hip_status.cor_ext_rcv);\n         a.hip_status.cor_ext_rpl(b.hip_status.cor_ext_rpl);\n         a.hip_status.rpl(b.hip_status.rpl);\n         a.hip_status.dlup(b.hip_status.dlup);\n         a.hip_status.dlup_exit(b.hip_status.dlup_exit);\n         a.hip_status.ev128ns(b.hip_status.ev128ns);\n         a.hip_status.ev1us(b.hip_status.ev1us);\n         a.hip_status.hotrst(b.hip_status.hotrst);\n         a.hip_status.int_status(b.hip_status.int_status);\n         a.hip_status.l2_exit(b.hip_status.l2_exit);\n         a.hip_status.lane_act(b.hip_status.lane_act);\n         a.hip_status.ltssmstate(b.hip_status.ltssmstate);\n         a.hip_status.rx_par_err(b.hip_status.rx_par_err);\n         a.hip_status.tx_par_err(b.hip_status.tx_par_err);\n         a.hip_status.cfg_par_err(b.hip_status.cfg_par_err);\n         a.hip_status.ko_cpl_spc_data(b.hip_status.ko_cpl_spc_data);\n         a.hip_status.ko_cpl_spc_header(b.hip_status.ko_cpl_spc_header);\n      endrule\n   endmodule\nendinstance\n\nmodule mkPcieS5App#(Clock core_clk, Reset core_clk_rst) (PcieS5App);\n\n   PcieEdWrap pcie_app <- mkPcieEdWrap(core_clk, core_clk_rst);\n\n   rule every1;\n      pcie_app.testin.zero(0);\n      pcie_app.pme.to_sr(0);\n      pcie_app.reset.status(0);\n      pcie_app.rx_s.t_be(16'hFFFF); // rx_st.be is deprecated.\n   endrule\n\n   interface PcieS5AppRxSt rx_st;\n      method sop   = pcie_app.rx_s.t_sop;\n      method eop   = pcie_app.rx_s.t_eop;\n      method data  = pcie_app.rx_s.t_data;\n      method valid = pcie_app.rx_s.t_valid;\n      method empty = pcie_app.rx_s.t_empty;\n      method err   = pcie_app.rx_s.t_err;\n      method Bit#(1) ready; return pcie_app.rx_s.t_ready; endmethod\n   endinterface\n\n   interface PcieS5AppRxBar rx_bar;\n      method bar = pcie_app.rx_s.t_bar;\n      method Bit#(1) mask; return pcie_app.rx_s.t_mask; endmethod\n   endinterface\n\n   interface PcieS5AppTxSt tx_st;\n      method Bit#(1) sop;   return pcie_app.tx_s.t_sop;   endmethod\n      method Bit#(1) eop;   return pcie_app.tx_s.t_eop;   endmethod\n      method Bit#(1) valid; return pcie_app.tx_s.t_valid; endmethod\n      method Bit#(1) err;   return pcie_app.tx_s.t_err;   endmethod\n      method Bit#(2) empty; return pcie_app.tx_s.t_empty; endmethod\n      method Bit#(128) data; return pcie_app.tx_s.t_data;  endmethod\n      method ready = pcie_app.tx_s.t_ready;\n   endinterface\n\n   interface PcieS5AppTxCred tx_cred;\n      method datafccp   = pcie_app.tx_cred.datafccp;\n      method datafcnp   = pcie_app.tx_cred.datafcnp;\n      method datafcp    = pcie_app.tx_cred.datafcp;\n      method fchipcons  = pcie_app.tx_cred.fchipcons;\n      method fcinfinite = pcie_app.tx_cred.fcinfinite;\n      method hdrfccp    = pcie_app.tx_cred.hdrfccp;\n      method hdrfcnp    = pcie_app.tx_cred.hdrfcnp;\n      method hdrfcp     = pcie_app.tx_cred.hdrfcp;\n   endinterface\n\n   interface PcieS5AppHipRst hip_rst;\n      method serdes_pll_locked = pcie_app.serdes.pll_locked;\n      method pld_clk_inuse = pcie_app.pld.clk_inuse;\n      method Bit#(1) core_ready;\n         return pcie_app.pld.core_ready;\n      endmethod\n   endinterface\n\n   interface PcieS5AppMsi msi;\n      method Bit#(1) int_sts;  return pcie_app.app.int_sts;  endmethod\n      method Bit#(5) msi_num;  return pcie_app.app.msi_num;  endmethod\n      method Bit#(1) msi_req;  return pcie_app.app.msi_req;  endmethod\n      method Bit#(3) msi_tc;   return pcie_app.app.msi_tc;   endmethod\n      method int_ack = pcie_app.app.int_ack;\n      method msi_ack = pcie_app.app.msi_ack;\n   endinterface\n\n   interface PcieS5AppHipStatus hip_status;\n      method cor_ext_rcv = pcie_app.derr.cor_ext_rcv;\n      method cor_ext_rpl = pcie_app.derr.cor_ext_rpl;\n      method rpl         = pcie_app.derr.rpl;\n      method dlup        = pcie_app.dl.up;\n      method dlup_exit   = pcie_app.dl.up_exit;\n      method ev128ns     = pcie_app.ev128.ns;\n      method ev1us       = pcie_app.ev1.us;\n      method hotrst      = pcie_app.hotrst.exit;\n      method int_status  = pcie_app.int_s.tatus;\n      method l2_exit     = pcie_app.l2.exit;\n      method lane_act    = pcie_app.lane.act;\n      method ltssmstate  = pcie_app.ltssm.state;\n      method rx_par_err  = pcie_app.rx_par.err;\n      method tx_par_err  = pcie_app.tx_par.err;\n      method cfg_par_err  = pcie_app.cfg_par.err;\n      method ko_cpl_spc_data = pcie_app.ko.cpl_spc_data;\n      method ko_cpl_spc_header = pcie_app.ko.cpl_spc_header;\n   endinterface\n\n   interface PcieS5AppTlCfg tl;\n      method cfg_add = pcie_app.tl.cfg_add;\n      method cfg_ctl = pcie_app.tl.cfg_ctl;\n      method cfg_sts = pcie_app.tl.cfg_sts;\n      method cpl_pending; return pcie_app.cpl.pending; endmethod\n      method cpl_err;     return pcie_app.cpl.err;     endmethod\n   endinterface\n\n   interface PcieS5AppLmi lmi;\n      method Bit#(12) addr;  return pcie_app.lmi.addr;  endmethod\n      method Bit#(32) din;   return pcie_app.lmi.din;   endmethod\n      method Bit#(1)  rden;  return pcie_app.lmi.rden;  endmethod\n      method Bit#(1)  wren;  return pcie_app.lmi.wren;  endmethod\n      method ack = pcie_app.lmi.ack;\n      method dout = pcie_app.lmi.dout;\n   endinterface\nendmodule\n\n`ifdef PCIES5_SIM\n// PcieS5Top\n// Used for simulation with Default Pcie Application\n(* always_ready, always_enabled *)\ninterface PcieS5Top;\n   interface PcieS5HipSerial hip_serial;\n   interface PcieS5HipPipe hip_pipe;\n   interface PcieS5HipCtrl hip_ctrl;\nendinterface\n\n(* synthesize, no_default_clock, no_default_reset, clock_prefix=\"\", reset_prefix=\"\" *)\nmodule mkPcieS5Top #(Clock clk_50_clk, Clock clk_100_clk, Reset clk_50_rst_reset_n, Reset rst_n_npor, Reset rst_n_pin_perst) (PcieS5Top);\n\n   PcieS5Wrap#(12, 32, 128) pcie <- mkPcieS5Wrap(clk_100_clk, clk_50_clk, rst_n_npor, rst_n_pin_perst, clk_50_rst_reset_n, clocked_by clk_100_clk, reset_by clk_50_rst_reset_n);\n\n   Clock coreclk = pcie.coreclkout_hip;\n   PcieS5App pcie_app <- mkPcieS5App(coreclk, clk_50_rst_reset_n, clocked_by clk_100_clk, reset_by clk_50_rst_reset_n);\n\n   mkConnection(pcie_app, pcie);\n\n   interface PcieS5HipSerial hip_serial;\n      interface rx = pcie.rx;\n      interface tx = pcie.tx;\n   endinterface\n\n   interface PcieS5HipPipe hip_pipe = pcie.hip_pipe;\n   interface PcieS5HipCtrl hip_ctrl = pcie.hip_ctrl;\nendmodule\n`endif\n"
  },
  {
    "path": "bsv/PcieGearbox.bsv",
    "content": "\n// Copyright (c) 2008- 2009 Bluespec, Inc.  All rights reserved.\n// $Revision$\n// $Date$\n// Copyright (c) 2013 Quanta Research Cambridge, Inc.\n\n// PCI-Express for Xilinx 7\n// FPGAs.\n\n`include \"ConnectalProjectConfig.bsv\"\nimport Vector          :: *;\nimport GetPut          :: *;\nimport PCIE            :: *;\nimport Clocks          :: *;\nimport DefaultValue    :: *;\nimport TieOff          :: *;\nimport XilinxCells     :: *;\nimport ClientServer    :: *;\n`ifdef XILINX\nimport PCIEWRAPPER     :: *;\n`endif\nimport Connectable     ::*;\nimport Reserved        ::*;\nimport DReg            ::*;\nimport Gearbox         ::*;\nimport FIFO            ::*;\nimport FIFOF           ::*;\nimport SpecialFIFOs    ::*;\n\n// Interface wrapper for PCIE\ninterface PcieGearbox;\n   interface Client#(TLPData#(8), TLPData#(8)) tlp;\n   interface Server#(TLPData#(16), TLPData#(16)) pci;\nendinterface\n\n// This module builds the transactor hierarchy, the clock\n// generation logic and the PCIE-to-port logic.\n(* no_default_clock, no_default_reset, synthesize *)\nmodule mkPcieGearbox#(Clock epClock250, Reset epReset250, Clock epClock125, Reset epReset125)(PcieGearbox);\n   // Connections between TLPData#(16) and a PCIE endpoint, using a gearbox\n   // to match data rates between the endpoint and design clocks.\n   Gearbox#(1, 2, TLPData#(8)) fifoRxData   <- mk1toNGearbox(epClock250, epReset250, epClock125, epReset125);\n   Reg#(Bool)                  rOddBeat     <- mkRegA(False, clocked_by epClock250, reset_by epReset250);\n   Reg#(Bool)                  rSendInvalid <- mkRegA(False, clocked_by epClock250, reset_by epReset250);\n   FIFO#(TLPData#(8))          inFifo       <- mkFIFO(clocked_by epClock250, reset_by epReset250);\n   FIFO#(TLPData#(8))          outFifo      <- mkFIFO(clocked_by epClock250, reset_by epReset250);\n   Gearbox#(2, 1, TLPData#(8)) fifoTxData   <- mkNto1Gearbox(epClock125, epReset125, epClock250, epReset250);\n\n   rule process_incoming_packets1(!rSendInvalid);\n      let data = inFifo.first; inFifo.deq;\n      rOddBeat     <= !rOddBeat;\n      rSendInvalid <= !rOddBeat && data.eof;\n      Vector#(1, TLPData#(8)) v = defaultValue;\n      v[0] = data;\n      fifoRxData.enq(v);\n   endrule\n\n   rule send_invalid_packets1(rSendInvalid);\n      rOddBeat     <= !rOddBeat;\n      rSendInvalid <= False;\n      Vector#(1, TLPData#(8)) v = defaultValue;\n      v[0].eof = True;\n      v[0].be  = 0;\n      fifoRxData.enq(v);\n   endrule\n\n   rule process_outgoing_packets;\n      let data = fifoTxData.first; fifoTxData.deq;\n      let temp = head(data);\n      // filter out TLPs with 00 byte enable\n      if (temp.be != 0)\n          outFifo.enq(temp);\n   endrule\n\n   interface Server pci;\n      interface Get response;\n         method ActionValue#(TLPData#(16)) get();\n            function TLPData#(16) combine(Vector#(2, TLPData#(8)) in);\n               return TLPData {sof:   in[0].sof, eof: in[1].eof, hit: in[0].hit,\n                   be: { in[0].be, in[1].be }, data: { in[0].data, in[1].data } };\n            endfunction\n            fifoRxData.deq;\n            return combine(fifoRxData.first);\n         endmethod\n      endinterface\n      interface Put request;\n         method Action put(TLPData#(16) data);\n            function Vector#(2, TLPData#(8)) split(TLPData#(16) in);\n               Vector#(2, TLPData#(8)) v = defaultValue;\n               v[0].sof  = in.sof;\n               v[0].eof  = (in.be[7:0] == 0) ? in.eof : False;\n               v[0].hit  = in.hit;\n               v[0].be   = in.be[15:8];\n               v[0].data = in.data[127:64];\n               v[1].sof  = False;\n               v[1].eof  = in.eof;\n               v[1].hit  = in.hit;\n               v[1].be   = in.be[7:0];\n               v[1].data = in.data[63:0];\n               return v;\n            endfunction\n            fifoTxData.enq(split(data));\n         endmethod\n      endinterface\n   endinterface\n   interface Client tlp;\n      interface request = toGet(outFifo);\n      interface response = toPut(inFifo);\n   endinterface\nendmodule: mkPcieGearbox\n"
  },
  {
    "path": "bsv/PcieHost.bsv",
    "content": "// Copyright (c) 2014-2015 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\nimport Vector            :: *;\nimport BuildVector       :: *;\nimport Clocks            :: *;\nimport GetPut            :: *;\nimport FIFO              :: *;\nimport Connectable       :: *;\nimport ClientServer      :: *;\nimport BRAM              :: *;\nimport DefaultValue      :: *;\nimport ConnectalConfig   :: *;\nimport PCIE              :: *;\nimport PcieSplitter      :: *;\nimport PcieTracer        :: *;\nimport Xilinx            :: *;\nimport ConnectalXilinxCells :: *;\nimport Bscan             :: *;\nimport Portal            :: *;\nimport MemToPcie    :: *;\nimport PcieToMem   :: *;\nimport PcieCsr           :: *;\nimport ConnectalMemTypes          :: *;\n`include \"ConnectalProjectConfig.bsv\"\n`ifndef SIMULATION\n`ifdef XILINX\n`ifdef PCIE1\nimport PCIEWRAPPER       :: *;\nimport Pcie1EndpointX7   :: *;\n`endif // pcie1\n`ifdef PCIE2\nimport PCIEWRAPPER2       :: *;\nimport Pcie2EndpointX7 :: *;\n`endif // pcie2\n`ifdef PCIE3\n`ifdef VirtexUltrascalePlus\n  import PCIEWRAPPER3uplus::*;\n`else\n  `ifdef XilinxUltrascale\n   import PCIEWRAPPER3u   ::*;\n  `else\n   import PCIEWRAPPER3    :: *;\n  `endif\n`endif\nimport Pcie3EndpointX7   :: *;\n`endif // pcie3\n`elsif ALTERA\nimport PcieEndpointS5    :: *;\n`endif\n`endif\nimport HostInterface     :: *;\n\n`ifdef XILINX_SYS_CLK\n `ifdef VirtexUltrascalePlus\n   `define SYS_CLK_PARAM Clock sys_clk_p, Clock sys_clk_n, Clock sys_clk_300_p, Clock sys_clk_300_n, Clock sys_clk1_250_p, Clock sys_clk1_250_n, Clock sys_clk2_250_p, Clock sys_clk2_250_n, \n   `define SYS_CLK_ARG sys_clk_p, sys_clk_n, sys_clk_300_p, sys_clk_300_n, sys_clk1_250_p, sys_clk1_250_n, sys_clk2_250_p, sys_clk2_250_n, \n `else\n   `ifdef VirtexUltrascale\n     `define SYS_CLK_PARAM Clock sys_clk_p, Clock sys_clk_n, Clock sys_clk1_300_p, Clock sys_clk1_300_n, Clock sys_clk2_300_p, Clock sys_clk2_300_n, \n     `define SYS_CLK_ARG sys_clk_p, sys_clk_n, sys_clk1_300_p, sys_clk1_300_n, sys_clk2_300_p, sys_clk2_300_n, \n   `else\n     `define SYS_CLK_PARAM Clock sys_clk_p, Clock sys_clk_n,\n     `define SYS_CLK_ARG sys_clk_p, sys_clk_n,\n   `endif\n  `endif\n`else\n  `define SYS_CLK_PARAM\n  `define SYS_CLK_ARG\n`endif\n\n\n`ifdef PCIE3\ntypedef TMin#(DataBusWidth, 128) PcieDataBusWidth;\n`else\ntypedef TMin#(DataBusWidth, 128) PcieDataBusWidth;\n`endif\n\n(* synthesize *)\nmodule mkMemToPcieSynth#(PciId my_id)(MemToPcie#(PcieDataBusWidth));\n   let memSlaveEngine <- mkMemToPcie(my_id);\n   return memSlaveEngine;\nendmodule\n\n// ==================================================\n// PCIE Gen3  PcieHost\n//\n`ifdef PCIE3\n(* synthesize *)\nmodule mkPcieHost#(PciId my_pciId)(PcieHost#(PcieDataBusWidth, NumberOfMasters));\n   TLPDispatcher dispatcher <- mkTLPDispatcher;\n   TLPArbiter arbiter <- mkTLPArbiter;\n   MemToPcie#(PcieDataBusWidth) sEngine <- mkMemToPcieSynth(my_pciId);\n`ifdef PCIE3\n   MemInterrupt intr <- mkMemInterrupt(my_pciId);\n`endif\n   Vector#(PortMax, PcieToMem) mvec;\n   for (Integer i=0; i < valueOf(PortMax) - 1; i=i+1) begin\n      let tlp;\n      if (i == portInterrupt)\n         tlp = intr.tlp;\n      else begin\n         mvec[i] <- mkPcieToMem(my_pciId);\n         tlp = mvec[i].tlp;\n      end\n      mkConnection((interface Server;\n                       interface response = dispatcher.out[i];\n                       interface request = arbiter.in[i];\n                    endinterface), tlp);\n   end\n\n   PcieTracer traceif <- mkPcieTracer();\n   let splitter = (interface Client;\n                      interface request = arbiter.outToBus;\n                      interface response = dispatcher.inFromBus;\n                  endinterface);\n`ifdef TRACE_PORTAL\n   mkConnection(traceif.bus, splitter);\n`else\n   mkConnection(traceif.bus, sEngine.tlp);\n`endif\n\n   PcieControlAndStatusRegs csr <- mkPcieControlAndStatusRegs();\n   mkConnection(mvec[portConfig].master, csr.memSlave);\n\n   mkConnection(csr.traceClient, traceif.traceServer);\n   interface msixEntry = csr.msixEntry;\n   interface master = mvec[portPortal].master;\n   interface slave = vec(sEngine.slave);\n   interface interruptRequest = intr.interruptRequest;\n`ifdef TRACE_PORTAL\n   interface pcic = traceif.pci;\n   interface pcir = sEngine.tlp;\n`else\n   interface pcic = splitter;\n   interface pcir = traceif.pci;\n`endif\n   interface changes = csr.changes;\nendmodule: mkPcieHost\n`else //NOT PCIE3\n// ======================================================\n// PCIE GEN1 and GEN2 PcieHost\n//(* synthesize *) commented out so that the guards in MemServer aren't destroyed (mdk)\nmodule  mkPcieHost#(PciId my_pciId)(PcieHost#(PcieDataBusWidth, NumberOfMasters));\n   let dispatcher <- mkTLPDispatcher;\n   let arbiter    <- mkTLPArbiter;\n   Vector#(NumberOfMasters,MemToPcie#(PcieDataBusWidth)) sEngine <- replicateM(mkMemToPcieSynth(my_pciId));\n   Vector#(NumberOfMasters,PhysMemSlave#(PciePhysAddrWidth,PcieDataBusWidth)) slavearr;\n   MemInterrupt intr <- mkMemInterrupt(my_pciId);\n`ifdef PCIE_BSCAN\n   BscanTop bscan <- mkBscanTop(3); // Use USER3  (JTAG IDCODE address 0x22)\n   BscanLocal lbscan <- mkBscanLocal(bscan, clocked_by bscan.tck, reset_by bscan.rst);\n`endif\n\n   Vector#(PortMax, PcieToMem) mvec;\n   for (Integer i = 0; i < valueOf(PortMax) - 1 + valueOf(NumberOfMasters); i=i+1) begin\n       let tlp;\n       if (i == portInterrupt)\n           tlp = intr.tlp;\n       else if (i >= portAxi) begin\n           tlp = sEngine[i - portAxi].tlp;\n           slavearr[i - portAxi] = sEngine[i - portAxi].slave;\n       end\n       else begin\n           mvec[i] <- mkPcieToMem(my_pciId);\n           tlp = mvec[i].tlp;\n       end\n       mkConnection((interface Server;\n                        interface response = dispatcher.out[i];\n                        interface request = arbiter.in[i];\n                     endinterface), tlp);\n   end\n\n   PcieTracer  traceif <- mkPcieTracer();\n   mkConnection(traceif.bus, (interface Client;\n                                 interface request = arbiter.outToBus;\n                                 interface response = dispatcher.inFromBus;\n                              endinterface));\n\n`ifndef SIMULATION\n`ifdef PCIE_BSCAN\n   Reg#(Bit#(TAdd#(TlpTraceAddrSize,1))) bscanPcieTraceBramWrAddrReg <- mkReg(0);\n   BscanBram#(Bit#(TAdd#(TlpTraceAddrSize,1)), TimestampedTlpData) pcieBscanBram <- mkBscanBram(127, bscanPcieTraceBramWrAddrReg, lbscan.loc[1]);\n   mkConnection(pcieBscanBram.bramClient, traceif.tlpdata.altBramServer);\n   rule tdorule;\n      lbscan.loc[1].tdo(pcieBscanBram.data_out());\n   endrule\n`endif\n`endif\n\n   PcieControlAndStatusRegs csr <- mkPcieControlAndStatusRegs;\n   mkConnection(mvec[portConfig].master, csr.memSlave);\n   mkConnection(csr.traceClient, traceif.traceServer);\n\n   interface msixEntry = csr.msixEntry;\n   interface master = mvec[portPortal].master;\n   interface slave = slavearr;\n   interface interruptRequest = intr.interruptRequest;\n   interface pci = traceif.pci;\n   interface changes = csr.changes;\n`ifdef PCIE_BSCAN\n   interface BscanTop bscanif = lbscan.loc[0];\n`else\n`ifdef PCIE_TRACE_PORT\n   interface BRAMServer traceBramServer = traceif.tlpdata.altBramServer;\n`endif\n`endif\nendmodule: mkPcieHost\n`endif //PCIE3\n\ninterface PcieTop#(type ipins);\n`ifndef SIMULATION\n   (* prefix=\"PCIE\" *)\n   interface PciewrapPci_exp#(PcieLanes) pcie;\n`ifdef PINS_ALWAYS_READY\n   (* always_ready *)\n`endif\n   (* prefix=\"\" *)\n   interface ipins       pins;\n`endif\nendinterface\n\n`ifdef SIMULATION\nmodule mkBsimPcieHostTop #(Clock pci_sys_clk_p, Clock pci_sys_clk_n, `SYS_CLK_PARAM Reset pci_sys_reset_n)(PcieHostTop);\n   let dc <- exposeCurrentClock;\n   let dr <- exposeCurrentReset;\n   PcieHost#(PcieDataBusWidth, NumberOfMasters) pciehost <- mkPcieHost(PciId{ bus:0, dev:0, func:0});\n   // connect pciehost.pci to bdip functions here\n   rule from_bdpi if (can_get_tlp);\n      TLPData#(16) foo <- get_tlp;\n      pciehost.pci.response.put(foo);\n      //$display(\"from_bdpi: %h %d\", foo, valueOf(SizeOf#(TLPData#(16))));\n   endrule\n   rule to_bdpi if (can_put_tlp);\n      TLPData#(16) foo <- pciehost.pci.request.get;\n      put_tlp(foo);\n      //$display(\"to_bdpi\");\n   endrule\n   interface Clock pcieClock = dc;\n   interface Reset pcieReset = dr;\n   interface PcieHost tpciehost = pciehost;\nendmodule\n`endif\n\n`ifdef XILINX\n(* no_default_clock, no_default_reset *)\nmodule mkXilinxPcieHostTop #(Clock pci_sys_clk_p, Clock pci_sys_clk_n, `SYS_CLK_PARAM Reset pci_sys_reset_n)(PcieHostTop);\n\n// Clock and PcieEndpoint for Xilinx\n`ifdef XILINX_SYS_CLK\n   Clock sys_clk_200mhz <- mkClockIBUFDS(\n`ifdef ClockDefaultParam\n       defaultValue,\n`endif\n       sys_clk_p, sys_clk_n);\n   Clock sys_clk_200mhz_buf <- mkClockBUFG(clocked_by sys_clk_200mhz);\n\n`ifdef VirtexUltrascalePlus   \n   Clock sys_clk_300mhz <- mkClockIBUFDS(\n                                         `ifdef ClockDefaultParam\n                                         defaultValue,\n                                         `endif\n                                         sys_clk_300_p, sys_clk_300_n);\n   Clock sys_clk_300mhz_buf <- mkClockBUFG(clocked_by sys_clk_300mhz);\n   \n   Clock sys_clk1_250mhz <- mkClockIBUFDS(\n                                          `ifdef ClockDefaultParam\n                                          defaultValue,\n                                          `endif\n                                          sys_clk1_250_p, sys_clk1_250_n);\n   Clock sys_clk1_250mhz_buf <- mkClockBUFG(clocked_by sys_clk1_250mhz);\n   Clock sys_clk2_250mhz <- mkClockIBUFDS(\n                                          `ifdef ClockDefaultParam\n                                          defaultValue,\n                                          `endif\n                                          sys_clk2_250_p, sys_clk2_250_n);\n   Clock sys_clk2_250mhz_buf <- mkClockBUFG(clocked_by sys_clk2_250mhz);\n`else\n `ifdef VirtexUltrascale \n   Clock sys_clk1_300mhz <- mkClockIBUFDS(\n                                          `ifdef ClockDefaultParam\n                                          defaultValue,\n                                          `endif\n                                          sys_clk1_300_p, sys_clk1_300_n);\n   Clock sys_clk1_300mhz_buf <- mkClockBUFG(clocked_by sys_clk1_300mhz);\n   \n   Clock sys_clk2_300mhz <- mkClockIBUFDS(\n                                          `ifdef ClockDefaultParam\n                                          defaultValue,\n                                          `endif\n                                          sys_clk2_300_p, sys_clk2_300_n);\n   Clock sys_clk2_300mhz_buf <- mkClockBUFG(clocked_by sys_clk2_300mhz);\n  `endif // VirtexUltrascale\n`endif // VirtexUltrascalePlus\n`endif // XILINX_SYS_CLK\n   \n   GTE2ClockGenIfc clockGen <- mkClockIBUFDS_GTE(\n`ifdef ClockDefaultParam\n       defaultValue,\n`endif\n       True, pci_sys_clk_p, pci_sys_clk_n);\n`ifdef XilinxUltrascale\n   Clock pci_clk_100mhz_buf = clockGen.gen_clk2;\n`else\n   Clock pci_clk_100mhz_buf = clockGen.gen_clk;\n`endif\n   \n   let pci_sys_reset_n_c <- mkResetIBUF(defaultValue, reset_by pci_sys_reset_n);\n   // Instantiate the PCIE endpoint\n   PcieEndpointX7#(PcieLanes) ep7 <- mkPcieEndpointX7(\n`ifdef PCIE3\n      clockGen.gen_clk,\n`endif\n      clocked_by pci_clk_100mhz_buf, reset_by pci_sys_reset_n_c);\n\n   Clock pcieClock_ = ep7.epPcieClock;\n   Reset pcieReset_ = ep7.epPcieReset;\n   PcieHost#(PcieDataBusWidth, NumberOfMasters) pciehost <- mkPcieHost(\n`ifdef PCIE3\n         PciId{bus: 0, dev: 0, func:0},\n`else\n         PciId{ bus:  ep7.cfg.bus_number(), dev: ep7.cfg.device_number(), func: ep7.cfg.function_number()},\n`endif\n         clocked_by pcieClock_, reset_by pcieReset_);\n`ifdef PCIE3\n   mkConnection(ep7.tlpr, pciehost.pcir, clocked_by pcieClock_, reset_by pcieReset_);\n   mkConnection(ep7.tlpc, pciehost.pcic, clocked_by pcieClock_, reset_by pcieReset_);\n`ifndef PCIE_CHANGES_HOSTIF\n   mkConnection(ep7.regChanges, pciehost.changes);\n`endif\n   let ipciehost = (interface PcieHost;\n\t\t    interface msixEntry = pciehost.msixEntry;\n\t\t    interface master = pciehost.master;\n\t\t    interface slave = pciehost.slave;\n\t\t    interface pcir = pciehost.pcir;\n\t\t    interface pcic = pciehost.pcic;\n\t\t    interface trace = pciehost.trace;\n\t\t    interface interruptRequest = ep7.interruptRequest;\n\t\t    endinterface);\n`else\n   mkConnection(ep7.tlp, pciehost.pci, clocked_by pcieClock_, reset_by pcieReset_);\n`ifndef PCIE_CHANGES_HOSTIF\n   mkConnection(ep7.regChanges, pciehost.changes, clocked_by pcieClock_, reset_by pcieReset_);\n`endif\n   let ipciehost = pciehost;\n`endif\n\n`ifdef XILINX_SYS_CLK\n   interface Clock tsys_clk_200mhz = sys_clk_200mhz;\n   interface Clock tsys_clk_200mhz_buf = sys_clk_200mhz_buf;\n `ifdef VirtexUltrascalePlus\n   interface Clock tsys_clk_300mhz      = sys_clk_300mhz;\n   interface Clock tsys_clk_300mhz_buf  = sys_clk_300mhz_buf;\n   interface Clock tsys_clk1_250mhz     = sys_clk1_250mhz;\n   interface Clock tsys_clk1_250mhz_buf = sys_clk1_250mhz_buf;\n   interface Clock tsys_clk2_250mhz     = sys_clk2_250mhz;\n   interface Clock tsys_clk2_250mhz_buf = sys_clk2_250mhz_buf;\n `else\n  `ifdef VirtexUltrascale\n   interface Clock tsys_clk1_300mhz = sys_clk1_300mhz;\n   interface Clock tsys_clk1_300mhz_buf = sys_clk1_300mhz_buf;\n   interface Clock tsys_clk2_300mhz = sys_clk2_300mhz;\n   interface Clock tsys_clk2_300mhz_buf = sys_clk2_300mhz_buf;\n  `endif // VirtexUltrascale\n `endif // VirtexUltrascalePlus\n`endif // XILINX_SYS_CLK\n   interface Clock tpci_clk_100mhz_buf = pci_clk_100mhz_buf;\n\n   interface PcieEndpointX7 tep7 = ep7;\n   interface PcieHost tpciehost = ipciehost;\n`ifdef PCIE_CHANGES_HOSTIF\n   interface PipeOut tchanges = ep7.regChanges;\n`endif\n\n   interface pcieClock = ep7.epPcieClock;\n   interface pcieReset = ep7.epPcieReset;\n   interface portalClock = ep7.epPortalClock;\n   interface portalReset = ep7.epPortalReset;\n   interface derivedClock = ep7.epDerivedClock;\n   interface derivedReset = ep7.epDerivedReset;\nendmodule\n`endif\n\n`ifdef ALTERA\n`define ALTERA_TOP\n`endif\n\n`ifdef ALTERA_TOP\n(* no_default_clock, no_default_reset *)\nmodule mkAlteraPcieHostTop #(Clock clk_100MHz, Clock clk_50MHz, Reset perst_n)(PcieHostTop);\n\n   PcieEndpointS5#(PcieLanes) ep7 <- mkPcieEndpointS5(clk_100MHz, clk_50MHz, perst_n, clocked_by clk_100MHz, reset_by perst_n);\n\n   Clock epPcieClock = ep7.epPcieClock;\n   Reset epPcieReset = ep7.epPcieReset;\n\n   Clock portalClock_ = epPcieClock;\n   Reset portalReset_ = epPcieReset;\n\n   PcieHost#(PcieDataBusWidth, NumberOfMasters) pciehost <- mkPcieHost(ep7.device, clocked_by portalClock_, reset_by portalReset_);\n   mkConnection(ep7.tlp, pciehost.pci, clocked_by portalClock_, reset_by portalReset_);\n\n   interface PcieEndpointS5 tep7 = ep7;\n   interface PcieHost tpciehost = pciehost;\n\n   interface Clock pcieClock = epPcieClock;\n   interface Reset pcieReset = epPcieReset;\n   interface portalClock = portalClock_;\n   interface portalReset = portalReset_;\n   interface derivedClock = ep7.epDerivedClock;\n   interface derivedReset = ep7.epDerivedReset;\n\nendmodule\n`endif\n\n`ifdef SIMULATION\nmodule mkPcieHostTop #(Clock pci_sys_clk_p, Clock pci_sys_clk_n, `SYS_CLK_PARAM Reset pci_sys_reset_n)(PcieHostTop);\n   (* hide *)\n   PcieHostTop pcieHostTop <- mkBsimPcieHostTop(pci_sys_clk_p, pci_sys_clk_n, `SYS_CLK_ARG pci_sys_reset_n);\n   return pcieHostTop;\nendmodule\n`elsif XILINX // XILINX\n//(* synthesize, no_default_clock, no_default_reset *)\n(* no_default_clock, no_default_reset *)\nmodule mkPcieHostTop #(Clock pci_sys_clk_p, Clock pci_sys_clk_n, `SYS_CLK_PARAM Reset pci_sys_reset_n)(PcieHostTop);\n   (* hide *)\n   PcieHostTop pcieHostTop <- mkXilinxPcieHostTop(pci_sys_clk_p, pci_sys_clk_n, `SYS_CLK_ARG pci_sys_reset_n);\n   return pcieHostTop;\nendmodule\n`elsif ALTERA_TOP\n//(* synthesize, no_default_clock, no_default_reset *)\n(* no_default_clock, no_default_reset *)\nmodule mkPcieHostTop #(Clock clk_100MHz, Clock clk_50MHz, Reset perst_n)(PcieHostTop);\n   (* hide *)\n   PcieHostTop pcieHostTop <- mkAlteraPcieHostTop(clk_100MHz, clk_50MHz, perst_n);\n   return pcieHostTop;\nendmodule\n`endif // NOT ALTERA\n"
  },
  {
    "path": "bsv/PcieRootDevice.bsv",
    "content": "// Copyright (c) 2015 Connectal Project\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\nimport GetPut::*;\nimport Connectable::*;\n\ninterface PcieRoot#(numeric type n);\n   interface Get#(TLPData#(n)) fromRoot;\n   interface Put#(TLPData#(n)) toRoot;\nendinterface\n\ninterface PcieDevice#(numeric type n);\n   interface Put#(TLPData#(n)) fromRoot;\n   interface Get#(TLPData#(n)) toRoot;\nendinterface\n\ninstance Connectable#(PcieRoot#(n),PcieDevice#(n));\n   module mkConnection(PcieRoot#(n) r, PcieDevice#(n) d);\n      mkConnection(r.fromRoot, d.fromRoot);\n      mkConnection(r.toRoot, d.toRoot);\n   endmodule\nendinstance\n"
  },
  {
    "path": "bsv/PcieRootPortX7.bsv",
    "content": "\n// Copyright (c) 2013-2015 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\npackage PcieRootPortX7;\n\nimport Clocks            ::*;\nimport Vector            ::*;\nimport Connectable       ::*;\nimport GetPut            ::*;\nimport Reserved          ::*;\nimport TieOff            ::*;\nimport DefaultValue      ::*;\nimport DReg              ::*;\nimport Gearbox           ::*;\nimport FIFO              ::*;\nimport FIFOF             ::*;\nimport SpecialFIFOs      ::*;\nimport ClientServer      ::*;\nimport Real              ::*;\n\nimport ConnectalClocks   ::*;\nimport ConnectalXilinxCells   ::*;\nimport XilinxCells       ::*;\nimport PCIE              ::*;\nimport PCIEWRAPPER       ::*;\nimport Bufgctrl           ::*;\n\n////////////////////////////////////////////////////////////////////////////////\n/// Interfaces\n////////////////////////////////////////////////////////////////////////////////\n\ninterface PcieRootPortX7#(numeric type lanes);\n   interface PciewrapPci_exp#(lanes)   pcie;\n   interface PciewrapUser#(lanes)      user;\n   interface PciewrapCfg#(lanes)       cfg;\n   interface Server#(TLPData#(16), TLPData#(16)) tlp;\n   interface Clock portalClock;\n   interface Reset portalReset;\n   interface Clock epDerivedClock;\n   interface Reset epDerivedReset;\nendinterface\n\ntypedef struct {\n   Bit#(22)      user;\n   Bit#(1)       last;\n   Bit#(16)      keep;\n   Bit#(128)     data;\n} AxiRx deriving (Bits, Eq);\n\ntypedef struct {\n   Bit#(1)       last;\n   Bit#(16)      keep;\n   Bit#(128)     data;\n} AxiTx deriving (Bits, Eq);\n\n(* synthesize *)\nmodule mkPcieRootPortX7(PcieRootPortX7#(PcieLanes));\n\n   Clock defaultClock <- exposeCurrentClock();\n   Reset defaultReset <- exposeCurrentReset();\n\n   PcieWrap#(PcieLanes) pcie_ep <- mkPcieWrap(defaultClock, defaultReset);\n\n   Clock user_clk = pcie_ep.user_clk_out;\n   Reset user_reset_n <- mkResetInverter(pcie_ep.user_reset_out, clocked_by user_clk);\n\n   FIFOF#(AxiTx)             fAxiTx              <- mkFIFOF(clocked_by user_clk, reset_by user_reset_n);\n   FIFOF#(AxiRx)             fAxiRx              <- mkFIFOF(clocked_by user_clk, reset_by user_reset_n);\n\n   (* fire_when_enabled, no_implicit_conditions *)\n   rule every1;\n      pcie_ep.fc.sel(0 /*RECEIVE_BUFFER_AVAILABLE_SPACE*/);\n      pcie_ep.cfg_dsn({ 32'h0000_0001, {{ 8'h1 } , 24'h000A35 }});\n      pcie_ep.rx.np_ok(1);\n      pcie_ep.rx.np_req(1);\n      pcie_ep.tx.cfg_gnt(1);\n      pcie_ep.s_axis_tx.tuser(4'b0);\n      pcie_ep.m_axis_rx.tready(pack(fAxiRx.notFull));\n   endrule\n   rule every_cfg_err;\n      pcie_ep.cfg_err.acs(0);\n      pcie_ep.cfg_err.aer_headerlog(0);\n      pcie_ep.cfg_err.atomic_egress_blocked(0);\n      pcie_ep.cfg_err.cor(0);\n      pcie_ep.cfg_err.cpl_abort(0);\n      pcie_ep.cfg_err.cpl_timeout(0);\n      pcie_ep.cfg_err.cpl_unexpect(0);\n      pcie_ep.cfg_err.ecrc(0);\n      pcie_ep.cfg_err.internal_cor(0);\n      pcie_ep.cfg_err.internal_uncor(0);\n      pcie_ep.cfg_err.locked(0);\n      pcie_ep.cfg_err.malformed(0);\n      pcie_ep.cfg_err.mc_blocked(0);\n      pcie_ep.cfg_err.norecovery(0);\n      pcie_ep.cfg_err.poisoned(0);\n      pcie_ep.cfg_err.posted(0);\n      pcie_ep.cfg_err.tlp_cpl_header(0);\n      pcie_ep.cfg_err.ur(0);\n   endrule\n   rule every_interrupt;\n      pcie_ep.cfg_interrupt.zzassert(0);\n      pcie_ep.cfg_interrupt.di(0);\n      pcie_ep.cfg_interrupt.stat(0);\n   endrule\n   rule every_mgmt;\n      pcie_ep.cfg_mgmt.byte_en(0);\n      pcie_ep.cfg_mgmt.di(0);\n      pcie_ep.cfg_mgmt.dwaddr(0);\n      pcie_ep.cfg_mgmt.rd_en(0);\n      pcie_ep.cfg_mgmt.wr_en(0);\n      pcie_ep.cfg_mgmt.wr_readonly(0);\n   endrule\n   rule every_pm;\n      pcie_ep.cfg_pm.force_state(0);\n      pcie_ep.cfg_pm.force_state_en(0);\n      pcie_ep.cfg_pm.halt_aspm_l0s(0);\n      pcie_ep.cfg_pm.halt_aspm_l1(0);\n      pcie_ep.cfg_pm.send_pme_to(0);\n      pcie_ep.cfg_pm.wake(0);\n   endrule\n   rule every_pl;\n      pcie_ep.pl.directed_link_auton(0);\n      pcie_ep.pl.directed_link_change(0);\n      pcie_ep.pl.directed_link_speed(0);\n      pcie_ep.pl.directed_link_width(0);\n      pcie_ep.pl.downstream_deemph_source(0);\n      pcie_ep.pl.transmit_hot_rst(0);\n      pcie_ep.pl.upstream_prefer_deemph(1);\n   endrule\n\n   let txready = (pcie_ep.s_axis_tx.tready == 1 && fAxiTx.notEmpty);\n\n   (* fire_when_enabled *)\n   rule drive_axi_tx if (txready);\n      let info = unpack(0);\n      if (fAxiTx.notEmpty) begin\n\t info <- toGet(fAxiTx).get();\n      end\n      pcie_ep.s_axis_tx.tlast(info.last);\n      pcie_ep.s_axis_tx.tdata(info.data);\n      pcie_ep.s_axis_tx.tkeep(info.keep);\n   endrule\n   (* fire_when_enabled, no_implicit_conditions *)\n   rule drive_axi_txvalid if (fAxiTx.notEmpty);\n      pcie_ep.s_axis_tx.tvalid(1);\n   endrule\n   (* fire_when_enabled, no_implicit_conditions *)\n   rule drive_axi_tx2 if (!fAxiTx.notEmpty);\n      pcie_ep.s_axis_tx.tvalid(0);\n      pcie_ep.s_axis_tx.tlast(0);\n      pcie_ep.s_axis_tx.tdata(0);\n      pcie_ep.s_axis_tx.tkeep(0);\n   endrule\n\n   (* fire_when_enabled *)\n   rule sink_axi_rx if (pcie_ep.m_axis_rx.tvalid == 1);\n      fAxiRx.enq(AxiRx {user: pcie_ep.m_axis_rx.tuser,\n                        last: pcie_ep.m_axis_rx.tlast,\n                        keep: pcie_ep.m_axis_rx.tkeep,\n                        data: pcie_ep.m_axis_rx.tdata });\n   endrule\n\n   Reset user_reset <- mkSyncReset(5, user_reset_n, user_clk);\n\n   ClockGenerator7Params     clkgenParams = defaultValue;\n   clkgenParams.clkin1_period    = 4.000; //  250MHz\n   clkgenParams.clkin_buffer     = False;\n   clkgenParams.clkfbout_mult_f  = 4.000; // 1000MHz\n   clkgenParams.clkout0_divide_f = 4.000; //  250MHz\n   clkgenParams.clkout1_divide     = round(derivedClockPeriod);\n   clkgenParams.clkout1_duty_cycle = 0.5;\n   clkgenParams.clkout1_phase      = 0.0000;\n   ClockGenerator7           clkgen <- mkClockGenerator7(clkgenParams, clocked_by user_clk, reset_by user_reset_n);\n   Clock derivedClock = clkgen.clkout1;\n   Reset derivedReset <- mkSyncReset(5, user_reset_n, derivedClock);\n\n   Server#(TLPData#(16), TLPData#(16)) tlp16 = (interface Server;\n\t\t\t\t\t\tinterface Put request;\n\t\t\t\t\t\t   method Action put(TLPData#(16) data);\n\t\t\t\t\t\t      fAxiTx.enq(AxiTx {last: pack(data.eof),\n\t\t\t\t\t\t\t\t\tkeep: dwordSwap128BE(data.be), data: dwordSwap128(data.data) });\n\t\t\t\t\t\t   endmethod\n\t\t\t\t\t\tendinterface\n\t\t\t\t\t\tinterface Get response;\n\t\t\t\t\t\t   method ActionValue#(TLPData#(16)) get();\n\t\t\t\t\t\t      let info <- toGet(fAxiRx).get;\n\t\t\t\t\t\t      TLPData#(16) retval = defaultValue;\n\t\t\t\t\t\t      retval.sof  = (info.user[14] == 1);\n\t\t\t\t\t\t      retval.eof  = info.last != 0;\n\t\t\t\t\t\t      retval.hit  = info.user[8:2];\n\t\t\t\t\t\t      retval.be= dwordSwap128BE(info.keep);\n\t\t\t\t\t\t      retval.data = dwordSwap128(info.data);\n\t\t\t\t\t\t      return retval;\n\t\t\t\t\t\t   endmethod\n\t\t\t\t\t\tendinterface\n\t\t\t\t\t     endinterface);\n\n   interface Clock portalClock = user_clk;\n   interface Reset portalReset = user_reset_n;\n   interface tlp = tlp16;\n   interface pcie    = pcie_ep.pci_exp;\n   interface PciewrapUser user = pcie_ep.user;\n   interface PciewrapCfg cfg = pcie_ep.cfg;\n   interface Clock epDerivedClock = derivedClock;\n   interface Reset epDerivedReset = derivedReset;\nendmodule: mkPcieRootPortX7\n\nendpackage: PcieRootPortX7\n"
  },
  {
    "path": "bsv/PcieSplitter.bsv",
    "content": "\n// Copyright (c) 2008- 2009 Bluespec, Inc.  All rights reserved.\n// $Revision$\n// $Date$\n// Copyright (c) 2013 Quanta Research Cambridge, Inc.\n\n// PCI-Express for Xilinx 7\n// FPGAs.\n\npackage PcieSplitter;\n\n// This is a package which acts as a bridge between a TLP-based PCIe\n// interface on one side and an AXI slave (portal) and AXI Master on\n// the other.\n\nimport GetPut       :: *;\nimport Connectable  :: *;\nimport Vector       :: *;\nimport FIFO         :: *;\nimport FIFOF        :: *;\nimport Counter      :: *;\nimport PCIE         :: *;\nimport Clocks       :: *;\nimport ClientServer :: *;\n\nInteger portConfig = 0;\nInteger portPortal = 1;\nInteger portInterrupt = 2;\nInteger portAxi    = 3;\ntypedef 4 PortMax;\n\n// When TLP packets come in from the PCIe bus, they are dispatched to\n// either the configuration register block, the portal (AXI slave) or\n// the AXI master.\ninterface TLPDispatcher;\n   // TLPs in from PCIe\n   interface Put#(TLPData#(16)) inFromBus;\n   // TLPs out to the bridge implementation\n   interface Vector#(PortMax, Get#(TLPData#(16))) out;\nendinterface: TLPDispatcher\n\ntypedef function Bool tlpMatchFunction(TLPData#(16) tlp, TLPMemoryIO3DWHeader hdr_3dw) TlpMatchFunction;\n\n(* synthesize *)\nmodule mkTLPDispatcher(TLPDispatcher);\n   FIFO#(TLPData#(16))  tlp_in_fifo     <- mkFIFO();\n   Vector#(PortMax, FIFOF#(TLPData#(16))) tlp_out_fifo <- replicateM(mkGFIFOF(True,False)); // unguarded enq\n   Reg#(Maybe#(Bit#(TLog#(PortMax)))) routeToPort <- mkReg(tagged Invalid);\n   Vector#(PortMax, TlpMatchFunction) matchFunctions = newVector;\n\n   function Bool configMatch(TLPData#(16) tlp, TLPMemoryIO3DWHeader hdr_3dw);\n      return tlp.hit == 7'h01 &&\n             pack(hdr_3dw.r1) == 0 && // not a TLP Prefix\n          (hdr_3dw.format == MEM_READ_3DW_NO_DATA /* read */\n        || (hdr_3dw.format == MEM_WRITE_3DW_DATA && hdr_3dw.pkttype != COMPLETION)); /* write */\n   endfunction\n\n   function Bool axiMatch(TLPData#(16) tlp, TLPMemoryIO3DWHeader hdr_3dw);\n      return tlp.hit == 7'h04 &&\n             pack(hdr_3dw.r1) == 0 && // not a TLP Prefix\n          (hdr_3dw.format == MEM_READ_3DW_NO_DATA /* read */\n        || (hdr_3dw.format == MEM_WRITE_3DW_DATA && hdr_3dw.pkttype != COMPLETION)); /* write */\n   endfunction\n\n   function Bool axiCompletionMatch(TLPData#(16) tlp, TLPMemoryIO3DWHeader hdr_3dw);\n      return (pack(hdr_3dw.r1) == 0) && // not a TLP Prefix\n              hdr_3dw.format == MEM_WRITE_3DW_DATA && hdr_3dw.pkttype == COMPLETION;\n   endfunction\n\n   matchFunctions[portConfig] = configMatch;\n   matchFunctions[portPortal] = axiMatch;\n   matchFunctions[portAxi]    = axiCompletionMatch;\n\n   (* fire_when_enabled *)\n   rule dispatch_incoming_TLP;\n      TLPData#(16) tlp = tlp_in_fifo.first();\n      TLPMemoryIO3DWHeader hdr_3dw = unpack(tlp.data);\n\n      if (tlp.sof) begin\n\t Bool matched = False;\n         // route the packet based on this header\n\t for (Integer port = 0; port < valueOf(PortMax); port = port+1)\n            if (!matched && matchFunctions[port](tlp, hdr_3dw)) begin\n\t       matched = True;\n               if (tlp_out_fifo[port].notFull()) begin\n\t\t  tlp_in_fifo.deq();\n\t\t  tlp_out_fifo[port].enq(tlp);\n\t\t  if (!tlp.eof)\n                     routeToPort <= tagged Valid fromInteger(port);\n               end\n            end\n         if (!matched) begin\n            // unknown packet type -- just discard it\n            tlp_in_fifo.deq();\n         end\n      end\n      else if (routeToPort matches tagged Valid .port) begin\n         if (tlp_out_fifo[port].notFull()) begin\n            tlp_in_fifo.deq();\n            tlp_out_fifo[port].enq(tlp);\n            if (tlp.eof)\n               routeToPort <= tagged Invalid;\n         end\n      end\n      else begin\n         // unknown packet type -- just discard it\n         tlp_in_fifo.deq();\n      end\n   endrule: dispatch_incoming_TLP\n\n   Vector#(PortMax, Get#(TLPData#(16))) outtemp;\n   for (Integer i = 0; i < valueOf(PortMax); i=i+1)\n       outtemp[i] = toGet(tlp_out_fifo[i]);\n   interface out = outtemp;\n   interface Put inFromBus    = toPut(tlp_in_fifo);\nendmodule: mkTLPDispatcher\n\n// Multiple sources of TLP packets must all share the PCIe bus. There\n// is an arbiter which controls which source gets access to the PCIe\n// endpoint.\n\ninterface TLPArbiter;\n   // TLPs out to PCIe\n   interface Get#(TLPData#(16)) outToBus;\n   // TLPs in from the bridge implementation\n   interface Vector#(PortMax, Put#(TLPData#(16))) in;\nendinterface: TLPArbiter\n\n(* synthesize *)\nmodule mkTLPArbiter(TLPArbiter);\n   FIFO#(TLPData#(16))  tlp_out_fifo     <- mkFIFO();\n   Vector#(PortMax, FIFOF#(TLPData#(16))) tlp_in_fifo <- replicateM(mkGFIFOF(False,True)); // unguarded deq\n   Reg#(Maybe#(Bit#(TLog#(PortMax)))) routeFrom <- mkReg(tagged Invalid);\n\n   (* fire_when_enabled *)\n   rule arbitrate_outgoing_TLP;\n      if (routeFrom matches tagged Valid .port) begin\n         if (tlp_in_fifo[port].notEmpty()) begin\n            TLPData#(16) tlp <- toGet(tlp_in_fifo[port]).get();\n            tlp_out_fifo.enq(tlp);\n            if (tlp.eof)\n               routeFrom <= tagged Invalid;\n         end\n      end\n      else begin\n\t Bool sentOne = False;\n\t for (Integer port = 0; port < valueOf(PortMax); port = port+1) begin\n\t    if (!sentOne && tlp_in_fifo[port].notEmpty()) begin\n               TLPData#(16) tlp <- toGet(tlp_in_fifo[port]).get();\n\t       sentOne = True;\n               if (tlp.sof) begin\n\t\t  tlp_out_fifo.enq(tlp);\n\t\t  if (!tlp.eof)\n\t\t     routeFrom <= tagged Valid fromInteger(port);\n               end\n\t    end\n\t end\n      end\n   endrule: arbitrate_outgoing_TLP\n\n   Vector#(PortMax, Put#(TLPData#(16))) intemp;\n   for (Integer i = 0; i < valueOf(PortMax); i=i+1)\n       intemp[i] = toPut(tlp_in_fifo[i]);\n   interface in = intemp;\n   interface Get outToBus     = toGet(tlp_out_fifo);\nendmodule\n\nendpackage: PcieSplitter\n"
  },
  {
    "path": "bsv/PcieStateChanges.bsv",
    "content": "// Copyright (c) 2015 Connectal Project\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\nimport FIFOF             ::*;\nimport Probe             ::*;\n\nimport Pipe              ::*;\n\ntypedef enum {\n   PcieCfg_none,\n   PcieCfg_current_speed,\n   PcieCfg_dpa_substate_change,\n   PcieCfg_err_cor_out,\n   PcieCfg_err_fatal_out,\n   PcieCfg_err_nonfatal_out,\n   PcieCfg_flr_in_process,\n   PcieCfg_function_power_state,\n   PcieCfg_function_status,\n   PcieCfg_hot_reset_out,\n   PcieCfg_link_power_state,\n   PcieCfg_ltr_enable,\n   PcieCfg_ltssm_state,\n   PcieCfg_max_payload,\n   PcieCfg_max_read_req,\n   PcieCfg_negotiated_width,\n   PcieCfg_obff_enable,\n   PcieCfg_phy_link_down,\n   PcieCfg_phy_link_status,\n   PcieCfg_pl_status_change,\n   PcieCfg_power_state_change_interrupt,\n   PcieCfg_rcb_status,\n   PcieCfg_rq_backpressure,\n   PcieCfg_initial_link_width,\n   PcieCfg_lane_reversal_mode,\n   PcieCfg_phy_link_up,\n   PcieCfg_received_hot_rst,\n   PcieCfg_rx_pm_state,\n   PcieCfg_sel_lnk_rate,\n   PcieCfg_tx_pm_state,\n   PcieCfg_link_gen2_cap,\n   PcieCfg_link_partner_gen2_supported,\n   PcieCfg_link_up\n   } PcieCfgType deriving (Bits,Eq);\n\ntypedef struct {\n   Bit#(32) timestamp;\n   Bit#(8) src;\n   Bit#(24) value;\n} RegChange deriving (Bits);\n\nmodule mkChangeSource#(Reg#(Bit#(32)) cyclesReg, Tuple2#(PcieCfgType,Bit#(24)) tpl)(PipeOut#(RegChange));\n   match { .src, .v } = tpl;\n   Reg#(Bit#(24))    snapshot <- mkReg(0);\n   FIFOF#(RegChange) changeFifo <- mkFIFOF1();\n   rule rl_update if (v != snapshot);\n      if (changeFifo.notFull) begin\n\t changeFifo.enq(RegChange { timestamp: cyclesReg, src: extend(pack(src)), value: extend(v) });\n\t snapshot <= v;\n      end\n   endrule\n   return toPipeOut(changeFifo);\nendmodule\n"
  },
  {
    "path": "bsv/PcieToMem.bsv",
    "content": "// Copyright (c) 2013 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\nimport FIFOF        :: *;\nimport Vector       :: *;\nimport GetPut       :: *;\nimport Connectable  :: *;\nimport MIMO         :: *;\nimport PCIE         :: *;\nimport DefaultValue :: *;\nimport ClientServer :: *;\nimport ConnectalMemTypes     :: *;\nimport ConnectalConfig::*;\n\n`include \"ConnectalProjectConfig.bsv\"\n\n//\n// Top interface: PCIe transaction level packets (TLPs)\n// Bottom interface: MemMaster that sends read/write requests to an MemSlave\n// Also sources interrupt MSIX requests\ninterface PcieToMem;\n    interface Client#(TLPData#(16), TLPData#(16)) tlp;\n    interface PhysMemMaster#(32,32) master;\nendinterface\n\n`ifdef XILINX\n   `define AXI\n`elsif SIMULATION\n   `define AXI\n`elsif ALTERA\n   `define AVALON\n`elsif VSIM\n   `define AVALON\n`endif\n\n\n(* synthesize *)\nmodule mkPcieToMem#(PciId my_id)(PcieToMem);\n\n    let verbose = False;\n\n    Reg#(Bit#(7)) hitReg <- mkReg(0);\n    FIFOF#(TLPMemoryIO3DWHeader) readHeaderFifo <- mkSizedFIFOF(8);\n    FIFOF#(TLPMemoryIO3DWHeader) readDataFifo <- mkSizedFIFOF(8);\n    FIFOF#(TLPMemoryIO3DWHeader) writeHeaderFifo <- mkSizedFIFOF(8);\n    FIFOF#(TLPMemoryIO3DWHeader) writeDataFifo <- mkSizedFIFOF(8);\n    FIFOF#(TLPData#(16)) tlpOutFifo <- mkSizedFIFOF(8);\n    Reg#(TLPTag) tlpTag <- mkReg(0);\n\n    MIMOConfiguration mimoCfg = defaultValue;\n    MIMO#(1,4,4,Bit#(32)) completionMimo <- mkMIMO(mimoCfg);\n   Reg#(TLPLength)             readBurstCount <- mkReg(0);\n   Reg#(LUInt#(4))     completionMimoDeqCount <- mkReg(0);\n   Reg#(Bool)      readBurstCountGreaterThan4 <- mkReg(False);\n   Reg#(Bool)                  readInProgress <- mkReg(False);\n   Reg#(Bit#(7))               address <- mkReg(0);\n\n   rule completionHeader if (!readInProgress && readDataFifo.notEmpty() && completionMimo.deqReadyN(1));\n      let hdr = readDataFifo.first;\n      TLPLength rbc = hdr.length;\n\n      Vector#(4, Bit#(32)) dvec = unpack(0);\n`ifdef AXI\n      dvec = completionMimo.first();\n      completionMimo.deq(1);\n`elsif AVALON\n      let quadWordAligned = isQuadWordAligned(getLowerAddr(hdr.addr, hdr.firstbe));\n      // if quad-word aligned, insert bubble.\n      if (!quadWordAligned) begin\n         dvec = completionMimo.first();\n         completionMimo.deq(1);\n      end\n`endif\n      if (verbose) $display(\"completionHeader length=%d rbc=%d addr=%x\", hdr.length, rbc, hdr.addr);\n      TLPCompletionHeader completion = defaultValue;\n      completion.format = MEM_WRITE_3DW_DATA;\n      completion.pkttype = COMPLETION;\n      completion.relaxed = hdr.relaxed;\n      completion.nosnoop = hdr.nosnoop;\n      completion.length = hdr.length;\n      completion.tclass = hdr.tclass;\n      completion.cmplid = my_id;\n      completion.tag = truncate(hdr.tag);\n      completion.bytecount = 4;\n      completion.reqid = hdr.reqid;\n      completion.loweraddr = getLowerAddr(hdr.addr, hdr.firstbe);\n`ifdef AXI\n      completion.data = byteSwap(dvec[0]);\n`elsif AVALON\n      if (!quadWordAligned) begin\n         completion.data = (dvec[0]);\n      end\n      else begin\n         completion.data = unpack(0);\n      end\n`endif\n      TLPData#(16) tlp = defaultValue;\n      tlp.data = pack(completion);\n      tlp.sof = True;\n\n`ifdef AXI\n      tlp.eof = (rbc == 1) ? True : False;\n`elsif AVALON\n      tlp.eof = (rbc == 1 && !quadWordAligned) ? True : False;\n`endif\n      tlp.be = 16'hFFFF;\n      tlp.hit = hitReg;\n      tlpOutFifo.enq(tlp);\n\n`ifdef AXI\n      rbc = rbc - 1;\n`elsif AVALON\n      if (!quadWordAligned) begin\n         rbc = rbc - 1;\n      end\n`endif\n      readBurstCount <= rbc;\n      completionMimoDeqCount <= truncate(min(4,unpack(rbc)));\n      readInProgress <= (rbc != 0);\n      readBurstCountGreaterThan4 <= (rbc > 4);\n      if (rbc == 0) begin\n\t readDataFifo.deq;\n      end\n   endrule\n\n    function Bit#(16) tlpBe(TLPLength len);\n       if (len == 0)\n\t  return 0;\n       else if (len == 1)\n\t  return 16'hf000;\n       else if (len == 2)\n\t  return 16'hff00;\n       else if (len == 3)\n\t  return 16'hfff0;\n       else\n\t  return 16'hffff;\n    endfunction\n\n   rule continuation if (readInProgress && completionMimo.deqReadyN(completionMimoDeqCount));\n      let rbc = readBurstCount;\n      TLPData#(16) tlp = defaultValue;\n      Vector#(4, Bit#(32)) dvec = unpack(0);\n      tlp.sof = False;\n      dvec = completionMimo.first();\n      completionMimo.deq(completionMimoDeqCount);\n\n      if (readBurstCountGreaterThan4) begin\n\t rbc = rbc - 4;\n\t tlp.be = tlpBe(4);\n\t tlp.eof = False;\n      end\n      else begin\n\t tlp.be = tlpBe(rbc);\n\t if (verbose) $display(\"tlp.data=%h tlp.be=%h\", tlp.data, tlp.be);\n\t tlp.eof = True;\n\t rbc = 0;\n      end\n\n      readBurstCount <= rbc;\n      completionMimoDeqCount <= truncate(min(4,unpack(rbc)));\n      readBurstCountGreaterThan4 <= (rbc > 4);\n      if (!readBurstCountGreaterThan4) begin\n\t readDataFifo.deq();\n\t readInProgress <= False;\n      end\n      for (Integer i = 0; i < 4; i = i + 1)\n`ifdef AXI\n\t tlp.data[(i+1)*32-1:i*32] = byteSwap(dvec[3-i]);\n`elsif AVALON\n\t tlp.data[(i+1)*32-1:i*32] = (dvec[3-i]);\n         tlp.hit = hitReg;\n`endif\n      tlpOutFifo.enq(tlp);\n   endrule\n\n    interface Client        tlp;\n    interface Put response;\n        method Action put(TLPData#(16) tlp);\n\t    if (verbose) $display(\"PcieToMem.put tlp=%h\", tlp);\n\t    TLPMemoryIO3DWHeader h = unpack(tlp.data);\n\t    hitReg <= tlp.hit;\n\t    TLPMemoryIO3DWHeader hdr_3dw = unpack(tlp.data);\n`ifdef AVALON\n            // For Altera, the position of payload in a 3DW TLP depends on alignment.\n            let quadWordAligned = isQuadWordAligned(getLowerAddr(hdr_3dw.addr, hdr_3dw.firstbe));\n`endif\n\t    if (tlp.sof && hdr_3dw.format == MEM_READ_3DW_NO_DATA) begin\n\t       if (readHeaderFifo.notFull())\n\t          readHeaderFifo.enq(hdr_3dw);\n\t       else begin\n\t\t  // FIXME: should generate a response or host will lock up\n\t       end\n\t    end\n\t    else begin\n               //FIXME: should rewrite to allow burst write.\n               if (tlp.sof && writeHeaderFifo.notFull()) begin\n\t\t  writeHeaderFifo.enq(hdr_3dw);\n               end\n\t    end\n\tendmethod\n    endinterface\n    interface Get request = toGet(tlpOutFifo);\n    endinterface: tlp\n    interface PhysMemMaster master;\n    interface PhysMemWriteClient write_client;\n        interface Get    writeReq;\n\t  method ActionValue#(PhysMemRequest#(32,32)) get();\n\t     let hdr = writeHeaderFifo.first;\n\t     writeHeaderFifo.deq;\n\t     writeDataFifo.enq(hdr);\n\t     let burstLen = extend(hdr.length << 2);\n             if (verbose) $display(\"burstLen = %h\", hdr.length << 2);\n\t     return PhysMemRequest { addr: extend(writeHeaderFifo.first.addr) << 2, burstLen: burstLen, tag: truncate(writeHeaderFifo.first.tag)\n`ifdef BYTE_ENABLES\n\t\t\t\t    , firstbe: maxBound, lastbe: maxBound\n`endif\n};\n\t  endmethod\n       endinterface\n        interface Get writeData;\n\t  method ActionValue#(MemData#(32)) get();\n\t     let hdr <- toGet(writeDataFifo).get();\n`ifdef AXI\n\t     let data = byteSwap(hdr.data);\n`elsif AVALON\n\t     let data = hdr.data;\n`endif\n\t     return MemData { data: data, tag: truncate(hdr.tag), last: True};\n\t  endmethod\n       endinterface\n        interface Put       writeDone;\n\t  method Action put(Bit#(MemTagSize) resp);\n\t  endmethod\n       endinterface\n     endinterface\n    interface PhysMemReadClient read_client;\n        interface Get    readReq;\n\t  method ActionValue#(PhysMemRequest#(32,32)) get();\n\t     let hdr = readHeaderFifo.first;\n\t     readHeaderFifo.deq;\n\t     //if (verbose) $display(\"req_ar hdr.length=%d hdr.addr=%h\", hdr.length, hdr.addr);\n\t     readDataFifo.enq(hdr);\n\t     let burstLen = extend(hdr.length << 2);\n\t     return PhysMemRequest { addr: extend(readHeaderFifo.first.addr) << 2, burstLen: burstLen, tag: truncate(readHeaderFifo.first.tag)\n`ifdef BYTE_ENABLES\n\t\t\t\t    , firstbe: maxBound, lastbe: maxBound\n`endif\n};\n\t    endmethod\n       endinterface\n        interface Put readData;\n\t  method Action put(MemData#(32) resp) if (completionMimo.enqReadyN(1));\n\t     Vector#(1, Bit#(32)) vec = cons(resp.data, nil);\n\t     completionMimo.enq(1, vec);\n\t  endmethod\n\tendinterface\n    endinterface\n    endinterface: master\nendmodule: mkPcieToMem\n\ninterface MemInterrupt;\n    interface Client#(TLPData#(16), TLPData#(16)) tlp;\n    interface Put#(Tuple2#(Bit#(64),Bit#(32))) interruptRequest;\n    interface Get#(Tuple2#(Bit#(64),Bit#(32))) interruptTrace;\nendinterface\n\ntypedef struct {\n   Bit#(64) addr;\n   Bit#(32) data;\n   Bool     mswIsZero;\n   Bool     lswIsZero;\n   } InterruptRequest deriving (Bits);\n\n(* synthesize *)\nmodule mkMemInterrupt#(PciId my_id)(MemInterrupt);\n    FIFOF#(InterruptRequest) interruptRequestFifo <- mkFIFOF();\n    FIFOF#(InterruptRequest) interruptTraceFifo <- mkSizedFIFOF(4);\n    Reg#(Maybe#(Bit#(32))) interruptSecondHalf <- mkReg(tagged Invalid);\n    Reg#(TLPTag) tlpTag <- mkReg(0);\n    FIFOF#(TLPData#(16)) tlpOutFifo <- mkSizedFIFOF(8);\n\n    function Bool isQuadWordAligned(Bit#(7) lower_addr);\n       return (lower_addr[2:0]==3'b0);\n    endfunction\n\n    rule interruptTlpOut if (interruptRequestFifo.notEmpty &&& interruptSecondHalf matches tagged Invalid);\n       TLPData#(16) tlp = defaultValue;\n       tlp.sof = True;\n       tlp.eof = False;\n       tlp.hit = 7'h00;\n       tlp.be = 16'hffff;\n\n       let deqInterruptRequestFifo = False;\n       let sendInterrupt = False;\n\n       let interruptRequest = interruptRequestFifo.first;\n       let interruptAddr = interruptRequest.addr;\n       let interruptData = interruptRequest.data;\n       let mswIsZero = interruptRequest.mswIsZero;\n       let lswIsZero = interruptRequest.lswIsZero;\n\n`ifdef AXI\n       let dataInSecondTlp = False;\n`elsif AVALON\n       let quadWordAligned = isQuadWordAligned(truncate(interruptAddr));\n       let dataInSecondTlp = quadWordAligned;\n`endif\n\n       if (mswIsZero && lswIsZero) begin\n\t  // do not write to 0 -- it wedges the host\n\t  deqInterruptRequestFifo = True;\n       end\n       else if (mswIsZero) begin\n          TLPMemoryIO3DWHeader hdr_3dw = defaultValue();\n          hdr_3dw.format = MEM_WRITE_3DW_DATA;\n\t  //hdr_3dw.pkttype = MEM_READ_WRITE;\n          hdr_3dw.tag = tlpTag;\n          hdr_3dw.reqid = my_id;\n          hdr_3dw.length = 1;\n          hdr_3dw.firstbe = '1;\n          hdr_3dw.lastbe = '0;\n          hdr_3dw.addr = interruptAddr[31:2];\n`ifdef AXI\n\t  hdr_3dw.data = byteSwap(interruptData);\n`elsif AVALON\n\t  hdr_3dw.data = interruptData;\n`endif\n\n\t  tlp.data = pack(hdr_3dw);\n          if (dataInSecondTlp) begin\n\t     tlp.eof = False;\n             interruptSecondHalf <= tagged Valid interruptData;\n          end\n\t  else begin\n\t     tlp.eof = True;\n\t     deqInterruptRequestFifo = True;\n\t  end\n\t  sendInterrupt = True;\n       end\n       else begin\n\t  TLPMemory4DWHeader hdr_4dw = defaultValue;\n\t  hdr_4dw.format = MEM_WRITE_4DW_DATA;\n\t  //hdr_4dw.pkttype = MEM_READ_WRITE;\n\t  hdr_4dw.tag = tlpTag;\n\t  hdr_4dw.reqid = my_id;\n\t  hdr_4dw.nosnoop = SNOOPING_REQD;\n\t  hdr_4dw.addr = interruptAddr[40-1:2];\n\t  hdr_4dw.length = 1;\n\t  hdr_4dw.firstbe = 4'hf;\n\t  hdr_4dw.lastbe = 0;\n\t  tlp.data = pack(hdr_4dw);\n\n\t  sendInterrupt = True;\n\t  interruptSecondHalf <= tagged Valid interruptData;\n       end\n\n       if (deqInterruptRequestFifo) begin\n\t  interruptRequestFifo.deq();\n       end\n       if (sendInterrupt)\n\t  tlpOutFifo.enq(tlp);\n    endrule\n\n    rule interruptTlpDataOut if (interruptSecondHalf matches tagged Valid .interruptData);\n       TLPData#(16) tlp = defaultValue;\n       tlp.sof = False;\n       tlp.eof = True;\n       tlp.hit = 7'h00;\n       tlp.be = 16'hf000;\n`ifdef AXI\n       tlp.data[7+8*15:8*12] = byteSwap(interruptData);\n`elsif AVALON\n       tlp.data[7+8*15:8*12] = interruptData;\n`endif\n       tlpOutFifo.enq(tlp);\n       interruptSecondHalf <= tagged Invalid;\n       interruptRequestFifo.deq();\n    endrule\n\n    interface Client        tlp;\n    interface Put response;\n        method Action put(TLPData#(16) tlp);\n\tendmethod\n    endinterface\n    interface Get request = toGet(tlpOutFifo);\n    endinterface: tlp\n    interface Put interruptRequest;\n       method Action put(Tuple2#(Bit#(64),Bit#(32)) intr);\n\t  match { .addr, .data } = intr;\n\t  Bool mswIsZero = (addr[63:32] == 0);\n\t  Bool lswIsZero = (addr[31:0] == 0);\n\t  let interruptRequest = InterruptRequest { addr: addr, data: data, mswIsZero: mswIsZero, lswIsZero: lswIsZero };\n          interruptRequestFifo.enq(interruptRequest);\n\t  if (interruptTraceFifo.notFull())\n\t      interruptTraceFifo.enq(interruptRequest);\n       endmethod\n    endinterface\n    interface Get interruptTrace;\n       method ActionValue#(Tuple2#(Bit#(64),Bit#(32))) get();\n           let req = interruptTraceFifo.first();\n           interruptTraceFifo.deq();\n\t   return tuple2(req.addr, req.data);\n       endmethod\n    endinterface\nendmodule: mkMemInterrupt\n"
  },
  {
    "path": "bsv/PcieTop.bsv",
    "content": "// Copyright (c) 2014 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\nimport Vector            :: *;\nimport Clocks            :: *;\nimport GetPut            :: *;\nimport FIFO              :: *;\nimport Connectable       :: *;\nimport ClientServer      :: *;\nimport DefaultValue      :: *;\n\nimport ConnectalConfig::*;\n`include \"ConnectalProjectConfig.bsv\"\nimport PcieSplitter      :: *;\nimport Xilinx            :: *;\nimport Portal            :: *;\nimport Top               :: *;\nimport PcieCsr           :: *;\nimport ConnectalMemTypes          :: *;\nimport Bscan             :: *;\nimport ConnectalClocks   :: *;\nimport GetPutWithClocks  :: *;\n`ifdef XILINX\n`ifdef PCIE3\n`ifdef XilinxUltrascale\nimport PCIEWRAPPER3u     ::*;\n`else\nimport PCIEWRAPPER3      :: *;\n`endif\nimport Pcie3EndpointX7   :: *;\n`endif\n`ifdef PCIE2\nimport PCIEWRAPPER2       :: *;\nimport Pcie2EndpointX7 :: *;\n`endif // pcie2\n`ifdef PCIE1\nimport PCIEWRAPPER       :: *;\nimport Pcie1EndpointX7   :: *;\n`endif // pcie2\n`elsif ALTERA\nimport PcieEndpointS5    :: *;\n`endif\nimport PcieHost          :: *;\nimport HostInterface     :: *;\nimport `PinTypeInclude::*;\nimport Platform          :: *;\n\n`ifndef DataBusWidth\n`define DataBusWidth 64\n`endif\n\n`ifdef XILINX_SYS_CLK\n `ifdef VirtexUltrascalePlus\n   `define SYS_CLK_PARAM Clock sys_clk_p, Clock sys_clk_n, Clock sys_clk_300_p, Clock sys_clk_300_n, Clock sys_clk1_250_p, Clock sys_clk1_250_n, Clock sys_clk2_250_p, Clock sys_clk2_250_n, \n   `define SYS_CLK_ARG sys_clk_p, sys_clk_n, sys_clk_300_p, sys_clk_300_n, sys_clk1_250_p, sys_clk1_250_n, sys_clk2_250_p, sys_clk2_250_n, \n `else\n   `ifdef VirtexUltrascale\n     `define SYS_CLK_PARAM Clock sys_clk_p, Clock sys_clk_n, Clock sys_clk1_300_p, Clock sys_clk1_300_n, Clock sys_clk2_300_p, Clock sys_clk2_300_n, \n     `define SYS_CLK_ARG sys_clk_p, sys_clk_n, sys_clk1_300_p, sys_clk1_300_n, sys_clk2_300_p, sys_clk2_300_n, \n   `else\n     `define SYS_CLK_PARAM Clock sys_clk_p, Clock sys_clk_n,\n     `define SYS_CLK_ARG sys_clk_p, sys_clk_n,\n   `endif\n  `endif\n`else\n  `define SYS_CLK_PARAM\n  `define SYS_CLK_ARG\n`endif\n\n// `ifdef XILINX_SYS_CLK\n// `ifdef VirtexUltrascale\n// `define SYS_CLK_PARAM Clock sys_clk_p, Clock sys_clk_n, Clock sys_clk1_300_p, Clock sys_clk1_300_n, Clock sys_clk2_300_p, Clock sys_clk2_300_n, \n// `define SYS_CLK_ARG sys_clk_p, sys_clk_n, sys_clk1_300_p, sys_clk1_300_n, sys_clk2_300_p, sys_clk2_300_n, \n// `else\n// `define SYS_CLK_PARAM Clock sys_clk_p, Clock sys_clk_n, \n// `define SYS_CLK_ARG sys_clk_p, sys_clk_n,\n// `endif\n// `else\n// `define SYS_CLK_PARAM\n// `define SYS_CLK_ARG\n// `endif\n\n\n(* synthesize, no_default_clock, no_default_reset *)\n`ifdef XILINX\nmodule mkPcieTop #(Clock pci_sys_clk_p, Clock pci_sys_clk_n, `SYS_CLK_PARAM Reset pci_sys_reset_n) (PcieTop#(`PinType));\n   PcieHostTop host <- mkPcieHostTop(pci_sys_clk_p, pci_sys_clk_n, `SYS_CLK_ARG pci_sys_reset_n);\n`elsif ALTERA\n(* clock_prefix=\"\", reset_prefix=\"\" *)\nmodule mkPcieTop #(Clock pcie_refclk_p, Clock osc_50_b3b, Reset pcie_perst_n) (PcieTop#(`PinType));\n   PcieHostTop host <- mkPcieHostTop(pcie_refclk_p, osc_50_b3b, pcie_perst_n);\n`endif\n   Vector#(NumberOfUserTiles,ConnectalTop#(`PinType)) tile <- replicateM(mkConnectalTop(\n`ifdef IMPORT_HOSTIF // no synthesis boundary\n      host,\n`else                // enables synthesis boundary\n`ifdef IMPORT_HOST_CLOCKS\n       host.derivedClock, host.derivedReset,\n`endif\n`endif\n       clocked_by host.portalClock, reset_by host.portalReset));\n   Platform portalTop <- mkPlatform(tile, clocked_by host.portalClock, reset_by host.portalReset);\n\n   if (mainClockPeriod == pcieClockPeriod) begin\n       mkConnection(host.tpciehost.master, portalTop.slave, clocked_by host.portalClock, reset_by host.portalReset);\n       if (valueOf(NumberOfMasters) > 0) begin\n          for ( Integer i = 0; i < valueOf(NumberOfMasters); i = i + 1) begin\n             `ifndef USE_WIDE_WIDTH\n\t         mkConnection(portalTop.masters[i], host.tpciehost.slave[i]);\n             `else\n             let memCnx <- GetPutWithClocks::mkConnectionWithGearbox(host.portalClock, host.portalReset,\n\t\t\t                                           host.pcieClock, host.pcieReset,\n\t\t\t                                           portalTop.masters[i], host.tpciehost.slave[i]);\n             `endif\n          end\n       end\n   end\n   else begin\n       let portalCnx <- GetPutWithClocks::mkConnectionWithClocks(host.pcieClock, host.pcieReset,\n\t\t\t\t\t\t\t\t host.portalClock, host.portalReset,\n\t\t\t\t\t\t\t\t host.tpciehost.master, portalTop.slave);\n      if (valueOf(NumberOfMasters) > 0) begin\n\t  //zipWithM_(GetPutWithClocks::mkConnectionWithClocks2, portalTop.masters, host.tpciehost.slave);\n\t     for (Integer i = 0; i < valueOf(NumberOfMasters); i = i + 1) begin\n            \n            `ifndef USE_WIDE_WIDTH\n\t        GetPutWithClocks::mkConnectionWithClocks(host.portalClock, host.portalReset,\n\t\t\t                                         host.pcieClock, host.pcieReset,\n\t\t\t                                         portalTop.masters[i], host.tpciehost.slave[i]);\n            `else\n            let memCnx <- GetPutWithClocks::mkConnectionWithGearbox(host.portalClock, host.portalReset,\n\t\t\t                                                        host.pcieClock, host.pcieReset,\n\t\t\t                                                        portalTop.masters[i], host.tpciehost.slave[i]);\n            `endif\n         end\n      end\n   end\n\n   // going from level to edge-triggered interrupt\n   FIFO#(Bit#(4)) intrFifo <- mkFIFO(clocked_by host.portalClock, reset_by host.portalReset);\n   //(8, host.portalClock, host.portalReset, host.pcieClock);\n   Vector#(16, Reg#(Bool)) interruptRequested <- replicateM(mkReg(False, clocked_by host.portalClock, reset_by host.portalReset));\n   rule interrupt_rule;\n     Maybe#(Bit#(4)) intr = tagged Invalid;\n     for (Integer i = 0; i < 16; i = i + 1) begin\n\t if (portalTop.interrupt[i] && !interruptRequested[i])\n             intr = tagged Valid fromInteger(i);\n\t interruptRequested[i] <= portalTop.interrupt[i];\n     end\n     if (intr matches tagged Valid .intr_num) begin\n\tintrFifo.enq(intr_num);\n     end\n   endrule\n   Put#(Bit#(4)) intrPut = (interface Put;\n      method Action put(Bit#(4) intr_num);\n\tReadOnly_MSIX_Entry msixEntry = host.tpciehost.msixEntry[intr_num];\n\thost.tpciehost.interruptRequest.put(tuple2({msixEntry.addr_hi, msixEntry.addr_lo}, msixEntry.msg_data));\n      endmethod\n      endinterface);\n\n   GetPutWithClocks::mkConnectionWithClocks(host.portalClock, host.portalReset,\n\t\t\t\t\t    host.pcieClock, host.pcieReset,\n\t\t\t\t\t    toGet(intrFifo),\n\t\t\t\t\t    intrPut);\n\n   interface pcie = host.tep7.pcie;\n   interface pins = portalTop.pins;\nendmodule\n\n"
  },
  {
    "path": "bsv/PcieTracer.bsv",
    "content": "// Copyright (c) 2014 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\nimport Vector            :: *;\nimport Clocks          :: *;\nimport GetPut            :: *;\nimport Connectable    :: *;\nimport FIFO              :: *;\nimport FIFOF        :: *;\nimport PCIE               :: *;\nimport BRAM         :: *;\nimport BramMux        :: *;\nimport ConnectalBram  ::*;\n\n`include \"ConnectalProjectConfig.bsv\"\n\n`ifdef PCIE_BSCAN\n`define PCIE_ALT_BRAM_SERVER\n`endif\n\ntypedef 11 TlpTraceAddrSize;\ntypedef TAdd#(TlpTraceAddrSize,1) TlpTraceAddrSize1;\n\ntypedef struct {\n    Bit#(32) timestamp;\n    Bit#(7) source;   // 4==frombus 8=tobus\n    TLPData#(16) tlp; // 153 bits\n} TimestampedTlpData deriving (Bits);\ntypedef SizeOf#(TimestampedTlpData) TimestampedTlpDataSize;\ntypedef SizeOf#(TLPData#(16)) TlpData16Size;\ntypedef SizeOf#(TLPCompletionHeader) TLPCompletionHeaderSize;\ninterface TlpTrace;\n   interface Get#(TimestampedTlpData) tlp;\nendinterface\n\ninterface TlpTraceServer;\n   interface Reg#(Bool)     tlpTracing;\n   interface Reg#(Bit#(TlpTraceAddrSize)) tlpTraceLimit;\n   interface Reg#(Bit#(TlpTraceAddrSize)) tlpTraceBramWrAddr;\n   interface BRAMServer#(Bit#(TAdd#(TlpTraceAddrSize,1)), TimestampedTlpData) bramServer;\n`ifdef PCIE_ALT_BRAM_SERVER\n   interface BRAMServer#(Bit#(TAdd#(TlpTraceAddrSize,1)), TimestampedTlpData) altBramServer;\n`endif\nendinterface\ninterface TlpTraceClient;\n   interface Reg#(Bool)     tlpTracing;\n   interface Reg#(Bit#(TlpTraceAddrSize)) tlpTraceLimit;\n   interface Reg#(Bit#(TlpTraceAddrSize)) tlpTraceBramWrAddr;\n   interface BRAMClient#(Bit#(TAdd#(TlpTraceAddrSize,1)), TimestampedTlpData) bramClient;\nendinterface\n\ninterface PcieTracer;\n   interface Client#(TLPData#(16), TLPData#(16)) pci;\n   interface Put#(TimestampedTlpData) trace;\n   interface Server#(TLPData#(16), TLPData#(16)) bus;\n   interface TlpTraceServer traceServer;\nendinterface: PcieTracer\n\n// The PCIe-to-AXI bridge puts all of the elements together\n(* synthesize *)\nmodule mkPcieTracer(PcieTracer);\n   // Trace Support\n   Reg#(Bool) tlpTracingReg        <- mkReg(False);\n   Reg#(Bit#(TlpTraceAddrSize)) tlpTraceLimitReg <- mkReg(0);\n   FIFOF#(Bit#(TlpTraceAddrSize)) tlpTraceBramWrAddrFifo <- mkFIFOF();\n   Reg#(Bit#(TlpTraceAddrSize)) tlpTraceBramWrAddrReg <- mkReg(0);\n   Integer memorySize = 2**valueOf(TlpTraceAddrSize);\n\n   BRAM_Configure bramCfg = defaultValue;\n   bramCfg.memorySize = memorySize;\n   bramCfg.latency = 1;\n`ifdef PCIE_ALT_BRAM_SERVER\n   BRAM2Port#(Bit#(TlpTraceAddrSize), TimestampedTlpData) fromPcieTraceBram <- ConnectalBram::mkBRAM2Server(bramCfg);\n   BRAM2Port#(Bit#(TlpTraceAddrSize), TimestampedTlpData) toPcieTraceBram <- ConnectalBram::mkBRAM2Server(bramCfg);\n`else\n   BRAM1Port#(Bit#(TlpTraceAddrSize), TimestampedTlpData) fromPcieTraceBram <- ConnectalBram::mkBRAM1Server(bramCfg);\n   BRAM1Port#(Bit#(TlpTraceAddrSize), TimestampedTlpData) toPcieTraceBram <- ConnectalBram::mkBRAM1Server(bramCfg);\n`endif\n   Vector#(2, BRAMServer#(Bit#(TlpTraceAddrSize), TimestampedTlpData)) bramServers;\n   bramServers[0] = fromPcieTraceBram.portA;\n   bramServers[1] =   toPcieTraceBram.portA;\n   Reg#(Bool) tlpNotTracingReg = (interface Reg;\n      method Bool _read(); return !tlpTracingReg; endmethod\n      method Action _write(Bool w); endmethod\n      endinterface);\n   BramServerMux#(TAdd#(TlpTraceAddrSize,1), TimestampedTlpData) bramMuxReg <- mkGatedBramServerMux(tlpNotTracingReg, bramServers);\n\n`ifdef PCIE_ALT_BRAM_SERVER\n   Vector#(2, BRAMServer#(Bit#(TlpTraceAddrSize), TimestampedTlpData)) altBramServers;\n   altBramServers[0] = fromPcieTraceBram.portB;\n   altBramServers[1] =   toPcieTraceBram.portB;\n   BramServerMux#(TAdd#(TlpTraceAddrSize,1), TimestampedTlpData) altBramMux <- mkBramServerMux(altBramServers);\n`endif\n\n   Reg#(Bit#(32)) timestamp <- mkReg(0);\n   rule incTimestamp;\n       timestamp <= timestamp + 1;\n   endrule\n//   rule endTrace if (tlpTracingReg && tlpTraceLimitReg != 0 && tlpTraceBramWrAddr > truncate(tlpTraceLimitReg));\n//       tlpTracingReg <= False;\n//   endrule\n\n   FIFO#(TLPData#(16)) tlpFromBusFifo <- mkFIFO();\n   FIFO#(TLPData#(16)) tlpToBusFifo <- mkFIFO();\n   FIFO#(TLPData#(16)) tlpBusResponseFifo <- mkFIFO();\n\n   Reg#(Bool) skippingIncomingTlps <- mkReg(False);\n   FIFO#(Bool) isRootBroadcastMessage <- mkFIFO();\n   PulseWire fromPcie <- mkPulseWire;\n   PulseWire   toPcie <- mkPulseWire;\n   Wire#(TLPData#(16)) fromPcieTlp <- mkDWire(unpack(0));\n   Wire#(TLPData#(16))   toPcieTlp <- mkDWire(unpack(0));\n\n   rule sniffTlpFromBus;\n      let tlp <- toGet(tlpFromBusFifo).get();\n      tlpBusResponseFifo.enq(tlp);\n\n      TLPMemoryIO3DWHeader hdr_3dw = unpack(tlp.data);\n      // skip root_broadcast_messages sent to tlp.hit 0\n      isRootBroadcastMessage.enq(tlp.sof && tlp.hit == 0 && hdr_3dw.pkttype != COMPLETION);\n\n   endrule\n\n   rule doTracing if (tlpTracingReg && (fromPcie || toPcie));\n      TimestampedTlpData fromttd = fromPcie ? TimestampedTlpData { timestamp: timestamp, source: 7'h04, tlp: fromPcieTlp } : unpack(0);\n      let writeAddr = tlpTraceBramWrAddrReg;\n      if (tlpTraceBramWrAddrFifo.notEmpty)\n\t writeAddr <- toGet(tlpTraceBramWrAddrFifo).get();\n\n      fromPcieTraceBram.portA.request.put(BRAMRequest{ write: True, responseOnWrite: False, address: writeAddr, datain: fromttd });\n\n      TimestampedTlpData   tottd = toPcie ? TimestampedTlpData { timestamp: timestamp, source: 7'h08, tlp: toPcieTlp } : unpack(0);\n      toPcieTraceBram.portA.request.put(BRAMRequest{ write: True, responseOnWrite: False, address: writeAddr, datain: tottd });\n\n      tlpTraceBramWrAddrReg <= writeAddr + 1;\n   endrule\n\n   interface Server     bus;\n      interface Get response;\n           method ActionValue#(TLPData#(16)) get();\n\t      let tlp <- toGet(tlpBusResponseFifo).get();\n\n\t      if (tlpTracingReg) begin\n\t\t if (tlp.sof && isRootBroadcastMessage.first) begin\n \t\t    skippingIncomingTlps <= True;\n\t\t end\n\t\t else if (skippingIncomingTlps && !tlp.sof) begin\n\t\t    // do nothing\n\t\t end\n\t\t else begin\n\t\t    fromPcie.send();\n\t\t    fromPcieTlp <= tlp;\n\t\t    skippingIncomingTlps <= False;\n\t\t end\n\t      end\n\n\t      isRootBroadcastMessage.deq();\n\t      return tlp;\n\t   endmethod\n      endinterface\n\n       interface Put request;\n           method Action put(TLPData#(16) tlp);\n           tlpToBusFifo.enq(tlp);\n           if (tlpTracingReg) begin\n\t      toPcie.send();\n\t      toPcieTlp <= tlp;\n           end\n           endmethod\n       endinterface\n   endinterface\n\n   interface Client    pci;\n      interface request = toGet(tlpToBusFifo);\n      interface response = toPut(tlpFromBusFifo);\n   endinterface\n   interface Put trace;\n       method Action put(TimestampedTlpData ttd) if (!fromPcie && !toPcie);\n\t   if (tlpTracingReg) begin\n\t       ttd.timestamp = timestamp;\n\t       toPcieTraceBram.portA.request.put(BRAMRequest{ write: True, responseOnWrite: False, address: truncate(tlpTraceBramWrAddrReg), datain: ttd });\n\t       tlpTraceBramWrAddrReg <= tlpTraceBramWrAddrReg + 1;\n\t   end\n       endmethod\n   endinterface: trace\n   interface TlpTraceServer traceServer;\n      interface Reg tlpTracing    = tlpTracingReg;\n      interface Reg tlpTraceLimit = tlpTraceLimitReg;\n      interface Reg tlpTraceBramWrAddr;\n\t method Bit#(TlpTraceAddrSize) _read(); return tlpTraceBramWrAddrReg; endmethod\n\t method Action _write(Bit#(TlpTraceAddrSize) v); tlpTraceBramWrAddrFifo.enq(v); endmethod\n      endinterface\n      interface Server bramServer = bramMuxReg.bramServer;\n`ifdef PCIE_ALT_BRAM_SERVER\n      interface Server altBramServer = altBramMux.bramServer;\n`endif\n   endinterface\nendmodule: mkPcieTracer\n\ninstance Connectable#(TlpTraceClient,TlpTraceServer);\n   module mkConnection#(TlpTraceClient client, TlpTraceServer tracer)(Empty);\n      mkConnection(client.bramClient, tracer.bramServer);\n      Reg#(Bool)                           tlpTracingReg <- mkReg(False);\n      Reg#(Bit#(TlpTraceAddrSize))      tlpTraceLimitReg <- mkReg(0);\n      Reg#(Bit#(TlpTraceAddrSize)) tlpTraceBramWrAddrReg <- mkReg(0);\n      rule tracingRule if (tlpTracingReg != client.tlpTracing);\n\t tracer.tlpTracing <= client.tlpTracing;\n\t tlpTracingReg <= client.tlpTracing;\n      endrule\n      rule traceLimitRule if (tlpTraceLimitReg != client.tlpTraceLimit);\n\t tracer.tlpTraceLimit <= client.tlpTraceLimit;\n\t tlpTraceLimitReg <= client.tlpTraceLimit;\n      endrule\n      // both client and server update the tlpBramWrAddr\n      rule traceBramWrAddrRule if (tlpTraceBramWrAddrReg != client.tlpTraceBramWrAddr);\n\t tracer.tlpTraceBramWrAddr <= client.tlpTraceBramWrAddr;\n\t tlpTraceBramWrAddrReg <= client.tlpTraceBramWrAddr;\n      endrule\n   endmodule\nendinstance\n"
  },
  {
    "path": "bsv/PhysMemSlaveFromBram.bsv",
    "content": "// Copyright (c) 2013 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\n`include \"ConnectalProjectConfig.bsv\"\nimport FIFOF::*;\nimport FIFO::*;\nimport GetPut::*;\nimport ConnectalMemTypes::*;\nimport AddressGenerator::*;\nimport BRAM::*;\nimport Memory::*;\n\n\nmodule mkPhysMemSlaveFromBram#(BRAMServer#(Bit#(bramAddrWidth), Bit#(busDataWidth)) br) (PhysMemSlave#(busAddrWidth, busDataWidth))\n   provisos(Add#(a__, bramAddrWidth, busAddrWidth));\n\n   FIFOF#(Bit#(6))  readTagFifo <- mkFIFOF();\n   FIFOF#(Bit#(6)) writeTagFifo <- mkFIFOF();\n   FIFO#(Bool)     readLastFifo <- mkFIFO();\n   AddressGenerator#(busAddrWidth,busDataWidth) readAddrGenerator <- mkAddressGenerator();\n   AddressGenerator#(busAddrWidth,busDataWidth) writeAddrGenerator <- mkAddressGenerator();\n   let verbose = False;\n\n    Reg#(Bit#(32)) cycles      <- mkReg(0);\n    rule count;\n       cycles <= cycles + 1;\n    endrule\n\n   rule read_req;\n      let addrBeat <- readAddrGenerator.addrBeat.get();\n      let addr = addrBeat.addr;\n      let tag = addrBeat.tag;\n      let burstCount = addrBeat.bc;\n      readTagFifo.enq(tag);\n      readLastFifo.enq(addrBeat.last);\n      Bit#(bramAddrWidth) regFileAddr = truncate(addr/fromInteger(valueOf(TDiv#(busDataWidth,8))));\n      br.request.put(BRAMRequest{write:False, responseOnWrite:False, address:regFileAddr, datain:?});\n      if (verbose) $display(\"%d read_server.readData (a) %h %d last=%d\", cycles, addr, burstCount, addrBeat.last);\n   endrule\n\n   interface PhysMemReadServer read_server;\n      interface Put readReq;\n\t method Action put(PhysMemRequest#(busAddrWidth, busDataWidth) req);\n            if (verbose) $display(\"%d axiSlave.read.readAddr %h bc %d\", cycles, req.addr, req.burstLen);\n\t    readAddrGenerator.request.put(req);\n\t endmethod\n      endinterface\n      interface Get readData;\n\t method ActionValue#(MemData#(busDataWidth)) get();\n   \t    let tag = readTagFifo.first;\n\t    readTagFifo.deq;\n\t    readLastFifo.deq;\n            let data <- br.response.get;\n            if (verbose) $display(\"%d read_server.readData (b) %h\", cycles, data);\n            return MemData { data: data, tag: tag, last: readLastFifo.first };\n\t endmethod\n      endinterface\n   endinterface\n   interface PhysMemWriteServer write_server;\n      interface Put writeReq;\n\t method Action put(PhysMemRequest#(busAddrWidth, busDataWidth) req);\n\t    writeAddrGenerator.request.put(req);\n            if (verbose) $display(\"%d write_server.writeAddr %h bc %d\", cycles, req.addr, req.burstLen);\n\t endmethod\n      endinterface\n      interface Put writeData;\n\t method Action put(MemData#(busDataWidth) resp);\n\t    let addrBeat <- writeAddrGenerator.addrBeat.get();\n\t    let addr = addrBeat.addr;\n\t    Bit#(bramAddrWidth) regFileAddr = truncate(addr/fromInteger(valueOf(TDiv#(busDataWidth,8))));\n            br.request.put(BRAMRequest{write:True, responseOnWrite:False, address:regFileAddr, datain:resp.data});\n            if (verbose) $display(\"%d write_server.writeData %h %h %d\", cycles, addr, resp.data, addrBeat.bc);\n            if (addrBeat.last)\n               writeTagFifo.enq(addrBeat.tag);\n\t endmethod\n      endinterface\n      interface Get writeDone;\n\t method ActionValue#(Bit#(6)) get();\n\t    writeTagFifo.deq;\n            return writeTagFifo.first;\n\t endmethod\n      endinterface\n   endinterface\nendmodule\n\nmodule mkPhysMemSlaveFromBramBE#(BRAMServerBE#(Bit#(bramAddrWidth), Bit#(busDataWidth), dataWidthBytes) br) (PhysMemSlave#(busAddrWidth, busDataWidth))\n   provisos(Add#(a__, bramAddrWidth, busAddrWidth)\n           ,Mul#(dataWidthBytes, 8, busDataWidth)\n           ,Div#(busDataWidth, 8, dataWidthBytes)\n           );\n   let verbose = False;\n\n   FIFOF#(Bit#(6))  readTagFifo <- mkFIFOF();\n   FIFOF#(Bit#(6)) writeTagFifo <- mkFIFOF();\n   FIFO#(Bool)     readLastFifo <- mkFIFO();\n   FIFOF#(Bit#(TDiv#(busDataWidth, 8))) readByteEnableFifo <- mkFIFOF;\n   FIFOF#(Bit#(TDiv#(busDataWidth, 8))) writeByteEnableFifo <- mkFIFOF;\n\n   AddressGenerator#(busAddrWidth,busDataWidth) readAddrGenerator <- mkAddressGenerator();\n   AddressGenerator#(busAddrWidth,busDataWidth) writeAddrGenerator <- mkAddressGenerator();\n\n   FIFO#(PhysMemRequest#(busAddrWidth, busDataWidth)) req_ars <- mkFIFO1;\n   FIFO#(Bit#(bramAddrWidth)) req_addr <- mkFIFO1;\n   FIFO#(BRAMRequestBE#(Bit#(bramAddrWidth), Bit#(busDataWidth), dataWidthBytes)) req_aws <- mkFIFO1;\n\n   Reg#(Bit#(32)) cycles      <- mkReg(0);\n   rule count if (verbose);\n      cycles <= cycles + 1;\n   endrule\n\n   rule req_ar;\n     let req <- toGet(req_ars).get;\n     readAddrGenerator.request.put(req);\n   endrule\n\n   rule read_req;\n      let addrBeat <- readAddrGenerator.addrBeat.get();\n      let addr = addrBeat.addr;\n      let tag = addrBeat.tag;\n      let burstCount = addrBeat.bc;\n      readTagFifo.enq(tag);\n      readLastFifo.enq(addrBeat.last);\n      Bit#(bramAddrWidth) regFileAddr = truncate(addr/fromInteger(valueOf(TDiv#(busDataWidth,8))));\n      req_addr.enq(regFileAddr);\n      if (verbose) $display(\"%d read_server.readData (a) %h %d last=%d\", cycles, addr, burstCount, addrBeat.last);\n   endrule\n\n   rule read_bram_req;\n      let addr <- toGet(req_addr).get;\n      br.request.put(BRAMRequestBE{writeen:0, responseOnWrite:False, address:addr, datain:?});\n   endrule\n\n   rule req_aw;\n      let req <- toGet(req_aws).get;\n      br.request.put(req);\n   endrule\n\n   interface PhysMemReadServer read_server;\n      interface Put readReq;\n\t method Action put(PhysMemRequest#(busAddrWidth, busDataWidth) req);\n            if (verbose) $display(\"%d read_server.readAddr %h bc %d fbe %x lbe %x\", cycles, req.addr, req.burstLen\n`ifdef BYTE_ENABLES\n               , req.firstbe, req.lastbe\n`endif\n               );\n            req_ars.enq(req);\n            readByteEnableFifo.enq(reqLastByteEnable(req));\n\t endmethod\n      endinterface\n      interface Get readData;\n\t method ActionValue#(MemData#(busDataWidth)) get();\n   \t    let tag = readTagFifo.first;\n\t    readTagFifo.deq;\n\t    readLastFifo.deq;\n            let data <- br.response.get;\n            let readBE = readByteEnableFifo.first;\n            Bit#(dataWidthBytes) byteEnable = readLastFifo.first ? readBE : maxBound;\n            let newdata = updateDataWithMask(0, data, byteEnable);\n            if (verbose) $display(\"%d read_server.readData (b) %h, %h\", cycles, data, newdata);\n            if (readLastFifo.first) begin\n               readByteEnableFifo.deq;\n            end\n            return MemData { data: newdata, tag: tag, last: readLastFifo.first };\n\t endmethod\n      endinterface\n   endinterface\n   interface PhysMemWriteServer write_server;\n      interface Put writeReq;\n\t method Action put(PhysMemRequest#(busAddrWidth, busDataWidth) req);\n\t    writeAddrGenerator.request.put(req);\n            writeByteEnableFifo.enq(reqLastByteEnable(req));\n            if (verbose) $display(\"%d write_server.writeAddr %h bc %d fbe %x lbe %x\", cycles, req.addr, req.burstLen\n`ifdef BYTE_ENABLES\n               , req.firstbe, req.lastbe\n`endif\n               );\n\t endmethod\n      endinterface\n      interface Put writeData;\n\t method Action put(MemData#(busDataWidth) resp);\n\t    let addrBeat <- writeAddrGenerator.addrBeat.get();\n\t    let addr = addrBeat.addr;\n\t    Bit#(bramAddrWidth) regFileAddr = truncate(addr/fromInteger(valueOf(TDiv#(busDataWidth,8))));\n            let writeBE = writeByteEnableFifo.first;\n            Bit#(dataWidthBytes) byteEnable = addrBeat.last ? writeBE : maxBound;\n            req_aws.enq(BRAMRequestBE{writeen:byteEnable, responseOnWrite:False, address:regFileAddr, datain:resp.data});\n            if (verbose) $display(\"%d write_server.writeData %h %h %d\", cycles, addr, resp.data, addrBeat.bc);\n            if (addrBeat.last)\n               writeByteEnableFifo.deq;\n               writeTagFifo.enq(addrBeat.tag);\n\t endmethod\n      endinterface\n      interface Get writeDone;\n\t method ActionValue#(Bit#(6)) get();\n\t    writeTagFifo.deq;\n            return writeTagFifo.first;\n\t endmethod\n      endinterface\n   endinterface\nendmodule\n\n\nmodule mkMemServerFromBram#(BRAMServer#(Bit#(bramAddrWidth), Bit#(busDataWidth)) br) (MemServer#(busDataWidth))\n   provisos(Add#(a__, bramAddrWidth, MemOffsetSize));\n\n   FIFOF#(Tuple2#(Bit#(6),Bool))  readTagFifo <- mkFIFOF();\n   FIFOF#(Bit#(6)) writeTagFifo <- mkFIFOF();\n   AddressGenerator#(bramAddrWidth,busDataWidth) readAddrGenerator <- mkAddressGenerator();\n   AddressGenerator#(bramAddrWidth,busDataWidth) writeAddrGenerator <- mkAddressGenerator();\n   let verbose = False;\n\n    Reg#(Bit#(32)) cycles      <- mkReg(0);\n    rule count;\n       cycles <= cycles + 1;\n    endrule\n\n   rule read_req;\n      let addrBeat <- readAddrGenerator.addrBeat.get();\n      let addr = addrBeat.addr;\n      let tag = addrBeat.tag;\n      let burstCount = addrBeat.bc;\n      readTagFifo.enq(tuple2(tag, addrBeat.last));\n      Bit#(bramAddrWidth) regFileAddr = truncate(addr/fromInteger(valueOf(TDiv#(busDataWidth,8))));\n      br.request.put(BRAMRequest{write:False, responseOnWrite:False, address:regFileAddr, datain:?});\n      if (verbose) $display(\"%d read_server.readData (a) %h %d last=%d\", cycles, addr, burstCount, addrBeat.last);\n   endrule\n\n   interface MemReadServer readServer;\n      interface Put readReq;\n\t method Action put(MemRequest req);\n            if (verbose) $display(\"%d axiSlave.read.readAddr %h bc %d\", cycles, req.offset, req.burstLen);\n\t    readAddrGenerator.request.put(PhysMemRequest { addr: truncate(req.offset), burstLen: req.burstLen, tag: req.tag });\n\t endmethod\n      endinterface\n      interface Get readData;\n\t method ActionValue#(MemData#(busDataWidth)) get();\n\t    match { .tag, .last } = readTagFifo.first;\n\t    readTagFifo.deq;\n            let data <- br.response.get;\n            if (verbose) $display(\"%d read_server.readData (b) %h\", cycles, data);\n            return MemData { data: data, tag: tag, last: last };\n\t endmethod\n      endinterface\n   endinterface\n   interface MemWriteServer writeServer;\n      interface Put writeReq;\n\t method Action put(MemRequest req);\n\t    writeAddrGenerator.request.put(PhysMemRequest { addr: truncate(req.offset), burstLen: req.burstLen, tag: req.tag});\n            if (verbose) $display(\"%d write_server.writeAddr %h bc %d\", cycles, req.offset, req.burstLen);\n\t endmethod\n      endinterface\n      interface Put writeData;\n\t method Action put(MemData#(busDataWidth) resp);\n\t    let addrBeat <- writeAddrGenerator.addrBeat.get();\n\t    let addr = addrBeat.addr;\n\t    Bit#(bramAddrWidth) regFileAddr = truncate(addr/fromInteger(valueOf(TDiv#(busDataWidth,8))));\n            br.request.put(BRAMRequest{write:True, responseOnWrite:False, address:regFileAddr, datain:resp.data});\n            if (verbose) $display(\"%d write_server.writeData %h %h %d\", cycles, addr, resp.data, addrBeat.bc);\n            if (addrBeat.last)\n               writeTagFifo.enq(addrBeat.tag);\n\t endmethod\n      endinterface\n      interface Get writeDone;\n\t method ActionValue#(Bit#(6)) get();\n\t    writeTagFifo.deq;\n            return writeTagFifo.first;\n\t endmethod\n      endinterface\n   endinterface\nendmodule\n"
  },
  {
    "path": "bsv/Pipe.bsv",
    "content": "// Copyright (c) 2014 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\n\nimport FIFOF::*;\nimport SpecialFIFOs::*;\nimport GetPut::*;\nimport Connectable::*;\nimport Vector::*;\nimport BuildVector::*;\nimport MIMO::*;\nimport DefaultValue::*;\nimport Gearbox::*;\nimport Clocks::*;\nimport AxiStream::*;\n\ntypedef Tuple3#(x,x,x) Triplet#(type x);\ntypedef Tuple2#(x,x)   Pair#(type x);\n\ninterface PipeIn#(type a);\n   method Action enq(a v);\n   method Bool notFull();\nendinterface\n\ninterface PipeOut#(type a);\n   method a first();\n   method Action deq();\n   method Bool notEmpty();\nendinterface\n\nfunction Bool pipeInNotFull(PipeIn#(a) pipein); return pipein.notFull(); endfunction\nfunction Bool pipeOutNotEmpty(PipeOut#(a) pipein); return pipein.notEmpty(); endfunction\n\ntypeclass ToPipeIn#(type a, type b) dependencies (b determines a);\n   function PipeIn#(a) toPipeIn(b in);\nendtypeclass\n\ntypeclass ToPipeOut#(type a, type b) dependencies ( b determines a);\n   function PipeOut#(a) toPipeOut(b in);\nendtypeclass\n\ntypeclass MkPipeOut#(type a, type b) dependencies ( b determines a);\n   module mkPipeOut#(b in)(PipeOut#(a));\nendtypeclass\n\ntypeclass MkPipeIn#(type a, type b) dependencies ( b determines a);\n   module mkPipeIn#(b in)(PipeIn#(a));\nendtypeclass\n\ninstance ToPipeIn#(a, FIFOF#(a));\n   function PipeIn#(a) toPipeIn(FIFOF#(a) in);\n      return (interface PipeIn#(a);\n\t\t method enq = in.enq;\n\t\t method notFull = in.notFull;\n\t      endinterface);\n   endfunction\nendinstance\n\ninstance ToPipeOut#(a, function a pipefn());\n   function PipeOut#(a) toPipeOut(function a pipefn());\n      return (interface PipeOut#(a);\n\t\t method first(); return pipefn(); endmethod\n\t\t method Action deq(); endmethod\n\t\t method Bool notEmpty(); return False; endmethod\n\t      endinterface);\n   endfunction\nendinstance\n\ninstance ToPipeOut#(a, Reg#(a));\n   function PipeOut#(a) toPipeOut(Reg#(a) in);\n      return (interface PipeOut#(a);\n\t\t method first(); return in; endmethod\n\t\t method Action deq(); endmethod\n\t\t method Bool notEmpty(); return False; endmethod\n\t      endinterface);\n   endfunction\nendinstance\n\ninstance ToPipeIn#(a, Gearbox#(1, n, a));\n   function PipeIn#(a) toPipeIn(Gearbox#(1, n, a) in);\n      return (interface PipeIn#(a);\n\t\t method Action enq(a v); in.enq(vec(v)); endmethod\n\t\t method notFull = in.notFull;\n\t      endinterface);\n   endfunction\nendinstance\n\ninstance ToPipeIn#(Vector#(m, a), Gearbox#(m, n, a));\n   function PipeIn#(Vector#(m, a)) toPipeIn(Gearbox#(m, n, a) in);\n      return (interface PipeIn#(Vector#(m, a));\n\t\t method enq = in.enq;\n\t\t method notFull = in.notFull;\n\t      endinterface);\n   endfunction\nendinstance\n\ninstance ToPipeOut#(a, FIFOF#(a));\n   function PipeOut#(a) toPipeOut(FIFOF#(a) in);\n      return (interface PipeOut#(a);\n\t\t method first = in.first;\n\t\t method deq = in.deq;\n\t\t method notEmpty = in.notEmpty;\n\t      endinterface);\n   endfunction\nendinstance\n\ninstance ToPipeOut#(Vector#(n,a), MIMO#(k,n,sz,a));\n   function PipeOut#(Vector#(n,a)) toPipeOut(MIMO#(k,n,sz,a) in);\n      return (interface PipeOut#(a);\n\t\t method first = in.first;\n\t\t method Action deq() if (in.deqReadyN(fromInteger(valueOf(n))));\n\t\t    in.deq(fromInteger(valueOf(n)));\n\t\t endmethod\n\t\t method Bool notEmpty();\n\t\t    return in.deqReadyN(fromInteger(valueOf(n)));\n\t\t endmethod\n\t      endinterface);\n   endfunction\nendinstance\n\ninstance ToPipeOut#(Vector#(n, a), Gearbox#(m, n, a));\n   function PipeOut#(Vector#(n, a)) toPipeOut(Gearbox#(m, n, a) in);\n      return (interface PipeOut#(Vector#(n,a));\n\t\t method first = in.first;\n\t\t method deq = in.deq;\n\t\t method notEmpty = in.notEmpty;\n\t      endinterface);\n   endfunction\nendinstance\ninstance ToPipeOut#(a, Gearbox#(m, 1, a));\n   function PipeOut#(a) toPipeOut(Gearbox#(m, 1, a) in);\n      return (interface PipeOut#(a);\n\t\t method a first(); return in.first[0]; endmethod\n\t\t method deq = in.deq;\n\t\t method notEmpty = in.notEmpty;\n\t      endinterface);\n   endfunction\nendinstance\n\ninstance ToPipeIn#(a, SyncFIFOIfc#(a));\n   function PipeIn#(a) toPipeIn(SyncFIFOIfc#(a) in);\n      return (interface PipeIn#(a);\n\t\t method enq = in.enq;\n\t\t method notFull = in.notFull;\n\t      endinterface);\n   endfunction\nendinstance\n\ninstance ToPipeOut#(a, SyncFIFOIfc#(a));\n   function PipeOut#(a) toPipeOut(SyncFIFOIfc#(a) in);\n      return (interface PipeOut#(a);\n\t\t method first = in.first;\n\t\t method deq = in.deq;\n\t\t method notEmpty = in.notEmpty;\n\t      endinterface);\n   endfunction\nendinstance\n\ninstance MkPipeOut#(a, ActionValue#(a))\n   provisos (Bits#(a, asz));\n   module mkPipeOut#(ActionValue#(a) in)(PipeOut#(a));\n      FIFOF#(a) fifo <- mkFIFOF();\n      rule connect;\n\t let v <- in;\n\t fifo.enq(v);\n      endrule\n      return toPipeOut(fifo);\n   endmodule\nendinstance\n\ninstance MkPipeOut#(a, Get#(a))\n   provisos (Bits#(a, asz));\n   module mkPipeOut#(Get#(a) in)(PipeOut#(a));\n      FIFOF#(a) fifo <- mkFIFOF();\n      rule connect;\n\t let v <- in.get();\n\t fifo.enq(v);\n      endrule\n      return toPipeOut(fifo);\n   endmodule\nendinstance\n\ninstance MkPipeIn#(a, Put#(a))\n   provisos (Bits#(a, asz));\n   module mkPipeIn#(Put#(a) out)(PipeIn#(a));\n      FIFOF#(a) fifo <- mkFIFOF();\n      rule connect;\n\t let v <- toGet(fifo).get;\n\t out.put(v);\n      endrule\n      return toPipeIn(fifo);\n   endmodule\nendinstance\n\nfunction PipeOut#(a) toCountedPipeOut(Reg#(Bit#(n)) r, PipeOut#(a) pipe);\n   return (interface PipeOut#(Vector#(n,a));\n\t      method first = pipe.first;\n\t      method Action deq(); pipe.deq; r <= r + 1; endmethod\n\t      method notEmpty = pipe.notEmpty;\n\t   endinterface);\nendfunction   \n\ninstance ToGet #(PipeOut #(a), a);\n   function Get #(a) toGet (PipeOut #(a) po);\n      return (interface Get;\n                 method ActionValue #(a) get ();\n                    po.deq ();\n                    return po.first ();\n                 endmethod\n              endinterface);\n   endfunction\nendinstance\n\ninstance ToPut #(PipeIn #(a), a);\n   function Put #(a) toPut (PipeIn #(a) pi);\n      return (interface Put;\n\t\t method Action put(a v);\n                    pi.enq (v);\n                 endmethod\n              endinterface);\n   endfunction\nendinstance\n\ninstance Connectable#(PipeOut#(a),Put#(a));\n   module mkConnection#(PipeOut#(a) in, Put#(a) out)(Empty);\n      rule connect if (in.notEmpty);\n\t let v = in.first;\n\t in.deq();\n\t out.put(v);\n      endrule\n   endmodule\nendinstance\n\ninstance Connectable#(ActionValue#(a),PipeIn#(a));\n   module mkConnection#(ActionValue#(a) in, PipeIn#(a) out)(Empty);\n      rule connect;\n\t let v <- in;\n\t out.enq(v);\n      endrule\n   endmodule\nendinstance\n\ninstance Connectable#(PipeOut#(a),PipeIn#(a));\n   module mkConnection#(PipeOut#(a) in, PipeIn#(a) out)(Empty);\n      rule connect if (in.notEmpty);\n\t let v = in.first;\n\t in.deq();\n\t out.enq(v);\n      endrule\n   endmodule\nendinstance\n\nfunction PipeOut#(a) unvectorPipeOut(PipeOut#(Vector#(1,a)) in);\n   return (interface PipeOut#(a);\n\t      method first = in.first[0];\n\t      method deq = in.deq;\n\t      method notEmpty = in.notEmpty;\n\t   endinterface);\nendfunction\n\nfunction PipeOut#(Tuple2#(a,b)) zipPipeOut(PipeOut#(a) ina, PipeOut#(b) inb);\n      return (interface PipeOut#(Tuple2#(a,b));\n\t\t method Tuple2#(a,b) first(); return tuple2(ina.first, inb.first); endmethod\n\t\t method Action deq(); ina.deq(); inb.deq(); endmethod\n\t\t method Bool notEmpty(); return ina.notEmpty() && inb.notEmpty(); endmethod\n\t      endinterface);\n   endfunction\n\nmodule mkFunnel#(PipeOut#(Vector#(mk,a)) in)(PipeOut#(Vector#(m, a)))\n   provisos (Mul#(m, k, mk),\n\t     Bits#(a, asz),\n\t     Add#(a__, TMul#(asz, m), TMul#(asz, mk)),\n\t     Add#(1, b__, asz),\n\t     Add#(2, c__, mk),\n\t     Add#(d__, m, mk),\n\t     Add#(asz, m, e__),\n\t     Add#(asz, mk, f__));\n   let m = fromInteger(valueOf(m));\n   let mk = fromInteger(valueOf(mk));\n\n   MIMOConfiguration cfg = defaultValue();\n   MIMO#(mk, m, mk, a) mimo <- mkMIMO(cfg);\n   rule consumer if (mimo.enqReadyN(mk));\n      Vector#(mk, a) v = in.first();\n      in.deq();\n      mimo.enq(mk, v);\n   endrule\n\n   method Vector#(m, a) first() if (mimo.deqReadyN(m));\n      return mimo.first();\n   endmethod\n   method Action deq() if (mimo.deqReadyN(m));\n      mimo.deq(m);\n   endmethod\n   method notEmpty();\n      return mimo.deqReadyN(m);\n   endmethod\nendmodule\n\nmodule mkFunnel1#(PipeOut#(Vector#(k,a)) in)(PipeOut#(a))\n   provisos (Bits#(a, asz), Log#(k,ksz));\n\n   Reg#(Bit#(ksz)) selector <- mkReg(0);\n\n   method a first();\n      return in.first[selector];\n   endmethod\n   method Action deq();\n      if (selector == fromInteger(valueOf(k)-1)) begin\n\t in.deq();\n\t selector <= 0;\n      end\n      else\n\t selector <= selector + 1;\n   endmethod\n   method notEmpty();\n      return in.notEmpty();\n   endmethod\nendmodule\n\nmodule mkFunnelGB1#(Clock slowClock, Reset slowReset, Clock fastClock, Reset fastReset, PipeOut#(Vector#(k,a)) in)(PipeOut#(a))\n   provisos (Bits#(a, asz), Log#(k,ksz), Add#(1,a__,k));\n\n   Gearbox#(k,1,a) gb <- mkNto1Gearbox(slowClock, slowReset, fastClock, fastReset);\n   PipeIn#(Vector#(k,a)) toGb = toPipeIn(gb);\n   mkConnection(in, toGb);\n   PipeOut#(Vector#(1,a)) fromGb = toPipeOut(gb);\n   return mapPipe(head, fromGb);\nendmodule\n\n// 'j' is the width of the narrow end, and 'k' is the width of the wide end\ntypedef Vector#(j,PipeOut#(a))   FunnelPipe#(numeric type j, numeric type k, type a, numeric type bitsPerCycle);\ntypedef Vector#(k,PipeOut#(a)) UnFunnelPipe#(numeric type j, numeric type k, type a, numeric type bitsPerCycle);\n\ntypeclass FunnelPipesPipelined#(numeric type j, numeric type k, type a, numeric type bpc);\n   module mkFunnelPipesPipelined#(Vector#(k,PipeOut#(a)) in) (FunnelPipe#(j,k,a,bpc));\n   module mkFunnelPipesPipelinedRR#(Vector#(k,PipeOut#(a)) in, Integer c) (FunnelPipe#(j,k,a,bpc));\n   module mkUnFunnelPipesPipelined#(Vector#(j,PipeOut#(Tuple2#(Bit#(TLog#(k)),a))) in) (UnFunnelPipe#(j,k,a,bpc));\n   module mkUnFunnelPipesPipelinedRR#(Vector#(j,PipeOut#(a)) in, Integer c) (UnFunnelPipe#(j,k,a,bpc));\nendtypeclass\n\nfunction PipeOut#(b) pipeSecond(PipeOut#(Tuple2#(a,b)) x) = \n   (interface PipeOut;\n       method b first;\n\t  return tpl_2(x.first);\n       endmethod\n       method Action deq = x.deq;\n       method Bool notEmpty = x.notEmpty;\n    endinterface);\n   \ninstance FunnelPipesPipelined#(1,1,a,bpc)   \n   provisos (Bits#(a,a__));\n   module mkFunnelPipesPipelined#(Vector#(1,PipeOut#(a)) in) (FunnelPipe#(1,1,a,bpc));\n      return in;\n   endmodule\n   module mkFunnelPipesPipelinedRR#(Vector#(1,PipeOut#(a)) in, Integer c) (FunnelPipe#(1,1,a,bpc));\n      return in;\n   endmodule\n   module mkUnFunnelPipesPipelined#(Vector#(1,PipeOut#(Tuple2#(Bit#(0),a))) in) (UnFunnelPipe#(1,1,a,bpc));\n      return map(pipeSecond, in);\n   endmodule\n   module mkUnFunnelPipesPipelinedRR#(Vector#(1,PipeOut#(a)) in, Integer c) (UnFunnelPipe#(1,1,a,bpc));\n      return in;\n   endmodule\nendinstance\n\nmodule mkUnFunnelPipesPipelinedInternal#(Vector#(1, PipeOut#(Tuple2#(Bit#(TLog#(k)),a))) in) (UnFunnelPipe#(1,k,a,bpc))\n   provisos (Log#(k, logk),\n\t     Bits#(a,a__),\n\t     Add#(1,b__,k),\n\t     Div#(k,TExp#(bpc),c__),\n\t     Mul#(c__,TExp#(bpc),krounded),\n\t     Add#(1, d__, krounded),\n\t     Add#(k, e__, krounded),\n\t     Div#(logk,bpc,stages));\n   Vector#(krounded, PipeOut#(Tuple2#(Bit#(logk),a))) ins  = append(in,replicate(?));\n   Vector#(krounded, PipeOut#(Tuple2#(Bit#(logk),a))) outs = newVector;\n   for(Integer j = 0; j < valueOf(stages); j=j+1) begin \n      for(Integer i = 0; i < min(valueOf(krounded), 2**(j*valueOf(bpc))); i=i+1) begin\n\t     Integer bits = (j == valueOf(stages)-1) ? valueOf(logk)-(j*valueOf(bpc)) : valueOf(bpc);\n\t     function Bit#(bpc) sh(Bit#(bpc) x) = x<<(valueOf(bpc)-bits);\n\t     for(Integer l = 0; l < 2**bits; l=l+1)  begin\n\t        let buff <- mkFIFOF;\n\t        // extra conditional in case 'k' is not a power of 2\n\t        let idx = (2**bits)*i+l;\n\t        if (idx < valueOf(k)) begin\n\t           outs[idx] = toPipeOut(buff);\n\t           rule xfer if(tpl_1(ins[i].first)[(valueOf(logk)-1):max(0,(valueOf(logk)-valueOf(bpc)))] == sh(fromInteger(l)));\n\t\t          match{.idx, .v} <- toGet(ins[i]).get;\n\t\t          buff.enq(tuple2(idx<<valueOf(bpc), v));\n\t           endrule\n\t        end\n\t     end\n      end\n      ins = outs;\n   end\n   return take(map(pipeSecond,outs));\nendmodule\n   \nmodule mkFunnelNode#(Vector#(n, PipeOut#(a)) inpipes, Integer numPipes, Put#(a) outpipe)(Empty);\n   rule funnel;\n      a v = ?;\n      Bool send = False;\n      for (Integer i = 0; i < valueOf(n) && i < numPipes; i = i+1)\n\t if (!send && inpipes[i].notEmpty) begin\n\t    v <- toGet(inpipes[i]).get();\n\t    send = True;\n\t end\n      if (send)\n\t outpipe.put(v);\n   endrule\nendmodule\n   \nmodule mkFunnelNodeRR#(Vector#(n, PipeOut#(a)) inpipes, Integer numPipes, Put#(a) outpipe)(Empty)\n   provisos (Log#(n, pipeIdxSz));\n   Reg#(Bit#(TAdd#(pipeIdxSz, 1))) idx <- mkReg(0);\n\n   rule funnel;\n      a v = ?;\n      Bool send = False;\n      Bit#(TAdd#(pipeIdxSz, 1)) curIdx = idx;\n      for (Integer i = 0; i < valueOf(n) && i < numPipes; i = i+1)\n         if (fromInteger(i) != curIdx && !send && inpipes[i].notEmpty) begin\n            send = True;\n            idx <= fromInteger(i);\n            curIdx = fromInteger(i);\n         end\n      if (!send && inpipes[curIdx].notEmpty)\n         send = True;\n      if (send) begin\n         v <- toGet(inpipes[curIdx]).get();\n         outpipe.put(v);\n      end\n   endrule\nendmodule\n\ninstance FunnelPipesPipelined#(1,k,a,bpc)\n   provisos (Log#(k, logk),\n\t     Bits#(a,a__),\n\t     Add#(1,b__,k),\n\t     Div#(logk,bpc,stages),\n\t     Mul#(TDiv#(k, TExp#(bpc)), TExp#(bpc), krounded),\n\t     Add#(k, c__, krounded),\n\t     Add#(TExp#(bpc), d__, krounded),\n\t     Add#(1, e__, krounded)\n\t     );\n   module mkFunnelPipesPipelined#(Vector#(k,PipeOut#(a)) in) (FunnelPipe#(1,k,a,bpc));\n      Vector#(stages, Vector#(krounded, FIFOF#(a))) buffs  <- replicateM(replicateM(mkFIFOF));\n      Vector#(krounded, PipeOut#(a)) paddedIn = append(in, replicate(?));\n      Vector#(TAdd#(stages,1), Vector#(krounded, PipeOut#(a))) infss = append(map(map(toPipeOut),buffs), vec(paddedIn));\n      for(Integer j = valueOf(stages); j > 0; j=j-1) begin\n\t Integer width = min(valueOf(krounded),2**(j*valueOf(bpc)));\n\t Integer stride = valueOf(TExp#(bpc));\n\t Vector#(krounded,PipeOut#(a)) pipes = infss[j];\n\t for(Integer i = 0; i < width && i < valueOf(k); i=i+stride) begin\n\t    Vector#(TExp#(bpc),PipeOut#(a)) inpipes = takeAt(i, pipes);\n\t    Integer numPipes = stride;\n\t    if (i + stride > valueOf(k))\n\t       numPipes = valueOf(k) - i;\n\t    mkFunnelNode(inpipes, numPipes, toPut(buffs[j-1][i/stride]));\n\t end\n      end\n      return vec(infss[0][0]);\n   endmodule\n   module mkFunnelPipesPipelinedRR#(Vector#(k,PipeOut#(a)) in, Integer c) (FunnelPipe#(1,k,a,bpc));\n      Vector#(stages, Vector#(k, FIFOF#(a))) buffs  <- replicateM(replicateM(mkFIFOF));\n      Vector#(TAdd#(stages,1), Vector#(k, PipeOut#(a))) infss = append(map(map(toPipeOut),buffs), cons(in,nil));\n      for(Integer j = valueOf(stages); j > 0; j=j-1) begin\n\t Vector#(k, FIFOF#(void)) ctrl  <- replicateM(mkFIFOF1());\n   \t for(Integer i = 0; i < 2**(j*valueOf(bpc)) && i < valueOf(k); i=i+1) begin\n   \t    let first = i==0;\n   \t    Reg#(Bit#(32)) cnt <- mkReg(0);\n   \t    let maxp = (2**((valueOf(stages)-j)*valueOf(bpc)))*c;\n   \t    let last = (maxp*(i+1) >= valueOf(k)*c);\n   \t    if (maxp*(i+1) > valueOf(k)*c) begin\n   \t       maxp = valueOf(k)*c-maxp*i;\n\t    end\n   \t    let xfer_guard = True;\n   \t    if (!first)\n   \t       xfer_guard = xfer_guard && ctrl[(i-1)].notEmpty;\n   \t    if (!last)\n   \t       xfer_guard = xfer_guard && (!ctrl[i].notEmpty);\n   \t    rule xfer if (xfer_guard);\n   \t       let new_cnt = cnt+1;\n   \t       if (new_cnt==fromInteger(maxp)) begin\n   \t\t  cnt <= 0;\n   \t\t  if (!last)\n   \t\t     ctrl[i].enq(?);\n   \t\t  if (last) \n   \t\t     for(Integer ff = 0; ff < i; ff=ff+1)\n   \t\t     \tctrl[ff].deq;\n   \t       end\n   \t       else begin\n   \t\t  cnt <= new_cnt;\n   \t       end\n   \t       let v <- toGet(infss[j][i]).get;\n   \t       toPut(buffs[j-1][i/(2**valueOf(bpc))]).put(v);\n   \t    endrule\n   \t end\n      end\n      return cons(infss[0][0],nil);\n   endmodule\n   module mkUnFunnelPipesPipelined#(Vector#(1, PipeOut#(Tuple2#(Bit#(logk),a))) in) (UnFunnelPipe#(1,k,a,bpc));\n      (* hide *)\n      let rv <- mkUnFunnelPipesPipelinedInternal(in);\n      return rv;\n   endmodule\n   module mkUnFunnelPipesPipelinedRR#(Vector#(1, PipeOut#(a)) in, Integer c) (UnFunnelPipe#(1,k,a,bpc));\n      Vector#(1, FIFOF#(Tuple2#(Bit#(logk),a))) tagged_in_buffers <- replicateM(mkFIFOF);\n      Vector#(1, PipeOut#(Tuple2#(Bit#(logk),a))) tagged_in = map(toPipeOut, tagged_in_buffers);\n      let rv <- mkUnFunnelPipesPipelinedInternal(tagged_in);\n      Reg#(Bit#(TAdd#(logk,1))) dest <- mkReg(0);\n      Reg#(Bit#(32)) cnt <- mkReg(0);\n      rule fill;\n\t let new_cnt = cnt+1;\n\t let new_dest = dest;\n\t if (new_cnt == fromInteger(c)) begin\n\t    new_cnt = 0;\n\t    new_dest = dest+1;\n\t    if(new_dest==fromInteger(valueOf(k)))\n\t       new_dest=0;\n\t end\n\t cnt <= new_cnt;\n\t dest <= new_dest;\n\t let v <- toGet(in[0]).get;\n\t tagged_in_buffers[0].enq(tuple2(truncate(dest),v));\n\t //$display(\"mkUnFunnelPipesPipelinedInternal::fill %d\", dest);\n      endrule\n      return rv;\n   endmodule\nendinstance\n   \nmodule mkUnfunnel#(PipeOut#(Vector#(m,a)) in)(PipeOut#(Vector#(mk, a)))\n   provisos (Mul#(m, k, mk),\n\t     Bits#(a, asz),\n\t     Add#(1, b__, asz),\n\t     Add#(2, c__, mk),\n\t     Add#(d__, m, mk),\n\t     Add#(asz, m, e__),\n\t     Add#(asz, mk, f__));\n   let m = fromInteger(valueOf(m));\n   let mk = fromInteger(valueOf(mk));\n\n   MIMOConfiguration cfg = defaultValue();\n   MIMO#(m, mk, mk, a) mimo <- mkMIMO(cfg);\n   rule consumer if (mimo.enqReadyN(m));\n      Vector#(m, a) v = in.first();\n      in.deq();\n      mimo.enq(m, v);\n   endrule\n\n   method Vector#(mk, a) first() if (mimo.deqReadyN(mk));\n      return mimo.first();\n   endmethod\n   method Action deq() if (mimo.deqReadyN(mk));\n      mimo.deq(mk);\n   endmethod\n   method notEmpty();\n      return mimo.deqReadyN(mk);\n   endmethod\nendmodule\n\nmodule mkUnfunnelGB#(Clock slowClock, Reset slowReset, Clock fastClock, Reset fastReset, PipeOut#(Vector#(1,a)) in)(PipeOut#(Vector#(k, a)))\n   provisos (Bits#(a, asz),\n\t     Add#(1, a__, k),\n\t     Add#(1, b__, asz),\n\t     Add#(1, c__, TMul#(2,k)),\n\t     Add#(k, d__, TMul#(2,k))\n      );\n   let k = fromInteger(valueOf(k));\n\n   Gearbox#(1,k,a) gb <- mk1toNGearbox(fastClock, fastReset, slowClock, slowReset);\n   PipeIn#(Vector#(1,a)) toGb = toPipeIn(gb);\n   PipeOut#(Vector#(k,a)) fromGb = toPipeOut(gb);\n   mkConnection(in,toGb);\n   return fromGb;\nendmodule: mkUnfunnelGB\n\nmodule mkFunnelPipes#(Vector#(mk, PipeOut#(a)) ins)(Vector#(m, PipeOut#(a)))\n   provisos (Mul#(m, k, mk),\n\t     Bits#(a, asz),\n\t     Log#(k,ksz)\n      );\n   let k = fromInteger(valueOf(k));\n   let m = fromInteger(valueOf(m));\n   let mk = fromInteger(valueOf(mk));\n\n   Vector#(m, FIFOF#(a)) fifos <- replicateM(mkFIFOF);\n   for (Integer i = 0; i < m; i = i+1) begin\n      Reg#(Bit#(asz)) which <- mkReg(0);\n      rule consumer;\n\t let index = (which << valueOf(ksz)) + fromInteger(i);\n\t let v <- toGet(ins[index]).get();\n\t fifos[i].enq(v);\n\t which <= (which + 1) % k;\n      endrule\n   end\n\n   return map(toPipeOut, fifos);\nendmodule\n\nmodule mkFunnelPipes1#(Vector#(k, PipeOut#(a)) ins)(PipeOut#(a))\n   provisos (Bits#(a, asz),\n\t     Log#(k,ksz)\n      );\n   let k = fromInteger(valueOf(k));\n   Reg#(Bit#(ksz)) selector <- mkReg(0);\n\n   method a first();\n      return ins[selector].first();\n   endmethod\n   method Action deq();\n      ins[selector].deq();\n      if (selector == fromInteger(valueOf(k)-1))\n\t selector <= 0;\n   else\n      selector <= selector + 1;\n   endmethod\n   method Bool notEmpty();\n      return ins[selector].notEmpty();\n   endmethod\nendmodule\n\nmodule mkUnfunnelPipes#(Vector#(m, PipeOut#(a)) ins)(Vector#(mk, PipeOut#(a)))\n   provisos (Mul#(m, k, mk),\n\t     Log#(k,ksz),\n\t     Bits#(a,asz));\n   \n   let m = fromInteger(valueOf(m));\n   let k = fromInteger(valueOf(k));\n   let mk = fromInteger(valueOf(mk));\n   \n   Vector#(mk, FIFOF#(a)) fifos <- replicateM(mkFIFOF);\n   for (Integer i = 0; i < m; i = i + 1) begin\n      Reg#(Bit#(TAdd#(1,ksz))) which <- mkReg(0);\n      rule consumer;\n\t let index = which + fromInteger(i)*k;\n\t let v <- toGet(ins[i]).get();\n\t fifos[index].enq(v);\n\t which <= (which + 1) % k;\n      endrule\n   end\n   return map(toPipeOut, fifos);\nendmodule\n\nmodule mkRepeat#(UInt#(n) repetitions, PipeOut#(a) inpipe)(PipeOut#(a));\n   Reg#(UInt#(n)) count <- mkReg(0);\n   method first = inpipe.first;\n   method Action deq();\n      let c = count + 1;\n      if (count == (repetitions - 1)) begin\n\t c = 0;\n\t inpipe.deq();\n      end\n      count <= c;\n   endmethod\n   method notEmpty = inpipe.notEmpty;\nendmodule\n\nmodule mkForkVectorPipelined#(PipeOut#(a) inpipe)(UnFunnelPipe#(1,k,a,bpc))\n   provisos ( Bits#(a,a__)\n\t     ,Add#(1,b__,k)\n\t     ,Log#(k,logk)\n\t     ,Div#(logk,bpc,stages));\n   Vector#(k, FIFOF#(a))  buffs = newVector;\n   Vector#(k, PipeOut#(a)) infs = cons(inpipe,replicate(?));\n   for(Integer j = 0; j < valueOf(stages); j=j+1)begin\n      for(Integer i = 0; i < 2**((j+1)*valueOf(bpc)) && i < valueOf(k); i=i+1) \n\t buffs[i] <- mkFIFOF;\n      rule xfer;\n      \t for(Integer i = 0; i < 2**(j*valueOf(bpc)) && i < valueOf(k); i=i+1) begin\n      \t    for(Integer l = 0; l < 2**valueOf(bpc) && l < valueOf(k); l=l+1) begin\n\t       Integer idx = (i*(2**valueOf(bpc)))+l;\n      \t       if (idx < valueOf(k)) \n\t\t  buffs[idx].enq(infs[i].first);\n      \t    end\n      \t    infs[i].deq;\n      \t end\n      endrule\n      infs = map(toPipeOut, buffs);\n   end\n   return infs;\nendmodule\n\nmodule mkForkVector#(PipeOut#(a) inpipe)(Vector#(n, PipeOut#(a)))\n   provisos (Bits#(a, asz));\n   Vector#(n, FIFOF#(a)) fifos <- replicateM(mkFIFOF());\n   rule forkelts;\n      let v = inpipe.first();\n      inpipe.deq;\n      for (Integer i = 0; i < valueOf(n); i = i + 1) begin\n\t fifos[i].enq(v);\n      end\n   endrule\n   return map(toPipeOut, fifos);\nendmodule\n\nmodule mkSizedForkVector#(Integer size, PipeOut#(a) inpipe)(Vector#(n, PipeOut#(a)))\n   provisos (Bits#(a, asz));\n   Vector#(n, FIFOF#(a)) fifos <- replicateM(mkSizedFIFOF(size));\n   rule forkelts;\n      let v = inpipe.first();\n      inpipe.deq;\n      for (Integer i = 0; i < valueOf(n); i = i + 1) begin\n\t fifos[i].enq(v);\n      end\n   endrule\n   return map(toPipeOut, fifos);\nendmodule\n   \n\n\nmodule mkJoin#(function c f(a av, b bv), PipeOut#(a) apipe, PipeOut#(b) bpipe)(PipeOut#(c));\n   method c first();\n      let av = apipe.first();\n      let bv = bpipe.first();\n      return f(av, bv);\n   endmethod\n   method Action deq();\n      apipe.deq();\n      bpipe.deq();\n   endmethod\n   method Bool notEmpty();\n      return apipe.notEmpty() && bpipe.notEmpty();\n   endmethod\nendmodule\n\nmodule mkJoinBuffered#(function c f(a av, b bv), PipeOut#(a) apipe, PipeOut#(b) bpipe)(PipeOut#(c))\n   provisos (Bits#(c, csz));\n   FIFOF#(c) joinFifo <- mkFIFOF();\n   rule joinrule;\n      let av <- toGet(apipe).get();\n      let bv <- toGet(bpipe).get();\n      joinFifo.enq(f(av, bv));\n   endrule\n   return toPipeOut(joinFifo);\nendmodule\n\nmodule mkJoinVector#(function b f(Vector#(n, a) av), Vector#(n, PipeOut#(a)) apipes)(PipeOut#(b))\n   provisos (Bits#(Vector#(n,a),vasz));\n   method b first();\n      function a getfirst(PipeOut#(a) pipein); return pipein.first(); endfunction\n      Vector#(n,a) vec = map(getfirst, apipes);\n      return f(vec);\n   endmethod\n   method Action deq();\n      function a getfirst(PipeOut#(a) pipein); return pipein.first(); endfunction\n      for (Integer i = 0; i < valueOf(n); i = i + 1)\n\t apipes[i].deq();\n   endmethod\n   method Bool notEmpty();\n      function Bool myand(Bool a, Bool b); return a && b; endfunction\n      return foldl(myand, True, map(pipeOutNotEmpty, apipes));\n   endmethod\nendmodule\n\nfunction PipeOut#(b) mapPipe(function b f(a av), PipeOut#(a) apipe);\n   return (interface PipeOut#(b);\n      method b first();\n\t let av = apipe.first();\n\t return f(av);\n      endmethod\n      method Action deq();\n\t apipe.deq();\n      endmethod\n      method Bool notEmpty();\n\t return apipe.notEmpty();\n      endmethod\n      endinterface);\nendfunction\n   \nfunction PipeIn#(a) mapPipeIn(function b f(a av), PipeIn#(b) apipe);\n   return (interface PipeIn#(b);\n\t      method Action enq(a v);\n\t\t apipe.enq(f(v));\n\t      endmethod\n\t      method Bool notFull();\n\t\t return apipe.notFull();\n\t      endmethod\n\t   endinterface);\nendfunction\n\n// buffered version of mapPipe\nmodule mkMapPipe#(function b f(a av), PipeOut#(a) apipe)(PipeOut#(b))\n   provisos (Bits#(b,bsz));\n   FIFOF#(b) fifo <- mkFIFOF();\n   rule compute;\n      let v <- toGet(apipe).get();\n      fifo.enq(f(v));\n   endrule\n   return toPipeOut(fifo);\nendmodule\n\ntypedef (function tb f(ta x)) CombinePipe#(type ta, type tb);\n\ntypeclass ReducePipe#( numeric type n, type a);\n   module  mkReducePipe#(CombinePipe#(Tuple2#(a,a), a) combinepipe,\n\t\t\t PipeOut#(Vector#(n,a)) inpipe)\n\t\t\t (PipeOut#(a));\n   module  mkReducePipes#(CombinePipe#(Tuple2#(a,a), a) combinepipe,\n\t\t\t  Vector#(n,PipeOut#(a)) inpipe)\n\t\t\t  (PipeOut#(a));\nendtypeclass\ninstance ReducePipe#(1, a);\n   module  mkReducePipe#(CombinePipe#(Tuple2#(a,a), a) combinepipe,\n\t\t\t\t PipeOut#(Vector#(1,a)) inpipe)\n\t\t\t\t (PipeOut#(a));\n      let pipe = mapPipe(head, inpipe);\n      return pipe;\n   endmodule\n   module  mkReducePipes#(CombinePipe#(Tuple2#(a,a), a) combinepipe,\n\t\t\t\t  Vector#(1,PipeOut#(a)) inpipes)\n\t\t\t\t  (PipeOut#(a));\n      return inpipes[0];\n   endmodule\nendinstance\ninstance ReducePipe#(2, a)\n   provisos(Bits#(a,a__));\n   module  mkReducePipe#(CombinePipe#(Tuple2#(a,a), a) combinepipe,\n\t\t\t PipeOut#(Vector#(2,a)) inpipe)\n\t\t\t(PipeOut#(a));\n      function a foo(Vector#(2,a) invec); \n\t return combinepipe(tuple2(invec[0], invec[1])); \n      endfunction\n      let pipe <- mkMapPipe(foo, inpipe);\n      return pipe;\n   endmodule\n   module  mkReducePipes#(CombinePipe#(Tuple2#(a,a), a) combinepipe,\n\t\t\t  Vector#(2,PipeOut#(a)) inpipes)\n\t\t\t  (PipeOut#(a));\n      function a foo(Tuple2#(a,a) invec); \n\t return combinepipe(invec);\n      endfunction\n      let pipe <- mkMapPipe(foo, zipPipeOut(inpipes[0], inpipes[1]));\n      return pipe;\n   endmodule\nendinstance\n\ninstance ReducePipe#(n, a)\n   provisos (Add#(TDiv#(n,2), a__, n),\n\t     Bits#(Vector#(TDiv#(n,2), a), b__),\n\t     ReducePipe#(TDiv#(n,2),a),\n\t     ReducePipe#(TSub#(n, TDiv#(n, 2)), a)\n      );\n   module  mkReducePipe#(CombinePipe#(Tuple2#(a,a), a) combinepipe,\n\t\t\t PipeOut#(Vector#(n,a)) inpipe)\n\t\t\t(PipeOut#(a));\n      FIFOF#(Vector#(TDiv#(n,2),a)) infifo0 <- mkFIFOF;\n      FIFOF#(Vector#(TSub#(n,TDiv#(n,2)),a)) infifo1 <- mkFIFOF;\n      rule splitinput;\n\t let v = inpipe.first();\n\t inpipe.deq();\n\t infifo0.enq(takeAt(0, v));\n\t infifo1.enq(takeAt(valueOf(TDiv#(n,2)), v));\n      endrule\n      PipeOut#(Vector#(TDiv#(n,2),a)) inpipe0 = toPipeOut(infifo0);\n      PipeOut#(Vector#(TSub#(n,TDiv#(n,2)),a)) inpipe1 = toPipeOut(infifo1);\n   \n      PipeOut#(a) p0 <- mkReducePipe(combinepipe, inpipe0);\n      PipeOut#(a) p1 <- mkReducePipe(combinepipe, inpipe1);\n\n      function a foo(Tuple2#(a,a) invec); \n\t return combinepipe(invec);\n      endfunction\n      let pipe <- mkMapPipe(foo,zipPipeOut(p0, p1));\n      return pipe;\n   endmodule\n\n   module  mkReducePipes#(CombinePipe#(Tuple2#(a,a), a) combinepipe,\n\t\t\t  Vector#(n, PipeOut#(a)) inpipes)\n\t\t\t (PipeOut#(a));\n      Vector#(TDiv#(n,2),PipeOut#(a)) pipes0 = takeAt(0, inpipes);\n      Vector#(TSub#(n,TDiv#(n,2)),PipeOut#(a)) pipes1 = takeAt(valueOf(TDiv#(n,2)), inpipes);\n\n      PipeOut#(a) p0 <- mkReducePipes(combinepipe, pipes0);\n      PipeOut#(a) p1 <- mkReducePipes(combinepipe, pipes1);\n\n      function a foo(Tuple2#(a,a) invec); \n\t return combinepipe(invec);\n      endfunction\n      let pipe <- mkMapPipe(foo,zipPipeOut(p0, p1));\n      return pipe;\n   endmodule\nendinstance\n\ninterface FirstLastPipe#(type a);\n   interface PipeOut#(Tuple2#(Bool,Bool)) pipe;\n   method Action start(a count);\nendinterface\n\nmodule mkFirstLastPipe(FirstLastPipe#(a))\n   provisos (Bits#(a,asz), Ord#(a), Arith#(a), Eq#(a));\n   Reg#(a) countReg <- mkReg(0);\n   Reg#(Bool) firstReg <- mkReg(False);\n   Reg#(Bool) lastReg <- mkReg(False);\n   interface PipeOut pipe;\n      method Tuple2#(Bool, Bool) first();\n\t return tuple2(firstReg, lastReg);\n      endmethod\n      method Action deq() if (countReg > 0);\n\t firstReg <= False;\n\t let c = countReg - 1;\n\t if (c == 1)\n\t    lastReg <= True;\n\t countReg <= c;\n      endmethod\n      method Bool notEmpty();\n\t return countReg > 0;\n      endmethod\n   endinterface\n   method Action start(a count) if (countReg == 0);\n      firstReg <= True;\n      lastReg <= False;\n      countReg <= count;\n   endmethod\nendmodule\n\ntypedef struct {\n   a xbase;\n   a xlimit;\n   a xstep;\n} IteratorConfig#(type a) deriving (Bits, FShow);\n\ntypedef struct {\n   a value;\n   Bool first;\n   Bool last;\n   b ctxt;\n} IteratorValue#(type a, type b) deriving (Bits);\nfunction a iteratorValueData(IteratorValue#(a,b) ivd); return ivd.value; endfunction\n\ninterface IteratorWithContext#(type a, type c);\n   interface PipeOut#(a) pipe;\n   interface PipeOut#(IteratorValue#(a,c)) ivpipe;\n   method a count();\n   method Bool isFirst();\n   method Bool isLast();\n   method Action start(IteratorConfig#(a) cfg, c ctxt);\n   method c ctxt();\nendinterface\n\ninterface IteratorIfc#(type a);\n   interface PipeOut#(a) pipe;\n   interface PipeOut#(IteratorValue#(a,void)) ivpipe;\n   method a count();\n   method Bool isFirst();\n   method Bool isLast();\n   method Action start(IteratorConfig#(a) cfg);\nendinterface\n\nmodule mkIteratorWithContext(IteratorWithContext#(a,c)) provisos (Arith#(a), Bits#(a,awidth), Eq#(a), Ord#(a), Bits#(c,cwidth));\n   Reg#(c) ctxtReg <- mkReg(unpack(0));\n   Reg#(a) countReg <- mkReg(0);\n   Reg#(a) x <- mkReg(0);\n   Reg#(a) xbase <- mkReg(0);\n   Reg#(a) xstep <- mkReg(0);\n   // inclusive limit\n   Reg#(a) xlimit <- mkReg(0);\n   Reg#(Bool) first <- mkReg(False);\n   Reg#(Bool) last <- mkReg(False);\n   Reg#(Bool) idle <- mkReg(True);\n   Bool verbose = False;\n   interface PipeOut pipe;\n      method a first();\n\t return x;\n      endmethod\n      method Action deq if (!idle);\n\t let next_x = x + xstep;\n\t countReg <= countReg + 1;\n\t x <= x + xstep;\n\t first <= False;\n\t last <= (x + xstep*2 >= xlimit);\n\t idle <= last;\n      endmethod\n      method Bool notEmpty();\n\t return !idle;\n      endmethod\n   endinterface\n   interface PipeOut ivpipe;\n      method IteratorValue#(a,c) first();\n\t return IteratorValue { value: x, first: first, last: last, ctxt: ctxtReg };\n      endmethod\n      method Action deq if (!idle);\n\t let next_x = x + xstep;\n\t countReg <= countReg + 1;\n\t x <= x + xstep;\n\t first <= False;\n\t last <= (x + xstep*2 >= xlimit);\n\t idle <= last;\n      endmethod\n      method Bool notEmpty();\n\t return !idle;\n      endmethod\n   endinterface\n   method Action start(IteratorConfig#(a) cfg, c ctxt) if (idle);\n      countReg <= 0;\n      x <= cfg.xbase;\n      xbase <= cfg.xbase;\n      xstep <= cfg.xstep;\n      xlimit <= cfg.xlimit;\n\n      first <= True;\n      last <= (cfg.xbase+cfg.xstep >= cfg.xlimit);\n      idle <= False;\n      ctxtReg <= ctxt;\n      if (verbose) $display(\"mkIterator xbase=%d xstep=%d xlimit=%d last=%d notEmpty=%d\", cfg.xbase, cfg.xstep, cfg.xlimit, (cfg.xbase+cfg.xstep >= cfg.xlimit),\n\t (cfg.xbase < cfg.xlimit));\n   endmethod\n   method Bool isFirst() = first;\n   method Bool isLast() = last;\n   method a count() = countReg;\n   method c ctxt() = ctxtReg;\nendmodule: mkIteratorWithContext\n\nmodule mkIterator(IteratorIfc#(a)) provisos (Arith#(a), Bits#(a,awidth), Eq#(a), Ord#(a));\n   IteratorWithContext#(a,void) iter <- mkIteratorWithContext();\n   interface PipeOut pipe = iter.pipe;\n   interface PipeOut ivpipe = iter.ivpipe;\n   method Action start(IteratorConfig#(a) cfg);\n      iter.start(cfg, ?);\n   endmethod\n   method a count() = iter.count();\n   method isFirst = iter.isFirst;\n   method isLast = iter.isLast;\nendmodule\n\ntypedef struct {\n   a xbase;\n   a xlimit;\n   a xstep;\n   a ybase;\n   a ylimit;\n   a ystep;\n} XYIteratorConfig#(type a) deriving (Bits, FShow);\n\ninterface XYIteratorIfc#(type a);\n   interface PipeOut#(Tuple2#(a,a)) pipe;\n   method Bool isFirst();\n   method Bool isLast();\n   method Action start(XYIteratorConfig#(a) cfg);\n   method Action display();\nendinterface\n\nmodule mkXYIterator(XYIteratorIfc#(a)) provisos (Arith#(a), Bits#(a,awidth), Eq#(a), Ord#(a));\n   Reg#(a) x <- mkReg(0);\n   Reg#(a) y <- mkReg(0);\n   Reg#(a) xbase <- mkReg(0);\n   Reg#(a) ybase <- mkReg(0);\n   Reg#(a) xstep <- mkReg(0);\n   Reg#(a) ystep <- mkReg(0);\n   Reg#(a) xlimit <- mkReg(0);\n   Reg#(a) ylimit <- mkReg(0);\n   \n   Reg#(Bool) isFirstReg <- mkReg(False);\n   Reg#(Bool) isLastReg <- mkReg(False);\n\n   let guard = x < xlimit && y < ylimit;\n   \n   interface PipeOut pipe;\n      method Tuple2#(a,a) first() if (guard);\n\t return tuple2(x,y);\n      endmethod\n      method Action deq if (guard);\n\t let newx = x;\n\t let newy = y+ystep;\n\t if (newy >= ylimit && x < xlimit) begin\n\t    newy = ybase;\n\t    newx = newx + xstep;\n\t end\n\t x <= newx;\n\t y <= newy;\n\t isLastReg <= (newx+xstep >= xlimit && newy+ystep >= ylimit);\n\t isFirstReg <= False;\n      endmethod\n      method Bool notEmpty();\n\t return guard;\n      endmethod\n   endinterface\n   method Action start(XYIteratorConfig#(a) cfg) if (!guard);\n      x <= cfg.xbase;\n      y <= cfg.ybase;\n      xbase <= cfg.xbase;\n      ybase <= cfg.ybase;\n      xstep <= cfg.xstep;\n      ystep <= cfg.ystep;\n      xlimit <= cfg.xlimit;\n      ylimit <= cfg.ylimit;\n      isFirstReg <= True;\n      isLastReg <= (cfg.xbase+cfg.xstep) > cfg.xlimit && (cfg.ybase+cfg.ystep) > cfg.ylimit;\n   endmethod\n   method Bool isFirst(); return isFirstReg; endmethod\n   method Bool isLast(); return isLastReg; endmethod\n   method Action display();\n      $display(\"XYIterator x=%d xlimit=%d y=%d ylimit=%d xstep=%d ystep=%d\", x, xlimit, xstep, y, ylimit, ystep);\n   endmethod\nendmodule: mkXYIterator\n\ninstance MkAxiStream#(AxiStreamMaster#(dsize), PipeOut#(dtype)) provisos (Bits#(dtype,dsize));\n   module mkAxiStream#(PipeOut#(dtype) f)(AxiStreamMaster#(dsize));\n      Wire#(Bool) readyWire <- mkDWire(False);\n      rule rl_deq if (readyWire && f.notEmpty);\n\t f.deq();\n      endrule\n     method Bit#(dsize)              tdata();\n\tif (f.notEmpty())\n\t  return pack(f.first());\n\telse\n\t  return 0;\n     endmethod\n     method Bit#(TDiv#(dsize,8))     tkeep(); return maxBound; endmethod\n     method Bit#(1)                tlast(); return 0; endmethod\n     method Action                 tready(Bit#(1) v);\n\treadyWire <= unpack(v);\n     endmethod\n     method Bit#(1)                tvalid(); return pack(f.notEmpty()); endmethod\n   endmodule\nendinstance\n\ninstance MkAxiStream#(AxiStreamSlave#(dsize), PipeIn#(dtype)) provisos (Bits#(dtype,dsize));\n   module mkAxiStream#(PipeIn#(dtype) f)(AxiStreamSlave#(dsize));\n      Wire#(Bit#(dsize)) dataWire <- mkDWire(unpack(0));\n      Wire#(Bool) validWire <- mkDWire(False);\n      rule enq if (validWire && f.notFull());\n\t f.enq(unpack(dataWire));\n      endrule\n      method Action      tdata(Bit#(dsize) v);\n\t dataWire <= v;\n      endmethod\n      method Action      tkeep(Bit#(TDiv#(dsize,8)) v); endmethod\n      method Action      tlast(Bit#(1) v); endmethod\n      method Bit#(1)     tready(); return pack(f.notFull()); endmethod\n      method Action      tvalid(Bit#(1) v);\n\t validWire <= unpack(v);\n      endmethod\n   endmodule\nendinstance\n\ninstance Connectable#(AxiStreamMaster#(dataWidth), PipeIn#(dtype))\n   provisos (Bits#(dtype, dataWidth));\n   module mkConnection#(AxiStreamMaster#(dataWidth) from, PipeIn#(dtype) to)(Empty);\n      rule rl_ready;\n\t from.tready(pack(to.notFull));\n      endrule\n      rule rl_enq if (from.tvalid == 1);\n\t to.enq(unpack(from.tdata));\n      endrule\n   endmodule\nendinstance\n\ninstance Connectable#(PipeOut#(dtype), AxiStreamSlave#(dataWidth))\n   provisos (Bits#(dtype, dataWidth));\n   module mkConnection#(PipeOut#(dtype) from, AxiStreamSlave#(dataWidth) to)(Empty);\n      rule rl_tvalid;\n\t to.tvalid(pack(from.notEmpty()));\n      endrule\n      rule rl_axi_stream;\n\t to.tdata(pack(from.first));\n\t to.tkeep(maxBound);\n\t to.tlast(0);\n      endrule\n      rule rl_deq if (to.tready == 1);\n\t from.deq();\n      endrule\n   endmodule\nendinstance\n"
  },
  {
    "path": "bsv/Platform.bsv",
    "content": "// Copyright (c) 2015 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\nimport ConnectalConfig::*;\nimport Vector::*;\nimport BuildVector::*;\nimport Portal::*;\nimport HostInterface::*;\nimport ConnectalMMU::*;\nimport MemServer::*;\nimport ConnectalMemTypes::*;\nimport CtrlMux::*;\nimport FIFO::*;\nimport GetPut::*;\nimport SpecialFIFOs::*;\nimport Pipe::*;\nimport ConnectalMemory::*;\nimport MMURequest::*;\nimport MMUIndication::*;\nimport MemServerIndication::*;\nimport MemServerRequest::*;\nimport IfcNames::*;\n`include \"ConnectalProjectConfig.bsv\"\nimport `PinTypeInclude::*;\n\ninterface Platform;\n   interface PhysMemSlave#(32,32) slave;\n   interface Vector#(NumberOfMasters,PhysMemMaster#(PhysAddrWidth, DataBusWidth)) masters;\n   interface Vector#(MaxNumberOfPortals,ReadOnly#(Bool)) interrupt;\n   interface `PinType pins;\nendinterface\n\ntypedef TMax#(TLog#(TSub#(NumberOfTiles,1)),1) TileTagBits;\nfunction Bit#(TSub#(MemTagSize,TileTagBits)) tagLsb(Bit#(MemTagSize) tag); return truncate(tag); endfunction\nfunction Bit#(TileTagBits) tagMsb(Bit#(MemTagSize) tag); return truncate(tag >> valueOf(TSub#(MemTagSize,TileTagBits))); endfunction\n\nmodule renameReads#(Integer tile, MemReadClient#(DataBusWidth) reader, MemServerIndication err)(MemReadClient#(DataBusWidth));\n   interface Get readReq;\n      method ActionValue#(MemRequest) get;\n\t let req <- reader.readReq.get;\n\t Bit#(TSub#(MemTagSize,TileTagBits)) lsb = tagLsb(req.tag);\n\t Bit#(TileTagBits) msb = tagMsb(req.tag);\n\t if(req.tag != extend(lsb) && valueOf(NumberOfTiles) > 2) begin // one mgmt tile and one user tile\n\t    $display(\"renameReads tile tag out of range: 'h%h\", req.tag);\n\t    err.error(extend(pack(DmaErrorTileTagOutOfRange)), req.sglId, extend(req.tag), fromInteger(tile));\n\t end\n\t req.tag = {fromInteger(tile),lsb};\n\t return req;\n      endmethod\n   endinterface\n   interface Put readData;\n      method Action put(MemData#(DataBusWidth) v);\n\t reader.readData.put(MemData{data:v.data,\n                                     tag:{0,tagLsb(v.tag)},\n`ifdef BYTE_ENABLES_MEM_DATA\n\t\t\t\t     byte_enables: v.byte_enables,\n`endif\n                                     last:v.last});\n      endmethod\n   endinterface\nendmodule\n\nmodule renameWrites#(Integer tile, MemWriteClient#(DataBusWidth) writer, MemServerIndication err)(MemWriteClient#(DataBusWidth));\n   interface Get writeReq;\n      method ActionValue#(MemRequest) get;\n\t let req <- writer.writeReq.get;\n\t Bit#(TSub#(MemTagSize,TileTagBits)) lsb = tagLsb(req.tag);\n\t Bit#(TileTagBits) msb = tagMsb(req.tag);\n\t if(req.tag != extend(lsb) && valueOf(NumberOfTiles) > 2) begin // one mgmt tile and one user tile\n\t    $display(\"renameWrites tile tag out of range: 'h%h\", req.tag);\n\t    err.error(extend(pack(DmaErrorTileTagOutOfRange)), req.sglId, extend(req.tag), fromInteger(tile));\n\t end\n\t req.tag = {fromInteger(tile),lsb};\n\t return req;\n      endmethod\n   endinterface\n   interface Get writeData;\n      method ActionValue#(MemData#(DataBusWidth)) get;\n\t let rv <- writer.writeData.get;\n   \t return MemData{data:rv.data,\n                        tag:{0,tagLsb(rv.tag)},\n`ifdef BYTE_ENABLES_MEM_DATA\n                             byte_enables: rv.byte_enables,\n`endif\n                             last:rv.last};\n      endmethod\n   endinterface\n   interface Put writeDone;\n      method Action put(Bit#(MemTagSize) v);\n\t writer.writeDone.put({0,tagLsb(v)});\n      endmethod\n   endinterface\nendmodule\n\nmodule mkPlatform#(Vector#(NumberOfUserTiles, ConnectalTop#(`PinType)) tiles)(Platform);\n   /////////////////////////////////////////////////////////////\n   // connecting up the tiles\n\n   Vector#(NumberOfUserTiles, PhysMemSlave#(18,32)) tile_slaves;\n   Vector#(NumberOfUserTiles, ReadOnly#(Bool)) tile_interrupts;\n   Vector#(NumberOfUserTiles, Vector#(NumReadClients, MemReadClient#(DataBusWidth))) tile_read_clients;\n   Vector#(NumberOfUserTiles, Vector#(NumWriteClients, MemWriteClient#(DataBusWidth))) tile_write_clients;\n   Vector#(NumberOfUserTiles, Vector#(NumReadClients, Integer)) read_client_tile_numbers;\n   Vector#(NumberOfUserTiles, Vector#(NumWriteClients, Integer)) write_client_tile_numbers;\n   for(Integer i = 0; i < valueOf(NumberOfUserTiles); i=i+1) begin\n      tile_slaves[i] = tiles[i].slave;\n      let imux <- mkInterruptMux(tiles[i].interrupt);\n      //ReadOnly#(Bool) imux = tiles[i].interrupt;\n      tile_interrupts[i] = imux;\n      tile_read_clients[i] = tiles[i].readers;\n      tile_write_clients[i] = tiles[i].writers;\n      read_client_tile_numbers[i] = replicate(i);\n      write_client_tile_numbers[i] = replicate(i);\n   end\n\n   /////////////////////////////////////////////////////////////\n   // framework internal portals\n\n   MMUIndicationProxy lMMUIndicationProxy <- mkMMUIndicationProxy(PlatformIfcNames_MMUIndicationH2S);\n   MemServerIndicationProxy lMemServerIndicationProxy <- mkMemServerIndicationProxy(PlatformIfcNames_MemServerIndicationH2S);\n\n`ifdef USE_SIMPLE_MMU\n   MMU#(PhysAddrWidth) lMMU <- mkSimpleMMU(0,True, lMMUIndicationProxy.ifc);\n`else\n   MMU#(PhysAddrWidth) lMMU <- mkMMU(0,True, lMMUIndicationProxy.ifc);\n`endif\n   Vector#(TMul#(NumberOfUserTiles,NumReadClients), MemReadClient#(DataBusWidth)) tile_read_clients_renamed <- zipWith3M(renameReads, concat(read_client_tile_numbers), concat(tile_read_clients), replicate(lMemServerIndicationProxy.ifc));\n   Vector#(TMul#(NumberOfUserTiles,NumWriteClients), MemWriteClient#(DataBusWidth)) tile_write_clients_renamed <- zipWith3M(renameWrites, concat(write_client_tile_numbers), concat(tile_write_clients), replicate(lMemServerIndicationProxy.ifc));\n   MemServer#(PhysAddrWidth,DataBusWidth,NumberOfMasters) lMemServer <- mkMemServer(tile_read_clients_renamed, tile_write_clients_renamed, vec(lMMU), lMemServerIndicationProxy.ifc);\n\n   MMURequestWrapper lMMURequestWrapper <- mkMMURequestWrapper(PlatformIfcNames_MMURequestS2H, lMMU.request);\n   MemServerRequestWrapper lMemServerRequestWrapper <- mkMemServerRequestWrapper(PlatformIfcNames_MemServerRequestS2H, lMemServer.request);\n\n   Vector#(4,StdPortal) framework_portals;\n   framework_portals[0] = lMMUIndicationProxy.portalIfc;\n   framework_portals[1] = lMemServerIndicationProxy.portalIfc;\n   framework_portals[2] = lMMURequestWrapper.portalIfc;\n   framework_portals[3] = lMemServerRequestWrapper.portalIfc;\n   PhysMemSlave#(18,32) framework_ctrl_mux <- mkSlaveMux(framework_portals);\n   let framework_intr <- mkInterruptMux(getInterruptVector(framework_portals));\n   \n   /////////////////////////////////////////////////////////////\n   // expose interface to top\n\n   PhysMemSlave#(32,32) ctrl_mux <- mkPhysMemSlaveMux(cons(framework_ctrl_mux,tile_slaves));\n   Vector#(MaxNumberOfPortals, ReadOnly#(Bool)) interrupts = replicate(interface ReadOnly; method Bool _read(); return False; endmethod endinterface);\n   interrupts[0] = framework_intr;\n   for (Integer i = 1; i < valueOf(NumberOfTiles); i = i + 1)\n      interrupts[i] = tile_interrupts[i-1];\n   interface interrupt = interrupts;\n   interface slave = ctrl_mux;\n   interface masters = lMemServer.masters;\n   interface pins = tiles[0].pins;\nendmodule\n"
  },
  {
    "path": "bsv/Portal.bsv",
    "content": "// Copyright (c) 2013 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\nimport ConnectalConfig::*;\nimport Vector::*;\nimport ConnectalMemTypes::*;\nimport Pipe::*;\nimport ConnectalMemory::*;\nimport HostInterface::*;\n`include \"ConnectalProjectConfig.bsv\"\nimport `PinTypeInclude::*;\n\ninterface PortalInterrupt#(numeric type dataWidth);\n   method Bool status();\n   method Bit#(dataWidth) channel();\nendinterface\n\ninterface PortalSize;\n   method Bit#(16) size(Bit#(16) methodNumber);\nendinterface\n\ntypeclass PortalMessageSize#(type t);\n   function Bit#(16) portalMessageSize(t p, Bit#(16) methodNumber);\nendtypeclass\n\n// implementation of a Portal as a group of Pipes\ninterface PipePortal#(numeric type numRequests, numeric type numIndications, numeric type slaveDataWidth);\n   interface PortalSize messageSize;\n   interface Vector#(numRequests, PipeIn#(Bit#(slaveDataWidth))) requests;\n   //method PipeIn#(Bit#(slaveDataWidth)) requestsPipe(Integer a);\n   interface Vector#(numIndications, PipeOut#(Bit#(slaveDataWidth))) indications;\n   //method PipeOut#(Bit#(slaveDataWidth)) indicationsPipe(Integer a);\n   interface PortalInterrupt#(slaveDataWidth) intr;\nendinterface\n\n// implementation of a Portal as a physical memory slave\ninterface MemPortal#(numeric type slaveAddrWidth, numeric type slaveDataWidth);\n   interface PhysMemSlave#(slaveAddrWidth,slaveDataWidth) slave;\n   interface ReadOnly#(Bool) interrupt;\n   interface WriteOnly#(Bit#(slaveDataWidth)) num_portals;\nendinterface\n\nfunction ReadOnly#(Bool) getInterrupt(MemPortal#(_a,_d) p);\n   return p.interrupt;\nendfunction\n\nfunction Vector#(MaxNumberOfPortals, ReadOnly#(Bool)) getInterruptVector(Vector#(numPortals, MemPortal#(_a,_d)) portals);\n   Vector#(MaxNumberOfPortals, ReadOnly#(Bool)) interrupts = replicate(interface ReadOnly; method Bool _read(); return False; endmethod endinterface);\n   for (Integer i = 0; i < valueOf(numPortals); i = i + 1)\n      interrupts[i] = getInterrupt(portals[i]);\n   return interrupts;\nendfunction\n\ninterface SharedMemoryPortalConfig;\n   method Action setSglId(Bit#(32) sglId);\nendinterface\n\ninterface SharedMemoryPortal#(numeric type dataBusWidth);\n   interface SharedMemoryPortalConfig cfg;\n   interface ReadOnly#(Bool) interrupt;\nendinterface\n\ntypedef MemPortal#(12,32) StdPortal;\n\ninterface ConnectalTop#(type pinType);\n   interface PhysMemSlave#(18,32) slave;\n   interface Vector#(MaxNumberOfPortals,ReadOnly#(Bool)) interrupt;\n   interface Vector#(NumReadClients,MemReadClient#(DataBusWidth)) readers;\n   interface Vector#(NumWriteClients,MemWriteClient#(DataBusWidth)) writers;\n`ifdef TOP_SOURCES_PORTAL_CLOCK\n   interface Clock portalClockSource;\n`endif\n   interface pinType pins;\nendinterface\n"
  },
  {
    "path": "bsv/SimDma.bsv",
    "content": "// Copyright (c) 2015 Connectal Project\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\nimport Vector::*;\nimport FIFO::*;\nimport FIFOF::*;\nimport GetPut::*;\n\nimport ConnectalMemTypes::*;\nimport ConnectalConfig::*;\n\n`include \"ConnectalProjectConfig.bsv\"\n\n`ifdef SIM_DMA_READ_LATENCY\ntypedef `SIM_DMA_READ_LATENCY SimDmaReadLatency;\n`else\ntypedef 150 SimDmaReadLatency;\n`endif\n`ifdef SIM_DMA_WRITE_LATENCY\ntypedef `SIM_DMA_WRITE_LATENCY SimDmaWriteLatency;\n`else\ntypedef 150 SimDmaWriteLatency;\n`endif\n\ninterface SimDma#(numeric type dataWidth);\n   method Action init(Bit#(32) id, Bit#(32) handle, Bit#(32) size);\n   method Action initfd(Bit#(32) id, Bit#(32) fd);\n   method Action idreturn(Bit#(32) id);\n   method Action write(Bit#(32) handle, Bit#(32) addr, Bit#(dataWidth) v, Bit#(TDiv#(dataWidth,8)) byteEnable);\n   method Action readrequest(Bit#(32) handle, Bit#(32) addr);\n   method ActionValue#(Bit#(dataWidth)) readresponse();\nendinterface\n\n`ifdef BOARD_bluesim\nimport \"BDPI\" function ActionValue#(Bit#(32)) simDma_init(Bit#(32) id, Bit#(32) handle, Bit#(32) size);\nimport \"BDPI\" function ActionValue#(Bit#(32)) simDma_initfd(Bit#(32) id, Bit#(32) fd);\nimport \"BDPI\" function ActionValue#(Bit#(32)) simDma_idreturn(Bit#(32) id);\n\n// implemented in BsimDma.cpp\nimport \"BDPI\" function Action write_simDma32(Bit#(32) handle, Bit#(32) addr, Bit#(32) v, Bit#(4) byteEnable);\nimport \"BDPI\" function Action write_simDma64(Bit#(32) handle, Bit#(32) addr, Bit#(64) v, Bit#(8) byteEnable);\nimport \"BDPI\" function ActionValue#(Bit#(32)) read_simDma32(Bit#(32) handle, Bit#(32) addr);\nimport \"BDPI\" function ActionValue#(Bit#(64)) read_simDma64(Bit#(32) handle, Bit#(32) addr);\n\nmodule mkSimDma(SimDma#(dataWidth) ifc)\n   provisos (Mul#(TDiv#(dataWidth, 32), 32, dataWidth),\n\t     Bits#(Vector#(TDiv#(dataWidth, 32), Bit#(4)), TDiv#(dataWidth, 8))\n\t     );\n   FIFO#(Bit#(dataWidth)) dataFifo <- mkFIFO();\n      method Action init(Bit#(32) id, Bit#(32) handle, Bit#(32) size);\n\t let v <- simDma_init(id, handle, size);\n\t //return v;\n      endmethod\n      method Action initfd(Bit#(32) id, Bit#(32) fd);\n\t let v <- simDma_initfd(id, fd);\n\t //return v;\n      endmethod\n      method Action idreturn(Bit#(32) id);\n\t let v <- simDma_idreturn(id);\n\t //return v;\n      endmethod\n      method Action write(Bit#(32) handle, Bit#(32) addr, Bit#(dataWidth) v, Bit#(TDiv#(dataWidth,8)) byteEnable);\n          let aligned_addr = addr & ~7;\n\t  Vector#(TDiv#(dataWidth, 32), Bit#(32)) vs = unpack(v);\n\t  Vector#(TDiv#(dataWidth, 32), Bit#(4)) byteEnables = unpack(byteEnable);\n\t  function Action write32(Integer i);\n\t     action\n\t\twrite_simDma32(handle, aligned_addr+4*fromInteger(i), vs[i], byteEnables[i]);\n\t     endaction\n\t  endfunction\n\t Vector#(TDiv#(dataWidth,32),Integer) indices = genVector();\n\t mapM_(write32, indices);\n      endmethod\n      method Action  readrequest(Bit#(32) handle, Bit#(32) addr);\n\t  function ActionValue#(Bit#(32)) read32(Integer i);\n\t     actionvalue\n\t\tlet v <- read_simDma32(handle, addr+4*fromInteger(i));\n\t\treturn v;\n\t     endactionvalue\n\t  endfunction\n   \t  Vector#(TDiv#(dataWidth,32),Bit#(32)) vs <- mapM(read32, genVector());\n\t  dataFifo.enq(pack(vs));\n      endmethod\n      method ActionValue#(Bit#(dataWidth)) readresponse();\n          let v <- toGet(dataFifo).get();\n\t  return v;\n      endmethod\nendmodule\n`endif\n\t\t \n`ifdef SVDPI\ninterface XsimDmaReadWrite;\n   method Action init(Bit#(32) id, Bit#(32) handle, Bit#(32) size);\n   method Action initfd(Bit#(32) id, Bit#(32) fd);\n   method Action idreturn(Bit#(32) id);\n   method Action write32(Bit#(32) handle, Bit#(32) addr, Bit#(32) v, Bit#(4) byteEnable);\n   method Action readrequest(Bit#(32) handle, Bit#(32) addr);\n   method ActionValue#(Bit#(32)) readresponse();\nendinterface\n\nimport \"BVI\" XsimDmaReadWrite =\nmodule mkXsimReadWrite(XsimDmaReadWrite);\n   method init(init_id, init_handle, init_size) enable (en_init);\n   method initfd(initfd_id, initfd_fd) enable (en_initfd);\n   method idreturn(idreturn_id) enable (en_idreturn);\n   method write32(write32_handle, write32_addr, write32_data, write32_byteenable) enable (en_write32);\n   method readrequest(readrequest_handle, readrequest_addr) enable (en_readrequest) ready (rdy_readrequest);\n   method readresponse_data readresponse() enable (en_readresponse) ready (rdy_readresponse);\n   schedule (init, initfd, write32, readrequest, readresponse, idreturn) CF (init, initfd, write32, readrequest, readresponse, idreturn);\nendmodule\n\nmodule mkSimDma(SimDma#(dataWidth) ifc)\n   provisos (Mul#(TDiv#(dataWidth, 32), 32, dataWidth),\n\t     Bits#(Vector#(TDiv#(dataWidth, 32), Bit#(4)), TDiv#(dataWidth, 8)));\n   Vector#(TDiv#(dataWidth,32),XsimDmaReadWrite) rws <- replicateM(mkXsimReadWrite());\n   method Action init(Bit#(32) id, Bit#(32) handle, Bit#(32) size);\n      rws[0].init(id, handle, size);\n   endmethod\n   method Action initfd(Bit#(32) id, Bit#(32) fd);\n      rws[0].initfd(id, fd);\n   endmethod\n   method Action idreturn(Bit#(32) id);\n      rws[0].idreturn(id);\n   endmethod\n   method Action write(Bit#(32) handle, Bit#(32) addr, Bit#(dataWidth) v, Bit#(TDiv#(dataWidth,8)) byteEnable);\n      Vector#(TDiv#(dataWidth, 32), Bit#(32)) vs = unpack(v);\n      Vector#(TDiv#(dataWidth, 32), Bit#(4)) byteEnables = unpack(byteEnable);\n      let aligned_addr = addr & ~7;\n      function Action write32(Integer i);\n\t action\n\t    rws[i].write32(handle, aligned_addr+4*fromInteger(i), vs[i], byteEnables[i]);\n\t endaction\n      endfunction\n      Vector#(TDiv#(dataWidth,32),Integer) indices = genVector();\n      mapM_(write32, indices);\n   endmethod\n   method Action readrequest(Bit#(32) handle, Bit#(32) addr);\n      function Action doreadrequest(Integer i);\n\t action\n\t    rws[i].readrequest(handle, addr+4*fromInteger(i));\n\t endaction\n      endfunction\n      Vector#(TDiv#(dataWidth,32),Integer) indexes = genVector();\n      mapM_(doreadrequest, indexes);\n   endmethod\n   method ActionValue#(Bit#(dataWidth)) readresponse();\n      function ActionValue#(Bit#(32)) readresponse32(Integer i);\n\t actionvalue\n\t    let v <- rws[i].readresponse();\n\t    return v;\n\t endactionvalue\n      endfunction\n      Vector#(TDiv#(dataWidth,32),Bit#(32)) vs <- mapM(readresponse32, genVector());\n      return pack(vs);\n   endmethod\nendmodule\n`endif\n\n`ifndef SIMULATION\nmodule mkSimDma(SimDma#(dataWidth) ifc);\n   method Action init(Bit#(32) id, Bit#(32) handle, Bit#(32) size);\n   endmethod\n   method Action initfd(Bit#(32) id, Bit#(32) fd);\n   endmethod\n   method Action idreturn(Bit#(32) id);\n   endmethod\n   method Action write(Bit#(32) handle, Bit#(32) addr, Bit#(dataWidth) v, Bit#(TDiv#(dataWidth,8)) byteEnable);\n   endmethod\n   method Action readrequest(Bit#(32) handle, Bit#(32) addr);\n   endmethod\n   method ActionValue#(Bit#(dataWidth)) readresponse();\n      return 0;\n   endmethod\nendmodule\n`endif // SIMULATION\n\nmodule mkSimDmaDmaMaster(PhysMemSlave#(serverAddrWidth,serverBusWidth))\n   provisos(Div#(serverBusWidth,8,dataWidthBytes),\n\t    Mul#(dataWidthBytes,8,serverBusWidth),\n\t    Log#(dataWidthBytes,beatShift),\n\t    Mul#(TDiv#(serverBusWidth, 32), 32, serverBusWidth),\n\t    Mul#(TDiv#(serverBusWidth, 32), 4, TDiv#(serverBusWidth, 8)),\n\t    Bits#(Tuple2#(Bit#(64), PhysMemRequest#(serverAddrWidth,serverBusWidth)), a__),\n\t    Add#(b__, ByteEnableSize, TDiv#(serverBusWidth, 8))\n\t    );\n\n   let verbose = False;\n   SimDma#(serverBusWidth) rw <- mkSimDma();\n\n   Reg#(Bit#(BurstLenSize))  readLenReg <- mkReg(0);\n   Reg#(Bit#(32))         readOffsetReg <- mkReg(0);\n\n   Reg#(Bit#(BurstLenSize))  writeLenReg <- mkReg(0);\n   Reg#(Bit#(32))         writeOffsetReg <- mkReg(0);\n\n   let readLatency_I = valueOf(SimDmaReadLatency);\n   let writeLatency_I = valueOf(SimDmaWriteLatency);\n\n   Bit#(64) readLatency = fromInteger(readLatency_I);\n   Bit#(64) writeLatency = fromInteger(writeLatency_I);\n\n   Reg#(Bit#(64)) req_ar_b_ts <- mkReg(0);\n   Reg#(Bit#(64)) req_aw_b_ts <- mkReg(0);\n   Reg#(Bit#(64)) cycles <- mkReg(0);\n   Reg#(Bit#(64)) last_reqAr <- mkReg(0);\n   Reg#(Bit#(64)) last_read_eob <- mkReg(0);\n   Reg#(Bit#(64)) last_write_eob <- mkReg(0);\n\n   FIFOF#(Tuple2#(Bit#(64), PhysMemRequest#(serverAddrWidth,serverBusWidth)))  readDelayFifo <- mkSizedFIFOF(readLatency_I);\n   FIFOF#(Tuple2#(Bit#(64),PhysMemRequest#(serverAddrWidth,serverBusWidth))) writeDelayFifo <- mkSizedFIFOF(writeLatency_I);\n\n   FIFOF#(Tuple2#(Bit#(64), Bit#(MemTagSize))) bFifo <- mkSizedFIFOF(writeLatency_I);\n   FIFOF#(Tuple2#(Bit#(MemTagSize),Bool)) taglastfifo <- mkFIFOF();\n   rule increment_cycle;\n      cycles <= cycles+1;\n   endrule\n\n   let read_jitter = True; //cycles[4:0] == 0;\n   let write_jitter = True; //cycles[4:0] == 5;\n\n   Reg#(Bit#(8))  burstReg <- mkReg(0);\n   FIFO#(Bit#(8)) reqs <- mkSizedFIFO(32);\n   \n   let beat_shift = fromInteger(valueOf(beatShift));\n\n   rule read_rule if (readDelayFifo.notEmpty() && (cycles-tpl_1(readDelayFifo.first) >= readLatency));\n\t match { .reqTime, .req } = readDelayFifo.first;\n\t Bit#(BurstLenSize) readLen = readLenReg;\n\t Bit#(32) readOffset = readOffsetReg;\n\t Bit#(MemTagSize) tag = req.tag;\n\t Bit#(8) handle = req.addr[39:32];\n\n\t if (readLen == 0) begin\n\t    req_ar_b_ts <= cycles;\n\t    readLen     = req.burstLen>>beat_shift;\n\t    readOffset  = 0;\n\t end\n\t rw.readrequest(extend(handle), req.addr[31:0]+readOffset);\n\t let last = (readLen == 1);\n\t if (last)\n\t    readDelayFifo.deq();\n\t taglastfifo.enq(tuple2(tag, last));\n\t readLenReg <= readLen - 1;\n\t readOffsetReg <= readOffset + fromInteger(valueOf(serverBusWidth)/8);\n   endrule\n\n   interface PhysMemReadServer read_server;\n      interface Put readReq;\n\t method Action put(PhysMemRequest#(serverAddrWidth,serverBusWidth) req);\n            if (verbose) $display(\"mkSimDmaDmaMaster::%d axiSlave.read.readAddr %h bc %d\", cycles, req.addr, req.burstLen);\n\t    //readAddrGenerator.request.put(req);\n\t    readDelayFifo.enq(tuple2(cycles,req));\n\t endmethod\n      endinterface\n      interface Get readData;\n\t method ActionValue#(MemData#(serverBusWidth)) get();\n\t     match { .tag, .last } <- toGet(taglastfifo).get();\n \t     let v <- rw.readresponse();\n \t     //if (verbose) $display(\"mkSimDmaDmaMaster::%d axiSlave.read.readData %h tag %d last %d\", cycles, v, tag, last);\n\t     return MemData { data: v, tag: tag, last: last };\n\t endmethod\n      endinterface\n   endinterface\n   interface PhysMemWriteServer write_server;\n      interface Put writeReq;\n\t method Action put(PhysMemRequest#(serverAddrWidth,serverBusWidth) req);\n\t //$display(\"mkSimDmaDmaMaster::req_aw id=%d\", req.tag);\n\t writeDelayFifo.enq(tuple2(cycles,req));\n\t endmethod\n      endinterface\n      interface Put writeData;\n\t method Action put(MemData#(serverBusWidth) resp) if (writeDelayFifo.notEmpty && (cycles-tpl_1(writeDelayFifo.first)) >= writeLatency);\n\t    match { .reqTime, .req } = writeDelayFifo.first;\n\t    Bit#(BurstLenSize) writeLen = writeLenReg;\n\t    Bit#(32) writeOffset = writeOffsetReg;\n\t    Bit#(MemTagSize) tag = req.tag;\n\t    Bit#(8) handle = req.addr[39:32];\n\t    Bit#(TDiv#(serverBusWidth,8)) byteEnable = maxBound;\n\t    if (writeLen == 1) byteEnable = reqLastByteEnable(req);\n\t    if (writeLenReg == 0) begin\n\t       req_aw_b_ts <= cycles;\n\t       writeLen = req.burstLen>>beat_shift;\n\t       writeOffset = 0;\n\t       byteEnable = reqFirstByteEnable(req);\n\t    end\n`ifdef BYTE_ENABLES_MEM_DATA\n            byteEnable = resp.byte_enables;\n`endif\n\t    rw.write(extend(handle), req.addr[31:0] + writeOffset, resp.data, extend(byteEnable));\n\t    writeLenReg <= writeLen - 1;\n\t    writeOffsetReg <= writeOffset + fromInteger(valueOf(serverBusWidth)/8);\n\t    if (writeLen == 1) begin\n\t       bFifo.enq(tuple2(cycles,tag));\n\t       writeDelayFifo.deq;\n\t    end\n\t endmethod\n      endinterface\n      interface Get writeDone;\n\t method ActionValue#(Bit#(MemTagSize)) get() if ((cycles-tpl_1(bFifo.first)) >= writeLatency);\n\t bFifo.deq();\n\t return tpl_2(bFifo.first());\n\t endmethod\n      endinterface\n   endinterface\nendmodule\n"
  },
  {
    "path": "bsv/SimLink.bsv",
    "content": "// Copyright (c) 2015 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\nimport GetPut            :: *;\nimport Connectable       :: *;\nimport FIFOF             :: *;\nimport Pipe              :: *;\n\n`include \"ConnectalProjectConfig.bsv\"\n\ninterface SimLink#(numeric type dataWidth);\n   method Action start(Bit#(32) linknumber, Bool listening);\n   method Bool   linkUp();\n   interface PipeOut#(Bit#(dataWidth)) rx;\n   interface PipeIn#(Bit#(dataWidth)) tx;\nendinterface\n\n`ifdef BOARD_bluesim\nimport \"BDPI\" function Action                 bsimLinkOpen(Bit#(32) linknumber, Bool listening);\nimport \"BDPI\" function Bit#(1)                bsimLinkUp(Bit#(32) linknumber, Bool listening);\nimport \"BDPI\" function Bool                   bsimLinkCanReceive(Bit#(32) linknumber, Bool listening);\nimport \"BDPI\" function Bool                   bsimLinkCanTransmit(Bit#(32) linknumber, Bool listening);\nimport \"BDPI\" function ActionValue#(Bit#(32)) bsimLinkReceive32(Bit#(32) linknumber, Bool listening);\nimport \"BDPI\" function Action                 bsimLinkTransmit32(Bit#(32) linknumber, Bool listening, Bit#(32) value);\nimport \"BDPI\" function ActionValue#(Bit#(64)) bsimLinkReceive64(Bit#(32) linknumber, Bool listening);\nimport \"BDPI\" function Action                 bsimLinkTransmit64(Bit#(32) linknumber, Bool listening, Bit#(64) value);\n\ntypeclass SelectLinkWidth#(numeric type dsz);\n   function ActionValue#(Bit#(dsz)) bsimLinkReceive(Bit#(32) linknumber, Bool listening);\n   function Action bsimLinkTransmit(Bit#(32) linknumber, Bool listening, Bit#(dsz) value);\nendtypeclass\n\ninstance SelectLinkWidth#(32);\n   function ActionValue#(Bit#(32)) bsimLinkReceive(Bit#(32) linknumber, Bool listening);\n   actionvalue\n      let v <- bsimLinkReceive32(linknumber, listening);\n      return v;\n   endactionvalue\n   endfunction\n   function Action bsimLinkTransmit(Bit#(32) linknumber, Bool listening, Bit#(32) value);\n   action\n      bsimLinkTransmit32(linknumber, listening, value);\n   endaction\n   endfunction\nendinstance\ninstance SelectLinkWidth#(64);\n   function ActionValue#(Bit#(64)) bsimLinkReceive(Bit#(32) linknumber, Bool listening);\n   actionvalue\n      let v <- bsimLinkReceive64(linknumber, listening);\n      return v;\n   endactionvalue\n   endfunction\n   function Action bsimLinkTransmit(Bit#(32) linknumber, Bool listening, Bit#(64) value);\n   action\n      bsimLinkTransmit64(linknumber, listening, value);\n   endaction\n   endfunction\nendinstance\n\nmodule mkSimLink(SimLink#(dataWidth)) provisos (SelectLinkWidth#(dataWidth));\n   FIFOF#(Bit#(dataWidth)) rxFifo <- mkFIFOF();\n   FIFOF#(Bit#(dataWidth)) txFifo <- mkFIFOF();\n   Reg#(Bit#(32)) linknumber <- mkReg(0);\n   Reg#(Bool) opened    <- mkReg(False);\n   Reg#(Bool) listening <- mkReg(False);\n   Reg#(Bool) started   <- mkReg(False);\n\n   rule open if (!opened && started);\n      bsimLinkOpen(linknumber, listening);\n      opened <= True;\n   endrule\n\n   rule receive if (bsimLinkCanReceive(linknumber, listening));\n      let v <- bsimLinkReceive(linknumber, listening);\n      rxFifo.enq(v);\n   endrule\n\n   rule transmit if (bsimLinkCanTransmit(linknumber, listening));\n      let v <- toGet(txFifo).get();\n      bsimLinkTransmit(linknumber, listening, v);\n   endrule\n\n   interface rx = toPipeOut(rxFifo);\n   interface tx = toPipeIn(txFifo);\n   method Action start(Bit#(32) number, Bool l);\n      linknumber <= number;\n      started <= True;\n      listening <= l;\n   endmethod\n   method Bool linkUp();\n      if (started)\n\t return unpack(bsimLinkUp(linknumber, listening));\n      else\n\t return False;\n   endmethod\nendmodule\n`endif\n\n`ifdef SVDPI\nimport \"BVI\" XsimLink =\nmodule mkSimLink(SimLink#(dataWidth));\n   parameter DATAWIDTH=valueOf(dataWidth);\n   method start(start_linknumber, start_listening) enable (en_start);\n   method link_up linkUp();\n   interface PipeOut rx;\n      method rx_first first() ready (rdy_rx_first);\n      method deq() enable (en_rx_deq) ready (rdy_rx_deq);\n      method rx_not_empty notEmpty();\n   endinterface\n   interface PipeIn tx;\n      method enq(tx_enq_v) enable (en_tx_enq) ready (rdy_tx_enq);\n      method tx_not_full notFull();\n   endinterface\n   schedule (rx_first, rx_notEmpty, tx_notFull, rx_deq, tx_enq, start, linkUp) CF (rx_first, rx_notEmpty, tx_notFull, rx_deq, tx_enq, start, linkUp);\nendmodule\n`endif //SVDPI\n"
  },
  {
    "path": "bsv/SyncAxisFifo32x8.bsv",
    "content": "\n/*\n   ../../generated/scripts/importbvi.py\n   -I\n   SyncAxisFifo32x8\n   -P\n   SyncAxisFifo32x8\n   -c\n   m_aclk\n   -c\n   s_aclk\n   -r\n   s_aresetn\n   -o\n   SyncAxisFifo32x8.bsv\n   cores/nfsume/dual_clock_axis_fifo_32x8/dual_clock_axis_fifo_32x8_stub.v\n*/\n\nimport Clocks::*;\nimport ConnectalFIFO::*;\nimport DefaultValue::*;\nimport FIFOF::*;\nimport XilinxCells::*;\nimport GetPut::*;\nimport Connectable::*;\nimport AxiBits::*;\nimport AxiStream::*;\nimport Vector::*;\n\n(* always_ready, always_enabled *)\ninterface SyncAxisFifo8#(numeric type dwidth);\n    interface AxiStreamMaster#(dwidth) m_axis;\n    interface AxiStreamSlave#(dwidth)  s_axis;\nendinterface\nimport \"BVI\" dual_clock_axis_fifo_32x8 =\nmodule mkSyncAxisFifo32x8#(Clock s_aclk, Reset s_aresetn, Clock m_aclk, Reset m_aresetn)(SyncAxisFifo8#(32));\n    default_clock no_clock;\n    default_reset no_reset;\n        input_clock m_aclk(m_aclk, (* unused *) GATE) = m_aclk;\n        input_clock s_aclk(s_aclk, (* unused *) GATE) = s_aclk;\n        input_reset s_aresetn(s_aresetn) clocked_by (s_aclk) = s_aresetn;\n        input_reset m_aresetn_foo() clocked_by (m_aclk) = m_aresetn;\n    interface AxiStreamMaster     m_axis;\n        method m_axis_tdata tdata() clocked_by (m_aclk) reset_by (m_aresetn_foo);\n        method m_axis_tkeep tkeep() clocked_by (m_aclk) reset_by (m_aresetn_foo);\n        method m_axis_tlast tlast() clocked_by (m_aclk) reset_by (m_aresetn_foo);\n        method tready(m_axis_tready) enable((*inhigh*) EN_m_axis_tready) clocked_by (m_aclk) reset_by (m_aresetn_foo);\n        method m_axis_tvalid tvalid() clocked_by (m_aclk) reset_by (m_aresetn_foo);\n    endinterface\n    interface AxiStreamSlave     s_axis;\n        method tdata(s_axis_tdata) enable((*inhigh*) EN_s_axis_tdata) clocked_by (s_aclk) reset_by (s_aresetn);\n        method tkeep(s_axis_tkeep) enable((*inhigh*) EN_s_axis_tkeep) clocked_by (s_aclk) reset_by (s_aresetn);\n        method tlast(s_axis_tlast) enable((*inhigh*) EN_s_axis_tlast) clocked_by (s_aclk) reset_by (s_aresetn);\n        method s_axis_tready tready() clocked_by (s_aclk) reset_by (s_aresetn);\n        method tvalid(s_axis_tvalid) enable((*inhigh*) EN_s_axis_tvalid) clocked_by (s_aclk) reset_by (s_aresetn);\n    endinterface\n    schedule (m_axis.tdata, m_axis.tkeep, m_axis.tlast, m_axis.tready, m_axis.tvalid, s_axis.tdata, s_axis.tkeep, s_axis.tlast, s_axis.tready, s_axis.tvalid) CF (m_axis.tdata, m_axis.tkeep, m_axis.tlast, m_axis.tready, m_axis.tvalid, s_axis.tdata, s_axis.tkeep, s_axis.tlast, s_axis.tready, s_axis.tvalid);\nendmodule\n\n(* no_default_clock, no_default_reset *)\nmodule mkSyncAxisFifo8#(Clock sclk, Reset srst, Clock dclk, Reset drst)(SyncAxisFifo8#(dwidth))\n   provisos (Div#(dwidth, 32, numFifos),\n\t     Mul#(numFifos, 32, numBits),\n\t     Add#(a__, dwidth, numBits),\n\t     Bits#(Vector#(numFifos, Bit#(4)), TDiv#(numBits, 8)),\n\t     Add#(b__, TDiv#(dwidth, 8), TDiv#(numBits, 8))\n      );\n   Vector#(numFifos,SyncAxisFifo8#(32)) fifos <- replicateM(mkSyncAxisFifo32x8(sclk, srst, dclk, drst));\n   Integer numFifos = valueOf(numFifos);\n   interface AxiStreamSlave s_axis;\n       method tready = fifos[0].s_axis.tready;\n       method Action tdata(Bit#(dwidth) v);\n\t  Vector#(numFifos,Bit#(32)) data = unpack(extend(v));\n\t  for (Integer i = 0; i < numFifos; i = i + 1)\n\t     fifos[i].s_axis.tdata(data[i]);\n       endmethod\n       method Action tkeep(Bit#(TDiv#(dwidth,8)) v);\n\t  Vector#(numFifos,Bit#(4)) keep = unpack(extend(v));\n\t  for (Integer i = 0; i < numFifos; i = i + 1)\n\t     fifos[i].s_axis.tkeep(keep[i]);\n       endmethod\n       method Action tlast(Bit#(1) v);\n\t  for (Integer i = 0; i < numFifos; i = i + 1)\n\t     fifos[i].s_axis.tlast(v);\n       endmethod\n       method Action tvalid(Bit#(1) v);\n          function Action fifo_tvalid(SyncAxisFifo8#(32) f); action f.s_axis.tvalid(v); endaction endfunction\n\t mapM_(fifo_tvalid, fifos);\n       endmethod\n   endinterface\n   interface AxiStreamMaster m_axis;\n      method Bit#(dwidth)              tdata();\n\t function Bit#(32) fifo_tdata(SyncAxisFifo8#(32) f); return f.m_axis.tdata(); endfunction\n\t Vector#(numFifos,Bit#(32)) datavec = map(fifo_tdata, fifos);\n\t Bit#(numBits) data = pack(datavec);\n\t return truncate(data);\n      endmethod\n      method Bit#(TDiv#(dwidth,8))     tkeep();\n\t function Bit#(4) fifo_tkeep(SyncAxisFifo8#(32) f); return f.m_axis.tkeep(); endfunction\n\t Vector#(numFifos,Bit#(4)) keepvec = map(fifo_tkeep, fifos);\n\t Bit#(TDiv#(dwidth,8)) keep = truncate(pack(keepvec));\n\t return truncate(keep);\n      endmethod\n      method Bit#(1)                tlast();\n\t return fifos[0].m_axis.tlast();\n      endmethod\n      method Action                 tready(Bit#(1) v);\n\t function Action fifo_tready(SyncAxisFifo8#(32) f); action f.m_axis.tready(v); endaction endfunction\n\t mapM_(fifo_tready, fifos);\n      endmethod\n      method Bit#(1)                tvalid();\n\t return fifos[0].m_axis.tvalid();\n      endmethod\n   endinterface\nendmodule\n\n(* no_default_clock, no_default_reset *)\nmodule mkSyncFifo8#(Clock fromClock, Reset fromReset, Clock toClock, Reset toReset)(FIFOF#(a))\n   provisos (Bits#(a, asz),\n\t     Div#(asz,32,afifos),\n\t     Mul#(afifos,32,fsz),\n\t     Div#(fsz, 32, afifos),\n\t     Mul#(TDiv#(fsz, 32), 4, TDiv#(fsz, 8)),\n\t     Add#(a__, asz, fsz)\n      );\n   FIFOF#(a)   fromFIFOF <- mkCFFIFOF(clocked_by fromClock, reset_by fromReset);\n   SyncAxisFifo8#(fsz) syncFIFOF <- mkSyncAxisFifo8(fromClock, fromReset, toClock, toReset);\n   FIFOF#(a)     toFIFOF <- mkCFFIFOF(clocked_by toClock, reset_by toReset);\n\n   rule rl_from if (syncFIFOF.s_axis.tready() == 1);\n      syncFIFOF.s_axis.tdata(extend(pack(fromFIFOF.first())));\n      fromFIFOF.deq();\n   endrule\n   rule rl_from_handshake;\n      syncFIFOF.s_axis.tvalid(pack(fromFIFOF.notEmpty()));\n      syncFIFOF.s_axis.tkeep(maxBound);\n      syncFIFOF.s_axis.tlast(1);\n   endrule\n\n   rule rl_to if (syncFIFOF.m_axis.tvalid() == 1);\n      toFIFOF.enq(unpack(truncate(syncFIFOF.m_axis.tdata)));\n   endrule\n   rule rl_to_handshake;\n      syncFIFOF.m_axis.tready(pack(toFIFOF.notFull()));\n   endrule\n\n   method notEmpty = toFIFOF.notEmpty;\n   method first    = toFIFOF.first;\n   method deq      = toFIFOF.deq;\n   method enq      = fromFIFOF.enq;\n   method notFull  = fromFIFOF.notFull;\nendmodule\n   \n"
  },
  {
    "path": "bsv/SyncBits.bsv",
    "content": "\n// Copyright (c) 2013 Quanta Research Cambridge, Inc.\n//\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\n\nimport Vector::*;\nimport Clocks::*;\n\nmodule mkSyncBits#(a initValue, Clock sClkIn, Reset sRst, Clock dClkIn, Reset dRst)(SyncBitIfc#(a))\n   provisos (Bits#(a,awidth));\n   \n   Reg#(a) ff0 <- mkReg(initValue, clocked_by sClkIn, reset_by sRst);\n   Reg#(a) ff1 <- mkReg(initValue, clocked_by dClkIn, reset_by dRst);\n   Reg#(a) ff2 <- mkReg(initValue, clocked_by dClkIn, reset_by dRst);\n\n   ReadOnly#(a) ff0cross <- mkNullCrossingWire(dClkIn, ff0);\n\n   rule update;\n      ff1 <= ff0cross;\n      ff2 <= ff1;\n   endrule\n\n   method a read();\n      return ff2;\n   endmethod: read\n\n   method Action send(a value);\n      ff0 <= value;\n   endmethod: send\nendmodule\n"
  },
  {
    "path": "bsv/Trace.bsv",
    "content": "import BRAM::*;\nimport BRAMFIFO::*;\nimport ConnectalFIFO::*;\nimport DefaultValue::*;\nimport FIFOF::*;\nimport GetPut::*;\nimport ConnectalMemTypes::*;\n\ntypedef struct {\n   MemRequest readReq;\n   } TraceRecord deriving (Bits);\n\ntypedef struct {\n   Bit#(32) timestamp;\n   Bool       readReqValid;\n   MemRequest readReq;\n   Bool       readDataValid;\n   Bit#(64) readData;\n   Bit#(8) readDataTag;\n   Bool readDataLast;\n   } TimestampedTraceRecord deriving (Bits);\n\ninterface TraceIndication;\n   method Action traceEntry(Bit#(32) timestamp,\n\t\t\t    Bool readReqValid, Bit#(8) sglId, Bit#(32) offset, Bit#(16) burstLen, Bit#(8) tag,\n\t\t\t    Bool readDataValid, Bit#(64) readData, Bit#(8) readDataTag, Bool readDataLast);\nendinterface\n\ninterface TraceValue#(type a);\n   interface Wire#(a) w;\n   method a m();\nendinterface\ninterface TraceAction#(type a);\n   interface Wire#(a) w;\n   method Action m(a v);\nendinterface\ninterface TraceGet#(type a);\n   method Bool valid();\n   interface Wire#(a) w;\n   interface Get#(a) get;\nendinterface\ninterface TracePut#(type a);\n   method Bool valid();\n   interface Wire#(a) w;\n   interface Put#(a) put;\nendinterface\n\nmodule mkTraceValue#(a f)(TraceValue#(a))\n   provisos (Bits#(a, asz));\n   Wire#(a) _w <- mkDWire(unpack(0));\n   rule rl_value;\n      _w <= f();\n   endrule\n   interface w = _w;\n   method a m(); return f(); endmethod\nendmodule\n\nmodule mkTraceAction#(function Action f(a v))(TraceAction#(a))\n   provisos (Bits#(a, asz));\n   Wire#(a) _w <- mkDWire(unpack(0));\n   interface w = _w;\n   method Action m(a v);\n      _w <= v;\n      f(v);\n   endmethod\nendmodule\n\nmodule mkTraceGet#(Get#(a) g)(TraceGet#(a))\n   provisos (Bits#(a, asz));\n   Wire#(Bool) _valid <- mkDWire(False);\n   Wire#(a) _w <- mkDWire(unpack(0));\n\t \n   method valid = _valid;\n   interface w = _w;\n   interface Get get;\n      method ActionValue#(a) get();\n\t let v <- g.get();\n\t _valid <= True;\n\t _w <= v;\n\t return v;\n      endmethod\n   endinterface\nendmodule\n\nmodule mkTracePut#(Put#(a) p)(TracePut#(a))\n   provisos (Bits#(a, asz));\n   Wire#(Bool) _valid <- mkDWire(False);\n   Wire#(a) _w <- mkDWire(unpack(0));\n\t \n   method valid = _valid;\n   interface w = _w;\n   interface Put put;\n      method Action put(a v);\n\t _valid <= True;\n\t _w <= v;\n\t p.put(v);\n      endmethod\n   endinterface\nendmodule\n\nmodule mkTracer#(MemReadClient#(64) client, TraceIndication tind)(MemReadClient#(64));\n\n   Reg#(Bit#(32)) cycles <- mkReg(0);\n   let addrReg <- mkReg(0);\n\n   let traceFifo <- mkSizedBRAMFIFOF(1024);\n   rule rl_cycles;\n      cycles <= cycles + 1;\n   endrule\n\n   let readReqTrace <- mkTraceGet(client.readReq);\n   let readDataTrace <- mkTracePut(client.readData);\n\n   rule rl_trace if (readReqTrace.valid);\n      let record = TimestampedTraceRecord {\n\t\t\t\t\t   timestamp: cycles,\n\n\t\t\t\t\t   readReqValid: readReqTrace.valid,\n\t\t\t\t\t   readReq: readReqTrace.w,\n\n\t\t\t\t\t   readDataValid: readDataTrace.valid,\n\t\t\t\t\t   readData: truncate(readDataTrace.w.data),\n\t\t\t\t\t   readDataTag: extend(readDataTrace.w.tag),\n\t\t\t\t\t   readDataLast: readDataTrace.w.last\n\t\t\t\t\t   };\n      if (traceFifo.notFull()) begin\n\t traceFifo.enq(record);\n      end\n   endrule\n   rule rl_upload;\n      let tr <- toGet(traceFifo).get();\n      tind.traceEntry(tr.timestamp,\n\n\t\t      tr.readReqValid,\n\t\t      truncate(tr.readReq.sglId), truncate(tr.readReq.offset), extend(tr.readReq.burstLen), extend(tr.readReq.tag),\n\n\t\t      tr.readDataValid,\n\t\t      tr.readData, tr.readDataTag, tr.readDataLast\n\t\t      );\n   endrule\n\n   interface readReq = readReqTrace.get;\n   interface readData = readDataTrace.put;\n\nendmodule\n"
  },
  {
    "path": "bsv/TraceMemClient.bsv",
    "content": "// Copyright (c) 2016 Connectal Project\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\nimport FIFOF::*;\nimport Pipe::*;\nimport GetPut::*;\nimport ConnectalMemTypes::*;\nimport ConnectalMemory::*;\n\nmodule mkTraceReadClient#(PipeIn#(Tuple4#(dmaChanId,Bool,MemRequest,Bit#(timeStampWidth))) tracePipe,\n\t\t\t  PipeIn#(Tuple4#(dmaChanId,Bool,MemData#(dataWidth),Bit#(timeStampWidth))) traceDataPipe,\n\t\t\t  dmaChanId chan,\n\t\t\t  MemReadClient#(dataWidth) m)\n   (MemReadClient#(dataWidth));\n\n   Reg#(Bit#(timeStampWidth)) cycles <- mkReg(0);\n   rule rl_cycles;\n      cycles <= cycles + 1;\n   endrule\n\n   let reqFifo  <- mkFIFOF();\n   let dataFifo <- mkFIFOF();\n\n   rule rl_rd_req;\n      let mr <- m.readReq.get();\n      if (tracePipe.notFull())\n\t tracePipe.enq(tuple4(chan, False, mr, cycles));\n      reqFifo.enq(mr);\n   endrule\n\n   rule rl_rd_data;\n      let md <- toGet(dataFifo).get();\n      if (traceDataPipe.notFull())\n\t traceDataPipe.enq(tuple4(chan, False, md, cycles));\n      m.readData.put(md);\n   endrule\n\n   interface Get readReq = toGet(reqFifo);\n   interface Put readData = toPut(dataFifo);\nendmodule\n\nmodule mkTraceWriteClient#(PipeIn#(Tuple4#(dmaChanId,Bool,MemRequest,Bit#(timeStampWidth))) tracePipe,\n\t\t\t   PipeIn#(Tuple4#(dmaChanId,Bool,MemData#(dataWidth),Bit#(timeStampWidth))) traceDataPipe,\n\t\t\t   PipeIn#(Tuple2#(dmaChanId,Bit#(timeStampWidth))) traceDonePipe,\n\t\t\t   dmaChanId chan, MemWriteClient#(dataWidth) m)\n   (MemWriteClient#(dataWidth));\n\n   Reg#(Bit#(timeStampWidth)) cycles <- mkReg(0);\n   rule rl_cycles;\n      cycles <= cycles + 1;\n   endrule\n\n   let reqFifo <- mkFIFOF();\n   let dataFifo <- mkFIFOF();\n   let doneFifo <- mkFIFOF();\n\n   rule rl_wr_req;\n      let mr <- m.writeReq.get();\n      if (tracePipe.notFull())\n\t tracePipe.enq(tuple4(chan, True, mr, cycles));\n      reqFifo.enq(mr);\n   endrule\n\n   rule rl_wr_data;\n      let md <- m.writeData.get();\n      if (traceDataPipe.notFull())\n\t traceDataPipe.enq(tuple4(chan, True, md, cycles));\n      dataFifo.enq(md);\n   endrule\n\n   rule rl_wr_done;\n      let tag <- toGet(doneFifo).get();\n      if (traceDonePipe.notFull())\n\t traceDonePipe.enq(tuple2(chan, cycles));\n      m.writeDone.put(tag);\n   endrule\n\n   interface Get writeReq = toGet(reqFifo);\n   interface Get writeData = toGet(dataFifo);\n   interface Put writeDone = toPut(doneFifo);\nendmodule\n"
  },
  {
    "path": "bsv/UntetheredTop.bsv",
    "content": "// Copyright (c) 2017 Accelerated Tech, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\nimport Vector            :: *;\nimport Clocks            :: *;\nimport GetPut            :: *;\nimport FIFO              :: *;\nimport Connectable       :: *;\nimport ClientServer      :: *;\nimport DefaultValue      :: *;\nimport Real              :: *;\n\nimport ConnectalConfig::*;\n`include \"ConnectalProjectConfig.bsv\"\nimport Xilinx            :: *;\nimport Portal            :: *;\nimport Top               :: *;\nimport ConnectalMemTypes          :: *;\nimport ConnectalClocks   :: *;\nimport GetPutWithClocks  :: *;\nimport HostInterface     :: *;\nimport `PinTypeInclude::*;\nimport Platform          :: *;\n\n`ifndef DataBusWidth\n`define DataBusWidth 64\n`endif\n\ninterface UntetheredTop#(type pintype);\n   (* prefix=\"\" *)\n   interface pintype pins;\nendinterface\n\ninterface UntetheredHost;\n   interface Clock portalClock;\n   interface Reset portalReset;\n   interface Clock derivedClock;\n   interface Reset derivedReset;\nendinterface\n\n`ifdef VirtexUltrascale\n`define SYS_CLK_PARAM Clock sys_clk1_300_p, Clock sys_clk1_300_n, Clock sys_clk2_300_p, Clock sys_clk2_300_n, \n`define SYS_CLK_ARG sys_clk1_300_p, sys_clk1_300_n, sys_clk2_300_p, sys_clk2_300_n, \n`else\n`define SYS_CLK_PARAM\n`define SYS_CLK_ARG \n`endif\n\n(* synthesize, no_default_clock, no_default_reset, reset_prefix=\"RST\" *)\nmodule mkUntetheredTop #(Clock sys_clk_p, Clock sys_clk_n, `SYS_CLK_PARAM Reset cpu_reset) (UntetheredTop#(`PinType));\n\n   Clock sys_clk_200mhz <- mkClockIBUFDS(\n`ifdef ClockDefaultParam\n       defaultValue,\n`endif\n       sys_clk_p, sys_clk_n);\n   Clock sys_clk_200mhz_buf <- mkClockBUFG(clocked_by sys_clk_200mhz);\n   Reset sys_reset_n <- mkResetInverter(cpu_reset, clocked_by sys_clk_200mhz_buf);\n\n   ClockGenerator7Params     clkgenParams = defaultValue;\n   clkgenParams.clkin1_period    = 5.000; //  200MHz\n   clkgenParams.clkin_buffer     = False;\n   clkgenParams.clkfbout_mult_f  = 5.000; // 1000MHz\n   clkgenParams.clkout0_divide_f = derivedClockPeriod;\n   clkgenParams.clkout1_divide     = round(mainClockPeriod);\n   clkgenParams.clkout1_duty_cycle = 0.5;\n   clkgenParams.clkout1_phase      = 0.0000;\n   clkgenParams.clkout2_divide     = 4; // 250MHz\n   clkgenParams.clkout2_duty_cycle = 0.5;\n   clkgenParams.clkout2_phase      = 0.0000;\n   ClockGenerator7           clkgen <- mkClockGenerator7(clkgenParams, clocked_by sys_clk_200mhz_buf, reset_by sys_reset_n);\n   Clock portalClock;\n   Reset portalReset;\n   if (mainClockPeriod == 5) begin\n      portalClock = sys_clk_200mhz_buf;\n      portalReset = sys_reset_n;\n   end\n   else begin\n      portalClock = clkgen.clkout1;\n      portalReset <- mkSyncReset(5, sys_reset_n, portalClock);\n   end\n   Clock derivedClock = clkgen.clkout0;\n   Reset derivedReset <- mkSyncReset(5, sys_reset_n, derivedClock);\n\n   UntetheredHost host = (interface UntetheredHost;\n\t\t\t  interface portalClock = portalClock;\n\t\t\t  interface portalReset = portalReset;\n\t\t\t  interface derivedClock = derivedClock;\n\t\t\t  interface derivedReset = derivedReset;\n\t\t\t  endinterface);\n\n   Vector#(NumberOfUserTiles,ConnectalTop#(`PinType)) tile <- replicateM(mkConnectalTop(\n`ifdef IMPORT_HOSTIF // no synthesis boundary\n      host,\n`else                // enables synthesis boundary\n`ifdef IMPORT_HOST_CLOCKS\n       host.derivedClock, host.derivedReset,\n`endif\n`endif\n       clocked_by host.portalClock, reset_by host.portalReset));\n   Platform portalTop <- mkPlatform(tile, clocked_by host.portalClock, reset_by host.portalReset);\n\n   interface pins = portalTop.pins;\nendmodule\n\n"
  },
  {
    "path": "bsv/XsimIF.bsv",
    "content": "// Copyright (c) 2015 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\ntypedef enum { XsimIfcNames_XsimMsgRequest, XsimIfcNames_XsimMsgIndication } XsimIfcNames;\n\ninterface XsimMsgRequest;\n   method Action msgSink(Bit#(32) portal, Bit#(32) data);\n   method Action msgSinkFd(Bit#(32) portal, SpecialTypeForSendingFd data);\nendinterface\ninterface XsimMsgIndication;\n   method Action msgSource(Bit#(32) portal, Bit#(32) data);\nendinterface\n"
  },
  {
    "path": "bsv/XsimTop.bsv",
    "content": "// Copyright (c) 2015 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\nimport ConnectalConfig::*;\nimport Vector            :: *;\nimport GetPut::*;\nimport Connectable::*;\nimport Portal            :: *;\nimport Top               :: *;\nimport HostInterface     :: *;\nimport Pipe::*;\nimport CnocPortal::*;\nimport ConnectalMemTypes:: *;\nimport ConnectalMMU:: *;\nimport MemServer:: *;\nimport MMURequest::*;\nimport MMUIndication::*;\nimport MemServerIndication::*;\nimport MemServerRequest::*;\nimport SimDma::*;\nimport IfcNames::*;\nimport BuildVector::*;\n\n`include \"ConnectalProjectConfig.bsv\"\n\n`ifdef PinTypeInclude\nimport `PinTypeInclude::*;\n`endif\n`ifdef PinType\ntypedef `PinType PinType;\n`else\ntypedef Empty PinType;\n`endif\n\n`ifndef SVDPI\nimport \"BDPI\" function Action dpi_init();\nimport \"BDPI\" function ActionValue#(Bool) dpi_cycle(); // returns non-zero if verilog should $finish().\n`endif\n\ninterface XsimTop;\n   interface PinType pins;\nendinterface\n\ninterface XsimSource;\n    method Action beat(Bit#(32) v);\nendinterface\n`ifdef SVDPI\nimport \"BVI\" XsimSource =\nmodule mkXsimSourceBVI#(Bit#(32) portal)(XsimSource);\n    port portal = portal;\n    method beat(beat) enable(en_beat);\n    schedule (beat) C (beat);\nendmodule\nmodule mkXsimSource#(PortalMsgIndication indication)(Empty);\n   let tmp <- mkXsimSourceBVI(indication.id);\n   rule ind_dst_rdy;\n      indication.message.deq();\n      tmp.beat(indication.message.first());\n   endrule\nendmodule\n`else\nimport \"BDPI\" function Action dpi_msgSource_beat(Bit#(32)  portal, Bit#(32)  beat);\nmodule mkXsimSource#(PortalMsgIndication indication)(Empty);\n   rule ind_dst_rdy;\n      indication.message.deq();\n      dpi_msgSource_beat(indication.id, indication.message.first());\n   endrule\nendmodule\n`endif\n\ninterface MsgSinkR#(numeric type bytes_per_beat);\n   method ActionValue#(Bit#(32)) beat();\nendinterface\n\n`ifdef SVDPI\nimport \"BVI\" XsimSink =\nmodule mkXsimSinkBVI#(Bit#(32) portal)(MsgSinkR#(4));\n   port portal = portal;\n   method beat beat() enable (EN_beat) ready (RDY_beat);\n   schedule (beat) C (beat);\nendmodule\nmodule mkXsimSink#(PortalMsgRequest request)(Empty);\n   let sink <- mkXsimSinkBVI(request.id);\n\n   rule req_src_rdy;\n      let beat <- sink.beat();\n      request.message.enq(beat);\n   endrule\nendmodule\n`else\nimport \"BDPI\" function ActionValue#(Bit#(33)) dpi_msgSink_beat(Bit#(32) portal);\nmodule mkXsimSink#(PortalMsgRequest request)(Empty);\n   rule req_src_rdy;\n      let beat <- dpi_msgSink_beat(request.id);\n      if (unpack(beat[32]))\n\t request.message.enq(beat[31:0]);\n   endrule\nendmodule\n`endif\n\nmodule mkXsimMemoryConnection#(PhysMemMaster#(addrWidth, dataWidth) master)(Empty)\n   provisos (Mul#(TDiv#(dataWidth, 8), 8, dataWidth),\n\t     Mul#(TDiv#(dataWidth, 32), 32, dataWidth),\n\t     Add#(a__, TDiv#(DataBusWidth,8), TDiv#(dataWidth, 8)),\n\t     Mul#(TDiv#(dataWidth, 32), 4, TDiv#(dataWidth, 8)));\n   PhysMemSlave#(addrWidth,dataWidth) slave <- mkSimDmaDmaMaster();\n   mkConnection(master, slave);\nendmodule\n\nmodule mkXsimTop#(Clock derivedClock, Reset derivedReset, Clock sys_clk)(XsimTop);\n\n   Reg#(Bool) dumpstarted <- mkReg(False);\n   rule startdump if (!dumpstarted);\n      //$dumpfile(\"dump.vcd\");\n      //$dumpvars;\n      $display(\"XsimTop starting\");\n      dumpstarted <= True;\n   endrule\n   XsimHost host <- mkXsimHost(derivedClock, derivedReset, sys_clk);\n   let top <- mkCnocTop(\n`ifdef IMPORT_HOSTIF\n       host\n`else\n`ifdef IMPORT_HOST_CLOCKS // enables synthesis boundary\n       derivedClock, derivedReset\n`else\n// otherwise no params\n`endif\n`endif\n       );\n\n`ifndef SVDPI\n   Reg#(Bool) initCalled <- mkReg(False);\n   rule call_init if (!initCalled);\n      dpi_init();\n      initCalled <= True;\n   endrule\n   rule finish;\n      let doFinish <- dpi_cycle();\n      if (doFinish) begin\n\t $display(\"simulator calling $finish\");\n\t $finish();\n      end\n   endrule\n`endif\n\n   MMUIndicationOutput lMMUIndicationOutput <- mkMMUIndicationOutput;\n   MMURequestInput lMMURequestInput <- mkMMURequestInput;\n   MMU#(PhysAddrWidth) lMMU <- mkMMU(0,True, lMMUIndicationOutput.ifc);\n   mkConnection(lMMURequestInput.pipes, lMMU.request);\n\n   MemServerIndicationOutput lMemServerIndicationOutput <- mkMemServerIndicationOutput;\n   MemServerRequestInput lMemServerRequestInput <- mkMemServerRequestInput;\n   MemServer::MemServer#(PhysAddrWidth,DataBusWidth,NumberOfMasters) lMemServer <- mkMemServer(top.readers, top.writers, cons(lMMU,nil), lMemServerIndicationOutput.ifc);\n   mkConnection(lMemServerRequestInput.pipes, lMemServer.request);\n\n   let lMMUIndicationOutputNoc <- mkPortalMsgIndication(extend(pack(PlatformIfcNames_MMUIndicationH2S)), lMMUIndicationOutput.portalIfc.indications, lMMUIndicationOutput.portalIfc.messageSize);\n   let lMMURequestInputNoc <- mkPortalMsgRequest(extend(pack(PlatformIfcNames_MMURequestS2H)), lMMURequestInput.portalIfc.requests);\n   let lMemServerIndicationOutputNoc <- mkPortalMsgIndication(extend(pack(PlatformIfcNames_MemServerIndicationH2S)), lMemServerIndicationOutput.portalIfc.indications, lMemServerIndicationOutput.portalIfc.messageSize);\n   let lMemServerRequestInputNoc <- mkPortalMsgRequest(extend(pack(PlatformIfcNames_MemServerRequestS2H)), lMemServerRequestInput.portalIfc.requests);\n\n   mapM_(mkXsimSink, append(top.requests, append(vec(lMMURequestInputNoc), vec(lMemServerRequestInputNoc))));\n   mapM_(mkXsimSource, append(top.indications, append(vec(lMMUIndicationOutputNoc), vec(lMemServerIndicationOutputNoc))));\n   mapM_(mkXsimMemoryConnection, lMemServer.masters);\n\n`ifdef PinType\n   interface pins = top.pins;\n`endif\nendmodule\n"
  },
  {
    "path": "bsv/ZynqTop.bsv",
    "content": "// Copyright (c) 2014 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\nimport ConnectalConfig::*;\nimport ConnectalClocks::*;\nimport Clocks :: *;\nimport DefaultValue      :: *;\nimport Vector            :: *;\nimport Connectable       :: *;\nimport ConnectableWithTrace::*;\nimport Portal            :: *;\nimport ConnectalMemTypes          :: *;\nimport AxiMasterSlave    :: *;\nimport XilinxCells       :: *;\nimport ConnectalXilinxCells   :: *;\nimport PS7LIB::*;\nimport PS7Trace::*;\nimport PPS7LIB::*;\nimport CtrlMux::*;\nimport AxiDma            :: *;\nimport Top               :: *;\nimport Bscan             :: *;\nimport HostInterface     :: *;\nimport Platform          :: *;\n`include \"ConnectalProjectConfig.bsv\"\nimport `PinTypeInclude::*;\n\n`ifdef XILINX_SYS_CLK\n`define SYS_CLK_PARAM #( Clock sys_clk_p, Clock sys_clk_n )\n`define SYS_CLK_ARG sys_clk_p, sys_clk_n,\n`else\n`define SYS_CLK_PARAM\n`define SYS_CLK_ARG\n`endif\n\ninterface I2C_Pins;\n   interface Inout#(Bit#(1)) scl;\n   interface Inout#(Bit#(1)) sda;\nendinterface\n\n(* always_ready, always_enabled *)\ninterface ZynqTop;\n   (* prefix=\"\" *)\n   interface ZynqPins zynq;\n`ifdef USE_I2C0\n   (* prefix=\"I2C0\" *)\n   interface I2C_Pins         i2c0;\n`endif\n`ifdef USE_I2C1\n   (* prefix=\"I2C1\" *)\n   interface I2C_Pins         i2c1;\n`endif\n   (* prefix=\"\" *)\n   interface `PinType          pins;\n   interface Vector#(4, Clock) deleteme_unused_clock;\n   interface Vector#(4, Reset) deleteme_unused_reset;\nendinterface\n\nmodule mkZynqTop `SYS_CLK_PARAM (ZynqTop);\n`ifndef TOP_SOURCES_PORTAL_CLOCK\n   let axiClock <- exposeCurrentClock();\n`else\n   B2C axiClockB2C <- mkB2C();\n   let axiClock = axiClockB2C.c;\n`endif\n   PS7 ps7 <- mkPS7(axiClock);\n   Clock mainclock = ps7.portalClock;\n   Reset mainreset = ps7.portalReset;\n\n`ifdef XILINX_SYS_CLK\n   Clock sys_clk_200mhz <- mkClockIBUFDS(\n`ifdef ClockDefaultParam\n       defaultValue,\n`endif\n       sys_clk_p, sys_clk_n);\n   Clock sys_clk_200mhz_buf <- mkClockBUFG(clocked_by sys_clk_200mhz);\n`endif // XILINX_SYS_CLK\n\n`ifdef USE_I2C0\n   let tscl0 <- mkIOBUF(~ps7.i2c[0].scltn, ps7.i2c[0].sclo, clocked_by mainclock, reset_by mainreset);\n   let tsda0 <- mkIOBUF(~ps7.i2c[0].sdatn, ps7.i2c[0].sdao, clocked_by mainclock, reset_by mainreset);\n   rule sdai0;\n      ps7.i2c[0].sdai(tsda0.o);\n      ps7.i2c[0].scli(tscl0.o);\n   endrule\n`endif\n\n`ifdef USE_I2C1\n   let tscl1 <- mkIOBUF(~ps7.i2c[1].scltn, ps7.i2c[1].sclo, clocked_by mainclock, reset_by mainreset);\n   let tsda1 <- mkIOBUF(~ps7.i2c[1].sdatn, ps7.i2c[1].sdao, clocked_by mainclock, reset_by mainreset);\n   rule sdai1;\n      ps7.i2c[1].sdai(tsda1.o);\n      ps7.i2c[1].scli(tscl1.o);\n   endrule\n`endif\n\n   BscanTop bscan <- mkBscanTop(3, clocked_by mainclock, reset_by mainreset); // Use USER3  (JTAG IDCODE address 0x22)\n   BscanLocal lbscan <- mkBscanLocal(bscan, clocked_by bscan.tck, reset_by bscan.rst);\n   Vector#(NumberOfUserTiles,ConnectalTop#(`PinType)) ts <- replicateM(mkConnectalTop(\n`ifdef IMPORT_HOSTIF\n      (interface HostInterface;\n          interface ps7 = ps7;\n\t  interface portalClock = mainclock;\n\t  interface portalReset = mainreset;\n\t  interface derivedClock = ps7.derivedClock;\n\t  interface derivedReset = ps7.derivedReset;\n          interface bscan = lbscan.loc[0];\n`ifdef XILINX_SYS_CLK\n       interface tsys_clk_200mhz = sys_clk_200mhz;\n       interface tsys_clk_200mhz_buf = sys_clk_200mhz_buf;\n`endif\n      endinterface),\n`else                  // enables synthesis boundary\n`ifdef IMPORT_HOST_CLOCKS\n      ps7.derivedClock, ps7.derivedReset,\n`endif\n`endif\n      clocked_by mainclock, reset_by mainreset));\n\n`ifdef TOP_SOURCES_PORTAL_CLOCK\n   C2B portalClockC2B <- mkC2B(ts[0].portalClockSource, clocked_by axiClockB2C.c);\n   rule rl_portal_clock_source;\n      axiClockB2C.inputclock(portalClockC2B.o);\n   endrule\n`endif\n\n   Platform top <- mkPlatform(ts, clocked_by mainclock, reset_by mainreset);\n   mkConnectionWithTrace(ps7, top, lbscan.loc[1], clocked_by mainclock, reset_by mainreset);\n\n   let intr_mux <- mkInterruptMux(top.interrupt);\n   rule send_int_rule;\n      ps7.interrupt(pack(intr_mux));\n   endrule\n\n   module bufferClock#(Integer i)(Clock); let bc <- mkClockBUFG(clocked_by ps7.fclkclk[i]); return bc; endmodule\n   module bufferReset#(Integer i)(Reset); let rc <- mkSyncReset(10, ps7.fclkreset[i], ps7.fclkclk[0]); return rc; endmodule\n   Vector#(4, Clock) unused_clock <- genWithM(bufferClock);\n   Vector#(4, Reset) unused_reset <- genWithM(bufferReset);\n\n   interface zynq = ps7.pins;\n`ifdef USE_I2C0\n   interface I2C_Pins i2c0;\n      interface Inout scl = tscl0.io;\n      interface Inout sda = tsda0.io;\n   endinterface\n`endif\n`ifdef USE_I2C1\n   interface I2C_Pins i2c1;\n      interface Inout scl = tscl1.io;\n      interface Inout sda = tsda1.io;\n   endinterface\n`endif\n   interface pins = top.pins;\n   interface deleteme_unused_clock = unused_clock;\n   interface deleteme_unused_reset = unused_reset;\nendmodule\n"
  },
  {
    "path": "bsv/ZynqUltraTop.bsv",
    "content": "// Copyright (c) 2014 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\nimport ConnectalConfig::*;\nimport ConnectalClocks::*;\nimport Clocks :: *;\nimport DefaultValue      :: *;\nimport Vector            :: *;\nimport Connectable       :: *;\nimport ConnectableWithTrace::*;\nimport Portal            :: *;\nimport ConnectalMemTypes          :: *;\nimport AxiMasterSlave    :: *;\nimport XilinxCells       :: *;\nimport ConnectalXilinxCells   :: *;\nimport PS8LIB::*;\nimport ZYNQ_ULTRA::*;\nimport CtrlMux::*;\nimport AxiDma            :: *;\nimport Top               :: *;\nimport Bscan             :: *;\nimport HostInterface     :: *;\nimport Platform          :: *;\n`include \"ConnectalProjectConfig.bsv\"\nimport `PinTypeInclude::*;\n\n`ifdef XILINX_SYS_CLK\n`define SYS_CLK_PARAM #( Clock sys_clk_p, Clock sys_clk_n )\n`define SYS_CLK_ARG sys_clk_p, sys_clk_n,\n`else\n`define SYS_CLK_PARAM\n`define SYS_CLK_ARG\n`endif\n\ninterface I2C_Pins;\n   interface Inout#(Bit#(1)) scl;\n   interface Inout#(Bit#(1)) sda;\nendinterface\n\n(* always_ready, always_enabled *)\ninterface ZynqUltraTop;\n   (* prefix=\"\" *)\n   interface ZynqPins zynq;\n`ifdef USE_I2C0\n   (* prefix=\"I2C0\" *)\n   interface I2C_Pins         i2c0;\n`endif\n`ifdef USE_I2C1\n   (* prefix=\"I2C1\" *)\n   interface I2C_Pins         i2c1;\n`endif\n   (* prefix=\"\" *)\n   interface `PinType          pins;\n   interface Vector#(4, Clock) deleteme_unused_clock;\n   //interface Vector#(4, Reset) deleteme_unused_reset;\nendinterface\n\nmodule mkZynqUltraTop `SYS_CLK_PARAM (ZynqUltraTop);\n`ifndef TOP_SOURCES_PORTAL_CLOCK\n   let axiClock <- exposeCurrentClock();\n`else\n   B2C axiClockB2C <- mkB2C();\n   let axiClock = axiClockB2C.c;\n`endif\n   PS8LIB ps8 <- mkPS8LIB(axiClock);\n   Clock mainclock = ps8.portalClock;\n   Reset mainreset = ps8.portalReset;\n\n`ifdef XILINX_SYS_CLK\n   Clock sys_clk_200mhz <- mkClockIBUFDS(\n`ifdef ClockDefaultParam\n       defaultValue,\n`endif\n       sys_clk_p, sys_clk_n);\n   Clock sys_clk_200mhz_buf <- mkClockBUFG(clocked_by sys_clk_200mhz);\n`endif // XILINX_SYS_CLK\n\n   BscanTop bscan <- mkBscanTop(3, clocked_by mainclock, reset_by mainreset); // Use USER3  (JTAG IDCODE address 0x22)\n   BscanLocal lbscan <- mkBscanLocal(bscan, clocked_by bscan.tck, reset_by bscan.rst);\n   Vector#(NumberOfUserTiles,ConnectalTop#(`PinType)) ts <- replicateM(mkConnectalTop(\n`ifdef IMPORT_HOSTIF\n      (interface HostInterface;\n          interface ps8 = ps8;\n\t  interface portalClock = mainclock;\n\t  interface portalReset = mainreset;\n\t  interface derivedClock = ps8.derivedClock;\n\t  interface derivedReset = ps8.derivedReset;\n          interface bscan = lbscan.loc[0];\n`ifdef XILINX_SYS_CLK\n       interface tsys_clk_200mhz = sys_clk_200mhz;\n       interface tsys_clk_200mhz_buf = sys_clk_200mhz_buf;\n`endif\n      endinterface),\n`else                  // enables synthesis boundary\n`ifdef IMPORT_HOST_CLOCKS\n      ps8.derivedClock, ps8.derivedReset,\n`endif\n`endif\n      clocked_by mainclock, reset_by mainreset));\n\n`ifdef TOP_SOURCES_PORTAL_CLOCK\n   C2B portalClockC2B <- mkC2B(ts[0].portalClockSource, clocked_by axiClockB2C.c);\n   rule rl_portal_clock_source;\n      axiClockB2C.inputclock(portalClockC2B.o);\n   endrule\n`endif\n\n   Platform top <- mkPlatform(ts, clocked_by mainclock, reset_by mainreset);\n   mkConnectionWithTrace(ps8, top, lbscan.loc[1], clocked_by mainclock, reset_by mainreset);\n\n   let intr_mux <- mkInterruptMux(top.interrupt);\n   rule send_int_rule;\n      ps8.interrupt(pack(intr_mux));\n   endrule\n\n   module bufferClock#(Integer i)(Clock); let bc <- mkClockBUFG(clocked_by ps8.plclk[i]); return bc; endmodule\n   //module bufferReset#(Integer i)(Reset); let rc <- mkSyncReset(10, ps8.fclkreset[i], ps8.fclkclk[0]); return rc; endmodule\n   Vector#(4, Clock) unused_clock <- genWithM(bufferClock);\n   //Vector#(4, Reset) unused_reset <- genWithM(bufferReset);\n\n   //interface zynq = ps8.pins;\n   interface pins = top.pins;\n   interface deleteme_unused_clock = unused_clock;\n   //interface deleteme_unused_reset = unused_reset;\nendmodule\n"
  },
  {
    "path": "constraints/altera/de5.qsf",
    "content": "#============================================================\n# BUTTON\n#============================================================\nset_instance_assignment -name IO_STANDARD \"2.5 V\" -to button[0]\nset_instance_assignment -name IO_STANDARD \"2.5 V\" -to button[1]\nset_instance_assignment -name IO_STANDARD \"2.5 V\" -to button[2]\nset_instance_assignment -name IO_STANDARD \"2.5 V\" -to button[3]\n#============================================================\n# CLOCK\n#============================================================\nset_instance_assignment -name IO_STANDARD \"2.5 V\" -to clock_scl\nset_instance_assignment -name IO_STANDARD \"2.5 V\" -to clock_sda\n#============================================================\n# CPU\n#============================================================\nset_instance_assignment -name IO_STANDARD \"2.5 V\" -to cpu_reset_n\n#============================================================\n# DDR3A\n#============================================================\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3a_a[0]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3a_a[1]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3a_a[2]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3a_a[3]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3a_a[4]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3a_a[5]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3a_a[6]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3a_a[7]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3a_a[8]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3a_a[9]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3a_a[10]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3a_a[11]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3a_a[12]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3a_a[13]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3a_a[14]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3a_a[15]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3a_ba[0]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3a_ba[1]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3a_ba[2]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3a_cas_n\nset_instance_assignment -name IO_STANDARD \"DIFFERENTIAL 1.5-V SSTL CLASS I\" -to ddr3a_ck[0]\nset_instance_assignment -name IO_STANDARD \"DIFFERENTIAL 1.5-V SSTL CLASS I\" -to ddr3a_ck[1]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3a_cke[0]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3a_cke[1]\nset_instance_assignment -name IO_STANDARD \"DIFFERENTIAL 1.5-V SSTL CLASS I\" -to ddr3a_ck_n[0]\nset_instance_assignment -name IO_STANDARD \"DIFFERENTIAL 1.5-V SSTL CLASS I\" -to ddr3a_ck_n[1]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3a_cs_n[0]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3a_cs_n[1]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3a_dm[0]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3a_dm[1]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3a_dm[2]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3a_dm[3]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3a_dm[4]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3a_dm[5]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3a_dm[6]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3a_dm[7]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3a_dq[0]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3a_dq[1]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3a_dq[2]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3a_dq[3]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3a_dq[4]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3a_dq[5]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3a_dq[6]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3a_dq[7]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3a_dq[8]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3a_dq[9]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3a_dq[10]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3a_dq[11]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3a_dq[12]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3a_dq[13]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3a_dq[14]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3a_dq[15]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3a_dq[16]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3a_dq[17]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3a_dq[18]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3a_dq[19]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3a_dq[20]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3a_dq[21]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3a_dq[22]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3a_dq[23]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3a_dq[24]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3a_dq[25]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3a_dq[26]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3a_dq[27]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3a_dq[28]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3a_dq[29]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3a_dq[30]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3a_dq[31]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3a_dq[32]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3a_dq[33]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3a_dq[34]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3a_dq[35]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3a_dq[36]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3a_dq[37]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3a_dq[38]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3a_dq[39]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3a_dq[40]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3a_dq[41]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3a_dq[42]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3a_dq[43]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3a_dq[44]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3a_dq[45]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3a_dq[46]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3a_dq[47]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3a_dq[48]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3a_dq[49]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3a_dq[50]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3a_dq[51]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3a_dq[52]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3a_dq[53]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3a_dq[54]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3a_dq[55]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3a_dq[56]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3a_dq[57]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3a_dq[58]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3a_dq[59]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3a_dq[60]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3a_dq[61]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3a_dq[62]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3a_dq[63]\nset_instance_assignment -name IO_STANDARD \"DIFFERENTIAL 1.5-V SSTL CLASS I\" -to ddr3a_dqs[0]\nset_instance_assignment -name IO_STANDARD \"DIFFERENTIAL 1.5-V SSTL CLASS I\" -to ddr3a_dqs[1]\nset_instance_assignment -name IO_STANDARD \"DIFFERENTIAL 1.5-V SSTL CLASS I\" -to ddr3a_dqs[2]\nset_instance_assignment -name IO_STANDARD \"DIFFERENTIAL 1.5-V SSTL CLASS I\" -to ddr3a_dqs[3]\nset_instance_assignment -name IO_STANDARD \"DIFFERENTIAL 1.5-V SSTL CLASS I\" -to ddr3a_dqs[4]\nset_instance_assignment -name IO_STANDARD \"DIFFERENTIAL 1.5-V SSTL CLASS I\" -to ddr3a_dqs[5]\nset_instance_assignment -name IO_STANDARD \"DIFFERENTIAL 1.5-V SSTL CLASS I\" -to ddr3a_dqs[6]\nset_instance_assignment -name IO_STANDARD \"DIFFERENTIAL 1.5-V SSTL CLASS I\" -to ddr3a_dqs[7]\nset_instance_assignment -name IO_STANDARD \"DIFFERENTIAL 1.5-V SSTL CLASS I\" -to ddr3a_dqs_n[0]\nset_instance_assignment -name IO_STANDARD \"DIFFERENTIAL 1.5-V SSTL CLASS I\" -to ddr3a_dqs_n[1]\nset_instance_assignment -name IO_STANDARD \"DIFFERENTIAL 1.5-V SSTL CLASS I\" -to ddr3a_dqs_n[2]\nset_instance_assignment -name IO_STANDARD \"DIFFERENTIAL 1.5-V SSTL CLASS I\" -to ddr3a_dqs_n[3]\nset_instance_assignment -name IO_STANDARD \"DIFFERENTIAL 1.5-V SSTL CLASS I\" -to ddr3a_dqs_n[4]\nset_instance_assignment -name IO_STANDARD \"DIFFERENTIAL 1.5-V SSTL CLASS I\" -to ddr3a_dqs_n[5]\nset_instance_assignment -name IO_STANDARD \"DIFFERENTIAL 1.5-V SSTL CLASS I\" -to ddr3a_dqs_n[6]\nset_instance_assignment -name IO_STANDARD \"DIFFERENTIAL 1.5-V SSTL CLASS I\" -to ddr3a_dqs_n[7]\nset_instance_assignment -name IO_STANDARD \"1.5 V\" -to ddr3a_event_n\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3a_odt[0]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3a_odt[1]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3a_ras_n\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3a_reset_n\nset_instance_assignment -name IO_STANDARD \"1.5 V\" -to ddr3a_scl\nset_instance_assignment -name IO_STANDARD \"1.5 V\" -to ddr3a_sda\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3a_we_n\n#============================================================\n# DDR3B\n#============================================================\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3b_a[0]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3b_a[1]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3b_a[2]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3b_a[3]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3b_a[4]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3b_a[5]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3b_a[6]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3b_a[7]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3b_a[8]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3b_a[9]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3b_a[10]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3b_a[11]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3b_a[12]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3b_a[13]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3b_a[14]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3b_a[15]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3b_ba[0]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3b_ba[1]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3b_ba[2]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3b_cas_n\nset_instance_assignment -name IO_STANDARD \"DIFFERENTIAL 1.5-V SSTL CLASS I\" -to ddr3b_ck[0]\nset_instance_assignment -name IO_STANDARD \"DIFFERENTIAL 1.5-V SSTL CLASS I\" -to ddr3b_ck[1]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3b_cke[0]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3b_cke[1]\nset_instance_assignment -name IO_STANDARD \"DIFFERENTIAL 1.5-V SSTL CLASS I\" -to ddr3b_ck_n[0]\nset_instance_assignment -name IO_STANDARD \"DIFFERENTIAL 1.5-V SSTL CLASS I\" -to ddr3b_ck_n[1]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3b_cs_n[0]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3b_cs_n[1]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3b_dm[0]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3b_dm[1]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3b_dm[2]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3b_dm[3]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3b_dm[4]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3b_dm[5]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3b_dm[6]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3b_dm[7]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3b_dq[0]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3b_dq[1]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3b_dq[2]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3b_dq[3]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3b_dq[4]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3b_dq[5]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3b_dq[6]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3b_dq[7]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3b_dq[8]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3b_dq[9]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3b_dq[10]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3b_dq[11]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3b_dq[12]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3b_dq[13]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3b_dq[14]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3b_dq[15]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3b_dq[16]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3b_dq[17]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3b_dq[18]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3b_dq[19]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3b_dq[20]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3b_dq[21]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3b_dq[22]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3b_dq[23]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3b_dq[24]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3b_dq[25]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3b_dq[26]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3b_dq[27]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3b_dq[28]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3b_dq[29]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3b_dq[30]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3b_dq[31]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3b_dq[32]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3b_dq[33]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3b_dq[34]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3b_dq[35]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3b_dq[36]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3b_dq[37]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3b_dq[38]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3b_dq[39]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3b_dq[40]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3b_dq[41]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3b_dq[42]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3b_dq[43]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3b_dq[44]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3b_dq[45]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3b_dq[46]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3b_dq[47]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3b_dq[48]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3b_dq[49]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3b_dq[50]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3b_dq[51]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3b_dq[52]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3b_dq[53]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3b_dq[54]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3b_dq[55]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3b_dq[56]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3b_dq[57]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3b_dq[58]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3b_dq[59]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3b_dq[60]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3b_dq[61]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3b_dq[62]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3b_dq[63]\nset_instance_assignment -name IO_STANDARD \"DIFFERENTIAL 1.5-V SSTL CLASS I\" -to ddr3b_dqs[0]\nset_instance_assignment -name IO_STANDARD \"DIFFERENTIAL 1.5-V SSTL CLASS I\" -to ddr3b_dqs[1]\nset_instance_assignment -name IO_STANDARD \"DIFFERENTIAL 1.5-V SSTL CLASS I\" -to ddr3b_dqs[2]\nset_instance_assignment -name IO_STANDARD \"DIFFERENTIAL 1.5-V SSTL CLASS I\" -to ddr3b_dqs[3]\nset_instance_assignment -name IO_STANDARD \"DIFFERENTIAL 1.5-V SSTL CLASS I\" -to ddr3b_dqs[4]\nset_instance_assignment -name IO_STANDARD \"DIFFERENTIAL 1.5-V SSTL CLASS I\" -to ddr3b_dqs[5]\nset_instance_assignment -name IO_STANDARD \"DIFFERENTIAL 1.5-V SSTL CLASS I\" -to ddr3b_dqs[6]\nset_instance_assignment -name IO_STANDARD \"DIFFERENTIAL 1.5-V SSTL CLASS I\" -to ddr3b_dqs[7]\nset_instance_assignment -name IO_STANDARD \"DIFFERENTIAL 1.5-V SSTL CLASS I\" -to ddr3b_dqs_n[0]\nset_instance_assignment -name IO_STANDARD \"DIFFERENTIAL 1.5-V SSTL CLASS I\" -to ddr3b_dqs_n[1]\nset_instance_assignment -name IO_STANDARD \"DIFFERENTIAL 1.5-V SSTL CLASS I\" -to ddr3b_dqs_n[2]\nset_instance_assignment -name IO_STANDARD \"DIFFERENTIAL 1.5-V SSTL CLASS I\" -to ddr3b_dqs_n[3]\nset_instance_assignment -name IO_STANDARD \"DIFFERENTIAL 1.5-V SSTL CLASS I\" -to ddr3b_dqs_n[4]\nset_instance_assignment -name IO_STANDARD \"DIFFERENTIAL 1.5-V SSTL CLASS I\" -to ddr3b_dqs_n[5]\nset_instance_assignment -name IO_STANDARD \"DIFFERENTIAL 1.5-V SSTL CLASS I\" -to ddr3b_dqs_n[6]\nset_instance_assignment -name IO_STANDARD \"DIFFERENTIAL 1.5-V SSTL CLASS I\" -to ddr3b_dqs_n[7]\nset_instance_assignment -name IO_STANDARD \"1.5 V\" -to ddr3b_event_n\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3b_odt[0]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3b_odt[1]\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3b_ras_n\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3b_reset_n\nset_instance_assignment -name IO_STANDARD \"1.5 V\" -to ddr3b_scl\nset_instance_assignment -name IO_STANDARD \"1.5 V\" -to ddr3b_sda\nset_instance_assignment -name IO_STANDARD \"SSTL-15 CLASS I\" -to ddr3b_we_n\n#============================================================\n# FAN\n#============================================================\nset_instance_assignment -name IO_STANDARD \"2.5 V\" -to fan_ctrl\n#============================================================\n# FLASH\n#============================================================\nset_instance_assignment -name IO_STANDARD \"2.5 V\" -to flash_adv_n\nset_instance_assignment -name IO_STANDARD \"2.5 V\" -to flash_ce_n[0]\nset_instance_assignment -name IO_STANDARD \"2.5 V\" -to flash_ce_n[1]\nset_instance_assignment -name IO_STANDARD \"2.5 V\" -to flash_clk\nset_instance_assignment -name IO_STANDARD \"2.5 V\" -to flash_oe_n\nset_instance_assignment -name IO_STANDARD \"2.5 V\" -to flash_rdy_bsy_n[0]\nset_instance_assignment -name IO_STANDARD \"2.5 V\" -to flash_rdy_bsy_n[1]\nset_instance_assignment -name IO_STANDARD \"2.5 V\" -to flash_reset_n\nset_instance_assignment -name IO_STANDARD \"2.5 V\" -to flash_we_n\n#============================================================\n# FSM\n#============================================================\nset_instance_assignment -name IO_STANDARD \"2.5 V\" -to fsm_a[0]\nset_instance_assignment -name IO_STANDARD \"2.5 V\" -to fsm_a[1]\nset_instance_assignment -name IO_STANDARD \"2.5 V\" -to fsm_a[2]\nset_instance_assignment -name IO_STANDARD \"2.5 V\" -to fsm_a[3]\nset_instance_assignment -name IO_STANDARD \"2.5 V\" -to fsm_a[4]\nset_instance_assignment -name IO_STANDARD \"2.5 V\" -to fsm_a[5]\nset_instance_assignment -name IO_STANDARD \"2.5 V\" -to fsm_a[6]\nset_instance_assignment -name IO_STANDARD \"2.5 V\" -to fsm_a[7]\nset_instance_assignment -name IO_STANDARD \"2.5 V\" -to fsm_a[8]\nset_instance_assignment -name IO_STANDARD \"2.5 V\" -to fsm_a[9]\nset_instance_assignment -name IO_STANDARD \"2.5 V\" -to fsm_a[10]\nset_instance_assignment -name IO_STANDARD \"2.5 V\" -to fsm_a[11]\nset_instance_assignment -name IO_STANDARD \"2.5 V\" -to fsm_a[12]\nset_instance_assignment -name IO_STANDARD \"2.5 V\" -to fsm_a[13]\nset_instance_assignment -name IO_STANDARD \"2.5 V\" -to fsm_a[14]\nset_instance_assignment -name IO_STANDARD \"2.5 V\" -to fsm_a[15]\nset_instance_assignment -name IO_STANDARD \"2.5 V\" -to fsm_a[16]\nset_instance_assignment -name IO_STANDARD \"2.5 V\" -to fsm_a[17]\nset_instance_assignment -name IO_STANDARD \"2.5 V\" -to fsm_a[18]\nset_instance_assignment -name IO_STANDARD \"2.5 V\" -to fsm_a[19]\nset_instance_assignment -name IO_STANDARD \"2.5 V\" -to fsm_a[20]\nset_instance_assignment -name IO_STANDARD \"2.5 V\" -to fsm_a[21]\nset_instance_assignment -name IO_STANDARD \"2.5 V\" -to fsm_a[22]\nset_instance_assignment -name IO_STANDARD \"2.5 V\" -to fsm_a[23]\nset_instance_assignment -name IO_STANDARD \"2.5 V\" -to fsm_a[24]\nset_instance_assignment -name IO_STANDARD \"2.5 V\" -to fsm_a[25]\nset_instance_assignment -name IO_STANDARD \"2.5 V\" -to fsm_a[26]\nset_instance_assignment -name IO_STANDARD \"2.5 V\" -to fsm_d[0]\nset_instance_assignment -name IO_STANDARD \"2.5 V\" -to fsm_d[1]\nset_instance_assignment -name IO_STANDARD \"2.5 V\" -to fsm_d[2]\nset_instance_assignment -name IO_STANDARD \"2.5 V\" -to fsm_d[3]\nset_instance_assignment -name IO_STANDARD \"2.5 V\" -to fsm_d[4]\nset_instance_assignment -name IO_STANDARD \"2.5 V\" -to fsm_d[5]\nset_instance_assignment -name IO_STANDARD \"2.5 V\" -to fsm_d[6]\nset_instance_assignment -name IO_STANDARD \"2.5 V\" -to fsm_d[7]\nset_instance_assignment -name IO_STANDARD \"2.5 V\" -to fsm_d[8]\nset_instance_assignment -name IO_STANDARD \"2.5 V\" -to fsm_d[9]\nset_instance_assignment -name IO_STANDARD \"2.5 V\" -to fsm_d[10]\nset_instance_assignment -name IO_STANDARD \"2.5 V\" -to fsm_d[11]\nset_instance_assignment -name IO_STANDARD \"2.5 V\" -to fsm_d[12]\nset_instance_assignment -name IO_STANDARD \"2.5 V\" -to fsm_d[13]\nset_instance_assignment -name IO_STANDARD \"2.5 V\" -to fsm_d[14]\nset_instance_assignment -name IO_STANDARD \"2.5 V\" -to fsm_d[15]\nset_instance_assignment -name IO_STANDARD \"2.5 V\" -to fsm_d[16]\nset_instance_assignment -name IO_STANDARD \"2.5 V\" -to fsm_d[17]\nset_instance_assignment -name IO_STANDARD \"2.5 V\" -to fsm_d[18]\nset_instance_assignment -name IO_STANDARD \"2.5 V\" -to fsm_d[19]\nset_instance_assignment -name IO_STANDARD \"2.5 V\" -to fsm_d[20]\nset_instance_assignment -name IO_STANDARD \"2.5 V\" -to fsm_d[21]\nset_instance_assignment -name IO_STANDARD \"2.5 V\" -to fsm_d[22]\nset_instance_assignment -name IO_STANDARD \"2.5 V\" -to fsm_d[23]\nset_instance_assignment -name IO_STANDARD \"2.5 V\" -to fsm_d[24]\nset_instance_assignment -name IO_STANDARD \"2.5 V\" -to fsm_d[25]\nset_instance_assignment -name IO_STANDARD \"2.5 V\" -to fsm_d[26]\nset_instance_assignment -name IO_STANDARD \"2.5 V\" -to fsm_d[27]\nset_instance_assignment -name IO_STANDARD \"2.5 V\" -to fsm_d[28]\nset_instance_assignment -name IO_STANDARD \"2.5 V\" -to fsm_d[29]\nset_instance_assignment -name IO_STANDARD \"2.5 V\" -to fsm_d[30]\nset_instance_assignment -name IO_STANDARD \"2.5 V\" -to fsm_d[31]\n#============================================================\n# HEX0\n#============================================================\nset_instance_assignment -name IO_STANDARD \"1.5 V\" -to hex0_d[0]\nset_instance_assignment -name IO_STANDARD \"1.5 V\" -to hex0_d[1]\nset_instance_assignment -name IO_STANDARD \"1.5 V\" -to hex0_d[2]\nset_instance_assignment -name IO_STANDARD \"1.5 V\" -to hex0_d[3]\nset_instance_assignment -name IO_STANDARD \"1.5 V\" -to hex0_d[4]\nset_instance_assignment -name IO_STANDARD \"1.5 V\" -to hex0_d[5]\nset_instance_assignment -name IO_STANDARD \"1.5 V\" -to hex0_d[6]\nset_instance_assignment -name IO_STANDARD \"1.5 V\" -to hex0_dp\n#============================================================\n# HEX1\n#============================================================\nset_instance_assignment -name IO_STANDARD \"1.5 V\" -to hex1_d[0]\nset_instance_assignment -name IO_STANDARD \"1.5 V\" -to hex1_d[1]\nset_instance_assignment -name IO_STANDARD \"1.5 V\" -to hex1_d[2]\nset_instance_assignment -name IO_STANDARD \"1.5 V\" -to hex1_d[3]\nset_instance_assignment -name IO_STANDARD \"1.5 V\" -to hex1_d[4]\nset_instance_assignment -name IO_STANDARD \"1.5 V\" -to hex1_d[5]\nset_instance_assignment -name IO_STANDARD \"1.5 V\" -to hex1_d[6]\nset_instance_assignment -name IO_STANDARD \"1.5 V\" -to hex1_dp\n#============================================================\n# LED\n#============================================================\nset_instance_assignment -name IO_STANDARD \"2.5 V\" -to leds[0]\nset_instance_assignment -name IO_STANDARD \"2.5 V\" -to leds[1]\nset_instance_assignment -name IO_STANDARD \"2.5 V\" -to leds[2]\nset_instance_assignment -name IO_STANDARD \"2.5 V\" -to leds[3]\nset_instance_assignment -name IO_STANDARD \"2.5 V\" -to led_bracket[0]\nset_instance_assignment -name IO_STANDARD \"2.5 V\" -to led_bracket[1]\nset_instance_assignment -name IO_STANDARD \"2.5 V\" -to led_bracket[2]\nset_instance_assignment -name IO_STANDARD \"2.5 V\" -to led_bracket[3]\nset_instance_assignment -name IO_STANDARD \"2.5 V\" -to led_rj45_l\nset_instance_assignment -name IO_STANDARD \"2.5 V\" -to led_rj45_r\n#============================================================\n# MAX2\n#============================================================\n#============================================================\n# OSC\n#============================================================\nset_instance_assignment -name IO_STANDARD \"2.5 V\" -to osc_50_b3b\nset_instance_assignment -name IO_STANDARD \"1.8 V\" -to osc_50_b3d\nset_instance_assignment -name IO_STANDARD \"1.8 V\" -to osc_50_b4a\nset_instance_assignment -name IO_STANDARD \"1.8 V\" -to osc_50_b4d\nset_instance_assignment -name IO_STANDARD \"1.5 V\" -to osc_50_b7a\nset_instance_assignment -name IO_STANDARD \"1.5 V\" -to osc_50_b7d\nset_instance_assignment -name IO_STANDARD \"1.5 V\" -to osc_50_b8a\nset_instance_assignment -name IO_STANDARD \"1.8 V\" -to osc_50_b8d\n#============================================================\n# PCIE\n#============================================================\nset_instance_assignment -name IO_STANDARD \"2.5 V\" -to pcie_perst_n\nset_instance_assignment -name IO_STANDARD HCSL -to pcie_refclk_p\nset_instance_assignment -name IO_STANDARD \"1.4-V PCML\" -to PCIE_rx_p[0]\nset_instance_assignment -name IO_STANDARD \"1.4-V PCML\" -to PCIE_rx_p[1]\nset_instance_assignment -name IO_STANDARD \"1.4-V PCML\" -to PCIE_rx_p[2]\nset_instance_assignment -name IO_STANDARD \"1.4-V PCML\" -to PCIE_rx_p[3]\nset_instance_assignment -name IO_STANDARD \"1.4-V PCML\" -to PCIE_rx_p[4]\nset_instance_assignment -name IO_STANDARD \"1.4-V PCML\" -to PCIE_rx_p[5]\nset_instance_assignment -name IO_STANDARD \"1.4-V PCML\" -to PCIE_rx_p[6]\nset_instance_assignment -name IO_STANDARD \"1.4-V PCML\" -to PCIE_rx_p[7]\nset_instance_assignment -name IO_STANDARD \"2.5 V\" -to pcie_smbclk\nset_instance_assignment -name IO_STANDARD \"2.5 V\" -to pcie_smbdat\nset_instance_assignment -name IO_STANDARD \"1.4-V PCML\" -to PCIE_tx_p[0]\nset_instance_assignment -name IO_STANDARD \"1.4-V PCML\" -to PCIE_tx_p[1]\nset_instance_assignment -name IO_STANDARD \"1.4-V PCML\" -to PCIE_tx_p[2]\nset_instance_assignment -name IO_STANDARD \"1.4-V PCML\" -to PCIE_tx_p[3]\nset_instance_assignment -name IO_STANDARD \"1.4-V PCML\" -to PCIE_tx_p[4]\nset_instance_assignment -name IO_STANDARD \"1.4-V PCML\" -to PCIE_tx_p[5]\nset_instance_assignment -name IO_STANDARD \"1.4-V PCML\" -to PCIE_tx_p[6]\nset_instance_assignment -name IO_STANDARD \"1.4-V PCML\" -to PCIE_tx_p[7]\nset_instance_assignment -name IO_STANDARD \"2.5 V\" -to pcie_wake_n\n#============================================================\n# QDRIIA\n#============================================================\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriia_a[0]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriia_a[1]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriia_a[2]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriia_a[3]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriia_a[4]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriia_a[5]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriia_a[6]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriia_a[7]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriia_a[8]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriia_a[9]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriia_a[10]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriia_a[11]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriia_a[12]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriia_a[13]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriia_a[14]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriia_a[15]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriia_a[16]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriia_a[17]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriia_a[18]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriia_a[19]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriia_a[20]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriia_bws_n[0]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriia_bws_n[1]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriia_cq_n\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriia_cq_p\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriia_d[0]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriia_d[1]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriia_d[2]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriia_d[3]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriia_d[4]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriia_d[5]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriia_d[6]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriia_d[7]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriia_d[8]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriia_d[9]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriia_d[10]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriia_d[11]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriia_d[12]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriia_d[13]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriia_d[14]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriia_d[15]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriia_d[16]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriia_d[17]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriia_doff_n\nset_instance_assignment -name IO_STANDARD \"DIFFERENTIAL 1.8-V HSTL CLASS I\" -to qdriia_k_n\nset_instance_assignment -name IO_STANDARD \"DIFFERENTIAL 1.8-V HSTL CLASS I\" -to qdriia_k_p\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriia_odt\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriia_q[0]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriia_q[1]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriia_q[2]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriia_q[3]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriia_q[4]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriia_q[5]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriia_q[6]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriia_q[7]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriia_q[8]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriia_q[9]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriia_q[10]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriia_q[11]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriia_q[12]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriia_q[13]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriia_q[14]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriia_q[15]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriia_q[16]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriia_q[17]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriia_qvld\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriia_rps_n\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriia_wps_n\n#============================================================\n# QDRIIB\n#============================================================\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriib_a[0]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriib_a[1]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriib_a[2]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriib_a[3]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriib_a[4]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriib_a[5]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriib_a[6]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriib_a[7]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriib_a[8]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriib_a[9]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriib_a[10]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriib_a[11]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriib_a[12]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriib_a[13]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriib_a[14]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriib_a[15]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriib_a[16]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriib_a[17]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriib_a[18]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriib_a[19]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriib_a[20]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriib_bws_n[0]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriib_bws_n[1]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriib_cq_n\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriib_cq_p\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriib_d[0]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriib_d[1]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriib_d[2]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriib_d[3]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriib_d[4]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriib_d[5]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriib_d[6]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriib_d[7]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriib_d[8]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriib_d[9]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriib_d[10]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriib_d[11]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriib_d[12]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriib_d[13]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriib_d[14]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriib_d[15]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriib_d[16]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriib_d[17]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriib_doff_n\nset_instance_assignment -name IO_STANDARD \"DIFFERENTIAL 1.8-V HSTL CLASS I\" -to qdriib_k_n\nset_instance_assignment -name IO_STANDARD \"DIFFERENTIAL 1.8-V HSTL CLASS I\" -to qdriib_k_p\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriib_odt\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriib_q[0]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriib_q[1]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriib_q[2]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriib_q[3]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriib_q[4]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriib_q[5]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriib_q[6]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriib_q[7]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriib_q[8]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriib_q[9]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriib_q[10]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriib_q[11]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriib_q[12]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriib_q[13]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriib_q[14]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriib_q[15]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriib_q[16]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriib_q[17]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriib_qvld\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriib_rps_n\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriib_wps_n\n#============================================================\n# QDRIIC\n#============================================================\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriic_a[0]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriic_a[1]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriic_a[2]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriic_a[3]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriic_a[4]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriic_a[5]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriic_a[6]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriic_a[7]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriic_a[8]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriic_a[9]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriic_a[10]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriic_a[11]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriic_a[12]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriic_a[13]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriic_a[14]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriic_a[15]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriic_a[16]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriic_a[17]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriic_a[18]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriic_a[19]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriic_a[20]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriic_bws_n[0]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriic_bws_n[1]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriic_cq_n\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriic_cq_p\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriic_d[0]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriic_d[1]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriic_d[2]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriic_d[3]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriic_d[4]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriic_d[5]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriic_d[6]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriic_d[7]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriic_d[8]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriic_d[9]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriic_d[10]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriic_d[11]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriic_d[12]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriic_d[13]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriic_d[14]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriic_d[15]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriic_d[16]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriic_d[17]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriic_doff_n\nset_instance_assignment -name IO_STANDARD \"DIFFERENTIAL 1.8-V HSTL CLASS I\" -to qdriic_k_n\nset_instance_assignment -name IO_STANDARD \"DIFFERENTIAL 1.8-V HSTL CLASS I\" -to qdriic_k_p\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriic_odt\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriic_q[0]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriic_q[1]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriic_q[2]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriic_q[3]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriic_q[4]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriic_q[5]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriic_q[6]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriic_q[7]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriic_q[8]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriic_q[9]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriic_q[10]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriic_q[11]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriic_q[12]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriic_q[13]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriic_q[14]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriic_q[15]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriic_q[16]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriic_q[17]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriic_qvld\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriic_rps_n\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriic_wps_n\n#============================================================\n# QDRIID\n#============================================================\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriid_a[0]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriid_a[1]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriid_a[2]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriid_a[3]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriid_a[4]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriid_a[5]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriid_a[6]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriid_a[7]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriid_a[8]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriid_a[9]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriid_a[10]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriid_a[11]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriid_a[12]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriid_a[13]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriid_a[14]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriid_a[15]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriid_a[16]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriid_a[17]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriid_a[18]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriid_a[19]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriid_a[20]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriid_bws_n[0]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriid_bws_n[1]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriid_cq_n\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriid_cq_p\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriid_d[0]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriid_d[1]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriid_d[2]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriid_d[3]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriid_d[4]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriid_d[5]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriid_d[6]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriid_d[7]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriid_d[8]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriid_d[9]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriid_d[10]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriid_d[11]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriid_d[12]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriid_d[13]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriid_d[14]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriid_d[15]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriid_d[16]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriid_d[17]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriid_doff_n\nset_instance_assignment -name IO_STANDARD \"DIFFERENTIAL 1.8-V HSTL CLASS I\" -to qdriid_k_n\nset_instance_assignment -name IO_STANDARD \"DIFFERENTIAL 1.8-V HSTL CLASS I\" -to qdriid_k_p\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriid_odt\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriid_q[0]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriid_q[1]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriid_q[2]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriid_q[3]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriid_q[4]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriid_q[5]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriid_q[6]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriid_q[7]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriid_q[8]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriid_q[9]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriid_q[10]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriid_q[11]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriid_q[12]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriid_q[13]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriid_q[14]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriid_q[15]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriid_q[16]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriid_q[17]\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriid_qvld\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriid_rps_n\nset_instance_assignment -name IO_STANDARD \"1.8-V HSTL CLASS I\" -to qdriid_wps_n\n#============================================================\n# RS422\n#============================================================\nset_instance_assignment -name IO_STANDARD \"2.5 V\" -to rs422_de\nset_instance_assignment -name IO_STANDARD \"2.5 V\" -to rs422_din\nset_instance_assignment -name IO_STANDARD \"2.5 V\" -to rs422_dout\nset_instance_assignment -name IO_STANDARD \"2.5 V\" -to rs422_re_n\nset_instance_assignment -name IO_STANDARD \"2.5 V\" -to rs422_te\n#============================================================\n# RZQ\n#============================================================\nset_instance_assignment -name IO_STANDARD \"2.5 V\" -to rzq_0\nset_instance_assignment -name IO_STANDARD \"1.8 V\" -to rzq_1\nset_instance_assignment -name IO_STANDARD \"1.5 V\" -to rzq_4\nset_instance_assignment -name IO_STANDARD \"1.5 V\" -to rzq_5\n#============================================================\n# SATA\n#============================================================\n#============================================================\n# SFP10G\n#============================================================\n#============================================================\n# SFP1G\n#============================================================\nset_instance_assignment -name IO_STANDARD HCSL -to sfp1g_refclk_p\n#============================================================\n# SFPA\n#============================================================\nset_instance_assignment -name IO_STANDARD \"2.5 V\" -to sfpa_los\nset_instance_assignment -name IO_STANDARD \"2.5 V\" -to sfpa_mod0_prsnt_n\nset_instance_assignment -name IO_STANDARD \"2.5 V\" -to sfpa_mod1_scl\nset_instance_assignment -name IO_STANDARD \"2.5 V\" -to sfpa_mod2_sda\nset_instance_assignment -name IO_STANDARD \"2.5 V\" -to sfpa_ratesel[0]\nset_instance_assignment -name IO_STANDARD \"2.5 V\" -to sfpa_ratesel[1]\nset_instance_assignment -name IO_STANDARD \"1.4-V PCML\" -to sfpa_rx_p\nset_instance_assignment -name IO_STANDARD \"2.5 V\" -to sfpa_txdisable\nset_instance_assignment -name IO_STANDARD \"2.5 V\" -to sfpa_txfault\nset_instance_assignment -name IO_STANDARD \"1.4-V PCML\" -to sfpa_tx_p\n#============================================================\n# SFPB\n#============================================================\nset_instance_assignment -name IO_STANDARD \"2.5 V\" -to sfpb_los\nset_instance_assignment -name IO_STANDARD \"2.5 V\" -to sfpb_mod0_prsnt_n\nset_instance_assignment -name IO_STANDARD \"2.5 V\" -to sfpb_mod1_scl\nset_instance_assignment -name IO_STANDARD \"2.5 V\" -to sfpb_mod2_sda\nset_instance_assignment -name IO_STANDARD \"2.5 V\" -to sfpb_ratesel[0]\nset_instance_assignment -name IO_STANDARD \"2.5 V\" -to sfpb_ratesel[1]\nset_instance_assignment -name IO_STANDARD \"1.4-V PCML\" -to sfpb_rx_p\nset_instance_assignment -name IO_STANDARD \"2.5 V\" -to sfpb_txdisable\nset_instance_assignment -name IO_STANDARD \"2.5 V\" -to sfpb_txfault\nset_instance_assignment -name IO_STANDARD \"1.4-V PCML\" -to sfpb_tx_p\n#============================================================\n# SFPC\n#============================================================\nset_instance_assignment -name IO_STANDARD \"2.5 V\" -to sfpc_los\nset_instance_assignment -name IO_STANDARD \"2.5 V\" -to sfpc_mod0_prsnt_n\nset_instance_assignment -name IO_STANDARD \"2.5 V\" -to sfpc_mod1_scl\nset_instance_assignment -name IO_STANDARD \"2.5 V\" -to sfpc_mod2_sda\nset_instance_assignment -name IO_STANDARD \"2.5 V\" -to sfpc_ratesel[0]\nset_instance_assignment -name IO_STANDARD \"2.5 V\" -to sfpc_ratesel[1]\nset_instance_assignment -name IO_STANDARD \"1.4-V PCML\" -to sfpc_rx_p\nset_instance_assignment -name IO_STANDARD \"2.5 V\" -to sfpc_txdisable\nset_instance_assignment -name IO_STANDARD \"2.5 V\" -to sfpc_txfault\nset_instance_assignment -name IO_STANDARD \"1.4-V PCML\" -to sfpc_tx_p\n#============================================================\n# SFPD\n#============================================================\nset_instance_assignment -name IO_STANDARD \"2.5 V\" -to sfpd_los\nset_instance_assignment -name IO_STANDARD \"2.5 V\" -to sfpd_mod0_prsnt_n\nset_instance_assignment -name IO_STANDARD \"2.5 V\" -to sfpd_mod1_scl\nset_instance_assignment -name IO_STANDARD \"2.5 V\" -to sfpd_mod2_sda\nset_instance_assignment -name IO_STANDARD \"2.5 V\" -to sfpd_ratesel[0]\nset_instance_assignment -name IO_STANDARD \"2.5 V\" -to sfpd_ratesel[1]\nset_instance_assignment -name IO_STANDARD \"1.4-V PCML\" -to sfpd_rx_p\nset_instance_assignment -name IO_STANDARD \"2.5 V\" -to sfpd_txdisable\nset_instance_assignment -name IO_STANDARD \"2.5 V\" -to sfpd_txfault\nset_instance_assignment -name IO_STANDARD \"1.4-V PCML\" -to sfpd_tx_p\nset_instance_assignment -name IO_STANDARD HCSL -to sfp_refclk_p\n#============================================================\n# SMA\n#============================================================\nset_instance_assignment -name IO_STANDARD \"2.5 V\" -to sma_clkin\nset_instance_assignment -name IO_STANDARD \"2.5 V\" -to sma_clkout\n#============================================================\n# SW\n#============================================================\nset_instance_assignment -name IO_STANDARD \"1.8 V\" -to sw[0]\nset_instance_assignment -name IO_STANDARD \"1.8 V\" -to sw[1]\nset_instance_assignment -name IO_STANDARD \"1.8 V\" -to sw[2]\nset_instance_assignment -name IO_STANDARD \"1.8 V\" -to sw[3]\n#============================================================\n# TEMP\n#============================================================\nset_instance_assignment -name IO_STANDARD \"2.5 V\" -to temp_clk\nset_instance_assignment -name IO_STANDARD \"2.5 V\" -to temp_data\nset_instance_assignment -name IO_STANDARD \"2.5 V\" -to temp_int_n\nset_instance_assignment -name IO_STANDARD \"2.5 V\" -to temp_overt_n\n\n#============================================================\n# SATA\n#============================================================\nset_instance_assignment -name IO_STANDARD HCSL -to sata_host_refclk_p\nset_instance_assignment -name IO_STANDARD HCSL -to sata_device_refclk_p\nset_instance_assignment -name IO_STANDARD \"1.4-V PCML\" -to sata_device_rx_p[0]\nset_instance_assignment -name IO_STANDARD \"1.4-V PCML\" -to sata_device_rx_p[1]\nset_instance_assignment -name IO_STANDARD \"1.4-V PCML\" -to sata_device_tx_p[0]\nset_instance_assignment -name IO_STANDARD \"1.4-V PCML\" -to sata_device_tx_p[1]\nset_instance_assignment -name IO_STANDARD \"1.4-V PCML\" -to sata_host_rx_p[0]\nset_instance_assignment -name IO_STANDARD \"1.4-V PCML\" -to sata_host_rx_p[1]\nset_instance_assignment -name IO_STANDARD \"1.4-V PCML\" -to sata_host_tx_p[0]\nset_instance_assignment -name IO_STANDARD \"1.4-V PCML\" -to sata_host_tx_p[1]\n\n#============================================================\n# SATA\n#============================================================\nset_instance_assignment -name IO_STANDARD \"2.5 V\" -to pll_scl\nset_location_assignment PIN_AF32 -to pll_scl\nset_instance_assignment -name IO_STANDARD \"2.5 V\" -to pll_sda\nset_location_assignment PIN_AG32 -to pll_sda\n\n#============================================================\n# End of pin assignments by Terasic System Builder\n#============================================================\n\n\nset_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION \"USE AS REGULAR IO\"\nset_location_assignment PIN_AK15 -to button[0]\nset_location_assignment PIN_AK14 -to button[1]\nset_location_assignment PIN_AL14 -to button[2]\nset_location_assignment PIN_AL15 -to button[3]\nset_location_assignment PIN_AE15 -to clock_scl\nset_location_assignment PIN_AE16 -to clock_sda\nset_location_assignment PIN_BC37 -to cpu_reset_n\nset_location_assignment PIN_M39 -to ddr3a_a[0]\nset_location_assignment PIN_L35 -to ddr3a_a[1]\nset_location_assignment PIN_N38 -to ddr3a_a[2]\nset_location_assignment PIN_L36 -to ddr3a_a[3]\nset_location_assignment PIN_H36 -to ddr3a_a[4]\nset_location_assignment PIN_K29 -to ddr3a_a[5]\nset_location_assignment PIN_D37 -to ddr3a_a[6]\nset_location_assignment PIN_K35 -to ddr3a_a[7]\nset_location_assignment PIN_K32 -to ddr3a_a[8]\nset_location_assignment PIN_K37 -to ddr3a_a[9]\nset_location_assignment PIN_M38 -to ddr3a_a[10]\nset_location_assignment PIN_C37 -to ddr3a_a[11]\nset_location_assignment PIN_K36 -to ddr3a_a[12]\nset_location_assignment PIN_M33 -to ddr3a_a[13]\nset_location_assignment PIN_K34 -to ddr3a_a[14]\nset_location_assignment PIN_B38 -to ddr3a_a[15]\nset_location_assignment PIN_M37 -to ddr3a_ba[0]\nset_location_assignment PIN_P39 -to ddr3a_ba[1]\nset_location_assignment PIN_J36 -to ddr3a_ba[2]\nset_location_assignment PIN_M36 -to ddr3a_cas_n\nset_location_assignment PIN_G37 -to ddr3a_ck[0]\nset_location_assignment PIN_J37 -to ddr3a_ck[1]\nset_location_assignment PIN_E36 -to ddr3a_cke[0]\nset_location_assignment PIN_B35 -to ddr3a_cke[1]\nset_location_assignment PIN_F36 -to ddr3a_ck_n[0]\nset_location_assignment PIN_H37 -to ddr3a_ck_n[1]\nset_location_assignment PIN_P36 -to ddr3a_cs_n[0]\nset_location_assignment PIN_R28 -to ddr3a_cs_n[1]\nset_location_assignment PIN_C36 -to ddr3a_dm[0]\nset_location_assignment PIN_E32 -to ddr3a_dm[1]\nset_location_assignment PIN_H34 -to ddr3a_dm[2]\nset_location_assignment PIN_L32 -to ddr3a_dm[3]\nset_location_assignment PIN_N32 -to ddr3a_dm[4]\nset_location_assignment PIN_W32 -to ddr3a_dm[5]\nset_location_assignment PIN_K30 -to ddr3a_dm[6]\nset_location_assignment PIN_T28 -to ddr3a_dm[7]\nset_location_assignment PIN_A35 -to ddr3a_dq[0]\nset_location_assignment PIN_A34 -to ddr3a_dq[1]\nset_location_assignment PIN_D36 -to ddr3a_dq[2]\nset_location_assignment PIN_C33 -to ddr3a_dq[3]\nset_location_assignment PIN_B32 -to ddr3a_dq[4]\nset_location_assignment PIN_D35 -to ddr3a_dq[5]\nset_location_assignment PIN_D33 -to ddr3a_dq[6]\nset_location_assignment PIN_E33 -to ddr3a_dq[7]\nset_location_assignment PIN_A32 -to ddr3a_dq[8]\nset_location_assignment PIN_A31 -to ddr3a_dq[9]\nset_location_assignment PIN_C30 -to ddr3a_dq[10]\nset_location_assignment PIN_D30 -to ddr3a_dq[11]\nset_location_assignment PIN_B29 -to ddr3a_dq[12]\nset_location_assignment PIN_E30 -to ddr3a_dq[13]\nset_location_assignment PIN_F31 -to ddr3a_dq[14]\nset_location_assignment PIN_G31 -to ddr3a_dq[15]\nset_location_assignment PIN_F35 -to ddr3a_dq[16]\nset_location_assignment PIN_G34 -to ddr3a_dq[17]\nset_location_assignment PIN_J33 -to ddr3a_dq[18]\nset_location_assignment PIN_J34 -to ddr3a_dq[19]\nset_location_assignment PIN_F34 -to ddr3a_dq[20]\nset_location_assignment PIN_E35 -to ddr3a_dq[21]\nset_location_assignment PIN_J31 -to ddr3a_dq[22]\nset_location_assignment PIN_K31 -to ddr3a_dq[23]\nset_location_assignment PIN_P34 -to ddr3a_dq[24]\nset_location_assignment PIN_R33 -to ddr3a_dq[25]\nset_location_assignment PIN_M34 -to ddr3a_dq[26]\nset_location_assignment PIN_L33 -to ddr3a_dq[27]\nset_location_assignment PIN_R34 -to ddr3a_dq[28]\nset_location_assignment PIN_T34 -to ddr3a_dq[29]\nset_location_assignment PIN_W34 -to ddr3a_dq[30]\nset_location_assignment PIN_V35 -to ddr3a_dq[31]\nset_location_assignment PIN_P33 -to ddr3a_dq[32]\nset_location_assignment PIN_P32 -to ddr3a_dq[33]\nset_location_assignment PIN_V33 -to ddr3a_dq[34]\nset_location_assignment PIN_V34 -to ddr3a_dq[35]\nset_location_assignment PIN_N31 -to ddr3a_dq[36]\nset_location_assignment PIN_M31 -to ddr3a_dq[37]\nset_location_assignment PIN_U32 -to ddr3a_dq[38]\nset_location_assignment PIN_U33 -to ddr3a_dq[39]\nset_location_assignment PIN_R31 -to ddr3a_dq[40]\nset_location_assignment PIN_W31 -to ddr3a_dq[41]\nset_location_assignment PIN_U30 -to ddr3a_dq[42]\nset_location_assignment PIN_P31 -to ddr3a_dq[43]\nset_location_assignment PIN_T31 -to ddr3a_dq[44]\nset_location_assignment PIN_Y32 -to ddr3a_dq[45]\nset_location_assignment PIN_T29 -to ddr3a_dq[46]\nset_location_assignment PIN_P30 -to ddr3a_dq[47]\nset_location_assignment PIN_H32 -to ddr3a_dq[48]\nset_location_assignment PIN_H31 -to ddr3a_dq[49]\nset_location_assignment PIN_L30 -to ddr3a_dq[50]\nset_location_assignment PIN_L29 -to ddr3a_dq[51]\nset_location_assignment PIN_F32 -to ddr3a_dq[52]\nset_location_assignment PIN_G32 -to ddr3a_dq[53]\nset_location_assignment PIN_M30 -to ddr3a_dq[54]\nset_location_assignment PIN_N29 -to ddr3a_dq[55]\nset_location_assignment PIN_U29 -to ddr3a_dq[56]\nset_location_assignment PIN_V28 -to ddr3a_dq[57]\nset_location_assignment PIN_Y28 -to ddr3a_dq[58]\nset_location_assignment PIN_W29 -to ddr3a_dq[59]\nset_location_assignment PIN_V30 -to ddr3a_dq[60]\nset_location_assignment PIN_V29 -to ddr3a_dq[61]\nset_location_assignment PIN_W28 -to ddr3a_dq[62]\nset_location_assignment PIN_Y27 -to ddr3a_dq[63]\nset_location_assignment PIN_C34 -to ddr3a_dqs[0]\nset_location_assignment PIN_C31 -to ddr3a_dqs[1]\nset_location_assignment PIN_H35 -to ddr3a_dqs[2]\nset_location_assignment PIN_U35 -to ddr3a_dqs[3]\nset_location_assignment PIN_T33 -to ddr3a_dqs[4]\nset_location_assignment PIN_T30 -to ddr3a_dqs[5]\nset_location_assignment PIN_J30 -to ddr3a_dqs[6]\nset_location_assignment PIN_Y30 -to ddr3a_dqs[7]\nset_location_assignment PIN_B34 -to ddr3a_dqs_n[0]\nset_location_assignment PIN_B31 -to ddr3a_dqs_n[1]\nset_location_assignment PIN_G35 -to ddr3a_dqs_n[2]\nset_location_assignment PIN_T35 -to ddr3a_dqs_n[3]\nset_location_assignment PIN_T32 -to ddr3a_dqs_n[4]\nset_location_assignment PIN_R30 -to ddr3a_dqs_n[5]\nset_location_assignment PIN_H30 -to ddr3a_dqs_n[6]\nset_location_assignment PIN_Y29 -to ddr3a_dqs_n[7]\nset_location_assignment PIN_K19 -to ddr3a_event_n\nset_location_assignment PIN_V36 -to ddr3a_odt[0]\nset_location_assignment PIN_W35 -to ddr3a_odt[1]\nset_location_assignment PIN_P38 -to ddr3a_ras_n\nset_location_assignment PIN_H33 -to ddr3a_reset_n\nset_location_assignment PIN_C15 -to ddr3a_scl\nset_location_assignment PIN_P15 -to ddr3a_sda\nset_location_assignment PIN_N37 -to ddr3a_we_n\nset_location_assignment PIN_G17 -to ddr3b_a[0]\nset_location_assignment PIN_F17 -to ddr3b_a[1]\nset_location_assignment PIN_N17 -to ddr3b_a[2]\nset_location_assignment PIN_F19 -to ddr3b_a[3]\nset_location_assignment PIN_N19 -to ddr3b_a[4]\nset_location_assignment PIN_H16 -to ddr3b_a[5]\nset_location_assignment PIN_M17 -to ddr3b_a[6]\nset_location_assignment PIN_T18 -to ddr3b_a[7]\nset_location_assignment PIN_H17 -to ddr3b_a[8]\nset_location_assignment PIN_J19 -to ddr3b_a[9]\nset_location_assignment PIN_C19 -to ddr3b_a[10]\nset_location_assignment PIN_R18 -to ddr3b_a[11]\nset_location_assignment PIN_K18 -to ddr3b_a[12]\nset_location_assignment PIN_E18 -to ddr3b_a[13]\nset_location_assignment PIN_T19 -to ddr3b_a[14]\nset_location_assignment PIN_R19 -to ddr3b_a[15]\nset_location_assignment PIN_C18 -to ddr3b_ba[0]\nset_location_assignment PIN_G19 -to ddr3b_ba[1]\nset_location_assignment PIN_M20 -to ddr3b_ba[2]\nset_location_assignment PIN_A17 -to ddr3b_cas_n\nset_location_assignment PIN_B16 -to ddr3b_ck[0]\nset_location_assignment PIN_E17 -to ddr3b_ck[1]\nset_location_assignment PIN_P17 -to ddr3b_cke[0]\nset_location_assignment PIN_V18 -to ddr3b_cke[1]\nset_location_assignment PIN_A16 -to ddr3b_ck_n[0]\nset_location_assignment PIN_D17 -to ddr3b_ck_n[1]\nset_location_assignment PIN_B19 -to ddr3b_cs_n[0]\nset_location_assignment PIN_B17 -to ddr3b_cs_n[1]\nset_location_assignment PIN_R15 -to ddr3b_dm[0]\nset_location_assignment PIN_K15 -to ddr3b_dm[1]\nset_location_assignment PIN_V12 -to ddr3b_dm[2]\nset_location_assignment PIN_G10 -to ddr3b_dm[3]\nset_location_assignment PIN_T12 -to ddr3b_dm[4]\nset_location_assignment PIN_C16 -to ddr3b_dm[5]\nset_location_assignment PIN_H15 -to ddr3b_dm[6]\nset_location_assignment PIN_B11 -to ddr3b_dm[7]\nset_location_assignment PIN_Y17 -to ddr3b_dq[0]\nset_location_assignment PIN_W17 -to ddr3b_dq[1]\nset_location_assignment PIN_V15 -to ddr3b_dq[2]\nset_location_assignment PIN_T15 -to ddr3b_dq[3]\nset_location_assignment PIN_V13 -to ddr3b_dq[4]\nset_location_assignment PIN_V16 -to ddr3b_dq[5]\nset_location_assignment PIN_W14 -to ddr3b_dq[6]\nset_location_assignment PIN_U15 -to ddr3b_dq[7]\nset_location_assignment PIN_T17 -to ddr3b_dq[8]\nset_location_assignment PIN_T16 -to ddr3b_dq[9]\nset_location_assignment PIN_R16 -to ddr3b_dq[10]\nset_location_assignment PIN_P16 -to ddr3b_dq[11]\nset_location_assignment PIN_N16 -to ddr3b_dq[12]\nset_location_assignment PIN_M15 -to ddr3b_dq[13]\nset_location_assignment PIN_M14 -to ddr3b_dq[14]\nset_location_assignment PIN_L14 -to ddr3b_dq[15]\nset_location_assignment PIN_T14 -to ddr3b_dq[16]\nset_location_assignment PIN_U14 -to ddr3b_dq[17]\nset_location_assignment PIN_U11 -to ddr3b_dq[18]\nset_location_assignment PIN_T13 -to ddr3b_dq[19]\nset_location_assignment PIN_U12 -to ddr3b_dq[20]\nset_location_assignment PIN_R13 -to ddr3b_dq[21]\nset_location_assignment PIN_P13 -to ddr3b_dq[22]\nset_location_assignment PIN_N13 -to ddr3b_dq[23]\nset_location_assignment PIN_K12 -to ddr3b_dq[24]\nset_location_assignment PIN_J12 -to ddr3b_dq[25]\nset_location_assignment PIN_J10 -to ddr3b_dq[26]\nset_location_assignment PIN_H12 -to ddr3b_dq[27]\nset_location_assignment PIN_N11 -to ddr3b_dq[28]\nset_location_assignment PIN_M11 -to ddr3b_dq[29]\nset_location_assignment PIN_H10 -to ddr3b_dq[30]\nset_location_assignment PIN_H11 -to ddr3b_dq[31]\nset_location_assignment PIN_T10 -to ddr3b_dq[32]\nset_location_assignment PIN_R10 -to ddr3b_dq[33]\nset_location_assignment PIN_M12 -to ddr3b_dq[34]\nset_location_assignment PIN_L12 -to ddr3b_dq[35]\nset_location_assignment PIN_V10 -to ddr3b_dq[36]\nset_location_assignment PIN_V9 -to ddr3b_dq[37]\nset_location_assignment PIN_R12 -to ddr3b_dq[38]\nset_location_assignment PIN_P12 -to ddr3b_dq[39]\nset_location_assignment PIN_D14 -to ddr3b_dq[40]\nset_location_assignment PIN_C13 -to ddr3b_dq[41]\nset_location_assignment PIN_B14 -to ddr3b_dq[42]\nset_location_assignment PIN_B13 -to ddr3b_dq[43]\nset_location_assignment PIN_E14 -to ddr3b_dq[44]\nset_location_assignment PIN_F14 -to ddr3b_dq[45]\nset_location_assignment PIN_A14 -to ddr3b_dq[46]\nset_location_assignment PIN_A13 -to ddr3b_dq[47]\nset_location_assignment PIN_K13 -to ddr3b_dq[48]\nset_location_assignment PIN_K16 -to ddr3b_dq[49]\nset_location_assignment PIN_H13 -to ddr3b_dq[50]\nset_location_assignment PIN_H14 -to ddr3b_dq[51]\nset_location_assignment PIN_J13 -to ddr3b_dq[52]\nset_location_assignment PIN_J16 -to ddr3b_dq[53]\nset_location_assignment PIN_G13 -to ddr3b_dq[54]\nset_location_assignment PIN_F13 -to ddr3b_dq[55]\nset_location_assignment PIN_D11 -to ddr3b_dq[56]\nset_location_assignment PIN_C10 -to ddr3b_dq[57]\nset_location_assignment PIN_A10 -to ddr3b_dq[58]\nset_location_assignment PIN_B10 -to ddr3b_dq[59]\nset_location_assignment PIN_G11 -to ddr3b_dq[60]\nset_location_assignment PIN_F11 -to ddr3b_dq[61]\nset_location_assignment PIN_E11 -to ddr3b_dq[62]\nset_location_assignment PIN_E12 -to ddr3b_dq[63]\nset_location_assignment PIN_Y16 -to ddr3b_dqs[0]\nset_location_assignment PIN_V17 -to ddr3b_dqs[1]\nset_location_assignment PIN_P14 -to ddr3b_dqs[2]\nset_location_assignment PIN_K11 -to ddr3b_dqs[3]\nset_location_assignment PIN_U9 -to ddr3b_dqs[4]\nset_location_assignment PIN_E15 -to ddr3b_dqs[5]\nset_location_assignment PIN_L15 -to ddr3b_dqs[6]\nset_location_assignment PIN_D12 -to ddr3b_dqs[7]\nset_location_assignment PIN_W16 -to ddr3b_dqs_n[0]\nset_location_assignment PIN_U17 -to ddr3b_dqs_n[1]\nset_location_assignment PIN_N14 -to ddr3b_dqs_n[2]\nset_location_assignment PIN_L11 -to ddr3b_dqs_n[3]\nset_location_assignment PIN_T9 -to ddr3b_dqs_n[4]\nset_location_assignment PIN_D15 -to ddr3b_dqs_n[5]\nset_location_assignment PIN_K14 -to ddr3b_dqs_n[6]\nset_location_assignment PIN_C12 -to ddr3b_dqs_n[7]\nset_location_assignment PIN_K17 -to ddr3b_event_n\nset_location_assignment PIN_M18 -to ddr3b_odt[0]\nset_location_assignment PIN_A19 -to ddr3b_odt[1]\nset_location_assignment PIN_H19 -to ddr3b_ras_n\nset_location_assignment PIN_T20 -to ddr3b_reset_n\nset_location_assignment PIN_P18 -to ddr3b_scl\nset_location_assignment PIN_P19 -to ddr3b_sda\nset_location_assignment PIN_D18 -to ddr3b_we_n\nset_location_assignment PIN_AR32 -to fan_ctrl\nset_location_assignment PIN_AK29 -to flash_adv_n\nset_location_assignment PIN_AE27 -to flash_ce_n[0]\nset_location_assignment PIN_BA31 -to flash_ce_n[1]\nset_location_assignment PIN_AL29 -to flash_clk\nset_location_assignment PIN_AY30 -to flash_oe_n\nset_location_assignment PIN_BA29 -to flash_rdy_bsy_n[0]\nset_location_assignment PIN_BB32 -to flash_rdy_bsy_n[1]\nset_location_assignment PIN_AE28 -to flash_reset_n\nset_location_assignment PIN_AR31 -to flash_we_n\nset_location_assignment PIN_AU32 -to fsm_a[0]\nset_location_assignment PIN_AH30 -to fsm_a[1]\nset_location_assignment PIN_AJ30 -to fsm_a[2]\nset_location_assignment PIN_AH31 -to fsm_a[3]\nset_location_assignment PIN_AK30 -to fsm_a[4]\nset_location_assignment PIN_AJ32 -to fsm_a[5]\nset_location_assignment PIN_AG33 -to fsm_a[6]\nset_location_assignment PIN_AL30 -to fsm_a[7]\nset_location_assignment PIN_AK33 -to fsm_a[8]\nset_location_assignment PIN_AJ33 -to fsm_a[9]\nset_location_assignment PIN_AN30 -to fsm_a[10]\nset_location_assignment PIN_AH33 -to fsm_a[11]\nset_location_assignment PIN_AK32 -to fsm_a[12]\nset_location_assignment PIN_AM32 -to fsm_a[13]\nset_location_assignment PIN_AM31 -to fsm_a[14]\nset_location_assignment PIN_AL31 -to fsm_a[15]\nset_location_assignment PIN_AN33 -to fsm_a[16]\nset_location_assignment PIN_AP33 -to fsm_a[17]\nset_location_assignment PIN_AT32 -to fsm_a[18]\nset_location_assignment PIN_AT29 -to fsm_a[19]\nset_location_assignment PIN_AP31 -to fsm_a[20]\nset_location_assignment PIN_AR30 -to fsm_a[21]\nset_location_assignment PIN_AU30 -to fsm_a[22]\nset_location_assignment PIN_AJ31 -to fsm_a[23]\nset_location_assignment PIN_AP30 -to fsm_a[24]\nset_location_assignment PIN_AN31 -to fsm_a[25]\nset_location_assignment PIN_AT30 -to fsm_a[26]\nset_location_assignment PIN_AG26 -to fsm_d[0]\nset_location_assignment PIN_AD33 -to fsm_d[1]\nset_location_assignment PIN_AE34 -to fsm_d[2]\nset_location_assignment PIN_AF31 -to fsm_d[3]\nset_location_assignment PIN_AG28 -to fsm_d[4]\nset_location_assignment PIN_AG30 -to fsm_d[5]\nset_location_assignment PIN_AF29 -to fsm_d[6]\nset_location_assignment PIN_AE29 -to fsm_d[7]\nset_location_assignment PIN_AG25 -to fsm_d[8]\nset_location_assignment PIN_AF34 -to fsm_d[9]\nset_location_assignment PIN_AE33 -to fsm_d[10]\nset_location_assignment PIN_AE31 -to fsm_d[11]\nset_location_assignment PIN_AF28 -to fsm_d[12]\nset_location_assignment PIN_AE30 -to fsm_d[13]\nset_location_assignment PIN_AG29 -to fsm_d[14]\nset_location_assignment PIN_AG27 -to fsm_d[15]\nset_location_assignment PIN_AP28 -to fsm_d[16]\nset_location_assignment PIN_AN28 -to fsm_d[17]\nset_location_assignment PIN_AU31 -to fsm_d[18]\nset_location_assignment PIN_AW32 -to fsm_d[19]\nset_location_assignment PIN_BD32 -to fsm_d[20]\nset_location_assignment PIN_AY31 -to fsm_d[21]\nset_location_assignment PIN_BA30 -to fsm_d[22]\nset_location_assignment PIN_BB30 -to fsm_d[23]\nset_location_assignment PIN_AM29 -to fsm_d[24]\nset_location_assignment PIN_AR29 -to fsm_d[25]\nset_location_assignment PIN_AV31 -to fsm_d[26]\nset_location_assignment PIN_AV32 -to fsm_d[27]\nset_location_assignment PIN_BC31 -to fsm_d[28]\nset_location_assignment PIN_AW30 -to fsm_d[29]\nset_location_assignment PIN_BC32 -to fsm_d[30]\nset_location_assignment PIN_BD31 -to fsm_d[31]\nset_location_assignment PIN_G8 -to hex0_d[0]\nset_location_assignment PIN_H8 -to hex0_d[1]\nset_location_assignment PIN_J9 -to hex0_d[2]\nset_location_assignment PIN_K10 -to hex0_d[3]\nset_location_assignment PIN_K8 -to hex0_d[4]\nset_location_assignment PIN_K9 -to hex0_d[5]\nset_location_assignment PIN_N8 -to hex0_d[6]\nset_location_assignment PIN_P8 -to hex0_dp\nset_location_assignment PIN_H18 -to hex1_d[0]\nset_location_assignment PIN_G16 -to hex1_d[1]\nset_location_assignment PIN_F16 -to hex1_d[2]\nset_location_assignment PIN_A7 -to hex1_d[3]\nset_location_assignment PIN_B7 -to hex1_d[4]\nset_location_assignment PIN_C9 -to hex1_d[5]\nset_location_assignment PIN_D10 -to hex1_d[6]\nset_location_assignment PIN_E9 -to hex1_dp\nset_location_assignment PIN_AW37 -to leds[0]\nset_location_assignment PIN_AV37 -to leds[1]\nset_location_assignment PIN_BB36 -to leds[2]\nset_location_assignment PIN_BB39 -to leds[3]\nset_location_assignment PIN_AH15 -to led_bracket[0]\nset_location_assignment PIN_AH13 -to led_bracket[1]\nset_location_assignment PIN_AJ13 -to led_bracket[2]\nset_location_assignment PIN_AJ14 -to led_bracket[3]\nset_location_assignment PIN_AG15 -to led_rj45_l\nset_location_assignment PIN_AG16 -to led_rj45_r\nset_location_assignment PIN_AW35 -to osc_50_b3b\nset_location_assignment PIN_BC28 -to osc_50_b3d\nset_location_assignment PIN_AP10 -to osc_50_b4a\nset_location_assignment PIN_AY18 -to osc_50_b4d\nset_location_assignment PIN_M8 -to osc_50_b7a\nset_location_assignment PIN_J18 -to osc_50_b7d\nset_location_assignment PIN_R36 -to osc_50_b8a\nset_location_assignment PIN_R25 -to osc_50_b8d\nset_location_assignment PIN_AU33 -to pcie_perst_n\nset_location_assignment PIN_AK38 -to pcie_refclk_p\nset_location_assignment PIN_BB43 -to PCIE_rx_p[0]\nset_location_assignment PIN_BA41 -to PCIE_rx_p[1]\nset_location_assignment PIN_AW41 -to PCIE_rx_p[2]\nset_location_assignment PIN_AY43 -to PCIE_rx_p[3]\nset_location_assignment PIN_AT43 -to PCIE_rx_p[4]\nset_location_assignment PIN_AP43 -to PCIE_rx_p[5]\nset_location_assignment PIN_AM43 -to PCIE_rx_p[6]\nset_location_assignment PIN_AK43 -to PCIE_rx_p[7]\nset_location_assignment PIN_BD34 -to pcie_smbclk\nset_location_assignment PIN_AT33 -to pcie_smbdat\nset_location_assignment PIN_AY39 -to PCIE_tx_p[0]\nset_location_assignment PIN_AV39 -to PCIE_tx_p[1]\nset_location_assignment PIN_AT39 -to PCIE_tx_p[2]\nset_location_assignment PIN_AU41 -to PCIE_tx_p[3]\nset_location_assignment PIN_AN41 -to PCIE_tx_p[4]\nset_location_assignment PIN_AL41 -to PCIE_tx_p[5]\nset_location_assignment PIN_AJ41 -to PCIE_tx_p[6]\nset_location_assignment PIN_AG41 -to PCIE_tx_p[7]\nset_location_assignment PIN_BD35 -to pcie_wake_n\nset_location_assignment PIN_AU29 -to qdriia_a[0]\nset_location_assignment PIN_BA28 -to qdriia_a[1]\nset_location_assignment PIN_AP27 -to qdriia_a[2]\nset_location_assignment PIN_AK27 -to qdriia_a[3]\nset_location_assignment PIN_AN27 -to qdriia_a[4]\nset_location_assignment PIN_AM28 -to qdriia_a[5]\nset_location_assignment PIN_AV28 -to qdriia_a[6]\nset_location_assignment PIN_AY27 -to qdriia_a[7]\nset_location_assignment PIN_BC29 -to qdriia_a[8]\nset_location_assignment PIN_AU28 -to qdriia_a[9]\nset_location_assignment PIN_AW27 -to qdriia_a[10]\nset_location_assignment PIN_AY28 -to qdriia_a[11]\nset_location_assignment PIN_BD28 -to qdriia_a[12]\nset_location_assignment PIN_AV29 -to qdriia_a[13]\nset_location_assignment PIN_AW29 -to qdriia_a[14]\nset_location_assignment PIN_BB29 -to qdriia_a[15]\nset_location_assignment PIN_BD29 -to qdriia_a[16]\nset_location_assignment PIN_AL27 -to qdriia_a[17]\nset_location_assignment PIN_AR27 -to qdriia_a[18]\nset_location_assignment PIN_AL28 -to qdriia_a[19]\nset_location_assignment PIN_AR28 -to qdriia_a[20]\nset_location_assignment PIN_AJ24 -to qdriia_bws_n[0]\nset_location_assignment PIN_AT27 -to qdriia_bws_n[1]\nset_location_assignment PIN_BA25 -to qdriia_cq_n\nset_location_assignment PIN_AH22 -to qdriia_cq_p\nset_location_assignment PIN_AH28 -to qdriia_d[0]\nset_location_assignment PIN_AH27 -to qdriia_d[1]\nset_location_assignment PIN_AH25 -to qdriia_d[2]\nset_location_assignment PIN_AJ28 -to qdriia_d[3]\nset_location_assignment PIN_AJ27 -to qdriia_d[4]\nset_location_assignment PIN_AJ26 -to qdriia_d[5]\nset_location_assignment PIN_AJ25 -to qdriia_d[6]\nset_location_assignment PIN_AL25 -to qdriia_d[7]\nset_location_assignment PIN_AH24 -to qdriia_d[8]\nset_location_assignment PIN_AN25 -to qdriia_d[9]\nset_location_assignment PIN_AM26 -to qdriia_d[10]\nset_location_assignment PIN_AM25 -to qdriia_d[11]\nset_location_assignment PIN_AL26 -to qdriia_d[12]\nset_location_assignment PIN_AK26 -to qdriia_d[13]\nset_location_assignment PIN_AU27 -to qdriia_d[14]\nset_location_assignment PIN_AU26 -to qdriia_d[15]\nset_location_assignment PIN_AV26 -to qdriia_d[16]\nset_location_assignment PIN_AW26 -to qdriia_d[17]\nset_location_assignment PIN_AR23 -to qdriia_doff_n\nset_location_assignment PIN_AR26 -to qdriia_k_n\nset_location_assignment PIN_AP25 -to qdriia_k_p\nset_location_assignment PIN_AN23 -to qdriia_odt\nset_location_assignment PIN_AK23 -to qdriia_q[0]\nset_location_assignment PIN_BB26 -to qdriia_q[1]\nset_location_assignment PIN_BD26 -to qdriia_q[2]\nset_location_assignment PIN_BA24 -to qdriia_q[3]\nset_location_assignment PIN_AL23 -to qdriia_q[4]\nset_location_assignment PIN_AJ23 -to qdriia_q[5]\nset_location_assignment PIN_AL21 -to qdriia_q[6]\nset_location_assignment PIN_AK21 -to qdriia_q[7]\nset_location_assignment PIN_AJ22 -to qdriia_q[8]\nset_location_assignment PIN_AW24 -to qdriia_q[9]\nset_location_assignment PIN_BC26 -to qdriia_q[10]\nset_location_assignment PIN_AY25 -to qdriia_q[11]\nset_location_assignment PIN_AU24 -to qdriia_q[12]\nset_location_assignment PIN_AV25 -to qdriia_q[13]\nset_location_assignment PIN_AU25 -to qdriia_q[14]\nset_location_assignment PIN_AR25 -to qdriia_q[15]\nset_location_assignment PIN_AP24 -to qdriia_q[16]\nset_location_assignment PIN_AL24 -to qdriia_q[17]\nset_location_assignment PIN_AM23 -to qdriia_qvld\nset_location_assignment PIN_AT26 -to qdriia_rps_n\nset_location_assignment PIN_AK24 -to qdriia_wps_n\nset_location_assignment PIN_AR24 -to qdriib_a[0]\nset_location_assignment PIN_BB23 -to qdriib_a[1]\nset_location_assignment PIN_AK20 -to qdriib_a[2]\nset_location_assignment PIN_AJ19 -to qdriib_a[3]\nset_location_assignment PIN_AL20 -to qdriib_a[4]\nset_location_assignment PIN_AG19 -to qdriib_a[5]\nset_location_assignment PIN_AT23 -to qdriib_a[6]\nset_location_assignment PIN_AU23 -to qdriib_a[7]\nset_location_assignment PIN_AV23 -to qdriib_a[8]\nset_location_assignment PIN_AM22 -to qdriib_a[9]\nset_location_assignment PIN_AJ20 -to qdriib_a[10]\nset_location_assignment PIN_AG20 -to qdriib_a[11]\nset_location_assignment PIN_AW23 -to qdriib_a[12]\nset_location_assignment PIN_BB24 -to qdriib_a[13]\nset_location_assignment PIN_AY24 -to qdriib_a[14]\nset_location_assignment PIN_BD23 -to qdriib_a[15]\nset_location_assignment PIN_BC23 -to qdriib_a[16]\nset_location_assignment PIN_AG21 -to qdriib_a[17]\nset_location_assignment PIN_AM20 -to qdriib_a[18]\nset_location_assignment PIN_AK18 -to qdriib_a[19]\nset_location_assignment PIN_AN22 -to qdriib_a[20]\nset_location_assignment PIN_AV20 -to qdriib_bws_n[0]\nset_location_assignment PIN_AU21 -to qdriib_bws_n[1]\nset_location_assignment PIN_AP18 -to qdriib_cq_n\nset_location_assignment PIN_AJ15 -to qdriib_cq_p\nset_location_assignment PIN_BB21 -to qdriib_d[0]\nset_location_assignment PIN_BD20 -to qdriib_d[1]\nset_location_assignment PIN_BC20 -to qdriib_d[2]\nset_location_assignment PIN_AR22 -to qdriib_d[3]\nset_location_assignment PIN_BB20 -to qdriib_d[4]\nset_location_assignment PIN_AU22 -to qdriib_d[5]\nset_location_assignment PIN_BA21 -to qdriib_d[6]\nset_location_assignment PIN_AY21 -to qdriib_d[7]\nset_location_assignment PIN_AW21 -to qdriib_d[8]\nset_location_assignment PIN_AT21 -to qdriib_d[9]\nset_location_assignment PIN_AR21 -to qdriib_d[10]\nset_location_assignment PIN_AP21 -to qdriib_d[11]\nset_location_assignment PIN_BD22 -to qdriib_d[12]\nset_location_assignment PIN_BC22 -to qdriib_d[13]\nset_location_assignment PIN_BA22 -to qdriib_d[14]\nset_location_assignment PIN_AV22 -to qdriib_d[15]\nset_location_assignment PIN_AY22 -to qdriib_d[16]\nset_location_assignment PIN_AW22 -to qdriib_d[17]\nset_location_assignment PIN_AH19 -to qdriib_doff_n\nset_location_assignment PIN_AT20 -to qdriib_k_n\nset_location_assignment PIN_AR20 -to qdriib_k_p\nset_location_assignment PIN_AH18 -to qdriib_odt\nset_location_assignment PIN_AR19 -to qdriib_q[0]\nset_location_assignment PIN_AM19 -to qdriib_q[1]\nset_location_assignment PIN_AL19 -to qdriib_q[2]\nset_location_assignment PIN_AM17 -to qdriib_q[3]\nset_location_assignment PIN_AL18 -to qdriib_q[4]\nset_location_assignment PIN_AN19 -to qdriib_q[5]\nset_location_assignment PIN_AU18 -to qdriib_q[6]\nset_location_assignment PIN_AK17 -to qdriib_q[7]\nset_location_assignment PIN_AL17 -to qdriib_q[8]\nset_location_assignment PIN_AG17 -to qdriib_q[9]\nset_location_assignment PIN_AJ18 -to qdriib_q[10]\nset_location_assignment PIN_AJ17 -to qdriib_q[11]\nset_location_assignment PIN_AG18 -to qdriib_q[12]\nset_location_assignment PIN_AU19 -to qdriib_q[13]\nset_location_assignment PIN_AW19 -to qdriib_q[14]\nset_location_assignment PIN_AV19 -to qdriib_q[15]\nset_location_assignment PIN_AP19 -to qdriib_q[16]\nset_location_assignment PIN_AN20 -to qdriib_q[17]\nset_location_assignment PIN_AJ16 -to qdriib_qvld\nset_location_assignment PIN_AW20 -to qdriib_rps_n\nset_location_assignment PIN_AU20 -to qdriib_wps_n\nset_location_assignment PIN_AV16 -to qdriic_a[0]\nset_location_assignment PIN_AW16 -to qdriic_a[1]\nset_location_assignment PIN_AP16 -to qdriic_a[2]\nset_location_assignment PIN_AW9 -to qdriic_a[3]\nset_location_assignment PIN_BD7 -to qdriic_a[4]\nset_location_assignment PIN_BC7 -to qdriic_a[5]\nset_location_assignment PIN_AR17 -to qdriic_a[6]\nset_location_assignment PIN_AR18 -to qdriic_a[7]\nset_location_assignment PIN_AT17 -to qdriic_a[8]\nset_location_assignment PIN_BB9 -to qdriic_a[9]\nset_location_assignment PIN_AH21 -to qdriic_a[10]\nset_location_assignment PIN_AU17 -to qdriic_a[11]\nset_location_assignment PIN_AU16 -to qdriic_a[12]\nset_location_assignment PIN_BB8 -to qdriic_a[13]\nset_location_assignment PIN_AT18 -to qdriic_a[14]\nset_location_assignment PIN_AW17 -to qdriic_a[15]\nset_location_assignment PIN_AV17 -to qdriic_a[16]\nset_location_assignment PIN_AU8 -to qdriic_a[17]\nset_location_assignment PIN_AT9 -to qdriic_a[18]\nset_location_assignment PIN_AV8 -to qdriic_a[19]\nset_location_assignment PIN_AN17 -to qdriic_a[20]\nset_location_assignment PIN_AJ11 -to qdriic_bws_n[0]\nset_location_assignment PIN_AJ10 -to qdriic_bws_n[1]\nset_location_assignment PIN_AF13 -to qdriic_cq_n\nset_location_assignment PIN_BC11 -to qdriic_cq_p\nset_location_assignment PIN_AG9 -to qdriic_d[0]\nset_location_assignment PIN_AG10 -to qdriic_d[1]\nset_location_assignment PIN_AG12 -to qdriic_d[2]\nset_location_assignment PIN_AG11 -to qdriic_d[3]\nset_location_assignment PIN_AV10 -to qdriic_d[4]\nset_location_assignment PIN_AH12 -to qdriic_d[5]\nset_location_assignment PIN_AK12 -to qdriic_d[6]\nset_location_assignment PIN_AL12 -to qdriic_d[7]\nset_location_assignment PIN_AJ12 -to qdriic_d[8]\nset_location_assignment PIN_AN12 -to qdriic_d[9]\nset_location_assignment PIN_AM13 -to qdriic_d[10]\nset_location_assignment PIN_AR12 -to qdriic_d[11]\nset_location_assignment PIN_AR13 -to qdriic_d[12]\nset_location_assignment PIN_AU9 -to qdriic_d[13]\nset_location_assignment PIN_AU10 -to qdriic_d[14]\nset_location_assignment PIN_AU11 -to qdriic_d[15]\nset_location_assignment PIN_AV11 -to qdriic_d[16]\nset_location_assignment PIN_AT12 -to qdriic_d[17]\nset_location_assignment PIN_AE14 -to qdriic_doff_n\nset_location_assignment PIN_AP13 -to qdriic_k_n\nset_location_assignment PIN_AP12 -to qdriic_k_p\nset_location_assignment PIN_BD10 -to qdriic_odt\nset_location_assignment PIN_BA12 -to qdriic_q[0]\nset_location_assignment PIN_AF14 -to qdriic_q[1]\nset_location_assignment PIN_AE13 -to qdriic_q[2]\nset_location_assignment PIN_AD14 -to qdriic_q[3]\nset_location_assignment PIN_AE12 -to qdriic_q[4]\nset_location_assignment PIN_AF11 -to qdriic_q[5]\nset_location_assignment PIN_AE11 -to qdriic_q[6]\nset_location_assignment PIN_AE10 -to qdriic_q[7]\nset_location_assignment PIN_AE9 -to qdriic_q[8]\nset_location_assignment PIN_BB11 -to qdriic_q[9]\nset_location_assignment PIN_AW11 -to qdriic_q[10]\nset_location_assignment PIN_AF10 -to qdriic_q[11]\nset_location_assignment PIN_AY12 -to qdriic_q[12]\nset_location_assignment PIN_AW10 -to qdriic_q[13]\nset_location_assignment PIN_AY10 -to qdriic_q[14]\nset_location_assignment PIN_BB12 -to qdriic_q[15]\nset_location_assignment PIN_BC10 -to qdriic_q[16]\nset_location_assignment PIN_BA10 -to qdriic_q[17]\nset_location_assignment PIN_BD11 -to qdriic_qvld\nset_location_assignment PIN_AH10 -to qdriic_rps_n\nset_location_assignment PIN_AL11 -to qdriic_wps_n\nset_location_assignment PIN_N26 -to qdriid_a[0]\nset_location_assignment PIN_P28 -to qdriid_a[1]\nset_location_assignment PIN_N28 -to qdriid_a[2]\nset_location_assignment PIN_L26 -to qdriid_a[3]\nset_location_assignment PIN_K27 -to qdriid_a[4]\nset_location_assignment PIN_L27 -to qdriid_a[5]\nset_location_assignment PIN_U26 -to qdriid_a[6]\nset_location_assignment PIN_T26 -to qdriid_a[7]\nset_location_assignment PIN_T27 -to qdriid_a[8]\nset_location_assignment PIN_V27 -to qdriid_a[9]\nset_location_assignment PIN_U27 -to qdriid_a[10]\nset_location_assignment PIN_R27 -to qdriid_a[11]\nset_location_assignment PIN_P27 -to qdriid_a[12]\nset_location_assignment PIN_V25 -to qdriid_a[13]\nset_location_assignment PIN_V26 -to qdriid_a[14]\nset_location_assignment PIN_T25 -to qdriid_a[15]\nset_location_assignment PIN_P26 -to qdriid_a[16]\nset_location_assignment PIN_M27 -to qdriid_a[17]\nset_location_assignment PIN_M28 -to qdriid_a[18]\nset_location_assignment PIN_P29 -to qdriid_a[19]\nset_location_assignment PIN_D29 -to qdriid_a[20]\nset_location_assignment PIN_E26 -to qdriid_bws_n[0]\nset_location_assignment PIN_K26 -to qdriid_bws_n[1]\nset_location_assignment PIN_H27 -to qdriid_cq_n\nset_location_assignment PIN_E29 -to qdriid_cq_p\nset_location_assignment PIN_H25 -to qdriid_d[0]\nset_location_assignment PIN_H24 -to qdriid_d[1]\nset_location_assignment PIN_H23 -to qdriid_d[2]\nset_location_assignment PIN_J25 -to qdriid_d[3]\nset_location_assignment PIN_J24 -to qdriid_d[4]\nset_location_assignment PIN_K25 -to qdriid_d[5]\nset_location_assignment PIN_D26 -to qdriid_d[6]\nset_location_assignment PIN_F25 -to qdriid_d[7]\nset_location_assignment PIN_G25 -to qdriid_d[8]\nset_location_assignment PIN_N23 -to qdriid_d[9]\nset_location_assignment PIN_P24 -to qdriid_d[10]\nset_location_assignment PIN_P23 -to qdriid_d[11]\nset_location_assignment PIN_L24 -to qdriid_d[12]\nset_location_assignment PIN_R24 -to qdriid_d[13]\nset_location_assignment PIN_U23 -to qdriid_d[14]\nset_location_assignment PIN_U24 -to qdriid_d[15]\nset_location_assignment PIN_T24 -to qdriid_d[16]\nset_location_assignment PIN_T23 -to qdriid_d[17]\nset_location_assignment PIN_E27 -to qdriid_doff_n\nset_location_assignment PIN_K24 -to qdriid_k_n\nset_location_assignment PIN_L23 -to qdriid_k_p\nset_location_assignment PIN_H26 -to qdriid_odt\nset_location_assignment PIN_C27 -to qdriid_q[0]\nset_location_assignment PIN_A26 -to qdriid_q[1]\nset_location_assignment PIN_B26 -to qdriid_q[2]\nset_location_assignment PIN_F26 -to qdriid_q[3]\nset_location_assignment PIN_G26 -to qdriid_q[4]\nset_location_assignment PIN_C28 -to qdriid_q[5]\nset_location_assignment PIN_A29 -to qdriid_q[6]\nset_location_assignment PIN_A28 -to qdriid_q[7]\nset_location_assignment PIN_B28 -to qdriid_q[8]\nset_location_assignment PIN_G28 -to qdriid_q[9]\nset_location_assignment PIN_F28 -to qdriid_q[10]\nset_location_assignment PIN_D27 -to qdriid_q[11]\nset_location_assignment PIN_G29 -to qdriid_q[12]\nset_location_assignment PIN_F29 -to qdriid_q[13]\nset_location_assignment PIN_H28 -to qdriid_q[14]\nset_location_assignment PIN_K28 -to qdriid_q[15]\nset_location_assignment PIN_J28 -to qdriid_q[16]\nset_location_assignment PIN_H29 -to qdriid_q[17]\nset_location_assignment PIN_J27 -to qdriid_qvld\nset_location_assignment PIN_F24 -to qdriid_rps_n\nset_location_assignment PIN_M23 -to qdriid_wps_n\nset_location_assignment PIN_AG14 -to rs422_de\nset_location_assignment PIN_AE18 -to rs422_din\nset_location_assignment PIN_AE17 -to rs422_dout\nset_location_assignment PIN_AF17 -to rs422_re_n\nset_location_assignment PIN_AF16 -to rs422_te\nset_location_assignment PIN_BA36 -to rzq_0\nset_location_assignment PIN_AR8 -to rzq_1\nset_location_assignment PIN_H9 -to rzq_4\nset_location_assignment PIN_P35 -to rzq_5\nset_location_assignment PIN_AH6 -to sfp1g_refclk_p\nset_location_assignment PIN_F22 -to sfpa_los\nset_location_assignment PIN_E21 -to sfpa_mod0_prsnt_n\nset_location_assignment PIN_B20 -to sfpa_mod1_scl\nset_location_assignment PIN_A20 -to sfpa_mod2_sda\nset_location_assignment PIN_E20 -to sfpa_ratesel[0]\nset_location_assignment PIN_G22 -to sfpa_ratesel[1]\nset_location_assignment PIN_AK2 -to sfpa_rx_p\nset_location_assignment PIN_B22 -to sfpa_txdisable\nset_location_assignment PIN_A22 -to sfpa_txfault\nset_location_assignment PIN_AG4 -to sfpa_tx_p\nset_location_assignment PIN_R22 -to sfpb_los\nset_location_assignment PIN_K22 -to sfpb_mod0_prsnt_n\nset_location_assignment PIN_K21 -to sfpb_mod1_scl\nset_location_assignment PIN_K20 -to sfpb_mod2_sda\nset_location_assignment PIN_R21 -to sfpb_ratesel[0]\nset_location_assignment PIN_T22 -to sfpb_ratesel[1]\nset_location_assignment PIN_AP2 -to sfpb_rx_p\nset_location_assignment PIN_H22 -to sfpb_txdisable\nset_location_assignment PIN_H20 -to sfpb_txfault\nset_location_assignment PIN_AL4 -to sfpb_tx_p\nset_location_assignment PIN_L21 -to sfpc_los\nset_location_assignment PIN_J21 -to sfpc_mod0_prsnt_n\nset_location_assignment PIN_H21 -to sfpc_mod1_scl\nset_location_assignment PIN_G20 -to sfpc_mod2_sda\nset_location_assignment PIN_J22 -to sfpc_ratesel[0]\nset_location_assignment PIN_P21 -to sfpc_ratesel[1]\nset_location_assignment PIN_AW4 -to sfpc_rx_p\nset_location_assignment PIN_F21 -to sfpc_txdisable\nset_location_assignment PIN_F20 -to sfpc_txfault\nset_location_assignment PIN_AT6 -to sfpc_tx_p\nset_location_assignment PIN_N22 -to sfpd_los\nset_location_assignment PIN_V20 -to sfpd_mod0_prsnt_n\nset_location_assignment PIN_U21 -to sfpd_mod1_scl\nset_location_assignment PIN_V19 -to sfpd_mod2_sda\nset_location_assignment PIN_V21 -to sfpd_ratesel[0]\nset_location_assignment PIN_M22 -to sfpd_ratesel[1]\nset_location_assignment PIN_BB2 -to sfpd_rx_p\nset_location_assignment PIN_U20 -to sfpd_txdisable\nset_location_assignment PIN_T21 -to SFPD_TXFAULT\nset_location_assignment PIN_AY6 -to SFPD_TX_p\nset_location_assignment PIN_BB33 -to sma_clkin\nset_location_assignment PIN_B25 -to sw[0]\nset_location_assignment PIN_A25 -to sw[1]\nset_location_assignment PIN_B23 -to sw[2]\nset_location_assignment PIN_A23 -to sw[3]\nset_location_assignment PIN_D21 -to temp_clk\nset_location_assignment PIN_D20 -to temp_data\nset_location_assignment PIN_C21 -to temp_int_n\nset_location_assignment PIN_C22 -to temp_overt_n\nset_location_assignment PIN_AV34 -to sma_clkout\nset_location_assignment PIN_V39 -to sata_device_refclk_p\nset_location_assignment PIN_V6 -to sata_host_refclk_p\nset_location_assignment PIN_V5 -to \"sata_host_refclk_p(n)\"\nset_location_assignment PIN_V40 -to \"sata_device_refclk_p(n)\"\nset_location_assignment PIN_K43 -to sata_device_rx_p[0]\nset_location_assignment PIN_H43 -to sata_device_rx_p[1]\nset_location_assignment PIN_K39 -to sata_device_tx_p[0]\nset_location_assignment PIN_H39 -to sata_device_tx_p[1]\nset_location_assignment PIN_K44 -to \"sata_device_rx_p[0](n)\"\nset_location_assignment PIN_H44 -to \"sata_device_rx_p[1](n)\"\nset_location_assignment PIN_K40 -to \"sata_device_tx_p[0](n)\"\nset_location_assignment PIN_H40 -to \"sata_device_tx_p[1](n)\"\nset_location_assignment PIN_K2 -to sata_host_rx_p[0]\nset_location_assignment PIN_K1 -to \"sata_host_rx_p[0](n)\"\nset_location_assignment PIN_H2 -to sata_host_rx_p[1]\nset_location_assignment PIN_H1 -to \"sata_host_rx_p[1](n)\"\nset_location_assignment PIN_K6 -to sata_host_tx_p[0]\nset_location_assignment PIN_K5 -to \"sata_host_tx_p[0](n)\"\nset_location_assignment PIN_H6 -to sata_host_tx_p[1]\nset_location_assignment PIN_H5 -to \"sata_host_tx_p[1](n)\"\nset_location_assignment PIN_AK7 -to sfp_refclk_p\n\n#============================================================\n\n\n\nset_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top\nset_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top\nset_global_assignment -name PARTITION_COLOR 16764057 -section_id Top\nset_global_assignment -name STRATIX_DEVICE_IO_STANDARD \"2.5 V\"\nset_global_assignment -name MIN_CORE_JUNCTION_TEMP 0\nset_global_assignment -name MAX_CORE_JUNCTION_TEMP 85\nset_global_assignment -name POWER_PRESET_COOLING_SOLUTION \"23 MM HEAT SINK WITH 200 LFPM AIRFLOW\"\nset_global_assignment -name POWER_BOARD_THERMAL_MODEL \"NONE (CONSERVATIVE)\"\n\nset_location_assignment PIN_PIN -to NETName\nset_location_assignment PIN_AK39 -to \"pcie_refclk_p(n)\"\nset_instance_assignment -name IO_STANDARD HCSL -to \"pcie_refclk_p(n)\"\nset_location_assignment PIN_BB44 -to \"PCIE_rx_p[0](n)\"\nset_instance_assignment -name IO_STANDARD \"1.4-V PCML\" -to \"PCIE_rx_p[0](n)\"\nset_location_assignment PIN_BA42 -to \"PCIE_rx_p[1](n)\"\nset_instance_assignment -name IO_STANDARD \"1.4-V PCML\" -to \"PCIE_rx_p[1](n)\"\nset_location_assignment PIN_AW42 -to \"PCIE_rx_p[2](n)\"\nset_instance_assignment -name IO_STANDARD \"1.4-V PCML\" -to \"PCIE_rx_p[2](n)\"\nset_location_assignment PIN_AY44 -to \"PCIE_rx_p[3](n)\"\nset_instance_assignment -name IO_STANDARD \"1.4-V PCML\" -to \"PCIE_rx_p[3](n)\"\nset_location_assignment PIN_AT44 -to \"PCIE_rx_p[4](n)\"\nset_instance_assignment -name IO_STANDARD \"1.4-V PCML\" -to \"PCIE_rx_p[4](n)\"\nset_location_assignment PIN_AP44 -to \"PCIE_rx_p[5](n)\"\nset_instance_assignment -name IO_STANDARD \"1.4-V PCML\" -to \"PCIE_rx_p[5](n)\"\nset_location_assignment PIN_AM44 -to \"PCIE_rx_p[6](n)\"\nset_instance_assignment -name IO_STANDARD \"1.4-V PCML\" -to \"PCIE_rx_p[6](n)\"\nset_location_assignment PIN_AK44 -to \"PCIE_rx_p[7](n)\"\nset_instance_assignment -name IO_STANDARD \"1.4-V PCML\" -to \"PCIE_rx_p[7](n)\"\nset_location_assignment PIN_AY40 -to \"PCIE_tx_p[0](n)\"\nset_instance_assignment -name IO_STANDARD \"1.4-V PCML\" -to \"PCIE_tx_p[0](n)\"\nset_location_assignment PIN_AV40 -to \"PCIE_tx_p[1](n)\"\nset_instance_assignment -name IO_STANDARD \"1.4-V PCML\" -to \"PCIE_tx_p[1](n)\"\nset_location_assignment PIN_AT40 -to \"PCIE_tx_p[2](n)\"\nset_instance_assignment -name IO_STANDARD \"1.4-V PCML\" -to \"PCIE_tx_p[2](n)\"\nset_location_assignment PIN_AU42 -to \"PCIE_tx_p[3](n)\"\nset_instance_assignment -name IO_STANDARD \"1.4-V PCML\" -to \"PCIE_tx_p[3](n)\"\nset_location_assignment PIN_AN42 -to \"PCIE_tx_p[4](n)\"\nset_instance_assignment -name IO_STANDARD \"1.4-V PCML\" -to \"PCIE_tx_p[4](n)\"\nset_location_assignment PIN_AL42 -to \"PCIE_tx_p[5](n)\"\nset_instance_assignment -name IO_STANDARD \"1.4-V PCML\" -to \"PCIE_tx_p[5](n)\"\nset_location_assignment PIN_AJ42 -to \"PCIE_tx_p[6](n)\"\nset_instance_assignment -name IO_STANDARD \"1.4-V PCML\" -to \"PCIE_tx_p[6](n)\"\nset_location_assignment PIN_AG42 -to \"PCIE_tx_p[7](n)\"\nset_instance_assignment -name IO_STANDARD \"1.4-V PCML\" -to \"PCIE_tx_p[7](n)\"\nset_instance_assignment -name IO_STANDARD HCSL -to \"sata_device_refclk_p(n)\"\nset_instance_assignment -name IO_STANDARD \"1.4-V PCML\" -to \"sata_device_rx_p[0](n)\"\nset_instance_assignment -name IO_STANDARD \"1.4-V PCML\" -to \"sata_device_rx_p[1](n)\"\nset_instance_assignment -name IO_STANDARD \"1.4-V PCML\" -to \"sata_device_tx_p[0](n)\"\nset_instance_assignment -name IO_STANDARD \"1.4-V PCML\" -to \"sata_device_tx_p[1](n)\"\nset_instance_assignment -name IO_STANDARD HCSL -to \"sata_host_refclk_p(n)\"\nset_instance_assignment -name IO_STANDARD \"1.4-V PCML\" -to \"sata_host_rx_p[0](n)\"\nset_instance_assignment -name IO_STANDARD \"1.4-V PCML\" -to \"sata_host_rx_p[1](n)\"\nset_instance_assignment -name IO_STANDARD \"1.4-V PCML\" -to \"sata_host_tx_p[0](n)\"\nset_instance_assignment -name IO_STANDARD \"1.4-V PCML\" -to \"sata_host_tx_p[1](n)\"\nset_location_assignment PIN_AH5 -to \"sfp1g_refclk_p(n)\"\nset_instance_assignment -name IO_STANDARD HCSL -to \"sfp1g_refclk_p(n)\"\nset_location_assignment PIN_AK1 -to \"sfpa_rx_p(n)\"\nset_instance_assignment -name IO_STANDARD \"1.4-V PCML\" -to \"sfpa_rx_p(n)\"\nset_location_assignment PIN_AG3 -to \"sfpa_tx_p(n)\"\nset_instance_assignment -name IO_STANDARD \"1.4-V PCML\" -to \"sfpa_tx_p(n)\"\nset_location_assignment PIN_AP1 -to \"sfpb_rx_p(n)\"\nset_instance_assignment -name IO_STANDARD \"1.4-V PCML\" -to \"sfpb_rx_p(n)\"\nset_location_assignment PIN_AL3 -to \"sfpb_tx_p(n)\"\nset_instance_assignment -name IO_STANDARD \"1.4-V PCML\" -to \"sfpb_tx_p(n)\"\nset_location_assignment PIN_AW3 -to \"sfpc_rx_p(n)\"\nset_instance_assignment -name IO_STANDARD \"1.4-V PCML\" -to \"sfpc_rx_p(n)\"\nset_location_assignment PIN_AT5 -to \"sfpc_tx_p(n)\"\nset_instance_assignment -name IO_STANDARD \"1.4-V PCML\" -to \"sfpc_tx_p(n)\"\nset_location_assignment PIN_BB1 -to \"sfpd_rx_p(n)\"\nset_instance_assignment -name IO_STANDARD \"1.4-V PCML\" -to \"sfpd_rx_p(n)\"\nset_location_assignment PIN_AY5 -to \"sfpd_tx_p(n)\"\nset_instance_assignment -name IO_STANDARD \"1.4-V PCML\" -to \"sfpd_tx_p(n)\"\nset_location_assignment PIN_AK7 -to sfp_refclk_p\nset_instance_assignment -name IO_STANDARD HCSL -to sfp_refclk_p\nset_location_assignment PIN_AK6 -to \"sfp_refclk_p(n)\"\nset_instance_assignment -name IO_STANDARD HCSL -to \"sfp_refclk_p(n)\"\nset_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top\n"
  },
  {
    "path": "constraints/altera/de5.sdc",
    "content": "\r\n#**************************************************************\r\n# Create Clock\r\n#**************************************************************\r\n\r\ncreate_clock -period 10 [get_ports pcie_refclk_p]\r\ncreate_clock -period 1.552 [get_ports sfp_refclk]\r\ncreate_clock -period 20 [get_ports osc_50_b3b]\r\ncreate_clock -period 20 [get_ports osc_50_b3d]\r\ncreate_clock -period 20 [get_ports osc_50_b4d]\r\ncreate_clock -period 20 [get_ports osc_50_b4a]\r\ncreate_clock -period 20 [get_ports osc_50_b7a]\r\ncreate_clock -period 20 [get_ports osc_50_b7d]\r\ncreate_clock -period 20 [get_ports osc_50_b8d]\r\ncreate_clock -period 20 [get_ports osc_50_b8a]\r\n\r\nset_clock_groups -exclusive -group [get_clocks { *central_clk_div0* }] -group [get_clocks { *_hssi_pcie_hip* }]\r\nset_clock_groups -exclusive -group [get_clocks { refclk*clkout }] -group [get_clocks { *div0*coreclkout }]\r\n\r\n#**************************************************************\r\n# Create Generated Clock\r\n#**************************************************************\r\nderive_pll_clocks\r\n\r\n#**************************************************************\r\n# Set Clock Latency\r\n#**************************************************************\r\n\r\n\r\n#**************************************************************\r\n# Set Clock Uncertainty\r\n#**************************************************************\r\nderive_clock_uncertainty\r\n\r\n\r\n\r\n#**************************************************************\r\n# Set Input Delay\r\n#**************************************************************\r\n\r\n\r\n\r\n#**************************************************************\r\n# Set Output Delay\r\n#**************************************************************\r\n\r\n\r\n\r\n#**************************************************************\r\n# Set Clock Groups\r\n#**************************************************************\r\n\r\n\r\n\r\n#**************************************************************\r\n# Set False Path\r\n#**************************************************************\r\n\r\n\r\n\r\n#**************************************************************\r\n# Set Multicycle Path\r\n#**************************************************************\r\n\r\n\r\n\r\n#**************************************************************\r\n# Set Maximum Delay\r\n#**************************************************************\r\n\r\n\r\n\r\n#**************************************************************\r\n# Set Minimum Delay\r\n#**************************************************************\r\n\r\n\r\n\r\n#**************************************************************\r\n# Set Input Transition\r\n#**************************************************************\r\n\r\n\r\n\r\n#**************************************************************\r\n# Set Load\r\n#**************************************************************\r\n\r\n\r\n#Constraining JTAG interface\r\n#TCK port\r\ncreate_clock -name altera_reserved_tck -period 100 [get_ports altera_reserved_tck]\r\n#cut all paths to and from tck\r\nset_clock_groups -exclusive -group [get_clocks altera_reserved_tck]\r\n#constrain the TDI port\r\nset_input_delay -clock altera_reserved_tck 20 [get_ports altera_reserved_tdi]\r\n#constrain the TMS port\r\nset_input_delay -clock altera_reserved_tck 20 [get_ports altera_reserved_tms]\r\n#constrain the TDO port\r\nset_output_delay -clock altera_reserved_tck 20 [get_ports altera_reserved_tdo]\r\n\r\n\r\n"
  },
  {
    "path": "constraints/altera/htg4.qsf",
    "content": "set_instance_assignment -name IO_STANDARD \"DIFFERENTIAL LVPECL\" -to refclk\nset_instance_assignment -name IO_STANDARD \"2.5 V\" -to local_rstn_ext\nset_instance_assignment -name IO_STANDARD \"2.5 V\" -to pcie_rstn\nset_instance_assignment -name IO_STANDARD \"1.4-V PCML\" -to rx_in0\nset_instance_assignment -name IO_STANDARD \"1.4-V PCML\" -to rx_in1\nset_instance_assignment -name IO_STANDARD \"1.4-V PCML\" -to rx_in2\nset_instance_assignment -name IO_STANDARD \"1.4-V PCML\" -to rx_in3\nset_instance_assignment -name IO_STANDARD \"1.4-V PCML\" -to rx_in4\nset_instance_assignment -name IO_STANDARD \"1.4-V PCML\" -to rx_in5\nset_instance_assignment -name IO_STANDARD \"1.4-V PCML\" -to rx_in6\nset_instance_assignment -name IO_STANDARD \"1.4-V PCML\" -to rx_in7\nset_instance_assignment -name IO_STANDARD \"1.4-V PCML\" -to tx_out0\nset_instance_assignment -name IO_STANDARD \"1.4-V PCML\" -to tx_out1\nset_instance_assignment -name IO_STANDARD \"1.4-V PCML\" -to tx_out2\nset_instance_assignment -name IO_STANDARD \"1.4-V PCML\" -to tx_out3\nset_instance_assignment -name IO_STANDARD \"1.4-V PCML\" -to tx_out4\nset_instance_assignment -name IO_STANDARD \"1.4-V PCML\" -to tx_out5\nset_instance_assignment -name IO_STANDARD \"1.4-V PCML\" -to tx_out6\nset_instance_assignment -name IO_STANDARD \"1.4-V PCML\" -to tx_out7\nset_instance_assignment -name IO_STANDARD \"2.5 V\" -to lane_active_led[0]\nset_instance_assignment -name IO_STANDARD \"2.5 V\" -to lane_active_led[1]\nset_instance_assignment -name IO_STANDARD \"2.5 V\" -to lane_active_led[2]\nset_instance_assignment -name IO_STANDARD \"2.5 V\" -to lane_active_led[3]\nset_instance_assignment -name IO_STANDARD \"2.5 V\" -to L0_led\nset_instance_assignment -name IO_STANDARD \"2.5 V\" -to alive_led\nset_instance_assignment -name IO_STANDARD \"2.5 V\" -to comp_led\nset_instance_assignment -name IO_STANDARD \"1.4-V PCML\" -to tx_serial_data_1\nset_instance_assignment -name IO_STANDARD \"1.4-V PCML\" -to tx_serial_data_0\nset_instance_assignment -name IO_STANDARD \"1.4-V PCML\" -to rx_serial_data_1\nset_instance_assignment -name IO_STANDARD \"1.4-V PCML\" -to rx_serial_data_0\nset_instance_assignment -name GLOBAL_SIGNAL \"GLOBAL CLOCK\" -to core_clk_out\nset_instance_assignment -name IO_STANDARD \"DIFFERENTIAL LVPECL\" -to clk_644MHz\nset_instance_assignment -name IO_STANDARD LVDS -to clk_200MHz\nset_location_assignment PIN_G33 -to local_rstn_ext\nset_location_assignment PIN_AG24 -to pcie_rstn\nset_location_assignment PIN_AA38 -to refclk\nset_location_assignment PIN_AU38 -to rx_in0\nset_location_assignment PIN_AR38 -to rx_in1\nset_location_assignment PIN_AJ38 -to rx_in2\nset_location_assignment PIN_AG38 -to rx_in3\nset_location_assignment PIN_AE38 -to rx_in4\nset_location_assignment PIN_AC38 -to rx_in5\nset_location_assignment PIN_U38 -to rx_in6\nset_location_assignment PIN_R38 -to rx_in7\nset_location_assignment PIN_AT36 -to tx_out0\nset_location_assignment PIN_AP36 -to tx_out1\nset_location_assignment PIN_AH36 -to tx_out2\nset_location_assignment PIN_AF36 -to tx_out3\nset_location_assignment PIN_AD36 -to tx_out4\nset_location_assignment PIN_AB36 -to tx_out5\nset_location_assignment PIN_T36 -to tx_out6\nset_location_assignment PIN_P36 -to tx_out7\nset_location_assignment PIN_E34 -to gen2_led\nset_location_assignment PIN_N28 -to L0_led\nset_location_assignment PIN_F34 -to alive_led\nset_location_assignment PIN_R27 -to comp_led\nset_location_assignment PIN_D33 -to lane_active_led[0]\nset_location_assignment PIN_M28 -to lane_active_led[2]\nset_location_assignment PIN_D34 -to lane_active_led[3]\nset_location_assignment PIN_C34 -to lane_active_led[1]\nset_location_assignment PIN_A19 -to free_100MHz\nset_instance_assignment -name VIRTUAL_PIN ON -to app_int_sts\nset_instance_assignment -name VIRTUAL_PIN ON -to app_msi_num\nset_instance_assignment -name VIRTUAL_PIN ON -to app_msi_req\nset_instance_assignment -name VIRTUAL_PIN ON -to app_msi_tc\nset_instance_assignment -name VIRTUAL_PIN ON -to busy_altgxb_reconfig\nset_instance_assignment -name VIRTUAL_PIN ON -to cal_blk_clk\nset_instance_assignment -name VIRTUAL_PIN ON -to cpl_err\nset_instance_assignment -name VIRTUAL_PIN ON -to cpl_pending\nset_instance_assignment -name VIRTUAL_PIN ON -to crst\nset_instance_assignment -name VIRTUAL_PIN ON -to fixedclk_serdes\nset_instance_assignment -name VIRTUAL_PIN ON -to gxb_powerdown\nset_instance_assignment -name VIRTUAL_PIN ON -to hpg_ctrler\nset_instance_assignment -name VIRTUAL_PIN ON -to lmi_addr\nset_instance_assignment -name VIRTUAL_PIN ON -to lmi_din\nset_instance_assignment -name VIRTUAL_PIN ON -to lmi_rden\nset_instance_assignment -name VIRTUAL_PIN ON -to lmi_wren\nset_instance_assignment -name VIRTUAL_PIN ON -to pclk_in\nset_instance_assignment -name VIRTUAL_PIN ON -to pex_msi_num\nset_instance_assignment -name VIRTUAL_PIN ON -to phystatus_ext\nset_instance_assignment -name VIRTUAL_PIN ON -to pld_clk\nset_instance_assignment -name VIRTUAL_PIN ON -to pll_powerdown\nset_instance_assignment -name VIRTUAL_PIN ON -to pm_auxpwr\nset_instance_assignment -name VIRTUAL_PIN ON -to pm_data\nset_instance_assignment -name VIRTUAL_PIN ON -to pm_event\nset_instance_assignment -name VIRTUAL_PIN ON -to pme_to_cr\nset_instance_assignment -name VIRTUAL_PIN ON -to reconfig_clk\nset_instance_assignment -name VIRTUAL_PIN ON -to reconfig_togxb\nset_instance_assignment -name VIRTUAL_PIN ON -to rx_st_mask0\nset_instance_assignment -name VIRTUAL_PIN ON -to rx_st_ready0\nset_instance_assignment -name VIRTUAL_PIN ON -to rxdata0_ext\nset_instance_assignment -name VIRTUAL_PIN ON -to rxdata1_ext\nset_instance_assignment -name VIRTUAL_PIN ON -to rxdata2_ext\nset_instance_assignment -name VIRTUAL_PIN ON -to rxdata3_ext\nset_instance_assignment -name VIRTUAL_PIN ON -to rxdata4_ext\nset_instance_assignment -name VIRTUAL_PIN ON -to rxdata5_ext\nset_instance_assignment -name VIRTUAL_PIN ON -to rxdata6_ext\nset_instance_assignment -name VIRTUAL_PIN ON -to rxdata7_ext\nset_instance_assignment -name VIRTUAL_PIN ON -to rxdatak0_ext\nset_instance_assignment -name VIRTUAL_PIN ON -to rxdatak1_ext\nset_instance_assignment -name VIRTUAL_PIN ON -to rxdatak2_ext\nset_instance_assignment -name VIRTUAL_PIN ON -to rxdatak3_ext\nset_instance_assignment -name VIRTUAL_PIN ON -to rxdatak4_ext\nset_instance_assignment -name VIRTUAL_PIN ON -to rxdatak5_ext\nset_instance_assignment -name VIRTUAL_PIN ON -to rxdatak6_ext\nset_instance_assignment -name VIRTUAL_PIN ON -to rxdatak7_ext\nset_instance_assignment -name VIRTUAL_PIN ON -to rxelecidle0_ext\nset_instance_assignment -name VIRTUAL_PIN ON -to rxelecidle1_ext\nset_instance_assignment -name VIRTUAL_PIN ON -to rxelecidle2_ext\nset_instance_assignment -name VIRTUAL_PIN ON -to rxelecidle3_ext\nset_instance_assignment -name VIRTUAL_PIN ON -to rxelecidle4_ext\nset_instance_assignment -name VIRTUAL_PIN ON -to rxelecidle5_ext\nset_instance_assignment -name VIRTUAL_PIN ON -to rxelecidle6_ext\nset_instance_assignment -name VIRTUAL_PIN ON -to rxelecidle7_ext\nset_instance_assignment -name VIRTUAL_PIN ON -to rxstatus0_ext\nset_instance_assignment -name VIRTUAL_PIN ON -to rxstatus1_ext\nset_instance_assignment -name VIRTUAL_PIN ON -to rxstatus2_ext\nset_instance_assignment -name VIRTUAL_PIN ON -to rxstatus3_ext\nset_instance_assignment -name VIRTUAL_PIN ON -to rxstatus4_ext\nset_instance_assignment -name VIRTUAL_PIN ON -to rxstatus5_ext\nset_instance_assignment -name VIRTUAL_PIN ON -to rxstatus6_ext\nset_instance_assignment -name VIRTUAL_PIN ON -to rxstatus7_ext\nset_instance_assignment -name VIRTUAL_PIN ON -to rxvalid0_ext\nset_instance_assignment -name VIRTUAL_PIN ON -to rxvalid1_ext\nset_instance_assignment -name VIRTUAL_PIN ON -to rxvalid2_ext\nset_instance_assignment -name VIRTUAL_PIN ON -to rxvalid3_ext\nset_instance_assignment -name VIRTUAL_PIN ON -to rxvalid4_ext\nset_instance_assignment -name VIRTUAL_PIN ON -to rxvalid5_ext\nset_instance_assignment -name VIRTUAL_PIN ON -to rxvalid6_ext\nset_instance_assignment -name VIRTUAL_PIN ON -to rxvalid7_ext\nset_instance_assignment -name VIRTUAL_PIN ON -to srst\nset_instance_assignment -name VIRTUAL_PIN ON -to test_in\nset_instance_assignment -name VIRTUAL_PIN ON -to tx_st_data0\nset_instance_assignment -name VIRTUAL_PIN ON -to tx_st_empty0\nset_instance_assignment -name VIRTUAL_PIN ON -to tx_st_eop0\nset_instance_assignment -name VIRTUAL_PIN ON -to tx_st_err0\nset_instance_assignment -name VIRTUAL_PIN ON -to tx_st_sop0\nset_instance_assignment -name VIRTUAL_PIN ON -to tx_st_valid0\nset_instance_assignment -name VIRTUAL_PIN ON -to app_int_ack\nset_instance_assignment -name VIRTUAL_PIN ON -to app_msi_ack\nset_instance_assignment -name VIRTUAL_PIN ON -to clk250_out\nset_instance_assignment -name VIRTUAL_PIN ON -to clk500_out\nset_instance_assignment -name VIRTUAL_PIN ON -to derr_cor_ext_rcv0\nset_instance_assignment -name VIRTUAL_PIN ON -to derr_cor_ext_rpl\nset_instance_assignment -name VIRTUAL_PIN ON -to derr_rpl\nset_instance_assignment -name VIRTUAL_PIN ON -to dlup_exit\nset_instance_assignment -name VIRTUAL_PIN ON -to hotrst_exit\nset_instance_assignment -name VIRTUAL_PIN ON -to ko_cpl_spc_vc0\nset_instance_assignment -name VIRTUAL_PIN ON -to l2_exit\nset_instance_assignment -name VIRTUAL_PIN ON -to lane_act\nset_instance_assignment -name VIRTUAL_PIN ON -to lmi_ack\nset_instance_assignment -name VIRTUAL_PIN ON -to lmi_dout\nset_instance_assignment -name VIRTUAL_PIN ON -to ltssm\nset_instance_assignment -name VIRTUAL_PIN ON -to npd_alloc_1cred_vc0\nset_instance_assignment -name VIRTUAL_PIN ON -to npd_cred_vio_vc0\nset_instance_assignment -name VIRTUAL_PIN ON -to nph_alloc_1cred_vc0\nset_instance_assignment -name VIRTUAL_PIN ON -to nph_cred_vio_vc0\nset_instance_assignment -name VIRTUAL_PIN ON -to pme_to_sr\nset_instance_assignment -name VIRTUAL_PIN ON -to powerdown_ext\nset_instance_assignment -name VIRTUAL_PIN ON -to r2c_err0\nset_instance_assignment -name VIRTUAL_PIN ON -to rate_ext\nset_instance_assignment -name VIRTUAL_PIN ON -to rc_pll_locked\nset_instance_assignment -name VIRTUAL_PIN ON -to rc_rx_digitalreset\nset_instance_assignment -name VIRTUAL_PIN ON -to reconfig_fromgxb\nset_instance_assignment -name VIRTUAL_PIN ON -to reset_status\nset_instance_assignment -name VIRTUAL_PIN ON -to rx_fifo_empty0\nset_instance_assignment -name VIRTUAL_PIN ON -to rx_fifo_full0\nset_instance_assignment -name VIRTUAL_PIN ON -to rx_st_bardec0\nset_instance_assignment -name VIRTUAL_PIN ON -to rx_st_be0\nset_instance_assignment -name VIRTUAL_PIN ON -to rx_st_data0\nset_instance_assignment -name VIRTUAL_PIN ON -to rx_st_empty0\nset_instance_assignment -name VIRTUAL_PIN ON -to rx_st_eop0\nset_instance_assignment -name VIRTUAL_PIN ON -to rx_st_err0\nset_instance_assignment -name VIRTUAL_PIN ON -to rx_st_sop0\nset_instance_assignment -name VIRTUAL_PIN ON -to rx_st_valid0\nset_instance_assignment -name VIRTUAL_PIN ON -to rxpolarity0_ext\nset_instance_assignment -name VIRTUAL_PIN ON -to rxpolarity1_ext\nset_instance_assignment -name VIRTUAL_PIN ON -to rxpolarity2_ext\nset_instance_assignment -name VIRTUAL_PIN ON -to rxpolarity3_ext\nset_instance_assignment -name VIRTUAL_PIN ON -to rxpolarity4_ext\nset_instance_assignment -name VIRTUAL_PIN ON -to rxpolarity5_ext\nset_instance_assignment -name VIRTUAL_PIN ON -to rxpolarity6_ext\nset_instance_assignment -name VIRTUAL_PIN ON -to rxpolarity7_ext\nset_instance_assignment -name VIRTUAL_PIN ON -to suc_spd_neg\nset_instance_assignment -name VIRTUAL_PIN ON -to test_out\nset_instance_assignment -name VIRTUAL_PIN ON -to tl_cfg_add\nset_instance_assignment -name VIRTUAL_PIN ON -to tl_cfg_ctl\nset_instance_assignment -name VIRTUAL_PIN ON -to tl_cfg_ctl_wr\nset_instance_assignment -name VIRTUAL_PIN ON -to tl_cfg_sts\nset_instance_assignment -name VIRTUAL_PIN ON -to tl_cfg_sts_wr\nset_instance_assignment -name VIRTUAL_PIN ON -to tx_cred0\nset_instance_assignment -name VIRTUAL_PIN ON -to tx_fifo_empty0\nset_instance_assignment -name VIRTUAL_PIN ON -to tx_fifo_full0\nset_instance_assignment -name VIRTUAL_PIN ON -to tx_fifo_rdptr0\nset_instance_assignment -name VIRTUAL_PIN ON -to tx_fifo_wrptr0\nset_instance_assignment -name VIRTUAL_PIN ON -to tx_st_ready0\nset_instance_assignment -name VIRTUAL_PIN ON -to txcompl0_ext\nset_instance_assignment -name VIRTUAL_PIN ON -to txcompl1_ext\nset_instance_assignment -name VIRTUAL_PIN ON -to txcompl2_ext\nset_instance_assignment -name VIRTUAL_PIN ON -to txcompl3_ext\nset_instance_assignment -name VIRTUAL_PIN ON -to txcompl4_ext\nset_instance_assignment -name VIRTUAL_PIN ON -to txcompl5_ext\nset_instance_assignment -name VIRTUAL_PIN ON -to txcompl6_ext\nset_instance_assignment -name VIRTUAL_PIN ON -to txcompl7_ext\nset_instance_assignment -name VIRTUAL_PIN ON -to txdata0_ext\nset_instance_assignment -name VIRTUAL_PIN ON -to txdata1_ext\nset_instance_assignment -name VIRTUAL_PIN ON -to txdata2_ext\nset_instance_assignment -name VIRTUAL_PIN ON -to txdata3_ext\nset_instance_assignment -name VIRTUAL_PIN ON -to txdata4_ext\nset_instance_assignment -name VIRTUAL_PIN ON -to txdata5_ext\nset_instance_assignment -name VIRTUAL_PIN ON -to txdata6_ext\nset_instance_assignment -name VIRTUAL_PIN ON -to txdata7_ext\nset_instance_assignment -name VIRTUAL_PIN ON -to txdatak0_ext\nset_instance_assignment -name VIRTUAL_PIN ON -to txdatak1_ext\nset_instance_assignment -name VIRTUAL_PIN ON -to txdatak2_ext\nset_instance_assignment -name VIRTUAL_PIN ON -to txdatak3_ext\nset_instance_assignment -name VIRTUAL_PIN ON -to txdatak4_ext\nset_instance_assignment -name VIRTUAL_PIN ON -to txdatak5_ext\nset_instance_assignment -name VIRTUAL_PIN ON -to txdatak6_ext\nset_instance_assignment -name VIRTUAL_PIN ON -to txdatak7_ext\nset_instance_assignment -name VIRTUAL_PIN ON -to txdetectrx_ext\nset_instance_assignment -name VIRTUAL_PIN ON -to txelecidle0_ext\nset_instance_assignment -name VIRTUAL_PIN ON -to txelecidle1_ext\nset_instance_assignment -name VIRTUAL_PIN ON -to txelecidle2_ext\nset_instance_assignment -name VIRTUAL_PIN ON -to txelecidle3_ext\nset_instance_assignment -name VIRTUAL_PIN ON -to txelecidle4_ext\nset_instance_assignment -name VIRTUAL_PIN ON -to txelecidle5_ext\nset_instance_assignment -name VIRTUAL_PIN ON -to txelecidle6_ext\nset_instance_assignment -name VIRTUAL_PIN ON -to txelecidle7_ext\nset_instance_assignment -name INPUT_TERMINATION OFF -to refclk\nset_location_assignment PIN_K34 -to clk_200MHz\nset_location_assignment PIN_AK25 -to mdc_from_the_mdio\nset_location_assignment PIN_AM26 -to mdio_in_out_from_the_mdio\nset_location_assignment PIN_AN26 -to lane2_prwdn\nset_location_assignment PIN_AP27 -to lane1_prwdn\nset_location_assignment PIN_AT27 -to sfp1_mod\nset_location_assignment PIN_AU27 -to sfp1_rate_sel\nset_location_assignment PIN_AW30 -to sfp1_tx_disable\nset_location_assignment PIN_AW32 -to sfp2_mod\nset_location_assignment PIN_AW33 -to sfp2_rate_sel\nset_location_assignment PIN_AW28 -to sfp2_tx_disable\nset_location_assignment PIN_AW31 -to sfp2_tx_fault\nset_location_assignment PIN_AW27 -to sfp1_tx_fault\nset_location_assignment PIN_AK26 -to phy_reset_n\nset_location_assignment PIN_K4 -to tx_serial_data_1\nset_location_assignment PIN_L2 -to rx_serial_data_1\nset_location_assignment PIN_M4 -to tx_serial_data_0\nset_location_assignment PIN_N2 -to rx_serial_data_0\nset_location_assignment PIN_J2 -to clk_644MHz\nset_location_assignment PIN_N30 -to usr_sw[7]\nset_location_assignment PIN_N29 -to usr_sw[6]\nset_location_assignment PIN_M31 -to usr_sw[5]\nset_location_assignment PIN_L31 -to usr_sw[4]\nset_location_assignment PIN_K32 -to usr_sw[3]\nset_location_assignment PIN_J33 -to usr_sw[2]\nset_location_assignment PIN_H34 -to usr_sw[1]\nset_location_assignment PIN_T27 -to usr_sw[0]\nset_location_assignment PIN_V29 -to req_compliance_push_button_n\nset_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top\n"
  },
  {
    "path": "constraints/altera/htg4.sdc",
    "content": "\r\n#**************************************************************\r\n# Create Clock\r\n#**************************************************************\r\n\r\n#create_clock -period 10 [get_ports pcie_refclk_p]\r\n#create_clock -period 10 [get_ports sfp_refclk]\r\n#create_clock -period 20 [get_ports osc_50_b3b]\r\n#create_clock -period 20 [get_ports osc_50_b3d]\r\n#create_clock -period 20 [get_ports osc_50_b4d]\r\n#create_clock -period 20 [get_ports osc_50_b4a]\r\n#create_clock -period 20 [get_ports osc_50_b7a]\r\n#create_clock -period 20 [get_ports osc_50_b7d]\r\n#create_clock -period 20 [get_ports osc_50_b8d]\r\n#create_clock -period 20 [get_ports osc_50_b8a]\r\n#\r\nset_clock_groups -exclusive -group [get_clocks { *central_clk_div0* }] -group [get_clocks { *_hssi_pcie_hip* }]\r\nset_clock_groups -exclusive -group [get_clocks { refclk*clkout }] -group [get_clocks { *div0*coreclkout }]\r\n\r\n#**************************************************************\r\n# Create Generated Clock\r\n#**************************************************************\r\nderive_pll_clocks\r\n\r\n\r\n\r\n\r\n\r\n\r\n#**************************************************************\r\n# Set Clock Latency\r\n#**************************************************************\r\n\r\n\r\n#**************************************************************\r\n# Set Clock Uncertainty\r\n#**************************************************************\r\nderive_clock_uncertainty\r\n\r\n\r\n\r\n#**************************************************************\r\n# Set Input Delay\r\n#**************************************************************\r\n\r\n\r\n\r\n#**************************************************************\r\n# Set Output Delay\r\n#**************************************************************\r\n\r\n\r\n\r\n#**************************************************************\r\n# Set Clock Groups\r\n#**************************************************************\r\n\r\n\r\n\r\n#**************************************************************\r\n# Set False Path\r\n#**************************************************************\r\n\r\n\r\n\r\n#**************************************************************\r\n# Set Multicycle Path\r\n#**************************************************************\r\n\r\n\r\n\r\n#**************************************************************\r\n# Set Maximum Delay\r\n#**************************************************************\r\n\r\n\r\n\r\n#**************************************************************\r\n# Set Minimum Delay\r\n#**************************************************************\r\n\r\n\r\n\r\n#**************************************************************\r\n# Set Input Transition\r\n#**************************************************************\r\n\r\n\r\n\r\n#**************************************************************\r\n# Set Load\r\n#**************************************************************\r\n\r\n\r\n\r\n\r\n\r\n"
  },
  {
    "path": "constraints/xilinx/Readme.md",
    "content": "Procedure for creating part constraint files\n\nStart Vivado\nCreate new project\n  In New Vivado Project window\n     click Next\n  In Project Name window\n     click next (but note the name, or change it)\n  In Project Type window\n    select RTL Project\n    click next\n  In Add Sources\n     select Target language Verilog\n     click next\n  In Add Existing IP\n     click next\n  In Add Constraints\n     click next\n  In Default Part\n\nIf the board type is known to Vivado, select board and choose the right board\notherwise \n     Specify Parts\n     Search for desired part\n     click next\n  In New Project Summary\n     click finish\n\nIn Flow Navigator, \n   Create Block Design\n\nIn Block Design\n   Add IP\n      search for Processing System, add that\n      Click Run Block Automation, to make DDR and Fixed_IO connections\n   Add IP\n      search for GPIO, add that\n   Run connection automation\n      use drop down box to select GPIO AXI\n\nThis will add the reset logic and other basic stuff\n\n\nCtrl-S or Save Block Design\n\nIn Hierarch winddow, select Sources tab\nRight click Design top level\n   Select Generate HDL wrapper\n\nIn Flow navigator\n  Run Synthesis\n \n(The file you need should be there now)\n  Run Implementation\n  Run Generate Bitstream\n\nExit Vivado\nGo to project directory tree\nSearch for xdc files:\n\nfind .|grep .xdc\n\nThere should be one named something like\n\n\nIn part area, search for and select desired part\n\n./project_6.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0.xdc\n\nCopy this file to\n\n.../connectal/constraints/xilinx/<partnumber>.xdc\n\nCheck this file into git, then edit it to add a comment about where it\ncame from and to comment out the create_clock and set_jitter\nlines near the top\n\n"
  },
  {
    "path": "constraints/xilinx/ac701.xdc",
    "content": "######################################################################################################\n##  File name :       default.xdc\n##\n##  Details :     Constraints file\n##                    FPGA family:       artix7\n##                    FPGA:              xc7a200tfbg676\n##                    Speedgrade:        -2\n##\n######################################################################################################\n\n######################################################################################################\n# PIN ASSIGNMENTS\n######################################################################################################\nset_property LOC M26 [get_ports {GPIO_leds[0]}]\nset_property LOC T24 [get_ports {GPIO_leds[1]}]\nset_property LOC T25 [get_ports {GPIO_leds[2]}]\nset_property LOC R26 [get_ports {GPIO_leds[3]}]\nset_property LOC U4 [get_ports {RST_cpu_reset}]\n\nset_property IOSTANDARD LVCMOS33 [get_ports {GPIO_leds[0]}]\nset_property IOSTANDARD LVCMOS33 [get_ports {GPIO_leds[1]}]\nset_property IOSTANDARD LVCMOS33 [get_ports {GPIO_leds[2]}]\nset_property IOSTANDARD LVCMOS33 [get_ports {GPIO_leds[3]}]\nset_property IOSTANDARD LVCMOS15 [get_ports {RST_cpu_reset}]\n\nset_property SLEW SLOW [get_ports GPIO_leds]\nset_property DRIVE 12 [get_ports GPIO_leds]\n\nset_property LOC F11   [get_ports { CLK_pci_sys_clk_p }]\nset_property LOC E11  [get_ports { CLK_pci_sys_clk_n }]\nset_property LOC M20  [get_ports { RST_N_pci_sys_reset_n }]\n\nset_property LOC R3 [get_ports { CLK_sys_clk_p }]\nset_property LOC P3 [get_ports { CLK_sys_clk_n }]\n# set_property LOC M21  [get_ports { CLK_user_clk_p }]\n# set_property LOC M22  [get_ports { CLK_user_clk_n }]\n\nset_property LOC D12  [get_ports { PCIE_rxp_i[0] }]\nset_property LOC B13  [get_ports { PCIE_rxp_i[1] }]\nset_property LOC D14  [get_ports { PCIE_rxp_i[2] }]\nset_property LOC B11  [get_ports { PCIE_rxp_i[3] }]\n\nset_property LOC C12  [get_ports { PCIE_rxn_i[0] }]\nset_property LOC A13  [get_ports { PCIE_rxn_i[1] }]\nset_property LOC C14  [get_ports { PCIE_rxn_i[2] }]\nset_property LOC A11  [get_ports { PCIE_rxn_i[3] }]\n\nset_property LOC D10   [get_ports { PCIE_txp[0] }]\nset_property LOC B9   [get_ports { PCIE_txp[1] }]\nset_property LOC D8   [get_ports { PCIE_txp[2] }]\nset_property LOC B7   [get_ports { PCIE_txp[3] }]\n\nset_property LOC C10  [get_ports { PCIE_txn[0] }]\nset_property LOC A9   [get_ports { PCIE_txn[1] }]\nset_property LOC C8   [get_ports { PCIE_txn[2] }]\nset_property LOC A7   [get_ports { PCIE_txn[3] }]\n\n######################################################################################################\n# I/O STANDARDS\n######################################################################################################\nset_property IOSTANDARD LVCMOS33    [get_ports { GPIO_leds[*] }]\nset_property IOSTANDARD DIFF_SSTL15 [get_ports { CLK_sys_clk_* }]\n# set_property IOSTANDARD DIFF_SSTL15 [get_ports { CLK_user_clk_* }]\nset_property IOSTANDARD LVCMOS33    [get_ports { RST_N_pci_sys_reset_n }]\nset_property PULLUP     true        [get_ports { RST_N_pci_sys_reset_n }]\n\n######################################################################################################\n# CELL LOCATIONS\n######################################################################################################\n#\n# SYS clock 100 MHz (input) signal. The sys_clk_p and sys_clk_n\n# signals are the PCI Express reference clock. Virtex-7 GT\n# Transceiver architecture requires the use of a dedicated clock\n# resources (FPGA input pins) associated with each GT Transceiver.\n# To use these pins an IBUFDS primitive (refclk_ibuf) is\n# instantiated in user's design.\n# Please refer to the Virtex-7 GT Transceiver User Guide\n# (UG) for guidelines regarding clock resource selection.\n#\nset_property LOC IBUFDS_GTE2_X0Y2  [get_cells { *pci_clk_100mhz_buf }]\n#set_property LOC MMCME2_ADV_X1Y1 [get_cells -hier -filter { NAME =~ *clk_gen_pll }]\n\n#\n# PCI Express Block placement. This constraint selects the PCI Express\n# Block to be used.\n#\nset_property LOC PCIE_X0Y0 [get_cells -hierarchical -regexp {.*pcie_7x_i/pcie_block_i}]\nset_property LOC MMCME2_ADV_X0Y4 [get_cells *clkgen_pll]\nset_property LOC MMCME2_ADV_X0Y3 [get_cells *_ep/ext_clk.pipe_clock_i/mmcm_i]\n\n#\n# BlockRAM placement\n#\nset_property LOC RAMB36_X1Y46 [get_cells {*\\/pcie_7x_i/pcie_top_i/pcie_7x_i/pcie_bram_top/pcie_brams_rx/brams[3].ram/use_tdp.ramb36/genblk*.bram36_tdp_bl.bram36_tdp_bl}] */\nset_property LOC RAMB36_X1Y45 [get_cells {*\\/pcie_7x_i/pcie_top_i/pcie_7x_i/pcie_bram_top/pcie_brams_rx/brams[2].ram/use_tdp.ramb36/genblk*.bram36_tdp_bl.bram36_tdp_bl}] */\nset_property LOC RAMB36_X1Y44 [get_cells {*\\/pcie_7x_i/pcie_top_i/pcie_7x_i/pcie_bram_top/pcie_brams_rx/brams[1].ram/use_tdp.ramb36/genblk*.bram36_tdp_bl.bram36_tdp_bl}] */\nset_property LOC RAMB36_X1Y43 [get_cells {*\\/pcie_7x_i/pcie_top_i/pcie_7x_i/pcie_bram_top/pcie_brams_rx/brams[0].ram/use_tdp.ramb36/genblk*.bram36_tdp_bl.bram36_tdp_bl}] */\nset_property LOC RAMB36_X1Y42 [get_cells {*\\/pcie_7x_i/pcie_top_i/pcie_7x_i/pcie_bram_top/pcie_brams_tx/brams[0].ram/use_tdp.ramb36/genblk*.bram36_tdp_bl.bram36_tdp_bl}] */\nset_property LOC RAMB36_X1Y41 [get_cells {*\\/pcie_7x_i/pcie_top_i/pcie_7x_i/pcie_bram_top/pcie_brams_tx/brams[1].ram/use_tdp.ramb36/genblk*.bram36_tdp_bl.bram36_tdp_bl}] */\nset_property LOC RAMB36_X1Y40 [get_cells {*\\/pcie_7x_i/pcie_top_i/pcie_7x_i/pcie_bram_top/pcie_brams_tx/brams[2].ram/use_tdp.ramb36/genblk*.bram36_tdp_bl.bram36_tdp_bl}] */\nset_property LOC RAMB36_X1Y39 [get_cells {*\\/pcie_7x_i/pcie_top_i/pcie_7x_i/pcie_bram_top/pcie_brams_tx/brams[3].ram/use_tdp.ramb36/genblk*.bram36_tdp_bl.bram36_tdp_bl}] */\n\n######################################################################################################\n# TIMING CONSTRAINTS\n######################################################################################################\n\n## in pcie-clocks.xdc\n"
  },
  {
    "path": "constraints/xilinx/awsf1.xdc",
    "content": "# TBD\n"
  },
  {
    "path": "constraints/xilinx/bluesim.xdc",
    "content": "this file intentionally left blank\n"
  },
  {
    "path": "constraints/xilinx/bluesim_pcie.xdc",
    "content": "this file intentionally left blank\n"
  },
  {
    "path": "constraints/xilinx/cdc.tcl",
    "content": "##\n## set properties to help out clock domain crossing analysis\n##\n\n# set ASYNC_REG property on SyncReset and SyncFifo variants\nforeach pat {\"reset_hold_reg[*]\" \"sGEnqPtr*_reg[*]\" \"dGDeqPtr*_reg[*]\" \"sSyncReg*_reg[*]\" \"dSyncReg*_reg[*]\"} {\n    set cells [get_cells -hier $pat]\n    if {[llength $cells] > 0} {\n\tputs \"ASYNC_REG $cells\"\n\tset_property ASYNC_REG 1 $cells\n    }\n}\n"
  },
  {
    "path": "constraints/xilinx/kc160g2.xdc",
    "content": "######################################################################################################\n##  File name :       default.xdc\n##\n##  Details :     Constraints file\n##                    FPGA family:       kintex7\n##                    FPGA:              xc7k325t-2ffg900\n##                    Speedgrade:        -2\n##\n######################################################################################################\n\n######################################################################################################\n# PIN ASSIGNMENTS\n######################################################################################################\n\n######################################################################################################\n# I/O STANDARDS\n######################################################################################################\nset_property IOSTANDARD DIFF_SSTL15 [get_ports { CLK_pci_sys_clk_* }]\nset_property IOSTANDARD DIFF_SSTL15 [get_ports { CLK_sys_clk_* }]\n#set_property IOSTANDARD DIFF_SSTL15 [get_ports { CLK_user_clk_* }]\nset_property IOSTANDARD LVCMOS25    [get_ports { RST_N_pci_sys_reset_n }]\nset_property PULLUP     true        [get_ports { RST_N_pci_sys_reset_n }]\n\n######################################################################################################\n# CELL LOCATIONS\n######################################################################################################\n#\n# SYS clock 100 MHz (input) signal. The sys_clk_p and sys_clk_n\n# signals are the PCI Express reference clock. Virtex-7 GT\n# Transceiver architecture requires the use of a dedicated clock\n# resources (FPGA input pins) associated with each GT Transceiver.\n# To use these pins an IBUFDS primitive (refclk_ibuf) is\n# instantiated in user's design.\n# Please refer to the Virtex-7 GT Transceiver User Guide\n# (UG) for guidelines regarding clock resource selection.\n#\n##set_property LOC IBUFDS_GTE2_X0Y1  [get_cells { *pci_clk_100mhz_buf }]\n\n######################################################################################################\n# TIMING CONSTRAINTS\n######################################################################################################\n\n## in pcie-clocks.xdc\n"
  },
  {
    "path": "constraints/xilinx/kc705-3.0.xdc",
    "content": "######################################################################################################\n##  File name :       default.xdc\n##\n##  Details :     Constraints file\n##                    FPGA family:       kintex7\n##                    FPGA:              xc7k325t-2ffg900\n##                    Speedgrade:        -2\n##\n######################################################################################################\n\n######################################################################################################\n# PIN ASSIGNMENTS\n######################################################################################################\nset_property LOC AB8  [get_ports { GPIO_leds[0] }]\nset_property LOC AA8  [get_ports { GPIO_leds[1] }]\nset_property LOC AC9  [get_ports { GPIO_leds[2] }]\nset_property LOC AB9  [get_ports { GPIO_leds[3] }]\nset_property LOC AE26 [get_ports { GPIO_leds[4] }]\nset_property LOC G19  [get_ports { GPIO_leds[5] }]\nset_property LOC E18  [get_ports { GPIO_leds[6] }]\nset_property LOC F16  [get_ports { GPIO_leds[7] }]\n\n# set_property LOC Y28  [get_ports { DIP_3_gpio }]\n# set_property LOC AA28 [get_ports { DIP_2_gpio }]\n# set_property LOC W29  [get_ports { DIP_1_gpio }]\n# set_property LOC Y29  [get_ports { DIP_0_gpio }]\n\n#set_property LOC G12  [get_ports { BUTTON_0_gpio }]\n#set_property LOC AC6  [get_ports { BUTTON_1_gpio }]\n#set_property LOC AB12 [get_ports { BUTTON_2_gpio }]\n#set_property LOC AG5  [get_ports { BUTTON_3_gpio }]\n#set_property LOC AA12 [get_ports { BUTTON_4_gpio }]\n\n# set_property LOC AA21 [get_ports { BUTTON_0_gpio }]\n# set_property LOC AB22 [get_ports { BUTTON_1_gpio }]\n# set_property LOC AB23 [get_ports { BUTTON_2_gpio }]\n# set_property LOC AA22 [get_ports { BUTTON_3_gpio }]\n# set_property LOC AA23 [get_ports { BUTTON_4_gpio }]\n\n\n# set_property LOC Y10  [get_ports { LCD_db[3] }]\n# set_property LOC AA11 [get_ports { LCD_db[2] }]\n# set_property LOC AA10 [get_ports { LCD_db[1] }]\n# set_property LOC AA13 [get_ports { LCD_db[0] }]\n# set_property LOC AB10 [get_ports { LCD_e }]\n# set_property LOC Y11  [get_ports { LCD_rs }]\n# set_property LOC AB13 [get_ports { LCD_rw }]\n\nset_property LOC U8   [get_ports { CLK_pci_sys_clk_p }]\nset_property LOC U7   [get_ports { CLK_pci_sys_clk_n }]\nset_property LOC G25  [get_ports { RST_N_pci_sys_reset_n }]\nset_property LOC AD12 [get_ports { CLK_sys_clk_p }]\nset_property LOC AD11 [get_ports { CLK_sys_clk_n }]\nset_property LOC K28  [get_ports { CLK_user_clk_p }]\nset_property LOC K29  [get_ports { CLK_user_clk_n }]\n\nset_property LOC M6   [get_ports { PCIE_rxp_i[0] }]\nset_property LOC P6   [get_ports { PCIE_rxp_i[1] }]\nset_property LOC R4   [get_ports { PCIE_rxp_i[2] }]\nset_property LOC T6   [get_ports { PCIE_rxp_i[3] }]\nset_property LOC V6   [get_ports { PCIE_rxp_i[4] }]\nset_property LOC W4   [get_ports { PCIE_rxp_i[5] }]\nset_property LOC Y6   [get_ports { PCIE_rxp_i[6] }]\nset_property LOC AA4  [get_ports { PCIE_rxp_i[7] }]\n\nset_property LOC M5   [get_ports { PCIE_rxn_i[0] }]\nset_property LOC P5   [get_ports { PCIE_rxn_i[1] }]\nset_property LOC R3   [get_ports { PCIE_rxn_i[2] }]\nset_property LOC T5   [get_ports { PCIE_rxn_i[3] }]\nset_property LOC V5   [get_ports { PCIE_rxn_i[4] }]\nset_property LOC W3   [get_ports { PCIE_rxn_i[5] }]\nset_property LOC Y5   [get_ports { PCIE_rxn_i[6] }]\nset_property LOC AA3  [get_ports { PCIE_rxn_i[7] }]\n\nset_property LOC L4   [get_ports { PCIE_txp[0] }]\nset_property LOC M2   [get_ports { PCIE_txp[1] }]\nset_property LOC N4   [get_ports { PCIE_txp[2] }]\nset_property LOC P2   [get_ports { PCIE_txp[3] }]\nset_property LOC T2   [get_ports { PCIE_txp[4] }]\nset_property LOC U4   [get_ports { PCIE_txp[5] }]\nset_property LOC V2   [get_ports { PCIE_txp[6] }]\nset_property LOC Y2   [get_ports { PCIE_txp[7] }]\n\nset_property LOC L3   [get_ports { PCIE_txn[0] }]\nset_property LOC M1   [get_ports { PCIE_txn[1] }]\nset_property LOC N3   [get_ports { PCIE_txn[2] }]\nset_property LOC P1   [get_ports { PCIE_txn[3] }]\nset_property LOC T1   [get_ports { PCIE_txn[4] }]\nset_property LOC U3   [get_ports { PCIE_txn[5] }]\nset_property LOC V1   [get_ports { PCIE_txn[6] }]\nset_property LOC Y1   [get_ports { PCIE_txn[7] }]\n\n######################################################################################################\n# I/O STANDARDS\n######################################################################################################\nset_property IOSTANDARD LVCMOS15    [get_ports { GPIO_leds[*] }]\n# set_property IOSTANDARD LVCMOS15    [get_ports { DIP_*_gpio }]\n# set_property IOSTANDARD LVCMOS25    [get_ports { BUTTON_*_gpio }]\n# set_property IOSTANDARD LVCMOS15    [get_ports { LCD_* }]\nset_property IOSTANDARD DIFF_SSTL15 [get_ports { CLK_sys_clk_* }]\nset_property IOSTANDARD DIFF_SSTL15 [get_ports { CLK_user_clk_* }]\nset_property IOSTANDARD LVCMOS25    [get_ports { RST_N_pci_sys_reset_n }]\nset_property PULLUP     true        [get_ports { RST_N_pci_sys_reset_n }]\n\n######################################################################################################\n# CELL LOCATIONS\n######################################################################################################\n#\n# SYS clock 100 MHz (input) signal. The sys_clk_p and sys_clk_n\n# signals are the PCI Express reference clock. Virtex-7 GT\n# Transceiver architecture requires the use of a dedicated clock\n# resources (FPGA input pins) associated with each GT Transceiver.\n# To use these pins an IBUFDS primitive (refclk_ibuf) is\n# instantiated in user's design.\n# Please refer to the Virtex-7 GT Transceiver User Guide\n# (UG) for guidelines regarding clock resource selection.\n#\nset_property LOC IBUFDS_GTE2_X0Y1  [get_cells { *pci_clk_100mhz_buf }]\nset_property LOC MMCME2_ADV_X1Y1 [get_cells -hier -filter { NAME =~ *clk_gen_pll }]\n\n#\n# Transceiver instance placement.  This constraint selects the\n# transceivers to be used, which also dictates the pinout for the\n# transmit and receive differential pairs.  Please refer to the\n# Virtex-7 GT Transceiver User Guide (UG) for more information.\n#\n\n# PCIe Lane 0\nset_property LOC GTXE2_CHANNEL_X0Y7 [get_cells -hierarchical -regexp {.*pipe_lane\\[0\\].gt_wrapper_i/gtx_channel.gtxe2_channel_i}]\n# PCIe Lane 1\nset_property LOC GTXE2_CHANNEL_X0Y6 [get_cells -hierarchical -regexp {.*pipe_lane\\[1\\].gt_wrapper_i/gtx_channel.gtxe2_channel_i}]\n# PCIe Lane 2\nset_property LOC GTXE2_CHANNEL_X0Y5 [get_cells -hierarchical -regexp {.*pipe_lane\\[2\\].gt_wrapper_i/gtx_channel.gtxe2_channel_i}]\n# PCIe Lane 3\nset_property LOC GTXE2_CHANNEL_X0Y4 [get_cells -hierarchical -regexp {.*pipe_lane\\[3\\].gt_wrapper_i/gtx_channel.gtxe2_channel_i}]\n# PCIe Lane 4\nset_property LOC GTXE2_CHANNEL_X0Y3 [get_cells -hierarchical -regexp {.*pipe_lane\\[4\\].gt_wrapper_i/gtx_channel.gtxe2_channel_i}]\n# PCIe Lane 5\nset_property LOC GTXE2_CHANNEL_X0Y2 [get_cells -hierarchical -regexp {.*pipe_lane\\[5\\].gt_wrapper_i/gtx_channel.gtxe2_channel_i}]\n# PCIe Lane 6\nset_property LOC GTXE2_CHANNEL_X0Y1 [get_cells -hierarchical -regexp {.*pipe_lane\\[6\\].gt_wrapper_i/gtx_channel.gtxe2_channel_i}]\n# PCIe Lane 7\nset_property LOC GTXE2_CHANNEL_X0Y0 [get_cells -hierarchical -regexp {.*pipe_lane\\[7\\].gt_wrapper_i/gtx_channel.gtxe2_channel_i}]\n\n#\n# PCI Express Block placement. This constraint selects the PCI Express\n# Block to be used.\n#\nset_property LOC PCIE_X0Y0 [get_cells -hierarchical -regexp {.*pcie_7x_i/pcie_block_i}]\n\n#\n# BlockRAM placement\n#\nset_property LOC RAMB36_X4Y35 [get_cells {*/pcie_7x_i/pcie_top_i/pcie_7x_i/pcie_bram_top/pcie_brams_rx/brams[3].ram/use_tdp.ramb36/genblk*.bram36_tdp_bl.bram36_tdp_bl}]\nset_property LOC RAMB36_X4Y34 [get_cells {*/pcie_7x_i/pcie_top_i/pcie_7x_i/pcie_bram_top/pcie_brams_rx/brams[2].ram/use_tdp.ramb36/genblk*.bram36_tdp_bl.bram36_tdp_bl}]\nset_property LOC RAMB36_X4Y33 [get_cells {*/pcie_7x_i/pcie_top_i/pcie_7x_i/pcie_bram_top/pcie_brams_rx/brams[1].ram/use_tdp.ramb36/genblk*.bram36_tdp_bl.bram36_tdp_bl}]\nset_property LOC RAMB36_X4Y32 [get_cells {*/pcie_7x_i/pcie_top_i/pcie_7x_i/pcie_bram_top/pcie_brams_rx/brams[0].ram/use_tdp.ramb36/genblk*.bram36_tdp_bl.bram36_tdp_bl}]\nset_property LOC RAMB36_X4Y31 [get_cells {*/pcie_7x_i/pcie_top_i/pcie_7x_i/pcie_bram_top/pcie_brams_tx/brams[0].ram/use_tdp.ramb36/genblk*.bram36_tdp_bl.bram36_tdp_bl}]\nset_property LOC RAMB36_X4Y30 [get_cells {*/pcie_7x_i/pcie_top_i/pcie_7x_i/pcie_bram_top/pcie_brams_tx/brams[1].ram/use_tdp.ramb36/genblk*.bram36_tdp_bl.bram36_tdp_bl}]\nset_property LOC RAMB36_X4Y29 [get_cells {*/pcie_7x_i/pcie_top_i/pcie_7x_i/pcie_bram_top/pcie_brams_tx/brams[2].ram/use_tdp.ramb36/genblk*.bram36_tdp_bl.bram36_tdp_bl}]\nset_property LOC RAMB36_X4Y28 [get_cells {*/pcie_7x_i/pcie_top_i/pcie_7x_i/pcie_bram_top/pcie_brams_tx/brams[3].ram/use_tdp.ramb36/genblk*.bram36_tdp_bl.bram36_tdp_bl}]\n\n######################################################################################################\n# AREA GROUPS\n######################################################################################################\n## startgroup\n## create_pblock pblock_pcie0\n## resize_pblock pblock_pcie0 -add {SLICE_X70Y139:SLICE_X147Y299 DSP48_X3Y56:DSP48_X5Y119 RAMB18_X3Y56:RAMB18_X6Y119 RAMB36_X3Y28:RAMB36_X6Y59}\n## add_cells_to_pblock pblock_pcie0 [get_cells [list *_pcie_*]]\n## add_cells_to_pblock pblock_pcie0 [get_cells [list *_outFifo*]]\n## add_cells_to_pblock pblock_pcie0 [get_cells [list *_inFifo*]]\n## add_cells_to_pblock pblock_pcie0 [get_cells [list *_fifoTxData_*]]\n## add_cells_to_pblock pblock_pcie0 [get_cells [list *_fifoRxData_*]]\n## add_cells_to_pblock pblock_pcie0 [get_cells [list *\\/pbb*]]\n## add_cells_to_pblock pblock_pcie0 [get_cells [list *fS1OutPort*]]\n## add_cells_to_pblock pblock_pcie0 [get_cells [list *fS1MsgOut*]]\n## add_cells_to_pblock pblock_pcie0 [get_cells [list *fS2MsgOut*]]\n## endgroup\n\n\n######################################################################################################\n# TIMING CONSTRAINTS\n######################################################################################################\n\n# # clocks\ncreate_clock -name bscan_refclk -period 20 [get_pins -hier -filter {NAME=~\"*pcieBscanBram_bscan/TCK\"}]\n\ncreate_clock -name pci_refclk -period 10 [get_pins *pci_clk_100mhz_buf/O]\ncreate_clock -name sys_clk -period 5 [get_pins *sys_clk_200mhz/O]\n\ncreate_clock -name pci_extclk -period 10 [get_pins *ep7/pcie_ep/inst/inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/gtx_channel.gtxe2_channel_i/TXOUTCLK]\n\n# # False Paths\n# set_false_path -from [get_ports { RST_N_pci_sys_reset_n }]\nset_false_path -through [get_pins -hierarchical {*pcie_block_i/PLPHYLNKUPN*}]\nset_false_path -through [get_pins -hierarchical {*pcie_block_i/PLRECEIVEDHOTRST*}]\n\n#set_false_path -through [get_nets {*/pcie_7x_i/inst/inst/gt_top_i/pipe_wrapper_i/user_resetdone*}]\nset_false_path -through [get_nets {*/pcie_7x_i/inst/inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].pipe_rate.pipe_rate_i/*}]\nset_false_path -through [get_nets {*/pcie_7x_i/inst/inst/gt_top_i/pipe_wrapper_i/pipe_lane[1].pipe_rate.pipe_rate_i/*}]\nset_false_path -through [get_nets {*/pcie_7x_i/inst/inst/gt_top_i/pipe_wrapper_i/pipe_lane[2].pipe_rate.pipe_rate_i/*}]\nset_false_path -through [get_nets {*/pcie_7x_i/inst/inst/gt_top_i/pipe_wrapper_i/pipe_lane[3].pipe_rate.pipe_rate_i/*}]\nset_false_path -through [get_nets {*/pcie_7x_i/inst/inst/gt_top_i/pipe_wrapper_i/pipe_lane[4].pipe_rate.pipe_rate_i/*}]\nset_false_path -through [get_nets {*/pcie_7x_i/inst/inst/gt_top_i/pipe_wrapper_i/pipe_lane[5].pipe_rate.pipe_rate_i/*}]\nset_false_path -through [get_nets {*/pcie_7x_i/inst/inst/gt_top_i/pipe_wrapper_i/pipe_lane[6].pipe_rate.pipe_rate_i/*}]\nset_false_path -through [get_nets {*/pcie_7x_i/inst/inst/gt_top_i/pipe_wrapper_i/pipe_lane[7].pipe_rate.pipe_rate_i/*}]\n\nset_false_path -through [get_cells {*/pcie_7x_i/inst/inst/gt_top_i/pipe_wrapper_i/pipe_reset.pipe_reset_i/cpllreset_reg*}]\n\nset_false_path -through [get_nets {*/ext_clk.pipe_clock_i/pclk_sel*}]\n\nset_case_analysis 1 [get_pins {*/ext_clk.pipe_clock_i/pclk_i1_bufgctrl.pclk_i1/S0}] \nset_case_analysis 0 [get_pins {*/ext_clk.pipe_clock_i/pclk_i1_bufgctrl.pclk_i1/S1}] \n\nset_clock_groups -name ___clk_groups_generated_0_1_0_0_0 -physically_exclusive -group [get_clocks clk_125mhz] -group [get_clocks clk_250mhz]\n\nset_clock_groups -name async_sysclk_coreclk -asynchronous -group [get_clocks -include_generated_clocks sys_clk] -group [get_clocks -include_generated_clocks user_clk] -group [get_clocks -include_generated_clocks pci_refclk]\n\nset_max_delay -from [get_clocks noc_clk] -to [get_clocks clk_userclk2] 8.000 -datapath_only\nset_max_delay -from [get_clocks clk_userclk2] -to [get_clocks noc_clk] 8.000 -datapath_only\nset_max_delay -from [get_clocks cclock] -to [get_clocks core_clock] 20.000 -datapath_only\nset_max_delay -from [get_clocks uclock] -to [get_clocks core_clock] 20.000 -datapath_only\nset_max_delay -from [get_clocks core_clock] -to [get_clocks cclock] 20.000 -datapath_only\nset_max_delay -from [get_clocks core_clock] -to [get_clocks uclock] 20.000 -datapath_only\n"
  },
  {
    "path": "constraints/xilinx/kc705-ddr3.prj",
    "content": "<?xml version='1.0' encoding='UTF-8'?>\n<!-- IMPORTANT: This is an internal file that has been generated by the MIG software. Any direct editing or changes made to this file may result in unpredictable behavior or data corruption. It is strongly advised that users do not edit the contents of this file. Re-run the MIG GUI with the required settings if any of the options provided below need to be altered. -->\n<Project NoOfControllers=\"1\" >\n    <ModuleName>ddr3</ModuleName>\n    <dci_inouts_inputs>1</dci_inouts_inputs>\n    <dci_inputs>1</dci_inputs>\n    <Debug_En>OFF</Debug_En>\n    <DataDepth_En>1024</DataDepth_En>\n    <LowPower_En>ON</LowPower_En>\n    <XADC_En>Enabled</XADC_En>\n    <TargetFPGA>xc7k325t-2ffg900/-2</TargetFPGA>\n    <Version>2.0</Version>\n    <SystemClock>No Buffer</SystemClock>\n    <ReferenceClock>No Buffer</ReferenceClock>\n    <SysResetPolarity>ACTIVE LOW</SysResetPolarity>\n    <BankSelectionFlag>FALSE</BankSelectionFlag>\n    <InternalVref>0</InternalVref>\n    <dci_hr_inouts_inputs>50 Ohms</dci_hr_inouts_inputs>\n    <dci_cascade>0</dci_cascade>\n    <Controller number=\"0\" >\n        <MemoryDevice>DDR3_SDRAM/SODIMMs/MT8JTF12864HZ-1G6</MemoryDevice>\n        <TimePeriod>1250</TimePeriod>\n        <VccAuxIO>2.0V</VccAuxIO>\n        <PHYRatio>4:1</PHYRatio>\n        <InputClkFreq>800</InputClkFreq>\n        <UIExtraClocks>0</UIExtraClocks>\n        <MMCMClkOut0> 1.000</MMCMClkOut0>\n        <MMCMClkOut1>1</MMCMClkOut1>\n        <MMCMClkOut2>1</MMCMClkOut2>\n        <MMCMClkOut3>1</MMCMClkOut3>\n        <MMCMClkOut4>1</MMCMClkOut4>\n        <DataWidth>64</DataWidth>\n        <DeepMemory>1</DeepMemory>\n        <DataMask>1</DataMask>\n        <ECC>Disabled</ECC>\n        <Ordering>Normal</Ordering>\n        <CustomPart>FALSE</CustomPart>\n        <NewPartName></NewPartName>\n        <RowAddress>14</RowAddress>\n        <ColAddress>10</ColAddress>\n        <BankAddress>3</BankAddress>\n        <MemoryVoltage>1.5V</MemoryVoltage>\n        <UserMemoryAddressMap>BANK_ROW_COLUMN</UserMemoryAddressMap>\n        <PinSelection>\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15\" PADName=\"AH12\" SLEW=\"\" name=\"ddr3_addr[0]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15\" PADName=\"AF13\" SLEW=\"\" name=\"ddr3_addr[10]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15\" PADName=\"AE13\" SLEW=\"\" name=\"ddr3_addr[11]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15\" PADName=\"AJ11\" SLEW=\"\" name=\"ddr3_addr[12]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15\" PADName=\"AH11\" SLEW=\"\" name=\"ddr3_addr[13]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15\" PADName=\"AG13\" SLEW=\"\" name=\"ddr3_addr[1]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15\" PADName=\"AG12\" SLEW=\"\" name=\"ddr3_addr[2]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15\" PADName=\"AF12\" SLEW=\"\" name=\"ddr3_addr[3]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15\" PADName=\"AJ12\" SLEW=\"\" name=\"ddr3_addr[4]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15\" PADName=\"AJ13\" SLEW=\"\" name=\"ddr3_addr[5]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15\" PADName=\"AJ14\" SLEW=\"\" name=\"ddr3_addr[6]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15\" PADName=\"AH14\" SLEW=\"\" name=\"ddr3_addr[7]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15\" PADName=\"AK13\" SLEW=\"\" name=\"ddr3_addr[8]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15\" PADName=\"AK14\" SLEW=\"\" name=\"ddr3_addr[9]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15\" PADName=\"AH9\" SLEW=\"\" name=\"ddr3_ba[0]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15\" PADName=\"AG9\" SLEW=\"\" name=\"ddr3_ba[1]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15\" PADName=\"AK9\" SLEW=\"\" name=\"ddr3_ba[2]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15\" PADName=\"AC11\" SLEW=\"\" name=\"ddr3_cas_n\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"DIFF_SSTL15\" PADName=\"AH10\" SLEW=\"\" name=\"ddr3_ck_n[0]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"DIFF_SSTL15\" PADName=\"AG10\" SLEW=\"\" name=\"ddr3_ck_p[0]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15\" PADName=\"AF10\" SLEW=\"\" name=\"ddr3_cke[0]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15\" PADName=\"AC12\" SLEW=\"\" name=\"ddr3_cs_n[0]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15\" PADName=\"Y16\" SLEW=\"\" name=\"ddr3_dm[0]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15\" PADName=\"AB17\" SLEW=\"\" name=\"ddr3_dm[1]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15\" PADName=\"AF17\" SLEW=\"\" name=\"ddr3_dm[2]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15\" PADName=\"AE16\" SLEW=\"\" name=\"ddr3_dm[3]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15\" PADName=\"AK5\" SLEW=\"\" name=\"ddr3_dm[4]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15\" PADName=\"AJ3\" SLEW=\"\" name=\"ddr3_dm[5]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15\" PADName=\"AF6\" SLEW=\"\" name=\"ddr3_dm[6]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15\" PADName=\"AC7\" SLEW=\"\" name=\"ddr3_dm[7]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"AA15\" SLEW=\"\" name=\"ddr3_dq[0]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"AC19\" SLEW=\"\" name=\"ddr3_dq[10]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"AD17\" SLEW=\"\" name=\"ddr3_dq[11]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"AA18\" SLEW=\"\" name=\"ddr3_dq[12]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"AB18\" SLEW=\"\" name=\"ddr3_dq[13]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"AE18\" SLEW=\"\" name=\"ddr3_dq[14]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"AD18\" SLEW=\"\" name=\"ddr3_dq[15]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"AG19\" SLEW=\"\" name=\"ddr3_dq[16]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"AK19\" SLEW=\"\" name=\"ddr3_dq[17]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"AG18\" SLEW=\"\" name=\"ddr3_dq[18]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"AF18\" SLEW=\"\" name=\"ddr3_dq[19]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"AA16\" SLEW=\"\" name=\"ddr3_dq[1]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"AH19\" SLEW=\"\" name=\"ddr3_dq[20]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"AJ19\" SLEW=\"\" name=\"ddr3_dq[21]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"AE19\" SLEW=\"\" name=\"ddr3_dq[22]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"AD19\" SLEW=\"\" name=\"ddr3_dq[23]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"AK16\" SLEW=\"\" name=\"ddr3_dq[24]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"AJ17\" SLEW=\"\" name=\"ddr3_dq[25]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"AG15\" SLEW=\"\" name=\"ddr3_dq[26]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"AF15\" SLEW=\"\" name=\"ddr3_dq[27]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"AH17\" SLEW=\"\" name=\"ddr3_dq[28]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"AG14\" SLEW=\"\" name=\"ddr3_dq[29]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"AC14\" SLEW=\"\" name=\"ddr3_dq[2]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"AH15\" SLEW=\"\" name=\"ddr3_dq[30]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"AK15\" SLEW=\"\" name=\"ddr3_dq[31]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"AK8\" SLEW=\"\" name=\"ddr3_dq[32]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"AK6\" SLEW=\"\" name=\"ddr3_dq[33]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"AG7\" SLEW=\"\" name=\"ddr3_dq[34]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"AF7\" SLEW=\"\" name=\"ddr3_dq[35]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"AF8\" SLEW=\"\" name=\"ddr3_dq[36]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"AK4\" SLEW=\"\" name=\"ddr3_dq[37]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"AJ8\" SLEW=\"\" name=\"ddr3_dq[38]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"AJ6\" SLEW=\"\" name=\"ddr3_dq[39]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"AD14\" SLEW=\"\" name=\"ddr3_dq[3]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"AH5\" SLEW=\"\" name=\"ddr3_dq[40]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"AH6\" SLEW=\"\" name=\"ddr3_dq[41]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"AJ2\" SLEW=\"\" name=\"ddr3_dq[42]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"AH2\" SLEW=\"\" name=\"ddr3_dq[43]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"AH4\" SLEW=\"\" name=\"ddr3_dq[44]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"AJ4\" SLEW=\"\" name=\"ddr3_dq[45]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"AK1\" SLEW=\"\" name=\"ddr3_dq[46]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"AJ1\" SLEW=\"\" name=\"ddr3_dq[47]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"AF1\" SLEW=\"\" name=\"ddr3_dq[48]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"AF2\" SLEW=\"\" name=\"ddr3_dq[49]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"AA17\" SLEW=\"\" name=\"ddr3_dq[4]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"AE4\" SLEW=\"\" name=\"ddr3_dq[50]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"AE3\" SLEW=\"\" name=\"ddr3_dq[51]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"AF3\" SLEW=\"\" name=\"ddr3_dq[52]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"AF5\" SLEW=\"\" name=\"ddr3_dq[53]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"AE1\" SLEW=\"\" name=\"ddr3_dq[54]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"AE5\" SLEW=\"\" name=\"ddr3_dq[55]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"AC1\" SLEW=\"\" name=\"ddr3_dq[56]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"AD3\" SLEW=\"\" name=\"ddr3_dq[57]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"AC4\" SLEW=\"\" name=\"ddr3_dq[58]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"AC5\" SLEW=\"\" name=\"ddr3_dq[59]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"AB15\" SLEW=\"\" name=\"ddr3_dq[5]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"AE6\" SLEW=\"\" name=\"ddr3_dq[60]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"AD6\" SLEW=\"\" name=\"ddr3_dq[61]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"AC2\" SLEW=\"\" name=\"ddr3_dq[62]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"AD4\" SLEW=\"\" name=\"ddr3_dq[63]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"AE15\" SLEW=\"\" name=\"ddr3_dq[6]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"Y15\" SLEW=\"\" name=\"ddr3_dq[7]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"AB19\" SLEW=\"\" name=\"ddr3_dq[8]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"AD16\" SLEW=\"\" name=\"ddr3_dq[9]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"DIFF_SSTL15_T_DCI\" PADName=\"AC15\" SLEW=\"\" name=\"ddr3_dqs_n[0]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"DIFF_SSTL15_T_DCI\" PADName=\"Y18\" SLEW=\"\" name=\"ddr3_dqs_n[1]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"DIFF_SSTL15_T_DCI\" PADName=\"AK18\" SLEW=\"\" name=\"ddr3_dqs_n[2]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"DIFF_SSTL15_T_DCI\" PADName=\"AJ16\" SLEW=\"\" name=\"ddr3_dqs_n[3]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"DIFF_SSTL15_T_DCI\" PADName=\"AJ7\" SLEW=\"\" name=\"ddr3_dqs_n[4]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"DIFF_SSTL15_T_DCI\" PADName=\"AH1\" SLEW=\"\" name=\"ddr3_dqs_n[5]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"DIFF_SSTL15_T_DCI\" PADName=\"AG3\" SLEW=\"\" name=\"ddr3_dqs_n[6]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"DIFF_SSTL15_T_DCI\" PADName=\"AD1\" SLEW=\"\" name=\"ddr3_dqs_n[7]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"DIFF_SSTL15_T_DCI\" PADName=\"AC16\" SLEW=\"\" name=\"ddr3_dqs_p[0]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"DIFF_SSTL15_T_DCI\" PADName=\"Y19\" SLEW=\"\" name=\"ddr3_dqs_p[1]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"DIFF_SSTL15_T_DCI\" PADName=\"AJ18\" SLEW=\"\" name=\"ddr3_dqs_p[2]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"DIFF_SSTL15_T_DCI\" PADName=\"AH16\" SLEW=\"\" name=\"ddr3_dqs_p[3]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"DIFF_SSTL15_T_DCI\" PADName=\"AH7\" SLEW=\"\" name=\"ddr3_dqs_p[4]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"DIFF_SSTL15_T_DCI\" PADName=\"AH1\" SLEW=\"\" name=\"ddr3_dqs_p[5]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"DIFF_SSTL15_T_DCI\" PADName=\"AG4\" SLEW=\"\" name=\"ddr3_dqs_p[6]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"DIFF_SSTL15_T_DCI\" PADName=\"AD2\" SLEW=\"\" name=\"ddr3_dqs_p[7]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15\" PADName=\"AD8\" SLEW=\"\" name=\"ddr3_odt[0]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15\" PADName=\"AD9\" SLEW=\"\" name=\"ddr3_ras_n\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"LVCMOS15\" PADName=\"AK3\" SLEW=\"\" name=\"ddr3_reset_n\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15\" PADName=\"AE9\" SLEW=\"\" name=\"ddr3_we_n\" IN_TERM=\"\" />\n        </PinSelection>\n        <System_Control>\n            <Pin PADName=\" connect\" Bank=\"Select Bank\" name=\"sys_rst\" />\n            <Pin PADName=\" connect\" Bank=\"Select Bank\" name=\"init_calib_complete\" />\n            <Pin PADName=\" connect\" Bank=\"Select Bank\" name=\"tg_compare_error\" />\n        </System_Control>\n        <TimingParameters>\n            <Parameters twtr=\"7.5\" trrd=\"6\" trefi=\"7.8\" tfaw=\"30\" trtp=\"7.5\" tcke=\"5\" trfc=\"110\" trp=\"13.125\" tras=\"35\" trcd=\"13.125\" />\n        </TimingParameters>\n        <mrBurstLength name=\"Burst Length\" >8 - Fixed</mrBurstLength>\n        <mrBurstType name=\"Read Burst Type and Length\" >Sequential</mrBurstType>\n        <mrCasLatency name=\"CAS Latency\" >11</mrCasLatency>\n        <mrMode name=\"Mode\" >Normal</mrMode>\n        <mrDllReset name=\"DLL Reset\" >No</mrDllReset>\n        <mrPdMode name=\"DLL control for precharge PD\" >Slow Exit</mrPdMode>\n        <emrDllEnable name=\"DLL Enable\" >Enable</emrDllEnable>\n        <emrOutputDriveStrength name=\"Output Driver Impedance Control\" >RZQ/7</emrOutputDriveStrength>\n        <emrMirrorSelection name=\"Address Mirroring\" >Disable</emrMirrorSelection>\n        <emrCSSelection name=\"Controller Chip Select Pin\" >Enable</emrCSSelection>\n        <emrRTT name=\"RTT (nominal) - On Die Termination (ODT)\" >RZQ/4</emrRTT>\n        <emrPosted name=\"Additive Latency (AL)\" >0</emrPosted>\n        <emrOCD name=\"Write Leveling Enable\" >Disabled</emrOCD>\n        <emrDQS name=\"TDQS enable\" >Enabled</emrDQS>\n        <emrRDQS name=\"Qoff\" >Output Buffer Enabled</emrRDQS>\n        <mr2PartialArraySelfRefresh name=\"Partial-Array Self Refresh\" >Full Array</mr2PartialArraySelfRefresh>\n        <mr2CasWriteLatency name=\"CAS write latency\" >8</mr2CasWriteLatency>\n        <mr2AutoSelfRefresh name=\"Auto Self Refresh\" >Enabled</mr2AutoSelfRefresh>\n        <mr2SelfRefreshTempRange name=\"High Temparature Self Refresh Rate\" >Normal</mr2SelfRefreshTempRange>\n        <mr2RTTWR name=\"RTT_WR - Dynamic On Die Termination (ODT)\" >Dynamic ODT off</mr2RTTWR>\n        <PortInterface>NATIVE</PortInterface>\n    </Controller>\n\n</Project>\n"
  },
  {
    "path": "constraints/xilinx/kc705.xdc",
    "content": "######################################################################################################\n##  File name :       default.xdc\n##\n##  Details :     Constraints file\n##                    FPGA family:       kintex7\n##                    FPGA:              xc7k325t-2ffg900\n##                    Speedgrade:        -2\n##\n######################################################################################################\n\n######################################################################################################\n# PIN ASSIGNMENTS\n######################################################################################################\nset_property LOC U8   [get_ports { CLK_pci_sys_clk_p }]\nset_property LOC U7   [get_ports { CLK_pci_sys_clk_n }]\nset_property LOC G25  [get_ports { RST_N_pci_sys_reset_n }]\nset_property LOC AD12 [get_ports { CLK_sys_clk_p }]\nset_property LOC AD11 [get_ports { CLK_sys_clk_n }]\n#set_property LOC K28  [get_ports { CLK_user_clk_p }]\n#set_property LOC K29  [get_ports { CLK_user_clk_n }]\nset_property LOC G25  [get_ports { RST_cpu_reset }]\n\nset_property LOC M6   [get_ports { PCIE_rxp_v[0] }]\nset_property LOC P6   [get_ports { PCIE_rxp_v[1] }]\nset_property LOC R4   [get_ports { PCIE_rxp_v[2] }]\nset_property LOC T6   [get_ports { PCIE_rxp_v[3] }]\nset_property LOC V6   [get_ports { PCIE_rxp_v[4] }]\nset_property LOC W4   [get_ports { PCIE_rxp_v[5] }]\nset_property LOC Y6   [get_ports { PCIE_rxp_v[6] }]\nset_property LOC AA4  [get_ports { PCIE_rxp_v[7] }]\n\nset_property LOC M5   [get_ports { PCIE_rxn_v[0] }]\nset_property LOC P5   [get_ports { PCIE_rxn_v[1] }]\nset_property LOC R3   [get_ports { PCIE_rxn_v[2] }]\nset_property LOC T5   [get_ports { PCIE_rxn_v[3] }]\nset_property LOC V5   [get_ports { PCIE_rxn_v[4] }]\nset_property LOC W3   [get_ports { PCIE_rxn_v[5] }]\nset_property LOC Y5   [get_ports { PCIE_rxn_v[6] }]\nset_property LOC AA3  [get_ports { PCIE_rxn_v[7] }]\n\nset_property LOC L4   [get_ports { PCIE_txp[0] }]\nset_property LOC M2   [get_ports { PCIE_txp[1] }]\nset_property LOC N4   [get_ports { PCIE_txp[2] }]\nset_property LOC P2   [get_ports { PCIE_txp[3] }]\nset_property LOC T2   [get_ports { PCIE_txp[4] }]\nset_property LOC U4   [get_ports { PCIE_txp[5] }]\nset_property LOC V2   [get_ports { PCIE_txp[6] }]\nset_property LOC Y2   [get_ports { PCIE_txp[7] }]\n\nset_property LOC L3   [get_ports { PCIE_txn[0] }]\nset_property LOC M1   [get_ports { PCIE_txn[1] }]\nset_property LOC N3   [get_ports { PCIE_txn[2] }]\nset_property LOC P1   [get_ports { PCIE_txn[3] }]\nset_property LOC T1   [get_ports { PCIE_txn[4] }]\nset_property LOC U3   [get_ports { PCIE_txn[5] }]\nset_property LOC V1   [get_ports { PCIE_txn[6] }]\nset_property LOC Y1   [get_ports { PCIE_txn[7] }]\n\n######################################################################################################\n# I/O STANDARDS\n######################################################################################################\nset_property IOSTANDARD DIFF_SSTL15 [get_ports { CLK_pci_sys_clk_* }]\nset_property IOSTANDARD DIFF_SSTL15 [get_ports { CLK_sys_clk_* }]\n#set_property IOSTANDARD DIFF_SSTL15 [get_ports { CLK_user_clk_* }]\nset_property IOSTANDARD LVCMOS25    [get_ports { RST_N_pci_sys_reset_n }]\nset_property PULLUP     true        [get_ports { RST_N_pci_sys_reset_n }]\nset_property IOSTANDARD LVCMOS15    [get_ports { RST_cpu_reset }]\n\n######################################################################################################\n# CELL LOCATIONS\n######################################################################################################\n#\n# SYS clock 100 MHz (input) signal. The sys_clk_p and sys_clk_n\n# signals are the PCI Express reference clock. Virtex-7 GT\n# Transceiver architecture requires the use of a dedicated clock\n# resources (FPGA input pins) associated with each GT Transceiver.\n# To use these pins an IBUFDS primitive (refclk_ibuf) is\n# instantiated in user's design.\n# Please refer to the Virtex-7 GT Transceiver User Guide\n# (UG) for guidelines regarding clock resource selection.\n#\nset_property LOC IBUFDS_GTE2_X0Y1  [get_cells { *pci_clk_100mhz_buf }]\n\n\n######################################################################################################\n# TIMING CONSTRAINTS\n######################################################################################################\n\n## in pcie-clocks.xdc\n\n# ignore this timing violation\nset_false_path -from [get_pins host_ep7/pclk_sel_reg/C]\n"
  },
  {
    "path": "constraints/xilinx/kc705g2.xdc",
    "content": "######################################################################################################\n##  File name :       default.xdc\n##\n##  Details :     Constraints file\n##                    FPGA family:       kintex7\n##                    FPGA:              xc7k325t-2ffg900\n##                    Speedgrade:        -2\n##\n######################################################################################################\n\n######################################################################################################\n# PIN ASSIGNMENTS\n######################################################################################################\nset_property LOC U8   [get_ports { CLK_pci_sys_clk_p }]\nset_property LOC U7   [get_ports { CLK_pci_sys_clk_n }]\nset_property LOC G25  [get_ports { RST_N_pci_sys_reset_n }]\nset_property LOC AD12 [get_ports { CLK_sys_clk_p }]\nset_property LOC AD11 [get_ports { CLK_sys_clk_n }]\n#set_property LOC K28  [get_ports { CLK_user_clk_p }]\n#set_property LOC K29  [get_ports { CLK_user_clk_n }]\n\nset_property LOC M6   [get_ports { PCIE_rxp_v[0] }]\nset_property LOC P6   [get_ports { PCIE_rxp_v[1] }]\nset_property LOC R4   [get_ports { PCIE_rxp_v[2] }]\nset_property LOC T6   [get_ports { PCIE_rxp_v[3] }]\nset_property LOC V6   [get_ports { PCIE_rxp_v[4] }]\nset_property LOC W4   [get_ports { PCIE_rxp_v[5] }]\nset_property LOC Y6   [get_ports { PCIE_rxp_v[6] }]\nset_property LOC AA4  [get_ports { PCIE_rxp_v[7] }]\n\nset_property LOC M5   [get_ports { PCIE_rxn_v[0] }]\nset_property LOC P5   [get_ports { PCIE_rxn_v[1] }]\nset_property LOC R3   [get_ports { PCIE_rxn_v[2] }]\nset_property LOC T5   [get_ports { PCIE_rxn_v[3] }]\nset_property LOC V5   [get_ports { PCIE_rxn_v[4] }]\nset_property LOC W3   [get_ports { PCIE_rxn_v[5] }]\nset_property LOC Y5   [get_ports { PCIE_rxn_v[6] }]\nset_property LOC AA3  [get_ports { PCIE_rxn_v[7] }]\n\nset_property LOC L4   [get_ports { PCIE_txp[0] }]\nset_property LOC M2   [get_ports { PCIE_txp[1] }]\nset_property LOC N4   [get_ports { PCIE_txp[2] }]\nset_property LOC P2   [get_ports { PCIE_txp[3] }]\nset_property LOC T2   [get_ports { PCIE_txp[4] }]\nset_property LOC U4   [get_ports { PCIE_txp[5] }]\nset_property LOC V2   [get_ports { PCIE_txp[6] }]\nset_property LOC Y2   [get_ports { PCIE_txp[7] }]\n\nset_property LOC L3   [get_ports { PCIE_txn[0] }]\nset_property LOC M1   [get_ports { PCIE_txn[1] }]\nset_property LOC N3   [get_ports { PCIE_txn[2] }]\nset_property LOC P1   [get_ports { PCIE_txn[3] }]\nset_property LOC T1   [get_ports { PCIE_txn[4] }]\nset_property LOC U3   [get_ports { PCIE_txn[5] }]\nset_property LOC V1   [get_ports { PCIE_txn[6] }]\nset_property LOC Y1   [get_ports { PCIE_txn[7] }]\n\n######################################################################################################\n# I/O STANDARDS\n######################################################################################################\nset_property IOSTANDARD DIFF_SSTL15 [get_ports { CLK_pci_sys_clk_* }]\nset_property IOSTANDARD DIFF_SSTL15 [get_ports { CLK_sys_clk_* }]\n#set_property IOSTANDARD DIFF_SSTL15 [get_ports { CLK_user_clk_* }]\nset_property IOSTANDARD LVCMOS25    [get_ports { RST_N_pci_sys_reset_n }]\nset_property PULLUP     true        [get_ports { RST_N_pci_sys_reset_n }]\n\n######################################################################################################\n# CELL LOCATIONS\n######################################################################################################\n#\n# SYS clock 100 MHz (input) signal. The sys_clk_p and sys_clk_n\n# signals are the PCI Express reference clock. Virtex-7 GT\n# Transceiver architecture requires the use of a dedicated clock\n# resources (FPGA input pins) associated with each GT Transceiver.\n# To use these pins an IBUFDS primitive (refclk_ibuf) is\n# instantiated in user's design.\n# Please refer to the Virtex-7 GT Transceiver User Guide\n# (UG) for guidelines regarding clock resource selection.\n#\nset_property LOC IBUFDS_GTE2_X0Y1  [get_cells { *pci_clk_100mhz_buf }]\n\n######################################################################################################\n# TIMING CONSTRAINTS\n######################################################################################################\n\n## in pcie-clocks.xdc\n"
  },
  {
    "path": "constraints/xilinx/kcu105.xdc",
    "content": "######################################################################################################\n##  File name :       default.xdc\n##\n##  Details :     Constraints file\n##                    FPGA family:       virtex7\n##                    FPGA:              xc7vx690t-3ffg1761C\n##                    Speedgrade:        -3\n##\n######################################################################################################\n\n##The following two properties should be set for every design\nset_property CFGBVS GND [current_design]\nset_property CONFIG_VOLTAGE 1.8 [current_design]\n\n######################################################################################################\n# PIN ASSIGNMENTS\n######################################################################################################\nset_property LOC AB6  [get_ports { CLK_pci_sys_clk_n }]\nset_property LOC AB5  [get_ports { CLK_pci_sys_clk_p }]\nset_property LOC K225 [get_ports { RST_N_pci_sys_reset_n }]\nset_property LOC AK17  [get_ports { CLK_sys_clk_p }] // 300MHz SYSCLK\nset_property LOC AK16 [get_ports { CLK_sys_clk_n }]  // 300MHz SYSCLK\n\n######################################################################################################\n# I/O STANDARDS\n######################################################################################################\nset_property IOSTANDARD LVCMOS18    [get_ports { leds_leds[*] }]\nset_property IOSTANDARD DIFF_SSTL12 [get_ports { CLK_sys_clk_* }]\nset_property IOSTANDARD LVCMOS18    [get_ports { RST_N_pci_sys_reset_n }]\nset_property PULLUP     true        [get_ports { RST_N_pci_sys_reset_n }]\n\n######################################################################################################\n# TIMING CONSTRAINTS\n######################################################################################################\n\n## in pcie-clocks.xdc\n\n"
  },
  {
    "path": "constraints/xilinx/miniitx100-axiddr3.prj",
    "content": "<?xml version='1.0' encoding='UTF-8'?>\n<!-- IMPORTANT: This is an internal file that has been generated by the MIG software. Any direct editing or changes made to this file may result in unpredictable behavior or data corruption. It is strongly advised that users do not edit the contents of this file. Re-run the MIG GUI with the required settings if any of the options provided below need to be altered. -->\n<Project NoOfControllers=\"1\" >\n    <ModuleName>mig_7series_0</ModuleName>\n    <dci_inouts_inputs>1</dci_inouts_inputs>\n    <dci_inputs>1</dci_inputs>\n    <Debug_En>OFF</Debug_En>\n    <DataDepth_En>1024</DataDepth_En>\n    <LowPower_En>ON</LowPower_En>\n    <XADC_En>Enabled</XADC_En>\n    <TargetFPGA>xc7z100-ffg900/-2</TargetFPGA>\n    <Version>4.0</Version>\n    <SystemClock>No Buffer</SystemClock>\n    <ReferenceClock>Use System Clock</ReferenceClock>\n    <SysResetPolarity>ACTIVE LOW</SysResetPolarity>\n    <BankSelectionFlag>FALSE</BankSelectionFlag>\n    <InternalVref>0</InternalVref>\n    <dci_hr_inouts_inputs>50 Ohms</dci_hr_inouts_inputs>\n    <dci_cascade>0</dci_cascade>\n    <FPGADevice>\n        <selected>7z/xc7z045-ffg900</selected>\n    </FPGADevice>\n    <Controller number=\"0\" >\n        <MemoryDevice>DDR3_SDRAM/Components/MT41K256M16XX-125</MemoryDevice>\n        <TimePeriod>1250</TimePeriod>\n        <VccAuxIO>2.0V</VccAuxIO>\n        <PHYRatio>4:1</PHYRatio>\n        <InputClkFreq>200</InputClkFreq>\n        <UIExtraClocks>0</UIExtraClocks>\n        <MMCM_VCO>800</MMCM_VCO>\n        <MMCMClkOut0> 1.000</MMCMClkOut0>\n        <MMCMClkOut1>1</MMCMClkOut1>\n        <MMCMClkOut2>1</MMCMClkOut2>\n        <MMCMClkOut3>1</MMCMClkOut3>\n        <MMCMClkOut4>1</MMCMClkOut4>\n        <DataWidth>32</DataWidth>\n        <DeepMemory>1</DeepMemory>\n        <DataMask>1</DataMask>\n        <ECC>Disabled</ECC>\n        <Ordering>Normal</Ordering>\n        <CustomPart>FALSE</CustomPart>\n        <NewPartName></NewPartName>\n        <RowAddress>15</RowAddress>\n        <ColAddress>10</ColAddress>\n        <BankAddress>3</BankAddress>\n        <MemoryVoltage>1.5V</MemoryVoltage>\n        <UserMemoryAddressMap>BANK_ROW_COLUMN</UserMemoryAddressMap>\n        <PinSelection>\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15\" PADName=\"J8\" SLEW=\"\" name=\"ddr3_addr[0]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15\" PADName=\"H12\" SLEW=\"\" name=\"ddr3_addr[10]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15\" PADName=\"D11\" SLEW=\"\" name=\"ddr3_addr[11]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15\" PADName=\"E11\" SLEW=\"\" name=\"ddr3_addr[12]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15\" PADName=\"H11\" SLEW=\"\" name=\"ddr3_addr[13]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15\" PADName=\"J11\" SLEW=\"\" name=\"ddr3_addr[14]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15\" PADName=\"E8\" SLEW=\"\" name=\"ddr3_addr[1]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15\" PADName=\"F9\" SLEW=\"\" name=\"ddr3_addr[2]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15\" PADName=\"D8\" SLEW=\"\" name=\"ddr3_addr[3]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15\" PADName=\"D9\" SLEW=\"\" name=\"ddr3_addr[4]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15\" PADName=\"F10\" SLEW=\"\" name=\"ddr3_addr[5]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15\" PADName=\"G10\" SLEW=\"\" name=\"ddr3_addr[6]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15\" PADName=\"D10\" SLEW=\"\" name=\"ddr3_addr[7]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15\" PADName=\"E10\" SLEW=\"\" name=\"ddr3_addr[8]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15\" PADName=\"G11\" SLEW=\"\" name=\"ddr3_addr[9]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15\" PADName=\"F7\" SLEW=\"\" name=\"ddr3_ba[0]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15\" PADName=\"F8\" SLEW=\"\" name=\"ddr3_ba[1]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15\" PADName=\"H8\" SLEW=\"\" name=\"ddr3_ba[2]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15\" PADName=\"D6\" SLEW=\"\" name=\"ddr3_cas_n\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"DIFF_SSTL15\" PADName=\"K8\" SLEW=\"\" name=\"ddr3_ck_n[0]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"DIFF_SSTL15\" PADName=\"L8\" SLEW=\"\" name=\"ddr3_ck_p[0]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15\" PADName=\"L7\" SLEW=\"\" name=\"ddr3_cke[0]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15\" PADName=\"G7\" SLEW=\"\" name=\"ddr3_cs_n[0]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15\" PADName=\"J4\" SLEW=\"\" name=\"ddr3_dm[0]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15\" PADName=\"G2\" SLEW=\"\" name=\"ddr3_dm[1]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15\" PADName=\"D4\" SLEW=\"\" name=\"ddr3_dm[2]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15\" PADName=\"C4\" SLEW=\"\" name=\"ddr3_dm[3]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"J3\" SLEW=\"\" name=\"ddr3_dq[0]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"G6\" SLEW=\"\" name=\"ddr3_dq[10]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"H2\" SLEW=\"\" name=\"ddr3_dq[11]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"G1\" SLEW=\"\" name=\"ddr3_dq[12]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"H4\" SLEW=\"\" name=\"ddr3_dq[13]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"H3\" SLEW=\"\" name=\"ddr3_dq[14]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"G5\" SLEW=\"\" name=\"ddr3_dq[15]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"F5\" SLEW=\"\" name=\"ddr3_dq[16]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"E5\" SLEW=\"\" name=\"ddr3_dq[17]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"F4\" SLEW=\"\" name=\"ddr3_dq[18]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"F3\" SLEW=\"\" name=\"ddr3_dq[19]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"L1\" SLEW=\"\" name=\"ddr3_dq[1]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"D3\" SLEW=\"\" name=\"ddr3_dq[20]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"E3\" SLEW=\"\" name=\"ddr3_dq[21]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"E2\" SLEW=\"\" name=\"ddr3_dq[22]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"E1\" SLEW=\"\" name=\"ddr3_dq[23]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"B5\" SLEW=\"\" name=\"ddr3_dq[24]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"B4\" SLEW=\"\" name=\"ddr3_dq[25]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"C2\" SLEW=\"\" name=\"ddr3_dq[26]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"C1\" SLEW=\"\" name=\"ddr3_dq[27]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"B2\" SLEW=\"\" name=\"ddr3_dq[28]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"B1\" SLEW=\"\" name=\"ddr3_dq[29]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"K1\" SLEW=\"\" name=\"ddr3_dq[2]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"A3\" SLEW=\"\" name=\"ddr3_dq[30]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"A2\" SLEW=\"\" name=\"ddr3_dq[31]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"L3\" SLEW=\"\" name=\"ddr3_dq[3]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"L2\" SLEW=\"\" name=\"ddr3_dq[4]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"K5\" SLEW=\"\" name=\"ddr3_dq[5]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"J5\" SLEW=\"\" name=\"ddr3_dq[6]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"K6\" SLEW=\"\" name=\"ddr3_dq[7]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"F2\" SLEW=\"\" name=\"ddr3_dq[8]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"H6\" SLEW=\"\" name=\"ddr3_dq[9]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"DIFF_SSTL15_T_DCI\" PADName=\"K2\" SLEW=\"\" name=\"ddr3_dqs_n[0]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"DIFF_SSTL15_T_DCI\" PADName=\"H1\" SLEW=\"\" name=\"ddr3_dqs_n[1]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"DIFF_SSTL15_T_DCI\" PADName=\"D5\" SLEW=\"\" name=\"ddr3_dqs_n[2]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"DIFF_SSTL15_T_DCI\" PADName=\"A4\" SLEW=\"\" name=\"ddr3_dqs_n[3]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"DIFF_SSTL15_T_DCI\" PADName=\"K3\" SLEW=\"\" name=\"ddr3_dqs_p[0]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"DIFF_SSTL15_T_DCI\" PADName=\"J1\" SLEW=\"\" name=\"ddr3_dqs_p[1]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"DIFF_SSTL15_T_DCI\" PADName=\"E6\" SLEW=\"\" name=\"ddr3_dqs_p[2]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"DIFF_SSTL15_T_DCI\" PADName=\"A5\" SLEW=\"\" name=\"ddr3_dqs_p[3]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15\" PADName=\"J10\" SLEW=\"\" name=\"ddr3_odt[0]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15\" PADName=\"E7\" SLEW=\"\" name=\"ddr3_ras_n\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"LVCMOS15\" PADName=\"G4\" SLEW=\"\" name=\"ddr3_reset_n\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15\" PADName=\"H7\" SLEW=\"\" name=\"ddr3_we_n\" IN_TERM=\"\" />\n        </PinSelection>\n        <System_Control>\n            <Pin PADName=\"No connect\" Bank=\"Select Bank\" name=\"sys_rst\" />\n            <Pin PADName=\"No connect\" Bank=\"Select Bank\" name=\"init_calib_complete\" />\n            <Pin PADName=\"No connect\" Bank=\"Select Bank\" name=\"tg_compare_error\" />\n        </System_Control>\n        <TimingParameters>\n            <Parameters twtr=\"7.5\" trrd=\"7.5\" trefi=\"7.8\" tfaw=\"40\" trtp=\"7.5\" tcke=\"5\" trfc=\"260\" trp=\"13.75\" tras=\"35\" trcd=\"13.75\" />\n        </TimingParameters>\n        <mrBurstLength name=\"Burst Length\" >8 - Fixed</mrBurstLength>\n        <mrBurstType name=\"Read Burst Type and Length\" >Sequential</mrBurstType>\n        <mrCasLatency name=\"CAS Latency\" >11</mrCasLatency>\n        <mrMode name=\"Mode\" >Normal</mrMode>\n        <mrDllReset name=\"DLL Reset\" >No</mrDllReset>\n        <mrPdMode name=\"DLL control for precharge PD\" >Slow Exit</mrPdMode>\n        <emrDllEnable name=\"DLL Enable\" >Enable</emrDllEnable>\n        <emrOutputDriveStrength name=\"Output Driver Impedance Control\" >RZQ/7</emrOutputDriveStrength>\n        <emrMirrorSelection name=\"Address Mirroring\" >Disable</emrMirrorSelection>\n        <emrCSSelection name=\"Controller Chip Select Pin\" >Enable</emrCSSelection>\n        <emrRTT name=\"RTT (nominal) - On Die Termination (ODT)\" >RZQ/4</emrRTT>\n        <emrPosted name=\"Additive Latency (AL)\" >0</emrPosted>\n        <emrOCD name=\"Write Leveling Enable\" >Disabled</emrOCD>\n        <emrDQS name=\"TDQS enable\" >Enabled</emrDQS>\n        <emrRDQS name=\"Qoff\" >Output Buffer Enabled</emrRDQS>\n        <mr2PartialArraySelfRefresh name=\"Partial-Array Self Refresh\" >Full Array</mr2PartialArraySelfRefresh>\n        <mr2CasWriteLatency name=\"CAS write latency\" >8</mr2CasWriteLatency>\n        <mr2AutoSelfRefresh name=\"Auto Self Refresh\" >Enabled</mr2AutoSelfRefresh>\n        <mr2SelfRefreshTempRange name=\"High Temparature Self Refresh Rate\" >Normal</mr2SelfRefreshTempRange>\n        <mr2RTTWR name=\"RTT_WR - Dynamic On Die Termination (ODT)\" >Dynamic ODT off</mr2RTTWR>\n        <PortInterface>AXI</PortInterface>\n        <AXIParameters>\n            <C0_C_RD_WR_ARB_ALGORITHM>RD_PRI_REG</C0_C_RD_WR_ARB_ALGORITHM>\n            <C0_S_AXI_ADDR_WIDTH>30</C0_S_AXI_ADDR_WIDTH>\n            <C0_S_AXI_DATA_WIDTH>256</C0_S_AXI_DATA_WIDTH>\n            <C0_S_AXI_ID_WIDTH>4</C0_S_AXI_ID_WIDTH>\n            <C0_S_AXI_SUPPORTS_NARROW_BURST>0</C0_S_AXI_SUPPORTS_NARROW_BURST>\n        </AXIParameters>\n    </Controller>\n\n</Project>\n"
  },
  {
    "path": "constraints/xilinx/miniitx100.xdc",
    "content": "# Avnet Mini-ITX Zynq100\nset_property LOC H9  [get_ports { CLK_sys_clk_p }]\nset_property LOC G9  [get_ports { CLK_sys_clk_n }]\nset_property IOSTANDARD DIFF_SSTL15 [get_ports { CLK_sys_clk_* }]\n\nset_property iostandard \"LVCMOS18\" [get_ports \"GPIO_leds[0]\"]\nset_property PACKAGE_PIN \"C6\" [get_ports \"GPIO_leds[0]\"]\nset_property slew \"SLOW\" [get_ports \"GPIO_leds[0]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"GPIO_leds[0]\"]\n\nset_property iostandard \"LVCMOS18\" [get_ports \"GPIO_leds[1]\"]\nset_property PACKAGE_PIN \"B6\" [get_ports \"GPIO_leds[1]\"]\nset_property slew \"SLOW\" [get_ports \"GPIO_leds[1]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"GPIO_leds[1]\"]\n\nset_property iostandard \"LVCMOS18\" [get_ports \"GPIO_leds[2]\"]\nset_property PACKAGE_PIN \"L9\" [get_ports \"GPIO_leds[2]\"]\nset_property slew \"SLOW\" [get_ports \"GPIO_leds[2]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"GPIO_leds[2]\"]\n\nset_property iostandard \"LVCMOS18\" [get_ports \"GPIO_leds[3]\"]\nset_property PACKAGE_PIN \"L10\" [get_ports \"GPIO_leds[3]\"]\nset_property slew \"SLOW\" [get_ports \"GPIO_leds[3]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"GPIO_leds[3]\"]\n\nset_property iostandard \"LVCMOS18\" [get_ports \"GPIO_leds[4]\"]\nset_property PACKAGE_PIN \"K10\" [get_ports \"GPIO_leds[4]\"]\nset_property slew \"SLOW\" [get_ports \"GPIO_leds[4]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"GPIO_leds[4]\"]\n\nset_property iostandard \"LVCMOS18\" [get_ports \"GPIO_leds[5]\"]\nset_property PACKAGE_PIN \"K11\" [get_ports \"GPIO_leds[5]\"]\nset_property slew \"SLOW\" [get_ports \"GPIO_leds[5]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"GPIO_leds[5]\"]\n\nset_property iostandard \"LVCMOS18\" [get_ports \"GPIO_leds[6]\"]\nset_property PACKAGE_PIN \"L12\" [get_ports \"GPIO_leds[6]\"]\nset_property slew \"SLOW\" [get_ports \"GPIO_leds[6]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"GPIO_leds[6]\"]\n\nset_property iostandard \"LVCMOS18\" [get_ports \"GPIO_leds[7]\"]\nset_property PACKAGE_PIN \"K12\" [get_ports \"GPIO_leds[7]\"]\nset_property slew \"SLOW\" [get_ports \"GPIO_leds[7]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"GPIO_leds[7]\"]\n"
  },
  {
    "path": "constraints/xilinx/nfsume-axiddr3.prj",
    "content": "<?xml version='1.0' encoding='UTF-8'?>\n<!-- IMPORTANT: This is an internal file that has been generated by the MIG software. Any direct editing or changes made to this file may result in unpredictable behavior or data corruption. It is strongly advised that users do not edit the contents of this file. Re-run the MIG GUI with the required settings if any of the options provided below need to be altered. -->\n<Project NoOfControllers=\"1\" >\n    <ModuleName>nfsume_ddr3a</ModuleName>\n    <dci_inouts_inputs>1</dci_inouts_inputs>\n    <dci_inputs>1</dci_inputs>\n    <Debug_En>OFF</Debug_En>\n    <DataDepth_En>1024</DataDepth_En>\n    <LowPower_En>ON</LowPower_En>\n    <XADC_En>Enabled</XADC_En>\n    <TargetFPGA>xc7vx690t-ffg1761/-3</TargetFPGA>\n    <Version>2.4</Version>\n    <SystemClock>No Buffer</SystemClock>\n    <ReferenceClock>Use System Clock</ReferenceClock>\n    <SysResetPolarity>ACTIVE LOW</SysResetPolarity>\n    <BankSelectionFlag>FALSE</BankSelectionFlag>\n    <InternalVref>0</InternalVref>\n    <dci_hr_inouts_inputs>50 Ohms</dci_hr_inouts_inputs>\n    <dci_cascade>0</dci_cascade>\n    <Controller number=\"0\" >\n        <MemoryDevice>DDR3_SDRAM/SODIMMs/MT8KTF51264HZ-1G9</MemoryDevice>\n        <TimePeriod>1250</TimePeriod>\n        <VccAuxIO>1.8V</VccAuxIO>\n        <PHYRatio>4:1</PHYRatio>\n        <InputClkFreq>200</InputClkFreq>\n        <UIExtraClocks>0</UIExtraClocks>\n        <MMCM_VCO>800</MMCM_VCO>\n        <MMCMClkOut0> 1.000</MMCMClkOut0>\n        <MMCMClkOut1>1</MMCMClkOut1>\n        <MMCMClkOut2>1</MMCMClkOut2>\n        <MMCMClkOut3>1</MMCMClkOut3>\n        <MMCMClkOut4>1</MMCMClkOut4>\n        <DataWidth>64</DataWidth>\n        <DeepMemory>1</DeepMemory>\n        <DataMask>1</DataMask>\n        <ECC>Disabled</ECC>\n        <Ordering>Normal</Ordering>\n        <CustomPart>FALSE</CustomPart>\n        <NewPartName></NewPartName>\n        <RowAddress>16</RowAddress>\n        <ColAddress>10</ColAddress>\n        <BankAddress>3</BankAddress>\n        <MemoryVoltage>1.5V</MemoryVoltage>\n        <UserMemoryAddressMap>BANK_ROW_COLUMN</UserMemoryAddressMap>\n        <PinSelection>\n            <Pin VCCAUX_IO=\"NORMAL\" IOSTANDARD=\"SSTL15\" PADName=\"G17\" SLEW=\"\" name=\"ddr3_addr[0]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"NORMAL\" IOSTANDARD=\"SSTL15\" PADName=\"E20\" SLEW=\"\" name=\"ddr3_addr[10]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"NORMAL\" IOSTANDARD=\"SSTL15\" PADName=\"A17\" SLEW=\"\" name=\"ddr3_addr[11]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"NORMAL\" IOSTANDARD=\"SSTL15\" PADName=\"K19\" SLEW=\"\" name=\"ddr3_addr[12]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"NORMAL\" IOSTANDARD=\"SSTL15\" PADName=\"C20\" SLEW=\"\" name=\"ddr3_addr[13]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"NORMAL\" IOSTANDARD=\"SSTL15\" PADName=\"F17\" SLEW=\"\" name=\"ddr3_addr[14]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"NORMAL\" IOSTANDARD=\"SSTL15\" PADName=\"K17\" SLEW=\"\" name=\"ddr3_addr[15]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"NORMAL\" IOSTANDARD=\"SSTL15\" PADName=\"J20\" SLEW=\"\" name=\"ddr3_addr[1]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"NORMAL\" IOSTANDARD=\"SSTL15\" PADName=\"H18\" SLEW=\"\" name=\"ddr3_addr[2]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"NORMAL\" IOSTANDARD=\"SSTL15\" PADName=\"D21\" SLEW=\"\" name=\"ddr3_addr[3]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"NORMAL\" IOSTANDARD=\"SSTL15\" PADName=\"D18\" SLEW=\"\" name=\"ddr3_addr[4]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"NORMAL\" IOSTANDARD=\"SSTL15\" PADName=\"C21\" SLEW=\"\" name=\"ddr3_addr[5]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"NORMAL\" IOSTANDARD=\"SSTL15\" PADName=\"J17\" SLEW=\"\" name=\"ddr3_addr[6]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"NORMAL\" IOSTANDARD=\"SSTL15\" PADName=\"E17\" SLEW=\"\" name=\"ddr3_addr[7]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"NORMAL\" IOSTANDARD=\"SSTL15\" PADName=\"B21\" SLEW=\"\" name=\"ddr3_addr[8]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"NORMAL\" IOSTANDARD=\"SSTL15\" PADName=\"A19\" SLEW=\"\" name=\"ddr3_addr[9]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"NORMAL\" IOSTANDARD=\"SSTL15\" PADName=\"F20\" SLEW=\"\" name=\"ddr3_ba[0]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"NORMAL\" IOSTANDARD=\"SSTL15\" PADName=\"D17\" SLEW=\"\" name=\"ddr3_ba[1]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"NORMAL\" IOSTANDARD=\"SSTL15\" PADName=\"B19\" SLEW=\"\" name=\"ddr3_ba[2]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"NORMAL\" IOSTANDARD=\"SSTL15\" PADName=\"D20\" SLEW=\"\" name=\"ddr3_cas_n\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"NORMAL\" IOSTANDARD=\"DIFF_SSTL15\" PADName=\"F19\" SLEW=\"\" name=\"ddr3_ck_n[0]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"NORMAL\" IOSTANDARD=\"DIFF_SSTL15\" PADName=\"G19\" SLEW=\"\" name=\"ddr3_ck_p[0]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"NORMAL\" IOSTANDARD=\"SSTL15\" PADName=\"M17\" SLEW=\"\" name=\"ddr3_cke[0]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"NORMAL\" IOSTANDARD=\"SSTL15\" PADName=\"C19\" SLEW=\"\" name=\"ddr3_cs_n[0]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"NORMAL\" IOSTANDARD=\"SSTL15\" PADName=\"M13\" SLEW=\"\" name=\"ddr3_dm[0]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"NORMAL\" IOSTANDARD=\"SSTL15\" PADName=\"J13\" SLEW=\"\" name=\"ddr3_dm[1]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"NORMAL\" IOSTANDARD=\"SSTL15\" PADName=\"G14\" SLEW=\"\" name=\"ddr3_dm[2]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"NORMAL\" IOSTANDARD=\"SSTL15\" PADName=\"A14\" SLEW=\"\" name=\"ddr3_dm[3]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"NORMAL\" IOSTANDARD=\"SSTL15\" PADName=\"B23\" SLEW=\"\" name=\"ddr3_dm[4]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"NORMAL\" IOSTANDARD=\"SSTL15\" PADName=\"D26\" SLEW=\"\" name=\"ddr3_dm[5]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"NORMAL\" IOSTANDARD=\"SSTL15\" PADName=\"A31\" SLEW=\"\" name=\"ddr3_dm[6]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"NORMAL\" IOSTANDARD=\"SSTL15\" PADName=\"F31\" SLEW=\"\" name=\"ddr3_dm[7]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"NORMAL\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"M11\" SLEW=\"\" name=\"ddr3_dq[0]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"NORMAL\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"H14\" SLEW=\"\" name=\"ddr3_dq[10]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"NORMAL\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"L16\" SLEW=\"\" name=\"ddr3_dq[11]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"NORMAL\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"K13\" SLEW=\"\" name=\"ddr3_dq[12]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"NORMAL\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"H13\" SLEW=\"\" name=\"ddr3_dq[13]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"NORMAL\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"H15\" SLEW=\"\" name=\"ddr3_dq[14]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"NORMAL\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"J15\" SLEW=\"\" name=\"ddr3_dq[15]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"NORMAL\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"E14\" SLEW=\"\" name=\"ddr3_dq[16]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"NORMAL\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"F15\" SLEW=\"\" name=\"ddr3_dq[17]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"NORMAL\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"F16\" SLEW=\"\" name=\"ddr3_dq[18]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"NORMAL\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"E15\" SLEW=\"\" name=\"ddr3_dq[19]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"NORMAL\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"M12\" SLEW=\"\" name=\"ddr3_dq[1]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"NORMAL\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"G12\" SLEW=\"\" name=\"ddr3_dq[20]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"NORMAL\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"F12\" SLEW=\"\" name=\"ddr3_dq[21]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"NORMAL\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"E13\" SLEW=\"\" name=\"ddr3_dq[22]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"NORMAL\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"F14\" SLEW=\"\" name=\"ddr3_dq[23]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"NORMAL\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"D15\" SLEW=\"\" name=\"ddr3_dq[24]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"NORMAL\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"D16\" SLEW=\"\" name=\"ddr3_dq[25]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"NORMAL\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"B16\" SLEW=\"\" name=\"ddr3_dq[26]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"NORMAL\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"C16\" SLEW=\"\" name=\"ddr3_dq[27]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"NORMAL\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"E12\" SLEW=\"\" name=\"ddr3_dq[28]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"NORMAL\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"C13\" SLEW=\"\" name=\"ddr3_dq[29]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"NORMAL\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"N14\" SLEW=\"\" name=\"ddr3_dq[2]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"NORMAL\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"B14\" SLEW=\"\" name=\"ddr3_dq[30]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"NORMAL\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"D13\" SLEW=\"\" name=\"ddr3_dq[31]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"NORMAL\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"C24\" SLEW=\"\" name=\"ddr3_dq[32]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"NORMAL\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"A25\" SLEW=\"\" name=\"ddr3_dq[33]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"NORMAL\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"B26\" SLEW=\"\" name=\"ddr3_dq[34]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"NORMAL\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"B27\" SLEW=\"\" name=\"ddr3_dq[35]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"NORMAL\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"B22\" SLEW=\"\" name=\"ddr3_dq[36]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"NORMAL\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"A22\" SLEW=\"\" name=\"ddr3_dq[37]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"NORMAL\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"C23\" SLEW=\"\" name=\"ddr3_dq[38]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"NORMAL\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"A24\" SLEW=\"\" name=\"ddr3_dq[39]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"NORMAL\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"M14\" SLEW=\"\" name=\"ddr3_dq[3]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"NORMAL\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"D25\" SLEW=\"\" name=\"ddr3_dq[40]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"NORMAL\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"C25\" SLEW=\"\" name=\"ddr3_dq[41]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"NORMAL\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"E24\" SLEW=\"\" name=\"ddr3_dq[42]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"NORMAL\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"E23\" SLEW=\"\" name=\"ddr3_dq[43]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"NORMAL\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"D22\" SLEW=\"\" name=\"ddr3_dq[44]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"NORMAL\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"D23\" SLEW=\"\" name=\"ddr3_dq[45]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"NORMAL\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"E22\" SLEW=\"\" name=\"ddr3_dq[46]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"NORMAL\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"F22\" SLEW=\"\" name=\"ddr3_dq[47]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"NORMAL\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"A29\" SLEW=\"\" name=\"ddr3_dq[48]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"NORMAL\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"A30\" SLEW=\"\" name=\"ddr3_dq[49]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"NORMAL\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"N13\" SLEW=\"\" name=\"ddr3_dq[4]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"NORMAL\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"A32\" SLEW=\"\" name=\"ddr3_dq[50]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"NORMAL\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"D28\" SLEW=\"\" name=\"ddr3_dq[51]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"NORMAL\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"C28\" SLEW=\"\" name=\"ddr3_dq[52]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"NORMAL\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"C29\" SLEW=\"\" name=\"ddr3_dq[53]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"NORMAL\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"D27\" SLEW=\"\" name=\"ddr3_dq[54]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"NORMAL\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"C31\" SLEW=\"\" name=\"ddr3_dq[55]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"NORMAL\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"D30\" SLEW=\"\" name=\"ddr3_dq[56]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"NORMAL\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"E30\" SLEW=\"\" name=\"ddr3_dq[57]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"NORMAL\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"C30\" SLEW=\"\" name=\"ddr3_dq[58]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"NORMAL\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"F30\" SLEW=\"\" name=\"ddr3_dq[59]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"NORMAL\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"L12\" SLEW=\"\" name=\"ddr3_dq[5]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"NORMAL\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"F27\" SLEW=\"\" name=\"ddr3_dq[60]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"NORMAL\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"F26\" SLEW=\"\" name=\"ddr3_dq[61]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"NORMAL\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"F29\" SLEW=\"\" name=\"ddr3_dq[62]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"NORMAL\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"E29\" SLEW=\"\" name=\"ddr3_dq[63]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"NORMAL\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"L14\" SLEW=\"\" name=\"ddr3_dq[6]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"NORMAL\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"N15\" SLEW=\"\" name=\"ddr3_dq[7]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"NORMAL\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"K15\" SLEW=\"\" name=\"ddr3_dq[8]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"NORMAL\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"K14\" SLEW=\"\" name=\"ddr3_dq[9]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"NORMAL\" IOSTANDARD=\"DIFF_SSTL15_T_DCI\" PADName=\"M16\" SLEW=\"\" name=\"ddr3_dqs_n[0]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"NORMAL\" IOSTANDARD=\"DIFF_SSTL15_T_DCI\" PADName=\"J12\" SLEW=\"\" name=\"ddr3_dqs_n[1]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"NORMAL\" IOSTANDARD=\"DIFF_SSTL15_T_DCI\" PADName=\"G16\" SLEW=\"\" name=\"ddr3_dqs_n[2]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"NORMAL\" IOSTANDARD=\"DIFF_SSTL15_T_DCI\" PADName=\"C14\" SLEW=\"\" name=\"ddr3_dqs_n[3]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"NORMAL\" IOSTANDARD=\"DIFF_SSTL15_T_DCI\" PADName=\"A27\" SLEW=\"\" name=\"ddr3_dqs_n[4]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"NORMAL\" IOSTANDARD=\"DIFF_SSTL15_T_DCI\" PADName=\"E25\" SLEW=\"\" name=\"ddr3_dqs_n[5]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"NORMAL\" IOSTANDARD=\"DIFF_SSTL15_T_DCI\" PADName=\"B29\" SLEW=\"\" name=\"ddr3_dqs_n[6]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"NORMAL\" IOSTANDARD=\"DIFF_SSTL15_T_DCI\" PADName=\"E28\" SLEW=\"\" name=\"ddr3_dqs_n[7]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"NORMAL\" IOSTANDARD=\"DIFF_SSTL15_T_DCI\" PADName=\"N16\" SLEW=\"\" name=\"ddr3_dqs_p[0]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"NORMAL\" IOSTANDARD=\"DIFF_SSTL15_T_DCI\" PADName=\"K12\" SLEW=\"\" name=\"ddr3_dqs_p[1]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"NORMAL\" IOSTANDARD=\"DIFF_SSTL15_T_DCI\" PADName=\"H16\" SLEW=\"\" name=\"ddr3_dqs_p[2]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"NORMAL\" IOSTANDARD=\"DIFF_SSTL15_T_DCI\" PADName=\"C15\" SLEW=\"\" name=\"ddr3_dqs_p[3]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"NORMAL\" IOSTANDARD=\"DIFF_SSTL15_T_DCI\" PADName=\"A26\" SLEW=\"\" name=\"ddr3_dqs_p[4]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"NORMAL\" IOSTANDARD=\"DIFF_SSTL15_T_DCI\" PADName=\"F25\" SLEW=\"\" name=\"ddr3_dqs_p[5]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"NORMAL\" IOSTANDARD=\"DIFF_SSTL15_T_DCI\" PADName=\"B28\" SLEW=\"\" name=\"ddr3_dqs_p[6]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"NORMAL\" IOSTANDARD=\"DIFF_SSTL15_T_DCI\" PADName=\"E27\" SLEW=\"\" name=\"ddr3_dqs_p[7]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"NORMAL\" IOSTANDARD=\"SSTL15\" PADName=\"J18\" SLEW=\"\" name=\"ddr3_odt[0]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"NORMAL\" IOSTANDARD=\"SSTL15\" PADName=\"B17\" SLEW=\"\" name=\"ddr3_ras_n\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"NORMAL\" IOSTANDARD=\"LVCMOS15\" PADName=\"A15\" SLEW=\"\" name=\"ddr3_reset_n\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"NORMAL\" IOSTANDARD=\"SSTL15\" PADName=\"H20\" SLEW=\"\" name=\"ddr3_we_n\" IN_TERM=\"\" />\n        </PinSelection>\n        <System_Control>\n            <Pin PADName=\"No connect\" Bank=\"Select Bank\" name=\"sys_rst\" />\n            <Pin PADName=\"No connect\" Bank=\"Select Bank\" name=\"init_calib_complete\" />\n            <Pin PADName=\"No connect\" Bank=\"Select Bank\" name=\"tg_compare_error\" />\n        </System_Control>\n        <TimingParameters>\n            <Parameters twtr=\"7.5\" trrd=\"5\" trefi=\"7.8\" tfaw=\"27\" trtp=\"7.5\" tcke=\"5\" trfc=\"260\" trp=\"13.91\" tras=\"34\" trcd=\"13.91\" />\n        </TimingParameters>\n        <mrBurstLength name=\"Burst Length\" >8 - Fixed</mrBurstLength>\n        <mrBurstType name=\"Read Burst Type and Length\" >Sequential</mrBurstType>\n        <mrCasLatency name=\"CAS Latency\" >11</mrCasLatency>\n        <mrMode name=\"Mode\" >Normal</mrMode>\n        <mrDllReset name=\"DLL Reset\" >No</mrDllReset>\n        <mrPdMode name=\"DLL control for precharge PD\" >Slow Exit</mrPdMode>\n        <emrDllEnable name=\"DLL Enable\" >Enable</emrDllEnable>\n        <emrOutputDriveStrength name=\"Output Driver Impedance Control\" >RZQ/7</emrOutputDriveStrength>\n        <emrMirrorSelection name=\"Address Mirroring\" >Disable</emrMirrorSelection>\n        <emrCSSelection name=\"Controller Chip Select Pin\" >Enable</emrCSSelection>\n        <emrRTT name=\"RTT (nominal) - On Die Termination (ODT)\" >RZQ/6</emrRTT>\n        <emrPosted name=\"Additive Latency (AL)\" >0</emrPosted>\n        <emrOCD name=\"Write Leveling Enable\" >Disabled</emrOCD>\n        <emrDQS name=\"TDQS enable\" >Enabled</emrDQS>\n        <emrRDQS name=\"Qoff\" >Output Buffer Enabled</emrRDQS>\n        <mr2PartialArraySelfRefresh name=\"Partial-Array Self Refresh\" >Full Array</mr2PartialArraySelfRefresh>\n        <mr2CasWriteLatency name=\"CAS write latency\" >8</mr2CasWriteLatency>\n        <mr2AutoSelfRefresh name=\"Auto Self Refresh\" >Enabled</mr2AutoSelfRefresh>\n        <mr2SelfRefreshTempRange name=\"High Temparature Self Refresh Rate\" >Normal</mr2SelfRefreshTempRange>\n        <mr2RTTWR name=\"RTT_WR - Dynamic On Die Termination (ODT)\" >Dynamic ODT off</mr2RTTWR>\n        <PortInterface>AXI</PortInterface>\n        <AXIParameters>\n            <C0_C_RD_WR_ARB_ALGORITHM>RD_PRI_REG</C0_C_RD_WR_ARB_ALGORITHM>\n            <C0_S_AXI_ADDR_WIDTH>32</C0_S_AXI_ADDR_WIDTH>\n            <C0_S_AXI_DATA_WIDTH>512</C0_S_AXI_DATA_WIDTH>\n            <C0_S_AXI_ID_WIDTH>4</C0_S_AXI_ID_WIDTH>\n            <C0_S_AXI_SUPPORTS_NARROW_BURST>0</C0_S_AXI_SUPPORTS_NARROW_BURST>\n        </AXIParameters>\n    </Controller>\n\n</Project>\n"
  },
  {
    "path": "constraints/xilinx/nfsume.xdc",
    "content": "######################################################################################################\n##  File name :       default.xdc\n##\n##  Details :     Constraints file\n##                    FPGA family:       virtex7\n##                    FPGA:              xc7vx690t-3ffg1761C\n##                    Speedgrade:        -3\n##\n######################################################################################################\n\n##The following two properties should be set for every design\nset_property CFGBVS GND [current_design]\nset_property CONFIG_VOLTAGE 1.8 [current_design]\n\n######################################################################################################\n# PIN ASSIGNMENTS\n######################################################################################################\nset_property LOC AR22 [get_ports { leds[0] }]\nset_property LOC AR23 [get_ports { leds[1] }]\nset_property LOC AB7  [get_ports { CLK_pci_sys_clk_n }]\nset_property LOC AB8  [get_ports { CLK_pci_sys_clk_p }]\nset_property LOC AY35 [get_ports { RST_N_pci_sys_reset_n }]\nset_property LOC H19  [get_ports { CLK_sys_clk_p }]\nset_property LOC G18  [get_ports { CLK_sys_clk_n }]\n\n# set_property LOC W2   [get_ports { PCIE_rxp_v[0] }]\n# set_property LOC AA2  [get_ports { PCIE_rxp_v[1] }]\n# set_property LOC AC2  [get_ports { PCIE_rxp_v[2] }]\n# set_property LOC AE2  [get_ports { PCIE_rxp_v[3] }]\n# set_property LOC AG2  [get_ports { PCIE_rxp_v[4] }]\n# set_property LOC AH4  [get_ports { PCIE_rxp_v[5] }]\n# set_property LOC AJ2  [get_ports { PCIE_rxp_v[6] }]\n# set_property LOC AK4  [get_ports { PCIE_rxp_v[7] }]\n\n# set_property LOC W1   [get_ports { PCIE_rxn_v[0] }]\n# set_property LOC AA1  [get_ports { PCIE_rxn_v[1] }]\n# set_property LOC AC1  [get_ports { PCIE_rxn_v[2] }]\n# set_property LOC AE1  [get_ports { PCIE_rxn_v[3] }]\n# set_property LOC AG1  [get_ports { PCIE_rxn_v[4] }]\n# set_property LOC AH3  [get_ports { PCIE_rxn_v[5] }]\n# set_property LOC AJ1  [get_ports { PCIE_rxn_v[6] }]\n# set_property LOC AK3  [get_ports { PCIE_rxn_v[7] }]\n\n# set_property LOC Y4   [get_ports { PCIE_txp[0] }]\n# set_property LOC AA6  [get_ports { PCIE_txp[1] }]\n# set_property LOC AB4  [get_ports { PCIE_txp[2] }]\n# set_property LOC AC6  [get_ports { PCIE_txp[3] }]\n# set_property LOC AD4  [get_ports { PCIE_txp[4] }]\n# set_property LOC AE6  [get_ports { PCIE_txp[5] }]\n# set_property LOC AF4  [get_ports { PCIE_txp[6] }]\n# set_property LOC AG6  [get_ports { PCIE_txp[7] }]\n\n# set_property LOC Y3   [get_ports { PCIE_txn[0] }]\n# set_property LOC AA5  [get_ports { PCIE_txn[1] }]\n# set_property LOC AB3  [get_ports { PCIE_txn[2] }]\n# set_property LOC AC5  [get_ports { PCIE_txn[3] }]\n# set_property LOC AD3  [get_ports { PCIE_txn[4] }]\n# set_property LOC AE5  [get_ports { PCIE_txn[5] }]\n# set_property LOC AF3  [get_ports { PCIE_txn[6] }]\n# set_property LOC AG5  [get_ports { PCIE_txn[7] }]\n\n######################################################################################################\n# I/O STANDARDS\n######################################################################################################\nset_property IOSTANDARD LVCMOS15    [get_ports { leds[*] }]\nset_property IOSTANDARD DIFF_SSTL15 [get_ports { CLK_sys_clk_* }]\nset_property IOSTANDARD LVCMOS18    [get_ports { RST_N_pci_sys_reset_n }]\nset_property PULLUP     true        [get_ports { RST_N_pci_sys_reset_n }]\n\n######################################################################################################\n# CELL LOCATIONS\n######################################################################################################\n#\n# SYS clock 100 MHz (input) signal. The sys_clk_p and sys_clk_n\n# signals are the PCI Express reference clock. Virtex-7 GT\n# Transceiver architecture requires the use of a dedicated clock\n# resources (FPGA input pins) associated with each GT Transceiver.\n# To use these pins an IBUFDS primitive (refclk_ibuf) is\n# instantiated in user's design.\n# Please refer to the Virtex-7 GT Transceiver User Guide\n# (UG) for guidelines regarding clock resource selection.\n#\n#set_property LOC IBUFDS_GTE2_X1Y5 [get_cells { *pci_clk_100mhz_buf }]\n\n#set_property LOC bogus [get_cells -hier -filter { NAME =~ */ext_clk.pipe_clock_i/mmcm_i }]\n#set_property LOC bogus [get_cells -hier -filter { NAME =~ *clkgen_pll }]\n#set_property LOC bogus [get_cells -hier -filter { NAME =~ *clk_gen_pll }]\n\n######################################################################################################\n# TIMING CONSTRAINTS\n######################################################################################################\n\n## in pcie-clocks.xdc\n"
  },
  {
    "path": "constraints/xilinx/ok/zc7z010clg400.xdc",
    "content": "############################################################################\n##\n##  Xilinx, Inc. 2006            www.xilinx.com\n############################################################################\n##  File name :       ps7_constraints.xdc\n##\n##  Details :     Constraints file\n##                    FPGA family:       zynq\n##                    FPGA:              xc7z020clg484-1\n##                    Device Size:        xc7z020\n##                    Package:            clg484\n##                    Speedgrade:         -1\n##\n##\n############################################################################\n############################################################################\n############################################################################\n# Clock constraints                                                        #\n############################################################################\ncreate_clock -name clk_fpga_0 -period \"10\" [get_pins \"*ps7_foo/FCLKCLK[0]\"]\nset_input_jitter clk_fpga_0 0.6\nset_clock_groups -asynchronous -group {clk_fpga_0}\ncreate_clock -name clk_fpga_1 -period \"6\" [get_pins \"*ps7_foo/FCLKCLK[1]\"]\nset_input_jitter clk_fpga_1 0.6\nset_clock_groups -asynchronous -group {clk_fpga_1}\ncreate_clock -name clk_fpga_3 -period \"5\" [get_pins \"*ps7_foo/FCLKCLK[3]\"]\nset_input_jitter clk_fpga_3 0.6\nset_clock_groups -asynchronous -group {clk_fpga_3}\n\n############################################################################\n# I/O STANDARDS and Location Constraints                                   #\n############################################################################\n\nset_property iostandard \"SSTL15\" [get_ports \"DDR_WEB\"]\nset_property PACKAGE_PIN \"M5\" [get_ports \"DDR_WEB\"]\nset_property slew \"SLOW\" [get_ports \"DDR_WEB\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_WEB\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_VRP\"]\nset_property PACKAGE_PIN \"H5\" [get_ports \"DDR_VRP\"]\nset_property slew \"FAST\" [get_ports \"DDR_VRP\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_VRP\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_VRN\"]\nset_property PACKAGE_PIN \"G5\" [get_ports \"DDR_VRN\"]\nset_property slew \"FAST\" [get_ports \"DDR_VRN\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_VRN\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_RAS_n\"]\nset_property PACKAGE_PIN \"P4\" [get_ports \"DDR_RAS_n\"]\nset_property slew \"SLOW\" [get_ports \"DDR_RAS_n\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_RAS_n\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_ODT\"]\nset_property PACKAGE_PIN \"N5\" [get_ports \"DDR_ODT\"]\nset_property slew \"SLOW\" [get_ports \"DDR_ODT\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_ODT\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_DRSTB\"]\nset_property PACKAGE_PIN \"B4\" [get_ports \"DDR_DRSTB\"]\nset_property slew \"FAST\" [get_ports \"DDR_DRSTB\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_DRSTB\"]\nset_property iostandard \"DIFF_SSTL15_T_DCI\" [get_ports \"DDR_DQS[3]\"]\nset_property PACKAGE_PIN \"W5\" [get_ports \"DDR_DQS[3]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQS[3]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQS[3]\"]\nset_property iostandard \"DIFF_SSTL15_T_DCI\" [get_ports \"DDR_DQS[2]\"]\nset_property PACKAGE_PIN \"R2\" [get_ports \"DDR_DQS[2]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQS[2]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQS[2]\"]\nset_property iostandard \"DIFF_SSTL15_T_DCI\" [get_ports \"DDR_DQS[1]\"]\nset_property PACKAGE_PIN \"G2\" [get_ports \"DDR_DQS[1]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQS[1]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQS[1]\"]\nset_property iostandard \"DIFF_SSTL15_T_DCI\" [get_ports \"DDR_DQS[0]\"]\nset_property PACKAGE_PIN \"C2\" [get_ports \"DDR_DQS[0]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQS[0]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQS[0]\"]\nset_property iostandard \"DIFF_SSTL15_T_DCI\" [get_ports \"DDR_DQS_n[3]\"]\nset_property PACKAGE_PIN \"W4\" [get_ports \"DDR_DQS_n[3]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQS_n[3]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQS_n[3]\"]\nset_property iostandard \"DIFF_SSTL15_T_DCI\" [get_ports \"DDR_DQS_n[2]\"]\nset_property PACKAGE_PIN \"T2\" [get_ports \"DDR_DQS_n[2]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQS_n[2]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQS_n[2]\"]\nset_property iostandard \"DIFF_SSTL15_T_DCI\" [get_ports \"DDR_DQS_n[1]\"]\nset_property PACKAGE_PIN \"F2\" [get_ports \"DDR_DQS_n[1]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQS_n[1]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQS_n[1]\"]\nset_property iostandard \"DIFF_SSTL15_T_DCI\" [get_ports \"DDR_DQS_n[0]\"]\nset_property PACKAGE_PIN \"B2\" [get_ports \"DDR_DQS_n[0]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQS_n[0]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQS_n[0]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[9]\"]\nset_property PACKAGE_PIN \"E3\" [get_ports \"DDR_DQ[9]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[9]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[9]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[8]\"]\nset_property PACKAGE_PIN \"E2\" [get_ports \"DDR_DQ[8]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[8]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[8]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[7]\"]\nset_property PACKAGE_PIN \"E1\" [get_ports \"DDR_DQ[7]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[7]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[7]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[6]\"]\nset_property PACKAGE_PIN \"C1\" [get_ports \"DDR_DQ[6]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[6]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[6]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[5]\"]\nset_property PACKAGE_PIN \"D1\" [get_ports \"DDR_DQ[5]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[5]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[5]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[4]\"]\nset_property PACKAGE_PIN \"D3\" [get_ports \"DDR_DQ[4]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[4]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[4]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[3]\"]\nset_property PACKAGE_PIN \"A4\" [get_ports \"DDR_DQ[3]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[3]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[3]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[31]\"]\nset_property PACKAGE_PIN \"V3\" [get_ports \"DDR_DQ[31]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[31]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[31]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[30]\"]\nset_property PACKAGE_PIN \"V2\" [get_ports \"DDR_DQ[30]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[30]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[30]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[2]\"]\nset_property PACKAGE_PIN \"A2\" [get_ports \"DDR_DQ[2]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[2]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[2]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[29]\"]\nset_property PACKAGE_PIN \"W3\" [get_ports \"DDR_DQ[29]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[29]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[29]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[28]\"]\nset_property PACKAGE_PIN \"Y2\" [get_ports \"DDR_DQ[28]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[28]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[28]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[27]\"]\nset_property PACKAGE_PIN \"Y4\" [get_ports \"DDR_DQ[27]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[27]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[27]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[26]\"]\nset_property PACKAGE_PIN \"W1\" [get_ports \"DDR_DQ[26]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[26]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[26]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[25]\"]\nset_property PACKAGE_PIN \"Y3\" [get_ports \"DDR_DQ[25]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[25]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[25]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[24]\"]\nset_property PACKAGE_PIN \"V1\" [get_ports \"DDR_DQ[24]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[24]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[24]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[23]\"]\nset_property PACKAGE_PIN \"U3\" [get_ports \"DDR_DQ[23]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[23]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[23]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[22]\"]\nset_property PACKAGE_PIN \"U2\" [get_ports \"DDR_DQ[22]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[22]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[22]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[21]\"]\nset_property PACKAGE_PIN \"U4\" [get_ports \"DDR_DQ[21]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[21]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[21]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[20]\"]\nset_property PACKAGE_PIN \"T4\" [get_ports \"DDR_DQ[20]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[20]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[20]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[1]\"]\nset_property PACKAGE_PIN \"B3\" [get_ports \"DDR_DQ[1]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[1]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[1]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[19]\"]\nset_property PACKAGE_PIN \"R1\" [get_ports \"DDR_DQ[19]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[19]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[19]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[18]\"]\nset_property PACKAGE_PIN \"R3\" [get_ports \"DDR_DQ[18]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[18]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[18]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[17]\"]\nset_property PACKAGE_PIN \"P3\" [get_ports \"DDR_DQ[17]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[17]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[17]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[16]\"]\nset_property PACKAGE_PIN \"P1\" [get_ports \"DDR_DQ[16]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[16]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[16]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[15]\"]\nset_property PACKAGE_PIN \"J1\" [get_ports \"DDR_DQ[15]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[15]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[15]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[14]\"]\nset_property PACKAGE_PIN \"H1\" [get_ports \"DDR_DQ[14]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[14]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[14]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[13]\"]\nset_property PACKAGE_PIN \"H2\" [get_ports \"DDR_DQ[13]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[13]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[13]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[12]\"]\nset_property PACKAGE_PIN \"J3\" [get_ports \"DDR_DQ[12]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[12]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[12]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[11]\"]\nset_property PACKAGE_PIN \"H3\" [get_ports \"DDR_DQ[11]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[11]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[11]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[10]\"]\nset_property PACKAGE_PIN \"G3\" [get_ports \"DDR_DQ[10]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[10]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[10]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[0]\"]\nset_property PACKAGE_PIN \"C3\" [get_ports \"DDR_DQ[0]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[0]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[0]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DM[3]\"]\nset_property PACKAGE_PIN \"Y1\" [get_ports \"DDR_DM[3]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DM[3]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_DM[3]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DM[2]\"]\nset_property PACKAGE_PIN \"T1\" [get_ports \"DDR_DM[2]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DM[2]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_DM[2]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DM[1]\"]\nset_property PACKAGE_PIN \"F1\" [get_ports \"DDR_DM[1]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DM[1]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_DM[1]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DM[0]\"]\nset_property PACKAGE_PIN \"A1\" [get_ports \"DDR_DM[0]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DM[0]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_DM[0]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_CS_n\"]\nset_property PACKAGE_PIN \"N1\" [get_ports \"DDR_CS_n\"]\nset_property slew \"SLOW\" [get_ports \"DDR_CS_n\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_CS_n\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_CKE\"]\nset_property PACKAGE_PIN \"N3\" [get_ports \"DDR_CKE\"]\nset_property slew \"SLOW\" [get_ports \"DDR_CKE\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_CKE\"]\nset_property iostandard \"DIFF_SSTL15\" [get_ports \"DDR_Clk\"]\nset_property PACKAGE_PIN \"L2\" [get_ports \"DDR_Clk\"]\nset_property slew \"FAST\" [get_ports \"DDR_Clk\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_Clk\"]\nset_property iostandard \"DIFF_SSTL15\" [get_ports \"DDR_Clk_n\"]\nset_property PACKAGE_PIN \"M2\" [get_ports \"DDR_Clk_n\"]\nset_property slew \"FAST\" [get_ports \"DDR_Clk_n\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_Clk_n\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_CAS_n\"]\nset_property PACKAGE_PIN \"P5\" [get_ports \"DDR_CAS_n\"]\nset_property slew \"SLOW\" [get_ports \"DDR_CAS_n\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_CAS_n\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_BankAddr[2]\"]\nset_property PACKAGE_PIN \"J5\" [get_ports \"DDR_BankAddr[2]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_BankAddr[2]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_BankAddr[2]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_BankAddr[1]\"]\nset_property PACKAGE_PIN \"R4\" [get_ports \"DDR_BankAddr[1]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_BankAddr[1]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_BankAddr[1]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_BankAddr[0]\"]\nset_property PACKAGE_PIN \"L5\" [get_ports \"DDR_BankAddr[0]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_BankAddr[0]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_BankAddr[0]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_Addr[9]\"]\nset_property PACKAGE_PIN \"J4\" [get_ports \"DDR_Addr[9]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_Addr[9]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_Addr[9]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_Addr[8]\"]\nset_property PACKAGE_PIN \"K1\" [get_ports \"DDR_Addr[8]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_Addr[8]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_Addr[8]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_Addr[7]\"]\nset_property PACKAGE_PIN \"K4\" [get_ports \"DDR_Addr[7]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_Addr[7]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_Addr[7]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_Addr[6]\"]\nset_property PACKAGE_PIN \"L4\" [get_ports \"DDR_Addr[6]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_Addr[6]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_Addr[6]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_Addr[5]\"]\nset_property PACKAGE_PIN \"L1\" [get_ports \"DDR_Addr[5]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_Addr[5]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_Addr[5]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_Addr[4]\"]\nset_property PACKAGE_PIN \"M4\" [get_ports \"DDR_Addr[4]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_Addr[4]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_Addr[4]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_Addr[3]\"]\nset_property PACKAGE_PIN \"K3\" [get_ports \"DDR_Addr[3]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_Addr[3]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_Addr[3]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_Addr[2]\"]\nset_property PACKAGE_PIN \"M3\" [get_ports \"DDR_Addr[2]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_Addr[2]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_Addr[2]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_Addr[1]\"]\nset_property PACKAGE_PIN \"K2\" [get_ports \"DDR_Addr[1]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_Addr[1]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_Addr[1]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_Addr[14]\"]\nset_property PACKAGE_PIN \"F4\" [get_ports \"DDR_Addr[14]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_Addr[14]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_Addr[14]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_Addr[13]\"]\nset_property PACKAGE_PIN \"D4\" [get_ports \"DDR_Addr[13]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_Addr[13]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_Addr[13]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_Addr[12]\"]\nset_property PACKAGE_PIN \"E4\" [get_ports \"DDR_Addr[12]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_Addr[12]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_Addr[12]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_Addr[11]\"]\nset_property PACKAGE_PIN \"G4\" [get_ports \"DDR_Addr[11]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_Addr[11]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_Addr[11]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_Addr[10]\"]\nset_property PACKAGE_PIN \"F5\" [get_ports \"DDR_Addr[10]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_Addr[10]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_Addr[10]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_Addr[0]\"]\nset_property PACKAGE_PIN \"N2\" [get_ports \"DDR_Addr[0]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_Addr[0]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_Addr[0]\"]\n"
  },
  {
    "path": "constraints/xilinx/ok/zc7z020clg400.xdc",
    "content": "############################################################################\n##\n##  Xilinx, Inc. 2006            www.xilinx.com\n############################################################################\n##  File name :       ps7_constraints.xdc\n##\n##  Details :     Constraints file\n##                    FPGA family:       zynq\n##                    FPGA:              xc7z020clg484-1\n##                    Device Size:        xc7z020\n##                    Package:            clg484\n##                    Speedgrade:         -1\n##\n##\n############################################################################\n############################################################################\n############################################################################\n# Clock constraints                                                        #\n############################################################################\ncreate_clock -name clk_fpga_0 -period \"10\" [get_pins \"*ps7_foo/FCLKCLK[0]\"]\nset_input_jitter clk_fpga_0 0.6\nset_clock_groups -asynchronous -group {clk_fpga_0}\ncreate_clock -name clk_fpga_1 -period \"6\" [get_pins \"*ps7_foo/FCLKCLK[1]\"]\nset_input_jitter clk_fpga_1 0.6\nset_clock_groups -asynchronous -group {clk_fpga_1}\ncreate_clock -name clk_fpga_3 -period \"5\" [get_pins \"*ps7_foo/FCLKCLK[3]\"]\nset_input_jitter clk_fpga_3 0.6\nset_clock_groups -asynchronous -group {clk_fpga_3}\n\n############################################################################\n# I/O STANDARDS and Location Constraints                                   #\n############################################################################\n\nset_property iostandard \"SSTL15\" [get_ports \"DDR_WEB\"]\nset_property PACKAGE_PIN \"R4\" [get_ports \"DDR_WEB\"]\nset_property slew \"SLOW\" [get_ports \"DDR_WEB\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_WEB\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_RAS_n\"]\nset_property PACKAGE_PIN \"R5\" [get_ports \"DDR_RAS_n\"]\nset_property slew \"SLOW\" [get_ports \"DDR_RAS_n\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_RAS_n\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_ODT\"]\nset_property PACKAGE_PIN \"P5\" [get_ports \"DDR_ODT\"]\nset_property slew \"SLOW\" [get_ports \"DDR_ODT\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_ODT\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_DRSTB\"]\nset_property PACKAGE_PIN \"F3\" [get_ports \"DDR_DRSTB\"]\nset_property slew \"FAST\" [get_ports \"DDR_DRSTB\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DRSTB\"]\nset_property iostandard \"DIFF_SSTL15_T_DCI\" [get_ports \"DDR_DQS_p[3]\"]\nset_property PACKAGE_PIN \"V2\" [get_ports \"DDR_DQS_p[3]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQS_p[3]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQS_p[3]\"]\nset_property iostandard \"DIFF_SSTL15_T_DCI\" [get_ports \"DDR_DQS_p[2]\"]\nset_property PACKAGE_PIN \"N2\" [get_ports \"DDR_DQS_p[2]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQS_p[2]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQS_p[2]\"]\nset_property iostandard \"DIFF_SSTL15_T_DCI\" [get_ports \"DDR_DQS_p[1]\"]\nset_property PACKAGE_PIN \"H2\" [get_ports \"DDR_DQS_p[1]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQS_p[1]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQS_p[1]\"]\nset_property iostandard \"DIFF_SSTL15_T_DCI\" [get_ports \"DDR_DQS_p[0]\"]\nset_property PACKAGE_PIN \"C2\" [get_ports \"DDR_DQS_p[0]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQS_p[0]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQS_p[0]\"]\nset_property iostandard \"DIFF_SSTL15_T_DCI\" [get_ports \"DDR_DQS_n[3]\"]\nset_property PACKAGE_PIN \"W2\" [get_ports \"DDR_DQS_n[3]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQS_n[3]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQS_n[3]\"]\nset_property iostandard \"DIFF_SSTL15_T_DCI\" [get_ports \"DDR_DQS_n[2]\"]\nset_property PACKAGE_PIN \"P2\" [get_ports \"DDR_DQS_n[2]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQS_n[2]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQS_n[2]\"]\nset_property iostandard \"DIFF_SSTL15_T_DCI\" [get_ports \"DDR_DQS_n[1]\"]\nset_property PACKAGE_PIN \"J2\" [get_ports \"DDR_DQS_n[1]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQS_n[1]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQS_n[1]\"]\nset_property iostandard \"DIFF_SSTL15_T_DCI\" [get_ports \"DDR_DQS_n[0]\"]\nset_property PACKAGE_PIN \"D2\" [get_ports \"DDR_DQS_n[0]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQS_n[0]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQS_n[0]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[9]\"]\nset_property PACKAGE_PIN \"G1\" [get_ports \"DDR_DQ[9]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[9]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[9]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[8]\"]\nset_property PACKAGE_PIN \"G2\" [get_ports \"DDR_DQ[8]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[8]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[8]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[7]\"]\nset_property PACKAGE_PIN \"F1\" [get_ports \"DDR_DQ[7]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[7]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[7]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[6]\"]\nset_property PACKAGE_PIN \"F2\" [get_ports \"DDR_DQ[6]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[6]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[6]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[5]\"]\nset_property PACKAGE_PIN \"E1\" [get_ports \"DDR_DQ[5]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[5]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[5]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[4]\"]\nset_property PACKAGE_PIN \"E3\" [get_ports \"DDR_DQ[4]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[4]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[4]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[3]\"]\nset_property PACKAGE_PIN \"D3\" [get_ports \"DDR_DQ[3]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[3]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[3]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[31]\"]\nset_property PACKAGE_PIN \"Y1\" [get_ports \"DDR_DQ[31]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[31]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[31]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[30]\"]\nset_property PACKAGE_PIN \"W3\" [get_ports \"DDR_DQ[30]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[30]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[30]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[2]\"]\nset_property PACKAGE_PIN \"B2\" [get_ports \"DDR_DQ[2]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[2]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[2]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[29]\"]\nset_property PACKAGE_PIN \"Y3\" [get_ports \"DDR_DQ[29]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[29]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[29]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[28]\"]\nset_property PACKAGE_PIN \"W1\" [get_ports \"DDR_DQ[28]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[28]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[28]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[27]\"]\nset_property PACKAGE_PIN \"U2\" [get_ports \"DDR_DQ[27]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[27]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[27]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[26]\"]\nset_property PACKAGE_PIN \"AA1\" [get_ports \"DDR_DQ[26]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[26]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[26]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[25]\"]\nset_property PACKAGE_PIN \"U1\" [get_ports \"DDR_DQ[25]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[25]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[25]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[24]\"]\nset_property PACKAGE_PIN \"AA3\" [get_ports \"DDR_DQ[24]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[24]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[24]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[23]\"]\nset_property PACKAGE_PIN \"R1\" [get_ports \"DDR_DQ[23]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[23]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[23]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[22]\"]\nset_property PACKAGE_PIN \"M2\" [get_ports \"DDR_DQ[22]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[22]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[22]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[21]\"]\nset_property PACKAGE_PIN \"T2\" [get_ports \"DDR_DQ[21]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[21]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[21]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[20]\"]\nset_property PACKAGE_PIN \"R3\" [get_ports \"DDR_DQ[20]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[20]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[20]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[1]\"]\nset_property PACKAGE_PIN \"C3\" [get_ports \"DDR_DQ[1]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[1]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[1]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[19]\"]\nset_property PACKAGE_PIN \"T1\" [get_ports \"DDR_DQ[19]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[19]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[19]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[18]\"]\nset_property PACKAGE_PIN \"N3\" [get_ports \"DDR_DQ[18]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[18]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[18]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[17]\"]\nset_property PACKAGE_PIN \"T3\" [get_ports \"DDR_DQ[17]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[17]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[17]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[16]\"]\nset_property PACKAGE_PIN \"M1\" [get_ports \"DDR_DQ[16]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[16]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[16]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[15]\"]\nset_property PACKAGE_PIN \"K3\" [get_ports \"DDR_DQ[15]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[15]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[15]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[14]\"]\nset_property PACKAGE_PIN \"J1\" [get_ports \"DDR_DQ[14]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[14]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[14]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[13]\"]\nset_property PACKAGE_PIN \"K1\" [get_ports \"DDR_DQ[13]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[13]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[13]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[12]\"]\nset_property PACKAGE_PIN \"L3\" [get_ports \"DDR_DQ[12]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[12]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[12]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[11]\"]\nset_property PACKAGE_PIN \"L2\" [get_ports \"DDR_DQ[11]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[11]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[11]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[10]\"]\nset_property PACKAGE_PIN \"L1\" [get_ports \"DDR_DQ[10]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[10]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[10]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[0]\"]\nset_property PACKAGE_PIN \"D1\" [get_ports \"DDR_DQ[0]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[0]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[0]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DM[3]\"]\nset_property PACKAGE_PIN \"AA2\" [get_ports \"DDR_DM[3]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DM[3]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DM[3]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DM[2]\"]\nset_property PACKAGE_PIN \"P1\" [get_ports \"DDR_DM[2]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DM[2]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DM[2]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DM[1]\"]\nset_property PACKAGE_PIN \"H3\" [get_ports \"DDR_DM[1]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DM[1]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DM[1]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DM[0]\"]\nset_property PACKAGE_PIN \"B1\" [get_ports \"DDR_DM[0]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DM[0]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DM[0]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_CS_n\"]\nset_property PACKAGE_PIN \"P6\" [get_ports \"DDR_CS_n\"]\nset_property slew \"SLOW\" [get_ports \"DDR_CS_n\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_CS_n\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_CKE\"]\nset_property PACKAGE_PIN \"V3\" [get_ports \"DDR_CKE\"]\nset_property slew \"SLOW\" [get_ports \"DDR_CKE\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_CKE\"]\nset_property iostandard \"DIFF_SSTL15\" [get_ports \"DDR_Clk_p\"]\nset_property PACKAGE_PIN \"N4\" [get_ports \"DDR_Clk_p\"]\nset_property slew \"FAST\" [get_ports \"DDR_Clk_p\"]\nset_property PIO_DIRECTION \"INPUT\" [get_ports \"DDR_Clk_p\"]\nset_property iostandard \"DIFF_SSTL15\" [get_ports \"DDR_Clk_n\"]\nset_property PACKAGE_PIN \"N5\" [get_ports \"DDR_Clk_n\"]\nset_property slew \"FAST\" [get_ports \"DDR_Clk_n\"]\nset_property PIO_DIRECTION \"INPUT\" [get_ports \"DDR_Clk_n\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_CAS_n\"]\nset_property PACKAGE_PIN \"P3\" [get_ports \"DDR_CAS_n\"]\nset_property slew \"SLOW\" [get_ports \"DDR_CAS_n\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_CAS_n\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_BankAddr[2]\"]\nset_property PACKAGE_PIN \"M6\" [get_ports \"DDR_BankAddr[2]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_BankAddr[2]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_BankAddr[2]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_BankAddr[1]\"]\nset_property PACKAGE_PIN \"L6\" [get_ports \"DDR_BankAddr[1]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_BankAddr[1]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_BankAddr[1]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_BankAddr[0]\"]\nset_property PACKAGE_PIN \"L7\" [get_ports \"DDR_BankAddr[0]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_BankAddr[0]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_BankAddr[0]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_Addr[9]\"]\nset_property PACKAGE_PIN \"H5\" [get_ports \"DDR_Addr[9]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_Addr[9]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_Addr[9]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_Addr[8]\"]\nset_property PACKAGE_PIN \"J5\" [get_ports \"DDR_Addr[8]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_Addr[8]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_Addr[8]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_Addr[7]\"]\nset_property PACKAGE_PIN \"J6\" [get_ports \"DDR_Addr[7]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_Addr[7]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_Addr[7]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_Addr[6]\"]\nset_property PACKAGE_PIN \"J7\" [get_ports \"DDR_Addr[6]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_Addr[6]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_Addr[6]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_Addr[5]\"]\nset_property PACKAGE_PIN \"K5\" [get_ports \"DDR_Addr[5]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_Addr[5]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_Addr[5]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_Addr[4]\"]\nset_property PACKAGE_PIN \"K6\" [get_ports \"DDR_Addr[4]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_Addr[4]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_Addr[4]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_Addr[3]\"]\nset_property PACKAGE_PIN \"L4\" [get_ports \"DDR_Addr[3]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_Addr[3]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_Addr[3]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_Addr[2]\"]\nset_property PACKAGE_PIN \"K4\" [get_ports \"DDR_Addr[2]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_Addr[2]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_Addr[2]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_Addr[1]\"]\nset_property PACKAGE_PIN \"M5\" [get_ports \"DDR_Addr[1]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_Addr[1]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_Addr[1]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_Addr[14]\"]\nset_property PACKAGE_PIN \"G4\" [get_ports \"DDR_Addr[14]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_Addr[14]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_Addr[14]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_Addr[13]\"]\nset_property PACKAGE_PIN \"F4\" [get_ports \"DDR_Addr[13]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_Addr[13]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_Addr[13]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_Addr[12]\"]\nset_property PACKAGE_PIN \"H4\" [get_ports \"DDR_Addr[12]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_Addr[12]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_Addr[12]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_Addr[11]\"]\nset_property PACKAGE_PIN \"G5\" [get_ports \"DDR_Addr[11]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_Addr[11]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_Addr[11]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_Addr[10]\"]\nset_property PACKAGE_PIN \"J3\" [get_ports \"DDR_Addr[10]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_Addr[10]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_Addr[10]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_Addr[0]\"]\nset_property PACKAGE_PIN \"M4\" [get_ports \"DDR_Addr[0]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_Addr[0]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_Addr[0]\"]\n\n"
  },
  {
    "path": "constraints/xilinx/ok/zc7z020clg484.xdc",
    "content": "############################################################################\n##\n##  Xilinx, Inc. 2006            www.xilinx.com\n############################################################################\n##  File name :       ps7_constraints.xdc\n##\n##  Details :     Constraints file\n##                    FPGA family:       zynq\n##                    FPGA:              xc7z020clg484-1\n##                    Device Size:        xc7z020\n##                    Package:            clg484\n##                    Speedgrade:         -1\n##\n##\n############################################################################\n############################################################################\n############################################################################\n# Clock constraints                                                        #\n############################################################################\ncreate_clock -name clk_fpga_0 -period \"10\" [get_pins \"*ps7_foo/FCLKCLK[0]\"]\nset_input_jitter clk_fpga_0 0.6\nset_clock_groups -asynchronous -group {clk_fpga_0}\ncreate_clock -name clk_fpga_1 -period \"6\" [get_pins \"*ps7_foo/FCLKCLK[1]\"]\nset_input_jitter clk_fpga_1 0.6\nset_clock_groups -asynchronous -group {clk_fpga_1}\ncreate_clock -name clk_fpga_3 -period \"5\" [get_pins \"*ps7_foo/FCLKCLK[3]\"]\nset_input_jitter clk_fpga_3 0.6\nset_clock_groups -asynchronous -group {clk_fpga_3}\n\n############################################################################\n# I/O STANDARDS and Location Constraints                                   #\n############################################################################\n\nset_property iostandard \"SSTL15\" [get_ports \"DDR_WEB\"]\nset_property PACKAGE_PIN \"R4\" [get_ports \"DDR_WEB\"]\nset_property slew \"SLOW\" [get_ports \"DDR_WEB\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_WEB\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_RAS_n\"]\nset_property PACKAGE_PIN \"R5\" [get_ports \"DDR_RAS_n\"]\nset_property slew \"SLOW\" [get_ports \"DDR_RAS_n\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_RAS_n\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_ODT\"]\nset_property PACKAGE_PIN \"P5\" [get_ports \"DDR_ODT\"]\nset_property slew \"SLOW\" [get_ports \"DDR_ODT\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_ODT\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_DRSTB\"]\nset_property PACKAGE_PIN \"F3\" [get_ports \"DDR_DRSTB\"]\nset_property slew \"FAST\" [get_ports \"DDR_DRSTB\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DRSTB\"]\nset_property iostandard \"DIFF_SSTL15_T_DCI\" [get_ports \"DDR_DQS_p[3]\"]\nset_property PACKAGE_PIN \"V2\" [get_ports \"DDR_DQS_p[3]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQS_p[3]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQS_p[3]\"]\nset_property iostandard \"DIFF_SSTL15_T_DCI\" [get_ports \"DDR_DQS_p[2]\"]\nset_property PACKAGE_PIN \"N2\" [get_ports \"DDR_DQS_p[2]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQS_p[2]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQS_p[2]\"]\nset_property iostandard \"DIFF_SSTL15_T_DCI\" [get_ports \"DDR_DQS_p[1]\"]\nset_property PACKAGE_PIN \"H2\" [get_ports \"DDR_DQS_p[1]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQS_p[1]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQS_p[1]\"]\nset_property iostandard \"DIFF_SSTL15_T_DCI\" [get_ports \"DDR_DQS_p[0]\"]\nset_property PACKAGE_PIN \"C2\" [get_ports \"DDR_DQS_p[0]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQS_p[0]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQS_p[0]\"]\nset_property iostandard \"DIFF_SSTL15_T_DCI\" [get_ports \"DDR_DQS_n[3]\"]\nset_property PACKAGE_PIN \"W2\" [get_ports \"DDR_DQS_n[3]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQS_n[3]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQS_n[3]\"]\nset_property iostandard \"DIFF_SSTL15_T_DCI\" [get_ports \"DDR_DQS_n[2]\"]\nset_property PACKAGE_PIN \"P2\" [get_ports \"DDR_DQS_n[2]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQS_n[2]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQS_n[2]\"]\nset_property iostandard \"DIFF_SSTL15_T_DCI\" [get_ports \"DDR_DQS_n[1]\"]\nset_property PACKAGE_PIN \"J2\" [get_ports \"DDR_DQS_n[1]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQS_n[1]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQS_n[1]\"]\nset_property iostandard \"DIFF_SSTL15_T_DCI\" [get_ports \"DDR_DQS_n[0]\"]\nset_property PACKAGE_PIN \"D2\" [get_ports \"DDR_DQS_n[0]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQS_n[0]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQS_n[0]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[9]\"]\nset_property PACKAGE_PIN \"G1\" [get_ports \"DDR_DQ[9]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[9]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[9]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[8]\"]\nset_property PACKAGE_PIN \"G2\" [get_ports \"DDR_DQ[8]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[8]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[8]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[7]\"]\nset_property PACKAGE_PIN \"F1\" [get_ports \"DDR_DQ[7]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[7]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[7]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[6]\"]\nset_property PACKAGE_PIN \"F2\" [get_ports \"DDR_DQ[6]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[6]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[6]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[5]\"]\nset_property PACKAGE_PIN \"E1\" [get_ports \"DDR_DQ[5]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[5]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[5]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[4]\"]\nset_property PACKAGE_PIN \"E3\" [get_ports \"DDR_DQ[4]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[4]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[4]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[3]\"]\nset_property PACKAGE_PIN \"D3\" [get_ports \"DDR_DQ[3]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[3]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[3]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[31]\"]\nset_property PACKAGE_PIN \"Y1\" [get_ports \"DDR_DQ[31]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[31]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[31]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[30]\"]\nset_property PACKAGE_PIN \"W3\" [get_ports \"DDR_DQ[30]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[30]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[30]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[2]\"]\nset_property PACKAGE_PIN \"B2\" [get_ports \"DDR_DQ[2]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[2]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[2]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[29]\"]\nset_property PACKAGE_PIN \"Y3\" [get_ports \"DDR_DQ[29]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[29]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[29]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[28]\"]\nset_property PACKAGE_PIN \"W1\" [get_ports \"DDR_DQ[28]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[28]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[28]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[27]\"]\nset_property PACKAGE_PIN \"U2\" [get_ports \"DDR_DQ[27]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[27]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[27]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[26]\"]\nset_property PACKAGE_PIN \"AA1\" [get_ports \"DDR_DQ[26]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[26]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[26]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[25]\"]\nset_property PACKAGE_PIN \"U1\" [get_ports \"DDR_DQ[25]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[25]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[25]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[24]\"]\nset_property PACKAGE_PIN \"AA3\" [get_ports \"DDR_DQ[24]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[24]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[24]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[23]\"]\nset_property PACKAGE_PIN \"R1\" [get_ports \"DDR_DQ[23]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[23]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[23]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[22]\"]\nset_property PACKAGE_PIN \"M2\" [get_ports \"DDR_DQ[22]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[22]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[22]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[21]\"]\nset_property PACKAGE_PIN \"T2\" [get_ports \"DDR_DQ[21]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[21]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[21]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[20]\"]\nset_property PACKAGE_PIN \"R3\" [get_ports \"DDR_DQ[20]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[20]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[20]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[1]\"]\nset_property PACKAGE_PIN \"C3\" [get_ports \"DDR_DQ[1]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[1]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[1]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[19]\"]\nset_property PACKAGE_PIN \"T1\" [get_ports \"DDR_DQ[19]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[19]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[19]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[18]\"]\nset_property PACKAGE_PIN \"N3\" [get_ports \"DDR_DQ[18]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[18]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[18]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[17]\"]\nset_property PACKAGE_PIN \"T3\" [get_ports \"DDR_DQ[17]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[17]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[17]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[16]\"]\nset_property PACKAGE_PIN \"M1\" [get_ports \"DDR_DQ[16]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[16]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[16]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[15]\"]\nset_property PACKAGE_PIN \"K3\" [get_ports \"DDR_DQ[15]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[15]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[15]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[14]\"]\nset_property PACKAGE_PIN \"J1\" [get_ports \"DDR_DQ[14]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[14]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[14]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[13]\"]\nset_property PACKAGE_PIN \"K1\" [get_ports \"DDR_DQ[13]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[13]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[13]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[12]\"]\nset_property PACKAGE_PIN \"L3\" [get_ports \"DDR_DQ[12]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[12]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[12]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[11]\"]\nset_property PACKAGE_PIN \"L2\" [get_ports \"DDR_DQ[11]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[11]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[11]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[10]\"]\nset_property PACKAGE_PIN \"L1\" [get_ports \"DDR_DQ[10]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[10]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[10]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[0]\"]\nset_property PACKAGE_PIN \"D1\" [get_ports \"DDR_DQ[0]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[0]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[0]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DM[3]\"]\nset_property PACKAGE_PIN \"AA2\" [get_ports \"DDR_DM[3]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DM[3]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DM[3]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DM[2]\"]\nset_property PACKAGE_PIN \"P1\" [get_ports \"DDR_DM[2]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DM[2]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DM[2]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DM[1]\"]\nset_property PACKAGE_PIN \"H3\" [get_ports \"DDR_DM[1]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DM[1]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DM[1]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DM[0]\"]\nset_property PACKAGE_PIN \"B1\" [get_ports \"DDR_DM[0]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DM[0]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DM[0]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_CS_n\"]\nset_property PACKAGE_PIN \"P6\" [get_ports \"DDR_CS_n\"]\nset_property slew \"SLOW\" [get_ports \"DDR_CS_n\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_CS_n\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_CKE\"]\nset_property PACKAGE_PIN \"V3\" [get_ports \"DDR_CKE\"]\nset_property slew \"SLOW\" [get_ports \"DDR_CKE\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_CKE\"]\nset_property iostandard \"DIFF_SSTL15\" [get_ports \"DDR_Clk_p\"]\nset_property PACKAGE_PIN \"N4\" [get_ports \"DDR_Clk_p\"]\nset_property slew \"FAST\" [get_ports \"DDR_Clk_p\"]\nset_property PIO_DIRECTION \"INPUT\" [get_ports \"DDR_Clk_p\"]\nset_property iostandard \"DIFF_SSTL15\" [get_ports \"DDR_Clk_n\"]\nset_property PACKAGE_PIN \"N5\" [get_ports \"DDR_Clk_n\"]\nset_property slew \"FAST\" [get_ports \"DDR_Clk_n\"]\nset_property PIO_DIRECTION \"INPUT\" [get_ports \"DDR_Clk_n\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_CAS_n\"]\nset_property PACKAGE_PIN \"P3\" [get_ports \"DDR_CAS_n\"]\nset_property slew \"SLOW\" [get_ports \"DDR_CAS_n\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_CAS_n\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_BankAddr[2]\"]\nset_property PACKAGE_PIN \"M6\" [get_ports \"DDR_BankAddr[2]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_BankAddr[2]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_BankAddr[2]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_BankAddr[1]\"]\nset_property PACKAGE_PIN \"L6\" [get_ports \"DDR_BankAddr[1]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_BankAddr[1]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_BankAddr[1]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_BankAddr[0]\"]\nset_property PACKAGE_PIN \"L7\" [get_ports \"DDR_BankAddr[0]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_BankAddr[0]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_BankAddr[0]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_Addr[9]\"]\nset_property PACKAGE_PIN \"H5\" [get_ports \"DDR_Addr[9]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_Addr[9]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_Addr[9]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_Addr[8]\"]\nset_property PACKAGE_PIN \"J5\" [get_ports \"DDR_Addr[8]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_Addr[8]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_Addr[8]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_Addr[7]\"]\nset_property PACKAGE_PIN \"J6\" [get_ports \"DDR_Addr[7]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_Addr[7]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_Addr[7]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_Addr[6]\"]\nset_property PACKAGE_PIN \"J7\" [get_ports \"DDR_Addr[6]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_Addr[6]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_Addr[6]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_Addr[5]\"]\nset_property PACKAGE_PIN \"K5\" [get_ports \"DDR_Addr[5]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_Addr[5]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_Addr[5]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_Addr[4]\"]\nset_property PACKAGE_PIN \"K6\" [get_ports \"DDR_Addr[4]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_Addr[4]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_Addr[4]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_Addr[3]\"]\nset_property PACKAGE_PIN \"L4\" [get_ports \"DDR_Addr[3]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_Addr[3]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_Addr[3]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_Addr[2]\"]\nset_property PACKAGE_PIN \"K4\" [get_ports \"DDR_Addr[2]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_Addr[2]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_Addr[2]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_Addr[1]\"]\nset_property PACKAGE_PIN \"M5\" [get_ports \"DDR_Addr[1]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_Addr[1]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_Addr[1]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_Addr[14]\"]\nset_property PACKAGE_PIN \"G4\" [get_ports \"DDR_Addr[14]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_Addr[14]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_Addr[14]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_Addr[13]\"]\nset_property PACKAGE_PIN \"F4\" [get_ports \"DDR_Addr[13]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_Addr[13]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_Addr[13]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_Addr[12]\"]\nset_property PACKAGE_PIN \"H4\" [get_ports \"DDR_Addr[12]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_Addr[12]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_Addr[12]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_Addr[11]\"]\nset_property PACKAGE_PIN \"G5\" [get_ports \"DDR_Addr[11]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_Addr[11]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_Addr[11]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_Addr[10]\"]\nset_property PACKAGE_PIN \"J3\" [get_ports \"DDR_Addr[10]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_Addr[10]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_Addr[10]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_Addr[0]\"]\nset_property PACKAGE_PIN \"M4\" [get_ports \"DDR_Addr[0]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_Addr[0]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_Addr[0]\"]\n\n"
  },
  {
    "path": "constraints/xilinx/ok/zc7z045ffg900.xdc",
    "content": "############################################################################\n##\n##  Xilinx, Inc. 2006            www.xilinx.com\n############################################################################\n##  File name :       ps7_constraints.xdc\n##\n##  Details :     Constraints file\n##                    FPGA family:       zynq\n##                    FPGA:              xc7z045ffg900-2\n##                    Device Size:        xc7z045\n##                    Package:            ffg900\n##                    Speedgrade:         -2\n##\n##\n############################################################################\n############################################################################\n############################################################################\n# Clock constraints                                                        #\n############################################################################\ncreate_clock -name clk_fpga_0 -period \"5\" [get_pins \"*ps7_foo/FCLKCLK[0]\"]\nset_input_jitter clk_fpga_0 0.6\nset_clock_groups -asynchronous -group {clk_fpga_0}\ncreate_clock -name clk_fpga_1 -period \"6\" [get_pins \"*ps7_foo/FCLKCLK[1]\"]\nset_input_jitter clk_fpga_1 0.6\nset_clock_groups -asynchronous -group {clk_fpga_1}\ncreate_clock -name clk_fpga_3 -period \"5\" [get_pins \"*ps7_foo/FCLKCLK[3]\"]\nset_input_jitter clk_fpga_3 0.6\nset_clock_groups -asynchronous -group {clk_fpga_3}\n\n############################################################################\n# I/O STANDARDS and Location Constraints                                   #\n############################################################################\n\nset_property iostandard \"SSTL15\" [get_ports \"DDR_WEB\"]\nset_property PACKAGE_PIN \"N23\" [get_ports \"DDR_WEB\"]\nset_property slew \"SLOW\" [get_ports \"DDR_WEB\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_WEB\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_RAS_n\"]\nset_property PACKAGE_PIN \"N24\" [get_ports \"DDR_RAS_n\"]\nset_property slew \"SLOW\" [get_ports \"DDR_RAS_n\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_RAS_n\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_ODT\"]\nset_property PACKAGE_PIN \"L23\" [get_ports \"DDR_ODT\"]\nset_property slew \"SLOW\" [get_ports \"DDR_ODT\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_ODT\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_DRSTB\"]\nset_property PACKAGE_PIN \"F25\" [get_ports \"DDR_DRSTB\"]\nset_property slew \"FAST\" [get_ports \"DDR_DRSTB\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DRSTB\"]\nset_property iostandard \"DIFF_SSTL15_T_DCI\" [get_ports \"DDR_DQS_p[3]\"]\nset_property PACKAGE_PIN \"L28\" [get_ports \"DDR_DQS_p[3]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQS_p[3]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQS_p[3]\"]\nset_property iostandard \"DIFF_SSTL15_T_DCI\" [get_ports \"DDR_DQS_p[2]\"]\nset_property PACKAGE_PIN \"G29\" [get_ports \"DDR_DQS_p[2]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQS_p[2]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQS_p[2]\"]\nset_property iostandard \"DIFF_SSTL15_T_DCI\" [get_ports \"DDR_DQS_p[1]\"]\nset_property PACKAGE_PIN \"C29\" [get_ports \"DDR_DQS_p[1]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQS_p[1]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQS_p[1]\"]\nset_property iostandard \"DIFF_SSTL15_T_DCI\" [get_ports \"DDR_DQS_p[0]\"]\nset_property PACKAGE_PIN \"C26\" [get_ports \"DDR_DQS_p[0]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQS_p[0]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQS_p[0]\"]\nset_property iostandard \"DIFF_SSTL15_T_DCI\" [get_ports \"DDR_DQS_n[3]\"]\nset_property PACKAGE_PIN \"L29\" [get_ports \"DDR_DQS_n[3]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQS_n[3]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQS_n[3]\"]\nset_property iostandard \"DIFF_SSTL15_T_DCI\" [get_ports \"DDR_DQS_n[2]\"]\nset_property PACKAGE_PIN \"F29\" [get_ports \"DDR_DQS_n[2]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQS_n[2]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQS_n[2]\"]\nset_property iostandard \"DIFF_SSTL15_T_DCI\" [get_ports \"DDR_DQS_n[1]\"]\nset_property PACKAGE_PIN \"B29\" [get_ports \"DDR_DQS_n[1]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQS_n[1]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQS_n[1]\"]\nset_property iostandard \"DIFF_SSTL15_T_DCI\" [get_ports \"DDR_DQS_n[0]\"]\nset_property PACKAGE_PIN \"B26\" [get_ports \"DDR_DQS_n[0]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQS_n[0]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQS_n[0]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[9]\"]\nset_property PACKAGE_PIN \"A28\" [get_ports \"DDR_DQ[9]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[9]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[9]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[8]\"]\nset_property PACKAGE_PIN \"A27\" [get_ports \"DDR_DQ[8]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[8]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[8]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[7]\"]\nset_property PACKAGE_PIN \"B27\" [get_ports \"DDR_DQ[7]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[7]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[7]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[6]\"]\nset_property PACKAGE_PIN \"D25\" [get_ports \"DDR_DQ[6]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[6]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[6]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[5]\"]\nset_property PACKAGE_PIN \"B25\" [get_ports \"DDR_DQ[5]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[5]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[5]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[4]\"]\nset_property PACKAGE_PIN \"D26\" [get_ports \"DDR_DQ[4]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[4]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[4]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[3]\"]\nset_property PACKAGE_PIN \"E25\" [get_ports \"DDR_DQ[3]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[3]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[3]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[31]\"]\nset_property PACKAGE_PIN \"M30\" [get_ports \"DDR_DQ[31]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[31]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[31]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[30]\"]\nset_property PACKAGE_PIN \"L30\" [get_ports \"DDR_DQ[30]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[30]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[30]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[2]\"]\nset_property PACKAGE_PIN \"E27\" [get_ports \"DDR_DQ[2]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[2]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[2]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[29]\"]\nset_property PACKAGE_PIN \"M29\" [get_ports \"DDR_DQ[29]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[29]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[29]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[28]\"]\nset_property PACKAGE_PIN \"K30\" [get_ports \"DDR_DQ[28]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[28]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[28]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[27]\"]\nset_property PACKAGE_PIN \"J29\" [get_ports \"DDR_DQ[27]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[27]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[27]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[26]\"]\nset_property PACKAGE_PIN \"J28\" [get_ports \"DDR_DQ[26]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[26]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[26]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[25]\"]\nset_property PACKAGE_PIN \"J30\" [get_ports \"DDR_DQ[25]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[25]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[25]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[24]\"]\nset_property PACKAGE_PIN \"K27\" [get_ports \"DDR_DQ[24]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[24]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[24]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[23]\"]\nset_property PACKAGE_PIN \"F30\" [get_ports \"DDR_DQ[23]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[23]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[23]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[22]\"]\nset_property PACKAGE_PIN \"G30\" [get_ports \"DDR_DQ[22]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[22]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[22]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[21]\"]\nset_property PACKAGE_PIN \"F28\" [get_ports \"DDR_DQ[21]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[21]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[21]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[20]\"]\nset_property PACKAGE_PIN \"E30\" [get_ports \"DDR_DQ[20]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[20]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[20]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[1]\"]\nset_property PACKAGE_PIN \"A25\" [get_ports \"DDR_DQ[1]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[1]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[1]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[19]\"]\nset_property PACKAGE_PIN \"E28\" [get_ports \"DDR_DQ[19]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[19]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[19]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[18]\"]\nset_property PACKAGE_PIN \"H28\" [get_ports \"DDR_DQ[18]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[18]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[18]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[17]\"]\nset_property PACKAGE_PIN \"G27\" [get_ports \"DDR_DQ[17]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[17]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[17]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[16]\"]\nset_property PACKAGE_PIN \"H27\" [get_ports \"DDR_DQ[16]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[16]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[16]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[15]\"]\nset_property PACKAGE_PIN \"D28\" [get_ports \"DDR_DQ[15]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[15]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[15]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[14]\"]\nset_property PACKAGE_PIN \"D29\" [get_ports \"DDR_DQ[14]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[14]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[14]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[13]\"]\nset_property PACKAGE_PIN \"A30\" [get_ports \"DDR_DQ[13]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[13]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[13]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[12]\"]\nset_property PACKAGE_PIN \"D30\" [get_ports \"DDR_DQ[12]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[12]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[12]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[11]\"]\nset_property PACKAGE_PIN \"C28\" [get_ports \"DDR_DQ[11]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[11]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[11]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[10]\"]\nset_property PACKAGE_PIN \"A29\" [get_ports \"DDR_DQ[10]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[10]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[10]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[0]\"]\nset_property PACKAGE_PIN \"E26\" [get_ports \"DDR_DQ[0]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[0]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[0]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DM[3]\"]\nset_property PACKAGE_PIN \"K28\" [get_ports \"DDR_DM[3]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DM[3]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DM[3]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DM[2]\"]\nset_property PACKAGE_PIN \"H29\" [get_ports \"DDR_DM[2]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DM[2]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DM[2]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DM[1]\"]\nset_property PACKAGE_PIN \"B30\" [get_ports \"DDR_DM[1]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DM[1]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DM[1]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DM[0]\"]\nset_property PACKAGE_PIN \"C27\" [get_ports \"DDR_DM[0]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DM[0]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DM[0]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_CS_n\"]\nset_property PACKAGE_PIN \"N22\" [get_ports \"DDR_CS_n\"]\nset_property slew \"SLOW\" [get_ports \"DDR_CS_n\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_CS_n\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_CKE\"]\nset_property PACKAGE_PIN \"M22\" [get_ports \"DDR_CKE\"]\nset_property slew \"SLOW\" [get_ports \"DDR_CKE\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_CKE\"]\nset_property iostandard \"DIFF_SSTL15\" [get_ports \"DDR_Clk_p\"]\nset_property PACKAGE_PIN \"K25\" [get_ports \"DDR_Clk_p\"]\nset_property slew \"FAST\" [get_ports \"DDR_Clk_p\"]\nset_property PIO_DIRECTION \"INPUT\" [get_ports \"DDR_Clk_p\"]\nset_property iostandard \"DIFF_SSTL15\" [get_ports \"DDR_Clk_n\"]\nset_property PACKAGE_PIN \"J25\" [get_ports \"DDR_Clk_n\"]\nset_property slew \"FAST\" [get_ports \"DDR_Clk_n\"]\nset_property PIO_DIRECTION \"INPUT\" [get_ports \"DDR_Clk_n\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_CAS_n\"]\nset_property PACKAGE_PIN \"M24\" [get_ports \"DDR_CAS_n\"]\nset_property slew \"SLOW\" [get_ports \"DDR_CAS_n\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_CAS_n\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_BankAddr[2]\"]\nset_property PACKAGE_PIN \"M25\" [get_ports \"DDR_BankAddr[2]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_BankAddr[2]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_BankAddr[2]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_BankAddr[1]\"]\nset_property PACKAGE_PIN \"M26\" [get_ports \"DDR_BankAddr[1]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_BankAddr[1]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_BankAddr[1]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_BankAddr[0]\"]\nset_property PACKAGE_PIN \"M27\" [get_ports \"DDR_BankAddr[0]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_BankAddr[0]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_BankAddr[0]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_Addr[9]\"]\nset_property PACKAGE_PIN \"J23\" [get_ports \"DDR_Addr[9]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_Addr[9]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_Addr[9]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_Addr[8]\"]\nset_property PACKAGE_PIN \"F27\" [get_ports \"DDR_Addr[8]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_Addr[8]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_Addr[8]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_Addr[7]\"]\nset_property PACKAGE_PIN \"K22\" [get_ports \"DDR_Addr[7]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_Addr[7]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_Addr[7]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_Addr[6]\"]\nset_property PACKAGE_PIN \"H26\" [get_ports \"DDR_Addr[6]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_Addr[6]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_Addr[6]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_Addr[5]\"]\nset_property PACKAGE_PIN \"G24\" [get_ports \"DDR_Addr[5]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_Addr[5]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_Addr[5]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_Addr[4]\"]\nset_property PACKAGE_PIN \"J26\" [get_ports \"DDR_Addr[4]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_Addr[4]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_Addr[4]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_Addr[3]\"]\nset_property PACKAGE_PIN \"G25\" [get_ports \"DDR_Addr[3]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_Addr[3]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_Addr[3]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_Addr[2]\"]\nset_property PACKAGE_PIN \"L27\" [get_ports \"DDR_Addr[2]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_Addr[2]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_Addr[2]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_Addr[1]\"]\nset_property PACKAGE_PIN \"K26\" [get_ports \"DDR_Addr[1]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_Addr[1]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_Addr[1]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_Addr[14]\"]\nset_property PACKAGE_PIN \"J24\" [get_ports \"DDR_Addr[14]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_Addr[14]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_Addr[14]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_Addr[13]\"]\nset_property PACKAGE_PIN \"H23\" [get_ports \"DDR_Addr[13]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_Addr[13]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_Addr[13]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_Addr[12]\"]\nset_property PACKAGE_PIN \"K23\" [get_ports \"DDR_Addr[12]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_Addr[12]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_Addr[12]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_Addr[11]\"]\nset_property PACKAGE_PIN \"H24\" [get_ports \"DDR_Addr[11]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_Addr[11]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_Addr[11]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_Addr[10]\"]\nset_property PACKAGE_PIN \"G26\" [get_ports \"DDR_Addr[10]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_Addr[10]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_Addr[10]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_Addr[0]\"]\nset_property PACKAGE_PIN \"L25\" [get_ports \"DDR_Addr[0]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_Addr[0]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_Addr[0]\"]\n\n"
  },
  {
    "path": "constraints/xilinx/ok/zc7z100ffg900.xdc",
    "content": "############################################################################\n##\n##  Xilinx, Inc. 2006            www.xilinx.com\n############################################################################\n##  File name :       ps7_constraints.xdc\n##\n##  Details :     Constraints file\n##                    FPGA family:       zynq\n##                    FPGA:              xc7z045ffg900-2\n##                    Device Size:        xc7z045\n##                    Package:            ffg900\n##                    Speedgrade:         -2\n##\n##\n############################################################################\n############################################################################\n############################################################################\n# Clock constraints                                                        #\n############################################################################\ncreate_clock -name clk_fpga_0 -period \"5\" [get_pins \"*ps7_foo/FCLKCLK[0]\"]\nset_input_jitter clk_fpga_0 0.6\nset_clock_groups -asynchronous -group {clk_fpga_0}\ncreate_clock -name clk_fpga_1 -period \"6\" [get_pins \"*ps7_foo/FCLKCLK[1]\"]\nset_input_jitter clk_fpga_1 0.6\nset_clock_groups -asynchronous -group {clk_fpga_1}\ncreate_clock -name clk_fpga_3 -period \"5\" [get_pins \"*ps7_foo/FCLKCLK[3]\"]\nset_input_jitter clk_fpga_3 0.6\nset_clock_groups -asynchronous -group {clk_fpga_3}\n\n############################################################################\n# I/O STANDARDS and Location Constraints                                   #\n############################################################################\n\nset_property iostandard \"SSTL15\" [get_ports \"DDR_WEB\"]\nset_property PACKAGE_PIN \"N23\" [get_ports \"DDR_WEB\"]\nset_property slew \"SLOW\" [get_ports \"DDR_WEB\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_WEB\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_RAS_n\"]\nset_property PACKAGE_PIN \"N24\" [get_ports \"DDR_RAS_n\"]\nset_property slew \"SLOW\" [get_ports \"DDR_RAS_n\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_RAS_n\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_ODT\"]\nset_property PACKAGE_PIN \"L23\" [get_ports \"DDR_ODT\"]\nset_property slew \"SLOW\" [get_ports \"DDR_ODT\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_ODT\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_DRSTB\"]\nset_property PACKAGE_PIN \"F25\" [get_ports \"DDR_DRSTB\"]\nset_property slew \"FAST\" [get_ports \"DDR_DRSTB\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DRSTB\"]\nset_property iostandard \"DIFF_SSTL15_T_DCI\" [get_ports \"DDR_DQS_p[3]\"]\nset_property PACKAGE_PIN \"L28\" [get_ports \"DDR_DQS_p[3]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQS_p[3]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQS_p[3]\"]\nset_property iostandard \"DIFF_SSTL15_T_DCI\" [get_ports \"DDR_DQS_p[2]\"]\nset_property PACKAGE_PIN \"G29\" [get_ports \"DDR_DQS_p[2]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQS_p[2]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQS_p[2]\"]\nset_property iostandard \"DIFF_SSTL15_T_DCI\" [get_ports \"DDR_DQS_p[1]\"]\nset_property PACKAGE_PIN \"C29\" [get_ports \"DDR_DQS_p[1]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQS_p[1]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQS_p[1]\"]\nset_property iostandard \"DIFF_SSTL15_T_DCI\" [get_ports \"DDR_DQS_p[0]\"]\nset_property PACKAGE_PIN \"C26\" [get_ports \"DDR_DQS_p[0]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQS_p[0]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQS_p[0]\"]\nset_property iostandard \"DIFF_SSTL15_T_DCI\" [get_ports \"DDR_DQS_n[3]\"]\nset_property PACKAGE_PIN \"L29\" [get_ports \"DDR_DQS_n[3]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQS_n[3]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQS_n[3]\"]\nset_property iostandard \"DIFF_SSTL15_T_DCI\" [get_ports \"DDR_DQS_n[2]\"]\nset_property PACKAGE_PIN \"F29\" [get_ports \"DDR_DQS_n[2]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQS_n[2]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQS_n[2]\"]\nset_property iostandard \"DIFF_SSTL15_T_DCI\" [get_ports \"DDR_DQS_n[1]\"]\nset_property PACKAGE_PIN \"B29\" [get_ports \"DDR_DQS_n[1]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQS_n[1]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQS_n[1]\"]\nset_property iostandard \"DIFF_SSTL15_T_DCI\" [get_ports \"DDR_DQS_n[0]\"]\nset_property PACKAGE_PIN \"B26\" [get_ports \"DDR_DQS_n[0]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQS_n[0]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQS_n[0]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[9]\"]\nset_property PACKAGE_PIN \"A28\" [get_ports \"DDR_DQ[9]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[9]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[9]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[8]\"]\nset_property PACKAGE_PIN \"A27\" [get_ports \"DDR_DQ[8]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[8]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[8]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[7]\"]\nset_property PACKAGE_PIN \"B27\" [get_ports \"DDR_DQ[7]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[7]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[7]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[6]\"]\nset_property PACKAGE_PIN \"D25\" [get_ports \"DDR_DQ[6]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[6]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[6]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[5]\"]\nset_property PACKAGE_PIN \"B25\" [get_ports \"DDR_DQ[5]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[5]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[5]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[4]\"]\nset_property PACKAGE_PIN \"D26\" [get_ports \"DDR_DQ[4]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[4]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[4]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[3]\"]\nset_property PACKAGE_PIN \"E25\" [get_ports \"DDR_DQ[3]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[3]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[3]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[31]\"]\nset_property PACKAGE_PIN \"M30\" [get_ports \"DDR_DQ[31]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[31]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[31]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[30]\"]\nset_property PACKAGE_PIN \"L30\" [get_ports \"DDR_DQ[30]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[30]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[30]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[2]\"]\nset_property PACKAGE_PIN \"E27\" [get_ports \"DDR_DQ[2]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[2]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[2]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[29]\"]\nset_property PACKAGE_PIN \"M29\" [get_ports \"DDR_DQ[29]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[29]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[29]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[28]\"]\nset_property PACKAGE_PIN \"K30\" [get_ports \"DDR_DQ[28]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[28]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[28]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[27]\"]\nset_property PACKAGE_PIN \"J29\" [get_ports \"DDR_DQ[27]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[27]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[27]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[26]\"]\nset_property PACKAGE_PIN \"J28\" [get_ports \"DDR_DQ[26]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[26]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[26]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[25]\"]\nset_property PACKAGE_PIN \"J30\" [get_ports \"DDR_DQ[25]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[25]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[25]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[24]\"]\nset_property PACKAGE_PIN \"K27\" [get_ports \"DDR_DQ[24]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[24]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[24]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[23]\"]\nset_property PACKAGE_PIN \"F30\" [get_ports \"DDR_DQ[23]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[23]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[23]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[22]\"]\nset_property PACKAGE_PIN \"G30\" [get_ports \"DDR_DQ[22]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[22]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[22]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[21]\"]\nset_property PACKAGE_PIN \"F28\" [get_ports \"DDR_DQ[21]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[21]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[21]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[20]\"]\nset_property PACKAGE_PIN \"E30\" [get_ports \"DDR_DQ[20]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[20]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[20]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[1]\"]\nset_property PACKAGE_PIN \"A25\" [get_ports \"DDR_DQ[1]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[1]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[1]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[19]\"]\nset_property PACKAGE_PIN \"E28\" [get_ports \"DDR_DQ[19]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[19]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[19]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[18]\"]\nset_property PACKAGE_PIN \"H28\" [get_ports \"DDR_DQ[18]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[18]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[18]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[17]\"]\nset_property PACKAGE_PIN \"G27\" [get_ports \"DDR_DQ[17]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[17]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[17]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[16]\"]\nset_property PACKAGE_PIN \"H27\" [get_ports \"DDR_DQ[16]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[16]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[16]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[15]\"]\nset_property PACKAGE_PIN \"D28\" [get_ports \"DDR_DQ[15]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[15]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[15]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[14]\"]\nset_property PACKAGE_PIN \"D29\" [get_ports \"DDR_DQ[14]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[14]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[14]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[13]\"]\nset_property PACKAGE_PIN \"A30\" [get_ports \"DDR_DQ[13]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[13]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[13]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[12]\"]\nset_property PACKAGE_PIN \"D30\" [get_ports \"DDR_DQ[12]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[12]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[12]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[11]\"]\nset_property PACKAGE_PIN \"C28\" [get_ports \"DDR_DQ[11]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[11]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[11]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[10]\"]\nset_property PACKAGE_PIN \"A29\" [get_ports \"DDR_DQ[10]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[10]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[10]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[0]\"]\nset_property PACKAGE_PIN \"E26\" [get_ports \"DDR_DQ[0]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[0]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[0]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DM[3]\"]\nset_property PACKAGE_PIN \"K28\" [get_ports \"DDR_DM[3]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DM[3]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DM[3]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DM[2]\"]\nset_property PACKAGE_PIN \"H29\" [get_ports \"DDR_DM[2]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DM[2]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DM[2]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DM[1]\"]\nset_property PACKAGE_PIN \"B30\" [get_ports \"DDR_DM[1]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DM[1]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DM[1]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DM[0]\"]\nset_property PACKAGE_PIN \"C27\" [get_ports \"DDR_DM[0]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DM[0]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DM[0]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_CS_n\"]\nset_property PACKAGE_PIN \"N22\" [get_ports \"DDR_CS_n\"]\nset_property slew \"SLOW\" [get_ports \"DDR_CS_n\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_CS_n\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_CKE\"]\nset_property PACKAGE_PIN \"M22\" [get_ports \"DDR_CKE\"]\nset_property slew \"SLOW\" [get_ports \"DDR_CKE\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_CKE\"]\nset_property iostandard \"DIFF_SSTL15\" [get_ports \"DDR_Clk_p\"]\nset_property PACKAGE_PIN \"K25\" [get_ports \"DDR_Clk_p\"]\nset_property slew \"FAST\" [get_ports \"DDR_Clk_p\"]\nset_property PIO_DIRECTION \"INPUT\" [get_ports \"DDR_Clk_p\"]\nset_property iostandard \"DIFF_SSTL15\" [get_ports \"DDR_Clk_n\"]\nset_property PACKAGE_PIN \"J25\" [get_ports \"DDR_Clk_n\"]\nset_property slew \"FAST\" [get_ports \"DDR_Clk_n\"]\nset_property PIO_DIRECTION \"INPUT\" [get_ports \"DDR_Clk_n\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_CAS_n\"]\nset_property PACKAGE_PIN \"M24\" [get_ports \"DDR_CAS_n\"]\nset_property slew \"SLOW\" [get_ports \"DDR_CAS_n\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_CAS_n\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_BankAddr[2]\"]\nset_property PACKAGE_PIN \"M25\" [get_ports \"DDR_BankAddr[2]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_BankAddr[2]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_BankAddr[2]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_BankAddr[1]\"]\nset_property PACKAGE_PIN \"M26\" [get_ports \"DDR_BankAddr[1]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_BankAddr[1]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_BankAddr[1]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_BankAddr[0]\"]\nset_property PACKAGE_PIN \"M27\" [get_ports \"DDR_BankAddr[0]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_BankAddr[0]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_BankAddr[0]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_Addr[9]\"]\nset_property PACKAGE_PIN \"J23\" [get_ports \"DDR_Addr[9]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_Addr[9]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_Addr[9]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_Addr[8]\"]\nset_property PACKAGE_PIN \"F27\" [get_ports \"DDR_Addr[8]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_Addr[8]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_Addr[8]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_Addr[7]\"]\nset_property PACKAGE_PIN \"K22\" [get_ports \"DDR_Addr[7]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_Addr[7]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_Addr[7]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_Addr[6]\"]\nset_property PACKAGE_PIN \"H26\" [get_ports \"DDR_Addr[6]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_Addr[6]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_Addr[6]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_Addr[5]\"]\nset_property PACKAGE_PIN \"G24\" [get_ports \"DDR_Addr[5]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_Addr[5]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_Addr[5]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_Addr[4]\"]\nset_property PACKAGE_PIN \"J26\" [get_ports \"DDR_Addr[4]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_Addr[4]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_Addr[4]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_Addr[3]\"]\nset_property PACKAGE_PIN \"G25\" [get_ports \"DDR_Addr[3]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_Addr[3]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_Addr[3]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_Addr[2]\"]\nset_property PACKAGE_PIN \"L27\" [get_ports \"DDR_Addr[2]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_Addr[2]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_Addr[2]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_Addr[1]\"]\nset_property PACKAGE_PIN \"K26\" [get_ports \"DDR_Addr[1]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_Addr[1]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_Addr[1]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_Addr[14]\"]\nset_property PACKAGE_PIN \"J24\" [get_ports \"DDR_Addr[14]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_Addr[14]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_Addr[14]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_Addr[13]\"]\nset_property PACKAGE_PIN \"H23\" [get_ports \"DDR_Addr[13]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_Addr[13]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_Addr[13]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_Addr[12]\"]\nset_property PACKAGE_PIN \"K23\" [get_ports \"DDR_Addr[12]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_Addr[12]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_Addr[12]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_Addr[11]\"]\nset_property PACKAGE_PIN \"H24\" [get_ports \"DDR_Addr[11]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_Addr[11]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_Addr[11]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_Addr[10]\"]\nset_property PACKAGE_PIN \"G26\" [get_ports \"DDR_Addr[10]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_Addr[10]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_Addr[10]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_Addr[0]\"]\nset_property PACKAGE_PIN \"L25\" [get_ports \"DDR_Addr[0]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_Addr[0]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_Addr[0]\"]\n\n"
  },
  {
    "path": "constraints/xilinx/parallella.xdc",
    "content": "# Nothing here, until the standard Parallella stuff gets defined\n"
  },
  {
    "path": "constraints/xilinx/pcie-clocks.xdc",
    "content": "#create_clock -name bscan_refclk -period 20 [get_pins host_pciehost_bscan_bscan/TCK]\ncreate_clock -name pci_refclk -period 10 [get_ports CLK_pci_sys_clk_p]\ncreate_clock -name sys_clk -period 5 [get_ports CLK_sys_clk_p]\n    \ncreate_clock -name sys_clk1_300 -period 3.333 [get_ports CLK_sys_clk1_300_p]\ncreate_clock -name sys_clk2_300 -period 3.333 [get_ports CLK_sys_clk2_300_p]\n\ncreate_clock -name sys_clk_300 -period 3.333 [get_ports CLK_sys_clk_300_p]\ncreate_clock -name sys_clk1_250 -period 4.0 [get_ports CLK_sys_clk1_250_p]\ncreate_clock -name sys_clk2_250 -period 4.0 [get_ports CLK_sys_clk2_250_p]\n\n\n\n\nset_max_delay -from [get_clocks {clkgen_pll_CLKOUT0}] -to   [get_clocks {userclk2}] [get_property PERIOD [get_clocks {userclk2}]] -datapath_only\nset_max_delay -to   [get_clocks {clkgen_pll_CLKOUT0}] -from [get_clocks {userclk2}] [get_property PERIOD [get_clocks {userclk2}]]           -datapath_only\n\nset_max_delay -from [get_clocks {clkgen_pll_CLKOUT1}] -to   [get_clocks {userclk2}] [get_property PERIOD [get_clocks {userclk2}]] -datapath_only\nset_max_delay -to   [get_clocks {clkgen_pll_CLKOUT1}] -from [get_clocks {userclk2}] [get_property PERIOD [get_clocks {userclk2}]]           -datapath_only\n\nset_max_delay -from [get_clocks {clkgen_pll_CLKOUT2}] -to   [get_clocks {userclk2}] [get_property PERIOD [get_clocks {userclk2}]] -datapath_only\nset_max_delay -to   [get_clocks {clkgen_pll_CLKOUT2}] -from [get_clocks {userclk2}] [get_property PERIOD [get_clocks {userclk2}]]           -datapath_only\n\nset_max_delay -from [get_clocks {userclk2}] -to   [get_clocks {sys_clk}] 4.0 -datapath_only\nset_max_delay -to   [get_clocks {userclk2}] -from [get_clocks {sys_clk}] 4.0 -datapath_only\n\nset_max_delay -from [get_clocks {userclk2}] -to   [get_clocks {clk_pll_i}] 4.0 -datapath_only\nset_max_delay -to   [get_clocks {userclk2}] -from [get_clocks {clk_pll_i}] 4.0 -datapath_only\n"
  },
  {
    "path": "constraints/xilinx/v2000t.xdc",
    "content": "# constraints TBD\n"
  },
  {
    "path": "constraints/xilinx/vc707-axiddr3.prj",
    "content": "<?xml version='1.0' encoding='UTF-8'?>\n<!-- IMPORTANT: This is an internal file that has been generated by the MIG software. Any direct editing or changes made to this file may result in unpredictable behavior or data corruption. It is strongly advised that users do not edit the contents of this file. Re-run the MIG GUI with the required settings if any of the options provided below need to be altered. -->\n<Project NoOfControllers=\"1\" >\n    <ModuleName>mig_7series_0</ModuleName>\n    <dci_inouts_inputs>1</dci_inouts_inputs>\n    <dci_inputs>1</dci_inputs>\n    <Debug_En>OFF</Debug_En>\n    <DataDepth_En>1024</DataDepth_En>\n    <LowPower_En>ON</LowPower_En>\n    <XADC_En>Enabled</XADC_En>\n    <TargetFPGA>xc7vx485t-ffg1761/-2</TargetFPGA>\n    <Version>2.3</Version>\n    <SystemClock>No Buffer</SystemClock>\n    <ReferenceClock>Use System Clock</ReferenceClock>\n    <SysResetPolarity>ACTIVE LOW</SysResetPolarity>\n    <BankSelectionFlag>FALSE</BankSelectionFlag>\n    <InternalVref>0</InternalVref>\n    <dci_hr_inouts_inputs>50 Ohms</dci_hr_inouts_inputs>\n    <dci_cascade>0</dci_cascade>\n    <Controller number=\"0\" >\n        <MemoryDevice>DDR3_SDRAM/SODIMMs/MT8JTF12864HZ-1G6</MemoryDevice>\n        <TimePeriod>1250</TimePeriod>\n        <VccAuxIO>2.0V</VccAuxIO>\n        <PHYRatio>4:1</PHYRatio>\n        <InputClkFreq>200</InputClkFreq>\n        <UIExtraClocks>0</UIExtraClocks>\n        <MMCM_VCO>800</MMCM_VCO>\n        <MMCMClkOut0> 1.000</MMCMClkOut0>\n        <MMCMClkOut1>1</MMCMClkOut1>\n        <MMCMClkOut2>1</MMCMClkOut2>\n        <MMCMClkOut3>1</MMCMClkOut3>\n        <MMCMClkOut4>1</MMCMClkOut4>\n        <DataWidth>64</DataWidth>\n        <DeepMemory>1</DeepMemory>\n        <DataMask>1</DataMask>\n        <ECC>Disabled</ECC>\n        <Ordering>Normal</Ordering>\n        <CustomPart>FALSE</CustomPart>\n        <NewPartName></NewPartName>\n        <RowAddress>14</RowAddress>\n        <ColAddress>10</ColAddress>\n        <BankAddress>3</BankAddress>\n        <MemoryVoltage>1.5V</MemoryVoltage>\n        <UserMemoryAddressMap>BANK_ROW_COLUMN</UserMemoryAddressMap>\n        <PinSelection>\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15\" PADName=\"A20\" SLEW=\"\" name=\"ddr3_addr[0]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15\" PADName=\"B21\" SLEW=\"\" name=\"ddr3_addr[10]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15\" PADName=\"B17\" SLEW=\"\" name=\"ddr3_addr[11]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15\" PADName=\"A15\" SLEW=\"\" name=\"ddr3_addr[12]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15\" PADName=\"A21\" SLEW=\"\" name=\"ddr3_addr[13]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15\" PADName=\"B19\" SLEW=\"\" name=\"ddr3_addr[1]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15\" PADName=\"C20\" SLEW=\"\" name=\"ddr3_addr[2]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15\" PADName=\"A19\" SLEW=\"\" name=\"ddr3_addr[3]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15\" PADName=\"A17\" SLEW=\"\" name=\"ddr3_addr[4]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15\" PADName=\"A16\" SLEW=\"\" name=\"ddr3_addr[5]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15\" PADName=\"D20\" SLEW=\"\" name=\"ddr3_addr[6]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15\" PADName=\"C18\" SLEW=\"\" name=\"ddr3_addr[7]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15\" PADName=\"D17\" SLEW=\"\" name=\"ddr3_addr[8]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15\" PADName=\"C19\" SLEW=\"\" name=\"ddr3_addr[9]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15\" PADName=\"D21\" SLEW=\"\" name=\"ddr3_ba[0]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15\" PADName=\"C21\" SLEW=\"\" name=\"ddr3_ba[1]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15\" PADName=\"D18\" SLEW=\"\" name=\"ddr3_ba[2]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15\" PADName=\"K17\" SLEW=\"\" name=\"ddr3_cas_n\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"DIFF_SSTL15\" PADName=\"G18\" SLEW=\"\" name=\"ddr3_ck_n[0]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"DIFF_SSTL15\" PADName=\"H19\" SLEW=\"\" name=\"ddr3_ck_p[0]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15\" PADName=\"K19\" SLEW=\"\" name=\"ddr3_cke[0]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15\" PADName=\"J17\" SLEW=\"\" name=\"ddr3_cs_n[0]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15\" PADName=\"M13\" SLEW=\"\" name=\"ddr3_dm[0]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15\" PADName=\"K15\" SLEW=\"\" name=\"ddr3_dm[1]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15\" PADName=\"F12\" SLEW=\"\" name=\"ddr3_dm[2]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15\" PADName=\"A14\" SLEW=\"\" name=\"ddr3_dm[3]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15\" PADName=\"C23\" SLEW=\"\" name=\"ddr3_dm[4]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15\" PADName=\"D25\" SLEW=\"\" name=\"ddr3_dm[5]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15\" PADName=\"C31\" SLEW=\"\" name=\"ddr3_dm[6]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15\" PADName=\"F31\" SLEW=\"\" name=\"ddr3_dm[7]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"N14\" SLEW=\"\" name=\"ddr3_dq[0]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"H13\" SLEW=\"\" name=\"ddr3_dq[10]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"J13\" SLEW=\"\" name=\"ddr3_dq[11]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"L16\" SLEW=\"\" name=\"ddr3_dq[12]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"L15\" SLEW=\"\" name=\"ddr3_dq[13]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"H14\" SLEW=\"\" name=\"ddr3_dq[14]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"J15\" SLEW=\"\" name=\"ddr3_dq[15]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"E15\" SLEW=\"\" name=\"ddr3_dq[16]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"E13\" SLEW=\"\" name=\"ddr3_dq[17]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"F15\" SLEW=\"\" name=\"ddr3_dq[18]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"E14\" SLEW=\"\" name=\"ddr3_dq[19]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"N13\" SLEW=\"\" name=\"ddr3_dq[1]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"G13\" SLEW=\"\" name=\"ddr3_dq[20]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"G12\" SLEW=\"\" name=\"ddr3_dq[21]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"F14\" SLEW=\"\" name=\"ddr3_dq[22]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"G14\" SLEW=\"\" name=\"ddr3_dq[23]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"B14\" SLEW=\"\" name=\"ddr3_dq[24]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"C13\" SLEW=\"\" name=\"ddr3_dq[25]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"B16\" SLEW=\"\" name=\"ddr3_dq[26]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"D15\" SLEW=\"\" name=\"ddr3_dq[27]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"D13\" SLEW=\"\" name=\"ddr3_dq[28]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"E12\" SLEW=\"\" name=\"ddr3_dq[29]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"L14\" SLEW=\"\" name=\"ddr3_dq[2]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"C16\" SLEW=\"\" name=\"ddr3_dq[30]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"D16\" SLEW=\"\" name=\"ddr3_dq[31]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"A24\" SLEW=\"\" name=\"ddr3_dq[32]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"B23\" SLEW=\"\" name=\"ddr3_dq[33]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"B27\" SLEW=\"\" name=\"ddr3_dq[34]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"B26\" SLEW=\"\" name=\"ddr3_dq[35]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"A22\" SLEW=\"\" name=\"ddr3_dq[36]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"B22\" SLEW=\"\" name=\"ddr3_dq[37]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"A25\" SLEW=\"\" name=\"ddr3_dq[38]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"C24\" SLEW=\"\" name=\"ddr3_dq[39]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"M14\" SLEW=\"\" name=\"ddr3_dq[3]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"E24\" SLEW=\"\" name=\"ddr3_dq[40]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"D23\" SLEW=\"\" name=\"ddr3_dq[41]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"D26\" SLEW=\"\" name=\"ddr3_dq[42]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"C25\" SLEW=\"\" name=\"ddr3_dq[43]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"E23\" SLEW=\"\" name=\"ddr3_dq[44]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"D22\" SLEW=\"\" name=\"ddr3_dq[45]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"F22\" SLEW=\"\" name=\"ddr3_dq[46]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"E22\" SLEW=\"\" name=\"ddr3_dq[47]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"A30\" SLEW=\"\" name=\"ddr3_dq[48]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"D27\" SLEW=\"\" name=\"ddr3_dq[49]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"M12\" SLEW=\"\" name=\"ddr3_dq[4]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"A29\" SLEW=\"\" name=\"ddr3_dq[50]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"C28\" SLEW=\"\" name=\"ddr3_dq[51]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"D28\" SLEW=\"\" name=\"ddr3_dq[52]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"B31\" SLEW=\"\" name=\"ddr3_dq[53]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"A31\" SLEW=\"\" name=\"ddr3_dq[54]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"A32\" SLEW=\"\" name=\"ddr3_dq[55]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"E30\" SLEW=\"\" name=\"ddr3_dq[56]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"F29\" SLEW=\"\" name=\"ddr3_dq[57]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"F30\" SLEW=\"\" name=\"ddr3_dq[58]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"F27\" SLEW=\"\" name=\"ddr3_dq[59]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"N15\" SLEW=\"\" name=\"ddr3_dq[5]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"C30\" SLEW=\"\" name=\"ddr3_dq[60]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"E29\" SLEW=\"\" name=\"ddr3_dq[61]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"F26\" SLEW=\"\" name=\"ddr3_dq[62]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"D30\" SLEW=\"\" name=\"ddr3_dq[63]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"M11\" SLEW=\"\" name=\"ddr3_dq[6]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"L12\" SLEW=\"\" name=\"ddr3_dq[7]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"K14\" SLEW=\"\" name=\"ddr3_dq[8]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"K13\" SLEW=\"\" name=\"ddr3_dq[9]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"DIFF_SSTL15_T_DCI\" PADName=\"M16\" SLEW=\"\" name=\"ddr3_dqs_n[0]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"DIFF_SSTL15_T_DCI\" PADName=\"J12\" SLEW=\"\" name=\"ddr3_dqs_n[1]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"DIFF_SSTL15_T_DCI\" PADName=\"G16\" SLEW=\"\" name=\"ddr3_dqs_n[2]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"DIFF_SSTL15_T_DCI\" PADName=\"C14\" SLEW=\"\" name=\"ddr3_dqs_n[3]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"DIFF_SSTL15_T_DCI\" PADName=\"A27\" SLEW=\"\" name=\"ddr3_dqs_n[4]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"DIFF_SSTL15_T_DCI\" PADName=\"E25\" SLEW=\"\" name=\"ddr3_dqs_n[5]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"DIFF_SSTL15_T_DCI\" PADName=\"B29\" SLEW=\"\" name=\"ddr3_dqs_n[6]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"DIFF_SSTL15_T_DCI\" PADName=\"E28\" SLEW=\"\" name=\"ddr3_dqs_n[7]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"DIFF_SSTL15_T_DCI\" PADName=\"N16\" SLEW=\"\" name=\"ddr3_dqs_p[0]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"DIFF_SSTL15_T_DCI\" PADName=\"K12\" SLEW=\"\" name=\"ddr3_dqs_p[1]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"DIFF_SSTL15_T_DCI\" PADName=\"H16\" SLEW=\"\" name=\"ddr3_dqs_p[2]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"DIFF_SSTL15_T_DCI\" PADName=\"C15\" SLEW=\"\" name=\"ddr3_dqs_p[3]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"DIFF_SSTL15_T_DCI\" PADName=\"A26\" SLEW=\"\" name=\"ddr3_dqs_p[4]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"DIFF_SSTL15_T_DCI\" PADName=\"F25\" SLEW=\"\" name=\"ddr3_dqs_p[5]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"DIFF_SSTL15_T_DCI\" PADName=\"B28\" SLEW=\"\" name=\"ddr3_dqs_p[6]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"DIFF_SSTL15_T_DCI\" PADName=\"E27\" SLEW=\"\" name=\"ddr3_dqs_p[7]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15\" PADName=\"H20\" SLEW=\"\" name=\"ddr3_odt[0]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15\" PADName=\"E20\" SLEW=\"\" name=\"ddr3_ras_n\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"LVCMOS15\" PADName=\"C29\" SLEW=\"\" name=\"ddr3_reset_n\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15\" PADName=\"F20\" SLEW=\"\" name=\"ddr3_we_n\" IN_TERM=\"\" />\n        </PinSelection>\n        <System_Control>\n            <Pin PADName=\"No connect\" Bank=\"Select Bank\" name=\"sys_rst\" />\n            <Pin PADName=\"No connect\" Bank=\"Select Bank\" name=\"init_calib_complete\" />\n            <Pin PADName=\"No connect\" Bank=\"Select Bank\" name=\"tg_compare_error\" />\n        </System_Control>\n        <TimingParameters>\n            <Parameters twtr=\"7.5\" trrd=\"6\" trefi=\"7.8\" tfaw=\"30\" trtp=\"7.5\" tcke=\"5\" trfc=\"110\" trp=\"13.75\" tras=\"35\" trcd=\"13.75\" />\n        </TimingParameters>\n        <mrBurstLength name=\"Burst Length\" >8 - Fixed</mrBurstLength>\n        <mrBurstType name=\"Read Burst Type and Length\" >Sequential</mrBurstType>\n        <mrCasLatency name=\"CAS Latency\" >11</mrCasLatency>\n        <mrMode name=\"Mode\" >Normal</mrMode>\n        <mrDllReset name=\"DLL Reset\" >No</mrDllReset>\n        <mrPdMode name=\"DLL control for precharge PD\" >Slow Exit</mrPdMode>\n        <emrDllEnable name=\"DLL Enable\" >Enable</emrDllEnable>\n        <emrOutputDriveStrength name=\"Output Driver Impedance Control\" >RZQ/7</emrOutputDriveStrength>\n        <emrMirrorSelection name=\"Address Mirroring\" >Disable</emrMirrorSelection>\n        <emrCSSelection name=\"Controller Chip Select Pin\" >Enable</emrCSSelection>\n        <emrRTT name=\"RTT (nominal) - On Die Termination (ODT)\" >RZQ/4</emrRTT>\n        <emrPosted name=\"Additive Latency (AL)\" >0</emrPosted>\n        <emrOCD name=\"Write Leveling Enable\" >Disabled</emrOCD>\n        <emrDQS name=\"TDQS enable\" >Enabled</emrDQS>\n        <emrRDQS name=\"Qoff\" >Output Buffer Enabled</emrRDQS>\n        <mr2PartialArraySelfRefresh name=\"Partial-Array Self Refresh\" >Full Array</mr2PartialArraySelfRefresh>\n        <mr2CasWriteLatency name=\"CAS write latency\" >8</mr2CasWriteLatency>\n        <mr2AutoSelfRefresh name=\"Auto Self Refresh\" >Enabled</mr2AutoSelfRefresh>\n        <mr2SelfRefreshTempRange name=\"High Temparature Self Refresh Rate\" >Normal</mr2SelfRefreshTempRange>\n        <mr2RTTWR name=\"RTT_WR - Dynamic On Die Termination (ODT)\" >Dynamic ODT off</mr2RTTWR>\n        <PortInterface>AXI</PortInterface>\n        <AXIParameters>\n            <C0_C_RD_WR_ARB_ALGORITHM>RD_PRI_REG</C0_C_RD_WR_ARB_ALGORITHM>\n            <C0_S_AXI_ADDR_WIDTH>30</C0_S_AXI_ADDR_WIDTH>\n            <C0_S_AXI_DATA_WIDTH>512</C0_S_AXI_DATA_WIDTH>\n            <C0_S_AXI_ID_WIDTH>6</C0_S_AXI_ID_WIDTH>\n            <C0_S_AXI_SUPPORTS_NARROW_BURST>0</C0_S_AXI_SUPPORTS_NARROW_BURST>\n        </AXIParameters>\n    </Controller>\n\n</Project>\n"
  },
  {
    "path": "constraints/xilinx/vc707-portal-pblock.xdc",
    "content": "startgroup\ncreate_pblock pblock_portalTop\nresize_pblock pblock_portalTop -add {SLICE_X0Y0:SLICE_X105Y199 DSP48_X0Y0:DSP48_X8Y79 PCIE_X0Y0:PCIE_X0Y0 RAMB18_X0Y0:RAMB18_X6Y79 RAMB36_X0Y0:RAMB36_X6Y39}\nadd_cells_to_pblock pblock_portalTop [get_cells top_portalTop]\nendgroup\n"
  },
  {
    "path": "constraints/xilinx/vc707.xdc",
    "content": "######################################################################################################\n##  File name :       default.xdc\n##\n##  Details :     Constraints file\n##                    FPGA family:       virtex7\n##                    FPGA:              xc7vx485t-2ffg1761C\n##                    Speedgrade:        -2\n##\n######################################################################################################\n\n######################################################################################################\n# PIN ASSIGNMENTS\n######################################################################################################\nset_property LOC AD8  [get_ports { CLK_pci_sys_clk_p }]\nset_property LOC AD7  [get_ports { CLK_pci_sys_clk_n }]\nset_property LOC AV35 [get_ports { RST_N_pci_sys_reset_n }]\nset_property LOC E19  [get_ports { CLK_sys_clk_p }]\nset_property LOC E18  [get_ports { CLK_sys_clk_n }]\n\nset_property LOC Y4   [get_ports { PCIE_rxp_v[0] }]\nset_property LOC AA6  [get_ports { PCIE_rxp_v[1] }]\nset_property LOC AB4  [get_ports { PCIE_rxp_v[2] }]\nset_property LOC AC6  [get_ports { PCIE_rxp_v[3] }]\nset_property LOC AD4  [get_ports { PCIE_rxp_v[4] }]\nset_property LOC AE6  [get_ports { PCIE_rxp_v[5] }]\nset_property LOC AF4  [get_ports { PCIE_rxp_v[6] }]\nset_property LOC AG6  [get_ports { PCIE_rxp_v[7] }]\n\nset_property LOC Y3   [get_ports { PCIE_rxn_v[0] }]\nset_property LOC AA5  [get_ports { PCIE_rxn_v[1] }]\nset_property LOC AB3  [get_ports { PCIE_rxn_v[2] }]\nset_property LOC AC5  [get_ports { PCIE_rxn_v[3] }]\nset_property LOC AD3  [get_ports { PCIE_rxn_v[4] }]\nset_property LOC AE5  [get_ports { PCIE_rxn_v[5] }]\nset_property LOC AF3  [get_ports { PCIE_rxn_v[6] }]\nset_property LOC AG5  [get_ports { PCIE_rxn_v[7] }]\n\nset_property LOC W2   [get_ports { PCIE_txp[0] }]\nset_property LOC AA2  [get_ports { PCIE_txp[1] }]\nset_property LOC AC2  [get_ports { PCIE_txp[2] }]\nset_property LOC AE2  [get_ports { PCIE_txp[3] }]\nset_property LOC AG2  [get_ports { PCIE_txp[4] }]\nset_property LOC AH4  [get_ports { PCIE_txp[5] }]\nset_property LOC AJ2  [get_ports { PCIE_txp[6] }]\nset_property LOC AK4  [get_ports { PCIE_txp[7] }]\n\nset_property LOC W1   [get_ports { PCIE_txn[0] }]\nset_property LOC AA1  [get_ports { PCIE_txn[1] }]\nset_property LOC AC1  [get_ports { PCIE_txn[2] }]\nset_property LOC AE1  [get_ports { PCIE_txn[3] }]\nset_property LOC AG1  [get_ports { PCIE_txn[4] }]\nset_property LOC AH3  [get_ports { PCIE_txn[5] }]\nset_property LOC AJ1  [get_ports { PCIE_txn[6] }]\nset_property LOC AK3  [get_ports { PCIE_txn[7] }]\n\n######################################################################################################\n# I/O STANDARDS\n######################################################################################################\nset_property IOSTANDARD DIFF_SSTL15 [get_ports { CLK_sys_clk_* }]\nset_property IOSTANDARD LVCMOS15    [get_ports { RST_N_pci_sys_reset_n }]\nset_property PULLUP     true        [get_ports { RST_N_pci_sys_reset_n }]\n\n######################################################################################################\n# CELL LOCATIONS\n######################################################################################################\n#\n# SYS clock 100 MHz (input) signal. The sys_clk_p and sys_clk_n\n# signals are the PCI Express reference clock. Virtex-7 GT\n# Transceiver architecture requires the use of a dedicated clock\n# resources (FPGA input pins) associated with each GT Transceiver.\n# To use these pins an IBUFDS primitive (refclk_ibuf) is\n# instantiated in user's design.\n# Please refer to the Virtex-7 GT Transceiver User Guide\n# (UG) for guidelines regarding clock resource selection.\n#\nset_property LOC IBUFDS_GTE2_X1Y5  [get_cells { host_pcieHostTop_clockGen }]\n\nset_property LOC MMCME2_ADV_X1Y2 [get_cells -hier -filter { NAME =~ */ext_clk.pipe_clock_i/mmcm_i }]\nset_property LOC MMCME2_ADV_X1Y1 [get_cells -hier -filter { NAME =~ *clkgen_pll }]\nset_property LOC MMCME2_ADV_X1Y5 [get_cells -hier -filter { NAME =~ *clk_gen_pll }]\n\n######################################################################################################\n# TIMING CONSTRAINTS\n######################################################################################################\n \n## in pcie-clocks.xdc\n\n# ignore this timing violation\nset_false_path -from [get_pins host_ep7/pclk_sel_reg/C]\n"
  },
  {
    "path": "constraints/xilinx/vc707_aurora.xdc",
    "content": " ##################################################################################\n ##\n ## Project:  Aurora 64B/66B\n ## Company:  Xilinx\n ##\n ##\n ##\n ## (c) Copyright 2012 - 2013 Xilinx, Inc. All rights reserved.\n ##\n ## This file contains confidential and proprietary information\n ## of Xilinx, Inc. and is protected under U.S. and\n ## international copyright and other intellectual property\n ## laws.\n ##\n ## DISCLAIMER\n ## This disclaimer is not a license and does not grant any\n ## rights to the materials distributed herewith. Except as\n ## otherwise provided in a valid license issued to you by\n ## Xilinx, and to the maximum extent permitted by applicable\n ## law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n ## WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n ## AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n ## BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n ## INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n ## (2) Xilinx shall not be liable (whether in contract or tort,\n ## including negligence, or under any other theory of\n ## liability) for any loss or damage of any kind or nature\n ## related to, arising under or in connection with these\n ## materials, including for any direct, or any indirect,\n ## special, incidental, or consequential loss or damage\n ## (including loss of data, profits, goodwill, or any type of\n ## loss or damage suffered as a result of any action brought\n ## by a third party) even if such damage or loss was\n ## reasonably foreseeable or Xilinx had been advised of the\n ## possibility of the same.\n ##\n ## CRITICAL APPLICATIONS\n ## Xilinx products are not designed or intended to be fail-\n ## safe, or for use in any application requiring fail-safe\n ## performance, such as life-support or safety devices or\n ## systems, Class III medical devices, nuclear facilities,\n ## applications related to the deployment of airbags, or any\n ## other applications that could lead to death, personal\n ## injury, or severe property or environmental damage\n ## (individually and collectively, \"Critical\n ## Applications\"). Customer assumes the sole risk and\n ## liability of any use of Xilinx products in Critical\n ## Applications, subject only to applicable laws and\n ## regulations governing limitations on product liability.\n ##\n ## THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n ## PART OF THIS FILE AT ALL TIMES.\n \n ##\n #################################################################################\n \n ##\n ##  aurora_64b66b_0\n ##\n ##\n ##  Description: This is the design constraints file for a 1 lane Aurora\n ##               core. \n ##\n ##\n ##\n \n ################################ CLOCK CONSTRAINTS ##############################\n \nset_false_path -to [get_pins -hier *data_fifo*/RST]        \nset_false_path -to [get_pins -hier *rxrecclk_bufg_i*/CE]        \n\ncreate_clock -period 3.200\t [get_pins -hier -filter {name=~*AURORA_64B66B_0_GTX_INST/gtxe2_i/TXOUTCLK}]\n## create_clock -period 3.200\t [get_pins -hier -filter {name=~aurora_64b66b_0_wrapper_i*aurora_64b66b_0_multi_gt_i*AURORA_64B66B_0_GTX_INST/gtxe2_i/TXOUTCLK}]\n## create_clock -period 3.200\t [get_pins -hier -filter {name=~*aurora_64b66b_0_wrapper_i*aurora_64b66b_0_multi_gt_i*AURORA_64B66B_0_GTX_INST/gtxe2_i/TXOUTCLK}]\n## create_clock -period 3.200\t [get_pins */top_auroraImport0/auroraImport/aurora_64b66b_0_block_i/aurora_64b66b_0_i/inst/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/AURORA_64B66B_0_GTX_INST/gtxe2_i/TXOUTCLK]\n\ncreate_clock -period 3.200\t [get_pins -hier -filter {name=~*AURORA_64B66B_0_GTX_INST/gtxe2_i/RXOUTCLK}]\n## create_clock -period 3.200\t [get_pins -hier -filter {name=~aurora_64b66b_0_wrapper_i*aurora_64b66b_0_multi_gt_i*AURORA_64B66B_0_GTX_INST/gtxe2_i/RXOUTCLK}]\n## create_clock -period 3.200\t [get_pins -hier -filter {name=~top_auroraImport1_0*aurora_64b66b_0_wrapper_i*aurora_64b66b_0_multi_gt_i*AURORA_64B66B_0_GTX_INST/gtxe2_i/RXOUTCLK}]\n## create_clock -period 3.200\t [get_pins */top_auroraImport0/auroraImport/aurora_64b66b_0_block_i/aurora_64b66b_0_i/inst/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/AURORA_64B66B_0_GTX_INST/gtxe2_i/RXOUTCLK]\n\n\n\nset_false_path -to [get_pins -hier *aurora_64b66b_0_cdc_to*/D]        \n\n\n\n## create_clock -name TS_sync_clk_i -period 3.200\t [get_pins */aurora_64b66b_0_block_i/clock_module_i/sync_clock_net_i/O] \ncreate_clock -name TS_sync_clk_i_0 -period 3.200\t [get_pins */top_auroraImport0/auroraImport/aurora_64b66b_0_block_i/clock_module_i/sync_clock_net_i/O] \n## create_clock -name TS_sync_clk_i_1_0 -period 3.200\t [get_pins */top_auroraImport1_0/auroraImport/aurora_64b66b_0_block_i/clock_module_i/sync_clock_net_i/O] \n\n\n\n## port 0\ncreate_clock -name GTXQ0_left_i_p -period 8.000\t [get_ports CLK_gtx_clk_0_p] \ncreate_clock -name GTXQ0_left_i_n -period 8.000\t [get_ports CLK_gtx_clk_0_n] \nset_property LOC AH8 [get_ports CLK_gtx_clk_0_p]\nset_property LOC AH7 [get_ports CLK_gtx_clk_0_n]\n\nset_property LOC GTXE2_CHANNEL_X1Y0 [get_cells  */top_auroraImport0/auroraImport/aurora_64b66b_0_block_i/aurora_64b66b_0_i/inst/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/AURORA_64B66B_0_GTX_INST/gtxe2_i]\n\n\nset_property LOC AP4 [get_ports { pins_aurora0_TXP }]\nset_property LOC AP3 [get_ports { pins_aurora0_TXN }]\nset_property LOC AN6 [get_ports { pins_aurora0_rxp_i }]\nset_property LOC AN5 [get_ports { pins_aurora0_rxn_i }]\n\n## fmc 1 port 0\n## create_clock -name GTXQ1_0_left_i_p -period 8.000\t [get_ports CLK_gtx_clk_1_0_p] \n## create_clock -name GTXQ1_0_left_i_n -period 8.000\t [get_ports CLK_gtx_clk_1_0_n] \n## set_property LOC E10 [get_ports CLK_gtx_clk_1_0_p]\n## set_property LOC E9 [get_ports CLK_gtx_clk_1_0_n]\n## \n## set_property LOC GTXE2_CHANNEL_X1Y24 [get_cells  */top_auroraImport1_0/auroraImport/aurora_64b66b_0_block_i/aurora_64b66b_0_i/inst/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/AURORA_64B66B_0_GTX_INST/gtxe2_i]\n## \n## \n## set_property LOC E2 [get_ports { pins_aurora1_0_TXP }]\n## set_property LOC E1 [get_ports { pins_aurora1_0_TXN }]\n## set_property LOC D8 [get_ports { pins_aurora1_0_rxp_i }]\n## set_property LOC D7 [get_ports { pins_aurora1_0_rxn_i }]\n\n\n"
  },
  {
    "path": "constraints/xilinx/vc707_ddr3.xdc",
    "content": "######################################################################################################\n##  DDR3 Constraints\n######################################################################################################\n\n######################################################################################################\n# PIN ASSIGNMENTS\n######################################################################################################\n# PadFunction: IO_L23N_T3_39 \nset_property VCCAUX_IO NORMAL [get_ports {pins_ddr3_DQ[0]}]\nset_property SLEW FAST [get_ports {pins_ddr3_DQ[0]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {pins_ddr3_DQ[0]}]\nset_property LOC N14 [get_ports {pins_ddr3_DQ[0]}]\n\n# PadFunction: IO_L22P_T3_39 \nset_property VCCAUX_IO NORMAL [get_ports {pins_ddr3_DQ[1]}]\nset_property SLEW FAST [get_ports {pins_ddr3_DQ[1]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {pins_ddr3_DQ[1]}]\nset_property LOC N13 [get_ports {pins_ddr3_DQ[1]}]\n\n# PadFunction: IO_L20N_T3_39 \nset_property VCCAUX_IO NORMAL [get_ports {pins_ddr3_DQ[2]}]\nset_property SLEW FAST [get_ports {pins_ddr3_DQ[2]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {pins_ddr3_DQ[2]}]\nset_property LOC L14 [get_ports {pins_ddr3_DQ[2]}]\n\n# PadFunction: IO_L20P_T3_39 \nset_property VCCAUX_IO NORMAL [get_ports {pins_ddr3_DQ[3]}]\nset_property SLEW FAST [get_ports {pins_ddr3_DQ[3]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {pins_ddr3_DQ[3]}]\nset_property LOC M14 [get_ports {pins_ddr3_DQ[3]}]\n\n# PadFunction: IO_L24P_T3_39 \nset_property VCCAUX_IO NORMAL [get_ports {pins_ddr3_DQ[4]}]\nset_property SLEW FAST [get_ports {pins_ddr3_DQ[4]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {pins_ddr3_DQ[4]}]\nset_property LOC M12 [get_ports {pins_ddr3_DQ[4]}]\n\n# PadFunction: IO_L23P_T3_39 \nset_property VCCAUX_IO NORMAL [get_ports {pins_ddr3_DQ[5]}]\nset_property SLEW FAST [get_ports {pins_ddr3_DQ[5]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {pins_ddr3_DQ[5]}]\nset_property LOC N15 [get_ports {pins_ddr3_DQ[5]}]\n\n# PadFunction: IO_L24N_T3_39 \nset_property VCCAUX_IO NORMAL [get_ports {pins_ddr3_DQ[6]}]\nset_property SLEW FAST [get_ports {pins_ddr3_DQ[6]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {pins_ddr3_DQ[6]}]\nset_property LOC M11 [get_ports {pins_ddr3_DQ[6]}]\n\n# PadFunction: IO_L19P_T3_39 \nset_property VCCAUX_IO NORMAL [get_ports {pins_ddr3_DQ[7]}]\nset_property SLEW FAST [get_ports {pins_ddr3_DQ[7]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {pins_ddr3_DQ[7]}]\nset_property LOC L12 [get_ports {pins_ddr3_DQ[7]}]\n\n# PadFunction: IO_L17P_T2_39 \nset_property VCCAUX_IO NORMAL [get_ports {pins_ddr3_DQ[8]}]\nset_property SLEW FAST [get_ports {pins_ddr3_DQ[8]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {pins_ddr3_DQ[8]}]\nset_property LOC K14 [get_ports {pins_ddr3_DQ[8]}]\n\n# PadFunction: IO_L17N_T2_39 \nset_property VCCAUX_IO NORMAL [get_ports {pins_ddr3_DQ[9]}]\nset_property SLEW FAST [get_ports {pins_ddr3_DQ[9]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {pins_ddr3_DQ[9]}]\nset_property LOC K13 [get_ports {pins_ddr3_DQ[9]}]\n\n# PadFunction: IO_L14N_T2_SRCC_39 \nset_property VCCAUX_IO NORMAL [get_ports {pins_ddr3_DQ[10]}]\nset_property SLEW FAST [get_ports {pins_ddr3_DQ[10]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {pins_ddr3_DQ[10]}]\nset_property LOC H13 [get_ports {pins_ddr3_DQ[10]}]\n\n# PadFunction: IO_L14P_T2_SRCC_39 \nset_property VCCAUX_IO NORMAL [get_ports {pins_ddr3_DQ[11]}]\nset_property SLEW FAST [get_ports {pins_ddr3_DQ[11]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {pins_ddr3_DQ[11]}]\nset_property LOC J13 [get_ports {pins_ddr3_DQ[11]}]\n\n# PadFunction: IO_L18P_T2_39 \nset_property VCCAUX_IO NORMAL [get_ports {pins_ddr3_DQ[12]}]\nset_property SLEW FAST [get_ports {pins_ddr3_DQ[12]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {pins_ddr3_DQ[12]}]\nset_property LOC L16 [get_ports {pins_ddr3_DQ[12]}]\n\n# PadFunction: IO_L18N_T2_39 \nset_property VCCAUX_IO NORMAL [get_ports {pins_ddr3_DQ[13]}]\nset_property SLEW FAST [get_ports {pins_ddr3_DQ[13]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {pins_ddr3_DQ[13]}]\nset_property LOC L15 [get_ports {pins_ddr3_DQ[13]}]\n\n# PadFunction: IO_L13N_T2_MRCC_39 \nset_property VCCAUX_IO NORMAL [get_ports {pins_ddr3_DQ[14]}]\nset_property SLEW FAST [get_ports {pins_ddr3_DQ[14]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {pins_ddr3_DQ[14]}]\nset_property LOC H14 [get_ports {pins_ddr3_DQ[14]}]\n\n# PadFunction: IO_L16N_T2_39 \nset_property VCCAUX_IO NORMAL [get_ports {pins_ddr3_DQ[15]}]\nset_property SLEW FAST [get_ports {pins_ddr3_DQ[15]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {pins_ddr3_DQ[15]}]\nset_property LOC J15 [get_ports {pins_ddr3_DQ[15]}]\n\n# PadFunction: IO_L7N_T1_39 \nset_property VCCAUX_IO NORMAL [get_ports {pins_ddr3_DQ[16]}]\nset_property SLEW FAST [get_ports {pins_ddr3_DQ[16]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {pins_ddr3_DQ[16]}]\nset_property LOC E15 [get_ports {pins_ddr3_DQ[16]}]\n\n# PadFunction: IO_L8N_T1_39 \nset_property VCCAUX_IO NORMAL [get_ports {pins_ddr3_DQ[17]}]\nset_property SLEW FAST [get_ports {pins_ddr3_DQ[17]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {pins_ddr3_DQ[17]}]\nset_property LOC E13 [get_ports {pins_ddr3_DQ[17]}]\n\n# PadFunction: IO_L11P_T1_SRCC_39 \nset_property VCCAUX_IO NORMAL [get_ports {pins_ddr3_DQ[18]}]\nset_property SLEW FAST [get_ports {pins_ddr3_DQ[18]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {pins_ddr3_DQ[18]}]\nset_property LOC F15 [get_ports {pins_ddr3_DQ[18]}]\n\n# PadFunction: IO_L8P_T1_39 \nset_property VCCAUX_IO NORMAL [get_ports {pins_ddr3_DQ[19]}]\nset_property SLEW FAST [get_ports {pins_ddr3_DQ[19]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {pins_ddr3_DQ[19]}]\nset_property LOC E14 [get_ports {pins_ddr3_DQ[19]}]\n\n# PadFunction: IO_L12N_T1_MRCC_39 \nset_property VCCAUX_IO NORMAL [get_ports {pins_ddr3_DQ[20]}]\nset_property SLEW FAST [get_ports {pins_ddr3_DQ[20]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {pins_ddr3_DQ[20]}]\nset_property LOC G13 [get_ports {pins_ddr3_DQ[20]}]\n\n# PadFunction: IO_L10P_T1_39 \nset_property VCCAUX_IO NORMAL [get_ports {pins_ddr3_DQ[21]}]\nset_property SLEW FAST [get_ports {pins_ddr3_DQ[21]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {pins_ddr3_DQ[21]}]\nset_property LOC G12 [get_ports {pins_ddr3_DQ[21]}]\n\n# PadFunction: IO_L11N_T1_SRCC_39 \nset_property VCCAUX_IO NORMAL [get_ports {pins_ddr3_DQ[22]}]\nset_property SLEW FAST [get_ports {pins_ddr3_DQ[22]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {pins_ddr3_DQ[22]}]\nset_property LOC F14 [get_ports {pins_ddr3_DQ[22]}]\n\n# PadFunction: IO_L12P_T1_MRCC_39 \nset_property VCCAUX_IO NORMAL [get_ports {pins_ddr3_DQ[23]}]\nset_property SLEW FAST [get_ports {pins_ddr3_DQ[23]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {pins_ddr3_DQ[23]}]\nset_property LOC G14 [get_ports {pins_ddr3_DQ[23]}]\n\n# PadFunction: IO_L2P_T0_39 \nset_property VCCAUX_IO NORMAL [get_ports {pins_ddr3_DQ[24]}]\nset_property SLEW FAST [get_ports {pins_ddr3_DQ[24]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {pins_ddr3_DQ[24]}]\nset_property LOC B14 [get_ports {pins_ddr3_DQ[24]}]\n\n# PadFunction: IO_L4N_T0_39 \nset_property VCCAUX_IO NORMAL [get_ports {pins_ddr3_DQ[25]}]\nset_property SLEW FAST [get_ports {pins_ddr3_DQ[25]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {pins_ddr3_DQ[25]}]\nset_property LOC C13 [get_ports {pins_ddr3_DQ[25]}]\n\n# PadFunction: IO_L1N_T0_39 \nset_property VCCAUX_IO NORMAL [get_ports {pins_ddr3_DQ[26]}]\nset_property SLEW FAST [get_ports {pins_ddr3_DQ[26]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {pins_ddr3_DQ[26]}]\nset_property LOC B16 [get_ports {pins_ddr3_DQ[26]}]\n\n# PadFunction: IO_L5N_T0_39 \nset_property VCCAUX_IO NORMAL [get_ports {pins_ddr3_DQ[27]}]\nset_property SLEW FAST [get_ports {pins_ddr3_DQ[27]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {pins_ddr3_DQ[27]}]\nset_property LOC D15 [get_ports {pins_ddr3_DQ[27]}]\n\n# PadFunction: IO_L4P_T0_39 \nset_property VCCAUX_IO NORMAL [get_ports {pins_ddr3_DQ[28]}]\nset_property SLEW FAST [get_ports {pins_ddr3_DQ[28]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {pins_ddr3_DQ[28]}]\nset_property LOC D13 [get_ports {pins_ddr3_DQ[28]}]\n\n# PadFunction: IO_L6P_T0_39 \nset_property VCCAUX_IO NORMAL [get_ports {pins_ddr3_DQ[29]}]\nset_property SLEW FAST [get_ports {pins_ddr3_DQ[29]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {pins_ddr3_DQ[29]}]\nset_property LOC E12 [get_ports {pins_ddr3_DQ[29]}]\n\n# PadFunction: IO_L1P_T0_39 \nset_property VCCAUX_IO NORMAL [get_ports {pins_ddr3_DQ[30]}]\nset_property SLEW FAST [get_ports {pins_ddr3_DQ[30]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {pins_ddr3_DQ[30]}]\nset_property LOC C16 [get_ports {pins_ddr3_DQ[30]}]\n\n# PadFunction: IO_L5P_T0_39 \nset_property VCCAUX_IO NORMAL [get_ports {pins_ddr3_DQ[31]}]\nset_property SLEW FAST [get_ports {pins_ddr3_DQ[31]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {pins_ddr3_DQ[31]}]\nset_property LOC D16 [get_ports {pins_ddr3_DQ[31]}]\n\n# PadFunction: IO_L1P_T0_37 \nset_property VCCAUX_IO NORMAL [get_ports {pins_ddr3_DQ[32]}]\nset_property SLEW FAST [get_ports {pins_ddr3_DQ[32]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {pins_ddr3_DQ[32]}]\nset_property LOC A24 [get_ports {pins_ddr3_DQ[32]}]\n\n# PadFunction: IO_L4N_T0_37 \nset_property VCCAUX_IO NORMAL [get_ports {pins_ddr3_DQ[33]}]\nset_property SLEW FAST [get_ports {pins_ddr3_DQ[33]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {pins_ddr3_DQ[33]}]\nset_property LOC B23 [get_ports {pins_ddr3_DQ[33]}]\n\n# PadFunction: IO_L5N_T0_37 \nset_property VCCAUX_IO NORMAL [get_ports {pins_ddr3_DQ[34]}]\nset_property SLEW FAST [get_ports {pins_ddr3_DQ[34]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {pins_ddr3_DQ[34]}]\nset_property LOC B27 [get_ports {pins_ddr3_DQ[34]}]\n\n# PadFunction: IO_L5P_T0_37 \nset_property VCCAUX_IO NORMAL [get_ports {pins_ddr3_DQ[35]}]\nset_property SLEW FAST [get_ports {pins_ddr3_DQ[35]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {pins_ddr3_DQ[35]}]\nset_property LOC B26 [get_ports {pins_ddr3_DQ[35]}]\n\n# PadFunction: IO_L2N_T0_37 \nset_property VCCAUX_IO NORMAL [get_ports {pins_ddr3_DQ[36]}]\nset_property SLEW FAST [get_ports {pins_ddr3_DQ[36]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {pins_ddr3_DQ[36]}]\nset_property LOC A22 [get_ports {pins_ddr3_DQ[36]}]\n\n# PadFunction: IO_L2P_T0_37 \nset_property VCCAUX_IO NORMAL [get_ports {pins_ddr3_DQ[37]}]\nset_property SLEW FAST [get_ports {pins_ddr3_DQ[37]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {pins_ddr3_DQ[37]}]\nset_property LOC B22 [get_ports {pins_ddr3_DQ[37]}]\n\n# PadFunction: IO_L1N_T0_37 \nset_property VCCAUX_IO NORMAL [get_ports {pins_ddr3_DQ[38]}]\nset_property SLEW FAST [get_ports {pins_ddr3_DQ[38]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {pins_ddr3_DQ[38]}]\nset_property LOC A25 [get_ports {pins_ddr3_DQ[38]}]\n\n# PadFunction: IO_L6P_T0_37 \nset_property VCCAUX_IO NORMAL [get_ports {pins_ddr3_DQ[39]}]\nset_property SLEW FAST [get_ports {pins_ddr3_DQ[39]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {pins_ddr3_DQ[39]}]\nset_property LOC C24 [get_ports {pins_ddr3_DQ[39]}]\n\n# PadFunction: IO_L7N_T1_37 \nset_property VCCAUX_IO NORMAL [get_ports {pins_ddr3_DQ[40]}]\nset_property SLEW FAST [get_ports {pins_ddr3_DQ[40]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {pins_ddr3_DQ[40]}]\nset_property LOC E24 [get_ports {pins_ddr3_DQ[40]}]\n\n# PadFunction: IO_L10N_T1_37 \nset_property VCCAUX_IO NORMAL [get_ports {pins_ddr3_DQ[41]}]\nset_property SLEW FAST [get_ports {pins_ddr3_DQ[41]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {pins_ddr3_DQ[41]}]\nset_property LOC D23 [get_ports {pins_ddr3_DQ[41]}]\n\n# PadFunction: IO_L11N_T1_SRCC_37 \nset_property VCCAUX_IO NORMAL [get_ports {pins_ddr3_DQ[42]}]\nset_property SLEW FAST [get_ports {pins_ddr3_DQ[42]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {pins_ddr3_DQ[42]}]\nset_property LOC D26 [get_ports {pins_ddr3_DQ[42]}]\n\n# PadFunction: IO_L12P_T1_MRCC_37 \nset_property VCCAUX_IO NORMAL [get_ports {pins_ddr3_DQ[43]}]\nset_property SLEW FAST [get_ports {pins_ddr3_DQ[43]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {pins_ddr3_DQ[43]}]\nset_property LOC C25 [get_ports {pins_ddr3_DQ[43]}]\n\n# PadFunction: IO_L7P_T1_37 \nset_property VCCAUX_IO NORMAL [get_ports {pins_ddr3_DQ[44]}]\nset_property SLEW FAST [get_ports {pins_ddr3_DQ[44]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {pins_ddr3_DQ[44]}]\nset_property LOC E23 [get_ports {pins_ddr3_DQ[44]}]\n\n# PadFunction: IO_L10P_T1_37 \nset_property VCCAUX_IO NORMAL [get_ports {pins_ddr3_DQ[45]}]\nset_property SLEW FAST [get_ports {pins_ddr3_DQ[45]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {pins_ddr3_DQ[45]}]\nset_property LOC D22 [get_ports {pins_ddr3_DQ[45]}]\n\n# PadFunction: IO_L8P_T1_37 \nset_property VCCAUX_IO NORMAL [get_ports {pins_ddr3_DQ[46]}]\nset_property SLEW FAST [get_ports {pins_ddr3_DQ[46]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {pins_ddr3_DQ[46]}]\nset_property LOC F22 [get_ports {pins_ddr3_DQ[46]}]\n\n# PadFunction: IO_L8N_T1_37 \nset_property VCCAUX_IO NORMAL [get_ports {pins_ddr3_DQ[47]}]\nset_property SLEW FAST [get_ports {pins_ddr3_DQ[47]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {pins_ddr3_DQ[47]}]\nset_property LOC E22 [get_ports {pins_ddr3_DQ[47]}]\n\n# PadFunction: IO_L17N_T2_37 \nset_property VCCAUX_IO NORMAL [get_ports {pins_ddr3_DQ[48]}]\nset_property SLEW FAST [get_ports {pins_ddr3_DQ[48]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {pins_ddr3_DQ[48]}]\nset_property LOC A30 [get_ports {pins_ddr3_DQ[48]}]\n\n# PadFunction: IO_L13P_T2_MRCC_37 \nset_property VCCAUX_IO NORMAL [get_ports {pins_ddr3_DQ[49]}]\nset_property SLEW FAST [get_ports {pins_ddr3_DQ[49]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {pins_ddr3_DQ[49]}]\nset_property LOC D27 [get_ports {pins_ddr3_DQ[49]}]\n\n# PadFunction: IO_L17P_T2_37 \nset_property VCCAUX_IO NORMAL [get_ports {pins_ddr3_DQ[50]}]\nset_property SLEW FAST [get_ports {pins_ddr3_DQ[50]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {pins_ddr3_DQ[50]}]\nset_property LOC A29 [get_ports {pins_ddr3_DQ[50]}]\n\n# PadFunction: IO_L14P_T2_SRCC_37 \nset_property VCCAUX_IO NORMAL [get_ports {pins_ddr3_DQ[51]}]\nset_property SLEW FAST [get_ports {pins_ddr3_DQ[51]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {pins_ddr3_DQ[51]}]\nset_property LOC C28 [get_ports {pins_ddr3_DQ[51]}]\n\n# PadFunction: IO_L13N_T2_MRCC_37 \nset_property VCCAUX_IO NORMAL [get_ports {pins_ddr3_DQ[52]}]\nset_property SLEW FAST [get_ports {pins_ddr3_DQ[52]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {pins_ddr3_DQ[52]}]\nset_property LOC D28 [get_ports {pins_ddr3_DQ[52]}]\n\n# PadFunction: IO_L18N_T2_37 \nset_property VCCAUX_IO NORMAL [get_ports {pins_ddr3_DQ[53]}]\nset_property SLEW FAST [get_ports {pins_ddr3_DQ[53]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {pins_ddr3_DQ[53]}]\nset_property LOC B31 [get_ports {pins_ddr3_DQ[53]}]\n\n# PadFunction: IO_L16P_T2_37 \nset_property VCCAUX_IO NORMAL [get_ports {pins_ddr3_DQ[54]}]\nset_property SLEW FAST [get_ports {pins_ddr3_DQ[54]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {pins_ddr3_DQ[54]}]\nset_property LOC A31 [get_ports {pins_ddr3_DQ[54]}]\n\n# PadFunction: IO_L16N_T2_37 \nset_property VCCAUX_IO NORMAL [get_ports {pins_ddr3_DQ[55]}]\nset_property SLEW FAST [get_ports {pins_ddr3_DQ[55]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {pins_ddr3_DQ[55]}]\nset_property LOC A32 [get_ports {pins_ddr3_DQ[55]}]\n\n# PadFunction: IO_L19P_T3_37 \nset_property VCCAUX_IO NORMAL [get_ports {pins_ddr3_DQ[56]}]\nset_property SLEW FAST [get_ports {pins_ddr3_DQ[56]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {pins_ddr3_DQ[56]}]\nset_property LOC E30 [get_ports {pins_ddr3_DQ[56]}]\n\n# PadFunction: IO_L22P_T3_37 \nset_property VCCAUX_IO NORMAL [get_ports {pins_ddr3_DQ[57]}]\nset_property SLEW FAST [get_ports {pins_ddr3_DQ[57]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {pins_ddr3_DQ[57]}]\nset_property LOC F29 [get_ports {pins_ddr3_DQ[57]}]\n\n# PadFunction: IO_L24P_T3_37 \nset_property VCCAUX_IO NORMAL [get_ports {pins_ddr3_DQ[58]}]\nset_property SLEW FAST [get_ports {pins_ddr3_DQ[58]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {pins_ddr3_DQ[58]}]\nset_property LOC F30 [get_ports {pins_ddr3_DQ[58]}]\n\n# PadFunction: IO_L23N_T3_37 \nset_property VCCAUX_IO NORMAL [get_ports {pins_ddr3_DQ[59]}]\nset_property SLEW FAST [get_ports {pins_ddr3_DQ[59]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {pins_ddr3_DQ[59]}]\nset_property LOC F27 [get_ports {pins_ddr3_DQ[59]}]\n\n# PadFunction: IO_L20N_T3_37 \nset_property VCCAUX_IO NORMAL [get_ports {pins_ddr3_DQ[60]}]\nset_property SLEW FAST [get_ports {pins_ddr3_DQ[60]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {pins_ddr3_DQ[60]}]\nset_property LOC C30 [get_ports {pins_ddr3_DQ[60]}]\n\n# PadFunction: IO_L22N_T3_37 \nset_property VCCAUX_IO NORMAL [get_ports {pins_ddr3_DQ[61]}]\nset_property SLEW FAST [get_ports {pins_ddr3_DQ[61]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {pins_ddr3_DQ[61]}]\nset_property LOC E29 [get_ports {pins_ddr3_DQ[61]}]\n\n# PadFunction: IO_L23P_T3_37 \nset_property VCCAUX_IO NORMAL [get_ports {pins_ddr3_DQ[62]}]\nset_property SLEW FAST [get_ports {pins_ddr3_DQ[62]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {pins_ddr3_DQ[62]}]\nset_property LOC F26 [get_ports {pins_ddr3_DQ[62]}]\n\n# PadFunction: IO_L20P_T3_37 \nset_property VCCAUX_IO NORMAL [get_ports {pins_ddr3_DQ[63]}]\nset_property SLEW FAST [get_ports {pins_ddr3_DQ[63]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {pins_ddr3_DQ[63]}]\nset_property LOC D30 [get_ports {pins_ddr3_DQ[63]}]\n\n#set_property VCCAUX_IO NORMAL [get_ports {pins_ddr3_A[15]}]\n#set_property SLEW FAST [get_ports {pins_ddr3_A[15]}]\n#set_property IOSTANDARD SSTL15 [get_ports {pins_ddr3_A[15]}]\n#set_property LOC E17 [get_ports {pins_ddr3_A[15]}]\n\nset_property VCCAUX_IO NORMAL [get_ports {pins_ddr3_A[14]}]\nset_property SLEW FAST [get_ports {pins_ddr3_A[14]}]\nset_property IOSTANDARD SSTL15 [get_ports {pins_ddr3_A[14]}]\nset_property LOC F17 [get_ports {pins_ddr3_A[14]}]\n\n# PadFunction: IO_L5N_T0_38 \nset_property VCCAUX_IO NORMAL [get_ports {pins_ddr3_A[13]}]\nset_property SLEW FAST [get_ports {pins_ddr3_A[13]}]\nset_property IOSTANDARD SSTL15 [get_ports {pins_ddr3_A[13]}]\nset_property LOC A21 [get_ports {pins_ddr3_A[13]}]\n\n# PadFunction: IO_L2N_T0_38 \nset_property VCCAUX_IO NORMAL [get_ports {pins_ddr3_A[12]}]\nset_property SLEW FAST [get_ports {pins_ddr3_A[12]}]\nset_property IOSTANDARD SSTL15 [get_ports {pins_ddr3_A[12]}]\nset_property LOC A15 [get_ports {pins_ddr3_A[12]}]\n\n# PadFunction: IO_L4P_T0_38 \nset_property VCCAUX_IO NORMAL [get_ports {pins_ddr3_A[11]}]\nset_property SLEW FAST [get_ports {pins_ddr3_A[11]}]\nset_property IOSTANDARD SSTL15 [get_ports {pins_ddr3_A[11]}]\nset_property LOC B17 [get_ports {pins_ddr3_A[11]}]\n\n# PadFunction: IO_L5P_T0_38 \nset_property VCCAUX_IO NORMAL [get_ports {pins_ddr3_A[10]}]\nset_property SLEW FAST [get_ports {pins_ddr3_A[10]}]\nset_property IOSTANDARD SSTL15 [get_ports {pins_ddr3_A[10]}]\nset_property LOC B21 [get_ports {pins_ddr3_A[10]}]\n\n# PadFunction: IO_L1P_T0_38 \nset_property VCCAUX_IO NORMAL [get_ports {pins_ddr3_A[9]}]\nset_property SLEW FAST [get_ports {pins_ddr3_A[9]}]\nset_property IOSTANDARD SSTL15 [get_ports {pins_ddr3_A[9]}]\nset_property LOC C19 [get_ports {pins_ddr3_A[9]}]\n\n# PadFunction: IO_L10N_T1_38 \nset_property VCCAUX_IO NORMAL [get_ports {pins_ddr3_A[8]}]\nset_property SLEW FAST [get_ports {pins_ddr3_A[8]}]\nset_property IOSTANDARD SSTL15 [get_ports {pins_ddr3_A[8]}]\nset_property LOC D17 [get_ports {pins_ddr3_A[8]}]\n\n# PadFunction: IO_L6P_T0_38 \nset_property VCCAUX_IO NORMAL [get_ports {pins_ddr3_A[7]}]\nset_property SLEW FAST [get_ports {pins_ddr3_A[7]}]\nset_property IOSTANDARD SSTL15 [get_ports {pins_ddr3_A[7]}]\nset_property LOC C18 [get_ports {pins_ddr3_A[7]}]\n\n# PadFunction: IO_L7P_T1_38 \nset_property VCCAUX_IO NORMAL [get_ports {pins_ddr3_A[6]}]\nset_property SLEW FAST [get_ports {pins_ddr3_A[6]}]\nset_property IOSTANDARD SSTL15 [get_ports {pins_ddr3_A[6]}]\nset_property LOC D20 [get_ports {pins_ddr3_A[6]}]\n\n# PadFunction: IO_L2P_T0_38 \nset_property VCCAUX_IO NORMAL [get_ports {pins_ddr3_A[5]}]\nset_property SLEW FAST [get_ports {pins_ddr3_A[5]}]\nset_property IOSTANDARD SSTL15 [get_ports {pins_ddr3_A[5]}]\nset_property LOC A16 [get_ports {pins_ddr3_A[5]}]\n\n# PadFunction: IO_L4N_T0_38 \nset_property VCCAUX_IO NORMAL [get_ports {pins_ddr3_A[4]}]\nset_property SLEW FAST [get_ports {pins_ddr3_A[4]}]\nset_property IOSTANDARD SSTL15 [get_ports {pins_ddr3_A[4]}]\nset_property LOC A17 [get_ports {pins_ddr3_A[4]}]\n\n# PadFunction: IO_L3N_T0_DQS_38 \nset_property VCCAUX_IO NORMAL [get_ports {pins_ddr3_A[3]}]\nset_property SLEW FAST [get_ports {pins_ddr3_A[3]}]\nset_property IOSTANDARD SSTL15 [get_ports {pins_ddr3_A[3]}]\nset_property LOC A19 [get_ports {pins_ddr3_A[3]}]\n\n# PadFunction: IO_L7N_T1_38 \nset_property VCCAUX_IO NORMAL [get_ports {pins_ddr3_A[2]}]\nset_property SLEW FAST [get_ports {pins_ddr3_A[2]}]\nset_property IOSTANDARD SSTL15 [get_ports {pins_ddr3_A[2]}]\nset_property LOC C20 [get_ports {pins_ddr3_A[2]}]\n\n# PadFunction: IO_L1N_T0_38 \nset_property VCCAUX_IO NORMAL [get_ports {pins_ddr3_A[1]}]\nset_property SLEW FAST [get_ports {pins_ddr3_A[1]}]\nset_property IOSTANDARD SSTL15 [get_ports {pins_ddr3_A[1]}]\nset_property LOC B19 [get_ports {pins_ddr3_A[1]}]\n\n# PadFunction: IO_L3P_T0_DQS_38 \nset_property VCCAUX_IO NORMAL [get_ports {pins_ddr3_A[0]}]\nset_property SLEW FAST [get_ports {pins_ddr3_A[0]}]\nset_property IOSTANDARD SSTL15 [get_ports {pins_ddr3_A[0]}]\nset_property LOC A20 [get_ports {pins_ddr3_A[0]}]\n\n# PadFunction: IO_L10P_T1_38 \nset_property VCCAUX_IO NORMAL [get_ports {pins_ddr3_BA[2]}]\nset_property SLEW FAST [get_ports {pins_ddr3_BA[2]}]\nset_property IOSTANDARD SSTL15 [get_ports {pins_ddr3_BA[2]}]\nset_property LOC D18 [get_ports {pins_ddr3_BA[2]}]\n\n# PadFunction: IO_L9N_T1_DQS_38 \nset_property VCCAUX_IO NORMAL [get_ports {pins_ddr3_BA[1]}]\nset_property SLEW FAST [get_ports {pins_ddr3_BA[1]}]\nset_property IOSTANDARD SSTL15 [get_ports {pins_ddr3_BA[1]}]\nset_property LOC C21 [get_ports {pins_ddr3_BA[1]}]\n\n# PadFunction: IO_L9P_T1_DQS_38 \nset_property VCCAUX_IO NORMAL [get_ports {pins_ddr3_BA[0]}]\nset_property SLEW FAST [get_ports {pins_ddr3_BA[0]}]\nset_property IOSTANDARD SSTL15 [get_ports {pins_ddr3_BA[0]}]\nset_property LOC D21 [get_ports {pins_ddr3_BA[0]}]\n\n# PadFunction: IO_L15N_T2_DQS_38 \nset_property VCCAUX_IO NORMAL [get_ports {pins_ddr3_RAS_N}]\nset_property SLEW FAST [get_ports {pins_ddr3_RAS_N}]\nset_property IOSTANDARD SSTL15 [get_ports {pins_ddr3_RAS_N}]\nset_property LOC E20 [get_ports {pins_ddr3_RAS_N}]\n\n# PadFunction: IO_L16P_T2_38 \nset_property VCCAUX_IO NORMAL [get_ports {pins_ddr3_CAS_N}]\nset_property SLEW FAST [get_ports {pins_ddr3_CAS_N}]\nset_property IOSTANDARD SSTL15 [get_ports {pins_ddr3_CAS_N}]\nset_property LOC K17 [get_ports {pins_ddr3_CAS_N}]\n\n# PadFunction: IO_L15P_T2_DQS_38 \nset_property VCCAUX_IO NORMAL [get_ports {pins_ddr3_WE_N}]\nset_property SLEW FAST [get_ports {pins_ddr3_WE_N}]\nset_property IOSTANDARD SSTL15 [get_ports {pins_ddr3_WE_N}]\nset_property LOC F20 [get_ports {pins_ddr3_WE_N}]\n\n# PadFunction: IO_L14N_T2_SRCC_37 \nset_property VCCAUX_IO NORMAL [get_ports {pins_ddr3_RESET_N}]\nset_property SLEW FAST [get_ports {pins_ddr3_RESET_N}]\nset_property IOSTANDARD LVCMOS15 [get_ports {pins_ddr3_RESET_N}]\nset_property LOC C29 [get_ports {pins_ddr3_RESET_N}]\n\n# PadFunction: IO_L14P_T2_SRCC_38 \nset_property VCCAUX_IO NORMAL [get_ports {pins_ddr3_CKE}]\nset_property SLEW FAST [get_ports {pins_ddr3_CKE}]\nset_property IOSTANDARD SSTL15 [get_ports {pins_ddr3_CKE}]\nset_property LOC K19 [get_ports {pins_ddr3_CKE}]\n\n# PadFunction: IO_L17N_T2_38 \nset_property VCCAUX_IO NORMAL [get_ports {pins_ddr3_ODT}]\nset_property SLEW FAST [get_ports {pins_ddr3_ODT}]\nset_property IOSTANDARD SSTL15 [get_ports {pins_ddr3_ODT}]\nset_property LOC H20 [get_ports {pins_ddr3_ODT}]\n\n# PadFunction: IO_L16N_T2_38 \nset_property VCCAUX_IO NORMAL [get_ports {pins_ddr3_CS_N}]\nset_property SLEW FAST [get_ports {pins_ddr3_CS_N}]\nset_property IOSTANDARD SSTL15 [get_ports {pins_ddr3_CS_N}]\nset_property LOC J17 [get_ports {pins_ddr3_CS_N}]\n\n# PadFunction: IO_L22N_T3_39 \nset_property VCCAUX_IO NORMAL [get_ports {pins_ddr3_DM[0]}]\nset_property SLEW FAST [get_ports {pins_ddr3_DM[0]}]\nset_property IOSTANDARD SSTL15 [get_ports {pins_ddr3_DM[0]}]\nset_property LOC M13 [get_ports {pins_ddr3_DM[0]}]\n\n# PadFunction: IO_L16P_T2_39 \nset_property VCCAUX_IO NORMAL [get_ports {pins_ddr3_DM[1]}]\nset_property SLEW FAST [get_ports {pins_ddr3_DM[1]}]\nset_property IOSTANDARD SSTL15 [get_ports {pins_ddr3_DM[1]}]\nset_property LOC K15 [get_ports {pins_ddr3_DM[1]}]\n\n# PadFunction: IO_L10N_T1_39 \nset_property VCCAUX_IO NORMAL [get_ports {pins_ddr3_DM[2]}]\nset_property SLEW FAST [get_ports {pins_ddr3_DM[2]}]\nset_property IOSTANDARD SSTL15 [get_ports {pins_ddr3_DM[2]}]\nset_property LOC F12 [get_ports {pins_ddr3_DM[2]}]\n\n# PadFunction: IO_L2N_T0_39 \nset_property VCCAUX_IO NORMAL [get_ports {pins_ddr3_DM[3]}]\nset_property SLEW FAST [get_ports {pins_ddr3_DM[3]}]\nset_property IOSTANDARD SSTL15 [get_ports {pins_ddr3_DM[3]}]\nset_property LOC A14 [get_ports {pins_ddr3_DM[3]}]\n\n# PadFunction: IO_L4P_T0_37 \nset_property VCCAUX_IO NORMAL [get_ports {pins_ddr3_DM[4]}]\nset_property SLEW FAST [get_ports {pins_ddr3_DM[4]}]\nset_property IOSTANDARD SSTL15 [get_ports {pins_ddr3_DM[4]}]\nset_property LOC C23 [get_ports {pins_ddr3_DM[4]}]\n\n# PadFunction: IO_L11P_T1_SRCC_37 \nset_property VCCAUX_IO NORMAL [get_ports {pins_ddr3_DM[5]}]\nset_property SLEW FAST [get_ports {pins_ddr3_DM[5]}]\nset_property IOSTANDARD SSTL15 [get_ports {pins_ddr3_DM[5]}]\nset_property LOC D25 [get_ports {pins_ddr3_DM[5]}]\n\n# PadFunction: IO_L18P_T2_37 \nset_property VCCAUX_IO NORMAL [get_ports {pins_ddr3_DM[6]}]\nset_property SLEW FAST [get_ports {pins_ddr3_DM[6]}]\nset_property IOSTANDARD SSTL15 [get_ports {pins_ddr3_DM[6]}]\nset_property LOC C31 [get_ports {pins_ddr3_DM[6]}]\n\n# PadFunction: IO_L24N_T3_37 \nset_property VCCAUX_IO NORMAL [get_ports {pins_ddr3_DM[7]}]\nset_property SLEW FAST [get_ports {pins_ddr3_DM[7]}]\nset_property IOSTANDARD SSTL15 [get_ports {pins_ddr3_DM[7]}]\nset_property LOC F31 [get_ports {pins_ddr3_DM[7]}]\n\n# PadFunction: IO_L21P_T3_DQS_39 \nset_property VCCAUX_IO NORMAL [get_ports {pins_ddr3_DQS_P[0]}]\nset_property SLEW FAST [get_ports {pins_ddr3_DQS_P[0]}]\nset_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports {pins_ddr3_DQS_P[0]}]\nset_property LOC N16 [get_ports {pins_ddr3_DQS_P[0]}]\n\n# PadFunction: IO_L21N_T3_DQS_39 \nset_property VCCAUX_IO NORMAL [get_ports {pins_ddr3_DQS_N[0]}]\nset_property SLEW FAST [get_ports {pins_ddr3_DQS_N[0]}]\nset_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports {pins_ddr3_DQS_N[0]}]\nset_property LOC M16 [get_ports {pins_ddr3_DQS_N[0]}]\n\n# PadFunction: IO_L15P_T2_DQS_39 \nset_property VCCAUX_IO NORMAL [get_ports {pins_ddr3_DQS_P[1]}]\nset_property SLEW FAST [get_ports {pins_ddr3_DQS_P[1]}]\nset_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports {pins_ddr3_DQS_P[1]}]\nset_property LOC K12 [get_ports {pins_ddr3_DQS_P[1]}]\n\n# PadFunction: IO_L15N_T2_DQS_39 \nset_property VCCAUX_IO NORMAL [get_ports {pins_ddr3_DQS_N[1]}]\nset_property SLEW FAST [get_ports {pins_ddr3_DQS_N[1]}]\nset_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports {pins_ddr3_DQS_N[1]}]\nset_property LOC J12 [get_ports {pins_ddr3_DQS_N[1]}]\n\n# PadFunction: IO_L9P_T1_DQS_39 \nset_property VCCAUX_IO NORMAL [get_ports {pins_ddr3_DQS_P[2]}]\nset_property SLEW FAST [get_ports {pins_ddr3_DQS_P[2]}]\nset_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports {pins_ddr3_DQS_P[2]}]\nset_property LOC H16 [get_ports {pins_ddr3_DQS_P[2]}]\n\n# PadFunction: IO_L9N_T1_DQS_39 \nset_property VCCAUX_IO NORMAL [get_ports {pins_ddr3_DQS_N[2]}]\nset_property SLEW FAST [get_ports {pins_ddr3_DQS_N[2]}]\nset_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports {pins_ddr3_DQS_N[2]}]\nset_property LOC G16 [get_ports {pins_ddr3_DQS_N[2]}]\n\n# PadFunction: IO_L3P_T0_DQS_39 \nset_property VCCAUX_IO NORMAL [get_ports {pins_ddr3_DQS_P[3]}]\nset_property SLEW FAST [get_ports {pins_ddr3_DQS_P[3]}]\nset_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports {pins_ddr3_DQS_P[3]}]\nset_property LOC C15 [get_ports {pins_ddr3_DQS_P[3]}]\n\n# PadFunction: IO_L3N_T0_DQS_39 \nset_property VCCAUX_IO NORMAL [get_ports {pins_ddr3_DQS_N[3]}]\nset_property SLEW FAST [get_ports {pins_ddr3_DQS_N[3]}]\nset_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports {pins_ddr3_DQS_N[3]}]\nset_property LOC C14 [get_ports {pins_ddr3_DQS_N[3]}]\n\n# PadFunction: IO_L3P_T0_DQS_37 \nset_property VCCAUX_IO NORMAL [get_ports {pins_ddr3_DQS_P[4]}]\nset_property SLEW FAST [get_ports {pins_ddr3_DQS_P[4]}]\nset_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports {pins_ddr3_DQS_P[4]}]\nset_property LOC A26 [get_ports {pins_ddr3_DQS_P[4]}]\n\n# PadFunction: IO_L3N_T0_DQS_37 \nset_property VCCAUX_IO NORMAL [get_ports {pins_ddr3_DQS_N[4]}]\nset_property SLEW FAST [get_ports {pins_ddr3_DQS_N[4]}]\nset_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports {pins_ddr3_DQS_N[4]}]\nset_property LOC A27 [get_ports {pins_ddr3_DQS_N[4]}]\n\n# PadFunction: IO_L9P_T1_DQS_37 \nset_property VCCAUX_IO NORMAL [get_ports {pins_ddr3_DQS_P[5]}]\nset_property SLEW FAST [get_ports {pins_ddr3_DQS_P[5]}]\nset_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports {pins_ddr3_DQS_P[5]}]\nset_property LOC F25 [get_ports {pins_ddr3_DQS_P[5]}]\n\n# PadFunction: IO_L9N_T1_DQS_37 \nset_property VCCAUX_IO NORMAL [get_ports {pins_ddr3_DQS_N[5]}]\nset_property SLEW FAST [get_ports {pins_ddr3_DQS_N[5]}]\nset_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports {pins_ddr3_DQS_N[5]}]\nset_property LOC E25 [get_ports {pins_ddr3_DQS_N[5]}]\n\n# PadFunction: IO_L15P_T2_DQS_37 \nset_property VCCAUX_IO NORMAL [get_ports {pins_ddr3_DQS_P[6]}]\nset_property SLEW FAST [get_ports {pins_ddr3_DQS_P[6]}]\nset_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports {pins_ddr3_DQS_P[6]}]\nset_property LOC B28 [get_ports {pins_ddr3_DQS_P[6]}]\n\n# PadFunction: IO_L15N_T2_DQS_37 \nset_property VCCAUX_IO NORMAL [get_ports {pins_ddr3_DQS_N[6]}]\nset_property SLEW FAST [get_ports {pins_ddr3_DQS_N[6]}]\nset_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports {pins_ddr3_DQS_N[6]}]\nset_property LOC B29 [get_ports {pins_ddr3_DQS_N[6]}]\n\n# PadFunction: IO_L21P_T3_DQS_37 \nset_property VCCAUX_IO NORMAL [get_ports {pins_ddr3_DQS_P[7]}]\nset_property SLEW FAST [get_ports {pins_ddr3_DQS_P[7]}]\nset_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports {pins_ddr3_DQS_P[7]}]\nset_property LOC E27 [get_ports {pins_ddr3_DQS_P[7]}]\n\n# PadFunction: IO_L21N_T3_DQS_37 \nset_property VCCAUX_IO NORMAL [get_ports {pins_ddr3_DQS_N[7]}]\nset_property SLEW FAST [get_ports {pins_ddr3_DQS_N[7]}]\nset_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports {pins_ddr3_DQS_N[7]}]\nset_property LOC E28 [get_ports {pins_ddr3_DQS_N[7]}]\n\n# PadFunction: IO_L13P_T2_MRCC_38 \nset_property VCCAUX_IO NORMAL [get_ports {pins_ddr3_CLK_P}]\nset_property SLEW FAST [get_ports {pins_ddr3_CLK_P}]\nset_property IOSTANDARD DIFF_SSTL15 [get_ports {pins_ddr3_CLK_P}]\nset_property LOC H19 [get_ports {pins_ddr3_CLK_P}]\n\n# PadFunction: IO_L13N_T2_MRCC_38 \nset_property VCCAUX_IO NORMAL [get_ports {pins_ddr3_CLK_N}]\nset_property SLEW FAST [get_ports {pins_ddr3_CLK_N}]\nset_property IOSTANDARD DIFF_SSTL15 [get_ports {pins_ddr3_CLK_N}]\nset_property LOC G18 [get_ports {pins_ddr3_CLK_N}]\n\n\n\nset_property LOC PHASER_OUT_PHY_X1Y19 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out}]\nset_property LOC PHASER_OUT_PHY_X1Y18 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out}]\nset_property LOC PHASER_OUT_PHY_X1Y17 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out}]\nset_property LOC PHASER_OUT_PHY_X1Y16 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out}]\nset_property LOC PHASER_OUT_PHY_X1Y23 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out}]\nset_property LOC PHASER_OUT_PHY_X1Y22 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out}]\nset_property LOC PHASER_OUT_PHY_X1Y21 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out}]\nset_property LOC PHASER_OUT_PHY_X1Y27 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out}]\nset_property LOC PHASER_OUT_PHY_X1Y26 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out}]\nset_property LOC PHASER_OUT_PHY_X1Y25 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out}]\nset_property LOC PHASER_OUT_PHY_X1Y24 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out}]\n\nset_property LOC PHASER_IN_PHY_X1Y19 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in}]\nset_property LOC PHASER_IN_PHY_X1Y18 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in}]\nset_property LOC PHASER_IN_PHY_X1Y17 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_in_gen.phaser_in}]\nset_property LOC PHASER_IN_PHY_X1Y16 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_in_gen.phaser_in}]\n## set_property LOC PHASER_IN_PHY_X1Y23 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in}]\n## set_property LOC PHASER_IN_PHY_X1Y22 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in}]\n## set_property LOC PHASER_IN_PHY_X1Y21 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_in_gen.phaser_in}]\nset_property LOC PHASER_IN_PHY_X1Y27 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in}]\nset_property LOC PHASER_IN_PHY_X1Y26 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in}]\nset_property LOC PHASER_IN_PHY_X1Y25 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_in_gen.phaser_in}]\nset_property LOC PHASER_IN_PHY_X1Y24 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_in_gen.phaser_in}]\n\n\n\nset_property LOC OUT_FIFO_X1Y19 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo}]\nset_property LOC OUT_FIFO_X1Y18 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo}]\nset_property LOC OUT_FIFO_X1Y17 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo}]\nset_property LOC OUT_FIFO_X1Y16 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo}]\nset_property LOC OUT_FIFO_X1Y23 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo}]\nset_property LOC OUT_FIFO_X1Y22 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo}]\nset_property LOC OUT_FIFO_X1Y21 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo}]\nset_property LOC OUT_FIFO_X1Y27 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo}]\nset_property LOC OUT_FIFO_X1Y26 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo}]\nset_property LOC OUT_FIFO_X1Y25 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo}]\nset_property LOC OUT_FIFO_X1Y24 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo}]\n\nset_property LOC IN_FIFO_X1Y19 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/in_fifo_gen.in_fifo}]\nset_property LOC IN_FIFO_X1Y18 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/in_fifo_gen.in_fifo}]\nset_property LOC IN_FIFO_X1Y17 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/in_fifo_gen.in_fifo}]\nset_property LOC IN_FIFO_X1Y16 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/in_fifo_gen.in_fifo}]\nset_property LOC IN_FIFO_X1Y27 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/in_fifo_gen.in_fifo}]\nset_property LOC IN_FIFO_X1Y26 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/in_fifo_gen.in_fifo}]\nset_property LOC IN_FIFO_X1Y25 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/in_fifo_gen.in_fifo}]\nset_property LOC IN_FIFO_X1Y24 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/in_fifo_gen.in_fifo}]\n\nset_property LOC PHY_CONTROL_X1Y4 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_2.u_ddr_phy_4lanes/phy_control_i}]\nset_property LOC PHY_CONTROL_X1Y5 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_1.u_ddr_phy_4lanes/phy_control_i}]\nset_property LOC PHY_CONTROL_X1Y6 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i}]\n\nset_property LOC PHASER_REF_X1Y4 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_2.u_ddr_phy_4lanes/phaser_ref_i}]\nset_property LOC PHASER_REF_X1Y5 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_1.u_ddr_phy_4lanes/phaser_ref_i}]\nset_property LOC PHASER_REF_X1Y6 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/phaser_ref_i}]\n\nset_property LOC OLOGIC_X1Y243 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/*slave_ts}]\nset_property LOC OLOGIC_X1Y231 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/*slave_ts}]\nset_property LOC OLOGIC_X1Y219 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/*slave_ts}]\nset_property LOC OLOGIC_X1Y207 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/*slave_ts}]\nset_property LOC OLOGIC_X1Y343 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/*slave_ts}]\nset_property LOC OLOGIC_X1Y331 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/*slave_ts}]\nset_property LOC OLOGIC_X1Y319 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/*slave_ts}]\nset_property LOC OLOGIC_X1Y307 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/*slave_ts}]\n\nset_property LOC PLLE2_ADV_X1Y5 [get_cells -hier -filter { NAME =~ */u_ddr3_infrastructure/plle2_i }]\nset_property LOC MMCME2_ADV_X1Y6 [get_cells -hier -filter { NAME =~ */u_ddr3_infrastructure/mmcm_i }]\n\n\n######################################################################################################\n# AREA GROUPS\n######################################################################################################\nstartgroup\ncreate_pblock pblock_ddr3\nresize_pblock pblock_ddr3 -add { SLICE_X120Y200:SLICE_X220Y360 DSP48_X13Y82:DSP48_X19Y137 RAMB18_X9Y82:RAMB18_X13Y137 RAMB36_X9Y41:RAMB36_X13Y68 }\n#resize_pblock pblock_ddr3 -add { SLICE_X146Y201:SLICE_X205Y348 DSP48_X13Y82:DSP48_X19Y137 RAMB18_X9Y82:RAMB18_X13Y137 RAMB36_X9Y41:RAMB36_X13Y68 }\nadd_cells_to_pblock pblock_ddr3 [get_cells [list */top_ddr3* ]]\n#add_cells_to_pblock pblock_ddr3 [get_cells [list */top_dramController* ]]\n#add_cells_to_pblock pblock_ddr3 [get_cells [list ddr3* ]]\nendgroup\n\n\n######################################################################################################\n# TIMING CONSTRAINTS\n######################################################################################################\ncreate_clock -name top_x7pcie_sys_clk_200mhz -period 5 [get_pins *sys_clk_200mhz/O]\ncreate_generated_clock -name ddr3_refclk -source [get_pins *sys_clk_200mhz_buf/O] -divide_by 1 [get_pins */top_clk_gen_pll/CLKOUT1]\ncreate_generated_clock -name ddr3_usrclk -source [get_pins *sys_clk_200mhz_buf/O] -multiply_by 5 -divide_by 10 [get_pins */top_clk_gen_pll/CLKOUT0]\n#create_generated_clock -name ddr3_refclk -source [get_pins sys_clk/O] -divide_by 1 [get_pins clk_gen_pll/CLKOUT1]\n\nset_multicycle_path -from [get_cells -hier -filter {NAME =~ */mc0/mc_read_idle_r_reg}] \\\n                    -to   [get_cells -hier -filter {NAME =~ */input_[?].iserdes_dq_.iserdesdq}] \\\n                    -setup 6\n\nset_multicycle_path -from [get_cells -hier -filter {NAME =~ */mc0/mc_read_idle_r_reg}] \\\n                    -to   [get_cells -hier -filter {NAME =~ */input_[?].iserdes_dq_.iserdesdq}] \\\n                    -hold 5\n\nset_false_path -through [get_pins -filter {NAME =~ */DQSFOUND} -of [get_cells -hier -filter {REF_NAME == PHASER_IN_PHY}]]\n\nset_multicycle_path -through [get_pins -filter {NAME =~ */OSERDESRST} -of [get_cells -hier -filter {REF_NAME == PHASER_OUT_PHY}]] -setup 2 -start\nset_multicycle_path -through [get_pins -filter {NAME =~ */OSERDESRST} -of [get_cells -hier -filter {REF_NAME == PHASER_OUT_PHY}]] -hold 1 -start\n\nset_multicycle_path -to   [get_cells -hier -filter {NAME =~ */temp_mon_enabled.u_mig_7series_v1_7_tempmon/device_temp_sync_r1*}] \\\n                    -setup 12 -end\n\nset_multicycle_path -to   [get_cells -hier -filter {NAME =~ */temp_mon_enabled.u_mig_7series_v1_7_tempmon/device_temp_sync_r1*}] \\\n                    -hold 11 -end\n\nset_multicycle_path -to   [get_cells -hier -filter {NAME =~ */temp_mon_enabled.u_mig_7series_v1_7_tempmon/rst_r1*}] \\\n                    -setup 2 -end\n\nset_multicycle_path -to   [get_cells -hier -filter {NAME =~ */temp_mon_enabled.u_mig_7series_v1_7_tempmon/rst_r1*}] \\\n                    -hold 1 -end\n\n#set_max_delay -from [get_clocks uclock] -to [get_clocks clk_pll_i] 20.000 -datapath_only\n#set_max_delay -from [get_clocks uclock] -to [get_clocks clk_pll_i_1] 20.000 -datapath_only\n"
  },
  {
    "path": "constraints/xilinx/vc707_ddr3_pins.xdc",
    "content": "######################################################################################################\n# PIN ASSIGNMENTS\n######################################################################################################\n# PadFunction: IO_L23N_T3_39 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_dq[0]}]\nset_property SLEW FAST [get_ports {ddr3_dq[0]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[0]}]\nset_property LOC N14 [get_ports {ddr3_dq[0]}]\n\n# PadFunction: IO_L22P_T3_39 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_dq[1]}]\nset_property SLEW FAST [get_ports {ddr3_dq[1]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[1]}]\nset_property LOC N13 [get_ports {ddr3_dq[1]}]\n\n# PadFunction: IO_L20N_T3_39 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_dq[2]}]\nset_property SLEW FAST [get_ports {ddr3_dq[2]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[2]}]\nset_property LOC L14 [get_ports {ddr3_dq[2]}]\n\n# PadFunction: IO_L20P_T3_39 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_dq[3]}]\nset_property SLEW FAST [get_ports {ddr3_dq[3]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[3]}]\nset_property LOC M14 [get_ports {ddr3_dq[3]}]\n\n# PadFunction: IO_L24P_T3_39 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_dq[4]}]\nset_property SLEW FAST [get_ports {ddr3_dq[4]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[4]}]\nset_property LOC M12 [get_ports {ddr3_dq[4]}]\n\n# PadFunction: IO_L23P_T3_39 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_dq[5]}]\nset_property SLEW FAST [get_ports {ddr3_dq[5]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[5]}]\nset_property LOC N15 [get_ports {ddr3_dq[5]}]\n\n# PadFunction: IO_L24N_T3_39 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_dq[6]}]\nset_property SLEW FAST [get_ports {ddr3_dq[6]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[6]}]\nset_property LOC M11 [get_ports {ddr3_dq[6]}]\n\n# PadFunction: IO_L19P_T3_39 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_dq[7]}]\nset_property SLEW FAST [get_ports {ddr3_dq[7]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[7]}]\nset_property LOC L12 [get_ports {ddr3_dq[7]}]\n\n# PadFunction: IO_L17P_T2_39 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_dq[8]}]\nset_property SLEW FAST [get_ports {ddr3_dq[8]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[8]}]\nset_property LOC K14 [get_ports {ddr3_dq[8]}]\n\n# PadFunction: IO_L17N_T2_39 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_dq[9]}]\nset_property SLEW FAST [get_ports {ddr3_dq[9]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[9]}]\nset_property LOC K13 [get_ports {ddr3_dq[9]}]\n\n# PadFunction: IO_L14N_T2_SRCC_39 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_dq[10]}]\nset_property SLEW FAST [get_ports {ddr3_dq[10]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[10]}]\nset_property LOC H13 [get_ports {ddr3_dq[10]}]\n\n# PadFunction: IO_L14P_T2_SRCC_39 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_dq[11]}]\nset_property SLEW FAST [get_ports {ddr3_dq[11]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[11]}]\nset_property LOC J13 [get_ports {ddr3_dq[11]}]\n\n# PadFunction: IO_L18P_T2_39 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_dq[12]}]\nset_property SLEW FAST [get_ports {ddr3_dq[12]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[12]}]\nset_property LOC L16 [get_ports {ddr3_dq[12]}]\n\n# PadFunction: IO_L18N_T2_39 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_dq[13]}]\nset_property SLEW FAST [get_ports {ddr3_dq[13]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[13]}]\nset_property LOC L15 [get_ports {ddr3_dq[13]}]\n\n# PadFunction: IO_L13N_T2_MRCC_39 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_dq[14]}]\nset_property SLEW FAST [get_ports {ddr3_dq[14]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[14]}]\nset_property LOC H14 [get_ports {ddr3_dq[14]}]\n\n# PadFunction: IO_L16N_T2_39 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_dq[15]}]\nset_property SLEW FAST [get_ports {ddr3_dq[15]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[15]}]\nset_property LOC J15 [get_ports {ddr3_dq[15]}]\n\n# PadFunction: IO_L7N_T1_39 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_dq[16]}]\nset_property SLEW FAST [get_ports {ddr3_dq[16]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[16]}]\nset_property LOC E15 [get_ports {ddr3_dq[16]}]\n\n# PadFunction: IO_L8N_T1_39 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_dq[17]}]\nset_property SLEW FAST [get_ports {ddr3_dq[17]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[17]}]\nset_property LOC E13 [get_ports {ddr3_dq[17]}]\n\n# PadFunction: IO_L11P_T1_SRCC_39 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_dq[18]}]\nset_property SLEW FAST [get_ports {ddr3_dq[18]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[18]}]\nset_property LOC F15 [get_ports {ddr3_dq[18]}]\n\n# PadFunction: IO_L8P_T1_39 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_dq[19]}]\nset_property SLEW FAST [get_ports {ddr3_dq[19]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[19]}]\nset_property LOC E14 [get_ports {ddr3_dq[19]}]\n\n# PadFunction: IO_L12N_T1_MRCC_39 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_dq[20]}]\nset_property SLEW FAST [get_ports {ddr3_dq[20]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[20]}]\nset_property LOC G13 [get_ports {ddr3_dq[20]}]\n\n# PadFunction: IO_L10P_T1_39 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_dq[21]}]\nset_property SLEW FAST [get_ports {ddr3_dq[21]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[21]}]\nset_property LOC G12 [get_ports {ddr3_dq[21]}]\n\n# PadFunction: IO_L11N_T1_SRCC_39 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_dq[22]}]\nset_property SLEW FAST [get_ports {ddr3_dq[22]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[22]}]\nset_property LOC F14 [get_ports {ddr3_dq[22]}]\n\n# PadFunction: IO_L12P_T1_MRCC_39 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_dq[23]}]\nset_property SLEW FAST [get_ports {ddr3_dq[23]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[23]}]\nset_property LOC G14 [get_ports {ddr3_dq[23]}]\n\n# PadFunction: IO_L2P_T0_39 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_dq[24]}]\nset_property SLEW FAST [get_ports {ddr3_dq[24]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[24]}]\nset_property LOC B14 [get_ports {ddr3_dq[24]}]\n\n# PadFunction: IO_L4N_T0_39 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_dq[25]}]\nset_property SLEW FAST [get_ports {ddr3_dq[25]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[25]}]\nset_property LOC C13 [get_ports {ddr3_dq[25]}]\n\n# PadFunction: IO_L1N_T0_39 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_dq[26]}]\nset_property SLEW FAST [get_ports {ddr3_dq[26]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[26]}]\nset_property LOC B16 [get_ports {ddr3_dq[26]}]\n\n# PadFunction: IO_L5N_T0_39 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_dq[27]}]\nset_property SLEW FAST [get_ports {ddr3_dq[27]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[27]}]\nset_property LOC D15 [get_ports {ddr3_dq[27]}]\n\n# PadFunction: IO_L4P_T0_39 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_dq[28]}]\nset_property SLEW FAST [get_ports {ddr3_dq[28]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[28]}]\nset_property LOC D13 [get_ports {ddr3_dq[28]}]\n\n# PadFunction: IO_L6P_T0_39 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_dq[29]}]\nset_property SLEW FAST [get_ports {ddr3_dq[29]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[29]}]\nset_property LOC E12 [get_ports {ddr3_dq[29]}]\n\n# PadFunction: IO_L1P_T0_39 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_dq[30]}]\nset_property SLEW FAST [get_ports {ddr3_dq[30]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[30]}]\nset_property LOC C16 [get_ports {ddr3_dq[30]}]\n\n# PadFunction: IO_L5P_T0_39 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_dq[31]}]\nset_property SLEW FAST [get_ports {ddr3_dq[31]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[31]}]\nset_property LOC D16 [get_ports {ddr3_dq[31]}]\n\n# PadFunction: IO_L1P_T0_37 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_dq[32]}]\nset_property SLEW FAST [get_ports {ddr3_dq[32]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[32]}]\nset_property LOC A24 [get_ports {ddr3_dq[32]}]\n\n# PadFunction: IO_L4N_T0_37 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_dq[33]}]\nset_property SLEW FAST [get_ports {ddr3_dq[33]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[33]}]\nset_property LOC B23 [get_ports {ddr3_dq[33]}]\n\n# PadFunction: IO_L5N_T0_37 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_dq[34]}]\nset_property SLEW FAST [get_ports {ddr3_dq[34]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[34]}]\nset_property LOC B27 [get_ports {ddr3_dq[34]}]\n\n# PadFunction: IO_L5P_T0_37 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_dq[35]}]\nset_property SLEW FAST [get_ports {ddr3_dq[35]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[35]}]\nset_property LOC B26 [get_ports {ddr3_dq[35]}]\n\n# PadFunction: IO_L2N_T0_37 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_dq[36]}]\nset_property SLEW FAST [get_ports {ddr3_dq[36]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[36]}]\nset_property LOC A22 [get_ports {ddr3_dq[36]}]\n\n# PadFunction: IO_L2P_T0_37 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_dq[37]}]\nset_property SLEW FAST [get_ports {ddr3_dq[37]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[37]}]\nset_property LOC B22 [get_ports {ddr3_dq[37]}]\n\n# PadFunction: IO_L1N_T0_37 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_dq[38]}]\nset_property SLEW FAST [get_ports {ddr3_dq[38]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[38]}]\nset_property LOC A25 [get_ports {ddr3_dq[38]}]\n\n# PadFunction: IO_L6P_T0_37 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_dq[39]}]\nset_property SLEW FAST [get_ports {ddr3_dq[39]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[39]}]\nset_property LOC C24 [get_ports {ddr3_dq[39]}]\n\n# PadFunction: IO_L7N_T1_37 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_dq[40]}]\nset_property SLEW FAST [get_ports {ddr3_dq[40]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[40]}]\nset_property LOC E24 [get_ports {ddr3_dq[40]}]\n\n# PadFunction: IO_L10N_T1_37 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_dq[41]}]\nset_property SLEW FAST [get_ports {ddr3_dq[41]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[41]}]\nset_property LOC D23 [get_ports {ddr3_dq[41]}]\n\n# PadFunction: IO_L11N_T1_SRCC_37 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_dq[42]}]\nset_property SLEW FAST [get_ports {ddr3_dq[42]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[42]}]\nset_property LOC D26 [get_ports {ddr3_dq[42]}]\n\n# PadFunction: IO_L12P_T1_MRCC_37 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_dq[43]}]\nset_property SLEW FAST [get_ports {ddr3_dq[43]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[43]}]\nset_property LOC C25 [get_ports {ddr3_dq[43]}]\n\n# PadFunction: IO_L7P_T1_37 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_dq[44]}]\nset_property SLEW FAST [get_ports {ddr3_dq[44]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[44]}]\nset_property LOC E23 [get_ports {ddr3_dq[44]}]\n\n# PadFunction: IO_L10P_T1_37 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_dq[45]}]\nset_property SLEW FAST [get_ports {ddr3_dq[45]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[45]}]\nset_property LOC D22 [get_ports {ddr3_dq[45]}]\n\n# PadFunction: IO_L8P_T1_37 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_dq[46]}]\nset_property SLEW FAST [get_ports {ddr3_dq[46]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[46]}]\nset_property LOC F22 [get_ports {ddr3_dq[46]}]\n\n# PadFunction: IO_L8N_T1_37 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_dq[47]}]\nset_property SLEW FAST [get_ports {ddr3_dq[47]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[47]}]\nset_property LOC E22 [get_ports {ddr3_dq[47]}]\n\n# PadFunction: IO_L17N_T2_37 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_dq[48]}]\nset_property SLEW FAST [get_ports {ddr3_dq[48]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[48]}]\nset_property LOC A30 [get_ports {ddr3_dq[48]}]\n\n# PadFunction: IO_L13P_T2_MRCC_37 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_dq[49]}]\nset_property SLEW FAST [get_ports {ddr3_dq[49]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[49]}]\nset_property LOC D27 [get_ports {ddr3_dq[49]}]\n\n# PadFunction: IO_L17P_T2_37 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_dq[50]}]\nset_property SLEW FAST [get_ports {ddr3_dq[50]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[50]}]\nset_property LOC A29 [get_ports {ddr3_dq[50]}]\n\n# PadFunction: IO_L14P_T2_SRCC_37 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_dq[51]}]\nset_property SLEW FAST [get_ports {ddr3_dq[51]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[51]}]\nset_property LOC C28 [get_ports {ddr3_dq[51]}]\n\n# PadFunction: IO_L13N_T2_MRCC_37 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_dq[52]}]\nset_property SLEW FAST [get_ports {ddr3_dq[52]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[52]}]\nset_property LOC D28 [get_ports {ddr3_dq[52]}]\n\n# PadFunction: IO_L18N_T2_37 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_dq[53]}]\nset_property SLEW FAST [get_ports {ddr3_dq[53]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[53]}]\nset_property LOC B31 [get_ports {ddr3_dq[53]}]\n\n# PadFunction: IO_L16P_T2_37 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_dq[54]}]\nset_property SLEW FAST [get_ports {ddr3_dq[54]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[54]}]\nset_property LOC A31 [get_ports {ddr3_dq[54]}]\n\n# PadFunction: IO_L16N_T2_37 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_dq[55]}]\nset_property SLEW FAST [get_ports {ddr3_dq[55]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[55]}]\nset_property LOC A32 [get_ports {ddr3_dq[55]}]\n\n# PadFunction: IO_L19P_T3_37 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_dq[56]}]\nset_property SLEW FAST [get_ports {ddr3_dq[56]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[56]}]\nset_property LOC E30 [get_ports {ddr3_dq[56]}]\n\n# PadFunction: IO_L22P_T3_37 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_dq[57]}]\nset_property SLEW FAST [get_ports {ddr3_dq[57]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[57]}]\nset_property LOC F29 [get_ports {ddr3_dq[57]}]\n\n# PadFunction: IO_L24P_T3_37 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_dq[58]}]\nset_property SLEW FAST [get_ports {ddr3_dq[58]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[58]}]\nset_property LOC F30 [get_ports {ddr3_dq[58]}]\n\n# PadFunction: IO_L23N_T3_37 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_dq[59]}]\nset_property SLEW FAST [get_ports {ddr3_dq[59]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[59]}]\nset_property LOC F27 [get_ports {ddr3_dq[59]}]\n\n# PadFunction: IO_L20N_T3_37 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_dq[60]}]\nset_property SLEW FAST [get_ports {ddr3_dq[60]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[60]}]\nset_property LOC C30 [get_ports {ddr3_dq[60]}]\n\n# PadFunction: IO_L22N_T3_37 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_dq[61]}]\nset_property SLEW FAST [get_ports {ddr3_dq[61]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[61]}]\nset_property LOC E29 [get_ports {ddr3_dq[61]}]\n\n# PadFunction: IO_L23P_T3_37 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_dq[62]}]\nset_property SLEW FAST [get_ports {ddr3_dq[62]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[62]}]\nset_property LOC F26 [get_ports {ddr3_dq[62]}]\n\n# PadFunction: IO_L20P_T3_37 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_dq[63]}]\nset_property SLEW FAST [get_ports {ddr3_dq[63]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[63]}]\nset_property LOC D30 [get_ports {ddr3_dq[63]}]\n\n#set_property VCCAUX_IO HIGH [get_ports {ddr3_addr[15]}]\n#set_property SLEW FAST [get_ports {ddr3_addr[15]}]\n#set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[15]}]\n#set_property LOC E17 [get_ports {ddr3_addr[15]}]\n\nset_property VCCAUX_IO HIGH [get_ports {ddr3_addr[14]}]\nset_property SLEW FAST [get_ports {ddr3_addr[14]}]\nset_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[14]}]\nset_property LOC F17 [get_ports {ddr3_addr[14]}]\n\n# PadFunction: IO_L5N_T0_38 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_addr[13]}]\nset_property SLEW FAST [get_ports {ddr3_addr[13]}]\nset_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[13]}]\nset_property LOC A21 [get_ports {ddr3_addr[13]}]\n\n# PadFunction: IO_L2N_T0_38 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_addr[12]}]\nset_property SLEW FAST [get_ports {ddr3_addr[12]}]\nset_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[12]}]\nset_property LOC A15 [get_ports {ddr3_addr[12]}]\n\n# PadFunction: IO_L4P_T0_38 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_addr[11]}]\nset_property SLEW FAST [get_ports {ddr3_addr[11]}]\nset_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[11]}]\nset_property LOC B17 [get_ports {ddr3_addr[11]}]\n\n# PadFunction: IO_L5P_T0_38 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_addr[10]}]\nset_property SLEW FAST [get_ports {ddr3_addr[10]}]\nset_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[10]}]\nset_property LOC B21 [get_ports {ddr3_addr[10]}]\n\n# PadFunction: IO_L1P_T0_38 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_addr[9]}]\nset_property SLEW FAST [get_ports {ddr3_addr[9]}]\nset_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[9]}]\nset_property LOC C19 [get_ports {ddr3_addr[9]}]\n\n# PadFunction: IO_L10N_T1_38 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_addr[8]}]\nset_property SLEW FAST [get_ports {ddr3_addr[8]}]\nset_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[8]}]\nset_property LOC D17 [get_ports {ddr3_addr[8]}]\n\n# PadFunction: IO_L6P_T0_38 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_addr[7]}]\nset_property SLEW FAST [get_ports {ddr3_addr[7]}]\nset_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[7]}]\nset_property LOC C18 [get_ports {ddr3_addr[7]}]\n\n# PadFunction: IO_L7P_T1_38 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_addr[6]}]\nset_property SLEW FAST [get_ports {ddr3_addr[6]}]\nset_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[6]}]\nset_property LOC D20 [get_ports {ddr3_addr[6]}]\n\n# PadFunction: IO_L2P_T0_38 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_addr[5]}]\nset_property SLEW FAST [get_ports {ddr3_addr[5]}]\nset_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[5]}]\nset_property LOC A16 [get_ports {ddr3_addr[5]}]\n\n# PadFunction: IO_L4N_T0_38 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_addr[4]}]\nset_property SLEW FAST [get_ports {ddr3_addr[4]}]\nset_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[4]}]\nset_property LOC A17 [get_ports {ddr3_addr[4]}]\n\n# PadFunction: IO_L3N_T0_DQS_38 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_addr[3]}]\nset_property SLEW FAST [get_ports {ddr3_addr[3]}]\nset_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[3]}]\nset_property LOC A19 [get_ports {ddr3_addr[3]}]\n\n# PadFunction: IO_L7N_T1_38 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_addr[2]}]\nset_property SLEW FAST [get_ports {ddr3_addr[2]}]\nset_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[2]}]\nset_property LOC C20 [get_ports {ddr3_addr[2]}]\n\n# PadFunction: IO_L1N_T0_38 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_addr[1]}]\nset_property SLEW FAST [get_ports {ddr3_addr[1]}]\nset_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[1]}]\nset_property LOC B19 [get_ports {ddr3_addr[1]}]\n\n# PadFunction: IO_L3P_T0_DQS_38 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_addr[0]}]\nset_property SLEW FAST [get_ports {ddr3_addr[0]}]\nset_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[0]}]\nset_property LOC A20 [get_ports {ddr3_addr[0]}]\n\n# PadFunction: IO_L10P_T1_38 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_ba[2]}]\nset_property SLEW FAST [get_ports {ddr3_ba[2]}]\nset_property IOSTANDARD SSTL15 [get_ports {ddr3_ba[2]}]\nset_property LOC D18 [get_ports {ddr3_ba[2]}]\n\n# PadFunction: IO_L9N_T1_DQS_38 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_ba[1]}]\nset_property SLEW FAST [get_ports {ddr3_ba[1]}]\nset_property IOSTANDARD SSTL15 [get_ports {ddr3_ba[1]}]\nset_property LOC C21 [get_ports {ddr3_ba[1]}]\n\n# PadFunction: IO_L9P_T1_DQS_38 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_ba[0]}]\nset_property SLEW FAST [get_ports {ddr3_ba[0]}]\nset_property IOSTANDARD SSTL15 [get_ports {ddr3_ba[0]}]\nset_property LOC D21 [get_ports {ddr3_ba[0]}]\n\n# PadFunction: IO_L15N_T2_DQS_38 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_ras_n}]\nset_property SLEW FAST [get_ports {ddr3_ras_n}]\nset_property IOSTANDARD SSTL15 [get_ports {ddr3_ras_n}]\nset_property LOC E20 [get_ports {ddr3_ras_n}]\n\n# PadFunction: IO_L16P_T2_38 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_cas_n}]\nset_property SLEW FAST [get_ports {ddr3_cas_n}]\nset_property IOSTANDARD SSTL15 [get_ports {ddr3_cas_n}]\nset_property LOC K17 [get_ports {ddr3_cas_n}]\n\n# PadFunction: IO_L15P_T2_DQS_38 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_we_n}]\nset_property SLEW FAST [get_ports {ddr3_we_n}]\nset_property IOSTANDARD SSTL15 [get_ports {ddr3_we_n}]\nset_property LOC F20 [get_ports {ddr3_we_n}]\n\n# PadFunction: IO_L14N_T2_SRCC_37 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_reset_n}]\nset_property SLEW FAST [get_ports {ddr3_reset_n}]\nset_property IOSTANDARD LVCMOS15 [get_ports {ddr3_reset_n}]\nset_property LOC C29 [get_ports {ddr3_reset_n}]\n\n# PadFunction: IO_L14P_T2_SRCC_38 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_cke[0]}]\nset_property SLEW FAST [get_ports {ddr3_cke[0]}]\nset_property IOSTANDARD SSTL15 [get_ports {ddr3_cke[0]}]\nset_property LOC K19 [get_ports {ddr3_cke[0]}]\n\n# PadFunction: IO_L17N_T2_38 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_odt[0]}]\nset_property SLEW FAST [get_ports {ddr3_odt[0]}]\nset_property IOSTANDARD SSTL15 [get_ports {ddr3_odt[0]}]\nset_property LOC H20 [get_ports {ddr3_odt[0]}]\n\n# PadFunction: IO_L16N_T2_38 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_cs_n[0]}]\nset_property SLEW FAST [get_ports {ddr3_cs_n[0]}]\nset_property IOSTANDARD SSTL15 [get_ports {ddr3_cs_n[0]}]\nset_property LOC J17 [get_ports {ddr3_cs_n[0]}]\n\n# PadFunction: IO_L22N_T3_39 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_dm[0]}]\nset_property SLEW FAST [get_ports {ddr3_dm[0]}]\nset_property IOSTANDARD SSTL15 [get_ports {ddr3_dm[0]}]\nset_property LOC M13 [get_ports {ddr3_dm[0]}]\n\n# PadFunction: IO_L16P_T2_39 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_dm[1]}]\nset_property SLEW FAST [get_ports {ddr3_dm[1]}]\nset_property IOSTANDARD SSTL15 [get_ports {ddr3_dm[1]}]\nset_property LOC K15 [get_ports {ddr3_dm[1]}]\n\n# PadFunction: IO_L10N_T1_39 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_dm[2]}]\nset_property SLEW FAST [get_ports {ddr3_dm[2]}]\nset_property IOSTANDARD SSTL15 [get_ports {ddr3_dm[2]}]\nset_property LOC F12 [get_ports {ddr3_dm[2]}]\n\n# PadFunction: IO_L2N_T0_39 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_dm[3]}]\nset_property SLEW FAST [get_ports {ddr3_dm[3]}]\nset_property IOSTANDARD SSTL15 [get_ports {ddr3_dm[3]}]\nset_property LOC A14 [get_ports {ddr3_dm[3]}]\n\n# PadFunction: IO_L4P_T0_37 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_dm[4]}]\nset_property SLEW FAST [get_ports {ddr3_dm[4]}]\nset_property IOSTANDARD SSTL15 [get_ports {ddr3_dm[4]}]\nset_property LOC C23 [get_ports {ddr3_dm[4]}]\n\n# PadFunction: IO_L11P_T1_SRCC_37 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_dm[5]}]\nset_property SLEW FAST [get_ports {ddr3_dm[5]}]\nset_property IOSTANDARD SSTL15 [get_ports {ddr3_dm[5]}]\nset_property LOC D25 [get_ports {ddr3_dm[5]}]\n\n# PadFunction: IO_L18P_T2_37 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_dm[6]}]\nset_property SLEW FAST [get_ports {ddr3_dm[6]}]\nset_property IOSTANDARD SSTL15 [get_ports {ddr3_dm[6]}]\nset_property LOC C31 [get_ports {ddr3_dm[6]}]\n\n# PadFunction: IO_L24N_T3_37 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_dm[7]}]\nset_property SLEW FAST [get_ports {ddr3_dm[7]}]\nset_property IOSTANDARD SSTL15 [get_ports {ddr3_dm[7]}]\nset_property LOC F31 [get_ports {ddr3_dm[7]}]\n\n# PadFunction: IO_L21P_T3_DQS_39 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_dqs_p[0]}]\nset_property SLEW FAST [get_ports {ddr3_dqs_p[0]}]\nset_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports {ddr3_dqs_p[0]}]\nset_property LOC N16 [get_ports {ddr3_dqs_p[0]}]\n\n# PadFunction: IO_L21N_T3_DQS_39 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_dqs_n[0]}]\nset_property SLEW FAST [get_ports {ddr3_dqs_n[0]}]\nset_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports {ddr3_dqs_n[0]}]\nset_property LOC M16 [get_ports {ddr3_dqs_n[0]}]\n\n# PadFunction: IO_L15P_T2_DQS_39 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_dqs_p[1]}]\nset_property SLEW FAST [get_ports {ddr3_dqs_p[1]}]\nset_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports {ddr3_dqs_p[1]}]\nset_property LOC K12 [get_ports {ddr3_dqs_p[1]}]\n\n# PadFunction: IO_L15N_T2_DQS_39 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_dqs_n[1]}]\nset_property SLEW FAST [get_ports {ddr3_dqs_n[1]}]\nset_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports {ddr3_dqs_n[1]}]\nset_property LOC J12 [get_ports {ddr3_dqs_n[1]}]\n\n# PadFunction: IO_L9P_T1_DQS_39 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_dqs_p[2]}]\nset_property SLEW FAST [get_ports {ddr3_dqs_p[2]}]\nset_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports {ddr3_dqs_p[2]}]\nset_property LOC H16 [get_ports {ddr3_dqs_p[2]}]\n\n# PadFunction: IO_L9N_T1_DQS_39 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_dqs_n[2]}]\nset_property SLEW FAST [get_ports {ddr3_dqs_n[2]}]\nset_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports {ddr3_dqs_n[2]}]\nset_property LOC G16 [get_ports {ddr3_dqs_n[2]}]\n\n# PadFunction: IO_L3P_T0_DQS_39 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_dqs_p[3]}]\nset_property SLEW FAST [get_ports {ddr3_dqs_p[3]}]\nset_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports {ddr3_dqs_p[3]}]\nset_property LOC C15 [get_ports {ddr3_dqs_p[3]}]\n\n# PadFunction: IO_L3N_T0_DQS_39 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_dqs_n[3]}]\nset_property SLEW FAST [get_ports {ddr3_dqs_n[3]}]\nset_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports {ddr3_dqs_n[3]}]\nset_property LOC C14 [get_ports {ddr3_dqs_n[3]}]\n\n# PadFunction: IO_L3P_T0_DQS_37 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_dqs_p[4]}]\nset_property SLEW FAST [get_ports {ddr3_dqs_p[4]}]\nset_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports {ddr3_dqs_p[4]}]\nset_property LOC A26 [get_ports {ddr3_dqs_p[4]}]\n\n# PadFunction: IO_L3N_T0_DQS_37 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_dqs_n[4]}]\nset_property SLEW FAST [get_ports {ddr3_dqs_n[4]}]\nset_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports {ddr3_dqs_n[4]}]\nset_property LOC A27 [get_ports {ddr3_dqs_n[4]}]\n\n# PadFunction: IO_L9P_T1_DQS_37 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_dqs_p[5]}]\nset_property SLEW FAST [get_ports {ddr3_dqs_p[5]}]\nset_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports {ddr3_dqs_p[5]}]\nset_property LOC F25 [get_ports {ddr3_dqs_p[5]}]\n\n# PadFunction: IO_L9N_T1_DQS_37 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_dqs_n[5]}]\nset_property SLEW FAST [get_ports {ddr3_dqs_n[5]}]\nset_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports {ddr3_dqs_n[5]}]\nset_property LOC E25 [get_ports {ddr3_dqs_n[5]}]\n\n# PadFunction: IO_L15P_T2_DQS_37 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_dqs_p[6]}]\nset_property SLEW FAST [get_ports {ddr3_dqs_p[6]}]\nset_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports {ddr3_dqs_p[6]}]\nset_property LOC B28 [get_ports {ddr3_dqs_p[6]}]\n\n# PadFunction: IO_L15N_T2_DQS_37 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_dqs_n[6]}]\nset_property SLEW FAST [get_ports {ddr3_dqs_n[6]}]\nset_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports {ddr3_dqs_n[6]}]\nset_property LOC B29 [get_ports {ddr3_dqs_n[6]}]\n\n# PadFunction: IO_L21P_T3_DQS_37 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_dqs_p[7]}]\nset_property SLEW FAST [get_ports {ddr3_dqs_p[7]}]\nset_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports {ddr3_dqs_p[7]}]\nset_property LOC E27 [get_ports {ddr3_dqs_p[7]}]\n\n# PadFunction: IO_L21N_T3_DQS_37 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_dqs_n[7]}]\nset_property SLEW FAST [get_ports {ddr3_dqs_n[7]}]\nset_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports {ddr3_dqs_n[7]}]\nset_property LOC E28 [get_ports {ddr3_dqs_n[7]}]\n\n# PadFunction: IO_L13P_T2_MRCC_38 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_ck_p[0]}]\nset_property SLEW FAST [get_ports {ddr3_ck_p[0]}]\nset_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_ck_p[0]}]\nset_property LOC H19 [get_ports {ddr3_ck_p[0]}]\n\n# PadFunction: IO_L13N_T2_MRCC_38 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_ck_n[0]}]\nset_property SLEW FAST [get_ports {ddr3_ck_n[0]}]\nset_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_ck_n[0]}]\nset_property LOC G18 [get_ports {ddr3_ck_n[0]}]\n"
  },
  {
    "path": "constraints/xilinx/vc707g2-axiddr3.prj",
    "content": "<?xml version='1.0' encoding='UTF-8'?>\n<!-- IMPORTANT: This is an internal file that has been generated by the MIG software. Any direct editing or changes made to this file may result in unpredictable behavior or data corruption. It is strongly advised that users do not edit the contents of this file. Re-run the MIG GUI with the required settings if any of the options provided below need to be altered. -->\n<Project NoOfControllers=\"1\" >\n    <ModuleName>mig_7series_0</ModuleName>\n    <dci_inouts_inputs>1</dci_inouts_inputs>\n    <dci_inputs>1</dci_inputs>\n    <Debug_En>OFF</Debug_En>\n    <DataDepth_En>1024</DataDepth_En>\n    <LowPower_En>ON</LowPower_En>\n    <XADC_En>Enabled</XADC_En>\n    <TargetFPGA>xc7vx485t-ffg1761/-2</TargetFPGA>\n    <Version>2.3</Version>\n    <SystemClock>No Buffer</SystemClock>\n    <ReferenceClock>Use System Clock</ReferenceClock>\n    <SysResetPolarity>ACTIVE LOW</SysResetPolarity>\n    <BankSelectionFlag>FALSE</BankSelectionFlag>\n    <InternalVref>0</InternalVref>\n    <dci_hr_inouts_inputs>50 Ohms</dci_hr_inouts_inputs>\n    <dci_cascade>0</dci_cascade>\n    <Controller number=\"0\" >\n        <MemoryDevice>DDR3_SDRAM/SODIMMs/MT8JTF12864HZ-1G6</MemoryDevice>\n        <TimePeriod>1250</TimePeriod>\n        <VccAuxIO>2.0V</VccAuxIO>\n        <PHYRatio>4:1</PHYRatio>\n        <InputClkFreq>200</InputClkFreq>\n        <UIExtraClocks>0</UIExtraClocks>\n        <MMCM_VCO>800</MMCM_VCO>\n        <MMCMClkOut0> 1.000</MMCMClkOut0>\n        <MMCMClkOut1>1</MMCMClkOut1>\n        <MMCMClkOut2>1</MMCMClkOut2>\n        <MMCMClkOut3>1</MMCMClkOut3>\n        <MMCMClkOut4>1</MMCMClkOut4>\n        <DataWidth>64</DataWidth>\n        <DeepMemory>1</DeepMemory>\n        <DataMask>1</DataMask>\n        <ECC>Disabled</ECC>\n        <Ordering>Normal</Ordering>\n        <CustomPart>FALSE</CustomPart>\n        <NewPartName></NewPartName>\n        <RowAddress>14</RowAddress>\n        <ColAddress>10</ColAddress>\n        <BankAddress>3</BankAddress>\n        <MemoryVoltage>1.5V</MemoryVoltage>\n        <UserMemoryAddressMap>BANK_ROW_COLUMN</UserMemoryAddressMap>\n        <PinSelection>\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15\" PADName=\"A20\" SLEW=\"\" name=\"ddr3_addr[0]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15\" PADName=\"B21\" SLEW=\"\" name=\"ddr3_addr[10]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15\" PADName=\"B17\" SLEW=\"\" name=\"ddr3_addr[11]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15\" PADName=\"A15\" SLEW=\"\" name=\"ddr3_addr[12]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15\" PADName=\"A21\" SLEW=\"\" name=\"ddr3_addr[13]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15\" PADName=\"B19\" SLEW=\"\" name=\"ddr3_addr[1]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15\" PADName=\"C20\" SLEW=\"\" name=\"ddr3_addr[2]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15\" PADName=\"A19\" SLEW=\"\" name=\"ddr3_addr[3]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15\" PADName=\"A17\" SLEW=\"\" name=\"ddr3_addr[4]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15\" PADName=\"A16\" SLEW=\"\" name=\"ddr3_addr[5]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15\" PADName=\"D20\" SLEW=\"\" name=\"ddr3_addr[6]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15\" PADName=\"C18\" SLEW=\"\" name=\"ddr3_addr[7]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15\" PADName=\"D17\" SLEW=\"\" name=\"ddr3_addr[8]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15\" PADName=\"C19\" SLEW=\"\" name=\"ddr3_addr[9]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15\" PADName=\"D21\" SLEW=\"\" name=\"ddr3_ba[0]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15\" PADName=\"C21\" SLEW=\"\" name=\"ddr3_ba[1]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15\" PADName=\"D18\" SLEW=\"\" name=\"ddr3_ba[2]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15\" PADName=\"K17\" SLEW=\"\" name=\"ddr3_cas_n\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"DIFF_SSTL15\" PADName=\"G18\" SLEW=\"\" name=\"ddr3_ck_n[0]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"DIFF_SSTL15\" PADName=\"H19\" SLEW=\"\" name=\"ddr3_ck_p[0]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15\" PADName=\"K19\" SLEW=\"\" name=\"ddr3_cke[0]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15\" PADName=\"J17\" SLEW=\"\" name=\"ddr3_cs_n[0]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15\" PADName=\"M13\" SLEW=\"\" name=\"ddr3_dm[0]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15\" PADName=\"K15\" SLEW=\"\" name=\"ddr3_dm[1]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15\" PADName=\"F12\" SLEW=\"\" name=\"ddr3_dm[2]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15\" PADName=\"A14\" SLEW=\"\" name=\"ddr3_dm[3]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15\" PADName=\"C23\" SLEW=\"\" name=\"ddr3_dm[4]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15\" PADName=\"D25\" SLEW=\"\" name=\"ddr3_dm[5]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15\" PADName=\"C31\" SLEW=\"\" name=\"ddr3_dm[6]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15\" PADName=\"F31\" SLEW=\"\" name=\"ddr3_dm[7]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"N14\" SLEW=\"\" name=\"ddr3_dq[0]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"H13\" SLEW=\"\" name=\"ddr3_dq[10]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"J13\" SLEW=\"\" name=\"ddr3_dq[11]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"L16\" SLEW=\"\" name=\"ddr3_dq[12]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"L15\" SLEW=\"\" name=\"ddr3_dq[13]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"H14\" SLEW=\"\" name=\"ddr3_dq[14]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"J15\" SLEW=\"\" name=\"ddr3_dq[15]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"E15\" SLEW=\"\" name=\"ddr3_dq[16]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"E13\" SLEW=\"\" name=\"ddr3_dq[17]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"F15\" SLEW=\"\" name=\"ddr3_dq[18]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"E14\" SLEW=\"\" name=\"ddr3_dq[19]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"N13\" SLEW=\"\" name=\"ddr3_dq[1]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"G13\" SLEW=\"\" name=\"ddr3_dq[20]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"G12\" SLEW=\"\" name=\"ddr3_dq[21]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"F14\" SLEW=\"\" name=\"ddr3_dq[22]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"G14\" SLEW=\"\" name=\"ddr3_dq[23]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"B14\" SLEW=\"\" name=\"ddr3_dq[24]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"C13\" SLEW=\"\" name=\"ddr3_dq[25]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"B16\" SLEW=\"\" name=\"ddr3_dq[26]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"D15\" SLEW=\"\" name=\"ddr3_dq[27]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"D13\" SLEW=\"\" name=\"ddr3_dq[28]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"E12\" SLEW=\"\" name=\"ddr3_dq[29]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"L14\" SLEW=\"\" name=\"ddr3_dq[2]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"C16\" SLEW=\"\" name=\"ddr3_dq[30]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"D16\" SLEW=\"\" name=\"ddr3_dq[31]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"A24\" SLEW=\"\" name=\"ddr3_dq[32]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"B23\" SLEW=\"\" name=\"ddr3_dq[33]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"B27\" SLEW=\"\" name=\"ddr3_dq[34]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"B26\" SLEW=\"\" name=\"ddr3_dq[35]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"A22\" SLEW=\"\" name=\"ddr3_dq[36]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"B22\" SLEW=\"\" name=\"ddr3_dq[37]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"A25\" SLEW=\"\" name=\"ddr3_dq[38]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"C24\" SLEW=\"\" name=\"ddr3_dq[39]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"M14\" SLEW=\"\" name=\"ddr3_dq[3]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"E24\" SLEW=\"\" name=\"ddr3_dq[40]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"D23\" SLEW=\"\" name=\"ddr3_dq[41]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"D26\" SLEW=\"\" name=\"ddr3_dq[42]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"C25\" SLEW=\"\" name=\"ddr3_dq[43]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"E23\" SLEW=\"\" name=\"ddr3_dq[44]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"D22\" SLEW=\"\" name=\"ddr3_dq[45]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"F22\" SLEW=\"\" name=\"ddr3_dq[46]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"E22\" SLEW=\"\" name=\"ddr3_dq[47]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"A30\" SLEW=\"\" name=\"ddr3_dq[48]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"D27\" SLEW=\"\" name=\"ddr3_dq[49]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"M12\" SLEW=\"\" name=\"ddr3_dq[4]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"A29\" SLEW=\"\" name=\"ddr3_dq[50]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"C28\" SLEW=\"\" name=\"ddr3_dq[51]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"D28\" SLEW=\"\" name=\"ddr3_dq[52]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"B31\" SLEW=\"\" name=\"ddr3_dq[53]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"A31\" SLEW=\"\" name=\"ddr3_dq[54]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"A32\" SLEW=\"\" name=\"ddr3_dq[55]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"E30\" SLEW=\"\" name=\"ddr3_dq[56]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"F29\" SLEW=\"\" name=\"ddr3_dq[57]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"F30\" SLEW=\"\" name=\"ddr3_dq[58]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"F27\" SLEW=\"\" name=\"ddr3_dq[59]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"N15\" SLEW=\"\" name=\"ddr3_dq[5]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"C30\" SLEW=\"\" name=\"ddr3_dq[60]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"E29\" SLEW=\"\" name=\"ddr3_dq[61]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"F26\" SLEW=\"\" name=\"ddr3_dq[62]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"D30\" SLEW=\"\" name=\"ddr3_dq[63]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"M11\" SLEW=\"\" name=\"ddr3_dq[6]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"L12\" SLEW=\"\" name=\"ddr3_dq[7]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"K14\" SLEW=\"\" name=\"ddr3_dq[8]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"K13\" SLEW=\"\" name=\"ddr3_dq[9]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"DIFF_SSTL15_T_DCI\" PADName=\"M16\" SLEW=\"\" name=\"ddr3_dqs_n[0]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"DIFF_SSTL15_T_DCI\" PADName=\"J12\" SLEW=\"\" name=\"ddr3_dqs_n[1]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"DIFF_SSTL15_T_DCI\" PADName=\"G16\" SLEW=\"\" name=\"ddr3_dqs_n[2]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"DIFF_SSTL15_T_DCI\" PADName=\"C14\" SLEW=\"\" name=\"ddr3_dqs_n[3]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"DIFF_SSTL15_T_DCI\" PADName=\"A27\" SLEW=\"\" name=\"ddr3_dqs_n[4]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"DIFF_SSTL15_T_DCI\" PADName=\"E25\" SLEW=\"\" name=\"ddr3_dqs_n[5]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"DIFF_SSTL15_T_DCI\" PADName=\"B29\" SLEW=\"\" name=\"ddr3_dqs_n[6]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"DIFF_SSTL15_T_DCI\" PADName=\"E28\" SLEW=\"\" name=\"ddr3_dqs_n[7]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"DIFF_SSTL15_T_DCI\" PADName=\"N16\" SLEW=\"\" name=\"ddr3_dqs_p[0]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"DIFF_SSTL15_T_DCI\" PADName=\"K12\" SLEW=\"\" name=\"ddr3_dqs_p[1]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"DIFF_SSTL15_T_DCI\" PADName=\"H16\" SLEW=\"\" name=\"ddr3_dqs_p[2]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"DIFF_SSTL15_T_DCI\" PADName=\"C15\" SLEW=\"\" name=\"ddr3_dqs_p[3]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"DIFF_SSTL15_T_DCI\" PADName=\"A26\" SLEW=\"\" name=\"ddr3_dqs_p[4]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"DIFF_SSTL15_T_DCI\" PADName=\"F25\" SLEW=\"\" name=\"ddr3_dqs_p[5]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"DIFF_SSTL15_T_DCI\" PADName=\"B28\" SLEW=\"\" name=\"ddr3_dqs_p[6]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"DIFF_SSTL15_T_DCI\" PADName=\"E27\" SLEW=\"\" name=\"ddr3_dqs_p[7]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15\" PADName=\"H20\" SLEW=\"\" name=\"ddr3_odt[0]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15\" PADName=\"E20\" SLEW=\"\" name=\"ddr3_ras_n\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"LVCMOS15\" PADName=\"C29\" SLEW=\"\" name=\"ddr3_reset_n\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15\" PADName=\"F20\" SLEW=\"\" name=\"ddr3_we_n\" IN_TERM=\"\" />\n        </PinSelection>\n        <System_Control>\n            <Pin PADName=\"No connect\" Bank=\"Select Bank\" name=\"sys_rst\" />\n            <Pin PADName=\"No connect\" Bank=\"Select Bank\" name=\"init_calib_complete\" />\n            <Pin PADName=\"No connect\" Bank=\"Select Bank\" name=\"tg_compare_error\" />\n        </System_Control>\n        <TimingParameters>\n            <Parameters twtr=\"7.5\" trrd=\"6\" trefi=\"7.8\" tfaw=\"30\" trtp=\"7.5\" tcke=\"5\" trfc=\"110\" trp=\"13.75\" tras=\"35\" trcd=\"13.75\" />\n        </TimingParameters>\n        <mrBurstLength name=\"Burst Length\" >8 - Fixed</mrBurstLength>\n        <mrBurstType name=\"Read Burst Type and Length\" >Sequential</mrBurstType>\n        <mrCasLatency name=\"CAS Latency\" >11</mrCasLatency>\n        <mrMode name=\"Mode\" >Normal</mrMode>\n        <mrDllReset name=\"DLL Reset\" >No</mrDllReset>\n        <mrPdMode name=\"DLL control for precharge PD\" >Slow Exit</mrPdMode>\n        <emrDllEnable name=\"DLL Enable\" >Enable</emrDllEnable>\n        <emrOutputDriveStrength name=\"Output Driver Impedance Control\" >RZQ/7</emrOutputDriveStrength>\n        <emrMirrorSelection name=\"Address Mirroring\" >Disable</emrMirrorSelection>\n        <emrCSSelection name=\"Controller Chip Select Pin\" >Enable</emrCSSelection>\n        <emrRTT name=\"RTT (nominal) - On Die Termination (ODT)\" >RZQ/4</emrRTT>\n        <emrPosted name=\"Additive Latency (AL)\" >0</emrPosted>\n        <emrOCD name=\"Write Leveling Enable\" >Disabled</emrOCD>\n        <emrDQS name=\"TDQS enable\" >Enabled</emrDQS>\n        <emrRDQS name=\"Qoff\" >Output Buffer Enabled</emrRDQS>\n        <mr2PartialArraySelfRefresh name=\"Partial-Array Self Refresh\" >Full Array</mr2PartialArraySelfRefresh>\n        <mr2CasWriteLatency name=\"CAS write latency\" >8</mr2CasWriteLatency>\n        <mr2AutoSelfRefresh name=\"Auto Self Refresh\" >Enabled</mr2AutoSelfRefresh>\n        <mr2SelfRefreshTempRange name=\"High Temparature Self Refresh Rate\" >Normal</mr2SelfRefreshTempRange>\n        <mr2RTTWR name=\"RTT_WR - Dynamic On Die Termination (ODT)\" >Dynamic ODT off</mr2RTTWR>\n        <PortInterface>AXI</PortInterface>\n        <AXIParameters>\n            <C0_C_RD_WR_ARB_ALGORITHM>RD_PRI_REG</C0_C_RD_WR_ARB_ALGORITHM>\n            <C0_S_AXI_ADDR_WIDTH>30</C0_S_AXI_ADDR_WIDTH>\n            <C0_S_AXI_DATA_WIDTH>512</C0_S_AXI_DATA_WIDTH>\n            <C0_S_AXI_ID_WIDTH>6</C0_S_AXI_ID_WIDTH>\n            <C0_S_AXI_SUPPORTS_NARROW_BURST>0</C0_S_AXI_SUPPORTS_NARROW_BURST>\n        </AXIParameters>\n    </Controller>\n\n</Project>\n"
  },
  {
    "path": "constraints/xilinx/vc707g2.xdc",
    "content": "######################################################################################################\n##  File name :       default.xdc\n##\n##  Details :     Constraints file\n##                    FPGA family:       virtex7\n##                    FPGA:              xc7vx485t-2ffg1761C\n##                    Speedgrade:        -2\n##\n######################################################################################################\n\n######################################################################################################\n# PIN ASSIGNMENTS\n######################################################################################################\nset_property LOC AD8  [get_ports { CLK_pci_sys_clk_p }]\nset_property LOC AD7  [get_ports { CLK_pci_sys_clk_n }]\nset_property LOC AV35 [get_ports { RST_N_pci_sys_reset_n }]\nset_property LOC E19  [get_ports { CLK_sys_clk_p }]\nset_property LOC E18  [get_ports { CLK_sys_clk_n }]\n\nset_property LOC Y4   [get_ports { PCIE_rxp_v[0] }]\nset_property LOC AA6  [get_ports { PCIE_rxp_v[1] }]\nset_property LOC AB4  [get_ports { PCIE_rxp_v[2] }]\nset_property LOC AC6  [get_ports { PCIE_rxp_v[3] }]\nset_property LOC AD4  [get_ports { PCIE_rxp_v[4] }]\nset_property LOC AE6  [get_ports { PCIE_rxp_v[5] }]\nset_property LOC AF4  [get_ports { PCIE_rxp_v[6] }]\nset_property LOC AG6  [get_ports { PCIE_rxp_v[7] }]\n\nset_property LOC Y3   [get_ports { PCIE_rxn_v[0] }]\nset_property LOC AA5  [get_ports { PCIE_rxn_v[1] }]\nset_property LOC AB3  [get_ports { PCIE_rxn_v[2] }]\nset_property LOC AC5  [get_ports { PCIE_rxn_v[3] }]\nset_property LOC AD3  [get_ports { PCIE_rxn_v[4] }]\nset_property LOC AE5  [get_ports { PCIE_rxn_v[5] }]\nset_property LOC AF3  [get_ports { PCIE_rxn_v[6] }]\nset_property LOC AG5  [get_ports { PCIE_rxn_v[7] }]\n\nset_property LOC W2   [get_ports { PCIE_txp[0] }]\nset_property LOC AA2  [get_ports { PCIE_txp[1] }]\nset_property LOC AC2  [get_ports { PCIE_txp[2] }]\nset_property LOC AE2  [get_ports { PCIE_txp[3] }]\nset_property LOC AG2  [get_ports { PCIE_txp[4] }]\nset_property LOC AH4  [get_ports { PCIE_txp[5] }]\nset_property LOC AJ2  [get_ports { PCIE_txp[6] }]\nset_property LOC AK4  [get_ports { PCIE_txp[7] }]\n\nset_property LOC W1   [get_ports { PCIE_txn[0] }]\nset_property LOC AA1  [get_ports { PCIE_txn[1] }]\nset_property LOC AC1  [get_ports { PCIE_txn[2] }]\nset_property LOC AE1  [get_ports { PCIE_txn[3] }]\nset_property LOC AG1  [get_ports { PCIE_txn[4] }]\nset_property LOC AH3  [get_ports { PCIE_txn[5] }]\nset_property LOC AJ1  [get_ports { PCIE_txn[6] }]\nset_property LOC AK3  [get_ports { PCIE_txn[7] }]\n\n######################################################################################################\n# I/O STANDARDS\n######################################################################################################\nset_property IOSTANDARD DIFF_SSTL15 [get_ports { CLK_sys_clk_* }]\nset_property IOSTANDARD LVCMOS18    [get_ports { RST_N_pci_sys_reset_n }]\nset_property PULLUP     true        [get_ports { RST_N_pci_sys_reset_n }]\n\n######################################################################################################\n# CELL LOCATIONS\n######################################################################################################\n#\n# SYS clock 100 MHz (input) signal. The sys_clk_p and sys_clk_n\n# signals are the PCI Express reference clock. Virtex-7 GT\n# Transceiver architecture requires the use of a dedicated clock\n# resources (FPGA input pins) associated with each GT Transceiver.\n# To use these pins an IBUFDS primitive (refclk_ibuf) is\n# instantiated in user's design.\n# Please refer to the Virtex-7 GT Transceiver User Guide\n# (UG) for guidelines regarding clock resource selection.\n#\nset_property LOC IBUFDS_GTE2_X1Y5  [get_cells { host_pcieHostTop_clockGen }]\n\n\nset_property LOC MMCME2_ADV_X1Y1 [get_cells -hier -filter { NAME =~ *clkgen_pll }]\n\n######################################################################################################\n# TIMING CONSTRAINTS\n######################################################################################################\n\n## in pcie-clocks.xdc\n"
  },
  {
    "path": "constraints/xilinx/vc709.xdc",
    "content": "######################################################################################################\n##  File name :       default.xdc\n##\n##  Details :     Constraints file\n##                    FPGA family:       virtex7\n##                    FPGA:              xc7vx690t-3ffg1761C\n##                    Speedgrade:        -3\n##\n######################################################################################################\n\n##The following two properties should be set for every design\nset_property CFGBVS GND [current_design]\nset_property CONFIG_VOLTAGE 1.8 [current_design]\n\n######################################################################################################\n# PIN ASSIGNMENTS\n######################################################################################################\nset_property LOC AB7  [get_ports { CLK_pci_sys_clk_n }]\nset_property LOC AB8  [get_ports { CLK_pci_sys_clk_p }]\nset_property LOC AV35 [get_ports { RST_N_pci_sys_reset_n }]\nset_property LOC H19  [get_ports { CLK_sys_clk_p }]\nset_property LOC G18  [get_ports { CLK_sys_clk_n }]\n\n######################################################################################################\n# I/O STANDARDS\n######################################################################################################\nset_property IOSTANDARD LVCMOS15    [get_ports { leds_leds[*] }]\nset_property IOSTANDARD DIFF_SSTL15 [get_ports { CLK_sys_clk_* }]\nset_property IOSTANDARD LVCMOS18    [get_ports { RST_N_pci_sys_reset_n }]\nset_property PULLUP     true        [get_ports { RST_N_pci_sys_reset_n }]\n\n######################################################################################################\n# TIMING CONSTRAINTS\n######################################################################################################\n\n## in pcie-clocks.xdc\n\n"
  },
  {
    "path": "constraints/xilinx/vcu108.xdc",
    "content": "######################################################################################################\n##  File name :       default.xdc\n##\n##  Details :     Constraints file\n##                    FPGA family:       virtex7\n##                    FPGA:              xc7vx485t-2ffg1761C\n##                    Speedgrade:        -2\n##\n######################################################################################################\n\n######################################################################################################\n# PIN ASSIGNMENTS\n######################################################################################################\nset_property LOC AL9  [get_ports { CLK_pci_sys_clk_p }]\nset_property LOC AL8  [get_ports { CLK_pci_sys_clk_n }]\nset_property LOC AM17 [get_ports { RST_N_pci_sys_reset_n }]\nset_property LOC G31  [get_ports { CLK_sys_clk1_300_p }]\nset_property LOC F31  [get_ports { CLK_sys_clk1_300_n }]\nset_property LOC G22  [get_ports { CLK_sys_clk2_300_p }]\nset_property LOC G21  [get_ports { CLK_sys_clk2_300_n }]\n\nset_property IOSTANDARD DIFF_SSTL12 [get_ports { CLK_sys_clk1_300_p }]\nset_property IOSTANDARD DIFF_SSTL12 [get_ports { CLK_sys_clk1_300_n }]\nset_property IOSTANDARD DIFF_SSTL12 [get_ports { CLK_sys_clk2_300_p }]\nset_property IOSTANDARD DIFF_SSTL12 [get_ports { CLK_sys_clk2_300_n }]\n\nset_property IOSTANDARD LVCMOS18    [get_ports { RST_N_pci_sys_reset_n }]\nset_property PULLUP     true        [get_ports { RST_N_pci_sys_reset_n }]\n"
  },
  {
    "path": "constraints/xilinx/vcu118.xdc",
    "content": "######################################################################################################\n##  File name :       vcu118.xdc\n##\n\n######################################################################################################\n# PIN ASSIGNMENTS\n######################################################################################################\n#set_property LOC AL9  [get_ports { CLK_pci_sys_clk_p }]\n#set_property LOC AL8  [get_ports { CLK_pci_sys_clk_n }]\nset_property LOC AC9  [get_ports { CLK_pci_sys_clk_p }]\nset_property LOC AC8  [get_ports { CLK_pci_sys_clk_n }]\nset_property LOC AM17 [get_ports { RST_N_pci_sys_reset_n }]\n    \nset_property LOC G31  [get_ports { CLK_sys_clk_300_p }]\nset_property IOSTANDARD DIFF_SSTL12 [get_ports { CLK_sys_clk_300_p }]\nset_property LOC F31  [get_ports { CLK_sys_clk_300_n }]\nset_property IOSTANDARD DIFF_SSTL12 [get_ports { CLK_sys_clk_300_n }]\n\n\nset_property PACKAGE_PIN E12 [ get_ports { CLK_sys_clk1_250_p } ]\nset_property IOSTANDARD DIFF_SSTL12 [ get_ports { CLK_sys_clk1_250_p } ]\nset_property PACKAGE_PIN D12 [ get_ports { CLK_sys_clk1_250_n } ]\nset_property IOSTANDARD DIFF_SSTL12 [ get_ports { CLK_sys_clk1_250_n } ]\n\n    \nset_property PACKAGE_PIN AW26 [ get_ports { CLK_sys_clk2_250_p } ]\nset_property IOSTANDARD DIFF_SSTL12 [ get_ports { CLK_sys_clk2_250_p } ]\nset_property PACKAGE_PIN AW27 [ get_ports { CLK_sys_clk2_250_n } ]\nset_property IOSTANDARD DIFF_SSTL12 [ get_ports { CLK_sys_clk2_250_n } ]\n\n\n\n\nset_property IOSTANDARD LVCMOS18    [get_ports { RST_N_pci_sys_reset_n }]\nset_property PULLUP     true        [get_ports { RST_N_pci_sys_reset_n }]\n"
  },
  {
    "path": "constraints/xilinx/verilator.xdc",
    "content": "this file intentionally left blank\n"
  },
  {
    "path": "constraints/xilinx/xc7z010clg400.xdc",
    "content": "#created using vivado from microzed board type\n# create_clock manually commented out\n############################################################################\n##\n##  Xilinx, Inc. 2006            www.xilinx.com\n############################################################################\n##  File name :       ps7_constraints.xdc\n##\n##  Details :     Constraints file\n##                    FPGA family:       zynq\n##                    FPGA:              xc7z010clg400-1\n##                    Device Size:        xc7z010\n##                    Package:            clg400\n##                    Speedgrade:         -1\n##\n##\n############################################################################\n############################################################################\n############################################################################\n# Clock constraints                                                        #\n############################################################################\n## get the period from the clock generator cell\ncreate_clock -name clk_fpga_0 -period [get_property CLKIN1_PERIOD [get_cells -hierarchical ps7_clockGen_pll]] [get_pins \"*ps7_foo/FCLKCLK[0]\"]\nset_input_jitter clk_fpga_0 [expr 0.3 * [get_property CLKIN1_PERIOD [get_cells -hierarchical ps7_clockGen_pll]]]\nset_clock_groups -asynchronous -group {clk_fpga_0}\ncreate_clock -name clk_fpga_1 -period \"6\" [get_pins \"*ps7_foo/FCLKCLK[1]\"]\nset_input_jitter clk_fpga_1 0.6\nset_clock_groups -asynchronous -group {clk_fpga_1}\ncreate_clock -name clk_fpga_3 -period \"5\" [get_pins \"*ps7_foo/FCLKCLK[3]\"]\nset_input_jitter clk_fpga_3 0.6\nset_clock_groups -asynchronous -group {clk_fpga_3}\n\n\n############################################################################\n# I/O STANDARDS and Location Constraints                                   #\n############################################################################\n\n#  Enet 0 / mdio / MIO[53]\nset_property iostandard \"LVCMOS18\" [get_ports \"MIO[53]\"]\nset_property PACKAGE_PIN \"C11\" [get_ports \"MIO[53]\"]\nset_property slew \"slow\" [get_ports \"MIO[53]\"]\nset_property drive \"8\" [get_ports \"MIO[53]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"MIO[53]\"]\n#  Enet 0 / mdc / MIO[52]\nset_property iostandard \"LVCMOS18\" [get_ports \"MIO[52]\"]\nset_property PACKAGE_PIN \"C10\" [get_ports \"MIO[52]\"]\nset_property slew \"slow\" [get_ports \"MIO[52]\"]\nset_property drive \"8\" [get_ports \"MIO[52]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"MIO[52]\"]\n#  GPIO / gpio[51] / MIO[51]\nset_property iostandard \"LVCMOS18\" [get_ports \"MIO[51]\"]\nset_property PACKAGE_PIN \"B9\" [get_ports \"MIO[51]\"]\nset_property slew \"slow\" [get_ports \"MIO[51]\"]\nset_property drive \"8\" [get_ports \"MIO[51]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"MIO[51]\"]\n#  SD 0 / wp / MIO[50]\nset_property iostandard \"LVCMOS18\" [get_ports \"MIO[50]\"]\nset_property PACKAGE_PIN \"B13\" [get_ports \"MIO[50]\"]\nset_property slew \"slow\" [get_ports \"MIO[50]\"]\nset_property drive \"8\" [get_ports \"MIO[50]\"]\nset_property PIO_DIRECTION \"INPUT\" [get_ports \"MIO[50]\"]\n#  UART 1 / rx / MIO[49]\nset_property iostandard \"LVCMOS18\" [get_ports \"MIO[49]\"]\nset_property PACKAGE_PIN \"C12\" [get_ports \"MIO[49]\"]\nset_property slew \"slow\" [get_ports \"MIO[49]\"]\nset_property drive \"8\" [get_ports \"MIO[49]\"]\nset_property PIO_DIRECTION \"INPUT\" [get_ports \"MIO[49]\"]\n#  UART 1 / tx / MIO[48]\nset_property iostandard \"LVCMOS18\" [get_ports \"MIO[48]\"]\nset_property PACKAGE_PIN \"B12\" [get_ports \"MIO[48]\"]\nset_property slew \"slow\" [get_ports \"MIO[48]\"]\nset_property drive \"8\" [get_ports \"MIO[48]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"MIO[48]\"]\n#  GPIO / gpio[47] / MIO[47]\nset_property iostandard \"LVCMOS18\" [get_ports \"MIO[47]\"]\nset_property PACKAGE_PIN \"B14\" [get_ports \"MIO[47]\"]\nset_property slew \"slow\" [get_ports \"MIO[47]\"]\nset_property drive \"8\" [get_ports \"MIO[47]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"MIO[47]\"]\n#  SD 0 / cd / MIO[46]\nset_property iostandard \"LVCMOS18\" [get_ports \"MIO[46]\"]\nset_property PACKAGE_PIN \"D16\" [get_ports \"MIO[46]\"]\nset_property slew \"slow\" [get_ports \"MIO[46]\"]\nset_property drive \"8\" [get_ports \"MIO[46]\"]\nset_property PIO_DIRECTION \"INPUT\" [get_ports \"MIO[46]\"]\n#  SD 0 / data[3] / MIO[45]\nset_property iostandard \"LVCMOS18\" [get_ports \"MIO[45]\"]\nset_property PACKAGE_PIN \"B15\" [get_ports \"MIO[45]\"]\nset_property slew \"slow\" [get_ports \"MIO[45]\"]\nset_property drive \"8\" [get_ports \"MIO[45]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"MIO[45]\"]\n#  SD 0 / data[2] / MIO[44]\nset_property iostandard \"LVCMOS18\" [get_ports \"MIO[44]\"]\nset_property PACKAGE_PIN \"F13\" [get_ports \"MIO[44]\"]\nset_property slew \"slow\" [get_ports \"MIO[44]\"]\nset_property drive \"8\" [get_ports \"MIO[44]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"MIO[44]\"]\n#  SD 0 / data[1] / MIO[43]\nset_property iostandard \"LVCMOS18\" [get_ports \"MIO[43]\"]\nset_property PACKAGE_PIN \"A9\" [get_ports \"MIO[43]\"]\nset_property slew \"slow\" [get_ports \"MIO[43]\"]\nset_property drive \"8\" [get_ports \"MIO[43]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"MIO[43]\"]\n#  SD 0 / data[0] / MIO[42]\nset_property iostandard \"LVCMOS18\" [get_ports \"MIO[42]\"]\nset_property PACKAGE_PIN \"E12\" [get_ports \"MIO[42]\"]\nset_property slew \"slow\" [get_ports \"MIO[42]\"]\nset_property drive \"8\" [get_ports \"MIO[42]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"MIO[42]\"]\n#  SD 0 / cmd / MIO[41]\nset_property iostandard \"LVCMOS18\" [get_ports \"MIO[41]\"]\nset_property PACKAGE_PIN \"C17\" [get_ports \"MIO[41]\"]\nset_property slew \"slow\" [get_ports \"MIO[41]\"]\nset_property drive \"8\" [get_ports \"MIO[41]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"MIO[41]\"]\n#  SD 0 / clk / MIO[40]\nset_property iostandard \"LVCMOS18\" [get_ports \"MIO[40]\"]\nset_property PACKAGE_PIN \"D14\" [get_ports \"MIO[40]\"]\nset_property slew \"slow\" [get_ports \"MIO[40]\"]\nset_property drive \"8\" [get_ports \"MIO[40]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"MIO[40]\"]\n#  USB 0 / data[7] / MIO[39]\nset_property iostandard \"LVCMOS18\" [get_ports \"MIO[39]\"]\nset_property PACKAGE_PIN \"C18\" [get_ports \"MIO[39]\"]\nset_property slew \"slow\" [get_ports \"MIO[39]\"]\nset_property drive \"8\" [get_ports \"MIO[39]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"MIO[39]\"]\n#  USB 0 / data[6] / MIO[38]\nset_property iostandard \"LVCMOS18\" [get_ports \"MIO[38]\"]\nset_property PACKAGE_PIN \"E13\" [get_ports \"MIO[38]\"]\nset_property slew \"slow\" [get_ports \"MIO[38]\"]\nset_property drive \"8\" [get_ports \"MIO[38]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"MIO[38]\"]\n#  USB 0 / data[5] / MIO[37]\nset_property iostandard \"LVCMOS18\" [get_ports \"MIO[37]\"]\nset_property PACKAGE_PIN \"A10\" [get_ports \"MIO[37]\"]\nset_property slew \"slow\" [get_ports \"MIO[37]\"]\nset_property drive \"8\" [get_ports \"MIO[37]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"MIO[37]\"]\n#  USB 0 / clk / MIO[36]\nset_property iostandard \"LVCMOS18\" [get_ports \"MIO[36]\"]\nset_property PACKAGE_PIN \"A11\" [get_ports \"MIO[36]\"]\nset_property slew \"slow\" [get_ports \"MIO[36]\"]\nset_property drive \"8\" [get_ports \"MIO[36]\"]\nset_property PIO_DIRECTION \"INPUT\" [get_ports \"MIO[36]\"]\n#  USB 0 / data[3] / MIO[35]\nset_property iostandard \"LVCMOS18\" [get_ports \"MIO[35]\"]\nset_property PACKAGE_PIN \"F12\" [get_ports \"MIO[35]\"]\nset_property slew \"slow\" [get_ports \"MIO[35]\"]\nset_property drive \"8\" [get_ports \"MIO[35]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"MIO[35]\"]\n#  USB 0 / data[2] / MIO[34]\nset_property iostandard \"LVCMOS18\" [get_ports \"MIO[34]\"]\nset_property PACKAGE_PIN \"A12\" [get_ports \"MIO[34]\"]\nset_property slew \"slow\" [get_ports \"MIO[34]\"]\nset_property drive \"8\" [get_ports \"MIO[34]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"MIO[34]\"]\n#  USB 0 / data[1] / MIO[33]\nset_property iostandard \"LVCMOS18\" [get_ports \"MIO[33]\"]\nset_property PACKAGE_PIN \"D15\" [get_ports \"MIO[33]\"]\nset_property slew \"slow\" [get_ports \"MIO[33]\"]\nset_property drive \"8\" [get_ports \"MIO[33]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"MIO[33]\"]\n#  USB 0 / data[0] / MIO[32]\nset_property iostandard \"LVCMOS18\" [get_ports \"MIO[32]\"]\nset_property PACKAGE_PIN \"A14\" [get_ports \"MIO[32]\"]\nset_property slew \"slow\" [get_ports \"MIO[32]\"]\nset_property drive \"8\" [get_ports \"MIO[32]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"MIO[32]\"]\n#  USB 0 / nxt / MIO[31]\nset_property iostandard \"LVCMOS18\" [get_ports \"MIO[31]\"]\nset_property PACKAGE_PIN \"E16\" [get_ports \"MIO[31]\"]\nset_property slew \"slow\" [get_ports \"MIO[31]\"]\nset_property drive \"8\" [get_ports \"MIO[31]\"]\nset_property PIO_DIRECTION \"INPUT\" [get_ports \"MIO[31]\"]\n#  USB 0 / stp / MIO[30]\nset_property iostandard \"LVCMOS18\" [get_ports \"MIO[30]\"]\nset_property PACKAGE_PIN \"C15\" [get_ports \"MIO[30]\"]\nset_property slew \"slow\" [get_ports \"MIO[30]\"]\nset_property drive \"8\" [get_ports \"MIO[30]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"MIO[30]\"]\n#  USB 0 / dir / MIO[29]\nset_property iostandard \"LVCMOS18\" [get_ports \"MIO[29]\"]\nset_property PACKAGE_PIN \"C13\" [get_ports \"MIO[29]\"]\nset_property slew \"slow\" [get_ports \"MIO[29]\"]\nset_property drive \"8\" [get_ports \"MIO[29]\"]\nset_property PIO_DIRECTION \"INPUT\" [get_ports \"MIO[29]\"]\n#  USB 0 / data[4] / MIO[28]\nset_property iostandard \"LVCMOS18\" [get_ports \"MIO[28]\"]\nset_property PACKAGE_PIN \"C16\" [get_ports \"MIO[28]\"]\nset_property slew \"slow\" [get_ports \"MIO[28]\"]\nset_property drive \"8\" [get_ports \"MIO[28]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"MIO[28]\"]\n#  Enet 0 / rx_ctl / MIO[27]\nset_property iostandard \"LVCMOS18\" [get_ports \"MIO[27]\"]\nset_property PACKAGE_PIN \"D13\" [get_ports \"MIO[27]\"]\nset_property slew \"slow\" [get_ports \"MIO[27]\"]\nset_property drive \"8\" [get_ports \"MIO[27]\"]\nset_property PIO_DIRECTION \"INPUT\" [get_ports \"MIO[27]\"]\n#  Enet 0 / rxd[3] / MIO[26]\nset_property iostandard \"LVCMOS18\" [get_ports \"MIO[26]\"]\nset_property PACKAGE_PIN \"A15\" [get_ports \"MIO[26]\"]\nset_property slew \"slow\" [get_ports \"MIO[26]\"]\nset_property drive \"8\" [get_ports \"MIO[26]\"]\nset_property PIO_DIRECTION \"INPUT\" [get_ports \"MIO[26]\"]\n#  Enet 0 / rxd[2] / MIO[25]\nset_property iostandard \"LVCMOS18\" [get_ports \"MIO[25]\"]\nset_property PACKAGE_PIN \"F15\" [get_ports \"MIO[25]\"]\nset_property slew \"slow\" [get_ports \"MIO[25]\"]\nset_property drive \"8\" [get_ports \"MIO[25]\"]\nset_property PIO_DIRECTION \"INPUT\" [get_ports \"MIO[25]\"]\n#  Enet 0 / rxd[1] / MIO[24]\nset_property iostandard \"LVCMOS18\" [get_ports \"MIO[24]\"]\nset_property PACKAGE_PIN \"A16\" [get_ports \"MIO[24]\"]\nset_property slew \"slow\" [get_ports \"MIO[24]\"]\nset_property drive \"8\" [get_ports \"MIO[24]\"]\nset_property PIO_DIRECTION \"INPUT\" [get_ports \"MIO[24]\"]\n#  Enet 0 / rxd[0] / MIO[23]\nset_property iostandard \"LVCMOS18\" [get_ports \"MIO[23]\"]\nset_property PACKAGE_PIN \"D11\" [get_ports \"MIO[23]\"]\nset_property slew \"slow\" [get_ports \"MIO[23]\"]\nset_property drive \"8\" [get_ports \"MIO[23]\"]\nset_property PIO_DIRECTION \"INPUT\" [get_ports \"MIO[23]\"]\n#  Enet 0 / rx_clk / MIO[22]\nset_property iostandard \"LVCMOS18\" [get_ports \"MIO[22]\"]\nset_property PACKAGE_PIN \"B17\" [get_ports \"MIO[22]\"]\nset_property slew \"slow\" [get_ports \"MIO[22]\"]\nset_property drive \"8\" [get_ports \"MIO[22]\"]\nset_property PIO_DIRECTION \"INPUT\" [get_ports \"MIO[22]\"]\n#  Enet 0 / tx_ctl / MIO[21]\nset_property iostandard \"LVCMOS18\" [get_ports \"MIO[21]\"]\nset_property PACKAGE_PIN \"F14\" [get_ports \"MIO[21]\"]\nset_property slew \"slow\" [get_ports \"MIO[21]\"]\nset_property drive \"8\" [get_ports \"MIO[21]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"MIO[21]\"]\n#  Enet 0 / txd[3] / MIO[20]\nset_property iostandard \"LVCMOS18\" [get_ports \"MIO[20]\"]\nset_property PACKAGE_PIN \"A17\" [get_ports \"MIO[20]\"]\nset_property slew \"slow\" [get_ports \"MIO[20]\"]\nset_property drive \"8\" [get_ports \"MIO[20]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"MIO[20]\"]\n#  Enet 0 / txd[2] / MIO[19]\nset_property iostandard \"LVCMOS18\" [get_ports \"MIO[19]\"]\nset_property PACKAGE_PIN \"D10\" [get_ports \"MIO[19]\"]\nset_property slew \"slow\" [get_ports \"MIO[19]\"]\nset_property drive \"8\" [get_ports \"MIO[19]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"MIO[19]\"]\n#  Enet 0 / txd[1] / MIO[18]\nset_property iostandard \"LVCMOS18\" [get_ports \"MIO[18]\"]\nset_property PACKAGE_PIN \"B18\" [get_ports \"MIO[18]\"]\nset_property slew \"slow\" [get_ports \"MIO[18]\"]\nset_property drive \"8\" [get_ports \"MIO[18]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"MIO[18]\"]\n#  Enet 0 / txd[0] / MIO[17]\nset_property iostandard \"LVCMOS18\" [get_ports \"MIO[17]\"]\nset_property PACKAGE_PIN \"E14\" [get_ports \"MIO[17]\"]\nset_property slew \"slow\" [get_ports \"MIO[17]\"]\nset_property drive \"8\" [get_ports \"MIO[17]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"MIO[17]\"]\n#  Enet 0 / tx_clk / MIO[16]\nset_property iostandard \"LVCMOS18\" [get_ports \"MIO[16]\"]\nset_property PACKAGE_PIN \"A19\" [get_ports \"MIO[16]\"]\nset_property slew \"slow\" [get_ports \"MIO[16]\"]\nset_property drive \"8\" [get_ports \"MIO[16]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"MIO[16]\"]\n#  GPIO / gpio[15] / MIO[15]\nset_property iostandard \"LVCMOS33\" [get_ports \"MIO[15]\"]\nset_property PACKAGE_PIN \"C8\" [get_ports \"MIO[15]\"]\nset_property slew \"slow\" [get_ports \"MIO[15]\"]\nset_property drive \"8\" [get_ports \"MIO[15]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"MIO[15]\"]\n#  GPIO / gpio[14] / MIO[14]\nset_property iostandard \"LVCMOS33\" [get_ports \"MIO[14]\"]\nset_property PACKAGE_PIN \"C5\" [get_ports \"MIO[14]\"]\nset_property slew \"slow\" [get_ports \"MIO[14]\"]\nset_property drive \"8\" [get_ports \"MIO[14]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"MIO[14]\"]\n#  GPIO / gpio[13] / MIO[13]\nset_property iostandard \"LVCMOS33\" [get_ports \"MIO[13]\"]\nset_property PACKAGE_PIN \"E8\" [get_ports \"MIO[13]\"]\nset_property slew \"slow\" [get_ports \"MIO[13]\"]\nset_property drive \"8\" [get_ports \"MIO[13]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"MIO[13]\"]\n#  GPIO / gpio[12] / MIO[12]\nset_property iostandard \"LVCMOS33\" [get_ports \"MIO[12]\"]\nset_property PACKAGE_PIN \"D9\" [get_ports \"MIO[12]\"]\nset_property slew \"slow\" [get_ports \"MIO[12]\"]\nset_property drive \"8\" [get_ports \"MIO[12]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"MIO[12]\"]\n#  GPIO / gpio[11] / MIO[11]\nset_property iostandard \"LVCMOS33\" [get_ports \"MIO[11]\"]\nset_property PACKAGE_PIN \"C6\" [get_ports \"MIO[11]\"]\nset_property slew \"slow\" [get_ports \"MIO[11]\"]\nset_property drive \"8\" [get_ports \"MIO[11]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"MIO[11]\"]\n#  GPIO / gpio[10] / MIO[10]\nset_property iostandard \"LVCMOS33\" [get_ports \"MIO[10]\"]\nset_property PACKAGE_PIN \"E9\" [get_ports \"MIO[10]\"]\nset_property slew \"slow\" [get_ports \"MIO[10]\"]\nset_property drive \"8\" [get_ports \"MIO[10]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"MIO[10]\"]\n#  GPIO / gpio[9] / MIO[9]\nset_property iostandard \"LVCMOS33\" [get_ports \"MIO[9]\"]\nset_property PACKAGE_PIN \"B5\" [get_ports \"MIO[9]\"]\nset_property slew \"slow\" [get_ports \"MIO[9]\"]\nset_property drive \"8\" [get_ports \"MIO[9]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"MIO[9]\"]\n#  Quad SPI Flash / qspi_fbclk / MIO[8]\nset_property iostandard \"LVCMOS33\" [get_ports \"MIO[8]\"]\nset_property PACKAGE_PIN \"D5\" [get_ports \"MIO[8]\"]\nset_property slew \"slow\" [get_ports \"MIO[8]\"]\nset_property drive \"8\" [get_ports \"MIO[8]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"MIO[8]\"]\n#  USB Reset / reset / MIO[7]\nset_property iostandard \"LVCMOS33\" [get_ports \"MIO[7]\"]\nset_property PACKAGE_PIN \"D8\" [get_ports \"MIO[7]\"]\nset_property slew \"slow\" [get_ports \"MIO[7]\"]\nset_property drive \"8\" [get_ports \"MIO[7]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"MIO[7]\"]\n#  Quad SPI Flash / qspi0_sclk / MIO[6]\nset_property iostandard \"LVCMOS33\" [get_ports \"MIO[6]\"]\nset_property PACKAGE_PIN \"A5\" [get_ports \"MIO[6]\"]\nset_property slew \"slow\" [get_ports \"MIO[6]\"]\nset_property drive \"8\" [get_ports \"MIO[6]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"MIO[6]\"]\n#  Quad SPI Flash / qspi0_io[3] / MIO[5]\nset_property iostandard \"LVCMOS33\" [get_ports \"MIO[5]\"]\nset_property PACKAGE_PIN \"A6\" [get_ports \"MIO[5]\"]\nset_property slew \"slow\" [get_ports \"MIO[5]\"]\nset_property drive \"8\" [get_ports \"MIO[5]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"MIO[5]\"]\n#  Quad SPI Flash / qspi0_io[2] / MIO[4]\nset_property iostandard \"LVCMOS33\" [get_ports \"MIO[4]\"]\nset_property PACKAGE_PIN \"B7\" [get_ports \"MIO[4]\"]\nset_property slew \"slow\" [get_ports \"MIO[4]\"]\nset_property drive \"8\" [get_ports \"MIO[4]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"MIO[4]\"]\n#  Quad SPI Flash / qspi0_io[1] / MIO[3]\nset_property iostandard \"LVCMOS33\" [get_ports \"MIO[3]\"]\nset_property PACKAGE_PIN \"D6\" [get_ports \"MIO[3]\"]\nset_property slew \"slow\" [get_ports \"MIO[3]\"]\nset_property drive \"8\" [get_ports \"MIO[3]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"MIO[3]\"]\n#  Quad SPI Flash / qspi0_io[0] / MIO[2]\nset_property iostandard \"LVCMOS33\" [get_ports \"MIO[2]\"]\nset_property PACKAGE_PIN \"B8\" [get_ports \"MIO[2]\"]\nset_property slew \"slow\" [get_ports \"MIO[2]\"]\nset_property drive \"8\" [get_ports \"MIO[2]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"MIO[2]\"]\n#  Quad SPI Flash / qspi0_ss_b / MIO[1]\nset_property iostandard \"LVCMOS33\" [get_ports \"MIO[1]\"]\nset_property PACKAGE_PIN \"A7\" [get_ports \"MIO[1]\"]\nset_property slew \"slow\" [get_ports \"MIO[1]\"]\nset_property drive \"8\" [get_ports \"MIO[1]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"MIO[1]\"]\n#  GPIO / gpio[0] / MIO[0]\nset_property iostandard \"LVCMOS33\" [get_ports \"MIO[0]\"]\nset_property PACKAGE_PIN \"E6\" [get_ports \"MIO[0]\"]\nset_property slew \"slow\" [get_ports \"MIO[0]\"]\nset_property drive \"8\" [get_ports \"MIO[0]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"MIO[0]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"FIXED_IO_ddr_vrp\"]\nset_property PACKAGE_PIN \"H5\" [get_ports \"FIXED_IO_ddr_vrp\"]\nset_property slew \"FAST\" [get_ports \"FIXED_IO_ddr_vrp\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"FIXED_IO_ddr_vrp\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"FIXED_IO_ddr_vrn\"]\nset_property PACKAGE_PIN \"G5\" [get_ports \"FIXED_IO_ddr_vrn\"]\nset_property slew \"FAST\" [get_ports \"FIXED_IO_ddr_vrn\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"FIXED_IO_ddr_vrn\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_WEB\"]\nset_property PACKAGE_PIN \"M5\" [get_ports \"DDR_WEB\"]\nset_property slew \"SLOW\" [get_ports \"DDR_WEB\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_WEB\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_RAS_n\"]\nset_property PACKAGE_PIN \"P4\" [get_ports \"DDR_RAS_n\"]\nset_property slew \"SLOW\" [get_ports \"DDR_RAS_n\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_RAS_n\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_ODT\"]\nset_property PACKAGE_PIN \"N5\" [get_ports \"DDR_ODT\"]\nset_property slew \"SLOW\" [get_ports \"DDR_ODT\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_ODT\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_DRSTB\"]\nset_property PACKAGE_PIN \"B4\" [get_ports \"DDR_DRSTB\"]\nset_property slew \"FAST\" [get_ports \"DDR_DRSTB\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DRSTB\"]\nset_property iostandard \"DIFF_SSTL15_T_DCI\" [get_ports \"DDR_DQS_p[3]\"]\nset_property PACKAGE_PIN \"W5\" [get_ports \"DDR_DQS_p[3]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQS_p[3]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQS_p[3]\"]\nset_property iostandard \"DIFF_SSTL15_T_DCI\" [get_ports \"DDR_DQS_p[2]\"]\nset_property PACKAGE_PIN \"R2\" [get_ports \"DDR_DQS_p[2]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQS_p[2]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQS_p[2]\"]\nset_property iostandard \"DIFF_SSTL15_T_DCI\" [get_ports \"DDR_DQS_p[1]\"]\nset_property PACKAGE_PIN \"G2\" [get_ports \"DDR_DQS_p[1]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQS_p[1]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQS_p[1]\"]\nset_property iostandard \"DIFF_SSTL15_T_DCI\" [get_ports \"DDR_DQS_p[0]\"]\nset_property PACKAGE_PIN \"C2\" [get_ports \"DDR_DQS_p[0]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQS_p[0]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQS_p[0]\"]\nset_property iostandard \"DIFF_SSTL15_T_DCI\" [get_ports \"DDR_DQS_n[3]\"]\nset_property PACKAGE_PIN \"W4\" [get_ports \"DDR_DQS_n[3]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQS_n[3]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQS_n[3]\"]\nset_property iostandard \"DIFF_SSTL15_T_DCI\" [get_ports \"DDR_DQS_n[2]\"]\nset_property PACKAGE_PIN \"T2\" [get_ports \"DDR_DQS_n[2]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQS_n[2]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQS_n[2]\"]\nset_property iostandard \"DIFF_SSTL15_T_DCI\" [get_ports \"DDR_DQS_n[1]\"]\nset_property PACKAGE_PIN \"F2\" [get_ports \"DDR_DQS_n[1]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQS_n[1]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQS_n[1]\"]\nset_property iostandard \"DIFF_SSTL15_T_DCI\" [get_ports \"DDR_DQS_n[0]\"]\nset_property PACKAGE_PIN \"B2\" [get_ports \"DDR_DQS_n[0]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQS_n[0]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQS_n[0]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[9]\"]\nset_property PACKAGE_PIN \"E3\" [get_ports \"DDR_DQ[9]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[9]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[9]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[8]\"]\nset_property PACKAGE_PIN \"E2\" [get_ports \"DDR_DQ[8]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[8]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[8]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[7]\"]\nset_property PACKAGE_PIN \"E1\" [get_ports \"DDR_DQ[7]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[7]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[7]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[6]\"]\nset_property PACKAGE_PIN \"C1\" [get_ports \"DDR_DQ[6]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[6]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[6]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[5]\"]\nset_property PACKAGE_PIN \"D1\" [get_ports \"DDR_DQ[5]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[5]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[5]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[4]\"]\nset_property PACKAGE_PIN \"D3\" [get_ports \"DDR_DQ[4]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[4]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[4]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[3]\"]\nset_property PACKAGE_PIN \"A4\" [get_ports \"DDR_DQ[3]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[3]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[3]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[31]\"]\nset_property PACKAGE_PIN \"V3\" [get_ports \"DDR_DQ[31]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[31]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[31]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[30]\"]\nset_property PACKAGE_PIN \"V2\" [get_ports \"DDR_DQ[30]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[30]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[30]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[2]\"]\nset_property PACKAGE_PIN \"A2\" [get_ports \"DDR_DQ[2]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[2]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[2]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[29]\"]\nset_property PACKAGE_PIN \"W3\" [get_ports \"DDR_DQ[29]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[29]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[29]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[28]\"]\nset_property PACKAGE_PIN \"Y2\" [get_ports \"DDR_DQ[28]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[28]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[28]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[27]\"]\nset_property PACKAGE_PIN \"Y4\" [get_ports \"DDR_DQ[27]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[27]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[27]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[26]\"]\nset_property PACKAGE_PIN \"W1\" [get_ports \"DDR_DQ[26]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[26]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[26]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[25]\"]\nset_property PACKAGE_PIN \"Y3\" [get_ports \"DDR_DQ[25]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[25]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[25]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[24]\"]\nset_property PACKAGE_PIN \"V1\" [get_ports \"DDR_DQ[24]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[24]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[24]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[23]\"]\nset_property PACKAGE_PIN \"U3\" [get_ports \"DDR_DQ[23]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[23]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[23]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[22]\"]\nset_property PACKAGE_PIN \"U2\" [get_ports \"DDR_DQ[22]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[22]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[22]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[21]\"]\nset_property PACKAGE_PIN \"U4\" [get_ports \"DDR_DQ[21]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[21]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[21]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[20]\"]\nset_property PACKAGE_PIN \"T4\" [get_ports \"DDR_DQ[20]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[20]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[20]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[1]\"]\nset_property PACKAGE_PIN \"B3\" [get_ports \"DDR_DQ[1]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[1]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[1]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[19]\"]\nset_property PACKAGE_PIN \"R1\" [get_ports \"DDR_DQ[19]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[19]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[19]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[18]\"]\nset_property PACKAGE_PIN \"R3\" [get_ports \"DDR_DQ[18]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[18]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[18]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[17]\"]\nset_property PACKAGE_PIN \"P3\" [get_ports \"DDR_DQ[17]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[17]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[17]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[16]\"]\nset_property PACKAGE_PIN \"P1\" [get_ports \"DDR_DQ[16]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[16]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[16]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[15]\"]\nset_property PACKAGE_PIN \"J1\" [get_ports \"DDR_DQ[15]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[15]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[15]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[14]\"]\nset_property PACKAGE_PIN \"H1\" [get_ports \"DDR_DQ[14]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[14]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[14]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[13]\"]\nset_property PACKAGE_PIN \"H2\" [get_ports \"DDR_DQ[13]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[13]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[13]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[12]\"]\nset_property PACKAGE_PIN \"J3\" [get_ports \"DDR_DQ[12]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[12]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[12]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[11]\"]\nset_property PACKAGE_PIN \"H3\" [get_ports \"DDR_DQ[11]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[11]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[11]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[10]\"]\nset_property PACKAGE_PIN \"G3\" [get_ports \"DDR_DQ[10]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[10]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[10]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[0]\"]\nset_property PACKAGE_PIN \"C3\" [get_ports \"DDR_DQ[0]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[0]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[0]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DM[3]\"]\nset_property PACKAGE_PIN \"Y1\" [get_ports \"DDR_DM[3]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DM[3]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DM[3]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DM[2]\"]\nset_property PACKAGE_PIN \"T1\" [get_ports \"DDR_DM[2]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DM[2]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DM[2]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DM[1]\"]\nset_property PACKAGE_PIN \"F1\" [get_ports \"DDR_DM[1]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DM[1]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DM[1]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DM[0]\"]\nset_property PACKAGE_PIN \"A1\" [get_ports \"DDR_DM[0]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DM[0]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DM[0]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_CS_n\"]\nset_property PACKAGE_PIN \"N1\" [get_ports \"DDR_CS_n\"]\nset_property slew \"SLOW\" [get_ports \"DDR_CS_n\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_CS_n\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_CKE\"]\nset_property PACKAGE_PIN \"N3\" [get_ports \"DDR_CKE\"]\nset_property slew \"SLOW\" [get_ports \"DDR_CKE\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_CKE\"]\nset_property iostandard \"DIFF_SSTL15\" [get_ports \"DDR_Clk_p\"]\nset_property PACKAGE_PIN \"L2\" [get_ports \"DDR_Clk_p\"]\nset_property slew \"FAST\" [get_ports \"DDR_Clk_p\"]\nset_property PIO_DIRECTION \"INPUT\" [get_ports \"DDR_Clk_p\"]\nset_property iostandard \"DIFF_SSTL15\" [get_ports \"DDR_Clk_n\"]\nset_property PACKAGE_PIN \"M2\" [get_ports \"DDR_Clk_n\"]\nset_property slew \"FAST\" [get_ports \"DDR_Clk_n\"]\nset_property PIO_DIRECTION \"INPUT\" [get_ports \"DDR_Clk_n\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_CAS_n\"]\nset_property PACKAGE_PIN \"P5\" [get_ports \"DDR_CAS_n\"]\nset_property slew \"SLOW\" [get_ports \"DDR_CAS_n\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_CAS_n\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_BankAddr[2]\"]\nset_property PACKAGE_PIN \"J5\" [get_ports \"DDR_BankAddr[2]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_BankAddr[2]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_BankAddr[2]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_BankAddr[1]\"]\nset_property PACKAGE_PIN \"R4\" [get_ports \"DDR_BankAddr[1]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_BankAddr[1]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_BankAddr[1]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_BankAddr[0]\"]\nset_property PACKAGE_PIN \"L5\" [get_ports \"DDR_BankAddr[0]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_BankAddr[0]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_BankAddr[0]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_Addr[9]\"]\nset_property PACKAGE_PIN \"J4\" [get_ports \"DDR_Addr[9]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_Addr[9]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_Addr[9]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_Addr[8]\"]\nset_property PACKAGE_PIN \"K1\" [get_ports \"DDR_Addr[8]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_Addr[8]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_Addr[8]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_Addr[7]\"]\nset_property PACKAGE_PIN \"K4\" [get_ports \"DDR_Addr[7]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_Addr[7]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_Addr[7]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_Addr[6]\"]\nset_property PACKAGE_PIN \"L4\" [get_ports \"DDR_Addr[6]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_Addr[6]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_Addr[6]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_Addr[5]\"]\nset_property PACKAGE_PIN \"L1\" [get_ports \"DDR_Addr[5]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_Addr[5]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_Addr[5]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_Addr[4]\"]\nset_property PACKAGE_PIN \"M4\" [get_ports \"DDR_Addr[4]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_Addr[4]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_Addr[4]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_Addr[3]\"]\nset_property PACKAGE_PIN \"K3\" [get_ports \"DDR_Addr[3]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_Addr[3]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_Addr[3]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_Addr[2]\"]\nset_property PACKAGE_PIN \"M3\" [get_ports \"DDR_Addr[2]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_Addr[2]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_Addr[2]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_Addr[1]\"]\nset_property PACKAGE_PIN \"K2\" [get_ports \"DDR_Addr[1]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_Addr[1]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_Addr[1]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_Addr[14]\"]\nset_property PACKAGE_PIN \"F4\" [get_ports \"DDR_Addr[14]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_Addr[14]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_Addr[14]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_Addr[13]\"]\nset_property PACKAGE_PIN \"D4\" [get_ports \"DDR_Addr[13]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_Addr[13]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_Addr[13]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_Addr[12]\"]\nset_property PACKAGE_PIN \"E4\" [get_ports \"DDR_Addr[12]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_Addr[12]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_Addr[12]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_Addr[11]\"]\nset_property PACKAGE_PIN \"G4\" [get_ports \"DDR_Addr[11]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_Addr[11]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_Addr[11]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_Addr[10]\"]\nset_property PACKAGE_PIN \"F5\" [get_ports \"DDR_Addr[10]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_Addr[10]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_Addr[10]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_Addr[0]\"]\nset_property PACKAGE_PIN \"N2\" [get_ports \"DDR_Addr[0]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_Addr[0]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_Addr[0]\"]\nset_property iostandard \"LVCMOS33\" [get_ports \"PS_PORB\"]\nset_property PACKAGE_PIN \"C7\" [get_ports \"PS_PORB\"]\nset_property slew \"slow\" [get_ports \"PS_PORB\"]\nset_property drive \"8\" [get_ports \"PS_PORB\"]\nset_property iostandard \"LVCMOS33\" [get_ports \"PS_SRSTB\"]\nset_property PACKAGE_PIN \"B10\" [get_ports \"PS_SRSTB\"]\nset_property slew \"slow\" [get_ports \"PS_SRSTB\"]\nset_property drive \"8\" [get_ports \"PS_SRSTB\"]\nset_property iostandard \"LVCMOS33\" [get_ports \"PS_CLK\"]\nset_property PACKAGE_PIN \"E7\" [get_ports \"PS_CLK\"]\nset_property slew \"slow\" [get_ports \"PS_CLK\"]\nset_property drive \"8\" [get_ports \"PS_CLK\"]\n\n"
  },
  {
    "path": "constraints/xilinx/xc7z045ffg900.xdc",
    "content": "#created using vivado, see instructions in Readme.md\n#create clock manually commented out\n############################################################################\n##\n##  Xilinx, Inc. 2006            www.xilinx.com\n############################################################################\n##  File name :       ps7_constraints.xdc\n##\n##  Details :     Constraints file\n##                    FPGA family:       zynq\n##                    FPGA:              xc7z045ffg900-1\n##                    Device Size:        xc7z045\n##                    Package:            ffg900\n##                    Speedgrade:         -1\n##\n##\n############################################################################\n############################################################################\n############################################################################\n# Clock constraints                                                        #\n############################################################################\n## get the period from the clock generator cell\ncreate_clock -name clk_fpga_0 -period [get_property CLKIN1_PERIOD [get_cells -hierarchical ps7_clockGen_pll]] [get_pins \"*ps7_foo/FCLKCLK[0]\"]\nset_input_jitter clk_fpga_0 [expr 0.03 * [get_property CLKIN1_PERIOD [get_cells -hierarchical ps7_clockGen_pll]]]\nset_clock_groups -asynchronous -group {clk_fpga_0}\ncreate_clock -name clk_fpga_1 -period \"6\" [get_pins \"*ps7_foo/FCLKCLK[1]\"]\nset_input_jitter clk_fpga_1 0.6\nset_clock_groups -asynchronous -group {clk_fpga_1}\ncreate_clock -name clk_fpga_3 -period \"5\" [get_pins \"*ps7_foo/FCLKCLK[3]\"]\nset_input_jitter clk_fpga_3 0.6\nset_clock_groups -asynchronous -group {clk_fpga_3}\n\n\n############################################################################\n# I/O STANDARDS and Location Constraints                                   #\n############################################################################\n\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"FIXED_IO_ddr_vrp\"]\nset_property PACKAGE_PIN \"M21\" [get_ports \"FIXED_IO_ddr_vrp\"]\nset_property slew \"FAST\" [get_ports \"FIXED_IO_ddr_vrp\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"FIXED_IO_ddr_vrp\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"FIXED_IO_ddr_vrn\"]\nset_property PACKAGE_PIN \"N21\" [get_ports \"FIXED_IO_ddr_vrn\"]\nset_property slew \"FAST\" [get_ports \"FIXED_IO_ddr_vrn\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"FIXED_IO_ddr_vrn\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_WEB\"]\nset_property PACKAGE_PIN \"N23\" [get_ports \"DDR_WEB\"]\nset_property slew \"SLOW\" [get_ports \"DDR_WEB\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_WEB\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_RAS_n\"]\nset_property PACKAGE_PIN \"N24\" [get_ports \"DDR_RAS_n\"]\nset_property slew \"SLOW\" [get_ports \"DDR_RAS_n\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_RAS_n\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_ODT\"]\nset_property PACKAGE_PIN \"L23\" [get_ports \"DDR_ODT\"]\nset_property slew \"SLOW\" [get_ports \"DDR_ODT\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_ODT\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_DRSTB\"]\nset_property PACKAGE_PIN \"F25\" [get_ports \"DDR_DRSTB\"]\nset_property slew \"FAST\" [get_ports \"DDR_DRSTB\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DRSTB\"]\nset_property iostandard \"DIFF_SSTL15_T_DCI\" [get_ports \"DDR_DQS_p[3]\"]\nset_property PACKAGE_PIN \"L28\" [get_ports \"DDR_DQS_p[3]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQS_p[3]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQS_p[3]\"]\nset_property iostandard \"DIFF_SSTL15_T_DCI\" [get_ports \"DDR_DQS_p[2]\"]\nset_property PACKAGE_PIN \"G29\" [get_ports \"DDR_DQS_p[2]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQS_p[2]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQS_p[2]\"]\nset_property iostandard \"DIFF_SSTL15_T_DCI\" [get_ports \"DDR_DQS_p[1]\"]\nset_property PACKAGE_PIN \"C29\" [get_ports \"DDR_DQS_p[1]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQS_p[1]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQS_p[1]\"]\nset_property iostandard \"DIFF_SSTL15_T_DCI\" [get_ports \"DDR_DQS_p[0]\"]\nset_property PACKAGE_PIN \"C26\" [get_ports \"DDR_DQS_p[0]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQS_p[0]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQS_p[0]\"]\nset_property iostandard \"DIFF_SSTL15_T_DCI\" [get_ports \"DDR_DQS_n[3]\"]\nset_property PACKAGE_PIN \"L29\" [get_ports \"DDR_DQS_n[3]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQS_n[3]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQS_n[3]\"]\nset_property iostandard \"DIFF_SSTL15_T_DCI\" [get_ports \"DDR_DQS_n[2]\"]\nset_property PACKAGE_PIN \"F29\" [get_ports \"DDR_DQS_n[2]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQS_n[2]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQS_n[2]\"]\nset_property iostandard \"DIFF_SSTL15_T_DCI\" [get_ports \"DDR_DQS_n[1]\"]\nset_property PACKAGE_PIN \"B29\" [get_ports \"DDR_DQS_n[1]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQS_n[1]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQS_n[1]\"]\nset_property iostandard \"DIFF_SSTL15_T_DCI\" [get_ports \"DDR_DQS_n[0]\"]\nset_property PACKAGE_PIN \"B26\" [get_ports \"DDR_DQS_n[0]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQS_n[0]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQS_n[0]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[9]\"]\nset_property PACKAGE_PIN \"A27\" [get_ports \"DDR_DQ[9]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[9]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[9]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[8]\"]\nset_property PACKAGE_PIN \"A29\" [get_ports \"DDR_DQ[8]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[8]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[8]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[7]\"]\nset_property PACKAGE_PIN \"E27\" [get_ports \"DDR_DQ[7]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[7]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[7]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[6]\"]\nset_property PACKAGE_PIN \"D26\" [get_ports \"DDR_DQ[6]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[6]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[6]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[5]\"]\nset_property PACKAGE_PIN \"E26\" [get_ports \"DDR_DQ[5]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[5]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[5]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[4]\"]\nset_property PACKAGE_PIN \"B25\" [get_ports \"DDR_DQ[4]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[4]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[4]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[3]\"]\nset_property PACKAGE_PIN \"D25\" [get_ports \"DDR_DQ[3]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[3]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[3]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[31]\"]\nset_property PACKAGE_PIN \"M30\" [get_ports \"DDR_DQ[31]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[31]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[31]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[30]\"]\nset_property PACKAGE_PIN \"L30\" [get_ports \"DDR_DQ[30]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[30]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[30]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[2]\"]\nset_property PACKAGE_PIN \"B27\" [get_ports \"DDR_DQ[2]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[2]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[2]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[29]\"]\nset_property PACKAGE_PIN \"M29\" [get_ports \"DDR_DQ[29]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[29]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[29]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[28]\"]\nset_property PACKAGE_PIN \"K30\" [get_ports \"DDR_DQ[28]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[28]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[28]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[27]\"]\nset_property PACKAGE_PIN \"J28\" [get_ports \"DDR_DQ[27]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[27]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[27]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[26]\"]\nset_property PACKAGE_PIN \"J30\" [get_ports \"DDR_DQ[26]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[26]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[26]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[25]\"]\nset_property PACKAGE_PIN \"K27\" [get_ports \"DDR_DQ[25]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[25]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[25]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[24]\"]\nset_property PACKAGE_PIN \"J29\" [get_ports \"DDR_DQ[24]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[24]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[24]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[23]\"]\nset_property PACKAGE_PIN \"F30\" [get_ports \"DDR_DQ[23]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[23]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[23]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[22]\"]\nset_property PACKAGE_PIN \"G30\" [get_ports \"DDR_DQ[22]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[22]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[22]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[21]\"]\nset_property PACKAGE_PIN \"F28\" [get_ports \"DDR_DQ[21]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[21]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[21]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[20]\"]\nset_property PACKAGE_PIN \"E30\" [get_ports \"DDR_DQ[20]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[20]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[20]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[1]\"]\nset_property PACKAGE_PIN \"E25\" [get_ports \"DDR_DQ[1]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[1]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[1]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[19]\"]\nset_property PACKAGE_PIN \"E28\" [get_ports \"DDR_DQ[19]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[19]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[19]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[18]\"]\nset_property PACKAGE_PIN \"H28\" [get_ports \"DDR_DQ[18]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[18]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[18]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[17]\"]\nset_property PACKAGE_PIN \"G27\" [get_ports \"DDR_DQ[17]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[17]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[17]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[16]\"]\nset_property PACKAGE_PIN \"H27\" [get_ports \"DDR_DQ[16]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[16]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[16]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[15]\"]\nset_property PACKAGE_PIN \"D29\" [get_ports \"DDR_DQ[15]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[15]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[15]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[14]\"]\nset_property PACKAGE_PIN \"D28\" [get_ports \"DDR_DQ[14]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[14]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[14]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[13]\"]\nset_property PACKAGE_PIN \"D30\" [get_ports \"DDR_DQ[13]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[13]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[13]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[12]\"]\nset_property PACKAGE_PIN \"C28\" [get_ports \"DDR_DQ[12]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[12]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[12]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[11]\"]\nset_property PACKAGE_PIN \"A28\" [get_ports \"DDR_DQ[11]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[11]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[11]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[10]\"]\nset_property PACKAGE_PIN \"A30\" [get_ports \"DDR_DQ[10]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[10]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[10]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[0]\"]\nset_property PACKAGE_PIN \"A25\" [get_ports \"DDR_DQ[0]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[0]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[0]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DM[3]\"]\nset_property PACKAGE_PIN \"K28\" [get_ports \"DDR_DM[3]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DM[3]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DM[3]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DM[2]\"]\nset_property PACKAGE_PIN \"H29\" [get_ports \"DDR_DM[2]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DM[2]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DM[2]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DM[1]\"]\nset_property PACKAGE_PIN \"B30\" [get_ports \"DDR_DM[1]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DM[1]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DM[1]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DM[0]\"]\nset_property PACKAGE_PIN \"C27\" [get_ports \"DDR_DM[0]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DM[0]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DM[0]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_CS_n\"]\nset_property PACKAGE_PIN \"N22\" [get_ports \"DDR_CS_n\"]\nset_property slew \"SLOW\" [get_ports \"DDR_CS_n\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_CS_n\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_CKE\"]\nset_property PACKAGE_PIN \"M22\" [get_ports \"DDR_CKE\"]\nset_property slew \"SLOW\" [get_ports \"DDR_CKE\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_CKE\"]\nset_property iostandard \"DIFF_SSTL15\" [get_ports \"DDR_Clk_p\"]\nset_property PACKAGE_PIN \"K25\" [get_ports \"DDR_Clk_p\"]\nset_property slew \"FAST\" [get_ports \"DDR_Clk_p\"]\nset_property PIO_DIRECTION \"INPUT\" [get_ports \"DDR_Clk_p\"]\nset_property iostandard \"DIFF_SSTL15\" [get_ports \"DDR_Clk_n\"]\nset_property PACKAGE_PIN \"J25\" [get_ports \"DDR_Clk_n\"]\nset_property slew \"FAST\" [get_ports \"DDR_Clk_n\"]\nset_property PIO_DIRECTION \"INPUT\" [get_ports \"DDR_Clk_n\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_CAS_n\"]\nset_property PACKAGE_PIN \"M24\" [get_ports \"DDR_CAS_n\"]\nset_property slew \"SLOW\" [get_ports \"DDR_CAS_n\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_CAS_n\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_BankAddr[2]\"]\nset_property PACKAGE_PIN \"M25\" [get_ports \"DDR_BankAddr[2]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_BankAddr[2]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_BankAddr[2]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_BankAddr[1]\"]\nset_property PACKAGE_PIN \"M26\" [get_ports \"DDR_BankAddr[1]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_BankAddr[1]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_BankAddr[1]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_BankAddr[0]\"]\nset_property PACKAGE_PIN \"M27\" [get_ports \"DDR_BankAddr[0]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_BankAddr[0]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_BankAddr[0]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_Addr[9]\"]\nset_property PACKAGE_PIN \"J23\" [get_ports \"DDR_Addr[9]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_Addr[9]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_Addr[9]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_Addr[8]\"]\nset_property PACKAGE_PIN \"F27\" [get_ports \"DDR_Addr[8]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_Addr[8]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_Addr[8]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_Addr[7]\"]\nset_property PACKAGE_PIN \"K22\" [get_ports \"DDR_Addr[7]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_Addr[7]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_Addr[7]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_Addr[6]\"]\nset_property PACKAGE_PIN \"H26\" [get_ports \"DDR_Addr[6]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_Addr[6]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_Addr[6]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_Addr[5]\"]\nset_property PACKAGE_PIN \"G24\" [get_ports \"DDR_Addr[5]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_Addr[5]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_Addr[5]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_Addr[4]\"]\nset_property PACKAGE_PIN \"J26\" [get_ports \"DDR_Addr[4]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_Addr[4]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_Addr[4]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_Addr[3]\"]\nset_property PACKAGE_PIN \"G25\" [get_ports \"DDR_Addr[3]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_Addr[3]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_Addr[3]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_Addr[2]\"]\nset_property PACKAGE_PIN \"L27\" [get_ports \"DDR_Addr[2]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_Addr[2]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_Addr[2]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_Addr[1]\"]\nset_property PACKAGE_PIN \"K26\" [get_ports \"DDR_Addr[1]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_Addr[1]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_Addr[1]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_Addr[14]\"]\nset_property PACKAGE_PIN \"J24\" [get_ports \"DDR_Addr[14]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_Addr[14]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_Addr[14]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_Addr[13]\"]\nset_property PACKAGE_PIN \"H23\" [get_ports \"DDR_Addr[13]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_Addr[13]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_Addr[13]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_Addr[12]\"]\nset_property PACKAGE_PIN \"K23\" [get_ports \"DDR_Addr[12]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_Addr[12]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_Addr[12]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_Addr[11]\"]\nset_property PACKAGE_PIN \"H24\" [get_ports \"DDR_Addr[11]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_Addr[11]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_Addr[11]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_Addr[10]\"]\nset_property PACKAGE_PIN \"G26\" [get_ports \"DDR_Addr[10]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_Addr[10]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_Addr[10]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_Addr[0]\"]\nset_property PACKAGE_PIN \"L25\" [get_ports \"DDR_Addr[0]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_Addr[0]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_Addr[0]\"]\n\n"
  },
  {
    "path": "constraints/xilinx/xc7z100ffg900.xdc",
    "content": "#created using vivado see readme.md\n# create_clock manually commented out\n############################################################################\n##\n##  Xilinx, Inc. 2006            www.xilinx.com\n############################################################################\n##  File name :       ps7_constraints.xdc\n##\n##  Details :     Constraints file\n##                    FPGA family:       zynq\n##                    FPGA:              xc7z100ffg900-1\n##                    Device Size:        xc7z100\n##                    Package:            ffg900\n##                    Speedgrade:         -1\n##\n##\n############################################################################\n############################################################################\n############################################################################\n# Clock constraints                                                        #\n############################################################################\n## get the period from the clock generator cell\ncreate_clock -name clk_fpga_0 -period [get_property CLKIN1_PERIOD [get_cells -hierarchical ps7_clockGen_pll]] [get_pins \"*ps7_foo/FCLKCLK[0]\"]\nset_input_jitter clk_fpga_0 [expr 0.3 * [get_property CLKIN1_PERIOD [get_cells -hierarchical ps7_clockGen_pll]]]\nset_clock_groups -asynchronous -group {clk_fpga_0}\ncreate_clock -name clk_fpga_1 -period \"6\" [get_pins \"*ps7_foo/FCLKCLK[1]\"]\nset_input_jitter clk_fpga_1 0.6\nset_clock_groups -asynchronous -group {clk_fpga_1}\ncreate_clock -name clk_fpga_3 -period \"5\" [get_pins \"*ps7_foo/FCLKCLK[3]\"]\nset_input_jitter clk_fpga_3 0.6\nset_clock_groups -asynchronous -group {clk_fpga_3}\n\n\n############################################################################\n# I/O STANDARDS and Location Constraints                                   #\n############################################################################\n\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"FIXED_IO_ddr_vrp\"]\nset_property PACKAGE_PIN \"M21\" [get_ports \"FIXED_IO_ddr_vrp\"]\nset_property slew \"FAST\" [get_ports \"FIXED_IO_ddr_vrp\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"FIXED_IO_ddr_vrp\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"FIXED_IO_ddr_vrn\"]\nset_property PACKAGE_PIN \"N21\" [get_ports \"FIXED_IO_ddr_vrn\"]\nset_property slew \"FAST\" [get_ports \"FIXED_IO_ddr_vrn\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"FIXED_IO_ddr_vrn\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_WEB\"]\nset_property PACKAGE_PIN \"N23\" [get_ports \"DDR_WEB\"]\nset_property slew \"SLOW\" [get_ports \"DDR_WEB\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_WEB\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_RAS_n\"]\nset_property PACKAGE_PIN \"N24\" [get_ports \"DDR_RAS_n\"]\nset_property slew \"SLOW\" [get_ports \"DDR_RAS_n\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_RAS_n\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_ODT\"]\nset_property PACKAGE_PIN \"L23\" [get_ports \"DDR_ODT\"]\nset_property slew \"SLOW\" [get_ports \"DDR_ODT\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_ODT\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_DRSTB\"]\nset_property PACKAGE_PIN \"F25\" [get_ports \"DDR_DRSTB\"]\nset_property slew \"FAST\" [get_ports \"DDR_DRSTB\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DRSTB\"]\nset_property iostandard \"DIFF_SSTL15_T_DCI\" [get_ports \"DDR_DQS_p[3]\"]\nset_property PACKAGE_PIN \"L28\" [get_ports \"DDR_DQS_p[3]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQS_p[3]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQS_p[3]\"]\nset_property iostandard \"DIFF_SSTL15_T_DCI\" [get_ports \"DDR_DQS_p[2]\"]\nset_property PACKAGE_PIN \"G29\" [get_ports \"DDR_DQS_p[2]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQS_p[2]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQS_p[2]\"]\nset_property iostandard \"DIFF_SSTL15_T_DCI\" [get_ports \"DDR_DQS_p[1]\"]\nset_property PACKAGE_PIN \"C29\" [get_ports \"DDR_DQS_p[1]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQS_p[1]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQS_p[1]\"]\nset_property iostandard \"DIFF_SSTL15_T_DCI\" [get_ports \"DDR_DQS_p[0]\"]\nset_property PACKAGE_PIN \"C26\" [get_ports \"DDR_DQS_p[0]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQS_p[0]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQS_p[0]\"]\nset_property iostandard \"DIFF_SSTL15_T_DCI\" [get_ports \"DDR_DQS_n[3]\"]\nset_property PACKAGE_PIN \"L29\" [get_ports \"DDR_DQS_n[3]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQS_n[3]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQS_n[3]\"]\nset_property iostandard \"DIFF_SSTL15_T_DCI\" [get_ports \"DDR_DQS_n[2]\"]\nset_property PACKAGE_PIN \"F29\" [get_ports \"DDR_DQS_n[2]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQS_n[2]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQS_n[2]\"]\nset_property iostandard \"DIFF_SSTL15_T_DCI\" [get_ports \"DDR_DQS_n[1]\"]\nset_property PACKAGE_PIN \"B29\" [get_ports \"DDR_DQS_n[1]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQS_n[1]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQS_n[1]\"]\nset_property iostandard \"DIFF_SSTL15_T_DCI\" [get_ports \"DDR_DQS_n[0]\"]\nset_property PACKAGE_PIN \"B26\" [get_ports \"DDR_DQS_n[0]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQS_n[0]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQS_n[0]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[9]\"]\nset_property PACKAGE_PIN \"A27\" [get_ports \"DDR_DQ[9]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[9]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[9]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[8]\"]\nset_property PACKAGE_PIN \"A29\" [get_ports \"DDR_DQ[8]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[8]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[8]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[7]\"]\nset_property PACKAGE_PIN \"E27\" [get_ports \"DDR_DQ[7]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[7]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[7]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[6]\"]\nset_property PACKAGE_PIN \"D26\" [get_ports \"DDR_DQ[6]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[6]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[6]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[5]\"]\nset_property PACKAGE_PIN \"E26\" [get_ports \"DDR_DQ[5]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[5]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[5]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[4]\"]\nset_property PACKAGE_PIN \"B25\" [get_ports \"DDR_DQ[4]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[4]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[4]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[3]\"]\nset_property PACKAGE_PIN \"D25\" [get_ports \"DDR_DQ[3]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[3]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[3]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[31]\"]\nset_property PACKAGE_PIN \"M30\" [get_ports \"DDR_DQ[31]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[31]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[31]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[30]\"]\nset_property PACKAGE_PIN \"L30\" [get_ports \"DDR_DQ[30]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[30]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[30]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[2]\"]\nset_property PACKAGE_PIN \"B27\" [get_ports \"DDR_DQ[2]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[2]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[2]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[29]\"]\nset_property PACKAGE_PIN \"M29\" [get_ports \"DDR_DQ[29]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[29]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[29]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[28]\"]\nset_property PACKAGE_PIN \"K30\" [get_ports \"DDR_DQ[28]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[28]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[28]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[27]\"]\nset_property PACKAGE_PIN \"J28\" [get_ports \"DDR_DQ[27]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[27]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[27]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[26]\"]\nset_property PACKAGE_PIN \"J30\" [get_ports \"DDR_DQ[26]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[26]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[26]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[25]\"]\nset_property PACKAGE_PIN \"K27\" [get_ports \"DDR_DQ[25]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[25]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[25]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[24]\"]\nset_property PACKAGE_PIN \"J29\" [get_ports \"DDR_DQ[24]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[24]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[24]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[23]\"]\nset_property PACKAGE_PIN \"F30\" [get_ports \"DDR_DQ[23]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[23]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[23]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[22]\"]\nset_property PACKAGE_PIN \"G30\" [get_ports \"DDR_DQ[22]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[22]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[22]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[21]\"]\nset_property PACKAGE_PIN \"F28\" [get_ports \"DDR_DQ[21]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[21]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[21]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[20]\"]\nset_property PACKAGE_PIN \"E30\" [get_ports \"DDR_DQ[20]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[20]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[20]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[1]\"]\nset_property PACKAGE_PIN \"E25\" [get_ports \"DDR_DQ[1]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[1]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[1]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[19]\"]\nset_property PACKAGE_PIN \"E28\" [get_ports \"DDR_DQ[19]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[19]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[19]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[18]\"]\nset_property PACKAGE_PIN \"H28\" [get_ports \"DDR_DQ[18]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[18]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[18]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[17]\"]\nset_property PACKAGE_PIN \"G27\" [get_ports \"DDR_DQ[17]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[17]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[17]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[16]\"]\nset_property PACKAGE_PIN \"H27\" [get_ports \"DDR_DQ[16]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[16]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[16]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[15]\"]\nset_property PACKAGE_PIN \"D29\" [get_ports \"DDR_DQ[15]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[15]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[15]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[14]\"]\nset_property PACKAGE_PIN \"D28\" [get_ports \"DDR_DQ[14]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[14]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[14]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[13]\"]\nset_property PACKAGE_PIN \"D30\" [get_ports \"DDR_DQ[13]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[13]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[13]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[12]\"]\nset_property PACKAGE_PIN \"C28\" [get_ports \"DDR_DQ[12]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[12]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[12]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[11]\"]\nset_property PACKAGE_PIN \"A28\" [get_ports \"DDR_DQ[11]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[11]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[11]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[10]\"]\nset_property PACKAGE_PIN \"A30\" [get_ports \"DDR_DQ[10]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[10]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[10]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[0]\"]\nset_property PACKAGE_PIN \"A25\" [get_ports \"DDR_DQ[0]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[0]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[0]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DM[3]\"]\nset_property PACKAGE_PIN \"K28\" [get_ports \"DDR_DM[3]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DM[3]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DM[3]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DM[2]\"]\nset_property PACKAGE_PIN \"H29\" [get_ports \"DDR_DM[2]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DM[2]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DM[2]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DM[1]\"]\nset_property PACKAGE_PIN \"B30\" [get_ports \"DDR_DM[1]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DM[1]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DM[1]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DM[0]\"]\nset_property PACKAGE_PIN \"C27\" [get_ports \"DDR_DM[0]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DM[0]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DM[0]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_CS_n\"]\nset_property PACKAGE_PIN \"N22\" [get_ports \"DDR_CS_n\"]\nset_property slew \"SLOW\" [get_ports \"DDR_CS_n\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_CS_n\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_CKE\"]\nset_property PACKAGE_PIN \"M22\" [get_ports \"DDR_CKE\"]\nset_property slew \"SLOW\" [get_ports \"DDR_CKE\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_CKE\"]\nset_property iostandard \"DIFF_SSTL15\" [get_ports \"DDR_Clk_p\"]\nset_property PACKAGE_PIN \"K25\" [get_ports \"DDR_Clk_p\"]\nset_property slew \"FAST\" [get_ports \"DDR_Clk_p\"]\nset_property PIO_DIRECTION \"INPUT\" [get_ports \"DDR_Clk_p\"]\nset_property iostandard \"DIFF_SSTL15\" [get_ports \"DDR_Clk_n\"]\nset_property PACKAGE_PIN \"J25\" [get_ports \"DDR_Clk_n\"]\nset_property slew \"FAST\" [get_ports \"DDR_Clk_n\"]\nset_property PIO_DIRECTION \"INPUT\" [get_ports \"DDR_Clk_n\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_CAS_n\"]\nset_property PACKAGE_PIN \"M24\" [get_ports \"DDR_CAS_n\"]\nset_property slew \"SLOW\" [get_ports \"DDR_CAS_n\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_CAS_n\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_BankAddr[2]\"]\nset_property PACKAGE_PIN \"M25\" [get_ports \"DDR_BankAddr[2]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_BankAddr[2]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_BankAddr[2]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_BankAddr[1]\"]\nset_property PACKAGE_PIN \"M26\" [get_ports \"DDR_BankAddr[1]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_BankAddr[1]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_BankAddr[1]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_BankAddr[0]\"]\nset_property PACKAGE_PIN \"M27\" [get_ports \"DDR_BankAddr[0]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_BankAddr[0]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_BankAddr[0]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_Addr[9]\"]\nset_property PACKAGE_PIN \"J23\" [get_ports \"DDR_Addr[9]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_Addr[9]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_Addr[9]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_Addr[8]\"]\nset_property PACKAGE_PIN \"F27\" [get_ports \"DDR_Addr[8]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_Addr[8]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_Addr[8]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_Addr[7]\"]\nset_property PACKAGE_PIN \"K22\" [get_ports \"DDR_Addr[7]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_Addr[7]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_Addr[7]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_Addr[6]\"]\nset_property PACKAGE_PIN \"H26\" [get_ports \"DDR_Addr[6]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_Addr[6]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_Addr[6]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_Addr[5]\"]\nset_property PACKAGE_PIN \"G24\" [get_ports \"DDR_Addr[5]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_Addr[5]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_Addr[5]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_Addr[4]\"]\nset_property PACKAGE_PIN \"J26\" [get_ports \"DDR_Addr[4]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_Addr[4]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_Addr[4]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_Addr[3]\"]\nset_property PACKAGE_PIN \"G25\" [get_ports \"DDR_Addr[3]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_Addr[3]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_Addr[3]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_Addr[2]\"]\nset_property PACKAGE_PIN \"L27\" [get_ports \"DDR_Addr[2]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_Addr[2]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_Addr[2]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_Addr[1]\"]\nset_property PACKAGE_PIN \"K26\" [get_ports \"DDR_Addr[1]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_Addr[1]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_Addr[1]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_Addr[14]\"]\nset_property PACKAGE_PIN \"J24\" [get_ports \"DDR_Addr[14]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_Addr[14]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_Addr[14]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_Addr[13]\"]\nset_property PACKAGE_PIN \"H23\" [get_ports \"DDR_Addr[13]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_Addr[13]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_Addr[13]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_Addr[12]\"]\nset_property PACKAGE_PIN \"K23\" [get_ports \"DDR_Addr[12]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_Addr[12]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_Addr[12]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_Addr[11]\"]\nset_property PACKAGE_PIN \"H24\" [get_ports \"DDR_Addr[11]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_Addr[11]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_Addr[11]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_Addr[10]\"]\nset_property PACKAGE_PIN \"G26\" [get_ports \"DDR_Addr[10]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_Addr[10]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_Addr[10]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_Addr[0]\"]\nset_property PACKAGE_PIN \"L25\" [get_ports \"DDR_Addr[0]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_Addr[0]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_Addr[0]\"]\n\n"
  },
  {
    "path": "constraints/xilinx/zc706-axiddr3.prj",
    "content": "<?xml version='1.0' encoding='UTF-8'?>\n<!-- IMPORTANT: This is an internal file that has been generated by the MIG software. Any direct editing or changes made to this file may result in unpredictable behavior or data corruption. It is strongly advised that users do not edit the contents of this file. Re-run the MIG GUI with the required settings if any of the options provided below need to be altered. -->\n<Project NoOfControllers=\"1\" >\n    <ModuleName>axiddr3</ModuleName>\n    <dci_inouts_inputs>1</dci_inouts_inputs>\n    <dci_inputs>1</dci_inputs>\n    <Debug_En>OFF</Debug_En>\n    <DataDepth_En>1024</DataDepth_En>\n    <LowPower_En>ON</LowPower_En>\n    <XADC_En>Enabled</XADC_En>\n    <TargetFPGA>xc7z045-ffg900/-2</TargetFPGA>\n    <Version>2.3</Version>\n    <SystemClock>No Buffer</SystemClock>\n    <ReferenceClock>Use System Clock</ReferenceClock>\n    <SysResetPolarity>ACTIVE LOW</SysResetPolarity>\n    <BankSelectionFlag>FALSE</BankSelectionFlag>\n    <InternalVref>0</InternalVref>\n    <dci_hr_inouts_inputs>50 Ohms</dci_hr_inouts_inputs>\n    <dci_cascade>0</dci_cascade>\n    <Controller number=\"0\" >\n        <MemoryDevice>DDR3_SDRAM/SODIMMs/MT8JTF12864HZ-1G6</MemoryDevice>\n        <TimePeriod>1250</TimePeriod>\n        <VccAuxIO>2.0V</VccAuxIO>\n        <PHYRatio>4:1</PHYRatio>\n        <InputClkFreq>200</InputClkFreq>\n        <UIExtraClocks>0</UIExtraClocks>\n        <MMCM_VCO>800</MMCM_VCO>\n        <MMCMClkOut0> 1.000</MMCMClkOut0>\n        <MMCMClkOut1>1</MMCMClkOut1>\n        <MMCMClkOut2>1</MMCMClkOut2>\n        <MMCMClkOut3>1</MMCMClkOut3>\n        <MMCMClkOut4>1</MMCMClkOut4>\n        <DataWidth>64</DataWidth>\n        <DeepMemory>1</DeepMemory>\n        <DataMask>1</DataMask>\n        <ECC>Disabled</ECC>\n        <Ordering>Normal</Ordering>\n        <CustomPart>FALSE</CustomPart>\n        <NewPartName></NewPartName>\n        <RowAddress>14</RowAddress>\n        <ColAddress>10</ColAddress>\n        <BankAddress>3</BankAddress>\n        <MemoryVoltage>1.5V</MemoryVoltage>\n        <UserMemoryAddressMap>BANK_ROW_COLUMN</UserMemoryAddressMap>\n        <PinSelection>\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15\" PADName=\"E10\" SLEW=\"FAST\" name=\"ddr3_addr[0]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15\" PADName=\"D6\" SLEW=\"FAST\" name=\"ddr3_addr[10]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15\" PADName=\"B7\" SLEW=\"FAST\" name=\"ddr3_addr[11]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15\" PADName=\"H12\" SLEW=\"FAST\" name=\"ddr3_addr[12]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15\" PADName=\"A10\" SLEW=\"FAST\" name=\"ddr3_addr[13]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15\" PADName=\"B9\" SLEW=\"FAST\" name=\"ddr3_addr[1]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15\" PADName=\"E11\" SLEW=\"FAST\" name=\"ddr3_addr[2]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15\" PADName=\"A9\" SLEW=\"FAST\" name=\"ddr3_addr[3]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15\" PADName=\"D11\" SLEW=\"FAST\" name=\"ddr3_addr[4]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15\" PADName=\"B6\" SLEW=\"FAST\" name=\"ddr3_addr[5]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15\" PADName=\"F9\" SLEW=\"FAST\" name=\"ddr3_addr[6]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15\" PADName=\"E8\" SLEW=\"FAST\" name=\"ddr3_addr[7]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15\" PADName=\"B10\" SLEW=\"FAST\" name=\"ddr3_addr[8]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15\" PADName=\"J8\" SLEW=\"FAST\" name=\"ddr3_addr[9]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15\" PADName=\"F8\" SLEW=\"FAST\" name=\"ddr3_ba[0]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15\" PADName=\"H7\" SLEW=\"FAST\" name=\"ddr3_ba[1]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15\" PADName=\"A7\" SLEW=\"FAST\" name=\"ddr3_ba[2]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15\" PADName=\"E7\" SLEW=\"FAST\" name=\"ddr3_cas_n\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"DIFF_SSTL15\" PADName=\"F10\" SLEW=\"FAST\" name=\"ddr3_ck_n[0]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"DIFF_SSTL15\" PADName=\"G10\" SLEW=\"FAST\" name=\"ddr3_ck_p[0]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15\" PADName=\"D10\" SLEW=\"FAST\" name=\"ddr3_cke[0]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15\" PADName=\"J11\" SLEW=\"FAST\" name=\"ddr3_cs_n[0]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15\" PADName=\"J3\" SLEW=\"FAST\" name=\"ddr3_dm[0]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15\" PADName=\"F2\" SLEW=\"FAST\" name=\"ddr3_dm[1]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15\" PADName=\"E1\" SLEW=\"FAST\" name=\"ddr3_dm[2]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15\" PADName=\"C2\" SLEW=\"FAST\" name=\"ddr3_dm[3]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15\" PADName=\"L12\" SLEW=\"FAST\" name=\"ddr3_dm[4]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15\" PADName=\"G14\" SLEW=\"FAST\" name=\"ddr3_dm[5]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15\" PADName=\"C16\" SLEW=\"FAST\" name=\"ddr3_dm[6]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15\" PADName=\"C11\" SLEW=\"FAST\" name=\"ddr3_dm[7]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"L1\" SLEW=\"FAST\" name=\"ddr3_dq[0]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"H6\" SLEW=\"FAST\" name=\"ddr3_dq[10]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"H3\" SLEW=\"FAST\" name=\"ddr3_dq[11]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"G1\" SLEW=\"FAST\" name=\"ddr3_dq[12]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"H2\" SLEW=\"FAST\" name=\"ddr3_dq[13]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"G5\" SLEW=\"FAST\" name=\"ddr3_dq[14]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"G4\" SLEW=\"FAST\" name=\"ddr3_dq[15]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"E2\" SLEW=\"FAST\" name=\"ddr3_dq[16]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"E3\" SLEW=\"FAST\" name=\"ddr3_dq[17]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"D4\" SLEW=\"FAST\" name=\"ddr3_dq[18]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"E5\" SLEW=\"FAST\" name=\"ddr3_dq[19]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"L2\" SLEW=\"FAST\" name=\"ddr3_dq[1]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"F4\" SLEW=\"FAST\" name=\"ddr3_dq[20]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"F3\" SLEW=\"FAST\" name=\"ddr3_dq[21]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"D1\" SLEW=\"FAST\" name=\"ddr3_dq[22]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"D3\" SLEW=\"FAST\" name=\"ddr3_dq[23]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"A2\" SLEW=\"FAST\" name=\"ddr3_dq[24]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"B2\" SLEW=\"FAST\" name=\"ddr3_dq[25]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"B4\" SLEW=\"FAST\" name=\"ddr3_dq[26]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"B5\" SLEW=\"FAST\" name=\"ddr3_dq[27]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"A3\" SLEW=\"FAST\" name=\"ddr3_dq[28]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"B1\" SLEW=\"FAST\" name=\"ddr3_dq[29]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"K5\" SLEW=\"FAST\" name=\"ddr3_dq[2]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"C1\" SLEW=\"FAST\" name=\"ddr3_dq[30]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"C4\" SLEW=\"FAST\" name=\"ddr3_dq[31]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"K10\" SLEW=\"FAST\" name=\"ddr3_dq[32]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"L9\" SLEW=\"FAST\" name=\"ddr3_dq[33]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"K12\" SLEW=\"FAST\" name=\"ddr3_dq[34]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"J9\" SLEW=\"FAST\" name=\"ddr3_dq[35]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"K11\" SLEW=\"FAST\" name=\"ddr3_dq[36]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"L10\" SLEW=\"FAST\" name=\"ddr3_dq[37]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"J10\" SLEW=\"FAST\" name=\"ddr3_dq[38]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"L7\" SLEW=\"FAST\" name=\"ddr3_dq[39]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"J4\" SLEW=\"FAST\" name=\"ddr3_dq[3]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"F14\" SLEW=\"FAST\" name=\"ddr3_dq[40]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"F15\" SLEW=\"FAST\" name=\"ddr3_dq[41]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"F13\" SLEW=\"FAST\" name=\"ddr3_dq[42]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"G16\" SLEW=\"FAST\" name=\"ddr3_dq[43]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"G15\" SLEW=\"FAST\" name=\"ddr3_dq[44]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"E12\" SLEW=\"FAST\" name=\"ddr3_dq[45]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"D13\" SLEW=\"FAST\" name=\"ddr3_dq[46]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"E13\" SLEW=\"FAST\" name=\"ddr3_dq[47]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"D15\" SLEW=\"FAST\" name=\"ddr3_dq[48]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"E15\" SLEW=\"FAST\" name=\"ddr3_dq[49]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"K1\" SLEW=\"FAST\" name=\"ddr3_dq[4]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"D16\" SLEW=\"FAST\" name=\"ddr3_dq[50]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"E16\" SLEW=\"FAST\" name=\"ddr3_dq[51]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"C17\" SLEW=\"FAST\" name=\"ddr3_dq[52]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"B16\" SLEW=\"FAST\" name=\"ddr3_dq[53]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"D14\" SLEW=\"FAST\" name=\"ddr3_dq[54]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"B17\" SLEW=\"FAST\" name=\"ddr3_dq[55]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"B12\" SLEW=\"FAST\" name=\"ddr3_dq[56]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"C12\" SLEW=\"FAST\" name=\"ddr3_dq[57]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"A12\" SLEW=\"FAST\" name=\"ddr3_dq[58]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"A14\" SLEW=\"FAST\" name=\"ddr3_dq[59]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"L3\" SLEW=\"FAST\" name=\"ddr3_dq[5]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"A13\" SLEW=\"FAST\" name=\"ddr3_dq[60]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"B11\" SLEW=\"FAST\" name=\"ddr3_dq[61]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"C14\" SLEW=\"FAST\" name=\"ddr3_dq[62]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"B14\" SLEW=\"FAST\" name=\"ddr3_dq[63]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"J5\" SLEW=\"FAST\" name=\"ddr3_dq[6]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"K6\" SLEW=\"FAST\" name=\"ddr3_dq[7]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"G6\" SLEW=\"FAST\" name=\"ddr3_dq[8]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15_T_DCI\" PADName=\"H4\" SLEW=\"FAST\" name=\"ddr3_dq[9]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"DIFF_SSTL15_T_DCI\" PADName=\"K2\" SLEW=\"FAST\" name=\"ddr3_dqs_n[0]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"DIFF_SSTL15_T_DCI\" PADName=\"H1\" SLEW=\"FAST\" name=\"ddr3_dqs_n[1]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"DIFF_SSTL15_T_DCI\" PADName=\"D5\" SLEW=\"FAST\" name=\"ddr3_dqs_n[2]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"DIFF_SSTL15_T_DCI\" PADName=\"A4\" SLEW=\"FAST\" name=\"ddr3_dqs_n[3]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"DIFF_SSTL15_T_DCI\" PADName=\"K8\" SLEW=\"FAST\" name=\"ddr3_dqs_n[4]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"DIFF_SSTL15_T_DCI\" PADName=\"F12\" SLEW=\"FAST\" name=\"ddr3_dqs_n[5]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"DIFF_SSTL15_T_DCI\" PADName=\"E17\" SLEW=\"FAST\" name=\"ddr3_dqs_n[6]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"DIFF_SSTL15_T_DCI\" PADName=\"A15\" SLEW=\"FAST\" name=\"ddr3_dqs_n[7]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"DIFF_SSTL15_T_DCI\" PADName=\"K3\" SLEW=\"FAST\" name=\"ddr3_dqs_p[0]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"DIFF_SSTL15_T_DCI\" PADName=\"J1\" SLEW=\"FAST\" name=\"ddr3_dqs_p[1]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"DIFF_SSTL15_T_DCI\" PADName=\"E6\" SLEW=\"FAST\" name=\"ddr3_dqs_p[2]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"DIFF_SSTL15_T_DCI\" PADName=\"A5\" SLEW=\"FAST\" name=\"ddr3_dqs_p[3]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"DIFF_SSTL15_T_DCI\" PADName=\"L8\" SLEW=\"FAST\" name=\"ddr3_dqs_p[4]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"DIFF_SSTL15_T_DCI\" PADName=\"G12\" SLEW=\"FAST\" name=\"ddr3_dqs_p[5]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"DIFF_SSTL15_T_DCI\" PADName=\"F17\" SLEW=\"FAST\" name=\"ddr3_dqs_p[6]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"DIFF_SSTL15_T_DCI\" PADName=\"B15\" SLEW=\"FAST\" name=\"ddr3_dqs_p[7]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15\" PADName=\"G7\" SLEW=\"FAST\" name=\"ddr3_odt[0]\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15\" PADName=\"H11\" SLEW=\"FAST\" name=\"ddr3_ras_n\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"LVCMOS15\" PADName=\"G17\" SLEW=\"FAST\" name=\"ddr3_reset_n\" IN_TERM=\"\" />\n            <Pin VCCAUX_IO=\"HIGH\" IOSTANDARD=\"SSTL15\" PADName=\"F7\" SLEW=\"FAST\" name=\"ddr3_we_n\" IN_TERM=\"\" />\n        </PinSelection>\n        <System_Control>\n            <Pin PADName=\"No connect\" Bank=\"Select Bank\" name=\"sys_rst\" />\n            <Pin PADName=\"No connect\" Bank=\"Select Bank\" name=\"init_calib_complete\" />\n            <Pin PADName=\"No connect\" Bank=\"Select Bank\" name=\"tg_compare_error\" />\n        </System_Control>\n        <TimingParameters>\n            <Parameters twtr=\"7.5\" trrd=\"6\" trefi=\"7.8\" tfaw=\"30\" trtp=\"7.5\" tcke=\"5\" trfc=\"110\" trp=\"13.75\" tras=\"35\" trcd=\"13.75\" />\n        </TimingParameters>\n        <mrBurstLength name=\"Burst Length\" >8 - Fixed</mrBurstLength>\n        <mrBurstType name=\"Read Burst Type and Length\" >Sequential</mrBurstType>\n        <mrCasLatency name=\"CAS Latency\" >11</mrCasLatency>\n        <mrMode name=\"Mode\" >Normal</mrMode>\n        <mrDllReset name=\"DLL Reset\" >No</mrDllReset>\n        <mrPdMode name=\"DLL control for precharge PD\" >Slow Exit</mrPdMode>\n        <emrDllEnable name=\"DLL Enable\" >Enable</emrDllEnable>\n        <emrOutputDriveStrength name=\"Output Driver Impedance Control\" >RZQ/7</emrOutputDriveStrength>\n        <emrMirrorSelection name=\"Address Mirroring\" >Disable</emrMirrorSelection>\n        <emrCSSelection name=\"Controller Chip Select Pin\" >Enable</emrCSSelection>\n        <emrRTT name=\"RTT (nominal) - On Die Termination (ODT)\" >RZQ/4</emrRTT>\n        <emrPosted name=\"Additive Latency (AL)\" >0</emrPosted>\n        <emrOCD name=\"Write Leveling Enable\" >Disabled</emrOCD>\n        <emrDQS name=\"TDQS enable\" >Enabled</emrDQS>\n        <emrRDQS name=\"Qoff\" >Output Buffer Enabled</emrRDQS>\n        <mr2PartialArraySelfRefresh name=\"Partial-Array Self Refresh\" >Full Array</mr2PartialArraySelfRefresh>\n        <mr2CasWriteLatency name=\"CAS write latency\" >8</mr2CasWriteLatency>\n        <mr2AutoSelfRefresh name=\"Auto Self Refresh\" >Enabled</mr2AutoSelfRefresh>\n        <mr2SelfRefreshTempRange name=\"High Temparature Self Refresh Rate\" >Normal</mr2SelfRefreshTempRange>\n        <mr2RTTWR name=\"RTT_WR - Dynamic On Die Termination (ODT)\" >Dynamic ODT off</mr2RTTWR>\n        <PortInterface>AXI</PortInterface>\n        <AXIParameters>\n            <C0_C_RD_WR_ARB_ALGORITHM>RD_PRI_REG</C0_C_RD_WR_ARB_ALGORITHM>\n            <C0_S_AXI_ADDR_WIDTH>30</C0_S_AXI_ADDR_WIDTH>\n            <C0_S_AXI_DATA_WIDTH>512</C0_S_AXI_DATA_WIDTH>\n            <C0_S_AXI_ID_WIDTH>6</C0_S_AXI_ID_WIDTH>\n            <C0_S_AXI_SUPPORTS_NARROW_BURST>0</C0_S_AXI_SUPPORTS_NARROW_BURST>\n        </AXIParameters>\n    </Controller>\n\n</Project>\n"
  },
  {
    "path": "constraints/xilinx/zc706.xdc",
    "content": "set_property LOC H9  [get_ports { CLK_sys_clk_p }]\nset_property LOC G9  [get_ports { CLK_sys_clk_n }]\nset_property IOSTANDARD DIFF_SSTL15 [get_ports { CLK_sys_clk_* }]\ncreate_clock -name sys_clk -period 5 [get_ports CLK_sys_clk_p]\n\n# set_property iostandard \"LVCMOS15\" [get_ports \"GPIO_leds[0]\"]\n# set_property PACKAGE_PIN \"A17\" [get_ports \"GPIO_leds[0]\"]\n# set_property slew \"SLOW\" [get_ports \"GPIO_leds[0]\"]\n# set_property PIO_DIRECTION \"OUTPUT\" [get_ports \"GPIO_leds[0]\"]\n\n# set_property iostandard \"LVCMOS18\" [get_ports \"GPIO_leds[1]\"]\n# set_property PACKAGE_PIN \"W21\" [get_ports \"GPIO_leds[1]\"]\n# set_property slew \"SLOW\" [get_ports \"GPIO_leds[1]\"]\n# set_property PIO_DIRECTION \"OUTPUT\" [get_ports \"GPIO_leds[1]\"]\n\n# set_property iostandard \"LVCMOS15\" [get_ports \"GPIO_leds[2]\"]\n# set_property PACKAGE_PIN \"G2\" [get_ports \"GPIO_leds[2]\"]\n# set_property slew \"SLOW\" [get_ports \"GPIO_leds[2]\"]\n# set_property PIO_DIRECTION \"OUTPUT\" [get_ports \"GPIO_leds[2]\"]\n\n# set_property iostandard \"LVCMOS18\" [get_ports \"GPIO_leds[3]\"]\n# set_property PACKAGE_PIN \"Y21\" [get_ports \"GPIO_leds[3]\"]\n# set_property slew \"SLOW\" [get_ports \"GPIO_leds[3]\"]\n# set_property PIO_DIRECTION \"OUTPUT\" [get_ports \"GPIO_leds[3]\"]\n\n# set_property iostandard \"LVCMOS18\" [get_ports \"XADC_gpio[0]\"]\n# set_property PACKAGE_PIN \"H14\" [get_ports \"XADC_gpio[0]\"]\n# set_property slew \"SLOW\" [get_ports \"XADC_gpio[0]\"]\n# set_property PIO_DIRECTION \"OUTPUT\" [get_ports \"XADC_gpio[0]\"]\n\n# set_property iostandard \"LVCMOS18\" [get_ports \"XADC_gpio[1]\"]\n# set_property PACKAGE_PIN \"J15\" [get_ports \"XADC_gpio[1]\"]\n# set_property slew \"SLOW\" [get_ports \"XADC_gpio[1]\"]\n# set_property PIO_DIRECTION \"OUTPUT\" [get_ports \"XADC_gpio[1]\"]\n\n# set_property iostandard \"LVCMOS18\" [get_ports \"XADC_gpio[2]\"]\n# set_property PACKAGE_PIN \"J16\" [get_ports \"XADC_gpio[2]\"]\n# set_property slew \"SLOW\" [get_ports \"XADC_gpio[2]\"]\n# set_property PIO_DIRECTION \"OUTPUT\" [get_ports \"XADC_gpio[2]\"]\n\n# set_property iostandard \"LVCMOS18\" [get_ports \"XADC_gpio[3]\"]\n# set_property PACKAGE_PIN \"J14\" [get_ports \"XADC_gpio[3]\"]\n# set_property slew \"SLOW\" [get_ports \"XADC_gpio[3]\"]\n# set_property PIO_DIRECTION \"OUTPUT\" [get_ports \"XADC_gpio[3]\"]\n\n# PS_MIO50 set_property PACKAGE_PIN \"A19\" [get_ports \"I2C0_scl\"]\n# PS_MIO51 set_property PACKAGE_PIN \"F19\" [get_ports \"I2C0_sda\"]\n"
  },
  {
    "path": "constraints/xilinx/zc706_pl_ddr3_pins.xdc",
    "content": "######################################################################################################\n# PIN ASSIGNMENTS\n######################################################################################################\nset_property VCCAUX_IO HIGH [get_ports {ddr3_dq[0]}]\nset_property SLEW FAST [get_ports {ddr3_dq[0]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[0]}]\nset_property LOC L1 [get_ports {ddr3_dq[0]}]\n\nset_property VCCAUX_IO HIGH [get_ports {ddr3_dq[1]}]\nset_property SLEW FAST [get_ports {ddr3_dq[1]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[1]}]\nset_property LOC L2 [get_ports {ddr3_dq[1]}]\n\nset_property VCCAUX_IO HIGH [get_ports {ddr3_dq[2]}]\nset_property SLEW FAST [get_ports {ddr3_dq[2]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[2]}]\nset_property LOC K5 [get_ports {ddr3_dq[2]}]\n\nset_property VCCAUX_IO HIGH [get_ports {ddr3_dq[3]}]\nset_property SLEW FAST [get_ports {ddr3_dq[3]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[3]}]\nset_property LOC J4 [get_ports {ddr3_dq[3]}]\n\nset_property VCCAUX_IO HIGH [get_ports {ddr3_dq[4]}]\nset_property SLEW FAST [get_ports {ddr3_dq[4]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[4]}]\nset_property LOC K1 [get_ports {ddr3_dq[4]}]\n\nset_property VCCAUX_IO HIGH [get_ports {ddr3_dq[5]}]\nset_property SLEW FAST [get_ports {ddr3_dq[5]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[5]}]\nset_property LOC L3 [get_ports {ddr3_dq[5]}]\n\nset_property VCCAUX_IO HIGH [get_ports {ddr3_dq[6]}]\nset_property SLEW FAST [get_ports {ddr3_dq[6]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[6]}]\nset_property LOC J5 [get_ports {ddr3_dq[6]}]\n\nset_property VCCAUX_IO HIGH [get_ports {ddr3_dq[7]}]\nset_property SLEW FAST [get_ports {ddr3_dq[7]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[7]}]\nset_property LOC K6 [get_ports {ddr3_dq[7]}]\n\nset_property VCCAUX_IO HIGH [get_ports {ddr3_dq[8]}]\nset_property SLEW FAST [get_ports {ddr3_dq[8]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[8]}]\nset_property LOC G6 [get_ports {ddr3_dq[8]}]\n\nset_property VCCAUX_IO HIGH [get_ports {ddr3_dq[9]}]\nset_property SLEW FAST [get_ports {ddr3_dq[9]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[9]}]\nset_property LOC H4 [get_ports {ddr3_dq[9]}]\n\nset_property VCCAUX_IO HIGH [get_ports {ddr3_dq[10]}]\nset_property SLEW FAST [get_ports {ddr3_dq[10]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[10]}]\nset_property LOC H6 [get_ports {ddr3_dq[10]}]\n\nset_property VCCAUX_IO HIGH [get_ports {ddr3_dq[11]}]\nset_property SLEW FAST [get_ports {ddr3_dq[11]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[11]}]\nset_property LOC H3 [get_ports {ddr3_dq[11]}]\n\nset_property VCCAUX_IO HIGH [get_ports {ddr3_dq[12]}]\nset_property SLEW FAST [get_ports {ddr3_dq[12]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[12]}]\nset_property LOC G1 [get_ports {ddr3_dq[12]}]\n\nset_property VCCAUX_IO HIGH [get_ports {ddr3_dq[13]}]\nset_property SLEW FAST [get_ports {ddr3_dq[13]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[13]}]\nset_property LOC H2 [get_ports {ddr3_dq[13]}]\n\nset_property VCCAUX_IO HIGH [get_ports {ddr3_dq[14]}]\nset_property SLEW FAST [get_ports {ddr3_dq[14]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[14]}]\nset_property LOC G5 [get_ports {ddr3_dq[14]}]\n\nset_property VCCAUX_IO HIGH [get_ports {ddr3_dq[15]}]\nset_property SLEW FAST [get_ports {ddr3_dq[15]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[15]}]\nset_property LOC G4 [get_ports {ddr3_dq[15]}]\n\nset_property VCCAUX_IO HIGH [get_ports {ddr3_dq[16]}]\nset_property SLEW FAST [get_ports {ddr3_dq[16]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[16]}]\nset_property LOC E2 [get_ports {ddr3_dq[16]}]\n\nset_property VCCAUX_IO HIGH [get_ports {ddr3_dq[17]}]\nset_property SLEW FAST [get_ports {ddr3_dq[17]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[17]}]\nset_property LOC E3 [get_ports {ddr3_dq[17]}]\n\nset_property VCCAUX_IO HIGH [get_ports {ddr3_dq[18]}]\nset_property SLEW FAST [get_ports {ddr3_dq[18]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[18]}]\nset_property LOC D4 [get_ports {ddr3_dq[18]}]\n\nset_property VCCAUX_IO HIGH [get_ports {ddr3_dq[19]}]\nset_property SLEW FAST [get_ports {ddr3_dq[19]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[19]}]\nset_property LOC E5 [get_ports {ddr3_dq[19]}]\n\nset_property VCCAUX_IO HIGH [get_ports {ddr3_dq[20]}]\nset_property SLEW FAST [get_ports {ddr3_dq[20]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[20]}]\nset_property LOC F4 [get_ports {ddr3_dq[20]}]\n\nset_property VCCAUX_IO HIGH [get_ports {ddr3_dq[21]}]\nset_property SLEW FAST [get_ports {ddr3_dq[21]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[21]}]\nset_property LOC F3 [get_ports {ddr3_dq[21]}]\n\nset_property VCCAUX_IO HIGH [get_ports {ddr3_dq[22]}]\nset_property SLEW FAST [get_ports {ddr3_dq[22]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[22]}]\nset_property LOC D1 [get_ports {ddr3_dq[22]}]\n\nset_property VCCAUX_IO HIGH [get_ports {ddr3_dq[23]}]\nset_property SLEW FAST [get_ports {ddr3_dq[23]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[23]}]\nset_property LOC D3 [get_ports {ddr3_dq[23]}]\n\nset_property VCCAUX_IO HIGH [get_ports {ddr3_dq[24]}]\nset_property SLEW FAST [get_ports {ddr3_dq[24]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[24]}]\nset_property LOC A2 [get_ports {ddr3_dq[24]}]\n\nset_property VCCAUX_IO HIGH [get_ports {ddr3_dq[25]}]\nset_property SLEW FAST [get_ports {ddr3_dq[25]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[25]}]\nset_property LOC B2 [get_ports {ddr3_dq[25]}]\n\nset_property VCCAUX_IO HIGH [get_ports {ddr3_dq[26]}]\nset_property SLEW FAST [get_ports {ddr3_dq[26]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[26]}]\nset_property LOC B4 [get_ports {ddr3_dq[26]}]\n\nset_property VCCAUX_IO HIGH [get_ports {ddr3_dq[27]}]\nset_property SLEW FAST [get_ports {ddr3_dq[27]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[27]}]\nset_property LOC B5 [get_ports {ddr3_dq[27]}]\n\nset_property VCCAUX_IO HIGH [get_ports {ddr3_dq[28]}]\nset_property SLEW FAST [get_ports {ddr3_dq[28]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[28]}]\nset_property LOC A3 [get_ports {ddr3_dq[28]}]\n\nset_property VCCAUX_IO HIGH [get_ports {ddr3_dq[29]}]\nset_property SLEW FAST [get_ports {ddr3_dq[29]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[29]}]\nset_property LOC B1 [get_ports {ddr3_dq[29]}]\n\nset_property VCCAUX_IO HIGH [get_ports {ddr3_dq[30]}]\nset_property SLEW FAST [get_ports {ddr3_dq[30]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[30]}]\nset_property LOC C1 [get_ports {ddr3_dq[30]}]\n\nset_property VCCAUX_IO HIGH [get_ports {ddr3_dq[31]}]\nset_property SLEW FAST [get_ports {ddr3_dq[31]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[31]}]\nset_property LOC C4 [get_ports {ddr3_dq[31]}]\n\nset_property VCCAUX_IO HIGH [get_ports {ddr3_dq[32]}]\nset_property SLEW FAST [get_ports {ddr3_dq[32]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[32]}]\nset_property LOC K10 [get_ports {ddr3_dq[32]}]\n\nset_property VCCAUX_IO HIGH [get_ports {ddr3_dq[33]}]\nset_property SLEW FAST [get_ports {ddr3_dq[33]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[33]}]\nset_property LOC L9 [get_ports {ddr3_dq[33]}]\n\nset_property VCCAUX_IO HIGH [get_ports {ddr3_dq[34]}]\nset_property SLEW FAST [get_ports {ddr3_dq[34]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[34]}]\nset_property LOC K12 [get_ports {ddr3_dq[34]}]\n\nset_property VCCAUX_IO HIGH [get_ports {ddr3_dq[35]}]\nset_property SLEW FAST [get_ports {ddr3_dq[35]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[35]}]\nset_property LOC J9 [get_ports {ddr3_dq[35]}]\n\nset_property VCCAUX_IO HIGH [get_ports {ddr3_dq[36]}]\nset_property SLEW FAST [get_ports {ddr3_dq[36]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[36]}]\nset_property LOC K11 [get_ports {ddr3_dq[36]}]\n\nset_property VCCAUX_IO HIGH [get_ports {ddr3_dq[37]}]\nset_property SLEW FAST [get_ports {ddr3_dq[37]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[37]}]\nset_property LOC L10 [get_ports {ddr3_dq[37]}]\n\nset_property VCCAUX_IO HIGH [get_ports {ddr3_dq[38]}]\nset_property SLEW FAST [get_ports {ddr3_dq[38]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[38]}]\nset_property LOC J10 [get_ports {ddr3_dq[38]}]\n\nset_property VCCAUX_IO HIGH [get_ports {ddr3_dq[39]}]\nset_property SLEW FAST [get_ports {ddr3_dq[39]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[39]}]\nset_property LOC L7 [get_ports {ddr3_dq[39]}]\n\nset_property VCCAUX_IO HIGH [get_ports {ddr3_dq[40]}]\nset_property SLEW FAST [get_ports {ddr3_dq[40]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[40]}]\nset_property LOC F14 [get_ports {ddr3_dq[40]}]\n\nset_property VCCAUX_IO HIGH [get_ports {ddr3_dq[41]}]\nset_property SLEW FAST [get_ports {ddr3_dq[41]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[41]}]\nset_property LOC F15 [get_ports {ddr3_dq[41]}]\n\nset_property VCCAUX_IO HIGH [get_ports {ddr3_dq[42]}]\nset_property SLEW FAST [get_ports {ddr3_dq[42]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[42]}]\nset_property LOC F13 [get_ports {ddr3_dq[42]}]\n\nset_property VCCAUX_IO HIGH [get_ports {ddr3_dq[43]}]\nset_property SLEW FAST [get_ports {ddr3_dq[43]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[43]}]\nset_property LOC G16 [get_ports {ddr3_dq[43]}]\n\nset_property VCCAUX_IO HIGH [get_ports {ddr3_dq[44]}]\nset_property SLEW FAST [get_ports {ddr3_dq[44]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[44]}]\nset_property LOC G15 [get_ports {ddr3_dq[44]}]\n\nset_property VCCAUX_IO HIGH [get_ports {ddr3_dq[45]}]\nset_property SLEW FAST [get_ports {ddr3_dq[45]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[45]}]\nset_property LOC E12 [get_ports {ddr3_dq[45]}]\n\nset_property VCCAUX_IO HIGH [get_ports {ddr3_dq[46]}]\nset_property SLEW FAST [get_ports {ddr3_dq[46]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[46]}]\nset_property LOC D13 [get_ports {ddr3_dq[46]}]\n\nset_property VCCAUX_IO HIGH [get_ports {ddr3_dq[47]}]\nset_property SLEW FAST [get_ports {ddr3_dq[47]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[47]}]\nset_property LOC E13 [get_ports {ddr3_dq[47]}]\n\nset_property VCCAUX_IO HIGH [get_ports {ddr3_dq[48]}]\nset_property SLEW FAST [get_ports {ddr3_dq[48]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[48]}]\nset_property LOC D15 [get_ports {ddr3_dq[48]}]\n\nset_property VCCAUX_IO HIGH [get_ports {ddr3_dq[49]}]\nset_property SLEW FAST [get_ports {ddr3_dq[49]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[49]}]\nset_property LOC E15 [get_ports {ddr3_dq[49]}]\n\nset_property VCCAUX_IO HIGH [get_ports {ddr3_dq[50]}]\nset_property SLEW FAST [get_ports {ddr3_dq[50]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[50]}]\nset_property LOC D16 [get_ports {ddr3_dq[50]}]\n\nset_property VCCAUX_IO HIGH [get_ports {ddr3_dq[51]}]\nset_property SLEW FAST [get_ports {ddr3_dq[51]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[51]}]\nset_property LOC E16 [get_ports {ddr3_dq[51]}]\n\nset_property VCCAUX_IO HIGH [get_ports {ddr3_dq[52]}]\nset_property SLEW FAST [get_ports {ddr3_dq[52]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[52]}]\nset_property LOC C17 [get_ports {ddr3_dq[52]}]\n\nset_property VCCAUX_IO HIGH [get_ports {ddr3_dq[53]}]\nset_property SLEW FAST [get_ports {ddr3_dq[53]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[53]}]\nset_property LOC B16 [get_ports {ddr3_dq[53]}]\n\nset_property VCCAUX_IO HIGH [get_ports {ddr3_dq[54]}]\nset_property SLEW FAST [get_ports {ddr3_dq[54]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[54]}]\nset_property LOC D14 [get_ports {ddr3_dq[54]}]\n\nset_property VCCAUX_IO HIGH [get_ports {ddr3_dq[55]}]\nset_property SLEW FAST [get_ports {ddr3_dq[55]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[55]}]\nset_property LOC B17 [get_ports {ddr3_dq[55]}]\n\nset_property VCCAUX_IO HIGH [get_ports {ddr3_dq[56]}]\nset_property SLEW FAST [get_ports {ddr3_dq[56]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[56]}]\nset_property LOC B12 [get_ports {ddr3_dq[56]}]\n\nset_property VCCAUX_IO HIGH [get_ports {ddr3_dq[57]}]\nset_property SLEW FAST [get_ports {ddr3_dq[57]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[57]}]\nset_property LOC C12 [get_ports {ddr3_dq[57]}]\n\nset_property VCCAUX_IO HIGH [get_ports {ddr3_dq[58]}]\nset_property SLEW FAST [get_ports {ddr3_dq[58]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[58]}]\nset_property LOC A12 [get_ports {ddr3_dq[58]}]\n\nset_property VCCAUX_IO HIGH [get_ports {ddr3_dq[59]}]\nset_property SLEW FAST [get_ports {ddr3_dq[59]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[59]}]\nset_property LOC A14 [get_ports {ddr3_dq[59]}]\n\nset_property VCCAUX_IO HIGH [get_ports {ddr3_dq[60]}]\nset_property SLEW FAST [get_ports {ddr3_dq[60]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[60]}]\nset_property LOC A13 [get_ports {ddr3_dq[60]}]\n\nset_property VCCAUX_IO HIGH [get_ports {ddr3_dq[61]}]\nset_property SLEW FAST [get_ports {ddr3_dq[61]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[61]}]\nset_property LOC B11 [get_ports {ddr3_dq[61]}]\n\nset_property VCCAUX_IO HIGH [get_ports {ddr3_dq[62]}]\nset_property SLEW FAST [get_ports {ddr3_dq[62]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[62]}]\nset_property LOC C14 [get_ports {ddr3_dq[62]}]\n\nset_property VCCAUX_IO HIGH [get_ports {ddr3_dq[63]}]\nset_property SLEW FAST [get_ports {ddr3_dq[63]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[63]}]\nset_property LOC B14 [get_ports {ddr3_dq[63]}]\n\n#set_property VCCAUX_IO HIGH [get_ports {ddr3_addr[15]}]\n#set_property SLEW FAST [get_ports {ddr3_addr[15]}]\n#set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[15]}]\n#set_property LOC C6 [get_ports {ddr3_addr[15]}]\n\nset_property VCCAUX_IO HIGH [get_ports {ddr3_addr[14]}]\nset_property SLEW FAST [get_ports {ddr3_addr[14]}]\nset_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[14]}]\nset_property LOC G11 [get_ports {ddr3_addr[14]}]\n\nset_property VCCAUX_IO HIGH [get_ports {ddr3_addr[13]}]\nset_property SLEW FAST [get_ports {ddr3_addr[13]}]\nset_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[13]}]\nset_property LOC A10 [get_ports {ddr3_addr[13]}]\n\nset_property VCCAUX_IO HIGH [get_ports {ddr3_addr[12]}]\nset_property SLEW FAST [get_ports {ddr3_addr[12]}]\nset_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[12]}]\nset_property LOC H12 [get_ports {ddr3_addr[12]}]\n\nset_property VCCAUX_IO HIGH [get_ports {ddr3_addr[11]}]\nset_property SLEW FAST [get_ports {ddr3_addr[11]}]\nset_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[11]}]\nset_property LOC B7 [get_ports {ddr3_addr[11]}]\n\nset_property VCCAUX_IO HIGH [get_ports {ddr3_addr[10]}]\nset_property SLEW FAST [get_ports {ddr3_addr[10]}]\nset_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[10]}]\nset_property LOC D6 [get_ports {ddr3_addr[10]}]\n\nset_property VCCAUX_IO HIGH [get_ports {ddr3_addr[9]}]\nset_property SLEW FAST [get_ports {ddr3_addr[9]}]\nset_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[9]}]\nset_property LOC J8 [get_ports {ddr3_addr[9]}]\n\nset_property VCCAUX_IO HIGH [get_ports {ddr3_addr[8]}]\nset_property SLEW FAST [get_ports {ddr3_addr[8]}]\nset_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[8]}]\nset_property LOC B10 [get_ports {ddr3_addr[8]}]\n\nset_property VCCAUX_IO HIGH [get_ports {ddr3_addr[7]}]\nset_property SLEW FAST [get_ports {ddr3_addr[7]}]\nset_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[7]}]\nset_property LOC E8 [get_ports {ddr3_addr[7]}]\n\nset_property VCCAUX_IO HIGH [get_ports {ddr3_addr[6]}]\nset_property SLEW FAST [get_ports {ddr3_addr[6]}]\nset_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[6]}]\nset_property LOC F9 [get_ports {ddr3_addr[6]}]\n\nset_property VCCAUX_IO HIGH [get_ports {ddr3_addr[5]}]\nset_property SLEW FAST [get_ports {ddr3_addr[5]}]\nset_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[5]}]\nset_property LOC B6 [get_ports {ddr3_addr[5]}]\n\nset_property VCCAUX_IO HIGH [get_ports {ddr3_addr[4]}]\nset_property SLEW FAST [get_ports {ddr3_addr[4]}]\nset_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[4]}]\nset_property LOC D11 [get_ports {ddr3_addr[4]}]\n\nset_property VCCAUX_IO HIGH [get_ports {ddr3_addr[3]}]\nset_property SLEW FAST [get_ports {ddr3_addr[3]}]\nset_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[3]}]\nset_property LOC A9 [get_ports {ddr3_addr[3]}]\n\nset_property VCCAUX_IO HIGH [get_ports {ddr3_addr[2]}]\nset_property SLEW FAST [get_ports {ddr3_addr[2]}]\nset_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[2]}]\nset_property LOC E11 [get_ports {ddr3_addr[2]}]\n\nset_property VCCAUX_IO HIGH [get_ports {ddr3_addr[1]}]\nset_property SLEW FAST [get_ports {ddr3_addr[1]}]\nset_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[1]}]\nset_property LOC B9 [get_ports {ddr3_addr[1]}]\n\nset_property VCCAUX_IO HIGH [get_ports {ddr3_addr[0]}]\nset_property SLEW FAST [get_ports {ddr3_addr[0]}]\nset_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[0]}]\nset_property LOC E10 [get_ports {ddr3_addr[0]}]\n\nset_property VCCAUX_IO HIGH [get_ports {ddr3_ba[2]}]\nset_property SLEW FAST [get_ports {ddr3_ba[2]}]\nset_property IOSTANDARD SSTL15 [get_ports {ddr3_ba[2]}]\nset_property LOC A7 [get_ports {ddr3_ba[2]}]\n\nset_property VCCAUX_IO HIGH [get_ports {ddr3_ba[1]}]\nset_property SLEW FAST [get_ports {ddr3_ba[1]}]\nset_property IOSTANDARD SSTL15 [get_ports {ddr3_ba[1]}]\nset_property LOC H7 [get_ports {ddr3_ba[1]}]\n\nset_property VCCAUX_IO HIGH [get_ports {ddr3_ba[0]}]\nset_property SLEW FAST [get_ports {ddr3_ba[0]}]\nset_property IOSTANDARD SSTL15 [get_ports {ddr3_ba[0]}]\nset_property LOC F8 [get_ports {ddr3_ba[0]}]\n\nset_property VCCAUX_IO HIGH [get_ports {ddr3_ras_n}]\nset_property SLEW FAST [get_ports {ddr3_ras_n}]\nset_property IOSTANDARD SSTL15 [get_ports {ddr3_ras_n}]\nset_property LOC H11 [get_ports {ddr3_ras_n}]\n\nset_property VCCAUX_IO HIGH [get_ports {ddr3_cas_n}]\nset_property SLEW FAST [get_ports {ddr3_cas_n}]\nset_property IOSTANDARD SSTL15 [get_ports {ddr3_cas_n}]\nset_property LOC E7 [get_ports {ddr3_cas_n}]\n\nset_property VCCAUX_IO HIGH [get_ports {ddr3_we_n}]\nset_property SLEW FAST [get_ports {ddr3_we_n}]\nset_property IOSTANDARD SSTL15 [get_ports {ddr3_we_n}]\nset_property LOC F7 [get_ports {ddr3_we_n}]\n\nset_property VCCAUX_IO HIGH [get_ports {ddr3_reset_n}]\nset_property SLEW FAST [get_ports {ddr3_reset_n}]\nset_property IOSTANDARD LVCMOS15 [get_ports {ddr3_reset_n}]\nset_property LOC G17 [get_ports {ddr3_reset_n}]\n\nset_property VCCAUX_IO HIGH [get_ports {ddr3_cke[0]}]\nset_property SLEW FAST [get_ports {ddr3_cke[0]}]\nset_property IOSTANDARD SSTL15 [get_ports {ddr3_cke[0]}]\nset_property LOC D10 [get_ports {ddr3_cke[0]}]\n\nset_property VCCAUX_IO HIGH [get_ports {ddr3_odt[0]}]\nset_property SLEW FAST [get_ports {ddr3_odt[0]}]\nset_property IOSTANDARD SSTL15 [get_ports {ddr3_odt[0]}]\nset_property LOC G7 [get_ports {ddr3_odt[0]}]\n\nset_property VCCAUX_IO HIGH [get_ports {ddr3_cs_n[0]}]\nset_property SLEW FAST [get_ports {ddr3_cs_n[0]}]\nset_property IOSTANDARD SSTL15 [get_ports {ddr3_cs_n[0]}]\nset_property LOC J11 [get_ports {ddr3_cs_n[0]}]\n\nset_property VCCAUX_IO HIGH [get_ports {ddr3_dm[0]}]\nset_property SLEW FAST [get_ports {ddr3_dm[0]}]\nset_property IOSTANDARD SSTL15 [get_ports {ddr3_dm[0]}]\nset_property LOC J3 [get_ports {ddr3_dm[0]}]\n\nset_property VCCAUX_IO HIGH [get_ports {ddr3_dm[1]}]\nset_property SLEW FAST [get_ports {ddr3_dm[1]}]\nset_property IOSTANDARD SSTL15 [get_ports {ddr3_dm[1]}]\nset_property LOC F2 [get_ports {ddr3_dm[1]}]\n\nset_property VCCAUX_IO HIGH [get_ports {ddr3_dm[2]}]\nset_property SLEW FAST [get_ports {ddr3_dm[2]}]\nset_property IOSTANDARD SSTL15 [get_ports {ddr3_dm[2]}]\nset_property LOC E1 [get_ports {ddr3_dm[2]}]\n\nset_property VCCAUX_IO HIGH [get_ports {ddr3_dm[3]}]\nset_property SLEW FAST [get_ports {ddr3_dm[3]}]\nset_property IOSTANDARD SSTL15 [get_ports {ddr3_dm[3]}]\nset_property LOC C2 [get_ports {ddr3_dm[3]}]\n\nset_property VCCAUX_IO HIGH [get_ports {ddr3_dm[4]}]\nset_property SLEW FAST [get_ports {ddr3_dm[4]}]\nset_property IOSTANDARD SSTL15 [get_ports {ddr3_dm[4]}]\nset_property LOC L12 [get_ports {ddr3_dm[4]}]\n\nset_property VCCAUX_IO HIGH [get_ports {ddr3_dm[5]}]\nset_property SLEW FAST [get_ports {ddr3_dm[5]}]\nset_property IOSTANDARD SSTL15 [get_ports {ddr3_dm[5]}]\nset_property LOC G14 [get_ports {ddr3_dm[5]}]\n\nset_property VCCAUX_IO HIGH [get_ports {ddr3_dm[6]}]\nset_property SLEW FAST [get_ports {ddr3_dm[6]}]\nset_property IOSTANDARD SSTL15 [get_ports {ddr3_dm[6]}]\nset_property LOC C16 [get_ports {ddr3_dm[6]}]\n\nset_property VCCAUX_IO HIGH [get_ports {ddr3_dm[7]}]\nset_property SLEW FAST [get_ports {ddr3_dm[7]}]\nset_property IOSTANDARD SSTL15 [get_ports {ddr3_dm[7]}]\nset_property LOC C11 [get_ports {ddr3_dm[7]}]\n\nset_property VCCAUX_IO HIGH [get_ports {ddr3_dqs_p[0]}]\nset_property SLEW FAST [get_ports {ddr3_dqs_p[0]}]\nset_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports {ddr3_dqs_p[0]}]\nset_property LOC K3 [get_ports {ddr3_dqs_p[0]}]\n\nset_property VCCAUX_IO HIGH [get_ports {ddr3_dqs_n[0]}]\nset_property SLEW FAST [get_ports {ddr3_dqs_n[0]}]\nset_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports {ddr3_dqs_n[0]}]\nset_property LOC K2 [get_ports {ddr3_dqs_n[0]}]\n\nset_property VCCAUX_IO HIGH [get_ports {ddr3_dqs_p[1]}]\nset_property SLEW FAST [get_ports {ddr3_dqs_p[1]}]\nset_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports {ddr3_dqs_p[1]}]\nset_property LOC J1 [get_ports {ddr3_dqs_p[1]}]\n\nset_property VCCAUX_IO HIGH [get_ports {ddr3_dqs_n[1]}]\nset_property SLEW FAST [get_ports {ddr3_dqs_n[1]}]\nset_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports {ddr3_dqs_n[1]}]\nset_property LOC H1 [get_ports {ddr3_dqs_n[1]}]\n\nset_property VCCAUX_IO HIGH [get_ports {ddr3_dqs_p[2]}]\nset_property SLEW FAST [get_ports {ddr3_dqs_p[2]}]\nset_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports {ddr3_dqs_p[2]}]\nset_property LOC E6 [get_ports {ddr3_dqs_p[2]}]\n\nset_property VCCAUX_IO HIGH [get_ports {ddr3_dqs_n[2]}]\nset_property SLEW FAST [get_ports {ddr3_dqs_n[2]}]\nset_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports {ddr3_dqs_n[2]}]\nset_property LOC D5 [get_ports {ddr3_dqs_n[2]}]\n\nset_property VCCAUX_IO HIGH [get_ports {ddr3_dqs_p[3]}]\nset_property SLEW FAST [get_ports {ddr3_dqs_p[3]}]\nset_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports {ddr3_dqs_p[3]}]\nset_property LOC A5 [get_ports {ddr3_dqs_p[3]}]\n\nset_property VCCAUX_IO HIGH [get_ports {ddr3_dqs_n[3]}]\nset_property SLEW FAST [get_ports {ddr3_dqs_n[3]}]\nset_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports {ddr3_dqs_n[3]}]\nset_property LOC A4 [get_ports {ddr3_dqs_n[3]}]\n\nset_property VCCAUX_IO HIGH [get_ports {ddr3_dqs_p[4]}]\nset_property SLEW FAST [get_ports {ddr3_dqs_p[4]}]\nset_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports {ddr3_dqs_p[4]}]\nset_property LOC L8 [get_ports {ddr3_dqs_p[4]}]\n\nset_property VCCAUX_IO HIGH [get_ports {ddr3_dqs_n[4]}]\nset_property SLEW FAST [get_ports {ddr3_dqs_n[4]}]\nset_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports {ddr3_dqs_n[4]}]\nset_property LOC K8 [get_ports {ddr3_dqs_n[4]}]\n\nset_property VCCAUX_IO HIGH [get_ports {ddr3_dqs_p[5]}]\nset_property SLEW FAST [get_ports {ddr3_dqs_p[5]}]\nset_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports {ddr3_dqs_p[5]}]\nset_property LOC G12 [get_ports {ddr3_dqs_p[5]}]\n\nset_property VCCAUX_IO HIGH [get_ports {ddr3_dqs_n[5]}]\nset_property SLEW FAST [get_ports {ddr3_dqs_n[5]}]\nset_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports {ddr3_dqs_n[5]}]\nset_property LOC F12 [get_ports {ddr3_dqs_n[5]}]\n\nset_property VCCAUX_IO HIGH [get_ports {ddr3_dqs_p[6]}]\nset_property SLEW FAST [get_ports {ddr3_dqs_p[6]}]\nset_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports {ddr3_dqs_p[6]}]\nset_property LOC F17 [get_ports {ddr3_dqs_p[6]}]\n\nset_property VCCAUX_IO HIGH [get_ports {ddr3_dqs_n[6]}]\nset_property SLEW FAST [get_ports {ddr3_dqs_n[6]}]\nset_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports {ddr3_dqs_n[6]}]\nset_property LOC E17 [get_ports {ddr3_dqs_n[6]}]\n\nset_property VCCAUX_IO HIGH [get_ports {ddr3_dqs_p[7]}]\nset_property SLEW FAST [get_ports {ddr3_dqs_p[7]}]\nset_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports {ddr3_dqs_p[7]}]\nset_property LOC B15 [get_ports {ddr3_dqs_p[7]}]\n\nset_property VCCAUX_IO HIGH [get_ports {ddr3_dqs_n[7]}]\nset_property SLEW FAST [get_ports {ddr3_dqs_n[7]}]\nset_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports {ddr3_dqs_n[7]}]\nset_property LOC A15 [get_ports {ddr3_dqs_n[7]}]\n\nset_property VCCAUX_IO HIGH [get_ports {ddr3_ck_p[0]}]\nset_property SLEW FAST [get_ports {ddr3_ck_p[0]}]\nset_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_ck_p[0]}]\nset_property LOC G10 [get_ports {ddr3_ck_p[0]}]\n\nset_property VCCAUX_IO HIGH [get_ports {ddr3_ck_n[0]}]\nset_property SLEW FAST [get_ports {ddr3_ck_n[0]}]\nset_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_ck_n[0]}]\nset_property LOC F10 [get_ports {ddr3_ck_n[0]}]\n"
  },
  {
    "path": "constraints/xilinx/zc7z020clg400.xdc",
    "content": "# This file pulled from a Vidado manual run of a minimal design\n# using PS7.  It was named \n# project/project_srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0.xdc\n# clocking manually commented out\n############################################################################\n##\n##  Xilinx, Inc. 2006            www.xilinx.com\n############################################################################\n##  File name :       ps7_constraints.xdc\n##\n##  Details :     Constraints file\n##                    FPGA family:       zynq\n##                    FPGA:              xc7z020clg400-1\n##                    Device Size:        xc7z020\n##                    Package:            clg400\n##                    Speedgrade:         -1\n##\n##\n############################################################################\n############################################################################\n############################################################################\n# Clock constraints                                                        #\n############################################################################\n## get the period from the clock generator cell\ncreate_clock -name clk_fpga_0 -period [get_property CLKIN1_PERIOD [get_cells -hierarchical ps7_clockGen_pll]] [get_pins \"*ps7_foo/FCLKCLK[0]\"]\nset_input_jitter clk_fpga_0 [expr 0.3 * [get_property CLKIN1_PERIOD [get_cells -hierarchical ps7_clockGen_pll]]]\nset_clock_groups -asynchronous -group {clk_fpga_0}\ncreate_clock -name clk_fpga_1 -period \"6\" [get_pins \"*ps7_foo/FCLKCLK[1]\"]\nset_input_jitter clk_fpga_1 0.6\nset_clock_groups -asynchronous -group {clk_fpga_1}\ncreate_clock -name clk_fpga_3 -period \"5\" [get_pins \"*ps7_foo/FCLKCLK[3]\"]\nset_input_jitter clk_fpga_3 0.6\nset_clock_groups -asynchronous -group {clk_fpga_3}\ncreate_clock -name bscan_refclk -period 20 [get_pins -hier -filter {NAME=~\"*/bscan_mytck/O\"}]\n\n\n############################################################################\n# I/O STANDARDS and Location Constraints                                   #\n############################################################################\n\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"FIXED_IO_ddr_vrp\"]\nset_property PACKAGE_PIN \"H5\" [get_ports \"FIXED_IO_ddr_vrp\"]\nset_property slew \"FAST\" [get_ports \"FIXED_IO_ddr_vrp\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"FIXED_IO_ddr_vrp\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"FIXED_IO_ddr_vrn\"]\nset_property PACKAGE_PIN \"G5\" [get_ports \"FIXED_IO_ddr_vrn\"]\nset_property slew \"FAST\" [get_ports \"FIXED_IO_ddr_vrn\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"FIXED_IO_ddr_vrn\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_WEB\"]\nset_property PACKAGE_PIN \"M5\" [get_ports \"DDR_WEB\"]\nset_property slew \"SLOW\" [get_ports \"DDR_WEB\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_WEB\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_RAS_n\"]\nset_property PACKAGE_PIN \"P4\" [get_ports \"DDR_RAS_n\"]\nset_property slew \"SLOW\" [get_ports \"DDR_RAS_n\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_RAS_n\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_ODT\"]\nset_property PACKAGE_PIN \"N5\" [get_ports \"DDR_ODT\"]\nset_property slew \"SLOW\" [get_ports \"DDR_ODT\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_ODT\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_DRSTB\"]\nset_property PACKAGE_PIN \"B4\" [get_ports \"DDR_DRSTB\"]\nset_property slew \"FAST\" [get_ports \"DDR_DRSTB\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DRSTB\"]\nset_property iostandard \"DIFF_SSTL15_T_DCI\" [get_ports \"DDR_DQS_p[3]\"]\nset_property PACKAGE_PIN \"W5\" [get_ports \"DDR_DQS_p[3]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQS_p[3]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQS_p[3]\"]\nset_property iostandard \"DIFF_SSTL15_T_DCI\" [get_ports \"DDR_DQS_p[2]\"]\nset_property PACKAGE_PIN \"R2\" [get_ports \"DDR_DQS_p[2]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQS_p[2]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQS_p[2]\"]\nset_property iostandard \"DIFF_SSTL15_T_DCI\" [get_ports \"DDR_DQS_p[1]\"]\nset_property PACKAGE_PIN \"G2\" [get_ports \"DDR_DQS_p[1]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQS_p[1]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQS_p[1]\"]\nset_property iostandard \"DIFF_SSTL15_T_DCI\" [get_ports \"DDR_DQS_p[0]\"]\nset_property PACKAGE_PIN \"C2\" [get_ports \"DDR_DQS_p[0]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQS_p[0]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQS_p[0]\"]\nset_property iostandard \"DIFF_SSTL15_T_DCI\" [get_ports \"DDR_DQS_n[3]\"]\nset_property PACKAGE_PIN \"W4\" [get_ports \"DDR_DQS_n[3]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQS_n[3]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQS_n[3]\"]\nset_property iostandard \"DIFF_SSTL15_T_DCI\" [get_ports \"DDR_DQS_n[2]\"]\nset_property PACKAGE_PIN \"T2\" [get_ports \"DDR_DQS_n[2]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQS_n[2]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQS_n[2]\"]\nset_property iostandard \"DIFF_SSTL15_T_DCI\" [get_ports \"DDR_DQS_n[1]\"]\nset_property PACKAGE_PIN \"F2\" [get_ports \"DDR_DQS_n[1]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQS_n[1]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQS_n[1]\"]\nset_property iostandard \"DIFF_SSTL15_T_DCI\" [get_ports \"DDR_DQS_n[0]\"]\nset_property PACKAGE_PIN \"B2\" [get_ports \"DDR_DQS_n[0]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQS_n[0]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQS_n[0]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[9]\"]\nset_property PACKAGE_PIN \"E3\" [get_ports \"DDR_DQ[9]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[9]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[9]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[8]\"]\nset_property PACKAGE_PIN \"E2\" [get_ports \"DDR_DQ[8]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[8]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[8]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[7]\"]\nset_property PACKAGE_PIN \"E1\" [get_ports \"DDR_DQ[7]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[7]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[7]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[6]\"]\nset_property PACKAGE_PIN \"C1\" [get_ports \"DDR_DQ[6]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[6]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[6]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[5]\"]\nset_property PACKAGE_PIN \"D1\" [get_ports \"DDR_DQ[5]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[5]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[5]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[4]\"]\nset_property PACKAGE_PIN \"D3\" [get_ports \"DDR_DQ[4]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[4]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[4]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[3]\"]\nset_property PACKAGE_PIN \"A4\" [get_ports \"DDR_DQ[3]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[3]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[3]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[31]\"]\nset_property PACKAGE_PIN \"V3\" [get_ports \"DDR_DQ[31]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[31]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[31]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[30]\"]\nset_property PACKAGE_PIN \"V2\" [get_ports \"DDR_DQ[30]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[30]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[30]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[2]\"]\nset_property PACKAGE_PIN \"A2\" [get_ports \"DDR_DQ[2]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[2]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[2]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[29]\"]\nset_property PACKAGE_PIN \"W3\" [get_ports \"DDR_DQ[29]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[29]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[29]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[28]\"]\nset_property PACKAGE_PIN \"Y2\" [get_ports \"DDR_DQ[28]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[28]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[28]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[27]\"]\nset_property PACKAGE_PIN \"Y4\" [get_ports \"DDR_DQ[27]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[27]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[27]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[26]\"]\nset_property PACKAGE_PIN \"W1\" [get_ports \"DDR_DQ[26]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[26]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[26]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[25]\"]\nset_property PACKAGE_PIN \"Y3\" [get_ports \"DDR_DQ[25]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[25]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[25]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[24]\"]\nset_property PACKAGE_PIN \"V1\" [get_ports \"DDR_DQ[24]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[24]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[24]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[23]\"]\nset_property PACKAGE_PIN \"U3\" [get_ports \"DDR_DQ[23]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[23]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[23]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[22]\"]\nset_property PACKAGE_PIN \"U2\" [get_ports \"DDR_DQ[22]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[22]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[22]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[21]\"]\nset_property PACKAGE_PIN \"U4\" [get_ports \"DDR_DQ[21]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[21]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[21]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[20]\"]\nset_property PACKAGE_PIN \"T4\" [get_ports \"DDR_DQ[20]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[20]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[20]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[1]\"]\nset_property PACKAGE_PIN \"B3\" [get_ports \"DDR_DQ[1]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[1]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[1]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[19]\"]\nset_property PACKAGE_PIN \"R1\" [get_ports \"DDR_DQ[19]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[19]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[19]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[18]\"]\nset_property PACKAGE_PIN \"R3\" [get_ports \"DDR_DQ[18]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[18]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[18]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[17]\"]\nset_property PACKAGE_PIN \"P3\" [get_ports \"DDR_DQ[17]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[17]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[17]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[16]\"]\nset_property PACKAGE_PIN \"P1\" [get_ports \"DDR_DQ[16]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[16]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[16]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[15]\"]\nset_property PACKAGE_PIN \"J1\" [get_ports \"DDR_DQ[15]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[15]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[15]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[14]\"]\nset_property PACKAGE_PIN \"H1\" [get_ports \"DDR_DQ[14]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[14]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[14]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[13]\"]\nset_property PACKAGE_PIN \"H2\" [get_ports \"DDR_DQ[13]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[13]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[13]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[12]\"]\nset_property PACKAGE_PIN \"J3\" [get_ports \"DDR_DQ[12]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[12]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[12]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[11]\"]\nset_property PACKAGE_PIN \"H3\" [get_ports \"DDR_DQ[11]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[11]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[11]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[10]\"]\nset_property PACKAGE_PIN \"G3\" [get_ports \"DDR_DQ[10]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[10]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[10]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[0]\"]\nset_property PACKAGE_PIN \"C3\" [get_ports \"DDR_DQ[0]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[0]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[0]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DM[3]\"]\nset_property PACKAGE_PIN \"Y1\" [get_ports \"DDR_DM[3]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DM[3]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DM[3]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DM[2]\"]\nset_property PACKAGE_PIN \"T1\" [get_ports \"DDR_DM[2]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DM[2]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DM[2]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DM[1]\"]\nset_property PACKAGE_PIN \"F1\" [get_ports \"DDR_DM[1]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DM[1]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DM[1]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DM[0]\"]\nset_property PACKAGE_PIN \"A1\" [get_ports \"DDR_DM[0]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DM[0]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DM[0]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_CS_n\"]\nset_property PACKAGE_PIN \"N1\" [get_ports \"DDR_CS_n\"]\nset_property slew \"SLOW\" [get_ports \"DDR_CS_n\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_CS_n\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_CKE\"]\nset_property PACKAGE_PIN \"N3\" [get_ports \"DDR_CKE\"]\nset_property slew \"SLOW\" [get_ports \"DDR_CKE\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_CKE\"]\nset_property iostandard \"DIFF_SSTL15\" [get_ports \"DDR_Clk_p\"]\nset_property PACKAGE_PIN \"L2\" [get_ports \"DDR_Clk_p\"]\nset_property slew \"FAST\" [get_ports \"DDR_Clk_p\"]\nset_property PIO_DIRECTION \"INPUT\" [get_ports \"DDR_Clk_p\"]\nset_property iostandard \"DIFF_SSTL15\" [get_ports \"DDR_Clk_n\"]\nset_property PACKAGE_PIN \"M2\" [get_ports \"DDR_Clk_n\"]\nset_property slew \"FAST\" [get_ports \"DDR_Clk_n\"]\nset_property PIO_DIRECTION \"INPUT\" [get_ports \"DDR_Clk_n\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_CAS_n\"]\nset_property PACKAGE_PIN \"P5\" [get_ports \"DDR_CAS_n\"]\nset_property slew \"SLOW\" [get_ports \"DDR_CAS_n\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_CAS_n\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_BankAddr[2]\"]\nset_property PACKAGE_PIN \"J5\" [get_ports \"DDR_BankAddr[2]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_BankAddr[2]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_BankAddr[2]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_BankAddr[1]\"]\nset_property PACKAGE_PIN \"R4\" [get_ports \"DDR_BankAddr[1]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_BankAddr[1]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_BankAddr[1]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_BankAddr[0]\"]\nset_property PACKAGE_PIN \"L5\" [get_ports \"DDR_BankAddr[0]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_BankAddr[0]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_BankAddr[0]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_Addr[9]\"]\nset_property PACKAGE_PIN \"J4\" [get_ports \"DDR_Addr[9]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_Addr[9]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_Addr[9]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_Addr[8]\"]\nset_property PACKAGE_PIN \"K1\" [get_ports \"DDR_Addr[8]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_Addr[8]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_Addr[8]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_Addr[7]\"]\nset_property PACKAGE_PIN \"K4\" [get_ports \"DDR_Addr[7]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_Addr[7]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_Addr[7]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_Addr[6]\"]\nset_property PACKAGE_PIN \"L4\" [get_ports \"DDR_Addr[6]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_Addr[6]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_Addr[6]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_Addr[5]\"]\nset_property PACKAGE_PIN \"L1\" [get_ports \"DDR_Addr[5]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_Addr[5]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_Addr[5]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_Addr[4]\"]\nset_property PACKAGE_PIN \"M4\" [get_ports \"DDR_Addr[4]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_Addr[4]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_Addr[4]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_Addr[3]\"]\nset_property PACKAGE_PIN \"K3\" [get_ports \"DDR_Addr[3]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_Addr[3]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_Addr[3]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_Addr[2]\"]\nset_property PACKAGE_PIN \"M3\" [get_ports \"DDR_Addr[2]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_Addr[2]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_Addr[2]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_Addr[1]\"]\nset_property PACKAGE_PIN \"K2\" [get_ports \"DDR_Addr[1]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_Addr[1]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_Addr[1]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_Addr[14]\"]\nset_property PACKAGE_PIN \"F4\" [get_ports \"DDR_Addr[14]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_Addr[14]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_Addr[14]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_Addr[13]\"]\nset_property PACKAGE_PIN \"D4\" [get_ports \"DDR_Addr[13]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_Addr[13]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_Addr[13]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_Addr[12]\"]\nset_property PACKAGE_PIN \"E4\" [get_ports \"DDR_Addr[12]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_Addr[12]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_Addr[12]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_Addr[11]\"]\nset_property PACKAGE_PIN \"G4\" [get_ports \"DDR_Addr[11]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_Addr[11]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_Addr[11]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_Addr[10]\"]\nset_property PACKAGE_PIN \"F5\" [get_ports \"DDR_Addr[10]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_Addr[10]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_Addr[10]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_Addr[0]\"]\nset_property PACKAGE_PIN \"N2\" [get_ports \"DDR_Addr[0]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_Addr[0]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_Addr[0]\"]\n\n"
  },
  {
    "path": "constraints/xilinx/zc7z020clg484.xdc",
    "content": "# This file pulled from a Vidado manual run of a minimal design\n# using PS7.  It was named \n# project/project_srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0.xdc\n# clocking manually commented out here\n############################################################################\n##\n##  Xilinx, Inc. 2006            www.xilinx.com\n############################################################################\n##  File name :       ps7_constraints.xdc\n##\n##  Details :     Constraints file\n##                    FPGA family:       zynq\n##                    FPGA:              xc7z020clg484-1\n##                    Device Size:        xc7z020\n##                    Package:            clg484\n##                    Speedgrade:         -1\n##\n##\n############################################################################\n############################################################################\n############################################################################\n# Clock constraints                                                        #\n############################################################################\n## get the period from the clock generator cell\ncreate_clock -name clk_fpga_0 -period [get_property CLKIN1_PERIOD [get_cells -hierarchical ps7_clockGen_pll]] [get_pins \"*ps7_foo/FCLKCLK[0]\"]\nset_input_jitter clk_fpga_0 [expr 0.3 * [get_property CLKIN1_PERIOD [get_cells -hierarchical ps7_clockGen_pll]]]\nset_clock_groups -asynchronous -group {clk_fpga_0}\ncreate_clock -name clk_fpga_1 -period \"6\" [get_pins \"*ps7_foo/FCLKCLK[1]\"]\nset_input_jitter clk_fpga_1 0.6\nset_clock_groups -asynchronous -group {clk_fpga_1}\ncreate_clock -name clk_fpga_3 -period \"5\" [get_pins \"*ps7_foo/FCLKCLK[3]\"]\nset_input_jitter clk_fpga_3 0.6\nset_clock_groups -asynchronous -group {clk_fpga_3}\ncreate_clock -name bscan_refclk -period 20 [get_pins -hier -filter {NAME=~\"*/bscan_mytck/O\"}]\n\n\n############################################################################\n# I/O STANDARDS and Location Constraints                                   #\n############################################################################\n\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"FIXED_IO_ddr_vrp\"]\nset_property PACKAGE_PIN \"N7\" [get_ports \"FIXED_IO_ddr_vrp\"]\nset_property slew \"FAST\" [get_ports \"FIXED_IO_ddr_vrp\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"FIXED_IO_ddr_vrp\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"FIXED_IO_ddr_vrn\"]\nset_property PACKAGE_PIN \"M7\" [get_ports \"FIXED_IO_ddr_vrn\"]\nset_property slew \"FAST\" [get_ports \"FIXED_IO_ddr_vrn\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"FIXED_IO_ddr_vrn\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_WEB\"]\nset_property PACKAGE_PIN \"R4\" [get_ports \"DDR_WEB\"]\nset_property slew \"SLOW\" [get_ports \"DDR_WEB\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_WEB\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_RAS_n\"]\nset_property PACKAGE_PIN \"R5\" [get_ports \"DDR_RAS_n\"]\nset_property slew \"SLOW\" [get_ports \"DDR_RAS_n\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_RAS_n\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_ODT\"]\nset_property PACKAGE_PIN \"P5\" [get_ports \"DDR_ODT\"]\nset_property slew \"SLOW\" [get_ports \"DDR_ODT\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_ODT\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_DRSTB\"]\nset_property PACKAGE_PIN \"F3\" [get_ports \"DDR_DRSTB\"]\nset_property slew \"FAST\" [get_ports \"DDR_DRSTB\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DRSTB\"]\nset_property iostandard \"DIFF_SSTL15_T_DCI\" [get_ports \"DDR_DQS_p[3]\"]\nset_property PACKAGE_PIN \"V2\" [get_ports \"DDR_DQS_p[3]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQS_p[3]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQS_p[3]\"]\nset_property iostandard \"DIFF_SSTL15_T_DCI\" [get_ports \"DDR_DQS_p[2]\"]\nset_property PACKAGE_PIN \"N2\" [get_ports \"DDR_DQS_p[2]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQS_p[2]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQS_p[2]\"]\nset_property iostandard \"DIFF_SSTL15_T_DCI\" [get_ports \"DDR_DQS_p[1]\"]\nset_property PACKAGE_PIN \"H2\" [get_ports \"DDR_DQS_p[1]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQS_p[1]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQS_p[1]\"]\nset_property iostandard \"DIFF_SSTL15_T_DCI\" [get_ports \"DDR_DQS_p[0]\"]\nset_property PACKAGE_PIN \"C2\" [get_ports \"DDR_DQS_p[0]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQS_p[0]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQS_p[0]\"]\nset_property iostandard \"DIFF_SSTL15_T_DCI\" [get_ports \"DDR_DQS_n[3]\"]\nset_property PACKAGE_PIN \"W2\" [get_ports \"DDR_DQS_n[3]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQS_n[3]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQS_n[3]\"]\nset_property iostandard \"DIFF_SSTL15_T_DCI\" [get_ports \"DDR_DQS_n[2]\"]\nset_property PACKAGE_PIN \"P2\" [get_ports \"DDR_DQS_n[2]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQS_n[2]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQS_n[2]\"]\nset_property iostandard \"DIFF_SSTL15_T_DCI\" [get_ports \"DDR_DQS_n[1]\"]\nset_property PACKAGE_PIN \"J2\" [get_ports \"DDR_DQS_n[1]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQS_n[1]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQS_n[1]\"]\nset_property iostandard \"DIFF_SSTL15_T_DCI\" [get_ports \"DDR_DQS_n[0]\"]\nset_property PACKAGE_PIN \"D2\" [get_ports \"DDR_DQS_n[0]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQS_n[0]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQS_n[0]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[9]\"]\nset_property PACKAGE_PIN \"G1\" [get_ports \"DDR_DQ[9]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[9]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[9]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[8]\"]\nset_property PACKAGE_PIN \"G2\" [get_ports \"DDR_DQ[8]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[8]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[8]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[7]\"]\nset_property PACKAGE_PIN \"F1\" [get_ports \"DDR_DQ[7]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[7]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[7]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[6]\"]\nset_property PACKAGE_PIN \"F2\" [get_ports \"DDR_DQ[6]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[6]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[6]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[5]\"]\nset_property PACKAGE_PIN \"E1\" [get_ports \"DDR_DQ[5]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[5]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[5]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[4]\"]\nset_property PACKAGE_PIN \"E3\" [get_ports \"DDR_DQ[4]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[4]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[4]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[3]\"]\nset_property PACKAGE_PIN \"D3\" [get_ports \"DDR_DQ[3]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[3]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[3]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[31]\"]\nset_property PACKAGE_PIN \"Y1\" [get_ports \"DDR_DQ[31]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[31]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[31]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[30]\"]\nset_property PACKAGE_PIN \"W3\" [get_ports \"DDR_DQ[30]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[30]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[30]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[2]\"]\nset_property PACKAGE_PIN \"B2\" [get_ports \"DDR_DQ[2]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[2]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[2]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[29]\"]\nset_property PACKAGE_PIN \"Y3\" [get_ports \"DDR_DQ[29]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[29]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[29]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[28]\"]\nset_property PACKAGE_PIN \"W1\" [get_ports \"DDR_DQ[28]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[28]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[28]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[27]\"]\nset_property PACKAGE_PIN \"U2\" [get_ports \"DDR_DQ[27]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[27]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[27]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[26]\"]\nset_property PACKAGE_PIN \"AA1\" [get_ports \"DDR_DQ[26]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[26]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[26]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[25]\"]\nset_property PACKAGE_PIN \"U1\" [get_ports \"DDR_DQ[25]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[25]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[25]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[24]\"]\nset_property PACKAGE_PIN \"AA3\" [get_ports \"DDR_DQ[24]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[24]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[24]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[23]\"]\nset_property PACKAGE_PIN \"R1\" [get_ports \"DDR_DQ[23]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[23]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[23]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[22]\"]\nset_property PACKAGE_PIN \"M2\" [get_ports \"DDR_DQ[22]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[22]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[22]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[21]\"]\nset_property PACKAGE_PIN \"T2\" [get_ports \"DDR_DQ[21]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[21]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[21]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[20]\"]\nset_property PACKAGE_PIN \"R3\" [get_ports \"DDR_DQ[20]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[20]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[20]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[1]\"]\nset_property PACKAGE_PIN \"C3\" [get_ports \"DDR_DQ[1]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[1]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[1]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[19]\"]\nset_property PACKAGE_PIN \"T1\" [get_ports \"DDR_DQ[19]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[19]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[19]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[18]\"]\nset_property PACKAGE_PIN \"N3\" [get_ports \"DDR_DQ[18]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[18]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[18]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[17]\"]\nset_property PACKAGE_PIN \"T3\" [get_ports \"DDR_DQ[17]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[17]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[17]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[16]\"]\nset_property PACKAGE_PIN \"M1\" [get_ports \"DDR_DQ[16]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[16]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[16]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[15]\"]\nset_property PACKAGE_PIN \"K3\" [get_ports \"DDR_DQ[15]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[15]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[15]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[14]\"]\nset_property PACKAGE_PIN \"J1\" [get_ports \"DDR_DQ[14]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[14]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[14]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[13]\"]\nset_property PACKAGE_PIN \"K1\" [get_ports \"DDR_DQ[13]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[13]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[13]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[12]\"]\nset_property PACKAGE_PIN \"L3\" [get_ports \"DDR_DQ[12]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[12]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[12]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[11]\"]\nset_property PACKAGE_PIN \"L2\" [get_ports \"DDR_DQ[11]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[11]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[11]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[10]\"]\nset_property PACKAGE_PIN \"L1\" [get_ports \"DDR_DQ[10]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[10]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[10]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DQ[0]\"]\nset_property PACKAGE_PIN \"D1\" [get_ports \"DDR_DQ[0]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DQ[0]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DQ[0]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DM[3]\"]\nset_property PACKAGE_PIN \"AA2\" [get_ports \"DDR_DM[3]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DM[3]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DM[3]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DM[2]\"]\nset_property PACKAGE_PIN \"P1\" [get_ports \"DDR_DM[2]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DM[2]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DM[2]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DM[1]\"]\nset_property PACKAGE_PIN \"H3\" [get_ports \"DDR_DM[1]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DM[1]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DM[1]\"]\nset_property iostandard \"SSTL15_T_DCI\" [get_ports \"DDR_DM[0]\"]\nset_property PACKAGE_PIN \"B1\" [get_ports \"DDR_DM[0]\"]\nset_property slew \"FAST\" [get_ports \"DDR_DM[0]\"]\nset_property PIO_DIRECTION \"BIDIR\" [get_ports \"DDR_DM[0]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_CS_n\"]\nset_property PACKAGE_PIN \"P6\" [get_ports \"DDR_CS_n\"]\nset_property slew \"SLOW\" [get_ports \"DDR_CS_n\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_CS_n\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_CKE\"]\nset_property PACKAGE_PIN \"V3\" [get_ports \"DDR_CKE\"]\nset_property slew \"SLOW\" [get_ports \"DDR_CKE\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_CKE\"]\nset_property iostandard \"DIFF_SSTL15\" [get_ports \"DDR_Clk_p\"]\nset_property PACKAGE_PIN \"N4\" [get_ports \"DDR_Clk_p\"]\nset_property slew \"FAST\" [get_ports \"DDR_Clk_p\"]\nset_property PIO_DIRECTION \"INPUT\" [get_ports \"DDR_Clk_p\"]\nset_property iostandard \"DIFF_SSTL15\" [get_ports \"DDR_Clk_n\"]\nset_property PACKAGE_PIN \"N5\" [get_ports \"DDR_Clk_n\"]\nset_property slew \"FAST\" [get_ports \"DDR_Clk_n\"]\nset_property PIO_DIRECTION \"INPUT\" [get_ports \"DDR_Clk_n\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_CAS_n\"]\nset_property PACKAGE_PIN \"P3\" [get_ports \"DDR_CAS_n\"]\nset_property slew \"SLOW\" [get_ports \"DDR_CAS_n\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_CAS_n\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_BankAddr[2]\"]\nset_property PACKAGE_PIN \"M6\" [get_ports \"DDR_BankAddr[2]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_BankAddr[2]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_BankAddr[2]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_BankAddr[1]\"]\nset_property PACKAGE_PIN \"L6\" [get_ports \"DDR_BankAddr[1]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_BankAddr[1]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_BankAddr[1]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_BankAddr[0]\"]\nset_property PACKAGE_PIN \"L7\" [get_ports \"DDR_BankAddr[0]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_BankAddr[0]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_BankAddr[0]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_Addr[9]\"]\nset_property PACKAGE_PIN \"H5\" [get_ports \"DDR_Addr[9]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_Addr[9]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_Addr[9]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_Addr[8]\"]\nset_property PACKAGE_PIN \"J5\" [get_ports \"DDR_Addr[8]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_Addr[8]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_Addr[8]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_Addr[7]\"]\nset_property PACKAGE_PIN \"J6\" [get_ports \"DDR_Addr[7]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_Addr[7]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_Addr[7]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_Addr[6]\"]\nset_property PACKAGE_PIN \"J7\" [get_ports \"DDR_Addr[6]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_Addr[6]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_Addr[6]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_Addr[5]\"]\nset_property PACKAGE_PIN \"K5\" [get_ports \"DDR_Addr[5]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_Addr[5]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_Addr[5]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_Addr[4]\"]\nset_property PACKAGE_PIN \"K6\" [get_ports \"DDR_Addr[4]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_Addr[4]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_Addr[4]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_Addr[3]\"]\nset_property PACKAGE_PIN \"L4\" [get_ports \"DDR_Addr[3]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_Addr[3]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_Addr[3]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_Addr[2]\"]\nset_property PACKAGE_PIN \"K4\" [get_ports \"DDR_Addr[2]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_Addr[2]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_Addr[2]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_Addr[1]\"]\nset_property PACKAGE_PIN \"M5\" [get_ports \"DDR_Addr[1]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_Addr[1]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_Addr[1]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_Addr[14]\"]\nset_property PACKAGE_PIN \"G4\" [get_ports \"DDR_Addr[14]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_Addr[14]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_Addr[14]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_Addr[13]\"]\nset_property PACKAGE_PIN \"F4\" [get_ports \"DDR_Addr[13]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_Addr[13]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_Addr[13]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_Addr[12]\"]\nset_property PACKAGE_PIN \"H4\" [get_ports \"DDR_Addr[12]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_Addr[12]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_Addr[12]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_Addr[11]\"]\nset_property PACKAGE_PIN \"G5\" [get_ports \"DDR_Addr[11]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_Addr[11]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_Addr[11]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_Addr[10]\"]\nset_property PACKAGE_PIN \"J3\" [get_ports \"DDR_Addr[10]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_Addr[10]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_Addr[10]\"]\nset_property iostandard \"SSTL15\" [get_ports \"DDR_Addr[0]\"]\nset_property PACKAGE_PIN \"M4\" [get_ports \"DDR_Addr[0]\"]\nset_property slew \"SLOW\" [get_ports \"DDR_Addr[0]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"DDR_Addr[0]\"]\n\n"
  },
  {
    "path": "constraints/xilinx/zcu102.xdc",
    "content": "\n## TBD\n\n"
  },
  {
    "path": "constraints/xilinx/zcu111.xdc",
    "content": "\n## TBD\n\n"
  },
  {
    "path": "constraints/xilinx/zybo.xdc",
    "content": "set_property iostandard \"LVCMOS25\" [get_ports \"GPIO_leds[0]\"]\nset_property PACKAGE_PIN \"M14\" [get_ports \"GPIO_leds[0]\"]\nset_property slew \"SLOW\" [get_ports \"GPIO_leds[0]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"GPIO_leds[0]\"]\n\nset_property iostandard \"LVCMOS25\" [get_ports \"GPIO_leds[1]\"]\nset_property PACKAGE_PIN \"M15\" [get_ports \"GPIO_leds[1]\"]\nset_property slew \"SLOW\" [get_ports \"GPIO_leds[1]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"GPIO_leds[1]\"]\n\nset_property iostandard \"LVCMOS25\" [get_ports \"GPIO_leds[2]\"]\nset_property PACKAGE_PIN \"G14\" [get_ports \"GPIO_leds[2]\"]\nset_property slew \"SLOW\" [get_ports \"GPIO_leds[2]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"GPIO_leds[2]\"]\n\nset_property iostandard \"LVCMOS25\" [get_ports \"GPIO_leds[3]\"]\nset_property PACKAGE_PIN \"D18\" [get_ports \"GPIO_leds[3]\"]\nset_property slew \"SLOW\" [get_ports \"GPIO_leds[3]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"GPIO_leds[3]\"]\n"
  },
  {
    "path": "constraints/xilinx/zynq100.xdc",
    "content": "\nset_property iostandard \"LVCMOS18\" [get_ports \"GPIO_leds[0]\"]\nset_property PACKAGE_PIN \"A17\" [get_ports \"GPIO_leds[0]\"]\nset_property slew \"SLOW\" [get_ports \"GPIO_leds[0]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"GPIO_leds[0]\"]\n\nset_property iostandard \"LVCMOS18\" [get_ports \"GPIO_leds[1]\"]\nset_property PACKAGE_PIN \"W21\" [get_ports \"GPIO_leds[1]\"]\nset_property slew \"SLOW\" [get_ports \"GPIO_leds[1]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"GPIO_leds[1]\"]\n\nset_property iostandard \"LVCMOS18\" [get_ports \"GPIO_leds[2]\"]\nset_property PACKAGE_PIN \"G2\" [get_ports \"GPIO_leds[2]\"]\nset_property slew \"SLOW\" [get_ports \"GPIO_leds[2]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"GPIO_leds[2]\"]\n\nset_property iostandard \"LVCMOS18\" [get_ports \"GPIO_leds[3]\"]\nset_property PACKAGE_PIN \"Y21\" [get_ports \"GPIO_leds[3]\"]\nset_property slew \"SLOW\" [get_ports \"GPIO_leds[3]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"GPIO_leds[3]\"]\n\nset_property iostandard \"LVCMOS18\" [get_ports \"XADC_gpio[0]\"]\nset_property PACKAGE_PIN \"H14\" [get_ports \"XADC_gpio[0]\"]\nset_property slew \"SLOW\" [get_ports \"XADC_gpio[0]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"XADC_gpio[0]\"]\n\nset_property iostandard \"LVCMOS18\" [get_ports \"XADC_gpio[1]\"]\nset_property PACKAGE_PIN \"J15\" [get_ports \"XADC_gpio[1]\"]\nset_property slew \"SLOW\" [get_ports \"XADC_gpio[1]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"XADC_gpio[1]\"]\n\nset_property iostandard \"LVCMOS18\" [get_ports \"XADC_gpio[2]\"]\nset_property PACKAGE_PIN \"J16\" [get_ports \"XADC_gpio[2]\"]\nset_property slew \"SLOW\" [get_ports \"XADC_gpio[2]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"XADC_gpio[2]\"]\n\nset_property iostandard \"LVCMOS18\" [get_ports \"XADC_gpio[3]\"]\nset_property PACKAGE_PIN \"J14\" [get_ports \"XADC_gpio[3]\"]\nset_property slew \"SLOW\" [get_ports \"XADC_gpio[3]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"XADC_gpio[3]\"]\n\n# PS_MIO50 set_property PACKAGE_PIN \"A19\" [get_ports \"I2C0_scl\"]\n# PS_MIO51 set_property PACKAGE_PIN \"F19\" [get_ports \"I2C0_sda\"]\n"
  },
  {
    "path": "contrib/bluescope/Makefile",
    "content": "\nCONNECTALDIR?=../..\nINTERFACES = MemcpyRequest BlueScopeRequest MemcpyIndication BlueScopeIndication MemServerIndication\nBSVFILES = Memcpy.bsv $(CONNECTALDIR)/lib/bsv/BlueScope.bsv Top.bsv\nCPPFILES=testbluescope.cpp\n\ninclude $(CONNECTALDIR)/Makefile.connectal\n"
  },
  {
    "path": "contrib/bluescope/Memcpy.bsv",
    "content": "// Copyright (c) 2013 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\nimport Vector::*;\nimport FIFOF::*;\nimport GetPut::*;\nimport FIFO::*;\nimport Connectable::*;\nimport ClientServer::*;\nimport ConnectalMemory::*;\nimport ConnectalMemTypes::*;\nimport BlueScope::*;\nimport MemReadEngine::*;\nimport MemWriteEngine::*;\nimport Pipe::*;\n\ninterface MemcpyRequest;\n   method Action startCopy(Bit#(32) wrPointer, Bit#(32) rdPointer, Bit#(32) numWords, Bit#(32) burstLen);\nendinterface\n\ninterface MemcpyIndication;\n   method Action started();\n   method Action done();\nendinterface\n\ninterface Memcpy;\n   interface MemcpyRequest request;\n   interface MemReadClient#(64) readClient;\n   interface MemWriteClient#(64) writeClient;\nendinterface\n\nmodule mkMemcpyRequest#(MemcpyIndication indication,\n\t\t\tBlueScope#(64) bs)(Memcpy);\n   \n   MemReadEngine#(64,64,1,1)  re <- mkMemReadEngine;\n   MemWriteEngine#(64,64,1,1) we <- mkMemWriteEngine;\n\n   Reg#(Bit#(32))          iterCnt <- mkReg(0);\n   Reg#(Bit#(32))         numWords <- mkReg(0);\n   Reg#(SGLId)      rdPointer <- mkReg(0);\n   Reg#(SGLId)      wrPointer <- mkReg(0);\n   Reg#(Bit#(32))         burstLen <- mkReg(0);\n   FIFO#(void)       doneFifo <- mkFIFO;\n      \n   rule start(iterCnt > 0);\n      re.readServers[0].request.put(MemengineCmd{sglId:rdPointer, base:0, len:numWords*4, burstLen:truncate(burstLen*4)});\n      we.writeServers[0].request.put(MemengineCmd{sglId:wrPointer, base:0, len:numWords*4, burstLen:truncate(burstLen*4)});\n      iterCnt <= iterCnt-1;\n   endrule\n\n   rule finish;\n      doneFifo.deq;\n      let rv1 <- we.writeServers[0].done.get;\n      if(iterCnt==0) begin\n\t indication.done;\n      end\n   endrule\n   \n   rule xfer;\n      let v <- toGet(re.readServers[0].data).get;\n      we.writeServers[0].data.enq(v.data);\n      bs.dataIn(v.data,v.data);\n      if (v.last)\n         doneFifo.enq(?);\n   endrule\n   \n   interface MemcpyRequest request;\n      method Action startCopy(Bit#(32) wp, Bit#(32) rp, Bit#(32) nw, Bit#(32) bl);\n\t $display(\"startCopy wrPointer=%d rdPointer=%d numWords=%h burstLen=%d\", wp, rp, nw, bl);\n\t indication.started;\n\t // initialized\n\t wrPointer <= wp;\n\t rdPointer <= rp;\n\t numWords  <= nw;\n\t iterCnt   <= 1;\n\t burstLen  <= bl;\n      endmethod\n   endinterface\n   interface readClient = re.dmaClient;\n   interface writeClient = we.dmaClient;\nendmodule\n"
  },
  {
    "path": "contrib/bluescope/Top.bsv",
    "content": "/* Copyright (c) 2014 Quanta Research Cambridge, Inc\n *\n * Permission is hereby granted, free of charge, to any person obtaining a\n * copy of this software and associated documentation files (the \"Software\"),\n * to deal in the Software without restriction, including without limitation\n * the rights to use, copy, modify, merge, publish, distribute, sublicense,\n * and/or sell copies of the Software, and to permit persons to whom the\n * Software is furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n * DEALINGS IN THE SOFTWARE.\n */\nimport SpecialFIFOs::*;\nimport Vector::*;\nimport StmtFSM::*;\nimport FIFO::*;\nimport CtrlMux::*;\nimport Portal::*;\nimport HostInterface::*;\nimport BlueScope::*;\nimport ConnectalMemory::*;\nimport ConnectalMemTypes::*;\nimport MemServer::*;\nimport ConnectalMMU::*;\nimport MemcpyRequest::*;\nimport BlueScopeRequest::*;\nimport MemServerRequest::*;\nimport MMURequest::*;\nimport MemcpyIndication::*;\nimport BlueScopeIndication::*;\nimport MemServerIndication::*;\nimport MMUIndication::*;\nimport Memcpy::*;\n\n`define BluescopeSampleLength 8\n\ntypedef enum {IfcNames_MemcpyIndication, IfcNames_MemcpyRequest, IfcNames_HostMemServerIndication, IfcNames_HostMemServerRequest, IfcNames_HostMMURequest, IfcNames_HostMMUIndication, IfcNames_BluescopeIndication, IfcNames_BluescopeRequest} IfcNames deriving (Eq,Bits);\n\nmodule mkConnectalTop(StdConnectalDmaTop#(PhysAddrWidth));\n\n   BlueScopeIndicationProxy blueScopeIndicationProxy <- mkBlueScopeIndicationProxy(IfcNames_BluescopeIndication);\n   BlueScope#(64) bs <- mkBlueScope(`BluescopeSampleLength, blueScopeIndicationProxy.ifc);\n   BlueScopeRequestWrapper blueScopeRequestWrapper <- mkBlueScopeRequestWrapper(IfcNames_BluescopeRequest,bs.requestIfc);\n\n   MemcpyIndicationProxy memcpyIndicationProxy <- mkMemcpyIndicationProxy(IfcNames_MemcpyIndication);\n   Memcpy memcpy <- mkMemcpyRequest(memcpyIndicationProxy.ifc, bs);\n   MemcpyRequestWrapper memcpyRequestWrapper <- mkMemcpyRequestWrapper(IfcNames_MemcpyRequest,memcpy.request);\n\n   Vector#(1,  MemReadClient#(64))   readClients = newVector();\n   readClients[0] = memcpy.readClient;\n   Vector#(2, MemWriteClient#(64)) writeClients = newVector();\n   writeClients[0] = bs.writeClient;\n   writeClients[1] = memcpy.writeClient;\n   MMUIndicationProxy hostMMUIndicationProxy <- mkMMUIndicationProxy(IfcNames_HostMMUIndication);\n   MMU#(PhysAddrWidth) hostMMU <- mkMMU(0, True, hostMMUIndicationProxy.ifc);\n   MMURequestWrapper hostMMURequestWrapper <- mkMMURequestWrapper(IfcNames_HostMMURequest, hostMMU.request);\n\n   MemServerIndicationProxy hostMemServerIndicationProxy <- mkMemServerIndicationProxy(IfcNames_HostMemServerIndication);\n   MemServer#(PhysAddrWidth,64,1) dma <- mkMemServer(readClients, writeClients, cons(hostMMU,nil), hostMemServerIndicationProxy.ifc);\n   MemServerRequestWrapper hostMemServerRequestWrapper <- mkMemServerRequestWrapper(IfcNames_HostMemServerRequest, dma.request);\n\n   Vector#(8,StdPortal) portals;\n   portals[0] = memcpyRequestWrapper.portalIfc;\n   portals[1] = memcpyIndicationProxy.portalIfc; \n   portals[2] = blueScopeRequestWrapper.portalIfc;\n   portals[3] = blueScopeIndicationProxy.portalIfc; \n   portals[4] = hostMemServerRequestWrapper.portalIfc;\n   portals[5] = hostMemServerIndicationProxy.portalIfc; \n   portals[6] = hostMMURequestWrapper.portalIfc;\n   portals[7] = hostMMUIndicationProxy.portalIfc;\n   let ctrl_mux <- mkSlaveMux(portals);\n   \n   interface interrupt = getInterruptVector(portals);\n   interface slave = ctrl_mux;\n   interface masters = dma.masters;\nendmodule\n\n\n"
  },
  {
    "path": "contrib/bluescope/testbluescope.cpp",
    "content": "/* Copyright (c) 2013 Quanta Research Cambridge, Inc\n *\n * Permission is hereby granted, free of charge, to any person obtaining a\n * copy of this software and associated documentation files (the \"Software\"),\n * to deal in the Software without restriction, including without limitation\n * the rights to use, copy, modify, merge, publish, distribute, sublicense,\n * and/or sell copies of the Software, and to permit persons to whom the\n * Software is furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n * DEALINGS IN THE SOFTWARE.\n */\n#include <monkit.h>\n#include <semaphore.h>\n#include \"dmaManager.h\"\n#include \"BlueScopeIndication.h\"\n#include \"BlueScopeRequest.h\"\n#include \"MemcpyIndication.h\"\n#include \"MemcpyRequest.h\"\n\nsem_t done_sem;\nint srcAlloc;\nint dstAlloc;\nint bsAlloc;\nunsigned int *srcBuffer = 0;\nunsigned int *dstBuffer = 0;\nunsigned int *bsBuffer  = 0;\nint numWords = 128; //16 << 10;\nsize_t alloc_sz = numWords*sizeof(unsigned int);\nbool trigger_fired = false;\nbool finished = false;\nbool memcmp_fail = false;\nunsigned int memcmp_count = 0;\n\nstatic void memdump(void *p, int len, const char *title)\n{\nint i;\n\n    i = 0;\n    while (len > 0) {\n        if (!(i & 0xf)) {\n            if (i > 0)\n                fprintf(stderr, \"\\n\");\n            fprintf(stderr, \"%s: \",title);\n        }\n        fprintf(stderr, \"%02x \", *(unsigned char *)p);\n        p = (unsigned char *)p + 1;\n        i++;\n        len--;\n    }\n    fprintf(stderr, \"\\n\");\n}\n\nvoid exit_test()\n{\n  fprintf(stderr, \"testmemcpy finished count=%d memcmp_fail=%d, trigger_fired=%d\\n\", memcmp_count, memcmp_fail, trigger_fired);\n  exit(memcmp_fail || !trigger_fired);\n}\n\nclass MemcpyIndication : public MemcpyIndicationWrapper\n{\n\npublic:\n  MemcpyIndication(unsigned int id) : MemcpyIndicationWrapper(id){}\n\n\n  virtual void started(){\n    fprintf(stderr, \"started\");\n  }\n  virtual void done() {\n    sem_post(&done_sem);\n    finished = true;\n    unsigned int mcf = memcmp(srcBuffer, dstBuffer, numWords*sizeof(unsigned int));\n    memcmp_fail |= mcf;\n    fprintf(stderr, \"memcpy done:\\n\");\n    fprintf(stderr, \"(%d) memcmp src=%lx dst=%lx success=%s\\n\", memcmp_count, (long)srcBuffer, (long)dstBuffer, mcf == 0 ? \"pass\" : \"fail\");\n    memdump(srcBuffer, 128, \"src\");\n    memdump(dstBuffer, 128, \"dst\");\n    memdump(bsBuffer,  128, \"dbg\");\n  }\n};\n\nclass BlueScopeIndication : public BlueScopeIndicationWrapper\n{\npublic:\n  BlueScopeIndication(unsigned int id) : BlueScopeIndicationWrapper(id){}\n\n  virtual void done( ){\n    fprintf(stderr, \"BlueScope::done\\n\");\n  }\n  virtual void triggerFired( ){\n    fprintf(stderr, \"BlueScope::triggerFired\\n\");\n    trigger_fired = true;\n  }\n  virtual void reportStateDbg(uint64_t mask, uint64_t value){\n    fprintf(stderr, \"BlueScope::reportStateDbg mask=%\" PRIu64 \", value=%\" PRIu64 \"\\n\", mask, value);\n  }\n};\n\n// we can use the data synchronization barrier instead of flushing the \n// cache only because the ps7 is configured to run in buffered-write mode\n//\n// an opc2 of '4' and CRm of 'c10' encodes \"CP15DSB, Data Synchronization Barrier \n// operation\". this is a legal instruction to execute in non-privileged mode (mdk)\n//\n// #define DATA_SYNC_BARRIER   __asm __volatile( \"MCR p15, 0, %0, c7, c10, 4\" ::  \"r\" (0) );\n\nint main(int argc, const char **argv)\n{\n  MemcpyRequestProxy *device = 0;\n  BlueScopeRequestProxy *bluescope = 0;\n  MemcpyIndication *deviceIndication = 0;\n  BlueScopeIndication *bluescopeIndication = 0;\n\n  if(sem_init(&done_sem, 1, 0)){\n    fprintf(stderr, \"failed to init done_sem\\n\");\n    exit(1);\n  }\n\n  fprintf(stderr, \"%s %s\\n\", __DATE__, __TIME__);\n\n  device = new MemcpyRequestProxy(IfcNames_MemcpyRequest);\n  bluescope = new BlueScopeRequestProxy(IfcNames_BluescopeRequest);\n    DmaManager *dma = platformInit();\n  deviceIndication = new MemcpyIndication(IfcNames_MemcpyIndication);\n  bluescopeIndication = new BlueScopeIndication(IfcNames_BluescopeIndication);\n\n  fprintf(stderr, \"Main::allocating memory of size=%d...\\n\", (int)alloc_sz);\n\n  srcAlloc = portalAlloc(alloc_sz, 0);\n  dstAlloc = portalAlloc(alloc_sz, 0);\n  bsAlloc = portalAlloc(alloc_sz, 0);\n\n  // for(int i = 0; i < srcAlloc->header.numEntries; i++)\n  //   fprintf(stderr, \"%lx %lx\\n\", srcAlloc->entries[i].dma_address, srcAlloc->entries[i].length);\n  // for(int i = 0; i < dstAlloc->header.numEntries; i++)\n  //   fprintf(stderr, \"%lx %lx\\n\", dstAlloc->entries[i].dma_address, dstAlloc->entries[i].length);\n  // for(int i = 0; i < bsAlloc->header.numEntries; i++)\n  //   fprintf(stderr, \"%lx %lx\\n\", bsAlloc->entries[i].dma_address, bsAlloc->entries[i].length);\n\n\n  srcBuffer = (unsigned int *)portalMmap(srcAlloc, alloc_sz);\n  dstBuffer = (unsigned int *)portalMmap(dstAlloc, alloc_sz);\n  bsBuffer  = (unsigned int *)portalMmap(bsAlloc, alloc_sz);\n\n  for (int i = 0; i < numWords; i++){\n    srcBuffer[i] = i;\n    dstBuffer[i] = 0x5a5abeef;\n    bsBuffer[i]  = 0x5a5abeef;\n  }\n\n  portalCacheFlush(bsAlloc, bsBuffer, alloc_sz, 1);\n  portalCacheFlush(srcAlloc, srcBuffer, alloc_sz, 1);\n  portalCacheFlush(dstAlloc, dstBuffer, alloc_sz, 1);\n  fprintf(stderr, \"Main::flush and invalidate complete\\n\");\n\n  unsigned int ref_srcAlloc = dma->reference(srcAlloc);\n  unsigned int ref_dstAlloc = dma->reference(dstAlloc);\n  unsigned int ref_bsAlloc  = dma->reference(bsAlloc);\n  \n  bluescope->reset();\n  bluescope->setTriggerMask (0xFFFFFFFF);\n  bluescope->setTriggerValue(0x00000008);\n  bluescope->start(ref_bsAlloc, alloc_sz);\n\n  sleep(1);\n  //hostMemServerRequest->addrRequest(ref_srcAlloc, 1*sizeof(unsigned int));\n  sleep(1);\n  //hostMemServerRequest->addrRequest(ref_dstAlloc, 2*sizeof(unsigned int));\n  sleep(1);\n  //hostMemServerRequest->addrRequest(ref_bsAlloc, 3*sizeof(unsigned int));\n  sleep(1);\n  \n  fprintf(stderr, \"Main::starting mempcy numWords:%d\\n\", numWords);\n  int burstLen = 16;\n  device->startCopy(ref_dstAlloc, ref_srcAlloc, numWords, burstLen);\n  sem_wait(&done_sem);\n  sleep(2);\n  exit_test();\n}\n"
  },
  {
    "path": "contrib/bluescopeevent/Makefile",
    "content": "\nCONNECTALDIR?=../..\nINTERFACES = SignalGenRequest SignalGenIndication \\\n\tBlueScopeEventRequest BlueScopeEventIndication\nBSVFILES = ../../lib/bsv/BlueScopeEvent.bsv SignalGen.bsv Top.bsv\nCPPFILES=testbluescopeevent.cpp\n\ninclude $(CONNECTALDIR)/Makefile.connectal\n"
  },
  {
    "path": "contrib/bluescopeevent/SignalGen.bsv",
    "content": "// Copyright (c) 2014 Quanta Research Cambridge, Inc.\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\nimport BlueScopeEvent::*;\n\ninterface SignalGenIndication;\n   method Action ack1(Bit#(32) d1);\n   method Action ack2(Bit#(32) d1, Bit#(32) d2);\nendinterface\n      \ninterface SignalGenRequest;\n   method Action send1(Bit#(32) d1);\nendinterface\n\n\nmodule mkSignalGen#(BlueScopeEvent#(32) bse, SignalGenIndication indication)(SignalGenRequest);\n \n   method Action send1(Bit#(32) d1);\n      bse.dataIn(d1);\n      indication.ack1(d1);\n   endmethod\n  \n   \nendmodule\n"
  },
  {
    "path": "contrib/bluescopeevent/Top.bsv",
    "content": "/* Copyright (c) 2014 Quanta Research Cambridge, Inc\n *\n * Permission is hereby granted, free of charge, to any person obtaining a\n * copy of this software and associated documentation files (the \"Software\"),\n * to deal in the Software without restriction, including without limitation\n * the rights to use, copy, modify, merge, publish, distribute, sublicense,\n * and/or sell copies of the Software, and to permit persons to whom the\n * Software is furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n * DEALINGS IN THE SOFTWARE.\n */\nimport SpecialFIFOs::*;\nimport Vector::*;\nimport StmtFSM::*;\nimport FIFO::*;\nimport CtrlMux::*;\nimport Portal::*;\nimport HostInterface::*;\nimport BlueScopeEvent::*;\nimport ConnectalMemory::*;\nimport ConnectalMemTypes::*;\nimport MemServer::*;\nimport ConnectalMMU::*;\nimport SignalGen::*;\nimport BlueScopeEventRequest::*;\nimport BlueScopeEventIndication::*;\nimport MemServerRequest::*;\nimport MemServerIndication::*;\nimport MMURequest::*;\nimport MMUIndication::*;\nimport SignalGenRequest::*;\nimport SignalGenIndication::*;\n\n`define BlueScopeEventSampleLength 512\n\ntypedef enum {IfcNames_HostMemServerIndication, IfcNames_HostMemServerRequest, IfcNames_HostMMURequest, IfcNames_HostMMUIndication, IfcNames_BlueScopeEventIndication, IfcNames_BlueScopeEventRequest, IfcNames_SignalGenIndication, IfcNames_SignalGenRequest} IfcNames deriving (Eq,Bits);\n\nmodule mkConnectalTop(ConnectalTop);\n\n   BlueScopeEventIndicationProxy blueScopeEventIndicationProxy <- mkBlueScopeEventIndicationProxy(IfcNames_BlueScopeEventIndication);\n   BlueScopeEventControl#(32) bs <- mkBlueScopeEvent(`BlueScopeEventSampleLength, blueScopeEventIndicationProxy.ifc);\n   BlueScopeEventRequestWrapper blueScopeEventRequestWrapper <- mkBlueScopeEventRequestWrapper(IfcNames_BlueScopeEventRequest,bs.requestIfc);\n\n   SignalGenIndicationProxy signalGenIndicationProxy <- mkSignalGenIndicationProxy(IfcNames_SignalGenIndication);\n   SignalGenRequest sg <- mkSignalGen(bs.bse, signalGenIndicationProxy.ifc);\n   SignalGenRequestWrapper signalGenRequestWrapper <- mkSignalGenRequestWrapper(IfcNames_SignalGenRequest,sg);\n\n\n   Vector#(1, MemWriteClient#(DataBusWidth)) writeClients = newVector();\n   writeClients[0] = bs.writeClient;\n\n   MMUIndicationProxy hostMMUIndicationProxy <- mkMMUIndicationProxy(IfcNames_HostMMUIndication);\n   MMU#(PhysAddrWidth) hostMMU <- mkMMU(0, True, hostMMUIndicationProxy.ifc);\n   MMURequestWrapper hostMMURequestWrapper <- mkMMURequestWrapper(IfcNames_HostMMURequest, hostMMU.request);\n\n   MemServerIndicationProxy hostMemServerIndicationProxy <- mkMemServerIndicationProxy(IfcNames_HostMemServerIndication);\n   MemServer#(PhysAddrWidth,64,1) dma <- mkMemServer(nil, writeClients, cons(hostMMU,nil), hostMemServerIndicationProxy.ifc);\n   MemServerRequestWrapper hostMemServerRequestWrapper <- mkMemServerRequestWrapper(IfcNames_HostMemServerRequest, dma.request);\n\n   Vector#(8,StdPortal) portals;\n   portals[0] = signalGenRequestWrapper.portalIfc;\n   portals[1] = signalGenIndicationProxy.portalIfc; \n   portals[2] = blueScopeEventRequestWrapper.portalIfc;\n   portals[3] = blueScopeEventIndicationProxy.portalIfc; \n   portals[4] = hostMemServerRequestWrapper.portalIfc;\n   portals[5] = hostMemServerIndicationProxy.portalIfc; \n   portals[6] = hostMMURequestWrapper.portalIfc;\n   portals[7] = hostMMUIndicationProxy.portalIfc;\n   let ctrl_mux <- mkSlaveMux(portals);\n   \n   interface interrupt = getInterruptVector(portals);\n   interface slave = ctrl_mux;\n   interface masters = dma.masters;\nendmodule\n\n\n"
  },
  {
    "path": "contrib/bluescopeevent/testbluescopeevent.cpp",
    "content": "/* Copyright (c) 2013 Quanta Research Cambridge, Inc\n *\n * Permission is hereby granted, free of charge, to any person obtaining a\n * copy of this software and associated documentation files (the \"Software\"),\n * to deal in the Software without restriction, including without limitation\n * the rights to use, copy, modify, merge, publish, distribute, sublicense,\n * and/or sell copies of the Software, and to permit persons to whom the\n * Software is furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n * DEALINGS IN THE SOFTWARE.\n */\n#include <monkit.h>\n#include <semaphore.h>\n#include \"dmaManager.h\"\n#include \"BlueScopeEventIndication.h\"\n#include \"BlueScopeEventRequest.h\"\n#include \"SignalGenIndication.h\"\n#include \"SignalGenRequest.h\"\n\nsem_t done_sem;\nsem_t cv_sem;\nunsigned int counter_value = 0;\nint bsAlloc;\nuint64_t *bsBuffer  = 0;\nint numWords = 512; //16 << 10;\nsize_t alloc_sz = numWords*sizeof(uint64_t);\n\nbool finished = false;\n\n\nvoid exit_test()\n{\n  fprintf(stderr, \"test finished\\n\");\n  exit(0);\n}\n\nclass BlueScopeEventIndication : public BlueScopeEventIndicationWrapper\n{\npublic:\n  BlueScopeEventIndication(unsigned int id) : BlueScopeEventIndicationWrapper(id){}\n\n  virtual void dmaDone( ){\n    sem_post(&done_sem);\n    finished = true;\n    fprintf(stderr, \"BlueScopeEvent::dmaDone\\n\");\n  }\n  virtual void counterValue(uint32_t v){\n    counter_value = v;\n    sem_post(&cv_sem);\n    fprintf(stderr, \"BlueScopeEvent::counterValue value=%u\\n\", v);\n    \n  }\n};\n\nclass SignalGenIndication : public SignalGenIndicationWrapper\n{\npublic:\n  SignalGenIndication(unsigned int id) : SignalGenIndicationWrapper(id){}\n\n  virtual void ack1(unsigned int d1 ){\n    fprintf(stderr, \"SignalGen::ack1(%d)\\n\", d1);\n  }\n  virtual void ack2(unsigned int d1, unsigned int d2){ \n    fprintf(stderr, \"SignalGen::ack2(%d, %d)\\n\", d1, d2);\n }\n};\n\n// we can use the data synchronization barrier instead of flushing the \n// cache only because the ps7 is configured to run in buffered-write mode\n//\n// an opc2 of '4' and CRm of 'c10' encodes \"CP15DSB, Data Synchronization Barrier \n// operation\". this is a legal instruction to execute in non-privileged mode (mdk)\n//\n// #define DATA_SYNC_BARRIER   __asm __volatile( \"MCR p15, 0, %0, c7, c10, 4\" ::  \"r\" (0) );\n\nint main(int argc, const char **argv)\n{\n  BlueScopeEventRequestProxy *bluescope = 0;\n  BlueScopeEventIndication *bluescopeIndication = 0;\n  SignalGenRequestProxy *signalgen = 0;\n  SignalGenIndication *signalgenIndication = 0;\n  int i;\n\n  if(sem_init(&done_sem, 1, 0)){\n    fprintf(stderr, \"failed to init done_sem\\n\");\n    exit(1);\n  }\n  if(sem_init(&cv_sem, 1, 0)){\n    fprintf(stderr, \"failed to init cv_sem\\n\");\n    exit(1);\n  }\n\n  fprintf(stderr, \"%s %s\\n\", __DATE__, __TIME__);\n\n  bluescope = new BlueScopeEventRequestProxy(IfcNames_BlueScopeEventRequest);\n    DmaManager *dma = platformInit();\n  bluescopeIndication = new BlueScopeEventIndication(IfcNames_BlueScopeEventIndication);\n\n\n  signalgen = new SignalGenRequestProxy(IfcNames_SignalGenRequest);\n  signalgenIndication = new SignalGenIndication(IfcNames_SignalGenIndication);\n\n\n  fprintf(stderr, \"Main::allocating memory of size=%d...\\n\", (int)alloc_sz);\n\n  bsAlloc = portalAlloc(alloc_sz, 0);\n  bsBuffer  = (uint64_t *)portalMmap(bsAlloc, alloc_sz);\n\n  portalCacheFlush(bsAlloc, bsBuffer, alloc_sz, 1);\n  fprintf(stderr, \"Main::flush and invalidate complete\\n\");\n\n  unsigned int ref_bsAlloc  = dma->reference(bsAlloc);\n  \n  bluescope->doReset();\n  bluescope->setTriggerMask (0xFFFFFFFF);\n  bluescope->getCounterValue();\n  sem_wait(&cv_sem);\n  fprintf(stderr, \"Main::initial BlueScopeEvent counterValue: %d\\n\", counter_value);\n\n  sleep(1);\n  signalgen->send1(0x1);\n  fprintf(stderr, \"Main::send1\\n\");\n  signalgen->send1(0x2);\n  fprintf(stderr, \"Main::send1\\n\");\n  signalgen->send1(0x3);\n  fprintf(stderr, \"Main::send1\\n\");\n  signalgen->send1(0x4);\n  fprintf(stderr, \"Main::send1\\n\");\n  bluescope->getCounterValue();\n  fprintf(stderr, \"Main::getCounter\\n\");\n \n  sem_wait(&cv_sem);\n  fprintf(stderr, \"Main::final BlueScopeEvent counterValue: %d\\n\", counter_value);\n\n  // test here\n  if (counter_value != 4) counter_value = 4;\n  bluescope->startDma(ref_bsAlloc, counter_value * sizeof(uint64_t));\n  sem_wait(&done_sem);\n  for (i = 0; i < 5; i += 1) {\n    fprintf(stderr, \"event %3d: %08lx\\n\", i, bsBuffer[i]);\n  }\n  // XXX print event buffer\n  sleep(2);\n  exit_test();\n}\n"
  },
  {
    "path": "contrib/bluescopeeventpio/Makefile",
    "content": "CONNECTALDIR?=../..\nINTERFACES = SignalGenRequest SignalGenIndication \\\n\tBlueScopeEventPIORequest BlueScopeEventPIOIndication\n\nBSVFILES = ../../lib/bsv/BlueScopeEventPIO.bsv SignalGen.bsv Top.bsv\nCPPFILES=testbluescopeeventpio.cpp\n\ninclude $(CONNECTALDIR)/Makefile.connectal\n"
  },
  {
    "path": "contrib/bluescopeeventpio/SignalGen.bsv",
    "content": "// Copyright (c) 2014 Quanta Research Cambridge, Inc.\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\nimport BlueScopeEventPIO::*;\n\ninterface SignalGenIndication;\n   method Action ack1(Bit#(32) d1);\nendinterface\n      \ninterface SignalGenRequest;\n   method Action send1(Bit#(32) d1);\nendinterface\n\nmodule mkSignalGen#(BlueScopeEventPIO#(32) bse, SignalGenIndication indication)(SignalGenRequest);\n \n   method Action send1(Bit#(32) d1);\n      bse.dataIn(d1);\n      indication.ack1(d1);\n   endmethod\n   \nendmodule\n"
  },
  {
    "path": "contrib/bluescopeeventpio/Top.bsv",
    "content": "/* Copyright (c) 2014 Quanta Research Cambridge, Inc\n *\n * Permission is hereby granted, free of charge, to any person obtaining a\n * copy of this software and associated documentation files (the \"Software\"),\n * to deal in the Software without restriction, including without limitation\n * the rights to use, copy, modify, merge, publish, distribute, sublicense,\n * and/or sell copies of the Software, and to permit persons to whom the\n * Software is furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n * DEALINGS IN THE SOFTWARE.\n */\nimport Vector::*;\nimport FIFO::*;\nimport CtrlMux::*;\nimport Portal::*;\nimport HostInterface::*;\nimport BlueScopeEventPIO::*;\nimport SignalGen::*;\nimport BlueScopeEventPIORequest::*;\nimport BlueScopeEventPIOIndication::*;\nimport SignalGenRequest::*;\nimport SignalGenIndication::*;\n\n`define BlueScopeEventPIOSampleLength 512\n\ntypedef enum {IfcNames_BlueScopeEventPIOIndication, IfcNames_BlueScopeEventPIORequest, IfcNames_SignalGenIndication, IfcNames_SignalGenRequest} IfcNames deriving (Eq,Bits);\n\nmodule mkConnectalTop(StdConnectalTop#(PhysAddrWidth));\n\n   BlueScopeEventPIOIndicationProxy blueScopeEventPIOIndicationProxy <- mkBlueScopeEventPIOIndicationProxy(IfcNames_BlueScopeEventPIOIndication);\n   BlueScopeEventPIOControl#(32) bs <- mkBlueScopeEventPIO(`BlueScopeEventPIOSampleLength, blueScopeEventPIOIndicationProxy.ifc);\n   BlueScopeEventPIORequestWrapper blueScopeEventPIORequestWrapper <- mkBlueScopeEventPIORequestWrapper(IfcNames_BlueScopeEventPIORequest,bs.requestIfc);\n\n   SignalGenIndicationProxy signalGenIndicationProxy <- mkSignalGenIndicationProxy(IfcNames_SignalGenIndication);\n   SignalGenRequest sg <- mkSignalGen(bs.bse, signalGenIndicationProxy.ifc);\n   SignalGenRequestWrapper signalGenRequestWrapper <- mkSignalGenRequestWrapper(IfcNames_SignalGenRequest,sg);\n\n\n   Vector#(4,StdPortal) portals;\n   portals[0] = signalGenRequestWrapper.portalIfc;\n   portals[1] = signalGenIndicationProxy.portalIfc; \n   portals[2] = blueScopeEventPIORequestWrapper.portalIfc;\n   portals[3] = blueScopeEventPIOIndicationProxy.portalIfc; \n   let ctrl_mux <- mkSlaveMux(portals);\n   \n   interface interrupt = getInterruptVector(portals);\n   interface slave = ctrl_mux;\n   interface masters = nil;\nendmodule\n\n\n"
  },
  {
    "path": "contrib/bluescopeeventpio/testbluescopeeventpio.cpp",
    "content": "/* Copyright (c) 2013 Quanta Research Cambridge, Inc\n *\n * Permission is hereby granted, free of charge, to any person obtaining a\n * copy of this software and associated documentation files (the \"Software\"),\n * to deal in the Software without restriction, including without limitation\n * the rights to use, copy, modify, merge, publish, distribute, sublicense,\n * and/or sell copies of the Software, and to permit persons to whom the\n * Software is furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n * DEALINGS IN THE SOFTWARE.\n */\n#include <stdio.h>\n#include <stdint.h>\n#include <string.h>\n#include <stdlib.h>\n#include <unistd.h>\n#include <monkit.h>\n#include <semaphore.h>\n\n#include \"BlueScopeEventPIOIndication.h\"\n#include \"BlueScopeEventPIORequest.h\"\n#include \"SignalGenIndication.h\"\n#include \"SignalGenRequest.h\"\n\nsem_t done_sem;\nsem_t cv_sem;\nunsigned int counter_value = 0;\n\nbool finished = false;\n\n\nvoid exit_test()\n{\n  fprintf(stderr, \"test finished\\n\");\n  exit(0);\n}\n\nclass BlueScopeEventPIOIndication : public BlueScopeEventPIOIndicationWrapper\n{\npublic:\n  BlueScopeEventPIOIndication(unsigned int id) : BlueScopeEventPIOIndicationWrapper(id){}\n\n  virtual void reportEvent(uint32_t v, uint32_t timestamp ){\n    fprintf(stderr, \"BlueScopeEventPIO::reportEvent(%08x, %08x)\\n\", v, timestamp);\n  }\n  virtual void counterValue(uint32_t v){\n    counter_value = v;\n    sem_post(&cv_sem);\n    fprintf(stderr, \"BlueScopeEventPIO::counterValue value=%u\\n\", v);\n    \n  }\n};\n\nclass SignalGenIndication : public SignalGenIndicationWrapper\n{\npublic:\n  SignalGenIndication(unsigned int id) : SignalGenIndicationWrapper(id){}\n\n  virtual void ack1(unsigned int d1 ){\n    fprintf(stderr, \"SignalGen::ack1(%d)\\n\", d1);\n  }\n};\n\n// we can use the data synchronization barrier instead of flushing the \n// cache only because the ps7 is configured to run in buffered-write mode\n//\n// an opc2 of '4' and CRm of 'c10' encodes \"CP15DSB, Data Synchronization Barrier \n// operation\". this is a legal instruction to execute in non-privileged mode (mdk)\n//\n// #define DATA_SYNC_BARRIER   __asm __volatile( \"MCR p15, 0, %0, c7, c10, 4\" ::  \"r\" (0) );\n\nint main(int argc, const char **argv)\n{\n  BlueScopeEventPIORequestProxy *bluescope = 0;\n  BlueScopeEventPIOIndication *bluescopeIndication = 0;\n  SignalGenRequestProxy *signalgen = 0;\n  SignalGenIndication *signalgenIndication = 0;\n  int i;\n\n  if(sem_init(&done_sem, 1, 0)){\n    fprintf(stderr, \"failed to init done_sem\\n\");\n    exit(1);\n  }\n  if(sem_init(&cv_sem, 1, 0)){\n    fprintf(stderr, \"failed to init cv_sem\\n\");\n    exit(1);\n  }\n\n  fprintf(stderr, \"%s %s\\n\", __DATE__, __TIME__);\n\n  bluescope = new BlueScopeEventPIORequestProxy(IfcNames_BlueScopeEventPIORequest);\n\n  bluescopeIndication = new BlueScopeEventPIOIndication(IfcNames_BlueScopeEventPIOIndication);\n\n  signalgen = new SignalGenRequestProxy(IfcNames_SignalGenRequest);\n  signalgenIndication = new SignalGenIndication(IfcNames_SignalGenIndication);\n\n  bluescope->doReset();\n  bluescope->setTriggerMask (0xFFFFFFFF);\n  bluescope->getCounterValue();\n  bluescope->enableIndications(1);\n  sem_wait(&cv_sem);\n  fprintf(stderr, \"Main::initial BlueScopeEventPIO counterValue: %d\\n\", counter_value);\n\n  sleep(1);\n  signalgen->send1(0x1);\n  fprintf(stderr, \"Main::send1\\n\");\n  signalgen->send1(0x2);\n  fprintf(stderr, \"Main::send1\\n\");\n  signalgen->send1(0x3);\n  fprintf(stderr, \"Main::send1\\n\");\n  signalgen->send1(0x4);\n  fprintf(stderr, \"Main::send1\\n\");\n  bluescope->getCounterValue();\n  fprintf(stderr, \"Main::getCounter\\n\");\n \n  sem_wait(&cv_sem);\n  fprintf(stderr, \"Main::final BlueScopeEventPIO counterValue: %d\\n\", counter_value);\n\n  // test here\n  // XXX print event buffer\n  sleep(2);\n  exit_test();\n}\n"
  },
  {
    "path": "contrib/channelselect/ChannelSelect.bsv",
    "content": "// Copyright (c) 2014 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\nimport Complex::*;\nimport FixedPoint::*;\nimport SDRTypes::*;\nimport FPCMult::*;\nimport Gearbox::*;\nimport Pipe::*;\nimport FIFO::*;\nimport FIFOF::*;\nimport SpecialFIFOs::*;\nimport BRAM::*;\nimport BRAMFIFO::*;\nimport Vector::*;\nimport Clocks::*;\nimport DefaultValue::*;\nimport DDS::*;\n\n/* note rf signal is 64 bits wide, 2 sample of complex fixed point(0,16)\n */\n(* always_enabled *)\ninterface ChannelSelect;\n   interface PipeIn#(Vector#(2, Complex#(Signal))) rfreq;\n   interface PipeOut#(Complex#(Signal)) ifreq;\n   method Action setCoeff(Bit#(11) addr, Complex#(FixedPoint#(2,23)) value);\nendinterface\n\n\nmodule mkChannelSelect#(Bit#(10) decimation, DDS dds)(ChannelSelect);\n   BRAM_Configure cfg = defaultValue;\n   cfg.memorySize = 1024;\n   BRAM2Port#(Bit#(10), Complex#(FixedPoint#(2,23))) coeffRam0 <- \n       mkBRAM2Server(cfg);\n   BRAM2Port#(Bit#(10), Complex#(FixedPoint#(2,23))) coeffRam1 <- \n       mkBRAM2Server(cfg);\n   Reg#(Bit#(10)) filterPhase <- mkReg(0);\n   FIFO#(Bit#(1)) delayFilterPhase <- mkSizedFIFO(3);  // length > bram read latency\n   FIFOF#(Vector#(2, Complex#(Signal))) infifo <- mkFIFOF();\n   FIFOF#(Complex#(Signal)) outfifo <- mkFIFOF();\n   Vector#(2, FPCMult) mul <- replicateM(mkFPCMult());\n   Vector#(2, Reg#(Complex#(Product))) accum <- replicateM(mkReg(?));\n   Vector#(2, FIFO#(Complex#(Product))) accumout <- replicateM(mkFIFO());\n   FIFO#(Complex#(Product)) ycombined <- mkFIFO();\n   FPCMult lo <- mkFPCMult();\n\n   /* could do this with mkForkVector() but we don't need the extra FIFOs\n      since everything is ready every cycle\n    */\n   rule duplicateSignal;\n      let v = infifo.first;\n      infifo.deq();\n      mul[0].x.enq(v[0]);\n      mul[1].x.enq(v[1]);\n   endrule\n   \n   rule filter_phase;\n      $display(\"filter_phase %d dec %d\\n\", filterPhase, decimation\n);\n      if (filterPhase == (decimation - 1))\n\t begin\n\t    filterPhase <= 0;\n\t    delayFilterPhase.enq(1);\n\t end\n      else\n\t begin\n\t    filterPhase <= filterPhase + 1;\n\t    delayFilterPhase.enq(0);\n\t end\n      coeffRam0.portB.request.put(BRAMRequest{write: False, responseOnWrite: False, address: filterPhase, datain: ?});\n      coeffRam1.portB.request.put(BRAMRequest{write: False, responseOnWrite: False, address: filterPhase, datain: ?});\n   endrule\n   \n   rule mulin;\n      let c0 <- coeffRam0.portB.response.get();\n      let c1 <- coeffRam1.portB.response.get();\n      Bit#(1) phase = delayFilterPhase.first();\n      $write(\"mulin ph %d c0 \", phase);\n      $write(fshow(c0));\n      $write(\" c1 \");\n      $write(fshow(c1));\n      $write(\"\\n\");\n      \n      delayFilterPhase.deq();\n      mul[0].a.enq(CoeffData{a: c0, filterPhase: phase});\n      mul[1].a.enq(CoeffData{a: c1, filterPhase: phase});\n   endrule\n   \n   rule muloutaccumin0;\n      ProductData m = mul[0].y.first();\n      mul[0].y.deq();\n      if (m.filterPhase == 1)\n\t begin\n\t    accum[0] <= m.y;\n\t    $write(\"muloutaccumin0 ph 1 \");\n\t    $display(fshow(m.y));\n\t    accumout[0].enq(accum[0]);\n\t end\n      else\n\t begin\n\t    $write(\"muloutaccumin0 ph 0 \");\n\t    $display(fshow(m.y));\n\t    accum[0] <= accum[0] + m.y;\n\t end\n   endrule\n\n   rule muloutaccumin1;\n      ProductData m = mul[1].y.first();\n      mul[1].y.deq();\n      if (m.filterPhase == 1)\n\t begin\n\t    $write(\"muloutaccumin1 ph 1 \");\n\t    $display(fshow(m.y));\n\t    accum[1] <= m.y;\n\t    accumout[1].enq(accum[1]);\n\t end\n      else\n\t begin\n\t    $write(\"muloutaccumin0 ph 0 \");\n\t    $display(fshow(m.y));\n\t    accum[1] <= accum[1] + m.y;\n\t end\n   endrule\n\n   rule accumoutcombinein;\n      Complex#(Product) a0 = accumout[0].first();\n      Complex#(Product) a1 = accumout[1].first();\n      ycombined.enq(a0 + a1);\n      accumout[0].deq();\n      accumout[1].deq();\n   endrule\n   \n   rule combineoutloin;\n      Complex#(Product) yin = ycombined.first();\n      FixedPoint#(2,16) yrel = fxptTruncate(yin.rel);\n      FixedPoint#(2,16) yimg = fxptTruncate(yin.img);\n      DDSOutType loin = dds.osc.first();\n      dds.osc.deq();\n      ycombined.deq();\n      lo.x.enq(Complex{rel: yrel, img: yimg});\n      lo.a.enq(CoeffData{a: loin, filterPhase: 0});\n      $write(\"combineoutloin x \");\n      $write(fshow(Complex{rel: yrel, img: yimg}));\n      $write(\" loin \");\n      $display(fshow(loin));\n   endrule\n   \n   rule loout;\n      Complex#(Product) ifc = lo.y.first().y;\n      FixedPoint#(2,16) ifrel = fxptTruncate(ifc.rel);\n      FixedPoint#(2,16) ifimg = fxptTruncate(ifc.img);\n      outfifo.enq(Complex{rel: ifrel, img: ifimg});\n      lo.y.deq();\n      $write(\"loout \");\n      $display(fshow(Complex{rel: ifrel, img: ifimg}));\n   endrule\n   \n   interface PipeIn rfreq = toPipeIn(infifo);\n   \n   method Action setCoeff(Bit#(11) addr, Complex#(FixedPoint#(2,23)) value);\n      Bit#(1) idx = addr[0];\n      if (idx == 0)\n\t coeffRam0.portA.request.put(BRAMRequest{write: True, responseOnWrite: False, address: addr[10:1], datain: value});\n      else\n\t coeffRam1.portA.request.put(BRAMRequest{write: True, responseOnWrite: False, address: addr[10:1], datain: value});\n   endmethod\n      \n   interface PipeOut ifreq = toPipeOut(outfifo);\n   \nendmodule"
  },
  {
    "path": "contrib/channelselect/ChannelSelectTest.bsv",
    "content": "// Copyright (c) 2013 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\nimport DDS::*;\nimport Gearbox::*;\nimport ChannelSelect::*;\n\nimport Complex::*;\nimport SDRTypes::*;\nimport FPCMult::*;\nimport FixedPoint::*;\nimport Pipe::*;\nimport Vector::*;\nimport ChannelSelectTestInterfaces::*;\n\n\nmodule mkChannelSelectTestRequest#(ChannelSelectTestIndication indication) (ChannelSelectTestRequest)\n   provisos(Bits#(CoeffData, a__),\n\t    Bits#(ProductData, b__),\n\t    Bits#(MulData, c__));\n   Clock clk <- exposeCurrentClock;\n   Reset rst <- exposeCurrentReset;\n   Gearbox#(1, 2, Complex#(Signal)) gb <- mk1toNGearbox(clk, rst, clk, rst);\n   DDS dds <- mkDDS();\n   ChannelSelect cs <- mkChannelSelect(4, dds);\n   \n   rule processRF;\n      let data = gb.first();\n      gb.deq();\n      cs.rfreq.enq(data);\n   endrule\n   \n   rule processIF;\n      let data = cs.ifreq.first();\n      cs.ifreq.deq();\n      indication.ifreqData(zeroExtend(pack(data.rel)), zeroExtend(pack(data.img)));\n   endrule\n   \n   method Action rfreqDataWrite(Bit#(32) dataRe, Bit#(32) dataIm);\n      Signal re = unpack(truncate(dataRe));\n      Signal im = unpack(truncate(dataIm));\n      Vector#(1, Complex#(Signal)) x = newVector();\n      x[0] = Complex{rel: re, img: im};\n      gb.enq(x);\n      indication.setDataResp();\n   endmethod\n\n   method Action setCoeff(Bit#(11) addr, Bit#(32) valueRe, Bit#(32) valueIm);\n    FixedPoint#(2, 23) re = unpack(pack(truncate(valueRe)));\n    FixedPoint#(2, 23) im = unpack(pack(truncate(valueIm)));\n      cs.setCoeff(addr, Complex{rel: re, img:im});\n      indication.setConfigResp();\n   endmethod\n\n   method Action setPhaseAdvance(Bit#(32) i, Bit#(32) f);\n    dds.setPhaseAdvance(PhaseType{i: truncate(i), f: truncate(f)});\n      indication.setConfigResp();\n   endmethod\nendmodule\n\n\n"
  },
  {
    "path": "contrib/channelselect/ChannelSelectTestInterfaces.bsv",
    "content": "// Copyright (c) 2013 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\n\n/* rfreqDataWrite data is FixedPoint(2,14) */\n/* setCoeff data is FixedPoint(2, 23) */\ninterface ChannelSelectTestRequest;\n   method Action rfreqDataWrite(Bit#(32) dataRe, Bit#(32) dataIm);\n   method Action setCoeff(Bit#(11) addr, Bit#(32) valueRe, Bit#(32) valueIm);\n   method Action setPhaseAdvance(Bit#(32) i, Bit#(32) f);\nendinterface\n\n\n/* rfreqDataWrite data is FixedPoint(2,14) */\ninterface ChannelSelectTestIndication;\n   method Action ifreqData(Bit#(32) dataRe, Bit#(32) dataIm);\n   method Action setDataResp();\n   method Action setConfigResp();\nendinterface\n\n\n\n"
  },
  {
    "path": "contrib/channelselect/DDS.bsv",
    "content": "// Copyright (c) 2014 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\nimport Complex::*;\nimport FixedPoint::*;\n//import StmtFSM::*;\nimport BRAM::*;\nimport FIFOF::*;\nimport Pipe::*;\nimport Vector::*;\n\ntypedef Complex#(FixedPoint#(2,23)) DDSOutType;\ntypedef FixedPoint#(10,23) PhaseType;\n\ninterface DDS;\n   method Action setPhaseAdvance(PhaseType v);\n   method PhaseType getPhase();\n   interface PipeOut#(DDSOutType) osc;\nendinterface\n\nmodule mkDDS(DDS);\n   BRAM_Configure cfg = defaultValue;\n   cfg.memorySize = 1024;\n   cfg.loadFormat = tagged Binary \"sine.bin\";\n   BRAM1Port#(Bit#(10), DDSOutType) ram <-mkBRAM1Server(cfg);\n   FIFOF#(DDSOutType) ddsout <- mkFIFOF();\n   Reg#(PhaseType) phase <- mkReg(0);\n   Reg#(PhaseType) phaseAdvance <- mkReg(0);\n      /*\n   Reg#(UInt#(12)) idx <- mkReg(0);\n   Stmt dumpRam =   \n   seq\n      for (idx <= 0; idx < 1024; idx <= idx + 1)\n\t seq\n\t    ram.portA.request.put(BRAMRequest{write: False, responseOnWrite: False, address: truncate(pack(idx)), datain: ?});\n\t   action\n\t      let v <- ram.portA.response.get();\n\t      $display(\"adr %d\", idx);\n\t      $write( \"re \" ) ; fxptWrite( 10, v.rel ) ; $display(\"\" ) ;\n\t      $write( \"im \" ) ; fxptWrite( 10, v.img ) ; $display(\"\" ) ;\n\t      endaction\n\t    endseq\n   endseq;\n\n   mkAutoFSM (dumpRam);\n   */\n\n   rule filter_phase;\n      Bit#(10) addr;\n      phase <= phase + phaseAdvance;\n      addr = phase.i;\n      ram.portA.request.put(BRAMRequest{write: False, responseOnWrite: False, address: addr, datain: ?});\n      // $display(\"dds addr %x\\n\", addr);\n   endrule\n   \n   rule ddsoutrule;\n      let v <- ram.portA.response.get();\n      // $write(\"ddsout ph %d \" , phase);\n      // $display(fshow(v));\n      ddsout.enq(v);\n   endrule\n   \n\n   method Action setPhaseAdvance(PhaseType v);\n      // $write(\"setphase advance \");\n      $display(fshow(v));\n      phaseAdvance <= v;\n   endmethod\n   \n   method PhaseType getPhase();\n      return(phase);\n   endmethod\n   \n   interface PipeOut osc = toPipeOut(ddsout);\n\nendmodule\n"
  },
  {
    "path": "contrib/channelselect/DDSTest.bsv",
    "content": "// Copyright (c) 2013 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\nimport DDS::*;\nimport FixedPoint::*;\nimport Complex::*;\nimport Pipe::*;\nimport DDSTestInterfaces::*;\n\nmodule mkDDSTestRequest#(DDSTestIndication indication) (DDSTestRequest);\n   DDS dds <- mkDDS();\n\n   method Action setPhaseAdvance(Bit#(32) i, Bit#(32) f);\n    dds.setPhaseAdvance(PhaseType{i: truncate(i), f: truncate(f)});\n      indication.setConfigResp();\n   endmethod\n   \n   method Action getData();\n      PhaseType p = dds.getPhase();\n      DDSOutType d = dds.osc.first();\n      dds.osc.deq();\n      indication.ddsData(zeroExtend(p.i), zeroExtend(pack(d.rel)), zeroExtend(pack(d.img)));\n   endmethod\nendmodule\n\n\n"
  },
  {
    "path": "contrib/channelselect/DDSTestInterfaces.bsv",
    "content": "// Copyright (c) 2013 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\n\n/* setPhaseAdvance data is FixedPoint(10, 23) */\ninterface DDSTestRequest;\n   method Action setPhaseAdvance(Bit#(32) i, Bit#(32) f);\n   method Action getData();\nendinterface\n\n/* ddsData is Complex#(FixedPoint(2,23)) */\ninterface DDSTestIndication;\n   method Action setConfigResp();\n   method Action ddsData(Bit#(32) phase, Bit#(32) dataRe, Bit#(32) dataIm);\nendinterface\n\n\n\n"
  },
  {
    "path": "contrib/channelselect/FPCMult.bsv",
    "content": "// Copyright (c) 2014 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\n\n// This module implements a fixed point complex multiplication\n// that is intended to map smoothly onto the DSP slices in Xilinx\n// FPGAs.  To this end, the signal path is 18 bits (2 bits of integer\n// and 16 bits of fraction), the coefficient path is 25 bits (2 bits\n// of integer and 23 bits of fraction), and the product is 43 bits\n// 4 bits of integer and 39 bits of fraction).  The multiplier\n// in a DSP slice is actually 18 x 25 -> 45 bits.  The additional two\n// product bits are for overflow, since the complex multipler adds\n// four intermediate results.\n\n// Signal inputs and outputs are Pipe datatypes, to provide flow control.\n// The module is intended for use in environments where there may be\n// one result per cycle, but at slow signal rates, clock cycles may\n// be skipped.  Because the logic is pipelined, there are valid\n// bits that follow the signal path.  The signal is assumed to be provided\n// intermittently, while the coefficients are provided on demand up to\n// one per cycle.\n\n// Because one intended application is a Channel Select filter with\n// downconversion, the coefficient path supplies a \"filter phase\" boolean\n// which indicates the start of a new sample period at the output\n// intermediate frequency.\n\nimport FIFOF::*;\nimport SpecialFIFOs::*;\nimport Complex::*;\nimport FixedPoint::*;\nimport Pipe::*;\nimport FIFOF::*;\nimport SpecialFIFOs::*;\nimport SDRTypes::*;\n\ntypedef struct {\n\t\tComplex#(Coeff) a;\n\t\tBit#(1) filterPhase;\n\t\t} CoeffData deriving(Bits);\n\ntypedef struct {\n\t\tComplex#(Product) y;\n\t\tBit#(1) filterPhase;\n\t\t} ProductData deriving(Bits);\n\ntypedef struct {\n\t\tProduct arxr;\n\t\tProduct arxi;\n\t\tProduct aixr;\n\t\tProduct aixi;\n\t\tBit#(1) filterPhase;\n\t\t} MulData deriving(Bits);\n\ninterface FPCMult;\n   interface PipeIn#(Complex#(Signal)) x;\n   interface PipeIn#(CoeffData) a;\n   interface PipeOut#(ProductData) y;\nendinterface\n   \nmodule mkFPCMult(FPCMult)\n  provisos(Bits#(CoeffData, a__),\n     Bits#(ProductData, b__),\n     Bits#(MulData, c__));\n   /* input registers */\n   FIFOF#(CoeffData) ain <- mkPipelineFIFOF();\n   FIFOF#(Complex#(Signal)) xin <- mkPipelineFIFOF();\n   /* pipeline registers at output of multipliers */\n   Reg#(MulData) ax <- mkReg(?);\n   /* result registers */\n   FIFOF#(ProductData) yout <- mkPipelineFIFOF();\n\n   rule work;\n      /* compute multiplies */\n\n      Product arxr = fxptMult(ain.first().a.rel, xin.first.rel);\n      Product aixi = fxptMult(ain.first().a.img, xin.first.img);\n      Product arxi = fxptMult(ain.first().a.rel, xin.first.img);\n      Product aixr = fxptMult(ain.first().a.img, xin.first.rel);\n      ain.deq();\n      xin.deq();\n\n      ax <= MulData{arxr: arxr, aixi: aixi, arxi: arxi, aixr: aixr,\n\t filterPhase: ain.first().filterPhase};\n      /* pipeline and combine into outputs */\n      yout.enq(ProductData{y: Complex{rel: ax.arxr - ax.aixi, img: ax.arxi + ax.aixr}, filterPhase: ax.filterPhase});\n   endrule\n   \n   interface PipeOut y = toPipeOut(yout);\n   interface PipeIn x = toPipeIn(xin);\n   interface PipeIn a = toPipeIn(ain);\n   \nendmodule\n"
  },
  {
    "path": "contrib/channelselect/Makefile",
    "content": "CONNECTALDIR?=../..\nINTERFACES = ChannelSelectTestRequest DDSTestRequest ChannelSelectTestIndication DDSTestIndication\n\nBSVFILES = ChannelSelectTestInterfaces.bsv  DDSTestInterfaces.bsv Top.bsv\nCPPFILES=testchannelselecttest.cpp\n\ngentarget:: sine.bin\n\nsine.bin: sinetable\n\tmkdir -p bluesim\n\t./sinetable >sine.bin\n\tcp sine.bin bluesim\n\nsinetable: sinetable.c\n\tcc -o sinetable sinetable.c -lm\n\ninclude $(CONNECTALDIR)/Makefile.connectal\n"
  },
  {
    "path": "contrib/channelselect/Readme.md",
    "content": "## ChannelSelectTest\n\nL. Stewart <stewart@qrclab.com>\nAugust 21, 2014\n\nThis example is part of the front end of a software defined radio.\n\nDigital samples at the RF sample rate come in, are filtered by a\nfinite impulse response digital filter, and multiplied by a digital\nlocal oscillator signal.  The output is at the IF sample rate.\nDue to the high expected RF sample rate, the input is two samples\nper cycle at half the RF rate. Output is one sample per cycle at the\nIF rate.\n\nThis example is a test harness for the signal processing logic\nlocated in examples/fmcomms1\n\nThe test software loads filter coefficients one by one, then\nfeeds RF samples one at a time to the hardware.\n\nOccasionally, the hardware sends IF sample back, using the\nindications interface.\n\nThe hardware is supposed to map onto MAC units in the Xilinx.\n\nWhat it does\n\nThe hardware under test accepts two-at-a-time complex valued RF\nsamples.  Real and imaginary parts of the signal are 16 bits, \nwith 2 integer bits and 14 fraction bits.\n\nAn FIR filter is applied to the RF filter, and the result is\nmultiplied by a local oscillator.  The result is decimated\nand delivered as Complex valued IF samples.\n\nThe trick of Vanu and Welborn is used, so that the FIR filter only\ncomputes results at the IF sampling rate, and the local oscillator\nalso runs at the IF sample rate\n\n     \n"
  },
  {
    "path": "contrib/channelselect/SDRTypes.bsv",
    "content": "// Copyright (c) 2014 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\n\nimport Complex::*;\nimport FixedPoint::*;\n\ntypedef FixedPoint#(2,16) Signal;\ntypedef FixedPoint#(2,23) Coeff;\ntypedef FixedPoint#(4,39) Product;\n\n"
  },
  {
    "path": "contrib/channelselect/Top.bsv",
    "content": "// Copyright (c) 2014 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\nimport Vector::*;\nimport GetPut::*;\nimport Connectable :: *;\nimport FIFO::*;\nimport Portal::*;\nimport HostInterface::*;\nimport CtrlMux::*;\nimport MemServer::*;\nimport DDSTestInterfaces::*;\nimport DDSTest::*;\nimport ChannelSelectTestInterfaces::*;\nimport ChannelSelectTest::*;\nimport ChannelSelectTestRequest::*;\nimport ChannelSelectTestIndication::*;\nimport DDSTestRequest::*;\nimport DDSTestIndication::*;\n\ntypedef enum { IfcNames_ChannelSelectTestIndication, IfcNames_ChannelSelectTestRequest, IfcNames_DDSTestIndication, IfcNames_DDSTestRequest} IfcNames deriving (Eq,Bits);\n\nmodule mkConnectalTop(StdConnectalTop#(PhysAddrWidth));\n   ChannelSelectTestIndicationProxy channelSelectTestIndicationProxy <- mkChannelSelectTestIndicationProxy(IfcNames_ChannelSelectTestIndication);\n   ChannelSelectTestRequest channelSelectTestRequest <- mkChannelSelectTestRequest(channelSelectTestIndicationProxy.ifc);\n   ChannelSelectTestRequestWrapper channelSelectTestRequestWrapper <- mkChannelSelectTestRequestWrapper(IfcNames_ChannelSelectTestRequest, channelSelectTestRequest);\n   DDSTestIndicationProxy ddsTestIndicationProxy <- mkDDSTestIndicationProxy(IfcNames_DDSTestIndication);\n   DDSTestRequest ddsTestRequest <- mkDDSTestRequest(ddsTestIndicationProxy.ifc);\n   DDSTestRequestWrapper ddsTestRequestWrapper <- mkDDSTestRequestWrapper(IfcNames_DDSTestRequest, ddsTestRequest);\n\n   Vector#(4,StdPortal) portals;\n   portals[0] = channelSelectTestRequestWrapper.portalIfc;\n   portals[1] = channelSelectTestIndicationProxy.portalIfc; \n   portals[2] = ddsTestRequestWrapper.portalIfc;\n   portals[3] = ddsTestIndicationProxy.portalIfc; \n   let ctrl_mux <- mkSlaveMux(portals);\n   \n   interface interrupt = getInterruptVector(portals);\n   interface slave = ctrl_mux;\n   interface masters = nil;\nendmodule : mkConnectalTop\n"
  },
  {
    "path": "contrib/channelselect/sinetable.c",
    "content": "/* create hex file to load BRAM with sine and cosine tables\n * for the direct digital synthesizer\n */\n/*\n Copyright (c) 2014 Quanta Research Cambridge, Inc.\n\n Permission is hereby granted, free of charge, to any person\n obtaining a copy of this software and associated documentation\n files (the \"Software\"), to deal in the Software without\n restriction, including without limitation the rights to use, copy,\n modify, merge, publish, distribute, sublicense, and/or sell copies\n of the Software, and to permit persons to whom the Software is\n furnished to do so, subject to the following conditions:\n\n The above copyright notice and this permission notice shall be\n included in all copies or substantial portions of the Software.\n\n THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n SOFTWARE.\n*/\n\n\n#include <stdio.h>\n#include <math.h>\n\n\nint main(int argc, char *argv[])\n{\n  double s, c;\n  double phase;\n  int i, j;\n  unsigned long c_frac, s_frac;\n  for (i = 0; i < 1024; i += 1) {\n    c = cos(((double) i / 1024.0) * 2.0 * M_PI);\n    s = sin(((double) i / 1024.0) * 2.0 * M_PI);\n    c_frac = c * (double) (1L << 23);\n    s_frac = s * (double) (1L << 23);\n    for (j = 24; j >= 0; j -= 1)\n      printf(\"%1lx\", (c_frac >> j) & 0x1);\n    for (j = 24; j >= 0; j -= 1)\n      printf(\"%1lx\", (s_frac >> j) & 0x1);\n    printf(\"\\n\");\n  }\n  return(0);\n}\n"
  },
  {
    "path": "contrib/channelselect/testchannelselecttest.cpp",
    "content": "/* Copyright (c) 2014 Quanta Research Cambridge, Inc\n *\n * Permission is hereby granted, free of charge, to any person obtaining a\n * copy of this software and associated documentation files (the \"Software\"),\n * to deal in the Software without restriction, including without limitation\n * the rights to use, copy, modify, merge, publish, distribute, sublicense,\n * and/or sell copies of the Software, and to permit persons to whom the\n * Software is furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n * DEALINGS IN THE SOFTWARE.\n */\n#include <stdio.h>\n#include <stdlib.h>\n#include <unistd.h>\n\n#include <assert.h>\n#include <semaphore.h>\n\n#include \"ChannelSelectTestRequest.h\"\n#include \"ChannelSelectTestIndication.h\"\n#include \"DDSTestRequest.h\"\n#include \"DDSTestIndication.h\"\n#include \"GeneratedTypes.h\"\n\nsem_t data_sem;\nsem_t config_sem;\n\nclass ChannelSelectTestIndication : public ChannelSelectTestIndicationWrapper\n{\n\npublic:\n  ChannelSelectTestIndication(unsigned int id) : ChannelSelectTestIndicationWrapper(id){}\n\n  virtual void ifreqData(unsigned dataRe, unsigned dataIm){\n    fprintf(stdout, \"read %x %x\\n\", dataRe, dataIm);\n  }\n  virtual void setDataResp(){\n    fprintf(stdout, \"setDataResp\\n\");\n    sem_post(&data_sem);\n  }\n  virtual void setConfigResp(){\n    fprintf(stdout, \"setDataResp\\n\");\n    sem_post(&config_sem);\n  }\n};\n\nclass DDSTestIndication : public DDSTestIndicationWrapper\n{\n\npublic:\n  DDSTestIndication(unsigned int id) : DDSTestIndicationWrapper(id){}\n\n  virtual void ddsData(unsigned phase, unsigned dataRe, unsigned dataIm){\n    fprintf(stdout, \"data %d %X %x\\n\", phase, dataRe, dataIm);\n    sem_post(&data_sem);\n  }\n  virtual void setConfigResp(){\n    fprintf(stdout, \"dds.setDataResp\\n\");\n    sem_post(&config_sem);\n  }\n  \n};\n\nint main(int argc, const char **argv)\n{\n\n  ChannelSelectTestRequestProxy *ctdevice = 0;\n  ChannelSelectTestIndication *ctindication = 0;\n  DDSTestRequestProxy *ddsdevice = 0;\n  DDSTestIndication *ddsindication = 0;\n  sem_init(&data_sem, 0, 0);\n  sem_init(&config_sem, 0, 0);\n  fprintf(stdout, \"Main::%s %s\\n\", __DATE__, __TIME__);\n\n  ctdevice = new ChannelSelectTestRequestProxy(IfcNames_ChannelSelectTestRequest);\n\n  ctindication = new ChannelSelectTestIndication(IfcNames_ChannelSelectTestIndication);\n\n  ddsdevice = new DDSTestRequestProxy(IfcNames_DDSTestRequest);\n\n  ddsindication = new DDSTestIndication(IfcNames_DDSTestIndication);\n\n  fprintf(stdout, \"DDSTest\\n\");\n  ddsdevice->setPhaseAdvance(1, 0);\n\n  for (int i = 0; i < 2048; i += 1) {\n    ddsdevice->getData();\n    sem_wait(&data_sem);\n  }\n\n\n  fprintf(stdout, \"Main::starting\\n\");\n\n  ctdevice->setCoeff(0, 1<<21, 0);\n  sem_wait(&config_sem);\n  ctdevice->setCoeff(1, 1<<21, 0);\n  sem_wait(&config_sem);\n  ctdevice->setCoeff(2, 1<<21, 0);\n  sem_wait(&config_sem);\n  ctdevice->setCoeff(3, 1<<21, 0);\n  sem_wait(&config_sem);\n  ctdevice->setPhaseAdvance(0, 1 << 21);\n  sem_wait(&config_sem);\n\n  int i;\n  for (i = 0; i < 128; i += 1) {\n    ctdevice->rfreqDataWrite(1<<16, 0);   // should be re=1, im=0\n    sem_wait(&data_sem);\n  }\n\n  fprintf(stdout, \"Main::stopping\\n\");\n\n  exit(0);\n}\n"
  },
  {
    "path": "contrib/fib/Fib.bsv",
    "content": "// Copyright (c) 2014 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\nimport StackReg::*;\nimport StmtFSM::*;\n\ninterface FibIndication;\n    method Action fibresult(Bit#(32) v);\nendinterface\n\ninterface FibRequest;\n   method Action fib(Bit#(32) v);\nendinterface\n\ninterface Fib;\n   interface FibRequest request;\nendinterface\n\ntypedef enum {FIBSTATEIDLE, FIBSTATE1, FIBSTATE2, \n   FIBSTATE3, FIBSTATECOMPLETE} FSState\nderiving (Bits,Eq);\n\n\nmodule mkFib#(FibIndication indication)(Fib);\n\n   /* pc, args, vars */\n   StackReg#(128, FSState, Bit#(16), Bit#(16)) frame <- mkStackReg(128, FIBSTATEIDLE);\n\n   /* function variables that do not need to be saved or restored \n    *    in the pseudocode below, this is tmp2\n    */\n   Reg#(Bit#(16)) fibretval <- mkReg(0);\n      \n   /* experiment: recursive fibonnaci\n    * fib(n):\n    *   int tmp1, tmp2;\n    *   if n == 0 return 0  // fibstate1\n    *   if n == 1 return 1\n    *   tmp1 = fib(n-1)\n    *   tmp2 = fib(n-2)     // fibstate2\n    *   return tmp1 + tmp2  // fibstate3\n    */\n\n   rule fib1 (frame.pc == FIBSTATE1);\n      //$display(\"FIBSTATE1 %d\", frame.args);\n      if (frame.args == 0)\n\t begin\n\t    fibretval <= 0;\n\t    frame.doreturn();\n\t end\n     else if (frame.args == 1)\n\tbegin\n\t   fibretval <= 1;\n\t   frame.doreturn();\n\tend\n     else\n\t// call FIBSTATE1 and return to FIBSTATE2\n\t// call with argument frame.args -1 and tmp2 = 0\n\tframe.docall(FIBSTATE1, FIBSTATE2, frame.args - 1, 0);\n     endrule\n\n   rule fib2 (frame.pc == FIBSTATE2);\n      //$display(\"FIBSTATE2 (retval %d)\", fibretval);\n      // frame.vars <= fibretval; subsumed in docall\n      frame.docall(FIBSTATE1, FIBSTATE3, frame.args - 2, fibretval);\n   endrule\n      \n   rule fib3 (frame.pc == FIBSTATE3);\n      //$display(\"FIBSTATE3 tmp1 %d fibretval %d return %d\", frame.vars, fibretval, frame.vars + fibretval);\n      fibretval <= frame.vars + fibretval;\n      frame.doreturn();\n   endrule\n      \n   rule fibcomplete (frame.pc == FIBSTATECOMPLETE);\n      //$display(\"FIBSTATECOMPLETE %d %d\", frame.args, fibretval);\n      indication.fibresult(zeroExtend(fibretval));\n      // our work here is done\n      frame.nextpc(FIBSTATEIDLE);\n   endrule\n\n   interface FibRequest request;\n\n      method Action fib(Bit#(32) v);\n         //$display(\"request fib %d\", v);\n         // call FIBSTATE1 and return to FIBSTATECOMPLETE\n         // with argument v\n         frame.docall(FIBSTATE1, FIBSTATECOMPLETE, truncate(v), 0);\n      endmethod\n\n   endinterface\n      \nendmodule\n\n"
  },
  {
    "path": "contrib/fib/FibNarrow.bsv",
    "content": "// Copyright (c) 2014 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\nimport Stack::*;\nimport StmtFSM::*;\n\ninterface FibIndication;\n    method Action fibresult(Bit#(32) v);\n    method Action fibnote(Bit#(32) v);\nendinterface\n\ninterface FibRequest;\n   method Action fib(Bit#(32) v);\nendinterface\n\ntypedef enum {FIBSTATEIDLE, FIBSTATE1, FIBSTATE2, \n   FIBSTATE3, FIBSTATECOMPLETE, FIBCALLING, FIBRETURNING} FSState\nderiving (Bits,Eq);\n\nmodule mkFibRequest#(FibIndication indication)(FibRequest);\n//   provisos(Literal#(FSState));\n\n\n   /* stack frame */\n   Reg#(Bit#(16)) fibn <- mkReg(0);\n   Reg#(Bit#(16)) fibtmp1 <- mkReg(0);\n   Reg#(FSState) fibstate <- mkReg(FIBSTATEIDLE);\n\n   /* function variables that do not need to be saved or restored */\n   Reg#(Bit#(16)) fibretval <- mkReg(0);\n   \n   \n   /* offsets in stack frame */\n   Bit#(2) fsoffsetn = 0;\n   Bit#(2) fsoffsettmp1 = 1;\n   Bit#(2) fsoffsetnext = 2;\n   \n   Stack#(128, 3, Bit#(16)) stack <- mkStack(128 ,3);\n   \n   /* experiment: recursive fibonnaci\n    * fib(n):\n    *   int tmp1, tmp2;\n    *   if n == 0 return 1  // fibstate1\n    *   if n == 1 return 1\n    *   tmp1 = fib(n-1)\n    *   tmp2 = fib(n-2      // fibstate2\n    *   return tmp1 + tmp2  // fibstate3\n    *\n    * with explicit stack:\n    * struct fsf {\n    *   int level;\n    *   int tmp1;\n    *   int n;\n    *   int next_state;\n    * } stack[N]\n    * \n    */\n   \n   Reg#(Bit#(16)) fibcallarg <- mkReg(0);\n   Reg#(FSState) fibcallreturnto <- mkReg(FIBSTATEIDLE);\n   \n   Stmt callfibstmt =\n   seq\n//      $display(\"FIBCALL\");\n      stack.store(fsoffsetn, fibn);\n      stack.store(fsoffsettmp1, fibtmp1);\n      stack.store(fsoffsetnext, zeroExtend(pack(fibcallreturnto)));\n//      par\n\t stack.push();\n\t fibn <= fibcallarg;\n\t fibstate <= FIBSTATE1;\n//      endpar\n   endseq;\n   \n   FSM callFibFSM <- mkFSM(callfibstmt);\n   \n   Stmt fibreturnstmt =\n   seq\n//      $display(\"FIBRETURN\");\n      stack.pop();\n//      $display(\"FIBRETURN pop\");\n      stack.loadstart(fsoffsetn);\n      action\n\t let t <- stack.loadfinish();\n\t stack.loadstart(fsoffsettmp1);\n\t fibn <= t;\n      endaction\n//      $display(\"FIBRETURN n\");\n      action\n\t let t <- stack.loadfinish();\n\t stack.loadstart(fsoffsetnext);\n\t fibtmp1 <= t;\n      endaction\n//      $display(\"FIBRETURN tmp1\");\n      action\n\t let t <- stack.loadfinish();\n//\t $display(\"FIBRETURN set state %d\", t);\n\t fibstate <= unpack(truncate(t));\n      endaction\n   endseq;\n\n   FSM fibreturnFSM <- mkFSM(fibreturnstmt);\n\n   function Action callfib(Bit#(16) arg,  FSState returnto);\n   return action\n\t     fibstate <= FIBCALLING;\n\t     fibcallarg <= arg;\n\t     fibcallreturnto <= returnto;\n\t     callFibFSM.start();\n\t  endaction;\n   endfunction\n   \n   \n   \n   function Action fibreturn(Bit#(16) returnval);\n      return action\n\t\tfibstate <= FIBRETURNING;\n\t\tfibretval <= returnval;      \n\t\tfibreturnFSM.start();\n\t     endaction;\n   endfunction\n\n   rule fib1 (fibstate == FIBSTATE1);\n//      $display(\"FIBSTATE1\");\n     if (fibn == 0)\n\tfibreturn(0);\n     else if (fibn == 1)\n\tfibreturn(1);\n     else\n\tcallfib(fibn - 1, FIBSTATE2);\n     endrule\n\n   rule fib2 (fibstate == FIBSTATE2);\n//      $display(\"FIBSTATE2\");\n      fibtmp1 <= fibretval;\n      callfib(fibn - 2, FIBSTATE3);\n   endrule\n   \n   rule fib3 (fibstate == FIBSTATE3);\n//      $display(\"FIBSTATE3 fibtmp1 %d fibretval %d return %d\", fibtmp1, fibretval, fibtmp1 + fibretval);\n      fibreturn(fibtmp1 + fibretval);\n   endrule\n      \n   rule fibcomplete (fibstate == FIBSTATECOMPLETE);\n//      $display(\"FIBSTATECOMPLETE %d %d\", fibn, fibretval);\n      indication.fibresult(zeroExtend(fibretval));\n      fibstate <= FIBSTATEIDLE;\n   endrule\n   \n   method Action fib(Bit#(32) v);\n      $display(\"request fib %d\", v);\n      fibn <= truncate(v);\n      indication.fibnote(8);\n      callfib(truncate(v), FIBSTATECOMPLETE);\n   endmethod\n      \nendmodule\n\n"
  },
  {
    "path": "contrib/fib/Makefile",
    "content": "CONNECTALDIR?=../..\nS2H_INTERFACES = FibRequest:Fib.request\nH2S_INTERFACES = Fib:FibIndication\n\nBSVFILES = Fib.bsv\nCPPFILES=testfib.cpp\n\ninclude $(CONNECTALDIR)/Makefile.connectal\n"
  },
  {
    "path": "contrib/fib/Readme.md",
    "content": "Larry Stewart <stewart@serissa.com>\nFib is an example of a stylized way to construct recursive algorithms\nin hardware.\n\nThe main algorithm is constructed as a state machine.  In the\ncase of fibonacci, the pseudo code is\n\n    \n    fib(n):\n       int tmp1, tmp2;\n       if n == 0 return 0\n       if n == 1 return 1\n       tmp1 = fib(n-1)\n       tmp2 = fib(n-2)   \n       return tmp1 + tmp2\n\nExcept for the recursion, this could be implemented in the StmtFSM\nlanguage, but StmtFSM leaves the state machinery hidden, so there is no way\nto save and restore the \"program counter\" as would be needed to\nresume execution in the middle of an FSM after a return.\n\nLikewise, FSM server doesn't help, because you cannot call yourself.\n\nInstead, Fib is implemented using an FSM constructed out of individual rules\nwhich fire according to a state variable.  Fib takes three rules:\n\n\n   rule fib1 (fibstate == FIBSTATE1);\n     if (fibn == 0)\n\tfibreturn(0);\n     else if (fibn == 1)\n\tfibreturn(1);\n     else\n\tcallfib(fibn - 1, FIBSTATE2);\n     endrule\n\n   rule fib2 (fibstate == FIBSTATE2);\n      fibtmp1 <= fibretval;\n      callfib(fibn - 2, FIBSTATE3);\n   endrule\n   \n   rule fib3 (fibstate == FIBSTATE3);\n      fibreturn(fibtmp1 + fibretval);\n   endrule\n\nIn accordance with bluespec, each rule takes exactly one cycle to run,\nonce its guards are satisfied.\n\nThe newest version of thisfib is in the module FibWide.bsv, which uses\nthe library module lib/bsv/StackReg.bsv\n\nThe idea of StackReg is that it stores the entire \"local frame\" on a stack.\nThe local frame includes the program counter, the function arguments,\nand any local variables.  These are all stored in parallel, so it takes\nthree BRAMs of the appropriate widths.  Additional registers are used\nfor the \"top of stack\" and a bypass register that permits single cycle\nreturns.\n\nTo use the StackReg library, you instantiate a StackReg, with\nparameters for stack depth, types for the PC, arguments, and locals,\nand a parameter for the initial value of the PC.\n\nThereafter, you can use the docall and doreturn methods to implement\nrecursive algorithms.\n\n      \nThe original version of thisFib is in the module Fib.bsv, which uses\nthe library module lib/bsv/Stack.bsv\n\nStack uses a single 16 bit wide BRAM to store all the stack data in the\nlocal frame.  This is a multicycle operation, and requires the caller to\nimplement the FSMs to do the save and restore.  It uses less hardware, more\ntime, and is messy to code.\n\nThe original caller of this FSM uses \"callfib\" to start the run.\nThe first argument to callfib is the argument to this invocation of\nfib, and the second argument is the \"state\" to return to. In effect\nthis is the program counter value to push on the stack.  The state\nmachine returns from a call by using \"fibreturn\" with a return value.\n   \n   method Action fib(Bit#(32) v);\n      fibn <= truncate(v);\n      callfib(truncate(v), FIBSTATECOMPLETE);\n   endmethod\n\n   rule fibcomplete (fibstate == FIBSTATECOMPLETE);\n      indication.fibresult(zeroExtend(fibretval));\n      fibstate <= FIBSTATEIDLE;\n   endrule\n\nCall and return are a bit more complicated\n\n   function Action callfib(Bit#(16) arg,  FSState returnto);\n   return action\n\t     fibstate <= FIBCALLING;\n\t     fibcallarg <= arg;\n\t     fibcallreturnto <= returnto;\n\t     callFibFSM.start();\n\t  endaction;\n   endfunction\n   \nBecause it is a multicycle process to push the current state onto the\nstack and start the recursive call, the callfib function saves its\narguments in registers, changes the FSM state to FIBCALLING and launches\nthe callFibFSM.\n\n\n   Stmt callfibstmt =\n   seq\n      stack.store(fsoffsetn, fibn);\n      stack.store(fsoffsettmp1, fibtmp1);\n      stack.store(fsoffsetnext, zeroExtend(pack(fibcallreturnto)));\n      par\n\t stack.push();\n\t fibn <= fibcallarg;\n\t fibstate <= FIBSTATE1;\n      endpar\n   endseq;\n\nThis state machine pushes local variables onto the stack, increments the\nstack pointer, and changes the working register for the new call.  It \nthen sets the state to FIBSTATE1, the state for the first chunk of code\nin fib.\n\nWhen an invocation is finished, it calls \"fibreturn\" with a return value.\n   \n   function Action fibreturn(Bit#(16) returnval);\n      return action\n\t\tfibstate <= FIBRETURNING;\n\t\tfibretval <= returnval;      \n\t\tfibreturnFSM.start();\n\t     endaction;\n   endfunction\n\nSimilar to callfib, the process of popping the previous state off the\nstack is multicycle, so it is relegated to a StmtFSM.  While that FSM\nruns, the main machine state is set to FIBRETURNING\n\n   Stmt fibreturnstmt =\n   seq\n      stack.pop();\n      stack.loadstart(fsoffsetn);\n      action\n\t let t <- stack.loadfinish();\n\t stack.loadstart(fsoffsettmp1);\n\t fibn <= t;\n      endaction\n      action\n\t let t <- stack.loadfinish();\n\t stack.loadstart(fsoffsetnext);\n\t fibtmp1 <= t;\n      endaction\n      action\n\t let t <- stack.loadfinish();\n\t fibstate <= unpack(truncate(t));\n      endaction\n   endseq;\n\nThis FSM decrements the frame pointer, then restores the local variables\nto their previous values.  The final step is restoring the \"pc\" which\ncauses the original state machine to resume execution in its previous\ncontext.\n\n"
  },
  {
    "path": "contrib/fib/testfib.cpp",
    "content": "/* Copyright (c) 2014 Quanta Research Cambridge, Inc\n *\n * Permission is hereby granted, free of charge, to any person obtaining a\n * copy of this software and associated documentation files (the \"Software\"),\n * to deal in the Software without restriction, including without limitation\n * the rights to use, copy, modify, merge, publish, distribute, sublicense,\n * and/or sell copies of the Software, and to permit persons to whom the\n * Software is furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n * DEALINGS IN THE SOFTWARE.\n */\n\n#include <stdio.h>\n#include <stdlib.h>\n#include <semaphore.h>\n#include <unistd.h>\n\n#include \"FibIndication.h\"\n#include \"FibRequest.h\"\n#include \"GeneratedTypes.h\"\n\nsem_t test_sem;\n\nclass FibIndication : public FibIndicationWrapper\n{\npublic:\n    virtual void fibresult(uint32_t v) {\n      fprintf(stderr, \"fibresult: %d\\n\", v);\n\tsem_post(&test_sem);\n    }\n    FibIndication(unsigned int id) : FibIndicationWrapper(id) {}\n};\n\nstatic FibRequestProxy *fibRequestProxy = 0;\nFibIndication *fibIndication;\n\n\nint main(int argc, const char **argv)\n{\n  int i;\n  // these use the default poller\n\n  fibIndication = new FibIndication(IfcNames_FibIndicationH2S);\n  fibRequestProxy = new FibRequestProxy(IfcNames_FibRequestS2H);\n  \n  if(sem_init(&test_sem, 1, 0)){\n    fprintf(stderr, \"failed to init test_sem\\n\");\n    return -1;\n  }\n  for (i = 0; i < 20; i += 1) {\n    fprintf(stderr, \"fib(%d)\\n\", i);\n    fibRequestProxy->fib(i);\n    sem_wait(&test_sem);\n  }\n\n  return 0;\n}\n"
  },
  {
    "path": "contrib/flowcontrol/Makefile",
    "content": "CONNECTALDIR?=../..\nINTERFACES = SinkRequest SinkIndication\n\nBSVFILES = Sink.bsv Top.bsv\nCPPFILES=test.cpp\n\ninclude $(CONNECTALDIR)/Makefile.connectal\n"
  },
  {
    "path": "contrib/flowcontrol/Sink.bsv",
    "content": "\n// Copyright (c) 2013 Nokia, Inc.\n// Copyright (c) 2013 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\nimport FIFO::*;\n\ninterface SinkIndication;\n   method Action returnTokens(Bit#(32) v);\nendinterface\n\ninterface SinkRequest;\n   method Action init(Bit#(32) v);\n   method Action put(Bit#(32) v);\nendinterface\n\nmodule mkSinkRequest#(SinkIndication indication)(SinkRequest);\n      \n   Bit#(32) threshold = 4;\n   Bit#(32) capacity = 24;\n   Reg#(Bit#(32)) count <- mkReg(0);\n\n   rule consume (count >= threshold);\n      indication.returnTokens(count);\n      count <= 0;\n   endrule\n   \n   method Action init(Bit#(32) v);\n      indication.returnTokens(capacity);\n   endmethod\n\n   method Action put(Bit#(32) v) if (count < capacity);\n      count <= count+1;\n   endmethod\n\nendmodule\n\n\n\n\n\n"
  },
  {
    "path": "contrib/flowcontrol/Top.bsv",
    "content": "/* Copyright (c) 2014 Quanta Research Cambridge, Inc\n *\n * Permission is hereby granted, free of charge, to any person obtaining a\n * copy of this software and associated documentation files (the \"Software\"),\n * to deal in the Software without restriction, including without limitation\n * the rights to use, copy, modify, merge, publish, distribute, sublicense,\n * and/or sell copies of the Software, and to permit persons to whom the\n * Software is furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n * DEALINGS IN THE SOFTWARE.\n */\nimport Vector::*;\nimport FIFO::*;\nimport Connectable::*;\nimport Portal::*;\nimport HostInterface::*;\nimport CtrlMux::*;\nimport SinkIndication::*;\nimport SinkRequest::*;\nimport Sink::*;\n\ntypedef enum {IfcNames_SinkIndication, IfcNames_SinkRequest} IfcNames deriving (Eq,Bits);\n\nmodule mkConnectalTop(StdConnectalTop#(PhysAddrWidth));\n\n   // instantiate user portals\n   SinkIndicationProxy sinkIndicationProxy <- mkSinkIndicationProxy(IfcNames_SinkIndication);\n   SinkRequest sinkRequest <- mkSinkRequest(sinkIndicationProxy.ifc);\n   SinkRequestWrapper sinkRequestWrapper <- mkSinkRequestWrapper(IfcNames_SinkRequest,sinkRequest);\n   \n   Vector#(2,StdPortal) portals;\n   portals[0] = sinkIndicationProxy.portalIfc;\n   portals[1] = sinkRequestWrapper.portalIfc; \n   let ctrl_mux <- mkSlaveMux(portals);\n   \n   interface interrupt = getInterruptVector(portals);\n   interface slave = ctrl_mux;\n   interface masters = nil;\nendmodule : mkConnectalTop\n"
  },
  {
    "path": "contrib/flowcontrol/test.cpp",
    "content": "/* Copyright (c) 2014 Quanta Research Cambridge, Inc\n *\n * Permission is hereby granted, free of charge, to any person obtaining a\n * copy of this software and associated documentation files (the \"Software\"),\n * to deal in the Software without restriction, including without limitation\n * the rights to use, copy, modify, merge, publish, distribute, sublicense,\n * and/or sell copies of the Software, and to permit persons to whom the\n * Software is furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n * DEALINGS IN THE SOFTWARE.\n */\n\n#include <stdio.h>\n#include <stdlib.h>\n#include <pthread.h>\n\n#include \"SinkIndication.h\"\n#include \"SinkRequest.h\"\n#include \"GeneratedTypes.h\"\n\n#include <stdio.h>\n#include <stdlib.h>\n\npthread_mutex_t count_mutex     = PTHREAD_MUTEX_INITIALIZER;\npthread_cond_t  condition_var   = PTHREAD_COND_INITIALIZER;\nint count = 0;\n\nclass SinkIndication : public SinkIndicationWrapper\n{\npublic:\n  virtual void returnTokens(uint32_t v) {\n    // Lock mutex and update the count variable\n    pthread_mutex_lock( &count_mutex );\n    count += v;\n\n    // Signal to main() thread that more tokens have been\n    // returned from the SinkRequest hardware and unlock mutex\n    pthread_cond_signal( &condition_var );\n    pthread_mutex_unlock( &count_mutex );\n  }\n  SinkIndication(unsigned int id) : SinkIndicationWrapper(id){}\n};\n\nint main(int argc, const char **argv)\n{\n\n  int tokens = 0;\n  SinkIndication *sinkIndication = new SinkIndication(IfcNames_SinkIndication);\n  SinkRequestProxy *sinkRequestProxy = new SinkRequestProxy(IfcNames_SinkRequest);\n  \n  fprintf(stderr, \"Main::creating exec thread\\n\");\n  sinkRequestProxy->init(0);\n  while(tokens < 32){\n\n    // Lock mutex and then wait for signal to relase mutex\n    pthread_mutex_lock( &count_mutex );\n\n    // Wait while SinkIndication::returnTokens updates count\n    // mutex unlocked if condition varialbe is signaled.\n    pthread_cond_wait( &condition_var, &count_mutex );\n\n    // consume the credit\n    int local_count = count;\n    count = 0;\n\n    // Unlock the mutex so SinkIndication::returnTokens can\n    // accept more tokens from the SinkRequest hardware\n    pthread_mutex_unlock( &count_mutex );\n\n    while(local_count){\n      fprintf(stderr, \"main() count:%d\\n\", local_count--);\n      sinkRequestProxy->put(tokens++);\n    }\n\n  }\n  \n  return 0;\n}\n"
  },
  {
    "path": "contrib/importverilog/.gitignore",
    "content": "RegFile.bsv\n"
  },
  {
    "path": "contrib/importverilog/Main.bsv",
    "content": "\n// Copyright (c) 2013 Nokia, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\nimport FIFOF::*;\nimport RegFile::*;\nimport Clocks::*;\nimport DefaultValue::*;\nimport StmtFSM::*;\n\ninterface MainRequest;\n    method Action write_rf(Bit#(16) address, Bit#(16) data);\n    method Action read_rf(Bit#(16) address, Bit#(16) data);\nendinterface\n\ninterface Main;\n   interface MainRequest request;\nendinterface\n\ntypedef struct{\n   Bit#(2) address;\n   Bit#(8) data;\n   } RFItem deriving (Bits);\n\n\nmodule mkMain#(MainRequest indication)(Main);\n   let verbose = False;\n   Clock defaultClock <- exposeCurrentClock();\n\n   Reset defaultReset <- exposeCurrentReset();\n   RegFile rf <- mkRegFile(defaultClock, defaultReset, defaultReset);\n   FIFOF#(RFItem) read_item <- mkSizedFIFOF(2);\n\n   // The purpose of this state machine is to read\n   \n   Stmt handleRead =\n   seq\n      while(True)\n   seq\n      if (read_item.notEmpty())\n\t seq\n\t    rf.read.address(zeroExtend(read_item.first().address));\n\t    action\n\t       read_item.deq();\n\t       indication.read_rf(zeroExtend(read_item.first().address), zeroExtend(rf.read.data()));\n\t    endaction\n\t endseq\n      endseq\n   endseq;\n   \n  mkAutoFSM(handleRead);\n   \n   interface MainRequest request;\n\n   method Action write_rf(Bit#(16) address, Bit#(16) data);\n      if (verbose) $display(\"mkMain::write_rf\");\n      rf.write.address(truncate(address));\n      rf.write.data(truncate(data));\n      rf.write.en(1);\n      indication.write_rf(address, data);\n   endmethod\n\n   method Action read_rf(Bit#(16) address, Bit#(16) data);\n      if (verbose) $display(\"mkMain::read_rf\");\n      read_item.enq(RFItem{address:truncate(address), data:0});\n    endmethod\n\n   endinterface\nendmodule\n"
  },
  {
    "path": "contrib/importverilog/Makefile",
    "content": "CONNECTALDIR?=../..\nS2H_INTERFACES = MainRequest:Main.request\nH2S_INTERFACES = Main:MainRequest\n\nBSVFILES = Main.bsv RegFile.bsv\nCPPFILES=testmain.cpp\n\nRegFile.bsv: regfile.v\n\t$(CONNECTALDIR)/generated/scripts/importbvi.py -o RegFile.bsv -I RegFile -P RF  -c clock -r reset_n \\\n\tregfile.v\n\ninclude $(CONNECTALDIR)/Makefile.connectal\n"
  },
  {
    "path": "contrib/importverilog/Readme.md",
    "content": "This example shows how to integrate a verilog module\nwith Bluespec code.\n\nIn the Makefile there is a target to build RefFile.bsv automatically\nfrom regfile.v.  This creates a Bluespec wrapper for the verilog,\nallowing Bluespec code to send signals into the verilog and to get\nresults back into Bluespec.\n"
  },
  {
    "path": "contrib/importverilog/regfile.v",
    "content": "// simple verilog example of a 2 port register file with 4 registers\n\n module regfile (clock, reset_n, write_address, write_data, write_en,\n\t\tread_address, read_data);\n   input clock;\n   input reset_n;\n   input [1:0] write_address;\n   input [7:0] write_data;\n   input       write_en;\n   input [1:0] read_address;\n   output [7:0] read_data;\n\n   reg [7:0] \treg0;\n   reg [7:0] \treg1;\n   reg [7:0] \treg2;\n   reg [7:0] \treg3;\n   reg [1:0] \tra;\n   \n   wire [7:0] \tread_data;\n   \n  assign read_data = (ra == 0) ? reg0 :\n\t\t      (ra == 1) ? reg1 :\n\t\t      (ra == 2) ? reg2 :\n\t\t     (ra == 3) ? reg3 : 0;\n\n   \n   always @ (posedge clock)\n     ra <= read_address;\n   \n   always @ (posedge clock)\n   if (reset_n == 0) begin\n      reg0 <= 0;\n      reg1 <= 0;\n      reg2 <= 0;\n      reg3 <= 0;\n   end else begin\n      if (write_en) begin\n\t case(write_address)\n\t   0: reg0 <= write_data;\n\t   1: reg1 <= write_data;\n\t   2: reg2 <= write_data;\n\t   3: reg3 <= write_data;\n\t endcase // case (write_address)\n      end\n   end // else: !if(rst)\n\nendmodule\n\n"
  },
  {
    "path": "contrib/importverilog/regfile_tb.v",
    "content": "module regfile_tb;\n\n   reg clock;\n   reg reset;\n   reg [1:0] read_address;\n\n   reg [1:0] write_address;\n\n   reg [7:0] write_data;\n   reg   write_en;\n   wire [7:0] read_data;\n\n   initial begin\n      $monitor (\"we=%b, wa=%b, wd=%b, ra=%b, rd=%b\",\n\t\twrite_en, write_address, write_data,\n\t\tread_address, read_data);\n      clock=0;\n      reset=0;\n      write_address=0;\n      write_data=0;\n      write_en=0;\n      read_address=0;\n\n      #20 reset = 1;\n      #20 reset = 0;\n\n      #20 read_address = 2'b00;\n      #20 read_address = 2'b01;\n      #20 read_address = 2'b10;\n      #20 read_address = 2'b11;\n\n      #20 write_address = 2'b00;\n      #1 write_data = 8'b00010000;\n      \n      #20 write_en = 1;\n      #20 write_address = 2'b01;\n      #1 write_data = 8'b00010001;\n      #20 write_address = 2'b10;\n      #1 write_data = 8'b00010010;\n      #20 write_address = 2'b11;\n      #1 write_data = 8'b00010011;\n      #20 write_en = 0;\n      #20 read_address = 2'b00;\n      #20 read_address = 2'b01;\n      #20 read_address = 2'b10;\n      #20 read_address = 2'b11;\n   $finish;\n   end // initial begin\n   always begin\n      #5 clock = !clock;\n   end\n\n   regfile U0 (\n\t       .clock (clock),\n\t       .reset (reset),\n\t       .write_address (write_address),\n\t       .write_data (write_data),\n\t       .write_en (write_en),\n\t       .read_address (read_address),\n\t       .read_data (read_data)\n\t       );\n   \n   \nendmodule // regfile_tb\n"
  },
  {
    "path": "contrib/importverilog/testmain.cpp",
    "content": "/* Copyright (c) 2014 Quanta Research Cambridge, Inc\n *\n * Permission is hereby granted, free of charge, to any person obtaining a\n * copy of this software and associated documentation files (the \"Software\"),\n * to deal in the Software without restriction, including without limitation\n * the rights to use, copy, modify, merge, publish, distribute, sublicense,\n * and/or sell copies of the Software, and to permit persons to whom the\n * Software is furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n * DEALINGS IN THE SOFTWARE.\n */\n\n#include <stdio.h>\n#include <assert.h>\n\n#include \"MainRequest.h\"\n\n#define NUMBER_OF_TESTS 8\n\n\nclass Main : public MainRequestWrapper\n{  \npublic:\n  uint32_t cnt;\n  void incr_cnt(){\n    if (++cnt == NUMBER_OF_TESTS)\n      exit(0);\n  }\n  virtual void write_rf(uint16_t address, uint16_t data) {\n    fprintf(stderr, \"write_rf(%d 0x%02x)\\n\", address, data);\n    incr_cnt();\n  }\n  virtual void read_rf(uint16_t address, uint16_t data) {\n    fprintf(stderr, \"read_rf(%d 0x%02x)\\n\", address, data);\n    incr_cnt();\n  }\n  Main(unsigned int id) : MainRequestWrapper(id), cnt(0){}\n};\n\n\n\nint main(int argc, const char **argv)\n{\n  Main *indication = new Main(IfcNames_MainRequestH2S);\n  MainRequestProxy *device = new MainRequestProxy(IfcNames_MainRequestS2H);\n  device->pint.busyType = BUSY_SPIN;   /* spin until request portal 'notFull' */\n\n  fprintf(stderr, \"Main::calling write_rf(11, 22, 33, 44)\\n\");\n  device->write_rf(0, 0x11);\n  device->write_rf(1, 0x22);\n  device->write_rf(2, 0x33);\n  device->write_rf(3, 0x44);\n  fprintf(stderr, \"Main::calling read_rf(0, 1, 2, 3)\\n\");\n  device->read_rf(0,0);\n  device->read_rf(1,0);\n  device->read_rf(2,0);\n  device->read_rf(3,0);\n  fprintf(stderr, \"Main::about to go to sleep\\n\");\n  while(true){sleep(2);}\n}\n"
  },
  {
    "path": "contrib/maxcommonsubseq/HirschA.bsv",
    "content": "// Copyright (c) 2014 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\nimport StmtFSM::*;\nimport BRAM::*;\nimport MCSAlgorithm::*;\n\nmodule mkHirschA#(BRAMServer#(Bit#(strIndexWidth), Bit#(8)) strA, BRAMServer#(Bit#(strIndexWidth), Bit#(8)) strB, BRAMServer#(Bit#(lIndexWidth), Bit#(16)) matL)(MCSAlgorithm)\n      provisos(Add#(0, 14, strIndexWidth),\n\t       Add#(0, 14, lIndexWidth));\n\n   Reg#(Bit#(14)) aStartReg <- mkReg(0);\n   Reg#(Bit#(14)) bStartReg <- mkReg(0);\n   Reg#(Bit#(14)) aLenReg <- mkReg(0);\n   Reg#(Bit#(14)) bLenReg <- mkReg(0);\n   Reg#(Bit#(14)) rLenReg <- mkReg(0);\n   Reg#(Bit#(14)) ii <- mkReg(0);\n   Reg#(Bit#(14)) jj <- mkReg(0);\n   Reg#(Bit#(8)) aData <- mkReg(0);\n   Reg#(Bit#(8)) bData <- mkReg(0);\n   Reg#(Bit#(16)) lim1jm1 <- mkReg(0);\n   Reg#(Bit#(16)) lim1j <- mkReg(0);\n   Reg#(Bit#(16)) lijm1 <- mkReg(0);\n\n   Stmt hirschA =\n   seq\n//      $display(\"hirschA running alen %d blen %d\", aLenReg, bLenReg);\n      for (ii<= 0; ii < aLenReg; ii <= ii + 1)\n\t seq\n\t    matL.request.put(BRAMRequest{write: True, responseOnWrite: False, address: {ii[6:0],0}, datain: 0});\n\t    endseq\n      for (ii<= 0; ii < aLenReg; ii <= ii + 1)\n\t seq\n\t    matL.request.put(BRAMRequest{write: True, responseOnWrite: False, address: {0,ii[6:0]}, datain: 0});\n\t endseq\n      for (ii<= 1; ii <= aLenReg; ii <= ii + 1)\n\t for (jj<= 1; jj <= bLenReg; jj <= jj + 1)\n\t    seq\n\t       strA.request.put(BRAMRequest{write: False, responseOnWrite: False, address: aStartReg + ii-1, datain: 0});\n\t       strB.request.put(BRAMRequest{write: False, responseOnWrite: False, address: bStartReg + jj-1, datain: 0});\n\t       action\n\t\t  let ta <- strA.response.get();\n\t\t  let tb <- strB.response.get();\n\t\t  aData <= ta;\n\t\t  bData <= tb;\n\t       endaction\n\t       if (aData == bData)\n\t\t  seq\n\t\t     matL.request.put(BRAMRequest{write: False, responseOnWrite: False, address: {ii[6:0]-1,jj[6:0]-1}, datain: 0});\n\t\t     action\n\t\t\tlet temp <- matL.response.get();\n\t\t\tlim1jm1 <= temp;\n\t\t     endaction\n\t\t     matL.request.put(BRAMRequest{write: True, responseOnWrite: False, address: {ii[6:0],jj[6:0]}, datain: lim1jm1+1});\n\t\t     \n\t\t  endseq\n\t       else\n\t\t  seq\n\t\t     matL.request.put(BRAMRequest{write: False, responseOnWrite: False, address: {ii[6:0],jj[6:0]-1}, datain: 0});\n\t\t     action\n\t\t\tlet tlijm1 <- matL.response.get();\n\t\t\tlijm1 <= tlijm1;\n\t\t     endaction\n\t\t     matL.request.put(BRAMRequest{write: False, responseOnWrite: False, address: {ii[6:0]-1,jj[6:0]}, datain: 0});\n\t\t     action\n\t\t\tlet tlim1j <- matL.response.get();\n\t\t\tlim1j <= tlim1j;\n\t\t     endaction\n\t\t\tmatL.request.put(BRAMRequest{write: True, responseOnWrite: False, address: {ii[6:0],jj[6:0]}, datain: max(lijm1,lim1j)});\n\t\t  endseq\n\t    endseq\n   endseq;\n   \n   FSM hA <- mkFSM(hirschA);\n  \n   method Action setupA(Bit#(14) start, Bit#(14) length);\n      aStartReg <= start;\n      aLenReg <= length;\n   endmethod\n   \n   method Action setupB(Bit#(14) start, Bit#(14) length);\n      bStartReg <= start;\n      bLenReg <= length;\n   endmethod\n  \n   method Action setupL(Bit#(14) start);\n   endmethod\n\n   method Bit#(14) result();\n      return(zeroExtend(aLenReg) * zeroExtend(bLenReg));\n   endmethod\n  \n   interface FSM fsm = hA;\n\n\nendmodule\n"
  },
  {
    "path": "contrib/maxcommonsubseq/HirschB.bsv",
    "content": "// Copyright (c) 2014 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\nimport StmtFSM::*;\nimport BRAM::*;\nimport MCSAlgorithm::*;\n\nmodule mkHirschB#(BRAMServer#(Bit#(strIndexWidth), Bit#(8)) strA, BRAMServer#(Bit#(strIndexWidth), Bit#(8)) strB, BRAMServer#(Bit#(lIndexWidth), Bit#(16)) matL, int dir)(MCSAlgorithm)\n         provisos(Add#(0, 14, strIndexWidth),\n\t       Add#(0, 14, lIndexWidth));\n\n\n   Reg#(Bit#(14)) aStartReg <- mkReg(0);\n   Reg#(Bit#(14)) bStartReg <- mkReg(0);\n   Reg#(Bit#(14)) rStartReg <- mkReg(0);\n   Reg#(Bit#(14)) aLenReg <- mkReg(0);\n   Reg#(Bit#(14)) bLenReg <- mkReg(0);\n   Reg#(Bit#(14)) ii <- mkReg(0);\n   Reg#(Bit#(14)) jj <- mkReg(0);\n   Reg#(Bit#(8)) aData <- mkReg(0);\n   Reg#(Bit#(8)) bData <- mkReg(0);\n   Reg#(Bit#(16)) k1j <- mkReg(0);\n   Reg#(Bit#(16)) k1jm1 <- mkReg(0);\n   Reg#(Bit#(16)) k0j <- mkReg(0);\n   Reg#(Bit#(16)) k0jm1 <- mkReg(0);\n   BRAM1Port#(Bit#(lIndexWidth), Bit#(16)) k0  <- mkBRAM1Server(defaultValue);\n\n/* The original algorithm B uses two vectors K0 and K1 to store two rows of the full L\n * matrix from algoritm A.  For any particular iteration, K[0][j-1] K[0][j]\n * and K[1][j-1] are used to compute K[1][j]\n * \n * Each cycle, K[1] is copied to K[0], and then a new K[1] is computed.  First, the\n * the previous K[0][j] is copied to K[0][j-1] and the previous K[1][j] is copied to\n * K[1][j-1].  Then a new K[1][j] is computed.\n * \n * In the revised version, a single vector is used, plus auxiliary registers.\n * First the old K[0][j] auxiliary is copied to K[0][j-1] and the K[1][j] auxiliary\n * is copied to K[1][j-1].  Then K[0][j] is read. Then K[1][j] is computed <and written> to\n * K[0][j].  When the row is finished, K[0] is effectively K[1]\n *  \n */\n   \n  Stmt hirschB =\n   seq\n      jj <= 17;  // one cycle delay to permit the control registers to get set\n      //$display(\"hirschB running %d %d %d %d dir %d\",\n\t// aStartReg, aLenReg, bStartReg, bLenReg, dir);\n      /* initialize K1 (stored in lMat) of temporary storage */\n      for (jj <= 0; jj <= bLenReg; jj <= jj + 1)\n\t seq\n\t    matL.request.put(BRAMRequest{write: True, responseOnWrite: False, address: rStartReg + zeroExtend(jj), datain: 0});\n\t endseq\n      /* Loop through string a */\n      for (ii <= 1; ii <= aLenReg; ii <= ii + 1)\n\t seq\n\t    //$display(\"hirschB ii = %d\", ii);\n\t    par\n\t       /* initialize pipelining */\n\t       jj <= 1;\n\t       k0j <= 0;\n\t       k1j <= 0;\n\t       action\n\t\t  let idx = ?;\n\t\t  if (dir == 1)\n\t\t     idx = aStartReg + ii - 1;  // 0 to aLen - 1\n\t\t  else\n\t\t     idx = aStartReg + aLenReg - ii;  // aLen-1 downto 0\n\t\t  strA.request.put(BRAMRequest{write: False, responseOnWrite: False, address: idx, datain: ?});\n\t       endaction\n\t       /* Read b[j] */\n\t       action\n\t\t  let idx = ?;\n\t\t  if (dir == 1)\n\t\t     idx = bStartReg;\n\t\t  else\n\t\t     idx = bStartReg + bLenReg - 1;\n\t\t  strB.request.put(BRAMRequest{write: False, responseOnWrite: False, address: idx, datain: ?});\n\t       endaction\n\t       /* start read of k0j */\n\t       matL.request.put(BRAMRequest{write: False, responseOnWrite: False, address: rStartReg + 1, datain: ?});\n\t    endpar\n\t    action\n\t       let ta <- strA.response.get(); /* read a[i] */\n\t       aData <= ta;\n\t    endaction\n\n\t    /* Loop through string B */\n\t    while (jj <= bLenReg)\n\t       seq\n\t\t  //$display(\"hirschB jj = %d\", jj);\n\t\t  action\n\t\t     let tb <- strB.response.get();\n\t\t     let tk <- matL.response.get();\n\t\t     k0jm1 <= k0j;  /* pipeline from previous cycle */\n\t\t     k1jm1 <= k1j;\n\t\t     bData <= tb;   /* read b[j] from bram */\n\t\t     k0j <= tk;     /* read k[0][j] from bram */\n\t\t     matL.request.put(BRAMRequest{write: True, responseOnWrite: False, address: rStartReg + zeroExtend(jj-1), datain: k1j});\n\t\t  endaction\n\t\t  //$display(\"hirschB ii %d jj %d A %h B %h k1j\", ii, jj, aData, bData, k1j);\n\t\t  action\n\t\t     let tmp = ?;\n\t\t     /* Read b[j] */\n\t\t     /* if backwards B[bStartReg + bLenReg - jj] */\n\t\t     action\n\t\t\tlet idx = ?;\n\t\t\tif (dir == 1)\n\t\t\t   idx = bStartReg + jj;\n\t\t\telse\n\t\t\t   idx = bStartReg + bLenReg - jj - 1;\n\t\t\tstrB.request.put(BRAMRequest{write: False, responseOnWrite: False, address: idx, datain: ?});\n\t\t     endaction\n\t\t     if (aData == bData)\n\t\t\ttmp = k0jm1 + 1;\n\t\t     else\n\t\t        tmp = max(k0j,k1jm1);\n\t\t     k1j <= tmp;\n\t\t     jj <= jj + 1;\n\t\t     /* start read of k0j */\n\t\t     matL.request.put(BRAMRequest{write: False, responseOnWrite: False, address: rStartReg + zeroExtend(jj+1), datain: ?});\n\t\t  endaction\n\t\t  //$display(\"     L[%d][%d] = %d \", ii, jj, k1j);\n\t       endseq\n\t    action\n\t       let tb <- strB.response.get();\n\t       let tk <- matL.response.get();\n\t       matL.request.put(BRAMRequest{write: True, responseOnWrite: False, address: rStartReg + zeroExtend(jj-1), datain: k1j});\n\t    endaction\n\t endseq\n   endseq;\n\n   FSM hB <- mkFSM(hirschB);\n   \n   method Action setupA(Bit#(14) start, Bit#(14) length);\n      aStartReg <= start;\n      aLenReg <= length;\n   endmethod\n   \n   method Action setupB(Bit#(14) start, Bit#(14) length);\n      bStartReg <= start;\n      bLenReg <= length;\n   endmethod\n\n   method Action setupL(Bit#(14) start);\n      rStartReg <= start;\n   endmethod\n\n   method Bit#(14) result();\n      return(zeroExtend(bLenReg));\n   endmethod\n   \n   interface FSM fsm = hB;\n\nendmodule\n"
  },
  {
    "path": "contrib/maxcommonsubseq/HirschC.bsv",
    "content": "// Copyright (c) 2014 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\nimport StmtFSM::*;\nimport BRAM::*;\nimport MCSAlgorithm::*;\nimport StackReg::*;\n\n/* frame arguments */\ntypedef struct {\n   Bit#(14) aStart;\n   Bit#(14) bStart;\n   Bit#(14) aLen;\n   Bit#(14) bLen;\n   } CArgs deriving(Bits);\n\ntypedef struct {\n   Bit#(14) midi;\n   Bit#(14) maxj;\n   } CVars deriving(Bits);\n\ntypedef enum {HCSIdle, HCS1, HCS2, HCS3, HCS4, HCS5, HCS6, \n   HCSComplete} HCState deriving (Bits, Eq);\n\n/* Strings A and B are passed in as BRAMs, they are loaded in\n * the caller\n * matL is a bram for the output.  It is Bit#(16) here but it should\n * be Bit#(8) like the strings\n * The forward and backwards Hirsch algorithm B modules are passed in.\n * They share access to the strings, but have their own result matrixes.\n * used here (l0 and l1). \n */\n\n\nmodule mkHirschC#(BRAMServer#(Bit#(strIndexWidth), Bit#(8)) strA, BRAMServer#(Bit#(strIndexWidth), Bit#(8)) strB, BRAMServer#(Bit#(lIndexWidth), Bit#(16)) matL, MCSAlgorithm chirschB0,  MCSAlgorithm chirschB1, BRAMServer#(Bit#(lIndexWidth), Bit#(16)) l0, BRAMServer#(Bit#(lIndexWidth), Bit#(16)) l1)(MCSAlgorithm)\n         provisos(Add#(0, 14, strIndexWidth),\n\t       Add#(0, 14, lIndexWidth));\n\n      /* pc, args, vars */\n   StackReg#(128, HCState, CArgs, CVars) fr <- mkStackReg(128, HCSIdle);\n\n\n   Reg#(Bit#(14)) aStartReg <- mkReg(0);\n   Reg#(Bit#(14)) bStartReg <- mkReg(0);\n   Reg#(Bit#(14)) rStartReg <- mkReg(0);\n   Reg#(Bit#(14)) aLenReg <- mkReg(0);\n   Reg#(Bit#(14)) bLenReg <- mkReg(0);\n   Reg#(Bit#(14)) ii <- mkReg(0);\n   Reg#(Bit#(14)) jj <- mkReg(0);\n   Reg#(Bit#(8)) aData <- mkReg(0);\n   Reg#(Bit#(8)) bData <- mkReg(0);\n   Reg#(Bit#(14)) outcounter <- mkReg(0);\n   Reg#(Bit#(16)) maxjvalue <- mkReg(0);\n\n/*\n * HirschC(Astart, Alen, Bstart, Blen, output fifo)\n * implicit A storage, B storage\n * \n */\n   \n  // This FSM searches string B looking for the first char of string A\n   Stmt hirschC2Stmt =\n   seq\n      //$display(\"hirschC2Stmt running \");\n      // read A[0]\n      strA.request.put(BRAMRequest{write: False, responseOnWrite: False, address: fr.args.aStart, datain: ?});\n      action\n\t let tmp <- strA.response.get();\n\t aData <= tmp;\n      endaction\n      // scan for it in B\n      for (jj <= 0; jj < fr.args.bLen; jj <= jj + 1)\n\t seq\n\t    strB.request.put(BRAMRequest{write: False, responseOnWrite: False, address: fr.args.bStart + jj, datain: ?});\n\t    action\n\t       let tmp <- strB.response.get();\n\t       bData <= tmp;\n\t    endaction\n\t    if (aData == bData)\n\t       seq\n\t\t  //$display(\"output %d\", aData);\n\t\t  matL.request.put(BRAMRequest{write: True, responseOnWrite: False, address: outcounter, datain: zeroExtend(aData)});\n\t\t  outcounter <= outcounter + 1;\n\t\t  break;\n\t       endseq\n\t endseq\n      fr.doreturn();\n   endseq;\n\n   FSM hC2fsm <- mkFSM(hirschC2Stmt);\n   \n   // AlgC step 1, 2, and 3\n   rule hc1 (fr.pc == HCS1);\n      //$display(\"HCS1 aStart %d aLen %d bStart %d bLen %d\", fr.args.aStart, fr.args.aLen, fr.args.bStart, fr.args.bLen);\n      if (fr.args.bLen == 0)\n\tfr.doreturn();\n     else if (fr.args.aLen == 1)\n\tbegin\n\t   hC2fsm.start();\n\t   fr.nextpc(HCS2);\n\tend\n     else\n\taction\n\t   let midi = fr.args.aLen >> 1;\n\t   fr.vars.midi <= midi;\n\t   chirschB1.setupA(fr.args.aStart, midi);\n\t   chirschB1.setupB(fr.args.bStart, fr.args.bLen);\n\t   chirschB0.setupA(fr.args.aStart+midi, fr.args.aLen - midi);\n\t   chirschB0.setupB(fr.args.bStart, fr.args.bLen);\n\t   chirschB0.fsm.start();\n\t   chirschB1.fsm.start();\n\t   fr.nextpc(HCS3);\n\tendaction\n   endrule\n   \n   // This FSM searches the results of the two calls to HirschB\n   Stmt hirschC4Stmt =\n   seq\n      //$display (\"hirschC4A stmt running\");\n      maxjvalue <= 0;\n      fr.vars.maxj <= 0;\n      for (jj <= 0; jj <= fr.args.bLen; jj <= jj + 1)\n\t seq\n\t    l0.request.put(BRAMRequest{write: False, responseOnWrite: False, address: zeroExtend(jj), datain: ?});\n\t    l1.request.put(BRAMRequest{write: False, responseOnWrite: False, address: zeroExtend(fr.args.bLen - jj), datain: ?});\n\t    action\n\t       let t1 <- l0.response.get();\n\t       let t2 <- l1.response.get();\n\t       //$display(\" j %d l0 %d l1 %d, sum %d oldmax %d\",\n\t\t // jj, t1, t2, t1 + t2, maxjvalue);\n\t       if ((t1 + t2) > maxjvalue)\n\t\t  action\n\t\t     maxjvalue <= t1 + t2;\n\t\t     fr.vars.maxj <= jj;\n\t\t  endaction\n\t    endaction\n\t endseq\n      //$display (\"midi %d maxj %d\", fr.vars.midi, fr.vars.maxj);\n      fr.docall(HCS1, HCS5, CArgs {aStart: fr.args.aStart, aLen: fr.vars.midi, bStart: fr.args.bStart, bLen: fr.vars.maxj}, fr.vars);\n   endseq;\n\n   FSM hc4fsm <- mkFSM(hirschC4Stmt);\n   \n   rule hc3 (fr.pc == HCS3 && chirschB0.fsm.done() && chirschB1.fsm.done());\n      //$display(\"HSC3\");\n      hc4fsm.start();\n      fr.nextpc(HCS4);\n   endrule\n   \n   rule hc5 (fr.pc == HCS5);\n      //$display(\"HSC5 aStart %d aLen %d bStart %d bLen %d midi %d maxj %d\",\n\t// fr.args.aStart, fr.args.aLen, fr.args.bStart, fr.args.bLen,\n\t// fr.vars.midi, fr.vars.maxj);\n      fr.docall(HCS1, HCS6, CArgs{aStart: fr.args.aStart + fr.vars.midi, aLen: fr.args.aLen - fr.vars.midi, bStart: fr.args.bStart + fr.vars.maxj, bLen: fr.args.bLen - fr.vars.maxj}, fr.vars);\n   endrule\n   \n   rule hc6 (fr.pc == HCS6);\n      //$display(\"HSC6\");\n      fr.doreturn();\n   endrule\n\n   rule hccomplete (fr.pc == HCSComplete);\n      $display(\"HSCComplete, result size %d\", outcounter);\n      fr.nextpc(HCSIdle);\n   endrule\n   \n   method Action setupA(Bit#(14) start, Bit#(14) length);\n      $display(\"HirschC setupA %d %d\", start, length);\n      aStartReg <= start;\n      aLenReg <= length;\n   endmethod\n   \n   method Action setupB(Bit#(14) start, Bit#(14) length);\n      $display(\"HirschC setupB %d %d\", start, length);\n      bStartReg <= start;\n      bLenReg <= length;\n   endmethod\n\n   method Action setupL(Bit#(14) start);\n      rStartReg <= start;\n   endmethod\n\n   method Bit#(14) result();\n      return(outcounter);\n   endmethod\n\n   \n   interface FSM fsm;\n      method Action start();\n         $display(\"HirschC running aLen %d bLen %d\", aLenReg, bLenReg);\n\t fr.docall(HCS1, HCSComplete, CArgs{aStart: 0, aLen: aLenReg,\n\t    bStart: 0, bLen: bLenReg}, CVars {midi: 0, maxj: 0});\n      endmethod\n      method Bool done();\n\t return(fr.pc == HCSIdle);\n      endmethod\n      method Action waitTillDone();\n      endmethod\n      method Action abort();\n      endmethod\n   endinterface: fsm\n\nendmodule\n"
  },
  {
    "path": "contrib/maxcommonsubseq/MCSAlgorithm.bsv",
    "content": "// Copyright (c) 2014 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\nimport StmtFSM::*;\n\ninterface MCSAlgorithm;\n   method Action setupA (Bit#(14) start, Bit#(14) length);\n   method Action setupB (Bit#(14) start, Bit#(14) length);\n   method Action setupL (Bit#(14) start);\n   method Bit#(14) result();\n   interface FSM fsm;\nendinterface\n\n"
  },
  {
    "path": "contrib/maxcommonsubseq/Makefile",
    "content": "\nCONNECTALDIR?=../..\nINTERFACES = MaxcommonsubseqRequest MaxcommonsubseqIndication\nBSVFILES = Maxcommonsubseq.bsv Top.bsv $(CONNECTALDIR)/lib/deprecated/DmaUtils.bsv\nCPPFILES=testmaxcommonsubseq.cpp\nCONNECTALFLAGS += -I $(CONNECTALDIR)/lib/strstr/cpp\n\ninclude $(CONNECTALDIR)/Makefile.connectal\n"
  },
  {
    "path": "contrib/maxcommonsubseq/Maxcommonsubseq.bsv",
    "content": "// Copyright (c) 2014 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\n\nimport FIFO::*;\nimport FIFOF::*;\nimport SpecialFIFOs::*;\nimport GetPut::*;\nimport StmtFSM::*;\nimport BRAM::*;\nimport Connectable::*;\nimport MCSAlgorithm::*;\nimport ConnectalMemTypes::*;\nimport DmaUtils::*;\nimport Dma2BRAM::*;\n\n// algorithm\nimport HirschA::*;\nimport HirschB::*;\nimport HirschC::*;\n\n\n/* This module solves the maximum common subsequence problem.\n * It finds the longest subsequence of characters present in both input strings\n * the subsequence does not have to be contiguous and the characters can have different locations\n * and offsets in the two strings, just so long as they occur in the same order\n *\n *  To initialize, load string A with request setupA, and wait for indication setup complete\n * Then load string B with request setupB, and wait for indication setup complete\n * To start the unit, signal start, and wait for searchResult, which will tell you the length\n * To retreive the result, use fetch and wait for fetchComplete\n */\n\n/* First pass implements Hirschberg Algorithm A and the fetch call returns the L matrix\n */\ninterface MaxcommonsubseqRequest;\n   method Action setupA(Bit#(32) strPointer, Bit#(32) strOffset, Bit#(32) strLen);\n   method Action setupB(Bit#(32) strPointer, Bit#(32) strOffset, Bit#(32) strLen);\n   method Action fetch(Bit#(32) strPointer, Bit#(32) dest, Bit#(32) src, Bit#(32) strLen);\n   method Action start(Bit#(32) alg);\nendinterface\n\ninterface MaxcommonsubseqIndication;\n   method Action searchResult(Bit#(32) v);\n   method Action setupAComplete(); \n   method Action setupBComplete(); \n   method Action fetchComplete(); \nendinterface\n\ntypedef Bit#(64) DWord;\ntypedef Bit#(32) Word;\n\ntypedef 16384 MaxStringLen;\ntypedef 16384 MaxFetchLen;\ntypedef TLog#(MaxStringLen) StringIdxWidth;\ntypedef Bit#(StringIdxWidth) StringIdx;\ntypedef TLog#(MaxFetchLen) LIdxWidth;\ntypedef Bit#(LIdxWidth) LIdx;\n\nmodule mkMaxcommonsubseqRequest#(MaxcommonsubseqIndication indication,\n\t\t\tMemReadServer#(busWidth)   setupA_read_server,\n\t\t\tMemReadServer#(busWidth)   setupB_read_server,\n\t\t\tMemWriteServer#(busWidth)   fetch_write_server )(MaxcommonsubseqRequest)\n   \n   provisos(Add#(a__, 8, busWidth),\n\t    Div#(busWidth,8,nc),\n\t    Mul#(nc,8,busWidth),\n\t    Add#(1, b__, nc),\n\t    Add#(c__, 32, busWidth),\n\t    Add#(1, d__, TDiv#(busWidth, 32)),\n\t    Mul#(TDiv#(busWidth, 32), 32, busWidth),\n            Mul#(TDiv#(busWidth, 16), 16, busWidth),\n            Add#(1, e__, TDiv#(busWidth, 16)),\n            Add#(1, f__, TMul#(2, TDiv#(busWidth, 16))),\n            Add#(1, h__, busWidth),\n            Add#(TDiv#(busWidth, 16), g__, TMul#(2, TDiv#(busWidth, 16))));\n\n   \n  Reg#(Bit#(14)) aLenReg <- mkReg(0);\n  Reg#(Bit#(14)) bLenReg <- mkReg(0);\n  Reg#(Bit#(14)) rLenReg <- mkReg(0);\n   BRAM2Port#(StringIdx, Bit#(8)) strA  <- mkBRAM2Server(defaultValue);\n   BRAM2Port#(StringIdx, Bit#(8)) strB <- mkBRAM2Server(defaultValue);\n   BRAM2Port#(LIdx, Bit#(16)) matL0 <- mkBRAM2Server(defaultValue);\n   BRAM2Port#(LIdx, Bit#(16)) matL1 <- mkBRAM2Server(defaultValue);\n   BRAM2Port#(LIdx, Bit#(16)) matL <- mkBRAM2Server(defaultValue);\n\n   BRAMReadClient#(StringIdxWidth,busWidth) n2a <- mkBRAMReadClient(strA.portB);\n   mkConnection(n2a.dmaClient, setupA_read_server);\n   BRAMReadClient#(StringIdxWidth,busWidth) n2b <- mkBRAMReadClient(strB.portB);\n   mkConnection(n2b.dmaClient, setupB_read_server);\n   BRAMWriteClient#(LIdxWidth, busWidth) l2n <- mkBRAMWriteClient(matL.portB);\n   mkConnection(l2n.dmaClient, fetch_write_server);\n\n\n   Reg#(Bool) hirschARunning <- mkReg(False);\n   Reg#(Bool) hirschB0Running <- mkReg(False);\n   Reg#(Bool) hirschB1Running <- mkReg(False);\n   Reg#(Bool) hirschCRunning <- mkReg(False);\n\n   MCSAlgorithm hirschA <- mkHirschA(strA.portA, strB.portA, matL.portA);\n   MCSAlgorithm hirschB1 <- mkHirschB(strA.portA, strB.portA, matL.portA, 1);\n   MCSAlgorithm hirschB0 <- mkHirschB(strA.portA, strB.portA, matL.portA, 0);\n   MCSAlgorithm chirschB1 <- mkHirschB(strA.portA, strB.portA, matL0.portA, 1);\n   MCSAlgorithm chirschB0 <- mkHirschB(strA.portA, strB.portA, matL1.portA, 0);\n   MCSAlgorithm hirschC <- mkHirschC(strA.portA, strB.portA, matL.portA, chirschB0, chirschB1, matL0.portB, matL1.portB);\n   // create BRAM Write client for matL\n\n   rule finish_setupA;\n      $display(\"finish setupA\");\n      let x <- n2a.finish;\n      indication.setupAComplete();\n   endrule\n\n   rule finish_setupB;\n      $display(\"finish setupB\");\n      let x <- n2b.finish;\n      indication.setupBComplete();\n   endrule\n\n   rule finish_fetch;\n      $display(\"finish fetch\");\n      let x <- l2n.finish;\n      indication.fetchComplete();\n   endrule\n\n   rule hirschA_completion (hirschARunning && hirschA.fsm.done);\n      hirschARunning <= False;\n      indication.searchResult(pack(zeroExtend(hirschA.result())));\n      endrule\n   \n   rule hirschB0_completion (hirschB0Running && hirschB0.fsm.done);\n      hirschB0Running <= False;\n      indication.searchResult(pack(zeroExtend(hirschB0.result())));\n      endrule\n   \n   rule hirschB1_completion (hirschB1Running && hirschB1.fsm.done);\n      hirschB1Running <= False;\n      indication.searchResult(pack(zeroExtend(hirschB1.result())));\n      endrule\n   \n   rule hirschC_completion (hirschCRunning && hirschC.fsm.done);\n      hirschCRunning <= False;\n      indication.searchResult(pack(zeroExtend(hirschC.result())));\n      endrule\n   \n   \n   method Action setupA(Bit#(32) strPointer, Bit#(32) strOffset, Bit#(32) strLen);\n      aLenReg <= truncate(strLen);\n      $display(\"setupA %h %h %d\", strPointer, strOffset, strLen);\n      n2a.start(strPointer, 0, pack(truncate(strOffset)), pack(truncate(strOffset + strLen-1)));\n      hirschA.setupA(truncate(strOffset), pack(truncate(strLen)));\n      hirschB0.setupA(truncate(strOffset), pack(truncate(strLen)));\n      hirschB1.setupA(truncate(strOffset), pack(truncate(strLen)));\n      hirschC.setupA(truncate(strOffset), pack(truncate(strLen)));\n   endmethod\n\n   method Action setupB(Bit#(32) strPointer, Bit#(32) strOffset, Bit#(32) strLen);\n      bLenReg <= truncate(strLen);\n      $display(\"setupB %h %h %d\", strPointer, strOffset, strLen);\n      n2b.start(strPointer, 0, pack(truncate(strOffset)), pack(truncate(strOffset + strLen-1)));\n      hirschA.setupB(truncate(strOffset), pack(truncate(strLen)));\n      hirschB0.setupB(truncate(strOffset), pack(truncate(strLen)));\n      hirschB1.setupB(truncate(strOffset), pack(truncate(strLen)));\n      hirschC.setupB(truncate(strOffset), pack(truncate(strLen)));\n   endmethod\n   \n   method Action fetch(Bit#(32) strPointer, Bit#(32) dest, Bit#(32) src, Bit#(32) strLen);\n      //rLenReg <= truncate(strLen);\n      $display(\"fetch %h %h %h %h\", strPointer, dest, src, strLen);\n      let bram_start_idx = pack(truncate(src));\n      let bram_finish_idx = bram_start_idx+pack(truncate(strLen-1));\n      l2n.start(strPointer, zeroExtend(dest), bram_start_idx, bram_finish_idx);\n   endmethod\n\n   method Action start(Bit#(32) alg);\n      $display (\"start %d\", alg);\n      case (alg) \n\t 0: begin\n\t       hirschA.setupL(0);\n\t       hirschA.fsm.start();\n\t       hirschARunning <= True;\n\t    end\n\t 1: begin\n\t       hirschB1.fsm.start();\n\t       hirschB1.setupL(0);\n\t       hirschB1Running <= True;\n\t    end\n\t 2: begin\n\t       hirschB0.fsm.start();\n\t       hirschB0.setupL(0);\n\t       hirschB0Running <= True;\n\t    end\n\t 3: begin\n\t       hirschC.setupL(0);\n\t       hirschC.fsm.start();\n\t       hirschCRunning <= True;\n\t    end\n      endcase\n   endmethod\n\nendmodule\n"
  },
  {
    "path": "contrib/maxcommonsubseq/Top.bsv",
    "content": "/* Copyright (c) 2014 Quanta Research Cambridge, Inc\n *\n * Permission is hereby granted, free of charge, to any person obtaining a\n * copy of this software and associated documentation files (the \"Software\"),\n * to deal in the Software without restriction, including without limitation\n * the rights to use, copy, modify, merge, publish, distribute, sublicense,\n * and/or sell copies of the Software, and to permit persons to whom the\n * Software is furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n * DEALINGS IN THE SOFTWARE.\n */\nimport SpecialFIFOs::*;\nimport Vector::*;\nimport StmtFSM::*;\nimport FIFO::*;\nimport CtrlMux::*;\nimport Portal::*;\nimport HostInterface::*;\nimport BlueScope::*;\nimport ConnectalMemory::*;\nimport DmaUtils::*;\nimport ConnectalMemTypes::*;\nimport MemServer::*;\nimport ConnectalMMU::*;\nimport MaxcommonsubseqRequest::*;\nimport MemServerRequest::*;\nimport MMURequest::*;\nimport MaxcommonsubseqIndication::*;\nimport MemServerIndication::*;\nimport MMUIndication::*;\nimport Maxcommonsubseq::*;\n\ntypedef enum {IfcNames_MaxcommonsubseqIndication, IfcNames_MaxcommonsubseqRequest, IfcNames_HostMemServerIndication, IfcNames_HostMemServerRequest, IfcNames_HostMMURequest, IfcNames_HostMMUIndication} IfcNames deriving (Eq,Bits);\ntypedef 1 DegPar;\n\n\nmodule mkConnectalTop(StdConnectalDmaTop#(PhysAddrWidth));\n\n   DmaReadBuffer#(64,1) setupA_read_chan <- mkDmaReadBuffer();\n   DmaReadBuffer#(64,1) setupB_read_chan <- mkDmaReadBuffer();\n   DmaWriteBuffer#(64,1) fetch_write_chan <- mkDmaWriteBuffer();\n   \n   MemReadClient#(64) setupA_read_client = setupA_read_chan.dmaClient;\n   MemReadClient#(64) setupB_read_client = setupB_read_chan.dmaClient;\n   MemWriteClient#(64) fetch_write_client = fetch_write_chan.dmaClient;\n   \n   Vector#(2,  MemReadClient#(64)) readClients;\n   readClients[0] = setupA_read_client;\n   readClients[1] = setupB_read_client;\n\n   Vector#(1, MemWriteClient#(64)) writeClients;\n   writeClients[0] = fetch_write_client;\n\n\n   MMUIndicationProxy hostMMUIndicationProxy <- mkMMUIndicationProxy(IfcNames_HostMMUIndication);\n   MMU#(PhysAddrWidth) hostMMU <- mkMMU(0, True, hostMMUIndicationProxy.ifc);\n   MMURequestWrapper hostMMURequestWrapper <- mkMMURequestWrapper(IfcNames_HostMMURequest, hostMMU.request);\n\n   MemServerIndicationProxy hostMemServerIndicationProxy <- mkMemServerIndicationProxy(IfcNames_HostMemServerIndication);\n   MemServer#(PhysAddrWidth,64,1) dma <- mkMemServer(readClients, writeClients, cons(hostMMU,nil), hostMemServerIndicationProxy.ifc);\n   MemServerRequestWrapper hostMemServerRequestWrapper <- mkMemServerRequestWrapper(IfcNames_HostMemServerRequest, dma.request);\n   \n   MaxcommonsubseqIndicationProxy maxcommonsubseqIndicationProxy <- mkMaxcommonsubseqIndicationProxy(IfcNames_MaxcommonsubseqIndication);\n   MaxcommonsubseqRequest maxcommonsubseqRequest <- mkMaxcommonsubseqRequest(maxcommonsubseqIndicationProxy.ifc, setupA_read_chan.dmaServer, setupB_read_chan.dmaServer, fetch_write_chan.dmaServer);\n   MaxcommonsubseqRequestWrapper maxcommonsubseqRequestWrapper <- mkMaxcommonsubseqRequestWrapper(IfcNames_MaxcommonsubseqRequest,maxcommonsubseqRequest);\n\n   Vector#(6,StdPortal) portals;\n   portals[0] = maxcommonsubseqRequestWrapper.portalIfc;\n   portals[1] = maxcommonsubseqIndicationProxy.portalIfc; \n   portals[2] = hostMemServerRequestWrapper.portalIfc;\n   portals[3] = hostMemServerIndicationProxy.portalIfc; \n   portals[4] = hostMMURequestWrapper.portalIfc;\n   portals[5] = hostMMUIndicationProxy.portalIfc;\n   let ctrl_mux <- mkSlaveMux(portals);\n   \n   interface interrupt = getInterruptVector(portals);\n   interface slave = ctrl_mux;\n   interface masters = dma.masters;\nendmodule\n"
  },
  {
    "path": "contrib/maxcommonsubseq/hirschberg.py",
    "content": "# Copyright (c) 2014 Quanta Research Cambridge, Inc\n#\n# Permission is hereby granted, free of charge, to any person obtaining a\n# copy of this software and associated documentation files (the \"Software\"),\n# to deal in the Software without restriction, including without limitation\n# the rights to use, copy, modify, merge, publish, distribute, sublicense,\n# and/or sell copies of the Software, and to permit persons to whom the\n# Software is furnished to do so, subject to the following conditions:\n#\n# The above copyright notice and this permission notice shall be included\n# in all copies or substantial portions of the Software.\n#\n# THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n# OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n# DEALINGS IN THE SOFTWARE.\n#\n# ASIC project\n# This code implements Hirschberg's longest common subsequence algorithm from\n# CACM June 1975\n# Given strings A and B of lengths m and n, this runs in O(mn) time and O(m + n) space\n# with recursion depth O(lg n)\nfrom __future__ import print_function\n\ntry:\n    xrange\nexcept NameError:\n    xrange = range  # Python 3 compatibility\n\n# compute maximal length subsequence of A and B\n# returns a full matrix L, where L[i][j] is the longest common subsequence in \n# the prefixes A[:i] B[:j] up to L[m][n] which is the answer\n# uses O(mn) time and O(mn) space\n\ndef hirschbergalga(A, B):\n    m = len(A)\n    n = len(B)\n    L = [[0 for j in xrange(n+1)] for i in xrange(m+1)]\n    for i in xrange(1, m+1):\n        L[i][0] = 0\n    for j in xrange(1, n+1):\n        L[0][j] = 0\n    for i in xrange(1, m+1):\n        for j in xrange(1, n+1):\n            if A[i-1]==B[j-1]:\n                L[i][j] = L[i-1][j-1] + 1\n            else:\n                L[i][j] = max(L[i][j-1], L[i-1][j])\n    return L\n\n# should be 2\nhirschbergalga(\"   a b c   \", \"xxbsscee\")\n\n\n# compute the length of the longest common subsequence\n# returns the last row of the L matrix above, namely L[m][j] for j in [0..m]\n# uses O(mn) time and O(n) space.\n# It is prudent to pass B as the shorter argument\ndef hirschbergalgb(A, B):\n    m = len(A)\n    n = len(B)\n    K = [[0 for j in xrange(n+1)] for i in xrange(2)]\n    for i in xrange(1,m+1):\n        for j in xrange(1,n+1):\n            K[0][j] = K[1][j]\n        for j in xrange(1, n+1):\n            if A[i-1]==B[j-1]:\n                K[1][j] = K[0][j-1] + 1\n            else:\n                K[1][j] = max(K[1][j-1], K[0][j])\n    LL = [K[1][j] for j in xrange(n+1)]\n    return(LL)\n\n# returns the actual longest common subsequence, as a string\n# The natural order of execution will return the parts of the answer <in order> so the results\n# could be pushed into a stream or fifo\ndef hirschbergalgc(A, B):\n    print(\"algC \", A, B)\n    m = len(A)\n    n = len(B)\n    if n == 0:\n        return \"\"\n    if m == 1:\n        if A[0] in B:\n            return A\n        else:\n            return \"\"\n    i = m / 2\n    # solve the forward problem, using string prefixes\n    L1 = hirschbergalgb(A[0:i], B)\n    print(\"algB \", \" A \", A[0:i], \" B \", B, \" L1 \", L1)\n    # solve the reverse problem, using string suffixes\n    L2 = hirschbergalgb(A[i:][::-1], B[::-1])\n    print(\"algB \", \" A \", A[i:][::-1], \" B \", B, \" L2 \", L2)\n    # find k, the j at which m is maximized\n    m = -1\n    for j in xrange(n+1):\n        t = L1[j] + L2[n-j];\n        if t > m:\n            m = t\n            k = j\n    # given break points i and k, solve the two subproblems recursively\n    C1 = hirschbergalgc(A[0:i],B[0:k])\n    C2 = hirschbergalgc(A[i:], B[k:])\n    return C1 + C2\n\ndef hirschbergalgc2(sa, sb, A, B):\n    m = len(A)\n    n = len(B)\n    print(\"algC \", \"sa \", sa, \" la \", m, \" sb \", sb, \" lb \", n, A, B)\n    if n == 0:\n        return \"\"\n    if m == 1:\n        if A[0] in B:\n            return A\n        else:\n            return \"\"\n    i = m / 2\n    print(\"m= \", m, \" i = \", i)\n    # solve the forward problem, using string prefixes\n    L1 = hirschbergalgb(A[0:i], B)\n    print(\"algB \", \" A \", A[0:i], \" B \", B, \" L1 \", L1)\n    # solve the reverse problem, using string suffixes\n    L2 = hirschbergalgb(A[i:][::-1], B[::-1])\n    print(\"algB \", \" A \", A[i:][::-1], \" B \", B, \" L2 \", L2)\n    # find k, the j at which m is maximized\n    m = -1\n    for j in xrange(n+1):\n        t = L1[j] + L2[n-j];\n        if t > m:\n            m = t\n            k = j\n    # given break points i and k, solve the two subproblems recursively\n    C1 = hirschbergalgc2(sa, sb, A[0:i],B[0:k])\n    C2 = hirschbergalgc2(sa +i, sb + k, A[i:], B[k:])\n    return C1 + C2\n\n\nstrA = \"___a_____b______c____\"\nstrB = \"..a........b.c....\";    \nstrA = \"012a45678b012345c7890\";\nstrB = \"ABaDEFGHIJKbMcOPQR\";\n    \nhirschbergalgc2(0, 0, strA, strB)\n"
  },
  {
    "path": "contrib/maxcommonsubseq/testmaxcommonsubseq.cpp",
    "content": "/* Copyright (c) 2013 Quanta Research Cambridge, Inc\n *\n * Permission is hereby granted, free of charge, to any person obtaining a\n * copy of this software and associated documentation files (the \"Software\"),\n * to deal in the Software without restriction, including without limitation\n * the rights to use, copy, modify, merge, publish, distribute, sublicense,\n * and/or sell copies of the Software, and to permit persons to whom the\n * Software is furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n * DEALINGS IN THE SOFTWARE.\n */\n#include <assert.h>\n#include <semaphore.h>\n#include <ctype.h>\n#include <ctime>\n#include <monkit.h>\n#include <mp.h>\n#include \"dmaManager.h\"\n#include <sys/types.h>\n#include <sys/stat.h>\n\n#include \"MaxcommonsubseqIndication.h\"\n#include \"MaxcommonsubseqRequest.h\"\n\nsem_t test_sem;\nint result_length;\n\nclass MaxcommonsubseqIndication : public MaxcommonsubseqIndicationWrapper\n{\npublic:\n  MaxcommonsubseqIndication(unsigned int id) : MaxcommonsubseqIndicationWrapper(id){};\n\n  virtual void setupAComplete() {\n    fprintf(stderr, \"setupAComplete\\n\");\n    sem_post(&test_sem);\n  }\n  virtual void setupBComplete() {\n    fprintf(stderr, \"setupBComplete\\n\");\n    sem_post(&test_sem);\n  }\n  virtual void fetchComplete() {\n    fprintf(stderr, \"fetchComplete\\n\");\n    sem_post(&test_sem);\n  }\n  virtual void searchResult (uint32_t v){\n    result_length = v;\n    fprintf(stderr, \"searchResult = %d\\n\", v);\n    sem_post(&test_sem);\n  }\n};\n\n\nint main(int argc, const char **argv)\n{\n  MaxcommonsubseqRequestProxy *device = 0;\n  MaxcommonsubseqIndication *deviceIndication = 0;\n\n  fprintf(stderr, \"%s %s\\n\", __DATE__, __TIME__);\n  device = new MaxcommonsubseqRequestProxy(IfcNames_MaxcommonsubseqRequest);\n    DmaManager *dma = platformInit();\n  deviceIndication = new MaxcommonsubseqIndication(IfcNames_MaxcommonsubseqIndication);\n\n  if(sem_init(&test_sem, 1, 0)){\n    fprintf(stderr, \"failed to init test_sem\\n\");\n    return -1;\n  }\n\n    fprintf(stderr, \"simple tests\\n\");\n    int strAAlloc;\n    int strBAlloc;\n    int fetchAlloc;\n    unsigned int alloc_len = 128;\n    unsigned int fetch_len = alloc_len * alloc_len;\n    int rcA, rcB, rcFetch;\n    struct stat statAbuf, statBbuf, statFetchbuf;\n    \n    fetchAlloc = portalAlloc(fetch_len*sizeof(uint16_t), 0);\n    rcFetch = fstat(fetchAlloc, &statFetchbuf);\n    if (rcA < 0) perror(\"fstatFetch\");\n    int *fetch = (int *)portalMmap(fetchAlloc, fetch_len * sizeof(uint16_t));\n    if (fetch == MAP_FAILED) perror(\"fetch mmap failed\");\n    assert(fetch != MAP_FAILED);\n\n    strAAlloc = portalAlloc(alloc_len, 0);\n    rcA = fstat(strAAlloc, &statAbuf);\n    if (rcA < 0) perror(\"fstatA\");\n    char *strA = (char *)portalMmap(strAAlloc, alloc_len);\n    if (strA == MAP_FAILED) perror(\"strA mmap failed\");\n    assert(strA != MAP_FAILED);\n\n    strBAlloc = portalAlloc(alloc_len, 0);\n    rcB = fstat(strBAlloc, &statBbuf);\n    if (rcA < 0) perror(\"fstatB\");\n    char *strB = (char *)portalMmap(strBAlloc, alloc_len);\n    if (strB == MAP_FAILED) perror(\"strB mmap failed\");\n    assert(strB != MAP_FAILED);\n\n/*\n    const char *strA_text = \"___a_____b______c____\";\n    const char *strB_text = \"..a........b.c....\";\n*/\n    const char *strA_text = \"012a45678b012345c7890\";\n    const char *strB_text = \"ABaDEFGHIJKbMcOPQR\";\n    \n    assert(strlen(strA_text) < alloc_len);\n    assert(strlen(strB_text) < alloc_len);\n\n    strncpy(strA, strA_text, alloc_len);\n    strncpy(strB, strB_text, alloc_len);\n\n    int strA_len = strlen(strA);\n    int strB_len = strlen(strB);\n    uint16_t swFetch[fetch_len];\n\n    portalTimerInit();\n    portalTimerStart(0);\n\n\n    fprintf(stderr, \"elapsed time (hw cycles): %lld\\n\", (long long)portalTimerLap(0));\n    \n    portalCacheFlush(strAAlloc, strA, alloc_len, 1);\n    portalCacheFlush(strBAlloc, strB, alloc_len, 1);\n    portalCacheFlush(fetchAlloc, fetch, fetch_len*sizeof(uint16_t), 1);\n\n    unsigned int ref_strAAlloc = dma->reference(strAAlloc);\n    unsigned int ref_strBAlloc = dma->reference(strBAlloc);\n    unsigned int ref_fetchAlloc = dma->reference(fetchAlloc);\n\n    device->setupA(ref_strAAlloc, 0, strA_len);\n    sem_wait(&test_sem);\n\n    device->setupB(ref_strBAlloc, 0, strB_len);\n    sem_wait(&test_sem);\n\n    uint64_t cycles;\n    uint64_t beats;\n\n    fprintf(stderr, \"starting algorithm A\\n\");\n\n    portalTimerInit();\n    portalTimerStart(0);\n\n    device->start(0);\n    sem_wait(&test_sem);\n    cycles = portalTimerLap(0);\n    beats = hostMemServerIndication->getMemoryTraffic(ChannelType_Read);\n    fprintf(stderr, \"hw cycles: %f\\n\", (float)cycles);\n    device->fetch(ref_fetchAlloc, 0, 0, fetch_len / 2);\n    sem_wait(&test_sem);\n    printf(\"fetch 1 finished \\n\");\n    device->fetch(ref_fetchAlloc, fetch_len, fetch_len / 2, fetch_len / 2);\n    sem_wait(&test_sem);\n    printf(\"fetch 2 finished \\n\");\n\n    memcpy(swFetch, fetch, fetch_len * sizeof(uint16_t));\n    printf(\"        \");\n    for (int j = 0; j <= strB_len; j += 1) {\n      printf(\"%4d\", j);\n    }\n    printf(\"\\n\");\n    printf(\"        \");\n    for (int j = 0; j <= strB_len; j += 1) {\n      printf(\"%4c\", strB[j-1]);\n    }\n    printf(\"\\n\");\n    for (int i = 0; i <= strA_len; i += 1) {\n      printf(\"%4c%4d\", strA[i-1], i);\n      for (int j = 0; j <= strB_len; j += 1) {\n\tprintf(\"%4d\", swFetch[(i << 7) + j] & 0xff);\n      }\n    printf(\"\\n\");\n    }\n\n\n    fprintf(stderr, \"starting algorithm B, forward\\n\");\n    portalTimerInit();\n    portalTimerStart(0);\n\n    device->start(1);\n    sem_wait(&test_sem);\n    cycles = portalTimerLap(0);\n    fprintf(stderr, \"hw cycles: %f\\n\", (float)cycles);\n    device->fetch(ref_fetchAlloc, 0, 0, fetch_len / 2);\n    sem_wait(&test_sem);\n\n    memcpy(swFetch, fetch, fetch_len * sizeof(uint16_t));\n\n    printf(\"        \");\n    for (int j = 0; j <= strB_len; j += 1) {\n      printf(\"%4d\", j);\n    }\n    printf(\"\\n\");\n    printf(\"        \");\n    for (int j = 0; j <= strB_len; j += 1) {\n      printf(\"%4c\", strB[j-1]);\n    }\n    printf(\"\\n\");\n    for (int i = 0; i < 1; i += 1) {\n      printf(\"%4c%4d\", strA[i-1], i);\n      for (int j = 0; j <= strB_len; j += 1) {\n\tprintf(\"%4d\", swFetch[(i << 7) + j] & 0xff);\n      }\n    printf(\"\\n\");\n    }\n\n    /* reverse argument strings */\n    for (int i = 0; i < strA_len; i += 1) {\n      strA[i] = strA_text[strA_len - i - 1];\n    }\n    for (int i = 0; i < strB_len; i += 1) {\n      strB[i] = strB_text[strB_len - i - 1];\n    }\n    device->setupA(ref_strAAlloc, 0, strA_len);\n    sem_wait(&test_sem);\n\n    device->setupB(ref_strBAlloc, 0, strB_len);\n    sem_wait(&test_sem);\n\n    fprintf(stderr, \"starting algorithm B, backward\\n\");\n\n\n\n    portalTimerInit();\n    portalTimerStart(0);\n\n    device->start(2);\n    sem_wait(&test_sem);\n    cycles = portalTimerLap(0);\n    fprintf(stderr, \"hw cycles: %f\\n\", (float)cycles);\n    device->fetch(ref_fetchAlloc, 0, 0, fetch_len / 2);\n    sem_wait(&test_sem);\n\n    memcpy(swFetch, fetch, fetch_len * sizeof(uint16_t));\n\n    printf(\"        \");\n    for (int j = 0; j <= strB_len; j += 1) {\n      printf(\"%4d\", j);\n    }\n    printf(\"\\n\");\n    printf(\"        \");\n    for (int j = 0; j <= strB_len; j += 1) {\n      printf(\"%4c\", strB[j-1]);\n    }\n    printf(\"\\n\");\n    for (int i = 0; i < 1; i += 1) {\n      printf(\"%4c%4d\", strA[i-1], i);\n      for (int j = 0; j <= strB_len; j += 1) {\n\tprintf(\"%4d\", swFetch[(i << 7) + j] & 0xff);\n      }\n    printf(\"\\n\");\n    }\n\n    /* forward argument strings */\n    for (int i = 0; i < strA_len; i += 1) {\n      strA[i] = strA_text[i];\n    }\n    for (int i = 0; i < strB_len; i += 1) {\n      strB[i] = strB_text[i];\n    }\n    device->setupA(ref_strAAlloc, 0, strA_len);\n    sem_wait(&test_sem);\n\n    device->setupB(ref_strBAlloc, 0, strB_len);\n    sem_wait(&test_sem);\n\n\n    fprintf(stderr, \"starting algorithm C\\n\");\n    portalTimerInit();\n    portalTimerStart(0);\n\n    device->start(3);\n    sem_wait(&test_sem);\n    cycles = portalTimerLap(0);\n    fprintf(stderr, \"hw cycles: %f\\n\", (float)cycles);\n    device->fetch(ref_fetchAlloc, 0, 0, fetch_len / 2);\n    sem_wait(&test_sem);\n\n    memcpy(swFetch, fetch, fetch_len * sizeof(uint16_t));\n\n    if (result_length > strB_len) result_length = strB_len;\n    \n    printf(\"Algorithm C results\\n\");\n    for (int j = 0; j < result_length; j += 1) {\n      char c =  swFetch[j] & 0xff;\n      printf(\" %02x (%c)\", 0xff & c, (isalnum(c) ? c: '_'));\n    }\n    printf(\"\\n\");\n\n\n\n    close(strAAlloc);\n    close(strBAlloc);\n    close(fetchAlloc);\n  }\n\n\n"
  },
  {
    "path": "contrib/noc/Makefile",
    "content": "CONNECTALDIR?=../..\nINTERFACES = NocRequest NocIndication\n\nBSVFILES = Noc.bsv Top.bsv\nCPPFILES=testnoc.cpp\n\ninclude $(CONNECTALDIR)/Makefile.connectal\n"
  },
  {
    "path": "contrib/noc/Noc.bsv",
    "content": "// Copyright (c) 2014 Quanta Research Cambridge, Inc.\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\nimport SerialFIFO::*;\nimport NocNode::*;\nimport Connectable::*;\nimport StmtFSM::*;\nimport Vector::*;\nimport FIFOF::*;\nimport Pipe::*;\n\ninterface NocIndication;\n   method Action ack(Bit#(4) recvnode, Bit#(4) to, Bit#(32) message);\nendinterface\n      \ninterface NocRequest;\n   method Action send(Bit#(4) sendnode, Bit#(4) to, Bit#(32) message);\nendinterface\n\n\nmodule mkNocRequest#(NocIndication indication)(NocRequest);\n   \n   SerialFIFO#(DataMessage) xxx <- mkSerialFIFO();\n   Vector#(5, SerialFIFO#(DataMessage)) we <- replicateM( mkSerialFIFO );\n   Vector#(5, SerialFIFO#(DataMessage)) ew <- replicateM( mkSerialFIFO );\n\n   // discard traffic from loose ends\n   rule discardeast;\n      $display(\"we[4] discard %x\", we[4].out.first);\n      we[4].out.deq();\n      endrule\n\n   rule discardwest;\n      $display(\"ew[0] discard %x\", ew[0].out.first);\n      ew[0].out.deq();\n      endrule\n\n   Vector#(4, SerialFIFO#(DataMessage)) node;\n\n    for (Bit#(4) i = 0; i < 4; i = i + 1)\n    begin\n        node[i] <- mkNocNode(unpack(i), \n\t    SerialFIFO {in: ew[i+0].in, out: we[i+0].out},\n\t    SerialFIFO {in: we[i+1].in, out: ew[i+1].out});\n    end\n\n\n  \n  // fsm to read from host ports and generate indications\n\n  Reg#(Bit#(4)) id <- mkReg(0);\n\n  Stmt readindications =\n    seq\n    while(True) seq\n      for(id <= 0; id < 4; id <= id + 1)\n          if (node[id].out.notEmpty())\n\t      seq\n\t\t $display(\"recv at %d to %d m %x\", \n\t\t    id,\n\t\t    node[id].out.first.address,\n\t            node[id].out.first.payload);\n\t\t indication.ack(id, \n\t\t    node[id].out.first.address,\n\t            node[id].out.first.payload);\n\t\t node[id].out.deq();\n              endseq\n      endseq\n    endseq;\n\n    mkAutoFSM(readindications);\n \n   method Action send(Bit#(4) sendnode, Bit#(4) to, Bit#(32) message);\n      $display(\"send f %d t %d m %x\", sendnode, to, message);\n      node[sendnode].in.enq(DataMessage{address: to, payload: message});\n   endmethod\n  \n   \nendmodule\n"
  },
  {
    "path": "contrib/noc/NocNode.bsv",
    "content": "// Copyright (c) 2014 Quanta Research Cambridge, Inc.\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\nimport Connectable::*;\nimport SerialFIFO::*;\nimport FIFOF::*;\nimport Vector::*;\nimport Pipe::*;\nimport Arbiter::*;\n\ntypedef struct {\n   Bit#(4) address;\n   Bit#(32) payload;\n   } DataMessage deriving(Bits);\n\n      \nfunction Action move(PipeOut#(DataMessage) from, PipeIn#(DataMessage) to);\n   return action\n\t     $display(\"move %x\", from.first);\n\t     to.enq(from.first);\n\t     from.deq();\n\t  endaction;\nendfunction\n\n\nmodule mkNocArbitrate#(Bit#(4) id, String name, Vector#(n, PipeOut#(a)) in, PipeIn#(a) out)(Empty);\n   Arbiter_IFC#(n) arb <- mkArbiter(False);   \n   for (Integer i = 0; i < valueOf(n); i = i + 1)\n      rule send_request (out.notFull && in[i].notEmpty);\n\t arb.clients[i].request();\n      endrule\n   \n   rule move;\n      if (out.notFull && in[arb.grant_id].notEmpty)\n\t action\n\t    $display(\"%s id %d from %d\", name, id, arb.grant_id);\n\t    out.enq(in[arb.grant_id].first());\n\t    in[arb.grant_id].deq();\n\t endaction\n   endrule\nendmodule\n\nmodule mkNocNode#(Bit#(4) id, \n\t\t  SerialFIFO#(DataMessage) west,\n\t\t  SerialFIFO#(DataMessage) east)(SerialFIFO#(DataMessage));\n\n   // host Links\n   FIFOF#(DataMessage) fifofromhost <- mkSizedFIFOF(4);\n   FIFOF#(DataMessage) fifotohost <- mkSizedFIFOF(4);\n   SerialFIFO#(DataMessage) host = SerialFIFO{in: toPipeIn(fifotohost),\n\t\t\t\t    out: toPipeOut(fifofromhost)}; \n  \n   // buffers for crossbar switch\n   \n   FIFOF#(DataMessage) he <- mkSizedFIFOF(4);\n   FIFOF#(DataMessage) hw <- mkSizedFIFOF(4);\n   FIFOF#(DataMessage) hh <- mkSizedFIFOF(4);\n   \n   FIFOF#(DataMessage) ew <- mkSizedFIFOF(4);\n   FIFOF#(DataMessage) we <- mkSizedFIFOF(4);\n\n   FIFOF#(DataMessage) eh <- mkSizedFIFOF(4);\n   FIFOF#(DataMessage) wh <- mkSizedFIFOF(4);\n\n   // collate for inputs to host, east, west\n   Vector#(3,PipeOut#(DataMessage)) vToHost = newVector;\n   Vector#(2,PipeOut#(DataMessage)) vToEast = newVector;\n   Vector#(2,PipeOut#(DataMessage)) vToWest = newVector;\n   \n   vToHost[0] = toPipeOut(hh);\n   vToHost[1] = toPipeOut(eh);\n   vToHost[2] = toPipeOut(wh);\n   \n   vToEast[0] = toPipeOut(he);\n   vToEast[1] = toPipeOut(we);\n   \n   vToWest[0] = toPipeOut(hw);\n   vToWest[1] = toPipeOut(ew);\n   \n   mkNocArbitrate(id, \"toHost\", vToHost, host.in);\n   mkNocArbitrate(id, \"toEast\", vToEast, east.in);\n   mkNocArbitrate(id, \"toWest\", vToWest, west.in);\n   \n   // sort host messages to proper queue\n   \n   rule fromhost (host.out.notEmpty);\n      if (host.out.first.address < id)\n\t begin\n\t    $display(\"id %d host to west\", id);\n\t    move(host.out, toPipeIn(hw));\n\t end\n      else if (host.out.first.address == id)\n\t begin\n\t    $display(\"id %d host to host\", id);\n\t    move(host.out, toPipeIn(hh));\n\t end\n      else\n\t begin\n\t    $display(\"id %d host to east\", id);\n\t    move(host.out, toPipeIn(he));\n\t end\n   endrule\n   \n   // Handle arriving messages from East\n   \n   rule fromeast (east.out.notEmpty);\n      if (east.out.first.address == id)\n\t begin\n\t    $display(\"fromeast %d to host v %x\", id, east.out.first);\n\t    move(east.out, toPipeIn(eh));\n\t end\n      else\n\t begin\n\t    $display(\"fromeast %d to west v %x\", id, east.out.first);\n\t    move(east.out, toPipeIn(ew));\n\t end\n   endrule\n   \n   // Handle arriving messages from West\n\n   rule fromwest (west.out.notEmpty);\n      if (west.out.first.address == id)\n\t begin\n\t    $display(\"fromwest %d to host v %x\", id, west.out.first);\n\t    move(west.out, toPipeIn(wh));\n\t end\n      else\n\t begin\n\t    $display(\"fromwest %d  to east v %x\", id, west.out.first);\n\t    move(west.out, toPipeIn(we));\n\t end\n      endrule\n      \n  // interface wiring\n\n   interface PipeIn in = toPipeIn(fifofromhost);\n   interface PipeOut out = toPipeOut(fifotohost);\n\nendmodule\n\n"
  },
  {
    "path": "contrib/noc/Readme.md",
    "content": "Network on Chip\n\nThis example is an extension of the serialconfig scheme to make\nmore of an on-chip network.\n\nThe network is composed of nodes, each of which can send or receive\nmessages.  Point to point links between the nodes complete the design.\n\nStage 1:  1-D mesh\n\nEach node has two links, called East and West, and an address which is\nits coordinate.\n\nEach node therefore has inputs from East, West, and Local. plus three\noutputs to East, West, and Local.  The local link is called \"host\"\n\nThe switch is a 3x3 crossbar, implemented with three three input\nmuxes.  (In the alternative, we could choose not to support loopback\ntraffic, simplifying the switch by 1 leg on the muxes.)\n\nThe Each swith input is a FIFOF.  Each output (row) is a round-robin\narbiter that selects the next message to send from the various inputs.\n\nEach input link has a distributor switch column) rule that routes an \narriving message to the proper swith FIFO.\n\n\nEach link is a SerialFIFO, which is two back-to-back Gearbox modules,\nso the node ends of a link have the DataMessage type, while the \"middle\" of\nthe link is serial (a 1-bit wide FIFO, really).\n\nTest Program\n\nThe test program sends a message from each node to each other node\n"
  },
  {
    "path": "contrib/noc/Top.bsv",
    "content": "// Copyright (c) 2014 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\nimport Vector::*;\nimport FIFO::*;\nimport Connectable::*;\nimport Portal::*;\nimport HostInterface::*;\nimport CtrlMux::*;\nimport NocIndication::*;\nimport NocRequest::*;\nimport Noc::*;\n\ntypedef enum {IfcNames_NocIndication, IfcNames_NocRequest} IfcNames deriving (Eq,Bits);\n\nmodule mkConnectalTop(StdConnectalTop#(PhysAddrWidth));\n\n   // instantiate user portals\n   NocIndicationProxy nocIndicationProxy <- mkNocIndicationProxy(IfcNames_NocIndication);\n   NocRequest nocRequest <- mkNocRequest(nocIndicationProxy.ifc);\n   NocRequestWrapper nocRequestWrapper <- mkNocRequestWrapper(IfcNames_NocRequest,nocRequest);\n   \n   Vector#(2,StdPortal) portals;\n   portals[0] = nocRequestWrapper.portalIfc; \n   portals[1] = nocIndicationProxy.portalIfc;\n   let ctrl_mux <- mkSlaveMux(portals);\n   \n   interface interrupt = getInterruptVector(portals);\n   interface slave = ctrl_mux;\n   interface masters = nil;\nendmodule : mkConnectalTop\n"
  },
  {
    "path": "contrib/noc/testnoc.cpp",
    "content": "/* Copyright (c) 2013 Quanta Research Cambridge, Inc\n *\n * Permission is hereby granted, free of charge, to any person obtaining a\n * copy of this software and associated documentation files (the \"Software\"),\n * to deal in the Software without restriction, including without limitation\n * the rights to use, copy, modify, merge, publish, distribute, sublicense,\n * and/or sell copies of the Software, and to permit persons to whom the\n * Software is furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n * DEALINGS IN THE SOFTWARE.\n */\n\n#include <stdio.h>\n#include <sys/mman.h>\n#include <stdlib.h>\n#include <unistd.h>\n#include <assert.h>\n#include <semaphore.h>\n#include <ctime>\n#include <monkit.h>\n#include <sys/types.h>\n#include <sys/stat.h>\n\n#include \"NocIndication.h\"\n#include \"NocRequest.h\"\n#include \"GeneratedTypes.h\"\n\nsem_t test_sem;\n\nuint32_t lastheardby;\nuint32_t lastto;\nuint32_t lastmsg;\n\n  NocRequestProxy *dev = 0;\n\nclass NocIndication : public NocIndicationWrapper\n{\npublic:\n  NocIndication(unsigned int id) : NocIndicationWrapper(id){};\n\n  virtual void ack(uint32_t heardby, uint32_t to, uint32_t msg) {\n    fprintf(stderr, \"ack h %d t %d msg %08x\\n\", heardby, to, msg);\n    lastheardby = heardby;\n    lastto = to;\n    lastmsg = msg;\n    sem_post(&test_sem);\n  }\n};\n\nvoid lastheardbyshouldbe(uint32_t heardby)\n{\n  if (lastheardby != heardby)\n    printf(\"error, expected data %08x got %08x\\n\", heardby, lastheardby);\n}\n\nvoid lastmsgshouldbe(uint32_t msg)\n{\n  if (lastmsg != msg)\n    printf(\"error, expected data %08x got %08x\\n\", msg, lastmsg);\n}\n\nvoid lasttoshouldbe(uint32_t to)\n{\n  if (lastto != to)\n    printf(\"error, expected to address %08x got %08x\\n\", to, lastto);\n}\n\nvoid dosend(uint32_t from, uint32_t to, uint32_t msg)\n{\n  dev->send(from, to, msg);\n  sem_wait(&test_sem);\n  lastheardbyshouldbe(to);\n  lasttoshouldbe(to);\n  lastmsgshouldbe(msg);\n}\n\nvoid dotest()\n{\n  uint32_t from, to, msg;\n  for (from = 0; from < 4; from += 1) {\n    for (to = 0; to < 4; to += 1) {\n      printf(\"send from %d to %d v %08x\\n\", from, to, (from << 16) + to);\n      dosend(from, to, (from << 16) + to);\n    }\n  }\n}\n\nint main(int argc, const char **argv)\n{\n  \n  NocIndication *deviceIndication = 0;\n\n  fprintf(stderr, \"%s %s\\n\", __DATE__, __TIME__);\n  dev = new NocRequestProxy(IfcNames_NocRequest);\n\n  deviceIndication = new NocIndication(IfcNames_NocIndication);\n\n  if(sem_init(&test_sem, 1, 0)){\n    fprintf(stderr, \"failed to init test_sem\\n\");\n    return -1;\n  }\n\n    fprintf(stderr, \"simple tests\\n\");\n    \n    dotest();\n}\n"
  },
  {
    "path": "contrib/noc2d/Makefile",
    "content": "CONNECTALDIR?=../..\nINTERFACES = NocRequest NocIndication\n\nBSVFILES = Noc2d.bsv Top.bsv\nCPPFILES=testnoc2d.cpp\n\ninclude $(CONNECTALDIR)/Makefile.connectal\n"
  },
  {
    "path": "contrib/noc2d/Noc2d.bsv",
    "content": "// Copyright (c) 2014 Quanta Research Cambridge, Inc.\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\nimport SerialFIFO::*;\nimport NocNode::*;\nimport Connectable::*;\nimport StmtFSM::*;\nimport Vector::*;\nimport FIFOF::*;\nimport Pipe::*;\n\ninterface NocIndication;\n   method Action ack(Bit#(8) recvnode, Bit#(8) to, Bit#(32) message);\nendinterface\n      \ninterface NocRequest;\n   method Action send(Bit#(8) sendnode, Bit#(8) to, Bit#(32) message);\nendinterface\n\nmodule mkPipeOutDiscard#(PipeOut#(Bit#(1)) x)(Empty);\n   rule toss;\n      x.deq();\n   endrule\nendmodule\n\n\n\nmodule mkNocRequest#(NocIndication indication)(NocRequest);\n   \n  \n   Vector#(4, Vector#(4, NocNode#(2))) node = replicate(newVector);\n\n   for (Bit#(4) x = 0; x < 4; x = x + 1)\n      for (Bit#(4) y = 0; y < 4; y = y + 1)\n\t begin\n\t    Vector#(2, Bit#(4)) id = newVector;\n\t    id[0] = x;\n\t    id[1] = y;\n\t    node[x][y] <- mkNocNode(id);\n\t end\n\n   // wire up the links in the x direction\n   Vector#(3, Integer) indexes3 = genVector();\n   Vector#(4, Integer) indexes4 = genVector();\n   module mkXLinks#(Integer x)(Empty);\n      module mkXLink#(Integer x, Integer y)(Empty);\n\t mkConnection(node[x][y].linkupout[0], node[x+1][y].linkdownin[0]);\n\t mkConnection(node[x+1][y].linkdownout[0], node[x][y].linkupin[0]);\n      endmodule\n      mapM_(mkXLink(x), indexes4);\n   endmodule\n\n   mapM_(mkXLinks, indexes3);\n\n   // wire up the links in the y direction\n   \n   module mkYLinks#(Integer y)(Empty);\n   module mkYLink#(Integer y, Integer x)(Empty);\n      mkConnection(node[x][y].linkupout[1], node[x][y+1].linkdownin[1]);\n      mkConnection(node[x][y+1].linkdownout[1], node[x][y].linkupin[1]);\n   endmodule\n      mapM_(mkYLink(y), indexes4);\n   endmodule\n   mapM_(mkYLinks, indexes3);\n\n   // discard traffic from loose ends in y direction\n   for (Bit#(4) x = 0; x < 4; x = x + 1)\n      begin\n\t mkPipeOutDiscard(node[x][0].linkdownout[1]);\n\t mkPipeOutDiscard(node[x][3].linkupout[1]);\n      end\n   // discard traffic from loose ends in x direction\n   for (Bit#(4) y = 0; y < 4; y = y + 1)\n      begin\n\t mkPipeOutDiscard(node[0][y].linkdownout[0]);\n\t mkPipeOutDiscard(node[3][y].linkupout[0]);\n      end\n   \n  // fsm to read from host ports and generate indications\n\n  Reg#(Bit#(4)) idx <- mkReg(0);\n  Reg#(Bit#(4)) idy <- mkReg(0);\n\n  Stmt readindications =\n    seq\n    while(True) seq\n      for(idx <= 0; idx < 4; idx <= idx + 1)\n\t for(idy <= 0; idy < 4; idy <= idy + 1)\n            if (node[idx][idy].nodetohost.notEmpty())\n\t      seq\n\t\t $display(\"recv at [%d,%d] to [%d,%d] m %x\", \n\t\t    idx,idy,\n\t\t    node[idx][idy].nodetohost.first.address[0],\n\t\t    node[idx][idy].nodetohost.first.address[1],\n\t            node[idx][idy].nodetohost.first.payload);\n\t\t indication.ack((zeroExtend(idx)<<4) + zeroExtend(idy), \n\t\t    (zeroExtend(node[idx][idy].nodetohost.first.address[0])<<4)+\n\t\t    zeroExtend(node[idx][idy].nodetohost.first.address[1]),\n\t            node[idx][idy].nodetohost.first.payload);\n\t\t node[idx][idy].nodetohost.deq();\n              endseq\n      endseq\n    endseq;\n\n    mkAutoFSM(readindications);\n \n   method Action send(Bit#(8) sendnode, Bit#(8) to, Bit#(32) message);\n      Vector#(2,Bit#(4)) id = newVector;\n      Vector#(2,Bit#(4)) dest = newVector;\n      id[0] = sendnode[7:4];\n      id[1] = sendnode[3:0];\n      dest[0] = to[7:4];\n      dest[1] = to[3:0];\n      $display(\"send f %x t %x m %x\", sendnode, to, message);\n      node[id[0]][id[1]].hosttonode.enq(DataMessage{address: dest, payload: message});\n   endmethod\n  \n   \nendmodule\n"
  },
  {
    "path": "contrib/noc2d/NocNode.bsv",
    "content": "// Copyright (c) 2014 Quanta Research Cambridge, Inc.\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\nimport Connectable::*;\nimport SerialFIFO::*;\nimport FIFOF::*;\nimport Vector::*;\nimport Pipe::*;\nimport Arbiter::*;\n\ntypedef struct {\n   Vector#(2, Bit#(4)) address;\n   Bit#(32) payload;\n   } DataMessage deriving(Bits);\n\ninterface NocNode#(numeric type dim);\n   interface PipeIn#(DataMessage) hosttonode;\n   interface PipeOut#(DataMessage) nodetohost;\n   interface Vector#(dim, PipeIn#(Bit#(1))) linkupin;\n   interface Vector#(dim, PipeOut#(Bit#(1))) linkupout;\n   interface Vector#(dim, PipeIn#(Bit#(1))) linkdownin;\n   interface Vector#(dim, PipeOut#(Bit#(1))) linkdownout;\nendinterface\n\t \nfunction PipeOut#(Bit#(1)) selectoutput(SerialFIFOTX#(DataMessage) x);\n   return x.out;\nendfunction\n\nfunction PipeIn#(Bit#(1)) selectinput(SerialFIFORX#(DataMessage) x);\n   return x.in;\nendfunction\n\nfunction Action move(PipeOut#(DataMessage) from, PipeIn#(DataMessage) to);\n   return action\n\t     $display(\"move %x\", from.first);\n\t     to.enq(from.first);\n\t     from.deq();\n\t  endaction;\nendfunction\n\n\nmodule mkNocArbitrate#(Vector#(n, Bit#(4)) id, Bit#(4) outlink, Vector#(r, PipeOut#(a)) in, PipeIn#(a) out)(Empty)\n/*   provisos(\n      Add#(0,n,2),\n      Add#(0,r,5)\n      ) */ ;\n   Arbiter_IFC#(r) arb <- mkArbiter(False);   \n   for (Integer i = 0; i < valueOf(r); i = i + 1)\n      rule send_request (out.notFull && in[i].notEmpty);\n\t arb.clients[i].request();\n      endrule\n   \n   rule move;\n      if (out.notFull && in[arb.grant_id].notEmpty)\n\t action\n\t    $display(\"arb id [%d,%d] link %d from %d\", id[0], id[1], outlink, arb.grant_id);\n\t    out.enq(in[arb.grant_id].first());\n\t    in[arb.grant_id].deq();\n\t endaction\n   endrule\nendmodule\n\nmodule mkDistributor#(Vector#(n, Bit#(4)) id, PipeOut#(DataMessage) in, Vector#(r, PipeIn#(DataMessage)) out)(Empty)\n/*    provisos(\n      Add#(0,n,2),\n      Add#(0,r,5)\n      ) */\n;\n   rule move;\n      $display(\"distrib [%d,%d] to [%d,%d] v %x\",\n\t id[0], id[1], in.first.address[0], in.first.address[1],\n\t in.first.payload);\n      if (in.first.address[0] < id[0]) \n\t begin\n\t    $display(\" to link 1\");\n\t    move(in, out[1]);\n\t end\n      else if (in.first.address[0] > id[0]) \n\t begin\n\t    $display(\" to link 0\");\n\t    move(in, out[0]);\n\t end\n      else /* in.first.address[0] == id[0] */\n\t begin\n\t    if (in.first.address[1] < id[1]) \n\t       begin\n\t\t  $display(\" to link 3\");\n\t\t  move (in, out[3]);\n\t       end\n\t    else if (in.first.address[1] > id[1]) \n\t       begin\n\t\t  $display(\" to link 2\");\n\t\t  move (in, out[2]);\n\t       end\n\t    else\n\t       begin\n\t\t  $display(\" to link 4\");\n\t\t  move(in, out[4]);\n\t       end\n\t end\n   endrule\nendmodule\n\n// This makes a FIFO which throws away data and is never ready to read\nmodule mkDiscard(FIFOF#(DataMessage));\n   method Action enq(DataMessage d);\n   endmethod\n   method Bool notFull;\n      return True;\n   endmethod\n   method DataMessage first() = ?;\n   method Bool notEmpty();\n      return False;\n   endmethod\n   method Action deq;\n      if (False) noAction;\n   endmethod\n   method Action clear = ?;\nendmodule\n\ntypedef 2 NumDims;\n(* synthesize *)\nmodule mkNocNode#(Vector#(NumDims, Bit#(4)) id)(NocNode#(NumDims));\n   Integer radix = (valueOf(NumDims) * 2) + 1;\n\n   // host Links\n   FIFOF#(DataMessage) fifofromhost <- mkSizedFIFOF(4);\n   FIFOF#(DataMessage) fifotohost <- mkSizedFIFOF(4);\n   PipeIn#(DataMessage) tohost = toPipeIn(fifotohost);\n   PipeOut#(DataMessage) fromhost = toPipeOut(fifofromhost); \n  \n   Vector#(NumDims, SerialFIFOTX#(DataMessage)) txup <- replicateM(mkSerialFIFOTX);\n   Vector#(NumDims, SerialFIFORX#(DataMessage)) rxup <- replicateM(mkSerialFIFORX);\n   Vector#(NumDims, SerialFIFOTX#(DataMessage)) txdown <- replicateM(mkSerialFIFOTX);\n   Vector#(NumDims, SerialFIFORX#(DataMessage)) rxdown <- replicateM(mkSerialFIFORX);\n\t \n\t \n   // sources\n   Vector#(TAdd#(TMul#(NumDims, 2), 1), PipeOut#(DataMessage)) switchin = newVector;\n   Vector#(TAdd#(TMul#(NumDims, 2), 1), PipeIn#(DataMessage)) switchout = newVector;\n   // buffers for crossbar switch\n   Vector#(TAdd#(TMul#(NumDims, 2), 1), Vector#(TAdd#(TMul#(NumDims, 2), 1), FIFOF#(DataMessage))) xp = replicate(newVector);\n   // temps for building switch\n   Vector#(TAdd#(TMul#(NumDims, 2), 1), PipeIn#(DataMessage)) tmpin = newVector;\n   Vector#(TAdd#(TMul#(NumDims, 2), 1), PipeOut#(DataMessage)) tmpout = newVector;\n\n\n   for (Integer i = 0; i < valueOf(NumDims); i = i + 1)\n      begin\n\t switchin[(2*i) + 0] = rxup[i].out;\n\t switchin[(2*i) + 1] = rxdown[i].out;\n\t switchout[(2*i) + 0] = txup[i].in;\n\t switchout[(2*i) + 1] = txdown[i].in;\n      end\n   switchin[radix - 1] = fromhost;\n   switchout[radix - 1] = tohost;\n   \n\n   for (Integer x = 0; x < radix; x = x + 1)\n      for (Integer y = 0; y < radix; y = y + 1)\n\t if (x != y) xp[x][y] <- mkSizedFIFOF(4);\n\n   for (Integer x = 0; x < (radix - 1); x = x + 1)\n      xp[x][x] <- mkDiscard();\n   \n   xp[radix - 1][radix - 1] <- mkSizedFIFOF(4);\n   \n   // create distributors\n   \n   for (Integer x = 0; x < radix; x = x + 1)\n      begin\n\t for (Integer y = 0; y < radix; y = y + 1)\n\t    tmpin[y] = toPipeIn(xp[x][y]);\n\t mkDistributor(id, switchin[x], tmpin);\n      end\n   // create arbiters\n   for (Integer y = 0; y < radix; y = y + 1)\n      begin\n\t for (Integer x = 0; x < radix; x = x + 1)\n\t    tmpout[x] = toPipeOut(xp[x][y]);\n\t mkNocArbitrate(id, fromInteger(y), tmpout, switchout[y]);\n      end\n\n  // interface wiring\n\n   interface PipeIn hosttonode = toPipeIn(fifofromhost);\n   interface PipeOut nodetohost = toPipeOut(fifotohost);\n   interface Vector linkupin = map(selectinput, rxup);\n   interface Vector linkupout = map(selectoutput, txup);\n   interface Vector linkdownin = map(selectinput, rxdown);\n   interface Vector linkdownout = map(selectoutput, txdown);\n\nendmodule\n\n"
  },
  {
    "path": "contrib/noc2d/Readme.md",
    "content": "Network on Chip\n\nThis is a two dimensional mesh network with 16 nodes.\n\nEach node has four links to adjacent nodes, plus a link to the local\n\"host\". Each node has a crossbar switch for routing.\n\nMessages are a compiled-in datatype, plus a message address which is\nthe coordinates of the destination host in the X and Y directions.\n\nLinks are SerialFIFOs, from the connectal library.  The link \"transmitter\"\nis a GearBox from the message datatype to a Bit#(1) serial datatype.\nThe link \"receiver\" is a Gearbox from Bit#(1) back to the message\ndatatype.\n\n\nThe crossbar switch consists of a matrix of FIFOF.  A particular FIFO\naccepts messages from a particular input link which are routed to a\nparticular output link.\n\nThe four input links, plus a FIFO from the host, feed distributors.\nEach distributor examines the address of a message and copies the\nmessage to the correct crosspoint FIFO.\n\nA \"row\" in the crossbar consists of all the FIFOs which accept traffic\nfrom a particular link plus a row for messages from the host.  A\n\"column\" in the crossbar consists of all the FIFOs which send traffic\nto a particular link, plus a column for traffic to the host.\n\nEach output link has an arbiter, which merges traffic from the\nassociated FIFOs.\n\nIn order to avoid deadlock, the network uses dimension order routing.\nA message traverses links in the X direction until it reaches the\ncorrect X coordinate, and then traverses links in the Y direction\nuntil the Y coordinates match. The message is then delivered to the\nhost.\n\nA message can never be routed back to the node from which it just\narrived, so there are no FIFOs needed on the diagonal of the switch\nmatrix.  There is a crosspoint to route host messages back to the\nlocal host.\n"
  },
  {
    "path": "contrib/noc2d/Top.bsv",
    "content": "// Copyright (c) 2014 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\nimport Vector::*;\nimport FIFO::*;\nimport Connectable::*;\nimport Portal::*;\nimport HostInterface::*;\nimport CtrlMux::*;\nimport NocIndication::*;\nimport NocRequest::*;\nimport Noc2d::*;\n\ntypedef enum {IfcNames_NocIndication, IfcNames_NocRequest} IfcNames deriving (Eq,Bits);\n\nmodule mkConnectalTop(StdConnectalTop#(PhysAddrWidth));\n   NocIndicationProxy nocIndicationProxy <- mkNocIndicationProxy(IfcNames_NocIndication);\n   NocRequest nocRequest <- mkNocRequest(nocIndicationProxy.ifc);\n   NocRequestWrapper nocRequestWrapper <- mkNocRequestWrapper(IfcNames_NocRequest,nocRequest);\n   \n   Vector#(2,StdPortal) portals;\n   portals[0] = nocRequestWrapper.portalIfc; \n   portals[1] = nocIndicationProxy.portalIfc;\n   let ctrl_mux <- mkSlaveMux(portals);\n   \n   interface interrupt = getInterruptVector(portals);\n   interface slave = ctrl_mux;\n   interface masters = nil;\nendmodule : mkConnectalTop\n"
  },
  {
    "path": "contrib/noc2d/testnoc2d.cpp",
    "content": "/* Copyright (c) 2013 Quanta Research Cambridge, Inc\n *\n * Permission is hereby granted, free of charge, to any person obtaining a\n * copy of this software and associated documentation files (the \"Software\"),\n * to deal in the Software without restriction, including without limitation\n * the rights to use, copy, modify, merge, publish, distribute, sublicense,\n * and/or sell copies of the Software, and to permit persons to whom the\n * Software is furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n * DEALINGS IN THE SOFTWARE.\n */\n\n#include <stdio.h>\n#include <sys/mman.h>\n#include <stdlib.h>\n#include <unistd.h>\n#include <assert.h>\n#include <semaphore.h>\n#include <ctime>\n#include <monkit.h>\n#include <sys/types.h>\n#include <sys/stat.h>\n\n#include \"NocIndication.h\"\n#include \"NocRequest.h\"\n#include \"GeneratedTypes.h\"\n\nsem_t test_sem;\n\nuint32_t lastheardby;\nuint32_t lastto;\nuint32_t lastmsg;\n\n  NocRequestProxy *dev = 0;\n\nclass NocIndication : public NocIndicationWrapper\n{\npublic:\n  NocIndication(unsigned int id) : NocIndicationWrapper(id){};\n\n  virtual void ack(uint32_t heardby, uint32_t to, uint32_t msg) {\n    fprintf(stderr, \"ack h [%d.%d] t [%d.%d] msg %08x\\n\", \n\t    (heardby >> 4) & 0x0f, heardby & 0xf, \n\t    (to >> 4) & 0xf, to & 0xf, \n\t    msg);\n    lastheardby = heardby;\n    lastto = to;\n    lastmsg = msg;\n    sem_post(&test_sem);\n  }\n};\n\nvoid lastheardbyshouldbe(uint32_t heardby)\n{\n  if (lastheardby != heardby)\n    printf(\"error, expected data %08x got %08x\\n\", heardby, lastheardby);\n}\n\nvoid lastmsgshouldbe(uint32_t msg)\n{\n  if (lastmsg != msg)\n    printf(\"error, expected data %08x got %08x\\n\", msg, lastmsg);\n}\n\nvoid lasttoshouldbe(uint32_t to)\n{\n  if (lastto != to)\n    printf(\"error, expected to address %08x got %08x\\n\", to, lastto);\n}\n\nvoid dosend(uint32_t from, uint32_t to, uint32_t msg)\n{\n  dev->send(from, to, msg);\n  sem_wait(&test_sem);\n  lastheardbyshouldbe(to);\n  lasttoshouldbe(to);\n  lastmsgshouldbe(msg);\n}\n\nvoid dotest()\n{\n  uint32_t fromx, fromy, tox, toy, msg;\n  for (fromx = 0; fromx < 4; fromx += 1) {\n    for (fromy = 0; fromy < 4; fromy += 1) {\n      for (tox = 0; tox < 4; tox += 1) {\n\tfor (toy = 0; toy < 4; toy += 1) {\n\t  printf(\"send from [%d.%d] to [%d.%d] v %08x\\n\", fromx, fromy, tox, toy, (fromx << 20) + (fromy << 16) + (tox << 4) + toy);\n\t  dosend((fromx << 4) + fromy, (tox << 4) + toy, (fromx << 20) + (fromy << 16) + (tox << 4) + toy);\n\t}\n      }\n    }\n  }\n}\n\nint main(int argc, const char **argv)\n{\n  \n  NocIndication *deviceIndication = 0;\n\n  fprintf(stderr, \"%s %s\\n\", __DATE__, __TIME__);\n  dev = new NocRequestProxy(IfcNames_NocRequest);\n\n  deviceIndication = new NocIndication(IfcNames_NocIndication);\n\n  if(sem_init(&test_sem, 1, 0)){\n    fprintf(stderr, \"failed to init test_sem\\n\");\n    return -1;\n  }\n\n    fprintf(stderr, \"simple tests\\n\");\n    dotest();\n}\n"
  },
  {
    "path": "contrib/parallella/ELink.bsv",
    "content": "// Copyright (c) 2015 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\n// This file is a hand-generated file that we hope will someday be\n// generated automatically by connectal/generated/scripts/importbvi.py\n//\n// Created by copying the style of connectal/generated/xilinx/PPS7LIB.bsv\n\nimport Clocks::*;\nimport DefaultValue::*;\nimport XilinxCells::*;\nimport GetPut::*;\nimport AxiBits::*;\n\n\n// The name of this interface is a prefix \"Par_\" plus the common \n// prefix of the signals \"tx\"\n// Hopefully this is what importbvi.py would do\n(* always_ready, always_enabled *)\ninterface Par_tx;\n   method Action data_p(Bit#(8) v);\n   method Action data_n(Bit#(8) v);\n   method Action frame_p(Bit#(1) v);\n   method Action frame_n(Bit#(1) v);\n   method Action lclk_p(Bit#(1) v);\n   method Action lclk_n(Bit#(1) v);\n   method Bit#(1) wr_wait_p();\n   method Bit#(1) wr_wait_n();\n   method Bit#(1) rd_wait_p();\n   method Bit#(1) rd_wait_n();\nendinterface\n\n(* always_ready, always_enabled *)\ninterface Par_rx;\n   method Bit#(8) data_p();\n   method Bit#(8) data_n();\n   method Bit#(1) frame_p();\n   method Bit#(1) frame_n();\n   method Bit#(1) lclk_p();\n   method Bit#(1) lclk_n();\n   method Action wr_wait_p(Bit#(1) v);\n   method Action wr_wait_n(Bit#(1) v);\n   method Action rd_wait_p(Bit#(1) v);\n   method Action rd_wait_n(Bit#(1) v);\nendinterface\n\n(* always_ready, always_enabled *)\ninterface Par_misc;\n   method Bit#(1) csysack();\n   method Bit#(1) cactive();\n   method Action csysreq(Bit#(1) v);\n   method Bit#(1) reset_chip();\n   method Bit#(1) reset_fpga();\n   method Action cclk_p(Bit#(1) v);\n   method Action cclk_n(Bit#(1) v);\nendinterface\n\ntypedef AxiMasterBits#(32,64,6,Empty) ParSaxiHp;\ntypedef AxiSlaveBits#(32,32,12,Empty) ParMaxiGp;\n\n(* always_ready, always_enabled *)\ninterface ELink;\n   interface Par_tx tx;\n   interface Par_rx rx;\n   interface ParMaxiGp maxi;   // this will connect to a master\n   interface ParSaxiHp saxi;  // this will connect to a slave\n   interface Par_misc misc;\nendinterface\n\nimport \"BVI\" elink =\nmodule mkELink#(Clock maxiclk, Clock saxiclk, \n   Reset maxiclk_reset, Reset saxiclk_reset,\n   Reset maxireset, Reset saxireset,\n   Reset reset_chip, Reset reset_fpga)(ELink);\n   // default_clock clk();\n   // default_reset rst();\n   input_clock maxiclk(emaxi_aclk) = maxiclk;  // assigns the verilog emaxi_aclk\n   input_clock saxiclk(s_axi_aclk) = saxiclk;  // assigns the verilog s_axi_aclk\n   input_reset maxiclk_reset() = maxiclk_reset; /* from clock*/\n   input_reset saxiclk_reset() = saxiclk_reset; /* from clock*/\n   input_reset maxireset() = maxireset;\n   input_reset saxireset() = saxireset;\n   \n   interface Par_misc misc;\n      method csysack csysack();\n      method cactive cactive();\n      method reset_chip reset_chip();\n      method reset_fpga reset_fpga();\n      method csysreq(csysreq) enable((*inhigh*) EN_csysreq);\n      method cclk_p(cclk_p) enable((*inhigh*) EN_cclk_p);\n      method cclk_n(cclk_n) enable((*inhigh*) EN_cclk_n);\n   endinterface\n   \n   interface Par_tx tx;\n      method data_p(tx_data_p) enable((*inhigh*) EN_tx_data_p);\n      method data_n(tx_data_n) enable((*inhigh*) EN_tx_data_n);\n      method frame_p(tx_frame_p) enable((*inhigh*) EN_tx_frame_p);\n      method frame_n(tx_frame_n) enable((*inhigh*) EN_tx_frame_n);\n      method lclk_p(tx_lclk_p) enable((*inhigh*) EN_tx_lclk_p);\n      method lclk_n(tx_lclk_n) enable((*inhigh*) EN_tx_lclk_n);\n      method tx_wr_wait_p wr_wait_p();\n      method tx_wr_wait_n wr_wait_n();\n      method tx_rd_wait_p rd_wait_p();\n      method tx_rd_wait_n rd_wait_n();\n   endinterface\n\n   interface Par_rx rx;\n      method rx_data_p data_p();\n      method rx_data_n data_n();\n      method rx_frame_p frame_p();\n      method rx_frame_n frame_n();\n      method rx_lclk_p lclk_p();\n      method rx_lclk_n lclk_n();\n      method wr_wait_p(rx_wr_wait_p) enable((*inhigh*) EN_rx_wr_wait_p);\n      method wr_wait_n(rx_wr_wait_n) enable((*inhigh*) EN_rx_wr_wait_n);\n      method rd_wait_p(rx_rd_wait_p) enable((*inhigh*) EN_rx_rd_wait_p);\n      method rd_wait_n(rx_rd_wait_n) enable((*inhigh*) EN_rx_rd_wait_n);\n   endinterface\n   \n   interface ParSaxiHp saxi;\n      method m_axi_araddr araddr() clocked_by (saxiclk) reset_by(saxireset);\n      method m_axi_arburst arburst() clocked_by (saxiclk) reset_by(saxireset);\n      method m_axi_arcache arcache() clocked_by (saxiclk) reset_by(saxireset);\n      method m_axi_aresetn aresetn() clocked_by (saxiclk) reset_by(saxireset);\n      method m_axi_arid arid() clocked_by (saxiclk) reset_by(saxireset);\n      method m_axi_arlen arlen() clocked_by (saxiclk) reset_by(saxireset);\n      method m_axi_arlock arlock() clocked_by (saxiclk) reset_by(saxireset);\n      method m_axi_arprot arprot() clocked_by (saxiclk) reset_by(saxireset);\n      method m_axi_arqos arqos() clocked_by (saxiclk) reset_by(saxireset);\n      method arready(m_axi_arready)  clocked_by (saxiclk) reset_by(saxireset) enable((*inhigh*) EN_m_axi_arready);\n      method m_axi_arsize arsize() clocked_by (saxiclk) reset_by(saxireset);\n      method m_axi_arvalid arvalid() clocked_by (saxiclk) reset_by(saxireset);\n      method m_axi_awaddr awaddr() clocked_by (saxiclk) reset_by(saxireset);\n      method m_axi_awburst awburst() clocked_by (saxiclk) reset_by(saxireset);\n      method m_axi_awcache awcache() clocked_by (saxiclk) reset_by(saxireset);\n      method m_axi_awid awid() clocked_by (saxiclk) reset_by(saxireset);\n      method m_axi_awlen awlen() clocked_by (saxiclk) reset_by(saxireset);\n      method m_axi_awlock awlock() clocked_by (saxiclk) reset_by(saxireset);\n      method m_axi_awprot awprot() clocked_by (saxiclk) reset_by(saxireset);\n      method m_axi_awqos awqos() clocked_by (saxiclk) reset_by(saxireset);\n      method awready(m_axi_awready)  clocked_by (saxiclk) reset_by(saxireset) enable((*inhigh*) EN_m_axi_awready);\n      method m_axi_awsize awsize() clocked_by (saxiclk) reset_by(saxireset);\n      method m_axi_awvalid awvalid() clocked_by (saxiclk) reset_by(saxireset);\n      method bid(m_axi_bid) enable((*inhigh*) EN_m_axi_bid);\n      method m_axi_bready bready() clocked_by (saxiclk) reset_by(saxireset);\n      method bresp(m_axi_bresp)  clocked_by (saxiclk) reset_by(saxireset) enable((*inhigh*) EN_m_axi_bresp);\n      method bvalid(m_axi_bvalid)  clocked_by (saxiclk) reset_by(saxireset) enable((*inhigh*) EN_m_axi_bvalid);\n      method rdata(m_axi_rdata)  clocked_by (saxiclk) reset_by(saxireset) enable((*inhigh*) EN_m_axi_rdata);\n      method rid(m_axi_rid)  clocked_by (saxiclk) reset_by(saxireset) enable((*inhigh*) EN_m_axi_rid);\n      method rlast(m_axi_rlast)  clocked_by (saxiclk) reset_by(saxireset) enable((*inhigh*) EN_m_axi_rlast);\n      method m_axi_rready rready() clocked_by (saxiclk) reset_by(saxireset);\n      method rresp(m_axi_rresp)  clocked_by (saxiclk) reset_by(saxireset) enable((*inhigh*) EN_m_axi_rresp);\n      method rvalid(m_axi_rvalid)  clocked_by (saxiclk) reset_by(saxireset) enable((*inhigh*) EN_m_axi_rvalid);\n      method m_axi_wdata wdata() clocked_by (saxiclk) reset_by(saxireset);\n      method m_axi_wid wid() clocked_by (saxiclk) reset_by(saxireset);\n      method m_axi_wlast wlast() clocked_by (saxiclk) reset_by(saxireset);\n      method wready(m_axi_wready)  clocked_by (saxiclk) reset_by(saxireset) enable((*inhigh*) EN_m_axi_wready);\n      method m_axi_wstrb wstrb() clocked_by (saxiclk) reset_by(saxireset);\n      method m_axi_wvalid wvalid() clocked_by (saxiclk) reset_by(saxireset);\n   endinterface   \n   \n   interface ParMaxiGp maxi;\n      method araddr(s_axi_araddr) clocked_by(maxiclk) reset_by(maxireset) enable((*inhigh*) EN_s_axi_araddr);\n      method arburst(s_axi_arburst) clocked_by(maxiclk) reset_by(maxireset) enable((*inhigh*) EN_s_axi_arburst);\n      method arcache(s_axi_arcache) clocked_by(maxiclk) reset_by(maxireset) enable((*inhigh*) EN_s_axi_arcache);\n      method s_axi_aresetn aresetn() clocked_by(maxiclk) reset_by(maxireset);\n      method arid(s_axi_arid) clocked_by(maxiclk) reset_by(maxireset) enable((*inhigh*) EN_s_axi_arid);\n      method arlen(s_axi_arlen) clocked_by(maxiclk) reset_by(maxireset) enable((*inhigh*) EN_s_axi_arlen);\n      method arlock(s_axi_arlock) clocked_by(maxiclk) reset_by(maxireset) enable((*inhigh*) EN_s_axi_arlock);\n      method arprot(s_axi_arprot) clocked_by(maxiclk) reset_by(maxireset) enable((*inhigh*) EN_s_axi_arprot);\n      method arqos(s_axi_arqos) clocked_by(maxiclk) reset_by(maxireset) enable((*inhigh*) EN_s_axi_arqos);\n      method s_axi_arready arready() clocked_by(maxiclk) reset_by(maxireset);\n      method arsize(s_axi_arsize) clocked_by(maxiclk) reset_by(maxireset) enable((*inhigh*) EN_s_axi_arsize);\n      method arvalid(s_axi_arvalid) clocked_by(maxiclk) reset_by(maxireset) enable((*inhigh*) EN_s_axi_arvalid);\n      method awaddr(s_axi_awaddr) clocked_by(maxiclk) reset_by(maxireset) enable((*inhigh*) EN_s_axi_awaddr);\n      method awburst(s_axi_awburst) clocked_by(maxiclk) reset_by(maxireset) enable((*inhigh*) EN_s_axi_awburst);\n      method awcache(s_axi_awcache) clocked_by(maxiclk) reset_by(maxireset) enable((*inhigh*) EN_s_axi_awcache);\n      method awid(s_axi_awid) clocked_by(maxiclk) reset_by(maxireset) enable((*inhigh*) EN_s_axi_awid);\n      method awlen(s_axi_awlen) clocked_by(maxiclk) reset_by(maxireset) enable((*inhigh*) EN_s_axi_awlen);\n      method awlock(s_axi_awlock) clocked_by(maxiclk) reset_by(maxireset) enable((*inhigh*) EN_s_axi_awlock);\n      method awprot(s_axi_awprot) clocked_by(maxiclk) reset_by(maxireset) enable((*inhigh*) EN_s_axi_awprot);\n      method awqos(s_axi_awqos) clocked_by(maxiclk) reset_by(maxireset) enable((*inhigh*) EN_s_axi_awqos);\n      method s_axi_awready awready() clocked_by(maxiclk) reset_by(maxireset);\n      method awsize(s_axi_awsize) clocked_by(maxiclk) reset_by(maxireset) enable((*inhigh*) EN_s_axi_awsize);\n      method awvalid(s_axi_awvalid) clocked_by(maxiclk) reset_by(maxireset) enable((*inhigh*) EN_s_axi_awvalid);\n      method s_axi_bid bid() clocked_by(maxiclk) reset_by(maxireset);\n      method bready(s_axi_bready) clocked_by(maxiclk) reset_by(maxireset) enable((*inhigh*) EN_s_axi_bready);\n      method s_axi_bresp bresp() clocked_by(maxiclk) reset_by(maxireset);\n      method s_axi_bvalid bvalid() clocked_by(maxiclk) reset_by(maxireset);\n      method s_axi_rdata rdata() clocked_by(maxiclk) reset_by(maxireset);\n      method s_axi_rlast rlast() clocked_by(maxiclk) reset_by(maxireset);\n      method rready(s_axi_rready) clocked_by(maxiclk) reset_by(maxireset) enable((*inhigh*) EN_s_axi_rready);\n      method s_axi_rresp rresp() clocked_by(maxiclk) reset_by(maxireset);\n      method s_axi_rvalid rvalid() clocked_by(maxiclk) reset_by(maxireset);\n      method wdata(s_axi_wdata) clocked_by(maxiclk) reset_by(maxireset) enable((*inhigh*) EN_s_axi_wdata);\n      method wid(s_axi_wid) clocked_by(maxiclk) reset_by(maxireset) enable((*inhigh*) EN_s_axi_wid);\n      method wlast(s_axi_wlast) clocked_by(maxiclk) reset_by(maxireset) enable((*inhigh*) EN_s_axi_wlast);\n      method s_axi_wready wready() clocked_by(maxiclk) reset_by(maxireset);\n      method wstrb(s_axi_wstrb) clocked_by(maxiclk) reset_by(maxireset) enable((*inhigh*) EN_s_axi_wstrb);\n      method wvalid(s_axi_wvalid) clocked_by(maxiclk) reset_by(maxireset) enable((*inhigh*) EN_s_axi_wvalid);\n      method s_axi_rid rid() clocked_by(maxiclk) reset_by(maxireset);\n   endinterface\n   \n   \nschedule (\n   misc.csysack, misc.cactive, misc.reset_chip, misc.reset_fpga, tx.data_p, tx.data_n,\n   tx.frame_p, tx.frame_n, tx.lclk_p, tx.lclk_n, rx.wr_wait_p,\n   rx.wr_wait_n, rx.rd_wait_p, rx.rd_wait_n, misc.cclk_p,\n   misc.cclk_n, maxi.awid, maxi.awaddr, maxi.awlen, maxi.awsize,\n   maxi.awburst, maxi.awlock, maxi.awcache, maxi.awprot,\n   maxi.awvalid, saxi.awready, maxi.wid, maxi.wdata, maxi.wstrb,\n   maxi.wlast, maxi.wvalid, saxi.wready, maxi.bready, saxi.bid,\n   saxi.bresp, saxi.bvalid, maxi.arid, maxi.araddr, maxi.arlen,\n   maxi.arsize, maxi.arburst, maxi.arlock, maxi.arcache,\n   maxi.arprot, maxi.arvalid, saxi.arready, maxi.rready,\n   saxi.rid, saxi.rdata, saxi.rresp, saxi.rlast, saxi.rvalid,\n   maxi.awqos, maxi.arqos,\n   // Inputs\n   // clkin_100, saxi.aclk, maxi.aclk, reset, \n   saxi.aresetn,\n   maxi.aresetn, misc.csysreq, rx.data_p, rx.data_n, rx.frame_p,\n   rx.frame_n, rx.lclk_p, rx.lclk_n, tx.wr_wait_p, tx.wr_wait_n,\n   tx.rd_wait_p, tx.rd_wait_n, maxi.awready, saxi.awid,\n   saxi.awaddr, saxi.awlen, saxi.awsize, saxi.awburst,\n   saxi.awlock, saxi.awcache, saxi.awprot, saxi.awvalid,\n   maxi.wready, saxi.wid, saxi.wdata, saxi.wstrb, saxi.wlast,\n   saxi.wvalid, maxi.bid, maxi.bresp, maxi.bvalid, saxi.bready,\n   maxi.arready, saxi.arid, saxi.araddr, saxi.arlen, saxi.arsize,\n   saxi.arburst, saxi.arlock, saxi.arcache, saxi.arprot,\n   saxi.arvalid, maxi.rid, maxi.rdata, maxi.rresp, maxi.rlast,\n   maxi.rvalid, saxi.rready, saxi.awqos, saxi.arqos\n) CF (\n   misc.csysack, misc.cactive, misc.reset_chip, misc.reset_fpga, tx.data_p, tx.data_n,\n   tx.frame_p, tx.frame_n, tx.lclk_p, tx.lclk_n, rx.wr_wait_p,\n   rx.wr_wait_n, rx.rd_wait_p, rx.rd_wait_n, misc.cclk_p,\n   misc.cclk_n, maxi.awid, maxi.awaddr, maxi.awlen, maxi.awsize,\n   maxi.awburst, maxi.awlock, maxi.awcache, maxi.awprot,\n   maxi.awvalid, saxi.awready, maxi.wid, maxi.wdata, maxi.wstrb,\n   maxi.wlast, maxi.wvalid, saxi.wready, maxi.bready, saxi.bid,\n   saxi.bresp, saxi.bvalid, maxi.arid, maxi.araddr, maxi.arlen,\n   maxi.arsize, maxi.arburst, maxi.arlock, maxi.arcache,\n   maxi.arprot, maxi.arvalid, saxi.arready, maxi.rready,\n   saxi.rid, saxi.rdata, saxi.rresp, saxi.rlast, saxi.rvalid,\n   maxi.awqos, maxi.arqos,\n   // Inputs\n   // clkin_100, saxi.aclk, maxi.aclk, reset, \n   saxi.aresetn,\n   maxi.aresetn, misc.csysreq, rx.data_p, rx.data_n, rx.frame_p,\n   rx.frame_n, rx.lclk_p, rx.lclk_n, tx.wr_wait_p, tx.wr_wait_n,\n   tx.rd_wait_p, tx.rd_wait_n, maxi.awready, saxi.awid,\n   saxi.awaddr, saxi.awlen, saxi.awsize, saxi.awburst,\n   saxi.awlock, saxi.awcache, saxi.awprot, saxi.awvalid,\n   maxi.wready, saxi.wid, saxi.wdata, saxi.wstrb, saxi.wlast,\n   saxi.wvalid, maxi.bid, maxi.bresp, maxi.bvalid, saxi.bready,\n   maxi.arready, saxi.arid, saxi.araddr, saxi.arlen, saxi.arsize,\n   saxi.arburst, saxi.arlock, saxi.arcache, saxi.arprot,\n   saxi.arvalid, maxi.rid, maxi.rdata, maxi.rresp, maxi.rlast,\n   maxi.rvalid, saxi.rready, saxi.awqos, saxi.arqos\n   \n   );\n\nendmodule\n"
  },
  {
    "path": "contrib/parallella/Makefile",
    "content": "CONNECTALDIR?=../..\n#S2H_INTERFACES = MainRequest:Main.request\n#H2S_INTERFACES = Main:MainRequest\n\nBSVFILES = ELink.bsv ParallellaLibDefs.bsv\nCPPFILES=testmain.cpp\nPARDIR=/scratch/stewart/parallella/parallella-hw/fpga/src\nPIN_TYPE = ParallellaLibDefs::ParallellaPins\nPIN_TYPE_INCLUDE = ParallellaLibDefs\n# CONNECTALFLAGS = -C /scratch/stewart/parallella/parallella-hw/boards/parallella-I/constraints/parallella_z70x0_loc.xdc\nCONNECTALFLAGS += \\\n\t--verilog $(PARDIR)/elink/hdl/elink_regmap.v \\\n\t--verilog $(PARDIR)/constants/hdl \\\n\t--verilog $(PARDIR)/elink/hdl \\\n\t--verilog $(PARDIR)/embox/hdl \\\n\t--verilog $(PARDIR)/emmu/hdl \\\n\t--verilog $(PARDIR)/gpio/hdl \\\n\t--verilog $(PARDIR)/i2c/hdl \\\n\t--verilog $(PARDIR)/memory/hdl \\\n\t--verilog $(PARDIR)/stubs/hdl \n\n\n\n\nCONNECTALFLAGS += -D IMPORT_HOSTIF\n\nParallella.bsv: parallella.v\n\t$(CONNECTALDIR)/generated/scripts/importbvi.py -o Parallella.bsv -I Parallella -P PP --factor esaxi --factor emaxi --factor rx --factor tx -c clkin_100 -r reset \\\n\t-p SIDW:12 \\\n\t-p SAW:32 \\\n\t-p SDW:32 \\\n\t-p MIDW:6 \\\n\t-p MAW:32 \\\n\t-p MDW:64 \\\n\t-p STW:8 \\\n\t-p LW:8 \\\n\t-p AW:32 \\\n\t-p DW:32 \\\n\tparallella.v\n\ninclude $(CONNECTALDIR)/Makefile.connectal\n"
  },
  {
    "path": "contrib/parallella/PParallellaLIB.bsv",
    "content": "// Copyright (c) 2015 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\n// This file is a hand-generated file that we hope will someday be\n// generated automatically by connectal/generated/scripts/importbvi.py\n//\n// Created by copying the style of connectal/generated/xilinx/PPS7LIB.bsv\n\nimport Clocks::*;\nimport DefaultValue::*;\nimport XilinxCells::*;\nimport GetPut::*;\nimport AxiBits::*;\n\n\n// The name of this interface is a prefix \"Par_\" plus the common prefix of the signals \"txo\"\n// Hopefully this is what importbvi.py would do\n(* always_ready, always_enabled *)\ninterface Par_txo;\n   method Action data_p(Bit#(8) v);\n   method Action data_n(Bit#(8) v);\n   method Action frame_p(Bit#(1) v);\n   method Action frame_n(Bit#(1) v);\n   method Action lclk_p(Bit#(1) v);\n   method Action lclk_n(Bit#(1) v);\nendinterface\n\n(* always_ready, always_enabled *)\ninterface Par_txi; \n   method Bit#(1) wr_wait_p();\n   method Bit#(1) wr_wait_n();\n   method Bit#(1) rd_wait_p();\n   method Bit#(1) rd_wait_n();\nendinterface\n\n(* always_ready, always_enabled *)\ninterface Par_rxi;\n   method Bit#(8) data_p();\n   method Bit#(8) data_n();\n   method Bit#(1) frame_p();\n   method Bit#(1) frame_n();\n   method Bit#(1) lclk_p();\n   method Bit#(1) lclk_n();\n   method Action cclk_p(Bit#(1) v);\n   method Action cclk_n(Bit#(1) v);\nendinterface\n\n(* always_ready, always_enabled *)\ninterface Par_rxo;\n   method Action wr_wait_p(Bit#(1) v);\n   method Action wr_wait_n(Bit#(1) v);\n   method Action rd_wait_p(Bit#(1) v);\n   method Action rd_wait_n(Bit#(1) v);\nendinterface\n\n(* always_ready, always_enabled *)\ninterface Par_misc;\n   method Bit#(1) csysack();\n   method Bit#(1) cactive();\n   method Action csysreq(Bit#(1) v);\n   method Bit#(1) reset_chip();\n   method Bit#(1) reset_fpga();\nendinterface\n\ntypedef AxiMasterBits#(32,64,6,Empty) ParSaxiHp;\ntypedef AxiSlaveBits#(32,32,12,Empty) ParMaxiGp;\n\n(* always_ready, always_enabled *)\ninterface PParallellaLIB;\n   interface Par_txo txo;\n   interface Par_txi txi;\n   interface Par_rxo rxo;\n   interface Par_rxi rxi;\n   interface ParMaxiGp maxi;   // this will connect to a master\n   interface ParSaxiHp saxi;  // this will connect to a slave\n   interface Par_misc misc;\nendinterface\n\nimport \"BVI\" parallella =\nmodule mkPParallellaLIB#(Clock maxiclk, Clock saxiclk, \n   Reset maxiclk_reset, Reset saxiclk_reset,\n   Reset maxireset, Reset saxireset,\n   Reset reset_chip, Reset reset_fpga)(PParallellaLIB);\n   // default_clock clk();\n   // default_reset rst();\n   input_clock maxiclk(emaxi_aclk) = maxiclk;  // assigns the verilog emaxi_aclk\n   input_clock saxiclk(esaxi_aclk) = saxiclk;  // assigns the verilog esaxi_aclk\n   input_reset maxiclk_reset() = maxiclk_reset; /* from clock*/\n   input_reset saxiclk_reset() = saxiclk_reset; /* from clock*/\n   input_reset maxireset() = maxireset;\n   input_reset saxireset() = saxireset;\n   \n   interface Par_misc misc;\n      method csysack csysack();\n      method cactive cactive();\n      method reset_chip reset_chip();\n      method reset_fpga reset_fpga();\n      method csysreq(csysreq) enable((*inhigh*) EN_csysreq);\n   endinterface\n   \n   interface Par_txo txo;\n      method data_p(txo_data_p) enable((*inhigh*) EN_txo_data_p);\n      method data_n(txo_data_n) enable((*inhigh*) EN_txo_data_n);\n      method frame_p(txo_frame_p) enable((*inhigh*) EN_txo_frame_p);\n      method frame_n(txo_frame_n) enable((*inhigh*) EN_txo_frame_n);\n      method lclk_p(txo_lclk_p) enable((*inhigh*) EN_txo_lclk_p);\n      method lclk_n(txo_lclk_n) enable((*inhigh*) EN_txo_lclk_n);\n   endinterface\n\n   interface Par_txi txi;\n      method txo_wr_wait_p wr_wait_p();\n      method txo_wr_wait_n wr_wait_n();\n      method txo_rd_wait_p rd_wait_p();\n      method txo_rd_wait_n rd_wait_n();\n   endinterface\n\n   interface Par_rxi rxi;\n      method rxi_data_p data_p();\n      method rxi_data_n data_n();\n      method rxi_frame_p frame_p();\n      method rxi_frame_n frame_n();\n      method rxi_lclk_p lclk_p();\n      method rxi_lclk_n lclk_n();\n      method cclk_p(rxi_cclk_p) enable((*inhigh*) EN_rxi_cclk_p);\n      method cclk_n(rxi_cclk_n) enable((*inhigh*) EN_rxi_cclk_n);\n   endinterface\n \n   interface Par_rxo rxo;\n      method wr_wait_p(rxo_wr_wait_p) enable((*inhigh*) EN_rxo_wr_wait_p);\n      method wr_wait_n(rxo_wr_wait_n) enable((*inhigh*) EN_rxo_wr_wait_n);\n      method rd_wait_p(rxo_rd_wait_p) enable((*inhigh*) EN_rxo_rd_wait_p);\n      method rd_wait_n(rxo_rd_wait_n) enable((*inhigh*) EN_rxo_rd_wait_n);\n   endinterface\n   \n   interface ParSaxiHp saxi;\n      method esaxi_araddr araddr() clocked_by (saxiclk) reset_by(saxireset);\n      method esaxi_arburst arburst() clocked_by (saxiclk) reset_by(saxireset);\n      method esaxi_arcache arcache() clocked_by (saxiclk) reset_by(saxireset);\n      method esaxi_aresetn aresetn() clocked_by (saxiclk) reset_by(saxireset);\n      method esaxi_arid arid() clocked_by (saxiclk) reset_by(saxireset);\n      method esaxi_arlen arlen() clocked_by (saxiclk) reset_by(saxireset);\n      method esaxi_arlock arlock() clocked_by (saxiclk) reset_by(saxireset);\n      method esaxi_arprot arprot() clocked_by (saxiclk) reset_by(saxireset);\n      method esaxi_arqos arqos() clocked_by (saxiclk) reset_by(saxireset);\n      method arready(esaxi_arready)  clocked_by (saxiclk) reset_by(saxireset) enable((*inhigh*) EN_esaxi_arready);\n      method esaxi_arsize arsize() clocked_by (saxiclk) reset_by(saxireset);\n      method esaxi_arvalid arvalid() clocked_by (saxiclk) reset_by(saxireset);\n      method esaxi_awaddr awaddr() clocked_by (saxiclk) reset_by(saxireset);\n      method esaxi_awburst awburst() clocked_by (saxiclk) reset_by(saxireset);\n      method esaxi_awcache awcache() clocked_by (saxiclk) reset_by(saxireset);\n      method esaxi_awid awid() clocked_by (saxiclk) reset_by(saxireset);\n      method esaxi_awlen awlen() clocked_by (saxiclk) reset_by(saxireset);\n      method esaxi_awlock awlock() clocked_by (saxiclk) reset_by(saxireset);\n      method esaxi_awprot awprot() clocked_by (saxiclk) reset_by(saxireset);\n      method esaxi_awqos awqos() clocked_by (saxiclk) reset_by(saxireset);\n      method awready(esaxi_awready)  clocked_by (saxiclk) reset_by(saxireset) enable((*inhigh*) EN_esaxi_awready);\n      method esaxi_awsize awsize() clocked_by (saxiclk) reset_by(saxireset);\n      method esaxi_awvalid awvalid() clocked_by (saxiclk) reset_by(saxireset);\n      method bid(esaxi_bid) enable((*inhigh*) EN_esaxi_bid);\n      method esaxi_bready bready() clocked_by (saxiclk) reset_by(saxireset);\n      method bresp(esaxi_bresp)  clocked_by (saxiclk) reset_by(saxireset) enable((*inhigh*) EN_esaxi_bresp);\n      method bvalid(esaxi_bvalid)  clocked_by (saxiclk) reset_by(saxireset) enable((*inhigh*) EN_esaxi_bvalid);\n      method rdata(esaxi_rdata)  clocked_by (saxiclk) reset_by(saxireset) enable((*inhigh*) EN_esaxi_rdata);\n      method rid(esaxi_rid)  clocked_by (saxiclk) reset_by(saxireset) enable((*inhigh*) EN_esaxi_rid);\n      method rlast(esaxi_rlast)  clocked_by (saxiclk) reset_by(saxireset) enable((*inhigh*) EN_esaxi_rlast);\n      method esaxi_rready rready() clocked_by (saxiclk) reset_by(saxireset);\n      method rresp(esaxi_rresp)  clocked_by (saxiclk) reset_by(saxireset) enable((*inhigh*) EN_esaxi_rresp);\n      method rvalid(esaxi_rvalid)  clocked_by (saxiclk) reset_by(saxireset) enable((*inhigh*) EN_esaxi_rvalid);\n      method esaxi_wdata wdata() clocked_by (saxiclk) reset_by(saxireset);\n      method esaxi_wid wid() clocked_by (saxiclk) reset_by(saxireset);\n      method esaxi_wlast wlast() clocked_by (saxiclk) reset_by(saxireset);\n      method wready(esaxi_wready)  clocked_by (saxiclk) reset_by(saxireset) enable((*inhigh*) EN_esaxi_wready);\n      method esaxi_wstrb wstrb() clocked_by (saxiclk) reset_by(saxireset);\n      method esaxi_wvalid wvalid() clocked_by (saxiclk) reset_by(saxireset);\n   endinterface   \n   \n   interface ParMaxiGp maxi;\n      method araddr(emaxi_araddr) clocked_by(maxiclk) reset_by(maxireset) enable((*inhigh*) EN_emaxi_araddr);\n      method arburst(emaxi_arburst) clocked_by(maxiclk) reset_by(maxireset) enable((*inhigh*) EN_emaxi_arburst);\n      method arcache(emaxi_arcache) clocked_by(maxiclk) reset_by(maxireset) enable((*inhigh*) EN_emaxi_arcache);\n      method emaxi_aresetn aresetn() clocked_by(maxiclk) reset_by(maxireset);\n      method arid(emaxi_arid) clocked_by(maxiclk) reset_by(maxireset) enable((*inhigh*) EN_emaxi_arid);\n      method arlen(emaxi_arlen) clocked_by(maxiclk) reset_by(maxireset) enable((*inhigh*) EN_emaxi_arlen);\n      method arlock(emaxi_arlock) clocked_by(maxiclk) reset_by(maxireset) enable((*inhigh*) EN_emaxi_arlock);\n      method arprot(emaxi_arprot) clocked_by(maxiclk) reset_by(maxireset) enable((*inhigh*) EN_emaxi_arprot);\n      method arqos(emaxi_arqos) clocked_by(maxiclk) reset_by(maxireset) enable((*inhigh*) EN_emaxi_arqos);\n      method emaxi_arready arready() clocked_by(maxiclk) reset_by(maxireset);\n      method arsize(emaxi_arsize) clocked_by(maxiclk) reset_by(maxireset) enable((*inhigh*) EN_emaxi_arsize);\n      method arvalid(emaxi_arvalid) clocked_by(maxiclk) reset_by(maxireset) enable((*inhigh*) EN_emaxi_arvalid);\n      method awaddr(emaxi_awaddr) clocked_by(maxiclk) reset_by(maxireset) enable((*inhigh*) EN_emaxi_awaddr);\n      method awburst(emaxi_awburst) clocked_by(maxiclk) reset_by(maxireset) enable((*inhigh*) EN_emaxi_awburst);\n      method awcache(emaxi_awcache) clocked_by(maxiclk) reset_by(maxireset) enable((*inhigh*) EN_emaxi_awcache);\n      method awid(emaxi_awid) clocked_by(maxiclk) reset_by(maxireset) enable((*inhigh*) EN_emaxi_awid);\n      method awlen(emaxi_awlen) clocked_by(maxiclk) reset_by(maxireset) enable((*inhigh*) EN_emaxi_awlen);\n      method awlock(emaxi_awlock) clocked_by(maxiclk) reset_by(maxireset) enable((*inhigh*) EN_emaxi_awlock);\n      method awprot(emaxi_awprot) clocked_by(maxiclk) reset_by(maxireset) enable((*inhigh*) EN_emaxi_awprot);\n      method awqos(emaxi_awqos) clocked_by(maxiclk) reset_by(maxireset) enable((*inhigh*) EN_emaxi_awqos);\n      method emaxi_awready awready() clocked_by(maxiclk) reset_by(maxireset);\n      method awsize(emaxi_awsize) clocked_by(maxiclk) reset_by(maxireset) enable((*inhigh*) EN_emaxi_awsize);\n      method awvalid(emaxi_awvalid) clocked_by(maxiclk) reset_by(maxireset) enable((*inhigh*) EN_emaxi_awvalid);\n      method emaxi_bid bid() clocked_by(maxiclk) reset_by(maxireset);\n      method bready(emaxi_bready) clocked_by(maxiclk) reset_by(maxireset) enable((*inhigh*) EN_emaxi_bready);\n      method emaxi_bresp bresp() clocked_by(maxiclk) reset_by(maxireset);\n      method emaxi_bvalid bvalid() clocked_by(maxiclk) reset_by(maxireset);\n      method emaxi_rdata rdata() clocked_by(maxiclk) reset_by(maxireset);\n      method emaxi_rlast rlast() clocked_by(maxiclk) reset_by(maxireset);\n      method rready(emaxi_rready) clocked_by(maxiclk) reset_by(maxireset) enable((*inhigh*) EN_emaxi_rready);\n      method emaxi_rresp rresp() clocked_by(maxiclk) reset_by(maxireset);\n      method emaxi_rvalid rvalid() clocked_by(maxiclk) reset_by(maxireset);\n      method wdata(emaxi_wdata) clocked_by(maxiclk) reset_by(maxireset) enable((*inhigh*) EN_emaxi_wdata);\n      method wid(emaxi_wid) clocked_by(maxiclk) reset_by(maxireset) enable((*inhigh*) EN_emaxi_wid);\n      method wlast(emaxi_wlast) clocked_by(maxiclk) reset_by(maxireset) enable((*inhigh*) EN_emaxi_wlast);\n      method emaxi_wready wready() clocked_by(maxiclk) reset_by(maxireset);\n      method wstrb(emaxi_wstrb) clocked_by(maxiclk) reset_by(maxireset) enable((*inhigh*) EN_emaxi_wstrb);\n      method wvalid(emaxi_wvalid) clocked_by(maxiclk) reset_by(maxireset) enable((*inhigh*) EN_emaxi_wvalid);\n      method emaxi_rid rid() clocked_by(maxiclk) reset_by(maxireset);\n   endinterface\n   \n   \nschedule (\n   misc.csysack, misc.cactive, misc.reset_chip, misc.reset_fpga, txo.data_p, txo.data_n,\n   txo.frame_p, txo.frame_n, txo.lclk_p, txo.lclk_n, rxo.wr_wait_p,\n   rxo.wr_wait_n, rxo.rd_wait_p, rxo.rd_wait_n, rxi.cclk_p,\n   rxi.cclk_n, maxi.awid, maxi.awaddr, maxi.awlen, maxi.awsize,\n   maxi.awburst, maxi.awlock, maxi.awcache, maxi.awprot,\n   maxi.awvalid, saxi.awready, maxi.wid, maxi.wdata, maxi.wstrb,\n   maxi.wlast, maxi.wvalid, saxi.wready, maxi.bready, saxi.bid,\n   saxi.bresp, saxi.bvalid, maxi.arid, maxi.araddr, maxi.arlen,\n   maxi.arsize, maxi.arburst, maxi.arlock, maxi.arcache,\n   maxi.arprot, maxi.arvalid, saxi.arready, maxi.rready,\n   saxi.rid, saxi.rdata, saxi.rresp, saxi.rlast, saxi.rvalid,\n   maxi.awqos, maxi.arqos,\n   // Inputs\n   // clkin_100, saxi.aclk, maxi.aclk, reset, \n   saxi.aresetn,\n   maxi.aresetn, misc.csysreq, rxi.data_p, rxi.data_n, rxi.frame_p,\n   rxi.frame_n, rxi.lclk_p, rxi.lclk_n, txi.wr_wait_p, txi.wr_wait_n,\n   txi.rd_wait_p, txi.rd_wait_n, maxi.awready, saxi.awid,\n   saxi.awaddr, saxi.awlen, saxi.awsize, saxi.awburst,\n   saxi.awlock, saxi.awcache, saxi.awprot, saxi.awvalid,\n   maxi.wready, saxi.wid, saxi.wdata, saxi.wstrb, saxi.wlast,\n   saxi.wvalid, maxi.bid, maxi.bresp, maxi.bvalid, saxi.bready,\n   maxi.arready, saxi.arid, saxi.araddr, saxi.arlen, saxi.arsize,\n   saxi.arburst, saxi.arlock, saxi.arcache, saxi.arprot,\n   saxi.arvalid, maxi.rid, maxi.rdata, maxi.rresp, maxi.rlast,\n   maxi.rvalid, saxi.rready, saxi.awqos, saxi.arqos\n) CF (\n   misc.csysack, misc.cactive, misc.reset_chip, misc.reset_fpga, txo.data_p, txo.data_n,\n   txo.frame_p, txo.frame_n, txo.lclk_p, txo.lclk_n, rxo.wr_wait_p,\n   rxo.wr_wait_n, rxo.rd_wait_p, rxo.rd_wait_n, rxi.cclk_p,\n   rxi.cclk_n, maxi.awid, maxi.awaddr, maxi.awlen, maxi.awsize,\n   maxi.awburst, maxi.awlock, maxi.awcache, maxi.awprot,\n   maxi.awvalid, saxi.awready, maxi.wid, maxi.wdata, maxi.wstrb,\n   maxi.wlast, maxi.wvalid, saxi.wready, maxi.bready, saxi.bid,\n   saxi.bresp, saxi.bvalid, maxi.arid, maxi.araddr, maxi.arlen,\n   maxi.arsize, maxi.arburst, maxi.arlock, maxi.arcache,\n   maxi.arprot, maxi.arvalid, saxi.arready, maxi.rready,\n   saxi.rid, saxi.rdata, saxi.rresp, saxi.rlast, saxi.rvalid,\n   maxi.awqos, maxi.arqos,\n   // Inputs\n   // clkin_100, saxi.aclk, maxi.aclk, reset, \n   saxi.aresetn,\n   maxi.aresetn, misc.csysreq, rxi.data_p, rxi.data_n, rxi.frame_p,\n   rxi.frame_n, rxi.lclk_p, rxi.lclk_n, txi.wr_wait_p, txi.wr_wait_n,\n   txi.rd_wait_p, txi.rd_wait_n, maxi.awready, saxi.awid,\n   saxi.awaddr, saxi.awlen, saxi.awsize, saxi.awburst,\n   saxi.awlock, saxi.awcache, saxi.awprot, saxi.awvalid,\n   maxi.wready, saxi.wid, saxi.wdata, saxi.wstrb, saxi.wlast,\n   saxi.wvalid, maxi.bid, maxi.bresp, maxi.bvalid, saxi.bready,\n   maxi.arready, saxi.arid, saxi.araddr, saxi.arlen, saxi.arsize,\n   saxi.arburst, saxi.arlock, saxi.arcache, saxi.arprot,\n   saxi.arvalid, maxi.rid, maxi.rdata, maxi.rresp, maxi.rlast,\n   maxi.rvalid, saxi.rready, saxi.awqos, saxi.arqos\n   \n   );\n\nendmodule\n"
  },
  {
    "path": "contrib/parallella/ParallellaLib.bsv",
    "content": "// Copyright (c) 2015 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\nimport Clocks::*;\nimport DefaultValue::*;\nimport GetPut::*;\nimport Connectable::*;\nimport ConnectableWithTrace::*;\nimport Bscan::*;\nimport Vector::*;\nimport ELink::*;\nimport Portal::*;\nimport AxiMasterSlave::*;\nimport AxiDma::*;\nimport XilinxCells::*;\nimport ConnectalXilinxCells::*;\nimport ConnectalClocks::*;\nimport AxiBits::*;\nimport AxiGather::*;\nimport ParallellaLibDefs::*;\n   \n\nmodule mkParallellaLib#(Clock axi_clock, Reset axi_reset)(ParallellaLib);\n\n   ELink foo <- mkELink( \n      axi_clock,  axi_clock, \n      axi_reset, axi_reset,\n      axi_reset, axi_reset,\n       axi_reset, axi_reset );\n      AxiSlaveCommon#(32,32,12,Empty) vtopm_axi_gp;\n    AxiMasterCommon#(32,64,6) vtops_axi_hp;\n    vtopm_axi_gp <- mkAxi3SlaveGather(foo.maxi, clocked_by axi_clock, reset_by axi_reset);\n    vtops_axi_hp <- mkAxi3MasterGather(foo.saxi, clocked_by axi_clock, reset_by axi_reset);\n    interface maxi = vtopm_axi_gp;\n    interface saxi = vtops_axi_hp;\n    interface  ParallellaPins pins;\n     interface  tx = foo.tx;\n      interface  rx = foo.rx;\n   endinterface\n   interface  misc = foo.misc;\n      \nendmodule\n"
  },
  {
    "path": "contrib/parallella/ParallellaLibDefs.bsv",
    "content": "// Copyright (c) 2015 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\nimport ELink::*;\nimport AxiMasterSlave::*;\nimport AxiBits::*;\nimport AxiGather::*;\n\ninterface ParallellaPins;\n   interface Par_tx tx;\n   interface Par_rx rx;\nendinterface\n\ninterface ParallellaLib;\n   interface ParallellaPins pins;\n   interface AxiSlaveCommon#(32,32,12,Empty) maxi;  // this will connect to a master\n   interface AxiMasterCommon#(32,64,6) saxi;  // this will connect to a slave\n   interface Par_misc misc;\nendinterface\n"
  },
  {
    "path": "contrib/parallella/Top.bsv",
    "content": "// Copyright (c) 2014 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\nimport Vector::*;\nimport GetPut::*;\nimport Connectable :: *;\nimport Clocks :: *;\nimport FIFO::*;\nimport Portal::*;\nimport HostInterface::*;\nimport CtrlMux::*;\nimport PS7LIB::*;\nimport PPS7LIB::*;\nimport ConnectalClocks::*;\nimport BlueScopeEventPIO::*;\nimport ParallellaLibDefs::*;\nimport ParallellaLib::*;\nimport PParallellaLIB::*;\nimport AxiMasterSlave::*;\nimport AxiGather::*;\nimport AxiDma::*;\n\n\n\nmodule mkConnectalTop#(HostInterface host)(ConnectalTop);\n   Clock oneTrueClock <- exposeCurrentClock;\n   Reset oneTrueReset <- exposeCurrentReset;\n   ParallellaLib plib <- mkParallellaLib(oneTrueClock, oneTrueReset);\n\n\n   mkConnection(host.ps7.m_axi_gp[1].client, plib.maxi.server);\n   mkConnection(plib.saxi.client, host.ps7.s_axi_hp[3].server);\n   interface ParallellaPins pins = plib.pins;\n\nendmodule : mkConnectalTop\nexport mkConnectalTop;\nexport ParallellaLibDefs::*;\nexport PParallellaLIB::*;\n"
  },
  {
    "path": "contrib/parallella/notes.txt",
    "content": "In parallella-hw I'm getting width differences between various axi bus signals in elink.v and the corresponding signals on the PS7.\nFrom Table 5-9 in the Zynq TRM ug585-Zynq-7000-TRM.pdf, I think elink.v has the wrong values.\n\nWhy is elink.v like this?  Is there a module that actually wires up the ps7 to elink.v somewhere?\n\n\nWARNING: [Synth 8-689] width (6) of port connection 'm_axi_bid' does not match port width (1) of module 'elink' [/scratch/stewart/connectal/contrib/parallella/zedboard/verilog/mkZynqTop.v:1539]\nWARNING: [Synth 8-689] width (6) of port connection 'm_axi_rid' does not match port width (1) of module 'elink' [/scratch/stewart/connectal/contrib/parallella/zedboard/verilog/mkZynqTop.v:1543]\nWARNING: [Synth 8-689] width (6) of port connection 'm_axi_arid' does not match port width (1) of module 'elink' [/scratch/stewart/connectal/contrib/parallella/zedboard/verilog/mkZynqTop.v:1603]\nWARNING: [Synth 8-689] width (6) of port connection 'm_axi_awid' does not match port width (1) of module 'elink' [/scratch/stewart/connectal/contrib/parallella/zedboard/verilog/mkZynqTop.v:1613]\n\nWARNING: [Synth 8-689] width (4) of port connection 'm_axi_arlen' does not match port width (8) of module 'elink' [/scratch/stewart/connectal/contrib/parallella/zedboard/verilog/mkZynqTop.v:1604]\nWARNING: [Synth 8-689] width (4) of port connection 'm_axi_awlen' does not match port width (8) of module 'elink' [/scratch/stewart/connectal/contrib/parallella/zedboard/verilog/mkZynqTop.v:1614]\n\nWARNING: [Synth 8-689] width (2) of port connection 'm_axi_arlock' does not match port width (1) of module 'elink' [/scratch/stewart/connectal/contrib/parallella/zedboard/verilog/mkZynqTop.v:1605]\nWARNING: [Synth 8-689] width (2) of port connection 'm_axi_awlock' does not match port width (1) of module 'elink' [/scratch/stewart/connectal/contrib/parallella/zedboard/verilog/mkZynqTop.v:1615]\n\nWARNING: [Synth 8-689] width (2) of port connection 'm_axi_arsize' does not match port width (3) of module 'elink' [/scratch/stewart/connectal/contrib/parallella/zedboard/verilog/mkZynqTop.v:1608]\nWARNING: [Synth 8-689] width (2) of port connection 'm_axi_awsize' does not match port width (3) of module 'elink' [/scratch/stewart/connectal/contrib/parallella/zedboard/verilog/mkZynqTop.v:1618]\n\n\nWARNING: [Synth 8-689] width (32) of port connection 's_axi_araddr' does not match port width (30) of module 'elink' [/scratch/stewart/connectal/contrib/parallella/zedboard/verilog/mkZynqTop.v:1552]\nWARNING: [Synth 8-689] width (32) of port connection 's_axi_awaddr' does not match port width (30) of module 'elink' [/scratch/stewart/connectal/contrib/parallella/zedboard/verilog/mkZynqTop.v:1562]\n\nWARNING: [Synth 8-689] width (4) of port connection 's_axi_arlen' does not match port width (8) of module 'elink' [/scratch/stewart/connectal/contrib/parallella/zedboard/verilog/mkZynqTop.v:1556]\nWARNING: [Synth 8-689] width (4) of port connection 's_axi_awlen' does not match port width (8) of module 'elink' [/scratch/stewart/connectal/contrib/parallella/zedboard/verilog/mkZynqTop.v:1566]\n\nWARNING: [Synth 8-689] width (2) of port connection 's_axi_arlock' does not match port width (1) of module 'elink' [/scratch/stewart/connectal/contrib/parallella/zedboard/verilog/mkZynqTop.v:1557]\nWARNING: [Synth 8-689] width (2) of port connection 's_axi_awlock' does not match port width (1) of module 'elink' [/scratch/stewart/connectal/contrib/parallella/zedboard/verilog/mkZynqTop.v:1567]\n\n\nWARNING: [Synth 8-689] width (2) of port connection 's_axi_arsize' does not match port width (3) of module 'elink' [/scratch/stewart/connectal/contrib/parallella/zedboard/verilog/mkZynqTop.v:1560]\nWARNING: [Synth 8-689] width (2) of port connection 's_axi_awsize' does not match port width (3) of module 'elink' [/scratch/stewart/connectal/contrib/parallella/zedboard/verilog/mkZynqTop.v:1570]\n\n"
  },
  {
    "path": "contrib/parallella/parallella.v",
    "content": "/*\n  File: parallella.v\n \n  This file is part of the Parallella FPGA Reference Design.\n\n  Copyright (C) 2013 Adapteva, Inc.\n  Contributed by Roman Trogan <support@adapteva.com>\n\n  This program is free software: you can redistribute it and/or modify\n  it under the terms of the GNU General Public License as published by\n  the Free Software Foundation, either version 3 of the License, or\n  (at your option) any later version.\n\n  This program is distributed in the hope that it will be useful,\n  but WITHOUT ANY WARRANTY; without even the implied warranty of\n  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n  GNU General Public License for more details.\n\n  You should have received a copy of the GNU General Public License\n  along with this program (see the file COPYING).  If not, see\n  <http://www.gnu.org/licenses/>.\n*/\nmodule parallella (/*AUTOARG*/\n   // Outputs\n   csysack, cactive, reset_chip, reset_fpga, txo_data_p, txo_data_n,\n   txo_frame_p, txo_frame_n, txo_lclk_p, txo_lclk_n, rxo_wr_wait_p,\n   rxo_wr_wait_n, rxo_rd_wait_p, rxo_rd_wait_n, rxi_cclk_p,\n   rxi_cclk_n, emaxi_awid, emaxi_awaddr, emaxi_awlen, emaxi_awsize,\n   emaxi_awburst, emaxi_awlock, emaxi_awcache, emaxi_awprot,\n   emaxi_awvalid, esaxi_awready, emaxi_wid, emaxi_wdata, emaxi_wstrb,\n   emaxi_wlast, emaxi_wvalid, esaxi_wready, emaxi_bready, esaxi_bid,\n   esaxi_bresp, esaxi_bvalid, emaxi_arid, emaxi_araddr, emaxi_arlen,\n   emaxi_arsize, emaxi_arburst, emaxi_arlock, emaxi_arcache,\n   emaxi_arprot, emaxi_arvalid, esaxi_arready, emaxi_rready,\n   esaxi_rid, esaxi_rdata, esaxi_rresp, esaxi_rlast, esaxi_rvalid,\n   emaxi_awqos, emaxi_arqos,\n   // Inputs\n   clkin_100, esaxi_aclk, emaxi_aclk, reset, esaxi_aresetn,\n   emaxi_aresetn, csysreq, rxi_data_p, rxi_data_n, rxi_frame_p,\n   rxi_frame_n, rxi_lclk_p, rxi_lclk_n, txi_wr_wait_p, txi_wr_wait_n,\n   txi_rd_wait_p, txi_rd_wait_n, emaxi_awready, esaxi_awid,\n   esaxi_awaddr, esaxi_awlen, esaxi_awsize, esaxi_awburst,\n   esaxi_awlock, esaxi_awcache, esaxi_awprot, esaxi_awvalid,\n   emaxi_wready, esaxi_wid, esaxi_wdata, esaxi_wstrb, esaxi_wlast,\n   esaxi_wvalid, emaxi_bid, emaxi_bresp, emaxi_bvalid, esaxi_bready,\n   emaxi_arready, esaxi_arid, esaxi_araddr, esaxi_arlen, esaxi_arsize,\n   esaxi_arburst, esaxi_arlock, esaxi_arcache, esaxi_arprot,\n   esaxi_arvalid, emaxi_rid, emaxi_rdata, emaxi_rresp, emaxi_rlast,\n   emaxi_rvalid, esaxi_rready, esaxi_awqos, esaxi_arqos\n   );\n\n   parameter SIDW = 12; //ID Width\n   parameter SAW  = 32; //Address Bus Width\n   parameter SDW  = 32; //Data Bus Width\n   parameter MIDW = 6;  //ID Width\n   parameter MAW  = 32; //Address Bus Width\n   parameter MDW  = 64; //Data Bus Width\n   parameter STW = 8;   //Number of strobes\n   parameter LW  = 8;\n   parameter AW  = 32;  //Address Bus Width\n   parameter DW  = 32;  //Data Bus Width\n   \n   //#########\n   //# Inputs\n   //#########\n\n   // global signals\n   input       clkin_100;      // 100MHz input clock \n   input       esaxi_aclk;     // clock source of the axi bus for slave port\n   input       emaxi_aclk;     // clock source of the axi bus for master port\n   input       reset;          // system reset\n   input       esaxi_aresetn;  // reset of axi bus for slave port\n   input       emaxi_aresetn;  // reset of axi bus for master port\n   input       csysreq;        // system exit low-power state request \n      \n   // LVDS FMC Port\n   input [7:0] rxi_data_p;\n   input [7:0] rxi_data_n;\n   input       rxi_frame_p;\n   input       rxi_frame_n;\n   input       rxi_lclk_p;\n   input       rxi_lclk_n;\n   input       txi_wr_wait_p;\n   input       txi_wr_wait_n;\n   input       txi_rd_wait_p;\n   input       txi_rd_wait_n;\n   \n   //########################\n   //# Write address channel\n   //########################\n   // Master Port\n   input            emaxi_awready; //write address ready\n   // Slave Port\n   input [SIDW-1:0] esaxi_awid;    //write address ID\n   input [MAW-1:0]  esaxi_awaddr;  //write address\n   input [3:0] \t    esaxi_awlen;   //burst lenght (the number of data transfers)\n   input [2:0] \t    esaxi_awsize;  //burst size (the size of each transfer)\n   input [1:0] \t    esaxi_awburst; //burst type\n   input [1:0] \t    esaxi_awlock;  //lock type (atomic characteristics)\n   input [3:0] \t    esaxi_awcache; //memory type\n   input [2:0] \t    esaxi_awprot;  //protection type\n   input \t    esaxi_awvalid; //write address valid\n   \n   //########################\n   //# Write data channel\n   //########################\n   // Master Port\n   input \t    emaxi_wready;//write ready\n   // Slave Port\n   input [SIDW-1:0] esaxi_wid;   //write ID tag (supported only in AXI3)\n   input [SDW-1:0]  esaxi_wdata; //write data\n   input [3:0] \t    esaxi_wstrb; //write strobes\n   input \t    esaxi_wlast; //write last. Indicates last transfer in burst\n   input \t    esaxi_wvalid;//write valid\n   \n   //########################\n   // Write response channel\n   //########################\n   // Master Port\n   input [MIDW-1:0] emaxi_bid;   //response ID tag\n   input [1:0] \t    emaxi_bresp; //write response\n   input \t    emaxi_bvalid;//write response valid\n   // Slave Port\n   input \t    esaxi_bready;//response ready\n      \n   //########################\n   //# Read address channel\n   //########################\n   // Master Port\n   input \t    emaxi_arready;//read address ready\n   // Slave Port\n   input [SIDW-1:0] esaxi_arid;    //read address ID\n   input [MAW-1:0]  esaxi_araddr;  //read address\n   input [3:0] \t    esaxi_arlen;   //burst lenght (the number of data transfers)\n   input [2:0] \t    esaxi_arsize;  //burst size (the size of each transfer)\n   input [1:0] \t    esaxi_arburst; //burst type\n   input [1:0] \t    esaxi_arlock;  //lock type (atomic characteristics)\n   input [3:0] \t    esaxi_arcache; //memory type\n   input [2:0] \t    esaxi_arprot;  //protection type\n   input \t    esaxi_arvalid; //write address valid\n\n   //########################\n   //# Read data channel\n   //########################\n   // Master Port\n   input [MIDW-1:0] emaxi_rid;   //read ID tag \n   input [MDW-1:0]  emaxi_rdata; //read data\n   input [1:0] \t    emaxi_rresp; //read response\n   input \t    emaxi_rlast; //read last, indicates last transfer in burst\n   input \t    emaxi_rvalid;//read valid\n   // Slave Port\n   input \t    esaxi_rready; //read ready\n\n   //##########\n   //# Outputs\n   //##########\n\n   // global signals\n   output \t   csysack;//exit low-power state acknowledgement\n   output \t   cactive;//clock active\n   output \t   reset_chip;\n   output \t   reset_fpga;\n      \n   // LVDS FMC Port\n   output [7:0]    txo_data_p;\n   output [7:0]    txo_data_n;\n   output \t   txo_frame_p;\n   output \t   txo_frame_n;\n   output \t   txo_lclk_p;\n   output \t   txo_lclk_n;\n   output \t   rxo_wr_wait_p;\n   output \t   rxo_wr_wait_n;\n   output \t   rxo_rd_wait_p;\n   output \t   rxo_rd_wait_n;\n\n   output      rxi_cclk_p;\n   output \t   rxi_cclk_n;\n\n   //########################\n   //# Write address channel\n   //########################\n   // Master Port\n   output [MIDW-1:0] emaxi_awid;    //write address ID\n   output [MAW-1:0]  emaxi_awaddr;  //write address\n   output [3:0]      emaxi_awlen;   //burst length (number of data transfers)\n   output [2:0]      emaxi_awsize;  //burst size (the size of each transfer)\n   output [1:0]      emaxi_awburst; //burst type\n   output [1:0]      emaxi_awlock;  //lock type (atomic characteristics)\n   output [3:0]      emaxi_awcache; //memory type\n   output [2:0]      emaxi_awprot;  //protection type\n   output \t     emaxi_awvalid; //write address valid\n   // Slave Port\n   output \t     esaxi_awready; //write address ready\n      \n   //########################\n   //# Write data channel\n   //########################\n   // Master Port\n   output [MIDW-1:0] emaxi_wid;   //write ID tag (supported only in AXI3)\n   output [MDW-1:0]  emaxi_wdata; //write data\n   output [STW-1:0]  emaxi_wstrb; //write strobes\n   output \t     emaxi_wlast; //write last, indicates last transfer in burst\n   output \t     emaxi_wvalid;//write valid\n   // Slave Port\n   output \t     esaxi_wready;//write ready\n   \n   //########################\n   // Write response channel\n   //########################\n   // Master Port\n   output \t     emaxi_bready;//response ready\n   // Slave Port\n   output [SIDW-1:0] esaxi_bid;   //response ID tag\n   output [1:0]      esaxi_bresp; //write response\n   output \t     esaxi_bvalid;//write response valid\n  \n   //########################\n   //# Read address channel\n   //########################\n   // Master Port\n   output [MIDW-1:0] emaxi_arid;    //read address ID\n   output [MAW-1:0]  emaxi_araddr;  //read address\n   output [3:0]      emaxi_arlen;   //burst lenght (number of data transfers)\n   output [2:0]      emaxi_arsize;  //burst size (the size of each transfer)\n   output [1:0]      emaxi_arburst; //burst type\n   output [1:0]      emaxi_arlock;  //lock type (atomic characteristics)\n   output [3:0]      emaxi_arcache; //memory type\n   output [2:0]      emaxi_arprot;  //protection type\n   output \t     emaxi_arvalid; //write address valid\n   // Slave Port\n   output \t     esaxi_arready; //read address ready\n      \n   //########################\n   //# Read data channel\n   //########################\n   // Master Port\n   output \t     emaxi_rready; //read ready\n   // Slave Port\n   output [SIDW-1:0] esaxi_rid;   //read ID tag (must match arid of transaction)\n   output [SDW-1:0]  esaxi_rdata; //read data\n   output [1:0]      esaxi_rresp; //read response\n   output \t     esaxi_rlast; //read last, indicates last transfer in burst\n   output \t     esaxi_rvalid;//read valid\n\n   //#######################################################################\n   //# The following features are not supported (AXI4 only)\n   //# If un-commented, those signals have to be driven with default values\n   //#######################################################################\n   // input \t    emaxi_buser;   //user signal \n   // input         emaxi_ruser;   //user signal \n   output [3:0]     emaxi_awqos;   //quality of service default 4'b0000\n   // output [3:0]  emaxi_awregion;//region identifier \n   // output \t    emaxi_awuser;  //user signal \n   // output        emaxi_wuser;   //user signal  \n   output [3:0]     emaxi_arqos;   //quality of service default 4'b0000\n   // output [3:0]  emaxi_arregion;//region identifier \n   // output \t    emaxi_aruser;  //user signal \n   input [3:0] \t    esaxi_awqos;   //Quality of Service default 4'b0000\n   // input [3:0]   awregion;      //region identifier  \n   // input   \t    awuser;        //user signal \n   // input         wuser;         //user signal   \n   input [3:0] \t    esaxi_arqos;   //quality of service default 4'b0000\n   // input [3:0]   arregion;      //region identifier (AXI4 only)\n   // input \t    aruser;        //user signal (AXI4 only)\n   // output        buser;         //user signal (AXI4 only)\n   // output        ruser;         //user signal (AXI4 only)\n   \n   /*AUTOINPUT*/\n   /*AUTOWIRE*/\n   // Beginning of automatic wires (for undeclared instantiated-module outputs)\n   wire                 elink_access_inb;       // From ewrapper_link_top of ewrapper_link_top.v\n   wire                 elink_access_outb;      // From axi_elink_if of axi_elink_if.v\n   wire                 elink_cclk_enb;         // From axi_elink_if of axi_elink_if.v\n   wire [1:0]           elink_clk_div;          // From axi_elink_if of axi_elink_if.v\n   wire [3:0]           elink_ctrlmode_inb;     // From ewrapper_link_top of ewrapper_link_top.v\n   wire [3:0]           elink_ctrlmode_outb;    // From axi_elink_if of axi_elink_if.v\n   wire [31:0]          elink_data_inb;         // From ewrapper_link_top of ewrapper_link_top.v\n   wire [31:0]          elink_data_outb;        // From axi_elink_if of axi_elink_if.v\n   wire [1:0]           elink_datamode_inb;     // From ewrapper_link_top of ewrapper_link_top.v\n   wire [1:0]           elink_datamode_outb;    // From axi_elink_if of axi_elink_if.v\n   wire                 elink_disable;          // From axi_elink_if of axi_elink_if.v\n   wire [31:0]          elink_dstaddr_outb;     // From axi_elink_if of axi_elink_if.v\n   wire                 elink_rd_wait_inb;      // From ewrapper_link_top of ewrapper_link_top.v\n   wire                 elink_rd_wait_outb;     // From axi_elink_if of axi_elink_if.v\n   wire [31:0]          elink_srcaddr_inb;      // From ewrapper_link_top of ewrapper_link_top.v\n   wire [31:0]          elink_srcaddr_outb;     // From axi_elink_if of axi_elink_if.v\n   wire                 elink_wr_wait_inb;      // From ewrapper_link_top of ewrapper_link_top.v\n   wire                 elink_wr_wait_outb;     // From axi_elink_if of axi_elink_if.v\n   wire                 elink_write_inb;        // From ewrapper_link_top of ewrapper_link_top.v\n   wire                 elink_write_outb;       // From axi_elink_if of axi_elink_if.v\n   wire                 emaxi_access_inb;       // From axi_master of axi_master.v\n   wire                 emaxi_access_outb;      // From axi_elink_if of axi_elink_if.v\n   wire [3:0]           emaxi_ctrlmode_inb;     // From axi_master of axi_master.v\n   wire [3:0]           emaxi_ctrlmode_outb;    // From axi_elink_if of axi_elink_if.v\n   wire [31:0]          emaxi_data_inb;         // From axi_master of axi_master.v\n   wire [31:0]          emaxi_data_outb;        // From axi_elink_if of axi_elink_if.v\n   wire [1:0]           emaxi_datamode_inb;     // From axi_master of axi_master.v\n   wire [1:0]           emaxi_datamode_outb;    // From axi_elink_if of axi_elink_if.v\n   wire [31:0]          emaxi_dstaddr_inb;      // From axi_master of axi_master.v\n   wire [31:0]          emaxi_dstaddr_outb;     // From axi_elink_if of axi_elink_if.v\n   wire                 emaxi_rd_wait_inb;      // From axi_master of axi_master.v\n   wire [31:0]          emaxi_srcaddr_inb;      // From axi_master of axi_master.v\n   wire [31:0]          emaxi_srcaddr_outb;     // From axi_elink_if of axi_elink_if.v\n   wire                 emaxi_wr_wait_inb;      // From axi_master of axi_master.v\n   wire                 emaxi_wr_wait_outb;     // From axi_elink_if of axi_elink_if.v\n   wire                 emaxi_write_inb;        // From axi_master of axi_master.v\n   wire                 emaxi_write_outb;       // From axi_elink_if of axi_elink_if.v\n   wire                 esaxi_access_inb;       // From axi_slave of axi_slave.v\n   wire                 esaxi_access_outb;      // From axi_elink_if of axi_elink_if.v\n   wire [3:0]           esaxi_ctrlmode_inb;     // From axi_slave of axi_slave.v\n   wire [3:0]           esaxi_ctrlmode_outb;    // From axi_elink_if of axi_elink_if.v\n   wire [31:0]          esaxi_data_inb;         // From axi_slave of axi_slave.v\n   wire [31:0]          esaxi_data_outb;        // From axi_elink_if of axi_elink_if.v\n   wire [1:0]           esaxi_datamode_inb;     // From axi_slave of axi_slave.v\n   wire [1:0]           esaxi_datamode_outb;    // From axi_elink_if of axi_elink_if.v\n   wire [31:0]          esaxi_dstaddr_inb;      // From axi_slave of axi_slave.v\n   wire [31:0]          esaxi_dstaddr_outb;     // From axi_elink_if of axi_elink_if.v\n   wire                 esaxi_rd_wait_inb;      // From axi_slave of axi_slave.v\n   wire                 esaxi_rd_wait_outb;     // From axi_elink_if of axi_elink_if.v\n   wire [31:0]          esaxi_srcaddr_inb;      // From axi_slave of axi_slave.v\n   wire [31:0]          esaxi_srcaddr_outb;     // From axi_elink_if of axi_elink_if.v\n   wire                 esaxi_wr_wait_inb;      // From axi_slave of axi_slave.v\n   wire                 esaxi_wr_wait_outb;     // From axi_elink_if of axi_elink_if.v\n   wire                 esaxi_write_inb;        // From axi_slave of axi_slave.v\n   wire                 esaxi_write_outb;       // From axi_elink_if of axi_elink_if.v\n   // End of automatics\n\n   //#########\n   //# Regs\n   //#########\n   \n   //#########\n   //# Wires\n   //#########\n   wire \t    emaxi_reset;\n   wire \t    esaxi_reset;\n   wire \t    rxi_eclk;\n   wire [31:0] \t    elink_dstaddr_inb;\n   wire [31:0] \t    elink_dstaddr_tmp;\n   wire \t    ext_mem_access;\n      \n   //#################\n   //# global signals\n   //#################\n   \n   assign emaxi_reset = ~emaxi_aresetn;\n   assign esaxi_reset = ~esaxi_aresetn;\n\n   //##################################\n   //# AXI Slave Port Instantiation\n   //##################################\n\n   /*axi_slave AUTO_TEMPLATE(.eclk         (rxi_eclk),\n                             .reset        (esaxi_reset),\n                             .aclk\t   (esaxi_aclk),\n                             .aw\\(.*\\)     (esaxi_aw\\1[]),\n                             .w\\(.*\\)      (esaxi_w\\1[]),\n                             .b\\(.*\\)      (esaxi_b\\1[]),\n                             .ar\\(.*\\)     (esaxi_ar\\1[]),\n                             .r\\(.*\\)      (esaxi_r\\1[]),\n                             .emesh_\\(.*\\) (esaxi_\\1[]),\n                            );\n    */                                    \n\n   axi_slave axi_slave(/*AUTOINST*/\n                       // Outputs\n                       .csysack         (csysack),\n                       .cactive         (cactive),\n                       .awready         (esaxi_awready),         // Templated\n                       .wready          (esaxi_wready),          // Templated\n                       .bid             (esaxi_bid[SIDW-1:0]),   // Templated\n                       .bresp           (esaxi_bresp[1:0]),      // Templated\n                       .bvalid          (esaxi_bvalid),          // Templated\n                       .arready         (esaxi_arready),         // Templated\n                       .rid             (esaxi_rid[SIDW-1:0]),   // Templated\n                       .rdata           (esaxi_rdata[SDW-1:0]),  // Templated\n                       .rresp           (esaxi_rresp[1:0]),      // Templated\n                       .rlast           (esaxi_rlast),           // Templated\n                       .rvalid          (esaxi_rvalid),          // Templated\n                       .emesh_access_inb(esaxi_access_inb),      // Templated\n                       .emesh_write_inb (esaxi_write_inb),       // Templated\n                       .emesh_datamode_inb(esaxi_datamode_inb[1:0]), // Templated\n                       .emesh_ctrlmode_inb(esaxi_ctrlmode_inb[3:0]), // Templated\n                       .emesh_dstaddr_inb(esaxi_dstaddr_inb[31:0]), // Templated\n                       .emesh_srcaddr_inb(esaxi_srcaddr_inb[31:0]), // Templated\n                       .emesh_data_inb  (esaxi_data_inb[31:0]),  // Templated\n                       .emesh_wr_wait_inb(esaxi_wr_wait_inb),    // Templated\n                       .emesh_rd_wait_inb(esaxi_rd_wait_inb),    // Templated\n                       // Inputs\n                       .aclk            (esaxi_aclk),            // Templated\n                       .eclk            (rxi_eclk),              // Templated\n                       .reset           (esaxi_reset),           // Templated\n                       .csysreq         (csysreq),\n                       .awid            (esaxi_awid[SIDW-1:0]),  // Templated\n                       .awaddr          (esaxi_awaddr[SAW-1:0]), // Templated\n                       .awlen           (esaxi_awlen[3:0]),      // Templated\n                       .awsize          (esaxi_awsize[2:0]),     // Templated\n                       .awburst         (esaxi_awburst[1:0]),    // Templated\n                       .awlock          (esaxi_awlock[1:0]),     // Templated\n                       .awcache         (esaxi_awcache[3:0]),    // Templated\n                       .awprot          (esaxi_awprot[2:0]),     // Templated\n                       .awvalid         (esaxi_awvalid),         // Templated\n                       .wid             (esaxi_wid[SIDW-1:0]),   // Templated\n                       .wdata           (esaxi_wdata[SDW-1:0]),  // Templated\n                       .wstrb           (esaxi_wstrb[3:0]),      // Templated\n                       .wlast           (esaxi_wlast),           // Templated\n                       .wvalid          (esaxi_wvalid),          // Templated\n                       .bready          (esaxi_bready),          // Templated\n                       .arid            (esaxi_arid[SIDW-1:0]),  // Templated\n                       .araddr          (esaxi_araddr[SAW-1:0]), // Templated\n                       .arlen           (esaxi_arlen[3:0]),      // Templated\n                       .arsize          (esaxi_arsize[2:0]),     // Templated\n                       .arburst         (esaxi_arburst[1:0]),    // Templated\n                       .arlock          (esaxi_arlock[1:0]),     // Templated\n                       .arcache         (esaxi_arcache[3:0]),    // Templated\n                       .arprot          (esaxi_arprot[2:0]),     // Templated\n                       .arvalid         (esaxi_arvalid),         // Templated\n                       .rready          (esaxi_rready),          // Templated\n                       .emesh_access_outb(esaxi_access_outb),    // Templated\n                       .emesh_write_outb(esaxi_write_outb),      // Templated\n                       .emesh_datamode_outb(esaxi_datamode_outb[1:0]), // Templated\n                       .emesh_ctrlmode_outb(esaxi_ctrlmode_outb[3:0]), // Templated\n                       .emesh_dstaddr_outb(esaxi_dstaddr_outb[31:0]), // Templated\n                       .emesh_srcaddr_outb(esaxi_srcaddr_outb[31:0]), // Templated\n                       .emesh_data_outb (esaxi_data_outb[31:0]), // Templated\n                       .emesh_wr_wait_outb(esaxi_wr_wait_outb),  // Templated\n                       .emesh_rd_wait_outb(esaxi_rd_wait_outb),  // Templated\n                       .awqos           (esaxi_awqos[3:0]),      // Templated\n                       .arqos           (esaxi_arqos[3:0]));      // Templated\n   \n   //##################################\n   //# AXI Master Port Instantiation\n   //##################################\n\n   /*axi_master AUTO_TEMPLATE(.eclk         (rxi_eclk),\n                              .reset        (emaxi_reset),\n                              .aclk\t    (emaxi_aclk),\n                              .aw\\(.*\\)     (emaxi_aw\\1[]),\n                              .w\\(.*\\)      (emaxi_w\\1[]),\n                              .b\\(.*\\)      (emaxi_b\\1[]),\n                              .ar\\(.*\\)     (emaxi_ar\\1[]),\n                              .r\\(.*\\)      (emaxi_r\\1[]),\n                              .emesh_\\(.*\\) (emaxi_\\1[]),\n                             );\n    */                                    \n\n   axi_master axi_master(/*AUTOINST*/\n                         // Outputs\n                         .awid                  (emaxi_awid[MIDW-1:0]), // Templated\n                         .awaddr                (emaxi_awaddr[MAW-1:0]), // Templated\n                         .awlen                 (emaxi_awlen[3:0]), // Templated\n                         .awsize                (emaxi_awsize[2:0]), // Templated\n                         .awburst               (emaxi_awburst[1:0]), // Templated\n                         .awlock                (emaxi_awlock[1:0]), // Templated\n                         .awcache               (emaxi_awcache[3:0]), // Templated\n                         .awprot                (emaxi_awprot[2:0]), // Templated\n                         .awvalid               (emaxi_awvalid), // Templated\n                         .wid                   (emaxi_wid[MIDW-1:0]), // Templated\n                         .wdata                 (emaxi_wdata[MDW-1:0]), // Templated\n                         .wstrb                 (emaxi_wstrb[STW-1:0]), // Templated\n                         .wlast                 (emaxi_wlast),   // Templated\n                         .wvalid                (emaxi_wvalid),  // Templated\n                         .bready                (emaxi_bready),  // Templated\n                         .arid                  (emaxi_arid[MIDW-1:0]), // Templated\n                         .araddr                (emaxi_araddr[MAW-1:0]), // Templated\n                         .arlen                 (emaxi_arlen[3:0]), // Templated\n                         .arsize                (emaxi_arsize[2:0]), // Templated\n                         .arburst               (emaxi_arburst[1:0]), // Templated\n                         .arlock                (emaxi_arlock[1:0]), // Templated\n                         .arcache               (emaxi_arcache[3:0]), // Templated\n                         .arprot                (emaxi_arprot[2:0]), // Templated\n                         .arvalid               (emaxi_arvalid), // Templated\n                         .rready                (emaxi_rready),  // Templated\n                         .emesh_access_inb      (emaxi_access_inb), // Templated\n                         .emesh_write_inb       (emaxi_write_inb), // Templated\n                         .emesh_datamode_inb    (emaxi_datamode_inb[1:0]), // Templated\n                         .emesh_ctrlmode_inb    (emaxi_ctrlmode_inb[3:0]), // Templated\n                         .emesh_dstaddr_inb     (emaxi_dstaddr_inb[31:0]), // Templated\n                         .emesh_srcaddr_inb     (emaxi_srcaddr_inb[31:0]), // Templated\n                         .emesh_data_inb        (emaxi_data_inb[31:0]), // Templated\n                         .emesh_wr_wait_inb     (emaxi_wr_wait_inb), // Templated\n                         .emesh_rd_wait_inb     (emaxi_rd_wait_inb), // Templated\n                         .awqos                 (emaxi_awqos[3:0]), // Templated\n                         .arqos                 (emaxi_arqos[3:0]), // Templated\n                         // Inputs\n                         .aclk                  (emaxi_aclk),    // Templated\n                         .eclk                  (rxi_eclk),      // Templated\n                         .reset                 (emaxi_reset),   // Templated\n                         .awready               (emaxi_awready), // Templated\n                         .wready                (emaxi_wready),  // Templated\n                         .bid                   (emaxi_bid[MIDW-1:0]), // Templated\n                         .bresp                 (emaxi_bresp[1:0]), // Templated\n                         .bvalid                (emaxi_bvalid),  // Templated\n                         .arready               (emaxi_arready), // Templated\n                         .rid                   (emaxi_rid[MIDW-1:0]), // Templated\n                         .rdata                 (emaxi_rdata[MDW-1:0]), // Templated\n                         .rresp                 (emaxi_rresp[1:0]), // Templated\n                         .rlast                 (emaxi_rlast),   // Templated\n                         .rvalid                (emaxi_rvalid),  // Templated\n                         .emesh_access_outb     (emaxi_access_outb), // Templated\n                         .emesh_write_outb      (emaxi_write_outb), // Templated\n                         .emesh_datamode_outb   (emaxi_datamode_outb[1:0]), // Templated\n                         .emesh_ctrlmode_outb   (emaxi_ctrlmode_outb[3:0]), // Templated\n                         .emesh_dstaddr_outb    (emaxi_dstaddr_outb[31:0]), // Templated\n                         .emesh_srcaddr_outb    (emaxi_srcaddr_outb[31:0]), // Templated\n                         .emesh_data_outb       (emaxi_data_outb[31:0]), // Templated\n                         .emesh_wr_wait_outb    (emaxi_wr_wait_outb)); // Templated\n\n   //#####################################\n   //# ELINK (CHIP Port) Instantiation\n   //#####################################\n   \n   //# \"manual remapping\" of external memory address seen by the chips\n   assign ext_mem_access = (elink_dstaddr_tmp[31:28] == `VIRT_EXT_MEM) &\n\t\t\t  ~(elink_dstaddr_tmp[31:20] == `AXI_COORD);\n   \n   assign elink_dstaddr_inb[31:28] = ext_mem_access ? `PHYS_EXT_MEM :\n\t\t\t                              elink_dstaddr_tmp[31:28];\n\n   assign elink_dstaddr_inb[27:0] = elink_dstaddr_tmp[27:0];\n      \n   /*ewrapper_link_top AUTO_TEMPLATE(.emesh_clk_inb (rxi_eclk),\n                                     .burst_en      (1'b1),\n                                     .emesh_dstaddr_inb(elink_dstaddr_tmp[31:0]),\n                                     .emesh_\\(.*\\)  (elink_\\1[]),\n                                    );\n    */                                    \n\n   ewrapper_link_top ewrapper_link_top\n     (/*AUTOINST*/\n      // Outputs\n      .emesh_clk_inb                    (rxi_eclk),              // Templated\n      .emesh_access_inb                 (elink_access_inb),      // Templated\n      .emesh_write_inb                  (elink_write_inb),       // Templated\n      .emesh_datamode_inb               (elink_datamode_inb[1:0]), // Templated\n      .emesh_ctrlmode_inb               (elink_ctrlmode_inb[3:0]), // Templated\n      .emesh_dstaddr_inb                (elink_dstaddr_tmp[31:0]), // Templated\n      .emesh_srcaddr_inb                (elink_srcaddr_inb[31:0]), // Templated\n      .emesh_data_inb                   (elink_data_inb[31:0]),  // Templated\n      .emesh_wr_wait_inb                (elink_wr_wait_inb),     // Templated\n      .emesh_rd_wait_inb                (elink_rd_wait_inb),     // Templated\n      .txo_data_p                       (txo_data_p[7:0]),\n      .txo_data_n                       (txo_data_n[7:0]),\n      .txo_frame_p                      (txo_frame_p),\n      .txo_frame_n                      (txo_frame_n),\n      .txo_lclk_p                       (txo_lclk_p),\n      .txo_lclk_n                       (txo_lclk_n),\n      .rxo_wr_wait_p                    (rxo_wr_wait_p),\n      .rxo_wr_wait_n                    (rxo_wr_wait_n),\n      .rxo_rd_wait_p                    (rxo_rd_wait_p),\n      .rxo_rd_wait_n                    (rxo_rd_wait_n),\n      .rxi_cclk_p                       (rxi_cclk_p),\n      .rxi_cclk_n                       (rxi_cclk_n),\n      // Inputs\n      .reset                            (reset),\n      .clkin_100                        (clkin_100),\n      .elink_disable                    (elink_disable),\n      .elink_cclk_enb                   (elink_cclk_enb),\n      .elink_clk_div                    (elink_clk_div[1:0]),\n      .emesh_access_outb                (elink_access_outb),     // Templated\n      .emesh_write_outb                 (elink_write_outb),      // Templated\n      .emesh_datamode_outb              (elink_datamode_outb[1:0]), // Templated\n      .emesh_ctrlmode_outb              (elink_ctrlmode_outb[3:0]), // Templated\n      .emesh_dstaddr_outb               (elink_dstaddr_outb[31:0]), // Templated\n      .emesh_srcaddr_outb               (elink_srcaddr_outb[31:0]), // Templated\n      .emesh_data_outb                  (elink_data_outb[31:0]), // Templated\n      .emesh_wr_wait_outb               (elink_wr_wait_outb),    // Templated\n      .emesh_rd_wait_outb               (elink_rd_wait_outb),    // Templated\n      .rxi_data_p                       (rxi_data_p[7:0]),\n      .rxi_data_n                       (rxi_data_n[7:0]),\n      .rxi_frame_p                      (rxi_frame_p),\n      .rxi_frame_n                      (rxi_frame_n),\n      .rxi_lclk_p                       (rxi_lclk_p),\n      .rxi_lclk_n                       (rxi_lclk_n),\n      .txi_wr_wait_p                    (txi_wr_wait_p),\n      .txi_wr_wait_n                    (txi_wr_wait_n),\n      .txi_rd_wait_p                    (txi_rd_wait_p),\n      .txi_rd_wait_n                    (txi_rd_wait_n),\n      .burst_en                         (1'b1));                  // Templated\n   \n   //####################################\n   //# AXI-ELINK Interface Instantiation\n   //####################################\n\n   /*axi_elink_if AUTO_TEMPLATE(.eclk (rxi_eclk),\n                                .aclk (esaxi_aclk),\n                               );\n    */\n\n   axi_elink_if axi_elink_if\n     (/*AUTOINST*/\n      // Outputs\n      .reset_chip                       (reset_chip),\n      .reset_fpga                       (reset_fpga),\n      .emaxi_access_outb                (emaxi_access_outb),\n      .emaxi_write_outb                 (emaxi_write_outb),\n      .emaxi_datamode_outb              (emaxi_datamode_outb[1:0]),\n      .emaxi_ctrlmode_outb              (emaxi_ctrlmode_outb[3:0]),\n      .emaxi_dstaddr_outb               (emaxi_dstaddr_outb[31:0]),\n      .emaxi_srcaddr_outb               (emaxi_srcaddr_outb[31:0]),\n      .emaxi_data_outb                  (emaxi_data_outb[31:0]),\n      .emaxi_wr_wait_outb               (emaxi_wr_wait_outb),\n      .esaxi_access_outb                (esaxi_access_outb),\n      .esaxi_write_outb                 (esaxi_write_outb),\n      .esaxi_datamode_outb              (esaxi_datamode_outb[1:0]),\n      .esaxi_ctrlmode_outb              (esaxi_ctrlmode_outb[3:0]),\n      .esaxi_dstaddr_outb               (esaxi_dstaddr_outb[31:0]),\n      .esaxi_srcaddr_outb               (esaxi_srcaddr_outb[31:0]),\n      .esaxi_data_outb                  (esaxi_data_outb[31:0]),\n      .esaxi_wr_wait_outb               (esaxi_wr_wait_outb),\n      .esaxi_rd_wait_outb               (esaxi_rd_wait_outb),\n      .elink_access_outb                (elink_access_outb),\n      .elink_write_outb                 (elink_write_outb),\n      .elink_datamode_outb              (elink_datamode_outb[1:0]),\n      .elink_ctrlmode_outb              (elink_ctrlmode_outb[3:0]),\n      .elink_dstaddr_outb               (elink_dstaddr_outb[31:0]),\n      .elink_srcaddr_outb               (elink_srcaddr_outb[31:0]),\n      .elink_data_outb                  (elink_data_outb[31:0]),\n      .elink_wr_wait_outb               (elink_wr_wait_outb),\n      .elink_rd_wait_outb               (elink_rd_wait_outb),\n      .elink_disable                    (elink_disable),\n      .elink_cclk_enb                   (elink_cclk_enb),\n      .elink_clk_div                    (elink_clk_div[1:0]),\n      // Inputs\n      .eclk                             (rxi_eclk),              // Templated\n      .aclk                             (esaxi_aclk),            // Templated\n      .reset                            (reset),\n      .emaxi_access_inb                 (emaxi_access_inb),\n      .emaxi_write_inb                  (emaxi_write_inb),\n      .emaxi_datamode_inb               (emaxi_datamode_inb[1:0]),\n      .emaxi_ctrlmode_inb               (emaxi_ctrlmode_inb[3:0]),\n      .emaxi_dstaddr_inb                (emaxi_dstaddr_inb[31:0]),\n      .emaxi_srcaddr_inb                (emaxi_srcaddr_inb[31:0]),\n      .emaxi_data_inb                   (emaxi_data_inb[31:0]),\n      .emaxi_wr_wait_inb                (emaxi_wr_wait_inb),\n      .emaxi_rd_wait_inb                (emaxi_rd_wait_inb),\n      .esaxi_access_inb                 (esaxi_access_inb),\n      .esaxi_write_inb                  (esaxi_write_inb),\n      .esaxi_datamode_inb               (esaxi_datamode_inb[1:0]),\n      .esaxi_ctrlmode_inb               (esaxi_ctrlmode_inb[3:0]),\n      .esaxi_dstaddr_inb                (esaxi_dstaddr_inb[31:0]),\n      .esaxi_srcaddr_inb                (esaxi_srcaddr_inb[31:0]),\n      .esaxi_data_inb                   (esaxi_data_inb[31:0]),\n      .esaxi_wr_wait_inb                (esaxi_wr_wait_inb),\n      .esaxi_rd_wait_inb                (esaxi_rd_wait_inb),\n      .elink_access_inb                 (elink_access_inb),\n      .elink_write_inb                  (elink_write_inb),\n      .elink_datamode_inb               (elink_datamode_inb[1:0]),\n      .elink_ctrlmode_inb               (elink_ctrlmode_inb[3:0]),\n      .elink_dstaddr_inb                (elink_dstaddr_inb[31:0]),\n      .elink_srcaddr_inb                (elink_srcaddr_inb[31:0]),\n      .elink_data_inb                   (elink_data_inb[31:0]),\n      .elink_wr_wait_inb                (elink_wr_wait_inb),\n      .elink_rd_wait_inb                (elink_rd_wait_inb));\n   \nendmodule // parallella\n\n    // Local Variables:\n    // verilog-library-directories:(\".\" \"../elink\" \"../axi\")\n    // End:\n"
  },
  {
    "path": "contrib/parallella/testmain.cpp",
    "content": "/* Copyright (c) 2014 Quanta Research Cambridge, Inc\n *\n * Permission is hereby granted, free of charge, to any person obtaining a\n * copy of this software and associated documentation files (the \"Software\"),\n * to deal in the Software without restriction, including without limitation\n * the rights to use, copy, modify, merge, publish, distribute, sublicense,\n * and/or sell copies of the Software, and to permit persons to whom the\n * Software is furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n * DEALINGS IN THE SOFTWARE.\n */\n\n#include <stdio.h>\n#include <assert.h>\n\n\nint main(int argc, const char **argv)\n{\n\n  printf( \"Hello world\\n\");\n}\n"
  },
  {
    "path": "contrib/perf/Makefile",
    "content": "\nCONNECTALDIR?=../..\nINTERFACES = PerfRequest PerfIndication\nBSVFILES = Perf.bsv Top.bsv $(CONNECTALDIR)/lib/deprecated/DmaUtils.bsv\nCPPFILES=testperf.cpp\n\ninclude $(CONNECTALDIR)/Makefile.connectal\n"
  },
  {
    "path": "contrib/perf/Perf.bsv",
    "content": "// Copyright (c) 2013 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\nimport Vector::*;\nimport FIFOF::*;\nimport GetPut::*;\n\nimport ConnectalMemory::*;\nimport ConnectalMemTypes::*;\n\ninterface PerfRequest;\n   method Action startCopy(Bit#(32) wrPointer, Bit#(32) rdPointer, Bit#(32) numWords, Bit#(32) repeatCount);\n   method Action readWord();\n   method Action getStateDbg();   \nendinterface\n\ninterface PerfIndication;\n   method Action started(Bit#(32) numWords);\n   method Action readWordResult(Bit#(32) v);\n   method Action done(Bit#(32) dataMismatch);\n   method Action rData(Bit#(64) v);\n   method Action readReq(Bit#(32) v);\n   method Action writeReq(Bit#(32) v);\n   method Action writeAck(Bit#(32) v);\n   method Action reportStateDbg(Bit#(32) srcGen, Bit#(32) streamRdCnt, Bit#(32) streamWrCnt, Bit#(32) writeInProg, Bit#(32) dataMismatch);\nendinterface\n\nmodule mkPerfRequest#(PerfIndication indication,\n\t\t\tMemReadServer#(busWidth) dma_stream_read_server,\n\t\t\tMemWriteServer#(busWidth) dma_stream_write_server,\n\t\t\tMemReadServer#(busWidth) dma_word_read_server)\n   (PerfRequest)\n   provisos (Div#(busWidth,8,busWidthBytes),\n\t     Add#(a__,32,busWidth));\n\n   let busWidthBytes = valueOf(busWidthBytes);\n   let busWidthWords = busWidthBytes/4;\n\n   Reg#(Bit#(32))      srcGen <- mkReg(0);\n   Reg#(Bit#(32)) byteCnt <- mkReg(0);\n   Reg#(Bit#(32)) streamRdCnt <- mkReg(0);\n   Reg#(Bit#(32)) streamWrCnt <- mkReg(0);\n   Reg#(Bit#(32)) streamAckCnt <- mkReg(0);\n   Reg#(Bit#(32)) repeatCnt <- mkReg(0);\n   Reg#(Bit#(MemOffsetSize)) streamRdOff <- mkReg(0);\n   Reg#(Bit#(MemOffsetSize)) streamWrOff <- mkReg(0);\n   Reg#(SGLId)    streamRdPointer <- mkReg(0);\n   Reg#(SGLId)    streamWrPointer <- mkReg(0);\n   Reg#(Bool)               writeInProg <- mkReg(False);\n   Reg#(Bool)               iterInProg <- mkReg(False);\n   Reg#(Bool)              dataMismatch <- mkReg(False);  \n   \n   Reg#(Bit#(8)) burstLen <- mkReg(8*fromInteger(busWidthBytes));\n   Reg#(Bit#(MemOffsetSize)) deltaOffset <- mkReg(8*fromInteger(busWidthBytes));\n\n   rule readReq(streamRdCnt > 0);\n      streamRdCnt <= streamRdCnt - extend(burstLen);\n      streamRdOff <= streamRdOff + deltaOffset;\n      //$display(\"readReq.put pointer=%h address=%h, burstlen=%h\", streamRdPointer, streamRdOff, burstLen);\n      dma_stream_read_server.readReq.put(MemRequest {sglId: streamRdPointer, offset: streamRdOff, burstLen: extend(burstLen), tag: truncate(streamRdOff>>5)});\n      //indication.readReq(streamRdCnt);\n   endrule\n\n   rule writeReq(streamWrCnt > 0 && !writeInProg);\n      writeInProg <= True;\n      streamWrCnt <= streamWrCnt-extend(burstLen);\n      streamWrOff <= streamWrOff + deltaOffset;\n      //$display(\"writeReq.put pointer=%h address=%h\", streamWrPointer, streamWrOff);\n      dma_stream_write_server.writeReq.put(MemRequest {sglId: streamWrPointer, offset: streamWrOff, burstLen: extend(burstLen), tag: truncate(streamWrOff>>5)});\n      //indication.writeReq(streamWrCnt);\n   endrule\n   \n   rule writeAck(writeInProg);\n      writeInProg <= False;\n      let tag <- dma_stream_write_server.writeDone.get();\n      //$display(\"writeAck: tag=%d\", tag);\n      streamAckCnt <= streamAckCnt-extend(burstLen);\n      //indication.writeAck(streamAckCnt);\n      if(streamAckCnt==extend(burstLen)) begin\n\t if (repeatCnt == 0) indication.done(0);\n\t iterInProg <= False;\n\t end\n   endrule\n\n   rule loopback;\n      let tagdata <- dma_stream_read_server.readData.get();\n      let v = tagdata.data;\n      Bool mismatch = False;\n      //for (Integer i = 0; i < busWidthWords; i = i+1)\n\t// mismatch = mismatch || (v[31+i*32:i*32] != (srcGen + fromInteger(i)));\n      //dataMismatch <= dataMismatch || mismatch;\n      dma_stream_write_server.writeData.put(tagdata);\n      srcGen <= srcGen+fromInteger(busWidthWords);\n      //$display(\"loopback %h\", tagdata.data);\n      // indication.rData(v);\n   endrule\n   \n   rule readWordResp;\n      let tagdata <- dma_word_read_server.readData.get;\n      indication.readWordResult(truncate(tagdata.data));\n   endrule\n   \n   rule startIteration((iterInProg == False) && (repeatCnt > 0));\n      streamRdOff <= 0;\n      streamWrOff <= 0;\n      streamRdCnt <= byteCnt;\n      streamWrCnt <= byteCnt;\n      streamAckCnt <= byteCnt;\n      iterInProg <= True;\n      repeatCnt <= repeatCnt - 1;\n   endrule\n   \n   method Action startCopy(Bit#(32) wrPointer, Bit#(32) rdPointer, Bit#(32) numWords, Bit#(32) repeatCount) if (streamRdCnt == 0 && streamWrCnt == 0);\n      //$display(\"startCopy wrPointer=%h rdPointer=%h numWords=%d\", wrPointer, rdPointer, numWords);\n      streamWrPointer <= wrPointer;\n      streamRdPointer <= rdPointer;\n      byteCnt <= numWords << 2;\n      repeatCnt <= repeatCount;\n      indication.started(numWords);\n   endmethod\n\n   method Action readWord();\n      dma_word_read_server.readReq.put(MemRequest {sglId: streamWrPointer, offset: 0, burstLen: fromInteger(busWidthBytes), tag: 1});\n   endmethod\n\n   method Action getStateDbg();\n      indication.reportStateDbg(srcGen, streamRdCnt, streamWrCnt, writeInProg ? 32'd1 : 32'd0, dataMismatch  ? 32'd1 : 32'd0);\n   endmethod\n\nendmodule\n"
  },
  {
    "path": "contrib/perf/Top.bsv",
    "content": "/* Copyright (c) 2014 Quanta Research Cambridge, Inc\n *\n * Permission is hereby granted, free of charge, to any person obtaining a\n * copy of this software and associated documentation files (the \"Software\"),\n * to deal in the Software without restriction, including without limitation\n * the rights to use, copy, modify, merge, publish, distribute, sublicense,\n * and/or sell copies of the Software, and to permit persons to whom the\n * Software is furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n * DEALINGS IN THE SOFTWARE.\n */\nimport SpecialFIFOs::*;\nimport Vector::*;\nimport StmtFSM::*;\nimport FIFO::*;\nimport CtrlMux::*;\nimport Portal::*;\nimport HostInterface::*;\nimport ConnectalMemory::*;\nimport DmaUtils::*;\nimport ConnectalMemTypes::*;\nimport MemServer::*;\nimport ConnectalMMU::*;\nimport PerfRequest::*;\nimport MemServerRequest::*;\nimport MMURequest::*;\nimport PerfIndication::*;\nimport MemServerIndication::*;\nimport MMUIndication::*;\nimport Perf::*;\n\ntypedef enum {IfcNames_PerfIndication, IfcNames_PerfRequest, IfcNames_HostMemServerIndication, IfcNames_HostMemServerRequest, IfcNames_HostMMURequest, IfcNames_HostMMUIndication} IfcNames deriving (Eq,Bits);\n\nmodule mkConnectalTop(StdConnectalDmaTop#(PhysAddrWidth));\n\n   DmaReadBuffer#(64,8)   dma_stream_read_chan <- mkDmaReadBuffer();\n   DmaWriteBuffer#(64,8) dma_stream_write_chan <- mkDmaWriteBuffer();\n   DmaReadBuffer#(64,8)     dma_word_read_chan <- mkDmaReadBuffer();\n   DmaWriteBuffer#(64,8)  dma_debug_write_chan <- mkDmaWriteBuffer();\n\n   Vector#(2,  MemReadClient#(64))   readClients = newVector();\n   readClients[0] = dma_stream_read_chan.dmaClient;\n   readClients[1] = dma_word_read_chan.dmaClient;\n\n   Vector#(2, MemWriteClient#(64)) writeClients = newVector();\n   writeClients[0] = dma_stream_write_chan.dmaClient;\n   writeClients[1] = dma_debug_write_chan.dmaClient;\n\n   MMUIndicationProxy hostMMUIndicationProxy <- mkMMUIndicationProxy(IfcNames_HostMMUIndication);\n   MMU#(PhysAddrWidth) hostMMU <- mkMMU(0, True, hostMMUIndicationProxy.ifc);\n   MMURequestWrapper hostMMURequestWrapper <- mkMMURequestWrapper(IfcNames_HostMMURequest, hostMMU.request);\n\n   MemServerIndicationProxy hostMemServerIndicationProxy <- mkMemServerIndicationProxy(IfcNames_HostMemServerIndication);\n   MemServer#(PhysAddrWidth,64,1) dma <- mkMemServer(readClients, writeClients, cons(hostMMU,nil), hostMemServerIndicationProxy.ifc);\n   MemServerRequestWrapper hostMemServerRequestWrapper <- mkMemServerRequestWrapper(IfcNames_HostMemServerRequest, dma.request);\n\n   PerfIndicationProxy perfIndicationProxy <- mkPerfIndicationProxy(IfcNames_PerfIndication);\n   PerfRequest perfRequest <- mkPerfRequest(perfIndicationProxy.ifc, dma_stream_read_chan.dmaServer,\n\t\t\t\t\t\t  dma_stream_write_chan.dmaServer, dma_word_read_chan.dmaServer);\n   PerfRequestWrapper perfRequestWrapper <- mkPerfRequestWrapper(IfcNames_PerfRequest,perfRequest);\n\n   Vector#(6,StdPortal) portals;\n   portals[0] = perfRequestWrapper.portalIfc;\n   portals[1] = perfIndicationProxy.portalIfc; \n   portals[2] = hostMemServerRequestWrapper.portalIfc;\n   portals[3] = hostMemServerIndicationProxy.portalIfc; \n   portals[4] = hostMMURequestWrapper.portalIfc;\n   portals[5] = hostMMUIndicationProxy.portalIfc;\n   let ctrl_mux <- mkSlaveMux(portals);\n   \n   interface interrupt = getInterruptVector(portals);\n   interface slave = ctrl_mux;\n   interface masters = dma.masters;\nendmodule\n\n\n"
  },
  {
    "path": "contrib/perf/testperf.cpp",
    "content": "/* Copyright (c) 2013 Quanta Research Cambridge, Inc\n *\n * Permission is hereby granted, free of charge, to any person obtaining a\n * copy of this software and associated documentation files (the \"Software\"),\n * to deal in the Software without restriction, including without limitation\n * the rights to use, copy, modify, merge, publish, distribute, sublicense,\n * and/or sell copies of the Software, and to permit persons to whom the\n * Software is furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n * DEALINGS IN THE SOFTWARE.\n */\n#include <sys/time.h>\n#include <semaphore.h>\n#include \"dmaManager.h\"\n#include \"PerfIndication.h\"\n#include \"PerfRequest.h\"\n\nsem_t copy_sem;\n\nPerfRequestProxy *device = 0;\nMMURequestProxy *dmap = 0;\n  \nint srcAlloc;\nint dstAlloc;\nunsigned int *srcBuffer = 0;\nunsigned int *dstBuffer = 0;\nint numWords;\nsize_t test_sz  = (1 << 20) *sizeof(unsigned int);\nsize_t alloc_sz = test_sz;\nunsigned int finishedCount;\nunsigned int ref_srcAlloc;\nunsigned int ref_dstAlloc;\n\nbool memcmp_fail = false;\nunsigned int memcmp_count = 0;\nunsigned int start_count = 0;\nunsigned int copy_size = 0;\n\nvoid dump(const char *prefix, char *buf, size_t len)\n{\n    fprintf(stderr, \"%s \", prefix);\n    for (int i = 0; i < len ; i++) {\n\tfprintf(stderr, \"%02x\", (unsigned char)buf[i]);\n\tif (i % 32 == 31)\n\t  fprintf(stderr, \"\\n\");\n    }\n    fprintf(stderr, \"\\n\");\n}\n\nclass PerfIndication : public PerfIndicationWrapper\n{\n\npublic:\n  PerfIndication(unsigned int id) : PerfIndicationWrapper(id){}\n\n\n  virtual void started(uint32_t words){\n    // fprintf(stderr, \"started: words=%ld\\n\", words);\n    start_count += 1;\n    if (copy_size == 0) sem_post(&copy_sem);\n  }\n  virtual void readWordResult ( uint32_t v ){\n    dump(\"readWordResult: \", (char*)&v, sizeof(v));\n  }\n  virtual void done(uint32_t v) {\n    finishedCount += 1;\n    sem_post(&copy_sem);\n  }\n  virtual void rData ( uint64_t v ){\n    dump(\"rData: \", (char*)&v, sizeof(v));\n  }\n  virtual void readReq(uint32_t v){\n    //fprintf(stderr, \"readReq %lx\\n\", v);\n  }\n  virtual void writeReq(uint32_t v){\n    //fprintf(stderr, \"writeReq %lx\\n\", v);\n  }\n  virtual void writeAck(uint32_t v){\n    //fprintf(stderr, \"writeAck %lx\\n\", v);\n  }\n  virtual void reportStateDbg(uint32_t srcGen, uint32_t streamRdCnt, \n\t\t\t      uint32_t streamWrCnt, uint32_t writeInProg, \n\t\t\t      uint32_t dataMismatch){\n    fprintf(stderr, \"Perf::reportStateDbg: srcGen=%d, streamRdCnt=%d, streamWrCnt=%d, writeInProg=%d, dataMismatch=%d\\n\", \n\t    srcGen, streamRdCnt, streamWrCnt, writeInProg, dataMismatch);\n  }  \n};\nPerfIndication *deviceIndication = 0;\n\n\n// we can use the data synchronization barrier instead of flushing the \n// cache only because the ps7 is configured to run in buffered-write mode\n//\n// an opc2 of '4' and CRm of 'c10' encodes \"CP15DSB, Data Synchronization Barrier \n// operation\". this is a legal instruction to execute in non-privileged mode (mdk)\n//\n// #define DATA_SYNC_BARRIER   __asm __volatile( \"MCR p15, 0, %0, c7, c10, 4\" ::  \"r\" (0) );\n\nlong long deltatime( struct timeval start, struct timeval stop)\n{\n  long long diff = ((long long) (stop.tv_sec - start.tv_sec)) * 1000000;\n  diff = diff + ((long long) (stop.tv_usec - start.tv_usec));\n  return (diff);\n}\n\nint dotest(unsigned size, unsigned repeatCount)\n{\n  struct timeval start, stop;\n  unsigned loops = 1;\n  unsigned int i;\n  long long interval;\n  fprintf(stderr, \"repeat %d size %d loop \", repeatCount, size);\n  for(;;) {\n    finishedCount = 0;\n    copy_size = size;\n    fprintf(stderr, \" %d\", loops);\n    gettimeofday(&start, NULL);\n    for (i = 0; i < loops; i += 1) {\n      device->startCopy(ref_dstAlloc, ref_srcAlloc, numWords, repeatCount);\n      sem_wait(&copy_sem);\n    }\n    gettimeofday(&stop, NULL);\n    interval = deltatime(start, stop);\n    if (interval >= 500000) break;\n    loops <<= 1;\n  }\n  fprintf(stderr, \"\\n  block size %d microseconds %lld\\n\", size*16, interval / loops); \n}\n\nint main(int argc, const char **argv)\n{\n  unsigned int srcGen = 0;\n  unsigned repeatCount = 0;\n\n  fprintf(stderr, \"%s %s\\n\", __DATE__, __TIME__);\n\n    DmaManager *dma = platformInit();\n  device = new PerfRequestProxy(IfcNames_PerfRequest);\n  deviceIndication = new PerfIndication(IfcNames_PerfIndication);\n\n  fprintf(stderr, \"Main::allocating memory...\\n\");\n\n  srcAlloc = portalAlloc(alloc_sz, 0);\n  dstAlloc = portalAlloc(alloc_sz, 0);\n\n  srcBuffer = (unsigned int *)portalMmap(srcAlloc, alloc_sz);\n  dstBuffer = (unsigned int *)portalMmap(dstAlloc, alloc_sz);\n\n  portalCacheFlush(srcAlloc, srcBuffer, alloc_sz, 1);\n  portalCacheFlush(dstAlloc, dstBuffer, alloc_sz, 1);\n  fprintf(stderr, \"Main::flush and invalidate complete\\n\");\n\n  ref_srcAlloc = dma->reference(srcAlloc);\n  ref_dstAlloc = dma->reference(dstAlloc);\n  fprintf(stderr, \"ref_srcAlloc %d\\n\", ref_srcAlloc);\n  fprintf(stderr, \"ref_dstAlloc %d\\n\", ref_dstAlloc);\n  //fprintf(stderr, \"Main::starting mempcy numWords:%d\\n\", 0);\n  \n  //dotest(0);\n  for (repeatCount = 1; repeatCount <= 16; repeatCount <<= 1) {\n    fprintf(stderr, \"Main::starting mempcy repeatCount:%d\\n\", repeatCount);\n    for (numWords = 16; numWords < (1 << 16); numWords <<= 1){\n    \n      //fprintf(stderr, \"Main::starting mempcy numWords:%d\\n\", numWords);\n      \n      dotest(numWords, repeatCount);\n    }\n  }\n\n  device->getStateDbg();\n  fprintf(stderr, \"Main::exiting\\n\");\n}\n"
  },
  {
    "path": "contrib/pipe_mul/Makefile",
    "content": "CONNECTALDIR?=../..\nINTERFACES = PipeMulRequest PipeMulIndication\n\nBSVFILES = PipeMulTB.bsv  Top.bsv\nCPPFILES=testpipe_mul.cpp\n\ninclude $(CONNECTALDIR)/Makefile.connectal\n"
  },
  {
    "path": "contrib/pipe_mul/PipeMulTB.bsv",
    "content": "\n// Copyright (c) 2013 Nokia, Inc.\n// Copyright (c) 2013 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\nimport FIFO::*;\nimport PipeMul::*;\n\ninterface PipeMulIndication;\n    method Action res(Bit#(32) v);\nendinterface\n\ninterface PipeMulRequest;\n   method Action mul(Bit#(32) x, Bit#(32) y);\nendinterface\n\ninterface PipeMulTB;\n   interface PipeMulRequest ifc;\nendinterface\n\nmodule mkPipeMulTB#(PipeMulIndication indication)(PipeMulTB);\n   PipeMul#(1,16,void) multiplier <- mkPipeMul;\n   rule res;\n      match {.rv, .*} <- multiplier.get;\n      indication.res(pack(extend(rv)));\n   endrule\n   interface PipeMulRequest ifc;\n      method Action mul(Bit#(32) a, Bit#(32) b);\n\t multiplier.put(unpack(truncate(a)),unpack(truncate(b)),?);\n      endmethod\n   endinterface\nendmodule\n"
  },
  {
    "path": "contrib/pipe_mul/Top.bsv",
    "content": "/* Copyright (c) 2014 Quanta Research Cambridge, Inc\n *\n * Permission is hereby granted, free of charge, to any person obtaining a\n * copy of this software and associated documentation files (the \"Software\"),\n * to deal in the Software without restriction, including without limitation\n * the rights to use, copy, modify, merge, publish, distribute, sublicense,\n * and/or sell copies of the Software, and to permit persons to whom the\n * Software is furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n * DEALINGS IN THE SOFTWARE.\n */\nimport Vector::*;\nimport FIFO::*;\nimport Connectable::*;\nimport Portal::*;\nimport HostInterface::*;\nimport CtrlMux::*;\nimport PipeMulIndication::*;\nimport PipeMulRequest::*;\nimport PipeMulTB::*;\n\ntypedef enum {IfcNames_PipeMulIndication, IfcNames_PipeMulRequest} IfcNames deriving (Eq,Bits);\n\nmodule mkConnectalTop(StdConnectalTop#(PhysAddrWidth));\n   PipeMulIndicationProxy indProxy <- mkPipeMulIndicationProxy(IfcNames_PipeMulIndication);\n   PipeMulTB pmTB <- mkPipeMulTB(indProxy.ifc);\n   PipeMulRequestWrapper reqWrapper <- mkPipeMulRequestWrapper(IfcNames_PipeMulRequest,pmTB.ifc);\n   \n   Vector#(2,StdPortal) portals;\n   portals[0] = indProxy.portalIfc;\n   portals[1] = reqWrapper.portalIfc; \n   let ctrl_mux <- mkSlaveMux(portals);\n   \n   interface interrupt = getInterruptVector(portals);\n   interface slave = ctrl_mux;\n   interface masters = nil;\nendmodule : mkConnectalTop\n"
  },
  {
    "path": "contrib/pipe_mul/testpipe_mul.cpp",
    "content": "/* Copyright (c) 2014 Quanta Research Cambridge, Inc\n *\n * Permission is hereby granted, free of charge, to any person obtaining a\n * copy of this software and associated documentation files (the \"Software\"),\n * to deal in the Software without restriction, including without limitation\n * the rights to use, copy, modify, merge, publish, distribute, sublicense,\n * and/or sell copies of the Software, and to permit persons to whom the\n * Software is furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n * DEALINGS IN THE SOFTWARE.\n */\n\n#include <stdio.h>\n#include <stdlib.h>\n#include <semaphore.h>\n#include <unistd.h>\n\n#include \"PipeMulIndication.h\"\n#include \"PipeMulRequest.h\"\n#include \"GeneratedTypes.h\"\n\n\nclass PipeMulIndication : public PipeMulIndicationWrapper\n{\npublic:\n    virtual void res(uint32_t v) {\n      fprintf(stderr, \"res: %d\\n\", v);\n      exit(0);\n    }\n    PipeMulIndication(unsigned int id) : PipeMulIndicationWrapper(id) {}\n};\n\n\nint main(int argc, const char **argv)\n{\n  PipeMulIndication *indication = new PipeMulIndication(IfcNames_PipeMulIndication);\n  PipeMulRequestProxy *device = new PipeMulRequestProxy(IfcNames_PipeMulRequest);\n  device->mul(3,4);  \n  while(true);\n}\n"
  },
  {
    "path": "contrib/pipe_mul2/Makefile",
    "content": "CONNECTALDIR?=../..\nINTERFACES = PipeMulRequest PipeMulIndication\n\nBSVFILES = PipeMulTB.bsv  Top.bsv\nCPPFILES=testpipe_mul.cpp\n\ninclude $(CONNECTALDIR)/Makefile.connectal\n"
  },
  {
    "path": "contrib/pipe_mul2/PipeMulTB.bsv",
    "content": "\n// Copyright (c) 2013 Nokia, Inc.\n// Copyright (c) 2013 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\nimport FIFO::*;\nimport PipeMul::*;\n\ninterface PipeMulIndication;\n    method Action res(Bit#(64) v);\nendinterface\n\ninterface PipeMulRequest;\n   method Action mul(Bit#(32) x, Bit#(32) y);\nendinterface\n\ninterface PipeMulTB;\n   interface PipeMulRequest ifc;\nendinterface\n\n(* synthesize *)\nmodule mkPipeMul2Synth(PipeMul2#(2,24,void));\n   let pm <- mkPipeMul2();\n   return pm;\nendmodule\n\nmodule mkPipeMulTB#(PipeMulIndication indication)(PipeMulTB);\n   PipeMul2#(2,24,void) multiplier <- mkPipeMul2Synth;\n   rule res;\n      match {.rv, .*} <- multiplier.get;\n      indication.res(extend(pack(rv)));\n   endrule\n   interface PipeMulRequest ifc;\n      method Action mul(Bit#(32) a, Bit#(32) b);\n\t multiplier.put(unpack(truncate(a)),unpack(truncate(b)),?);\n      endmethod\n   endinterface\nendmodule\n"
  },
  {
    "path": "contrib/pipe_mul2/Top.bsv",
    "content": "/* Copyright (c) 2014 Quanta Research Cambridge, Inc\n *\n * Permission is hereby granted, free of charge, to any person obtaining a\n * copy of this software and associated documentation files (the \"Software\"),\n * to deal in the Software without restriction, including without limitation\n * the rights to use, copy, modify, merge, publish, distribute, sublicense,\n * and/or sell copies of the Software, and to permit persons to whom the\n * Software is furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n * DEALINGS IN THE SOFTWARE.\n */\nimport Vector::*;\nimport FIFO::*;\nimport Connectable::*;\nimport Portal::*;\nimport HostInterface::*;\nimport CtrlMux::*;\nimport PipeMulIndication::*;\nimport PipeMulRequest::*;\nimport PipeMulTB::*;\n\ntypedef enum {IfcNames_PipeMulIndication, IfcNames_PipeMulRequest} IfcNames deriving (Eq,Bits);\n\nmodule mkConnectalTop(StdConnectalTop#(PhysAddrWidth));\n   PipeMulIndicationProxy indProxy <- mkPipeMulIndicationProxy(IfcNames_PipeMulIndication);\n   PipeMulTB pmTB <- mkPipeMulTB(indProxy.ifc);\n   PipeMulRequestWrapper reqWrapper <- mkPipeMulRequestWrapper(IfcNames_PipeMulRequest,pmTB.ifc);\n   \n   Vector#(2,StdPortal) portals;\n   portals[0] = indProxy.portalIfc;\n   portals[1] = reqWrapper.portalIfc; \n   let ctrl_mux <- mkSlaveMux(portals);\n   \n   interface interrupt = getInterruptVector(portals);\n   interface slave = ctrl_mux;\n   interface masters = nil;\nendmodule : mkConnectalTop\n"
  },
  {
    "path": "contrib/pipe_mul2/testpipe_mul.cpp",
    "content": "/* Copyright (c) 2014 Quanta Research Cambridge, Inc\n *\n * Permission is hereby granted, free of charge, to any person obtaining a\n * copy of this software and associated documentation files (the \"Software\"),\n * to deal in the Software without restriction, including without limitation\n * the rights to use, copy, modify, merge, publish, distribute, sublicense,\n * and/or sell copies of the Software, and to permit persons to whom the\n * Software is furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n * DEALINGS IN THE SOFTWARE.\n */\n\n#include <stdio.h>\n#include <stdlib.h>\n#include <semaphore.h>\n#include <unistd.h>\n\n#include \"PipeMulIndication.h\"\n#include \"PipeMulRequest.h\"\n#include \"GeneratedTypes.h\"\n\n\nclass PipeMulIndication : public PipeMulIndicationWrapper\n{\npublic:\n    virtual void res(uint64_t v) {\n      fprintf(stderr, \"res: %lld\\n\", (long long)v);\n      exit(0);\n    }\n    PipeMulIndication(unsigned int id) : PipeMulIndicationWrapper(id) {}\n};\n\n\nint main(int argc, const char **argv)\n{\n  PipeMulIndication *indication = new PipeMulIndication(IfcNames_PipeMulIndication);\n  PipeMulRequestProxy *device = new PipeMulRequestProxy(IfcNames_PipeMulRequest);\n  device->mul(3,4);  \n  while(true);\n}\n"
  },
  {
    "path": "contrib/portalperf/Makefile",
    "content": "CONNECTALDIR?=../..\nINTERFACES = PortalPerfRequest PortalPerfIndication\n\nBSVFILES = Repeat.bsv PortalPerf.bsv Top.bsv\nCPPFILES=testportalperf.cpp\n\ninclude $(CONNECTALDIR)/Makefile.connectal\n"
  },
  {
    "path": "contrib/portalperf/PortalPerf.bsv",
    "content": "\n// Copyright (c) 2013 Nokia, Inc.\n// Copyright (c) 2013 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\nimport Repeat::*;\nimport Vector::*;\n\ninterface PortalPerfRequest;\n   method Action swallow();\n   method Action swallowl(Bit#(32) v1);\n   method Action swallowll(Bit#(32) v1, Bit#(32) v2);\n   method Action swallowlll(Bit#(32) v1, Bit#(32) v2, Bit#(32) v3);\n   method Action swallowllll(Bit#(32) v1, Bit#(32) v2, Bit#(32) v3, Bit#(32) v4);\n   method Action swallowd(Bit#(64) v1);\n   method Action swallowdd(Bit#(64) v1, Bit#(64) v2);\n   method Action swallowddd(Bit#(64) v1, Bit#(64) v2, Bit#(64) v3);\n   method Action swallowdddd(Bit#(64) v1, Bit#(64) v2, Bit#(64) v3, Bit#(64) v4);\n   method Action startspit(Bit#(16) spitType, Bit#(16) loops);\nendinterface\n\n\ninterface PortalPerfIndication;\n   method Action spit();\n   method Action spitl(Bit#(32) v1);\n   method Action spitll(Bit#(32) v1, Bit#(32) v2);\n   method Action spitlll(Bit#(32) v1, Bit#(32) v2, Bit#(32) v3);\n   method Action spitllll(Bit#(32) v1, Bit#(32) v2, Bit#(32) v3, Bit#(32) v4);\n   method Action spitd(Bit#(64) v1);\n   method Action spitdd(Bit#(64) v1, Bit#(64) v2);\n   method Action spitddd(Bit#(64) v1, Bit#(64) v2, Bit#(64) v3);\n   method Action spitdddd(Bit#(64) v1, Bit#(64) v2, Bit#(64) v3, Bit#(64) v4);\nendinterface\n\n\n\nmodule mkPortalPerfRequest#(PortalPerfIndication indication) (PortalPerfRequest);\n   \n   Reg#(Bit#(32)) sinkl1 <- mkReg(0);\n\n   Reg#(Bit#(32)) sinkll1 <- mkReg(0);\n   Reg#(Bit#(32)) sinkll2 <- mkReg(0);\n\n   Reg#(Bit#(32)) sinklll1 <- mkReg(0);\n   Reg#(Bit#(32)) sinklll2 <- mkReg(0);\n   Reg#(Bit#(32)) sinklll3 <- mkReg(0);\n\n   Reg#(Bit#(32)) sinkllll1 <- mkReg(0);\n   Reg#(Bit#(32)) sinkllll2 <- mkReg(0);\n   Reg#(Bit#(32)) sinkllll3 <- mkReg(0);\n   Reg#(Bit#(32)) sinkllll4 <- mkReg(0);\n   \n   Reg#(Bit#(64)) sinkd1 <- mkReg(0);\n   \n   Reg#(Bit#(64)) sinkdd1 <- mkReg(0);\n   Reg#(Bit#(64)) sinkdd2 <- mkReg(0);\n   \n   Reg#(Bit#(64)) sinkddd1 <- mkReg(0);\n   Reg#(Bit#(64)) sinkddd2 <- mkReg(0);\n   Reg#(Bit#(64)) sinkddd3 <- mkReg(0);\n   \n   Reg#(Bit#(64)) sinkdddd1 <- mkReg(0);\n   Reg#(Bit#(64)) sinkdddd2 <- mkReg(0);\n   Reg#(Bit#(64)) sinkdddd3 <- mkReg(0);\n   Reg#(Bit#(64)) sinkdddd4 <- mkReg(0);\n   \n\n   function Action dospit();\n      return  \n\t action \n\t indication.spit(); \n\t endaction \n\t ;\n   endfunction\n\n   function Action dospitl();\n      return ( action \n\t indication.spitl(sinkl1);\n\t endaction );\n   endfunction\n\n   function Action dospitll();\n      return ( action \n\t indication.spitll(sinkll1, sinkll2);\n\t endaction );\n   endfunction\n\n   function Action dospitlll();\n      return ( action \n\t indication.spitlll(sinklll1, sinklll2, sinklll3);\n\t endaction );\n   endfunction\n\n   function Action dospitllll();\n      return ( action \n\t indication.spitllll(sinkllll1, sinkllll2, sinkllll3, sinkllll4);\n\t endaction );\n   endfunction\n\n   function Action dospitd();\n      return ( action \n\t indication.spitd(sinkd1);\n\t endaction );\n   endfunction\n\n   function Action dospitdd();\n      return ( action \n\t indication.spitdd(sinkdd1, sinkdd2);\n\t endaction );\n   endfunction\n\n   function Action dospitddd();\n      return ( action \n\t indication.spitddd(sinkddd1, sinkddd2, sinkddd3);\n\t endaction );\n   endfunction\n\n   function Action dospitdddd();\n      return ( action \n\t indication.spitdddd(sinkdddd1, sinkdddd2, sinkdddd3, sinkdddd4);\n\t endaction );\n   endfunction\n\n   Vector#(9, Repeat) rfns = ?;\n   rfns[0] <- mkRepeat(dospit);\n   rfns[1] <- mkRepeat(dospitl);\n   rfns[2] <- mkRepeat(dospitll);\n   rfns[3] <- mkRepeat(dospitlll);\n   rfns[4] <- mkRepeat(dospitllll);\n   rfns[5] <- mkRepeat(dospitd);\n   rfns[6] <- mkRepeat(dospitdd);\n   rfns[7] <- mkRepeat(dospitddd);\n   rfns[8] <- mkRepeat(dospitdddd);\n\n   method Action swallowl(Bit#(32) v1);\n      sinkl1 <= v1;\n   endmethod\n\n   method Action swallow();\n   endmethod\n\n   method Action swallowll(Bit#(32) v1, Bit#(32) v2);\n      sinkll1 <= v1;\n      sinkll2 <= v2;\n   endmethod\n\n   method Action swallowlll(Bit#(32) v1, Bit#(32) v2, Bit#(32) v3);\n      sinklll1 <= v1;\n      sinklll2 <= v2;\n      sinklll3 <= v3;\n   endmethod\n\n   method Action swallowllll(Bit#(32) v1, Bit#(32) v2, Bit#(32) v3, Bit#(32) v4);\n      sinkllll1 <= v1;\n      sinkllll2 <= v2;\n      sinkllll3 <= v3;\n      sinkllll4 <= v4;\n   endmethod\n\n   method Action swallowd(Bit#(64) v1);\n      sinkd1 <= v1;\n   endmethod\n\n   method Action swallowdd(Bit#(64) v1, Bit#(64) v2);\n      sinkdd1 <= v1;\n      sinkdd2 <= v2;\n   endmethod\n\n   method Action swallowddd(Bit#(64) v1, Bit#(64) v2, Bit#(64) v3);\n      sinkddd1 <= v1;\n      sinkddd2 <= v2;\n      sinkddd3 <= v3;\n   endmethod\n\n   method Action swallowdddd(Bit#(64) v1, Bit#(64) v2, Bit#(64) v3, Bit#(64) v4\n      );\n      sinkdddd1 <= v1;\n      sinkdddd2 <= v2;\n      sinkdddd3 <= v3;\n      sinkdddd4 <= v4;\n   endmethod\n\n   method Action startspit(Bit#(16) spitType, Bit#(16) loops);\n      rfns[spitType].start(loops);\n   endmethod\n\nendmodule"
  },
  {
    "path": "contrib/portalperf/Repeat.bsv",
    "content": "\n// Copyright (c) 2013 Nokia, Inc.\n// Copyright (c) 2013 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\ninterface Repeat;\n   method Action start(Bit#(16) loops);\nendinterface\n\nmodule mkRepeat#(function Action tocall)(Repeat);\n   \n   Reg#(Bit#(16)) loopcount <- mkReg(0);\n   \n   rule doonce (loopcount > 0);\n      tocall();\n      loopcount <= loopcount - 1;\n   endrule\n   \n   method Action start(Bit#(16) loops);   \n      loopcount <= loops;\n   endmethod\n\nendmodule\n"
  },
  {
    "path": "contrib/portalperf/Top.bsv",
    "content": "/* Copyright (c) 2014 Quanta Research Cambridge, Inc\n *\n * Permission is hereby granted, free of charge, to any person obtaining a\n * copy of this software and associated documentation files (the \"Software\"),\n * to deal in the Software without restriction, including without limitation\n * the rights to use, copy, modify, merge, publish, distribute, sublicense,\n * and/or sell copies of the Software, and to permit persons to whom the\n * Software is furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n * DEALINGS IN THE SOFTWARE.\n */\nimport Vector::*;\nimport FIFO::*;\nimport Connectable::*;\nimport Portal::*;\nimport HostInterface::*;\nimport CtrlMux::*;\nimport PortalPerfIndication::*;\nimport PortalPerfRequest::*;\nimport PortalPerf::*;\n\ntypedef enum {IfcNames_PortalPerfIndication, IfcNames_PortalPerfRequest} IfcNames deriving (Eq,Bits);\n\nmodule mkConnectalTop(StdConnectalTop#(PhysAddrWidth));\n   PortalPerfIndicationProxy portalPerfIndicationProxy <- mkPortalPerfIndicationProxy(IfcNames_PortalPerfIndication);\n   PortalPerfRequest portalPerfRequest <- mkPortalPerfRequest(portalPerfIndicationProxy.ifc);\n   PortalPerfRequestWrapper portalPerfRequestWrapper <- mkPortalPerfRequestWrapper(IfcNames_PortalPerfRequest, portalPerfRequest);\n   \n   Vector#(2,StdPortal) portals;\n   portals[0] = portalPerfIndicationProxy.portalIfc;\n   portals[1] = portalPerfRequestWrapper.portalIfc; \n   let ctrl_mux <- mkSlaveMuxDbg(portals);\n   \n   interface interrupt = getInterruptVector(portals);\n   interface slave = ctrl_mux;\n   interface masters = nil;\nendmodule : mkConnectalTop\n"
  },
  {
    "path": "contrib/portalperf/testportalperf.cpp",
    "content": "// Copyright (c) 2014 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\n#include <stdio.h>\n#include <stdlib.h>\n#include <unistd.h>\n\n#include \"PortalPerfIndication.h\"\n#include \"PortalPerfRequest.h\"\n\n//#define DEBUG 1\n\n#ifdef DEBUG\n#define DEBUGWHERE() \\\n  fprintf(stderr, \"at %s, %s:%d\\n\", __FUNCTION__, __FILE__, __LINE__)\n#else\n#define DEBUGWHERE()\n#endif\n\n#define LOOP_COUNT 10000\n\nPortalPerfRequestProxy *portalPerfRequestProxy = 0;\n\nint heard_count;\n\nstatic void *wait_for(int n)\n{\n    void *rc = NULL;\n    while ((heard_count != n) && !rc) {\n        rc = defaultPoller->pollFn(0);\n        if ((long)rc >= 0)\n            rc = defaultPoller->event();\n    }\n    return rc;\n}\n\nuint32_t vrl1, vrl2, vrl3, vrl4;\nuint64_t vrd1, vrd2, vrd3, vrd4;\n\nclass PortalPerfIndication : public PortalPerfIndicationWrapper\n{\npublic:\n  virtual void spit() {\n\tDEBUGWHERE();\n\theard_count++;\n    }\n  virtual void spitl(uint32_t v1) {\n\tDEBUGWHERE();\n\theard_count++;\n\tvrl1 = v1;\n    }\n  virtual void spitll(uint32_t v1, uint32_t v2) {\n\tDEBUGWHERE();\n        heard_count++;\n\tvrl1 = v1;\n\tvrl2 = v2;\n    }\n  virtual void spitlll(uint32_t v1, uint32_t v2, uint32_t v3) {\n\tDEBUGWHERE();\n        heard_count++;\n\tvrl1 = v1;\n\tvrl2 = v2;\n\tvrl3 = v3;\n    }\n  virtual void spitllll(uint32_t v1, uint32_t v2, uint32_t v3, uint32_t v4) {\n\tDEBUGWHERE();\n        heard_count++;\n\tvrl1 = v1;\n\tvrl2 = v2;\n\tvrl3 = v3;\n\tvrl4 = v4;\n    }\n  virtual void spitd(uint64_t v1) {\n\tDEBUGWHERE();\n        heard_count++;\n\tvrd1 = v1;\n    }\n  virtual void spitdd(uint64_t v1, uint64_t v2) {\n\tDEBUGWHERE();\n        heard_count++;\n\tvrd1 = v1;\n\tvrd2 = v2;\n    }\n  virtual void spitddd(uint64_t v1, uint64_t v2, uint64_t v3) {\n\tDEBUGWHERE();\n        heard_count++;\n\tvrd1 = v1;\n\tvrd2 = v2;\n\tvrd3 = v3;\n    }\n  virtual void spitdddd(uint64_t v1, uint64_t v2, uint64_t v3, uint64_t v4) {\n\tDEBUGWHERE();\n        heard_count++;\n\tvrd1 = v1;\n\tvrd2 = v2;\n\tvrd3 = v3;\n\tvrd4 = v4;\n    }\n    PortalPerfIndication(unsigned int id) : PortalPerfIndicationWrapper(id) {}\n};\n\nuint32_t vl1, vl2, vl3, vl4;\nuint64_t vd1, vd2, vd3, vd4;\n\nvoid call_swallow(void)\n{\n  DEBUGWHERE();\n  portalTimerStart(0);\n  portalTimerCatch(0);\n  portalPerfRequestProxy->swallow();\n  portalTimerCatch(19);\n}\n\nvoid call_swallowl(void)\n{\n  DEBUGWHERE();\n  portalTimerStart(0);\n  portalTimerCatch(0);\n  portalPerfRequestProxy->swallowl(vl1);\n  portalTimerCatch(19);\n}\n\nvoid call_swallowll(void)\n{\n  DEBUGWHERE();\n  portalTimerStart(0);\n  portalTimerCatch(0);\n  portalPerfRequestProxy->swallowll(vl1, vl2);\n  portalTimerCatch(19);\n}\n\nvoid call_swallowlll(void)\n{\n  DEBUGWHERE();\n  portalTimerStart(0);\n  portalTimerCatch(0);\n  portalPerfRequestProxy->swallowlll(vl1, vl2, vl3);\n  portalTimerCatch(19);\n}\n\nvoid call_swallowllll(void)\n{\n  DEBUGWHERE();\n  portalTimerStart(0);\n  portalTimerCatch(0);\n  portalPerfRequestProxy->swallowllll(vl1, vl2, vl3, vl4);\n  portalTimerCatch(19);\n}\n\nvoid call_swallowd(void)\n{\n  DEBUGWHERE();\n  portalTimerStart(0);\n  portalTimerCatch(0);\n  portalPerfRequestProxy->swallowd(vd1);\n  portalTimerCatch(19);\n}\n\nvoid call_swallowdd(void)\n{\n  DEBUGWHERE();\n  portalTimerStart(0);\n  portalTimerCatch(0);\n  portalPerfRequestProxy->swallowdd(vd1, vd2);\n  portalTimerCatch(19);\n}\n\nvoid call_swallowddd(void)\n{\n  DEBUGWHERE();\n  portalTimerStart(0);\n  portalTimerCatch(0);\n  portalPerfRequestProxy->swallowddd(vd1, vd2, vd3);\n  portalTimerCatch(19);\n}\n\nvoid call_swallowdddd(void)\n{\n  DEBUGWHERE();\n  portalTimerStart(0);\n  portalTimerCatch(0);\n  portalPerfRequestProxy->swallowdddd(vd1, vd2, vd3, vd4);\n  portalTimerCatch(19);\n}\n\nvoid dotestout(const char *testname, void (*testfn)(void))\n{\n  uint64_t elapsed;\n  portalTimerInit();\n  portalTimerStart(1);\n  for (int i = 0; i < LOOP_COUNT; i++) {\n    testfn();\n  }\n  elapsed = portalTimerLap(1);\n  printf(\"test %s: elapsed %g average %g\\n\", testname, (double) elapsed, (double) elapsed/ (double) LOOP_COUNT);\n  portalTimerPrint(LOOP_COUNT);\n}\n\nvoid dotestin(const char *testname, int which)\n{\n  uint64_t elapsed;\n  heard_count = 0;\n  printf(\"starting test %s, which %d\\n\", testname, which);\n  portalTimerInit();\n  portalTimerStart(1);\n  portalTimerStart(0);\n  portalTimerCatch(0);\n  portalPerfRequestProxy->startspit(which, LOOP_COUNT);\n  portalTimerCatch(19);\n  wait_for(LOOP_COUNT);\n  portalTimerCatch(21);\n  elapsed = portalTimerLap(1);\n  printf(\"test %s: heard %d elapsed %g average %g\\n\", testname, heard_count, (double) elapsed, (double) elapsed/ (double) LOOP_COUNT);\n  portalTimerPrint(1);\n}\n\nint main(int argc, const char **argv)\n{\n    PortalPerfIndication *portalPerfIndication = new PortalPerfIndication(IfcNames_PortalPerfIndication);\n    portalPerfRequestProxy = new PortalPerfRequestProxy(IfcNames_PortalPerfRequest);\n\n    printf(\"Timer tests\\n\");\n    portalTimerInit();\n    for (int i = 0; i < 1000; i++) {\n      portalTimerStart(0);\n      portalTimerCatch(1);\n      portalTimerCatch(2);\n      portalTimerCatch(3);\n      portalTimerCatch(4);\n      portalTimerCatch(5);\n      portalTimerCatch(6);\n      portalTimerCatch(7);\n      portalTimerCatch(8);\n    }\n    printf(\"Each line 1-8 is one more call to portalTimerCatch()\\n\");\n    portalTimerPrint(1000);\n\n    vl1 = 0xfeed000000000011;\n    vl2 = 0xface000000000012;\n    vl3 = 0xdead000000000013;\n    vl4 = 0xbeef000000000014;\n    vd1 = 0xfeed0000000000000021LL;\n    vd2 = 0xface0000000000000022LL;\n    vd3 = 0xdead0000000000000023LL;\n    vd4 = 0xbeef0000000000000024LL;\n\n    dotestout(\"swallow\", call_swallow);\n    dotestout(\"swallowl\", call_swallowl);\n    dotestout(\"swallowll\", call_swallowll);\n    dotestout(\"swallowlll\", call_swallowlll);\n    dotestout(\"swallowllll\", call_swallowllll);\n    dotestout(\"swallowd\", call_swallowd);\n    dotestout(\"swallowdd\", call_swallowdd);\n    dotestout(\"swallowddd\", call_swallowddd);\n    dotestout(\"swallowdddd\", call_swallowdddd);\n    dotestin(\"spitl\", 1);\n    dotestin(\"spit\", 0);\n    dotestin(\"spitll\", 2);\n    dotestin(\"spitlll\", 3);\n    dotestin(\"spitllll\", 4);\n    dotestin(\"spitd\", 5);\n    dotestin(\"spitdd\", 6);\n    dotestin(\"spitddd\", 7);\n    dotestin(\"spitdddd\", 8);\n\n    return 0;\n}\n"
  },
  {
    "path": "contrib/ptest/Makefile",
    "content": "CONNECTALDIR?=../..\nINTERFACES = PTestRequest PTestIndication\n\nBSVFILES = PTest.bsv\n\ninclude $(CONNECTALDIR)/Makefile.connectal\n"
  },
  {
    "path": "contrib/ptest/PTest.bsv",
    "content": "/* Copyright (c) 2014 Quanta Research Cambridge, Inc\n *\n * Permission is hereby granted, free of charge, to any person obtaining a\n * copy of this software and associated documentation files (the \"Software\"),\n * to deal in the Software without restriction, including without limitation\n * the rights to use, copy, modify, merge, publish, distribute, sublicense,\n * and/or sell copies of the Software, and to permit persons to whom the\n * Software is furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n * DEALINGS IN THE SOFTWARE.\n */\ntypedef struct { Bit#(16) a; Bit#(16) b; } Rec;\n\ntypedef Bit#(16) Signal;\n\ninterface PTestRequest;\n   method Action func2(Rec data); \n   method Action func1(Signal data); \nendinterface\n\ninterface PTestIndication;\n   method Action func3(Signal data);\nendinterface\n\n"
  },
  {
    "path": "contrib/ptest/PTest.bsv.bad",
    "content": "/* Copyright (c) 2014 Quanta Research Cambridge, Inc\n *\n * Permission is hereby granted, free of charge, to any person obtaining a\n * copy of this software and associated documentation files (the \"Software\"),\n * to deal in the Software without restriction, including without limitation\n * the rights to use, copy, modify, merge, publish, distribute, sublicense,\n * and/or sell copies of the Software, and to permit persons to whom the\n * Software is furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n * DEALINGS IN THE SOFTWARE.\n */\ntypedef struct { Bit#(16) a; Bit#(16) b; } Rec;\n\ntypedef Bit#(16) Signal;\n\ninterface PTestRequest;\n   method Action func2(Rec data); \n   method Action func1(Signal data); \nendinterface\n\ninterface PTestIndication;\n   method Action func3(Signal data);\nendinterface\n\n"
  },
  {
    "path": "contrib/ptest/PTest.bsv.good",
    "content": "/* Copyright (c) 2014 Quanta Research Cambridge, Inc\n *\n * Permission is hereby granted, free of charge, to any person obtaining a\n * copy of this software and associated documentation files (the \"Software\"),\n * to deal in the Software without restriction, including without limitation\n * the rights to use, copy, modify, merge, publish, distribute, sublicense,\n * and/or sell copies of the Software, and to permit persons to whom the\n * Software is furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n * DEALINGS IN THE SOFTWARE.\n */\n\ntypedef Bit#(16) Signal;\n\ninterface PTestRequest;\n   method Action func1(Bit#(16) data); \nendinterface\n\ninterface PTestIndication;\n   method Action fun2(Bit#(16) data);\nendinterface\n\n"
  },
  {
    "path": "contrib/serialconfig/Makefile",
    "content": "CONNECTALDIR?=../..\nS2H_INTERFACES = SerialconfigRequest:Serialconfig.request\nH2S_INTERFACES = Serialconfig:SerialconfigIndication\n\nBSVFILES = Serialconfig.bsv\nCPPFILES=testserialconfig.cpp\n\ninclude $(CONNECTALDIR)/Makefile.connectal\n"
  },
  {
    "path": "contrib/serialconfig/Readme.md",
    "content": "# Serial Configuration Register\n\nL. Stewart, Quanta Research Cambridge, stewart@qrclab.com\n\nIn many designs, there is a need for configuration control registers\nthat do not have high bandwidth requirements. They are used to configure\na piece of hardware, to contain near constants, etc.\n\nThere is also a need to read the contents of registers in the design.\n\nThe straightforward way to specify configuration registers using\nportals leads to wide parallel busses to each register.\n\nSerial Configuration Registers are intended to solve these problems.\n\nThe example defines two modules, an SpiReg and an SpiRoot.\n\nAn SpiReg creates a Register for a user defined type, and also\nan SpiTap to read and write the register over a serial bus.\n\nThis is much like a JTAG scannable register, but with simpler SPI type\nserial protocol.  Each SpiReg has an address and up to 32 bits of data.\n\nThe SpiRoot module provides a parallel, FIFO interface to a collection\nof Spi Registers.  The Registers are connected in a serial chain. To\nperform a write to an SpiReg, the client writes register address and data\ninto the FIFO.  Returning read data (and acks for write data) show\nup at the output of the FIFO.\n\n"
  },
  {
    "path": "contrib/serialconfig/Serialconfig.bsv",
    "content": "// Copyright (c) 2014 Quanta Research Cambridge, Inc.\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\nimport FIFO::*;\nimport SpiTap::*;\nimport SpiRoot::*;\nimport Connectable::*;\n\ninterface SerialconfigIndication;\n   method Action ack(Bit#(32) a, Bit#(32) d);\nendinterface\n      \ninterface SerialconfigRequest;\n   method Action send(Bit#(32) a, Bit#(32) d);\nendinterface\n\ninterface Serialconfig;\n    interface SerialconfigRequest request;\nendinterface\n\nmodule mkSerialconfig#(SerialconfigIndication indication)(Serialconfig);\n\n   \n   SpiReg#(Bit#(32)) tap1 <- mkSpiReg('h11110000);\n   SpiReg#(Bit#(24)) tap2 <- mkSpiReg('h22220000);\n   SpiReg#(Bit#(16)) tap3 <- mkSpiReg('h33330000);\n   SpiReg#(Bit#(8)) tap4 <- mkSpiReg('h44440000);\n\n   mkConnection(tap1.tap.out, tap2.tap.in);\n   mkConnection(tap2.tap.out, tap3.tap.in);\n   mkConnection(tap3.tap.out, tap4.tap.in);\n\n   FIFO#(SpiItem) spi <- mkSpiRoot(SpiTap{in: tap1.tap.in, out: tap4.tap.out});\n  \n   rule getresults;\n      indication.ack(spi.first().a, spi.first().d);\n      spi.deq();\n   endrule\n\n   interface SerialconfigRequest request;\n \n      method Action send(Bit#(32) a, Bit#(32) d);\n         spi.enq(SpiItem{a: a, d: d});\n      endmethod\n\n  endinterface\n   \nendmodule\n"
  },
  {
    "path": "contrib/serialconfig/testserialconfig.cpp",
    "content": "/* Copyright (c) 2013 Quanta Research Cambridge, Inc\n *\n * Permission is hereby granted, free of charge, to any person obtaining a\n * copy of this software and associated documentation files (the \"Software\"),\n * to deal in the Software without restriction, including without limitation\n * the rights to use, copy, modify, merge, publish, distribute, sublicense,\n * and/or sell copies of the Software, and to permit persons to whom the\n * Software is furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n * DEALINGS IN THE SOFTWARE.\n */\n\n#include <stdio.h>\n#include <sys/mman.h>\n#include <stdlib.h>\n#include <unistd.h>\n#include <assert.h>\n#include <semaphore.h>\n#include <ctime>\n#include <monkit.h>\n#include <sys/types.h>\n#include <sys/stat.h>\n\n#include \"SerialconfigIndication.h\"\n#include \"SerialconfigRequest.h\"\n#include \"GeneratedTypes.h\"\n\nsem_t test_sem;\n\nuint32_t lasta;\nuint32_t lastd;\n\nstatic SerialconfigRequestProxy *serialconfigRequestProxy = 0;\n\nclass SerialconfigIndication : public SerialconfigIndicationWrapper\n{\npublic:\n  SerialconfigIndication(unsigned int id) : SerialconfigIndicationWrapper(id){};\n\n  virtual void ack(uint32_t a, uint32_t d) {\n    fprintf(stderr, \"ack a %x d %x\\n\", a, d);\n    lasta = a;\n    lastd = d;\n    sem_post(&test_sem);\n  }\n};\n\nvoid lastdshouldbe(uint32_t v)\n{\n  if (lastd != v)\n    printf(\"error, expected data %08x got %08x\\n\", v, lastd);\n}\nvoid lastashouldbe(uint32_t a)\n{\n  if ((lasta & ~1) != a)\n    printf(\"error, expected address %08x got %08x\\n\", a, lasta & ~1);\n}\n\nvoid doread(uint32_t a, uint32_t expect)\n{\n  serialconfigRequestProxy->send(a & ~1, 0xfeedface);\n  sem_wait(&test_sem);\n  lastashouldbe(a);\n  lastdshouldbe(expect);\n}\n\nvoid dowrite(uint32_t a, uint32_t d)\n{\n  serialconfigRequestProxy->send(a | 1, d);\n  sem_wait(&test_sem);\n  lastashouldbe(a);\n  lastdshouldbe(d);\n}\n\nvoid dotest()\n{\n  dowrite(0x0, 0xf00f00);\n\n  dowrite(0x11110000, 0x00000000);\n  dowrite(0x22220000, 0x00000000);\n  dowrite(0x33330000, 0x00000000);\n  dowrite(0x44440000, 0x00000000);\n\n  doread(0x11110000, 0x00000000);\n  doread(0x22220000, 0x00000000);\n  doread(0x33330000, 0x00000000);\n  doread(0x44440000, 0x00000000);\n\n\n  dowrite(0x11110000, 0x11111111);\n  dowrite(0x22220000, 0x22222222);\n  dowrite(0x33330000, 0x33333333);\n  dowrite(0x44440000, 0x44444444);\n\n  doread(0x11110000, 0x11111111);\n  doread(0x22220000, 0x00222222);\n  doread(0x33330000, 0x00003333);\n  doread(0x44440000, 0x00000044);\n\n\n  dowrite(0x0, 0xdeadbeef);\n  doread(0x0, 0xfeedface);\n}\n\nint main(int argc, const char **argv)\n{\n  \n  SerialconfigIndication serialconfigIndication(IfcNames_SerialconfigIndicationH2S);\n\n  fprintf(stderr, \"%s %s\\n\", __DATE__, __TIME__);\n\n  serialconfigRequestProxy = new SerialconfigRequestProxy(IfcNames_SerialconfigRequestS2H);\n\n  if(sem_init(&test_sem, 1, 0)){\n    fprintf(stderr, \"failed to init test_sem\\n\");\n    return -1;\n  }\n\n    fprintf(stderr, \"simple tests\\n\");\n    dotest();\n}\n"
  },
  {
    "path": "contrib/smithwaterman/GotohB.bsv",
    "content": "// Copyright (c) 2014 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\nimport StmtFSM::*;\nimport BRAM::*;\n\ninterface GotohAlgorithm;\n   method Action setupA (Bit#(14) start, Bit#(14) length);\n   method Action setupB (Bit#(14) start, Bit#(14) length);\n   method Action setupG (Bit#(16) g);\n   method Action setupCC (Bit#(14) start);\n   method Action setupDD (Bit#(14) start);\n   method Bit#(14) result();\n   interface FSM fsm;\nendinterface\n\n\nmodule mkGotohB#(BRAMServer#(Bit#(strIndexWidth), Bit#(8)) strA, BRAMServer#(Bit#(strIndexWidth), Bit#(8)) strB, BRAMServer#(Bit#(lIndexWidth), Bit#(16)) matCC, BRAMServer#(Bit#(lIndexWidth), Bit#(16)) matDD, int dir)(GotohAlgorithm)\n         provisos(Add#(0, 14, strIndexWidth),\n\t       Add#(0, 14, lIndexWidth));\n\n\n   Bit#(16) initialH = 1;\n   Bit#(16) initialG = 4;\n   Reg#(Bit#(14)) aStartReg <- mkReg(0);\n   Reg#(Bit#(14)) bStartReg <- mkReg(0);\n   Reg#(Bit#(14)) ccStartReg <- mkReg(0);\n   Reg#(Bit#(14)) ddStartReg <- mkReg(0);\n   Reg#(Bit#(14)) aLenReg <- mkReg(0);\n   Reg#(Bit#(14)) bLenReg <- mkReg(0);\n   Reg#(Bit#(14)) ii <- mkReg(0);\n   Reg#(Bit#(14)) jj <- mkReg(0);\n   Reg#(Bit#(8)) aData <- mkReg(0);\n   Reg#(Bit#(8)) bData <- mkReg(0);\n   Reg#(Bit#(16)) vd <- mkReg(0);\n   Reg#(Bit#(16)) vc <- mkReg(0);\n   Reg#(Bit#(16)) ve <- mkReg(0);\n   Reg#(Bit#(16)) vs <- mkReg(0);\n   Reg#(Bit#(16)) vt <- mkReg(0);\n   Reg#(Bit#(16)) ccData <- mkReg(0);\n   Reg#(Bit#(16)) ddData <- mkReg(0);\n   Reg#(Bit#(16)) wdata <- mkReg(0);\n   Reg#(Bit#(16)) argt <- mkReg(0);\n   \n  Stmt gotohB =\n   seq\n      $display(\"gotohB running %d %d %d %d dir %d\",\n\t aStartReg, aLenReg, bStartReg, bLenReg, dir);\n      \n      /* initialize arrays */\n      vt <= initialG + initialH;\n      jj<= 1;\n      while (jj <= bLenReg)\n\t seq\n\t    action\n\t       matCC.request.put(BRAMRequest{write: True, responseOnWrite: False, address: ccStartReg + zeroExtend(jj), datain: vt});\n\t       matDD.request.put(BRAMRequest{write: True, responseOnWrite: False, address: ddStartReg + zeroExtend(jj), datain: vt + initialG});\n\t       vt <= vt + initialH;\n\t       jj <= jj + 1;\n\t    endaction\n\t endseq\n      action\n\t ve <= 0;\n\t vc <= 0;\n\t vs <= 0;\n\t matCC.request.put(BRAMRequest{write: True, responseOnWrite: False, address: ccStartReg, datain: 0});\n\t matDD.request.put(BRAMRequest{write: True, responseOnWrite: False, address: ddStartReg, datain: 0});\n      endaction\n      \n      \n      vt <= argt; /* Use passed-in value here */\n      /* Loop through string a */\n      ii <= 1;\n      while (ii <= aLenReg)\n\t seq\n\t    $display(\"gotohB ii = %d\", ii);\n\t    /* read string A */\n\t    action\n\t       let idx = ?;\n\t       if (dir == 1)\n\t\t  idx = aStartReg + ii - 1;  // 0 to aLen - 1\n\t       else\n\t\t  idx = aStartReg + aLenReg - ii;  // aLen-1 downto 0\n\t       strA.request.put(BRAMRequest{write: False, responseOnWrite: False, address: idx, datain: ?});\n\t    endaction\n\t    action\n\t       let tmp <- strA.response.get(); /* read a[i] */\n\t       aData <= tmp;\n\t    endaction\n\t    /* s = CC[0] */\n\t    matCC.request.put(BRAMRequest{write: False, responseOnWrite: False, address: ccStartReg + 0, datain: ?});\n       \t    action\n\t       let tmp <- matCC.response.get();\n\t       vs <= tmp;\n\t    endaction\n\t    \n\t    action\n\t       let newt = vt + initialH;\n\t       vc <= newt;   /* c = t + i * h */\n\t       vt <= newt;\n\t       matCC.request.put(BRAMRequest{write: True, responseOnWrite: False, address: ccStartReg + 0, datain: newt}); /* CC[0] = c */\n\t       matDD.request.put(BRAMRequest{write: True, responseOnWrite: False, address: ddStartReg + 0, datain: newt}); /* DD[0] = CC[0] */\n\t       ve <= newt + initialG;\n\t       jj <= 1;\n\t    endaction\n\n\n\t    /* Loop through string B */\n\t    while (jj <= bLenReg)\n\t       seq\n\t\t  $display(\"gotohB jj = %d\", jj);\n\t\t  ve <= min (ve, vc + initialG) + initialH;\n\t\t  /* read CC[j] and DD[j] */\n\t\t  matCC.request.put(BRAMRequest{write: False, responseOnWrite: False, address: ccStartReg + jj, datain: ?});\n\t\t  matDD.request.put(BRAMRequest{write: False, responseOnWrite: False, address: ddStartReg + jj, datain: ?});\n\t\t  action\n\t\t     let tmpcc <- matCC.response.get();\n\t\t     let tmpdd <- matDD.response.get();\n\t\t     ccData <= tmpcc;\n\t\t     ddData <= tmpdd;\n\t\t  endaction\n\t\t  /* read bData */\n\t\t  action\n\t\t     let idx = ?;\n\t\t     if (dir == 1)\n\t\t\tidx = bStartReg + jj - 1;  /* b[0] tp b[m-1] */\n\t\t     else\n\t\t\tidx = bStartReg + bLenReg - jj; /* b[m-1] downto b[0] */\n\t\t     strB.request.put(BRAMRequest{write: False, responseOnWrite: False, address: idx, datain: ?});\n\t\t  endaction\n\t\t  action\n\t\t     let tmp <- strB.response.get();\n\t\t     bData <= tmp;\n\t\t  endaction\n\t\t  if (aData == bData)\n\t\t     wdata <= 0;\n\t\t  else\n\t\t     wdata <= 2;\n\t\t  \n\t\t  action\n\t\t     let newdd = min(ddData, ccData + initialG) + initialH;\n\t\t     matDD.request.put(BRAMRequest{write: True, responseOnWrite: False, address: ddStartReg + jj, datain: newdd});\n\t\t     vc <= min(newdd, min(ve, vs + wdata));\n\t\t  endaction\n\t\t  vs <= ccData;\n\t\t  matCC.request.put(BRAMRequest{write: True, responseOnWrite: False, address: ccStartReg + jj, datain: vc});\n\t\t  jj <= jj + 1;\n\t       endseq\n\t    ii <= ii + 1;\n\t endseq\n   endseq;\n\n   FSM hB <- mkFSM(gotohB);\n   \n   method Action setupA(Bit#(14) start, Bit#(14) length);\n      aStartReg <= start;\n      aLenReg <= length;\n   endmethod\n   \n   method Action setupB(Bit#(14) start, Bit#(14) length);\n      bStartReg <= start;\n      bLenReg <= length;\n   endmethod\n\n   method Action setupG(Bit#(16) g);\n      argt <= g;\n   endmethod\n\n   method Action setupCC(Bit#(14) start);\n      ccStartReg <= start;\n   endmethod\n\n   method Action setupDD(Bit#(14) start);\n      ddStartReg <= start;\n   endmethod\n\n   method Bit#(14) result();\n      return(zeroExtend(bLenReg));\n   endmethod\n   \n   interface FSM fsm = hB;\n\nendmodule\n"
  },
  {
    "path": "contrib/smithwaterman/GotohC.bsv",
    "content": "// Copyright (c) 2014 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\nimport StmtFSM::*;\nimport BRAM::*;\nimport GotohB::*;\nimport StackReg::*;\n\ninterface SWAlgorithm;\n   method Action setupA (Bit#(14) start, Bit#(14) length);\n   method Action setupB (Bit#(14) start, Bit#(14) length);\n   method Bit#(14) result();\n   interface FSM fsm;\nendinterface\n\n\n/* frame arguments */\ntypedef struct {\n   Bit#(14) aStart;\n   Bit#(14) bStart;\n   Bit#(14) aLen;\n   Bit#(14) bLen;\n   Bit#(16) tb; /* tb, te only need to be 1 bit, to represent 0 or g */\n   Bit#(16) te;\n   } CArgs deriving(Bits);\n\ntypedef struct {\n   Bit#(14) midi;\n   Bit#(14) minj;\n   Bit#(2) mintype;\n   } CVars deriving(Bits);\n\ntypedef enum {GCSIdle, GCS1, GCS2, GCS3, GCS4, GCS5, GCS6, \n   GCSComplete} GCState deriving (Bits, Eq);\n\nmodule mkGotohC#(\n   BRAMServer#(Bit#(strIndexWidth), Bit#(8)) strA, \n   BRAMServer#(Bit#(strIndexWidth), Bit#(8)) strB, \n   GotohAlgorithm cgotohB0,  \n   GotohAlgorithm cgotohB1, \n   BRAMServer#(Bit#(lIndexWidth), Bit#(16)) cc, \n   BRAMServer#(Bit#(lIndexWidth), Bit#(16)) dd, \n   BRAMServer#(Bit#(lIndexWidth), Bit#(16)) rr, \n   BRAMServer#(Bit#(lIndexWidth), Bit#(16)) ss)(SWAlgorithm)\n   provisos(Add#(0, 14, strIndexWidth),\n\t    Add#(0, 14, lIndexWidth));\n\n   Bit#(16) initialH = 1;\n   Bit#(16) initialG = 4;\n      /* pc, args, vars */\n   StackReg#(128, GCState, CArgs, CVars) fr <- mkStackReg(128, GCSIdle);\n\n   Reg#(Bit#(14)) aStartReg <- mkReg(0);\n   Reg#(Bit#(14)) bStartReg <- mkReg(0);\n   Reg#(Bit#(14)) rStartReg <- mkReg(0);\n   Reg#(Bit#(14)) aLenReg <- mkReg(0);\n   Reg#(Bit#(14)) bLenReg <- mkReg(0);\n   Reg#(Bit#(14)) ii <- mkReg(0);\n   Reg#(Bit#(14)) jj <- mkReg(0);\n   Reg#(Bit#(8)) aData <- mkReg(0);\n   Reg#(Bit#(8)) bData <- mkReg(0);\n   Reg#(Bit#(14)) outcounter <- mkReg(0);\n   Reg#(Bit#(16)) alt1 <- mkReg(0);\n   Reg#(Bit#(16)) alt2 <- mkReg(0);\n   Reg#(Bit#(16)) minsofar <- mkReg(0);\n   Reg#(Bit#(1)) minfound <- mkReg(0);\n\n/*\n * GotohC(Astart, Alen, Bstart, Blen, tb, te, output fifo)\n * implicit A storage, B storage\n * \n */\n   function Bit#(16) gap (Bit#(16) i);\n      \n      if (i == 0) gap = 0;\n      else gap = (initialG + (initialH * i));\n      endfunction: gap\n   \n  // This FSM searches string B looking for the first char of string A\n   Stmt gotohC2Stmt =\n   seq\n      $display(\"gotohC2Stmt running \");\n      // read A[0]\n      strA.request.put(BRAMRequest{write: False, responseOnWrite: False, address: fr.args.aStart, datain: ?});\n      action\n\t let tmp <- strA.response.get();\n\t aData <= tmp;\n      endaction\n      alt1 <= min(fr.args.tb, fr.args.te) + initialH + gap(zeroExtend(fr.args.bLen));\n      minsofar <= alt1;\n      fr.vars <= CVars{midi: 0, minj: 1, mintype: 1};\n      // scan B\n      for (jj <= 1; jj <= fr.args.bLen; jj <= jj + 1)\n\t seq\n\t    strB.request.put(BRAMRequest{write: False, responseOnWrite: False, address: fr.args.bStart + jj - 1, datain: ?});\n\t    action\n\t       let tmp <- strB.response.get();\n\t       bData <= tmp;\n\t    endaction\n\t    if (aData == bData)\n\t       alt2 <= 0;\n\t    else\n\t       alt2 <= 2;\n\t    alt2 <= alt2 + gap(zeroExtend(jj - 1)) + gap(zeroExtend(fr.args.bLen - jj));\n\t    if (min(alt1, alt2) < minsofar)\n\t       par\n\t\t  minsofar <= min(alt1, alt2);\n\t\t  fr.vars <= CVars{midi: 0, minj: jj, mintype: 1};\n\t       endpar\n\t endseq\n      if (fr.vars.minj > 1)\n\t $display(\"delete B[%d] through B[%d]\",\n\t    fr.args.bStart, fr.args.bStart + fr.vars.minj - 1);\n      $display(\"convert A[%d] (%s) to B[%d] (%s)\",\n\t       fr.args.aStart, aData, fr.args.bStart + fr.vars.minj - 1, bData);\n      if (fr.vars.minj < fr.args.bLen)\n\t $display(\"delete B[%d] through B[%d]\",\n\t\t  fr.args.bStart + fr.vars.minj, fr.args.bStart + fr.args.bLen - 1);\n      $display(\"notes fr.vars.minj %f fr.args.bLen %d\",\n\t fr.vars.minj, fr.args.bLen);\n      fr.doreturn();\n   endseq;\n\n   FSM gC2fsm <- mkFSM(gotohC2Stmt);\n   \n   // AlgC step 1, 2, and 3\n   rule gc1 (fr.pc == GCS1);\n      $display(\"GCS1 aStart %d aLen %d bStart %d bLen %d\", \n\t fr.args.aStart, fr.args.aLen, fr.args.bStart, fr.args.bLen);\n      if (fr.args.bLen == 0)\n\t begin\n\t    if (fr.args.aLen > 0)\n\t       $display(\"delete A[%d] through A[%d]\", \n\t\t  fr.args.aStart, fr.args.aStart + fr.args.aLen - 1);\n\t    fr.doreturn();\n\t end\n     else if (fr.args.aLen == 0)\n\tbegin\n\t   $display(\"insert B[%d] through B[%d]\",\n\t      fr.args.bStart, fr.args.bStart + fr.args.bLen - 1);\n\tend\n     else if (fr.args.aLen == 1)\n\tbegin\n\t   gC2fsm.start();\n\t   fr.nextpc(GCS2);\n\tend\n     else\n\taction\n\t   let midi = fr.args.aLen >> 1;\n\t   fr.vars.midi <= midi;\n\t   cgotohB1.setupA(fr.args.aStart, midi);\n\t   cgotohB1.setupB(fr.args.bStart, fr.args.bLen);\n\t   cgotohB1.setupG(fr.args.tb);\n\t   cgotohB0.setupA(fr.args.aStart+midi, fr.args.aLen - midi);\n\t   cgotohB0.setupB(fr.args.bStart, fr.args.bLen);\n\t   cgotohB0.setupG(fr.args.te);\n\t   cgotohB0.fsm.start();\n\t   cgotohB1.fsm.start();\n\t   fr.nextpc(GCS3);\n\tendaction\n   endrule\n   \n   // This FSM searches the results of the two calls to GotohB\n   Stmt gotohC4Stmt =\n   seq\n      $display (\"gotohC4A stmt running\");\n      action\n\t minfound <= 0;\n\t minsofar <= 0;\n\t fr.vars.minj <= 0;\n      endaction\n      for (jj <= 0; jj <= fr.args.bLen; jj <= jj + 1)\n\t seq\n\t    action\n\t       cc.request.put(BRAMRequest{write: False, responseOnWrite: False, address: zeroExtend(jj), datain: ?});\n\t       rr.request.put(BRAMRequest{write: False, responseOnWrite: False, address: zeroExtend(fr.args.bLen - jj), datain: ?});\n\t       dd.request.put(BRAMRequest{write: False, responseOnWrite: False, address: zeroExtend(jj), datain: ?});\n\t       ss.request.put(BRAMRequest{write: False, responseOnWrite: False, address: zeroExtend(fr.args.bLen - jj), datain: ?});\n\t    endaction\n\t    action\n\t       let tc <- cc.response.get();\n\t       let td <- dd.response.get();\n\t       let tr <- rr.response.get();\n\t       let ts <- ss.response.get();\n\t       let t1 = tc + tr;\n\t       let t2 = td + ts - initialG;\n\t       $display(\" j %d cc %d dd %d rr %d ss %d\",\n\t\t  jj, tc, td, tr, ts);\n\t       if ((minfound == 0) || (t1 < minsofar) || (t2 < minsofar))\n\t\t  action\n\t\t     if (t1 < t2)\n\t\t\taction\n\t\t\t   fr.vars <= CVars{midi: fr.vars.midi, minj: jj, mintype: 1};\n\t\t\t   minsofar <= t1;\n\t\t\tendaction\n\t\t     else\n\t\t\taction\n\t\t\t   fr.vars <= CVars{midi: fr.vars.midi, minj: jj, mintype: 2};\n\t\t\t   minsofar <= t2;\n\t\t\tendaction\n\t\t  endaction\n\t       minfound <= 1;\n\t    endaction\n\t endseq\n      $display (\"midi %d minj %d fr.vars.mintype %d\", \n\t fr.vars.midi, fr.vars.minj, fr.vars.mintype);\n      if (fr.vars.mintype == 1)\n\t action\n\t    fr.docall(GCS1, GCS5, CArgs {aStart: fr.args.aStart, aLen: fr.vars.midi, bStart: fr.args.bStart, bLen: fr.vars.minj, tb: fr.args.tb, te: initialG}, fr.vars);\n\t endaction\n      else /* fr.vars.mintype == 2 */\n\t action\n\t    fr.docall(GCS1, GCS5, CArgs {aStart: fr.args.aStart, aLen: fr.vars.midi - 1, bStart: fr.args.bStart, bLen: fr.vars.minj, tb: fr.args.tb, te: 0}, fr.vars);\n\t endaction\n   endseq;\n\n   FSM gc4fsm <- mkFSM(gotohC4Stmt);\n   \n   rule gc3 (fr.pc == GCS3 && cgotohB0.fsm.done() && cgotohB1.fsm.done());\n      //$display(\"HSC3\");\n      gc4fsm.start();\n      fr.nextpc(GCS4);\n   endrule\n   \n   rule gc5 (fr.pc == GCS5);\n      $display(\"GCC5 aStart %d aLen %d bStart %d bLen %d midi %d maj %d\",\n\t fr.args.aStart, fr.args.aLen, fr.args.bStart, fr.args.bLen,\n\t fr.vars.midi, fr.vars.minj);\n      if (fr.vars.mintype == 1)\n\t action\n\t    fr.docall(GCS1, GCS6, CArgs{aStart: fr.args.aStart + fr.vars.midi, aLen: fr.args.aLen - fr.vars.midi, bStart: fr.args.bStart + fr.vars.minj, bLen: fr.args.bLen - fr.vars.minj, tb: initialG, te: fr.args.te}, fr.vars);\n\t endaction\n      else\n\t action\n\t    $display(\"delete A[%d] and A[%d]\",\n\t       fr.args.aStart + fr.vars.midi,\n\t       fr.args.aStart + fr.vars.midi + 1);\n\t    fr.docall(GCS1, GCS6, CArgs{aStart: fr.args.aStart + fr.vars.midi + 1, aLen: fr.args.aLen - fr.vars.midi- 1, bStart: fr.args.bStart + fr.vars.minj, bLen: fr.args.bLen - fr.vars.minj, tb: 0, te: fr.args.te}, fr.vars);\n\t endaction\n   endrule\n   \n   rule gc6 (fr.pc == GCS6);\n      $display(\"GSC6\");\n      fr.doreturn();\n   endrule\n\n   rule hccomplete (fr.pc == GCSComplete);\n      $display(\"GSCComplete, result size %d\", outcounter);\n      fr.nextpc(GCSIdle);\n   endrule\n   \n   method Action setupA(Bit#(14) start, Bit#(14) length);\n      $display(\"GotohC setupA %d %d\", start, length);\n      aStartReg <= start;\n      aLenReg <= length;\n   endmethod\n   \n   method Action setupB(Bit#(14) start, Bit#(14) length);\n      $display(\"GotohC setupB %d %d\", start, length);\n      bStartReg <= start;\n      bLenReg <= length;\n   endmethod\n\n   method Bit#(14) result();\n      return(outcounter);\n   endmethod\n\n   \n   interface FSM fsm;\n      method Action start();\n         $display(\"GotohC running aLen %d bLen %d\", aLenReg, bLenReg);\n\t fr.docall(GCS1, GCSComplete, CArgs{aStart: 0, aLen: aLenReg,\n\t    bStart: 0, bLen: bLenReg, tb: initialG, te: initialG}, CVars {midi: 0, minj: 0, mintype: 1});\n      endmethod\n      method Bool done();\n\t return(fr.pc == GCSIdle);\n      endmethod\n      method Action waitTillDone();\n      endmethod\n      method Action abort();\n      endmethod\n   endinterface: fsm\n\nendmodule\n"
  },
  {
    "path": "contrib/smithwaterman/Makefile",
    "content": "\nCONNECTALDIR?=../..\nINTERFACES = SmithwatermanRequest SmithwatermanIndication\nBSVFILES = Smithwaterman.bsv Top.bsv $(CONNECTALDIR)/lib/deprecated/DmaUtils.bsv\nCPPFILES=testsmithwaterman.cpp\nCONNECTALFLAGS += -I $(CONNECTALDIR)/lib/strstr/cpp\n\ninclude $(CONNECTALDIR)/Makefile.connectal\n"
  },
  {
    "path": "contrib/smithwaterman/Readme.md",
    "content": "## Smith-Waterman\n\nL. Stewart <stewart@qrclab.com>\nMarch17, 2014\n\nSee connectal/doc/SmithWaterman.md\n"
  },
  {
    "path": "contrib/smithwaterman/Smithwaterman.bsv",
    "content": "// Copyright (c) 2014 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\n\nimport FIFO::*;\nimport FIFOF::*;\nimport SpecialFIFOs::*;\nimport GetPut::*;\nimport StmtFSM::*;\nimport BRAM::*;\nimport Connectable::*;\nimport ConnectalMemTypes::*;\nimport DmaUtils::*;\nimport Dma2BRAM::*;\n\n// algorithm\nimport GotohB::*;\nimport GotohC::*;\n\ninterface SmithwatermanRequest;\n   method Action setupA(Bit#(32) strPointer, Bit#(32) strOffset, Bit#(32) strLen);\n   method Action setupB(Bit#(32) strPointer, Bit#(32) strOffset, Bit#(32) strLen);\n   method Action start(Bit#(32) alg);\nendinterface\n\ninterface SmithwatermanIndication;\n   method Action searchResult(Bit#(32) v);\n   method Action setupAComplete(); \n   method Action setupBComplete(); \nendinterface\n\ntypedef Bit#(64) DWord;\ntypedef Bit#(32) Word;\n\ntypedef 16384 MaxStringLen;\ntypedef 16384 MaxFetchLen;\ntypedef TLog#(MaxStringLen) StringIdxWidth;\ntypedef Bit#(StringIdxWidth) StringIdx;\ntypedef TLog#(MaxFetchLen) LIdxWidth;\ntypedef Bit#(LIdxWidth) LIdx;\n\nmodule mkSmithwatermanRequest#(SmithwatermanIndication indication,\n\t\t\tMemReadServer#(busWidth)   setupA_read_server,\n\t\t\tMemReadServer#(busWidth)   setupB_read_server)(SmithwatermanRequest)\n   \n   provisos(Add#(a__, 8, busWidth),\n\t    Div#(busWidth,8,nc),\n\t    Mul#(nc,8,busWidth),\n\t    Add#(1, b__, nc),\n\t    Add#(c__, 32, busWidth),\n\t    Add#(1, d__, TDiv#(busWidth, 32)),\n\t    Mul#(TDiv#(busWidth, 32), 32, busWidth),\n            Mul#(TDiv#(busWidth, 16), 16, busWidth),\n            Add#(1, e__, TDiv#(busWidth, 16)),\n            Add#(1, f__, TMul#(2, TDiv#(busWidth, 16))),\n            Add#(TDiv#(busWidth, 16), g__, TMul#(2, TDiv#(busWidth, 16))));\n\n   \n  Reg#(Bit#(14)) aLenReg <- mkReg(0);\n  Reg#(Bit#(14)) bLenReg <- mkReg(0);\n  Reg#(Bit#(14)) rLenReg <- mkReg(0);\n   BRAM2Port#(StringIdx, Bit#(8)) strA  <- mkBRAM2Server(defaultValue);\n   BRAM2Port#(StringIdx, Bit#(8)) strB <- mkBRAM2Server(defaultValue);\n   BRAM2Port#(LIdx, Bit#(16)) cc <- mkBRAM2Server(defaultValue);\n   BRAM2Port#(LIdx, Bit#(16)) dd <- mkBRAM2Server(defaultValue);\n   BRAM2Port#(LIdx, Bit#(16)) rr <- mkBRAM2Server(defaultValue);\n   BRAM2Port#(LIdx, Bit#(16)) ss <- mkBRAM2Server(defaultValue);\n\n   BRAMReadClient#(StringIdxWidth,busWidth) n2a <- mkBRAMReadClient(strA.portB);\n   mkConnection(n2a.dmaClient, setupA_read_server);\n   BRAMReadClient#(StringIdxWidth,busWidth) n2b <- mkBRAMReadClient(strB.portB);\n   mkConnection(n2b.dmaClient, setupB_read_server);\n\n   \n   Reg#(Bool) gotohCRunning <- mkReg(False);\n\n   GotohAlgorithm cgotohB1 <- mkGotohB(strA.portA, strB.portA, cc.portA, dd.portA, 1);\n   GotohAlgorithm cgotohB0 <- mkGotohB(strA.portA, strB.portA, rr.portA, ss.portA, 0);\n   SWAlgorithm gotohC <- mkGotohC(strA.portA, strB.portA, cgotohB0, cgotohB1, cc.portB, dd.portB, rr.portB, ss.portB);\n   // create BRAM Write client for matL\n\n   rule finish_setupA;\n      $display(\"finish setupA\");\n      let x <- n2a.finish;\n      indication.setupAComplete();\n   endrule\n\n   rule finish_setupB;\n      $display(\"finish setupB\");\n      let x <- n2b.finish;\n      indication.setupBComplete();\n   endrule\n\n   rule gotohC_completion (gotohCRunning && gotohC.fsm.done);\n      gotohCRunning <= False;\n      indication.searchResult(pack(zeroExtend(gotohC.result())));\n      endrule\n   \n   \n   method Action setupA(Bit#(32) strPointer, Bit#(32) strOffset, Bit#(32) strLen);\n      aLenReg <= truncate(strLen);\n      $display(\"setupA %h %h %d\", strPointer, strOffset, strLen);\n      n2a.start(strPointer, 0, pack(truncate(strOffset)), pack(truncate(strOffset + strLen-1)));\n      gotohC.setupA(truncate(strOffset), pack(truncate(strLen)));\n   endmethod\n\n   method Action setupB(Bit#(32) strPointer, Bit#(32) strOffset, Bit#(32) strLen);\n      bLenReg <= truncate(strLen);\n      $display(\"setupB %h %h %d\", strPointer, strOffset, strLen);\n      n2b.start(strPointer, 0, pack(truncate(strOffset)), pack(truncate(strOffset + strLen-1)));\n      gotohC.setupB(truncate(strOffset), pack(truncate(strLen)));\n   endmethod\n   \n\n   method Action start(Bit#(32) alg);\n      $display (\"start %d\", alg);\n      case (alg) \n\t 3: begin\n\t       gotohC.fsm.start();\n\t       gotohCRunning <= True;\n\t    end\n      endcase\n   endmethod\n\nendmodule\n"
  },
  {
    "path": "contrib/smithwaterman/Top.bsv",
    "content": "/* Copyright (c) 2014 Quanta Research Cambridge, Inc\n *\n * Permission is hereby granted, free of charge, to any person obtaining a\n * copy of this software and associated documentation files (the \"Software\"),\n * to deal in the Software without restriction, including without limitation\n * the rights to use, copy, modify, merge, publish, distribute, sublicense,\n * and/or sell copies of the Software, and to permit persons to whom the\n * Software is furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n * DEALINGS IN THE SOFTWARE.\n */\nimport SpecialFIFOs::*;\nimport Vector::*;\nimport StmtFSM::*;\nimport FIFO::*;\nimport CtrlMux::*;\nimport Portal::*;\nimport HostInterface::*;\nimport BlueScope::*;\nimport ConnectalMemory::*;\nimport DmaUtils::*;\nimport ConnectalMemTypes::*;\nimport MemServer::*;\nimport ConnectalMMU::*;\nimport SmithwatermanRequest::*;\nimport MemServerRequest::*;\nimport MMURequest::*;\nimport SmithwatermanIndication::*;\nimport MemServerIndication::*;\nimport MMUIndication::*;\nimport Smithwaterman::*;\n\ntypedef enum {IfcNames_SmithwatermanIndication, IfcNames_SmithwatermanRequest, IfcNames_HostMemServerIndication, IfcNames_HostMemServerRequest, IfcNames_HostMMURequest, IfcNames_HostMMUIndication} IfcNames deriving (Eq,Bits);\ntypedef 1 DegPar;\n\n\nmodule mkConnectalTop(StdConnectalDmaTop#(PhysAddrWidth));\n\n   DmaReadBuffer#(64,1) setupA_read_chan <- mkDmaReadBuffer();\n   DmaReadBuffer#(64,1) setupB_read_chan <- mkDmaReadBuffer();\n   \n   MemReadClient#(64) setupA_read_client = setupA_read_chan.dmaClient;\n   MemReadClient#(64) setupB_read_client = setupB_read_chan.dmaClient;\n   \n   Vector#(2,  MemReadClient#(64)) readClients;\n   readClients[0] = setupA_read_client;\n   readClients[1] = setupB_read_client;\n\n   MMUIndicationProxy hostMMUIndicationProxy <- mkMMUIndicationProxy(IfcNames_HostMMUIndication);\n   MMU#(PhysAddrWidth) hostMMU <- mkMMU(0, True, hostMMUIndicationProxy.ifc);\n   MMURequestWrapper hostMMURequestWrapper <- mkMMURequestWrapper(IfcNames_HostMMURequest, hostMMU.request);\n\n   MemServerIndicationProxy hostMemServerIndicationProxy <- mkMemServerIndicationProxy(IfcNames_HostMemServerIndication);\n   MemServer#(PhysAddrWidth,64,1) dma <- mkMemServer(readClients, nil, cons(hostMMU,nil), hostMemServerIndicationProxy.ifc);\n   MemServerRequestWrapper hostMemServerRequestWrapper <- mkMemServerRequestWrapper(IfcNames_HostMemServerRequest, dma.request);\n\n   SmithwatermanIndicationProxy smithwatermanIndicationProxy <- mkSmithwatermanIndicationProxy(IfcNames_SmithwatermanIndication);\n   SmithwatermanRequest smithwatermanRequest <- mkSmithwatermanRequest(smithwatermanIndicationProxy.ifc, setupA_read_chan.dmaServer, setupB_read_chan.dmaServer);\n   SmithwatermanRequestWrapper smithwatermanRequestWrapper <- mkSmithwatermanRequestWrapper(IfcNames_SmithwatermanRequest,smithwatermanRequest);\n\n   Vector#(6,StdPortal) portals;\n   portals[0] = smithwatermanRequestWrapper.portalIfc;\n   portals[1] = smithwatermanIndicationProxy.portalIfc; \n   portals[2] = hostMemServerRequestWrapper.portalIfc;\n   portals[3] = hostMemServerIndicationProxy.portalIfc; \n   portals[4] = hostMMURequestWrapper.portalIfc;\n   portals[5] = hostMMUIndicationProxy.portalIfc;\n   let ctrl_mux <- mkSlaveMux(portals);\n   \n   interface interrupt = getInterruptVector(portals);\n   interface slave = ctrl_mux;\n   interface masters = dma.masters;\nendmodule\n"
  },
  {
    "path": "contrib/smithwaterman/sw.py",
    "content": "from __future__ import print_function\n\ntry:\n    xrange\nexcept NameError:\n    xrange = range  # Python 3 compatibility\n\ndef printmatrix(m):\n  print(\"%s\\n\" * len (m) % tuple(m))\n              \n# Step 1 is Gotoh's algorithm]\n# arrays C[0..m, 0..n], D[0..m, 0..n] I[0..M, 0..N]\n# scalar t\n# paramters w(a, b), g, h\n# where w(a,b) is the cost of converting a to b\n# and cost of a gap is g + hk where k is the length ofthe gap\n\n# C(i,j) is the minimum cost of converting A(0..i) to B(0..j)\n# D(i,j) is the minimum cost of converting A(0..i) to B(0..j) when ai is deleted\n# C(i,j) is the minimum cost of converting A(0..i) to B(0..j) when bj is inserted\n# \n\ndef w(a, b):\n    if (a == b):\n        return 0.0\n    else:\n        return 1.0\n\ng = 2.0\nh = 0.5\n\ndef gap(k):\n    return g + (k * h)\n\ndef gotoh(A, B):\n    m = len(A)\n    n = len(B)\n    C = [[0 for j in xrange(n+1)] for i in xrange(m+1)]\n    D = [[0 for j in xrange(n+1)] for i in xrange(m+1)]\n    I = [[0 for j in xrange(n+1)] for i in xrange(m+1)]\n    C[0][0] = 0\n    for j in xrange(1,n+1):\n        C[0][j] = gap(j)\n        D[0][j] = C[0][j] + g\n    for i in xrange(1,m+1):\n        C[i][0] = gap(i)\n        I[i][0] = C[i][0] + g\n        for j in xrange(1,n+1):\n            I[i][j] = min(I[i][j-1], C[i][j-1] + g) + h\n            D[i][j] = min(D[i-1][j], C[i-1][j] + g) + h\n            C[i][j] = min(D[i][j], I[i][j], C[i-1][j-1] + w(A[i-1], B[j-1]))\n    print(\"String A %s String B %s\" % (A, B))\n    print(\"Matrix C\")\n    printmatrix(C)\n    print(\"Matrix D\")\n    printmatrix(D)\n    print(\"Matrix I\")\n    printmatrix(I)\n    return(C[m][n])\n\nA = \"agtac\"\nB = \"aag\"\ngotoh(A, B)\n\n\n# The recurrances in Gotoh only depend on the previous row, so\n# in a manner analagous to the conversion from Hirschberg algorithm A\n# to Hirschberg algorithm B we can write algorithm gotohb that uses\n# only two row vectors CC and DD\n\ndef gotohb(A, B):\n    m = len(A)\n    n = len(B)\n    e = 0\n    c = 0\n    s = 0\n    CC = [0 for j in xrange(n+1)]\n    DD = [0 for j in xrange(n+1)]\n    CC[0] = 0\n    for j in xrange(1,n+1):\n        CC[j] = gap(j)\n        DD[j] = CC[j] + g\n    # print 0, CC, DD, e, c, s\n    for i in xrange(1,m+1):\n        s = CC[0]\n        c = gap(i)\n        CC[0] = c\n        e = c + g\n        for j in xrange(1, n+1):\n            e = min(e, c + g) + h\n            DD[j] = min(DD[j], CC[j] + g) + h\n            c = min(DD[j], e, s+w(A[i-1], B[j-1]))\n            s = CC[j]\n            CC[j] = c\n    return([CC, DD])\n\nprint(\"Calling gotohb(%s, %s)\" % (A, B))\nregular = gotohb(A, B)\nprint(regular)\n\ndef gotohb2(A, B, t):\n    m = len(A)\n    n = len(B)\n    e = 0\n    c = 0\n    s = 0\n    CC = [0 for j in xrange(n+1)]\n    DD = [0 for j in xrange(n+1)]\n    CC[0] = 0\n    for j in xrange(1,n+1):\n        CC[j] = gap(j)\n        DD[j] = CC[j] + g\n    for i in xrange(1,m+1):\n        s = CC[0]\n        c = t + i * h\n        CC[0] = c\n        e = c + g\n        for j in xrange(1, n+1):\n            e = min(e, c + g) + h\n            DD[j] = min(DD[j], CC[j] + g) + h\n            c = min(DD[j], e, s+w(A[i-1], B[j-1]))\n            s = CC[j]\n            CC[j] = c\n    DD[0] = CC[0]\n    return([CC, DD])\n\nprint(\"Calling gotohb2 (%s, %s) \" % ( A, B))\nalternate = gotohb2(A, B, g)\nprint(alternate)\n              \n#\n#\n#\n\n\n\ndef gotohc(A, B, sa, sb, m, n, tb, te):\n    # m = len(A) - sa\n    # n = len(B) - sb\n    print(\"in gotohc\", A, B, sa, sb, m, n, tb, te)\n    if n == 0:\n        if m > 0:\n            print(\"delete A[%d] through A[%d]\" % (sa, sa + m - 1))\n    elif m == 0:\n        print(\"insert B[%d] through B[%d]\" % (sb, sb + n - 1))\n    elif m == 1:\n        alt1 = min(tb, te) + h + gap(n)\n        minsofar = alt1;\n        jsofar = 1;\n        for j in xrange(1, n+1):\n            alt2 = gap(j-1) + w(A[sa + 0], B[sb + j-1]) + gap(n-j)\n            if (min(alt1, alt2) < minsofar):\n                minsofar = min(alt1, alt2)\n                jsofar = j\n        if (jsofar > 1):\n            print(\"delete B[%d] through B[%d]\" % (sb, sb + jsofar -1))\n        print(\"convert A[%d] (%s) to B[%d] (%s) \" % (sa, A[sa], sb + jsofar - 1, B[sb + jsofar - 1]))\n        if jsofar < n:\n            print(\"delete B[%d] through B[%d]\" % (sb + jsofar, sb + n - 1))\n    else:\n        i = m >> 1\n        # print \"fwd rev\", A, sa, i, B, sb, n\n        fwd = gotohb2(A[sa : sa + i], B[sb:sb+n], tb)\n        rev = gotohb2(A[sa + i:sa + m][::-1],B[sb:sb+n][::-1], te)\n        minfound = 0\n        minsofar = 0\n        print(\"CC \", fwd[0], \" DD \", fwd[1])\n        print(\"RR \", rev[0], \" SS \", rev[1])\n        for j in xrange(0,n+1):\n            t1 = fwd[0][j] + rev[0][n-j]\n            t2 = fwd[1][j] + rev[1][n-j] - g\n            if (minfound == 0) or (t1 < minsofar):\n                mintype = 1\n                minsofar = t1\n                minj = j\n            if (t2 < minsofar):\n                mintype = 2\n                minsofar = t2\n                minj = j\n            minfound = 1\n        # minj minsofar and mintype are set\n        if mintype == 1:\n            print(\"type 1 midpoint at %d,%d\" % (i, minj))\n            gotohc(A,B, sa, sb, i, minj, tb, g)\n            gotohc(A,B, sa+i, sb+minj, m-i, n-minj, g, te)\n        else:\n            print(\"type 2 midpoint at %d,%d\" % (i, minj))\n            gotohc(A,B, sa, sb, i - 1, minj, tb, 0)\n            print(\"delete a[\", sa + i, \"] and a[\", sa + i + 1, \"]\")\n            gotohc(A,B, sa + i + 1, sb + minj, m - i - 1, n - minj, 0, te)\n\nprint(\"calling gotohc(%s, %s)\" %(A, B))\ngotohc(A, B, 0, 0, len(A), len(B),  g, g)\n"
  },
  {
    "path": "contrib/smithwaterman/testsmithwaterman.cpp",
    "content": "/* Copyright (c) 2013 Quanta Research Cambridge, Inc\n *\n * Permission is hereby granted, free of charge, to any person obtaining a\n * copy of this software and associated documentation files (the \"Software\"),\n * to deal in the Software without restriction, including without limitation\n * the rights to use, copy, modify, merge, publish, distribute, sublicense,\n * and/or sell copies of the Software, and to permit persons to whom the\n * Software is furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n * DEALINGS IN THE SOFTWARE.\n */\n#include <assert.h>\n#include <semaphore.h>\n#include <ctime>\n#include <monkit.h>\n#include <mp.h>\n#include \"dmaManager.h\"\n#include <sys/types.h>\n#include <sys/stat.h>\n#include \"SmithwatermanIndication.h\"\n#include \"SmithwatermanRequest.h\"\n\nsem_t test_sem;\nint result_length;\n\nclass SmithwatermanIndication : public SmithwatermanIndicationWrapper\n{\npublic:\n  SmithwatermanIndication(unsigned int id) : SmithwatermanIndicationWrapper(id){};\n\n  virtual void setupAComplete() {\n    fprintf(stderr, \"setupAComplete\\n\");\n    sem_post(&test_sem);\n  }\n  virtual void setupBComplete() {\n    fprintf(stderr, \"setupBComplete\\n\");\n    sem_post(&test_sem);\n  }\n  virtual void searchResult (uint32_t v){\n    result_length = v;\n    fprintf(stderr, \"searchResult = %d\\n\", v);\n    sem_post(&test_sem);\n  }\n};\n\n\nint main(int argc, const char **argv)\n{\n  SmithwatermanRequestProxy *device = 0;\n  SmithwatermanIndication *deviceIndication = 0;\n\n  fprintf(stderr, \"%s %s\\n\", __DATE__, __TIME__);\n  device = new SmithwatermanRequestProxy(IfcNames_SmithwatermanRequest);\n  deviceIndication = new SmithwatermanIndication(IfcNames_SmithwatermanIndication);\n    DmaManager *dma = platformInit();\n\n  if(sem_init(&test_sem, 1, 0)){\n    fprintf(stderr, \"failed to init test_sem\\n\");\n    return -1;\n  }\n\n    fprintf(stderr, \"simple tests\\n\");\n    int strAAlloc;\n    int strBAlloc;\n    unsigned int alloc_len = 128;\n    int rcA, rcB;\n    struct stat statAbuf, statBbuf;\n    \n    strAAlloc = portalAlloc(alloc_len, 0);\n    rcA = fstat(strAAlloc, &statAbuf);\n    if (rcA < 0) perror(\"fstatA\");\n    char *strA = (char *)portalMmap(strAAlloc, alloc_len);\n    if (strA == MAP_FAILED) perror(\"strA mmap failed\");\n    assert(strA != MAP_FAILED);\n\n    strBAlloc = portalAlloc(alloc_len, 0);\n    rcB = fstat(strBAlloc, &statBbuf);\n    if (rcA < 0) perror(\"fstatB\");\n    char *strB = (char *)portalMmap(strBAlloc, alloc_len);\n    if (strB == MAP_FAILED) perror(\"strB mmap failed\");\n    assert(strB != MAP_FAILED);\n\n    const char *strA_text = \"agtac\";\n    const char *strB_text = \"aag\";\n    \n    assert(strlen(strA_text) < alloc_len);\n    assert(strlen(strB_text) < alloc_len);\n\n    strncpy(strA, strA_text, alloc_len);\n    strncpy(strB, strB_text, alloc_len);\n\n    int strA_len = strlen(strA);\n    int strB_len = strlen(strB);\n\n    portalTimerInit();\n    portalTimerStart(0);\n\n\n    fprintf(stderr, \"elapsed time (hw cycles): %lld\\n\", (long long)portalTimerLap(0));\n    \n    portalCacheFlush(strAAlloc, strA, alloc_len, 1);\n    portalCacheFlush(strBAlloc, strB, alloc_len, 1);\n\n    unsigned int ref_strAAlloc = dma->reference(strAAlloc);\n    unsigned int ref_strBAlloc = dma->reference(strBAlloc);\n\n    device->setupA(ref_strAAlloc, 0, strA_len);\n    sem_wait(&test_sem);\n\n    device->setupB(ref_strBAlloc, 0, strB_len);\n    sem_wait(&test_sem);\n\n    uint64_t cycles;\n    uint64_t beats;\n\n\n    fprintf(stderr, \"starting algorithm C\\n\");\n    portalTimerInit();\n    portalTimerStart(0);\n\n    device->start(3);\n    sem_wait(&test_sem);\n    cycles = portalTimerLap(0);\n    fprintf(stderr, \"hw cycles: %f\\n\", (float)cycles);\n\n    sem_wait(&test_sem);\n\n    printf(\"Algorithm C results\\n\");\n    printf(\"\\n\");\n\n\n\n    close(strAAlloc);\n    close(strBAlloc);\n}\n"
  },
  {
    "path": "contrib/splice/Makefile",
    "content": "\nCONNECTALDIR?=../..\nINTERFACES = SpliceRequest SpliceIndication\nBSVFILES = Splice.bsv Top.bsv $(CONNECTALDIR)/lib/deprecated/DmaUtils.bsv\nCPPFILES=testsplice.cpp\n\ninclude $(CONNECTALDIR)/Makefile.connectal\n"
  },
  {
    "path": "contrib/splice/Splice.bsv",
    "content": "// Copyright (c) 2013 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\n\nimport FIFO::*;\nimport FIFOF::*;\nimport SpecialFIFOs::*;\nimport GetPut::*;\nimport StmtFSM::*;\nimport BRAM::*;\nimport Connectable::*;\nimport ConnectalMemTypes::*;\nimport DmaUtils::*;\nimport Dma2BRAM::*;\n\n/* This module solves the maximum common subsequence problem.\n * It finds the longest subsequence of characters present in both input strings\n * the subsequence does not have to be contiguous and the characters can have different locations\n * and offsets in the two strings, just so long as they occur in the same order\n *\n *  To initialize, load string A with request setupA, and wait for indication setup complete\n * Then load string B with request setupB, and wait for indication setup complete\n * To start the unit, signal start, and wait for searchResult, which will tell you the length\n * To retreive the result, use fetch and wait for fetchComplete\n */\n\n/* First pass implements Hirschberg Algorithm A and the fetch call returns the L matrix\n */\ninterface SpliceRequest;\n   method Action setupA(Bit#(32) strPointer, Bit#(32) strLen);\n   method Action setupB(Bit#(32) strPointer, Bit#(32) strLen);\n   method Action fetch(Bit#(32) strPointer, Bit#(32) strLen);\n   method Action start();\nendinterface\n\ninterface SpliceIndication;\n   method Action searchResult(Int#(32) v);\n   method Action setupAComplete(); \n   method Action setupBComplete(); \n   method Action fetchComplete(); \nendinterface\n\ntypedef Bit#(8) Char;\ntypedef Bit#(64) DWord;\ntypedef Bit#(32) Word;\n\ntypedef 128 MaxStringLen;\ntypedef 16384 MaxFetchLen;\ntypedef TLog#(MaxStringLen) StringIdx;\ntypedef TLog#(MaxFetchLen) LIdx;\n\nmodule mkSpliceRequest#(SpliceIndication indication,\n\t\t\tMemReadServer#(busWidth)   setupA_read_server,\n\t\t\tMemReadServer#(busWidth)   setupB_read_server,\n\t\t\tMemWriteServer#(busWidth)   fetch_write_server )(SpliceRequest)\n   \n   provisos(Add#(a__, 8, busWidth),\n\t    Div#(busWidth,8,nc),\n\t    Mul#(nc,8,busWidth),\n\t    Add#(1, b__, nc),\n\t    Add#(c__, 32, busWidth),\n\t    Add#(1, d__, TDiv#(busWidth, 32)),\n\t    Mul#(TDiv#(busWidth, 32), 32, busWidth),\n            Mul#(TDiv#(busWidth, 16), 16, busWidth),\n            Add#(1, e__, TDiv#(busWidth, 16)),\n            Add#(1, f__, TMul#(2, TDiv#(busWidth, 16))),\n            Add#(1, h__, busWidth),\n            Add#(TDiv#(busWidth, 16), g__, TMul#(2, TDiv#(busWidth, 16))));\n\n   \n  Reg#(Bit#(32)) aLenReg <- mkReg(0);\n  Reg#(Bit#(32)) bLenReg <- mkReg(0);\n  Reg#(Bit#(32)) rLenReg <- mkReg(0);\n  Reg#(Bit#(32)) ii <- mkReg(0);\n   Reg#(Char) aData <- mkReg(0);\n   Reg#(Char) bData <- mkReg(0);\n   BRAM2Port#(Bit#(StringIdx), Char) strA  <- mkBRAM2Server(defaultValue);\n   BRAM2Port#(Bit#(StringIdx), Char) strB <- mkBRAM2Server(defaultValue);\n   BRAM2Port#(Bit#(LIdx), Bit#(16)) matL <- mkBRAM2Server(defaultValue);\n\n   BRAMReadClient#(StringIdx,busWidth) n2a <- mkBRAMReadClient(strA.portB);\n   mkConnection(n2a.dmaClient, setupA_read_server);\n   BRAMReadClient#(StringIdx,busWidth) n2b <- mkBRAMReadClient(strB.portB);\n   mkConnection(n2b.dmaClient, setupB_read_server);\n   BRAMWriteClient#(LIdx, busWidth) l2n <- mkBRAMWriteClient(matL.portB);\n   mkConnection(l2n.dmaClient, fetch_write_server);\n\n   FIFOF#(void) aReady <- mkFIFOF;\n   FIFOF#(void) bReady <- mkFIFOF;\n   FIFOF#(void) mReady <- mkFIFOF;\n   Stmt splice =\n   seq while(True)\n   seq\n      action\n\t let ra <- aReady.deq();\n\t $display(\"Splice A Ready\");\n      endaction\n      action\n\t let rb <- bReady.deq();\n\t $display(\"Splice B Ready\");\n      endaction\n      if (aLenReg > bLenReg)\n\t rLenReg <= aLenReg;\n      else\n\t rLenReg <= bLenReg;\n      for (ii <= 0; ii < rLenReg; ii <= ii + 1)\n\t seq\n\t    $display(\"Splice ii %d \", ii);\n\t    strA.portA.request.put(BRAMRequest{write: False, responseOnWrite: False, address: truncate(ii), datain: 0});\n\t    strB.portA.request.put(BRAMRequest{write: False, responseOnWrite: False, address: truncate(ii), datain: 0});\n\t    action\n\t       let left <- strA.portA.response.get();\n\t       let right <- strB.portA.response.get();\n\t       aData <= left;\n\t       bData <= right;\n\t    endaction\n\t    $display(\"aData %h bData %h\", aData, bData);\n\t    matL.portA.request.put(BRAMRequest{write: True, responseOnWrite: False, address: truncate(ii), datain: {aData, bData}});\n\t endseq\n      indication.searchResult(unpack(rLenReg));\n   endseq\n   endseq;\n   \n   // create BRAM Write client for matL\n\n   rule finish_setupA;\n      $display(\"finish setupA\");\n      let x <- n2a.finish;\n      aReady.enq(?);\n      indication.setupAComplete();\n   endrule\n\n   rule finish_setupB;\n      $display(\"finish setupB\");\n      let x <- n2b.finish;\n      bReady.enq(?);\n      indication.setupBComplete();\n   endrule\n\n   rule finish_fetch;\n      $display(\"finish fetch\");\n      let x <- l2n.finish;\n      indication.fetchComplete();\n   endrule\n\n   mkAutoFSM(splice);\n   \n   method Action setupA(Bit#(32) strPointer, Bit#(32) strLen);\n      aLenReg <= strLen;\n      $display(\"setupA %h %d\", strPointer, strLen);\n      n2a.start(strPointer, 0, 0, truncate(strLen - 1));\n   endmethod\n\n   method Action setupB(Bit#(32) strPointer, Bit#(32) strLen);\n      bLenReg <= strLen;\n      $display(\"setupB %h %d\", strPointer, strLen);\n      n2b.start(strPointer, 0, 0, truncate(strLen - 1));\n   endmethod\n   \n   method Action fetch(Bit#(32) strPointer, Bit#(32) strLen);\n      rLenReg <= strLen;\n      $display(\"fetch %h %d\", strPointer, strLen);\n      l2n.start(strPointer, 0, 0, truncate(strLen - 1));\n   endmethod\n\n   method Action start();\n   endmethod\n\nendmodule\n"
  },
  {
    "path": "contrib/splice/Top.bsv",
    "content": "/* Copyright (c) 2014 Quanta Research Cambridge, Inc\n *\n * Permission is hereby granted, free of charge, to any person obtaining a\n * copy of this software and associated documentation files (the \"Software\"),\n * to deal in the Software without restriction, including without limitation\n * the rights to use, copy, modify, merge, publish, distribute, sublicense,\n * and/or sell copies of the Software, and to permit persons to whom the\n * Software is furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n * DEALINGS IN THE SOFTWARE.\n */\nimport SpecialFIFOs::*;\nimport Vector::*;\nimport StmtFSM::*;\nimport FIFO::*;\nimport CtrlMux::*;\nimport Portal::*;\nimport HostInterface::*;\nimport BlueScope::*;\nimport ConnectalMemory::*;\nimport DmaUtils::*;\nimport ConnectalMemTypes::*;\nimport MemServer::*;\nimport ConnectalMMU::*;\nimport SpliceRequest::*;\nimport MemServerRequest::*;\nimport MMURequest::*;\nimport SpliceIndication::*;\nimport MemServerIndication::*;\nimport MMUIndication::*;\nimport Splice::*;\n\ntypedef enum {IfcNames_SpliceIndication, IfcNames_SpliceRequest, IfcNames_HostMemServerIndication, IfcNames_HostMemServerRequest, IfcNames_HostMMURequest, IfcNames_HostMMUIndication} IfcNames deriving (Eq,Bits);\ntypedef 1 DegPar;\n\n\nmodule mkConnectalTop(StdConnectalDmaTop#(PhysAddrWidth));\n\n   DmaReadBuffer#(64,1) setupA_read_chan <- mkDmaReadBuffer();\n   DmaReadBuffer#(64,1) setupB_read_chan <- mkDmaReadBuffer();\n   DmaWriteBuffer#(64,1) fetch_write_chan <- mkDmaWriteBuffer();\n   \n   MemReadClient#(64) setupA_read_client = setupA_read_chan.dmaClient;\n   MemReadClient#(64) setupB_read_client = setupB_read_chan.dmaClient;\n   MemWriteClient#(64) fetch_write_client = fetch_write_chan.dmaClient;\n   \n   Vector#(2,  MemReadClient#(64)) readClients;\n   readClients[0] = setupA_read_client;\n   readClients[1] = setupB_read_client;\n\n   Vector#(1, MemWriteClient#(64)) writeClients;\n   writeClients[0] = fetch_write_client;\n\n\n   MMUIndicationProxy hostMMUIndicationProxy <- mkMMUIndicationProxy(IfcNames_HostMMUIndication);\n   MMU#(PhysAddrWidth) hostMMU <- mkMMU(0, True, hostMMUIndicationProxy.ifc);\n   MMURequestWrapper hostMMURequestWrapper <- mkMMURequestWrapper(IfcNames_HostMMURequest, hostMMU.request);\n\n   MemServerIndicationProxy hostMemServerIndicationProxy <- mkMemServerIndicationProxy(IfcNames_HostMemServerIndication);\n   MemServer#(PhysAddrWidth,64,1) dma <- mkMemServer(readClients, writeClients, cons(hostMMU,nil), hostMemServerIndicationProxy.ifc);\n   MemServerRequestWrapper hostMemServerRequestWrapper <- mkMemServerRequestWrapper(IfcNames_HostMemServerRequest, dma.request);\n   \n   SpliceIndicationProxy spliceIndicationProxy <- mkSpliceIndicationProxy(IfcNames_SpliceIndication);\n   SpliceRequest spliceRequest <- mkSpliceRequest(spliceIndicationProxy.ifc, setupA_read_chan.dmaServer, setupB_read_chan.dmaServer, fetch_write_chan.dmaServer);\n   SpliceRequestWrapper spliceRequestWrapper <- mkSpliceRequestWrapper(IfcNames_SpliceRequest,spliceRequest);\n\n   Vector#(6,StdPortal) portals;\n   portals[0] = spliceRequestWrapper.portalIfc;\n   portals[1] = spliceIndicationProxy.portalIfc; \n   portals[2] = hostMemServerRequestWrapper.portalIfc;\n   portals[3] = hostMemServerIndicationProxy.portalIfc; \n   portals[4] = hostMMURequestWrapper.portalIfc;\n   portals[5] = hostMMUIndicationProxy.portalIfc;\n   let ctrl_mux <- mkSlaveMux(portals);\n   \n   interface interrupt = getInterruptVector(portals);\n   interface slave = ctrl_mux;\n   interface masters = dma.masters;\nendmodule\n"
  },
  {
    "path": "contrib/splice/testsplice.cpp",
    "content": "/* Copyright (c) 2013 Quanta Research Cambridge, Inc\n *\n * Permission is hereby granted, free of charge, to any person obtaining a\n * copy of this software and associated documentation files (the \"Software\"),\n * to deal in the Software without restriction, including without limitation\n * the rights to use, copy, modify, merge, publish, distribute, sublicense,\n * and/or sell copies of the Software, and to permit persons to whom the\n * Software is furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n * DEALINGS IN THE SOFTWARE.\n */\n\n#include <assert.h>\n#include <semaphore.h>\n#include <string.h>\n#include <ctime>\n#include <monkit.h>\n#include \"dmaManager.h\"\n\n#include \"SpliceIndication.h\"\n#include \"SpliceRequest.h\"\n\nsem_t test_sem;\nsem_t setup_sem;\nint sw_match_cnt = 0;\nint hw_match_cnt = 0;\nunsigned result_len = 0;\n\nclass SpliceIndication : public SpliceIndicationWrapper\n{\npublic:\n  SpliceIndication(unsigned int id) : SpliceIndicationWrapper(id){};\n\n  virtual void setupAComplete() {\n    fprintf(stderr, \"setupAComplete\\n\");\n    sem_post(&setup_sem);\n  }\n  virtual void setupBComplete() {\n    fprintf(stderr, \"setupBComplete\\n\");\n    sem_post(&setup_sem);\n  }\n  virtual void fetchComplete() {\n    fprintf(stderr, \"fetchComplete\\n\");\n    sem_post(&setup_sem);\n  }\n\n  virtual void searchResult (int v){\n    fprintf(stderr, \"searchResult = %d\\n\", v);\n    result_len = v;\n    sem_post(&test_sem);\n  }\n};\n\n\nint main(int argc, const char **argv)\n{\n  SpliceRequestProxy *device = 0;\n  SpliceIndication *deviceIndication = 0;\n\n  fprintf(stderr, \"%s %s\\n\", __DATE__, __TIME__);\n  device = new SpliceRequestProxy(IfcNames_SpliceRequest);\n  deviceIndication = new SpliceIndication(IfcNames_SpliceIndication);\n    DmaManager *dma = platformInit();\n\n  if(sem_init(&test_sem, 1, 0)){\n    fprintf(stderr, \"failed to init test_sem\\n\");\n    return -1;\n  }\n\n  if(sem_init(&setup_sem, 1, 0)){\n    fprintf(stderr, \"failed to init setup_sem\\n\");\n    return -1;\n  }\n\n    fprintf(stderr, \"simple tests\\n\");\n    int strAAlloc;\n    int strBAlloc;\n    int fetchAlloc;\n    unsigned int alloc_len = 128;\n    unsigned int fetch_len = alloc_len * alloc_len;\n    \n    strAAlloc = portalAlloc(alloc_len, 0);\n    strBAlloc = portalAlloc(alloc_len, 0);\n    fetchAlloc = portalAlloc(fetch_len, 0);\n\n    char *strA = (char *)portalMmap(strAAlloc, alloc_len);\n    char *strB = (char *)portalMmap(strBAlloc, alloc_len);\n    int *fetch = (int *)portalMmap(fetchAlloc, fetch_len);\n    \n    const char *strA_text = \"   a     b      c    \";\n    const char *strB_text = \"..a........b......\";\n    \n    assert(strlen(strA_text) < alloc_len);\n    assert(strlen(strB_text) < alloc_len);\n\n    strncpy(strA, strA_text, alloc_len);\n    strncpy(strB, strB_text, alloc_len);\n\n    int strA_len = strlen(strA);\n    int strB_len = strlen(strB);\n    uint16_t swFetch[fetch_len];\n\n    for (int i = 0; i < alloc_len; i += 1) {\n      strA[i] = i;\n      strB[i] = 255 - i;\n    }\n\n\n    portalTimerStart(0);\n\n\n    fprintf(stderr, \"elapsed time (hw cycles): %lld\\n\", (long long)portalTimerLap(0));\n    \n    portalCacheFlush(strAAlloc, strA, alloc_len, 1);\n    portalCacheFlush(strBAlloc, strB, alloc_len, 1);\n    portalCacheFlush(fetchAlloc, fetch, fetch_len, 1);\n\n    unsigned int ref_strAAlloc = dma->reference(strAAlloc);\n    unsigned int ref_strBAlloc = dma->reference(strBAlloc);\n    unsigned int ref_fetchAlloc = dma->reference(fetchAlloc);\n\n    device->setupA(ref_strAAlloc, strA_len);\n    sem_wait(&setup_sem);\n\n    device->setupB(ref_strBAlloc, strB_len);\n    sem_wait(&setup_sem);\n    portalTimerStart(0);\n\n    device->start();\n    sem_wait(&test_sem);\n    uint64_t cycles = portalTimerLap(0);\n    uint64_t beats = hostMemServerIndication->getMemoryTraffic(ChannelType_Read);\n    fprintf(stderr, \"hw cycles: %f\\n\", (float)cycles);\n    assert(result_len < alloc_len * alloc_len);\n    //    device->fetch(ref_fetchAlloc, (result_len+7)& ~7);\n    device->fetch(ref_fetchAlloc, 32);\n    printf(\"fetch called %d\\n\", result_len);\n    sem_wait(&setup_sem);\n    printf(\"fetch finished \\n\");\n\n    memcpy(swFetch, fetch, result_len * sizeof(uint16_t));\n    for (int i = 0; i < result_len; i += 1) {\n      if ((swFetch[i] & 0xffff) != ((strA[i] << 8) & 0xff00 | (strB[i] & 0xff)))\n\tprintf(\"mismatch i %d A %02x B %02x R %04x\\n\", \n\t       i, strA[i], strB[i], swFetch[i]);\n    }\n\n\n    close(strAAlloc);\n    close(strBAlloc);\n    close(fetchAlloc);\n  }\n\n"
  },
  {
    "path": "cpp/BsimDma.cpp",
    "content": "\n// Copyright (c) 2013-2014 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\n#include <stdio.h>\n#include <stdint.h>\n#include <string.h>\n#include <errno.h>\n#include <assert.h>\n#include <sys/mman.h>\n#include <stdlib.h>\n#include \"sock_utils.h\"\n\n#define MAX_DMA_PORTS    4\n#define MAX_DMA_IDS     32\ntypedef struct {\n    int fd;\n    unsigned char *buffer;\n    uint32_t buffer_len;\n    int size_accum;\n} DMAINFO[MAX_DMA_IDS];\nstatic DMAINFO dma_info[MAX_DMA_PORTS];\nstatic int dma_trace ;//= 1;\n\n#define BUFFER_CHECK \\\n    if (!dma_info[id][pref].buffer || offset >= dma_info[id][pref].buffer_len) { \\\n      fprintf(stderr, \"BsimDma [%s:%d]: Error: offset %d too large for buffer %p len %d; reference id %d pref %d\\n\", __FUNCTION__, __LINE__, offset, dma_info[id][pref].buffer, dma_info[id][pref].buffer_len, id, pref); \\\n      exit(-1); \\\n    }\n\nextern \"C\" void write_simDma32(uint32_t pref, uint32_t offset, unsigned int data, uint8_t byteEnable)\n{\n    uint32_t id = pref>>5;\n    pref -= id<<5; \n    if (dma_trace)\n      fprintf(stderr, \"%s: %d [%d:%d] = %x\\n\", __FUNCTION__, id, pref, offset, data);\n    BUFFER_CHECK\n    if (byteEnable != 0xF) {\n      uint32_t old_data = *(unsigned int *)&dma_info[id][pref].buffer[offset];\n      uint32_t mask = 0;\n      for (int i = 0; i < 4; i++) {\n\tif (byteEnable & (1 << i))\n\t  mask |= (0xFF << (i*8));\n      }\n      //fprintf(stderr, \"write_simDma32 mask=%08x data=%08x old_data=%08x\\n\", mask, data, old_data);\n      data &= mask;\n      old_data &= ~mask;\n      //fprintf(stderr, \"write_simDma32 mask=%08x data=%08x old_data=%08x\\n\", mask, data, old_data);\n      data = data | old_data;\n    }\n    *(unsigned int *)&dma_info[id][pref].buffer[offset] = data;\n}\n\nextern \"C\" unsigned int read_simDma32(uint32_t pref, uint32_t offset)\n{\n    uint32_t id = pref>>5;\n    unsigned int ret;\n    pref -= id<<5; \n    BUFFER_CHECK\n    ret = *(unsigned int *)&dma_info[id][pref].buffer[offset];\n    if (dma_trace)\n      fprintf(stderr, \"%s: %d [%d:%d] = %x\\n\", __FUNCTION__, id, pref, offset, ret);\n    return ret;\n}\n\nextern \"C\" void write_simDma64(uint32_t pref, uint32_t offset, uint64_t data, uint8_t byteEnable)\n{\n    uint32_t id = pref>>5;\n    pref -= id<<5; \n    if (dma_trace)\n      fprintf(stderr, \"%s: %d [%d:%d] = %llx\\n\", __FUNCTION__, id, pref, offset, (long long)data);\n    BUFFER_CHECK\n    if (byteEnable != 0xFF) {\n      uint64_t old_data = *(uint64_t *)&dma_info[id][pref].buffer[offset];\n      uint64_t mask = 0;\n      for (int i = 0; i < 8; i++) {\n\tif (byteEnable & (1 << i))\n\t  mask |= (0xFF << (i*8));\n      }\n      data &= mask;\n      old_data &= ~mask;\n      data = data | old_data;\n    }\n    *(uint64_t *)&dma_info[id][pref].buffer[offset] = data;\n}\n\nextern \"C\" uint64_t read_simDma64(uint32_t pref, uint32_t offset)\n{\n    uint32_t id = pref>>5;\n    uint64_t ret;\n    pref -= id<<5; \n    BUFFER_CHECK\n    ret = *(uint64_t *)&dma_info[id][pref].buffer[offset];\n    if (dma_trace)\n      fprintf(stderr, \"%s: %d [%d:%d] = %llx\\n\", __FUNCTION__, id, pref, offset, (long long)ret);\n    return ret;\n}\n\nextern \"C\" void simDma_initfd(uint32_t aid, uint32_t fd)\n{\n    uint32_t id = aid >> 16;\n    uint32_t pref = aid & 0xffff;\n    if (dma_trace)\n      fprintf(stderr, \"%s: id=%d pref=%d fd=%d\\n\", __FUNCTION__, id, pref, fd);\n    assert(pref < MAX_DMA_IDS);\n    dma_info[id][pref].fd = fd;\n    assert(dma_info[id][pref].size_accum == 0);\n}\nextern \"C\" void simDma_init(uint32_t id, uint32_t pref, uint32_t size)\n{\n    if (dma_trace)\n      fprintf(stderr, \"simDma_init: id=%d pref=%d, size=%08x size_accum=%08x\\n\", id, pref, size, dma_info[id][pref].size_accum);\n    assert(pref < MAX_DMA_IDS);\n    dma_info[id][pref].size_accum += size;\n    if(size == 0){\n      if (dma_trace)\n          fprintf(stderr, \"%s: id=%d pref=%d fd=%d\\n\", __FUNCTION__, id, pref, dma_info[id][pref].fd);\n      dma_info[id][pref].buffer = (unsigned char *)mmap(0,\n          dma_info[id][pref].size_accum, PROT_WRITE|PROT_WRITE|PROT_EXEC, MAP_SHARED, dma_info[id][pref].fd, 0);\n      if (dma_info[id][pref].buffer == MAP_FAILED) {\n\tfprintf(stderr, \"simDma_init Error: mmap failed fd %x buffer %p size %x errno %d\\n\", dma_info[id][pref].fd, dma_info[id][pref].buffer, size, errno);\n\texit(-1);\n      }\n      dma_info[id][pref].buffer_len = dma_info[id][pref].size_accum;\n    }\n    if (dma_trace)\n      fprintf(stderr, \"simDma_init: done\\n\");\n}\n\nextern \"C\" void simDma_idreturn(uint32_t aid)\n{\n    uint32_t id = aid >> 16;\n    uint32_t pref = aid & 0xffff;\n    if (dma_trace)\n      fprintf(stderr, \"simDma_idreturn: aid=%08x id=%d pref=%d size=%08x\\n\", aid, id, pref, dma_info[id][pref].size_accum);\n    assert(pref < MAX_DMA_IDS);\n    int unmapped = munmap(dma_info[id][pref].buffer, dma_info[id][pref].size_accum);\n    if (unmapped != 0)\n      fprintf(stderr, \"%s: failed to unmap id=%d pref=%d fd=%d\\n\", __FUNCTION__, id, pref, dma_info[id][pref].fd);\n    memset(&dma_info[id][pref], 0, sizeof(dma_info[id][pref]));\n}\n"
  },
  {
    "path": "cpp/DmaBuffer.cpp",
    "content": "/* Copyright (c) 2016 Connectal Project\n *\n * Permission is hereby granted, free of charge, to any person obtaining a\n * copy of this software and associated documentation files (the \"Software\"),\n * to deal in the Software without restriction, including without limitation\n * the rights to use, copy, modify, merge, publish, distribute, sublicense,\n * and/or sell copies of the Software, and to permit persons to whom the\n * Software is furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n * DEALINGS IN THE SOFTWARE.\n */\n\n#include \"DmaBuffer.h\"\n\nDmaManager *DmaBuffer::mgr;\n\nvoid DmaBuffer::initDmaManager()\n{\n    if (!mgr)\n\tmgr = platformInit();\n}\n\n\nDmaBuffer::DmaBuffer(int size, bool cached)\n    : size(size), cached(cached), ref(-1)\n{\n    fd = portalAlloc(size, cached);\n    buf = (char *)portalMmap(fd, size);\n    if (1) {\n\tcacheInvalidate(size, 0);\n    }\n}\n\nDmaBuffer::~DmaBuffer()\n{\n    dereference();\n    portalMunmap(buf, size);\n    close(fd);\n}\n\nuint32_t DmaBuffer::reference()\n{\n    initDmaManager();\n    if (ref == -1)\n\tref = mgr->reference(fd);\n    return ref;\n}\n\nvoid DmaBuffer::dereference()\n{\n    if (ref != -1 && mgr)\n\tmgr->dereference(ref);\n    ref = -1;\n}\n\nvoid DmaBuffer::cacheInvalidate(int size, int flush)\n{\n#ifndef USE_ACP\n    if (size == 0)\n\tsize = this->size;\n    if (cached) {\n      portalCacheFlush(fd, buf, size, flush);\n    }\n#else\n    //fprintf(stderr, \"cacheInvalidate skipped due to use of ACP\\n\");\n#endif\n}\n"
  },
  {
    "path": "cpp/DmaBuffer.h",
    "content": "/* Copyright (c) 2016 Connectal Project\n *\n * Permission is hereby granted, free of charge, to any person obtaining a\n * copy of this software and associated documentation files (the \"Software\"),\n * to deal in the Software without restriction, including without limitation\n * the rights to use, copy, modify, merge, publish, distribute, sublicense,\n * and/or sell copies of the Software, and to permit persons to whom the\n * Software is furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n * DEALINGS IN THE SOFTWARE.\n */\n\n#ifndef _DMA_BUFFER_H_\n#define _DMA_BUFFER_H_\n\n#include \"dmaManager.h\"\n\nclass DmaBuffer {\n    const int size;\n    const bool cached;\n    int fd;\n    char *buf;\n    int ref;\n    static DmaManager *mgr;\n    static void initDmaManager();\npublic:\n    // Allocates a portal memory object of specified size and maps it into user process\n    DmaBuffer(int size, bool cached=true);\n    // Dereferences and deallocates the portal memory object\n    // if destructor is not called, the object is automatically\n    // unreferenced and freed when the process exits\n    ~DmaBuffer();\n    // returns the address of the mapped buffer\n    char *buffer() {\n\treturn buf;\n    }\n    // returns the reference to the object\n    //\n    // Sends the address translation table to hardware MMU if necessary.\n    uint32_t reference();\n    // Removes the address translation table from the hardware MMU\n    void dereference();\n    // invalidate and optionally flush from the dcache\n    void cacheInvalidate(int size=0, int flush=0);\n};\n\n\n#endif // _DMA_BUFFER_H_\n"
  },
  {
    "path": "cpp/MMUServer.h",
    "content": "/* Copyright (c) 2014 Quanta Research Cambridge, Inc\n *\n * Permission is hereby granted, free of charge, to any person obtaining a\n * copy of this software and associated documentation files (the \"Software\"),\n * to deal in the Software without restriction, including without limitation\n * the rights to use, copy, modify, merge, publish, distribute, sublicense,\n * and/or sell copies of the Software, and to permit persons to whom the\n * Software is furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n * DEALINGS IN THE SOFTWARE.\n */\n\n#include \"MMURequest.h\"\n#include \"MMUIndication.h\"\n\n#define MAX_SERVER_AREAS 20\nstatic int trace_mmuserver;// = 1;\n\nclass MMUServer : public MMURequestWrapper\n{\n    struct {\n        int fd;\n        void *ptr;\n        int len;\n    } memoryAreas[MAX_SERVER_AREAS];\n    int memoryAreasIndex;\n    PortalInternal *ifcarr[MAX_SERVER_AREAS];\n    MMUIndicationProxy *mIndicationProxy;\npublic:\n    void sglist (const uint32_t sglId, const uint32_t sglIndex, const uint64_t addr, const uint32_t len ) {\n        if (trace_mmuserver)\n            fprintf(stderr, \"daemon[%s:%d](%x, %x, %lx, %x)\\n\", __FUNCTION__, __LINE__, sglId, sglIndex, addr, len);\n        memoryAreas[sglId].len += len;\n    }\n    void region (const uint32_t sglId, const uint64_t barr12, const uint32_t index12, const uint64_t barr8, const uint32_t index8, const uint64_t barr4, const uint32_t index4, const uint64_t barr0, const uint32_t index0 ) {\n        memoryAreas[sglId].ptr = portalMmap(memoryAreas[sglId].fd, memoryAreas[sglId].len);\n        //if (trace_mmuserver)\n            fprintf(stderr, \"daemon[%s:%d] fd %d ptr %p len %x\\n\", __FUNCTION__, __LINE__, memoryAreas[sglId].fd, memoryAreas[sglId].ptr, memoryAreas[sglId].len);\n        mIndicationProxy->configResp(0);\n    }\n    void idRequest(SpecialTypeForSendingFd fd) {\n        memoryAreas[memoryAreasIndex].fd = fd;\n        memoryAreas[memoryAreasIndex].ptr = NULL;\n        memoryAreas[memoryAreasIndex].len = 0;\n        //if (trace_mmuserver)\n        fprintf(stderr, \"daemon[%s:%d] fd %d\\n\", __FUNCTION__, __LINE__, fd);\n        if (fd <= 0) {\n            fprintf(stderr, \"[%s:%d] bogus fd value %d\\n\", __FUNCTION__, __LINE__, fd);\n            exit(1);\n        }\n\n        mIndicationProxy->idResponse(memoryAreasIndex++);\n    }\n    void setInterface(uint32_t interfaceId, uint32_t sglId) {\n        if (trace_mmuserver)\n            fprintf(stderr, \"[%s:%d] ifc %d sgl %d\\n\", __FUNCTION__, __LINE__, interfaceId, sglId);\n        ifcarr[interfaceId]->map_base = (volatile unsigned int *)memoryAreas[sglId].ptr;\n    }\n    void idReturn (const uint32_t sglId ) {\n        if (trace_mmuserver)\n            fprintf(stderr, \"daemon[%s:%d] sglId %d\\n\", __FUNCTION__, __LINE__, sglId);\n    }\n    void *getPtr (const uint32_t sglId ) {\n        return memoryAreas[sglId].ptr;\n    }\n    void registerInterface(uint32_t interfaceId, PortalInternal *p) {\n        ifcarr[interfaceId] = p;\n    }\n    MMUServer(unsigned int id, MMUIndicationProxy *mind, PortalTransportFunctions *transport, void *param) :\n        MMURequestWrapper(id, transport, param), memoryAreasIndex(1), mIndicationProxy(mind) {}\n};\n"
  },
  {
    "path": "cpp/TlpReplay.cpp",
    "content": "\n// Copyright (c) 2013-2014 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\n#include <stdio.h>\n#include <stdlib.h>\n#include <errno.h>\n#include <string.h>\n#include <unistd.h>\n#include <sys/types.h>\n#include <sys/un.h>\n#include <assert.h>\n\n#include <fcntl.h>\n#include <sys/stat.h>\n#include <fstream>\n#include <stdint.h>\n\nstatic bool loaded = false;\nuint8_t *tlp_packets = NULL;\n\nuint8_t cvt(char c)\n{\n  if (c >= 'a')\n    return c-'a'+0xA;\n  if (c >= 'A')\n    return c-'A'+0xA;\n  return c-'0';\n}\n\nvoid load_tlp()\n{\n  if(!loaded){\n    fprintf(stderr, \"about to load tlp.log\\n\");\n    int tlp_file = open(\"tlp.log\", O_RDONLY);\n    struct stat fileStat;\n    assert(fstat(tlp_file,&fileStat) >= 0);\n    tlp_packets = (uint8_t*)malloc(fileStat.st_size);\n    \n    std::ifstream infile(\"tlp.log\");\n    std::string line;\n    unsigned char *tlpp = tlp_packets;\n\n    // skip over the first 8 characters in each \n    // line as they correspond to the timestamp \n    while (std::getline(infile, line)){\n      for(int i = 0; i < 40; i+=2) {\n\tuint8_t high = cvt(line[8+i+0]);\n\tuint8_t low  = cvt(line[8+i+1]);\n\t*tlpp = (high<<4)|low;\n\ttlpp++;\n      }\n    }\n    loaded = true;\n    fprintf(stderr, \"loaded tlp.log successfully\\n\");\n  }\n}\n\nuint8_t portnum() \n{\n  return *tlp_packets >> 1;\n}\n\nextern \"C\" {\n  bool can_put_tlp()\n  {\n    load_tlp();\n    return portnum() == 8;\n  }\n  \n  bool can_get_tlp()\n  {\n    load_tlp();\n    return portnum() == 4;\n  }\n  \n  void put_tlp(unsigned int* tlp)\n  {\n    assert(loaded);\n    tlp_packets += 20;\n  }\n  \n  void get_tlp(unsigned int* tlp)\n  {\n    assert(loaded);\n    // fprintf(stderr, \"           \");\n    // for(int i = i; i < 20; i++)\n    //   fprintf(stderr, \"%02x\", tlp_packets[i]);\n    // fprintf(stderr, \"\\n\");\n\n    // byte-swapping for bsim compatability\n    for(int i = 0; i < 20; i++){\n      ((uint8_t*)tlp)[19-i] = tlp_packets[i];\n    }\t\n    tlp_packets += 20;\n  }\n}\n"
  },
  {
    "path": "cpp/XsimTop.cpp",
    "content": "/* Copyright (c) 2014 Quanta Research Cambridge, Inc\n *\n * Permission is hereby granted, free of charge, to any person obtaining a\n * copy of this software and associated documentation files (the \"Software\"),\n * to deal in the Software without restriction, including without limitation\n * the rights to use, copy, modify, merge, publish, distribute, sublicense,\n * and/or sell copies of the Software, and to permit persons to whom the\n * Software is furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n * DEALINGS IN THE SOFTWARE.\n */\n#include <queue>\n#include <XsimTop.h>\n#include <XsimMsgRequest.h>\n#include <XsimMsgIndication.h>\n#include <pthread.h>\n\nstatic int trace_xsimtop; // = 1;\n\nclass XsimMsgRequest : public XsimMsgRequestWrapper {\n  pthread_mutex_t mutex;\n  std::queue<uint32_t> sinkbeats[16];\npublic:\n  XsimMsgRequest(int id, PortalTransportFunctions *item, void *param, PortalPoller *poller = 0):XsimMsgRequestWrapper(id, item, param, poller){\n    pthread_mutex_init(&mutex, 0);\n  }\n  ~XsimMsgRequest() {\n    pthread_mutex_destroy(&mutex);\n  }\n  void msgSink ( const uint32_t portal, const uint32_t data ) {\n      if (trace_xsimtop)\n          fprintf(stderr, \"XsimRX: portal %d data=%08x\\n\", portal, data);\n      pthread_mutex_lock(&mutex);\n      sinkbeats[portal].push(data);\n      pthread_mutex_unlock(&mutex);\n  }\n  void msgSinkFd ( const uint32_t portal, const uint32_t data ) {\n      if (trace_xsimtop)\n          fprintf(stderr, \"XsimRXFD: portal %d data=%08x\\n\", portal, data);\n      pthread_mutex_lock(&mutex);\n      sinkbeats[portal].push(data);\n      pthread_mutex_unlock(&mutex);\n  }\n  bool notEmpty(int portal) {\n      pthread_mutex_lock(&mutex);\n      bool notEmpty = sinkbeats[portal].size() > 0;\n      pthread_mutex_unlock(&mutex);\n      return notEmpty;\n  }\n  uint32_t get(int portal) {\n      pthread_mutex_lock(&mutex);\n      uint32_t data = sinkbeats[portal].front();\n      sinkbeats[portal].pop();\n      pthread_mutex_unlock(&mutex);\n      return data;\n  }\n};\n\nstatic Portal                 *mcommon;\nstatic XsimMsgIndicationProxy *xsimIndicationProxy;\nstatic XsimMsgRequest         *xsimRequest;\n\nstatic int finish = 0;\nstatic int xsim_disconnect(struct PortalInternal *pint)\n{\n  fprintf(stderr, \"%s:%d pint=%p calling $finish\\n\", __FUNCTION__, __LINE__, pint);\n  finish = 1;\n  return 0;\n}\n\nstatic PortalHandlerTemplate xsim_handler = {\n  xsim_disconnect\n};\n\nlong cycleCount;\n\nextern \"C\" int dpi_cycle()\n{\n  cycleCount++;\n  return finish;\n}\n\ndouble sc_time_stamp()\n{\n  return (double)cycleCount;\n}\n\nextern \"C\" void dpi_init()\n{\n    if (trace_xsimtop)\n      fprintf(stderr, \"%s:%d &xsim_handler=%p\\n\", __FUNCTION__, __LINE__, &xsim_handler);\n#ifdef POLL_IN_DPI_POLL\n    defaultPoller->stop();\n#endif\n    mcommon = new Portal(0, 0, sizeof(uint32_t), portal_mux_handler, &xsim_handler, &transportSocketResp, NULL, NULL);\n    PortalMuxParam param = {};\n    param.pint = &mcommon->pint;\n    xsimIndicationProxy = new XsimMsgIndicationProxy(XsimIfcNames_XsimMsgIndication, &transportMux, &param);\n    xsimRequest = new XsimMsgRequest(XsimIfcNames_XsimMsgRequest, &transportMux, &param);\n    if (trace_xsimtop) fprintf(stderr, \"%s: end\\n\", __FUNCTION__);\n}\n\n#ifdef POLL_IN_DPI_POLL\nextern \"C\" void dpi_poll()\n{\n      void *rc = defaultPoller->pollFn(1);\n      //fprintf(stderr, \"%s:%d: rc=%ld\\n\", __FUNCTION__, __LINE__, (long)rc);\n      if ((long)rc > 0)\n\t  defaultPoller->event();\n}\n#endif\n\nextern \"C\" long long dpi_msgSink_beat(int portal)\n{\n  long long result = 0xbadad7a;\n  //if (trace_xsimtop) fprintf(stderr, \"%s: portal %d rdy %d\\n\", __FUNCTION__, portal, (int)xsimRequest->sinkbeats[portal].size());\n  if (xsimRequest->notEmpty(portal)) {\n      uint32_t beat = xsimRequest->get(portal);\n      if (trace_xsimtop)\n          fprintf(stderr, \"%s: portal %d beat %08x\\n\", __FUNCTION__, portal, beat);\n      result = (1ll << 32) | beat;\n  }\n  return result;\n}\n\nextern \"C\" void dpi_msgSource_beat(int portal, int beat)\n{\n    if (trace_xsimtop)\n        fprintf(stderr, \"dpi_msgSource_beat: portal %d beat=%08x\\n\", portal, beat);\n    xsimIndicationProxy->msgSource(portal, beat);\n}\n"
  },
  {
    "path": "cpp/XsimTop.h",
    "content": "// Copyright (c) 2015 The Connectal Project\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\n#ifndef _XsimTop_h\n#define _XsimTop_h\nextern \"C\" void dpi_init();\nextern \"C\" int dpi_cycle();\n#endif\n\n\n"
  },
  {
    "path": "cpp/bluesim_main.cxx",
    "content": "// Copyright (c) 2016 Bluespec, Inc.  All Rights Reserved.\n\n// This is a boilerplate 'main' to drive a Bluesim executable without\n// using the BlueTcl top-level that bsc normally generates.\n\n// Example:\n// Suppose your top-level BSV file is Foo.bsv, with top-level module mkFoo\n// Compile and link the top-level BSV as usual, e.g.,:\n//    bsc -sim -u Foo.bsv\n//    bsc -sim -e mkFoo\n// This will produce the usual Bluetcl-based executable (a.out and a.out.so)\n// but it will also produce:\n//    mkFoo.{h,cxx,o}\n//    model_mkFoo.{h,cxx,o}\n//    (and of course similar files for any other imported BSV modules)\n// Then, compile and link this file with those .o's, like this Makefile target\n//\n//     CXXFAMILY=g++4                // for 32-bit platforms\n//     CXXFAMILY=g++4_64             // for 64-bit platforms\n//\n//     $(EXE): model_$(TOPMOD).o $(TOPMOD).o\n//             c++ -O3                                \\\n//                 bluesim_main.cxx                        \\    // This file\n//                 -o $@                                   \\    // Your final executable\n//                 -I.                                     \\    // bsc-generated .h files, project .h files\n//                 -I$(BLUESPECDIR)/Bluesim                \\    // Dir for Bluespec release .h files\n//                 -L$(BLUESPECDIR)/Bluesim/$(CXXFAMILY)   \\    // Dir Bluespec release libs\n//                 $^                                      \\    // all your .o's\n//                 -lbskernel -lbsprim -lpthread                // libs\n\n#include <stdio.h>\n#include <stdlib.h>\n#include <errno.h>\n#include <string.h>\n\n#include \"bluesim_kernel_api.h\"\n\n// #include MODEL_MKFOO_H\n#include \"model_mkXsimTop.h\"\n\n// ================================================================\n// Process command line args\n\nstatic char default_vcd_filename [] = \"dump.vcd\";\nstatic char *vcd_filename = NULL;    // Valid if not NULL\n\nstatic tUInt64  count = 0;           // Valid if positive\n\nstatic\nvoid process_command_line_args (int argc, char *argv [])\n{\n    // Check for -h (help)\n    for (int j = 0; j < argc; j++) {\n\tif (strcmp (argv [j], \"-h\") == 0) {\n\t    fprintf (stderr, \"Usage: %s [opts]\\n\", argv [0]);\n\t    fprintf (stderr, \"Options:\\n\");\n\t    fprintf (stderr, \"  -h            = print help and exit\\n\");\n\t    fprintf (stderr, \"  -m <N>        = execute for N cycles\\n\");\n\t    fprintf (stderr, \"  -V [<file>]   = dump waveforms to VCD file (default: dump.vcd)\\n\");\n\t    fprintf (stderr, \"\\n\");\n\t    fprintf (stderr, \"Examples:\\n\");\n\t    fprintf (stderr, \"  %s\\n\", argv [0]);\n\t    fprintf (stderr, \"  %s -m 3000\\n\", argv [0]);\n\t    fprintf (stderr, \"  %s -V sim.vcd\\n\", argv [0]);\n\t    exit (1);\n\t}\n    }\n\n    // Check for -V or -V vcd_filename in command-line args\n    for (int j = 0; j < argc; j++) {\n\tif (strcmp (argv [j], \"-V\") == 0) {\n\t    if (j == (argc - 1))\n\t\tvcd_filename = & (default_vcd_filename [0]);\n\t    else if (argv [j+1][0] != '-')\n\t\tvcd_filename = argv [j+1];\n\t    break;\n\t}\n    }\n\n    // Check for -m <N> flag (execute for N cycles)\n    long int n = -1;\n    for (int j = 0; j < argc; j++) {\n\tif (strcmp (argv [j], \"-m\") == 0) {\n\t    if (j == (argc - 1)) {\n\t\tfprintf (stderr, \"Command-line error: -m flag must be followed by a positive integer\\n\");\n\t\texit (1);\n\t    }\n\t    errno = 0;\n\t    n = strtol (argv [j+1], NULL, 0);\n\t    if ((errno != 0) || (n < 1)) {\n\t\tfprintf (stderr, \"Command-line error: -m flag must be followed by a positive integer\\n\");\n\t\texit (1);\n\t    }\n\t    count = n;\n\t    break;\n\t}\n    }\n}\n\n// ================================================================\n\nint main (int argc, char *argv[])\n{\n    process_command_line_args (argc, argv);\n\n    // tModel model = NEW_MODEL_MKFOO ();\n    tModel model = new_MODEL_mkXsimTop();\n\n#ifdef BSC_OBSOLETE\n    tSimStateHdl sim = bk_init (model, true, false);\n#else\n    tSimStateHdl sim = bk_init (model, true);\n#endif\n\n    if (vcd_filename != NULL) {\n\ttStatus status = bk_set_VCD_file (sim, vcd_filename);\n\tif (status == BK_ERROR) {\n\t    fprintf (stderr, \"Error: Could not open file for VCD output: %s\\n\", vcd_filename);\n\t    exit (1);\n\t}\n\ttBool b = bk_enable_VCD_dumping (sim);\n\tif (b == 0) {\n\t    fprintf (stderr, \"Error: Could not enable VCD dumping in file: %s\\n\", vcd_filename);\n\t    exit (1);\n\t}\n\tfprintf (stdout, \"Enabled VCD dumping to file %s\\n\", vcd_filename);\n    }\n\n    if (count > 0) {\n\ttClock clk = 0;\n\ttEdgeDirection dir = POSEDGE;\n\tbk_quit_after_edge (sim, clk, dir, count);\n\tfprintf (stdout, \"Will stop after %0lld clocks\\n\", count);\n    }\n\n    bk_advance (sim, false);\n\n    bk_shutdown (sim);\n\n    if (count > 0) {\n\tfprintf (stdout, \"Stopped after %0lld clocks\\n\", count);\n    }\n}\n"
  },
  {
    "path": "cpp/bsim_relay.c",
    "content": "/* Copyright (c) 2014 Quanta Research Cambridge, Inc\n *\n * Permission is hereby granted, free of charge, to any person obtaining a\n * copy of this software and associated documentation files (the \"Software\"),\n * to deal in the Software without restriction, including without limitation\n * the rights to use, copy, modify, merge, publish, distribute, sublicense,\n * and/or sell copies of the Software, and to permit persons to whom the\n * Software is furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n * DEALINGS IN THE SOFTWARE.\n */\n\n#include <stdlib.h>\n#include <stdio.h>\n#include <fcntl.h>\n#include <sys/select.h>\n#include <sys/mman.h>\n#include <errno.h>\n\n#include \"sock_utils.h\"\n#include \"portal.h\"\n\nstatic void memdump(unsigned char *p, int len, char *title)\n{\nint i;\n\n    i = 0;\n    while (len > 0) {\n        if (!(i & 0xf)) {\n            if (i > 0)\n                fprintf(stderr, \"\\n\");\n            fprintf(stderr, \"%s: \",title);\n        }\n        fprintf(stderr, \"%02x \", *p++);\n        i++;\n        len--;\n    }\n    fprintf(stderr, \"\\n\");\n}\n\nstatic char devicename[1000];\nint main(int argc, char *argv[])\n{\n    struct memrequest req;\n    static PortalInternal pint;\n    int rc;\n    char *bashpid = getenv(\"CONNECTAL_MODULE_NAME\");\n\n    if (!bashpid) {\n        fprintf(stderr, \"bsim_relay: define environment variable CONNECTAL_MODULE_NAME\\n\");\n        return -1;\n    }\n    sprintf(devicename, \"/dev/%s\", bashpid);\n    int fd = open(devicename, O_RDWR);\n    if (fd == -1) {\n        fprintf(stderr, \"bsimhost: '%s' not found\\n\", devicename);\n        return -1;\n    }\nfprintf(stderr, \"[%s:%d] trying to connect to bsim\\n\", __FUNCTION__, __LINE__);\n    connect_to_bsim();\nfprintf(stderr, \"[%s:%d] opened bsim\\n\", __FUNCTION__, __LINE__);\n    while ((rc = read(fd, &req, sizeof(req)))) {\n        struct memresponse rv;\n        if (rc == -1) {\n            struct timeval timeout;\n            timeout.tv_sec = 0;\n            timeout.tv_usec = 10000;\n            select(0, NULL, NULL, NULL, &timeout);\n            continue;\n        }\n        if (rc != sizeof(req)) {\n            fprintf(stderr, \"[%s:%d] rc = %d.\\n\", __FUNCTION__, __LINE__, rc);\n            memdump((unsigned char *)&req, sizeof(req), \"RX\");\n        }\n        rv.portal = req.portal;\n        pint.fpga_number = req.portal;\n        if (req.portal == MAGIC_PORTAL_FOR_SENDING_FD) {\nfprintf(stderr, \"[%s:%d] sending fd %d\\n\", __FUNCTION__, __LINE__, req.data_or_tag);\n            transportBsim.writefd(&pint, &req.addr, req.data_or_tag);\n            rv.data = 0xdead;\n            write(fd, &rv, sizeof(rv));\n        }\n        else if (req.write_flag)\n            transportBsim.write(&pint, &req.addr, req.data_or_tag);\n        else {\n            rv.data = transportBsim.read(&pint, &req.addr);\n            write(fd, &rv, sizeof(rv));\n        }\n    }\n    return 0;\n}\n"
  },
  {
    "path": "cpp/dmaManager.c",
    "content": "\n// Copyright (c) 2013,2014 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n#include \"dmaManager.h\"\n#ifndef __KERNEL__\n#include <string.h>\n#include <errno.h>\n#include <sys/ioctl.h>\n#ifdef ZYNQ\n#include \"drivers/zynqportal/zynqportal.h\"\n#else\n#include \"drivers/pcieportal/pcieportal.h\"\n#endif\n#endif\n#if defined(SIMULATION)\n#include \"dmaSendFd.h\"\n#endif\n#include \"GeneratedTypes.h\"\n\n#ifndef __KERNEL__\nstatic pthread_mutex_t dma_mutex;\npthread_once_t mutex_once = PTHREAD_ONCE_INIT;\nstatic void dmaManagerOnce(void)\n{\n  fprintf(stderr, \"[%s:%d]\\n\", __FUNCTION__, __LINE__);\n  pthread_mutex_init(&dma_mutex, 0);\n}\n#endif\n\nvoid DmaManager_init(DmaManagerPrivate *priv, PortalInternal *sglDevice)\n{\n    memset(priv, 0, sizeof(*priv));\n    priv->sglDevice = sglDevice;\n#ifndef __KERNEL__\n    pthread_once(&mutex_once, dmaManagerOnce);\n#endif\n    initPortalMemory();\n    if (sem_init(&priv->sglIdSem, 0, 0)){\n        PORTAL_PRINTF(\"failed to init sglIdSem\\n\");\n    }\n    if (sem_init(&priv->confSem, 0, 0)){\n        PORTAL_PRINTF(\"failed to init confSem\\n\");\n    }\n}\n\nvoid DmaManager_dereference(DmaManagerPrivate *priv, int ref)\n{\n#if  !defined(SIMULATION) && !defined(__KERNEL__)\n  pthread_mutex_lock(&dma_mutex);\n#ifdef ZYNQ\n    int rc = ioctl(priv->sglDevice->fpga_fd, PORTAL_DEREFERENCE, ref);\n#else\n    int rc = ioctl(priv->sglDevice->fpga_fd, PCIE_DEREFERENCE, ref);\n#endif\n  pthread_mutex_unlock(&dma_mutex);\n    if (rc != 0)\n      fprintf(stderr, \"[%s:%d] dereference ioctl error %d\\n\", __FUNCTION__, __LINE__, errno);\n#else\n    MMURequest_idReturn(priv->sglDevice, ref);\n#endif\n}\n\nint DmaManager_reference(DmaManagerPrivate *priv, int fd)\n{\n    int id = 0;\n    int rc = 0;\n    pthread_mutex_lock(&dma_mutex);\n    initPortalMemory();\n    MMURequest_idRequest(priv->sglDevice, (SpecialTypeForSendingFd)fd);\n    if (priv->poll) {\n        int rc = priv->poll(priv->shared_mmu_indication, &priv->sglId);\n        fprintf(stderr, \"[%s:%d] return after idrequest %d %d\\n\", __FUNCTION__, __LINE__, rc, priv->sglId);\n    }\n    else\n        sem_wait(&priv->sglIdSem);\n    id = priv->sglId;\n#if  !defined(SIMULATION) && !defined(__KERNEL__)\n#ifdef ZYNQ\n    PortalSendFd sendFd;\n    sendFd.fd = fd;\n    sendFd.id = id;\n    rc = ioctl(priv->sglDevice->fpga_fd, PORTAL_SEND_FD, &sendFd);\n#else\n    tSendFd sendFd;\n    sendFd.fd = fd;\n    sendFd.id = id;\n    rc = ioctl(priv->sglDevice->fpga_fd, PCIE_SEND_FD, &sendFd);\n#endif\n    if (!rc) {\n        if (priv->poll) {\n            uint32_t ret;\n            int rc = priv->poll(priv->shared_mmu_indication, &ret);\n            fprintf(stderr, \"[%s:%d] return after ioctl %d %d\\n\", __FUNCTION__, __LINE__, rc, ret);\n        }\n        else\n            sem_wait(&priv->confSem);\n    }\n    rc = id;\n#else // defined(SIMULATION) || defined(__KERNEL__)\n    rc = send_fd_to_portal(priv->sglDevice, fd, id, global_pa_fd);\n    if (rc >= 0) {\n        //PORTAL_PRINTF(\"%s:%d sem_wait\\n\", __FUNCTION__, __LINE__);\n        if (priv->poll) {\n            uint32_t ret;\n            int rc = priv->poll(priv->shared_mmu_indication, &ret);\n            fprintf(stderr, \"[%s:%d] return after sendfd %d %d\\n\", __FUNCTION__, __LINE__, rc, ret);\n        }\n        else\n            sem_wait(&priv->confSem);\n    }\n#endif // defined(SIMULATION) || defined(__KERNEL__)\n    pthread_mutex_unlock(&dma_mutex);\n    return rc;\n}\n\nvoid DmaManager_idresp(DmaManagerPrivate *priv, uint32_t sglId)\n{\n    priv->sglId = sglId;\n#ifndef __KERNEL__\n    sem_post(&priv->sglIdSem);\n#endif\n}\n\nvoid DmaManager_confresp(DmaManagerPrivate *priv, uint32_t channelId)\n{\n#ifndef __KERNEL__\n    //fprintf(stderr, \"configResp %d\\n\", channelId);\n    sem_post(&priv->confSem);\n#endif\n}\n"
  },
  {
    "path": "cpp/dmaManager.h",
    "content": "// Copyright (c) 2013-2014 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\n#ifndef _PORTAL_MEMORY_H_\n#define _PORTAL_MEMORY_H_\n\n#include \"ConnectalProjectConfig.h\"\n\n#ifdef __KERNEL__\n#include <linux/types.h>\n#include <linux/semaphore.h>\n#include <asm/cacheflush.h>\n#define sem_wait(A) down_interruptible(A)\n#define sem_post(A) up(A)\n#define sem_init(A, B, C) (sema_init ((A), (C)), 0)\ntypedef struct semaphore sem_t;\n#include <linux/slab.h>\n#include <linux/dma-buf.h>\n#define PORTAL_MALLOC(A) vmalloc(A)\n#define PORTAL_FREE(A) vfree(A)\n#else\n#include <semaphore.h>\n#include <pthread.h>\n#include <stdint.h>\n#define PORTAL_MALLOC(A) malloc(A)\n#define PORTAL_FREE(A) free(A)\n#endif\n\n#include \"portal.h\"\n\ntypedef struct {\n  sem_t confSem;\n  sem_t sglIdSem;\n#ifndef __KERNEL__\n  pthread_mutex_t mutex;\n#endif\n  uint32_t sglId;\n  PortalInternal *sglDevice;\n  int pa_fd;\n  SHARED_MMUINDICATION_POLL poll;\n  PortalInternal  *shared_mmu_indication;\n} DmaManagerPrivate;\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\nvoid DmaManager_init(DmaManagerPrivate *priv, PortalInternal *sglDevice);\nint DmaManager_reference(DmaManagerPrivate *priv, int fd);\nvoid DmaManager_dereference(DmaManagerPrivate *priv, int ref);\nvoid DmaManager_idresp(DmaManagerPrivate *priv, uint32_t sglId);\nvoid DmaManager_confresp(DmaManagerPrivate *priv, uint32_t channelId);\n#ifdef __cplusplus\n}\n#endif\n\n#ifndef NO_CPP_PORTAL_CODE\n#ifdef __cplusplus\n#include \"GeneratedTypes.h\" //ChannelType!!\nclass DmaManager\n{\n public:\n  DmaManagerPrivate priv;\n  DmaManager(Portal *sglDevice) {\n    DmaManager_init(&priv, &sglDevice->pint);\n  };\n  int reference(int fd) {\n    return DmaManager_reference(&priv, fd);\n  };\n  void dereference(int ref){\n    DmaManager_dereference(&priv, ref);\n  }\n  void sglIdResp(uint32_t sglId) {\n    DmaManager_idresp(&priv, sglId);\n  }\n  void confResp(uint32_t channelId) {\n    DmaManager_confresp(&priv, channelId);\n  };\n};\nextern \"C\" DmaManager *platformInit(void);\nextern \"C\" void platformStatistics(void);\n#else\nstruct DmaManager\n{\n  DmaManagerPrivate priv;\n};\ntypedef struct DmaManager DmaManager;\nDmaManager *platformInit(void);\nvoid platformStatistics(void);\n#endif\n#endif\n#endif // _PORTAL_MEMORY_H_\n"
  },
  {
    "path": "cpp/dmaSendFd.h",
    "content": "/* Copyright (c) 2014 Quanta Research Cambridge, Inc\n *\n * Permission is hereby granted, free of charge, to any person obtaining a\n * copy of this software and associated documentation files (the \"Software\"),\n * to deal in the Software without restriction, including without limitation\n * the rights to use, copy, modify, merge, publish, distribute, sublicense,\n * and/or sell copies of the Software, and to permit persons to whom the\n * Software is furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n * DEALINGS IN THE SOFTWARE.\n */\n\n#define PAGE_SHIFT0 12\n#define PAGE_SHIFT4 16\n#define PAGE_SHIFT8 20\n#define PAGE_SHIFT12 24\n#define NUM_SHIFTS 4\nstatic int shifts[NUM_SHIFTS+1] = {PAGE_SHIFT12, PAGE_SHIFT8, PAGE_SHIFT4, PAGE_SHIFT0, 0 /* needed for border computation */};\n\n#include \"drivers/portalmem/portalmem.h\" // PortalAlloc\n\n#ifdef CONNECTAL_DRIVER_CODE\n#define NO_WRAPPER_FUNCTIONS\n#include \"MMURequest.c\"\n#endif\nstatic int trace_memory = 0;\n\n#include \"GeneratedTypes.h\" // generated in project directory\n\n#ifdef SIMULATION\n// indexed by fd\nextern int portalmem_sizes[1024];\n#endif\n\nint send_fd_to_portal(PortalInternal *device, int fd, int id, int pa_fd)\n{\n    int rc = 0;\n    int i, j;\n    uint32_t regions[4] = {0,0,0,0};\n    uint64_t border = 0;\n    unsigned char entryCount = 0;\n    uint64_t borderVal[4];\n    uint32_t indexVal[4];\n    unsigned char idxOffset;\n#if defined(SIMULATION)\n    int size_accum = 0;\n#endif\n#ifdef __KERNEL__\n    struct scatterlist *sg;\n    struct file *fmem;\n    struct sg_table *sgtable;\n    fmem = fget(fd);\n    sgtable = ((struct pa_buffer *)((struct dma_buf *)fmem->private_data)->priv)->sg_table;\n#elif !defined(SIMULATION)\n#error\n#endif\n  rc = id;\n#ifdef __KERNEL__\n  for_each_sg(sgtable->sgl, sg, sgtable->nents, i) {\n      long addr = sg_phys(sg);\n      long len = sg->length;\n#elif defined(SIMULATION)\n  long object_len = portalmem_sizes[fd];\n  object_len = ((object_len + 4095) & ~4095l);\n  for (i = 0; object_len > 0; i++) {\n    long addr = size_accum;\n    long len = object_len;\n    if ((unsigned int)fd > sizeof(portalmem_sizes)/sizeof(portalmem_sizes[0]))\n        goto retlab;\n    if (!len)\n        break;\n    for (j = 0; (unsigned)j < NUM_SHIFTS; j++) {\n      long size = 1 << shifts[j];\n      if (object_len >= size) {\n\tlen = size;\n\tbreak;\n      }\n    }\n    //fprintf(stderr, \"%s:%d i=%d fd=%d object_len=%ld len=%ld\\n\", __FUNCTION__, __LINE__, i, fd, object_len, len);\n    size_accum += len;\n    object_len -= len;\n    addr |= ((long)id) << 32; //[39:32] = truncate(pref);\n#elif !defined(SIMULATION)\n#error\n#endif\n\n    for(j = 0; j < NUM_SHIFTS; j++)\n        if (len == 1<<shifts[j]) {\n          regions[j]++;\n          if (addr & ((1L<<shifts[j]) - 1))\n              PORTAL_PRINTF(\"%s: addr %lx shift %x *********\\n\", __FUNCTION__, addr, shifts[j]);\n          addr >>= shifts[j];\n          break;\n        }\n    if (j >= 4)\n      PORTAL_PRINTF(\"DmaManager:unsupported sglist size %lx\\n\", len);\n    if (trace_memory)\n      PORTAL_PRINTF(\"DmaManager:sglist(id=%08x, i=%d dma_addr=%08lx, len=%08lx)\\n\", id, i, (long)addr, len);\n    MMURequest_sglist(device, id, i, addr, len);\n  } // balance }\n#ifdef __KERNEL__\n  fput(fmem);\n#endif\n\n  // HW interprets zeros as end of sglist\n  if (trace_memory)\n    PORTAL_PRINTF(\"DmaManager:sglist(id=%08x, i=%d end of list)\\n\", id, i);\n  MMURequest_sglist(device, id, i, 0, 0); // end list\n\n  for(i = 0; i < 4; i++){\n    idxOffset = entryCount - border;\n    entryCount += regions[i];\n    border += regions[i];\n    borderVal[i] = border;\n    indexVal[i] = idxOffset;\n    border <<= (shifts[i] - shifts[i+1]);\n  }\n  if (trace_memory) {\n    PORTAL_PRINTF(\"regions %d (%x %x %x %x)\\n\", id, regions[0], regions[1], regions[2], regions[3]);\n    PORTAL_PRINTF(\"borders %d (%\" PRIx64 \" %\" PRIx64 \" %\" PRIx64 \" %\" PRIx64 \")\\n\", id,borderVal[0], borderVal[1], borderVal[2], borderVal[3]);\n  }\n  MMURequest_region(device, id, borderVal[0], indexVal[0], borderVal[1], indexVal[1], borderVal[2], indexVal[2], borderVal[3], indexVal[3]);\n  /* ifdefs here to supress warning during kernel build */\n#ifndef __KERNEL__\nretlab:\n#endif\n    return rc;\n}\n"
  },
  {
    "path": "cpp/kernel_module.c",
    "content": "// Copyright (c) 2014 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\n/*\n * This is a test harness for running connectal test programs as kernel modules.\n *\n * After the module is loaded, it calls 'main(0, NULL)' to start the program.\n */\n\n#include <linux/module.h>\n#include <linux/kernel.h>\n#include <linux/miscdevice.h>\n#include <linux/fs.h>\n#include <linux/kthread.h>\n\n#include \"portal.h\"   // pthread_t\n\nextern int main(int argc, char *argv[]);\nint bsim_relay_running;\nstruct semaphore bsim_start;\nDECLARE_COMPLETION(main_completion);\n\nint pthread_create(pthread_t *thread, void *attr, void *(*start_routine) (void *), void *arg)\n{\n  if (!(*thread = kthread_run ((int (*)(void *))start_routine, arg, \"pthread_worker\"))) {\n        printk (\"pthread_create: kthread_run failed\");\n  }\n  return 0;\n}\nvoid memdump(unsigned char *p, int len, char *title)\n{\nint i;\n\n    i = 0;\n    while (len > 0) {\n        if (!(i & 0xf)) {\n            if (i > 0)\n                printk(\"\\n\");\n            printk(\"%s: \",title);\n        }\n        printk(\"%02x \", *p++);\n        i++;\n        len--;\n    }\n    printk(\"\\n\");\n}\n\n/* in sock_utils.c */\nssize_t connectal_kernel_read (struct file *f, char __user *arg, size_t len, loff_t *data);\nssize_t connectal_kernel_write (struct file *f, const char __user *arg, size_t len, loff_t *data);\nint main_program_finished = 0;\n\nstatic struct file_operations pa_fops = {\n    .owner = THIS_MODULE,\n#if defined(SIMULATION)\n    .read = connectal_kernel_read,\n    .write = connectal_kernel_write,\n#endif\n  };\nstatic struct miscdevice miscdev = {\n  .minor = MISC_DYNAMIC_MINOR,  // Must be < 256!\n  .name = \"connectal_unknown\",\n  .fops = &pa_fops,\n  .mode = S_IRUGO | S_IWUGO,\n};\n\nvoid *main_start(void *arg)\n{\n  main(0, NULL); /* start the test program */\n  printk(\"TestProgram::main program finished\\n\");\n  complete(&main_completion);\n  main_program_finished = 1;\n  return NULL;\n}\n\nstatic int __init pa_init(void)\n{\n  pthread_t pid;\n  printk(\"TestProgram::pa_init minor %d thisname %s\\n\", miscdev.minor, THIS_MODULE->name);\n  miscdev.name = THIS_MODULE->name;\n  misc_register(&miscdev);\n  sema_init (&bsim_start, 0);\n  pthread_create(&pid, NULL, main_start, NULL);\n  return 0;\n}\n\nstatic void __exit pa_exit(void)\n{\n  printk(\"TestProgram::pa_exit %s\\n\", THIS_MODULE->name);\n#ifdef SIMULATION\n  if (!bsim_relay_running) {\n    printk(\"TestProgram::pa_exit terminate main program\\n\");\n    main_program_finished = 1;\n    up(&bsim_start); // in case host never starts\n  }\n  else\n#endif\n    wait_for_completion(&main_completion);\n  misc_deregister(&miscdev);\n}\n\nmodule_init(pa_init);\nmodule_exit(pa_exit);\n\nMODULE_LICENSE(\"GPL v2\");\nMODULE_DESCRIPTION(\"connectal test program\");\nMODULE_VERSION(\"0.1\");\n"
  },
  {
    "path": "cpp/manualMMUIndication.h",
    "content": "// Copyright (c) 2015 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\n#include \"dmaManager.h\"\n#include \"MMUIndication.h\"\n\nstatic int return_code;\nstatic uint32_t return_id;\nenum {ManualMMU_None, ManualMMU_IdResponse, ManualMMU_ConfigResp, ManualMMU_Error};\nstatic int manualDisconnect(struct PortalInternal *p)\n{\n    return 0;\n}\nstatic int manualIdResponse(struct PortalInternal *p, const uint32_t sglId )\n{\n    return_id = sglId;\n    return_code = ManualMMU_IdResponse;\n    return 0;\n}\nstatic int manualConfigResp(struct PortalInternal *p, const uint32_t sglId )\n{\n    return_id = sglId;\n    return_code = ManualMMU_ConfigResp;\n    return 0;\n}\nstatic int manualError(struct PortalInternal *p, const uint32_t code, const uint32_t sglId, const uint64_t offset, const uint64_t extra )\n{\n    return_code = ManualMMU_Error;\n    return 0;\n}\nstatic MMUIndicationCb manualMMU_Cb = {manualDisconnect, manualIdResponse, manualConfigResp, manualError};\n\nstatic int manualWaitForResp(PortalInternal *p, uint32_t *arg_id)\n{\n    return_code = ManualMMU_None;\nprintf(\"[%s:%d]\\n\", __FUNCTION__, __LINE__);\n    while(return_code == ManualMMU_None) {\n        p->transport->event(p);\n    }\nprintf(\"[%s:%d]\\n\", __FUNCTION__, __LINE__);\n    *arg_id = return_id;\n    return return_code;\n}\n"
  },
  {
    "path": "cpp/monkit.h",
    "content": "// Copyright (c) 2014 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\n#ifndef _MONKIT_H_\n#define _MONKIT_H_\n#include <stdio.h>\n#include <errno.h>\n#include <string.h> // strerrror\n\nclass MonkitFile {\n public:\n \n  MonkitFile(const char *name) : name(name), hw_cycles(1), sw_cycles(0), hw_read_bw_util(0), hw_write_bw_util(0) {}\n  ~MonkitFile() {}\n  MonkitFile &setHwCycles(float cycles) { this->hw_cycles = cycles; return *this; }\n  MonkitFile &setSwCycles(float cycles) { this->sw_cycles = cycles; return *this; }\n  MonkitFile &setReadBwUtil(float u) { this->hw_read_bw_util = u; return *this; }\n  MonkitFile &setWriteBwUtil(float u) { this->hw_write_bw_util = u; return *this; }\n  void writeFile();\n  \n private:\n  const char *name;\n  float hw_cycles;\n  float sw_cycles;\n  float hw_read_bw_util;\n  float hw_write_bw_util;\n};\n\n#define monkit \"<?xml version=\\\"1.0\\\" encoding=\\\"UTF-8\\\"?>\\n\\\n<categories>\\n\\\n    <category name=\\\"time\\\" scale=\\\"cycles\\\">\\n\\\n        <observations>\\n\\\n            <observation name=\\\"hw_cycles\\\">%f</observation>\\n\\\n            <observation name=\\\"sw_cycles\\\">%f</observation>\\n\\\n        </observations>\\n\\\n    </category>\\n\\\n    \\n\\\n    <category name=\\\"utilization\\\" scale=\\\"%%\\\">\\n\\\n        <observations>\\n\\\n            <observation name=\\\"read_memory_bw\\\">%f</observation>\\n\\\n            <observation name=\\\"write_memory_bw\\\">%f</observation>\\n\\\n        </observations>\\n\\\n    </category>\\n\\\n    <category name=\\\"speedup\\\" scale=\\\"X\\\">\\n\\\n        <observations>\\n\\\n            <observation name=\\\"hw_speedup\\\">%f</observation>\\n\\\n        </observations>\\n\\\n    </category>\\n\\\n</categories>\\n\"\n\nvoid MonkitFile::writeFile()\n{\n  float hw_speedup = sw_cycles/hw_cycles;\n  FILE *out = fopen(name, \"w\");\n  if (out) {\n    fprintf(out, monkit, hw_cycles, sw_cycles, hw_read_bw_util, hw_write_bw_util, hw_speedup);\n    fclose(out);\n  } else {\n    fprintf(stderr, \"Failed to open MonkitFile %s errno=%d:%s\\n\", name, errno, strerror(errno));\n  }\n}\n\n#endif\n"
  },
  {
    "path": "cpp/platformMemory.cpp",
    "content": "\n// Copyright (c) 2013-2014 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n#include <assert.h>\n#include \"dmaManager.h\"\n#include \"MMURequest.h\"\n#include \"MMUIndication.h\"\n#include \"MemServerRequest.h\"\n#include \"MemServerIndication.h\"\n\n#define PLATFORM_TILE 0\n\nclass PortalPoller;\nint mmu_error_limit = 20;\nint mem_error_limit = 20;\nconst char *dmaErrors[] = {\n\t\t\t\t\"None\",\n\t\t\t\t\"SGL Id out of range for read\",\n\t\t\t\t\"SGL Id out of range for write\",\n\t\t\t\t\"MMU out of range for read\",\n\t\t\t\t\"MMU out of range for write\",\n\t\t\t\t\"Offset out of range\",\n\t\t\t\t\"SGL Id invalid\",\n\t\t\t\t\"Tile tag out of range\"\n\t\t\t\t};\nclass MMUIndication : public MMUIndicationWrapper\n{\n  DmaManager *portalMemory;\n public:\n  MMUIndication(DmaManager *pm, unsigned int  id, int tile=PLATFORM_TILE) : MMUIndicationWrapper(id,tile), portalMemory(pm) {}\n  MMUIndication(DmaManager *pm, unsigned int  id, PortalTransportFunctions *item, void *param) : MMUIndicationWrapper(id, item, param), portalMemory(pm) {}\n  virtual void configResp(uint32_t pointer){\n    portalMemory->confResp(pointer);\n  }\n  virtual void error (uint32_t code, uint32_t pointer, uint64_t offset, uint64_t extra) {\n    fprintf(stderr, \"MMUIndication::error(code=0x%x:%s, pointer=0x%x, offset=0x%\" PRIx64 \" extra=0x%\" PRIx64 \"\\n\", code, dmaErrors[code], pointer, offset, extra);\n    if (--mmu_error_limit < 0)\n        exit(-1);\n  }\n  virtual void idResponse(uint32_t sglId){\n    portalMemory->sglIdResp(sglId);\n  }\n};\n\nclass MemServerIndication : public MemServerIndicationWrapper\n{\n  MemServerRequestProxy *memServerRequestProxy;\n  sem_t mtSem;\n  uint64_t mtCnt;\n  void init(){\n    if (sem_init(&mtSem, 0, 0))\n      PORTAL_PRINTF(\"MemServerIndication::init failed to init mtSem\\n\");\n  }\n public:\n  MemServerIndication(unsigned int  id, int tile=PLATFORM_TILE) : MemServerIndicationWrapper(id,tile), memServerRequestProxy(NULL) {init();}\n  MemServerIndication(MemServerRequestProxy *p, unsigned int  id, int tile=PLATFORM_TILE) : MemServerIndicationWrapper(id,tile), memServerRequestProxy(p) {init();}\n  virtual void addrResponse(uint64_t physAddr){\n    fprintf(stderr, \"DmaIndication::addrResponse(physAddr=%\" PRIx64 \")\\n\", physAddr);\n  }\n  virtual void reportStateDbg(const DmaDbgRec rec){\n    fprintf(stderr, \"MemServerIndication::reportStateDbg: {x:%08x y:%08x z:%08x w:%08x}\\n\", rec.x,rec.y,rec.z,rec.w);\n  }\n  virtual void reportMemoryTraffic(uint64_t words){\n    //fprintf(stderr, \"reportMemoryTraffic: words=%\" PRIx64 \"\\n\", words);\n    mtCnt = words;\n    sem_post(&mtSem);\n  }\n  virtual void error (uint32_t code, uint32_t pointer, uint64_t offset, uint64_t extra) {\n    fprintf(stderr, \"MemServerIndication::error(code=%x:%s, pointer=%x, offset=%\" PRIx64 \" extra=%\" PRIx64 \"\\n\", code, dmaErrors[code], pointer, offset, extra);\n    if (--mem_error_limit < 0)\n      exit(-1);\n  }\n  uint64_t receiveMemoryTraffic(){\n    sem_wait(&mtSem);\n    return mtCnt; \n  }\n  uint64_t getMemoryTraffic(const ChannelType rc){\n    assert(memServerRequestProxy);\n    memServerRequestProxy->memoryTraffic(rc);\n    return receiveMemoryTraffic();\n  }\n};\n\nstatic MemServerRequestProxy *hostMemServerRequest;\nstatic MemServerIndication *hostMemServerIndication;\nstatic MMUIndication *mmuIndication;\nstatic DmaManager *dma;\nstatic pthread_once_t once_control = PTHREAD_ONCE_INIT;\nvoid platformInitOnce(void)\n{\n    hostMemServerRequest = new MemServerRequestProxy(PlatformIfcNames_MemServerRequestS2H, PLATFORM_TILE);\n    MMURequestProxy *dmap = new MMURequestProxy(PlatformIfcNames_MMURequestS2H, PLATFORM_TILE);\n    dma = new DmaManager(dmap);\n    hostMemServerIndication = new MemServerIndication(hostMemServerRequest, PlatformIfcNames_MemServerIndicationH2S, PLATFORM_TILE);\n    mmuIndication = new MMUIndication(dma, PlatformIfcNames_MMUIndicationH2S, PLATFORM_TILE);\n\n#ifdef MainClockPeriod\n    long req_freq = (long)(1e9 / MainClockPeriod);\n    long freq = 0;\n    setClockFrequency(0, req_freq, &freq);\n    fprintf(stderr, \"Requested FCLK[0]=%ld actually %ld\\n\", req_freq, freq);\n#endif\n}\nDmaManager *platformInit(void)\n{\n    pthread_once(&once_control, platformInitOnce);\n    return dma;\n}\n\nvoid platformStatistics(void)\n{\n    uint64_t cycles = portalTimerLap(0);\n    hostMemServerRequest->memoryTraffic(ChannelType_Read);\n    uint64_t read_beats = hostMemServerIndication->receiveMemoryTraffic();\n    float read_util = (float)read_beats/(float)cycles;\n    hostMemServerRequest->memoryTraffic(ChannelType_Write);\n    uint64_t write_beats = hostMemServerIndication->receiveMemoryTraffic();\n    float write_util = (float)write_beats/(float)cycles;\n    fprintf(stderr, \"   read_beats: %lld\\n\", (long long)read_beats);\n    fprintf(stderr, \"  write_beats: %lld\\n\", (long long)write_beats);\n    fprintf(stderr, \"       cycles: %lld\\n\", (long long)cycles);\n    fprintf(stderr, \"memory utilization (beats/cycle): read %f write %f\\n\", read_util, write_util);\n}\n"
  },
  {
    "path": "cpp/poller.cpp",
    "content": "// Copyright (c) 2012 Nokia, Inc.\n// Copyright (c) 2013-2014 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n#include \"portal.h\"\n#include \"sock_utils.h\"\n#include <string.h>\n#include <poll.h>\n#include <errno.h>\n#include <pthread.h>\n#include <fcntl.h>\n\nstatic int trace_poller;//=1;\n\n#ifndef NO_CPP_PORTAL_CODE\nPortalPoller *defaultPoller = new PortalPoller();\nuint64_t poll_enter_time, poll_return_time; // for performance measurement\n\nPortalPoller::PortalPoller(int autostart)\n  : startThread(autostart), numWrappers(0), numFds(0), inPoll(0), stopping(0)\n{\n    memset(portal_fds, 0, sizeof(portal_fds));\n    memset(portal_wrappers, 0, sizeof(portal_wrappers));\n    int rc = pipe(pipefd);\n    if (rc != 0)\n      fprintf(stderr, \"[%s:%d] pipe error %d:%s\\n\", __FUNCTION__, __LINE__, errno, strerror(errno));\n    sem_init(&sem_startup, 0, 0);\n    pthread_mutex_init(&mutex, NULL);\n    fcntl(pipefd[0], F_SETFL, O_NONBLOCK);\n    addFd(pipefd[0]);\n\n    timeout = -1; // wait for interrupt\n#if defined(SIMULATION)\n    timeout = 100;\n#endif\n    if (getenv(\"PORTAL_TIMEOUT\") != 0) {\n        timeout = strtoul(getenv(\"PORTAL_TIMEOUT\"), 0, 0);\n    }\n}\n\nint PortalPoller::unregisterInstance(Portal *portal)\n{\n    int i = 0;\n    pthread_mutex_lock(&mutex);\n    while(i < numWrappers){\n        if(portal_wrappers[i]->pint.fpga_number == portal->pint.fpga_number) {\n\t    //fprintf(stderr, \"PortalPoller::unregisterInstance %d %d\\n\", i, portal->pint.fpga_number);\n            break;\n        }\n        i++;\n    }\n\n    while(i < numWrappers-1){\n        portal_wrappers[i] = portal_wrappers[i+1];\n        i++;\n    }\n    numWrappers--;\n    i = 0;\n    while(i < numFds){\n        if(portal_fds[i].fd == portal->pint.fpga_fd)\n            break;\n        i++;\n    }\n\n    while(i < numFds-1){\n        portal_fds[i] = portal_fds[i+1];\n        i++;\n    }\n    numFds--;\n    pthread_mutex_unlock(&mutex);\n    return 0;\n}\n\nvoid PortalPoller::addFd(int fd)\n{\n    /* this internal function assumes mutex locked by caller.\n     * since it can be called from addFdToPoller(), which was called under mutex lock\n     * event().\n     */\n    numFds++;\n    struct pollfd *pollfd = &portal_fds[numFds-1];\n    memset(pollfd, 0, sizeof(struct pollfd));\n    pollfd->fd = fd;\n    pollfd->events = POLLIN;\n}\n\nint PortalPoller::registerInstance(Portal *portal)\n{\n    uint8_t ch = 0;\n    pthread_mutex_lock(&mutex);\n    int rc = write(pipefd[1], &ch, 1); // get poll to return, so that it will try again with the new file descriptor\n    if (rc < 0)\n        fprintf(stderr, \"[%s:%d] write error %d\\n\", __FUNCTION__, __LINE__, errno);\n    numWrappers++;\n    if (trace_poller)\n        fprintf(stderr, \"Poller: registerInstance fpga%d fd %d clients %d\\n\", portal->pint.fpga_number, portal->pint.fpga_fd, portal->pint.client_fd_number);\n    while(inPoll)\n        usleep(1000);\n    portal_wrappers[numWrappers-1] = portal;\n\n    if (portal->pint.fpga_fd != -1)\n        addFd(portal->pint.fpga_fd);\n    for (int i = 0; i < portal->pint.client_fd_number; i++)\n        addFd(portal->pint.client_fd[i]);\n    portal->pint.transport->enableint(&portal->pint, 1);\n    pthread_mutex_unlock(&mutex);\n    start();\n    return 0;\n}\n\nvoid* PortalPoller::init(void)\n{\n#ifdef SIMULATION\n    if (global_sockfd != -1) {\n        pthread_mutex_lock(&mutex);\n        addFd(global_sockfd);\n        pthread_mutex_unlock(&mutex);\n    }\n#endif\n    //fprintf(stderr, \"Poller: about to enter loop, numFds=%d\\n\", numFds);\n    return NULL;\n}\nvoid PortalPoller::stop(void)\n{\n    uint8_t ch = 0;\n    int rc;\n    stopping = 1;\n    startThread = 0;\n    rc = write(pipefd[1], &ch, 1);\n    if (rc < 0)\n        fprintf(stderr, \"[%s:%d] write error %d\\n\", __FUNCTION__, __LINE__, errno);\n}\nvoid PortalPoller::end(void)\n{\n    stopping = 1;\n    fprintf(stderr, \"%s: don't disable interrupts when stopping\\n\", __FUNCTION__);\n    return;\n    pthread_mutex_lock(&mutex);\n    for (int i = 0; i < numWrappers; i++) {\n        Portal *instance = portal_wrappers[i];\n        fprintf(stderr, \"Poller::disabling interrupts portal %d fpga%d\\n\", i, instance->pint.fpga_number);\n        instance->pint.transport->enableint(&instance->pint, 0);\n    }\n    pthread_mutex_unlock(&mutex);\n}\n\nvoid* PortalPoller::pollFn(int timeout)\n{\n    long rc = 0;\n    //printf(\"[%s:%d] before poll %d numFds %d\\n\", __FUNCTION__, __LINE__, timeout, numFds);\n    //for (int i = 0; i < numFds; i++)\n        //printf(\"%s: fd %d events %x\\n\", __FUNCTION__, portal_fds[i].fd, portal_fds[i].events);\n    inPoll = 1;\n    if (timeout != 0)\n        rc = poll(portal_fds, numFds, timeout);\n    inPoll = 0;\n    if(rc < 0) {\n        // return only in error case\n        fprintf(stderr, \"Poller: poll returned rc=%ld errno=%d:%s\\n\", rc, errno, strerror(errno));\n    }\n    return (void*)rc;\n}\n\nvoid* PortalPoller::event(void)\n{\n    uint8_t ch;\n    pthread_mutex_lock(&mutex);\n    size_t rc = read(pipefd[0], &ch, 1);\n    if (rc < 0)\n        fprintf(stderr, \"[%s:%d] read error %d\\n\", __FUNCTION__, __LINE__, errno);\n    for (int i = 0; i < numWrappers; i++) {\n        if (!portal_wrappers)\n            fprintf(stderr, \"Poller: No portal_instances revents=%d\\n\", portal_fds[i].revents);\n        Portal *instance = portal_wrappers[i];\n        if (trace_poller)\n            fprintf(stderr, \"Poller: event tile %d fpga%d fd %d handler %p parent %p\\n\",\n                instance->pint.fpga_tile, instance->pint.fpga_number, instance->pint.fpga_fd, instance->pint.handler, instance->pint.parent);\n        instance->pint.transport->event(&instance->pint);\n        if (instance->pint.handler) {\n            // re-enable interrupt which was disabled by portal_isr\n            instance->pint.transport->enableint(&instance->pint, 1);\n        }\n    }\n    pthread_mutex_unlock(&mutex);\n    return NULL;\n}\nextern \"C\" void addFdToPoller(struct PortalPoller *poller, int fd)\n{\n    poller->addFd(fd);\n}\n\nvoid* PortalPoller::threadFn(void* __x)\n{\n    void *rc = init();\n    sem_post(&sem_startup);\n    while (!rc && !stopping) {\n        rc = pollFn(timeout);\n        if ((long) rc >= 0)\n            rc = event();\n    }\n    end();\n    fprintf(stderr, \"[%s] thread ending\\n\", __FUNCTION__);\n    return rc;\n}\n\nstatic void *pthread_worker(void *__x)\n{\n    ((PortalPoller *)__x)->threadFn(__x);\n    return 0;\n}\n\nvoid PortalPoller::start()\n{\n    pthread_t threaddata;\n    pthread_mutex_lock(&mutex);\n    if (!startThread) {\n        pthread_mutex_unlock(&mutex);\n        return;\n    }\n    startThread = 0;\n    pthread_mutex_unlock(&mutex);\n    pthread_create(&threaddata, NULL, &pthread_worker, (void *)this);\n    sem_wait(&sem_startup);\n}\n#endif // NO_CPP_PORTAL_CODE\n"
  },
  {
    "path": "cpp/portal.c",
    "content": "// Copyright (c) 2012 Nokia, Inc.\n// Copyright (c) 2013-2014 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n#include \"ConnectalProjectConfig.h\"\n\n#include \"portal.h\"\n#include \"sock_utils.h\"\n#ifdef __KERNEL__\n#include \"linux/delay.h\"\n#include \"linux/file.h\"\n#include \"linux/dma-buf.h\"\n#else\n#include <stdlib.h>\n#include <string.h>\n#include <errno.h>\n#include <fcntl.h>\n#include <sys/mman.h>\n#include <unistd.h>\n#include <sys/ioctl.h>\n#include <time.h> // ctime\n#include <stdarg.h> // for portal_printf\n#include <sys/wait.h>\n#include <sys/stat.h>\n#include <libgen.h>  // dirname\n#include <pthread.h>\n#endif\n\n#ifdef __APPLE__ // hack for debugging\n#include <libproc.h>\n#else\n#include \"drivers/portalmem/portalmem.h\" // PA_MALLOC\n#if defined(ZYNQ) || defined(__riscv__)\n#include \"drivers/zynqportal/zynqportal.h\"\n#else\n#include \"drivers/pcieportal/pcieportal.h\" // BNOC_TRACE\n#endif\n#endif // !__APPLE__\n\nint simulator_dump_vcd = 0;\nconst char *simulator_vcd_name = \"dump.vcd\";\n// set this to 1 to suppress call to fpgajtag\n#ifndef DEFAULT_NOPROGRAM\n#define DEFAULT_NOPROGRAM 0\n#endif\nint noprogram = DEFAULT_NOPROGRAM;\n\nstatic int trace_portal;//= 1;\n\nint global_pa_fd = -1;\nPortalInternal *utility_portal = 0x0;\nvoid (*connectalPrintfHandler)(struct PortalInternal *p, unsigned int header);\n\n#ifdef __KERNEL__\nstatic tBoard* tboard;\n#endif\n\n/*\n * Initialize control data structure for portal\n */\nvoid init_portal_internal(PortalInternal *pint, int id, int tile,\n    PORTAL_INDFUNC handler, void *cb, PortalTransportFunctions *transport, void *param, void *parent,\n    uint32_t reqinfo)\n{\n    int rc;\n    memset(pint, 0, sizeof(*pint));\n    if(!utility_portal)\n      utility_portal = pint;\n    pint->board_number = 0;\n    pint->fpga_number = id;\n    pint->fpga_tile = tile;\n    pint->fpga_fd = -1;\n    pint->muxid = -1;\n    pint->handler = handler;\n    pint->cb = (PortalHandlerTemplate *)cb;\n    pint->parent = parent;\n    pint->reqinfo = reqinfo;\n    pint->busyType = BUSY_SPIN;\n    if (getenv(\"FPGA_NUMBER\") != 0)\n\tpint->board_number = strtoul(getenv(\"FPGA_NUMBER\"), 0, 0);\n    if(trace_portal)\n\tPORTAL_PRINTF(\"%s: **initialize portal_b%dt%dp%d handler %p cb %p parent %p\\n\", __FUNCTION__, pint->board_number, pint->fpga_tile, pint->fpga_number, handler, cb, parent);\n    if (!transport) {\n        // Use defaults for transport handling methods\n#if defined(SIMULATION) && !defined(__ATOMICC__)\n        transport = &transportXsim;\n#else\n        transport = &transportHardware;\n#endif\n    }\n    pint->transport = transport;\n    rc = pint->transport->init(pint, param);\n    if (rc != 0) {\n        PORTAL_PRINTF(\"%s: failed to initialize Portal portal_b%dt%dp%d\\n\", __FUNCTION__, pint->board_number, pint->fpga_tile, pint->fpga_number);\n#ifndef __KERNEL__\n        exit(1);\n#endif\n    }\n}\nint portal_disconnect(struct PortalInternal *pint)\n{\n    if(trace_portal)\n        PORTAL_PRINTF(\"[%s:%d] fpgafd %d num %d cli %d\\n\", __FUNCTION__, __LINE__, pint->fpga_fd, pint->client_fd_number, pint->client_fd[0], pint->client_fd[1]);\n    close(pint->fpga_fd);\n    if (pint->client_fd_number > 0)\n        close(pint->client_fd[--pint->client_fd_number]);\n    return 0;\n}\n\nint portal_event(struct PortalInternal *pint)\n{\n#if defined(SIMULATION) && !defined(__ATOMICC__)\n    return event_xsim(pint);\n#else\n    return event_hardware(pint);\n#endif\n}\n\nchar *getExecutionFilename(char *buf, int buflen)\n{\n    int rc, fd;\n#ifdef __APPLE__ // hack for debugging\n    static char pathbuf[PROC_PIDPATHINFO_MAXSIZE];\n    rc = proc_pidpath (getpid(), pathbuf, sizeof(pathbuf));\n    return pathbuf;\n#endif\n    char *filename = 0;\n    buf[0] = 0;\n    fd = open(\"/proc/self/maps\", O_RDONLY);\n    while ((rc = read(fd, buf, buflen-1)) > 0) {\n\tbuf[rc] = 0;\n\trc = 0;\n\twhile(buf[rc]) {\n\t    char *endptr;\n\t    unsigned long addr = strtoul(&buf[rc], &endptr, 16);\n\t    if (endptr && *endptr == '-') {\n\t\tchar *endptr2;\n\t\tunsigned long addr2 = strtoul(endptr+1, &endptr2, 16);\n\t\tif (addr <= (unsigned long)&initPortalHardware && (unsigned long)&initPortalHardware <= addr2) {\n\t\t    filename = strstr(endptr2, \"  \");\n\t\t    while (*filename == ' ')\n\t\t\tfilename++;\n\t\t    endptr2 = strstr(filename, \"\\n\");\n\t\t    if (endptr2)\n\t\t\t*endptr2 = 0;\n\t\t    fprintf(stderr, \"buffer %s\\n\", filename);\n\t\t    goto endloop;\n\t\t}\n\t    }\n\t    while(buf[rc] && buf[rc] != '\\n')\n\t\trc++;\n\t    if (buf[rc])\n\t\trc++;\n\t}\n    }\nendloop:\n    if (!filename) {\n\tfprintf(stderr, \"[%s:%d] could not find execution filename\\n\", __FUNCTION__, __LINE__);\n\treturn 0;\n    }\n    return filename;\n}\n/*\n * One time initialization of portal framework\n */\nstatic pthread_once_t once_control;\nstatic void initPortalHardwareOnce(void)\n{\n#ifdef __KERNEL__\n    tboard = get_pcie_portal_descriptor();\n#else\n    /*\n     * fork/exec 'fpgajtag' to download bits to hardware\n     * (the FPGA bits are stored as an extra ELF segment in the executable file)\n     */\n    int pid = fork();\n    if (pid == -1) {\n\tfprintf(stderr, \"[%s:%d] fork error\\n\", __FUNCTION__, __LINE__);\n        exit(-1);\n    }\n    else if (pid) {\n#ifndef SIMULATION\n        int status;\n        waitpid(pid, &status, 0);\n\tfprintf(stderr, \"subprocess pid %d completed status=%x %d\\n\", pid, status, WEXITSTATUS(status));\n#ifndef BOARD_de5\n\tif (WEXITSTATUS(status) != 0)\n\t    exit(-1);\n#endif\n\t{\n\t  int fd = -1;\n\t  ssize_t len;\n\t  int attempt;\n\t  for (attempt = 0; attempt < 10; attempt++) {\n            struct stat statbuf;\n            int rc = stat(\"/dev/connectal\", &statbuf); /* wait for driver to load */\n            if (rc == -1)\n                continue;\n\t    fd = open(\"/dev/connectal\", O_RDONLY); /* scan the fpga directory */\n\t    if (fd < 0) {\n\t\tfprintf(stderr, \"[%s:%d] waiting for '/dev/connectal'\\n\", __FUNCTION__, __LINE__);\n\t\tsleep(1);\n\t\tcontinue;\n\t    }\n\t    len = read(fd, &status, sizeof(status));\n\t    if (len < (ssize_t)sizeof(status))\n\t      fprintf(stderr, \"[%s:%d] fd %d len %lu\\n\", __FUNCTION__, __LINE__, fd, (unsigned long)len);\n\t    close(fd);\n\t    break;\n\t  }\n\t  if (fd == -1) {\n\t      PORTAL_PRINTF(\"Error: %s: failed to open /dev/connectal, exiting\\n\", __FUNCTION__);\n\t      exit(-1);\n\t  }\n\t}\n#endif // !defined(SIMULATION)\n    }\n    else {\n#define MAX_PATH 2000\n        static char buf[400000];\n        char *filename = NULL;\n        char *argv[] = { (char *)\"fpgajtag\", NULL, NULL, NULL, NULL, NULL, NULL, NULL};\n\tint ind = 1;\n        if (noprogram || getenv(\"NOFPGAJTAG\") || getenv(\"NOPROGRAM\"))\n            exit(0);\n#ifndef SIMULATOR_USE_PATH\n\tfilename = getExecutionFilename(buf, sizeof(buf));\n#endif\n#ifdef SIMULATION\n        char *bindir = (filename) ? dirname(filename) : 0;\n        static char exename[MAX_PATH];\n        char *library_path = 0;\n\tif (getenv(\"DUMP_VCD\")) {\n\t  simulator_dump_vcd = 1;\n\t  simulator_vcd_name = getenv(\"DUMP_VCD\");\n\t}\n#if defined(BOARD_bluesim)\n\tconst char *exetype = \"bsim\";\n\targv[ind++] = (char*)\"-w\"; // wait for license\n\tif (simulator_dump_vcd) {\n\t  argv[ind++] = (char*)\"-V\";\n\t  argv[ind++] = (char*)simulator_vcd_name;\n\t}\n#endif\n#if defined(BOARD_ncverilog)\n\tconst char *exetype = \"ncverilog\";\n\tbindir = 0; // the simulation driver is found in $PATH\n\t//FIXME ARGS\n#endif\n#if defined(BOARD_verilator)\n\tconst char *exetype = \"vlsim\";\n\tif (simulator_dump_vcd) {\n\t  argv[ind++] = (char*)\"-t\";\n\t  argv[ind++] = (char*)simulator_vcd_name;\n\t}\n#endif\n#if defined(BOARD_cvc)\n\tconst char *exetype = \"cvcsim\";\n\tif (simulator_dump_vcd) {\n\t  //argv[ind++] = (char*)\"-t\";\n\t  //argv[ind++] = (char*)simulator_vcd_name;\n\t}\n#endif\n#if defined(BOARD_xsim)\n\tconst char *exetype = \"xsim\";\n\tbindir = 0; // the simulation driver is found in $PATH\n        argv[ind++] = (char *)\"-R\";\n        argv[ind++] = (char *)\"work.xsimtop\";\n#endif\n#if defined(BOARD_vcs)\n\tconst char *exetype = \"simv\";\n        argv[ind++] = (char *)\"+verbose=1\";\n        argv[ind++] = (char *)\"-assert\";\n        argv[ind++] = (char *)\"verbose+success\";\n\tif (simulator_dump_vcd) {\n\t  //argv[ind++] = (char*)\"-t\";\n\t  //argv[ind++] = (char*)simulator_vcd_name;\n\t}\n#endif\n#if defined(BOARD_vsim)\n\tconst char *exetype = \"vsim\";\n\tbindir = 0; // the simulation driver is found in $PATH\n        argv[ind++] = (char *)\"-c\";\n        argv[ind++] = (char *)\"-sv_lib\";\n        argv[ind++] = (char *)\"xsimtop\";\n        argv[ind++] = (char *)\"work.xsimtop\";\n        argv[ind++] = (char *)\"-do\";\n        argv[ind++] = (char *)\"run -all; quit -f\";\n#endif\n\tif (bindir)\n\t    sprintf(exename, \"%s/%s\", bindir, exetype);\n\telse\n\t    sprintf(exename, \"%s\", exetype);\n\targv[0] = exename;\nif (trace_portal) fprintf(stderr, \"[%s:%d] %s %s *******\\n\", __FUNCTION__, __LINE__, exetype, exename);\n        argv[ind++] = NULL;\n\tif (bindir) {\n\t    const char *old_library_path = getenv(\"LD_LIBRARY_PATH\");\n\t    int library_path_len = strlen(bindir);\n\t    if (old_library_path)\n\t\tlibrary_path_len += strlen(old_library_path);\n\t    library_path = (char *)malloc(library_path_len + 2);\n\t    if (old_library_path)\n\t\tsnprintf(library_path, library_path_len+2, \"%s:%s\", bindir, old_library_path);\n\t    else\n\t\tsnprintf(library_path, library_path_len+1, \"%s\", bindir);\n\t    setenv(\"LD_LIBRARY_PATH\", library_path, 1);\nif (trace_portal) fprintf(stderr, \"[%s:%d] LD_LIBRARY_PATH %s *******\\n\", __FUNCTION__, __LINE__, library_path);\n\t}\n        execvp (exename, argv);\n\tfprintf(stderr, \"[%s:%d] exec(%s) failed errno=%d:%s\\n\", __FUNCTION__, __LINE__, exename, errno, strerror(errno));\n#else // !defined(SIMULATION)\n        char *serial = getenv(\"SERIALNO\");\n        if (serial) {\n            argv[ind++] = (char *)\"-s\";\n            argv[ind++] = strdup(serial);\n        }\n        {\n#ifdef __ANDROID__\n\t  // on zynq android, fpgajtag is in the initramdisk in the root directory\n\t  const char *fpgajtag = \"/fpgajtag\";\n#else\n\t  const char *fpgajtag = \"fpgajtag\";\n#endif // !__arm__\n#ifdef __arm__\n\t  argv[ind++] = (char *)\"-x\"; // program via /dev/xdevcfg\n#endif\n#ifdef __aarch64__\n\t  argv[ind++] = (char *)\"-m\"; // program via fpga manager\n#endif\n\t  argv[ind++] = filename;\n          errno = 0;\n          if (filename) // only run fpgajtag if filename was found\n\t      execvp (fpgajtag, argv);\n\t  fprintf(stderr, \"[%s:%d] exec(%s) failed errno=%d:%s\\n\", __FUNCTION__, __LINE__, fpgajtag, errno, strerror(errno));\n        }\n#endif // !SIMULATION\n        exit(-1);\n    }\n#endif // !__KERNEL__\n}\nvoid initPortalHardware(void)\n{\n    pthread_once(&once_control, initPortalHardwareOnce);\n}\n\n/*\n * Utility functions for alloc/mmap/cache for shared memory\n */\nvoid initPortalMemory(void)\n{\n#ifndef __KERNEL__\n    if (global_pa_fd == -1)\n#ifndef SIMULATION\n        global_pa_fd = open(\"/dev/portalmem\", O_RDWR);\n    if (global_pa_fd < 0){\n\tPORTAL_PRINTF(\"Failed to open /dev/portalmem pa_fd=%d errno=%d:%s\\n\", global_pa_fd, errno, strerror(errno));\n        exit(ENODEV);\n    }\n#else\n        global_pa_fd = -1;\n#endif\n#endif\n}\n\nint portalmem_sizes[1024];\n\nint portalAlloc(size_t size, int cached)\n{\n    int fd;\n    initPortalMemory();\n#ifdef __KERNEL__\n    fd = portalmem_dmabuffer_create(size);\n#else\n#ifndef SIMULATION\n    {\n\t    struct PortalAlloc portalAlloc;\n\t    portalAlloc.len = size;\n\t    portalAlloc.cached = cached;\n\t    fd = ioctl(global_pa_fd, PA_MALLOC, &portalAlloc);\n    }\n#else\n    {\n      #define FNAME_BUF_SIZE 128\n      static int portalmem_number = 0;\n      char fname[FNAME_BUF_SIZE];\n      snprintf(fname, sizeof(fname), \"/tmp/portalmem-%d-%d.bin\", getpid(), portalmem_number++);\n      fd = open(fname, O_RDWR|O_CREAT, 0600);\n      if (fd < 0)\n\tfprintf(stderr, \"ERROR %s:%d fname=%s fd=%d\\n\", __FUNCTION__, __LINE__, fname, fd);\n      unlink(fname);\n      lseek(fd, size, SEEK_SET);\n      size_t bytesWritten = write(fd, (void*)fname, FNAME_BUF_SIZE);\n      if (bytesWritten != FNAME_BUF_SIZE)\n\tfprintf(stderr, \"ERROR %s:%d fname=%s fd=%d wrote %ld bytes\\n\", __FUNCTION__, __LINE__, fname, fd, (long)bytesWritten);\n      portalmem_sizes[fd] = size;\n    }\n#endif\n#endif\n    if(trace_portal)\n        PORTAL_PRINTF(\"alloc size=%ld fd=%d\\n\", (unsigned long)size, fd);\n    if (fd == -1) {\n        PORTAL_PRINTF(\"portalAllocCached: alloc failed size=%ld errno=%d\\n\", (unsigned long)size, errno);\n        exit(-1);\n    }\n    return fd;\n}\n\nvoid *portalMmap(int fd, size_t size)\n{\n#ifdef __KERNEL__\n    struct file *fmem = fget(fd);\n    void *retptr = dma_buf_vmap(fmem->private_data);\n    fput(fmem);\n    return retptr;\n#else      ///////////////////////// userspace version\n    void *mapped = mmap(0, size, PROT_READ|PROT_WRITE|PROT_EXEC, MAP_SHARED, fd, 0);\n    if (mapped == MAP_FAILED)\n      fprintf(stderr, \"ERROR: portalMmap fd=%d size=%ld mapped=%p\\n\", fd, (long)size, mapped);\n    return mapped;\n#endif\n}\nint portalMunmap(void *addr, size_t size)\n{\n#ifdef __KERNEL__\n    fprintf(stderr, \"UNIMPLEMENTED: portalMunmap addr=%p size=%d\\n\", addr, size);\n#else      ///////////////////////// userspace version\n    return munmap(addr, size);\n#endif\n}\n\nint portalCacheFlush(int fd, void *__p, long size, int flush)\n{\n#if defined(__arm__) || defined (__riscv__)\n#ifdef __KERNEL__\n    int i;\n    struct scatterlist *sg;\n    struct file *fmem = fget(fd);\n    struct sg_table *sgtable = ((struct pa_buffer *)((struct dma_buf *)fmem->private_data)->priv)->sg_table;\nprintk(\"[%s:%d] flush %d\\n\", __FUNCTION__, __LINE__, fd);\n    for_each_sg(sgtable->sgl, sg, sgtable->nents, i) {\n        unsigned int length = sg->length;\n        dma_addr_t start_addr = sg_phys(sg), end_addr = start_addr+length;\nprintk(\"[%s:%d] start %lx end %lx len %x\\n\", __FUNCTION__, __LINE__, (long)start_addr, (long)end_addr, length);\n        if(flush) outer_clean_range(start_addr, end_addr);\n        outer_inv_range(start_addr, end_addr);\n    }\n    fput(fmem);\n#else\n    int rc;\n    if (utility_portal){\n        PortalCacheRequest req;\n        req.fd = fd;\n        req.base = __p;\n        req.len = size;\n        if(flush)\n            rc = ioctl(utility_portal->fpga_fd, PORTAL_DCACHE_FLUSH_INVAL, &req);\n        else\n            rc = ioctl(utility_portal->fpga_fd, PORTAL_DCACHE_INVAL, &req);\n    }\n    else\n        rc = -1;\n    if (rc){\n        PORTAL_PRINTF(\"portal dcache flush failed rc=%d errno=%d:%s\\n\", rc, errno, strerror(errno));\n        return rc;\n    }\n#endif\n#elif defined(__i386__) || defined(__x86_64__)\n    {\n\tint i;\n\t// not sure any of this is necessary (mdk)\n\tfor(i = 0; i < size; i++){\n\t    char foo = *(((volatile char *)__p)+i);\n\t    asm volatile(\"clflush %0\" :: \"m\" (foo));\n\t}\n\tasm volatile(\"mfence\");\n    }\n#elif defined(__aarch64__)\n    // TBD\n#else\n#error(\"portalCacheFlush not defined for unspecified architecture\")\n#endif\n    if(trace_portal)\n        PORTAL_PRINTF(\"dcache flush\\n\");\n    return 0;\n}\n\n/*\n * Miscellaneous utility functions\n */\nint setClockFrequency(int clkNum, long requestedFrequency, long *actualFrequency)\n{\n    int status = -1;\n    initPortalHardware();\n#ifdef ZYNQ\n    PortalClockRequest request;\n    request.clknum = clkNum;\n    request.requested_rate = requestedFrequency;\n    if (utility_portal){\n        status = ioctl(utility_portal->fpga_fd, PORTAL_SET_FCLK_RATE, (long)&request);\n        if (status == 0 && actualFrequency)\n\t    *actualFrequency = request.actual_rate;\n        if (status < 0)\n\t    status = errno;\n    } else {\n      fprintf(stderr, \"[%s:%d] no utility portal\\n\", __FUNCTION__, __LINE__);\n      status = -1;\n    }\n#endif\n    return status;\n}\n"
  },
  {
    "path": "cpp/portal.h",
    "content": "/* Copyright (c) 2014 Quanta Research Cambridge, Inc\n *\n * Permission is hereby granted, free of charge, to any person obtaining a\n * copy of this software and associated documentation files (the \"Software\"),\n * to deal in the Software without restriction, including without limitation\n * the rights to use, copy, modify, merge, publish, distribute, sublicense,\n * and/or sell copies of the Software, and to permit persons to whom the\n * Software is furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n * DEALINGS IN THE SOFTWARE.\n */\n\n#ifndef __PORTAL_OFFSETS_H__\n#define __PORTAL_OFFSETS_H__\n#ifdef __KERNEL__\n#include <linux/types.h>  // has same typedefs as stdint.h\n#include <linux/module.h>\n#include <linux/kernel.h>\ntypedef struct task_struct *pthread_t;\nint pthread_create(pthread_t *thread, void *attr, void *(*start_routine) (void *), void *arg);\n#define PRIu64 \"llx\"\n#define PRIx64 \"llx\"\n#define PORTAL_PRINTF printk\n#else\n#include <stdint.h>\n#include <sys/types.h>\n#include <sys/socket.h> // for send()/recv()\n#include <string.h> // memcpy\n#include <stdio.h>   // printf()\n#include <stdlib.h>  // exit()\n#ifndef __STDC_FORMAT_MACROS\n#define __STDC_FORMAT_MACROS\n#endif\n#include <inttypes.h>\n#ifdef __cplusplus\n#include <semaphore.h>\n#include <unistd.h>\n#include <pthread.h> // pthread_mutex_t\n#include <poll.h>\n#endif\n\n#include \"ConnectalProjectConfig.h\"\n\nextern int simulator_dump_vcd;\nextern const char *simulator_vcd_name;\nextern int noprogram;\n\n#define PORTAL_PRINTF portal_printf\n#endif\n\n// Other constants\n#define MAX_TIMERS    50\n#define MAX_CLIENT_FD 10\n#ifdef __ATOMICC__\n#define DEFAULT_TILE  0\n#else\n#define DEFAULT_TILE  1\n#endif\n\n/*\n * Function vector for portal transport primitives used in generated C code\n */\nstruct PortalInternal;\ntypedef int  (*ITEMINIT)(struct PortalInternal *pint, void *param);\ntypedef unsigned int (*READWORD)(struct PortalInternal *pint, volatile unsigned int **addr);\ntypedef void (*WRITEWORD)(struct PortalInternal *pint, volatile unsigned int **addr, unsigned int v);\ntypedef void (*WRITEFDWORD)(struct PortalInternal *pint, volatile unsigned int **addr, unsigned int v);\ntypedef volatile unsigned int *(*MAPCHANNELIND)(struct PortalInternal *pint, unsigned int v);\ntypedef volatile unsigned int *(*MAPCHANNELREQ)(struct PortalInternal *pint, unsigned int v, unsigned int size);\ntypedef void (*SENDMSG)(struct PortalInternal *pint, volatile unsigned int *buffer, unsigned int hdr, int sendFd);\ntypedef int  (*RECVMSG)(struct PortalInternal *pint, volatile unsigned int *buffer, int len, int *recvfd);\ntypedef int  (*BUSYWAIT)(struct PortalInternal *pint, unsigned int v, const char *str);\ntypedef void (*ENABLEINT)(struct PortalInternal *pint, int val);\ntypedef int  (*EVENT)(struct PortalInternal *pint);\ntypedef int  (*NOTFULL)(struct PortalInternal *pint, unsigned int v);\ntypedef struct {\n    ITEMINIT    init;\n    READWORD    read;\n    WRITEWORD   write;\n    WRITEFDWORD writefd;\n    MAPCHANNELIND  mapchannelInd;\n    MAPCHANNELREQ  mapchannelReq;\n    SENDMSG     send;\n    RECVMSG     recv;\n    BUSYWAIT    busywait;\n    ENABLEINT   enableint;\n    EVENT       event;\n    NOTFULL     notFull;\n} PortalTransportFunctions;\n\n/*\n * Indication function vector for method invocations from HW->SW\n */\ntypedef int (*PORTAL_INDFUNC)(struct PortalInternal *p, unsigned int channel, int messageFd);\n\n/*\n * Disconnect indications from sockets\n */\ntypedef int (*PORTAL_DISCONNECT)(struct PortalInternal *pint);\ntypedef struct {\n    PORTAL_DISCONNECT disconnect;\n} PortalHandlerTemplate;\n\n/*\n * Main data structure used for managing Portal info at runtime\n */\ntypedef struct PortalInternal {\n    struct PortalPoller   *poller;\n    int                    fpga_fd;\n    uint32_t               fpga_number;\n    uint32_t               fpga_tile;\n    uint32_t               board_number;\n    volatile unsigned int *map_base;\n    void                  *parent;\n    PORTAL_INDFUNC         handler;\n    uint32_t               reqinfo;\n    int                    accept_finished;\n    PortalTransportFunctions    *transport;\n    PortalHandlerTemplate  *cb;\n    struct PortalInternal  *mux;\n    int                    muxid;\n    int                    busyType;\n#define BUSY_TIMEWAIT 0\n#define BUSY_SPIN     1\n#define BUSY_EXIT     2\n#define BUSY_ERROR    3\n    uint32_t               sharedMem;\n    int                    indication_index;\n    int                    request_index;\n    int                    client_fd_number;\n    int                    client_fd[MAX_CLIENT_FD];\n    int                    mux_ports_number;\n    struct PortalMuxHandler *mux_ports;\n    void                   *websock;\n    void                   *websock_context;\n    void                   *websock_wsi;\n    void                   *shared_dma;\n    struct PortalInternal  *shared_cfg;\n    int                    poller_register;\n    int                    json_arg_vector;\n} PortalInternal;\n\ntypedef struct PortalMuxHandler {\n    PortalInternal *pint;\n} PortalMuxHandler;\n\n/*\n * Struct definitions for optional parameter when initializing transport for portal\n */\ntypedef int (*SHARED_CONFIG_SETSGLID)(struct PortalInternal *, const uint32_t sglId);\ntypedef int (*SHARED_MMUINDICATION_POLL)(PortalInternal *p, uint32_t *arg_id);\ntypedef struct {\n    struct {\n        struct DmaManager *manager;\n        uint32_t reqport;\n        uint32_t reqinfo;\n        uint32_t indport;\n        uint32_t indinfo;\n        PORTAL_INDFUNC     handler;\n        void              *callbackFunctions;\n        SHARED_MMUINDICATION_POLL poll;\n    } dma;\n    uint32_t    size;\n    struct {\n        uint32_t port;\n        uint32_t reqinfo;\n        SHARED_CONFIG_SETSGLID setSglId;\n    } hardware;\n    struct {\n\tint serial_fd;\n    } serial;\n} PortalSharedParam; /* for ITEMINIT function */\n\ntypedef struct {\n    PortalInternal       *pint;\n    void                 *socketParam;\n} PortalMuxParam;\n\ntypedef struct {\n    const char *name;\n    int         offset;\n    int         itype;\n} ConnectalParamJsonInfo;\ntypedef struct {\n    const char *name;\n    ConnectalParamJsonInfo *param;\n} ConnectalMethodJsonInfo;\nenum {ITYPE_other,\n      ITYPE_int,\n      ITYPE_uint8_t,\n      ITYPE_uint16_t,\n      ITYPE_uint32_t,\n      ITYPE_uint64_t,\n      ITYPE_int8_t,\n      ITYPE_int16_t,\n      ITYPE_int32_t,\n      ITYPE_int64_t,\n      ITYPE_SpecialTypeForSendingFd,\n      ITYPE_ChannelType,\n      ITYPE_DmaDbgRec};\n\ntypedef int Bool;   /* for GeneratedTypes.h */\ntypedef uint32_t fixed32; /* for GeneratedTypes.h from protobuf */\n\n#define SHARED_DMA(REQPORTALNAME, INDPORTALNAME) {NULL, (REQPORTALNAME), MMURequest_reqinfo, (INDPORTALNAME), MMUIndication_reqinfo, MMUIndication_handleMessage, (void *)&manualMMU_Cb, manualWaitForResp}\n#define SHARED_HARDWARE(PORTALNAME) {(PORTALNAME), SharedMemoryPortalConfig_reqinfo, SharedMemoryPortalConfig_setSglId}\n#define Connectaloffsetof(TYPE, MEMBER) ((unsigned long)&((TYPE *)0)->MEMBER)\n\n/*\n * Address constants for portal memory mapped registers\n */\n/* Divide up 20 bits of physical address space into Tile:Portal:Method selectors */\n#define ADDRESS_TILE_SELECTOR   2\n#define ADDRESS_PORTAL_SELECTOR 6\n#define ADDRESS_METHOD_SELECTOR 7\n#define ADDRESS_METHOD_SIZE     5\n\n/* Offset of each /dev/fpgaxxx device in the address space */\n#define PORTAL_BASE_OFFSET   (1 << (ADDRESS_METHOD_SIZE+ADDRESS_METHOD_SELECTOR))\n#define TILE_BASE_OFFSET     (PORTAL_BASE_OFFSET << ADDRESS_PORTAL_SELECTOR)\n\n/* Offsets of mapped registers within an /dev/fpgaxxx device */\n#define PORTAL_FIFO(A)   ( (((A)+1) << ADDRESS_METHOD_SIZE) / sizeof(uint32_t) )\n\n// PortalCtrl offsets\n#define PORTAL_CTRL_INTERRUPT_STATUS 0\n#define PORTAL_CTRL_INTERRUPT_ENABLE 1\n#define PORTAL_CTRL_NUM_TILES        2\n#define PORTAL_CTRL_IND_QUEUE_STATUS 3\n#define PORTAL_CTRL_PORTAL_ID        4\n#define PORTAL_CTRL_NUM_PORTALS      5\n#define PORTAL_CTRL_COUNTER_MSB      6\n#define PORTAL_CTRL_COUNTER_LSB      7\n#define PORTAL_CTRL_SIZE            (8 * sizeof(uint32_t))\n\n/*\n * Constants used in shared memory transport for portals\n */\n#define SHARED_LIMIT  0\n#define SHARED_WRITE  1\n#define SHARED_READ   2\n#define SHARED_START  4\n// Since PortalCtrl fields appear as 'method 0', we need to be sure we have\n// enough memory allocated to 'read' them on simulation\n#define REQINFO_SIZE(A)  (((A) & 0xffff) > PORTAL_CTRL_SIZE ? ((A) & 0xffff) : PORTAL_CTRL_SIZE)\n#define REQINFO_COUNT(A) (((A) >> 16) & 0xffff)\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n// Initialize portal control structure. (called by constructor when creating a portal at runtime)\nvoid init_portal_internal(PortalInternal *pint, int id, int tile,\n    PORTAL_INDFUNC handler, void *cb, PortalTransportFunctions *transport,\n    void *param, void *parent, uint32_t reqinfo);\nint portal_disconnect(struct PortalInternal *p);\n// Shared memory functions\nvoid initPortalMemory(void);\nint portalAlloc(size_t size, int cached);\nvoid *portalMmap(int fd, size_t size);\nint portalMunmap(void *addr, size_t size);\nint portalCacheFlush(int fd, void *__p, long size, int flush);\n\n// Timer functions\nuint64_t portalCycleCount(void);\nvoid portalTimerStart(unsigned int i);\nuint64_t portalTimerLap(unsigned int i);\nvoid portalTimerInit(void);\nuint64_t portalTimerCatch(unsigned int i);\nvoid portalTimerPrint(int loops);\n\n// Functions shared across several portal transports\nvoid enableint_portal_null(struct PortalInternal *pint, int val);\nint busy_portal_null(struct PortalInternal *pint, unsigned int v, const char *str);\nint notfull_null(PortalInternal *pint, unsigned int v);\nvoid send_portal_null(struct PortalInternal *pint, volatile unsigned int *buffer, unsigned int hdr, int sendFd);\nint recv_portal_null(struct PortalInternal *pint, volatile unsigned int *buffer, int len, int *recvfd);\nint event_null(struct PortalInternal *pint);\nvolatile unsigned int *mapchannel_req_generic(struct PortalInternal *pint, unsigned int v, unsigned int size);\nunsigned int read_portal_memory(PortalInternal *pint, volatile unsigned int **addr);\nvoid write_portal_memory(PortalInternal *pint, volatile unsigned int **addr, unsigned int v);\nvoid write_fd_portal_memory(PortalInternal *pint, volatile unsigned int **addr, unsigned int v);\nvoid enableint_hardware(struct PortalInternal *pint, int val);\nint busy_hardware(struct PortalInternal *pint, unsigned int v, const char *str);\nint notfull_hardware(PortalInternal *pint, unsigned int v);\nint event_hardware(struct PortalInternal *pint);\nint event_xsim(struct PortalInternal *pint);\nint portal_event(struct PortalInternal *pint);\nvolatile unsigned int *mapchannel_hardware(struct PortalInternal *pint, unsigned int v);\nvolatile unsigned int *mapchannel_socket(struct PortalInternal *pint, unsigned int v);\nint portal_mux_handler(struct PortalInternal *p, unsigned int channel, int messageFd);\nint portal_serialmux_handler(struct PortalInternal *p, unsigned int channel, int messageFd);\n\n// Json encode/decode functions called from generated code\nvoid connectalJsonEncode(char *json, void *data, ConnectalMethodJsonInfo *info, int json_arg_vector);\nvoid connectalJsonEncodeAndSend(PortalInternal *pint, void *data, ConnectalMethodJsonInfo *info);\nvoid connectalJsonSend(PortalInternal *pint, const char *jsonp, int methodNumber);\nconst char *connectalJsonReceive(PortalInternal *pint);\n\n// Primitive used to send/recv data across a socket.\nvoid portalSendFd(int fd, void *data, int len, int sendFd);\nint portalRecvFd(int fd, void *data, int len, int *recvFd);\nunsigned int bsim_poll_interrupt(void);\nunsigned int read_pareff32(uint32_t pref, uint32_t offset);\nunsigned int read_pareff64(uint64_t pref, uint64_t offset);\n\nint setClockFrequency(int clkNum, long requestedFrequency, long *actualFrequency);\nvoid initPortalHardware(void);\nvoid addFdToPoller(struct PortalPoller *poller, int fd);\n#ifndef __KERNEL__\nint portal_printf(const char *format, ...); // outputs to stderr\n#endif\n\nextern int global_sockfd, global_pa_fd;\nextern PortalInternal *utility_portal;\n\n#define CONNECTAL_PRINTF_PORT       0x7fff\nextern void (*connectalPrintfHandler)(struct PortalInternal *p, unsigned int header);\n\n// Portal transport variants\nextern PortalTransportFunctions transportBsim, // Transport for bsim\n  transportHardware,    // Memory-mapped register transport for hardware\n  transportSocketInit,  // Linux socket transport (Unix sockets and TCP); Initiator side\n                   // (the 'connect()' call is on Initiator side; Responder does 'listen()'\n  transportSocketResp,  // Linux socket transport (Unix sockets and TCP); Responder side\n  transportSerial,      // Serial port transport\n  transportSerialMux,   // Serial port mux\n  transportShared,      // Shared memory transport\n  transportMux,         // Multiplex transport (to use 1 transport for all methods or multiple portals)\n  transportTrace,       // Trace transport tee\n  transportXsim,        // Xilinx xsim transport\n  transportWebSocketInit, // Websocket transport; Initiator side\n  transportWebSocketResp, // Websocket transport; Responder side\n  transportPortal;\n#ifdef __cplusplus\n}\n#endif\n\n/*\n * C++ class definitions used in application software\n */\n#ifdef __cplusplus\nclass Portal;\nclass PortalPoller {\nprivate:\n    Portal *portal_wrappers[32];\n    struct pollfd portal_fds[32]; // 16 portals + pipefd[0] + extra\n    pthread_mutex_t mutex;\n    int pipefd[2];\n    int startThread;\n    int numWrappers;\n    int numFds;\n    int inPoll;\npublic:\n    PortalPoller(int autostart=1);\n    int registerInstance(Portal *portal);\n    int unregisterInstance(Portal *portal);\n    void *init(void);\n    void *pollFn(int timeout);\n    void *event(void);\n    void end(void);\n    void start();\n    void stop();\n    void addFd(int fd);\n    int timeout;\n    int stopping;\n    sem_t sem_startup;\n    void* threadFn(void* __x);\n};\n\nextern PortalPoller *defaultPoller;\nclass Portal {\n    void initPortal() {\n        if (pint.handler || pint.poller_register) {\n            if (pint.poller == 0)\n                pint.poller = defaultPoller;\n            pint.poller->registerInstance(this);\n        }\n    }\npublic:\n    Portal(int id, int tile, uint32_t reqinfo, PORTAL_INDFUNC handler, void *cb, void *parent, PortalPoller *poller = 0) {\n        init_portal_internal(&pint, id, tile, handler, cb, NULL, NULL, parent, reqinfo); \n        pint.poller = poller;\n        initPortal();\n    };\n    Portal(int id, int tile, uint32_t reqinfo, PORTAL_INDFUNC handler, void *cb,\n          PortalTransportFunctions *transport, void *param, void *parent, PortalPoller *poller = 0) {\n        init_portal_internal(&pint, id, tile, handler, cb, transport, param, parent, reqinfo); \n        pint.poller = poller;\n        initPortal();\n    };\n    ~Portal() {\n        if (pint.handler)\n            pint.poller->unregisterInstance(this);\n        if (pint.fpga_fd > 0) {\n            ::close(pint.fpga_fd);\n            pint.fpga_fd = -1;\n        }    \n    };\n    PortalInternal pint;\n};\n\nextern uint64_t poll_enter_time, poll_return_time; // for performance measurement\nextern int mmu_error_limit, mem_error_limit;       // portalMemory\nextern const char *dmaErrors[];                    // portalMemory\n#endif // __cplusplus\n\n#endif /* __PORTAL_OFFSETS_H__ */\n"
  },
  {
    "path": "cpp/portalJson.c",
    "content": "// Copyright (c) 2014 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\n#include <string.h>\n#include \"portal.h\"\n\n// extern \"C\" because some of the makefiles use g++ to compile this file\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\nstatic int trace_json;// = 1;\nvoid connectalJsonEncode(char *datap, void *binarydata, ConnectalMethodJsonInfo *info, int json_arg_vector)\n{\n    ConnectalParamJsonInfo *iparam = info->param;\n    char *data = (char *)datap;\n    if (!json_arg_vector)\n\tdata += sprintf(data, \"{\\\"name\\\":\\\"%s\\\"\", info->name);\n    else\n\tdata += sprintf(data, \"[\\\"%s\\\"\", info->name);\n    while(iparam->name) {\n        uint8_t  tmp8;\n        uint16_t tmp16;\n        uint32_t tmp32;\n        uint64_t tmp64;\n\tint8_t  stmp8;\n\tint16_t stmp16;\n\tint32_t stmp32;\n\tint64_t stmp64;\n        int      tmpint;\n\tif (!json_arg_vector)\n\t    data += sprintf(data, \",\\\"%s\\\":\", iparam->name);\n\telse\n\t    data += sprintf(data, \", \");\n        switch(iparam->itype) {\n\tcase ITYPE_int8_t:\n            stmp8 = *(int8_t *)((unsigned long)binarydata + iparam->offset);\n            data += sprintf(data, \"%d\", stmp8);\n            break;\n\tcase ITYPE_int16_t:\n            stmp16 = *(int16_t *)((unsigned long)binarydata + iparam->offset);\n            data += sprintf(data, \"%d\", stmp16);\n            break;\n\tcase ITYPE_int:\n\tcase ITYPE_int32_t:\n            stmp32 = *(int32_t *)((unsigned long)binarydata + iparam->offset);\n            data += sprintf(data, \"%d\", stmp32);\n            break;\n\tcase ITYPE_int64_t:\n            stmp64 = *(int64_t *)((unsigned long)binarydata + iparam->offset);\n            data += sprintf(data, \"%lld\", (long long)stmp64);\n            break;\n        case ITYPE_uint8_t:\n            tmp8 = *(uint8_t *)((unsigned long)binarydata + iparam->offset);\n            data += sprintf(data, \"%d\", tmp8);\n            break;\n        case ITYPE_uint16_t:\n            tmp16 = *(uint16_t *)((unsigned long)binarydata + iparam->offset);\n            data += sprintf(data, \"%d\", tmp16);\n            break;\n        case ITYPE_uint32_t:\n            tmp32 = *(uint32_t *)((unsigned long)binarydata + iparam->offset);\n            data += sprintf(data, \"%d\", tmp32);\n            break;\n        case ITYPE_uint64_t:\n            tmp64 = *(uint64_t *)((unsigned long)binarydata + iparam->offset);\n            data += sprintf(data, \"%lld\", (unsigned long long)tmp64);\n            break;\n        case ITYPE_SpecialTypeForSendingFd:\n            tmpint = *(int *)((unsigned long)binarydata + iparam->offset);\n            data += sprintf(data, \"%d\", tmpint);\n            break;\n        default:\n            fprintf(stderr, \"%x type %d\\n\", *(uint32_t *)((unsigned long)binarydata + iparam->offset), iparam->itype);\n        }\n        iparam++;\n    }\n    if (!json_arg_vector)\n\tdata += sprintf(data, \"}\");\n    else\n\tdata += sprintf(data, \"]\");\n    if (trace_json)\n        fprintf(stderr, \"[%s] num %d message '%s'\\n\", __FUNCTION__, iparam->offset, (char *)datap);\n    int slength = strlen(datap);\n    int rounded_size = (slength + sizeof(uint32_t) - 1) / sizeof(uint32_t);\n    while (slength++ < (int)(rounded_size*sizeof(uint32_t)))\n        *data++ = ' ';\n    *data++ = 0;\n}\n\nvoid connectalJsonEncodeAndSend(PortalInternal *pint, void *binarydata, ConnectalMethodJsonInfo *info)\n{\n    ConnectalParamJsonInfo *iparam = info->param;\n    char *jsonp = (char *)pint->transport->mapchannelInd(pint, 0);\n    if (pint->json_arg_vector)\n\tjsonp = (char *)pint->parent;\n    connectalJsonEncode(jsonp, binarydata, info, pint->json_arg_vector);\n    if (!pint->json_arg_vector) {\n\tint rounded_size = strlen(jsonp);\n\tpint->transport->send(pint, (volatile unsigned int*)jsonp, (iparam->offset << 16) | (1 + rounded_size), -1);\n    }\n}\n\nvoid connectalJsonSend(PortalInternal *pint, const char *jsonp, int methodNumber)\n{\n    //fprintf(stderr, \"%s:%d jsonp=%s\\n\", __FUNCTION__, __LINE__, jsonp);\n    if (pint->json_arg_vector) {\n\t//FIXME strncpy\n\tstrcpy((char *)pint->parent, jsonp);\n    }\n    if (!pint->json_arg_vector) {\n\tint rounded_size = strlen(jsonp);\n\tpint->transport->send(pint, (volatile unsigned int*)jsonp, (methodNumber << 16) | (1 + rounded_size), -1);\n    }\n}\n\nconst char *connectalJsonReceive(PortalInternal *pint)\n{\n    uint32_t header = *(uint32_t *)pint->map_base;\n    char *datap = (char *)pint->transport->mapchannelInd(pint, 0);\n    int tmpfd;\n    int len = (header & 0xffff)-1;\n    int rc = pint->transport->recv(pint, (volatile unsigned int*)datap, len, &tmpfd);\n    if (rc != len)\n      fprintf(stderr, \"[%s:%d] short read %d\\n\", __FUNCTION__, __LINE__, rc);\n\n    datap[len*sizeof(uint32_t)] = 0;\n    if (trace_json)\n        fprintf(stderr, \"[%s] message '%s'\\n\", __FUNCTION__, (char *)datap);\n    return datap;\n}\n\nint connectalJsonDecode(PortalInternal *pint, int _unused_channel, void *binarydata, ConnectalMethodJsonInfo *infoa)\n{\n    int channel = 0;\n    ConnectalMethodJsonInfo *info = NULL;\n    //&infoa[channel];\n    uint32_t header = *(uint32_t *)pint->map_base;\n    char *datap = (char *)pint->transport->mapchannelInd(pint, 0);\n    char ch, *attr = NULL, *val = NULL;\n    int tmpfd;\n    int len = (header & 0xffff)-1;\n    int rc = pint->transport->recv(pint, (volatile unsigned int*)datap, len, &tmpfd);\n    if (rc != len)\n      fprintf(stderr, \"[%s:%d] short read %d\\n\", __FUNCTION__, __LINE__, rc);\n    \n    datap[len*sizeof(uint32_t)] = 0;\n    if (trace_json)\n        fprintf(stderr, \"[%s] message '%s'\\n\", __FUNCTION__, (char *)datap);\n\n    while ((ch = *datap++)) {\n        if (ch == '\\\"') {\n            if (!attr)\n                attr = datap;\n            else if (!val)\n                *(datap - 1) = 0;\n        }\n        else if (ch == ':')\n            val = datap;\n        else if ((ch == ',' || ch == '}') && attr && val) {\n            *(datap - 1) = 0;\n            if (!strcmp(attr, \"name\")) {\n                info = infoa;\n                val++; /* skip leading '\"' */\n                val[strlen(val) - 1] = 0; /* delete trailing '\"' */\n                while (info->name && strcmp(info->name, val)){\n                    info++;\n\t\t    channel++;\n\t\t}\n                if (!info->name) {\n                    fprintf(stderr, \"[%s:%d] unknown method name '%s'\\n\", __FUNCTION__, __LINE__, val);\n                    exit(1);\n                }\n            }\n            ConnectalParamJsonInfo *iparam = info->param;\n            while (iparam->name) {\n                if (!strcmp(iparam->name, attr)) {\n                    char *endptr;\n                    if (trace_json)\n                        fprintf(stderr, \"[%s] attr '%s' val '%s'\\n\", __FUNCTION__, attr, val);\n                    uint64_t tmp64 = strtol(val, &endptr, 0);\n                    if (endptr != &val[strlen(val)])\n                        fprintf(stderr, \"[%s:%d] strtol didn't use all characters %p != %p\\n\", __FUNCTION__, __LINE__, endptr, val+strlen(val));\n                    switch(iparam->itype) {\n                    case ITYPE_int16_t:\n                        *(int16_t *)((unsigned long)binarydata + iparam->offset) = tmp64;\n                        break;\n                    case ITYPE_uint16_t:\n                        *(uint16_t *)((unsigned long)binarydata + iparam->offset) = tmp64;\n                        break;\n                    case ITYPE_uint32_t:\n                        *(uint32_t *)((unsigned long)binarydata + iparam->offset) = tmp64;\n                        break;\n                    case ITYPE_uint64_t:\n                        *(uint64_t *)((unsigned long)binarydata + iparam->offset) = tmp64;\n                        break;\n                    case ITYPE_SpecialTypeForSendingFd:\n                        *(int *)((unsigned long)binarydata + iparam->offset) = tmp64;\n                        break;\n                    default:\n                        fprintf(stderr, \"%x type %d\\n\", *(uint32_t *)((unsigned long)binarydata + iparam->offset), iparam->itype);\n                    }\n                    break;\n                }\n                iparam++;\n            }\n            attr = NULL;\n            val = NULL;\n        }\n    }\n    return channel;\n}\n\n#ifdef __cplusplus\n}\n#endif\n"
  },
  {
    "path": "cpp/portalKernel.h",
    "content": "// Copyright (c) 2014 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\nvoid send_portal_null(struct PortalInternal *pint, volatile unsigned int *buffer, unsigned int hdr, int sendFd)\n{\n}\nint recv_portal_null(struct PortalInternal *pint, volatile unsigned int *buffer, int len, int *recvfd)\n{\n    return 0;\n}\nvolatile unsigned int *mapchannel_portal_kernel_ind(struct PortalInternal *pint, unsigned int v)\n{\n    return &pint->map_base[PORTAL_FIFO(v)];\n}\nvolatile unsigned int *mapchannel_portal_kernel_req(struct PortalInternal *pint, unsigned int v, unsigned int size)\n{\n    return pint->transport->mapchannelInd(pint, v);\n}\nint notfull_kernel(PortalInternal *pint, unsigned int v)\n{\n    volatile unsigned int *tempp = pint->transport->mapchannelInd(pint, v) + 1;\n    return pint->transport->read(pint, &tempp);\n}\nint busy_portal_kernel(struct PortalInternal *pint, unsigned int v, const char *str)\n{\n    int count = 50;\n    while (!pint->transport->notFull(pint, v) && count-- > 0)\n        ; /* busy wait a bit on 'fifo not full' */\n    if (count <= 0){\n        PORTAL_PRINTF(\"putFailed: %s\\n\", str);\n        return 1;\n    }\n    return 0;\n}\nvoid enableint_portal_kernel(struct PortalInternal *pint, int val)\n{\n    volatile unsigned int *enp = &(pint->map_base[PORTAL_CTRL_INTERRUPT_ENABLE]);\n    pint->transport->write(pint, &enp, val);\n}\nint event_portal_kernel(struct PortalInternal *pint)\n{\n    // handle all messasges from this portal instance\n    //event_hardware(pint);\n    return -1;\n}\n\nstatic int init_portal_kernel(struct PortalInternal *pint, void *param)\n{\n    //pint->map_base = (volatile unsigned int*)(tboard->bar2io + pint->fpga_number * PORTAL_BASE_OFFSET);\n    return 0;\n}\nstatic unsigned int read_portal_kernel(PortalInternal *pint, volatile unsigned int **addr)\n{\n    return **addr;\n}\nstatic void write_portal_kernel(PortalInternal *pint, volatile unsigned int **addr, unsigned int v)\n{\n    **addr = v;\n}\nstatic void write_fd_portal_kernel(PortalInternal *pint, volatile unsigned int **addr, unsigned int v)\n{\n    **addr = v;\n}\n\nPortalTransportFunctions kernelfunc = {\n    init_portal_kernel, read_portal_kernel, write_portal_kernel, write_fd_portal_kernel, mapchannel_portal_kernel_ind, mapchannel_portal_kernel_req,\n    send_portal_null, recv_portal_null, busy_portal_kernel, enableint_portal_kernel, event_portal_kernel, notfull_kernel};\n"
  },
  {
    "path": "cpp/portalPrintf.c",
    "content": "// Copyright (c) 2013-2015 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\n#include <stdio.h>\n#include <stdarg.h>\n\n#ifndef __KERNEL__\n#ifdef  __cplusplus\nextern \"C\"\n#endif\nint portal_printf(const char *format, ...)\n{\n    va_list ap;\n    va_start(ap, format);\n    return vfprintf(stderr, format, ap);\n}\n#endif\n"
  },
  {
    "path": "cpp/portalPython.cpp",
    "content": "/* Copyright (c) 2014 Quanta Research Cambridge, Inc\n * Copyright (c) 2016 ConnectalProject\n *\n * Permission is hereby granted, free of charge, to any person obtaining a\n * copy of this software and associated documentation files (the \"Software\"),\n * to deal in the Software without restriction, including without limitation\n * the rights to use, copy, modify, merge, publish, distribute, sublicense,\n * and/or sell copies of the Software, and to permit persons to whom the\n * Software is furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n * DEALINGS IN THE SOFTWARE.\n */\n\n#include <stdio.h>\n#include \"GeneratedTypes.h\"\n#include <python2.7/Python.h>\n\nstatic int tracePython;// = 1;\nstatic PortalInternal pythonTransport;\n\n#define STUB \\\n{ \\\n    fprintf(stderr, \"[%s:%d]\\n\", __FUNCTION__, __LINE__);\t\\\n    exit(-1); \\\n}\nstatic volatile unsigned int *pythonTransportMAPCHANNELIND(struct PortalInternal *pint, unsigned int v)\n{\n    return &pythonTransport.map_base[0];\n}\nstatic volatile unsigned int *pythonTransportMAPCHANNELREQ(struct PortalInternal *pint, unsigned int v, unsigned int size)\n{\n    return &pythonTransport.map_base[0];\n}\nstatic void pythonTransportSENDMSG(struct PortalInternal *pint, volatile unsigned int *buffer, unsigned int hdr, int sendFd)\n{\n    if (tracePython)\n\tfprintf(stderr, \"%s:%d %s\\n\", __FUNCTION__, __LINE__, (const char *)buffer);\n}\nstatic int pythonTransportTRANSPORTINIT(struct PortalInternal *pint, void *param) STUB\nstatic unsigned int pythonTransportREADWORD(struct PortalInternal *pint, volatile unsigned int **addr) STUB\nstatic void pythonTransportWRITEWORD(struct PortalInternal *pint, volatile unsigned int **addr, unsigned int v) STUB\nstatic void pythonTransportWRITEFDWORD(struct PortalInternal *pint, volatile unsigned int **addr, unsigned int v) STUB\nstatic int pythonTransportRECVMSG(struct PortalInternal *pint, volatile unsigned int *buffer, int len, int *recvfd) STUB\nstatic int pythonTransportBUSYWAIT(struct PortalInternal *pint, unsigned int v, const char *str) STUB\nstatic void pythonTransportENABLEINT(struct PortalInternal *pint, int val) STUB\nstatic int pythonTransportEVENT(struct PortalInternal *pint) STUB\nstatic int pythonTransportNOTFULL(struct PortalInternal *pint, unsigned int v) STUB\nPortalTransportFunctions callbackTransport = {\n    pythonTransportTRANSPORTINIT, pythonTransportREADWORD, pythonTransportWRITEWORD, pythonTransportWRITEFDWORD,\n    pythonTransportMAPCHANNELIND, pythonTransportMAPCHANNELREQ, pythonTransportSENDMSG, pythonTransportRECVMSG,\n    pythonTransportBUSYWAIT, pythonTransportENABLEINT, pythonTransportEVENT, pythonTransportNOTFULL};\n\nextern \"C\" {\n\ntypedef int (*HandleMessage)(struct PortalInternal *pint, unsigned int channel, int messageFd);\n\nstruct PortalPython {\n    struct PortalInternal pint;\n    HandleMessage handleMessage;\n    PyObject *callbackFunction;\n};\n\nstatic int handleIndicationMessage(struct PortalInternal *pint, unsigned int channel, int messageFd)\n{\n    struct PortalPython *ppython = (struct PortalPython *)pint;\n    HandleMessage handleMessage = ppython->handleMessage;\n    pint->json_arg_vector = 1;\n    int value = handleMessage(pint, channel, messageFd);\n    PyGILState_STATE gstate = PyGILState_Ensure();\n    const char *jsonp = (const char *)pint->parent;\n    if (tracePython) fprintf(stderr, \"handleIndicationMessage: json=%s\\n\", jsonp);\n    if (ppython->callbackFunction) {\n\tPyEval_CallMethod(ppython->callbackFunction, \"callback\", \"(s)\", jsonp, NULL);\n    } else {\n\tfprintf(stderr, \"%s:%d no callback for portal\\n\", __FUNCTION__, __LINE__);\n    }\n    PyGILState_Release(gstate);\n    return value;\n}\n\nvoid set_callback(struct PortalPython *ppython, PyObject *param)\n{\n    Py_INCREF(param);\n    ppython->callbackFunction = param;\n    pythonTransport.transport = &callbackTransport;\n    pythonTransport.map_base = (volatile unsigned int *)malloc(1000);\n}\n\nvoid *newRequestPortal(int ifcname, int reqinfo)\n{\n    struct PortalInternal *pint = (struct PortalInternal *)calloc(1, sizeof(struct PortalInternal));\n    void *parent = NULL;;\n    if (tracePython) fprintf(stderr, \"%s:%d ifcname=%x reqinfo=%08x pint=%p\\n\", __FUNCTION__, __LINE__, ifcname, reqinfo, pint);\n    init_portal_internal(pint, ifcname, DEFAULT_TILE, NULL, NULL, NULL, NULL, parent, reqinfo);\n    return pint;\n}\n\nvoid *newIndicationPortal(int ifcname, int reqinfo, HandleMessage handleMessage, void *proxyreq)\n{\n    void *parent = malloc(4096);\n    struct PortalPython *ppython = (struct PortalPython *)calloc(1, sizeof(struct PortalPython));\n    ppython->handleMessage = handleMessage;\n    if (tracePython)\n    fprintf(stderr, \"%s:%d ifcname=%x reqinfo=%08x handleMessage=%p proxyreq=%p pint=%p\\n\",\n\t    __FUNCTION__, __LINE__, ifcname, reqinfo, handleMessage, proxyreq, ppython);\n    init_portal_internal(&ppython->pint, ifcname, DEFAULT_TILE,\n\t\t\t (PORTAL_INDFUNC) handleIndicationMessage, proxyreq, NULL, NULL, parent, reqinfo);\n    // encode message as vector [\"methodname\", arg0, arg1, ...]\n    pythonTransport.json_arg_vector = 1;\n    return ppython;\n}\n} // extern \"C\"\n"
  },
  {
    "path": "cpp/runpython.cpp",
    "content": "#include <stdio.h>\n#include <stdlib.h>\n#include <unistd.h>\n#include <string.h>\n#include <sys/stat.h>\n#include <sys/types.h>\n#include <sys/utsname.h>\n#include <libgen.h>\n\n#include <ConnectalProjectConfig.h>\n\n#define STR_VALUE_(arg)      #arg\n#define STR_VALUE(arg)      STR_VALUE_(arg)\n\nint main(int argc, char * const *argv)\n{\n    const char *exename = \"../test.py\";\n    char library_path[4096];\n    struct utsname utsname;\n    struct stat statbuf;\n    const char *libdir = \"./bin\";\n    int statok = 0;\n\n    fprintf(stderr, \"runpython args: \");\n    for (int i = 0; i < argc; i++)\n      fprintf(stderr, \" %s\", argv[i]);\n    fprintf(stderr, \"\\n\");\n    if (argc > 1) {\n\texename = argv[1];\n\t// What? dirname modifies its argument?\n\tlibdir = dirname(strdup(argv[1]));\n    }\n    statok = stat(\"/usr/bin/python\", &statbuf);\n    uname(&utsname);\n\n    if ((statok != 0)\n\t&& strcmp(utsname.machine, \"armv7l\") == 0) {\n\tstrncpy(library_path, \"./bin:../lib:.\", sizeof(library_path));\n\texename = \"../bin/python\";\n    } else {\n\tstrncpy(library_path, libdir, sizeof(library_path));\n        strncat(library_path, \":./bin\", sizeof(library_path)-strlen(\":./bin\")-1);\n    }\n    \n    if (getenv(\"LD_LIBRARY_PATH\") != 0) {\n        strncat(library_path, \":\", sizeof(library_path)-strlen(library_path)-1);\n        strncat(library_path, getenv(\"LD_LIBRARY_PATH\"), sizeof(library_path)-strlen(library_path)-1);\n    }\n    fprintf(stderr, \"LD_LIBRARY_PATH: %s\\n\", library_path);\n    setenv(\"LD_LIBRARY_PATH\", library_path, 1);\n#ifdef PYTHONPATH\n    fprintf(stderr, \"PYTHONPATH=%s\\n\", PYTHONPATH);\n    fprintf(stderr, \"CONNECTALDIR=%s\\n\", CONNECTALDIR);\n    static char pythonpath[1024];\n    snprintf(pythonpath, sizeof(pythonpath), \"%s:%s/scripts\", PYTHONPATH, CONNECTALDIR);\n    fprintf(stderr, \"using PYTHONPATH=%s\\n\", pythonpath);\n    setenv(\"PYTHONPATH\", pythonpath, 1);\n#endif\n    fprintf(stderr, \"%s: execv(%s)\\n\", argv[0], exename);\n    return execv(exename, argv);\n}\n"
  },
  {
    "path": "cpp/sock_utils.c",
    "content": "\n// Copyright (c) 2013-2014 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n#include \"portal.h\"\n#include \"sock_utils.h\"\n#include <stdio.h>\n#include <stdlib.h>\n#include <errno.h>\n#include <string.h>\n#include <unistd.h>\n#include <sys/types.h>\n#include <sys/socket.h>\n#include <sys/un.h>\n#include <semaphore.h>\n#include <pthread.h>\n#include <assert.h>\n#include <netdb.h>\n#include <arpa/inet.h>\n\nstatic int trace_socket ;//= 1;\n\nconst char *bluesimSocketName()\n{\n  char *name = getenv(\"BLUESIM_SOCKET_NAME\");\n  return name ? name : \"socket_for_bluesim\";\n}\n\nint init_listening(const char *arg_name, PortalSocketParam *param)\n{\n    int listening_socket;\n    struct sockaddr_un sa = {0};\n    sa.sun_family = AF_UNIX;\n    strcpy(sa.sun_path, arg_name);\n    struct addrinfo addrinfo = { 0, AF_UNIX, SOCK_STREAM, 0};\n    addrinfo.ai_addrlen =\n#ifdef __APPLE__\n        SUN_LEN(&sa);\n#else\n        sizeof(sa.sun_family) + strlen(sa.sun_path);\n#endif\n    addrinfo.ai_addr = (struct sockaddr *)&sa;\n    struct addrinfo *addr = &addrinfo;\n\n    if (trace_socket)\n        fprintf(stderr, \"[%s:%d] listenName %s\\n\", __FUNCTION__, __LINE__, arg_name);\n    if (param && param->addr) {\n        fprintf(stderr, \"[%s:%d] TCP\\n\", __FUNCTION__, __LINE__);\n        addr = param->addr;\n        // added these for android\n        addr->ai_socktype = SOCK_STREAM;\n        addr->ai_protocol = 0;\n    }\n    else\n        unlink(sa.sun_path);\n    listening_socket = socket(addr->ai_family, addr->ai_socktype, addr->ai_protocol);\n\n    int tmp = 1;\n    setsockopt(listening_socket, SOL_SOCKET, SO_REUSEADDR, &tmp, sizeof(tmp));\n    if (listening_socket == -1 || bind(listening_socket, addr->ai_addr, addr->ai_addrlen) == -1) {\n        fprintf(stderr, \"%s[%d]: bind error %s\\n\",__FUNCTION__, listening_socket, strerror(errno));\n        exit(1);\n    }\n\n    if (listen(listening_socket, 5) == -1) {\n        fprintf(stderr, \"%s[%d]: listen error %s\\n\",__FUNCTION__, listening_socket, strerror(errno));\n        exit(1);\n    }\n    if (trace_socket)\n        fprintf(stderr, \"%s: listen(%d)\\n\", __FUNCTION__, listening_socket);\n    return listening_socket;\n}\n\nint accept_socket(int arg_listening)\n{\n    int sockfd = accept(arg_listening, NULL, NULL);\n    if (sockfd == -1) {\n        if (errno == EAGAIN)\n            return -1;\n        fprintf(stderr, \"%s[%d]: accept error %s\\n\",__FUNCTION__, arg_listening, strerror(errno));\n        exit(1);\n    }\n    if (trace_socket)\n        fprintf(stderr, \"%s: accept(%d) = %d\\n\", __FUNCTION__, arg_listening, sockfd);\n    return sockfd;\n}\n\nint init_connecting(const char *arg_name, PortalSocketParam *param)\n{\n    int connect_attempts = 0;\n    int sockfd;\n    struct sockaddr_un sa = {0};\n    struct addrinfo addrinfo = { 0, AF_UNIX, SOCK_STREAM, 0};\n    struct addrinfo *addr = &addrinfo;\n\n    sa.sun_family = AF_UNIX;\n    strcpy(sa.sun_path, arg_name);\n    addrinfo.ai_addrlen = \n#ifdef __APPLE__\n        SUN_LEN(&sa);\n#else\n        sizeof(sa.sun_family) + strlen(sa.sun_path);\n#endif\n    addrinfo.ai_addr = (struct sockaddr *)&sa;\n\n    if (param && param->addr) {\n\tif (trace_socket) fprintf(stderr, \"[%s:%d] TCP\\n\", __FUNCTION__, __LINE__);\n        addr = param->addr;\n    }\n    if ((sockfd = socket(addr->ai_family, addr->ai_socktype, addr->ai_protocol)) == -1) {\n        PORTAL_PRINTF( \"%s[%d]: socket error %s\\n\",__FUNCTION__, sockfd, strerror(errno));\n\treturn -1;\n    }\n    if (trace_socket)\n        PORTAL_PRINTF( \"%s (%s) trying to connect...\\n\",__FUNCTION__, arg_name);\n\n    while (connect(sockfd, addr->ai_addr, addr->ai_addrlen) == -1) {\n        if(connect_attempts++ > 16){\n            PORTAL_PRINTF( \"%s (%s) connect error %s\\n\",__FUNCTION__, arg_name, strerror(errno));\n            return -1;\n        }\n        if (trace_socket)\n            PORTAL_PRINTF( \"%s (%s) retrying connection\\n\",__FUNCTION__, arg_name);\n        sleep(1);\n    }\n    if (trace_socket) PORTAL_PRINTF( \"%s (%s) connected.  Attempts %d\\n\",__FUNCTION__, arg_name, connect_attempts);\n    return sockfd;\n}\n\n// Taken from: UNIX Network Programming, Richard Stevens\n// http://www.kohala.com/start/unpv12e.html\nssize_t sock_fd_write(int sockfd, void *ptr, size_t nbytes, int sendfd)\n{\n    struct msghdr    msg;\n    struct iovec     iov[1];\n    union {\n        struct cmsghdr cm;\n        char           control[CMSG_SPACE(sizeof(int))];\n    } control_un;\n    struct cmsghdr   *cmptr;\n\n    msg.msg_control = control_un.control;\n    msg.msg_controllen = 0;\n    if (sendfd >= 0) {\n        memset(&control_un, 0, sizeof(control_un));\n        msg.msg_controllen = sizeof(control_un.control);\n        cmptr = CMSG_FIRSTHDR(&msg);\n        cmptr->cmsg_len = CMSG_LEN(sizeof(int));\n        cmptr->cmsg_level = SOL_SOCKET;\n        cmptr->cmsg_type = SCM_RIGHTS;\n        int *foo = (int *)CMSG_DATA(cmptr);\n        *foo = sendfd;\n    }\n    msg.msg_name = NULL;\n    msg.msg_namelen = 0;\n    iov[0].iov_base = ptr;\n    iov[0].iov_len = nbytes;\n    msg.msg_iov = iov;\n    msg.msg_iovlen = 1;\n#ifdef __APPLE__\n    ssize_t bytesSent = send(sockfd, ptr, nbytes, 0);\n#else\n    ssize_t bytesSent = sendmsg(sockfd, &msg, 0);\n#endif\n    if (bytesSent != (ssize_t)nbytes) {\n        fprintf(stderr, \"[%s:%d] error in sendmsg %ld %d\\n\", __FUNCTION__, __LINE__, (long)bytesSent, errno);\n        exit(1);\n    }\n    return bytesSent;\n}\n\nssize_t sock_fd_read(int sockfd, void *ptr, size_t nbytes, int *recvfd)\n{\n    struct msghdr    msg;\n    struct iovec     iov[1];\n    ssize_t          n;\n    union {\n        struct cmsghdr cm;\n        char           control[CMSG_SPACE(sizeof(int))];\n    } control_un;\n    struct cmsghdr   *cmptr;\n\n    //if (trace_socket)\n    //    printf(\"[%s:%d] sock %d\\n\", __FUNCTION__, __LINE__, sockfd);\n    msg.msg_control = control_un.control;\n    msg.msg_controllen = sizeof(control_un.control);\n    msg.msg_name = NULL;\n    msg.msg_namelen = 0;\n    iov[0].iov_base = ptr;\n    iov[0].iov_len = nbytes;\n    msg.msg_iov = iov;\n    msg.msg_iovlen = 1;\n\n    *recvfd = -1;        /* descriptor was not passed */\n    if ((n = recvmsg(sockfd, &msg, MSG_DONTWAIT)) <= 0)\n        return n;\n    if ((cmptr = CMSG_FIRSTHDR(&msg)) && cmptr->cmsg_len == CMSG_LEN(sizeof(int))) {\n        if (cmptr->cmsg_level != SOL_SOCKET || cmptr->cmsg_type != SCM_RIGHTS) {\n            fprintf(stderr, \"%s failed\\n\", __FUNCTION__);\n            exit(1);\n        }\n        int *datap = (int *)CMSG_DATA(cmptr);\n        *recvfd = *datap;\n        if (trace_socket)\n            fprintf(stderr, \"[%s:%d] got fd %d\\n\", __FUNCTION__, __LINE__, *datap);\n    }\n    if (n != (ssize_t)nbytes) {\n        iov[0].iov_base = (void *)((unsigned long)iov[0].iov_base + n);\n        iov[0].iov_len -= n;\n        if ((n = recvmsg(sockfd, &msg, 0)) <= 0)\n            return n;\n    }\n    return n;\n}\n\nvoid portalSendFd(int fd, void *data, int len, int sendFd)\n{\n    int rc;\n    if (trace_socket)\n        fprintf(stderr, \"%s: fd %d data %p len %d\\n\", __FUNCTION__, fd, data, len);\n    if ((rc = sock_fd_write(fd, data, len, sendFd)) != len) {\n        fprintf(stderr, \"%s: send len %d error %d\\n\",__FUNCTION__, rc, errno);\n        exit(1);\n    }\n}\nint portalRecvFd(int fd, void *data, int len, int *recvFd)\n{\n    int rc = sock_fd_read(fd, data, len, recvFd);\n    if (trace_socket && rc && rc != -1)\n        fprintf(stderr, \"%s: fd %d data %p len %d rc %d\\n\", __FUNCTION__, fd, data, len, rc);\n    return rc;\n}\n"
  },
  {
    "path": "cpp/sock_utils.h",
    "content": "\n// Copyright (c) 2013-2014 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\n#ifndef _SOCK_UTILS_H_\n#define _SOCK_UTILS_H_\n#include \"portal.h\"   // ssize_t and uint32_t\n\n#define MAX_SIMULATOR_PORTAL_ID 128\n#define MAGIC_PORTAL_FOR_SENDING_FD                 666\n#define MAGIC_PORTAL_FOR_SENDING_INTERRUPT          999\n#define SOCKET_NAME                 bluesimSocketName()\n\ntypedef struct PortalSocketParam {\n    struct addrinfo *addr;\n} PortalSocketParam; /* for ITEMINIT function */\n\nstruct memrequest{\n  uint32_t portal;\n  int write_flag;\n  volatile unsigned int *addr;\n  unsigned int data_or_tag;\n};\nstruct memresponse{\n  uint32_t portal;\n  unsigned int data;\n  unsigned int tag;\n};\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\nconst char *bluesimSocketName();\nvoid connect_to_bsim(void);\nssize_t sock_fd_write(int sockfd, void *ptr, size_t nbytes, int sendfd);\nssize_t sock_fd_read(int sockfd, void *ptr, size_t nbytes, int *recvfd);\nint pareff_fd(int *fd);\nvoid init_pareff(void);\nint init_connecting(const char *arg_name, struct PortalSocketParam *param);\nint init_listening(const char *arg_name, struct PortalSocketParam *param);\nint accept_socket(int arg_listening);\n#ifdef __cplusplus\n}\n#endif\n\n#endif //_SOCK_UTILS_H_\n"
  },
  {
    "path": "cpp/timer.c",
    "content": "// Copyright (c) 2012 Nokia, Inc.\n// Copyright (c) 2013-2014 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n#include \"portal.h\"\n\n#define MAX_TIMER_COUNT      16\n\ntypedef struct {\n    uint64_t total, min, max, over;\n} PORTAL_TIMETYPE;\n\nstatic uint64_t c_start[MAX_TIMER_COUNT];\nstatic uint64_t lap_timer_temp;\nstatic PORTAL_TIMETYPE timers[MAX_TIMERS];\n\nuint64_t portalCycleCount()\n{\n    uint64_t high_bits, low_bits;\n    volatile unsigned int *msb, *lsb;\n    initPortalHardware();\n    if(!utility_portal)\n        return 0;\n    msb = &utility_portal->map_base[PORTAL_CTRL_COUNTER_MSB];\n    lsb = &utility_portal->map_base[PORTAL_CTRL_COUNTER_LSB];\n    high_bits = utility_portal->transport->read(utility_portal, &msb);\n    low_bits = utility_portal->transport->read(utility_portal, &lsb);\n    return (high_bits << 32) | low_bits;\n}\n\nvoid portalTimerStart(unsigned int i) \n{\n    if (i < MAX_TIMER_COUNT)\n        c_start[i] = portalCycleCount();\n}\n\nuint64_t portalTimerLap(unsigned int i)\n{\n    uint64_t temp = portalCycleCount();\n    if (i >= MAX_TIMER_COUNT)\n        return 0;\n    lap_timer_temp = temp;\n    return temp - c_start[i];\n}\n\nvoid portalTimerInit(void)\n{\n    int i;\n    memset(timers, 0, sizeof(timers));\n    for (i = 0; i < MAX_TIMERS; i++)\n      timers[i].min = 1LLU << 63;\n}\n\nuint64_t portalTimerCatch(unsigned int i)\n{\n    uint64_t val = portalTimerLap(0);\n    if (i >= MAX_TIMERS)\n        return 0;\n    if (val > timers[i].max)\n        timers[i].max = val;\n    if (val < timers[i].min)\n        timers[i].min = val;\n    if (val == 000000)\n        timers[i].over++;\n    timers[i].total += val;\n    return lap_timer_temp;\n}\n\nvoid portalTimerPrint(int loops)\n{\n    int i;\n    for (i = 0; i < MAX_TIMERS; i++) {\n      if (timers[i].min != (1LLU << 63))\n           PORTAL_PRINTF(\"[%d]: avg %\" PRIx64 \" min %\" PRIx64 \" max %\" PRIx64 \" over %\" PRIx64 \"\\n\",\n               i, timers[i].total/loops, timers[i].min, timers[i].max, timers[i].over);\n    }\n}\n\n"
  },
  {
    "path": "cpp/transportHardware.c",
    "content": "\n// Copyright (c) 2012 Nokia, Inc.\n// Copyright (c) 2013-2014 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\n#include \"portal.h\"\n#ifdef __KERNEL__\n//#include \"linux/delay.h\"\n//#include \"linux/file.h\"\n//#include \"linux/dma-buf.h\"\n#else\n#include <errno.h>\n#include <fcntl.h>\n#include <sys/mman.h>\n#include <unistd.h>\n#endif\n\nstatic int trace_hardware;//=1;\nvoid send_portal_null(struct PortalInternal *pint, volatile unsigned int *buffer, unsigned int hdr, int sendFd)\n{\n}\nint recv_portal_null(struct PortalInternal *pint, volatile unsigned int *buffer, int len, int *recvfd)\n{\n    return 0;\n}\nint notfull_null(PortalInternal *pint, unsigned int v)\n{\n    return 0;\n}\nint busy_portal_null(struct PortalInternal *pint, unsigned int v, const char *str)\n{\n    return 0;\n}\nvoid enableint_portal_null(struct PortalInternal *pint, int val)\n{\n}\nint event_null(struct PortalInternal *pint)\n{\n    return -1;\n}\nunsigned int read_portal_memory(PortalInternal *pint, volatile unsigned int **addr)\n{\n    unsigned int rc = **addr;\n    *addr += 1;\n    return rc;\n}\nvoid write_portal_memory(PortalInternal *pint, volatile unsigned int **addr, unsigned int v)\n{\n    **addr = v;\n    *addr += 1;\n}\nvoid write_fd_portal_memory(PortalInternal *pint, volatile unsigned int **addr, unsigned int v)\n{\n    **addr = v;\n    *addr += 1;\n}\nvolatile unsigned int *mapchannel_req_generic(struct PortalInternal *pint, unsigned int v, unsigned int size)\n{\n    return pint->transport->mapchannelInd(pint, v);\n}\nvolatile unsigned int *mapchannel_hardware(struct PortalInternal *pint, unsigned int v)\n{\n    return &pint->map_base[PORTAL_FIFO(v)];\n}\nint notfull_hardware(PortalInternal *pint, unsigned int v)\n{\n    volatile unsigned int *tempp = pint->transport->mapchannelInd(pint, v) + 1;\n    return pint->transport->read(pint, &tempp);\n}\nint busy_hardware(struct PortalInternal *pint, unsigned int v, const char *str)\n{\n    int count = 50;\n    while (!pint->transport->notFull(pint, v) && ((pint->busyType == BUSY_SPIN) || count-- > 0))\n        ; /* busy wait a bit on 'fifo not full' */\n    if (count <= 0) {\n        if (0 && pint->busyType == BUSY_TIMEWAIT)\n            while (!pint->transport->notFull(pint, v)) {\n#ifndef __KERNEL__\n                struct timeval timeout;\n                timeout.tv_sec = 0;\n                timeout.tv_usec = 10000;\n                select(0, NULL, NULL, NULL, &timeout);\n#endif\n            }\n        else {\n          /* PORTAL_PRINTF(\"putFailed: %s\\n\", str); */\n#ifndef __KERNEL__\n            if (pint->busyType == BUSY_EXIT)\n                exit(1);\n#endif\n            return 1;\n        }\n    }\n    return 0;\n}\nvoid enableint_hardware(struct PortalInternal *pint, int val)\n{\n    volatile unsigned int *enp = &(pint->map_base[PORTAL_CTRL_INTERRUPT_ENABLE]);\n    pint->transport->write(pint, &enp, val);\n}\nint event_hardware(struct PortalInternal *pint)\n{\n    // handle all messasges from this portal instance\n    volatile unsigned int *map_base = pint->map_base;\n    // sanity check, to see the status of interrupt source and enable\n    unsigned int queue_status;\n    volatile unsigned int *statp = &map_base[PORTAL_CTRL_IND_QUEUE_STATUS];\n    volatile unsigned int *srcp = &map_base[PORTAL_CTRL_INTERRUPT_STATUS];\n    volatile unsigned int *enp = &map_base[PORTAL_CTRL_INTERRUPT_ENABLE];\n    while ((queue_status = pint->transport->read(pint, &statp))) {\n        if(trace_hardware) {\n            unsigned int int_src = pint->transport->read(pint, &srcp);\n            unsigned int int_en  = pint->transport->read(pint, &enp);\n            PORTAL_PRINTF( \"%s: (fpga%d) about to receive messages int=%08x en=%08x qs=%08x handler %p parent %p\\n\", __FUNCTION__, pint->fpga_number, int_src, int_en, queue_status, pint->handler, pint->parent);\n        }\n        if (pint->handler)\n            pint->handler(pint, queue_status-1, 0);\n        else {\n            unsigned int int_src = pint->transport->read(pint, &srcp);\n            unsigned int int_en  = pint->transport->read(pint, &enp);\n            PORTAL_PRINTF( \"%s: (fpga%d) no handler receive int=%08x en=%08x qs=%08x handler %p parent %p\\n\", __FUNCTION__, pint->fpga_number, int_src, int_en, queue_status, pint->handler, pint->parent);\n            exit(-1);\n        }\n    }\n    return -1;\n}\n\nstatic int init_hardware(struct PortalInternal *pint, void *param)\n{\n    initPortalHardware();\n#if defined(__KERNEL__)\n    int i;\n    pint->map_base = NULL;\n    for (i = 0; i < MAX_NUM_PORTALS; i++) {\n      if (tboard->portal[i].device_name == pint->fpga_number) {\n        pint->map_base = (volatile unsigned int*)(tboard->bar2io + i * PORTAL_BASE_OFFSET);\n        break;\n      }\n    }\n    if (!pint->map_base) {\n\tPORTAL_PRINTF(\"init_hardware: portal not found %d.\\n\", pint->fpga_number);\n        return -1;\n    }\n#else\n    char oldname[128];\n    char newname[128];\n    int i;\n    snprintf(oldname, sizeof(oldname), \"/dev/portal_%d_%d\", pint->fpga_tile, pint->fpga_number);\n    snprintf(newname, sizeof(newname), \"/dev/portal_b%dt%dp%d\", pint->board_number, pint->fpga_tile, pint->fpga_number);\n    //FIXME: race condition on Zynq between cat /dev/connectal and here\n    for (i = 0; i < 5; i++) {\n\n\t// try old style name\n\tpint->fpga_fd = open(oldname, O_RDWR);\n\tif (pint->fpga_fd >= 0)\n\t    break;\n\n\t// try new style name\n\tpint->fpga_fd = open(newname, O_RDWR);\n\tif (pint->fpga_fd >= 0)\n\t    break;\n\n\t// retry if EACCESS\n\tif (errno == EACCES && i != 4) {\n\t    sleep(1);\n\t    continue;\n\t}\n\n\t// else fail\n\tPORTAL_PRINTF(\"Failed to open %s fd=%d errno=%d:%s\\n\", oldname, pint->fpga_fd, errno, strerror(errno));\n\treturn -errno;\n    }\n    pint->map_base = (volatile unsigned int*)portalMmap(pint->fpga_fd, PORTAL_BASE_OFFSET);\n    if (pint->map_base == MAP_FAILED) {\n        PORTAL_PRINTF(\"Failed to mmap PortalHWRegs from fd=%d errno=%d\\n\", pint->fpga_fd, errno);\n        return -errno;\n    }  \n#endif\n    return 0;\n}\nstatic unsigned int read_hardware(PortalInternal *pint, volatile unsigned int **addr)\n{\n    return **addr;\n}\nstatic void write_hardware(PortalInternal *pint, volatile unsigned int **addr, unsigned int v)\n{\n    **addr = v;\n}\nstatic void write_fd_hardware(PortalInternal *pint, volatile unsigned int **addr, unsigned int v)\n{\n    **addr = v;\n}\n\nPortalTransportFunctions transportHardware = {\n    init_hardware, read_hardware, write_hardware, write_fd_hardware, mapchannel_hardware, mapchannel_req_generic,\n    send_portal_null, recv_portal_null, busy_hardware, enableint_hardware, event_hardware, notfull_hardware};\n"
  },
  {
    "path": "cpp/transportPortal.c",
    "content": "\n// Copyright (c) 2018, The Connectal Project\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\n#include \"portal.h\"\n#include <errno.h>\n#include <fcntl.h>\n#include <sys/mman.h>\n#include <unistd.h>\n\nstatic int trace_portal=0;\nstatic void enableint_portal(struct PortalInternal *pint, int val)\n{\n   pint->map_base[PORTAL_CTRL_INTERRUPT_ENABLE] = val;\n}\nstatic int event_portal(struct PortalInternal *pint)\n{\n    // handle all messasges from this portal instance\n    volatile unsigned int *map_base = pint->map_base, len;\n    while ((len = map_base[PORTAL_CTRL_IND_QUEUE_STATUS])) {\n        if(trace_portal)\n            PORTAL_PRINTF( \"%s: (fpga%d) about to receive messages int=%08x en=%08x qs=%08x handler %p parent %p\\n\", __FUNCTION__, pint->fpga_number, 0, 0, 0, pint->handler, pint->parent);\n        if (pint->handler)\n            pint->handler(pint, 5/*portal number ATOMICC */, 0);\n        else {\n            PORTAL_PRINTF( \"%s: (fpga%d) no handler receive int=%08x en=%08x qs=%08x handler %p parent %p\\n\", __FUNCTION__, pint->fpga_number, 0, 0, 0, pint->handler, pint->parent);\n            exit(-1);\n        }\n    }\n    return -1;\n}\n\nstatic volatile unsigned int *portalPtr;\nstatic int init_portal(struct PortalInternal *pint, void *param)\n{\n    initPortalHardware();\n    char oldname[128];\n    int i;\n    snprintf(oldname, sizeof(oldname), \"/dev/portal_%d_%d\", pint->fpga_tile, pint->fpga_number);\n    //FIXME: race condition on Zynq between cat /dev/connectal and here\n    for (i = 0; i < 5; i++) {\n\t// try old style name\n\tpint->fpga_fd = open(oldname, O_RDWR);\n\tif (pint->fpga_fd >= 0)\n\t    break;\n\n\t// retry if EACCESS\n\tif (errno == EACCES && i != 4) {\n\t    sleep(1);\n\t    continue;\n\t}\n\n\t// else fail\n\tPORTAL_PRINTF(\"Failed to open %s fd=%d errno=%d:%s\\n\", oldname, pint->fpga_fd, errno, strerror(errno));\n\treturn -errno;\n    }\n    pint->map_base = (volatile unsigned int*)portalMmap(pint->fpga_fd, PORTAL_BASE_OFFSET);\n    if (pint->map_base == MAP_FAILED) {\n        PORTAL_PRINTF(\"Failed to mmap PortalHWRegs from fd=%d errno=%d\\n\", pint->fpga_fd, errno);\n        return -errno;\n    }  \n    portalPtr = &pint->map_base[PORTAL_FIFO(0)];\n    return 0;\n}\nstatic void send_portal(struct PortalInternal *pint, volatile unsigned int *data, unsigned int hdr, int sendFd)\n{\n    volatile unsigned int *buffer = data-1;\n    //if(trace_portal)\n        fprintf(stderr, \"[%s:%d] hdr %x fpga %x num %d\\n\", __FUNCTION__, __LINE__, hdr, pint->fpga_number, pint->client_fd_number);\n    buffer[0] = hdr;\n    if (!portalPtr[1]) {\n        printf(\"[%s:%d] ERROR: queue full\\n\", __FUNCTION__, __LINE__);\n        return;\n    }\n    int i = (hdr & 0xffff) - 2;\n    for (; i > 0; i--) {\nprintf(\"[SEND] data[%d] = %x\\n\", i, data[i]);\n        portalPtr[0] = data[i];\n    }\nprintf(\"[SEND] Ldata[%d] = %x\\n\", 0, data[0]);\n    portalPtr[1] = data[0];\n}\nstatic int recv_portal(struct PortalInternal *pint, volatile unsigned int *buffer, int len, int *recvfd)\n{\n    int i;\n    for (i = 0; i < len; i++) {\n        buffer[i] = portalPtr[0];\nprintf(\"[RECV] data[%d] = %x\\n\", i, buffer[i]);\n    }\n    return 0;\n}\n\nPortalTransportFunctions transportPortal = {\n    init_portal, NULL, NULL, NULL, NULL, NULL,\n    send_portal, recv_portal, NULL, enableint_portal, event_portal, NULL};\n"
  },
  {
    "path": "cpp/transportSerial.c",
    "content": "// Copyright (c) 2016 Connectal Project\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\n#include <arpa/inet.h>\n#include <errno.h>\n\n#include \"portal.h\"\n#include \"dmaManager.h\"\n#include \"sock_utils.h\"\n\n#ifdef __KERNEL__\n#include \"linux/delay.h\"\n#include \"linux/file.h\"\n#include \"linux/dma-buf.h\"\n#define assert(A)\n#else\n#include <string.h>\n#include <assert.h>\n#include <errno.h>\n#include <fcntl.h>\n#include <sys/mman.h>\n#include <termios.h>\n#include <unistd.h>\n#include <sys/ioctl.h>\n#include <time.h> // ctime\n#endif\n#include \"drivers/portalmem/portalmem.h\" // PA_MALLOC\n#define PLATFORM_TILE 0\n\nstatic int init_serial(struct PortalInternal *pint, void *aparam)\n{\n    PortalSharedParam *param = (PortalSharedParam *)aparam;\n    if (param) {\n\tint serial_fd = param->serial.serial_fd;\n\tpint->map_base = (volatile unsigned int *)malloc(4096);\n\tpint->client_fd[0] = serial_fd;\n\tpint->client_fd_number = 1;\n\tfprintf(stderr, \"init_serial param=%p pint=%p serial_fd=%d map_base=%p\\n\",\n\t\tparam, pint, param->serial.serial_fd, pint->map_base);\n\n\tif (0) {\n\t    struct termios terminfo;\n\t    int rc;\n\t    tcflush(serial_fd, TCIOFLUSH);\n\t    tcgetattr(serial_fd, &terminfo);\n\t    terminfo.c_cflag = CS8 | CLOCAL | CREAD | PARENB;\n\t    terminfo.c_cflag &= ~CRTSCTS; // needed for /dev/tty.SLAB_USBtoUART\n\t    terminfo.c_iflag = IGNCR;\n\t    terminfo.c_lflag = ICANON;\n\t    cfsetspeed(&terminfo, B115200);\n\t    rc = tcsetattr(serial_fd, TCSANOW, &terminfo);\n\t    if (rc != 0) {\n\t\tfprintf(stderr, \"tcsetattr %d errno %d:%s\\n\", rc, errno, strerror(errno));\n\t    }\n\t}\n    }\n    return 0;\n}\nstatic volatile unsigned int *mapchannel_serialInd(struct PortalInternal *pint, unsigned int v)\n{\n    return &pint->map_base[128+1];\n}\nstatic volatile unsigned int *mapchannel_serialReq(struct PortalInternal *pint, unsigned int v, unsigned int size)\n{\n    return &pint->map_base[0+1];\n}\nstatic int busywait_serial(struct PortalInternal *pint, unsigned int v, const char *str)\n{\n    return 0;\n}\nstatic void send_serial(struct PortalInternal *pint, volatile unsigned int *buffer, unsigned int hdr, int sendFd)\n{\n    int reqwords = hdr & 0xffff;\n    int i;\n\n    fprintf(stderr, \"send_serial head=%d hdr=%08x reqwords=%d buffer=%p buffer[1]=%08x buffer[2]=%08x\\n\",\n\t    buffer[0], hdr, reqwords, buffer, buffer[1], buffer[2]);\n    buffer[0] = hdr;\n    if (0)\n    for (i = 0; i < reqwords+1; i++)\n\tbuffer[i] = htonl(buffer[i]);\n    int nbytes = write(pint->client_fd[0], (void*)buffer, 4*reqwords);\n    if (nbytes != 4*reqwords) {\n\tfprintf(stderr, \"%s:%x pint=%p fd=%d nbytes=%d errno=%d:%s\\n\", __FUNCTION__, __LINE__, pint, pint->client_fd[0], nbytes, errno, strerror(errno));\n    }\n    buffer[0] = 0;\n    //tcdrain(pint->client_fd[0]);\n}\nstatic int event_serial(struct PortalInternal *pint)\n{\n    if (0) fprintf(stderr, \"%s:%d serial_fd=%d\\n\", __FUNCTION__, __LINE__, pint->client_fd[0]);\n    int nbytes;\n    int i = 0;\n    char *base = (char *)&pint->map_base[128];\n    int tries = 0;\n    do {\n      nbytes = read(pint->client_fd[0], (void*)(base + i), 4);\n      if (nbytes > 0)\n\ti += nbytes;\n      if (0) fprintf(stderr, \"%s:%d i=%d nbytes=%d hdr=%#08x\\n\", __FUNCTION__, __LINE__, i, nbytes, pint->map_base[128]);\n      if (i >= 4) {\n\tint reqwords = pint->map_base[128] & 0xFFFF;\n\tint msg_num = pint->map_base[128] >> 16;\n\tif (reqwords > 1) {\n\t  nbytes = read(pint->client_fd[0], (void*)&pint->map_base[129], 4*(reqwords-1));\n\t  if (nbytes < 4*(reqwords-1))\n\t    fprintf(stderr, \"SHORT READ %s:%d i=%d nbytes=%d buffer=%p msgbody[0]=%08x\\n\", __FUNCTION__, __LINE__, i, nbytes, &pint->map_base[128], pint->map_base[128+1]);\n\t}\n\tif (msg_num != 0xFFFF && pint->handler)\n\t    pint->handler(pint, msg_num, 0);\n\ti = 0;\n      }\n    } while (nbytes > 0 || tries-- > 0);\n    return -1;\n}\nPortalTransportFunctions transportSerial = {\n    init_serial, read_portal_memory, write_portal_memory, write_fd_portal_memory, mapchannel_serialInd, mapchannel_serialReq,\n    send_serial, recv_portal_null, busywait_serial, enableint_portal_null, event_serial, notfull_null};\n\nstatic int init_serialmux(struct PortalInternal *pint, void *aparam)\n{\n    PortalMuxParam *param = (PortalMuxParam *)aparam;\n    fprintf(stderr, \"%s:%d pint=%p client_fd=%d\\n\", __FUNCTION__, __LINE__, pint, pint->client_fd[0]);\n    pint->mux = param->pint;\n    pint->map_base = ((volatile unsigned int*)malloc(REQINFO_SIZE(pint->reqinfo) + sizeof(uint32_t))) + 1;\n    memset((void *)(pint->map_base-1), 0, REQINFO_SIZE(pint->reqinfo) + sizeof(uint32_t));  // for valgrind\n    pint->mux->map_base[0] = -1;\n    pint->mux->mux_ports_number++;\n    pint->mux->mux_ports = (PortalMuxHandler *)realloc(pint->mux->mux_ports, pint->mux->mux_ports_number * sizeof(PortalMuxHandler));\n    pint->mux->mux_ports[pint->mux->mux_ports_number-1].pint = pint;\n    return 0;\n}\nstatic void send_serialmux(struct PortalInternal *pint, volatile unsigned int *data, unsigned int hdr, int sendFd)\n{\n    volatile unsigned int *buffer = data-1;\n    buffer[0] = hdr;\n    fprintf(stderr, \"%s:%d pint=%p mux=%p map_base=%p mux->map_base=%p buffer=%p\\n\", __FUNCTION__, __LINE__, pint, pint->mux, pint->map_base, pint->mux->map_base, buffer);\n    pint->mux->request_index = pint->request_index;\n    pint->mux->transport->send(pint->mux, buffer, (pint->fpga_number << 24) | hdr, sendFd);\n}\nstatic int recv_serialmux(struct PortalInternal *pint, volatile unsigned int *buffer, int len, int *recvfd)\n{\n    return pint->mux->transport->recv(pint->mux, buffer, len, recvfd);\n}\nint portal_serialmux_handler(struct PortalInternal *pint, unsigned int channel, int messageFd)\n{\n    int i;\n    unsigned int fpga_number = (channel >> 8) & 0xFF;\n    unsigned int msg_number  = (channel >> 0) & 0xFF;\n    fprintf(stderr, \"%s:%d channel=%x\\n\", __FUNCTION__, __LINE__, channel);\n    for (i = 0; i < pint->mux_ports_number; i++) {\n        PortalInternal *p = pint->mux_ports[i].pint;\n\tint hdr = pint->map_base[128];\n\tint reqwords = hdr & 0xffff;\n\tmemcpy((void *)&p->map_base[128], (void *)&pint->map_base[128], 4*reqwords);\n        if (fpga_number == p->fpga_number && p->handler) {\n            p->handler(p, msg_number, messageFd);\n        }\n    }\n    return -1;\n}\nPortalTransportFunctions transportSerialMux = {\n    init_serialmux, read_portal_memory, write_portal_memory, write_fd_portal_memory, mapchannel_serialInd, mapchannel_req_generic,\n    send_serialmux, recv_serialmux, busy_portal_null, enableint_portal_null, event_null, notfull_null};\n\n"
  },
  {
    "path": "cpp/transportShared.c",
    "content": "// Copyright (c) 2014 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\n#include \"portal.h\"\n#include \"dmaManager.h\"\n#include \"sock_utils.h\"\n\n#ifdef __KERNEL__\n#include \"linux/delay.h\"\n#include \"linux/file.h\"\n#include \"linux/dma-buf.h\"\n#define assert(A)\n#else\n#include <string.h>\n#include <assert.h>\n#include <errno.h>\n#include <fcntl.h>\n#include <sys/mman.h>\n#include <unistd.h>\n#include <sys/ioctl.h>\n#include <time.h> // ctime\n#endif\n#include \"drivers/portalmem/portalmem.h\" // PA_MALLOC\n#define PLATFORM_TILE 0\n\nstatic int init_shared(struct PortalInternal *pint, void *aparam)\n{\n    PortalSharedParam *param = (PortalSharedParam *)aparam;\n    if (param) {\n        int fd = portalAlloc(param->size, 1);\n        pint->map_base = (volatile unsigned int *)portalMmap(fd, param->size);\n        pint->map_base[SHARED_LIMIT] = param->size/sizeof(uint32_t);\n        pint->map_base[SHARED_WRITE] = SHARED_START;\n        pint->map_base[SHARED_READ] = SHARED_START;\n        pint->map_base[SHARED_START] = 0;\n        if (param->dma.manager)\n            pint->shared_dma = &param->dma.manager->priv;\n        else if (param->dma.reqinfo) {\n            PortalInternal *psgl = (PortalInternal *)malloc(sizeof(PortalInternal));\n            init_portal_internal(psgl, param->dma.reqport, PLATFORM_TILE, NULL,\n                NULL, NULL, NULL, NULL, param->dma.reqinfo);\n            DmaManagerPrivate *p = (DmaManagerPrivate *)malloc(sizeof(DmaManagerPrivate));\n            pint->shared_dma = p;\n            DmaManager_init(p, psgl);\n            p->poll = param->dma.poll;\n            p->shared_mmu_indication = (PortalInternal *)malloc(sizeof(PortalInternal));\n            init_portal_internal(p->shared_mmu_indication, param->dma.indport, PLATFORM_TILE, param->dma.handler,\n                param->dma.callbackFunctions, NULL, NULL, NULL, param->dma.indinfo);\n        }\n        DmaManagerPrivate *p = (DmaManagerPrivate *)pint->shared_dma;\n        if (p) {\n            pint->sharedMem = DmaManager_reference(p, fd);\n            MMURequest_setInterface(p->sglDevice, pint->fpga_number, pint->sharedMem);\n        }\n        if (param->hardware.setSglId) {\n            PortalInternal *p = (PortalInternal *)malloc(sizeof(PortalInternal));\n            pint->shared_cfg = p;\n            init_portal_internal(p, param->hardware.port, pint->fpga_tile, NULL,\n                NULL, NULL, NULL, NULL, param->hardware.reqinfo);\n            param->hardware.setSglId(p, pint->sharedMem);\n        }\n    }\n    return 0;\n}\nstatic volatile unsigned int *mapchannel_sharedInd(struct PortalInternal *pint, unsigned int v)\n{\n    return &pint->map_base[pint->map_base[SHARED_READ]+1];\n}\nstatic volatile unsigned int *mapchannel_sharedReq(struct PortalInternal *pint, unsigned int v, unsigned int size)\n{\n    return &pint->map_base[pint->map_base[SHARED_WRITE]+1];\n}\nstatic int busywait_shared(struct PortalInternal *pint, unsigned int v, const char *str)\n{\n    int reqwords = REQINFO_SIZE(pint->reqinfo)/sizeof(uint32_t) + 1;\n    reqwords = (reqwords + 1) & 0xfffe;\n    volatile unsigned int *map_base = pint->map_base;\n    int limit = map_base[SHARED_LIMIT];\n    while (1) {\n\tint write = map_base[SHARED_WRITE];\n\tint read = map_base[SHARED_READ];\n\tint avail;\n\tif (write >= read) {\n\t    avail = limit - (write - read) - 4;\n\t} else {\n\t    avail = read - write;\n\t}\n\tint enqready = (avail > 2*reqwords); // might have to wrap\n\t//fprintf(stderr, \"busywait_shared limit=%d write=%d read=%d avail=%d enqready=%d\\n\", limit, write, read, avail, enqready);\n\tif (avail < reqwords)\n\t    fprintf(stderr, \"****\\n    not enough space available \\n****\\n\");\n\tif (enqready)\n\t    return 0;\n    }\n    return 0;\n}\nstatic inline unsigned int increment_shared(PortalInternal *pint, unsigned int newp)\n{\n    int reqwords = REQINFO_SIZE(pint->reqinfo)/sizeof(uint32_t) + 1;\n    reqwords = (reqwords + 1) & 0xfffe;\n    if (newp + reqwords >= pint->map_base[SHARED_LIMIT])\n        newp = SHARED_START;\n    return newp;\n}\nstatic void send_shared(struct PortalInternal *pint, volatile unsigned int *buff, unsigned int hdr, int sendFd)\n{\n    int reqwords = hdr & 0xffff;\n    int needs_padding = (reqwords & 1);\n\n    pint->map_base[pint->map_base[SHARED_WRITE]] = hdr;\n    if (needs_padding) {\n\t// pad req\n\tpint->map_base[pint->map_base[SHARED_WRITE] + reqwords] = 0xffff0001;\n\treqwords = (reqwords + 1) & 0xfffe;\n    }\n    pint->map_base[SHARED_WRITE] = increment_shared(pint, pint->map_base[SHARED_WRITE] + reqwords);\n    //fprintf(stderr, \"send_shared head=%d padded=%d hdr=%08x\\n\", pint->map_base[SHARED_WRITE], needs_padding, hdr);\n    pint->map_base[pint->map_base[SHARED_WRITE]] = 0;\n}\nstatic int event_shared(struct PortalInternal *pint)\n{\n    if (pint->map_base && pint->map_base[SHARED_READ] != pint->map_base[SHARED_WRITE]) {\n        unsigned int hdr = pint->map_base[pint->map_base[SHARED_READ]];\n\tunsigned short msg_num = hdr >> 16;\n\tunsigned short msg_words = hdr & 0xffff;\n\tmsg_words = (msg_words + 1) & 0xfffe;\n\tif (msg_num != 0xffff && pint->handler)\n\t    pint->handler(pint, msg_num, 0);\n        pint->map_base[SHARED_READ] = increment_shared(pint, pint->map_base[SHARED_READ] + msg_words);\n    }\n    return -1;\n}\nPortalTransportFunctions transportShared = {\n    init_shared, read_portal_memory, write_portal_memory, write_fd_portal_memory, mapchannel_sharedInd, mapchannel_sharedReq,\n    send_shared, recv_portal_null, busywait_shared, enableint_portal_null, event_shared, notfull_null};\nstatic volatile unsigned int *mapchannel_traceInd(struct PortalInternal *pint, unsigned int v)\n{\n    return &pint->map_base[pint->map_base[SHARED_READ]];\n}\nstatic volatile unsigned int *mapchannel_traceReq(struct PortalInternal *pint, unsigned int v, unsigned int size)\n{\n    return &pint->map_base[pint->map_base[SHARED_WRITE]];\n}\nextern void memdump(uint8_t *p, int len, const char *title);\nstatic void send_trace(struct PortalInternal *pint, volatile unsigned int *buff, unsigned int hdr, int sendFd)\n{\n    int reqwords = hdr & 0xffff;\n    pint->map_base[pint->map_base[SHARED_WRITE]+reqwords-1] = hdr;\n    pint->map_base[SHARED_WRITE] = increment_shared(pint, pint->map_base[SHARED_WRITE] + reqwords);\n    //fprintf(stderr, \"send_shared head=%d padded=%d hdr=%08x\\n\", pint->map_base[SHARED_WRITE], needs_padding, hdr);\n    pint->map_base[pint->map_base[SHARED_WRITE]] = 0;\n}\nPortalTransportFunctions transportTrace = {\n    init_shared, read_portal_memory, write_portal_memory, write_fd_portal_memory, mapchannel_traceInd, mapchannel_traceReq,\n    send_trace, recv_portal_null, busywait_shared, enableint_portal_null, event_shared, notfull_null};\n\n\n"
  },
  {
    "path": "cpp/transportSocket.c",
    "content": "\n// Copyright (c) 2013-2014 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\n#include \"portal.h\"\n#include \"sock_utils.h\"\n#include <assert.h>\n\nstatic int trace_socket; // = 1;\n\n#ifndef __KERNEL__\n#include <stdio.h>\n#include <stdlib.h>\n#include <errno.h>\n#include <string.h>\n#include <unistd.h>\n#include <sys/ioctl.h>      // FIONBIO\n#include <sys/types.h>\n#include <sys/socket.h>\n#include <sys/un.h>\n#include <semaphore.h>\n#include <pthread.h>\n#include <netdb.h>\n\nvoid memdump(unsigned char *p, int len, const char *title)\n{\nint i;\n\n    i = 0;\n    while (len > 0) {\n        if (!(i & 0xf)) {\n            if (i > 0)\n                fprintf(stderr, \"\\n\");\n            fprintf(stderr, \"%s: \",title);\n        }\n        fprintf(stderr, \"%02x \", *p++);\n        i++;\n        len--;\n    }\n    fprintf(stderr, \"\\n\");\n}\n\nstatic pthread_mutex_t socket_mutex;\nint global_sockfd = -1;\n\nstatic int init_socketResp(struct PortalInternal *pint, void *aparam)\n{\n    //initPortalHardware();\n    PortalSocketParam *param = (PortalSocketParam *)aparam;\n    char buff[128];\n    int on = 1;\n    const char *name = getenv(\"SOFTWARE_SOCKET_NAME\");\n    if (!name)\n\tname = \"SWSOCK\";\n    sprintf(buff, \"%s%d\", name, pint->fpga_number);\n    pint->fpga_fd = init_listening(buff, param);\n    ioctl(pint->fpga_fd, FIONBIO, &on);\n    pint->map_base = (volatile unsigned int*)malloc(REQINFO_SIZE(pint->reqinfo));\n    memset((void *)pint->map_base, 0, REQINFO_SIZE(pint->reqinfo));  // for valgrind\n    pint->poller_register = 1;\n    return 0;\n}\nstatic int init_socketInit(struct PortalInternal *pint, void *aparam)\n{\n#if defined(SIMULATION) || !defined(__ATOMICC__)\n    initPortalHardware();\n#endif\n    PortalSocketParam *param = (PortalSocketParam *)aparam;\n    char buff[128];\n    const char *name = getenv(\"SOFTWARE_SOCKET_NAME\");\n    if (!name)\n\tname = \"SWSOCK\";\n    sprintf(buff, \"%s%d\", name, pint->fpga_number);\n    pint->client_fd[pint->client_fd_number++] = init_connecting(buff, param);\n    pint->accept_finished = 1;\n    pint->map_base = (volatile unsigned int*)malloc(REQINFO_SIZE(pint->reqinfo));\n    memset((void *)pint->map_base, 0, REQINFO_SIZE(pint->reqinfo));  // for valgrind\n    pint->poller_register = 1;\n    return 0;\n}\nvolatile unsigned int *mapchannel_socket(struct PortalInternal *pint, unsigned int v)\n{\n    return &pint->map_base[1];\n}\nstatic int recv_socket(struct PortalInternal *pint, volatile unsigned int *buffer, int len, int *recvfd)\n{\n    int rc = portalRecvFd(pint->client_fd[pint->indication_index], (void *)buffer, len * sizeof(uint32_t), recvfd);\n    if(trace_socket) {\n        fprintf(stderr, \"[%s:%d] len %d fd %d rc %d\\n\", __FUNCTION__, __LINE__, len, pint->client_fd[pint->indication_index], rc);\n        if (rc > 0) {\n        char bname[100];\n        sprintf(bname,\"RECV%d.%d\", getpid(), pint->client_fd[pint->indication_index]);\n        memdump((uint8_t*)buffer, rc, bname);\n        }\n    }\n    return rc;\n}\nstatic int event_socket(struct PortalInternal *pint)\n{\n    int i, j, event_socket_fd;\n    for (i = 0; i < pint->client_fd_number;) {\n       int len = portalRecvFd(pint->client_fd[i], (void *)pint->map_base, sizeof(uint32_t), &event_socket_fd);\n       if (len==sizeof(uint32_t) && trace_socket) fprintf(stderr, \"[%s:%d] %d\\n\", __FUNCTION__, __LINE__, pint->map_base[0]);\n       if (len == 0) { /* EOF */\n           close(pint->client_fd[i]);\n           pint->client_fd_number--;\n           for (j = i; j < pint->client_fd_number; j++)\n                pint->client_fd[j] = pint->client_fd[j+1];\n           if (pint->cb)\n               pint->cb->disconnect(pint);\n       }\n       else if (len == -1 && errno == EAGAIN) {\n           i++;\n           continue;\n       }\n       else if (len == -1) {\n           PORTAL_PRINTF( \"%s[%d]: read error %d\\n\",__FUNCTION__, pint->client_fd[i], errno);\n           exit(1);\n       }\n       pint->indication_index = i;\n       if (pint->handler)\n           pint->handler(pint, *pint->map_base >> 16, event_socket_fd);\n       break;\n    }\n    if (pint->fpga_fd != -1) {\n        int sockfd = accept_socket(pint->fpga_fd);\n        if (sockfd != -1) {\n            if (trace_socket)\n                fprintf(stderr, \"[%s:%d]afteracc %p accfd %d fd %d\\n\", __FUNCTION__, __LINE__, pint, pint->fpga_fd, sockfd);\n            pint->client_fd[pint->client_fd_number++] = sockfd;\n            pint->accept_finished = 1;\n#ifndef NO_CPP_PORTAL_CODE\n#ifndef NO_POLLER_SUPPORT\n            if (pint->poller)\n                addFdToPoller(pint->poller, sockfd);\n#endif\n#endif\n            //return sockfd;\n        }\n    }\n    return -1;\n}\nstatic void send_socket(struct PortalInternal *pint, volatile unsigned int *data, unsigned int hdr, int sendFd)\n{\n    volatile unsigned int *buffer = data-1;\n    if(trace_socket)\n        fprintf(stderr, \"[%s:%d] hdr %x fpga %x num %d\\n\", __FUNCTION__, __LINE__, hdr, pint->fpga_number, pint->client_fd_number);\n    buffer[0] = hdr;\n    while (pint->client_fd_number == 0)\n        event_socket(pint);\n    if(trace_socket) {\n        char bname[100];\n        sprintf(bname,\"SEND%d.%d\", getpid(), pint->client_fd[pint->request_index]);\n        memdump((uint8_t*)buffer, (hdr & 0xffff) * sizeof(uint32_t), bname);\n    }\n    portalSendFd(pint->client_fd[pint->request_index], (void *)buffer, (hdr & 0xffff) * sizeof(uint32_t), sendFd);\n}\nPortalTransportFunctions transportSocketResp = {\n    init_socketResp, read_portal_memory, write_portal_memory, write_fd_portal_memory, mapchannel_socket, mapchannel_req_generic,\n    send_socket, recv_socket, busy_portal_null, enableint_portal_null, event_socket, notfull_null};\nPortalTransportFunctions transportSocketInit = {\n    init_socketInit, read_portal_memory, write_portal_memory, write_fd_portal_memory, mapchannel_socket, mapchannel_req_generic,\n    send_socket, recv_socket, busy_portal_null, enableint_portal_null, event_socket, notfull_null};\n\n\nstatic int init_mux(struct PortalInternal *pint, void *aparam)\n{\n    //initPortalHardware();\n    PortalMuxParam *param = (PortalMuxParam *)aparam;\n    if(trace_socket)\n        fprintf(stderr, \"[%s:%d]\\n\", __FUNCTION__, __LINE__);\n    pint->mux = param->pint;\n    pint->map_base = ((volatile unsigned int*)malloc(REQINFO_SIZE(pint->reqinfo) + sizeof(uint32_t))) + 1;\n    memset((void *)(pint->map_base-1), 0, REQINFO_SIZE(pint->reqinfo) + sizeof(uint32_t));  // for valgrind\n    pint->mux->map_base[0] = -1;\n    pint->mux->mux_ports_number++;\n    pint->mux->mux_ports = (PortalMuxHandler *)realloc(pint->mux->mux_ports, pint->mux->mux_ports_number * sizeof(PortalMuxHandler));\n    pint->mux->mux_ports[pint->mux->mux_ports_number-1].pint = pint;\n    return 0;\n}\nstatic void send_mux(struct PortalInternal *pint, volatile unsigned int *data, unsigned int hdr, int sendFd)\n{\n    volatile unsigned int *buffer = data-1;\n    if(trace_socket)\n        fprintf(stderr, \"[%s:%d] hdr %x fpga %x\\n\", __FUNCTION__, __LINE__, hdr, pint->fpga_number);\n    buffer[0] = hdr;\n    pint->mux->request_index = pint->request_index;\n    pint->mux->transport->send(pint->mux, buffer, (pint->fpga_number << 16) | ((hdr + 1) & 0xffff), sendFd);\n}\nstatic int recv_mux(struct PortalInternal *pint, volatile unsigned int *buffer, int len, int *recvfd)\n{\n    return pint->mux->transport->recv(pint->mux, buffer, len, recvfd);\n}\nint portal_mux_handler(struct PortalInternal *pint, unsigned int channel, int messageFd)\n{\n    int i, dummy;\n    for (i = 0; i < pint->mux_ports_number; i++) {\n        PortalInternal *p = pint->mux_ports[i].pint;\n        if (channel == p->fpga_number && p->handler) {\n            p->transport->recv(p, p->map_base, 1, &dummy);\n            if (connectalPrintfHandler && (*p->map_base >> 16) == CONNECTAL_PRINTF_PORT)\n                connectalPrintfHandler(p, *p->map_base);\n            else\n                p->handler(p, *p->map_base >> 16, messageFd);\n        }\n    }\n    return -1;\n}\nPortalTransportFunctions transportMux = {\n    init_mux, read_portal_memory, write_portal_memory, write_fd_portal_memory, mapchannel_socket, mapchannel_req_generic,\n    send_mux, recv_mux, busy_portal_null, enableint_portal_null, event_null, notfull_null};\n\n/*\n * BOARD_bluesim\n */\nstatic struct memresponse shared_response;\nstatic int shared_response_valid;\nstatic uint32_t interrupt_value;\nint poll_response(uint32_t id)\n{\n  int recvFd;\n  if (!shared_response_valid) {\n      if (portalRecvFd(global_sockfd, &shared_response, sizeof(shared_response), &recvFd) == sizeof(shared_response)) {\n          if (shared_response.portal == MAGIC_PORTAL_FOR_SENDING_INTERRUPT)\n              interrupt_value = shared_response.data;\n          else\n              shared_response_valid = 1;\n      }\n  }\n  return shared_response_valid && shared_response.portal == id;\n}\nunsigned int bsim_poll_interrupt(void)\n{\n  if (global_sockfd == -1)\n      return 0;\n  pthread_mutex_lock(&socket_mutex);\n  poll_response(-1);\n  pthread_mutex_unlock(&socket_mutex);\n  return interrupt_value;\n}\n#else // __KERNEL__\n\n/*\n * Used when running application in kernel and BOARD_bluesim in userspace\n */\n\n#include <linux/kernel.h>\n#include <linux/uaccess.h> // copy_to/from_user\n#include <linux/mutex.h>\n#include <linux/semaphore.h>\n#include <linux/slab.h>\n#include <linux/dma-buf.h>\n\nextern struct semaphore bsim_start;\nstatic struct semaphore bsim_avail;\nstatic struct semaphore bsim_have_response;\nvoid memdump(unsigned char *p, int len, char *title);\nstatic int have_request;\nstatic struct memrequest upreq;\nstatic struct memresponse downresp;\nextern int bsim_relay_running;\nextern int main_program_finished;\n\nssize_t connectal_kernel_read (struct file *f, char __user *arg, size_t len, loff_t *data)\n{\n    int err;\n    if (!bsim_relay_running)\n        up(&bsim_start);\n    bsim_relay_running = 1;\n    if (main_program_finished)\n        return 0;          // all done!\n    if (!have_request)\n        return -EAGAIN;\n    if (len > sizeof(upreq))\n        len = sizeof(upreq);\n    if (upreq.write_flag == MAGIC_PORTAL_FOR_SENDING_FD) // part of sock_fd_write() processing\n        upreq.addr = (void *)(long)dma_buf_fd((struct dma_buf *)upreq.addr, O_CLOEXEC); /* get an fd in user process!! */\n    err = copy_to_user((void __user *) arg, &upreq, len);\n    have_request = 0;\n    up(&bsim_avail);\n    return len;\n}\nssize_t connectal_kernel_write (struct file *f, const char __user *arg, size_t len, loff_t *data)\n{\n    int err;\n    if (len > sizeof(downresp))\n        len = sizeof(downresp);\n    err = copy_from_user(&downresp, (void __user *) arg, len);\n    if (!err)\n        up(&bsim_have_response);\n    return len;\n}\n\nvoid connect_to_bsim(void)\n{\n    printk(\"[%s:%d]\\n\", __FUNCTION__, __LINE__);\n    if (bsim_relay_running)\n        return;\n    sema_init (&bsim_avail, 1);\n    sema_init (&bsim_have_response, 0);\n    initialize_bsim_map();\n    printk(\"[%s:%d]\\n\", __FUNCTION__, __LINE__);\n    down_interruptible(&bsim_start);\n}\n\nstatic struct memresponse shared_response;\nstatic int shared_response_valid;\nstatic uint32_t interrupt_value;\nstatic int poll_response(int id)\n{\n  //int recvFd;\n  if (!shared_response_valid) {\n#if 0\n      if (portalRecvFd(global_sockfd, &shared_response, sizeof(shared_response), &recvFd) == sizeof(shared_response)) {\n          if (shared_response.portal == MAGIC_PORTAL_FOR_SENDING_INTERRUPT)\n              interrupt_value = shared_response.data;\n          else\n              shared_response_valid = 1;\n      }\n#endif\n  }\n  return shared_response_valid && shared_response.portal == id;\n}\n#endif\n\n"
  },
  {
    "path": "cpp/transportWebSocket.c",
    "content": "\n// Copyright (c) 2014 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\n#include <sys/types.h>\n#include <sys/socket.h>\n#include <netdb.h>\n#include \"portal.h\"\n#include \"sock_utils.h\"\n#include \"libwebsockets.h\"\n\n#define MAX_ZEDBOARD_PAYLOAD 4096\n\nstruct per_session_data_connectal {\n};\n\n#define WEB(P) ((struct per_session_data_connectal *)(P)->websock)\nstatic int connect_proceed;\nstatic int websock_trace ;//= 1;\nstatic int\ncallback_connectal(struct libwebsocket_context *context,\n                   struct libwebsocket *wsi,\n                   enum libwebsocket_callback_reasons reason, void *user, void *in, size_t len)\n{\n    PortalInternal *pint = (PortalInternal *)libwebsocket_context_user(context);\n    switch (reason) {\n    case LWS_CALLBACK_CLIENT_ESTABLISHED:\n        connect_proceed = 1;\n    case LWS_CALLBACK_ESTABLISHED:\n        if (websock_trace)\n        fprintf(stderr, \"LWS/ESTABLISHED %d context %p pint %p wsi %p user %p in %p len %ld fd %d\\n\", reason, context, pint, wsi, user, in, (long)len, libwebsocket_get_socket_fd(wsi));\n        pint->websock = user;\n        pint->websock_wsi = wsi;\n        if (pint->poller)\n            addFdToPoller(pint->poller, libwebsocket_get_socket_fd(wsi));\n        else\n            pint->fpga_fd = libwebsocket_get_socket_fd(wsi);\n        break;\n    case LWS_CALLBACK_ADD_POLL_FD:\n        if (websock_trace)\n        fprintf(stderr, \"LWS_CALLBACK_ADD_POLL_FD %p wsi %p poller %p fd %d.\\n\", context, wsi, pint->poller, libwebsocket_get_socket_fd(wsi));\n        if (pint->poller)\n            addFdToPoller(pint->poller, libwebsocket_get_socket_fd(wsi));\n        else\n            pint->fpga_fd = libwebsocket_get_socket_fd(wsi);\n        break;\n    case LWS_CALLBACK_CLIENT_CONNECTION_ERROR:\n        fprintf(stderr, \"LWS_CALLBACK_CLIENT_CONNECTION_ERROR context %p wsi %p user %p in %p len %ld\\n\", context, wsi, user, in, (long)len);\n        pint->websock = user;\n        pint->websock_wsi = wsi;\n        break;\n    case LWS_CALLBACK_CLOSED:\n        fprintf(stderr, \"LWS_CALLBACK_CLOSED context %p pint %p\\n\", context, pint);\n        pint->websock = user;\n        pint->websock_wsi = wsi;\n        break;\n    case LWS_CALLBACK_RECEIVE:\n    case LWS_CALLBACK_CLIENT_RECEIVE: {\n        if (websock_trace)\n            fprintf(stderr, \"LWS_CALLBACK_RECEIVE context %p pint %p user %p len %ld\\n\", context, pint, user, (long)len);\n        if (pint->handler) {\n            pint->map_base[0] = len+1;\n            memcpy((void *)&pint->map_base[1], in, len);\n            pint->handler(pint, 0, 0);\n            memset((void *)pint->map_base, 0, 16);\n        }\n        break;\n        }\n    case LWS_CALLBACK_SERVER_NEW_CLIENT_INSTANTIATED:\n    case LWS_CALLBACK_SERVER_WRITEABLE:\n    case LWS_CALLBACK_CLIENT_WRITEABLE:\n    case LWS_CALLBACK_CLIENT_FILTER_PRE_ESTABLISH:\n    case LWS_CALLBACK_CLIENT_APPEND_HANDSHAKE_HEADER:\n    case LWS_CALLBACK_FILTER_NETWORK_CONNECTION:\n    case LWS_CALLBACK_FILTER_PROTOCOL_CONNECTION:\n    case LWS_CALLBACK_PROTOCOL_INIT:\n    case LWS_CALLBACK_WSI_CREATE:\n    case LWS_CALLBACK_WSI_DESTROY:\n    case LWS_CALLBACK_CLOSED_HTTP:\n    case LWS_CALLBACK_OPENSSL_LOAD_EXTRA_CLIENT_VERIFY_CERTS:\n    case LWS_CALLBACK_GET_THREAD_ID:\n    case LWS_CALLBACK_LOCK_POLL:\n    case LWS_CALLBACK_UNLOCK_POLL:\n    case LWS_CALLBACK_CHANGE_MODE_POLL_FD:\n    case LWS_CALLBACK_DEL_POLL_FD:\n        break;\n    default:\n        printf(\"[%s:%d] reason %d\\n\", __FUNCTION__, __LINE__, reason);\n        break;\n    }\n    return 0;\n}\n\nstatic int event_webSocket(struct PortalInternal *pint)\n{\n    libwebsocket_service((struct libwebsocket_context *)pint->websock_context, 1);\n}\n\n#define HANDLE(A) \\\nstatic struct libwebsocket_protocols protocols ## A[] = { \\\n    /* first protocol must always be HTTP handler */ \\\n    { \"connectal\" # A, callback_connectal, sizeof(struct per_session_data_connectal) }, { NULL, NULL, 0 } };\n\nHANDLE(0);  HANDLE(1);  HANDLE(2);  HANDLE(3);  HANDLE(4);  HANDLE(5);\nHANDLE(6);  HANDLE(7);  HANDLE(8);  HANDLE(9);  HANDLE(10); HANDLE(11);\nHANDLE(12); HANDLE(13); HANDLE(14); HANDLE(15);\n\n#define NHANDLE(A) protocols ## A\n\nstatic struct libwebsocket_protocols *protocols[] = {\n    NHANDLE(0),  NHANDLE(1),  NHANDLE(2),  NHANDLE(3),  NHANDLE(4),  NHANDLE(5),\n    NHANDLE(6),  NHANDLE(7),  NHANDLE(8),  NHANDLE(9),  NHANDLE(10), NHANDLE(11),\n    NHANDLE(12), NHANDLE(13), NHANDLE(14), NHANDLE(15) };\n\nstatic void get_context(PortalInternal *pint, int port)\n{\n    struct lws_context_creation_info info = {0};\n    pint->poller_register = 1;\n    info.port = port;\n    info.protocols = protocols[pint->fpga_number];\n    info.gid = -1;\n    info.uid = -1;\n    info.user = pint;\n    pint->websock_context = libwebsocket_create_context(&info);\n    if (!pint->websock_context) {\n        lwsl_err(\"libwebsocket init failed\\n\");\n        exit(-1);\n    }\n}\n\nstatic int init_webSocketInit(struct PortalInternal *pint, void *aparam)\n{\n    PortalSocketParam *param = (PortalSocketParam *)aparam;\n    unsigned short port = 5050;\n    char buffer[INET6_ADDRSTRLEN];\n\n    pint->map_base = (volatile unsigned int *)malloc(4+MAX_ZEDBOARD_PAYLOAD+1);\n    memset((void *)pint->map_base, 0, 4+MAX_ZEDBOARD_PAYLOAD+1); // for valgrind\n    if (param->addr->ai_family == AF_INET) {\n        struct sockaddr_in *sa = (struct sockaddr_in *)param->addr->ai_addr;\n        port = htons(sa->sin_port);\n    } else if (param->addr->ai_family == AF_INET6) {\n        struct sockaddr_in6 *sa = (struct sockaddr_in6 *)param->addr->ai_addr;\n        port = htons(sa->sin6_port);\n    }\n    if (websock_trace)\n    fprintf(stderr, \"[%s:%d] connecting addr=%p ai_family=%d port %d\\n\", __FUNCTION__, __LINE__, param->addr->ai_addr, param->addr->ai_family, port);\n    get_context(pint, CONTEXT_PORT_NO_LISTEN);\n    int err=getnameinfo(param->addr->ai_addr, param->addr->ai_addrlen, buffer, sizeof(buffer),\n        0, 0, NI_NUMERICHOST);\n    connect_proceed = 0;\n    struct libwebsocket *lsock = libwebsocket_client_connect((libwebsocket_context *)pint->websock_context, buffer, port, 0,\n         \"/\", \"hostname\", \"originname\", protocols[pint->fpga_number][0].name, -1);\n    if (websock_trace)\n        printf(\"[%s:%d] pint %p = %p address %s name %s\\n\", __FUNCTION__, __LINE__, pint, lsock, buffer, protocols[pint->fpga_number][0].name);\n    while(!connect_proceed)\n        event_webSocket(pint);\n    return 0;\n}\n\nstatic int init_webSocketResp(struct PortalInternal *pint, void *aparam)\n{\n    PortalSocketParam *param = (PortalSocketParam *)aparam;\n    unsigned short port = 5050;\n\n    pint->map_base = (volatile unsigned int *)malloc(4+MAX_ZEDBOARD_PAYLOAD+1);\n    memset((void *)pint->map_base, 0, 4+MAX_ZEDBOARD_PAYLOAD+1); // for valgrind\n    if (param->addr->ai_family == AF_INET) {\n        struct sockaddr_in *sa = (struct sockaddr_in *)param->addr->ai_addr;\n        port = htons(sa->sin_port);\n    } else if (param->addr->ai_family == AF_INET6) {\n        struct sockaddr_in6 *sa = (struct sockaddr_in6 *)param->addr->ai_addr;\n        port = htons(sa->sin6_port);\n    }\n    if (websock_trace)\n    fprintf(stderr, \"[%s:%d] listening on addr=%p ai_family=%d port %d\\n\", __FUNCTION__, __LINE__, param->addr->ai_addr, param->addr->ai_family, port);\n    get_context(pint, port);\n    if (websock_trace)\n    fprintf(stderr, \"[%s:%d] pint %p context %p fd %d.\\n\", __FUNCTION__, __LINE__, pint, pint->websock_context, pint->fpga_fd);\n    return 0;\n}\nstatic void send_webSocket(struct PortalInternal *pint, volatile unsigned int *data, unsigned int hdr, int sendFd)\n{\n    int n;\n    uint32_t len = (hdr & 0xffff);\n    unsigned char txbuf[LWS_SEND_BUFFER_PRE_PADDING + MAX_ZEDBOARD_PAYLOAD + LWS_SEND_BUFFER_POST_PADDING];\n    if (websock_trace)\n        printf(\"[%s:%d] pint %p websock %p len %d data %s\\n\", __FUNCTION__, __LINE__, pint, WEB(pint), len, (char*)data);\n    memcpy(&txbuf[LWS_SEND_BUFFER_PRE_PADDING], (void *)data, len);\n    n = libwebsocket_write((libwebsocket *)pint->websock_wsi, &txbuf[LWS_SEND_BUFFER_PRE_PADDING], len, LWS_WRITE_TEXT);\n}\n\nPortalTransportFunctions transportWebSocketInit = {\n    init_webSocketInit, read_portal_memory, write_portal_memory, write_fd_portal_memory, mapchannel_socket, mapchannel_req_generic,\n    send_webSocket, recv_portal_null, busy_portal_null, enableint_portal_null, event_webSocket, notfull_null};\n\nPortalTransportFunctions transportWebSocketResp = {\n    init_webSocketResp, read_portal_memory, write_portal_memory, write_fd_portal_memory, mapchannel_socket, mapchannel_req_generic,\n    send_webSocket, recv_portal_null, busy_portal_null, enableint_portal_null, event_webSocket, notfull_null};\n"
  },
  {
    "path": "cpp/transportXsim.c",
    "content": "/* Copyright (c) 2014 Quanta Research Cambridge, Inc\n *\n * Permission is hereby granted, free of charge, to any person obtaining a\n * copy of this software and associated documentation files (the \"Software\"),\n * to deal in the Software without restriction, including without limitation\n * the rights to use, copy, modify, merge, publish, distribute, sublicense,\n * and/or sell copies of the Software, and to permit persons to whom the\n * Software is furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n * DEALINGS IN THE SOFTWARE.\n */\n#include \"GeneratedTypes.h\"\n#include <sys/types.h>\n#include <unistd.h>\n\nstatic int trace_xsim; // = 1;\n\nstatic uint32_t indicationIndex[16];\nstatic uint32_t indicationHdr[16];\nstatic PortalInternal mcommon, indPortal, reqPortal;\n\nstatic int indMsgSource (PortalInternal *pint, const uint32_t portal, const uint32_t data )\n{\n    PortalInternal *clientp = pint->mux_ports[portal].pint;\n    uint32_t index = indicationIndex[portal]++;\n    if (index == 0)\n\tindicationHdr[portal] = data;\n    uint32_t hdr = indicationHdr[portal];\n    if (clientp)\n\tclientp->map_base[index] = data;\n    uint32_t numwords = hdr & 0xFF;\n    if (trace_xsim)\n\tfprintf(stderr, \"pid %d %s: portal=%d data=%x hdr=%08x numwords=%d pid=%d\\n\", getpid(), __FUNCTION__, portal, data, hdr, numwords, getpid());\n\n    if (indicationIndex[portal] >= numwords) {\n        uint32_t methodId = (hdr >> 16) & 0xFF;\n\tif (trace_xsim)\n            fprintf(stderr, \"pid %d %s: clientp=%p srcbeats=%d methodwords=%d methodId=%d hdr=%08x\\n\",\n\t\t    getpid(), __FUNCTION__, clientp, indicationIndex[portal], numwords, methodId, hdr);\n        if (clientp && clientp->handler)\n            clientp->handler(clientp, methodId, 0);\n        indicationIndex[portal] = 0;\n    }\n    return 0;\n}\n\nstatic XsimMsgIndicationCb indHandlers = {portal_disconnect, indMsgSource};\n\nstatic int init_xsim(struct PortalInternal *pint, void *init_param)\n{\n    initPortalHardware();\nprintf(\"[%s:%d]\\n\", __FUNCTION__, __LINE__);\n//sleep(10);\n    if (!indPortal.mux_ports) {\n        init_portal_internal(&mcommon, 0, 0, portal_mux_handler, NULL,\n            &transportSocketInit, NULL, NULL, sizeof(uint32_t)); \n        PortalMuxParam param = {};\n        param.pint = &mcommon;\n        init_portal_internal(&indPortal, XsimIfcNames_XsimMsgIndication, 0,\n            XsimMsgIndication_handleMessage, &indHandlers, &transportMux, &param, NULL, XsimMsgIndication_reqinfo);\n        init_portal_internal(&reqPortal, XsimIfcNames_XsimMsgRequest, 0,\n            NULL, NULL, &transportMux, &param, NULL, XsimMsgRequest_reqinfo);\n        indPortal.mux_ports_number = 16;\n        indPortal.mux_ports = (PortalMuxHandler *)malloc(indPortal.mux_ports_number * sizeof(PortalMuxHandler));\n    }\n    //pint->fpga_number = indPortal->fpgaNumber(pint->fpga_number);\n    pint->map_base = ((volatile unsigned int*)malloc(REQINFO_SIZE(pint->reqinfo) + sizeof(uint32_t))) + 1;\n    memset((void *)(pint->map_base-1), 0, REQINFO_SIZE(pint->reqinfo) + sizeof(uint32_t));  // for valgrind\n    indPortal.mux_ports[pint->fpga_number].pint = pint;  // FIXME: depends on ids < 16\n    pint->fpga_fd = mcommon.client_fd[0];\n    return 0;\n}\n\nvoid write_portal_xsim(PortalInternal *pint, volatile unsigned int **addr, unsigned int v)\n{\n    if (trace_xsim)\n        printf(\"%s %d sending data %d\\n\", __FUNCTION__, pint->fpga_number, v);\n    XsimMsgRequest_msgSink(&reqPortal, pint->fpga_number, v);\n}\nvoid write_fd_portal_xsim(PortalInternal *pint, volatile unsigned int **addr, unsigned int v)\n{\n    //if (trace_xsim)\n        printf(\"%s: %d sending fd %d\\n\", __FUNCTION__, pint->fpga_number, v);\n    XsimMsgRequest_msgSinkFd(&reqPortal, pint->fpga_number, v);\n}\n\nstatic volatile unsigned int *mapchannel_req_xsim(struct PortalInternal *pint, unsigned int v, unsigned int size)\n{\n    if (trace_xsim)\n        printf(\"%s: %d sending header %x\\n\", __FUNCTION__, pint->fpga_number, (v << 16) | size);\n    XsimMsgRequest_msgSink(&reqPortal, pint->fpga_number, (v << 16) | size);\n    return pint->transport->mapchannelInd(pint, v);\n}\n\nint event_xsim(struct PortalInternal *pint)\n{\n    mcommon.transport->event(&mcommon);\n    return -1;\n}\n\nPortalTransportFunctions transportXsim = {\n    init_xsim, read_portal_memory, write_portal_xsim, write_fd_portal_xsim, mapchannel_socket, mapchannel_req_xsim,\n    send_portal_null, recv_portal_null, busy_portal_null, enableint_portal_null, event_xsim, notfull_null};\n\n"
  },
  {
    "path": "cpp/verilatortop.cpp",
    "content": "#include \"vlsim.h\"\n#include \"verilated.h\"\n#include <unistd.h>\n#include <XsimTop.h>\n#include <ConnectalProjectConfig.h>\n\n#ifdef BSV_POSITIVE_RESET\n  #define BSV_RESET_VALUE 1\n  #define BSV_RESET_EDGE 0 //posedge\n#else\n  #define BSV_RESET_VALUE 0\n  #define BSV_RESET_EDGE 1 //negedge\n#endif\n\n#if VM_TRACE\n# include <verilated_vcd_c.h>   // Trace file format header\n#endif\n\nbool dump_vcd = false;\nconst char *vcd_file_name = \"dump.vcd\";\n\nvoid parseArgs(int argc, char **argv)\n{\n    signed char opt;\n    while ((opt = getopt(argc, argv, \"ht:\")) != -1) {\n      switch (opt) {\n      case 't':\n\tdump_vcd = true;\n\tvcd_file_name = optarg;\n\tbreak;\n      }\n    }\n}\n\nvluint64_t main_time = 0;\nvluint64_t derived_time = 0;\nint main(int argc, char **argv, char **env)\n{\n  fprintf(stderr, \"vlsim::main\\n\");\n  Verilated::commandArgs(argc, argv);\n  parseArgs(argc, argv);\n\n  vlsim* top = new vlsim;\n\n  fprintf(stderr, \"vlsim calling dpi_init\\n\");\n  dpi_init();\n\n#if VM_TRACE                    // If verilator was invoked with --trace\n  VerilatedVcdC* tfp = 0;\n  if (dump_vcd) {\n        Verilated::traceEverOn(true);       // Verilator must compute traced signals\n\tVL_PRINTF(\"Enabling vcd waves to %s\\n\", vcd_file_name);\n\ttfp = new VerilatedVcdC;\n\ttop->trace (tfp, 4);       // Trace 4 levels of hierarchy\n\ttfp->open (vcd_file_name); // Open the dump file\n  }\n#endif\n\n  fprintf(stderr, \"starting simulation\\n\");\n  top->CLK = 0;\n  top->RST_N = BSV_RESET_VALUE;\n  top->CLK_derivedClock = 0;\n  top->CLK_sys_clk = 0;\n  top->RST_N_derivedReset = BSV_RESET_VALUE;\n  while (!Verilated::gotFinish()) {\n    if (main_time >= 10) {\n      if ((top->CLK == BSV_RESET_EDGE) && (top->RST_N == BSV_RESET_VALUE)) {\n\tfprintf(stderr, \"time=%ld leaving reset new value %d\\n\", (long)main_time, !BSV_RESET_VALUE);\n\ttop->RST_N = !BSV_RESET_VALUE;\n      }\n    }\n    if (derived_time >= 10) {\n      if ((top->CLK_derivedClock == BSV_RESET_EDGE) && (top->RST_N_derivedReset == BSV_RESET_VALUE)) {\n\tfprintf(stderr, \"time=%ld deasserting derivedReset new value %d\\n\", (long)main_time, !BSV_RESET_VALUE);\n\ttop->RST_N_derivedReset = !BSV_RESET_VALUE;\n      }\n    }\n\n    if (dpi_cycle())\n      vl_finish(__FILE__, __LINE__, \"vlsim\");\n\n    top->CLK = main_time % 2;\n    top->CLK_derivedClock = derived_time % 2;\n    top->CLK_sys_clk = main_time % 2;\n    top->eval();\n\n#if VM_TRACE\n    if (tfp) tfp->dump (main_time); // Create waveform trace for this timestamp                                                                \n#endif\n\n    main_time++;\n    if (main_time & 1)\n      derived_time++;\n  }\n  top->final();\n#if VM_TRACE\n  if (tfp) tfp->close();\n#endif                                                                                                                                             \n\n  delete top;\n  exit(0);\n}\n"
  },
  {
    "path": "debian/changelog",
    "content": "connectal (15.08.4-1precise1) precise; urgency=medium\n\n  * Fixed DMA write path through MemSlaveEngine post Altera merge\n\n -- Jamey Hicks <jamey.hicks@gmail.com>  Fri, 07 Aug 2015 14:42:17 -0400\n\nconnectal (15.08.3-1precise1) precise; urgency=medium\n\n  * Fixed python location\n  * 15.08.3\n\n -- Jamey Hicks <jamey.hicks@gmail.com>  Tue, 04 Aug 2015 15:46:36 -0400\n\nconnectal (15.08.2-1precise1) precise; urgency=medium\n\n  * Another hugetlb page size change.\n  * 15.08.2\n\n -- Jamey Hicks <jamey.hicks@gmail.com>  Tue, 04 Aug 2015 15:31:41 -0400\n\nconnectal (15.08.1-1precise1) precise; urgency=medium\n\n  * Added hugetlb page size.\n  * Version 15.08.1\n\n -- Jamey Hicks <jamey.hicks@gmail.com>  Mon, 03 Aug 2015 08:11:10 -0400\n\nconnectal (15.07.4-1precise1) precise; urgency=medium\n\n  * Driver fixes.\n\n -- Jamey Hicks <jamey.hicks@gmail.com>  Fri, 10 Jul 2015 09:48:19 -0400\n\nconnectal (15.07.3-1precise1) precise; urgency=medium\n\n  * One more PCIE3 fix.\n\n -- Jamey Hicks <jamey.hicks@gmail.com>  Mon, 06 Jul 2015 10:02:28 -0400\n\nconnectal (15.07.2-1precise1) precise; urgency=medium\n\n  * 15.07.2, fixed PCIE3 conditionalization\n\n -- Jamey Hicks <jamey.hicks@gmail.com>  Mon, 06 Jul 2015 09:31:16 -0400\n\nconnectal (15.07.1-1precise1) precise; urgency=medium\n\n  * v15.07.1\n\n -- Jamey Hicks <jamey.hicks@gmail.com>  Mon, 06 Jul 2015 09:04:37 -0400\n\nconnectal (15.06.3-1precise1) precise; urgency=medium\n\n  * v15.06.3\n\n -- Jamey Hicks <jamey.hicks@gmail.com>  Tue, 09 Jun 2015 14:47:44 -0400\n\nconnectal (15.06.2-1precise1) precise; urgency=medium\n\n  * 15.06.2\n\n -- Jamey Hicks <jamey.hicks@gmail.com>  Thu, 04 Jun 2015 09:21:24 -0400\n\nconnectal (15.06.1-3precise3) precise; urgency=medium\n\n  * updated dkms build\n\n -- Jamey Hicks <jamey.hicks@gmail.com>  Mon, 01 Jun 2015 12:47:00 -0400\n\nconnectal (15.06.1-2precise2) precise; urgency=medium\n\n  * fixing dkms\n\n -- Jamey Hicks <jamey.hicks@gmail.com>  Mon, 01 Jun 2015 11:09:43 -0400\n\nconnectal (15.06.1-1precise1) precise; urgency=medium\n\n  * 15.06.1\n\n -- Jamey Hicks <jamey.hicks@gmail.com>  Mon, 01 Jun 2015 10:34:18 -0400\n\nconnectal (15.05.2-1precise1) precise; urgency=medium\n\n  * 15.05.2\n\n -- Jamey Hicks <jamey.hicks@gmail.com>  Tue, 26 May 2015 09:24:41 -0400\n\nconnectal (15.05.1-1precise1) precise; urgency=medium\n\n  * Updated to 15.05.1\n\n -- Jamey Hicks <jamey.hicks@gmail.com>  Wed, 20 May 2015 15:30:20 -0400\n\nconnectal (15.04.4-2precise2) precise; urgency=medium\n\n  * Fixed sed DRIVER_VERSION and DEV_VERSION for DKMS\n\n -- Jamey Hicks <jamey.hicks@gmail.com>  Wed, 29 Apr 2015 12:34:38 -0400\n\nconnectal (15.04.4-1precise1) precise; urgency=medium\n\n  * 15.04.4: fixes rmmod pcieportal, etc.\n\n -- Jamey Hicks <jamey.hicks@gmail.com>  Tue, 28 Apr 2015 16:07:16 -0400\n\nconnectal (15.04.3-1precise1) precise; urgency=medium\n\n  * 15.04.3: fixed make pciedrivers\n\n -- Jamey Hicks <jamey.hicks@gmail.com>  Mon, 27 Apr 2015 11:52:46 -0400\n\nconnectal (15.04.2-1precise1) precise; urgency=medium\n\n  * Fixing DKMS sources\n\n -- Jamey Hicks <jamey.hicks@gmail.com>  Mon, 27 Apr 2015 11:06:34 -0400\n\nconnectal (15.04.1-1precise1) precise; urgency=medium\n\n  * 15.04.1\n\n -- Jamey Hicks <jamey.hicks@gmail.com>  Fri, 24 Apr 2015 09:41:52 -0400\n\nconnectal (15.03.12-1precise1) precise; urgency=medium\n\n  * 15.03.12\n\n -- Jamey Hicks <jamey.hicks@gmail.com>  Wed, 01 Apr 2015 16:58:40 -0400\n\nconnectal (15.03.11-1precise1) precise; urgency=medium\n\n  * 15.03.11\n\n -- Jamey Hicks <jamey.hicks@gmail.com>  Mon, 30 Mar 2015 12:59:29 -0400\n\nconnectal (15.03.10-1precise1) precise; urgency=medium\n\n  * 15.03.10\n\n -- Jamey Hicks <jamey.hicks@gmail.com>  Wed, 25 Mar 2015 15:20:34 -0400\n\nconnectal (15.03.9-1precise1ubuntu1) precise; urgency=medium\n\n  * 15.03.9\n\n -- Jamey Hicks <jamey.hicks@gmail.com>  Tue, 24 Mar 2015 13:21:43 -0400\n\nconnectal (15.03.8-1precise1) precise; urgency=medium\n\n  * 15.03.8\n\n -- Jamey Hicks <jamey.hicks@gmail.com>  Mon, 23 Mar 2015 09:12:55 -0400\n\nconnectal (15.03.7-1precise1) precise; urgency=medium\n\n  * 15.03.7: reverts interface to mkMemServer, plus other fixes\n\n -- Jamey Hicks <jamey.hicks@gmail.com>  Fri, 20 Mar 2015 11:47:05 -0400\n\nconnectal (15.03.6-1precise1) precise; urgency=medium\n\n  * 15.03.6: a couple of driver fixes\n\n -- Jamey Hicks <jamey.hicks@gmail.com>  Thu, 19 Mar 2015 17:04:55 -0400\n\nconnectal (15.03.5-1precise1) precise; urgency=medium\n\n  * 15.03.5\n\n -- Jamey Hicks <jamey.hicks@gmail.com>  Thu, 19 Mar 2015 16:32:38 -0400\n\nconnectal (15.03.4-1precise1) precise; urgency=medium\n\n  * Updated to 15.03.4\n\n -- Jamey Hicks <jamey.hicks@gmail.com>  Wed, 18 Mar 2015 12:51:41 -0400\n\nconnectal (15.03.2-1precise1) precise; urgency=medium\n\n  * Updated to 15.03.2\n\n -- Jamey Hicks <jamey.hicks@gmail.com>  Mon, 09 Mar 2015 15:21:08 -0400\n\nconnectal (15.03.1-1precise1) precise; urgency=medium\n\n  * Updated to 15.03.1\n\n -- Jamey Hicks <jamey.hicks@gmail.com>  Wed, 04 Mar 2015 15:30:27 -0500\n\nconnectal (15.02.5-1precise1) precise; urgency=medium\n\n  * Updated to 15.02.5\n\n -- Jamey Hicks <jamey.hicks@gmail.com>  Mon, 16 Feb 2015 20:37:45 -0500\n\nconnectal (15.02.4-1precise1) precise; urgency=medium\n\n  * Updated to 15.02.4\n\n -- Jamey Hicks <jamey.hicks@gmail.com>  Sun, 15 Feb 2015 20:37:45 -0500\n\nconnectal (15.02.3-1precise1) precise; urgency=medium\n\n  * Updated to 15.02.3\n\n -- Jamey Hicks <jamey.hicks@gmail.com>  Wed, 11 Feb 2015 11:48:40 -0500\n\nconnectal (15.02.2-2precise2) precise; urgency=medium\n\n  * For Trusty\n\n -- Jamey Hicks <jamey.hicks@gmail.com>  Tue, 10 Feb 2015 10:33:22 -0500\n\nconnectal (15.02.2-1precise1) precise; urgency=medium\n\n  * Fixed include string.h for zynqdrivers\n\n -- Jamey Hicks <jamey.hicks@gmail.com>  Tue, 10 Feb 2015 10:09:21 -0500\n\nconnectal (15.02.1-1precise3) precise; urgency=medium\n\n  * Updated to 15.02.1\n\n -- Jamey Hicks <jamey.hicks@gmail.com>  Tue, 10 Feb 2015 09:53:44 -0500\n\nconnectal (14.12.3-4precise1) precise; urgency=medium\n\n  * Second try to add pciescan\n\n -- Jamey Hicks <jamey.hicks@gmail.com>  Wed, 10 Dec 2014 08:22:10 -0500\n\nconnectal (14.12.3-3precise1) precise; urgency=medium\n\n  * Added dependence on pciescan\n\n -- Jamey Hicks <jamey.hicks@gmail.com>  Wed, 10 Dec 2014 08:03:00 -0500\n\nconnectal (14.12.3-2precise1) precise; urgency=medium\n\n  * Added support for setting derivedClock frequency\n\n -- Jamey Hicks <jamey.hicks@gmail.com>  Fri, 05 Dec 2014 16:24:47 -0500\n\nconnectal (14.12.2-4precise1) precise; urgency=medium\n\n  * Fix include paths for dkms\n\n -- Jamey Hicks <jamey.hicks@gmail.com>  Thu, 04 Dec 2014 13:16:48 -0500\n\nconnectal (14.12.2-2precise1) precise; urgency=medium\n\n  * Bump kernel version to fix DKMS error\n\n -- Jamey Hicks <jamey.hicks@gmail.com>  Thu, 04 Dec 2014 12:59:07 -0500\n\nconnectal (14.12.2-1precise1) precise; urgency=medium\n\n  * Removed zynqdrivers build and install until I find the cross arm toolchain for precise\n\n -- Jamey Hicks <jamey.hicks@gmail.com>  Thu, 04 Dec 2014 12:37:57 -0500\n\nconnectal (14.12.2-1precise1) precise; urgency=medium\n\n  * Fixed Vector compilation in C\n\n -- Jamey Hicks <jamey.hicks@gmail.com>  Tue, 02 Dec 2014 09:40:36 -0500\n\nconnectal (14.12.1-1precise1) precise; urgency=medium\n\n  * Added support for Vector in portal interfaces.\n\n -- Jamey Hicks <jamey.hicks@gmail.com>  Mon, 01 Dec 2014 11:48:25 -0500\n\nconnectal (14.11.6-2precise3) precise; urgency=low\n\n  * Tweak install of pcieflat\n\n -- Jamey Hicks <jamey.hicks@gmail.com>  Mon, 24 Nov 2014 16:55:21 -0500\n\nconnectal (14.11.6-1precise1) precise; urgency=low\n\n  * Updated to 14.11.6\n\n -- Jamey Hicks <jamey.hicks@gmail.com>  Mon, 24 Nov 2014 15:54:34 -0500\n\nconnectal (14.11.5-1precise1) precise; urgency=low\n\n  * Updated to 14.11.5\n\n -- Jamey Hicks <jamey.hicks@gmail.com>  Tue, 18 Nov 2014 08:43:29 -0500\n\nconnectal (14.11.4-1precise1) precise; urgency=low\n\n  * Updated to 14.11.4\n\n -- Jamey Hicks <jamey.hicks@gmail.com>  Mon, 17 Nov 2014 12:00:21 -0500\n\nconnectal (14.11.3-2precise2) precise; urgency=low\n\n  * Updated to 14.11.3\n\n -- Jamey Hicks <jamey.hicks@gmail.com>  Fri, 14 Nov 2014 11:38:22 -0500\n\nconnectal (14.11.2-1precise1) precise; urgency=low\n\n  * Update to 14.11.2\n\n -- Jamey Hicks <jamey.hicks@gmail.com>  Fri, 07 Nov 2014 09:07:26 -0500\n\nconnectal (14.11.1-2precise1) precise; urgency=low\n\n  * Update install-dkms\n\n -- Jamey Hicks <jamey.hicks@gmail.com>  Thu, 06 Nov 2014 13:03:40 -0500\n\nconnectal (14.11.1-1precise1) precise; urgency=low\n\n  * Updated to connectal 14.11.1\n\n -- Jamey Hicks <jamey.hicks@gmail.com>  Thu, 06 Nov 2014 11:35:05 -0500\n\nconnectal (14.10.2-7precise4) precise; urgency=medium\n\n  * Specify CROSS_COMPILE and add to arm-linux-gnueabi-gcc to Build-Depends\n\n -- Jamey Hicks <jamey.hicks@gmail.com>  Mon, 27 Oct 2014 08:27:24 -0400\n\nconnectal (14.10.2-7precise2) precise; urgency=medium\n\n  * Specify driver version\n\n -- Jamey Hicks <jamey.hicks@gmail.com>  Sat, 25 Oct 2014 14:34:22 -0400\n\nconnectal (14.10.2-6precise1) precise; urgency=medium\n\n  * Added the build depdences on zynqdrivers and zynqdrivers-install\n\n -- Jamey Hicks <jamey.hicks@gmail.com>  Fri, 24 Oct 2014 16:19:17 -0400\n\nconnectal (14.10.2-5precise1) precise; urgency=medium\n\n  * Build zynqdrivers and package in connectal-zynqdrivers\n\n -- Jamey Hicks <jamey.hicks@gmail.com>  Fri, 24 Oct 2014 13:23:21 -0400\n\nconnectal (14.10.2-4precise1) precise; urgency=medium\n\n  * Depend on fpgamake, buildcache, and fpgajtag\n\n -- Jamey Hicks <jamey.hicks@gmail.com>  Thu, 23 Oct 2014 14:09:00 -0400\n\nconnectal (14.10.2-3precise1) precise; urgency=medium\n\n  * Fix DKMS install\n\n -- Jamey Hicks <jamey.hicks@gmail.com>  Thu, 23 Oct 2014 12:26:54 -0400\n\nconnectal (14.10.2-2precise1) precise; urgency=high\n\n  * Depends on vim for xxd\n\n -- Jamey Hicks <jamey.hicks@gmail.com>  Thu, 23 Oct 2014 11:18:06 -0400\n\nconnectal (14.10.2-1precise1) precise; urgency=high\n\n  * Updated to 14.10.2\n\n -- Jamey Hicks <jamey.hicks@gmail.com>  Thu, 23 Oct 2014 11:15:16 -0400\n\nconnectal (14.10.01-5precise1) precise; urgency=low\n\n  * DKMS\n\n -- Jamey Hicks <jamey.hicks@gmail.com>  Thu, 23 Oct 2014 09:09:02 -0400\n\nconnectal (14.10.01-4precise2) precise; urgency=low\n\n  * Do not build kernel modules\n\n -- Jamey Hicks <jamey.hicks@gmail.com>  Wed, 22 Oct 2014 17:43:44 -0400\n\nconnectal (14.10.01-3precise1) precise; urgency=low\n\n  * Depends on python-ply\n\n -- Jamey Hicks <jamey.hicks@gmail.com>  Wed, 22 Oct 2014 17:29:22 -0400\n\nconnectal (14.10.01-2precise2) precise; urgency=low\n\n  * Include the source tarball\n\n -- Jamey Hicks <jamey.hicks@gmail.com>  Wed, 22 Oct 2014 08:11:22 -0400\n\nconnectal (14.10.01-2precise1) precise; urgency=low\n\n  * Missed some files\n\n -- Jamey Hicks <jamey.hicks@gmail.com>  Tue, 21 Oct 2014 16:44:23 -0400\n\nconnectal (14.10.01-1precise1) precise; urgency=low\n\n  * Initial release\n\n -- Jamey Hicks <jamey.hicks@gmail.com>  Fri, 17 Oct 2014 17:10:47 -0400\n"
  },
  {
    "path": "debian/compat",
    "content": "8\n"
  },
  {
    "path": "debian/connectal-doc.docs",
    "content": "#DOCS#\n"
  },
  {
    "path": "debian/connectal-doc.install",
    "content": "#DOCS#\n"
  },
  {
    "path": "debian/connectal-zynqdrivers.install",
    "content": "/usr/share/connectal-zynqdrivers/*.ko\n"
  },
  {
    "path": "debian/connectal.dkms",
    "content": "drivers/pcieportal/dkms.conf.out\n"
  },
  {
    "path": "debian/connectal.install",
    "content": "/usr/bin/pcieflat\n/usr/share/connectal\n/usr/src/\n"
  },
  {
    "path": "debian/connectal.udev",
    "content": "# UDev rules for setting up Bluespec emulation device drivers\n\nACTION==\"add\",SUBSYSTEM==\"pci\",ATTR{vendor}==\"0x1be7\", ATTR{device}=\"0xb100\", RUN+=\"/sbin/modprobe -ba pcieportal portalmem\"\nKERNEL==\"portal*\",MODE=\"666\"\nKERNEL==\"portalmem\",MODE=\"666\"\nKERNEL==\"connectal\",MODE=\"666\"\n"
  },
  {
    "path": "debian/control",
    "content": "Source: connectal\nSection: devel\nPriority: extra\nMaintainer: Jamey Hicks <jamey.hicks@gmail.com>\nBuild-Depends: debhelper (>= 8.0.0), python3 (>= 3.7), python3-ply, python3-support (>= 0.90), dkms\nStandards-Version: 3.9.2\nHomepage: https://github.com/cambridgehackers/connectal\n#Vcs-Git: git://git.debian.org/collab-maint/connectal.git\n#Vcs-Browser: http://git.debian.org/?p=collab-maint/connectal.git;a=summary\n\nPackage: connectal\nArchitecture: any\nDepends: ${shlibs:Depends}, ${misc:Depends}, python3 (>= 3.7), python3-ply, python3-gmpy, python3-netifaces, python3-gflags, python3-support (>= 0.90), dkms, fpgamake, buildcache, fpgajtag, pciescan, gcc, g++, libfontconfig1, libxft2\nDescription: Software-driven hardware development framework\n Connectal provides a hardware-software interface for applications\n split between user mode code and custom hardware in an FPGA. Portal\n can automatically build the software and hardware glue for a message\n based interface and also provides for configuring and using shared\n memory between applications and hardware. Communications between\n hardware and software are provided by a bidirectional flow of events\n and regions of memory shared between hardware and software. Events\n from software to hardware are called requests and events from\n hardware to software are called indications, but in fact they are\n symmetric.\n\nPackage: connectal-doc\nSection: doc\nArchitecture: all\nDescription: documentation for connectal\n More of the same description\n"
  },
  {
    "path": "debian/copyright",
    "content": "Format: http://dep.debian.net/deps/dep5\nUpstream-Name: connectal\nSource: <https://github.com/cambridgehackers/connectal>\n\nFiles: *\nCopyright: 2012 Nokia, Inc.\n           2013-2014 Quanta Research Cambridge\nLicense: MIT\n Permission is hereby granted, free of charge, to any person\n obtaining a copy of this software and associated documentation\n files (the \"Software\"), to deal in the Software without\n restriction, including without limitation the rights to use, copy,\n modify, merge, publish, distribute, sublicense, and/or sell copies\n of the Software, and to permit persons to whom the Software is\n furnished to do so, subject to the following conditions:\n\n The above copyright notice and this permission notice shall be\n included in all copies or substantial portions of the Software.\n\n THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n SOFTWARE.\n .\n\n\n"
  },
  {
    "path": "debian/docs",
    "content": "README.md\n"
  },
  {
    "path": "debian/rules",
    "content": "#!/usr/bin/make -f\n# -*- makefile -*-\n# Sample debian/rules that uses debhelper.\n#\n# This file was originally written by Joey Hess and Craig Small.\n# As a special exception, when this file is copied by dh-make into a\n# dh-make output file, you may use that output file without restriction.\n# This special exception was added by Craig Small in version 0.37 of dh-make.\n#\n# Modified to make a template file for a multi-binary package with separated\n# build-arch and build-indep targets  by Bill Allombert 2001\n\n# Uncomment this to turn on verbose mode.\n#export DH_VERBOSE=1\n\n# This has to be exported to make some magic below work.\nexport DH_OPTIONS\n\n\n%:\n\tdh $@ --with dkms\n"
  },
  {
    "path": "doc/Makefile",
    "content": "\n\nall:\n\tmake -C library html latexpdf\n"
  },
  {
    "path": "doc/ReadmePartialReconfiguration.md",
    "content": "CONNECTAL Support for Partial Reconfiguration\n=========================================\n\nCONNECTAL supports partial reconfiguration on pcie-based platforms (kc705\nand vc707). There's not enough static logic on the zedboard to make\nthis worthwhile at the moment.\n\nRun connectalgen as usual to create the project directory.\n\nCreate proxies, wrappers, scripts, and Makefiles:\n\n    cd examples/echo\n    connectalgen -Bkc705 -p kc705 -x mkPcieTop -s2h Say -h2s Say -s test.cpp -t ../../bsv/StdPcieTop.bsv  Say.bsv\n\nCompile the full bitstream:\n\n    cd kc705\n    make verilog\n    make partial ## generates full and partial bitstreams\n    make program ## loads the full bitstream\n\nNow reboot to configure the PCIe endpoint\n\n    sudo shutdown -r now\n\nNow you can edit the source code, recompile, and generate a new partial bitstream:\n\n    ## edit the BSV\n    make verilog\n    make partial\n\nLoad the partial bitstream:\n\n    make reprogram\n\nThis also calls \"connectalutil reset /dev/fpga0\" to reset the portals in the design. No reboot required.\n\n"
  },
  {
    "path": "doc/SmithWaterman.md",
    "content": "## Smith-Waterman\n\nL. Stewart <stewart@qrclab.com> March 17, 2014\n\nSmith-Waterman is an algorithm for determining the best alignment of two strands of DNA.  It is a variant of dynamic programming, published in 1981.  For strands of lengths m and n, it runs in O(mn) space and O(mn) time and returns all alignments with the best score, according to weights for mismatches, insertions, and deletions.\n\nIn 1982, Gotoh found an O(mn) time but only O(shorter of m and n) space scheme that returns only a single instance of the best match.\n\nIn 1986, Altschul and Erickson published a version with \"affine gap costs.\"  The original Smith-Waterman had the same weight for each step in a run of inserts or deletes, but a model in which the first insert or delete costs more than adding to an existing run models biology more accurately.\n\nIn 1988, Miller, Webb, and Myers adapted a computer science algorithm by Hirshberg (1975) to the problem, leading O(smaller of m or n) space.\n\nLimiting space usage is fairly important for FPGA implementations, since while FGPAs or ASICs have a lot of internal memory units, they aren't very big each.  In order to achieve a big speedup on sequencing, we have to have a lot of parallelism.  Each instance can have its own memory, but not very much of it.\n\nFor the Hirschberg algorithm, see connectal/examples/maxcommonsubseq.\n\n\nHow it works\n\nThe problem is to find the minimum cost of converting one string, A, into another one, B.  Three things can happen: a character can be deleted from string A, a character can be inserted into string A, and combination event, in which a character in string A is changed (delete combined with insert).\n\nParameters are needed: a substitution matrix that details the cost of converting a character to another (or itself), and a gap model, which expresses the cost of deleting or inserting a run of characters.\n\nThe simplest gap model has a fixed cost for every deletion or insertion, but an \"affine model\" better matches what happens in biology: there is a startup cost for a run of deletions or insertions, and a typically lower, cost for extending a run.\n\nCall the substitution matrix w(a, b)\n\n    def w(a, b): \n      if (a == b): \n        return 0.0 \n      else: \n        return 1.0\n\nIn other words, no cost to leave a character unchanged, and unit cost to change it.\n\nA typical gap model is\n\n    g = 2.0 h = 0.5\n\n    def gap(k): \n      return g + (k * h)\n\nThe magnitudes of these costs are irrelevant, only the relative costs matter.\n\nThe basic idea of Smith Waterman is dynamic programming. Suppose that\n\n    m = len(A) \n    n = len(B)\n\nDefine A_i to be the subsequence A[0]..A[i].\n\nLet's define C[i][j] as the minimum cost of a conversion from A_i to B_j.  D[i][j] as the minimum cost of a conversion from A_i to B_j such that A[i] is deleted (a suffix gap in A), and that I[i][j] is the minimum cost of conversion from A_i to B_j such that b[j] is inserted (into A).\n\nD and I are only necessary to handle the gap cost model - you have to know whether the best answer up to a point has a gap at the end or not, so you can apply the gap cost model to either extend a gap or open a new one.\n\nThe essence of dynamic programming is a recurrance that expresses that expresses matrix values as functions of \"earlier\" values.\n\n    C[i][j] = min ( \n      D[i][j], \n      I[i][j], \n      C[i-1][j-1] + w(a[i], b[j]))\n\n    D[i][j] = min( \n      D[i-1][j] + h, // extend an old gap \n      C[i-1][j] + g + h) // start a new gap\n\n\n    I[i][j] = min( \n      I[i][j-1] + h, // extend an old gap \n      C[i][j-1] + g + h) // start a new gap\n\nThe Gotoh version of Smith-Waterman does exactly this, building the full C, D, and I matrices.\n\nFrom inspection of the recurrance relations, it is clear that you don't need to save the full matrices, and the algorithm Gotohb keeps only two row vectors.  CC[j] represents conversion costs of A_i to B_j (for all j) and DD[j] represents conversion costs of A_i to B_j ending with a deletion, for all j.\n\nAll of the above follows the lines of Hirschberg's algorithms A and B for the maximum common subsequence problem.\n\nThe key insight in the Myers and Miller paper is that you can write a recursive version of Smith Waterman along the lines of Hirschberg's algorithm C.\n\n1 Choose a midpoint i in the A string.  \n2 Find j such that the best overall solution passes through C[i][j]\n3 Recursively solve the conversion of A_i to B_j and the solution of A_m-i to B_n-j, where A_m-i and B_n-j are the suffixes of A and B.\n\n\nStep 1 is straightforward, the best solution passes through A_i, although we don't know at what j.\n\nStep 2 uses Gotoh Algorithm B to find the cost of solutions which cross A_i for all values of j.\n\nThis is done in two parts.  The first half part is done in the forward direction by using GotohB(A_i, B_j). This produces vectors CC and DD as above.  Then GotohB(A*_m-i, B*_j) is run, where A* and B* are the reversed strings A and B. A*_m-i is the reversed suffix of A, from i+1 to the end. This produces vectors RR, the conversion from A*_m-i to B*_j for all j, and SS, the conversion costs from A*_i to B*_j ending with a delete.  The reverse solution finds costs for the suffixes of A and B\n\nThere are two cases.  In type 1 cases, the cost of the overall conversion that splits B at j is just CC[j] + RR[N-j].  This is minimized over j to find the best split point for string B.  In type 2 cases, the best solution for the prefix of B ends with a delete and the best solution for the suffix begins with a delete. In this case, we have to coalesce the deletions into a single gap.\n\nmin over j (CC[j] + RR[N-j], DD[j] + SS[N-j] -g)\n\nGiven the split points i and j, we can run step 3, to solve the prefix and suffix problems recursively.\n\nBelow the top level of the recursion, it may be necessary to coalesce gaps at either the beginning or end of the string, and for this reason, additional parameters are passed in to control this accounting.\n\n    def gotohc(A, B, tb, te): ...\n\nIn order to make the python version more like the eventual hardware version, we also pass in sa and sb, the starting indices in A and B, and m and n, the lengths of the active substrings in A and B.\n \n    def gotohc(A, B, sa, sb, m, n, tb, te): ...\n\nFor full details, see examples/smithwaterman/sw.py\n\n"
  },
  {
    "path": "doc/axi_tracing.md",
    "content": "\n## How to trace AXI bus transactions on the Zynq platform.\n\n### Preparation\n\n1. Connect a usb cable to either a linux box or Mac\n\n2. Install openocd\n      Linux: sudo apt-get install openocd\n\n      Mac using 'port': \n\n          sudo port install libftdi\n\n          sudo port install openocd\n\n      Mac using 'brew': \n\n\t  brew install libftdi\n\n\t  brew install openocd --enable-ft2232_libftdi\n\n      On Mac, if you get the message: 'unable to claim usb device. Make sure the default FTDI driver is not in use':\n\n          Please read: http://pylibftdi.readthedocs.org/en/latest/troubleshooting.html\n\n          Summarized here:\n\n              OS X Mavericks\n\n              OS X Mavericks includes kernel drivers which will reserve the FTDI device by default. This needs unloading before libftdi will be able to communicate with the device:\n\n              sudo kextunload -bundle-id com.apple.driver.AppleUSBFTDI\n\n              Similarly to reload it:\n\n              sudo kextload -bundle-id com.apple.driver.AppleUSBFTDI\n\n              OS X Mountain Lion and earlier\n\n              Whereas Mavericks includes an FTDI driver directly, earlier versions of OS X did not, and if this issue occurred it would typically as a result of installing some other program - for example the Arduino IDE.\n\n              As a result, the kernel module may have different names, but FTDIUSBSerialDriver.kext is the usual culprit. Unload the kernel driver as follows:\n\n              sudo kextunload /System/Library/Extensions/FTDIUSBSerialDriver.kext\n\n\n### Compile time\n\nIn the project makefile, add the line:\n     CONNECTALFLAGS=--bscflags \" -D TRACE_AXI\"\n\nFor getting timestamps inserted in read request data, also specify the conditional compile flag AXI_READ_TIMING.\n\nThis will compile ConnectableWithTrace to trace transactions into BRAM.\n\n### After running the test:\n\n1. run the script connectal/jtag/run_trace.sh.\n\n2. the trace output will be in the file trace.log.\n"
  },
  {
    "path": "doc/centos.md",
    "content": "# CentOS\n\n[CentOS](http://centos.org/) has joined forces with Red Hat, working to provide a common platform for open source community project needs.\nSince [RedHat](http://www.redhat.com/) is one of the preferred Linux platform for all EDA vendors, this page lists all the packages that \nwere required to be installed on top of the typical installation to run the CONNECTAL framework. \nVivado-14.1 also lists native support for CentOS in their [release notes](http://www.xilinx.com/support/documentation/sw_manuals/xilinx2014_1/ug973-vivado-release-notes-install-license.pdf).\n\n# yum\n\nRedHat/CentOS uses [yum](http://www.ibm.com/developerworks/library/l-lpic1-v3-102-5/) to fetch packages and install RPMs whereas Ubuntu which is derived from Debian distribution\nuses [apt](http://www.ibm.com/developerworks/linux/library/l-lpic1-v3-102-4/) commands to install packages. All the packages installed using yum [commands](http://yum.baseurl.org/wiki/YumCommands) need sudo or root privileges.\n\n# Packages\n\nThe following table lists the package name, the command used to install the package followed by a brief comment.\n\n<table border=\"2\" cellspacing=\"0\" cellpadding=\"6\" rules=\"all\" frame=\"border\">\n\n\n<colgroup>\n<col  class=\"left\" />\n\n<col  class=\"left\" />\n\n<col  class=\"left\" />\n</colgroup>\n<thead>\n<tr>\n<th scope=\"col\" class=\"left\">**package name**</th>\n<th scope=\"col\" class=\"left\">**installation command**</th>\n<th scope=\"col\" class=\"left\">**comment**</th>\n</tr>\n</thead>\n\n<tbody>\n<tr>\n<td class=\"left\">32-bit libstdc</td>\n<td class=\"left\">sudo yum install “Compatibility libraries”</td>\n<td class=\"left\">arm-xilinx-linux-gnueabi-g++ needs 32-bit libs</td>\n</tr>\n\n\n<tr>\n<td class=\"left\">[LiberOffice](http://www.libreoffice.org/)</td>\n<td class=\"left\">sudo yum groupinstall “Office Suite and Productivity”</td>\n<td class=\"left\">Optional (groupinfo will list packages)</td>\n</tr>\n\n\n<tr>\n<td class=\"left\">[flashplayer](http://get.adobe.com/flashplayer/)</td>\n<td class=\"left\">sudo yum install flash-plugin nspluginwrapper curl</td>\n<td class=\"left\">For several viewing video tutorials, e.g. [vivado training](http://www.xilinx.com/training/vivado/)</td>\n</tr>\n</tbody>\n\n<tbody>\n<tr>\n<td class=\"left\">python-ply</td>\n<td class=\"left\">sudo yum install python-ply</td>\n<td class=\"left\">Python Lex-Yacc</td>\n</tr>\n\n\n<tr>\n<td class=\"left\">python-argparse</td>\n<td class=\"left\">sudo yum install python-argparse</td>\n<td class=\"left\">Parser for command-line options, arguments and sub-commands</td>\n</tr>\n</tbody>\n\n<tbody>\n<tr>\n<td class=\"left\">[graphviz](http://www.graphviz.org/Download_linux_rhel.php)</td>\n<td class=\"left\">sudo yum install graphviz graphviz-tcl</td>\n<td class=\"left\">To view dot files generated by \"bsc -sched-dot\"</td>\n</tr>\n</tbody>\n\n<tbody>\n<tr>\n<td class=\"left\">ftp client</td>\n<td class=\"left\">sudo yum install ftp</td>\n<td class=\"left\">[needed for running out-of-the-box Linux example](http://zedboard.org/content/zedboard-setting-arm-development-environment-linux)</td>\n</tr>\n\n\n<tr>\n<td class=\"left\">cable drivers</td>\n<td class=\"left\">&#xa0;</td>\n<td class=\"left\">[Install Instructions](http://www.xilinx.com/support/answers/29310.htm)</td>\n</tr>\n\n\n<tr>\n<td class=\"left\">[fxload](http://pkgs.org/centos-6-rhel-6/linuxtech-x86_64/fxload-2008_10_13-3.el6.x86_64.rpm.html)</td>\n<td class=\"left\">&#xa0;</td>\n<td class=\"left\">Used to update the firmware of the platform cable.</td>\n</tr>\n\n\n<tr>\n<td class=\"left\">ldd \\`which docnav\\`</td>\n<td class=\"left\">&#xa0;</td>\n<td class=\"left\">Need to install \"not found\" libs for running Xilinx docnav</td>\n</tr>\n\n\n<tr>\n<td class=\"left\">&#xa0;</td>\n<td class=\"left\">sudo yum whatprovides libgthread-2.0.so.0</td>\n<td class=\"left\">repo: glib2-2.26.1-3.el6.i686</td>\n</tr>\n\n\n<tr>\n<td class=\"left\">libpng12.so.0</td>\n<td class=\"left\">sudo yum install 2:libpng-1.2.49-1.el6\\_2.i686</td>\n<td class=\"left\">A library of functions for manipulating PNG image format files</td>\n</tr>\n\n\n<tr>\n<td class=\"left\">libfontconfig.so.1</td>\n<td class=\"left\">sudo yum install fontconfig-2.8.0-3.el6.i686</td>\n<td class=\"left\">Font configuration and customization library</td>\n</tr>\n\n\n<tr>\n<td class=\"left\">libfreetype.so.6</td>\n<td class=\"left\">sudo yum install freetype-2.3.11-14.el6\\_3.1.i686</td>\n<td class=\"left\">A free and portable font rendering engine</td>\n</tr>\n\n\n<tr>\n<td class=\"left\">libXext.so.6</td>\n<td class=\"left\">sudo yum install libXext.so.6</td>\n<td class=\"left\">X.Org X11 libXext runtime library</td>\n</tr>\n\n\n<tr>\n<td class=\"left\">libXrender.so.q</td>\n<td class=\"left\">sudo yum install libXrender-0.9.7-2.el6.i686</td>\n<td class=\"left\">X.Org X11 libXrender runtime library</td>\n</tr>\n\n\n<tr>\n<td class=\"left\">libstdc++.so.6</td>\n<td class=\"left\">sudo yum install libstdc++-4.4.7-4.el6.i686</td>\n<td class=\"left\">GNU Standard C++ Library</td>\n</tr>\n\n\n<tr>\n<td class=\"left\">libgthread-2.0.so.0</td>\n<td class=\"left\">sudo yum install glib2-2.26.1-3.el6.i686</td>\n<td class=\"left\">A library of handy utility functions</td>\n</tr>\n\n\n<tr>\n<td class=\"left\">libSM.so.6</td>\n<td class=\"left\">sudo yum install libSM-1.2.1-2.el6.i686</td>\n<td class=\"left\">X.Org X11 SM runtime library</td>\n</tr>\n\n\n<tr>\n<td class=\"left\">libICE.so.6</td>\n<td class=\"left\">sudo yum install libICE-1.0.6-1.el6.i686</td>\n<td class=\"left\">X.Org X11 ICE runtime library</td>\n</tr>\n\n\n<tr>\n<td class=\"left\">libX11.so.6</td>\n<td class=\"left\">sudo yum install libX11-1.5.0-4.el6.i686</td>\n<td class=\"left\">Core X11 protocol client library</td>\n</tr>\n\n\n<tr>\n<td class=\"left\">&#xa0;</td>\n<td class=\"left\">cd /<pkg-dir>/xilinx/14.7/ISE\\_DS/ISE/lib/lin64</td>\n<td class=\"left\">To fix 'GLIBCXX\\_3.4.9' not found</td>\n</tr>\n\n\n<tr>\n<td class=\"left\">&#xa0;</td>\n<td class=\"left\">sudo mv libstdc++.so libstdc++.so.orig</td>\n<td class=\"left\">Do the same also in the following directories:</td>\n</tr>\n\n\n<tr>\n<td class=\"left\">&#xa0;</td>\n<td class=\"left\">sudo mv libstdc++.so.6 libstdc++.so.6.orig</td>\n<td class=\"left\">*<pkg-dir>/xilinx/14.7/ISE\\_DS/common/lib/lin64*</td>\n</tr>\n\n\n<tr>\n<td class=\"left\">&#xa0;</td>\n<td class=\"left\">sudo mv libstdc++.so.6.0.8 libstdc++.so.6.0.8.orig</td>\n<td class=\"left\">/<pkg-dir>/xilinx/Vivado/2013.3/ids\\_lite/ISE/lib/lin64</td>\n</tr>\n</tbody>\n\n<tbody>\n<tr>\n<td class=\"left\">emacs 24.3</td>\n<td class=\"left\">&#xa0;</td>\n<td class=\"left\">[Install instructions](http://h1de0ut.com/bl0g/article/2012/03/01/emacs24-ricty-centos6/)  (for better org mode support)</td>\n</tr>\n</tbody>\n</table>"
  },
  {
    "path": "doc/generated/html/portal.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.1//EN\"\r\n    \"http://www.w3.org/TR/xhtml11/DTD/xhtml11.dtd\">\r\n<html xmlns=\"http://www.w3.org/1999/xhtml\" xml:lang=\"en\">\r\n<head>\r\n<meta http-equiv=\"Content-Type\" content=\"application/xhtml+xml; charset=UTF-8\" />\r\n<meta name=\"generator\" content=\"AsciiDoc 8.6.6\" />\r\n<title>CONNECTAL</title>\r\n<style type=\"text/css\">\r\n/* Shared CSS for AsciiDoc xhtml11 and html5 backends */\r\n\r\n/* Default font. */\r\nbody {\r\n  font-family: Georgia,serif;\r\n}\r\n\r\n/* Title font. */\r\nh1, h2, h3, h4, h5, h6,\r\ndiv.title, caption.title,\r\nthead, p.table.header,\r\n#toctitle,\r\n#author, #revnumber, #revdate, #revremark,\r\n#footer {\r\n  font-family: Arial,Helvetica,sans-serif;\r\n}\r\n\r\nbody {\r\n  margin: 1em 5% 1em 5%;\r\n}\r\n\r\na {\r\n  color: blue;\r\n  text-decoration: underline;\r\n}\r\na:visited {\r\n  color: fuchsia;\r\n}\r\n\r\nem {\r\n  font-style: italic;\r\n  color: navy;\r\n}\r\n\r\nstrong {\r\n  font-weight: bold;\r\n  color: #083194;\r\n}\r\n\r\nh1, h2, h3, h4, h5, h6 {\r\n  color: #527bbd;\r\n  margin-top: 1.2em;\r\n  margin-bottom: 0.5em;\r\n  line-height: 1.3;\r\n}\r\n\r\nh1, h2, h3 {\r\n  border-bottom: 2px solid silver;\r\n}\r\nh2 {\r\n  padding-top: 0.5em;\r\n}\r\nh3 {\r\n  float: left;\r\n}\r\nh3 + * {\r\n  clear: left;\r\n}\r\nh5 {\r\n  font-size: 1.0em;\r\n}\r\n\r\ndiv.sectionbody {\r\n  margin-left: 0;\r\n}\r\n\r\nhr {\r\n  border: 1px solid silver;\r\n}\r\n\r\np {\r\n  margin-top: 0.5em;\r\n  margin-bottom: 0.5em;\r\n}\r\n\r\nul, ol, li > p {\r\n  margin-top: 0;\r\n}\r\nul > li     { color: #aaa; }\r\nul > li > * { color: black; }\r\n\r\npre {\r\n  padding: 0;\r\n  margin: 0;\r\n}\r\n\r\n#author {\r\n  color: #527bbd;\r\n  font-weight: bold;\r\n  font-size: 1.1em;\r\n}\r\n#email {\r\n}\r\n#revnumber, #revdate, #revremark {\r\n}\r\n\r\n#footer {\r\n  font-size: small;\r\n  border-top: 2px solid silver;\r\n  padding-top: 0.5em;\r\n  margin-top: 4.0em;\r\n}\r\n#footer-text {\r\n  float: left;\r\n  padding-bottom: 0.5em;\r\n}\r\n#footer-badges {\r\n  float: right;\r\n  padding-bottom: 0.5em;\r\n}\r\n\r\n#preamble {\r\n  margin-top: 1.5em;\r\n  margin-bottom: 1.5em;\r\n}\r\ndiv.imageblock, div.exampleblock, div.verseblock,\r\ndiv.quoteblock, div.literalblock, div.listingblock, div.sidebarblock,\r\ndiv.admonitionblock {\r\n  margin-top: 1.0em;\r\n  margin-bottom: 1.5em;\r\n}\r\ndiv.admonitionblock {\r\n  margin-top: 2.0em;\r\n  margin-bottom: 2.0em;\r\n  margin-right: 10%;\r\n  color: #606060;\r\n}\r\n\r\ndiv.content { /* Block element content. */\r\n  padding: 0;\r\n}\r\n\r\n/* Block element titles. */\r\ndiv.title, caption.title {\r\n  color: #527bbd;\r\n  font-weight: bold;\r\n  text-align: left;\r\n  margin-top: 1.0em;\r\n  margin-bottom: 0.5em;\r\n}\r\ndiv.title + * {\r\n  margin-top: 0;\r\n}\r\n\r\ntd div.title:first-child {\r\n  margin-top: 0.0em;\r\n}\r\ndiv.content div.title:first-child {\r\n  margin-top: 0.0em;\r\n}\r\ndiv.content + div.title {\r\n  margin-top: 0.0em;\r\n}\r\n\r\ndiv.sidebarblock > div.content {\r\n  background: #ffffee;\r\n  border: 1px solid #dddddd;\r\n  border-left: 4px solid #f0f0f0;\r\n  padding: 0.5em;\r\n}\r\n\r\ndiv.listingblock > div.content {\r\n  border: 1px solid #dddddd;\r\n  border-left: 5px solid #f0f0f0;\r\n  background: #f8f8f8;\r\n  padding: 0.5em;\r\n}\r\n\r\ndiv.quoteblock, div.verseblock {\r\n  padding-left: 1.0em;\r\n  margin-left: 1.0em;\r\n  margin-right: 10%;\r\n  border-left: 5px solid #f0f0f0;\r\n  color: #888;\r\n}\r\n\r\ndiv.quoteblock > div.attribution {\r\n  padding-top: 0.5em;\r\n  text-align: right;\r\n}\r\n\r\ndiv.verseblock > pre.content {\r\n  font-family: inherit;\r\n  font-size: inherit;\r\n}\r\ndiv.verseblock > div.attribution {\r\n  padding-top: 0.75em;\r\n  text-align: left;\r\n}\r\n/* DEPRECATED: Pre version 8.2.7 verse style literal block. */\r\ndiv.verseblock + div.attribution {\r\n  text-align: left;\r\n}\r\n\r\ndiv.admonitionblock .icon {\r\n  vertical-align: top;\r\n  font-size: 1.1em;\r\n  font-weight: bold;\r\n  text-decoration: underline;\r\n  color: #527bbd;\r\n  padding-right: 0.5em;\r\n}\r\ndiv.admonitionblock td.content {\r\n  padding-left: 0.5em;\r\n  border-left: 3px solid #dddddd;\r\n}\r\n\r\ndiv.exampleblock > div.content {\r\n  border-left: 3px solid #dddddd;\r\n  padding-left: 0.5em;\r\n}\r\n\r\ndiv.imageblock div.content { padding-left: 0; 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Stewart - Scribe</span><br />\r\n<span id=\"revdate\">0.002</span>\r\n<div id=\"toc\">\n  <div id=\"toctitle\">Table of Contents</div>\n  <noscript><p><b>JavaScript must be enabled in your browser to display the table of contents.</b></p></noscript>\n</div>\r\n</div>\r\n<div id=\"content\">\r\n<div id=\"preamble\">\r\n<div class=\"sectionbody\">\r\n<div class=\"paragraph\"><p>April 29, 2014</p></div>\r\n</div>\r\n</div>\r\n<div class=\"sect1\">\r\n<h2 id=\"_what_is_connectal\">What is CONNECTAL?</h2>\r\n<div class=\"sectionbody\">\r\n<div class=\"paragraph lead\"><p>CONNECTAL provides a hardware-software interface for applications split\r\nbetween user mode code and custom hardware in an FPGA or ASIC.</p></div>\r\n<div class=\"paragraph\"><p>CONNECTAL can automaticaly build the software and hardware glue for a\r\nmessage based interface and also provides for configuring and using\r\nshared memory between applications and hardware. Communications\r\nbetween hardware and software are provided by a bidirectional flow of\r\nevents and regions of memory shared between hardware and software.\r\nEvents from software to hardware are called requests and events from\r\nhardware to software are called indications, but in fact they are\r\nsymmetric.</p></div>\r\n</div>\r\n</div>\r\n<div class=\"sect1\">\r\n<h2 id=\"_lexicon\">Lexicon</h2>\r\n<div class=\"sectionbody\">\r\n<div class=\"dlist\"><dl>\r\n<dt class=\"hdlist1\">\r\nconnectal\r\n</dt>\r\n<dd>\r\n<p>\r\nThe name of the project, whose goal is to ease the task of\r\nbuilding applications composed of hardware and software components.\r\nProgrammers use bsv as an IDL to specify the interface between the\r\nhardware and software components.  A combination of generated code and\r\nlibraries coordinate the data-flow between the program modules.\r\nBecause the HW and SW stacks are customized for each application, the\r\noverheads associated with communicating across the HW/SW boundary are\r\nlow.\r\n</p>\r\n</dd>\r\n<dt class=\"hdlist1\">\r\nHW/SW interface \r\n</dt>\r\n<dd>\r\n<p>\r\nportal\r\n</p>\r\n</dd>\r\n<dt class=\"hdlist1\">\r\nbsv\r\n</dt>\r\n<dd>\r\n<p>\r\nBluespec System Verilog.  bsv is a language for describing hardware that is might higher level than verilog. See <a href=\"http://wiki.bluespec.com/Home/BSV-Documentation\">BSV Documentation</a> and <a href=\"http://www.bluespec.com/\">Bluespec, Inc</a>.\r\n</p>\r\n</dd>\r\n<dt class=\"hdlist1\">\r\nbluespec\r\n</dt>\r\n<dd>\r\n<p>\r\nShorthand for Bluespec System Verilog (bsv)\r\n</p>\r\n</dd>\r\n</dl></div>\r\n<div class=\"paragraph\"><p>indexterm:portal\r\nportal:: a logical request/indication pair is referred to as a portal.  current tools require their specification in the IDL to be syntactically identifiable (i.e. fooRequest/fooIndication).  An application can make use of multiple portals, which may be specified independently.</p></div>\r\n<div class=\"dlist\"><dl>\r\n<dt class=\"hdlist1\">\r\nrequest interface\r\n</dt>\r\n<dd>\r\n<p>\r\nThese methods are implemented by the application hardware to be invoked by application software.   A bsv interface consisting of ‘Action’ methods.  Because of the ‘Action’ type, data flow across this interface is unidirectional (SW &#8594; HW).\r\n</p>\r\n</dd>\r\n<dt class=\"hdlist1\">\r\nindication interface\r\n</dt>\r\n<dd>\r\n<p>\r\nThe dual of a request interface, indication interfaces are ‘Action’ methods implemented by application software to be invoked by application hardware.   As with request interfaces, the data flow across this interface is unidirectional, but in the opposite direction.\r\n</p>\r\n</dd>\r\n<dt class=\"hdlist1\">\r\npcieportal/zynqportal\r\n</dt>\r\n<dd>\r\n<p>\r\nthese two loadable kernel modules implement the minimal set of driver functionality.  Specifically, they expose portal HW registers to SW through mmap, and set up interrupts to notify SW that an indication method has been invoked by HW.\r\n</p>\r\n</dd>\r\n<dt class=\"hdlist1\">\r\nportalalloc\r\n</dt>\r\n<dd>\r\n<p>\r\nThis loadable kernel module exposes a subset of dma-buf functionality to user-space software (though a set of ioctl commands) to allocate and manage memory regions which can be shared between SW and HW processes.   Maintaining coherence of the allocated buffers between processes is not automatic: ioctl commands for flush/invalidate are provided to be invoked explicitly by the users if necessary.\r\n</p>\r\n</dd>\r\n<dt class=\"hdlist1\">\r\nconnectalgen\r\n</dt>\r\n<dd>\r\n<p>\r\nThe name of the interface compiler which takes as input the bsv interface specification along with a description of a target platform and generates logic in both HW and SW to support this interface across the communication fabric.\r\n</p>\r\n</dd>\r\n</dl></div>\r\n</div>\r\n</div>\r\n<div class=\"sect1\">\r\n<h2 id=\"_example_setups\">Example setups:</h2>\r\n<div class=\"sectionbody\">\r\n<div class=\"paragraph\"><p>A zedboard ( <a href=\"http://www.zedboard.org/\">http://www.zedboard.org/</a> ),\r\nwith Android running on the embedded ARM processors (the Processing\r\nSystem 7), an application running as a user process, and custom\r\nhardware configured into the Programmable Logic FPGA.</p></div>\r\n<div class=\"paragraph\"><p>An x86 server, with Linux running on the host processor, an\r\napplication running partly as a user process on the host and partly as\r\nhardware configured into an FPGA connected by PCI express (such as the\r\nXilinx VC707\r\n(<a href=\"http://www.xilinx.com/products/boards-and-kits/EK-V7-VC707-G.htm\">http://www.xilinx.com/products/boards-and-kits/EK-V7-VC707-G.htm</a>).</p></div>\r\n</div>\r\n</div>\r\n<div class=\"sect1\">\r\n<h2 id=\"_background\">Background</h2>\r\n<div class=\"sectionbody\">\r\n<div class=\"paragraph\"><p>When running part or all of an application in an FPGA, it is usually\r\nnecessary to communicate between code running in user mode on the host\r\nand the hardware.  Typically this has been accomplished by custom\r\ndevice drivers in the OS, or by shared memory mapped between the\r\nsoftware and the hardware, or both.  Shared memory has been\r\nparticularly troublesome under Linux or Android, because devices\r\nfrequently require contiguous memory, and the mechanisms for\r\nguaranteeing successful memory allocation often require reserving the\r\nmaximum amount of memory at boot time.</p></div>\r\n<div class=\"paragraph\"><p>Portal tries to provide convenient solutions to these problems in a portable way.</p></div>\r\n<div class=\"paragraph\"><p>It is desirable to have</p></div>\r\n<div class=\"ulist\"><ul>\r\n<li>\r\n<p>\r\nlow latency for small messages\r\n</p>\r\n</li>\r\n<li>\r\n<p>\r\nhigh bandwidth for large messages\r\n</p>\r\n</li>\r\n<li>\r\n<p>\r\nnotification of arriving messages\r\n</p>\r\n</li>\r\n<li>\r\n<p>\r\nasynchronous replies to messages\r\n</p>\r\n</li>\r\n<li>\r\n<p>\r\nsupport for hardware simulation by a separate user mode process\r\n</p>\r\n</li>\r\n<li>\r\n<p>\r\nsupport for shared memory (DMA) between hardware and software\r\n</p>\r\n</li>\r\n</ul></div>\r\n</div>\r\n</div>\r\n<div class=\"sect1\">\r\n<h2 id=\"_overview\">Overview</h2>\r\n<div class=\"sectionbody\">\r\n<div class=\"paragraph\"><p>Portal is implemented as a loadable kernel module device driver for Linux/Android and a set of tools to automatically construct the hardware and software glue necessary for communications.</p></div>\r\n<div class=\"paragraph\"><p>Short messages are handled by programmed I/O.  The message interface from software to hardware (so called \"requests\") is defined as a bsv interface containing a number of Action methods, each with a name and typed arguments.  The interface generator creates all the software and hardware glue so that software invocations of the interface stubs flow through to, and are turned into bsv invocations of the matching hardware.  The machinery does not have flow control. Software is responsible for not overrunning the hardware.  There is a debug mechanism which will return the request type of a failed method, but it does not tell which invocation failed.  Hardware to software interfaces (so called “indications”) are likewise defined by bsv interfaces containing Action methods. Hardware invocations of these methods flow through to and cause software calls to corresponding user-supplied functions.  In the current implementation there is flow control, in that the hardware will stall until there is room for a hardware to software message.  There is also a mechanism for software to report a failure, and there is machinery for these failures to be returned to the hardware.</p></div>\r\n<div class=\"imageblock seqdiag\">\r\n<div class=\"content\">\r\n<img src=\"request-response-1.png\" alt=\"request-response-1.png\" />\r\n</div>\r\n</div>\r\n<div class=\"paragraph\"><p>Portals do not have to be structured as request/response. Hardware can\r\nsend messages to software without a prior request from software.</p></div>\r\n<div class=\"imageblock seqdiag\">\r\n<div class=\"content\">\r\n<img src=\"indication-only.png\" alt=\"indication-only.png\" />\r\n</div>\r\n</div>\r\n<div class=\"paragraph\"><p>Incoming messages can cause host interrupts, which wake up the device driver, which can wake up the user mode application by using the select(2) or poll(2) interfaces.</p></div>\r\n<div class=\"paragraph\"><p>Most of the time, communications between hardware and software will\r\nproceed without requiring use of the OS.  User code will read and\r\nwrite directly to memory mapped I/O space. Library code will poll for\r\nincoming messages, and [true? eventually time out and call poll(2).\r\nOnly when poll(2) or select(2) are called will the device driver\r\nenable hardware interrupts.  Thus interrupts are only used to wake up\r\nsoftware after a quiet period.</p></div>\r\n<div class=\"paragraph\"><p>The designer specifies a set of hardware functions that can be called\r\nfrom software, and a set of actions that the hardware can take which\r\nresult in messages to software. Portal tools take this specification\r\nand build software glue modules to translate software function calls\r\ninto I/O writes to hardware registers, and to report hardware events\r\nto software.</p></div>\r\n<div class=\"paragraph\"><p>For larger memory and OS bypass (OS bypass means letting the user mode\r\napplication talk directly to the hardware without using the OS except\r\nfor setup), portal implements shared memory.  Portal memory objects\r\nare allocated by the user mode program, and appear as Linux file\r\ndescriptors. The user can mmap(2) the file to obtain user mode access\r\nto the shared memory region. Portal does not assure that the memory is\r\nphysically contiguous, but does pin it to prevent the OS from reusing\r\nthe memory.  An FPGA DMA controller module is provided that gives the\r\nillusion of contiguous memory to application hardware, while under the\r\ncovers using a translation table of scattered addresses.</p></div>\r\n<div class=\"paragraph\"><p>The physical addresses are provided to the user code in order to\r\ninitialize the dma controller, and address \"handles\" are provided for\r\nthe application hardware to use.</p></div>\r\n<div class=\"paragraph\"><p>The DMA controller provides Bluespec objects that support streaming access with automatic page crossings, or random access.</p></div>\r\n</div>\r\n</div>\r\n<div class=\"sect1\">\r\n<h2 id=\"_an_example\">An Example</h2>\r\n<div class=\"sectionbody\">\r\n<div class=\"paragraph\"><p>An application developer will typically write the hardware part of the application in Bluespec and the software part of the application in C or C++.  In a short example, there will be a bsv source file for the hardware and a cpp source file for the application.</p></div>\r\n<div class=\"paragraph\"><p>The application developer is free to specify whatever hardware-software interface makes sense.</p></div>\r\n<div class=\"paragraph\"><p>Refer to <a href=\"https://github.com/cambridgehackers/connectal\">https://github.com/cambridgehackers/connectal</a></p></div>\r\n<div class=\"paragraph\"><p>In the examples directory, see [simple](../examples/simple/).  The file [Simple.bsv](../examples/simple/Simple.bsv) defines the hardware, and testsimple.cpp supplies the software part. In this case, the software part is a test framework for the hardware.</p></div>\r\n<div class=\"paragraph\"><p>Simple.bsv declares a few <tt>struct</tt> and <tt>enum</tt> types:</p></div>\r\n<div class=\"listingblock\">\r\n<div class=\"content\">\r\n<pre><tt>    typedef struct{\r\n       Bit#(32) a;\r\n       Bit#(32) b;\r\n       } S1 deriving (Bits);\r\n\r\n    typedef struct{\r\n       Bit#(32) a;\r\n       Bit#(16) b;\r\n       Bit#(7) c;\r\n       } S2 deriving (Bits);\r\n\r\n    typedef enum {\r\n       E1Choice1,\r\n       E1Choice2,\r\n       E1Choice3\r\n       } E1 deriving (Bits,Eq);\r\n\r\n    typedef struct{\r\n       Bit#(32) a;\r\n       E1 e1;\r\n       } S3 deriving (Bits);</tt></pre>\r\n</div></div>\r\n<div class=\"paragraph\"><p>Simple.bsv defines the actions (called Requests) that software can use to cause the hardware to act, and defines the notifications (called Indications) that the hardware can use to signal the software.</p></div>\r\n<div class=\"listingblock\">\r\n<div class=\"content\">\r\n<pre><tt>    interface SimpleIndication;\r\n        method Action heard1(Bit#(32) v);\r\n        method Action heard2(Bit#(16) a, Bit#(16) b);\r\n        method Action heard3(S1 v);\r\n        method Action heard4(S2 v);\r\n        method Action heard5(Bit#(32) a, Bit#(64) b, Bit#(32) c);\r\n        method Action heard6(Bit#(32) a, Bit#(40) b, Bit#(32) c);\r\n        method Action heard7(Bit#(32) a, E1 e1);\r\n    endinterface\r\n\r\n    interface SimpleRequest;\r\n        method Action say1(Bit#(32) v);\r\n        method Action say2(Bit#(16) a, Bit#(16) b);\r\n        method Action say3(S1 v);\r\n        method Action say4(S2 v);\r\n        method Action say5(Bit#(32)a, Bit#(64) b, Bit#(32) c);\r\n        method Action say6(Bit#(32)a, Bit#(40) b, Bit#(32) c);\r\n        method Action say7(S3 v);\r\n    endinterface</tt></pre>\r\n</div></div>\r\n<div class=\"paragraph\"><p>Software can start the hardware working via say, say2, &#8230; Hardware\r\nsignals back to software with heard and heard2 and so fort.  In the\r\ncase of this example, say and say2 merely echo their arguments back to\r\nsoftware.</p></div>\r\n<div class=\"paragraph\"><p>The definitions in the bsv file are used by the connectal infrastructure ( a python program)  to automatically create corresponding c++ interfaces.</p></div>\r\n<div class=\"listingblock\">\r\n<div class=\"content\">\r\n<pre><tt>    ../../connectalgen -Bbluesim -p bluesim -x mkBsimTop \\\r\n         -s2h SimpleRequest \\\r\n         -h2s SimpleIndication \\\r\n         -s testsimple.cpp \\\r\n         -t ../../bsv/BsimTop.bsv  Simple.bsv Top.bsv</tt></pre>\r\n</div></div>\r\n<div class=\"paragraph\"><p>The tools have to be told which interface records should be used for\r\nSoftware to Hardware messages and which should be used for Hardware to\r\nSoftware messages. These interfaces are given on the command line for\r\ngenxpprojfrombsv</p></div>\r\n<div class=\"paragraph\"><p>connectalgen constructs all the hardware and software modules\r\nneeded to wire up portals. This is sort of like an RPC compiler for\r\nthe hardware-software interface. However, unlike an RPC each method is\r\nasynchronous.</p></div>\r\n<div class=\"paragraph\"><p>The user must also create a toplevel bsv module Top.bsv, which\r\ninstantiates the user portals, the standard hardware environment, and\r\nany additional hardware modules.</p></div>\r\n<div class=\"paragraph\"><p>Rather than constructing the <tt>connectalgen</tt> command line from\r\nscratch, the examples in connectal use include\r\n[Makefile.common](../Makefile.common) and define some <tt>make</tt>\r\nvariables.</p></div>\r\n<div class=\"paragraph\"><p>Here is the Makefile for the <tt>simple</tt> example:</p></div>\r\n<div class=\"listingblock\">\r\n<div class=\"content\"><!-- Generator: GNU source-highlight 3.1.5\r\nby Lorenzo Bettini\r\nhttp://www.lorenzobettini.it\r\nhttp://www.gnu.org/software/src-highlite -->\r\n<pre><tt>    <span style=\"color: #009900\">BSVDIR</span><span style=\"color: #990000\">=../..</span>/bsv\r\n    S2H <span style=\"color: #990000\">=</span> SimpleRequest\r\n    H2S <span style=\"color: #990000\">=</span> SimpleIndication\r\n    BSVFILES <span style=\"color: #990000\">=</span> Simple.bsv Top.bsv\r\n    <span style=\"color: #009900\">CPPFILES</span><span style=\"color: #990000\">=</span>testsimple.cpp\r\n    Dma <span style=\"color: #990000\">=</span>\r\n    PINS <span style=\"color: #990000\">=</span> Std\r\n\r\n    include <span style=\"color: #990000\">../..</span>/Makefile.common</tt></pre></div></div>\r\n<div class=\"paragraph\"><p>Designs using <tt>connectal</tt> may also include <tt>connectal/Makefile.common</tt> if they define <tt>CONNECTALDIR</tt> in their Makefile:</p></div>\r\n<div class=\"listingblock\">\r\n<div class=\"content\"><!-- Generator: GNU source-highlight 3.1.5\r\nby Lorenzo Bettini\r\nhttp://www.lorenzobettini.it\r\nhttp://www.gnu.org/software/src-highlite -->\r\n<pre><tt>    <span style=\"color: #009900\">CONNECTALDIR</span><span style=\"color: #990000\">=</span>/scratch/connectal\r\n    S2H <span style=\"color: #990000\">=</span> <span style=\"color: #990000\">...</span>\r\n    H2S <span style=\"color: #990000\">=</span> <span style=\"color: #990000\">...</span>\r\n    BSVFILES <span style=\"color: #990000\">=</span> <span style=\"color: #990000\">...</span>\r\n    CPPFILES <span style=\"color: #990000\">=</span> <span style=\"color: #990000\">...</span>\r\n    include <span style=\"color: #009900\">$(CONNECTALDIR)</span>/Makefile.common</tt></pre></div></div>\r\n<div class=\"sect2\">\r\n<h3 id=\"_simple_top_bsv\">simple/Top.bsv</h3>\r\n<div class=\"paragraph\"><p>Each CONNECTAL design implements [Top.bsv](../examples/simple/Top.bsv) with some standard components.</p></div>\r\n<div class=\"paragraph\"><p>It defines the <tt>IfcNames</tt> enum, for use in identifying the portals between software and hardware:</p></div>\r\n<div class=\"listingblock\">\r\n<div class=\"content\">\r\n<pre><tt>    typedef enum {SimpleIndication, SimpleRequest} IfcNames deriving (Eq,Bits);</tt></pre>\r\n</div></div>\r\n<div class=\"paragraph\"><p>It defines <tt>mkConnectalTop</tt>, which instantiates the wrappers, proxies, and the design itself:</p></div>\r\n<div class=\"listingblock\">\r\n<div class=\"content\">\r\n<pre><tt>    module mkConnectalTop(StdConnectalTop#(addrWidth));</tt></pre>\r\n</div></div>\r\n<div class=\"paragraph\"><p><tt>StdConnectalTop</tt> is parameterized by <tt>addrWidth</tt> because Zynq and x86 have different width addressing. <tt>StdConnectalTop</tt> is a typedef:</p></div>\r\n<div class=\"listingblock\">\r\n<div class=\"content\">\r\n<pre><tt>    typedef ConnectalTop#(addrWidth,64,Empty)     StdConnectalTop#(numeric type addrWidth);</tt></pre>\r\n</div></div>\r\n<div class=\"paragraph\"><p>The \"64\" specifies the data width and <tt>Empty</tt> specifies the empty\r\ninterface is exposed as pins from the design. In designs using HDMI,\r\nfor example, <tt>Empty</tt> is replaced by <tt>HDMI</tt>.  On some platforms, the\r\ndesign may be able to use different data widths, such as 128 bits on\r\nx86/PCIe.</p></div>\r\n<div class=\"paragraph\"><p>Next, <tt>mkConnectalTop</tt> instantiates user portals:</p></div>\r\n<div class=\"listingblock\">\r\n<div class=\"content\">\r\n<pre><tt>    // instantiate user portals\r\n       SimpleIndicationProxy simpleIndicationProxy &lt;- mkSimpleIndicationProxy(SimpleIndication);</tt></pre>\r\n</div></div>\r\n<div class=\"paragraph\"><p>Instantiate the design:</p></div>\r\n<div class=\"listingblock\">\r\n<div class=\"content\">\r\n<pre><tt>       SimpleRequest simpleRequest &lt;- mkSimpleRequest(simpleIndicationProxy.ifc);</tt></pre>\r\n</div></div>\r\n<div class=\"paragraph\"><p>Instantiate the wrapper for the design:</p></div>\r\n<div class=\"listingblock\">\r\n<div class=\"content\">\r\n<pre><tt>       SimpleRequestWrapper simpleRequestWrapper &lt;- mkSimpleRequestWrapper(SimpleRequest,simpleRequest);</tt></pre>\r\n</div></div>\r\n<div class=\"paragraph\"><p>Collect the portals into a vector:</p></div>\r\n<div class=\"listingblock\">\r\n<div class=\"content\">\r\n<pre><tt>       Vector#(2,StdPortal) portals;\r\n       portals[0] = simpleRequestWrapper.portalIfc;\r\n       portals[1] = simpleIndicationProxy.portalIfc;</tt></pre>\r\n</div></div>\r\n<div class=\"paragraph\"><p>Create an interrupt multiplexer from the vector of portals:</p></div>\r\n<div class=\"listingblock\">\r\n<div class=\"content\">\r\n<pre><tt>       let interrupt_mux &lt;- mkInterruptMux(portals);</tt></pre>\r\n</div></div>\r\n<div class=\"paragraph\"><p>Create the system directory, which is used by software to locate each portal via the <tt>IfcNames</tt> enum:</p></div>\r\n<div class=\"listingblock\">\r\n<div class=\"content\">\r\n<pre><tt>       // instantiate system directory\r\n       StdDirectory dir &lt;- mkStdDirectory(portals);\r\n       let ctrl_mux &lt;- mkAxiSlaveMux(dir,portals);</tt></pre>\r\n</div></div>\r\n<div class=\"paragraph\"><p>The following generic interfaces are used by the platform specific top BSV module:</p></div>\r\n<div class=\"listingblock\">\r\n<div class=\"content\">\r\n<pre><tt>       interface interrupt = interrupt_mux;\r\n       interface ctrl = ctrl_mux;\r\n       interface m_axi = null_axi_master;\r\n       interface leds = echoRequestInternal.leds;\r\n\r\n    endmodule : mkConnectalTop</tt></pre>\r\n</div></div>\r\n</div>\r\n<div class=\"sect2\">\r\n<h3 id=\"_simple_testsimple_cpp\">simple/testsimple.cpp</h3>\r\n<div class=\"paragraph\"><p>CONNECTAL generates header files declaring wrappers for\r\nhardware-to-software interfaces and proxies for software-to-hardware\r\ninterfaces. These will be in the \"jni/\" subdirectory of the project directory.</p></div>\r\n<div class=\"listingblock\">\r\n<div class=\"content\"><!-- Generator: GNU source-highlight 3.1.5\r\nby Lorenzo Bettini\r\nhttp://www.lorenzobettini.it\r\nhttp://www.gnu.org/software/src-highlite -->\r\n<pre><tt><span style=\"font-weight: bold\"><span style=\"color: #000080\">    #include</span></span> <span style=\"color: #FF0000\">\"SimpleIndicationWrapper.h\"</span>\r\n<span style=\"font-weight: bold\"><span style=\"color: #000080\">    #include</span></span> <span style=\"color: #FF0000\">\"SimpleRequestProxy.h\"</span></tt></pre></div></div>\r\n<div class=\"paragraph\"><p>It also declares software equivalents for structs and enums declared in the processed BSV files:</p></div>\r\n<div class=\"listingblock\">\r\n<div class=\"content\"><!-- Generator: GNU source-highlight 3.1.5\r\nby Lorenzo Bettini\r\nhttp://www.lorenzobettini.it\r\nhttp://www.gnu.org/software/src-highlite -->\r\n<pre><tt><span style=\"font-weight: bold\"><span style=\"color: #000080\">    #include</span></span> <span style=\"color: #FF0000\">\"GeneratedTypes.h\"</span></tt></pre></div></div>\r\n<div class=\"paragraph\"><p>CONNECTAL generates abstract virtual base classes for each Indication interface.</p></div>\r\n<div class=\"listingblock\">\r\n<div class=\"content\"><!-- Generator: GNU source-highlight 3.1.5\r\nby Lorenzo Bettini\r\nhttp://www.lorenzobettini.it\r\nhttp://www.gnu.org/software/src-highlite -->\r\n<pre><tt>    <span style=\"font-weight: bold\"><span style=\"color: #0000FF\">class</span></span> <span style=\"color: #008080\">SimpleIndicationWrapper</span> <span style=\"color: #990000\">:</span> <span style=\"font-weight: bold\"><span style=\"color: #0000FF\">public</span></span> Portal <span style=\"color: #FF0000\">{</span>\r\n\r\n    <span style=\"font-weight: bold\"><span style=\"color: #0000FF\">public</span></span><span style=\"color: #990000\">:</span>\r\n        <span style=\"color: #990000\">...</span>\r\n        <span style=\"font-weight: bold\"><span style=\"color: #000000\">SimpleIndicationWrapper</span></span><span style=\"color: #990000\">(</span><span style=\"color: #009900\">int</span> id<span style=\"color: #990000\">,</span> <span style=\"color: #008080\">PortalPoller</span> <span style=\"color: #990000\">*</span>poller <span style=\"color: #990000\">=</span> <span style=\"color: #993399\">0</span><span style=\"color: #990000\">);</span>\r\n        <span style=\"font-weight: bold\"><span style=\"color: #0000FF\">virtual</span></span> <span style=\"color: #009900\">void</span> <span style=\"font-weight: bold\"><span style=\"color: #000000\">heard1</span></span> <span style=\"color: #990000\">(</span> <span style=\"font-weight: bold\"><span style=\"color: #0000FF\">const</span></span> <span style=\"color: #008080\">uint32_t</span> v <span style=\"color: #990000\">)=</span> <span style=\"color: #993399\">0</span><span style=\"color: #990000\">;</span>\r\n        <span style=\"color: #990000\">...</span>\r\n    <span style=\"color: #FF0000\">}</span><span style=\"color: #990000\">;</span></tt></pre></div></div>\r\n<div class=\"paragraph\"><p>Implement subclasses of the wrapper in order to define the callbacks</p></div>\r\n<div class=\"listingblock\">\r\n<div class=\"content\"><!-- Generator: GNU source-highlight 3.1.5\r\nby Lorenzo Bettini\r\nhttp://www.lorenzobettini.it\r\nhttp://www.gnu.org/software/src-highlite -->\r\n<pre><tt>    <span style=\"font-weight: bold\"><span style=\"color: #0000FF\">class</span></span> <span style=\"color: #008080\">SimpleIndication</span> <span style=\"color: #990000\">:</span> <span style=\"font-weight: bold\"><span style=\"color: #0000FF\">public</span></span> SimpleIndicationWrapper\r\n    <span style=\"color: #FF0000\">{</span>\r\n    <span style=\"font-weight: bold\"><span style=\"color: #0000FF\">public</span></span><span style=\"color: #990000\">:</span>\r\n      <span style=\"color: #990000\">...</span>\r\n        <span style=\"font-weight: bold\"><span style=\"color: #0000FF\">virtual</span></span> <span style=\"color: #009900\">void</span> <span style=\"font-weight: bold\"><span style=\"color: #000000\">heard1</span></span><span style=\"color: #990000\">(</span><span style=\"color: #008080\">uint32_t</span> a<span style=\"color: #990000\">)</span> <span style=\"color: #FF0000\">{</span>\r\n          <span style=\"font-weight: bold\"><span style=\"color: #000000\">fprintf</span></span><span style=\"color: #990000\">(</span>stderr<span style=\"color: #990000\">,</span> <span style=\"color: #FF0000\">\"heard1(%d)</span><span style=\"color: #CC33CC\">\\n</span><span style=\"color: #FF0000\">\"</span><span style=\"color: #990000\">,</span> a<span style=\"color: #990000\">);</span>\r\n          <span style=\"font-weight: bold\"><span style=\"color: #000000\">assert</span></span><span style=\"color: #990000\">(</span>a <span style=\"color: #990000\">==</span> v1a<span style=\"color: #990000\">);</span>\r\n          <span style=\"font-weight: bold\"><span style=\"color: #000000\">incr_cnt</span></span><span style=\"color: #990000\">();</span>\r\n        <span style=\"color: #FF0000\">}</span>\r\n        <span style=\"color: #990000\">...</span>\r\n    <span style=\"color: #FF0000\">}</span><span style=\"color: #990000\">;</span></tt></pre></div></div>\r\n<div class=\"paragraph\"><p>To connect these classes to the hardware, instantiate them using the\r\n<tt>IfcNames</tt> enum identifiers. CONNECTAL prepends the name of the type\r\nbecause C++ does not support overloading of enum tags.</p></div>\r\n<div class=\"listingblock\">\r\n<div class=\"content\"><!-- Generator: GNU source-highlight 3.1.5\r\nby Lorenzo Bettini\r\nhttp://www.lorenzobettini.it\r\nhttp://www.gnu.org/software/src-highlite -->\r\n<pre><tt>    <span style=\"color: #008080\">SimpleIndication</span> <span style=\"color: #990000\">*</span>indication <span style=\"color: #990000\">=</span> <span style=\"font-weight: bold\"><span style=\"color: #0000FF\">new</span></span> <span style=\"font-weight: bold\"><span style=\"color: #000000\">SimpleIndication</span></span><span style=\"color: #990000\">(</span>IfcNames_SimpleIndication<span style=\"color: #990000\">);</span>\r\n    <span style=\"color: #008080\">SimpleRequestProxy</span> <span style=\"color: #990000\">*</span>device <span style=\"color: #990000\">=</span> <span style=\"font-weight: bold\"><span style=\"color: #0000FF\">new</span></span> <span style=\"font-weight: bold\"><span style=\"color: #000000\">SimpleRequestProxy</span></span><span style=\"color: #990000\">(</span>IfcNames_SimpleRequest<span style=\"color: #990000\">);</span></tt></pre></div></div>\r\n<div class=\"paragraph\"><p>Create a thread for handling notifications from hardware:</p></div>\r\n<div class=\"listingblock\">\r\n<div class=\"content\"><!-- Generator: GNU source-highlight 3.1.5\r\nby Lorenzo Bettini\r\nhttp://www.lorenzobettini.it\r\nhttp://www.gnu.org/software/src-highlite -->\r\n<pre><tt>    <span style=\"color: #008080\">pthread_t</span> tid<span style=\"color: #990000\">;</span>\r\n    <span style=\"font-weight: bold\"><span style=\"color: #0000FF\">if</span></span><span style=\"color: #990000\">(</span><span style=\"font-weight: bold\"><span style=\"color: #000000\">pthread_create</span></span><span style=\"color: #990000\">(&amp;</span>tid<span style=\"color: #990000\">,</span> NULL<span style=\"color: #990000\">,</span>  portalExec<span style=\"color: #990000\">,</span> NULL<span style=\"color: #990000\">))</span><span style=\"color: #FF0000\">{</span>\r\n      <span style=\"font-weight: bold\"><span style=\"color: #000000\">exit</span></span><span style=\"color: #990000\">(</span><span style=\"color: #993399\">1</span><span style=\"color: #990000\">);</span>\r\n    <span style=\"color: #FF0000\">}</span></tt></pre></div></div>\r\n<div class=\"paragraph\"><p>Now the software invokes hardware methods via the proxy:</p></div>\r\n<div class=\"listingblock\">\r\n<div class=\"content\"><!-- Generator: GNU source-highlight 3.1.5\r\nby Lorenzo Bettini\r\nhttp://www.lorenzobettini.it\r\nhttp://www.gnu.org/software/src-highlite -->\r\n<pre><tt>    device<span style=\"color: #990000\">-&gt;</span><span style=\"font-weight: bold\"><span style=\"color: #000000\">say1</span></span><span style=\"color: #990000\">(</span>v1a<span style=\"color: #990000\">);</span>\r\n\r\n    device<span style=\"color: #990000\">-&gt;</span><span style=\"font-weight: bold\"><span style=\"color: #000000\">say2</span></span><span style=\"color: #990000\">(</span>v2a<span style=\"color: #990000\">,</span>v2b<span style=\"color: #990000\">);</span></tt></pre></div></div>\r\n</div>\r\n<div class=\"sect2\">\r\n<h3 id=\"_simple_example_design_structure\">Simple Example Design Structure</h3>\r\n<div class=\"paragraph\"><p>The <tt>simple</tt> example consists of the following files:</p></div>\r\n<div class=\"listingblock\">\r\n<div class=\"content\">\r\n<pre><tt>    Simple.bsv\r\n    Makefile\r\n    Top.bsv\r\n    testsimple.cpp</tt></pre>\r\n</div></div>\r\n<div class=\"paragraph\"><p>After running <tt>make BOARD=zedboard verilog</tt> in the <tt>simple</tt> directory,\r\nthe <tt>zedboard</tt> project directory is created, populated by the generated files.</p></div>\r\n<div class=\"paragraph\"><p>A top level <tt>Makefile</tt> is created:</p></div>\r\n<div class=\"listingblock\">\r\n<div class=\"content\">\r\n<pre><tt>    zedboard/Makefile</tt></pre>\r\n</div></div>\r\n<div class=\"paragraph\"><p>connectalgen generates wrappers for software-to-hardware interfaces and proxies for hardware-to-software interfaces:</p></div>\r\n<div class=\"listingblock\">\r\n<div class=\"content\">\r\n<pre><tt>    zedboard/sources/mkzynqtop/SimpleIndicationProxy.bsv\r\n    zedboard/sources/mkzynqtop/SimpleRequestWrapper.bsv</tt></pre>\r\n</div></div>\r\n<div class=\"paragraph\"><p>CONNECTAL supports Android on Zynq platforms, so connectalgen generates <tt>jni/Android.mk</tt> for <tt>ndk-build</tt>.</p></div>\r\n<div class=\"listingblock\">\r\n<div class=\"content\">\r\n<pre><tt>    zedboard/jni/Android.mk\r\n    zedboard/jni/Application.mk</tt></pre>\r\n</div></div>\r\n<div class=\"paragraph\"><p>CONNECTAL generates <tt>jni/Makefile</tt> to compile the software for PCIe platforms (vc707 and kc705).</p></div>\r\n<div class=\"listingblock\">\r\n<div class=\"content\">\r\n<pre><tt>    zedboard/jni/Makefile</tt></pre>\r\n</div></div>\r\n<div class=\"paragraph\"><p>CONNECTAL generates software proxies for software-to-hardware interfaces and software wrappers for hardware-to-software interfaces:</p></div>\r\n<div class=\"listingblock\">\r\n<div class=\"content\">\r\n<pre><tt>    zedboard/jni/SimpleIndicationWrapper.h\r\n    zedboard/jni/SimpleIndicationWrapper.cpp\r\n    zedboard/jni/SimpleRequestProxy.cpp\r\n    zedboard/jni/SimpleRequestProxy.h</tt></pre>\r\n</div></div>\r\n<div class=\"paragraph\"><p>CONNECTAL also generates <tt>GeneratedTypes.h</tt> for struct and enum types in the processed BSV source files:</p></div>\r\n<div class=\"listingblock\">\r\n<div class=\"content\">\r\n<pre><tt>    zedboard/jni/GeneratedTypes.h</tt></pre>\r\n</div></div>\r\n<div class=\"paragraph\"><p>CONNECTAL copies in standard and specified constraints files:</p></div>\r\n<div class=\"listingblock\">\r\n<div class=\"content\">\r\n<pre><tt>    zedboard/constraints/design_1_processing_system7_1_0.xdc\r\n    zedboard/constraints/zedboard.xdc</tt></pre>\r\n</div></div>\r\n<div class=\"paragraph\"><p>CONNECTAL generates several TCL files to run <tt>vivado</tt>.</p></div>\r\n<div class=\"paragraph\"><p>The <tt>board.tcl</tt> file specifies <tt>partname</tt>, <tt>boardname</tt>, and <tt>connectaldir</tt> for the other TCL scripts.</p></div>\r\n<div class=\"listingblock\">\r\n<div class=\"content\">\r\n<pre><tt>    zedboard/board.tcl</tt></pre>\r\n</div></div>\r\n<div class=\"paragraph\"><p>To generate an FPGA bit file, run <tt>make bits</tt>. This runs vivado with the <tt>mkzynqtop-impl.tcl</tt> script.</p></div>\r\n<div class=\"listingblock\">\r\n<div class=\"content\">\r\n<pre><tt>    zedboard/mkzynqtop-impl.tcl</tt></pre>\r\n</div></div>\r\n</div>\r\n<div class=\"sect2\">\r\n<h3 id=\"_make_verilog\">make verilog</h3>\r\n<div class=\"paragraph\"><p>Compiling to verilog results in the following verilog files:</p></div>\r\n<div class=\"listingblock\">\r\n<div class=\"content\">\r\n<pre><tt>    zedboard/verilog/top/mkSimpleIndicationProxySynth.v\r\n    zedboard/verilog/top/mkZynqTop.v</tt></pre>\r\n</div></div>\r\n<div class=\"paragraph\"><p>Verilog library files referenced in the design are copied for use in synthesis.</p></div>\r\n<div class=\"listingblock\">\r\n<div class=\"content\">\r\n<pre><tt>    zedboard/verilog/top/FIFO1.v\r\n    ...</tt></pre>\r\n</div></div>\r\n</div>\r\n<div class=\"sect2\">\r\n<h3 id=\"_make_bits\">make bits</h3>\r\n<div class=\"paragraph\"><p>Running <tt>make bits</tt> in the zedboard directory results in timing reports:</p></div>\r\n<div class=\"listingblock\">\r\n<div class=\"content\">\r\n<pre><tt>    zedboard/hw/mkzynqtop_post_place_timing_summary.rpt\r\n    zedboard/hw/mkzynqtop_post_route_timing_summary.rpt\r\n    zedboard/hw/mkzynqtop_post_route_timing.rpt</tt></pre>\r\n</div></div>\r\n<div class=\"paragraph\"><p>and some design checkpoints:</p></div>\r\n<div class=\"listingblock\">\r\n<div class=\"content\">\r\n<pre><tt>    zedboard/hw/mkzynqtop_post_synth.dcp\r\n    zedboard/hw/mkzynqtop_post_place.dcp\r\n    zedboard/hw/mkzynqtop_post_route.dcp</tt></pre>\r\n</div></div>\r\n<div class=\"paragraph\"><p>and the FPGA configuration file in .bit and .bin formats:</p></div>\r\n<div class=\"listingblock\">\r\n<div class=\"content\">\r\n<pre><tt>    zedboard/hw/mkZynqTop.bit\r\n    zedboard/hw/mkZynqTop.bin</tt></pre>\r\n</div></div>\r\n</div>\r\n<div class=\"sect2\">\r\n<h3 id=\"_make_android_exe\">make android_exe</h3>\r\n<div class=\"paragraph\"><p>CONNECTAL supports Android 4.0 on Zynq platforms. It generates\r\n<tt>jni/Android.mk</tt> which is used by <tt>ndk-build</tt> to create a native\r\nAndroid executable.</p></div>\r\n<div class=\"listingblock\">\r\n<div class=\"content\">\r\n<pre><tt>    make android_exe</tt></pre>\r\n</div></div>\r\n<div class=\"paragraph\"><p>This produces the ARM elf executable:</p></div>\r\n<div class=\"listingblock\">\r\n<div class=\"content\">\r\n<pre><tt>    libs/armeabi/android_exe</tt></pre>\r\n</div></div>\r\n</div>\r\n<div class=\"sect2\">\r\n<h3 id=\"_make_run\">make run</h3>\r\n<div class=\"paragraph\"><p>For Zynq platforms,</p></div>\r\n<div class=\"listingblock\">\r\n<div class=\"content\">\r\n<pre><tt>    make run</tt></pre>\r\n</div></div>\r\n<div class=\"paragraph\"><p>will copy the Android executable and FPGA configuration file to the\r\ntarget device, program the FPGA, and run the executable. See\r\n[run.android](../scripts/run.android) for details.</p></div>\r\n<div class=\"paragraph\"><p>It uses <tt>connectal/consolable/checkip</tt> to determine the IP address of the\r\ndevice via a USB console connection to the device. If the target is\r\nnot connected to the build machine via USB, specify the IP address of\r\nthe target manually:</p></div>\r\n<div class=\"listingblock\">\r\n<div class=\"content\">\r\n<pre><tt>    make RUNPARAM=ipaddr run</tt></pre>\r\n</div></div>\r\n<div class=\"paragraph\"><p>For PCIe platforms, <tt>make run</tt> programs the FPGA via USB and runs the software locally.</p></div>\r\n<div class=\"paragraph\"><p>For bluesim, <tt>make run</tt> invokes bluesim on the design and runs the software locally.</p></div>\r\n</div>\r\n</div>\r\n</div>\r\n<div class=\"sect1\">\r\n<h2 id=\"_shared_memory\">Shared Memory</h2>\r\n<div class=\"sectionbody\">\r\n<div class=\"sect2\">\r\n<h3 id=\"_shared_memory_hardware\">Shared Memory Hardware</h3>\r\n<div class=\"paragraph\"><p>In order to use shared memory, the hardware design instantiates a DMA module in Top.bsv:</p></div>\r\n<div class=\"listingblock\">\r\n<div class=\"content\">\r\n<pre><tt>   AxiDmaServer#(addrWidth,64) dma &lt;- mkAxiDmaServer(dmaIndicationProxy.ifc, readClients, writeClients);</tt></pre>\r\n</div></div>\r\n<div class=\"paragraph\"><p>The <tt>AxiDmaServer</tt> multiplexes read and write requests from the\r\nclients, translates DMA addresses to physical addresses, initiates bus\r\ntransactions to memory, and delivers responses to the clients.</p></div>\r\n<div class=\"paragraph\"><p>DMA requests are specified with respect to \"portal\" memory allocated\r\nby software and identified by a <tt>pointer</tt>.</p></div>\r\n<div class=\"paragraph\"><p>Requests and responses are tagged in order to enable pipelining.</p></div>\r\n<div class=\"listingblock\">\r\n<div class=\"content\">\r\n<pre><tt>    typedef struct {\r\n       SGLId pointer;\r\n       Bit#(MemOffsetSize) offset;\r\n       Bit#(8) burstLen;\r\n       Bit#(6)  tag;\r\n       } MemRequest deriving (Bits);\r\n\r\n    typedef struct {\r\n       Bit#(dsz) data;\r\n       Bit#(6) tag;\r\n       } MemData#(numeric type dsz) deriving (Bits);</tt></pre>\r\n</div></div>\r\n<div class=\"paragraph\"><p>Read clients implement the <tt>MemReadClient</tt> interface. On response to\r\nthe read, <tt>burstLen</tt> <tt>MemData</tt> items will be put to the <tt>readData</tt>\r\ninterface. The design must be ready to consume the data when it is\r\ndelivered from the memory bus or the system may hang.</p></div>\r\n<div class=\"listingblock\">\r\n<div class=\"content\">\r\n<pre><tt>    interface MemReadClient#(numeric type dsz);\r\n       interface GetF#(MemRequest)    readReq;\r\n       interface PutF#(MemData#(dsz)) readData;\r\n    endinterface</tt></pre>\r\n</div></div>\r\n<div class=\"paragraph\"><p>Write clients implement <tt>MemWriteClient</tt>. To complete the transaction,\r\n<tt>burstLen</tt> data items will be consumed from the <tt>writeData</tt>\r\ninterace. Upon completion of the request, the specified tag will be\r\nput to the <tt>writeDone</tt> interface. The data must be available when the\r\nwrite request is issued to the memory bus or the system may hang.</p></div>\r\n<div class=\"listingblock\">\r\n<div class=\"content\">\r\n<pre><tt>    interface MemWriteClient#(numeric type dsz);\r\n       interface GetF#(MemRequest)    writeReq;\r\n       interface GetF#(MemData#(dsz)) writeData;\r\n       interface PutF#(Bit#(6))       writeDone;\r\n    endinterface</tt></pre>\r\n</div></div>\r\n<div class=\"paragraph\"><p>A design may implement <tt>MemReadClient</tt> and <tt>MemWriteClient</tt> interfaces directly, or it may instantiate DmaReadBuffer or DmaWriteBuffer.</p></div>\r\n<div class=\"literalblock\">\r\n<div class=\"content\">\r\n<pre><tt> The `AxiDmaServer` is configured with physical address translations\r\nfor each region of memory identified by a `pointer`. A design using\r\nDMA must export the `DmaConfig` and `DmaIndication` interfaces of the\r\nDMA server.</tt></pre>\r\n</div></div>\r\n<div class=\"paragraph\"><p>Here are the DMA components of [memread_nobuff/Top.bsv](../examples/memread_nobuff/Top.bsv):</p></div>\r\n<div class=\"paragraph\"><p>Instantiate the design and its interface wrappers and proxies:</p></div>\r\n<div class=\"listingblock\">\r\n<div class=\"content\">\r\n<pre><tt>    MemreadIndicationProxy memreadIndicationProxy &lt;- mkMemreadIndicationProxy(MemreadIndication);\r\n    Memread memread &lt;- mkMemread(memreadIndicationProxy.ifc);\r\n    MemreadRequestWrapper memreadRequestWrapper &lt;- mkMemreadRequestWrapper(MemreadRequest,memread.request);</tt></pre>\r\n</div></div>\r\n<div class=\"paragraph\"><p>Collect the read and write clients:</p></div>\r\n<div class=\"listingblock\">\r\n<div class=\"content\">\r\n<pre><tt>    Vector#(1, MemReadClient#(64)) readClients = cons(memread.dmaClient, nil);\r\n    Vector#(0, MemReadClient#(64)) writeClients = nil;</tt></pre>\r\n</div></div>\r\n<div class=\"paragraph\"><p>Instantiate the DMA server and its wrapper and proxy:</p></div>\r\n<div class=\"listingblock\">\r\n<div class=\"content\">\r\n<pre><tt>    DmaIndicationProxy dmaIndicationProxy &lt;- mkDmaIndicationProxy(DmaIndication);\r\n    AxiDmaServer#(addrWidth,64) dma &lt;- mkAxiDmaServer(dmaIndicationProxy.ifc, readClients, writeClients);\r\n    DmaConfigWrapper dmaConfigWrapper &lt;- mkDmaConfigWrapper(DmaConfig,dma.request);</tt></pre>\r\n</div></div>\r\n<div class=\"paragraph\"><p>Include <tt>DmaConfig</tt> and <tt>DmaIndication</tt> in the portals of the design:</p></div>\r\n<div class=\"listingblock\">\r\n<div class=\"content\">\r\n<pre><tt>    Vector#(4,StdPortal) portals;\r\n    portals[0] = memreadRequestWrapper.portalIfc;\r\n    portals[1] = memreadIndicationProxy.portalIfc;\r\n    portals[2] = dmaConfigWrapper.portalIfc;\r\n    portals[3] = dmaIndicationProxy.portalIfc;</tt></pre>\r\n</div></div>\r\n<div class=\"paragraph\"><p>The code generation tools will then produce the software glue necessary for the shared memory support libraries to initialize the DMA \"library module\" included in the hardware.</p></div>\r\n</div>\r\n<div class=\"sect2\">\r\n<h3 id=\"_shared_memory_software\">Shared Memory Software</h3>\r\n<div class=\"paragraph\"><p>The software side instantiates the DmaConfig proxy and the DmaIndication wrapper:</p></div>\r\n<div class=\"listingblock\">\r\n<div class=\"content\">\r\n<pre><tt>    dma = new DmaConfigProxy(IfcNames_DmaConfig);\r\n    dmaIndication = new DmaIndication(dma, IfcNames_DmaIndication);</tt></pre>\r\n</div></div>\r\n<div class=\"paragraph\"><p>Call <tt>dma-&gt;alloc()</tt> to allocate DMA memory. Each chunk of portal\r\nmemory is identified by a file descriptor. Portal memory may be shared\r\nwith other processes. Portal memory is reference counted according to\r\nthe number of file descriptors associated with it.</p></div>\r\n<div class=\"listingblock\">\r\n<div class=\"content\">\r\n<pre><tt>    PortalAlloc *srcAlloc;\r\n    dma-&gt;alloc(alloc_sz, &amp;srcAlloc);</tt></pre>\r\n</div></div>\r\n<div class=\"paragraph\"><p>Memory map it to make it accessible to software:</p></div>\r\n<div class=\"listingblock\">\r\n<div class=\"content\">\r\n<pre><tt>    srcBuffer = (unsigned int *)mmap(0, alloc_sz, PROT_READ|PROT_WRITE|PROT_EXEC, MAP_SHARED, srcAlloc-&gt;header.fd, 0);</tt></pre>\r\n</div></div>\r\n<div class=\"paragraph\"><p>CONNECTAL is currently using non-snooped interfaces, so the cache must be flushed and invalidated before hardware accesses portal memory:</p></div>\r\n<div class=\"listingblock\">\r\n<div class=\"content\">\r\n<pre><tt>    dma-&gt;dCacheFlushInval(srcAlloc, srcBuffer);</tt></pre>\r\n</div></div>\r\n<div class=\"paragraph\"><p>Call <tt>dma-&gt;reference()</tt> to get a pointer that may be passed to hardware:</p></div>\r\n<div class=\"listingblock\">\r\n<div class=\"content\">\r\n<pre><tt>    unsigned int ref_srcAlloc = dma-&gt;reference(srcAlloc);</tt></pre>\r\n</div></div>\r\n<div class=\"paragraph\"><p>This also transfers the DMA-to-physical address translation information to the hardware via the <tt>DmaConfig</tt> interface.</p></div>\r\n<div class=\"listingblock\">\r\n<div class=\"content\">\r\n<pre><tt>    device-&gt;startRead(ref_srcAlloc, numWords, burstLen, iterCnt);</tt></pre>\r\n</div></div>\r\n</div>\r\n</div>\r\n</div>\r\n<div class=\"sect1\">\r\n<h2 id=\"_notes\">Notes</h2>\r\n<div class=\"sectionbody\">\r\n<div class=\"sidebarblock\">\r\n<div class=\"content\">\r\n<div class=\"paragraph\"><p>stewart notes</p></div>\r\n<div class=\"paragraph\"><p>Currently there are no valid bits and no protections against bursts crossing page boundaries]</p></div>\r\n<div class=\"paragraph\"><p>There needs to be a way to synchronize Request actions and DMA reads, and to synchronize DMA writes with Indications, so that the writes complete to the coherence point before the indication is delivered to software. One could imagine an absurdly buffered memory interface and a rather direct path for I/O reads that could get out of order.</p></div>\r\n</div></div>\r\n</div>\r\n</div>\r\n<div class=\"sect1\">\r\n<h2 id=\"_portal_interface_structure\">Portal Interface Structure</h2>\r\n<div class=\"sectionbody\">\r\n<div class=\"paragraph\"><p>CONNECTAL connects software and hardware via portals, where each portal is\r\nan interface that allows one side to invoke methods on the other side.</p></div>\r\n<div class=\"paragraph\"><p>We generally call a portal from software to hardware to be a \"request\"\r\nand from hardware to software to be an \"indication\" interface.</p></div>\r\n<div class=\"imageblock seqdiag\">\r\n<div class=\"content\">\r\n<img src=\"request-response-21.png\" alt=\"request-response-21.png\" />\r\n</div>\r\n</div>\r\n<div class=\"paragraph\"><p>A portal is conceptually a FIFO, where the arguments to a method are\r\npackaged as a message. CONNECTAL generates a \"proxy\" that marshalls the\r\narguments to the method into a message and a \"wrapper\" that unpacks\r\nthe arguments and invokes the method.</p></div>\r\n<div class=\"paragraph\"><p>Currently, connectalgen includes a library that implements portals via\r\nmemory mapped hardware.</p></div>\r\n<div class=\"sect2\">\r\n<h3 id=\"_portal_device_drivers\">Portal Device Drivers</h3>\r\n<div class=\"paragraph\"><p>CONNECTAL uses a platform-specific driver to enable user-space applications\r\nto memory-map each portal used by the application and to enable the\r\napplication to wait for interrupts from the hardware.</p></div>\r\n<div class=\"paragraph\"><p>indexterm:pcieportal\r\nindexterm:zynqportal</p></div>\r\n<div class=\"ulist\"><ul>\r\n<li>\r\n<p>\r\npcieportal.ko\r\n</p>\r\n</li>\r\n<li>\r\n<p>\r\nzynqportal.ko\r\n</p>\r\n</li>\r\n</ul></div>\r\n<div class=\"paragraph\"><p>CONNECTAL also uses a generic driver to enable the applications to allocate DRAM that will be shared with the hardware and to send the memory mapping of that memory to the hardware.</p></div>\r\n<div class=\"ulist\"><ul>\r\n<li>\r\n<p>\r\nportalmem.ko\r\n</p>\r\n</li>\r\n</ul></div>\r\n</div>\r\n<div class=\"sect2\">\r\n<h3 id=\"_portal_memory_map\">Portal Memory Map</h3>\r\n<div class=\"paragraph\"><p>CONNECTAL currently supports up to 15 portals connected between software and hardware, for a total of 1MB of address space. It also provides a directory.</p></div>\r\n<div class=\"tableblock\">\r\n<table rules=\"all\"\r\nwidth=\"100%\"\r\nframe=\"border\"\r\ncellspacing=\"0\" cellpadding=\"4\">\r\n<col width=\"50%\" />\r\n<col width=\"50%\" />\r\n<thead>\r\n<tr>\r\n<th align=\"left\" valign=\"top\"> Base address </th>\r\n<th align=\"left\" valign=\"top\"> Function</th>\r\n</tr>\r\n</thead>\r\n<tbody>\r\n<tr>\r\n<td align=\"left\" valign=\"top\"><p class=\"table\">0x00000</p></td>\r\n<td align=\"left\" valign=\"top\"><p class=\"table\">Directory that maps portal identifier to portal number</p></td>\r\n</tr>\r\n<tr>\r\n<td align=\"left\" valign=\"top\"><p class=\"table\">0x10000</p></td>\r\n<td align=\"left\" valign=\"top\"><p class=\"table\">Portal 0</p></td>\r\n</tr>\r\n<tr>\r\n<td align=\"left\" valign=\"top\"><p class=\"table\">0x20000</p></td>\r\n<td align=\"left\" valign=\"top\"><p class=\"table\">Portal 1</p></td>\r\n</tr>\r\n<tr>\r\n<td align=\"left\" valign=\"top\"><p class=\"table\">0x30000</p></td>\r\n<td align=\"left\" valign=\"top\"><p class=\"table\">Portal 2</p></td>\r\n</tr>\r\n<tr>\r\n<td align=\"left\" valign=\"top\"><p class=\"table\">0x40000</p></td>\r\n<td align=\"left\" valign=\"top\"><p class=\"table\">Portal 3</p></td>\r\n</tr>\r\n<tr>\r\n<td align=\"left\" valign=\"top\"><p class=\"table\">0x50000</p></td>\r\n<td align=\"left\" valign=\"top\"><p class=\"table\">Portal 4</p></td>\r\n</tr>\r\n<tr>\r\n<td align=\"left\" valign=\"top\"><p class=\"table\">0x60000</p></td>\r\n<td align=\"left\" valign=\"top\"><p class=\"table\">Portal 5</p></td>\r\n</tr>\r\n<tr>\r\n<td align=\"left\" valign=\"top\"><p class=\"table\">0x70000</p></td>\r\n<td align=\"left\" valign=\"top\"><p class=\"table\">Portal 6</p></td>\r\n</tr>\r\n<tr>\r\n<td align=\"left\" valign=\"top\"><p class=\"table\">0x80000</p></td>\r\n<td align=\"left\" valign=\"top\"><p class=\"table\">Portal 7</p></td>\r\n</tr>\r\n<tr>\r\n<td align=\"left\" valign=\"top\"><p class=\"table\">0x90000</p></td>\r\n<td align=\"left\" valign=\"top\"><p class=\"table\">Portal 8</p></td>\r\n</tr>\r\n<tr>\r\n<td align=\"left\" valign=\"top\"><p class=\"table\">0xa0000</p></td>\r\n<td align=\"left\" valign=\"top\"><p class=\"table\">Portal 9</p></td>\r\n</tr>\r\n<tr>\r\n<td align=\"left\" valign=\"top\"><p class=\"table\">0xb0000</p></td>\r\n<td align=\"left\" valign=\"top\"><p class=\"table\">Portal 10</p></td>\r\n</tr>\r\n<tr>\r\n<td align=\"left\" valign=\"top\"><p class=\"table\">0xc0000</p></td>\r\n<td align=\"left\" valign=\"top\"><p class=\"table\">Portal 11</p></td>\r\n</tr>\r\n<tr>\r\n<td align=\"left\" valign=\"top\"><p class=\"table\">0xd0000</p></td>\r\n<td align=\"left\" valign=\"top\"><p class=\"table\">Portal 12</p></td>\r\n</tr>\r\n<tr>\r\n<td align=\"left\" valign=\"top\"><p class=\"table\">0xe0000</p></td>\r\n<td align=\"left\" valign=\"top\"><p class=\"table\">Portal 13</p></td>\r\n</tr>\r\n<tr>\r\n<td align=\"left\" valign=\"top\"><p class=\"table\">0xf0000</p></td>\r\n<td align=\"left\" valign=\"top\"><p class=\"table\">Portal 14</p></td>\r\n</tr>\r\n</tbody>\r\n</table>\r\n</div>\r\n<div class=\"paragraph\"><p>Each portal uses 64KB of address space, divided equally into 4 sections:</p></div>\r\n<div class=\"tableblock\">\r\n<table rules=\"all\"\r\nwidth=\"100%\"\r\nframe=\"border\"\r\ncellspacing=\"0\" cellpadding=\"4\">\r\n<col width=\"50%\" />\r\n<col width=\"50%\" />\r\n<thead>\r\n<tr>\r\n<th align=\"left\" valign=\"top\"> Base address </th>\r\n<th align=\"left\" valign=\"top\"> Function</th>\r\n</tr>\r\n</thead>\r\n<tbody>\r\n<tr>\r\n<td align=\"left\" valign=\"top\"><p class=\"table\">0x0000</p></td>\r\n<td align=\"left\" valign=\"top\"><p class=\"table\">Request FIFO base</p></td>\r\n</tr>\r\n<tr>\r\n<td align=\"left\" valign=\"top\"><p class=\"table\">0x4000</p></td>\r\n<td align=\"left\" valign=\"top\"><p class=\"table\">Request register base</p></td>\r\n</tr>\r\n<tr>\r\n<td align=\"left\" valign=\"top\"><p class=\"table\">0x8000</p></td>\r\n<td align=\"left\" valign=\"top\"><p class=\"table\">Indication FIFO base</p></td>\r\n</tr>\r\n<tr>\r\n<td align=\"left\" valign=\"top\"><p class=\"table\">0xc000</p></td>\r\n<td align=\"left\" valign=\"top\"><p class=\"table\">Indication register base</p></td>\r\n</tr>\r\n</tbody>\r\n</table>\r\n</div>\r\n<div class=\"paragraph\"><p>Although each portal only passes messages in one direction, it\r\nsupports two way communication. For \"request\" portals, the indication\r\npath is used to communicate that a message send failed.</p></div>\r\n</div>\r\n<div class=\"sect2\">\r\n<h3 id=\"_portal_fifos\">Portal FIFOs</h3>\r\n<div class=\"paragraph\"><p>Each method is implemented as a FIFO to or from hardware. Each FIFO is allocated 256 bytes of address space.</p></div>\r\n<div class=\"tableblock\">\r\n<table rules=\"all\"\r\nwidth=\"100%\"\r\nframe=\"border\"\r\ncellspacing=\"0\" cellpadding=\"4\">\r\n<col width=\"50%\" />\r\n<col width=\"50%\" />\r\n<thead>\r\n<tr>\r\n<th align=\"left\" valign=\"top\"> base address </th>\r\n<th align=\"left\" valign=\"top\"> Function</th>\r\n</tr>\r\n</thead>\r\n<tbody>\r\n<tr>\r\n<td align=\"left\" valign=\"top\"><p class=\"table\">0x0000</p></td>\r\n<td align=\"left\" valign=\"top\"><p class=\"table\">Request method 0 FIFO</p></td>\r\n</tr>\r\n<tr>\r\n<td align=\"left\" valign=\"top\"><p class=\"table\">0x0100</p></td>\r\n<td align=\"left\" valign=\"top\"><p class=\"table\">Request method 1 FIFO</p></td>\r\n</tr>\r\n<tr>\r\n<td align=\"left\" valign=\"top\"><p class=\"table\">&#8230;</p></td>\r\n<td align=\"left\" valign=\"top\"><p class=\"table\">&#8230;</p></td>\r\n</tr>\r\n<tr>\r\n<td align=\"left\" valign=\"top\"><p class=\"table\">0x8000</p></td>\r\n<td align=\"left\" valign=\"top\"><p class=\"table\">Indication method 0 FIFO</p></td>\r\n</tr>\r\n<tr>\r\n<td align=\"left\" valign=\"top\"><p class=\"table\">0x0100</p></td>\r\n<td align=\"left\" valign=\"top\"><p class=\"table\">Indication method 1 FIFO</p></td>\r\n</tr>\r\n<tr>\r\n<td align=\"left\" valign=\"top\"><p class=\"table\">&#8230;</p></td>\r\n<td align=\"left\" valign=\"top\"><p class=\"table\">&#8230;</p></td>\r\n</tr>\r\n</tbody>\r\n</table>\r\n</div>\r\n</div>\r\n<div class=\"sect2\">\r\n<h3 id=\"_portal_request_registers\">Portal Request Registers</h3>\r\n<div class=\"tableblock\">\r\n<table rules=\"all\"\r\nwidth=\"100%\"\r\nframe=\"border\"\r\ncellspacing=\"0\" cellpadding=\"4\">\r\n<col width=\"50%\" />\r\n<col width=\"50%\" />\r\n<thead>\r\n<tr>\r\n<th align=\"left\" valign=\"top\"> Base address </th>\r\n<th align=\"left\" valign=\"top\"> Function</th>\r\n</tr>\r\n</thead>\r\n<tbody>\r\n<tr>\r\n<td align=\"left\" valign=\"top\"><p class=\"table\">0x4000</p></td>\r\n<td align=\"left\" valign=\"top\"><p class=\"table\">Request fired count</p></td>\r\n</tr>\r\n<tr>\r\n<td align=\"left\" valign=\"top\"><p class=\"table\">0x4004</p></td>\r\n<td align=\"left\" valign=\"top\"><p class=\"table\">Out of range write count</p></td>\r\n</tr>\r\n</tbody>\r\n</table>\r\n</div>\r\n</div>\r\n<div class=\"sect2\">\r\n<h3 id=\"_portal_indication_registers\">Portal Indication Registers</h3>\r\n<div class=\"tableblock\">\r\n<table rules=\"all\"\r\nwidth=\"100%\"\r\nframe=\"border\"\r\ncellspacing=\"0\" cellpadding=\"4\">\r\n<col width=\"33%\" />\r\n<col width=\"33%\" />\r\n<col width=\"33%\" />\r\n<thead>\r\n<tr>\r\n<th align=\"left\" valign=\"top\"> Base address </th>\r\n<th align=\"left\" valign=\"top\"> Function                    </th>\r\n<th align=\"left\" valign=\"top\"> Description</th>\r\n</tr>\r\n</thead>\r\n<tbody>\r\n<tr>\r\n<td align=\"left\" valign=\"top\"><p class=\"table\">0xc000</p></td>\r\n<td align=\"left\" valign=\"top\"><p class=\"table\">Interrupt status register</p></td>\r\n<td align=\"left\" valign=\"top\"><p class=\"table\">1 if this portal has any messages ready, 0 otherwise</p></td>\r\n</tr>\r\n<tr>\r\n<td align=\"left\" valign=\"top\"><p class=\"table\">0xC004</p></td>\r\n<td align=\"left\" valign=\"top\"><p class=\"table\">Interrupt enable register</p></td>\r\n<td align=\"left\" valign=\"top\"><p class=\"table\">Write 1 to enable interrupts, 0 to disable</p></td>\r\n</tr>\r\n<tr>\r\n<td align=\"left\" valign=\"top\"><p class=\"table\">0xC008</p></td>\r\n<td align=\"left\" valign=\"top\"><p class=\"table\">Method count?</p></td>\r\n<td align=\"left\" valign=\"top\"><p class=\"table\">Number of methods implemented by this portal</p></td>\r\n</tr>\r\n<tr>\r\n<td align=\"left\" valign=\"top\"><p class=\"table\">0xC00C</p></td>\r\n<td align=\"left\" valign=\"top\"><p class=\"table\">Underflow read count reg</p></td>\r\n<td align=\"left\" valign=\"top\"><p class=\"table\"></p></td>\r\n</tr>\r\n<tr>\r\n<td align=\"left\" valign=\"top\"><p class=\"table\">0xC010</p></td>\r\n<td align=\"left\" valign=\"top\"><p class=\"table\">Out of range read count reg</p></td>\r\n<td align=\"left\" valign=\"top\"><p class=\"table\"></p></td>\r\n</tr>\r\n<tr>\r\n<td align=\"left\" valign=\"top\"><p class=\"table\">0xC014</p></td>\r\n<td align=\"left\" valign=\"top\"><p class=\"table\">Out of range write count reg</p></td>\r\n<td align=\"left\" valign=\"top\"><p class=\"table\"></p></td>\r\n</tr>\r\n<tr>\r\n<td align=\"left\" valign=\"top\"><p class=\"table\">0xC018</p></td>\r\n<td align=\"left\" valign=\"top\"><p class=\"table\">Ready channel indication</p></td>\r\n<td align=\"left\" valign=\"top\"><p class=\"table\">channel number + 1 if message is available, 0 otherwise</p></td>\r\n</tr>\r\n</tbody>\r\n</table>\r\n</div>\r\n</div>\r\n</div>\r\n</div>\r\n<div class=\"sect1\">\r\n<h2 id=\"_index\">Index</h2>\r\n<div class=\"sectionbody\">\r\n</div>\r\n</div>\r\n</div>\r\n<div id=\"footnotes\"><hr /></div>\r\n<div id=\"footer\">\r\n<div id=\"footer-text\">\r\nLast updated 2014-05-02 16:02:41 EDT\r\n</div>\r\n</div>\r\n</body>\r\n</html>\r\n"
  },
  {
    "path": "doc/ifdef.md",
    "content": "--BSC\n\n  ZYNQ is defined for the following platforms: [zc702,zedboard]\n  PCIE is defined for the following platforms: [ac701, kc705, vc707]\n  SIMULATION is defined for the following platforms: [bsim, bsim_pcie] \n\n--CPP\n\n  ZYNQ is defined for the following platforms: [zedboard, zc702]\n"
  },
  {
    "path": "doc/library/Makefile",
    "content": "# Makefile for Sphinx documentation\n#\n\n# You can set these variables from the command line.\nSPHINXOPTS    =\nSPHINXBUILD   = sphinx-build\nPAPER         =\nBUILDDIR      = build\n\ninclude ../../Makefile.version\n\n# User-friendly check for sphinx-build\nifeq ($(shell which $(SPHINXBUILD) >/dev/null 2>&1; echo $$?), 1)\n$(error The '$(SPHINXBUILD)' command was not found. Make sure you have Sphinx installed, then set the SPHINXBUILD environment variable to point to the full path of the '$(SPHINXBUILD)' executable. Alternatively you can add the directory with the executable to your PATH. If you don't have Sphinx installed, grab it from http://sphinx-doc.org/)\nendif\n\n# Internal variables.\nPAPEROPT_a4     = -D latex_paper_size=a4\nPAPEROPT_letter = -D latex_paper_size=letter\nALLSPHINXOPTS   = -d $(BUILDDIR)/doctrees $(PAPEROPT_$(PAPER)) $(SPHINXOPTS) source\n# the i18n builder cannot share the environment and doctrees with the others\nI18NSPHINXOPTS  = $(PAPEROPT_$(PAPER)) $(SPHINXOPTS) source\n\n.PHONY: help clean html dirhtml singlehtml pickle json htmlhelp qthelp devhelp epub latex latexpdf text man changes linkcheck doctest gettext\n\nhelp:\n\t@echo \"Please use \\`make <target>' where <target> is one of\"\n\t@echo \"  html       to make standalone HTML files\"\n\t@echo \"  dirhtml    to make HTML files named index.html in directories\"\n\t@echo \"  singlehtml to make a single large HTML file\"\n\t@echo \"  pickle     to make pickle files\"\n\t@echo \"  json       to make JSON files\"\n\t@echo \"  htmlhelp   to make HTML files and a HTML help project\"\n\t@echo \"  qthelp     to make HTML files and a qthelp project\"\n\t@echo \"  devhelp    to make HTML files and a Devhelp project\"\n\t@echo \"  epub       to make an epub\"\n\t@echo \"  latex      to make LaTeX files, you can set PAPER=a4 or PAPER=letter\"\n\t@echo \"  latexpdf   to make LaTeX files and run them through pdflatex\"\n\t@echo \"  latexpdfja to make LaTeX files and run them through platex/dvipdfmx\"\n\t@echo \"  text       to make text files\"\n\t@echo \"  man        to make manual pages\"\n\t@echo \"  texinfo    to make Texinfo files\"\n\t@echo \"  info       to make Texinfo files and run them through makeinfo\"\n\t@echo \"  gettext    to make PO message catalogs\"\n\t@echo \"  changes    to make an overview of all changed/added/deprecated items\"\n\t@echo \"  xml        to make Docutils-native XML files\"\n\t@echo \"  pseudoxml  to make pseudoxml-XML files for display purposes\"\n\t@echo \"  linkcheck  to check all external links for integrity\"\n\t@echo \"  doctest    to run all doctests embedded in the documentation (if enabled)\"\n\nclean:\n\trm -rf $(BUILDDIR)/*\n\nhtml: images\n\t$(SPHINXBUILD) -b html $(ALLSPHINXOPTS) $(BUILDDIR)/html\n\t@echo\n\t@echo \"Build finished. The HTML pages are in $(BUILDDIR)/html.\"\n\ndirhtml:\n\t$(SPHINXBUILD) -b dirhtml $(ALLSPHINXOPTS) $(BUILDDIR)/dirhtml\n\t@echo\n\t@echo \"Build finished. The HTML pages are in $(BUILDDIR)/dirhtml.\"\n\nsinglehtml:\n\t$(SPHINXBUILD) -b singlehtml $(ALLSPHINXOPTS) $(BUILDDIR)/singlehtml\n\t@echo\n\t@echo \"Build finished. The HTML page is in $(BUILDDIR)/singlehtml.\"\n\npickle:\n\t$(SPHINXBUILD) -b pickle $(ALLSPHINXOPTS) $(BUILDDIR)/pickle\n\t@echo\n\t@echo \"Build finished; now you can process the pickle files.\"\n\njson:\n\t$(SPHINXBUILD) -b json $(ALLSPHINXOPTS) $(BUILDDIR)/json\n\t@echo\n\t@echo \"Build finished; now you can process the JSON files.\"\n\nhtmlhelp:\n\t$(SPHINXBUILD) -b htmlhelp $(ALLSPHINXOPTS) $(BUILDDIR)/htmlhelp\n\t@echo\n\t@echo \"Build finished; now you can run HTML Help Workshop with the\" \\\n\t      \".hhp project file in $(BUILDDIR)/htmlhelp.\"\n\nqthelp:\n\t$(SPHINXBUILD) -b qthelp $(ALLSPHINXOPTS) $(BUILDDIR)/qthelp\n\t@echo\n\t@echo \"Build finished; now you can run \"qcollectiongenerator\" with the\" \\\n\t      \".qhcp project file in $(BUILDDIR)/qthelp, like this:\"\n\t@echo \"# qcollectiongenerator $(BUILDDIR)/qthelp/connectal.qhcp\"\n\t@echo \"To view the help file:\"\n\t@echo \"# assistant -collectionFile $(BUILDDIR)/qthelp/connectal.qhc\"\n\ndevhelp:\n\t$(SPHINXBUILD) -b devhelp $(ALLSPHINXOPTS) $(BUILDDIR)/devhelp\n\t@echo\n\t@echo \"Build finished.\"\n\t@echo \"To view the help file:\"\n\t@echo \"# mkdir -p $$HOME/.local/share/devhelp/connectal\"\n\t@echo \"# ln -s $(BUILDDIR)/devhelp $$HOME/.local/share/devhelp/connectal\"\n\t@echo \"# devhelp\"\n\nepub:\n\t$(SPHINXBUILD) -b epub $(ALLSPHINXOPTS) $(BUILDDIR)/epub\n\t@echo\n\t@echo \"Build finished. The epub file is in $(BUILDDIR)/epub.\"\n\nlatex:\n\t$(SPHINXBUILD) -b latex $(ALLSPHINXOPTS) $(BUILDDIR)/latex\n\t@echo\n\t@echo \"Build finished; the LaTeX files are in $(BUILDDIR)/latex.\"\n\t@echo \"Run \\`make' in that directory to run these through (pdf)latex\" \\\n\t      \"(use \\`make latexpdf' here to do that automatically).\"\n\nlatexpdf: images\n\t$(SPHINXBUILD) -b latex $(ALLSPHINXOPTS) $(BUILDDIR)/latex\n\t@echo \"Running LaTeX files through pdflatex...\"\n\t$(MAKE) -C $(BUILDDIR)/latex all-pdf\n\t@echo \"pdflatex finished; the PDF files are in $(BUILDDIR)/latex.\"\n\nlatexpdfja:\n\t$(SPHINXBUILD) -b latex $(ALLSPHINXOPTS) $(BUILDDIR)/latex\n\t@echo \"Running LaTeX files through platex and dvipdfmx...\"\n\t$(MAKE) -C $(BUILDDIR)/latex all-pdf-ja\n\t@echo \"pdflatex finished; the PDF files are in $(BUILDDIR)/latex.\"\n\ntext:\n\t$(SPHINXBUILD) -b text $(ALLSPHINXOPTS) $(BUILDDIR)/text\n\t@echo\n\t@echo \"Build finished. The text files are in $(BUILDDIR)/text.\"\n\nman:\n\t$(SPHINXBUILD) -b man $(ALLSPHINXOPTS) $(BUILDDIR)/man\n\t@echo\n\t@echo \"Build finished. The manual pages are in $(BUILDDIR)/man.\"\n\ntexinfo:\n\t$(SPHINXBUILD) -b texinfo $(ALLSPHINXOPTS) $(BUILDDIR)/texinfo\n\t@echo\n\t@echo \"Build finished. The Texinfo files are in $(BUILDDIR)/texinfo.\"\n\t@echo \"Run \\`make' in that directory to run these through makeinfo\" \\\n\t      \"(use \\`make info' here to do that automatically).\"\n\ninfo:\n\t$(SPHINXBUILD) -b texinfo $(ALLSPHINXOPTS) $(BUILDDIR)/texinfo\n\t@echo \"Running Texinfo files through makeinfo...\"\n\tmake -C $(BUILDDIR)/texinfo info\n\t@echo \"makeinfo finished; the Info files are in $(BUILDDIR)/texinfo.\"\n\ngettext:\n\t$(SPHINXBUILD) -b gettext $(I18NSPHINXOPTS) $(BUILDDIR)/locale\n\t@echo\n\t@echo \"Build finished. The message catalogs are in $(BUILDDIR)/locale.\"\n\nchanges:\n\t$(SPHINXBUILD) -b changes $(ALLSPHINXOPTS) $(BUILDDIR)/changes\n\t@echo\n\t@echo \"The overview file is in $(BUILDDIR)/changes.\"\n\nlinkcheck:\n\t$(SPHINXBUILD) -b linkcheck $(ALLSPHINXOPTS) $(BUILDDIR)/linkcheck\n\t@echo\n\t@echo \"Link check complete; look for any errors in the above output \" \\\n\t      \"or in $(BUILDDIR)/linkcheck/output.txt.\"\n\ndoctest:\n\t$(SPHINXBUILD) -b doctest $(ALLSPHINXOPTS) $(BUILDDIR)/doctest\n\t@echo \"Testing of doctests in the sources finished, look at the \" \\\n\t      \"results in $(BUILDDIR)/doctest/output.txt.\"\n\nxml:\n\t$(SPHINXBUILD) -b xml $(ALLSPHINXOPTS) $(BUILDDIR)/xml\n\t@echo\n\t@echo \"Build finished. The XML files are in $(BUILDDIR)/xml.\"\n\npseudoxml:\n\t$(SPHINXBUILD) -b pseudoxml $(ALLSPHINXOPTS) $(BUILDDIR)/pseudoxml\n\t@echo\n\t@echo \"Build finished. The pseudo-XML files are in $(BUILDDIR)/pseudoxml.\"\n\nsource/devguide/connectalbuild-1.png: source/devguide/connectalbuild.pdf\n\tpdftoppm -png source/devguide/connectalbuild.pdf source/devguide/connectalbuild\n\nimages: source/devguide/connectalbuild-1.png\n\tmake -C source/design all\n\ninstall:\n\tsudo apt-get install poppler-utils\n\tsudo pip install docutils sphinx sphinxcontrib-makedomain sphinx-argparse\n\npublish:\n\tsed -i \"s/version = .*/version = '$(VERSION)'/\" source/conf.py\n\tsed -i \"s/release = .*/release = '$(VERSION)'/\" source/conf.py\n\tmake images html latexpdf\n\trsync -avz build/html/* ../../../doc/current/ref\n\trsync -av build/latex/connectal.pdf ../../../doc/current/ref\n"
  },
  {
    "path": "doc/library/source/bsv/addressgenerator.rst",
    "content": "Address Generator\n=================\n\n.. bsv:package:: AddressGenerator\n\nOne of the common patterns that leads to long critical paths in\ndesigns on the FPGA are counters and comparisons against\ncounters. This package contains a module for generating the sequence\nof addresses used by a memory read or write burst, along with a field\nindicating the last beat of the burst.\n\n.. bsv:struct:: AddrBeat#(numeric type addrWidth)\n\n   .. bsv:field:: Bit#(addrWidth) addr\n\n      The address for this beat of the request.\n\n   .. bsv:field:: Bit#(BurstLenSize) bc\n\n   .. bsv:field:: Bit#(MemTagSize) tag\n\n   .. bsv:field:: Bool    last\n\n\n.. bsv:interface:: AddressGenerator#(numeric type addrWidth, numeric type dataWidth)\n\n   .. bsv:subinterface:: Put#(PhysMemRequest#(addrWidth)) request\n\n      The interface for requesting a sequence of addresses.\n\n   .. bsv:subinterface:: Get#(AddrBeat#(addrWidth)) addrBeat\n\n      The interface for getting the address beats of the burst. There\n      is one pipeline cycle from the reuqest to the first address\n      beat.\n\n.. bsv:module:: mkAddressGenerator#()(AddressGenerator#(addrWidth, dataWidth))\n\n   Instantiates an address generator.\n"
  },
  {
    "path": "doc/library/source/bsv/arith.rst",
    "content": "Arith Package\n=============\n\n.. bsv:package:: Arith\n\nThe Arith package implements some functions that correspond to infix operators.\n\n.. bsv:function:: Bool booland(Bool x1, Bool x2)\n\n   Returns logical \"and\" of inputs. Named to avoid conflict with the Verilog keyword \"and\".\n\n.. bsv:function:: Bool boolor(Bool x1, Bool x2)\n\n   Returns logical \"or\" of inputs. Named to avoid conflict with the Verilog keyword \"or\".\n\n.. bsv:function:: Bool eq(a x1, a x2);\n\n.. bsv:function:: a add(a x1, a x2)\n\n   Returns sum of inputs. Requires Arith#(a).\n\n.. bsv:function:: a mul(a x1, a x2)\n\n   Returns product of inputs. Requires Arith#(a).\n\n.. bsv:function:: Bit#(b) rshift(Bit#(b) x1, Integer i)\n\n   Returns input right shifted by i bits.\n\n.. bsv:function:: Vector#(n, a) vadd(Vector#(n, a) x1, Vector#(n, a) x2)\n\n   Returns sum of input vectors.\n\n.. bsv:function:: Vector#(n, a) vmul(Vector#(n, a) x1, Vector#(n, a) x2)\n\n   Returns element-wise product of input vectors.\n\n.. bsv:function:: Vector#(n, Bit#(b)) vrshift(Vector#(n, Bit#(b)) x1, Integer i)\n\n   Right shifts the elements of the input vector by i bits.\n"
  },
  {
    "path": "doc/library/source/bsv/axistream.rst",
    "content": "AxiStream Package\n================\n\n.. bsv:package:: AxiStream\n\n\n\nAXI Stream Interfaces\n---------------------\n\n.. bsv:interface:: AxiStreamMaster#(numeric type dataWidth)\n\n   AXI stream source with dataWidth data bits.\n\n    .. bsv:method:: Bit#(dsz) tdata()\n\n       Returns the data from this beat if tvalid is asserted, otherwise returns undefined.\n    \n    .. bsv:method:: Bit#(TDiv#(dsz,8))     tkeep()\n\n       Returns the byte enables from this beat if tvalid is asserted, otherwise returns undefined.\n\n    .. bsv:method::  Bit#(1)               tlast()\n\n       Indicates if this is the last data beat of this transaction tvalid is asserted, otherwise returns undefined.\n\n    .. bsv:method::  Action                 tready(Bit#(1) v)\n\n       When tvalid and tready are both asserted the current data is\n       consumed. The value passed to tready may not depend on the output\n       of tvalid.\n\n    .. bsv:method:: Bit#(1)                tvalid()\n\n       Asserted when the data is valid.\n\n.. bsv:interface:: AxiStreamSlave#(numeric type dataWidth)\n\n   AXI stream sink with dataWidth data bits.\n\n    .. bsv:method:: Action tdata(Bit#(dsz) data)\n\n       The data passed from the source if tvalid is asserted, otherwise undefined..\n    \n    .. bsv:method:: Action tkeep(Bit#(TDiv#(dsz,8)) keep)\n\n       The byte enables passed from the source if tvalid is asserted, otherwise undefined.\n\n    .. bsv:method::  Action tlast(Bit#(1) last)\n\n       Indicates if this is the last data beat of this transaction tvalid is asserted, otherwise returns undefined.\n\n    .. bsv:method::  Bit#(1) tready()\n\n       Return 1 if ready to receive data, 0 otherwise.\n\n       When tvalid and tready are both asserted the current data is\n       consumed. The value passed to tready may not depend on the output\n       of tvalid.\n\n    .. bsv:method:: Action tvalid(Bit#(1) v)\n\n       Indicates the data from the source is valid.\n\nConnectable Type Instances\n--------------------------\n\n.. bsv:instance:: Connectable#(AxiStreamMaster#(dataWidth), AxiStreamSlave#(dataWidth))\n\n   .. bsv::module:: mkConnection#(AxiStreamMaster#(dataWidth) from, AxiStreamSlave#(dataWidth) to)(Empty)\n\n      Enables mkConnection(axiStreamMaster, axiStreamSlave)\n\n\n.. bsv:instance:: ToGetM#(AxiStreamMaster#(asz), Bit#(asz))\n\t\t\t\n   .. bsv:module: toGetM#(AxiStreamMaster#(asz) m)(Get#(Bit#(asz)))\n\n.. bsv:instance:: ToPutM#(AxiStreamSlave#(asz), Bit#(asz))\n\n   .. bsv:module: toPutM#(AxiStreamSlave#(asz) m)(Put#(Bit#(asz)))\n\nAXI Stream Type Classes and Instances   \n----------------------------------------\n\n.. bsv:typeclass:: ToAxiStream#(type atype, type btype)\n\n   .. bsv:function:: atype toAxiStream(btype b)\n\n      Convert to an AXI stream interface.\n\n.. bsv:typeclass:: MkAxiStream#(type atype, type btype)\n\n   .. bsv:module:: mkAxiStream#(btype b)(atype)\n\n      Create a module with an AXI Stream interface.\n\n.. bsv:instance:: MkAxiStream#(AxiStreamMaster#(dsize), FIFOF#(Bit#(dsize)))\n\n   .. bsv:module:: mkAxiStream#(FIFOF#(Bit#(dsize)) f)(AxiStreamMaster#(dsize));\n\n   Create an AXI Stream master from a FIFOF of bits\n\n.. bsv:instance:: MkAxiStream#(AxiStreamSlave#(dsize), FIFOF#(Bit#(dsize)))\n\n   .. bsv:module:: mkAxiStream#(FIFOF#(Bit#(dsize)) f)(AxiStreamSlave#(dsize));\n\n      Create an AXI Stream slave from a FIFOF of bits\n\n.. bsv:instance:: MkAxiStream#(AxiStreamMaster#(dsize), FIFOF#(Bit#(dsize)))\n\n   .. bsv:module:: mkAxiStream#(FIFOF#(Bit#(dsize)) f)(AxiStreamMaster#(dsize));\n\n   Create an AXI Stream master from a FIFOF of MemDataF\n\n.. bsv:instance:: MkAxiStream#(AxiStreamSlave#(dsize), FIFOF#(MemDataF#(dsize)))\n\n   .. bsv:module:: mkAxiStream#(FIFOF#(MemDataF#(dsize)) f)(AxiStreamSlave#(dsize));\n\n      Create an AXI Stream slave from a FIFOF of MemDataF\n\n.. bsv:instance:: MkAxiStream#(AxiStreamMaster#(dsize), PipeOut#(dtype))\n\n   .. bsv:module:: mkAxiStream#(PipeOut#(dtype) f)(AxiStreamMaster#(dsize));\n\n   Create an AXI Stream master from a PipeOut#(dtype)\n\n.. bsv:instance:: MkAxiStream#(AxiStreamSlave#(dsize), FIFOF#(PipeIn#(dtype))\n\n   .. bsv:module:: mkAxiStream#(PipeIn#(dtype) f)(AxiStreamSlave#(dsize));\n\n      Create an AXI Stream slave from a PipeIn#(dtype)\n"
  },
  {
    "path": "doc/library/source/bsv/bsv.rst",
    "content": "=======================\nConnectal BSV Libraries\n=======================\n\n.. toctree::\n   :maxdepth: 2\n   :numbered:\n\n   addressgenerator.rst\n   arith.rst\n   axistream.rst\n   ctrlmux.rst\n   hostinterface.rst\n   leds.rst\n   memportal.rst\n   memreadengine.rst\n   memtypes.rst\n   mmu.rst\n   pipe.rst\n   portal.rst\n"
  },
  {
    "path": "doc/library/source/bsv/ctrlmux.rst",
    "content": "CtrlMux Package\n=====================\n\n.. bsv:package:: CtrlMux\n\n.. bsv:module:: mkInterruptMux#(Vector#(numPortals,MemPortal#(aw,dataWidth)) portals)(ReadOnly#(Bool))\n\n   Used by BsimTop, PcieTop, and ZynqTop. Takes a vector of MemPortals and returns a boolean indicating whether any of the portals has indication method data available.\n\n.. bsv:module:: mkSlaveMux#(Vector#(numPortals,MemPortal#(aw,dataWidth)) portals)(PhysMemSlave#(addrWidth,dataWidth))\n\n   Takes a vector of MemPortals and returns a PhysMemSlave combining them.\n\n"
  },
  {
    "path": "doc/library/source/bsv/hostinterface.rst",
    "content": "HostInterface Package\n=====================\n\nThe HostInterface package provides host-specific typedefs and interfaces.\n\n.. bsv:package:: HostInterface\n\nHost-Specific Constants\n------------------------\n\n.. bsv:typedef:: DataBusWidth\n\n   Width in bits of the data bus connected to host shared memory.\n\n.. bsv:typedef:: PhysAddrWidth\n\n   Width in bits of physical addresses on the data bus connected to host shared memory.\n\n.. bsv:typedef:: NumberOfMasters\n\n   Number of memory interfaces used for connecting to host shared memory.\n\nHost-Specific Interfaces\n------------------------\n\n.. bsv:interface:: BsimHost\n\n   Host interface for the bluesim platform\n\n.. bsv:interface:: PcieHost\n\n   Host interface for PCIe-attached FPGAs such as vc707 and kc705\n\n.. bsv:interface:: ZynqHost\n\n   Host interface for Zynq FPGAs such as zedboard, zc702, zc706, and zybo.\n\n   The Zc706 is a ZynqHost even when it is plugged into a PCIe slot.\n\nApplication-Specific Types\n--------------------------\n\n.. bsv:typedef:: PinType\n\n   Specifies the type of the application pins interface. Defined from PIN_TYPE.\n\n"
  },
  {
    "path": "doc/library/source/bsv/leds.rst",
    "content": "Leds Package\n=====================\n\n.. bsv:package:: Leds\n\n.. bsv:interface:: LEDS\n\n.. bsv:typedef:: LedsWidth\n\n   Defined to be the number of default LEDs on the FPGA board.\n\n   The Zedboard has 8, Zc706 has 4, ...\n\n.. bsv:method:: Bit#(LedsWidth) leds()\n\n"
  },
  {
    "path": "doc/library/source/bsv/memportal.rst",
    "content": "MemPortal Package\n=================\n\n.. bsv:package:: MemPortal\n\n\nmkMemPortal Module\n------------------\n\n.. bsv:module:: mkMemPortal#(Bit#(slaveDataWidth) ifcId, PipePortal#(numRequests, numIndications, slaveDataWidth) portal)(MemPortal#(slaveAddrWidth, slaveDataWidth))\n\n   Takes an interface identifier and a PipePortal and returns a MemPortal.\n\n"
  },
  {
    "path": "doc/library/source/bsv/memreadengine.rst",
    "content": "MemReadEngine Package\n=====================\n\n.. bsv:package:: MemReadEngine\n\n.. bsv:module:: mkMemReadEngine(MemReadEngine#(busWidth, userWidth, cmdQDepth, numServers))\n\n   Creates a MemReadEngine with default 256 bytes of buffer per server.\n\n.. bsv:module:: mkMemReadEngineBuff#(Integer bufferSizeBytes) (MemReadEngine#(busWidth, userWidth, cmdQDepth, numServers))\n\n   Creates a MemReadEngine with the specified buffer size.\n\n"
  },
  {
    "path": "doc/library/source/bsv/memtypes.rst",
    "content": "MemTypes Package\n================\n\n.. bsv:package:: MemTypes\n\nConstants\n------------------\n\n.. bsv:typedef:: Bit#(32) SGLId\n.. bsv:typedef:: 44 MemOffsetSize\n.. bsv:typedef:: 6 MemTagSize\n.. bsv:typedef:: 8 BurstLenSize\n.. bsv:typedef:: 32 MemServerTags\n.. bsv:typedef:: TDiv#(DataBusSize,8) ByteEnableSize\n\nData Types\n----------\n\n.. bsv:struct:: PhysMemRequest#(numeric type addrWidth, dataWidth)\n\n   A memory request containing a physical memory address\n\n   .. bsv:field:: Bit#(addrWidth) addr\n\n      Physical address to read or write\n\n   .. bsv:field:: Bit#(BurstLenSize) burstLen\n\n      Length of read or write burst, in bytes.  The number of beats of the request will be the burst length divided by the physical width of the memory interface.\n\n   .. bsv:field:: Bit#(MemTagSize) tag\n\n   .. bsv:field:: Bit#(TDiv#(dataWidth,8)) firstbe\n\n   .. bsv:field:: Bit#(TDiv#(dataWidth,8)) lastbe\n\n      If BYTE_ENABLESis defined as aBSV preprocessor macro,byte write\n      enables are added to PhysMemRequest, intwo fields: firstbe and\n      lastbe.The idea is to enable writing any number of contiguous\n      bytes even if it is less than the width of the shared memory\n      data bus.\n\n      These have roughly the same semantics as in PCIE. The write\n      enable in firstbe apply to the first beat of a burst request and\n      those inlastbe apply to the last beat of a multi-beat burst\n      request. Intervening beats of a burst request enable the write\n      of all beats of that burst.\n\n.. bsv:struct:: MemRequest\n\n   A logical memory read or write request. The linear offset of the request will be translated by an MMU according to the specified scatter-gather list.\n\n   .. bsv:field:: SGLId sglId\n\n      Indicates which scatter-gather list the MMU should use when translating the address\n\n   .. bsv:field:: Bit#(MemOffsetSize) offset\n\n      Linear byte offset to read or write.\n\n   .. bsv:field:: Bit#(BurstLenSize) burstLen\n\n      Length of read or write burst, in bytes. The number of beats of the request will be the burst length divided by the physical width of the memory interface.\n\n   .. bsv:field:: Bit#(MemTagSize)  tag\n\n   .. bsv:field:: Bit#(ByteEnableSize) firstbe\n\n   .. bsv:field:: Bit#(ByteEnableSize) lastbe\n\n      If BYTE_ENABLESis defined as aBSV preprocessor macro,byte write\n      enables are added to PhysMemRequest, intwo fields: firstbe and\n      lastbe.The idea is to enable writing any number of contiguous\n      bytes even if it is less than the width of the shared memory\n      data bus.\n\n      These have roughly the same semantics as in PCIE. The write\n      enable in firstbe apply to the first beat of a burst request and\n      those inlastbe apply to the last beat of a multi-beat burst\n      request. Intervening beats of a burst request enable the write\n      of all beats of that burst.\n\n\n.. bsv:struct:: MemData#(numeric type dsz)\n\n   One beat of the payload of a physical or logical memory read or write request.\n\n   .. bsv:field:: Bit#(dsz) data\n\n      One data beat worth of data.\n\n   .. bsv:field:: Bit#(MemTagSize) tag\n\n      Indicates to which request this beat belongs.\n\n   .. bsv:field:: Bool last\n\n      Indicates that this is the last beat of a burst.\n\n\n.. bsv:struct:: MemDataF#(numeric type dsz)\n\n   One beat of the payload of a physical or logical memory read or write request. Used by MemReadEngine and MemWriteEngine.\n\n   .. bsv:field:: Bit#(dsz) data\n\n      One data beat worth of data.\n\n   .. bsv:field:: Bit#(MemTagSize) tag\n\n      Indicates to which request this beat belongs.\n\n   .. bsv:field:: Bool first\n\n      Indicates that this is the first data beat of a request.\n\n   .. bsv:field:: Bool last\n\n      Indicates that this is the last data beat of a request.\n\nPhysical Memory Clients and Servers\n-----------------------------------\n\n.. bsv:interface:: PhysMemMaster#(numeric type addrWidth, numeric type dataWidth)\n\n   The physical memory interface exposed by MemMaster. For example, connects via AXI to Zynq or via PCIe to x86 memory.\n\n   .. bsv:subinterface:: PhysMemReadClient#(addrWidth, dataWidth) read_client\n\n   .. bsv:subinterface:: PhysMemWriteClient#(addrWidth, dataWidth) write_client \n\n.. bsv:interface:: PhysMemReadClient#(numeric type asz, numeric type dsz)\n\n   .. bsv:subinterface:: Get#(PhysMemRequest#(asz))    readReq\n\n   .. bsv:subinterface:: Put#(MemData#(dsz)) readData\n\n.. bsv:interface:: PhysMemWriteClient#(numeric type asz, numeric type dsz)\n\n   .. bsv:subinterface:: Get#(PhysMemRequest#(asz))    writeReq\n\n   .. bsv:subinterface:: Get#(MemData#(dsz)) writeData\n\n   .. bsv:subinterface:: Put#(Bit#(MemTagSize))       writeDone\n\n.. bsv:interface:: PhysMemSlave#(numeric type addrWidth, numeric type dataWidth)\n\n   .. bsv:subinterface:: PhysMemReadServer#(addrWidth, dataWidth) read_server\n\n   .. bsv:subinterface:: PhysMemWriteServer#(addrWidth, dataWidth) write_server \n\n\n.. bsv:interface:: PhysMemReadServer#(numeric type asz, numeric type dsz)\n\n   .. bsv:subinterface:: Put#(PhysMemRequest#(asz)) readReq\n\n   .. bsv:subinterface:: Get#(MemData#(dsz))     readData\n\n\n.. bsv:interface:: PhysMemWriteServer#(numeric type asz, numeric type dsz)\n\n   .. bsv:subinterface:: Put#(PhysMemRequest#(asz)) writeReq\n\n   .. bsv:subinterface:: Put#(MemData#(dsz))     writeData\n\n   .. bsv:subinterface:: Get#(Bit#(MemTagSize))           writeDone\n\n\nMemory Clients and Servers\n--------------------------\n\nThese clients and servers operate on logical addresses. These are\ntranslated by an MMU before being issued to system memory.\n\n.. bsv:interface:: MemReadClient#(numeric type dsz)\n\n   The system memory read interface exported by a client of MemServer, such as MemReadEngine.\n\n   .. bsv:subinterface:: Get#(MemRequest)    readReq\n\n   .. bsv:subinterface:: Put#(MemData#(dsz)) readData\n\n\n.. bsv:interface:: MemWriteClient#(numeric type dsz)\n\n   The system memory write interface exported by a client of MemServer, such as MemWriteEngine.\n\n   .. bsv:subinterface:: Get#(MemRequest)    writeReq\n\n   .. bsv:subinterface:: Get#(MemData#(dsz)) writeData\n\n   .. bsv:subinterface:: Put#(Bit#(MemTagSize))       writeDone\n\n.. bsv:interface:: MemReadServer#(numeric type dsz)\n\n   The system memory read interface exported by MemServer.\n\n   .. bsv:subinterface:: Put#(MemRequest) readReq\n\n   .. bsv:subinterface:: Get#(MemData#(dsz))     readData\n\n\n.. bsv:interface:: MemWriteServer#(numeric type dsz)\n\n   The system memory write interface exported by MemServer.\n\n   .. bsv:subinterface:: Put#(MemRequest) writeReq\n\n   .. bsv:subinterface:: Put#(MemData#(dsz))     writeData\n\n   .. bsv:subinterface:: Get#(Bit#(MemTagSize)) writeDone\n\n\nMemory Engine Types\n-------------------\n\n.. bsv:struct:: MemengineCmd\n\n   A read or write request for a MemReadEngine or a MemWriteEngine. MemRead and MemWrite engines will issue one or more burst requests to satisfy the overall length of the request.\n\n   .. bsv:field:: SGLId sglId\n\n      Which memory object identifer (scatter gather list ID) the MMU should use to translate the addresses\n\n   .. bsv:field:: Bit#(MemOffsetSize) base\n\n      Logical base address of the request, as a byte offset\n\n   .. bsv:field:: Bit#(BurstLenSize) burstLen\n\n      Maximum burst length, in bytes.\n\n   .. bsv:field:: Bit#(32) len\n\n      Number of bytes to transfer. Must be a multiple of the data bus width.\n\n   .. bsv:field:: Bit#(MemTagSize) tag\n\n      Identifier for this request.\n\nMemory Engine Interfaces\n------------------------\n\n.. bsv:interface:: MemWriteEngineServer#(numeric type userWidth)\n\n   The interface used by one client of a MemWriteEngine.\n\n   .. bsv:subinterface:: Put#(MemengineCmd)       request\n\n   .. bsv:subinterface:: Get#(Bool)               done\n\n   .. bsv:subinterface:: PipeIn#(Bit#(userWidth)) data\n\n.. bsv:interface:: MemWriteEngine#(numeric type busWidth, numeric type userWidth, numeric type cmdQDepth, numeric type numServers)\n\n   A multi-client component that supports multi-burst writes to system memory.\n\n   .. bsv:subinterface:: MemWriteClient#(busWidth) dmaClient\n\n   .. bsv:subinterface:: Vector#(numServers, MemWriteEngineServer#(userWidth)) writeServers\n\n.. bsv:interface:: MemReadEngineServer#(numeric type userWidth)\n\n   The interface used by one client of a MemReadEngine.\n\n   .. bsv:subinterface:: Put#(MemengineCmd)        request\n\n   .. bsv:subinterface:: PipeOut#(MemDataF#(userWidth)) data\n      \n.. bsv:interface:: MemReadEngine#(numeric type busWidth, numeric type userWidth, numeric type cmdQDepth, numeric type numServers)\n\n   A multi-client component that supports multi-burst reads from system memory.\n\n   .. bsv:subinterface:: MemReadClient#(busWidth) dmaClient\n\n   .. bsv:subinterface:: Vector#(numServers, MemReadEngineServer#(userWidth)) readServers\n\n\nMemory Traffic Interfaces\n-------------------------\n\n\n.. bsv:interface:: DmaDbg\n\n   .. bsv:method:: ActionValue#(Bit#(64)) getMemoryTraffic()\n   .. bsv:method:: ActionValue#(DmaDbgRec) dbg()\n\nConnectable Instances\n---------------------\n\n.. bsv:instance:: Connectable#(MemReadClient#(dsz), MemReadServer#(dsz))\n\n.. bsv:instance:: Connectable#(MemWriteClient#(dsz), MemWriteServer#(dsz))\n\n.. bsv:instance:: Connectable#(PhysMemMaster#(addrWidth, busWidth), PhysMemSlave#(addrWidth, busWidth))\n\n.. bsv:instance:: Connectable#(PhysMemMaster#(32, busWidth), PhysMemSlave#(40, busWidth))\n\n\n\n\n"
  },
  {
    "path": "doc/library/source/bsv/mmu.rst",
    "content": "MMU Package\n===========\n\n.. bsv:package:: MMU\n\n.. bsv:typedef:: 32 MaxNumSGLists\n.. bsv:typedef:: Bit#(TLog#(MaxNumSGLists)) SGListId\n.. bsv:typedef:: 12 SGListPageShift0\n.. bsv:typedef:: 16 SGListPageShift4\n.. bsv:typedef:: 20 SGListPageShift8\n.. bsv:typedef:: 24 SGListPageShift12\n.. bsv:typedef:: Bit#(TLog#(MaxNumSGLists)) RegionsIdx\n\n.. bsv:typedef:: 8 IndexWidth\n\nAddress Translation\n-------------------\n\n.. bsv:struct:: AddrTransRequest\n\n   Address translation request type\n\n   .. bsv:field:: SGListId             id\n\n      Which object identifier to use.\n\n   .. bsv:field:: Bit#(MemOffsetSize) off\n\n      The address to translate.\n\n.. bsv:interface:: MMU#(numeric type addrWidth)\n\n   An address translator\n\n   .. bsv:subinterface:: MMURequest request\n\n      The interface of the MMU that is exposed to software as a portal.\n\n   .. bsv:subinterface:: Vector#(2,Server#(AddrTransRequest,Bit#(addrWidth))) addr\n\n      The address translation servers\n\n\n.. bsv:interface:: MMURequest;\n\n   The Connectal MMU maps linear offsets on objects identified by\n   sglId to dmaAddress. It is constructed from a list of\n   segments, where the segments are sorted by size in descending\n   order. Each segment must be one of the supported sizes.\n\n   .. bsv:method:: Action sglist(Bit#(32) sglId, Bit#(32) segmentIndex, Bit#(64) addr,  Bit#(32) len);\n\n      Updates the address of the segment number segmentIndex for object identified by sglId. The\n      address has been preshifted so that the final address may be\n      constructed by concatenating addr and offset within the segment.\n\n   .. bsv:method:: Action region(Bit#(32) sglId, Bit#(64) barr12, Bit#(32) idxOffset12, Bit#(64) barr8, Bit#(32) idxOffset8, Bit#(64) barr4, Bit#(32) idxOffset4, Bit#(64) barr0, Bit#(32) idxOffset0);\n\n      Updates the boundaries between the segments of different sizes for the object identified by sglId.\n\n      For example, if an offset to be translated is less than barr12,\n      then the target segment is of size SGListPageShift12 (2^24\n      bytes). If the offset is less than barr12, then idxOffset12 points to the first translation table entry for segments of that size\n\n      pbase      = offset >> segAddrSize + idxOffset\n      segNumber  = pbase + idxOffset\n      dmaBase    = translationTable[sglId,segNumber]\n      dmaAddress = {dmaBase[physAddrSize-segAddrSize-1:0],offset[segAddrSize-1:0]}\n\n   .. bsv:method:: Action idRequest(SpecialTypeForSendingFd fd);\n\n      Requests a new object identifier.\n\n   .. bsv:method:: Action idReturn(Bit#(32) sglId);\n\n      Indicates that the designated object is no longer in use. The MMU clears the translation entries for this object.\n\n   .. bsv:method:: Action setInterface(Bit#(32) interfaceId, Bit#(32) sglId);\n\n      This method is only implemented in software responders.\n\n.. bsv:interface:: MMUIndication;\n   .. bsv:method:: Action idResponse(Bit#(32) sglId);\n\n      Response from idRequest indicating the new object identifier sglId.\n\n   .. bsv:method:: Action configResp(Bit#(32) sglId);\n\n   .. bsv:method:: Action error(Bit#(32) code, Bit#(32) sglId, Bit#(64) offset, Bit#(64) extra);\n\n      Sent from the MMU when there is a translation error.\n\n.. bsv:struct:: DmaErrorType\n\n   .. bsv:field:: DmaErrorNone\n\n      Code 0 indicates no error.\n\n   .. bsv:field:: DmaErrorSGLIdOutOfRange_r\n\n      Code 1 indicates object identifier was out of range during a read request.\n\n   .. bsv:field:: DmaErrorSGLIdOutOfRange_w\n\n      Code 2 indicates object identifier was out of range during a read request.\n\n   .. bsv:field:: DmaErrorMMUOutOfRange_r\n\n      Code 3 indicates MMU identifier was out of range during a read request.\n\n   .. bsv:field:: DmaErrorMMUOutOfRange_w\n\n      Code 4 indicates MMU identifier was out of range during a read request.\n\n   .. bsv:field:: DmaErrorOffsetOutOfRange\n\n      Code 5 indicates offset was out of range for the designated object.\n\n   .. bsv:field:: DmaErrorSGLIdInvalid\n\n      Code 6 indicates the object identifier was out of range.\n\n   .. bsv:field:: DmaErrorTileTagOutOfRange\n\n      Code 7 indicates the tag was out of range for the requesting platform application tile.\n\n.. bsv:module:: mkMMU#(Integer iid, Bool hostMapped, MMUIndication mmuIndication)(MMU#(addrWidth))\n\n   Instantiates an address translator that stores a scatter-gather\n   list to define the logical to physical address mapping.\n\n   Parameter iid is the portal identifier of the MMURequest interface.\n\n   Parameter hostMapped is true for simulation.\n\n\n.. bsv:interface:: MemServerRequest;\n\n   .. bsv:method:: Action addrTrans(Bit#(32) sglId, Bit#(32) offset);\n\n      Requests an address translation\n\n   .. bsv:method:: Action setTileState(TileControl tc);\n\n      Changes tile status\n\n   .. bsv:method:: Action stateDbg(ChannelType rc)\n\n      Requests debug info for the specified channel type\n\n   .. bsv:method:: Action memoryTraffic(ChannelType rc);\n\n.. bsv:interface:: MemServerIndication;\n   .. bsv:method:: Action addrResponse(Bit#(64) physAddr);\n   .. bsv:method:: Action reportStateDbg(DmaDbgRec rec);\n   .. bsv:method:: Action reportMemoryTraffic(Bit#(64) words);\n   .. bsv:method:: Action error(Bit#(32) code, Bit#(32) sglId, Bit#(64) offset, Bit#(64) extra);\n"
  },
  {
    "path": "doc/library/source/bsv/pipe.rst",
    "content": "Pipe Package\n============\n\n.. bsv:package:: Pipe\n\nThe Pipe package is modeled on Bluespec, Inc's PAClib package. It\nprovides functions and modules for composing pipelines of operations.\n\nPipe Interfaces\n---------------\n\n.. bsv:interface:: PipeIn#(type a)\n\n   Corresponds to the input interface of a FIFOF.\n\n   .. bsv:method:: Action enq(a v)\n\n   .. bsv:method:: Bool notFull()\n\n.. bsv:interface:: PipeOut#(type a)\n\n   Corresponds to the output interface of a FIFOF.\n\n   .. bsv:method:: a first()\n\n   .. bsv:method:: Action deq()\n\n   .. bsv:method:: Bool notEmpty()\n\n.. bsv:typeclass:: ToPipeIn#(type a, type b)\n\n   .. bsv:function:: PipeIn#(a) toPipeIn(b in)\n\n      Returns a PipeIn to the object \"in\" with no additional buffering.\n\n.. bsv:typeclass:: ToPipeOut#(type a, type b)\n\n   .. bsv:function:: PipeOut#(a) toPipeOut(b in)\n\n      Returns a PipeOut from the object \"in\" with no additional buffering.\n\n.. bsv:typeclass:: MkPipeIn#(type a, type b)\n\n   .. bsv:module:: mkPipeIn#(b in)(PipeIn#(a))\n\n      Instantiates a module whose interface is a PipeIn to the input\n      parameter \"in\". Includes a FIFO buffering stage.\n\n.. bsv:typeclass:: MkPipeOut#(type a, type b)\n\n   .. bsv:module:: mkPipeOut#(b in)(PipeOut#(a))\n\n      Instantiates a module whose interface is PipeOut from the input\n      parameter \"in\". Includes a FIFO buffering stage.\n\n.. bsv:instance:: ToPipeIn#(a, FIFOF#(a))\n\n   Converts a FIFOF to a PipeIn.\n\n.. bsv:instance:: ToPipeOut#(a, function a pipefn())\n\n   Converts a function to a PipeOut.\n\n.. bsv:instance:: ToPipeOut#(a, Reg#(a))\n\n   Converts a register to a PipeOut.\n\n.. bsv:instance:: ToPipeIn#(Vector#(m, a), Gearbox#(m, n, a))\n\n   Converts a Gearbox to a PipeOut.\n\n.. bsv:instance:: ToPipeOut#(a, FIFOF#(a))\n\n   Converts a FIFOF to a PipeOut.\n\n.. bsv:instance:: ToPipeOut#(Vector#(n,a), MIMO#(k,n,sz,a))\n\n   Converts a MIMO to a PipeOut.\n\n.. bsv:instance:: ToPipeOut#(Vector#(n, a), Gearbox#(m, n, a))\n\n   Converts a Gearbox to a PipeOut.\n\n.. bsv:instance:: MkPipeOut#(a, Get#(a))\n\n   Instantiates a pipelined PipeOut from a Get interface.\n\n.. bsv:instance:: MkPipeIn#(a, Put#(a))\n\n   Instantiates a pipelined PipeIn to a Put interface.\n\nGet and Put Pipes\n-----------------\n\n.. bsv:instance:: ToGet #(PipeOut #(a), a)\n\n.. bsv:instance:: ToPut #(PipeIn #(a), a)\n\nConnectable Pipes\n-----------------\n\n.. bsv:instance:: Connectable#(PipeOut#(a),Put#(a))\n\n.. bsv:instance:: Connectable#(PipeOut#(a),PipeIn#(a))\n\n\nMapping over Pipes\n------------------\n\n.. bsv:function:: PipeOut#(a) toCountedPipeOut(Reg#(Bit#(n)) r, PipeOut#(a) pipe)\n\n.. bsv:function:: PipeOut#(Tuple2#(a,b)) zipPipeOut(PipeOut#(a) ina, PipeOut#(b) inb)\n\n   Returns a PipeOut whose elements are 2-tuples of the elements of the input pipes.\n\n\n.. bsv:function:: PipeOut#(b) mapPipe(function b f(a av), PipeOut#(a) apipe)\n\n   Returns a PipeOut that maps the function f to each element of the\n   input pipes with no buffering.\n\n.. bsv:module:: mkMapPipe#(function b f(a av), PipeOut#(a) apipe)(PipeOut#(b))\n\n   Instantiates a PipeOut that maps the function f to each element of\n   the input pipes using a FIFOF for buffering.\n\n.. bsv:function:: PipeIn#(a) mapPipeIn(function b f(a av), PipeIn#(b) apipe)\n\n   Returns a PipeIn applies the function f to each value that is enqueued.\n\n\nReducing Pipes\n--------------\n\n.. bsv::typeclass ReducePipe#( numeric type n, type a)\n\n   Instantiates a tree of logic to reduce the values of the input pipes using the combinepipe function.\n\n   .. bsv:module::  mkReducePipe (CombinePipe#(Tuple2#(a,a), a) combinepipe, PipeOut#(Vector#(n,a)) inpipe, PipeOut#(a) ifc)\n\n   .. bsv:module::  mkReducePipes (CombinePipe#(Tuple2#(a,a), a) combinepipe, Vector#(n,PipeOut#(a)) inpipe, PipeOut#(a) ifc)\n\n\n\nFunctions on Pipes of Vectors\n-----------------------------\n\n.. bsv:function:: PipeOut#(a) unvectorPipeOut(PipeOut#(Vector#(1,a)) in)\n\nFunneling and Unfunneling\n-------------------------\n\n.. bsv:module:: mkFunnel#(PipeOut#(Vector#(mk,a)) in)(PipeOut#(Vector#(m, a)))\n\n   Returns k Vectors of m elements for each Vector#(mk,a) element of the input pipe.\n\n.. bsv:module:: mkFunnel1#(PipeOut#(Vector#(k,a)) in)(PipeOut#(a))\n\n   Sames as mkFunnel, but returns k singleton elements for each vector\n   element of the input pipe.\n\n.. bsv:module:: mkFunnelGB1#(Clock slowClock, Reset slowReset, Clock fastClock, Reset fastReset, PipeOut#(Vector#(k,a)) in)(PipeOut#(a))\n\n   Same as mkFunnel1, but uses a Gearbox with a 1 to k ratio.\n\n.. bsv:module:: mkUnfunnel#(PipeOut#(Vector#(m,a)) in)(PipeOut#(Vector#(mk, a)))\n\n   The dual of mkFunnel. Consumes k elements from the input pipe, each of which is an\n   m-element vector, and returns an mk-element vector.\n\n.. bsv:module:: mkUnfunnelGB#(Clock slowClock, Reset slowReset, Clock fastClock, Reset fastReset, PipeOut#(Vector#(1,a)) in)(PipeOut#(Vector#(k, a)))\n\n   The same as mkUnfunnel, but uses a Gearbox with a 1-to-k.\n\n.. bsv:module:: mkRepeat#(UInt#(n) repetitions, PipeOut#(a) inpipe)(PipeOut#(a))\n\n   Returns a PipeOut which repeats each element of the input pipe the specified number of times.\n\n\n\nFork and Join\n-------------\n\nFork and Join with limited scalability\n\n.. bsv:module:: mkForkVector#(PipeOut#(a) inpipe)(Vector#(n, PipeOut#(a)))\n\n   Replicates each element of the input pipe to each of the output\n   pipes. It uses a FIFOF per output pipe.\n\n.. bsv:module:: mkSizedForkVector#(Integer size, PipeOut#(a) inpipe)(Vector#(n, PipeOut#(a)))\n\n   Used a SizedFIFOF for each of the output pipes.\n\n\n.. bsv:module:: mkJoin#(function c f(a av, b bv), PipeOut#(a) apipe, PipeOut#(b) bpipe)(PipeOut#(c))\n\n   Returns a PipeOut that applies the function f to the elements of\n   the input pipes, with no buffering.\n\n.. bsv:module:: mkJoinBuffered#(function c f(a av, b bv), PipeOut#(a) apipe, PipeOut#(b) bpipe)(PipeOut#(c))\n\n   Returns a PipeOut that applies the function f to the elements of\n   the input pipes, using a FIFOF to buffer the output.\n   \n.. bsv:module:: mkJoinVector#(function b f(Vector#(n, a) av), Vector#(n, PipeOut#(a)) apipes)(PipeOut#(b))\n\n   Same as mkJoin, but operates on a vector of PipeOut as input.\n\n\n\nFunnel Pipes\n---------------\n\nFork and Join with tree-based fanout and fanin for scalability.\n\nThese are used by MemReadEngine and MemWriteEngine.\n\n.. bsv:typedef:: Vector#(j,PipeOut#(a))   FunnelPipe#(numeric type j, numeric type k, type a, numeric type bitsPerCycle)\n\n.. bsv:typedef:: Vector#(k,PipeOut#(a)) UnFunnelPipe#(numeric type j, numeric type k, type a, numeric type bitsPerCycle)\n\n.. bsv:typeclass:: FunnelPipesPipelined#(numeric type j, numeric type k, type a, numeric type bpc)\n\n   .. bsv:module:: mkFunnelPipesPipelined#(Vector#(k,PipeOut#(a)) in) (FunnelPipe#(j,k,a,bpc))\n\n   .. bsv:module:: mkFunnelPipesPipelinedRR#(Vector#(k,PipeOut#(a)) in, Integer c) (FunnelPipe#(j,k,a,bpc))\n\n   .. bsv:module:: mkUnFunnelPipesPipelined#(Vector#(j,PipeOut#(Tuple2#(Bit#(TLog#(k)),a))) in) (UnFunnelPipe#(j,k,a,bpc))\n\n   .. bsv:module:: mkUnFunnelPipesPipelinedRR#(Vector#(j,PipeOut#(a)) in, Integer c) (UnFunnelPipe#(j,k,a,bpc))\n\n\n\n.. bsv:instance:: FunnelPipesPipelined#(1,1,a,bpc)\n\n.. bsv:instance:: FunnelPipesPipelined#(1,k,a,bpc)\n\n.. bsv:module:: mkUnFunnelPipesPipelinedInternal#(Vector#(1, PipeOut#(Tuple2#(Bit#(TLog#(k)),a))) in)(UnFunnelPipe#(1,k,a,bpc))\n\n.. bsv:module:: mkFunnelPipes#(Vector#(mk, PipeOut#(a)) ins)(Vector#(m, PipeOut#(a)))\n\n.. bsv:module:: mkFunnelPipes1#(Vector#(k, PipeOut#(a)) ins)(PipeOut#(a))\n\n.. bsv:module:: mkUnfunnelPipes#(Vector#(m, PipeOut#(a)) ins)(Vector#(mk, PipeOut#(a)))\n\n.. bsv:module:: mkPipelinedForkVector#(PipeOut#(a) inpipe, Integer id)(UnFunnelPipe#(1,k,a,bpc))\n\nDelimited Pipes\n---------------\n\n.. bsv:interface:: FirstLastPipe#(type a)\n\n   A pipe whose elements two-tuples of boolean values indicating first\n   and last in a series. The ttype a indicates the type of the counter\n   used.\n\n   .. bsv:subinterface:: PipeOut#(Tuple2#(Bool,Bool)) pipe\n\n      The pipe of delimited elements\n\n   .. bsv:method:: Action start(a count)\n\n      Starts the series of count elements\n\n.. bsv:module:: mkFirstLastPipe#()(FirstLastPipe#(a))\n\n   Creates a FirstLastPipe.\n\n.. bsv:struct:: RangeConfig#(type a)\n\n   The base, limit and step for mkRangePipeOut.\n\n   .. bsv:field:: a xbase\n\n   .. bsv:field:: a xlimit\n\n   .. bsv:field:: a xstep\n\n.. bsv:interface:: RangePipeIfc#(type a)\n\n   .. bsv:subinterface:: PipeOut#(a) pipe\n\n   .. bsv:method:: Bool isFirst()\n\n   .. bsv:method:: Bool isLast()\n\n   .. bsv:method:: Action start(RangeConfig#(a) cfg)\n\n.. bsv:module:: mkRangePipeOut#()(RangePipeIfc#(a))\n\n   Creates a Pipe of values from xbase to xlimit by xstep. Used by MemRead.\n\n"
  },
  {
    "path": "doc/library/source/bsv/portal.rst",
    "content": "Portal Package\n==============\n\n.. bsv:package:: Portal\n\nPipePortal Interface\n--------------------\n\n.. bsv:interface:: PipePortal#(numeric type numRequests, numeric type numIndications, numeric type slaveDataWidth)\n\n   .. bsv:method:: Bit#(16) messageSize(Bit#(16) methodNumber)\n\n      Returns the message size of the methodNumber method of the portal.\n\n  .. bsv:subinterface:: Vector#(numRequests, PipeIn#(Bit#(slaveDataWidth))) requests\n\n  .. bsv:subinterface:: Vector#(numIndications, PipeOut#(Bit#(slaveDataWidth))) indications\n\n\nMemPortal Interface\n-------------------\n\n.. bsv:interface:: MemPortal#(numeric type slaveAddrWidth, numeric type slaveDataWidth)\n\n   .. bsv:subinterface:: PhysMemSlave#(slaveAddrWidth,slaveDataWidth) slave\n   \n   .. bsv:subinterface:: ReadOnly#(Bool) interrupt\n\n   .. bsv:subinterface:: WriteOnly#(Bool) top\n\n.. bsv:function:: PhysMemSlave(_a,_d) getSlave(MemPortal#(_a,_d) p)\n\n.. bsv:function:: ReadOnly#(Bool) getInterrupt(MemPortal#(_a,_d) p)\n\n.. bsv:function:: Vector#(16,ReadOnly#(Bool)) getInterruptVector(Vector#(numPortals, MemPortal#(_a,_d)) portals)\n\n\nShareMemoryPortal Interface\n---------------------------\n\n.. bsv:interface:: SharedMemoryPortal#(numeric type dataBusWidth)\n\n   Should be in SharedMemoryPortal.bsv\n\n   .. bsv:subinterface:: MemReadClient(dataBusWidth) readClient\n\n   .. bsv:subinterface:: MemWriteClient#(dataBusWidth) writeClient\n\n   .. bsv:subinterface:: SharedMemoryPortalConfig cfg\n\n   .. bsv:subinterface:: ReadOnly#(Bool) interrupt\n\nConnectalTop Interface\n----------------------\n\n.. bsv:interface:: ConnectalTop#(numeric type addrWidth, numeric type dataWidth, type pins, numeric type numMasters)\n\n   Interface ConnectalTop is the interface exposed by the top module of a Connectal hardware design.\n\n   .. bsv:subinterface:: PhysMemSlave#(32,32) slave\n\n   .. bsv:subinterface:: Vector#(numMasters,PhysMemMaster#(addrWidth, dataWidth)) masters\n\n   .. bsv:subinterface:: Vector#(16,ReadOnly#(Bool)) interrupt\t\t   \n\n   .. bsv:subinterface:: LEDS leds\n\n   .. bsv:subinterface:: pins pins\n\nStdConnectalTop Typedef\n-----------------------\n\n.. bsv:typedef:: StdConnectalTop\n   :parameter: numeric type addrWidth\t \n   :returntype: ConnectalTop#(addrWidth,64,Empty,0)\n\n   Type StdConnectalTop indicates a Connectal hardware design with no\n   user defined pins and no user of host shared memory. The \"pins\"\n   interface is Empty and the number of masters is 0.\n\n.. bsv:typedef:: StdConnectalDmaTop\n   :parameter: numeric type addrWidth\n   :returnType:  ConnectalTop#(addrWidth,64,Empty,1)\n\n   Type StdConnectalDmaTop indicates a Connectal hardware design with\n   no user defined pins and a single client of host shared memory. The\n   \"pins\" interface is Empty and the number of masters is 1.\n"
  },
  {
    "path": "doc/library/source/bsvsphinx.py",
    "content": "# -*- coding: utf-8 -*-\n\"\"\"\n    The Bsv domain.\n\n    :copyright: Copyright 2007-2014 by the Sphinx team, see AUTHORS.\n                Copyright 2014 Quanta Research Cambridge.\n    :license: BSD, see LICENSE for details.\n\"\"\"\n\nfrom __future__ import print_function\n\nimport re\n\nfrom docutils import nodes\nfrom docutils.parsers.rst import directives\n\nfrom sphinx import addnodes\nfrom sphinx.roles import XRefRole\nfrom sphinx.locale import l_, _\nfrom sphinx.domains import Domain, ObjType, Index\nfrom sphinx.directives import ObjectDescription\nfrom sphinx.util.nodes import make_refnode\nfrom sphinx.util.docutils import SphinxDirective\nfrom sphinx.util.docfields import Field, GroupedField, TypedField\n\n\n# REs for Bsv signatures\nbsv_param_re = re.compile('^\\((.*)\\)$')\n\ndef _pseudo_parse_arglist(signode, arglist):\n    \"\"\"\"Parse\" a list of arguments separated by commas.\n\n    Arguments can have \"optional\" annotations given by enclosing them in\n    brackets.  Currently, this will split at any comma, even if it's inside a\n    string literal (e.g. default argument value).\n    \"\"\"\n    paramlist = addnodes.desc_parameterlist()\n    stack = [paramlist]\n    try:\n        for argument in arglist.split(','):\n            argument = argument.strip()\n            ends_open = ends_close = 0\n            while argument.startswith('['):\n                stack.append(addnodes.desc_optional())\n                stack[-2] += stack[-1]\n                argument = argument[1:].strip()\n            while argument.startswith(']'):\n                stack.pop()\n                argument = argument[1:].strip()\n            while argument.endswith(']'):\n                ends_close += 1\n                argument = argument[:-1].strip()\n            while argument.endswith('['):\n                ends_open += 1\n                argument = argument[:-1].strip()\n            if argument:\n                stack[-1] += addnodes.desc_parameter(argument, argument)\n            while ends_open:\n                stack.append(addnodes.desc_optional())\n                stack[-2] += stack[-1]\n                ends_open -= 1\n            while ends_close:\n                stack.pop()\n                ends_close -= 1\n        if len(stack) != 1:\n            raise IndexError\n    except IndexError:\n        # if there are too few or too many elements on the stack, just give up\n        # and treat the whole argument list as one argument, discarding the\n        # already partially populated paramlist node\n        signode += addnodes.desc_parameterlist()\n        signode[-1] += addnodes.desc_parameter(arglist, arglist)\n    else:\n        signode += paramlist\n\n\nclass BsvObject(ObjectDescription):\n    \"\"\"\n    Description of a general Bsv object.\n    \"\"\"\n    option_spec = {\n        'noindex': directives.flag,\n        'package': directives.unchanged,\n        'annotation': directives.unchanged,\n        'parameter': directives.unchanged,\n        'returntype': directives.unchanged,\n    }\n\n    doc_field_types = [\n        TypedField('parameter', label=l_('Parameters'),\n                   names=('param', 'parameter', 'arg', 'argument',\n                          'keyword', 'kwarg', 'kwparam'),\n                   typerolename='obj', typenames=('paramtype', 'type'),\n                   can_collapse=True),\n        TypedField('variable', label=l_('Variables'), rolename='obj',\n                   names=('var', 'ivar', 'cvar'),\n                   typerolename='obj', typenames=('vartype',),\n                   can_collapse=True),\n        GroupedField('exceptions', label=l_('Raises'), rolename='exc',\n                     names=('raises', 'raise', 'exception', 'except'),\n                     can_collapse=True),\n        Field('returnvalue', label=l_('Returns'), has_arg=False,\n              names=('returns', 'return')),\n        Field('returntype', label=l_('Return type'), has_arg=False,\n              names=('rtype',)),\n    ]\n\n    def get_signatures(self):\n        siglines = ObjectDescription.get_signatures(self)\n        return siglines\n\n    def get_signature_prefix(self, sig):\n        \"\"\"May return a prefix to put before the object name in the\n        signature.\n        \"\"\"\n        return ''\n\n    def needs_arglist(self):\n        \"\"\"May return true if an empty argument list is to be generated even if\n        the document contains none.\n        \"\"\"\n        return False\n\n    def handle_signature(self, sig, signode):\n        \"\"\"Transform a Bsv signature into RST nodes.\n\n        Return (fully qualified name of the thing, interfacename if any).\n\n        If inside a interface, the current interface name is handled intelligently:\n        * it is stripped from the displayed name if present\n        * it is added to the full name (return value) if not present\n        \"\"\"\n        print('BsvObject.handle_signature', sig)\n        name_prefix = ''\n        name = sig\n        arglist = ''\n        retann = ''\n        if self.objtype in ['interface', 'instance', 'typeclass']:\n            split = sig.split('#', 1)\n            name = split[0]\n            if len(split) > 1:\n                arglist = split[1]\n                m = bsv_param_re.match(arglist)\n                if m: arglist = m.group(1)\n        elif self.objtype in ['subinterface', 'field']:\n            split = sig.rsplit(' ', 1)\n            print('rsplit', split)\n            name = split[-1]\n            if len(split) > 1:\n                retann = split[0]\n        elif self.objtype in ['method', 'function']:\n            split = sig.split(' ', 1)\n            retann = split[0]\n            nameparams = split[1]\n            split = nameparams.split('(', 1)\n            name = split[0]\n            if len(split) > 1:\n                arglist = split[1][0:-1]\n        elif self.objtype in ['module']:\n            split = sig.split('#', 1)\n            name = split[0]\n            if len(split) > 1:\n                depth = 0\n                paramreturn = split[1]\n                #print('module', paramreturn, len(paramreturn))\n                for i in range(0,len(paramreturn)):\n                    c = paramreturn[i]\n                    if c == '(': depth = depth+1\n                    elif c == ')': depth = depth-1\n                    \n                    #print(i, c, depth)\n                    if depth==0:\n                        endofparam=i\n                        break\n                arglist = paramreturn[1:endofparam]\n                retann = paramreturn[endofparam+1:-1]\n                #print(arglist)\n                #print(endofparam, retann)\n\n        # determine package and interface name (if applicable), as well as full name\n        modname = self.options.get(\n            'package', self.env.temp_data.get('bsv:package'))\n        interfacename = self.env.temp_data.get('bsv:interface')\n        if interfacename:\n            add_package = False\n            if name_prefix and name_prefix.startswith(interfacename):\n                fullname = name_prefix + name\n                # interface name is given again in the signature\n                name_prefix = name_prefix[len(interfacename):].lstrip('.')\n            elif name_prefix:\n                # interface name is given in the signature, but different\n                # (shouldn't happen)\n                fullname = interfacename + '.' + name_prefix + name\n            else:\n                # interface name is not given in the signature\n                fullname = interfacename + '.' + name\n        else:\n            add_package = True\n            if name_prefix:\n                interfacename = name_prefix.rstrip('.')\n                fullname = name_prefix + name\n            else:\n                interfacename = ''\n                fullname = name\n\n        signode['package'] = modname\n        signode['interface'] = interfacename\n        signode['fullname'] = fullname\n\n        sig_prefix = self.get_signature_prefix(sig)\n        if sig_prefix:\n            signode += addnodes.desc_annotation(sig_prefix, sig_prefix)\n\n        if name_prefix:\n            signode += addnodes.desc_addname(name_prefix, name_prefix)\n        # exceptions are a special case, since they are documented in the\n        # 'exceptions' package.\n        elif add_package and self.env.config.add_package_names:\n            modname = self.options.get(\n                'package', self.env.temp_data.get('bsv:package'))\n            if modname and modname != 'exceptions':\n                nodetext = modname + '::'\n                signode += addnodes.desc_addname(nodetext, nodetext)\n\n        anno = self.options.get('annotation')\n\n        signode += addnodes.desc_name(name, name)\n        #print('arglist', arglist)\n        if not arglist:\n            if self.needs_arglist():\n                # for callables, add an empty parameter list\n                if arglist:\n                    signode += addnodes.desc_parameterlist(text=arglist)\n                elif self.options.get('parameter'):\n                    signode += addnodes.desc_parameterlist(text=self.options.get('parameter'))\n            if retann:\n                signode += addnodes.desc_returns(text=retann)\n            elif self.options.get('returntype'):\n                signode += addnodes.desc_returns(text=self.options.get('returntype'))\n            if anno:\n                signode += addnodes.desc_annotation(' ' + anno, ' ' + anno)\n            #print('signode', signode)\n            return fullname, name_prefix\n\n        _pseudo_parse_arglist(signode, arglist)\n        if retann:\n            signode += addnodes.desc_returns(retann, retann)\n        if anno:\n            signode += addnodes.desc_annotation(' ' + anno, ' ' + anno)\n        return fullname, name_prefix\n\n    def get_index_text(self, modname, name):\n        \"\"\"Return the text for the index entry of the object.\"\"\"\n        raise NotImplementedError('must be implemented in subinterfacees')\n\n    def add_target_and_index(self, name_cls, sig, signode):\n        modname = self.options.get(\n            'package', self.env.temp_data.get('bsv:package'))\n        fullname = (modname and modname + '::' or '') + name_cls[0]\n        # note target\n        if fullname not in self.state.document.ids:\n            signode['names'].append(fullname)\n            signode['ids'].append(fullname)\n            signode['first'] = (not self.names)\n            self.state.document.note_explicit_target(signode)\n            objects = self.env.domaindata['bsv']['objects']\n            if fullname in objects:\n                self.state_machine.reporter.warning(\n                    'duplicate object description of %s, ' % fullname +\n                    'other instance in ' +\n                    self.env.doc2path(objects[fullname][0]) +\n                    ', use :noindex: for one of them',\n                    line=self.lineno)\n            objects[fullname] = (self.env.docname, self.objtype)\n\n        indextext = self.get_index_text(modname, name_cls)\n        if indextext:\n            self.indexnode['entries'].append(('single', indextext,\n                                              fullname, ''))\n\n    def before_content(self):\n        # needed for automatic qualification of members (reset in subinterfacees)\n        self.clsname_set = False\n\n    def after_content(self):\n        if self.clsname_set:\n            self.env.temp_data['bsv:interface'] = None\n\n\nclass BsvPackagelevel(BsvObject):\n    \"\"\"\n    Description of an object on package level (functions, data).\n    \"\"\"\n\n    def get_signature_prefix(self, sig):\n        return self.objtype + ' '\n\n    def needs_arglist(self):\n        return self.objtype.endswith('method') or self.objtype in ['typedef', 'function', 'interface', 'typeclass']\n\n    def get_index_text(self, modname, name_cls):\n        if modname:\n            return _('%s (%s in package %s)') % (name_cls[0], self.objtype, modname)\n        else:\n            return _('%s (%s)') % (name_cls[0], self.objtype)\n\n\nclass BsvInterfacelike(BsvObject):\n    \"\"\"\n    Description of a interface-like object (interfacees).\n    \"\"\"\n\n    def get_signature_prefix(self, sig):\n        return self.objtype + ' '\n\n    def get_index_text(self, modname, name_cls):\n        if modname:\n            return _('%s (%s in package %s)') % (name_cls[0], self.objtype, modname)\n        else:\n            return _('%s (%s)') % (name_cls[0], self.objtype)\n\n    def before_content(self):\n        BsvObject.before_content(self)\n        if self.names:\n            self.env.temp_data['bsv:interface'] = self.names[0][0]\n            self.clsname_set = True\n\n\nclass BsvInterfacemember(BsvObject):\n    \"\"\"\n    Description of a interface member (methods, fields).\n    \"\"\"\n\n    option_spec = {\n        'noindex': directives.flag,\n        'package': directives.unchanged,\n        'annotation': directives.unchanged,\n        'returntype': directives.unchanged_required,\n        'parameter': directives.unchanged_required\n        }\n\n    def needs_arglist(self):\n        return self.objtype.endswith('method') or self.objtype in ['typedef', 'interface', 'subinterface', 'field']\n\n    def get_signature_prefix(self, sig):\n        if self.objtype == 'staticmethod':\n            return 'static '\n        elif self.objtype == 'interfacemethod':\n            return 'interfacemethod '\n        return ''\n\n    def get_index_text(self, modname, name_cls):\n        name, cls = name_cls\n        add_packages = self.env.config.add_package_names\n        print('BsvInterfacemember.get_index_text', name, cls, modname)\n        if self.objtype == 'method':\n            try:\n                clsname, methname = name.rsplit('.', 1)\n            except ValueError:\n                if modname:\n                    return _('%s() (in package %s)') % (name, modname)\n                else:\n                    return '%s()' % name\n            if modname and add_packages:\n                return _('%s() (%s::%s method)') % (methname, modname, clsname)\n            else:\n                return _('%s() (%s method)') % (methname, clsname)\n        elif self.objtype == 'staticmethod':\n            try:\n                clsname, methname = name.rsplit('.', 1)\n            except ValueError:\n                if modname:\n                    return _('%s() (in package %s)') % (name, modname)\n                else:\n                    return '%s()' % name\n            if modname and add_packages:\n                return _('%s() (%s::%s static method)') % (methname, modname,\n                                                          clsname)\n            else:\n                return _('%s() (%s static method)') % (methname, clsname)\n        elif self.objtype == 'interfacemethod':\n            try:\n                clsname, methname = name.rsplit('.', 1)\n            except ValueError:\n                if modname:\n                    return _('%s() (in package %s)') % (name, modname)\n                else:\n                    return '%s()' % name\n            if modname:\n                return _('%s() (%s::%s interface method)') % (methname, modname,\n                                                         clsname)\n            else:\n                return _('%s() (%s interface method)') % (methname, clsname)\n        elif self.objtype == 'attribute':\n            try:\n                clsname, attrname = name.rsplit('.', 1)\n            except ValueError:\n                if modname:\n                    return _('%s (in package %s)') % (name, modname)\n                else:\n                    return name\n            if modname and add_packages:\n                return _('%s (%s::%s attribute)') % (attrname, modname, clsname)\n            else:\n                return _('%s (%s attribute)') % (attrname, clsname)\n        else:\n            return ''\n\n    def before_content(self):\n        BsvObject.before_content(self)\n        lastname = self.names and self.names[-1][1]\n        if lastname and not self.env.temp_data.get('bsv:interface'):\n            self.env.temp_data['bsv:interface'] = lastname.strip('.')\n            self.clsname_set = True\n\n\nclass BsvDecoratorMixin(object):\n    \"\"\"\n    Mixin for decorator directives.\n    \"\"\"\n    def handle_signature(self, sig, signode):\n        print('BsvDecoratorMixin.handle_signature', sig)\n        ret = super(BsvDecoratorMixin, self).handle_signature(sig, signode)\n        signode.insert(0, addnodes.desc_addname('@', '@'))\n        return ret\n\n    def needs_arglist(self):\n        return False\n\n\nclass BsvDecoratorFunction(BsvDecoratorMixin, BsvPackagelevel):\n    \"\"\"\n    Directive to mark functions meant to be used as decorators.\n    \"\"\"\n    def run(self):\n        # a decorator function is a function after all\n        self.name = 'bsv:function'\n        return BsvPackagelevel.run(self)\n\n\nclass BsvDecoratorMethod(BsvDecoratorMixin, BsvInterfacemember):\n    \"\"\"\n    Directive to mark methods meant to be used as decorators.\n    \"\"\"\n    def run(self):\n        self.name = 'bsv:method'\n        return BsvInterfacemember.run(self)\n\n\nclass BsvPackage(SphinxDirective):\n    \"\"\"\n    Directive to mark description of a new package.\n    \"\"\"\n\n    has_content = False\n    required_arguments = 1\n    optional_arguments = 0\n    final_argument_whitespace = False\n    option_spec = {\n        'platform': lambda x: x,\n        'synopsis': lambda x: x,\n        'noindex': directives.flag,\n        'deprecated': directives.flag,\n    }\n\n    def run(self):\n        env = self.state.document.settings.env\n        modname = self.arguments[0].strip()\n        noindex = 'noindex' in self.options\n        env.temp_data['bsv:package'] = modname\n        ret = []\n        if not noindex:\n            env.domaindata['bsv']['packages'][modname] = \\\n                (env.docname, self.options.get('synopsis', ''),\n                 self.options.get('platform', ''), 'deprecated' in self.options)\n            # make a duplicate entry in 'objects' to facilitate searching for\n            # the package in BsvDomain.find_obj()\n            env.domaindata['bsv']['objects'][modname] = (env.docname, 'package')\n            targetnode = nodes.target('', '', ids=['package-' + modname],\n                                      ismod=True)\n            self.state.document.note_explicit_target(targetnode)\n            # the platform and synopsis aren't printed; in fact, they are only\n            # used in the pkgindex currently\n            ret.append(targetnode)\n            indextext = _('%s (package)') % modname\n            inode = addnodes.index(entries=[('single', indextext,\n                                             'package-' + modname, '')])\n            ret.append(inode)\n        return ret\n\n\nclass BsvCurrentPackage(SphinxDirective):\n    \"\"\"\n    This directive is just to tell Sphinx that we're documenting\n    stuff in package foo, but links to package foo won't lead here.\n    \"\"\"\n\n    has_content = False\n    required_arguments = 1\n    optional_arguments = 0\n    final_argument_whitespace = False\n    option_spec = {}\n\n    def run(self):\n        env = self.state.document.settings.env\n        modname = self.arguments[0].strip()\n        if modname == 'None':\n            env.temp_data['bsv:package'] = None\n        else:\n            env.temp_data['bsv:package'] = modname\n        return []\n\n\nclass BsvXRefRole(XRefRole):\n    def process_link(self, env, refnode, has_explicit_title, title, target):\n        refnode['bsv:package'] = env.temp_data.get('bsv:package')\n        refnode['bsv:interface'] = env.temp_data.get('bsv:interface')\n        if not has_explicit_title:\n            title = title.lstrip('.')   # only has a meaning for the target\n            target = target.lstrip('~') # only has a meaning for the title\n            # if the first character is a tilde, don't display the package/interface\n            # parts of the contents\n            if title[0:1] == '~':\n                title = title[1:]\n                dot = title.rfind('.')\n                if dot != -1:\n                    title = title[dot+1:]\n        # if the first character is a dot, search more specific namespaces first\n        # else search builtins first\n        if target[0:1] == '.':\n            target = target[1:]\n            refnode['refspecific'] = True\n        return title, target\n\n\nclass BsvPackageIndex(Index):\n    \"\"\"\n    Index subinterface to provide the Bsv package index.\n    \"\"\"\n\n    name = 'pkgindex'\n    localname = l_('Bsv Package Index')\n    shortname = l_('bsvpkgs')\n\n    def generate(self, docnames=None):\n        content = {}\n        # list of prefixes to ignore\n        ignores = self.domain.env.config['pkgindex_common_prefix']\n        ignores = sorted(ignores, key=len, reverse=True)\n        # list of all packages, sorted by package name\n        packages = sorted(self.domain.data['packages'].items(),\n                         key=lambda x: x[0].lower())\n        # sort out collapsable packages\n        prev_modname = ''\n        num_toplevels = 0\n        for modname, (docname, synopsis, platforms, deprecated) in packages:\n            if docnames and docname not in docnames:\n                continue\n\n            for ignore in ignores:\n                if modname.startswith(ignore):\n                    modname = modname[len(ignore):]\n                    stripped = ignore\n                    break\n            else:\n                stripped = ''\n\n            # we stripped the whole package name?\n            if not modname:\n                modname, stripped = stripped, ''\n\n            entries = content.setdefault(modname[0].lower(), [])\n\n            package = modname.split('.')[0]\n            if package != modname:\n                # it's a subpackage\n                if prev_modname == package:\n                    # first subpackage - make parent a group head\n                    if entries:\n                        entries[-1][1] = 1\n                elif not prev_modname.startswith(package):\n                    # subpackage without parent in list, add dummy entry\n                    entries.append([stripped + package, 1, '', '', '', '', ''])\n                subtype = 2\n            else:\n                num_toplevels += 1\n                subtype = 0\n\n            qualifier = deprecated and _('Deprecated') or ''\n            entries.append([stripped + modname, subtype, docname,\n                            'package-' + stripped + modname, platforms,\n                            qualifier, synopsis])\n            prev_modname = modname\n\n        # apply heuristics when to collapse pkgindex at page load:\n        # only collapse if number of toplevel packages is larger than\n        # number of subpackages\n        collapse = len(packages) - num_toplevels < num_toplevels\n\n        # sort by first letter\n        content = sorted(content.items())\n\n        return content, collapse\n\nclass BsvModuleIndex(Index):\n    \"\"\"\n    Index subinterface to provide the Bsv module index.\n    \"\"\"\n\n    name = 'bsvmodules'\n    localname = l_('Bsv Module Index')\n    shortname = l_('bsvmodules')\n\n    def generate(self, docnames=None):\n        content = {}\n        # list of prefixes to ignore\n        ignores = self.domain.env.config['pkgindex_common_prefix']\n        ignores = sorted(ignores, key=len, reverse=True)\n        # list of all packages, sorted by package name\n        modules = sorted(self.domain.data['modules'].items(),\n                         key=lambda x: x[0].lower())\n        # sort out collapsable modules\n        prev_modname = ''\n        num_toplevels = 0\n        for modname, (docname, synopsis, platforms, deprecated) in modules:\n            if docnames and docname not in docnames:\n                continue\n\n            for ignore in ignores:\n                if modname.startswith(ignore):\n                    modname = modname[len(ignore):]\n                    stripped = ignore\n                    break\n            else:\n                stripped = ''\n\n            # we stripped the whole module name?\n            if not modname:\n                modname, stripped = stripped, ''\n\n            entries = content.setdefault(modname[0].lower(), [])\n\n            module = modname.split('.')[0]\n            if module != modname:\n                # it's a submodule\n                if prev_modname == module:\n                    # first submodule - make parent a group head\n                    if entries:\n                        entries[-1][1] = 1\n                elif not prev_modname.startswith(module):\n                    # submodule without parent in list, add dummy entry\n                    entries.append([stripped + module, 1, '', '', '', '', ''])\n                subtype = 2\n            else:\n                num_toplevels += 1\n                subtype = 0\n\n            qualifier = deprecated and _('Deprecated') or ''\n            entries.append([stripped + modname, subtype, docname,\n                            'module-' + stripped + modname, platforms,\n                            qualifier, synopsis])\n            prev_modname = modname\n\n        # apply heuristics when to collapse pkgindex at page load:\n        # only collapse if number of toplevel modules is larger than\n        # number of submodules\n        collapse = len(modules) - num_toplevels < num_toplevels\n\n        # sort by first letter\n        content = sorted(content.items())\n\n        return content, collapse\n\n\nclass BsvDomain(Domain):\n    \"\"\"Bsv language domain.\"\"\"\n    name = 'bsv'\n    label = 'Bsv'\n    object_types = {\n        'function':     ObjType(l_('function'),      'func', 'obj'),\n        'data':         ObjType(l_('data'),          'data', 'obj'),\n        'interface':        ObjType(l_('interface'),         'interface', 'exc', 'obj'),\n        'instance':     ObjType(l_('instance'),         'instance', 'obj'),\n        'exception':    ObjType(l_('exception'),     'exc', 'interface', 'obj'),\n        'method':       ObjType(l_('method'),        'meth', 'obj'),\n        'subinterface': ObjType(l_('subinterface'),  'ifc', 'obj'),\n        'field': ObjType(l_('field'),  'fld', 'obj'),\n        'interfacemethod':  ObjType(l_('interface method'),  'meth', 'obj'),\n        'staticmethod': ObjType(l_('static method'), 'meth', 'obj'),\n        'package':       ObjType(l_('package'),      'pkg', 'obj'),\n        'module':       ObjType(l_('module'),        'mod', 'obj'),\n        'struct':        ObjType(l_('struct'),       'struct', 'obj'),\n        'typedef':       ObjType(l_('typedef'),      'mod', 'obj'),\n        'typeclass':        ObjType(l_('typeclass'),         'typeclass', 'obj'),\n    }\n\n    directives = {\n        'function':        BsvPackagelevel,\n        'data':            BsvPackagelevel,\n        'module':          BsvPackagelevel,\n        'typedef':         BsvPackagelevel,\n        'interface':       BsvInterfacelike,\n        'typeclass':       BsvInterfacelike,\n        'instance':        BsvInterfacelike,\n        'struct':          BsvInterfacelike,\n        'method':          BsvInterfacemember,\n        'interfacemethod':     BsvInterfacemember,\n        'staticmethod':    BsvInterfacemember,\n        'subinterface':    BsvInterfacemember,\n        'field':           BsvInterfacemember,\n        'package':          BsvPackage,\n        'currentpackage':   BsvCurrentPackage,\n        'decorator':       BsvDecoratorFunction,\n        'decoratormethod': BsvDecoratorMethod,\n    }\n    roles = {\n        'data':  BsvXRefRole(),\n        'exc':   BsvXRefRole(),\n        'func':  BsvXRefRole(fix_parens=True),\n        'interface': BsvXRefRole(),\n        'const': BsvXRefRole(),\n        'attr':  BsvXRefRole(),\n        'meth':  BsvXRefRole(fix_parens=True),\n        'mod':   BsvXRefRole(),\n        'pkg':   BsvXRefRole(),\n        'obj':   BsvXRefRole(),\n    }\n    initial_data = {\n        'objects': {},  # fullname -> docname, objtype\n        'packages': {},  # modname -> docname, synopsis, platform, deprecated\n        'modules': {},  # modname -> docname, synopsis, platform, deprecated\n        'labels': {         # labelname -> docname, labelid, sectionname\n            'pkgindex': ('bsv-pkgindex', '', l_('Package Index')),\n        },\n        'anonlabels': {     # labelname -> docname, labelid\n            'pkgindex': ('bsv-pkgindex', ''),\n        },\n    }\n    indices = [\n        BsvPackageIndex,\n        BsvModuleIndex\n    ]\n\n    def clear_doc(self, docname):\n        for fullname, (fn, _) in self.data['objects'].items():\n            if fn == docname:\n                del self.data['objects'][fullname]\n        for modname, (fn, _, _, _) in self.data['packages'].items():\n            if fn == docname:\n                del self.data['packages'][modname]\n\n    def find_obj(self, env, modname, interfacename, name, type, searchmode=0):\n        \"\"\"Find a Bsv object for \"name\", perhaps using the given package\n        and/or interfacename.  Returns a list of (name, object entry) tuples.\n        \"\"\"\n        # skip parens\n        if name[-2:] == '()':\n            name = name[:-2]\n\n        if not name:\n            return []\n\n        objects = self.data['objects']\n        matches = []\n\n        newname = None\n        if searchmode == 1:\n            objtypes = self.objtypes_for_role(type)\n            if objtypes is not None:\n                if modname and interfacename:\n                    fullname = modname + '::' + interfacename + '.' + name\n                    if fullname in objects and objects[fullname][1] in objtypes:\n                        newname = fullname\n                if not newname:\n                    if modname and modname + '::' + name in objects and \\\n                       objects[modname + '::' + name][1] in objtypes:\n                        newname = modname + '::' + name\n                    elif name in objects and objects[name][1] in objtypes:\n                        newname = name\n                    else:\n                        # \"fuzzy\" searching mode\n                        searchname = '.' + name\n                        matches = [(oname, objects[oname]) for oname in objects\n                                   if oname.endswith(searchname)\n                                   and objects[oname][1] in objtypes]\n        else:\n            # NOTE: searching for exact match, object type is not considered\n            if name in objects:\n                newname = name\n            elif type == 'mod':\n                # only exact matches allowed for packages\n                return []\n            elif interfacename and interfacename + '.' + name in objects:\n                newname = interfacename + '.' + name\n            elif modname and modname + '::' + name in objects:\n                newname = modname + '::' + name\n            elif modname and interfacename and \\\n                     modname + '::' + interfacename + '.' + name in objects:\n                newname = modname + '::' + interfacename + '.' + name\n            # special case: builtin exceptions have package \"exceptions\" set\n            elif type == 'exc' and '.' not in name and \\\n                 'exceptions.' + name in objects:\n                newname = 'exceptions.' + name\n            # special case: object methods\n            elif type in ('func', 'meth') and '.' not in name and \\\n                 'object.' + name in objects:\n                newname = 'object.' + name\n        if newname is not None:\n            matches.append((newname, objects[newname]))\n        return matches\n\n    def resolve_xref(self, env, fromdocname, builder,\n                     type, target, node, contnode):\n        modname = node.get('bsv:package')\n        clsname = node.get('bsv:interface')\n        searchmode = node.hasattr('refspecific') and 1 or 0\n        matches = self.find_obj(env, modname, clsname, target,\n                                type, searchmode)\n        if not matches:\n            return None\n        elif len(matches) > 1:\n            env.warn_node(\n                'more than one target found for cross-reference '\n                '%r: %s' % (target, ', '.join(match[0] for match in matches)),\n                node)\n        name, obj = matches[0]\n\n        if obj[1] == 'package':\n            # get additional info for packages\n            docname, synopsis, platform, deprecated = self.data['packages'][name]\n            assert docname == obj[0]\n            title = name\n            if synopsis:\n                title += ': ' + synopsis\n            if deprecated:\n                title += _(' (deprecated)')\n            if platform:\n                title += ' (' + platform + ')'\n            return make_refnode(builder, fromdocname, docname,\n                                'package-' + name, contnode, title)\n        else:\n            return make_refnode(builder, fromdocname, obj[0], name,\n                                contnode, name)\n\n    def get_objects(self):\n        for modname, info in self.data['packages'].items():\n            yield (modname, modname, 'package', info[0], 'package-' + modname, 0)\n        for refname, (docname, type) in self.data['objects'].items():\n            if type != 'package':  # packages are already handled\n                yield (refname, refname, type, docname, refname, 1)\n\ndef setup(app):\n    print('sphinxbsv setup')\n    app.add_config_value('bsv_include_bsvs', False, False)\n    app.add_config_value('add_package_names', True, True)\n    app.add_config_value('pkgindex_common_prefix', [], 'html')\n\n    app.add_domain(BsvDomain)\n"
  },
  {
    "path": "doc/library/source/c/c.rst",
    "content": "\nConnectal C/C++ Libraries\n=========================\n\n.. toctree::\n   :maxdepth: 2\n   :numbered:\n\n   portal.rst\n"
  },
  {
    "path": "doc/library/source/c/portal.rst",
    "content": "C/C++ Portal\n============\n\nConnecting to Bluesim\n---------------------\n\n.. envvar:: BLUESIM_SOCKET_NAME\n\n   Controls the name of the socket used for connecting software and hardware simulated by bluesim.\n\nConnecting to Xsim and Verilator\n--------------------------------\n\n.. envvar:: SOFTWARE_SOCKET_NAME\n\n   Controls the name of the socket used for connecting software and hardware simulated by xsim/verilator.\n\nAutomatically Programming the FPGA\n----------------------------------\n\nConnectal application executables or shared objects contain the FPGA\nbitstream in the \"fpgadata\" section of the ELF file. When the\napplication (or library) first tries to access the hardware, the\nConnectal library automatically programs the FGPA with the associated\nbitstream, unless :c:data:`noprogram` is set to a non-zero value or\nenvironment variable :envvar:`NOPROGRAM` is nonzero.\n\nIn the case of simulation hardware, the simulator is launched when the\napplication first tries to access the hardware. This behavior is also\nsuppressed by a nonzero value for either :c:data:`noprogram` or\n:envvar:`NOPROGRAM`.\n\n.. c:var:: int noprogram\n\n   If :c:data:`noprogram` is set to a non-zero value, then the FPGA is not programmed automatically.\n   \nTracing Simulation\n------------------\n\n.. envvar:: DUMP_VCD\n\n   If set, directs the simulator to dump a VCD trace to the $DUMP_VCD.\n\n.. c:var:: int simulator_dump_vcd\n\n   The application can enable VCD tracing by setting\n   :c:data:`simulator_dump_vcd` to 1. It takes the file name from\n   :c:data:`simulator_vcd_name`. DUMP_VCD overrides this variable.\n\n.. c:var::  const char *simulator_vcd_name;\n\n   Specifies the name of the vcd file. Defaults to\n   \"dump.vcd\". DUMP_VCD overrides this variable.\n\nZynq Clock Control\n------------------\n\n.. c:function:: void setClockFrequency(int clkNum, long requestedFrequency, long *actualFrequency)\n\n   Changes the frequency of Zynq FPGA Clock clkNum to the closest\n   frequency to requestedFrequency available from the PLL. If the\n   actualFrequency pointer is non-null, stores the actual freqency\n   before returning.\n\nPortal Memory\n-------------\n\n.. c:function:: int portalAlloc(size_t size, int cached)\n\n   Uses portalmem to allocate a region of size bytes.\n\n   On platforms that support non-cache-coherent I/O (e.g., zedboard),\n   cached=0 indicates that the programmable logic will use a port to\n   memory that is not snooped by the CPU's caches. In this case, it is\n   up to the allocation to flush or invalidate the CPU cache as\n   needed, using portalCacheFlush().\n\n   Returns the file descriptor associated with the memory region.\n\n.. c:function:: void *portalMmap(int fd, size_t size)\n\n   Memory maps size bytes of the portal memory region indicated by fd.\n\n   Returns a pointer to memory on success or -1 on failure.\n\n.. c:function:: portalCacheFlush(int fd, void *__p, long size, int flush)\n\n\nPortalPoller\n============\n\n.. cpp:class:: PortalPoller\n\n   Polls portals\n\n   .. cpp:member:: PortalPoller::PortalPoller(int autostart = 1)\n\n      If autostart is 1, then invoke :cpp:member:`start()` from :cpp:member:`registerInstance()`\n\n   .. cpp:member:: void PortalPoller::start();\n\n      Starts the poller. Called automatically from :cpp:member:`registerInstance()` if :cpp:member:`autostart` is 1.\n\n   .. cpp:member:: void PortalPoller::stop();\n\n      Stops the poller.\n\n   .. cpp:member:: int PortalPoller::timeout\n\n      The timeout value, in milliseconds, passed to :c:function:`poll()`\n\n:envvar:`PORTAL_TIMEOUT`.\n\n    Overrides the default value for :cpp:member:`PortalPoller::timeout`.\n\nDeprecated Functions\n--------------------\n\n.. c:function:: void *portalExec(void *__x)\n   Polls the registered portals and invokes their callback handlers.\n\n.. c:function:: void portalExec_start()\n\n.. c:function:: void portalExec_poll()\n\n"
  },
  {
    "path": "doc/library/source/conf.py",
    "content": "# -*- coding: utf-8 -*-\n#\n# connectal documentation build configuration file, created by\n# sphinx-quickstart on Tue Nov 25 12:27:26 2014.\n#\n# This file is execfile()d with the current directory set to its\n# containing dir.\n#\n# Note that not all possible configuration values are present in this\n# autogenerated file.\n#\n# All configuration values have a default; values that are commented out\n# serve to show the default.\n\nimport sys\nimport os\n\n# If extensions (or modules to document with autodoc) are in another directory,\n# add these directories to sys.path here. If the directory is relative to the\n# documentation root, use os.path.abspath to make it absolute, like shown here.\n#sys.path.insert(0, os.path.abspath('.'))\n\nsys.path.insert(0, os.path.abspath('.'))\nsys.path.insert(0, os.path.abspath('../../../scripts'))\n\n# -- General configuration ------------------------------------------------\n\n# If your documentation needs a minimal Sphinx version, state it here.\n#needs_sphinx = '1.0'\n\n# Add any Sphinx extension module names here, as strings. They can be\n# extensions coming with Sphinx (named 'sphinx.ext.*') or your custom\n# ones.\nextensions = [\n    'sphinx.ext.autodoc',\n    'sphinx.ext.autosummary',\n    'sphinx.ext.todo',\n    'sphinx.ext.mathjax',\n    'sphinx.ext.viewcode',\n    'sphinxcontrib.makedomain',\n    'sphinxarg.ext',\n    'bsvsphinx'\n]\n\n# Add any paths that contain templates here, relative to this directory.\ntemplates_path = ['_templates']\n\n# The suffix of source filenames.\nsource_suffix = '.rst'\n\n# The encoding of source files.\n#source_encoding = 'utf-8-sig'\n\n# The master toctree document.\nmaster_doc = 'index'\n\n# General information about the project.\nproject = u'connectal'\ncopyright = u'2015-2020, Jamey Hicks, Myron King, John Ankcorn'\n\ngoogleanalytics_id = 'UA-15845210-2'\ngoogleanalytics_enabled = True\n\n# The version info for the project you're documenting, acts as replacement for\n# |version| and |release|, also used in various other places throughout the\n# built documents.\n#\n# The short X.Y version.\nversion = '22.05.23b'\n# The full version, including alpha/beta/rc tags.\nrelease = '22.05.23b'\n\n# The language for content autogenerated by Sphinx. Refer to documentation\n# for a list of supported languages.\n#language = None\n\n# There are two options for replacing |today|: either, you set today to some\n# non-false value, then it is used:\n#today = ''\n# Else, today_fmt is used as the format for a strftime call.\n#today_fmt = '%B %d, %Y'\n\n# List of patterns, relative to source directory, that match files and\n# directories to ignore when looking for source files.\nexclude_patterns = []\n\n# The reST default role (used for this markup: `text`) to use for all\n# documents.\n#default_role = None\n\n# If true, '()' will be appended to :func: etc. cross-reference text.\n#add_function_parentheses = True\n\n# If true, the current module name will be prepended to all description\n# unit titles (such as .. function::).\n#add_module_names = True\n\n# If true, sectionauthor and moduleauthor directives will be shown in the\n# output. They are ignored by default.\n#show_authors = False\n\n# The name of the Pygments (syntax highlighting) style to use.\npygments_style = 'sphinx'\n\n# A list of ignored prefixes for module index sorting.\n#modindex_common_prefix = []\n\n# If true, keep warnings as \"system message\" paragraphs in the built documents.\n#keep_warnings = False\n\nautosummary_generate = True\nautoclass_content = 'both'\nautodoc_default_flags = ['members', 'undoc-members', 'show-inheritance']\n\n# -- Options for HTML output ----------------------------------------------\n\n# The theme to use for HTML and HTML Help pages.  See the documentation for\n# a list of builtin themes.\nhtml_theme = 'connectal'\n\n# Theme options are theme-specific and customize the look and feel of a theme\n# further.  For a list of options available for each theme, see the\n# documentation.\n#html_theme_options = {}\n\n# Add any paths that contain custom themes here, relative to this directory.\nhtml_theme_path = ['themes']\n\n# The name for this set of Sphinx documents.  If None, it defaults to\n# \"<project> v<release> documentation\".\n#html_title = None\n\n# A shorter title for the navigation bar.  Default is the same as html_title.\n#html_short_title = None\n\n# The name of an image file (relative to this directory) to place at the top\n# of the sidebar.\n#html_logo = None\n\n# The name of an image file (within the static path) to use as favicon of the\n# docs.  This file should be a Windows icon file (.ico) being 16x16 or 32x32\n# pixels large.\n#html_favicon = None\n\n# Add any paths that contain custom static files (such as style sheets) here,\n# relative to this directory. They are copied after the builtin static files,\n# so a file named \"default.css\" will overwrite the builtin \"default.css\".\nhtml_static_path = ['_static']\n\n# Add any extra paths that contain custom files (such as robots.txt or\n# .htaccess) here, relative to this directory. These files are copied\n# directly to the root of the documentation.\n#html_extra_path = []\n\n# If not '', a 'Last updated on:' timestamp is inserted at every page bottom,\n# using the given strftime format.\n#html_last_updated_fmt = '%b %d, %Y'\n\n# If true, SmartyPants will be used to convert quotes and dashes to\n# typographically correct entities.\n#html_use_smartypants = True\n\n# Custom sidebar templates, maps document names to template names.\n#html_sidebars = {}\n\n# Additional templates that should be rendered to pages, maps page names to\n# template names.\n#html_additional_pages = {}\n\n# If false, no module index is generated.\nhtml_domain_indices = True\n\n# If false, no index is generated.\nhtml_use_index = True\n\n# If true, the index is split into individual pages for each letter.\n#html_split_index = False\n\n# If true, links to the reST sources are added to the pages.\n#html_show_sourcelink = True\n\n# If true, \"Created using Sphinx\" is shown in the HTML footer. Default is True.\n#html_show_sphinx = True\n\n# If true, \"(C) Copyright ...\" is shown in the HTML footer. Default is True.\n#html_show_copyright = True\n\n# If true, an OpenSearch description file will be output, and all pages will\n# contain a <link> tag referring to it.  The value of this option must be the\n# base URL from which the finished HTML is served.\n#html_use_opensearch = ''\n\n# This is the file name suffix for HTML files (e.g. \".xhtml\").\n#html_file_suffix = None\n\n# Output file base name for HTML help builder.\nhtmlhelp_basename = 'connectaldoc'\n\n\n# -- Options for LaTeX output ---------------------------------------------\n\nlatex_elements = {\n# The paper size ('letterpaper' or 'a4paper').\n#'papersize': 'letterpaper',\n\n# The font size ('10pt', '11pt' or '12pt').\n#'pointsize': '10pt',\n\n# Additional stuff for the LaTeX preamble.\n#'preamble': '',\n}\n\n# Grouping the document tree into LaTeX files. List of tuples\n# (source start file, target name, title,\n#  author, documentclass [howto, manual, or own class]).\nlatex_documents = [\n  ('index', 'connectal.tex', u'connectal Documentation',\n   u'Jamey Hicks, Myron King, John Ankcorn', 'manual'),\n]\n\n# The name of an image file (relative to this directory) to place at the top of\n# the title page.\n#latex_logo = None\n\n# For \"manual\" documents, if this is true, then toplevel headings are parts,\n# not chapters.\n#latex_use_parts = False\n\n# If true, show page references after internal links.\n#latex_show_pagerefs = False\n\n# If true, show URL addresses after external links.\n#latex_show_urls = False\n\n# Documents to append as an appendix to all manuals.\n#latex_appendices = []\n\n# If false, no module index is generated.\n#latex_domain_indices = True\n\n\n# -- Options for manual page output ---------------------------------------\n\n# One entry per manual page. List of tuples\n# (source start file, name, description, authors, manual section).\nman_pages = [\n    ('index', 'connectal', u'connectal Documentation',\n     [u'Jamey Hicks, Myron King, John Ankcorn'], 1)\n]\n\n# If true, show URL addresses after external links.\n#man_show_urls = False\n\n\n# -- Options for Texinfo output -------------------------------------------\n\n# Grouping the document tree into Texinfo files. List of tuples\n# (source start file, target name, title, author,\n#  dir menu entry, description, category)\ntexinfo_documents = [\n  ('index', 'connectal', u'connectal Documentation',\n   u'Jamey Hicks, Myron King, John Ankcorn', 'connectal', 'One line description of project.',\n   'Miscellaneous'),\n]\n\n# Documents to append as an appendix to all manuals.\n#texinfo_appendices = []\n\n# If false, no module index is generated.\n#texinfo_domain_indices = True\n\n# How to display URL addresses: 'footnote', 'no', or 'inline'.\n#texinfo_show_urls = 'footnote'\n\n# If true, do not generate a @detailmenu in the \"Top\" node's menu.\n#texinfo_no_detailmenu = False\n\n"
  },
  {
    "path": "doc/library/source/design/Makefile",
    "content": "\nall:\n\tmake -C images all\n"
  },
  {
    "path": "doc/library/source/design/abstract.rst",
    "content": "Abstract\n********\n\nThe cost and complexity of hardware-centric systems can often be\nreduced by using software to perform tasks which don't appear on the\ncritical path.  Alternately, the performance of software can sometimes\nbe improved by using special purpose hardware to implement tasks which\n*do* appear on the critical path.  Whatever the motivation,\nmost modern systems are composed of both hardware and software\ncomponents.\n\nGiven the importance of the connection between hardware and\nsoftware in these systems, it is surprising how little automated and\nmachine-checkable support there is for co-design space exploration.\nThis paper presents the Connectal framework, which enables the\ndevelopment of hardware accelerators for software applications by\ngenerating hardware/software interface implementations from abstract\nInterface Design Language (IDL) specifications.\n\n`Connectal`_ generates stubs to support asynchronous remote method\ninvocation from software to software, hardware to software, software\nto hardware, and hardware to hardware. For high-bandwidth\ncommunication, the Connectal framework provides comprehensive support\nfor shared memory between hardware and software components, removing\nthe repetitive work of processor bus interfacing from project tasks.\n\nThis framework is released as open software under an MIT license, making\nit available for use in any projects.\n\n.. _Connectal: http://www.connectal.org/\n"
  },
  {
    "path": "doc/library/source/design/bs-related-papers.bib",
    "content": "\n% ----------------------------------------------------\n% Bluespec References \n% ----------------------------------------------------\n\n% --------------\n% PHD Theses\n% --------------\n\n@PHDTHESIS{Hoe:Thesis,\n        AUTHOR = \"James C. Hoe\",\n        TITLE = {{Operation-Centric Hardware Description and Synthesis}},\n        SCHOOL = \"MIT\",\n        YEAR = {2000},\n        ADDRESS = {Cambridge,~MA}\n}\n\n@PHDTHESIS{Shen:Thesis,\n        AUTHOR = \"Xiaowei Shen\",\n        TITLE = {{Design and Verification of Adaptive Cache Coherence Protocols}},\n        SCHOOL = \"MIT\",\n        YEAR = {2000},\n        ADDRESS = {Cambridge,~MA}\n}\n\n@PHDTHESIS{Rosenband:Thesis,\n        AUTHOR = \"Daniel L. Rosenband\",\n        TITLE = {{A Performance Driven Approach for Hardware Synthesis of Guarded Atomic Actions}},\n        SCHOOL = \"MIT\",\n        YEAR = {2005},\n        ADDRESS = {Cambridge,~MA}\n}\n% --------------\n% Masters Theses\n% --------------\n\n@MASTERSTHESIS{Lis:Thesis,\n        AUTHOR = \"Mieszko Lis\",\n        TITLE = {{Superscalar Processors via Automatic Microarchitecture Transformations}},\n        SCHOOL = \"MIT\",\n        MONTH = {May},\n        YEAR = 2000,\n        ADDRESS = {Cambridge,~MA}\n}\n\n@MASTERSTHESIS{Dave:MSThesis,\n        AUTHOR = \"Nirav Dave\",\n        TITLE = {{Designing a Processor in Bluespec }},\n        SCHOOL = \"MIT\",\n        MONTH = {Jan},\n        YEAR = 2005,\n        ADDRESS = {Cambridge,~MA}\n}\n\n@MASTERSTHESIS{Dave:MSThesisPutGet,\n        AUTHOR = \"Nirav Dave\",\n        TITLE = {{Designing a Processor in Bluespec }},\n        SCHOOL = \"MIT\",\n        MONTH = {Jan},\n        YEAR = 2005,\n        pages = {23},\n        ADDRESS = {Cambridge,~MA}\n}\n\n@MASTERSTHESIS{ChunChieh:MSThesis,\n        AUTHOR = \"Chun-Chieh Lin\",\n        TITLE = {{ Implementation of H.264 Decoder in Bluespec System Verilog}},\n        SCHOOL = \"MIT\",\n        MONTH = {Feb},\n        YEAR = 2007,\n        ADDRESS = {Cambridge,~MA}\n}\n\n\n\n% --------------\n% Conference Papers\n% --------------\n\n@inproceedings{DBLP:conf/iccad/KarczmarekA08,\n  author    = {Michal Karczmarek and\n               Arvind},\n  title     = {Synthesis from multi-cycle atomic actions as a solution\n               to the timing closure problem},\n  booktitle = {ICCAD},\n  year      = {2008},\n  ee        = {http://doi.acm.org/10.1145/1509456.1509475},\n  bibsource = {DBLP, http://dblp.uni-trier.de}\n}\n\n\n@article{ArvindNikhil:ExecutingProgram,\n author = {Arvind and Rishiyur S. Nikhil},\n title = {Executing a Program on the MIT Tagged-Token Dataflow Architecture},\n journal = {IEEE Trans. Comput.},\n volume = {39},\n number = {3},\n year = {1990},\n issn = {0018-9340},\n pages = {300--318},\n doi = {http://dx.doi.org/10.1109/12.48862},\n publisher = {IEEE Computer Society},\n address = {Washington, DC, USA},\n }\n\n@article{HCAA:MonsoonPerformance,\n    author = \"James Hicks and Derek Chiou and Boon Seong Ang and Arvind\",\n    title = \"Performance Studies of {Id} on the {Monsoon Dataflow System}\",\n    journal = \"Journal of Parallel and Distributed Computing\",\n    volume = \"18\",\n    number = \"3\",\n    pages = \"273--300\",\n    year = \"1993\",\n    url = \"citeseer.ist.psu.edu/hicks94performance.html\" \n}\n\n\n@INPROCEEDINGS{HoeArvind:TRS_Synthesis1,\n        AUTHOR = \"James C. Hoe and Arvind\",\n        TITLE = {{Synthesis of Operation-Centric Hardware Descriptions}},\n        BOOKTITLE = {{Proceedings of ICCAD'00}},\n        PAGES = {511--518},\n        YEAR = {2000},\n        ADDRESS = {San Jose,~CA}\n}\n\n@INPROCEEDINGS{Dave:ROB,\n        AUTHOR = \"Nirav Dave\",\n        TITLE = {{Designing a Reorder Buffer in Bluespec}},\n        BOOKTITLE = \"Proceedings of MEMOCODE'04\",\n        YEAR = {2004},\n        ADDRESS = {San Diego,~CA}\n}\n\n@INPROCEEDINGS{ArvindNikhilRosenbandDave:HighLevelSynthesis,\n        AUTHOR = \"Arvind and Rishiyur S. Nikhil and Daniel L. Rosenband and Nirav Dave\",\n        TITLE = {{High-level Synthesis: An Essential Ingredient for Designing Complex ASICs}},\n        BOOKTITLE = \"Proceedings of ICCAD'04\",\n        YEAR = {2004},\n        ADDRESS = {San Jose,~CA}\n}\n\n@INPROCEEDINGS{ANRD:HighLevelSynthesis,\n        AUTHOR = \"Arvind and Rishiyur S. Nikhil and Daniel L. Rosenband and Nirav Dave\",\n        TITLE = {{High-level Synthesis: An Essential Ingredient for Designing Complex ASICs}},\n        BOOKTITLE = \"Proceedings of ICCAD'04\",\n        YEAR = {2004},\n        ADDRESS = {San Jose,~CA}\n}\n\n\n@INPROCEEDINGS{RosenbandArvind:ModularScheduling,\n        AUTHOR = \"Daniel L. Rosenband and Arvind\",\n        TITLE = {{Modular Scheduling of Guarded Atomic Actions}},\n        BOOKTITLE = \"Proceedings of DAC'04\",\n        YEAR = 2004,\n        ADDRESS = {San Diego,~CA}\n}\n\n@INPROCEEDINGS{Rosenband:PerformanceGuarantees,\n        AUTHOR = \"Daniel L. Rosenband and Arvind\",\n        TITLE = {{Hardware Synthesis from Guarded Atomic Actions with Performance Specifications}},\n        BOOKTITLE = \"Proceedings of ICCAD'05\",\n        YEAR = 2005,\n        ADDRESS = {San Jose,~CA}\n}\n\n@INPROCEEDINGS{Rosenband:EHR,\n        AUTHOR = \"Daniel L. Rosenband\",\n        TITLE = {{The Ephemeral History Register: Flexible Scheduling for Rule-Based Designs}},\n        BOOKTITLE = \"Proceedings of MEMOCODE'04\",\n        YEAR = {2004},\n        ADDRESS = {San Diego,~CA}\n}\n\n\n@INPROCEEDINGS{StoyShenArvind:Proofs,\n        AUTHOR = \"Joseph E. Stoy and Xiaowei Shen and Arvind\",\n        TITLE = {{Proofs of Correctness of Cache-Coherence Protocols}},\n        BOOKTITLE = {{Proceedings of FME'01: Formal Methods for Increasing Software Productivity}},\n        YEAR = {2001},\n        PAGES = {47--71},\n        PUBLISHER = {Springer-Verlag},\n        ADDRESS = {London,~UK}\n}\n\n@inproceedings{Bluespec:MCD,\n author = {Ed Czeck and Ravi Nanavati and Joe Stoy},\n title = {{Reliable Design with Multiple Clock Domains}},\n booktitle = {Proceedings of Formal Methods and Models for Codesign (MEMOCODE)},\n year = {2006}\n }\n \n@InProceedings{DPGA:80211,\n  author = {Nirav Dave and Michael Pellauer and Steve Gerding and Arvind},\n  title =  {{802.11a Transmitter: A Case Study in Microarchitectural Exploration}},\n  booktitle = {Proceedings of Formal Methods and Models for Codesign (MEMOCODE)},\n  year = {2006},\n  ADDRESS = {Napa,~CA}\n}\n\n@INPROCEEDINGS{DAP:CompositionScheduling,\n        AUTHOR = \"Nirav Dave and Arvind and Michael Pellauer\",\n        TITLE = {{Scheduling as Rule Composition}},\n        BOOKTITLE = \"Proceedings of Formal Methods and Models for Codesign (MEMOCODE)\",\n        YEAR = {2007},\n        ADDRESS = {Nice,~France}\n}\n\n@INPROCEEDINGS{Ng:OFDM,\n        AUTHOR = \"Man Cheuk Ng and Muralidaran Vijayaraghavan and Gopal Raghavan and Nirav Dave and Jamey Hicks and Arvind\",\n        TITLE = {{From WiFI to WiMAX: Techniques for IP Reuse Across Different OFDM Protocols}},\n        BOOKTITLE = \"Proceedings of Formal Methods and Models for Codesign (MEMOCODE)\",\n        YEAR = {2007},\n        ADDRESS = {Nice,~France}\n}\n\n@INPROCEEDINGS{MEMOCODE2011,\n        AUTHOR = \"Nirav Dave and Michael Katelman and Myron King and Jose Meseguer and Arvind\",\n        TITLE = {{Verification of Microarchitectural Refinements in Rule-based systems}},\n        BOOKTITLE = \"MEMOCODE\",\n        YEAR = {2011},\n        ADDRESS = {Cambridge,~UK}\n}\n\n\n@INPROCEEDINGS{Bluespec:H264,\n        AUTHOR = \"Kermin Fleming and Chun-Chieh Lin and Nirav Dave and Gopal Raghavan and Jamey Hicks and Arvind\",\n        TITLE = {{H.264 Decoder: A Case Study in Multiple Design Points}},\n        BOOKTITLE = \"Proceedings of Formal Methods and Models for Codesign (MEMOCODE)\",\n        YEAR = {2008},\n        ADDRESS = {Anaheim,~CA}\n}\n\n@INPROCEEDINGS{NordinHoe:SynchronousExtensions,\n        AUTHOR = \"Grace Nordin and James C. Hoe\",\n        TITLE = {{Synchronous Extensions to Operation-Centric Hardware Description Languages}},\n        BOOKTITLE = \"Proceedings of MEMOCODE'04\",\n        YEAR = 2004,\n        ADDRESS = {San Diego,~CA}\n}\n\n@inproceedings{Shen:CRF,\n author = {Xiaowei Shen and Arvind and Larry Rudolph},\n title = {Commit-reconcile \\& fences (CRF): a new memory model for architects and compiler writers},\n booktitle = {Proceedings of the 26th annual international symposium on Computer architecture},\n year = {1999},\n isbn = {0-7695-0170-2},\n pages = {150--161},\n location = {Atlanta, Georgia, United States},\n doi = {http://doi.acm.org/10.1145/300979.300992},\n publisher = {IEEE Computer Society},\n }\n\n\n@inproceedings{Fleming:FPGA,\n  author = {K. Fleming and M. Adler and M. Pellauer and A. Parashar and Arvind and J. Emer},\n  title = {Leveraging Latency-Insensitivity to Ease Multiple FPGA Design},\n  booktitle = {FPGA},\n  month = {February},\n  year = {2011}\n}\n\n\n@inproceedings{DBLP:conf/memocode/VijayaraghavanA09,\n  author    = {Muralidaran Vijayaraghavan and\n               Arvind},\n  title     = {Bounded Dataflow Networks and Latency-Insensitive circuits},\n  booktitle = {MEMOCODE},\n  year      = {2009},\n  pages     = {171-180},\n  ee        = {http://dx.doi.org/10.1109/MEMCOD.2009.5185393},\n  bibsource = {DBLP, http://dblp.uni-trier.de}\n}\n\n% --------------\n% Journal Articles\n% --------------\n\n@ARTICLE{HoeArvind:TRS_Synthesis2,\n        AUTHOR = \"James C. Hoe and Arvind\",\n        TITLE = {{Operation-Centric Hardware Description and Synthesis}},\n        JOURNAL = {{IEEE TRANSACTIONS on Computer-Aided Design of Integrated Circuits and Systems}},\n        VOLUME = {23},\n        NUMBER = {9},\n        MONTH = {September},\n        YEAR = {2004}\n}\n\n@ARTICLE{ArvindShen:TRS_Processors,\n        AUTHOR = \"Arvind and Xiaowei Shen\",\n        TITLE = {{Using Term Rewriting Systems to Design and Verify Processors}},\n        JOURNAL = {{IEEE Micro}},\n        VOLUME = {19},\n        NUMBER = {3},\n        PAGES = {36--46},\n        MONTH = May,\n        YEAR = {1999}\n}\n\n% --------------\n% Patents\n% --------------\n\n@MISC{ArvindHoe:Patent,\n        AUTHOR = \"Arvind and James C. Hoe\",\n        TITLE = {{Digital Circuit Synthesis System}},\n        MONTH = {July},\n        HOWPUBLISHED = {{United States Patent US 6,597,664 B1}},\n        YEAR = {2003}\n}\n\n@MISC{Esposito:Patent,\n        AUTHOR = {Thomas Esposito and Mieszko Lis and Ravi Nanavati and Joseph Stoy and Jacob Schwartz},\n        TITLE = {System and Method for Scheduling {TRS} Rules},\n        MONTH = {February},\n        HOWPUBLISHED = {{United States Patent US 133051-0001}},\n        YEAR = {2005}\n}\n\n\n% -------------\n% Other\n% -------------\n\n@misc{BSV:LangRef,\n    title = \"{Bluespec Language definition}\",\n    author = \"Lennart Augustsson and Jacob Schwarz and Rishiyur S. Nikhil\",\n    year = 2001,\n    pages = \"95\",\n    note = {{Sandburst Corp.}}\n}\n\n@MISC{Interra:QoR,\n        AUTHOR = {{Interra Systems}},\n        TITLE = {{Bluespec Testing Results: Comparing RTL Tool Output to Hand-designed RTL}},\n        HOWPUBLISHED = {{\\texttt{http://www.bluespec.com/images/pdfs/InterraReport042604.pdf}}},\n        MONTH = {April},\n        YEAR = {2004}\n}\n\n@MISC{Bluespec:www,\n        AUTHOR = {{Bluespec Inc.}},\n        HOWPUBLISHED = {{\\texttt{http://www.bluespec.com}}},\n}\n\n@MANUAL{Bluespec:TFRG,\n        TITLE = \"Bluespec SystemVerilog Version~3.8 Reference Guide\",\n        ORGANIZATION = \"Bluespec,~Inc.\",\n        ADDRESS = {Waltham,~MA},\n        MONTH = \"November\",\n        YEAR = {2004}\n}\n\n@MANUAL{Bluespec:UG,\n        TITLE = \"Bluespec SystemVerilog User Guide\",\n        ORGANIZATION = \"Bluespec,~Inc.\",\n        ADDRESS = {Waltham,~MA},\n        MONTH = \"November\",\n        YEAR = {2004}\n}\n\n@UNPUBLISHED{EckerEsenSteiniLis:BSV_Eval,\n        AUTHOR = {Volkan Esen and Thomas Steininger and Wolfgang Ecker and Mieszko Lis},\n        TITLE = {{A Case Study in Rule-based Synthesis for IP Reuse}},\n        NOTE = {Unpublished},\n        MONTH = {November},\n        YEAR = {2004}\n}\n\n\n\n% ----------------------------------------------------\n% Other Useful References\n% ----------------------------------------------------\n\n@INPROCEEDINGS{Haskell:STM,\n AUTHOR = {Tim Harris and Simon Marlow and Simon Peyton-Jones and Maurice Herlihy},\n TITLE = {Composable Memory Transactions},\n BOOKTITLE = {PPoPP '05: Proceedings of the tenth ACM SIGPLAN symposium on Principles and practice of parallel programming},\n YEAR = {2005}\n }\n\n@article{Dijkstra:GuardedCommands,\n author = {Edsger W. Dijkstra},\n title = {Guarded commands, nondeterminacy and formal derivation of programs},\n journal = {Commun. ACM},\n volume = {18},\n number = {8},\n year = {1975},\n issn = {0001-0782},\n doi = {http://doi.acm.org/10.1145/360933.360975},\n publisher = {ACM Press},\n address = {New York, NY, USA},\n }\n\n@book{ChandyMisra:Book,\n    AUTHOR = \"Chandy, K. Mani and Jayadev Misra\",\n    TITLE = \"Parallel Program Design: A Foundation\",\n    PUBLISHER = {Addison-Wesley},\n    ADDRESS = {Reading, Massachusetts},\n    YEAR = {1988}\n    }\n\n@MANUAL{SystemVerilog:LRM,\n        TITLE = \"SystemVerilog 3.1a Language Reference Manual\",\n        ORGANIZATION = \"Accelera Organization,~Inc.\",\n        ADDRESS = {Napa,~CA},\n        MONTH = \"May\",\n        YEAR = {2004}\n}\n\n@article{Hoare:CSP,\n author = {C. A. R. Hoare},\n title = {Communicating sequential processes},\n journal = {Commun. ACM},\n volume = {21},\n number = {8},\n year = {1978},\n issn = {0001-0782},\n pages = {666--677},\n doi = {http://doi.acm.org/10.1145/359576.359585},\n publisher = {ACM Press},\n address = {New York, NY, USA},\n }\n\n@INPROCEEDINGS{ SystemC,\n    AUTHOR = \"S. Y. Liao\",\n    TITLE = \"Towards a New Standard for System Level Design\",\n    PAGES = \"2--7\",\n    BOOKTITLE = {{Proceedings of the Eighth International Workshop on Hardware/Software Codesign}},\n    MONTH={May},\n    YEAR={2000},\n    ADDRESS= {San Diego, ~CA}\n}\n\n@article{Maessen:StoreAtomicity,\n  author    = {Jan-Willem Maessen and Arvind},\n  title     = {Store Atomicity for Transactional Memory},\n  journal   = {Electr. Notes Theor. Comput. Sci.},\n  volume    = {174},\n  number    = {9},\n  year      = {2007},\n  pages     = {117-137},\n  ee        = {http://dx.doi.org/10.1016/j.entcs.2007.04.009},\n  bibsource = {DBLP, http://dblp.uni-trier.de}\n}\n\n\n"
  },
  {
    "path": "doc/library/source/design/conclusion.rst",
    "content": ".. _Sec-Conclusion:\n\nConclusion\n==========\n\n`Connectal`_ bridges the gap between software and hardware development,\nenabling developers to create integrated solutions rapidly. With\nConnectal, we take a pragmatic approach to software and hardware\ndevelopment in which we try to avoid any dependence on proposed\nsolutions to open research problems.\n\nUse of Connectal's interface compiler ensures that software and\nhardware remain consistent and make it easy to update the\nhardware/software boundary as needed in a variety of execution\ncontexts. The generated portals permit concurrent and low-latency\naccess to the accelerator and enable different processes or the kernel\nto have safe isolated access through dedicated interfaces.  Support\nfor sharing memory between software and hardware makes it easy to\nachieve high transfer speeds between the two environments.\n\nConnectal supports Linux and Android operating systems running on x86\nand ARM CPUs. It currently supports Xilinx FPGAs and runs on the full\nrange of Xilinx Series 7 devices. Our fully-scripted development\nprocess enables the use of continuous integration of software and\nhardware development. Integrating software development early makes it\neasier to ensure that the complete solution actually meets design\ntargets and customer requirements.\n\n.. _Connectal: http://www.connectal.org/\n"
  },
  {
    "path": "doc/library/source/design/connectal-framework.rst",
    "content": ".. _Sec-Framework:\n\nThe Connectal Framework\n=======================\n\nIn and of themselves, none of the HW/SW interfaces considered in\nSection :ref:`Sec-StrStr` are particularly complex.  On the other hand,\nimplementing the complete set and maintaining correctness as the\napplication evolves is a considerable amount of care, requiring deep\nunderstanding of both the application and the platform.  The Connectal\nframework is a collection of tools and library components which was\ndesigned to address these challenges with the following features:\n\n\n* Easy declaration and invocation of remote methods between\n  application components running on the host or in the FPGA.\n\n* Direct user-mode access to hardware accelerators from software.\n\n* High performance read and write bus master access to system\n  memory from the FPGA\n\n* Infrastructure for sharing full speed memory port access between\n  an arbitrary number of clients in the FPGA fabric\n\n* Portability across platforms using different CPUs, buses,\n  operating systems, and FPGAs\n\n* Fully integrated tool-chain support for dependency builds and\n  device configuration.\n\nIn this section, we introduce the Connectal framework through a\ndiscussion of its prominent features.\n\nPortals\n-------\n\nConnectal implements remote method invocation between application\ncomponents using asynchronous messaging. The message and channel types\nare application specific, requiring the user to define the HW/SW\ninterface using BSV interfaces as the interface definition language\n(IDL).  These interfaces declare logical groups of unidirectional\n``send'' methods, each of which is implemented as a FIFO channel by\nthe Connectal interface compiler; all channels corresponding to a\nsingle BSV interface are grouped together into a single\n*portal*.\n\nFrom the interface specification, the Connectal interface compiler\ngenerates code for marshalling the arguments of a method into a\nmessage to be sent and unmarshaling values from a received\nmessage. It generates a \\textit{proxy} to be invoked on the sending\nside and a \\textit{wrapper} that invokes the appropriate method on the\nreceiving side.  Platform specific libraries are used to connect the\nproxies and wrappers to the communication fabric.\n\nIn the hardware, each portal is assigned a disjoint address range.  On\nthe host, Connectal assigns each portal a unique Linux device\n(/dev/portal*n*$) which is accessed by the application\nsoftware using the generated wrappers and proxies.  An application can\npartition methods across several portals, to control access to the\ninterfaces by specific hardware or software modules.  To support\nbi-directional communication, at least two portals are required: one\nwhich allows software to ``invoke'' hardware, and another for hardware\nto ``invoke'' software.  Each portal may be accessed by different\nthreads, processes, or directly from the kernel.\n\n\nDirect user-mode access to hardware\n-----------------------------------\n\nWe designed Connectal to provide direct access to accelerators from\nuser-mode programs in order to eliminate the need for device-drivers\nspecific to each accelerator.  We have implemented a kernel module for\nboth X86 and ARM architectures with a minimal set of functionality:\nthe driver implements \\textbf{mmap} to map hardware registers into\nuser space and \\textbf{poll} to enable applications to suspend a thread waiting for\ninterrupts originating from the hardware accelerators.  These two\npieces of functionality have been defined to be completely generic; no\nmodification is required to kernel drivers as the HW/SW interface\nevolves.  All knowledge of the interface register semantics (and\ncorresponding changes) is encoded by the interface compiler in the\ngenerated proxies and wrappers which are compiled as part of the\napplication and executed in user-mode.\n\nThis approach is known as user-space device\ndrivers~\\cite{Khalidi:1995:EZI:974947,UIO:Howto} and has a number of\ndistinct advantages over traditional kernel modules.  To begin with,\nit reduces the number of components that need to be modified if the\nHW/SW interface changes, and eliminates the need for device-driver\ndevelopment expertise in many cases.  Secondly, after the hardware\nregisters have been mapped into user address space, the need for\nsoftware to switch between user and kernel mode is all but eliminated\nsince all ``driver'' functionality is being executed in user-space.\n\nShared Access to Host Memory\n----------------------------\n\nConnectal generates a hardware FIFO corresponding to each method in\nthe portal interface, and the software reads and writes these FIFOs\nunder certain conditions. To improve throughput, Connectal libraries\nalso support credit-based flow-control. Though credit-based\nflow-control with interrupts is more efficient than polling status\nregisters from software, there is often the need for much higher\nbandwidth communication between the hardware and software.\n\nHardware accelerators often communicate with the application through\ndirect access to shared memory. An important feature of Connectal is a\nflexible, high performance API for allocating and sharing such memory,\nand support for reading and writing this memory from hardware and\nsoftware. The Connectal framework implements this through the\ncombination of a Linux kernel driver, C++ libraries, and BSV modules\nfor the FPGA.  We implemented a custom kernel memory allocator for\nConnectal, \\textbf{portalmem}, using the kernel dmabuf support.  Any\nsolution which allocates and shares memory between hardware and\nsoftware must meet two high-level requirements:\n\n* Allocated buffers must have reference counts to prevent memory \n      leaks.\n\n* Efficient mechanisms must be provided to share the location of \n      allocated regions.\n\n\nUsing the portalmem driver, programs can allocate regions of system\nmemory (DRAM) and map it into their own virtual address space.\nReference-counted access to shared memory regions allocated using\nportalmem can be granted to other SW processes by transmitting the\nfile descriptor for the allocated region.\nReference counting has been implemented in the driver so that\nonce an allocated memory region has been dereferenced by all SW and HW\nprocesses, it will be deallocated and returned to the kernel free\nmemory pool.\n\nSimple hardware accelerators often require contiguous physical\naddresses.  Unfortunately, when allocating memory from a shared pool\nin a running system, obtaining large areas of contiguous\nmemory is often problematic, limiting the size of the region that can\nbe allocated. To support indexed access to non-contiguous memory\naggregates, Connectal provides address translation support to hardware\naccelerators in the FPGA, similar to the MMU functionality on the CPU\nside.\n\n.. _Sec-MemReadEngine:\n\nDistributed Access to Memory Ports\n----------------------------------\n\nWhen building accelerators for an algorithm, multiple parameters are\noften accessed directly from system memory using DMA. As the hardware\nimplementation is parallelized, multiple accesses to each parameter\nmay be required.  In these cases, the number of memory clients in the\napplication hardware usually exceeds the number of host memory ports.\nSharing these ports requires substantial effort, and scaling up a\nmemory interconnect while maximizing throughput and clock speed is\nextremely challenging.\n\nTo support this common design pattern, the Connectal framework\nprovides provides a portable, scalable, high performance library that\napplications can use to to facilitate the efficient sharing of host\nmemory ports.  This library is implemented as parameterized Bluespec\nmodules which allow the user to easily configure high-performance\nmemory access trees, supporting both reading and writing.\n\nPlatform Portability\n--------------------\n\nWe structured Connectal to improve the portability of applications\nacross CPU types, operating systems, FPGAs, and how the CPU and FPGA\nare connected.  The software and hardware libraries are largely\nplatform independent.  As a result, applications implemented in the\nframework can be compiled to run on the range of different platforms.\n\nSupported platforms are shown in Figure :ref:`Fig-platforms`.\nApplication software can be executed on x86 and ARM CPUs running\neither Ubuntu or Android operating systems. A range of different\nXilinx FPGAs can be connected to the CPU and system memory via PCI\nExpress or AXI. The BSV simulator (Bluesim) can be used in place of\nactual FPGA hardware for debugging purposes.\n\nWhen the target application needs to interact with other Linux kernel\nresources (for example, a block device or a network interface), the\napplication may run in kernel mode with the logic run either in an\nFPGA or in Bluesim.\n\n.. image:: images/platforms.*\n\n.. _Fig-platforms: Platforms supported by Connectal\n   \n\n"
  },
  {
    "path": "doc/library/source/design/design.rst",
    "content": "Connectal Design\n****************\n\n.. toctree::\n   :maxdepth: 2\n\n   abstract.rst\n   introduction.rst\n   string-search.rst\n   connectal-framework.rst\n   implementing-string-search.rst\n   toolchain.rst\n   performance.rst\n   related-work.rst\n   conclusion.rst\n\n   portalstructure.rst\n   portal.rst\n   interface_definitions.rst\n   flowcontrol.rst\n   host_interface.rst\n"
  },
  {
    "path": "doc/library/source/design/flowcontrol.rst",
    "content": ".. _flow_control:\n\nFlow Control\n============\n\n"
  },
  {
    "path": "doc/library/source/design/host_interface.rst",
    "content": ".. host_interface:\n\nHost Interface\n==============\n"
  },
  {
    "path": "doc/library/source/design/images/Makefile",
    "content": "\nall: images\n\n%.png: %.pdf\n\tpdftoppm -singlefile -png $(*).pdf $(*)\n\nimages: \\\n    data_accel_logical0.png \\\n    data_accel_logical1.png \\\n    data_accel_logical2.png \\\n    data_accel_logical3.png \\\n    data_accel_logical4.png \\\n    MemreadEngine.png \\\n    msc0.png \\\n    msc1.png \\\n    msc2.png \\\n    platform.png \\\n    platforms.png\n"
  },
  {
    "path": "doc/library/source/design/implementing-string-search.rst",
    "content": ".. Sec-Impl:\n\nImplementing String Search\n==========================\n\nHaving covered the features of the Connectal at a high level, we now\nexplain more specifically how the framework can be applied to\nimplement the refinements outlined in Section :ref:`Sec-StrStr`.\n\nInitial Implementation\n----------------------\n\nThe FPGA is connected to the host system with a PCIe bus, and to the\nmemory array with wires.  In addition to implementing a search kernel,\nthe hardware accelerator must communicate with the software components\nand with the flash chips.  Communication with the software takes place\nthrough portals, whose interface declaration is given below::\n\n    interface StrstrRequest;\n      method Action setupNeedle(Bit#(8) needleChars);\n      method Action search(Bit#(32) haystackPtr,\n\t\t\t   Bit#(32) haystackLen);\n    endinterface\n    interface StrstrIndication;\n      method Action searchResult(Int#(32) v);\n      method Action setupComplete();\n    endinterface\n\nThe hardware implements the StrstrRequest interface, which the\nsoftware invokes (remotely) to specify the search string and the\nlocation in flash memory to search.  The software implements the\nStrstrIndication interface, which the hardware invokes (remotely) to\nnotify the software of configuration completion or search results.\nThe interface compiler generates a separate portal for each of these\ninterfaces. Within each portal, a dedicated unidirectional FIFO is\nassigned to each logical interface method.\n\nIn our initial implementation the accelerator does not access system\nmemory directly, so the search string is transmitted to the\naccelerator one character at a time via the {\\tt setupNeedle}\nmethod. We will see in Section :ref:Sec-StringSearchSystemMemory` how\nto use a pointer to system memory instead. \n\nInvoking Hardware from Software\n^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^\n\n\nBecause the StrStrRequest functionality is implemented in hardware,\nthe Connectal interface compiler generates a C++ \\textbf{proxy} with\nthe following interface to be invoked by the application software::\n\n    class StrStrRequestProxy : public Portal {\n    public:\n      void setupNeedle(uint32_t needleChars);\n      void search(uint32_t haystackPtr,\n\t\t  uint32_t haystackLen);\n    };\n\nThe implementation of StrStrRequestProxy marshals the arguments of\neach method and en-queues them directly into their dedicated hardware\nFIFOs. To execute searches in the FPGA fabric over data stored in\nflash memory, the software developer simply instantiates\n*StrStrRequestProxy* and invokes its methods::\n\n    StrStrRequestProxy *proxy = \n\t\tnew StrStrRequestProxy(...);\n    proxy->search(haystackPtr, haystackLen);\n\nOn the FPGA, the user implements the application logic as a BSV module\nwith the StrStrRequest interface. A *wrapper* is generated by\nthe interface compiler to connect this module to the hardware\nFIFOs. The wrapper unmarshals messages that it receives and then\ninvokes the appropriate method in the StrStrRequest interface.  Here\nis the BSV code that instantiates the generated wrapper and connects\nit to the user's \\texttt{mkStrStr} module::\n\n    StrStrRequest strStr <- mkStrStr(...);\n    StrStrRequestWrapper wrapper <-\n\tmkStrStrRequestWrapper(strStr);\n\nFigure :ref:`Fig-msc1`_ shows how all the pieces of an application\nimplemented using Connectal work together when hardware functionality\nis invoked remotely from software.  Direct access to the memory mapped\nhardware FIFOs by the generated proxy running in user-mode is key to\nthe efficiency of our implementation strategy.\n\n.. only:: html\n\n   .. image:: images/msc1.*\n\n.. only:: latexpdf\n\n   .. image:: design/images/msc1.png\n\n.. _Fig-msc1: \n\n.. figure:: images/msc1.png\n\n   SW invokes HW: *main* and *app HW* are implemented by the user.\n\n\nInvoking Software from Hardware\n^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^\n\nInvoking software from hardware takes a slightly different form, due\nprimarily to the fact that ``main'' is still owned by software.  Since\nthe direction of the remote invocation is reversed, the proxy on this\npath will be instantiated on the FPGA and the wrapper instantiated on\nhost side.  The user implements the StrStrResponse interface in\nsoftware and connects it to the generated wrapper using C++\nsubclasses::\n\n    class StrStrResponse:\n      public StrStrResponseWrapper {\n\t...\n      void searchResult(int32_t v) {...}\n    }\n\nThe StrStrResponseWrapper constructor registers a pointer to the\nobject with the event library which keeps track of all instantiated\nsoftware wrappers.  The wrapper implementation unmarshals messages\nsent through the hardware FIFOs and invokes the appropriate subclass\ninterface method.  To activate this path, main simply instantiates the\nresponse implementation and invokes the library event handler::\n\n      StrStrResponse *response = \n\tnew StrStrResponse(...);\n      while(1)\n\tportalExec_event();\n\nOn the invocation side, the interface compiler generates a proxy which\nthe application logic instantiates and invokes directly::\n\n    StrStrResponseProxy proxy <-\n\t mkStrStrRequestProxy();\n    StrStrRequest strStr <- \n\t mkStrStr(... proxy.ifc ...);\n\nFigure :ref:Fig-msc0 shows how all the pieces of an application\ncollaborate when software functionality is being invoked from\nhardware.\n\n.. only:: html\n\n   .. image:: images/msc0.*\n\n.. only:: latexpdf\n\n   .. image:: images/msc0.png\n\n.. _Fig-msc0:\n\n.. figure:: images/msc0.png\n\n       HW invokes SW: `main', `ind::wrapper', and `app HW' are implemented by the user.\n\nThe simplest software execution environment for the string search accelerator\nis to have a single thread making requests and waiting for responses as\nfollows::\n\n    void search(char *str){\n      StrStrRequestProxy *req = \n\tnew StrStrRequestProxy(...);\n      StrStrResponse *resp = \n\tnew StrStrResponse(...);\n      while (char c = *str++)\n\treq->setupNeedle(c);\n      // start search\n      req->search(...);\n      // handle responses from the HW\n      while(1)\n\tportalExec_event();\n    }\n\nThe call to :c:func:portalExec_event() checks for a response from HW.  If\nthere is a pending response, it invokes the method corresponding to\nthat FIFO in the wrapper class.  This generated method reads out a\ncomplete message from the FIFO and unmarshals it before invoking the\nuser-defined call-back function, which in this case would be\n\\texttt{StrStrResponse::searchResult}.\n\nConnecting To Flash\n^^^^^^^^^^^^^^^^^^^\n\nOn BlueDBM, one of our target platforms, the flash memory array is connected directly\nto the FPGA chip, and DDR signals are used to read/write/erase flash\nmemory cells. The RTL required to communicate with the memory requires\nsome commonly used functionality, such as *SerDes* and DDR\ncontrollers, both of which are included in the BSV libraries\ndistributed as part of the Connectal framework.\n\nMultithreading The Software\n---------------------------\n\nIn many cases, we would like to avoid a hardware-to-software path\nwhich requires the software to poll a hardware register on the other\nside of a bus for relatively infrequent events.  To accommodate this,\nthe Connectal framework generates interrupts which are raised when\nhardware invokes software interface methods.  The generic Connectal\ndriver connects these signals to the Linux kernel and the software\nwrappers can exploit then by calling poll.  Connectal applications\noften use a separate thread to execute hardware-to-software\nasynchronous invocations, since dedicated thread can put itself to sleep until the\nhardware raises an interrupt.  The ``main'' thread is free to do other\nwork and can communicate with the ``indication'' thread using a\nsemaphore as shown below::\n\n    class StrStrResponse:\n\tpublic StrStrResponseWrapper {\n      sem_t sem;\n      int v;\n      void searchResult(int32_t v) {\n\tthis->response = v;\n\tsem_post(&sem);\n      }\n      void waitResponse(){sem_wait(&sem);}\n    };\n    StrStrResponse *resp;\n    StrStrRequestProxy *req;\n    int search(char *str){\n      while (char c = *str++)\n\treq->setupNeedle(c);\n      // start search\n      req->search(...);\n      // wait for response\n      resp->waitResponse();\n      // return result\n      return resp->v;\n    }\n\nThe polling thread is started by a call\nto :c:func:portalExec_start(), which ultimately invokes\nthe :c:func:portalExec_poll() function implemented in the Connectal\nevent library.  :c:func:portalExec_poll() invokes the system call\n\\textbf{poll} on the FDs corresponding to all the indication or response portals,\nputting itself to sleep.  When an interface method is invoked in the\nhardware proxy, an interrupt is raised, waking the indication thread.\nA register is read which indicates which method is being called and\nthe corresponding wrapper method is invoked to read/marshal the\narguments and invoke the actual user-defined methods.\nFigure :ref:`Fig-msc2` shows this process.\n\n.. only:: html\n\n   .. image:: images/msc2.*\n\n.. only:: latexpdf\n\n   .. image:: images/msc2.png\n\n.. _Fig-msc2:\n\n.. figure:: \n\n    HW invokes SW using interrupts\n\nMultithreading often leads to simultaneous access to shared\nhardware resources.  If a software solution to protect\nthese resources (such as mutex) is not available, the hardware interface\ncan be refactored into separate portals, one for each control thread.\n\nEach interface will generate a separate Portal which is assigned its own\naddress space and Linux device.  Using Linux devices in this way\nenables access control restrictions to be specified individually for\neach portal.  This feature can be used to grant different users or\nprocesses exclusive access and prevent unauthorized access to specific\npieces of hardware functionality.\n\n.. Sec-StringSearchSystemMemory:\n\nShared Access to Host Memory\n----------------------------\n\n\nIn the first three refinements presented in Section :ref:`Sec-StrStr`,\nall communication between hardware and software takes place through\nregister-mapped IO.  The final refinement in\nSection :ref:`Sec-StrStrDma` is to grant hardware and software shared\naccess to host memory.  The interface to the search accelerator shown\nbelow has been updated to use direct access to system memory for the\nsearch strings::\n\n    interface StrstrRequest;\n      method Action setup(Bit#(32) needlePtr,\n\t\t\t  Bit#(32) mpNextPtr,\n\t\t\t  Bit#(32) needleLen);\n      method Action search(Bit#(32) haystackPtr,\n\t\t\t   Bit#(32) haystackLen,\n\t\t\t   Bit#(32) iterCount);\n    endinterface\n    interface StrstrIndication;\n       method Action searchResult(Int#(32) v);\n       method Action setupComplete();\n    endinterface\n\nIn order to share memory with hardware accelerators, it needs to be\nallocated using :c:func:portalAlloc(). Here is the search function updated\naccordingly::\n\n    int search(char *str){\n      int size = strlen(str)+1;\n      int fd = portalAlloc(size, 0);\n      char *sharedStr = portalMmap(fd, size);\n      strcpy(sharedStr, str);\n      // send a DMA reference to the search pattern\n      req->needle(dma->reference(fd), size);\n      // start search\n      req->search(...);\n      resp->waitResponse();\n      ... unmap and free the string\n      return resp->v;\n    }\n\nThe application allocates shared memory via {\\tt portalAlloc}, which\nreturns a file descriptor, and then passes that file descriptor to\n{\\tt mmap}, which maps the physical pages into the application's\naddress space. The file descriptor corresponds to a\ndmabuf\\cite{dmabuf}, which is a standard Linux kernel mechanism.\n\nTo share that memory with the accelerator, the application calls {\\tt\n  reference}, which sends a logical to physical address\nmapping to the hardware's address translator. The call to {\\tt\n  reference} returns a handle, which the application sends to\nthe accelerator. Connectal's BSV libraries for DMA enable the\naccelerator to read or write from offsets to these handles,\ntaking care of address translation transparently.\n\nTo fully exploit the data parallelism, {\\tt mkStrStr} partitions the\nsearch space into $p$ partitions. It instantiates two memory read\ntrees from the Connectal library ({\\tt MemReadEngineV}, discussed in\nSection :ref:`Sec-MemReadEngine`, each with $p$ read servers.  One set\nis used by the search kernels to read the configuration data from the\nhost memory, while the other is used to read the ``haystack'' from\nflash.\n\nOn supported platforms such as Zynq which provide multiple physical\nmaster connections to system memory, Connectal interleaves DMA\nrequests over the parallel links. It does this on a per-read-client\nbasis, rather than a per-request basis.\n\nAlternate Portal Implementations\n--------------------------------\n\nConnectal separates the generation of code for marshalling and\nunmarshaling method arguments from the transport mechanism used to\ntransmit the messages. This separation enables ``swappable''\napplication-specific transport libraries.  In light of this, a large\nnumber of transport mechanism can be considered. Switching between\nmechanism requires a simple directive in the project Makefile (more\ndetails are given in Section :ref:`Sec-ToolChain`).\n\nBy default, each portal is mapped to a region of address space and a\nmemory-mapped FIFO channel is generated for each method. Though\nsoftware access to all FIFO channels in a design may occur through\nsingle bus slave interface, Connectal libraries implement their\nmultiplexing to ensure that each FIFO is independent, allowing\nconcurrent access to different methods from multiple threads or\nprocesses.\n\nThe default portal library implements the method FIFOs in the hardware\naccelerator. This provides the lowest latency path between hardware\nand software, taking about 1 microsecond to send a message. If higher\nbandwidth or transaction rates are needed, FIFOs implemented as a ring buffer in DRAM can be\nused instead.  This requires more instructions per message send and\nreceive, but may achieve higher throughput between the CPU and\nhardware.\n\nDuring the design exploration process, a component originally\nimplemented on the FPGA may migrate to software running on the host\nprocessor.  Remote invocations which were originally from software to\nhardware must be recast as software to software. Without changing the\nIDL specification, the transport mechanism assigned to a portal can be\nre-specified to implement communication between software components\nrunning either on the same host or across a network.  \n\nConnectal uses UNIX sockets or shared memory to transport messages\nbetween the application software components or the hardware simulator.\nIn other situations, TCP or UDP can be used to transport the messages\nto hardware running on another machine.  Viable connections to the\nFPGA board range from low-speed interconnects such as JTAG, SPI, to\nhigher-speed interconnects such as USB or Aurora over multi-gigabit\nper second transceivers.\n"
  },
  {
    "path": "doc/library/source/design/interface_definitions.rst",
    "content": ".. _interface_definitions:\n\nInterface Declarations\n======================\n\n"
  },
  {
    "path": "doc/library/source/design/introduction.rst",
    "content": ".. Sec-Introduction:\n\nIntroduction\n************\n\nBecause they are so small and inexpensive, processors are now included\nin all but the smallest hardware designs. This grants flexibility to\nhardware designers because the non-performance-critical components can\nbe implemented in software and the performance-critical components\ncan be implemented in hardware.  Using software for parts of the\ndesign can decrease the effort required to implement configuration and\norchestration logic (for example). It can also offer hardware\ndevelopers greater adaptability in meeting new project requirements or\nsupporting additional applications.\n\nAs a system evolves through design exploration, the boundary between\nthe software and hardware pieces can change substantially.  The old\nparadigm of ``separate hardware and software designs before the\nproject starts'' is no longer sustainable, and hardware teams are\nincreasingly responsible for delivering significant software\ncomponents.\n\nDespite this trend, hardware engineers find themselves with\nsurprisingly poor support for the development of the software that is\nso integral to their project's success. They are often required to\nmanually develop the necessary software and hardware to connect the\ntwo environments. In the software world, this is equivalent to\nmanually re-creating header files from the prose description of an\ninterface implemented by a library.  Such ad hoc solutions are tedious,\nfragile, and difficult to maintain. Without a consistent framework and\ntoolchain for jointly managing the components of the hardware/software\nboundary, designers are prone to make simple errors which can be\nexpensive to debug.\n\nThe goal of our work is to support the flexible and consistent\npartitioning of designs across hardware and software components.  We\nhave identified the following four goals as central to this endeavor:\n\n\n* Connect software and hardware by compiling interface declarations.\n* Enable concurrent access to hardware accelerators from software.\n* Enable high-bandwidth sharing of system memory with hardware accelerators.\n* Provide portability across platforms (CPU, OS, bus types, FPGAs).\n\nIn this paper, we present a software-driven hardware development\nframework called `Connectal`_.  Connectal consists of a\nfully-scripted tool-chain and a collection of libraries which can be\nused to develop production quality applications comprised of software components running\non CPUs communicating with hardware components implemented in FPGA or\nASIC.\n\nWhen designing Connectal, our primary goal was to create a collection\nof components which are easy to use for simple implementations and\nwhich can be configured or tuned for high performance in more\ncomplicated applications.  To this end, we adopted a decidedly\nminimalist approach, attempting to provide the smallest viable\nprogramming interface which can guarantee consistent access to shared\nresources in a wide range of software and hardware execution\nenvironments.  Because our framework targets the implementation of\nperformance-critical systems rather than their simulation, we have\nworked hard to remove any performance penalty associated with its use.\n\nWe wrote the hardware components of the Connectal libraries in\n`Bluespec System Verilog`_\n(BSV) because it enables a higher level of abstraction than the\nalternatives and supports parameterized types.  The software\ncomponents are implemented in C/C++. We chose Bluespec interfaces as\nthe interface definition language (IDL) for Connectal's interface\ncompiler.\n\nThis paper describes the Connectal framework, and how it can be used\nto flexibly move between a variety of software environments and\ncommunication models when mapping applications to platforms with\nconnected FPGAs and CPUs.\n\nDocument Organization\n=====================\n\nIn Section :ref:`Sec-StrStr`, we present an example running in a\nnumber of different execution environments. In Section\n:ref:`Sec-Framework`, we give an overview of the Connectal framework\nand its design goals.  In Section :ref:`Sec-Impl` we discuss the\ndetails of Connectal and how it can be used to implement the\nexample. Section :ref:`Sec-ToolChain` describes the implementation of\nConnectal, supported platforms, and the tool chain used to coordinate\nthe various parts of the framework.  The paper concludes with a\ndiscussion of performance metrics and related work.\n\n.. _Connectal: http://www.connectal.org/\n.. _Bluespec System Verilog: http://www.bluespec.com/\n.. [Hoe:Thesis]: Hoe:Thesis\n.. [HoeArvind:TRS_Synthesis2]: HoeArvind:TRS_Synthesis2\n"
  },
  {
    "path": "doc/library/source/design/performance.rst",
    "content": ".. _Sec-Performance:\n\nPerformance of Generated Systems\n================================\n\nA framework is only useful if it reduces the effort required by\ndevelopers to achieve the desired performance objective. Trying to gauge the\nrelative effort is difficult since the authors implemented both the\nframework and the running example. On PCIE-based platforms we were\nable to reduce the time required to search for a fixed set of strings\nin a large corpus by an order of magnitude after integrating hardware\nacceleration using Connectal.  Performance improvements on the\nZynq-based platforms was even greater due to the relative processing\npower of the ARM CPU and scaled with the number of bus master\ninterfaced used for DMA.  In the Connectal framework, developing these\napplications took very little time.\n\nPerformance of Portals\n----------------------\n\nThe current implementation of HW/SW \\textbf{portal} transfers 32 bits\nper FPGA clock cycle. Our example designs run at 100MHz to 250MHz,\ndepending on the complexity of the design and the speed grade of the\nFPGA used. Due to their intended use, the important performance metric\nof Portals is latency.  These values are given in\nFigure~\\ref{Fig:PortalLatency}.\n\n    \\begin{figure}\n      \\centering\n      \\begin{tabular}{|c|c|c|c|c|c|c|c|c|}\n\t\\hline\n\t     & \\rt{KC705} & \\rt{VC707} & \\rt{ZYBO} & \\rt{Zedboard} & \\rt{ZC702} & \\rt{ZC706} & \\rt{Parallel} & \\rt{Mini-ITX} \\\\\n\t\\hline\n\tHW $\\rightarrow$ SW  &  3  &  3  &  X  &  0.80  &  0.80  &  0.65  &  X  &  0.65  \\\\\n\t\\hline\n\tSW $\\rightarrow$ HW  & 5  &  5  &  X  &  1.50  &  1.50 &  1.10  &  X  &  1.10  \\\\\n\t\\hline\n      \\end{tabular}\n      \\caption{Latency ($\\mu$s) of communication through portals on supported\n\tplatforms\\label{Fig:PortalLatency}}\n    \\end{figure}\n\nThe Xilinx KC705 and VC707 boards connect to x86 CPUs and system\nmemory via PCIe gen1. The default FPGA clock for those boards is\n125MHz.  The other platforms use AXI to connect the programmable logic\nto the quad-core ARM Cortex A9 and system memory. The ZYBO, Zedboard\nand ZC702 use a slower speed grade part on which our designs run at\n100MHz. The ZC706 and Mini-ITX use a faster part on which many of our\ndesigns run at 200MHz. The lower latency measured on the ZC706\nreflects the higher clock speed of the latency performance test.\n\nPerformance of Reads/Writes of System Memory\n--------------------------------------------\n\nFor high bandwidth transfers, we assume the developer will have the\napplication hardware read or write system memory directly. Direct\naccess to memory enables transfers with longer bursts, reducing memory\nbus protocol overhead. The framework supports transfer widths of 32 to\n128 bits per cycle, depending on the interconnect used. \n\nOur goal in the design of the library components used to read and\nwrite system memory is to ensure that a developer's application can\nuse all bandwidth available to the FPGA when accessing system memory.\nDMA Bandwidth on supported platforms is listed in\nFigure\\ref{Fig:DmaBandwidth}.\n\n    \\begin{figure}\n      \\centering\n      \\begin{tabular}{|c|c|c|c|c|c|c|c|c|}\n\t\\hline\n\t     & \\rt{KC705} & \\rt{VC707} & \\rt{ZYBO} & \\rt{Zedboard} & \\rt{ZC702} & \\rt{ZC706} & \\rt{Parallel} & \\rt{Mini-ITX} \\\\\n\t\\hline\n\tRead  &  1.4  &  1.4  &  X  &  0.8  &  0.8  &  1.6  &  X  &  1.6  \\\\\n\t\\hline\n\tWrite  &  1.4  &  1.4  &  X  &  0.8  &  0.8  &  1.6  &  X  &  1.6  \\\\\n\t\\hline\n      \\end{tabular}\n      \\caption{Maximum bandwidth (GB/s) between FPGA and host memory using\n\tConnectal RTL libraries on supported\n\tplatforms\\label{Fig:DmaBandwidth}}\n    \\end{figure}\n\nOn PCIe systems, Connectal currently supports 8 lane PCIe gen1. We've\nmeasured 1.4 gigabytes per second for both reads and writes. Maximum\nthroughput of 8 lane PCIe gen1 is 1.8GB/s, taking into account 1\nheader transaction per 8 data transactions, where 8 is the maximum\nnumber of data transactions per request supported by our server's\nchipset.  The current version of the test needs some more tuning in order to\nreach the full bandwidth available. In addition, we are\nin the process of updating to 8 lane PCIe gen2 using newer Xilinx\ncores.\n\nZynq systems have four *high performance* ports for accessing system\nmemory. Connectal enables an accelerator to use all four. In our\nexperiments, we have been able to achieve 3.6x higher bandwidth using\n4 ports than using 1 port.\n\n\n\n"
  },
  {
    "path": "doc/library/source/design/portal.rst",
    "content": "\n==================\nWhat is Connectal?\n==================\n\nConnectal provides a hardware-software interface for applications split\nbetween user mode code and custom hardware in an FPGA or ASIC.\n\nConnectal can automaticaly build the software and hardware glue for a\nmessage based interface and also provides for configuring and using\nshared memory between applications and hardware. Communications\nbetween hardware and software are provided by a bidirectional flow of\nevents and regions of memory shared between hardware and software.\nEvents from software to hardware are called requests and events from\nhardware to software are called indications, but in fact they are\nsymmetric.\n\n.. _bsvdocumentation: http://wiki.bluespec.com/Home/BSV-Documentation\n.. _bluespecdotcom:     http://www.bluespec.com/\n\nLexicon\n-------\n\nconnectal:: The name of the project, whose goal is to ease the task of\nbuilding applications composed of hardware and software components.\nProgrammers use bsv as an IDL to specify the interface between the\nhardware and software components.  A combination of generated code and\nlibraries coordinate the data-flow between the program modules.\nBecause the HW and SW stacks are customized for each application, the\noverheads associated with communicating across the HW/SW boundary are\nlow.\n\nHW/SW interface :: portal\n\nbsv:: Bluespec System Verilog.  bsv is a language for describing hardware that is might higher level than verilog. See {bsvdocumentation}[BSV Documentation] and {bluespecdotcom}[Bluespec, Inc].\n\nbluespec:: Shorthand for Bluespec System Verilog (bsv)\n\nindexterm:portal\nportal:: a logical request/indication pair is referred to as a portal.  current tools require their specification in the IDL to be syntactically identifiable (i.e. fooRequest/fooIndication).  An application can make use of multiple portals, which may be specified independently.\n\nrequest interface:: These methods are implemented by the application hardware to be invoked by application software.   A bsv interface consisting of ‘Action’ methods.  Because of the ‘Action’ type, data flow across this interface is unidirectional (SW -> HW).\n\nindication interface:: The dual of a request interface, indication interfaces are ‘Action’ methods implemented by application software to be invoked by application hardware.   As with request interfaces, the data flow across this interface is unidirectional, but in the opposite direction.\n\npcieportal/zynqportal:: these two loadable kernel modules implement the minimal set of driver functionality.  Specifically, they expose portal HW registers to SW through mmap, and set up interrupts to notify SW that an indication method has been invoked by HW.  \n\nportalalloc:: This loadable kernel module exposes a subset of dma-buf functionality to user-space software (though a set of ioctl commands) to allocate and manage memory regions which can be shared between SW and HW processes.   Maintaining coherence of the allocated buffers between processes is not automatic: ioctl commands for flush/invalidate are provided to be invoked explicitly by the users if necessary. \n\nconnectalgen:: The name of the interface compiler which takes as input the bsv interface specification along with a description of a target platform and generates logic in both HW and SW to support this interface across the communication fabric.\n\nExample setups:\n---------------\n\nA zedboard ( http://www.zedboard.org/ ),\nwith Android running on the embedded ARM processors (the Processing\nSystem 7), an application running as a user process, and custom\nhardware configured into the Programmable Logic FPGA.\n\nAn x86 server, with Linux running on the host processor, an\napplication running partly as a user process on the host and partly as\nhardware configured into an FPGA connected by PCI express (such as the\nXilinx VC707\n(http://www.xilinx.com/products/boards-and-kits/EK-V7-VC707-G.htm).\n\nBackground\n----------\n\nWhen running part or all of an application in an FPGA, it is usually\nnecessary to communicate between code running in user mode on the host\nand the hardware.  Typically this has been accomplished by custom\ndevice drivers in the OS, or by shared memory mapped between the\nsoftware and the hardware, or both.  Shared memory has been\nparticularly troublesome under Linux or Android, because devices\nfrequently require contiguous memory, and the mechanisms for\nguaranteeing successful memory allocation often require reserving the\nmaximum amount of memory at boot time.\n\nPortal tries to provide convenient solutions to these problems in a portable way.\n\nIt is desirable to have\n\n* low latency for small messages\n\n* high bandwidth for large messages\n\n* notification of arriving messages\n\n* asynchronous replies to messages\n\n* support for hardware simulation by a separate user mode process\n\n* support for shared memory (DMA) between hardware and software\n\n\nOverview\n--------\n\nPortal is implemented as a loadable kernel module device driver for Linux/Android and a set of tools to automatically construct the hardware and software glue necessary for communications.\n\nShort messages are handled by programmed I/O.  The message interface\nfrom software to hardware (so called \"requests\") is defined as a bsv\ninterface containing a number of Action methods, each with a name and\ntyped arguments.  The interface generator creates all the software and\nhardware glue so that software invocations of the interface stubs flow\nthrough to, and are turned into bsv invocations of the matching\nhardware.  The machinery does not have flow control. Software is\nresponsible for not overrunning the hardware.  There is a debug\nmechanism which will return the request type of a failed method, but\nit does not tell which invocation failed.  Hardware to software\ninterfaces (so called “indications”) are likewise defined by bsv\ninterfaces containing Action methods. Hardware invocations of these\nmethods flow through to and cause software calls to corresponding\nuser-supplied functions.  In the current implementation there is flow\ncontrol, in that the hardware will stall until there is room for a\nhardware to software message.  There is also a mechanism for software\nto report a failure, and there is machinery for these failures to be\nreturned to the hardware.\n\n    [\"seqdiag\",target=\"request-response-1.png\"]\n    ---------------------------------------------------------------------\n    {\n      // edge label\n      SW -> HW [label = \"request\"];\n      SW <- HW [label = \"indication\"];\n    }\n    ---------------------------------------------------------------------\n\nPortals do not have to be structured as request/response. Hardware can\nsend messages to software without a prior request from software.\n\n    [\"seqdiag\",target=\"indication-only.png\"]\n    ---------------------------------------------------------------------\n    {\n      // edge label\n      SW <- HW [label = \"indication\"];\n    }\n    ---------------------------------------------------------------------\n\nIncoming messages can cause host interrupts, which wake up the device\ndriver, which can wake up the user mode application by using the\nselect(2) or poll(2) interfaces.\n\n\nMost of the time, communications between hardware and software will\nproceed without requiring use of the OS.  User code will read and\nwrite directly to memory mapped I/O space. Library code will poll for\nincoming messages, and [true? eventually time out and call poll(2).\nOnly when poll(2) or select(2) are called will the device driver\nenable hardware interrupts.  Thus interrupts are only used to wake up\nsoftware after a quiet period.\n\nThe designer specifies a set of hardware functions that can be called\nfrom software, and a set of actions that the hardware can take which\nresult in messages to software. Portal tools take this specification\nand build software glue modules to translate software function calls\ninto I/O writes to hardware registers, and to report hardware events\nto software.\n\nFor larger memory and OS bypass (OS bypass means letting the user mode\napplication talk directly to the hardware without using the OS except\nfor setup), portal implements shared memory.  Portal memory objects\nare allocated by the user mode program, and appear as Linux file\ndescriptors. The user can mmap(2) the file to obtain user mode access\nto the shared memory region. Portal does not assure that the memory is\nphysically contiguous, but does pin it to prevent the OS from reusing\nthe memory.  An FPGA DMA controller module is provided that gives the\nillusion of contiguous memory to application hardware, while under the\ncovers using a translation table of scattered addresses.\n\nThe physical addresses are provided to the user code in order to\ninitialize the dma controller, and address \"handles\" are provided for\nthe application hardware to use.\n\nThe DMA controller provides Bluespec objects that support streaming access with automatic page crossings, or random access.\n\nAn Example\n----------\n\nAn application developer will typically write the hardware part of the\napplication in Bluespec and the software part of the application in C\nor C++.  In a short example, there will be a bsv source file for the\nhardware and a cpp source file for the application.\n\nThe application developer is free to specify whatever hardware-software interface makes sense.\n\nRefer to https://github.com/cambridgehackers/connectal\n\nIn the examples directory, see [simple](../examples/simple/).  The\nfile [Simple.bsv](../examples/simple/Simple.bsv) defines the hardware,\nand testsimple.cpp supplies the software part. In this case, the\nsoftware part is a test framework for the hardware.\n\nSimple.bsv declares a few `struct` and `enum` types::\n\n    typedef struct{\n       Bit#(32) a;\n       Bit#(32) b;\n       } S1 deriving (Bits);\n\n    typedef struct{\n       Bit#(32) a;\n       Bit#(16) b;\n       Bit#(7) c;\n       } S2 deriving (Bits);\n\n    typedef enum {\n       E1Choice1,\n       E1Choice2,\n       E1Choice3\n       } E1 deriving (Bits,Eq);\n\n    typedef struct{\n       Bit#(32) a;\n       E1 e1;\n       } S3 deriving (Bits);\n\nSimple.bsv defines the actions (called Requests) that software can use\nto cause the hardware to act, and defines the notifications (called\nIndications) that the hardware can use to signal the software. ::\n\n    interface SimpleIndication;\n\tmethod Action heard1(Bit#(32) v);\n\tmethod Action heard2(Bit#(16) a, Bit#(16) b);\n\tmethod Action heard3(S1 v);\n\tmethod Action heard4(S2 v);\n\tmethod Action heard5(Bit#(32) a, Bit#(64) b, Bit#(32) c);\n\tmethod Action heard6(Bit#(32) a, Bit#(40) b, Bit#(32) c);\n\tmethod Action heard7(Bit#(32) a, E1 e1);\n    endinterface\n\n    interface SimpleRequest;\n\tmethod Action say1(Bit#(32) v);\n\tmethod Action say2(Bit#(16) a, Bit#(16) b);\n\tmethod Action say3(S1 v);\n\tmethod Action say4(S2 v);\n\tmethod Action say5(Bit#(32)a, Bit#(64) b, Bit#(32) c);\n\tmethod Action say6(Bit#(32)a, Bit#(40) b, Bit#(32) c);\n\tmethod Action say7(S3 v);\n    endinterface\n\nSoftware can start the hardware working via say, say2, ... Hardware\nsignals back to software with heard and heard2 and so fort.  In the\ncase of this example, say and say2 merely echo their arguments back to\nsoftware.\n\nThe definitions in the bsv file are used by the connectal infrastructure ( a python program)  to automatically create corresponding c++ interfaces.::\n\n    ../../connectalgen -Bbluesim -p bluesim -x mkBsimTop \\\n         -s2h SimpleRequest \\\n         -h2s SimpleIndication \\\n         -s testsimple.cpp \\\n         -t ../../bsv/BsimTop.bsv  Simple.bsv Top.bsv\n\nThe tools have to be told which interface records should be used for\nSoftware to Hardware messages and which should be used for Hardware to\nSoftware messages. These interfaces are given on the command line for\ngenxpprojfrombsv\n\nconnectalgen constructs all the hardware and software modules\nneeded to wire up portals. This is sort of like an RPC compiler for\nthe hardware-software interface. However, unlike an RPC each method is\nasynchronous.\n\nThe user must also create a toplevel bsv module Top.bsv, which\ninstantiates the user portals, the standard hardware environment, and\nany additional hardware modules.\n\nRather than constructing the *makefilegen* command line from\nscratch, the examples in connectal use include\n*Makefile.connectal* and define some *make*\nvariables.\n\nHere is the Makefile for the `simple` example::\n\n    CONNECTALDIR?=../..\n    INTERFACES = SimpleRequest SimpleIndication\n    BSVFILES = Simple.bsv Top.bsv\n    CPPFILES=testsimple.cpp\n\n    include $(CONNECTALDIR)/Makefile.connectal\n\n\n\nDesigns outside the connectal directory using `connectal` may also include `Makefile.connectal`::\n\n    CONNECTALDIR?=/scratch/connectal\n    INTERFACES = ...\n    BSVFILES = ...\n    CPPFILES = ...\n    include $(CONNECTALDIR)/Makefile.connectal\n\nsimple/Top.bsv\n---------------\n\nEach CONNECTAL design implements [Top.bsv](../examples/simple/Top.bsv) with some standard components.\n\nIt defines the `IfcNames` enum, for use in identifying the portals between software and hardware::\n\n    typedef enum {SimpleIndication, SimpleRequest} IfcNames deriving (Eq,Bits);\n\nIt defines `mkConnectalTop`, which instantiates the wrappers, proxies, and the design itself::\n\n    module mkConnectalTop(StdConnectalTop#(addrWidth));\n\n\n\n:bsv:module:StdConnectalTop is parameterized by `addrWidth` because Zynq and x86 have different width addressing. `StdConnectalTop` is a typedef::\n\n    typedef ConnectalTop#(addrWidth,64,Empty)     StdConnectalTop#(numeric type addrWidth);\n\nThe \"64\" specifies the data width and `Empty` specifies the empty\ninterface is exposed as pins from the design. In designs using HDMI,\nfor example, `Empty` is replaced by `HDMI`.  On some platforms, the\ndesign may be able to use different data widths, such as 128 bits on\nx86/PCIe.\n\nNext, `mkConnectalTop` instantiates user portals::\n\n    // instantiate user portals\n       SimpleIndicationProxy simpleIndicationProxy <- mkSimpleIndicationProxy(SimpleIndication);\n\nInstantiate the design::\n\n       SimpleRequest simpleRequest <- mkSimpleRequest(simpleIndicationProxy.ifc);\n\nInstantiate the wrapper for the design::\n\n       SimpleRequestWrapper simpleRequestWrapper <- mkSimpleRequestWrapper(SimpleRequest,simpleRequest);\n\nCollect the portals into a vector::\n\n       Vector#(2,StdPortal) portals;\n       portals[0] = simpleRequestWrapper.portalIfc; \n       portals[1] = simpleIndicationProxy.portalIfc;\n\nCreate an interrupt multiplexer from the vector of portals::\n\n       let interrupt_mux <- mkInterruptMux(portals);\n\nCreate the system directory, which is used by software to locate each portal via the `IfcNames` enum::\n\n       // instantiate system directory\n       StdDirectory dir <- mkStdDirectory(portals);\n       let ctrl_mux <- mkAxiSlaveMux(dir,portals);\n\nThe following generic interfaces are used by the platform specific top BSV module::\n\n       interface interrupt = interrupt_mux;\n       interface ctrl = ctrl_mux;\n       interface m_axi = null_axi_master;\n       interface leds = echoRequestInternal.leds;\n\n    endmodule : mkConnectalTop\n\nsimple/testsimple.cpp\n---------------------\n\nCONNECTAL generates header files declaring wrappers for\nhardware-to-software interfaces and proxies for software-to-hardware\ninterfaces. These will be in the \"jni/\" subdirectory of the project directory. ::\n\n    #include \"SimpleIndication.h\"\n    #include \"SimpleRequest.h\"\n\n\nIt also declares software equivalents for structs and enums declared in the processed BSV files::\n\n    #include \"GeneratedTypes.h\"\n\n\nCONNECTAL generates abstract virtual base classes for each Indication interface. ::\n\n    class SimpleIndicationWrapper : public Portal {\n\n    public:\n\t...\n\tSimpleIndicationWrapper(int id, PortalPoller *poller = 0);\n\tvirtual void heard1 ( const uint32_t v )= 0;\n\t...\n    };\n\nImplement subclasses of the wrapper in order to define the callbacks::\n\n    class SimpleIndication : public SimpleIndicationWrapper\n    {  \n    public:\n      ...\n\tvirtual void heard1(uint32_t a) {\n\t  fprintf(stderr, \"heard1(%d)\\n\", a);\n\t  assert(a == v1a);\n\t  incr_cnt();\n\t}\n\t...\n    };\n\nTo connect these classes to the hardware, instantiate them using the\n`IfcNames` enum identifiers. CONNECTAL prepends the name of the type\nbecause C++ does not support overloading of enum tags. ::\n\n    SimpleIndication *indication = new SimpleIndication(IfcNames_SimpleIndication);\n    SimpleRequestProxy *device = new SimpleRequestProxy(IfcNames_SimpleRequest);\n\n\nCreate a thread for handling notifications from hardware::\n\n    pthread_t tid;\n    if(pthread_create(&tid, NULL,  portalExec, NULL)){\n      exit(1);\n    }\n\nNow the software invokes hardware methods via the proxy::\n\n    device->say1(v1a);  \n\n    device->say2(v2a,v2b);\n\n\nSimple Example Design Structure\n-------------------------------\n\nThe `simple` example consists of the following files::\n\n    Simple.bsv\n    Makefile\n    Top.bsv\n    testsimple.cpp\n\nAfter running `make BOARD=zedboard verilog` in the `simple` directory,\nthe `zedboard` project directory is created, populated by the generated files.\n\nA top level `Makefile` is created::\n\n    zedboard/Makefile\n\nmakefilegen generates wrappers for software-to-hardware interfaces and proxies for hardware-to-software interfaces::\n\n    zedboard/sources/mkzynqtop/SimpleIndicationProxy.bsv\n    zedboard/sources/mkzynqtop/SimpleRequestWrapper.bsv\n\nConnectal supports Android on Zynq platforms, so connectalgen generates `jni/Android.mk` for `ndk-build`::\n\n    zedboard/jni/Android.mk\n    zedboard/jni/Application.mk\n\nConnectal generates `jni/Makefile` to compile the software for PCIe platforms (vc707 and kc705):\n\n    zedboard/jni/Makefile\n\nCONNECTAL generates software proxies for software-to-hardware interfaces and software wrappers for hardware-to-software interfaces::\n\n    zedboard/jni/SimpleIndication.h\n    zedboard/jni/SimpleIndication.cpp\n    zedboard/jni/SimpleRequest.cpp\n    zedboard/jni/SimpleRequest.h\n\nCONNECTAL also generates `GeneratedTypes.h` for struct and enum types in the processed BSV source files::\n\n    zedboard/jni/GeneratedTypes.h\n\nCONNECTAL copies in standard and specified constraints files::\n\n    zedboard/constraints/design_1_processing_system7_1_0.xdc\n    zedboard/constraints/zedboard.xdc\n\nCONNECTAL generates several TCL files to run `vivado`. \n\nThe `board.tcl` file specifies `partname`, `boardname`, and `connectaldir` for the other TCL scripts.::\n\n    zedboard/board.tcl\n\nTo generate an FPGA bit file, run `make bits`. This runs vivado with the `mkzynqtop-impl.tcl` script.::\n\n    zedboard/mkzynqtop-impl.tcl\n\n\nmake verilog\n^^^^^^^^^^^^\n\nCompiling to verilog results in the following verilog files::\n\n    zedboard/verilog/top/mkSimpleIndicationProxySynth.v\n    zedboard/verilog/top/mkZynqTop.v\n\nVerilog library files referenced in the design are copied for use in synthesis.::\n\n    zedboard/verilog/top/FIFO1.v\n    ...\n\nmake bits\n^^^^^^^^^\n\nRunning `make bits` in the zedboard directory results in timing reports::\n\n    zedboard/bin/mkzynqtop_post_place_timing_summary.rpt\n    zedboard/bin/mkzynqtop_post_route_timing_summary.rpt\n    zedboard/bin/mkzynqtop_post_route_timing.rpt\n\nand some design checkpoints::\n\n    zedboard/hw/mkzynqtop_post_synth.dcp\n    zedboard/hw/mkzynqtop_post_place.dcp\n    zedboard/hw/mkzynqtop_post_route.dcp\n\nand the FPGA configuration file in .bit and .bin formats::\n\n    zedboard/hw/mkZynqTop.bit\n    zedboard/hw/mkZynqTop.bin\n\nmake android_exe\n^^^^^^^^^^^^^^^^\n\nCONNECTAL supports Android 4.0 on Zynq platforms. It generates\n`jni/Android.mk` which is used by `ndk-build` to create a native\nAndroid executable.::\n\n    make android_exe\n\nThis produces the ARM elf executable::\n\n    libs/armeabi/android_exe\n\nmake run\n^^^^^^^^\n\nFor Zynq platforms::\n\n    make run\n\nwill copy the Android executable and FPGA configuration file to the\ntarget device, program the FPGA, and run the executable. See\n[run.android](../scripts/run.android) for details.\n\nIt uses `checkip` to determine the IP address of the\ndevice via a USB console connection to the device (it is built/installed\non the host machine from the git repo cambridgehackers/consolable). If the target is\nnot connected to the build machine via USB, specify the IP address of\nthe target manually::\n\n    make RUNPARAM=ipaddr run\n\nFor PCIe platforms, `make run` programs the FPGA via USB and runs the software locally.\n\nFor bluesim, `make run` invokes bluesim on the design and runs the software locally.\n\nShared Memory\n-------------\n\nShared Memory Hardware\n^^^^^^^^^^^^^^^^^^^^^^\n\nIn order to use shared memory, the hardware design instantiates a DMA module in Top.bsv::\n\n   AxiDmaServer#(addrWidth,64) dma <- mkAxiDmaServer(dmaIndicationProxy.ifc, readClients, writeClients);\n\nThe AxiDmaServer multiplexes read and write requests from the\nclients, translates DMA addresses to physical addresses, initiates bus\ntransactions to memory, and delivers responses to the clients.\n\nDMA requests are specified with respect to \"portal\" memory allocated\nby software and identified by a `pointer`.\n\nRequests and responses are tagged in order to enable pipelining::\n\n    typedef struct {\n       SGLId pointer;\n       Bit#(MemOffsetSize) offset;\n       Bit#(8) burstLen;\n       Bit#(6)  tag;\n       } MemRequest deriving (Bits);\n\n    typedef struct {\n       Bit#(dsz) data;\n       Bit#(6) tag;\n       } MemData#(numeric type dsz) deriving (Bits);\n\nRead clients implement the `MemReadClient` interface. On response to\nthe read, `burstLen` `MemData` items will be put to the `readData`\ninterface. The design must be ready to consume the data when it is\ndelivered from the memory bus or the system may hang::\n\n    interface MemReadClient#(numeric type dsz);\n       interface GetF#(MemRequest)    readReq;\n       interface PutF#(MemData#(dsz)) readData;\n    endinterface\n\nWrite clients implement `MemWriteClient`. To complete the transaction,\n`burstLen` data items will be consumed from the `writeData`\ninterace. Upon completion of the request, the specified tag will be\nput to the `writeDone` interface. The data must be available when the\nwrite request is issued to the memory bus or the system may hang::\n\n    interface MemWriteClient#(numeric type dsz);\n       interface GetF#(MemRequest)    writeReq;\n       interface GetF#(MemData#(dsz)) writeData;\n       interface PutF#(Bit#(6))       writeDone;\n    endinterface\n\nA design may implement `MemReadClient` and `MemWriteClient` interfaces directly, or it may instantiate DmaReadBuffer or DmaWriteBuffer.\n\nThe `AxiDmaServer` is configured with physical address translations\nfor each region of memory identified by a `pointer`. A design using\nDMA must export the `DmaConfig` and `DmaIndication` interfaces of the\nDMA server.\n\nHere are the DMA components of [memread_nobuff/Top.bsv](../examples/memread_nobuff/Top.bsv):\n\nInstantiate the design and its interface wrappers and proxies::\n\n    MemreadIndicationProxy memreadIndicationProxy <- mkMemreadIndicationProxy(MemreadIndication);\n    Memread memread <- mkMemread(memreadIndicationProxy.ifc);\n    MemreadRequestWrapper memreadRequestWrapper <- mkMemreadRequestWrapper(MemreadRequest,memread.request);\n\nCollect the read and write clients::\n\n    Vector#(1, MemReadClient#(64)) readClients = cons(memread.dmaClient, nil);\n    Vector#(0, MemReadClient#(64)) writeClients = nil;\n\nInstantiate the DMA server and its wrapper and proxy::\n\n    DmaIndicationProxy dmaIndicationProxy <- mkDmaIndicationProxy(DmaIndication);\n    AxiDmaServer#(addrWidth,64) dma <- mkAxiDmaServer(dmaIndicationProxy.ifc, readClients, writeClients);\n    DmaConfigWrapper dmaConfigWrapper <- mkDmaConfigWrapper(DmaConfig,dma.request);\n\nInclude `DmaConfig` and `DmaIndication` in the portals of the design::\n\n    Vector#(4,StdPortal) portals;\n    portals[0] = memreadRequestWrapper.portalIfc;\n    portals[1] = memreadIndicationProxy.portalIfc; \n    portals[2] = dmaConfigWrapper.portalIfc;\n    portals[3] = dmaIndicationProxy.portalIfc; \n\nThe code generation tools will then produce the software glue necessary for the shared memory support libraries to initialize the DMA \"library module\" included in the hardware.\n\nShared Memory Software\n^^^^^^^^^^^^^^^^^^^^^^\n\nThe software side instantiates the DmaConfig proxy and the DmaIndication wrapper::\n\n    dma = new DmaConfigProxy(IfcNames_DmaConfig);\n    dmaIndication = new DmaIndication(dma, IfcNames_DmaIndication);\n\nCall `dma->alloc()` to allocate DMA memory. Each chunk of portal\nmemory is identified by a file descriptor. Portal memory may be shared\nwith other processes. Portal memory is reference counted according to\nthe number of file descriptors associated with it::\n\n    PortalAlloc *srcAlloc;\n    dma->alloc(alloc_sz, &srcAlloc);\n\nMemory map it to make it accessible to software::\n\n    srcBuffer = (unsigned int *)mmap(0, alloc_sz, PROT_READ|PROT_WRITE|PROT_EXEC, MAP_SHARED, srcAlloc->header.fd, 0);\n\nConnectal is currently using non-snooped interfaces, so the cache must be flushed and invalidated before hardware accesses portal memory::\n\n    dma->dCacheFlushInval(srcAlloc, srcBuffer);\n\nCall `dma->reference()` to get a pointer that may be passed to hardware::\n\n    unsigned int ref_srcAlloc = dma->reference(srcAlloc);\n\nThis also transfers the DMA-to-physical address translation information to the hardware via the `DmaConfig` interface::\n\n    device->startRead(ref_srcAlloc, numWords, burstLen, iterCnt);\n\nNotes\n-----\n\nstewart notes\n^^^^^^^^^^^^^\n\n.. caution::\nCurrently there are no valid bits and no protections against bursts crossing page boundaries\n\n.. caution::\n\nThere needs to be a way to synchronize Request actions and DMA reads,\nand to synchronize DMA writes with Indications, so that the writes\ncomplete to the coherence point before the indication is delivered to\nsoftware. One could imagine an absurdly buffered memory interface and\na rather direct path for I/O reads that could get out of order.\n\n"
  },
  {
    "path": "doc/library/source/design/portalstructure.rst",
    "content": "Portal Interface Structure\n**************************\n\nConnectal connects software and hardware via portals, where each portal is\nan interface that allows one side to invoke methods on the other side.\n\nWe generally call a portal from software to hardware to be a \"request\"\nand from hardware to software to be an \"indication\" interface::\n\n    Sequence Diagram to be drawn\n    {\n      SW; HW\n      SW -> HW [label = \"request\"];\n      SW <- HW [label = \"indication\"];\n    }\n\n\nA portal is conceptually a FIFO, where the arguments to a method are\npackaged as a message. CONNECTAL generates a \"proxy\" that marshalls the\narguments to the method into a message and a \"wrapper\" that unpacks\nthe arguments and invokes the method.\n\nCurrently, connectal Includes a library that implements portals from\nsoftware to hardware via memory mapped hardware FIFOs.\n\nPortal Device Drivers\n=====================\n\nConnectal uses a platform-specific driver to enable user-space applications\nto memory-map each portal used by the application and to enable the\napplication to wait for interrupts from the hardware.\n\nindexterm:pcieportal\nindexterm:zynqportal\n\n* pcieportal.ko\n* zynqportal.ko\n\nConnectal also uses a generic driver to enable the applications to allocate DRAM that will be shared with the hardware and to send the memory mapping of that memory to the hardware.\n\n* portalmem.ko\n\nPortal Memory Map\n=================\n\nConnectal is designed to support multiple tiles, each of which can\nhold an independent design. Currently, the number of tiles is one.\n\nConnectal currently supports up to 16 portals connected between software and hardware, for a total of 64KB of address space.\n\n=============  =========\n Base address  Function\n=============  =========\n       0x0000  Portal 0\n       0x1000  Portal 1\n       0x2000  Portal 2\n       0x3000  Portal 3\n       0x4000  Portal 4\n       0x5000  Portal 5\n       0x6000  Portal 6\n       0x7000  Portal 7\n       0x8000  Portal 8\n       0x9000  Portal 9\n       0xa000  Portal 10\n       0xb000  Portal 11\n       0xc000  Portal 12\n       0xd000  Portal 13\n       0xe000  Portal 14\n       0xf000  Portal 15\n=============  =========\n\nEach portal uses 16KB of address space, consisting of a control\nregister region and then per-method FIFOs, each of which takes 32\nbytes of address space.\n\n============== ==========\n Base address   Function\n============== ==========\n  0x000        Portal control regs\n  0x020        Method 0 FIFO\n  0x040        Method 1 FIFO\n ...           ...\n============== ==========\n\nFor request portals, the FIFOs are from software to hardware, and for\nindication portals the FIFOs are from hardware to software.\n\nPortal FIFOs\n------------\n\n============== ==========\n Base address   Function\n============== ==========\n   0x00        FIFO data (write request data, read indication data)\n   0x04        Request FIFO not full / Indication FIFO not empty\n============== ==========\n\nPortal Control Registers\n------------------------\n\n============= ============================= =========================================================\nBase address  Function                      Description\n============= ============================= =========================================================\n\t0x00  Interrupt status register     1 if this portal has any messages ready, 0 otherwise\n\t0x04  Interrupt enable register     Write 1 to enable interrupts, 0 to disable\n\t0x08  Number of tiles\n\t0x0C  Ready Channel number + 1      Reads as zero if no indication channel ready\n\t0x10  Interface Id\n\t0x14  Number of portals\n\t0x18  Cycle count LSW               Snapshots MSW when read\n\t0x1C  Cycle count MSW               MSW of cycle count when LSW was read\n============= ============================= =========================================================\n\n\n"
  },
  {
    "path": "doc/library/source/design/references.bib",
    "content": "% ----------------------------------------------------\n% Paper Specific References\n% ----------------------------------------------------    \n\n\n@inproceedings{DBLP:conf/fpga/WillenbergC13,\n  author    = {Ruediger Willenberg and\n               Paul Chow},\n  title     = {A remote memory access infrastructure for global address space programming\n               models in FPGAs},\n  booktitle = {The 2013 {ACM/SIGDA} International Symposium on Field Programmable\n               Gate Arrays, {FPGA} '13, Monterey, CA, USA, February 11-13, 2013},\n  pages     = {211--220},\n  year      = {2013},\n  url       = {http://doi.acm.org/10.1145/2435264.2435301},\n  doi       = {10.1145/2435264.2435301},\n  timestamp = {Wed, 27 Feb 2013 08:26:59 +0100},\n  biburl    = {http://dblp.uni-trier.de/rec/bib/conf/fpga/WillenbergC13},\n  bibsource = {dblp computer science bibliography, http://dblp.org}\n}\n\n@article{DBLP:journals/jpdc/MooreLK12,\n  author    = {Nicholas Moore and\n               Miriam Leeser and\n               Laurie A. Smith King},\n  title     = {VForce: An environment for portable applications on high performance\n               systems with accelerators},\n  journal   = {J. Parallel Distrib. Comput.},\n  volume    = {72},\n  number    = {9},\n  pages     = {1144--1156},\n  year      = {2012},\n  url       = {http://dx.doi.org/10.1016/j.jpdc.2011.07.014},\n  doi       = {10.1016/j.jpdc.2011.07.014},\n  timestamp = {Fri, 19 Oct 2012 13:56:48 +0200},\n  biburl    = {http://dblp.uni-trier.de/rec/bib/journals/jpdc/MooreLK12},\n  bibsource = {dblp computer science bibliography, http://dblp.org}\n}\n\n@article{DBLP:journals/trets/SaldanaPMNWCWSP10,\n  author    = {Manuel Salda{\\~{n}}a and\n               Arun Patel and\n               Christopher A. Madill and\n               Daniel Nunes and\n               Danyao Wang and\n               Paul Chow and\n               Ralph Wittig and\n               Henry Styles and\n               Andrew Putnam},\n  title     = {{MPI} as a Programming Model for High-Performance Reconfigurable Computers},\n  journal   = {{TRETS}},\n  volume    = {3},\n  number    = {4},\n  pages     = {22},\n  year      = {2010},\n  url       = {http://doi.acm.org/10.1145/1862648.1862652},\n  doi       = {10.1145/1862648.1862652},\n  timestamp = {Wed, 08 Dec 2010 08:58:19 +0100},\n  biburl    = {http://dblp.uni-trier.de/rec/bib/journals/trets/SaldanaPMNWCWSP10},\n  bibsource = {dblp computer science bibliography, http://dblp.org}\n}\n\n@inproceedings{DBLP:conf/fpga/FilguerasGJAMLNV14,\n  author    = {Antonio Filgueras and\n               Eduard Gil and\n               Daniel Jim{\\'{e}}nez{-}Gonz{\\'{a}}lez and\n               Carlos Alvarez and\n               Xavier Martorell and\n               Jan Langer and\n               Juanjo Noguera and\n               Kees A. Vissers},\n  title     = {OmpSs@Zynq all-programmable SoC ecosystem},\n  booktitle = {The 2014 {ACM/SIGDA} International Symposium on Field-Programmable\n               Gate Arrays, {FPGA} '14, Monterey, CA, {USA} - February 26 - 28, 2014},\n  pages     = {137--146},\n  year      = {2014},\n  url       = {http://doi.acm.org/10.1145/2554688.2554777},\n  doi       = {10.1145/2554688.2554777},\n  timestamp = {Mon, 24 Feb 2014 13:13:31 +0100},\n  biburl    = {http://dblp.uni-trier.de/rec/bib/conf/fpga/FilguerasGJAMLNV14},\n  bibsource = {dblp computer science bibliography, http://dblp.org}\n}\n\n\n@article{DBLP:journals/ijrc/JozwikHETT13,\n  author    = {Krzysztof Jozwik and\n               Shinya Honda and\n               Masato Edahiro and\n               Hiroyuki Tomiyama and\n               Hiroaki Takada},\n  title     = {Rainbow: An Operating System for Software-Hardware Multitasking on\n               Dynamically Partially Reconfigurable FPGAs},\n  journal   = {Int. J. Reconfig. Comp.},\n  volume    = {2013},\n  year      = {2013},\n  url       = {http://dx.doi.org/10.1155/2013/789134},\n  doi       = {10.1155/2013/789134},\n  timestamp = {Mon, 24 Mar 2014 18:09:23 +0100},\n  biburl    = {http://dblp.uni-trier.de/rec/bib/journals/ijrc/JozwikHETT13},\n  bibsource = {dblp computer science bibliography, http://dblp.org}\n}\n\n@inproceedings{DBLP:conf/fpl/FlemingYAE14,\n  author    = {Kermin Fleming and\n               Hsin{-}Jung Yang and\n               Michael Adler and\n               Joel S. Emer},\n  title     = {The {LEAP} {FPGA} operating system},\n  booktitle = {24th International Conference on Field Programmable Logic and Applications,\n               {FPL} 2014, Munich, Germany, 2-4 September, 2014},\n  pages     = {1--8},\n  year      = {2014},\n  url       = {http://dx.doi.org/10.1109/FPL.2014.6927488},\n  doi       = {10.1109/FPL.2014.6927488},\n  timestamp = {Thu, 30 Oct 2014 14:01:03 +0100},\n  biburl    = {http://dblp.uni-trier.de/rec/bib/conf/fpl/FlemingYAE14},\n  bibsource = {dblp computer science bibliography, http://dblp.org}\n}\n\n@inproceedings{DBLP:conf/fpl/PeckAASBA06,\n  author    = {Wesley Peck and\n               Erik K. Anderson and\n               Jason Agron and\n               Jim Stevens and\n               Fabrice Baijot and\n               David L. Andrews},\n  title     = {Hthreads: {A} Computational Model for Reconfigurable Devices},\n  booktitle = {Proceedings of the 2006 International Conference on Field Programmable\n               Logic and Applications (FPL), Madrid, Spain, August 28-30, 2006},\n  pages     = {1--4},\n  year      = {2006},\n  url       = {http://doi.ieeecomputersociety.org/10.1109/FPL.2006.311336},\n  doi       = {10.1109/FPL.2006.311336},\n  timestamp = {Mon, 11 Jul 2011 13:44:26 +0200},\n  biburl    = {http://dblp.uni-trier.de/rec/bib/conf/fpl/PeckAASBA06},\n  bibsource = {dblp computer science bibliography, http://dblp.org}\n}\n\n\n@MISC{Opencl,\n        AUTHOR = {{The Kronos Group}},\n        HOWPUBLISHED = {{https://www.khronos.org/registry/cl/}}},\n}\n\n@MISC{AlteraOpencl,\n        AUTHOR = {{Altera Inc.}},\n        HOWPUBLISHED = {{http://www.altera.com/products/software/opencl/opencl-index.html}}\n}\n\n@MISC{XilinxOpencl,\n        AUTHOR = {{Xilinx Inc.}},\n        HOWPUBLISHED = {{http://www.xilinx.com}}\n}\n\n\n@inbook{mpAlgo,\n author = {Alberto Apostolico, Zvi Galil},\n title = {Pattern Matching Algorithms},\n year = {1997},\n pages = {7-11},\n chapter = {1},\n note = {mp algorithm}\n}\n\n@INPROCEEDINGS{Chou92synthesisof,\n    author = {Pai Chou and Ross Ortega and Gaetano Borriello},\n    title = {Synthesis of the Hardware/Software Interface in Microcontroller-Based Systems},\n    booktitle = {In Proceedings of the International Conference on Computer Aided Design},\n    year = {1992},\n    pages = {488--495}\n}\n\n@INPROCEEDINGS{Chou95thechinook,\n    author = {Pai H. Chou and Ross B. Ortega and Gaetano Borriello},\n    title = {The Chinook Hardware/Software Co-Synthesis System},\n    booktitle = {In International Symposium on System Synthesis},\n    year = {1995},\n    pages = {22--27}\n}\n\n\n@inproceedings{DBLP:conf/dac/LiaoTG97,\n  author    = {Stan Y. Liao and\n               Steven W. K. Tjiang and\n               Rajesh K. Gupta},\n  title     = {An Efficient Implementation of Reactivity for Modeling Hardware\n               in the Scenic Design Environment},\n  booktitle = {DAC},\n  year      = {1997},\n  pages     = {70-75},\n  ee        = {http://doi.acm.org/10.1145/266021.266037},\n  bibsource = {DBLP, http://dblp.uni-trier.de}\n}\n\n\n\n\n@INPROCEEDINGS{Abdulla04designingsafe,\n    author = {Parosh Aziz Abdulla and Johann Deneux},\n    title = {Designing Safe, Reliable Systems using Scade},\n    booktitle = {In Proc. ISoLA 2004},\n    year = {2004}\n}\n\n@inproceedings{Colaco,\n author = {Cola\\c{c}o, Jean-Louis and Hamon, Gr\\'{e}goire and Pouzet, Marc},\n title = {Mixing signals and modes in synchronous data-flow systems},\n booktitle = {Proceedings of the 6th ACM \\& IEEE International conference on Embedded software},\n series = {EMSOFT '06},\n year = {2006},\n isbn = {1-59593-542-8},\n location = {Seoul, Korea},\n pages = {73--82},\n numpages = {10},\n acmid = {1176899},\n publisher = {ACM},\n address = {New York, NY, USA},\n keywords = {compilation, languages, mode automata, synchronous},\n} \n\n\n\n@ARTICLE{Lustre1991,\nauthor={Halbwachs, N. and Caspi, P. and Raymond, P. and Pilaud, D.},\njournal={Proceedings of the IEEE}, title={The synchronous data flow programming language LUSTRE},\nyear={1991},\nmonth={sep},\nvolume={79},\nnumber={9},\npages={1305 -1320},\nkeywords={LUSTRE;description tools;program verification methodology;reactive systems;sequential program;synchronous data flow programming language;temporal logics;parallel languages;program verification;temporal logic;},\ndoi={10.1109/5.97300},\nISSN={0018-9219},}\n\n\n@inproceedings{MainlandM10,\n  author = {Geoffrey Mainland and Greg Morrisett},\n  title = {Nikola: Embedding Compiled {GPU} Functions in {Haskell}},\n  booktitle = {Proceedings of the 2010 ACM SIGPLAN Symposium on Haskell (Haskell'10)},\n  year = {2010},\n  month = sep,\n  location = {Baltimore, MD},\n  publisher = {ACM},\n  address = {New York, NY, USA},\n  pdf = {http://www.eecs.harvard.edu/~mainland/publications/mainland10nikola.pdf}\n  }\n}\n\n@inproceedings{MEMOCODE2010,\ntitle={A Design Flow Based on Modular Refinement},\nauthor = {Nirav Dave and  \n          Man Cheuk Ng and\n          Michael Pellauer and\n          Arvind},\nbooktitle = {Formal Methods and Models for Codesign (MEMOCODE 2010)},\nlocation = {Grenoble, France. June 2010 }\n}\n\n@inproceedings{DBLP:conf/emsoft/TalpinBGG06,\n  author    = {Jean-Pierre Talpin and\n               Christian Brunette and\n               Thierry Gautier and\n               Abdoulaye Gamati{\\'e}},\n  title     = {Polychronous mode automata},\n  booktitle = {EMSOFT},\n  year      = {2006},\n  pages     = {83-92},\n  ee        = {http://doi.acm.org/10.1145/1176887.1176900},\n  bibsource = {DBLP, http://dblp.uni-trier.de}\n}\n\n\n@ARTICLE{Lynch89IOAutomata,\n    author = {Nancy A. Lynch and Mark R. Tuttle},\n    title = {An introduction to input/output automata},\n    journal = {CWI Quarterly},\n    year = {1989},\n    volume = {2},\n    pages = {219--246}\n}\n\n@inproceedings{meredith-katelman-meseguer-rosu-2010-memocode,\nauthor={Patrick O'Neil Meredith and Michael Katelman and Jos{\\'e} Meseguer and Grigore Ro\\c{s}u},\ntitle={A Formal Executable Semantics of {V}erilog},\nbooktitle={Eighth ACM/IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE'10)},\nyear={2010},\npublisher={IEEE},\npages={179-188}\n}\n\n@article{DBLP:journals/dc/ShavitT97,\n  author    = {Nir Shavit and\n               Dan Touitou},\n  title     = {Software Transactional Memory},\n  journal   = {Distributed Computing},\n  volume    = {10},\n  number    = {2},\n  year      = {1997},\n  pages     = {99-116},\n  bibsource = {DBLP, http://dblp.uni-trier.de}\n}\n\n@inproceedings{DBLP:conf/podc/SchererS05,\n  author    = {William N. Scherer III and\n               Michael L. Scott},\n  title     = {Advanced contention management for dynamic software transactional\n               memory},\n  booktitle = {PODC},\n  year      = {2005},\n  ee        = {http://doi.acm.org/10.1145/1073814.1073861},\n  bibsource = {DBLP, http://dblp.uni-trier.de}\n}\n%  pages     = {240-248},\n\n\n@inproceedings{DBLP:conf/ershov/DennisFL72,\n  author    = {Jack B. Dennis and\n               John B. Fosseen and\n               John P. Linderman},\n  title     = {Data flow schemas},\n  booktitle = {International Sympoisum on Theoretical Programming},\n  year      = {1972},\n  ee        = {http://dx.doi.org/10.1007/3-540-06720-5_15},\n  bibsource = {DBLP, http://dblp.uni-trier.de}\n}\n%  pages     = {187-216},\n\n\n@ARTICLE{ArvindNikhil:TaggedToken,\nauthor={Arvind and Nikhil, R.S.},\njournal={Computers, IEEE Transactions on}, \ntitle={{Executing a program on the MIT Tagged-Token Dataflow Architecture }},\nyear={1990},\nmonth=mar,\nvolume={39},\nnumber={3},\npages={300 -318},\nkeywords={Id;MIT tagged-token dataflow architecture;compilation;determinacy;dynamic dataflow graphs;fine-grained parallelism;general-purpose high-performance parallel computing;high-level language;multiprocessor architecture;operational semantics;parallel machine language;high level languages;parallel architectures;parallel programming;program compilers;},\ndoi={10.1109/12.48862},\nISSN={0018-9340},}\n\n\n@inproceedings{DBLP:conf/isca/Arvind81,\n  author    = {Arvind},\n  title     = {Data Flow Languages and Architecture},\n  booktitle = {ISCA},\n  year      = {1981},\n  pages     = {1},\n  bibsource = {DBLP, http://dblp.uni-trier.de}\n}\n\n@article{DBLP:journals/tc/LeeM87,\n  author    = {Edward A. Lee and\n               David G. Messerschmitt},\n  title     = {Static Scheduling of Synchronous Data Flow Programs for\n               Digital Signal Processing},\n  journal   = {IEEE Trans. Computers},\n  volume    = {36},\n  number    = {1},\n  year      = {1987},\n  pages     = {24-35},\n  bibsource = {DBLP, http://dblp.uni-trier.de}\n}\n\n@ARTICLE{ESLIEEE/Agarwal/ManCheuk/Arvind, \n  author={Agarwal, A. and Man Cheuk Ng and Arvind}, \n  journal={Embedded Systems Letters, IEEE}, title={A Comparative Evaluation of High-Level Hardware Synthesis Using Reed-Solomon Decoder}, \n  year={2010}, \n  month=sept. , \n  volume={2}, \n  number={3}, \n  pages={72 -76}, \n  keywords={C code;HDL;Reed-Solomon decoder;high-level hardware synthesis;Reed-Solomon codes;decoding;hardware description languages;high level synthesis;}, \n  doi={10.1109/LES.2010.2055231}, \n  ISSN={1943-0663},}\n\n@inproceedings{DBLP:conf/cc/ThiesKA02,\n  author    = {William Thies and\n               Michal Karczmarek and\n               Saman P. Amarasinghe},\n  title     = {StreamIt: A Language for Streaming Applications},\n  booktitle = {CC},\n  year      = {2002},\n  ee        = {http://link.springer.de/link/service/series/0558/bibs/2304/23040179.htm},\n  crossref  = {DBLP:conf/cc/2002},\n  bibsource = {DBLP, http://dblp.uni-trier.de}\n}\n%  pages     = {179-196},\n\n\n@proceedings{DBLP:conf/cc/2002,\n  editor    = {R. Nigel Horspool},\n  title     = {Compiler Construction, 11th International Conference, CC\n               2002, Held as Part of the Joint European Conferences on\n               Theory and Practice of Software, ETAPS 2002, Grenoble, France,\n               April 8-12, 2002, Proceedings},\n  booktitle = {CC},\n  publisher = {Springer},\n  series    = {Lecture Notes in Computer Science},\n  volume    = {2304},\n  year      = {2002},\n  isbn      = {3-540-43369-4},\n  bibsource = {DBLP, http://dblp.uni-trier.de}\n}\n\n\n@inproceedings{DBLP:conf/ifip/Kahn74,\n  author    = {Gilles Kahn},\n  title     = {The Semantics of Simple Language for Parallel Programming},\n  booktitle = {IFIP Congress},\n  year      = {1974},\n  pages     = {471-475},\n  bibsource = {DBLP, http://dblp.uni-trier.de}\n}\n\n@MISC{Verilator:www,\n        AUTHOR = {{W. Snyder and P. Wasson, and D. Galbi}},\n        TITLE = {{Verilator}},\n        YEAR   = {{2007}},\n        HOWPUBLISHED = {{\\texttt{http://www.veripool.com/verilator.html}}},\n}\n\n@MISC{AutoESL:www,\n        AUTHOR = {{AutoESL Desisgn Technologies, Inc.}},\n        HOWPUBLISHED = {{\\texttt{http://www.autoesl.com}}},\n}\n\n\n@MISC{MDC09:Spec,\n        AUTHOR = {{MEMOCode Design Contest}},\n        TITLE  = {{Cartesian-to-Polar Interpolation}},\n        HOWPUBLISHED = {\\texttt{{http://www.ece.cmu.edu/~jhoe/distribution/}}\n                        \\texttt{mc09contest/contest09.pdf}}\n}\n\n\n@inproceedings{Strassen:MatrixAlgo,\n author = {Volker Strassen},\n title = {Gaussian Elimination is Not Optimal},\n booktitle = {Numerische Mathematik 13},\n year = {1969},\n pages = {354--356}\n }\n\n\n@MANUAL{IBM:PLBSpec,\n        TITLE = \"The CoreConnect (TM) Bus Architecture\",\n        ORGANIZATION = \"IBM,~Inc.\",\n        YEAR = {1999}\n}\n\n@MISC{Memocode:DesignContest,\n        AUTHOR = {{Forrest Brewer and James C. Hoe}},\n        TITLE = {{The First MEMOCODE HW/SW Co-design Contest}},\n        HOWPUBLISHED = {{\\texttt{https://memocode07.ece.cmu.edu/contest.html}}},\n        MONTH = {March},\n        YEAR = {2007}\n}\n\n@ARTICLE{Volder:CORDIC,\n        AUTHOR = \"Jack E. Volder\",\n        TITLE = {{The CORDIC Trigonometric Computing Technique}},\n        JOURNAL = {{IRE Transactions on Electronic Computers}},\n        VOLUME = {8},\n        NUMBER = {3},\n        PAGES = {330--334},\n        MONTH = {September},\n        YEAR = {1959}\n}\n\n\n@article{Ptolemy,\n  author    = {Joseph T. Buck and\n               Soonhoi Ha and\n               Edward A. Lee and\n               David G. Messerschmitt},\n  title     = {Ptolemy: A Framework for Simulating and Prototyping Heterogenous\n               Systems},\n  journal   = {Int. Journal in Computer Simulation},\n  volume    = {4},\n  number    = {2},\n  year      = {1994},\n  pages     = {0-},\n  bibsource = {DBLP, http://dblp.uni-trier.de}\n}\n\n@MISC{PtolemyII,\n        TITLE  = {{Ptolomy II}},\n        AUTHOR = {{Department of EECS, University of California, Berkeley}},\n        HOWPUBLISHED = {{http://ptolemy.eecs.berkeley.edu/ptolemyII/}}}\n}\n\n@MISC{CatC:www,\n        TITLE = {{Catapult-C}},\n        AUTHOR = {{Mentor Graphics}},\n        HOWPUBLISHED = {{{ http://www.mentor.com/products/esl/}}}\n}\n\n@MANUAL{CatC:Manual,\n        TITLE = {{Catapult-C Manual and C/C++ style guide}},\n        ORGANIZATION = \"Mentor Graphics\",\n        YEAR = {2004}\n}\n\n@inproceedings{REL:Lime,\n author = {Huang, Shan Shan and Hormati, Amir and Bacon, David F. and Rabbah, Rodric},\n title = {Liquid Metal: Object-Oriented Programming Across the Hardware/Software Boundary},\n booktitle = {ECOOP '08: Proceedings of the 22nd European conference on Object-Oriented Programming},\n year = {2008},\n isbn = {978-3-540-70591-8},\n location = {Paphos, Cypress},\n doi = {http://dx.doi.org/10.1007/978-3-540-70592-5_5},\n address = {Berlin, Heidelberg},\n }\n\n@article{Metropolis, \nauthor = {Felice Balarin and Yosinori Watanabe and Harry Hsieh and Luciano Lavagno and Claudio Passerone and Alberto Sangiovanni-Vincentelli},\ntitle = {Metropolis: An Integrated Electronic System Design Environment},\njournal ={Computer},\nvolume = {36},\nissn = {0018-9162},\nyear = {2003},\npages = {45-52},\ndoi = {http://doi.ieeecomputersociety.org/10.1109/MC.2003.1193228},\npublisher = {IEEE Computer Society},\naddress = {Los Alamitos, CA, USA},\n}\n\n\n@inproceedings{REL:Rapide,\n  author    = {David C. Luckham},\n  title     = {Rapide: A Language and Toolset for Causal Event Modeling\n               of Distributed System Architectures},\n  booktitle = {WWCA},\n  year      = {1998},\n  bibsource = {DBLP, http://dblp.uni-trier.de}\n}\n%  pages     = {88-96},\n\n\n@article{REL:Shim,\n  author    = {Stephen A. Edwards and\n               Olivier Tardieu},\n  title     = {SHIM: a deterministic model for heterogeneous embedded systems},\n  journal   = {IEEE Trans. VLSI Syst.},\n  volume    = {14},\n  number    = {8},\n  year      = {2006},\n  pages     = {854-867},\n  ee        = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2006.878473},\n  bibsource = {DBLP, http://dblp.uni-trier.de}\n}\n\n\n@inproceedings{Magellan,\n  author    = {Karam S. Chatha and\n               Ranga Vemuri},\n  title     = {MAGELLAN: multiway hardware-software partitioning and scheduling\n               for latency minimization of hierarchical control-dataflow\n               task graphs},\n  booktitle = {CODES},\n  year      = {2001},\n  pages     = {42-47},\n  ee        = {http://doi.acm.org/10.1145/371636.371671},\n  bibsource = {DBLP, http://dblp.uni-trier.de}\n}\n\n@MISC{Eles97systemlevel,\n    author = {Petru Eles and Zebo Peng and Krzysztof Kuchcinski and Alexa Doboli},\n    title = {System Level Hardware/Software Partitioning Based on Simulated Annealing and Tabu Search},\n    year = {1997}\n}\n\n@article{Arato:2005:AAH:1044111.1044119,\n author = {Arat\\'{o}, P\\'{e}ter and Mann, Zolt\\'{a}n \\'{A}d\\'{a}m and Orb\\'{a}n, Andr\\'{a}s},\n title = {Algorithmic aspects of hardware/software partitioning},\n journal = {ACM Trans. Des. Autom. Electron. Syst.},\n volume = {10},\n issue = {1},\n month = {January},\n year = {2005},\n issn = {1084-4309},\n pages = {136--156},\n numpages = {21},\n url = {http://doi.acm.org/10.1145/1044111.1044119},\n doi = {http://doi.acm.org/10.1145/1044111.1044119},\n acmid = {1044119},\n publisher = {ACM},\n address = {New York, NY, USA},\n keywords = {Hardware/software partitioning, graph algorithms, graph bipartitioning, hardware/software codesign, optimization},\n}\n\n@article{HWCo_Ernst,\n author = {Ernst, Rolf and Henkel, Jorg and Benner, Thomas},\n title = {Hardware-Software Cosynthesis for Microcontrollers},\n journal = {IEEE Des. Test},\n volume = {10},\n number = {4},\n year = {1993},\n issn = {0740-7475},\n pages = {64--75},\n doi = {http://dx.doi.org/10.1109/54.245964},\n publisher = {IEEE Computer Society Press},\n address = {Los Alamitos, CA, USA},\n }\n\n@INPROCEEDINGS{Edwards:SynthesisFromEsterel,\n        AUTHOR = \"Stephen Edwards\",\n        TITLE = {{High-Level Synthesis from the Synchronous Language Esterel}},\n        BOOKTITLE = {{Proceedings of IWLS'02}},\n        YEAR = {2002},\n        ADDRESS = {New Orleans,~LA}\n}\n\n@inproceedings{DBLP:conf/concur/BerryC84,\n  author    = {G{\\'e}rard Berry and\n               Laurent Cosserat},\n  title     = {{The ESTEREL Synchronous Programming Language and its Mathematical\n               Semantics}},\n  booktitle = {Seminar on Concurrency},\n  year      = {1984},\n  pages     = {389-448},\n  ee        = {http://dx.doi.org/10.1007/3-540-15670-4_19},\n  bibsource = {DBLP, http://dblp.uni-trier.de}\n}\n\n\n@INCOLLECTION{Berry:EsterelOnHW,\n        AUTHOR = \"G\\'erard Berry\",\n        TITLE = {{Esterel on hardware}},\n        BOOKTITLE = {{Mechanized Reasoning and Hardware Design}},\n        PAGES = {87--104},\n        PUBLISHER = {Prentice Hall},\n        YEAR = {1992},\n        ADDRESS = {Hertfordshire,~UK}\n}\n\n@MISC{Synfora:www,\n        TITLE = {{PICO Platform}},\n        AUTHOR = {{Synfora}},\n        HOWPUBLISHED = {{\\texttt{http://www.synfora.com/}}}\n}\n\n@MISC{coware:www,\n        TITLE = {{ESL Coware 2.0}},\n        HOWPUBLISHED = {{\\texttt{http://www.coware.com/}}}\n}\n\n@MISC{carbon:www,\n        TITLE = {{Carbon Design Systems Inc}},\n        HOWPUBLISHED = {{\\texttt{http://carbondesignsystems.com}}}\n}\n\n@MISC{UIO:Howto,\n\tTITLE = {{The Userspace I/O HOWTO}},\n\tHOWPUBLISHED = {{https://www.kernel.org/doc/htmldocs/uio-howto/index.html}}}\n\n@techreport{Khalidi:1995:EZI:974947,\n author = {Khalidi, Yousef A. and Thadani, Moti N.},\n title = {{An Efficient Zero-Copy I/O Framework for UNIX}},\n year = {1995},\n publisher = {Sun Microsystems, Inc.},\n address = {Mountain View, CA, USA},\n}\n\n@inproceedings{Agrawal:2008:DTS:1404014.1404019,\n author = {Agrawal, Nitin and Prabhakaran, Vijayan and Wobber, Ted and Davis, John D. and Manasse, Mark and Panigrahy, Rina},\n title = {Design Tradeoffs for SSD Performance},\n booktitle = {USENIX 2008 Annual Technical Conference on Annual Technical Conference},\n series = {ATC'08},\n year = {2008},\n location = {Boston, Massachusetts},\n pages = {57--70},\n numpages = {14},\n url = {http://dl.acm.org/citation.cfm?id=1404014.1404019},\n acmid = {1404019},\n publisher = {USENIX Association},\n address = {Berkeley, CA, USA},\n}\n\n@MISC{dmabuf,\n author = {Semwal, Sumit},\n title = {{DMA Buffer Sharing API Guide}},\n howpublished = {https://www.kernel.org/doc/Documentation/dma-buf-sharing.txt}}\n\n@inproceedings{King:2012:AGH:2150976.2151011,\n author = {King, Myron and Dave, Nirav and Arvind},\n title = {Automatic Generation of Hardware/Software Interfaces},\n booktitle = {Proceedings of the Seventeenth International Conference on Architectural Support for Programming Languages and Operating Systems},\n series = {ASPLOS XVII},\n year = {2012},\n isbn = {978-1-4503-0759-8},\n location = {London, England, UK},\n pages = {325--336},\n numpages = {12},\n url = {http://doi.acm.org/10.1145/2150976.2151011},\n doi = {10.1145/2150976.2151011},\n acmid = {2151011},\n publisher = {ACM},\n address = {New York, NY, USA},\n keywords = {hardware/software codesign},\n}"
  },
  {
    "path": "doc/library/source/design/related-work.rst",
    "content": ".. _Sec:RelWork\n\nRelated Work\n============\n\nA number of research projects, such as Lime~\\cite{REL:Lime},\nBCL~\\cite{King:2012:AGH:2150976.2151011},\nHThreads~\\cite{DBLP:conf/fpl/PeckAASBA06}, and\nCatapaultC~\\cite{CatC:www} (to name just a few) bridge the\nsoftware/hardware development gap by providing a single language for\ndeveloping both the software and hardware components of the design.\nIn addition, Altera and Xilinx have both implemented\nOpenCL~\\cite{Opencl} on FPGAs~\\cite{AlteraOpencl,XilinxOpencl} in an\nattempt to attract GPU programmers.\n\nThe computation model of software differs significantly from that of\nhardware, and so far none of the unified language approaches deliver\nthe same performance as languages designed specifically for hardware\nor software. Connectal is intended to be used for the design of\nperformance-critical systems.  In this context we think that designers\nprefer a mix of languages specifically designed for their respective\nimplementation contexts.\n\nInfrastructures such as LEAP~\\cite{DBLP:conf/fpl/FlemingYAE14},\nRainbow~\\cite{DBLP:journals/ijrc/JozwikHETT13}, and\nOmpSs~\\cite{DBLP:conf/fpga/FilguerasGJAMLNV14} (to name just a\nfew) use resource abstraction to enable FPGA development.  We found\nthat in their intended context, these tools were easy to use but that\nperformance tuning in applications not foreseen by the infrastructure\ndevelopers was problematic.\n\nSome projects such as\nTMD-MPI~\\cite{DBLP:journals/trets/SaldanaPMNWCWSP10},\nVFORCE/ \\\\VSIPL++~\\cite{DBLP:journals/jpdc/MooreLK12}, and\nGASNet/GAScore~\\cite{DBLP:conf/fpga/WillenbergC13} target only the\nhardware software interface.  These tools provide message passing\ncapabilities, but rely on purely operational semantics to describe the\nHW/SW interface.  Apart from the implementation details, Connectal\ndistinguishes itself by using an IDL to enforce denotational interface\nsemantics.\n\nUIO~\\cite{UIO:Howto} is a user-space device driver framework for\nLinux. It is very similar to the Connectal's portal device driver, but\nit does not provide a solution to multiple device nodes per hardware\ndevice. The portal driver provides this so that different interfaces\nof a design may be accessed independently, providing process boundary\nprotection, thread safety, and the ability for user processes and the\nkernel both to access the hardware device.\n"
  },
  {
    "path": "doc/library/source/design/string-search.rst",
    "content": ".. _Sec-StrStr:\n\nAccelerating String Search\n==========================\n\nThe structure of a hardware/software (HW/SW) system can evolve quite\ndramatically to reflect changing requirements, or during design\nexploration.  In this section, we consider several different\nimplementations of a simple string search\napplication~\\cite{mpAlgo}. Each variation represents a step in the\niterative refinement process, intended to enhance performance or\nenable a different software execution environment.\n\n    \\begin{figure}[!h]\n      \\centering\n     \\includegraphics[width=0.43\\textwidth]{platform.pdf}\n      \\caption{\\label{Fig:Platform0}Target platform for string search\n\tapplication}\n    \\end{figure}\n\nFigure~\\ref{Fig:Platform0} shows the target platform for our example.\nThe pertinent components of the host system are the multi-core CPU,\nsystem memory, and PCI Express (PCIe) bus.  The software components of\nour application will be run on the CPU in a Linux environment.\nConnected to the host is a PCIe expansion card containing (among other\nthings) a high-performance FPGA chip and a large array of flash\nmemory.  The FPGA board was designed as a platform to accelerate ``big\ndata'' analytics by moving more processing power closer to the storage\ndevice.\n\n.. _Sec:StrStrInitial:\n\nInitial Implementation\n----------------------\n\n    \\begin{figure}[!h]\n      \\centering\n     \\includegraphics[width=0.43\\textwidth]{data_accel_logical0.pdf}\n      \\caption{\\label{Fig:StringSearch0}Logical components of the string\n\tsearch system}\n    \\end{figure}\n\nThe design process really begins with a pure software implementation\nof the algorithm, but the first attempt we consider is the initial\ninclusion of HW acceleration shown in Figure~\\ref{Fig:StringSearch0}.\nThe search functionality is executed by software running in user-space\nwhich communicates with the hardware accelerator through a device\ndriver running in the Linux kernel.  The hardware accelerator,\nimplemented in the FPGA fabric, executes searches over data stored in\nthe flash array as directed by the software.\n\nThe FPGA has direct access to the massive flash memory array, so if we\nimplement the search kernel in hardware, we can avoid bringing data\ninto the CPU cache (an important consideration if we intend to run\nother programs simultaneously).  By exploiting the high parallelism of\nthe execution fabric as well as application aware caching of data, an\nFPGA implementation can outperform the same search executed on the\nCPU.\n\nMultithreading the Software\n---------------------------\n\nThe efficient use of flash memory requires a relatively sophisticated\nmanagement strategy.  Our first refinement is based on the observation\nthat there are four distinct tasks which the application software\nexecutes (mostly) independently:\n\n\n* Send search command to the hardware.\n* Receive search results from the hardware.\n* Send commands to the hardware to manage the flash arrays\n* Receive responses from the flash management hardware\n\nTo exploit the task-level parallelism in our application, we can\nassign one thread to each of the four enumerated tasks.  To further\nimprove efficiency, the two threads receiving data from the hardware\nput themselves to sleep by calling \\textbf{poll} and are woken up only\nwhen a message has been received.  \n\n    \\begin{figure}[!h]\n      \\centering\n     \\includegraphics[width=0.43\\textwidth]{data_accel_logical1.pdf}\n      \\caption{\\label{Fig:StringSearch1}Using a mutex to coordinate\n      user-level access to hardware accelerator}\n    \\end{figure}\n\nWith the introduction of multithreading, we will need a\nsynchronization mechanism to enforce coherent access to the hardware\nresources. Because the tasks which need coordinating are all being\nexecuted as user-space threads, the access control must be implemented\nin software as well.  As shown in Figure~\\ref{Fig:StringSearch1}, a\nmutex is used to coordinate access to the shared hardware resource\nbetween user-level processes.\n\n.. _Sec:StrStrRefiningInterfaces:\n\nRefining the Interfaces\n-----------------------\n\n    \\begin{figure}[!h]\n      \\centering\n      \\includegraphics[width=0.43\\textwidth]{data_accel_logical2.pdf}\n      \\caption{\\label{Fig:StringSearch2}Movement of functionality from\n\tuser to kernel space.  Software-based coordination between kernel\n\tand user processes are prohibitively expensive.}\n    \\end{figure}\n\nFigure~\\ref{Fig:StringSearch2} shows a further refinement to our\nsystem in which we have reimplemented the Flash Management\nfunctionality as a block-device driver.  Instead of directly operating\non physical addresses, the string search now takes a file descriptor\nas input and uses a Linux system-call to retrieve the file block addresses\nthrough the file system. This refinement permits other developers to\nwrite applications which can take advantage of the accelerator without\nany knowledge of the internal details of the underlying storage\ndevice.  It also enables support for different file systems as we now\nuse a POSIX interface to generate physical block lists for the the\nstorage device hardware.  The problem with this refinement is that we\nno longer have an efficient SW mechanism to synchronize the block\ndevice driver running in kernel space with the application running in\nuser space.\n\n    \\begin{figure}[htb]\n      \\centering\n      \\includegraphics[width=0.43\\textwidth]{data_accel_logical3.pdf}\n      \\caption{\\label{Fig:StringSearch3}Correct interface design\n\tremoves the need for coordination between user and kernel\n\tthreads.}\n    \\end{figure}\n \nTo solve to this problem (shown in Figure~\\ref{Fig:StringSearch3}), we\ncan remove the need for explicit SW coordination altogether by giving\neach thread uncontested access to its own dedicated HW resources\nmapped into disjoint address regions. (There will of course be\nimplicit synchronization through the file system.)\n\n.. _Sec:StrStrDma:\n\nShared Access to Host Memory\n----------------------------\n\nIn the previous implementations, all communication between hardware\nand software takes place through memory mapped register IO.  Suppose that instead of\nsearching for single strings, we want to search for large numbers of\n(potentially lengthy) strings stored in the flash array.  Attempting\nto transfer these strings to the hardware accelerator using programmed\nregister transfers introduces a performance bottleneck.  In our final\nrefinement, the program will allocate memory on the host system,\npopulate it with the search strings, and pass a reference to this\nmemory to the hardware accelerator which can then read the search\nstrings directly from the host memory.\n\n    \\begin{figure}[htb]\n      \\centering\n      \\includegraphics[width=0.43\\textwidth]{data_accel_logical4.pdf}\n      \\caption{\\label{Fig:StringSearch4}Connectal support for DMA.}\n    \\end{figure}\n\nEfficient high-bandwidth communication in this style requires the\nability to share allocated memory regions between hardware and\nsoftware processes without copying.  Normally, a programmer would\nsimply call application space \\textbf{malloc}, but this does not\nprovide a buffer that can be shared with hardware or other software\nprocesses.  As shown in Figure~\\ref{Fig:StringSearch4}, a\nspecial-purpose memory allocator has been implemented in Linux, using\ndmabuf\\cite{dmabuf} to provide reference counted sharing of memory\nbuffers across user processes and hardware.\n\nTo conclude, we consider how the HW/SW interface changed to\naccommodate each step in the refinement process: The hardware\ninterface required by the design in Figure~\\ref{Fig:StringSearch0} is\nrelatively simple.  Command/response queues in the hardware\naccelerator are exposed using a register interface with accompanying\n*empty*/*full* signals.  To support the use of *poll* by\nthe refinement in Figure~\\ref{Fig:StringSearch1}, interrupt signals\nmust be added to the hardware interface and connected to the Linux\nkernel.  Partitioning the address space as required by the refinement\nin Figure~\\ref{Fig:StringSearch3} necessitates a consistent remapping\nof registers in both hardware and software.\n\n\n"
  },
  {
    "path": "doc/library/source/design/toolchain.rst",
    "content": ".. _Sec:Toolchain:\n\nWorkflow using Connectal\n========================\n\nIn this section, we give an overview of the Connectal workflow and\ntoolchain.  The complete toolchain, libraries, and many running\nexamples may be obtained at \\textit{www.connectal.org} or by emailing\n\\textit{connectal@googlegroups.com}.\n\nTop level structure of Connectal applications\n---------------------------------------------\n\nThe simplest Connectal application consists of 4 files:\n\nMakefile\n^^^^^^^^\n\nThe top-level Makefile defines parameters for the entire application\nbuild process.  In its simplest form, it specifies which Bluespec\ninterfaces to use as portals, the hardware and software source files,\nand the libraries to use for the hardware and software compilation.\n\nApplication Hardware\n^^^^^^^^^^^^^^^^^^^^\n\nConnectal applications typically have at least one BSV file containing\ndeclarations of the interfaces being exposed as portals, along with\nthe implementation of the application hardware itself.\n\nTop.bsv\n^^^^^^^\n\nIn this file, the developer instantiates the application hardware\nmodules, connecting them to the generated wrappers and proxies for the\nportals exported to software.  To connect to the host processor bus, a\nparameterized standard interface is used, making it easy to synthesize\nthe application for different CPUs or for simulation.  If CPU specific\ninterface signals are needed by the design (for example, extra clocks\nthat are generated by the PCIe core), then an optional CPU-specific\ninterface can also be used.\n\nIf the design uses multiple clock domains or additional pins on the\nFPGA, those connections are also made here by exporting a 'Pins'\ninterface.  The Bluespec compiler generates a Verilog module from the\ntop level BSV module, in which the methods of exposed interfaces are\nimplemented as Verilog ports. Those ports are associated to physical\npins on the FPGA using a physical constraints file.\n\nApplication CPP\n^^^^^^^^^^^^^^^\n\nThe software portion of a Connectal application generally consists of\nat least one C++ file, which instantiates the generated software\nportal wrapper and proxies.  The application software is also\nresponsible for implementing main.\n\nDevelopment cycle\n------------------\n\nAfter creating or editing the source code for the application, the\ndevelopment cycle consists of four steps: generating makefiles,\ncompiling the interface, building the application, and running the\napplication.\n\nGenerating Makefiles\n^^^^^^^^^^^^^^^^^^^^\n\nGiven the parameters specified in the application Makefile and a\nplatform target specified at the command line, Connectal generates a\ntarget-specific Makefile to control the build process. This Makefile\ncontains the complete dependency information for the generation of\nwrappers/proxies, the use of these wrappers/proxies in compiling both\nthe software and hardware, and the collection of build artifacts into\na package that can be either run locally or over a network to a remote\n'device under test' machine.\n\nCompiling the Interface\n^^^^^^^^^^^^^^^^^^^^^^^\n\nThe Connectal interface compiler generates the C++ and BSV files to\nimplement wrappers and proxies for all interfaces specified in the\napplication Makefile.  Human readable \\textbf{JSON} is used as an\nintermediate representation of portal interfaces, exposing a useful\ndebugging window as well as a path for future support of\nadditional languages and IDLs.\n\nBuilding the Application\n^^^^^^^^^^^^^^^^^^^^^^^^\n\nA target in the generated Makefile invokes GCC to compiler the\nsoftware components of the application.  The Bluespec compiler (bsc)\nis then invoked to compiler the hardware components to Verilog.  A\nparameterized Tcl scripts is used to drive Vivado to build the Xilinx\nFPGA configuration bitstream for the design.\n\nA Connectal utility called `fpgamake`_ supports\nspecification of which Bluespec and Verilog modules should be compiled to\nseparate netlists and to enable separate place and route of those\nnetlists given a floor plan. Separate synthesis and floor planning in\nthis manner can reduce build times, and to make it easier to meet\ntiming constraints.\n\nAnother Connectal utility called `buildcache`_ \nspeeds recompilation by caching previous compilation results\nand detecting cases where input files have not changed. \nAlthough similar to the better-known utility \\textit{ccache}, this\nprogram has no specific knowledge of the tools being executed,\nallowing it to be integrated into any workflow and any tool set.\nThis utility\nuses the system call \\textbf{strace} to track which files are read and\nwritten by each build step, computing an 'input signature' of the MD5\nchecksum for each of these files.  When the input signature matches,\nthe output files are just refreshed from the cache, avoiding the long\nsynthesis times for the unchanged portions of the project.\n\nRunning the Application\n^^^^^^^^^^^^^^^^^^^^^^^\n\nAs part of our goal to have a fully scripted design flow, the\ngenerated Makefile includes a \\texttt{run} target that will program\nthe FPGA and launch the specified application or test bench.  In order\nto support shared target hardware resources, the developer can direct the run\nto a particular machines, which can be accessed over the network.  For\nUbuntu target machines, ssh is used to copy/run the application.  For\nAndroid target machines, 'adb' is used.\n\n\n\nContinuous Integration and Debug Support\n----------------------------------------\n\nConnectal provides a fully scripted flow in order to make it easy to\nautomate the building and running of applications for continuous\nintegration. Our development team builds and runs large collections of\ntests whenever the source code repository is updated.\n\nConnectal also provides trace ring buffers in hardware and analysis software\nto trace and display the last transactions on the PCIe or AXI memory\nbus. This trace is useful when debugging performance or correctness\nproblems, answering questions of the form:\n\n* What were the last memory requests and responses?\n* What was the timing of the last memory request and responses?\n* What were the last hardware method invocations or indications?\n\n\n.. _fpgamake: https://github.com/cambridgehackers/fpgamake\n.. _buildcache: https://github.com/cambridgehackers/buildcache\n"
  },
  {
    "path": "doc/library/source/devguide/clocks.rst",
    "content": ".. _devguide_clocks:\n\n***************************************\nClocking Your Design\n***************************************\n\nEvery board has a main clock, which is the clock exposed by\n\"exposeCurrentClock\". It has a default value, but that value can be\noverriden with CONNECTALFLAG --mainclockperiod, which is an integer\nspecified in nanoseconds.\n\nThere is a second clock available, which I called \"derivedClock\"\nbecause it was derived from the main clock. You can specify its clock\nperiod with --derivedclockperiod, which is a float specified in\nnanoseconds. I'm using an MMCM, which has one clock specified by a\nfractional divisor.\n\nOn PCIe-connected boards, the main clock frequency defaults to the\nPCIe user clock frequency (125MHz for gen1, 250MHz for gen2). But you\ncan override that, in which case your hardware is connected to PCIe\nvia sync FIFOs.\n\nYou are responsible for any synchronization required between the main\nand derived clock domains.\n\nThere are two ways to get access to the derivedClock in your design.\n\nIMPORT_HOST_CLOCKS\n==================\n\nThis is simpler, and preserves the synthesis boundary on mkConnectalTop. See examples/echoslow\n\nIn the Makefile\n\n    CONNECTALFLAGS += -D IMPORT_HOST_CLOCKS\n\nAdd \":host.derivedClock,host.derivedReset\" to H2S_INTERFACES:\n\n    H2S_INTERFACES = Echo:EchoIndication:host.derivedClock,host.derivedReset\n\nOr just pass in host.derivedClock and create a reset locally.\n\nLook at the generated <board>/generatedbsv/Top.bsv to see how this changed the generated code.\n\nIMPORT_HOSTIF\n=============\n\nThis option is only useful for Zynq, in order to get access to other PS7\ninterfaces and clocks that are not part of the standard portal\ninterface, e.g., I2C.\n\n    CONNECTALFLAGS += -D IMPORT_HOSTIF\n\nAdd \":host\" to H2S_INTERFACES.\n\nSee tests/test_sdio1 for an example of the use of IMPORT_HOSTIF, though it has a manually written Top.bsv.\n\nSetting Zynq Clock Speeds\n=========================\n\n\n\nDefault Clock Speeds\n====================\n\nThe default values for --mainclockperiod and --derivedclockperiod for\nthe each board are in the JSON files in the boardinfo directory.\n"
  },
  {
    "path": "doc/library/source/devguide/compilingproject.rst",
    "content": ".. _compiling_a_project:\n\n***************************************\nCompiling and Running Connectal Project\n***************************************\n\nCompiling on ConnectalBuild\n===========================\n\nThe Connectal toolchain can be run on ConnectalBuild using the\nfollowing Buildbot web interface:\nhttp://connectalbuild.qrclab.com/projects.\n\n.. image:: connectalbuild-1.png\n\n*Before submitting a project, you must sign in using your github\ncredentials.* We do not store credentials, but pass them througth\nto github.  Next, enter a name for the project, which will be used\nfor subsequent build requests through the Buildbot web interface.  The\nproject must be in a publicly accessible git-hub repository, whose\nRepo location is entered beginning with `git://`_ as follows\n`git://github.com/connectal-examples/leds.git`_.  If the project\nmakefile is not in the root directory of the repository, enter its\nrelative path in the 'Path' field of the form.  If a particular branch\nor revision number are desired, enter these as well.  Check the button\nto select the build target.  If you have selected a zynq-based\nplatform and would like the tool-chain to automatically program the\ndevice and execute the design as its final step, then enter the IP\naddress of your board. This works only because ``adb`` doesn't\nrequire authentication. SSH keys required to run on PCIe-based\nplatforms are not currently supported.  Finally, don't forget to click\n'Add'. If the project name has already been used, you will be prompted\nto enter a new one at this point.\n\n\nCompiling Locally\n=================\n\nBefore compiling a project locally, you will need to install the\ntoolchain.  After setting the ``CONNECTALDIR`` to the root of the\nconnectal source tree, enter the command ``make``\n\nRunning the Design\n==================\n\nWhen preparing a zedboard:\n\n * Following the directions in the zynq-boot git repo, create an Android boot SD card files.\n * Write the SD card files into the first partition of an SD card (FAT format).\n * Verify that the boot mode jumpers on the board are JP8/9/10 (MIO3/4/5) == 110 for booting from SD card.\n * Verify that the PS_MIO0 pull-down jumper on the board JP6 is shorted.\n * Connect a USB cable to the 'UART' connector.  Use the 'connectable' program from the connectable git repo to display linux console output.\n * Connect an ethernet cable (linux uses DHCP to get an IP address during boot).\n\nWhen preparing a PCIe board:\n\n * Attach a USB cable to the JTAG port\n\n\n.. _git://: git://\n.. _git://github.com/connectal-examples/leds.git: git://github.com/connectal-examples/leds.git\n"
  },
  {
    "path": "doc/library/source/devguide/design.rst",
    "content": "Connectal Rationale\n===================\n\nAre you happy with the connection between software development and\nhardware development on your projects? Do you wish you had more\nflexible tools for developing test benches, drivers, and applications\nusing your hardware? Do you wish you didn't need a kernel driver?\n\nDo you wish that you could use a common flow to drive your hardware\ndevelopment, across simulation, timing verification, FPGA\nimplementation, and even the ASIC back end?\n\nDo you wish you could use a better programming language to implement\nthe hardware? Do you miss declared interfaces and structural types?\n\nDo you wish you had better tools for debugging the hardware? For\nreflecting conditions encountered on the hardware back into the\nsimulation environment where you can drill down into the problem?\n\nThese are the kinds of problems we encountered which inspired us to\ndevelop the Connectal framework. With Connectal, we are trying to\nbring the productivity of software engineering practices to hardware\ndevelopment without compromising on the performance of the hardware.\n\nConnectal provides:\n\n * Seamless development environment with test benches and apps written in C/C++\n * Streamlined application structure\n * Faster builds and greater visibility simulating hardware in bluesim/modelsim/xsim\n * Support for capture traces on interfaces and replaying them in test benches\n\n\n\n"
  },
  {
    "path": "doc/library/source/devguide/devguide.rst",
    "content": "Connectal Developer's Guide\n===========================\n\n.. toctree::\n   :maxdepth: 2\n\n   design.rst\n   projectstructure.rst\n   compilingproject.rst\n   clocks.rst\n"
  },
  {
    "path": "doc/library/source/devguide/projectstructure.rst",
    "content": "Connectal Project Structure\n***************************\n\nThe set of files composing the input to the Connectal toolchain is\nreferred to as a project.  A collection of out-of-tree example\nprojects is available at https://github.com/connectal-examples.\nTo illustrate the structure of a project, this chapter uses the\nexample https://github.com/connectal-examples/leds, which can be\nexecuted on the Bluesim or Zynq target platforms.\n\nProject Makefile\n================\n\nThe top-level Makefile in the project\n(in our example, https://github.com/connectal-examples/leds/blob/master/Makefile)\ndefines parameters building and executing the project.  In its\nsimplest form, it specifies the hardware and software source files, \nwhich Bluespec interfaces to use as interfaces (portals) between them, \nand the libraries to use for the hardware and software compilation::\n\n    INTERFACES = LedControllerRequest\n    BSVFILES = LedController.bsv Top.bsv\n    CPPFILES= testleds.cpp\n    include \\$(CONNECTALDIR)/Makefile.connectal\n\n``BSVFILES`` is a list of bsv files containing interface\ndefinitions used to generate portals and module definitions used to\ngenerate HW components.  Connectal bsv libraries can be used without\nbeing listed explicitly.\n\n``CPPFILES`` is a list of C/C++ files containing software\ncomponents and ``main``.  The Connectal C/C++ libraries can be\nused without being listed explicitly.\n\n``INTERFACES`` is a list of names of BSV interfaces which may be\nused to communicate between the HW and SW componentsy.  In addition to\nuser-defined interfaces, there are a wide variety of interfaces\ndefined in Connectal libraries which may be included in this list.\n\n``NUMBER_OF_MASTERS`` is used to designate the number of host\nbus masters the hardware components will instantiate.  For PCIe-based\nplatforms, this value can be set to 1, while on Zynq-based\nplatforms values from 1 to 4 are valid.\n\n``CONNECTALDIR`` must be set so that the top-level Connectal\nmakefile can be included, defining the makefile build targets for the project.\nThis brings in the default definitions of\nall project build parameters as well as the Connectal hardware and\nsoftware libraries.  When running the toolchain on AWS, this varible\nis set automatically in the build environment.\n(See :ref:`compiling_a_project`)\n\nProject Source\n==============\n\nInterface Definitions\n---------------------\n\\label{interface_definitions}\n\nWhen generating portals, the Connectal interface compiler searches the\nConnectal bsv libraries and the files listed in ``BSVFILES`` for\ndefinitions of the interfaces listed in ``INTERFACES``.  If\nthe definition of a listed interfaces is not found, an error is\nreported and the compilation aborts.  The interfaces in this list must\nbe composed exclusively of ``Action`` methods.  Supported method\nargument types are ``Bit\\#(n)``, ``Bool``,\n``Int\\#(32)``, ``UInt\\#(32)``, ``Float``,\n``Vector\\#(t)``, ``enum``, and ``struct``.\n\nSoftware\n--------\n\nThe software in a Connectal project consists of at least one C++ file\nwhich instantiates the generated portal wrappers and proxies and\nimplements ``main()``.  The following source defines the SW\ncomponent of the example, which simply toggles LEDs on the Zedboard\n(\\url{https://github.com/connectal-examples/leds/blob/master/testleds.cpp})::\n\n    #include <unistd.h>\n    #include \"LedControllerRequest.h\"\n    #include \"GeneratedTypes.h\"\n    int main(int argc, const char **argv)\n    {\n      LedControllerRequestProxy *device = \n\tnew LedControllerRequestProxy(IfcNames_LedControllerRequest);\n      for (int i = 0; i < 20; i++) {\n\tdevice->setLeds(10, 10000);\n\tsleep(1);\n\tdevice->setLeds(5, 10000);\n\tsleep(1);\n      }\n    }\n\n\nThe makefile listed ``LedControllerRequest`` as the only communication\ninterface.  The generated proxies and wrappers for this interface are\nin ``LedControllerRequest.h`` which is included, along with C++\nimplementations of all additional interface types in\n``GeneratedTypes.h``. Line 9 instantiates the proxy through which\nthe software invokes the hardware methods\n(See also :ref:`flow_control`)\n\nTo support projects that will execute software inside the linux kernel\n(for example, to work in conjunction with filesystems or the network stack),\nconnectal project software can also be written in C.\n\nHardware\n=========\n\nConnectal projects typically have at least one BSV file containing\ninterface declarations and module definitions.  The implementation of\nthe interfaces and all supporting infrastructure is standard BSV.\nInterfaces being used as portals are subject to the type restrictions\ndescribed earlier\n(See also :ref:`interface_definitions`)\n\nTop.bsv\n-------\n\nIn Top.bsv\n(https://github.com/connectal-examples/leds/blob/master/Top.bsv),\nthe developer instantiates all hardware modules explicitly.\nInterfaces which can be invoked through portals need to be connected\nto the generated wrappers and proxies.  To connect to the host\nprocessor bus, a parameterized standard interface is used, making it\neasy to synthesize the application for different CPUs or for\nsimulation::\n\n    // Connectal Libraries\n    import CtrlMux::*;\n    import Portal::*;\n    import Leds::*;\n    import MemTypes::*;\n    import MemPortal::*;\n    import HostInterface::*;\n    import LedControllerRequest::*;\n    import LedController::*;\n\n    typedef enum {LedControllerRequestPortal} IfcNames deriving (Eq,Bits);\n\n    module mkConnectalTop(StdConnectalTop#(PhysAddrWidth));\n       LedController ledController <- mkLedControllerRequest();\n       LedControllerRequestWrapper ledControllerRequestWrapper <- \n\t  mkLedControllerRequestWrapper(LedControllerRequestPortal,\n\t  ledController.request);\n\n       Vector#(1,StdPortal) portals;\n       portals[0] = ledControllerRequestWrapper.portalIfc;\n       let ctrl_mux <- mkSlaveMux(portals);\n\n       interface interrupt = getInterruptVector(portals);\n       interface slave = ctrl_mux;\n       interface masters = nil;\n       interface leds = ledController.leds;\n    endmodule\n\nLike the SW components, the HW begins by importing the generated\nwrappers and proxies corresponding to the interfaces listed in the\nproject Makefile.  The user-defined implementation of the\nLedControllerRequest interface is instantiated on line 14, and wrapped\non line 15.  This wrapped interface is connected to the bus using the\nlibrary module ``mkSlaveMux`` on line 21 so it can be invoked\nfrom the software.  At the end of the module definition, the top-level\ninterface elements must be connected.  A board-specific top-level\nmodule will include this file, instantiate ``mkConnectalTop`` and\nconnect the interfaces to the actual peripherals. The module\n``mkConnectalTop`` must be defined in a file named\n``Top.bsv`` in the user project.\n\nThe Bluespec compiler generates a Verilog module from the top level\nBSV module, in which the methods of exposed interfaces are implemented\nas Verilog ports. Those ports are bound to physical pins on the\nFPGA using a physical constraints file. If CPU specific interface\nsignals are needed by the design (for example, extra clocks that are\ngenerated by the PCIe core), then an optional CPU-specific HostInterface\nparameter to ``mkConnectalTop`` can also be used.  If the design uses\nexternal pins on the FPGA, those connections are also made here by\nexporting a 'Pins' interface\n(\\hyperref[host_interface]{Section~\\ref{host_interface}})\nand providing bindings in the constraints file.\n\n"
  },
  {
    "path": "doc/library/source/examples/index.rst",
    "content": "\nConnectal Examples\n==================\n\n.. toctree::\n   :maxdepth: 2\n\n   simple.rst\n"
  },
  {
    "path": "doc/library/source/examples/simple.rst",
    "content": "\nSimple Example\n==============\n\n"
  },
  {
    "path": "doc/library/source/index.rst",
    "content": ".. connectal documentation master file, created by\n   sphinx-quickstart on Tue Nov 25 12:27:26 2014.\n   You can adapt this file completely to your liking, but it should at least\n   contain the root `toctree` directive.\n\n=====================================\nWelcome to connectal's documentation!\n=====================================\n\nContents\n--------\n\n.. toctree::\n   :maxdepth: 2\n\n   intro.rst\n   installation.rst\n   design/design.rst\n   devguide/devguide.rst\n   make.rst\n   tools/tools.rst\n   bsv/bsv.rst\n   c/c.rst\n   examples/index.rst\n\nIndices and tables\n==================\n\n* :ref:`genindex`\n* :ref:`modindex`\n* :ref:`search`\n\n"
  },
  {
    "path": "doc/library/source/installation.rst",
    "content": "============\nInstallation\n============\n\nInstalling Connectal from Packages\n-----------------------------------\n\nOn Ubuntu systems, connectal may be installed from pre-built packages::\n\n    sudo add-apt-repository -y ppa:jamey-hicks/connectal\n    sudo apt-get update\n    sudo apt-get -y install connectal\n\n\nInstalling Connectal from Source\n--------------------------------\n\nConnectal source comes from three repositories::\n\n    git clone git://github.com/cambridgehackers/connectal\n    git clone git://github.com/cambridgehackers/fpgamake\n    git clone git://github.com/cambridgehackers/buildcache\n\nTo use Connectal to build hardware/software applications, some additional packages are required::\n\n    cd connectal; sudo make install-dependences\n\nInstalling Connectal and Bluespec on CentOS 7\n---------------------------------------------\n\nThe following dependencies were needed on CentOS::\n\n    sudo yum install gmp glibc-devel autoconf gperf compat-libstdc++-33\n\nCentOS does not have an iverilog packages, but it can be build from\nsource, following the instructions in its repository:\n\n  * https://github.com/steveicarus/iverilog.git\n\n\nInstalling Connectal Drivers and PCI Express Utilities:\n-------------------------------------------------------\n\nTo run Connectal applications on FPGAs attached via PCI Express, a\ncouple of device drivers have to be built and installed::\n\n   cd connectal; make all && sudo make install\n\nIn addition, you will need to build and install fpgajtag and pciescan::\n\n    git clone git://github.com/cambridgehackers/pciescan\n    (cd pciescan; make && sudo make install)\n    \n    git clone git://github.com/cambridgehackers/fpgajtag\n    (cd fpgajtag; make && sudo make install)\n\n\nInstalling Vivado\n-----------------\n    \nDownload Vivado from Xilinx:\n\n    http://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/vivado-design-tools/2015-4.html\n\nConnectal builds do not use the Vivado SDK.\n\nInstalling Ubuntu on Zynq (Zedboard, etc)\n-----------------------------------------\n\nThe shorthand instructions are:\n\n  * Follow the instructions to install Ubuntu for Raspberry Pi 2 on and SD Card\n  * Copy a Zedboard boot.bin to the first (VFAT) partition of the SD Card\n  * Boot the Zedboard\n  * Default password for user \"ubuntu\" is \"ubuntu\"\n\nToolchain\n^^^^^^^^^\n\nZynq contains dual ARM Cortex A9 cores, which are 32-bit processors\nusing the ARMv7 instruction set. They are compatible with the\ntoolchain used for Raspberry Pi 2, which has prefix\n\"arm-linux-gnueabihf\".\n\nThe \"eabi\" suffix indicates the ARM extended application binary\ninterface standard.\n\nThe \"hf\" suffix indicates that the toolchain generates floating point\ninstructions rather than subroutine calls to emulate floating point,\nbecause not all 32-bit ARM processors have floating point units.\n\nDownload the base image\n^^^^^^^^^^^^^^^^^^^^^^^\n\nDownload the Ubuntu SD card image:\n   * http://cdimage.ubuntu.com/ubuntu/releases/16.04/release/ubuntu-16.04-preinstalled-server-armhf+raspi2.img.xz\n\nWhich is referenced on this page:\n   * https://wiki.ubuntu.com/ARM/RaspberryPi\n\nFormatting and SD Card for Ubuntu\n^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^\n\nUbuntu 16.04 uses filesystem labels to determine which partitions to mount. There should be two partitions, with the following labels:\n\n   * system-boot The first partition should be vfat so that the\n     firmware in the Zynq ROM can read it to find boot.bin. The\n     following command will format the partition and label it::\n\n     mkfs -t vfat -n system-boot /dev/sdb1\n\n   * cloudimg-rootfs The second partition should be a Linux filesystem\n     (default ext4) containing the ubuntu installation. The following\n     two commands will format a partition and label it::\n\n       mkfs -t ext4 /dev/sdb2\n       e2label /dev/sdb2 cloudimg-rootfs\n\n\nInstall a boot.bin file\n^^^^^^^^^^^^^^^^^^^^^^^\n\nSee the instructions at https://github.com/cambridgehackers/zynq-boot\n\nConfiguring a Linux Kernel for Ubuntu 16.04\n^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^\n\nI had to change the kernel configuration to suppport systemd, the init\nsystem used in Ubuntu 16.04.\n\nTo be written ...\n\n\n"
  },
  {
    "path": "doc/library/source/intro.rst",
    "content": "============\nIntroduction\n============\n\nIntroduction goes here.\n\n"
  },
  {
    "path": "doc/library/source/make.rst",
    "content": "=======================\nConnectal Makefile Variables\n=======================\n\n.. toctree::\n   :maxdepth: 2\n   :numbered:\n\n   makefile.connectal.rst\n   makefile.connectal.build.rst\n"
  },
  {
    "path": "doc/library/source/makefile.connectal.build.rst",
    "content": "Makefile.connectal.build\n========================\n\nThe target Makefile, which generated by makefilegen.py (which is invoked by Makefile.connectal), includes Makefile.connectal.build.\n\nMake targets\n------------\n\n.. make:target:: bits\n\n   Builds the FPGA bitstream.\n\n.. make:target:: exe\n\n   Builds the application software (executable or shared library).\n\n.. make:target:: run\n\n   Programs the FPGA and Runs the application.\n\nBoard-specific targets\n----------------------\n\n.. make:target:: ubuntu.exe\n\n   Builds the application for boards using Ubuntu/Debian/CentOS Linux. Also used with xsim.\n\n.. make:target:: android.exe\n\n   Builds the application for boards using Android (e.g., zedboard).\n\n.. make:target:: bsim_exe\n\n   Builds the application for use with bluesim\n\n.. make:target:: bsim\n\n   Builds the hardware for Bluespec bluesim simulator\n\n.. make:target:: xsim\n\n   Builds the hardware for Xilinx xsim simulator\n\n\nEnvironment Variables\n---------------------\n\n.. envvar:: RUNPARAM\n\n   Specifies the name or address of the host on which to run the application.\n\n.. envvar:: NOFPGAJTAG\n\n   (Deprecated, use :envvar::`NOPROGRAM`. See also See also :c:data:`noprogram`.)\n   If NOFPGAJTAG is defined, then fpgajtag is not called by ubuntu.exe\n   or android.exe.\n\n.. envvar:: NOPROGRAM\n\n   If NOPROGRAM is defined, then the FPGA is not automatically\n   programmed by ubuntu.exe or android.exe. See also\n   :c:data:`noprogram`.\n\n\nVariables Controlling the Build\n-------------------------------\n\n.. make:var:: V\n\n   Binding V=1 makes the build verbose, displaying the commands that are run while building the project.\n\n.. make:var:: CONNECTAL_SHARED\n\n   Bind to 1 to build a shared library instead of an executable application.\n\n.. make:var:: CONNECTAL_NOHARDWARE\n\n   Binding to 1 suppresses creation of FPGA bitstream.\n\n.. make:var:: CONNECTAL_NDK_PARAM\n\n   Specifies options to pass to ndk-build.\n\n\nVariables Controlling the Bluespec Compiler\n-------------------------------------------\n\n.. make:var:: BSCOPTFLAGS\n\n   Specifies bsc optimization flags.\n\n.. make:var:: BSCPATHFLAGS\n\n   Specifies directories used to store output files from Bluespec compilation.\n\n.. make:var:: BSCFLAGS_COMMON\n\n   Specifies Connectal-specific bsc flags.\n\n.. make:var:: BSCFLAGS_PROJECT\n\n   Specifies project-specific bsc flags, -p argument passed to makefilegen.py via CONNECTALFLAGS.\n\n.. make:var:: BSCFLAGS_EXTRA\n\n   Specifies additional flags to pass to bsc.\n\nVerilator-related Variables\n-------------------------\n\n.. make:var:: VERILATOR_PROJECT_ARGS\n\n   Flags passed to verilator when compiling verilog for\n   simulation. For example, to enable saving signal traces to a VCD\n   file, add the following to your project's Makefile::\n\n    CONNECTALFLAGS += -DVERILATOR_PROJECT_ARGS=\"--trace\"\n\n\nBluesim-related Variables\n-------------------------\n\n.. make:var:: BSC_CXXFLAGS\n\n   CXXFLAGS passed to C++ compiler when building application for bluesim target\n\nVivado-related Variables\n------------------------\n\n.. make:var:: VIVADOFLAGS\n\n   Specifies options to pass when running vivado.\n\nBuildcache related Variables\n----------------------------\n\n.. make:var:: USE_BUILDCACHE\n\n   Bind to 1 to use buildcache.\n\n\n\nVariables Controlling the Application\n-------------------------------------\n\n.. make:var:: CONNECTAL_DEBUG\n\n   Bind CONNECTAL_DEBUG=1 to run the application under gdb.\n\n.. make:var:: RUN_ARGS\n\n   Specifies arguments to pass to the application when invoking it.\n\n"
  },
  {
    "path": "doc/library/source/makefile.connectal.rst",
    "content": "Makefile.connectal\n==================\n\nA Connectal design imports Makefile.connectal into its Makefile in order to drive the build.\n\nA number of variables are used to control the build and parameters of the design.\n\nEnvironment Variables\n---------------------\n\n.. envvar:: CONNECTALDIR\n\n   Points to the location where Makefile.connectal and the connectal tools are installed.\n\nMake Variables Defining the Application\n---------------------------------------\n\n.. make:var:: BOARD\n\n   This is typically set from the suffix of the build target, e.g., make build.zedbard defines BOARD=zedboard.\n\n.. make:var:: INTERFACES\n\n   Specifies for which interfaces to generate c/c++/bsv proxies and wrappers.\n\n.. make:var:: NUMBER_OF_MASTERS\n\n   Number of DMA masters in the design. Defaults to 1.\n\n.. make:var:: PIN_TYPE\n\n   BSV interface of exported pins. Defaults to Empty. BSV type bsv:typedef::PinType is defined from PIN_TYPE.\n\n.. make:var:: PIN_TYPE_INCLUDE\n\n   Which BSV package to import to get the declaration of PIN_TYPE.\n\n.. make:var:: PINOUT_FILE\n\n   Which pin usage JSON files to pass to makefilegen.py as :option::`--pinout` options.\n\n.. make:var:: BSVFILES\n\n   Lists the BSV files to scan when processing INTERFACES.\n\n.. make:var:: CPPFILES\n\n   Lists the C/C++ files that implement the application.\n\n.. make:var:: CPPFILES2\n\n   Lists the C/C++ files that implement the (optional) second executable of an application. For example, a daemon that coordinates access to the hardware.\n\n.. make:var:: PORTAL_DUMP_MAP\n\n   Specifies the option to provide to pcieflat to annotate PCIe traces with portal numbers and method names. Uses generatedDesignInterfaceFile.json.\n\n\nAuto Top\n--------\n\n.. make:var:: S2H_INTERFACES\n\n.. make:var:: H2S_INTERFACES\n\n.. make:var:: MEM_READ_INTERFACES\n\n.. make:var:: MEM_WRITE_INTERFACES\n\n\n\nControlling the Build\n---------------------\n\n.. make:var:: CONNECTALFLAGS\n\n   Flags to pass to makefilegen.py. See :ref:`_invocation_makefilegen.py` for its options.\n\n.. make:var:: V\n\n   Controls verbosity of the build. V=1 for verbose.\n\n.. make:var:: USE_BUILDCACHE\n\n   Define USE_BUILDCACHE=1 to use buildcache. Except fpgamake seems to use buildcache anyway.\n\n.. make:var:: BUILDCACHE\n\n   Location of buildcache script.\n\n.. make:var:: BUILDCACHE_CACHEDIR\n\n   To specify an alternate location for the buildcache cache files.\n\n.. make:var:: IPDIR\n\n   Specifies into which directory to generate IP cores. This allows generated cores to be shared between designs when the FPGA part and core parameters match.\n\n\n.. make:var:: MAIN_CLOCK_PERIOD\n\n   Bound to the clock period, in nanoseconds, of the clock domain of mkConnectalTop.\n\n   Defaults to 8ns for vc707 and kc705.\n\n   Defaults to 10ns for zedboard.\n\n   Defaults to 5ns for zc706.\n\n.. make:var:: DEFAULT_DERIVED_CLOCK_PERIOD\n\n   Bound to the default clock period, in nanoseconds, of the derived\n   clock provided via HostInterface to mkConnectalTop. Defaults to\n   half the period, twice the frequency of the main clock.\n\n.. make:var:: DERIVED_CLOCK_PERIOD\n\n   Bound to the clock period, in nanoseconds, of the derived clock provided via HostInterface to mkConnectalTop. Defaults to DEFAULT_DERIVED_CLOCK_PERIOD.\n\n.. make:var:: BURST_LEN_SIZE\n\n   Controls width of fields specifying memory request burst lengths. Defaults to 8.\n\n.. make:var:: RUNPARAM\n\n   Specifies the name or IP address of the machine on which to run the application, e.g.::\n\n      make RUNPARAM=192.168.168.100 run.android\n\n\nTop Level Make Targets\n----------------------\n\n.. make:target:: build.%\n\n   Builds software and bitfile for the specified board name, e.g.,::\n\n     make build.zedboard\n\n.. make:target:: run.%\n\n   Programs the FPGA and runs the application using the build for the specified board name. Uses :make:var:RUNPARAM. For example,::\n\n      make RUNPARAM=sj10 run.vc707\n\nIntermediate Make Targets\n-------------------------\n\n.. make:target:: verilog\n\n   Runs the build up through generation of verilog from BSV. Requires BOARD to be defined.\n\n.. make:target:: bits\n\n   Generates the FPGA bit file from the design. Requires BOARD to be defined.\n\n.. make:target:: bsim\n\n   For BOARD=bluesim, generates the simulation executable.\n\n.. make:target:: xsim\n\n   For BOARD=xsim, generates the simulation executable.\n\n.. make:target:: android.exe\n\n   Builds the software executable for boards using Android.\n\n.. make:target:: ubuntu.exe\n\n   Builds the software executable for boards using Ubunto/CentOS.\n\n.. make:target:: bsim_exe\n\n   Builds the software executable for bluesim.\n\n.. make:target:: gentarget\n\n   This step creates the board directory and Makefile.\n\n.. make:target:: prebuild\n\n   Additional steps needed before making verilog, etc.  Use this\n   target for dependences such as constraint file and IP core\n   generation that need to be run before the design is built. This is\n   a :: dependence, so you can specify it multiple times.\n"
  },
  {
    "path": "doc/library/source/themes/connectal/layout.html",
    "content": "{#\n    connectal/layout.html\n    ~~~~~~~~~~~~~~~~~~~\n\n#}\n{%- extends \"classic/layout.html\" %}\n\n{% set script_files = script_files + ['_static/tracking.js'] %}\n"
  },
  {
    "path": "doc/library/source/themes/connectal/static/tracking.js_t",
    "content": "(function(i,s,o,g,r,a,m){i['GoogleAnalyticsObject']=r;i[r]=i[r]||function(){\n(i[r].q=i[r].q||[]).push(arguments)},i[r].l=1*new Date();a=s.createElement(o),\nm=s.getElementsByTagName(o)[0];a.async=1;a.src=g;m.parentNode.insertBefore(a,m)\n})(window,document,'script','//www.google-analytics.com/analytics.js','ga');\n\nga('create', 'UA-15845210-2', 'auto');  // Replace with your property ID.\nga('send', 'pageview');\n"
  },
  {
    "path": "doc/library/source/themes/connectal/theme.conf",
    "content": "[theme]\ninherit = classic\n\n"
  },
  {
    "path": "doc/library/source/tools/generate-constraints.rst",
    "content": "\n.. _invocation_generate-constraints.py\n\nInvocation of generate-constraints.py\n=======================\n\n.. argparse::\n   :module: generate-constraints\n   :func: newArgparser\n   :prog: generate-constraints\n"
  },
  {
    "path": "doc/library/source/tools/makefilegen.rst",
    "content": "\n.. _invocation_makefilegen.py\n\nInvocation of makefilegen.py\n============================\n\nThe :program:`makefilegen.py` script generates project Makefiles. Normally, it is invoked from Makefile.connectal and passed options via :make:var:`CONNECTALFLAGS`.\n\nProject Options\n---------------\n\n.. option:: -B board, --board=board\n\n   Specifies which board to build for. \n\n.. option:: --O os, --option=os\n\n   Specifies which operating system to support. Usually derived from :option:board.\n\n.. option:: --project-dir=dir\n\n   Specifies the directory in which to creat the Makefile that\n   performs the build. Creates the directory if it does not exist.\n\nSource Options\n--------------\n\n.. option:: bsvfile\n\n   This positional argument specifies which BSV files to parse for type and interface declarations.\n\n.. option:: -s foo.cpp, --source=foo.cpp\n\n   Specifies C and C++ files to include in the application.\n\n.. option:: --ipdir=dir\n\n   Specifies where to store IP cores generated by Vivado or Quartus\n\n.. option:: --cachedir=dirname\n\n   Specifies directory to be used by `buildcache`\n\n.. option:: --nocache\n\n   Disables `buildcache`\n\n.. option:: -D var=value\n\n   Binds var to value in software, BSV, Verilog, and Tcl contexts.\n\n.. option:: -v, --verbose\n\n   Verbose operation\n\nInterface Options\n-----------------\n\n.. option:: --interfaces=...\n\n   To be written...\n\n.. option:: --dump_map\n\n   Generate a JSON file describing the portals, for use in tracing tools such as `pcieflat`.\n\nSoftware Options\n----------------\n\n.. option:: --cflags=flags\n\n   Specifies build flags for the C/C++ compiler\n\n.. option:: -I dir --cinclude=dir\n\n.. option:: -l lib, --clib=lib\n\n   Link the application with library lib.\n\n.. option:: -S libfile, --clibfiles=libfile.a\n\n   Link the application with library file `libfile.a`.\n\n.. option:: -L libdir, --clibdir=libdir\n\n   Addes `libdir` to the software library path.\n\n.. option:: --nonstrict\n\n   Pass --Wall to gcc instead of -Werror.\n\n.. option:: --shared\n\n   Specifies to build a shared library instead of an executable.\n\n.. option:: --nohardware\n\n   Suppresses build of hardware, for software-only projects.\n\n.. option:: --stl=stltype\n\n   Specifies which C++ Standard Template Library to use for Android. The choices are:\n\n    * stlport_static: STLport runtime C++ exceptions and RTTI and Standard Template Library\n    * stlport_shared\n    * gnustl_static: GNU STL runtime C++ exceptions and RTTI and Standard Template Library\n    * gnustl_shared\n    * c++_static: LLVM libc++ runtime C++ exceptions and RTTI and Standard Template Library\n    * c++_shared\n    * gabi++_static: GAbi++ runtime C++ exceptions and RTTI\n    * gabi++_shared\n\nHardware Options\n----------------\n\n.. option:: --bsvpath=dirname\n\n   Adds `dirname` to the BSV module import path.\n\n.. option:: -b options, --bscflags=options\n\n   Flags to pass to the BSV compiler.\n\n\n.. option:: -V file.v, --verilog=file.v\n\n   Specifies verilog file to include in the design\n\n.. option:: --pinfo=project.json\n\n   This does what?\n\n.. option:: --pinout=pinusage.json\n\n   Specifies connection of pins on the board to top level signals of\n   the design. A board-specific constraint file will be generated from\n   pinusage.json and the boardinfo json file, and will be added to\n   constraint and implconstraint.\n\n   See :make:var::`PINOUT_FILE`, whose values are passed as --pinout options to makefilegen.\n\n.. option:: --constraint=file.xdc\n\n   Specifies synthesis phase constraint file.\n\n.. option:: --implconstraint=file.xdc\n\n   Specifies implementation (place and route) constraint file.\n\n.. option:: --unmanaged-implconstraint=file.xdc\n\n   Specifies unmanaged implementation (place and route) constraint file.\n   This causes the xdc file to be read in using the `-unmanaged` flag of `read_xdc`.\n   This allows the xdc files to use more tcl commands than a normal xdc file (including `if` and\n   `foreach`).\n\n.. option:: -P modulename, --partition=modulename\n\n   Directs `fpgamake` to build a separate netlist for\n   `modulename`. With `buildcache`, Reduces build times if module changes infrequently.\n\nXilinx Options\n--------------\n\n.. option:: --xci=core.xci\n\n   Specifies IP core to include in the design. (Xilinx only)\n\nAltera Options\n--------------\n\n.. option:: --qip=core.qip\n\n   Specifies IP core to include in the design. (Altera only)\n\n.. option:: --qsf=settings.qsf\n\n   Specifies Altera Quartus settings.\n\nPartial Reconfiguration Options\n-------------------------------\n\n.. option:: --prtop=mkTop.dcp\n\n   Specifies filename of previously built top level.\n\n.. option:: --prvariant=name\n\n   ...\n\n.. option:: --reconfig=modulenames\n\n   ...\n\nBluesim Options\n------------------\n\n.. option:: -q, --qtused\n\n   Link the bluesim `bsim` executable with libQt.\n\n.. option:: -m foo.cpp, --bsimsource foo.cpp\n\n   Specifies additional sources to compile into the `bsim`\n   executable. If you are using Bluespec import \"BDPI\" or\n   SystemVerilog \"DPI\"/\"DPI-C\", you will need to link additional\n   sources into the simulator.\n\n   Note: These files are currently compiled with g++, even if they are\n   C files. You will need to use extern \"C\" to export symbols to the\n   simulator.\n\nXsim Options\n------------\n\n.. option:: --xelabflags=flags\n\n   Options to pass to `xelab`\n\n.. option:: --xsimflags\n\n  Options to pass to `xsim`\n\n\nClocking Options\n----------------\n\n.. option:: --mainclockperiod\n\n   Specifies the period, in nanoseconds, of the main clock. Must be an integer.\n\n   On Zynq boards, \n\n   On PCIe-connected boards, if the main clock period differs from the\n   PCIe clock period, then the design's portals and DMA ports will\n   automatically be connected via SyncFIFO's.\n\n   Each boardinfo JSON file specifies the default value for mainclockperiod.\n\n.. option:: --derivedclockperiod\n\n   Connectal also makes a second clock available, host.derivedClock. The period of this clock is \n\n   Each boardinfo JSON file specifies the default value for mainclockperiod.\n\n"
  },
  {
    "path": "doc/library/source/tools/pcieflat.rst",
    "content": "\n.. _invocation_pcieflat\n\npcieflat\n========\n\nUsage::\n\n    pcieflat\n\nDumps trace of PCIE transactions.\n\nThe trace contains the following columns:\n\n=========  ======================\ncol        description\n=========  ======================\ndirtype    TLP direction and type\ntimestamp  Timestamp of TLP, in main clock cycles\ndelta      Number of cycles since previous TLP\ntype       type:pktype:format\nbe         Byte enables\nhit        BAR hit\neof        End of frame\nsof        Start of frame\naddress    Request physical address\ntag        Request tag\n=========  ======================\n\nThe first column, `dirtype`, contains RX if received by FPGA, TX if\ntransmitted by FPGA, qq for start of request, pp for start of\nresponse, and cc for continuation.\n\nThe second column, `timestamp`, displays the timestamp in terms of a\n64-bit counter running at the PCIe user clock frequency (125MHz for\ngen1, 250MHz for gen2 and gen3).\n\nThe third column, `delta`, displays the number of cycles since the\nprevious TLP. If a TLP is transmitted and received on the same cycle,\nthen the transmitted TLP will have a delta of 0. The first TLP shown\nin the trace will have a delta of 0.\n\nThe fourth column shows the type of the TLP. If it is the start of a\ntransaction, it will be of the form `type:tlppkttype:tlpformat`, where\nthe types are:\n\n  * CpuRReq: read request from CPU to FPGA\n  * CpuWReq: write request from CPU to FPGA\n  * CpuRRsp: read response from FPGA to CPU\n  * DmaRReq: read request from FPGA to CPU DRAM\n  * DmaWReq: write request from FPGA to CPU DRAM\n  * DmaRRsp: read response from CPU DRAM to FPGA\n  * CpuRCon: continuation data sent from FPGA to CPU (continuation of CpuRRsp or DmaWReq)\n  * DmaRCon: continuation data sent from CPU DRAM to FPGA (continuation of DmaRRsp or CpuWReq)\n  * Interru: interrupt message from FPGA to CPU\n\nThe TLP `pkttype` is one of the following:\n\n  * MRW:  Memory read/write\n  * COMP: additional data (\"completion\") of transaction\n\nThe TLP `format` is one of the following:\n\n  * MEM_WRITE_3DW_DATA: 96-bit write request header containing 32-bit address and 32-bit data\n  * MEM_WRITE_4DW_DATA: 128-bit write request header containing 64-bit address and no data\n  * MEM_READ__3DW: 96-bit read request header containing 32-bit address\n  * MEM_READ__4DW: 128-bit read request header containing 64-bit address\n\nThe `sof` and `eof` flags indicate the start and end TLPs of each\ntransaction.\n\nDiagnosing Crashes\n------------------\n\nIf the machine crashed, look for transactions that were\nstarted but not ended.\n\nThese will generally fall before very large deltas, where the machine\nwas rebooted before it had any more interactions with the FPGA.\n\nExample Trace\n--------------\n\nHere are some excerpts from the output of `pcieflat` after running `tests/memserver_copy`::\n\n    pcieflat: devices are ['/dev/portal_0_6', '/dev/portal_0_5', '/dev/portal_0_4', '/dev/portal_0_3', '/dev/portal_0_2', '/dev/portal_0_1']\n\t\t ts     delta   response                     XXX          tlp          address  off   be       tag     clid  nosnp  laddr        data\n\t\t\t\t    pkttype format               foo (be hit eof sof)            (1st last)        req     stat  bcnt    length\n    RXpp  513858932          0 DmaRRsp:COMP:MEM_WRITE_3DW_DATA 09 0x4 tlp(ffff 0 0 1)                        tag:07 0300 0000 0 00 080 00  16 01179d1d \n    TXcc  513858932          0 CpuRCon                         10 0x8 tlp(ffff 0 0 0)                            data:259b17012c9b1701339b17013a9b1701 \n    RXcc  513858933          1 DmaRCon                         08 0x4 tlp(ffff 0 0 0)                            data:249d17012b9d1701329d1701399d1701 \n    TXcc  513858933          0 CpuRCon                         10 0x8 tlp(ffff 0 1 0)                            data:419b1701489b17014f9b1701569b1701 \n    RXcc  513858934          1 DmaRCon                         08 0x4 tlp(ffff 0 0 0)                            data:409d1701479d17014e9d1701559d1701 \n    RXcc  513858935          1 DmaRCon                         08 0x4 tlp(ffff 0 0 0)                            data:5c9d1701639d17016a9d1701719d1701 \n    RXcc  513858936          1 DmaRCon                         08 0x4 tlp(ffff 0 1 0)                            data:789d17017f9d1701869d170164b19a21 \n    RXpp  513858938          2 DmaRRsp:COMP:MEM_WRITE_3DW_DATA 09 0x4 tlp(ffff 0 0 1)                        tag:07 0300 0000 0 00 040 40  16 01179d8d \n    RXcc  513858939          1 DmaRCon                         08 0x4 tlp(ffff 0 0 0)                            data:949d17019b9d1701a29d1701a99d1701 \n    RXcc  513858940          1 DmaRCon                         08 0x4 tlp(ffff 0 0 0)                            data:b09d1701b79d1701be9d1701c59d1701 \n    RXcc  513858941          1 DmaRCon                         08 0x4 tlp(ffff 0 0 0)                            data:cc9d1701d39d1701da9d1701e19d1701 \n    RXcc  513858942          1 DmaRCon                         08 0x4 tlp(ffff 0 1 0)                            data:e89d1701ef9d1701f69d1701af3ad2c2 \n    TXqq  513858949          7 DmaWReq: MRW:MEM_WRITE_4DW_DATA 11 0x8 tlp(ffff 0 0 1) address: 000000035f4fc680 be(1st: f last:f) tag:05 reqid:0300 length:32 \n    TXcc  513858950          1 CpuRCon                         10 0x8 tlp(ffff 0 0 0)                            data:5d9b1701649b17016b9b1701729b1701 \n    TXcc  513858951          1 CpuRCon                         10 0x8 tlp(ffff 0 0 0)                            data:799b1701809b1701879b17018e9b1701 \n    TXcc  513858952          1 CpuRCon                         10 0x8 tlp(ffff 0 0 0)                            data:959b17019c9b1701a39b1701aa9b1701 \n    TXcc  513858953          1 CpuRCon                         10 0x8 tlp(ffff 0 0 0)                            data:b19b1701b89b1701bf9b1701c69b1701 \n    TXcc  513858954          1 CpuRCon                         10 0x8 tlp(ffff 0 0 0)                            data:cd9b1701d49b1701db9b1701e29b1701 \n    TXcc  513858955          1 CpuRCon                         10 0x8 tlp(ffff 0 0 0)                            data:e99b1701f09b1701f79b1701fe9b1701 \n    TXcc  513858956          1 CpuRCon                         10 0x8 tlp(ffff 0 0 0)                            data:059c17010c9c1701139c17011a9c1701 \n    TXcc  513858957          1 CpuRCon                         10 0x8 tlp(ffff 0 1 0)                            data:219c1701289c17012f9c1701369c1701 \n\n\nIt may contain DMA Read Requests::\n\n    TXqq  513859009          1 DmaRReq: MRW:MEM_READ__4DW      11 0x8 tlp(ffff 0 1 1) address: 000000039e8fc800 be(1st: f last:f) tag:00 reqid:0300 length:32 \n    TXqq  513859010          1 DmaRReq: MRW:MEM_READ__4DW      11 0x8 tlp(ffff 0 1 1) address: 000000039e8fc880 be(1st: f last:f) tag:01 reqid:0300 length:32 \n\nThe trace may contain interrupts::\n\n    TXqq  513865009         12 Interru: MRW:MEM_WRITE_3DW_DATA 11 0x8 tlp(ffff 0 1 1)  fee00000    0 be(f 0) tag:00 0300                    1 0000406e \n\nIt will also contain reads and writes from the CPU to the FPGA::\n\n    RXqq  513874994       9985 CpuRReq: MRW:MEM_READ__3DW      09 0x4 tlp(ffff 4 1 1)  df400000    0 be(f 0) tag:00 0038                    1 \n    TXpp  513875008         14 CpuRRsp:COMP:MEM_WRITE_3DW_DATA 11 0x8 tlp(ffff 4 1 1)                        tag:00 0038 0300 0 00 004 00   1 00000001 \n    RXqq  513875159        151 CpuRReq: MRW:MEM_READ__3DW      09 0x4 tlp(ffff 4 1 1)  df402000  800 be(f 0) tag:00 0038                    1 \n    TXpp  513875173         14 CpuRRsp:COMP:MEM_WRITE_3DW_DATA 11 0x8 tlp(ffff 4 1 1)                        tag:00 0038 0300 0 00 004 00   1 00000000 \n    RXqq  513875323        150 CpuRReq: MRW:MEM_READ__3DW      09 0x4 tlp(ffff 4 1 1)  df401000  400 be(f 0) tag:00 0038                    1 \n    TXpp  513875337         14 CpuRRsp:COMP:MEM_WRITE_3DW_DATA 11 0x8 tlp(ffff 4 1 1)                        tag:00 0038 0300 0 00 004 00   1 00000000 \n    RXqq  513876236        899 CpuRReq: MRW:MEM_READ__3DW      09 0x4 tlp(ffff 4 1 1)  df40000c    3 be(f 0) tag:00 0038                    1 \n    TXpp  513876250         14 CpuRRsp:COMP:MEM_WRITE_3DW_DATA 11 0x8 tlp(ffff 4 1 1)                        tag:00 0038 0300 0 00 004 0c   1 00000001 \n    RXqq  513876449        199 CpuRReq: MRW:MEM_READ__3DW      09 0x4 tlp(ffff 4 1 1)  df400020    8 be(f 0) tag:00 0038                    1 \n    TXpp  513876463         14 CpuRRsp:COMP:MEM_WRITE_3DW_DATA 11 0x8 tlp(ffff 4 1 1)                        tag:00 0038 0300 0 00 004 20   1 00000000 \n    RXqq  513883818       7355 CpuRReq: MRW:MEM_READ__3DW      09 0x4 tlp(ffff 4 1 1)  df40000c    3 be(f 0) tag:00 0038                    1 \n    TXpp  513883832         14 CpuRRsp:COMP:MEM_WRITE_3DW_DATA 11 0x8 tlp(ffff 4 1 1)                        tag:00 0038 0300 0 00 004 0c   1 00000000 \n    RXqq  513883976        144 CpuWReq: MRW:MEM_WRITE_3DW_DATA 09 0x4 tlp(ffff 4 1 1)  df400004    1 be(f 0) tag:02 0000                    1 00000001 \n    RXqq  513884007         31 CpuRReq: MRW:MEM_READ__3DW      09 0x4 tlp(ffff 4 1 1)  df40200c  803 be(f 0) tag:00 0038                    1 \n    TXpp  513884021         14 CpuRRsp:COMP:MEM_WRITE_3DW_DATA 11 0x8 tlp(ffff 4 1 1)                        tag:00 0038 0300 0 00 004 0c   1 00000000 \n    RXqq  513884165        144 CpuWReq: MRW:MEM_WRITE_3DW_DATA 09 0x4 tlp(ffff 4 1 1)  df402004  801 be(f 0) tag:03 0000                    1 00000001 \n\nThe trace will end with a summary of the kinds of PCIe transactions::\n\n    {'DmaWReq': 115, 'CpuRReq': 45, 'Interru': 3, 'CpuRRsp': 45, 'CpuRCon': 922, 'CpuWReq': 15, 'DmaRReq': 112, 'DmaRRsp': 141, 'DmaRCon': 904}\n    2302\n\n"
  },
  {
    "path": "doc/library/source/tools/tools.rst",
    "content": "=======================\nConnectal Tools\n=======================\n\n.. toctree::\n   :maxdepth: 2\n   :numbered:\n\n   makefilegen.rst\n   generate-constraints.rst\n   pcieflat.rst\n   topgen.rst\n"
  },
  {
    "path": "doc/library/source/tools/topgen.rst",
    "content": "\n.. _invocation_topgen.py\n\nInvocation of topgen.py\n=======================\n\n.. argparse::\n   :module: topgen\n   :func: newArgparser\n   :prog: topgen\n"
  },
  {
    "path": "doc/makefilegen.md",
    "content": "# Using makefilegen.py\n\nHere are the options supported by `makefilegen.py`\n\n| Option | Long Option | Default | Description |\n---------|-------------|---------|-------------------------------------|\n| -b     | --bscflags  |         | Options to pass to the BSV compiler |\n| -B     | --board     | zc702   | Board to generate code for (Mandatory) [bluesim, zedboard, zc702, vc707, kc705, ...]|\n| -C     | --constraint|         | Additional constraint files (Optional) |\n| -I     | --contentid |         | Specify 64-bit contentid for PCIe designs (Optional) |\n| -M     | --make      |         | Run make on the specified targets after generating code (Optional) |\n| -O     | --OS        |         | Operating system of platform, inferred from board (Optional) |\n| -V     | --verilog   |         | Additional verilog sources to include in hardware synthesis. (Optional) |\n| -h2s   | --h2sinterface |      | Hardware to software interface |\n| -l     | --clib      |         | Additional C++ libary (Optional) |\n| -p     | --project-dir | ./xpsproj | Directory in which to generate files (Optional) |\n| -s     | --source    |         | C++ source files (Optional) |\n| -s2h   |--s2hinterface |       | Software to hardware interface |\n| -t     | --topbsv    |         | Top-level bsv file (Required) |\n| -x     | --export    |         | Promote/export named interface from top module (Required) |\n\n"
  },
  {
    "path": "doc/maxcommonsubseq.md",
    "content": "## Maximum Common Subsequence\n\nA problem very much related to DNA sequence alignment is the problem of finding the longest common subsequence in a pair of strings.\n\nSuppose we have two strings:\n\nA = \"   A  B   C    D  \"\nB = \"........B....C..\"\n\nThe longest common subsequence is \"BC\" even though the positions of the B and the C are different in the two strings and the gap between them is different.\n\nIt was known in 1974 how to find the answer in O(mn) time and O(mn) space where m = len(A) and n = len(B).\n\nIn 1975, Hirschberg discovered a way to find the longest common subsequence in O(mn) time but only O(m+n) space.\n\nHirschberg, D. S. (1975). A Linear Space Algorithm for Computing Maximal Common Subsequences. CACM, 18(6), pp 341-343.(A Linear Space Algorithm for Computing Maximal Common Subsequences)\n\nRefer to [http://www.akira.ruc.dk/~keld/teaching/algoritmedesign_f03/Artikler/05/Hirschberg75.pdf]{\n\nSee also [http://en.wikipedia.org/wiki/Hirschberg's_algorithm](Wikipedia article on Hirschberg's Algorithm)\n\nThe straightforward way to solve this problem is via dynamic programming.   Let A_i be the first i characters of A, and B_j be the first j characters of B.\n\n Imagine a matrix L with m rows and n columns, such that L[i][j] is the length of the longest common subsequence of A_i and B_j\n\nThen\n\n            if A[i-1]==B[j-1]:\n                L[i][j] = L[i-1][j-1] + 1\n            else:\n                L[i][j] = max(L[i][j-1], L[i-1][j])\n\nIf the last characters match, then L[i][j], the length of the longest common subsequence is the lcs of the prefixes plus 1.  If the last characters don't match, then the lcs is the longer of L[i-1][j] or L[i][j-1].  In the references to A[i-1] and B[j-1], the -1's are there because in python strings are 0 origin.\n\nSince the dependencies of the recurrence are only \"up\" and \"to the left\" we can compute the whole matrix incrementally from top to bottom and left to right. Here is Hirschberg's Algorithm A:\n\n    # compute maximal length subsequence of A and B\n    def hirschbergalga(A, B):\n\tm = len(A)\n\tn = len(B)\n\tL = [[0 for j in xrange(n+1)] for i in xrange(m+1)]\n\tfor i in xrange(1, m+1):\n\t    L[i][0] = 0\n\tfor j in xrange(1, n+1):\n\t    L[0][j] = 0\n\tfor i in xrange(1, m+1):\n\t    for j in xrange(1, n+1):\n\t\tif A[i-1]==B[j-1]:\n\t\t    L[i][j] = L[i-1][j-1] + 1\n\t\telse:\n\t\t    L[i][j] = max(L[i][j-1], L[i-1][j])\n\treturn L\n\nConsider again the recurrence. Row j of L depends only on earlier values in row j and on row j-1. Therefore we do not need to retain the entire matrix, but rather only the last two rows.  If we also return the final row we get Hirschberg's Algorithm B\n\n    def hirschbergalgb(A, B):\n\tm = len(A)\n\tn = len(B)\n\tK = [[0 for j in xrange(n+1)] for i in xrange(2)]\n\tfor i in xrange(1,m+1):\n\t    for j in xrange(n+1):\n\t\tK[0][j] = K[1][j]\n\t    for j in xrange(1, n+1):\n\t\tif A[i-1]==B[j-1]:\n\t\t    K[1][j] = K[0][j-1] + 1\n\t\telse:\n\t\t    K[1][j] = max(K[1][j-1], K[0][j])\n\tLL = [K[1][j] for j in xrange(n+1)]\n\treturn(LL)\n\n\nThis is not coded as efficiently as it could be, in that the rows of K are copied every time through the loop.\n\nAt this point, Hirschberg adopts a recursive strategy.  For any point i in A there is at least one point j in B\nsuch that\n\n    L[m][n] = L[i][j] + L'[i][j]  \n\nwhere L' is the \"reverse problem\", the maximum length subsequence from subscripts i and j to the ends of strings A and B.  In other words.   The algorithm chooses an i halfway through string A, then uses Algorithm B to locate the corresponding point j, then recursively solves the two subproblems.\n\n\n    def hirschbergalgc(A, B):\n\tm = len(A)\n\tn = len(B)\n\tC = \"\"\n\tif n == 0:\n\t    return \"\"\n\tif m == 1:\n\t    if A[0] in B:\n\t\treturn A\n\t    else:\n\t\treturn \"\"\n\ti = m / 2\n\tL1 = hirschbergalgb(A[0:i], B)\n\tL2 = hirschbergalgb(A[i:][::-1], B[::-1])\n\tm = -1\n\tfor j in xrange(n+1):\n\t    t = L1[j] + L2[n-j];\n\t    if t > m:\n\t\tm = t\n\t\tk = j\n\tC1 = hirschbergalgc(A[0:i],B[0:k])\n\tC2 = hirschbergalgc(A[i:], B[k:])\n\treturn C1 + C2\n\n\n    This method takes a logarithmic recursion depth, because the subproblems are half the size at each level. The storage used is O(m+n) and the time is O(mn).  The really clever bit is the use of Algorithm B to locate\nthe j corresponding to a particular i.  Algorithm B uses the dynamic programming recurrance to solve for all possible j values in a single pass, then it is a simple matter to find the best j.\n\nSee the actual example code in connectal/examples/maxcommonsubseq/hirschberg.py\n"
  },
  {
    "path": "doc/previous/portal.asciidoc",
    "content": "CONNECTAL\n====\nJamey Hicks <jamey.hicks@gmail.com>, John Ankcorn, Myron King, L. Stewart - Scribe\n0.002\nApril 29, 2014\n\n\n== What is CONNECTAL?\n\n[role=\"lead\"]\nCONNECTAL provides a hardware-software interface for applications split\nbetween user mode code and custom hardware in an FPGA or ASIC.\n\nCONNECTAL can automaticaly build the software and hardware glue for a\nmessage based interface and also provides for configuring and using\nshared memory between applications and hardware. Communications\nbetween hardware and software are provided by a bidirectional flow of\nevents and regions of memory shared between hardware and software.\nEvents from software to hardware are called requests and events from\nhardware to software are called indications, but in fact they are\nsymmetric.\n\n:bsvdocumentation: http://wiki.bluespec.com/Home/BSV-Documentation\n:bluespecdotcom:     http://www.bluespec.com/\n\n== Lexicon\n\nconnectal:: The name of the project, whose goal is to ease the task of\nbuilding applications composed of hardware and software components.\nProgrammers use bsv as an IDL to specify the interface between the\nhardware and software components.  A combination of generated code and\nlibraries coordinate the data-flow between the program modules.\nBecause the HW and SW stacks are customized for each application, the\noverheads associated with communicating across the HW/SW boundary are\nlow.\n\nHW/SW interface :: portal\n\nbsv:: Bluespec System Verilog.  bsv is a language for describing hardware that is might higher level than verilog. See {bsvdocumentation}[BSV Documentation] and {bluespecdotcom}[Bluespec, Inc].\n\nbluespec:: Shorthand for Bluespec System Verilog (bsv)\n\nindexterm:portal\nportal:: a logical request/indication pair is referred to as a portal.  current tools require their specification in the IDL to be syntactically identifiable (i.e. fooRequest/fooIndication).  An application can make use of multiple portals, which may be specified independently.\n\nrequest interface:: These methods are implemented by the application hardware to be invoked by application software.   A bsv interface consisting of ‘Action’ methods.  Because of the ‘Action’ type, data flow across this interface is unidirectional (SW -> HW).\n\nindication interface:: The dual of a request interface, indication interfaces are ‘Action’ methods implemented by application software to be invoked by application hardware.   As with request interfaces, the data flow across this interface is unidirectional, but in the opposite direction.\n\npcieportal/zynqportal:: these two loadable kernel modules implement the minimal set of driver functionality.  Specifically, they expose portal HW registers to SW through mmap, and set up interrupts to notify SW that an indication method has been invoked by HW.  \n\nportalalloc:: This loadable kernel module exposes a subset of dma-buf functionality to user-space software (though a set of ioctl commands) to allocate and manage memory regions which can be shared between SW and HW processes.   Maintaining coherence of the allocated buffers between processes is not automatic: ioctl commands for flush/invalidate are provided to be invoked explicitly by the users if necessary. \n\nconnectalgen:: The name of the interface compiler which takes as input the bsv interface specification along with a description of a target platform and generates logic in both HW and SW to support this interface across the communication fabric.\n\n== Example setups:\n\nA zedboard ( http://www.zedboard.org/ ),\nwith Android running on the embedded ARM processors (the Processing\nSystem 7), an application running as a user process, and custom\nhardware configured into the Programmable Logic FPGA.\n\nAn x86 server, with Linux running on the host processor, an\napplication running partly as a user process on the host and partly as\nhardware configured into an FPGA connected by PCI express (such as the\nXilinx VC707\n(http://www.xilinx.com/products/boards-and-kits/EK-V7-VC707-G.htm).\n\n== Background\n\nWhen running part or all of an application in an FPGA, it is usually\nnecessary to communicate between code running in user mode on the host\nand the hardware.  Typically this has been accomplished by custom\ndevice drivers in the OS, or by shared memory mapped between the\nsoftware and the hardware, or both.  Shared memory has been\nparticularly troublesome under Linux or Android, because devices\nfrequently require contiguous memory, and the mechanisms for\nguaranteeing successful memory allocation often require reserving the\nmaximum amount of memory at boot time.\n\nPortal tries to provide convenient solutions to these problems in a portable way.\n\nIt is desirable to have\n\n* low latency for small messages\n\n* high bandwidth for large messages\n\n* notification of arriving messages\n\n* asynchronous replies to messages\n\n* support for hardware simulation by a separate user mode process\n\n* support for shared memory (DMA) between hardware and software\n\n\n== Overview\n\nPortal is implemented as a loadable kernel module device driver for Linux/Android and a set of tools to automatically construct the hardware and software glue necessary for communications.\n\nShort messages are handled by programmed I/O.  The message interface from software to hardware (so called \"requests\") is defined as a bsv interface containing a number of Action methods, each with a name and typed arguments.  The interface generator creates all the software and hardware glue so that software invocations of the interface stubs flow through to, and are turned into bsv invocations of the matching hardware.  The machinery does not have flow control. Software is responsible for not overrunning the hardware.  There is a debug mechanism which will return the request type of a failed method, but it does not tell which invocation failed.  Hardware to software interfaces (so called “indications”) are likewise defined by bsv interfaces containing Action methods. Hardware invocations of these methods flow through to and cause software calls to corresponding user-supplied functions.  In the current implementation there is flow control, in that the hardware will stall until there is room for a hardware to software message.  There is also a mechanism for software to report a failure, and there is machinery for these failures to be returned to the hardware.\n\n[\"seqdiag\",target=\"request-response-1.png\"]\n---------------------------------------------------------------------\n{\n  // edge label\n  SW -> HW [label = \"request\"];\n  SW <- HW [label = \"indication\"];\n}\n---------------------------------------------------------------------\n\nPortals do not have to be structured as request/response. Hardware can\nsend messages to software without a prior request from software.\n\n[\"seqdiag\",target=\"indication-only.png\"]\n---------------------------------------------------------------------\n{\n  // edge label\n  SW <- HW [label = \"indication\"];\n}\n---------------------------------------------------------------------\n\nIncoming messages can cause host interrupts, which wake up the device driver, which can wake up the user mode application by using the select(2) or poll(2) interfaces.\n\n\nMost of the time, communications between hardware and software will\nproceed without requiring use of the OS.  User code will read and\nwrite directly to memory mapped I/O space. Library code will poll for\nincoming messages, and [true? eventually time out and call poll(2).\nOnly when poll(2) or select(2) are called will the device driver\nenable hardware interrupts.  Thus interrupts are only used to wake up\nsoftware after a quiet period.\n\nThe designer specifies a set of hardware functions that can be called\nfrom software, and a set of actions that the hardware can take which\nresult in messages to software. Portal tools take this specification\nand build software glue modules to translate software function calls\ninto I/O writes to hardware registers, and to report hardware events\nto software.\n\nFor larger memory and OS bypass (OS bypass means letting the user mode\napplication talk directly to the hardware without using the OS except\nfor setup), portal implements shared memory.  Portal memory objects\nare allocated by the user mode program, and appear as Linux file\ndescriptors. The user can mmap(2) the file to obtain user mode access\nto the shared memory region. Portal does not assure that the memory is\nphysically contiguous, but does pin it to prevent the OS from reusing\nthe memory.  An FPGA DMA controller module is provided that gives the\nillusion of contiguous memory to application hardware, while under the\ncovers using a translation table of scattered addresses.\n\nThe physical addresses are provided to the user code in order to\ninitialize the dma controller, and address \"handles\" are provided for\nthe application hardware to use.\n\nThe DMA controller provides Bluespec objects that support streaming access with automatic page crossings, or random access.\n\n== An Example\n\nAn application developer will typically write the hardware part of the application in Bluespec and the software part of the application in C or C++.  In a short example, there will be a bsv source file for the hardware and a cpp source file for the application.\n\nThe application developer is free to specify whatever hardware-software interface makes sense.\n\nRefer to https://github.com/cambridgehackers/connectal\n\nIn the examples directory, see [simple](../examples/simple/).  The file [Simple.bsv](../examples/simple/Simple.bsv) defines the hardware, and testsimple.cpp supplies the software part. In this case, the software part is a test framework for the hardware.\n\nSimple.bsv declares a few `struct` and `enum` types:\n\n---------------------------------\n    typedef struct{\n       Bit#(32) a;\n       Bit#(32) b;\n       } S1 deriving (Bits);\n\n    typedef struct{\n       Bit#(32) a;\n       Bit#(16) b;\n       Bit#(7) c;\n       } S2 deriving (Bits);\n\n    typedef enum {\n       E1Choice1,\n       E1Choice2,\n       E1Choice3\n       } E1 deriving (Bits,Eq);\n\n    typedef struct{\n       Bit#(32) a;\n       E1 e1;\n       } S3 deriving (Bits);\n---------------------------------\n\nSimple.bsv defines the actions (called Requests) that software can use to cause the hardware to act, and defines the notifications (called Indications) that the hardware can use to signal the software.\n\n---------------------------------\n    interface SimpleIndication;\n\tmethod Action heard1(Bit#(32) v);\n\tmethod Action heard2(Bit#(16) a, Bit#(16) b);\n\tmethod Action heard3(S1 v);\n\tmethod Action heard4(S2 v);\n\tmethod Action heard5(Bit#(32) a, Bit#(64) b, Bit#(32) c);\n\tmethod Action heard6(Bit#(32) a, Bit#(40) b, Bit#(32) c);\n\tmethod Action heard7(Bit#(32) a, E1 e1);\n    endinterface\n\n    interface SimpleRequest;\n\tmethod Action say1(Bit#(32) v);\n\tmethod Action say2(Bit#(16) a, Bit#(16) b);\n\tmethod Action say3(S1 v);\n\tmethod Action say4(S2 v);\n\tmethod Action say5(Bit#(32)a, Bit#(64) b, Bit#(32) c);\n\tmethod Action say6(Bit#(32)a, Bit#(40) b, Bit#(32) c);\n\tmethod Action say7(S3 v);\n    endinterface\n---------------------------------\n\n\nSoftware can start the hardware working via say, say2, ... Hardware\nsignals back to software with heard and heard2 and so fort.  In the\ncase of this example, say and say2 merely echo their arguments back to\nsoftware.\n\nThe definitions in the bsv file are used by the connectal infrastructure ( a python program)  to automatically create corresponding c++ interfaces.\n\n---------------------------------\n    ../../connectalgen -Bbluesim -p bluesim -x mkBsimTop \\\n         -s2h SimpleRequest \\\n         -h2s SimpleIndication \\\n         -s testsimple.cpp \\\n         -t ../../bsv/BsimTop.bsv  Simple.bsv Top.bsv\n---------------------------------\n\nThe tools have to be told which interface records should be used for\nSoftware to Hardware messages and which should be used for Hardware to\nSoftware messages. These interfaces are given on the command line for\ngenxpprojfrombsv\n\nconnectalgen constructs all the hardware and software modules\nneeded to wire up portals. This is sort of like an RPC compiler for\nthe hardware-software interface. However, unlike an RPC each method is\nasynchronous.\n\nThe user must also create a toplevel bsv module Top.bsv, which\ninstantiates the user portals, the standard hardware environment, and\nany additional hardware modules.\n\nRather than constructing the `connectalgen` command line from\nscratch, the examples in connectal use include\n[Makefile.connectal] and define some `make`\nvariables.\n\nHere is the Makefile for the `simple` example:\n\n[source,makefile]\n---------------------------------\n    CONNECTALDIR?=../..\n    INTERFACES = SimpleRequest SimpleIndication\n    BSVFILES = Simple.bsv Top.bsv\n    CPPFILES=testsimple.cpp\n\n    include $(CONNECTALDIR)/Makefile.connectal\n---------------------------------\n\n\nDesigns outside the connectal directory using `connectal` may also include `Makefile.connectal`:\n\n[source,makefile]\n---------------------------------\n    \n    CONNECTALDIR?=/scratch/connectal\n    INTERFACES = ...\n    BSVFILES = ...\n    CPPFILES = ...\n    include $(CONNECTALDIR)/Makefile.connectal\n---------------------------------\n\n\n=== simple/Top.bsv\n\nEach CONNECTAL design implements [Top.bsv](../examples/simple/Top.bsv) with some standard components.\n\nIt defines the `IfcNames` enum, for use in identifying the portals between software and hardware:\n\n\n---------------------------------\n    typedef enum {SimpleIndication, SimpleRequest} IfcNames deriving (Eq,Bits);\n---------------------------------\n\n\nIt defines `mkConnectalTop`, which instantiates the wrappers, proxies, and the design itself:\n\n\n---------------------------------\n    module mkConnectalTop(StdConnectalTop#(addrWidth));\n---------------------------------\n\n\n`StdConnectalTop` is parameterized by `addrWidth` because Zynq and x86 have different width addressing. `StdConnectalTop` is a typedef:\n\n---------------------------------\n    typedef ConnectalTop#(addrWidth,64,Empty)     StdConnectalTop#(numeric type addrWidth);\n---------------------------------\n\nThe \"64\" specifies the data width and `Empty` specifies the empty\ninterface is exposed as pins from the design. In designs using HDMI,\nfor example, `Empty` is replaced by `HDMI`.  On some platforms, the\ndesign may be able to use different data widths, such as 128 bits on\nx86/PCIe.\n\nNext, `mkConnectalTop` instantiates user portals:\n\n---------------------------------\n    // instantiate user portals\n       SimpleIndicationProxy simpleIndicationProxy <- mkSimpleIndicationProxy(SimpleIndication);\n---------------------------------\n\nInstantiate the design:\n\n---------------------------------\n       SimpleRequest simpleRequest <- mkSimpleRequest(simpleIndicationProxy.ifc);\n---------------------------------\n\n\nInstantiate the wrapper for the design:\n\n---------------------------------\n       SimpleRequestWrapper simpleRequestWrapper <- mkSimpleRequestWrapper(SimpleRequest,simpleRequest);\n---------------------------------\n\n\nCollect the portals into a vector:\n\n---------------------------------\n       Vector#(2,StdPortal) portals;\n       portals[0] = simpleRequestWrapper.portalIfc; \n       portals[1] = simpleIndicationProxy.portalIfc;\n---------------------------------\n\nCreate an interrupt multiplexer from the vector of portals:\n\n---------------------------------\n       let interrupt_mux <- mkInterruptMux(portals);\n---------------------------------\n\nCreate the system directory, which is used by software to locate each portal via the `IfcNames` enum:\n\n---------------------------------\n       // instantiate system directory\n       StdDirectory dir <- mkStdDirectory(portals);\n       let ctrl_mux <- mkAxiSlaveMux(dir,portals);\n---------------------------------\n\nThe following generic interfaces are used by the platform specific top BSV module:\n\n---------------------------------\n       interface interrupt = interrupt_mux;\n       interface ctrl = ctrl_mux;\n       interface m_axi = null_axi_master;\n       interface leds = echoRequestInternal.leds;\n\n    endmodule : mkConnectalTop\n---------------------------------\n\n\n\n=== simple/testsimple.cpp\n\nCONNECTAL generates header files declaring wrappers for\nhardware-to-software interfaces and proxies for software-to-hardware\ninterfaces. These will be in the \"jni/\" subdirectory of the project directory.\n\n[source,C]\n---------------------------------\n    #include \"SimpleIndication.h\"\n    #include \"SimpleRequest.h\"\n---------------------------------\n\n\nIt also declares software equivalents for structs and enums declared in the processed BSV files:\n\n[source,C]\n---------------------------------\n    #include \"GeneratedTypes.h\"\n---------------------------------\n\n\nCONNECTAL generates abstract virtual base classes for each Indication interface.\n\n[source,C]\n---------------------------------\n    class SimpleIndicationWrapper : public Portal {\n\n    public:\n\t...\n\tSimpleIndicationWrapper(int id, PortalPoller *poller = 0);\n\tvirtual void heard1 ( const uint32_t v )= 0;\n\t...\n    };\n---------------------------------\n\nImplement subclasses of the wrapper in order to define the callbacks\n\n[source,C]\n---------------------------------\n    class SimpleIndication : public SimpleIndicationWrapper\n    {  \n    public:\n      ...\n\tvirtual void heard1(uint32_t a) {\n\t  fprintf(stderr, \"heard1(%d)\\n\", a);\n\t  assert(a == v1a);\n\t  incr_cnt();\n\t}\n\t...\n    };\n---------------------------------\n\nTo connect these classes to the hardware, instantiate them using the\n`IfcNames` enum identifiers. CONNECTAL prepends the name of the type\nbecause C++ does not support overloading of enum tags.\n\n[source,C]\n---------------------------------\n    SimpleIndication *indication = new SimpleIndication(IfcNames_SimpleIndication);\n    SimpleRequestProxy *device = new SimpleRequestProxy(IfcNames_SimpleRequest);\n---------------------------------\n\nCreate a thread for handling notifications from hardware:\n\n[source,C]\n---------------------------------\n    pthread_t tid;\n    if(pthread_create(&tid, NULL,  portalExec, NULL)){\n      exit(1);\n    }\n---------------------------------\n\nNow the software invokes hardware methods via the proxy:\n\n[source,C]\n---------------------------------\n    device->say1(v1a);  \n\n    device->say2(v2a,v2b);\n---------------------------------\n\n\n=== Simple Example Design Structure\n\nThe `simple` example consists of the following files:\n\n---------------------------------\n    Simple.bsv\n    Makefile\n    Top.bsv\n    testsimple.cpp\n---------------------------------\n\nAfter running `make BOARD=zedboard verilog` in the `simple` directory,\nthe `zedboard` project directory is created, populated by the generated files.\n\nA top level `Makefile` is created:\n\n---------------------------------\n    zedboard/Makefile\n---------------------------------\n\nconnectalgen generates wrappers for software-to-hardware interfaces and proxies for hardware-to-software interfaces:\n\n---------------------------------\n    zedboard/sources/mkzynqtop/SimpleIndicationProxy.bsv\n    zedboard/sources/mkzynqtop/SimpleRequestWrapper.bsv\n---------------------------------\n\nCONNECTAL supports Android on Zynq platforms, so connectalgen generates `jni/Android.mk` for `ndk-build`.\n\n---------------------------------\n    zedboard/jni/Android.mk\n    zedboard/jni/Application.mk\n---------------------------------\n\nCONNECTAL generates `jni/Makefile` to compile the software for PCIe platforms (vc707 and kc705).\n\n---------------------------------\n    zedboard/jni/Makefile\n---------------------------------\n\nCONNECTAL generates software proxies for software-to-hardware interfaces and software wrappers for hardware-to-software interfaces:\n\n---------------------------------\n    zedboard/jni/SimpleIndication.h\n    zedboard/jni/SimpleIndication.cpp\n    zedboard/jni/SimpleRequest.cpp\n    zedboard/jni/SimpleRequest.h\n---------------------------------\n\nCONNECTAL also generates `GeneratedTypes.h` for struct and enum types in the processed BSV source files:\n\n---------------------------------\n    zedboard/jni/GeneratedTypes.h\n---------------------------------\n\nCONNECTAL copies in standard and specified constraints files:\n\n---------------------------------\n    zedboard/constraints/design_1_processing_system7_1_0.xdc\n    zedboard/constraints/zedboard.xdc\n---------------------------------\n\nCONNECTAL generates several TCL files to run `vivado`. \n\nThe `board.tcl` file specifies `partname`, `boardname`, and `connectaldir` for the other TCL scripts.\n\n---------------------------------\n    zedboard/board.tcl\n---------------------------------\n\nTo generate an FPGA bit file, run `make bits`. This runs vivado with the `mkzynqtop-impl.tcl` script.\n\n---------------------------------\n    zedboard/mkzynqtop-impl.tcl\n---------------------------------\n\n=== make verilog\n\nCompiling to verilog results in the following verilog files:\n\n---------------------------------\n    zedboard/verilog/top/mkSimpleIndicationProxySynth.v\n    zedboard/verilog/top/mkZynqTop.v\n---------------------------------\n\nVerilog library files referenced in the design are copied for use in synthesis.\n\n---------------------------------\n    zedboard/verilog/top/FIFO1.v\n    ...\n---------------------------------\n\n=== make bits\n\nRunning `make bits` in the zedboard directory results in timing reports:\n\n---------------------------------\n    zedboard/hw/mkzynqtop_post_place_timing_summary.rpt\n    zedboard/hw/mkzynqtop_post_route_timing_summary.rpt\n    zedboard/hw/mkzynqtop_post_route_timing.rpt\n---------------------------------\n\nand some design checkpoints:\n\n---------------------------------\n    zedboard/hw/mkzynqtop_post_synth.dcp\n    zedboard/hw/mkzynqtop_post_place.dcp\n    zedboard/hw/mkzynqtop_post_route.dcp\n---------------------------------\n\nand the FPGA configuration file in .bit and .bin formats:\n\n---------------------------------\n    zedboard/hw/mkZynqTop.bit\n    zedboard/hw/mkZynqTop.bin\n---------------------------------\n\n=== make android_exe\n\nCONNECTAL supports Android 4.0 on Zynq platforms. It generates\n`jni/Android.mk` which is used by `ndk-build` to create a native\nAndroid executable.\n\n---------------------------------\n    make android_exe\n---------------------------------\n\nThis produces the ARM elf executable:\n\n---------------------------------\n    libs/armeabi/android_exe\n---------------------------------\n\n=== make run\n\nFor Zynq platforms,\n\n---------------------------------\n    make run\n---------------------------------\n\nwill copy the Android executable and FPGA configuration file to the\ntarget device, program the FPGA, and run the executable. See\n[run.android](../scripts/run.android) for details.\n\nIt uses `checkip` to determine the IP address of the\ndevice via a USB console connection to the device (it is built/installed\non the host machine from the git repo cambridgehackers/consolable). If the target is\nnot connected to the build machine via USB, specify the IP address of\nthe target manually:\n\n---------------------------------\n    make RUNPARAM=ipaddr run\n---------------------------------\n\nFor PCIe platforms, `make run` programs the FPGA via USB and runs the software locally.\n\nFor bluesim, `make run` invokes bluesim on the design and runs the software locally.\n\n== Shared Memory\n\n=== Shared Memory Hardware\n\nIn order to use shared memory, the hardware design instantiates a DMA module in Top.bsv:\n\n---------------------------------\n   AxiDmaServer#(addrWidth,64) dma <- mkAxiDmaServer(dmaIndicationProxy.ifc, readClients, writeClients);\n---------------------------------\n\nThe `AxiDmaServer` multiplexes read and write requests from the\nclients, translates DMA addresses to physical addresses, initiates bus\ntransactions to memory, and delivers responses to the clients.\n\nDMA requests are specified with respect to \"portal\" memory allocated\nby software and identified by a `pointer`.\n\nRequests and responses are tagged in order to enable pipelining.\n\n---------------------------------\n    typedef struct {\n       SGLId pointer;\n       Bit#(MemOffsetSize) offset;\n       Bit#(8) burstLen;\n       Bit#(6)  tag;\n       } MemRequest deriving (Bits);\n\n    typedef struct {\n       Bit#(dsz) data;\n       Bit#(6) tag;\n       } MemData#(numeric type dsz) deriving (Bits);\n---------------------------------\n\nRead clients implement the `MemReadClient` interface. On response to\nthe read, `burstLen` `MemData` items will be put to the `readData`\ninterface. The design must be ready to consume the data when it is\ndelivered from the memory bus or the system may hang.\n\n---------------------------------\n    interface MemReadClient#(numeric type dsz);\n       interface GetF#(MemRequest)    readReq;\n       interface PutF#(MemData#(dsz)) readData;\n    endinterface\n---------------------------------\n\nWrite clients implement `MemWriteClient`. To complete the transaction,\n`burstLen` data items will be consumed from the `writeData`\ninterace. Upon completion of the request, the specified tag will be\nput to the `writeDone` interface. The data must be available when the\nwrite request is issued to the memory bus or the system may hang.\n\n---------------------------------\n    interface MemWriteClient#(numeric type dsz);\n       interface GetF#(MemRequest)    writeReq;\n       interface GetF#(MemData#(dsz)) writeData;\n       interface PutF#(Bit#(6))       writeDone;\n    endinterface\n---------------------------------\n\nA design may implement `MemReadClient` and `MemWriteClient` interfaces directly, or it may instantiate DmaReadBuffer or DmaWriteBuffer.\n\n The `AxiDmaServer` is configured with physical address translations\nfor each region of memory identified by a `pointer`. A design using\nDMA must export the `DmaConfig` and `DmaIndication` interfaces of the\nDMA server.\n\nHere are the DMA components of [memread_nobuff/Top.bsv](../examples/memread_nobuff/Top.bsv):\n\nInstantiate the design and its interface wrappers and proxies:\n\n---------------------------------\n    MemreadIndicationProxy memreadIndicationProxy <- mkMemreadIndicationProxy(MemreadIndication);\n    Memread memread <- mkMemread(memreadIndicationProxy.ifc);\n    MemreadRequestWrapper memreadRequestWrapper <- mkMemreadRequestWrapper(MemreadRequest,memread.request);\n---------------------------------\n\nCollect the read and write clients:\n\n---------------------------------\n    Vector#(1, MemReadClient#(64)) readClients = cons(memread.dmaClient, nil);\n    Vector#(0, MemReadClient#(64)) writeClients = nil;\n---------------------------------\n\nInstantiate the DMA server and its wrapper and proxy:\n\n---------------------------------\n    DmaIndicationProxy dmaIndicationProxy <- mkDmaIndicationProxy(DmaIndication);\n    AxiDmaServer#(addrWidth,64) dma <- mkAxiDmaServer(dmaIndicationProxy.ifc, readClients, writeClients);\n    DmaConfigWrapper dmaConfigWrapper <- mkDmaConfigWrapper(DmaConfig,dma.request);\n---------------------------------\n\nInclude `DmaConfig` and `DmaIndication` in the portals of the design:\n\n---------------------------------\n    Vector#(4,StdPortal) portals;\n    portals[0] = memreadRequestWrapper.portalIfc;\n    portals[1] = memreadIndicationProxy.portalIfc; \n    portals[2] = dmaConfigWrapper.portalIfc;\n    portals[3] = dmaIndicationProxy.portalIfc; \n---------------------------------\n\nThe code generation tools will then produce the software glue necessary for the shared memory support libraries to initialize the DMA \"library module\" included in the hardware.\n\n=== Shared Memory Software\n\nThe software side instantiates the DmaConfig proxy and the DmaIndication wrapper:\n\n---------------------------------\n    dma = new DmaConfigProxy(IfcNames_DmaConfig);\n    dmaIndication = new DmaIndication(dma, IfcNames_DmaIndication);\n---------------------------------\n\nCall `dma->alloc()` to allocate DMA memory. Each chunk of portal\nmemory is identified by a file descriptor. Portal memory may be shared\nwith other processes. Portal memory is reference counted according to\nthe number of file descriptors associated with it.\n\n---------------------------------\n    PortalAlloc *srcAlloc;\n    dma->alloc(alloc_sz, &srcAlloc);\n---------------------------------\n\nMemory map it to make it accessible to software:\n\n---------------------------------\n    srcBuffer = (unsigned int *)mmap(0, alloc_sz, PROT_READ|PROT_WRITE|PROT_EXEC, MAP_SHARED, srcAlloc->header.fd, 0);\n---------------------------------\n\nCONNECTAL is currently using non-snooped interfaces, so the cache must be flushed and invalidated before hardware accesses portal memory:\n\n---------------------------------\n    dma->dCacheFlushInval(srcAlloc, srcBuffer);\n---------------------------------\n\nCall `dma->reference()` to get a pointer that may be passed to hardware:\n\n---------------------------------\n    unsigned int ref_srcAlloc = dma->reference(srcAlloc);\n---------------------------------\n\nThis also transfers the DMA-to-physical address translation information to the hardware via the `DmaConfig` interface.\n\n---------------------------------\n    device->startRead(ref_srcAlloc, numWords, burstLen, iterCnt);\n---------------------------------\n\n== Notes\n\n*****\nstewart notes\n\nCurrently there are no valid bits and no protections against bursts crossing page boundaries]\n\nThere needs to be a way to synchronize Request actions and DMA reads, and to synchronize DMA writes with Indications, so that the writes complete to the coherence point before the indication is delivered to software. One could imagine an absurdly buffered memory interface and a rather direct path for I/O reads that could get out of order.\n*****\n\ninclude::portalstructure.asciidoc[]\n\n== Index\n"
  },
  {
    "path": "doc/server.md",
    "content": "Data Center Accelerators\n========================\n\nApproach\n--------\n\n * Application process can request a coprocessing tile to be loaded\n * Process startup triggers tile load\n * Tile deactivated when process ends\n\n * Tile manager on the FPGA\n   * Only user of the pins and PCIe/system interface\n   * The tiles export MemClient interfaces, which are connected to a corresponding MemServer for the tile. [draw nifty picture.]\n   * As part of this, prepends tile number onto object ID used to access the MMU in MemServer, providing inter-tile, inter-process access control\n   * Responsible for QoS, Fairness, Arbitration of resource use by tiles.\n\n * For virtualization, device-driver in the host OS controls the actual hardware\n * Device-driver in the guest OS requests resources from the host OS, i.e., a tile\n\n * Misbehaviour in a tile cannot affect other tiles:\n   * PCIe transactions buffered.  If tile logic not ready, then TLP deleted.  \n   * If worried about integrity of bitfile contents, perhaps only load ones that have been signed by an authorized build server\n\nTasks\n-----\n\n * Construct tile manager with fixed per-tile interface ports\n   * Per-tile ports disabled during tile reconfiguration\n * Tile manager configuration and floor planning\n * Partial reconfiguration to load a tile\n * Disable ports without locking PCIe\n * Floor planning.\n * Relocatable tiles?\n * Implement tile loader\n\nTile Interface\n--------------\n\n interface Tile;\n   interface PhysMemSlave portal;\n   interface ReadOnly#(Bool) interrupt;\n\n   interface Vector#(N,MemReadClient) readClients;\n   interface Vector#(N,MemWriteClient) writeClients;\n   interface Pins pins;\n endinterface\n\nNotes\n-----\n\n * The Tile Manager looks like the infra that a Verilog module would plug into, but with fixed configuration.\n\nQuestions\n---------\n\n"
  },
  {
    "path": "doc/syntax.md",
    "content": "\n--Capitalization\n    Foo: Type names, Typeclass names, Interface names, Enum labels,\n        Tagged union labels, Package names\n    foo: bit[..], int, module names, instance names, all variables,\n        all type variables, rule names\n--Package\n    package Package_name ;\n        typedef statements\n        import statements\n        interface declarations\n        module declarations\n    endpackage [: Package_name] \n--Import Statement\n    import Package_name :: * ;\n--Predefined Data Types\n    Bit#(n)\n    Int#(n)  // signed\n    Uint#(n) // unsigned\n    Integer  // static elaboration only\n    Bool\n    String\n    Action\n    ActionValue#(t)\n    Rules\n    Tuple2#(t1, t2) ... Tuple7#(t1,..., t7)\n    int // Int#(32)\n    Nat // Bit#(32)\n    Maybe#(t)\n--Type Definition\n    Type_name\n    Type_name#(type_variable)    // polymorphic type\n--Type Synonym\n    typedef type Type_name[#({type type_var})];\n    example:\n        typedef Bit#(8) Byte;\n        typedef Tuple3#(a, a, a) Triple#(type a);\n--Interface Declaration\n    interface ifc_name;\n        method declarations\n        subinterface declarations\n    endinterface[:ifc_name]\n    interface ifc_name #({type Type_name});\n        method declarations\n        subinterface declarations\n    endinterface[:ifc_name]\n    example:\n        interface MyIfc#(t) ;\n            method Action tick() ;\n            interface FIFO#(t) inbuffer ;\n        endinterface:MyIfc\n--Method Declaration\n    method Type method_name [(Type argument)] ;\n        \n--Module Definition\n    module module_name [# ({parameter})]\n        ({Ifc_type ifc_name*})[provisos] ;\n            module instantiations\n            variable declaration and initializations\n            rules\n            interface/method definitions\n    endmodule [:module_name]\n    * ifc_name optional if only one ifc\n--Module Instantiation\n    Ifc_type ifc_name <- module_name({parameter});\n    Ifc_type ifc_name <- module_name([{parameter,}\n        clocked_by clock_name,\n        reset_by reset_name]);\n    example:\n        Reg#(Time32) state <- mkReg(0);\n--Rules\n    rule rule_name [rule_predicate] ;\n        action statements\n    endrule[: rule_name]\n    rules [: rules_name]\n        rule\n        variable declaration or variable assignment\n    endrules[: rules_name]\n--Action Block\n    action [: action_name] ;\n        action statements\n    endaction [:action_name] \n--Value Method Definition\n    method Type method_name ({parameter})\n        [if (method_predicate)];\n            method body statements\n            return statement\n    endmethod [:method_name]\n\n--Action Method Definition\n    method Action method_name ({parameter})\n        [if (method_predicate)];\n            method body statements\n    endmethod [:method_name] \n--ActionValue Method Definition\n    method ActionValue method_name({parameter})\n        [if (method_predicate)];\n             method body statements\n             return statement\n    endmethod [:method_name]\n--Variable Declaration and Initialization\n    Type {variable_name [= expression ]};\n    example:\n        Integer x = 16, y = 32;\n        int a[20], b[40];\n        Int#(5) xs[2][4] = {{1,2,3,4},\n                            {5,6,7,8}};\n--Variable Assignment\n    variable_name = expression ;\n    example:\n        x = 23 ;\n        b = foo.bar(x);\n--ActionValue Assignment Statement\n    Special <- notation used to perform the action and return the value\n    type identifier <- expression ;\n    identifier <- expression ;\n--Implicit Type Declaration and Initialization\n    let identifier = expression ;\n---if expression is actionvalue method\n    let identifier <-­ expression ;\n    example:\n        let n = valueof(Buffsize);\n        let z <- rndm.get;\n--Register Read and Write\n    register_name <= expression ;\n    example:\n        state <= state + 1 ; // same as: state._write (state.read() + 1)\n--Enumeration\n    typedef enum {{Elements}} Type_name\n        [deriving (Typeclass)];\n    example:\n        typedef enum {Red, White, Blue} Color\n            deriving (Eq, Bits);\n\n--Structure\n    (struct value contains member1 and member2, etc.)\n    typedef struct {Type member1;...;Type memberN}\n        Type_name [#{[numeric] type type_variable}]\n            [deriving (Typeclass)];\n----example:\n    typedef struct {Int x;\n        Int y;} Coord deriving (Eq, Bits);\n----Declaration and initialization of a structure variable\n    Type variable_name = Type{member:expression}\n        Coord c1 = Coord{x:1, y:foo};\n----Update of a structure variable\n    c1.x = c1.x + 5 ;\n----Structure member selection\n    xposition = c1.x ;\n--Tagged Union\n    (union value contains member1 or member2)\n    typedef union tagged {type Member1; ... ;\n        type MemberN;} Type_name [#...[numeric]\n    type type_variable];\n    example:\n        typedef union tagged { void Invalid;\n            int Valid; } MaybeInt;\n---Declaration and initialization of a tagged union\n    Type variable_name = Member expression ;\n        MaybeInt x = tagged Valid 5 ;\n--Pattern Matching\n---Tagged Union\n    tagged Member [ pattern ] \n---Structure\n    tagged Type [ member:pattern ]\n---Tuple\n    tagged {pattern, pattern} \n---Pattern Matching Examples\n-----Pattern matching in a case statement\n    case (f(a)) matches\n        tagged Valid .x : return x;\n        tagged Invalid : return 0;\n    endcase\n-----Pattern matching in an if statement\n    if (x matches tagged Valid .n &&& n > 5...)\n---Pattern Matching Assignment Statement\n    match pattern = expression ;\n    example:\n        Tuple2#(Bits(32) x, Bool y) a_tuple;\n        match {.a, .b} = a_tuple ;\n--Function Definition\n    function type function_name ([{arguments}])\n        [provisos];\n            function body statements\n            return statement\n    endfunction [: function_name]\n\n--Attributes\n    (* {attribute [= expression ]}*)\n---Module Attributes (top­level only)\n    synthesize\n    RST_N = \"string\"\n    CLK = \"string\"\n    always_ready [= \"interface_method\"]\n    always_enabled [= \"interface_method\"]\n    descending urgency = \"{rule_names}\"\n    preempts = \"{rule_names, (list_rule_names)]}\"\n    doc = \"string\"\n---Method Attributes\n    always_ready [= \"interface_method\"]\n    always_enabled [= \"interface_method\"]\n    ready = \"string\"\n    enable = \"string\"\n    result = \"string\"\n    prefix = \"string\"\n    port = \"string\"\n---Interface Attributes\n    always_ready [= \"interface_method\"]\n    always_enabled [= \"interface_method\"]\n---Function Attributes (top­level only)\n    noinline\n---Rule Attributes\n    fire_when_enabled\n    no_implicit_conditions\n    descending_urgency = \"{rule_names}\"\n    preempts \"{rule_names, [(list_rule_names)]}\"\n--System Tasks and Functions\n    $display $write $fopen $fdisplay $fwrite $fgetc $fflush $fclose $ungetc\n    $finish $stop $dumpon $dumpoff $dumpvars $test$plusargs $time $stime\n--Importing C Functions\n    import \"BDPI\" [c_function_name =] function Return_type function_name [{argument}]) [provisos] ;\n--Importing Verilog Modules\n    import \"BVI\" [verilog_module_name] =\n        module [[Type]] module_name [# ({parameter})]\n        ({Ifc_type ifc_name}) [provisos] ;\n            module statements\n            importBVI statements\n    endmodule [: module_name]\n\n----importBVI Statements\n    parameter parameter_name = expression ;\n    port port_name = expression ;\n    default_clock clock_name\n        [(port_name, port_name)][= expression];\n    input_clock clock_name [(port_name,\n        port_name)] = expression;\n    output_clock clock_name\n        (port_name [,port_name]);\n    no_reset;\n    default_reset clock_name ([port_name]) [= expression];\n    input_reset clock_name ([port_name]) = expression;\n    output_reset clock_name ( port_name );\n    ancestor ( clock1, clock2 );\n    same_family ( clock1, clock2 );\n    method [output_port] method_name\n        ({input_ports}) [enable enable_port]\n        [ready ready_port][clocked_by clock_name]    [reset_by clock_name];\n    schedule ({method_name}) operator\n        ({method_name});\n            operators are CF, SB, SBR, and C\n    path (port_name1, port_name2) ;\n        \n--Defined Interfaces\n---Reg\n    interface Reg #(type a_type);\n        method Action _write(a_type x1);\n        method a_type _read();\n    endinterface: Reg\n---PulseWire\n    interface PulseWire;\n        method Action send();\n        method Bool _read();\n    endinterface\n---Wire\n    typedef Reg#(a_type) Wire#(type a_type);\n--Defined Modules\n---Reg\n    module mkReg#(a_type resetval) (Reg#(a_type));\n    module mkRegU(Reg#(a_type));\n    module mkRegA#(a_type resetval)(Reg#(a_type));\n---Wire\n    module mkWire(Wire#(a_type));\n---BypassWire\n    module mkBypassWire(Wire#(a_type));\n---DWire\n    module mkDWire#(a_type defaultval) (Wire#(a_type));\n---PulseWire\n    module mkPulseWire(PulseWire);\n\n--Library Packages \n---FIFOFs (import FIFOF::*;)\n    see LRM for additional FIFOs\n----Interface\n    interface FIFOF #(type a_type);\n        method Action enq(a_type x1);\n        method Action deq();\n        method a_type first();\n        method Bool notFull();\n        method Bool notEmpty();\n        method Action clear();\n    endinterface: FIFOF\n----Modules\n    module mkFIFOF# (FIFO#(a_type)) ;\n    module mkFIFOF1#(FIFO#(a_type));\n    module mkSizedFIFOF#(Integer n)(FIFO#(a_type)) ;\n    module mkLFIFOF#(FIFO#(a_type));\n---Get/Put (importGetPut::*;)\n----Interfaces\n    interface Get#(type a_type);\n        method ActionValue#(a_type) get();\n    endinterface: Get\n    interface Put#(type a_type);\n        method Action put(a_type x1);\n    endinterface: Put\n----Type\n    typedef Tuple2#( Get#(a_type), Put#(a_type) )\n        GetPut#(type a_type);\n----Connectable (import Connectable::*;)\n----Typeclass\n    typeclass Connectable#(type a , type b) ;\n----Module\n    mkConnection#(a x1, b x2) ;\n        \n---Client/Server (import ClientServer::*;)\n----Interfaces\n    interface Client#(type req_type, type resp_type);\n        interface Get#(req_type) request;\n        interface Put#(resp_type) response;\n    endinterface: Client\n    interface Server#(type req_type, type resp_type);\n        interface Put#(req_type) request;\n        interface Get#(resp_type) response;\n    endinterface: Server\n----Type\n    typedef Tuple2#(Client#(req_type, resp_type),\n    Server#(req_type,resp_type))\n        ClientServer#(type req_type, type resp_type);\n\n--BSV Example\n    package Counter ;\n    interface Counter#(type count_t);\n        method count_t read();\n        method Action load(count_t newval);\n        method Action increment();\n        method Action decrement();\n    endinterface\n    module mkCounter(Counter#(count_t)) provisos(Arith#(count_t), Bits#(count_t, count_t_sz));\n        Reg#(count_t) value <- mkReg(0);\n        PulseWire increment_called <- mkPulseWire();\n        PulseWire decrement_called <- mkPulseWire();\n        rule do_increment(increment_called && ! decrement_called);\n            value <= value + 1;\n        endrule\n        rule do_decrement(!increment_called && decrement_called);\n            value <= value ­ 1;\n        endrule\n        method count_t read();\n            return value;\n        endmethod\n        method Action load(count_t newval);\n            value <= newval;\n        endmethod\n        method Action increment();\n            increment_called.send();\n        endmethod\n        method Action decrement();\n            decrement_called.send();\n        endmethod\n    endmodule endpackage: Counter\n"
  },
  {
    "path": "docker/Dockerfile",
    "content": "FROM bsc-contrib:latest\nADD . /build/\nRUN apt update; apt-get -y install jq python python-ply rsync awscli\nENV PATH /opt/bluespec/bin:$PATH\nENV BLUESPECDIR /opt/bluespec/lib\n"
  },
  {
    "path": "drivers/awsf1portal/Makefile",
    "content": "\n# On Centos: sudo yum install kernel-headers\n\nV?=0\nifeq ($(V),0)\nQ=@\nelse\nQ=\nendif\nCURRENTDIR := $(PWD)\nCONNECTALDIR ?= $(CURRENTDIR)/../..\ninclude $(CONNECTALDIR)/Makefile.version\n\npcieportal-objs := portal.o libxdma.o xdma_cdev.o cdev_ctrl.o cdev_events.o cdev_sgdma.o cdev_xvc.o cdev_bypass.o xdma_mod.o\n\nTARGET_MODULE:=pcieportal\nobj-m += pcieportal.o\n\nPKG_NAME?=connectal\n# DKMS only looks in /usr/src\nPREFIX?=/usr\nKVERSION=$(shell uname -r)\nKROOT=/lib/modules/$(KVERSION)/build\nexport BS_MOD_DIR=$(DESTDIR)/lib/modules/$(KVERSION)/connectal\n\n.PHONY: default\ndefault: pcieportal.ko ../portalmem/portalmem.ko\n\nEXTRA_CFLAGS := -I$(CONNECTALDIR)/drivers/pciportal -I$(CONNECTALDIR)/cpp -I$(CONNECTALDIR) -I$(CONNECTALDIR)/drivers/portalmem -I$(CONNECTALDIR)/generated/cpp\ncflags-y += -I$(PWD)\n\n../portalmem/portalmem.ko: ../portalmem/portalmem.c\n\tcd ../portalmem; make\n\ndriverversion.h:\n\tVERSION=$(VERSION) echo \"#define DRIVER_VERSION \\\"$$VERSION\\\"\" > driverversion.h\n\npcieportal.ko: portal.c pcieportal.h driverversion.h\n\t$(Q)$(MAKE) -C $(KROOT) M=$(PWD) modules\n\n.PHONY: modules_check\nmodules_check:\n\t$(Q)$(MAKE) -C $(KROOT) C=2 M=$(PWD) modules\n\n.PHONY: install\ninstall: pcieportal.ko\n\tinstall -d -m755 $(BS_MOD_DIR)\n\tinstall -m644 pcieportal.ko $(BS_MOD_DIR)\n\tinstall -m644 ../portalmem/portalmem.ko $(BS_MOD_DIR)\nifeq (\"$(DESTDIR)\", \"\")\n\tdepmod\nendif\n\n.PHONY: uninstall\nuninstall:\n\trm -f $(BS_MOD_DIR)/pcieportal.ko\n\trmdir --ignore-fail-on-non-empty $(BS_MOD_DIR)\nifeq (\"$(DESTDIR)\", \"\")\n\tdepmod\nendif\n\n.PHONY: clean\nclean:\n\t$(Q)$(MAKE) -C $(KROOT) M=$(PWD) clean\n\tcd ../portalmem; make clean\n\n.PHONY: distclean\ndistclean: clean\n\n.PHONY: rmmod\nrmmod:\n\trmmod portalmem || true\n\trmmod pcieportal || true\n\n.PHONY: insmod\ninsmod: rmmod\n\tinsmod pcieportal.ko\n\t-chmod agu+rw /dev/portal*\n\tinsmod ../portalmem/portalmem.ko\n\tchmod agu+rw /dev/portalmem\n\n\nPCIEPORTAL_SOURCE=$(wildcard portal.c portal_internal.h pcieportal.h version.h cdev*.[ch] *xdma*.[ch] driverversion.h)\nPORTALMEM_SOURCE=$(wildcard ../portalmem/*.[ch])\nCONNECTAL_HEADERS=$(addprefix ../../cpp/, portal.h portalKernel.h dmaSendFd.h)\nGENERATED_SOURCE=$(wildcard ../../generated/cpp/*.[ch])\n\n.PHONY: install-dkms\ninstall-dkms:\n\trm -f driverversion.h\n\tmake driverversion.h\n\tmkdir -p $(DESTDIR)$(PREFIX)/src/$(PKG_NAME)-$(VERSION)\n\tsed \"s/@VERSION@/$(VERSION)/\" dkms.conf | sed \"s/@PKG_NAME@/$(PKG_NAME)/\" > dkms.conf.out\n\tsed \"s/@VERSION@/$(VERSION)/\" Makefile.dkms > Makefile.dkms.out\n\tcp -fv dkms.conf.out $(DESTDIR)$(PREFIX)/src/$(PKG_NAME)-$(VERSION)/dkms.conf\n\tcp -fv Makefile.dkms.out $(DESTDIR)$(PREFIX)/src/$(PKG_NAME)-$(VERSION)/Makefile\n\tcp -fv $(PCIEPORTAL_SOURCE) $(DESTDIR)$(PREFIX)/src/$(PKG_NAME)-$(VERSION)\n\tcp -fv $(PORTALMEM_SOURCE) $(DESTDIR)$(PREFIX)/src/$(PKG_NAME)-$(VERSION)\n\tcp -fv $(CONNECTAL_HEADERS) $(DESTDIR)$(PREFIX)/src/$(PKG_NAME)-$(VERSION)\n\tcp -fv $(GENERATED_SOURCE) $(DESTDIR)$(PREFIX)/src/$(PKG_NAME)-$(VERSION)\n\tsed -i 's|drivers/portalmem/||' $(DESTDIR)$(PREFIX)/src/$(PKG_NAME)-$(VERSION)/*.[ch]\n\tsed -i 's|drivers/pcieportal/||' $(DESTDIR)$(PREFIX)/src/$(PKG_NAME)-$(VERSION)/*.[ch]\n\tsed -i 's|drivers/zynqportal/||' $(DESTDIR)$(PREFIX)/src/$(PKG_NAME)-$(VERSION)/*.[ch]\n\tsed -i 's|../../cpp/||g' $(DESTDIR)$(PREFIX)/src/$(PKG_NAME)-$(VERSION)/*.[ch]\n\ntest-dkms:\n\trm -fr test-dkms\n\tmake DESTDIR=dkms install-dkms\n\tcd dkms$(PREFIX)/src/$(PKG_NAME)-$(VERSION); make -C $(KROOT) M=$(PWD)/dkms$(PREFIX)/src/$(PKG_NAME)-$(VERSION) modules\n\trm -fr test-dkms\n"
  },
  {
    "path": "drivers/awsf1portal/Makefile.dkms",
    "content": "obj-m += pcieportal.o\nobj-m += portalmem.o\n\npcieportal-objs := portal.o libxdma.o xdma_cdev.o cdev_ctrl.o cdev_events.o cdev_sgdma.o cdev_xvc.o cdev_bypass.o xdma_mod.o\npcieportal.ko: driverversion.h\n\ndriverversion.h:\n\techo \"#define DRIVER_VERSION \\\"@VERSION@\\\"\" > driverversion.h\n"
  },
  {
    "path": "drivers/awsf1portal/cdev_bypass.c",
    "content": "/*******************************************************************************\n *\n * Xilinx XDMA IP Core Linux Driver\n * Copyright(c) 2015 - 2017 Xilinx, Inc.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms and conditions of the GNU General Public License,\n * version 2, as published by the Free Software Foundation.\n *\n * This program is distributed in the hope it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\n * more details.\n *\n * You should have received a copy of the GNU General Public License along\n * with this program.  If not, see <http://www.gnu.org/licenses/>.\n *\n * The full GNU General Public License is included in this distribution in\n * the file called \"LICENSE\".\n *\n * Karen Xie <karen.xie@xilinx.com>\n *\n ******************************************************************************/\n\n#include \"libxdma_api.h\"\n#include \"xdma_cdev.h\"\n\n#define write_register(v,mem,off) iowrite32(v, mem)\n\nstatic int copy_desc_data(struct xdma_transfer *transfer, char __user *buf,\n\t\tsize_t *buf_offset, size_t buf_size)\n{\n\tint i;\n\tint copy_err;\n\tint rc = 0;\n\n\tBUG_ON(!buf);\n\tBUG_ON(!buf_offset);\n\n\t/* Fill user buffer with descriptor data */\n\tfor (i = 0; i < transfer->desc_num; i++) {\n\t\tif (*buf_offset + sizeof(struct xdma_desc) <= buf_size) {\n\t\t\tcopy_err = copy_to_user(&buf[*buf_offset],\n\t\t\t\ttransfer->desc_virt + i,\n\t\t\t\tsizeof(struct xdma_desc));\n\n\t\t\tif (copy_err) {\n\t\t\t\tdbg_sg(\"Copy to user buffer failed\\n\");\n\t\t\t\t*buf_offset = buf_size;\n\t\t\t\trc = -EINVAL;\n\t\t\t} else {\n\t\t\t\t*buf_offset += sizeof(struct xdma_desc);\n\t\t\t}\n\t\t} else {\n\t\t\trc = -ENOMEM;\n\t\t}\n\t}\n\n\treturn rc;\n}\n\nstatic ssize_t char_bypass_read(struct file *file, char __user *buf,\n\t\tsize_t count, loff_t *pos)\n{\n\tstruct xdma_dev *xdev;\n\tstruct xdma_engine *engine;\n\tstruct xdma_cdev *xcdev = (struct xdma_cdev *)file->private_data;\n\tstruct xdma_transfer *transfer;\n\tstruct list_head *idx;\n\tsize_t buf_offset = 0;\n\tint rc = 0;\n\n\trc = xcdev_check(__func__, xcdev, 1);\n\tif (rc < 0)\n\t\treturn rc;\n\txdev = xcdev->xdev;\n\tengine = xcdev->engine;\n\n\tdbg_sg(\"In char_bypass_read()\\n\");\n\n\tif (count & 3) {\n\t\tdbg_sg(\"Buffer size must be a multiple of 4 bytes\\n\");\n\t\treturn -EINVAL;\n\t}\n\n\tif (!buf) {\n\t\tdbg_sg(\"Caught NULL pointer\\n\");\n\t\treturn -EINVAL;\n\t}\n\n\tif (xdev->bypass_bar_idx < 0) {\n\t\tdbg_sg(\"Bypass BAR not present - unsupported operation\\n\");\n\t\treturn -ENODEV;\n\t}\n\n\tspin_lock(&engine->lock);\n\n\tif (!list_empty(&engine->transfer_list)) {\n\t\tlist_for_each(idx, &engine->transfer_list) {\n\t\t\ttransfer = list_entry(idx, struct xdma_transfer, entry);\n\n\t\t\trc = copy_desc_data(transfer, buf, &buf_offset, count);\n\t\t}\n\t}\n\n\tspin_unlock(&engine->lock);\n\n\tif (rc < 0)\n\t\treturn rc;\n\telse\n\t\treturn buf_offset;\n}\n\nstatic ssize_t char_bypass_write(struct file *file, const char __user *buf,\n\t\tsize_t count, loff_t *pos)\n{\n\tstruct xdma_dev *xdev;\n\tstruct xdma_engine *engine;\n\tstruct xdma_cdev *xcdev = (struct xdma_cdev *)file->private_data;\n\n\tu32 desc_data;\n\tu32 *bypass_addr;\n\tsize_t buf_offset = 0;\n\tint rc = 0;\n\tint copy_err;\n\n\trc = xcdev_check(__func__, xcdev, 1);\n\tif (rc < 0)\n\t\treturn rc;\n\txdev = xcdev->xdev;\n\tengine = xcdev->engine;\n\n\tif (count & 3) {\n\t\tdbg_sg(\"Buffer size must be a multiple of 4 bytes\\n\");\n\t\treturn -EINVAL;\n\t}\n\n\tif (!buf) {\n\t\tdbg_sg(\"Caught NULL pointer\\n\");\n\t\treturn -EINVAL;\n\t}\n\n\tif (xdev->bypass_bar_idx < 0) {\n\t\tdbg_sg(\"Bypass BAR not present - unsupported operation\\n\");\n\t\treturn -ENODEV;\n\t}\n\n\tdbg_sg(\"In char_bypass_write()\\n\");\n\n\tspin_lock(&engine->lock);\n\n\t/* Write descriptor data to the bypass BAR */\n\tbypass_addr = (u32 *)xdev->bar[xdev->bypass_bar_idx];\n\tbypass_addr += engine->bypass_offset;\n\twhile (buf_offset < count) {\n\t\tcopy_err = copy_from_user(&desc_data, &buf[buf_offset],\n\t\t\tsizeof(u32));\n\t\tif (!copy_err) {\n\t\t\twrite_register(desc_data, bypass_addr, bypass_addr - engine->bypass_offset);\n\t\t\tbuf_offset += sizeof(u32);\n\t\t\trc = buf_offset;\n\t\t} else {\n\t\t\tdbg_sg(\"Error reading data from userspace buffer\\n\");\n\t\t\trc = -EINVAL;\n\t\t\tbreak;\n\t\t}\n\t}\n\n\tspin_unlock(&engine->lock);\n\n\n\treturn rc;\n}\n\n\n/*\n * character device file operations for bypass operation\n */\n\nstatic const struct file_operations bypass_fops = {\n\t.owner = THIS_MODULE,\n\t.open = char_open,\n\t.release = char_close,\n\t.read = char_bypass_read,\n\t.write = char_bypass_write,\n\t.mmap = bridge_mmap,\n};\n\nvoid cdev_bypass_init(struct xdma_cdev *xcdev)\n{\n        cdev_init(&xcdev->cdev, &bypass_fops);\n}\n"
  },
  {
    "path": "drivers/awsf1portal/cdev_ctrl.c",
    "content": "/*******************************************************************************\n *\n * Xilinx XDMA IP Core Linux Driver\n * Copyright(c) 2015 - 2017 Xilinx, Inc.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms and conditions of the GNU General Public License,\n * version 2, as published by the Free Software Foundation.\n *\n * This program is distributed in the hope it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\n * more details.\n *\n * You should have received a copy of the GNU General Public License along\n * with this program.  If not, see <http://www.gnu.org/licenses/>.\n *\n * The full GNU General Public License is included in this distribution in\n * the file called \"LICENSE\".\n *\n * Karen Xie <karen.xie@xilinx.com>\n *\n ******************************************************************************/\n#define pr_fmt(fmt)     KBUILD_MODNAME \":%s: \" fmt, __func__\n\n#include <linux/ioctl.h>\n#include \"version.h\"\n#include \"xdma_cdev.h\"\n#include \"cdev_ctrl.h\"\n\n/*\n * character device file operations for control bus (through control bridge)\n */\nstatic ssize_t char_ctrl_read(struct file *fp, char __user *buf, size_t count,\n\t\tloff_t *pos)\n{\n\tstruct xdma_cdev *xcdev = (struct xdma_cdev *)fp->private_data;\n\tstruct xdma_dev *xdev;\n\tvoid *reg;\n\tu32 w;\n\tint rv;\n\n\trv = xcdev_check(__func__, xcdev, 0);\n\tif (rv < 0)\n\t\treturn rv;\t\n\txdev = xcdev->xdev;\n\n\t/* only 32-bit aligned and 32-bit multiples */\n\tif (*pos & 3)\n\t\treturn -EPROTO;\n\t/* first address is BAR base plus file position offset */\n\treg = xdev->bar[xcdev->bar] + *pos;\n\t//w = read_register(reg);\n\tw = ioread32(reg);\n\tdbg_sg(\"char_ctrl_read(@%p, count=%ld, pos=%d) value = 0x%08x\\n\", reg,\n\t\t(long)count, (int)*pos, w);\n\trv = copy_to_user(buf, &w, 4);\n\tif (rv)\n\t\tdbg_sg(\"Copy to userspace failed but continuing\\n\");\n\n\t*pos += 4;\n\treturn 4;\n}\n\nstatic ssize_t char_ctrl_write(struct file *file, const char __user *buf,\n\t\t\tsize_t count, loff_t *pos)\n{\n\tstruct xdma_cdev *xcdev = (struct xdma_cdev *)file->private_data;\n\tstruct xdma_dev *xdev;\n\tvoid *reg;\n\tu32 w;\n\tint rv;\n\n\trv = xcdev_check(__func__, xcdev, 0);\n\tif (rv < 0)\n\t\treturn rv;\t\n\txdev = xcdev->xdev;\n\n\t/* only 32-bit aligned and 32-bit multiples */\n\tif (*pos & 3)\n\t\treturn -EPROTO;\n\n\t/* first address is BAR base plus file position offset */\n\treg = xdev->bar[xcdev->bar] + *pos;\n\trv = copy_from_user(&w, buf, 4);\n\tif (rv) {\n\t\tpr_info(\"copy from user failed %d/4, but continuing.\\n\", rv);\n\t}\n\n\tdbg_sg(\"char_ctrl_write(0x%08x @%p, count=%ld, pos=%d)\\n\", w, reg,\n\t\t(long)count, (int)*pos);\n\t//write_register(w, reg);\n\tiowrite32(w, reg);\n\t*pos += 4;\n\treturn 4;\n}\n\nstatic long version_ioctl(struct xdma_cdev *xcdev, void __user *arg)\n{\n\tstruct xdma_ioc_info obj;\n\tstruct xdma_dev *xdev = xcdev->xdev;\n\tint rv;\n\n\trv = copy_from_user((void *)&obj, arg, sizeof(struct xdma_ioc_info));\n\tif (rv) {\n\t\tpr_info(\"copy from user failed %d/%ld.\\n\",\n\t\t\trv, sizeof(struct xdma_ioc_info));\n\t\treturn -EFAULT;\n\t}\n\tmemset(&obj, 0, sizeof(obj));\n\tobj.vendor = xdev->pdev->vendor;\n\tobj.device = xdev->pdev->device;\n\tobj.subsystem_vendor = xdev->pdev->subsystem_vendor;\n\tobj.subsystem_device = xdev->pdev->subsystem_device;\n\tobj.feature_id = xdev->feature_id;\n\tobj.driver_version = DRV_MOD_VERSION_NUMBER;\n\tobj.domain = 0;\n\tobj.bus = PCI_BUS_NUM(xdev->pdev->devfn);\n\tobj.dev = PCI_SLOT(xdev->pdev->devfn);\n\tobj.func = PCI_FUNC(xdev->pdev->devfn);\n\tif (copy_to_user(arg, &obj, sizeof(struct xdma_ioc_info)))\n\t\treturn -EFAULT;\n\treturn 0;\n}\n\nlong char_ctrl_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)\n{\n\tstruct xdma_cdev *xcdev = (struct xdma_cdev *)filp->private_data;\n\tstruct xdma_dev *xdev;\n\tstruct xdma_ioc_base ioctl_obj;\n\tlong result = 0;\n\tint rv;\n\n\trv = xcdev_check(__func__, xcdev, 0);\n\tif (rv < 0)\n\t\treturn rv;\t\n\txdev = xcdev->xdev;\n\n\tpr_info(\"cmd 0x%x, xdev 0x%p, pdev 0x%p.\\n\", cmd, xdev, xdev->pdev);\n\n\tif (_IOC_TYPE(cmd) != XDMA_IOC_MAGIC) {\n\t\tpr_err(\"cmd %u, bad magic 0x%x/0x%x.\\n\",\n\t\t\t cmd, _IOC_TYPE(cmd), XDMA_IOC_MAGIC);\n\t\treturn -ENOTTY;\n\t}\n\n\tif (_IOC_DIR(cmd) & _IOC_READ) {\n#if (LINUX_VERSION_CODE < KERNEL_VERSION(5,0,0)) && !(defined(RHEL_MAJOR) && RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(8,0))\n\t\tresult = !access_ok(VERIFY_READ, (void __user *)arg, _IOC_SIZE(cmd));\n#else\n\t\tresult = !access_ok((void __user *)arg, _IOC_SIZE(cmd));\n#endif\n\t} else if (_IOC_DIR(cmd) & _IOC_WRITE)\n#if (LINUX_VERSION_CODE < KERNEL_VERSION(5,0,0)) && !(defined(RHEL_MAJOR) && RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(8,0))\n\t\tresult =  !access_ok(VERIFY_WRITE, (void __user *)arg, _IOC_SIZE(cmd));\n#else\n\t\tresult =  !access_ok((void __user *)arg, _IOC_SIZE(cmd));\n#endif\n\tif (result) {\n\t\tpr_err(\"bad access %ld.\\n\", result);\n\t\treturn -EFAULT;\n\t}\n\n\tswitch (cmd) {\n\tcase XDMA_IOCINFO:\n\t\tif (copy_from_user((void *)&ioctl_obj, (void *) arg,\n\t\t\t sizeof(struct xdma_ioc_base))) {\n\t\t\tpr_err(\"copy_from_user failed.\\n\");\n\t\t\treturn -EFAULT;\n\t\t}\n\n\t\tif (ioctl_obj.magic != XDMA_XCL_MAGIC) {\n\t\t\tpr_err(\"magic 0x%x !=  XDMA_XCL_MAGIC (0x%x).\\n\",\n\t\t\t\tioctl_obj.magic, XDMA_XCL_MAGIC);\n\t\t\treturn -ENOTTY;\n\t\t}\n\n\t\treturn version_ioctl(xcdev, (void __user *)arg);\n\tcase XDMA_IOCOFFLINE:\n\t\tif (!xdev) {\n\t\t\tpr_info(\"cmd %u, xdev NULL.\\n\", cmd);\n\t\t\treturn -EINVAL;\n\t\t}\n\t\txdma_device_offline(xdev->pdev, xdev);\n\t\tbreak;\n\tcase XDMA_IOCONLINE:\n\t\tif (!xdev) {\n\t\t\tpr_info(\"cmd %u, xdev NULL.\\n\", cmd);\n\t\t\treturn -EINVAL;\n\t\t}\n\t\txdma_device_online(xdev->pdev, xdev);\n\t\tbreak;\n\tdefault:\n\t\tpr_err(\"UNKNOWN ioctl cmd 0x%x.\\n\", cmd);\n\t\treturn -ENOTTY;\n\t}\n\treturn 0;\n}\n\n/* maps the PCIe BAR into user space for memory-like access using mmap() */\nint bridge_mmap(struct file *file, struct vm_area_struct *vma)\n{\n\tstruct xdma_dev *xdev;\n\tstruct xdma_cdev *xcdev = (struct xdma_cdev *)file->private_data;\n\tunsigned long off;\n\tunsigned long phys;\n\tunsigned long vsize;\n\tunsigned long psize;\n\tint rv;\n\n\trv = xcdev_check(__func__, xcdev, 0);\n\tif (rv < 0)\n\t\treturn rv;\t\n\txdev = xcdev->xdev;\n\n\toff = vma->vm_pgoff << PAGE_SHIFT;\n\t/* BAR physical address */\n\tphys = pci_resource_start(xdev->pdev, xcdev->bar) + off;\n\tvsize = vma->vm_end - vma->vm_start;\n\t/* complete resource */\n\tpsize = pci_resource_end(xdev->pdev, xcdev->bar) -\n\t\tpci_resource_start(xdev->pdev, xcdev->bar) + 1 - off;\n\n\tdbg_sg(\"mmap(): xcdev = 0x%08lx\\n\", (unsigned long)xcdev);\n\tdbg_sg(\"mmap(): cdev->bar = %d\\n\", xcdev->bar);\n\tdbg_sg(\"mmap(): xdev = 0x%p\\n\", xdev);\n\tdbg_sg(\"mmap(): pci_dev = 0x%08lx\\n\", (unsigned long)xdev->pdev);\n\n\tdbg_sg(\"off = 0x%lx\\n\", off);\n\tdbg_sg(\"start = 0x%llx\\n\",\n\t\t(unsigned long long)pci_resource_start(xdev->pdev,\n\t\txcdev->bar));\n\tdbg_sg(\"phys = 0x%lx\\n\", phys);\n\n\tif (vsize > psize)\n\t\treturn -EINVAL;\n\t/*\n\t * pages must not be cached as this would result in cache line sized\n\t * accesses to the end point\n\t */\n\tvma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);\n\t/*\n\t * prevent touching the pages (byte access) for swap-in,\n\t * and prevent the pages from being swapped out\n\t */\n\tvma->vm_flags |= VMEM_FLAGS;\n\t/* make MMIO accessible to user space */\n\trv = io_remap_pfn_range(vma, vma->vm_start, phys >> PAGE_SHIFT,\n\t\t\tvsize, vma->vm_page_prot);\n\tdbg_sg(\"vma=0x%p, vma->vm_start=0x%lx, phys=0x%lx, size=%lu = %d\\n\",\n\t\tvma, vma->vm_start, phys >> PAGE_SHIFT, vsize, rv);\n\n\tif (rv)\n\t\treturn -EAGAIN;\n\treturn 0;\n}\n\n/*\n * character device file operations for control bus (through control bridge)\n */\nstatic const struct file_operations ctrl_fops = {\n\t.owner = THIS_MODULE,\n\t.open = char_open,\n\t.release = char_close,\n\t.read = char_ctrl_read,\n\t.write = char_ctrl_write,\n\t.mmap = bridge_mmap,\n\t.unlocked_ioctl = char_ctrl_ioctl,\n};\n\nvoid cdev_ctrl_init(struct xdma_cdev *xcdev)\n{\n\tcdev_init(&xcdev->cdev, &ctrl_fops);\n}\n"
  },
  {
    "path": "drivers/awsf1portal/cdev_ctrl.h",
    "content": "/*******************************************************************************\n *\n * Xilinx XDMA IP Core Linux Driver\n * Copyright(c) 2015 - 2017 Xilinx, Inc.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms and conditions of the GNU General Public License,\n * version 2, as published by the Free Software Foundation.\n *\n * This program is distributed in the hope it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\n * more details.\n *\n * You should have received a copy of the GNU General Public License along\n * with this program.  If not, see <http://www.gnu.org/licenses/>.\n *\n * The full GNU General Public License is included in this distribution in\n * the file called \"LICENSE\".\n *\n * Karen Xie <karen.xie@xilinx.com>\n *\n ******************************************************************************/\n#ifndef _XDMA_IOCALLS_POSIX_H_\n#define _XDMA_IOCALLS_POSIX_H_\n\n#include <linux/ioctl.h>\n\n/* Use 'x' as magic number */\n#define XDMA_IOC_MAGIC\t'x'\n/* XL OpenCL X->58(ASCII), L->6C(ASCII), O->0 C->C L->6C(ASCII); */\n#define XDMA_XCL_MAGIC 0X586C0C6C\n\n/*\n * S means \"Set\" through a ptr,\n * T means \"Tell\" directly with the argument value\n * G means \"Get\": reply by setting through a pointer\n * Q means \"Query\": response is on the return value\n * X means \"eXchange\": switch G and S atomically\n * H means \"sHift\": switch T and Q atomically\n *\n * _IO(type,nr)\t\t    no arguments\n * _IOR(type,nr,datatype)   read data from driver\n * _IOW(type,nr.datatype)   write data to driver\n * _IORW(type,nr,datatype)  read/write data\n *\n * _IOC_DIR(nr)\t\t    returns direction\n * _IOC_TYPE(nr)\t    returns magic\n * _IOC_NR(nr)\t\t    returns number\n * _IOC_SIZE(nr)\t    returns size\n */\n\nenum XDMA_IOC_TYPES {\n\tXDMA_IOC_NOP,\n\tXDMA_IOC_INFO,\n\tXDMA_IOC_OFFLINE,\n\tXDMA_IOC_ONLINE,\n\tXDMA_IOC_MAX\n};\n\nstruct xdma_ioc_base {\n\tunsigned int magic;\n\tunsigned int command;\n};\n\nstruct xdma_ioc_info {\n        struct xdma_ioc_base\tbase;\n        unsigned short\t\tvendor;\n        unsigned short\t\tdevice;\n        unsigned short\t\tsubsystem_vendor;\n        unsigned short\t\tsubsystem_device;\n        unsigned int\t\tdma_engine_version;\n        unsigned int\t\tdriver_version;\n        unsigned long long \tfeature_id;\n\tunsigned short\t\tdomain;\n\tunsigned char\t\tbus;\n\tunsigned char\t\tdev;\n\tunsigned char\t\tfunc;\n};\n\n/* IOCTL codes */\n#define XDMA_IOCINFO\t\t_IOWR(XDMA_IOC_MAGIC, XDMA_IOC_INFO, \\\n\t\t\t\t\tstruct xdma_ioc_info)\n#define XDMA_IOCOFFLINE\t\t_IO(XDMA_IOC_MAGIC, XDMA_IOC_OFFLINE)\n#define XDMA_IOCONLINE\t\t_IO(XDMA_IOC_MAGIC, XDMA_IOC_ONLINE)\n\n#define IOCTL_XDMA_ADDRMODE_SET\t_IOW('q', 4, int)\n#define IOCTL_XDMA_ADDRMODE_GET\t_IOR('q', 5, int)\n#define IOCTL_XDMA_ALIGN_GET\t_IOR('q', 6, int)\n\n#endif /* _XDMA_IOCALLS_POSIX_H_ */\n"
  },
  {
    "path": "drivers/awsf1portal/cdev_events.c",
    "content": "/*******************************************************************************\n *\n * Xilinx XDMA IP Core Linux Driver\n * Copyright(c) 2015 - 2017 Xilinx, Inc.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms and conditions of the GNU General Public License,\n * version 2, as published by the Free Software Foundation.\n *\n * This program is distributed in the hope it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\n * more details.\n *\n * You should have received a copy of the GNU General Public License along\n * with this program.  If not, see <http://www.gnu.org/licenses/>.\n *\n * The full GNU General Public License is included in this distribution in\n * the file called \"LICENSE\".\n *\n * Karen Xie <karen.xie@xilinx.com>\n *\n ******************************************************************************/\n#define pr_fmt(fmt)     KBUILD_MODNAME \":%s: \" fmt, __func__\n\n#include \"xdma_cdev.h\"\n\n/*\n * character device file operations for events\n */\nstatic ssize_t char_events_read(struct file *file, char __user *buf,\n\t\tsize_t count, loff_t *pos)\n{\n\tint rv;\n\tstruct xdma_user_irq *user_irq;\n\tstruct xdma_cdev *xcdev = (struct xdma_cdev *)file->private_data;\n\tu32 events_user;\n\tunsigned long flags;\n\n\trv = xcdev_check(__func__, xcdev, 0);\n\tif (rv < 0)\n\t\treturn rv;\t\n\tuser_irq = xcdev->user_irq;\n\tif (!user_irq) {\n\t\tpr_info(\"xcdev 0x%p, user_irq NULL.\\n\", xcdev);\n\t\treturn -EINVAL;\n\t}\n\n\tif (count != 4)\n\t\treturn -EPROTO;\n\n\tif (*pos & 3)\n\t\treturn -EPROTO;\n\n\t/*\n\t * sleep until any interrupt events have occurred,\n\t * or a signal arrived\n\t */\n\trv = wait_event_interruptible(user_irq->events_wq,\n\t\t\tuser_irq->events_irq != 0);\n\tif (rv)\n\t\tdbg_sg(\"wait_event_interruptible=%d\\n\", rv);\n\n\t/* wait_event_interruptible() was interrupted by a signal */\n\tif (rv == -ERESTARTSYS)\n\t\treturn -ERESTARTSYS;\n\n\t/* atomically decide which events are passed to the user */\n\tspin_lock_irqsave(&user_irq->events_lock, flags);\n\tevents_user = user_irq->events_irq;\n\tuser_irq->events_irq = 0;\n\tspin_unlock_irqrestore(&user_irq->events_lock, flags);\n\n\trv = copy_to_user(buf, &events_user, 4);\n\tif (rv)\n\t\tdbg_sg(\"Copy to user failed but continuing\\n\");\n\n\treturn 4;\n}\n\nstatic unsigned int char_events_poll(struct file *file, poll_table *wait)\n{\n\tstruct xdma_user_irq *user_irq;\n\tstruct xdma_cdev *xcdev = (struct xdma_cdev *)file->private_data;\n\tunsigned long flags;\n\tunsigned int mask = 0;\n\tint rv;\n\n\trv = xcdev_check(__func__, xcdev, 0);\n\tif (rv < 0)\n\t\treturn rv;\t\n\tuser_irq = xcdev->user_irq;\n\tif (!user_irq) {\n\t\tpr_info(\"xcdev 0x%p, user_irq NULL.\\n\", xcdev);\n\t\treturn -EINVAL;\n\t}\n\n\tpoll_wait(file, &user_irq->events_wq,  wait);\n\n\tspin_lock_irqsave(&user_irq->events_lock, flags);\n\tif (user_irq->events_irq)\n\t\tmask = POLLIN | POLLRDNORM;\t/* readable */\n\n\tspin_unlock_irqrestore(&user_irq->events_lock, flags);\n\n\treturn mask;\n}\n\n/*\n * character device file operations for the irq events\n */\nstatic const struct file_operations events_fops = {\n\t.owner = THIS_MODULE,\n\t.open = char_open,\n\t.release = char_close,\n\t.read = char_events_read,\n\t.poll = char_events_poll,\n};\n\nvoid cdev_event_init(struct xdma_cdev *xcdev)\n{\n\txcdev->user_irq = &(xcdev->xdev->user_irq[xcdev->bar]);\n\tcdev_init(&xcdev->cdev, &events_fops);\n}\n"
  },
  {
    "path": "drivers/awsf1portal/cdev_sgdma.c",
    "content": "/*******************************************************************************\n *\n * Xilinx XDMA IP Core Linux Driver\n * Copyright(c) 2015 - 2017 Xilinx, Inc.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms and conditions of the GNU General Public License,\n * version 2, as published by the Free Software Foundation.\n *\n * This program is distributed in the hope it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\n * more details.\n *\n * You should have received a copy of the GNU General Public License along\n * with this program.  If not, see <http://www.gnu.org/licenses/>.\n *\n * The full GNU General Public License is included in this distribution in\n * the file called \"LICENSE\".\n *\n * Karen Xie <karen.xie@xilinx.com>\n *\n ******************************************************************************/\n#define pr_fmt(fmt)     KBUILD_MODNAME \":%s: \" fmt, __func__\n\n#include <asm/cacheflush.h>\n#include \"libxdma_api.h\"\n#include \"xdma_cdev.h\"\n#include \"cdev_sgdma.h\"\n\n/* Module Parameters */\nunsigned int sgdma_timeout = 10;\nmodule_param(sgdma_timeout, uint, 0644);\nMODULE_PARM_DESC(sgdma_timeout, \"timeout in seconds for sgdma, default is 10 sec.\");\n\n/*\n * character device file operations for SG DMA engine\n */\nstatic loff_t char_sgdma_llseek(struct file *file, loff_t off, int whence)\n{\n\tloff_t newpos = 0;\n\n\tswitch (whence) {\n\tcase 0: /* SEEK_SET */\n\t\tnewpos = off;\n\t\tbreak;\n\tcase 1: /* SEEK_CUR */\n\t\tnewpos = file->f_pos + off;\n\t\tbreak;\n\tcase 2: /* SEEK_END, @TODO should work from end of address space */\n\t\tnewpos = UINT_MAX + off;\n\t\tbreak;\n\tdefault: /* can't happen */\n\t\treturn -EINVAL;\n\t}\n\tif (newpos < 0)\n\t\treturn -EINVAL;\n\tfile->f_pos = newpos;\n\tdbg_fops(\"char_sgdma_llseek: pos=%lld\\n\", (signed long long)newpos);\n\n#if 0\n\tpr_err(\"0x%p, off 0x%lld, whence %d -> pos %lld.\\n\",\n\t\tfile, (signed long long)off, whence, (signed long long)off);\n#endif\n\n\treturn newpos;\n}\n\n/* char_sgdma_read_write() -- Read from or write to the device\n *\n * @buf userspace buffer\n * @count number of bytes in the userspace buffer\n * @pos byte-address in device\n * @dir_to_device If !0, a write to the device is performed\n *\n * Iterate over the userspace buffer, taking at most 255 * PAGE_SIZE bytes for\n * each DMA transfer.\n *\n * For each transfer, get the user pages, build a sglist, map, build a\n * descriptor table. submit the transfer. wait for the interrupt handler\n * to wake us on completion.\n */\n\nstatic int check_transfer_align(struct xdma_engine *engine,\n\tconst char __user *buf, size_t count, loff_t pos, int sync)\n{\n\tBUG_ON(!engine);\n\n\t/* AXI ST or AXI MM non-incremental addressing mode? */\n\tif (engine->non_incr_addr) {\n\t\tint buf_lsb = (int)((uintptr_t)buf) & (engine->addr_align - 1);\n\t\tsize_t len_lsb = count & ((size_t)engine->len_granularity - 1);\n\t\tint pos_lsb = (int)pos & (engine->addr_align - 1);\n\n\t\tdbg_tfr(\"AXI ST or MM non-incremental\\n\");\n\t\tdbg_tfr(\"buf_lsb = %d, pos_lsb = %d, len_lsb = %ld\\n\", buf_lsb,\n\t\t\tpos_lsb, len_lsb);\n\n\t\tif (buf_lsb != 0) {\n\t\t\tdbg_tfr(\"FAIL: non-aligned buffer address %p\\n\", buf);\n\t\t\treturn -EINVAL;\n\t\t}\n\n\t\tif ((pos_lsb != 0) && (sync)) {\n\t\t\tdbg_tfr(\"FAIL: non-aligned AXI MM FPGA addr 0x%llx\\n\",\n\t\t\t\t(unsigned long long)pos);\n\t\t\treturn -EINVAL;\n\t\t}\n\n\t\tif (len_lsb != 0) {\n\t\t\tdbg_tfr(\"FAIL: len %d is not a multiple of %d\\n\",\n\t\t\t\t(int)count,\n\t\t\t\t(int)engine->len_granularity);\n\t\t\treturn -EINVAL;\n\t\t}\n\t\t/* AXI MM incremental addressing mode */\n\t} else {\n\t\tint buf_lsb = (int)((uintptr_t)buf) & (engine->addr_align - 1);\n\t\tint pos_lsb = (int)pos & (engine->addr_align - 1);\n\n\t\tif (buf_lsb != pos_lsb) {\n\t\t\tdbg_tfr(\"FAIL: Misalignment error\\n\");\n\t\t\tdbg_tfr(\"host addr %p, FPGA addr 0x%llx\\n\", buf, pos);\n\t\t\treturn -EINVAL;\n\t\t}\n\t}\n\n\treturn 0;\n}\n\n/*\n * Map a user memory range into a scatterlist\n * inspired by vhost_scsi_map_to_sgl()\n * Returns the number of scatterlist entries used or -errno on error.\n */\nstatic inline void xdma_io_cb_release(struct xdma_io_cb *cb)\n{\n\tint i;\n\n\tfor (i = 0; i < cb->pages_nr; i++)\n\t\tput_page(cb->pages[i]);\n\n\tsg_free_table(&cb->sgt);\n\tkfree(cb->pages);\n\n\tmemset(cb, 0, sizeof(*cb));\n}\n\nstatic void char_sgdma_unmap_user_buf(struct xdma_io_cb *cb, bool write)\n{\n\tint i;\n\n\tsg_free_table(&cb->sgt);\n\n\tif (!cb->pages || !cb->pages_nr)\n\t\treturn;\n\n\tfor (i = 0; i < cb->pages_nr; i++) {\n\t\tif (cb->pages[i]) {\n\t\t\tif (!write)\n\t\t\t\tset_page_dirty_lock(cb->pages[i]);\n\t\t\tput_page(cb->pages[i]);\n\t\t} else\n\t\t\tbreak;\n\t}\n\n\tif (i != cb->pages_nr)\n\t\tpr_info(\"sgl pages %d/%u.\\n\", i, cb->pages_nr);\n\n\tkfree(cb->pages);\n\tcb->pages = NULL;\n}\n\nstatic int char_sgdma_map_user_buf_to_sgl(struct xdma_io_cb *cb, bool write)\n{\n\tstruct sg_table *sgt = &cb->sgt;\n\tunsigned long len = cb->len;\n\tchar *buf = cb->buf;\n\tstruct scatterlist *sg;\n\tunsigned int pages_nr = (((unsigned long)buf + len + PAGE_SIZE -1) -\n\t\t\t\t ((unsigned long)buf & PAGE_MASK))\n\t\t\t\t>> PAGE_SHIFT;\n\tint i;\n\tint rv;\n\n\tif (pages_nr == 0) {\n\t\treturn -EINVAL;\n\t}\n\n\tif (sg_alloc_table(sgt, pages_nr, GFP_KERNEL)) {\n\t\tpr_err(\"sgl OOM.\\n\");\n\t\treturn -ENOMEM;\n\t}\n\n\tcb->pages = kcalloc(pages_nr, sizeof(struct page *), GFP_KERNEL);\n\tif (!cb->pages) {\n\t\tpr_err(\"pages OOM.\\n\");\n\t\trv = -ENOMEM;\n\t\tgoto err_out;\n\t}\n\n\trv = get_user_pages_fast((unsigned long)buf, pages_nr, 1/* write */,\n\t\t\t\tcb->pages);\n\t/* No pages were pinned */\n\tif (rv < 0) {\n\t\tpr_err(\"unable to pin down %u user pages, %d.\\n\",\n\t\t\tpages_nr, rv);\n\t\tgoto err_out;\n\t}\n\t/* Less pages pinned than wanted */\n\tif (rv != pages_nr) {\n\t\tpr_err(\"unable to pin down all %u user pages, %d.\\n\",\n\t\t\tpages_nr, rv);\n\t\trv = -EFAULT;\n\t\tcb->pages_nr = rv;\n\t\tgoto err_out;\n\t}\n\n\tfor (i = 1; i < pages_nr; i++) {\n\t\tif (cb->pages[i - 1] == cb->pages[i]) {\n\t\t\tpr_err(\"duplicate pages, %d, %d.\\n\",\n\t\t\t\ti - 1, i);\n\t\t\trv = -EFAULT;\n\t\t\tcb->pages_nr = pages_nr;\n\t\t\tgoto err_out;\n\t\t}\n\t}\n\n\tsg = sgt->sgl;\n\tfor (i = 0; i < pages_nr; i++, sg = sg_next(sg)) {\n\t\t//unsigned int offset = (uintptr_t)buf & ~PAGE_MASK;\n\t\tunsigned int offset = offset_in_page(buf);\n\t\tunsigned int nbytes = min_t(unsigned int, PAGE_SIZE - offset, len);\n\n\t\tflush_dcache_page(cb->pages[i]);\n\t\tsg_set_page(sg, cb->pages[i], nbytes, offset);\n\n\t\tbuf += nbytes;\n\t\tlen -= nbytes;\n\t}\n\n\tBUG_ON(len);\n\tcb->pages_nr = pages_nr;\n\treturn 0;\n\nerr_out:\n\tchar_sgdma_unmap_user_buf(cb, write);\n\n\treturn rv;\n}\n\nstatic ssize_t char_sgdma_read_write(struct file *file, char __user *buf,\n\t\tsize_t count, loff_t *pos, bool write)\n{\n\tint rv;\n\tssize_t res = 0;\n\tstruct xdma_cdev *xcdev = (struct xdma_cdev *)file->private_data;\n\tstruct xdma_dev *xdev;\n\tstruct xdma_engine *engine;\n\tstruct xdma_io_cb cb;\n\n\trv = xcdev_check(__func__, xcdev, 1);\n\tif (rv < 0)\n\t\treturn rv;\n\txdev = xcdev->xdev;\n\tengine = xcdev->engine;\n\n\tdbg_tfr(\"file 0x%p, priv 0x%p, buf 0x%p,%llu, pos %llu, W %d, %s.\\n\",\n\t\tfile, file->private_data, buf, (u64)count, (u64)*pos, write,\n\t\tengine->name);\n\n\tif ((write && engine->dir != DMA_TO_DEVICE) ||\n\t    (!write && engine->dir != DMA_FROM_DEVICE)) {\n\t\tpr_err(\"r/w mismatch. W %d, dir %d.\\n\",\n\t\t\twrite, engine->dir);\n\t\treturn -EINVAL;\n\t}\n\n\trv = check_transfer_align(engine, buf, count, *pos, 1);\n\tif (rv) {\n\t\tpr_info(\"Invalid transfer alignment detected\\n\");\n\t\treturn rv;\n\t}\n\n\tmemset(&cb, 0, sizeof(struct xdma_io_cb));\n\tcb.buf = buf;\n\tcb.len = count;\n\trv = char_sgdma_map_user_buf_to_sgl(&cb, write);\n\tif (rv < 0)\n\t\treturn rv;\n\n\tres = xdma_xfer_submit(xdev, engine->channel, write, *pos, &cb.sgt,\n\t\t\t\t0, sgdma_timeout * 1000);\t\n\t//pr_err(\"xfer_submit return=%lld.\\n\", (s64)res);\n\n\t//interrupt_status(xdev);\n\n\tchar_sgdma_unmap_user_buf(&cb, write);\n\n\treturn res;\n}\n\n\nstatic ssize_t char_sgdma_write(struct file *file, const char __user *buf,\n                size_t count, loff_t *pos)\n{\n        return char_sgdma_read_write(file, (char *)buf, count, pos, 1);\n}\n\nstatic ssize_t char_sgdma_read(struct file *file, char __user *buf,\n\t\tsize_t count, loff_t *pos)\n{\n\tstruct xdma_cdev *xcdev = (struct xdma_cdev *)file->private_data;\n\tstruct xdma_engine *engine;\n\tint rv;\n\n\trv = xcdev_check(__func__, xcdev, 1);\n\tif (rv < 0)\n\t\treturn rv;\n\n\tengine = xcdev->engine;\n\n\tif (engine->streaming && engine->dir == DMA_FROM_DEVICE) {\n\t\trv = xdma_cyclic_transfer_setup(engine);\n\t\tif (rv < 0 && rv != -EBUSY)\n\t\t\treturn rv;\n\t\t/* 600 sec. timeout */\n\t\treturn xdma_engine_read_cyclic(engine, buf, count, 600000);\n\t}\n\n        return char_sgdma_read_write(file, (char *)buf, count, pos, 0);\n}\n\nstatic int ioctl_do_perf_start(struct xdma_engine *engine, unsigned long arg)\n{\n        int rv;\n        struct xdma_dev *xdev;\n\n        BUG_ON(!engine);\n        xdev = engine->xdev;\n        BUG_ON(!xdev);\n\n        /* performance measurement already running on this engine? */\n        if (engine->xdma_perf) {\n                dbg_perf(\"IOCTL_XDMA_PERF_START failed!\\n\");\n                dbg_perf(\"Perf measurement already seems to be running!\\n\");\n                return -EBUSY;\n        }\n        engine->xdma_perf = kzalloc(sizeof(struct xdma_performance_ioctl),\n                GFP_KERNEL);\n\n        if (!engine->xdma_perf)\n                return -ENOMEM;\n\n        rv = copy_from_user(engine->xdma_perf,\n                (struct xdma_performance_ioctl *)arg,\n                sizeof(struct xdma_performance_ioctl));\n\n        if (rv < 0) {\n                dbg_perf(\"Failed to copy from user space 0x%lx\\n\", arg);\n                return -EINVAL;\n        }\n        if (engine->xdma_perf->version != IOCTL_XDMA_PERF_V1) {\n                dbg_perf(\"Unsupported IOCTL version %d\\n\",\n                        engine->xdma_perf->version);\n                return -EINVAL;\n        }\n\n\tenable_perf(engine);\n        dbg_perf(\"transfer_size = %d\\n\", engine->xdma_perf->transfer_size);\n        /* initialize wait queue */\n        init_waitqueue_head(&engine->xdma_perf_wq);\n        xdma_performance_submit(xdev, engine);\n\n        return 0;\n}\n\nstatic int ioctl_do_perf_stop(struct xdma_engine *engine, unsigned long arg)\n{\n        struct xdma_transfer *transfer = NULL;\n        int rv;\n\n        dbg_perf(\"IOCTL_XDMA_PERF_STOP\\n\");\n\n        /* no performance measurement running on this engine? */\n        if (!engine->xdma_perf) {\n                dbg_perf(\"No measurement in progress\\n\");\n                return -EINVAL;\n        }\n\n        /* stop measurement */\n        transfer = engine_cyclic_stop(engine);\n        dbg_perf(\"Waiting for measurement to stop\\n\");\n\n        if (engine->xdma_perf) {\n                get_perf_stats(engine);\n\n                rv = copy_to_user((void __user *)arg, engine->xdma_perf,\n                        sizeof(struct xdma_performance_ioctl));\n                if (rv) {\n                        dbg_perf(\"Error copying result to user\\n\");\n                        return -EINVAL;\n                }\n        } else {\n                dbg_perf(\"engine->xdma_perf == NULL?\\n\");\n        }\n\n        kfree(engine->xdma_perf);\n        engine->xdma_perf = NULL;\n\n        return 0;\n}\n\nstatic int ioctl_do_perf_get(struct xdma_engine *engine, unsigned long arg)\n{\n        int rc;\n\n        BUG_ON(!engine);\n\n        dbg_perf(\"IOCTL_XDMA_PERF_GET\\n\");\n\n        if (engine->xdma_perf) {\n                get_perf_stats(engine);\n\n                rc = copy_to_user((void __user *)arg, engine->xdma_perf,\n                        sizeof(struct xdma_performance_ioctl));\n                if (rc) {\n                        dbg_perf(\"Error copying result to user\\n\");\n                        return -EINVAL;\n                }\n        } else {\n                dbg_perf(\"engine->xdma_perf == NULL?\\n\");\n                return -EPROTO;\n        }\n\n        return 0;\n}\n\nstatic int ioctl_do_addrmode_set(struct xdma_engine *engine, unsigned long arg) \n{\n\treturn engine_addrmode_set(engine, arg);\n}\n\nstatic int ioctl_do_addrmode_get(struct xdma_engine *engine, unsigned long arg) \n{\n\tint rv;\n\tunsigned long src;\n\n\tBUG_ON(!engine);\n\tsrc = !!engine->non_incr_addr;\n\n\tdbg_perf(\"IOCTL_XDMA_ADDRMODE_GET\\n\");\n\trv = put_user(src, (int __user *)arg);\n\n\treturn rv;\n}\n\nstatic int ioctl_do_align_get(struct xdma_engine *engine, unsigned long arg) \n{\n\tBUG_ON(!engine);\n\n\tdbg_perf(\"IOCTL_XDMA_ALIGN_GET\\n\");\n\treturn put_user(engine->addr_align, (int __user *)arg);\n}\n\nstatic long char_sgdma_ioctl(struct file *file, unsigned int cmd,\n                unsigned long arg)\n{\n\tstruct xdma_cdev *xcdev = (struct xdma_cdev *)file->private_data;\n\tstruct xdma_dev *xdev;\n\tstruct xdma_engine *engine;\n\n        int rv = 0;\n\n\trv = xcdev_check(__func__, xcdev, 1);\n\tif (rv < 0)\n\t\treturn rv;\n\n\txdev = xcdev->xdev;\n\tengine = xcdev->engine;\n\n        switch (cmd) {\n        case IOCTL_XDMA_PERF_START:\n                rv = ioctl_do_perf_start(engine, arg);\n                break;\n        case IOCTL_XDMA_PERF_STOP:\n                rv = ioctl_do_perf_stop(engine, arg);\n                break;\n        case IOCTL_XDMA_PERF_GET:\n                rv = ioctl_do_perf_get(engine, arg);\n                break;\n\tcase IOCTL_XDMA_ADDRMODE_SET:\n\t\trv = ioctl_do_addrmode_set(engine, arg);\n\t\tbreak;\n\tcase IOCTL_XDMA_ADDRMODE_GET:\n\t\trv = ioctl_do_addrmode_get(engine, arg);\n\t\tbreak;\n\tcase IOCTL_XDMA_ALIGN_GET:\n\t\trv = ioctl_do_align_get(engine, arg);\n\t\tbreak;\n        default:\n                dbg_perf(\"Unsupported operation\\n\");\n                rv = -EINVAL;\n                break;\n        }\n\n        return rv;\n}\n\nstatic int char_sgdma_open(struct inode *inode, struct file *file)\n{\n\tstruct xdma_cdev *xcdev;\n\tstruct xdma_engine *engine;\n\n\tchar_open(inode, file);\n\n\txcdev = (struct xdma_cdev *)file->private_data;\n\tengine = xcdev->engine;\n\n\tif (engine->streaming && engine->dir == DMA_FROM_DEVICE) {\n\t\tif (engine->device_open == 1)\n\t\t\treturn -EBUSY;\n\t\telse\n\t\t\tengine->device_open = 1;\n\t}\n\n\treturn 0;\n}\n\nstatic int char_sgdma_close(struct inode *inode, struct file *file)\n{\n\tstruct xdma_cdev *xcdev = (struct xdma_cdev *)file->private_data;\n\tstruct xdma_engine *engine;\n\tint rv;\n\n\trv = xcdev_check(__func__, xcdev, 1);\n\tif (rv < 0)\n\t\treturn rv;\n\n\tengine = xcdev->engine;\n\n\tif (engine->streaming && engine->dir == DMA_FROM_DEVICE) {\n\t\tengine->device_open = 0;\n\t\tif (engine->cyclic_req)\n\t\t\treturn xdma_cyclic_transfer_teardown(engine);\n\t}\n\n\treturn 0;\n}\nstatic const struct file_operations sgdma_fops = {\n\t.owner = THIS_MODULE,\n\t.open = char_sgdma_open,\n\t.release = char_sgdma_close,\n\t.write = char_sgdma_write,\n\t.read = char_sgdma_read,\n\t.unlocked_ioctl = char_sgdma_ioctl,\n\t.llseek = char_sgdma_llseek,\n};\n\nvoid cdev_sgdma_init(struct xdma_cdev *xcdev)\n{\n\tcdev_init(&xcdev->cdev, &sgdma_fops);\n}\n"
  },
  {
    "path": "drivers/awsf1portal/cdev_sgdma.h",
    "content": "/*******************************************************************************\n *\n * Xilinx XDMA IP Core Linux Driver\n * Copyright(c) 2015 - 2017 Xilinx, Inc.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms and conditions of the GNU General Public License,\n * version 2, as published by the Free Software Foundation.\n *\n * This program is distributed in the hope it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\n * more details.\n *\n * You should have received a copy of the GNU General Public License along\n * with this program.  If not, see <http://www.gnu.org/licenses/>.\n *\n * The full GNU General Public License is included in this distribution in\n * the file called \"LICENSE\".\n *\n * Karen Xie <karen.xie@xilinx.com>\n *\n ******************************************************************************/\n#ifndef _XDMA_IOCALLS_POSIX_H_\n#define _XDMA_IOCALLS_POSIX_H_\n\n#include <linux/ioctl.h>\n\n\n#define IOCTL_XDMA_PERF_V1 (1)\n#define XDMA_ADDRMODE_MEMORY (0)\n#define XDMA_ADDRMODE_FIXED (1)\n\n/*\n * S means \"Set\" through a ptr,\n * T means \"Tell\" directly with the argument value\n * G means \"Get\": reply by setting through a pointer\n * Q means \"Query\": response is on the return value\n * X means \"eXchange\": switch G and S atomically\n * H means \"sHift\": switch T and Q atomically\n *\n * _IO(type,nr)\t\t    no arguments\n * _IOR(type,nr,datatype)   read data from driver\n * _IOW(type,nr.datatype)   write data to driver\n * _IORW(type,nr,datatype)  read/write data\n *\n * _IOC_DIR(nr)\t\t    returns direction\n * _IOC_TYPE(nr)\t    returns magic\n * _IOC_NR(nr)\t\t    returns number\n * _IOC_SIZE(nr)\t    returns size\n */\n\nstruct xdma_performance_ioctl\n{\n        /* IOCTL_XDMA_IOCTL_Vx */\n        uint32_t version;\n        uint32_t transfer_size;\n        /* measurement */\n        uint32_t stopped;\n        uint32_t iterations;\n        uint64_t clock_cycle_count;\n        uint64_t data_cycle_count;\n        uint64_t pending_count;\n};\n\n\n\n/* IOCTL codes */\n\n#define IOCTL_XDMA_PERF_START   _IOW('q', 1, struct xdma_performance_ioctl *)\n#define IOCTL_XDMA_PERF_STOP    _IOW('q', 2, struct xdma_performance_ioctl *)\n#define IOCTL_XDMA_PERF_GET     _IOR('q', 3, struct xdma_performance_ioctl *)\n#define IOCTL_XDMA_ADDRMODE_SET _IOW('q', 4, int)\n#define IOCTL_XDMA_ADDRMODE_GET _IOR('q', 5, int)\n#define IOCTL_XDMA_ALIGN_GET    _IOR('q', 6, int)\n\n#endif /* _XDMA_IOCALLS_POSIX_H_ */\n"
  },
  {
    "path": "drivers/awsf1portal/cdev_xvc.c",
    "content": "/*******************************************************************************\n *\n * Xilinx XDMA IP Core Linux Driver\n * Copyright(c) 2015 - 2017 Xilinx, Inc.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms and conditions of the GNU General Public License,\n * version 2, as published by the Free Software Foundation.\n *\n * This program is distributed in the hope it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\n * more details.\n *\n * You should have received a copy of the GNU General Public License along\n * with this program.  If not, see <http://www.gnu.org/licenses/>.\n *\n * The full GNU General Public License is included in this distribution in\n * the file called \"LICENSE\".\n *\n * Karen Xie <karen.xie@xilinx.com>\n *\n ******************************************************************************/\n#define pr_fmt(fmt)     KBUILD_MODNAME \":%s: \" fmt, __func__\n\n#include \"xdma_cdev.h\"\n#include \"cdev_xvc.h\"\n\n#define COMPLETION_LOOP_MAX\t100\n\n#define XVC_BAR_LENGTH_REG\t0x0\n#define XVC_BAR_TMS_REG\t\t0x4\n#define XVC_BAR_TDI_REG\t\t0x8\n#define XVC_BAR_TDO_REG\t\t0xC\n#define XVC_BAR_CTRL_REG\t0x10\n\n#ifdef __REG_DEBUG__\n/* SECTION: Function definitions */\ninline void __write_register(const char *fn, u32 value, void *base,\n\t\t\t\tunsigned int off)\n{\n        pr_info(\"%s: 0x%p, W reg 0x%lx, 0x%x.\\n\", fn, base, off, value);\n        iowrite32(value, base + off);\n}\n\ninline u32 __read_register(const char *fn, void *base, unsigned int off)\n{\n\tu32 v = ioread32(base + off);\n\n        pr_info(\"%s: 0x%p, R reg 0x%lx, 0x%x.\\n\", fn, base, off, v);\n        return v;\n}\n#define write_register(v,base,off) __write_register(__func__, v, base, off)\n#define read_register(base,off) __read_register(__func__, base, off)\n\n#else\n#define write_register(v,base,off)\tiowrite32(v, (base) + (off))\n#define read_register(base,off)\t\tioread32((base) + (off))\n#endif /* #ifdef __REG_DEBUG__ */\n\n\nstatic int xvc_shift_bits(void *base, u32 tms_bits, u32 tdi_bits,\n\t\t\tu32 *tdo_bits)\n{\n\tu32 control;\n\tint count;\n\n\t/* set tms bit */\n\twrite_register(tms_bits, base, XVC_BAR_TMS_REG);\n\t/* set tdi bits and shift data out */\n\twrite_register(tdi_bits, base, XVC_BAR_TDI_REG);\n\t/* enable shift operation */\n\twrite_register(0x1, base, XVC_BAR_CTRL_REG);\n\n\t/* poll for completion */\n\tcount = COMPLETION_LOOP_MAX;\n\twhile (count) {\n\t\t/* read control reg to check shift operation completion */\n\t\tcontrol = read_register(base, XVC_BAR_CTRL_REG);\n\t\tif ((control & 0x01) == 0)\n\t\t\tbreak;\n\n\t\tcount--;\n\t}\n\n\tif (!count)\t{\n\t\tpr_warn(\"XVC bar transaction timed out (0x%0X)\\n\", control);\n\t\treturn -ETIMEDOUT;\n\t}\n\n\t/* read tdo bits back out */\n\t*tdo_bits = read_register(base, XVC_BAR_TDO_REG);\n\n\treturn 0;\n}\n\nstatic long xvc_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)\n{\n        struct xdma_cdev *xcdev = (struct xdma_cdev *)filp->private_data;\n\tstruct xdma_dev *xdev;\n\tstruct xvc_ioc xvc_obj;\n\tunsigned int opcode;\n\tunsigned int total_bits;\n\tunsigned int total_bytes;\n\tunsigned char *buffer = NULL;\n\tunsigned char *tms_buf = NULL;\n\tunsigned char *tdi_buf = NULL;\n\tunsigned char *tdo_buf = NULL;\n\tunsigned int bits, bits_left;\n\tvoid __iomem *iobase;\n\tint rv;\n\n\trv = xcdev_check(__func__, xcdev, 0);\n\tif (rv < 0)\n\t\treturn rv;\n\txdev = xcdev->xdev;\n\n\tif (cmd != XDMA_IOCXVC) {\n\t\tpr_info(\"ioctl 0x%x, UNKNOWN cmd.\\n\", cmd);\n\t\treturn -ENOIOCTLCMD;\n\t}\n\n\trv = copy_from_user((void *)&xvc_obj, (void __user *)arg,\n\t\t\t\tsizeof(struct xvc_ioc));\n\t/* anything not copied ? */\n\tif (rv) {\n\t\tpr_info(\"copy_from_user xvc_obj failed: %d.\\n\", rv);\n\t\tgoto cleanup;\n\t}\n\n\topcode = xvc_obj.opcode;\n\n\t/* Invalid operation type, no operation performed */\n\tif (opcode != 0x01 && opcode != 0x02) {\n\t\tpr_info(\"UNKNOWN opcode 0x%x.\\n\", opcode);\n\t\treturn -EINVAL;\n\t}\n\n\ttotal_bits = xvc_obj.length;\n\ttotal_bytes = (total_bits + 7) >> 3;\n\n\tbuffer = (char *)kmalloc(total_bytes * 3, GFP_KERNEL);\n\tif (!buffer) {\n\t\tpr_info(\"OOM %u, op 0x%x, len %u bits, %u bytes.\\n\",\n\t\t\t3 * total_bytes, opcode, total_bits, total_bytes);\n\t\trv = -ENOMEM;\n\t\tgoto cleanup;\n\t}\n\ttms_buf = buffer;\n\ttdi_buf = tms_buf + total_bytes;\n\ttdo_buf = tdi_buf + total_bytes;\n\n\trv = copy_from_user((void *)tms_buf, xvc_obj.tms_buf, total_bytes);\n\tif (rv) {\n\t\tpr_info(\"copy tmfs_buf failed: %d/%u.\\n\", rv, total_bytes);\n\t\tgoto cleanup;\n\t}\n\trv = copy_from_user((void *)tdi_buf, xvc_obj.tdi_buf, total_bytes);\n\tif (rv) {\n\t\tpr_info(\"copy tdi_buf failed: %d/%u.\\n\", rv, total_bytes);\n\t\tgoto cleanup;\n\t}\n\n\t/* exclusive access */\n\tspin_lock(&xcdev->lock);\n\n\tiobase = xdev->bar[xcdev->bar] + xcdev->base;\n\t/* set length register to 32 initially if more than one\n\t * word-transaction is to be done */\n\tif (total_bits >= 32)\n\t\twrite_register(0x20, iobase, XVC_BAR_LENGTH_REG);\n\n\tfor (bits = 0, bits_left = total_bits; bits < total_bits; bits += 32,\n\t\tbits_left -= 32) {\n\t\tunsigned int bytes = bits >> 3;\n\t\tunsigned int shift_bytes = 4;\n\t\tu32 tms_store = 0;\n\t\tu32 tdi_store = 0;\n\t\tu32 tdo_store = 0;\n\t\t\n\t\tif (bits_left < 32) {\n\t\t\t/* set number of bits to shift out */\n\t\t\twrite_register(bits_left, iobase, XVC_BAR_LENGTH_REG);\n\t\t\tshift_bytes = (bits_left + 7) >> 3;\n\t\t}\n\n\t\tmemcpy(&tms_store, tms_buf + bytes, shift_bytes);\n\t\tmemcpy(&tdi_store, tdi_buf + bytes, shift_bytes);\n\n\t\t/* Shift data out and copy to output buffer */\n\t\trv = xvc_shift_bits(iobase, tms_store, tdi_store, &tdo_store);\n\t\tif (rv < 0)\n\t\t\tgoto cleanup;\n\n\t\tmemcpy(tdo_buf + bytes, &tdo_store, shift_bytes);\n\t}\n\n\t/* if testing bar access swap tdi and tdo bufferes to \"loopback\" */\n\tif (opcode == 0x2) {\n\t\tchar *tmp = tdo_buf;\n\n\t\ttdo_buf = tdi_buf;\n\t\ttdi_buf = tmp;\n\t}\n\n\trv = copy_to_user((void *)xvc_obj.tdo_buf, tdo_buf, total_bytes);\n\tif (rv) {\n\t\tpr_info(\"copy back tdo_buf failed: %d/%u.\\n\", rv, total_bytes);\n\t\trv = -EFAULT;\n\t\tgoto cleanup;\n\t}\n\ncleanup:\n\tif (buffer)\n\t\tkfree(buffer);\n\n\twmb();\n\tspin_unlock(&xcdev->lock);\n\n\treturn rv;\n}\n\n/*\n * character device file operations for the XVC\n */\nstatic const struct file_operations xvc_fops = {\n        .owner = THIS_MODULE,\n        .open = char_open,\n        .release = char_close,\n        .unlocked_ioctl = xvc_ioctl,\n};\n\nvoid cdev_xvc_init(struct xdma_cdev *xcdev)\n{\n#ifdef __XVC_BAR_NUM__\n\txcdev->bar = __XVC_BAR_NUM__;\n#endif\n#ifdef __XVC_BAR_OFFSET__\n\txcdev->base = __XVC_BAR_OFFSET__;\n#else\n\txcdev->base = XVC_BAR_OFFSET_DFLT;\n#endif\n\tpr_info(\"xcdev 0x%p, bar %u, offset 0x%lx.\\n\",\n\t\txcdev, xcdev->bar, xcdev->base);\n\tcdev_init(&xcdev->cdev, &xvc_fops);\n}\n"
  },
  {
    "path": "drivers/awsf1portal/cdev_xvc.h",
    "content": "/*******************************************************************************\n *\n * Xilinx XDMA IP Core Linux Driver\n * Copyright(c) 2015 - 2017 Xilinx, Inc.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms and conditions of the GNU General Public License,\n * version 2, as published by the Free Software Foundation.\n *\n * This program is distributed in the hope it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\n * more details.\n *\n * You should have received a copy of the GNU General Public License along\n * with this program.  If not, see <http://www.gnu.org/licenses/>.\n *\n * The full GNU General Public License is included in this distribution in\n * the file called \"LICENSE\".\n *\n * Karen Xie <karen.xie@xilinx.com>\n *\n ******************************************************************************/\n#ifndef __XVC_IOCTL_H__\n#define __XVC_IOCTL_H__\n\n#include <linux/ioctl.h>\n\n/*\n * !!! TODO !!!\n * need a better way set the bar offset dynamicly\n */\n#define XVC_BAR_OFFSET_DFLT\t0x40000\t/* DSA 4.0 */\n\n#define XVC_MAGIC 0x58564344  // \"XVCD\"\n\nstruct xvc_ioc {\n\tunsigned int opcode;\n\tunsigned int length;\n\tunsigned char *tms_buf;\n\tunsigned char *tdi_buf;\n\tunsigned char *tdo_buf;\n};\n\n#define XDMA_IOCXVC\t_IOWR(XVC_MAGIC, 1, struct xvc_ioc)\n\n#endif /* __XVC_IOCTL_H__ */\n"
  },
  {
    "path": "drivers/awsf1portal/dkms.conf",
    "content": "PACKAGE_NAME=\"@PKG_NAME@\"\nPACKAGE_VERSION=\"@VERSION@\"\nBUILT_MODULE_NAME[0]=\"pcieportal\"\nDEST_MODULE_LOCATION[0]=\"/extra/fpga\"\nBUILT_MODULE_NAME[1]=\"portalmem\"\nDEST_MODULE_LOCATION[1]=\"/extra/fpga\"\nAUTOINSTALL=\"yes\"\n"
  },
  {
    "path": "drivers/awsf1portal/driverversion.h",
    "content": "#define DRIVER_VERSION \"\"\n"
  },
  {
    "path": "drivers/awsf1portal/libxdma.c",
    "content": "/*******************************************************************************\n *\n * Xilinx XDMA IP Core Linux Driver\n * Copyright(c) 2015 - 2017 Xilinx, Inc.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms and conditions of the GNU General Public License,\n * version 2, as published by the Free Software Foundation.\n *\n * This program is distributed in the hope it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\n * more details.\n *\n * You should have received a copy of the GNU General Public License along\n * with this program.  If not, see <http://www.gnu.org/licenses/>.\n *\n * The full GNU General Public License is included in this distribution in\n * the file called \"LICENSE\".\n *\n * Karen Xie <karen.xie@xilinx.com>\n *\n ******************************************************************************/\n\n#define pr_fmt(fmt)     KBUILD_MODNAME \":%s: \" fmt, __func__\n\n#include <linux/module.h>\n#include <linux/kernel.h>\n#include <linux/string.h>\n#include <linux/mm.h>\n#include <linux/io.h>\n#include <linux/errno.h>\n#include <linux/sched.h>\n#include <linux/vmalloc.h>\n\n#include \"libxdma.h\"\n#include \"libxdma_api.h\"\n#include \"cdev_sgdma.h\"\n\n/* SECTION: Module licensing */\n\n#ifdef __LIBXDMA_MOD__\n#include \"version.h\"\n#define DRV_MODULE_NAME\t\t\"libxdma\"\n#define DRV_MODULE_DESC\t\t\"Xilinx XDMA Base Driver\"\n#define DRV_MODULE_RELDATE\t\"Feb. 2017\"\n\nstatic char version[] =\n        DRV_MODULE_DESC \" \" DRV_MODULE_NAME \" v\" DRV_MODULE_VERSION \"\\n\";\n\nMODULE_AUTHOR(\"Xilinx, Inc.\");\nMODULE_DESCRIPTION(DRV_MODULE_DESC);\nMODULE_VERSION(DRV_MODULE_VERSION);\nMODULE_LICENSE(\"GPL v2\");\n#endif\n\n/* Module Parameters */\nstatic unsigned int poll_mode;\nmodule_param(poll_mode, uint, 0644);\nMODULE_PARM_DESC(poll_mode, \"Set 1 for hw polling, default is 0 (interrupts)\");\n\nstatic unsigned int interrupt_mode;\nmodule_param(interrupt_mode, uint, 0644);\nMODULE_PARM_DESC(interrupt_mode, \"0 - MSI-x , 1 - MSI, 2 - Legacy\");\n\nstatic unsigned int enable_credit_mp;\nmodule_param(enable_credit_mp, uint, 0644);\nMODULE_PARM_DESC(enable_credit_mp, \"Set 1 to enable creidt feature, default is 0 (no credit control)\");\n\nunsigned int desc_blen_max = XDMA_DESC_BLEN_MAX;\nmodule_param(desc_blen_max, uint, 0644);\nMODULE_PARM_DESC(desc_blen_max, \"per descriptor max. buffer length, default is (1 << 28) - 1\");\n\n/*\n * xdma device management\n * maintains a list of the xdma devices\n */\nstatic LIST_HEAD(xdev_list);\nstatic DEFINE_MUTEX(xdev_mutex);\n\nstatic LIST_HEAD(xdev_rcu_list);\nstatic DEFINE_SPINLOCK(xdev_rcu_lock);\n\n#ifndef list_last_entry\n#define list_last_entry(ptr, type, member) \\\n\t\tlist_entry((ptr)->prev, type, member)\n#endif\n\nstatic inline void xdev_list_add(struct xdma_dev *xdev)\n{\n\tmutex_lock(&xdev_mutex);\n\tif (list_empty(&xdev_list))\n\t\txdev->idx = 0;\n\telse {\n\t\tstruct xdma_dev *last;\n\n\t\tlast = list_last_entry(&xdev_list, struct xdma_dev, list_head);\n\t\txdev->idx = last->idx + 1;\n\t}\n\tlist_add_tail(&xdev->list_head, &xdev_list);\n\tmutex_unlock(&xdev_mutex);\n\n\tdbg_init(\"dev %s, xdev 0x%p, xdma idx %d.\\n\",\n\t\tdev_name(&xdev->pdev->dev), xdev, xdev->idx);\n\n\tspin_lock(&xdev_rcu_lock);\n\tlist_add_tail_rcu(&xdev->rcu_node, &xdev_rcu_list);\n\tspin_unlock(&xdev_rcu_lock);\n}\n\n#undef list_last_entry\n\nstatic inline void xdev_list_remove(struct xdma_dev *xdev)\n{\n\tmutex_lock(&xdev_mutex);\n\tlist_del(&xdev->list_head);\n\tmutex_unlock(&xdev_mutex);\n\n\tspin_lock(&xdev_rcu_lock);\n\tlist_del_rcu(&xdev->rcu_node);\n\tspin_unlock(&xdev_rcu_lock);\n\tsynchronize_rcu();\n}\n\nstruct xdma_dev *xdev_find_by_pdev(struct pci_dev *pdev)\n{\n        struct xdma_dev *xdev, *tmp;\n\n        mutex_lock(&xdev_mutex);\n        list_for_each_entry_safe(xdev, tmp, &xdev_list, list_head) {\n                if (xdev->pdev == pdev) {\n                        mutex_unlock(&xdev_mutex);\n                        return xdev;\n                }\n        }\n        mutex_unlock(&xdev_mutex);\n        return NULL;\n}\nEXPORT_SYMBOL_GPL(xdev_find_by_pdev);\n\nstatic inline int debug_check_dev_hndl(const char *fname, struct pci_dev *pdev,\n\t\t\t\t void *hndl)\n{\n\tstruct xdma_dev *xdev;\n\n\tif (!pdev)\n\t\treturn -EINVAL;\n\n\txdev = xdev_find_by_pdev(pdev);\n\tif (!xdev) {\n\t\tpr_info(\"%s pdev 0x%p, hndl 0x%p, NO match found!\\n\",\n\t\t\tfname, pdev, hndl);\n\t\treturn -EINVAL;\n\t}\n\tif (xdev != hndl) {\n\t\tpr_err(\"%s pdev 0x%p, hndl 0x%p != 0x%p!\\n\",\n\t\t\tfname, pdev, hndl, xdev);\n\t\treturn -EINVAL;\n\t}\n\n\treturn 0;\n}\n\n#ifdef __LIBXDMA_DEBUG__\n/* SECTION: Function definitions */\ninline void __write_register(const char *fn, u32 value, void *iomem, unsigned long off)\n{\n\tpr_err(\"%s: w reg 0x%lx(0x%p), 0x%x.\\n\", fn, off, iomem, value);\n\tiowrite32(value, iomem);\n}\n#define write_register(v,mem,off) __write_register(__func__, v, mem, off)\n#else\n#define write_register(v,mem,off) iowrite32(v, mem)\n#endif\n\ninline u32 read_register(void *iomem)\n{\n\treturn ioread32(iomem);\n}\n\nstatic inline u32 build_u32(u32 hi, u32 lo)\n{\n\treturn ((hi & 0xFFFFUL) << 16) | (lo & 0xFFFFUL);\n}\n\nstatic inline u64 build_u64(u64 hi, u64 lo)\n{\n\treturn ((hi & 0xFFFFFFFULL) << 32) | (lo & 0xFFFFFFFFULL);\n}\n\nstatic void check_nonzero_interrupt_status(struct xdma_dev *xdev)\n{\n\tstruct interrupt_regs *reg = (struct interrupt_regs *)\n\t\t(xdev->bar[xdev->config_bar_idx] + XDMA_OFS_INT_CTRL);\n\tu32 w;\n\n\tw = read_register(&reg->user_int_enable);\n\tif (w)\n\t\tpr_info(\"%s xdma%d user_int_enable = 0x%08x\\n\",\n\t\t\tdev_name(&xdev->pdev->dev), xdev->idx, w);\n\n\tw = read_register(&reg->channel_int_enable);\n\tif (w)\n\tpr_info(\"%s xdma%d channel_int_enable = 0x%08x\\n\",\n\t\t\tdev_name(&xdev->pdev->dev), xdev->idx, w);\n\n\tw = read_register(&reg->user_int_request);\n\tif (w)\n\t\tpr_info(\"%s xdma%d user_int_request = 0x%08x\\n\",\n\t\t\tdev_name(&xdev->pdev->dev), xdev->idx, w);\n\tw = read_register(&reg->channel_int_request);\n\tif (w)\n\t\tpr_info(\"%s xdma%d channel_int_request = 0x%08x\\n\",\n\t\t\tdev_name(&xdev->pdev->dev), xdev->idx, w);\n\n\tw = read_register(&reg->user_int_pending);\n\tif (w)\n\t\tpr_info(\"%s xdma%d user_int_pending = 0x%08x\\n\",\n\t\t\tdev_name(&xdev->pdev->dev), xdev->idx, w);\n\tw = read_register(&reg->channel_int_pending);\n\tif (w)\n\t\tpr_info(\"%s xdma%d channel_int_pending = 0x%08x\\n\",\n\t\t\tdev_name(&xdev->pdev->dev), xdev->idx, w);\n}\n\n/* channel_interrupts_enable -- Enable interrupts we are interested in */\nstatic void channel_interrupts_enable(struct xdma_dev *xdev, u32 mask)\n{\n\tstruct interrupt_regs *reg = (struct interrupt_regs *)\n\t\t(xdev->bar[xdev->config_bar_idx] + XDMA_OFS_INT_CTRL);\n\n\twrite_register(mask, &reg->channel_int_enable_w1s, XDMA_OFS_INT_CTRL);\n}\n\n/* channel_interrupts_disable -- Disable interrupts we not interested in */\nstatic void channel_interrupts_disable(struct xdma_dev *xdev, u32 mask)\n{\n\tstruct interrupt_regs *reg = (struct interrupt_regs *)\n\t\t(xdev->bar[xdev->config_bar_idx] + XDMA_OFS_INT_CTRL);\n\n\twrite_register(mask, &reg->channel_int_enable_w1c, XDMA_OFS_INT_CTRL);\n}\n\n/* user_interrupts_enable -- Enable interrupts we are interested in */\nstatic void user_interrupts_enable(struct xdma_dev *xdev, u32 mask)\n{\n\tstruct interrupt_regs *reg = (struct interrupt_regs *)\n\t\t(xdev->bar[xdev->config_bar_idx] + XDMA_OFS_INT_CTRL);\n\n\twrite_register(mask, &reg->user_int_enable_w1s, XDMA_OFS_INT_CTRL);\n}\n\n/* user_interrupts_disable -- Disable interrupts we not interested in */\nstatic void user_interrupts_disable(struct xdma_dev *xdev, u32 mask)\n{\n\tstruct interrupt_regs *reg = (struct interrupt_regs *)\n\t\t(xdev->bar[xdev->config_bar_idx] + XDMA_OFS_INT_CTRL);\n\n\twrite_register(mask, &reg->user_int_enable_w1c, XDMA_OFS_INT_CTRL);\n}\n\n/* read_interrupts -- Print the interrupt controller status */\nstatic u32 read_interrupts(struct xdma_dev *xdev)\n{\n\tstruct interrupt_regs *reg = (struct interrupt_regs *)\n\t\t(xdev->bar[xdev->config_bar_idx] + XDMA_OFS_INT_CTRL);\n\tu32 lo;\n\tu32 hi;\n\n\t/* extra debugging; inspect complete engine set of registers */\n\thi = read_register(&reg->user_int_request);\n\tdbg_io(\"ioread32(0x%p) returned 0x%08x (user_int_request).\\n\",\n\t\t&reg->user_int_request, hi);\n\tlo = read_register(&reg->channel_int_request);\n\tdbg_io(\"ioread32(0x%p) returned 0x%08x (channel_int_request)\\n\",\n\t\t&reg->channel_int_request, lo);\n\n\t/* return interrupts: user in upper 16-bits, channel in lower 16-bits */\n\treturn build_u32(hi, lo);\n}\n\nvoid enable_perf(struct xdma_engine *engine)\n{\n\tu32 w;\n\n\tw = XDMA_PERF_CLEAR;\n\twrite_register(w, &engine->regs->perf_ctrl,\n\t\t\t(unsigned long)(&engine->regs->perf_ctrl) -\n\t\t\t(unsigned long)(&engine->regs));\n\tread_register(&engine->regs->identifier);\n\tw = XDMA_PERF_AUTO | XDMA_PERF_RUN;\n\twrite_register(w, &engine->regs->perf_ctrl,\n\t\t\t(unsigned long)(&engine->regs->perf_ctrl) -\n\t\t\t(unsigned long)(&engine->regs));\n\tread_register(&engine->regs->identifier);\n\n\tdbg_perf(\"IOCTL_XDMA_PERF_START\\n\");\n\n}\nEXPORT_SYMBOL_GPL(enable_perf);\n\nvoid get_perf_stats(struct xdma_engine *engine)\n{\n\tu32 hi;\n\tu32 lo;\n\n\tBUG_ON(!engine);\n\n\tif (!engine->xdma_perf) {\n\t\tpr_info(\"%s perf struct not set up.\\n\", engine->name);\n\t\treturn;\n\t}\n\n\thi = 0;\n\tlo = read_register(&engine->regs->completed_desc_count);\n\tengine->xdma_perf->iterations = build_u64(hi, lo);\n\n\thi = read_register(&engine->regs->perf_cyc_hi);\n\tlo = read_register(&engine->regs->perf_cyc_lo);\n\n\tengine->xdma_perf->clock_cycle_count = build_u64(hi, lo);\n\n\thi = read_register(&engine->regs->perf_dat_hi);\n\tlo = read_register(&engine->regs->perf_dat_lo);\n\tengine->xdma_perf->data_cycle_count = build_u64(hi, lo);\n\n\thi = read_register(&engine->regs->perf_pnd_hi);\n\tlo = read_register(&engine->regs->perf_pnd_lo);\n\tengine->xdma_perf->pending_count = build_u64(hi, lo);\n}\nEXPORT_SYMBOL_GPL(get_perf_stats);\n\nstatic void engine_reg_dump(struct xdma_engine *engine)\n{\n\tu32 w;\n\n\tBUG_ON(!engine);\n\n\tw = read_register(&engine->regs->identifier);\n\tpr_info(\"%s: ioread32(0x%p) = 0x%08x (id).\\n\",\n\t\tengine->name, &engine->regs->identifier, w);\n\tw &= BLOCK_ID_MASK;\n\tif (w != BLOCK_ID_HEAD) {\n\t\tpr_info(\"%s: engine id missing, 0x%08x exp. & 0x%x = 0x%x\\n\",\n\t\t\t engine->name, w, BLOCK_ID_MASK, BLOCK_ID_HEAD);\n\t\treturn;\n\t}\n\t/* extra debugging; inspect complete engine set of registers */\n\tw = read_register(&engine->regs->status);\n\tpr_info(\"%s: ioread32(0x%p) = 0x%08x (status).\\n\",\n\t\tengine->name, &engine->regs->status, w);\n\tw = read_register(&engine->regs->control);\n\tpr_info(\"%s: ioread32(0x%p) = 0x%08x (control)\\n\",\n\t\tengine->name, &engine->regs->control, w);\n\tw = read_register(&engine->sgdma_regs->first_desc_lo);\n\tpr_info(\"%s: ioread32(0x%p) = 0x%08x (first_desc_lo)\\n\",\n\t\tengine->name, &engine->sgdma_regs->first_desc_lo, w);\n\tw = read_register(&engine->sgdma_regs->first_desc_hi);\n\tpr_info(\"%s: ioread32(0x%p) = 0x%08x (first_desc_hi)\\n\",\n\t\tengine->name, &engine->sgdma_regs->first_desc_hi, w);\n\tw = read_register(&engine->sgdma_regs->first_desc_adjacent);\n\tpr_info(\"%s: ioread32(0x%p) = 0x%08x (first_desc_adjacent).\\n\",\n\t\tengine->name, &engine->sgdma_regs->first_desc_adjacent, w);\n\tw = read_register(&engine->regs->completed_desc_count);\n\tpr_info(\"%s: ioread32(0x%p) = 0x%08x (completed_desc_count).\\n\",\n\t\tengine->name, &engine->regs->completed_desc_count, w);\n\tw = read_register(&engine->regs->interrupt_enable_mask);\n\tpr_info(\"%s: ioread32(0x%p) = 0x%08x (interrupt_enable_mask)\\n\",\n\t\tengine->name, &engine->regs->interrupt_enable_mask, w);\n}\n\n/**\n * engine_status_read() - read status of SG DMA engine (optionally reset)\n *\n * Stores status in engine->status.\n *\n * @return -1 on failure, status register otherwise\n */\nstatic void engine_status_dump(struct xdma_engine *engine)\n{\n\tu32 v = engine->status;\n\tchar buffer[256];\n\tchar *buf = buffer;\n\tint len = 0;\n\n\tlen = sprintf(buf, \"SG engine %s status: 0x%08x: \", engine->name, v);\n\t\n\tif ((v & XDMA_STAT_BUSY))\n\t\tlen += sprintf(buf + len, \"BUSY,\");\n\tif ((v & XDMA_STAT_DESC_STOPPED))\n\t\tlen += sprintf(buf + len, \"DESC_STOPPED,\");\n\tif ((v & XDMA_STAT_DESC_COMPLETED))\n\t\tlen += sprintf(buf + len, \"DESC_COMPL,\");\n\n\t/* common H2C & C2H */\t\n \tif ((v & XDMA_STAT_COMMON_ERR_MASK)) {\n\t\tif ((v & XDMA_STAT_ALIGN_MISMATCH))\n\t\t\tlen += sprintf(buf + len, \"ALIGN_MISMATCH \");\n\t\tif ((v & XDMA_STAT_MAGIC_STOPPED))\n\t\t\tlen += sprintf(buf + len, \"MAGIC_STOPPED \");\n\t\tif ((v & XDMA_STAT_INVALID_LEN))\n\t\t\tlen += sprintf(buf + len, \"INVLIAD_LEN \");\n\t\tif ((v & XDMA_STAT_IDLE_STOPPED))\n\t\t\tlen += sprintf(buf + len, \"IDLE_STOPPED \");\n\t\tbuf[len - 1] = ',';\n\t}\n\n\tif ((engine->dir == DMA_TO_DEVICE)) {\n\t\t/* H2C only */\n\t\tif ((v & XDMA_STAT_H2C_R_ERR_MASK)) {\n\t\t\tlen += sprintf(buf + len, \"R:\");\n\t\t\tif ((v & XDMA_STAT_H2C_R_UNSUPP_REQ))\n\t\t\t\tlen += sprintf(buf + len, \"UNSUPP_REQ \");\n\t\t\tif ((v & XDMA_STAT_H2C_R_COMPL_ABORT))\n\t\t\t\tlen += sprintf(buf + len, \"COMPL_ABORT \");\n\t\t\tif ((v & XDMA_STAT_H2C_R_PARITY_ERR))\n\t\t\t\tlen += sprintf(buf + len, \"PARITY \");\n\t\t\tif ((v & XDMA_STAT_H2C_R_HEADER_EP))\n\t\t\t\tlen += sprintf(buf + len, \"HEADER_EP \");\n\t\t\tif ((v & XDMA_STAT_H2C_R_UNEXP_COMPL))\n\t\t\t\tlen += sprintf(buf + len, \"UNEXP_COMPL \");\n\t\t\tbuf[len - 1] = ',';\n\t\t}\n\n\t\tif ((v & XDMA_STAT_H2C_W_ERR_MASK)) {\n\t\t\tlen += sprintf(buf + len, \"W:\");\n\t\t\tif ((v & XDMA_STAT_H2C_W_DECODE_ERR))\n\t\t\t\tlen += sprintf(buf + len, \"DECODE_ERR \");\n\t\t\tif ((v & XDMA_STAT_H2C_W_SLAVE_ERR))\n\t\t\t\tlen += sprintf(buf + len, \"SLAVE_ERR \");\n\t\t\tbuf[len - 1] = ',';\n\t\t}\n\t\t\n\t} else {\n\t\t/* C2H only */\n\t\tif ((v & XDMA_STAT_C2H_R_ERR_MASK)) {\n\t\t\tlen += sprintf(buf + len, \"R:\");\n\t\t\tif ((v & XDMA_STAT_C2H_R_DECODE_ERR))\n\t\t\t\tlen += sprintf(buf + len, \"DECODE_ERR \");\n\t\t\tif ((v & XDMA_STAT_C2H_R_SLAVE_ERR))\n\t\t\t\tlen += sprintf(buf + len, \"SLAVE_ERR \");\n\t\t\tbuf[len - 1] = ',';\n\t\t}\n\t}\n\n\t/* common H2C & C2H */\t\n \tif ((v & XDMA_STAT_DESC_ERR_MASK)) {\n\t\tlen += sprintf(buf + len, \"DESC_ERR:\");\n\t\tif ((v & XDMA_STAT_DESC_UNSUPP_REQ))\n\t\t\tlen += sprintf(buf + len, \"UNSUPP_REQ \");\n\t\tif ((v & XDMA_STAT_DESC_COMPL_ABORT))\n\t\t\tlen += sprintf(buf + len, \"COMPL_ABORT \");\n\t\tif ((v & XDMA_STAT_DESC_PARITY_ERR))\n\t\t\tlen += sprintf(buf + len, \"PARITY \");\n\t\tif ((v & XDMA_STAT_DESC_HEADER_EP))\n\t\t\tlen += sprintf(buf + len, \"HEADER_EP \");\n\t\tif ((v & XDMA_STAT_DESC_UNEXP_COMPL))\n\t\t\tlen += sprintf(buf + len, \"UNEXP_COMPL \");\n\t\tbuf[len - 1] = ',';\n\t}\n\n\tbuf[len - 1] = '\\0';\n\tpr_info(\"%s\\n\", buffer);\n}\n\nstatic u32 engine_status_read(struct xdma_engine *engine, bool clear, bool dump)\n{\n\tu32 value;\n\n\tBUG_ON(!engine);\n\n\tif (dump)\n\t\tengine_reg_dump(engine);\n\n\t/* read status register */\n\tif (clear)\n\t\tvalue = engine->status =\n\t\t\tread_register(&engine->regs->status_rc);\n\telse\n\t\tvalue = engine->status = read_register(&engine->regs->status);\n\n\tif (dump)\n\t\tengine_status_dump(engine);\n\n\treturn value;\n}\n\n/**\n * xdma_engine_stop() - stop an SG DMA engine\n *\n */\nstatic void xdma_engine_stop(struct xdma_engine *engine)\n{\n\tu32 w;\n\n\tBUG_ON(!engine);\n\tdbg_tfr(\"xdma_engine_stop(engine=%p)\\n\", engine);\n\n\tw = 0;\n\tw |= (u32)XDMA_CTRL_IE_DESC_ALIGN_MISMATCH;\n\tw |= (u32)XDMA_CTRL_IE_MAGIC_STOPPED;\n\tw |= (u32)XDMA_CTRL_IE_READ_ERROR;\n\tw |= (u32)XDMA_CTRL_IE_DESC_ERROR;\n\n\tif (poll_mode) {\n\t\tw |= (u32) XDMA_CTRL_POLL_MODE_WB;\n\t} else {\n\t\tw |= (u32)XDMA_CTRL_IE_DESC_STOPPED;\n\t\tw |= (u32)XDMA_CTRL_IE_DESC_COMPLETED;\n\n\t\t/* Disable IDLE STOPPED for MM */\n\t\tif ((engine->streaming && (engine->dir == DMA_FROM_DEVICE)) ||\n\t\t    (engine->xdma_perf))\n\t\t\tw |= (u32)XDMA_CTRL_IE_IDLE_STOPPED;\n\t}\n\n\tdbg_tfr(\"Stopping SG DMA %s engine; writing 0x%08x to 0x%p.\\n\",\n\t\t\tengine->name, w, (u32 *)&engine->regs->control);\n\twrite_register(w, &engine->regs->control,\n\t\t\t(unsigned long)(&engine->regs->control) -\n\t\t\t(unsigned long)(&engine->regs));\n\t/* dummy read of status register to flush all previous writes */\n\tdbg_tfr(\"xdma_engine_stop(%s) done\\n\", engine->name);\n}\n\nstatic void engine_start_mode_config(struct xdma_engine *engine)\n{\n\tu32 w;\n\n\tBUG_ON(!engine);\n\n\t/* If a perf test is running, enable the engine interrupts */\n\tif (engine->xdma_perf) {\n\t\tw = XDMA_CTRL_IE_DESC_STOPPED;\n\t\tw |= XDMA_CTRL_IE_DESC_COMPLETED;\n\t\tw |= XDMA_CTRL_IE_DESC_ALIGN_MISMATCH;\n\t\tw |= XDMA_CTRL_IE_MAGIC_STOPPED;\n\t\tw |= XDMA_CTRL_IE_IDLE_STOPPED;\n\t\tw |= XDMA_CTRL_IE_READ_ERROR;\n\t\tw |= XDMA_CTRL_IE_DESC_ERROR;\n\n\t\twrite_register(w, &engine->regs->interrupt_enable_mask,\n\t\t\t(unsigned long)(&engine->regs->interrupt_enable_mask) -\n\t\t\t(unsigned long)(&engine->regs));\n\t}\n\n\t/* write control register of SG DMA engine */\n\tw = (u32)XDMA_CTRL_RUN_STOP;\n\tw |= (u32)XDMA_CTRL_IE_READ_ERROR;\n\tw |= (u32)XDMA_CTRL_IE_DESC_ERROR;\n\tw |= (u32)XDMA_CTRL_IE_DESC_ALIGN_MISMATCH;\n\tw |= (u32)XDMA_CTRL_IE_MAGIC_STOPPED;\n\n\tif (poll_mode) {\n\t\tw |= (u32)XDMA_CTRL_POLL_MODE_WB;\n\t} else { \n\t\tw |= (u32)XDMA_CTRL_IE_DESC_STOPPED;\n\t\tw |= (u32)XDMA_CTRL_IE_DESC_COMPLETED;\n\n\t\tif ((engine->streaming && (engine->dir == DMA_FROM_DEVICE)) ||\n\t\t    (engine->xdma_perf))\n\t\t\tw |= (u32)XDMA_CTRL_IE_IDLE_STOPPED;\n\n\t\t/* set non-incremental addressing mode */\n\t\tif (engine->non_incr_addr)\n\t\t\tw |= (u32)XDMA_CTRL_NON_INCR_ADDR;\n\t}\n\n\tdbg_tfr(\"iowrite32(0x%08x to 0x%p) (control)\\n\", w,\n\t\t\t(void *)&engine->regs->control);\n\t/* start the engine */\n\twrite_register(w, &engine->regs->control,\n\t\t\t(unsigned long)(&engine->regs->control) -\n\t\t\t(unsigned long)(&engine->regs));\n\n\t/* dummy read of status register to flush all previous writes */\n\tw = read_register(&engine->regs->status);\n\tdbg_tfr(\"ioread32(0x%p) = 0x%08x (dummy read flushes writes).\\n\",\n\t\t\t&engine->regs->status, w);\n}\n\n/**\n * engine_start() - start an idle engine with its first transfer on queue\n *\n * The engine will run and process all transfers that are queued using\n * transfer_queue() and thus have their descriptor lists chained.\n *\n * During the run, new transfers will be processed if transfer_queue() has\n * chained the descriptors before the hardware fetches the last descriptor.\n * A transfer that was chained too late will invoke a new run of the engine\n * initiated from the engine_service() routine.\n *\n * The engine must be idle and at least one transfer must be queued.\n * This function does not take locks; the engine spinlock must already be\n * taken.\n *\n */\nstatic struct xdma_transfer *engine_start(struct xdma_engine *engine)\n{\n\tstruct xdma_transfer *transfer;\n\tu32 w;\n\tint extra_adj = 0;\n\n\t/* engine must be idle */\n\tBUG_ON(engine->running);\n\t/* engine transfer queue must not be empty */\n\tBUG_ON(list_empty(&engine->transfer_list));\n\t/* inspect first transfer queued on the engine */\n\ttransfer = list_entry(engine->transfer_list.next, struct xdma_transfer,\n\t\t\t\tentry);\n\tBUG_ON(!transfer);\n\n\t/* engine is no longer shutdown */\n\tengine->shutdown = ENGINE_SHUTDOWN_NONE;\n\n\tdbg_tfr(\"engine_start(%s): transfer=0x%p.\\n\", engine->name, transfer);\n\n\t/* initialize number of descriptors of dequeued transfers */\n\tengine->desc_dequeued = 0;\n\n\t/* write lower 32-bit of bus address of transfer first descriptor */\n\tw = cpu_to_le32(PCI_DMA_L(transfer->desc_bus));\n\tdbg_tfr(\"iowrite32(0x%08x to 0x%p) (first_desc_lo)\\n\", w,\n\t\t\t(void *)&engine->sgdma_regs->first_desc_lo);\n\twrite_register(w, &engine->sgdma_regs->first_desc_lo,\n\t\t\t(unsigned long)(&engine->sgdma_regs->first_desc_lo) -\n\t\t\t(unsigned long)(&engine->sgdma_regs));\n\t/* write upper 32-bit of bus address of transfer first descriptor */\n\tw = cpu_to_le32(PCI_DMA_H(transfer->desc_bus));\n\tdbg_tfr(\"iowrite32(0x%08x to 0x%p) (first_desc_hi)\\n\", w,\n\t\t\t(void *)&engine->sgdma_regs->first_desc_hi);\n\twrite_register(w, &engine->sgdma_regs->first_desc_hi,\n\t\t\t(unsigned long)(&engine->sgdma_regs->first_desc_hi) -\n\t\t\t(unsigned long)(&engine->sgdma_regs));\n\n\tif (transfer->desc_adjacent > 0) {\n\t\textra_adj = transfer->desc_adjacent - 1;\n\t\tif (extra_adj > MAX_EXTRA_ADJ)\n\t\t\textra_adj = MAX_EXTRA_ADJ;\n\t}\n\tdbg_tfr(\"iowrite32(0x%08x to 0x%p) (first_desc_adjacent)\\n\",\n\t\textra_adj, (void *)&engine->sgdma_regs->first_desc_adjacent);\n\twrite_register(extra_adj, &engine->sgdma_regs->first_desc_adjacent,\n\t\t\t(unsigned long)(&engine->sgdma_regs->first_desc_adjacent) -\n\t\t\t(unsigned long)(&engine->sgdma_regs));\n\n\tdbg_tfr(\"ioread32(0x%p) (dummy read flushes writes).\\n\",\n\t\t&engine->regs->status);\n\twmb();\n\n\tengine_start_mode_config(engine);\n\n\tengine_status_read(engine, 0, 0);\n\n\tdbg_tfr(\"%s engine 0x%p now running\\n\", engine->name, engine);\n\t/* remember the engine is running */\n\tengine->running = 1;\n\treturn transfer;\n}\n\n/**\n * engine_service() - service an SG DMA engine\n *\n * must be called with engine->lock already acquired\n *\n * @engine pointer to struct xdma_engine\n *\n */\nstatic void engine_service_shutdown(struct xdma_engine *engine)\n{\n\t/* if the engine stopped with RUN still asserted, de-assert RUN now */\n\tdbg_tfr(\"engine just went idle, resetting RUN_STOP.\\n\");\n\txdma_engine_stop(engine);\n\tengine->running = 0;\n\n\t/* awake task on engine's shutdown wait queue */\n\twake_up_interruptible(&engine->shutdown_wq);\n}\n\nstruct xdma_transfer *engine_transfer_completion(struct xdma_engine *engine,\n\t\tstruct xdma_transfer *transfer)\n{\n\tBUG_ON(!engine);\n\n\tif (unlikely(!transfer)) {\n\t\tpr_info(\"%s: xfer empty.\\n\", engine->name);\n\t\treturn NULL;\n\t}\n\n\t/* synchronous I/O? */\n\t/* awake task on transfer's wait queue */\n\twake_up_interruptible(&transfer->wq);\n\n\treturn transfer;\n}\n\nstruct xdma_transfer *engine_service_transfer_list(struct xdma_engine *engine,\n\t\tstruct xdma_transfer *transfer, u32 *pdesc_completed)\n{\n\tBUG_ON(!engine);\n\tBUG_ON(!pdesc_completed);\n\n\tif (unlikely(!transfer)) {\n\t\tpr_info(\"%s xfer empty, pdesc completed %u.\\n\",\n\t\t\tengine->name, *pdesc_completed);\n\t\treturn NULL;\n\t}\n\n\t/*\n\t * iterate over all the transfers completed by the engine,\n\t * except for the last (i.e. use > instead of >=).\n\t */\n\twhile (transfer && (!transfer->cyclic) &&\n\t\t(*pdesc_completed > transfer->desc_num)) {\n\t\t/* remove this transfer from pdesc_completed */\n\t\t*pdesc_completed -= transfer->desc_num;\n\t\tdbg_tfr(\"%s engine completed non-cyclic xfer 0x%p (%d desc)\\n\",\n\t\t\tengine->name, transfer, transfer->desc_num);\n\t\t/* remove completed transfer from list */\n\t\tlist_del(engine->transfer_list.next);\n\t\t/* add to dequeued number of descriptors during this run */\n\t\tengine->desc_dequeued += transfer->desc_num;\n\t\t/* mark transfer as succesfully completed */\n\t\ttransfer->state = TRANSFER_STATE_COMPLETED;\n\n\t\t/* Complete transfer - sets transfer to NULL if an async\n\t\t * transfer has completed */\n\t\ttransfer = engine_transfer_completion(engine, transfer);\n\n\t\t/* if exists, get the next transfer on the list */\n\t\tif (!list_empty(&engine->transfer_list)) {\n\t\t\ttransfer = list_entry(engine->transfer_list.next,\n\t\t\t\t\tstruct xdma_transfer, entry);\n\t\t\tdbg_tfr(\"Non-completed transfer %p\\n\", transfer);\n\t\t} else {\n\t\t\t/* no further transfers? */\n\t\t\ttransfer = NULL;\n\t\t}\n\t}\n\n\treturn transfer;\n}\n\nstatic void engine_err_handle(struct xdma_engine *engine,\n\t\tstruct xdma_transfer *transfer, u32 desc_completed)\n{\n\tu32 value;\n\n\t/*\n\t * The BUSY bit is expected to be clear now but older HW has a race\n\t * condition which could cause it to be still set.  If it's set, re-read\n\t * and check again.  If it's still set, log the issue.\n\t */\n\tif (engine->status & XDMA_STAT_BUSY) {\n\t\tvalue = read_register(&engine->regs->status);\n\t\tif ((value & XDMA_STAT_BUSY) && printk_ratelimit())\n\t\t\tpr_info(\"%s has errors but is still BUSY\\n\",\n\t\t\t\tengine->name);\n\t}\n\n\tif (printk_ratelimit()) {\n\t\tpr_info(\"%s, s 0x%x, aborted xfer 0x%p, cmpl %d/%d\\n\",\n\t\t\tengine->name, engine->status, transfer, desc_completed,\n\t\t\ttransfer->desc_num);\n\t}\n\t\n\t/* mark transfer as failed */\n\ttransfer->state = TRANSFER_STATE_FAILED;\n\txdma_engine_stop(engine);\n}\n\nstruct xdma_transfer *engine_service_final_transfer(struct xdma_engine *engine,\n\t\t\tstruct xdma_transfer *transfer, u32 *pdesc_completed)\n{\n\tBUG_ON(!engine);\n\tBUG_ON(!pdesc_completed);\n\n\t/* inspect the current transfer */\n\tif (unlikely(!transfer)) {\n\t\tpr_info(\"%s xfer empty, pdesc completed %u.\\n\",\n\t\t\tengine->name, *pdesc_completed);\n\t\treturn NULL;\n\t} else {\n\t\tif (((engine->dir == DMA_FROM_DEVICE) &&\n\t\t     (engine->status & XDMA_STAT_C2H_ERR_MASK)) ||\n\t\t    ((engine->dir == DMA_TO_DEVICE) &&\n\t\t     (engine->status & XDMA_STAT_H2C_ERR_MASK))) {\n\t\t\tpr_info(\"engine %s, status error 0x%x.\\n\",\n\t\t\t\tengine->name, engine->status);\n\t\t\tengine_status_dump(engine);\n\t\t\tengine_err_handle(engine, transfer, *pdesc_completed);\n\t\t\tgoto transfer_del;\n\t\t}\n\n\t\tif (engine->status & XDMA_STAT_BUSY)\n\t\t\tpr_debug(\"engine %s is unexpectedly busy - ignoring\\n\",\n\t\t\t\tengine->name);\n\n\t\t/* the engine stopped on current transfer? */\n\t\tif (*pdesc_completed < transfer->desc_num) {\n\t\t\ttransfer->state = TRANSFER_STATE_FAILED;\n\t\t\tpr_info(\"%s, xfer 0x%p, stopped half-way, %d/%d.\\n\",\n\t\t\t\tengine->name, transfer, *pdesc_completed,\n\t\t\t\ttransfer->desc_num);\n\t\t} else {\n\t\t\tdbg_tfr(\"engine %s completed transfer\\n\", engine->name);\n\t\t\tdbg_tfr(\"Completed transfer ID = 0x%p\\n\", transfer);\n\t\t\tdbg_tfr(\"*pdesc_completed=%d, transfer->desc_num=%d\",\n\t\t\t\t*pdesc_completed, transfer->desc_num);\n\n\t\t\tif (!transfer->cyclic) {\n\t\t\t\t/*\n\t\t\t\t * if the engine stopped on this transfer,\n\t\t\t\t * it should be the last\n\t\t\t\t */\n\t\t\t\tWARN_ON(*pdesc_completed > transfer->desc_num);\n\t\t\t}\n\t\t\t/* mark transfer as succesfully completed */\n\t\t\ttransfer->state = TRANSFER_STATE_COMPLETED;\n\t\t}\n\ntransfer_del:\n\t\t/* remove completed transfer from list */\n\t\tlist_del(engine->transfer_list.next);\n\t\t/* add to dequeued number of descriptors during this run */\n\t\tengine->desc_dequeued += transfer->desc_num;\n\n\t\t/*\n\t\t * Complete transfer - sets transfer to NULL if an asynchronous\n\t\t * transfer has completed\n\t\t */\n\t\ttransfer = engine_transfer_completion(engine, transfer);\n\t} \n\n\treturn transfer;\n}\n\nstatic void engine_service_perf(struct xdma_engine *engine, u32 desc_completed)\n{\n\tBUG_ON(!engine);\n\n\t/* performance measurement is running? */\n\tif (engine->xdma_perf) {\n\t\t/* a descriptor was completed? */\n\t\tif (engine->status & XDMA_STAT_DESC_COMPLETED) {\n\t\t\tengine->xdma_perf->iterations = desc_completed;\n\t\t\tdbg_perf(\"transfer->xdma_perf->iterations=%d\\n\",\n\t\t\t\tengine->xdma_perf->iterations);\n\t\t}\n\n\t\t/* a descriptor stopped the engine? */\n\t\tif (engine->status & XDMA_STAT_DESC_STOPPED) {\n\t\t\tengine->xdma_perf->stopped = 1;\n\t\t\t/*\n\t\t\t * wake any XDMA_PERF_IOCTL_STOP waiting for\n\t\t\t * the performance run to finish\n\t\t\t */\n\t\t\twake_up_interruptible(&engine->xdma_perf_wq);\n\t\t\tdbg_perf(\"transfer->xdma_perf stopped\\n\");\n\t\t}\n\t}\n}\n\nstatic void engine_transfer_dequeue(struct xdma_engine *engine)\n{\n\tstruct xdma_transfer *transfer;\n\n\tBUG_ON(!engine);\n\n\t/* pick first transfer on the queue (was submitted to the engine) */\n\ttransfer = list_entry(engine->transfer_list.next, struct xdma_transfer,\n\t\tentry);\n\tif (!transfer || transfer != &engine->cyclic_req->xfer) {\n\t\tpr_info(\"%s, xfer 0x%p != 0x%p.\\n\",\n\t\t\tengine->name, transfer, &engine->cyclic_req->xfer);\n\t\treturn;\n\t}\n\tdbg_tfr(\"%s engine completed cyclic transfer 0x%p (%d desc).\\n\",\n\t\tengine->name, transfer, transfer->desc_num);\n\t/* remove completed transfer from list */\n\tlist_del(engine->transfer_list.next);\n}\n\nstatic int engine_ring_process(struct xdma_engine *engine)\n{\n\tstruct xdma_result *result;\n\tint start;\n\tint eop_count = 0;\n\n\tBUG_ON(!engine);\n\tresult = engine->cyclic_result;\n\tBUG_ON(!result);\n\n\t/* where we start receiving in the ring buffer */\n\tstart = engine->rx_tail;\n\n\t/* iterate through all newly received RX result descriptors */\n\tdbg_tfr(\"%s, result %d, 0x%x, len 0x%x.\\n\",\n\t\tengine->name, engine->rx_tail, result[engine->rx_tail].status,\n\t\tresult[engine->rx_tail].length);\n\twhile (result[engine->rx_tail].status && !engine->rx_overrun) {\n\t\t/* EOP bit set in result? */\n\t\tif (result[engine->rx_tail].status & RX_STATUS_EOP){\n\t\t\teop_count++;\n\t\t}\n\n\t\t/* increment tail pointer */\n\t\tengine->rx_tail = (engine->rx_tail + 1) % CYCLIC_RX_PAGES_MAX;\n\n\t\tdbg_tfr(\"%s, head %d, tail %d, 0x%x, len 0x%x.\\n\",\n\t\t\tengine->name, engine->rx_head, engine->rx_tail,\n\t\t\tresult[engine->rx_tail].status,\n\t\t\tresult[engine->rx_tail].length);\n\n\t\t/* overrun? */\n\t\tif (engine->rx_tail == engine->rx_head) {\n\t\t\tdbg_tfr(\"%s: overrun\\n\", engine->name);\n\t\t\t/* flag to user space that overrun has occurred */\n\t\t\tengine->rx_overrun = 1;\n\t\t}\n\t}\n\n\treturn eop_count;\n}\n\nstatic int engine_service_cyclic_polled(struct xdma_engine *engine)\n{\n\tint eop_count = 0;\n\tint rc = 0;\n\tstruct xdma_poll_wb *writeback_data;\n\tu32 sched_limit = 0;\n\n\tBUG_ON(!engine);\n\tBUG_ON(engine->magic != MAGIC_ENGINE);\n\n\twriteback_data = (struct xdma_poll_wb *)engine->poll_mode_addr_virt;\n\n\twhile (eop_count == 0) {\n\t\tif (sched_limit != 0) {\n\t\t\tif ((sched_limit % NUM_POLLS_PER_SCHED) == 0)\n\t\t\t\tschedule();\n\t\t}\n\t\tsched_limit++;\n\n\t\t/* Monitor descriptor writeback address for errors */\n\t\tif ((writeback_data->completed_desc_count) & WB_ERR_MASK) {\n\t\t\trc = -1;\n\t\t\tbreak;\n\t\t}\n\n\t\teop_count = engine_ring_process(engine);\n\t}\n\n\tif (eop_count == 0) {\n\t\tengine_status_read(engine, 1, 0);\n\t\tif ((engine->running) && !(engine->status & XDMA_STAT_BUSY)) {\n\t\t\t/* transfers on queue? */\n\t\t\tif (!list_empty(&engine->transfer_list))\n\t\t\t\tengine_transfer_dequeue(engine);\n\n\t\t\tengine_service_shutdown(engine);\n\t\t}\n\t}\n\n\treturn rc;\n}\n\nstatic int engine_service_cyclic_interrupt(struct xdma_engine *engine)\n{\n\tint eop_count = 0;\n\tstruct xdma_transfer *xfer;\n\n\tBUG_ON(!engine);\n\tBUG_ON(engine->magic != MAGIC_ENGINE);\n\n\tengine_status_read(engine, 1, 0);\n\n\teop_count = engine_ring_process(engine);\n\t/*\n\t * wake any reader on EOP, as one or more packets are now in\n\t * the RX buffer\n\t */\n\txfer = &engine->cyclic_req->xfer;\n\tif(enable_credit_mp){\n\t\tif (eop_count > 0) {\n\t\t\t//engine->eop_found = 1;\n\t\t}\n\t\twake_up_interruptible(&xfer->wq);\n\t}else{\n\t\tif (eop_count > 0) {\n\t\t\t/* awake task on transfer's wait queue */\n\t\t\tdbg_tfr(\"wake_up_interruptible() due to %d EOP's\\n\", eop_count);\n\t\t\tengine->eop_found = 1;\n\t\t\twake_up_interruptible(&xfer->wq);\n\t\t}\n\t}\n\n\t/* engine was running but is no longer busy? */\n\tif ((engine->running) && !(engine->status & XDMA_STAT_BUSY)) {\n\t\t/* transfers on queue? */\n\t\tif (!list_empty(&engine->transfer_list))\n\t\t\tengine_transfer_dequeue(engine);\n\n\t\tengine_service_shutdown(engine);\n\t}\n\n\treturn 0;\n}\n\n/* must be called with engine->lock already acquired */\nstatic int engine_service_cyclic(struct xdma_engine *engine)\n{\n\tint rc = 0;\n\n\tdbg_tfr(\"engine_service_cyclic()\");\n\n\tBUG_ON(!engine);\n\tBUG_ON(engine->magic != MAGIC_ENGINE);\n\n\tif (poll_mode)\n\t\trc = engine_service_cyclic_polled(engine);\n\telse\n\t\trc = engine_service_cyclic_interrupt(engine);\n\n\treturn rc;\n}\n\n\nstatic void engine_service_resume(struct xdma_engine *engine)\n{\n\tstruct xdma_transfer *transfer_started;\n\n\tBUG_ON(!engine);\n\n\t/* engine stopped? */\n\tif (!engine->running) {\n\t\t/* in the case of shutdown, let it finish what's in the Q */\n\t\tif (!list_empty(&engine->transfer_list)) {\n\t\t\t/* (re)start engine */\n\t\t\ttransfer_started = engine_start(engine);\n\t\t\tpr_info(\"re-started %s engine with pending xfer 0x%p\\n\",\n\t\t\t\tengine->name, transfer_started);\n\t\t/* engine was requested to be shutdown? */\n\t\t} else if (engine->shutdown & ENGINE_SHUTDOWN_REQUEST) {\n\t\t\tengine->shutdown |= ENGINE_SHUTDOWN_IDLE;\n\t\t\t/* awake task on engine's shutdown wait queue */\n\t\t\twake_up_interruptible(&engine->shutdown_wq);\n\t\t} else {\n\t\t\tdbg_tfr(\"no pending transfers, %s engine stays idle.\\n\",\n\t\t\t\tengine->name);\n\t\t}\n\t} else {\n\t\t/* engine is still running? */\n\t\tif (list_empty(&engine->transfer_list)) {\n\t\t\tpr_warn(\"no queued transfers but %s engine running!\\n\",\n\t\t\t\tengine->name);\n\t\t\tWARN_ON(1);\n\t\t}\n\t}\n}\n\n/**\n * engine_service() - service an SG DMA engine\n *\n * must be called with engine->lock already acquired\n *\n * @engine pointer to struct xdma_engine\n *\n */\nstatic int engine_service(struct xdma_engine *engine, int desc_writeback)\n{\n\tstruct xdma_transfer *transfer = NULL;\n\tu32 desc_count = desc_writeback & WB_COUNT_MASK;\n\tu32 err_flag = desc_writeback & WB_ERR_MASK;\n\tint rv = 0;\n\tstruct xdma_poll_wb *wb_data;\n\n\tBUG_ON(!engine);\n\n\t/* If polling detected an error, signal to the caller */\n\tif (err_flag)\n\t\trv = -1;\n\n\t/* Service the engine */\n\tif (!engine->running) {\n\t\tdbg_tfr(\"Engine was not running!!! Clearing status\\n\");\n\t\tengine_status_read(engine, 1, 0);\n\t\treturn 0;\n\t}\n\n\t/*\n\t * If called by the ISR or polling detected an error, read and clear\n\t * engine status. For polled mode descriptor completion, this read is\n\t * unnecessary and is skipped to reduce latency\n\t */\n\tif ((desc_count == 0) || (err_flag != 0))\n\t\tengine_status_read(engine, 1, 0);\n\n\t/*\n\t * engine was running but is no longer busy, or writeback occurred,\n\t * shut down\n\t */\n\tif ((engine->running && !(engine->status & XDMA_STAT_BUSY)) ||\n\t\t(desc_count != 0))\n\t\tengine_service_shutdown(engine);\n\n\t/*\n\t * If called from the ISR, or if an error occurred, the descriptor\n\t * count will be zero.  In this scenario, read the descriptor count\n\t * from HW.  In polled mode descriptor completion, this read is\n\t * unnecessary and is skipped to reduce latency\n\t */\n\tif (!desc_count)\n\t\tdesc_count = read_register(&engine->regs->completed_desc_count);\n\tdbg_tfr(\"desc_count = %d\\n\", desc_count);\n\n\t/* transfers on queue? */\n\tif (!list_empty(&engine->transfer_list)) {\n\t\t/* pick first transfer on queue (was submitted to the engine) */\n\t\ttransfer = list_entry(engine->transfer_list.next,\n\t\t\t\tstruct xdma_transfer, entry);\n\n\t\tdbg_tfr(\"head of queue transfer 0x%p has %d descriptors\\n\",\n\t\t\ttransfer, (int)transfer->desc_num);\n\n\t\tdbg_tfr(\"Engine completed %d desc, %d not yet dequeued\\n\",\n\t\t\t(int)desc_count,\n\t\t\t(int)desc_count - engine->desc_dequeued);\n\n\t\tengine_service_perf(engine, desc_count);\n\t}\n\n\t/* account for already dequeued transfers during this engine run */\n\tdesc_count -= engine->desc_dequeued;\n\n\t/* Process all but the last transfer */\n\ttransfer = engine_service_transfer_list(engine, transfer, &desc_count);\n\n\t/*\n\t * Process final transfer - includes checks of number of descriptors to\n\t * detect faulty completion\n\t */\n\ttransfer = engine_service_final_transfer(engine, transfer, &desc_count);\n\n\t/* Before starting engine again, clear the writeback data */\n        if (poll_mode) {\n\t\twb_data = (struct xdma_poll_wb *)engine->poll_mode_addr_virt;\n\t\twb_data->completed_desc_count = 0;\n\t}\n\n\t/* Restart the engine following the servicing */\n\tengine_service_resume(engine);\n\n\treturn 0;\n}\n\n/* engine_service_work */\nstatic void engine_service_work(struct work_struct *work)\n{\n\tstruct xdma_engine *engine;\n\tunsigned long flags;\n\n\tengine = container_of(work, struct xdma_engine, work);\n\tBUG_ON(engine->magic != MAGIC_ENGINE);\n\n\t/* lock the engine */\n\tspin_lock_irqsave(&engine->lock, flags);\n\n\tdbg_tfr(\"engine_service() for %s engine %p\\n\",\n\t\tengine->name, engine);\n\tif (engine->cyclic_req)\n                engine_service_cyclic(engine);\n\telse\n\t\tengine_service(engine, 0);\n\n\t/* re-enable interrupts for this engine */\n\tif (engine->xdev->msix_enabled){\n\t\twrite_register(engine->interrupt_enable_mask_value,\n\t\t\t       &engine->regs->interrupt_enable_mask_w1s,\n\t\t\t(unsigned long)(&engine->regs->interrupt_enable_mask_w1s) -\n\t\t\t(unsigned long)(&engine->regs));\n\t} else\n\t\tchannel_interrupts_enable(engine->xdev, engine->irq_bitmask);\n\t\t\n\t/* unlock the engine */\n\tspin_unlock_irqrestore(&engine->lock, flags);\n}\n\nstatic u32 engine_service_wb_monitor(struct xdma_engine *engine,\n\tu32 expected_wb)\n{\n\tstruct xdma_poll_wb *wb_data;\n\tu32 desc_wb = 0;\n\tu32 sched_limit = 0;\n\tunsigned long timeout;\n\n\tBUG_ON(!engine);\n\twb_data = (struct xdma_poll_wb *)engine->poll_mode_addr_virt;\n\n\t/*\n \t * Poll the writeback location for the expected number of\n \t * descriptors / error events This loop is skipped for cyclic mode,\n \t * where the expected_desc_count passed in is zero, since it cannot be\n \t * determined before the function is called\n \t */\n\n\ttimeout = jiffies + (POLL_TIMEOUT_SECONDS * HZ);\n\twhile (expected_wb != 0) {\n\t\tdesc_wb = wb_data->completed_desc_count;\n\n\t\tif (desc_wb & WB_ERR_MASK)\n\t\t\tbreak;\n\t\telse if (desc_wb == expected_wb)\n\t\t\tbreak;\n\t\t\t\n\t\t/* RTO - prevent system from hanging in polled mode */\n\t\tif (time_after(jiffies, timeout)) {\n\t\t\tdbg_tfr(\"Polling timeout occurred\");\n\t\t\tdbg_tfr(\"desc_wb = 0x%08x, expected 0x%08x\\n\", desc_wb,\n\t\t\t\texpected_wb);\n\t\t\tif ((desc_wb & WB_COUNT_MASK) > expected_wb)\n\t\t\t\tdesc_wb = expected_wb | WB_ERR_MASK;\n\n\t\t\tbreak;\n\t\t}\n\n\t\t/*\n \t\t * Define NUM_POLLS_PER_SCHED to limit how much time is spent\n \t\t * in the scheduler\n \t\t */\n\n\t\tif (sched_limit != 0) {\n\t\t\tif ((sched_limit % NUM_POLLS_PER_SCHED) == 0)\n\t\t\t\tschedule();\n\t\t}\n\t\tsched_limit++;\n\t}\n\n\treturn desc_wb;\n}\n\nstatic int engine_service_poll(struct xdma_engine *engine,\n                u32 expected_desc_count)\n{\n\tstruct xdma_poll_wb *writeback_data;\n\tu32 desc_wb = 0;\n\tunsigned long flags;\n\tint rv = 0;\n\n\tBUG_ON(!engine);\n\tBUG_ON(engine->magic != MAGIC_ENGINE);\n\n\twriteback_data = (struct xdma_poll_wb *)engine->poll_mode_addr_virt;\n\n\tif ((expected_desc_count & WB_COUNT_MASK) != expected_desc_count) {\n\t\tdbg_tfr(\"Queued descriptor count is larger than supported\\n\");\n\t\treturn -1;\n\t}\n\n\t/*\n \t * Poll the writeback location for the expected number of\n \t * descriptors / error events This loop is skipped for cyclic mode,\n \t * where the expected_desc_count passed in is zero, since it cannot be\n \t * determined before the function is called\n \t */\n\n\tdesc_wb = engine_service_wb_monitor(engine, expected_desc_count);\n\n\tspin_lock_irqsave(&engine->lock, flags);\n\tdbg_tfr(\"%s service.\\n\", engine->name);\n\tif (engine->cyclic_req) {\n\t\trv = engine_service_cyclic(engine);\n\t} else {\n\t\trv = engine_service(engine, desc_wb);\n\t}\n\tspin_unlock_irqrestore(&engine->lock, flags);\n\n\treturn rv;\n}\n\nstatic irqreturn_t user_irq_service(int irq, struct xdma_user_irq *user_irq)\n{\n\tunsigned long flags;\n\n\tBUG_ON(!user_irq);\n\n\tif (user_irq->handler)\n\t\treturn user_irq->handler(user_irq->user_idx, user_irq->dev);\n\n\tspin_lock_irqsave(&(user_irq->events_lock), flags);\n\tif (!user_irq->events_irq) {\n\t\tuser_irq->events_irq = 1;\n\t\twake_up_interruptible(&(user_irq->events_wq));\n\t}\n\tspin_unlock_irqrestore(&(user_irq->events_lock), flags);\n\n\treturn IRQ_HANDLED;\n}\n\n/*\n * xdma_isr() - Interrupt handler\n *\n * @dev_id pointer to xdma_dev\n */\nstatic irqreturn_t xdma_isr(int irq, void *dev_id)\n{\n\tu32 ch_irq;\n\tu32 user_irq;\n\tu32 mask;\n\tstruct xdma_dev *xdev;\n\tstruct interrupt_regs *irq_regs;\n\n\tdbg_irq(\"(irq=%d, dev 0x%p) <<<< ISR.\\n\", irq, dev_id);\n\tBUG_ON(!dev_id);\n\txdev = (struct xdma_dev *)dev_id;\n\n\tif (!xdev) {\n\t\tWARN_ON(!xdev);\n\t\tdbg_irq(\"xdma_isr(irq=%d) xdev=%p ??\\n\", irq, xdev);\n\t\treturn IRQ_NONE;\n\t}\n\n\tirq_regs = (struct interrupt_regs *)(xdev->bar[xdev->config_bar_idx] +\n\t\t\tXDMA_OFS_INT_CTRL);\n\n\t/* read channel interrupt requests */\n\tch_irq = read_register(&irq_regs->channel_int_request);\n\tdbg_irq(\"ch_irq = 0x%08x\\n\", ch_irq);\n\n\t/*\n\t * disable all interrupts that fired; these are re-enabled individually\n\t * after the causing module has been fully serviced.\n\t */\n\tif (ch_irq)\n\t\tchannel_interrupts_disable(xdev, ch_irq);\n\n\t/* read user interrupts - this read also flushes the above write */\n\tuser_irq = read_register(&irq_regs->user_int_request);\n\tdbg_irq(\"user_irq = 0x%08x\\n\", user_irq);\n\n\tif (user_irq) {\n\t\tint user = 0;\n                u32 mask = 1;\n\t\tint max = xdev->h2c_channel_max;\n\n\t\tfor (; user < max && user_irq; user++, mask <<= 1) {\n\t\t\tif (user_irq & mask) {\n\t\t\t\tuser_irq &= ~mask;\n\t\t\t\tuser_irq_service(irq, &xdev->user_irq[user]);\n\t\t\t}\n\t\t}\n\t}\n\n\tmask = ch_irq & xdev->mask_irq_h2c;\n\tif (mask) {\n\t\tint channel = 0;\n\t\tint max = xdev->h2c_channel_max;\n\n\t\t/* iterate over H2C (PCIe read) */\n\t\tfor (channel = 0; channel < max && mask; channel++) {\n\t\t\tstruct xdma_engine *engine = &xdev->engine_h2c[channel];\n\n\t\t\t/* engine present and its interrupt fired? */\n\t\t\tif((engine->irq_bitmask & mask) &&\n\t\t\t   (engine->magic == MAGIC_ENGINE)) {\n\t\t\t\tmask &= ~engine->irq_bitmask;\n\t\t\t\tdbg_tfr(\"schedule_work, %s.\\n\", engine->name);\n\t\t\t\tschedule_work(&engine->work);\n\t\t\t}\n\t\t}\n\t}\n\n\tmask = ch_irq & xdev->mask_irq_c2h;\n\tif (mask) {\n\t\tint channel = 0;\n\t\tint max = xdev->c2h_channel_max;\n\n\t\t/* iterate over C2H (PCIe write) */\n\t\tfor (channel = 0; channel < max && mask; channel++) {\n\t\t\tstruct xdma_engine *engine = &xdev->engine_c2h[channel];\n\n\t\t\t/* engine present and its interrupt fired? */\n\t\t\tif((engine->irq_bitmask & mask) &&\n\t\t\t   (engine->magic == MAGIC_ENGINE)) {\n\t\t\t\tmask &= ~engine->irq_bitmask;\n\t\t\t\tdbg_tfr(\"schedule_work, %s.\\n\", engine->name);\n\t\t\t\tschedule_work(&engine->work);\n\t\t\t}\n\t\t}\n\t}\n\n\txdev->irq_count++;\n\treturn IRQ_HANDLED;\n}\n\n/*\n * xdma_user_irq() - Interrupt handler for user interrupts in MSI-X mode\n *\n * @dev_id pointer to xdma_dev\n */\nstatic irqreturn_t xdma_user_irq(int irq, void *dev_id)\n{\n\tstruct xdma_user_irq *user_irq;\n\n\tdbg_irq(\"(irq=%d) <<<< INTERRUPT SERVICE ROUTINE\\n\", irq);\n\n\tBUG_ON(!dev_id);\n\tuser_irq = (struct xdma_user_irq *)dev_id;\n\n\treturn  user_irq_service(irq, user_irq);\n}\n\n/*\n * xdma_channel_irq() - Interrupt handler for channel interrupts in MSI-X mode\n *\n * @dev_id pointer to xdma_dev\n */\nstatic irqreturn_t xdma_channel_irq(int irq, void *dev_id)\n{\n\tstruct xdma_dev *xdev;\n\tstruct xdma_engine *engine;\n\tstruct interrupt_regs *irq_regs;\n\n\tdbg_irq(\"(irq=%d) <<<< INTERRUPT service ROUTINE\\n\", irq);\n\tBUG_ON(!dev_id);\n\n\tengine = (struct xdma_engine *)dev_id;\n\txdev = engine->xdev;\n\n\tif (!xdev) {\n\t\tWARN_ON(!xdev);\n\t\tdbg_irq(\"xdma_channel_irq(irq=%d) xdev=%p ??\\n\", irq, xdev);\n\t\treturn IRQ_NONE;\n\t}\n\n\tirq_regs = (struct interrupt_regs *)(xdev->bar[xdev->config_bar_idx] +\n\t\t\tXDMA_OFS_INT_CTRL);\n\n\t/* Disable the interrupt for this engine */\n\twrite_register(engine->interrupt_enable_mask_value,\n\t\t\t&engine->regs->interrupt_enable_mask_w1c,\n\t\t\t(unsigned long)\n\t\t\t(&engine->regs->interrupt_enable_mask_w1c) -\n\t\t\t(unsigned long)(&engine->regs));\n\t/* Dummy read to flush the above write */\n\tread_register(&irq_regs->channel_int_pending);\n\t/* Schedule the bottom half */\n\tschedule_work(&engine->work);\n\n\t/*\n\t * RTO - need to protect access here if multiple MSI-X are used for\n\t * user interrupts\n\t */\n\txdev->irq_count++;\n\treturn IRQ_HANDLED;\n}\n\n/*\n * Unmap the BAR regions that had been mapped earlier using map_bars()\n */\nstatic void unmap_bars(struct xdma_dev *xdev, struct pci_dev *dev)\n{\n\tint i;\n\n\tfor (i = 0; i < XDMA_BAR_NUM; i++) {\n\t\t/* is this BAR mapped? */\n\t\tif (xdev->bar[i]) {\n\t\t\t/* unmap BAR */\n\t\t\tpci_iounmap(dev, xdev->bar[i]);\n\t\t\t/* mark as unmapped */\n\t\t\txdev->bar[i] = NULL;\n\t\t}\n\t}\n}\n\nstatic int map_single_bar(struct xdma_dev *xdev, struct pci_dev *dev, int idx)\n{\n\tresource_size_t bar_start;\n\tresource_size_t bar_len;\n\tresource_size_t map_len;\n\n\tbar_start = pci_resource_start(dev, idx);\n\tbar_len = pci_resource_len(dev, idx);\n\tmap_len = bar_len;\n\n\txdev->bar[idx] = NULL;\n\n\t/* do not map BARs with length 0. Note that start MAY be 0! */\n\tif (!bar_len) {\n\t\t//pr_info(\"BAR #%d is not present - skipping\\n\", idx);\n\t\treturn 0;\n\t}\n\n\t/* BAR size exceeds maximum desired mapping? */\n\tif (bar_len > INT_MAX) {\n\t\tpr_info(\"Limit BAR %d mapping from %llu to %d bytes\\n\", idx,\n\t\t\t(u64)bar_len, INT_MAX);\n\t\tmap_len = (resource_size_t)INT_MAX;\n\t}\n\t/*\n\t * map the full device memory or IO region into kernel virtual\n\t * address space\n\t */\n\tdbg_init(\"BAR%d: %llu bytes to be mapped.\\n\", idx, (u64)map_len);\n\txdev->bar[idx] = pci_iomap(dev, idx, map_len);\n\n\tif (!xdev->bar[idx]) {\n\t\tpr_info(\"Could not map BAR %d.\\n\", idx);\n\t\treturn -1;\n\t}\n\n\tpr_info(\"BAR%d at 0x%llx mapped at 0x%p, length=%llu(/%llu)\\n\", idx,\n\t\t(u64)bar_start, xdev->bar[idx], (u64)map_len, (u64)bar_len);\n\n\treturn (int)map_len;\n}\n\nstatic int is_config_bar(struct xdma_dev *xdev, int idx)\n{\n\tu32 irq_id = 0;\n\tu32 cfg_id = 0;\n\tint flag = 0;\n\tu32 mask = 0xffff0000; /* Compare only XDMA ID's not Version number */\n\tstruct interrupt_regs *irq_regs =\n\t\t(struct interrupt_regs *) (xdev->bar[idx] + XDMA_OFS_INT_CTRL);\n\tstruct config_regs *cfg_regs =\n\t\t(struct config_regs *)(xdev->bar[idx] + XDMA_OFS_CONFIG);\n\n\tirq_id = read_register(&irq_regs->identifier);\n\tcfg_id = read_register(&cfg_regs->identifier);\n\n\tif (((irq_id & mask)== IRQ_BLOCK_ID) &&\n\t    ((cfg_id & mask)== CONFIG_BLOCK_ID)) {\n\t\tdbg_init(\"BAR %d is the XDMA config BAR\\n\", idx);\n\t\tflag = 1;\n\t} else {\n\t\tdbg_init(\"BAR %d is NOT the XDMA config BAR: 0x%x, 0x%x.\\n\",\n\t\t\tidx, irq_id, cfg_id);\n\t\tflag = 0;\n\t}\n\n\treturn flag;\n}\n\nstatic void identify_bars(struct xdma_dev *xdev, int *bar_id_list, int num_bars,\n\t\t\tint config_bar_pos)\n{\n\t/*\n\t * The following logic identifies which BARs contain what functionality\n\t * based on the position of the XDMA config BAR and the number of BARs\n\t * detected. The rules are that the user logic and bypass logic BARs\n\t * are optional.  When both are present, the XDMA config BAR will be the\n\t * 2nd BAR detected (config_bar_pos = 1), with the user logic being\n\t * detected first and the bypass being detected last. When one is\n\t * omitted, the type of BAR present can be identified by whether the\n\t * XDMA config BAR is detected first or last.  When both are omitted,\n\t * only the XDMA config BAR is present.  This somewhat convoluted\n\t * approach is used instead of relying on BAR numbers in order to work\n\t * correctly with both 32-bit and 64-bit BARs.\n\t */\n\n\tBUG_ON(!xdev);\n\tBUG_ON(!bar_id_list);\n\n\tdbg_init(\"xdev 0x%p, bars %d, config at %d.\\n\",\n\t\txdev, num_bars, config_bar_pos);\n\n\tswitch (num_bars) {\n\tcase 1:\n\t\t/* Only one BAR present - no extra work necessary */\n\t\tbreak;\n\n\tcase 2:\n\t\tif (config_bar_pos == 0) {\n\t\t\txdev->bypass_bar_idx = bar_id_list[1];\n\t\t} else if (config_bar_pos == 1) {\n\t\t\txdev->user_bar_idx = bar_id_list[0];\n\t\t} else {\n\t\t\tpr_info(\"2, XDMA config BAR unexpected %d.\\n\",\n\t\t\t\tconfig_bar_pos);\n\t\t}\n\t\tbreak;\n\n\tcase 3:\n\tcase 4:\n\t\tif ((config_bar_pos == 1) || (config_bar_pos == 2)) {\n\t\t\t/* user bar at bar #0 */\n\t\t\txdev->user_bar_idx = bar_id_list[0];\n\t\t\t/* bypass bar at the last bar */\n\t\t\txdev->bypass_bar_idx = bar_id_list[num_bars - 1];\n\t\t} else {\n\t\t\tpr_info(\"3/4, XDMA config BAR unexpected %d.\\n\",\n\t\t\t\tconfig_bar_pos);\n\t\t}\n\t\tbreak;\n\n\tdefault:\n\t\t/* Should not occur - warn user but safe to continue */\n\t\tpr_info(\"Unexpected # BARs (%d), XDMA config BAR only.\\n\",\n\t\t\tnum_bars);\n\t\tbreak;\n\n\t}\n\tpr_info(\"%d BARs: config %d, user %d, bypass %d.\\n\",\n\t\tnum_bars, config_bar_pos, xdev->user_bar_idx,\n\t\txdev->bypass_bar_idx);\n}\n\n/* map_bars() -- map device regions into kernel virtual address space\n *\n * Map the device memory regions into kernel virtual address space after\n * verifying their sizes respect the minimum sizes needed\n */\nstatic int map_bars(struct xdma_dev *xdev, struct pci_dev *dev)\n{\n\tint rv;\n\tint i;\n\tint bar_id_list[XDMA_BAR_NUM];\n\tint bar_id_idx = 0;\n\tint config_bar_pos = 0;\n\n\t/* iterate through all the BARs */\n\tfor (i = 0; i < XDMA_BAR_NUM; i++) {\n\t\tint bar_len;\n\n\t\tbar_len = map_single_bar(xdev, dev, i);\n\t\tif (bar_len == 0) {\n\t\t\tcontinue;\n\t\t} else if (bar_len < 0) {\n\t\t\trv = -EINVAL;\n\t\t\tgoto fail;\n\t\t}\n\n\t\t/* Try to identify BAR as XDMA control BAR */\n\t\tif ((bar_len >= XDMA_BAR_SIZE) && (xdev->config_bar_idx < 0) && i == XDMA_CONFIG_BAR_NUM) {\n\n\t\t\tif (is_config_bar(xdev, i)) {\n\t\t\t\txdev->config_bar_idx = i;\n\t\t\t\tconfig_bar_pos = bar_id_idx;\n\t\t\t\tpr_info(\"config bar %d, pos %d.\\n\",\n\t\t\t\t\txdev->config_bar_idx, config_bar_pos);\n\t\t\t}\n\t\t}\n\n\t\tbar_id_list[bar_id_idx] = i;\n\t\tbar_id_idx++;\n\t}\n\n\t/* The XDMA config BAR must always be present */\n\tif (xdev->config_bar_idx < 0) {\n\t\tpr_info(\"Failed to detect XDMA config BAR\\n\");\n\t\trv = -EINVAL;\n\t\tgoto fail;\n\t}\n\n\tidentify_bars(xdev, bar_id_list, bar_id_idx, config_bar_pos);\n\n\t/* successfully mapped all required BAR regions */\n\treturn 0;\n\nfail:\n\t/* unwind; unmap any BARs that we did map */\n\tunmap_bars(xdev, dev);\n\treturn rv;\n}\n\n/*\n * MSI-X interrupt: \n *\t<h2c+c2h channel_max> vectors, followed by <user_max> vectors\n */\n\n/*\n * RTO - code to detect if MSI/MSI-X capability exists is derived\n * from linux/pci/msi.c - pci_msi_check_device\n */\n\n#ifndef arch_msi_check_device\nint arch_msi_check_device(struct pci_dev *dev, int nvec, int type)\n{\n\treturn 0;\n}\n#endif\n\n/* type = PCI_CAP_ID_MSI or PCI_CAP_ID_MSIX */\nstatic int msi_msix_capable(struct pci_dev *dev, int type)\n{\n\tstruct pci_bus *bus;\n\tint ret;\n\n\tif (!dev || dev->no_msi)\n\t\treturn 0;\n\n\tfor (bus = dev->bus; bus; bus = bus->parent)\n\t\tif (bus->bus_flags & PCI_BUS_FLAGS_NO_MSI)\n\t\t\treturn 0;\n\n\tret = arch_msi_check_device(dev, 1, type);\n\tif (ret)\n\t\treturn 0;\n\n\tif (!pci_find_capability(dev, type))\n\t\treturn 0;\n\n\treturn 1;\n}\n\nstatic void disable_msi_msix(struct xdma_dev *xdev, struct pci_dev *pdev)\n{\n\tif (xdev->msix_enabled) {\n\t\tpci_disable_msix(pdev);\n\t\txdev->msix_enabled = 0;\n\t} else if (xdev->msi_enabled) {\n\t\tpci_disable_msi(pdev);\n\t\txdev->msi_enabled = 0;\n\t}\n}\n\nstatic int enable_msi_msix(struct xdma_dev *xdev, struct pci_dev *pdev)\n{\n\tint rv = 0;\n\n\tBUG_ON(!xdev);\n\tBUG_ON(!pdev);\n\n\tif (!interrupt_mode && msi_msix_capable(pdev, PCI_CAP_ID_MSIX)) {\n\t\tint req_nvec = xdev->c2h_channel_max + xdev->h2c_channel_max +\n\t\t\t\t xdev->user_max;\n\n#if LINUX_VERSION_CODE >= KERNEL_VERSION(4,12,0)\n\t\tdbg_init(\"Enabling MSI-X\\n\");\n\t\trv = pci_alloc_irq_vectors(pdev, req_nvec, req_nvec,\n\t\t\t\t\tPCI_IRQ_MSIX);\n#else\n\t\tint i;\n\n\t\tdbg_init(\"Enabling MSI-X\\n\");\n\t\tfor (i = 0; i < req_nvec; i++)\n\t\t\txdev->entry[i].entry = i;\n\n\t\trv = pci_enable_msix(pdev, xdev->entry, req_nvec);\n#endif\n\t\tif (rv < 0)\n\t\t\tdbg_init(\"Couldn't enable MSI-X mode: %d\\n\", rv);\n\n\t\txdev->msix_enabled = 1;\n\n\t} else if (interrupt_mode == 1 &&\n\t\t   msi_msix_capable(pdev, PCI_CAP_ID_MSI)) {\n\t\t/* enable message signalled interrupts */\n\t\tdbg_init(\"pci_enable_msi()\\n\");\n\t\trv = pci_enable_msi(pdev);\n\t\tif (rv < 0)\n\t\t\tdbg_init(\"Couldn't enable MSI mode: %d\\n\", rv);\n\t\txdev->msi_enabled = 1;\n\n\t} else {\n\t\tdbg_init(\"MSI/MSI-X not detected - using legacy interrupts\\n\");\n\t}\n\n\treturn rv;\n}\n\nstatic void pci_check_intr_pend(struct pci_dev *pdev)\n{\n\tu16 v;\n\n\tpci_read_config_word(pdev, PCI_STATUS, &v);\n\tif (v & PCI_STATUS_INTERRUPT) {\n\t\tpr_info(\"%s PCI STATUS Interrupt pending 0x%x.\\n\",\n                        dev_name(&pdev->dev), v);\n\t\tpci_write_config_word(pdev, PCI_STATUS, PCI_STATUS_INTERRUPT);\n\t}\n}\n\nstatic void pci_keep_intx_enabled(struct pci_dev *pdev)\n{\n\t/* workaround to a h/w bug:\n\t * when msix/msi become unavaile, default to legacy.\n\t * However the legacy enable was not checked.\n\t * If the legacy was disabled, no ack then everything stuck\n\t */\n\tu16 pcmd, pcmd_new;\n\n\tpci_read_config_word(pdev, PCI_COMMAND, &pcmd);\n\tpcmd_new = pcmd & ~PCI_COMMAND_INTX_DISABLE;\n\tif (pcmd_new != pcmd) {\n\t\tpr_info(\"%s: clear INTX_DISABLE, 0x%x -> 0x%x.\\n\",\n\t\t\tdev_name(&pdev->dev), pcmd, pcmd_new);\n\t\tpci_write_config_word(pdev, PCI_COMMAND, pcmd_new);\n\t}\n}\n\nstatic void prog_irq_msix_user(struct xdma_dev *xdev, bool clear)\n{\n\t/* user */\n\tstruct interrupt_regs *int_regs = (struct interrupt_regs *)\n\t\t\t\t\t(xdev->bar[xdev->config_bar_idx] +\n\t\t\t\t\t XDMA_OFS_INT_CTRL);\n\tu32 i = xdev->c2h_channel_max + xdev->h2c_channel_max;\n\tu32 max = i + xdev->user_max;\n\tint j;\n\n\tfor (j = 0; i < max; j++) {\n\t\tu32 val = 0;\n\t\tint k;\n\t\tint shift = 0;\n\n\t\tif (clear)\n\t\t\ti += 4;\n\t\telse\n\t\t\tfor (k = 0; k < 4 && i < max; i++, k++, shift += 8)\n\t\t\t\tval |= (i & 0x1f) << shift;\n\t\t\n\t\twrite_register(val, &int_regs->user_msi_vector[j],\n\t\t\tXDMA_OFS_INT_CTRL +\n\t\t\t((unsigned long)&int_regs->user_msi_vector[j] -\n\t\t\t (unsigned long)int_regs));\n\n\t\tdbg_init(\"vector %d, 0x%x.\\n\", j, val);\n\t}\n}\n\nstatic void prog_irq_msix_channel(struct xdma_dev *xdev, bool clear) \n{\n\tstruct interrupt_regs *int_regs = (struct interrupt_regs *)\n\t\t\t\t\t(xdev->bar[xdev->config_bar_idx] +\n\t\t\t\t\t XDMA_OFS_INT_CTRL);\n\tu32 max = xdev->c2h_channel_max + xdev->h2c_channel_max;\n\tu32 i;\n\tint j;\n\n\t/* engine */\n\tfor (i = 0, j = 0; i < max; j++) {\n\t\tu32 val = 0;\n\t\tint k;\n\t\tint shift = 0;\n\n\t\tif (clear)\n\t\t\ti += 4;\n\t\telse\n\t\t\tfor (k = 0; k < 4 && i < max; i++, k++, shift += 8)\n\t\t\t\tval |= (i & 0x1f) << shift;\n\t\t\n\t\twrite_register(val, &int_regs->channel_msi_vector[j],\n\t\t\tXDMA_OFS_INT_CTRL +\n\t\t\t((unsigned long)&int_regs->channel_msi_vector[j] -\n\t\t\t (unsigned long)int_regs));\n\t\tdbg_init(\"vector %d, 0x%x.\\n\", j, val);\n\t}\n}\n\nstatic void irq_msix_channel_teardown(struct xdma_dev *xdev)\n{\n\tstruct xdma_engine *engine;\n\tint j = 0;\n\tint i = 0;\n\n\tif (!xdev->msix_enabled)\n\t\treturn;\n\n\tprog_irq_msix_channel(xdev, 1);\n\n \tengine = xdev->engine_h2c;\n\tfor (i = 0; i < xdev->h2c_channel_max; i++, j++, engine++) {\n\t\tif (!engine->msix_irq_line)\n\t\t\tbreak;\n\t\tdbg_sg(\"Release IRQ#%d for engine %p\\n\", engine->msix_irq_line,\n\t\t\tengine);\n\t\tfree_irq(engine->msix_irq_line, engine);\n\t}\n\n \tengine = xdev->engine_c2h;\n\tfor (i = 0; i < xdev->c2h_channel_max; i++, j++, engine++) {\n\t\tif (!engine->msix_irq_line)\n\t\t\tbreak;\n\t\tdbg_sg(\"Release IRQ#%d for engine %p\\n\", engine->msix_irq_line,\n\t\t\tengine);\n\t\tfree_irq(engine->msix_irq_line, engine);\n\t}\n}\n\nstatic int irq_msix_channel_setup(struct xdma_dev *xdev)\n{\n\tint i;\n\tint j = xdev->h2c_channel_max;\n\tint rv = 0;\n\tu32 vector;\n\tstruct xdma_engine *engine;\n\n\tBUG_ON(!xdev);\n\tif (!xdev->msix_enabled)\n\t\treturn 0;\n\n\tengine = xdev->engine_h2c;\n\tfor (i = 0; i < xdev->h2c_channel_max; i++, engine++) {\n#if LINUX_VERSION_CODE >= KERNEL_VERSION(4,12,0)\n\t\tvector = pci_irq_vector(xdev->pdev, i);\n#else\n\t\tvector = xdev->entry[i].vector;\n#endif\n\t\trv = request_irq(vector, xdma_channel_irq, 0, xdev->mod_name,\n\t\t\t\t engine);\n\t\tif (rv) {\n\t\t\tpr_info(\"requesti irq#%d failed %d, engine %s.\\n\",\n\t\t\t\tvector, rv, engine->name);\n\t\t\treturn rv;\n\t\t}\n\t\tpr_info(\"engine %s, irq#%d.\\n\", engine->name, vector);\n\t\tengine->msix_irq_line = vector;\n\t}\n\n\tengine = xdev->engine_c2h;\n\tfor (i = 0; i < xdev->c2h_channel_max; i++, j++, engine++) {\n#if LINUX_VERSION_CODE >= KERNEL_VERSION(4,12,0)\n\t\tvector = pci_irq_vector(xdev->pdev, j);\n#else\n\t\tvector = xdev->entry[j].vector;\n#endif\n\t\trv = request_irq(vector, xdma_channel_irq, 0, xdev->mod_name,\n\t\t\t\t engine);\n\t\tif (rv) {\n\t\t\tpr_info(\"requesti irq#%d failed %d, engine %s.\\n\",\n\t\t\t\tvector, rv, engine->name);\n\t\t\treturn rv;\n\t\t}\n\t\tpr_info(\"engine %s, irq#%d.\\n\", engine->name, vector);\n\t\tengine->msix_irq_line = vector;\n\t}\n\n\treturn 0;\n}\n\nstatic void irq_msix_user_teardown(struct xdma_dev *xdev)\n{\n\tint i;\n\tint j = xdev->h2c_channel_max + xdev->c2h_channel_max;\n\n\tBUG_ON(!xdev);\n\n\tif (!xdev->msix_enabled)\n\t\treturn;\n\n\tprog_irq_msix_user(xdev, 1);\n\n\tif (0)\n\tfor (i = 0; i < xdev->user_max; i++, j++) {\n#if LINUX_VERSION_CODE >= KERNEL_VERSION(4,12,0)\n\t\tu32 vector = pci_irq_vector(xdev->pdev, j);\n#else\n\t\tu32 vector = xdev->entry[j].vector;\n#endif\n\t\tdbg_init(\"user %d, releasing IRQ#%d\\n\", i, vector);\n\t\tfree_irq(vector, &xdev->user_irq[i]);\n\t}\n}\n\nstatic int irq_msix_user_setup(struct xdma_dev *xdev)\n{\n\tint i;\n\tint j = xdev->h2c_channel_max + xdev->c2h_channel_max;\n\tint rv = 0;\t\n\n\tprintk(\"irq_msix_user_setup min %d max %d\\n\", xdev->h2c_channel_max + xdev->c2h_channel_max, xdev->user_max);\n\t/* vectors set in probe_scan_for_msi() */\n\tif (0) {\n\tfor (i = 0; i < xdev->user_max; i++, j++) {\n#if LINUX_VERSION_CODE >= KERNEL_VERSION(4,12,0)\n\t\tu32 vector = pci_irq_vector(xdev->pdev, j);\n#else\n\t\tu32 vector = xdev->entry[j].vector;\n#endif\n\t\trv = request_irq(vector, xdma_user_irq, 0, xdev->mod_name,\n\t\t\t\t&xdev->user_irq[i]);\n\t\tif (rv) {\n\t\t\tpr_info(\"user %d couldn't use IRQ#%d, %d\\n\",\n\t\t\t\ti, vector, rv);\n\t\t\tbreak;\n\t\t}\n\t\tpr_info(\"%d-USR-%d, IRQ#%d with 0x%p\\n\", xdev->idx, i, vector,\n\t\t\t&xdev->user_irq[i]);\n        }\n\t}\n\n\t/* If any errors occur, free IRQs that were successfully requested */\n\tif (rv) {\n\t\tfor (i--, j--; i >= 0; i--, j--) {\n#if LINUX_VERSION_CODE >= KERNEL_VERSION(4,12,0)\n\t\t\tu32 vector = pci_irq_vector(xdev->pdev, j);\n#else\n\t\t\tu32 vector = xdev->entry[j].vector;\n#endif\n\t\t\tfree_irq(vector, &xdev->user_irq[i]);\n\t\t}\n\t}\n\n\treturn rv;\n}\n\nstatic int irq_msi_setup(struct xdma_dev *xdev, struct pci_dev *pdev)\n{\n\tint rv;\n\n\txdev->irq_line = (int)pdev->irq;\n\trv = request_irq(pdev->irq, xdma_isr, 0, xdev->mod_name, xdev);\n\tif (rv)\n\t\tdbg_init(\"Couldn't use IRQ#%d, %d\\n\", pdev->irq, rv);\n\telse\n\t\tdbg_init(\"Using IRQ#%d with 0x%p\\n\", pdev->irq, xdev);\n\n\treturn rv;\n}\n\nstatic int irq_legacy_setup(struct xdma_dev *xdev, struct pci_dev *pdev)\n{\n\tu32 w;\n\tu8 val;\n\tvoid *reg;\n\tint rv;\n\n\tpci_read_config_byte(pdev, PCI_INTERRUPT_PIN, &val);\n\tdbg_init(\"Legacy Interrupt register value = %d\\n\", val);\n\tif (val > 1) {\n\t\tval--;\n\t\tw = (val<<24) | (val<<16) | (val<<8)| val;\n\t\t/* Program IRQ Block Channel vactor and IRQ Block User vector\n\t\t * with Legacy interrupt value */\n\t\treg = xdev->bar[xdev->config_bar_idx] + 0x2080;   // IRQ user\n\t\twrite_register(w, reg, 0x2080);\n\t\twrite_register(w, reg+0x4, 0x2084);\n\t\twrite_register(w, reg+0x8, 0x2088);\n\t\twrite_register(w, reg+0xC, 0x208C);\n\t\treg = xdev->bar[xdev->config_bar_idx] + 0x20A0;   // IRQ Block\n\t\twrite_register(w, reg, 0x20A0);\n\t\twrite_register(w, reg+0x4, 0x20A4);\n\t}\n\n\txdev->irq_line = (int)pdev->irq;\n\trv = request_irq(pdev->irq, xdma_isr, IRQF_SHARED, xdev->mod_name,\n\t\t\txdev);\n\tif (rv)\n\t\tdbg_init(\"Couldn't use IRQ#%d, %d\\n\", pdev->irq, rv);\n\telse\n\t\tdbg_init(\"Using IRQ#%d with 0x%p\\n\", pdev->irq, xdev);\n\n\treturn rv;\n}\n\nstatic void irq_teardown(struct xdma_dev *xdev)\n{\n\tif (xdev->msix_enabled) {\n\t\tirq_msix_channel_teardown(xdev);\n\t\tirq_msix_user_teardown(xdev);\n\t} else if (xdev->irq_line != -1) {\n\t\tdbg_init(\"Releasing IRQ#%d\\n\", xdev->irq_line);\n\t\tfree_irq(xdev->irq_line, xdev);\n\t}\n}\n\nstatic int irq_setup(struct xdma_dev *xdev, struct pci_dev *pdev)\n{\n\tpci_keep_intx_enabled(pdev);\n\n\tif (xdev->msix_enabled) {\n\t\tint rv = irq_msix_channel_setup(xdev);\n\t\tif (rv)\n\t\t\treturn rv;\n\t\trv = irq_msix_user_setup(xdev);\n\t\tif (rv)\n\t\t\treturn rv;\n\t\tprog_irq_msix_channel(xdev, 0);\n\t\tprog_irq_msix_user(xdev, 0);\n\n\t\treturn 0;\n\t} else if (xdev->msi_enabled)\n\t\treturn irq_msi_setup(xdev, pdev);\n\n\treturn irq_legacy_setup(xdev, pdev);\n}\n\n#ifdef __LIBXDMA_DEBUG__\nstatic void dump_desc(struct xdma_desc *desc_virt)\n{\n\tint j;\n\tu32 *p = (u32 *)desc_virt;\n\tstatic char * const field_name[] = {\n\t\t\"magic|extra_adjacent|control\", \"bytes\", \"src_addr_lo\",\n\t\t\"src_addr_hi\", \"dst_addr_lo\", \"dst_addr_hi\", \"next_addr\",\n\t\t\"next_addr_pad\"};\n\tchar *dummy;\n\n\t/* remove warning about unused variable when debug printing is off */\n\tdummy = field_name[0];\n\n\tfor (j = 0; j < 8; j += 1) {\n\t\tpr_info(\"0x%08lx/0x%02lx: 0x%08x 0x%08x %s\\n\",\n\t\t\t (uintptr_t)p, (uintptr_t)p & 15, (int)*p,\n\t\t\t le32_to_cpu(*p), field_name[j]);\n\t\tp++;\n\t}\n\tpr_info(\"\\n\");\n}\n\nstatic void transfer_dump(struct xdma_transfer *transfer)\n{\n\tint i;\n\tstruct xdma_desc *desc_virt = transfer->desc_virt;\n\n\tpr_info(\"xfer 0x%p, state 0x%x, f 0x%x, dir %d, len %u, last %d.\\n\",\n\t\ttransfer, transfer->state, transfer->flags, transfer->dir,\n\t\ttransfer->len, transfer->last_in_request);\n\n\tpr_info(\"transfer 0x%p, desc %d, bus 0x%llx, adj %d.\\n\",\n\t\ttransfer, transfer->desc_num, (u64)transfer->desc_bus,\n\t\ttransfer->desc_adjacent);\n\tfor (i = 0; i < transfer->desc_num; i += 1)\n\t\tdump_desc(desc_virt + i);\n}\n#endif /* __LIBXDMA_DEBUG__ */\n\n/* xdma_desc_alloc() - Allocate cache-coherent array of N descriptors.\n *\n * Allocates an array of 'number' descriptors in contiguous PCI bus addressable\n * memory. Chains the descriptors as a singly-linked list; the descriptor's\n * next * pointer specifies the bus address of the next descriptor.\n *\n *\n * @dev Pointer to pci_dev\n * @number Number of descriptors to be allocated\n * @desc_bus_p Pointer where to store the first descriptor bus address\n *\n * @return Virtual address of the first descriptor\n *\n */\nstatic void transfer_desc_init(struct xdma_transfer *transfer, int count)\n{\n\tstruct xdma_desc *desc_virt = transfer->desc_virt;\n\tdma_addr_t desc_bus = transfer->desc_bus;\n\tint i;\n\tint adj = count - 1;\n\tint extra_adj;\n\tu32 temp_control;\n\n\tBUG_ON(count > XDMA_TRANSFER_MAX_DESC);\n\n\t/* create singly-linked list for SG DMA controller */\n\tfor (i = 0; i < count - 1; i++) {\n\t\t/* increment bus address to next in array */\n\t\tdesc_bus += sizeof(struct xdma_desc);\n\n\t\t/* singly-linked list uses bus addresses */\n\t\tdesc_virt[i].next_lo = cpu_to_le32(PCI_DMA_L(desc_bus));\n\t\tdesc_virt[i].next_hi = cpu_to_le32(PCI_DMA_H(desc_bus));\n\t\tdesc_virt[i].bytes = cpu_to_le32(0);\n\n\t\t/* any adjacent descriptors? */\n\t\tif (adj > 0) {\n\t\t\textra_adj = adj - 1;\n\t\t\tif (extra_adj > MAX_EXTRA_ADJ)\n\t\t\t\textra_adj = MAX_EXTRA_ADJ;\n\n\t\t\tadj--;\n\t\t} else {\n\t\t\textra_adj = 0;\n\t\t}\n\n\t\ttemp_control = DESC_MAGIC | (extra_adj << 8);\n\n\t\tdesc_virt[i].control = cpu_to_le32(temp_control);\n\t}\n\t/* { i = number - 1 } */\n\t/* zero the last descriptor next pointer */\n\tdesc_virt[i].next_lo = cpu_to_le32(0);\n\tdesc_virt[i].next_hi = cpu_to_le32(0);\n\tdesc_virt[i].bytes = cpu_to_le32(0);\n\n\ttemp_control = DESC_MAGIC;\n\n\tdesc_virt[i].control = cpu_to_le32(temp_control);\n}\n\n/* xdma_desc_link() - Link two descriptors\n *\n * Link the first descriptor to a second descriptor, or terminate the first.\n *\n * @first first descriptor\n * @second second descriptor, or NULL if first descriptor must be set as last.\n * @second_bus bus address of second descriptor\n */\nstatic void xdma_desc_link(struct xdma_desc *first, struct xdma_desc *second,\n\t\tdma_addr_t second_bus)\n{\n\t/*\n\t * remember reserved control in first descriptor, but zero\n\t * extra_adjacent!\n\t */\n\t /* RTO - what's this about?  Shouldn't it be 0x0000c0ffUL? */\n\tu32 control = le32_to_cpu(first->control) & 0x0000f0ffUL;\n\t/* second descriptor given? */\n\tif (second) {\n\t\t/*\n\t\t * link last descriptor of 1st array to first descriptor of\n\t\t * 2nd array\n\t\t */\n\t\tfirst->next_lo = cpu_to_le32(PCI_DMA_L(second_bus));\n\t\tfirst->next_hi = cpu_to_le32(PCI_DMA_H(second_bus));\n\t\tWARN_ON(first->next_hi);\n\t\t/* no second descriptor given */\n\t} else {\n\t\t/* first descriptor is the last */\n\t\tfirst->next_lo = 0;\n\t\tfirst->next_hi = 0;\n\t}\n\t/* merge magic, extra_adjacent and control field */\n\tcontrol |= DESC_MAGIC;\n\n\t/* write bytes and next_num */\n\tfirst->control = cpu_to_le32(control);\n}\n\n/* xdma_desc_adjacent -- Set how many descriptors are adjacent to this one */\nstatic void xdma_desc_adjacent(struct xdma_desc *desc, int next_adjacent)\n{\n\tint extra_adj = 0;\n\t/* remember reserved and control bits */\n\tu32 control = le32_to_cpu(desc->control) & 0x0000f0ffUL;\n\tu32 max_adj_4k = 0;\n\n\tif (next_adjacent > 0) {\n\t\textra_adj =  next_adjacent - 1;\n\t\tif (extra_adj > MAX_EXTRA_ADJ){\n\t\t\textra_adj = MAX_EXTRA_ADJ;\n\t\t}\n\t\tmax_adj_4k = (0x1000 - ((le32_to_cpu(desc->next_lo))&0xFFF))/32 - 1;\n\t\tif (extra_adj>max_adj_4k) {\n\t\t\textra_adj = max_adj_4k;\n\t\t}\n\t\tif(extra_adj<0){\n\t\t\tprintk(\"Warning: extra_adj<0, converting it to 0\\n\");\n\t\t\textra_adj = 0;\n\t\t}\n\t}\n\t/* merge adjacent and control field */\n\tcontrol |= 0xAD4B0000UL | (extra_adj << 8);\n\t/* write control and next_adjacent */\n\tdesc->control = cpu_to_le32(control);\n}\n\n/* xdma_desc_control -- Set complete control field of a descriptor. */\nstatic void xdma_desc_control_set(struct xdma_desc *first, u32 control_field)\n{\n\t/* remember magic and adjacent number */\n\tu32 control = le32_to_cpu(first->control) & ~(LS_BYTE_MASK);\n\n\tBUG_ON(control_field & ~(LS_BYTE_MASK));\n\t/* merge adjacent and control field */\n\tcontrol |= control_field;\n\t/* write control and next_adjacent */\n\tfirst->control = cpu_to_le32(control);\n}\n\n/* xdma_desc_clear -- Clear bits in control field of a descriptor. */\nstatic void xdma_desc_control_clear(struct xdma_desc *first, u32 clear_mask)\n{\n\t/* remember magic and adjacent number */\n\tu32 control = le32_to_cpu(first->control);\n\n\tBUG_ON(clear_mask & ~(LS_BYTE_MASK));\n\n\t/* merge adjacent and control field */\n\tcontrol &= (~clear_mask);\n\t/* write control and next_adjacent */\n\tfirst->control = cpu_to_le32(control);\n}\n\n/* xdma_desc_done - recycle cache-coherent linked list of descriptors.\n *\n * @dev Pointer to pci_dev\n * @number Number of descriptors to be allocated\n * @desc_virt Pointer to (i.e. virtual address of) first descriptor in list\n * @desc_bus Bus address of first descriptor in list\n */\nstatic inline void xdma_desc_done(struct xdma_desc *desc_virt)\n{\n\tmemset(desc_virt, 0, XDMA_TRANSFER_MAX_DESC * sizeof(struct xdma_desc));\n}\n\n/* xdma_desc() - Fill a descriptor with the transfer details\n *\n * @desc pointer to descriptor to be filled\n * @addr root complex address\n * @ep_addr end point address\n * @len number of bytes, must be a (non-negative) multiple of 4.\n * @dir, dma direction\n * is the end point address. If zero, vice versa.\n *\n * Does not modify the next pointer\n */\nstatic void xdma_desc_set(struct xdma_desc *desc, dma_addr_t rc_bus_addr,\n\t\tu64 ep_addr, int len, int dir)\n{\n\t/* transfer length */\n\tdesc->bytes = cpu_to_le32(len);\n\tif (dir == DMA_TO_DEVICE) {\n\t\t/* read from root complex memory (source address) */\n\t\tdesc->src_addr_lo = cpu_to_le32(PCI_DMA_L(rc_bus_addr));\n\t\tdesc->src_addr_hi = cpu_to_le32(PCI_DMA_H(rc_bus_addr));\n\t\t/* write to end point address (destination address) */\n\t\tdesc->dst_addr_lo = cpu_to_le32(PCI_DMA_L(ep_addr));\n\t\tdesc->dst_addr_hi = cpu_to_le32(PCI_DMA_H(ep_addr));\n\t} else {\n\t\t/* read from end point address (source address) */\n\t\tdesc->src_addr_lo = cpu_to_le32(PCI_DMA_L(ep_addr));\n\t\tdesc->src_addr_hi = cpu_to_le32(PCI_DMA_H(ep_addr));\n\t\t/* write to root complex memory (destination address) */\n\t\tdesc->dst_addr_lo = cpu_to_le32(PCI_DMA_L(rc_bus_addr));\n\t\tdesc->dst_addr_hi = cpu_to_le32(PCI_DMA_H(rc_bus_addr));\n\t}\n}\n\n/*\n * should hold the engine->lock;\n */\nstatic void transfer_abort(struct xdma_engine *engine,\n\t\t\tstruct xdma_transfer *transfer)\n{\n\tstruct xdma_transfer *head;\n\n\tBUG_ON(!engine);\n\tBUG_ON(!transfer);\n\tBUG_ON(transfer->desc_num == 0);\n\n\tpr_info(\"abort transfer 0x%p, desc %d, engine desc queued %d.\\n\",\n\t\ttransfer, transfer->desc_num, engine->desc_dequeued);\n\n\thead = list_entry(engine->transfer_list.next, struct xdma_transfer,\n\t\t\tentry);\n\tif (head == transfer)\n\t\tlist_del(engine->transfer_list.next);\n        else\n\t\tpr_info(\"engine %s, transfer 0x%p NOT found, 0x%p.\\n\",\n\t\t\tengine->name, transfer, head);\n\n\tif (transfer->state == TRANSFER_STATE_SUBMITTED)\n\t\ttransfer->state = TRANSFER_STATE_ABORTED;\n}\n\n/* transfer_queue() - Queue a DMA transfer on the engine\n *\n * @engine DMA engine doing the transfer\n * @transfer DMA transfer submitted to the engine\n *\n * Takes and releases the engine spinlock\n */\nstatic int transfer_queue(struct xdma_engine *engine,\n\t\tstruct xdma_transfer *transfer)\n{\n\tint rv = 0;\n\tstruct xdma_transfer *transfer_started;\n\tstruct xdma_dev *xdev;\n\tunsigned long flags;\n\n\tBUG_ON(!engine);\n\tBUG_ON(!engine->xdev);\n\tBUG_ON(!transfer);\n\tBUG_ON(transfer->desc_num == 0);\n\tdbg_tfr(\"transfer_queue(transfer=0x%p).\\n\", transfer);\n\n\txdev = engine->xdev;\n\tif (xdma_device_flag_check(xdev, XDEV_FLAG_OFFLINE)) {\n\t\tpr_info(\"dev 0x%p offline, transfer 0x%p not queued.\\n\",\n\t\t\txdev, transfer);\n\t\treturn -EBUSY;\n\t}\n\n\t/* lock the engine state */\n\tspin_lock_irqsave(&engine->lock, flags);\n\n\tengine->prev_cpu = get_cpu();\n\tput_cpu();\n\n\t/* engine is being shutdown; do not accept new transfers */\n\tif (engine->shutdown & ENGINE_SHUTDOWN_REQUEST) {\n\t\tpr_info(\"engine %s offline, transfer 0x%p not queued.\\n\",\n\t\t\tengine->name, transfer);\n\t\trv = -EBUSY;\n\t\tgoto shutdown;\n\t}\n\n\t/* mark the transfer as submitted */\n\ttransfer->state = TRANSFER_STATE_SUBMITTED;\n\t/* add transfer to the tail of the engine transfer queue */\n\tlist_add_tail(&transfer->entry, &engine->transfer_list);\n\n\t/* engine is idle? */\n\tif (!engine->running) {\n\t\t/* start engine */\n\t\tdbg_tfr(\"transfer_queue(): starting %s engine.\\n\",\n\t\t\tengine->name);\n\t\ttransfer_started = engine_start(engine);\n\t\tdbg_tfr(\"transfer=0x%p started %s engine with transfer 0x%p.\\n\",\n\t\t\ttransfer, engine->name, transfer_started);\n\t} else {\n\t\tdbg_tfr(\"transfer=0x%p queued, with %s engine running.\\n\",\n\t\t\ttransfer, engine->name);\n\t}\n\nshutdown:\n\t/* unlock the engine state */\n\tdbg_tfr(\"engine->running = %d\\n\", engine->running);\n\tspin_unlock_irqrestore(&engine->lock, flags);\n\treturn rv;\n}\n\nstatic void engine_alignments(struct xdma_engine *engine)\n{\n\tu32 w;\n\tu32 align_bytes;\n\tu32 granularity_bytes;\n\tu32 address_bits;\n\n\tw = read_register(&engine->regs->alignments);\n\tdbg_init(\"engine %p name %s alignments=0x%08x\\n\", engine,\n\t\tengine->name, (int)w);\n\n\t/* RTO  - add some macros to extract these fields */\n\talign_bytes = (w & 0x00ff0000U) >> 16;\n\tgranularity_bytes = (w & 0x0000ff00U) >> 8;\n\taddress_bits = (w & 0x000000ffU);\n\n\tdbg_init(\"align_bytes = %d\\n\", align_bytes);\n\tdbg_init(\"granularity_bytes = %d\\n\", granularity_bytes);\n\tdbg_init(\"address_bits = %d\\n\", address_bits);\n\n\tif (w) {\n\t\tengine->addr_align = align_bytes;\n\t\tengine->len_granularity = granularity_bytes;\n\t\tengine->addr_bits = address_bits;\n\t} else {\n\t\t/* Some default values if alignments are unspecified */\n\t\tengine->addr_align = 1;\n\t\tengine->len_granularity = 1;\n\t\tengine->addr_bits = 64;\n\t}\n}\n\nstatic void engine_free_resource(struct xdma_engine *engine)\n{\n\tstruct xdma_dev *xdev = engine->xdev;\n\n\t/* Release memory use for descriptor writebacks */\n\tif (engine->poll_mode_addr_virt) {\n\t\tdbg_sg(\"Releasing memory for descriptor writeback\\n\");\n\t\tdma_free_coherent(&xdev->pdev->dev,\n\t\t\t\tsizeof(struct xdma_poll_wb),\n\t\t\t\tengine->poll_mode_addr_virt,\n\t\t\t\tengine->poll_mode_bus);\n\t\tdbg_sg(\"Released memory for descriptor writeback\\n\");\n\t\tengine->poll_mode_addr_virt = NULL;\n\t}\n\n\tif (engine->desc) {\n\t\tdbg_init(\"device %s, engine %s pre-alloc desc 0x%p,0x%llx.\\n\",\n\t\t\tdev_name(&xdev->pdev->dev), engine->name,\n\t\t\tengine->desc, engine->desc_bus);\n\t\tdma_free_coherent(&xdev->pdev->dev,\n\t\t\tXDMA_TRANSFER_MAX_DESC * sizeof(struct xdma_desc),\n\t\t\tengine->desc, engine->desc_bus);\n\t\tengine->desc = NULL;\n\t}\n\n\tif (engine->cyclic_result) {\n\t\tdma_free_coherent(&xdev->pdev->dev,\n\t\t\tCYCLIC_RX_PAGES_MAX * sizeof(struct xdma_result),\n\t\t\tengine->cyclic_result, engine->cyclic_result_bus);\n\t\tengine->cyclic_result = NULL;\n\t}\n}\n\nstatic void engine_destroy(struct xdma_dev *xdev, struct xdma_engine *engine)\n{\n\tBUG_ON(!xdev);\n\tBUG_ON(!engine);\n\n\tdbg_sg(\"Shutting down engine %s%d\", engine->name, engine->channel);\n\n\t/* Disable interrupts to stop processing new events during shutdown */\n\twrite_register(0x0, &engine->regs->interrupt_enable_mask,\n\t\t\t(unsigned long)(&engine->regs->interrupt_enable_mask) -\n\t\t\t(unsigned long)(&engine->regs));\n\n\tif (enable_credit_mp && engine->streaming &&\n\t\tengine->dir == DMA_FROM_DEVICE) {\n\t\tu32 reg_value = (0x1 << engine->channel) << 16;\n\t\tstruct sgdma_common_regs *reg = (struct sgdma_common_regs *)\n\t\t\t\t(xdev->bar[xdev->config_bar_idx] +\n\t\t\t\t (0x6*TARGET_SPACING));\t\n\t\twrite_register(reg_value, &reg->credit_mode_enable_w1c, 0);\n\t}\n\n\t/* Release memory use for descriptor writebacks */\n\tengine_free_resource(engine);\n\n\tmemset(engine, 0, sizeof(struct xdma_engine));\n\t/* Decrement the number of engines available */\n\txdev->engines_num--;\n}\n\n/**\n *engine_cyclic_stop() - stop a cyclic transfer running on an SG DMA engine\n *\n *engine->lock must be taken\n */\nstruct xdma_transfer *engine_cyclic_stop(struct xdma_engine *engine)\n{\n\tstruct xdma_transfer *transfer = 0;\n\n\t/* transfers on queue? */\n\tif (!list_empty(&engine->transfer_list)) {\n\t\t/* pick first transfer on the queue (was submitted to engine) */\n\t\ttransfer = list_entry(engine->transfer_list.next,\n\t\t\t\t\tstruct xdma_transfer, entry);\n\t\tBUG_ON(!transfer);\n\n\t\txdma_engine_stop(engine);\n\n\t\tif (transfer->cyclic) {\n\t\t\tif (engine->xdma_perf)\n\t\t\t\tdbg_perf(\"Stopping perf transfer on %s\\n\",\n\t\t\t\t\tengine->name);\n\t\t\telse\n\t\t\t\tdbg_perf(\"Stopping cyclic transfer on %s\\n\",\n\t\t\t\t\tengine->name);\n\t\t\t/* make sure the handler sees correct transfer state */\n\t\t\ttransfer->cyclic = 1;\n\t\t\t/*\n\t\t\t* set STOP flag and interrupt on completion, on the\n\t\t\t* last descriptor\n\t\t\t*/\n\t\t\txdma_desc_control_set(\n\t\t\t\ttransfer->desc_virt + transfer->desc_num - 1,\n\t\t\t\tXDMA_DESC_COMPLETED | XDMA_DESC_STOPPED);\n\t\t} else {\n\t\t\tdbg_sg(\"(engine=%p) running transfer is not cyclic\\n\",\n\t\t\t\tengine);\n\t\t}\n\t} else {\n\t\tdbg_sg(\"(engine=%p) found not running transfer.\\n\", engine);\n\t}\n\treturn transfer;\n}\nEXPORT_SYMBOL_GPL(engine_cyclic_stop);\n\nstatic int engine_writeback_setup(struct xdma_engine *engine)\n{\n\tu32 w;\n\tstruct xdma_dev *xdev;\n\tstruct xdma_poll_wb *writeback;\n\n\tBUG_ON(!engine);\n\txdev = engine->xdev;\n\tBUG_ON(!xdev);\n\n\t/*\n\t * RTO - doing the allocation per engine is wasteful since a full page\n\t * is allocated each time - better to allocate one page for the whole\n\t * device during probe() and set per-engine offsets here\n\t */\n\twriteback = (struct xdma_poll_wb *)engine->poll_mode_addr_virt;\n\twriteback->completed_desc_count = 0;\n\n\tdbg_init(\"Setting writeback location to 0x%llx for engine %p\",\n\t\tengine->poll_mode_bus, engine);\n\tw = cpu_to_le32(PCI_DMA_L(engine->poll_mode_bus));\n\twrite_register(w, &engine->regs->poll_mode_wb_lo, \n\t\t\t(unsigned long)(&engine->regs->poll_mode_wb_lo) - \n\t\t\t(unsigned long)(&engine->regs));\n\tw = cpu_to_le32(PCI_DMA_H(engine->poll_mode_bus));\n\twrite_register(w, &engine->regs->poll_mode_wb_hi, \n\t\t\t(unsigned long)(&engine->regs->poll_mode_wb_hi) - \n\t\t\t(unsigned long)(&engine->regs));\n\n\treturn 0;\n}\n\n\n/* engine_create() - Create an SG DMA engine bookkeeping data structure\n *\n * An SG DMA engine consists of the resources for a single-direction transfer\n * queue; the SG DMA hardware, the software queue and interrupt handling.\n *\n * @dev Pointer to pci_dev\n * @offset byte address offset in BAR[xdev->config_bar_idx] resource for the\n * SG DMA * controller registers.\n * @dir: DMA_TO/FROM_DEVICE\n * @streaming Whether the engine is attached to AXI ST (rather than MM)\n */\nstatic int engine_init_regs(struct xdma_engine *engine)\n{\n\tu32 reg_value;\n\tint rv = 0;\n\n\twrite_register(XDMA_CTRL_NON_INCR_ADDR, &engine->regs->control_w1c,\n\t\t\t(unsigned long)(&engine->regs->control_w1c) -\n\t\t\t(unsigned long)(&engine->regs));\n\n\tengine_alignments(engine);\n\n\t/* Configure error interrupts by default */\n\treg_value = XDMA_CTRL_IE_DESC_ALIGN_MISMATCH;\n\treg_value |= XDMA_CTRL_IE_MAGIC_STOPPED;\n\treg_value |= XDMA_CTRL_IE_MAGIC_STOPPED;\n\treg_value |= XDMA_CTRL_IE_READ_ERROR;\n\treg_value |= XDMA_CTRL_IE_DESC_ERROR;\n\n\t/* if using polled mode, configure writeback address */\n\tif (poll_mode) {\n\t\trv = engine_writeback_setup(engine);\n\t\tif (rv) {\n\t\t\tdbg_init(\"%s descr writeback setup failed.\\n\",\n\t\t\t\tengine->name);\n\t\t\tgoto fail_wb;\n\t\t}\n\t} else {\n\t\t/* enable the relevant completion interrupts */\n\t\treg_value |= XDMA_CTRL_IE_DESC_STOPPED;\n\t\treg_value |= XDMA_CTRL_IE_DESC_COMPLETED;\n\n\t\tif (engine->streaming && engine->dir == DMA_FROM_DEVICE)\n\t\t\treg_value |= XDMA_CTRL_IE_IDLE_STOPPED;\n\t}\n\n\t/* Apply engine configurations */\n\twrite_register(reg_value, &engine->regs->interrupt_enable_mask,\n\t\t\t(unsigned long)(&engine->regs->interrupt_enable_mask) -\n\t\t\t(unsigned long)(&engine->regs));\n\n\tengine->interrupt_enable_mask_value = reg_value;\n\n\t/* only enable credit mode for AXI-ST C2H */\n\tif (enable_credit_mp && engine->streaming &&\n\t\tengine->dir == DMA_FROM_DEVICE) {\n\n\t\tstruct xdma_dev *xdev = engine->xdev;\n\t\tu32 reg_value = (0x1 << engine->channel) << 16;\n\t\tstruct sgdma_common_regs *reg = (struct sgdma_common_regs *)\n\t\t\t\t(xdev->bar[xdev->config_bar_idx] +\n\t\t\t\t (0x6*TARGET_SPACING));\t\n\n\t\twrite_register(reg_value, &reg->credit_mode_enable_w1s, 0);\n\t}\n\n\treturn 0;\n\nfail_wb:\n\treturn rv;\n}\n\nstatic int engine_alloc_resource(struct xdma_engine *engine)\n{\n\tstruct xdma_dev *xdev = engine->xdev;\n\n\tengine->desc = dma_alloc_coherent(&xdev->pdev->dev,\n\t\t\tXDMA_TRANSFER_MAX_DESC * sizeof(struct xdma_desc),\n\t\t\t&engine->desc_bus, GFP_KERNEL);\n\tif (!engine->desc) {\n\t\tpr_warn(\"dev %s, %s pre-alloc desc OOM.\\n\",\n\t\t\tdev_name(&xdev->pdev->dev), engine->name);\n\t\tgoto err_out;\n\t}\n\n\tif (poll_mode) {\n\t\tengine->poll_mode_addr_virt = dma_alloc_coherent(\n\t\t\t\t\t&xdev->pdev->dev,\n\t\t\t\t\tsizeof(struct xdma_poll_wb),\n\t\t\t\t\t&engine->poll_mode_bus, GFP_KERNEL);\n\t\tif (!engine->poll_mode_addr_virt) {\n                        pr_warn(\"%s, %s poll pre-alloc writeback OOM.\\n\",\n\t\t\t\tdev_name(&xdev->pdev->dev), engine->name);\n\t\t\tgoto err_out;\n\t\t}\n\t}\n\n\tif (engine->streaming && engine->dir == DMA_FROM_DEVICE) {\n\t\tengine->cyclic_result = dma_alloc_coherent(&xdev->pdev->dev,\n\t\t\tCYCLIC_RX_PAGES_MAX * sizeof(struct xdma_result),\n\t\t\t&engine->cyclic_result_bus, GFP_KERNEL);\n\n\t\tif (!engine->cyclic_result) {\n                        pr_warn(\"%s, %s pre-alloc result OOM.\\n\",\n\t\t\t\tdev_name(&xdev->pdev->dev), engine->name);\n\t\t\tgoto err_out;\n\t\t}\n\t}\n\n\treturn 0;\n\nerr_out:\n\tengine_free_resource(engine);\n\treturn -ENOMEM;\n}\n\nstatic int engine_init(struct xdma_engine *engine, struct xdma_dev *xdev,\n\t\t\tint offset, enum dma_data_direction dir, int channel)\n{\n\tint rv;\n\tu32 val;\n\n\tdbg_init(\"channel %d, offset 0x%x, dir %d.\\n\", channel, offset, dir);\n\n\t/* set magic */\n\tengine->magic = MAGIC_ENGINE;\n\n\tengine->channel = channel;\n\n\t/* engine interrupt request bit */\n\tengine->irq_bitmask = (1 << XDMA_ENG_IRQ_NUM) - 1;\n\tengine->irq_bitmask <<= (xdev->engines_num * XDMA_ENG_IRQ_NUM);\n\tengine->bypass_offset = xdev->engines_num * BYPASS_MODE_SPACING;\n\n\t/* parent */\n\tengine->xdev = xdev;\n\t/* register address */\n\tengine->regs = (xdev->bar[xdev->config_bar_idx] + offset);\n\tengine->sgdma_regs = xdev->bar[xdev->config_bar_idx] + offset +\n\t\t\t\tSGDMA_OFFSET_FROM_CHANNEL;\n\tval = read_register(&engine->regs->identifier);\n        if (val & 0x8000U)\n\t\tengine->streaming = 1;\n\n\t/* remember SG DMA direction */\n\tengine->dir = dir;\n\tsprintf(engine->name, \"%d-%s%d-%s\", xdev->idx,\n\t\t(dir == DMA_TO_DEVICE) ? \"H2C\" : \"C2H\", channel,\n\t\tengine->streaming ? \"ST\" : \"MM\");\n\n\tdbg_init(\"engine %p name %s irq_bitmask=0x%08x\\n\", engine, engine->name,\n\t\t(int)engine->irq_bitmask);\n\n\t/* initialize the deferred work for transfer completion */\n\tINIT_WORK(&engine->work, engine_service_work);\n\n\tif (dir == DMA_TO_DEVICE)\n\t\txdev->mask_irq_h2c |= engine->irq_bitmask;\n\telse\n\t\txdev->mask_irq_c2h |= engine->irq_bitmask;\n\txdev->engines_num++;\n\n\trv = engine_alloc_resource(engine);\n\tif (rv)\n\t\treturn rv;\n\n\trv = engine_init_regs(engine);\n\tif (rv)\n\t\treturn rv;\n\n\treturn 0;\n}\n\n/* transfer_destroy() - free transfer */\nstatic void transfer_destroy(struct xdma_dev *xdev, struct xdma_transfer *xfer)\n{\n\t/* free descriptors */\n\txdma_desc_done(xfer->desc_virt);\n\n\tif (xfer->last_in_request && (xfer->flags & XFER_FLAG_NEED_UNMAP)) {\n        \tstruct sg_table *sgt = xfer->sgt;\n\n\t\tif (sgt->nents) {\n\t\t\tpci_unmap_sg(xdev->pdev, sgt->sgl, sgt->nents,\n\t\t\t\txfer->dir);\n\t\t\tsgt->nents = 0;\n\t\t}\n\t}\n}\n\nstatic int transfer_build(struct xdma_engine *engine,\n\t\t\tstruct xdma_request_cb *req, unsigned int desc_max)\n{\n\tstruct xdma_transfer *xfer = &req->xfer;\n\tstruct sw_desc *sdesc = &(req->sdesc[req->sw_desc_idx]);\n\tint i = 0;\n\tint j = 0;\n\n\tfor (; i < desc_max; i++, j++, sdesc++) {\n\t\tdbg_desc(\"sw desc %d/%u: 0x%llx, 0x%x, ep 0x%llx.\\n\",\n\t\t\ti + req->sw_desc_idx, req->sw_desc_cnt,\n\t\t\tsdesc->addr, sdesc->len, req->ep_addr);\n\n\t\t/* fill in descriptor entry j with transfer details */\n\t\txdma_desc_set(xfer->desc_virt + j, sdesc->addr, req->ep_addr,\n\t\t\t\t sdesc->len, xfer->dir);\n\t\txfer->len += sdesc->len;\n\n\t\t/* for non-inc-add mode don't increment ep_addr */\n\t\tif (!engine->non_incr_addr)\n\t\t\treq->ep_addr += sdesc->len;\n\t}\n\treq->sw_desc_idx += desc_max; \n\treturn 0;\n}\n\nstatic int transfer_init(struct xdma_engine *engine, struct xdma_request_cb *req)\n{\n\tstruct xdma_transfer *xfer = &req->xfer;\n\tunsigned int desc_max = min_t(unsigned int,\n\t\t\t\treq->sw_desc_cnt - req->sw_desc_idx,\n\t\t\t\tXDMA_TRANSFER_MAX_DESC);\n\tint i = 0;\n\tint last = 0;\n\tu32 control;\n\n\tmemset(xfer, 0, sizeof(*xfer));\n\n\t/* initialize wait queue */\n\tinit_waitqueue_head(&xfer->wq);\n\n\t/* remember direction of transfer */\n\txfer->dir = engine->dir;\n\n\txfer->desc_virt = engine->desc;\n\txfer->desc_bus = engine->desc_bus;\n\n\ttransfer_desc_init(xfer, desc_max);\n\t\n\tdbg_sg(\"transfer->desc_bus = 0x%llx.\\n\", (u64)xfer->desc_bus);\n\n\ttransfer_build(engine, req, desc_max);\n\n\t/* terminate last descriptor */\n\tlast = desc_max - 1;\n\txdma_desc_link(xfer->desc_virt + last, 0, 0);\n\t/* stop engine, EOP for AXI ST, req IRQ on last descriptor */\n\tcontrol = XDMA_DESC_STOPPED;\n\tcontrol |= XDMA_DESC_EOP;\n\tcontrol |= XDMA_DESC_COMPLETED;\n\txdma_desc_control_set(xfer->desc_virt + last, control);\n\n\txfer->desc_num = xfer->desc_adjacent = desc_max;\n\n\tdbg_sg(\"transfer 0x%p has %d descriptors\\n\", xfer, xfer->desc_num);\n\t/* fill in adjacent numbers */\n\tfor (i = 0; i < xfer->desc_num; i++)\n\t\txdma_desc_adjacent(xfer->desc_virt + i, xfer->desc_num - i - 1);\n\n\treturn 0;\n}\n\n#ifdef __LIBXDMA_DEBUG__\nstatic void sgt_dump(struct sg_table *sgt)\n{\n\tint i;\n\tstruct scatterlist *sg = sgt->sgl;\n\n\tpr_info(\"sgt 0x%p, sgl 0x%p, nents %u/%u.\\n\",\n\t\tsgt, sgt->sgl, sgt->nents, sgt->orig_nents);\n\n\tfor (i = 0; i < sgt->orig_nents; i++, sg = sg_next(sg))\n\t\tpr_info(\"%d, 0x%p, pg 0x%p,%u+%u, dma 0x%llx,%u.\\n\",\n\t\t\ti, sg, sg_page(sg), sg->offset, sg->length,\n\t\t\tsg_dma_address(sg), sg_dma_len(sg)); \n}\n\nstatic void xdma_request_cb_dump(struct xdma_request_cb *req)\n{\n\tint i;\n\n\tpr_info(\"request 0x%p, total %u, ep 0x%llx, sw_desc %u, sgt 0x%p.\\n\",\n\t\treq, req->total_len, req->ep_addr, req->sw_desc_cnt, req->sgt);\n\tsgt_dump(req->sgt);\n\tfor (i = 0; i < req->sw_desc_cnt; i++)\n\t\tpr_info(\"%d/%u, 0x%llx, %u.\\n\",\n\t\t\ti, req->sw_desc_cnt, req->sdesc[i].addr,\n\t\t\treq->sdesc[i].len);\n}\n#endif\n\nstatic void xdma_request_free(struct xdma_request_cb *req)\n{\n\tif (((unsigned long)req) >= VMALLOC_START &&\n\t    ((unsigned long)req) < VMALLOC_END)\n\t\tvfree(req);\n\telse\n\t\tkfree(req);\n}\n\nstatic struct xdma_request_cb * xdma_request_alloc(unsigned int sdesc_nr)\n{\n\tstruct xdma_request_cb *req;\n\tunsigned int size = sizeof(struct xdma_request_cb) +\n\t\t\t\tsdesc_nr * sizeof(struct sw_desc);\n\n\treq = kzalloc(size, GFP_KERNEL);\n\tif (!req) {\n\t\treq = vmalloc(size);\n\t\tif (req)\n\t\t\tmemset(req, 0, size);\n\t}\n\tif (!req) {\n\t\tpr_info(\"OOM, %u sw_desc, %u.\\n\", sdesc_nr, size);\n\t\treturn NULL;\n\t}\n\n\treturn req;\n}\n\nstatic struct xdma_request_cb * xdma_init_request(struct sg_table *sgt,\n\t\t\t\t\t\tu64 ep_addr)\n{\n\tstruct xdma_request_cb *req;\n\tstruct scatterlist *sg = sgt->sgl;\n\tint max = sgt->nents;\n\tint extra = 0;\n\tint i, j = 0;\n\n\tfor (i = 0;  i < max; i++, sg = sg_next(sg)) {\n\t\tunsigned int len = sg_dma_len(sg);\n\n\t\tif (unlikely(len > desc_blen_max))\n\t\t\textra += (len + desc_blen_max - 1) / desc_blen_max;\n\t}\n\n//pr_info(\"ep 0x%llx, desc %u+%u.\\n\", ep_addr, max, extra);\n\n\tmax += extra;\n\treq = xdma_request_alloc(max);\n\tif (!req)\n\t\treturn NULL;\n\n\treq->sgt = sgt;\t\n\treq->ep_addr = ep_addr;\n\n\tfor (i = 0, sg = sgt->sgl;  i < sgt->nents; i++, sg = sg_next(sg)) {\n\t\tunsigned int tlen = sg_dma_len(sg);\n\t\tdma_addr_t addr = sg_dma_address(sg);\t\n\n\t\treq->total_len += tlen;\n\t\twhile (tlen) {\n\t\t\treq->sdesc[j].addr = addr;\n\t\t\tif (tlen > desc_blen_max) {\n\t\t\t\treq->sdesc[j].len = desc_blen_max;\n\t\t\t\taddr += desc_blen_max;\n\t\t\t\ttlen -= desc_blen_max;\t\n\t\t\t} else {\n\t\t\t\treq->sdesc[j].len = tlen;\n\t\t\t\ttlen = 0;\n\t\t\t}\n\t\t\tj++;\n\t\t}\n\t}\n\tBUG_ON(j > max);\n\n\treq->sw_desc_cnt = j;\n#ifdef __LIBXDMA_DEBUG__\n\txdma_request_cb_dump(req);\n#endif\n\treturn req;\n}\n\nssize_t xdma_xfer_submit(void *dev_hndl, int channel, bool write, u64 ep_addr,\n\t\t\tstruct sg_table *sgt, bool dma_mapped, int timeout_ms)\n{\n\tstruct xdma_dev *xdev = (struct xdma_dev *)dev_hndl;\n\tstruct xdma_engine *engine;\n\tint rv = 0;\n\tssize_t done = 0;\n\tstruct scatterlist *sg = sgt->sgl;\n\tint nents;\n\tenum dma_data_direction dir = write ? DMA_TO_DEVICE : DMA_FROM_DEVICE;\n\tstruct xdma_request_cb *req = NULL;\n\n\tif (!dev_hndl)\n\t\treturn -EINVAL;\n\n\tif (debug_check_dev_hndl(__func__, xdev->pdev, dev_hndl) < 0)\n\t\treturn -EINVAL;\n\n\tif (write == 1) {\n\t\tif (channel >= xdev->h2c_channel_max) {\n\t\t\tpr_warn(\"H2C channel %d >= %d.\\n\",\n\t\t\t\tchannel, xdev->h2c_channel_max);\n\t\t\treturn -EINVAL;\n\t\t}\n\t\tengine = &xdev->engine_h2c[channel];\n\t} else if (write == 0) {\n\t\tif (channel >= xdev->c2h_channel_max) {\n\t\t\tpr_warn(\"C2H channel %d >= %d.\\n\",\n\t\t\t\tchannel, xdev->c2h_channel_max);\n\t\t\treturn -EINVAL;\n\t\t}\n\t\tengine = &xdev->engine_c2h[channel];\n\t} else {\n\t\tpr_warn(\"write %d, exp. 0|1.\\n\", write);\n\t\treturn -EINVAL;\n\t}\n\n        BUG_ON(!engine);\n        BUG_ON(engine->magic != MAGIC_ENGINE);\n\n\txdev = engine->xdev;\n\tif (xdma_device_flag_check(xdev, XDEV_FLAG_OFFLINE)) {\n\t\tpr_info(\"xdev 0x%p, offline.\\n\", xdev);\n\t\treturn -EBUSY;\n\t}\n\n\t/* check the direction */\n\tif (engine->dir != dir) {\n\t\tpr_info(\"0x%p, %s, %d, W %d, 0x%x/0x%x mismatch.\\n\",\n\t\t\tengine, engine->name, channel, write, engine->dir, dir);\n\t\treturn -EINVAL;\n\t}\n\n\tif (!dma_mapped) {\n\t\tnents = pci_map_sg(xdev->pdev, sg, sgt->orig_nents, dir);\n\t\tif (!nents) {\n\t\t\tpr_info(\"map sgl failed, sgt 0x%p.\\n\", sgt);\n\t\t\treturn -EIO;\n\t\t}\n\t\tsgt->nents = nents;\n\t} else {\n\t\tBUG_ON(!sgt->nents);\n\t}\n\n\treq = xdma_init_request(sgt, ep_addr);\n\tif (!req) {\n\t\trv = -ENOMEM;\n\t\tgoto unmap_sgl;\n\t}\n\n\tdbg_tfr(\"%s, len %u sg cnt %u.\\n\",\n\t\tengine->name, req->total_len, req->sw_desc_cnt);\n\n\tsg = sgt->sgl;\n\tnents = req->sw_desc_cnt;\n\twhile (nents) {\n\t\tunsigned long flags;\n\t\tstruct xdma_transfer *xfer;\n\n\t\t/* one transfer at a time */\n\t\tspin_lock(&engine->desc_lock);\n\n\t\t/* build transfer */\t\n\t\trv = transfer_init(engine, req);\n\t\tif (rv < 0) {\n\t\t\tspin_unlock(&engine->desc_lock);\n\t\t\tgoto unmap_sgl;\n\t\t}\n\t\txfer = &req->xfer;\n\n\t\tif (!dma_mapped)\n\t\t\txfer->flags = XFER_FLAG_NEED_UNMAP;\n\n\t\t/* last transfer for the given request? */\n\t\tnents -= xfer->desc_num;\n\t\tif (!nents) {\n\t\t\txfer->last_in_request = 1;\n\t\t\txfer->sgt = sgt;\n\t\t}\n\n\t\tdbg_tfr(\"xfer, %u, ep 0x%llx, done %lu, sg %u/%u.\\n\",\n\t\t\txfer->len, req->ep_addr, done, req->sw_desc_idx,\n\t\t\treq->sw_desc_cnt);\n\n#ifdef __LIBXDMA_DEBUG__\n\t\ttransfer_dump(xfer);\n#endif\n\n\t\trv = transfer_queue(engine, xfer);\n\t\tif (rv < 0) {\n\t\t\tspin_unlock(&engine->desc_lock);\n\t\t\tpr_info(\"unable to submit %s, %d.\\n\", engine->name, rv);\n\t\t\tgoto unmap_sgl;\n\t\t}\n\n\t\t/*\n\t\t * When polling, determine how many descriptors have been queued\t\t * on the engine to determine the writeback value expected\n\t\t */\n\t\tif (poll_mode) {\n\t\t\tunsigned int desc_count;\n\n\t\t\tspin_lock_irqsave(&engine->lock, flags);\n                        desc_count = xfer->desc_num;\n\t\t\tspin_unlock_irqrestore(&engine->lock, flags);\n\n                        dbg_tfr(\"%s poll desc_count=%d\\n\",\n\t\t\t\tengine->name, desc_count);\n\t\t\trv = engine_service_poll(engine, desc_count);\n\n\t\t} else {\n\t\t\trv = wait_event_interruptible_timeout(xfer->wq,\n                \t        (xfer->state != TRANSFER_STATE_SUBMITTED),\n\t\t\t\tmsecs_to_jiffies(timeout_ms));\n\t\t}\n\n\t\tspin_lock_irqsave(&engine->lock, flags);\n\n\t\tswitch(xfer->state) {\n\t\tcase TRANSFER_STATE_COMPLETED:\n\t\t\tspin_unlock_irqrestore(&engine->lock, flags);\n\n\t\t\tdbg_tfr(\"transfer %p, %u, ep 0x%llx compl, +%lu.\\n\",\n\t\t\t\txfer, xfer->len, req->ep_addr - xfer->len, done);\n\t\t\tdone += xfer->len;\n\t\t\trv = 0;\n\t\t\tbreak;\n\t\tcase TRANSFER_STATE_FAILED:\n\t\t\tpr_info(\"xfer 0x%p,%u, failed, ep 0x%llx.\\n\",\n\t\t\t\t xfer, xfer->len, req->ep_addr - xfer->len);\n\t\t\tspin_unlock_irqrestore(&engine->lock, flags);\n\n#ifdef __LIBXDMA_DEBUG__\n\t\t\ttransfer_dump(xfer);\n\t\t\tsgt_dump(sgt);\n#endif\n\t\t\trv = -EIO;\n\t\t\tbreak;\n\t\tdefault:\n\t\t\t/* transfer can still be in-flight */\n\t\t\tpr_info(\"xfer 0x%p,%u, s 0x%x timed out, ep 0x%llx.\\n\",\n\t\t\t\t xfer, xfer->len, xfer->state, req->ep_addr);\n\t\t\tengine_status_read(engine, 0, 1);\n\t\t\t//engine_status_dump(engine);\n\t\t\ttransfer_abort(engine, xfer);\n\n\t\t\txdma_engine_stop(engine);\n\t\t\tspin_unlock_irqrestore(&engine->lock, flags);\n\n#ifdef __LIBXDMA_DEBUG__\n\t\t\ttransfer_dump(xfer);\n\t\t\tsgt_dump(sgt);\n#endif\n\t\t\trv = -ERESTARTSYS;\n\t\t\tbreak;\n\t\t}\n\n\t\ttransfer_destroy(xdev, xfer);\n\t\tspin_unlock(&engine->desc_lock);\n\n\t\tif (rv < 0)\n\t\t\tgoto unmap_sgl;\n\t} /* while (sg) */\n\nunmap_sgl:\n\tif (!dma_mapped && sgt->nents) {\n\t\tpci_unmap_sg(xdev->pdev, sgt->sgl, sgt->orig_nents, dir);\n\t\tsgt->nents = 0;\n\t}\n\n\tif (req)\n\t\txdma_request_free(req);\n\n\tif (rv < 0)\n\t\treturn rv;\n\n\treturn done;\n}\nEXPORT_SYMBOL_GPL(xdma_xfer_submit);\n\nint xdma_performance_submit(struct xdma_dev *xdev, struct xdma_engine *engine)\n{\n\tu8 *buffer_virt;\n\tu32 max_consistent_size = 128 * 32 * 1024; /* 1024 pages, 4MB */\n\tdma_addr_t buffer_bus;\t/* bus address */\n\tstruct xdma_transfer *transfer;\n\tu64 ep_addr = 0;\n\tint num_desc_in_a_loop = 128;\n\tint size_in_desc = engine->xdma_perf->transfer_size;\n\tint size = size_in_desc * num_desc_in_a_loop;\n\tint i;\n\n\tBUG_ON(size_in_desc > max_consistent_size);\n\n\tif (size > max_consistent_size) {\n\t\tsize = max_consistent_size;\n\t\tnum_desc_in_a_loop = size / size_in_desc;\n\t}\n\n\tbuffer_virt = dma_alloc_coherent(&xdev->pdev->dev, size,\n\t\t\t\t\t&buffer_bus, GFP_KERNEL);\n\n\t/* allocate transfer data structure */\n\ttransfer = kzalloc(sizeof(struct xdma_transfer), GFP_KERNEL);\n\tBUG_ON(!transfer);\n\n\t/* 0 = write engine (to_dev=0) , 1 = read engine (to_dev=1) */\n\ttransfer->dir = engine->dir;\n\t/* set number of descriptors */\n\ttransfer->desc_num = num_desc_in_a_loop;\n\n\t/* allocate descriptor list */\n\tif (!engine->desc) {\n\t\tengine->desc = dma_alloc_coherent(&xdev->pdev->dev,\n\t\t\tnum_desc_in_a_loop * sizeof(struct xdma_desc),\n\t\t\t&engine->desc_bus, GFP_KERNEL);\n\t\tBUG_ON(!engine->desc);\n\t\tdbg_init(\"device %s, engine %s pre-alloc desc 0x%p,0x%llx.\\n\",\n\t\t\tdev_name(&xdev->pdev->dev), engine->name,\n\t\t\tengine->desc, engine->desc_bus);\n\t}\n\ttransfer->desc_virt = engine->desc;\n\ttransfer->desc_bus = engine->desc_bus;\n\n\ttransfer_desc_init(transfer, transfer->desc_num);\n\n\tdbg_sg(\"transfer->desc_bus = 0x%llx.\\n\", (u64)transfer->desc_bus);\n\n\tfor (i = 0; i < transfer->desc_num; i++) {\n\t\tstruct xdma_desc *desc = transfer->desc_virt + i;\n\t\tdma_addr_t rc_bus_addr = buffer_bus + size_in_desc * i;\n\n\t\t/* fill in descriptor entry with transfer details */\n\t\txdma_desc_set(desc, rc_bus_addr, ep_addr, size_in_desc,\n\t\t\tengine->dir);\n\t}\n\n\t/* stop engine and request interrupt on last descriptor */\n\txdma_desc_control_set(transfer->desc_virt, 0);\n\t/* create a linked loop */\n\txdma_desc_link(transfer->desc_virt + transfer->desc_num - 1,\n\t\ttransfer->desc_virt, transfer->desc_bus);\n\n\ttransfer->cyclic = 1;\n\n\t/* initialize wait queue */\n\tinit_waitqueue_head(&transfer->wq);\n\n\t//printk(\"=== Descriptor print for PERF \\n\");\n\t//transfer_dump(transfer);\n\n\tdbg_perf(\"Queueing XDMA I/O %s request for performance measurement.\\n\",\n\t\tengine->dir ? \"write (to dev)\" : \"read (from dev)\");\n\ttransfer_queue(engine, transfer);\n\treturn 0;\n\n}\nEXPORT_SYMBOL_GPL(xdma_performance_submit);\n\nstatic struct xdma_dev *alloc_dev_instance(struct pci_dev *pdev)\n{\n\tint i;\n\tstruct xdma_dev *xdev;\n\tstruct xdma_engine *engine;\n\n\tBUG_ON(!pdev);\n\n\t/* allocate zeroed device book keeping structure */\n\txdev = kzalloc(sizeof(struct xdma_dev), GFP_KERNEL);\n\tif (!xdev) {\n\t\tpr_info(\"OOM, xdma_dev.\\n\");\n\t\treturn NULL;\n\t}\n\tspin_lock_init(&xdev->lock);\n\n\txdev->magic = MAGIC_DEVICE;\n\txdev->config_bar_idx = -1;\n\txdev->user_bar_idx = -1;\n\txdev->bypass_bar_idx = -1;\n\txdev->irq_line = -1;\n\n\t/* create a driver to device reference */\n\txdev->pdev = pdev;\n\tdbg_init(\"xdev = 0x%p\\n\", xdev);\n\n\t/* Set up data user IRQ data structures */\n\tfor (i = 0; i < 16; i++) {\n\t\txdev->user_irq[i].xdev = xdev;\n\t\tspin_lock_init(&xdev->user_irq[i].events_lock);\n\t\tinit_waitqueue_head(&xdev->user_irq[i].events_wq);\n\t\txdev->user_irq[i].handler = NULL;\n\t\txdev->user_irq[i].user_idx = i; /* 0 based */\n\t}\n\n\tengine = xdev->engine_h2c;\n\tfor (i = 0; i < XDMA_CHANNEL_NUM_MAX; i++, engine++) {\n\t\tspin_lock_init(&engine->lock);\n\t\tspin_lock_init(&engine->desc_lock);\n\t\tINIT_LIST_HEAD(&engine->transfer_list);\n\t\tinit_waitqueue_head(&engine->shutdown_wq);\n\t\tinit_waitqueue_head(&engine->xdma_perf_wq);\n\t}\n\n\tengine = xdev->engine_c2h;\n\tfor (i = 0; i < XDMA_CHANNEL_NUM_MAX; i++, engine++) {\n\t\tspin_lock_init(&engine->lock);\n\t\tspin_lock_init(&engine->desc_lock);\n\t\tINIT_LIST_HEAD(&engine->transfer_list);\n\t\tinit_waitqueue_head(&engine->shutdown_wq);\n\t\tinit_waitqueue_head(&engine->xdma_perf_wq);\n\t}\n\n\treturn xdev;\n}\n\nstatic int request_regions(struct xdma_dev *xdev, struct pci_dev *pdev)\n{\n\tint rv;\n\n\tBUG_ON(!xdev);\n\tBUG_ON(!pdev);\n\n\tdbg_init(\"pci_request_regions()\\n\");\n\trv = pci_request_regions(pdev, xdev->mod_name);\n\t/* could not request all regions? */\n\tif (rv) {\n\t\tdbg_init(\"pci_request_regions() = %d, device in use?\\n\", rv);\n\t\t/* assume device is in use so do not disable it later */\n\t\txdev->regions_in_use = 1;\n\t} else {\n\t\txdev->got_regions = 1;\n\t}\n\n\treturn rv;\n}\n\nstatic int set_dma_mask(struct pci_dev *pdev)\n{\n\tBUG_ON(!pdev);\n\n\tdbg_init(\"sizeof(dma_addr_t) == %ld\\n\", sizeof(dma_addr_t));\n\t/* 64-bit addressing capability for XDMA? */\n\tif (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {\n\t\t/* query for DMA transfer */\n\t\t/* @see Documentation/DMA-mapping.txt */\n\t\tdbg_init(\"pci_set_dma_mask()\\n\");\n\t\t/* use 64-bit DMA */\n\t\tdbg_init(\"Using a 64-bit DMA mask.\\n\");\n\t\t/* use 32-bit DMA for descriptors */\n\t\tpci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));\n\t\t/* use 64-bit DMA, 32-bit for consistent */\n\t} else if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) {\n\t\tdbg_init(\"Could not set 64-bit DMA mask.\\n\");\n\t\tpci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));\n\t\t/* use 32-bit DMA */\n\t\tdbg_init(\"Using a 32-bit DMA mask.\\n\");\n\t} else {\n\t\tdbg_init(\"No suitable DMA possible.\\n\");\n\t\treturn -EINVAL;\n\t}\n\n\treturn 0;\n}\n\nstatic u32 get_engine_channel_id(struct engine_regs *regs)\n{\n\tu32 value;\n\n\tBUG_ON(!regs);\n\n\tvalue = read_register(&regs->identifier);\n\n\treturn (value & 0x00000f00U) >> 8;\n}\n\nstatic u32 get_engine_id(struct engine_regs *regs)\n{\n\tu32 value;\n\n\tBUG_ON(!regs);\n\n\tvalue = read_register(&regs->identifier);\n\treturn (value & 0xffff0000U) >> 16;\n}\n\nstatic void remove_engines(struct xdma_dev *xdev)\n{\n\tstruct xdma_engine *engine;\n\tint i;\n\n\tBUG_ON(!xdev);\n\n\t/* iterate over channels */\n\tfor (i = 0; i < xdev->h2c_channel_max; i++) {\n\t\tengine = &xdev->engine_h2c[i];\n\t\tif (engine->magic == MAGIC_ENGINE) {\n\t\t\tdbg_sg(\"Remove %s, %d\", engine->name, i);\n\t\t\tengine_destroy(xdev, engine);\n\t\t\tdbg_sg(\"%s, %d removed\", engine->name, i);\n\t\t}\n\t}\n\n\tfor (i = 0; i < xdev->c2h_channel_max; i++) {\n\t\tengine = &xdev->engine_c2h[i];\n\t\tif (engine->magic == MAGIC_ENGINE) {\n\t\t\tdbg_sg(\"Remove %s, %d\", engine->name, i);\n\t\t\tengine_destroy(xdev, engine);\n\t\t\tdbg_sg(\"%s, %d removed\", engine->name, i);\n\t\t}\n\t}\n}\n\nstatic int probe_for_engine(struct xdma_dev *xdev, enum dma_data_direction dir,\n\t\t\tint channel)\n{\n\tstruct engine_regs *regs;\n\tint offset = channel * CHANNEL_SPACING;\n\tu32 engine_id;\n\tu32 engine_id_expected;\n\tu32 channel_id;\n\tstruct xdma_engine *engine;\n\tint rv;\n\n\t/* register offset for the engine */\n\t/* read channels at 0x0000, write channels at 0x1000,\n\t * channels at 0x100 interval */\n\tif (dir == DMA_TO_DEVICE) {\n\t\tengine_id_expected = XDMA_ID_H2C;\n\t\tengine = &xdev->engine_h2c[channel];\n\t} else {\n\t\toffset += H2C_CHANNEL_OFFSET;\n\t\tengine_id_expected = XDMA_ID_C2H;\n\t\tengine = &xdev->engine_c2h[channel];\n\t}\n\n\tregs = xdev->bar[xdev->config_bar_idx] + offset;\n\tengine_id = get_engine_id(regs);\n\tchannel_id = get_engine_channel_id(regs);\n\n\tif ((engine_id != engine_id_expected) || (channel_id != channel)) {\n\t\tdbg_init(\"%s %d engine, reg off 0x%x, id mismatch 0x%x,0x%x,\"\n\t\t\t\"exp 0x%x,0x%x, SKIP.\\n\",\n\t\t \tdir == DMA_TO_DEVICE ? \"H2C\" : \"C2H\",\n\t\t\t channel, offset, engine_id, channel_id,\n\t\t\tengine_id_expected, channel_id != channel);\n\t\treturn -EINVAL;\n\t}\n\n\tdbg_init(\"found AXI %s %d engine, reg. off 0x%x, id 0x%x,0x%x.\\n\",\n\t\t dir == DMA_TO_DEVICE ? \"H2C\" : \"C2H\", channel,\n\t\t offset, engine_id, channel_id);\n\n\t/* allocate and initialize engine */\n\trv = engine_init(engine, xdev, offset, dir, channel);\n\tif (rv != 0) {\n\t\tpr_info(\"failed to create AXI %s %d engine.\\n\",\n\t\t\tdir == DMA_TO_DEVICE ? \"H2C\" : \"C2H\",\n\t\t\tchannel);\n\t\treturn rv;\n\t}\n\n\treturn 0;\n}\n\nstatic int probe_engines(struct xdma_dev *xdev)\n{\n\tint i;\n\tint rv = 0;\n\n\tBUG_ON(!xdev);\n\n\t/* iterate over channels */\n\tfor (i = 0; i < xdev->h2c_channel_max; i++) {\n\t\trv = probe_for_engine(xdev, DMA_TO_DEVICE, i);\n\t\tif (rv)\n\t\t\tbreak;\n\t}\n\txdev->h2c_channel_max = i;\n\n\tfor (i = 0; i < xdev->c2h_channel_max; i++) {\n\t\trv = probe_for_engine(xdev, DMA_FROM_DEVICE, i);\n\t\tif (rv)\n\t\t\tbreak;\n\t}\n\txdev->c2h_channel_max = i;\n\n\treturn 0;\n}\n\n#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,5,0)\nstatic void pci_enable_relaxed_ordering(struct pci_dev *pdev)\n{\n\tpcie_capability_set_word(pdev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_RELAX_EN);\n}\n#else\nstatic void pci_enable_relaxed_ordering(struct pci_dev *pdev)\n{\n\tu16 v;\n\tint pos;\n\n\tpos = pci_pcie_cap(pdev);\n\tif (pos > 0) {\n\t\tpci_read_config_word(pdev, pos + PCI_EXP_DEVCTL, &v);\n\t\tv |= PCI_EXP_DEVCTL_RELAX_EN;\n\t\tpci_write_config_word(pdev, pos + PCI_EXP_DEVCTL, v);\n\t}\n}\n#endif\n\nstatic void pci_check_extended_tag(struct xdma_dev *xdev, struct pci_dev *pdev)\n{\n\tu16 cap;\n\tu32 v;\n\tvoid *__iomem reg;\n\n#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,5,0)\n\tpcie_capability_read_word(pdev, PCI_EXP_DEVCTL, &cap);\n#else\n\tint pos;\n\n\tpos = pci_pcie_cap(pdev);\n\tif (pos > 0)\n\t\tpci_read_config_word(pdev, pos + PCI_EXP_DEVCTL, &cap);\n\telse {\n\t\tpr_info(\"pdev 0x%p, unable to access pcie cap.\\n\", pdev);\n\t\treturn;\n\t}\n#endif\n\n\tif ((cap & PCI_EXP_DEVCTL_EXT_TAG))\n\t\treturn;\n\n\t/* extended tag not enabled */\n\tpr_info(\"0x%p EXT_TAG disabled.\\n\", pdev);\n\n\tif (xdev->config_bar_idx < 0) {\n\t\tpr_info(\"pdev 0x%p, xdev 0x%p, config bar UNKNOWN.\\n\",\n\t\t\tpdev, xdev);\n                return;\n\t}\n\n\treg = xdev->bar[xdev->config_bar_idx] + XDMA_OFS_CONFIG + 0x4C;\n\tv =  read_register(reg);\n\tv = (v & 0xFF) | (((u32)32) << 8);\n\twrite_register(v, reg, XDMA_OFS_CONFIG + 0x4C);\n}\n\nvoid *xdma_device_open(const char *mname, struct pci_dev *pdev, int *user_max,\n\t\t\tint *h2c_channel_max, int *c2h_channel_max)\n{\n\tstruct xdma_dev *xdev = NULL;\n\tint rv = 0;\n\n\tpr_info(\"%s device %s, 0x%p.\\n\", mname, dev_name(&pdev->dev), pdev);\n\n\t/* allocate zeroed device book keeping structure */\n\txdev = alloc_dev_instance(pdev);\n\tif (!xdev)\n\t\treturn NULL;\n\txdev->mod_name = mname;\n\txdev->user_max = *user_max;\n\txdev->h2c_channel_max = *h2c_channel_max;\n\txdev->c2h_channel_max = *c2h_channel_max;\n\n\txdma_device_flag_set(xdev, XDEV_FLAG_OFFLINE);\n\txdev_list_add(xdev);\n\n\tif (xdev->user_max == 0 || xdev->user_max > MAX_USER_IRQ)\n\t\txdev->user_max = MAX_USER_IRQ;\n\tif (xdev->h2c_channel_max == 0 ||\n\t    xdev->h2c_channel_max > XDMA_CHANNEL_NUM_MAX) \n\t\txdev->h2c_channel_max = XDMA_CHANNEL_NUM_MAX;\n\tif (xdev->c2h_channel_max == 0 ||\n\t    xdev->c2h_channel_max > XDMA_CHANNEL_NUM_MAX) \n\t\txdev->c2h_channel_max = XDMA_CHANNEL_NUM_MAX;\n\t\t\n\trv = pci_enable_device(pdev);\n\tif (rv) {\n\t\tdbg_init(\"pci_enable_device() failed, %d.\\n\", rv);\n\t\tgoto err_enable;\n\t}\n\n\t/* keep INTx enabled */\n\tpci_check_intr_pend(pdev);\n\n\t/* enable relaxed ordering */\n\tpci_enable_relaxed_ordering(pdev);\n\n\tpci_check_extended_tag(xdev, pdev);\n\n\t/* force MRRS to be 512 */\n\trv = pcie_set_readrq(pdev, 512);\n\tif (rv)\n\t\tpr_info(\"device %s, error set PCI_EXP_DEVCTL_READRQ: %d.\\n\",\n\t\t\tdev_name(&pdev->dev), rv);\n\n\t/* enable bus master capability */\n\tpci_set_master(pdev);\n\n\trv = request_regions(xdev, pdev);\n\tif (rv)\n\t\tgoto err_regions;\n\n\trv = map_bars(xdev, pdev);\n\tif (rv)\n\t\tgoto err_map;\n\n\trv = set_dma_mask(pdev);\n\tif (rv)\n\t\tgoto err_mask;\n\n\tcheck_nonzero_interrupt_status(xdev);\n\t/* explicitely zero all interrupt enable masks */\n\tchannel_interrupts_disable(xdev, ~0);\n\tuser_interrupts_disable(xdev, ~0);\n\tread_interrupts(xdev);\n\n\trv = probe_engines(xdev);\n\tif (rv)\n\t\tgoto err_engines;\n\n\trv = enable_msi_msix(xdev, pdev);\n\tif (rv < 0)\n\t\tgoto err_enable_msix;\n\n\trv = irq_setup(xdev, pdev);\n\tif (rv < 0)\n\t\tgoto err_interrupts;\n\n\tif (!poll_mode)\n\t\tchannel_interrupts_enable(xdev, ~0);\n\n\t/* Flush writes */\n\tread_interrupts(xdev);\n\n\t*user_max = xdev->user_max;\n\t*h2c_channel_max = xdev->h2c_channel_max;\n\t*c2h_channel_max = xdev->c2h_channel_max;\n\n\txdma_device_flag_clear(xdev, XDEV_FLAG_OFFLINE);\n\treturn (void *)xdev;\n\nerr_interrupts:\n\tirq_teardown(xdev);\nerr_enable_msix:\n\tdisable_msi_msix(xdev, pdev);\nerr_engines:\n\tremove_engines(xdev);\nerr_mask:\n\tunmap_bars(xdev, pdev);\nerr_map:\n\tif (xdev->got_regions)\n\t\tpci_release_regions(pdev);\nerr_regions:\n\tif (!xdev->regions_in_use)\n\t\tpci_disable_device(pdev);\nerr_enable:\n\txdev_list_remove(xdev);\n\tkfree(xdev);\n\treturn NULL;\n}\nEXPORT_SYMBOL_GPL(xdma_device_open);\n\nvoid xdma_device_close(struct pci_dev *pdev, void *dev_hndl)\n{\n\tstruct xdma_dev *xdev = (struct xdma_dev *)dev_hndl;\n\n\tdbg_init(\"pdev 0x%p, xdev 0x%p.\\n\", pdev, dev_hndl);\n\n\tif (!dev_hndl)\n\t\treturn;\n\n\tif (debug_check_dev_hndl(__func__, pdev, dev_hndl) < 0)\n\t\treturn;\n\n\tdbg_sg(\"remove(dev = 0x%p) where pdev->dev.driver_data = 0x%p\\n\",\n\t\t   pdev, xdev);\n\tif (xdev->pdev != pdev) {\n\t\tdbg_sg(\"pci_dev(0x%lx) != pdev(0x%lx)\\n\",\n\t\t\t(unsigned long)xdev->pdev, (unsigned long)pdev);\n\t}\n\n\tchannel_interrupts_disable(xdev, ~0);\n\tuser_interrupts_disable(xdev, ~0);\n\tread_interrupts(xdev);\n\n\tirq_teardown(xdev);\n\tdisable_msi_msix(xdev, pdev);\n\n\tremove_engines(xdev);\n\tunmap_bars(xdev, pdev);\n\n\tif (xdev->got_regions) {\n\t\tdbg_init(\"pci_release_regions 0x%p.\\n\", pdev);\n\t\tpci_release_regions(pdev);\n\t}\n\n\tif (!xdev->regions_in_use) {\n\t\tdbg_init(\"pci_disable_device 0x%p.\\n\", pdev);\n\t\tpci_disable_device(pdev);\n\t}\n\n\txdev_list_remove(xdev);\n\n\tkfree(xdev);\n}\nEXPORT_SYMBOL_GPL(xdma_device_close);\n\nvoid xdma_device_offline(struct pci_dev *pdev, void *dev_hndl)\n{\n\tstruct xdma_dev *xdev = (struct xdma_dev *)dev_hndl;\n\tstruct xdma_engine *engine;\n\tint i;\n\n\tif (!dev_hndl)\n\t\treturn;\n\n\tif (debug_check_dev_hndl(__func__, pdev, dev_hndl) < 0)\n\t\treturn;\n\npr_info(\"pdev 0x%p, xdev 0x%p.\\n\", pdev, xdev);\n\txdma_device_flag_set(xdev, XDEV_FLAG_OFFLINE);\n\n\t/* wait for all engines to be idle */\n\tfor (i  = 0; i < xdev->h2c_channel_max; i++) {\n\t\tunsigned long flags;\n\n\t\tengine = &xdev->engine_h2c[i];\n\t\t\n\t\tif (engine->magic == MAGIC_ENGINE) {\n\t\t\tspin_lock_irqsave(&engine->lock, flags);\n\t\t\tengine->shutdown |= ENGINE_SHUTDOWN_REQUEST;\n\n\t\t\txdma_engine_stop(engine);\n\t\t\tengine->running = 0;\n\t\t\tspin_unlock_irqrestore(&engine->lock, flags);\n\t\t}\n\t}\n\n\tfor (i  = 0; i < xdev->c2h_channel_max; i++) {\n\t\tunsigned long flags;\n\n\t\tengine = &xdev->engine_c2h[i];\n\t\tif (engine->magic == MAGIC_ENGINE) {\n\t\t\tspin_lock_irqsave(&engine->lock, flags);\n\t\t\tengine->shutdown |= ENGINE_SHUTDOWN_REQUEST;\n\n\t\t\txdma_engine_stop(engine);\n\t\t\tengine->running = 0;\n\t\t\tspin_unlock_irqrestore(&engine->lock, flags);\n\t\t}\n\t}\n\n\t/* turn off interrupts */\n\tchannel_interrupts_disable(xdev, ~0);\n\tuser_interrupts_disable(xdev, ~0);\n\tread_interrupts(xdev);\n\tirq_teardown(xdev);\n\n\tpr_info(\"xdev 0x%p, done.\\n\", xdev);\n}\nEXPORT_SYMBOL_GPL(xdma_device_offline);\n\nvoid xdma_device_online(struct pci_dev *pdev, void *dev_hndl)\n{\n\tstruct xdma_dev *xdev = (struct xdma_dev *)dev_hndl;\n\tstruct xdma_engine *engine;\n\tunsigned long flags;\n\tint i;\n\n\tif (!dev_hndl)\n\t\treturn;\n\n\tif (debug_check_dev_hndl(__func__, pdev, dev_hndl) < 0)\n\t\treturn;\n\npr_info(\"pdev 0x%p, xdev 0x%p.\\n\", pdev, xdev);\n\n\tfor (i  = 0; i < xdev->h2c_channel_max; i++) {\n\t\tengine = &xdev->engine_h2c[i];\n\t\tif (engine->magic == MAGIC_ENGINE) {\n\t\t\tengine_init_regs(engine);\n\t\t\tspin_lock_irqsave(&engine->lock, flags);\n\t\t\tengine->shutdown &= ~ENGINE_SHUTDOWN_REQUEST;\n\t\t\tspin_unlock_irqrestore(&engine->lock, flags);\n\t\t}\n\t}\n\n\tfor (i  = 0; i < xdev->c2h_channel_max; i++) {\n\t\tengine = &xdev->engine_c2h[i];\n\t\tif (engine->magic == MAGIC_ENGINE) {\n\t\t\tengine_init_regs(engine);\n\t\t\tspin_lock_irqsave(&engine->lock, flags);\n\t\t\tengine->shutdown &= ~ENGINE_SHUTDOWN_REQUEST;\n\t\t\tspin_unlock_irqrestore(&engine->lock, flags);\n\t\t}\n\t}\n\n\t/* re-write the interrupt table */\n\tif (!poll_mode) {\n\t\tirq_setup(xdev, pdev);\n\n\t\tchannel_interrupts_enable(xdev, ~0);\n\t\tuser_interrupts_enable(xdev, xdev->mask_irq_user);\n\t\tread_interrupts(xdev);\n\t}\n\t\n\txdma_device_flag_clear(xdev, XDEV_FLAG_OFFLINE);\npr_info(\"xdev 0x%p, done.\\n\", xdev);\n}\nEXPORT_SYMBOL_GPL(xdma_device_online);\n\nint xdma_device_restart(struct pci_dev *pdev, void *dev_hndl)\n{\n\tstruct xdma_dev *xdev = (struct xdma_dev *)dev_hndl;\n\n\tif (!dev_hndl)\n\t\treturn -EINVAL;\n\n\tif (debug_check_dev_hndl(__func__, pdev, dev_hndl) < 0)\n\t\treturn -EINVAL;\n\n\tpr_info(\"NOT implemented, 0x%p.\\n\", xdev);\n\treturn -EINVAL;\n}\nEXPORT_SYMBOL_GPL(xdma_device_restart);\n\nint xdma_user_isr_register(void *dev_hndl, unsigned int mask,\n\t\t\tirq_handler_t handler, void *dev)\n{\n\tstruct xdma_dev *xdev = (struct xdma_dev *)dev_hndl;\n\tint i;\n\n\tif (!dev_hndl)\n\t\treturn -EINVAL;\n\n\tif (debug_check_dev_hndl(__func__, xdev->pdev, dev_hndl) < 0)\n\t\treturn -EINVAL;\n\n\tfor (i = 0; i < xdev->user_max && mask; i++) {\n\t\tunsigned int bit = (1 << i);\n\n\t\tif ((bit & mask) == 0)\n\t\t\tcontinue;\n\n\t\tmask &= ~bit;\n\t\txdev->user_irq[i].handler = handler;\n\t\txdev->user_irq[i].dev = dev;\n\t}\n\n\treturn 0;\n}\nEXPORT_SYMBOL_GPL(xdma_user_isr_register);\n\nint xdma_user_isr_enable(void *dev_hndl, unsigned int mask)\n{\n\tstruct xdma_dev *xdev = (struct xdma_dev *)dev_hndl;\n\n\tif (!dev_hndl)\n\t\treturn -EINVAL;\n\n\tif (debug_check_dev_hndl(__func__, xdev->pdev, dev_hndl) < 0)\n\t\treturn -EINVAL;\n\n\txdev->mask_irq_user |= mask;\n\t/* enable user interrupts */\n\tuser_interrupts_enable(xdev, mask);\n\tread_interrupts(xdev);\n\n\treturn 0;\n}\nEXPORT_SYMBOL_GPL(xdma_user_isr_enable);\n\nint xdma_user_isr_disable(void *dev_hndl, unsigned int mask)\n{\n\tstruct xdma_dev *xdev = (struct xdma_dev *)dev_hndl;\n\n\tif (!dev_hndl)\n\t\treturn -EINVAL;\n\n\tif (debug_check_dev_hndl(__func__, xdev->pdev, dev_hndl) < 0)\n\t\treturn -EINVAL;\n\t\n\txdev->mask_irq_user &= ~mask;\n\tuser_interrupts_disable(xdev, mask);\n\tread_interrupts(xdev);\n\n\treturn 0;\n}\nEXPORT_SYMBOL_GPL(xdma_user_isr_disable);\n\n#ifdef __LIBXDMA_MOD__\nstatic int __init xdma_base_init(void)\n{\n\tprintk(KERN_INFO \"%s\", version);\n\treturn 0;\n}\n\nstatic void __exit xdma_base_exit(void)\n{\n\treturn;\n}\n\nmodule_init(xdma_base_init);\nmodule_exit(xdma_base_exit);\n#endif\n/* makes an existing transfer cyclic */\nstatic void xdma_transfer_cyclic(struct xdma_transfer *transfer)\n{\n\t/* link last descriptor to first descriptor */\n\txdma_desc_link(transfer->desc_virt + transfer->desc_num - 1,\n\t\t\ttransfer->desc_virt, transfer->desc_bus);\n\t/* remember transfer is cyclic */\n\ttransfer->cyclic = 1;\n}\n\nstatic int transfer_monitor_cyclic(struct xdma_engine *engine,\n\t\t\tstruct xdma_transfer *transfer, int timeout_ms)\n{\n\tstruct xdma_result *result;\n\tint rc = 0;\n\n\tBUG_ON(!engine);\n\tBUG_ON(!transfer);\n\n\tresult = engine->cyclic_result;\n\tBUG_ON(!result);\n\n\tif (poll_mode) {\n\t\tint i ; \n\t\tfor (i = 0; i < 5; i++) {\n\t\t\trc = engine_service_poll(engine, 0);\n\t\t\tif (rc) {\n\t\t\t\tpr_info(\"%s service_poll failed %d.\\n\",\n\t\t\t\t\tengine->name, rc);\n\t\t\t\trc = -ERESTARTSYS;\n\t\t\t}\n\t\t\tif (result[engine->rx_head].status)\n\t\t\t\treturn 0;\n\t\t}\n\t} else {\n\t\tif (enable_credit_mp){\n\t\t\tdbg_tfr(\"%s: rx_head=%d,rx_tail=%d, wait ...\\n\",\n\t\t\t\tengine->name, engine->rx_head, engine->rx_tail);\n\t\t\trc = wait_event_interruptible_timeout( transfer->wq,\n\t\t\t\t\t(engine->rx_head!=engine->rx_tail ||\n\t\t\t\t\t engine->rx_overrun),\n\t\t\t\t\tmsecs_to_jiffies(timeout_ms));\n\t\t\tdbg_tfr(\"%s: wait returns %d, rx %d/%d, overrun %d.\\n\",\n\t\t\t\t engine->name, rc, engine->rx_head,\n\t\t\t\tengine->rx_tail, engine->rx_overrun);\n\t\t} else {\n\t\t\trc = wait_event_interruptible_timeout( transfer->wq,\n\t\t\t\t\tengine->eop_found,\n\t\t\t\t\tmsecs_to_jiffies(timeout_ms));\n\t\t\tdbg_tfr(\"%s: wait returns %d, eop_found %d.\\n\",\n\t\t\t\tengine->name, rc, engine->eop_found);\n\t\t}\n\t}\n\n\treturn 0;\n}\n\nstruct scatterlist *sglist_index(struct sg_table *sgt, unsigned int idx)\n{\n\tstruct scatterlist *sg = sgt->sgl;\n\tint i;\n\n\tif (idx >= sgt->orig_nents)\n\t\treturn NULL;\n\n\tif (!idx)\n\t\treturn sg;\n\n\tfor (i = 0; i < idx; i++, sg = sg_next(sg))\n\t\t;\n\n\treturn sg;\n}\n\nstatic int copy_cyclic_to_user(struct xdma_engine *engine, int pkt_length,\n\t\t\t\tint head, char __user *buf, size_t count)\n{\n\tstruct scatterlist *sg;\n\tint more = pkt_length;\n\n\tBUG_ON(!engine);\n\tBUG_ON(!buf);\n\n\tdbg_tfr(\"%s, pkt_len %d, head %d, user buf idx %u.\\n\",\n\t\tengine->name, pkt_length, head, engine->user_buffer_index);\n\n\tsg = sglist_index(&engine->cyclic_sgt, head);\n\tif (!sg) {\n\t\tpr_info(\"%s, head %d OOR, sgl %u.\\n\",\n\t\t\tengine->name, head, engine->cyclic_sgt.orig_nents);\n\t\treturn -EIO;\n\t}\n\n\t/* EOP found? Transfer anything from head to EOP */\n\twhile (more) {\n\t\tunsigned int copy = more > PAGE_SIZE ? PAGE_SIZE : more; \n\t\tunsigned int blen = count - engine->user_buffer_index;\n\t\tint rv;\n\n\t\tif (copy > blen)\n\t\t\tcopy = blen;\n\n\t\tdbg_tfr(\"%s sg %d, 0x%p, copy %u to user %u.\\n\",\n\t\t\tengine->name, head, sg, copy,\n\t\t\tengine->user_buffer_index);\n\n\t\trv = copy_to_user(&buf[engine->user_buffer_index],\n\t\t\tpage_address(sg_page(sg)), copy);\n\t\tif (rv) {\n\t\t\tpr_info(\"%s copy_to_user %u failed %d\\n\",\n\t\t\t\tengine->name, copy, rv);\n\t\t\treturn -EIO;\n\t\t}\n\n\t\tmore -= copy;\n\t\tengine->user_buffer_index += copy;\n\n\t\tif (engine->user_buffer_index == count) {\n\t\t\t/* user buffer used up */\n\t\t\tbreak;\n\t\t}\n\t\t\n\t\thead++;\n\t\tif (head >= CYCLIC_RX_PAGES_MAX) {\n\t\t\thead = 0;\n\t\t\tsg = engine->cyclic_sgt.sgl;\n\t\t} else\n\t\t\tsg = sg_next(sg);\n\t}\n\n\treturn pkt_length;\n}\n\nstatic int complete_cyclic(struct xdma_engine *engine, char __user *buf,\n\t\t\t   size_t count)\n{\n\tstruct xdma_result *result;\n\tint pkt_length = 0;\n\tint fault = 0;\n\tint eop = 0;\n\tint head;\n\tint rc = 0;\n\tint num_credit = 0;\n\tunsigned long flags;\n\n\tBUG_ON(!engine);\n\tresult = engine->cyclic_result;\n\tBUG_ON(!result);\n\n\tspin_lock_irqsave(&engine->lock, flags);\n\n\t/* where the host currently is in the ring buffer */\n\thead = engine->rx_head;\n\n\t/* iterate over newly received results */\n\twhile (engine->rx_head != engine->rx_tail||engine->rx_overrun) {\n\n\t\tWARN_ON(result[engine->rx_head].status==0);\n\n\t\tdbg_tfr(\"%s, result[%d].status = 0x%x length = 0x%x.\\n\",\n\t\t\tengine->name, engine->rx_head, \n\t\t\tresult[engine->rx_head].status,\n\t\t\tresult[engine->rx_head].length);\n\n\t\tif ((result[engine->rx_head].status >> 16) != C2H_WB) {\n\t\t\tpr_info(\"%s, result[%d].status 0x%x, no magic.\\n\",\n\t\t\t\tengine->name, engine->rx_head,\n\t\t\t\tresult[engine->rx_head].status);\n\t\t\tfault = 1;\n\t\t} else if (result[engine->rx_head].length > PAGE_SIZE) {\n\t\t\tpr_info(\"%s, result[%d].len 0x%x, > PAGE_SIZE 0x%lx.\\n\",\n\t\t\t\tengine->name, engine->rx_head,\n\t\t\t\tresult[engine->rx_head].length, PAGE_SIZE);\n\t\t\tfault = 1;\n\t\t} else if (result[engine->rx_head].length == 0) {\n\t\t\tpr_info(\"%s, result[%d].length 0x%x.\\n\",\n\t\t\t\tengine->name, engine->rx_head,\n\t\t\t\tresult[engine->rx_head].length);\n\t\t\tfault = 1;\n\t\t\t/* valid result */\n\t\t} else {\n\t\t\tpkt_length += result[engine->rx_head].length;\n\t\t\tnum_credit++; \n\t\t\t/* seen eop? */\n\t\t\t//if (result[engine->rx_head].status & RX_STATUS_EOP)\n\t\t\tif (result[engine->rx_head].status & RX_STATUS_EOP){\n\t\t\t\teop = 1;\n\t\t\t\tengine->eop_found = 1;\n\t\t\t}\n\n\t\t\tdbg_tfr(\"%s, pkt_length=%d (%s)\\n\",\n\t\t\t\tengine->name, pkt_length,\n\t\t\t\teop ? \"with EOP\" : \"no EOP yet\");\n\t\t}\n\t\t/* clear result */\n\t\tresult[engine->rx_head].status = 0;\n\t\tresult[engine->rx_head].length = 0;\n\t\t/* proceed head pointer so we make progress, even when fault */\n\t\tengine->rx_head = (engine->rx_head + 1) % CYCLIC_RX_PAGES_MAX;\n\n\t\t/* stop processing if a fault/eop was detected */\n\t\tif (fault || eop){\n\t\t\tbreak;\n\t\t}\n\t}\n\n\tspin_unlock_irqrestore(&engine->lock, flags);\n\n\tif (fault)\n\t\treturn -EIO;\n\t\t\n\trc = copy_cyclic_to_user(engine, pkt_length, head, buf, count);\n\tengine->rx_overrun = 0; \n\t/* if copy is successful, release credits */\n\tif(rc > 0)\n\t\twrite_register(num_credit,&engine->sgdma_regs->credits, 0);\n\n\treturn rc;\n}\n\nssize_t xdma_engine_read_cyclic(struct xdma_engine *engine, char __user *buf,\n\t\t\t\tsize_t count, int timeout_ms)\n{\n\tint i = 0;\n\tint rc = 0;\n\tint rc_len = 0;\n\tstruct xdma_transfer *transfer;\n\n\tBUG_ON(!engine);\n\tBUG_ON(engine->magic != MAGIC_ENGINE);\n\n\ttransfer = &engine->cyclic_req->xfer;\n\tBUG_ON(!transfer);\n\n        engine->user_buffer_index = 0;\n        \n\tdo {\n\t\trc = transfer_monitor_cyclic(engine, transfer, timeout_ms);\n\t\tif (rc < 0)\n\t\t\treturn rc;\n\t\trc = complete_cyclic(engine, buf, count);\n\t\tif (rc < 0)\n\t\t\treturn rc;\n\t\trc_len += rc;\n\n\t\ti++;\n\t\tif (i > 10)\n\t\t\tbreak;\n\t} while (!engine->eop_found);\n\n\tif(enable_credit_mp)\n\t\tengine->eop_found = 0;\n\n\treturn rc_len;\n}\n\nstatic void sgt_free_with_pages(struct sg_table *sgt, int dir,\n\t\t\t\tstruct pci_dev *pdev)\n{\n\tstruct scatterlist *sg = sgt->sgl;\n\tint npages = sgt->orig_nents;\n\tint i;\n\n\tfor (i = 0; i < npages; i++, sg = sg_next(sg)) {\n\t\tstruct page *pg = sg_page(sg);\n\t\tdma_addr_t bus = sg_dma_address(sg);\n\n\t\tif (pg) {\n\t\t\tif (pdev)\n\t\t\t\tpci_unmap_page(pdev, bus, PAGE_SIZE, dir);\n\t\t\t__free_page(pg);\n\t\t} else\n\t\t\tbreak;\n\t}\n\tsg_free_table(sgt);\n\tmemset(sgt, 0, sizeof(struct sg_table));\n}\n\nstatic int sgt_alloc_with_pages(struct sg_table *sgt, unsigned int npages,\n\t\t\t\tint dir, struct pci_dev *pdev)\n{\n\tstruct scatterlist *sg;\n\tint i;\n\n\tif (sg_alloc_table(sgt, npages, GFP_KERNEL)) {\n\t\tpr_info(\"sgt OOM.\\n\");\n\t\treturn -ENOMEM;\n\t}\n\n\tsg = sgt->sgl;\n\tfor (i = 0; i < npages; i++, sg = sg_next(sg)) {\n\t\tstruct page *pg = alloc_page(GFP_KERNEL);\n\n        \tif (!pg) {\n\t\t\tpr_info(\"%d/%u, page OOM.\\n\", i, npages);\n\t\t\tgoto err_out;\n\t\t}\n\n\t\tif (pdev) {\n\t\t\tdma_addr_t bus = pci_map_page(pdev, pg, 0, PAGE_SIZE,\n\t\t\t\t\t\t\tdir);\n                \tif (unlikely(pci_dma_mapping_error(pdev, bus))) {\n\t\t\t\tpr_info(\"%d/%u, page 0x%p map err.\\n\",\n\t\t\t\t\t i, npages, pg);\n\t\t\t\t__free_page(pg);\n\t\t\t\tgoto err_out;\n\t\t\t}\n\t\t\tsg_dma_address(sg) = bus;\n\t\t\tsg_dma_len(sg) = PAGE_SIZE;\n\t\t}\n\t\tsg_set_page(sg, pg, PAGE_SIZE, 0);\n\t}\n\n\tsgt->orig_nents = sgt->nents = npages;\n\n\treturn 0;\n\nerr_out:\n\tsgt_free_with_pages(sgt, dir, pdev);\n\treturn -ENOMEM; \n}\n\nint xdma_cyclic_transfer_setup(struct xdma_engine *engine)\n{\n\tstruct xdma_dev *xdev;\n\tstruct xdma_transfer *xfer;\n\tdma_addr_t bus;\n\tunsigned long flags;\n\tint i;\n\tint rc;\n\n\tBUG_ON(!engine);\n\txdev = engine->xdev;\n\tBUG_ON(!xdev);\n\n\tif (engine->cyclic_req) {\n\t\tpr_info(\"%s: exclusive access already taken.\\n\",\n\t\t\tengine->name);\n\t\treturn -EBUSY;\n\t}\n\n\tspin_lock_irqsave(&engine->lock, flags);\n\n\tengine->rx_tail = 0;\n\tengine->rx_head = 0;\n\tengine->rx_overrun = 0;\n\tengine->eop_found = 0;\n\n\trc = sgt_alloc_with_pages(&engine->cyclic_sgt, CYCLIC_RX_PAGES_MAX,\n\t\t\t\tengine->dir, xdev->pdev);\n\tif (rc < 0) {\n\t\tpr_info(\"%s cyclic pages %u OOM.\\n\",\n\t\t\tengine->name, CYCLIC_RX_PAGES_MAX);\n\t\tgoto err_out;\n\t}\n\n\tengine->cyclic_req = xdma_init_request(&engine->cyclic_sgt, 0);\n\tif (!engine->cyclic_req) {\n\t\tpr_info(\"%s cyclic request OOM.\\n\", engine->name);\n\t\trc = -ENOMEM;\n\t\tgoto err_out;\n\t}\n\n#ifdef __LIBXDMA_DEBUG__\n\txdma_request_cb_dump(engine->cyclic_req);\n#endif\n\n\trc = transfer_init(engine, engine->cyclic_req);\n\tif (rc < 0)\n\t\tgoto err_out;\n\n\txfer = &engine->cyclic_req->xfer;\n\n\t/* replace source addresses with result write-back addresses */\n\tmemset(engine->cyclic_result, 0,\n\t\tCYCLIC_RX_PAGES_MAX * sizeof(struct xdma_result));\n\tbus = engine->cyclic_result_bus;\n        for (i = 0; i < xfer->desc_num; i++) {\n\t\txfer->desc_virt[i].src_addr_lo = cpu_to_le32(PCI_DMA_L(bus));\n        \txfer->desc_virt[i].src_addr_hi = cpu_to_le32(PCI_DMA_H(bus));\n                bus += sizeof(struct xdma_result);\n        }\n\t/* set control of all descriptors */\n        for (i = 0; i < xfer->desc_num; i++) {\n                xdma_desc_control_clear(xfer->desc_virt + i, LS_BYTE_MASK);\n                xdma_desc_control_set(xfer->desc_virt + i,\n\t\t\t\t XDMA_DESC_EOP | XDMA_DESC_COMPLETED);\n        }\n\n\t/* make this a cyclic transfer */\n\txdma_transfer_cyclic(xfer);\n\n#ifdef __LIBXDMA_DEBUG__\n\ttransfer_dump(xfer);\n#endif\n\n\tif(enable_credit_mp){\n\t\t//write_register(RX_BUF_PAGES,&engine->sgdma_regs->credits);\n\t\twrite_register(128, &engine->sgdma_regs->credits, 0);\n\t}\n\n\tspin_unlock_irqrestore(&engine->lock, flags);\n\n\t/* start cyclic transfer */\n\ttransfer_queue(engine, xfer);\n\n\treturn 0;\n\n\t/* unwind on errors */\nerr_out:\n\tif (engine->cyclic_req) {\n\t\txdma_request_free(engine->cyclic_req);\t\n\t\tengine->cyclic_req = NULL;\n\t}\n\t\n\tif (engine->cyclic_sgt.orig_nents) {\n\t\tsgt_free_with_pages(&engine->cyclic_sgt, engine->dir,\n\t\t\t\txdev->pdev);\n\t\tengine->cyclic_sgt.orig_nents = 0;\n\t\tengine->cyclic_sgt.nents = 0;\n\t\tengine->cyclic_sgt.sgl = NULL;\n\t}\n\n\tspin_unlock_irqrestore(&engine->lock, flags);\n\n\treturn rc;\n}\n\n\nstatic int cyclic_shutdown_polled(struct xdma_engine *engine)\n{\n\tBUG_ON(!engine);\n\n\tspin_lock(&engine->lock);\n\n\tdbg_tfr(\"Polling for shutdown completion\\n\");\n\tdo {\n\t\tengine_status_read(engine, 1, 0);\n\t\tschedule();\n\t} while (engine->status & XDMA_STAT_BUSY);\n\n\tif ((engine->running) && !(engine->status & XDMA_STAT_BUSY)) {\n\t\tdbg_tfr(\"Engine has stopped\\n\");\n\n\t\tif (!list_empty(&engine->transfer_list))\n\t\t\tengine_transfer_dequeue(engine);\n\n\t\tengine_service_shutdown(engine);\n\t}\n\n\tdbg_tfr(\"Shutdown completion polling done\\n\");\n\tspin_unlock(&engine->lock);\n\n\treturn 0;\n}\n\nstatic int cyclic_shutdown_interrupt(struct xdma_engine *engine)\n{\n\tint rc;\n\n\tBUG_ON(!engine);\n\n\trc = wait_event_interruptible_timeout(engine->shutdown_wq,\n\t\t\t\t!engine->running, msecs_to_jiffies(10000));\n\n#if 0\n\tif (rc) {\n\t\tdbg_tfr(\"wait_event_interruptible=%d\\n\", rc);\n\t\treturn rc;\n\t}\n#endif\n\n\tif (engine->running) {\n\t\tpr_info(\"%s still running?!, %d\\n\", engine->name, rc);\n\t\treturn -EINVAL;\n\t}\n\n\treturn rc;\n}\n\nint xdma_cyclic_transfer_teardown(struct xdma_engine *engine)\n{\n\tint rc;\n\tstruct xdma_dev *xdev = engine->xdev;\n\tstruct xdma_transfer *transfer;\n\tunsigned long flags;\n\n\ttransfer = engine_cyclic_stop(engine);\n\n\tspin_lock_irqsave(&engine->lock, flags);\n\tif (transfer) {\n\t\tdbg_tfr(\"%s: stop transfer 0x%p.\\n\", engine->name, transfer);\n\t\tif (transfer != &engine->cyclic_req->xfer) {\n\t\t\tpr_info(\"%s unexpected transfer 0x%p/0x%p\\n\",\n\t\t\t\tengine->name, transfer,\n\t\t\t\t&engine->cyclic_req->xfer);\n\t\t}\n\t}\n\t/* allow engine to be serviced after stop request */\n\tspin_unlock_irqrestore(&engine->lock, flags);\n\n\t/* wait for engine to be no longer running */\n\tif (poll_mode) \n\t\trc = cyclic_shutdown_polled(engine);\n\telse\n\t\trc = cyclic_shutdown_interrupt(engine);\n\n\t/* obtain spin lock to atomically remove resources */\n\tspin_lock_irqsave(&engine->lock, flags);\n\n\tif (engine->cyclic_req) {\n\t\txdma_request_free(engine->cyclic_req);\t\n\t\tengine->cyclic_req = NULL;\n\t}\n\n\tif (engine->cyclic_sgt.orig_nents) {\n\t\tsgt_free_with_pages(&engine->cyclic_sgt, engine->dir,\n\t\t\t\txdev->pdev);\n\t\tengine->cyclic_sgt.orig_nents = 0;\n\t\tengine->cyclic_sgt.nents = 0;\n\t\tengine->cyclic_sgt.sgl = NULL;\n\t}\n\n\tspin_unlock_irqrestore(&engine->lock, flags);\n\n\treturn 0;\n}\n\nint engine_addrmode_set(struct xdma_engine *engine, unsigned long arg)\n{\n\tint rv;\n\tunsigned long dst; \n\tu32 w = XDMA_CTRL_NON_INCR_ADDR;\n\n\tdbg_perf(\"IOCTL_XDMA_ADDRMODE_SET\\n\");\n\trv = get_user(dst, (int __user *)arg);\n\n\tif (rv == 0) { \n\t\tengine->non_incr_addr = !!dst;\n\t\tif (engine->non_incr_addr)\n\t\t\twrite_register(w, &engine->regs->control_w1s, \n\t\t\t\t(unsigned long)(&engine->regs->control_w1s) -\n\t\t\t\t(unsigned long)(&engine->regs));\n\t\telse\n\t\t\twrite_register(w, &engine->regs->control_w1c,\n\t\t\t\t(unsigned long)(&engine->regs->control_w1c) - \n\t\t\t\t(unsigned long)(&engine->regs));\n\t}\n\tengine_alignments(engine);\n\n\treturn rv;\n}\n\n"
  },
  {
    "path": "drivers/awsf1portal/libxdma.h",
    "content": "/*******************************************************************************\n *\n * Xilinx XDMA IP Core Linux Driver\n * Copyright(c) 2015 - 2017 Xilinx, Inc.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms and conditions of the GNU General Public License,\n * version 2, as published by the Free Software Foundation.\n *\n * This program is distributed in the hope it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\n * more details.\n *\n * You should have received a copy of the GNU General Public License along\n * with this program.  If not, see <http://www.gnu.org/licenses/>.\n *\n * The full GNU General Public License is included in this distribution in\n * the file called \"LICENSE\".\n *\n * Karen Xie <karen.xie@xilinx.com>\n *\n ******************************************************************************/\n#ifndef XDMA_LIB_H\n#define XDMA_LIB_H\n\n#include <linux/version.h>\n#include <linux/types.h>\n#include <linux/uaccess.h>\n#include <linux/module.h>\n#include <linux/dma-mapping.h>\n#include <linux/init.h>\n#include <linux/interrupt.h>\n#include <linux/jiffies.h>\n#include <linux/kernel.h>\n#include <linux/pci.h>\n#include <linux/workqueue.h>\n\n/* Switch debug printing on/off */\n#define XDMA_DEBUG 0\n\n#define XDMA_CONFIG_BAR_NUM (2) // no need to search for it. -Jamey\n\n/* SECTION: Preprocessor macros/constants */\n#define XDMA_BAR_NUM (6)\n\n/* maximum amount of register space to map */\n#define XDMA_BAR_SIZE (0x8000UL)\n\n/* Use this definition to poll several times between calls to schedule */\n#define NUM_POLLS_PER_SCHED 100\n\n#define XDMA_CHANNEL_NUM_MAX (4)\n/*\n * interrupts per engine, rad2_vul.sv:237\n * .REG_IRQ_OUT\t(reg_irq_from_ch[(channel*2) +: 2]),\n */\n#define XDMA_ENG_IRQ_NUM (1)\n#define MAX_EXTRA_ADJ (15)\n#define RX_STATUS_EOP (1)\n\n/* Target internal components on XDMA control BAR */\n#define XDMA_OFS_INT_CTRL\t(0x2000UL)\n#define XDMA_OFS_CONFIG\t\t(0x3000UL)\n\n/* maximum number of desc per transfer request */\n#define XDMA_TRANSFER_MAX_DESC (2048)\n\n/* maximum size of a single DMA transfer descriptor */\n#define XDMA_DESC_BLEN_BITS \t28\n#define XDMA_DESC_BLEN_MAX\t((1 << (XDMA_DESC_BLEN_BITS)) - 1)\n\n/* bits of the SG DMA control register */\n#define XDMA_CTRL_RUN_STOP\t\t\t(1UL << 0)\n#define XDMA_CTRL_IE_DESC_STOPPED\t\t(1UL << 1)\n#define XDMA_CTRL_IE_DESC_COMPLETED\t\t(1UL << 2)\n#define XDMA_CTRL_IE_DESC_ALIGN_MISMATCH\t(1UL << 3)\n#define XDMA_CTRL_IE_MAGIC_STOPPED\t\t(1UL << 4)\n#define XDMA_CTRL_IE_IDLE_STOPPED\t\t(1UL << 6)\n#define XDMA_CTRL_IE_READ_ERROR\t\t\t(0x1FUL << 9)\n#define XDMA_CTRL_IE_DESC_ERROR\t\t\t(0x1FUL << 19)\n#define XDMA_CTRL_NON_INCR_ADDR\t\t\t(1UL << 25)\n#define XDMA_CTRL_POLL_MODE_WB\t\t\t(1UL << 26)\n\n/* bits of the SG DMA status register */\n#define XDMA_STAT_BUSY\t\t\t(1UL << 0)\n#define XDMA_STAT_DESC_STOPPED\t\t(1UL << 1)\n#define XDMA_STAT_DESC_COMPLETED\t(1UL << 2)\n#define XDMA_STAT_ALIGN_MISMATCH\t(1UL << 3)\n#define XDMA_STAT_MAGIC_STOPPED\t\t(1UL << 4)\n#define XDMA_STAT_INVALID_LEN\t\t(1UL << 5)\n#define XDMA_STAT_IDLE_STOPPED\t\t(1UL << 6)\n\n#define XDMA_STAT_COMMON_ERR_MASK \\\n\t(XDMA_STAT_ALIGN_MISMATCH | XDMA_STAT_MAGIC_STOPPED | \\\n\t XDMA_STAT_INVALID_LEN)\n\n/* desc_error, C2H & H2C */\n#define XDMA_STAT_DESC_UNSUPP_REQ\t(1UL << 19)\n#define XDMA_STAT_DESC_COMPL_ABORT\t(1UL << 20)\n#define XDMA_STAT_DESC_PARITY_ERR\t(1UL << 21)\n#define XDMA_STAT_DESC_HEADER_EP\t(1UL << 22)\n#define XDMA_STAT_DESC_UNEXP_COMPL\t(1UL << 23)\n\n#define XDMA_STAT_DESC_ERR_MASK\t\\\n\t(XDMA_STAT_DESC_UNSUPP_REQ | XDMA_STAT_DESC_COMPL_ABORT | \\\n\t XDMA_STAT_DESC_PARITY_ERR | XDMA_STAT_DESC_HEADER_EP | \\\n\t XDMA_STAT_DESC_UNEXP_COMPL)\n\n/* read error: H2C */\n#define XDMA_STAT_H2C_R_UNSUPP_REQ\t(1UL << 9)\n#define XDMA_STAT_H2C_R_COMPL_ABORT\t(1UL << 10)\n#define XDMA_STAT_H2C_R_PARITY_ERR\t(1UL << 11)\n#define XDMA_STAT_H2C_R_HEADER_EP\t(1UL << 12)\n#define XDMA_STAT_H2C_R_UNEXP_COMPL\t(1UL << 13)\n\n#define XDMA_STAT_H2C_R_ERR_MASK\t\\\n\t(XDMA_STAT_H2C_R_UNSUPP_REQ | XDMA_STAT_H2C_R_COMPL_ABORT | \\\n\t XDMA_STAT_H2C_R_PARITY_ERR | XDMA_STAT_H2C_R_HEADER_EP | \\\n\t XDMA_STAT_H2C_R_UNEXP_COMPL)\n\n/* write error, H2C only */\n#define XDMA_STAT_H2C_W_DECODE_ERR\t(1UL << 14)\n#define XDMA_STAT_H2C_W_SLAVE_ERR\t(1UL << 15)\n\n#define XDMA_STAT_H2C_W_ERR_MASK\t\\\n\t(XDMA_STAT_H2C_W_DECODE_ERR | XDMA_STAT_H2C_W_SLAVE_ERR)\n\n/* read error: C2H */\n#define XDMA_STAT_C2H_R_DECODE_ERR\t(1UL << 9)\n#define XDMA_STAT_C2H_R_SLAVE_ERR\t(1UL << 10)\n\n#define XDMA_STAT_C2H_R_ERR_MASK\t\\\n\t(XDMA_STAT_C2H_R_DECODE_ERR | XDMA_STAT_C2H_R_SLAVE_ERR)\n\n/* all combined */\n#define XDMA_STAT_H2C_ERR_MASK\t\\\n\t(XDMA_STAT_COMMON_ERR_MASK | XDMA_STAT_DESC_ERR_MASK | \\\n\t XDMA_STAT_H2C_R_ERR_MASK | XDMA_STAT_H2C_W_ERR_MASK) \n\n#define XDMA_STAT_C2H_ERR_MASK\t\\\n\t(XDMA_STAT_COMMON_ERR_MASK | XDMA_STAT_DESC_ERR_MASK | \\\n\t XDMA_STAT_C2H_R_ERR_MASK)\n\n/* bits of the SGDMA descriptor control field */\n#define XDMA_DESC_STOPPED\t(1UL << 0)\n#define XDMA_DESC_COMPLETED\t(1UL << 1)\n#define XDMA_DESC_EOP\t\t(1UL << 4)\n\n#define XDMA_PERF_RUN\t(1UL << 0)\n#define XDMA_PERF_CLEAR\t(1UL << 1)\n#define XDMA_PERF_AUTO\t(1UL << 2)\n\n#define MAGIC_ENGINE\t0xEEEEEEEEUL\n#define MAGIC_DEVICE\t0xDDDDDDDDUL\n\n/* upper 16-bits of engine identifier register */\n#define XDMA_ID_H2C 0x1fc0U\n#define XDMA_ID_C2H 0x1fc1U\n\n/* for C2H AXI-ST mode */\n#define CYCLIC_RX_PAGES_MAX\t256\t\n\n#define LS_BYTE_MASK 0x000000FFUL\n\n#define BLOCK_ID_MASK 0xFFF00000\n#define BLOCK_ID_HEAD 0x1FC00000\n\n#define IRQ_BLOCK_ID 0x1fc20000UL\n#define CONFIG_BLOCK_ID 0x1fc30000UL\n\n#define WB_COUNT_MASK 0x00ffffffUL\n#define WB_ERR_MASK (1UL << 31)\n#define POLL_TIMEOUT_SECONDS 10\n\n#define MAX_USER_IRQ 16\n\n#define MAX_DESC_BUS_ADDR (0xffffffffULL)\n\n#define DESC_MAGIC 0xAD4B0000UL\n\n#define C2H_WB 0x52B4UL\n\n#define MAX_NUM_ENGINES (XDMA_CHANNEL_NUM_MAX * 2)\n#define H2C_CHANNEL_OFFSET 0x1000\n#define SGDMA_OFFSET_FROM_CHANNEL 0x4000\n#define CHANNEL_SPACING 0x100\n#define TARGET_SPACING 0x1000\n\n#define BYPASS_MODE_SPACING 0x0100\n\n/* obtain the 32 most significant (high) bits of a 32-bit or 64-bit address */\n#define PCI_DMA_H(addr) ((addr >> 16) >> 16)\n/* obtain the 32 least significant (low) bits of a 32-bit or 64-bit address */\n#define PCI_DMA_L(addr) (addr & 0xffffffffUL)\n\n#ifndef VM_RESERVED\n\t#define VMEM_FLAGS (VM_IO | VM_DONTEXPAND | VM_DONTDUMP)\n#else\n\t#define VMEM_FLAGS (VM_IO | VM_RESERVED)\n#endif\n\n#ifdef __LIBXDMA_DEBUG__\n#define dbg_io\t\tpr_err\n#define dbg_fops\tpr_err\n#define dbg_perf\tpr_err\n#define dbg_sg\t\tpr_err\n#define dbg_tfr\t\tpr_err\n#define dbg_irq\t\tpr_err\n#define dbg_init\tpr_err\n#define dbg_desc\tpr_err\n#else\n/* disable debugging */\n#define dbg_io(...)\n#define dbg_fops(...)\n#define dbg_perf(...)\n#define dbg_sg(...)\n#define dbg_tfr(...)\n#define dbg_irq(...)\n#define dbg_init(...)\n#define dbg_desc(...)\n#endif\n\n/* SECTION: Enum definitions */\nenum transfer_state {\n\tTRANSFER_STATE_NEW = 0,\n\tTRANSFER_STATE_SUBMITTED,\n\tTRANSFER_STATE_COMPLETED,\n\tTRANSFER_STATE_FAILED,\n\tTRANSFER_STATE_ABORTED\n};\n\nenum shutdown_state {\n\tENGINE_SHUTDOWN_NONE = 0,\t/* No shutdown in progress */\n\tENGINE_SHUTDOWN_REQUEST = 1,\t/* engine requested to shutdown */\n\tENGINE_SHUTDOWN_IDLE = 2\t/* engine has shutdown and is idle */\n};\n\nenum dev_capabilities {\n\tCAP_64BIT_DMA = 2,\n\tCAP_64BIT_DESC = 4,\n\tCAP_ENGINE_WRITE = 8,\n\tCAP_ENGINE_READ = 16\n};\n\n/* SECTION: Structure definitions */\n\nstruct config_regs {\n\tu32 identifier;\n\tu32 reserved_1[4];\n\tu32 msi_enable;\n};\n\n/**\n * SG DMA Controller status and control registers\n *\n * These registers make the control interface for DMA transfers.\n *\n * It sits in End Point (FPGA) memory BAR[0] for 32-bit or BAR[0:1] for 64-bit.\n * It references the first descriptor which exists in Root Complex (PC) memory.\n *\n * @note The registers must be accessed using 32-bit (PCI DWORD) read/writes,\n * and their values are in little-endian byte ordering.\n */\nstruct engine_regs {\n\tu32 identifier;\n\tu32 control;\n\tu32 control_w1s;\n\tu32 control_w1c;\n\tu32 reserved_1[12];\t/* padding */\n\n\tu32 status;\n\tu32 status_rc;\n\tu32 completed_desc_count;\n\tu32 alignments;\n\tu32 reserved_2[14];\t/* padding */\n\n\tu32 poll_mode_wb_lo;\n\tu32 poll_mode_wb_hi;\n\tu32 interrupt_enable_mask;\n\tu32 interrupt_enable_mask_w1s;\n\tu32 interrupt_enable_mask_w1c;\n\tu32 reserved_3[9];\t/* padding */\n\n\tu32 perf_ctrl;\n\tu32 perf_cyc_lo;\n\tu32 perf_cyc_hi;\n\tu32 perf_dat_lo;\n\tu32 perf_dat_hi;\n\tu32 perf_pnd_lo;\n\tu32 perf_pnd_hi;\n} __packed;\n\nstruct engine_sgdma_regs {\n\tu32 identifier;\n\tu32 reserved_1[31];\t/* padding */\n\n\t/* bus address to first descriptor in Root Complex Memory */\n\tu32 first_desc_lo;\n\tu32 first_desc_hi;\n\t/* number of adjacent descriptors at first_desc */\n\tu32 first_desc_adjacent;\n\tu32 credits;\n} __packed;\n\nstruct msix_vec_table_entry {\n\tu32 msi_vec_addr_lo;\n\tu32 msi_vec_addr_hi;\n\tu32 msi_vec_data_lo;\n\tu32 msi_vec_data_hi;\n} __packed;\n\nstruct msix_vec_table {\n\tstruct msix_vec_table_entry entry_list[32];\n} __packed;\n\nstruct interrupt_regs {\n\tu32 identifier;\n\tu32 user_int_enable;\n\tu32 user_int_enable_w1s;\n\tu32 user_int_enable_w1c;\n\tu32 channel_int_enable;\n\tu32 channel_int_enable_w1s;\n\tu32 channel_int_enable_w1c;\n\tu32 reserved_1[9];\t/* padding */\n\n\tu32 user_int_request;\n\tu32 channel_int_request;\n\tu32 user_int_pending;\n\tu32 channel_int_pending;\n\tu32 reserved_2[12];\t/* padding */\n\n\tu32 user_msi_vector[8];\n\tu32 channel_msi_vector[8];\n} __packed;\n\nstruct sgdma_common_regs {\n\tu32 padding[8];\n\tu32 credit_mode_enable;\n\tu32 credit_mode_enable_w1s;\n\tu32 credit_mode_enable_w1c;\n} __packed;\n\n\n/* Structure for polled mode descriptor writeback */\nstruct xdma_poll_wb {\n\tu32 completed_desc_count;\n\tu32 reserved_1[7];\n} __packed;\n\n\n/**\n * Descriptor for a single contiguous memory block transfer.\n *\n * Multiple descriptors are linked by means of the next pointer. An additional\n * extra adjacent number gives the amount of extra contiguous descriptors.\n *\n * The descriptors are in root complex memory, and the bytes in the 32-bit\n * words must be in little-endian byte ordering.\n */\nstruct xdma_desc {\n\tu32 control;\n\tu32 bytes;\t\t/* transfer length in bytes */\n\tu32 src_addr_lo;\t/* source address (low 32-bit) */\n\tu32 src_addr_hi;\t/* source address (high 32-bit) */\n\tu32 dst_addr_lo;\t/* destination address (low 32-bit) */\n\tu32 dst_addr_hi;\t/* destination address (high 32-bit) */\n\t/*\n\t * next descriptor in the single-linked list of descriptors;\n\t * this is the PCIe (bus) address of the next descriptor in the\n\t * root complex memory\n\t */\n\tu32 next_lo;\t\t/* next desc address (low 32-bit) */\n\tu32 next_hi;\t\t/* next desc address (high 32-bit) */\n} __packed;\n\n/* 32 bytes (four 32-bit words) or 64 bytes (eight 32-bit words) */\nstruct xdma_result {\n\tu32 status;\n\tu32 length;\n\tu32 reserved_1[6];\t/* padding */\n} __packed;\n\nstruct sw_desc {\n\tdma_addr_t addr;\n\tunsigned int len;\n};\n\n/* Describes a (SG DMA) single transfer for the engine */\nstruct xdma_transfer {\n\tstruct list_head entry;\t\t/* queue of non-completed transfers */\n\tstruct xdma_desc *desc_virt;\t/* virt addr of the 1st descriptor */\n\tdma_addr_t desc_bus;\t\t/* bus addr of the first descriptor */\n\tint desc_adjacent;\t\t/* adjacent descriptors at desc_bus */\n\tint desc_num;\t\t\t/* number of descriptors in transfer */\n\tenum dma_data_direction dir;\n\twait_queue_head_t wq;\t\t/* wait queue for transfer completion */\n\n\tenum transfer_state state;\t/* state of the transfer */\n\tunsigned int flags;\n#define XFER_FLAG_NEED_UNMAP\t0x1\n\tint cyclic;\t\t\t/* flag if transfer is cyclic */\n\tint last_in_request;\t\t/* flag if last within request */\n\tunsigned int len;\n\tstruct sg_table *sgt;\n};\n\nstruct xdma_request_cb {\n\tstruct sg_table *sgt;\n\tunsigned int total_len;\n\tu64 ep_addr;\n\n\tstruct xdma_transfer xfer;\n\n\tunsigned int sw_desc_idx;\n\tunsigned int sw_desc_cnt;\n\tstruct sw_desc sdesc[0];\n};\n\nstruct xdma_engine {\n\tunsigned long magic;\t/* structure ID for sanity checks */\n\tstruct xdma_dev *xdev;\t/* parent device */\n\tchar name[5];\t\t/* name of this engine */\n\tint version;\t\t/* version of this engine */\n\t//dev_t cdevno;\t\t/* character device major:minor */\n\t//struct cdev cdev;\t/* character device (embedded struct) */\n\n\t/* HW register address offsets */\n\tstruct engine_regs *regs;\t\t/* Control reg BAR offset */\n\tstruct engine_sgdma_regs *sgdma_regs;\t/* SGDAM reg BAR offset */\n\tu32 bypass_offset;\t\t\t/* Bypass mode BAR offset */\n\n\t/* Engine state, configuration and flags */\n\tenum shutdown_state shutdown;\t/* engine shutdown mode */\n\tenum dma_data_direction dir;\n\tint device_open;\t/* flag if engine node open, ST mode only */\n\tint running;\t\t/* flag if the driver started engine */\n\tint non_incr_addr;\t/* flag if non-incremental addressing used */\n\tint streaming;\n\tint addr_align;\t\t/* source/dest alignment in bytes */\n\tint len_granularity;\t/* transfer length multiple */\n\tint addr_bits;\t\t/* HW datapath address width */\n\tint channel;\t\t/* engine indices */\n\tint max_extra_adj;\t/* descriptor prefetch capability */\n\tint desc_dequeued;\t/* num descriptors of completed transfers */\n\tu32 status;\t\t/* last known status of device */\n\tu32 interrupt_enable_mask_value;/* only used for MSIX mode to store per-engine interrupt mask value */\n\n\t/* Transfer list management */\n\tstruct list_head transfer_list;\t/* queue of transfers */\n\n\t/* Members applicable to AXI-ST C2H (cyclic) transfers */\n\tstruct xdma_result *cyclic_result;\n\tdma_addr_t cyclic_result_bus;\t/* bus addr for transfer */\n\tstruct xdma_request_cb *cyclic_req; \n\tstruct sg_table cyclic_sgt; \n\tu8 eop_found; /* used only for cyclic(rx:c2h) */\n\n\tint rx_tail;\t/* follows the HW */\n\tint rx_head;\t/* where the SW reads from */\n\tint rx_overrun;\t/* flag if overrun occured */\n\n\t/* for copy from cyclic buffer to user buffer */\n\tunsigned int user_buffer_index;\n\n\t/* Members associated with polled mode support */\n\tu8 *poll_mode_addr_virt;\t/* virt addr for descriptor writeback */\n\tdma_addr_t poll_mode_bus;\t/* bus addr for descriptor writeback */\n\n\t/* Members associated with interrupt mode support */\n\twait_queue_head_t shutdown_wq;\t/* wait queue for shutdown sync */\n\tspinlock_t lock;\t\t/* protects concurrent access */\n\tint prev_cpu;\t\t\t/* remember CPU# of (last) locker */\n\tint msix_irq_line;\t\t/* MSI-X vector for this engine */\n\tu32 irq_bitmask;\t\t/* IRQ bit mask for this engine */\n\tstruct work_struct work;\t/* Work queue for interrupt handling */\n\n\tspinlock_t desc_lock;\t\t/* protects concurrent access */\n\tdma_addr_t desc_bus;\n\tstruct xdma_desc *desc;\n\n\t/* for performance test support */\n\tstruct xdma_performance_ioctl *xdma_perf;\t/* perf test control */\n\twait_queue_head_t xdma_perf_wq;\t/* Perf test sync */\n};\n\nstruct xdma_user_irq {\n\tstruct xdma_dev *xdev;\t\t/* parent device */\n\tu8 user_idx;\t\t\t/* 0 ~ 15 */\n\tu8 events_irq;\t\t\t/* accumulated IRQs */\n\tspinlock_t events_lock;\t\t/* lock to safely update events_irq */\n\twait_queue_head_t events_wq;\t/* wait queue to sync waiting threads */\n\tirq_handler_t handler;\n\n\tvoid *dev;\t\n};\n\n/* XDMA PCIe device specific book-keeping */\n#define XDEV_FLAG_OFFLINE\t0x1\nstruct xdma_dev {\n\tstruct list_head list_head;\n        struct list_head rcu_node;\n\n\tunsigned long magic;\t\t/* structure ID for sanity checks */\n\tstruct pci_dev *pdev;\t/* pci device struct from probe() */\n\tint idx;\t\t/* dev index */\n\n\tconst char *mod_name;\t\t/* name of module owning the dev */\n\n\tspinlock_t lock;\t\t/* protects concurrent access */\n\tunsigned int flags;\n\n\t/* PCIe BAR management */\n\tvoid *__iomem bar[XDMA_BAR_NUM];\t/* addresses for mapped BARs */\n\tint user_bar_idx;\t/* BAR index of user logic */\n\tint config_bar_idx;\t/* BAR index of XDMA config logic */\n\tint bypass_bar_idx;\t/* BAR index of XDMA bypass logic */\n\tint regions_in_use;\t/* flag if dev was in use during probe() */\n\tint got_regions;\t/* flag if probe() obtained the regions */\n\n\tint user_max;\n\tint c2h_channel_max;\n\tint h2c_channel_max;\n\n\t/* Interrupt management */\n\tint irq_count;\t\t/* interrupt counter */\n\tint irq_line;\t\t/* flag if irq allocated successfully */\n\tint msi_enabled;\t/* flag if msi was enabled for the device */\n\tint msix_enabled;\t/* flag if msi-x was enabled for the device */\n#if LINUX_VERSION_CODE < KERNEL_VERSION(4,12,0)\n\tstruct msix_entry entry[32];\t/* msi-x vector/entry table */\n#endif\n\tstruct xdma_user_irq user_irq[16];\t/* user IRQ management */\n\tunsigned int mask_irq_user;\n\n\t/* XDMA engine management */\n\tint engines_num;\t/* Total engine count */\n\tu32 mask_irq_h2c;\n\tu32 mask_irq_c2h;\n\tstruct xdma_engine engine_h2c[XDMA_CHANNEL_NUM_MAX];\n\tstruct xdma_engine engine_c2h[XDMA_CHANNEL_NUM_MAX];\n\n\t/* SD_Accel specific */\n\tenum dev_capabilities capabilities;\n\tu64 feature_id;\n};\n\nstatic inline int xdma_device_flag_check(struct xdma_dev *xdev, unsigned int f)\n{\n\tunsigned long flags;\n\n\tspin_lock_irqsave(&xdev->lock, flags);\n\tif (xdev->flags & f) {\n\t\tspin_unlock_irqrestore(&xdev->lock, flags);\n\t\treturn 1;\n\t}\n\tspin_unlock_irqrestore(&xdev->lock, flags);\n\treturn 0;\n}\n\nstatic inline int xdma_device_flag_test_n_set(struct xdma_dev *xdev,\n\t\t\t\t\t unsigned int f)\n{\n\tunsigned long flags;\n\tint rv = 0;\n\n\tspin_lock_irqsave(&xdev->lock, flags);\n\tif (xdev->flags & f) {\n\t\tspin_unlock_irqrestore(&xdev->lock, flags);\n\t\trv = 1;\n\t} else\n\t\txdev->flags |= f;\n\tspin_unlock_irqrestore(&xdev->lock, flags);\n\treturn rv;\n}\n\nstatic inline void xdma_device_flag_set(struct xdma_dev *xdev, unsigned int f)\n{\n\tunsigned long flags;\n\n\tspin_lock_irqsave(&xdev->lock, flags);\n\txdev->flags |= f;\n\tspin_unlock_irqrestore(&xdev->lock, flags);\n}\n\nstatic inline void xdma_device_flag_clear(struct xdma_dev *xdev, unsigned int f)\n{\n\tunsigned long flags;\n\n\tspin_lock_irqsave(&xdev->lock, flags);\n\txdev->flags &= ~f;\n\tspin_unlock_irqrestore(&xdev->lock, flags);\n}\n\nvoid write_register(u32 value, void *iomem);\nu32 read_register(void *iomem);\n\nstruct xdma_dev *xdev_find_by_pdev(struct pci_dev *pdev);\n\nvoid xdma_device_offline(struct pci_dev *pdev, void *dev_handle);\nvoid xdma_device_online(struct pci_dev *pdev, void *dev_handle);\n\nint xdma_performance_submit(struct xdma_dev *xdev, struct xdma_engine *engine);\nstruct xdma_transfer *engine_cyclic_stop(struct xdma_engine *engine);\nvoid enable_perf(struct xdma_engine *engine);\nvoid get_perf_stats(struct xdma_engine *engine);\n\nint xdma_cyclic_transfer_setup(struct xdma_engine *engine);\nint xdma_cyclic_transfer_teardown(struct xdma_engine *engine);\nssize_t xdma_engine_read_cyclic(struct xdma_engine *, char __user *, size_t,\n\t\t\t int);\nint engine_addrmode_set(struct xdma_engine *engine, unsigned long arg);\n\n#endif /* XDMA_LIB_H */\n"
  },
  {
    "path": "drivers/awsf1portal/libxdma_api.h",
    "content": "/*******************************************************************************\n *\n * Xilinx XDMA IP Core Linux Driver\n *\n * Copyright(c) Sidebranch.\n * Copyright(c) Xilinx, Inc.\n *\n * Karen Xie <karen.xie@xilinx.com>\n * Leon Woestenberg <leon@sidebranch.com>\n *\n ******************************************************************************/\n\n#ifndef __XDMA_BASE_API_H__\n#define __XDMA_BASE_API_H__\n\n#include <linux/types.h>\n#include <linux/scatterlist.h>\n#include <linux/interrupt.h>\n\n/*\n * functions exported by the xdma driver\n */\n\ntypedef struct {\n\tu64 write_submitted;\n\tu64 write_completed;\n\tu64 read_requested;\n\tu64 read_completed;\n\tu64 restart;\n\tu64 open;\n\tu64 close;\n\tu64 msix_trigger;\n} xdma_statistics;\n\n/*\n * This struct should be constantly updated by XMDA using u64_stats_* APIs\n * The front end will read the structure without locking (That's why updating atomically is a must)\n * every time it prints the statistics.\n */\n//static XDMA_Statistics stats;\n\n/* \n * xdma_device_open - read the pci bars and configure the fpga\n *\tshould be called from probe()\n * \tNOTE:\n *\t\tuser interrupt will not enabled until xdma_user_isr_enable()\n *\t\tis called\n * @pdev: ptr to pci_dev\n * @mod_name: the module name to be used for request_irq\n * @user_max: max # of user/event (interrupts) to be configured\n * @channel_max: max # of c2h and h2c channels to be configured\n * NOTE: if the user/channel provisioned is less than the max specified,\n *\t libxdma will update the user_max/channel_max\n * returns\n *\ta opaque handle (for libxdma to identify the device)\n *\tNULL, in case of error  \n */\nvoid *xdma_device_open(const char *mod_name, struct pci_dev *pdev,\n\t\t int *user_max, int *h2c_channel_max, int *c2h_channel_max);\n\n/* \n * xdma_device_close - prepare fpga for removal: disable all interrupts (users\n * and xdma) and release all resources\n *\tshould called from remove()\n * @pdev: ptr to struct pci_dev\n * @tuples: from xdma_device_open()\n */\nvoid xdma_device_close(struct pci_dev *pdev, void *dev_handle);\n\n/* \n * xdma_device_restart - restart the fpga\n * @pdev: ptr to struct pci_dev\n * TODO:\n *\tmay need more refining on the parameter list\n * return < 0 in case of error\n * TODO: exact error code will be defined later\n */\nint xdma_device_restart(struct pci_dev *pdev, void *dev_handle);\n\n/*\n * xdma_user_isr_register - register a user ISR handler\n * It is expected that the xdma will register the ISR, and for the user\n * interrupt, it will call the corresponding handle if it is registered and\n * enabled.\n *\n * @pdev: ptr to the the pci_dev struct\t\n * @mask: bitmask of user interrupts (0 ~ 15)to be registered\n *\t\tbit 0: user interrupt 0\n *\t\t...\n *\t\tbit 15: user interrupt 15\n *\t\tany bit above bit 15 will be ignored.\n * @handler: the correspoinding handler\n *\t\ta NULL handler will be treated as de-registeration\n * @name: to be passed to the handler, ignored if handler is NULL`\n * @dev: to be passed to the handler, ignored if handler is NULL`\n * return < 0 in case of error\n * TODO: exact error code will be defined later\n */\nint xdma_user_isr_register(void *dev_hndl, unsigned int mask,\n\t\t\t irq_handler_t handler, void *dev);\n\n/*\n * xdma_user_isr_enable/disable - enable or disable user interrupt\n * @pdev: ptr to the the pci_dev struct\t\n * @mask: bitmask of user interrupts (0 ~ 15)to be registered\n * return < 0 in case of error\n * TODO: exact error code will be defined later\n */\nint xdma_user_isr_enable(void *dev_hndl, unsigned int mask);\nint xdma_user_isr_disable(void *dev_hndl, unsigned int mask);\n\n/*\n * xdma_xfer_submit - submit data for dma operation (for both read and write)\n *\tThis is a blocking call\n * @channel: channle number (< channel_max)\n *\t== channel_max means libxdma can pick any channel available:q\n\n * @dir: DMA_FROM/TO_DEVICE\n * @offset: offset into the DDR/BRAM memory to read from or write to\n * @sg_tbl: the scatter-gather list of data buffers\n * @timeout: timeout in mili-seconds, *currently ignored\n * return # of bytes transfered or\n *\t < 0 in case of error\n * TODO: exact error code will be defined later\n */\nssize_t xdma_xfer_submit(void *dev_hndl, int channel, bool write, u64 ep_addr,\n\t\t\tstruct sg_table *sgt, bool dma_mapped, int timeout_ms);\n\t\t\t\n\n/////////////////////missing API////////////////////\n\n//xdma_get_channle_state - if no interrupt on DMA hang is available\n//xdma_channle_restart\n\n#endif\n"
  },
  {
    "path": "drivers/awsf1portal/linux/dma-buf.h",
    "content": "/*\n * Header file for dma buffer sharing framework.\n *\n * Copyright(C) 2011 Linaro Limited. All rights reserved.\n * Author: Sumit Semwal <sumit.semwal@ti.com>\n *\n * Many thanks to linaro-mm-sig list, and specially\n * Arnd Bergmann <arnd@arndb.de>, Rob Clark <rob@ti.com> and\n * Daniel Vetter <daniel@ffwll.ch> for their support in creation and\n * refining of this idea.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of the GNU General Public License version 2 as published by\n * the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\n * more details.\n *\n * You should have received a copy of the GNU General Public License along with\n * this program.  If not, see <http://www.gnu.org/licenses/>.\n */\n#ifndef __DMA_BUF_H__\n#define __DMA_BUF_H__\n\n#include <linux/file.h>\n#include <linux/err.h>\n#include <linux/scatterlist.h>\n#include <linux/list.h>\n#include <linux/dma-mapping.h>\n#include <linux/fs.h>\n\nstruct device;\nstruct dma_buf;\nstruct dma_buf_attachment;\n\n/**\n * struct dma_buf_ops - operations possible on struct dma_buf\n * @attach: [optional] allows different devices to 'attach' themselves to the\n *\t    given buffer. It might return -EBUSY to signal that backing storage\n *\t    is already allocated and incompatible with the requirements\n *\t    of requesting device.\n * @detach: [optional] detach a given device from this buffer.\n * @map_dma_buf: returns list of scatter pages allocated, increases usecount\n *\t\t of the buffer. Requires atleast one attach to be called\n *\t\t before. Returned sg list should already be mapped into\n *\t\t _device_ address space. This call may sleep. May also return\n *\t\t -EINTR. Should return -EINVAL if attach hasn't been called yet.\n * @unmap_dma_buf: decreases usecount of buffer, might deallocate scatter\n *\t\t   pages.\n * @release: release this buffer; to be called after the last dma_buf_put.\n * @begin_cpu_access: [optional] called before cpu access to invalidate cpu\n * \t\t      caches and allocate backing storage (if not yet done)\n * \t\t      respectively pin the objet into memory.\n * @end_cpu_access: [optional] called after cpu access to flush caches.\n * @kmap_atomic: maps a page from the buffer into kernel address\n * \t\t space, users may not block until the subsequent unmap call.\n * \t\t This callback must not sleep.\n * @kunmap_atomic: [optional] unmaps a atomically mapped page from the buffer.\n * \t\t   This Callback must not sleep.\n * @kmap: maps a page from the buffer into kernel address space.\n * @kunmap: [optional] unmaps a page from the buffer.\n * @mmap: used to expose the backing storage to userspace. Note that the\n * \t  mapping needs to be coherent - if the exporter doesn't directly\n * \t  support this, it needs to fake coherency by shooting down any ptes\n * \t  when transitioning away from the cpu domain.\n * @vmap: [optional] creates a virtual mapping for the buffer into kernel\n *\t  address space. Same restrictions as for vmap and friends apply.\n * @vunmap: [optional] unmaps a vmap from the buffer\n */\nstruct dma_buf_ops {\n\tint (*attach)(struct dma_buf *, struct device *,\n\t\t\tstruct dma_buf_attachment *);\n\n\tvoid (*detach)(struct dma_buf *, struct dma_buf_attachment *);\n\n\t/* For {map,unmap}_dma_buf below, any specific buffer attributes\n\t * required should get added to device_dma_parameters accessible\n\t * via dev->dma_params.\n\t */\n\tstruct sg_table * (*map_dma_buf)(struct dma_buf_attachment *,\n\t\t\t\t\t\tenum dma_data_direction);\n\tvoid (*unmap_dma_buf)(struct dma_buf_attachment *,\n\t\t\t\t\t\tstruct sg_table *,\n\t\t\t\t\t\tenum dma_data_direction);\n\t/* TODO: Add try_map_dma_buf version, to return immed with -EBUSY\n\t * if the call would block.\n\t */\n\n\t/* after final dma_buf_put() */\n\tvoid (*release)(struct dma_buf *);\n\n\tint (*begin_cpu_access)(struct dma_buf *, size_t, size_t,\n\t\t\t\tenum dma_data_direction);\n\tvoid (*end_cpu_access)(struct dma_buf *, size_t, size_t,\n\t\t\t       enum dma_data_direction);\n\tvoid *(*kmap_atomic)(struct dma_buf *, unsigned long);\n\tvoid (*kunmap_atomic)(struct dma_buf *, unsigned long, void *);\n\tvoid *(*kmap)(struct dma_buf *, unsigned long);\n\tvoid (*kunmap)(struct dma_buf *, unsigned long, void *);\n\n\tint (*mmap)(struct dma_buf *, struct vm_area_struct *vma);\n\n\tvoid *(*vmap)(struct dma_buf *);\n\tvoid (*vunmap)(struct dma_buf *, void *vaddr);\n};\n\n/**\n * struct dma_buf - shared buffer object\n * @size: size of the buffer\n * @file: file pointer used for sharing buffers across, and for refcounting.\n * @attachments: list of dma_buf_attachment that denotes all devices attached.\n * @ops: dma_buf_ops associated with this buffer object.\n * @priv: exporter specific private data for this buffer object.\n */\nstruct dma_buf {\n\tsize_t size;\n\tstruct file *file;\n\tstruct list_head attachments;\n\tconst struct dma_buf_ops *ops;\n\t/* mutex to serialize list manipulation, attach/detach and vmap/unmap */\n\tstruct mutex lock;\n\tunsigned vmapping_counter;\n\tvoid *vmap_ptr;\n\tvoid *priv;\n};\n\n/**\n * struct dma_buf_attachment - holds device-buffer attachment data\n * @dmabuf: buffer for this attachment.\n * @dev: device attached to the buffer.\n * @node: list of dma_buf_attachment.\n * @priv: exporter specific attachment data.\n *\n * This structure holds the attachment information between the dma_buf buffer\n * and its user device(s). The list contains one attachment struct per device\n * attached to the buffer.\n */\nstruct dma_buf_attachment {\n\tstruct dma_buf *dmabuf;\n\tstruct device *dev;\n\tstruct list_head node;\n\tvoid *priv;\n};\n\n/**\n * get_dma_buf - convenience wrapper for get_file.\n * @dmabuf:\t[in]\tpointer to dma_buf\n *\n * Increments the reference count on the dma-buf, needed in case of drivers\n * that either need to create additional references to the dmabuf on the\n * kernel side.  For example, an exporter that needs to keep a dmabuf ptr\n * so that subsequent exports don't create a new dmabuf.\n */\nstatic inline void get_dma_buf(struct dma_buf *dmabuf)\n{\n\tget_file(dmabuf->file);\n}\n\nstruct dma_buf_attachment *dma_buf_attach(struct dma_buf *dmabuf,\n\t\t\t\t\t\t\tstruct device *dev);\nvoid dma_buf_detach(struct dma_buf *dmabuf,\n\t\t\t\tstruct dma_buf_attachment *dmabuf_attach);\nstruct dma_buf *dma_buf_export(void *priv, const struct dma_buf_ops *ops,\n\t\t\t       size_t size, int flags);\nint dma_buf_fd(struct dma_buf *dmabuf, int flags);\nstruct dma_buf *dma_buf_get(int fd);\nvoid dma_buf_put(struct dma_buf *dmabuf);\n\nstruct sg_table *dma_buf_map_attachment(struct dma_buf_attachment *,\n\t\t\t\t\tenum dma_data_direction);\nvoid dma_buf_unmap_attachment(struct dma_buf_attachment *, struct sg_table *,\n\t\t\t\tenum dma_data_direction);\nint dma_buf_begin_cpu_access(struct dma_buf *dma_buf, size_t start, size_t len,\n\t\t\t     enum dma_data_direction dir);\nvoid dma_buf_end_cpu_access(struct dma_buf *dma_buf, size_t start, size_t len,\n\t\t\t    enum dma_data_direction dir);\nvoid *dma_buf_kmap_atomic(struct dma_buf *, unsigned long);\nvoid dma_buf_kunmap_atomic(struct dma_buf *, unsigned long, void *);\nvoid *dma_buf_kmap(struct dma_buf *, unsigned long);\nvoid dma_buf_kunmap(struct dma_buf *, unsigned long, void *);\n\nint dma_buf_mmap(struct dma_buf *, struct vm_area_struct *,\n\t\t unsigned long);\nvoid *dma_buf_vmap(struct dma_buf *);\nvoid dma_buf_vunmap(struct dma_buf *, void *vaddr);\n\n#endif /* __DMA_BUF_H__ */\n"
  },
  {
    "path": "drivers/awsf1portal/pcieportal.h",
    "content": "/* Copyright (c) 2014 Quanta Research Cambridge, Inc\n *\n * Permission is hereby granted, free of charge, to any person obtaining a\n * copy of this software and associated documentation files (the \"Software\"),\n * to deal in the Software without restriction, including without limitation\n * the rights to use, copy, modify, merge, publish, distribute, sublicense,\n * and/or sell copies of the Software, and to permit persons to whom the\n * Software is furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n * DEALINGS IN THE SOFTWARE.\n */\n#ifndef __PCIEPORTAL_H__\n#define __PCIEPORTAL_H__\n\n#include <linux/ioctl.h>\n\n/*\n * IOCTLs\n */\n\n/* magic number for IOCTLs */\n#define BNOC_IOC_MAGIC 0xB5\n\n/* Number of boards to support */\n#define NUM_BOARDS 4\n#define MAX_NUM_PORTALS 32\n\n/* Structures used with IOCTLs */\n\ntypedef struct {\n  unsigned long base;\n  unsigned int trace;\n  unsigned int traceLength;\n  unsigned int intval[MAX_NUM_PORTALS];\n  unsigned int name[MAX_NUM_PORTALS];\n} tTraceInfo;\n\ntypedef struct {\n  int fd;\n  int id;\n} tSendFd;\n\ntypedef struct {\n    int  index;        /* in param */\n    char md5[33];      /* out param -- asciz */\n    char filename[33]; /* out param -- asciz */\n} PortalSignaturePcie;\n\ntypedef unsigned int tTlpData[6];\n\ntypedef struct ChangeEntry {\n  unsigned int timestamp;\n  unsigned char src;\n  unsigned int value : 24;\n} tChangeEntry;\n/* IOCTL code definitions */\n\n#define BNOC_GET_TLP         _IOR(BNOC_IOC_MAGIC,7,tTlpData*)\n#define BNOC_TRACE           _IOWR(BNOC_IOC_MAGIC,8,tTraceInfo*)\n#define BNOC_ENABLE_TRACE    _IOR(BNOC_IOC_MAGIC,8,int*)\n#define PCIE_SEND_FD         _IOR(BNOC_IOC_MAGIC,12,tSendFd*)\n#define PCIE_DEREFERENCE     _IOR(BNOC_IOC_MAGIC,13,int)\n#define PCIE_SIGNATURE       _IOR(BNOC_IOC_MAGIC,14,PortalSignaturePcie)\n#define PCIE_CHANGE_ENTRY    _IOR(BNOC_IOC_MAGIC,15,tChangeEntry*)\n\n#endif // __PCIEPORTAL_H__\n"
  },
  {
    "path": "drivers/awsf1portal/portal.c",
    "content": "/* Copyright (c) 2014 Quanta Research Cambridge, Inc\n *\n * Permission is hereby granted, free of charge, to any person obtaining a\n * copy of this software and associated documentation files (the \"Software\"),\n * to deal in the Software without restriction, including without limitation\n * the rights to use, copy, modify, merge, publish, distribute, sublicense,\n * and/or sell copies of the Software, and to permit persons to whom the\n * Software is furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n * DEALINGS IN THE SOFTWARE.\n */\n/*\n * Linux device driver for CONNECTAL portals on FPGAs connected via PCIe.\n */\n\n#include <linux/kernel.h>\n#include <linux/module.h>\n#include <linux/version.h>      /* LINUX_VERSION_CODE, KERNEL_VERSION */\n#include <linux/pci.h>          /* pci device types, fns, etc. */\n#include <linux/errno.h>        /* error codes */\n#include <linux/io.h>           /* I/O mapping, reading, writing */\n#include <linux/cdev.h>         /* struct cdev */\n#include <linux/fs.h>           /* struct file_operations */\n#include <linux/init.h>         /* __init, __exit, etc. */\n#include <linux/ioctl.h>        /* ioctl macros */\n#include <linux/interrupt.h>    /* request_irq, free_irq, etc. */\n#include <linux/mm.h>           /* kmalloc, kfree, struct page, etc. */\n#include <linux/sched.h>        /* task_struct */\n#include <linux/scatterlist.h>  /* sg_* operations */\n#include <linux/mutex.h>        /* mutex_lock, mutex_unlock, etc. */\n#include <linux/poll.h>         /* poll_table, etc. */\n#include <asm/uaccess.h>        /* copy_to_user, copy_from_user */\n#include <linux/dma-buf.h>\n#include \"driverversion.h\"\n\n#include \"libxdma.h\"\n#include \"xdma_mod.h\"\n\n#include \"pcieportal.h\"\n#include \"portal_internal.h\"\n#define CONNECTAL_DRIVER_CODE\n#include \"portal.h\" // PORTAL_BASE_OFFSET\n#include \"dmaSendFd.h\"\n#include \"portalKernel.h\"\n\n/* stem used for module and device names */\n#define DEV_NAME \"portal\"\n\n#define BLUESPEC_VENDOR_ID 0x1be7\n#define AMAZON_VENDOR_ID   0x1d0f\n\n#define CONNECTAL_DEVICE_ID 0xc100\n#define AMAZON_DEVICE_ID 0xf000\n\n/* CSR address space offsets */\n#define CSR_ID                        (   0 << 2) /* 64-bit */\n#define CSR_TLPDATAFIFO_DEQ           ( 768 << 2)\n#define CSR_TLPTRACELENGTHREG         ( 774 << 2)\n#define CSR_TLPTRACINGREG             ( 775 << 2)\n#define CSR_TLPDATABRAMRESPONSESLICE0 ( 776 << 2)\n#define CSR_TLPDATABRAMRESPONSESLICE1 ( 777 << 2)\n#define CSR_TLPDATABRAMRESPONSESLICE2 ( 778 << 2)\n#define CSR_TLPDATABRAMRESPONSESLICE3 ( 779 << 2)\n#define CSR_TLPDATABRAMRESPONSESLICE4 ( 780 << 2)\n#define CSR_TLPDATABRAMRESPONSESLICE5 ( 781 << 2)\n#define CSR_TLPPCIEWRADDRREG          ( 792 << 2)\n#define CSR_CHANGELO                  ( 801 << 2)\n#define CSR_CHANGEHI                  ( 802 << 2)\n\n/* MSIX must be in separate 4kb page */\n#define CSR_MSIX_ADDR_LO              (1024 << 2)\n#define CSR_MSIX_ADDR_HI              (1025 << 2)\n#define CSR_MSIX_MSG_DATA             (1026 << 2)\n#define CSR_MSIX_MASKED               (1027 << 2)\n\n#define PCR_IID_OFFSET 0x010\n#define PCR_NUM_TILES_OFFSET 0x008\n#define PCR_NUM_PORTALS_OFFSET 0x014\n#define MAX_MSIX_ENTRIES 16\n#define MAX_MINOR_COUNT (NUM_BOARDS * MAX_NUM_PORTALS)\n\n/* static device data */\nstatic dev_t device_number;\nstatic char portalp[MAX_MINOR_COUNT]; // free map of minor numbers\nstatic struct class *pcieportal_class = NULL;\nstatic unsigned long long expected_magic = 'B' | ((unsigned long long) 'l' << 8)\n    | ((unsigned long long) 'u' << 16) | ((unsigned long long) 'e' << 24)\n    | ((unsigned long long) 's' << 32) | ((unsigned long long) 'p' << 40)\n    | ((unsigned long long) 'e' << 48) | ((unsigned long long) 'c' << 56);\n\n/*\n * interrupt handler\n */\nstatic irqreturn_t intr_handler(int irq, void *p)\n{\n\ttTile *this_tile = p;\n        tBoard *this_board = this_tile->board;\n        int i;\n        //printk(KERN_INFO \"%s_%d: interrupt %d!\\n\", DEV_NAME, this_tile->device_tile-1, irq);\n        for (i = 0; i < MAX_NUM_PORTALS; i++) {\n                if ((this_tile->device_tile-1 == this_board->portal[i].device_tile)\n                    || this_tile->board->info.aws_shell) {\n\t\t\twake_up_interruptible(&(this_board->portal[i].wait_queue));\n                }\n        }\n        return IRQ_HANDLED;\n}\n\n/*\n * driver file operations\n */\n\n/* open the device file */\nstatic int pcieportal_open(struct inode *inode, struct file *filp)\n{\n        int err = 0;\n        tPortal *this_portal = (tPortal *)inode->i_cdev;\n\n        if (!this_portal) {\n                printk(\"pcieportal_open: basedevice_number=%x /dev/connectal\\n\", device_number);\n        }\n        else {\n                printk(\"pcieportal_open: basedevice_number=%x tile=%d name=%d\\n\",\n                       device_number, this_portal->device_tile, this_portal->device_name);\n//printk(\"[%s:%d] inode %p filp %p portal %p priv %p privp %p extra %p\\n\", __FUNCTION__, __LINE__, inode, filp, this_portal, filp->private_data, privp, this_portal->extra);\n                init_waitqueue_head(&(this_portal->wait_queue));\n                /* increment the open file count */\n                this_portal->board->open_count += 1; \n        }\n        filp->private_data = (void *) this_portal;\n        // FIXME: why does the kernel think this device is RDONLY?\n        filp->f_mode |= FMODE_WRITE;\n\n        return err;\n}\n\n/* close the device file */\nstatic int pcieportal_release(struct inode *inode, struct file *filp)\n{\n        tPortal *this_portal = (tPortal *) filp->private_data;\n        if (this_portal) {\n        struct list_head *pmlist;\n        PortalInternal devptr = {.map_base = this_portal->regs, .transport = &kernelfunc};\n\n        /* decrement the open file count */\n        init_waitqueue_head(&(this_portal->wait_queue));\n        this_portal->board->open_count -= 1;\n        printk(\"%s_%d_%d: Closed device file\\n\", DEV_NAME, this_portal->device_tile, this_portal->device_name);\n        list_for_each(pmlist, &this_portal->pmlist) {\n                struct pmentry *pmentry = list_entry(pmlist, struct pmentry, pmlist);\n                printk(\"    returning id=%d fmem=%p\\n\", pmentry->id, pmentry->fmem);\n                MMURequest_idReturn(&devptr, pmentry->id);\n                fput(pmentry->fmem);\n                kfree(pmentry);\n        }\n        INIT_LIST_HEAD(&this_portal->pmlist);\n        }\n        return 0;                /* success */\n}\n\n/* poll operation to predict blocking of reads & writes */\nstatic unsigned int pcieportal_poll(struct file *filp, poll_table *poll_table)\n{\n        tPortal *this_portal = (tPortal *) filp->private_data;\n        unsigned int mask = 0;\n        uint32_t status = 0;\n\n        //printk(KERN_INFO \"%s_%d_%d: poll function called\\n\", DEV_NAME, this_portal->device_tile, this_portal->device_name);\n        poll_wait(filp, &this_portal->wait_queue, poll_table);\n        if (this_portal->regs) {\n            status = *this_portal->regs;\n        }\n        if (status)\n            mask |= POLLIN  | POLLRDNORM; /* readable */\n        //mask |= POLLOUT | POLLWRNORM; /* writable */\n        //printk(KERN_INFO \"%s_%d_%d: poll return status is %x\\n\", DEV_NAME, this_portal->device_tile, this_portal->device_name, mask);\n        return mask;\n}\n\n/*\n * driver IOCTL operations\n */\n\nstatic long pcieportal_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)\n{\n        int err = 0;\n        tPortal *this_portal = (tPortal *) filp->private_data;\n        tBoard *this_board = NULL;\n        //tBoardInfo info;\n\n        if (this_portal)\n            this_board = this_portal->board;\n        /* basic sanity checks */\n        if (_IOC_DIR(cmd) & _IOC_READ) {\n#if (LINUX_VERSION_CODE < KERNEL_VERSION(5,0,0)) && !(defined(RHEL_MAJOR) && RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(8,0))\n                err = !access_ok(VERIFY_WRITE, (void __user *) arg, _IOC_SIZE(cmd));\n#else\n                err = !access_ok((void __user *) arg, _IOC_SIZE(cmd));\n#endif\n        } else if (_IOC_DIR(cmd) & _IOC_WRITE) {\n#if (LINUX_VERSION_CODE < KERNEL_VERSION(5,0,0)) && !(defined(RHEL_MAJOR) && RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(8,0))\n                err = !access_ok(VERIFY_WRITE, (void __user *) arg, _IOC_SIZE(cmd));\n#else\n                err = !access_ok((void __user *) arg, _IOC_SIZE(cmd));\n#endif\n        }\n        if (!err)\n        switch (cmd) {\n        case PCIE_SEND_FD:\n                {\n                /* pushd down allocated fd */\n                tSendFd sendFd;\n                struct pmentry *pmentry;\n                PortalInternal devptr = {.map_base = this_portal->regs, .transport = &kernelfunc};\n\n                err = copy_from_user(&sendFd, (void __user *) arg, sizeof(sendFd));\n                if (err)\n                    break;\n                pmentry = (struct pmentry *)kzalloc(sizeof(struct pmentry), GFP_KERNEL);\n                INIT_LIST_HEAD(&pmentry->pmlist);\n                pmentry->fmem = fget(sendFd.fd);\n                pmentry->id   = sendFd.id;\n                printk(\"[%s:%d] PCIE_SEND_FD fd=%x id=%x fmem=%p  **\\n\", __FUNCTION__, __LINE__, sendFd.fd, sendFd.id, pmentry->fmem);\n                list_add(&pmentry->pmlist, &this_portal->pmlist);\n                err = send_fd_to_portal(&devptr, sendFd.fd, sendFd.id, 0);\n                if (err < 0)\n                    break;\n                err = 0;\n                }\n                break;\n        case PCIE_DEREFERENCE: {\n                int id = arg;\n                struct list_head *pmlist, *n;\n                PortalInternal devptr = {.map_base = this_portal->regs, .transport = &kernelfunc};\n                err = -ENOENT;\n                MMURequest_idReturn(&devptr, id);\n                list_for_each_safe(pmlist, n, &this_portal->pmlist) {\n                        struct pmentry *pmentry = list_entry(pmlist, struct pmentry, pmlist);\n                        if (pmentry->id == id) {\n                                printk(\"%s:%d releasing portalmem id=%d fmem=%p count=%ld\\n\", __FUNCTION__, __LINE__, id, pmentry->fmem, (unsigned long)pmentry->fmem->f_count.counter);\n                                fput(pmentry->fmem);\n                                list_del(&pmentry->pmlist);\n                                kfree(pmentry);\n                                err = 0;\n                                break;\n                        }\n                }\n        } break;\n        default:\n                return -ENOTTY;\n        }\n        if (err)\n                return -EFAULT;\n        return 0;\n}\n\nstatic int portal_mmap(struct file *filp, struct vm_area_struct *vma)\n{\n        tPortal *this_portal = (tPortal *) filp->private_data;\n        struct pci_dev *pci_dev = this_portal->board->pci_dev;\n        off_t off;\n\n        if (vma->vm_pgoff > (~0UL >> PAGE_SHIFT))\n                return -EINVAL;\n        if (vma->vm_pgoff < 16) {\n                if (this_portal->board->info.aws_shell) {\n                        off = pci_dev->resource[0].start + this_portal->offset;\n                } else {\n                        off = pci_dev->resource[2].start + this_portal->offset;\n                }\n                printk(\"portal_mmap portal_number=%d board_start=%012lx portal_start=%012lx\\n\",\n                     this_portal->portal_number, (long) pci_dev->resource[2].start, off);\n                vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);\n                vma->vm_pgoff = off >> PAGE_SHIFT;\n                //vma->vm_flags |= VM_IO | VM_RESERVED;\n        } else {\n                if (!this_portal->virt) {\n                        this_portal->virt = dma_alloc_coherent(&pci_dev->dev,\n                             vma->vm_end - vma->vm_start, &this_portal->dma_handle, GFP_ATOMIC);\n                        //this_portal->virt =pci_alloc_consistent(pci_dev, PORTAL_BASE_OFFSET, &this_portal->extra->dma_handle);\n                        printk(\"dma_alloc_coherent virt=%p dma_handle=%p\\n\",\n                             this_portal->virt, (void *) this_portal->dma_handle);\n                }\n                //vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);\n                off = this_portal->dma_handle;\n        }\n        vma->vm_flags |= VM_IO;\n        if (io_remap_pfn_range(vma, vma->vm_start, off >> PAGE_SHIFT,\n             vma->vm_end - vma->vm_start, vma->vm_page_prot))\n                return -EAGAIN;\n\n        return 0;\n}\n\nstatic ssize_t pcieportal_read(struct file *filp,\n      char *buffer, size_t length, loff_t *offset)\n{\n        return 0;\n}\n\n/* file operations pointers */\nstatic const struct file_operations pcieportal_fops = {\n        .owner = THIS_MODULE,\n        .open = pcieportal_open,\n        .read   = pcieportal_read,\n        .release = pcieportal_release,\n        .poll = pcieportal_poll,\n        .unlocked_ioctl = pcieportal_ioctl,\n        .compat_ioctl = pcieportal_ioctl,\n        .mmap = portal_mmap\n};\n\nstatic int connectal_open(struct inode *inode, struct file *filp)\n{\n        int err = 0;\n        tBoard *this_board = container_of(inode->i_cdev,  tBoard, cdev);\n\n\tprintk(\"%s: basedevice_number=%x /dev/connectal\\n\", __FUNCTION__, device_number);\n        filp->private_data = (void *) this_board;\n\n        return err;\n}\n\nstatic ssize_t connectal_read(struct file *filp,\n      char *buffer, size_t length, loff_t *offset)\n{\n        return 0;\n}\n\nstatic const struct file_operations connectal_fops = {\n        .owner = THIS_MODULE,\n        .open = connectal_open,\n        .read   = connectal_read\n};\n\n\nstatic int pcieportal_dma_pcis_open(struct inode *inode, struct file *filp)\n{\n\ttBoard *this_board = container_of(inode->i_cdev, tBoard, dma_pcis_cdev);\n        int err = 0;\n\n        printk(\"pcieportal_dma_pcis_open this_board %lx\\n\", (long)this_board);\n        filp->private_data = (void *) this_board;\n        // FIXME: why does the kernel think this device is RDONLY?\n        filp->f_mode |= FMODE_WRITE;\n\n        return err;\n}\n\n/* close the device file */\nstatic int pcieportal_dma_pcis_release(struct inode *inode, struct file *filp)\n{\n        // do we need to unmap?\n\n        return 0;                /* success */\n}\n\nstatic int portal_dma_pcis_mmap(struct file *filp, struct vm_area_struct *vma)\n{\n        tBoard *this_board = (tBoard *) filp->private_data;\n        struct pci_dev *pci_dev = this_board->pci_dev;\n        off_t off = 0;\n\n        printk(\"%s: this_board %08lx\\n\", __FUNCTION__, (long)this_board);\n        if (vma->vm_pgoff > (~0UL >> PAGE_SHIFT))\n                return -EINVAL;\n\n        if (this_board->info.aws_shell) {\n                off = pci_dev->resource[4].start;\n        } else {\n                printk(\"portal_dma_pcis only supported on AWS F1\\n\");\n                return -EINVAL;\n        }\n        printk(\"portal_dma_pcis_mmap board_start=%012lx\",\n               (long) pci_dev->resource[4].start);\n        vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);\n        vma->vm_pgoff = off >> PAGE_SHIFT;\n        //vma->vm_flags |= VM_IO | VM_RESERVED;\n\n        vma->vm_flags |= VM_IO;\n        if (io_remap_pfn_range(vma, vma->vm_start, off >> PAGE_SHIFT,\n                               vma->vm_end - vma->vm_start, vma->vm_page_prot))\n                return -EAGAIN;\n\n        return 0;\n}\n\nstatic const struct file_operations pcieportal_dma_pcis_fops = {\n        .owner = THIS_MODULE,\n        .open = pcieportal_dma_pcis_open,\n        .read   = pcieportal_read,\n        .release = pcieportal_dma_pcis_release,\n        .mmap = portal_dma_pcis_mmap\n};\n\n#ifdef PCIEPORTAL_TUNE_CAPS\nstatic void tune_pcie_caps(struct pci_dev *dev)\n{\n        struct pci_dev *parent;\n        u16 rc_mpss, rc_mps, ep_mpss, ep_mps;\n        u16 rc_mrrs, ep_mrrs, max_mrrs;\n\n        printk(\"%s: %s:%d\\n\", DEV_NAME, __FUNCTION__, __LINE__);\n        parent = dev->bus->self;\n        // why does parent have to be root?\n        if (!pci_is_root_bus(parent->bus)) {\n                printk(\"%s: parent is not root\\n\", DEV_NAME);\n                return;\n        }\n\n        /* max payload size adjustment */\n        rc_mpss = parent->pcie_mpss;\n        rc_mps  = ffs(pcie_get_mps(parent)) - 8;\n\n        ep_mpss = dev->pcie_mpss;\n        ep_mps  = ffs(pcie_get_mps(dev))    - 8;\n\n        rc_mpss = max(rc_mpss, ep_mpss);\n        if (rc_mpss > rc_mps) {\n                rc_mps = rc_mpss;\n                pcie_set_mps(parent, 128 << rc_mps);\n        }\n        if (rc_mpss > ep_mps) {\n                ep_mps = rc_mpss;\n                pcie_set_mps(dev, 128 << ep_mps);\n        }\n\n        printk(\"%s: %s:%d parent.mps=%d dev.mps=%d\\n\", DEV_NAME, __FUNCTION__, __LINE__, pcie_get_mps(parent), pcie_get_mps(dev));\n\n        /* max read request size, limited to 4096 by PCIe spec */\n        max_mrrs = 128 << 5;\n        rc_mrrs = pcie_get_readrq(parent);\n        ep_mrrs = pcie_get_readrq(dev);\n\n        if (max_mrrs > rc_mrrs) {\n                rc_mrrs = max_mrrs;\n                pcie_set_readrq(parent, rc_mrrs);\n        }\n        if (max_mrrs > ep_mrrs) {\n                ep_mrrs = max_mrrs;\n                pcie_set_readrq(dev, ep_mrrs);\n        }\n\n        printk(\"%s: %s:%d parent.readrq=%d dev.readrq=%d\\n\", DEV_NAME, __FUNCTION__, __LINE__, pcie_get_readrq(parent), pcie_get_readrq(dev));\n\n}\n#endif // PCIEPORTAL_TUNE_CAPS\n\nint pcieportal_board_activate(int activate, tBoard *this_board, struct xdma_pci_dev *xpdev, struct pci_dev *dev)\n{\n        int i;\n        int err = 0;\n        unsigned long long magic_num;\n#if 0\n        int rc;\n        int num_entries = MAX_MSIX_ENTRIES;\n        struct msix_entry msix_entries[MAX_MSIX_ENTRIES];\n#endif\n        int fpn = 0;\n        int num_tiles, tile_index;\n        void __iomem *ptile;\n        int board_number = this_board->info.board_number;\n\n        if (!device_number) {\n                pcieportal_class = class_create(THIS_MODULE, \"Connectal\");\n                if (IS_ERR(pcieportal_class)) {\n                        printk(KERN_ERR \"%s: failed to create class Connectal\\n\", DEV_NAME);\n                        return PTR_ERR(pcieportal_class);\n                }\n                /* dynamically allocate a device number */\n                if (alloc_chrdev_region(&device_number, 1, MAX_MINOR_COUNT + 1, DEV_NAME) < 0) {\n                        printk(KERN_ERR \"%s: failed to allocate character device region\\n\", DEV_NAME);\n                        class_destroy(pcieportal_class);\n                        return -1;\n                }\n        }\n        printk(\"this_board %08lx\\n\", (long)this_board);\n        if (activate && this_board->extra == 0) {\n                for (i = 0; i < MAX_NUM_PORTALS; i++) {\n                        INIT_LIST_HEAD(&this_board->portal[i].pmlist);\n                }\n        }\n\n        printk(\"[%s:%d]\\n\", __FUNCTION__, __LINE__);\n        if (activate) {\n                dev_t this_device_number;\n                void *portal_base = 0;\n                for (i = 0; i < MAX_NUM_PORTALS; i++)\n                        this_board->portal[i].device_name = -1;\n                for (i = 0; i < MAX_NUM_PORTALS; i++)\n                        init_waitqueue_head(&(this_board->portal[i].wait_queue));\n                this_board->pci_dev = dev;\n                /* enable the PCI device */\n                if (pci_enable_device(dev)) {\n                        printk(KERN_ERR \"%s: failed to enable %s\\n\", DEV_NAME, pci_name(dev));\n                        err = -EFAULT;\n                        goto err_exit;\n                }\n                /* reserve PCI memory regions */\n                for (i = 0; i < 5; i++)\n                        printk(\"pci bar %d start=%08lx end=%08lx flags=%lx\\n\", i,\n                               (unsigned long) dev->resource[i].start,\n                               (unsigned long) dev->resource[i].end,\n                               dev->resource[i].flags);\n\n                /* mapped BARs */\n                this_board->bar0io = xpdev->xdev->bar[0];\n                printk(\"bar0io=%p\\n\", this_board->bar0io);\n                this_board->bar1io = xpdev->xdev->bar[1];\n                printk(\"bar1io=%p\\n\", this_board->bar1io);\n                this_board->bar2io = xpdev->xdev->bar[2];\n                printk(\"bar2io=%p\\n\", this_board->bar2io);\n                this_board->bar4io = xpdev->xdev->bar[4];\n                printk(\"bar4io=%p\\n\", this_board->bar4io);\n\n                if (!this_board->bar4io) {\n                        this_board->info.aws_shell = 0;\n                        // this replaces 'connectal/pcie/connectalutil/connectalutil trace /dev/fpga0'\n                        // but why is it needed?...\n                        iowrite32(0, this_board->bar0io + CSR_TLPPCIEWRADDRREG);\n                        // enable tracing\n                        iowrite32(1, this_board->bar0io + CSR_TLPTRACINGREG);\n                        /* check the magic number in BAR 0 */\n                        magic_num = ((long long)ioread32(this_board->bar0io + CSR_ID +  4)) << 32;\n                        magic_num |= ioread32(this_board->bar0io + CSR_ID);\n                        if (magic_num != expected_magic) {\n                                printk(KERN_ERR \"%s: magic number %llx does not match expected %llx\\n\",\n                                       DEV_NAME, magic_num, expected_magic);\n                                err = -EINVAL;\n                        }\n                        // check for xdma on bar2\n                } else {\n                        this_board->info.aws_shell = 1;\n                        printk(\"  xdma block ID %x\\n\", ioread32(this_board->bar2io + 0x0000));\n                        printk(\"   irq block ID %x\\n\", ioread32(this_board->bar2io + 0x2000));\n                        printk(\"config block ID %x\\n\", ioread32(this_board->bar2io + 0x3000));\n                }\n                printk(\"pci_dev %08lx\\n\", (long)this_board->pci_dev);\n                this_board->irq_num = pci_irq_vector(this_board->pci_dev, 8);\n                for (i = 8; i < 16; i++) {\n\t\t\tint irq_num = pci_irq_vector(this_board->pci_dev, i);\n                        if (request_irq(irq_num, intr_handler, 0, DEV_NAME, (void *)&this_board->tile[0])) {\n                                printk(KERN_ERR \"%s: Failed to get requested IRQ %d\\n\", DEV_NAME, irq_num);\n                                err = -EBUSY;\n                        }\n                }\n#if 0\n                /* enable MSIX */\n                for (i = 0; i < num_entries; i++)\n                        msix_entries[i].entry = i;\n                if ((num_entries = pci_enable_msix_range(dev, msix_entries, num_entries, num_entries)) < 0) {\n                        printk(KERN_ERR \"%s: Failed to setup MSIX interrupts\\n\", DEV_NAME);\n                        err = -EFAULT;\n                        goto BARS_MAPPED_label;\n                }\n                this_board->irq_num = msix_entries[0].vector;\n                printk(KERN_INFO \"%s: Using MSIX interrupts num_entries=%d check_device\\n\", DEV_NAME, num_entries);\n                for (i = 0; i < num_entries; i++)\n                        printk(KERN_INFO \"%s: msix_entries[%d] vector=%d entry=%08x\\n\", DEV_NAME, i, msix_entries[i].vector, msix_entries[i].entry);\n                /* install the IRQ handler */\n                for (i = 0; i < num_entries; i++) {\n                        if (request_irq(this_board->irq_num + i, intr_handler, 0, DEV_NAME, (void *) &this_board->tile[i])) {\n                                printk(KERN_ERR \"%s: Failed to get requested IRQ %d\\n\", DEV_NAME, this_board->irq_num);\n                                err = -EBUSY;\n                                goto MSI_ENABLED_label;\n                        }\n                }\n                /* set MSIX Entry 0 Vector Control value to 0 (unmasked) */\n                printk(KERN_INFO \"%s: MSIX interrupts enabled with %d IRQs starting at %d\\n\",\n                       DEV_NAME, num_entries, this_board->irq_num);\n                iowrite32(0, this_board->bar0io + CSR_MSIX_MASKED);\n                pci_set_master(dev); /* enable PCI bus master */\n#endif\n                if (this_board->info.aws_shell) {\n                        portal_base = this_board->bar0io;\n                        ptile = this_board->bar0io;\n                        printk(\"bar0io[0]=%08x\\n\", *(int *)this_board->bar0io);\n\n                        // enable user interrupts via XDMA block in AWS F1 Shell\n                        iowrite32(0xFFFF, this_board->bar2io + 0x2000 + 4);\n                        printk(\"enabled user interrupts in XDMA %x\\n\", ioread32(this_board->bar2io + 0x2000 + 4));\n\n                } else {\n                        portal_base = this_board->bar2io;\n                        ptile = this_board->bar2io;\n                }\n                num_tiles = *(volatile uint32_t *)(ptile + PCR_NUM_TILES_OFFSET);\n                if (num_tiles < 0 || num_tiles > 16)\n                        num_tiles = 0;\n                tile_index = 0;\n                do {  // loop over all tiles\n                        void __iomem *pportal = ptile;\n                        int num_portals = *(volatile uint32_t *)(pportal + PCR_NUM_PORTALS_OFFSET);\n                        int portal_index = 0;\n\t\t\tprintk(\"tile %d num_portals %d\\n\", tile_index, num_portals);\n                        this_board->tile[tile_index].board = this_board;\n                        this_board->tile[tile_index].device_tile = tile_index + 1;\n                        do {  // loop over all portals in a tile\n                                int freep;\n                                uint32_t iid = *(volatile uint32_t *)(pportal + PCR_IID_OFFSET);\n                                tPortal *this_portal = &this_board->portal[fpn];\n                                unsigned long offs = ((unsigned long)pportal) - ((unsigned long)portal_base);\n                                if (iid == -1)\n                                        break;\n                                printk(\"%s:%d num_tiles %x/%x num_portals %x/%x fpn %x iid=%d pportal %p offset %lx\\n\", __FUNCTION__, __LINE__, tile_index, num_tiles, portal_index, num_portals, fpn, iid, pportal, offs);\n                                for (freep = 0; freep < sizeof(portalp)/sizeof(portalp[0]); freep++)\n                                        if (!portalp[freep])\n                                                break;\n                                if (freep == sizeof(portalp)/sizeof(portalp[0])) {\n                                        printk(KERN_ERR \"%s: too many portals\\n\", KERN_ERR);\n                                        err = -EFAULT;\n                                }\n                                else\n                                        portalp[freep] = 1;\n                                this_portal->device_number = freep;\n                                this_portal->device_tile = tile_index;\n                                this_portal->portal_number = fpn;\n                                this_portal->device_name = iid;\n                                this_portal->board = this_board;\n                                this_portal->regs = (volatile uint32_t *)pportal;\n                                this_portal->offset = offs;\n                                /* add the device operations */\n                                cdev_init(&this_portal->cdev, &pcieportal_fops);\n                                this_device_number = MKDEV(MAJOR(device_number), MINOR(device_number) + this_portal->device_number);\n                                printk(\"%s:%d: calling cdev_add this_device_number=%x\\n\", DEV_NAME, __LINE__, this_device_number);\n                                if (cdev_add(&this_portal->cdev, this_device_number, 1)) {\n                                        printk(KERN_ERR \"%s: cdev_add %x failed\\n\",\n                                               DEV_NAME, this_device_number);\n                                        err = -EFAULT;\n                                } else {\n                                        /* create a device node via udev */\n                                        printk(\"%s:%d: calling_device_create /dev/%s_b%dt%dp%d = %x\\n\",\n                                               DEV_NAME, __LINE__, DEV_NAME, this_portal->board->info.board_number, this_portal->device_tile, this_portal->device_name, this_device_number);\n                                        device_create(pcieportal_class, &dev->dev, this_device_number,\n                                                      this_portal, \"%s_b%dt%dp%d\", DEV_NAME, this_portal->board->info.board_number, this_portal->device_tile, this_portal->device_name);\n                                        printk(KERN_INFO \"%s: /dev/%s_b%dt%dp%d = %x created\\n\",\n                                               DEV_NAME, DEV_NAME, this_portal->board->info.board_number, this_portal->device_tile, this_portal->device_name, this_device_number);\n                                }\n                                if (++fpn >= MAX_NUM_PORTALS){\n                                        printk(KERN_INFO \"%s: MAX_NUM_PORTALS exceeded\", __func__);\n                                        err = -EFAULT;\n                                        break;\n                                }\n                                pportal += PORTAL_BASE_OFFSET;\n                        } while (++portal_index < num_portals);\n                        ptile += TILE_BASE_OFFSET;\n                } while (++tile_index < num_tiles);\n                this_board->info.num_portals = fpn;\n\n                if (board_number == 0) {\n                        this_device_number = MKDEV(MAJOR(device_number), MINOR(device_number) + MAX_MINOR_COUNT);\n                        cdev_init(&this_board->cdev, &connectal_fops);\n                        printk(\"%s:%d: calling cdev_add this_device_number=%x\\n\", DEV_NAME, __LINE__, this_device_number);\n                        if (cdev_add(&this_board->cdev, this_device_number, 1)) {\n                                printk(KERN_ERR \"%s: cdev_add board failed\\n\", DEV_NAME);\n                        }\n                        printk(\"%s:%d: calling device_create this_device_number=%x\\n\", DEV_NAME, __LINE__, this_device_number);\n                        device_create(pcieportal_class, &dev->dev, this_device_number, NULL, \"connectal\");\n\n                        // add the device node for portal_dma_pcis\n                        this_device_number = MKDEV(MAJOR(device_number), MINOR(device_number) + MAX_MINOR_COUNT + 1);\n                        cdev_init(&this_board->dma_pcis_cdev, &pcieportal_dma_pcis_fops);\n                        printk(\"%s:%d: calling cdev_add this_device_number=%x\\n\", DEV_NAME, __LINE__, this_device_number);\n                        printk(\"%s:%d: calling cdev_add this_board=%lx\\n\", DEV_NAME, __LINE__, (long)this_board);\n                        if (cdev_add(&this_board->dma_pcis_cdev, this_device_number, 1)) {\n                                printk(KERN_ERR \"%s: cdev_add board failed\\n\", DEV_NAME);\n                        }\n                        printk(\"%s:%d: calling device_create this_device_number=%x\\n\", DEV_NAME, __LINE__, this_device_number);\n                        device_create(pcieportal_class, &dev->dev, this_device_number, NULL, \"portal_dma_pcis\");\n                }\n\n                printk(\"%s:%d num_portals %d\\n\", DEV_NAME, __LINE__, this_board->info.num_portals);\n                printk(\"%s:%d returning %d\\n\", DEV_NAME, __LINE__, err);\n                if (err == 0)\n                        return err; /* if board activated correctly, return */\n        } /* end of if(activate) */\n\n        printk(\"%s:%d\\n\", DEV_NAME, __LINE__);\n        /******** deactivate board *******/\n        if (board_number == 0) {\n                device_destroy(pcieportal_class, MKDEV(MAJOR(device_number), MINOR(device_number) + MAX_MINOR_COUNT));\n                cdev_del(&this_board->cdev);\n\n                device_destroy(pcieportal_class, MKDEV(MAJOR(device_number), MINOR(device_number) + MAX_MINOR_COUNT + 1));\n                cdev_del(&this_board->dma_pcis_cdev);\n        }\n        fpn = 0;\n        printk(\"%s:%d\\n\", DEV_NAME, __LINE__);\n        printk(\"%s:%d num_portals %d\\n\", DEV_NAME, __LINE__, this_board->info.num_portals);\n        while(fpn < this_board->info.num_portals) {\n                tPortal *this_portal = &this_board->portal[fpn];\n                /* remove device node in udev */\n                dev_t this_device_number = MKDEV(MAJOR(device_number), MINOR(device_number) + this_portal->device_number);\n                portalp[this_portal->device_name] = 0;\n                device_destroy(pcieportal_class, this_device_number);\n                printk(KERN_INFO \"%s: /dev/%s_b%dt%dp%d = %x removed\\n\",\n                       DEV_NAME, DEV_NAME, this_portal->board->info.board_number, this_portal->device_tile, this_portal->device_name, this_device_number);\n                /* remove device */\n                cdev_del(&this_board->portal[fpn].cdev);\n                fpn++;\n        }\n#if 0\n        pci_clear_master(dev); /* disable PCI bus master */\n#endif\n        printk(\"%s:%d\\n\", DEV_NAME, __LINE__);\n        /* set MSIX Entry 0 Vector Control value to 1 (masked) */\n        iowrite32(1, this_board->bar0io + CSR_MSIX_MASKED);\n#if 0\n        disable_irq(this_board->irq_num);\n        for (i = 0; i < num_entries; i++) \n                free_irq(this_board->irq_num + i, (void *) &this_board->tile[i]);\n#endif\n\tfor (i = 8; i < 16; i++) {\n\t\tint irq_num = pci_irq_vector(this_board->pci_dev, i);\n\t\tfree_irq(irq_num, (void *)&this_board->tile[0]);\n\t}\n\n        if (pcieportal_class)\n                class_destroy(pcieportal_class);\n\nerr_exit:\n        this_board->pci_dev = NULL;\n#if 0\n        pci_set_drvdata(dev, NULL);\n#endif\n        printk(\"%s:%d\\n\", DEV_NAME, __LINE__);\n        return err;\n}\n\n/* driver PCI operations */\n\n#if 0\nstatic int pcieportal_probe(struct pci_dev *dev, const struct pci_device_id *id)\n{\n        tBoard *this_board = NULL;\n        int board_number = 0;\n        int activated;\n\nprintk(\"******[%s:%d] probe %p dev %p id %p getdrv %p\\n\", __FUNCTION__, __LINE__, &pcieportal_probe, dev, id, pci_get_drvdata(dev));\n        printk(KERN_INFO \"%s: PCI probe for 0x%04x 0x%04x\\n\", DEV_NAME, dev->vendor, dev->device); \n        /* double-check vendor and device */\n        if ((dev->vendor != BLUESPEC_VENDOR_ID || dev->device != CONNECTAL_DEVICE_ID)\n            && (dev->vendor != AMAZON_VENDOR_ID || dev->device != AMAZON_DEVICE_ID)) {\n                printk(KERN_ERR \"%s: probe with invalid vendor or device ID\\n\", DEV_NAME);\n                return -EINVAL;\n        }\n        /* assign a board number */\n        while (board_map[board_number].pci_dev && board_number < NUM_BOARDS)\n                board_number++;\n        if (board_number >= NUM_BOARDS) {\n                printk(KERN_ERR \"%s: %d boards are already in use!\\n\", DEV_NAME, NUM_BOARDS);\n                return -EBUSY;\n        }\n        this_board = &board_map[board_number];\n        printk(KERN_INFO \"%s: board_number = %d\\n\", DEV_NAME, board_number);\n        memset(this_board, 0, sizeof(tBoard));\n        this_board->info.board_number = board_number;\n        activated =  pcieportal_board_activate(1, this_board, 0, dev);\n        if (activated) {\n                pci_set_drvdata(dev, this_board);\n        }\n        return activated;\n}\n\nstatic void pcieportal_remove(struct pci_dev *dev)\n{\n        tBoard *this_board = pci_get_drvdata(dev);\nprintk(\"*****[%s:%d] getdrv %p\\n\", __FUNCTION__, __LINE__, this_board);\n        if (!this_board) {\n                printk(KERN_ERR \"%s: Unable to locate board when removing PCI device %p\\n\", DEV_NAME, dev);\n                return;\n        }\n        pcieportal_board_activate(0, this_board, dev);\n}\n\n/* PCI ID pattern table */\nstatic\n#ifdef DEFINE_PCI_DEVICE_TABLE // changed in Linux 4.8\n    DEFINE_PCI_DEVICE_TABLE(pcieportal_id_table)\n#else\n    const struct pci_device_id pcieportal_id_table[]\n#endif\n        = {\n  { PCI_DEVICE(BLUESPEC_VENDOR_ID, CONNECTAL_DEVICE_ID)},\n  { PCI_DEVICE(AMAZON_VENDOR_ID, AMAZON_DEVICE_ID)},\n  { /* end: all zeros */ }\n};\n\nMODULE_DEVICE_TABLE(pci, pcieportal_id_table);\n\nstatic pci_ers_result_t pcieportal_error_detected(struct pci_dev *pdev, enum pci_channel_state error)\n{\n        printk(KERN_ERR \"%s:%s: pcie error %d\\n\", DEV_NAME, __FUNCTION__, error);\n        return PCI_ERS_RESULT_CAN_RECOVER;\n}\n\nstatic pci_ers_result_t pcieportal_error_mmio_enabled(struct pci_dev *pdev)\n{\n        printk(KERN_ERR \"%s:%s\\n\", DEV_NAME, __FUNCTION__);\n        return PCI_ERS_RESULT_CAN_RECOVER;\n}\n\nstatic pci_ers_result_t pcieportal_error_slot_reset(struct pci_dev *pdev)\n{\n        printk(KERN_ERR \"%s:%s\\n\", DEV_NAME, __FUNCTION__);\n        return PCI_ERS_RESULT_CAN_RECOVER;\n}\n\nstatic void pcieportal_error_resume(struct pci_dev *pdev)\n{\n        printk(KERN_ERR \"%s:%s\\n\", DEV_NAME, __FUNCTION__);\n}\n\nstatic const struct pci_error_handlers pcieportal_err_handler = {\n        .error_detected = pcieportal_error_detected,\n        .mmio_enabled   = pcieportal_error_mmio_enabled,\n        .slot_reset     = pcieportal_error_slot_reset,\n        .resume         = pcieportal_error_resume,\n};\n#endif\n\n/*\n * driver initialization and exit\n *\n * these routines are responsible for allocating and\n * freeing kernel resources, creating device nodes,\n * registering the driver, obtaining a major and minor\n * numbers, etc.\n */\n\n#if 0\n/* PCI driver operations pointers */\nstatic struct pci_driver pcieportal_ops = {\n        .name = DEV_NAME,\n        .id_table = pcieportal_id_table,\n        .probe = pcieportal_probe,\n        .remove = pcieportal_remove,\n        .err_handler = &pcieportal_err_handler,\n};\n\n/* first routine called on module load */\nstatic int pcieportal_init(void)\n{\n        int status;\n\nprintk(\"[%s:%d]\\n\", __FUNCTION__, __LINE__);\n        pcieportal_class = class_create(THIS_MODULE, \"Connectal\");\n        if (IS_ERR(pcieportal_class)) {\n                printk(KERN_ERR \"%s: failed to create class Connectal\\n\", DEV_NAME);\n                return PTR_ERR(pcieportal_class);\n        }\n        /* dynamically allocate a device number */\n        if (alloc_chrdev_region(&device_number, 1, MAX_MINOR_COUNT + 1, DEV_NAME) < 0) {\n                printk(KERN_ERR \"%s: failed to allocate character device region\\n\", DEV_NAME);\n                class_destroy(pcieportal_class);\n                return -1;\n        }\n        /* initialize driver data */\n        memset(board_map, 0, sizeof(board_map));\n        /* log the fact that we loaded the driver module */\n        printk(KERN_INFO \"%s: Registered Connectal Pcieportal driver %s\\n\", DEV_NAME, DRIVER_VERSION);\n        printk(KERN_INFO \"%s: Major = %d  Minors = %d to %d\\n\", DEV_NAME,\n               MAJOR(device_number), MINOR(device_number),\n               MINOR(device_number) + MAX_MINOR_COUNT - 1);\n        /* register the driver with the PCI subsystem */\n        status = pci_register_driver(&pcieportal_ops);\n        if (status < 0) {\n                printk(KERN_ERR \"%s: failed to register PCI driver\\n\", DEV_NAME);\n                class_destroy(pcieportal_class);\n                return status;\n        }\nprintk(\"[%s:%d]\\n\", __FUNCTION__, __LINE__);\n        return 0;                /* success */\n}\n\n/* routine called on module unload */\nstatic void pcieportal_exit(void)\n{\n        /* unregister the driver with the PCI subsystem */\n        pci_unregister_driver(&pcieportal_ops);\n        /* release reserved device numbers */\n        unregister_chrdev_region(device_number, MAX_MINOR_COUNT + 1);\n        class_destroy(pcieportal_class);\n        /* log that the driver module has been unloaded */\n        printk(KERN_INFO \"%s: Unregistered Connectal Pcieportal driver %s\\n\", DEV_NAME, DRIVER_VERSION);\n}\n\n\n/*\n * driver module data for the kernel\n */\n\nmodule_init(pcieportal_init);\nmodule_exit(pcieportal_exit);\n#endif\n\nMODULE_AUTHOR(\"Bluespec, Inc., Cambridge hackers\");\nMODULE_DESCRIPTION(\"PCIe device driver for PCIe FPGA portals\");\nMODULE_LICENSE(\"Dual BSD/GPL\");\nMODULE_VERSION(DRIVER_VERSION);\n"
  },
  {
    "path": "drivers/awsf1portal/portal_internal.h",
    "content": "/* Copyright (c) 2020 Accelerated Tech, Inc\n *\n * Permission is hereby granted, free of charge, to any person obtaining a\n * copy of this software and associated documentation files (the \"Software\"),\n * to deal in the Software without restriction, including without limitation\n * the rights to use, copy, modify, merge, publish, distribute, sublicense,\n * and/or sell copies of the Software, and to permit persons to whom the\n * Software is furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n * DEALINGS IN THE SOFTWARE.\n */\n#ifndef __PORTAL_INTERNAL_H__\n#define __PORTAL_INTERNAL_H__\n\n#include <linux/ioctl.h>\n#include <linux/cdev.h>\n#include \"pcieportal.h\"\n\n#ifdef __KERNEL__\n/*\n * Per-device data\n */\ntypedef struct {\n        struct cdev       cdev; /* per-portal cdev structure */\n        unsigned int      device_number;\n        unsigned int      device_tile;\n        unsigned int      portal_number;\n        unsigned int      device_name;\n        struct tBoard    *board;\n        void             *virt;\n        volatile uint32_t *regs;  // Pointer to access portal from kernel\n        unsigned long     offset; // Offset from base of BAR2\n        struct extra_info *extra;\n\tstruct list_head pmlist;\n        wait_queue_head_t wait_queue; /* used for interrupt notifications */\n        dma_addr_t        dma_handle;\n} tPortal;\n\ntypedef struct {\n        unsigned int      device_tile;\n        struct tBoard    *board;\n} tTile;\n\nstruct pmentry {\n\tstruct file     *fmem;\n\tint              id;\n\tstruct list_head pmlist;\n};\n\ntypedef struct tBoard {\n\tstruct cdev       cdev;\n\tstruct cdev       dma_pcis_cdev;\n        void __iomem     *bar0io, *bar1io, *bar2io, *bar4io; /* bars */\n        struct pci_dev   *pci_dev; /* pci device pointer */\n        tPortal           portal[MAX_NUM_PORTALS];\n        unsigned int      irq_num;\n        unsigned int      open_count;\n        tTile             tile[MAX_NUM_PORTALS];\n        struct extra_info *extra;\n        struct extra_info *pcis; // DMA PCIS on AWSF1\n        struct {\n          unsigned int board_number;\n          unsigned int portal_number;\n          unsigned int num_portals;\n\t  unsigned int aws_shell;\n        }                 info; /* board identification fields */\n} tBoard;\n\nextern tBoard* get_pcie_portal_descriptor(void);\n#endif\n\nstruct xdma_pci_dev;\nint pcieportal_board_activate(int activate, tBoard *this_board, struct xdma_pci_dev *xpdev, struct pci_dev *dev);\n\n#endif /* __BLUENOC_H__ */\n"
  },
  {
    "path": "drivers/awsf1portal/version.h",
    "content": "/*******************************************************************************\n *\n * Xilinx XDMA IP Core Linux Driver\n * Copyright(c) 2015 - 2017 Xilinx, Inc.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms and conditions of the GNU General Public License,\n * version 2, as published by the Free Software Foundation.\n *\n * This program is distributed in the hope it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\n * more details.\n *\n * You should have received a copy of the GNU General Public License along\n * with this program.  If not, see <http://www.gnu.org/licenses/>.\n *\n * The full GNU General Public License is included in this distribution in\n * the file called \"LICENSE\".\n *\n * Karen Xie <karen.xie@xilinx.com>\n *\n ******************************************************************************/\n#ifndef __XDMA_VERSION_H__\n#define __XDMA_VERSION_H__\n\n#define DRV_MOD_MAJOR\t\t2017\n#define DRV_MOD_MINOR\t\t1\n#define DRV_MOD_PATCHLEVEL\t47\n\n#define DRV_MODULE_VERSION      \\\n\t__stringify(DRV_MOD_MAJOR) \".\" \\\n\t__stringify(DRV_MOD_MINOR) \".\" \\\n\t__stringify(DRV_MOD_PATCHLEVEL)\n\n#define DRV_MOD_VERSION_NUMBER  \\\n\t((DRV_MOD_MAJOR)*1000 + (DRV_MOD_MINOR)*100 + DRV_MOD_PATCHLEVEL)\n\n#endif /* ifndef __XDMA_VERSION_H__ */\n"
  },
  {
    "path": "drivers/awsf1portal/xdma_cdev.c",
    "content": "/*******************************************************************************\n *\n * Xilinx XDMA IP Core Linux Driver\n * Copyright(c) 2015 - 2017 Xilinx, Inc.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms and conditions of the GNU General Public License,\n * version 2, as published by the Free Software Foundation.\n *\n * This program is distributed in the hope it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\n * more details.\n *\n * You should have received a copy of the GNU General Public License along\n * with this program.  If not, see <http://www.gnu.org/licenses/>.\n *\n * The full GNU General Public License is included in this distribution in\n * the file called \"LICENSE\".\n *\n * Karen Xie <karen.xie@xilinx.com>\n *\n ******************************************************************************/\n#define pr_fmt(fmt)     KBUILD_MODNAME \":%s: \" fmt, __func__\n\n#include \"xdma_cdev.h\"\n\nstruct class *g_xdma_class;\n\nenum cdev_type {\n\tCHAR_USER,\n\tCHAR_CTRL,\n\tCHAR_XVC,\n\tCHAR_EVENTS,\n\tCHAR_XDMA_H2C,\n\tCHAR_XDMA_C2H,\n\tCHAR_BYPASS_H2C,\n\tCHAR_BYPASS_C2H,\n\tCHAR_BYPASS,\n};\n\nstatic const char * const devnode_names[] = {\n\tXDMA_NODE_NAME \"%d_user\",\n\tXDMA_NODE_NAME \"%d_control\",\n\tXDMA_NODE_NAME \"%d_xvc\",\n\tXDMA_NODE_NAME \"%d_events_%d\",\n\tXDMA_NODE_NAME \"%d_h2c_%d\",\n\tXDMA_NODE_NAME \"%d_c2h_%d\",\n\tXDMA_NODE_NAME \"%d_bypass_h2c_%d\",\n\tXDMA_NODE_NAME \"%d_bypass_c2h_%d\",\n\tXDMA_NODE_NAME \"%d_bypass\",\n};\n\nenum xpdev_flags_bits {\n        XDF_CDEV_USER,\n        XDF_CDEV_CTRL,\n        XDF_CDEV_XVC,\n        XDF_CDEV_EVENT,\n        XDF_CDEV_SG,\n        XDF_CDEV_BYPASS,\n};\n\nstatic inline void xpdev_flag_set(struct xdma_pci_dev *xpdev,\n\t\t\t\tenum xpdev_flags_bits fbit)\n{\n\txpdev->flags |= 1 << fbit;\n}\n\nstatic inline void xcdev_flag_clear(struct xdma_pci_dev *xpdev,\n\t\t\t\tenum xpdev_flags_bits fbit)\n{\n\txpdev->flags &= ~(1 << fbit);\n}\n\nstatic inline int xpdev_flag_test(struct xdma_pci_dev *xpdev,\n\t\t\t\tenum xpdev_flags_bits fbit)\n{\n\treturn xpdev->flags & (1 << fbit);\n}\n\n#ifdef __XDMA_SYSFS__\nssize_t show_device_numbers(struct device *dev, struct device_attribute *attr,\n\t\t\t\t char *buf)\n{\n\tstruct xdma_pci_dev *xpdev = (struct xdma_pci_dev *)dev_get_drvdata(dev);\n\n\treturn snprintf(buf, PAGE_SIZE, \"%d\\t%d\\n\",\n\t\t\txpdev->major, xpdev->xdev->idx);\n}\n\nstatic DEVICE_ATTR(xdma_dev_instance, S_IRUGO, show_device_numbers, NULL);\n#endif\n\nstatic int config_kobject(struct xdma_cdev *xcdev, enum cdev_type type)\n{\n\tint rv = -EINVAL;\n\tstruct xdma_dev *xdev = xcdev->xdev;\n\tstruct xdma_engine *engine = xcdev->engine;\n\n\tswitch (type) {\n\tcase CHAR_XDMA_H2C:\n\tcase CHAR_XDMA_C2H:\n\tcase CHAR_BYPASS_H2C:\n\tcase CHAR_BYPASS_C2H:\n\t\tBUG_ON(!engine);\n\t\trv = kobject_set_name(&xcdev->cdev.kobj, devnode_names[type],\n\t\t\txdev->idx, engine->channel);\n\t\tbreak;\n\tcase CHAR_BYPASS:\n\tcase CHAR_USER:\n\tcase CHAR_CTRL:\n\tcase CHAR_XVC:\n\t\trv = kobject_set_name(&xcdev->cdev.kobj, devnode_names[type],\n\t\t\txdev->idx);\n\t\tbreak;\n\tcase CHAR_EVENTS:\n\t\trv = kobject_set_name(&xcdev->cdev.kobj, devnode_names[type],\n\t\t\txdev->idx, xcdev->bar);\n\t\tbreak;\n\tdefault:\n\t\tpr_warn(\"%s: UNKNOWN type 0x%x.\\n\", __func__, type);\n\t\tbreak;\n\t}\n\n\tif (rv)\n\t\tpr_err(\"%s: type 0x%x, failed %d.\\n\", __func__, type, rv);\n\treturn rv;\n}\n\nint xcdev_check(const char *fname, struct xdma_cdev *xcdev, bool check_engine)\n{\n\tstruct xdma_dev *xdev;\n\n\tif (!xcdev || xcdev->magic != MAGIC_CHAR) {\n\t\tpr_info(\"%s, xcdev 0x%p, magic 0x%lx.\\n\",\n\t\t\tfname, xcdev, xcdev ? xcdev->magic : 0xFFFFFFFF);\t\n\t\treturn -EINVAL;\n\t}\n\n        xdev = xcdev->xdev;\n\tif (!xdev || xdev->magic != MAGIC_DEVICE) {\n\t\tpr_info(\"%s, xdev 0x%p, magic 0x%lx.\\n\",\n\t\t\tfname, xdev, xdev ? xdev->magic : 0xFFFFFFFF);\t\n\t\treturn -EINVAL;\n\t}\n\n\tif (check_engine) {\n        \tstruct xdma_engine *engine = xcdev->engine;\n\t\tif (!engine || engine->magic != MAGIC_ENGINE) {\n\t\t\tpr_info(\"%s, engine 0x%p, magic 0x%lx.\\n\", fname,\n\t\t\t\tengine, engine ? engine->magic : 0xFFFFFFFF);\t\n\t\t\treturn -EINVAL;\n\t\t}\n\t}\n\n\treturn 0;\n}\n\nint char_open(struct inode *inode, struct file *file)\n{\n\tstruct xdma_cdev *xcdev;\n\n\t/* pointer to containing structure of the character device inode */\n\txcdev = container_of(inode->i_cdev, struct xdma_cdev, cdev);\n\tBUG_ON(xcdev->magic != MAGIC_CHAR);\n\t/* create a reference to our char device in the opened file */\n\tfile->private_data = xcdev;\n\n\treturn 0;\n}\n\n/*\n * Called when the device goes from used to unused.\n */\nint char_close(struct inode *inode, struct file *file)\n{\n\tstruct xdma_dev *xdev;\n\tstruct xdma_cdev *xcdev = (struct xdma_cdev *)file->private_data;\n\n\tBUG_ON(!xcdev);\n\tBUG_ON(xcdev->magic != MAGIC_CHAR);\n\n\t/* fetch device specific data stored earlier during open */\n\txdev = xcdev->xdev;\n\tBUG_ON(!xdev);\n\tBUG_ON(xdev->magic != MAGIC_DEVICE);\n\n\treturn 0;\n}\n\n/* create_xcdev() -- create a character device interface to data or control bus\n *\n * If at least one SG DMA engine is specified, the character device interface\n * is coupled to the SG DMA file operations which operate on the data bus. If\n * no engines are specified, the interface is coupled with the control bus.\n */\n\nstatic int create_sys_device(struct xdma_cdev *xcdev, enum cdev_type type)\n{\n        struct xdma_dev *xdev = xcdev->xdev;\n        struct xdma_engine *engine = xcdev->engine;\n        int last_param;\n\n        if (type == CHAR_EVENTS)\n                last_param = xcdev->bar;\n        else\n                last_param = engine ? engine->channel : 0;\n\n        xcdev->sys_device = device_create(g_xdma_class, &xdev->pdev->dev,\n                xcdev->cdevno, NULL, devnode_names[type], xdev->idx,\n                last_param);\n\n        if (!xcdev->sys_device) {\n                pr_err(\"device_create(%s) failed\\n\", devnode_names[type]);\n                return -1;\n        }\n\n        return 0;\n}\n\nstatic int destroy_xcdev(struct xdma_cdev *cdev)\n{\n\tif (!cdev) {\n\t\tpr_warn(\"cdev NULL.\\n\");\n\t\treturn 0;\n\t}\n\tif (cdev->magic != MAGIC_CHAR) {\n\t\tpr_warn(\"cdev 0x%p magic mismatch 0x%lx\\n\", cdev, cdev->magic);\n\t\treturn 0;\n\t}\n\tBUG_ON(!cdev->xdev);\n\tBUG_ON(!g_xdma_class);\n\tBUG_ON(!cdev->sys_device);\n\n\tif (cdev->sys_device)\n\t\tdevice_destroy(g_xdma_class, cdev->cdevno);\n\n\tcdev_del(&cdev->cdev);\n\n\treturn 0;\n}\n\nstatic int create_xcdev(struct xdma_pci_dev *xpdev, struct xdma_cdev *xcdev,\n\t\t\tint bar, struct xdma_engine *engine,\n\t\t\tenum cdev_type type)\n{\n\tint rv;\n\tint minor;\n\tstruct xdma_dev *xdev = xpdev->xdev;\n\tdev_t dev;\n\n\tspin_lock_init(&xcdev->lock);\n\t/* new instance? */\n\tif (!xpdev->major) {\n\t\t/* allocate a dynamically allocated char device node */\n\t\tint rv = alloc_chrdev_region(&dev, XDMA_MINOR_BASE,\n\t\t\t\t\tXDMA_MINOR_COUNT, XDMA_NODE_NAME);\n\n\t\tif (rv) {\n\t\t\tpr_err(\"unable to allocate cdev region %d.\\n\", rv);\n\t\t\treturn rv;\n\t\t}\n\t\txpdev->major = MAJOR(dev);\n\t}\n\n\t/*\n\t * do not register yet, create kobjects and name them,\n\t */\n\txcdev->magic = MAGIC_CHAR;\n\txcdev->cdev.owner = THIS_MODULE;\n\txcdev->xpdev = xpdev;\n\txcdev->xdev = xdev;\n\txcdev->engine = engine;\n\txcdev->bar = bar;\n\n\trv = config_kobject(xcdev, type);\n\tif (rv < 0)\n\t\treturn rv;\n\n\tswitch (type) {\n\tcase CHAR_USER:\n\tcase CHAR_CTRL:\n\t\t/* minor number is type index for non-SGDMA interfaces */\n\t\tminor = type;\n\t\tcdev_ctrl_init(xcdev);\n\t\tbreak;\n\tcase CHAR_XVC:\n\t\t/* minor number is type index for non-SGDMA interfaces */\n\t\tminor = type;\n\t\tcdev_xvc_init(xcdev);\n\t\tbreak;\n\tcase CHAR_XDMA_H2C:\n\t\tminor = 32 + engine->channel;\n\t\tcdev_sgdma_init(xcdev);\n\t\tbreak;\n\tcase CHAR_XDMA_C2H:\n\t\tminor = 36 + engine->channel;\n\t\tcdev_sgdma_init(xcdev);\n\t\tbreak;\n\tcase CHAR_EVENTS:\n\t\tminor = 10 + bar;\n\t\tcdev_event_init(xcdev);\n\t\tbreak;\n\tcase CHAR_BYPASS_H2C:\n\t\tminor = 64 + engine->channel;\n\t\tcdev_bypass_init(xcdev);\n\t\tbreak;\n\tcase CHAR_BYPASS_C2H:\n\t\tminor = 68 + engine->channel;\n\t\tcdev_bypass_init(xcdev);\n\t\tbreak;\n\tcase CHAR_BYPASS:\n\t\tminor = 100;\n\t\tcdev_bypass_init(xcdev);\n\t\tbreak;\n\tdefault:\n\t\tpr_info(\"type 0x%x NOT supported.\\n\", type);\n\t\treturn -EINVAL;\n\t}\n\txcdev->cdevno = MKDEV(xpdev->major, minor);\n\n\t/* bring character device live */\n\trv = cdev_add(&xcdev->cdev, xcdev->cdevno, 1);\n\tif (rv < 0) {\n\t\tpr_err(\"cdev_add failed %d, type 0x%x.\\n\", rv, type);\n\t\tgoto unregister_region;\n\t}\n\n\tdbg_init(\"xcdev 0x%p, %u:%u, %s, type 0x%x.\\n\",\n\t\txcdev, xpdev->major, minor, xcdev->cdev.kobj.name, type);\n\n\t/* create device on our class */\n\tif (g_xdma_class) {\n\t\trv = create_sys_device(xcdev, type);\n\t\tif (rv < 0)\n\t\t\tgoto del_cdev;\n\t}\n\n\treturn 0;\n\ndel_cdev:\n\tcdev_del(&xcdev->cdev);\nunregister_region:\n\tunregister_chrdev_region(dev, XDMA_MINOR_COUNT);\n\treturn rv;\n}\n\nvoid xpdev_destroy_interfaces(struct xdma_pci_dev *xpdev)\n{\n\tint i;\n\n#ifdef __XDMA_SYSFS__\n        device_remove_file(&xpdev->pdev->dev, &dev_attr_xdma_dev_instance);\n#endif\n\n\tif (xpdev_flag_test(xpdev, XDF_CDEV_SG)) {\n\t\t/* iterate over channels */\n\t\tfor (i = 0; i < xpdev->h2c_channel_max; i++)\n\t\t\t/* remove SG DMA character device */\n\t\t\tdestroy_xcdev(&xpdev->sgdma_h2c_cdev[i]);\n\t\tfor (i = 0; i < xpdev->c2h_channel_max; i++)\n\t\t\tdestroy_xcdev(&xpdev->sgdma_c2h_cdev[i]);\n\t}\n\n\tif (xpdev_flag_test(xpdev, XDF_CDEV_EVENT)) {\n\t\tfor (i = 0; i < xpdev->user_max; i++)\n\t\t\tdestroy_xcdev(&xpdev->events_cdev[i]);\n\t}\n\n\t/* remove control character device */\n\tif (xpdev_flag_test(xpdev, XDF_CDEV_CTRL)) {\n\t\tdestroy_xcdev(&xpdev->ctrl_cdev);\n\t}\n\n\t/* remove user character device */\n\tif (xpdev_flag_test(xpdev, XDF_CDEV_USER)) {\n\t\tdestroy_xcdev(&xpdev->user_cdev);\n\t}\n\n\tif (xpdev_flag_test(xpdev, XDF_CDEV_XVC)) {\n\t\tdestroy_xcdev(&xpdev->xvc_cdev);\n\t}\n\n\tif (xpdev_flag_test(xpdev, XDF_CDEV_BYPASS)) {\n\t\t/* iterate over channels */\n\t\tfor (i = 0; i < xpdev->h2c_channel_max; i++)\n\t\t\t/* remove DMA Bypass character device */\n\t\t\tdestroy_xcdev(&xpdev->bypass_h2c_cdev[i]);\n\t\tfor (i = 0; i < xpdev->c2h_channel_max; i++)\n\t\t\tdestroy_xcdev(&xpdev->bypass_c2h_cdev[i]);\n\t\tdestroy_xcdev(&xpdev->bypass_cdev_base);\n\t}\n\n\tif (xpdev->major)\n\t\tunregister_chrdev_region(MKDEV(xpdev->major, XDMA_MINOR_BASE), XDMA_MINOR_COUNT);\n}\n\nint xpdev_create_interfaces(struct xdma_pci_dev *xpdev)\n{\n\tstruct xdma_dev *xdev = xpdev->xdev;\n\tstruct xdma_engine *engine;\n\tint i;\n\tint rv = 0;\n\n\t/* initialize control character device */\n\trv = create_xcdev(xpdev, &xpdev->ctrl_cdev, xdev->config_bar_idx,\n\t\t\tNULL, CHAR_CTRL);\n\tif (rv < 0) {\n\t\tpr_err(\"create_char(ctrl_cdev) failed\\n\");\n\t\tgoto fail;\n\t}\n\txpdev_flag_set(xpdev, XDF_CDEV_CTRL);\n\n\t/* initialize events character device */\n\tfor (i = 0; i < xpdev->user_max; i++) {\n\t\trv = create_xcdev(xpdev, &xpdev->events_cdev[i], i, NULL,\n\t\t\tCHAR_EVENTS);\n\t\tif (rv < 0) {\n\t\t\tpr_err(\"create char event %d failed, %d.\\n\", i, rv);\n\t\t\tgoto fail;\n\t\t}\n\t}\n\txpdev_flag_set(xpdev, XDF_CDEV_EVENT);\n\n\t/* iterate over channels */\n\tfor (i = 0; i < xpdev->h2c_channel_max; i++) {\n\t\tengine = &xdev->engine_h2c[i];\n\n\t\tif (engine->magic != MAGIC_ENGINE)\n\t\t\tcontinue;\n\n\t\trv = create_xcdev(xpdev, &xpdev->sgdma_h2c_cdev[i], i, engine,\n\t\t\t\t CHAR_XDMA_H2C);\n\t\tif (rv < 0) {\n\t\t\tpr_err(\"create char h2c %d failed, %d.\\n\", i, rv);\n\t\t\tgoto fail;\n\t\t}\n\t}\n\n\tfor (i = 0; i < xpdev->c2h_channel_max; i++) {\n\t\tengine = &xdev->engine_c2h[i];\n\n\t\tif (engine->magic != MAGIC_ENGINE)\n\t\t\tcontinue;\n\n\t\trv = create_xcdev(xpdev, &xpdev->sgdma_c2h_cdev[i], i, engine,\n\t\t\t\t CHAR_XDMA_C2H);\n\t\tif (rv < 0) {\n\t\t\tpr_err(\"create char c2h %d failed, %d.\\n\", i, rv);\n\t\t\tgoto fail;\n\t\t}\n\t}\n\txpdev_flag_set(xpdev, XDF_CDEV_SG);\n\n\t/* ??? Bypass */\n\t/* Initialize Bypass Character Device */\n\tif (xdev->bypass_bar_idx > 0){\n\t\tfor (i = 0; i < xpdev->h2c_channel_max; i++) {\n\t\t\tengine = &xdev->engine_h2c[i];\n\n\t\t\tif (engine->magic != MAGIC_ENGINE)\n\t\t\t\tcontinue;\n\n\t\t\trv = create_xcdev(xpdev, &xpdev->bypass_h2c_cdev[i], i,\n\t\t\t\t\tengine, CHAR_BYPASS_H2C);\n\t\t\tif (rv < 0) {\n\t\t\t\tpr_err(\"create h2c %d bypass I/F failed, %d.\\n\",\n\t\t\t\t\ti, rv);\n\t\t\t\tgoto fail;\n\t\t\t}\n\t\t}\n\n\t\tfor (i = 0; i < xpdev->c2h_channel_max; i++) {\n\t\t\tengine = &xdev->engine_c2h[i];\n\n\t\t\tif (engine->magic != MAGIC_ENGINE)\n\t\t\t\tcontinue;\n\n\t\t\trv = create_xcdev(xpdev, &xpdev->bypass_c2h_cdev[i], i,\n\t\t\t\t\tengine, CHAR_BYPASS_C2H);\n\t\t\tif (rv < 0) {\n\t\t\t\tpr_err(\"create c2h %d bypass I/F failed, %d.\\n\",\n\t\t\t\t\ti, rv);\n\t\t\t\tgoto fail;\n\t\t\t}\n\t\t}\n\n\t\trv = create_xcdev(xpdev, &xpdev->bypass_cdev_base,\n\t\t\t\txdev->bypass_bar_idx, NULL, CHAR_BYPASS);\n\t\tif (rv < 0) {\n\t\t\tpr_err(\"create bypass failed %d.\\n\", rv);\n\t\t\tgoto fail;\n\t\t}\n\t\txpdev_flag_set(xpdev, XDF_CDEV_BYPASS);\n\t}\n\n\t/* initialize user character device */\n\tif (xdev->user_bar_idx >= 0) {\n\t\trv = create_xcdev(xpdev, &xpdev->user_cdev, xdev->user_bar_idx,\n\t\t\tNULL, CHAR_USER);\n\t\tif (rv < 0) {\n\t\t\tpr_err(\"create_char(user_cdev) failed\\n\");\n\t\t\tgoto fail;\n\t\t}\n\t\txpdev_flag_set(xpdev, XDF_CDEV_USER);\n\n\t\t/* xvc */\n\t\trv = create_xcdev(xpdev, &xpdev->xvc_cdev, xdev->user_bar_idx,\n\t\t\t\t NULL, CHAR_XVC);\n\t\tif (rv < 0) {\n\t\t\tpr_err(\"create xvc failed, %d.\\n\", rv);\n\t\t\tgoto fail;\n\t\t}\n\t\txpdev_flag_set(xpdev, XDF_CDEV_XVC);\n\t}\n\n#ifdef __XDMA_SYSFS__\n\t/* sys file */\n\trv = device_create_file(&xpdev->pdev->dev,\n\t\t\t\t&dev_attr_xdma_dev_instance);\n\tif (rv) {\n\t\tpr_err(\"Failed to create device file \\n\");\n\t\tgoto fail;\n\t}\n#endif\n\n\treturn 0;\n\nfail:\n\trv = -1;\n\txpdev_destroy_interfaces(xpdev);\n\treturn rv;\n}\n\nint xdma_cdev_init(void)\n{\n\tg_xdma_class = class_create(THIS_MODULE, XDMA_NODE_NAME);\n        if (IS_ERR(g_xdma_class)) {\n                dbg_init(XDMA_NODE_NAME \": failed to create class\");\n                return -1;\n        }\n\n\treturn 0;\n}\n\nvoid xdma_cdev_cleanup(void)\n{\n\tif (g_xdma_class)\n\t\tclass_destroy(g_xdma_class);\n}\n"
  },
  {
    "path": "drivers/awsf1portal/xdma_cdev.h",
    "content": "/*******************************************************************************\n *\n * Xilinx XDMA IP Core Linux Driver\n * Copyright(c) 2015 - 2017 Xilinx, Inc.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms and conditions of the GNU General Public License,\n * version 2, as published by the Free Software Foundation.\n *\n * This program is distributed in the hope it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\n * more details.\n *\n * You should have received a copy of the GNU General Public License along\n * with this program.  If not, see <http://www.gnu.org/licenses/>.\n *\n * The full GNU General Public License is included in this distribution in\n * the file called \"LICENSE\".\n *\n * Karen Xie <karen.xie@xilinx.com>\n *\n ******************************************************************************/\n#ifndef __XDMA_CHRDEV_H__\n#define __XDMA_CHRDEV_H__\n\n#include <linux/kernel.h>\n#include <linux/types.h>\n#include <linux/uaccess.h>\n#include <linux/errno.h>\n#include \"xdma_mod.h\"\n\n#define XDMA_NODE_NAME\t\"xdma\"\n#define XDMA_MINOR_BASE (0)\n#define XDMA_MINOR_COUNT (255)\n\nvoid xdma_cdev_cleanup(void);\nint xdma_cdev_init(void);\n\nint char_open(struct inode *inode, struct file *file);\nint char_close(struct inode *inode, struct file *file);\nint xcdev_check(const char *, struct xdma_cdev *, bool);\n\nvoid cdev_ctrl_init(struct xdma_cdev *xcdev);\nvoid cdev_xvc_init(struct xdma_cdev *xcdev);\nvoid cdev_event_init(struct xdma_cdev *xcdev);\nvoid cdev_sgdma_init(struct xdma_cdev *xcdev);\nvoid cdev_bypass_init(struct xdma_cdev *xcdev);\n\nvoid xpdev_destroy_interfaces(struct xdma_pci_dev *xpdev);\nint xpdev_create_interfaces(struct xdma_pci_dev *xpdev);\n\nint bridge_mmap(struct file *file, struct vm_area_struct *vma);\n\n#endif /* __XDMA_CHRDEV_H__ */\n"
  },
  {
    "path": "drivers/awsf1portal/xdma_ioctl.h",
    "content": "/*******************************************************************************\n *\n * Xilinx XDMA IP Core Linux Driver\n *\n * Copyright(c) Sidebranch.\n * Copyright(c) Xilinx, Inc.\n *\n * Karen Xie <karen.xie@xilinx.com>\n * Leon Woestenberg <leon@sidebranch.com>\n *\n ******************************************************************************/\n#ifndef _XDMA_IOCALLS_POSIX_H_\n#define _XDMA_IOCALLS_POSIX_H_\n\n#include <linux/ioctl.h>\n\n/* Use 'x' as magic number */\n#define XDMA_IOC_MAGIC\t'x'\n/* XL OpenCL X->58(ASCII), L->6C(ASCII), O->0 C->C L->6C(ASCII); */\n#define XDMA_XCL_MAGIC 0X586C0C6C\n\n#define IOCTL_XDMA_PERF_V1 (1)\n#define XDMA_ADDRMODE_MEMORY (0)\n#define XDMA_ADDRMODE_FIXED (1)\n\n/*\n * S means \"Set\" through a ptr,\n * T means \"Tell\" directly with the argument value\n * G means \"Get\": reply by setting through a pointer\n * Q means \"Query\": response is on the return value\n * X means \"eXchange\": switch G and S atomically\n * H means \"sHift\": switch T and Q atomically\n *\n * _IO(type,nr)\t\t    no arguments\n * _IOR(type,nr,datatype)   read data from driver\n * _IOW(type,nr.datatype)   write data to driver\n * _IORW(type,nr,datatype)  read/write data\n *\n * _IOC_DIR(nr)\t\t    returns direction\n * _IOC_TYPE(nr)\t    returns magic\n * _IOC_NR(nr)\t\t    returns number\n * _IOC_SIZE(nr)\t    returns size\n */\n\nenum XDMA_IOC_TYPES {\n\tXDMA_IOC_NOP,\n\tXDMA_IOC_INFO,\n\tXDMA_IOC_MAX\n};\n\nstruct xdma_ioc_base {\n\tunsigned int magic;\n\tunsigned int command;\n};\n\nstruct xdma_ioc_info {\n\tstruct xdma_ioc_base base;\n\tunsigned short\t     vendor;\n\tunsigned short\t     device;\n\tunsigned short\t     subsystem_vendor;\n\tunsigned short\t     subsystem_device;\n\tunsigned             dma_engine_version;\n\tunsigned             driver_version;\n\tunsigned long long   feature_id;\n\tunsigned short\t     domain;\n\tunsigned char\t     bus;\n\tunsigned char\t     dev;\n\tunsigned char\t     func;\n};\n\n/* IOCTL codes */\n#define XDMA_IOCINFO\t\t_IOWR(XDMA_IOC_MAGIC, XDMA_IOC_INFO,\t\t\tstruct xdma_ioc_info)\n\n#define IOCTL_XDMA_ADDRMODE_SET\t_IOW('q', 4, int)\n#define IOCTL_XDMA_ADDRMODE_GET\t_IOR('q', 5, int)\n#define IOCTL_XDMA_ALIGN_GET\t_IOR('q', 6, int)\n\n#endif /* _XDMA_IOCALLS_POSIX_H_ */\n"
  },
  {
    "path": "drivers/awsf1portal/xdma_mod.c",
    "content": "/*******************************************************************************\n *\n * Xilinx XDMA IP Core Linux Driver\n * Copyright(c) 2015 - 2017 Xilinx, Inc.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms and conditions of the GNU General Public License,\n * version 2, as published by the Free Software Foundation.\n *\n * This program is distributed in the hope it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\n * more details.\n *\n * You should have received a copy of the GNU General Public License along\n * with this program.  If not, see <http://www.gnu.org/licenses/>.\n *\n * The full GNU General Public License is included in this distribution in\n * the file called \"LICENSE\".\n *\n * Karen Xie <karen.xie@xilinx.com>\n *\n ******************************************************************************/\n#define pr_fmt(fmt)     KBUILD_MODNAME \":%s: \" fmt, __func__\n\n#include <linux/ioctl.h>\n#include <linux/types.h>\n#include <linux/errno.h>\n#include <linux/aer.h>\n/* include early, to verify it depends only on the headers above */\n#include \"libxdma_api.h\"\n#include \"libxdma.h\"\n#include \"xdma_mod.h\"\n#include \"xdma_cdev.h\"\n#include \"version.h\"\n\n#define DRV_MODULE_NAME\t\t\"xdma\"\n#define DRV_MODULE_DESC\t\t\"Xilinx XDMA Classic Driver\"\n#define DRV_MODULE_RELDATE\t\"Feb. 2017\"\n\nstatic char version[] =\n\tDRV_MODULE_DESC \" \" DRV_MODULE_NAME \" v\" DRV_MODULE_VERSION \"\\n\";\n\nMODULE_AUTHOR(\"Xilinx, Inc.\");\nMODULE_DESCRIPTION(DRV_MODULE_DESC);\nMODULE_VERSION(DRV_MODULE_VERSION);\nMODULE_LICENSE(\"GPL v2\");\n\n/* SECTION: Module global variables */\nstatic int xpdev_cnt = 0;\n\nstatic const struct pci_device_id pci_ids[] = {\n\t{ PCI_DEVICE(0x10ee, 0x903f), },\n\t{ PCI_DEVICE(0x10ee, 0x9038), },\n\t{ PCI_DEVICE(0x10ee, 0x9028), },\n        { PCI_DEVICE(0x10ee, 0x9018), },\n\t{ PCI_DEVICE(0x10ee, 0x9034), },\n\t{ PCI_DEVICE(0x10ee, 0x9024), },\n        { PCI_DEVICE(0x10ee, 0x9014), },\n\t{ PCI_DEVICE(0x10ee, 0x9032), },\n\t{ PCI_DEVICE(0x10ee, 0x9022), },\n        { PCI_DEVICE(0x10ee, 0x9012), },\n\t{ PCI_DEVICE(0x10ee, 0x9031), },\n\t{ PCI_DEVICE(0x10ee, 0x9021), },\n        { PCI_DEVICE(0x10ee, 0x9011), },\n\n\t{ PCI_DEVICE(0x10ee, 0x8011), },\n\t{ PCI_DEVICE(0x10ee, 0x8012), },\n        { PCI_DEVICE(0x10ee, 0x8014), },\n        { PCI_DEVICE(0x10ee, 0x8018), },\n        { PCI_DEVICE(0x10ee, 0x8021), },\n        { PCI_DEVICE(0x10ee, 0x8022), },\n        { PCI_DEVICE(0x10ee, 0x8024), },\n        { PCI_DEVICE(0x10ee, 0x8028), },\n        { PCI_DEVICE(0x10ee, 0x8031), },\n        { PCI_DEVICE(0x10ee, 0x8032), },\n        { PCI_DEVICE(0x10ee, 0x8034), },\n        { PCI_DEVICE(0x10ee, 0x8038), },\n\n        { PCI_DEVICE(0x10ee, 0x7011), },\n        { PCI_DEVICE(0x10ee, 0x7012), },\n        { PCI_DEVICE(0x10ee, 0x7014), },\n        { PCI_DEVICE(0x10ee, 0x7018), },\n        { PCI_DEVICE(0x10ee, 0x7021), },\n        { PCI_DEVICE(0x10ee, 0x7022), },\n        { PCI_DEVICE(0x10ee, 0x7024), },\n\t{ PCI_DEVICE(0x10ee, 0x7028), },\n        { PCI_DEVICE(0x10ee, 0x7031), },\n        { PCI_DEVICE(0x10ee, 0x7032), },\n        { PCI_DEVICE(0x10ee, 0x7034), },\n        { PCI_DEVICE(0x10ee, 0x7038), },\n\n\t{ PCI_DEVICE(0x10ee, 0x6828), },\n\t{ PCI_DEVICE(0x10ee, 0x6830), },\n\t{ PCI_DEVICE(0x10ee, 0x6928), },\n\t{ PCI_DEVICE(0x10ee, 0x6930), },\n\t{ PCI_DEVICE(0x10ee, 0x6A28), },\n\t{ PCI_DEVICE(0x10ee, 0x6A30), },\n\t{ PCI_DEVICE(0x10ee, 0x6D30), },\n\n\t{ PCI_DEVICE(0x10ee, 0x4808), },\n\t{ PCI_DEVICE(0x10ee, 0x4828), },\n\t{ PCI_DEVICE(0x10ee, 0x4908), },\n\t{ PCI_DEVICE(0x10ee, 0x4A28), },\n\t{ PCI_DEVICE(0x10ee, 0x4B28), },\n\n\t{ PCI_DEVICE(0x10ee, 0x2808), },\n\n\t{ PCI_DEVICE(0x10ee, 0x2808), },\n\n    { PCI_DEVICE(0x1d0f, 0xf000), },\n    { PCI_DEVICE(0x1d0f, 0xf001), },\n\t{ PCI_DEVICE(0x1d0f, 0x1042), },\n\n\t// Connectal via PCIE\n\t{ PCI_DEVICE(0x1be7, 0xc100), },\n\n\t{0,}\n};\nMODULE_DEVICE_TABLE(pci, pci_ids);\n\nstatic void xpdev_free(struct xdma_pci_dev *xpdev)\n{\n\tstruct xdma_dev *xdev = xpdev->xdev;\n\n\tpr_info(\"xpdev 0x%p, destroy_interfaces, xdev 0x%p.\\n\", xpdev, xdev);\n\txpdev_destroy_interfaces(xpdev);\n\txpdev->xdev = NULL;\n\tpr_info(\"xpdev 0x%p, xdev 0x%p xdma_device_close.\\n\", xpdev, xdev);\n\txdma_device_close(xpdev->pdev, xdev);\n\txpdev_cnt--;\n\n\tkfree(xpdev);\n}\n\nstatic struct xdma_pci_dev *xpdev_alloc(struct pci_dev *pdev)\n{\n\tstruct xdma_pci_dev *xpdev = kmalloc(sizeof(*xpdev), GFP_KERNEL);\t\n\n\tif (!xpdev)\n\t\treturn NULL;\n\tmemset(xpdev, 0, sizeof(*xpdev));\n\n\txpdev->magic = MAGIC_DEVICE;\n\txpdev->pdev = pdev;\n\txpdev->user_max = MAX_USER_IRQ;\n\txpdev->h2c_channel_max = XDMA_CHANNEL_NUM_MAX;\n\txpdev->c2h_channel_max = XDMA_CHANNEL_NUM_MAX;\n\n\txpdev_cnt++;\n\treturn xpdev;\n}\n\nstatic int probe_one(struct pci_dev *pdev, const struct pci_device_id *id)\n{\n\tint rv = 0;\n\tstruct xdma_pci_dev *xpdev = NULL;\n\tstruct xdma_dev *xdev;\n\tvoid *hndl;\n\n\txpdev = xpdev_alloc(pdev);\n\tif (!xpdev)\n\t\treturn -ENOMEM;\n\n\thndl = xdma_device_open(DRV_MODULE_NAME, pdev, &xpdev->user_max,\n\t\t\t&xpdev->h2c_channel_max, &xpdev->c2h_channel_max);\n\tif (!hndl)\n\t\treturn -EINVAL;\n\n\tBUG_ON(xpdev->user_max > MAX_USER_IRQ);\n\tBUG_ON(xpdev->h2c_channel_max > XDMA_CHANNEL_NUM_MAX);\n\tBUG_ON(xpdev->c2h_channel_max > XDMA_CHANNEL_NUM_MAX);\n\n\tif (!xpdev->h2c_channel_max && !xpdev->c2h_channel_max)\n\t\tpr_warn(\"NO engine found!\\n\");\n\n\tif (xpdev->user_max) {\n\t\tu32 mask = (1 << (xpdev->user_max + 1)) - 1;\n\n\t\trv = xdma_user_isr_enable(hndl, mask);\n\t\tif (rv)\n\t\t\tgoto err_out;\n\t}\n\n\t/* make sure no duplicate */\n\txdev = xdev_find_by_pdev(pdev);\n\tif (!xdev) {\n\t\tpr_warn(\"NO xdev found!\\n\");\n\t\treturn -EINVAL;\n\t}\n\tBUG_ON(hndl != xdev );\n\n\tpr_info(\"%s xdma%d, pdev 0x%p, xdev 0x%p, 0x%p, usr %d, ch %d,%d.\\n\",\n\t\tdev_name(&pdev->dev), xdev->idx, pdev, xpdev, xdev,\n\t\txpdev->user_max, xpdev->h2c_channel_max,\n\t\txpdev->c2h_channel_max);\n\n\txpdev->xdev = hndl;\n\n\trv = xpdev_create_interfaces(xpdev);\n\tif (rv)\n\t\tgoto err_out;\n\n\trv = pcieportal_board_activate(1, &xpdev->portal_board, xpdev, pdev);\n\tif (rv)\n\t\tgoto err_out;\n\n        dev_set_drvdata(&pdev->dev, xpdev);\n\n\treturn 0;\n\nerr_out:\t\n\tpr_err(\"pdev 0x%p, err %d.\\n\", pdev, rv);\n\txpdev_free(xpdev);\n\treturn rv;\n}\n\nstatic void remove_one(struct pci_dev *pdev)\n{\n\tstruct xdma_pci_dev *xpdev;\n\n\tif (!pdev)\n\t\treturn;\n\n\txpdev = dev_get_drvdata(&pdev->dev);\n\tif (!xpdev)\n\t\treturn;\n\n\tpcieportal_board_activate(0, &xpdev->portal_board, xpdev, pdev);\n\n\tpr_info(\"pdev 0x%p, xdev 0x%p, 0x%p.\\n\",\n\t\tpdev, xpdev, xpdev->xdev);\n\txpdev_free(xpdev);\n\n        dev_set_drvdata(&pdev->dev, NULL);\n}\n\nstatic pci_ers_result_t xdma_error_detected(struct pci_dev *pdev,\n\t\t\t\t\tpci_channel_state_t state)\n{\n\tstruct xdma_pci_dev *xpdev = dev_get_drvdata(&pdev->dev);\n\n\tswitch (state) {\n\tcase pci_channel_io_normal:\n\t\treturn PCI_ERS_RESULT_CAN_RECOVER;\n\tcase pci_channel_io_frozen:\n\t\tpr_warn(\"dev 0x%p,0x%p, frozen state error, reset controller\\n\",\n\t\t\tpdev, xpdev);\n\t\txdma_device_offline(pdev, xpdev->xdev);\n\t\tpci_disable_device(pdev);\n\t\treturn PCI_ERS_RESULT_NEED_RESET;\n\tcase pci_channel_io_perm_failure:\n\t\tpr_warn(\"dev 0x%p,0x%p, failure state error, req. disconnect\\n\",\n\t\t\tpdev, xpdev);\n\t\treturn PCI_ERS_RESULT_DISCONNECT;\n\t}\n\treturn PCI_ERS_RESULT_NEED_RESET;\n}\n\nstatic pci_ers_result_t xdma_slot_reset(struct pci_dev *pdev)\n{\n\tstruct xdma_pci_dev *xpdev = dev_get_drvdata(&pdev->dev);\n\n\tpr_info(\"0x%p restart after slot reset\\n\", xpdev);\n\tif (pci_enable_device_mem(pdev)) {\n\t\tpr_info(\"0x%p failed to renable after slot reset\\n\", xpdev);\n\t\treturn PCI_ERS_RESULT_DISCONNECT;\n\t}\n\n\tpci_set_master(pdev);\n\tpci_restore_state(pdev);\n\tpci_save_state(pdev);\n\txdma_device_online(pdev, xpdev->xdev);\n\n\treturn PCI_ERS_RESULT_RECOVERED;\n}\n\nstatic void xdma_error_resume(struct pci_dev *pdev)\n{\n\tstruct xdma_pci_dev *xpdev = dev_get_drvdata(&pdev->dev);\n\n\tpr_info(\"dev 0x%p,0x%p.\\n\", pdev, xpdev);\n#if LINUX_VERSION_CODE < KERNEL_VERSION(5,7,0) && !(defined(RHEL_MAJOR) && RHEL_RELEASE_VERSION(8,3) >= RHEL_RELEASE_CODE)\n\tpci_cleanup_aer_uncorrect_error_status(pdev);\n#else\n\tpci_aer_clear_nonfatal_status(pdev);\n#endif\n}\n\n#if LINUX_VERSION_CODE >= KERNEL_VERSION(4,13,0)\nstatic void xdma_reset_prepare(struct pci_dev *pdev)\n{\n\tstruct xdma_pci_dev *xpdev = dev_get_drvdata(&pdev->dev);\n\n\tpr_info(\"dev 0x%p,0x%p.\\n\", pdev, xpdev);\n\txdma_device_offline(pdev, xpdev->xdev);\n}\n\nstatic void xdma_reset_done(struct pci_dev *pdev)\n{\n\tstruct xdma_pci_dev *xpdev = dev_get_drvdata(&pdev->dev);\n\n\tpr_info(\"dev 0x%p,0x%p.\\n\", pdev, xpdev);\n\txdma_device_online(pdev, xpdev->xdev);\n}\n\n#elif LINUX_VERSION_CODE >= KERNEL_VERSION(3,16,0)\nstatic void xdma_reset_notify(struct pci_dev *pdev, bool prepare)\n{\n\tstruct xdma_pci_dev *xpdev = dev_get_drvdata(&pdev->dev);\n\n\tpr_info(\"dev 0x%p,0x%p, prepare %d.\\n\", pdev, xpdev, prepare);\n\n\tif (prepare)\n\t\txdma_device_offline(pdev, xpdev->xdev);\n\telse\n\t\txdma_device_online(pdev, xpdev->xdev);\n}\n#endif\n\nstatic const struct pci_error_handlers xdma_err_handler = {\n\t.error_detected\t= xdma_error_detected,\n\t.slot_reset\t= xdma_slot_reset,\n\t.resume\t\t= xdma_error_resume,\n#if LINUX_VERSION_CODE >= KERNEL_VERSION(4,13,0)\n\t.reset_prepare\t= xdma_reset_prepare,\n\t.reset_done\t= xdma_reset_done,\n#elif LINUX_VERSION_CODE >= KERNEL_VERSION(3,16,0)\n\t.reset_notify\t= xdma_reset_notify,\n#endif\n};\n\nstatic struct pci_driver pci_driver = {\n\t.name = DRV_MODULE_NAME,\n\t.id_table = pci_ids,\n\t.probe = probe_one,\n\t.remove = remove_one,\n\t.err_handler = &xdma_err_handler,\n};\n\nstatic int __init xdma_mod_init(void)\n{\n\tint rv;\n\textern unsigned int desc_blen_max;\n\textern unsigned int sgdma_timeout;\n\n\tpr_info(\"%s\", version);\n\n\tif (desc_blen_max > XDMA_DESC_BLEN_MAX)\n\t\tdesc_blen_max = XDMA_DESC_BLEN_MAX;\n\tpr_info(\"desc_blen_max: 0x%x/%u, sgdma_timeout: %u sec.\\n\",\n\t\tdesc_blen_max, desc_blen_max, sgdma_timeout);\n\n\trv = xdma_cdev_init();\n\tif (rv < 0)\n\t\treturn rv;\n\n\treturn pci_register_driver(&pci_driver);\n}\n\nstatic void __exit xdma_mod_exit(void)\n{\n\t/* unregister this driver from the PCI bus driver */\n\tdbg_init(\"pci_unregister_driver.\\n\");\n\tpci_unregister_driver(&pci_driver);\n\txdma_cdev_cleanup();\n}\n\nmodule_init(xdma_mod_init);\nmodule_exit(xdma_mod_exit);\n"
  },
  {
    "path": "drivers/awsf1portal/xdma_mod.h",
    "content": "/*******************************************************************************\n *\n * Xilinx XDMA IP Core Linux Driver\n * Copyright(c) 2015 - 2017 Xilinx, Inc.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms and conditions of the GNU General Public License,\n * version 2, as published by the Free Software Foundation.\n *\n * This program is distributed in the hope it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\n * more details.\n *\n * You should have received a copy of the GNU General Public License along\n * with this program.  If not, see <http://www.gnu.org/licenses/>.\n *\n * The full GNU General Public License is included in this distribution in\n * the file called \"LICENSE\".\n *\n * Karen Xie <karen.xie@xilinx.com>\n *\n ******************************************************************************/\n#ifndef __XDMA_MODULE_H__\n#define __XDMA_MODULE_H__\n\n#include <linux/types.h>\n#include <linux/module.h>\n#include <linux/cdev.h>\n#include <linux/dma-mapping.h>\n#include <linux/delay.h>\n#include <linux/fb.h>\n#include <linux/fs.h>\n#include <linux/init.h>\n#include <linux/interrupt.h>\n#include <linux/io.h>\n#include <linux/jiffies.h>\n#include <linux/kernel.h>\n#include <linux/mm.h>\n#include <linux/mm_types.h>\n#include <linux/poll.h>\n#include <linux/pci.h>\n#include <linux/sched.h>\n#include <linux/slab.h>\n#include <linux/vmalloc.h>\n#include <linux/workqueue.h>\n#include <linux/aio.h>\n#include <linux/splice.h>\n#include <linux/version.h>\n#include <linux/uio.h>\n\n#include \"libxdma.h\"\n#include \"portal_internal.h\"\n\n#define MAGIC_ENGINE\t0xEEEEEEEEUL\n#define MAGIC_DEVICE\t0xDDDDDDDDUL\n#define MAGIC_CHAR\t0xCCCCCCCCUL\n#define MAGIC_BITSTREAM 0xBBBBBBBBUL\n\nstruct xdma_cdev {\n\tunsigned long magic;\t\t/* structure ID for sanity checks */\n\tstruct xdma_pci_dev *xpdev;\n\tstruct xdma_dev *xdev;\n\tdev_t cdevno;\t\t\t/* character device major:minor */\n\tstruct cdev cdev;\t\t/* character device embedded struct */\n\tint bar;\t\t\t/* PCIe BAR for HW access, if needed */\n\tunsigned long base;\t\t/* bar access offset */\n\tstruct xdma_engine *engine;\t/* engine instance, if needed */\n\tstruct xdma_user_irq *user_irq;\t/* IRQ value, if needed */\n\tstruct device *sys_device;\t/* sysfs device */\n\tspinlock_t lock;\n};\n\n/* XDMA PCIe device specific book-keeping */\nstruct xdma_pci_dev {\n\tunsigned long magic;\t\t/* structure ID for sanity checks */\n\tstruct pci_dev *pdev;\t/* pci device struct from probe() */\n\tstruct xdma_dev *xdev;\n\tint major;\t\t/* major number */\n\tint instance;\t\t/* instance number */\n\tint user_max;\n\tint c2h_channel_max;\n\tint h2c_channel_max;\n\n\tunsigned int flags;\n\t/* character device structures */\n\tstruct xdma_cdev ctrl_cdev;\n\tstruct xdma_cdev sgdma_c2h_cdev[XDMA_CHANNEL_NUM_MAX];\n\tstruct xdma_cdev sgdma_h2c_cdev[XDMA_CHANNEL_NUM_MAX];\n\tstruct xdma_cdev events_cdev[16];\n\n\tstruct xdma_cdev user_cdev;\n\tstruct xdma_cdev bypass_c2h_cdev[XDMA_CHANNEL_NUM_MAX];\n\tstruct xdma_cdev bypass_h2c_cdev[XDMA_CHANNEL_NUM_MAX];\n\tstruct xdma_cdev bypass_cdev_base;\n\n\tstruct xdma_cdev xvc_cdev;\n\n\tstruct tBoard portal_board;\n\n\tvoid *data;\n};\n\nstruct xdma_io_cb {\n\tvoid __user *buf;\n\tsize_t len;\n\tunsigned int pages_nr;\n\tstruct sg_table sgt;\n\tstruct page **pages;\n};\n\n#endif /* ifndef __XDMA_MODULE_H__ */\n"
  },
  {
    "path": "drivers/connectalsdhci/Makefile",
    "content": "\nV?=0\nifeq ($(V),0)\nQ=@\nelse\nQ=\nendif\nCONNECTALDIR ?= $(PWD)/../..\ninclude $(CONNECTALDIR)/Makefile.version\n\nobj-m += connectalsdhci.o\n\nCROSS_COMPILE?=arm-linux-gnueabi-\n\nccflags-y := -I$(src)/../portalmem -I$(src)/../../cpp -I$(PWD)/../.. -I$(src)/../../generated/cpp \\\n\t-DDRIVER_VERSION=\"KBUILD_STR($(VERSION))\"\n\nconnectalsdhci.ko: connectalsdhci.c\n\t@$(MAKE) ARCH=arm CROSS_COMPILE=$(CROSS_COMPILE) -C $(KROOT) xilinx_zynq_portal_defconfig\n\t@$(MAKE) ARCH=arm CROSS_COMPILE=$(CROSS_COMPILE) -C $(KROOT) oldconfig\n\t@$(MAKE) -j 8 ARCH=arm CROSS_COMPILE=$(CROSS_COMPILE) -C $(KROOT) zImage\n\t@$(MAKE) ARCH=arm CROSS_COMPILE=$(CROSS_COMPILE) -C $(KROOT) M=$(PWD) modules\n\nclean:\n\t@$(MAKE) ARCH=arm CROSS_COMPILE=$(CROSS_COMPILE) -C $(KROOT) M=$(PWD) clean\n"
  },
  {
    "path": "drivers/connectalsdhci/connectalsdhci.c",
    "content": "/*\n * Based on sdhci-of-xilinx.c\n *\n * Copyright (c) 2015 Quanta Research Cambridge Inc.\n *\n * This file is licensed under the terms of the GNU General Public License\n * version 2.  This program is licensed \"as is\" without any warranty of any\n * kind, whether express or implied.\n */\n\n#include <linux/module.h>\n#include <linux/platform_device.h>\n#include <asm/io.h>\n#include <linux/clk.h>\n\n// defined in drivers/mmc/host/sdhci-of-xilinxps.c\nextern int sdhci_zynq_remove(struct platform_device *pdev);\nextern int sdhci_zynq_probe(struct platform_device *pdev);\nextern int xsdhcips_suspend(struct device *dev);\nextern int xsdhcips_resume(struct device *dev);\n\n#ifdef CONFIG_PM_SLEEP\nstatic const struct dev_pm_ops xsdhcips_dev_pm_ops = {\n\tSET_SYSTEM_SLEEP_PM_OPS(xsdhcips_suspend, xsdhcips_resume)\n};\n#define XSDHCIPS_PM\t(&xsdhcips_dev_pm_ops)\n#else /* ! CONFIG_PM_SLEEP */\n#define XSDHCIPS_PM\tNULL\n#endif /* ! CONFIG_PM_SLEEP */\n\nstatic const struct of_device_id sdhci_zynq_of_match[] = {\n\t{ .compatible = \"connectalsdhci\" },\n\t{},\n};\nMODULE_DEVICE_TABLE(of, sdhci_zynq_of_match);\n\n\nstatic struct platform_driver sdhci_zynq_driver = {\n\t.driver = {\n\t\t.name = \"connectalsdhci-zynq\",\n\t\t.owner = THIS_MODULE,\n\t\t.of_match_table = sdhci_zynq_of_match,\n\t\t.pm = XSDHCIPS_PM,\n\t},\n\t.probe = local_zynq_probe,\n\t.remove = local_zynq_remove,\n};\n\nmodule_platform_driver(sdhci_zynq_driver);\nMODULE_LICENSE(\"GPL v2\");\n"
  },
  {
    "path": "drivers/connectalspi/Makefile",
    "content": "\nV?=0\nifeq ($(V),0)\nQ=@\nelse\nQ=\nendif\nCONNECTALDIR ?= $(PWD)/../..\ninclude $(CONNECTALDIR)/Makefile.version\n\nobj-m += connectalspi.o\n\nCROSS_COMPILE?=arm-linux-gnueabi-\n\nccflags-y := -I$(src)/../portalmem -I$(src)/../../cpp -I$(PWD)/../.. -I$(src)/../../generated/cpp \\\n\t-DDRIVER_VERSION=\"KBUILD_STR($(VERSION))\"\n\nconnectalspi.ko: connectalspi.c\n\t@$(MAKE) ARCH=arm CROSS_COMPILE=$(CROSS_COMPILE) -C $(KROOT) xilinx_zynq_portal_defconfig\n\t@$(MAKE) ARCH=arm CROSS_COMPILE=$(CROSS_COMPILE) -C $(KROOT) oldconfig\n\t@$(MAKE) -j 8 ARCH=arm CROSS_COMPILE=$(CROSS_COMPILE) -C $(KROOT) zImage\n\t@$(MAKE) ARCH=arm CROSS_COMPILE=$(CROSS_COMPILE) -C $(KROOT) M=$(PWD) modules\n\nclean:\n\t@$(MAKE) ARCH=arm CROSS_COMPILE=$(CROSS_COMPILE) -C $(KROOT) M=$(PWD) clean\n"
  },
  {
    "path": "drivers/connectalspi/connectalspi.c",
    "content": "/*\n * Based on spi-xilinx-ps.c\n *\n * Copyright (c) 2015 Quanta Research Cambridge Inc.\n *\n * This file is licensed under the terms of the GNU General Public License\n * version 2.  This program is licensed \"as is\" without any warranty of any\n * kind, whether express or implied.\n */\n\n#include <linux/module.h>\n#include <linux/platform_device.h>\n#include <asm/io.h>\n#include <linux/clk.h>\n\n//#define POKE_REG_ONLY\n\n// defined in drivers/spi/spi-xilinx-ps.c\nextern int xspips_remove(struct platform_device *pdev);\nextern int xspips_probe(struct platform_device *pdev);\nextern int xspips_suspend(struct device *dev);\nextern int xspips_resume(struct device *dev);\n\n#define XPSS_SYS_CTRL_BASEADDR    0xF8000000\n\n// SLCR\n#define XSLCR_MIO_PIN_00_OFFSET    0x700 /* MIO PIN0 control register */\n#define XSLCR_MIO_L0_SHIFT             1\n#define XSLCR_MIO_L1_SHIFT             2\n#define XSLCR_MIO_L2_SHIFT             3\n#define XSLCR_MIO_L3_SHIFT             5\n#define XSLCR_MIO_LMASK             0xFE\n#define XSLCR_MIO_PIN_XX_TRI_ENABLE    1\n#define XSLCR_MIO_PIN_GPIO_ENABLE   (0x00 << XSLCR_MIO_L3_SHIFT)\n#define XSLCR_MIO_PIN_SDIO_ENABLE   (0x04 << XSLCR_MIO_L3_SHIFT)\n#define XSLCR_MIO_PIN_SPI_ENABLE    (0x05 << XSLCR_MIO_L3_SHIFT)\n\n#define PINOFF(PIN) (XPSS_SYS_CTRL_BASEADDR + XSLCR_MIO_PIN_00_OFFSET + (PIN) * 4)\n\nstatic const struct {\n  uint32_t pinaddr;\n  uint32_t enable;\n} spi0_pindef[] = {\n\n  {PINOFF(16), XSLCR_MIO_PIN_SPI_ENABLE},\n  {PINOFF(17), XSLCR_MIO_PIN_SPI_ENABLE},\n  {PINOFF(18), XSLCR_MIO_PIN_SPI_ENABLE},\n  {PINOFF(19), XSLCR_MIO_PIN_SPI_ENABLE},\n  {PINOFF(20), XSLCR_MIO_PIN_SPI_ENABLE},\n  {PINOFF(21), XSLCR_MIO_PIN_SPI_ENABLE},\n\n  {PINOFF(28), XSLCR_MIO_PIN_SPI_ENABLE},\n  {PINOFF(29), XSLCR_MIO_PIN_SPI_ENABLE},\n  {PINOFF(30), XSLCR_MIO_PIN_SPI_ENABLE},\n  {PINOFF(31), XSLCR_MIO_PIN_SPI_ENABLE},\n  {PINOFF(32), XSLCR_MIO_PIN_SPI_ENABLE},\n  {PINOFF(33), XSLCR_MIO_PIN_SPI_ENABLE},\n\n  {PINOFF(40), XSLCR_MIO_PIN_SPI_ENABLE},\n  {PINOFF(41), XSLCR_MIO_PIN_SPI_ENABLE},\n  {PINOFF(42), XSLCR_MIO_PIN_SPI_ENABLE},\n  {PINOFF(43), XSLCR_MIO_PIN_SPI_ENABLE},\n  {PINOFF(44), XSLCR_MIO_PIN_SPI_ENABLE},\n  {PINOFF(45), XSLCR_MIO_PIN_SPI_ENABLE},\n\n  {0,0}};\n\n\nuint32_t bit_sel(uint32_t lsb, uint32_t msb, uint32_t v)\n{\n  return (v >> lsb) & ~(~0 << (msb-lsb+1));\n}\n\nstatic int local_probe(struct platform_device *pdev)\n{\n  uint32_t ind = 0;\n  uint32_t pinaddr = 0;\n  int rv = 0;\n#ifndef POKE_REG_ONLY\n  rv = xspips_probe(pdev);\n#endif\n\n  while ((pinaddr = spi0_pindef[ind].pinaddr)) {\n    // u32 en = spi0_pindef[ind].enable;\n    u32 v = readl(ioremap_nocache(pinaddr, sizeof(u32)));\n    printk(\"[%s:%d] %08x %x\\n\", __FUNCTION__, __LINE__, pinaddr, (v>>5)&7);\n    ind++;\n  }\n  {\n    struct clk *devclk = clk_get_sys(\"SPI0\", NULL);\n    printk(\"[%s:%d] devclk %x\\n\", __FUNCTION__, __LINE__, devclk);\n    printk(\"[%s:%d] rate %d\\n\", __FUNCTION__, __LINE__, clk_get_rate(devclk));\n  }\n  {\n    u32 v = readl(ioremap_nocache(0xF8000158, sizeof(u32)));\n    printk(\"[%s:%d] spi_clk_ctrl       v: %08x\\n\", __FUNCTION__, __LINE__, v);\n    printk(\"[%s:%d] spi_clk_ctrl divisor: %d\\n\", __FUNCTION__, __LINE__, bit_sel(8,13,v));\n    printk(\"[%s:%d] spi_clk_ctrl  srcsel: %d\\n\", __FUNCTION__, __LINE__, bit_sel(4,5,v));\n    printk(\"[%s:%d] spi_clk_ctrl clkact1: %d\\n\", __FUNCTION__, __LINE__, bit_sel(1,1,v));\n    printk(\"[%s:%d] spi_clk_ctrl clkact0: %d\\n\", __FUNCTION__, __LINE__, bit_sel(0,0,v));\n  }\n\n  {\n    u32 v = readl(ioremap_nocache(0xF800012C, sizeof(u32)));\n    printk(\"[%s:%d] aper_clk_ctrl       v: %08x\\n\", __FUNCTION__, __LINE__, v);\n    printk(\"[%s:%d] aper_clk_ctrl spi1_cpu_1xclkact: %08x\\n\", __FUNCTION__, __LINE__, bit_sel(15,15,v));\n    printk(\"[%s:%d] aper_clk_ctrl spi0_cpu_1xclkact: %08x\\n\", __FUNCTION__, __LINE__, bit_sel(14,14,v));\n  }\n  {\n    u32 v = readl(ioremap_nocache(0xE0006000, sizeof(u32)));\n    printk(\"[%s:%d] spi_config_reg0     v: %08x\\n\", __FUNCTION__, __LINE__, v);\n    printk(\"[%s:%d] spi_config_reg0  baud_rate_div: %08x\\n\", __FUNCTION__, __LINE__, bit_sel(3,5,v));\n  }\n  return rv;  \n}\nstatic int local_remove(struct platform_device *pdev)\n{\n  printk(\"[%s:%d] v %x\\n\", __FUNCTION__, __LINE__);\n#ifndef POKE_REG_ONLY\n  return xspips_remove(pdev);\n#else\n  return 0;\n#endif\n}\n\n#ifdef CONFIG_PM_SLEEP\nstatic const struct dev_pm_ops xspips_dev_pm_ops = {\n\tSET_SYSTEM_SLEEP_PM_OPS(xspips_suspend, xspips_resume)\n};\n#define XSPIPS_PM\t(&xspips_dev_pm_ops)\n#else /* ! CONFIG_PM_SLEEP */\n#define XSPIPS_PM\tNULL\n#endif /* ! CONFIG_PM_SLEEP */\n\nstatic struct of_device_id xspips_of_match[] = {\n\t{ .compatible = \"connectalspi\", },\n\t{ /* end of table */}\n};\nMODULE_DEVICE_TABLE(of, xspips_of_match);\n\n/*\n * xspips_driver - This structure defines the SPI subsystem platform driver\n */\nstatic struct platform_driver xspips_driver = {\n\t.probe\t= local_probe,\n\t.remove\t= local_remove,\n\t.driver = {\n\t\t.name = \"connectalspi-zynq\",\n\t\t.owner = THIS_MODULE,\n\t\t.of_match_table = xspips_of_match,\n\t\t.pm = XSPIPS_PM,\n\t},\n};\n\nmodule_platform_driver(xspips_driver);\nMODULE_LICENSE(\"GPL\");\n"
  },
  {
    "path": "drivers/pcieportal/Makefile",
    "content": "\n# On Centos: sudo yum install kernel-headers\n\nV?=0\nifeq ($(V),0)\nQ=@\nelse\nQ=\nendif\nCURRENTDIR := $(PWD)\nCONNECTALDIR ?= $(CURRENTDIR)/../..\ninclude $(CONNECTALDIR)/Makefile.version\n\nobj-m += pcieportal.o\n\nPKG_NAME?=connectal\n# DKMS only looks in /usr/src\nPREFIX?=/usr\nKVERSION=$(shell uname -r)\nKROOT=/lib/modules/$(KVERSION)/build\nexport BS_MOD_DIR=$(DESTDIR)/lib/modules/$(KVERSION)/connectal\n\n.PHONY: default\ndefault: pcieportal.ko ../portalmem/portalmem.ko\n\nEXTRA_CFLAGS := -I$(CONNECTALDIR)/drivers/pciportal -I$(CONNECTALDIR)/cpp -I$(CONNECTALDIR) -I$(CONNECTALDIR)/drivers/portalmem -I$(CONNECTALDIR)/generated/cpp\ncflags-y += -I$(PWD)\n\n../portalmem/portalmem.ko: ../portalmem/portalmem.c\n\tcd ../portalmem; make\n\ndriverversion.h:\n\tVERSION=$(VERSION) echo \"#define DRIVER_VERSION \\\"$$VERSION\\\"\" > driverversion.h\n\npcieportal.ko: pcieportal.c pcieportal.h driverversion.h\n\t$(Q)$(MAKE) -C $(KROOT) M=$(PWD) modules\n\n.PHONY: modules_check\nmodules_check:\n\t$(Q)$(MAKE) -C $(KROOT) C=2 M=$(PWD) modules\n\n.PHONY: install\ninstall: pcieportal.ko\n\tinstall -d -m755 $(BS_MOD_DIR)\n\tinstall -m644 pcieportal.ko $(BS_MOD_DIR)\n\tinstall -m644 ../portalmem/portalmem.ko $(BS_MOD_DIR)\nifeq (\"$(DESTDIR)\", \"\")\n\tdepmod\nendif\n\n.PHONY: uninstall\nuninstall:\n\trm -f $(BS_MOD_DIR)/pcieportal.ko\n\trmdir --ignore-fail-on-non-empty $(BS_MOD_DIR)\nifeq (\"$(DESTDIR)\", \"\")\n\tdepmod\nendif\n\n.PHONY: clean\nclean:\n\t$(Q)$(MAKE) -C $(KROOT) M=$(PWD) clean\n\tcd ../portalmem; make clean\n\n.PHONY: distclean\ndistclean: clean\n\n.PHONY: rmmod\nrmmod:\n\trmmod portalmem || true\n\trmmod pcieportal || true\n\n.PHONY: insmod\ninsmod: rmmod\n\tinsmod pcieportal.ko\n\t-chmod agu+rw /dev/portal*\n\tinsmod ../portalmem/portalmem.ko\n\tchmod agu+rw /dev/portalmem\n\n.PHONY: install-dkms\ninstall-dkms:\n\trm -f driverversion.h\n\tmake driverversion.h\n\tmkdir -p $(DESTDIR)$(PREFIX)/src/$(PKG_NAME)-$(VERSION)\n\tsed \"s/@VERSION@/$(VERSION)/\" dkms.conf | sed \"s/@PKG_NAME@/$(PKG_NAME)/\" > dkms.conf.out\n\tsed \"s/@VERSION@/$(VERSION)/\" Makefile.dkms > Makefile.dkms.out\n\tcp -fv dkms.conf.out $(DESTDIR)$(PREFIX)/src/$(PKG_NAME)-$(VERSION)/dkms.conf\n\tcp -fv Makefile.dkms.out $(DESTDIR)$(PREFIX)/src/$(PKG_NAME)-$(VERSION)/Makefile\n\tcp -fv pcieportal.c pcieportal.h driverversion.h $(DESTDIR)$(PREFIX)/src/$(PKG_NAME)-$(VERSION)\n\tcp -fv ../../cpp/*.[ch] ../portalmem/*.[ch] \\\n\t../../generated/cpp/*.[ch] \\\n\t$(DESTDIR)$(PREFIX)/src/$(PKG_NAME)-$(VERSION)\n\tsed -i 's|drivers/portalmem/||' $(DESTDIR)$(PREFIX)/src/$(PKG_NAME)-$(VERSION)/*.[ch]\n\tsed -i 's|drivers/pcieportal/||' $(DESTDIR)$(PREFIX)/src/$(PKG_NAME)-$(VERSION)/*.[ch]\n\tsed -i 's|drivers/zynqportal/||' $(DESTDIR)$(PREFIX)/src/$(PKG_NAME)-$(VERSION)/*.[ch]\n\tsed -i 's|../../cpp/||g' $(DESTDIR)$(PREFIX)/src/$(PKG_NAME)-$(VERSION)/*.[ch]\n"
  },
  {
    "path": "drivers/pcieportal/Makefile.dkms",
    "content": "obj-m += pcieportal.o\nobj-m += portalmem.o\n\npcieportal.ko: driverversion.h\n\ndriverversion.h:\n\techo \"#define DRIVER_VERSION \\\"@VERSION@\\\"\" > driverversion.h\n"
  },
  {
    "path": "drivers/pcieportal/dkms.conf",
    "content": "PACKAGE_NAME=\"@PKG_NAME@\"\nPACKAGE_VERSION=\"@VERSION@\"\nBUILT_MODULE_NAME[0]=\"pcieportal\"\nDEST_MODULE_LOCATION[0]=\"/extra/fpga\"\nBUILT_MODULE_NAME[1]=\"portalmem\"\nDEST_MODULE_LOCATION[1]=\"/extra/fpga\"\nAUTOINSTALL=\"yes\"\n"
  },
  {
    "path": "drivers/pcieportal/driverversion.h",
    "content": "#define DRIVER_VERSION \"\"\n"
  },
  {
    "path": "drivers/pcieportal/linux/dma-buf.h",
    "content": "/*\n * Header file for dma buffer sharing framework.\n *\n * Copyright(C) 2011 Linaro Limited. All rights reserved.\n * Author: Sumit Semwal <sumit.semwal@ti.com>\n *\n * Many thanks to linaro-mm-sig list, and specially\n * Arnd Bergmann <arnd@arndb.de>, Rob Clark <rob@ti.com> and\n * Daniel Vetter <daniel@ffwll.ch> for their support in creation and\n * refining of this idea.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of the GNU General Public License version 2 as published by\n * the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but WITHOUT\n * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\n * more details.\n *\n * You should have received a copy of the GNU General Public License along with\n * this program.  If not, see <http://www.gnu.org/licenses/>.\n */\n#ifndef __DMA_BUF_H__\n#define __DMA_BUF_H__\n\n#include <linux/file.h>\n#include <linux/err.h>\n#include <linux/scatterlist.h>\n#include <linux/list.h>\n#include <linux/dma-mapping.h>\n#include <linux/fs.h>\n\nstruct device;\nstruct dma_buf;\nstruct dma_buf_attachment;\n\n/**\n * struct dma_buf_ops - operations possible on struct dma_buf\n * @attach: [optional] allows different devices to 'attach' themselves to the\n *\t    given buffer. It might return -EBUSY to signal that backing storage\n *\t    is already allocated and incompatible with the requirements\n *\t    of requesting device.\n * @detach: [optional] detach a given device from this buffer.\n * @map_dma_buf: returns list of scatter pages allocated, increases usecount\n *\t\t of the buffer. Requires atleast one attach to be called\n *\t\t before. Returned sg list should already be mapped into\n *\t\t _device_ address space. This call may sleep. May also return\n *\t\t -EINTR. Should return -EINVAL if attach hasn't been called yet.\n * @unmap_dma_buf: decreases usecount of buffer, might deallocate scatter\n *\t\t   pages.\n * @release: release this buffer; to be called after the last dma_buf_put.\n * @begin_cpu_access: [optional] called before cpu access to invalidate cpu\n * \t\t      caches and allocate backing storage (if not yet done)\n * \t\t      respectively pin the objet into memory.\n * @end_cpu_access: [optional] called after cpu access to flush caches.\n * @kmap_atomic: maps a page from the buffer into kernel address\n * \t\t space, users may not block until the subsequent unmap call.\n * \t\t This callback must not sleep.\n * @kunmap_atomic: [optional] unmaps a atomically mapped page from the buffer.\n * \t\t   This Callback must not sleep.\n * @kmap: maps a page from the buffer into kernel address space.\n * @kunmap: [optional] unmaps a page from the buffer.\n * @mmap: used to expose the backing storage to userspace. Note that the\n * \t  mapping needs to be coherent - if the exporter doesn't directly\n * \t  support this, it needs to fake coherency by shooting down any ptes\n * \t  when transitioning away from the cpu domain.\n * @vmap: [optional] creates a virtual mapping for the buffer into kernel\n *\t  address space. Same restrictions as for vmap and friends apply.\n * @vunmap: [optional] unmaps a vmap from the buffer\n */\nstruct dma_buf_ops {\n\tint (*attach)(struct dma_buf *, struct device *,\n\t\t\tstruct dma_buf_attachment *);\n\n\tvoid (*detach)(struct dma_buf *, struct dma_buf_attachment *);\n\n\t/* For {map,unmap}_dma_buf below, any specific buffer attributes\n\t * required should get added to device_dma_parameters accessible\n\t * via dev->dma_params.\n\t */\n\tstruct sg_table * (*map_dma_buf)(struct dma_buf_attachment *,\n\t\t\t\t\t\tenum dma_data_direction);\n\tvoid (*unmap_dma_buf)(struct dma_buf_attachment *,\n\t\t\t\t\t\tstruct sg_table *,\n\t\t\t\t\t\tenum dma_data_direction);\n\t/* TODO: Add try_map_dma_buf version, to return immed with -EBUSY\n\t * if the call would block.\n\t */\n\n\t/* after final dma_buf_put() */\n\tvoid (*release)(struct dma_buf *);\n\n\tint (*begin_cpu_access)(struct dma_buf *, size_t, size_t,\n\t\t\t\tenum dma_data_direction);\n\tvoid (*end_cpu_access)(struct dma_buf *, size_t, size_t,\n\t\t\t       enum dma_data_direction);\n\tvoid *(*kmap_atomic)(struct dma_buf *, unsigned long);\n\tvoid (*kunmap_atomic)(struct dma_buf *, unsigned long, void *);\n\tvoid *(*kmap)(struct dma_buf *, unsigned long);\n\tvoid (*kunmap)(struct dma_buf *, unsigned long, void *);\n\n\tint (*mmap)(struct dma_buf *, struct vm_area_struct *vma);\n\n\tvoid *(*vmap)(struct dma_buf *);\n\tvoid (*vunmap)(struct dma_buf *, void *vaddr);\n};\n\n/**\n * struct dma_buf - shared buffer object\n * @size: size of the buffer\n * @file: file pointer used for sharing buffers across, and for refcounting.\n * @attachments: list of dma_buf_attachment that denotes all devices attached.\n * @ops: dma_buf_ops associated with this buffer object.\n * @priv: exporter specific private data for this buffer object.\n */\nstruct dma_buf {\n\tsize_t size;\n\tstruct file *file;\n\tstruct list_head attachments;\n\tconst struct dma_buf_ops *ops;\n\t/* mutex to serialize list manipulation, attach/detach and vmap/unmap */\n\tstruct mutex lock;\n\tunsigned vmapping_counter;\n\tvoid *vmap_ptr;\n\tvoid *priv;\n};\n\n/**\n * struct dma_buf_attachment - holds device-buffer attachment data\n * @dmabuf: buffer for this attachment.\n * @dev: device attached to the buffer.\n * @node: list of dma_buf_attachment.\n * @priv: exporter specific attachment data.\n *\n * This structure holds the attachment information between the dma_buf buffer\n * and its user device(s). The list contains one attachment struct per device\n * attached to the buffer.\n */\nstruct dma_buf_attachment {\n\tstruct dma_buf *dmabuf;\n\tstruct device *dev;\n\tstruct list_head node;\n\tvoid *priv;\n};\n\n/**\n * get_dma_buf - convenience wrapper for get_file.\n * @dmabuf:\t[in]\tpointer to dma_buf\n *\n * Increments the reference count on the dma-buf, needed in case of drivers\n * that either need to create additional references to the dmabuf on the\n * kernel side.  For example, an exporter that needs to keep a dmabuf ptr\n * so that subsequent exports don't create a new dmabuf.\n */\nstatic inline void get_dma_buf(struct dma_buf *dmabuf)\n{\n\tget_file(dmabuf->file);\n}\n\nstruct dma_buf_attachment *dma_buf_attach(struct dma_buf *dmabuf,\n\t\t\t\t\t\t\tstruct device *dev);\nvoid dma_buf_detach(struct dma_buf *dmabuf,\n\t\t\t\tstruct dma_buf_attachment *dmabuf_attach);\nstruct dma_buf *dma_buf_export(void *priv, const struct dma_buf_ops *ops,\n\t\t\t       size_t size, int flags);\nint dma_buf_fd(struct dma_buf *dmabuf, int flags);\nstruct dma_buf *dma_buf_get(int fd);\nvoid dma_buf_put(struct dma_buf *dmabuf);\n\nstruct sg_table *dma_buf_map_attachment(struct dma_buf_attachment *,\n\t\t\t\t\tenum dma_data_direction);\nvoid dma_buf_unmap_attachment(struct dma_buf_attachment *, struct sg_table *,\n\t\t\t\tenum dma_data_direction);\nint dma_buf_begin_cpu_access(struct dma_buf *dma_buf, size_t start, size_t len,\n\t\t\t     enum dma_data_direction dir);\nvoid dma_buf_end_cpu_access(struct dma_buf *dma_buf, size_t start, size_t len,\n\t\t\t    enum dma_data_direction dir);\nvoid *dma_buf_kmap_atomic(struct dma_buf *, unsigned long);\nvoid dma_buf_kunmap_atomic(struct dma_buf *, unsigned long, void *);\nvoid *dma_buf_kmap(struct dma_buf *, unsigned long);\nvoid dma_buf_kunmap(struct dma_buf *, unsigned long, void *);\n\nint dma_buf_mmap(struct dma_buf *, struct vm_area_struct *,\n\t\t unsigned long);\nvoid *dma_buf_vmap(struct dma_buf *);\nvoid dma_buf_vunmap(struct dma_buf *, void *vaddr);\n\n#endif /* __DMA_BUF_H__ */\n"
  },
  {
    "path": "drivers/pcieportal/pcieportal.c",
    "content": "/* Copyright (c) 2014 Quanta Research Cambridge, Inc\n *\n * Permission is hereby granted, free of charge, to any person obtaining a\n * copy of this software and associated documentation files (the \"Software\"),\n * to deal in the Software without restriction, including without limitation\n * the rights to use, copy, modify, merge, publish, distribute, sublicense,\n * and/or sell copies of the Software, and to permit persons to whom the\n * Software is furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n * DEALINGS IN THE SOFTWARE.\n */\n/*\n * Linux device driver for CONNECTAL portals on FPGAs connected via PCIe.\n */\n\n#include <linux/kernel.h>\n#include <linux/module.h>\n#include <linux/version.h>      /* LINUX_VERSION_CODE, KERNEL_VERSION */\n#include <linux/pci.h>          /* pci device types, fns, etc. */\n#include <linux/errno.h>        /* error codes */\n#include <linux/io.h>           /* I/O mapping, reading, writing */\n#include <linux/cdev.h>         /* struct cdev */\n#include <linux/fs.h>           /* struct file_operations */\n#include <linux/init.h>         /* __init, __exit, etc. */\n#include <linux/ioctl.h>        /* ioctl macros */\n#include <linux/interrupt.h>    /* request_irq, free_irq, etc. */\n#include <linux/mm.h>           /* kmalloc, kfree, struct page, etc. */\n#include <linux/sched.h>        /* task_struct */\n#include <linux/scatterlist.h>  /* sg_* operations */\n#include <linux/mutex.h>        /* mutex_lock, mutex_unlock, etc. */\n#include <linux/poll.h>         /* poll_table, etc. */\n#include <asm/uaccess.h>        /* copy_to_user, copy_from_user */\n#include <linux/dma-buf.h>\n#include \"driverversion.h\"\n\n#include \"pcieportal.h\"\n#define CONNECTAL_DRIVER_CODE\n#include \"portal.h\" // PORTAL_BASE_OFFSET\n#include \"dmaSendFd.h\"\n#include \"portalKernel.h\"\n\n/* stem used for module and device names */\n#define DEV_NAME \"portal\"\n\n#define BLUESPEC_VENDOR_ID 0x1be7\n#define AMAZON_VENDOR_ID   0x1d0f\n\n#define CONNECTAL_DEVICE_ID 0xc100\n#define AMAZON_DEVICE_ID 0xf000\n\n/* CSR address space offsets */\n#define CSR_ID                        (   0 << 2) /* 64-bit */\n#define CSR_TLPDATAFIFO_DEQ           ( 768 << 2)\n#define CSR_TLPTRACELENGTHREG         ( 774 << 2)\n#define CSR_TLPTRACINGREG             ( 775 << 2)\n#define CSR_TLPDATABRAMRESPONSESLICE0 ( 776 << 2)\n#define CSR_TLPDATABRAMRESPONSESLICE1 ( 777 << 2)\n#define CSR_TLPDATABRAMRESPONSESLICE2 ( 778 << 2)\n#define CSR_TLPDATABRAMRESPONSESLICE3 ( 779 << 2)\n#define CSR_TLPDATABRAMRESPONSESLICE4 ( 780 << 2)\n#define CSR_TLPDATABRAMRESPONSESLICE5 ( 781 << 2)\n#define CSR_TLPPCIEWRADDRREG          ( 792 << 2)\n#define CSR_CHANGELO                  ( 801 << 2)\n#define CSR_CHANGEHI                  ( 802 << 2)\n\n/* MSIX must be in separate 4kb page */\n#define CSR_MSIX_ADDR_LO              (1024 << 2)\n#define CSR_MSIX_ADDR_HI              (1025 << 2)\n#define CSR_MSIX_MSG_DATA             (1026 << 2)\n#define CSR_MSIX_MASKED               (1027 << 2)\n\n#define PCR_IID_OFFSET 0x010\n#define PCR_NUM_TILES_OFFSET 0x008\n#define PCR_NUM_PORTALS_OFFSET 0x014\n#define MAX_MSIX_ENTRIES 16\n#define MAX_MINOR_COUNT (NUM_BOARDS * MAX_NUM_PORTALS)\n\n/* static device data */\nstatic dev_t device_number;\nstatic char portalp[MAX_MINOR_COUNT]; // free map of minor numbers\nstatic struct class *pcieportal_class = NULL;\ntypedef struct extra_info { /* these datatypes are not available to userspace */\n        struct cdev       cdev; /* per-portal cdev structure */\n        wait_queue_head_t wait_queue; /* used for interrupt notifications */\n        dma_addr_t        dma_handle;\n        tPortal          *portal;\n} extra_info;\nstatic extra_info extra_portal_info[MAX_MINOR_COUNT];\nstatic extra_info extra_board_info[NUM_BOARDS];\nstatic extra_info pcis_board_info[NUM_BOARDS];\nstatic tBoard board_map[NUM_BOARDS + 1];\nstatic unsigned long long expected_magic = 'B' | ((unsigned long long) 'l' << 8)\n    | ((unsigned long long) 'u' << 16) | ((unsigned long long) 'e' << 24)\n    | ((unsigned long long) 's' << 32) | ((unsigned long long) 'p' << 40)\n    | ((unsigned long long) 'e' << 48) | ((unsigned long long) 'c' << 56);\nstatic tTraceInfo traceInfo;\n\n/*\n * interrupt handler\n */\nstatic irqreturn_t intr_handler(int irq, void *p)\n{\n        tTile *this_tile = p;\n        tBoard *this_board = this_tile->board;\n        int i;\n        //printk(KERN_INFO \"%s_%d: interrupt!\\n\", DEV_NAME, this_tile->device_tile-1);\n        for (i = 0; i < MAX_NUM_PORTALS; i++) {\n                if ((this_tile->device_tile-1 == this_board->portal[i].device_tile)\n                    || this_tile->board->info.aws_shell) {\n                        if (this_board->portal[i].extra)\n                                wake_up_interruptible(&(this_board->portal[i].extra->wait_queue));\n                }\n        }\n        return IRQ_HANDLED;\n}\n\n/*\n * driver file operations\n */\n\n/* open the device file */\nstatic int pcieportal_open(struct inode *inode, struct file *filp)\n{\n        int err = 0;\n        tPortal *this_portal = ((extra_info *)inode->i_cdev)->portal;\n\n        if (!this_portal) {\n                printk(\"pcieportal_open: basedevice_number=%x /dev/connectal\\n\", device_number);\n        }\n        else {\n                printk(\"pcieportal_open: basedevice_number=%x tile=%d name=%d\\n\",\n                       device_number, this_portal->device_tile, this_portal->device_name);\n//printk(\"[%s:%d] inode %p filp %p portal %p priv %p privp %p extra %p\\n\", __FUNCTION__, __LINE__, inode, filp, this_portal, filp->private_data, privp, this_portal->extra);\n                init_waitqueue_head(&(this_portal->extra->wait_queue));\n                /* increment the open file count */\n                this_portal->board->open_count += 1;\n        }\n        filp->private_data = (void *) this_portal;\n        // FIXME: why does the kernel think this device is RDONLY?\n        filp->f_mode |= FMODE_WRITE;\n\n        return err;\n}\n\n/* close the device file */\nstatic int pcieportal_release(struct inode *inode, struct file *filp)\n{\n        tPortal *this_portal = (tPortal *) filp->private_data;\n        if (this_portal) {\n        struct list_head *pmlist;\n        PortalInternal devptr = {.map_base = this_portal->regs, .transport = &kernelfunc};\n\n        /* decrement the open file count */\n        init_waitqueue_head(&(this_portal->extra->wait_queue));\n        this_portal->board->open_count -= 1;\n        printk(\"%s_%d_%d: Closed device file\\n\", DEV_NAME, this_portal->device_tile, this_portal->device_name);\n        list_for_each(pmlist, &this_portal->pmlist) {\n                struct pmentry *pmentry = list_entry(pmlist, struct pmentry, pmlist);\n                printk(\"    returning id=%d fmem=%p\\n\", pmentry->id, pmentry->fmem);\n                MMURequest_idReturn(&devptr, pmentry->id);\n                fput(pmentry->fmem);\n                kfree(pmentry);\n        }\n        INIT_LIST_HEAD(&this_portal->pmlist);\n        }\n        return 0;                /* success */\n}\n\n/* poll operation to predict blocking of reads & writes */\nstatic unsigned int pcieportal_poll(struct file *filp, poll_table *poll_table)\n{\n        tPortal *this_portal = (tPortal *) filp->private_data;\n        unsigned int mask = 0;\n        uint32_t status = 0;\n\n        //printk(KERN_INFO \"%s_%d_%d: poll function called\\n\", DEV_NAME, this_portal->device_tile, this_portal->device_name);\n        poll_wait(filp, &this_portal->extra->wait_queue, poll_table);\n        if (this_portal->regs) {\n            status = *this_portal->regs;\n        }\n        if (status)\n            mask |= POLLIN  | POLLRDNORM; /* readable */\n        //mask |= POLLOUT | POLLWRNORM; /* writable */\n        //printk(KERN_INFO \"%s_%d_%d: poll return status is %x\\n\", DEV_NAME, this_portal->device_tile, this_portal->device_name, mask);\n        return mask;\n}\n\n/*\n * driver IOCTL operations\n */\n\nstatic long pcieportal_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)\n{\n        int err = 0;\n        tPortal *this_portal = (tPortal *) filp->private_data;\n        tBoard *this_board = NULL;\n        //tBoardInfo info;\n        static int trace_index;\n\n        if (this_portal)\n            this_board = this_portal->board;\n        /* basic sanity checks */\n        if (_IOC_DIR(cmd) & _IOC_READ) {\n#if (LINUX_VERSION_CODE < KERNEL_VERSION(5,0,0))\n                err = !access_ok(VERIFY_WRITE, (void __user *) arg, _IOC_SIZE(cmd));\n#else\n                err = !access_ok((void __user *) arg, _IOC_SIZE(cmd));\n#endif\n        } else if (_IOC_DIR(cmd) & _IOC_WRITE) {\n#if (LINUX_VERSION_CODE < KERNEL_VERSION(5,0,0))\n                err = !access_ok(VERIFY_WRITE, (void __user *) arg, _IOC_SIZE(cmd));\n#else\n                err = !access_ok((void __user *) arg, _IOC_SIZE(cmd));\n#endif\n        }\n        if (!err)\n        switch (cmd) {\n        case BNOC_GET_TLP:\n                {\n                /* copy board identification info to a user-space struct */\n                unsigned int tlp[6];\n                memset((char *) tlp, 0xbf, sizeof(tlp));\n                tlp[5] = ioread32(this_board->bar0io + CSR_TLPDATABRAMRESPONSESLICE5);\n                mb();\n                tlp[0] = ioread32(this_board->bar0io + CSR_TLPDATABRAMRESPONSESLICE0);\n                mb();\n                tlp[4] = ioread32(this_board->bar0io + CSR_TLPDATABRAMRESPONSESLICE4);\n                mb();\n                tlp[1] = ioread32(this_board->bar0io + CSR_TLPDATABRAMRESPONSESLICE1);\n                mb();\n                tlp[3] = ioread32(this_board->bar0io + CSR_TLPDATABRAMRESPONSESLICE3);\n                mb();\n                tlp[2] = ioread32(this_board->bar0io + CSR_TLPDATABRAMRESPONSESLICE2);\n                iowrite32(trace_index++, this_board->bar0io + CSR_TLPDATAFIFO_DEQ);\n                // now deq the tlpDataFifo\n                err = copy_to_user((void __user *) arg, tlp, sizeof(tTlpData));\n                break;\n                }\n        case BNOC_TRACE:\n                {\n                trace_index = 0;\n                iowrite32(0, this_board->bar0io + CSR_TLPPCIEWRADDRREG);\n                traceInfo.trace = ioread32(this_board->bar0io + CSR_TLPTRACINGREG);\n                traceInfo.traceLength = ioread32(this_board->bar0io + CSR_TLPTRACELENGTHREG);\n                if (traceInfo.traceLength == 0xbad0add0) // unimplemented\n                         traceInfo.traceLength = 2048; // default value\n                iowrite32(0, this_board->bar0io + CSR_TLPTRACINGREG);  // disable tracing\n                printk(\"disable tracing old trace=%d\\n\", traceInfo.trace);\n                err = copy_to_user((void __user *) arg, &traceInfo, sizeof(tTraceInfo));\n                iowrite32(trace_index++, this_board->bar0io + CSR_TLPDATAFIFO_DEQ);\n                }\n                break;\n        case BNOC_ENABLE_TRACE:\n                traceInfo.trace = ioread32(this_board->bar0io + CSR_TLPTRACINGREG);\n                iowrite32(1, this_board->bar0io + CSR_TLPTRACINGREG);  // disable tracing\n                break;\n        case PCIE_SEND_FD:\n                {\n                /* pushd down allocated fd */\n                tSendFd sendFd;\n                struct pmentry *pmentry;\n                PortalInternal devptr = {.map_base = this_portal->regs, .transport = &kernelfunc};\n\n                err = copy_from_user(&sendFd, (void __user *) arg, sizeof(sendFd));\n                if (err)\n                    break;\n                pmentry = (struct pmentry *)kzalloc(sizeof(struct pmentry), GFP_KERNEL);\n                INIT_LIST_HEAD(&pmentry->pmlist);\n                pmentry->fmem = fget(sendFd.fd);\n                pmentry->id   = sendFd.id;\n                printk(\"[%s:%d] PCIE_SEND_FD fd=%x id=%x fmem=%p  **\\n\", __FUNCTION__, __LINE__, sendFd.fd, sendFd.id, pmentry->fmem);\n                list_add(&pmentry->pmlist, &this_portal->pmlist);\n                err = send_fd_to_portal(&devptr, sendFd.fd, sendFd.id, 0);\n                if (err < 0)\n                    break;\n                err = 0;\n                }\n                break;\n        case PCIE_DEREFERENCE: {\n                int id = arg;\n                struct list_head *pmlist, *n;\n                PortalInternal devptr = {.map_base = this_portal->regs, .transport = &kernelfunc};\n                err = -ENOENT;\n                MMURequest_idReturn(&devptr, id);\n                list_for_each_safe(pmlist, n, &this_portal->pmlist) {\n                        struct pmentry *pmentry = list_entry(pmlist, struct pmentry, pmlist);\n                        if (pmentry->id == id) {\n                                printk(\"%s:%d releasing portalmem id=%d fmem=%p count=%ld\\n\", __FUNCTION__, __LINE__, id, pmentry->fmem, (unsigned long)pmentry->fmem->f_count.counter);\n                                fput(pmentry->fmem);\n                                list_del(&pmentry->pmlist);\n                                kfree(pmentry);\n                                err = 0;\n                                break;\n                        }\n                }\n        } break;\n        case PCIE_SIGNATURE: {\n                return 0;\n                }\n        case PCIE_CHANGE_ENTRY: {\n                tChangeEntry entry;\n                uint32_t vlo;\n                vlo = ioread32(this_board->bar0io + CSR_CHANGELO);\n                entry.timestamp = ioread32(this_board->bar0io + CSR_CHANGEHI);\n                entry.src = (vlo >> 24);\n                entry.value = vlo;\n                printk(\"%s: timestamp=%08x src=%02x value=%96x\\n\", \"portal\", entry.timestamp, entry.src, entry.value);\n                if (copy_to_user((void __user *)arg, &entry, sizeof(entry)))\n                        return -EFAULT;\n                return 0;\n        } break;\n        default:\n                return -ENOTTY;\n        }\n        if (err)\n                return -EFAULT;\n        return 0;\n}\n\nstatic int portal_mmap(struct file *filp, struct vm_area_struct *vma)\n{\n        tPortal *this_portal = (tPortal *) filp->private_data;\n        struct pci_dev *pci_dev = this_portal->board->pci_dev;\n        off_t off;\n\n        if (vma->vm_pgoff > (~0UL >> PAGE_SHIFT))\n                return -EINVAL;\n        if (vma->vm_pgoff < 16) {\n                if (this_portal->board->info.aws_shell) {\n                        off = pci_dev->resource[0].start + this_portal->offset;\n                } else {\n                        off = pci_dev->resource[2].start + this_portal->offset;\n                }\n                printk(\"portal_mmap portal_number=%d board_start=%012lx portal_start=%012lx\\n\",\n                     this_portal->portal_number, (long) pci_dev->resource[2].start, off);\n                vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);\n                vma->vm_pgoff = off >> PAGE_SHIFT;\n                //vma->vm_flags |= VM_IO | VM_RESERVED;\n        } else {\n                if (!this_portal->virt) {\n                        this_portal->virt = dma_alloc_coherent(&pci_dev->dev,\n                             vma->vm_end - vma->vm_start, &this_portal->extra->dma_handle, GFP_ATOMIC);\n                        //this_portal->virt =pci_alloc_consistent(pci_dev, PORTAL_BASE_OFFSET, &this_portal->extra->dma_handle);\n                        printk(\"dma_alloc_coherent virt=%p dma_handle=%p\\n\",\n                             this_portal->virt, (void *) this_portal->extra->dma_handle);\n                }\n                //vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);\n                off = this_portal->extra->dma_handle;\n        }\n        vma->vm_flags |= VM_IO;\n        if (io_remap_pfn_range(vma, vma->vm_start, off >> PAGE_SHIFT,\n             vma->vm_end - vma->vm_start, vma->vm_page_prot))\n                return -EAGAIN;\n\n        return 0;\n}\n\nstatic ssize_t pcieportal_read(struct file *filp,\n      char *buffer, size_t length, loff_t *offset)\n{\n        return 0;\n}\n\n/* file operations pointers */\nstatic const struct file_operations pcieportal_fops = {\n        .owner = THIS_MODULE,\n        .open = pcieportal_open,\n        .read   = pcieportal_read,\n        .release = pcieportal_release,\n        .poll = pcieportal_poll,\n        .unlocked_ioctl = pcieportal_ioctl,\n        .compat_ioctl = pcieportal_ioctl,\n        .mmap = portal_mmap\n};\n\nstatic int pcieportal_dma_pcis_open(struct inode *inode, struct file *filp)\n{\n        //tBoard *this_board = &board_map[0];\n        int err = 0;\n\n        printk(\"pcieportal_dma_pcis_open\\n\");\n        filp->private_data = (void *) &board_map[0];\n        // FIXME: why does the kernel think this device is RDONLY?\n        filp->f_mode |= FMODE_WRITE;\n\n        return err;\n}\n\n/* close the device file */\nstatic int pcieportal_dma_pcis_release(struct inode *inode, struct file *filp)\n{\n        // do we need to unmap?\n\n        return 0;                /* success */\n}\n\nstatic int portal_dma_pcis_mmap(struct file *filp, struct vm_area_struct *vma)\n{\n        tBoard *this_board = &board_map[0];\n        struct pci_dev *pci_dev = this_board->pci_dev;\n        off_t off = 0;\n\n        if (vma->vm_pgoff > (~0UL >> PAGE_SHIFT))\n                return -EINVAL;\n\n        if (this_board->info.aws_shell) {\n                off = pci_dev->resource[4].start;\n        } else {\n                printk(\"portal_dma_pcis only supported on AWS F1\\n\");\n                return -EINVAL;\n        }\n        printk(\"portal_dma_pcis_mmap board_start=%012lx\",\n               (long) pci_dev->resource[4].start);\n        vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);\n        vma->vm_pgoff = off >> PAGE_SHIFT;\n        //vma->vm_flags |= VM_IO | VM_RESERVED;\n\n        vma->vm_flags |= VM_IO;\n        if (io_remap_pfn_range(vma, vma->vm_start, off >> PAGE_SHIFT,\n                               vma->vm_end - vma->vm_start, vma->vm_page_prot))\n                return -EAGAIN;\n\n        return 0;\n}\n\nstatic const struct file_operations pcieportal_dma_pcis_fops = {\n        .owner = THIS_MODULE,\n        .open = pcieportal_dma_pcis_open,\n        .read   = pcieportal_read,\n        .release = pcieportal_dma_pcis_release,\n        .mmap = portal_dma_pcis_mmap\n};\n\n\n#ifdef PCIEPORTAL_TUNE_CAPS\nstatic void tune_pcie_caps(struct pci_dev *dev)\n{\n        struct pci_dev *parent;\n        u16 rc_mpss, rc_mps, ep_mpss, ep_mps;\n        u16 rc_mrrs, ep_mrrs, max_mrrs;\n\n        printk(\"%s: %s:%d\\n\", DEV_NAME, __FUNCTION__, __LINE__);\n        parent = dev->bus->self;\n        // why does parent have to be root?\n        if (!pci_is_root_bus(parent->bus)) {\n                printk(\"%s: parent is not root\\n\", DEV_NAME);\n                return;\n        }\n\n        /* max payload size adjustment */\n        rc_mpss = parent->pcie_mpss;\n        rc_mps  = ffs(pcie_get_mps(parent)) - 8;\n\n        ep_mpss = dev->pcie_mpss;\n        ep_mps  = ffs(pcie_get_mps(dev))    - 8;\n\n        rc_mpss = max(rc_mpss, ep_mpss);\n        if (rc_mpss > rc_mps) {\n                rc_mps = rc_mpss;\n                pcie_set_mps(parent, 128 << rc_mps);\n        }\n        if (rc_mpss > ep_mps) {\n                ep_mps = rc_mpss;\n                pcie_set_mps(dev, 128 << ep_mps);\n        }\n\n        printk(\"%s: %s:%d parent.mps=%d dev.mps=%d\\n\", DEV_NAME, __FUNCTION__, __LINE__, pcie_get_mps(parent), pcie_get_mps(dev));\n\n        /* max read request size, limited to 4096 by PCIe spec */\n        max_mrrs = 128 << 5;\n        rc_mrrs = pcie_get_readrq(parent);\n        ep_mrrs = pcie_get_readrq(dev);\n\n        if (max_mrrs > rc_mrrs) {\n                rc_mrrs = max_mrrs;\n                pcie_set_readrq(parent, rc_mrrs);\n        }\n        if (max_mrrs > ep_mrrs) {\n                ep_mrrs = max_mrrs;\n                pcie_set_readrq(dev, ep_mrrs);\n        }\n\n        printk(\"%s: %s:%d parent.readrq=%d dev.readrq=%d\\n\", DEV_NAME, __FUNCTION__, __LINE__, pcie_get_readrq(parent), pcie_get_readrq(dev));\n\n}\n#endif // PCIEPORTAL_TUNE_CAPS\n\nstatic int board_activate(int activate, tBoard *this_board, struct pci_dev *dev)\n{\n        int i;\n        int rc, err = 0;\n        unsigned long long magic_num;\n        int num_entries = MAX_MSIX_ENTRIES;\n        struct msix_entry msix_entries[MAX_MSIX_ENTRIES];\n        int fpn = 0;\n        int num_tiles, tile_index;\n        void __iomem *ptile;\n\nprintk(\"[%s:%d]\\n\", __FUNCTION__, __LINE__);\n        for (i = 0; i < MAX_NUM_PORTALS; i++)\n                if (!this_board->portal[i].extra) {\n                        printk(KERN_ERR \"%s: extra not initialized!!! %s\\n\", DEV_NAME, pci_name(dev));\n                        err = -EFAULT;\n                        goto err_exit;\n                }\n        if (activate) {\n                dev_t this_device_number;\n                void *portal_base = 0;\n                for (i = 0; i < MAX_NUM_PORTALS; i++)\n                  this_board->portal[i].device_name = -1;\n                for (i = 0; i < MAX_NUM_PORTALS; i++)\n                  init_waitqueue_head(&(this_board->portal[i].extra->wait_queue));\n                this_board->pci_dev = dev;\n                /* enable the PCI device */\n                if (pci_enable_device(dev)) {\n                        printk(KERN_ERR \"%s: failed to enable %s\\n\", DEV_NAME, pci_name(dev));\n                        err = -EFAULT;\n                        goto err_exit;\n                }\n                /* reserve PCI memory regions */\n                for (i = 0; i < 5; i++)\n                        printk(\"pci bar %d start=%08lx end=%08lx flags=%lx\\n\", i,\n                             (unsigned long) dev->resource[i].start,\n                             (unsigned long) dev->resource[i].end,\n                             dev->resource[i].flags);\n                traceInfo.base = dev->resource[2].start; /* remember physical address of bar2 */\n                if ((rc = pci_request_region(dev, 0, \"bar0\"))) {\n                        printk(\"failed to request region bar0 rc=%d\\n\", rc);\n                        err = -EBUSY;\n                        goto PCI_DEV_ENABLED_label;\n                }\n                rc = pci_request_region(dev, 1, \"bar1\");\n                printk(\"reserving region bar1 rc=%d\\n\", rc);\n                rc = pci_request_region(dev, 2, \"bar2\");\n                printk(\"reserving region bar2 rc=%d\\n\", rc);\n                /* map BARs */\n                this_board->bar0io = pci_iomap(dev, 0, 0);\n                printk(\"bar0io=%p\\n\", this_board->bar0io);\n                this_board->bar1io = pci_iomap(dev, 1, 0);\n                printk(\"bar1io=%p\\n\", this_board->bar1io);\n                this_board->bar2io = pci_iomap(dev, 2, 0);\n                printk(\"bar2io=%p\\n\", this_board->bar2io);\n                this_board->bar4io = pci_iomap(dev, 4, 0);\n                printk(\"bar4io=%p\\n\", this_board->bar4io);\n\n                if (!this_board->bar1io) {\n                        this_board->bar1io = pci_iomap(dev, 1, 8192);\n                        printk(\"bar1io=%p\\n\", this_board->bar1io);\n                }\n                if (!this_board->bar0io) {\n                        printk(\"failed to map bar0\\n\");\n                        err = -EFAULT;\n                        goto BARS_ALLOCATED_label;\n                }\n                if (!this_board->bar2io) {\n                        printk(\"failed to map bar2\\n\");\n                        err = -EFAULT;\n                        goto BARS_ALLOCATED_label;\n                }\n                if (!this_board->bar4io) {\n                        this_board->info.aws_shell = 0;\n                        // this replaces 'connectal/pcie/connectalutil/connectalutil trace /dev/fpga0'\n                        // but why is it needed?...\n                        iowrite32(0, this_board->bar0io + CSR_TLPPCIEWRADDRREG);\n                        // enable tracing\n                        iowrite32(1, this_board->bar0io + CSR_TLPTRACINGREG);\n                        /* check the magic number in BAR 0 */\n                        magic_num = ((long long)ioread32(this_board->bar0io + CSR_ID +  4)) << 32;\n                        magic_num |= ioread32(this_board->bar0io + CSR_ID);\n                        if (magic_num != expected_magic) {\n                                printk(KERN_ERR \"%s: magic number %llx does not match expected %llx\\n\",\n                                       DEV_NAME, magic_num, expected_magic);\n                                err = -EINVAL;\n                                goto BARS_MAPPED_label;\n                        }\n                        // check for xdma on bar2\n                } else {\n                        this_board->info.aws_shell = 1;\n                        printk(\"  xdma block ID %x\\n\", ioread32(this_board->bar2io + 0x0000));\n                        printk(\"   irq block ID %x\\n\", ioread32(this_board->bar2io + 0x2000));\n                        printk(\"config block ID %x\\n\", ioread32(this_board->bar2io + 0x3000));\n                }\n                /* set DMA mask */\n                if (pci_set_dma_mask(dev, DMA_BIT_MASK(48))) {\n                        printk(KERN_ERR \"%s: pci_set_dma_mask failed for 48-bit DMA\\n\", DEV_NAME);\n                        err = -EIO;\n                        goto BARS_MAPPED_label;\n                }\n                /* enable MSIX */\n                for (i = 0; i < num_entries; i++)\n                        msix_entries[i].entry = i;\n                if ((num_entries = pci_enable_msix_range(dev, msix_entries, num_entries, num_entries)) < 0) {\n                        printk(KERN_ERR \"%s: Failed to setup MSIX interrupts\\n\", DEV_NAME);\n                        err = -EFAULT;\n                        goto BARS_MAPPED_label;\n                }\n                this_board->irq_num = msix_entries[0].vector;\n                printk(KERN_INFO \"%s: Using MSIX interrupts num_entries=%d check_device\\n\", DEV_NAME, num_entries);\n                for (i = 0; i < num_entries; i++)\n                        printk(KERN_INFO \"%s: msix_entries[%d] vector=%d entry=%08x\\n\", DEV_NAME, i, msix_entries[i].vector, msix_entries[i].entry);\n                /* install the IRQ handler */\n                for (i = 0; i < num_entries; i++) {\n                        if (request_irq(this_board->irq_num + i, intr_handler, 0, DEV_NAME, (void *) &this_board->tile[i])) {\n                                printk(KERN_ERR \"%s: Failed to get requested IRQ %d\\n\", DEV_NAME, this_board->irq_num);\n                                err = -EBUSY;\n                                goto MSI_ENABLED_label;\n                        }\n                }\n                /* set MSIX Entry 0 Vector Control value to 0 (unmasked) */\n                printk(KERN_INFO \"%s: MSIX interrupts enabled with %d IRQs starting at %d\\n\",\n                       DEV_NAME, num_entries, this_board->irq_num);\n                iowrite32(0, this_board->bar0io + CSR_MSIX_MASKED);\n                pci_set_master(dev); /* enable PCI bus master */\n\n                if (this_board->info.aws_shell) {\n                        portal_base = this_board->bar0io;\n                        ptile = this_board->bar0io;\n                        printk(\"bar0io[0]=%08x\\n\", *(int *)this_board->bar0io);\n\n                        // enable user interrupts via XDMA block in AWS F1 Shell\n                        iowrite32(0xFFFF, this_board->bar2io + 0x2000 + 4);\n                        printk(\"enabled user interrupts in XDMA %x\\n\", ioread32(this_board->bar2io + 0x2000 + 4));\n\n                } else {\n                        portal_base = this_board->bar2io;\n                        ptile = this_board->bar2io;\n                }\n                num_tiles = *(volatile uint32_t *)(ptile + PCR_NUM_TILES_OFFSET);\n                if (num_tiles < 0 || num_tiles > 16)\n                        num_tiles = 0;\n                tile_index = 0;\n                do {  // loop over all tiles\n                  void __iomem *pportal = ptile;\n                  int num_portals = *(volatile uint32_t *)(pportal + PCR_NUM_PORTALS_OFFSET);\n                  int portal_index = 0;\n                  this_board->tile[tile_index].board = this_board;\n                  this_board->tile[tile_index].device_tile = tile_index + 1;\n                  do {  // loop over all portals in a tile\n                    int freep;\n                    uint32_t iid = *(volatile uint32_t *)(pportal + PCR_IID_OFFSET);\n                    tPortal *this_portal = &this_board->portal[fpn];\n                    unsigned long offs = ((unsigned long)pportal) - ((unsigned long)portal_base);\n                    printk(\"%s:%d num_tiles %x/%x num_portals %x/%x fpn %x iid=%d pportal %p offset %lx\\n\", __FUNCTION__, __LINE__, tile_index, num_tiles, portal_index, num_portals, fpn, iid, pportal, offs);\n                    traceInfo.intval[fpn] = ioread32(this_board->bar0io + CSR_MSIX_MSG_DATA  + 16*fpn);\n                    traceInfo.name[fpn] = iid;\n                    for (freep = 0; freep < sizeof(portalp)/sizeof(portalp[0]); freep++)\n                        if (!portalp[freep])\n                             break;\n                    if (freep == sizeof(portalp)/sizeof(portalp[0])) {\n                        printk(KERN_ERR \"%s: too many portals\\n\", KERN_ERR);\n                        err = -EFAULT;\n                    }\n                    else\n                        portalp[freep] = 1;\n                    this_portal->device_number = freep;\n                    this_portal->device_tile = tile_index;\n                    this_portal->portal_number = fpn;\n                    this_portal->device_name = iid;\n                    this_portal->board = this_board;\n                    this_portal->regs = (volatile uint32_t *)pportal;\n                    this_portal->offset = offs;\n                    /* add the device operations */\n                    cdev_init(&this_portal->extra->cdev, &pcieportal_fops);\n                    this_device_number = MKDEV(MAJOR(device_number), MINOR(device_number) + this_portal->device_number);\n                    printk(\"%s:%d: calling cdev_add this_device_number=%x\\n\", DEV_NAME, __LINE__, this_device_number);\n                    if (cdev_add(&this_portal->extra->cdev, this_device_number, 1)) {\n                      printk(KERN_ERR \"%s: cdev_add %x failed\\n\",\n                             DEV_NAME, this_device_number);\n                      err = -EFAULT;\n                    } else {\n                      /* create a device node via udev */\n                      printk(\"%s:%d: calling_device_create /dev/%s_b%dt%dp%d = %x\\n\",\n                             DEV_NAME, __LINE__, DEV_NAME, this_portal->board->info.board_number, this_portal->device_tile, this_portal->device_name, this_device_number);\n                      device_create(pcieportal_class, &dev->dev, this_device_number,\n                                    this_portal, \"%s_b%dt%dp%d\", DEV_NAME, this_portal->board->info.board_number, this_portal->device_tile, this_portal->device_name);\n                      printk(KERN_INFO \"%s: /dev/%s_b%dt%dp%d = %x created\\n\",\n                             DEV_NAME, DEV_NAME, this_portal->board->info.board_number, this_portal->device_tile, this_portal->device_name, this_device_number);\n                    }\n                    if (++fpn >= MAX_NUM_PORTALS){\n                      printk(KERN_INFO \"%s: MAX_NUM_PORTALS exceeded\", __func__);\n                      err = -EFAULT;\n                      break;\n                    }\n                    pportal += PORTAL_BASE_OFFSET;\n                  } while (++portal_index < num_portals);\n                  ptile += TILE_BASE_OFFSET;\n                } while (++tile_index < num_tiles);\n                this_board->info.num_portals = fpn;\n                pci_set_drvdata(dev, this_board);\n\n                if (this_board->info.board_number == 0) {\n                        this_device_number = MKDEV(MAJOR(device_number), MINOR(device_number) + MAX_MINOR_COUNT);\n                        cdev_init(&this_board->extra->cdev, &pcieportal_fops);\n                        printk(\"%s:%d: calling cdev_add this_device_number=%x\\n\", DEV_NAME, __LINE__, this_device_number);\n                        if (cdev_add(&this_board->extra->cdev, this_device_number, 1)) {\n                                printk(KERN_ERR \"%s: cdev_add board failed\\n\", DEV_NAME);\n                        }\n                        printk(\"%s:%d: calling device_create this_device_number=%x\\n\", DEV_NAME, __LINE__, this_device_number);\n                        device_create(pcieportal_class, &dev->dev, this_device_number, NULL, \"connectal\");\n\n                        // add the device node for portal_dma_pcis\n                        this_device_number = MKDEV(MAJOR(device_number), MINOR(device_number) + MAX_MINOR_COUNT + 1);\n                        cdev_init(&this_board->pcis->cdev, &pcieportal_dma_pcis_fops);\n                        printk(\"%s:%d: calling cdev_add this_device_number=%x\\n\", DEV_NAME, __LINE__, this_device_number);\n                        if (cdev_add(&this_board->pcis->cdev, this_device_number, 1)) {\n                                printk(KERN_ERR \"%s: cdev_add board failed\\n\", DEV_NAME);\n                        }\n                        printk(\"%s:%d: calling device_create this_device_number=%x\\n\", DEV_NAME, __LINE__, this_device_number);\n                        device_create(pcieportal_class, &dev->dev, this_device_number, NULL, \"portal_dma_pcis\");\n\n                }\n\n#ifdef PCIEPORTAL_TUNE_CAPS\n                tune_pcie_caps(dev);\n#endif // PCIEPORTAL_TUNE_CAPS\n\n                if (err == 0)\n                    return err; /* if board activated correctly, return */\n        } /* end of if(activate) */\n\n        /******** deactivate board *******/\n        if (this_board->info.board_number == 0) {\n                device_destroy(pcieportal_class, MKDEV(MAJOR(device_number), MINOR(device_number) + MAX_MINOR_COUNT));\n                cdev_del(&this_board->extra->cdev);\n\n                device_destroy(pcieportal_class, MKDEV(MAJOR(device_number), MINOR(device_number) + MAX_MINOR_COUNT + 1));\n                cdev_del(&this_board->pcis->cdev);\n        }\n        fpn = 0;\n        while(fpn < this_board->info.num_portals) {\n                tPortal *this_portal = &this_board->portal[fpn];\n                  /* remove device node in udev */\n                dev_t this_device_number = MKDEV(MAJOR(device_number), MINOR(device_number) + this_portal->device_number);\n                portalp[this_portal->device_name] = 0;\n                device_destroy(pcieportal_class, this_device_number);\n                printk(KERN_INFO \"%s: /dev/%s_b%dt%dp%d = %x removed\\n\",\n                       DEV_NAME, DEV_NAME, this_portal->board->info.board_number, this_portal->device_tile, this_portal->device_name, this_device_number);\n                /* remove device */\n                cdev_del(&this_board->portal[fpn].extra->cdev);\n                fpn++;\n        }\n        pci_clear_master(dev); /* disable PCI bus master */\n        /* set MSIX Entry 0 Vector Control value to 1 (masked) */\n        iowrite32(1, this_board->bar0io + CSR_MSIX_MASKED);\n        disable_irq(this_board->irq_num);\n        for (i = 0; i < num_entries; i++)\n                free_irq(this_board->irq_num + i, (void *) &this_board->tile[i]);\nMSI_ENABLED_label:\n        /* disable MSI/MSIX */\n        pci_disable_msix(dev);\nBARS_MAPPED_label:\n        /* unmap PCI BARs */\n        if (this_board->bar0io)\n                pci_iounmap(dev, this_board->bar0io);\n        if (this_board->bar1io)\n                pci_iounmap(dev, this_board->bar1io);\n        if (this_board->bar2io)\n                pci_iounmap(dev, this_board->bar2io);\n        if (this_board->bar4io)\n                pci_iounmap(dev, this_board->bar4io);\nBARS_ALLOCATED_label:\n        pci_release_regions(dev); /* release PCI memory regions */\nPCI_DEV_ENABLED_label:\n        pci_disable_device(dev); /* disable pci device */\nerr_exit:\n        this_board->pci_dev = NULL;\n        pci_set_drvdata(dev, NULL);\n        return err;\n}\n\n/* driver PCI operations */\n\nstatic int pcieportal_probe(struct pci_dev *dev, const struct pci_device_id *id)\n{\n        tBoard *this_board = NULL;\n        int i, board_number = 0;\n\nprintk(\"******[%s:%d] probe %p dev %p id %p getdrv %p\\n\", __FUNCTION__, __LINE__, &pcieportal_probe, dev, id, pci_get_drvdata(dev));\n        printk(KERN_INFO \"%s: PCI probe for 0x%04x 0x%04x\\n\", DEV_NAME, dev->vendor, dev->device);\n        /* double-check vendor and device */\n        if ((dev->vendor != BLUESPEC_VENDOR_ID || dev->device != CONNECTAL_DEVICE_ID)\n            && (dev->vendor != AMAZON_VENDOR_ID || dev->device != AMAZON_DEVICE_ID)) {\n                printk(KERN_ERR \"%s: probe with invalid vendor or device ID\\n\", DEV_NAME);\n                return -EINVAL;\n        }\n        /* assign a board number */\n        while (board_map[board_number].pci_dev && board_number < NUM_BOARDS)\n                board_number++;\n        if (board_number >= NUM_BOARDS) {\n                printk(KERN_ERR \"%s: %d boards are already in use!\\n\", DEV_NAME, NUM_BOARDS);\n                return -EBUSY;\n        }\n        this_board = &board_map[board_number];\n        printk(KERN_INFO \"%s: board_number = %d\\n\", DEV_NAME, board_number);\n        memset(this_board, 0, sizeof(tBoard));\n        for (i = 0; i < MAX_NUM_PORTALS; i++) {\n                this_board->portal[i].extra = &extra_portal_info[board_number * MAX_NUM_PORTALS + i];\n                extra_portal_info[board_number * MAX_NUM_PORTALS + i].portal = &this_board->portal[i];\n                INIT_LIST_HEAD(&this_board->portal[i].pmlist);\n        }\n        this_board->extra = &extra_board_info[board_number];\n        this_board->pcis = &pcis_board_info[board_number];\n        this_board->info.board_number = board_number;\n        return board_activate(1, this_board, dev);\n}\n\nstatic void pcieportal_remove(struct pci_dev *dev)\n{\n        tBoard *this_board = pci_get_drvdata(dev);\nprintk(\"*****[%s:%d] getdrv %p\\n\", __FUNCTION__, __LINE__, this_board);\n        if (!this_board) {\n                printk(KERN_ERR \"%s: Unable to locate board when removing PCI device %p\\n\", DEV_NAME, dev);\n                return;\n        }\n        board_activate(0, this_board, dev);\n}\n\n/* PCI ID pattern table */\nstatic\n#ifdef DEFINE_PCI_DEVICE_TABLE // changed in Linux 4.8\n    DEFINE_PCI_DEVICE_TABLE(pcieportal_id_table)\n#else\n    const struct pci_device_id pcieportal_id_table[]\n#endif\n        = {\n  { PCI_DEVICE(BLUESPEC_VENDOR_ID, CONNECTAL_DEVICE_ID)},\n  { PCI_DEVICE(AMAZON_VENDOR_ID, AMAZON_DEVICE_ID)},\n  { /* end: all zeros */ }\n};\n\nMODULE_DEVICE_TABLE(pci, pcieportal_id_table);\n\nstatic pci_ers_result_t pcieportal_error_detected(struct pci_dev *pdev, enum pci_channel_state error)\n{\n        printk(KERN_ERR \"%s:%s: pcie error %d\\n\", DEV_NAME, __FUNCTION__, error);\n        return PCI_ERS_RESULT_CAN_RECOVER;\n}\n\nstatic pci_ers_result_t pcieportal_error_mmio_enabled(struct pci_dev *pdev)\n{\n        printk(KERN_ERR \"%s:%s\\n\", DEV_NAME, __FUNCTION__);\n        return PCI_ERS_RESULT_CAN_RECOVER;\n}\n\nstatic pci_ers_result_t pcieportal_error_slot_reset(struct pci_dev *pdev)\n{\n        printk(KERN_ERR \"%s:%s\\n\", DEV_NAME, __FUNCTION__);\n        return PCI_ERS_RESULT_CAN_RECOVER;\n}\n\nstatic void pcieportal_error_resume(struct pci_dev *pdev)\n{\n        printk(KERN_ERR \"%s:%s\\n\", DEV_NAME, __FUNCTION__);\n}\n\nstatic const struct pci_error_handlers pcieportal_err_handler = {\n        .error_detected = pcieportal_error_detected,\n        .mmio_enabled   = pcieportal_error_mmio_enabled,\n        .slot_reset     = pcieportal_error_slot_reset,\n        .resume         = pcieportal_error_resume,\n};\n\n/* PCI driver operations pointers */\nstatic struct pci_driver pcieportal_ops = {\n        .name = DEV_NAME,\n        .id_table = pcieportal_id_table,\n        .probe = pcieportal_probe,\n        .remove = pcieportal_remove,\n        .err_handler = &pcieportal_err_handler,\n};\n\n/*\n *\n * get the tBoard struct\n *\n */\n\ntBoard* get_pcie_portal_descriptor(void)\n{\n  return &board_map[0];\n}\n\n/*\n * driver initialization and exit\n *\n * these routines are responsible for allocating and\n * freeing kernel resources, creating device nodes,\n * registering the driver, obtaining a major and minor\n * numbers, etc.\n */\n\n/* first routine called on module load */\nstatic int pcieportal_init(void)\n{\n        int status;\n\nprintk(\"[%s:%d]\\n\", __FUNCTION__, __LINE__);\n        pcieportal_class = class_create(THIS_MODULE, \"Connectal\");\n        if (IS_ERR(pcieportal_class)) {\n                printk(KERN_ERR \"%s: failed to create class Connectal\\n\", DEV_NAME);\n                return PTR_ERR(pcieportal_class);\n        }\n        /* dynamically allocate a device number */\n        if (alloc_chrdev_region(&device_number, 1, MAX_MINOR_COUNT + 1, DEV_NAME) < 0) {\n                printk(KERN_ERR \"%s: failed to allocate character device region\\n\", DEV_NAME);\n                class_destroy(pcieportal_class);\n                return -1;\n        }\n        /* initialize driver data */\n        memset(board_map, 0, sizeof(board_map));\n        /* log the fact that we loaded the driver module */\n        printk(KERN_INFO \"%s: Registered Connectal Pcieportal driver %s\\n\", DEV_NAME, DRIVER_VERSION);\n        printk(KERN_INFO \"%s: Major = %d  Minors = %d to %d\\n\", DEV_NAME,\n               MAJOR(device_number), MINOR(device_number),\n               MINOR(device_number) + MAX_MINOR_COUNT - 1);\n        /* register the driver with the PCI subsystem */\n        status = pci_register_driver(&pcieportal_ops);\n        if (status < 0) {\n                printk(KERN_ERR \"%s: failed to register PCI driver\\n\", DEV_NAME);\n                class_destroy(pcieportal_class);\n                return status;\n        }\nprintk(\"[%s:%d]\\n\", __FUNCTION__, __LINE__);\n        return 0;                /* success */\n}\n\n/* routine called on module unload */\nstatic void pcieportal_exit(void)\n{\n        /* unregister the driver with the PCI subsystem */\n        pci_unregister_driver(&pcieportal_ops);\n        /* release reserved device numbers */\n        unregister_chrdev_region(device_number, MAX_MINOR_COUNT + 1);\n        class_destroy(pcieportal_class);\n        /* log that the driver module has been unloaded */\n        printk(KERN_INFO \"%s: Unregistered Connectal Pcieportal driver %s\\n\", DEV_NAME, DRIVER_VERSION);\n}\n\n\n/*\n * driver module data for the kernel\n */\n\nmodule_init(pcieportal_init);\nmodule_exit(pcieportal_exit);\n\nEXPORT_SYMBOL(get_pcie_portal_descriptor);\n\nMODULE_AUTHOR(\"Bluespec, Inc., Cambridge hackers\");\nMODULE_DESCRIPTION(\"PCIe device driver for PCIe FPGA portals\");\nMODULE_LICENSE(\"Dual BSD/GPL\");\nMODULE_VERSION(DRIVER_VERSION);\n"
  },
  {
    "path": "drivers/pcieportal/pcieportal.h",
    "content": "/* Copyright (c) 2014 Quanta Research Cambridge, Inc\n *\n * Permission is hereby granted, free of charge, to any person obtaining a\n * copy of this software and associated documentation files (the \"Software\"),\n * to deal in the Software without restriction, including without limitation\n * the rights to use, copy, modify, merge, publish, distribute, sublicense,\n * and/or sell copies of the Software, and to permit persons to whom the\n * Software is furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n * DEALINGS IN THE SOFTWARE.\n */\n#ifndef __BLUENOC_H__\n#define __BLUENOC_H__\n\n#include <linux/ioctl.h>\n\n/*\n * IOCTLs\n */\n\n/* magic number for IOCTLs */\n#define BNOC_IOC_MAGIC 0xB5\n\n/* Number of boards to support */\n#define NUM_BOARDS 4\n#define MAX_NUM_PORTALS 32\n\n/* Structures used with IOCTLs */\n\ntypedef struct {\n  unsigned long base;\n  unsigned int trace;\n  unsigned int traceLength;\n  unsigned int intval[MAX_NUM_PORTALS];\n  unsigned int name[MAX_NUM_PORTALS];\n} tTraceInfo;\n\ntypedef struct {\n  int fd;\n  int id;\n} tSendFd;\n\ntypedef struct {\n    int  index;        /* in param */\n    char md5[33];      /* out param -- asciz */\n    char filename[33]; /* out param -- asciz */\n} PortalSignaturePcie;\n\ntypedef unsigned int tTlpData[6];\n\ntypedef struct ChangeEntry {\n  unsigned int timestamp;\n  unsigned char src;\n  unsigned int value : 24;\n} tChangeEntry;\n/* IOCTL code definitions */\n\n#define BNOC_GET_TLP         _IOR(BNOC_IOC_MAGIC,7,tTlpData*)\n#define BNOC_TRACE           _IOWR(BNOC_IOC_MAGIC,8,tTraceInfo*)\n#define BNOC_ENABLE_TRACE    _IOR(BNOC_IOC_MAGIC,8,int*)\n#define PCIE_SEND_FD         _IOR(BNOC_IOC_MAGIC,12,tSendFd*)\n#define PCIE_DEREFERENCE     _IOR(BNOC_IOC_MAGIC,13,int)\n#define PCIE_SIGNATURE       _IOR(BNOC_IOC_MAGIC,14,PortalSignaturePcie)\n#define PCIE_CHANGE_ENTRY    _IOR(BNOC_IOC_MAGIC,15,tChangeEntry*)\n\n#ifdef __KERNEL__\n/*\n * Per-device data\n */\ntypedef struct {\n        unsigned int      device_number;\n        unsigned int      device_tile;\n        unsigned int      portal_number;\n        unsigned int      device_name;\n        struct tBoard    *board;\n        void             *virt;\n        volatile uint32_t *regs;  // Pointer to access portal from kernel\n        unsigned long     offset; // Offset from base of BAR2\n        struct extra_info *extra;\n        struct list_head pmlist;\n} tPortal;\n\ntypedef struct {\n        unsigned int      device_tile;\n        struct tBoard    *board;\n} tTile;\n\nstruct pmentry {\n        struct file     *fmem;\n        int              id;\n        struct list_head pmlist;\n};\n\ntypedef struct tBoard {\n        void __iomem     *bar0io, *bar1io, *bar2io, *bar4io; /* bars */\n        struct pci_dev   *pci_dev; /* pci device pointer */\n        tPortal           portal[MAX_NUM_PORTALS];\n        unsigned int      irq_num;\n        unsigned int      open_count;\n        tTile             tile[MAX_NUM_PORTALS];\n        struct extra_info *extra;\n        struct extra_info *pcis; // DMA PCIS on AWSF1\n        struct {\n          unsigned int board_number;\n          unsigned int portal_number;\n          unsigned int num_portals;\n          unsigned int aws_shell;\n        }                 info; /* board identification fields */\n} tBoard;\n\nextern tBoard* get_pcie_portal_descriptor(void);\n#endif\n\n#endif /* __BLUENOC_H__ */\n"
  },
  {
    "path": "drivers/portalmem/Makefile",
    "content": "\nV?=0\nifeq ($(V),0)\nQ=@\nelse\nQ=\nendif\nDEFCONFIG ?= xilinx_zynq_portal_atheros_sdio_defconfig\nCONNECTALDIR ?= $(PWD)/../..\ninclude $(CONNECTALDIR)/Makefile.version\n\nobj-m = portalmem.o\n\nccflags-y := -I$(CONNECTALDIR)\n\nifeq (\"$(KROOT)\",\"\")\nKVERSION=$(shell uname -r)\nexport KROOT=/lib/modules/$(KVERSION)/build\nelse\nCROSS_COMPILE?=arm-linux-gnueabi-\nPARAM=ARCH=arm CROSS_COMPILE=$(CROSS_COMPILE)\nendif\n\nportalmem.ko: portalmem.h portalmem.c driverversion.h\nifneq (\"$(PARAM)\",\"\")\n\t$(Q)$(MAKE) $(PARAM) -C $(KROOT) $(DEFCONFIG)\n\t$(Q)$(MAKE) $(PARAM) -C $(KROOT) -j8 zImage\nendif\n\t$(Q)$(MAKE) $(PARAM) -C $(KROOT) M=$(PWD) modules\n\ndriverversion.h:\n\tVERSION=$(VERSION) echo \"#define DRIVER_VERSION \\\"$VERSION\\\"\" > driverversion.h\n\nparallellaportalmem.ko: portalmem.h portalmem.c\n\t$(Q)$(MAKE) $(PARAM) -C $(KROOT) parallella_defconfig\n\t$(Q)$(MAKE) $(PARAM) -C $(KROOT) -j8 LOADADDR=0x8000 uImage\n\t$(Q)$(MAKE) $(PARAM) -C $(KROOT) M=$(PWD) modules\n\nclean:\n\t$(Q)$(MAKE) $(PARAM) -C $(KROOT) M=$(PWD) clean\n"
  },
  {
    "path": "drivers/portalmem/portalmem.c",
    "content": "/* Copyright (c) 2014 Quanta Research Cambridge, Inc\n * Copyright (c) 2015 Connectal Project\n *\n * Permission is hereby granted, free of charge, to any person obtaining a\n * copy of this software and associated documentation files (the \"Software\"),\n * to deal in the Software without restriction, including without limitation\n * the rights to use, copy, modify, merge, publish, distribute, sublicense,\n * and/or sell copies of the Software, and to permit persons to whom the\n * Software is furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n * DEALINGS IN THE SOFTWARE.\n */\n#include <linux/miscdevice.h>\n#include <linux/platform_device.h>\n#include <linux/module.h>\n#include <linux/version.h>\n#include <linux/kernel.h>\n#include <linux/types.h>\n#include <linux/device.h>\n#include <linux/uaccess.h>\n#include <linux/ioctl.h>\n#include <linux/dma-buf.h>\n#include <linux/slab.h>\n#include <linux/scatterlist.h>\n#include <linux/vmalloc.h>\n#include <asm/cacheflush.h>\n\n#include \"drivers/portalmem/portalmem.h\"\n#include \"driverversion.h\"\n\n#ifdef DEBUG // was KERN_DEBUG\n#define driver_devel(format, ...)               \\\n        do {                                    \\\n                printk(format, ## __VA_ARGS__); \\\n        } while (0)\n#else\n#define driver_devel(format, ...)\n#endif\n\n#define DRIVER_NAME \"portalmem\"\n#define DRIVER_DESCRIPTION \"Memory management between HW and SW processes\"\n\nstatic struct miscdevice miscdev;\n\nstatic void free_buffer_page(struct page *page, unsigned int order)\n{\n        __free_pages(page, order);\n}\n\nstatic int pa_buffer_free(struct pa_buffer *buffer)\n{\n        struct sg_table *table = buffer->sg_table;\n        struct scatterlist *sg;\n        LIST_HEAD(pages);\n        int i;\n        printk(\"PortalAlloc::pa_system_heap_free\\n\");\n        for_each_sg(table->sgl, sg, table->nents, i){\n                free_buffer_page(sg_page(sg), get_order(sg->length));\n        }\n        sg_free_table(table);\n        kfree(table);\n        kfree(buffer);\n        return 0;\n}\n\n/*\n * driver dma_buf callback functions\n */\n\nstatic struct sg_table *pa_dma_buf_map(struct dma_buf_attachment *attachment,\n                                       enum dma_data_direction direction)\n{\n        return ((struct pa_buffer *)attachment->dmabuf->priv)->sg_table;\n}\n\nstatic void pa_dma_buf_unmap(struct dma_buf_attachment *attachment,\n                             struct sg_table *table, enum dma_data_direction direction)\n{\n}\n\n//from: http://stackoverflow.com/questions/654393/examining-mmaped-addresses-using-gdb\nstatic inline int custom_vma_access(struct vm_area_struct *vma, unsigned long addr,\n                                    void *buf, int len, int write)\n{\n        void __iomem *maddr = NULL;\n        struct pa_buffer *buffer = vma->vm_private_data;\n        struct scatterlist *sg;\n        int i;\n        int offset = 0;\n        struct sg_table *table;\n\n        if (!buffer)\n                return -EFAULT;\n        offset = (addr) - vma->vm_start;\n\n        table = buffer->sg_table;\n        for_each_sg(table->sgl, sg, table->nents, i) {\n                struct page *page = sg_page(sg);\n                maddr = page_address(page);\n                if (offset < sg->length)\n                        break;\n                offset -= sg->length;\n        }\n        if (write)\n                memcpy(maddr + offset, buf, len);\n        else\n                memcpy(buf, maddr + offset, len);\n        return len;\n}\nstatic struct vm_operations_struct custom_vm_ops = {\n        .access = custom_vma_access,\n};\n\n#ifdef __arm__\n#include <linux/sched.h>\n#include \"asm/thread_info.h\"\n#include \"asm-generic/current.h\"\nstatic void llshow_pte(struct mm_struct *mm, unsigned long addr)\n{\n        pgd_t *pgd;\n        printk(KERN_ALERT \"pgd = %p\\n\", mm->pgd);\n        pgd = pgd_offset(mm, addr);\n        printk(KERN_ALERT \"[%08lx] *pgd=%08llx\", addr, (long long)pgd_val(*pgd));\n        do {\n                pud_t *pud;\n                pmd_t *pmd;\n                pte_t *pte;\n                if (pgd_none(*pgd))\n                        break;\n                if (pgd_bad(*pgd)) {\n                        printk(\"(bad)\");\n                        break;\n                }\n                pud = pud_offset(pgd, addr);\n                if (PTRS_PER_PUD != 1)\n                        printk(\", *pud=%08llx\", (long long)pud_val(*pud));\n                if (pud_none(*pud))\n                        break;\n                if (pud_bad(*pud)) {\n                        printk(\"(bad)\");\n                        break;\n                }\n                pmd = pmd_offset(pud, addr);\n                if (PTRS_PER_PMD != 1)\n                        printk(\", *pmd=%08llx\", (long long)pmd_val(*pmd));\n                if (pmd_none(*pmd))\n                        break;\n                if (pmd_bad(*pmd)) {\n                        printk(\"(bad)\");\n                        break;\n                }\n                /* We must not map this if we have highmem enabled */\n                if (PageHighMem(pfn_to_page(pmd_val(*pmd) >> PAGE_SHIFT)))\n                        break;\n                pte = pte_offset_map(pmd, addr);\n                printk(\", *pte=%08llx\", (long long)pte_val(*pte));\n#ifndef CONFIG_ARM_LPAE\n                printk(\", *ppte=%08llx\", (long long)pte_val(pte[PTE_HWTABLE_PTRS]));\n#endif\n                pte_unmap(pte);\n        } while(0);\n        printk(\"\\n\");\n}\n#endif\nstatic int pa_dma_buf_mmap(struct dma_buf *dmabuf, struct vm_area_struct *vma)\n{\n        struct pa_buffer *buffer = dmabuf->priv;\n        int ret = 0;\n        struct scatterlist *sg;\n        int i;\n\n        buffer->vaddr = (void *)(long)vma->vm_start;\n        /* Fill in vma_ops::access(), so that gdb print command works correctly */\n        vma->vm_ops = &custom_vm_ops;\n        vma->vm_private_data = buffer;\n        printk(\"pa_dma_buf_mmap %p %ld\\n\", (dmabuf->file), (unsigned long)dmabuf->file->f_count.counter);\n        if (!buffer->cached) {\n                // pgprot_writecombine must be disabled so that ld/strex work correctly on arm (in C: __gnu_cxx::__exchange_and_add )\n                // however, that currently breaks connectal examples. Jamey 10/2014\n                // According to Arm ARM A3.4.5: \"LDREX and STREX ... only on memory with Normal\"\n                // According to Arm ARM B3.7.2: TEX[2:0]/C/B == 000/0/1 -> \"Device\", 001/1/1 -> \"Normal\"\n                // (this is the difference between calling pgprot_writecombine() or not)\n                vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);\n        }\n        mutex_lock(&buffer->lock);\n        /* now map it to userspace */\n        {\n                struct sg_table *table = buffer->sg_table;\n                unsigned long addr = vma->vm_start;\n                unsigned long offset = vma->vm_pgoff * PAGE_SIZE;\n\n                //printk(\"(0) pa_system_heap_map_user %08lx %08lx %08lx\\n\", vma->vm_start, vma->vm_end, offset);\n                for_each_sg(table->sgl, sg, table->nents, i) {\n                        struct page *page = sg_page(sg);\n                        unsigned long remainder = vma->vm_end - addr;\n                        unsigned int len = sg->length; // sg->length is unsigned int\n                        //printk(\"pa_system_heap_map_user %08x %08x\\n\", sg->length, sg_dma_len(sg));\n                        //printk(\"(1) pa_system_heap_map_user %08lx %08lx %08x\\n\", (unsigned long) page, remainder, len);\n                        if (offset >= (sg->length)) {\n                                //printk(\"feck %08lx %08x\\n\", offset, (sg->length));\n                                offset -= (sg->length);\n                                continue;\n                        } else if (offset) {\n                                page += offset / PAGE_SIZE;\n                                len = (sg->length) - offset;\n                                offset = 0;\n                        }\n                        len = min((unsigned long)len, remainder);\n                        //printk(\"(2) pa_system_heap_map_user %08lx %08lx %08lx\\n\", addr, (unsigned long)page, page_to_pfn(page));\n                        remap_pfn_range(vma, addr, page_to_pfn(page), len,\n                                        vma->vm_page_prot);\n#ifdef __arm__\n                        llshow_pte(current->mm, (unsigned long) addr);\n#endif\n                        addr += len;\n                        if (addr >= vma->vm_end)\n                                break;\n                }\n        }\n        mutex_unlock(&buffer->lock);\n        if (ret)\n                pr_err(\"%s: failure mapping buffer to userspace\\n\", __func__);\n        return ret;\n}\n\nstatic void pa_dma_buf_release(struct dma_buf *dmabuf)\n{\n        struct pa_buffer *buffer = dmabuf->priv;\n        printk(\"PortalAlloc::pa_dma_buf_release %p %ld\\n\", (dmabuf->file), (unsigned long)dmabuf->file->f_count.counter);\n        pa_buffer_free(buffer);\n}\n\nstatic void *pa_dma_buf_kmap(struct dma_buf *dmabuf, unsigned long offset)\n{\n        struct pa_buffer *buffer = dmabuf->priv;\n        return buffer->vaddr + offset * PAGE_SIZE;\n}\n\nstatic void pa_dma_buf_kunmap(struct dma_buf *dmabuf, unsigned long offset,\n                              void *ptr)\n{\n}\n\nstatic int pa_dma_buf_begin_cpu_access(struct dma_buf *dmabuf,\n#if (LINUX_VERSION_CODE < KERNEL_VERSION(4,6,0))\n                                       size_t start,\n                                       size_t len,\n#endif\n                                       enum dma_data_direction direction)\n{\n        struct pa_buffer *buffer = dmabuf->priv;\n        void *vaddr = NULL;\n\n        mutex_lock(&buffer->lock);\n        vaddr = buffer->vaddr;\n        if (!buffer->kmap_cnt) {\n                struct sg_table *table = buffer->sg_table;\n                int npages = PAGE_ALIGN(buffer->size) / PAGE_SIZE;\n                struct page **pages = vmalloc(sizeof(struct page *) * npages);\n                struct page **tmp = pages;\n                if (pages) {\n                        int i, j;\n                        struct scatterlist *sg;\n                        pgprot_t pgprot = pgprot_writecombine(PAGE_KERNEL);\n                        for_each_sg(table->sgl, sg, table->nents, i) {\n                                int npages_this_entry = PAGE_ALIGN(sg->length) / PAGE_SIZE;\n                                struct page *page = sg_page(sg);\n                                BUG_ON(i >= npages);\n                                for (j = 0; j < npages_this_entry; j++)\n                                        *(tmp++) = page++;\n                        }\n                        vaddr = vmap(pages, npages, VM_MAP, pgprot);\n                        vfree(pages);\n                }\n        }\n        if (!IS_ERR_OR_NULL(vaddr)) {\n                buffer->vaddr = vaddr;\n                buffer->kmap_cnt++;\n        }\n        mutex_unlock(&buffer->lock);\n        if (IS_ERR(vaddr))\n                return PTR_ERR(vaddr);\n        if (!vaddr)\n                return -ENOMEM;\n        return 0;\n}\n\nstatic\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4,6,0))\nint\n#else\nvoid\n#endif\npa_dma_buf_end_cpu_access(struct dma_buf *dmabuf,\n#if (LINUX_VERSION_CODE < KERNEL_VERSION(4,6,0))\n                                      size_t start,\n                                      size_t len,\n#endif\n                                      enum dma_data_direction direction)\n{\n        struct pa_buffer *buffer = dmabuf->priv;\n\n        mutex_lock(&buffer->lock);\n        if (!--buffer->kmap_cnt) {\n                vunmap(buffer->vaddr);\n                buffer->vaddr = NULL;\n        }\n        mutex_unlock(&buffer->lock);\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4,6,0))\n        return 0;\n#endif\n}\n\nstatic void *pa_dma_buf_vmap(struct dma_buf *dmabuf)\n{\n        struct pa_buffer *buffer = dmabuf->priv;\n        pa_dma_buf_begin_cpu_access(dmabuf,\n#if (LINUX_VERSION_CODE < KERNEL_VERSION(4,6,0))\n                                    0, 0,\n#endif\n                                    0);\n        return buffer->vaddr;\n}\n\nstatic void pa_dma_buf_vunmap(struct dma_buf *dmabuf, void *vaddr)\n{\n        printk(\"%s: dmabuf %p vaddr %p\\n\", __FUNCTION__, dmabuf, vaddr);\n}\n\n\nstatic struct dma_buf_ops dma_buf_ops = {\n        .map_dma_buf      = pa_dma_buf_map,\n        .unmap_dma_buf    = pa_dma_buf_unmap,\n        .mmap             = pa_dma_buf_mmap,\n        .release          = pa_dma_buf_release,\n        .begin_cpu_access = pa_dma_buf_begin_cpu_access,\n        .end_cpu_access   = pa_dma_buf_end_cpu_access,\n#if (LINUX_VERSION_CODE < KERNEL_VERSION(4,12,0))\n        .kmap_atomic      = pa_dma_buf_kmap,\n        .kunmap_atomic    = pa_dma_buf_kunmap,\n        .kmap             = pa_dma_buf_kmap,\n        .kunmap           = pa_dma_buf_kunmap,\n#else\n#if (LINUX_VERSION_CODE < KERNEL_VERSION(5,0,0)) && !(defined(RHEL_MAJOR) && RHEL_MAJOR >= 8)\n        .map_atomic       = pa_dma_buf_kmap,\n        .unmap_atomic     = pa_dma_buf_kunmap,\n#endif\n#if !(defined(RHEL_MAJOR) && RHEL_MAJOR >= 8)\n        .map              = pa_dma_buf_kmap,\n        .unmap            = pa_dma_buf_kunmap,\n#endif\n#endif\n        .vmap             = pa_dma_buf_vmap,\n        .vunmap           = pa_dma_buf_vunmap,\n};\n\nint portalmem_dmabuffer_destroy(int fd)\n{\n        struct file *fmem = fget(fd);\n        pa_dma_buf_release(fmem->private_data);\n        //printk(\"%s:%d: fput fd=%d fmem=%p\\n\", __FUNCTION__, __LINE__, fd, fmem);\n        fput(fmem);\n        return 0;\n}\n\nint portalmem_dmabuffer_create(PortalAlloc portalAlloc)\n{\n        static const unsigned int orders[] = {8, 4, 0};\n        unsigned int allocated_orders[] = {0,0,0};\n        struct pa_buffer *buffer;\n        struct sg_table *table;\n        struct scatterlist *sg;\n        struct list_head pages;\n        struct page_info {\n                struct page *page;\n                unsigned long order;\n                struct list_head list;\n        } *info = NULL, *tmp_info;\n        unsigned int max_order = orders[0];\n        long size_remaining;\n        int infocount = 0;\n        size_t align = 4096;\n        size_t len = portalAlloc.len;\n        int return_fd;\n        unsigned int high_order_gfp_flags = (GFP_HIGHUSER | __GFP_ZERO | __GFP_NOWARN | __GFP_NORETRY );\n        unsigned int low_order_gfp_flags  = (GFP_HIGHUSER | __GFP_ZERO | __GFP_NOWARN);\n#ifdef __GFP_NO_KSWAPD\n        high_order_gfp_flags |= __GFP_NO_KSWAPD;\n#endif\n#ifdef __GFP_WAIT\n        high_order_gfp_flags &= ~__GFP_WAIT;\n#endif\n\n        printk(\"%s, size=%ld cached=%d\\n\", __FUNCTION__, (long)portalAlloc.len, portalAlloc.cached);\n        len = PAGE_ALIGN(round_up(len, align));\n        size_remaining = len;\n        buffer = kzalloc(sizeof(struct pa_buffer), GFP_KERNEL);\n        if (!buffer)\n                return -ENOMEM;\n        buffer->cached = portalAlloc.cached;\n\n        table = kmalloc(sizeof(struct sg_table), GFP_KERNEL);\n        if (!table) {\n                kfree(buffer);\n                return -ENOMEM;\n        }\n        INIT_LIST_HEAD(&pages);\n        while (size_remaining > 0) {\n                int ordindex = 0;\n                info = NULL;\n                for (; ordindex < ARRAY_SIZE(orders); ordindex++) {\n                        gfp_t gfp_flags = low_order_gfp_flags;\n                        if (orders[ordindex] > 4)\n                                gfp_flags = high_order_gfp_flags;\n                        if (size_remaining >= (PAGE_SIZE << orders[ordindex]) && max_order >= orders[ordindex]) {\n                                struct page *page = alloc_pages(gfp_flags, orders[ordindex]);\n                                if (page) {\n                                        info = kmalloc(sizeof(*info), GFP_KERNEL);\n                                        info->page = page;\n                                        info->order = orders[ordindex];\n                                        list_add_tail(&info->list, &pages);\n                                        size_remaining -= (1 << info->order) * PAGE_SIZE;\n                                        max_order = info->order;\n                                        infocount++;\n                                        allocated_orders[ordindex] += 1;\n                                        //printk(\"%s, alloc_pages succeeded with order=%d\\n\", __FUNCTION__, orders[ordindex]);\n                                        break;\n                                } else {\n                                        //printk(\"%s, alloc_pages failed with order=%d\\n\", __FUNCTION__, orders[ordindex]);\n                                }\n                        }\n                        //printk(\"%s, alloc_pages skipping order=%d\\n\", __FUNCTION__, orders[ordindex]);\n                }\n                if (!info)\n                        break;\n        }\n\n        printk(\"%s orders_allocated %d:%d, %d:%d, %d:%d\\n\", __FUNCTION__, orders[0], allocated_orders[0],orders[1], allocated_orders[1],orders[2], allocated_orders[2]);\n\n        if (info) {\n                int ret = sg_alloc_table(table, infocount, GFP_KERNEL);\n                if (!ret) {\n                        struct dma_buf *dmabuf;\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4,1,0) || LINUX_VERSION_CODE == KERNEL_VERSION(3,10,0))\n                        struct dma_buf_export_info export_info = {\n                                .exp_name = \"portalmem\",\n                        };\n#endif\n                        sg = table->sgl;\n                        list_for_each_entry_safe(info, tmp_info, &pages, list) {\n                                struct page *page = info->page;\n                                sg_set_page(sg, page, (1 << info->order) * PAGE_SIZE, 0);\n                                sg = sg_next(sg);\n                                list_del(&info->list);\n                                kfree(info);\n                        }\n                        if (IS_ERR_OR_NULL(table)) {\n                                pa_buffer_free(buffer);\n                                return PTR_ERR(table);\n                        }\n                        buffer->sg_table = table;\n                        buffer->size = len;\n                        mutex_init(&buffer->lock);\n                        /* this will set up dma addresses for the sglist -- it is not\n                           technically correct as per the dma api -- a specific\n                           device isn't really taking ownership here.  However, in practice on\n                           our systems the only dma_address space is physical addresses.\n                           Additionally, we can't afford the overhead of invalidating every\n                           allocation via dma_map_sg. The implicit contract here is that\n                           memory is ready for dma, ie if it has a\n                           cached mapping that mapping has been invalidated */\n                        for_each_sg(buffer->sg_table->sgl, sg, buffer->sg_table->nents, infocount){\n#ifdef __arm__\n                                unsigned int length = sg->length;\n                                dma_addr_t start_addr = sg_phys(sg);\n                                dma_addr_t  end_addr = start_addr+length;\n                                outer_clean_range(start_addr, end_addr);\n                                outer_inv_range(start_addr, end_addr);\n#endif\n                                sg_dma_address(sg) = sg_phys(sg);\n                        }\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4,1,0) || LINUX_VERSION_CODE == KERNEL_VERSION(3,10,0))\n                        export_info.ops = &dma_buf_ops;\n                        export_info.size = len;\n                        export_info.flags = O_RDWR;\n                        export_info.priv = buffer;\n                        dmabuf = dma_buf_export(&export_info);\n#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(3,17,0))\n                        dmabuf = dma_buf_export(buffer, &dma_buf_ops, len, O_RDWR , NULL);\n#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(3,11,0))\n                        dmabuf = dma_buf_export(buffer, &dma_buf_ops, len, O_RDWR);\n#else\n#error no dma_buf support known for this kernel version\n#endif\n                        if (IS_ERR(dmabuf))\n                                pa_buffer_free(buffer);\n                        printk(\"pa_get_dma_buf fmem=%p count=%ld\\n\", dmabuf->file, (unsigned long)dmabuf->file->f_count.counter);\n                        return_fd = dma_buf_fd(dmabuf, O_CLOEXEC);\n                        if (return_fd < 0)\n                                dma_buf_put(dmabuf);\n                        return return_fd;\n                }\n                kfree(table);\n        }\n\n        list_for_each_entry(info, &pages, list) {\n                free_buffer_page(info->page, info->order);\n                kfree(info);\n        }\n        kfree(buffer);\n        return -ENOMEM;\n}\n\n/*\n * driver file operations\n */\n\nstatic long pa_unlocked_ioctl(struct file *filep, unsigned int cmd, unsigned long arg)\n{\n        switch (cmd) {\n        case PA_MALLOC: {\n                struct PortalAlloc portalAlloc;\n                if (copy_from_user(&portalAlloc, (void __user *)arg, sizeof(portalAlloc)))\n                        return -EFAULT;\n                return portalmem_dmabuffer_create(portalAlloc);\n        }\n        case PA_ELEMENT_SIZE: {\n                struct PortalElementSize req;\n                struct file *fmem;\n                struct sg_table *sgtable;\n                struct scatterlist *sg;\n                int i = 0;\n                int retsize = 0;  // 0 -> end of sglist items\n\n                if (copy_from_user(&req, (void __user *)arg, sizeof(req)))\n                        return -EFAULT;\n                fmem = fget(req.fd);\n                //printk(\"%s:%d: fget fd=%d fmem=%p\\n\", __FUNCTION__, __LINE__, req.fd, fmem);\n                sgtable = ((struct pa_buffer *)((struct dma_buf *)fmem->private_data)->priv)->sg_table;\n                for_each_sg(sgtable->sgl, sg, sgtable->nents, i) {\n                        if (i == req.index) {\n                                retsize = sg->length;\n                                break;\n                        }\n                }\n                //printk(\"%s:%d: fput fd=%d fmem=%p\\n\", __FUNCTION__, __LINE__, req.fd, fmem);\n                fput(fmem);\n                return retsize;\n        }\n        default:\n                printk(\"pa_unlocked_ioctl ENOTTY cmd=%x\\n\", cmd);\n                return -ENOTTY;\n        }\n        return -ENODEV;\n}\n\nstatic struct file_operations pa_fops = {\n        .owner = THIS_MODULE,\n        .unlocked_ioctl = pa_unlocked_ioctl\n};\n\n/*\n * driver initialization and exit\n */\n\nstatic int __init pa_init(void)\n{\n        struct miscdevice *md = &miscdev;\n        printk(\"PortalAlloc::pa_init\\n\");\n        md->minor = MISC_DYNAMIC_MINOR;\n        md->name = \"portalmem\";\n        md->fops = &pa_fops;\n        md->parent = NULL;\n        misc_register(md);\n        return 0;\n}\n\nstatic void __exit pa_exit(void)\n{\n        struct miscdevice *md = &miscdev;\n        printk(\"PortalAlloc::pa_exit\\n\");\n        misc_deregister(md);\n}\n\nEXPORT_SYMBOL(portalmem_dmabuffer_create);\nEXPORT_SYMBOL(portalmem_dmabuffer_destroy);\n\nmodule_init(pa_init);\nmodule_exit(pa_exit);\n\nMODULE_LICENSE(\"GPL v2\");\nMODULE_DESCRIPTION(DRIVER_DESCRIPTION);\nMODULE_VERSION(DRIVER_VERSION);\n"
  },
  {
    "path": "drivers/portalmem/portalmem.h",
    "content": "/* Copyright (c) 2014 Quanta Research Cambridge, Inc\n * Copyright (c) 2015 Connectal Project\n *\n * Permission is hereby granted, free of charge, to any person obtaining a\n * copy of this software and associated documentation files (the \"Software\"),\n * to deal in the Software without restriction, including without limitation\n * the rights to use, copy, modify, merge, publish, distribute, sublicense,\n * and/or sell copies of the Software, and to permit persons to whom the\n * Software is furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n * DEALINGS IN THE SOFTWARE.\n */\n\n#ifndef __PORTALALLOC_H__\n#define __PORTALALLOC_H__\n\ntypedef struct DmaEntry {\n        long dma_address;\n        unsigned int length; // to match length field in scatterlist.h\n} DmaEntry;\n\ntypedef struct PortalAlloc {\n        size_t len;\n        int cached;\n} PortalAlloc;\n\ntypedef struct PortalElementSize {\n        int fd;\n        int index;\n} PortalElementSize;\n\ntypedef struct {\n        int  index;        /* in param */\n        char md5[33];      /* out param -- asciz */\n        char filename[33]; /* out param -- asciz */\n} PortalSignatureMem;\n\n#define PA_MALLOC              _IOR('B', 14, PortalAlloc)\n#define PA_ELEMENT_SIZE        _IOR('B', 15, PortalElementSize)\n#define PA_SIGNATURE           _IOR('B', 20, PortalSignatureMem)\n\n/**\n * struct pa_buffer - metadata for a particular buffer\n * @size:              size of the buffer\n * @lock:               protects the buffers cnt fields\n * @kmap_cnt:           number of times the buffer is mapped to the kernel\n * @vaddr:              the kenrel mapping if kmap_cnt is not zero\n * @sg_table:           the sg table for the buffer\n */\n#ifdef __KERNEL__\nstruct pa_buffer {\n        size_t          size;\n        struct mutex    lock;\n        int             kmap_cnt;\n        int             cached;\n        void            *vaddr;\n        struct sg_table *sg_table;\n};\nint portalmem_dmabuffer_create(struct PortalAlloc arg);\nint portalmem_dmabuffer_destroy(int fd);\n#endif\n\n#endif /* __PORTALALLOC_H__ */\n"
  },
  {
    "path": "drivers/zynqportal/Makefile",
    "content": "\nV?=0\nifeq ($(V),0)\nQ=@\nelse\nQ=\nendif\nCONNECTALDIR ?= $(PWD)/../..\ninclude $(CONNECTALDIR)/Makefile.version\n\nobj-m += zynqportal.o\n\nDEFCONFIG?=xilinx_zynq_portal_atheros_sdio_defconfig\nCROSS_COMPILE?=arm-linux-gnueabi-\nKROOT?=$(CONNECTALDIR)/../linux-xlnx\n\nccflags-y := -I$(src)/../portalmem -I$(src)/../../cpp -I$(PWD)/../.. -I$(src)/../../generated/cpp \\\n\t-DDRIVER_VERSION=\"\\\"$(VERSION)\\\"\"\n\nzynqportal.ko: zynqportal.h zynqportal.c\n\techo \"$(VERSION)\"\n\t$(Q)$(MAKE) ARCH=arm CROSS_COMPILE=$(CROSS_COMPILE) -C $(KROOT) $(DEFCONFIG)\n\t$(Q)$(MAKE) ARCH=arm CROSS_COMPILE=$(CROSS_COMPILE) -C $(KROOT) oldconfig\n\t$(Q)$(MAKE) -j 8 ARCH=arm CROSS_COMPILE=$(CROSS_COMPILE) -C $(KROOT) zImage\n\t$(Q)$(MAKE) ARCH=arm CROSS_COMPILE=$(CROSS_COMPILE) -C $(KROOT) M=$(PWD) modules\n\nparallellazynqportal.ko: zynqportal.h zynqportal.c\n\techo \"$(VERSION)\"\n\t$(Q)$(MAKE) ARCH=arm CROSS_COMPILE=$(CROSS_COMPILE) -C $(KROOT) parallella_defconfig\n\t$(Q)$(MAKE) ARCH=arm CROSS_COMPILE=$(CROSS_COMPILE) -C $(KROOT) oldconfig\n\t$(Q)$(MAKE) -j 8 ARCH=arm CROSS_COMPILE=$(CROSS_COMPILE) -C $(KROOT) LOADADDR=0x8000 uImage\n\t$(Q)$(MAKE) ARCH=arm CROSS_COMPILE=$(CROSS_COMPILE) -C $(KROOT) M=$(PWD) modules\n\nclean:\n\t$(Q)$(MAKE) ARCH=arm CROSS_COMPILE=$(CROSS_COMPILE) -C $(KROOT) M=$(PWD) clean\n"
  },
  {
    "path": "drivers/zynqportal/zynqportal.c",
    "content": "/*\n * Generic bridge to memory-mapped hardware\n *\n * Author: Jamey Hicks <jamey.hicks@gmail.com>\n *\n * This file is licensed under the terms of the GNU General Public License\n * version 2.  This program is licensed \"as is\" without any warranty of any\n * kind, whether express or implied.\n */\n\n#define DEBUG\n#include <linux/version.h>\n#include <linux/module.h>\n#include <linux/kernel.h>\n#include <linux/device.h>\n#include <linux/fs.h>\n#include <linux/interrupt.h>\n#include <linux/of.h>\n#include <linux/poll.h>\n#include <linux/uaccess.h>\n#include <linux/miscdevice.h>\n#include <linux/mutex.h>\n#include <linux/platform_device.h>\n#include <linux/sched.h>\n#include <linux/clk.h>\n#include <linux/ioctl.h>\n#include <linux/dma-buf.h>\n#include <linux/vmalloc.h>\n#include <linux/slab.h>\n#include <linux/scatterlist.h>\n#include <linux/workqueue.h>\n#include <linux/delay.h>\n#ifdef __arm__\n#include <asm/cacheflush.h> // cache_flush_all\n#include <asm/outercache.h> // outer_flush_*\n#endif\n\n#include \"zynqportal.h\"\n#define CONNECTAL_DRIVER_CODE\n#include \"../../cpp/dmaSendFd.h\"\n#include \"../../cpp/portalKernel.h\"\n\n#define DRIVER_NAME        \"zynqportal\"\n#define DRIVER_DESCRIPTION \"Generic userspace hardware bridge\"\n#define STATUS_OFFSET 0x000\n#define MASK_OFFSET 0x004\n#define NUM_TILES_OFFSET 0x008\n#define IID_OFFSET 0x010\n#define NUM_PORTALS_OFFSET 0x014\n#define MSB_OFFSET 0x018\n#define LSB_OFFSET 0x01C\n#define MAX_NUM_PORTALS 16\n#define MAX_NUM_TILES   2\n\n#ifdef DEBUG // was KERN_DEBUG\n#define driver_devel(format, ...) \\\n        do { \\\n                printk(format, ## __VA_ARGS__); \\\n        } while (0)\n#else\n#define driver_devel(format, ...)\n#endif\n\nstruct pmentry {\n\tstruct file *fmem;\n\tint          id;\n\tstruct list_head pmlist;\n};\n\nstruct portal_data {\n\tstruct miscdevice misc; // use container_of to get (struct portal_data *) from (struct miscdevice *)\n        wait_queue_head_t wait_queue;\n        dma_addr_t        dev_base_phys;\n        void             *map_base;\n        char              name[128];\n        char              irqname[128];\n\tstruct list_head pmlist;;\n};\n\nstruct connectal_data{\n  struct miscdevice  misc; /* must be first element (pointer passed to misc_register) */\n  unsigned int       portal_irq;\n  struct portal_data portald[MAX_NUM_TILES][MAX_NUM_PORTALS + 1];\n};\n\nstatic DEFINE_MUTEX(connectal_mutex);\n/* anyone should be able to get PORTAL_DIRECTORY_COUNTER */\n// FIXME: directory_virt = ws.portal_data;\n#define DIRECTORY_VIRT ((void *)ws.connectal_data->portald[0])\nstatic PortalInterruptTime inttime;\nstatic int flush = 0;\n\nstatic struct {\n  struct connectal_data *connectal_data;\n} ws;\nstatic struct workqueue_struct *wq = 0;\nstatic void connectal_work_handler(struct work_struct *__xxx);\nstatic DECLARE_DELAYED_WORK(connectal_work, connectal_work_handler);\n\n/*\n * Local helper functions\n */\n\nstatic irqreturn_t portal_isr(int irq, void *dev_id)\n{\n\t// request_irq used the portal_data pointer as dev_id;\n        struct portal_data *portal_data = (struct portal_data *)dev_id;\n        irqreturn_t rc = IRQ_NONE;\n\n        //driver_devel(\"%s %s %d %p\\n\", __func__, portal_data->misc.name, irq, dev_id);\n        if (portal_data->name[0]\n         && readl((void *)(STATUS_OFFSET + (unsigned long) portal_data->map_base))) {\n                inttime.msb = readl(DIRECTORY_VIRT + MSB_OFFSET);\n                inttime.lsb = readl(DIRECTORY_VIRT + LSB_OFFSET);\n                // disable interrupt.  this will be re-enabled by user mode\n                // driver  after all the HW->SW FIFOs have been emptied\n                writel(0, (void *)(MASK_OFFSET + (unsigned long) portal_data->map_base));\n                wake_up_interruptible(&portal_data->wait_queue);\n                rc = IRQ_HANDLED;\n        }\n        return rc;\n}\n\n/*\n * file_operations functions\n */\nstatic int portal_open(struct inode *inode, struct file *filep)\n{\n        struct portal_data *portal_data = container_of((struct miscdevice *)filep->private_data, struct portal_data, misc);\n        init_waitqueue_head(&portal_data->wait_queue);\n        return 0;\n}\n\nlong portal_unlocked_ioctl(struct file *filep, unsigned int cmd, unsigned long arg)\n{\n        struct portal_data *portal_data = container_of((struct miscdevice *)filep->private_data, struct portal_data, misc);\n        switch (cmd) {\n        case PORTAL_SET_FCLK_RATE: {\n                PortalClockRequest request;\n                char clkname[32];\n                int status = 0;\n                struct clk *fclk = NULL;\n\n                if (copy_from_user(&request, (void __user *)arg, sizeof(request)))\n                        return -EFAULT;\n\n                #if LINUX_VERSION_CODE < KERNEL_VERSION(3,17,0)\n                snprintf(clkname, sizeof(clkname), \"FPGA%d\", request.clknum);\n                fclk = clk_get_sys(clkname, NULL);\n                #else\n                snprintf(clkname, sizeof(clkname), \"fclk%d\", request.clknum);\n                fclk = clk_get(portal_data->misc.this_device, clkname);\n                #endif\n                printk(KERN_INFO \"[%s:%d] fclk %s %p\\n\", __FUNCTION__, __LINE__, clkname, fclk);\n                if (IS_ERR_OR_NULL(fclk))\n                        return -ENODEV;\n                request.actual_rate = clk_round_rate(fclk, request.requested_rate);\n                printk(KERN_INFO \"%s requested rate %ld actual rate %ld\\n\",\n                    __FUNCTION__, request.requested_rate, request.actual_rate);\n                if ((status = clk_set_rate(fclk, request.actual_rate))) {\n                        printk(KERN_INFO \"[%s:%d] err\\n\", __FUNCTION__, __LINE__);\n                        return status;\n                }\n                if (copy_to_user((void __user *)arg, &request, sizeof(request)))\n                        return -EFAULT;\n                return 0;\n                }\n                break;\n        case PORTAL_SEND_FD: {\n                /* pushd down allocated fd */\n                PortalSendFd sendFd;\n\t\tstruct pmentry *pmentry;\n                PortalInternal devptr = {.map_base = portal_data->map_base, .transport=&kernelfunc};\n\n                int err = copy_from_user(&sendFd, (void __user *) arg, sizeof(sendFd));\n                if (err)\n                    break;\n                printk(\"[%s:%d] PORTAL_SEND_FD fd 0x%x id 0x%x  **\\n\", __FUNCTION__, __LINE__, sendFd.fd, sendFd.id);\n\t\tpmentry = (struct pmentry *)kzalloc(sizeof(struct pmentry), GFP_KERNEL);\n                if (!pmentry)\n                        return -EFAULT;\n\t\tINIT_LIST_HEAD(&pmentry->pmlist);\n\t\tmutex_lock(&connectal_mutex);\n\t\tpmentry->fmem = fget(sendFd.fd);\n\t\tpmentry->id   = sendFd.id;\n\t\tlist_add(&pmentry->pmlist, &portal_data->pmlist);\n                err = send_fd_to_portal(&devptr, sendFd.fd, sendFd.id, 0);\n\t\tmutex_unlock(&connectal_mutex);\n                if (err < 0)\n                    break;\n                return 0;\n                }\n\tcase PORTAL_DEREFERENCE: {\n\t\tint id = arg;\n\t\tstruct list_head *pmlist, *n;\n                PortalInternal devptr = {.map_base = portal_data->map_base, .transport=&kernelfunc};\n\t\tMMURequest_idReturn(&devptr, id);\n\t\tlist_for_each_safe(pmlist, n, &portal_data->pmlist) {\n\t\t\tstruct pmentry *pmentry = list_entry(pmlist, struct pmentry, pmlist);\n\t\t\tif (pmentry->id == id) {\n\t\t\t\tprintk(\"%s:%d releasing portalmem object %d fmem=%p\\n\", __FUNCTION__, __LINE__, id, pmentry->fmem);\n\t\t\t\tfput(pmentry->fmem);\n\t\t\t\tlist_del(&pmentry->pmlist);\n\t\t\t\tkfree(pmentry);\n\t\t\t\treturn 0;\n\t\t\t}\n\t\t}\n\t\treturn -ENOENT;\n\t} break;\n        case PORTAL_DCACHE_FLUSH_INVAL: {\n  \t        flush = 1;\n\t} // fall through\n\tcase PORTAL_DCACHE_INVAL: {\n                struct scatterlist *sg;\n                PortalCacheRequest cacheReq;\n                struct file *fmem;\n\t\tstruct dma_buf *dma_buf;\n\t\tstruct pa_buffer *pa_buffer;\n                struct sg_table *sgtable;\n\t\tlong offset = 0;\n                int i;\n\t\tint verbose_flush = 0;\n\t\tvoid *virt;\n\t\tlong flush_offset;\n\t\tlong flush_length;\n                int err;\n\n\t\tif (verbose_flush)\n\t\t        printk(\"[%s:%d] portal dcache flush=%d\\n\", __FUNCTION__, __LINE__, flush);\n                err = copy_from_user(&cacheReq, (void __user *) arg, sizeof(cacheReq));\n                if (err)\n\t\t\tbreak;\n\t\tif (verbose_flush)\n\t\t        printk(\"[%s:%d] portal fd %d\\n\", __FUNCTION__, __LINE__, cacheReq.fd);\n\t\tfmem = fget(cacheReq.fd);\n\t\tif (verbose_flush)\n\t\t        printk(\"[%s:%d] portal fmem %p\\n\", __FUNCTION__, __LINE__, fmem);\n\t\tif (!fmem) {\n\t\t\tprintk(\"[%s:%d] invalid fd %d\\n\", __FUNCTION__, __LINE__, cacheReq.fd);\n\t\t\treturn -EINVAL;\n\t\t}\n\n\t\tdma_buf = (struct dma_buf *)fmem->private_data;\n\t\tif (verbose_flush)\n\t\t        printk(\"[%s:%d] portal dma_buf %p\\n\", __FUNCTION__, __LINE__, dma_buf);\n\t\tpa_buffer = ((struct pa_buffer *)(dma_buf)->priv);\n\t\tif (verbose_flush)\n\t\t        printk(\"[%s:%d] portal pa_buffer %p\\n\", __FUNCTION__, __LINE__, pa_buffer);\n\t\tsgtable = pa_buffer->sg_table;\n\t\tif (verbose_flush)\n\t\t        printk(\"[%s:%d] portal sgtable %p\\n\", __FUNCTION__, __LINE__, sgtable);\n\t\tvirt = pa_buffer->vaddr;\n\t\tflush_offset = cacheReq.base - virt;\n\t\tflush_length = cacheReq.len;\n\t\tif (verbose_flush)\n\t\t\tprintk(\"[%s:%d] fd %d flush %d base %p virt %p flush_offset %lx flush_length %lx\\n\", __FUNCTION__, __LINE__,\n\t\t\t       cacheReq.fd, flush,\n\t\t\t       cacheReq.base, virt, flush_offset, flush_length);\n\n\t\tflush_cache_all();\n\n                for_each_sg(sgtable->sgl, sg, sgtable->nents, i) {\n\t\t\tunsigned int length = sg->length;\n\t\t\tdma_addr_t start_addr = sg_phys(sg);\n\t\t\tdma_addr_t end_addr = start_addr+length;\n\t\t\tlong end_offset = offset + length;\n\t\t\tif (flush_length && offset <= flush_offset && flush_offset < end_offset) {\n\t\t\t\tlong delta = (flush_offset - offset);\n\t\t\t\tstart_addr += delta;\n\t\t\t\tlength -= delta;\n\t\t\t\tif (flush_length < length) {\n\t\t\t\t        if (verbose_flush)\n\t\t\t\t\t        printk(\"last segment: adjusting end_addr\\n\");\n\t\t\t\t\tend_addr = start_addr + flush_length;\n\t\t\t\t}\n\n\t\t\t\tif (verbose_flush) {\n\t\t\t\t\tprintk(\"[%s:%d] start %lx end %lx len %lx delta %lx flush_length %lx\\n\",\n\t\t\t\t\t       __FUNCTION__, __LINE__, (long)start_addr, (long)end_addr, (long)length, (long)delta, flush_length);\n\t\t\t\t\tprintk(\"[%s:%d]         start_offset %lx end_offset %lx flush_offset %lx\\n\",\n\t\t\t\t\t       __FUNCTION__, __LINE__, offset, end_offset, flush_offset);\n\t\t\t\t}\n#ifdef __arm__\n\t\t\t\tif (flush) {\n\t\t\t\t\t//flush_user_range(virt, virt+length, 0);\n\t\t\t\t\touter_flush_range(start_addr, end_addr);\n\t\t\t\t} else {\n\t\t\t\t\touter_inv_range(start_addr, end_addr);\n\t\t\t\t}\n#endif\n\t\t\t\tflush_offset += length;\n\t\t\t\tflush_length -= length;\n\t\t\t}\n\t\t\toffset += sg->length;\n                }\n                fput(fmem);\n\t\tflush = 0;\n                return 0;\n                }\n        case PORTAL_DIRECTORY_READ:\n                return readl(DIRECTORY_VIRT + arg);\n        case PORTAL_INTERRUPT_TIME:\n                if (copy_to_user((void __user *)arg, &inttime, sizeof(inttime)))\n                        return -EFAULT;\n                return 0;\n        default:\n                printk(\"portal_unlocked_ioctl ENOTTY cmd=%x\\n\", cmd);\n                return -ENOTTY;\n        }\n        return -ENODEV;\n}\n\nint portal_mmap(struct file *filep, struct vm_area_struct *vma)\n{\n        struct portal_data *portal_data = container_of((struct miscdevice *)filep->private_data, struct portal_data, misc);\n        if (vma->vm_pgoff > (~0UL >> PAGE_SHIFT))\n                return -EINVAL;\n        vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);\n        vma->vm_pgoff = portal_data->dev_base_phys >> PAGE_SHIFT;\n        vma->vm_flags |= VM_IO;\n#if LINUX_VERSION_CODE < KERNEL_VERSION(3,9,0)\n        vma->vm_flags |= VM_RESERVED;\n#endif\n        if (io_remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,\n                        vma->vm_end - vma->vm_start, vma->vm_page_prot))\n                return -EAGAIN;\n        return 0;\n}\n\nunsigned int portal_poll (struct file *filep, poll_table *poll_table)\n{\n        struct portal_data *portal_data = container_of((struct miscdevice *)filep->private_data, struct portal_data, misc);\n        poll_wait(filep, &portal_data->wait_queue, poll_table);\n\tif (readl((void *)(STATUS_OFFSET + (unsigned long) portal_data->map_base)))\n\t  return POLLIN | POLLRDNORM; /* when we wake up, always return back to user */\n\treturn 0;\n}\n\nstatic int portal_release(struct inode *inode, struct file *filep)\n{\n        struct portal_data *portal_data = container_of((struct miscdevice *)filep->private_data, struct portal_data, misc);\n\tPortalInternal devptr = {.map_base = portal_data->map_base, .transport=&kernelfunc};\n\tstruct list_head *pmlist;\n        driver_devel(\"%s inode=%p filep=%p\\n\", __func__, inode, filep);\n        if (portal_data->name[0]) {\n                // disable interrupt\n                writel(0, (void *)(STATUS_OFFSET + (unsigned long) portal_data->map_base));\n        }\n        init_waitqueue_head(&portal_data->wait_queue);\n\tlist_for_each(pmlist, &portal_data->pmlist) {\n\t\tstruct pmentry *pmentry = list_entry(pmlist, struct pmentry, pmlist);\n\t\tprintk(\"    returning id=%d fmem=%p\\n\", pmentry->id, pmentry->fmem);\n\t\tMMURequest_idReturn(&devptr, pmentry->id);\n\t\tfput(pmentry->fmem);\n\t\tkfree(pmentry);\n\t}\n\tINIT_LIST_HEAD(&portal_data->pmlist);\n        return 0;\n}\n\nstatic const struct file_operations portal_fops = {\n        .owner = THIS_MODULE,\n        .open = portal_open,\n        .mmap = portal_mmap,\n        .unlocked_ioctl = portal_unlocked_ioctl,\n        .poll = portal_poll,\n        .release = portal_release,\n};\n\nstatic int remove_portal_devices(struct connectal_data *connectal_data)\n{\n  int fpn, t;\n  for(t = 0; t < MAX_NUM_TILES; t++)\n    for (fpn = 0; fpn < MAX_NUM_PORTALS; fpn++) {\n      if (connectal_data->portald[t][fpn].name[0])\n\tmisc_deregister(&connectal_data->portald[t][fpn].misc);\n      connectal_data->portald[t][fpn].name[0] = 0;\n    }\n  return 0;\n}\n\n// this is called with connectal_mutex locked\nstatic void connectal_work_handler(struct work_struct *__xxx)\n{\n  int num_tiles = 0, num_portals = 0, fpn, t = 0;\n  struct device_node *of_node = ws.connectal_data->misc.this_device->of_node;\n  remove_portal_devices(ws.connectal_data);\n  do{\n    fpn = 0;\n    do {\n      int rc;\n      struct portal_data *portal_data = &ws.connectal_data->portald[t][fpn];\n      if(fpn==0){\n\tnum_portals = readl(portal_data->map_base+NUM_PORTALS_OFFSET);\n\tif(t==0)\n\t  num_tiles = readl(portal_data->map_base+NUM_TILES_OFFSET);\n      } else {\n\tif(num_portals != readl(portal_data->map_base+NUM_PORTALS_OFFSET))\n\t  driver_devel(\"%s: num_portals mismatch. Expected %d read %d\\n\", __func__, num_portals, readl(portal_data->map_base+NUM_PORTALS_OFFSET));;\n\tif(num_tiles   != readl(portal_data->map_base+NUM_TILES_OFFSET))\n\t  driver_devel(\"%s: num_tiles mismatch. Expected %d read %d\\n\", __func__, num_tiles, readl(portal_data->map_base+NUM_TILES_OFFSET));;\n      }\n      sprintf(portal_data->name, \"portal_b%dt%dp%d\", 0, t, readl(portal_data->map_base+IID_OFFSET));\n      driver_devel(\"%s: t=%d fpn=%08x top=%d name=%s\\n\", __func__, t, fpn, fpn==num_portals, portal_data->misc.name);\n      portal_data->misc.minor = MISC_DYNAMIC_MINOR;\n      rc = misc_register( &portal_data->misc);\n      portal_data->misc.this_device->of_node = of_node;\n      driver_devel(\"%s: rc=%d minor=%d\\n\", __func__, rc, portal_data->misc.minor);\n      if (fpn+1==num_portals)\n\tbreak;\n      fpn++;\n    } while (fpn < num_portals && fpn < MAX_NUM_PORTALS);\n    if (fpn > MAX_NUM_PORTALS - 1) {\n      printk(KERN_INFO \"%s: MAX_NUM_PORTALS exceeded\", __func__);\n    }\n    t++;\n  } while (t < num_tiles && t < MAX_NUM_TILES);\n  mutex_unlock(&connectal_mutex);\n}\n\nstatic int connectal_open(struct inode *inode, struct file *filep)\n{\n  driver_devel(\"%s:%d\\n\", __func__, __LINE__);\n  mutex_lock(&connectal_mutex);\n  queue_delayed_work(wq, &connectal_work, msecs_to_jiffies(0));\n  return 0;\n}\n\nlong connectal_unlocked_ioctl(struct file *filep, unsigned int cmd, unsigned long arg)\n{\n        switch (cmd) {\n#ifdef CONFIG_CLKDEV_LOOKUP\n        case PORTAL_SET_FCLK_RATE: {\n                PortalClockRequest request;\n                char clkname[32];\n                int status = 0;\n                struct clk *fclk = NULL;\n\n                if (copy_from_user(&request, (void __user *)arg, sizeof(request)))\n                        return -EFAULT;\n                snprintf(clkname, sizeof(clkname), \"FPGA%d\", request.clknum);\n                fclk = clk_get_sys(clkname, NULL);\n                printk(KERN_INFO \"[%s:%d] fclk %s %p\\n\", __FUNCTION__, __LINE__, clkname, fclk);\n                if (!fclk)\n                        return -ENODEV;\n                request.actual_rate = clk_round_rate(fclk, request.requested_rate);\n                printk(KERN_INFO \"%s requested rate %ld actual rate %ld\\n\",\n                    __FUNCTION__, request.requested_rate, request.actual_rate);\n                if ((status = clk_set_rate(fclk, request.actual_rate))) {\n                        printk(KERN_INFO \"[%s:%d] err\\n\", __FUNCTION__, __LINE__);\n                        return status;\n                }\n                if (copy_to_user((void __user *)arg, &request, sizeof(request)))\n                        return -EFAULT;\n                return 0;\n                }\n\n                break;\n#endif\n        case PORTAL_DCACHE_FLUSH_INVAL: {\n  \t        flush = 1;\n\t} // fall through\n\tcase PORTAL_DCACHE_INVAL: {\n                struct scatterlist *sg;\n                PortalCacheRequest cacheReq;\n                struct file *fmem;\n\t\tstruct pa_buffer *pa_buffer;\n                struct sg_table *sgtable;\n\t\tlong offset = 0;\n                int i;\n\t\tint verbose_flush = 0;\n\t\tvoid *virt;\n\t\tlong flush_offset;\n\t\tlong flush_length;\n\n                int err = copy_from_user(&cacheReq, (void __user *) arg, sizeof(cacheReq));\n                if (err)\n                    break;\n\t\tif (verbose_flush)\n\t\t        printk(\"[%s:%d] portal fd %d\\n\", __FUNCTION__, __LINE__, cacheReq.fd);\n\t\tfmem = fget(cacheReq.fd);\n\t\tpa_buffer = ((struct pa_buffer *)((struct dma_buf *)fmem->private_data)->priv);\n\t\tsgtable = pa_buffer->sg_table;\n\t\tvirt = pa_buffer->vaddr;\n\t\tflush_offset = cacheReq.base - virt;\n\t\tflush_length = cacheReq.len;\n\t\tif (verbose_flush)\n\t\t\tprintk(\"[%s:%d] fd %d flush %d base %p virt %p flush_offset %lx flush_length %lx\\n\", __FUNCTION__, __LINE__,\n\t\t\t       cacheReq.fd, flush,\n\t\t\t       cacheReq.base, virt, flush_offset, flush_length);\n\n\t\tflush_cache_all();\n\n                for_each_sg(sgtable->sgl, sg, sgtable->nents, i) {\n\t\t\tunsigned int length = sg->length;\n\t\t\tdma_addr_t start_addr = sg_phys(sg);\n\t\t\tdma_addr_t end_addr = start_addr+length;\n\t\t\tlong end_offset = offset + length;\n\t\t\tif (flush_length && offset <= flush_offset && flush_offset < end_offset) {\n\t\t\t\tlong delta = (flush_offset - offset);\n\t\t\t\tstart_addr += delta;\n\t\t\t\tlength -= delta;\n\t\t\t\tif (flush_length < length) {\n\t\t\t\t\tprintk(\"last segment: adjusting end_addr\\n\");\n\t\t\t\t\tend_addr = start_addr + flush_length;\n\t\t\t\t}\n\n\t\t\t\tif (verbose_flush) {\n\t\t\t\t\tprintk(\"[%s:%d] start %lx end %lx len %lx delta %lx flush_length %lx\\n\",\n\t\t\t\t\t       __FUNCTION__, __LINE__, (long)start_addr, (long)end_addr, (long)length, (long)delta, flush_length);\n\t\t\t\t\tprintk(\"[%s:%d]         start_offset %lx end_offset %lx flush_offset %lx\\n\",\n\t\t\t\t\t       __FUNCTION__, __LINE__, offset, end_offset, flush_offset);\n\t\t\t\t}\n#ifdef __arm__\n\t\t\t\tif (flush) {\n\t\t\t\t\t//flush_user_range(virt, virt+length, 0);\n\t\t\t\t\touter_flush_range(start_addr, end_addr);\n\t\t\t\t} else {\n\t\t\t\t\touter_inv_range(start_addr, end_addr);\n\t\t\t\t}\n#endif\n\t\t\t\tflush_offset += length;\n\t\t\t\tflush_length -= length;\n\t\t\t}\n\t\t\toffset += sg->length;\n                }\n                fput(fmem);\n\t\tflush = 0;\n                return 0;\n                }\n        default:\n                printk(\"portal_unlocked_ioctl ENOTTY cmd=%x\\n\", cmd);\n                return -ENOTTY;\n        }\n        return -ENODEV;\n}\n\nstatic ssize_t connectal_read(struct file *filp,\n      char *buffer, size_t length, loff_t *offset)\n{\n  driver_devel(\"%s:%d\\n\", __func__, __LINE__);\n  mutex_lock(&connectal_mutex);\n  mutex_unlock(&connectal_mutex);\n  return 0;\n}\n\nstatic const struct file_operations connectal_fops = {\n        .owner          = THIS_MODULE,\n        .open           = connectal_open,\n\t.read           = connectal_read,\n        .unlocked_ioctl = connectal_unlocked_ioctl,\n};\n\nstatic int connectal_of_probe(struct platform_device *pdev)\n{\n  u32 size;\n  int rc, fpn, t = 0;\n  struct connectal_data *connectal_data;\n  const char *dname = (char *)of_get_property(pdev->dev.of_node, \"device-name\", &size);\n  struct resource *reg_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);\n  struct resource *irq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);\n  if (!dname || !reg_res || !irq_res) {\n    pr_err(\"%s: Error getting device-name or resources\\n\", DRIVER_NAME);\n    return -EINVAL;\n  }\n  wq = create_singlethread_workqueue(\"connectal\");\n  if (!wq) {\n    pr_err(\"Error creating workqueue\\n\");\n    return -EINVAL;\n  }\n  mutex_lock(&connectal_mutex);\n  connectal_data = kzalloc(sizeof(struct connectal_data), GFP_KERNEL);\n  connectal_data->misc.name = dname;\n  connectal_data->misc.minor = MISC_DYNAMIC_MINOR;\n  connectal_data->misc.fops = &connectal_fops;\n  connectal_data->portal_irq = irq_res->start;\n  rc = misc_register(&connectal_data->misc);\n  connectal_data->misc.this_device->of_node = pdev->dev.of_node;\n  driver_devel(\"%s: name=%s rc=%d minor=%d\\n\", __func__, connectal_data->misc.name, rc, connectal_data->misc.minor);\n  dev_set_drvdata(&pdev->dev, connectal_data);\n  ws.connectal_data = connectal_data;\n  for(t = 0; t < MAX_NUM_TILES; t++)\n    for (fpn = 0; fpn < MAX_NUM_PORTALS; fpn++) {\n      struct portal_data *portal_data = &connectal_data->portald[t][fpn];\n      portal_data->dev_base_phys = reg_res->start+((t * TILE_BASE_OFFSET)+(fpn*PORTAL_BASE_OFFSET));\n      portal_data->map_base = ioremap_nocache(portal_data->dev_base_phys, PORTAL_BASE_OFFSET);\n      portal_data->misc.name = portal_data->name;\n      portal_data->misc.fops = &portal_fops;\n      INIT_LIST_HEAD(&portal_data->pmlist);\n      sprintf(portal_data->irqname, \"zynqportal_b%dt%dp%d\", 0, t, fpn);\n      if (request_irq(connectal_data->portal_irq, portal_isr,\n\t\t      IRQF_TRIGGER_HIGH | IRQF_SHARED , portal_data->irqname, portal_data)) {\n\tprintk(\"%s Failed to register irq\\n\", __func__);\n      }\n    }\n  mutex_unlock(&connectal_mutex);\n  return 0;\n}\n\nstatic int connectal_of_remove(struct platform_device *pdev)\n{\n  int fpn, t = 0;\n  struct connectal_data* connectal_data = dev_get_drvdata(&pdev->dev);\n  driver_devel(\"%s: %s\\n\",__FUNCTION__, pdev->name);\n  mutex_lock(&connectal_mutex);\n  for(t = 0; t < MAX_NUM_TILES; t++)\n    for (fpn = 0; fpn < MAX_NUM_PORTALS; fpn++)\n      free_irq(connectal_data->portal_irq, &connectal_data->portald[t][fpn]);\n  remove_portal_devices(connectal_data);\n  misc_deregister(&connectal_data->misc);\n  dev_set_drvdata(&pdev->dev, NULL);\n  cancel_delayed_work_sync(&connectal_work);\n  destroy_workqueue(wq);\n  kfree(connectal_data);\n  mutex_unlock(&connectal_mutex);\n  return 0;\n}\n\nstatic struct of_device_id connectal_of_match[]\n#if LINUX_VERSION_CODE < KERNEL_VERSION(3,9,0)\n      __devinitdata\n#endif\n      = {\n        { .compatible = \"linux,ushw-bridge-0.01.a\" }, /* old name */\n        { .compatible = \"linux,portal-0.01.a\" },\n        {/* end of table */},\n};\nMODULE_DEVICE_TABLE(of, connectal_of_match);\n\nstatic struct platform_driver connectal_of_driver = {\n        .probe = connectal_of_probe,\n        .remove = connectal_of_remove,\n        .driver = {\n                .owner = THIS_MODULE,\n                .name = DRIVER_NAME,\n                .of_match_table = connectal_of_match,\n        },\n};\n\n/*\n * Module functions\n */\nstatic int __init connectal_of_init(void)\n{\n        if (platform_driver_register(&connectal_of_driver)) {\n                pr_err(\"Error portal driver registration\\n\");\n                return -ENODEV;\n        }\n        return 0;\n}\n\nstatic void __exit connectal_of_exit(void)\n{\n        platform_driver_unregister(&connectal_of_driver);\n}\n\n#ifndef MODULE\nlate_initcall(connectal_of_init);\n#else\nmodule_init(connectal_of_init);\nmodule_exit(connectal_of_exit);\n#endif\n\nMODULE_LICENSE(\"GPL v2\");\nMODULE_DESCRIPTION(DRIVER_DESCRIPTION);\nMODULE_VERSION(DRIVER_VERSION);\n"
  },
  {
    "path": "drivers/zynqportal/zynqportal.h",
    "content": "/*\n * Generic userspace hardware bridge\n *\n * Author: Jamey Hicks <jamey.hicks@gmail.com>\n *\n * 2012 (c) Jamey Hicks\n *\n * This file is licensed under the terms of the GNU General Public License\n * version 2.  This program is licensed \"as is\" without any warranty of any\n * kind, whether express or implied.\n */\n\n#ifndef __PORTAL_H__\n#define __PORTAL_H__\n\ntypedef struct {\n    int clknum;\n    long requested_rate;\n    long actual_rate;\n} PortalClockRequest;\n\ntypedef struct {\n    int fd;\n    int id;\n} PortalSendFd;\n\ntypedef struct {\n    uint32_t msb;\n    uint32_t lsb;\n} PortalInterruptTime;\n\ntypedef struct {\n  int fd;\n  void *base;\n  size_t len;\n} PortalCacheRequest;\n\ntypedef struct {\n    int  index;        /* in param */\n    char md5[33];      /* out param -- asciz */\n    char filename[33]; /* out param -- asciz */\n} PortalSignature;\n\n#define PORTAL_SET_FCLK_RATE      _IOWR('B', 40, PortalClockRequest)\n#define PORTAL_SEND_FD            _IOR('B',  42, PortalSendFd)\n#define PORTAL_DCACHE_FLUSH_INVAL _IOR('B',  43, PortalCacheRequest)\n#define PORTAL_DIRECTORY_READ     _IOR('B',  44, unsigned long)\n#define PORTAL_INTERRUPT_TIME     _IOR('B',  45, PortalInterruptTime)\n#define PORTAL_DCACHE_INVAL       _IOR('B',  46, PortalCacheRequest)\n#define PORTAL_DEREFERENCE        _IOR('B',  47, int)\n#define PORTAL_SIGNATURE          _IOR('B',  47, PortalSignature)\n\n#endif /* __PORTAL_H__ */\n"
  },
  {
    "path": "etc/modules-load.d/connectal.conf",
    "content": "portalmem\n"
  },
  {
    "path": "etc/udev/rules.d/51-connectaltty.rules",
    "content": "# For Ubuntu 12.04\n# zedboard\nSUBSYSTEM==\"usb\", ATTR{idVendor}==\"04b4\", ATTR{idProduct}==\"0008\", MODE=\"0666\", OWNER=\"jenkins\"\nKERNEL==\"ttyACM*\", ATTRS{idVendor}==\"04b4\", ATTRS{idProduct}==\"0008\", MODE:=\"0666\"\n# zc702\nSUBSYSTEM==\"usb\", ATTR{idVendor}==\"10c4\", ATTR{idProduct}==\"ea60\", MODE=\"0666\", OWNER=\"jenkins\"\nKERNEL==\"ttyUSB*\", ATTRS{idVendor}==\"10c4\", ATTRS{idProduct}==\"ea60\", MODE:=\"0666\"\n# zybo\nSUBSYSTEM==\"usb\", ATTR{idVendor}==\"0403\", ATTR{idProduct}==\"6010\", MODE=\"0666\", OWNER=\"jenkins\"\nKERNEL==\"ttyUSB*\", ATTRS{idVendor}==\"0403\", ATTRS{idProduct}==\"6010\", MODE:=\"0666\"\n\n"
  },
  {
    "path": "etc/udev/rules.d/52-altera-usb.rules",
    "content": "\n# Allow users to access Altera Jtag device\nACTION==\"add\", ATTR{idVendor}==\"09fb\", MODE:=\"666\"\n"
  },
  {
    "path": "etc/udev/rules.d/52-connectaltest.rules",
    "content": "#\n# rule for connectal kernel test module\n#\nKERNEL==\"connectaltest\", MODE=\"0666\"\n"
  },
  {
    "path": "etc/udev/rules.d/52-digilent-usb.rules",
    "content": "###########################################################################\n#                                                                         #\n#  52-digilent-usb.rules -- UDEV rules for Digilent USB Devices           #\n#                                                                         #\n###########################################################################\n#  Author: MTA                                                            #\n#  Copyright 2010 Digilent Inc.                                           #\n###########################################################################\n#  File Description:                                                      #\n#                                                                         #\n#  This file contains the rules used by UDEV when creating entries for    #\n#  Digilent USB devices. In order for Digilent's shared libraries and     #\n#  applications to access these devices without root privalages it is     #\n#  necessary for UDEV to create entries for which all users have read     #\n#  and write permission.                                                  #\n#                                                                         #\n#  Usage:                                                                 #\n#                                                                         #\n#  Copy this file to \"/etc/udev/rules.d/\" and execute                     #\n#  \"/sbin/udevcontrol reload_rules\" as root. This only needs to be done   #\n#  immediately after installation. Each time you reboot your system the   #\n#  rules are automatically loaded by UDEV.                                #\n#                                                                         #\n###########################################################################\n#  Revision History:                                                      #\n#                                                                         #\n#  04/15/2010(MTA): created                                               #\n#  02/28/2011(MTA): modified to support FTDI based devices                #\n#  07/10/2012(MTA): modified to work with UDEV versions 098 or newer      #\n#  04/19/2013(MTA): modified mode assignment to use \":=\" insetead of \"=\"  #\n#       so that our permission settings can't be overwritten by other     #\n#       rules files                                                       #\n#                                                                         #\n###########################################################################\n\n# Create \"/dev\" entries for Digilent device's with read and write\n# permission granted to all users.\nATTR{idVendor}==\"1443\", MODE:=\"666\"\nACTION==\"add\", ATTR{idVendor}==\"0403\", ATTR{manufacturer}==\"Digilent\", MODE:=\"666\", RUN+=\"/usr/local/sbin/dftdrvdtch %s{busnum} %s{devnum}\"\n\n# The following rules (if present) cause UDEV to ignore all UEVENTS for\n# which the subsystem is \"usb_endpoint\" and the action is \"add\" or\n# \"remove\". These rules are necessary to work around what appears to be a\n# bug in the Kernel used by Red Hat Enterprise Linux 5/CentOS 5. The Kernel\n# sends UEVENTS to remove and then add entries for the endpoints of a USB\n# device in \"/dev\" each time a process releases an interface. This occurs\n# each time a data transaction occurs. When an FPGA is configured or flash\n# device is written a large number of transactions take place. If the\n# following lines are commented out then UDEV will be overloaded for a long\n# period of time while it tries to process the massive number of UEVENTS it\n# receives from the kernel. Please note that this work around only applies\n# to systems running RHEL5 or CentOS 5 and as a result the rules will only\n# be present on those systems.\n"
  },
  {
    "path": "etc/udev/rules.d/99-pcieportal.rules",
    "content": "# UDev rules for setting up Bluespec emulation device drivers\n\nACTION==\"add\",SUBSYSTEM==\"pci\",ATTR{vendor}==\"0x1be7\", ATTR{device}=\"0xb100\", RUN+=\"/sbin/modprobe -ba pcieportal portalmem\"\nKERNEL==\"portal*\",MODE=\"666\"\nKERNEL==\"xdma*\",MODE=\"666\"\nKERNEL==\"portalmem\",MODE=\"666\"\nKERNEL==\"connectal\",MODE=\"666\"\n"
  },
  {
    "path": "examples/algo1_nandsim/Algo1NandSim.bsv",
    "content": "\nimport GetPut::*;\nimport Connectable::*;\nimport Vector::*;\nimport BuildVector::*;\n\nimport ConnectalConfig::*;\nimport ConnectalMemory::*;\nimport ConnectalMemTypes::*;\nimport MemServer::*;\nimport ConnectalMMU::*;\n\nimport NandSim::*;\nimport Strstr::*;\n\ninterface Algo1NandSim;\n   interface NandCfgRequest   nandCfgRequest;\n   interface MMURequest       nandMMURequest;\n   interface MemServerRequest nandMemServerRequest;\n   interface StrstrRequest    strstrRequest;\n   interface Vector#(2, MemReadClient#(DataBusWidth)) dmaReadClients;\n   interface Vector#(1, MemWriteClient#(DataBusWidth)) dmaWriteClients;\nendinterface\n\n\nmodule mkAlgo1NandSim#(NandCfgIndication nandCfgIndication, MMUIndication nandMMUIndication, MemServerIndication nandSimMemServerIndication, StrstrIndication strstrIndication)(Algo1NandSim);\n\n\n   Strstr#(64,64) strstr <- mkStrstr(strstrIndication);\n\n   NandSim nandSim <- mkNandSim(nandCfgIndication);\n   MMU#(PhysAddrWidth) nandMMU <- mkMMU(0, False, nandMMUIndication);\n   MemServer#(PhysAddrWidth,64,1) nandSimMemServer <- mkMemServer(strstr.haystack_read_client, nil, vec(nandMMU), nandSimMemServerIndication);\n   let nandSimMemCnx <- mkConnection(nandSimMemServer.masters[0], nandSim.memSlave);\n   // rule rl_readReq;\n   //    let req <- nandSimMemServer.masters[0].read_client.readReq.get();\n   //    $display(\"rl_readReq addr=%h\", req.addr);\n   //    nandSim.memSlave.read_server.readReq.put(req);\n   // endrule\n\n   // let readDataCnx  <- mkConnection(nandSimMemServer.masters[0].read_client.readData, nandSim.memSlave.read_server.readData);\n   // let writeReqCnx  <- mkConnection(nandSimMemServer.masters[0].write_client.writeReq, nandSim.memSlave.write_server.writeReq);\n   // let writeDataCnx <- mkConnection(nandSimMemServer.masters[0].write_client.writeData, nandSim.memSlave.write_server.writeData);\n   // let writeDoneCnx <- mkConnection(nandSimMemServer.masters[0].write_client.writeDone, nandSim.memSlave.write_server.writeDone);\n\n   interface dmaReadClients = append(nandSim.readClient, strstr.config_read_client);\n   interface dmaWriteClients = nandSim.writeClient;\n\n   interface nandCfgRequest          = nandSim.request;\n   interface nandMMURequest          = nandMMU.request;\n   interface strstrRequest           = strstr.request;\n   interface nandMemServerRequest    = nandSimMemServer.request;\nendmodule\n"
  },
  {
    "path": "examples/algo1_nandsim/Makefile",
    "content": "\nCONNECTALDIR?=../..\n\nS2H_INTERFACES = NandCfgRequest:Algo1NandSim.nandCfgRequest MMURequest:Algo1NandSim.nandMMURequest MemServerRequest:Algo1NandSim.nandMemServerRequest StrstrRequest:Algo1NandSim.strstrRequest\nH2S_INTERFACES = Algo1NandSim:NandCfgIndication,MMUIndication,MemServerIndication,StrstrIndication\nMEM_READ_INTERFACES = lAlgo1NandSim.dmaReadClients\nMEM_WRITE_INTERFACES = lAlgo1NandSim.dmaWriteClients\n\nBSVFILES = $(CONNECTALDIR)/lib/nandsim/bsv/NandSim.bsv $(CONNECTALDIR)/lib/strstr/bsv/Strstr.bsv Algo1NandSim.bsv\nCPPFILES=test.cpp nandsim.cpp\n\nCONNECTALFLAGS += -D ALGO_NANDSIM\nCONNECTALFLAGS += -D DEGPAR=2\nCONNECTALFLAGS += -I$(CONNECTALDIR)/lib/strstr/cpp\nCONNECTALFLAGS += -I$(CONNECTALDIR)/lib/nandsim/cpp\n\n\ninclude $(CONNECTALDIR)/Makefile.connectal\n"
  },
  {
    "path": "examples/algo1_nandsim/nandsim.cpp",
    "content": "#include <errno.h>\n#include <fcntl.h>\n#include <stdio.h>\n#include <sys/stat.h>\n#include <sys/types.h>\n#include <unistd.h>\n\n#include \"portal.h\"\n#include \"dmaManager.h\"\n#include \"NandCfgRequest.h\"\n#include \"NandCfgIndication.h\"\n\nclass NandCfgIndication : public NandCfgIndicationWrapper\n{\npublic:\n  unsigned int rDataCnt;\n  virtual void readDone(uint32_t v){\n    fprintf(stderr, \"NandSim::readDone v=%x\\n\", v);\n    sem_post(&sem);\n  }\n  virtual void writeDone(uint32_t v){\n    fprintf(stderr, \"NandSim::writeDone v=%x\\n\", v);\n    sem_post(&sem);\n  }\n  virtual void eraseDone(uint32_t v){\n    fprintf(stderr, \"NandSim::eraseDone v=%x\\n\", v);\n    sem_post(&sem);\n  }\n  virtual void configureNandDone(){\n    fprintf(stderr, \"NandSim::configureNandDone\\n\");\n    sem_post(&sem);\n  }\n\n  NandCfgIndication(int id) : NandCfgIndicationWrapper(id) {\n    sem_init(&sem, 0, 0);\n  }\n  void wait() {\n    fprintf(stderr, \"NandSim::wait for semaphore\\n\");\n    sem_wait(&sem);\n  }\nprivate:\n  sem_t sem;\n};\n\nint initNandSim(DmaManager *hostDma)\n{\n    NandCfgRequestProxy *nandcfgRequest = new NandCfgRequestProxy(IfcNames_NandCfgRequestS2H);\n    NandCfgIndication *nandcfgIndication = new NandCfgIndication(IfcNames_NandCfgIndicationH2S);\n\n    int nandBytes = 1 << 12;\n    int nandAlloc = portalAlloc(nandBytes, 0);\n    fprintf(stderr, \"testnandsim::nandAlloc=%d\\n\", nandAlloc);\n    int ref_nandAlloc = hostDma->reference(nandAlloc);\n    fprintf(stderr, \"ref_nandAlloc=%d\\n\", ref_nandAlloc);\n    fprintf(stderr, \"testnandsim::NAND alloc fd=%d ref=%d\\n\", nandAlloc, ref_nandAlloc);\n    nandcfgRequest->configureNand(ref_nandAlloc, nandBytes);\n    nandcfgIndication->wait();\n\n    const char *filename = \"../test.bin\";\n    fprintf(stderr, \"testnandsim::opening %s\\n\", filename);\n    // open up the text file and read it into an allocated memory buffer\n    int data_fd = open(filename, O_RDONLY);\n    if (data_fd < 0) {\n\tfprintf(stderr, \"%s:%d failed to open file %s errno=%d:%s\\n\", __FUNCTION__, __LINE__, filename, errno, strerror(errno));\n\treturn 0;\n    }\n    off_t data_len = lseek(data_fd, 0, SEEK_END);\n    fprintf(stderr, \"%s:%d fd=%d data_len=%ld\\n\", __FUNCTION__, __LINE__, data_fd, data_len);\n    data_len = data_len & ~15; // because we are using a burst length of 16\n    lseek(data_fd, 0, SEEK_SET);\n\n    int dataAlloc = portalAlloc(data_len, 0);\n    char *data = (char *)portalMmap(dataAlloc, data_len);\n    ssize_t read_len = read(data_fd, data, data_len); \n    if(read_len != data_len) {\n\tfprintf(stderr, \"%s:%d::error reading %s %ld %ld\\n\", __FUNCTION__, __LINE__, filename, (long)data_len, (long) read_len);\n\texit(-1);\n    }\n    int ref_dataAlloc = hostDma->reference(dataAlloc);\n\n    // write the contents of data into \"flash\" memory\n    portalCacheFlush(ref_dataAlloc, data, data_len, 1);\n    fprintf(stderr, \"testnandsim::invoking write %08x %08lx\\n\", ref_dataAlloc, (long)data_len);\n    nandcfgRequest->startWrite(ref_dataAlloc, 0, 0, data_len, 16);\n    nandcfgIndication->wait();\n\n    fprintf(stderr, \"%s:%d finished -- data_len=%ld\\n\", __FUNCTION__, __LINE__, data_len);\n    return data_len;\n}\n"
  },
  {
    "path": "examples/algo1_nandsim/test.cpp",
    "content": "/* Copyright (c) 2014 Quanta Research Cambridge, Inc\n *\n * Permission is hereby granted, free of charge, to any person obtaining a\n * copy of this software and associated documentation files (the \"Software\"),\n * to deal in the Software without restriction, including without limitation\n * the rights to use, copy, modify, merge, publish, distribute, sublicense,\n * and/or sell copies of the Software, and to permit persons to whom the\n * Software is furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n * DEALINGS IN THE SOFTWARE.\n */\n#include <fstream>\n#include <iostream>\n#include <errno.h>\n#include <string.h>\n#include <sys/types.h>\n#include <sys/socket.h>\n#include <sys/un.h>\n#include <sys/mman.h>\n#include <assert.h>\n#include <mp.h>\n#include <semaphore.h>\n#include \"dmaManager.h\"\n#include \"MMURequest.h\"\n#include \"MMUIndication.h\"\n#include \"MemServerRequest.h\"\n#include \"MemServerIndication.h\"\n#include \"StrstrIndication.h\"\n#include \"StrstrRequest.h\"\n\nstatic int trace_memory = 1;\nextern \"C\" {\n#include \"drivers/portalmem/portalmem.h\"\n#include \"userReference.h\"\n}\n\n#include \"nandsim.h\"\n#include \"strstr.h\"\n\nclass MMUIndicationNandSim : public MMUIndicationWrapper\n{\n  DmaManager *portalMemory;\n  sem_t sem;\n public:\n  int sglId;\n\n  MMUIndicationNandSim(DmaManager *pm, unsigned int  id, int tile=DEFAULT_TILE) : MMUIndicationWrapper(id,tile), portalMemory(pm) {\n    sem_init(&sem, 0, 0);\n  }\n  void wait() {\n    sem_wait(&sem);\n  }\n\n  virtual void configResp(uint32_t pointer){\n    fprintf(stderr, \"MMUIndication::configResp: %x\\n\", pointer);\n    portalMemory->confResp(pointer);\n  }\n  virtual void error (uint32_t code, uint32_t pointer, uint64_t offset, uint64_t extra) {\n    fprintf(stderr, \"MMUIndication::error(code=0x%x, pointer=0x%x, offset=0x%\"PRIx64\" extra=-0x%\"PRIx64\"\\n\", code, pointer, offset, extra);\n    //if (--mmu_error_limit < 0)\n        exit(-1);\n  }\n  virtual void idResponse(uint32_t sglId){\n    fprintf(stderr, \"MMUIndication::idResponse: %x\\n\", sglId);\n    if (portalMemory)\n      portalMemory->sglIdResp(sglId);\n    this->sglId = sglId;\n    sem_post(&sem);\n  }\n};\n\nclass MemServerIndicationNandSim : public MemServerIndicationWrapper\n{\n  MemServerRequestProxy *memServerRequestProxy;\n  sem_t mtSem;\n  uint64_t mtCnt;\n  void init(){\n    if (sem_init(&mtSem, 0, 0))\n      PORTAL_PRINTF(\"MemServerIndication::init failed to init mtSem\\n\");\n  }\n public:\n  MemServerIndicationNandSim(unsigned int  id, int tile=DEFAULT_TILE) : MemServerIndicationWrapper(id,tile), memServerRequestProxy(NULL) {init();}\n  virtual void addrResponse(uint64_t physAddr){\n    fprintf(stderr, \"DmaIndication::addrResponse(physAddr=%\"PRIx64\")\\n\", physAddr);\n  }\n  virtual void reportStateDbg(const DmaDbgRec rec){\n    fprintf(stderr, \"MemServerIndication::reportStateDbg: {x:%08x y:%08x z:%08x w:%08x}\\n\", rec.x,rec.y,rec.z,rec.w);\n  }\n  virtual void reportMemoryTraffic(uint64_t words){\n    //fprintf(stderr, \"reportMemoryTraffic: words=%\"PRIx64\"\\n\", words);\n    mtCnt = words;\n    sem_post(&mtSem);\n  }\n  virtual void error (uint32_t code, uint32_t pointer, uint64_t offset, uint64_t extra) {\n    fprintf(stderr, \"MemServerIndication::error(code=%x, pointer=%x, offset=%\"PRIx64\" extra=%\"PRIx64\"\\n\", code, pointer, offset, extra);\n    if (--mem_error_limit < 0)\n      exit(-1);\n  }\n  uint64_t receiveMemoryTraffic(){\n    sem_wait(&mtSem);\n    return mtCnt; \n  }\n  uint64_t getMemoryTraffic(const ChannelType rc){\n    assert(memServerRequestProxy);\n    memServerRequestProxy->memoryTraffic(rc);\n    return receiveMemoryTraffic();\n  }\n};\n\nsize_t numBytes = 1 << 10;\n\nextern int initNandSim(DmaManager *hostDma);\n\nint main(int argc, const char **argv)\n{\n  fprintf(stderr, \"Main::%s %s\\n\", __DATE__, __TIME__);\n\n  DmaManager *hostDma = platformInit();\n  MMURequestProxy *nandsimMMU = new MMURequestProxy(IfcNames_MMURequestS2H);\n  DmaManager *nandsimDma = new DmaManager(nandsimMMU);\n\n  StrstrRequestProxy *strstrRequest = new StrstrRequestProxy(IfcNames_StrstrRequestS2H);\n  StrstrIndication *strstrIndication = new StrstrIndication(IfcNames_StrstrIndicationH2S);\n  \n  MMUIndicationNandSim nandsimMMUIndication(nandsimDma,IfcNames_MMUIndicationH2S);\n  MemServerIndicationNandSim nandsimMemServerIndication(IfcNames_MemServerIndicationH2S);\n\n  fprintf(stderr, \"Initializing nandSim...\\n\");\n  int haystack_len = initNandSim(hostDma);\n  int haystack_base = 0;\n  fprintf(stderr, \"haystack_base=%d haystack_len=%d\\n\", haystack_base, haystack_len);\n\n  fprintf(stderr, \"Main::allocating memory...\\n\");\n\n  // allocate memory for strstr data\n  int needleAlloc = portalAlloc(numBytes, 0);\n  int mpNextAlloc = portalAlloc(numBytes, 0);\n  int ref_needleAlloc = hostDma->reference(needleAlloc);\n  int ref_mpNextAlloc = hostDma->reference(mpNextAlloc);\n\n  fprintf(stderr, \"%s:%d %08x %08x\\n\", __FUNCTION__, __LINE__, ref_needleAlloc, ref_mpNextAlloc);\n\n  char *needle = (char *)portalMmap(needleAlloc, numBytes);\n  int *mpNext = (int *)portalMmap(mpNextAlloc, numBytes);\n\n  const char *needle_text = \"ababab\";\n  int needle_len = strlen(needle_text);\n  strncpy(needle, needle_text, needle_len);\n  compute_MP_next(needle, mpNext, needle_len);\n\n  portalCacheFlush(needleAlloc, needle, numBytes, 1);\n  portalCacheFlush(mpNextAlloc, mpNext, numBytes, 1);\n  fprintf(stderr, \"Main::flush and invalidate complete\\n\");\n\n  // request the next sglist identifier from the sglistMMU hardware module\n  // which is used by the mem server accessing flash memory.\n  int id = 0;\n  fprintf(stderr, \"[%s:%d]\\n\", __FUNCTION__, __LINE__);\n  if (1) {\n      MMURequest_idRequest(nandsimDma->priv.sglDevice, 0);\n      sem_wait(&nandsimDma->priv.sglIdSem);\n      id = nandsimDma->priv.sglId;\n  } else {\n      nandsimMMU->idRequest(0);\n      nandsimMMUIndication.wait();\n      id = nandsimMMUIndication.sglId;\n  }\n\n  fprintf(stderr, \"[%s:%d] id=%d\\n\", __FUNCTION__, __LINE__, id);\n  // pairs of ('offset','size') pointing to space in nandsim memory\n  // this is unsafe.  To do it properly, we should get this list from\n  // nandsim_exe or from the kernel driver.  This code here might overrun\n  // the backing store allocated by nandsim_exe.\n  RegionRef region[] = {{0, 0x100000}, {0x100000, 0x100000}};\n  fprintf(stderr, \"[%s:%d]\\n\", __FUNCTION__, __LINE__);\n  int ref_haystackInNandMemory = send_reference_to_portal(nandsimDma->priv.sglDevice, sizeof(region)/sizeof(region[0]), region, id);\n  sem_wait(&(nandsimDma->priv.confSem));\n  fprintf(stderr, \"[%s:%d] %08x\\n\", __FUNCTION__, __LINE__, ref_haystackInNandMemory);\n\n  // at this point, ref_needleAlloc and ref_mpNextAlloc are valid sgListIds for use by \n  // the host memory dma hardware, and ref_haystackInNandMemory is a valid sgListId for\n  // use by the nandsim dma hardware\n\n  fprintf(stderr, \"about to setup device %d %d\\n\", ref_needleAlloc, ref_mpNextAlloc);\n  strstrRequest->setup(ref_needleAlloc, ref_mpNextAlloc, needle_len);\n  fprintf(stderr, \"about to invoke search %d\\n\", ref_haystackInNandMemory);\n  strstrRequest->search(ref_haystackInNandMemory, haystack_len);\n  strstrIndication->wait();  \n\n  fprintf(stderr, \"algo1_nandsim: Done %d\\n\",  (strstrIndication->match_cnt==3));\n  sleep(2);\n  exit(!(strstrIndication->match_cnt==3));\n}\n"
  },
  {
    "path": "examples/algo2_nandsim/Makefile",
    "content": "\nCONNECTALDIR?=../..\nINTERFACES = NandCfgRequest RegexpRequest NandCfgIndication RegexpIndication\nBSVFILES = $(CONNECTALDIR)/lib/nandsim/bsv/NandSim.bsv $(CONNECTALDIR)/lib/regexp/bsv/Regexp.bsv $(CONNECTALDIR)/lib/nandsim/bsv/NandSimNames.bsv Top.bsv \nCPPFILES=test.cpp\nCPPFILES2=../nandsim/testnandsim.cpp\nCONNECTALFLAGS += -D HAYSTACKREADCLIENTS=1\nCONNECTALFLAGS += -D DEGPAR=4 -D MAX_NUM_STATES=32 -D MAX_NUM_CHARS=32 \nCONNECTALFLAGS += -I$(CONNECTALDIR)/lib/regexp/cpp\nCONNECTALFLAGS += -I$(CONNECTALDIR)/lib/nandsim/cpp\nCONNECTALFLAGS += -D ALGO_NANDSIM\n\ninclude $(CONNECTALDIR)/Makefile.connectal\n"
  },
  {
    "path": "examples/algo2_nandsim/Top.bsv",
    "content": "/* Copyright (c) 2014 Quanta Research Cambridge, Inc\n *\n * Permission is hereby granted, free of charge, to any person obtaining a\n * copy of this software and associated documentation files (the \"Software\"),\n * to deal in the Software without restriction, including without limitation\n * the rights to use, copy, modify, merge, publish, distribute, sublicense,\n * and/or sell copies of the Software, and to permit persons to whom the\n * Software is furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n * DEALINGS IN THE SOFTWARE.\n */\nimport SpecialFIFOs::*;\nimport Vector::*;\nimport StmtFSM::*;\nimport FIFO::*;\nimport BRAM::*;\nimport DefaultValue::*;\nimport Connectable::*;\nimport CtrlMux::*;\nimport Portal::*;\nimport ConnectalMemory::*;\nimport MemServer::*;\nimport MemServerInternal::*;\nimport ConnectalMMU::*;\nimport ConnectalConfig::*;\nimport NandCfgRequest::*;\nimport MMURequest::*;\nimport RegexpRequest::*;\nimport NandCfgIndication::*;\nimport MemServerRequest::*;\nimport MemServerIndication::*;\nimport MMUIndication::*;\nimport RegexpIndication::*;\nimport NandSim::*;\nimport NandSimNames::*;\nimport Regexp::*;\n\nmodule mkConnectalTop(ConnectalTop);\n   \n   // nandsim \n   NandCfgIndicationProxy nandSimIndicationProxy <- mkNandCfgIndicationProxy(IfcNames_NandCfgIndicationH2S);\n   NandSim nandSim <- mkNandSim(nandSimIndicationProxy.ifc);\n   NandCfgRequestWrapper nandSimRequestWrapper <- mkNandCfgRequestWrapper(IfcNames_NandCfgRequestS2H,nandSim.request);\n   \n   // regexp algo\n   RegexpIndicationProxy regexpIndicationProxy <- mkRegexpIndicationProxy(IfcNames_AlgoIndicationH2S);\n   Regexp#(64) regexp <- mkRegexp(regexpIndicationProxy.ifc);\n   RegexpRequestWrapper regexpRequestWrapper <- mkRegexpRequestWrapper(IfcNames_AlgoRequestS2H,regexp.request);\n   \n   // backing store mmu\n   MMUIndicationProxy mMUIndicationProxy <- mkMMUIndicationProxy(IfcNames_MMUIndicationH2S);\n   MMU#(PhysAddrWidth) mMU <- mkMMU(0, True, mMUIndicationProxy.ifc);\n   MMURequestWrapper mMURequestWrapper <- mkMMURequestWrapper(IfcNames_MMURequestS2H, mMU.request);\n\n   // algo mmu\n   MMUIndicationProxy algoMMUIndicationProxy <- mkMMUIndicationProxy(IfcNames_MMUIndicationH2S);\n   MMU#(PhysAddrWidth) algoMMU <- mkMMU(1, True, algoMMUIndicationProxy.ifc);\n   MMURequestWrapper algoMMURequestWrapper <- mkMMURequestWrapper(IfcNames_MMURequestS2H, algoMMU.request);\n   \n   // nandsim mmu\n   MMUIndicationProxy nandsimMMUIndicationProxy <- mkMMUIndicationProxy(IfcNames_NandMMUIndicationH2S);\n   MMU#(PhysAddrWidth) nandsimMMU <- mkMMU(0, False, nandsimMMUIndicationProxy.ifc);\n   MMURequestWrapper nandsimMMURequestWrapper <- mkMMURequestWrapper(IfcNames_NandMMURequestS2H, nandsimMMU.request);\n   \n   // host memory dma server\n   MemServerIndicationProxy hostMemServerIndicationProxy <- mkMemServerIndicationProxy(IfcNames_MemServerIndicationH2S);\n   let rcs = append(regexp.config_read_client,nandSim.readClient);\n   MemServer#(PhysAddrWidth,64,1) hostDma <- mkMemServer(rcs, nandSim.writeClient, cons(mMU,cons(algoMMU,nil)), hostMemServerIndicationProxy.ifc);\n   MemServerRequestWrapper memServerRequestWrapper <- mkMemServerRequestWrapper(IfcNames_MemServerRequestS2H, hostDma.request);\n   \n   // nandsim memory dma server\n   MemServerIndicationProxy nandsimMemServerIndicationProxy <- mkMemServerIndicationProxy(IfcNames_NandMemServerIndicationH2S);\n   MemServer#(PhysAddrWidth,64,1) nandsimDma <- mkMemServer(regexp.haystack_read_client, nil, cons(nandsimMMU,nil), nandsimMemServerIndicationProxy.ifc);\n   mkConnection(nandsimDma.masters[0], nandSim.memSlave);\n   \n   Vector#(13,StdPortal) portals;\n\n   portals[0] = nandSimRequestWrapper.portalIfc;\n   portals[1] = nandSimIndicationProxy.portalIfc; \n\n   portals[2] = regexpRequestWrapper.portalIfc;\n   portals[3] = regexpIndicationProxy.portalIfc; \n   \n   portals[4] = mMURequestWrapper.portalIfc;\n   portals[5] = mMUIndicationProxy.portalIfc;\n\n   portals[6] = nandsimMMURequestWrapper.portalIfc;\n   portals[7] = nandsimMMUIndicationProxy.portalIfc;\n   \n   portals[8] = algoMMURequestWrapper.portalIfc;\n   portals[9] = algoMMUIndicationProxy.portalIfc;\n   \n   portals[10] = hostMemServerIndicationProxy.portalIfc;\n   portals[11] = nandsimMemServerIndicationProxy.portalIfc;\n   portals[12] = memServerRequestWrapper.portalIfc;\n   \n   let ctrl_mux <- mkSlaveMux(portals);\n   \n   interface interrupt = getInterruptVector(portals);\n   interface slave = ctrl_mux;\n   interface masters = hostDma.masters;\nendmodule : mkConnectalTop\n"
  },
  {
    "path": "examples/algo2_nandsim/test.cpp",
    "content": "/* Copyright (c) 2014 Quanta Research Cambridge, Inc\n *\n * Permission is hereby granted, free of charge, to any person obtaining a\n * copy of this software and associated documentation files (the \"Software\"),\n * to deal in the Software without restriction, including without limitation\n * the rights to use, copy, modify, merge, publish, distribute, sublicense,\n * and/or sell copies of the Software, and to permit persons to whom the\n * Software is furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n * DEALINGS IN THE SOFTWARE.\n */\n#include <fstream>\n#include <iostream>\n#include <sys/types.h>\n#include <sys/socket.h>\n#include <sys/un.h>\n#include <sys/mman.h>\n#include <assert.h>\n#include \"dmaManager.h\"\n#include \"MMURequest.h\"\n#include \"MMUIndication.h\"\n#include \"NandCfgIndication.h\"\n#include \"NandCfgRequest.h\"\n#include \"RegexpIndication.h\"\n#include \"RegexpRequest.h\"\n\nstatic int trace_memory = 1;\nextern \"C\" {\n#include \"sys/ioctl.h\"\n#include \"drivers/portalmem/portalmem.h\"\n#include \"sock_utils.h\"\n#include \"userReference.h\"\n}\n\n#include \"regexp_utils.h\"\n#include \"nandsim.h\"\n\nclass MMUIndicationNAND : public MMUIndicationWrapper\n{\n  DmaManager *portalMemory;\n public:\n  MMUIndicationNAND(DmaManager *pm, unsigned int  id, int tile=DEFAULT_TILE) : MMUIndicationWrapper(id,tile), portalMemory(pm) {}\n  MMUIndicationNAND(DmaManager *pm, unsigned int  id, PortalTransportFunctions *item, void *param) : MMUIndicationWrapper(id, item, param), portalMemory(pm) {}\n  virtual void configResp(uint32_t pointer){\n    fprintf(stderr, \"MMUIndication::configResp: %x\\n\", pointer);\n    portalMemory->confResp(pointer);\n  }\n  virtual void error (uint32_t code, uint32_t pointer, uint64_t offset, uint64_t extra) {\n    fprintf(stderr, \"MMUIndication::error(code=0x%x, pointer=0x%x, offset=0x%\"PRIx64\" extra=-0x%\"PRIx64\"\\n\", code, pointer, offset, extra);\n    //if (--mmu_error_limit < 0)\n        exit(-1);\n  }\n  virtual void idResponse(uint32_t sglId){\n    portalMemory->sglIdResp(sglId);\n  }\n};\n\nsize_t numBytes = 1 << 10;\n\nint main(int argc, const char **argv)\n{\n  fprintf(stderr, \"Main::%s %s\\n\", __DATE__, __TIME__);\n\n  //MMURequestProxy *hostMMURequest = new MMURequestProxy(IfcNames_MMURequestS2H);\n  DmaManager *hostDma = platformInit();\n  MMURequestProxy *nandsimMMURequest = new MMURequestProxy(IfcNames_NandMMURequestS2H);\n  DmaManager *nandsimDma = new DmaManager(nandsimMMURequest);\n  MMUIndicationNAND nandsimMMUIndication(nandsimDma,IfcNames_NandMMUIndicationH2S);\n\n  RegexpRequestProxy *device = new RegexpRequestProxy(IfcNames_AlgoRequestS2H);\n  RegexpIndication *deviceIndication = new RegexpIndication(IfcNames_AlgoIndicationH2S);\n  \n  //MemServerIndication hostMemServerIndication(IfcNames_MemServerIndicationH2S);\n  //MemServerIndication nandsimMemServerIndication(IfcNames_NandMemServerIndicationH2S);\n\n  haystack_dma = hostDma;\n  //haystack_mmu = hostMMURequest;\n  regexp = device;\n\n  fprintf(stderr, \"Main::allocating memory...\\n\");\n\n  // this is hard-coded into the REParser.java\n  assert(32 == MAX_NUM_STATES);\n  assert(32 == MAX_NUM_CHARS);\n\n  ////////////////////////////////////////////////////////////////////\n  // \n\n  fprintf(stderr, \"Main::waiting to connect to nandsim_exe\\n\");\n  wait_for_connect_nandsim_exe();\n  fprintf(stderr, \"Main::connected to nandsim_exe\\n\");\n  // base of haystack in \"flash\" memory\n  // this is read from nandsim_exe, but could also come from kernel driver\n  int haystack_base = read_from_nandsim_exe();\n  int haystack_len  = read_from_nandsim_exe();\n  (void) haystack_base;  // unused\n\n  // request the next sglist identifier from the sglistMMU hardware module\n  // which is used by the mem server accessing flash memory.\n  int id = 0;\n  MMURequest_idRequest(nandsimDma->priv.sglDevice, 0);\n  sem_wait(&nandsimDma->priv.sglIdSem);\n  id = nandsimDma->priv.sglId;\n  // pairs of ('offset','size') pointing to space in nandsim memory\n  // this is unsafe.  To do it properly, we should get this list from\n  // nandsim_exe or from the kernel driver.  This code here might overrun\n  // the backing store allocated by nandsim_exe.\n  RegionRef region[] = {{0, 0x100000}, {0x100000, 0x100000}};\n  printf(\"[%s:%d]\\n\", __FUNCTION__, __LINE__);\n  int ref_haystackInNandMemory = send_reference_to_portal(nandsimDma->priv.sglDevice, sizeof(region)/sizeof(region[0]), region, id);\n  sem_wait(&(nandsimDma->priv.confSem));\n  fprintf(stderr, \"%08x\\n\", ref_haystackInNandMemory);\n\n  // \n  ////////////////////////////////////////////////////////////////////\n\n  if(1){\n    P charMapP;\n    P stateMapP;\n    P stateTransitionsP;\n    \n    readfile(\"../jregexp.charMap\", &charMapP);\n    readfile(\"../jregexp.stateMap\", &stateMapP);\n    readfile(\"../jregexp.stateTransitions\", &stateTransitionsP);\n\n    portalCacheFlush(charMapP.alloc, charMapP.mem, charMapP.length, 1);\n    portalCacheFlush(stateMapP.alloc, stateMapP.mem, stateMapP.length, 1);\n    portalCacheFlush(stateTransitionsP.alloc, stateTransitionsP.mem, stateTransitionsP.length, 1);\n\n    for(int i = 0; i < num_tests; i++){\n\n      device->setup(charMapP.ref, charMapP.length);\n      device->setup(stateMapP.ref, stateMapP.length);\n      device->setup(stateTransitionsP.ref, stateTransitionsP.length);\n\n      // for this test, we are just re-usng the same haystack which \n      // has been written to the nandsim backing store by nandsim_exe \n\n      if(i==0){\n\treadfile(\"test.bin\", &haystackP[0]);\n\tsw_match_cnt = num_tests*sw_ref(&haystackP[0], &charMapP, &stateMapP, &stateTransitionsP);\n      }\n\n      sem_wait(&test_sem);\n      int token = deviceIndication->token;\n\n      assert(token < max_num_tokens);\n      token_map[token] = i;\n      fprintf(stderr, \"Main::about to invoke search %08x %08x\\n\", ref_haystackInNandMemory, haystack_len);\n      // Regexp uses a data-bus width of 8 bytes.  length must be a multiple of this dimension\n      device->search(token, ref_haystackInNandMemory, haystack_len & ~((1<<3)-1));\n    }\n\n    sem_wait(&test_sem);\n    close(charMapP.alloc);\n    close(stateMapP.alloc);\n    close(stateTransitionsP.alloc);\n  }\n  fprintf(stderr, \"hw_match_cnt=%d, sw_match_cnt=%d\\n\", hw_match_cnt, sw_match_cnt);\n  return (hw_match_cnt == sw_match_cnt ? 0 : -1);\n}\n"
  },
  {
    "path": "examples/aurora/Aurora.bsv",
    "content": "\n// Copyright (c) 2014 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\nimport FIFO::*;\nimport Vector::*;\nimport GetPut::*;\nimport ClientServer::*;\nimport ConnectalXilinxCells::*;\nimport XilinxCells::*;\nimport BviAurora::*;\nimport Clocks::*;\nimport FrequencyCounter::*;\nimport Gtx::*;\n\n(* always_enabled, always_ready *)\ninterface AuroraPins;\n   method Action userClk(Bit#(1) p, Bit#(1) n);\n   method Action mgtRefClk(Bit#(1) p, Bit#(1) n);\n   method Action mgtRx(Bit#(1) p, Bit#(1) n);\n   method Bit#(1) mgtTx_p();\n   method Bit#(1) mgtTx_n();\n   interface DiffClock smaUserClk;\nendinterface\n\ninterface AuroraIndication;\n    method Action received(Bit#(64) v);\n    method Action debug(Bit#(1) channelUp, Bit#(1) laneUp, Bit#(1) hard_err, Bit#(1) soft_err, Bit#(1) qpllLock, Bit#(1) qpllRefClkLost);\n    method Action userClkElapsedCycles(Bit#(32) cycles);\n    method Action mgtRefClkElapsedCycles(Bit#(32) cycles);\n    method Action outClkElapsedCycles(Bit#(32) cycles);\n    method Action outRefClkElapsedCycles(Bit#(32) cycles);\n    method Action drpResponse(Bit#(16) v);\nendinterface\n\ninterface AuroraRequest;\n    method Action send(Bit#(64) v);\n    method Action debug();\n    method Action pma_init(Bit#(1) v);\n    method Action userClkElapsedCycles(Bit#(32) period);\n    method Action mgtRefClkElapsedCycles(Bit#(32) period);\n    method Action outClkElapsedCycles(Bit#(32) period);\n    method Action outRefClkElapsedCycles(Bit#(32) period);\n    method Action drpRequest(Bit#(9) addr, Bit#(16) data, Bit#(1) isWrite);\n    method Action qpllReset(Bit#(1) v);\n    method Action loopback(Bit#(3) v);\nendinterface\n\ninterface Aurora;\n   interface AuroraRequest request;\n   interface AuroraPins pins;\nendinterface\n\nmodule mkAuroraRequest#(AuroraIndication indication)(Aurora);\n   let defaultClock <- exposeCurrentClock;\n   let defaultReset <- exposeCurrentReset;\n\n   Wire#(Bit#(1)) userClkWireP <- mkDWire(0);\n   Wire#(Bit#(1)) userClkWireN <- mkDWire(0);\n   Clock userClkIn <- mkClockIBUFDS(userClkWireP, userClkWireN);\n   Clock userClk <- mkClockBUFG(clocked_by userClkIn);\n\n   DiffClock smaUserClockDS <- mkClockOBUFDS(clocked_by userClk);\n\n   let userReset <- mkAsyncReset(16, defaultReset, userClk);\n   let userClkFreqCounter <- mkFrequencyCounter(userClk, userReset);\n\n   Wire#(Bit#(1)) mgtRefClkWireP <- mkDWire(0);\n   Wire#(Bit#(1)) mgtRefClkWireN <- mkDWire(0);\n   Clock mgtRefClk <- mkClockIBUFDS_GTE2(True, mgtRefClkWireP, mgtRefClkWireN);\n\n   let mgtRefClkReset <- mkAsyncReset(16, defaultReset, mgtRefClk);\n   let mgtRefClkFreqCounter <- mkFrequencyCounter(mgtRefClk, mgtRefClkReset);\n\n   let b2c <- mkB2C();\n   Clock txClock <- mkClockBUFG(clocked_by b2c.c);\n\n   Clock syncClock = txClock; // should be doubled\n\n   let common <- mkGtxe2Common(defaultClock, mgtRefClk, defaultClock);\n\n   // let outClk <- mkClockBUFG(clocked_by common.qpll.outClk);\n   // let outClkReset <- mkAsyncReset(2, defaultReset, outClk);\n   // let outClkFreqCounter <- mkFrequencyCounter(outClk, outClkReset);\n\n   // let outRefClk <- mkClockBUFG(clocked_by common.qpll.outRefClk);\n   // let outRefClkReset <- mkAsyncReset(2, defaultReset, outRefClk);\n   // let outRefClkFreqCounter <- mkFrequencyCounter(outRefClk, outRefClkReset);\n\n   let initReset <- mkAsyncReset(128, defaultReset, userClk);\n   let aur <- mkBviAurora64(/* init_clk */ defaultClock,\n\t\t\t    mgtRefClk,\n\t\t\t    /* sync_clk */ syncClock,\n\t\t\t    /* user_clk */ txClock,\n\t\t\t    /* init_clk_reset */ defaultReset,\n\t\t\t    /* refclk1_in_reset */ defaultReset,\n\t\t\t    /* reset */ defaultReset,\n\t\t\t    /* sync_clk_reset */ defaultReset,\n\t\t\t    /* user_clk_reset */ defaultReset);\n      \n   Reg#(Bit#(1)) pmaInitVal <- mkReg(0);\n   Reg#(Bit#(3)) loopbackVal <- mkReg(0);\n   Reg#(Bit#(15)) ccCounter <- mkReg(0);\n\n   rule tx_out_clk_rule;\n      b2c.inputclock(aur.tx.out_clk());\n   endrule\n   // gt_pll_lock\n\n   rule settings;\n      aur.loopback(loopbackVal);\n      aur.power.down(0);\n      aur.pma.init(pmaInitVal);\n   endrule\n   rule qpll;\n      //aur.gt_qpllclk_quad2_in(common.qpll.outClk());\n      //aur.gt_qpllrefclk_quad2_in(common.qpll.outRefClk());\n   endrule      \n\n   rule receive if (unpack(aur.m_axi_rx.tvalid()));\n      let v = 0;\n      indication.received(aur.m_axi_rx.tdata());\n   endrule\n\n   Reg#(Bit#(1)) ccValue <- mkReg(0);\n   rule doCC;\n      aur.do_.cc(ccValue);\n   endrule\n\n   // The CC block code should be sent atleast once for every 5000 clock cycles.\n   rule countCC;\n      let counter = ccCounter + 1;\n      let doCC = 0;\n      if (aur.channel.up() == 0)\n\t counter = 0;\n      if (counter > 4992)\n\t doCC = 1;\n      if (counter > 5000)\n\t counter = 0;\n      ccCounter <= counter;\n      ccValue <= doCC;\n   endrule\n   rule userclkfreqcounter_rule;\n      let ec <- userClkFreqCounter.elapsedCycles();\n      indication.userClkElapsedCycles(ec);\n   endrule\n   rule mgtrefclkfreqcounter_rule;\n      let ec <- mgtRefClkFreqCounter.elapsedCycles();\n      indication.mgtRefClkElapsedCycles(ec);\n   endrule\n   rule outclkfreqcounter_rule;\n//      let ec <- outClkFreqCounter.elapsedCycles();\n//      indication.outClkElapsedCycles(ec);\n   endrule\n   rule outrefclkfreqcounter_rule;\n//      let ec <- outRefClkFreqCounter.elapsedCycles();\n//      indication.outRefClkElapsedCycles(ec);\n   endrule\n   rule drpResponseRule;\n      let v <- common.drp.response.get();\n      indication.drpResponse(v);\n   endrule\n\t \n   interface AuroraRequest request;\n       method Action send(Bit#(64) v) if (unpack(aur.s_axi_tx.tready()));\n\t  aur.s_axi_tx.tdata(v);\n\t  aur.s_axi_tx.tkeep(-1);\n\t  aur.s_axi_tx.tlast(1);\n\t  aur.s_axi_tx.tvalid(1);\n       endmethod\n      method Action debug();\n\t indication.debug(aur.channel.up(), aur.lane.up(), aur.hard.err(), aur.soft.err(), common.qpll.lock(), common.qpll.refClkLost());\n      endmethod\n      method Action pma_init(Bit#(1) v);\n\t pmaInitVal <= v;\n      endmethod\n      method Action loopback(Bit#(3) v);\n\t loopbackVal <= v;\n      endmethod\n      method Action userClkElapsedCycles(Bit#(32) period);\n\t userClkFreqCounter.start(period);\n      endmethod\n      method Action mgtRefClkElapsedCycles(Bit#(32) period);\n\t mgtRefClkFreqCounter.start(period);\n      endmethod\n      method Action outClkElapsedCycles(Bit#(32) period);\n//\t outClkFreqCounter.start(period);\n      endmethod\n      method Action outRefClkElapsedCycles(Bit#(32) period);\n//\t outRefClkFreqCounter.start(period);\n      endmethod\n      method Action drpRequest(Bit#(9) addr, Bit#(16) data, Bit#(1) isWrite);\n         common.drp.request.put(DrpRequest { addr: addr, data: data, isWrite: unpack(isWrite) });\n      endmethod\n      method Action qpllReset(Bit#(1) v);\n         common.qpll.reset(unpack(v));\n      endmethod\n   endinterface\n   interface AuroraPins pins;\n       method Action userClk(Bit#(1) p, Bit#(1) n);\n\t  userClkWireP <= p;\n\t  userClkWireN <= n;\n       endmethod\n       method Action mgtRefClk(Bit#(1) p, Bit#(1) n);\n\t  mgtRefClkWireP <= p;\n\t  mgtRefClkWireN <= n;\n       endmethod\n       method Action mgtRx(Bit#(1) p, Bit#(1) n);\n\t  aur.rxp(p);\n\t  aur.rxn(n);\n       endmethod\n       method mgtTx_p = aur.txp;\n       method mgtTx_n = aur.txn;\n\n       interface DiffClock smaUserClk = smaUserClockDS;\n   endinterface\n\nendmodule"
  },
  {
    "path": "examples/aurora/BviAurora.bsv",
    "content": "/* Copyright (c) 2014 Quanta Research Cambridge, Inc\n *\n * Permission is hereby granted, free of charge, to any person obtaining a\n * copy of this software and associated documentation files (the \"Software\"),\n * to deal in the Software without restriction, including without limitation\n * the rights to use, copy, modify, merge, publish, distribute, sublicense,\n * and/or sell copies of the Software, and to permit persons to whom the\n * Software is furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n * DEALINGS IN THE SOFTWARE.\n */\n\n/*\n   ../../generated/scripts/importbvi.py\n   -o\n   BviAurora.bsv\n   -I\n   BviAurora64\n   -P\n   Au64\n   -n\n   refclk1_in\n   -n\n   gt_qpllclk_quad2\n   -n\n   gt_qpllrefclk_quad2\n   -c\n   refclk1_in\n   -r\n   reset\n   -c\n   clk_in\n   -c\n   init_clk\n   -c\n   user_clk\n   -c\n   sync_clk\n   ../../generated/xilinx/zc706/aurora_64b66b_0/aurora_64b66b_0_stub.v\n*/\n\nimport Clocks::*;\nimport DefaultValue::*;\nimport XilinxCells::*;\nimport GetPut::*;\n\n(* always_ready, always_enabled *)\ninterface Au64Channel;\n    method Bit#(1)     up();\nendinterface\n(* always_ready, always_enabled *)\ninterface Au64Do;\n    method Action      cc(Bit#(1) v);\nendinterface\n(* always_ready, always_enabled *)\ninterface Au64Drp;\n    method Action      clk_in(Bit#(1) v);\nendinterface\n(* always_ready, always_enabled *)\ninterface Au64Gt;\n    method Bit#(1)     pll_lock();\n    method Action      rxcdrovrden_in(Bit#(1) v);\nendinterface\n(* always_ready, always_enabled *)\ninterface Au64Hard;\n    method Bit#(1)     err();\nendinterface\n(* always_ready, always_enabled *)\n(* always_ready, always_enabled *)\ninterface Au64Lane;\n    method Bit#(1)     up();\nendinterface\n(* always_ready, always_enabled *)\ninterface Au64Link;\n    method Bit#(1)     reset_out();\nendinterface\n(* always_ready, always_enabled *)\ninterface Au64M_axi_rx;\n    method Bit#(64)     tdata();\n    method Bit#(8)     tkeep();\n    method Bit#(1)     tlast();\n    method Bit#(1)     tvalid();\nendinterface\n(* always_ready, always_enabled *)\ninterface Au64Mmcm;\n    method Action      not_locked(Bit#(1) v);\nendinterface\n(* always_ready, always_enabled *)\ninterface Au64Pma;\n    method Action      init(Bit#(1) v);\nendinterface\n(* always_ready, always_enabled *)\ninterface Au64Power;\n    method Action      down(Bit#(1) v);\nendinterface\n(* always_ready, always_enabled *)\ninterface Au64Reset;\n    method Action      pb(Bit#(1) v);\nendinterface\n(* always_ready, always_enabled *)\ninterface Au64S_axi;\n    method Action      araddr(Bit#(32) v);\n    method Bit#(1)     arready();\n    method Action      arvalid(Bit#(1) v);\n    method Action      awaddr(Bit#(32) v);\n    method Bit#(1)     awready();\n    method Action      awvalid(Bit#(1) v);\n    method Action      bready(Bit#(1) v);\n    method Bit#(1)     bvalid();\n    method Bit#(32)     rdata();\n    method Action      rready(Bit#(1) v);\n    method Bit#(1)     rvalid();\n    method Action      wdata(Bit#(32) v);\n    method Bit#(1)     wready();\n    method Action      wvalid(Bit#(1) v);\nendinterface\n(* always_ready, always_enabled *)\ninterface Au64S_axi_tx;\n    method Action      tdata(Bit#(64) v);\n    method Action      tkeep(Bit#(8) v);\n    method Action      tlast(Bit#(1) v);\n    method Bit#(1)     tready();\n    method Action      tvalid(Bit#(1) v);\nendinterface\n(* always_ready, always_enabled *)\ninterface Au64Soft;\n    method Bit#(1)     err();\nendinterface\n(* always_ready, always_enabled *)\n(* always_ready, always_enabled *)\ninterface Au64Sys;\n    method Bit#(1)     reset_out();\nendinterface\n(* always_ready, always_enabled *)\ninterface Au64Tx;\n    method Bit#(1)     out_clk();\nendinterface\n(* always_ready, always_enabled *)\n(* always_ready, always_enabled *)\ninterface BviAurora64;\n    interface Au64Channel     channel;\n    interface Au64Do     do_;\n    interface Au64Drp     drp;\n    interface Au64Gt     gt;\n    method Action      gt_qpllclk_quad2_in(Bit#(1) v);\n    method Action      gt_qpllrefclk_quad2_in(Bit#(1) v);\n    interface Au64Hard     hard;\n    interface Au64Lane     lane;\n    interface Au64Link     link;\n    method Action      loopback(Bit#(3) v);\n    interface Au64M_axi_rx     m_axi_rx;\n    interface Au64Mmcm     mmcm;\n    interface Au64Pma     pma;\n    interface Au64Power     power;\n    interface Au64Reset     reset;\n    method Action      rxn(Bit#(1) v);\n    method Action      rxp(Bit#(1) v);\n    interface Au64S_axi     s_axi;\n    interface Au64S_axi_tx     s_axi_tx;\n    interface Au64Soft     soft;\n    interface Au64Sys     sys;\n    interface Au64Tx     tx;\n    method Bit#(1)     txn();\n    method Bit#(1)     txp();\nendinterface\nimport \"BVI\" aurora_64b66b_0 =\nmodule mkBviAurora64#(Clock init_clk, Clock refclk1_in, Clock sync_clk, Clock user_clk, Reset init_clk_reset, Reset refclk1_in_reset, Reset reset, Reset sync_clk_reset, Reset user_clk_reset)(BviAurora64);\n    default_clock clk();\n    default_reset rst();\n        input_clock init_clk(init_clk) = init_clk;\n        input_reset init_clk_reset() = init_clk_reset; /* from clock*/\n    input_clock refclk1_in(refclk1_in) = refclk1_in;\n    input_reset refclk1_in_reset() = refclk1_in_reset; /* from clock*/\n    input_reset reset(reset) = reset;\n        input_clock sync_clk(sync_clk) = sync_clk;\n        input_reset sync_clk_reset() = sync_clk_reset; /* from clock*/\n        input_clock user_clk(user_clk) = user_clk;\n        input_reset user_clk_reset() = user_clk_reset; /* from clock*/\n    interface Au64Channel     channel;\n        method channel_up up();\n    endinterface\n   interface Au64Do     do_;\n        method cc(do_cc) enable((*inhigh*) EN_do_cc);\n    endinterface\n    interface Au64Drp     drp;\n        method clk_in(drp_clk_in) enable((*inhigh*) EN_drp_clk_in);\n    endinterface\n    interface Au64Gt     gt;\n        method gt_pll_lock pll_lock();\n        method rxcdrovrden_in(gt_rxcdrovrden_in) enable((*inhigh*) EN_gt_rxcdrovrden_in);\n    endinterface\n    method gt_qpllclk_quad2_in(gt_qpllclk_quad2_in) enable((*inhigh*) EN_gt_qpllclk_quad2_in);\n    method gt_qpllrefclk_quad2_in(gt_qpllrefclk_quad2_in) enable((*inhigh*) EN_gt_qpllrefclk_quad2_in);\n    interface Au64Hard     hard;\n        method hard_err err();\n    endinterface\n    interface Au64Lane     lane;\n        method lane_up up();\n    endinterface\n    interface Au64Link     link;\n        method link_reset_out reset_out();\n    endinterface\n    method loopback(loopback) enable((*inhigh*) EN_loopback);\n    interface Au64M_axi_rx     m_axi_rx;\n        method m_axi_rx_tdata tdata();\n        method m_axi_rx_tkeep tkeep();\n        method m_axi_rx_tlast tlast();\n        method m_axi_rx_tvalid tvalid();\n    endinterface\n    interface Au64Mmcm     mmcm;\n        method not_locked(mmcm_not_locked) enable((*inhigh*) EN_mmcm_not_locked);\n    endinterface\n    interface Au64Pma     pma;\n        method init(pma_init) enable((*inhigh*) EN_pma_init);\n    endinterface\n    interface Au64Power     power;\n        method down(power_down) enable((*inhigh*) EN_power_down);\n    endinterface\n    interface Au64Reset     reset;\n        method pb(reset_pb) enable((*inhigh*) EN_reset_pb);\n    endinterface\n    method rxn(rxn) enable((*inhigh*) EN_rxn);\n    method rxp(rxp) enable((*inhigh*) EN_rxp);\n    interface Au64S_axi     s_axi;\n        method araddr(s_axi_araddr) enable((*inhigh*) EN_s_axi_araddr);\n        method s_axi_arready arready();\n        method arvalid(s_axi_arvalid) enable((*inhigh*) EN_s_axi_arvalid);\n        method awaddr(s_axi_awaddr) enable((*inhigh*) EN_s_axi_awaddr);\n        method s_axi_awready awready();\n        method awvalid(s_axi_awvalid) enable((*inhigh*) EN_s_axi_awvalid);\n        method bready(s_axi_bready) enable((*inhigh*) EN_s_axi_bready);\n        method s_axi_bvalid bvalid();\n        method s_axi_rdata rdata();\n        method rready(s_axi_rready) enable((*inhigh*) EN_s_axi_rready);\n        method s_axi_rvalid rvalid();\n        method wdata(s_axi_wdata) enable((*inhigh*) EN_s_axi_wdata);\n        method s_axi_wready wready();\n        method wvalid(s_axi_wvalid) enable((*inhigh*) EN_s_axi_wvalid);\n    endinterface\n    interface Au64S_axi_tx     s_axi_tx;\n        method tdata(s_axi_tx_tdata) enable((*inhigh*) EN_s_axi_tx_tdata);\n        method tkeep(s_axi_tx_tkeep) enable((*inhigh*) EN_s_axi_tx_tkeep);\n        method tlast(s_axi_tx_tlast) enable((*inhigh*) EN_s_axi_tx_tlast);\n        method s_axi_tx_tready tready();\n        method tvalid(s_axi_tx_tvalid) enable((*inhigh*) EN_s_axi_tx_tvalid);\n    endinterface\n    interface Au64Soft     soft;\n        method soft_err err();\n    endinterface\n    interface Au64Sys     sys;\n        method sys_reset_out reset_out();\n    endinterface\n    interface Au64Tx     tx;\n        method tx_out_clk out_clk() clocked_by (user_clk);\n    endinterface\n    method txn txn();\n    method txp txp();\n    schedule (channel.up, do_.cc, drp.clk_in, gt.pll_lock, gt.rxcdrovrden_in, gt_qpllclk_quad2_in, gt_qpllrefclk_quad2_in, hard.err, lane.up, link.reset_out, loopback, m_axi_rx.tdata, m_axi_rx.tkeep, m_axi_rx.tlast, m_axi_rx.tvalid, mmcm.not_locked, pma.init, power.down, reset.pb, rxn, rxp, s_axi.araddr, s_axi.arready, s_axi.arvalid, s_axi.awaddr, s_axi.awready, s_axi.awvalid, s_axi.bready, s_axi.bvalid, s_axi.rdata, s_axi.rready, s_axi.rvalid, s_axi.wdata, s_axi.wready, s_axi.wvalid, s_axi_tx.tdata, s_axi_tx.tkeep, s_axi_tx.tlast, s_axi_tx.tready, s_axi_tx.tvalid, soft.err, sys.reset_out, tx.out_clk, txn, txp) CF (channel.up, do_.cc, drp.clk_in, gt.pll_lock, gt.rxcdrovrden_in, gt_qpllclk_quad2_in, gt_qpllrefclk_quad2_in, hard.err, lane.up, link.reset_out, loopback, m_axi_rx.tdata, m_axi_rx.tkeep, m_axi_rx.tlast, m_axi_rx.tvalid, mmcm.not_locked, pma.init, power.down, reset.pb, rxn, rxp, s_axi.araddr, s_axi.arready, s_axi.arvalid, s_axi.awaddr, s_axi.awready, s_axi.awvalid, s_axi.bready, s_axi.bvalid, s_axi.rdata, s_axi.rready, s_axi.rvalid, s_axi.wdata, s_axi.wready, s_axi.wvalid, s_axi_tx.tdata, s_axi_tx.tkeep, s_axi_tx.tlast, s_axi_tx.tready, s_axi_tx.tvalid, soft.err, sys.reset_out, tx.out_clk, txn, txp);\nendmodule\n"
  },
  {
    "path": "examples/aurora/Gtx.bsv",
    "content": "\n// Copyright (c) 2014 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\nimport Vector::*;\nimport GetPut::*;\nimport ClientServer::*;\nimport Clocks::*;\n\ninterface Drp#(numeric type asz, numeric type dsz);\n   method Action addr(Bit#(asz) a);\n   method Action en(Bit#(1) en);\n   method Action we(Bit#(1) we);\n   method Bit#(dsz) dout();\n   method Action din(Bit#(dsz) d);\n   method Bit#(1) rdy();\nendinterface\n\ninterface Gtxe2Qpll;\n   method Action reset(Bool v);\n   method Bit#(1) lock();\n   interface Clock outClk;\n   interface Clock outRefClk;\n   method Bit#(1) refClkLost();\nendinterface\n\ninterface VGtxe2Common;\n    (* always_ready, always_enabled *)\n   interface Gtxe2Qpll qpll;\n    (* always_ready, always_enabled *)\n   interface Drp#(9,16) drp;\nendinterface\n\nimport \"BVI\" GTXE2_COMMON =\nmodule vMkGtxe2Common#(Clock qpllLockDetClk, Clock gtrefclk0, Clock drpClk)(VGtxe2Common);\n\n   default_clock clk();\n   default_reset reset();\n   input_clock gtrefclk0(GTREFCLK0) = gtrefclk0;\n   input_clock qpllLockDetClk(QPLLLOCKDETCLK) = qpllLockDetClk;\n   input_clock drpClk(DRPCLK) = drpClk;\n\n   parameter BIAS_CFG                               = (64'h0000040000001000);\n   parameter COMMON_CFG                             = (32'h00000000);\n   parameter QPLL_CFG                               = (27'h06801C1);\n   parameter QPLL_CLKOUT_CFG                        = (4'b0000);\n   parameter QPLL_COARSE_FREQ_OVRD                  = (6'b010000);\n   parameter QPLL_COARSE_FREQ_OVRD_EN               = (1'b0);\n   parameter QPLL_CP                                = (10'b0000011111);\n   parameter QPLL_CP_MONITOR_EN                     = (1'b0);\n   parameter QPLL_DMONITOR_SEL                      = (1'b0);\n   parameter QPLL_FBDIV                             = (10'b0000100000);\n   parameter QPLL_FBDIV_MONITOR_EN                  = (1'b0);\n   parameter QPLL_FBDIV_RATIO                       = (1'b1);\n   parameter QPLL_INIT_CFG                          = (24'h000006);\n   parameter QPLL_LOCK_CFG                          = (16'h21E8);\n   parameter QPLL_LPF                               = (4'b1111);\n   parameter QPLL_REFCLK_DIV                        = (1);\n\n   port GTGREFCLK = 0;\n   port GTNORTHREFCLK0 = 0;\n   port GTNORTHREFCLK1 = 0;\n   //port GTREFCLK0 = gtrefclk0;\n   port GTREFCLK1 = 0;\n   port GTSOUTHREFCLK0 = 0;\n   port GTSOUTHREFCLK1 = 0;\n   port QPLLLOCKEN = 1;\n   port QPLLOUTRESET = 0;\n   port QPLLPD = 0;\n   port QPLLREFCLKSEL = 3'b1;\n   port QPLLRSVD1 = 0;\n   port QPLLRSVD2 = 5'b11111;\n   port RCALENB = 1;\n   port BGBYPASSB = 1;\n   port BGMONITORENB = 1;\n   port BGPDB = 1;\n   port BGRCALOVRD = 5'b11111;\n   port PMARSVD = 0;\n   interface Drp drp;\n      method din(DRPDI) enable((*inhigh*)EN_DI) clocked_by(drpClk);\n      method addr(DRPADDR) enable((*inhigh*)EN_ADDR) clocked_by(drpClk);\n      method en(DRPEN) enable((*inhigh*)EN_EN) clocked_by(drpClk);\n      method we(DRPWE) enable((*inhigh*)EN_WE) clocked_by(drpClk);\n      method DRPDO dout() clocked_by(drpClk);\n      method DRPRDY rdy() clocked_by(drpClk);\n   endinterface\n   interface Gtxe2Qpll qpll;\n      method reset(QPLLRESET) enable ((*inhigh*)EN_RESET);\n      method QPLLLOCK lock();\n      output_clock outClk(QPLLOUTCLK);\n      output_clock outRefClk(QPLLOUTREFCLK);\n      method QPLLREFCLKLOST refClkLost();\n   endinterface\n   schedule (qpll_reset, qpll_lock, qpll_refClkLost, drp_addr, drp_din, drp_en, drp_we, drp_dout, drp_rdy, drp_we)\n         CF (qpll_reset, qpll_lock, qpll_refClkLost, drp_addr, drp_din, drp_en, drp_we, drp_dout, drp_rdy, drp_we);\nendmodule: vMkGtxe2Common\n\ntypedef struct {\n   Bool      isWrite;\n   Bit#(asz) addr;\n   Bit#(dsz) data;\n   } DrpRequest#(numeric type asz, numeric type dsz) deriving (Bits,Eq);\n\ninterface Gtxe2Common;\n   interface Gtxe2Qpll qpll;\n   interface Server#(DrpRequest#(9,16),Bit#(16)) drp;\nendinterface\n\n(* synthesize *)\nmodule mkGtxe2Common#(Clock qpllLockDetClk, Clock gtrefclk0, Clock drpClk)(Gtxe2Common);\n   let m <- vMkGtxe2Common(qpllLockDetClk, gtrefclk0, drpClk);\n   let defaultReset <- exposeCurrentReset();\n   let drpReset <- mkAsyncReset(2, defaultReset, drpClk);\n   Wire#(Bit#(1)) drpen <- mkDWire(0, clocked_by drpClk, reset_by drpReset);\n   rule drpenrule;\n      m.drp.en(drpen);\n   endrule\n\n   Reg#(Bool) resetWire <- mkReg(False);\n   rule qpll_reset_rule;\n      m.qpll.reset(resetWire);\n   endrule\n\n   interface Gtxe2Qpll qpll;\n      method Action reset(Bool v);\n\t resetWire <= v;\n      endmethod\n      method lock = m.qpll.lock;\n      interface outClk = m.qpll.outClk;\n      interface outRefClk = m.qpll.outRefClk;\n      method refClkLost = m.qpll.refClkLost;\n   endinterface\n   interface Server drp;\n      interface Put request;\n\t method Action put(DrpRequest#(9,16) req);\n\t    m.drp.addr(req.addr);\n\t    m.drp.din(req.data);\n\t    m.drp.we(pack(req.isWrite));\n\t    drpen <= 1;\n\t endmethod\n      endinterface\n      interface Get response;\n\t method ActionValue#(Bit#(16)) get() if (unpack(m.drp.rdy()));\n\t    return m.drp.dout();\n\t endmethod\n      endinterface\n   endinterface\nendmodule\n"
  },
  {
    "path": "examples/aurora/Makefile",
    "content": "CONNECTALDIR?=../..\nINTERFACES = AuroraRequest AuroraIndication\n\nBSVFILES = Aurora.bsv Top.bsv\nCPPFILES=testaurora.cpp\nPIN_TYPE = AuroraPins\nPIN_TYPE_INCLUDE = BviAurora\nCONNECTALFLAGS += -C $(BOARD)/sources/aurora-$(BOARD).xdc -C aurora-clocks.xdc --tcl clock.tcl\n\nAURORA_V = $(CONNECTALDIR)/generated/xilinx/$(BOARD)/aurora_64b66b_0/aurora_64b66b_0_stub.v\n\ngentarget:: $(BOARD)/sources/aurora-$(BOARD).xdc\n\nprebuild:: $(AURORA_V) BviAurora.bsv\n\n$(AURORA_V): synth-ip.tcl\n\t(cd $(BOARD); vivado -mode batch -source ../synth-ip.tcl)\n\nBviAurora.bsv:\n\t$(CONNECTALDIR)/generated/scripts/importbvi.py -o BviAurora.bsv -I BviAurora64  -P Au64 -n refclk1_in -n gt_qpllclk_quad2 -n gt_qpllrefclk_quad2 -c refclk1_in -r reset -c clk_in -c init_clk -c user_clk -c sync_clk $(AURORA_V)\n\n$(BOARD)/sources/aurora-$(BOARD).xdc: aurora.json $(CONNECTALDIR)/boardinfo/$(BOARD).json\n\tmkdir -p $(BOARD)/sources\n\t$(CONNECTALDIR)/scripts/generate-constraints.py --boardfile $(CONNECTALDIR)/boardinfo/$(BOARD).json --pinoutfile aurora.json > $(BOARD)/sources/aurora-$(BOARD).xdc\n\ninclude $(CONNECTALDIR)/Makefile.connectal\n"
  },
  {
    "path": "examples/aurora/Top.bsv",
    "content": "/* Copyright (c) 2014 Quanta Research Cambridge, Inc\n *\n * Permission is hereby granted, free of charge, to any person obtaining a\n * copy of this software and associated documentation files (the \"Software\"),\n * to deal in the Software without restriction, including without limitation\n * the rights to use, copy, modify, merge, publish, distribute, sublicense,\n * and/or sell copies of the Software, and to permit persons to whom the\n * Software is furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n * DEALINGS IN THE SOFTWARE.\n */\nexport Aurora::*;\nexport mkConnectalTop;\nimport Vector::*;\nimport FIFO::*;\nimport Connectable::*;\nimport CtrlMux::*;\nimport Portal::*;\nimport ConnectalConfig::*;\nimport AuroraIndication::*;\nimport AuroraRequest::*;\nimport Aurora::*;\ntypedef enum {IfcNames_AuroraIndication, IfcNames_AuroraRequest} IfcNames deriving (Eq,Bits);\n\nmodule mkConnectalTop(ConnectalTop);\n\n   // instantiate user portals\n   AuroraIndicationProxy auroraIndicationProxy <- mkAuroraIndicationProxy(IfcNames_AuroraIndication);\n   let auroraRequest <- mkAuroraRequest(auroraIndicationProxy.ifc);\n   AuroraRequestWrapper auroraRequestWrapper <- mkAuroraRequestWrapper(IfcNames_AuroraRequest,auroraRequest.request);\n   \n   Vector#(2,StdPortal) portals;\n   portals[0] = auroraRequestWrapper.portalIfc;\n   portals[1] = auroraIndicationProxy.portalIfc;\n   let ctrl_mux <- mkSlaveMux(portals);\n   \n   interface interrupt = getInterruptVector(portals);\n   interface slave = ctrl_mux;\n   interface masters = nil;\n   interface pins = auroraRequest.pins;\nendmodule : mkConnectalTop\n"
  },
  {
    "path": "examples/aurora/aurora-clocks.xdc",
    "content": "create_clock -name user_clk -period \"6.4\" [get_ports \"userClk_p\"]\ncreate_clock -name mgtref_clk -period \"6.4\" [get_ports \"mgtRefClk_p\"]\n"
  },
  {
    "path": "examples/aurora/aurora.json",
    "content": "{\n    \"userClk_p\": {\n\t\"IOSTANDARD\": \"LVDS_25\",\n\t\"DIFF_TERM\": \"TRUE\",\n        \"fmc\": \"userClk_p\"\n    },\n    \"userClk_n\": {\n\t\"IOSTANDARD\": \"LVDS_25\",\n\t\"DIFF_TERM\": \"TRUE\",\n        \"fmc\": \"userClk_n\"\n    },\n    \"smaUserClk_p\": {\n\t\"IOSTANDARD\": \"LVDS_25\",\n\t\"DIFF_TERM\": \"TRUE\",\n        \"fmc\": \"smaUserClk_p\"\n    },\n    \"smaUserClk_n\": {\n\t\"IOSTANDARD\": \"LVDS_25\",\n\t\"DIFF_TERM\": \"TRUE\",\n        \"fmc\": \"smaUserClk_n\"\n    },\n    \"mgtRefClk_p\": {\n\t\"DIFF_TERM\": \"TRUE\",\n        \"fmc\": \"mgtRefClk_p\"\n    },\n    \"mgtRefClk_n\": {\n\t\"DIFF_TERM\": \"TRUE\",\n        \"fmc\": \"mgtRefClk_n\"\n    },\n    \"mgtRx_p\": {\n        \"fmc\": \"mgtRx_p\"\n    },\n    \"mgtRx_n\": {\n        \"fmc\": \"mgtRx_n\"\n    },\n    \"mgtTx_p\": {\n        \"fmc\": \"mgtTx_p\"\n    },\n    \"mgtTx_n\": {\n        \"fmc\": \"mgtTx_n\"\n    }\n}"
  },
  {
    "path": "examples/aurora/clock.tcl",
    "content": "## disconnect unused CLK and RST ports inserted by bsc\nforeach {pat} {CLK_GATE*} {\n    puts $pat\n    puts ports\n    puts [get_ports $pat]\n    puts nets\n    puts [get_nets $pat]\n    foreach {net} [get_nets $pat] {\n\tdisconnect_net -net $net -objects [get_pins -of_objects $net]\n    }\n}\n"
  },
  {
    "path": "examples/aurora/synth-ip.tcl",
    "content": "source board.tcl\nsource $connectaldir/scripts/connectal-synth-ip.tcl\n\nconnectal_synth_ip aurora_64b66b 9.2 aurora_64b66b_0 [list CONFIG.interface_mode {Framing} CONFIG.C_GT_LOC_5 {1} CONFIG.C_GT_LOC_1 {X}]\n"
  },
  {
    "path": "examples/aurora/testaurora.cpp",
    "content": "/* Copyright (c) 2014 Quanta Research Cambridge, Inc\n *\n * Permission is hereby granted, free of charge, to any person obtaining a\n * copy of this software and associated documentation files (the \"Software\"),\n * to deal in the Software without restriction, including without limitation\n * the rights to use, copy, modify, merge, publish, distribute, sublicense,\n * and/or sell copies of the Software, and to permit persons to whom the\n * Software is furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n * DEALINGS IN THE SOFTWARE.\n */\n\n#include <stdio.h>\n#include <stdlib.h>\n#include <unistd.h>\n#include <assert.h>\n\n#include \"AuroraIndication.h\"\n#include \"AuroraRequest.h\"\n#include \"GeneratedTypes.h\"\n\n\nclass AuroraIndication : public AuroraIndicationWrapper\n{  \npublic:\n  uint32_t cnt;\n  void incr_cnt(){\n    if (++cnt == 7)\n      exit(0);\n  }\n  virtual void received(uint64_t v) {\n    fprintf(stderr, \"Received v=%lld\", v);\n  }\n  virtual void debug(uint32_t channelUp, uint32_t laneUp, uint32_t hardErr, uint32_t softErr, uint32_t qpllLock, uint32_t qpllRefClkLost) {\n    fprintf(stderr, \"debug: channelUp=%d laneUp=%d hardErr=%d, softErr=%d qpllLock=%d qpllRefClkLost=%d\\n\", channelUp, laneUp, hardErr, softErr, qpllLock, qpllRefClkLost);\n  }\n  virtual void userClkElapsedCycles(uint32_t ec) {\n    fprintf(stderr, \"userClk freq=%f MHz\\n\", (float)ec / 5.0);\n  }\n  virtual void mgtRefClkElapsedCycles(uint32_t ec) {\n    fprintf(stderr, \"mgtRefClk freq=%f MHz\\n\", (float)ec / 5.0);\n  }\n  virtual void outClkElapsedCycles(uint32_t ec) {\n    fprintf(stderr, \"outClk freq=%f MHz\\n\", (float)ec / 5.0);\n  }\n  virtual void outRefClkElapsedCycles(uint32_t ec) {\n    fprintf(stderr, \"outRefClk freq=%f MHz\\n\", (float)ec / 5.0);\n  }\n  virtual void drpResponse(uint32_t v) {\n    fprintf(stderr, \"drp response %#x\\n\", v);\n  }\n  AuroraIndication(unsigned int id) : AuroraIndicationWrapper(id), cnt(0){}\n};\n\n\n\nint main(int argc, const char **argv)\n{\n  PortalPoller *poller = new PortalPoller();\n  AuroraIndication *indication = new AuroraIndication(IfcNames_AuroraIndication);\n  AuroraRequestProxy *device = new AuroraRequestProxy(IfcNames_AuroraRequest, poller);\n\n  long freq = 0;\n  setClockFrequency(0, 200000000, &freq);\n\n  fprintf(stderr, \"Main::calling say1(%d)\\n\", 0);\n  device->send(0);\n\n  fprintf(stderr, \"Main::about to go to sleep\\n\");\n  int count = 0;\n  while(true){\n    device->debug();\n    device->userClkElapsedCycles(1000);\n    device->mgtRefClkElapsedCycles(1000);\n    device->qpllReset(count < 2);\n    device->pma_init(count < 2);\n    device->loopback(1);\n    if (count < 0x14) {\n      fprintf(stderr, \"Reading drp reg %x\\n\", count+0x30);\n      device->drpRequest(count+0x30, 0, 0);\n    }\n    count++;\n    sleep(1);\n  }\n}\n"
  },
  {
    "path": "examples/bscan/BscanIF.bsv",
    "content": "\n// Copyright (c) 2013 Nokia, Inc.\n// Copyright (c) 2013 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\nimport BRAM         :: *;\nimport Bscan        :: *;\nimport GetPut       :: *;\nimport Connectable  :: *;\nimport DefaultValue :: *;\nimport Clocks       :: *;\nimport HostInterface:: *;\n\ninterface BscanIndication;\n    method Action bscanGet(Bit#(64) v);\nendinterface\n\ninterface BscanRequest;\n   method Action bscanGet(Bit#(8) addr);\n   method Action bscanPut(Bit#(8) addr, Bit#(64) v);\nendinterface\n\ninterface BscanIF;\n   interface BscanRequest request;\nendinterface\n\nmodule mkBscanIF#(HostInterface host, BscanIndication indication)(BscanIF);\n   Clock defaultClock <- exposeCurrentClock();\n   Reset defaultReset <- exposeCurrentReset();\n\n   Reg#(Bit#(8)) addrReg <- mkReg(0);\n\n   BscanBram#(Bit#(8),Bit#(64)) bscanBram <- mkBscanBram(123, addrReg, host.bscan);\n   let bram <- mkBRAM2Server(defaultValue);\n   mkConnection(bscanBram.bramClient, bram.portB);\n   rule tdorule;\n      host.bscan.tdo(bscanBram.data_out());\n   endrule\n\n   rule bscanGetRule2;\n      let v <- bram.portA.response.get();\n      indication.bscanGet(v);\n   endrule\n   \n   interface BscanRequest request;\n   method Action bscanGet(Bit#(8) addr);\n      bram.portA.request.put(BRAMRequest {write:False, responseOnWrite:False, address:addr, datain: ?});\n   endmethod\n   \n   method Action bscanPut(Bit#(8) addr, Bit#(64) v);\n      bram.portA.request.put(BRAMRequest {write:True, responseOnWrite:False, address:addr, datain: truncate(v)});\n   endmethod\n   endinterface\nendmodule\n"
  },
  {
    "path": "examples/bscan/Makefile",
    "content": "CONNECTALDIR?=../..\nS2H_INTERFACES = BscanRequest:BscanIF.request:host\nH2S_INTERFACES = BscanIF:BscanIndication:host\n\nBSVFILES = BscanIF.bsv\nCPPFILES=testbscan.cpp\nCONNECTALFLAGS += -D IMPORT_HOSTIF\n\ninclude $(CONNECTALDIR)/Makefile.connectal\n\n"
  },
  {
    "path": "examples/bscan/testbscan.cpp",
    "content": "/* Copyright (c) 2014 Quanta Research Cambridge, Inc\n *\n * Permission is hereby granted, free of charge, to any person obtaining a\n * copy of this software and associated documentation files (the \"Software\"),\n * to deal in the Software without restriction, including without limitation\n * the rights to use, copy, modify, merge, publish, distribute, sublicense,\n * and/or sell copies of the Software, and to permit persons to whom the\n * Software is furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n * DEALINGS IN THE SOFTWARE.\n */\n\n#include <stdio.h>\n//#include <stdlib.h>\n//#include <semaphore.h>\n#include \"BscanIndication.h\"\n#include \"BscanRequest.h\"\n#include \"GeneratedTypes.h\"\n\nstatic BscanRequestProxy *bscanRequestProxy = 0;\nstatic sem_t sem_bscan;\n\nclass BscanIndication : public BscanIndicationWrapper\n{\npublic:\n    virtual void bscanGet(uint64_t v) {\n        printf(\"bscanGet: %llx\\n\", (long long)v);\n        sem_post(&sem_bscan);\n    }\n    BscanIndication(unsigned int id) : BscanIndicationWrapper(id) { }\n};\n\nint main(int argc, const char **argv)\n{\n    BscanIndication *bscanIndication = new BscanIndication(IfcNames_BscanIndicationH2S);\n    bscanRequestProxy = new BscanRequestProxy(IfcNames_BscanRequestS2H);\n\n    if (argc == 1) {\n        int v = 42;\n        printf(\"Bscan put %x\\n\", v);\n        for (int i = 0; i < 255; i++)\n{\n        printf(\"Bscan put %x\\n\", i);\n          bscanRequestProxy->bscanPut(i, i*v);\n}\n        for (int i = 0; i < 16; i++)\n           bscanRequestProxy->bscanGet(i);\n    }\n    else if (argc == 2) {\n        bscanRequestProxy->bscanGet(atoll(argv[1]));\n        sem_wait(&sem_bscan);\n    }\n    else if (argc == 3)\n        bscanRequestProxy->bscanPut(atoll(argv[1]), atoll(argv[2]));\nprintf(\"[%s:%d] now sleep for 20 sec\\n\", __FUNCTION__, __LINE__);\n    sleep(20);\n    return 0;\n}\n"
  },
  {
    "path": "examples/caffe/Conv.bsv",
    "content": "// Copyright (c) 2015 The Connectal Project\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\nimport FloatingPoint::*;\nimport GetPut::*;\nimport FIFO::*;\nimport FIFOF::*;\nimport Vector::*;\nimport StmtFSM::*;\nimport ConnectalMemTypes::*;\nimport MemReadEngine::*;\nimport MemWriteEngine::*;\nimport ConnectalConfig::*;\nimport FloatOps::*;\nimport Gearbox::*;\nimport GearboxGetPut::*;\nimport DefaultValue::*;\nimport Pipe::*;\nimport ClientServer::*;\n\ntypedef struct {\n    Bit#(32) bottom_hw;\n    Bit#(32) kernel_hw;\n    Bit#(32) in_group_size;\n    Bit#(32) baseSize;\n    Bit#(32) conv_in_width;\n    Bit#(32) kernel_w;\n    Bit#(32) objectId;\n} ConnectalParamType  deriving (Eq,Bits);\n\ninterface ConvIndication;\n    method Action outputp(Bit#(32) addr, Float v);\nendinterface\n\ninterface ConvRequest;\n    method Action init(ConnectalParamType param);\n    method Action forward_kernel(Bit#(32) ap_limit, Bit#(32) aq_limit, Bit#(1) askip, Float atemp, Bit#(32) abpx, Bit#(32) awpx, Bit#(32) aoutputp);\nendinterface\n\ninterface Conv;\n    interface ConvRequest request;\n    interface Vector#(1,MemReadClient#(DataBusWidth)) readDma;\n    interface Vector#(1,MemWriteClient#(DataBusWidth)) writeDma;\nendinterface\n\ntypedef struct {\n    Float a;\n    Float b;\n    Bool  last;\n} DotType deriving (Bits, Eq);\n\ninterface DotProd;\n    interface PipeIn#(DotType) sendPair;\n    interface PipeOut#(Float)   done;\n    method Action init(Float atemp);\n    method Action incrementWait();\nendinterface\n\n(* synthesize *)\nmodule mkDotProd(DotProd);\n    FIFOF#(DotType) dotFifo <- mkFIFOF;\n    FIFOF#(Bool) lastFifo <- mkFIFOF1;\n    FIFOF#(Float) innerDone <- mkFIFOF;\n    FloatAlu adder <- mkFloatAdder(defaultValue);\n    FloatAlu mul <- mkFloatMultiplier(defaultValue);\n    Reg#(Float)    temp <- mkReg(0);\n    Reg#(Bool)     running <- mkReg(False);\n    Reg#(Bit#(32))  waitCount <- mkReg(0);\n\n    rule dotrule;\n        let v <- toGet(dotFifo).get;\n        mul.request.put(tuple2(v.a, v.b));\n        toPut(lastFifo).put(v.last);\n    endrule\n\n    rule addrule;\n        match {.resp,.*} <- mul.response.get;\n        adder.request.put(tuple2(resp,temp));\n    endrule\n\n    rule storerule if (running);\n        let v <- toGet(lastFifo).get;\n        match {.resp,.*} <- adder.response.get;\n        temp <= resp;\n        if (v) begin\n            waitCount <= waitCount - 1;\n            if (waitCount == 1) begin\n                innerDone.enq(resp);\n                running <= False;\n            end\n        end\n    endrule\n    interface sendPair = toPipeIn(dotFifo);\n    interface done = toPipeOut(innerDone);\n    method Action init(Float atemp) if (!running);\n        temp <= atemp;\n        running <= True;\n        waitCount <= 0;\n    endmethod\n    method Action incrementWait();\n        waitCount <= waitCount + 1;\n    endmethod\nendmodule\n\nmodule mkConv#(ConvIndication indication)(Conv);\n    Clock defaultClock <- exposeCurrentClock();\n    Reset defaultReset <- exposeCurrentReset();\n    Gearbox#(2, 1, DotType) floatGear <- mkNto1Gearbox(defaultClock, defaultReset, defaultClock, defaultReset);\n    MemReadEngine#(DataBusWidth,DataBusWidth,2,2) rEngine <- mkMemReadEngine;\n    MemWriteEngine#(DataBusWidth,DataBusWidth,2,1) wEngine <- mkMemWriteEngine;\n    Vector#(2, Server#(Double,Float)) dToF <- replicateM(mkDoubleToFloat);\n    DotProd dotp <- mkDotProd;\n    Reg#(ConnectalParamType) param <- mkReg(unpack(0));\n    Reg#(Bit#(32)) p_limit <- mkReg(0);\n    Reg#(Bit#(32)) q_limit <- mkReg(0);\n    Reg#(Bit#(1)) skip <- mkReg(0);\n    Reg#(Bit#(32)) bpx <- mkReg(0);\n    Reg#(Bit#(32)) wpx <- mkReg(0);\n    Reg#(Bit#(32)) outputp <- mkReg(0);\n    Reg#(Bit#(32)) k <- mkReg(0);\n    Reg#(Bit#(32)) p <- mkReg(0);\n    Reg#(Bit#(32)) bp <- mkReg(0);\n    Reg#(Bit#(32)) wp <- mkReg(0);\n    Reg#(Bool)     fsmRunning <- mkReg(False);\n    Reg#(Bit#(BurstLenSize)) burstLenInBytes <- mkReg(8);\n    Reg#(Bool) dtypeFloat <- mkReg(False);\n    Reg#(Bool) dumpStart <- mkReg(False);\n    FIFOF#(Bool) dLast <- mkFIFOF;\n\n    rule readResD if (!dtypeFloat);\n        let vb <- toGet(rEngine.readServers[0].data).get;\n        let vw <- toGet(rEngine.readServers[1].data).get;\n        dToF[0].request.put(unpack(vb.data));\n        dToF[1].request.put(unpack(vw.data));\n        toPut(dLast).put(vb.last);\n    endrule\n\n    rule pushDotD;\n        let vb <- dToF[0].response.get();\n        let vw <- dToF[1].response.get();\n        let vl <- toGet(dLast).get();\n        toPut(dotp.sendPair).put(DotType{a: vb, b: vw, last: vl});\n    endrule\n\n    rule readResF if (dtypeFloat);\n        let vb <- toGet(rEngine.readServers[0].data).get;\n        let vw <- toGet(rEngine.readServers[1].data).get;\n        Vector#(2, DotType) temp;\n        temp[0] = DotType{a: unpack(vb.data[31:0]), b: unpack(vw.data[31:0]), last: False};\n        temp[1] = DotType{a: unpack(vb.data[63:32]), b: unpack(vw.data[63:32]), last: vb.last};\n        if (vb.last && skip != 0)\n            temp[1].a = 0;\n        floatGear.enq(temp);\n    endrule\n\n    rule pushDotF;\n        let vb <- toGet(floatGear).get;\n        toPut(dotp.sendPair).put(vb);\n    endrule\n\n    rule finishProcessing;\n        let v <- toGet(dotp.done).get;\n        // Write convolution result into output (image, channel, y, x)\n        //  *CACCESS(outputp) = v;\n        indication.outputp(outputp, v);\n        fsmRunning <= False;\n    endrule\n\n    FSM fsm <- mkFSM(seq\n        // for each 'in_group', add contribution into convolution\n        for ( k <= 0; k < param.in_group_size; k <= k + 1) seq\n            bp <= bpx;\n            wp <= wpx;\n            // Calculate single 2D filter convolution\n            for ( p <= 0; p < p_limit; p <= p + 1) action\n                dotp.incrementWait;\n                rEngine.readServers[0].request.put(MemengineCmd{sglId:param.objectId,\n                    base:extend(bp), len:q_limit, burstLen:burstLenInBytes, tag: 0});\n                rEngine.readServers[1].request.put(MemengineCmd{sglId:param.objectId,\n                    base:extend(wp), len:q_limit, burstLen:burstLenInBytes, tag: 0});\n                bp <= bp + param.conv_in_width;\n                wp <= wp + param.kernel_w;\n            endaction\n            bpx <= bpx + param.bottom_hw;\n            wpx <= wpx + param.kernel_hw;\n        endseq\n        endseq);\n\n    interface ConvRequest request;\n        method Action init(ConnectalParamType aparam);\n            param <= aparam;\n            dtypeFloat <= (aparam.baseSize == 4);\n            if (!dumpStart) begin\n               //$dumpon;\n               dumpStart <= True;\n            end\n        endmethod\n\n        method Action forward_kernel(Bit#(32) ap_limit, Bit#(32) aq_limit, Bit#(1) askip, Float atemp, Bit#(32) abpx, Bit#(32) awpx, Bit#(32) aoutputp) if (!fsmRunning);\n            p_limit <= ap_limit;\n            q_limit <= aq_limit;\n            skip <= askip;\n            dotp.init(atemp);\n            bpx <= extend(abpx);\n            wpx <= extend(awpx);\n            outputp <= aoutputp;\n            fsmRunning <= True;\n            fsm.start();\n        endmethod\n    endinterface\n    interface readDma = cons(rEngine.dmaClient, nil);\n    interface writeDma = cons(wEngine.dmaClient, nil);\nendmodule\n\n//void backward_bias(const ParamType<Dtype> *param, CPtr tptr)\n//{\n//  int output_hw = param->height_out_ * param->width_out_ * sizeof(Dtype);\n//  for (int j = 0; j < param->num_output_ * sizeof(Dtype); j += sizeof(Dtype)) {\n//    Dtype temp = 0;\n//    for (int i = 0; i < output_hw; i += sizeof(Dtype)) {\n//      temp += *CACCESS(tptr) * *CACCESS(param->bias_multiplier_ + i);\n//      tptr += sizeof(Dtype);\n//    }\n//    *CACCESS(param->bias_diff + j) += temp;\n//  }\n//}\n\n//void backward_kernel(const ParamType<Dtype> *param, int pad_x, int pad_y, int gchan, int wchan, Dtype chain_grad, CPtr bottom_bp, CPtr bottom_diff_bp)\n//{\n//  int p_start = MAX(0, pad_y);\n//  int p_limit = MIN(param->kernel_h_ * sizeof(Dtype), param->conv_in_height_ * sizeof(Dtype) + pad_y);\n//  int q_start = MAX(0, pad_x);\n//  int q_limit = MIN(param->kernel_w_ * sizeof(Dtype), param->conv_in_width_ * sizeof(Dtype) + pad_x);\n//  for (int p = p_start; p < p_limit; p += sizeof(Dtype)) {\n//    for (int q = q_start; q < q_limit; q += sizeof(Dtype)) {\n//      int belement = gchan + p * param->conv_in_width_ + q;\n//      int welement = wchan + p * param->kernel_w_ + q;\n//      // gradient w.r.t. weight. Note that we will accumulate diffs.\n//      if (param->weight_diff)\n//        *CACCESS(param->weight_diff + welement) += *CACCESS(bottom_bp + belement) * chain_grad;\n//      // gradient w.r.t. bottom data, if necessary.\n//      if (bottom_diff_bp)\n//        *CACCESS(bottom_diff_bp + belement) += *CACCESS(param->weight + welement) * chain_grad;\n//    }\n//  }\n//}\n"
  },
  {
    "path": "examples/caffe/INSTALL",
    "content": "\ncmake\nlibboost-all-dev\nlibgoogle-glog-dev\nlibprotobuf-dev protobuf-compiler\nlibhdf5-dev\nliblmdb-dev\nlibleveldb-dev\nlibsnappy-dev\nlibopencv-dev\nlibatlas-dev\nlibatlas-blas-dev\nlibblas-dev\nlibopenblas-dev\nlibatlas-base-dev\nlibpapi-dev\n"
  },
  {
    "path": "examples/caffe/Makefile",
    "content": "CONNECTALDIR?=../..\nS2H_INTERFACES = ConvRequest:Conv.request\nH2S_INTERFACES = Conv:ConvIndication\nMEM_READ_INTERFACES = lConv.readDma\nMEM_WRITE_INTERFACES = lConv.writeDma\n\n# Direct convolution/gradient calculation version\nCPPFILES = $(CONNECTALDIR)/lib/cpp/connectal_conv.cpp\nBSVFILES = Conv.bsv\nCONNECTALFLAGS += --shared --bsvpath $(CONNECTALDIR)/lib/matmul/bsv\n\ninclude $(CONNECTALDIR)/Makefile.connectal\n"
  },
  {
    "path": "examples/caffe/README.md",
    "content": "apt-get install libopencv-dev libopencv-core-dev \napt-get install autoconf\napt-get install libtool\napt-get install gtkwave\napt-get install cmake\napt-get install boost\napt-get install libboost-dev\napt-get install libboost-system\napt-get install libboost-system-dev libboost-thread-dev\napt-get install libgoogle-glog-dev glib-dev\napt-get install libgoogle-glog-dev \napt-get install libhdf5-dev\napt-get install liblmdb-dev\napt-get install libleveldb-dev \napt-get install libsnappy-dev\napt-get install libatlas-dev\napt-get install libopenblas-dev\napt-get install libatlas-dev libblas-test libopenblas-dev libatlas-cpp-0.6-dev libatlas-base-dev\napt-get install python-numpy\napt-get install libboost-python-dev \napt-get install python-numpy\napt-get install gfortran\n\n\n\n"
  },
  {
    "path": "examples/echo/Echo.bsv",
    "content": "// Copyright (c) 2013 Nokia, Inc.\n// Copyright (c) 2013 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\nimport FIFO::*;\nimport Vector::*;\n\ninterface EchoIndication;\n    method Action heard(Bit#(32) v);\n    method Action heard2(Bit#(16) a, Bit#(16) b);\nendinterface\n\ninterface EchoRequest;\n   method Action say(Bit#(32) v);\n   method Action say2(Bit#(16) a, Bit#(16) b);\n   method Action setLeds(Bit#(8) v);\nendinterface\n\ninterface Echo;\n   interface EchoRequest request;\nendinterface\n\ntypedef struct {\n\tBit#(16) a;\n\tBit#(16) b;\n} EchoPair deriving (Bits);\n\nmodule mkEcho#(EchoIndication indication)(Echo);\n    FIFO#(Bit#(32)) delay <- mkSizedFIFO(8);\n    FIFO#(EchoPair) delay2 <- mkSizedFIFO(8);\n\n    rule heard;\n        delay.deq;\n        indication.heard(delay.first);\n    endrule\n\n    rule heard2;\n        delay2.deq;\n        indication.heard2(delay2.first.b, delay2.first.a);\n    endrule\n   \n   interface EchoRequest request;\n      method Action say(Bit#(32) v);\n\t delay.enq(v);\n      endmethod\n      \n      method Action say2(Bit#(16) a, Bit#(16) b);\n\t delay2.enq(EchoPair { a: a, b: b});\n      endmethod\n      \n      method Action setLeds(Bit#(8) v);\n      endmethod\n   endinterface\nendmodule\n"
  },
  {
    "path": "examples/echo/Makefile",
    "content": "CONNECTALDIR?=../..\nS2H_INTERFACES = EchoRequest:Echo.request\nH2S_INTERFACES = Echo:EchoIndication\n\nBSVFILES = Echo.bsv\nCPPFILES= testecho.cpp\n\nCONNECTALFLAGS += -D TRACE_PORTAL\n\ninclude $(CONNECTALDIR)/Makefile.connectal\n\n"
  },
  {
    "path": "examples/echo/testecho.cpp",
    "content": "/* Copyright (c) 2014 Quanta Research Cambridge, Inc\n *\n * Permission is hereby granted, free of charge, to any person obtaining a\n * copy of this software and associated documentation files (the \"Software\"),\n * to deal in the Software without restriction, including without limitation\n * the rights to use, copy, modify, merge, publish, distribute, sublicense,\n * and/or sell copies of the Software, and to permit persons to whom the\n * Software is furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n * DEALINGS IN THE SOFTWARE.\n */\n\n#include <errno.h>\n#include <stdio.h>\n#include \"EchoIndication.h\"\n#include \"EchoRequest.h\"\n#include \"GeneratedTypes.h\"\n\nstatic EchoRequestProxy *echoRequestProxy = 0;\nstatic sem_t sem_heard2;\n\nclass EchoIndication : public EchoIndicationWrapper\n{\npublic:\n    virtual void heard(uint32_t v) {\n        printf(\"heard an echo: %d\\n\", v);\n\techoRequestProxy->say2(v, 2*v);\n    }\n    virtual void heard2(uint16_t a, uint16_t b) {\n        sem_post(&sem_heard2);\n        //printf(\"heard an echo2: %ld %ld\\n\", a, b);\n    }\n    EchoIndication(unsigned int id) : EchoIndicationWrapper(id) {}\n};\n\nstatic void call_say(int v)\n{\n    printf(\"[%s:%d] %d\\n\", __FUNCTION__, __LINE__, v);\n    echoRequestProxy->say(v);\n    sem_wait(&sem_heard2);\n}\n\nstatic void call_say2(int v, int v2)\n{\n    echoRequestProxy->say2(v, v2);\n    sem_wait(&sem_heard2);\n}\n\nint main(int argc, const char **argv)\n{\n    long actualFrequency = 0;\n    long requestedFrequency = 1e9 / MainClockPeriod;\n\n    EchoIndication echoIndication(IfcNames_EchoIndicationH2S);\n    echoRequestProxy = new EchoRequestProxy(IfcNames_EchoRequestS2H);\n\n    int status = setClockFrequency(0, requestedFrequency, &actualFrequency);\n    fprintf(stderr, \"Requested main clock frequency %5.2f, actual clock frequency %5.2f MHz status=%d errno=%d\\n\",\n\t    (double)requestedFrequency * 1.0e-6,\n\t    (double)actualFrequency * 1.0e-6,\n\t    status, (status != 0) ? errno : 0);\n\n    int v = 42;\n    printf(\"Saying %d\\n\", v);\n    call_say(v);\n    call_say(v*5);\n    call_say(v*17);\n    call_say(v*93);\n    call_say2(v, v*3);\n    printf(\"TEST TYPE: SEM\\n\");\n    echoRequestProxy->setLeds(9);\n    return 0;\n}\n"
  },
  {
    "path": "examples/echo2ind/Echo.bsv",
    "content": "// Copyright (c) 2013 Nokia, Inc.\n// Copyright (c) 2013 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\nimport FIFO::*;\nimport Vector::*;\n\ninterface EchoIndication;\n    method Action heard(Bit#(32) v);\n    method Action heard2(Bit#(16) a, Bit#(16) b);\nendinterface\n\ninterface EchoRequest;\n   method Action say(Bit#(32) v);\n   method Action say2(Bit#(16) a, Bit#(16) b);\n   method Action setLeds(Bit#(8) v);\nendinterface\n\ninterface Echo;\n   interface EchoRequest request1;\n   interface EchoRequest request2;\nendinterface\n\ntypedef struct {\n\tBit#(16) a;\n\tBit#(16) b;\n} EchoPair deriving (Bits);\n\nmodule mkEcho#(EchoIndication indication1, EchoIndication indication2)(Echo);\n    FIFO#(Bit#(32)) delay <- mkSizedFIFO(8);\n    FIFO#(EchoPair) delay2 <- mkSizedFIFO(8);\n\n    rule heard;\n        delay.deq;\n        indication1.heard(delay.first);\n    endrule\n\n    rule heard2;\n        delay2.deq;\n        indication2.heard2(delay2.first.b, delay2.first.a);\n    endrule\n   \n   interface EchoRequest request1;\n      method Action say(Bit#(32) v);\n\t delay.enq(v);\n      endmethod\n      \n      method Action say2(Bit#(16) a, Bit#(16) b);\n\t delay2.enq(EchoPair { a: a, b: b});\n      endmethod\n      \n      method Action setLeds(Bit#(8) v);\n      endmethod\n   endinterface\n   \n   interface EchoRequest request2;\n      method Action say(Bit#(32) v);\n\t delay.enq(v);\n      endmethod\n      \n      method Action say2(Bit#(16) a, Bit#(16) b);\n\t delay2.enq(EchoPair { a: a, b: b});\n      endmethod\n      \n      method Action setLeds(Bit#(8) v);\n      endmethod\n   endinterface\nendmodule\n"
  },
  {
    "path": "examples/echo2ind/Makefile",
    "content": "# Test program for multiple interfaces of same datatype\nCONNECTALDIR?=../..\nS2H_INTERFACES = EchoRequest:Echo.request1,Echo.request2\nH2S_INTERFACES = Echo:EchoIndication,EchoIndication\n\nBSVFILES = Echo.bsv\nCPPFILES= testecho.cpp\n\ninclude $(CONNECTALDIR)/Makefile.connectal\n\n"
  },
  {
    "path": "examples/echo2ind/testecho.cpp",
    "content": "/* Copyright (c) 2014 Quanta Research Cambridge, Inc\n *\n * Permission is hereby granted, free of charge, to any person obtaining a\n * copy of this software and associated documentation files (the \"Software\"),\n * to deal in the Software without restriction, including without limitation\n * the rights to use, copy, modify, merge, publish, distribute, sublicense,\n * and/or sell copies of the Software, and to permit persons to whom the\n * Software is furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n * DEALINGS IN THE SOFTWARE.\n */\n\n#include <errno.h>\n#include <stdio.h>\n#include \"EchoIndication.h\"\n#include \"EchoRequest.h\"\n#include \"GeneratedTypes.h\"\n\nstatic EchoRequestProxy *echoRequestProxy = 0;\nstatic EchoRequestProxy *echoRequestProxy1 = 0;\nstatic sem_t sem_heard2;\n\nclass EchoIndication : public EchoIndicationWrapper\n{\npublic:\n    virtual void heard(uint32_t v) {\n        printf(\"heard an echo: %d\\n\", v);\n\techoRequestProxy->say2(v, 2*v);\n    }\n    virtual void heard2(uint16_t a, uint16_t b) {\n        sem_post(&sem_heard2);\n        //printf(\"heard an echo2: %ld %ld\\n\", a, b);\n    }\n    EchoIndication(unsigned int id) : EchoIndicationWrapper(id) {}\n};\n\nstatic void call_say(int v)\n{\n    printf(\"[%s:%d] %d\\n\", __FUNCTION__, __LINE__, v);\n    echoRequestProxy->say(v);\n    sem_wait(&sem_heard2);\n}\n\nstatic void call_say2(int v, int v2)\n{\n    echoRequestProxy->say2(v, v2);\n    sem_wait(&sem_heard2);\n}\n\nint main(int argc, const char **argv)\n{\n    long actualFrequency = 0;\n    long requestedFrequency = 1e9 / MainClockPeriod;\n\n    EchoIndication echoIndication(IfcNames_EchoIndicationH2S0);\n    EchoIndication echoIndication1(IfcNames_EchoIndicationH2S1);\n    echoRequestProxy = new EchoRequestProxy(IfcNames_EchoRequestS2H0);\n    echoRequestProxy1 = new EchoRequestProxy(IfcNames_EchoRequestS2H1);\n\n    int status = setClockFrequency(0, requestedFrequency, &actualFrequency);\n    fprintf(stderr, \"Requested main clock frequency %5.2f, actual clock frequency %5.2f MHz status=%d errno=%d\\n\",\n\t    (double)requestedFrequency * 1.0e-6,\n\t    (double)actualFrequency * 1.0e-6,\n\t    status, (status != 0) ? errno : 0);\n\n    int v = 42;\n    printf(\"Saying %d\\n\", v);\n    call_say(v);\n    call_say(v*5);\n    call_say(v*17);\n    call_say(v*93);\n    call_say2(v, v*3);\n    printf(\"TEST TYPE: SEM\\n\");\n    echoRequestProxy->setLeds(9);\n    return 0;\n}\n"
  },
  {
    "path": "examples/echofast/Makefile",
    "content": "CONNECTALFLAGS += -D BSV_POSITIVE_RESET\n\nifeq ($(BOARD),zedboard)\nMAIN_CLOCK_PERIOD=5.0\nDERIVED_CLOCK_PERIOD=10.0\nendif\nifeq ($(BOARD),zc706)\nMAIN_CLOCK_PERIOD=2.0\nDERIVED_CLOCK_PERIOD=5.0\nendif\n\ninclude ../echo/Makefile\n"
  },
  {
    "path": "examples/echohost/Echo.bsv",
    "content": "// Copyright (c) 2013 Nokia, Inc.\n// Copyright (c) 2013 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\nimport FIFO::*;\nimport Vector::*;\nimport ConnectalConfig::*;\nimport HostInterface::*;\n\ninterface EchoIndication;\n    method Action heard(Bit#(32) v);\n    method Action heard2(Bit#(16) a, Bit#(16) b);\nendinterface\n\ninterface EchoRequest;\n   method Action say(Bit#(32) v);\n   method Action say2(Bit#(16) a, Bit#(16) b);\n   method Action setLeds(Bit#(8) v);\nendinterface\n\ninterface Echo;\n   interface EchoRequest request;\nendinterface\n\ntypedef struct {\n\tBit#(16) a;\n\tBit#(16) b;\n} EchoPair deriving (Bits);\n\nmodule mkEcho#(HostInterface host, EchoIndication indication)(Echo);\n    FIFO#(Bit#(32)) delay <- mkSizedFIFO(8);\n    FIFO#(EchoPair) delay2 <- mkSizedFIFO(8);\n\n    rule heard;\n        delay.deq;\n        indication.heard(delay.first);\n    endrule\n\n    rule heard2;\n        delay2.deq;\n        indication.heard2(delay2.first.b, delay2.first.a);\n    endrule\n   \n   interface EchoRequest request;\n      method Action say(Bit#(32) v);\n\t delay.enq(v);\n      endmethod\n      \n      method Action say2(Bit#(16) a, Bit#(16) b);\n\t delay2.enq(EchoPair { a: a, b: b});\n      endmethod\n      \n      method Action setLeds(Bit#(8) v);\n      endmethod\n   endinterface\nendmodule\n"
  },
  {
    "path": "examples/echohost/Makefile",
    "content": "CONNECTALDIR?=../..\nS2H_INTERFACES = EchoRequest:Echo.request:host\nH2S_INTERFACES = Echo:EchoIndication:host\n\nBSVFILES = ../echo/Echo.bsv\nCPPFILES= ../echo/testecho.cpp\n## for testing fpgamake:\nFPGAMAKE_CONNECTALFLAGS += -P mkEchoIndicationProxySynth -P mkEchoRequestWrapperMemPortalPipes\nPORTAL_DUMP_MAP = \"EchoIndication:EchoRequest:SwallowRequest\"\nCONNECTALFLAGS += -D IMPORT_HOSTIF\n\ninclude $(CONNECTALDIR)/Makefile.connectal\n"
  },
  {
    "path": "examples/echohost/testecho.cpp",
    "content": "/* Copyright (c) 2014 Quanta Research Cambridge, Inc\n *\n * Permission is hereby granted, free of charge, to any person obtaining a\n * copy of this software and associated documentation files (the \"Software\"),\n * to deal in the Software without restriction, including without limitation\n * the rights to use, copy, modify, merge, publish, distribute, sublicense,\n * and/or sell copies of the Software, and to permit persons to whom the\n * Software is furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n * DEALINGS IN THE SOFTWARE.\n */\n\n#include <errno.h>\n#include <stdio.h>\n#include \"EchoIndication.h\"\n#include \"EchoRequest.h\"\n#include \"GeneratedTypes.h\"\n\nstatic EchoRequestProxy *echoRequestProxy = 0;\nstatic sem_t sem_heard2;\n\nclass EchoIndication : public EchoIndicationWrapper\n{\npublic:\n    virtual void heard(uint32_t v) {\n        printf(\"heard an echo: %d\\n\", v);\n\techoRequestProxy->say2(v, 2*v);\n    }\n    virtual void heard2(uint16_t a, uint16_t b) {\n        sem_post(&sem_heard2);\n        //printf(\"heard an echo2: %ld %ld\\n\", a, b);\n    }\n    EchoIndication(unsigned int id) : EchoIndicationWrapper(id) {}\n};\n\nstatic void call_say(int v)\n{\n    printf(\"[%s:%d] %d\\n\", __FUNCTION__, __LINE__, v);\n    echoRequestProxy->say(v);\n    sem_wait(&sem_heard2);\n}\n\nstatic void call_say2(int v, int v2)\n{\n    echoRequestProxy->say2(v, v2);\n    sem_wait(&sem_heard2);\n}\n\nint main(int argc, const char **argv)\n{\n    long actualFrequency = 0;\n    long requestedFrequency = 1e9 / MainClockPeriod;\n\n    EchoIndication echoIndication(IfcNames_EchoIndicationH2S);\n    echoRequestProxy = new EchoRequestProxy(IfcNames_EchoRequestS2H);\n\n    int status = setClockFrequency(0, requestedFrequency, &actualFrequency);\n    fprintf(stderr, \"Requested main clock frequency %5.2f, actual clock frequency %5.2f MHz status=%d errno=%d\\n\",\n\t    (double)requestedFrequency * 1.0e-6,\n\t    (double)actualFrequency * 1.0e-6,\n\t    status, (status != 0) ? errno : 0);\n\n    int v = 42;\n    printf(\"Saying %d\\n\", v);\n    call_say(v);\n    call_say(v*5);\n    call_say(v*17);\n    call_say(v*93);\n    call_say2(v, v*3);\n    printf(\"TEST TYPE: SEM\\n\");\n    echoRequestProxy->setLeds(9);\n    return 0;\n}\n"
  },
  {
    "path": "examples/echohost/vc707_floorplan.xdc",
    "content": "startgroup\ncreate_pblock pblock_ep7\nresize_pblock pblock_ep7 -add {SLICE_X184Y54:SLICE_X221Y166 DSP48_X18Y22:DSP48_X19Y65 RAMB18_X12Y22:RAMB18_X14Y65 RAMB36_X12Y11:RAMB36_X14Y32}\nadd_cells_to_pblock pblock_ep7 [get_cells [list host_ep7]] -clear_locs\nset_property HD.PARTPIN_RANGE {SLICE_X185Y54:SLICE_X186Y166} [get_pins host_ep7/*]\nset_property CONTAIN_ROUTING true [get_pblocks pblock_ep7]\nendgroup\n\nstartgroup\ncreate_pblock pblock_pciehost\nresize_pblock pblock_pciehost -add {SLICE_X112Y55:SLICE_X173Y197 DSP48_X9Y22:DSP48_X16Y77 RAMB18_X7Y22:RAMB18_X10Y77 RAMB36_X7Y11:RAMB36_X10Y38}\nadd_cells_to_pblock pblock_pciehost [get_cells [list host_pciehost]] -clear_locs\nset_property HD.PARTPIN_RANGE {SLICE_X112Y55:SLICE_X113Y197} [get_pins host_pciehost/*]\nset_property HD.PARTPIN_RANGE {SLICE_X172Y55:SLICE_X173Y197} [get_pins host_pciehost/*pci_re*]\nset_property HD.PARTPIN_RANGE {SLICE_X172Y55:SLICE_X173Y197} [get_pins host_pciehost/*pci*]\nset_property CONTAIN_ROUTING true [get_pblocks pblock_pciehost]\nendgroup\n\n# startgroup\n# create_pblock pblock_pciehost\n# resize_pblock pblock_pciehost -add {SLICE_X112Y55:SLICE_X221Y197 DSP48_X9Y22:DSP48_X19Y77 RAMB18_X7Y22:RAMB18_X14Y77 RAMB36_X7Y11:RAMB36_X14Y38}\n# add_cells_to_pblock pblock_pciehost [get_cells [list host]] -clear_locs\n# set_property HD.PARTPIN_RANGE {SLICE_X112Y55:SLICE_X113Y197} [get_pins host/*]\n# endgroup\n\n"
  },
  {
    "path": "examples/echoinvert/Echo.bsv",
    "content": "// Copyright (c) 2013 Nokia, Inc.\n// Copyright (c) 2013 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n`include \"ConnectalProjectConfig.bsv\"\nimport FIFO::*;\nimport Vector::*;\nimport EchoInterface::*;\nimport EchoIndication::*;\n\ninterface Echo;\n   interface EchoRequest request;\n   interface EchoIndicationInverse inverseIfc;\nendinterface\n\ntypedef struct {\n\tBit#(16) a;\n\tBit#(16) b;\n} EchoPair deriving (Bits);\n\nmodule mkEcho(Echo);\n`ifdef BOARD_bluesim\n    let inv <- mkEchoIndicationInverter;\n`else\n    let inv <- mkEchoIndicationInverterV;\n`endif\n    EchoIndication indication = inv.ifc;\n    FIFO#(Bit#(32)) delay <- mkSizedFIFO(8);\n    FIFO#(EchoPair) delay2 <- mkSizedFIFO(8);\n    Reg#(Bool) dumpStart <- mkReg(False);\n\n    rule heard;\n        delay.deq;\n        indication.heard(delay.first);\n    endrule\n\n    rule heard2;\n        delay2.deq;\n        indication.heard2(delay2.first.b, delay2.first.a);\n    endrule\n   \n   interface EchoRequest request;\n      method Action say(Bit#(32) v);\n         if (!dumpStart) begin\n            $dumpon;\n            dumpStart <= True;\n         end\n\t delay.enq(v);\n      endmethod\n      \n      method Action say2(Bit#(16) a, Bit#(16) b);\n\t delay2.enq(EchoPair { a: a, b: b});\n      endmethod\n      \n      method Action setLeds(Bit#(8) v);\n      endmethod\n   endinterface\n   interface inverseIfc = inv.inverseIfc;\nendmodule\n"
  },
  {
    "path": "examples/echoinvert/EchoInterface.bsv",
    "content": "\ninterface EchoIndication;\n    method Action heard(Bit#(32) v);\n    method Action heard2(Bit#(16) a, Bit#(16) b);\nendinterface\n\ninterface EchoRequest;\n   method Action say(Bit#(32) v);\n   method Action say2(Bit#(16) a, Bit#(16) b);\n   method Action setLeds(Bit#(8) v);\nendinterface\n"
  },
  {
    "path": "examples/echoinvert/Makefile",
    "content": "CONNECTALDIR?=../..\nS2H_INTERFACES = EchoRequest:Echo.request\nH2S_INTERFACES = !Echo:EchoIndication\n\nBSVFILES = EchoInterface.bsv\nCPPFILES= testecho.cpp\n\ninclude $(CONNECTALDIR)/Makefile.connectal\n\n"
  },
  {
    "path": "examples/echoinvert/testecho.cpp",
    "content": "/* Copyright (c) 2014 Quanta Research Cambridge, Inc\n *\n * Permission is hereby granted, free of charge, to any person obtaining a\n * copy of this software and associated documentation files (the \"Software\"),\n * to deal in the Software without restriction, including without limitation\n * the rights to use, copy, modify, merge, publish, distribute, sublicense,\n * and/or sell copies of the Software, and to permit persons to whom the\n * Software is furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n * DEALINGS IN THE SOFTWARE.\n */\n\n#include <errno.h>\n#include <stdio.h>\n#include \"EchoIndication.h\"\n#include \"EchoRequest.h\"\n#include \"GeneratedTypes.h\"\n\nstatic EchoRequestProxy *echoRequestProxy = 0;\nstatic sem_t sem_heard2;\n\nclass EchoIndication : public EchoIndicationWrapper\n{\npublic:\n    virtual void heard(uint32_t v) {\n        printf(\"heard an echo: %d\\n\", v);\n\techoRequestProxy->say2(v, 2*v);\n    }\n    virtual void heard2(uint16_t a, uint16_t b) {\n        sem_post(&sem_heard2);\n        //printf(\"heard an echo2: %ld %ld\\n\", a, b);\n    }\n    EchoIndication(unsigned int id) : EchoIndicationWrapper(id) {}\n};\n\nstatic void call_say(int v)\n{\n    printf(\"[%s:%d] %d\\n\", __FUNCTION__, __LINE__, v);\n    echoRequestProxy->say(v);\n    sem_wait(&sem_heard2);\n}\n\nstatic void call_say2(int v, int v2)\n{\n    echoRequestProxy->say2(v, v2);\n    sem_wait(&sem_heard2);\n}\n\nint main(int argc, const char **argv)\n{\n    long actualFrequency = 0;\n    long requestedFrequency = 1e9 / MainClockPeriod;\n\n    EchoIndication echoIndication(IfcNames_EchoIndicationH2S);\n    echoRequestProxy = new EchoRequestProxy(IfcNames_EchoRequestS2H);\n\n    int status = setClockFrequency(0, requestedFrequency, &actualFrequency);\n    fprintf(stderr, \"Requested main clock frequency %5.2f, actual clock frequency %5.2f MHz status=%d errno=%d\\n\",\n\t    (double)requestedFrequency * 1.0e-6,\n\t    (double)actualFrequency * 1.0e-6,\n\t    status, (status != 0) ? errno : 0);\n\n    int v = 42;\n    printf(\"Saying %d\\n\", v);\n    call_say(v);\n    call_say(v*5);\n    call_say(v*17);\n    call_say(v*93);\n    call_say2(v, v*3);\n    printf(\"TEST TYPE: SEM\\n\");\n    echoRequestProxy->setLeds(9);\n    return 0;\n}\n"
  },
  {
    "path": "examples/echojson/Echo.bsv",
    "content": "\n// Copyright (c) 2013 Nokia, Inc.\n// Copyright (c) 2013 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\nimport FIFO::*;\nimport Vector::*;\n\ninterface EchoIndication;\n    method Action heard(Bit#(32) v);\n    method Action heard2(Bit#(16) a, Bit#(16) b);\nendinterface\n\ninterface EchoRequest;\n   method Action say(Bit#(32) v);\n   method Action say2(Bit#(16) a, Bit#(16) b);\n   method Action setLeds(Bit#(8) v);\nendinterface\n\ninterface Echo;\n   interface EchoRequest request;\nendinterface\n\ntypedef struct {\n\tBit#(16) a;\n\tBit#(16) b;\n} EchoPair deriving (Bits);\n\nmodule mkEcho#(EchoIndication indication)(Echo);\n    FIFO#(Bit#(32)) delay <- mkSizedFIFO(8);\n    FIFO#(EchoPair) delay2 <- mkSizedFIFO(8);\n\n    rule heard;\n        delay.deq;\n        indication.heard(delay.first);\n    endrule\n\n    rule heard2;\n        delay2.deq;\n        indication.heard2(delay2.first.b, delay2.first.a);\n    endrule\n   \n   interface EchoRequest request;\n      method Action say(Bit#(32) v);\n\t delay.enq(v);\n      endmethod\n      \n      method Action say2(Bit#(16) a, Bit#(16) b);\n\t delay2.enq(EchoPair { a: a, b: b});\n      endmethod\n      \n      method Action setLeds(Bit#(8) v);\n      endmethod\n   endinterface\nendmodule\n"
  },
  {
    "path": "examples/echojson/Makefile",
    "content": "CONNECTALDIR?=../..\nS2H_INTERFACES = EchoRequest:Echo.request SwallowRequest:Swallow.request\nH2S_INTERFACES = Echo:EchoIndication\n\nBSVFILES = Echo.bsv Swallow.bsv\nCPPFILES=testecho.cpp\nCPPFILES2=daemon.cpp\n\ninclude $(CONNECTALDIR)/Makefile.connectal\n"
  },
  {
    "path": "examples/echojson/Swallow.bsv",
    "content": "\n// Copyright (c) 2013 Nokia, Inc.\n// Copyright (c) 2013 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\ninterface SwallowRequest;\n   method Action swallow(Bit#(32) v);\nendinterface\n\ninterface Swallow;\n   interface SwallowRequest request;\nendinterface\nmodule mkSwallow(Swallow);\n\n   Reg#(Bit#(32)) sink <- mkReg(0);\n   \n   interface SwallowRequest request;\n   method Action swallow(Bit#(32) v);\n      sink <= v;\n   endmethod\n   endinterface\n\nendmodule\n"
  },
  {
    "path": "examples/echojson/daemon.cpp",
    "content": "/* Copyright (c) 2014 Quanta Research Cambridge, Inc\n *\n * Permission is hereby granted, free of charge, to any person obtaining a\n * copy of this software and associated documentation files (the \"Software\"),\n * to deal in the Software without restriction, including without limitation\n * the rights to use, copy, modify, merge, publish, distribute, sublicense,\n * and/or sell copies of the Software, and to permit persons to whom the\n * Software is furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n * DEALINGS IN THE SOFTWARE.\n */\n\n#include <stdio.h>\n#include <netdb.h>\n\n#include \"sock_utils.h\"\n\n#include \"EchoRequest.h\"\n#include \"EchoIndication.h\"\n\nEchoRequestProxy *echoRequestProxy;\nEchoIndicationProxy *sIndicationProxy;\nstatic int daemon_trace ;//= 1;\n\nclass EchoIndication : public EchoIndicationWrapper\n{\npublic:\n    void heard(uint32_t v) {\n        if (daemon_trace)\n        fprintf(stderr, \"daemon: %p heard an echo: %d\\n\", sIndicationProxy, v);\n        sIndicationProxy->heard(v);\n    }\n    void heard2(uint16_t a, uint16_t b) {\n        if (daemon_trace)\n        fprintf(stderr, \"daemon: %p heard an echo2: %d %d\\n\", sIndicationProxy, a, b);\n        sIndicationProxy->heard2(a, b);\n    }\n    EchoIndication(unsigned int id, PortalTransportFunctions *item, void *param) : EchoIndicationWrapper(id, item, param) {}\n};\n\nclass EchoRequest : public EchoRequestWrapper\n{\npublic:\n    void say ( const uint32_t v ) {\n        if (daemon_trace)\n        fprintf(stderr, \"daemon[%s:%d] proxy %p\\n\", __FUNCTION__, __LINE__, echoRequestProxy);\n        echoRequestProxy->say(v);\n    }\n    void say2 ( const uint16_t a, const uint16_t b ) {\n        if (daemon_trace)\n        fprintf(stderr, \"daemon[%s:%d] proxy %p\\n\", __FUNCTION__, __LINE__, echoRequestProxy);\n        echoRequestProxy->say2(a, b);\n    }\n    void setLeds ( const uint8_t v ) {\n        fprintf(stderr, \"daemon[%s:%d] proxy %p\\n\", __FUNCTION__, __LINE__, echoRequestProxy);\n        echoRequestProxy->setLeds(v);\n        sleep(1);\n        exit(1);\n    }\n    EchoRequest(unsigned int id, PortalTransportFunctions *item, void *param) : EchoRequestWrapper(id, item, param, &EchoRequestJson_handleMessage, 1000) {}\n};\n\nint main(int argc, const char **argv)\n{\n    PortalSocketParam param;\n//#define USE_UNIX_SOCKET\n#ifdef USE_UNIX_SOCKET\n#define PARAM NULL\n#else\n#define PARAM &param\n#endif\n\n    EchoIndication *echoIndication = new EchoIndication(IfcNames_EchoIndicationH2S, NULL, NULL);\n    echoRequestProxy = new EchoRequestProxy(IfcNames_EchoRequestS2H);\n    int rc = getaddrinfo(\"127.0.0.1\", \"5000\", NULL, &param.addr);\n    sIndicationProxy = new EchoIndicationProxy(IfcNames_EchoIndicationH2S, &transportSocketResp, PARAM, &EchoIndicationJsonProxyReq, 1000);\n    rc = getaddrinfo(\"127.0.0.1\", \"5001\", NULL, &param.addr);\n    EchoRequest *sRequest = new EchoRequest(IfcNames_EchoRequestS2H, &transportSocketResp, PARAM);\n\n    printf(\"[%s:%d] daemon sleeping...\\n\", __FUNCTION__, __LINE__);\n    while(1)\n        sleep(100);\n    return 0;\n}\n"
  },
  {
    "path": "examples/echojson/testecho.cpp",
    "content": "/* Copyright (c) 2014 Quanta Research Cambridge, Inc\n *\n * Permission is hereby granted, free of charge, to any person obtaining a\n * copy of this software and associated documentation files (the \"Software\"),\n * to deal in the Software without restriction, including without limitation\n * the rights to use, copy, modify, merge, publish, distribute, sublicense,\n * and/or sell copies of the Software, and to permit persons to whom the\n * Software is furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n * DEALINGS IN THE SOFTWARE.\n */\n\n#include <stdio.h>\n#include <netdb.h>\n\n#include \"sock_utils.h\"\n\n#include \"EchoRequest.h\"\n#include \"EchoIndication.h\"\n\nEchoRequestProxy *sRequestProxy;\nstatic sem_t sem_heard2;\n\nclass EchoIndication : public EchoIndicationWrapper\n{\npublic:\n    virtual void heard(uint32_t v) {\n        fprintf(stderr, \"heard an s: %d\\n\", v);\n\tsRequestProxy->say2(v, 2*v);\n    }\n    virtual void heard2(uint16_t a, uint16_t b) {\n        fprintf(stderr, \"heard an s2: %ld %ld\\n\", (long)a, (long)b);\n        sem_post(&sem_heard2);\n    }\n    EchoIndication(unsigned int id, PortalTransportFunctions *item, void *param) : EchoIndicationWrapper(id, item, param, &EchoIndicationJson_handleMessage, 1000) {}\n};\n\nstatic void call_say(int v)\n{\n    printf(\"[%s:%d] %d\\n\", __FUNCTION__, __LINE__, v);\n    sRequestProxy->say(v);\n    sem_wait(&sem_heard2);\n}\n\nstatic void call_say2(int v, int v2)\n{\n    sRequestProxy->say2(v, v2);\n    sem_wait(&sem_heard2);\n}\n\nint main(int argc, const char **argv)\n{\n    PortalSocketParam param = {0};\n//#define USE_UNIX_SOCKET\n#ifdef USE_UNIX_SOCKET\n#define PARAM NULL\n#else\n#define PARAM &param\n#endif\n\n    int rc = getaddrinfo(\"127.0.0.1\", \"5000\", NULL, &param.addr);\n    EchoIndication *sIndication = new EchoIndication(IfcNames_EchoIndicationH2S, &transportSocketInit, PARAM);\n    rc = getaddrinfo(\"127.0.0.1\", \"5001\", NULL, &param.addr);\n    sRequestProxy = new EchoRequestProxy(IfcNames_EchoRequestS2H, &transportSocketInit, PARAM, &EchoRequestJsonProxyReq, 1000);\n\n    int v = 42;\n    fprintf(stderr, \"Saying %d\\n\", v);\n    call_say(v);\n    call_say(v*5);\n    call_say(v*17);\n    call_say(v*93);\n    call_say2(v, v*3);\n    printf(\"TEST TYPE: SEM\\n\");\n    sRequestProxy->setLeds(9);\n    return 0;\n}\n"
  },
  {
    "path": "examples/echojsonpy/Echo.bsv",
    "content": "\n// Copyright (c) 2013 Nokia, Inc.\n// Copyright (c) 2013 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\nimport FIFO::*;\nimport Vector::*;\n\ninterface EchoIndication;\n    method Action heard(Bit#(32) x);\n    method Action heard2(Bit#(16) x, Bit#(16) y);\nendinterface\n\ninterface EchoRequest;\n   method Action say(Bit#(32) x);\n   method Action say2(Bit#(16) x, Bit#(16) y);\n   method Action setLeds(Bit#(8)x);\nendinterface\n\ninterface Echo;\n   interface EchoRequest request;\nendinterface\n\ntypedef struct {\n\tBit#(16) a;\n\tBit#(16) b;\n} EchoPair deriving (Bits);\n\nmodule mkEcho#(EchoIndication indication)(Echo);\n\n    FIFO#(Bit#(32)) delay <- mkSizedFIFO(8);\n    FIFO#(EchoPair) delay2 <- mkSizedFIFO(8);\n\n    rule heard;\n        delay.deq;\n        indication.heard(delay.first);\n    endrule\n\n    rule heard2;\n        delay2.deq;\n        indication.heard2(delay2.first.b, delay2.first.a);\n    endrule\n   \n   interface EchoRequest request;\n      method Action say(Bit#(32) v);\n\t delay.enq(v);\n      endmethod\n      \n      method Action say2(Bit#(16) a, Bit#(16) b);\n\t delay2.enq(EchoPair { a: a, b: b});\n      endmethod\n      \n      method Action setLeds(Bit#(8) v);\n      endmethod\n   endinterface\nendmodule\n"
  },
  {
    "path": "examples/echojsonpy/Makefile",
    "content": "CONNECTALDIR?=../..\nS2H_INTERFACES = EchoRequest:Echo.request SwallowRequest:Swallow.request\nH2S_INTERFACES = Echo:EchoIndication\n\nBSVFILES = Echo.bsv Swallow.bsv\nCPPFILES=daemon.cpp\n\ninclude $(CONNECTALDIR)/Makefile.connectal\n"
  },
  {
    "path": "examples/echojsonpy/Swallow.bsv",
    "content": "\n// Copyright (c) 2013 Nokia, Inc.\n// Copyright (c) 2013 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\ninterface SwallowRequest;\n   method Action swallow(Bit#(32) v);\nendinterface\n\ninterface Swallow;\n   interface SwallowRequest request;\nendinterface\nmodule mkSwallow(Swallow);\n\n   Reg#(Bit#(32)) sink <- mkReg(0);\n   \n   interface SwallowRequest request;\n   method Action swallow(Bit#(32) v);\n      sink <= v;\n   endmethod\n   endinterface\n\nendmodule\n"
  },
  {
    "path": "examples/echojsonpy/daemon.cpp",
    "content": "/* Copyright (c) 2014 Quanta Research Cambridge, Inc\n *\n * Permission is hereby granted, free of charge, to any person obtaining a\n * copy of this software and associated documentation files (the \"Software\"),\n * to deal in the Software without restriction, including without limitation\n * the rights to use, copy, modify, merge, publish, distribute, sublicense,\n * and/or sell copies of the Software, and to permit persons to whom the\n * Software is furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n * DEALINGS IN THE SOFTWARE.\n */\n\n#include <stdio.h>\n#include <netdb.h>\n#include <arpa/inet.h>\n\n#include \"sock_utils.h\"\n\n#include \"EchoRequest.h\"\n#include \"EchoIndication.h\"\n\nEchoIndicationProxy *sIndicationProxy;\nstatic int daemon_trace = 1;\n\nclass EchoRequest : public EchoRequestWrapper\n{\npublic:\n  void say ( const uint32_t v ) {\n    if (daemon_trace) fprintf(stderr, \"daemon say(%d)\\n\", v);\n    sIndicationProxy->heard(v);\n  }\n  void say2 ( const uint16_t a, const uint16_t b ) {\n    if (daemon_trace) fprintf(stderr, \"daemon say2(%d, %d)\\n\", a,b);\n    sIndicationProxy->heard2(a, b);\n  }\n  void setLeds ( const uint8_t v ) {\n    if (daemon_trace) fprintf(stderr, \"daemon setLeds(%d)\\n\", v);\n    sleep(1);\n    exit(1);\n  }\n  EchoRequest(unsigned int id, PortalTransportFunctions *item, void *param) : EchoRequestWrapper(id, item, param, &EchoRequestJson_handleMessage, 1000) {}\n};\n\nint main(int argc, const char **argv)\n{\n    PortalSocketParam param;\n\n    //talk to testecho.py\n    int rc = getaddrinfo(\"0.0.0.0\", \"5000\", NULL, &param.addr);\n    sIndicationProxy = new EchoIndicationProxy(IfcNames_EchoIndicationH2S, &transportSocketResp, &param, &EchoIndicationJsonProxyReq, 1000);\n    rc = getaddrinfo(\"0.0.0.0\", \"5001\", NULL, &param.addr);\n    EchoRequest *sRequest = new EchoRequest(IfcNames_EchoRequestS2H, &transportSocketResp, &param);\n\n    printf(\"[%s:%d] daemon sleeping...\\n\", __FUNCTION__, __LINE__);\n    while(1)\n        sleep(100);\n    return 0;\n}\n"
  },
  {
    "path": "examples/echojsonpy/old_testecho.py",
    "content": "#!/usr/bin/env python3\n\n# Copyright (c) 2013 Quanta Research Cambridge, Inc.\n\n# Permission is hereby granted, free of charge, to any person\n# obtaining a copy of this software and associated documentation\n# files (the \"Software\"), to deal in the Software without\n# restriction, including without limitation the rights to use, copy,\n# modify, merge, publish, distribute, sublicense, and/or sell copies\n# of the Software, and to permit persons to whom the Software is\n# furnished to do so, subject to the following conditions:\n\n# The above copyright notice and this permission notice shall be\n# included in all copies or substantial portions of the Software.\n\n# THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n# EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n# MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n# BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n# ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n# CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n# SOFTWARE.\n\nfrom __future__ import print_function\n\nimport sys\nimport socket\nimport struct\nimport time\nimport ctypes\nimport json\nimport math\n\nclass BaseClass(object):\n    def __init__(self, classtype):\n        self._type = classtype\n\nclass socket_client:\n    def __init__(self, devaddr, devport):\n        self.s = socket.socket(socket.AF_INET, socket.SOCK_STREAM)\n        self.s.connect((devaddr, devport))\n        self.llen = ctypes.sizeof(ctypes.c_int);\n    def recv_frame(self):\n        bytes_recd = 0\n        while bytes_recd < self.llen:\n            chunk = self.s.recv(self.llen)\n            bytes_recd = len(chunk)\n        liw = struct.unpack(\"hh\", chunk)[0]\n        blen = (liw-1)*self.llen\n        bytes_recd = 0\n        buffer = []\n        while bytes_recd < blen:\n            chunk = self.s.recv(blen)\n            bytes_recd += len(chunk) \n            buffer.append(chunk)\n        rv = buffer[0]\n        for b in buffer[1:]:\n            rv = rv + b\n        return rv\n    def send_frame(self, data):\n        liw = math.ceil(len(data)/4.0)\n        padding = ''.join([' ' for i in range(len(data), int(liw*4))])\n        print(\"send_frame (%d) %d %s\" % (len(data),liw, data))\n        self.s.send(struct.pack(\"@i\", (1+liw))+data+padding)\n    def shutdown(self):\n        self.s.shutdown(socket.SHUT_RDWR)\n        self.s.close()\n\ndef toascii(u):\n    return u.encode('ascii', 'replace')\n\ndef createSendMethod(methname):\n    def method(self, d):\n        d['name'] = methname\n        js = json.dumps(d, separators=(',',':'), sort_keys=True)\n        self.s.send_frame(js)\n    return (methname,method)\n\ndef createDefaultCallbackMethod(methname):\n    def method(self, d):\n        print(\"default %s(%s)\" %(methname, str(d)))\n    return (methname,method)\n\ndef createWrapperEvent(meths):\n    def method(self):\n        msg = self.s.recv_frame()\n        d = json.loads(msg)\n        n = d.pop('name')\n        getattr(self, n)(d)\n    return method\n\ndef ProxyClassFactory(name, meths, BaseClass=BaseClass):\n    def __init__(self, **kwargs):\n        for key, value in kwargs.items():\n            setattr(self, key, value)\n        BaseClass.__init__(self, name[:-len(\"Class\")])\n    newclass = type(toascii(name), (BaseClass,),dict([(\"__init__\",__init__)]+list(map(createSendMethod, meths))))\n    return newclass\n\ndef WrapperClassFactory(name, meths, BaseClass=BaseClass):\n    def __init__(self, **kwargs):\n        for key, value in kwargs.items():\n            setattr(self, key, value)\n        BaseClass.__init__(self, name[:-len(\"Class\")])\n    newclass = type(toascii(name), (BaseClass,),dict([(\"__init__\",__init__), (\"event\", createWrapperEvent(meths))]+list(map(createDefaultCallbackMethod, meths))))\n    return newclass\n\n\nif __name__ == \"__main__\":\n    ind_addr = \"127.0.0.1\"\n    ind_port = 5000\n    \n    req_addr = \"127.0.0.1\"\n    req_port = 5001\n    \n    ind_s = socket_client(ind_addr, ind_port)\n    req_s = socket_client(req_addr, req_port)\n    \n    json_data=open('./bluesim/generatedDesignInterfaceFile.json')\n    data = json.load(json_data)\n    json_data.close()\n    \n    proxy_classes = {}\n    wrapper_classes = {}\n    for ifc in data['interfaces']:\n        methods = [decl['name'] for decl in ifc['decls']]\n        proxy_classes[ifc['name']] = ProxyClassFactory(ifc['name'], methods)\n        wrapper_classes[ifc['name']] = WrapperClassFactory(ifc['name'], methods)\n        \n    ei = wrapper_classes['EchoIndication'](s=ind_s)\n    er = proxy_classes['EchoRequest'](s=req_s)\n    \n    def new_heard(d):\n        print(\"new heard(%s)\" %(str(d)))\n\n    er.say({'x':1})\n    ei.event()\n    er.say({'x':1})\n    setattr(ei,'heard', new_heard)\n    ei.event()\n    er.say2({'x':2,'y':1})\n    ei.event()\n    er.setLeds({'x':0})\n    time.sleep(1)\n    req_s.shutdown()\n    ind_s.shutdown()\n"
  },
  {
    "path": "examples/echojsonpy/testecho.py",
    "content": "#!/usr/bin/env python3\n\n# Copyright (c) 2013 Quanta Research Cambridge, Inc.\n\n# Permission is hereby granted, free of charge, to any person\n# obtaining a copy of this software and associated documentation\n# files (the \"Software\"), to deal in the Software without\n# restriction, including without limitation the rights to use, copy,\n# modify, merge, publish, distribute, sublicense, and/or sell copies\n# of the Software, and to permit persons to whom the Software is\n# furnished to do so, subject to the following conditions:\n\n# The above copyright notice and this permission notice shall be\n# included in all copies or substantial portions of the Software.\n\n# THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n# EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n# MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n# BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n# ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n# CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n# SOFTWARE.\n\nfrom __future__ import print_function\n\nimport time\nimport sys\nimport os\nimport argparse\n\nsys.path.append(os.path.abspath('../../scripts'))\nimport portalJson\n\nif __name__ == \"__main__\":\n\n    argparser = argparse.ArgumentParser('Display gyroscope data')\n    argparser.add_argument('-a', '--address', help='Device address', default=None)\n    options = argparser.parse_args()\n\n    print(options.address)\n    if not options.address:\n        options.address = os.environ['RUNPARAM']\n\n    ind_port = 5000\n    req_port = 5001\n    \n    ind_p = portalJson.portal(options.address, ind_port)\n    req_p = portalJson.portal(options.address, req_port)\n    \n    d = {'name':'say','x':1}\n    print(d)\n    req_p.send(d)\n    print(ind_p.recv())\n    d = {'name':'say','x':3}\n    print(d)\n    req_p.send(d)\n    print(ind_p.recv())\n    d = {'name':'say2','x':2,'y':1}\n    print(d)\n    req_p.send(d)\n    print(ind_p.recv())\n    d = {'name':'setLeds','x':0}\n    print(d)\n    req_p.send(d)\n    time.sleep(1)\n    req_p.shutdown()\n    ind_p.shutdown()\n"
  },
  {
    "path": "examples/echomux/Echo.bsv",
    "content": "\n// Copyright (c) 2013 Nokia, Inc.\n// Copyright (c) 2013 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\nimport FIFO::*;\nimport Vector::*;\n\ninterface EchoIndicationSW;\n    method Action heard(Bit#(32) v);\n    method Action heard2(Bit#(16) a, Bit#(16) b);\nendinterface\n\ninterface EchoRequestSW;\n   method Action say(Bit#(32) v);\n   method Action say2(Bit#(16) a, Bit#(16) b);\n   method Action setLeds(Bit#(8) v);\nendinterface\n\ninterface EchoIndication;\n    method Action heard(Bit#(32) id, Bit#(32) v);\n    method Action heard2(Bit#(32) id, Bit#(16) a, Bit#(16) b);\nendinterface\n\ninterface EchoRequest;\n   method Action say(Bit#(32) id, Bit#(32) v);\n   method Action say2(Bit#(32) id, Bit#(16) a, Bit#(16) b);\n   method Action setLeds(Bit#(32) id, Bit#(8) v);\nendinterface\n\ninterface Echo;\n   interface EchoRequest request;\nendinterface\n\ntypedef struct {\n\tBit#(32) id;\n\tBit#(32) v;\n} EchoPair1 deriving (Bits);\n\ntypedef struct {\n\tBit#(32) id;\n\tBit#(16) a;\n\tBit#(16) b;\n} EchoPair2 deriving (Bits);\n\nmodule mkEcho#(EchoIndication indication)(Echo);\n\n    FIFO#(EchoPair1) delay1 <- mkSizedFIFO(8);\n    FIFO#(EchoPair2) delay2 <- mkSizedFIFO(8);\n\n    rule heard;\n        delay1.deq;\n        indication.heard(delay1.first.id, delay1.first.v);\n    endrule\n\n    rule heard2;\n        delay2.deq;\n        indication.heard2(delay2.first.id, delay2.first.b, delay2.first.a);\n    endrule\n   \n   interface EchoRequest request;\n      method Action say(Bit#(32) id, Bit#(32) v);\n\t delay1.enq(EchoPair1 { id: id, v: v});\n      endmethod\n      \n      method Action say2(Bit#(32) id, Bit#(16) a, Bit#(16) b);\n\t delay2.enq(EchoPair2 { id: id, a: a, b: b});\n      endmethod\n      \n      method Action setLeds(Bit#(32) id, Bit#(8) v);\n      endmethod\n   endinterface\nendmodule\n"
  },
  {
    "path": "examples/echomux/Makefile",
    "content": "CONNECTALDIR?=../..\nINTERFACES = EchoRequestSW EchoIndicationSW SecondRequest SecondIndication ThirdRequest ThirdIndication\nS2H_INTERFACES = EchoRequest:Echo.request\nH2S_INTERFACES = Echo:EchoIndication\n\nBSVFILES = Echo.bsv Services.bsv\nCPPFILES=testecho.cpp\nCPPFILES2=daemon.cpp\nAUTOTOP = --portname IfcNames_SecondRequest --portname IfcNames_SecondIndication --portname IfcNames_ThirdRequest --portname IfcNames_ThirdIndication\n\ninclude $(CONNECTALDIR)/Makefile.connectal\n"
  },
  {
    "path": "examples/echomux/Services.bsv",
    "content": "// Copyright (c) 2014 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\ninterface EchoIndicationSW;\n    method Action heard(Bit#(32) v);\n    method Action heard2(Bit#(16) a, Bit#(16) b);\nendinterface\n\ninterface EchoRequestSW;\n   method Action say(Bit#(32) v);\n   method Action say2(Bit#(16) a, Bit#(16) b);\n   method Action setLeds(Bit#(8) v);\nendinterface\n\ninterface SecondRequest;\n    method Action say(Bit#(32) v, Bit#(64) a, Bit#(32)b);\nendinterface\n\ninterface SecondIndication;\n    method Action heard(Bit#(32) v, Bit#(32) a);\nendinterface\n\ninterface ThirdRequest;\n    method Action say();\nendinterface\n\ninterface ThirdIndication;\n    method Action heard();\nendinterface\n"
  },
  {
    "path": "examples/echomux/daemon.cpp",
    "content": "/* Copyright (c) 2014 Quanta Research Cambridge, Inc\n *\n * Permission is hereby granted, free of charge, to any person obtaining a\n * copy of this software and associated documentation files (the \"Software\"),\n * to deal in the Software without restriction, including without limitation\n * the rights to use, copy, modify, merge, publish, distribute, sublicense,\n * and/or sell copies of the Software, and to permit persons to whom the\n * Software is furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n * DEALINGS IN THE SOFTWARE.\n */\n\n#include <stdio.h>\n#include <netdb.h>\n\n#include \"sock_utils.h\"\n\n#include \"EchoRequest.h\"\n#include \"EchoIndication.h\"\n#include \"EchoRequestSW.h\"\n#include \"EchoIndicationSW.h\"\n#include \"SecondRequest.h\"\n#include \"SecondIndication.h\"\n#include \"ThirdRequest.h\"\n#include \"ThirdIndication.h\"\n\n\nEchoIndicationSWProxy *sIndicationProxy;\nEchoRequestProxy *echoRequestProxy;\nstatic int daemon_trace = 1;\n\nclass EchoIndication : public EchoIndicationWrapper\n{\npublic:\n    void heard(uint32_t id, uint32_t v) {\n        if (daemon_trace)\n        fprintf(stderr, \"daemon: heard an echo: id %d %d\\n\", id, v);\n        this->pint.request_index = id;\n        sIndicationProxy->heard(v);\n    }\n    void heard2(uint32_t id, uint16_t a, uint16_t b) {\n        if (daemon_trace)\n        fprintf(stderr, \"daemon: heard an echo2: id %d %d %d\\n\", id, a, b);\n        this->pint.request_index = id;\n        sIndicationProxy->heard2(a, b);\n    }\n    EchoIndication(unsigned int id, PortalTransportFunctions *item, void *param) : EchoIndicationWrapper(id, item, param) {}\n};\n\nclass EchoRequest : public EchoRequestSWWrapper\n{\npublic:\n    void say ( const uint32_t v ) {\n        if (daemon_trace)\n        fprintf(stderr, \"daemon[%s] id %d %d\\n\", __FUNCTION__, this->pint.indication_index, v);\n        echoRequestProxy->say(this->pint.indication_index, v);\n    }\n    void say2 ( const uint16_t a, const uint16_t b ) {\n        if (daemon_trace)\n        fprintf(stderr, \"daemon[%s] id %d %d %d\\n\", __FUNCTION__, this->pint.indication_index, a, b);\n        echoRequestProxy->say2(this->pint.indication_index, a, b);\n    }\n    void setLeds ( const uint8_t v ) {\n        fprintf(stderr, \"daemon[%s] id %d %d\\n\", __FUNCTION__, this->pint.indication_index, v);\n        echoRequestProxy->setLeds(this->pint.indication_index, v);\n    }\n    void disconnect(void) {\n        fprintf(stderr, \"daemon[%s] id %d\\n\", __FUNCTION__, this->pint.indication_index);\n        sleep(1);\n        exit(1);\n    }\n    EchoRequest(unsigned int id, PortalTransportFunctions *item, void *param) : EchoRequestSWWrapper(id, item, param) {}\n};\n\nSecondIndicationProxy *sSecondIndicationProxy;\nclass SecondRequest : public SecondRequestWrapper\n{\npublic:\n    void say(uint32_t v, uint64_t a, uint32_t b) {\n        if (daemon_trace)\n        fprintf(stderr, \"daemonSecond[%s] %d %lld %d\\n\", __FUNCTION__, v, (long long)a, b);\n        sSecondIndicationProxy->pint.request_index = this->pint.indication_index;\n        sSecondIndicationProxy->heard(v*4, a*2);\n    }\n    SecondRequest(unsigned int id, PortalTransportFunctions *item, void *param) : SecondRequestWrapper(id, item, param) {}\n};\n\nThirdIndicationProxy *sThirdIndicationProxy;\nclass ThirdRequest : public ThirdRequestWrapper\n{\npublic:\n    void say ( ) {\n        if (daemon_trace)\n        fprintf(stderr, \"daemonThird[%s]\\n\", __FUNCTION__);\n        sThirdIndicationProxy->pint.request_index = this->pint.indication_index;\n        sThirdIndicationProxy->heard();\n    }\n    ThirdRequest(unsigned int id, PortalTransportFunctions *item, void *param) : ThirdRequestWrapper(id, item, param) {}\n};\n\nint main(int argc, const char **argv)\n{\n    PortalSocketParam paramSocket = {};\n    PortalMuxParam param = {};\n\n    EchoIndication echoIndication(IfcNames_EchoIndicationH2S, NULL, NULL);\n    echoRequestProxy = new EchoRequestProxy(IfcNames_EchoRequestS2H);\n\n    Portal *mcommon = new Portal(0, 0, sizeof(uint32_t), portal_mux_handler, NULL, &transportSocketResp, &paramSocket, 0);\n    param.pint = &mcommon->pint;\n    sIndicationProxy = new EchoIndicationSWProxy(IfcNames_EchoIndicationH2S, &transportMux, &param);\n    EchoRequest sRequest(IfcNames_EchoRequestS2H, &transportMux, &param);\n\n    sSecondIndicationProxy = new SecondIndicationProxy(IfcNames_SecondIndication, &transportMux, &param);\n    SecondRequest sSecondRequest(IfcNames_SecondRequest, &transportMux, &param);\n\n    sThirdIndicationProxy = new ThirdIndicationProxy(IfcNames_ThirdIndication, &transportMux, &param);\n    ThirdRequest sThirdRequest(IfcNames_ThirdRequest, &transportMux, &param);\n\n    printf(\"[%s:%d] daemon sleeping...\\n\", __FUNCTION__, __LINE__);\n    while(1)\n        sleep(100);\n    return 0;\n}\n"
  },
  {
    "path": "examples/echomux/testecho.cpp",
    "content": "/* Copyright (c) 2014 Quanta Research Cambridge, Inc\n *\n * Permission is hereby granted, free of charge, to any person obtaining a\n * copy of this software and associated documentation files (the \"Software\"),\n * to deal in the Software without restriction, including without limitation\n * the rights to use, copy, modify, merge, publish, distribute, sublicense,\n * and/or sell copies of the Software, and to permit persons to whom the\n * Software is furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n * DEALINGS IN THE SOFTWARE.\n */\n\n#include <stdio.h>\n#include <netdb.h>\n\n#include \"sock_utils.h\"\n\n#include \"EchoRequestSW.h\"\n#include \"EchoIndicationSW.h\"\n#include \"SecondRequest.h\"\n#include \"SecondIndication.h\"\n#include \"ThirdRequest.h\"\n#include \"ThirdIndication.h\"\n\nstatic sem_t semEcho;\nEchoRequestSWProxy *sEcho;\n\nclass EchoIndication : public EchoIndicationSWWrapper\n{\npublic:\n    virtual void heard(uint32_t v) {\n        fprintf(stderr, \"heard an s: %d\\n\", v);\n\tsEcho->say2(v, 2*v);\n    }\n    virtual void heard2(uint16_t a, uint16_t b) {\n        sem_post(&semEcho);\n        //fprintf(stderr, \"heard an s2: %ld %ld\\n\", a, b);\n    }\n    EchoIndication(unsigned int id, PortalTransportFunctions *item, void *param) : EchoIndicationSWWrapper(id, item, param) {}\n};\n\nstatic void call_say(int v)\n{\n    printf(\"[%s:%d] %d\\n\", __FUNCTION__, __LINE__, v);\n    sEcho->say(v);\n    sem_wait(&semEcho);\n}\n\nstatic void call_say2(int v, int v2)\n{\n    sEcho->say2(v, v2);\n    sem_wait(&semEcho);\n}\n\n//static sem_t semSecond;\nSecondRequestProxy *sSecond;\n\nclass SecondIndication : public SecondIndicationWrapper\n{\npublic:\n    virtual void heard(uint32_t v, uint32_t a) {\n        fprintf(stderr, \"Secondheard an s: %d %d\\n\", v, a);\n    }\n    SecondIndication(unsigned int id, PortalTransportFunctions *item, void *param) : SecondIndicationWrapper(id, item, param) {}\n};\n\n//static sem_t semThird;\nThirdRequestProxy *sThird;\n\nclass ThirdIndication : public ThirdIndicationWrapper\n{\npublic:\n    virtual void heard() {\n        fprintf(stderr, \"Thirdheard\\n\");\n    }\n    ThirdIndication(unsigned int id, PortalTransportFunctions *item, void *param) : ThirdIndicationWrapper(id, item, param) {}\n};\n\nint main(int argc, const char **argv)\n{\n    PortalSocketParam paramSocket = {};\n    PortalMuxParam param = {};\n\n    Portal *mcommon = new Portal(0, 0, sizeof(uint32_t), portal_mux_handler, NULL, &transportSocketInit, &paramSocket, 0);\n    param.pint = &mcommon->pint;\n    EchoIndication sIndication(IfcNames_EchoIndicationH2S, &transportMux, &param);\n    sEcho = new EchoRequestSWProxy(IfcNames_EchoRequestS2H, &transportMux, &param);\n    SecondIndication sSecondIndication(IfcNames_SecondIndication, &transportMux, &param);\n    sSecond = new SecondRequestProxy(IfcNames_SecondRequest, &transportMux, &param);\n    ThirdIndication sThirdIndication(IfcNames_ThirdIndication, &transportMux, &param);\n    sThird = new ThirdRequestProxy(IfcNames_ThirdRequest, &transportMux, &param);\n\n    int v = 42;\n    fprintf(stderr, \"Saying %d\\n\", v);\n    call_say(v);\nsSecond->say(v*99, v * 1000000000L, v*55);\n    call_say(v*5);\nsThird->say();\n    call_say(v*17);\n    call_say(v*93);\n    call_say2(v, v*3);\n    printf(\"TEST TYPE: SEM\\n\");\n    sEcho->setLeds(9);\n    return 0;\n}\n"
  },
  {
    "path": "examples/echoproto/Echo.bsv",
    "content": "// Copyright (c) 2013 Nokia, Inc.\n// Copyright (c) 2013 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\nimport FIFO::*;\nimport Vector::*;\nimport EchoRequest::*;\nimport EchoIndication::*;\nimport GeneratedTypes::*;\n\ninterface Echo;\n   interface EchoRequest request;\nendinterface\n\nmodule mkEcho#(EchoIndication indication)(Echo);\n    FIFO#(EchoHeard) delay <- mkSizedFIFO(8);\n    FIFO#(EchoHeard2) delay2 <- mkSizedFIFO(8);\n\n    rule heard;\n        delay.deq;\n        indication.heard(delay.first);\n    endrule\n\n    rule heard2;\n        delay2.deq;\n        indication.heard2(delay2.first);\n    endrule\n   \n   interface EchoRequest request;\n      method Action say(EchoSay v);\n\t delay.enq(EchoHeard{v: v.v});\n      endmethod\n      \n      method Action say2(EchoSay2 v);\n\t delay2.enq(EchoHeard2{ a: v.a, b: v.b});\n      endmethod\n      \n      method Action setLeds(EchoLeds v);\n      endmethod\n   endinterface\nendmodule\n"
  },
  {
    "path": "examples/echoproto/Makefile",
    "content": "CONNECTALDIR?=../..\nS2H_INTERFACES = EchoRequest:Echo.request\nH2S_INTERFACES = Echo:EchoIndication\n\nCPPFILES=testecho.cpp\n#CONNECTALFLAGS += --protobuf interface.json\nCONNECTALFLAGS += --protobuf echo_pb.json\n\ninclude $(CONNECTALDIR)/Makefile.connectal\n\nprebuild::\n\t$(CONNECTALDIR)/../protobuf/src/protoc --cpp_out=. --bsv_out=. echo.proto\n"
  },
  {
    "path": "examples/echoproto/echo.proto",
    "content": "syntax = \"proto2\";\npackage echo;\n\nmessage EchoSay {\n  required fixed32 v = 1;\n}\nmessage EchoSay2 {\n  required fixed32 a = 1;\n  required fixed32 b = 2;\n}\nmessage EchoLeds {\n  required fixed32 v = 1;\n}\nmessage EchoHeard {\n  required fixed32 v = 1;\n}\nmessage EchoHeard2 {\n  required fixed32 a = 1;\n  required fixed32 b = 2;\n}\n\nmessage Empty {\n}\n\nservice EchoRequest {\n  rpc say (EchoSay) returns (Empty);\n  rpc say2 (EchoSay2) returns (Empty);\n  rpc setLeds (EchoLeds) returns (Empty);\n}\nservice EchoIndication {\n  rpc heard (EchoHeard) returns (Empty);\n  rpc heard2 (EchoHeard2) returns (Empty);\n}\n"
  },
  {
    "path": "examples/echoproto/testecho.cpp",
    "content": "/* Copyright (c) 2014 Quanta Research Cambridge, Inc\n *\n * Permission is hereby granted, free of charge, to any person obtaining a\n * copy of this software and associated documentation files (the \"Software\"),\n * to deal in the Software without restriction, including without limitation\n * the rights to use, copy, modify, merge, publish, distribute, sublicense,\n * and/or sell copies of the Software, and to permit persons to whom the\n * Software is furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n * DEALINGS IN THE SOFTWARE.\n */\n\n#include <stdio.h>\n#include \"EchoIndication.h\"\n#include \"EchoRequest.h\"\n#include \"GeneratedTypes.h\"\n#include \"topEnum.h\"\n\nstatic EchoRequestProxy *echoRequestProxy = 0;\nstatic sem_t sem_heard2;\n\nclass EchoIndication : public EchoIndicationWrapper\n{\npublic:\n    virtual void heard(EchoHeard v) {\n        EchoSay2 tmp = {v.v, 2*v.v};\n        printf(\"heard an echo: %d\\n\", v.v);\n        echoRequestProxy->say2(tmp);\n    }\n    virtual void heard2(EchoHeard2 v) {\n        sem_post(&sem_heard2);\n        //printf(\"heard an echo2: %ld %ld\\n\", a, b);\n    }\n    EchoIndication(unsigned int id) : EchoIndicationWrapper(id) {}\n};\n\nstatic void call_say(fixed32 v)\n{\n    EchoSay tmp = {v};\n    printf(\"[%s:%d] %d\\n\", __FUNCTION__, __LINE__, v);\n    echoRequestProxy->say(tmp);\n    sem_wait(&sem_heard2);\n}\n\nstatic void call_say2(fixed32 v, fixed32 v2)\n{\n    EchoSay2 tmp = {v, v2};\n    echoRequestProxy->say2(tmp);\n    sem_wait(&sem_heard2);\n}\n\nint main(int argc, const char **argv)\n{\n    EchoIndication echoIndication(IfcNames_EchoIndicationH2S);\n    echoRequestProxy = new EchoRequestProxy(IfcNames_EchoRequestS2H);\n\n    int v = 42;\n    printf(\"Saying %d\\n\", v);\n    call_say(v);\n    call_say(v*5);\n    call_say(v*17);\n    call_say(v*93);\n    call_say2(v, v*3);\n    printf(\"TEST TYPE: SEM\\n\");\n    EchoLeds tmp = {9};\n    echoRequestProxy->setLeds(tmp);\n    return 0;\n}\n"
  },
  {
    "path": "examples/echopy/Echo.bsv",
    "content": "\n// Copyright (c) 2013 Nokia, Inc.\n// Copyright (c) 2013 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\nimport FIFO::*;\nimport Vector::*;\nimport EchoInterface::*;\n\ninterface Echo;\n   interface EchoRequest request;\nendinterface\n\ntypedef struct {\n\tBit#(16) a;\n\tBit#(16) b;\n} EchoPair deriving (Bits);\n\nmodule mkEcho#(EchoResponse indication)(Echo);\n\n    FIFO#(Bit#(32)) delay <- mkSizedFIFO(8);\n    FIFO#(EchoPair) delay2 <- mkSizedFIFO(8);\n\n    rule heard;\n        delay.deq;\n        indication.heard(delay.first);\n    endrule\n\n    rule heard2;\n        delay2.deq;\n        indication.heard2(delay2.first.b, delay2.first.a);\n    endrule\n   \n   interface EchoRequest request;\n      method Action say(Bit#(32) v);\n   $display(\"say %h\", v);\n\t delay.enq(v);\n      endmethod\n      \n      method Action say2(Bit#(16) a, Bit#(16) b);\n   $display(\"say2 %h %h\", a, b);\n\t delay2.enq(EchoPair { a: a, b: b});\n      endmethod\n   endinterface\nendmodule\n"
  },
  {
    "path": "examples/echopy/EchoInterface.bsv",
    "content": "// Copyright (c) 2016 Connectal Project\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\ninterface EchoResponse;\n    method Action heard(Bit#(32) v);\n    method Action heard2(Bit#(16) a, Bit#(16) b);\nendinterface\n\ninterface EchoRequest;\n   method Action say(Bit#(32) v);\n   method Action say2(Bit#(16) a, Bit#(16) b);\nendinterface\n"
  },
  {
    "path": "examples/echopy/Makefile",
    "content": "CONNECTALDIR?=../..\nS2H_INTERFACES = EchoRequest:Echo.request\nH2S_INTERFACES = Echo:EchoResponse\n\nBSVFILES = EchoInterface.bsv\nPYFILES  = testecho.py\n\nCONNECTALFLAGS += --run-args=\"$(PWD)/testecho.py $(CONNECTALDIR)/scripts/portal.py $(PWD)/$(BOARD)/bin/connectal.so\"\nCONNECTALFLAGS += -D PYTHONPATH=\"$(CONNECTALDIR)/scripts:.\" -D CONNECTALDIR=\"$(CONNECTALDIR)\"\n\nifeq ($(BOARD),zedboard_ubuntu)\nprebuild::\n\t./ubuntu-python-dev.sh\nendif\n\ninclude $(CONNECTALDIR)/Makefile.connectal\n"
  },
  {
    "path": "examples/echopy/testecho.py",
    "content": "#!/usr/bin/env python3\n# Copyright (c) 2014 Quanta Research Cambridge, Inc\n#\n# Permission is hereby granted, free of charge, to any person obtaining a\n# copy of this software and associated documentation files (the \"Software\"),\n# to deal in the Software without restriction, including without limitation\n# the rights to use, copy, modify, merge, publish, distribute, sublicense,\n# and/or sell copies of the Software, and to permit persons to whom the\n# Software is furnished to do so, subject to the following conditions:\n#\n# The above copyright notice and this permission notice shall be included\n# in all copies or substantial portions of the Software.\n#\n# THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n# OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n# DEALINGS IN THE SOFTWARE.\n#\n\nfrom __future__ import print_function\n\nimport ctypes, json, os, sys, threading, time, portal\n\nclass Echo:\n    def __init__(self):\n        self.proxy = portal.NativeProxy('EchoRequest', self, responseInterface='EchoResponse', rpc=True)\n        self.response = None\n\n    def call_say(self, a):\n        self.proxy.say(a)\n        print('say response:', self.response)\n\n    def call_say2(self, a, b):\n        self.proxy.say2(a, b)\n        print('say2 response:', self.response)\n\n    def heard(self, v):\n        print('heard called!!!', v)\n        self.response = v\n\n    def heard2(self, a, b):\n        print('heard2 called!!!', a, b)\n        self.response = (a,b)\n\necho = Echo()\n\nv = 42\nprint(\"Saying %d\" % v)\necho.call_say(v);\necho.call_say2(v, v*3);\necho.call_say(v*5);\necho.call_say(v*17);\necho.call_say(v*93);\necho.proxy.stopPolling = True\n"
  },
  {
    "path": "examples/echopy/ubuntu-python-dev.sh",
    "content": "#!/bin/sh\n\nfor path in p/python2.7/libpython2.7_2.7.11-7ubuntu1_armhf p/python2.7/libpython2.7-dev_2.7.11-7ubuntu1_armhf libj/libjsoncpp/libjsoncpp1_1.7.2-1_armhf libj/libjsoncpp/libjsoncpp-dev_1.7.2-1_armhf; do\n    pkg=`basename $path`\n    [ -f $pkg.deb ] || (\n\twget http://ports.ubuntu.com/ubuntu-ports/pool/main/$path.deb;\n\tar x $pkg.deb;\n\txzcat data.tar.xz | tar -xvf -\n    )\ndone\nsed -i \"s|#define _POSIX_C_SOURCE 200112L|/* _POSIX_C_SOURCE defined by features.h*/|\" usr/include/arm-linux-gnueabihf/python2.7/pyconfig.h\nsed -i \"s|#define _XOPEN_SOURCE 600|/* _XOPEN_SOURCE defined by features.h*/|\" usr/include/arm-linux-gnueabihf/python2.7/pyconfig.h\nrm -f data.tar.xz control.tar.gz debian-binary\n"
  },
  {
    "path": "examples/echoshared/Echo.bsv",
    "content": "\n// Copyright (c) 2013 Nokia, Inc.\n// Copyright (c) 2013 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\nimport FIFO::*;\nimport Vector::*;\n\ninterface EchoIndication;\n    method Action heard(Bit#(32) v);\n    method Action heard2(Bit#(16) a, Bit#(16) b);\nendinterface\n\ninterface EchoRequest;\n   method Action say(Bit#(32) v);\n   method Action say2(Bit#(16) a, Bit#(16) b);\n   method Action setLeds(Bit#(8) v);\nendinterface\n\ninterface Echo;\n   interface EchoRequest request;\nendinterface\n\ntypedef struct {\n\tBit#(16) a;\n\tBit#(16) b;\n} EchoPair deriving (Bits);\n\nmodule mkEcho#(EchoIndication indication)(Echo);\n\n    FIFO#(Bit#(32)) delay <- mkSizedFIFO(8);\n    FIFO#(EchoPair) delay2 <- mkSizedFIFO(8);\n\n    rule heard;\n        delay.deq;\n        indication.heard(delay.first);\n    endrule\n\n    rule heard2;\n        delay2.deq;\n        indication.heard2(delay2.first.b, delay2.first.a);\n    endrule\n   \n   interface EchoRequest request;\n      method Action say(Bit#(32) v);\n\t delay.enq(v);\n      endmethod\n      \n      method Action say2(Bit#(16) a, Bit#(16) b);\n\t delay2.enq(EchoPair { a: a, b: b});\n      endmethod\n      \n      method Action setLeds(Bit#(8) v);\n      endmethod\n   endinterface\nendmodule\n"
  },
  {
    "path": "examples/echoshared/Makefile",
    "content": "CONNECTALDIR?=../..\nS2H_INTERFACES = EchoRequest:Echo.request\nH2S_INTERFACES = Echo:EchoIndication\nINTERFACES = MMURequest MMUIndication MemServerRequest MemServerIndication\n\nBSVFILES = Echo.bsv $(CONNECTALDIR)/bsv/ConnectalMemory.bsv\nCPPFILES=testecho.cpp $(CONNECTALDIR)/cpp/transportShared.c $(CONNECTALDIR)/cpp/dmaManager.c\nCPPFILES2=daemon.cpp $(CONNECTALDIR)/cpp/transportShared.c $(CONNECTALDIR)/cpp/dmaManager.c\nAUTOTOP = --portname MMURequestS2H --portname MMUIndicationH2S\n\ninclude $(CONNECTALDIR)/Makefile.connectal\n"
  },
  {
    "path": "examples/echoshared/daemon.cpp",
    "content": "/* Copyright (c) 2014 Quanta Research Cambridge, Inc\n *\n * Permission is hereby granted, free of charge, to any person obtaining a\n * copy of this software and associated documentation files (the \"Software\"),\n * to deal in the Software without restriction, including without limitation\n * the rights to use, copy, modify, merge, publish, distribute, sublicense,\n * and/or sell copies of the Software, and to permit persons to whom the\n * Software is furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n * DEALINGS IN THE SOFTWARE.\n */\n\n#include <stdio.h>\n#include \"EchoRequest.h\"\n#include \"EchoIndication.h\"\n#include \"MMUServer.h\"\n\nstatic EchoRequestProxy *echoRequestProxy;\nstatic EchoIndicationProxy *sIndicationProxy;\nstatic int daemon_trace;// = 1;\n\nclass EchoIndication : public EchoIndicationWrapper\n{\npublic:\n    void heard(uint32_t v) {\n        if (daemon_trace)\n        fprintf(stderr, \"daemon: heard an echo: %d\\n\", v);\n        sIndicationProxy->heard(v);\n    }\n    void heard2(uint16_t a, uint16_t b) {\n        if (daemon_trace)\n        fprintf(stderr, \"daemon: heard an echo2: %d %d\\n\", a, b);\n        sIndicationProxy->heard2(a, b);\n    }\n    EchoIndication(unsigned int id, PortalTransportFunctions *item, void *param) : EchoIndicationWrapper(id, item, param) {}\n};\n\nclass EchoRequest : public EchoRequestWrapper\n{\npublic:\n    void say ( const uint32_t v ) {\n        if (daemon_trace)\n        fprintf(stderr, \"daemon[%s:%d]\\n\", __FUNCTION__, __LINE__);\n        echoRequestProxy->say(v);\n    }\n    void say2 ( const uint16_t a, const uint16_t b ) {\n        if (daemon_trace)\n        fprintf(stderr, \"daemon[%s:%d]\\n\", __FUNCTION__, __LINE__);\n        echoRequestProxy->say2(a, b);\n    }\n    void setLeds ( const uint8_t v ) {\n        fprintf(stderr, \"daemon[%s:%d]\\n\", __FUNCTION__, __LINE__);\n        echoRequestProxy->setLeds(v);\n        sleep(1);\n        exit(0);\n    }\n    EchoRequest(unsigned int id, PortalTransportFunctions *item, void *param) : EchoRequestWrapper(id, item, param) {}\n};\n\nstatic EchoRequest *sRequest;\n\nint main(int argc, const char **argv)\n{\n    EchoIndication echoIndication(IfcNames_EchoIndicationH2S, NULL, NULL);\n    echoRequestProxy = new EchoRequestProxy(IfcNames_EchoRequestS2H);\n    sRequest = new EchoRequest(IfcNames_EchoRequestS2H, &transportShared, NULL);\n    sIndicationProxy = new EchoIndicationProxy(IfcNames_EchoIndicationH2S, &transportShared, NULL);\n\n    MMUServer *mServer = new MMUServer(IfcNames_MMURequestS2H,\n        new MMUIndicationProxy(IfcNames_MMUIndicationH2S, &transportSocketResp, NULL), &transportSocketResp, NULL);\n    mServer->registerInterface(IfcNames_EchoRequestS2H, &sRequest->pint);\n    mServer->registerInterface(IfcNames_EchoIndicationH2S, &sIndicationProxy->pint);\n\n    printf(\"[%s:%d] daemon sleeping...\\n\", __FUNCTION__, __LINE__);\n    while(1)\n        sleep(100);\n    return 0;\n}\n"
  },
  {
    "path": "examples/echoshared/testecho.cpp",
    "content": "/* Copyright (c) 2014 Quanta Research Cambridge, Inc\n *\n * Permission is hereby granted, free of charge, to any person obtaining a\n * copy of this software and associated documentation files (the \"Software\"),\n * to deal in the Software without restriction, including without limitation\n * the rights to use, copy, modify, merge, publish, distribute, sublicense,\n * and/or sell copies of the Software, and to permit persons to whom the\n * Software is furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n * DEALINGS IN THE SOFTWARE.\n */\n#include \"EchoRequest.h\"\n#include \"EchoIndication.h\"\n#include \"dmaManager.h\"\n\n#define LOOP_COUNT 2\nEchoRequestProxy *sRequestProxy;\nstatic sem_t sem_heard2;\n\nclass EchoIndication : public EchoIndicationWrapper\n{\npublic:\n    virtual void heard(uint32_t v) {\n        fprintf(stderr, \"heard an s: %d\\n\", v);\n\tsRequestProxy->say2(v, 2*v);\n    }\n    virtual void heard2(uint16_t a, uint16_t b) {\n        sem_post(&sem_heard2);\n        //fprintf(stderr, \"heard an s2: %d %d\\n\", a, b);\n    }\n    EchoIndication(unsigned int id, PortalTransportFunctions *item, void *param) : EchoIndicationWrapper(id, item, param) {}\n};\n\nstatic void call_say(int v)\n{\n    printf(\"[%s:%d] %d\\n\", __FUNCTION__, __LINE__, v);\n    sRequestProxy->say(v);\n    sem_wait(&sem_heard2);\n}\n\nstatic void call_say2(int v, int v2)\n{\n    sRequestProxy->say2(v, v2);\n    sem_wait(&sem_heard2);\n}\n\nint main(int argc, const char **argv)\n{\n    int alloc_sz = 64-4;\n    DmaManager *dma = platformInit();\n\n    PortalSharedParam param = {{dma}, (uint32_t)alloc_sz};\n    EchoIndication sIndication(IfcNames_EchoIndicationH2S, &transportShared, &param);\n    sRequestProxy = new EchoRequestProxy(IfcNames_EchoRequestS2H, &transportShared, &param);\n\nfor (int i = 0; i < LOOP_COUNT; i++) {\n    int v = 42;\n    fprintf(stderr, \"Saying %d\\n\", v);\n    call_say(v);\n    call_say(v*5);\n    call_say(v*17);\n    call_say(v*93);\n    call_say2(v, v*3);\n}\n\n    sRequestProxy->setLeds(9);\n    sleep(2);\n    return 0;\n}\n"
  },
  {
    "path": "examples/echoslow/Echo.bsv",
    "content": "// Copyright (c) 2013 Nokia, Inc.\n// Copyright (c) 2013 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\nimport Clocks::*;\nimport FIFO::*;\nimport GetPut::*;\nimport Vector::*;\n\ninterface EchoIndication;\n    method Action heard(Bit#(32) v);\n    method Action heard2(Bit#(16) a, Bit#(16) b);\nendinterface\n\ninterface EchoRequest;\n   method Action say(Bit#(32) v);\n   method Action say2(Bit#(16) a, Bit#(16) b);\n   method Action setLeds(Bit#(8) v);\nendinterface\n\ninterface Echo;\n   interface EchoRequest request;\nendinterface\n\ntypedef struct {\n\tBit#(16) a;\n\tBit#(16) b;\n} EchoPair deriving (Bits);\n\nmodule mkEcho#(Clock derivedClock, Reset derivedReset, EchoIndication indication)(Echo);\n   let clock <- exposeCurrentClock;\n   let reset <- exposeCurrentReset;\n\n    let delay_toslow <- mkSyncFIFO(16, clock, reset, derivedClock);\n    let delay_fromslow <- mkSyncFIFO(16, derivedClock, derivedReset, clock);\n    let delay2_toslow <- mkSyncFIFO(16, clock, reset, derivedClock);\n    let delay2_fromslow <- mkSyncFIFO(16, derivedClock, derivedReset, clock);\n\n   rule heard_slow; // derivedClock domain\n      let v <- toGet(delay_toslow).get();\n      delay_fromslow.enq(v);\n   endrule\n   rule hear_fast;\n      let v <- toGet(delay_fromslow).get();\n      indication.heard(v);\n   endrule\n\n   rule heard2_slow; // derivedClock domain\n      let v <- toGet(delay2_toslow).get();\n      delay2_fromslow.enq(v);\n   endrule\n   rule heard2_fast;\n      let v <- toGet(delay2_fromslow).get();\n      indication.heard2(v.b, v.a);\n   endrule\n   \n   interface EchoRequest request;\n      method Action say(Bit#(32) v);\n\t delay_toslow.enq(v);\n      endmethod\n      \n      method Action say2(Bit#(16) a, Bit#(16) b);\n\t delay2_toslow.enq(EchoPair { a: a, b: b});\n      endmethod\n      \n      method Action setLeds(Bit#(8) v);\n      endmethod\n   endinterface\nendmodule\n"
  },
  {
    "path": "examples/echoslow/Makefile",
    "content": "CONNECTALDIR?=../..\nS2H_INTERFACES = EchoRequest:Echo.request\nH2S_INTERFACES = Echo:EchoIndication:host.derivedClock,host.derivedReset\n\nBSVFILES = Echo.bsv\nCPPFILES= ../echo/testecho.cpp\nCONNECTALFLAGS += -D IMPORT_HOST_CLOCKS\nCONNECTALFLAGS += --derivedclockperiod=125\n\ninclude $(CONNECTALDIR)/Makefile.connectal\n"
  },
  {
    "path": "examples/echosoft/Echo.bsv",
    "content": "\n// Copyright (c) 2013 Nokia, Inc.\n// Copyright (c) 2013 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\nimport FIFO::*;\nimport Vector::*;\n\ninterface EchoIndication;\n    method Action heard(Bit#(32) v);\n    method Action heard2(Bit#(16) a, Bit#(16) b);\nendinterface\n\ninterface EchoRequest;\n   method Action say(Bit#(32) v);\n   method Action say2(Bit#(16) a, Bit#(16) b);\n   method Action setLeds(Bit#(8) v);\nendinterface\n\ninterface Echo;\n   interface EchoRequest request;\nendinterface\n\ntypedef struct {\n\tBit#(16) a;\n\tBit#(16) b;\n} EchoPair deriving (Bits);\n\nmodule mkEcho#(EchoIndication indication)(Echo);\n\n    FIFO#(Bit#(32)) delay <- mkSizedFIFO(8);\n    FIFO#(EchoPair) delay2 <- mkSizedFIFO(8);\n\n    rule heard;\n        delay.deq;\n        indication.heard(delay.first);\n    endrule\n\n    rule heard2;\n        delay2.deq;\n        indication.heard2(delay2.first.b, delay2.first.a);\n    endrule\n   \n   interface EchoRequest request;\n      method Action say(Bit#(32) v);\n\t delay.enq(v);\n      endmethod\n      \n      method Action say2(Bit#(16) a, Bit#(16) b);\n\t delay2.enq(EchoPair { a: a, b: b});\n      endmethod\n      \n      method Action setLeds(Bit#(8) v);\n      endmethod\n   endinterface\nendmodule\n"
  },
  {
    "path": "examples/echosoft/Makefile",
    "content": "CONNECTALDIR?=../..\nS2H_INTERFACES = EchoRequest:Echo.request SwallowRequest:Swallow.request\nH2S_INTERFACES = Echo:EchoIndication\n\nBSVFILES = Echo.bsv Swallow.bsv\nCPPFILES=testecho.cpp\nCPPFILES2=daemon.cpp\n\ninclude $(CONNECTALDIR)/Makefile.connectal\n"
  },
  {
    "path": "examples/echosoft/Swallow.bsv",
    "content": "\n// Copyright (c) 2013 Nokia, Inc.\n// Copyright (c) 2013 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\ninterface SwallowRequest;\n   method Action swallow(Bit#(32) v);\nendinterface\n\ninterface Swallow;\n   interface SwallowRequest request;\nendinterface\nmodule mkSwallow(Swallow);\n\n   Reg#(Bit#(32)) sink <- mkReg(0);\n   \n   interface SwallowRequest request;\n   method Action swallow(Bit#(32) v);\n      sink <= v;\n   endmethod\n   endinterface\n\nendmodule\n"
  },
  {
    "path": "examples/echosoft/daemon.cpp",
    "content": "/* Copyright (c) 2014 Quanta Research Cambridge, Inc\n *\n * Permission is hereby granted, free of charge, to any person obtaining a\n * copy of this software and associated documentation files (the \"Software\"),\n * to deal in the Software without restriction, including without limitation\n * the rights to use, copy, modify, merge, publish, distribute, sublicense,\n * and/or sell copies of the Software, and to permit persons to whom the\n * Software is furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n * DEALINGS IN THE SOFTWARE.\n */\n#include <stdio.h>\n#include <netdb.h>\n#include \"sock_utils.h\"\n#include \"EchoRequest.h\"\n#include \"EchoIndication.h\"\n\nEchoRequestProxy *echoRequestProxy;\nEchoIndicationProxy *sIndicationProxy;\nstatic int daemon_trace;// = 1;\n\nclass EchoIndication : public EchoIndicationWrapper\n{\npublic:\n    void heard(uint32_t v) {\n        if (daemon_trace)\n        fprintf(stderr, \"daemon: heard an echo: %d\\n\", v);\n        sIndicationProxy->heard(v);\n    }\n    void heard2(uint16_t a, uint16_t b) {\n        if (daemon_trace)\n        fprintf(stderr, \"daemon: heard an echo2: %d %d\\n\", a, b);\n        sIndicationProxy->heard2(a, b);\n    }\n    EchoIndication(unsigned int id, PortalTransportFunctions *item, void *param) : EchoIndicationWrapper(id, item, param) {}\n};\n\nclass EchoRequest : public EchoRequestWrapper\n{\npublic:\n    void say ( const uint32_t v ) {\n        if (daemon_trace)\n        fprintf(stderr, \"daemon[%s:%d]\\n\", __FUNCTION__, __LINE__);\n        echoRequestProxy->say(v);\n    }\n    void say2 ( const uint16_t a, const uint16_t b ) {\n        if (daemon_trace)\n        fprintf(stderr, \"daemon[%s:%d]\\n\", __FUNCTION__, __LINE__);\n        echoRequestProxy->say2(a, b);\n    }\n    void setLeds ( const uint8_t v ) {\n        fprintf(stderr, \"daemon[%s:%d]\\n\", __FUNCTION__, __LINE__);\n        echoRequestProxy->setLeds(v);\n    }\n    void disconnect (void) {\n        fprintf(stderr, \"daemon[%s:%d]\\n\", __FUNCTION__, __LINE__);\n        sleep(1);\n        exit(1);\n    }\n    EchoRequest(unsigned int id, PortalTransportFunctions *item, void *param) : EchoRequestWrapper(id, item, param) {}\n};\n\nint main(int argc, const char **argv)\n{\n    PortalSocketParam param;\n//#define USE_UNIX_SOCKET\n#ifdef USE_UNIX_SOCKET\n#define PARAM NULL\n#else\n#define PARAM &param\n#endif\n\n    EchoIndication echoIndication(IfcNames_EchoIndicationH2S, NULL, NULL);\n    echoRequestProxy = new EchoRequestProxy(IfcNames_EchoRequestS2H);\n    getaddrinfo(\"127.0.0.1\", \"5000\", NULL, &param.addr);\n    sIndicationProxy = new EchoIndicationProxy(IfcNames_EchoIndicationH2S, &transportSocketResp, PARAM);\n    getaddrinfo(\"127.0.0.1\", \"5001\", NULL, &param.addr);\n    EchoRequest sRequest(IfcNames_EchoRequestS2H, &transportSocketResp, PARAM);\n\n    printf(\"[%s:%d] daemon sleeping...\\n\", __FUNCTION__, __LINE__);\n    while(1)\n        sleep(100);\n    return 0;\n}\n"
  },
  {
    "path": "examples/echosoft/testecho.cpp",
    "content": "/* Copyright (c) 2014 Quanta Research Cambridge, Inc\n *\n * Permission is hereby granted, free of charge, to any person obtaining a\n * copy of this software and associated documentation files (the \"Software\"),\n * to deal in the Software without restriction, including without limitation\n * the rights to use, copy, modify, merge, publish, distribute, sublicense,\n * and/or sell copies of the Software, and to permit persons to whom the\n * Software is furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n * DEALINGS IN THE SOFTWARE.\n */\n#include <stdio.h>\n#include <netdb.h>\n#include \"sock_utils.h\"\n#include \"EchoRequest.h\"\n#include \"EchoIndication.h\"\n\nEchoRequestProxy *sRequestProxy;\nstatic sem_t sem_heard2;\n\nclass EchoIndication : public EchoIndicationWrapper\n{\npublic:\n    void heard(uint32_t v) {\n        fprintf(stderr, \"heard an s: %d\\n\", v);\n        sRequestProxy->say2(v, 2*v);\n    }\n    void heard2(uint16_t a, uint16_t b) {\n        sem_post(&sem_heard2);\n        //fprintf(stderr, \"heard an s2: %ld %ld\\n\", a, b);\n    }\n    EchoIndication(unsigned int id, PortalTransportFunctions *item, void *param) : EchoIndicationWrapper(id, item, param) {}\n};\n\nstatic void call_say(int v)\n{\n    printf(\"[%s:%d] %d\\n\", __FUNCTION__, __LINE__, v);\n    sRequestProxy->say(v);\n    sem_wait(&sem_heard2);\n}\n\nstatic void call_say2(int v, int v2)\n{\n    sRequestProxy->say2(v, v2);\n    sem_wait(&sem_heard2);\n}\n\nint main(int argc, const char **argv)\n{\n    PortalSocketParam param = {0};\n//#define USE_UNIX_SOCKET\n#ifdef USE_UNIX_SOCKET\n#define PARAM NULL\n#else\n#define PARAM &param\n#endif\n\n    getaddrinfo(\"127.0.0.1\", \"5000\", NULL, &param.addr);\n    EchoIndication sIndication(IfcNames_EchoIndicationH2S, &transportSocketInit, PARAM);\n    getaddrinfo(\"127.0.0.1\", \"5001\", NULL, &param.addr);\n    sRequestProxy = new EchoRequestProxy(IfcNames_EchoRequestS2H, &transportSocketInit, PARAM);\n\n    int v = 42;\n    fprintf(stderr, \"Saying %d\\n\", v);\n    call_say(v);\n    call_say(v*5);\n    call_say(v*17);\n    call_say(v*93);\n    call_say2(v, v*3);\n    printf(\"TEST TYPE: SEM\\n\");\n    sRequestProxy->setLeds(9);\n    portal_disconnect(&sRequestProxy->pint);\n    portal_disconnect(&sIndication.pint);\n    sleep(10);\n    return 0;\n}\n"
  },
  {
    "path": "examples/echotrace/Echo.bsv",
    "content": "\n// Copyright (c) 2013 Nokia, Inc.\n// Copyright (c) 2013 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\nimport FIFO::*;\nimport Vector::*;\n\ninterface EchoIndication;\n    method Action heard(Bit#(32) v);\n    method Action heard2(Bit#(16) a, Bit#(16) b);\nendinterface\n\ninterface EchoRequest;\n   method Action say(Bit#(32) v);\n   method Action say2(Bit#(16) a, Bit#(16) b);\n   method Action setLeds(Bit#(8) v);\nendinterface\n\ninterface Echo;\n   interface EchoRequest request;\nendinterface\n\ntypedef struct {\n\tBit#(16) a;\n\tBit#(16) b;\n} EchoPair deriving (Bits);\n\nmodule mkEcho#(EchoIndication indication)(Echo);\n\n    FIFO#(Bit#(32)) delay <- mkSizedFIFO(8);\n    FIFO#(EchoPair) delay2 <- mkSizedFIFO(8);\n\n    rule heard;\n        delay.deq;\n        indication.heard(delay.first);\n    endrule\n\n    rule heard2;\n        delay2.deq;\n        indication.heard2(delay2.first.b, delay2.first.a);\n    endrule\n   \n   interface EchoRequest request;\n      method Action say(Bit#(32) v);\n\t delay.enq(v);\n      endmethod\n      \n      method Action say2(Bit#(16) a, Bit#(16) b);\n\t delay2.enq(EchoPair { a: a, b: b});\n      endmethod\n      \n      method Action setLeds(Bit#(8) v);\n      endmethod\n   endinterface\nendmodule\n"
  },
  {
    "path": "examples/echotrace/Makefile",
    "content": "CONNECTALDIR?=../..\nINTERFACES = MMURequest\nS2H_INTERFACES = EchoRequest:Echo.request\nH2S_INTERFACES = Echo:EchoIndication\n\nBSVFILES = Echo.bsv $(CONNECTALDIR)/bsv/ConnectalMemory.bsv\nCPPFILES=testecho.cpp $(CONNECTALDIR)/cpp/transportShared.c $(CONNECTALDIR)/cpp/dmaManager.c\n\ninclude $(CONNECTALDIR)/Makefile.connectal\n"
  },
  {
    "path": "examples/echotrace/testecho.cpp",
    "content": "/* Copyright (c) 2014 Quanta Research Cambridge, Inc\n *\n * Permission is hereby granted, free of charge, to any person obtaining a\n * copy of this software and associated documentation files (the \"Software\"),\n * to deal in the Software without restriction, including without limitation\n * the rights to use, copy, modify, merge, publish, distribute, sublicense,\n * and/or sell copies of the Software, and to permit persons to whom the\n * Software is furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n * DEALINGS IN THE SOFTWARE.\n */\n\n#include <stdio.h>\n#include \"dmaManager.h\"\n#include \"EchoIndication.h\"\n#include \"EchoRequest.h\"\n\nstatic EchoRequestProxy *echoRequestProxy, *echoRequestTrace;\nstatic sem_t sem_heard2;\n\nstatic void memdump(uint8_t *p, int len, const char *title)\n{\nint i;\n\n    i = 0;\n    while (len > 0) {\n        if (!(i & 0xf)) {\n            if (i > 0)\n                printf(\"\\n\");\n            printf(\"%s: \",title);\n        }\n        printf(\"%02x \", *p++);\n        i++;\n        len--;\n    }\n    printf(\"\\n\");\n}\n\nclass EchoIndication : public EchoIndicationWrapper\n{\npublic:\n    virtual void heard(uint32_t v) {\n        printf(\"heard an echo: %d\\n\", v);\n\techoRequestProxy->say2(v, 2*v);\n\techoRequestTrace->say2(v, 2*v);\n    }\n    virtual void heard2(uint16_t a, uint16_t b) {\n        sem_post(&sem_heard2);\n        //printf(\"heard an echo2: %ld %ld\\n\", a, b);\n    }\n    EchoIndication(unsigned int id) : EchoIndicationWrapper(id) {}\n};\n\nstatic void call_say(int v)\n{\n    printf(\"[%s:%d] %d\\n\", __FUNCTION__, __LINE__, v);\n    echoRequestProxy->say(v);\n    echoRequestTrace->say(v);\n    sem_wait(&sem_heard2);\n}\n\nstatic void call_say2(int v, int v2)\n{\n    echoRequestProxy->say2(v, v2);\n    echoRequestTrace->say2(v, v2);\n    sem_wait(&sem_heard2);\n}\n\nint main(int argc, const char **argv)\n{\n    EchoIndication echoIndication(IfcNames_EchoIndicationH2S);\n    echoRequestProxy = new EchoRequestProxy(IfcNames_EchoRequestS2H);\n    int alloc_sz = 1000;\n    PortalSharedParam param = {{NULL}, (uint32_t)alloc_sz};\n    echoRequestTrace = new EchoRequestProxy(IfcNames_EchoRequestS2H, &transportTrace, &param);\n\n    int v = 42;\n    printf(\"Saying %d\\n\", v);\n    call_say(v);\n    call_say(v*5);\n    call_say(v*17);\n    call_say(v*93);\n    call_say2(v, v*3);\n    printf(\"TEST TYPE: SEM\\n\");\n    echoRequestProxy->setLeds(9);\n    echoRequestTrace->setLeds(9);\n\n    volatile unsigned int *p = echoRequestTrace->pint.map_base;\n    printf(\"[%s] Dump trace buffer: limit %d write %d read %d start %d\\n\", __FUNCTION__,\n        p[SHARED_LIMIT], p[SHARED_WRITE], p[SHARED_READ], p[SHARED_START]);\n    uint32_t current = p[SHARED_WRITE];\n    while (current != p[SHARED_READ]) {\n        unsigned int hdr = p[current-1];\n        current -= (hdr & 0xffff);\n        printf (\"W[%3d] %08x\", current, hdr);\n        memdump((uint8_t *)&p[current], ((hdr & 0xffff)-1) * sizeof(uint32_t), \"\");\n    }\n    return 0;\n}\n"
  },
  {
    "path": "examples/echotrace/vc707_floorplan.xdc",
    "content": "startgroup\ncreate_pblock pblock_ep7\nresize_pblock pblock_ep7 -add {SLICE_X184Y54:SLICE_X221Y166 DSP48_X18Y22:DSP48_X19Y65 RAMB18_X12Y22:RAMB18_X14Y65 RAMB36_X12Y11:RAMB36_X14Y32}\nadd_cells_to_pblock pblock_ep7 [get_cells [list host_ep7]] -clear_locs\nset_property HD.PARTPIN_RANGE {SLICE_X185Y54:SLICE_X186Y166} [get_pins host_ep7/*]\nset_property CONTAIN_ROUTING true [get_pblocks pblock_ep7]\nendgroup\n\nstartgroup\ncreate_pblock pblock_pciehost\nresize_pblock pblock_pciehost -add {SLICE_X112Y55:SLICE_X173Y197 DSP48_X9Y22:DSP48_X16Y77 RAMB18_X7Y22:RAMB18_X10Y77 RAMB36_X7Y11:RAMB36_X10Y38}\nadd_cells_to_pblock pblock_pciehost [get_cells [list host_pciehost]] -clear_locs\nset_property HD.PARTPIN_RANGE {SLICE_X112Y55:SLICE_X113Y197} [get_pins host_pciehost/*]\nset_property HD.PARTPIN_RANGE {SLICE_X172Y55:SLICE_X173Y197} [get_pins host_pciehost/*pci_re*]\nset_property HD.PARTPIN_RANGE {SLICE_X172Y55:SLICE_X173Y197} [get_pins host_pciehost/*pci*]\nset_property CONTAIN_ROUTING true [get_pblocks pblock_pciehost]\nendgroup\n\n# startgroup\n# create_pblock pblock_pciehost\n# resize_pblock pblock_pciehost -add {SLICE_X112Y55:SLICE_X221Y197 DSP48_X9Y22:DSP48_X19Y77 RAMB18_X7Y22:RAMB18_X14Y77 RAMB36_X7Y11:RAMB36_X14Y38}\n# add_cells_to_pblock pblock_pciehost [get_cells [list host]] -clear_locs\n# set_property HD.PARTPIN_RANGE {SLICE_X112Y55:SLICE_X113Y197} [get_pins host/*]\n# endgroup\n\n"
  },
  {
    "path": "examples/echowebsocket/Echo.bsv",
    "content": "\n// Copyright (c) 2013 Nokia, Inc.\n// Copyright (c) 2013 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\nimport FIFO::*;\nimport Vector::*;\n\ninterface EchoIndication;\n    method Action heard(Bit#(32) v);\n    method Action heard2(Bit#(16) a, Bit#(16) b);\nendinterface\n\ninterface EchoRequest;\n   method Action say(Bit#(32) v);\n   method Action say2(Bit#(16) a, Bit#(16) b);\n   method Action setLeds(Bit#(8) v);\nendinterface\n\ninterface Echo;\n   interface EchoRequest request;\nendinterface\n\ntypedef struct {\n\tBit#(16) a;\n\tBit#(16) b;\n} EchoPair deriving (Bits);\n\nmodule mkEcho#(EchoIndication indication)(Echo);\n\n    FIFO#(Bit#(32)) delay <- mkSizedFIFO(8);\n    FIFO#(EchoPair) delay2 <- mkSizedFIFO(8);\n\n    rule heard;\n        delay.deq;\n        indication.heard(delay.first);\n    endrule\n\n    rule heard2;\n        delay2.deq;\n        indication.heard2(delay2.first.b, delay2.first.a);\n    endrule\n   \n   interface EchoRequest request;\n      method Action say(Bit#(32) v);\n\t delay.enq(v);\n      endmethod\n      \n      method Action say2(Bit#(16) a, Bit#(16) b);\n\t delay2.enq(EchoPair { a: a, b: b});\n      endmethod\n      \n      method Action setLeds(Bit#(8) v);\n      endmethod\n   endinterface\nendmodule\n"
  },
  {
    "path": "examples/echowebsocket/Makefile",
    "content": "CONNECTALDIR?=../..\nS2H_INTERFACES = EchoRequest:Echo.request SwallowRequest:Swallow.request\nH2S_INTERFACES = Echo:EchoIndication\n\nBSVFILES = Echo.bsv Swallow.bsv\nCPPFILES=testecho.cpp $(CONNECTALDIR)/cpp/portalWebSocket.c\nCPPFILES2=daemon.cpp $(CONNECTALDIR)/cpp/portalWebSocket.c\nCONNECTALFLAGS += -lwebsockets\n\ninclude $(CONNECTALDIR)/Makefile.connectal\n"
  },
  {
    "path": "examples/echowebsocket/Swallow.bsv",
    "content": "\n// Copyright (c) 2013 Nokia, Inc.\n// Copyright (c) 2013 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\ninterface SwallowRequest;\n   method Action swallow(Bit#(32) v);\nendinterface\n\ninterface Swallow;\n   interface SwallowRequest request;\nendinterface\nmodule mkSwallow(Swallow);\n\n   Reg#(Bit#(32)) sink <- mkReg(0);\n   \n   interface SwallowRequest request;\n   method Action swallow(Bit#(32) v);\n      sink <= v;\n   endmethod\n   endinterface\n\nendmodule\n"
  },
  {
    "path": "examples/echowebsocket/daemon.cpp",
    "content": "/* Copyright (c) 2014 Quanta Research Cambridge, Inc\n *\n * Permission is hereby granted, free of charge, to any person obtaining a\n * copy of this software and associated documentation files (the \"Software\"),\n * to deal in the Software without restriction, including without limitation\n * the rights to use, copy, modify, merge, publish, distribute, sublicense,\n * and/or sell copies of the Software, and to permit persons to whom the\n * Software is furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n * DEALINGS IN THE SOFTWARE.\n */\n\n#include <stdio.h>\n#include <netdb.h>\n\n#include \"sock_utils.h\"\n\n#include \"EchoRequest.h\"\n#include \"EchoIndication.h\"\n\nEchoRequestProxy *echoRequestProxy;\nEchoIndicationProxy *sIndicationProxy;\nstatic int daemon_trace ;//= 1;\n\nclass EchoIndication : public EchoIndicationWrapper\n{\npublic:\n    void heard(uint32_t v) {\n        if (daemon_trace)\n        fprintf(stderr, \"daemon: %p heard an echo: %d\\n\", sIndicationProxy, v);\n        sIndicationProxy->heard(v);\n    }\n    void heard2(uint16_t a, uint16_t b) {\n        if (daemon_trace)\n        fprintf(stderr, \"daemon: %p heard an echo2: %d %d\\n\", sIndicationProxy, a, b);\n        sIndicationProxy->heard2(a, b);\n    }\n    EchoIndication(unsigned int id, PortalTransportFunctions *item, void *param) : EchoIndicationWrapper(id, item, param) {}\n};\n\nclass EchoRequest : public EchoRequestWrapper\n{\npublic:\n    void say ( const uint32_t v ) {\n        if (daemon_trace)\n        fprintf(stderr, \"daemon[%s:%d] proxy %p\\n\", __FUNCTION__, __LINE__, echoRequestProxy);\n        echoRequestProxy->say(v);\n    }\n    void say2 ( const uint16_t a, const uint16_t b ) {\n        if (daemon_trace)\n        fprintf(stderr, \"daemon[%s:%d] proxy %p\\n\", __FUNCTION__, __LINE__, echoRequestProxy);\n        echoRequestProxy->say2(a, b);\n    }\n    void setLeds ( const uint8_t v ) {\n        fprintf(stderr, \"daemon[%s:%d] proxy %p\\n\", __FUNCTION__, __LINE__, echoRequestProxy);\n        echoRequestProxy->setLeds(v);\n        sleep(1);\n        exit(1);\n    }\n    EchoRequest(unsigned int id, PortalTransportFunctions *item, void *param) : EchoRequestWrapper(id, item, param, &EchoRequestJson_handleMessage, 1000) {}\n};\n\nint main(int argc, const char **argv)\n{\n    PortalSocketParam param;\n//#define USE_UNIX_SOCKET\n#ifdef USE_UNIX_SOCKET\n#define PARAM NULL\n#else\n#define PARAM &param\n#endif\n\n    EchoIndication *echoIndication = new EchoIndication(IfcNames_EchoIndicationH2S, NULL, NULL);\n    echoRequestProxy = new EchoRequestProxy(IfcNames_EchoRequestS2H);\n    int rc = getaddrinfo(\"127.0.0.1\", \"5000\", NULL, &param.addr);\n    sIndicationProxy = new EchoIndicationProxy(IfcNames_EchoIndicationH2S, &transportWebSocketResp, PARAM, &EchoIndicationJsonProxyReq, 1000);\n    rc = getaddrinfo(\"127.0.0.1\", \"5001\", NULL, &param.addr);\n    EchoRequest *sRequest = new EchoRequest(IfcNames_EchoRequestS2H, &transportWebSocketResp, PARAM);\n\n    printf(\"[%s:%d] daemon sleeping...\\n\", __FUNCTION__, __LINE__);\n    while(1)\n        sleep(100);\n    return 0;\n}\n"
  },
  {
    "path": "examples/echowebsocket/testecho.cpp",
    "content": "/* Copyright (c) 2014 Quanta Research Cambridge, Inc\n *\n * Permission is hereby granted, free of charge, to any person obtaining a\n * copy of this software and associated documentation files (the \"Software\"),\n * to deal in the Software without restriction, including without limitation\n * the rights to use, copy, modify, merge, publish, distribute, sublicense,\n * and/or sell copies of the Software, and to permit persons to whom the\n * Software is furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n * DEALINGS IN THE SOFTWARE.\n */\n\n#include <stdio.h>\n#include <netdb.h>\n\n#include \"sock_utils.h\"\n\n#include \"EchoRequest.h\"\n#include \"EchoIndication.h\"\n\nEchoRequestProxy *sRequestProxy;\nstatic sem_t sem_heard2;\n\nclass EchoIndication : public EchoIndicationWrapper\n{\npublic:\n    virtual void heard(uint32_t v) {\n        fprintf(stderr, \"heard an s: %d\\n\", v);\n\tsRequestProxy->say2(v, 2*v);\n    }\n    virtual void heard2(uint16_t a, uint16_t b) {\n        fprintf(stderr, \"heard an s2: %ld %ld\\n\", (long)a, (long)b);\n        sem_post(&sem_heard2);\n    }\n    EchoIndication(unsigned int id, PortalTransportFunctions *item, void *param) : EchoIndicationWrapper(id, item, param, &EchoIndicationJson_handleMessage, 1000) {}\n};\n\nstatic void call_say(int v)\n{\n    printf(\"[%s:%d] %d\\n\", __FUNCTION__, __LINE__, v);\n    sRequestProxy->say(v);\n    sem_wait(&sem_heard2);\n}\n\nstatic void call_say2(int v, int v2)\n{\n    sRequestProxy->say2(v, v2);\n    sem_wait(&sem_heard2);\n}\n\nint main(int argc, const char **argv)\n{\n    PortalSocketParam param = {0};\n//#define USE_UNIX_SOCKET\n#ifdef USE_UNIX_SOCKET\n#define PARAM NULL\n#else\n#define PARAM &param\n#endif\n\n    int rc = getaddrinfo(\"127.0.0.1\", \"5000\", NULL, &param.addr);\n    EchoIndication *sIndication = new EchoIndication(IfcNames_EchoIndicationH2S, &transportWebSocketInit, PARAM);\n    rc = getaddrinfo(\"127.0.0.1\", \"5001\", NULL, &param.addr);\n    sRequestProxy = new EchoRequestProxy(IfcNames_EchoRequestS2H, &transportWebSocketInit, PARAM, &EchoRequestJsonProxyReq, 1000);\n\n    int v = 42;\n    fprintf(stderr, \"Saying %d\\n\", v);\n    call_say(v);\n    call_say(v*5);\n    call_say(v*17);\n    call_say(v*93);\n    call_say2(v, v*3);\n    printf(\"TEST TYPE: SEM\\n\");\n    sRequestProxy->setLeds(9);\n    return 0;\n}\n"
  },
  {
    "path": "examples/fmcomms1/ExtraXilinxCells.bsv",
    "content": "// Copyright (c) 2014 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\n\ninterface DiffOut;\n   method Bit#(1) read_p();\n   method Bit#(1) read_n();\nendinterface \n\nimport \"BVI\" OBUFDS =\nmodule mkxOBUFDS#(Wire#(Bit#(1)) i)(DiffOut);\n  default_clock clk();\n  default_reset rstn();\n\n   port I = i;\n   method O    read_p();\n   method OB    read_n();\n\n   path(I, O);\n   path(I, OB);\n\n  schedule (read_p, read_n) CF (read_p, read_n);\n\nendmodule: mkxOBUFDS\n\n"
  },
  {
    "path": "examples/fmcomms1/ExtraXilinxCells.bsv.pp",
    "content": "// Copyright (c) 2014 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\n\ninterface DiffOut;\n   method Bit#(1) read_p();\n   method Bit#(1) read_n();\nendinterface \n\nimport \"BVI\" OBUFDS =\nmodule mkxOBUFDS#(Wire#(Bit#(1)) i)(DiffOut);\n  default_clock clk();\n  default_reset rstn();\n\n   port I = i;\n   method O    read_p();\n   method OB    read_n();\n\n   path(I, O);\n   path(I, OB);\n\n  schedule (read_p, read_n) CF (read_p, read_n);\n\nendmodule: mkxOBUFDS\n\n\n"
  },
  {
    "path": "examples/fmcomms1/FMComms1.bsv",
    "content": "// Copyright (c) 2013 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\nimport FIFO::*;\nimport FIFOF::*;\nimport Vector::*;\nimport ClientServer::*;\nimport GetPut::*;\nimport ConnectalMemTypes::*;\nimport MemReadEngine::*;\nimport MemWriteEngine::*;\nimport Pipe::*;\nimport Connectable::*;\n\ninterface FMComms1Request;\n   method Action startRead(Bit#(32) pointer, Bit#(32) numWords, Bit#(32) burstLen, Bit#(32) run);\n   method Action startWrite(Bit#(32) pointer, Bit#(32) numWords, Bit#(32) burstLen, Bit#(32) run);\n   method Action getReadStatus();\n   method Action getWriteStatus();\nendinterface\n\ninterface FMComms1;\n   interface FMComms1Request request;\n   interface MemReadClient#(64) readDmaClient;\n   interface MemWriteClient#(64) writeDmaClient;\nendinterface\n\ninterface FMComms1Indication;\n   method Action readStatus(Bit#(32) numIter, Bit#(32) running);\n   method Action writeStatus(Bit#(32) numIter, Bit#(32) running);\nendinterface\n\n/* This is like a combined memread and memwrite.  \n * The read side is set to repetitively read a buffer, until\n * another portal call is made to startRead with the run bit off.\n * \n * Writes are the same\n */\nmodule mkFMComms1#(FMComms1Indication indication, PipeIn#(Bit#(64)) dac, PipeOut#(Bit#(64)) adc) (FMComms1);\n\n   Reg#(SGLId)     readPointer <- mkReg(0);\n   Reg#(Bit#(32))         readNumWords <- mkReg(0);\n   Reg#(Bit#(32))         readIterCount <- mkReg(0);\n   Reg#(Bit#(BurstLenSize)) readBurstLen <- mkReg(0);\n   Reg#(Bit#(1))          readRun <- mkReg(0);\n\n   MemReadEngine#(64,64,1,1)         re <- mkMemReadEngineBuff(64*16);\n\n   Reg#(SGLId)     writePointer <- mkReg(0);\n   Reg#(Bit#(32))         writeNumWords <- mkReg(0);\n   Reg#(Bit#(32))         writeIterCount <- mkReg(0);\n   Reg#(Bit#(BurstLenSize)) writeBurstLen <- mkReg(0);\n   Reg#(Bit#(1))          writeRun <- mkReg(0);\n   \n   MemWriteEngine#(64,64,1,1)        we <- mkMemWriteEngineBuff(64*16);\n   \n   mkConnection(adc, we.writeServers[0].data);\n   rule readrule;\n      let v <- toGet(re.readServers[0].data).get;\n      toPut(dac).put(v.data);\n      if (v.last && readRun == 0)\n\t indication.readStatus(readIterCount, zeroExtend(readRun));\n   endrule\n   \n   rule readStart (readRun == 1);\n      readIterCount <= readIterCount + 1;\n      re.readServers[0].request.put(MemengineCmd{sglId:readPointer, base:0, len:readNumWords*4, burstLen:readBurstLen*4});\n   endrule\n   \n   rule writeStart (writeRun == 1);\n      writeIterCount <= writeIterCount + 1;\n      we.writeServers[0].request.put(MemengineCmd{sglId:writePointer, base:0, len:writeNumWords*4, burstLen:writeBurstLen*4});\n   endrule\n   \n   rule writeFinish;\n      let rv <- we.writeServers[0].done.get;\n      if (writeRun == 0)\n\t indication.writeStatus(writeIterCount, zeroExtend(writeRun));\n   endrule\n   \n   interface MemReadClient readDmaClient = re.dmaClient;\n   interface ObjectWeadClient writeDmaClient = we.dmaClient;\n   interface FMComms1Request request;\n      method Action startRead(Bit#(32) pointer, Bit#(32) numWords, Bit#(32) burstLen, Bit#(32) run);\n\t $display(\"startRead rdPointer=%d numWords=%h burstLen=%d run=%d\",\n\t    pointer, numWords, burstLen, run);\n\t if (run == 1) indication.readStatus(readIterCount, run);\n\t readPointer <= pointer;\n\t readNumWords  <= numWords;\n\t readBurstLen  <= truncate(burstLen);\n\t readRun <= truncate(run);\n      endmethod\n      method Action startWrite(Bit#(32) pointer, Bit#(32) numWords, Bit#(32) burstLen, Bit#(32) run);\n\t $display(\"startWrite rdPointer=%d numWords=%h burstLen=%d run=%d\",\n\t    pointer, numWords, burstLen, run);\n\t if (run == 1) indication.writeStatus(writeIterCount, run);\n\t writePointer <= pointer;\n\t writeNumWords  <= numWords;\n\t writeBurstLen  <= truncate(burstLen);\n\t writeRun <= truncate(run);\n      endmethod\n      method Action getReadStatus();\n\t indication.readStatus(readIterCount, zeroExtend(readRun));\n      endmethod\n      method Action getWriteStatus();\n\t indication.writeStatus(writeIterCount, zeroExtend(writeRun));\n      endmethod\n   endinterface\nendmodule\n"
  },
  {
    "path": "examples/fmcomms1/FMComms1ADC.bsv",
    "content": "// Copyright (c) 2014 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\nimport XilinxCells::*;\nimport ConnectalXilinxCells::*;\nimport Gearbox::*;\nimport Pipe::*;\nimport FIFO::*;\nimport BRAMFIFO::*;\nimport Vector::*;\nimport Clocks::*;\nimport DefaultValue::*;\n\n(* always_enabled *)\ninterface FMComms1ADCPins;\n   method Action io_adc_data_p(Bit#(14) v);\n   method Action io_adc_data_n(Bit#(14) v);\n   method Action io_adc_or_p(Bit#(1) v);\n   method Action io_adc_or_n(Bit#(1) v);\n   method Action io_adc_dco_p(Bit#(1) v);\n   method Action io_adc_dco_n(Bit#(1) v);\n   interface Clock deleteme_unused_clock;\n   interface Reset deleteme_unused_reset;\nendinterface\n\ntypedef struct {\n   Bit#(14) data_i;\n   Bit#(1) z_i;\n   Bit#(1) or_i;\n   Bit#(14) data_q;\n   Bit#(1) z_q;\n   Bit#(1) or_q;\n   } IQ deriving (Bits);\n\ninterface FMComms1ADC;\n   interface FMComms1ADCPins pins;\n   interface PipeOut#(Bit#(64)) adc;\nendinterface\n\n\n\n/* This module accepts inputs from an Analog Devices FMComms1\n * evaluation board Analog to Digital Converter, and delivers\n * the data as a PipeOut type on the default clock.\n * \n * Input is double data rate, with clock supplied by the FMComms1\n * Input data is 14 bits twos-complement or offset binary, plus\n * an overrange signa=\n * \n * Differential inputs are converted to single ended by using Xilinx IBUFDS\n * cells. The clock is converted to single ended by an IBUFGDS cell\n * \n * DDR data is convered to SDR using IDDR cells\n * At this point, the data is a 14 bit in-phase data signal, plus in-phase\n * overrange, and a 14 bit quadrature signal, plus overrange.\n * \n * The data is packed into a 64-bit IQ datatype, with overrange as the LSB\n * \n * The 32-bit data is converted to 64-bits by a Gearbox\n * \n * Clock conversion happens 64-bits wide using a SyncBRAMFIFO, which\n * presents a PipeOut channel to the rest of the logic.\n */\n\n\nmodule mkFMComms1ADC(FMComms1ADC);\n   \n   Clock def_clock <- exposeCurrentClock;\n   Reset def_reset <- exposeCurrentReset;\n   \n   function Bit#(1) foo(ReadOnly#(Bit#(1)) v);\n      return (v._read());\n   endfunction\n   \n\n   function ReadOnly#(Bit#(14)) rofromrov(Vector#(14, ReadOnly#(Bit#(1))) v);\n      return(interface ReadOnly;\n\t     method Bit#(14) _read;\n\t\treturn ( pack(map(foo, v)));\n\t     endmethod\n\t     endinterface\n\t     );\n   endfunction\n   \n   Clock adc_dco;     /* DDR clock */\n   Wire#(Bit#(1)) adc_dco_p <- mkDWire(0);\n   Wire#(Bit#(1)) adc_dco_n <- mkDWire(0);\n   adc_dco <- mkConnectalClockIBUFDS(adc_dco_p, adc_dco_n);\n   Reset adc_reset <- mkAsyncReset(3, def_reset, adc_dco);\n   \n   Vector#(14, Wire#(Bit#(1))) adc_data_p = newVector;\n   for (Integer i = 0; i < 14; i = i + 1)\n      adc_data_p[i] <- mkDWire(0, clocked_by adc_dco, reset_by adc_reset);\n\n   Vector#(14, Wire#(Bit#(1))) adc_data_n = newVector;\n   for (Integer i = 0; i < 14; i = i + 1)\n      adc_data_n[i] <- mkDWire(0, clocked_by adc_dco, reset_by adc_reset);\n\n   Wire#(Bit#(1)) adc_or_p <- mkDWire(0, clocked_by adc_dco, reset_by adc_reset);\n   Wire#(Bit#(1)) adc_or_n <- mkDWire(0, clocked_by adc_dco, reset_by adc_reset);\n\n   Vector#(14, ReadOnly#(Bit#(1))) v_adc_data;   /* data */\n   ReadOnly#(Bit#(14)) adc_data;\n\n   ReadOnly#(Bit#(1)) adc_or;      /* overrange */\n   \n   \n   for(Integer i = 0; i < 14; i = i + 1)\n      v_adc_data[i] <- mkIBUFDS(adc_data_p[i], adc_data_n[i], clocked_by adc_dco, reset_by adc_reset);   \n   adc_data = rofromrov(v_adc_data);\n   \n   adc_or <- mkIBUFDS(adc_or_p, adc_or_n, clocked_by adc_dco, reset_by adc_reset);\n   \n   IDDRParams#(Bit#(14)) iddrparams_data = defaultValue;\n//   iddrparams_data.ddr_clk_edge = \"SAME_EDGE_PIPELINED\";\n      iddrparams_data.ddr_clk_edge = \"SAME_EDGE\";\n   IDDR#(Bit#(14)) adc_sdr_data <- mkIDDR(iddrparams_data, clocked_by adc_dco);\n   \n   IDDRParams#(Bit#(1)) iddrparams_or = defaultValue;\n//   iddrparams_or.ddr_clk_edge = \"SAME_EDGE_PIPELINED\";\n   iddrparams_or.ddr_clk_edge = \"SAME_EDGE\";\n   IDDR#(Bit#(1)) adc_sdr_or <- mkIDDR(iddrparams_or, clocked_by adc_dco);\n   \n   rule sendup_adc_data;\n      adc_sdr_data.d(pack(adc_data));\n   endrule\n   \n   rule sendup_adc_or;\n      adc_sdr_or.d(adc_or);\n   endrule\n   \n   rule alwaysenable;\n      adc_sdr_data.ce(True);\n      adc_sdr_data.s(False);\n      adc_sdr_or.ce(True);\n      adc_sdr_or.s(False);\n   endrule\n   \n   Gearbox#(1, 2, IQ) gb <- mk1toNGearbox(adc_dco, adc_reset, adc_dco, adc_reset);\n   SyncFIFOIfc#(Vector#(2, IQ)) infifo <- mkSyncBRAMFIFO(128, adc_dco, adc_reset, def_clock, def_reset);\n   \n   rule sendup_gb_data;\n      gb.enq(unpack(pack(IQ{data_i: adc_sdr_data.q1, z_i: 0, or_i: adc_sdr_or.q1,\n\t data_q: adc_sdr_data.q2, z_q: 0, or_q: adc_sdr_or.q2})));\n   endrule\n\n   rule sendup_adc_fifo_data;\n      gb.deq();\n      infifo.enq(gb.first());\n   endrule\n   \n   interface FMComms1ADCPins pins;\n      \n      method Action io_adc_data_p(Bit#(14) v);\n         for (Integer i = 0; i < 14; i = i + 1)\n\t    adc_data_p[i] <= v[i];\n      endmethod\n      \n      method Action io_adc_data_n(Bit#(14) v);\n         for (Integer i = 0; i < 14; i = i + 1)\n\t    adc_data_n[i] <= v[i];\n      endmethod\n      \n      method Action io_adc_or_p(Bit#(1) v);\n\t adc_or_p <= v;\n      endmethod\n      \n      method Action io_adc_or_n(Bit#(1) v);\n\t adc_or_n <= v;\n      endmethod\n      method Action io_adc_dco_p(Bit#(1) v);\n\t adc_dco_p <= v;\n      endmethod\n      \n      method Action io_adc_dco_n(Bit#(1) v);\n\t adc_dco_n <= v;\n      endmethod\n      interface deleteme_unused_clock = adc_dco;\n      interface deleteme_unused_reset = adc_reset;\n\n   endinterface\n   \n   interface PipeOut adc;\n   \n      method Bit#(64) first();\n\t return(unpack(pack(infifo.first)));\n      endmethod\n      \n      method Action deq() = infifo.deq;\n   \n      method Bool notEmpty() = infifo.notEmpty;\n      \n   endinterface\n\n\nendmodule"
  },
  {
    "path": "examples/fmcomms1/FMComms1DAC.bsv",
    "content": "// Copyright (c) 2014 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\nimport XilinxCells::*;\nimport ConnectalXilinxCells::*;\nimport ConnectalClocks::*;\nimport Gearbox::*;\nimport Pipe::*;\nimport FIFO::*;\nimport BRAMFIFO::*;\nimport Vector::*;\nimport Clocks::*;\nimport DefaultValue::*;\n\n\nimport ExtraXilinxCells::*;\n\n(* always_enabled *)\ninterface FMComms1DACPins;\n   method Bit#(14) io_dac_data_p();\n   method Bit#(14) io_dac_data_n();\n   method Action io_dac_dco_p(Bit#(1) v);\n   method Action io_dac_dco_n(Bit#(1) v);\n   method Bit#(1) io_dac_dci_p();\n   method Bit#(1) io_dac_dci_n();\n   method Clock deleteme_unused_clock;\n   method Reset deleteme_unused_reset;\nendinterface\n\ntypedef struct {\n   Bit#(16) data_i;\n   Bit#(16) data_q;\n   } OIQ deriving (Bits);\n\ninterface FMComms1DAC;\n   interface FMComms1DACPins pins;\n   interface PipeIn#(Bit#(64)) dac;\nendinterface\n\n/* This module drives an Analog Devices FMComms1\n * evaluation board Digital to Analog Converter, it accepts\n * the data as a PipeIn type on the default clock.\n * The FMComms1 supplies the DAC clock as a differential pair\n * \n * Output is double data rate, with clock supplied by the FMComms1\n * Output data is 14 bits twos-complement or offset binary\n * \n * Differential outputs are converted from single ended by using Xilinx OBUFDS\n * cells. The clock is converted to single ended by an IBUFGDS cell\n * \n * DDR data is convered from SDR using ODDR cells\n * At this point, the data is a 14 bit in-phase data signal, \n * plus a 14 bit quadrature signal, interleaved\n * \n * The SDR data is a 32-bit OIQ datatype\n * \n * The 32-bit data is converted from 64-bits by a Gearbox\n * \n * Clock conversion happens 64-bits wide using a SyncBRAMFIFO, which\n * presents a PipeIn channel to the rest of the logic.\n */\n\n\nmodule mkFMComms1DAC(FMComms1DAC);\n   \n   Clock def_clock <- exposeCurrentClock;\n   Reset def_reset <- exposeCurrentReset;\n   Clock dac_dco; \n   Wire#(Bit#(1)) dac_dco_p <- mkDWire(0);\n   Wire#(Bit#(1)) dac_dco_n <- mkDWire(0);\n\n   dac_dco <- mkConnectalClockIBUFDS(dac_dco_p, dac_dco_n);\n   Reset dac_reset <- mkAsyncReset(3, def_reset, dac_dco);\n   \n   SyncFIFOIfc#(Vector#(2, OIQ)) outfifo <- mkSyncBRAMFIFO(128, def_clock, def_reset, dac_dco, dac_reset);\n\n   Gearbox#(2, 1, OIQ) gb <- mkNto1Gearbox(dac_dco, dac_reset, dac_dco, dac_reset);\n   ODDRParams#(Bit#(14)) oddrparams = defaultValue;\n//   oddrparams.ddr_clk_edge = \"SAME_EDGE_PIPELINED\";\n      oddrparams.ddr_clk_edge = \"SAME_EDGE\";\n\n   ODDR#(Bit#(14)) dac_ddr <- mkODDR(oddrparams, clocked_by (dac_dco));\n\n   Vector#(14, Wire#(Bit#(1))) dac_ddr_data <- replicateM(mkDWire(0));\n   \n   Vector#(14, DiffOut) dac_out = newVector;\n   \n   for (Integer i = 0; i < 14; i = i + 1)\n      dac_out[i] <- mkxOBUFDS(dac_ddr_data[i]);\n   \n   C2B dac_dco_as_bit <- mkC2B(dac_dco);\n   Wire#(Bit#(1)) dac_dci_wire <- mkDWire(0);\n   \n   rule senddown_clk;\n      dac_dci_wire <= dac_dco_as_bit.o();\n   endrule\n   \n   DiffOut dac_dci <- mkxOBUFDS(dac_dci_wire);\n   \n   rule senddown_gb;\n      outfifo.deq();\n      gb.enq(outfifo.first());\n   endrule\n\n   rule senddown_oddr;\n      let d = gb.first;\n      gb.deq();\n      dac_ddr.d1(d[0].data_i[15:2]);\n      dac_ddr.d2(d[0].data_q[15:2]);\n   endrule\n\n   rule alwaysenable;\n      dac_ddr.ce(True);\n      dac_ddr.s(False);\n   endrule\n\n   function Bit#(1) foo_p(DiffOut v);\n      return (v.read_p());\n   endfunction\n\n   function Bit#(1) foo_n(DiffOut v);\n      return (v.read_n());\n   endfunction\n\n   function Bit#(14) get_p(Vector#(14, DiffOut) v);\n      return(pack(map(foo_p, v)));\n   endfunction\n   \n   function Bit#(14) get_n(Vector#(14, DiffOut) v);\n      return(pack(map(foo_n, v)));\n   endfunction\n   \n   interface FMComms1DACPins pins;\n      \n      method Bit#(14) io_dac_data_p();\n         return(get_p(dac_out));\n      endmethod\n      \n      method Bit#(14) io_dac_data_n();\n         return(get_n(dac_out));\n      endmethod\n\n      method Bit#(1) io_dac_dci_p();\n         return(dac_dci.read_p());\n      endmethod\n      \n      method Bit#(1) io_dac_dci_n();\n         return(dac_dci.read_n());\n      endmethod\n\n      method Action io_dac_dco_p(Bit#(1) v);\n\t dac_dco_p <= v;\n      endmethod\n      \n      method Action io_dac_dco_n(Bit#(1) v);\n\t dac_dco_n <= v;\n      endmethod\n      interface deleteme_unused_clock = dac_dco;\n      interface deleteme_unused_reset = dac_reset;\n\n   endinterface\n   \n   interface PipeIn dac;\n   \n      method Action enq(Bit#(64) v);\n\t outfifo.enq(unpack(pack(v)));\n      endmethod\n      \n      method Bool notFull() = outfifo.notFull;\n      \n   endinterface\n\nendmodule\n"
  },
  {
    "path": "examples/fmcomms1/FMComms1Pins.bsv",
    "content": "// Copyright (c) 2014 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n//import Vector::*;\n//import GetPut::*;\n//import Connectable :: *;\n//import Clocks :: *;\n//import FIFO::*;\n//import Portal::*;\n//import ConnectalConfig::*;\n//import CtrlMux::*;\n//import ConnectalMemTypes::*;\n//import MemServer::*;\n//import ConnectalMMU::*;\n//import PS7LIB::*;\n//import PPS7LIB::*;\n//import FMComms1Request::*;\n//import FMComms1Indication::*;\n//import MemServerRequest::*;\n//import MMURequest::*;\n//import MemServerIndication::*;\n//import MMUIndication::*;\n//import BlueScopeEventPIORequest::*;\n//import BlueScopeEventPIOIndication::*;\n//import XilinxCells::*;\n//import ConnectalXilinxCells::*;\n//import ConnectalClocks::*;\n//import BlueScopeEventPIO::*;\nimport FMComms1ADC::*;\nimport FMComms1DAC::*;\n//import FMComms1::*;\n//import extraXilinxCells::*;\n\n/* Duplicate def here, this is also in ZynqTop */\ninterface I2C_Pins;\n   interface Inout#(Bit#(1)) scl;\n   interface Inout#(Bit#(1)) sda;\nendinterface\n\ninterface FMComms1Pins;\n   interface FMComms1ADCPins adcpins;\n   interface FMComms1DACPins dacpins;\n   interface I2C_Pins         i2c1;\n   method Bit#(1) ad9548_ref_p();\n   method Bit#(1) ad9548_ref_n();\n//   (* prefix=\"\" *)\nendinterface\n"
  },
  {
    "path": "examples/fmcomms1/Makefile",
    "content": "CONNECTALDIR?=../..\n\nINTERFACES = FMComms1Request FMComms1Indication \\\n\tBlueScopeEventPIORequest  BlueScopeEventPIOIndication\n\nBSVFILES = ../../lib/bsv/BlueScopeEventPIO.bsv \\\n\tFMComms1ADC.bsv FMComms1DAC.bsv FMComms1.bsv \\\n\t Top.bsv\nCPPFILES=testfmcomms1.cpp fmci2c.c i2c_zedboardandroid.c\nCONNECTALFLAGS = -C fmcomms1-$(BOARD).xdc --tcl clock.tcl\nCONNECTALFLAGS +=  -D USE_FMC_I2C1 -D IMPORT_HOSTIF\nPIN_TYPE = FMComms1Pins\nPIN_TYPE_INCLUDE = FMComms1Pins\n\nifeq ($(BOARD),zedboard)\nHAS_PS7=true\n#CONNECTALFLAGS += -D USE_I2C0\nendif\nifeq ($(BOARD),zc702)\nHAS_PS7=true\nendif\n\nUSER_PIN_BINDINGS ?= --pin-binding fmc:fmc1\n\ngentarget:: fmcomms1-$(BOARD).xdc\n\nfmcomms1-$(BOARD).xdc: fmcomms1-fmc.json $(CONNECTALDIR)/boardinfo/$(BOARD).json\n\t$(CONNECTALDIR)/scripts/generate-constraints.py $(USER_PIN_BINDINGS) -o fmcomms1-$(BOARD).xdc --boardfile $(CONNECTALDIR)/boardinfo/$(BOARD).json --pinoutfile fmcomms1-fmc.json\n\ninclude $(CONNECTALDIR)/Makefile.connectal\n"
  },
  {
    "path": "examples/fmcomms1/Top.bsv",
    "content": "// Copyright (c) 2014 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n`include \"ConnectalProjectConfig.bsv\"\nimport Vector::*;\nimport GetPut::*;\nimport Connectable :: *;\nimport Clocks :: *;\nimport FIFO::*;\nimport Portal::*;\nimport ConnectalConfig::*;\nimport HostInterface::*;\nimport CtrlMux::*;\nimport ConnectalMemTypes::*;\nimport MemServer::*;\nimport ConnectalMMU::*;\nimport PS7LIB::*;\nimport PPS7LIB::*;\nimport FMComms1Request::*;\nimport FMComms1Indication::*;\nimport MemServerRequest::*;\nimport MMURequest::*;\nimport MemServerIndication::*;\nimport MMUIndication::*;\nimport BlueScopeEventPIORequest::*;\nimport BlueScopeEventPIOIndication::*;\nimport XilinxCells::*;\nimport ConnectalXilinxCells::*;\nimport ConnectalClocks::*;\nimport BlueScopeEventPIO::*;\nimport FMComms1ADC::*;\nimport FMComms1DAC::*;\nimport FMComms1::*;\nimport ExtraXilinxCells::*;\nimport FMComms1Pins::*;\n\n\n`define BlueScopeEventPIOSampleLength 512\n\ntypedef enum { IfcNames_BlueScopeEventPIORequest, IfcNames_BlueScopeEventPIOIndication, IfcNames_FMComms1Request, IfcNames_FMComms1Indication, IfcNames_MemServerIndicationH2S, IfcNames_MemServerRequestS2H, IfcNames_MMURequestS2H, IfcNames_MMUIndicationH2S} IfcNames deriving (Eq,Bits);\n\n/* clk1 is the FCLKCLK1 controlled by software */\n\nmodule mkConnectalTop#(HostInterface host)(ConnectalTop);\n\n   Clock clk1 = host.ps7.fclkclk[1];\n   C2B ref_clk_as_bit <- mkC2B(clk1);\n   Wire#(Bit#(1)) ref_clk_wire <- mkDWire(0);\n   \n   rule senddown_clk;\n      ref_clk_wire <= ref_clk_as_bit.o();\n   endrule\n\n   \n   DiffOut ref_clk <- mkxOBUFDS(ref_clk_wire);\n\n   FMComms1ADC adc <- mkFMComms1ADC();\n   FMComms1DAC dac <- mkFMComms1DAC();\n   \n   BlueScopeEventPIOIndicationProxy blueScopeEventPIOIndicationProxy <- mkBlueScopeEventPIOIndicationProxy(IfcNames_BlueScopeEventPIOIndication);\n   BlueScopeEventPIOControl#(32) bs <- mkBlueScopeEventPIO(`BlueScopeEventPIOSampleLength, blueScopeEventPIOIndicationProxy.ifc);\n   BlueScopeEventPIORequestWrapper blueScopeEventPIORequestWrapper <- mkBlueScopeEventPIORequestWrapper(IfcNames_BlueScopeEventPIORequest,bs.requestIfc);\n\n`ifdef USE_FMC_I2C1\n   Clock mainclock = host.ps7.fclkclk[0];\n   Reset mainreset = host.ps7.fclkreset[0];\n   let tscl1 <- mkIOBUF(~host.ps7.i2c[1].scltn, host.ps7.i2c[1].sclo, clocked_by mainclock, reset_by mainreset);\n   let tsda1 <- mkIOBUF(~host.ps7.i2c[1].sdatn, host.ps7.i2c[1].sdao, clocked_by mainclock, reset_by mainreset);\n   rule sdai1;\n      host.ps7.i2c[1].sdai(tsda1.o);\n      host.ps7.i2c[1].scli(tscl1.o);\n   endrule\n   rule watchi2c;\n      let a = host.ps7.i2c[1].sclo();\n      let b = host.ps7.i2c[1].scltn();\n      let c = host.ps7.i2c[1].sdao();\n      let d = host.ps7.i2c[1].sdatn();\n      bs.bse.dataIn({a, b, tscl1.o, c, d, tsda1.o, 0});\n   endrule\n`endif\n\n   FMComms1IndicationProxy fmcomms1IndicationProxy <- mkFMComms1IndicationProxy(IfcNames_FMComms1Indication);\n   FMComms1 fmcomms1 <- mkFMComms1(fmcomms1IndicationProxy.ifc, dac.dac, adc.adc);\n   FMComms1RequestWrapper fmcomms1RequestWrapper <- mkFMComms1RequestWrapper(IfcNames_FMComms1Request, fmcomms1.request);\n\n   Vector#(1,  MemReadClient#(64))   readClients = cons(fmcomms1.readDmaClient, nil);\n   Vector#(1, MemWriteClient#(64))  writeClients = cons(fmcomms1.writeDmaClient, nil);\n   MMUIndicationProxy hostMMUIndicationProxy <- mkMMUIndicationProxy(IfcNames_MMUIndicationH2S);\n   MMU#(PhysAddrWidth) hostMMU <- mkMMU(0, True, hostMMUIndicationProxy.ifc);\n   MMURequestWrapper hostMMURequestWrapper <- mkMMURequestWrapper(IfcNames_MMURequestS2H, hostMMU.request);\n\n   MemServerIndicationProxy hostMemServerIndicationProxy <- mkMemServerIndicationProxy(IfcNames_MemServerIndicationH2S);\n   MemServer#(PhysAddrWidth,64,1) dma <- mkMemServer(readClients, writeClients, cons(hostMMU,nil), hostMemServerIndicationProxy.ifc);\n   MemServerRequestWrapper hostMemServerRequestWrapper <- mkMemServerRequestWrapper(IfcNames_MemServerRequestS2H, dma.request);\n\n   Vector#(8,StdPortal) portals;\n   portals[0] = fmcomms1RequestWrapper.portalIfc;\n   portals[1] = fmcomms1IndicationProxy.portalIfc; \n   portals[2] = hostMemServerRequestWrapper.portalIfc;\n   portals[3] = hostMemServerIndicationProxy.portalIfc; \n   portals[4] = hostMMURequestWrapper.portalIfc;\n   portals[5] = hostMMUIndicationProxy.portalIfc;\n   portals[6] = blueScopeEventPIORequestWrapper.portalIfc;\n   portals[7] = blueScopeEventPIOIndicationProxy.portalIfc; \n   let ctrl_mux <- mkSlaveMux(portals);\n   \n\n   \n   interface interrupt = getInterruptVector(portals);\n   interface slave = ctrl_mux;\n   interface masters = dma.masters;\n   interface FMComms1Pins pins;\n`ifdef USE_FMC_I2C1\n   interface I2C_Pins i2c1;\n      interface Inout scl = tscl1.io;\n      interface Inout sda = tsda1.io;\n   endinterface\n`endif\n      interface FMComms1ADCPins adcpins = adc.pins;\n      interface FMComms1ADCPins dacpins = dac.pins;\n      method Bit#(1) ad9548_ref_p();\n\t return(ref_clk.read_p());\n      endmethod\n   \n      method Bit#(1) ad9548_ref_n();\n\t return(ref_clk.read_n());\n      endmethod\n   endinterface\nendmodule : mkConnectalTop\n"
  },
  {
    "path": "examples/fmcomms1/clock.tcl",
    "content": "## disconnect unused CLK and RST ports inserted by bsc\nforeach {pat} {CLK_GATE_* CLK_pins_spi_clock} {\n    foreach {net} [get_nets $pat] {\n\tdisconnect_net -net $net -objects [get_pins -of_objects $net]\n    }\n}\n"
  },
  {
    "path": "examples/fmcomms1/fmci2c.c",
    "content": "/* Copyright (c) 2014 Quanta Research Cambridge, Inc\n *\n * Permission is hereby granted, free of charge, to any person obtaining a\n * copy of this software and associated documentation files (the \"Software\"),\n * to deal in the Software without restriction, including without limitation\n * the rights to use, copy, modify, merge, publish, distribute, sublicense,\n * and/or sell copies of the Software, and to permit persons to whom the\n * Software is furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n * DEALINGS IN THE SOFTWARE.\n */\n/* copied from jca's i2chdmi.h */\n\n#include <linux/types.h>\n#include <fcntl.h>\n#include <sys/ioctl.h>\n#include <errno.h>\n#include \"/usr/include/linux/i2c.h\"\n#include \"/usr/include/linux/i2c-dev.h\"\n#include <stdio.h>\n#include <stdlib.h>\n#include <string.h>\n#include <ctype.h>\n#include \"i2c_zedboardandroid.h\"\n\n\n\nint fmcomms1_get_version(int fd, int device, unsigned char *datap, int size)\n{\n  int status;\n  struct i2c_msg msgs[2];\n  unsigned char command = 1;\n  struct i2c_rdwr_ioctl_data arg;\n  msgs[0].addr = device;\n  msgs[0].flags = 0;\n  msgs[0].len = 1;\n  msgs[0].buf = &command;\n  msgs[1].addr = device;\n  msgs[1].flags = I2C_M_RD | I2C_M_RECV_LEN;\n  msgs[1].len = 33;\n  msgs[1].buf = datap;\n  arg.msgs = &msgs[0];\n  arg.nmsgs = 1;\n  datap[0] = 1;\n  status = ioctl(fd, I2C_RDWR, &arg);\n  if (status != 0) {\n    fprintf(stdout, \"[%s:%d]: ioctl I2C_RW write status=%d errno=%d [%s]\\n\", __FILE__, __LINE__, status, errno, strerror(errno));\n  }\n  arg.msgs = &msgs[1];\n  status = ioctl(fd, I2C_RDWR, &arg);\n  if (status != 0) {\n    fprintf(stdout, \"[%s:%d]: ioctl I2C_RW read status=%d errno=%d [%s]\\n\", __FILE__, __LINE__, status, errno, strerror(errno));\n  }\n  return status;\n}\n\n\nunsigned char version_data[256];\nunsigned char msgbuf[256];\nvoid testi2c(const char *i2cdevice, int deviceid)\n{\n   \n\n  int fd;\n    int i;\n    int res;\n    printf(\"i2cdevice is %s, deviceid is 0x%02x\\n\", i2cdevice, deviceid);\n    I2C_Init(i2cdevice, deviceid);\n\n\n    // start version query\n    memset(version_data, 0, 256);\n    for (i = 0; i < 256; i += 16) {\n      int j;\n      res = I2C_Read(0x50, i, 64, msgbuf);\n      printf(\"returned %d bytes\\n\", msgbuf[0]);\n      for (j=0; j < 17; j += 1) {\n\tprintf(\" %2x[%c]\", msgbuf[j],isalnum(msgbuf[j]) ? msgbuf[j]:' ');\n      }\n      printf(\"\\n\");\n      if (res < 0) {\n\tfprintf(stdout, \"testi2c failed eeprom read at %d\\n\", i);\n\treturn;\n      }\n    }\n\n    /*\n    memset(version_data, 0, 128);\n    res = fmcomms1_get_version(fd, deviceid, version_data, 128);\n    printf (\"getversion result %d\\n\", res);\n    for (i = 0; i < 32; i += 1) {\n      if ((i != 0) && ((i % 16) == 0)) printf(\"\\n\");\n      printf(\" %2x[%c]\", version_data[i],isalnum(version_data[i]) ? version_data[i]:' ');\n    }\n    printf(\"\\n\");\n    */\n}\n"
  },
  {
    "path": "examples/fmcomms1/fmci2c.h",
    "content": "/* Copyright (c) 2014 Quanta Research Cambridge, Inc\n *\n * Permission is hereby granted, free of charge, to any person obtaining a\n * copy of this software and associated documentation files (the \"Software\"),\n * to deal in the Software without restriction, including without limitation\n * the rights to use, copy, modify, merge, publish, distribute, sublicense,\n * and/or sell copies of the Software, and to permit persons to whom the\n * Software is furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n * DEALINGS IN THE SOFTWARE.\n */\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\nvoid testi2c(const char *i2cdevice, int deviceid);\n#ifdef __cplusplus\n}\n#endif\n"
  },
  {
    "path": "examples/fmcomms1/fmcomms1-fmc.json",
    "content": "{\n    \"*dac_dco_p_v\": {\n        \"PIO_DIRECTION\": \"INPUT\",\n\t\"IOSTANDARD\": \"LVDS_25\",\n\t\"DIFF_TERM\": \"TRUE\",\n\t\"fmc\": \"CLK0_M2C_p\"\n    },\n    \"*dac_dco_n_v\": {\n        \"PIO_DIRECTION\": \"INPUT\",\n\t\"IOSTANDARD\": \"LVDS_25\",\n\t\"DIFF_TERM\": \"TRUE\",\n\t\"fmc\": \"CLK0_M2C_n\"\n    },\n    \"*adc_data_p_v[8]\": {\n        \"PIO_DIRECTION\": \"INPUT\",\n\t\"IOSTANDARD\": \"LVDS_25\",\n\t\"DIFF_TERM\": \"TRUE\",\n\t\"fmc\": \"LA02_p\"\n    },\n    \"*adc_data_n_v[8]\": {\n        \"PIO_DIRECTION\": \"INPUT\",\n\t\"IOSTANDARD\": \"LVDS_25\",\n\t\"DIFF_TERM\": \"TRUE\",\n\t\"fmc\": \"LA02_n\"\n    },\n    \"*adc_data_p_v[9]\": {\n        \"PIO_DIRECTION\": \"INPUT\",\n\t\"IOSTANDARD\": \"LVDS_25\",\n\t\"DIFF_TERM\": \"TRUE\",\n\t\"fmc\": \"LA04_p\"\n    },\n    \"*adc_data_n_v[9]\": {\n        \"PIO_DIRECTION\": \"INPUT\",\n\t\"IOSTANDARD\": \"LVDS_25\",\n\t\"DIFF_TERM\": \"TRUE\",\n\t\"fmc\": \"LA04_n\"\n    },\n    \"*adc_data_p_v[7]\": {\n        \"PIO_DIRECTION\": \"INPUT\",\n\t\"IOSTANDARD\": \"LVDS_25\",\n\t\"DIFF_TERM\": \"TRUE\",\n\t\"fmc\": \"LA07_p\"\n    },\n    \"*adc_data_n_v[7]\": {\n        \"PIO_DIRECTION\": \"INPUT\",\n\t\"IOSTANDARD\": \"LVDS_25\",\n\t\"DIFF_TERM\": \"TRUE\",\n\t\"fmc\": \"LA07_n\"\n    },\n    \"*dac_frame_p_v\": {\n        \"PIO_DIRECTION\": \"OUTPUT\",\n\t\"IOSTANDARD\": \"LVDS_25\",\n\t\"DIFF_TERM\": \"TRUE\",\n\t\"fmc\": \"LA11_p\"\n    },\n    \"*dac_frame_n\": {\n        \"PIO_DIRECTION\": \"OUTPUT\",\n\t\"IOSTANDARD\": \"LVDS_25\",\n\t\"DIFF_TERM\": \"TRUE\",\n\t\"fmc\": \"LA11_n\"\n    },\n    \"*dac_data_p[14]\": {\n        \"PIO_DIRECTION\": \"OUTPUT\",\n\t\"IOSTANDARD\": \"LVDS_25\",\n\t\"DIFF_TERM\": \"TRUE\",\n\t\"fmc\": \"LA15_p\"\n    },\n    \"*dac_data_n[14]\": {\n        \"PIO_DIRECTION\": \"OUTPUT\",\n\t\"IOSTANDARD\": \"LVDS_25\",\n\t\"DIFF_TERM\": \"TRUE\",\n\t\"fmc\": \"LA15_n\"\n    },\n    \"*dac_data_p[12]\": {\n        \"PIO_DIRECTION\": \"OUTPUT\",\n\t\"IOSTANDARD\": \"LVDS_25\",\n\t\"DIFF_TERM\": \"TRUE\",\n\t\"fmc\": \"LA19_p\"\n    },\n    \"*dac_data_n[12]\": {\n        \"PIO_DIRECTION\": \"OUTPUT\",\n\t\"IOSTANDARD\": \"LVDS_25\",\n\t\"DIFF_TERM\": \"TRUE\",\n\t\"fmc\": \"LA19_n\"\n    },\n    \"*dac_dci_p\": {\n        \"PIO_DIRECTION\": \"OUTPUT\",\n\t\"IOSTANDARD\": \"LVDS_25\",\n\t\"DIFF_TERM\": \"TRUE\",\n\t\"fmc\": \"LA21_p\"\n    },\n    \"*dac_dci_n\": {\n        \"PIO_DIRECTION\": \"OUTPUT\",\n\t\"IOSTANDARD\": \"LVDS_25\",\n\t\"DIFF_TERM\": \"TRUE\",\n\t\"fmc\": \"LA21_n\"\n    },\n    \"*dac_data_p[6]\": {\n        \"PIO_DIRECTION\": \"OUTPUT\",\n\t\"IOSTANDARD\": \"LVDS_25\",\n\t\"DIFF_TERM\": \"TRUE\",\n\t\"fmc\": \"LA24_p\"\n    },\n    \"*dac_data_n[6]\": {\n        \"PIO_DIRECTION\": \"OUTPUT\",\n\t\"IOSTANDARD\": \"LVDS_25\",\n\t\"DIFF_TERM\": \"TRUE\",\n\t\"fmc\": \"LA24_n\"\n    },\n    \"*dac_data_p[3]\": {\n        \"PIO_DIRECTION\": \"OUTPUT\",\n\t\"IOSTANDARD\": \"LVDS_25\",\n\t\"DIFF_TERM\": \"TRUE\",\n\t\"fmc\": \"LA28_p\"\n    },\n    \"*dac_data_n[3]\": {\n        \"PIO_DIRECTION\": \"OUTPUT\",\n\t\"IOSTANDARD\": \"LVDS_25\",\n\t\"DIFF_TERM\": \"TRUE\",\n\t\"fmc\": \"LA28_n\"\n    },\n    \"*dac_data_p[2]\": {\n        \"PIO_DIRECTION\": \"OUTPUT\",\n\t\"IOSTANDARD\": \"LVDS_25\",\n\t\"DIFF_TERM\": \"TRUE\",\n\t\"fmc\": \"LA30_p\"\n    },\n    \"*dac_data_n[2]\": {\n        \"PIO_DIRECTION\": \"OUTPUT\",\n\t\"IOSTANDARD\": \"LVDS_25\",\n\t\"DIFF_TERM\": \"TRUE\",\n\t\"fmc\": \"LA30_n\"\n    },\n    \"*dac_data_p[0]\": {\n        \"PIO_DIRECTION\": \"OUTPUT\",\n\t\"IOSTANDARD\": \"LVDS_25\",\n\t\"DIFF_TERM\": \"TRUE\",\n\t\"fmc\": \"LA32_p\"\n    },\n    \"*dac_data_n[0]\": {\n        \"PIO_DIRECTION\": \"OUTPUT\",\n\t\"IOSTANDARD\": \"LVDS_25\",\n\t\"DIFF_TERM\": \"TRUE\",\n\t\"fmc\": \"LA32_n\"\n    },\n    \"*adc_dco_p_v\": {\n        \"PIO_DIRECTION\": \"INPUT\",\n\t\"IOSTANDARD\": \"LVDS_25\",\n\t\"DIFF_TERM\": \"TRUE\",\n\t\"fmc\": \"CLK1_M2C_p\"\n    },\n    \"*adc_dco_n_v\": {\n        \"PIO_DIRECTION\": \"INPUT\",\n\t\"IOSTANDARD\": \"LVDS_25\",\n\t\"DIFF_TERM\": \"TRUE\",\n\t\"fmc\": \"CLK1_M2C_n\"\n    },\n    \"*adc_or_p_v\": {\n        \"PIO_DIRECTION\": \"OUTPUT\",\n\t\"IOSTANDARD\": \"LVDS_25\",\n\t\"DIFF_TERM\": \"TRUE\",\n\t\"fmc\": \"LA00_p_CC\"\n    },\n    \"*adc_or_n_v\": {\n        \"PIO_DIRECTION\": \"OUTPUT\",\n\t\"IOSTANDARD\": \"LVDS_25\",\n\t\"DIFF_TERM\": \"TRUE\",\n\t\"fmc\": \"LA00_n_CC\"\n    },\n    \"*adc_data_p_v[3]\": {\n        \"PIO_DIRECTION\": \"INPUT\",\n\t\"IOSTANDARD\": \"LVDS_25\",\n\t\"DIFF_TERM\": \"TRUE\",\n\t\"fmc\": \"LA03_p\"\n    },\n    \"*adc_data_n_v[3]\": {\n        \"PIO_DIRECTION\": \"INPUT\",\n\t\"IOSTANDARD\": \"LVDS_25\",\n\t\"DIFF_TERM\": \"TRUE\",\n\t\"fmc\": \"LA03_n\"\n    },\n    \"*adc_data_p_v[11]\": {\n        \"PIO_DIRECTION\": \"INPUT\",\n\t\"IOSTANDARD\": \"LVDS_25\",\n\t\"DIFF_TERM\": \"TRUE\",\n\t\"fmc\": \"LA08_p\"\n    },\n    \"*adc_data_n_v[11]\": {\n        \"PIO_DIRECTION\": \"INPUT\",\n\t\"IOSTANDARD\": \"LVDS_25\",\n\t\"DIFF_TERM\": \"TRUE\",\n\t\"fmc\": \"LA08_n\"\n    },\n    \"*adc_data_p_v[6]\": {\n        \"PIO_DIRECTION\": \"INPUT\",\n\t\"IOSTANDARD\": \"LVDS_25\",\n\t\"DIFF_TERM\": \"TRUE\",\n\t\"fmc\": \"LA12_p\"\n    },\n    \"*adc_data_n_v[6]\": {\n        \"PIO_DIRECTION\": \"INPUT\",\n\t\"IOSTANDARD\": \"LVDS_25\",\n\t\"DIFF_TERM\": \"TRUE\",\n\t\"fmc\": \"LA12_n\"\n    },\n    \"*dac_data_p[15]\": {\n        \"PIO_DIRECTION\": \"OUTPUT\",\n\t\"IOSTANDARD\": \"LVDS_25\",\n\t\"DIFF_TERM\": \"TRUE\",\n\t\"fmc\": \"LA16_p\"\n    },\n    \"*dac_data_n[15]\": {\n        \"PIO_DIRECTION\": \"OUTPUT\",\n\t\"IOSTANDARD\": \"LVDS_25\",\n\t\"DIFF_TERM\": \"TRUE\",\n\t\"fmc\": \"LA16_n\"\n    },\n    \"*dac_data_p[13]\": {\n        \"PIO_DIRECTION\": \"OUTPUT\",\n\t\"IOSTANDARD\": \"LVDS_25\",\n\t\"DIFF_TERM\": \"TRUE\",\n\t\"fmc\": \"LA20_p\"\n    },\n    \"*dac_data_n[13]\": {\n        \"PIO_DIRECTION\": \"OUTPUT\",\n\t\"IOSTANDARD\": \"LVDS_25\",\n\t\"DIFF_TERM\": \"TRUE\",\n\t\"fmc\": \"LA20_n\"\n    },\n    \"*dac_data_p[8]\": {\n        \"PIO_DIRECTION\": \"OUTPUT\",\n\t\"IOSTANDARD\": \"LVDS_25\",\n\t\"DIFF_TERM\": \"TRUE\",\n\t\"fmc\": \"LA22_p\"\n    },\n    \"*dac_data_n[8]\": {\n        \"PIO_DIRECTION\": \"OUTPUT\",\n\t\"IOSTANDARD\": \"LVDS_25\",\n\t\"DIFF_TERM\": \"TRUE\",\n\t\"fmc\": \"LA22_n\"\n    },\n    \"*dac_data_p[7]\": {\n        \"PIO_DIRECTION\": \"OUTPUT\",\n\t\"IOSTANDARD\": \"LVDS_25\",\n\t\"DIFF_TERM\": \"TRUE\",\n\t\"fmc\": \"LA25_p\"\n    },\n    \"*dac_data_n[7]\": {\n        \"PIO_DIRECTION\": \"OUTPUT\",\n\t\"IOSTANDARD\": \"LVDS_25\",\n\t\"DIFF_TERM\": \"TRUE\",\n\t\"fmc\": \"LA25_n\"\n    },\n    \"*dac_data_p[5]\": {\n        \"PIO_DIRECTION\": \"OUTPUT\",\n\t\"IOSTANDARD\": \"LVDS_25\",\n\t\"DIFF_TERM\": \"TRUE\",\n\t\"fmc\": \"LA29_p\"\n    },\n    \"*dac_data_n[5]\": {\n        \"PIO_DIRECTION\": \"OUTPUT\",\n\t\"IOSTANDARD\": \"LVDS_25\",\n\t\"DIFF_TERM\": \"TRUE\",\n\t\"fmc\": \"LA29_n\"\n    },\n    \"*dac_data_p[4]\": {\n        \"PIO_DIRECTION\": \"OUTPUT\",\n\t\"IOSTANDARD\": \"LVDS_25\",\n\t\"DIFF_TERM\": \"TRUE\",\n\t\"fmc\": \"LA31_p\"\n    },\n    \"*dac_data_n[4]\": {\n        \"PIO_DIRECTION\": \"OUTPUT\",\n\t\"IOSTANDARD\": \"LVDS_25\",\n\t\"DIFF_TERM\": \"TRUE\",\n\t\"fmc\": \"LA31_n\"\n    },\n    \"*dac_data_p[1]\": {\n        \"PIO_DIRECTION\": \"OUTPUT\",\n\t\"IOSTANDARD\": \"LVDS_25\",\n\t\"DIFF_TERM\": \"TRUE\",\n\t\"fmc\": \"LA33_p\"\n    },\n    \"*dac_data_n[1]\": {\n        \"PIO_DIRECTION\": \"OUTPUT\",\n\t\"IOSTANDARD\": \"LVDS_25\",\n\t\"DIFF_TERM\": \"TRUE\",\n\t\"fmc\": \"LA33_n\"\n    },\n    \"*adc_data_p_v[13]\": {\n        \"PIO_DIRECTION\": \"INPUT\",\n\t\"IOSTANDARD\": \"LVDS_25\",\n\t\"DIFF_TERM\": \"TRUE\",\n\t\"fmc\": \"LA01_p_CC\"\n    },\n    \"*adc_data_n_v[13]\": {\n        \"PIO_DIRECTION\": \"INPUT\",\n\t\"IOSTANDARD\": \"LVDS_25\",\n\t\"DIFF_TERM\": \"TRUE\",\n\t\"fmc\": \"LA01_n_CC\"\n    },\n    \"*adc_data_p_v[4]\": {\n        \"PIO_DIRECTION\": \"INPUT\",\n\t\"IOSTANDARD\": \"LVDS_25\",\n\t\"DIFF_TERM\": \"TRUE\",\n\t\"fmc\": \"LA05_p\"\n    },\n    \"*adc_data_n_v[4]\": {\n        \"PIO_DIRECTION\": \"INPUT\",\n\t\"IOSTANDARD\": \"LVDS_25\",\n\t\"DIFF_TERM\": \"TRUE\",\n\t\"fmc\": \"LA05_n\"\n    },\n    \"*adc_data_p_v[10]\": {\n        \"PIO_DIRECTION\": \"INPUT\",\n\t\"IOSTANDARD\": \"LVDS_25\",\n\t\"DIFF_TERM\": \"TRUE\",\n\t\"fmc\": \"LA09_p\"\n    },\n    \"*adc_data_n_v[10]\": {\n        \"PIO_DIRECTION\": \"INPUT\",\n\t\"IOSTANDARD\": \"LVDS_25\",\n\t\"DIFF_TERM\": \"TRUE\",\n\t\"fmc\": \"LA09_n\"\n    },\n    \"*adc_data_p_v[2]\": {\n        \"PIO_DIRECTION\": \"INPUT\",\n\t\"IOSTANDARD\": \"LVDS_25\",\n\t\"DIFF_TERM\": \"TRUE\",\n\t\"fmc\": \"LA13_p\"\n    },\n    \"*adc_data_n_v[2]\": {\n        \"PIO_DIRECTION\": \"INPUT\",\n\t\"IOSTANDARD\": \"LVDS_25\",\n\t\"DIFF_TERM\": \"TRUE\",\n\t\"fmc\": \"LA13_n\"\n    },\n    \"*ad9548_ref_p\": {\n        \"PIO_DIRECTION\": \"OUTPUT\",\n\t\"IOSTANDARD\": \"LVDS_25\",\n\t\"DIFF_TERM\": \"TRUE\",\n\t\"fmc\": \"LA17_p_CC\"\n    },\n    \"*ad9548_ref_n\": {\n        \"PIO_DIRECTION\": \"OUTPUT\",\n\t\"IOSTANDARD\": \"LVDS_25\",\n\t\"DIFF_TERM\": \"TRUE\",\n\t\"fmc\": \"LA17_n_CC\"\n    },\n    \"*dac_data_p[11]\": {\n        \"PIO_DIRECTION\": \"OUTPUT\",\n\t\"IOSTANDARD\": \"LVDS_25\",\n\t\"DIFF_TERM\": \"TRUE\",\n\t\"fmc\": \"LA23_p\"\n    },\n    \"*dac_data_n[11]\": {\n        \"PIO_DIRECTION\": \"OUTPUT\",\n\t\"IOSTANDARD\": \"LVDS_25\",\n\t\"DIFF_TERM\": \"TRUE\",\n\t\"fmc\": \"LA23_n\"\n    },\n    \"*dac_data_p[10]\": {\n        \"PIO_DIRECTION\": \"OUTPUT\",\n\t\"IOSTANDARD\": \"LVDS_25\",\n\t\"DIFF_TERM\": \"TRUE\",\n\t\"fmc\": \"LA26_p\"\n    },\n    \"*dac_data_n[10]\": {\n        \"PIO_DIRECTION\": \"OUTPUT\",\n\t\"IOSTANDARD\": \"LVDS_25\",\n\t\"DIFF_TERM\": \"TRUE\",\n\t\"fmc\": \"LA26_n\"\n    },\n    \"*adc_data_p_v[12]\": {\n        \"PIO_DIRECTION\": \"INPUT\",\n\t\"IOSTANDARD\": \"LVDS_25\",\n\t\"DIFF_TERM\": \"TRUE\",\n\t\"fmc\": \"LA06_p\"\n    },\n    \"*adc_data_n_v[12]\": {\n        \"PIO_DIRECTION\": \"INPUT\",\n\t\"IOSTANDARD\": \"LVDS_25\",\n\t\"DIFF_TERM\": \"TRUE\",\n\t\"fmc\": \"LA06_n\"\n    },\n    \"*adc_data_p_v[5]\": {\n        \"PIO_DIRECTION\": \"INPUT\",\n\t\"IOSTANDARD\": \"LVDS_25\",\n\t\"DIFF_TERM\": \"TRUE\",\n\t\"fmc\": \"LA10_p\"\n    },\n    \"*adc_data_n_v[5]\": {\n        \"PIO_DIRECTION\": \"INPUT\",\n\t\"IOSTANDARD\": \"LVDS_25\",\n\t\"DIFF_TERM\": \"TRUE\",\n\t\"fmc\": \"LA10_n\"\n    },\n    \"*adc_data_p_v[1]\": {\n        \"PIO_DIRECTION\": \"INPUT\",\n\t\"IOSTANDARD\": \"LVDS_25\",\n\t\"DIFF_TERM\": \"TRUE\",\n\t\"fmc\": \"LA14_p\"\n    },\n    \"*adc_data_n_v[1]\": {\n        \"PIO_DIRECTION\": \"INPUT\",\n\t\"IOSTANDARD\": \"LVDS_25\",\n\t\"DIFF_TERM\": \"TRUE\",\n\t\"fmc\": \"LA14_n\"\n    },\n    \"*adc_data_p_v[0]\": {\n        \"PIO_DIRECTION\": \"INPUT\",\n\t\"IOSTANDARD\": \"LVDS_25\",\n\t\"DIFF_TERM\": \"TRUE\",\n\t\"fmc\": \"LA18_p_CC\"\n    },\n    \"*adc_data_n_v[0]\": {\n        \"PIO_DIRECTION\": \"INPUT\",\n\t\"IOSTANDARD\": \"LVDS_25\",\n\t\"DIFF_TERM\": \"TRUE\",\n\t\"fmc\": \"LA18_n_CC\"\n    },\n    \"*dac_data_p[9]\": {\n        \"PIO_DIRECTION\": \"OUTPUT\",\n\t\"IOSTANDARD\": \"LVDS_25\",\n\t\"DIFF_TERM\": \"TRUE\",\n\t\"fmc\": \"LA27_p\"\n    },\n    \"*dac_data_n[9]\": {\n        \"PIO_DIRECTION\": \"OUTPUT\",\n\t\"IOSTANDARD\": \"LVDS_25\",\n\t\"DIFF_TERM\": \"TRUE\",\n\t\"fmc\": \"LA27_n\"\n    },\n    \"*i2c1_scl\": {\n\t\"PIO_DIRECTION\": \"BIDIR\",\n\t\"IOSTANDARD\": \"LVCMOS33\",\n\t\"fmc\": \"SCL\"\n    },\n    \"*i2c1_sda\": {\n\t\"PIO_DIRECTION\": \"BIDIR\",\n\t\"IOSTANDARD\": \"LVCMOS33\",\n\t\"fmc\": \"SDA\"\n    }\n}\n\n"
  },
  {
    "path": "examples/fmcomms1/i2c_zedboardandroid.c",
    "content": "/**************************************************************************//**\n*   @file   i2c_zedboardandroid.c\n*   @brief  ZYNQ Hardware I2C functions implementation.\n*\n*******************************************************************************\n* API copied from i2c_ps7.c\n* Copyright 2011(c) Analog Devices, Inc.\n*/\n\n#include \"/usr/include/linux/i2c.h\"\n#include \"/usr/include/linux/i2c-dev.h\"\n#include <stdio.h>\n#include <fcntl.h>\n#include <stdlib.h>\n#include <errno.h>\n\nstatic int fd;\n\nvoid dump_i2c_msg(struct i2c_msg *msg)\n{\n  int i;\n  fprintf(stdout, \"  addr 0x%02x flags[\", msg->addr);\n  if (msg->flags & I2C_M_RD) fprintf(stdout, \" RD\");\n  else fprintf(stdout, \" WR\");\n  if (msg->flags & I2C_M_RECV_LEN) fprintf(stdout, \" RDLEN\");\n  else fprintf(stdout, \"      \");\n  fprintf(stdout, \" ] len %d \", msg->len);\n  if ((msg->flags & I2C_M_RD) == 0) {\n    fprintf(stdout, \" [\");\n    for (i = 0; i < msg->len; i += 1)\n      fprintf(stdout, \" %02x\", msg->buf[i]);\n    fprintf(stdout, \" ]\\n\");\n  } else {\n    fprintf(stdout, \"\\n\");\n  }\n}\n\nvoid dump_i2c_rdwr(struct i2c_rdwr_ioctl_data *arg)\n{\n  int i;\n  fprintf(stdout, \"i2c_rdwr[%d]\\n\", arg->nmsgs);\n  for (i = 0; i < arg->nmsgs; i += 1)\n    dump_i2c_msg(&arg->msgs[i]);\n}\n\n/**************************************************************************//**\n* @brief Initializes the I2C communication multiplexer.\n*\n* @param sel - Multiplexer selection value.\n*\n* @return Returns 0 or negative error code.\n******************************************************************************/\nuint32_t I2C_Init(char * devfile, uint32_t i2cAddr)\n{\n\tuint32_t ret = 0;\n\tfprintf(stdout, \"opening %s\\n\", devfile);\n\tfd = open(devfile, O_RDWR);\n\tif (fd < 0) {\n\t  fprintf(stdout, \"can't open device %s: %s [%d]\", devfile, strerror(errno), errno);\n\t}\n\t\n\n\treturn ret;\n}\n\n/**************************************************************************//**\n* @brief Writes data to an I2C slave.\n*\n* @param i2cAddr - The address of the I2C slave.\n* @param regAddr - Address of the I2C register to be read.\n*\t\t\t\t   Must be set to -1 if it is not used.\n* @param txSize - Number of bytes to write to the slave.\n* @param txBuf - Buffer to store the data to be transmitted.\n*\n* @return Returns the number of bytes written.\n******************************************************************************/\nuint32_t I2C_Write(uint32_t i2cAddr, uint32_t regAddr, \n                       uint32_t txSize, uint8_t* txBuf)\n{\n  int status, i;\n  unsigned char buf[128];\n  struct i2c_msg msgs[1];\n  struct i2c_rdwr_ioctl_data arg;\n  msgs[0].addr = i2cAddr;\n  msgs[0].flags = 0;\n  msgs[0].buf = buf;\n  arg.msgs = msgs;\n  arg.nmsgs = 1;\n  if (txSize > 127) return -1;\n  if (regAddr != 0xffffffff) {\n    buf[0] = regAddr;\n    memcpy(&buf[1], txBuf, txSize);\n    msgs[0].len = txSize + 1;\n  } else {\n    memcpy(&buf[0], txBuf, txSize);\n    msgs[0].len = txSize;\n  }\n  fprintf(stdout, \"I2C_Write(0x%02x, 0x%02x, %d, [\", i2cAddr, regAddr, txSize);\n  for (i = 0 ; i < msgs[0].len; i += 1)\n    fprintf(stdout, \" %02x\", buf[i]);\n  fprintf(stdout, \" ])\\n\");\n  dump_i2c_rdwr(&arg);\n  status = ioctl(fd, I2C_RDWR, &arg);\n  if (status != 0) {\n    fprintf(stdout, \"[%s:%d]: ioctl I2C_RW 1 status=%d errno=%d [%s]\\n\", __FILE__, __LINE__, status, errno, strerror(errno));\n  }\n  fprintf(stdout, \"returns %d\\n\", txSize);\n  return txSize;\n}\n\n/**************************************************************************//**\n* @brief Reads data from an I2C slave.\n*\n* @param i2cAddr - The address of the I2C slave.\n* @param regAddr - Address of the I2C register to be read.\n*\t\t\t\t   Must be set to -1 if it is not used.\n* @param rxSize - Number of bytes to read from the slave.\n* @param rxBuf - Buffer to store the read data.\n*\n* @return Returns the number of bytes read.\n******************************************************************************/\nuint32_t I2C_Read(uint32_t i2cAddr, uint32_t regAddr, \n                      uint32_t rxSize, uint8_t* rxBuf)\n{\n  int status, i;\n  unsigned char buf[128];\n  struct i2c_msg msgs[1];\n  struct i2c_rdwr_ioctl_data arg;\n  msgs[0].addr = i2cAddr;\n  msgs[0].flags = I2C_M_RD | I2C_M_RECV_LEN;\n  msgs[0].len = rxSize;\n  msgs[0].buf = buf;\n  arg.msgs = msgs;\n  arg.nmsgs = 1;\n  buf[0] = 1;\n  if (regAddr != 0xffffffff) I2C_Write(i2cAddr, regAddr, 0, NULL);\n  fprintf(stdout, \"I2C_Read(0x%02x, 0x%02x, %d)\\n\", i2cAddr, regAddr, rxSize);\n  dump_i2c_rdwr(&arg);\n  status = ioctl(fd, I2C_RDWR, &arg);\n  if (status != 0) {\n    fprintf(stdout, \"[%s, %d]: ioctl I2C_RW status=%d errno=%d [%s]\\n\", __FILE__, __LINE__, status, errno, strerror(errno));\n  }\n  if (buf[0] > rxSize) buf[0] = rxSize;\n  memcpy(rxBuf, &buf[1], buf[0]);\n  fprintf(stdout, \"  returns %d [\", buf[0]);\n  for (i = 0 ; i <= buf[0]; i += 1)\n    fprintf(stdout, \" %02x\", buf[i]);\n  fprintf(stdout, \" ]\\n\");\n  return buf[0];\n\n}\n\n"
  },
  {
    "path": "examples/fmcomms1/i2c_zedboardandroid.h",
    "content": "/**************************************************************************//**\r\n*   @file   i2c_zedboardandroid.h\r\n*   @brief  ZYNQ Hardware I2C header file.\r\n*\r\n*******************************************************************************\r\n* API copied from i2c_ps7.h\r\n* Copyright 2011(c) Analog Devices, Inc.\r\n*/\r\n\r\n#include <stdint.h>\r\n\r\nuint32_t I2C_Init(const char * devfile, uint32_t i2cAddr);\r\n\r\nuint32_t I2C_Read(uint32_t i2cAddr, uint32_t regAddr, uint32_t rxSize, uint8_t* rxBuf);\r\n\r\nuint32_t I2C_Write(uint32_t i2cAddr, uint32_t regAddr, uint32_t txSize, uint8_t* txBuf);\r\n\r\n"
  },
  {
    "path": "examples/fmcomms1/readtrace.py",
    "content": "from __future__ import print_function\n\nlastevent = 0\nosclo = 0\noscltn = 0\noscli = 0\nosdao = 0\nosdatn = 0\nosdai = 0\nbitnum = 0\ndatabyte = 0\n\ndef reportEvent(v, timestamp):\n    global osclo\n    global oscltn\n    global oscli\n    global osdao\n    global osdatn\n    global osdai\n    global lastevent\n    global bitnum\n    global databyte\n    sclo = (v & 0x80000000) >> 31\n    scltn = (v & 0x40000000) >> 30\n    scli = (v & 0x20000000) >> 29\n    sdao = (v & 0x10000000) >> 28\n    sdatn = (v & 0x8000000) >> 27\n    sdai = (v & 0x4000000) >> 26\n    print(\"ts %8x %d sclo %d scltn %d scli %d sdao %d sdatn %d sdai %d\" % (timestamp, (timestamp - lastevent), sclo, scltn, scli, sdao, sdatn, sdai))\n    lastevent = timestamp\n    if (not oscltn and scltn):\n        print(\"drive SCL\")\n    if (oscltn and not scltn):\n        print(\"listen SCL\")\n    if (not osdatn and sdatn):\n        print(\"drive SDA\")\n    if (osdatn and not sdatn):\n        print(\"listen SDA\")\n    if (oscli and scli and osdai and not sdai):\n        print(\"START\")\n        bitnum = 0\n    if (oscli and scli and not osdai and sdai):\n        print( \"STOP\")\n    if (not oscli and scli and sdai):\n        if sdatn:\n            print( \"databit 1 TX\")\n        else:\n            print( \"databit 1 RX\")\n        if bitnum == 8:\n            print(\"databyte %02x NACK\" % databyte)\n            bitnum = 0\n            databyte = 0\n        else:\n            print (\"bitnum %x\" % bitnum)\n            databyte = (databyte << 1) + 1\n            bitnum = bitnum + 1\n    if (not oscli and scli and not sdai):\n        if sdatn:\n            print( \"databit 0 TX\")\n        else:\n            print( \"databit 0 RX\")\n        if bitnum == 8:\n            print(\"databyte %02x ACK\" % databyte)\n            bitnum = 0\n            databyte = 0\n        else:\n            print (\"bitnum %x\" % bitnum)\n            databyte = (databyte << 1) + 0\n            bitnum = bitnum + 1\n    osclo = sclo\n    oscltn = scltn\n    oscli = scli\n    osdao = sdao\n    osdatn = sdatn\n    osdai = sdai\n\n\n\nreportEvent(0x24000000, 0x44200000)\n\nreportEvent(0x2c000000, 0x4446383e)\nreportEvent(0x68000000, 0x444639ad)\nreportEvent(0x48000000, 0x444639b3)\nreportEvent(0x40000000, 0x44463c30)\nreportEvent(0x44000000, 0x44463c36)\nreportEvent(0x04000000, 0x44463d9f)\nreportEvent(0x24000000, 0x44463da5)\nreportEvent(0x44000000, 0x44463f98)\nreportEvent(0x48000000, 0x44464022)\nreportEvent(0x08000000, 0x44464191)\nreportEvent(0x28000000, 0x44464197)\nreportEvent(0x48000000, 0x4446438a)\nreportEvent(0x40000000, 0x44464413)\nreportEvent(0x44000000, 0x44464419)\nreportEvent(0x24000000, 0x44464587)\nreportEvent(0x64000000, 0x4446477b)\nreportEvent(0x44000000, 0x44464781)\nreportEvent(0x4c000000, 0x44464805)\nreportEvent(0x48000000, 0x4446480b)\nreportEvent(0x08000000, 0x44464974)\nreportEvent(0x28000000, 0x4446497a)\nreportEvent(0x68000000, 0x44464b6d)\nreportEvent(0x48000000, 0x44464b73)\nreportEvent(0x08000000, 0x44464d66)\nreportEvent(0x68000000, 0x44464f5f)\nreportEvent(0x08000000, 0x44465158)\nreportEvent(0x28000000, 0x4446515e)\nreportEvent(0x48000000, 0x44465351)\nreportEvent(0x08000000, 0x4446554a)\nreportEvent(0x28000000, 0x44465550)\nreportEvent(0x48000000, 0x44465743)\nreportEvent(0x28000000, 0x44465940)\nreportEvent(0x68000000, 0x44465b34)\nreportEvent(0x48000000, 0x44465b3a)\nreportEvent(0x40000000, 0x44465bbe)\nreportEvent(0x00000000, 0x44465d2d)\nreportEvent(0x20000000, 0x44465d33)\nreportEvent(0x60000000, 0x44465f26)\nreportEvent(0x40000000, 0x44465f2c)\nreportEvent(0x44000000, 0x44465f43)\nreportEvent(0x4c000000, 0x44465fb0)\nreportEvent(0x08000000, 0x4446611f)\nreportEvent(0x68000000, 0x44466318)\nreportEvent(0x08000000, 0x44466511)\nreportEvent(0x28000000, 0x44466517)\nreportEvent(0x48000000, 0x4446670a)\nreportEvent(0x08000000, 0x44466903)\nreportEvent(0x28000000, 0x44466909)\nreportEvent(0x48000000, 0x44466afc)\nreportEvent(0x28000000, 0x44466cf9)\nreportEvent(0x68000000, 0x44466eed)\nreportEvent(0x48000000, 0x44466ef3)\nreportEvent(0x08000000, 0x444670e6)\nreportEvent(0x28000000, 0x444670ec)\nreportEvent(0x68000000, 0x444672df)\nreportEvent(0x48000000, 0x444672e5)\nreportEvent(0x08000000, 0x444674d8)\nreportEvent(0x68000000, 0x444676d1)\nreportEvent(0x08000000, 0x444678ca)\nreportEvent(0x28000000, 0x444678d0)\nreportEvent(0x48000000, 0x44467ac3)\nreportEvent(0x08000000, 0x44467cbc)\nreportEvent(0x28000000, 0x44467cc2)\nreportEvent(0x48000000, 0x44467eb5)\nreportEvent(0x40000000, 0x44467f3e)\nreportEvent(0x20000000, 0x444680b2)\nreportEvent(0x60000000, 0x444682a6)\nreportEvent(0x40000000, 0x444682ac)\nreportEvent(0x4c000000, 0x44468330)\nreportEvent(0x48000000, 0x44468336)\nreportEvent(0x08000000, 0x4446849f)\nreportEvent(0x28000000, 0x444684a5)\nreportEvent(0x20000000, 0x44468722)\nreportEvent(0x24000000, 0x44468728)\nreportEvent(0x28000000, 0x44473a9c)\nreportEvent(0x68000000, 0x44473c0b)\nreportEvent(0x40000000, 0x44473e8e)\nreportEvent(0x44000000, 0x44473e94)\nreportEvent(0x04000000, 0x44473ffd)\nreportEvent(0x24000000, 0x44474003)\nreportEvent(0x44000000, 0x444741f6)\nreportEvent(0x4c000000, 0x4447427f)\nreportEvent(0x48000000, 0x44474285)\nreportEvent(0x08000000, 0x444743ef)\nreportEvent(0x28000000, 0x444743f5)\nreportEvent(0x48000000, 0x444745e8)\nreportEvent(0x40000000, 0x44474671)\nreportEvent(0x24000000, 0x444747e6)\nreportEvent(0x64000000, 0x444749d9)\nreportEvent(0x44000000, 0x444749df)\nreportEvent(0x4c000000, 0x44474a63)\nreportEvent(0x48000000, 0x44474a69)\nreportEvent(0x08000000, 0x44474bd2)\nreportEvent(0x68000000, 0x44474dcb)\nreportEvent(0x48000000, 0x44474dd1)\nreportEvent(0x08000000, 0x44474fc4)\nreportEvent(0x48000000, 0x444751bd)\nreportEvent(0x08000000, 0x444753b6)\nreportEvent(0x28000000, 0x444753bc)\nreportEvent(0x48000000, 0x444755af)\nreportEvent(0x28000000, 0x444757ac)\nreportEvent(0x48000000, 0x444759a1)\nreportEvent(0x40000000, 0x44475a2a)\nreportEvent(0x24000000, 0x44475b9f)\nreportEvent(0x64000000, 0x44475d92)\nreportEvent(0x44000000, 0x44475d98)\nreportEvent(0x00000000, 0x44475db6)\nreportEvent(0x40000000, 0x44475dbc)\nreportEvent(0x00000000, 0x44475f8b)\nreportEvent(0x60000000, 0x44476184)\nreportEvent(0x40000000, 0x4447618a)\nreportEvent(0x00000000, 0x4447637d)\nreportEvent(0x60000000, 0x44476c18)\nreportEvent(0x40000000, 0x44476c1e)\nreportEvent(0x00000000, 0x44476e11)\nreportEvent(0x60000000, 0x4447700a)\nreportEvent(0x00000000, 0x44477203)\nreportEvent(0x20000000, 0x44477209)\nreportEvent(0x40000000, 0x444773fc)\nreportEvent(0x00000000, 0x444775f5)\nreportEvent(0x20000000, 0x444775fb)\nreportEvent(0x40000000, 0x444777ee)\nreportEvent(0x20000000, 0x444779eb)\nreportEvent(0x60000000, 0x44477bdf)\nreportEvent(0x40000000, 0x44477be5)\nreportEvent(0x00000000, 0x44477dd8)\nreportEvent(0x20000000, 0x44477dde)\nreportEvent(0x60000000, 0x44477fd1)\nreportEvent(0x40000000, 0x44477fd7)\nreportEvent(0x00000000, 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0x445e7893)\nreportEvent(0x44000000, 0x445e7899)\nreportEvent(0x44000000, 0x445e78b9)\nreportEvent(0x40000000, 0x445e78bf)\nreportEvent(0x00000000, 0x445e7a8c)\nreportEvent(0x60000000, 0x445e7c85)\nreportEvent(0x40000000, 0x445e7c8b)\nreportEvent(0x44000000, 0x445e7ca2)\nreportEvent(0x04000000, 0x445e7e7e)\nreportEvent(0x44000000, 0x445e8077)\nreportEvent(0x48000000, 0x445e8101)\nreportEvent(0x08000000, 0x445e8270)\nreportEvent(0x28000000, 0x445e8276)\nreportEvent(0x48000000, 0x445e8469)\nreportEvent(0x44000000, 0x445e84f7)\nreportEvent(0x00000000, 0x445e8cc2)\nreportEvent(0x00000000, 0x445e8cc8)\nreportEvent(0x40000000, 0x445e8ecf)\nreportEvent(0x44000000, 0x445e8eec)\nreportEvent(0x04000000, 0x445e90c8)\nreportEvent(0x24000000, 0x445e90ce)\nreportEvent(0x44000000, 0x445e92c1)\nreportEvent(0x44000000, 0x445e92e6)\nreportEvent(0x20000000, 0x445e94be)\nreportEvent(0x40000000, 0x445e96b3)\nreportEvent(0x20000000, 0x445e98b1)\nreportEvent(0x60000000, 0x445e9aa4)\nreportEvent(0x40000000, 0x445e9aaa)\nreportEvent(0x04000000, 0x445e9c9d)\nreportEvent(0x64000000, 0x445e9e96)\nreportEvent(0x44000000, 0x445e9e9c)\nreportEvent(0x04000000, 0x445ea08f)\nreportEvent(0x44000000, 0x445ea288)\nreportEvent(0x48000000, 0x4458584a)\nreportEvent(0x00000000, 0x445ea481)\nreportEvent(0x20000000, 0x445ea487)\nreportEvent(0x40000000, 0x445ea67a)\nreportEvent(0x44000000, 0x445ea697)\nreportEvent(0x04000000, 0x445ea873)\nreportEvent(0x24000000, 0x445ea879)\nreportEvent(0x44000000, 0x445eaa6c)\nreportEvent(0x4c000000, 0x445eaaf5)\nreportEvent(0x48000000, 0x445eaafb)\nreportEvent(0x28000000, 0x445eac6a)\nreportEvent(0x68000000, 0x445eae5d)\nreportEvent(0x48000000, 0x445eae63)\nreportEvent(0x40000000, 0x445eaee7)\nreportEvent(0x04000000, 0x445eb056)\nreportEvent(0x04000000, 0x445eb6b3)\nreportEvent(0x20000000, 0x445eb6d0)\nreportEvent(0x40000000, 0x445eb8c4)\nreportEvent(0x44000000, 0x445eb8e1)\nreportEvent(0x24000000, 0x445ebac2)\nreportEvent(0x64000000, 0x445ebcb5)\nreportEvent(0x44000000, 0x445ebcbb)\nreportEvent(0x44000000, 0x445ebcdb)\nreportEvent(0x00000000, 0x445ebeae)\nreportEvent(0x60000000, 0x445ec0a7)\nreportEvent(0x40000000, 0x445ec0ad)\nreportEvent(0x44000000, 0x445ec0c4)\nreportEvent(0x04000000, 0x445ec2a0)\nreportEvent(0x44000000, 0x445ec499)\nreportEvent(0x44000000, 0x445ec4bc)\nreportEvent(0x00000000, 0x445ec692)\nreportEvent(0x20000000, 0x445ec698)\nreportEvent(0x40000000, 0x445ec88b)\nreportEvent(0x20000000, 0x445eca88)\nreportEvent(0x40000000, 0x445ecc7d)\nreportEvent(0x24000000, 0x445ece7b)\nreportEvent(0x64000000, 0x445ed06e)\nreportEvent(0x44000000, 0x445ed074)\nreportEvent(0x04000000, 0x445ed267)\nreportEvent(0x64000000, 0x445ed460)\nreportEvent(0x44000000, 0x445ed466)\nreportEvent(0x48000000, 0x445ed4ea)\nreportEvent(0x08000000, 0x445ed659)\nreportEvent(0x48000000, 0x445ed852)\nreportEvent(0x40000000, 0x445ed8dc)\nreportEvent(0x44000000, 0x445ed8e2)\nreportEvent(0x04000000, 0x445eda4b)\nreportEvent(0x04000000, 0x445ee0a6)\nreportEvent(0x00000000, 0x445ee0ac)\nreportEvent(0x60000000, 0x445ee2b8)\nreportEvent(0x40000000, 0x445ee2be)\nreportEvent(0x00000000, 0x445ee4b1)\nreportEvent(0x40000000, 0x445ee6aa)\nreportEvent(0x44000000, 0x445ee6c7)\nreportEvent(0x04000000, 0x445ee8a3)\nreportEvent(0x24000000, 0x445ee8a9)\nreportEvent(0x44000000, 0x445eea9c)\nreportEvent(0x24000000, 0x445eec99)\nreportEvent(0x44000000, 0x445eee8e)\nreportEvent(0x44000000, 0x445eeeb1)\nreportEvent(0x20000000, 0x445ef08c)\nreportEvent(0x60000000, 0x445ef27f)\nreportEvent(0x40000000, 0x445ef285)\nreportEvent(0x00000000, 0x445ef478)\nreportEvent(0x60000000, 0x445ef671)\nreportEvent(0x40000000, 0x445ef677)\nreportEvent(0x00000000, 0x445ef86a)\nreportEvent(0x40000000, 0x445efa63)\nreportEvent(0x44000000, 0x445efa80)\nreportEvent(0x04000000, 0x445efc5c)\nreportEvent(0x24000000, 0x445efc62)\nreportEvent(0x44000000, 0x445efe55)\nreportEvent(0x4c000000, 0x445efede)\nreportEvent(0x48000000, 0x445efee4)\nreportEvent(0x08000000, 0x445f004e)\nreportEvent(0x28000000, 0x445f0054)\nreportEvent(0x48000000, 0x445f0247)\nreportEvent(0x40000000, 0x445f02d0)\nreportEvent(0x20000000, 0x445f0aba)\nreportEvent(0x40000000, 0x445f0cad)\nreportEvent(0x00000000, 0x445f0ea6)\nreportEvent(0x20000000, 0x445f0eac)\nreportEvent(0x40000000, 0x445f109f)\nreportEvent(0x44000000, 0x445f10bc)\nreportEvent(0x24000000, 0x445f129d)\nreportEvent(0x64000000, 0x445f1490)\nreportEvent(0x44000000, 0x445f1496)\nreportEvent(0x64000000, 0x4458d598)\nreportEvent(0x44000000, 0x445f14b5)\nreportEvent(0x40000000, 0x445f14bb)\nreportEvent(0x00000000, 0x445f1689)\nreportEvent(0x60000000, 0x445f1882)\nreportEvent(0x40000000, 0x445f1888)\nreportEvent(0x44000000, 0x445f189f)\nreportEvent(0x04000000, 0x445f1a7b)\nreportEvent(0x44000000, 0x445f1c74)\nreportEvent(0x04000000, 0x445f1e6d)\nreportEvent(0x24000000, 0x445f1e73)\nreportEvent(0x44000000, 0x445f2066)\nreportEvent(0x44000000, 0x445f2089)\n"
  },
  {
    "path": "examples/fmcomms1/testfmcomms1.cpp",
    "content": "/* Copyright (c) 2014 Quanta Research Cambridge, Inc\n *\n * Permission is hereby granted, free of charge, to any person obtaining a\n * copy of this software and associated documentation files (the \"Software\"),\n * to deal in the Software without restriction, including without limitation\n * the rights to use, copy, modify, merge, publish, distribute, sublicense,\n * and/or sell copies of the Software, and to permit persons to whom the\n * Software is furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n * DEALINGS IN THE SOFTWARE.\n */\n#include <sys/mman.h>\n#include <assert.h>\n#include \"dmaManager.h\"\n#include \"FMComms1Request.h\"\n#include \"FMComms1Indication.h\"\n#include \"BlueScopeEventPIORequest.h\"\n#include \"BlueScopeEventPIOIndication.h\"\n#include \"fmci2c.h\"\n\nsem_t read_sem;\nsem_t write_sem;\nsem_t cv_sem;\n\nint readBurstLen = 16;\nint writeBurstLen = 16;\n\n#define WHERE(x) fprintf(stdout, \"at %s:%d\\n\",__FILE__, __LINE__)\n\n#ifndef SIMULATION\nint numWords = 0x4096; // make sure to allocate at least one entry of each size\n#else\nint numWords = 0x4096;\n#endif\n\nsize_t test_sz  = numWords*sizeof(unsigned int);\nsize_t alloc_sz = test_sz;\n\nclass FMComms1Indication : public FMComms1IndicationWrapper\n{\n\npublic:\n  FMComms1Indication(unsigned int id) : FMComms1IndicationWrapper(id){}\n\n  virtual void readStatus(unsigned iterCount, unsigned running){\n    fprintf(stdout, \"read %d %d\\n\", iterCount, running);\n    sem_post(&read_sem);\n  }\n  virtual void writeStatus(unsigned iterCount, unsigned running){\n    fprintf(stdout, \"write %d %d\\n\", iterCount, running);\n    sem_post(&write_sem);\n  }\n};\n\n#define NUMEVENTS 4096\nuint32_t counter_value = 0;\nuint32_t events[NUMEVENTS];\nuint32_t timestamps[NUMEVENTS];\nint eventcount = 0;\n\nclass BlueScopeEventPIOIndication : public BlueScopeEventPIOIndicationWrapper\n{\npublic:\n  BlueScopeEventPIOIndication(unsigned int id) : BlueScopeEventPIOIndicationWrapper(id){}\n\n  virtual void reportEvent(uint32_t v, uint32_t timestamp ){\n    if (eventcount < NUMEVENTS) {\n      events[eventcount] = v;\n      timestamps[eventcount] = timestamp;\n      eventcount += 1;\n    }\n  }\n  virtual void counterValue(uint32_t v){\n    counter_value = v;\n    sem_post(&cv_sem);\n    fprintf(stdout, \"BlueScopeEventPIO::counterValue value=%u\\n\", v);\n    \n  }\n};\n\n\nint main(int argc, const char **argv)\n{\n  int i;\n  int srcAlloc;\n  int dstAlloc;\n  unsigned int *srcBuffer = 0;\n  unsigned int *dstBuffer = 0;\n\n\n  FMComms1RequestProxy *device = 0;\n  FMComms1Indication *deviceIndication = 0;\n  BlueScopeEventPIORequestProxy *bluescope = 0;\n  BlueScopeEventPIOIndication *bluescopeIndication = 0;\n\n  fprintf(stdout, \"Main::%s %s\\n\", __DATE__, __TIME__);\n\n  if(sem_init(&cv_sem, 1, 0)){\n    fprintf(stdout, \"failed to init cv_sem\\n\");\n    exit(1);\n  }\n\n  if(sem_init(&read_sem, 1, 0)){\n    fprintf(stdout, \"failed to init read_sem\\n\");\n    exit(1);\n  }\n\n  if(sem_init(&write_sem, 1, 0)){\n    fprintf(stdout, \"failed to init write_sem\\n\");\n    exit(1);\n  }\n\n  device = new FMComms1RequestProxy(IfcNames_FMComms1Request);\n  DmaManager *dma = platformInit();\n  deviceIndication = new FMComms1Indication(IfcNames_FMComms1Indication);\n  bluescope = new BlueScopeEventPIORequestProxy(IfcNames_BlueScopeEventPIORequest);\n  bluescopeIndication = new BlueScopeEventPIOIndication(IfcNames_BlueScopeEventPIOIndication);\n\n  fprintf(stdout, \"Main::allocating memory...\\n\");\n  srcAlloc = portalAlloc(alloc_sz, 0);\n\n  srcBuffer = (unsigned int *)portalMmap(srcAlloc, alloc_sz);\n  if ((char *) srcBuffer == MAP_FAILED) perror(\"srcBuffer mmap failed\");\n  assert ((char *) srcBuffer != MAP_FAILED);\n\n  dstAlloc = portalAlloc(alloc_sz, 0);\n\n  dstBuffer = (unsigned int *)portalMmap(dstAlloc, alloc_sz);\n  if ((char *) dstBuffer == MAP_FAILED) perror(\"dstBuffer mmap failed\");\n  assert ((char *) dstBuffer != MAP_FAILED);\n\n  int status;\n  status = setClockFrequency(0, 100000000, 0);\n  /* FMComms1 refclk should be 30 MHz */\n  status = setClockFrequency(1,  30000000, 0);\n    \n  portalCacheFlush(srcAlloc, srcBuffer, alloc_sz, 1);\n  portalCacheFlush(dstAlloc, dstBuffer, alloc_sz, 1);\n  fprintf(stdout, \"Main::flush and invalidate complete\\n\");\n\n  bluescope->doReset();\n  WHERE();\n  bluescope->setTriggerMask (0xFFFFFFFF);\n  WHERE();\n  bluescope->getCounterValue();\n  WHERE();\n  bluescope->enableIndications(1);\n  WHERE();\n  sem_wait(&cv_sem);\n  fprintf(stdout, \"Main::initial BlueScopeEventPIO counterValue: %d\\n\", counter_value);\n\n  device->getReadStatus();\n  device->getWriteStatus();\n  sem_wait(&read_sem);\n  sem_wait(&write_sem);\n  fprintf(stdout, \"Main::after getStateDbg\\n\");\n\n  unsigned int ref_srcAlloc = dma->reference(srcAlloc);\n  fprintf(stdout, \"ref_srcAlloc=%d\\n\", ref_srcAlloc);\n  unsigned int ref_dstAlloc = dma->reference(dstAlloc);\n  fprintf(stdout, \"ref_dstAlloc=%d\\n\", ref_dstAlloc);\n\n  fprintf(stdout, \"Main::starting read %08x\\n\", numWords);\n\n  device->startRead(ref_srcAlloc, numWords, readBurstLen, 1);\n  device->startWrite(ref_dstAlloc, numWords, writeBurstLen, 1);\n  sem_wait(&read_sem);\n\n\n\n   sleep(5);\n  device->getReadStatus();\n  device->getWriteStatus();\n  sem_wait(&read_sem);\n  sem_wait(&write_sem);\n   sleep(5);\n  fprintf(stdout, \"Main::stopping reads\\n\");\n  device->startRead(ref_srcAlloc, numWords, readBurstLen, 0);\n  fprintf(stdout, \"Main::stopping writes\\n\");\n  device->startWrite(ref_dstAlloc, numWords, writeBurstLen, 0);\n  device->getReadStatus();\n  device->getWriteStatus();\n  sem_wait(&read_sem);\n  sem_wait(&write_sem);\n  testi2c(\"/dev/i2c-1\", 0x58);\n\n  bluescope->getCounterValue();\n  fprintf(stdout, \"Main::getCounter\\n\");\n \n  sem_wait(&cv_sem);\n  \n  fprintf(stdout, \"Main::final BlueScopeEventPIO counterValue: %d\\n\", counter_value);\n  fprintf(stdout, \"received %d events\\n\", eventcount);\n  for (i = 0; i < eventcount; i += 1) {\n      fprintf(stdout, \"reportEvent(0x%08x, 0x%08x)\\n\", events[i], timestamps[i]);\n  }\n\n  exit(0);\n}\n"
  },
  {
    "path": "examples/fmcomms1/testi2c.c",
    "content": "/* Copyright (c) 2014 Quanta Research Cambridge, Inc\n *\n * Permission is hereby granted, free of charge, to any person obtaining a\n * copy of this software and associated documentation files (the \"Software\"),\n * to deal in the Software without restriction, including without limitation\n * the rights to use, copy, modify, merge, publish, distribute, sublicense,\n * and/or sell copies of the Software, and to permit persons to whom the\n * Software is furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n * DEALINGS IN THE SOFTWARE.\n */\n/* copied from jca's i2chdmi.h */\n\n#include <linux/types.h>\n#include <fcntl.h>\n#include <sys/ioctl.h>\n#include <errno.h>\n#include \"/usr/include/linux/i2c.h\"\n#include \"/usr/include/linux/i2c-dev.h\"\n#include <stdio.h>\n#include <stdlib.h>\n#include <string.h>\n\n\n\nint fmcomms1_read_eeprom(int fd, int device, unsigned char *datap, int size)\n{\n  int status;\n  int i;\n  struct i2c_msg msgs[2];\n  unsigned char command[2] = { 0, 0 };\n  struct i2c_rdwr_ioctl_data arg;\n  msgs[0].addr = device;\n  msgs[0].flags = 0;\n  msgs[0].len = 1;\n  msgs[0].buf = &command[0];\n  msgs[1].addr = device;\n  msgs[1].flags = I2C_M_RD;\n  msgs[1].len = 1;\n  msgs[1].buf = datap;\n  arg.msgs = msgs;\n  arg.nmsgs = 1;\n  datap[0] = 1;\n  status = ioctl(fd, I2C_RDWR, &arg);\n  if (status != 0) {\n    fprintf(stderr, \"[%s:%d]: ioctl I2C_RW write status=%d errno=%d [%s]\\n\", __FILE__, __LINE__, status, errno, strerror(errno));\n  }\n  msgs[0] = msgs[1];\n  for (i = 0; i < 16; i += 1) {\n    msgs[0].buf = &datap[i];\n    status = ioctl(fd, I2C_RDWR, &arg);\n    if (status != 0) {\n      fprintf(stderr, \"[%s:%d]: loop %d ioctl I2C_RW read status=%d errno=%d [%]\\n\", __FILE__, __LINE__, i, status, errno, strerror(errno));\n    }\n  }\n  return status;\n}\n\nint fmcomms1_get_version(int fd, int device, unsigned char *datap, int size)\n{\n  int status;\n  struct i2c_msg msgs[2];\n  unsigned char command = 1;\n  struct i2c_rdwr_ioctl_data arg;\n  msgs[0].addr = device;\n  msgs[0].flags = 0;\n  msgs[0].len = 1;\n  msgs[0].buf = &command;\n  msgs[1].addr = device;\n  msgs[1].flags = I2C_M_RD | I2C_M_RECV_LEN;\n  msgs[1].len = 33;\n  msgs[1].buf = datap;\n  arg.msgs = msgs;\n  arg.nmsgs = 2;\n  datap[0] = 1;\n  status = ioctl(fd, I2C_RDWR, &arg);\n  if (status != 0) {\n    fprintf(stderr, \"[%s:%d]: ioctl I2C_RW write status=%d errno=%d [%s]\\n\", __FILE__, __LINE__, status, errno, strerror(errno));\n  }\n  msgs[0] = msgs[1];\n  status = ioctl(fd, I2C_RDWR, &arg);\n  if (status != 0) {\n    fprintf(stderr, \"[%s:%d]: ioctl I2C_RW read status=%d errno=%d [%s]\\n\", __FILE__, __LINE__, status, errno, strerror(errno));\n  }\n  return status;\n}\n\n\nunsigned char version_data[128];\nint main(int argc, char *argv[])\n{\n   \n\n  int fd;\n    int i;\n    int res;\n    printf(\"argv[1] is %s, argv[2] is 0x%02lx\\n\", argv[1], strtol(argv[2], NULL, 0));\n    fd = open(argv[1], O_RDWR);\n    if (fd < 0) {\n      printf(\"[%s:%d] open failed\\n\", __FILE__, __LINE__);\n      exit(1);\n    }\n    // start version query\n    memset(version_data, 0, 128);\n    res = fmcomms1_read_eeprom(fd, 0x50, version_data, 128);\n    printf (\"getversion result %d\\n\", res);\n    for (i = 0; i < 16; i += 1) {\n      if ((i != 0) && ((i % 16) == 0)) printf(\"\\n\");\n      printf(\" %2x\", version_data[i]);\n    }\n    printf(\"\\n\");\n    memset(version_data, 0, 128);\n    res = fmcomms1_get_version(fd, (int) strtol(argv[2], NULL, 0), version_data, 128);\n    printf (\"getversion result %d\\n\", res);\n    for (i = 0; i < 32; i += 1) {\n      if ((i != 0) && ((i % 16) == 0)) printf(\"\\n\");\n      printf(\" %2x\", version_data[i]);\n    }\n    printf(\"\\n\");\n}\n"
  },
  {
    "path": "examples/gyro_simple/Makefile",
    "content": "CONNECTALDIR ?= ../..\nS2H_INTERFACES = GyroCtrlRequest:GyroController.req\nH2S_INTERFACES = GyroController:GyroCtrlIndication\nMEM_WRITE_INTERFACES = cons\\(lGyroController.dmaClient,nil\\)\nINTERFACES = GyroSampleStream\n\nAUTOTOP = --interface pins:GyroController.pins --portname IfcNames_GyroSampleStream\nZBR = $(CONNECTALDIR)/lib/zedboard_robot\nBSVFILES = $(ZBR)/bsv/GyroController.bsv\nCPPFILES = test_gyro.cpp $(ZBR)/cpp/read_buffer.cpp\n\nPIN_TYPE = GyroSimplePins\nPIN_TYPE_INCLUDE = GyroController\nPINOUT_FILE = pinout.json\nPIN_BINDINGS = pmod:pmodd\n\ninclude $(CONNECTALDIR)/Makefile.connectal\n"
  },
  {
    "path": "examples/gyro_simple/clock.tcl",
    "content": "## disconnect unused CLK and RST ports inserted by bsc\nforeach {pat} {CLK_GATE_* CLK_clock} {\n    foreach {net} [get_nets $pat] {\n\tputs \"disconnecting net $net\"\n\tdisconnect_net -net $net -objects [get_pins -of_objects $net]\n    }\n}\n"
  },
  {
    "path": "examples/gyro_simple/gyro.h",
    "content": "\n// Copyright (c) 2014 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\n#define WHO_AM_I        0x0F\n#define CTRL_REG1       0x20\n#define CTRL_REG2       0x21\n#define CTRL_REG3       0x22\n#define CTRL_REG4       0x23\n#define CTRL_REG5       0x24\n#define REFERENCE       0x25\n#define OUT_TEMP        0x26\n#define STATUS_REG      0x27\n#define OUT_X_L         0x28\n#define OUT_X_H         0x29\n#define OUT_Y_L         0x2A\n#define OUT_Y_H         0x2B\n#define OUT_Z_L         0x2C\n#define OUT_Z_H         0x2D\n#define FIFO_CTRL_REG   0x2E\n#define FIFO_SRC_REG    0x2F\n#define INT1_CFG        0x30\n#define INT1_SRC        0x31\n#define INT1_THS_XH     0x32\n#define INT1_THS_XL     0x33\n#define INT1_THS_YH     0x34\n#define INT1_THS_YL     0x35\n#define INT1_THS_ZH     0x36\n#define INT1_THS_ZL     0x37\n#define INT1_DURATION   0x38\n\n\n"
  },
  {
    "path": "examples/gyro_simple/gyroVisualize.py",
    "content": "##\n## Copyright (c) 2013-2014 Quanta Research Cambridge, Inc.\n\n## Permission is hereby granted, free of charge, to any person\n## obtaining a copy of this software and associated documentation\n## files (the \"Software\"), to deal in the Software without\n## restriction, including without limitation the rights to use, copy,\n## modify, merge, publish, distribute, sublicense, and/or sell copies\n## of the Software, and to permit persons to whom the Software is\n## furnished to do so, subject to the following conditions:\n\n## The above copyright notice and this permission notice shall be\n## included in all copies or substantial portions of the Software.\n\n## THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n## EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n## MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n## NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n## BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n## ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n## CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n## SOFTWARE.\n\nfrom visual import *\n\nclass gv:\n    def __init__(self):\n        self.roll_bar = []\n        self.pitch_bar = []\n        self.main_window=display(title=\"Board Orientation\", forward = (1,0,-0.25), width=500, up=(0,0,1), y=200, range=(1.2,1.2,1.2))\n        self.aux_window = display(title='Roll/Pitch/Yaw',x=0, y=0, width=500, height=200,center=(0,0,0), background=(0,0,0), range=(1,1,1))\n\n        self.aux_window.select()\n        self.roll_bar.append(cylinder(pos=(-0.4,0,0),axis=(0.2,0,0),radius=0.01,color=color.red))\n        self.roll_bar.append(cylinder(pos=(-0.4,0,0),axis=(-0.2,0,0),radius=0.01,color=color.red))\n        self.pitch_bar.append(cylinder(pos=(0.1,0,0),axis=(0.2,0,0),radius=0.01,color=color.green))\n        self.pitch_bar.append(cylinder(pos=(0.1,0,0),axis=(-0.2,0,0),radius=0.01,color=color.green))\n        self.yaw_arrow = arrow(pos=(0.6,0,0),color=color.cyan,axis=(-0.2,0,0), shaftwidth=0.02, fixedwidth=1)\n\n        label(pos=(-0.4,0.3,0),text=\"Roll\",box=0,opacity=0)\n        label(pos=(0.1,0.3,0),text=\"Pitch\",box=0,opacity=0)\n        label(pos=(0.55,0.3,0),text=\"Yaw\",box=0,opacity=0)\n        label(pos=(0.6,0.22,0),height=8,text=\"N\",box=0,opacity=0,color=color.yellow)\n        label(pos=(0.6,-0.22,0),height=8,text=\"S\",box=0,opacity=0,color=color.yellow)\n        label(pos=(0.38,0,0),height=8,text=\"W\",box=0,opacity=0,color=color.yellow)\n        label(pos=(0.82,0,0),height=8,text=\"E\",box=0,opacity=0,color=color.yellow)\n\n        self.main_window.select()\n        arrow(color=color.green,axis=(1,0,0), shaftwidth=0.02, fixedwidth=1)\n        arrow(color=color.green,axis=(0,-1,0), shaftwidth=0.02 , fixedwidth=1)\n        arrow(color=color.green,axis=(0,0,-1), shaftwidth=0.02, fixedwidth=1)\n        label(pos=(0,0,0.8),text=\"Board Orientation\",box=0,opacity=0)\n        label(pos=(1,0,0),text=\"X\",box=0,opacity=0)\n        label(pos=(0,-1,0),text=\"Y\",box=0,opacity=0)\n        label(pos=(0,0,-1),text=\"Z\",box=0,opacity=0)\n        self.platform = box(length=1, height=0.05, width=1, color=color.red)\n        self.p_line = box(length=1,height=0.08,width=0.1,color=color.yellow)\n        self.plat_arrow = arrow(color=color.green,axis=(1,0,0), shaftwidth=0.06, fixedwidth=1)\n\n    def update(self, direction, sampling_period):\n        (roll,pitch,yaw) = direction\n        axis=(cos(pitch)*cos(yaw),-cos(pitch)*sin(yaw),sin(pitch)) \n        up=(sin(roll)*sin(yaw)+cos(roll)*sin(pitch)*cos(yaw),sin(roll)*cos(yaw)-cos(roll)*sin(pitch)*sin(yaw),-cos(roll)*cos(pitch))\n        self.platform.axis=axis\n        self.platform.up=up\n        self.platform.length=1.0\n        self.platform.width=0.65\n        self.plat_arrow.axis=axis\n        self.plat_arrow.up=up\n        self.plat_arrow.length=0.8\n        self.p_line.axis=axis\n        self.p_line.up=up\n        self.roll_bar[0].axis=(-0.2*cos(roll),0.2*sin(roll),0)\n        self.roll_bar[1].axis=(0.2*cos(roll),-0.2*sin(roll),0)\n        self.pitch_bar[0].axis=(-0.2*cos(pitch),0.2*sin(pitch),0)\n        self.pitch_bar[1].axis=(0.2*cos(pitch),-0.2*sin(pitch),0)\n        self.yaw_arrow.axis=(0.2*sin(yaw),0.2*cos(yaw),0)\n        rate(sampling_period)\n\n\n\nif __name__ == \"__main__\":\n    v = gv()\n    for i in range(1,1000):\n        v.update(i,i,i)\n        time.sleep(0.01)\n"
  },
  {
    "path": "examples/gyro_simple/gyro_simple.h",
    "content": "\n// Copyright (c) 2014 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\n\n#include <stdio.h>\n#include <stdlib.h>\n#include <unistd.h>\n#include <assert.h>\n#include <string.h>\n#include <pthread.h>\n#include <netdb.h>\n#include <netinet/in.h>\n#include <signal.h>\n\n#include \"GyroCtrlRequest.h\"\n#include \"GyroCtrlIndication.h\"\n#include \"GeneratedTypes.h\"\n#include \"GyroSampleStream.h\"\n#include \"gyro.h\"\n\n\nclass GyroCtrlIndication : public GyroCtrlIndicationWrapper\n{\n public:\n  sem_t status_sem;\n  sem_t read_sem;\n  sem_t write_sem;\n  uint32_t read_reg_val;\n  uint32_t write_addr;\n  int write_wrap_cnt;\n\n  GyroCtrlIndication(int id) : GyroCtrlIndicationWrapper(id) {\n    sem_init(&status_sem,1,0);\n    sem_init(&read_sem,1,0);\n    sem_init(&write_sem,1,0);\n    write_addr = 0;\n    write_wrap_cnt = 0;\n  }\n  virtual void read_reg_resp ( const uint8_t v){\n    //fprintf(stderr, \"GyroCtrlIndication::read_reg_resp(v=%x)\\n\", v);\n    read_reg_val = v;\n    sem_post(&read_sem);\n  }\n  virtual void write_reg_resp ( const uint8_t v){\n    //fprintf(stderr, \"GyroCtrlIndication::write_reg_resp(v=%x)\\n\", v);\n    sem_post(&write_sem);\n  }\n  virtual void memwrite_status(const uint32_t addr, const uint32_t wrap_cnt){\n    //fprintf(stderr, \"GyroCtrlIndication::memwrite_status(addr=%08x, wrap_cnt=%d)\\n\", addr, wrap_cnt);\n    write_addr = addr;\n    write_wrap_cnt = wrap_cnt;\n    sem_post(&status_sem);\n  }\n};\n\nvoid read_reg(GyroCtrlIndication *ind, GyroCtrlRequestProxy *device, unsigned short addr)\n{\n  device->read_reg_req(addr);\n  sem_wait(&(ind->read_sem));\n}\n\nvoid write_reg(GyroCtrlIndication *ind, GyroCtrlRequestProxy *device, unsigned short addr, unsigned short val)\n{\n  device->write_reg_req(addr,val);\n  sem_wait(&(ind->write_sem));\n}\n\nvoid set_en(GyroCtrlIndication *ind, GyroCtrlRequestProxy *device, unsigned int v)\n{\n  device->set_en(v);\n  if(!v) sem_wait(&(ind->status_sem));\n}\n\nint send(GyroSampleStreamProxy *gssp, void*b, int len, int drop, int spew, int send)\n{\n  int16_t *ss = (int16_t*)b;\n  int i = 3+drop;\n  while(i < len/2){\n    if (send) gssp->sample(ss[(i-3)+0], ss[(i-3)+1], ss[(i-3)+2]);\n    if (spew) fprintf(stderr, \"%8d %8d %8d\\n\", ss[(i-3)+0], ss[(i-3)+1], ss[(i-3)+2]);\n    i+=3;\n  }\n  int missing = i-(len/2);\n  return missing;\n}\n\n//#define HIGH_SAMPLE_RATE\nvoid setup_registers(GyroCtrlIndication *ind, GyroCtrlRequestProxy *device, int ref_dstAlloc, int alloc_sz)\n{\n#ifdef HIGH_SAMPLE_RATE\n  write_reg(ind,device, CTRL_REG1, 0b11001111);  // ODR:800Hz Cutoff:30\n#else\n  write_reg(ind,device, CTRL_REG1, 0b00001111);  // ODR:100Hz Cutoff:12.5\n#endif\n  write_reg(ind,device, CTRL_REG2, 0b00000000);\n  write_reg(ind,device, CTRL_REG3, 0b00000000);\n  write_reg(ind,device, CTRL_REG4, 0b10100000);  // BDU:1, Range:2000 dps\n  write_reg(ind,device, CTRL_REG5, 0b00000000);\n  // make sure the memwrite is disabled before we start\n  set_en(ind,device,0); \n#ifdef SIMULATION\n  device->sample(ref_dstAlloc, alloc_sz, 10);\n#else\n#ifdef HIGH_SAMPLE_RATE\n  // sampling rate of 800Hz. Model running at 100 MHz. \n  device->sample(ref_dstAlloc, alloc_sz, 1000000/8);\n#else\n  // sampling rate of 100Hz. Model running at 100 MHz. \n  device->sample(ref_dstAlloc, alloc_sz, 1000000);\n#endif\n#endif\n}\n\n\n"
  },
  {
    "path": "examples/gyro_simple/pinout.json",
    "content": "{\n    \"spi_mosi\": {\n\t\"PIO_DIRECTION\": \"OUTPUT\",\n\t\"pmod\": \"J2\"\n    },\n    \"spi_miso_v\": {\n\t\"PIO_DIRECTION\": \"INPUT\",\n\t\"pmod\": \"J3\"\n    },\n    \"spi_sel_n\": {\n\t\"PIO_DIRECTION\": \"OUTPUT\",\n\t\"pmod\": \"J1\"\n    },\n    \"CLK_spi_clock\": {\n\t\"PIO_DIRECTION\": \"OUTPUT\",\n\t\"pmod\": \"J4\"\n    },\n\n    \"leds_leds[0]\" : {\n\t\"PIO_DIRECTION\": \"OUTPUT\",\n\t\"leds\" : \"L0\"\n    },\n    \"leds_leds[1]\" : {\n\t\"PIO_DIRECTION\": \"OUTPUT\",\n\t\"leds\" : \"L1\"\n    },\n    \"leds_leds[2]\" : {\n\t\"PIO_DIRECTION\": \"OUTPUT\",\n\t\"leds\" : \"L2\"\n    },\n    \"leds_leds[3]\" : {\n\t\"PIO_DIRECTION\": \"OUTPUT\",\n\t\"leds\" : \"L3\"\n    },\n    \"leds_leds[4]\" : {\n\t\"PIO_DIRECTION\": \"OUTPUT\",\n\t\"leds\" : \"L4\"\n    },\n    \"leds_leds[5]\" : {\n\t\"PIO_DIRECTION\": \"OUTPUT\",\n\t\"leds\" : \"L5\"\n    },\n    \"leds_leds[6]\" : {\n\t\"PIO_DIRECTION\": \"OUTPUT\",\n\t\"leds\" : \"L6\"\n    },\n    \"leds_leds[7]\" : {\n\t\"PIO_DIRECTION\": \"OUTPUT\",\n\t\"leds\" : \"L7\"\n    }\n}\n\n\n"
  },
  {
    "path": "examples/gyro_simple/test_gyro.cpp",
    "content": "\n// Copyright (c) 2014 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n#include <netdb.h>\n#include <netinet/in.h>\n#include <signal.h>\n#include \"dmaManager.h\"\n#include \"sock_utils.h\"\n#include \"GyroSampleStream.h\"\n#include \"gyro_simple.h\"\n#include \"read_buffer.h\"\n\nstatic int spew = 1;\nstatic int host_sw = 1;\n#ifdef SIMULATION\nstatic int alloc_sz = 1<<7;\n#else\nstatic int alloc_sz = 1<<10;\n#endif\n\nint main(int argc, const char **argv)\n{\n  // this is because I don't want the server to abort when the client goes offline\n  signal(SIGPIPE, SIG_IGN); \n\n  GyroCtrlIndication *ind = new GyroCtrlIndication(IfcNames_GyroCtrlIndicationH2S);\n  GyroCtrlRequestProxy *device = new GyroCtrlRequestProxy(IfcNames_GyroCtrlRequestS2H);\n  DmaManager *dma = platformInit();\n\n  PortalSocketParam param;\n  getaddrinfo(\"0.0.0.0\", \"5000\", NULL, &param.addr);\n  GyroSampleStreamProxy *gssp = new GyroSampleStreamProxy(IfcNames_GyroSampleStream, &transportSocketResp, &param, &GyroSampleStreamJsonProxyReq, 1000);\n\n  int dstAlloc = portalAlloc(alloc_sz, 0);\n  char *dstBuffer = (char *)portalMmap(dstAlloc, alloc_sz);\n  unsigned int ref_dstAlloc = dma->reference(dstAlloc);\n\n  long req_freq = 100000000; // 100 mHz\n  long freq = 0;\n  setClockFrequency(0, req_freq, &freq);\n  fprintf(stderr, \"Requested FCLK[0]=%ld actually %ld\\n\", req_freq, freq);\n  \n  char* snapshot = (char*)malloc(alloc_sz);\n  reader* r = new reader();\n\n  // setup gyro registers and dma infra\n  setup_registers(ind,device, ref_dstAlloc, alloc_sz);  \n  int drop = 0;\n\n  while(true){\n#ifdef SIMULATION\n    sleep(5);\n#else\n    usleep(80000);\n#endif\n    set_en(ind,device, 0);\n    int datalen = r->read_circ_buff(alloc_sz, ref_dstAlloc, dstAlloc, dstBuffer, snapshot, ind->write_addr, ind->write_wrap_cnt); \n    set_en(ind,device, 2);\n    drop = send(gssp, snapshot, datalen, drop, spew, host_sw);\n  }\n}\n"
  },
  {
    "path": "examples/gyro_simple/test_gyro.py",
    "content": "#!/usr/bin/env python3\n\n# Copyright (c) 2013 Quanta Research Cambridge, Inc.\n\n# Permission is hereby granted, free of charge, to any person\n# obtaining a copy of this software and associated documentation\n# files (the \"Software\"), to deal in the Software without\n# restriction, including without limitation the rights to use, copy,\n# modify, merge, publish, distribute, sublicense, and/or sell copies\n# of the Software, and to permit persons to whom the Software is\n# furnished to do so, subject to the following conditions:\n\n# The above copyright notice and this permission notice shall be\n# included in all copies or substantial portions of the Software.\n\n# THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n# EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n# MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n# BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n# ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n# CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n# SOFTWARE.\n\nfrom __future__ import print_function\n\nimport sys\nimport socket\nimport struct\nimport time\nimport ctypes\nimport os\nimport numpy\nimport pandas as pd\nimport math\nfrom gyroVisualize import *\nimport argparse\nimport json\n\nsys.path.append(os.path.abspath('../../scripts'))\nimport portalJson\n\nclass gyro_stream:\n    def __init__(self, lpf=False):\n        self.times = 0\n        self.tails = [[],[],[]]\n        self.means = [0,0,0]\n        self.calibrate_window = 0\n        self.sample_freq_hz = 100\n        self.lpf = lpf\n\n    def radians(self, sample):\n        # sensitivity of sample is 70 milli-degrees-per-second/digit.  \n        # multiply sample by 70 to get milli-degrees-per-second                       \n        # divide by sample_freq_hz to get milli-degrees\n        # divide by 1000 to get degrees  \n        return (math.radians(sample[0]*70.0/self.sample_freq_hz/1000.0),\n                math.radians(-sample[1]*70.0/self.sample_freq_hz/1000.0),\n                math.radians(-sample[2]*70.0/self.sample_freq_hz/1000.0))\n\n    def next_samples(self,samples):\n        self.times = self.times+1\n        octave_length = 20\n        window_sz = 10\n        rv = []\n        write_octave = True\n        if (write_octave):\n            octave_file = open(\"x.m\", \"w\");\n            octave_file.write(\"#! /usr/bin/octave --persist \\nv = [\");\n        num_samples = len(samples)\n        if (self.lpf):\n            x = numpy.concatenate((self.tails[0],samples[0::3]),0)\n            y = numpy.concatenate((self.tails[1],samples[1::3]),0)\n            z = numpy.concatenate((self.tails[2],samples[2::3]),0)\n            xs = pd.rolling_mean(pd.Series(x),window=window_sz)[window_sz:]\n            ys = pd.rolling_mean(pd.Series(y),window=window_sz)[window_sz:]\n            zs = pd.rolling_mean(pd.Series(z),window=window_sz)[window_sz:]\n            self.tails[0] = x[-window_sz:]\n            self.tails[1] = y[-window_sz:]\n            self.tails[2] = z[-window_sz:]\n        else:\n            xs = samples[0::3]\n            ys = samples[1::3]\n            zs = samples[2::3]\n\n        if (self.times <= octave_length):\n            print(self.times)\n                \n        for x,y,z in zip(xs,ys,zs):\n            #print \"%d %d %d\" % (x,y,z)\n            if (self.times <= octave_length):\n                self.calibrate_window += 1\n                self.means[0] += x;\n                self.means[1] += y;\n                self.means[2] += z;\n                if (write_octave):\n                    octave_file.write(\"%d, %d, %d; \\n\" % (x,y,z));\n            else:\n                pos = (x-self.means[0],y-self.means[1],z-self.means[2])\n                rv.append(self.radians(pos))\n                #print \"%d %d %d\" %(pos[0],pos[1],pos[2])\n\n        if (self.times == octave_length):\n            for i in range (0,len(self.means)):\n                self.means[i] = self.means[i]/self.calibrate_window\n            print(\"x_mean:%d y_mean:%d, z_mean:%d\\n\" % (self.means[0],self.means[1],self.means[2]))\n            if (write_octave):\n                octave_file.write(\"];\\n\");\n                octave_file.write(\"plot(v(:,1),color=\\\"r\\\");\\n\");\n                octave_file.write(\"hold on;\\n\");\n                octave_file.write(\"plot(v(:,2),color=\\\"g\\\");\\n\");\n                octave_file.write(\"plot(v(:,3),color=\\\"b\\\");\\n\");\n                octave_file.close()\n                print(\"done writing octave_file\")\n\n        if (self.times > octave_length):\n            return rv\n\n                \nsmoothe = False\nif __name__ == \"__main__\":\n    argparser = argparse.ArgumentParser('Display gyroscope data')\n    argparser.add_argument('-v', '--visualize', help='Display gyro orientation in 3D rendering', default=False, action='store_true')\n    argparser.add_argument('-a', '--address', help='Device address', default=None)\n    options = argparser.parse_args()\n    spew = not options.visualize;\n    visualize = options.visualize;\n    print(options.address)\n    if not options.address:\n        options.address = os.environ['RUNPARAM']\n    if (visualize):\n        v  = gv()\n    gs = gyro_stream()\n    jp = portalJson.portal(options.address, 5000)\n    summ = [0,0,0]\n    try:\n        while (True):\n            samples = []\n            for i in range(0,48):\n                d = json.loads(jp.recv())\n                samples.append(d['x'])\n                samples.append(d['y'])\n                samples.append(d['z'])\n            poss = gs.next_samples(samples)\n            if poss is not None:\n                for pos in poss:\n                    if (spew): print(\"%f %f %f\" % (pos[0],pos[1],pos[2]))\n                    summ[0] = summ[0]+pos[0]\n                    summ[1] = summ[1]+pos[1]\n                    summ[2] = summ[2]+pos[2]\n                    if (visualize and smoothe):\n                        v.update(summ, gs.sample_freq_hz)\n                        time.sleep(1/gs.sample_freq_hz)\n                if (visualize and (not smoothe)):\n                    v.update(summ, gs.sample_freq_hz)\n                if (not spew): print(\"%f %f %f\" % (summ[0], summ[1], summ[2]))\n    except KeyboardInterrupt:\n        jp.shutdown()\n        sys.exit() \n\n\n\n\n\n"
  },
  {
    "path": "examples/gyrospi/Makefile",
    "content": "CONNECTALDIR ?= ../..\nS2H_INTERFACES = STestRequest:STest.request\nH2S_INTERFACES = STest:STestIndication\n\nBSVFILES = STest.bsv\nCPPFILES = testspi.cpp\n\nPIN_TYPE = STestPins\nPIN_TYPE_INCLUDE = STest\nPINOUT_FILE = pinout.json\nPIN_BINDINGS = pmod:pmodd\n\nAUTOTOP = --interface pins:STest.pins\n\ninclude $(CONNECTALDIR)/Makefile.connectal\n"
  },
  {
    "path": "examples/gyrospi/STest.bsv",
    "content": "// Copyright (c) 2015 The Connectal Project\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\nimport ConnectalSpi::*;\nimport GetPut::*;\n\ninterface STestRequest;\n   method Action request(Bit#(16) addr_data);\nendinterface\n\ninterface STestIndication;\n   method Action result(Bit#(16) val);\nendinterface\n\ninterface STestPins;\n   interface SpiMasterPins#(1) spi;\nendinterface\n\ninterface STest;\n   interface STestRequest request;\n   interface STestPins pins;\nendinterface\n\nmodule mkSTest#(STestIndication indication)(STest);\n   SPIMaster#(Bit#(16),1)  spiMaster <- mkSPIMaster(1000, True);\n   Reg#(Bool) inUse <- mkReg(False);\n   rule read_reg_resp;\n      let rv <- spiMaster.response[0].get;\n      indication.result(rv);\n      inUse <= False;\n   endrule\n      \n   interface STestRequest request;\n      method Action request(Bit#(16) addr_data) if (!inUse);\n         spiMaster.request[0].put(addr_data);\n         inUse <= True;\n      endmethod\n   endinterface\n   interface STestPins pins;\n       interface SpiMasterPins spi = spiMaster.pins;\n   endinterface\nendmodule\n"
  },
  {
    "path": "examples/gyrospi/gyro.h",
    "content": "// Copyright (c) 2014 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\n#define WHO_AM_I        0x0F\n#define CTRL_REG1       0x20\n#define CTRL_REG2       0x21\n#define CTRL_REG3       0x22\n#define CTRL_REG4       0x23\n#define CTRL_REG5       0x24\n#define REFERENCE       0x25\n#define OUT_TEMP        0x26\n#define STATUS_REG      0x27\n#define OUT_X_L         0x28\n#define OUT_X_H         0x29\n#define OUT_Y_L         0x2A\n#define OUT_Y_H         0x2B\n#define OUT_Z_L         0x2C\n#define OUT_Z_H         0x2D\n#define FIFO_CTRL_REG   0x2E\n#define FIFO_SRC_REG    0x2F\n#define INT1_CFG        0x30\n#define INT1_SRC        0x31\n#define INT1_THS_XH     0x32\n#define INT1_THS_XL     0x33\n#define INT1_THS_YH     0x34\n#define INT1_THS_YL     0x35\n#define INT1_THS_ZH     0x36\n#define INT1_THS_ZL     0x37\n#define INT1_DURATION   0x38\n"
  },
  {
    "path": "examples/gyrospi/pinout.json",
    "content": "{\n    \"spi_sel_n\": {\n\t\"PIO_DIRECTION\": \"OUTPUT\",\n\t\"pmod\": \"J1\"\n    },\n    \"spi_mosi\": {\n\t\"PIO_DIRECTION\": \"OUTPUT\",\n\t\"pmod\": \"J2\"\n    },\n    \"spi_miso_v\": {\n\t\"PIO_DIRECTION\": \"INPUT\",\n\t\"pmod\": \"J3\"\n    },\n    \"CLK_spi_clock\": {\n\t\"PIO_DIRECTION\": \"OUTPUT\",\n\t\"pmod\": \"J4\"\n    }\n}\n\n\n"
  },
  {
    "path": "examples/gyrospi/testspi.cpp",
    "content": "// Copyright (c) 2015 The Connectal Project\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n#include \"STestRequest.h\"\n#include \"STestIndication.h\"\n#include \"gyro.h\"\n#include <semaphore.h>\n\nstatic STestRequestProxy *device;\nstatic sem_t semp;\nstatic int indication_return_value;\n\nclass STestIndication: public STestIndicationWrapper {\npublic:\n    STestIndication(int id): STestIndicationWrapper(id) {}\n    void result(uint16_t val ) {\n        indication_return_value = val & 0xff;\n        sem_post(&semp);\n    }\n};\n\nint read_reg(int addr)\n{\n    device->request((addr << 8) | (1 << 15));\n    sem_wait(&semp);\n    printf(\"[%s:%d] addr %x = %x\\n\", __FUNCTION__, __LINE__, addr, indication_return_value);\n    return indication_return_value;\n}\nvoid write_reg(int addr, int data)\n{\n    device->request((addr << 8) | data);\n    sem_wait(&semp);\n}\n\nint main(int argc, const char **argv)\n{\n    STestIndication ind(IfcNames_STestIndicationH2S);\n    device = new STestRequestProxy(IfcNames_STestRequestS2H);\n    read_reg(WHO_AM_I);\n    //while(1)\n    //    read_reg(WHO_AM_I);\n    write_reg(CTRL_REG1, 0x0f);  // ODR:100Hz Cutoff:12.5\n    write_reg(CTRL_REG2, 0);\n    write_reg(CTRL_REG3, 0);\n    write_reg(CTRL_REG4, 0xa0);  // BDU:1, Range:2000 dps\n    write_reg(CTRL_REG5, 0);\n    sleep(1);\n    printf(\"[%s:%d] done\\n\", __FUNCTION__, __LINE__);\n    return 0;\n}\n"
  },
  {
    "path": "examples/hbridge_simple/Makefile",
    "content": "CONNECTALDIR ?= ../..\nS2H_INTERFACES = HBridgeCtrlRequest:HBridgeController.req\nH2S_INTERFACES = HBridgeController:HBridgeCtrlIndication\n\nZBLD = $(CONNECTALDIR)/lib/zedboard_robot/bsv\nBSVFILES = $(ZBLD)/HBridgeController.bsv\nCPPFILES= test_hbridge.cpp\n\nPIN_TYPE = HBridgeSimplePins\nPIN_TYPE_INCLUDE = HBridgeController\nPINOUT_FILE = pinout.json\nPIN_BINDINGS = pmod:pmodc\nAUTOTOP = --interface pins:HBridgeController.pins\n\ninclude $(CONNECTALDIR)/Makefile.connectal\n"
  },
  {
    "path": "examples/hbridge_simple/hbridge_simple.h",
    "content": "\n// Copyright (c) 2014 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\n\n#include \"HBridgeCtrlIndication.h\"\n#include \"GeneratedTypes.h\"\n\nuint8_t direction[2];\nuint16_t power[2];\n\n#define RIGHT 1\n#define LEFT  0\n\n#define CW   0\n#define CCW  1\n\n#define POWER_0  0x0000\n#define POWER_1  0x0200\n#define POWER_2  0x0400\n#define POWER_3  0x0500\n#define POWER_4  0x0600\n#define POWER_5  0x0680\n#define POWER_6  0x0700\n#define POWER_7  0x0780\n#define POWER_8  0x07FF\n\n#define STOP {power[RIGHT] = POWER_0;  power[LEFT] = POWER_0; device->ctrl(power,direction);}\n#define MOVE_FOREWARD(p) { direction[RIGHT] = CW;  direction[LEFT]  = CCW; power[RIGHT] = (p); power[LEFT] = (p); device->ctrl(power,direction);}\n#define MOVE_BACKWARD(p) { direction[RIGHT] = CCW; direction[LEFT]  = CW;  power[RIGHT] = (p); power[LEFT] = (p); device->ctrl(power,direction);}\n#define TURN_RIGHT(p)    { direction[RIGHT] = CCW; direction[LEFT]  = CCW; power[RIGHT] = (p); power[LEFT] = (p); device->ctrl(power,direction);}\n#define TURN_LEFT(p)     { direction[RIGHT] = CW;  direction[LEFT]  = CW;  power[RIGHT] = (p); power[LEFT] = (p); device->ctrl(power,direction);}\n\n\nclass HBridgeCtrlIndication : public HBridgeCtrlIndicationWrapper\n{\nprivate:\n  int hbc_event_cnt;\npublic:\n  HBridgeCtrlIndication(int id) : HBridgeCtrlIndicationWrapper(id), hbc_event_cnt(0){}\n  virtual void hbc_event( uint32_t e){\n    hbc_event_cnt++;\n    fprintf(stderr, \"(%d) hbc_event: {\", hbc_event_cnt);\n    if (e & (1 << HBridgeCtrlEvent_Started))\n      fprintf(stderr, \"Started\");\n    if (e & (1 << HBridgeCtrlEvent_Stopped))\n      fprintf(stderr, \"Stopped\");\n    fprintf(stderr, \"}\\n\");\n  }\n};\n"
  },
  {
    "path": "examples/hbridge_simple/pinout.json",
    "content": "{\n    \"hbridge_hbridge0_direction\" : {\n\t\"PIO_DIRECTION\": \"OUTPUT\",\n\t\"pmod\" : \"J1\"\n    },\n    \"hbridge_hbridge0_enabled\" : {\n\t\"PIO_DIRECTION\": \"OUTPUT\",\n\t\"pmod\" : \"J2\"\n    },\n    \"hbridge_hbridge1_direction\" : { \n\t\"PIO_DIRECTION\": \"OUTPUT\",\n\t\"pmod\" : \"J7\"\n    },\n    \"hbridge_hbridge1_enabled\" : { \n\t\"PIO_DIRECTION\": \"OUTPUT\",\n\t\"pmod\" : \"J8\"\n    },\n\n    \"leds_leds[0]\" : {\n\t\"PIO_DIRECTION\": \"OUTPUT\",\n\t\"leds\" : \"L0\"\n    },\n    \"leds_leds[1]\" : {\n\t\"PIO_DIRECTION\": \"OUTPUT\",\n\t\"leds\" : \"L1\"\n    },\n    \"leds_leds[2]\" : {\n\t\"PIO_DIRECTION\": \"OUTPUT\",\n\t\"leds\" : \"L2\"\n    },\n    \"leds_leds[3]\" : {\n\t\"PIO_DIRECTION\": \"OUTPUT\",\n\t\"leds\" : \"L3\"\n    },\n    \"leds_leds[4]\" : {\n\t\"PIO_DIRECTION\": \"OUTPUT\",\n\t\"leds\" : \"L4\"\n    },\n    \"leds_leds[5]\" : {\n\t\"PIO_DIRECTION\": \"OUTPUT\",\n\t\"leds\" : \"L5\"\n    },\n    \"leds_leds[6]\" : {\n\t\"PIO_DIRECTION\": \"OUTPUT\",\n\t\"leds\" : \"L6\"\n    },\n    \"leds_leds[7]\" : {\n\t\"PIO_DIRECTION\": \"OUTPUT\",\n\t\"leds\" : \"L7\"\n    }\n}\n\n\n"
  },
  {
    "path": "examples/hbridge_simple/test_hbridge.cpp",
    "content": "\n// Copyright (c) 2014 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n#include \"HBridgeCtrlRequest.h\"\n#include \"hbridge_simple.h\" \n\nint main(int argc, const char **argv)\n{\n  HBridgeCtrlIndication ind(IfcNames_HBridgeCtrlIndicationH2S);\n  HBridgeCtrlRequestProxy *device = new HBridgeCtrlRequestProxy(IfcNames_HBridgeCtrlRequestS2H);\n  sleep(2);\n\n  for(int i = 0; i < 2; i++){\n    MOVE_FOREWARD(POWER_5);\n    usleep(1000000);\n    STOP;\n    \n    MOVE_BACKWARD(POWER_5);\n    usleep(1000000);\n    STOP;\n    \n    TURN_RIGHT(POWER_5);\n    usleep(1000000);\n    STOP;\n    \n    TURN_LEFT(POWER_5);\n    usleep(1000000);\n    STOP;\n    sleep(1);\n  }\n}\n"
  },
  {
    "path": "examples/hdmidisplay/BsimHdmi.cpp",
    "content": "// Copyright (c) 2014 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\n#include <stdio.h>\n#include <stdlib.h>\n#include <dlfcn.h>\n#include <pthread.h>\n\n//#define LIBNAME EXECDIRECTORY \"/libHdmi.so\"\n\nstatic int run_xwindows = 1;\ntypedef int (*qtmain_t)(void *param);\ntypedef void (*show_data_t)(unsigned int vsync, unsigned int hsync, unsigned int de, unsigned int data);\n\nstatic show_data_t show_data;\nstatic pthread_t threaddata;\nstatic unsigned int vsync, hsync, de;\nstatic int trace_data;//= 1;\n\nstatic void startmeup()\n{\n    void* handle = dlopen(LIBNAME, RTLD_LAZY);\n    if (!handle) {\n        printf( \"Cannot open library\\n\");\n        exit(-1);\n    }\n    printf(\"Loading library for qtmain...\\n\");\n    dlerror();\n    if (!run_xwindows) {\n        printf( \"Not calling qtmain...\\n\");\n        return;\n    }\n    qtmain_t qtmain = (qtmain_t) dlsym(handle, \"qtmain\");\n    const char *dlsym_error = dlerror();\n    if (dlsym_error) {\n        printf( \"Cannot load symbol 'qtmain': %s\\n\", dlsym_error);\n        dlclose(handle);\n        exit(-1);\n    }\n    show_data = (show_data_t) dlsym(handle, \"show_data\");\n    dlsym_error = dlerror();\n    if (dlsym_error) {\n        printf( \"Cannot load symbol 'show_data': %s\\n\", dlsym_error);\n        dlclose(handle);\n        exit(-1);\n    }\n    printf( \"Calling qtmain...\\n\");\n    pthread_create(&threaddata, NULL, (void* (*)(void*))qtmain, (void*)NULL);\n    //dlclose(handle);\n}\n\nextern \"C\" void bdpi_hdmi_vsync(unsigned int v)\n{\n    vsync = v;\n}\n\nextern \"C\" void bdpi_hdmi_hsync(unsigned int v)\n{\n    hsync = v;\n}\n\nextern \"C\" void bdpi_hdmi_de(unsigned int v)\n{\n    de = v;\n}\n\nextern \"C\" void bdpi_hdmi_data(unsigned int v)\n{\n    static int once = 1;\n    if (once)\n       startmeup();\n    once = 0;\n    if (show_data)\n        show_data(vsync, hsync, de, v);\n    else if (trace_data)\n        printf(\"bdpi_hdmi_data: v %x; h %x; e %x = %4x\\n\", vsync, hsync, de, v);\n}\n"
  },
  {
    "path": "examples/hdmidisplay/HDMI16.bsv",
    "content": "/* Copyright (c) 2014 Quanta Research Cambridge, Inc\n *\n * Permission is hereby granted, free of charge, to any person obtaining a\n * copy of this software and associated documentation files (the \"Software\"),\n * to deal in the Software without restriction, including without limitation\n * the rights to use, copy, modify, merge, publish, distribute, sublicense,\n * and/or sell copies of the Software, and to permit persons to whom the\n * Software is furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n * DEALINGS IN THE SOFTWARE.\n */\nimport HDMI::*;\n\ntypedef HDMI#(Bit#(16)) HDMI16;\n\nimport \"BDPI\" function Action bdpi_hdmi_vsync(Bit#(1) v);\nimport \"BDPI\" function Action bdpi_hdmi_hsync(Bit#(1) v);\nimport \"BDPI\" function Action bdpi_hdmi_de(Bit#(1) v);\nimport \"BDPI\" function Action bdpi_hdmi_data(Bit#(16) v);\nmodule mkResponder#(HDMI#(Bit#(16)) pins)(Empty);\n    rule hvconv;\n        bdpi_hdmi_vsync(pins.hdmi_vsync);\n    endrule\n    rule hvconh;\n        bdpi_hdmi_hsync(pins.hdmi_hsync);\n    endrule\n    rule hvconde;\n        bdpi_hdmi_de(pins.hdmi_de);\n    endrule\n    rule hvcond;\n        bdpi_hdmi_data(pins.hdmi_data);\n    endrule\nendmodule\n"
  },
  {
    "path": "examples/hdmidisplay/Makefile",
    "content": "CONNECTALDIR?=../..\nifeq ($(BOARD),bluesim)\nH2S_INTERFACES = HdmiDisplay:HdmiDisplayIndication,HdmiGeneratorIndication:defaultClock\nelse\nH2S_INTERFACES = HdmiDisplay:HdmiDisplayIndication,HdmiGeneratorIndication:host.ps7.fclkclk\\[1\\]\nendif\nS2H_INTERFACES = HdmiDisplayRequest:HdmiDisplay.displayRequest HdmiGeneratorRequest:HdmiDisplay.internalRequest\nMEM_READ_INTERFACES = lHdmiDisplay.dmaClient\n\nLIBBSVDIR=$(CONNECTALDIR)/lib/bsv\nBSVFILES = $(LIBBSVDIR)/HdmiDisplay.bsv $(LIBBSVDIR)/HDMI.bsv $(CONNECTALDIR)/lib/deprecated/DmaUtils.bsv HDMI16.bsv\nCPPFILES= testhdmidisplay.cpp\nCONNECTALFLAGS = -C hdmidisplay-$(BOARD).xdc -D IMPORT_HOSTIF\nPIN_TYPE = HDMI16\nPIN_TYPE_INCLUDE = HDMI16\nifeq ($(BOARD),zedboard)\nCONNECTALFLAGS += -D USE_I2C0\nI2C_JSON_FILE = --pinoutfile i2c.json\nendif\nREALCONNECTALDIR=$(realpath ../..)\nCONNECTALFLAGS += -q -D LIBNAME=\\\\\\\"$(REALCONNECTALDIR)/examples/hdmidisplay/bluesim/jni/libHdmi.so\\\\\\\"\nCONNECTALFLAGS += -D SIMULATIONRESPONDER=mkResponder -m $(CONNECTALDIR)/examples/hdmidisplay/BsimHdmi.cpp \n\nCONNECTALFLAGS += -C $(BOARD)/sources/hdmi.xdc\nCONNECTALFLAGS += -D SIM_DMA_READ_LATENCY=1 -D SIM_DMA_WRITE_LATENCY=1\nAUTOTOP = --importfiles HDMI --importfiles PS7LIB --interface pins:HdmiDisplay.hdmi\n\ngentarget:: $(BOARD)/sources/hdmi.xdc\n\n$(BOARD)/sources/hdmi.xdc: hdmi.json $(CONNECTALDIR)/boardinfo/$(BOARD).json\n\tmkdir -p $(BOARD)/sources\nifneq ($(BOARD),bluesim)\n\t$(CONNECTALDIR)/scripts/generate-constraints.py $(PIN_BINDINGS) -o $(BOARD)/sources/hdmi.xdc --boardfile $(CONNECTALDIR)/boardinfo/$(BOARD).json --pinoutfile hdmi.json $(I2C_JSON_FILE)\nendif\n\ninclude $(CONNECTALDIR)/Makefile.connectal\n"
  },
  {
    "path": "examples/hdmidisplay/TestHdmi.pro",
    "content": "\nQT       += core gui\n\nTARGET = Hdmi\nTEMPLATE = lib\nCONFIG += sharedlib\n\nHEADERS += worker.h\nSOURCES += qtmain.cpp\n"
  },
  {
    "path": "examples/hdmidisplay/hdmi.json",
    "content": "{\n    \"CLK_hdmi_clock_if\": {\n\t\"hdmi\": \"clock\"\n    },\n    \"hdmi_hsync\": {\n\t\"hdmi\": \"hsync\"\n    },\n    \"hdmi_vsync\": {\n\t\"hdmi\": \"vsync\"\n    },\n    \"hdmi_de\": {\n\t\"hdmi\": \"de\"\n    },\n    \"hdmi_data[0]\": { \"hdmi\": \"data[0]\" },\n    \"hdmi_data[1]\": { \"hdmi\": \"data[1]\" },\n    \"hdmi_data[2]\": { \"hdmi\": \"data[2]\" },\n    \"hdmi_data[3]\": { \"hdmi\": \"data[3]\" },\n    \"hdmi_data[4]\": { \"hdmi\": \"data[4]\" },\n    \"hdmi_data[5]\": { \"hdmi\": \"data[5]\" },\n    \"hdmi_data[6]\": { \"hdmi\": \"data[6]\" },\n    \"hdmi_data[7]\": { \"hdmi\": \"data[7]\" },\n    \"hdmi_data[8]\": { \"hdmi\": \"data[8]\" },\n    \"hdmi_data[9]\": { \"hdmi\": \"data[9]\" },\n    \"hdmi_data[10]\": { \"hdmi\": \"data[10]\" },\n    \"hdmi_data[11]\": { \"hdmi\": \"data[11]\" },\n    \"hdmi_data[12]\": { \"hdmi\": \"data[12]\" },\n    \"hdmi_data[13]\": { \"hdmi\": \"data[13]\" },\n    \"hdmi_data[14]\": { \"hdmi\": \"data[14]\" },\n    \"hdmi_data[15]\": { \"hdmi\": \"data[15]\" }\n}\n"
  },
  {
    "path": "examples/hdmidisplay/hdmidisplay-bluesim.xdc",
    "content": "## intentionally blank\n"
  },
  {
    "path": "examples/hdmidisplay/hdmidisplay-vc707.xdc",
    "content": "\n\n\n"
  },
  {
    "path": "examples/hdmidisplay/hdmidisplay-zc702.xdc",
    "content": "set_property LOC L16 [get_ports \"hdmi_clk\"]\nset_property IOSTANDARD LVCMOS25 [get_ports \"hdmi_clk\"]\nset_property slew \"SLOW\" [get_ports \"hdmi_clk\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"hdmi_clk\"]\n\nset_property LOC H15 [get_ports \"hdmi_vsync\"]\nset_property IOSTANDARD LVCMOS25 [get_ports \"hdmi_vsync\"]\nset_property slew \"SLOW\" [get_ports \"hdmi_vsync\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"hdmi_vsync\"]\n\nset_property LOC R18 [get_ports \"hdmi_hsync\"]\nset_property IOSTANDARD LVCMOS25 [get_ports \"hdmi_hsync\"]\nset_property slew \"SLOW\" [get_ports \"hdmi_hsync\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"hdmi_hsync\"]\n\nset_property LOC T18 [get_ports \"hdmi_de\"]\nset_property IOSTANDARD LVCMOS25 [get_ports \"hdmi_de\"]\nset_property slew \"SLOW\" [get_ports \"hdmi_de\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"hdmi_de\"]\n\nset_property LOC AB21 [get_ports \"hdmi_data[0]\"]\nset_property IOSTANDARD LVCMOS25 [get_ports \"hdmi_data[0]\"]\nset_property slew \"SLOW\" [get_ports \"hdmi_data[0]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"hdmi_data[0]\"]\n\nset_property LOC AA21 [get_ports \"hdmi_data[1]\"]\nset_property IOSTANDARD LVCMOS25 [get_ports \"hdmi_data[1]\"]\nset_property slew \"SLOW\" [get_ports \"hdmi_data[1]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"hdmi_data[1]\"]\n\nset_property LOC AB22 [get_ports \"hdmi_data[2]\"]\nset_property IOSTANDARD LVCMOS25 [get_ports \"hdmi_data[2]\"]\nset_property slew \"SLOW\" [get_ports \"hdmi_data[2]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"hdmi_data[2]\"]\n\nset_property LOC AA22 [get_ports \"hdmi_data[3]\"]\nset_property IOSTANDARD LVCMOS25 [get_ports \"hdmi_data[3]\"]\nset_property slew \"SLOW\" [get_ports \"hdmi_data[3]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"hdmi_data[3]\"]\n\nset_property LOC V19 [get_ports \"hdmi_data[4]\"]\nset_property IOSTANDARD LVCMOS25 [get_ports \"hdmi_data[4]\"]\nset_property slew \"SLOW\" [get_ports \"hdmi_data[4]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"hdmi_data[4]\"]\n\nset_property LOC V18 [get_ports \"hdmi_data[5]\"]\nset_property IOSTANDARD LVCMOS25 [get_ports \"hdmi_data[5]\"]\nset_property slew \"SLOW\" [get_ports \"hdmi_data[5]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"hdmi_data[5]\"]\n\nset_property LOC V20 [get_ports \"hdmi_data[6]\"]\nset_property IOSTANDARD LVCMOS25 [get_ports \"hdmi_data[6]\"]\nset_property slew \"SLOW\" [get_ports \"hdmi_data[6]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"hdmi_data[6]\"]\n\nset_property LOC U20 [get_ports \"hdmi_data[7]\"]\nset_property IOSTANDARD LVCMOS25 [get_ports \"hdmi_data[7]\"]\nset_property slew \"SLOW\" [get_ports \"hdmi_data[7]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"hdmi_data[7]\"]\n\nset_property LOC W21 [get_ports \"hdmi_data[8]\"]\nset_property IOSTANDARD LVCMOS25 [get_ports \"hdmi_data[8]\"]\nset_property slew \"SLOW\" [get_ports \"hdmi_data[8]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"hdmi_data[8]\"]\n\nset_property LOC W20 [get_ports \"hdmi_data[9]\"]\nset_property IOSTANDARD LVCMOS25 [get_ports \"hdmi_data[9]\"]\nset_property slew \"SLOW\" [get_ports \"hdmi_data[9]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"hdmi_data[9]\"]\n\nset_property LOC W18 [get_ports \"hdmi_data[10]\"]\nset_property IOSTANDARD LVCMOS25 [get_ports \"hdmi_data[10]\"]\nset_property slew \"SLOW\" [get_ports \"hdmi_data[10]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"hdmi_data[10]\"]\n\nset_property LOC T19 [get_ports \"hdmi_data[11]\"]\nset_property IOSTANDARD LVCMOS25 [get_ports \"hdmi_data[11]\"]\nset_property slew \"SLOW\" [get_ports \"hdmi_data[11]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"hdmi_data[11]\"]\n\nset_property LOC U19 [get_ports \"hdmi_data[12]\"]\nset_property IOSTANDARD LVCMOS25 [get_ports \"hdmi_data[12]\"]\nset_property slew \"SLOW\" [get_ports \"hdmi_data[12]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"hdmi_data[12]\"]\n\nset_property LOC R19 [get_ports \"hdmi_data[13]\"]\nset_property IOSTANDARD LVCMOS25 [get_ports \"hdmi_data[13]\"]\nset_property slew \"SLOW\" [get_ports \"hdmi_data[13]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"hdmi_data[13]\"]\n\nset_property LOC T17 [get_ports \"hdmi_data[14]\"]\nset_property IOSTANDARD LVCMOS25 [get_ports \"hdmi_data[14]\"]\nset_property slew \"SLOW\" [get_ports \"hdmi_data[14]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"hdmi_data[14]\"]\n\nset_property LOC T16 [get_ports \"hdmi_data[15]\"]\nset_property IOSTANDARD LVCMOS25 [get_ports \"hdmi_data[15]\"]\nset_property slew \"SLOW\" [get_ports \"hdmi_data[15]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"hdmi_data[15]\"]\n\n"
  },
  {
    "path": "examples/hdmidisplay/hdmidisplay-zedboard.xdc",
    "content": "## \n## put the constraints for the HDMI pins here\n##\nset_property LOC W18 [get_ports \"hdmi_clk\"]\nset_property IOSTANDARD LVCMOS25 [get_ports \"hdmi_clk\"]\nset_property slew \"SLOW\" [get_ports \"hdmi_clk\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"hdmi_clk\"]\n\nset_property LOC W17 [get_ports \"hdmi_vsync\"]\nset_property IOSTANDARD LVCMOS25 [get_ports \"hdmi_vsync\"]\nset_property slew \"SLOW\" [get_ports \"hdmi_vsync\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"hdmi_vsync\"]\n\nset_property LOC V17 [get_ports \"hdmi_hsync\"]\nset_property IOSTANDARD LVCMOS25 [get_ports \"hdmi_hsync\"]\nset_property slew \"SLOW\" [get_ports \"hdmi_hsync\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"hdmi_hsync\"]\n\nset_property LOC U16 [get_ports \"hdmi_de\"]\nset_property IOSTANDARD LVCMOS25 [get_ports \"hdmi_de\"]\nset_property slew \"SLOW\" [get_ports \"hdmi_de\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"hdmi_de\"]\n\nset_property LOC Y13 [get_ports \"hdmi_data[0]\"]\nset_property IOSTANDARD LVCMOS25 [get_ports \"hdmi_data[0]\"]\nset_property slew \"SLOW\" [get_ports \"hdmi_data[0]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"hdmi_data[0]\"]\n\nset_property LOC AA13 [get_ports \"hdmi_data[1]\"]\nset_property IOSTANDARD LVCMOS25 [get_ports \"hdmi_data[1]\"]\nset_property slew \"SLOW\" [get_ports \"hdmi_data[1]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"hdmi_data[1]\"]\n\nset_property LOC AA14 [get_ports \"hdmi_data[2]\"]\nset_property IOSTANDARD LVCMOS25 [get_ports \"hdmi_data[2]\"]\nset_property slew \"SLOW\" [get_ports \"hdmi_data[2]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"hdmi_data[2]\"]\n\nset_property LOC Y14 [get_ports \"hdmi_data[3]\"]\nset_property IOSTANDARD LVCMOS25 [get_ports \"hdmi_data[3]\"]\nset_property slew \"SLOW\" [get_ports \"hdmi_data[3]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"hdmi_data[3]\"]\n\nset_property LOC AB15 [get_ports \"hdmi_data[4]\"]\nset_property IOSTANDARD LVCMOS25 [get_ports \"hdmi_data[4]\"]\nset_property slew \"SLOW\" [get_ports \"hdmi_data[4]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"hdmi_data[4]\"]\n\nset_property LOC AB16 [get_ports \"hdmi_data[5]\"]\nset_property IOSTANDARD LVCMOS25 [get_ports \"hdmi_data[5]\"]\nset_property slew \"SLOW\" [get_ports \"hdmi_data[5]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"hdmi_data[5]\"]\n\nset_property LOC AA16 [get_ports \"hdmi_data[6]\"]\nset_property IOSTANDARD LVCMOS25 [get_ports \"hdmi_data[6]\"]\nset_property slew \"SLOW\" [get_ports \"hdmi_data[6]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"hdmi_data[6]\"]\n\nset_property LOC AB17 [get_ports \"hdmi_data[7]\"]\nset_property IOSTANDARD LVCMOS25 [get_ports \"hdmi_data[7]\"]\nset_property slew \"SLOW\" [get_ports \"hdmi_data[7]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"hdmi_data[7]\"]\n\nset_property LOC AA17 [get_ports \"hdmi_data[8]\"]\nset_property IOSTANDARD LVCMOS25 [get_ports \"hdmi_data[8]\"]\nset_property slew \"SLOW\" [get_ports \"hdmi_data[8]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"hdmi_data[8]\"]\n\nset_property LOC Y15 [get_ports \"hdmi_data[9]\"]\nset_property IOSTANDARD LVCMOS25 [get_ports \"hdmi_data[9]\"]\nset_property slew \"SLOW\" [get_ports \"hdmi_data[9]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"hdmi_data[9]\"]\n\nset_property LOC W13 [get_ports \"hdmi_data[10]\"]\nset_property IOSTANDARD LVCMOS25 [get_ports \"hdmi_data[10]\"]\nset_property slew \"SLOW\" [get_ports \"hdmi_data[10]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"hdmi_data[10]\"]\n\nset_property LOC W15 [get_ports \"hdmi_data[11]\"]\nset_property IOSTANDARD LVCMOS25 [get_ports \"hdmi_data[11]\"]\nset_property slew \"SLOW\" [get_ports \"hdmi_data[11]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"hdmi_data[11]\"]\n\nset_property LOC V15 [get_ports \"hdmi_data[12]\"]\nset_property IOSTANDARD LVCMOS25 [get_ports \"hdmi_data[12]\"]\nset_property slew \"SLOW\" [get_ports \"hdmi_data[12]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"hdmi_data[12]\"]\n\nset_property LOC U17 [get_ports \"hdmi_data[13]\"]\nset_property IOSTANDARD LVCMOS25 [get_ports \"hdmi_data[13]\"]\nset_property slew \"SLOW\" [get_ports \"hdmi_data[13]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"hdmi_data[13]\"]\n\nset_property LOC V14 [get_ports \"hdmi_data[14]\"]\nset_property IOSTANDARD LVCMOS25 [get_ports \"hdmi_data[14]\"]\nset_property slew \"SLOW\" [get_ports \"hdmi_data[14]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"hdmi_data[14]\"]\n\nset_property LOC V13 [get_ports \"hdmi_data[15]\"]\nset_property IOSTANDARD LVCMOS25 [get_ports \"hdmi_data[15]\"]\nset_property slew \"SLOW\" [get_ports \"hdmi_data[15]\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"hdmi_data[15]\"]\n\n"
  },
  {
    "path": "examples/hdmidisplay/i2c.json",
    "content": "{\n    \"I2C0_scl\": {\n\t\"i2c0\": \"scl\"\n    },\n    \"I2C0_sda\": {\n\t\"i2c0\": \"sda\"\n    }\n}\n"
  },
  {
    "path": "examples/hdmidisplay/qtmain.cpp",
    "content": "// Copyright (c) 2014 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\n#include <stdio.h>\n#include <QApplication>                                                                                              \n#include <QPixmap>                                                                                                   \n#include <QLabel>\n#include <QImage>\n#include <QPainter>\n#include <QTimer>\n#include <QThread>\n#include <sys/select.h>\n#include \"worker.h\"\n\n//#define SIZE 300\n#define SIZE 600//300\n\nstatic int vpos, hpos;\nstatic int once = 1;\nstatic PinsUpdate *pinsglobal;\nstatic QImage image;\n\nextern \"C\" void show_data(unsigned int vsync, unsigned int hsync, unsigned int de, unsigned int data)\n{\n    //printf(\"qtshowdata: v %x; h %x; e %x = %4x\\n\", vsync, hsync, de, data);\n    if (once)\n        image = QImage(SIZE, SIZE, QImage::Format_RGB32);\n    once = 0;\n    if (de) {\n        if (vpos == 0 && hpos == 0 && !once)\n            pinsglobal->newpix(image);\n        if (hpos < SIZE && vpos < SIZE)\n            image.setPixel(hpos, vpos, data);\n        hpos++;\n    }\n    if (vsync)\n        vpos = 0;\n    if (hsync) {\n        if (hpos)\n            vpos++;\n        hpos = 0;\n    }\n}\n\nvoid Worker::newpix(QImage image)\n{\n    label.setPixmap(QPixmap::fromImage(image));\n    if (once) {\n        label.show();\n        once = 0;\n    }\n};\n\nextern \"C\" int qtmain(void *param)\n{\n    int argc = 1;\n    static char *fakeargv[] = {(char *)\"HA\", NULL};\n    QApplication app(argc, fakeargv); \n    Worker worker;\n    PinsUpdate pins;\n\n    (void)param;\n    printf(\"[%s:%d]\\n\", __FUNCTION__, __LINE__);\n    pinsglobal = &pins;\n    QObject::connect(&pins, SIGNAL(updatepix(QImage)), &worker, SLOT(newpix(QImage)));\n    printf(\"[%s:%d] starting app.exec thread %lx\\n\", __FUNCTION__, __LINE__, QThread::currentThreadId());\n    return app.exec();\n}\n"
  },
  {
    "path": "examples/hdmidisplay/testhdmidisplay.cpp",
    "content": "/* Copyright (c) 2014 Quanta Research Cambridge, Inc\n *\n * Permission is hereby granted, free of charge, to any person obtaining a\n * copy of this software and associated documentation files (the \"Software\"),\n * to deal in the Software without restriction, including without limitation\n * the rights to use, copy, modify, merge, publish, distribute, sublicense,\n * and/or sell copies of the Software, and to permit persons to whom the\n * Software is furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n * DEALINGS IN THE SOFTWARE.\n */\n#include <ctype.h>\n#include \"dmaManager.h\"\n#include \"HdmiDisplayRequest.h\"\n#include \"HdmiDisplayIndication.h\"\n#include \"HdmiGeneratorIndication.h\"\n#include \"HdmiGeneratorRequest.h\"\n#include \"i2chdmi.h\"\n#ifndef BOARD_bluesim\n#include \"edid.h\"\n#endif\n\n#define FRAME_COUNT 2\n#define MAX_PIXEL 256\n#define INCREMENT_PIXEL 2\n\nstatic HdmiGeneratorRequestProxy *hdmiGenerator;\nstatic HdmiDisplayRequestProxy *device;\nstatic int allocFrame[FRAME_COUNT];\nstatic unsigned int ref_srcAlloc[FRAME_COUNT];\nstatic int *dataptr[FRAME_COUNT];\nstatic int frame_index;\nstatic int nlines = 1080;\nstatic int npixels = 1920;\nstatic int fbsize;\n\nvoid memdump(unsigned char *p, int len, char *title)\n{\nint i;\n\n    i = 0;\n    while (len > 0) {\n        if (!(i & 0xf)) {\n            if (i > 0)\n                fprintf(stdout, \"\\n\");\n            fprintf(stdout, \"%s: \",title);\n        }\n        fprintf(stdout, \"%02x \", *p++);\n        i++;\n        len--;\n    }\n    fprintf(stdout, \"\\n\");\n}\n\nstatic int corner[] = {0, -1, 0xf00f, 0x0fff};\nstatic int corner_index;\nstatic void fill_pixels(int offset)\n{\nprintf(\"[%s:%d]\\n\", __FUNCTION__, __LINE__);\n    int *ptr = dataptr[frame_index];\n    for (int line = 0; line < nlines; line++)\n      for (int pixel = 0; pixel < npixels; pixel++) {\n\tint v = ((((MAX_PIXEL *  line) /  nlines)+offset) % MAX_PIXEL) << 16\n\t       | ((((MAX_PIXEL * pixel) / npixels)+offset) % MAX_PIXEL);\n        if (!v)\n            v = 1;\n        if (line < 20 && pixel < 20)\n            v = corner[(corner_index+0) % 4];\n        if (line < 30 && pixel > npixels - 40)\n            v = corner[(corner_index+1) % 4];\n        if (line > nlines - 20 && pixel < 20)\n            v = corner[(corner_index+2) % 4];\n        if (line > nlines - 30 && pixel > npixels - 40)\n            v = corner[(corner_index+3) % 4];\n        if (line < 20 && pixel % 20 < 2)\n            v = corner[(corner_index+0) % 4];\n        if (line % 30 < 2 && pixel > npixels - 40)\n            v = corner[(corner_index+1) % 4];\n\tptr[line * npixels + pixel] = v;\n      }\n    corner_index = offset/16;\n    portalCacheFlush(allocFrame[frame_index], dataptr[frame_index], fbsize, 1);\n    hdmiGenerator->setTestPattern(0);\n    device->startFrameBuffer(ref_srcAlloc[frame_index], fbsize);\n    hdmiGenerator->waitForVsync(0);\n    frame_index = 1 - frame_index;\n}\n\nstatic int synccount = 0;\nstatic long long totalcount;\nstatic int number;\nclass HdmiIndication : public HdmiGeneratorIndicationWrapper {\npublic:\n    HdmiIndication(int id) : HdmiGeneratorIndicationWrapper(id) {}\n  virtual void vsync ( uint64_t v, uint32_t w ) {\n      static int base = 0;\n\nprintf(\"[%s:%d]\\n\", __FUNCTION__, __LINE__);\ntotalcount += v;\nnumber += w;\n      fill_pixels(base);\nbase += INCREMENT_PIXEL;\n      if (synccount++ >= 20) {\n          synccount = 0;\nuint32_t zeros = v & 0xffffffff, pix = v >> 32;\n          fprintf(stderr, \"[%s] v %\"PRIx64\" pix=%x:%d. zero=%x:%d. w=%x:%d.\\n\", __FUNCTION__,v,pix,pix,zeros,zeros,w,w);\n      }\n    }\n};\nclass DisplayIndication : public HdmiDisplayIndicationWrapper {\npublic:\n    DisplayIndication(int id) : HdmiDisplayIndicationWrapper(id) {}\n    virtual void transferStarted ( uint32_t v ) {\n      fprintf(stderr, \"[%s:%d] v=%d\\n\", __FUNCTION__, __LINE__, v);\n    }\n    virtual void transferFinished ( uint32_t v, uint32_t len ) {\n      fprintf(stderr, \"[%s:%d] v=%d len=%d\\n\", __FUNCTION__, __LINE__, v, len);\n    }\n    virtual void transferStats ( uint32_t count, uint32_t cycles, uint64_t sumcycles ) {\n\tfprintf(stderr, \"[%s:%d] count=%d cycles=%d sumcycles=%\"PRIx64\" avgcycles=%f\\n\", __FUNCTION__, __LINE__, count, cycles, sumcycles, (double)sumcycles / count);\n    }\n};\n\nint main(int argc, const char **argv)\n{\n    device = new HdmiDisplayRequestProxy(IfcNames_HdmiDisplayRequestS2H);\n    DmaManager *dma = platformInit();\n    HdmiIndication hdmiIndication(IfcNames_HdmiGeneratorIndicationH2S);\n    DisplayIndication displayIndication(IfcNames_HdmiDisplayIndicationH2S);\n    hdmiGenerator = new HdmiGeneratorRequestProxy(IfcNames_HdmiGeneratorRequestS2H);\n\n    //device->setTraceTransfers(1);\n    device->stopFrameBuffer();\n    //setClockFrequency(0, 100000000, 0);\n\n    int vblank, hblank, vsyncoff, hsyncoff, vsyncwidth, hsyncwidth;\n#ifdef BOARD_bluesim\n    nlines = 300;\n    npixels = 500;\n    vblank = 10;\n    hblank = 10;\n    vsyncoff = 2;\n    hsyncoff = 2;\n    vsyncwidth = 3;\n    hsyncwidth = 3;\n\nhblank--; // needed on zc702\n#else\n    // read out monitor EDID from ADV7511\n    struct edid edid;\n    init_i2c_hdmi();\n    int i2cfd = open(\"/dev/i2c-0\", O_RDWR);\n    fprintf(stderr, \"Monitor EDID:\\n\");\n    for (int i = 0; i < 256; i++) {\n      edid.raw[i] = i2c_read_reg(i2cfd, 0x3f, i);\n      fprintf(stderr, \" %02x\", edid.raw[i]);\n      if ((i % 16) == 15) {\n\tfprintf(stderr, \" \");\n\tfor (int j = i-15; j <= i; j++) {\n\t  unsigned char c = edid.raw[j];\n\t  fprintf(stderr, \"%c\", (isprint(c) && isascii(c)) ? c : '.');\n\t}\n\tfprintf(stderr, \"\\n\");\n      }\n    }\n    close(i2cfd);\n    parseEdid(edid);\n    long actualFrequency = 0;\n    int status;\n    status = setClockFrequency(0, 100000000, &actualFrequency);\n    printf(\"[%s:%d] setClockFrequency 0 100000000 status=%d actualfreq=%ld\\n\", __FUNCTION__, __LINE__, status, actualFrequency);\n    status = setClockFrequency(1, 160000000, &actualFrequency);\n    printf(\"[%s:%d] setClockFrequency 1 160000000 status=%d actualfreq=%ld\\n\", __FUNCTION__, __LINE__, status, actualFrequency);\n    status = setClockFrequency(3, 200000000, &actualFrequency);\n    printf(\"[%s:%d] setClockFrequency 3 200000000 status=%d actualfreq=%ld\\n\", __FUNCTION__, __LINE__, status, actualFrequency);\n\n    for (int i = 0; i < 4; i++) {\n      int pixclk = (long)edid.timing[i].pixclk * 10000;\n      if ((pixclk > 0) && (pixclk < 148000000)) {\n\tnlines = edid.timing[i].nlines;    // number of visible lines\n\tnpixels = edid.timing[i].npixels;\n\tvblank = edid.timing[i].blines; // number of blanking lines\n\thblank = edid.timing[i].bpixels;\n\tvsyncoff = edid.timing[i].vsyncoff; // number of lines in FrontPorch (within blanking)\n\thsyncoff = edid.timing[i].hsyncoff;\n\tvsyncwidth = edid.timing[i].vsyncwidth; // width of Sync (within blanking)\n\thsyncwidth = edid.timing[i].hsyncwidth;\n\n\tfprintf(stderr, \"Using pixclk %d calc_pixclk %ld npixels %d nlines %d\\n\",\n\t\tpixclk,\n\t\t60l * (long)(hblank + npixels) * (long)(vblank + nlines),\n\t\tnpixels, nlines);\n\tsetClockFrequency(1, pixclk, 0);\n//hblank--; // needed on zc702\n\tbreak;\n      }\n    }\n#endif\n    fprintf(stderr, \"lines %d, pixels %d, vblank %d, hblank %d, vwidth %d, hwidth %d\\n\",\n             nlines, npixels, vblank, hblank, vsyncwidth, hsyncwidth);\n    hdmiGenerator->setDeLine(vsyncoff,          // End of FrontPorch\n                            vsyncoff+vsyncwidth,// End of Sync\n                            vblank-1,           // Start of Visible (start of BackPorch)\n                            vblank + nlines, vblank + nlines / 2); // End\n    hdmiGenerator->setDePixel(hsyncoff,\n                            hsyncoff+hsyncwidth, hblank,\n                            hblank + npixels, hblank + npixels / 2);\n#if 0\n    // horiz: frontPorch:87, sync: 44, backPorch:148, (blank=87+44+148=279) pixel:1920\n    // vert: frontPorch:3, sync:5, backPorch:36, (blank = 36+5+8=49) lines:1080\n    dePixelStartSync <- mkSyncReg(              87\n    dePixelEndSync <- mkSyncReg(           44 + 87\n    dePixelStartVisible <- mkSyncReg(148 + 44 + 87\n    dePixelEnd <- mkSyncReg(  1920 + 148 + 44 + 87\n    dePixelMid <- mkSyncReg((1920/2) + 148 + 44\n\n    deLineStartSync <- mkSyncReg(              3\n    deLineEndSync <- mkSyncReg(            5 + 3\n    deLineStartVisible <- mkSyncReg(  36 + 5 + 3\n    deLineEnd <- mkSyncReg(    1080 + 36 + 5 + 3\n    deLineMid <- mkSyncReg((1080/2) + 41\n#endif\n\n    fbsize = nlines*npixels*sizeof(uint32_t);\n\n    for (int i = 0; i < FRAME_COUNT; i++) {\n        allocFrame[i] = portalAlloc(fbsize, 0);\n        dataptr[i] = (int*)portalMmap(allocFrame[i], fbsize);\n        memset(dataptr[i], i ? 0xff : 0, fbsize);\n        fprintf(stderr, \"hdmidisplay: calling dma->reference %d/%d\\n\", i, FRAME_COUNT);\n        ref_srcAlloc[i] = dma->reference(allocFrame[i]);\n    }\n\n    //uint64_t beats = hostMemServerIndication->getMemoryTraffic(ChannelType_Read);\n    //fprintf(stderr, \"first mem_stats=%\"PRIx64\"\\n\", beats);\n    fprintf(stderr, \"hdmidisplay: sleep 3\\n\");\n    sleep(3);\n    fprintf(stderr, \"hdmidisplay: Starting frame buffer ref=%d...\", ref_srcAlloc[0]);\n    fill_pixels(0);\n    fprintf(stderr, \"hdmidisplay: run test\\n\");\n    sleep(60);\n    fprintf(stderr, \"hdmidisplay: done\\n\");\n}\n"
  },
  {
    "path": "examples/hdmidisplay/worker.h",
    "content": "/* Copyright (c) 2014 Quanta Research Cambridge, Inc\n *\n * Permission is hereby granted, free of charge, to any person obtaining a\n * copy of this software and associated documentation files (the \"Software\"),\n * to deal in the Software without restriction, including without limitation\n * the rights to use, copy, modify, merge, publish, distribute, sublicense,\n * and/or sell copies of the Software, and to permit persons to whom the\n * Software is furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n * DEALINGS IN THE SOFTWARE.\n */\n\n#include <QImage>\n#include <QLabel>\n\nclass Worker: public QObject {\n    Q_OBJECT\n    int once;\n    QLabel label;\npublic:\n    Worker(): once(1) { }\nprivate slots:\n    void newpix(QImage image);\n};\n\nclass PinsUpdate: public QObject {\n    Q_OBJECT\npublic:\n    void newpix(QImage image) {\n        emit updatepix(image);\n    };\nsignals:\n    void updatepix(QImage image);\n};\n\n"
  },
  {
    "path": "examples/imageon/ImageonCapture.bsv",
    "content": "// Copyright (c) 2014 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n`include \"ConnectalProjectConfig.bsv\"\nimport Vector::*;\nimport GetPut::*;\nimport Clocks :: *;\nimport BRAMFIFO::*;\nimport ConnectalMemTypes::*;\nimport ClientServer::*;\nimport Pipe::*;\nimport MemWriteEngine::*;\nimport IserdesDatadeser::*;\nimport IserdesDatadeserIF::*;\nimport Connectable :: *;\nimport FIFO::*;\nimport MemServer::*;\nimport ConnectalMMU::*;\nimport Portal::*;\nimport XilinxCells::*;\nimport ConnectalClocks::*;\nimport Gearbox::*;\nimport ConnectalSpi::*;\nimport ImageonVita::*;\nimport HDMI::*;\nimport YUV::*;\nimport ConnectalXilinxCells::*;\nimport ImageonCapturePins::*;\n\nBit#(10) imageDataTag = 10'h035;\nBit#(10) otherDataTag = 10'h015;\n\ntypedef struct {\n    Bit#(2) monitor;\n    Bit#(32) count;\n} MonitorCount deriving (Bits, Eq);\n\ninterface ImageonCaptureIndication;\n    method Action spi_response(Bit#(32) v);\nendinterface\n\ninterface ImageonCaptureRequest;\n    method Action set_trigger_cnt(Bit#(32) v);\n    method Action startWrite(Bit#(32) pointer, Bit#(32) numBytes);\n    method Action set_host_oe(Bit#(1) v);\n    method Action put_spi_request(Bit#(32) v);\n    method Action set_i2c_mux_reset_n(Bit#(1) v);\nendinterface\n\ninterface ImageonCapture;\n   interface ImageonSerdesRequest            serdes_request;\n   interface HdmiGeneratorRequest            hdmi_request;\n   interface Vector#(1, MemWriteClient#(64)) dmaClient;\n   interface ImageonCaptureRequest           capture_request;\n   interface ImageonCapturePins              pins;\nendinterface\n\nmodule mkImageonCapture#(ImageonSerdesIndication serdes_indication, HdmiGeneratorIndication hdmi_ind, ImageonCaptureIndication cap_ind)(ImageonCapture);\n`ifndef SIMULATION\n    B2C1 iclock <- mkB2C1();\n    Clock fmc_imageon_clk1 <- mkClockBUFG(clocked_by iclock.c);\n`else\n    Clock fmc_imageon_clk1 <- exposeCurrentClock();\n`endif\n    Clock defaultClock <- exposeCurrentClock();\n    Reset defaultReset <- exposeCurrentReset();\n    ImageClocks clk <- mkImageClocks(fmc_imageon_clk1);\n    Clock hdmi_clock = clk.hdmi;\n    Clock imageon_clock = clk.imageon;\n    Reset hdmi_reset <- mkAsyncReset(2, defaultReset, hdmi_clock);\n    Reset imageon_reset <- mkAsyncReset(2, defaultReset, imageon_clock);\n    SPIMaster#(Bit#(26), 1) spiController <- mkSPIMaster(1000, True);\n    Reg#(Bit#(1)) i2c_mux_reset_n_reg <- mkReg(0);\n    Reg#(Bool) dmaRun <- mkSyncReg(False, defaultClock, defaultReset, imageon_clock);\n    Reg#(Bit#(32)) trigger_cnt_reg <- mkSyncReg(0, defaultClock, defaultReset, imageon_clock);\n    Reg#(Bit#(1)) imageon_oe <- mkSyncReg(0, defaultClock, defaultReset, imageon_clock);\n    Vector#(3, ReadOnly#(Bit#(1))) vita_trigger_wire;\n    Reg#(Bool) remapKernel <- mkReg(False, clocked_by imageon_clock, reset_by imageon_reset);\n    Gearbox#(4, 1, Bit#(10)) dataGearbox <- mkNto1Gearbox(imageon_clock, imageon_reset, hdmi_clock, hdmi_reset);\n\n    function ReadOnly#(Bit#(1)) roval(Bit#(1) val);\n        return (interface ReadOnly; method Bit#(1) _read(); return val; endmethod endinterface);\n    endfunction\n\n    // serdes: serial line protocol for wires from sensor (nothing sensor specific)\n    ISerdes serdes <- mkISerdes(defaultClock, defaultReset, serdes_indication,\n\t\t\tclocked_by imageon_clock, reset_by imageon_reset);\n\n    // mem capture\n    MemWriteEngine#(64,64,1,1) we <- mkMemWriteEngine();\n    SyncFIFOIfc#(Bit#(64)) synchronizer <- mkSyncBRAMFIFO(10, imageon_clock, imageon_reset, defaultClock, defaultReset);\n    rule sync_data if (dmaRun);\n        synchronizer.enq(serdes.data.capture);\n    endrule\n    rule send_data;\n        we.writeServers[0].data.enq(synchronizer.first);\n        synchronizer.deq;\n    endrule\n    rule dma_response;\n        let rv <- we.writeServers[0].done.get;\n        serdes_indication.iserdes_dma('hffffffff); // request is all finished\n    endrule\n\n    SyncPulseIfc vsyncPulse <- mkSyncHandshake(hdmi_clock, hdmi_reset, imageon_clock);\n    Reg#(Bool)  triggerOutput <- mkReg(True, clocked_by imageon_clock, reset_by imageon_reset);\n    Reg#(Bit#(32)) tcounter <- mkReg(0, clocked_by imageon_clock, reset_by imageon_reset);\n    rule calcTrigger;\n        if (triggerOutput && vsyncPulse.pulse())\n            begin\n            tcounter <= trigger_cnt_reg;\n            triggerOutput <= False;\n            end\n        else\n            tcounter <= tcounter - 1;\n        if (!triggerOutput && tcounter == 0)\n            triggerOutput <= True;\n    endrule\n\n    // fromSensor: sensor specific processing of serdes input, resulting in pixels\n`ifndef SIMULATION\n    ConnectalODDR#(Bit#(1)) pll_out <- mkConnectalODDR(ODDRParams{ddr_clk_edge:\"SAME_EDGE\", init:1, srtype:\"ASYNC\"}, clocked_by imageon_clock, reset_by imageon_reset);\n    ConnectalODDR#(Bit#(1)) pll_t <- mkConnectalODDR(ODDRParams{ddr_clk_edge:\"SAME_EDGE\", init:1, srtype:\"ASYNC\"}, clocked_by imageon_clock, reset_by imageon_reset);\n    ReadOnly#(Bit#(1)) vita_clk_pll <- mkOBUFT(roval(pll_out.q()), roval(pll_t.q()), clocked_by imageon_clock, reset_by imageon_reset);\n    vita_trigger_wire[2] <- mkOBUFT(roval(0), regToReadOnly(imageon_oe), clocked_by imageon_clock, reset_by imageon_reset);\n    vita_trigger_wire[1] <- mkOBUFT(roval(1), regToReadOnly(imageon_oe), clocked_by imageon_clock, reset_by imageon_reset);\n    vita_trigger_wire[0] <- mkOBUFT(regToReadOnly(triggerOutput), regToReadOnly(imageon_oe), clocked_by imageon_clock, reset_by imageon_reset);\n    ReadOnly#(Bit#(1)) vita_reset_n_wire <- mkOBUFT(regToReadOnly(serdes.data.reset), regToReadOnly(imageon_oe), clocked_by imageon_clock, reset_by imageon_reset);\n\n    rule pll_rule;\n        pll_t.s(False);\n        pll_out.s(False);\n        pll_out.d1(0);\n        pll_out.d2(1);\n        pll_out.ce(True);\n        pll_t.d1(imageon_oe);\n        pll_t.d2(imageon_oe);\n        pll_t.ce(True);\n    endrule\n`else\n    let vita_clk_pll = 0;\n    let vita_reset_n_wire = 0;\n    vita_trigger_wire = replicate(interface ReadOnly; method Bit#(1) _read(); return 0; endmethod endinterface);\n`endif\n\n    rule frameData;\n        Vector#(5, Bit#(10)) v = serdes.data.raw_data();\n        if (v[0] == imageDataTag || v[0] == otherDataTag)\n            begin\n            Vector#(4, Bit#(10)) dor;\n            for (Integer i = 0; i < 4; i = i + 1)\n                if (!remapKernel)\n                    dor[i] = v[i+1];\n                else\n                    dor[i] = v[4-i];\n            remapKernel <= !remapKernel;\n            dataGearbox.enq(dor);\n            end\n        else\n            remapKernel <= False;\n    endrule\n\n    rule spiResponse;\n        Bit#(26) v <- spiController.response[0].get();\n        cap_ind.spi_response(extend(v));\n    endrule\n\n    // hdmi: output to display\n    HdmiGenerator#(Rgb888) lHdmiGenerator <- mkHdmiGenerator(defaultClock, defaultReset,\n        vsyncPulse, hdmi_ind, clocked_by hdmi_clock, reset_by hdmi_reset);\n    Rgb888ToYyuv converter <- mkRgb888ToYyuv(clocked_by hdmi_clock, reset_by hdmi_reset);\n    mkConnection(lHdmiGenerator.rgb888, converter.rgb888);\n    HDMI#(Bit#(HdmiBits)) hdmisignals <- mkHDMI(converter.yyuv, clocked_by hdmi_clock, reset_by hdmi_reset);\n\n    Reg#(Bool) frameStart <- mkReg(False, clocked_by imageon_clock, reset_by imageon_reset);\n    Reg#(Bit#(32)) frameCount <- mkReg(0, clocked_by imageon_clock, reset_by imageon_reset);\n    SyncFIFOIfc#(MonitorCount) frameStartSynchronizer <- mkSyncFIFO(2, imageon_clock, imageon_reset, defaultClock);\n    Wire#(Bit#(2)) monitor_wires <- mkDWire(0, clocked_by imageon_clock, reset_by imageon_reset);\n\n    rule frameStartRule;\n        Bool fs = unpack(monitor_wires[0]);\n        if (fs && !frameStart) begin\n\t   // start of frame?\n\t   // need to cross the clock domain\n\t   frameStartSynchronizer.enq(MonitorCount{monitor:monitor_wires, count:frameCount});\n\t   frameCount <= frameCount + 1;\n        end\n       frameStart <= fs;\n    endrule\n    rule frameStartIndication;\n       let tpl = frameStartSynchronizer.first();\n       frameStartSynchronizer.deq();\n       //captureIndicationProxy.ifc.frameStart(tpl.monitor, tpl.count);\n    endrule\n\n    Reg#(Bit#(10)) xsvi <- mkReg(0, clocked_by hdmi_clock, reset_by hdmi_reset);\n    rule xsviConnection;\n        // copy data from sensor to hdmi output\n        dataGearbox.deq;\n        xsvi <= dataGearbox.first[0];\n    endrule\n    rule xsviput;\n        Bit#(32) pixel = {8'b0, xsvi[9:2], xsvi[9:2], xsvi[9:2]};\n        lHdmiGenerator.pdata.put(pixel);\n    endrule\n\n    interface serdes_request = serdes.request;\n    interface hdmi_request = lHdmiGenerator.request;\n    interface dmaClient = cons(we.dmaClient, nil);\n    interface ImageonCaptureRequest capture_request;\n        method Action set_trigger_cnt(Bit#(32) v);\n            trigger_cnt_reg <= v;\n            serdes.data.start_capture();\n        endmethod\n        method Action startWrite(Bit#(32) pointer, Bit#(32) numBytes);\n            we.writeServers[0].request.put(MemengineCmd{sglId:pointer, base:0, len:truncate(numBytes), burstLen:8, tag:0});\n            dmaRun <= True;\n        endmethod\n\tmethod Action set_host_oe(Bit#(1) v);\n\t    imageon_oe <= ~v;\n\tendmethod\n        method Action put_spi_request(Bit#(32) v);\n            spiController.request[0].put(truncate(v));\n        endmethod\n        method Action set_i2c_mux_reset_n(Bit#(1) v);\n            i2c_mux_reset_n_reg <= v;\n        endmethod\n    endinterface\n    interface ImageonCapturePins pins;\n`ifndef SIMULATION\n        method Action fmc_video_clk1(Bit#(1) v);\n            iclock.inputclock(v);\n        endmethod\n`endif\n        method Action io_vita_monitor(Bit#(2) v);\n\t    monitor_wires <= v;\n        endmethod\n        method Bit#(1) io_vita_clk_pll();\n            return vita_clk_pll;\n        endmethod\n        method Bit#(1) io_vita_reset_n();\n            return vita_reset_n_wire;\n        endmethod\n        method Vector#(3, ReadOnly#(Bit#(1))) io_vita_trigger();\n            return vita_trigger_wire;\n        endmethod\n        method Bit#(1) i2c_mux_reset_n(); return i2c_mux_reset_n_reg; endmethod\n        interface SpiMasterPins spi = spiController.pins;\n        interface imageon_deleteme_unused_clock = imageon_clock;\n        interface imageon_deleteme_unused_reset = imageon_reset;\n        interface ImageonSerdesPins serpins = serdes.pins;\n        interface HDMI hdmi = hdmisignals;\n    endinterface\nendmodule\n"
  },
  {
    "path": "examples/imageon/ImageonCapturePins.bsv",
    "content": "// Copyright (c) 2014 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\nimport Vector::*;\nimport IserdesDatadeserIF::*;\nimport ConnectalSpi::*;\nimport HDMI::*;\n\ninterface ImageonCapturePins;\n    method Bit#(1) io_vita_clk_pll();\n    method Bit#(1) io_vita_reset_n();\n    method Vector#(3, ReadOnly#(Bit#(1))) io_vita_trigger();\n    method Action io_vita_monitor(Bit#(2) v);\n    interface SpiMasterPins#(1) spi;\n    method Bit#(1) i2c_mux_reset_n();\n    interface Clock imageon_deleteme_unused_clock;\n    interface Reset imageon_deleteme_unused_reset;\n    interface ImageonSerdesPins serpins;\n    (* prefix=\"\" *)\n    interface HDMI#(Bit#(HdmiBits)) hdmi;\n    method Action fmc_video_clk1(Bit#(1) v);\nendinterface\n"
  },
  {
    "path": "examples/imageon/Makefile",
    "content": "CONNECTALDIR?=../..\nS2H_INTERFACES = ImageonSerdesRequest:ImageonCapture.serdes_request HdmiGeneratorRequest:ImageonCapture.hdmi_request ImageonCaptureRequest:ImageonCapture.capture_request\nH2S_INTERFACES = ImageonCapture:ImageonSerdesIndication,HdmiGeneratorIndication,ImageonCaptureIndication\nMEM_WRITE_INTERFACES = lImageonCapture.dmaClient\n\nBSVFILES = $(CONNECTALDIR)/lib/bsv/IserdesDatadeserIF.bsv $(CONNECTALDIR)/lib/bsv/HDMI.bsv ImageonCapture.bsv\nCPPFILES=testimagecapture.cpp\nCONNECTALFLAGS = -D USE_I2C1\nPINOUT_FILE += imageon-fmc.json\nPIN_TYPE = ImageonCapturePins\nPIN_TYPE_INCLUDE = ImageonCapturePins\nifeq ($(BOARD),zedboard)\n    CONNECTALFLAGS += -D USE_I2C0 \n    PINOUT_FILE += imageon-zedboard.json\n    PIN_BINDINGS ?= fmc:fmc1\nelse\n    PIN_BINDINGS ?= fmc:fmc2\nendif\nCONNECTALFLAGS += -C imageon-clocks.xdc --tcl clock.tcl\nAUTOTOP = --interface pins:ImageonCapture.pins\n\ninclude $(CONNECTALDIR)/Makefile.connectal\n"
  },
  {
    "path": "examples/imageon/Makefile.dump",
    "content": "\nall:\n\tgcc -Wall -o dump_image dump_image.cpp\n\nfetchdata:\n\tadb -s 172.17.1.165:5555 pull /mnt/sdcard/tmp.outfile pixeldata.dat \n"
  },
  {
    "path": "examples/imageon/clock.tcl",
    "content": "## disconnect unused CLK and RST ports inserted by bsc\nforeach {pat} {CLK_GATE_* CLK_pins_spi_clock} {\n    foreach {net} [get_nets $pat] {\n\tputs \"disconnecting net $net\"\n\tdisconnect_net -net $net -objects [get_pins -of_objects $net]\n    }\n}\n"
  },
  {
    "path": "examples/imageon/dump_image.cpp",
    "content": "/* Copyright (c) 2014 Quanta Research Cambridge, Inc\n *\n * Permission is hereby granted, free of charge, to any person obtaining a\n * copy of this software and associated documentation files (the \"Software\"),\n * to deal in the Software without restriction, including without limitation\n * the rights to use, copy, modify, merge, publish, distribute, sublicense,\n * and/or sell copies of the Software, and to permit persons to whom the\n * Software is furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n * DEALINGS IN THE SOFTWARE.\n */\n#include <stdio.h>\n#include <string.h>\n#include <fcntl.h>\n#include <sys/types.h>\n#include <unistd.h>\n#include <stdint.h>\n#include <stdlib.h>\n\nstatic struct {\n    int         len;       /* number of bits of field */\n    const char *name;      /* name of field */\n    uint64_t    default_value; /* value to skip when dumping */\n} *dumpptr, *dumpend, dumpitem[] = {\n    {10, \"ei\", 0},\n    {5, \"wc\", 0},\n    {4, \"a\", 0},\n    {10, \"cdata\", 0x3a6},\n    {16, \"gen\", 0},\n    {3, \"csam\", 0},\n    {1, \"astart\", 0},\n    {1, \"autoa\", 0},\n    {1, \"sinc\", 0},\n    {1, \"sbit\", 0},\n    {1, \"sce\", 0},\n    {1, \"wren\", 1},\n    {10, \"sdata\", -1},\n//64\n    {}};\n        //return {edge_int, windowcount[4:0], pack(astate), ctrl_data, gencounter, ctrl_sample, align_start, autoalign,\n        //serdes_capture.send({pack(syncparam), pack(fifo_wren_sync), serdes_data});\n#define STRING_LEN 10000\nstatic char last_string[STRING_LEN], current_string[STRING_LEN];\nint main(int argc, char *argv[])\n{\n    int repeat_count = 0;\n    if (argc != 2) {\n        printf(\"dump_pixel <filename>\\n\");\n        return -1;\n    }\n    int fd = open(argv[1], O_RDONLY);\n    int len = lseek(fd, 0, SEEK_END);\n    printf(\"dump_pixel: filename '%s' len %d\\n\", argv[1], len);\n    lseek(fd, 0, SEEK_SET);\n    uint64_t *data = (uint64_t *)malloc(len);\n    read(fd, data, len);\n    close(fd);\n    dumpend = dumpitem;\n    while((dumpend+1)->len) /* get last value in list to be dumped (LSB bits) */\n        dumpend++;\n    for (unsigned int i = 0; i < len/sizeof(uint64_t); i++) {\n        uint64_t ditem = data[i];\n        dumpptr = dumpend;\n        char *p = current_string;\n        do {\n            uint64_t val = ditem & ((1 << dumpptr->len) - 1);\n            ditem >>= dumpptr->len;\n            if (val != dumpptr->default_value) {\n                sprintf(p, \" %s=%llx\", dumpptr->name, (long long)val);\n                p += strlen(p);\n            }\n        } while (dumpptr-- != dumpitem);\n        if (!strcmp(last_string, current_string))\n            repeat_count++;\n        else {\n            if (repeat_count)\n                printf(\"repeat %d\\n\", repeat_count);\n            printf(\"%s\\n\", current_string);\n            repeat_count = 0;\n            strcpy(last_string, current_string);\n        }\n    }\n    return 0;\n}\n"
  },
  {
    "path": "examples/imageon/i2ccamera.h",
    "content": "/* Copyright (c) 2014 Quanta Research Cambridge, Inc\n *\n * Permission is hereby granted, free of charge, to any person obtaining a\n * copy of this software and associated documentation files (the \"Software\"),\n * to deal in the Software without restriction, including without limitation\n * the rights to use, copy, modify, merge, publish, distribute, sublicense,\n * and/or sell copies of the Software, and to permit persons to whom the\n * Software is furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n * DEALINGS IN THE SOFTWARE.\n */\n#define BYTE_OPERATION 0x80 // to use BYTE_READ/WRITE instead of BLOCK_READ/WRITE (cdce913 datasheet, table 8)\nstatic void init_i2c_camera(void)\n{\n// PCA9546A Mux:\n//     Channel 0: HDMIO_DDC   0x01\n//     Channel 1: HDMIO       0x02\n//     Channel 2: HDMII       0x04\n//     Channel 3: PLL-IO      0x08\nstatic unsigned char cmuxdata[] = {8, 8};\nstatic unsigned char cdce913_data[] = {\n    0x00, 0x81,  0x01, 0x01,\n                  // [1:0] - Slave Address A[1:0]=01b\n    //0x02, 0xB4,\n    //0x03, 0x01,\n    0x02, 0xB4,   // [  7] = M1 = 1 (PLL1 Clock)\n                  // [1:0] = PDIV1[9:8] = 0\n    0x03, 0x02,   // [7:0] = PDIV1[7:0] = 2\n    0x04, 0x02,  0x05, 0x50,  0x06, 0x60,  0x07, 0x00,\n    0x08, 0x00,  0x09, 0x00,  0x0A, 0x00,  0x0B, 0x00,\n    0x0C, 0x00,  0x0D, 0x00,  0x0E, 0x00,  0x0F, 0x00,\n    0x10, 0x00,  0x11, 0x00,  0x12, 0x00,  0x13, 0x00,\n    //0x14, 0xED,\n    0x14, 0x6D,   // [  7] = MUX1 = 0 (PLL1)\n                  // [  6] = M2 = 1 (PDIV2)\n                  // [5:4] = M3 = 2 (PDIV3)\n    0x15, 0x02,\n    //0x16, 0x01,\n    //0x17, 0x01,\n    0x16, 0x00,   // [6:0] = PDIV2 = 0 (reset and stand-by)\n    0x17, 0x00,   // [6:0] = PDIV3 = 0 (reset and stand-by)\n    //0x18, 0x00,\n    //0x19, 0x40,\n    //0x1A, 0x02,\n    //0x1B, 0x08,\n                  // PLL1 : Fin=27MHz, M=2, N=11, PDIV=2 Fout=74.25MHz\n                  //        Fvco = 148.5 MHz\n                  //        P = 4 - int(log2(11/2)) = 4 - 2 = 2\n                  //        N'= 11 * 2^2 = 44\n                  //        Q = int(44/2) = 22\n                  //        R = 44 - 2*22 = 0\n    0x18, 0x00,   // [7:0] = PLL1_0N[11:4] = 00000000\n    0x19, 0xB0,   // [7:4] = PLL1_0N[3:0] = 1011\n                  // [3:0] = PLL1_0R[8:5] = 0000\n    0x1A, 0x02,   // [7:3] = PLL1_0R[4:0] = 00000\n                  // [2:0] = PLL1_0Q[5:3] = 010\n    0x1B, 0xC9,   // [7:5] = PLL1_0Q[2:0] = 110\n                  // [4:2] = PLL1_0P[2:0] = 010\n                  // [1:0] = VC01_0_RANGE[1:0] = 01 (125 MHz < Fvco1 < 150 MHz)\n    //0x1C, 0x00,\n    //0x1D, 0x40,\n    //0x1E, 0x02,\n    //0x1F, 0x08,\n                  // PLL1 : Fin=27MHz, M=2, N=11, PDIV=2 Fout=74.25MHz\n                  //        Fvco = 148.5 MHz\n                  //        P = 4 - int(log2(11/2)) = 4 - 2 = 2\n                  //        N'= 11 * 2^2 = 44\n                  //        Q = int(44/2) = 22\n                  //        R = 44 - 2*22 = 0\n    0x1C, 0x00,   // [7:0] = PLL1_1N[11:4] = 00000000\n    0x1D, 0xB0,   // [7:4] = PLL1_1N[3:0] = 1011\n                  // [3:0] = PLL1_1R[8:5] = 0000\n    0x1E, 0x02,   // [7:3] = PLL1_1R[4:0] = 00000\n                  // [2:0] = PLL1_1Q[5:3] = 010\n    0x1F, 0xC9,   // [7:5] = PLL1_1Q[2:0] = 110\n                  // [4:2] = PLL1_1P[2:0] = 010\n                  // [1:0] = VC01_1_RANGE[1:0] = 01 (125 MHz < Fvco1 < 150 MHz)\n    // 148.500000 MHz\n    // PLL1: M = 2, N = 11, Pdiv = 1\n    //       Fin  = 27.000000MHz\n    //       Fvco = Fin * N/M = 148.500000MHz\n    //       Range = 1 (125 MHz <= Fvco < 150 MHz)\n    //       Fout = Fvco / Pdiv = 148.500000MHz\n    //       P = 4 - int(log2(M/N)) = 2\n    //       Np = N * 2^P = 44\n    //       Q = int(Np/M) = 22\n    //       R = Np - M*Q = 0\n    0x02, 0xB4,   // [  7] = M1 = 1 (PLL1 clock)\n                  // [1:0] = Pdiv1[9:8]\n    0x03, 0x01,   // [7:0] = Pdiv1[7:0]\n    0x18, 0x00,   // [7:0] = PLL1_0N[11:4]\n    0x19, 0xB0,   // [7:4] = PLL1_0N[3:0]\n                  // [3:0] = PLL1_0R[8:5]\n    0x1A, 0x02,   // [7:3] = PLL1_0R[4:0]\n                  // [2:0] = PLL1_0Q[5:3]\n    0x1B, 0xC9};  // [7:5] = PLL1_0Q[2:0]\n                  // [4:2] = PLL1_0P[2:0]\n                  // [1:0] = VCO1_0_RANGE[1:0]\n\n    int fd = open(\"/dev/i2c-1\", O_RDWR);\nprintf(\"[%s:%d] /dev/i2c-1 open fd %d\\n\", __FUNCTION__, __LINE__, fd);\n    if (fd < 0)\n        printf(\"[%s] /dev/i2c-1 open failed\\n\", __FUNCTION__);\n    // setup mux for enabling clock generator\n    if (i2c_write_array(fd, 0x70, cmuxdata, sizeof(cmuxdata), 0))\n        printf(\"[%s] write mux failed\\n\", __FUNCTION__);\n    int version = i2c_read_reg(fd, 0x65, 0x00 | BYTE_OPERATION);\nprintf(\"[%s:%d] pllversion %x\\n\", __FUNCTION__, __LINE__, version);\n    // initialize clock generator\n    if (i2c_write_array(fd, 0x65, cdce913_data, sizeof(cdce913_data), BYTE_OPERATION))\n        printf(\"[%s] write data failed\\n\", __FUNCTION__);\n    close(fd);\n}\n"
  },
  {
    "path": "examples/imageon/imageon-clocks.xdc",
    "content": "create_clock -name video_clk -period \"10\" [get_ports \"fmc_video_clk1_v\"]\ncreate_clock -name serpins_clk -period \"10\" [get_ports \"serpins_io_vita_clk_p_v\"]\ncreate_clock -name spi_clk -period \"100\" [get_pins \"ts_0/lImageonCapture_spiController_clockDivider/cntr_reg[9]/Q\"]\n\n"
  },
  {
    "path": "examples/imageon/imageon-fmc.json",
    "content": "{\n    \"*io_vita_clk_pll\": {\n\t\"PIO_DIRECTION\": \"OUTPUT\",\n\t\"fmc\": \"LA13_P\"\n    },\n    \"*io_vita_reset_n\": {\n\t\"PIO_DIRECTION\": \"OUTPUT\",\n\t\"fmc\": \"CLK0_M2C_N\"\n    },\n    \"*io_vita_trigger_0*\": {\n\t\"PIO_DIRECTION\": \"OUTPUT\",\n\t\"fmc\": \"LA14_N\"\n    },\n    \"*io_vita_trigger_1*\": {\n\t\"PIO_DIRECTION\": \"OUTPUT\",\n\t\"fmc\": \"LA14_P\"\n    },\n    \"*io_vita_trigger_2*\": {\n\t\"PIO_DIRECTION\": \"OUTPUT\",\n\t\"fmc\": \"LA13_N\"\n    },\n    \"*io_vita_monitor*[0]\": {\n\t\"PIO_DIRECTION\": \"INPUT\",\n\t\"fmc\": \"LA15_P\"\n    },\n    \"*io_vita_monitor*[1]\": {\n\t\"PIO_DIRECTION\": \"INPUT\",\n\t\"fmc\": \"LA15_N\"\n    },\n    \"CLK_spi_clock\": {\n        \"original_name\": \"io_vita_spi_sclk\",\n\t\"PIO_DIRECTION\": \"OUTPUT\",\n\t\"fmc\": \"LA12_P\"\n    },\n    \"*spi_*sel_n\": {\n\t\"PIO_DIRECTION\": \"OUTPUT\",\n\t\"fmc\": \"LA12_N\"\n    },\n    \"*spi_mosi\": {\n\t\"PIO_DIRECTION\": \"OUTPUT\",\n\t\"fmc\": \"LA11_P\"\n    },\n    \"*miso_v\": {\n\t\"PIO_DIRECTION\": \"INPUT\",\n\t\"fmc\": \"LA11_N\"\n    },\n    \"*io_vita_clk_p_v\": {\n\t\"PIO_DIRECTION\": \"INPUT\",\n\t\"IOSTANDARD\": \"LVDS_25\",\n\t\"DIFF_TERM\": \"TRUE\",\n\t\"fmc\": \"LA00_CC_P\"\n    },\n    \"*io_vita_clk_n_v\": {\n\t\"PIO_DIRECTION\": \"INPUT\",\n\t\"IOSTANDARD\": \"LVDS_25\",\n\t\"DIFF_TERM\": \"TRUE\",\n\t\"fmc\": \"LA00_CC_N\"\n    },\n    \"*io_vita_sync_p*\": {\n\t\"PIO_DIRECTION\": \"INPUT\",\n\t\"IOSTANDARD\": \"LVDS_25\",\n\t\"DIFF_TERM\": \"TRUE\",\n\t\"fmc\": \"LA10_P\"\n    },\n    \"*io_vita_sync_n*\": {\n\t\"PIO_DIRECTION\": \"INPUT\",\n\t\"IOSTANDARD\": \"LVDS_25\",\n\t\"DIFF_TERM\": \"TRUE\",\n\t\"fmc\": \"LA10_N\"\n    },\n    \"*io_vita_data_p_v[0]\": {\n\t\"PIO_DIRECTION\": \"INPUT\",\n\t\"IOSTANDARD\": \"LVDS_25\",\n\t\"DIFF_TERM\": \"TRUE\",\n\t\"fmc\": \"LA09_P\"\n    },\n    \"*io_vita_data_n_v[0]\": {\n\t\"PIO_DIRECTION\": \"INPUT\",\n\t\"IOSTANDARD\": \"LVDS_25\",\n\t\"DIFF_TERM\": \"TRUE\",\n\t\"fmc\": \"LA09_N\"\n    },\n    \"*io_vita_data_p_v[1]\": {\n\t\"PIO_DIRECTION\": \"INPUT\",\n\t\"IOSTANDARD\": \"LVDS_25\",\n\t\"DIFF_TERM\": \"TRUE\",\n\t\"fmc\": \"LA07_P\"\n    },\n    \"*io_vita_data_n_v[1]\": {\n\t\"PIO_DIRECTION\": \"INPUT\",\n\t\"IOSTANDARD\": \"LVDS_25\",\n\t\"DIFF_TERM\": \"TRUE\",\n\t\"fmc\": \"LA07_N\"\n    },\n    \"*io_vita_data_p_v[2]\": {\n\t\"PIO_DIRECTION\": \"INPUT\",\n\t\"IOSTANDARD\": \"LVDS_25\",\n\t\"DIFF_TERM\": \"TRUE\",\n\t\"fmc\": \"LA08_P\"\n    },\n    \"*io_vita_data_n_v[2]\": {\n\t\"PIO_DIRECTION\": \"INPUT\",\n\t\"IOSTANDARD\": \"LVDS_25\",\n\t\"DIFF_TERM\": \"TRUE\",\n\t\"fmc\": \"LA08_N\"\n    },\n    \"*io_vita_data_p_v[3]\": {\n\t\"PIO_DIRECTION\": \"INPUT\",\n\t\"IOSTANDARD\": \"LVDS_25\",\n\t\"DIFF_TERM\": \"TRUE\",\n\t\"fmc\": \"LA05_P\"\n    },\n    \"*io_vita_data_n_v[3]\": {\n\t\"PIO_DIRECTION\": \"INPUT\",\n\t\"IOSTANDARD\": \"LVDS_25\",\n\t\"DIFF_TERM\": \"TRUE\",\n\t\"fmc\": \"LA05_N\"\n    },\n    \"fmc_video_clk1_v\": {\n\t\"PIO_DIRECTION\": \"INPUT\",\n\t\"fmc\": \"CLK0_M2C_P\"\n    },\n    \"*i2c_mux_reset_n\": {\n\t\"PIO_DIRECTION\": \"OUTPUT\",\n\t\"fmc\": \"LA01_CC_N\"\n    },\n    \"I2C1_scl\": {\n\t\"PIO_DIRECTION\": \"BIDIR\",\n\t\"fmc\": \"LA16_P\"\n    },\n    \"I2C1_sda\": {\n\t\"PIO_DIRECTION\": \"BIDIR\",\n\t\"fmc\": \"LA16_N\"\n    },\n    \"CLK_hdmi_clock_if\": {\n\t\"hdmi\": \"clock\"\n    },\n    \"hdmi_hsync\": {\n\t\"hdmi\": \"hsync\"\n    },\n    \"hdmi_vsync\": {\n\t\"hdmi\": \"vsync\"\n    },\n    \"hdmi_de\": {\n\t\"hdmi\": \"de\"\n    },\n    \"hdmi_data[0]\": { \"hdmi\": \"data[0]\" },\n    \"hdmi_data[1]\": { \"hdmi\": \"data[1]\" },\n    \"hdmi_data[2]\": { \"hdmi\": \"data[2]\" },\n    \"hdmi_data[3]\": { \"hdmi\": \"data[3]\" },\n    \"hdmi_data[4]\": { \"hdmi\": \"data[4]\" },\n    \"hdmi_data[5]\": { \"hdmi\": \"data[5]\" },\n    \"hdmi_data[6]\": { \"hdmi\": \"data[6]\" },\n    \"hdmi_data[7]\": { \"hdmi\": \"data[7]\" },\n    \"hdmi_data[8]\": { \"hdmi\": \"data[8]\" },\n    \"hdmi_data[9]\": { \"hdmi\": \"data[9]\" },\n    \"hdmi_data[10]\": { \"hdmi\": \"data[10]\" },\n    \"hdmi_data[11]\": { \"hdmi\": \"data[11]\" },\n    \"hdmi_data[12]\": { \"hdmi\": \"data[12]\" },\n    \"hdmi_data[13]\": { \"hdmi\": \"data[13]\" },\n    \"hdmi_data[14]\": { \"hdmi\": \"data[14]\" },\n    \"hdmi_data[15]\": { \"hdmi\": \"data[15]\" }\n}\n"
  },
  {
    "path": "examples/imageon/imageon-zedboard.json",
    "content": "{\n    \"I2C0_scl\": {\n\t\"i2c0\": \"scl\"\n    },\n    \"I2C0_sda\": {\n\t\"i2c0\": \"sda\"\n    }\n}\n"
  },
  {
    "path": "examples/imageon/testimagecapture.cpp",
    "content": "/* Copyright (c) 2014 Quanta Research Cambridge, Inc\n *\n * Permission is hereby granted, free of charge, to any person obtaining a\n * copy of this software and associated documentation files (the \"Software\"),\n * to deal in the Software without restriction, including without limitation\n * the rights to use, copy, modify, merge, publish, distribute, sublicense,\n * and/or sell copies of the Software, and to permit persons to whom the\n * Software is furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n * DEALINGS IN THE SOFTWARE.\n */\n#include <ctype.h> // isprint, isascii\n#include \"dmaManager.h\"\n#include \"ImageonCaptureRequest.h\"\n#include \"ImageonCaptureIndication.h\"\n#include \"ImageonSerdesRequest.h\"\n#include \"ImageonSerdesIndication.h\"\n#include \"HdmiGeneratorRequest.h\"\n#include \"HdmiGeneratorIndication.h\"\n#include \"i2chdmi.h\"\n#include \"i2ccamera.h\"\n#include \"edid.h\"\n\nstatic ImageonSerdesRequestProxy *serdesdevice;\nstatic HdmiGeneratorRequestProxy *hdmidevice;\nstatic ImageonCaptureRequestProxy *idevice;\nstatic int trace_spi = 0;\nstatic int nlines = 1080;\nstatic int npixels = 1920;\nstatic int fbsize = nlines*npixels*4;\n\n#define DECL(A) \\\n    static sem_t sem_ ## A; \\\n    static uint32_t cv_ ## A;\n\nDECL(iserdes_control)\nDECL(spi_response)\n\n#define GETFN(A) \\\n    static uint32_t read_ ## A (void) \\\n    { \\\n        serdesdevice->get_ ## A(); \\\n        sem_wait(&sem_ ## A); \\\n        return cv_ ## A; \\\n    }\n\nclass ImageonSerdesIndication : public ImageonSerdesIndicationWrapper {\npublic:\n    ImageonSerdesIndication(int id) : ImageonSerdesIndicationWrapper(id) {}\n    void iserdes_control_value ( const uint32_t v ){\n        cv_iserdes_control = v;\n        sem_post(&sem_iserdes_control);\n    }\n    void iserdes_dma ( const uint32_t v ){\nprintf(\"[%s:%d] 0x%x ***************************************************************** \\n\", __FUNCTION__, __LINE__, v);\n    }\n};\n\nclass ImageonCaptureIndication : public ImageonCaptureIndicationWrapper {\npublic:\n    ImageonCaptureIndication(int id) : ImageonCaptureIndicationWrapper(id) {}\n    void spi_response(uint32_t v){\n        //fprintf(stderr, \"spi_response: %x\\n\", v);\n        cv_spi_response = v;\n        sem_post(&sem_spi_response);\n    }\n};\n\nclass HdmiGeneratorIndication: public HdmiGeneratorIndicationWrapper {\n    HdmiGeneratorRequestProxy *hdmiRequest;\npublic:\n    HdmiGeneratorIndication(int id, HdmiGeneratorRequestProxy *proxy) : HdmiGeneratorIndicationWrapper(id), hdmiRequest(proxy) {}\n    virtual void vsync ( uint64_t v, uint32_t w ) {\n        fprintf(stderr, \"[%s:%d] v=%d w=%d\\n\", __FUNCTION__, __LINE__, (uint32_t) v, w);\n        hdmiRequest->waitForVsync(v+1);\n    }\n\n};\n\nstatic void memdump(unsigned char *p, int len, const char *title)\n{\nint i;\n\n    i = 0;\n    while (len > 0) {\n        if (!(i & 0xf)) {\n            if (i > 0)\n                printf(\"\\n\");\n            printf(\"%s: \",title);\n        }\n        printf(\"%02x \", *p++);\n        i++;\n        len--;\n    }\n    printf(\"\\n\");\n}\n\nstatic void init_local_semaphores(void)\n{\n    sem_init(&sem_iserdes_control, 0, 0);\n    sem_init(&sem_spi_response, 0, 0);\n}\nGETFN(iserdes_control)\n\n//#define VITA_ISERDES_CONTROL_REG     0x10\n   #define VITA_ISERDES_RESET_BIT       0x01\n   #define VITA_ISERDES_AUTO_ALIGN_BIT  0x02\n   #define VITA_ISERDES_ALIGN_START_BIT 0x04\n   #define VITA_ISERDES_FIFO_ENABLE_BIT 0x08\n//#define VITA_DECODER_CONTROL_REG           0x20\n   #define VITA_DECODER_RESET_BIT            0x01\n   #define VITA_DECODER_ENABLE_BIT           0x02\n\n#define VITA_SPI_SEQ1_QTY  8\n/* Table 6. enable clock management register upload - part 1 */\nstatic uint16_t vita_spi_seq1[VITA_SPI_SEQ1_QTY][3] = {\n   // Enable Clock Management - Part 1\n   //    V1/SN/SE 10-bit mode with PLL\n   {  2, 0xFFFF,      0}, // Monochrome Sensor\n// {  2, 0xFFFF, 0x0001}, // Color Sensor\n   { 32, 0xFFFF, 0x2004}, // Configure clock management\n   { 20, 0xFFFF,      0}, // Configure clock management\n   { 17, 0xFFFF, 0x2113}, // Configure PLL\n   { 26, 0xFFFF, 0x2280}, // Configure PLL lock detector\n   { 27, 0xFFFF, 0x3D2D}, // Configure PLL lock detector\n   {  8, 0xFFFF,      0}, // Release PLL soft reset\n   { 16, 0xFFFF, 0x0003}  // Enable PLL\n};\n\n#define VITA_SPI_SEQ3_QTY  3\n/* Table 7. enable clock management register upload - part 2 */\nstatic uint16_t vita_spi_seq3[VITA_SPI_SEQ3_QTY][3] = {\n   // Enable Clock Management - Part 2\n   //    V1/SN/SE 10-bit mode with PLL\n   {  9, 0xFFFF,      0}, // Release clock generator soft reset\n   { 32, 0xFFFF, 0x2006}, // Enable logic clock\n   { 34, 0xFFFF, 0x0001}  // Enable logic blocks\n};\n\n#define VITA_SPI_SEQ4_QTY  17\n/* Table 8. required register upload */\nstatic uint16_t vita_spi_seq4[VITA_SPI_SEQ4_QTY][3] = {\n   // Required Register Upload\n   //    V1/SN/SE 10-bit mode with PLL\n   { 41, 0xFFFF,      0}, // Configure image core\n   {129, 0x2000,      0}, // [13] 10-bit mode\n   { 65, 0xFFFF, 0x288B}, // Configure CP biasing\n   { 66, 0xFFFF, 0x53C6}, // Configure AFE biasing\n   { 67, 0xFFFF, 0x0344}, // Configure MUX biasing\n   { 68, 0xFFFF, 0x0085}, // Configure LVDS biasing\n   { 70, 0xFFFF, 0x4888}, // Configure reserved register\n   { 81, 0xFFFF, 0x86A1}, // Configure reserved register\n   {128, 0xFFFF, 0x460F}, // Configure  calibration\n   {176, 0xFFFF, 0x00F5}, // Configure AEC\n   {180, 0xFFFF, 0x00FD}, // Configure AEC\n   {181, 0xFFFF, 0x0144}, // Configure AEC\n   {194, 0xFFFF, 0x0404}, // Configure sequencer\n   {218, 0xFFFF, 0x160B}, // Configure sequencer\n   {224, 0xFFFF, 0x3E13}, // Configure sequencer\n   {391, 0xFFFF, 0x1010}, // Configure sequencer\n   {456, 0xFFFF, 0x0386}  // Configure sequencer\n};\n\n#define VITA_SPI_SEQ5_QTY  7\n/* Table 9. soft power up register uploads for mode dependent registers */\nstatic uint16_t vita_spi_seq5[VITA_SPI_SEQ5_QTY][3] = {\n   // Soft Power-Up\n   //    V1/SN/SE 10-bit mode with PLL\n   { 32, 0xFFFF, 0x2007}, // Enable analog clock distribution\n   { 10, 0xFFFF,      0}, // Release soft reset state\n   { 64, 0xFFFF, 0x0001}, // Enable biasing block\n   { 72, 0xFFFF, 0x0203}, // Enable charge pump\n   { 40, 0xFFFF, 0x0003}, // Enable column multiplexer\n   { 48, 0xFFFF, 0x0001}, // Enable AFE\n   {112, 0xFFFF, 0x0007}  // Enable LVDS transmitters\n};\n\n//#define VITA_SPI_SEQ6_QTY  1\n#define VITA_SPI_SEQ6_QTY  2\n/* Table 10. enable sequencer register upload */\nstatic uint16_t vita_spi_seq6[VITA_SPI_SEQ6_QTY][3] = {\n// {192, 0x0001, 0x0001}  // [0] Enable Sequencer\n#if defined(TRIGGERED_MASTER_MODE)\n   {192, 0x0051, 0x0011}, // [0] Enable Sequencer\n                          // [4] triggered_mode = on\n                          // [6] xsm_delay_enable = off\n   {193, 0xFF00,      0}  // [15:8] xsm_delay = 0x00\n#elif defined(STRETCH_VITA_HTIMING)\n   {192, 0x3841, 0x3841},\n// {192, 0x0041, 0x0041}, // [0] Enable Sequencer\n                          // [6] xsm_delay_enable = on\n   {193, 0xFF00, 0x0400}  // [15:8] xsm_delay = 0x04\n#else\n   {192, 0x0001, 0x0001}, // [0] Enable Sequencer\n                        // [6] xsm_delay_enable = off\n   {193, 0xFF00,      0}  // [15:8] xsm_delay = 0x00\n#endif\n};\n\n#define VITA_AUTOEXP_ON_QTY  1\nstatic uint16_t vita_autoexp_on_seq[VITA_AUTOEXP_ON_QTY][3] = {\n   // Auto-Exposure ON\n   {160, 0x0001, 0x0001} // [4] Auto Exposure enable\n   };\n\n#define VITA_ROI0_CROP_1080P_QTY  2\nstatic uint16_t vita_roi0_crop_1080p_seq[VITA_ROI0_CROP_1080P_QTY][3] = {\n   // Crop ROI0 from 1920x1200 to 1920x1080\n   //   R257[10:0] y_start = 60 (0x3C)\n   //   R258[10:0] y_end   = 60+1080 = 1140 (0x474)\n   {257, 0xFFFF, 0x003C},\n   {258, 0xFFFF, 0x0474} };\n\n#define VITA_MULT_TIMER_LINE_RESOLUTION_QTY  1\nstatic uint16_t vita_mult_timer_line_resolution_seq[VITA_MULT_TIMER_LINE_RESOLUTION_QTY][3] = {\n   // R199[15:0] mult_timer = (1920+88+44+148)/4 = 2200/4 = 550 (0x0226)\n   //199, 0xFFFF, 0x0226\n   // R199[15:0] mult_timer = (1920+88+44+132)/4 = 2184/4 = 546 (0x0222)\n   {199, 0xFFFF, 0x0222} };\n\nstatic uint32_t spi_transfer (uint32_t v)\n{\n    if (trace_spi)\n        printf(\"SPITRANSFER: %x\\n\", v);\n    idevice->put_spi_request(v);\n    sem_wait(&sem_spi_response);\n    return cv_spi_response;\n}\nstatic uint32_t vita_spi_read_internal(uint32_t uAddr)\n{\n    return spi_transfer(uAddr<<17);\n}\nstatic int vita_spi_write(uint32_t uAddr, uint16_t uData)\n{\n    uint32_t prev = 0;\n    if (trace_spi)\n        prev = vita_spi_read_internal(uAddr);\n    spi_transfer(uAddr<<17 | 1 <<16 | uData);\n    if (trace_spi)\n        printf(\"SPIWRITE: [%x] %x -> %x %x\\n\", uAddr, prev, uData, vita_spi_read_internal(uAddr));\n    return 1;\n}\n\nstatic uint16_t vita_spi_read(uint32_t uAddr)\n{\n    uint32_t ret = vita_spi_read_internal(uAddr);\n    if (trace_spi)\n        printf(\"SPIREAD: [%x] %x\\n\", uAddr, ret);\n    //printf(\"[%s:%d] return %x\\n\", __FUNCTION__, __LINE__, ret);\n    return ret;\n}\n\n/******************************************************************************\n* This function performs a sequence of SPI write transactions.\n******************************************************************************/\nstatic void vita_spi_write_sequence(uint16_t pConfig[][3], uint32_t uLength)\n{\n   uint16_t uData;\n   int i;\n\n   for ( i = 0; i < (int)uLength; i++) {\n      if ( pConfig[i][1] != 0xFFFF) {\n         uData = vita_spi_read(pConfig[i][0]) & ~pConfig[i][1];\n         printf( \"\\t                    0x%04X\\n\", pConfig[i][1]);\n     }\n   }\n   for ( i = 0; i < (int)uLength; i++) {\n      if ( pConfig[i][1] == 0xFFFF)\n         uData = pConfig[i][2];\n      else {\n         uData = vita_spi_read(pConfig[i][0]) & ~pConfig[i][1];\n         uData |=  pConfig[i][2];\n      }\n      vita_spi_write(pConfig[i][0], uData); usleep(100);\n   }\n}\n\nstatic void fmc_imageon_demo_enable_ipipe( void)\n{\n   // VITA-2000 Initialization\n   printf( \"FMC-IMAGEON VITA Initialization ...\\n\");\n   uint16_t uData;\n   uint32_t uStatus;\n   int timeout;\n   serdesdevice->set_serdes_training(0x03A6);\nuint32_t uManualTap = 25;\n   printf( \"VITA ISERDES - Setting Manual Tap to 0x%08X\\n\", uManualTap);\n   serdesdevice->set_serdes_manual_tap(uManualTap);\n\n   printf(\"VITA SPI Sequence 0 - Assert RESET_N pin\\n\");\n   serdesdevice->set_iserdes_control( VITA_ISERDES_RESET_BIT);\n   serdesdevice->set_decoder_control( VITA_DECODER_RESET_BIT);\n\n   usleep(10); // 10 usec\n   serdesdevice->set_iserdes_control( 0);\n   serdesdevice->set_decoder_control( 0);\n   //jca sleep(1); // 1 sec (time to get clocks to lock)\n   uData = vita_spi_read(0);\nprintf(\"[%s:%d] %x\\n\", __FUNCTION__, __LINE__, uData);\n   switch ( uData) {\n   case 0:\n       printf( \"\\tVITA Sensor absent\\n\");\n       break;\n   case 0x560D:\n       printf( \"\\tVITA-1300 Sensor detected\\n\");\n       break;\n   case 0x5614:\n       printf( \"\\tVITA-2000 Sensor detected\\n\");\n       break;\n   case 0x5632:\n       printf( \"\\tVITA-5000 Sensor detected\\n\");\n       break;\n   case 0x56FA:\n       printf( \"\\tVITA-25K Sensor detected\\n\");\n       break;\n   default:\n       printf( \"\\tERROR: Unknown CHIP_ID !!!\\n\");\n       break;\n   }\n   if ( uData != 0x5614) {\n      printf( \"\\tERROR: Absent or unsupported VITA sensor !!!\\n\");\n      return;\n   }\n   printf(\"VITA SPI Sequence 1 - Enable Clock Management - Part 1\\n\");\n   vita_spi_write_sequence(vita_spi_seq1, VITA_SPI_SEQ1_QTY);\n   {\n   uint16_t uLock = 0;\n   printf(\"VITA SPI Sequence 2 - Verify PLL Lock Indicator\\n\");\n   timeout = 10;\n   while ( !(uLock) && --timeout) {\n      usleep(100000);\n      uLock = vita_spi_read(24);\n   }\n   if ( !timeout) {\n       printf( \"\\tERROR: Timed Out while waiting for PLL lock to assert !!!\\n\");\n      return;\n   }\n   }\n   printf(\"VITA SPI Sequence 3 - Enable Clock Management - Part 2\\n\");\n   vita_spi_write_sequence(vita_spi_seq3, VITA_SPI_SEQ3_QTY);\n   printf(\"VITA SPI Sequence 4 - Required Register Upload\\n\");\n   vita_spi_write_sequence(vita_spi_seq4, VITA_SPI_SEQ4_QTY);\n   printf(\"VITA SPI Sequence 5 - Soft Power-Up\\n\");\n   vita_spi_write_sequence(vita_spi_seq5, VITA_SPI_SEQ5_QTY);\n   uStatus = read_iserdes_control();\n   printf( \"VITA ISERDES - Status = 0x%08X\\n\", uStatus);\n   uStatus = read_iserdes_control();\n   printf( \"VITA ISERDES - Status = 0x%08X\\n\", uStatus);\n   uStatus = read_iserdes_control();\n   printf( \"VITA ISERDES - Status = 0x%08X\\n\", uStatus);\n   printf( \"VITA ISERDES - Align Start\\n\");\n   serdesdevice->set_iserdes_control( VITA_ISERDES_ALIGN_START_BIT);\n   printf( \"VITA ISERDES - Waiting for ALIGN_BUSY to assert\\n\");\n   uStatus = read_iserdes_control();\n   printf( \"VITA ISERDES - Status = 0x%08X\\n\", uStatus);\n   timeout = 9;\n   while ( !(uStatus & 0x0200) && --timeout) {\n       uStatus = read_iserdes_control();\n       printf( \"VITA ISERDES - Status = 0x%08X\\n\", uStatus);\n       //usleep(1);\n   }\n   if ( !timeout) {\n       printf( \"\\tTimed Out !!!\\n\");\n       return;\n   }\n   serdesdevice->set_iserdes_control( 0);\n   printf( \"VITA ISERDES - Waiting for ALIGN_BUSY to de-assert\\n\");\n   uStatus = read_iserdes_control();\n   printf( \"VITA ISERDES - Status = 0x%08X\\n\", uStatus);\n   timeout = 9;\n   while ( (uStatus & 0x0200) && --timeout) {\n       uStatus = read_iserdes_control();\n       printf( \"VITA ISERDES - Status = 0x%08X\\n\", uStatus);\n       usleep(1);\n   }\n   if ( !timeout)\n       printf( \"\\tTimed Out !!!\\n\");\n   uStatus = read_iserdes_control();\n   printf( \"VITA ISERDES - Status = 0x%08X\\n\", uStatus);\n   vita_spi_write_sequence(vita_roi0_crop_1080p_seq, VITA_ROI0_CROP_1080P_QTY);\n   vita_spi_write_sequence(vita_mult_timer_line_resolution_seq, VITA_MULT_TIMER_LINE_RESOLUTION_QTY);\n   vita_spi_write_sequence(vita_autoexp_on_seq, VITA_AUTOEXP_ON_QTY);\n   vita_spi_write_sequence(vita_spi_seq6, VITA_SPI_SEQ6_QTY);\n   serdesdevice->set_iserdes_control( VITA_ISERDES_FIFO_ENABLE_BIT);\n   serdesdevice->set_decoder_control(VITA_DECODER_ENABLE_BIT);\n   //jca sleep(1);\n   vita_spi_write(192, 0); usleep(100);\n   vita_spi_write(193, 0x0400); usleep(100);\n   vita_spi_write(192, 0x40); usleep(100);\n   vita_spi_write(199, 1); usleep(100);\n   vita_spi_write(200, 0); usleep(100);\n   vita_spi_write(194, 0); usleep(100);\n   vita_spi_write(257, 0x3C); usleep(100);\n   vita_spi_write(258, 0x0474); usleep(100);\n   vita_spi_write(160, 0x10); usleep(100);\n\n   uint32_t trigDutyCycle    = 90; // exposure time is 90% of frame time (ie. 15msec)\n   uint32_t vitaTrigGenDefaultFreq = (((1920+88+44+148)*(1080+4+5+36))>>2) - 2;\n   idevice->set_trigger_cnt((vitaTrigGenDefaultFreq * (100-trigDutyCycle))/100 + 1);\n   vita_spi_write(194, 0x0400);\n   vita_spi_write(0x29, 0x0700);\n   uint16_t vspi_data = vita_spi_read(192) | 0x71; usleep(100);\n   vspi_data |= (4 << 11); // monitor0 Frame Start, monitor1 row-overhead-time (ROT)\n   vita_spi_write(192, vspi_data); usleep(100);\n   fprintf(stderr, \"VITA SPI 192 %x\\n\", vspi_data);\n   //jca usleep(10000);\n}\n\n#define DMA_BUFFER_SIZE 0x1240000\n\nint main(int argc, const char **argv)\n{\n    init_local_semaphores();\n    DmaManager *dma = platformInit();\n    serdesdevice = new ImageonSerdesRequestProxy(IfcNames_ImageonSerdesRequestS2H);\n    hdmidevice = new HdmiGeneratorRequestProxy(IfcNames_HdmiGeneratorRequestS2H);\n    idevice = new ImageonCaptureRequestProxy(IfcNames_ImageonCaptureRequestS2H);\n    \n    ImageonSerdesIndication imageonSerdesIndication(IfcNames_ImageonSerdesIndicationH2S);\n    ImageonCaptureIndication imageonCaptureIndication(IfcNames_ImageonCaptureIndicationH2S);\n    HdmiGeneratorIndication hdmiIndication(IfcNames_HdmiGeneratorIndicationH2S, hdmidevice);\n    // read out monitor EDID from ADV7511\n    struct edid edid;\n    init_i2c_hdmi();\n    int i2cfd = open(\"/dev/i2c-0\", O_RDWR);\n    fprintf(stderr, \"Monitor EDID:\\n\");\n    for (int i = 0; i < 256; i++) {\n      edid.raw[i] = i2c_read_reg(i2cfd, 0x3f, i);\n      fprintf(stderr, \" %02x\", edid.raw[i]);\n      if ((i % 16) == 15) {\n        fprintf(stderr, \" \");\n        for (int j = i-15; j <= i; j++) {\n          unsigned char c = edid.raw[j];\n          fprintf(stderr, \"%c\", (isprint(c) && isascii(c)) ? c : '.');\n        }\n        fprintf(stderr, \"\\n\");\n      }\n    }\n    close(i2cfd);\n    parseEdid(edid);\n\n    // for surfaceflinger \n    long actualFrequency = 0;\n    int status;\n    status = setClockFrequency(0, 100000000, &actualFrequency);\n    printf(\"[%s:%d] setClockFrequency 0 100000000 status=%d actualfreq=%ld\\n\", __FUNCTION__, __LINE__, status, actualFrequency);\n    status = setClockFrequency(1, 160000000, &actualFrequency);\n    printf(\"[%s:%d] setClockFrequency 1 160000000 status=%d actualfreq=%ld\\n\", __FUNCTION__, __LINE__, status, actualFrequency);\n    status = setClockFrequency(3, 200000000, &actualFrequency);\n    printf(\"[%s:%d] setClockFrequency 3 200000000 status=%d actualfreq=%ld\\n\", __FUNCTION__, __LINE__, status, actualFrequency);\n    printf(\"[%s:%d] before set_i2c_mux_reset_n\\n\", __FUNCTION__, __LINE__);\n    idevice->set_i2c_mux_reset_n(1);\n    printf(\"[%s:%d] before setDeLine/Pixel\\n\", __FUNCTION__, __LINE__);\n    for (int i = 0; i < 4; i++) {\n      int pixclk = (long)edid.timing[i].pixclk * 10000;\n        nlines = edid.timing[i].nlines;    // number of visible lines\n        npixels = edid.timing[i].npixels;\n        int vblank = edid.timing[i].blines; // number of blanking lines\n        int hblank = edid.timing[i].bpixels;\n        int vsyncoff = edid.timing[i].vsyncoff; // number of lines in FrontPorch (within blanking)\n        int hsyncoff = edid.timing[i].hsyncoff;\n        int vsyncwidth = edid.timing[i].vsyncwidth; // width of Sync (within blanking)\n        int hsyncwidth = edid.timing[i].hsyncwidth;\n\n        fprintf(stderr, \"lines %d, pixels %d, vblank %d, hblank %d, vwidth %d, hwidth %d\\n\",\n             nlines, npixels, vblank, hblank, vsyncwidth, hsyncwidth);\n        fprintf(stderr, \"Using pixclk %d calc_pixclk %ld npixels %d nlines %d\\n\",\n                pixclk,\n                60l * (long)(hblank + npixels) * (long)(vblank + nlines),\n                npixels, nlines);\n      if ((pixclk > 0) && (pixclk < 148000000)) {\n        status = setClockFrequency(1, pixclk, 0);\n\nhblank--; // needed on zc702\n        hdmidevice->setDeLine(vsyncoff,           // End of FrontPorch\n                                vsyncoff+vsyncwidth,// End of Sync\n                                vblank,             // Start of Visible (start of BackPorch)\n                                vblank + nlines, vblank + nlines / 2); // End\n        hdmidevice->setDePixel(hsyncoff,\n                                hsyncoff+hsyncwidth, hblank,\n                                hblank + npixels, hblank + npixels / 2);\n        i2c_hdmi_start();\n        break;\n      }\n    }\n\n    fbsize = nlines*npixels*4;\n\n    int srcAlloc = portalAlloc(DMA_BUFFER_SIZE, 0);\n    unsigned int *srcBuffer = (unsigned int *)portalMmap(srcAlloc, DMA_BUFFER_SIZE);\n    printf(\"[%s:%d] before dma->reference\\n\", __FUNCTION__, __LINE__);\n    memset(srcBuffer, 0xff, 16);\n    portalCacheFlush(srcAlloc, srcBuffer, DMA_BUFFER_SIZE, 1);\n    unsigned int ref_srcAlloc = dma->reference(srcAlloc);\n    printf(\"[%s:%d] before setTestPattern\\n\", __FUNCTION__, __LINE__);\n    hdmidevice->setTestPattern(1);\n\n    //ret = fmc_iic_axi_init(uBaseAddr_IIC_FmcImageon);\n    //fmc_iic_axi_GpoWrite(uBaseAddr_IIC_FmcImageon, fmc_iic_axi_GpoRead(uBaseAddr_IIC_FmcImageon) | 2);\n    idevice->set_host_oe(1);\n\nprintf(\"[%s:%d] before i2c_camera\\n\", __FUNCTION__, __LINE__);\n    init_i2c_camera();\nprintf(\"[%s:%d] before i2c_hdmi\\n\", __FUNCTION__, __LINE__);\n    init_i2c_hdmi();\nprintf(\"[%s:%d] after i2c_hdmi\\n\", __FUNCTION__, __LINE__);\n    //init_vclk();\n//jca sleep(5);\nprintf(\"[%s:%d] now displaying test pattern\\n\", __FUNCTION__, __LINE__);\nsleep(20);\n    hdmidevice->setTestPattern(0);\n\n    // Reset DCMs\n    /* puts the DCM_0 PCORE into reset */\n    //fmc_iic_axi_GpoWrite(uBaseAddr_IIC_FmcImageon, fmc_iic_axi_GpoRead(uBaseAddr_IIC_FmcImageon) | 4);\n    //jca usleep(200000);\n    /* releases the DCM_0 PCORE from reset */\n    //fmc_iic_axi_GpoWrite(uBaseAddr_IIC_FmcImageon, fmc_iic_axi_GpoRead(uBaseAddr_IIC_FmcImageon) & ~4);\n\n    //jca usleep(500000);\n    // FMC-IMAGEON VITA Receiver Initialization\n    printf( \"FMC-IMAGEON VITA Receiver Initialization ...\\n\");\n    idevice->startWrite(ref_srcAlloc, DMA_BUFFER_SIZE);\n    fmc_imageon_demo_enable_ipipe();\n    printf(\"[%s:%d] passed fmc_imageon_demo_init\\n\", __FUNCTION__, __LINE__);\n    //usleep(200000);\n    hdmidevice->waitForVsync(0);\n    //jca usleep(2000000);\n    printf(\"[%s:%d] before startWrite\\n\", __FUNCTION__, __LINE__);\n    //idevice->startWrite(ref_srcAlloc, DMA_BUFFER_SIZE);\n    int counter = 0;\n    while (1/*getchar() != EOF*/) {\n        printf(\"[%s:%d] iserdes %x\\n\", __FUNCTION__, __LINE__, read_iserdes_control());\n        static int regids[] = {24, 97, 186, 0};\n        int i;\n        for (i = 0; regids[i]; i++)\n            printf(\"[%s:%d] spi %d. %x\\n\", __FUNCTION__, __LINE__, regids[i], vita_spi_read(regids[i]));\n        printf(\"counter %d\\n\", counter);\n        if (counter == 1 && argc > 1) {\n            portalCacheFlush(srcAlloc, srcBuffer, DMA_BUFFER_SIZE, 1);\n            int fd = creat(\"tmp.outfile\", 0666);\n            int cnt = write(fd, srcBuffer, DMA_BUFFER_SIZE);\n            printf(\"[%s:%d] length written %d.\\n\", __FUNCTION__, __LINE__, cnt);\n            close(fd);\n        }\n        counter++;\n        memdump((unsigned char *)srcBuffer, 32, \"MEM\");\n\tusleep(1000000);\n    }\n    return 0;\n}\n"
  },
  {
    "path": "examples/leds/LedController.bsv",
    "content": "\n// Copyright (c) 2014 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\nimport FIFO::*;\nimport GetPut::*;\nimport Leds::*;\n\ntypedef struct {\n   Bit#(8) leds;\n   Bit#(32) duration;\n   } LedControllerCmd deriving (Bits);\n\ninterface LedControllerRequest;\n   method Action setLeds(Bit#(8) v, Bit#(32) duration);\nendinterface\n\ninterface LedPins;\n   interface LEDS leds;\n   interface Clock deleteme_unused_clock;\n   interface Reset deleteme_unused_reset;\nendinterface\n\ninterface LedController;\n   interface LedControllerRequest request;\n   interface LedPins leds;\nendinterface\n\nmodule mkLedController(LedController);\n   Clock defaultClock <- exposeCurrentClock();\n   Reset defaultReset <- exposeCurrentReset();\n   Reg#(Bit#(8)) ledsValue <- mkReg(0);\n   Reg#(Bit#(32)) remainingDuration <- mkReg(0);\n\n   FIFO#(LedControllerCmd) ledsCmdFifo <- mkSizedFIFO(32);\n\n   rule updateLeds;\n      let duration = remainingDuration;\n      if (duration == 0) begin\n\t let cmd <- toGet(ledsCmdFifo).get();\n\t $display(\"ledsValue <= %b\", cmd.leds);\n\t ledsValue <= cmd.leds;\n\t duration = cmd.duration;\n      end\n      else begin\n\t duration = duration - 1;\n      end\n      remainingDuration <= duration;\n   endrule\n\n   interface LedControllerRequest request;\n       method Action setLeds(Bit#(8) v, Bit#(32) duration);\n\t  $display(\"Enqueing v=%d duration=%d\", v, duration);\n\t  ledsCmdFifo.enq(LedControllerCmd { leds: v, duration: duration });\n       endmethod\n   endinterface\n   interface LedPins leds;\n      interface LEDS leds;\n         method leds = truncate(ledsValue._read);\n      endinterface\n      interface deleteme_unused_clock = defaultClock;\n      interface deleteme_unused_reset = defaultReset;\n   endinterface\nendmodule\n"
  },
  {
    "path": "examples/leds/Makefile",
    "content": "CONNECTALDIR?=../..\nS2H_INTERFACES = LedControllerRequest:LedController.request\n\nBSVFILES = LedController.bsv\nCPPFILES= testleds.cpp\n\nPIN_TYPE = LedPins\nPIN_TYPE_INCLUDE = LedController\nPINOUT_FILE = pinout.json\nAUTOTOP = --interface pins:LedController.leds\n\ninclude $(CONNECTALDIR)/Makefile.connectal\n"
  },
  {
    "path": "examples/leds/pinout.json",
    "content": "{\n    \"leds[0]\" : {\n\t\"PIO_DIRECTION\": \"OUTPUT\",\n\t\"leds\" : \"L0\"\n    },\n    \"leds[1]\" : {\n\t\"PIO_DIRECTION\": \"OUTPUT\",\n\t\"leds\" : \"L1\"\n    },\n    \"leds[2]\" : {\n\t\"PIO_DIRECTION\": \"OUTPUT\",\n\t\"leds\" : \"L2\"\n    },\n    \"leds[3]\" : {\n\t\"PIO_DIRECTION\": \"OUTPUT\",\n\t\"leds\" : \"L3\"\n    },\n    \"leds[4]\" : {\n\t\"PIO_DIRECTION\": \"OUTPUT\",\n\t\"leds\" : \"L4\"\n    },\n    \"leds[5]\" : {\n\t\"PIO_DIRECTION\": \"OUTPUT\",\n\t\"leds\" : \"L5\"\n    },\n    \"leds[6]\" : {\n\t\"PIO_DIRECTION\": \"OUTPUT\",\n\t\"leds\" : \"L6\"\n    },\n    \"leds[7]\" : {\n\t\"PIO_DIRECTION\": \"OUTPUT\",\n\t\"leds\" : \"L7\"\n    }\n}\n\n\n"
  },
  {
    "path": "examples/leds/testleds.cpp",
    "content": "/* Copyright (c) 2014 Quanta Research Cambridge, Inc\n *\n * Permission is hereby granted, free of charge, to any person obtaining a\n * copy of this software and associated documentation files (the \"Software\"),\n * to deal in the Software without restriction, including without limitation\n * the rights to use, copy, modify, merge, publish, distribute, sublicense,\n * and/or sell copies of the Software, and to permit persons to whom the\n * Software is furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n * DEALINGS IN THE SOFTWARE.\n */\n\n#include \"LedControllerRequest.h\"\n\nint main(int argc, const char **argv)\n{\n  LedControllerRequestProxy *device = new LedControllerRequestProxy(IfcNames_LedControllerRequestS2H);\n\n  printf(\"Starting LED test\");\n#ifdef SIMULATION\n  // SIMULATION does not run very many cycles per second\n  int blinkinterval = 10;\n#else\n  int blinkinterval = 100000000; // 100MHz cycles\n#endif\n  int blinkon = 10; // 1010\n  int blinkoff = 5; // 0101\n  int sleepinterval = 1; // seconds\n  for (int i = 0; i < 20; i++) {\n    printf(\"blink %d\", blinkon);\n    device->setLeds(blinkon, blinkinterval);\n    sleep(sleepinterval);\n    printf(\"blink off %d\", blinkoff);\n    device->setLeds(blinkoff, blinkinterval);\n    sleep(sleepinterval);\n  }\n  printf(\"Done.\\n\");\n}\n"
  },
  {
    "path": "examples/linking/GetInverse.v",
    "content": "\n`ifdef BSV_ASSIGNMENT_DELAY\n`else\n  `define BSV_ASSIGNMENT_DELAY\n`endif\n\n`ifdef BSV_POSITIVE_RESET\n  `define BSV_RESET_VALUE 1'b1\n  `define BSV_RESET_EDGE posedge\n`else\n  `define BSV_RESET_VALUE 1'b0\n  `define BSV_RESET_EDGE negedge\n`endif\n\nmodule GetInverse(CLK,\n\t\t  RST,\n\n\t\t  get,\n\t\t  EN_get,\n\t\t  RDY_get,\n\n\t\t  put,\n\t\t  EN_put,\n\t\t  RDY_put\n\t\t  );\n   parameter DATA_WIDTH = 1;\n\n   input CLK;\n   input RST;\n   output [DATA_WIDTH-1,0] get;\n   input  [DATA_WIDTH-1,0] put;\n   input \t\t   EN_get;\n   input \t\t   EN_put;\n   output \t\t   RDY_get;\n   output \t\t   RDY_put;\n\n   // will this work?\n   assign get = put;\n   assign RDY_get = EN_put;\n   assign RDY_put = EN_get;\n   \nendmodule // GetInverse\n"
  },
  {
    "path": "examples/linking/LinkerLib.bsv",
    "content": "// Generic definitions that should go in a shared library.\ntypeclass InverseIFC#(type a, type b)\n  dependencies (a determines b,\n                b determines a);\nendtypeclass\n\n\ninterface GetInverse#(type a);\n   interface Get#(a) mod;\n   interface Put#(a) inverse;\nendinterface\n\ninterface PutInverse#(type a);\n   interface Put#(a) mod;\n   interface Get#(a) inverse;\nendinterface\n\nimport \"BVI\" GetInverse =\nmodule mkGetInverseBvi(GetInverse#(Bits#(asz)));\n   parameter DATA_SIZE = asz;\n   default_clock (CLK);\n   default_reset (RST);\n   interface Get mod;\n      method get get() enable(EN_get) ready (RDY_get);\n   endinterface\n   interface Put inverse;\n      method put(put) enable (EN_put) ready (RDY_put);\n   endinterface\nendmodule\nmodule mkGetInverse(GetInverse#(a)) provisos (Bits#(a, asz));\n   inverter <- mkGetInverseBvi();\n   interface Get mod;\n      method a get();\n\t let v <- inverter.mod.get();\n\t return unpack(v);\n      endmethod\n   endinterface\n   interface Put inverse;\n      method Action put(a v);\n\t inverter.inverse.put(pack(v));\n      endmethod\n   endinterface\nendmodule\n\nimport \"BVI\" PutInverse =\nmodule mkPutInverseBvi(PutInverse#(Bits#(asz)));\n   parameter DATA_SIZE = asz;\n   default_clock (CLK);\n   default_reset (RST);\n   interface Put mod;\n      method put(put) enable(EN_put) ready (RDY_put);\n   endinterface\n   interface Get inverse;\n      method get get() enable (EN_get) ready (RDY_get);\n   endinterface\nendmodule\nmodule mkPutInverse(PutInverse#(a)) provisos (Bits#(a, asz));\n   inverter <- mkPutInverseBvi();\n   interface Put mod;\n      method Action put(a v);\n\t inverter.mod.put(pack(v));\n      endmethod\n   endinterface\n   interface Get inverse;\n      method a get();\n\t let v <- inverter.inverse.get();\n\t return unpack(v);\n      endmethod\n   endinterface\nendmodule\n\ninterface Inverter#(type ifcType, type invifcType);\n  interface ifcType mod;\n  interface invifcType inverse;\nendinterface\n    \ninterface SynthInverter0IFC#(type ifcType);\n  interface ifcType mod;\nendinterface\n  \ninterface SynthInverter1IFC#(type param1, type ifcType);\n  interface param1  arg1;\n  interface ifcType mod;\nendinterface  \n  \ninterface SynthInverter2IFC#(type param1, type param2, type ifcType);\n  interface param1 arg1;\n  interface param2 arg2;\n  interface ifcType mod;\nendinterface    \n  \ninterface SynthInverter3IFC#(type param1, type param2, type param3, type ifcType);\n  interface param1 arg1;\n  interface param2 arg2;\n  interface param3 arg3;\n  interface ifcType mod;\nendinterface     \n"
  },
  {
    "path": "examples/linking/Makefile",
    "content": "clean:\n\trm -f mk*.v *.b[iao]\n"
  },
  {
    "path": "examples/linking/Processor.bsv",
    "content": "interface Cache;\n   interface Put#(CacheRequest) request;\n   interface Get#(CacheResponse) response;\nendinterface   \n\n// we want to be able to synthesize this, but it has interface parameters\nmodule mkProcessor#(Cache cache, Peripherals peripherals)(Processor);\n   rule foo;\n      cache.request.put(req);\n   endrule\n   rule bar;\n      let response <- cache.response.get();\n   endrule\nendmodule\n\n// original top level\nmodule mkTopLevel(Pins);\n   Memory memory <- mkMemory();\n   Cache  cache  <- mkCache(memory); // standard parameter use example\n\n   Vector#(NumProcessors,Processor) processors <- replicateM(mkProcessor(cache)); // \n   \n   Vector#(NumCaches, Memory) mems <- replicateM(mkMemory);\n   Vector#(NumCaches, Cache)  caches <- mapM(mkCache, mems);\n  \n   interface pins = memory.pins;\nendmodule\n"
  },
  {
    "path": "examples/linking/ProcessorTop.bsv",
    "content": "import Processor_Generated::*;\n\n//====================================================================================================================\n\nmodule mkProcessorTop(Pins);\n   Memory memory <- mkMemory();\n   Cache  cache  <- mkCache(memory); // actually uses the wrapper from Processor_Generated.bsv\n\n   Vector#(NumProcessors,Processor) processors <- replicateM(mkProcessor(cache)); // same here\n\n   Vector#(NumCaches, Memory) mems <- replicateM(mkMemory);\n   Vector#(NumCaches, Cache)  caches <- mapM(mkCache, mems); // and here\n\n   interface mod;\n     interface Pins pins = memory.pins;\n   endinterface\nendmodule\n"
  },
  {
    "path": "examples/linking/Processor_Generated.bsv",
    "content": "// To be auto generated from Linking.bsv\n\nimport LinkerLib::*;\nimport Processor::*;\n  \n//================================================================================\n// Parts corresponding to Cache interface\n\ninterface CacheInverse;\n   interface GetInverse#(CacheRequest)   request;\n   interface PutInverse#(CacheResponse) response;\nendinterface\n\ninstance InverseIFC#(Cache, CacheInverse);\nendinstance\n\n//define how to connect Cache and it's inverse\ninstance Connectable#(Cache, CacheInverse);\n   module mkConnection#(Cache x, CacheInverse y)(Empty);\n     mkConnection( x.request,  y.request);\n     mkConnection(x.response, y.response);\n   endmodule\nendinstance  \n    \n// module to create Cache Inverter. This needs to have the same schedulign restrictions as the\n// initial parameter\nmodule mkCacheInverter(Inverter#(Cache, CacheInverse));\n  GetInverse  requestlink <- mkGetInverter(); // one for each sub component in Cache interface\n  PutInverse responselink <- mkPutInverter();\n  \n  interface Cache mod;\n    interface Get  request = requestlink.mod;\n    interface Put response = responselink.mod;  \n  endinterface\n  \n  interface CacheInverse inverse;\n    interface GetInverse  request = requestlink.inverse;\n    interface PutInverse response = responselink.inverse;  \n  endinterface  \nendmodule  \n    \n//================================================================================\n// Parts corresponding to mkCache    \n\n//linked version of mkCache. Hooks ups missing memory module\nmodule mkCacheSynth(SynthInverter1IFC#(MemoryInverse, Cache));\n  // parameter setup\n  let memoryInverter <- mkMemoryInverter();\n  // build base module (use original version)\n  let cache <- Cache::mkCache(memoryInverter.mod);\n  // hook up interface\n  interface arg1 = memoryInverter.inverse;\n  interface mod  = cache;\nendmodule\n\nimport \"BVI\" mkCacheSynth =\nmodule mkCacheBVI(Cache);\n//...\nendmodule\n\nmodule mkCache#(Memory arg1)(Cache);\n  let x <- mkCacheBVI; // It would be great if we could check schedule here. \n  mkConnection(x.arg1, arg1);\n  return x.mod;\nendmodule\n  \n  \n//=============================================================================================================\n// Parts Corresponding to mkProcessor\n  \n// This is the module we can synthesize\nmodule mkProcessorSynth(SynthInverter2IFC#(CacheInverse, PeripheralsInverse, Processor));\n   //instantiate param versions of modules\n   let cacheparam       <- mkCacheInverter();\n   let cache = cacheparam.mod;\n   let peripheralsparam  <- mkPeripheralsInverter();\n   let peripherals = peripheralsparam.mod;  \n   //instantiate actual module\n   let processor <- Processor::mkProcessor(cache, peripherals);\n   //hook params and return ifc\n   interface mod        = processor;\n   interface arg1       = cacheparam.inverse;\n   interface arg2       = peripheralsparam.inverse;\nendmodule\n   \n// to enable separate compilation\nimport \"BVI\" mkProcessorSynth =\nmodule mkProcessorBVI(ProcessorBvi);\nendmodule\n\nmodule mkProcessor#(Cache arg1, Peripherals arg2)(Processor);\n   let x <- mkProcessorBVI();\n   mkConnection(cache, x.arg1);\n   mkConnection(peripherals, x.arg2);  \n   return x.mod;\nendmodule  \n    \n"
  },
  {
    "path": "examples/matmul/Makefile",
    "content": "\nCONNECTALDIR?=../..\nBSCFLAGS=-aggressive-conditions -show-schedule -keep-fires -p +:../paclib\n\nMMDIR=../matmul\nRBMDIR=../rbm\nTESTCPPFILES=testmm.cpp\nCONNECTALFLAGS = -D J_VALUE=1 -D K_VALUE=1 -D N_VALUE=1 -D DataBusWidth=32\n\ninclude $(MMDIR)/Makefile.mm\ninclude $(MMDIR)/Makefile.mmif\ninclude $(CONNECTALDIR)/Makefile.connectal\n"
  },
  {
    "path": "examples/matmul/Makefile.mm",
    "content": "\nBSVFILES   +=  $(CONNECTALDIR)/lib/rbm/bsv/RbmTypes.bsv $(CONNECTALDIR)/lib/rbm/bsv/Timer.bsv\nCPPFILES   +=  $(CONNECTALDIR)/lib/matmul/cpp/portalmat.cpp $(TESTCPPFILES)\n\nCONNECTALFLAGS  +=  -D IMPORT_HOSTIF -D MATRIX_TN -D MATMUL_HACK\nCONNECTALFLAGS  +=  --bscflags=\"+RTS -K26777216 -RTS\"\nCONNECTALFLAGS  +=  --bsvpath $(CONNECTALDIR)/lib/matmul/bsv\nCONNECTALFLAGS  += -I$(CONNECTALDIR)/lib/matmul/cpp\n\nDma = Dma\nPINS = Std\n\nFAMILY=$(shell echo $(BOARD) | sed 's/z.*/zynq/' | sed 's/k.*/kintex/' | sed 's/v.*/virtex/' | sed 's/miniitx.*/zynq/')\n\n##\n## To build testmm for Android on Zynq\n## cd $(CONNECTALDIR); cd ..; git clone git://github.com:cambridgehackers/opencv-android-sdk.git\n##\n\nifdef CUDA_PERF_TEST\nOPENCVDIR=/scratch/opencv-cuda/opencv-2.4.9/install/\nCONNECTALFLAGS  += -I$(OPENCVDIR)/include\nCONNECTALFLAGS  += -L$(OPENCVDIR)/lib\nCONNECTALFLAGS  += -L/usr/local/cuda-5.5/lib64\nCONNECTALFLAGS  += --stl=stlport_static\nCONNECTALFLAGS  += --clib z\nCONNECTALFLAGS  += --clib cuda\nCONNECTALFLAGS  += --clib cudart\nCONNECTALFLAGS  += --clib nppi\nCONNECTALFLAGS  += --clib nppc\nCONNECTALFLAGS  += --clib npps\nCONNECTALFLAGS  += --clib cufft\nCONNECTALFLAGS  += --clib opencv_core\nCONNECTALFLAGS  += --clib opencv_gpu\nCONNECTALFLAGS  += --clib opencv_imgproc\nCONNECTALFLAGS  += --clib opencv_core\nCONNECTALFLAGS  += --clib opencv_objdetect\nCONNECTALFLAGS  += --clib opencv_imgproc\nCONNECTALFLAGS  += --clib cublas\nCPPFILES   +=  $(CONNECTALDIR)/lib/matmul/cpp/cuda.cpp \nelse\nCONNECTALFLAGS  +=  --clib opencv_core --stl=stlport_static\nendif\n\nifeq (zynq,$(FAMILY))\nNDK_DIR=$(shell ndk-which gcc | sed 's:toolchains.*::')\nOPENCVDIR=$(CONNECTALDIR)/../opencv-android-sdk/sdk/native/\nCONNECTALFLAGS += -I$(CONNECTALDIR)/lib/matmul/cpp -I$(OPENCVDIR)/jni/include -L$(OPENCVDIR)/libs/armeabi-v7a -lz\nCONNECTALFLAGS += -S$(NDK_DIR)/sources/cxx-stl/stlport/libs/armeabi-v7a/libstlport_static.a\nPLATFORM_NUMBER_OF_MASTERS=2\nendif\nifeq (bluesim,$(FAMILY))\nPLATFORM_NUMBER_OF_MASTERS=2\nendif\n\nsynth-ip.tcl:\n\tln -svf $(CONNECTALDIR)/examples/matmul/synth-ip.tcl .\n\nprebuild:: synth-ip.tcl\n\tif [ \"$(BOARD)\" != \"bluesim\" -a \"$(BOARD)\" != verilator ] ; then cd $(BOARD); BUILDCACHE_CACHEDIR=$(BUILDCACHE_CACHEDIR) $(BUILDCACHE) vivado -notrace -mode batch -source ../synth-ip.tcl; fi\n\nFPGAMAKE_CONNECTALFLAGS += -P mkMmTile --xci=$(IPDIR)/$(BOARD)/fp_add/fp_add.xci --xci=$(IPDIR)/$(BOARD)/fp_mul/fp_mul.xci\n\n"
  },
  {
    "path": "examples/matmul/Makefile.mmif",
    "content": "S2H_INTERFACES +=  MmRequestTN:MatrixTN.mmRequest:host TimerRequest:MatrixTN.timerRequest\nH2S_INTERFACES +=  MatrixTN\\#\\(TDiv\\#\\(DataBusWidth,32\\)\\):MmIndication,TimerIndication:host\nMEM_READ_INTERFACES = lMatrixTN.readClients\nMEM_WRITE_INTERFACES = lMatrixTN.writeClients\n\n"
  },
  {
    "path": "examples/matmul/clocks.tcl",
    "content": "\nforeach {pat} {CLK_GATE_hdmi_clock_if CLK_*deleteme_unused_clock* CLK_GATE_*deleteme_unused_clock* RST_N_*deleteme_unused_reset*} {\n    foreach {net} [get_nets $pat] {\n\tdisconnect_net -net $net -objects [get_pins -of_objects $net]\n    }\n}\n"
  },
  {
    "path": "examples/matmul/design-vc707.tcl",
    "content": "###############################################################\n###   Tcl Variables\n###############################################################\n#set tclParams [list <param1> <value> <param2> <value> ... <paramN> <value>]\nset tclParams [list place.closeImportedSites  1 \\\n                    hd.StrictContainRouting   1 \\\n              ]\n\n#Define location for \"Tcl\" directory. Defaults to \"../Tcl\"\nset tclHome \"../Tcl\"\nif {[file exists $tclHome]} {\n   set tclDir $tclHome\n} elseif {[file exists \"./Tcl\"]} {\n   set tclDir  \"./Tcl\"\n} else {\n   error \"ERROR: No valid location found for required Tcl scripts. Set \\$tclDir in design.tcl to a valid location.\"\n}\n\n###############################################################\n### Part Variables - Define Device, Package, Speedgrade \n###############################################################\nset device       \"xc7vx485t\"\nset package      \"ffg1761\"\nset speed        \"-2\"\nset part         $device$package$speed\n\n###############################################################\n###  Setup Variables\n###############################################################\n####flow control\nset run.topSynth   1\nset run.oocSynth   1\nset run.tdImpl     1\nset run.oocImpl    0\nset run.topImpl    0\nset run.flatImpl   0\n\n####Report and DCP controls - values: 0-required min; 1-few extra; 2-all\nset verbose      1\nset dcpLevel     1\n\n####Output Directories\nset synthDir  \"./Synth\"\nset implDir   \"./Implement\"\nset dcpDir    \"./Checkpoint\"\n\n####Input Directories\nset srcDir     \"./vc707\"\nset rtlDir     \"$srcDir/verilog\"\nset prjDir     \"$srcDir/prj\"\nset xdcDir     \"$srcDir/constraints\"\nset coreDir    \"$srcDir/cores\"\nset netlistDir \"$srcDir/netlist\"\n\n####Source required Tcl Procs\nsource $tclDir/design_utils.tcl\nsource $tclDir/synth_utils.tcl\nsource $tclDir/impl_utils.tcl\nsource $tclDir/hd_floorplan_utils.tcl\n\n###############################################################\n### Top Definition\n###############################################################\nset top \"mkPcieTop\"\nadd_module $top\nset_attribute module $top    top_level     1\nset_attribute module $top    vlog          [concat [glob $rtlDir/top/*.v] [glob $rtlDir/lib/*.v] ]\nset_attribute module $top    ip            [glob /scratch/jamey/connectal/generated/xilinx/zc706/*/*.xci]\n#set_attribute module $top    vlog_headers  [glob $rtlDir/top/*Stub.v]\nset_attribute module $top    synth         ${run.topSynth}\n\nadd_implementation $top\nset_attribute impl $top      top           $top\nset_attribute impl $top      implXDC       [glob $xdcDir/*.xdc]\nset_attribute impl $top      impl          ${run.topImpl}\nset_attribute impl $top      hd.impl       1\n\n####################################################################\n### OOC Module Definition and OOC Implementation for each instance\n####################################################################\nset module1 \"pcie_7x_0\"\nadd_module $module1\nset_attribute module $module1 vlog          [concat [glob $rtlDir/lib/*.v] [glob $rtlDir/mmtile/*.v]]\nset_attribute module $module1 ip            [glob /scratch/jamey/connectal/generated/xilinx/vc707/*/*.xci]\nset_attribute module $module1 synth        ${run.oocSynth}\n\nset instance \"top_top_mm_dmaMMF_dmaMMF_mmTiles_0\"\nadd_ooc_implementation $instance\nset_attribute ooc $instance   module       $module1\nset_attribute ooc $instance   inst         $instance\nset_attribute ooc $instance   hierInst     $instance\nset_attribute ooc $instance   implXDC      [list $xdcDir/${instance}_phys.xdc \\\n\t\t\t\t\t\t $xdcDir/${instance}_ooc_timing.xdc \\\n\t\t\t\t\t\t $xdcDir/${instance}_ooc_budget.xdc \\\n\t\t\t\t\t\t $xdcDir/${instance}_ooc_optimize.xdc \\\n\t\t\t\t\t\t]\nset_attribute ooc $instance   impl         ${run.oocImpl}\nset_attribute ooc $instance   preservation routing\n\n####################################################################\n### Create TopDown implementation run \n####################################################################\nset module1File \"$synthDir/$module1/${module1}_synth.dcp\"\nadd_implementation TopDown\nset_attribute impl TopDown      top          $top\nset_attribute impl TopDown      implXDC      [list $xdcDir/${top}_flpn.xdc] \nset_attribute impl TopDown      td.impl      1\nset_attribute impl TopDown      cores        [list $module1File                          \\\n                                                   [get_attribute module $top cores]     \\\n                                                   [get_attribute module $module1 cores] \\\n                                             ] \nset_attribute impl TopDown      impl         ${run.tdImpl}\nset_attribute impl TopDown      route        0\n\n####################################################################\n### Create Flat implementation run \n####################################################################\nadd_implementation Flat\nset_attribute impl Flat         top          $top\nset_attribute impl Flat         implXDC      [list $xdcDir/${top}_flpn.xdc] \nset_attribute impl Flat         cores        [list $module1File                          \\\n                                                   [get_attribute module $top cores]     \\\n                                                   [get_attribute module $module1 cores] \\\n                                             ] \nset_attribute impl Flat         impl         ${run.flatImpl}\n\n########################################################################\n### Task / flow portion\n########################################################################\n\n# Build the designs\nsource $tclDir/run.tcl\n\nexit\n"
  },
  {
    "path": "examples/matmul/design.tcl",
    "content": "###############################################################\n###   Tcl Variables\n###############################################################\n#set tclParams [list <param1> <value> <param2> <value> ... <paramN> <value>]\nset tclParams [list place.closeImportedSites  1 \\\n                    hd.StrictContainRouting   1 \\\n              ]\n\n#Define location for \"Tcl\" directory. Defaults to \"../Tcl\"\nset tclHome \"../Tcl\"\nif {[file exists $tclHome]} {\n   set tclDir $tclHome\n} elseif {[file exists \"./Tcl\"]} {\n   set tclDir  \"./Tcl\"\n} else {\n   error \"ERROR: No valid location found for required Tcl scripts. Set \\$tclDir in design.tcl to a valid location.\"\n}\n\n###############################################################\n### Part Variables - Define Device, Package, Speedgrade \n###############################################################\nset device       \"xc7z045\"\nset package      \"ffg900\"\nset speed        \"-2\"\nset part         $device$package$speed\n\n###############################################################\n###  Setup Variables\n###############################################################\n####flow control\nset run.topSynth   0\nset run.oocSynth   0\nset run.tdImpl     0\nset run.oocImpl    1\nset run.topImpl    1\nset run.flatImpl   0\n\n####Report and DCP controls - values: 0-required min; 1-few extra; 2-all\nset verbose      1\nset dcpLevel     1\n\n####Output Directories\nset synthDir  \"./Synth\"\nset implDir   \"./Implement\"\nset dcpDir    \"./Checkpoint\"\n\n####Input Directories\nset srcDir     \"./zc706\"\nset rtlDir     \"$srcDir/verilog\"\nset prjDir     \"$srcDir/prj\"\nset xdcDir     \"$srcDir/constraints\"\nset coreDir    \"$srcDir/cores\"\nset netlistDir \"$srcDir/netlist\"\n\n####Source required Tcl Procs\nsource $tclDir/design_utils.tcl\nsource $tclDir/synth_utils.tcl\nsource $tclDir/impl_utils.tcl\nsource $tclDir/hd_floorplan_utils.tcl\n\n###############################################################\n### Top Definition\n###############################################################\nset top \"mkZynqTop\"\nadd_module $top\nset_attribute module $top    top_level     1\nset_attribute module $top    vlog          [concat [glob $rtlDir/top/*.v] [glob $rtlDir/lib/*.v] ]\nset_attribute module $top    ip            [glob /scratch/jamey/connectal/generated/xilinx/zc706/*/*.xci]\n#set_attribute module $top    vlog_headers  [glob $rtlDir/top/*Stub.v]\nset_attribute module $top    synth         ${run.topSynth}\n\nadd_implementation $top\nset_attribute impl $top      top           $top\nset_attribute impl $top      implXDC       [glob $xdcDir/*.xdc]\nset_attribute impl $top      impl          ${run.topImpl}\nset_attribute impl $top      hd.impl       1\n\n####################################################################\n### OOC Module Definition and OOC Implementation for each instance\n####################################################################\nset module1 \"mkMmTile\"\nadd_module $module1\nset_attribute module $module1 vlog          [concat [glob $rtlDir/lib/*.v] [glob $rtlDir/mmtile/*.v]]\nset_attribute module $module1 ip            [glob /scratch/jamey/connectal/generated/xilinx/zc706/*/*.xci]\nset_attribute module $module1 synth        ${run.oocSynth}\n\nset instance \"top_top_mm_dmaMMF_dmaMMF_mmTiles_0\"\nadd_ooc_implementation $instance\nset_attribute ooc $instance   module       $module1\nset_attribute ooc $instance   inst         $instance\nset_attribute ooc $instance   hierInst     $instance\nset_attribute ooc $instance   implXDC      [list $xdcDir/${instance}_phys.xdc \\\n\t\t\t\t\t\t $xdcDir/${instance}_ooc_timing.xdc \\\n\t\t\t\t\t\t $xdcDir/${instance}_ooc_budget.xdc \\\n\t\t\t\t\t\t $xdcDir/${instance}_ooc_optimize.xdc \\\n\t\t\t\t\t\t]\nset_attribute ooc $instance   impl         ${run.oocImpl}\nset_attribute ooc $instance   preservation routing\n\n####################################################################\n### Create TopDown implementation run \n####################################################################\nset module1File \"$synthDir/$module1/${module1}_synth.dcp\"\nadd_implementation TopDown\nset_attribute impl TopDown      top          $top\nset_attribute impl TopDown      implXDC      [list $xdcDir/${top}_flpn.xdc] \nset_attribute impl TopDown      td.impl      1\nset_attribute impl TopDown      cores        [list $module1File                          \\\n                                                   [get_attribute module $top cores]     \\\n                                                   [get_attribute module $module1 cores] \\\n                                             ] \nset_attribute impl TopDown      impl         ${run.tdImpl}\nset_attribute impl TopDown      route        0\n\n####################################################################\n### Create Flat implementation run \n####################################################################\nadd_implementation Flat\nset_attribute impl Flat         top          $top\nset_attribute impl Flat         implXDC      [list $xdcDir/${top}_flpn.xdc] \nset_attribute impl Flat         cores        [list $module1File                          \\\n                                                   [get_attribute module $top cores]     \\\n                                                   [get_attribute module $module1 cores] \\\n                                             ] \nset_attribute impl Flat         impl         ${run.flatImpl}\n\n########################################################################\n### Task / flow portion\n########################################################################\n\n# Build the designs\nsource $tclDir/run.tcl\n\nexit\n"
  },
  {
    "path": "examples/matmul/mkZynqTop_flpn.xdc",
    "content": "create_pblock mmtile_0\nresize_pblock mmtile_0 -add {SLICE_X96Y270:SLICE_X171Y335 DSP48_X4Y108:DSP48_X6Y133 RAMB18_X5Y108:RAMB18_X8Y133 RAMB36_X5Y54:RAMB36_X8Y66}\nendgroup\nadd_cells_to_pblock mmtile_0 [get_cells [list top_top_mm_dmaMMF_dmaMMF_mmTiles_0]] -clear_locs\n"
  },
  {
    "path": "examples/matmul/perf.txt",
    "content": "These measurements based on \n  * dbn 9587023178c555dc8028cabb910e4571ae910798\n  * connectal 53a86e0d2e5dfbe6a034d166c99aa39b999afd71\n\nBluesim:\n\nN=2, J=1, K=4\n    MemLatency=1, FPLatency=1\n    NumMasters=1\n    64x64 * 64x64\n    mmfDone cycles=183352\n    macs 262144 cycles 183352.000000 macs/cycle: 1.429731\n    memory read beats 163840 utilization (beats/cycle): 0.893582\n    memory write beats 2048 utilization (beats/cycle): 0.011170\n\nN=2, J=1, K=4\n    MemLatency=1, FPLatency=1\n    NumMasters=5\n    64x64 * 64x64\n    mmfDone cycles=147480\n    macs 262144 cycles 147480.000000 macs/cycle: 1.777488\n    memory read beats 163840 utilization (beats/cycle): 1.110930\n    memory write beats 2048 utilization (beats/cycle): 0.013887\n\nN=4, J=1, K=16\n    MemLatency=1, FPLatency=1\n    NumMasters=17\n    64x64 * 64x64\n    mmfDone cycles=147483\n    macs 262144 cycles 147483.000000 macs/cycle: 1.777452\n    memory read beats 69632 utilization (beats/cycle): 0.472136\n    memory write beats 1024 utilization (beats/cycle): 0.006943\n\nN=4, J=1, K=16\n    MemLatency=1, FPLatency=1\n    NumMasters=1\n    64x64 * 64x64\n    mmfDone cycles=79674\n    macs 262144 cycles 79674.000000 macs/cycle: 3.290208\n    memory read beats 69632 utilization (beats/cycle): 0.873961\n    memory write beats 1024 utilization (beats/cycle): 0.012852\n\nN=4, J=1, K=32\n    MemLatency=1, FPLatency=1\n    NumMasters=1\n    64x64 * 64x64\n    mmfDone cycles=76689\n    macs 262144 cycles 76689.000000 macs/cycle: 3.418274\n    memory read beats 67584 utilization (beats/cycle): 0.881274\n    memory write beats 1024 utilization (beats/cycle): 0.013353\n\n\nZC702, 100MHz:\n    N=2, J=1, K=4\n    MemLatency=?, FPLatency=5\n    NumMasters=1\n    64x64 * 64x64\n    mmfDone cycles=189029\n    macs 262144 cycles 189029.000000 macs/cycle: 1.386793\n    memory read beats 163840 utilization (beats/cycle): 0.866745\n    memory write beats 2048 utilization (beats/cycle): 0.010834\n\n============================================================\n\nBluesim\n    N=2, J=4, K=4\n    MemLatency=1, NumMasters=1\n    mmfDone cycles=19876\n    macs 262144 cycles 19876.000000 macs/cycle: 13.188972\n    memory read beats 16384 utilization (beats/cycle): 0.824311\n    memory write beats 1024 utilization (beats/cycle): 0.051519\n\n    N=2, J=8, K=8\n    MemLatency=1, NumMasters=1\n    mmfDone cycles=34715\n    macs 262144 cycles 34715.000000 macs/cycle: 7.551318\n    memory read beats 32768 utilization (beats/cycle): 0.943915\n    memory write beats 2048 utilization (beats/cycle): 0.058995\n\n    N=2, J=16, K=16\n    MemLatency=1, NumMasters=1\n    mmfDone cycles=17291\n    macs 262144 cycles 17291.000000 macs/cycle: 15.160720\n    memory read beats 16384 utilization (beats/cycle): 0.947545\n    memory write beats 2048 utilization (beats/cycle): 0.118443\n\n    N=4, J=4, K=4\n    MemLatency=1, NumMasters=1\n    mmfDone cycles=36942\n    macs 262144 cycles 36942.000000 macs/cycle: 7.096097\n    memory read beats 32768 utilization (beats/cycle): 0.887012\n    memory write beats 1024 utilization (beats/cycle): 0.027719\n\n    N=4, J=8, K=8\n    MemLatency=1, NumMasters=1\n    mmfDone cycles=18793\n    macs 262144 cycles 18793.000000 macs/cycle: 13.949023\n    memory read beats 16384 utilization (beats/cycle): 0.871814\n    memory write beats 1024 utilization (beats/cycle): 0.054488\n\n    N=4, J=16, K=16\n    MemLatency=1, NumMasters=1\n    *failed to build*\n\nZC706, 100MHz:\n    N=2, J=4, K=4\n    MemLatency=?, NumMasters=1\n    mmfDone cycles=195439\n    macs 262144 cycles 195439.000000 macs/cycle: 1.341309, 134 MFLOPs\n    memory read beats 163840 utilization (beats/cycle): 0.838318\n    memory write beats 2048 utilization (beats/cycle): 0.010479\n\n\n    N=2, J=4, K=4\n    MemLatency=?, NumMasters=4\n    mmfDone cycles=68374\n    macs 262144 cycles 68374.000000 macs/cycle: 3.833972, 383 MFLOPs\n    memory read beats 65536 utilization (beats/cycle): 0.958493\n    memory write beats 2048 utilization (beats/cycle): 0.029953\n\n    N=2, J=8, K=4\n    MemLatency=?, NumMasters=4\n    mmfDone cycles=46017\n    macs 262144 cycles 46017.000000 macs/cycle: 5.696677, 570 MFLOPS\n    memory read beats 49152 utilization (beats/cycle): 1.068127\n    memory write beats 2048 utilization (beats/cycle): 0.044505\n\n    N=2, J=8, K=4\n    MemLatency=?, NumMasters=4\n    mmfDone cycles=41844\n    macs 262144 cycles 41844.000000 macs/cycle: 6.264793, 626 MFLOPS\n    memory read beats 32768 utilization (beats/cycle): 0.783099\n    memory write beats 2048 utilization (beats/cycle): 0.048944\n\n============================================================\nBluesim:\n\n    N=2, J=8, K=8\n    MemLatency=1, NumMasters=4\n\n    N=2, J=16, K=16, 64x64\n    MemLatency=1, NumMasters=4\n    mmfDone cycles=21048\n    macs 262144 cycles 21048.000000 macs/cycle: 12.454580\n    memory read beats 16384 utilization (beats/cycle): 0.778411\n    memory write beats 2048 utilization (beats/cycle): 0.097301\n\n    N=2, J=16, K=16, 256x256\n    MemLatency=1, NumMasters=4\n    mmfDone cycles=1131864\n    macs 16777216 cycles 1131864.000000 macs/cycle: 14.822643\n    memory read beats 1048576 utilization (beats/cycle): 0.926415\n    memory write beats 32768 utilization (beats/cycle): 0.028950\n\nZC706, 100MHz:\n\n    N=2, J=8, K=8\n    MemLatency=?, NumMasters=4\n    mmfDone cycles=61676\n    macs 262144 cycles 61676.000000 macs/cycle: 4.250340 425 MFLOPs\n    memory read beats 32768 utilization (beats/cycle): 0.531293\n    memory write beats 2048 utilization (beats/cycle): 0.033206\n"
  },
  {
    "path": "examples/matmul/synth-ip.tcl",
    "content": "source \"board.tcl\"\nsource \"$connectaldir/scripts/connectal-synth-ip.tcl\"\n\nconnectal_synth_ip floating_point 7.0 fp_add [list CONFIG.Axi_Optimize_Goal {Performance} CONFIG.Maximum_Latency {false} CONFIG.Has_ARESETN {true}]\nconnectal_synth_ip floating_point 7.0 fp_mul [list CONFIG.Operation_Type {Multiply} CONFIG.Axi_Optimize_Goal {Resources} CONFIG.Maximum_Latency {false} CONFIG.Has_ARESETN {true}]\n"
  },
  {
    "path": "examples/matmul/testmm.cpp",
    "content": "\n// Copyright (c) 2014 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\n#ifdef MATRIX_NT\n#include \"MmRequestNT.h\"\nMmRequestNTProxy *mmdevice = 0;\n#else\n#ifdef MATRIX_TN\n#include \"MmRequestTN.h\"\nMmRequestTNProxy *mmdevice = 0;\n#endif\n#endif\n#include <MmIndication.h>\n#include <dmaManager.h>\n#include <errno.h>\n#include <math.h> // frexp(), fabs()\n#include <assert.h>\n#include \"portalmat.h\"\n\nstatic int verbose = 0;\n\n#ifdef CUDA_PERF_TEST\nvoid cuda_test();\nlong int cuda_mm(cv::Mat& src1, cv::Mat& src2, cv::Mat& dst);\n#endif\n\n\nvoid *dbgThread(void *)\n{\n  while (1) {\n    sleep(2);\n    mmdevice->debug();\n  }\n  return 0;\n}\n\nbool compare(cv::Mat& m1, cv::Mat& m2, float epsilon)\n{\n  bool rv = (m1.rows == m2.rows);\n  rv &= (m1.cols == m2.cols);\n  for(int i = 0; i < m1.rows; i++){\n    for(int j = 0; j < m1.cols; j++) {\n      float err = fabs(m1.at<float>(i,j)-m2.at<float>(i,j))/m1.at<float>(i,j);\n      bool pass = (epsilon > err);\n      if (verbose && !pass) fprintf(stderr, \"%f %f\\n\", m1.at<float>(i,j), m2.at<float>(i,j));\n      rv &= pass;\n    }\n  }\n  return rv;\n}\n\nint main(int argc, const char **argv)\n{\n  fprintf(stderr, \"%s %s\\n\", __DATE__, __TIME__);\n  bool sane = 1;\n#define LARGE_MAT\n#ifdef LARGE_MAT\n#ifdef SIMULATION\n  int A = 64;\n  int B = 256;\n#else\n  int A = 256;\n  int B = 2048;\n#endif\n  if (argc > 1) {\n    B = strtoul(argv[1], 0, 0);\n    A = 2*B;\n  }\n  srand(A*B);\n  cv::Mat m1(A,B,CV_32F);\n  cv::Mat m2(B,A,CV_32F);\n  for(int a = 0; a < A; a++){\n    for(int b = 0; b < B; b++){\n      float v = (float)(rand() % 10);\n      m2.at<float>(b,a) = (A*B)+v;\n      m1.at<float>(a,b) = v;\n    }\n  }\n#else\n  cv::Mat m1 = (cv::Mat_<float>(4,8) <<\n\t\t11,12,13,14,15,16,17,18,\n\t\t21,22,23,24,25,26,27,28,\n\t\t31,32,33,34,35,36,37,38,\n\t\t41,42,43,44,45,46,47,48\n\t\t);\n  cv::Mat m2 = (cv::Mat_<float>(8,4) <<\n\t\t51,62,53,54,\n\t\t55,56,57,58,\n\t\t61,62,63,64,\n\t\t65,66,67,68,\n\t\t71,72,73,74,\n\t\t75,76,77,78,\n\t\t81,82,83,84,\n\t\t85,86,87,88\n\t\t);\n#endif\n\n#ifndef CUDA_PERF_TEST\n#ifdef MATRIX_NT\n  mmdevice = new MmRequestNTProxy(IfcNames_MmRequestNTS2H);\n#else\n#ifdef MATRIX_TN\n  mmdevice = new MmRequestTNProxy(IfcNames_MmRequestTNS2H);\n#endif\n#endif\n  MmIndication *mmdeviceIndication = new MmIndication(IfcNames_MmIndicationH2S);\n  //TimerRequestProxy *timerdevice = new TimerRequestProxy(IfcNames_TimerRequestPortalS2H);\n  TimerIndication timerdeviceIndication(IfcNames_TimerIndicationH2S);\n    DmaManager *dma = platformInit();\n\n  if(sem_init(&mul_sem, 1, 0)){\n    fprintf(stderr, \"failed to init mul_sem\\n\");\n    return -1;\n  }\n\n  long req_freq = 100000000;\n  long freq = 0;\n  setClockFrequency(0, req_freq, &freq);\n  fprintf(stderr, \"Requested FCLK[0]=%ld actually %ld\\n\", req_freq, freq);\n\n  matAllocator = new PortalMatAllocator(dma);\n  FILE *octave_file = fopen(\"foo.m\", \"w\");\n\n  fprintf(stderr, \"OpenCV matmul\\n\");\n  portalTimerStart(0);\n  cv::Mat  m3 = m1 * m2;\n  //uint64_t opencv_hw_cycles = portalTimerLap(0);\n\n  PortalMat tm3;\n  fprintf(stderr, \"Naive matmul\\n\");\n  portalTimerStart(0);\n  tm3.naive_mul(m1,m2, octave_file);\n  //uint64_t naive_hw_cycles = portalTimerLap(0);\n\n  if (1) {\n    fprintf(stderr, \"DumpMat\\n\");\n    dumpMatOctave<float>(\"m1\",  \"%10.5f\", m1,  octave_file);\n    dumpMatOctave<float>(\"m2\",  \"%10.5f\", m2,  octave_file);\n    dumpMatOctave<float>(\"m3\",  \"%10.5f\", m3,  octave_file);\n    dumpMatOctave<float>(\"tm3\", \"%10.5f\", tm3, octave_file);\n    fclose(octave_file);\n    sane = tm3.compare(m3, 0, 0, 0.0001, 0, false);\n    fprintf(stderr, \"sane=%d\\n\", sane);\n    fflush(stdout);\n  }\n\n#ifdef MATRIX_TN\n  fprintf(stderr, \"pm1t\\n\");\n  PortalMat pm1t(m1.t());\n  fprintf(stderr, \"pm2\\n\");\n  PortalMat pm2(m2);\n  pm1t.reference();\n  pm2.reference();\n#else\n#ifdef MATRIX_NT\n  fprintf(stderr, \"pm1\\n\");\n  PortalMat pm1(m1);\n  fprintf(stderr, \"pm2t\\n\");\n  PortalMat pm2t(m2.t());\n  pm1.reference();\n  pm2t.reference();\n#endif\n#endif\n  PortalMat pm3;\n  pm3.create(m1.rows, m2.cols, CV_32F);\n  pm3.reference();\n\n  // we invoke .reference on the matrices in advance \n  // in order to avoid counting the elapsed time for\n  // performance analysis.  This is not strictly necessary\n  // as all the portalmat methods make sure a valid \n  // reference is available before invoking the hardware\n\n  pthread_t dbgtid;\n  fprintf(stderr, \"creating debug thread\\n\");\n\n  if(pthread_create(&dbgtid, NULL,  dbgThread, NULL)){\n   fprintf(stderr, \"error creating debug thread\\n\");\n   exit(1);\n  }\n\n  fprintf(stderr, \"HW matmul\\n\");\n  portalTimerStart(0);\n#ifdef MATRIX_TN\n  pm3.multf(pm1t, pm2, mmdeviceIndication);\n#else\n#ifdef MATRIX_NT\n  pm3.multf(pm1, pm2t, mmdeviceIndication);\n#endif\n#endif\n#if 0\n  //uint64_t hw_cycles = portalTimerLap(0); \n  uint64_t read_beats = hostMemServerIndication.getMemoryTraffic(ChannelType_Read);\n  uint64_t write_beats = hostMemServerIndication.getMemoryTraffic(ChannelType_Write);\n  float read_util = (float)read_beats/(float)mmdeviceIndication->ccnt;\n  float write_util = (float)write_beats/(float)mmdeviceIndication->ccnt;\n  float read_bw = read_util * N_VALUE * 4 * (float)freq / 1.0e9;\n  float write_bw = write_util * N_VALUE * 4 * (float)freq / 1.0e9;\n  float macs = m1.rows * m2.rows * m2.cols;\n  fprintf(stderr, \"Bus frequency %f MHz\\n\", (float)freq / 1.0e6);\n  fprintf(stderr, \"memory read  beats %f utilization %f (beats/cycle), bandwidth %f (GB/s)\\n\", (float)read_beats, read_util, read_bw);\n  fprintf(stderr, \"memory write beats %f utilization %f (beats/cycle), bandwidth %f (GB/s)\\n\", (float)write_beats, write_util, write_bw);\n  fprintf(stderr, \"Throughput %f macs/cycle %f GFLOP/s\\n\",\n\t  (float)macs / (float)mmdeviceIndication->ccnt,\n\t  2.0 * (float)macs / (float)mmdeviceIndication->ccnt * freq / 1.0e9);\n  fprintf(stderr, \"Time %f cycles, opencv matmul %f cycles (speedup %f), naive matmul %f cycles (speedup %f)\\n\",\n\t  (float)mmdeviceIndication->ccnt,\n\t  (float)opencv_hw_cycles, (float)opencv_hw_cycles/(float)mmdeviceIndication->ccnt,\n\t  (float)naive_hw_cycles, (float)naive_hw_cycles/(float)mmdeviceIndication->ccnt);\n#endif\n\n  if (0) {\n    dumpMat<float>(\"pm3\", \"%5.1f\", pm3);\n    dumpMat<float>(\" m3\", \"%5.1f\", m3);\n  }\n  bool eq = pm3.compare(m3);\n#else // CUDA_PERF_TEST\n  cv::Mat cm3(m1.rows,m2.cols, CV_32F);\n  cuda_mm(m1, m2, cm3);\n  cv::Mat  m3 = m1 * m2;\n  bool eq = compare(m3, cm3, 0.01);\n#endif // CUDA_PERF_TEST\n  fprintf(stderr, \"XXXXXXXXXXXXXXXXXXXXXXXXXX eq=%d\\n\", eq);\n  return(!(eq&&sane));\n}\n\n"
  },
  {
    "path": "examples/maxsonar_simple/Makefile",
    "content": "CONNECTALDIR ?= ../..\nS2H_INTERFACES = MaxSonarCtrlRequest:MaxSonarController.req\nH2S_INTERFACES = MaxSonarController:MaxSonarCtrlIndication\n\nZBR = $(CONNECTALDIR)/lib/zedboard_robot\nBSVFILES = $(ZBR)/bsv/MaxSonarController.bsv\nCPPFILES= test_maxsonar.cpp $(ZBR)/cpp/read_buffer.cpp\nAUTOTOP = --interface pins:MaxSonarController.pins\n\nPIN_TYPE = MaxSonarSimplePins\nPIN_TYPE_INCLUDE = MaxSonarController\nPINOUT_FILE = pinout.json\nPIN_BINDINGS = pmod:pmodb\n\ninclude $(CONNECTALDIR)/Makefile.connectal\n"
  },
  {
    "path": "examples/maxsonar_simple/maxsonar_simple.h",
    "content": "\n// Copyright (c) 2014 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\n\n#include <stdio.h>\n#include <stdlib.h>\n#include <unistd.h>\n#include <assert.h>\n#include <string.h>\n\n\n\n#include \"MaxSonarCtrlIndication.h\"\n#include \"GeneratedTypes.h\"\n\nclass MaxSonarCtrlIndication : public MaxSonarCtrlIndicationWrapper\n{\n public:\n  sem_t status_sem;\n  sem_t pulse_width_sem;\n  uint32_t write_addr;\n  int write_wrap_cnt;\n  int verbose;\n  int useconds;\n\n  MaxSonarCtrlIndication(int id) : MaxSonarCtrlIndicationWrapper(id) {\n    sem_init(&status_sem,1,0);\n    sem_init(&pulse_width_sem,1,0);\n    write_addr = 0;\n    write_wrap_cnt = 0;\n    verbose = 0;\n  }\n  virtual void range_ctrl ( const uint8_t v){\n    if (verbose) fprintf(stderr, \"MaxSonarCtrlIndication::range_ctrl(v=%x)\\n\", v);\n  }\n  virtual void pulse_width ( const uint32_t v){\n    if (verbose) fprintf(stderr, \"MaxSonarCtrlIndication::pulse_width(v=%x)\\n\", v);\n    useconds = v/100;\n    sem_post(&pulse_width_sem);\n  }\n  virtual void memwrite_status(const uint32_t addr, const uint32_t wrap_cnt){\n    if (verbose) fprintf(stderr, \"MaxSonarCtrlIndication::memwrite_status(addr=%08x, wrap_cnt=%d)\\n\", addr, wrap_cnt);\n    write_addr = addr;\n    write_wrap_cnt = wrap_cnt;\n    sem_post(&status_sem);\n  }\n};\n\n\n\n"
  },
  {
    "path": "examples/maxsonar_simple/pinout.json",
    "content": "{\n    \"maxsonar_range_ctrl\" : {\n\t\"PIO_DIRECTION\": \"OUTPUT\",\n\t\"pmod\" : \"J2\"\n    },\n    \"maxsonar_pulse_v\" : {\n\t\"PIO_DIRECTION\": \"INPUT\",\n\t\"pmod\" : \"J4\"\n    },\n\n    \"leds_leds[0]\" : {\n\t\"PIO_DIRECTION\": \"OUTPUT\",\n\t\"leds\" : \"L0\"\n    },\n    \"leds_leds[1]\" : {\n\t\"PIO_DIRECTION\": \"OUTPUT\",\n\t\"leds\" : \"L1\"\n    },\n    \"leds_leds[2]\" : {\n\t\"PIO_DIRECTION\": \"OUTPUT\",\n\t\"leds\" : \"L2\"\n    },\n    \"leds_leds[3]\" : {\n\t\"PIO_DIRECTION\": \"OUTPUT\",\n\t\"leds\" : \"L3\"\n    },\n    \"leds_leds[4]\" : {\n\t\"PIO_DIRECTION\": \"OUTPUT\",\n\t\"leds\" : \"L4\"\n    },\n    \"leds_leds[5]\" : {\n\t\"PIO_DIRECTION\": \"OUTPUT\",\n\t\"leds\" : \"L5\"\n    },\n    \"leds_leds[6]\" : {\n\t\"PIO_DIRECTION\": \"OUTPUT\",\n\t\"leds\" : \"L6\"\n    },\n    \"leds_leds[7]\" : {\n\t\"PIO_DIRECTION\": \"OUTPUT\",\n\t\"leds\" : \"L7\"\n    }\n}\n\n\n"
  },
  {
    "path": "examples/maxsonar_simple/test_maxsonar.cpp",
    "content": "\n// Copyright (c) 2014 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n#include \"maxsonar_simple.h\"\n#include \"MaxSonarCtrlRequest.h\"\n#include \"read_buffer.h\"\n\nint main(int argc, const char **argv)\n{\n  MaxSonarCtrlIndication *ind = new MaxSonarCtrlIndication(IfcNames_MaxSonarCtrlIndicationH2S);\n  MaxSonarCtrlRequestProxy *device = new MaxSonarCtrlRequestProxy(IfcNames_MaxSonarCtrlRequestS2H);\n  long req_freq = 100000000; // 100 mHz\n  long freq = 0;\n  setClockFrequency(0, req_freq, &freq);\n  fprintf(stderr, \"Requested FCLK[0]=%ld actually %ld\\n\", req_freq, freq);\n  device->range_ctrl(1);\n\n  while(true){\n    usleep(50000);\n    device->pulse_width();\n    sem_wait(&(ind->pulse_width_sem));\n    float distance = ((float)ind->useconds)/147.0;\n    fprintf(stderr, \"(%8d microseconds == %8f inches)\\n\", ind->useconds, distance);\n  }\n}\n"
  },
  {
    "path": "examples/memcpy/Makefile",
    "content": "CONNECTALDIR?=../..\nS2H_INTERFACES = MemcpyRequest:Memcpy.request\nH2S_INTERFACES = Memcpy:MemcpyIndication\nMEM_READ_INTERFACES = lMemcpy.dmaReadClient\nMEM_WRITE_INTERFACES = lMemcpy.dmaWriteClient\n\nBSVFILES = ../memcpy/Memcpy.bsv\nCPPFILES=  ../memcpy/testmemcpy.cpp\n\ninclude $(CONNECTALDIR)/Makefile.connectal\n"
  },
  {
    "path": "examples/memcpy/Memcpy.bsv",
    "content": "// Copyright (c) 2013 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\nimport Vector::*;\nimport BuildVector::*;\nimport FIFOF::*;\nimport FIFO::*;\nimport BRAMFIFO::*;\nimport GetPut::*;\nimport ClientServer::*;\nimport ConnectalConfig::*;\nimport ConnectalMemory::*;\nimport ConnectalMemTypes::*;\nimport MemReadEngine::*;\nimport MemWriteEngine::*;\nimport Pipe::*;\n\ninterface MemcpyRequest;\n   method Action startCopy(Bit#(32) wrPointer, Bit#(32) rdPointer, Bit#(32) numWords, Bit#(32) burstLen, Bit#(32) iterCnt);\nendinterface\n\ninterface MemcpyIndication;\n   method Action started;\n   method Action done;\nendinterface\n\ninterface Memcpy;\n   interface MemcpyRequest request;\n   interface Vector#(1, MemReadClient#(DataBusWidth)) dmaReadClient;\n   interface Vector#(1, MemWriteClient#(DataBusWidth)) dmaWriteClient;\nendinterface\n\n\n// NOTE: this test doesn't rely on mkDma[Read|Write]Buffer to ensure that\n//       speculative read/write requests are not unsafely issued.  As a \n//       result this must be enforced manually (mdk)\n\ntypedef 8 CmdQDepth;\ntypedef TDiv#(DataBusWidth,32) WordsPerBeat;\n\nmodule mkMemcpy#(MemcpyIndication indication)(Memcpy);\n\n   MemReadEngine#(DataBusWidth,DataBusWidth,CmdQDepth,1)  re <- mkMemReadEngineBuff(valueOf(CmdQDepth)*512);\n   MemWriteEngine#(DataBusWidth,DataBusWidth,CmdQDepth,1) we <- mkMemWriteEngineBuff(valueOf(CmdQDepth)*512);\n\n   Integer wordsPerBeat = valueOf(WordsPerBeat);\n\n   Reg#(Bit#(32))        rdIterCnt <- mkReg(0);\n   Reg#(Bit#(32))        wrIterCnt <- mkReg(0);\n   Reg#(SGLId)           rdPointer <- mkReg(0);\n   Reg#(SGLId)           wrPointer <- mkReg(0);\n   Reg#(Bit#(32))         burstLen <- mkReg(0);\n   Reg#(Bit#(32))         numWords <- mkReg(0);\n   \n   FIFOF#(Bit#(DataBusWidth))    buffer <- mkSizedBRAMFIFOF(valueOf(CmdQDepth)*32);\n   \n   Bool verbose = False; //True;\n\n   rule start_read(rdIterCnt > 0);\n      if (verbose) $display(\"start_read obj %d numWords %d wordsPerBeat %d\", rdPointer, numWords, wordsPerBeat);\n      re.readServers[0].request.put(MemengineCmd{sglId:rdPointer, base:0, len:extend(numWords*4), burstLen:truncate(burstLen*4), tag:0});\n      rdIterCnt <= rdIterCnt-1;\n   endrule\n\n   rule start_write(wrIterCnt > 0);\n      if (verbose) $display(\"                    start_write obj %d numWords %d\", wrPointer, numWords);\n      we.writeServers[0].request.put(MemengineCmd{sglId:wrPointer, base:0, len:extend(numWords*4), burstLen:truncate(burstLen*4), tag:0});\n      wrIterCnt <= wrIterCnt-1;\n   endrule\n   \n   rule write_finish;\n      if (verbose) $display(\"                    write_finish %d\", wrIterCnt);\n      let rv1 <- we.writeServers[0].done.get;\n      if(wrIterCnt==0)\n\t indication.done;\n   endrule\n   \n   rule fill_buffer;\n      let v <- toGet(re.readServers[0].data).get;\n      buffer.enq(v.data);\n      if (verbose) $display(\"fill_buffer %h\", v.data);\n      if (v.last && verbose) $display(\"read_finish %d\", rdIterCnt);\n   endrule\n   \n   rule drain_buffer;\n      let v <- toGet(buffer).get();\n      we.writeServers[0].data.enq(v);\n      //$display(\"                    drain_buffer %h\", buffer.first);\n   endrule\n\n   interface MemcpyRequest request;\n   method Action startCopy(Bit#(32) wp, Bit#(32) rp, Bit#(32) nw, Bit#(32) bl, Bit#(32) ic);\n      $display(\"startCopy wrPointer=%d rdPointer=%d numWords=%h burstLen=%d iterCnt=%d\", wp, rp, nw, bl, ic);\n      indication.started;\n      // initialized\n      wrPointer <= wp;\n      rdPointer <= rp;\n      numWords  <= nw;\n      wrIterCnt <= ic;\n      rdIterCnt <= ic;\n      burstLen  <= bl;\n   endmethod\n   endinterface\n   interface MemReadClient dmaReadClient = vec(re.dmaClient);\n   interface MemWriteClient dmaWriteClient = vec(we.dmaClient);\nendmodule\n"
  },
  {
    "path": "examples/memcpy/testmemcpy.cpp",
    "content": "/* Copyright (c) 2013 Quanta Research Cambridge, Inc\n *\n * Permission is hereby granted, free of charge, to any person obtaining a\n * copy of this software and associated documentation files (the \"Software\"),\n * to deal in the Software without restriction, including without limitation\n * the rights to use, copy, modify, merge, publish, distribute, sublicense,\n * and/or sell copies of the Software, and to permit persons to whom the\n * Software is furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n * DEALINGS IN THE SOFTWARE.\n */\n#include <stdio.h>\n#include <sys/mman.h>\n#include <string.h>\n#include <stdlib.h>\n#include <unistd.h>\n#include <pthread.h>\n#include <monkit.h>\n#include <semaphore.h>\n\n#include \"dmaManager.h\"\n#include \"MemcpyIndication.h\"\n#include \"MemcpyRequest.h\"\n\nsem_t done_sem;\nsem_t memcmp_sem;\nint srcAlloc;\nint dstAlloc;\nunsigned int *srcBuffer = 0;\nunsigned int *dstBuffer = 0;\n#ifndef SIMULATION\nint numWords = 16 << 18;\n#else\nint numWords = 1 << 10;\n#endif\nsize_t alloc_sz = numWords*sizeof(unsigned int);\nbool finished = false;\nvolatile int memcmp_fail = 0;\nunsigned int memcmp_count = 0;\n\nvoid dump(const char *prefix, char *buf, size_t len)\n{\n    fprintf(stderr, \"%s \", prefix);\n    for (size_t i = 0; i < len ; i++) {\n\tfprintf(stderr, \"%02x\", (unsigned char)buf[i]);\n\tif (i % 32 == 31)\n\t  fprintf(stderr, \"\\n\");\n    }\n    fprintf(stderr, \"\\n\");\n}\n\nclass MemcpyIndication : public MemcpyIndicationWrapper\n{\n\npublic:\n  MemcpyIndication(unsigned int id) : MemcpyIndicationWrapper(id){}\n\n  virtual void started(){\n    fprintf(stderr, \"started\\n\");\n  }\n  virtual void done() {\n    sem_post(&done_sem);\n    fprintf(stderr, \"done\\n\");\n    finished = true;\n    memcmp_fail = memcmp(srcBuffer, dstBuffer, numWords*sizeof(unsigned int));\n    for (int i = 0; i < numWords; i++) {\n      int *s = (int *)srcBuffer;\n      int *d = (int *)dstBuffer;\n      if (s[i] != i)\n\tfprintf(stderr, \"bad data src[%x]=%x\\n\", i, s[i]);\n      if (d[i] != i)\n\tfprintf(stderr, \"bad data dst[%x]=%x\\n\", i, d[i]);\n    }\n    if (memcmp_fail) {\n      memcmp_fail=0;\n      for (int i = 0; i < numWords; i++) {\n\tint *s = (int *)srcBuffer;\n\tint *d = (int *)dstBuffer;\n\tif (s[i] != d[i]) {\n\t  fprintf(stderr, \"mismatch %d %08x %08x\\n\", i, s[i], d[i]);\n\t  memcmp_fail++;\n\t}\n      }\n    }\n    fprintf(stderr, \"memcmp=%x\\n\", memcmp_fail);\n    sem_post(&memcmp_sem);\n  }\n};\n\n\n// we can use the data synchronization barrier instead of flushing the \n// cache only because the ps7 is configured to run in buffered-write mode\n//\n// an opc2 of '4' and CRm of 'c10' encodes \"CP15DSB, Data Synchronization Barrier \n// operation\". this is a legal instruction to execute in non-privileged mode (mdk)\n//\n// #define DATA_SYNC_BARRIER   __asm __volatile( \"MCR p15, 0, %0, c7, c10, 4\" ::  \"r\" (0) );\n\nMemcpyIndication *deviceIndication = 0;\n\nint main(int argc, const char **argv)\n{\n  if(sem_init(&done_sem, 1, 0)){\n    fprintf(stderr, \"failed to init done_sem\\n\");\n    exit(1);\n  }\n  if(sem_init(&memcmp_sem, 1, 0)){\n    fprintf(stderr, \"failed to init memcmp_sem\\n\");\n    exit(1);\n  }\n\n  fprintf(stderr, \"%s %s\\n\", __DATE__, __TIME__);\n\n  MemcpyRequestProxy *device = new MemcpyRequestProxy(IfcNames_MemcpyRequestS2H);\n  deviceIndication = new MemcpyIndication(IfcNames_MemcpyIndicationH2S);\n  DmaManager *dma = platformInit();\n\n  fprintf(stderr, \"Main::allocating memory...\\n\");\n\n  srcAlloc = portalAlloc(alloc_sz, 0);\n  dstAlloc = portalAlloc(alloc_sz, 0);\n\n  // for(int i = 0; i < srcAlloc->header.numEntries; i++)\n  //   fprintf(stderr, \"%lx %lx\\n\", srcAlloc->entries[i].dma_address, srcAlloc->entries[i].length);\n  // for(int i = 0; i < dstAlloc->header.numEntries; i++)\n  //   fprintf(stderr, \"%lx %lx\\n\", dstAlloc->entries[i].dma_address, dstAlloc->entries[i].length);\n\n  srcBuffer = (unsigned int *)portalMmap(srcAlloc, alloc_sz);\n  dstBuffer = (unsigned int *)portalMmap(dstAlloc, alloc_sz);\n\n  for (int i = 0; i < numWords; i++){\n    srcBuffer[i] = i;\n    dstBuffer[i] = 0x5a5abeef;\n  }\n\n  portalCacheFlush(srcAlloc, srcBuffer, alloc_sz, 1);\n  portalCacheFlush(dstAlloc, dstBuffer, alloc_sz, 1);\n  fprintf(stderr, \"Main::flush and invalidate complete\\n\");\n\n  unsigned int ref_srcAlloc = dma->reference(srcAlloc);\n  unsigned int ref_dstAlloc = dma->reference(dstAlloc);\n  \n  fprintf(stderr, \"ref_srcAlloc=%d\\n\", ref_srcAlloc);\n  fprintf(stderr, \"ref_dstAlloc=%d\\n\", ref_dstAlloc);\n\n\n  // unsigned int refs[2] = {ref_srcAlloc, ref_dstAlloc};\n  // for(int j = 0; j < 2; j++){\n  //   unsigned int ref = refs[j];\n  //   for(int i = 0; i < numWords; i = i+(numWords/4)){\n  //     dmap->addrRequest(ref, i*sizeof(unsigned int));\n  //     sleep(1);\n  //   }\n  //   dmap->addrRequest(ref, (1<<16)*sizeof(unsigned int));\n  //   sleep(1);\n  // }\n\n  fprintf(stderr, \"Main::starting memcpy numWords:%d\\n\", numWords);\n  int burstLen = 32;\n#ifndef SIMULATION\n  int iterCnt = 128;\n#else\n  int iterCnt = 2;\n#endif\n  portalTimerStart(0);\n  device->startCopy(ref_dstAlloc, ref_srcAlloc, numWords, burstLen, iterCnt);\n  sem_wait(&done_sem);\n  platformStatistics();\n  //float read_util = (float)read_beats/(float)cycles;\n  //float write_util = (float)write_beats/(float)cycles;\n  //fprintf(stderr, \"   iters: %d\\n\", iterCnt);\n  //fprintf(stderr, \"wr_beats: %\"PRIx64\" %08lx\\n\", write_beats, (long)write_beats);\n  //fprintf(stderr, \"rd_beats: %\"PRIx64\" %08lx\\n\", read_beats, (long)read_beats);\n  //fprintf(stderr, \"numWords: %x\\n\", numWords);\n  //fprintf(stderr, \"  wr_est: %\"PRIx64\"\\n\", (write_beats*2)/iterCnt);\n  //fprintf(stderr, \"  rd_est: %\"PRIx64\"\\n\", (read_beats*2)/iterCnt);\n  //fprintf(stderr, \"memory read utilization (beats/cycle): %f\\n\", read_util);\n  //fprintf(stderr, \"memory write utilization (beats/cycle): %f\\n\", write_util);\n  \n#if 0\n  MonkitFile pmf(\"perf.monkit\");\n  pmf.setHwCycles(cycles)\n    .setReadBwUtil(read_util)\n    .setWriteBwUtil(write_util)\n    .writeFile();\n  fprintf(stderr, \"After updating perf.monkit\\n\");\n#endif\n  sem_wait(&memcmp_sem);\n  fprintf(stderr, \"after memcmp_sem memcmp_fail=%d\\n\", memcmp_fail);\n  return memcmp_fail;\n}\n"
  },
  {
    "path": "examples/memcpyslow/Makefile",
    "content": "include ../memcpy/Makefile\n\nCONNECTALFLAGS += --mainclockperiod=30\n\n"
  },
  {
    "path": "examples/memlatency/Makefile",
    "content": "CONNECTALDIR?=../..\nS2H_INTERFACES = MemlatencyRequest:Memlatency.request\nH2S_INTERFACES = Memlatency:MemlatencyIndication\nMEM_READ_INTERFACES = lMemlatency.dmaReadClient\nMEM_WRITE_INTERFACES = lMemlatency.dmaWriteClient\n\nBSVFILES = Memlatency.bsv\nCPPFILES = testmemlatency.cpp\n\ninclude $(CONNECTALDIR)/Makefile.connectal\n"
  },
  {
    "path": "examples/memlatency/Memlatency.bsv",
    "content": "// Copyright (c) 2013 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\nimport FIFOF::*;\nimport FIFO::*;\nimport ClientServer::*;\nimport GetPut::*;\nimport BRAMFIFO::*;\nimport Vector::*;\nimport Pipe::*;\nimport ConnectalMemory::*;\nimport ConnectalMemTypes::*;\nimport MemReadEngine::*;\nimport MemWriteEngine::*;\n\ninterface MemlatencyRequest;\n   method Action start(Bit#(32) wrPointer, Bit#(32) rdPointer, Bit#(32) burstLen);\nendinterface\n\ninterface MemlatencyIndication;\n   method Action started;\n   method Action readDone;\n   method Action writeDone;\n   method Action readLatency(Bit#(32) l);\n   method Action writeLatency(Bit#(32) l);\nendinterface\n\ninterface Memlatency;\n   interface MemlatencyRequest request;\n   interface Vector#(1, MemReadClient#(64)) dmaReadClient;\n   interface Vector#(1, MemWriteClient#(64)) dmaWriteClient;\nendinterface\n\nmodule mkMemlatency#(MemlatencyIndication indication)(Memlatency);\n\n\n   MemReadEngine#(64,64,1,1)  re <- mkMemReadEngine;\n   MemWriteEngine#(64,64,2,1) we <- mkMemWriteEngine;\n   \n   Reg#(Bit#(32))        rdIterCnt <- mkReg(0);\n   Reg#(Bit#(32))        wrIterCnt <- mkReg(0);\n   Reg#(SGLId)   rdPointer <- mkReg(0);\n   Reg#(SGLId)   wrPointer <- mkReg(0);\n   Reg#(Bit#(32))         burstLen <- mkReg(0);\n   \n   Reg#(Bit#(32))           cycles <- mkReg(0);\n   FIFO#(Bit#(32))     rdStartFifo <- mkSizedBRAMFIFO(16);\n   FIFO#(Bit#(32))     wrStartFifo <- mkSizedBRAMFIFO(16);\n   FIFO#(Bit#(32))       rdLatFifo <- mkSizedBRAMFIFO(16);\n   FIFO#(Bit#(32))       wrLatFifo <- mkSizedBRAMFIFO(16);\n   \n   rule cycle;\n      cycles <= cycles+1;\n   endrule\n   \n   rule startRead(rdIterCnt > 0);\n      re.readServers[0].request.put(MemengineCmd{sglId:rdPointer, base:0, len:burstLen*4, burstLen:truncate(burstLen*4), tag:0});\n      rdIterCnt <= rdIterCnt-1;\n      rdStartFifo.enq(cycles);\n   endrule\n\n   rule readConsume;\n      let v <- toGet(re.readServers[0].data).get;\n      if (v.last) begin\n         let rdStart <- toGet(rdStartFifo).get();\n         rdLatFifo.enq(cycles-rdStart);\n      end\n   endrule\n   \n   rule startWrite(wrIterCnt > 0);\n      we.writeServers[0].request.put(MemengineCmd{sglId:wrPointer, base:0, len:burstLen*4, burstLen:truncate(burstLen*4), tag:0});\n      wrIterCnt <= wrIterCnt-1;\n      wrStartFifo.enq(cycles);\n   endrule\n\n   rule finishWrite;\n      let rv0 <- we.writeServers[0].done.get;\n      let wrStart <- toGet(wrStartFifo).get();\n      wrLatFifo.enq(cycles-wrStart);\n   endrule\n   \n   rule writeProduce;\n      we.writeServers[0].data.enq(1);\n   endrule\n   \n   rule report;\n      let wl <- toGet(wrLatFifo).get;\n      let rl <- toGet(rdLatFifo).get;\n      indication.readLatency(rl);\n      indication.writeLatency(wl);\n      if(wrIterCnt==0)\n\t indication.writeDone;\n      if(rdIterCnt==0)\n\t indication.readDone;\n   endrule\n\n   interface MemlatencyRequest request;\n   method Action start(Bit#(32) wp, Bit#(32) rp, Bit#(32) bl) if (rdIterCnt == 0 && wrIterCnt == 0);\n      $display(\"start wrPointer=%d rdPointer=%d burstLen=%d\", wp, rp, bl);\n      indication.started;\n      // initialized\n      wrPointer <= wp;\n      rdPointer <= rp;\n      rdIterCnt <= 16;\n      wrIterCnt <= 16;\n      burstLen  <= bl;\n   endmethod\n   endinterface\n   interface MemReadClient dmaReadClient = cons(re.dmaClient, nil);\n   interface MemWriteClient dmaWriteClient = cons(we.dmaClient, nil);\nendmodule\n"
  },
  {
    "path": "examples/memlatency/testmemlatency.cpp",
    "content": "/* Copyright (c) 2013 Quanta Research Cambridge, Inc\n *\n * Permission is hereby granted, free of charge, to any person obtaining a\n * copy of this software and associated documentation files (the \"Software\"),\n * to deal in the Software without restriction, including without limitation\n * the rights to use, copy, modify, merge, publish, distribute, sublicense,\n * and/or sell copies of the Software, and to permit persons to whom the\n * Software is furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n * DEALINGS IN THE SOFTWARE.\n */\n#include <monkit.h>\n#include \"dmaManager.h\"\n#include \"MemlatencyIndication.h\"\n#include \"MemlatencyRequest.h\"\n\nsem_t read_done_sem;\nsem_t write_done_sem;\nint srcAlloc;\nint dstAlloc;\nunsigned int *srcBuffer = 0;\nunsigned int *dstBuffer = 0;\nint numWords = 16 << 10;\nsize_t alloc_sz = numWords*sizeof(unsigned int);\n\nunsigned int rd_latency = 0;\nunsigned int num_reads = 0;\n\nunsigned int wr_latency = 0;\nunsigned int num_writes = 0;\n\n\nclass MemlatencyIndication : public MemlatencyIndicationWrapper\n{\n\npublic:\n  MemlatencyIndication(unsigned int id) : MemlatencyIndicationWrapper(id){}\n\n  virtual void started(){\n    fprintf(stderr, \"started\\n\");\n  }\n  virtual void readLatency(uint32_t l) {\n    fprintf(stderr, \"readLatency %d\\n\", l);\n    rd_latency += l;\n    num_reads++;\n  }\n  virtual void writeLatency(uint32_t l){\n    fprintf(stderr, \"writeLatency %d\\n\", l);\n    wr_latency += l;\n    num_writes++;\n  }\n  virtual void readDone() {\n    sem_post(&read_done_sem);\n    fprintf(stderr, \"readDone\\n\");\n  }\n  virtual void writeDone() {\n    sem_post(&write_done_sem);\n    fprintf(stderr, \"writeDone\\n\");\n  }\n};\n\n\nMemlatencyIndication *deviceIndication = 0;\n\nint main(int argc, const char **argv)\n{\n  if(sem_init(&read_done_sem, 1, 0)){\n    fprintf(stderr, \"failed to init read_done_sem\\n\");\n    exit(1);\n  }\n  if(sem_init(&write_done_sem, 1, 0)){\n    fprintf(stderr, \"failed to init write_done_sem\\n\");\n    exit(1);\n  }\n\n  fprintf(stderr, \"%s %s\\n\", __DATE__, __TIME__);\n\n  MemlatencyRequestProxy device(IfcNames_MemlatencyRequestS2H);\n  DmaManager *dma = platformInit();\n  deviceIndication = new MemlatencyIndication(IfcNames_MemlatencyIndicationH2S);\n\n  fprintf(stderr, \"Main::allocating memory...\\n\");\n\n  srcAlloc = portalAlloc(alloc_sz, 0);\n  dstAlloc = portalAlloc(alloc_sz, 0);\n\n  srcBuffer = (unsigned int *)portalMmap(srcAlloc, alloc_sz);\n  dstBuffer = (unsigned int *)portalMmap(dstAlloc, alloc_sz);\n\n  for (int i = 0; i < numWords; i++){\n    srcBuffer[i] = i;\n    dstBuffer[i] = 0x5a5abeef;\n  }\n\n  portalCacheFlush(srcAlloc, srcBuffer, alloc_sz, 1);\n  portalCacheFlush(dstAlloc, dstBuffer, alloc_sz, 1);\n  fprintf(stderr, \"Main::flush and invalidate complete\\n\");\n\n  unsigned int ref_srcAlloc = dma->reference(srcAlloc);\n  unsigned int ref_dstAlloc = dma->reference(dstAlloc);\n    \n  fprintf(stderr, \"Main::starting mempcy numWords:%d\\n\", numWords);\n  int burstLen = 16;\n  device.start(ref_dstAlloc, ref_srcAlloc, burstLen);\n  sem_wait(&read_done_sem);\n  sem_wait(&write_done_sem);\n\n  fprintf(stderr, \"average read latency:  %d\\n\", (unsigned int)(((float)rd_latency)/((float)num_reads)));\n  fprintf(stderr, \"average write latency: %d\\n\", (unsigned int)(((float)wr_latency)/((float)num_writes)));\n\n  return 0;\n}\n"
  },
  {
    "path": "examples/memread/Makefile",
    "content": "\nCONNECTALDIR?=../..\nS2H_INTERFACES = ReadTestRequest:ReadTest.request\nH2S_INTERFACES = ReadTest:ReadTestIndication\nMEM_READ_INTERFACES = lReadTest.dmaClient\nBSVFILES = ReadTest.bsv\nCPPFILES=testmemread.cpp\n\nifeq ($(BOARD),zedboard)\nCONNECTALFLAGS += -DBSV_POSITIVE_RESET\nendif\nifeq ($(BOARD),xsim)\nCONNECTALFLAGS += -DBSV_POSITIVE_RESET\nendif\n\n#CONNECTALFLAGS += -DTLP32\nCONNECTALFLAGS += -DMEMENGINE_REQUEST_CYCLES\n\ninclude $(CONNECTALDIR)/Makefile.connectal\n"
  },
  {
    "path": "examples/memread/ReadTest.bsv",
    "content": "// Copyright (c) 2013 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n`include \"ConnectalProjectConfig.bsv\"\nimport FIFO::*;\nimport FIFOF::*;\nimport Vector::*;\nimport BuildVector::*;\nimport GetPut::*;\nimport ClientServer::*;\nimport Pipe::*;\nimport ConnectalMemTypes::*;\nimport MemReadEngine::*;\nimport ConnectalConfig::*;\n\ninterface ReadTestRequest;\n   method Action startRead(Bit#(32) pointer, Bit#(32) numBytes, Bit#(32) burstLen, Bit#(32) iterCnt);\nendinterface\n\ninterface ReadTest;\n   interface ReadTestRequest request;\n   interface Vector#(1,MemReadClient#(DataBusWidth)) dmaClient;\nendinterface\n\ninterface ReadTestIndication;\n   method Action readDone(Bit#(32) mismatchCount);\nendinterface\n\ntypedef 14 NumOutstandingRequests;\ntypedef TMul#(NumOutstandingRequests,TMul#(32,4)) BufferSizeBytes;\nmodule mkReadTest#(ReadTestIndication indication) (ReadTest);\n\n   Reg#(SGLId)   pointer <- mkReg(0);\n   Reg#(Bit#(32))       numBytes <- mkReg(0);\n   Reg#(Bit#(BurstLenSize)) burstLenBytes <- mkReg(0);\n   Reg#(Bit#(32))  itersToFinish <- mkReg(0);\n   Reg#(Bit#(32))   itersToStart <- mkReg(0);\n   Reg#(Bit#(32))        bytesRead <- mkReg(0);\n   Reg#(Bit#(32)) mismatchCounts <- mkReg(0);\n   MemReadEngine#(DataBusWidth,DataBusWidth,NumOutstandingRequests,1)        re <- mkMemReadEngineBuff(valueOf(BufferSizeBytes));\n   FIFO#(Bit#(32)) checkDoneFifo <- mkFIFO();\n   \n   rule start (itersToStart > 0);\n      $display(\"Test: request.put\");\n      re.readServers[0].request.put(MemengineCmd{sglId:pointer, base:0, len:numBytes, tag:0, burstLen:burstLenBytes});\n      itersToStart <= itersToStart-1;\n   endrule\n\n   Reg#(Bit#(DataBusWidth)) vReg <- mkReg(0);\n   Reg#(Bit#(DataBusWidth)) vExpectedReg <- mkReg(0);\n   Reg#(Bool)               validReg <- mkReg(False);\n   Reg#(Bit#(32))           bytesToRead <- mkReg(0);\n   Reg#(Bool)               lastReg <- mkReg(False);\n   FIFO#(void)              doneFifo <- mkFIFO;\n   rule check;\n      // first pipeline stage\n      if (re.readServers[0].data.notEmpty()) begin\n\t let md <- toGet(re.readServers[0].data).get;\n\t //$display(\"md v=%h tag=%d first=%d last=%d\", md.data, md.tag, md.first, md.last);\n\t let v = md.data;\n\t let rval = bytesRead/4;\n\t function Bit#(32) expectedVal(Integer i); return rval+fromInteger(i); endfunction\n\t let expectedV = pack(genWith(expectedVal));\n\t vReg <= v;\n\t vExpectedReg <= expectedV;\n\t validReg <= True;\n\t let next_bytesRead = bytesRead + fromInteger(valueOf(DataBusWidth))/8;\n\t let next_bytesToRead = bytesToRead - fromInteger(valueOf(DataBusWidth))/8;\n\t //$display(\"check next_bytesRead=%d next_bytesToRead=%d last=%d\", next_bytesRead, next_bytesToRead, last);\n\t if (md.last) begin\n\t    next_bytesRead = 0;\n\t    next_bytesToRead = numBytes;\n\t end\n\t lastReg <= md.last;\n\t bytesRead <= next_bytesRead;\n\t bytesToRead <= next_bytesToRead;\n         if (md.last)\n             doneFifo.enq(?);\n      end\n      else begin\n\t validReg <= False;\n      end\n\n      // second pipeline stage\n      if (validReg) begin\n\t let v = vReg;\n\t let expectedV = vExpectedReg;\n\t let misMatch = v != expectedV;\n\t mismatchCounts <= mismatchCounts + (misMatch ? 1 : 0);\n\t //$display(\"Test: check new=%x numBytes=%x bytesRead=%x misMatch=%x read=%x expect=%x\", new_bytesRead, numBytes, bytesRead, misMatch, v, expectedV);\n\t if (lastReg) begin\n\t    checkDoneFifo.enq(mismatchCounts);\n\t end\n      end\n   endrule\n   \n`ifdef MEMENGINE_REQUEST_CYCLES\n   rule request_cycles;\n      let reqcycles <- toGet(re.readServers[0].requestCycles).get();\n      $display(\"request %d took %d cycles\", reqcycles.tag, reqcycles.cycles);\n   endrule\n`endif\n   rule finish if (itersToFinish > 0);\n      $display(\"Test: response.get itersToFinish %x\", itersToFinish);\n      let mc <- toGet(checkDoneFifo).get();\n      doneFifo.deq;\n      if (itersToFinish == 1) begin\n\t indication.readDone(mismatchCounts);\n      end\n      itersToFinish <= itersToFinish - 1;\n   endrule\n   \n   interface dmaClient = vec(re.dmaClient);\n   interface ReadTestRequest request;\n      method Action startRead(Bit#(32) rp, Bit#(32) nb, Bit#(32) bl, Bit#(32) ic) if (itersToStart == 0 && itersToFinish == 0);\n         $display(\"startRead pointer=%x numBytes %x burstLen %x iteration %x\", rp, nb, bl, ic);\n\t pointer <= rp;\n\t numBytes  <= nb;\n\t bytesToRead <= nb;\n\t burstLenBytes  <= truncate(bl);\n\t itersToFinish <= ic;\n\t itersToStart <= ic;\n\t mismatchCounts <= 0;\n\t bytesRead <= 0;\n      endmethod\n   endinterface\nendmodule\n"
  },
  {
    "path": "examples/memread/design_vc707.tcl",
    "content": "###############################################################\n###   Tcl Variables\n###############################################################\n#set tclParams [list <param1> <value> <param2> <value> ... <paramN> <value>]\nset tclParams [list place.closeImportedSites  1 \\\n                    hd.StrictContainRouting   1 \\\n              ]\n\n#Define location for \"Tcl\" directory. Defaults to \"../Tcl\"\nset tclHome \"../../scripts/xilinx/tcl\"\nif {[file exists $tclHome]} {\n   set tclDir $tclHome\n} elseif {[file exists \"./Tcl\"]} {\n   set tclDir  \"./Tcl\"\n} else {\n   error \"ERROR: No valid location found for required Tcl scripts. Set \\$tclDir in design.tcl to a valid location.\"\n}\n\n###############################################################\n### Part Variables - Define Device, Package, Speedgrade \n###############################################################\nset device       \"xc7vx485t\"\nset package      \"ffg1761\"\nset speed        \"-2\"\nset part         $device$package$speed\n\n###############################################################\n###  Setup Variables\n###############################################################\n####flow control\nset run.topSynth   0\nset run.oocSynth   1\nset run.tdImpl     1\nset run.oocImpl    1\nset run.topImpl    1\nset run.flatImpl   0\n\n####Report and DCP controls - values: 0-required min; 1-few extra; 2-all\nset verbose      1\nset dcpLevel     1\n\n####Output Directories\nset synthDir  \"./Synth\"\nset implDir   \"./Implement\"\nset dcpDir    \"./Checkpoint\"\n\n####Input Directories\nset srcDir     \"./vc707\"\nset rtlDir     \"$srcDir/verilog\"\nset prjDir     \"$srcDir/prj\"\nset xdcDir     \"$srcDir/constraints\"\nset coreDir    \"$srcDir/cores\"\nset netlistDir \"$srcDir/netlist\"\n\n####Source required Tcl Procs\nsource $tclDir/design_utils.tcl\nsource $tclDir/synth_utils.tcl\nsource $tclDir/impl_utils.tcl\nsource $tclDir/hd_floorplan_utils.tcl\n\n###############################################################\n### Top Definition\n###############################################################\nset top \"mkPcieTop\"\nadd_module $top\nset_attribute module $top    top_level     1\nset_attribute module $top    vlog          [concat [glob $rtlDir/top/*.v] [glob $rtlDir/lib/*.v] ]\nset_attribute module $top    ip            []\n#set_attribute module $top    vlog_headers  [glob $rtlDir/top/*Stub.v]\nset_attribute module $top    synth         ${run.topSynth}\n\nadd_implementation $top\nset_attribute impl $top      top           $top\nset_attribute impl $top      implXDC       [glob $xdcDir/vc707.xdc]\nset_attribute impl $top      impl          ${run.topImpl}\nset_attribute impl $top      hd.impl       1\n\n####################################################################\n### OOC Module Definition and OOC Implementation for each instance\n####################################################################\nset module1 \"mkPcieHost\"\nadd_module $module1\nset_attribute module $module1 vlog          [concat [glob $rtlDir/lib/*.v] [glob $rtlDir/pciehost/*.v]]\nset_attribute module $module1 ip            []\nset_attribute module $module1 synth        ${run.oocSynth}\n\nset instance \"pciehost\"\nadd_ooc_implementation $instance\nset_attribute ooc $instance   module       $module1\nset_attribute ooc $instance   inst         $instance\nset_attribute ooc $instance   hierInst     $instance\nset_attribute ooc $instance   implXDC      [list $xdcDir/${instance}_phys.xdc \\\n\t\t\t\t\t\t $xdcDir/${instance}_ooc_timing.xdc \\\n\t\t\t\t\t\t $xdcDir/${instance}_ooc_budget.xdc \\\n\t\t\t\t\t\t $xdcDir/${instance}_ooc_optimize.xdc \\\n\t\t\t\t\t\t]\nset_attribute ooc $instance   impl         ${run.oocImpl}\nset_attribute ooc $instance   preservation routing\n\nset module2 \"mkPCIExpressEndpointX7\"\nadd_module $module2\nset_attribute module $module2 vlog          [concat [glob $rtlDir/lib/*.v] [list $rtlDir/ep7/mkPCIExpressEndpointX7.v]]\nset_attribute module $module2 ip            [glob /scratch/jamey/connectal/generated/xilinx/vc707/*/*.xci]\nset_attribute module $module2 synth        ${run.oocSynth}\n\nset instance \"ep7\"\nadd_ooc_implementation $instance\nset_attribute ooc $instance   module       $module2\nset_attribute ooc $instance   inst         $instance\nset_attribute ooc $instance   hierInst     $instance\nset_attribute ooc $instance   implXDC      [list $xdcDir/${instance}_phys.xdc \\\n\t\t\t\t\t\t $xdcDir/${instance}_ooc_timing.xdc \\\n\t\t\t\t\t\t $xdcDir/${instance}_ooc_budget.xdc \\\n\t\t\t\t\t\t $xdcDir/${instance}_ooc_optimize.xdc \\\n\t\t\t\t\t\t]\nset_attribute ooc $instance   impl         ${run.oocImpl}\nset_attribute ooc $instance   preservation routing\n\n# set module3 \"mkSynthesizeableConnectalTop\"\n# add_module $module3\n# set_attribute module $module3 vlog          [concat [glob $rtlDir/lib/*.v] [list $rtlDir/portal/mkSynthesizeableConnectalTop.v]]\n# set_attribute module $module3 ip            []\n# set_attribute module $module3 synth        ${run.oocSynth}\n\n# set instance \"portalTop\"\n# add_ooc_implementation $instance\n# set_attribute ooc $instance   module       $module3\n# set_attribute ooc $instance   inst         $instance\n# set_attribute ooc $instance   hierInst     $instance\n# set_attribute ooc $instance   implXDC      [list $xdcDir/${instance}_phys.xdc \\\n# \t\t\t\t\t\t $xdcDir/${instance}_ooc_timing.xdc \\\n# \t\t\t\t\t\t $xdcDir/${instance}_ooc_budget.xdc \\\n# \t\t\t\t\t\t $xdcDir/${instance}_ooc_optimize.xdc \\\n# \t\t\t\t\t\t]\n# set_attribute ooc $instance   impl         ${run.oocImpl}\n# set_attribute ooc $instance   preservation routing\n\n####################################################################\n### Create TopDown implementation run \n####################################################################\nset module1File \"$synthDir/$module1/${module1}_synth.dcp\"\nset module2File \"$synthDir/$module2/${module2}_synth.dcp\"\n#set module3File \"$synthDir/$module3/${module3}_synth.dcp\"\nadd_implementation TopDown\nset_attribute impl TopDown      top          $top\nset_attribute impl TopDown      implXDC      [list $xdcDir/floorplan_vc707.xdc $xdcDir/vc707.xdc]\nset_attribute impl TopDown      td.impl      1\nset_attribute impl TopDown      cores        [list $module1File                          \\\n                                                   $module2File                          \\\n                                                   [get_attribute module $top cores]     \\\n                                                   [get_attribute module $module1 cores] \\\n                                                   [get_attribute module $module2 cores] \\\n                                             ] \nset_attribute impl TopDown      impl         ${run.tdImpl}\nset_attribute impl TopDown      route        0\n\n####################################################################\n### Create Flat implementation run \n####################################################################\nadd_implementation Flat\nset_attribute impl Flat         top          $top\nset_attribute impl Flat         implXDC      [list $xdcDir/${top}_flpn.xdc $xdcDir/vc707.xdc]\nset_attribute impl Flat         cores        [list $module1File                          \\\n                                                   $module2File                          \\\n                                                   [get_attribute module $top cores]     \\\n                                                   [get_attribute module $module1 cores] \\\n                                                   [get_attribute module $module2 cores] \\\n                                             ] \nset_attribute impl Flat         impl         ${run.flatImpl}\n\n########################################################################\n### Task / flow portion\n########################################################################\n\nset_property SEVERITY {Warning} [get_drc_checks HDOOC-4]\n\n# Build the designs\nsource $tclDir/run.tcl\n\nexit\n"
  },
  {
    "path": "examples/memread/testmemread.cpp",
    "content": "/* Copyright (c) 2014 Quanta Research Cambridge, Inc\n *\n * Permission is hereby granted, free of charge, to any person obtaining a\n * copy of this software and associated documentation files (the \"Software\"),\n * to deal in the Software without restriction, including without limitation\n * the rights to use, copy, modify, merge, publish, distribute, sublicense,\n * and/or sell copies of the Software, and to permit persons to whom the\n * Software is furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n * DEALINGS IN THE SOFTWARE.\n */\n#include <monkit.h>\n#include \"dmaManager.h\"\n#include \"ReadTestRequest.h\"\n#include \"ReadTestIndication.h\"\n\n#if defined(PCIE)\nint burstLen = 32;\n#elif defined(ZynqUltrascale)\nint burstLen = 64; // ZynqUltrascale supports upto burstLenByte=4*64=256 (16 beats of 128bit transfer)\n#else\nint burstLen = 16;\n#endif\n\n#if defined(BOARD_xsim)\nint numWords = 0x40/4;\nint iterCnt = 1;\n#elif defined(SIMULATION)\nint numWords = 0x124000/4;\nint iterCnt = 3;\n#else\nint numWords = 0x1240000/4; // make sure to allocate at least one entry of each size\nint iterCnt = 64;\n#endif\n\nstatic sem_t test_sem;\nstatic size_t test_sz  = numWords*sizeof(unsigned int);\nstatic size_t alloc_sz = test_sz;\nstatic int mismatchCount = 0;\n\nclass ReadTestIndication : public ReadTestIndicationWrapper\n{\npublic:\n    void readDone(uint32_t v) {\n        fprintf(stderr, \"ReadTest::readDone(%x)\\n\", v);\n        mismatchCount += v;\n        sem_post(&test_sem);\n    }\n    // memread_4m\n    void started ( const uint32_t numWords ) {\n    }\n    void reportStateDbg ( const uint32_t streamRdCnt, const uint32_t mismatchCount )  {\n    }\n    ReadTestIndication(int id, int tile=DEFAULT_TILE) : ReadTestIndicationWrapper(id,tile){}\n};\n\nint main(int argc, const char **argv)\n{\n    int test_result = 0;\n    int srcAlloc;\n    unsigned int *srcBuffer = 0;\n\n    fprintf(stderr, \"Main::%s %s\\n\", __DATE__, __TIME__);\n    DmaManager *dma = platformInit();\n    ReadTestRequestProxy *device = new ReadTestRequestProxy(IfcNames_ReadTestRequestS2H);\n    ReadTestIndication memReadIndication(IfcNames_ReadTestIndicationH2S);\n\n    fprintf(stderr, \"Main::allocating memory...\\n\");\n    srcAlloc = portalAlloc(alloc_sz, 0);\n    srcBuffer = (unsigned int *)portalMmap(srcAlloc, alloc_sz);\n    for (int i = 0; i < numWords; i++)\n        srcBuffer[i] = i;\n    portalCacheFlush(srcAlloc, srcBuffer, alloc_sz, 1);\n    fprintf(stderr, \"Main::flush and invalidate complete\\n\");\n\n    /* Test 1: check that match is ok */\n    unsigned int ref_srcAlloc = dma->reference(srcAlloc);\n    fprintf(stderr, \"ref_srcAlloc=%d\\n\", ref_srcAlloc);\n    fprintf(stderr, \"Main::orig_test read numWords=%d burstLen=%d iterCnt=%d\\n\", numWords, burstLen, iterCnt);\n    portalTimerStart(0);\n    device->startRead(ref_srcAlloc, numWords * 4, burstLen * 4, iterCnt);\n    sem_wait(&test_sem);\n    platformStatistics();\n    if (mismatchCount) {\n        fprintf(stderr, \"Main::first test failed to match %d.\\n\", mismatchCount);\n        test_result++;     // failed\n    }\n\n    /* Test 2: check that mismatch is detected */\n    srcBuffer[0] = -1;\n    srcBuffer[numWords/2] = -1;\n    srcBuffer[numWords-1] = -1;\n    portalCacheFlush(srcAlloc, srcBuffer, alloc_sz, 1);\n\n    fprintf(stderr, \"Starting second read, mismatches expected\\n\");\n    mismatchCount = 0;\n    device->startRead(ref_srcAlloc, numWords * 4 / NumberOfMasters, burstLen * 4, iterCnt);\n    sem_wait(&test_sem);\n    if (mismatchCount != 3/*number of errors introduced above*/ * iterCnt) {\n        fprintf(stderr, \"Main::second test failed to match mismatchCount=%d (expected %d) iterCnt=%d numWords=%d.\\n\",\n            mismatchCount, 3*iterCnt,\n            iterCnt, numWords);\n        test_result++;     // failed\n    }\n#if 0\n    MonkitFile pmf(\"perf.monkit\");\n    pmf.setHwCycles(cycles)\n        .setReadBwUtil(read_util)\n        .writeFile();\n#endif\n    return test_result;\n}\n"
  },
  {
    "path": "examples/memread/vc707_floorplan.xdc",
    "content": "startgroup\ncreate_pblock pblock_ep7\nresize_pblock pblock_ep7 -add {SLICE_X184Y54:SLICE_X221Y166 DSP48_X18Y22:DSP48_X19Y65 RAMB18_X12Y22:RAMB18_X14Y65 RAMB36_X12Y11:RAMB36_X14Y32}\nadd_cells_to_pblock pblock_ep7 [get_cells [list ep7]] -clear_locs\nendgroup\n\nstartgroup\ncreate_pblock pblock_pciehost\nresize_pblock pblock_pciehost -add {SLICE_X112Y55:SLICE_X171Y197 DSP48_X9Y22:DSP48_X16Y77 RAMB18_X7Y22:RAMB18_X10Y77 RAMB36_X7Y11:RAMB36_X10Y38 BUFGCTRL_X0Y16}\nadd_cells_to_pblock pblock_pciehost [get_cells [list pciehost]] -clear_locs\nendgroup\n\nstartgroup\ncreate_pblock pblock_portalTop\nresize_pblock pblock_portalTop -add {SLICE_X0Y25:SLICE_X101Y247 DSP48_X0Y10:DSP48_X7Y97 RAMB18_X0Y10:RAMB18_X6Y97 RAMB36_X0Y5:RAMB36_X6Y48}\nadd_cells_to_pblock pblock_portalTop [get_cells [list portalTop]] -clear_locs\nendgroup\n"
  },
  {
    "path": "examples/memread128/Makefile",
    "content": "CONNECTALDIR?=../..\nS2H_INTERFACES = ReadTestRequest:ReadTest.request\nH2S_INTERFACES = ReadTest:ReadTestIndication\nMEM_READ_INTERFACES = lReadTest.dmaClient\n\nBSVFILES = ../memread/ReadTest.bsv\nCPPFILES= ../memread/testmemread.cpp\nCONNECTALFLAGS += -D DataBusWidth=128\n\ninclude $(CONNECTALDIR)/Makefile.connectal\n"
  },
  {
    "path": "examples/memread2/Makefile",
    "content": "CONNECTALDIR?=../..\nS2H_INTERFACES = Memread2Request:Memread2.request\nH2S_INTERFACES = Memread2:Memread2Indication\nMEM_READ_INTERFACES = lMemread2.dmaClients\n\nBSVFILES = Memread2.bsv\nCPPFILES=testmemread2.cpp\n\ninclude $(CONNECTALDIR)/Makefile.connectal\n"
  },
  {
    "path": "examples/memread2/Memread2.bsv",
    "content": "// Copyright (c) 2013 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\nimport FIFOF::*;\nimport Vector::*;\nimport GetPut::*;\nimport ClientServer::*;\nimport Connectable::*;\nimport ConnectalMemTypes::*;\nimport MemReadEngine::*;\nimport Pipe::*;\n\ninterface Memread2Request;\n   method Action startRead(Bit#(32) pointer, Bit#(32) pointer2, Bit#(32) numWords, Bit#(32) burstLen);\n   method Action getStateDbg();   \nendinterface\n\ninterface Memread2;\n   interface Memread2Request request;\n   interface Vector#(2, MemReadClient#(64)) dmaClients;\nendinterface\n\ninterface Memread2Indication;\n   method Action started(Bit#(32) numWords);\n   method Action rData(Bit#(64) v);\n   method Action reportStateDbg(Bit#(32) x, Bit#(32) y);\n   method Action readReq(Bit#(32) v);\n   method Action readDone(Bit#(32) mismatchCount);\n   method Action mismatch(Bit#(32) offset, Bit#(64) expectedValue, Bit#(64) value);\nendinterface\n\nmodule mkMemread2#(Memread2Indication indication) (Memread2);\n\n   Reg#(Bit#(32))     srcGen0 <- mkReg(0);\n   Reg#(Bit#(32))     srcGen1 <- mkReg(0);\n   Reg#(Bit#(32)) mismatchCount0 <- mkReg(0);\n   Reg#(Bit#(32)) mismatchCount1 <- mkReg(0);\n   MemReadEngine#(64,64,1,1) re0 <- mkMemReadEngine;\n   MemReadEngine#(64,64,1,1) re1 <- mkMemReadEngine;\n\n   FIFOF#(Bit#(64)) outReg0 <- mkFIFOF;\n   FIFOF#(Bit#(64)) outReg1 <- mkFIFOF;\n   PipeIn#(Bit#(64)) pi0 = toPipeIn(outReg0);\n   PipeIn#(Bit#(64)) pi1 = toPipeIn(outReg1);\n   FIFOF#(Bit#(1)) doneReg0 <- mkFIFOF;\n   FIFOF#(Bit#(1)) doneReg1 <- mkFIFOF;\n   rule re0_read;\n      let v <- toGet(re0.readServers[0].data).get;\n      toPut(pi0).put(v.data);\n      if (v.last)\n         doneReg0.enq(0);\n   endrule\n   rule re1_read;\n      let v <- toGet(re1.readServers[0].data).get;\n      toPut(pi1).put(v.data);\n      if (v.last)\n         doneReg1.enq(0);\n   endrule\n\n   Reg#(Bool)         valid0Reg <- mkReg(False);\n   Reg#(Bit#(64)) v0Reg <- mkReg(0);\n   Reg#(Bit#(64)) v0ExpectedReg <- mkReg(0);\n   rule read0;\n      // first stage of pipeline\n      if (outReg0.notEmpty) begin\n\t srcGen0 <= srcGen0+2;\n\t v0ExpectedReg  <= {srcGen0+1,srcGen0};\n\t let v0 <- toGet(outReg0).get;\n\t v0Reg <= v0;\n\t valid0Reg <= True;\n      end\n      else begin\n\t valid0Reg <= False;\n      end\n      \n      // second stage of pipeline\n      if (valid0Reg) begin\n\t let mm = v0Reg != v0ExpectedReg;\n\t mismatchCount0 <= mismatchCount0 + (mm ? 1 : 0);\n\t if (mm) indication.mismatch(0, v0ExpectedReg, v0Reg);\n      end\n   endrule\n\n   Reg#(Bool)         valid1Reg <- mkReg(False);\n   Reg#(Bit#(64)) v1Reg <- mkReg(0);\n   Reg#(Bit#(64)) v1ExpectedReg <- mkReg(0);\n   rule read1;\n      // first stage of pipeline\n      if (outReg1.notEmpty) begin\n\t srcGen1 <= srcGen1+2;\n\t v1ExpectedReg <= {(srcGen1+1)*3,srcGen1*3};\n\t let v1 <- toGet(outReg1).get;\n\t v1Reg <= v1;\n\t valid1Reg <= True;\n      end\n      else begin\n\t valid1Reg <= False;\n      end\n\n      // second stage of pipeline\n      if (valid1Reg) begin\n\t let mm = v1Reg != v1ExpectedReg;\n\t mismatchCount1 <= mismatchCount1 + (mm ? 1 : 0);\n\t if (mm) indication.mismatch(1, v1ExpectedReg, v1Reg); \n      end\n   endrule\n   \n   rule done;\n      doneReg0.deq;\n      doneReg1.deq;\n      indication.readDone(mismatchCount1+mismatchCount0);\n   endrule\n   \n   interface Memread2Request request;\n       method Action startRead(Bit#(32) pointer, Bit#(32) pointer2, Bit#(32) numWords, Bit#(32) bl);\n\t  $display(\"startRead(%d %d %d %d)\", pointer, pointer2, numWords, bl);\n\t  re0.readServers[0].request.put(MemengineCmd{sglId:pointer,  base:0, len:numWords*4, burstLen:truncate(bl*4), tag:0});\n\t  re1.readServers[0].request.put(MemengineCmd{sglId:pointer2, base:0, len:numWords*4, burstLen:truncate(bl*4), tag:0});\n\t  indication.started(numWords);\n       endmethod\n\n       method Action getStateDbg();\n\t  Bit#(16) sg0 = truncate(srcGen0);\n\t  Bit#(16) sg1 = truncate(srcGen1);\n\t  Bit#(16) mm0 = truncate(mismatchCount0);\n\t  Bit#(16) mm1 = truncate(mismatchCount1);\n\t  indication.reportStateDbg({sg0,sg1}, {mm0,mm1});\n       endmethod\n   endinterface\n   interface MemReadClient dmaClients = cons(re0.dmaClient, cons(re1.dmaClient, nil));\nendmodule\n"
  },
  {
    "path": "examples/memread2/testmemread2.cpp",
    "content": "/* Copyright (c) 2014 Quanta Research Cambridge, Inc\n *\n * Permission is hereby granted, free of charge, to any person obtaining a\n * copy of this software and associated documentation files (the \"Software\"),\n * to deal in the Software without restriction, including without limitation\n * the rights to use, copy, modify, merge, publish, distribute, sublicense,\n * and/or sell copies of the Software, and to permit persons to whom the\n * Software is furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n * DEALINGS IN THE SOFTWARE.\n */\n#include \"dmaManager.h\"\n#include \"Memread2Indication.h\"\n#include \"Memread2Request.h\"\n\nint srcAlloc, srcAlloc2;\nunsigned int *srcBuffer = 0;\nunsigned int *srcBuffer2 = 0;\nint numWords = 16 << 8;\nsize_t test_sz  = numWords*sizeof(unsigned int);\nsize_t alloc_sz = test_sz;\n\nvoid dump(const char *prefix, char *buf, size_t len)\n{\n    fprintf(stderr, \"%s \", prefix);\n    for (size_t i = 0; i < (len > 16 ? 16 : len) ; i++)\n\tfprintf(stderr, \"%02x\", (unsigned char)buf[i]);\n    fprintf(stderr, \"\\n\");\n}\n\nclass Memread2Indication : public Memread2IndicationWrapper\n{\npublic:\n  unsigned int rDataCnt;\n  virtual void readReq(uint32_t v){\n    //fprintf(stderr, \"Memread2::readReq %lx\\n\", v);\n  }\n  virtual void readDone(uint32_t v){\n    fprintf(stderr, \"Memread2::readDone mismatch=%x\\n\", v);\n    mismatchCount = v;\n    //    if (mismatchesReceived == mismatchCount)\n    // exit(v ? 1 : 0);\n  }\n  virtual void started(uint32_t words){\n    fprintf(stderr, \"Memread2::started: words=%x\\n\", words);\n  }\n  virtual void rData ( uint64_t v ){\n    fprintf(stderr, \"rData (%08x): \", rDataCnt++);\n    dump(\"\", (char*)&v, sizeof(v));\n  }\n  virtual void reportStateDbg(uint32_t x, uint32_t y){\n    fprintf(stderr, \"Memread2::reportStateDbg: x=%08x y=%08x\\n\", x, y);\n  }  \n  virtual void mismatch(uint32_t offset, uint64_t ev, uint64_t v) {\n    fprintf(stderr, \"Mismatch at %x %llx != %llx\\n\", offset, (long long)ev, (long long)v);\n\n    mismatchesReceived++;\n    if (mismatchesReceived == mismatchCount)\n      exit(1);\n  }\n  Memread2Indication(int id) : Memread2IndicationWrapper(id), mismatchCount(0), mismatchesReceived(0){}\nprivate:\n  int mismatchCount;\n  int mismatchesReceived;\n};\n\nint main(int argc, const char **argv)\n{\n  unsigned int srcGen = 0;\n  int limit = 20;\n\n  Memread2RequestProxy *device = 0;\n\n  fprintf(stderr, \"Main::%s %s\\n\", __DATE__, __TIME__);\n\n  device = new Memread2RequestProxy(IfcNames_Memread2RequestS2H);\n  DmaManager *dma = platformInit();\n  Memread2Indication deviceIndication(IfcNames_Memread2IndicationH2S);\n\n  fprintf(stderr, \"Main::allocating memory...\\n\");\n  srcAlloc = portalAlloc(alloc_sz, 0);\n  srcBuffer = (unsigned int *)portalMmap(srcAlloc, alloc_sz);\n  srcAlloc2 = portalAlloc(alloc_sz, 0);\n  srcBuffer2 = (unsigned int *)portalMmap(srcAlloc2, alloc_sz);\n\n  for (int i = 0; i < numWords; i++){\n    int v = srcGen++;\n    srcBuffer[i] = v;\n    srcBuffer2[i] = v*3;\n  }\n    \n  portalCacheFlush(srcAlloc, srcBuffer, alloc_sz, 1);\n  fprintf(stderr, \"Main::flush and invalidate complete\\n\");\n\n  unsigned int ref_srcAlloc = dma->reference(srcAlloc);\n  fprintf(stderr, \"ref_srcAlloc=%d\\n\", ref_srcAlloc);\n  unsigned int ref_srcAlloc2 = dma->reference(srcAlloc2);\n  fprintf(stderr, \"ref_srcAlloc2=%d\\n\", ref_srcAlloc2);\n\n  fprintf(stderr, \"Main::starting read %08x\\n\", numWords);\n  device->startRead(ref_srcAlloc, ref_srcAlloc2, 32, 16);\n  fprintf(stderr, \"Main::sleeping\\n\");\n  while(limit-- > 0){\n    sleep(3);\n    device->getStateDbg();\n    //uint64_t beats = hostMemServerIndication->getMemoryTraffic(ChannelType_Read);\n    uint64_t beats = 0;\n    fprintf(stderr, \"   beats: %\"PRIx64\"\\n\", beats);\n    //hostMemServerRequest->stateDbg(ChannelType_Read);\n    platformStatistics();\n  }\n  return 0;\n}\n"
  },
  {
    "path": "examples/memread256/Makefile",
    "content": "CONNECTALDIR?=../..\nS2H_INTERFACES = ReadTestRequest:ReadTest.request\nH2S_INTERFACES = ReadTest:ReadTestIndication\nMEM_READ_INTERFACES = lReadTest.dmaClient\n\nBSVFILES = ../memread/ReadTest.bsv\nCPPFILES= ../memread/testmemread.cpp\nCONNECTALFLAGS += -D DataBusWidth=256\nCONNECTALFLAGS += --mainclockperiod=8 -D USE_WIDE_WIDTH\n\ninclude $(CONNECTALDIR)/Makefile.connectal\n"
  },
  {
    "path": "examples/memread_4m/Makefile",
    "content": "CONNECTALDIR?=../..\nS2H_INTERFACES = ReadTestRequest:ReadTest.request\nH2S_INTERFACES = ReadTest\\#\\(\\`NumberOfMasters\\):ReadTestIndication\nMEM_READ_INTERFACES = lReadTest.dmaClients\n\nBSVFILES = ReadTest.bsv\nCPPFILES=../memread/testmemread.cpp\nPLATFORM_NUMBER_OF_MASTERS =4\n#CONNECTALFLAGS += -I$(CONNECTALDIR)/examples/memread\n\ninclude $(CONNECTALDIR)/Makefile.connectal\n"
  },
  {
    "path": "examples/memread_4m/ReadTest.bsv",
    "content": "// Copyright (c) 2013 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\nimport FIFO::*;\nimport FIFOF::*;\nimport Vector::*;\nimport StmtFSM::*;\nimport GetPut::*;\nimport ClientServer::*;\nimport Pipe::*;\nimport ConnectalMemTypes::*;\nimport MemReadEngine::*;\nimport ConnectalConfig::*;\n\ninterface ReadTestRequest;\n   method Action startRead(Bit#(32) pointer, Bit#(32) numBytes, Bit#(32) burstLen, Bit#(32) iterCnt);\n   method Action getStateDbg();   \nendinterface\n\ninterface ReadTest#(numeric type nClients);\n   interface ReadTestRequest request;\n   interface Vector#(nClients,MemReadClient#(DataBusWidth)) dmaClients;\nendinterface\n\ninterface ReadTestIndication;\n   method Action started(Bit#(32) numBytes);\n   method Action reportStateDbg(Bit#(32) streamRdCnt, Bit#(32) mismatchCount);\n   method Action readDone(Bit#(32) mismatchCount);\nendinterface\n\nmodule mkReadTest#(ReadTestIndication indication) (ReadTest#(4));\n   Reg#(SGLId)     pointer <- mkReg(0);\n   Reg#(Bit#(32)) numBytes <- mkReg(0);\n   Reg#(Bit#(BurstLenSize)) burstLenBytes <- mkReg(0);\n   Reg#(Bit#(32))          itersToStart <- mkReg(0);\n   Reg#(Bit#(32))        startBase <- mkReg(0);\n   Reg#(Bit#(3))          startPtr <- mkReg(0);\n   Reg#(Bit#(3))         finishPtr <- mkReg(0);\n   Reg#(Bit#(32))    mismatchAccum <- mkReg(0);\n   Vector#(4,MemReadEngine#(DataBusWidth,DataBusWidth,1,1))      res <- replicateM(mkMemReadEngine);\n   FIFO#(void)           startFifo <- mkFIFO;\n   \n   Vector#(4,Reg#(Bit#(32)))        srcGens <- replicateM(mkReg(0));\n   Vector#(4,Reg#(Bit#(32))) mismatchCounts <- replicateM(mkReg(0));\n   Vector#(4,FIFO#(void))          doneFifo <- replicateM(mkFIFO);\n   \n   Stmt startStmt = seq\n\t\t       startBase <= 0;\n\t\t       for(startPtr <= 0; startPtr < 4; startPtr <= startPtr+1)\n\t\t\t  (action\n\t\t\t      let cmd = MemengineCmd{sglId:pointer, base:extend(startBase), len:numBytes, burstLen:burstLenBytes, tag:0};\n\t\t\t      res[startPtr].readServers[0].request.put(cmd);\n\t\t\t      startBase <= startBase+numBytes;\n\t\t\t      //$display(\"start:%d %h %d %h (%d)\", startPtr, startBase, numBytes, burstLenBytes, itersToStart);\n\t\t\t   endaction);\n\t\t    endseq;\n   FSM startFSM <- mkFSM(startStmt);\n\n   Stmt finishStmt = seq\n\t\t\tmismatchAccum <= 0;\n\t\t\tfor(finishPtr <= 0; finishPtr < 4; finishPtr <= finishPtr+1)\n\t\t\t   mismatchAccum <= mismatchAccum + mismatchCounts[finishPtr];\n\t\t\tindication.readDone(mismatchAccum);\n\t\t\t//$display(\"finishStmt: %h\", mismatchAccum);\n\t\t    endseq;\n   FSM finishFSM <- mkFSM(finishStmt);\n   \n   rule start (itersToStart > 0);\n      startFifo.deq;\n      startFSM.start;\n      itersToStart <= itersToStart-1;\n   endrule\n   \n   rule finish;\n      for(Integer i = 0; i < 4; i=i+1)\n\t doneFifo[i].deq;\n      if (itersToStart == 0)\n\t finishFSM.start;\n      else\n\t startFifo.enq(?);\n   endrule\n   \n   for(Integer i = 0; i < 4; i=i+1)\n      rule check;\n\t let v <- toGet(res[i].readServers[0].data).get;\n\t let expectedV = {srcGens[i]+1,srcGens[i]};\n\t let misMatch = v.data != expectedV;\n\t mismatchCounts[i] <= mismatchCounts[i] + (misMatch ? 1 : 0);\n\t if (srcGens[i]+2 == fromInteger(i+1)*(numBytes>>2)) begin\n\t    //$display(\"check %d %d\", i, srcGens[i]+1);\n\t    srcGens[i] <= fromInteger(i)*(numBytes>>2);\n\t end\n\t else\n\t    srcGens[i] <= srcGens[i]+2;\n         if (v.last) begin\n\t    //$display(\"finish: %d (%d)\", i, itersToStart);\n            doneFifo[i].enq(?);\n         end\n      endrule\n   \n   function MemReadClient#(DataBusWidth) dc(MemReadEngine#(DataBusWidth,DataBusWidth,1,1) re) = re.dmaClient;\n   interface dmaClients = map(dc,res);\n   interface ReadTestRequest request;\n      method Action startRead(Bit#(32) rp, Bit#(32) nb, Bit#(32) bl, Bit#(32) ic);\n\t //$display(\"startRead rdPointer=%d numBytes=%h burstLenBytes=%d itersToStart=%d\", rp, nb, bl, ic);\n\t indication.started(nb);\n\t pointer <= rp;\n\t numBytes  <= nb;\n\t burstLenBytes  <= truncate(bl);\n\t itersToStart <= ic;\n\t for(Integer i = 0; i < 4; i=i+1) begin\n\t    mismatchCounts[i] <= 0;\n\t    srcGens[i] <= fromInteger(i)*(nb>>2);\n\t end\n\t startFifo.enq(?);\n      endmethod\n      method Action getStateDbg();\n\t indication.reportStateDbg(itersToStart, mismatchCounts[0]);\n      endmethod\n   endinterface\nendmodule\n"
  },
  {
    "path": "examples/memread_simple/Makefile",
    "content": "CONNECTALDIR?=../..\nS2H_INTERFACES = ReadTestRequest:ReadTest.request\nH2S_INTERFACES = ReadTest:ReadTestIndication\nMEM_READ_INTERFACES = lReadTest.dmaClient\n\nBSVFILES = ReadTest.bsv\nCPPFILES=testmemread.cpp\n\ninclude $(CONNECTALDIR)/Makefile.connectal\n"
  },
  {
    "path": "examples/memread_simple/ReadTest.bsv",
    "content": "// Copyright (c) 2013 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\nimport FIFO::*;\nimport FIFOF::*;\nimport Vector::*;\nimport GetPut::*;\nimport ClientServer::*;\nimport Pipe::*;\nimport ConnectalMemTypes::*;\nimport MemReadEngine::*;\nimport Pipe::*;\nimport ConnectalConfig::*; // for DataBusWidth\n\ninterface ReadTestRequest;\n   method Action startRead(Bit#(32) pointer, Bit#(32) numBytes, Bit#(32) burstLenInBytes, Bit#(32) iterCnt);\nendinterface\n\ninterface ReadTest;\n   interface ReadTestRequest request;\n   interface Vector#(1,MemReadClient#(DataBusWidth)) dmaClient;\nendinterface\n\ninterface ReadTestIndication;\n   method Action readDone(Bit#(32) mismatchCount);\nendinterface\n\nmodule mkReadTest#(ReadTestIndication indication) (ReadTest);\n   Reg#(SGLId)   pointer <- mkReg(0);\n   Reg#(Bit#(32))       numBytes <- mkReg(0);\n   Reg#(Bit#(BurstLenSize)) burstLenInBytes <- mkReg(0);\n   Reg#(Bit#(32))  itersToFinish <- mkReg(0);\n   Reg#(Bit#(32))   itersToStart <- mkReg(0);\n   Reg#(Bit#(32))      bytesRead <- mkReg(0);\n   Reg#(Bit#(32)) mismatchCounts <- mkReg(0);\n   MemReadEngine#(DataBusWidth,DataBusWidth,2,1) re <- mkMemReadEngine;\n\n   rule start (itersToStart > 0);\n      re.readServers[0].request.put(MemengineCmd{sglId:pointer, base:0, len:numBytes, burstLen:burstLenInBytes, tag: 0});\n      itersToStart <= itersToStart-1;\n   endrule\n\n   function Bit#(32) expectedVal(Integer i); return (bytesRead/4)+fromInteger(i); endfunction\n   rule check;\n      let v <- toGet(re.readServers[0].data).get;\n      if (v.data != pack(genWith(expectedVal)))\n         mismatchCounts <= mismatchCounts + 1;\n      let new_bytesRead = bytesRead + fromInteger(valueOf(DataBusWidth))/8;\n      if (v.last) begin\n\t new_bytesRead = 0;\n         if (itersToFinish == 1)\n\t    indication.readDone(mismatchCounts);\n         itersToFinish <= itersToFinish - 1;\n      end\n      bytesRead <= new_bytesRead;\n   endrule\n\n   interface dmaClient = cons(re.dmaClient, nil);\n   interface ReadTestRequest request;\n      method Action startRead(Bit#(32) rp, Bit#(32) nb, Bit#(32) bl, Bit#(32) ic) if (itersToFinish == 0);\n\t pointer <= rp;\n\t numBytes <= nb;\n\t burstLenInBytes  <= truncate(bl);\n\t itersToFinish <= ic;\n\t itersToStart <= ic;\n\t mismatchCounts <= 0;\n\t bytesRead <= 0;\n      endmethod\n   endinterface\nendmodule\n"
  },
  {
    "path": "examples/memread_simple/design_vc707.tcl",
    "content": "###############################################################\n###   Tcl Variables\n###############################################################\n#set tclParams [list <param1> <value> <param2> <value> ... <paramN> <value>]\nset tclParams [list place.closeImportedSites  1 \\\n                    hd.StrictContainRouting   1 \\\n              ]\n\n#Define location for \"Tcl\" directory. Defaults to \"../Tcl\"\nset tclHome \"../../scripts/xilinx/tcl\"\nif {[file exists $tclHome]} {\n   set tclDir $tclHome\n} elseif {[file exists \"./Tcl\"]} {\n   set tclDir  \"./Tcl\"\n} else {\n   error \"ERROR: No valid location found for required Tcl scripts. Set \\$tclDir in design.tcl to a valid location.\"\n}\n\n###############################################################\n### Part Variables - Define Device, Package, Speedgrade \n###############################################################\nset device       \"xc7vx485t\"\nset package      \"ffg1761\"\nset speed        \"-2\"\nset part         $device$package$speed\n\n###############################################################\n###  Setup Variables\n###############################################################\n####flow control\nset run.topSynth   0\nset run.oocSynth   1\nset run.tdImpl     1\nset run.oocImpl    1\nset run.topImpl    1\nset run.flatImpl   0\n\n####Report and DCP controls - values: 0-required min; 1-few extra; 2-all\nset verbose      1\nset dcpLevel     1\n\n####Output Directories\nset synthDir  \"./Synth\"\nset implDir   \"./Implement\"\nset dcpDir    \"./Checkpoint\"\n\n####Input Directories\nset srcDir     \"./vc707\"\nset rtlDir     \"$srcDir/verilog\"\nset prjDir     \"$srcDir/prj\"\nset xdcDir     \"$srcDir/constraints\"\nset coreDir    \"$srcDir/cores\"\nset netlistDir \"$srcDir/netlist\"\n\n####Source required Tcl Procs\nsource $tclDir/design_utils.tcl\nsource $tclDir/synth_utils.tcl\nsource $tclDir/impl_utils.tcl\nsource $tclDir/hd_floorplan_utils.tcl\n\n###############################################################\n### Top Definition\n###############################################################\nset top \"mkPcieTop\"\nadd_module $top\nset_attribute module $top    top_level     1\nset_attribute module $top    vlog          [concat [glob $rtlDir/top/*.v] [glob $rtlDir/lib/*.v] ]\nset_attribute module $top    ip            []\n#set_attribute module $top    vlog_headers  [glob $rtlDir/top/*Stub.v]\nset_attribute module $top    synth         ${run.topSynth}\n\nadd_implementation $top\nset_attribute impl $top      top           $top\nset_attribute impl $top      implXDC       [glob $xdcDir/vc707.xdc]\nset_attribute impl $top      impl          ${run.topImpl}\nset_attribute impl $top      hd.impl       1\n\n####################################################################\n### OOC Module Definition and OOC Implementation for each instance\n####################################################################\nset module1 \"mkPcieHost\"\nadd_module $module1\nset_attribute module $module1 vlog          [concat [glob $rtlDir/lib/*.v] [glob $rtlDir/pciehost/*.v]]\nset_attribute module $module1 ip            []\nset_attribute module $module1 synth        ${run.oocSynth}\n\nset instance \"pciehost\"\nadd_ooc_implementation $instance\nset_attribute ooc $instance   module       $module1\nset_attribute ooc $instance   inst         $instance\nset_attribute ooc $instance   hierInst     $instance\nset_attribute ooc $instance   implXDC      [list $xdcDir/${instance}_phys.xdc \\\n\t\t\t\t\t\t $xdcDir/${instance}_ooc_timing.xdc \\\n\t\t\t\t\t\t $xdcDir/${instance}_ooc_budget.xdc \\\n\t\t\t\t\t\t $xdcDir/${instance}_ooc_optimize.xdc \\\n\t\t\t\t\t\t]\nset_attribute ooc $instance   impl         ${run.oocImpl}\nset_attribute ooc $instance   preservation routing\n\nset module2 \"mkPCIExpressEndpointX7\"\nadd_module $module2\nset_attribute module $module2 vlog          [concat [glob $rtlDir/lib/*.v] [list $rtlDir/ep7/mkPCIExpressEndpointX7.v]]\nset_attribute module $module2 ip            [glob /scratch/jamey/connectal/generated/xilinx/vc707/*/*.xci]\nset_attribute module $module2 synth        ${run.oocSynth}\n\nset instance \"ep7\"\nadd_ooc_implementation $instance\nset_attribute ooc $instance   module       $module2\nset_attribute ooc $instance   inst         $instance\nset_attribute ooc $instance   hierInst     $instance\nset_attribute ooc $instance   implXDC      [list $xdcDir/${instance}_phys.xdc \\\n\t\t\t\t\t\t $xdcDir/${instance}_ooc_timing.xdc \\\n\t\t\t\t\t\t $xdcDir/${instance}_ooc_budget.xdc \\\n\t\t\t\t\t\t $xdcDir/${instance}_ooc_optimize.xdc \\\n\t\t\t\t\t\t]\nset_attribute ooc $instance   impl         ${run.oocImpl}\nset_attribute ooc $instance   preservation routing\n\n# set module3 \"mkSynthesizeableConnectalTop\"\n# add_module $module3\n# set_attribute module $module3 vlog          [concat [glob $rtlDir/lib/*.v] [list $rtlDir/portal/mkSynthesizeableConnectalTop.v]]\n# set_attribute module $module3 ip            []\n# set_attribute module $module3 synth        ${run.oocSynth}\n\n# set instance \"portalTop\"\n# add_ooc_implementation $instance\n# set_attribute ooc $instance   module       $module3\n# set_attribute ooc $instance   inst         $instance\n# set_attribute ooc $instance   hierInst     $instance\n# set_attribute ooc $instance   implXDC      [list $xdcDir/${instance}_phys.xdc \\\n# \t\t\t\t\t\t $xdcDir/${instance}_ooc_timing.xdc \\\n# \t\t\t\t\t\t $xdcDir/${instance}_ooc_budget.xdc \\\n# \t\t\t\t\t\t $xdcDir/${instance}_ooc_optimize.xdc \\\n# \t\t\t\t\t\t]\n# set_attribute ooc $instance   impl         ${run.oocImpl}\n# set_attribute ooc $instance   preservation routing\n\n####################################################################\n### Create TopDown implementation run \n####################################################################\nset module1File \"$synthDir/$module1/${module1}_synth.dcp\"\nset module2File \"$synthDir/$module2/${module2}_synth.dcp\"\n#set module3File \"$synthDir/$module3/${module3}_synth.dcp\"\nadd_implementation TopDown\nset_attribute impl TopDown      top          $top\nset_attribute impl TopDown      implXDC      [list $xdcDir/floorplan_vc707.xdc $xdcDir/vc707.xdc]\nset_attribute impl TopDown      td.impl      1\nset_attribute impl TopDown      cores        [list $module1File                          \\\n                                                   $module2File                          \\\n                                                   [get_attribute module $top cores]     \\\n                                                   [get_attribute module $module1 cores] \\\n                                                   [get_attribute module $module2 cores] \\\n                                             ] \nset_attribute impl TopDown      impl         ${run.tdImpl}\nset_attribute impl TopDown      route        0\n\n####################################################################\n### Create Flat implementation run \n####################################################################\nadd_implementation Flat\nset_attribute impl Flat         top          $top\nset_attribute impl Flat         implXDC      [list $xdcDir/${top}_flpn.xdc $xdcDir/vc707.xdc]\nset_attribute impl Flat         cores        [list $module1File                          \\\n                                                   $module2File                          \\\n                                                   [get_attribute module $top cores]     \\\n                                                   [get_attribute module $module1 cores] \\\n                                                   [get_attribute module $module2 cores] \\\n                                             ] \nset_attribute impl Flat         impl         ${run.flatImpl}\n\n########################################################################\n### Task / flow portion\n########################################################################\n\nset_property SEVERITY {Warning} [get_drc_checks HDOOC-4]\n\n# Build the designs\nsource $tclDir/run.tcl\n\nexit\n"
  },
  {
    "path": "examples/memread_simple/testmemread.cpp",
    "content": "/* Copyright (c) 2014 Quanta Research Cambridge, Inc\n *\n * Permission is hereby granted, free of charge, to any person obtaining a\n * copy of this software and associated documentation files (the \"Software\"),\n * to deal in the Software without restriction, including without limitation\n * the rights to use, copy, modify, merge, publish, distribute, sublicense,\n * and/or sell copies of the Software, and to permit persons to whom the\n * Software is furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n * DEALINGS IN THE SOFTWARE.\n */\n#include \"dmaManager.h\"\n#include \"ReadTestRequest.h\"\n#include \"ReadTestIndication.h\"\n\n#ifdef SIMULATION\nstatic size_t test_sz = 0x124000; // make sure to allocate at least one entry of each size\n#else\nstatic size_t test_sz = 0x1240000; // make sure to allocate at least one entry of each size\n#endif\nsem_t test_sem;\nstatic int burstLen = 16 * 4;\n\nclass ReadTestIndication : public ReadTestIndicationWrapper\n{\npublic:\n  void readDone(uint32_t v){\n    printf( \"ReadTest::readDone(mismatch = %x)\\n\", v);\n    sem_post(&test_sem);\n  }\n  ReadTestIndication(int id) : ReadTestIndicationWrapper(id){}\n};\n\nint main(int argc, const char **argv)\n{\n  ReadTestRequestProxy *device = new ReadTestRequestProxy(IfcNames_ReadTestRequestS2H);\n  ReadTestIndication deviceIndication(IfcNames_ReadTestIndicationH2S);\n  DmaManager *dma = platformInit();\n\n  int srcAlloc;\n  srcAlloc = portalAlloc(test_sz, 0);\n  unsigned int *srcBuffer = (unsigned int *)portalMmap(srcAlloc, test_sz);\n\n  for (unsigned int i = 0; i < test_sz/sizeof(unsigned int); i++)\n    srcBuffer[i] = i;\n  portalCacheFlush(srcAlloc, srcBuffer, test_sz, 1);\n  unsigned int ref_srcAlloc = dma->reference(srcAlloc);\n  printf( \"Main::starting read %lx\\n\", test_sz);\n  device->startRead(ref_srcAlloc, test_sz, burstLen, 1);\n  sem_wait(&test_sem);\n  return 0;\n}\n"
  },
  {
    "path": "examples/memread_simple/vc707_floorplan.xdc",
    "content": "startgroup\ncreate_pblock pblock_ep7\nresize_pblock pblock_ep7 -add {SLICE_X184Y54:SLICE_X221Y166 DSP48_X18Y22:DSP48_X19Y65 RAMB18_X12Y22:RAMB18_X14Y65 RAMB36_X12Y11:RAMB36_X14Y32}\nadd_cells_to_pblock pblock_ep7 [get_cells [list ep7]] -clear_locs\nendgroup\n\nstartgroup\ncreate_pblock pblock_pciehost\nresize_pblock pblock_pciehost -add {SLICE_X112Y55:SLICE_X171Y197 DSP48_X9Y22:DSP48_X16Y77 RAMB18_X7Y22:RAMB18_X10Y77 RAMB36_X7Y11:RAMB36_X10Y38 BUFGCTRL_X0Y16}\nadd_cells_to_pblock pblock_pciehost [get_cells [list pciehost]] -clear_locs\nendgroup\n\nstartgroup\ncreate_pblock pblock_portalTop\nresize_pblock pblock_portalTop -add {SLICE_X0Y25:SLICE_X101Y247 DSP48_X0Y10:DSP48_X7Y97 RAMB18_X0Y10:RAMB18_X6Y97 RAMB36_X0Y5:RAMB36_X6Y48}\nadd_cells_to_pblock pblock_portalTop [get_cells [list portalTop]] -clear_locs\nendgroup\n"
  },
  {
    "path": "examples/memwrite/Makefile",
    "content": "CONNECTALDIR?=../..\nS2H_INTERFACES = MemwriteRequest:Memwrite.request\nH2S_INTERFACES = Memwrite:MemwriteIndication\nMEM_WRITE_INTERFACES = lMemwrite.dmaClient\n\nBSVFILES = Memwrite.bsv\nCPPFILES=testmemwrite.cpp\nCONNECTALFLAGS += --bscflags \" -show-schedule\"\nCONNECTALFLAGS += -DMEMENGINE_REQUEST_CYCLES\n\ninclude $(CONNECTALDIR)/Makefile.connectal\n"
  },
  {
    "path": "examples/memwrite/Memwrite.bsv",
    "content": "// Copyright (c) 2013 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n`include \"ConnectalProjectConfig.bsv\"\nimport FIFO::*;\nimport FIFOF::*;\nimport Vector::*;\nimport ClientServer::*;\nimport GetPut::*;\nimport ConnectalMemTypes::*;\nimport MemWriteEngine::*;\nimport Pipe::*;\nimport Arith::*;\nimport ConnectalConfig::*;\n\n`ifdef NumEngineServers\ntypedef `NumEngineServers NumEngineServers;\n`else\ntypedef 1 NumEngineServers;\n`endif\n\ntypedef TDiv#(DataBusWidth,32) DataBusWords;\n\ninterface MemwriteRequest;\n   method Action startWrite(Bit#(32) pointer, Bit#(32) offset, Bit#(32) numWords, Bit#(32) burstLen, Bit#(32) iterCnt);\n   method Action getStateDbg();   \nendinterface\n\ninterface Memwrite;\n   interface MemwriteRequest request;\n   interface Vector#(1,MemWriteClient#(DataBusWidth)) dmaClient;\nendinterface\n\ninterface MemwriteIndication;\n   method Action started(Bit#(32) numWords);\n   method Action reportStateDbg(Bit#(32) wrCnt, Bit#(32) srcGen);\n   method Action writeDone(Bit#(32) v);\nendinterface\n\nmodule  mkMemwrite#(MemwriteIndication indication) (Memwrite);\n\n   Reg#(SGLId)   pointer <- mkReg(0);\n   Reg#(Bit#(32))       numWords <- mkReg(0);\n   Reg#(Bit#(32))       burstLen <- mkReg(0);\n   FIFOF#(void)               cf <- mkSizedFIFOF(1);\n\n   Vector#(NumEngineServers, Reg#(Bit#(32)))         srcGens <- replicateM(mkReg(0));\n   Reg#(Bit#(32))                                writeOffset <- mkReg(0);\n   Reg#(Bit#(32))                                    iterCnt <- mkReg(0);\n   Vector#(NumEngineServers, Reg#(Bit#(32)))        iterCnts <- replicateM(mkReg(0));\n   Vector#(NumEngineServers, FIFOF#(void))               cfs <- replicateM(mkSizedFIFOF(1));\n   Vector#(NumEngineServers, FIFOF#(Bool))       finishFifos <- replicateM(mkFIFOF);\n   MemWriteEngine#(DataBusWidth,DataBusWidth,8,NumEngineServers)                we <- mkMemWriteEngine;\n   Bit#(32) chunk = extend(numWords)*4;\n\n   for(Integer i = 0; i < valueOf(NumEngineServers); i=i+1) begin\n      rule start (iterCnts[i] > 0);\n\t we.writeServers[i].request.put(MemengineCmd{tag:0, sglId:pointer, base:extend(writeOffset)+(fromInteger(i)*chunk), len:truncate(chunk), burstLen:truncate(burstLen*4)});\n\t Bit#(32) srcGen = (fromInteger(i) << 28);\n\t srcGens[i] <= srcGen;\n\t $display(\"start %d/%d, %h 0x%x %h chunk=%h\", i, valueOf(NumEngineServers), srcGen, iterCnts[i], writeOffset, chunk);\n\t cfs[i].enq(?);\n\t iterCnts[i] <= iterCnts[i]-1;\n      endrule\n`ifdef MEMENGINE_REQUEST_CYCLES\n      rule requestCycles;\n\t let reqcycles <- toGet(we.writeServers[i].requestCycles).get();\n\t $display(\"request %d took %d cycles\", reqcycles.tag, reqcycles.cycles);\n      endrule\n`endif\n      rule finish;\n\t $display(\"finish %d 0x%x\", i, iterCnts[i]);\n\t let rv <- we.writeServers[i].done.get;\n\t finishFifos[i].enq(rv);\n      endrule\n      rule src if (cfs[i].notEmpty);\n\t Vector#(DataBusWords, Bit#(32)) v;\n\t for (Integer j = 0; j < valueOf(DataBusWords); j = j + 1)\n\t    v[j] = srcGens[i]+fromInteger(j);\n\t we.writeServers[i].data.enq(pack(v));\n\t let new_srcGen = srcGens[i]+fromInteger(valueOf(DataBusWords));\n\t srcGens[i] <= new_srcGen;\n\t if (new_srcGen[27:0] >= truncate(numWords))\n\t    cfs[i].deq;\n      endrule\n   end\n \n   PipeOut#(Vector#(NumEngineServers, Bool)) finishPipe <- mkJoinVector(id, map(toPipeOut, finishFifos));\n   PipeOut#(Bool) finishReducePipe <- mkReducePipe(uncurry(booland), finishPipe);\n\n   rule indicate_finish;\n      let rv <- toGet(finishReducePipe).get();\n      $display(\"indicate_finish rv=%d iterCnt=%d\", rv, iterCnt);\n      if (iterCnt == 1) begin\n\t cf.deq;\n\t indication.writeDone(0);\n      end\n      iterCnt <= iterCnt - 1;\n   endrule\n   \n   interface MemWriteClient dmaClient = cons(we.dmaClient, nil);\n   interface MemwriteRequest request;\n       method Action startWrite(Bit#(32) wp, Bit#(32) off, Bit#(32) nw, Bit#(32) bl, Bit#(32) ic);\n\t  $display(\"startWrite pointer=%d offset=%d numWords=%h burstLen=%d iterCnt=%d\", wp, off, nw, bl, ic);\n\t  indication.started(nw);\n\t  pointer <= wp;\n\t  cf.enq(?);\n\t  numWords  <= nw;\n\t  burstLen  <= bl;\n\t  iterCnt <= ic;\n\t  writeOffset <= off*4;\n\t  for(Integer i = 0; i < valueOf(NumEngineServers); i=i+1)\n\t     iterCnts[i] <= ic;\n       endmethod\n   endinterface\nendmodule\n"
  },
  {
    "path": "examples/memwrite/testmemwrite.cpp",
    "content": "/* Copyright (c) 2014 Quanta Research Cambridge, Inc\n *\n * Permission is hereby granted, free of charge, to any person obtaining a\n * copy of this software and associated documentation files (the \"Software\"),\n * to deal in the Software without restriction, including without limitation\n * the rights to use, copy, modify, merge, publish, distribute, sublicense,\n * and/or sell copies of the Software, and to permit persons to whom the\n * Software is furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n * DEALINGS IN THE SOFTWARE.\n */\n#include \"monkit.h\"\n#include \"dmaManager.h\"\n#include \"MemwriteIndication.h\"\n#include \"MemwriteRequest.h\"\n\n#ifdef BOARD_xsim\nstatic int numWords = 0x5000/4;\nstatic int iterCnt = 1;\n#elif defined(SIMULATION)\nstatic int numWords = 4096;\nstatic int iterCnt = 8;\n#else\nstatic int numWords = 0x1240000/4; // make sure to allocate at least one entry of each size\nstatic int iterCnt = 8;\n#endif\n#ifdef PCIE\nstatic int burstLen = 32;\nstatic int burstLenMin = 32;\nstatic int burstLenMax = 32;\n#elif defined(ZynqUltrascale)\nstatic int burstLen = 16;\nstatic int burstLenMin = 4;\nstatic int burstLenMax = 64; // 256byte = 16beats of 128bit\n#else\nstatic int burstLen = 16;\nstatic int burstLenMin = 16;\nstatic int burstLenMax = 16;\n#endif\n\n#ifdef NumEngineServers\nint numEngineServers = NumEngineServers;\n#else\nint numEngineServers = 1;\n#endif\n\nstatic sem_t test_sem;\nstatic size_t alloc_sz = numWords*sizeof(unsigned int);\n\nclass MemwriteIndication : public MemwriteIndicationWrapper\n{\npublic:\n    MemwriteIndication(int id, int tile=DEFAULT_TILE) : MemwriteIndicationWrapper(id,tile) {}\n    void started(uint32_t words) {\n        fprintf(stderr, \"Memwrite::started: words=%x\\n\", words);\n    }\n    void writeDone ( uint32_t srcGen ) {\n        fprintf(stderr, \"Memwrite::writeDone (%08x)\\n\", srcGen);\n        sem_post(&test_sem);\n    }\n    void reportStateDbg(uint32_t streamWrCnt, uint32_t srcGen) {\n        fprintf(stderr, \"Memwrite::reportStateDbg: streamWrCnt=%08x srcGen=%d\\n\", streamWrCnt, srcGen);\n    }\n};\n\nint main(int argc, const char **argv)\n{\n    int mismatch = 0;\n    uint32_t sg = 0;\n    int max_error = 10;\n\n    if (sem_init(&test_sem, 1, 0)) {\n        fprintf(stderr, \"error: failed to init test_sem\\n\");\n        exit(1);\n    }\n    fprintf(stderr, \"testmemwrite: start %s %s\\n\", __DATE__, __TIME__);\n    DmaManager *dma = platformInit();\n    MemwriteRequestProxy *device = new MemwriteRequestProxy(IfcNames_MemwriteRequestS2H);\n    MemwriteIndication deviceIndication(IfcNames_MemwriteIndicationH2S);\n\n    alloc_sz *= numEngineServers;\n\n    fprintf(stderr, \"main::allocating %lx bytes of memory...\\n\", (long)alloc_sz);\n    int dstAlloc = portalAlloc(alloc_sz, 0);\n    unsigned int *dstBuffer = (unsigned int *)portalMmap(dstAlloc, alloc_sz);\n#ifdef FPGA0_CLOCK_FREQ\n    long req_freq = FPGA0_CLOCK_FREQ, freq = 0;\n    setClockFrequency(0, req_freq, &freq);\n    fprintf(stderr, \"Requested FCLK[0]=%ld actually %ld\\n\", req_freq, freq);\n#endif\n    unsigned int ref_dstAlloc = dma->reference(dstAlloc);\n    for (int i = 0; i < numWords*numEngineServers; i++)\n        dstBuffer[i] = 0xDEADBEEF;\n    portalCacheFlush(dstAlloc, dstBuffer, alloc_sz, 1);\n    fprintf(stderr, \"testmemwrite: flush and invalidate complete\\n\");\n\n    burstLen = burstLenMin; // words\n    while (burstLen <= burstLenMax) {\n      fprintf(stderr, \"testmemwrite: starting write %#08x words burstLen=%d words\\n\", numWords, burstLen);\n      portalTimerStart(0);\n      device->startWrite(ref_dstAlloc, 0, numWords, burstLen, iterCnt);\n      sem_wait(&test_sem);\n      mismatch = 0;\n\t  sg = 0;\n      for (int i = 0; i < numWords; i++) {\n        if (dstBuffer[i] != sg) {\n\t  mismatch++;\n\t  if (max_error-- > 0)\n\t    fprintf(stderr, \"testmemwrite: [%d] actual %08x expected %08x\\n\", i, dstBuffer[i], sg);\n        }\n        sg++;\n      }\n      platformStatistics();\n      fprintf(stderr, \"testmemwrite: mismatch count %d.\\n\", mismatch);\n      burstLen *= 2;\n      if (mismatch)\n\texit(mismatch);\n\n      // now try with larger burstLen\n      burstLen *= 2;\n    }\n}\n"
  },
  {
    "path": "examples/memwrite128/Makefile",
    "content": "CONNECTALDIR?=../..\nS2H_INTERFACES = MemwriteRequest:Memwrite.request\nH2S_INTERFACES = Memwrite:MemwriteIndication\nMEM_WRITE_INTERFACES = lMemwrite.dmaClient\n\nBSVFILES = ../memwrite/Memwrite.bsv\nCPPFILES=../memwrite/testmemwrite.cpp\nCONNECTALFLAGS += --bscflags \" -show-schedule\"\nCONNECTALFLAGS += -D DataBusWidth=128\nCONNECTALFLAGS += -D USE_ACP\n\ninclude $(CONNECTALDIR)/Makefile.connectal\n"
  },
  {
    "path": "examples/memwrite256/Makefile",
    "content": "CONNECTALDIR?=../..\nS2H_INTERFACES = MemwriteRequest:Memwrite.request\nH2S_INTERFACES = Memwrite:MemwriteIndication\nMEM_WRITE_INTERFACES = lMemwrite.dmaClient\n\nBSVFILES = ../memwrite/Memwrite.bsv\nCPPFILES=../memwrite/testmemwrite.cpp\nCONNECTALFLAGS += --bscflags \" -show-schedule\"\nCONNECTALFLAGS += -D DataBusWidth=256\nCONNECTALFLAGS += -D USE_ACP\n# CONNECTALFLAGS += -D NumEngineServers=4\nCONNECTALFLAGS += --mainclockperiod=8 -D USE_WIDE_WIDTH\n\ninclude $(CONNECTALDIR)/Makefile.connectal\n"
  },
  {
    "path": "examples/memwrite_4m/Makefile",
    "content": "CONNECTALDIR?=../..\nS2H_INTERFACES = MemwriteRequest:Memwrite.request\nH2S_INTERFACES = Memwrite\\#\\(\\`NumberOfMasters\\):MemwriteIndication\nMEM_WRITE_INTERFACES = lMemwrite.dmaClients\n\nBSVFILES = Memwrite.bsv\nCPPFILES = ../memwrite/testmemwrite.cpp\nPLATFORM_NUMBER_OF_MASTERS =4\n\ninclude $(CONNECTALDIR)/Makefile.connectal\n"
  },
  {
    "path": "examples/memwrite_4m/Memwrite.bsv",
    "content": "// Copyright (c) 2013 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\nimport FIFO::*;\nimport FIFOF::*;\nimport Vector::*;\nimport ClientServer::*;\nimport GetPut::*;\nimport ConnectalMemTypes::*;\nimport MemWriteEngine::*;\nimport Pipe::*;\nimport Arith::*;\nimport ConnectalMemUtils::*;\nimport ConnectalConfig::*;\nimport StmtFSM ::*;\n\ninterface MemwriteRequest;\n   method Action startWrite(Bit#(32) pointer, Bit#(32) offset, Bit#(32) numWords, Bit#(32) burstLen, Bit#(32) iterCnt);\n   method Action getStateDbg();   \nendinterface\n\ninterface Memwrite#(numeric type nClients);\n   interface MemwriteRequest request;\n   interface Vector#(nClients,MemWriteClient#(64)) dmaClients;\nendinterface\n\ninterface MemwriteIndication;\n   method Action started(Bit#(32) numWords);\n   method Action reportStateDbg(Bit#(32) wrCnt, Bit#(32) srcGen);\n   method Action writeDone(Bit#(32) v);\nendinterface\n\nmodule  mkMemwrite#(MemwriteIndication indication) (Memwrite#(4));\n\n   Reg#(SGLId)     pointer <- mkReg(0);\n   Reg#(Bit#(32))         numWords <- mkReg(0);\n   Reg#(Bit#(32))         burstLen <- mkReg(0);\n   Reg#(Bit#(32))          iterCnt <- mkReg(0);\n   Reg#(Bit#(32))        startBase <- mkReg(0);\n   Reg#(Bit#(3))          startPtr <- mkReg(0);\n   Reg#(Bit#(3))         finishPtr <- mkReg(0);\n   FIFO#(void)           startFifo <- mkFIFO;\n\n   Vector#(4,Reg#(Bit#(32)))      srcGens <- replicateM(mkReg(0));\n   Vector#(4,MemWriteEngine#(64,64,2,1))   wes <- replicateM(mkMemWriteEngine);\n\n   Stmt startStmt = seq\n\t\t       startBase <= 0;\n\t\t       for(startPtr <= 0; startPtr < 4; startPtr <= startPtr+1)\n\t\t\t  (action\n\t\t\t      $display(\"start:%d %h %d %h (%d)\", startPtr, startBase, numWords, burstLen*4, iterCnt);\n\t\t\t      wes[startPtr].writeServers[0].request.put(MemengineCmd{sglId:pointer, base:extend(startBase), len:numWords, burstLen:truncate(burstLen*4), tag:0});\n\t\t\t      startBase <= startBase+numWords;\n\t\t\t   endaction);\n\t\t    endseq;\n   FSM startFSM <- mkFSM(startStmt);\n\n   rule start (iterCnt > 0);\n      startFifo.deq;\n      startFSM.start;\n      iterCnt <= iterCnt-1;\n   endrule\n   \n   rule finish;\n      for(Integer i = 0; i < 4; i=i+1) begin\n\t $display(\"finish: %d (%d)\", i, iterCnt);\n\t let rv <- wes[i].writeServers[0].done.get;\n      end\n      if (iterCnt == 0)\n\t indication.writeDone(0);\n      else\n\t startFifo.enq(?);\n   endrule\n   \n   for(Integer i = 0; i < 4; i=i+1)\n      rule src;\n\t wes[i].writeServers[0].data.enq({srcGens[i]+1,srcGens[i]});\n\t if (srcGens[i]+2 == fromInteger(i+1)*(numWords>>2)) begin\n\t    //$display(\"src %d %d\", i, srcGens[i]+1);\n\t    srcGens[i] <= fromInteger(i)*(numWords>>2);\n\t end\n\t else\n\t    srcGens[i] <= srcGens[i]+2;\n      endrule\n\n   function MemWriteClient#(64) dc(MemWriteEngine#(64,64,2,1) we) = we.dmaClient;\n   interface dmaClients = map(dc,wes);\n   interface MemwriteRequest request;\n      method Action startWrite(Bit#(32) wp, Bit#(32) ofs, Bit#(32) nw, Bit#(32) bl, Bit#(32) ic);\n\t  $display(\"startWrite pointer=%d numWords=%h burstLen=%d iterCnt=%d\", pointer, nw, bl, ic);\n\t  indication.started(nw);\n\t  pointer <= wp;\n\t  numWords <= nw;\n\t  burstLen <= bl;\n\t  iterCnt <= ic;\n\t  for(Integer i = 0; i < 4; i=i+1)\n\t     srcGens[i] <= fromInteger(i)*(nw>>2);\n\t  startFifo.enq(?);\n       endmethod\n       method Action getStateDbg();\n\t  indication.reportStateDbg(iterCnt, srcGens[0]);\n       endmethod\n   endinterface\nendmodule\n"
  },
  {
    "path": "examples/nandsim/Makefile",
    "content": "CONNECTALDIR?=../..\nS2H_INTERFACES = NandCfgRequest:NandSim.request\nH2S_INTERFACES = NandSim:NandCfgIndication\nMEM_READ_INTERFACES = lNandSim.readClient\nMEM_WRITE_INTERFACES = lNandSim.writeClient\n\nBSVFILES = $(CONNECTALDIR)/lib/nandsim/bsv/NandSim.bsv\nCPPFILES=testnandsim.cpp\nCONNECTALFLAGS += -I$(CONNECTALDIR)/lib/nandsim/cpp\n\ninclude $(CONNECTALDIR)/Makefile.connectal\n"
  },
  {
    "path": "examples/nandsim/testnandsim.cpp",
    "content": "/* Copyright (c) 2014 Quanta Research Cambridge, Inc\n *\n * Permission is hereby granted, free of charge, to any person obtaining a\n * copy of this software and associated documentation files (the \"Software\"),\n * to deal in the Software without restriction, including without limitation\n * the rights to use, copy, modify, merge, publish, distribute, sublicense,\n * and/or sell copies of the Software, and to permit persons to whom the\n * Software is furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n * DEALINGS IN THE SOFTWARE.\n */\n#include <fcntl.h>\n#include <errno.h>\n#include <sys/types.h>\n#include <sys/socket.h>\n#include <sys/un.h>\n#include \"dmaManager.h\"\n#include \"NandCfgIndication.h\"\n#include \"NandCfgRequest.h\"\n#include \"nandsim.h\"\n\nstatic int trace_memory = 1;\nextern \"C\" {\n#include \"userReference.h\"\n}\n\nusing namespace std;\n\nclass NandCfgIndication : public NandCfgIndicationWrapper\n{\npublic:\n  unsigned int rDataCnt;\n  virtual void readDone(uint32_t v){\n    fprintf(stderr, \"NandSim::readDone v=%x\\n\", v);\n    sem_post(&sem);\n  }\n  virtual void writeDone(uint32_t v){\n    fprintf(stderr, \"NandSim::writeDone v=%x\\n\", v);\n    sem_post(&sem);\n  }\n  virtual void eraseDone(uint32_t v){\n    fprintf(stderr, \"NandSim::eraseDone v=%x\\n\", v);\n    sem_post(&sem);\n  }\n  virtual void configureNandDone(){\n    fprintf(stderr, \"NandSim::configureNandDone\\n\");\n    sem_post(&sem);\n  }\n\n  NandCfgIndication(int id) : NandCfgIndicationWrapper(id) {\n    sem_init(&sem, 0, 0);\n  }\n  void wait() {\n    fprintf(stderr, \"NandSim::wait for semaphore\\n\");\n    sem_wait(&sem);\n  }\nprivate:\n  sem_t sem;\n};\n\nint main(int argc, const char **argv)\n{\n\n#ifndef BOARD_bluesim\n  size_t nandBytes = 1 << 12;\n#else\n  size_t nandBytes = 1 << 18;\n#endif\n\n  fprintf(stderr, \"testnandsim::%s %s\\n\", __DATE__, __TIME__);\n\n  DmaManager *hostDma = platformInit();\n  NandCfgRequestProxy *nandcfgRequest = new NandCfgRequestProxy(IfcNames_NandCfgRequestS2H);\n  NandCfgIndication *nandcfgIndication = new NandCfgIndication(IfcNames_NandCfgIndicationH2S);\n\n  int nandAlloc = portalAlloc(nandBytes, 0);\n  fprintf(stderr, \"testnandsim::nandAlloc=%d\\n\", nandAlloc);\n  int ref_nandAlloc = hostDma->reference(nandAlloc);\n  fprintf(stderr, \"ref_nandAlloc=%d\\n\", ref_nandAlloc);\n  fprintf(stderr, \"testnandsim::NAND alloc fd=%d ref=%d\\n\", nandAlloc, ref_nandAlloc);\n  nandcfgRequest->configureNand(ref_nandAlloc, nandBytes);\n  nandcfgIndication->wait();\n\n#ifndef ALGO_NANDSIM\n  if (argc == 1) {\n\n    fprintf(stderr, \"testnandsim::allocating memory...\\n\");\n    size_t srcBytes = nandBytes>>2;\n    int srcAlloc = portalAlloc(srcBytes, 0);\n    unsigned int *srcBuffer = (unsigned int *)portalMmap(srcAlloc, srcBytes);\n    unsigned int ref_srcAlloc = hostDma->reference(srcAlloc);\n    fprintf(stderr, \"testnandsim::fd=%d, srcBuffer=%p\\n\", srcAlloc, srcBuffer);\n\n    /* do tests */\n    fprintf(stderr, \"testnandsim::chamdoo-test\\n\");\n    unsigned long loop = 0;\n    unsigned long match = 0, mismatch = 0;\n\n    while (loop < nandBytes) {\n\n      fprintf(stderr, \"testnandsim::starting write ref=%d, len=%08zx (%lu)\\n\", ref_srcAlloc, srcBytes, loop);\n      for (unsigned int i = 0; i < srcBytes/sizeof(srcBuffer[0]); i++) {\n\tsrcBuffer[i] = loop+i;\n      }\n      portalCacheFlush(srcAlloc, srcBuffer, srcBytes, 1);\n      nandcfgRequest->startWrite(ref_srcAlloc, 0, loop, srcBytes, 16);\n      nandcfgIndication->wait();\n      loop+=srcBytes;\n    }\n    fprintf(stderr, \"testnandsim:: write phase complete\\n\");\n    loop = 0;\n    while (loop < nandBytes) {\n      fprintf(stderr, \"testnandsim::starting read %08zx (%lu)\\n\", srcBytes, loop);\n\n      for (unsigned int i = 0; i < srcBytes/sizeof(srcBuffer[0]); i++) {\n\tsrcBuffer[i] = 5;\n      }\n\n      portalCacheFlush(srcAlloc, srcBuffer, srcBytes, 1);\n      nandcfgRequest->startRead(ref_srcAlloc, 0, loop, srcBytes, 16);\n      nandcfgIndication->wait();\n      \n      for (unsigned int i = 0; i < srcBytes/sizeof(srcBuffer[0]); i++) {\n\tif (srcBuffer[i] != loop+i) {\n\t  fprintf(stderr, \"testnandsim::mismatch [%08ld] != [%08d] (%d,%zu)\\n\", loop+i, srcBuffer[i], i, srcBytes/sizeof(srcBuffer[0]));\n\t  mismatch++;\n\t} else {\n\t  match++;\n\t}\n      }\n      \n      loop+=srcBytes;\n    }\n    /* end */\n    \n    //uint64_t beats_r = hostDma->show_mem_stats(ChannelType_Read);\n    //uint64_t beats_w = hostDma->show_mem_stats(ChannelType_Write);\n\n    fprintf(stderr, \"testnandsim::Summary: match=%lu mismatch:%lu (%lu) (%f percent)\\n\", match, mismatch, match+mismatch, (float)mismatch/(float)(match+mismatch)*100.0);\n    //fprintf(stderr, \"(%\"PRIx64\", %\"PRIx64\")\\n\", beats_r, beats_w);\n    \n    return (mismatch > 0);\n  } else\n#endif\n  {\n\n    // else we were invoked by alg1_nandsim\n    const char *filename = \"../test.bin\";\n    fprintf(stderr, \"testnandsim::opening %s\\n\", filename);\n    // open up the text file and read it into an allocated memory buffer\n    int dataFile = open(filename, O_RDONLY);\n    off_t data_len = lseek(dataFile, 0, SEEK_END);\n    data_len = data_len & ~15; // because we are using a burst length of 16\n    lseek(dataFile, 0, SEEK_SET);\n\n    int dataAlloc = portalAlloc(data_len, 0);\n    int ref_dataAlloc = hostDma->reference(dataAlloc);\n    char *data = (char *)portalMmap(dataAlloc, data_len);\n    ssize_t read_len = read(dataFile, data, data_len); \n    if(read_len != data_len) {\n      fprintf(stderr, \"testnandsim::error reading %s %ld %ld\\n\", filename, (long)data_len, (long) read_len);\n      exit(-1);\n    }\n\n    // write the contents of data into \"flash\" memory\n    portalCacheFlush(ref_dataAlloc, data, data_len, 1);\n    fprintf(stderr, \"testnandsim::invoking write %08x %08lx\\n\", ref_dataAlloc, (long)data_len);\n    nandcfgRequest->startWrite(ref_dataAlloc, 0, 0, data_len, 16);\n    nandcfgIndication->wait();\n\n    fprintf(stderr, \"testnandsim::connecting to algo_exe...\\n\");\n    connect_to_algo_exe();\n    fprintf(stderr, \"testnandsim::connected to algo_exe\\n\");\n\n    // send the offset and length (in nandsim) of the text\n    write_to_algo_exe(0);\n    write_to_algo_exe(data_len);\n    printf(\"[%s:%d] sleep, waiting for search\\n\", __FUNCTION__, __LINE__);\n    sleep(200);\n    printf(\"[%s:%d] now closing down\\n\", __FUNCTION__, __LINE__);\n  }\n}\n"
  },
  {
    "path": "examples/portal-synth-boundary/Makefile",
    "content": "CONNECTALDIR?=../..\nINTERFACES = SimpleRequest SimpleIndication\n\nBSVFILES = Simple.bsv Top.bsv\nCPPFILES=testsimple.cpp\n\ninclude $(CONNECTALDIR)/Makefile.connectal\n"
  },
  {
    "path": "examples/portal-synth-boundary/Simple.bsv",
    "content": "\n// Copyright (c) 2013 Nokia, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\nimport FIFO::*;\n\ninterface SimpleIndication;\n    method Action heard1(Bit#(32) v);\nendinterface\n\ninterface SimpleResponse;\n   method ActionValue#(Bit#(32)) heard1();\nendinterface\n\ninterface SimpleRequest;\n    method Action say1(Bit#(32) v);\nendinterface\n\n\ninterface Simple;\n   interface SimpleRequest request;\n   interface SimpleResponse response;\nendinterface\n\n// Because mkSimple has a synthesis boundary, it cannot take\n// SimpleIndication as an interface parameter. Therefore, it exports a\n// complementary interface: SimpleResponse, where each Action method\n// from SimpleIndication has a corresponding ActionValue method.\n\n(* synthesize *)\nmodule mkSimple(Simple);\n   FIFO#(Bit#(32)) vFifo <- mkFIFO();\n   interface SimpleRequest request;\n      method Action say1(Bit#(32) v);\n\t vFifo.enq(v);\n      endmethod\n   endinterface\n   interface SimpleResponse response;\n      method ActionValue#(Bit#(32)) heard1();\n\t vFifo.deq();\n\t return vFifo.first();\n      endmethod\n   endinterface\nendmodule"
  },
  {
    "path": "examples/portal-synth-boundary/Top.bsv",
    "content": "/* Copyright (c) 2014 Quanta Research Cambridge, Inc\n *\n * Permission is hereby granted, free of charge, to any person obtaining a\n * copy of this software and associated documentation files (the \"Software\"),\n * to deal in the Software without restriction, including without limitation\n * the rights to use, copy, modify, merge, publish, distribute, sublicense,\n * and/or sell copies of the Software, and to permit persons to whom the\n * Software is furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n * DEALINGS IN THE SOFTWARE.\n */\nimport Vector::*;\nimport FIFO::*;\nimport Connectable::*;\nimport CtrlMux::*;\nimport Portal::*;\nimport ConnectalConfig::*;\nimport SimpleIndication::*;\nimport SimpleRequest::*;\nimport Simple::*;\n\ntypedef enum {IfcNames_SimpleIndication, IfcNames_SimpleRequest} IfcNames deriving (Eq,Bits);\n\nmodule mkConnectalTop(ConnectalTop);\n   SimpleIndicationProxy simpleIndicationProxy <- mkSimpleIndicationProxy(IfcNames_SimpleIndication);\n   Simple simpleRequest <- mkSimple();\n   SimpleRequestWrapper simpleRequestWrapper <- mkSimpleRequestWrapper(IfcNames_SimpleRequest,simpleRequest.request);\n   // connect the ActionValue heard1 to the Action method heard1\n   mkConnection(simpleRequest.response.heard1, simpleIndicationProxy.ifc.heard1);\n   \n   Vector#(2,StdPortal) portals;\n   portals[0] = simpleRequestWrapper.portalIfc; \n   portals[1] = simpleIndicationProxy.portalIfc;\n   let ctrl_mux <- mkSlaveMux(portals);\n   \n   interface interrupt = getInterruptVector(portals);\n   interface slave = ctrl_mux;\n   interface masters = nil;\nendmodule : mkConnectalTop\n\n\n"
  },
  {
    "path": "examples/portal-synth-boundary/testsimple.cpp",
    "content": "/* Copyright (c) 2014 Quanta Research Cambridge, Inc\n *\n * Permission is hereby granted, free of charge, to any person obtaining a\n * copy of this software and associated documentation files (the \"Software\"),\n * to deal in the Software without restriction, including without limitation\n * the rights to use, copy, modify, merge, publish, distribute, sublicense,\n * and/or sell copies of the Software, and to permit persons to whom the\n * Software is furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n * DEALINGS IN THE SOFTWARE.\n */\n\n#include <stdio.h>\n#include <stdlib.h>\n#include <unistd.h>\n#include <assert.h>\n\n#include \"SimpleIndication.h\"\n#include \"SimpleRequest.h\"\n#include \"GeneratedTypes.h\"\n\n\nint v1a = 42;\n\n\nclass SimpleIndication : public SimpleIndicationWrapper\n{  \npublic:\n  uint32_t cnt;\n  void incr_cnt(){\n    if (++cnt == 1)\n      exit(0);\n  }\n  virtual void heard1(uint32_t a) {\n    fprintf(stderr, \"heard1(%d)\\n\", a);\n    assert(a == v1a);\n    incr_cnt();\n  }\n  SimpleIndication(unsigned int id) : SimpleIndicationWrapper(id), cnt(0){}\n};\n\n\n\nint main(int argc, const char **argv)\n{\n  SimpleIndication *indication = new SimpleIndication(IfcNames_SimpleIndication);\n  SimpleRequestProxy *device = new SimpleRequestProxy(IfcNames_SimpleRequest);\n\n  fprintf(stderr, \"Main::calling say1(%d)\\n\", v1a);\n  device->say1(v1a);  \n\n  fprintf(stderr, \"Main::about to go to sleep\\n\");\n  while(true){sleep(2);}\n}\n"
  },
  {
    "path": "examples/printf/Echo.bsv",
    "content": "\n// Copyright (c) 2013 Nokia, Inc.\n// Copyright (c) 2013 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\nimport FIFO::*;\nimport DisplayInd::*;\n\ninterface EchoIndication;\n    method Action heard(Bit#(32) v);\n    method Action heard2(Bit#(16) a, Bit#(16) b);\nendinterface\n\ninterface EchoRequest;\n   method Action say(Bit#(32) v);\n   method Action say2(Bit#(16) a, Bit#(16) b);\n   method Action setLeds(Bit#(8) v);\nendinterface\n\ninterface EchoRequestInternal;\n   interface EchoRequest ifc;\nendinterface\n\ntypedef struct {\n\tBit#(16) a;\n\tBit#(16) b;\n} EchoPair deriving (Bits);\n\nmodule mkEchoRequestInternal#(EchoIndication indication, DisplayInd printfInd)(EchoRequestInternal);\n\n    FIFO#(Bit#(32)) delay <- mkSizedFIFO(8);\n    FIFO#(EchoPair) delay2 <- mkSizedFIFO(8);\n\n    rule heard;\n        delay.deq;\n        indication.heard(delay.first);\n    endrule\n\n    rule heard2;\n        delay2.deq;\n        indication.heard2(delay2.first.b, delay2.first.a);\n    endrule\n   \n   interface EchoRequest ifc;\n      method Action say(Bit#(32) v);\n         $display(\"Echo: say %x\", v);\n\t delay.enq(v);\n      endmethod\n      \n      method Action say2(Bit#(16) a, Bit#(16) b);\n         //$display(\"Echo: say2 %x %x\", extend(a), extend(b));\n\t delay2.enq(EchoPair { a: a, b: b});\n      endmethod\n      \n      method Action setLeds(Bit#(8) v);\n      endmethod\n   endinterface\nendmodule\n"
  },
  {
    "path": "examples/printf/Makefile",
    "content": "CONNECTALDIR?=../..\nINTERFACES = Swallow EchoRequest EchoIndication DisplayInd\n\nBSVFILES = Echo.bsv SwallowIF.bsv Top.bsv\nCPPFILES=testecho.cpp\nUSE_PRINTF = 1\n\ninclude $(CONNECTALDIR)/Makefile.connectal\n"
  },
  {
    "path": "examples/printf/SwallowIF.bsv",
    "content": "\n// Copyright (c) 2013 Nokia, Inc.\n// Copyright (c) 2013 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\ninterface Swallow;\n   method Action swallow(Bit#(32) v);\nendinterface\n\nmodule mkSwallow (Swallow);\n   Reg#(Bit#(32)) sink <- mkReg(0);\n   \n   method Action swallow(Bit#(32) v);\n      sink <= v;\n   endmethod\nendmodule\n"
  },
  {
    "path": "examples/printf/Top.bsv",
    "content": "/* Copyright (c) 2014 Quanta Research Cambridge, Inc\n *\n * Permission is hereby granted, free of charge, to any person obtaining a\n * copy of this software and associated documentation files (the \"Software\"),\n * to deal in the Software without restriction, including without limitation\n * the rights to use, copy, modify, merge, publish, distribute, sublicense,\n * and/or sell copies of the Software, and to permit persons to whom the\n * Software is furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n * DEALINGS IN THE SOFTWARE.\n */\nimport Vector::*;\nimport FIFO::*;\nimport Connectable::*;\nimport Portal::*;\nimport CtrlMux::*;\nimport ConnectalConfig::*;\nimport EchoIndication::*;\nimport EchoRequest::*;\nimport Swallow::*;\nimport Echo::*;\nimport SwallowIF::*;\nimport DisplayInd::*;\n\ntypedef enum {IfcNames_EchoIndication, IfcNames_EchoRequest, IfcNames_Swallow, IfcNames_DisplayInd} IfcNames deriving (Eq,Bits);\n\nmodule mkConnectalTop(ConnectalTop);\n   EchoIndicationProxy echoIndicationProxy <- mkEchoIndicationProxy(IfcNames_EchoIndication);\n   DisplayIndProxy displayIndProxy <- mkDisplayIndProxy(IfcNames_DisplayInd);\n   EchoRequestInternal echoRequestInternal <- mkEchoRequestInternal(echoIndicationProxy.ifc, displayIndProxy.ifc);\n   EchoRequestWrapper echoRequestWrapper <- mkEchoRequestWrapper(IfcNames_EchoRequest,echoRequestInternal.ifc);\n   \n   Swallow swallow <- mkSwallow();\n   SwallowWrapper swallowWrapper <- mkSwallowWrapper(IfcNames_Swallow, swallow);\n   \n   Vector#(4,StdPortal) portals;\n   portals[0] = echoIndicationProxy.portalIfc;\n   portals[1] = echoRequestWrapper.portalIfc; \n   portals[2] = swallowWrapper.portalIfc; \n   portals[3] = displayIndProxy.portalIfc; \n   let ctrl_mux <- mkSlaveMux(portals);\n   \n   interface interrupt = getInterruptVector(portals);\n   interface slave = ctrl_mux;\n   interface masters = nil;\nendmodule : mkConnectalTop\n"
  },
  {
    "path": "examples/printf/testecho.cpp",
    "content": "/* Copyright (c) 2014 Quanta Research Cambridge, Inc\n *\n * Permission is hereby granted, free of charge, to any person obtaining a\n * copy of this software and associated documentation files (the \"Software\"),\n * to deal in the Software without restriction, including without limitation\n * the rights to use, copy, modify, merge, publish, distribute, sublicense,\n * and/or sell copies of the Software, and to permit persons to whom the\n * Software is furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n * DEALINGS IN THE SOFTWARE.\n */\n\n#include <stdio.h>\n#include <stdlib.h>\n#include <pthread.h>\n#include <semaphore.h>\n#include <unistd.h>\n\n#include \"EchoIndication.h\"\n#include \"DisplayInd.h\"\n#include \"EchoRequest.h\"\n#include \"GeneratedTypes.h\"\n#include \"Swallow.h\"\n\n#define LOOP_COUNT 1//000\n#define SEPARATE_EVENT_THREAD\n//#define USE_MUTEX_SYNC\n\nEchoRequestProxy *echoRequestProxy = 0;\n\n#ifndef SEPARATE_EVENT_THREAD\ntypedef int SEM_TYPE;\n#define SEMPOST(A) (*(A))++\n#define SEMWAIT pthread_worker\n#elif defined(USE_MUTEX_SYNC)\ntypedef pthread_mutex_t SEM_TYPE;\n#define SEMINIT(A) pthread_mutex_lock(A);\n#define SEMWAIT(A) pthread_mutex_lock(A);\n#define SEMPOST(A) pthread_mutex_unlock(A);\n#else // use semaphores\ntypedef sem_t SEM_TYPE;\n#define SEMINIT(A) sem_init(A, 0, 0);\n#define SEMWAIT(A) sem_wait(A);\n#define SEMPOST(A) sem_post(A)\n#endif\n\n#ifdef SEPARATE_EVENT_THREAD\n#define PREPAREWAIT(A)\n#define CHECKSEM(A) 1\n#else // use inline sync\n#define PREPAREWAIT(A) (A) = 0\n#define CHECKSEM(A) (!(A))\n#endif\n\nstatic SEM_TYPE sem_heard2;\n\nPortalPoller *poller = 0;\n\nstatic void *pthread_worker(void *p)\n{\n    void *rc = NULL;\n    while (CHECKSEM(sem_heard2) && !rc && !poller->stopping) {\n        rc = poller->pollFn(poller->timeout);\n        if ((long)rc >= 0)\n            rc = poller->event();\n    }\n    return rc;\n}\nstatic void init_thread()\n{\n#ifdef SEPARATE_EVENT_THREAD\n    pthread_t threaddata;\n    SEMINIT(&sem_heard2);\n    pthread_create(&threaddata, NULL, &pthread_worker, (void*)poller);\n#endif\n}\n\nclass EchoIndication : public EchoIndicationWrapper\n{\npublic:\n    virtual void heard(uint32_t v) {\n        fprintf(stderr, \"heard an echo: %d\\n\", v);\n\techoRequestProxy->say2(v, 2*v);\n    }\n    virtual void heard2(uint16_t a, uint16_t b) {\n        portalTimerCatch(20);\n        SEMPOST(&sem_heard2);\n        //fprintf(stderr, \"heard an echo2: %ld %ld\\n\", a, b);\n        //portalTimerCatch(25);\n    }\n    EchoIndication(unsigned int id, PortalPoller *poller) : EchoIndicationWrapper(id, poller) {}\n};\n\n#include \"printfInd.h\"\n\nstatic void call_say(int v)\n{\n    printf(\"[%s:%d] %d\\n\", __FUNCTION__, __LINE__, v);\n    portalTimerStart(0);\n    PREPAREWAIT(sem_heard2);\n    echoRequestProxy->say(v);\n    SEMWAIT(&sem_heard2);\n    printf(\"call_say: elapsed %\" PRIu64 \"\\n\", portalTimerLap(0));\n}\n\nstatic void call_say2(int v, int v2)\n{\n    portalTimerStart(0);\n    PREPAREWAIT(sem_heard2);\n    portalTimerCatch(0);\n    echoRequestProxy->say2(v, v2);\n    portalTimerCatch(19);\n    SEMWAIT(&sem_heard2);\n    portalTimerCatch(30);\n}\n\nint main(int argc, const char **argv)\n{\n    poller = new PortalPoller();\n    EchoIndication *echoIndication = new EchoIndication(IfcNames_EchoIndication, poller);\n    DisplayInd *dispIndication = new DisplayInd(IfcNames_DisplayInd, poller);\n    // these use the default poller\n    SwallowProxy *swallowProxy = new SwallowProxy(IfcNames_Swallow);\n    echoRequestProxy = new EchoRequestProxy(IfcNames_EchoRequest);\n\n    poller->init();\n    init_thread();\n\n#if 0\n    printf(\"Timer tests\\n\");\n    portalTimerInit();\n    for (int i = 0; i < 1000; i++) {\n      portalTimerStart(0);\n      portalTimerCatch(1);\n      portalTimerCatch(2);\n      portalTimerCatch(3);\n      portalTimerCatch(4);\n      portalTimerCatch(5);\n      portalTimerCatch(6);\n      portalTimerCatch(7);\n      portalTimerCatch(8);\n    }\n    portalTimerPrint(1000);\n#endif\n\n    int v = 42;\n    fprintf(stderr, \"Saying %d\\n\", v);\n    call_say(v);\n    call_say(v*5);\n    call_say(v*17);\n    call_say(v*93);\n    printf(\"[%s:%d] run %d loops\\n\\n\", __FUNCTION__, __LINE__, LOOP_COUNT);\n    portalTimerInit();\n    portalTimerStart(1);\n    for (int i = 0; i < LOOP_COUNT; i++)\n        call_say2(v, v*3);\nuint64_t elapsed = portalTimerLap(1);\n    printf(\"TEST TYPE: \"\n#ifndef SEPARATE_EVENT_THREAD\n       \"INLINE\"\n#elif defined(USE_MUTEX_SYNC)\n       \"MUTEX\"\n#else\n       \"SEM\"\n#endif\n       \"\\n\");\n    portalTimerPrint(LOOP_COUNT);\n    printf(\"call_say: elapsed %g average %g\\n\", (double) elapsed, (double) elapsed/ (double) LOOP_COUNT);\n    echoRequestProxy->setLeds(9);\n    return 0;\n}\n"
  },
  {
    "path": "examples/rbm/LICENSE.txt",
    "content": "Copyright (c) 2013,2014 Quanta Research Cambridge, Inc.\n\nPermission is hereby granted, free of charge, to any person\nobtaining a copy of this software and associated documentation\nfiles (the \"Software\"), to deal in the Software without\nrestriction, including without limitation the rights to use, copy,\nmodify, merge, publish, distribute, sublicense, and/or sell copies\nof the Software, and to permit persons to whom the Software is\nfurnished to do so, subject to the following conditions:\n\nThe above copyright notice and this permission notice shall be\nincluded in all copies or substantial portions of the Software.\n\nTHE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\nEXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\nMERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\nNONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\nBE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\nACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\nCONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\nSOFTWARE.\n"
  },
  {
    "path": "examples/rbm/Makefile",
    "content": "CONNECTALDIR?=../..\nBSCFLAGS=-aggressive-conditions -show-schedule -keep-fires -p +:../paclib\nCONNECTALFLAGS = -D J_VALUE=1 -D K_VALUE=1 -D N_VALUE=1 -D DataBusWidth=32\n\nMMDIR=../matmul\nRBMDIR=../rbm\nTESTCPPFILES= testrbm.cpp\n\ninclude $(MMDIR)/Makefile.mm\ninclude $(RBMDIR)/Makefile.rbm\ninclude $(CONNECTALDIR)/Makefile.connectal\n"
  },
  {
    "path": "examples/rbm/Makefile.rbm",
    "content": "S2H_INTERFACES += RbmRequest:Rbm.rbmRequest MmRequestTN:Rbm.mmRequest SigmoidRequest:Rbm.sigmoidRequest TimerRequest:Rbm.timerRequest\nH2S_INTERFACES += Rbm\\#\\(TDiv\\#\\(DataBusWidth,32\\)\\):RbmIndication,SigmoidIndication,MmIndication,TimerIndication:host\nMEM_READ_INTERFACES = lRbm.readClients\nMEM_WRITE_INTERFACES = lRbm.writeClients\n\ngen:: $(RBMDIR)/datasets\n\n$(RBMDIR)/datasets:\n\tmkdir -p $(RBMDIR)/datasets\n\t(cd $(RBMDIR)/datasets; curl -O http://yann.lecun.com/exdb/mnist/train-images-idx3-ubyte.gz)\n\t(cd $(RBMDIR)/datasets; curl -O http://yann.lecun.com/exdb/mnist/train-labels-idx1-ubyte.gz)\n\t(cd $(RBMDIR)/datasets; curl -O http://yann.lecun.com/exdb/mnist/t10k-images-idx3-ubyte.gz)\n\t(cd $(RBMDIR)/datasets; curl -O http://yann.lecun.com/exdb/mnist/t10k-labels-idx1-ubyte.gz)\n\tcd $(RBMDIR)/datasets; gunzip *.gz\n\nCONNECTALFLAGS  +=  -D RBMDIR='\\\"'$(RBMDIR)'\\\"'\nCONNECTALFLAGS += -I$(RBMDIR)/cpp\n\nBSVFILES += $(CONNECTALDIR)/lib/rbm/bsv/Rbm.bsv\nCPPFILES += $(CONNECTALDIR)/lib/rbm/cpp/rbm.cpp\n\nprebuild:: $(RBMDIR)/datasets\n\tcp -fv $(RBMDIR)/datasets/train-images-idx3-ubyte .\n"
  },
  {
    "path": "examples/rbm/Readme.md",
    "content": "\nBSV implementation of Restricted Boltzmann Machine modeled on\n    git://github.com/echen/restricted-boltzmann-machines\n\nMNIST numeric digit data from:\n    http://yann.lecun.com/exdb/mnist/\n"
  },
  {
    "path": "examples/rbm/testrbm.cpp",
    "content": "\n// Copyright (c) 2014 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\n#include <RbmRequest.h>\n#include <RbmIndication.h>\n#include \"MemServerRequest.h\"\n#include \"MMURequest.h\"\n#include <stdio.h>\n#include <sys/mman.h>\n#include <string.h>\n#include <stdlib.h>\n#include <unistd.h>\n#include <semaphore.h>\n#include <pthread.h>\n#include <errno.h>\n#include <math.h> // frexp(), fabs()\n#include <assert.h>\n#include \"portalmat.h\"\n#include \"rbm.h\"\n#include \"mnist.h\"\n\nMmRequestTNProxy *mmdevice = 0;\nMemServerRequestProxy *hostMemServerRequest;\nMmIndication *mmdeviceIndication = 0;\nSigmoidIndication *sigmoidindication = 0;\nSigmoidRequestProxy *sigmoiddevice = 0;\nRbmIndication *rbmDeviceIndication = 0;\nRbmRequestProxy *rbmdevice = 0;\nTimerIndication *timerdeviceIndication = 0;\nTimerRequestProxy *timerdevice = 0;\n\nlong dotprod = 0;\n\nvoid dump(const char *prefix, char *buf, size_t len)\n{\n    fprintf(stderr, \"%s \", prefix);\n    for (unsigned int i = 0; i < (len > 64 ? 64 : len) ; i++) {\n\tfprintf(stderr, \"%02x\", (unsigned char)buf[i]);\n\tif (i % 4 == 3)\n\t  fprintf(stderr, \" \");\n    }\n    fprintf(stderr, \"\\n\");\n}\n\nvoid *dbgThread(void *)\n{\n  while (1) {\n    sleep(1);\n    mmdevice->debug();\n    //rbmdevice->sumOfErrorSquaredDebug();\n    if (hostMemServerRequest) hostMemServerRequest->stateDbg(ChannelType_Read);\n    sleep(5);\n  }\n  return 0;\n}\n\nint main(int argc, const char **argv)\n{\n  fprintf(stderr, \"%s %s\\n\", __DATE__, __TIME__);\n \n  mmdevice = new MmRequestTNProxy(IfcNames_MmRequestTNS2H);\n  rbmdevice = new RbmRequestProxy(IfcNames_RbmRequestS2H);\n  rbmDeviceIndication = new RbmIndication(IfcNames_RbmIndicationH2S);\n  mmdeviceIndication = new MmIndication(IfcNames_MmIndicationH2S);\n  sigmoiddevice = new SigmoidRequestProxy(IfcNames_SigmoidRequestS2H);\n  sigmoidindication = new SigmoidIndication(IfcNames_SigmoidIndicationH2S);\n  timerdevice = new TimerRequestProxy(IfcNames_TimerRequestS2H);\n  timerdeviceIndication = new TimerIndication(IfcNames_TimerIndicationH2S);\n  DmaManager *dma = platformInit();\n\n  if(sem_init(&mul_sem, 1, 0)){\n    fprintf(stderr, \"failed to init mul_sem\\n\");\n    return -1;\n  }\n\n  pthread_t dbgtid;\n  fprintf(stderr, \"creating debug thread\\n\");\n  if(pthread_create(&dbgtid, NULL,  dbgThread, NULL)){\n   fprintf(stderr, \"error creating debug thread\\n\");\n   exit(1);\n  }\n\n  matAllocator = new PortalMatAllocator(dma);\n  configureSigmoidTable();\n  int rv = 0;\n\n  RBM rbm(dma);\n  rbm.run();\n\n  rbmdevice->finish();\n  exit(rv);\n}\n"
  },
  {
    "path": "examples/readbw/ReadBW.bsv",
    "content": "// Copyright (c) 2013 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\nimport FIFO::*;\nimport GetPut::*;\nimport PcieToAxiBridge::*;\nimport ConnectalMemory::*;\nimport ConnectalMMU::*;\n\ninterface CoreIndication;\n    method Action loadValue(Bit#(128) value, Bit#(32) cycles);\n    method Action storeAddress(Bit#(64) addr);\n    method Action loadMultipleLatency(Bit#(32) busWidth, Bit#(32) length, Bit#(32) count, Bit#(32) startTime, Bit#(32) endTime);\nendinterface\n\ninterface CoreRequest;\n    method Action loadMultiple(Bit#(64) addr, Bit#(32) length, Bit#(32) repetitions);\n    method Action load(Bit#(64) addr, Bit#(32) length);\n    method Action store(Bit#(64) addr, Bit#(128) value);\n\n    //method Action sglist(Bit#(32) off, Bit#(40) addr, Bit#(32) len);\n    method Action paref(Bit#(32) addr, Bit#(32) len);\nendinterface\n\ninterface ReadBWIndication;\n    interface CoreIndication coreIndication;\nendinterface\n\ninterface ReadBWRequest;\n   interface CoreRequest coreRequest;\n   interface Axi4Master#(40,128,12) m_axi;\n   interface TlpTrace trace;\nendinterface\n\ninstance ConnectalMemory#(CoreRequest);\nendinstance\ninstance ConnectalMemory#(ReadBWRequest);\nendinstance\n\nmodule mkReadBWRequest#(ReadBWIndication ind)(ReadBWRequest);\n\n    FIFO#(Bit#(40)) readAddrFifo <- mkFIFO;\n    FIFO#(Bit#(8)) readLenFifo <- mkFIFO;\n    FIFO#(Bit#(40)) writeAddrFifo <- mkFIFO;\n    FIFO#(Bit#(128)) writeDataFifo <- mkFIFO;\n    FIFO#(TimestampedTlpData) ttdFifo <- mkFIFO;\n\n    Reg#(Bit#(9)) readBurstCount <- mkReg(0);\n   FIFO#(Tuple2#(Bit#(9),Bit#(32))) readBurstCountStartTimeFifo <- mkSizedFIFO(4);\n\n   Reg#(Bit#(40)) readMultipleAddr <- mkReg(0);\n   Reg#(Bit#(8)) readMultipleLen <- mkReg(0);\n   Reg#(Bit#(8)) readMultipleCount <- mkReg(0);\n\n    Reg#(Bit#(32)) timer <- mkReg(0);\n    rule updateTimer;\n        timer <= timer + 1;\n    endrule\n\n   Reg#(Bit#(16)) addrCount <- mkReg(0);\n   rule readMultipleAddrGenerator if (addrCount > 0);\n      readAddrFifo.enq(readMultipleAddr);\n      readLenFifo.enq(readMultipleLen);\n\n      addrCount <= addrCount - 1;\n   endrule\n\n   Reg#(Bit#(32)) loadMultipleStartTime <- mkReg(0);\n   Reg#(Bit#(16)) completedCount <- mkReg(0);\n\n   FIFO#(Tuple2#(Bit#(128),Bit#(32))) readDataFifo <- mkSizedFIFO(32);\n   rule receivedData;\n      let v = readDataFifo.first;\n      readDataFifo.deq;\n      ind.coreIndication.loadValue(tpl_1(v), tpl_2(v));\n   endrule\n\n    interface CoreRequest coreRequest;\n        method Action load(Bit#(64) addr, Bit#(32) len);\n    \t    readAddrFifo.enq(truncate(addr));\n\t    readLenFifo.enq(truncate(len));\n\tendmethod: load\n        method Action loadMultiple(Bit#(64) addr, Bit#(32) len, Bit#(32) count) if (completedCount == 0);\n\t   loadMultipleStartTime <= timer;\n    \t   readMultipleAddr <= truncate(addr);\n\t   readMultipleLen <= truncate(len);\n\t   readMultipleCount <= truncate(count);\n\t   addrCount <= truncate(count);\n\t   completedCount <= truncate(count);\n\tendmethod: loadMultiple\n        method Action store(Bit#(64) addr, Bit#(128) value);\n\t    writeAddrFifo.enq(truncate(addr));\n\t    writeDataFifo.enq(value);\n\tendmethod: store\n    endinterface: coreRequest\n\n    interface Axi4Master m_axi;\n\tinterface Axi4WriteClient write;\n\t   method ActionValue#(Axi4WriteRequest#(40, 12)) address();\n\t       writeAddrFifo.deq;\n\t      ind.coreIndication.storeAddress(zeroExtend(writeAddrFifo.first));\n\t       return Axi4WriteRequest { address: writeAddrFifo.first, burstLen: 0, id: 0 };\n\t   endmethod\n\t   method ActionValue#(Axi4WriteData#(128, 16, 12)) data();\n\t       writeDataFifo.deq;\n\t       return Axi4WriteData { data: writeDataFifo.first, byteEnable: 16'hffff, last: 1, id: 0 };\n\t   endmethod\n\t   method Action response(Axi4WriteResponse#(12) r);\n\t   endmethod\n\tendinterface: write\n\tinterface Axi4ReadClient read;\n\t   method ActionValue#(Axi4ReadRequest#(40, 12)) address();\n\t       Bit#(9) numWords = zeroExtend(readLenFifo.first) + 1;\n\t       TimestampedTlpData ttd = unpack(0);\n\t       ttd.unused = 1;\n\t       Bit#(153) trace = 0;\n\t       trace[127:64] = zeroExtend(numWords);\n\t       trace[31:0] = readAddrFifo.first[31:0];\n\t       ttd.tlp = unpack(trace);\n\t       ttdFifo.enq(ttd);\n\n\t       readAddrFifo.deq;\n\t       readLenFifo.deq;\n\t       readBurstCountStartTimeFifo.enq(tuple2(numWords, timer));\n\t       return Axi4ReadRequest { address: readAddrFifo.first, burstLen: readLenFifo.first, id: 0};\n\t   endmethod\n\t   method Action data(Axi4ReadResponse#(128, 12) response);\n\n\t      let rbc = readBurstCount;\n\t      if (rbc == 0) begin\n\t\t rbc = tpl_1(readBurstCountStartTimeFifo.first);\n\t      end\n\n\t      let readStartTime = tpl_2(readBurstCountStartTimeFifo.first);\n\t      let latency = timer - readStartTime;\n\n\t      TimestampedTlpData ttd = unpack(0);\n\t      ttd.unused = 2;\n\t      Bit#(153) trace = 0;\n\t      trace[127:96] = response.data[127:96];\n\t      trace[95:64] = latency;\n\t      trace[31:0] = zeroExtend(rbc);\n\t      ttd.tlp = unpack(trace);\n\n\t      if (rbc == 1) begin\n\t\t ttdFifo.enq(ttd);\n\n\t         readDataFifo.enq(tuple2(response.data, latency));\n\t\t // this request is done, dequeue its information\n\t\t readBurstCountStartTimeFifo.deq;\n\n\t\t if (completedCount == 1)\n\t\t    ind.coreIndication.loadMultipleLatency(128, zeroExtend(readMultipleLen), zeroExtend(readMultipleCount), loadMultipleStartTime, timer);\n\n\t\t if (completedCount > 0)\n\t\t    completedCount <= completedCount - 1;\n\n\t      end\n\n\t      readBurstCount <= rbc - 1;\n\n\t   endmethod\n\tendinterface: read\n    endinterface: m_axi\n   interface TlpTrace trace;\n      interface Get tlp;\n\t  method ActionValue#(TimestampedTlpData) get();\n\t     ttdFifo.deq;\n\t     return ttdFifo.first();\n\t  endmethod\n      endinterface: tlp\n   endinterface: trace\nendmodule: mkReadBWRequest\n"
  },
  {
    "path": "examples/readbw/testreadbw.cpp",
    "content": "/* Copyright (c) 2014 Quanta Research Cambridge, Inc\n *\n * Permission is hereby granted, free of charge, to any person obtaining a\n * copy of this software and associated documentation files (the \"Software\"),\n * to deal in the Software without restriction, including without limitation\n * the rights to use, copy, modify, merge, publish, distribute, sublicense,\n * and/or sell copies of the Software, and to permit persons to whom the\n * Software is furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n * DEALINGS IN THE SOFTWARE.\n */\n#include \"ReadBW.h\"\n#include <stdio.h>\n#include <sys/mman.h>\n#include <string.h>\n#include <stdlib.h>\n#include <unistd.h>\n#include <semaphore.h>\n//#include <pthread.h>\n#include <errno.h>\n#include \"../../drivers/pcie/bluenoc.h\"\n\nCoreRequest *device = 0;\nint srcAlloc;\nunsigned int *srcBuffer = 0;\nsize_t alloc_sz = 8192;\n\nint storeCount = 0;\n\nvoid dump(const char *prefix, char *buf, size_t len)\n{\n    fprintf(stderr, \"%s \", prefix);\n    for (int i = 0; i < (len > 16 ? 16 : len) ; i++)\n\tfprintf(stderr, \"%02x\", (unsigned char)buf[i]);\n    fprintf(stderr, \"\\n\");\n}\n\n\nclass TestCoreIndication : public CoreIndication\n{\n  virtual void storeAddress ( uint64_t addr ) {\n    fprintf(stderr, \"storeAddress addr=%08llx *(long*)srcBuffer=%lx\\n\", addr, *(long*)srcBuffer);\n    if (storeCount < 16) {\n      std::bitset<128>     value128(0xD00DF00DDEADBEEFul);\n      value128 |= (std::bitset<128>(0xAAAABBBBCCCCDDDDul) << 64);\n      device->store(srcAlloc.entries[0].dma_address+storeCount*8, value128);\n      storeCount++;\n    } else {\n      device->loadMultiple(srcAlloc.entries[0].dma_address, 7, 32);\n    }\n  }\n  virtual void loadAddress ( uint64_t addr ) {\n    fprintf(stderr, \"loadAddress addr=%08llx\\n\", addr);\n  }\n  virtual void loadValue ( std::bitset<128> &value, uint32_t cycles ) {\n    if (!srcBuffer) {\n      srcBuffer = (unsigned int *)mmap(NULL, 1<<16, PROT_READ|PROT_WRITE, MAP_SHARED, device->fd, 1<<16);\n    }\n    fprintf(stderr, \"loadValue value=%08lx%08lx cycles=%ld\\n\",\n\t    ((value >> 64) & std::bitset<128>(0xFFFFFFFFFFFFFFFFul)).to_ulong(),\n\t    (value & std::bitset<128>(0xFFFFFFFFFFFFFFFFul)).to_ulong(),\n\t    cycles);\n    fprintf(stderr, \"srcBuffer[0] = %08lx\\n\", *(long *)srcBuffer);\n  }\n  virtual void loadMultipleLatency ( uint32_t busWidth, uint32_t beatsPerRead, uint32_t numReads,\n\t\t\t\t     uint32_t startTime, uint32_t endTime )\n  {\n    uint32_t numBytes = beatsPerRead * numReads * busWidth / 8;\n    uint32_t numCycles = endTime - startTime;\n    double numMicroSeconds = numCycles / 125.0;\n    double megabytesPerSecond = numBytes / numMicroSeconds;\n\n    fprintf(stderr, \"loadMultiple  %ld bytes latency=%ld cycles %f us %f MB/s\\n\",\n\t    numBytes, numCycles, numMicroSeconds, megabytesPerSecond);\n  }\n\n};\n\nclass TestCoreRequest : public CoreRequest\n{\npublic:\n\n  virtual void sglist(uint32_t off, uint64_t addr, uint32_t len) {\n  }\n\n  virtual void paref(uint32_t off, uint32_t ref, uint32_t foo) {\n  }\n\n  static TestCoreRequest *createTestCoreRequest(CoreIndication *indication) {\n    const char *instanceName = \"fpga0\"; \n    TestCoreRequest *instance = new TestCoreRequest(instanceName, indication);\n    return instance;\n  }\n\nprotected:\n  TestCoreRequest(const char *instanceName, CoreIndication *indication)\n    : CoreRequest(instanceName, indication)\n  {\n  }\n\n  ~TestCoreRequest() {}\n};\n\nint main(int argc, const char **argv)\n{\n  unsigned int srcGen = 0;\n\n  fprintf(stderr, \"%s %s\\n\", __DATE__, __TIME__);\n  device = TestCoreRequest::createTestCoreRequest(new TestCoreIndication);\n\n  fprintf(stderr, \"allocating memory...\\n\");\n\n  memset(&srcAlloc, 0, sizeof(srcAlloc));\n\n\n  // use PortalAlloc\n  if (1) {\n    int rc = 0;\n    srcAlloc = device->alloc(alloc_sz);\n    fprintf(stderr, \"alloc rc=%d fd=%d\\n\", rc, srcAlloc);\n\n    srcBuffer = (unsigned int *)device->mmap(&srcAlloc);\n\n    fprintf(stderr, \"srcBuffer=%p\\n\", srcBuffer);\n    memset(srcBuffer, 0xba, alloc_sz);\n    fprintf(stderr, \"srcBuffer[0]=%x\\n\", srcBuffer[0]);\n\n    // flush cache not needed on x86\n#ifdef __arm__\n    rc = device->dCacheFlushInval(srcAlloc, alloc_sz, srcBuffer);\n    fprintf(stderr, \"cache flushed rc=%d\\n\", rc);\n#endif\n    // map the Dma buf into PCIe. Seems not to be needed.\n    //rc = ioctl(device->fd, BNOC_DMA_BUF_MAP, srcAlloc.header.fd);\n    //fprintf(stderr, \"BNOC_DMA_BUF_MAP rc=%d errno=%d\\n\", rc, errno);\n\n  } else {\n    // use bluenoc driver to allocate memory coherent with PCIe\n    tDmaMap dmaMap;\n    srcBuffer = (unsigned int *)mmap(NULL, 1<<16, PROT_READ|PROT_WRITE, MAP_SHARED, device->fd, 1<<16);\n    int rc = ioctl(device->fd, BNOC_DMA_MAP, &dmaMap);\n    fprintf(stderr, \"BNOC_PCI_ALLOC rc=%d errno=%d\\n\", rc, errno);\n    fprintf(stderr, \"srcBuffer=%p virt=%p dma_handle=%lx\\n\", srcBuffer, dmaMap.virt, dmaMap.dma_handle);\n\n    srcAlloc.entries[0].dma_address = dmaMap.dma_handle;\n    memset(srcBuffer, 0xda, 8192);\n  }\n\n  std::bitset<128>     value128(0xD00DF00DDEADBEEFul);\n  value128 |= (std::bitset<128>(0xAAAABBBBCCCCDDDDul) << 64);\n  device->store(srcAlloc.entries[0].dma_address, value128);\n  //device->loadMultiple(srcAlloc.entries[0].dma_address, 3, 1);\n  portalExec(0);\n\n}\n"
  },
  {
    "path": "examples/regexp/Makefile",
    "content": "CONNECTALDIR?=../..\nS2H_INTERFACES = RegexpRequest:Regexp.request\nH2S_INTERFACES = Regexp\\#\\(64\\):RegexpIndication\nMEM_READ_INTERFACES = \"append(lRegexp.config_read_client,lRegexp.haystack_read_client)\"\n\nBSVFILES = $(CONNECTALDIR)/lib/regexp/bsv/Regexp.bsv\nCPPFILES=testregexp.cpp\nCONNECTALFLAGS = -D DEGPAR=4 -D MAX_NUM_STATES=32 -D MAX_NUM_CHARS=32 \nCONNECTALFLAGS += --stl=gnustl_static\nRUN_ARGS = test.bin\nCONNECTALFLAGS += -I$(CONNECTALDIR)/lib/regexp/cpp\nCONNECTALFLAGS += --run-args=\"$(addprefix $(PWD)/, jregexp.charMap jregexp.stateMap jregexp.stateTransitions test.bin)\"\ninclude $(CONNECTALDIR)/Makefile.connectal\n"
  },
  {
    "path": "examples/regexp/testregexp.cpp",
    "content": "/* Copyright (c) 2013 Quanta Research Cambridge, Inc\n *\n * Permission is hereby granted, free of charge, to any person obtaining a\n * copy of this software and associated documentation files (the \"Software\"),\n * to deal in the Software without restriction, including without limitation\n * the rights to use, copy, modify, merge, publish, distribute, sublicense,\n * and/or sell copies of the Software, and to permit persons to whom the\n * Software is furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n * DEALINGS IN THE SOFTWARE.\n */\n#include <assert.h>\n//#include <iostream>\n//#include <fstream>\n//#include <sys/stat.h>\n#include \"dmaManager.h\"\n#include \"RegexpIndication.h\"\n#include \"RegexpRequest.h\"\n#include \"regexp_utils.h\"\n\nint main(int argc, const char **argv)\n{\n  fprintf(stderr, \"%s %s\\n\", __DATE__, __TIME__);\n  const char *charMapFilename = \"../jregexp.charMap\";\n  const char *stateMapFilename = \"../jregexp.stateMap\";\n  const char *stateTransitionsFilename = \"../jregexp.stateTransitions\";\n  const char *testFilename = \"../test.bin\";\n  if (argc >= 4) {\n    charMapFilename = argv[1];\n    stateMapFilename = argv[2];\n    stateTransitionsFilename = argv[3];\n    testFilename = argv[4];\n  }\n  fprintf(stderr, \"Using charMap %s stateMap %s stateTransitions %s test %s\\n\",\n\t  charMapFilename, stateMapFilename, stateTransitionsFilename, testFilename);\n\n  RegexpRequestProxy *device = new RegexpRequestProxy(IfcNames_RegexpRequestS2H);\n  DmaManager *hostDma = platformInit();\n  RegexpIndication *deviceIndication = new RegexpIndication(IfcNames_RegexpIndicationH2S);\n  \n  haystack_dma = hostDma;\n  //haystack_mmu = hostMMURequest;\n  regexp = device;\n\n  if(sem_init(&test_sem, 1, 0)){\n    fprintf(stderr, \"failed to init test_sem\\n\");\n    return -1;\n  }\n\n  // this is hard-coded into the REParser.java\n  assert(32 == MAX_NUM_STATES);\n  assert(32 == MAX_NUM_CHARS);\n\n  if(1){\n    P charMapP;\n    P stateMapP;\n    P stateTransitionsP;\n    \n    readfile(charMapFilename, &charMapP);\n    readfile(stateMapFilename, &stateMapP);\n    readfile(stateTransitionsFilename, &stateTransitionsP);\n\n    portalCacheFlush(charMapP.alloc, charMapP.mem, charMapP.length, 1);\n    portalCacheFlush(stateMapP.alloc, stateMapP.mem, stateMapP.length, 1);\n    portalCacheFlush(stateTransitionsP.alloc, stateTransitionsP.mem, stateTransitionsP.length, 1);\n\n    for(int i = 0; i < num_tests; i++){\n      device->setup(charMapP.ref, charMapP.length);\n      device->setup(stateMapP.ref, stateMapP.length);\n      device->setup(stateTransitionsP.ref, stateTransitionsP.length);\n\n      readfile(testFilename, &haystackP[i]);\n      portalCacheFlush(haystackP[i].alloc, haystackP[i].mem, haystackP[i].length, 1);\n\n      if(i==0)\n\tsw_match_cnt = num_tests*sw_ref(&haystackP[0], &charMapP, &stateMapP, &stateTransitionsP);\n\n      sem_wait(&test_sem);\n      int token = deviceIndication->token;\n\n      assert(token < max_num_tokens);\n      token_map[token] = i;\n      // Regexp uses a data-bus width of 8 bytes.  length must be a multiple of this dimension\n      device->search(token, haystackP[i].ref, haystackP[i].length & ~((1<<3)-1));\n    }\n\n    sem_wait(&test_sem);\n    close(charMapP.alloc);\n    close(stateMapP.alloc);\n    close(stateTransitionsP.alloc);\n  }\n  fprintf(stderr, \" testregexp: Done, hw_match_cnt=%d, sw_match_cnt=%d\\n\", hw_match_cnt, sw_match_cnt);\n  sleep(1);\n  return (hw_match_cnt == sw_match_cnt ? 0 : -1);\n}\n"
  },
  {
    "path": "examples/sdcard_spi/Makefile",
    "content": "\nCONNECTALDIR?=../..\n\nBSVFILES = SPITest.bsv\nCPPFILES = sdcard_spi.cpp\n\nS2H_INTERFACES = SPIRequest:SPITest.spiRequest\nH2S_INTERFACES = SPITest:SPIIndication\nMEM_READ_INTERFACES =\nMEM_WRITE_INTERFACES =\n\nPINOUT_FILE += pin_translation.json\nPIN_TYPE = SPIMasterPins\nPIN_TYPE_INCLUDE = SPI\nAUTOTOP = --interface pins:SPITest.spiMasterPins\n\ninclude $(CONNECTALDIR)/Makefile.connectal\n\n"
  },
  {
    "path": "examples/sdcard_spi/SPI.bsv",
    "content": "// This is a simple SPI Master module.\n// This has only been tested with cpol == 0 and cpha == 0\n\n// For information about SPI, check wikipedia:\n//   https://en.wikipedia.org/wiki/Serial_Peripheral_Interface_Bus\n\n(* always_ready, always_enabled *)\ninterface SPIMasterPins;\n    // serial clock\n    (* prefix = \"\", result = \"spi_sclk\" *)\n    method Bit#(1) sclk;\n    // master-out slave-in\n    (* prefix = \"\", result = \"spi_mosi\" *)\n    method Bit#(1) mosi;\n    // master-in slave-out\n    (* prefix = \"\" *)\n    method Action miso((* port = \"spi_miso\" *)Bit#(1) x);\n    // active-low chip select\n    (* prefix = \"\", result = \"spi_ncs\" *)\n    method Bit#(1) ncs;\n    interface Clock deleteme_unused_clock;\nendinterface\n\ninterface SPIMaster;\n    // configuration\n    method Action setSclkDiv(Bit#(16) d);\n    method Action setNcs(Bit#(1) new_ncs);\n    // Warning: mkSPIMaster untested for cpol == 1\n    method Action setCpol(Bit#(1) new_cpol); // idle value of clock\n    // Warning: mkSPIMaster untesetd for cpha == 1\n    method Action setCpha(Bit#(1) new_cpha); // which clock transition captures data\n                                             // cpha = 0 => odd transitions (1st, 3rd, etc.)\n                                             // cpha = 1 => even transitions (2nd, 4th, etc.)\n    // status\n    method Bool isChipSelectEnabled();\n    // data\n    method Action put(Bit#(8) x);\n    method ActionValue#(Bit#(8)) get();\n    // pins\n    (* prefix = \"\" *)\n    interface SPIMasterPins pins;\nendinterface\n\nmodule mkSPIMaster(SPIMaster);\n    let clock <- exposeCurrentClock();\n    // registers for the interface pins\n    Reg#(Bit#(1)) sclkReg <- mkReg(0);\n    Reg#(Bit#(16)) sclkDiv <- mkReg(1);\n    Wire#(Bit#(1)) misoWire <- mkDWire(0);\n    Reg#(Bit#(1)) misoReg <- mkReg(0);\n    Reg#(Bit#(1)) ncsReg <- mkReg(1);\n    // MSB gets shifted out\n    Reg#(Bit#(8)) shiftReg <- mkReg(0);\n\n    // SPI configuration\n    Reg#(Bit#(1)) cpol <- mkReg(0);\n    Reg#(Bit#(1)) cpha <- mkReg(0);\n\n    // 17 ticks per SPI cycle, between each tick is a clock transition\n    Reg#(Bool) running <- mkReg(False);\n    Reg#(Bool) resultReady <- mkReg(False);\n    Reg#(Bit#(5)) tickCount <- mkReg(0);\n    // sclkReg determines how many mini ticks make up a tick\n    Reg#(Bit#(16)) miniTickCount <- mkReg(0);\n\n    (* fire_when_enabled, no_implicit_conditions *)\n    rule run(running);\n        let nextMiniTickCount = miniTickCount + 1;\n        if ((nextMiniTickCount == sclkDiv) || sclkDiv == 0) begin\n            miniTickCount <= 0;\n            if (tickCount == 16) begin\n                // done\n                running <= False;\n                resultReady <= True;\n                tickCount <= 0;\n            end else begin\n                // tick clock\n                sclkReg <= ~sclkReg;\n                // increment tickCount\n                tickCount <= tickCount + 1;\n                // either capture input or shift output\n                if (tickCount[0] == cpha) begin\n                    // capture input\n                    misoReg <= misoWire;\n                end else begin\n                    // shift output\n                    if (tickCount == 0) begin\n                        // but never on the first tick\n                    end else begin\n                        shiftReg <= {shiftReg[6:0], misoReg};\n                    end\n                end\n            end\n        end else begin\n            miniTickCount <= nextMiniTickCount;\n        end\n    endrule\n\n    method Action setSclkDiv(Bit#(16) d) if (ncsReg == 1);\n        sclkDiv <= d;\n    endmethod\n    method Action setNcs(Bit#(1) new_ncs);\n        ncsReg <= new_ncs;\n    endmethod\n    method Action setCpol(Bit#(1) new_cpol) if (ncsReg == 1);\n        cpol <= new_cpol;\n    endmethod\n    method Action setCpha(Bit#(1) new_cpha) if (ncsReg == 1);\n        cpha <= new_cpha;\n    endmethod\n\n    method Bool isChipSelectEnabled();\n        return ncsReg == 0;\n    endmethod\n\n    method Action put(Bit#(8) x) if (!running);\n        resultReady <= False;\n        running <= True;\n        tickCount <= 0;\n        miniTickCount <= 0;\n        shiftReg <= x;\n    endmethod\n    method ActionValue#(Bit#(8)) get() if (resultReady);\n        resultReady <= False;\n        return shiftReg;\n    endmethod\n\n    interface SPIMasterPins pins;\n        method Bit#(1) sclk;\n            return sclkReg;\n        endmethod\n        method Bit#(1) mosi;\n            return running ? shiftReg[7] : 1;\n        endmethod\n        method Action miso(Bit#(1) x);\n            misoWire <= x;\n        endmethod\n        method Bit#(1) ncs;\n            return ncsReg;\n        endmethod\n        interface Clock deleteme_unused_clock = clock;\n    endinterface\nendmodule\n"
  },
  {
    "path": "examples/sdcard_spi/SPITest.bsv",
    "content": "import SPI::*;\n\ninterface SPITest;\n    interface SPIRequest spiRequest;\n    (* prefix = \"\" *)\n    interface SPIMasterPins spiMasterPins;\nendinterface\n\ninterface SPIRequest;\n    method Action setSclkDiv(Bit#(16) d);\n    method Action setNcs(Bit#(1) x);\n    method Action put(Bit#(8) x);\nendinterface\n\ninterface SPIIndication;\n    method Action get(Bit#(8) x);\nendinterface\n\nmodule mkSPITest#(SPIIndication spiIndication)(SPITest);\n    SPIMaster spi <- mkSPIMaster;\n    Reg#(Bool) init <- mkReg(False);\n    Reg#(Bool) active <- mkReg(False);\n    Bool verbose = False;\n\n    rule doInit(!init);\n        spi.setNcs(1);\n        spi.setCpol(0);\n        spi.setCpha(0);\n        spi.setSclkDiv(2);\n        init <= True;\n    endrule\n\n    rule doComplete;\n        active <= False;\n        let x <- spi.get;\n        spiIndication.get(x);\n        if (verbose) $display(\"get: \", fshow(x));\n    endrule\n\n    rule doDisplay(active);\n        let sclk = spi.pins.sclk;\n        let mosi = spi.pins.mosi;\n        if (verbose) $display(\"sclk: %0d, mosi: %0d\", sclk, mosi);\n    endrule\n\n    interface SPIRequest spiRequest;\n        method Action setSclkDiv(Bit#(16) d);\n            spi.setSclkDiv(d);\n        endmethod\n        method Action setNcs(Bit#(1) x);\n            spi.setNcs(x);\n        endmethod\n        method Action put(Bit#(8) x);\n            if (verbose) $display(\"put: \", fshow(x));\n            active <= True;\n            spi.put(x);\n        endmethod\n    endinterface\n\n    interface SPIMasterPins spiMasterPins = spi.pins;\nendmodule\n"
  },
  {
    "path": "examples/sdcard_spi/pin_translation.json",
    "content": "{\n    \"spi_sclk\": {\n        \"PIO_DIRECTION\": \"OUTPUT\",\n        \"sdio\": \"clk\"\n    },\n    \"spi_mosi\": {\n        \"PIO_DIRECTION\": \"OUTPUT\",\n        \"sdio\": \"cmd\"\n    },\n    \"spi_miso\": {\n        \"PIO_DIRECTION\": \"INPUT\",\n        \"sdio\": \"dat0\"\n    },\n    \"spi_ncs\": {\n        \"PIO_DIRECTION\": \"OUTPUT\",\n        \"sdio\": \"cd_dat3\"\n    }\n}\n"
  },
  {
    "path": "examples/sdcard_spi/readme.txt",
    "content": "sdcard_spi example\n------------------\n\nThis example uses SPI mode on an SD card to read the first block of data.\nThis example was initially designed for the kc705g2 FPGA platform using an\n8 GB SDHC card. Due to differences in initialization, this will not work on\nolder, smaller SD cards, and it may not work on larger, newer SD* cards.\n\nThe mkSPIMaster module in SPI.bsv has not been well tested. Currently this\nexample is the only time it has been used. You may find bugs if you try to\nuse it in a different situation (especially if SPI mode isn't 0).\n\n"
  },
  {
    "path": "examples/sdcard_spi/sdcard_spi.cpp",
    "content": "#include <semaphore.h>\n#include <iostream>\n#include <iomanip>\n\n#include \"SPIIndication.h\"\n#include \"SPIRequest.h\"\n#include \"GeneratedTypes.h\"\n#include \"portal.h\"\n\n// x is {2'b01, cmd, arg}\nuint8_t getCRC7(uint64_t x) {\n    uint8_t crc = 0;\n    \n    for (int i = 39 ; i >= 0 ; i--) {\n        if (((crc >> 6) ^ (x >> i)) & 1) {\n            crc = (0x7F & (crc << 1)) ^ 0x09;\n        } else {\n            crc = 0x7F & (crc << 1);\n        }\n    }\n\n    return crc;\n}\n\nvoid printR1Resp( uint8_t resp ) {\n    std::cout << \"R1 Resp:\";\n    if (resp != 0) {\n        if (resp & (1 << 7)) std::cout << \" ERROR_first_bit_not_zero\";\n        if (resp & (1 << 6)) std::cout << \" parameter_error\";\n        if (resp & (1 << 5)) std::cout << \" address_error\";\n        if (resp & (1 << 4)) std::cout << \" erase_sequence_error\";\n        if (resp & (1 << 3)) std::cout << \" com_crc_error\";\n        if (resp & (1 << 2)) std::cout << \" illegal_command\";\n        if (resp & (1 << 1)) std::cout << \" erase_reset\";\n        if (resp & (1 << 0)) std::cout << \" in_idle_state\";\n    } else {\n        std::cout << \" (all zero)\";\n    }\n    std::cout << std::endl;\n}\n\nclass SPI : public SPIIndicationWrapper {\n    private:\n        SPIRequestProxy spiRequest;\n        sem_t sem;\n        uint8_t data;\n\n    public:\n        SPI(unsigned int indicationId, unsigned int requestId)\n                : SPIIndicationWrapper(indicationId),\n                  spiRequest(requestId)\n        {\n            sem_init(&sem, 1, 0);\n        }\n\n        void setSclkDiv(uint16_t x) {\n            spiRequest.setSclkDiv(x);\n        }\n\n        void enableChip(bool x) {\n            // ncs is active-low, so true => 0 and false => 1\n            if (x) {\n                spiRequest.setNcs(0);\n            } else {\n                spiRequest.setNcs(1);\n            }\n        }\n\n        uint8_t req(uint8_t x) {\n            spiRequest.put(x);\n            sem_wait(&sem);\n            return data;\n        }\n\n        void get(uint8_t x) {\n            data = x;\n            sem_post(&sem);\n        }\n};\n\nclass SD_SPIMode {\n    private:\n        SPI *spi;\n        bool verbose;\n\n        static const int cmd_resp_no_resp_flag = 0x200; // set if SD card never sent a valid response\n        static const int cmd_resp_error_flag   = 0x100; // set if there is a critical error in the response\n        static const int cmd_resp_crc_error    = 0x008;\n        static const int cmd_resp_illegal_cmd  = 0x004;\n\n    public:\n        SD_SPIMode(SPI* myspi) {\n            spi = myspi;\n            verbose = true;\n        }\n\n        // If this returns a value greater than 0xFF, then any further response\n        // bytes will not be sent.\n        int sendSDReq(uint8_t cmdIndx, uint32_t arg) {\n            // This extra request is needed for some reason. This is not part\n            // of the actual command.\n            spi->req(0xFF);\n\n            // Calculate crc\n            uint64_t crc_in = 0x4000000000ull;\n            crc_in = crc_in | ((0x3F & ((uint64_t) cmdIndx)) << 32) | ((uint64_t) arg);\n            uint8_t crc = getCRC7(crc_in);\n\n            // Send command\n            if (verbose) std::cout << \"Sending CMD\" << std::dec << (int) cmdIndx << \" with argument 0x\" << std::hex << arg << std::endl;\n            spi->req(0x40 | (0x3F & cmdIndx));\n            spi->req(0xFF & (arg >> (3*8)));\n            spi->req(0xFF & (arg >> (2*8)));\n            spi->req(0xFF & (arg >> (1*8)));\n            spi->req(0xFF & arg);\n            spi->req(0x01 | ((0x7F & crc) << 1));\n\n            // Get initial R1 response\n            int resp;\n            for (int i = 0 ; i <= 8 ; i++) {\n                resp = (int) spi->req(0xFF);\n                if ((resp & 0x80) == 0) {\n                    // This is a valid response\n                    if (resp & cmd_resp_illegal_cmd) {\n                        std::cerr << \"ERROR: CMD\" << std::dec << (int) cmdIndx << \" is not supported by this SD card\" << std::endl;\n                        // Set error flag\n                        resp |= cmd_resp_error_flag;\n                    }\n                    if (resp & cmd_resp_crc_error) {\n                        std::cerr << \"ERROR: sendSDReq() for CMD\" << std::dec << (int) cmdIndx << \" had a CRC error\" << std::endl;\n                        // Set error flag\n                        resp |= cmd_resp_error_flag;\n                    }\n                    return resp;\n                }\n            }\n            std::cerr << \"ERROR: sendSDReq() for CMD\" << std::dec << (int) cmdIndx << \" failed to get an R1 response after 9 tries\" << std::endl;\n            return cmd_resp_no_resp_flag;\n        }\n\n        uint8_t getByteResp() {\n            return spi->req(0xFF);\n        }\n\n        uint32_t getWordResp() {\n            uint32_t resp = (0xFF & ((uint32_t) spi->req(0xFF))) << (8*3);\n            resp = resp | (0xFF & ((uint32_t) spi->req(0xFF))) << (8*2);\n            resp = resp | (0xFF & ((uint32_t) spi->req(0xFF))) << (8*1);\n            resp = resp | (0xFF & ((uint32_t) spi->req(0xFF)));\n            return resp;\n        }\n\n        // This follows the SDHC portion of figure 7-2 in the Physical Layer\n        // Specification Version 5.00\n        bool init(uint16_t d) {\n            spi->enableChip(false);\n            spi->setSclkDiv(d);\n            usleep(100000);\n            spi->enableChip(true);\n            usleep(100000);\n\n            for (int i = 0 ; i < 10 ; i++) {\n                spi->req(0xFF);\n            }\n\n            // CMD0\n            if (verbose) std::cout << \"init(): sending CMD0\" << std::endl;\n            int resp = sendSDReq(0, 0);\n            if (resp > 0xFF) {\n                return false;\n            }\n            if (resp != 1) {\n                std::cerr << \"ERROR: Unexpected R1 response from CMD0 during init()\" << std::endl;\n                printR1Resp(resp);\n                return false;\n            }\n\n            // CMD8 - specifying 2.7-2.6 V and using 0x5B as the check pattern\n            if (verbose) std::cout << \"init(): sending CMD8\" << std::endl;\n            uint8_t echo_back = 0x5B;\n            resp = sendSDReq(8, 0x100 | ((uint32_t) echo_back));\n            if (resp > 0xFF) {\n                if (resp & cmd_resp_illegal_cmd) {\n                    std::cerr << \"INFO: CMD8 is not supported by this SD card (SD card Ver 1.X)\" << std::endl;\n                    std::cerr << \"ERROR: This code does not support SD card Ver 1.X\" << std::endl;\n                    printR1Resp(0xFF & resp);\n                }\n                return false;\n            }\n            uint32_t r7 = getWordResp();\n            if (r7 != (0x100 | ((uint32_t) echo_back))) {\n                std::cerr << \"ERROR: CMD8 echo failed. r7 = \" << std::hex << r7 << std::endl;\n                return false;\n            }\n\n            // CMD58 (optional) - read OCR\n            if (verbose) std::cout << \"init(): sending CMD58\" << std::endl;\n            resp = sendSDReq(58, 0);\n            if (resp > 0xFF) {\n                return false;\n            }\n            uint32_t ocr = getWordResp();\n            bool ccs = (bool) (ocr & (1ull << 30));\n            bool ready = (bool) (ocr & (1ull << 31));\n            if (verbose) {\n                std::cout << \"OCR: 0x\" << std::hex << ocr << std::dec << std::endl;\n                std::cout << \"ccs: \" << (ccs ? \"yes\" : \"no\") << std::endl;\n                std::cout << \"ready: \" << (ready ? \"yes\" : \"no\") << std::endl;\n            }\n\n            // CMD55 -> ACMD41\n            if (verbose) std::cout << \"init(): sending CMD55 and ACMD41\" << std::endl;\n            do {\n                resp = sendSDReq(55, 0);\n                if (resp > 0xFF) {\n                    return false;\n                }\n                resp = sendSDReq(41, 0x1u << 30); // HCS = 1\n                if (resp > 0xFF) {\n                    return false;\n                }\n                usleep(1000);\n            } while (resp == 1);\n\n            // CMD58 - read OCR (again)\n            if (verbose) std::cout << \"init(): sending CMD58\" << std::endl;\n            resp = sendSDReq(58, 0);\n            if (resp > 0xFF) {\n                return false;\n            }\n            ocr = getWordResp();\n            ccs = (bool) (ocr & (1ull << 30));\n            ready = (bool) (ocr & (1ull << 31));\n            if (verbose) {\n                std::cout << \"OCR: 0x\" << std::hex << ocr << std::dec << std::endl;\n                std::cout << \"ccs: \" << (ccs ? \"yes\" : \"no\") << std::endl;\n                std::cout << \"ready: \" << (ready ? \"yes\" : \"no\") << std::endl;\n            }\n\n            if (!ready) {\n                std::cerr << \"ERROR: ready bit in OCR is not set\" << std::endl;\n                return false;\n            }\n            if (!ccs) {\n                std::cerr << \"INFO: ccs bit in OCR is not set.\" << std::endl;\n                std::cerr << \"ERROR: This code does not suport normal SD cards at the moment\" << std::endl;\n                return false;\n            }\n\n            if (verbose) {\n                std::cout << \"init(): made it to the end without failing\" << std::endl;\n            }\n            return true;\n        }\n\n        // The block is 512 bytes\n        bool readBlock(uint32_t blockAddr, void* data) {\n            uint8_t resp = sendSDReq(17, blockAddr);\n            if (resp > 0xFF) {\n                std::cerr << \"ERROR: readBlock failed\" << std::endl;\n                return false;\n            }\n            if (resp != 0) {\n                printR1Resp(0xFF & resp);\n            }\n\n            uint8_t byte = 0;\n            do {\n                byte = spi->req(0xFF);\n            } while (byte == 0xFF);\n\n            // the first byte of the data response should be 0xFE\n            if (byte != 0xFE) {\n                std::cerr << \"ERROR: Unexpected start of write block. resp = 0x\" << std::hex << (int) resp << std::endl;\n                return false;\n            }\n\n            uint8_t *dataChar = (uint8_t*) data;\n            for (int i = 0 ; i < 512 ; i++) {\n                dataChar[i] = spi->req(0xFF);\n            }\n            // Ignore the 16-bit CRC for now\n            spi->req(0xFF);\n            spi->req(0xFF);\n            // Read was successful\n            return true;\n        } \n};\n\nint main(int argc, char* argv[]) {\n    simulator_dump_vcd = 1;\n\n    SPI spi(IfcNames_SPIIndicationH2S, IfcNames_SPIRequestS2H);\n\n    SD_SPIMode sd(&spi);\n\n    // 2500 is the argument for setSclkDiv\n    if (!sd.init(2500)) {\n        std::cerr << \"ERROR: sd.init() failed\" << std::endl;\n        return -1;\n    } else {\n        std::cout << \"sd.init() successful\" << std::endl;\n    }\n\n    // much faster clock\n    spi.setSclkDiv(2);\n\n    uint8_t data[512];\n    std::cout << \"reading block 0\" << std::endl;\n    sd.readBlock(0, (void*) data);\n\n    std::cout << \"printing block 0\" << std::endl;\n    for (int i = 0 ; i < 512 ; i++) {\n        if (((i % 16) == 0) && (i != 0)) {\n            std::cout << std::endl;\n        } else if (((i % 2) == 0) && (i != 0)) {\n            std::cout << \" \";\n        }\n        std::cout << std::setfill('0') << std::setw(2) << std::hex << (int) data[i];\n    }\n    std::cout << std::endl;\n\n    return 0;\n}\n"
  },
  {
    "path": "examples/simple/Makefile",
    "content": "CONNECTALDIR?=../..\nS2H_INTERFACES = SimpleRequest:Simple.request\nH2S_INTERFACES = Simple:SimpleRequest\n\nBSVFILES = Simple.bsv\nCPPFILES = testsimple.cpp\n\nifeq ($(BOARD), $(filter $(BOARD), de5 htg4))\nPIN_BINDINGS?=PCIE:PCIE LED:LED OSC:OSC\nendif\n\ninclude $(CONNECTALDIR)/Makefile.connectal\n"
  },
  {
    "path": "examples/simple/Simple.bsv",
    "content": "\n// Copyright (c) 2013 Nokia, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\nimport FIFO::*;\nimport Vector::*;\n\ntypedef struct{\n   Bit#(32) a;\n   Bit#(32) b;\n   } S1 deriving (Bits);\n\ntypedef struct{\n   Bit#(32) a;\n   Bit#(16) b;\n   Bit#(7) c;\n   } S2 deriving (Bits);\n\ntypedef enum {\n   E1Choice1,\n   E1Choice2,\n   E1Choice3,\n   E1ChoiceBig = 33554432,\n   E1ChoiceBig2 = 33554433\n   } E1 deriving (Bits,Eq);\n\ntypedef struct{\n   Bit#(32) a;\n   E1 e1;\n   } S3 deriving (Bits);\n\ntypedef Bit#(24) Address;\ntypedef Bit#(32) Intptr;\ntypedef Bit#(8) Byte;\n\ninterface SimpleRequest;\n    method Action say1(Bit#(32) v);\n    method Action say2(Bit#(16) a, Bit#(16) b);\n    method Action say3(S1 v);\n    method Action say4(S2 v);\n    method Action say5(Bit#(32)a, Bit#(64) b, Bit#(32) c);\n    method Action say6(Bit#(32)a, Bit#(40) b, Bit#(32) c);\n    method Action say7(S3 v);\n    method Action say8(Vector#(128, Bit#(32)) v);\n    method Action say9(E1 v, E1 w);\n    method Action sayv1 (Vector#(4, Int#(32)) arg1, Vector#(4, Int#(32)) arg2);\n    method Action sayv2 (Vector#(16, Int#(16)) v);\n    method Action sayv3 (Vector#(16, Int#(16)) v, Int#(16) count);\n    method Action saypixels(Vector#(2, Bit#(32)) xs, Vector#(2, Bit#(32)) ys, Vector#(2, Bit#(32)) zs);\n    method Action reftest1(Address dst, Intptr dst_stride,\n              Address src1, Intptr i_src_stride1,\n              Address src2, Intptr i_src_stride2,\n              Byte i_width, Byte i_height, Bool qpelInt,\n              Bool hasWeight, Byte i_offset, Byte i_scale, Byte i_denom);\nendinterface\n\ntypedef struct {\n    Bit#(32) a;\n    Bit#(40) b;\n    Bit#(32) c;\n} Say6ReqSimple deriving (Bits);\n\ninterface Simple;\n    interface SimpleRequest request;\nendinterface\n\nmodule mkSimple#(SimpleRequest indication)(Simple);\n   let verbose = False;\n\n   interface SimpleRequest request;\n   method Action say1(Bit#(32) v);\n      if (verbose) $display(\"mkSimple::say1\");\n      indication.say1(v);\n   endmethod\n\n   method Action say2(Bit#(16) a, Bit#(16) b);\n      if (verbose) $display(\"mkSimple::say2\");\n      indication.say2(a,b);\n   endmethod\n\n   method Action say3(S1 v);\n      if (verbose) $display(\"mkSimple::say3\");\n      indication.say3(v);\n   endmethod\n\n   method Action say4(S2 v);\n      if (verbose) $display(\"mkSimple::say4\");\n      indication.say4(v);\n   endmethod\n\n   method Action say5(Bit#(32) a, Bit#(64) b, Bit#(32) c);\n      if (verbose) $display(\"mkSimple::say5\");\n      indication.say5(a, b, c);\n   endmethod\n\n   method Action say6(Bit#(32) a, Bit#(40) b, Bit#(32) c);\n      if (verbose) $display(\"mkSimple::say6\");\n      indication.say6(a, b, c);\n   endmethod\n\n   method Action say7(S3 v);\n      if (verbose) $display(\"mkSimple::say7\");\n      indication.say7(v);\n   endmethod\n\n   method Action say8(Vector#(128, Bit#(32)) v);\n      if (verbose) $display(\"mkSimple::say8\");\n      indication.say8(v);\n   endmethod\n\n   method Action say9(E1 v, E1 w);\n      if (verbose) $display(\"mkSimple::say9\", v, w);\n      indication.say9(v, w);\n   endmethod\n\n   method Action sayv1 (Vector#(4, Int#(32)) arg1, Vector#(4, Int#(32)) arg2);\n      if (verbose) $display(\"mkSimple::sayv1\");\n      indication.sayv1(arg1, arg2);\n   endmethod\n   method Action sayv2 (Vector#(16, Int#(16)) v);\n      if (verbose) $display(\"mkSimple::sayv2\");\n      indication.sayv2(v);\n   endmethod\n   method Action sayv3 (Vector#(16, Int#(16)) v, Int#(16) count);\n      if (verbose) $display(\"mkSimple::sayv3\");\n      indication.sayv3(v, count);\n   endmethod\n    method Action saypixels(Vector#(2, Bit#(32)) xs, Vector#(2, Bit#(32)) ys, Vector#(2, Bit#(32)) zs);\n      if (verbose) $display(\"mkSimple::saypixels\");\n      indication.saypixels(xs, ys, zs);\n   endmethod\n   method Action reftest1(Address dst, Intptr dst_stride,\n            Address src1, Intptr i_src_stride1,\n              Address src2, Intptr i_src_stride2,\n              Byte i_width, Byte i_height, Bool qpelInt,\n              Bool hasWeight, Byte i_offset, Byte i_scale, Byte i_denom);\n      //if (verbose) \n      $display(\"mkSimple::reftest1 dst %x dst_stride %x src1 %x i_src_stride1 %x src2 %x i_src_stride2 %x i_width %x i_height %x qpelInt %x hasWeight %x i_offset %x i_scale %x i_denom %x\\n\",\n          dst, dst_stride, src1, i_src_stride1, src2, i_src_stride2, i_width, i_height, qpelInt, hasWeight, i_offset, i_scale, i_denom);\n      indication.reftest1(dst, dst_stride, src1, i_src_stride1, src2, i_src_stride2, i_width, i_height, qpelInt, hasWeight, i_offset, i_scale, i_denom);\n   endmethod\n   endinterface\nendmodule\n"
  },
  {
    "path": "examples/simple/boards/de5.json",
    "content": "{\n    \"PCIE_tx_p[0]\": {\n\t\"PIO_DIRECTION\": \"OUTPUT\",\n\t\"PCIE\": \"PCIE_TX_p[0]\"\n    },\n    \"PCIE_tx_p[1]\": {\n\t\"PIO_DIRECTION\": \"OUTPUT\",\n\t\"PCIE\": \"PCIE_TX_p[1]\"\n    },\n    \"PCIE_tx_p[2]\": {\n\t\"PIO_DIRECTION\": \"OUTPUT\",\n\t\"PCIE\": \"PCIE_TX_p[2]\"\n    },\n    \"PCIE_tx_p[3]\": {\n\t\"PIO_DIRECTION\": \"OUTPUT\",\n\t\"PCIE\": \"PCIE_TX_p[3]\"\n    },\n    \"PCIE_tx_p[4]\": {\n\t\"PIO_DIRECTION\": \"OUTPUT\",\n\t\"PCIE\": \"PCIE_TX_p[4]\"\n    },\n    \"PCIE_tx_p[5]\": {\n\t\"PIO_DIRECTION\": \"OUTPUT\",\n\t\"PCIE\": \"PCIE_TX_p[5]\"\n    },\n    \"PCIE_tx_p[6]\": {\n\t\"PIO_DIRECTION\": \"OUTPUT\",\n\t\"PCIE\": \"PCIE_TX_p[6]\"\n    },\n    \"PCIE_tx_p[7]\": {\n\t\"PIO_DIRECTION\": \"OUTPUT\",\n\t\"PCIE\": \"PCIE_TX_p[7]\"\n    },\n    \"PCIE_rx_p[0]\": {\n\t\"PIO_DIRECTION\": \"INPUT\",\n\t\"PCIE\": \"PCIE_RX_p[0]\"\n    },\n    \"PCIE_rx_p[1]\": {\n\t\"PIO_DIRECTION\": \"INPUT\",\n\t\"PCIE\": \"PCIE_RX_p[1]\"\n    },\n    \"PCIE_rx_p[2]\": {\n\t\"PIO_DIRECTION\": \"INPUT\",\n\t\"PCIE\": \"PCIE_RX_p[2]\"\n    },\n    \"PCIE_rx_p[3]\": {\n\t\"PIO_DIRECTION\": \"INPUT\",\n\t\"PCIE\": \"PCIE_RX_p[3]\"\n    },\n    \"PCIE_rx_p[4]\": {\n\t\"PIO_DIRECTION\": \"INPUT\",\n\t\"PCIE\": \"PCIE_RX_p[4]\"\n    },\n    \"PCIE_rx_p[5]\": {\n\t\"PIO_DIRECTION\": \"INPUT\",\n\t\"PCIE\": \"PCIE_RX_p[5]\"\n    },\n    \"PCIE_rx_p[6]\": {\n\t\"PIO_DIRECTION\": \"INPUT\",\n\t\"PCIE\": \"PCIE_RX_p[6]\"\n    },\n    \"PCIE_rx_p[7]\": {\n\t\"PIO_DIRECTION\": \"INPUT\",\n\t\"PCIE\": \"PCIE_RX_p[7]\"\n    },\n    \"pcie_refclk_p\": {\n\t\"PIO_DIRECTION\": \"INPUT\",\n\t\"PCIE\": \"PCIE_REFCLK_p\"\n    },\n    \"pcie_perst_n\": {\n\t\"PIO_DIRECTION\": \"INPUT\",\n\t\"PCIE\": \"PCIE_PERST_n\"\n    },\n    \"osc_50_b3b\": {\n\t\"PIO_DIRECTION\": \"INPUT\",\n\t\"OSC\": \"OSC_50_B3B\"\n    },\n    \"leds[0]\": {\n\t\"PIO_DIRECTION\": \"OUTPUT\",\n\t\"LED\": \"LED[0]\"\n    },\n    \"leds[1]\": {\n\t\"PIO_DIRECTION\": \"OUTPUT\",\n\t\"LED\": \"LED[1]\"\n    },\n    \"leds[2]\": {\n\t\"PIO_DIRECTION\": \"OUTPUT\",\n\t\"LED\": \"LED[2]\"\n    },\n    \"leds[3]\": {\n\t\"PIO_DIRECTION\": \"OUTPUT\",\n\t\"LED\": \"LED[3]\"\n    }\n}\n"
  },
  {
    "path": "examples/simple/boards/htg4.json",
    "content": "{\n    \"PCIE_tx_p[0]\": {\n\t\"PIO_DIRECTION\": \"OUTPUT\",\n\t\"PCIE\": \"PCIE_TX_p[0]\"\n    },\n    \"PCIE_tx_p[1]\": {\n\t\"PIO_DIRECTION\": \"OUTPUT\",\n\t\"PCIE\": \"PCIE_TX_p[1]\"\n    },\n    \"PCIE_tx_p[2]\": {\n\t\"PIO_DIRECTION\": \"OUTPUT\",\n\t\"PCIE\": \"PCIE_TX_p[2]\"\n    },\n    \"PCIE_tx_p[3]\": {\n\t\"PIO_DIRECTION\": \"OUTPUT\",\n\t\"PCIE\": \"PCIE_TX_p[3]\"\n    },\n    \"PCIE_tx_p[4]\": {\n\t\"PIO_DIRECTION\": \"OUTPUT\",\n\t\"PCIE\": \"PCIE_TX_p[4]\"\n    },\n    \"PCIE_tx_p[5]\": {\n\t\"PIO_DIRECTION\": \"OUTPUT\",\n\t\"PCIE\": \"PCIE_TX_p[5]\"\n    },\n    \"PCIE_tx_p[6]\": {\n\t\"PIO_DIRECTION\": \"OUTPUT\",\n\t\"PCIE\": \"PCIE_TX_p[6]\"\n    },\n    \"PCIE_tx_p[7]\": {\n\t\"PIO_DIRECTION\": \"OUTPUT\",\n\t\"PCIE\": \"PCIE_TX_p[7]\"\n    },\n    \"PCIE_rx_p[0]\": {\n\t\"PIO_DIRECTION\": \"INPUT\",\n\t\"PCIE\": \"PCIE_RX_p[0]\"\n    },\n    \"PCIE_rx_p[1]\": {\n\t\"PIO_DIRECTION\": \"INPUT\",\n\t\"PCIE\": \"PCIE_RX_p[1]\"\n    },\n    \"PCIE_rx_p[2]\": {\n\t\"PIO_DIRECTION\": \"INPUT\",\n\t\"PCIE\": \"PCIE_RX_p[2]\"\n    },\n    \"PCIE_rx_p[3]\": {\n\t\"PIO_DIRECTION\": \"INPUT\",\n\t\"PCIE\": \"PCIE_RX_p[3]\"\n    },\n    \"PCIE_rx_p[4]\": {\n\t\"PIO_DIRECTION\": \"INPUT\",\n\t\"PCIE\": \"PCIE_RX_p[4]\"\n    },\n    \"PCIE_rx_p[5]\": {\n\t\"PIO_DIRECTION\": \"INPUT\",\n\t\"PCIE\": \"PCIE_RX_p[5]\"\n    },\n    \"PCIE_rx_p[6]\": {\n\t\"PIO_DIRECTION\": \"INPUT\",\n\t\"PCIE\": \"PCIE_RX_p[6]\"\n    },\n    \"PCIE_rx_p[7]\": {\n\t\"PIO_DIRECTION\": \"INPUT\",\n\t\"PCIE\": \"PCIE_RX_p[7]\"\n    },\n    \"pcie_refclk_p\": {\n\t\"PIO_DIRECTION\": \"INPUT\",\n\t\"PCIE\": \"PCIE_REFCLK_p\"\n    },\n    \"pcie_perst_n\": {\n\t\"PIO_DIRECTION\": \"INPUT\",\n\t\"PCIE\": \"PCIE_PERST_n\"\n    },\n    \"clk_100Mhz\": {\n\t\"PIO_DIRECTION\": \"INPUT\",\n\t\"OSC\": \"CLK100\"\n    },\n    \"leds[0]\": {\n\t\"PIO_DIRECTION\": \"OUTPUT\",\n\t\"LED\": \"LED[0]\"\n    },\n    \"leds[1]\": {\n\t\"PIO_DIRECTION\": \"OUTPUT\",\n\t\"LED\": \"LED[1]\"\n    },\n    \"leds[2]\": {\n\t\"PIO_DIRECTION\": \"OUTPUT\",\n\t\"LED\": \"LED[2]\"\n    },\n    \"leds[3]\": {\n\t\"PIO_DIRECTION\": \"OUTPUT\",\n\t\"LED\": \"LED[3]\"\n    }\n}\n"
  },
  {
    "path": "examples/simple/simple.h",
    "content": "/* Copyright (c) 2014 Quanta Research Cambridge, Inc\n * Copyright (c) 2016 Connectal Project\n *\n * Permission is hereby granted, free of charge, to any person obtaining a\n * copy of this software and associated documentation files (the \"Software\"),\n * to deal in the Software without restriction, including without limitation\n * the rights to use, copy, modify, merge, publish, distribute, sublicense,\n * and/or sell copies of the Software, and to permit persons to whom the\n * Software is furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n * DEALINGS IN THE SOFTWARE.\n */\n#include <assert.h>\n#include \"SimpleRequest.h\"\n\n#if 1\n#define TEST_ASSERT(A) assert(A)\n#else\n#define TEST_ASSERT(A) {}\n#endif\n\n#define NUMBER_OF_TESTS 13\n\nuint32_t v1a = 42;\nuint32_t v2a = 2;\nuint32_t v2b = 4;\nS2 s2 = {7, 8, 9};\nS1 s1 = {3, 6};\nuint32_t v5a = 0x00000000;\nuint64_t v5b = 0xDEADBEEFFECAFECA;\nuint32_t v5c = 0x00000001;\nuint32_t v6a = 0xBBBBBBBB;\nuint64_t v6b = 0x000000EFFECAFECA;\nuint32_t v6c = 0xCCCCCCCC;\nuint32_t v7a = 0xDADADADA;\nE1 v7b = E1Choice2;\nS3 s3 = { a: v7a, e1: v7b };\nE1 v9v = E1Choice2;\nE1 v9w = E1ChoiceBig;\n\nbsvvector_Luint32_t_L2 xs = { 0xa1, 0xa2 };\nbsvvector_Luint32_t_L2 ys = { 0xb1, 0xb2 };\nbsvvector_Luint32_t_L2 zs = { 0xc1, 0xc2 };\n\nclass Simple : public SimpleRequestWrapper\n{  \npublic:\n  uint32_t cnt;\n  uint32_t times;\n  void incr_cnt(){\n    if (++cnt == NUMBER_OF_TESTS)\n      exit(0);\n  }\n  void say1(uint32_t a) {\n    fprintf(stderr, \"say1(%d)\\n\", a);\n    TEST_ASSERT(a == v1a);\n    incr_cnt();\n  }\n  void say2(uint16_t a, uint16_t b) {\n    fprintf(stderr, \"say2(%d %d)\\n\", a, b);\n    TEST_ASSERT(a == v2a);\n    TEST_ASSERT(b == v2b);\n    incr_cnt();\n  }\n  void say3(S1 s){\n    fprintf(stderr, \"say3(S1{a:%d,b:%d})\\n\", s.a, s.b);\n    TEST_ASSERT(s.a == s1.a);\n    TEST_ASSERT(s.b == s1.b);\n    incr_cnt();\n  }\n  void say4(S2 s){\n    fprintf(stderr, \"say4(S2{a:%d,b:%d,c:%d})\\n\", s.a,s.b,s.c);\n    TEST_ASSERT(s.a == s2.a);\n    TEST_ASSERT(s.b == s2.b);\n    TEST_ASSERT(s.c == s2.c);\n    incr_cnt();\n  }\n  void say5(uint32_t a, uint64_t b, uint32_t c) {\n    fprintf(stderr, \"say5(%08x, %016llx, %08x)\\n\", a, (long long)b, c);\n    TEST_ASSERT(a == v5a);\n    TEST_ASSERT(b == v5b);\n    TEST_ASSERT(c == v5c);\n    incr_cnt();\n  }\n  void say6(uint32_t a, uint64_t b, uint32_t c) {\n    fprintf(stderr, \"say6(%08x, %016llx, %08x)\\n\", a, (long long)b, c);\n    TEST_ASSERT(a == v6a);\n    TEST_ASSERT(b == v6b);\n    TEST_ASSERT(c == v6c);\n    incr_cnt();\n  }\n  void say7(S3 v) {\n    fprintf(stderr, \"say7(%08x, %08x)\\n\", v.a, v.e1);\n    TEST_ASSERT(v.a == v7a);\n    TEST_ASSERT(v.e1 == v7b);\n    incr_cnt();\n  }\n  void say8 ( const bsvvector_Luint32_t_L128 v ) {\n    fprintf(stderr, \"say8\\n\");\n    for (int i = 0; i < 128; i++)\n        fprintf(stderr, \"    [%d] = 0x%x\\n\", i, v[i]);\n    incr_cnt();\n  }\n  void say9(E1 v, E1 w) {\n    fprintf(stderr, \"say9(%08x, %08x)\\n\", v, w);\n    TEST_ASSERT(v == v9v);\n    TEST_ASSERT(w == v9w);\n    incr_cnt();\n  }\n  void sayv1(const int32_t*arg1, const int32_t*arg2) {\n    fprintf(stderr, \"sayv1\\n\");\n    for (int i = 0; i < 4; i++)\n        fprintf(stderr, \"    [%d] = 0x%x, 0x%x\\n\", i, arg1[i], arg2[i]);\n    incr_cnt();\n  }\n  void sayv2(const int16_t* v) {\n    fprintf(stderr, \"sayv2\\n\");\n    for (int i = 0; i < 16; i++)\n        fprintf(stderr, \"    [%d] = 0x%x\\n\", i, v[i] & 0xffff);\n    incr_cnt();\n  }\n  void sayv3(const int16_t* v, int16_t count) {\n    fprintf(stderr, \"sayv3: count 0x%x\\n\", count);\n    for (int i = 0; i < 16; i++)\n        fprintf(stderr, \"    [%d] = 0x%x\\n\", i, v[i] & 0xffff);\n    incr_cnt();\n  }\n  void saypixels ( const bsvvector_Luint32_t_L2 indxs, const bsvvector_Luint32_t_L2 indys, const bsvvector_Luint32_t_L2 indzs ) {\n      fprintf(stderr, \"saypixels\\n\");\n      for (int i = 0; i < 2; i++) {\n          fprintf(stderr, \"xs[%d] = %08x ys[%d] = %08x zs[%d] = %08x\\n\",\n                  i, indxs[i], i, indys[i], i, indzs[i]);\n      }\n      incr_cnt();\n  }\n  void reftest1 ( const Address dst, const Intptr dst_stride, const Address src1, const Intptr i_src_stride1, const Address src2, const Intptr i_src_stride2, const Byte i_width, const Byte i_height, const int qpelInt, const int hasWeight, const Byte i_offset, const Byte i_scale, const Byte i_denom ) {\n    fprintf(stderr, \"reftest1: %x, %x, %x, %x, %x, %x, %x, %x, %x, %x, %x, %x, %x\\n\",\n       (uint32_t)dst, (uint32_t)dst_stride, (uint32_t)src1, (uint32_t)i_src_stride1, (uint32_t)src2, (uint32_t)i_src_stride2, (uint32_t)i_width, (uint32_t)i_height, (uint32_t)qpelInt, (uint32_t)hasWeight, (uint32_t)i_offset, (uint32_t)i_scale, (uint32_t)i_denom );\n    incr_cnt();\n  }\n  Simple(unsigned int id, PortalTransportFunctions *transport = 0, void *param = 0, PortalPoller *poller = 0)\n    : SimpleRequestWrapper(id, transport, param, poller), cnt(0){}\n};\n"
  },
  {
    "path": "examples/simple/testsimple.cpp",
    "content": "/* Copyright (c) 2014 Quanta Research Cambridge, Inc\n * Copyright (c) 2016 Connectal Project\n *\n * Permission is hereby granted, free of charge, to any person obtaining a\n * copy of this software and associated documentation files (the \"Software\"),\n * to deal in the Software without restriction, including without limitation\n * the rights to use, copy, modify, merge, publish, distribute, sublicense,\n * and/or sell copies of the Software, and to permit persons to whom the\n * Software is furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n * DEALINGS IN THE SOFTWARE.\n */\n#include <assert.h>\n#include \"SimpleRequest.h\"\n#include \"simple.h\"\n\nint main(int argc, const char **argv)\n{\n  int32_t testval = 0x1234abcd, v1arg1[4], v1arg2[4];\n  int16_t v2v[16];\n  Simple indication(IfcNames_SimpleRequestH2S);\n  SimpleRequestProxy *device = new SimpleRequestProxy(IfcNames_SimpleRequestS2H);\n  device->pint.busyType = BUSY_SPIN;   /* spin until request portal 'notFull' */\n\n  fprintf(stderr, \"Main::calling say1(%d)\\n\", v1a);\n  device->say1(v1a);  \n  fprintf(stderr, \"Main::calling say2(%d, %d)\\n\", v2a,v2b);\n  device->say2(v2a,v2b);\n  fprintf(stderr, \"Main::calling say3(S1{a:%d,b:%d})\\n\", s1.a,s1.b);\n  device->say3(s1);\n  fprintf(stderr, \"Main::calling say4(S2{a:%d,b:%d,c:%d})\\n\", s2.a,s2.b,s2.c);\n  device->say4(s2);\n  fprintf(stderr, \"Main::calling say5(%08x, %016llx, %08x)\\n\", v5a, (long long)v5b, v5c);\n  device->say5(v5a, v5b, v5c);  \n  fprintf(stderr, \"Main::calling say6(%08x, %016llx, %08x)\\n\", v6a, (long long)v6b, v6c);\n  device->say6(v6a, v6b, v6c);  \n  fprintf(stderr, \"Main::calling say7(%08x, %08x)\\n\", s3.a, s3.e1);\n  device->say7(s3);  \n  bsvvector_Luint32_t_L128 vect;\n  for (int i = 0; i < 128; i++)\n    vect[i] = -i*32;\n  fprintf(stderr, \"Main::calling say8\\n\");\n  device->say8(vect);  \n  for (int i = 0; i < 4; i++) {\n    v1arg1[i] = testval;\n    v1arg2[i] = ~testval;\n    testval = (testval << 4) | ((testval >> 28) & 0xf);\n  }\n  fprintf(stderr, \"Main::calling say9\\n\");\n  device->say9(v9v, v9w);\n  device->sayv1(v1arg1, v1arg2);\n  testval = 0x12349876;\n  for (int i = 0; i < 16; i++) {\n    v2v[i] = testval;\n    testval = (testval << 4) | ((testval >> 28) & 0xf);\n  }\n  device->sayv2(v2v);\n  device->sayv3(v2v, 44);\n  device->saypixels(xs, ys, zs);\n  device->reftest1 ( 0xaabbcc, 0x11223344, 0xddeeff, 0x44332211, 0x123456, 0x87654321, 0x12, 0x34, 0x123456, 0x7654321, 0x34, 0x56, 0x77);\n  fprintf(stderr, \"Main::about to go to sleep\\n\");\n  while(1)\n    sleep(10);\n}\n"
  },
  {
    "path": "examples/simplemultibluesim/Link.bsv",
    "content": "/* Copyright (c) 2015 Quanta Research Cambridge, Inc\n *\n * Permission is hereby granted, free of charge, to any person obtaining a\n * copy of this software and associated documentation files (the \"Software\"),\n * to deal in the Software without restriction, including without limitation\n * the rights to use, copy, modify, merge, publish, distribute, sublicense,\n * and/or sell copies of the Software, and to permit persons to whom the\n * Software is furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n * DEALINGS IN THE SOFTWARE.\n */\nimport Vector::*;\nimport FIFO::*;\nimport GetPut::*;\nimport Pipe::*;\nimport Connectable::*;\nimport CtrlMux::*;\nimport Portal::*;\nimport ConnectalConfig::*;\nimport CnocPortal::*;\nimport SimLink::*;\nimport LinkIF::*;\nimport Simple::*;\nimport SimpleRequest::*;\nimport LinkRequest::*;\n\nmodule mkLink#(SimpleRequest simple2IndicationProxy)(Link);\n   // the indications from simpleRequest will be connected to the request interface to simpleReuqest2\n   Reg#(Bit#(1)) listening <- mkReg(0);\n\n   Bool useLink = True;\n   Integer linknumber = 17;\n\n   SimpleRequestOutput simple1Output <- mkSimpleRequestOutput();\n   Simple simple1 <- mkSimple(simple1Output.ifc);\n\n   Simple simple2 <- mkSimple(simple2IndicationProxy);\n   SimpleRequestInput simple2Input <- mkSimpleRequestInput();\n   mkConnection(simple2Input.pipes, simple2.request);\n\n   // now connect them via a Cnoc link\n   SimLink#(32) link <- mkSimLink();\n\n   let msgIndication <- mkPortalMsgIndication(22, simple1Output.portalIfc.indications, simple1Output.portalIfc.messageSize);\n   let msgRequest <- mkPortalMsgRequest(23, simple2Input.portalIfc.requests);\n\n   if (useLink) begin\n       rule tx;\n\t  let msg <- toGet(msgIndication.message).get();\n\t  $display(\"%d.%d transmitting msg %h\", linknumber, listening, msg);\n\t  link.tx.enq(msg);\n       endrule\n      rule rx;\n\t let v <- toGet(link.rx).get();\n\t msgRequest.message.enq(v);\n\t $display(\"%d.%d received msg %h\", linknumber, listening, v);\n      endrule\n   end\n   if (!useLink)\n      rule connect if (!useLink);\n\t let v <- toGet(msgIndication.message).get();\n\t msgRequest.message.enq(v);\n\t $display(\"message value %h\", v);\n      endrule\n\n   interface SimpleRequest simpleRequest = simple1.request;\n   interface LinkRequest linkRequest;\n      method Action start(Bit#(32) l);\n\t $display(\"Link.start linknumber=%d l=%d\", linknumber,l);\n\t if (useLink) link.start(fromInteger(linknumber), unpack(truncate(l)));\n\t listening <= truncate(l);\n      endmethod\n   endinterface\n\nendmodule : mkLink\n\nexport mkLink;\nexport Link;\n"
  },
  {
    "path": "examples/simplemultibluesim/LinkIF.bsv",
    "content": "/* Copyright (c) 2015 Connectal Project.\n *\n * Permission is hereby granted, free of charge, to any person obtaining a\n * copy of this software and associated documentation files (the \"Software\"),\n * to deal in the Software without restriction, including without limitation\n * the rights to use, copy, modify, merge, publish, distribute, sublicense,\n * and/or sell copies of the Software, and to permit persons to whom the\n * Software is furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n * DEALINGS IN THE SOFTWARE.\n */\n\nimport ConnectalConfig::*;\nimport Simple::*;\n\ninterface LinkRequest;\n   method Action start(Bit#(32) listening);\nendinterface\n\ninterface Link;\n   interface LinkRequest linkRequest;\n   interface SimpleRequest simpleRequest;\nendinterface\n\n"
  },
  {
    "path": "examples/simplemultibluesim/Makefile",
    "content": "CONNECTALDIR?=../..\nS2H_INTERFACES = LinkRequest:Link.linkRequest SimpleRequest:Link.simpleRequest\nH2S_INTERFACES = Link:SimpleRequest\n\nBSVFILES = ../simple/Simple.bsv LinkIF.bsv\nCPPFILES=testsimple.cpp\n\ninclude $(CONNECTALDIR)/Makefile.connectal\n"
  },
  {
    "path": "examples/simplemultibluesim/run.sh",
    "content": "#!/bin/sh\n\ncd bluesim\n\nBLUESIM_SOCKET_NAME=socket1 ./bin/bsim & bsim1_pid=$!\nBLUESIM_SOCKET_NAME=socket2 ./bin/bsim & bsim2_pid=$!\n\nBLUESIM_SOCKET_NAME=socket1 ./bin/bsim_exe & bsimexe1_pid=$!\nBLUESIM_SOCKET_NAME=socket2 ./bin/bsim_exe & bsimexe2_pid=$!\n\nwait $bsimexe1_pid $bsimexe2_pid\nkill $bsim1_pid $bsim2_pid\n"
  },
  {
    "path": "examples/simplemultibluesim/testsimple.cpp",
    "content": "/* Copyright (c) 2014 Quanta Research Cambridge, Inc\n *\n * Permission is hereby granted, free of charge, to any person obtaining a\n * copy of this software and associated documentation files (the \"Software\"),\n * to deal in the Software without restriction, including without limitation\n * the rights to use, copy, modify, merge, publish, distribute, sublicense,\n * and/or sell copies of the Software, and to permit persons to whom the\n * Software is furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n * DEALINGS IN THE SOFTWARE.\n */\n\n#include <stdio.h>\n#include <assert.h>\n\n#include <GeneratedTypes.h>\n#include \"SimpleRequest.h\"\n#include \"LinkRequest.h\"\n\n#define NUMBER_OF_TESTS 8\n\nuint32_t v1a = 42;\n\nint v2a = 2;\nint v2b = 4;\n\nS2 s2 = {7, 8, 9};\n\nS1 s1 = {3, 6};\n\nuint32_t v5a = 0x00000000;\nuint64_t v5b = 0xDEADBEEFFECAFECA;\nuint32_t v5c = 0x00000001;\n\nuint32_t v6a = 0xBBBBBBBB;\nuint64_t v6b = 0x000000EFFECAFECA;\nuint32_t v6c = 0xCCCCCCCC;\n\nuint32_t v7a = 0xDADADADA;\nE1 v7b = E1Choice2;\nS3 s3 = { a: v7a, e1: v7b };\n\n\nclass SimpleRequest : public SimpleRequestWrapper\n{\npublic:\n  uint32_t cnt;\n  void incr_cnt(){\n    cnt++;\n    fprintf(stderr, \"saw %d responses\\n\", cnt);\n    if (cnt == NUMBER_OF_TESTS)\n      exit(0);\n  }\n  virtual void say1(uint32_t a) {\n    fprintf(stderr, \"say1(%d)\\n\", a);\n    assert(a == v1a);\n    incr_cnt();\n  }\n  virtual void say2(uint16_t a, uint16_t b) {\n    fprintf(stderr, \"say2(%d %d)\\n\", a, b);\n    assert(a == v2a);\n    assert(b == v2b);\n    incr_cnt();\n  }\n  virtual void say3(S1 s){\n    fprintf(stderr, \"say3(S1{a:%d,b:%d})\\n\", s.a, s.b);\n    assert(s.a == s1.a);\n    assert(s.b == s1.b);\n    incr_cnt();\n  }\n  virtual void say4(S2 s){\n    fprintf(stderr, \"say4(S2{a:%d,b:%d,c:%d})\\n\", s.a,s.b,s.c);\n    assert(s.a == s2.a);\n    assert(s.b == s2.b);\n    assert(s.c == s2.c);\n    incr_cnt();\n  }\n  virtual void say5(uint32_t a, uint64_t b, uint32_t c) {\n    fprintf(stderr, \"say5(%08x, %016llx, %08x)\\n\", a, (long long)b, c);\n    assert(a == v5a);\n    assert(b == v5b);\n    assert(c == v5c);\n    incr_cnt();\n  }\n  virtual void say6(uint32_t a, uint64_t b, uint32_t c) {\n    fprintf(stderr, \"say6(%08x, %016llx, %08x)\\n\", a, (long long)b, c);\n    assert(a == v6a);\n    assert(b == v6b);\n    assert(c == v6c);\n    incr_cnt();\n  }\n  virtual void say7(S3 v) {\n    fprintf(stderr, \"say7(%08x, %08x)\\n\", v.a, v.e1);\n    assert(v.a == v7a);\n    assert(v.e1 == v7b);\n    incr_cnt();\n  }\n  virtual void say8 ( const bsvvector_Luint32_t_L128 v ) {\n    fprintf(stderr, \"say8\\n\");\n    for (int i = 0; i < 128; i++)\n        fprintf(stderr, \"    [%d] = 0x%x\\n\", i, v[i]);\n    incr_cnt();\n  }\n  void sayv1(const int32_t*arg1, const int32_t*arg2) {\n    fprintf(stderr, \"sayv1\\n\");\n    for (int i = 0; i < 4; i++)\n        fprintf(stderr, \"    [%d] = 0x%x, 0x%x\\n\", i, arg1[i], arg2[i]);\n    incr_cnt();\n  }\n  void sayv2(const int16_t* v) {\n    fprintf(stderr, \"sayv2\\n\");\n    for (int i = 0; i < 16; i++)\n        fprintf(stderr, \"    [%d] = 0x%x\\n\", i, v[i] & 0xffff);\n    incr_cnt();\n  }\n  void sayv3(const int16_t* v, int16_t count) {\n    fprintf(stderr, \"sayv3: count 0x%x\\n\", count);\n    for (int i = 0; i < 16; i++)\n        fprintf(stderr, \"    [%d] = 0x%x\\n\", i, v[i] & 0xffff);\n    incr_cnt();\n  }\n  void reftest1 ( const Address dst, const Intptr dst_stride, const Address src1, const Intptr i_src_stride1, const Address src2, const Intptr i_src_stride2, const Byte i_width, const Byte i_height, const int qpelInt, const int hasWeight, const Byte i_offset, const Byte i_scale, const Byte i_denom ) {\n    fprintf(stderr, \"reftest1: %x, %x, %x, %x, %x, %x, %x, %x, %x, %x, %x, %x, %x\\n\",\n       (uint32_t)dst, (uint32_t)dst_stride, (uint32_t)src1, (uint32_t)i_src_stride1, (uint32_t)src2, (uint32_t)i_src_stride2, (uint32_t)i_width, (uint32_t)i_height, (uint32_t)qpelInt, (uint32_t)hasWeight, (uint32_t)i_offset, (uint32_t)i_scale, (uint32_t)i_denom );\n    incr_cnt();\n  }\n  SimpleRequest(unsigned int id) : SimpleRequestWrapper(id), cnt(0){}\n};\n\n\n\nint main(int argc, const char **argv)\n{\n  LinkRequestProxy linkRequest(IfcNames_LinkRequestS2H);\n  SimpleRequest indication(IfcNames_SimpleRequestH2S);\n  SimpleRequestProxy device(IfcNames_SimpleRequestS2H);\n  linkRequest.pint.busyType = BUSY_SPIN;   /* spin until request portal 'notFull' */\n  device.pint.busyType = BUSY_SPIN;   /* spin until request portal 'notFull' */\n\n  const char *socketName = getenv(\"BLUESIM_SOCKET_NAME\");\n  if (!socketName) {\n    fprintf(stderr, \"Specify name of link socket to use BLUESIM_SOCKET_NAME\");\n    exit(1);\n  }\n  int listening = (strcmp(socketName, \"socket1\") == 0);\n\n  fprintf(stderr, \"linkRequest.start(%d) [socketName=%s]\\n\", listening, socketName);\n  linkRequest.start(listening);\n\n  if (1) {\n    fprintf(stderr, \"Main::calling say1(%d)\\n\", v1a);\n    device.say1(v1a);\n    fprintf(stderr, \"Main::calling say2(%d, %d)\\n\", v2a,v2b);\n    device.say2(v2a,v2b);\n    fprintf(stderr, \"Main::calling say3(S1{a:%d,b:%d})\\n\", s1.a,s1.b);\n    device.say3(s1);\n    fprintf(stderr, \"Main::calling say4(S2{a:%d,b:%d,c:%d})\\n\", s2.a,s2.b,s2.c);\n    device.say4(s2);\n    fprintf(stderr, \"Main::calling say5(%08x, %016llx, %08x)\\n\", v5a, (long long)v5b, v5c);\n    device.say5(v5a, v5b, v5c);\n    fprintf(stderr, \"Main::calling say6(%08x, %016llx, %08x)\\n\", v6a, (long long)v6b, v6c);\n    device.say6(v6a, v6b, v6c);\n    fprintf(stderr, \"Main::calling say7(%08x, %08x)\\n\", s3.a, s3.e1);\n    device.say7(s3);\n    bsvvector_Luint32_t_L128 vect;\n    for (int i = 0; i < 128; i++)\n      vect[i] = -i*32;\n    fprintf(stderr, \"Main::calling say8\\n\");\n    device.say8(vect);\n  }\n  fprintf(stderr, \"Main::about to go to sleep\\n\");\n  while(true){sleep(2);}\n}\n"
  },
  {
    "path": "examples/simplemultibluesim/xsimrun.sh",
    "content": "#!/bin/sh\n\ncd xsim\n\nSOFTWARE_SOCKET_NAME=node1. xsim -R work.xsimtop  & xsim1_pid=$!\nSOFTWARE_SOCKET_NAME=node2. xsim -R work.xsimtop & xsim2_pid=$!\n\nsleep 10\n\nSOFTWARE_SOCKET_NAME=node1. ./bin/ubuntu.exe & xsimexe1_pid=$!\nSOFTWARE_SOCKET_NAME=node2. ./bin/ubuntu.exe & xsimexe2_pid=$!\n\nwait $xsimexe1_pid $xsimexe2_pid\nkill $xsim1_pid $xsim2_pid\n"
  },
  {
    "path": "examples/simplesharedhw/Makefile",
    "content": "CONNECTALDIR?=../..\nINTERFACES = SharedMemoryPortalConfig\nS2H_INTERFACES = /SimpleRequest:Simple.request\nH2S_INTERFACES = /Simple:SimpleRequest\nMEM_READ_INTERFACES = \"cons(lSharereadEngine.dmaClient,nil)\"\nMEM_WRITE_INTERFACES = \"cons(lSharewriteEngine.dmaClient,nil)\"\n\nCONNECTALFLAGS += -D USE_ACP -D USE_DUAL_CLOCK_FIFOF\nBSVFILES = Simple.bsv $(CONNECTALDIR)/bsv/Portal.bsv\nCPPFILES=testsimple.cpp\nCONNECTALFLAGS += -D USE_ACP\nAUTOTOP = --importfiles SharedMemoryPortal --importfiles SharedMemoryPortalConfig --importfiles MemTypes --importfiles MemReadEngine --importfiles MemWriteEngine\n\ninclude $(CONNECTALDIR)/Makefile.connectal\n"
  },
  {
    "path": "examples/simplesharedhw/Simple.bsv",
    "content": "\n// Copyright (c) 2013 Nokia, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\nimport FIFO::*;\nimport Vector::*;\n\ntypedef struct{\n   Bit#(32) a;\n   Bit#(32) b;\n   } S1 deriving (Bits);\n\ntypedef struct{\n   Bit#(32) a;\n   Bit#(16) b;\n   Bit#(7) c;\n   } S2 deriving (Bits);\n\ntypedef enum {\n   E1Choice1,\n   E1Choice2,\n   E1Choice3\n   } E1 deriving (Bits,Eq);\n\ntypedef struct{\n   Bit#(32) a;\n   E1 e1;\n   } S3 deriving (Bits);\n\ninterface SimpleRequest;\n    method Action say1(Bit#(32) v);\n    method Action say2(Bit#(16) a, Bit#(16) b);\n    method Action say3(S1 v);\n    method Action say4(S2 v);\n    method Action say5(Bit#(32)a, Bit#(64) b, Bit#(32) c);\n    method Action say6(Bit#(32)a, Bit#(40) b, Bit#(32) c);\n    method Action say7(S3 v);\n    method Action say8(Vector#(128, Bit#(32)) v);\n    method Action sayv1 (Vector#(4, Int#(32)) arg1, Vector#(4, Int#(32)) arg2);\n    method Action sayv2 (Vector#(16, Int#(16)) v);\n    method Action sayv3 (Vector#(16, Int#(16)) v, Int#(16) count);\nendinterface\n\ntypedef struct {\n    Bit#(32) a;\n    Bit#(40) b;\n    Bit#(32) c;\n} Say6ReqSimple deriving (Bits);\n\ninterface Simple;\n   interface SimpleRequest request;\nendinterface\n\nmodule mkSimple#(SimpleRequest indication)(Simple);\n   let verbose = False;\n\n   interface SimpleRequest request;\n   method Action say1(Bit#(32) v);\n      if (verbose) $display(\"mkSimple::say1\");\n      indication.say1(v);\n   endmethod\n\n   method Action say2(Bit#(16) a, Bit#(16) b);\n      if (verbose) $display(\"mkSimple::say2\");\n      indication.say2(a,b);\n   endmethod\n\n   method Action say3(S1 v);\n      if (verbose) $display(\"mkSimple::say3\");\n      indication.say3(v);\n   endmethod\n\n   method Action say4(S2 v);\n      if (verbose) $display(\"mkSimple::say4\");\n      indication.say4(v);\n   endmethod\n\n   method Action say5(Bit#(32) a, Bit#(64) b, Bit#(32) c);\n      if (verbose) $display(\"mkSimple::say5\");\n      indication.say5(a, b, c);\n   endmethod\n\n   method Action say6(Bit#(32) a, Bit#(40) b, Bit#(32) c);\n      if (verbose) $display(\"mkSimple::say6\");\n      indication.say6(a, b, c);\n   endmethod\n\n   method Action say7(S3 v);\n      if (verbose) $display(\"mkSimple::say7\");\n      indication.say7(v);\n   endmethod\n\n   method Action say8(Vector#(128, Bit#(32)) v);\n      if (verbose) $display(\"mkSimple::say8\");\n      indication.say8(v);\n   endmethod\n   method Action sayv1 (Vector#(4, Int#(32)) arg1, Vector#(4, Int#(32)) arg2);\n      if (verbose) $display(\"mkSimple::sayv1\");\n      indication.sayv1(arg1, arg2);\n   endmethod\n   method Action sayv2 (Vector#(16, Int#(16)) v);\n      if (verbose) $display(\"mkSimple::sayv2\");\n      indication.sayv2(v);\n   endmethod\n   method Action sayv3 (Vector#(16, Int#(16)) v, Int#(16) count);\n      if (verbose) $display(\"mkSimple::sayv3\");\n      indication.sayv3(v, count);\n   endmethod\n   endinterface\nendmodule\n"
  },
  {
    "path": "examples/simplesharedhw/testsimple.cpp",
    "content": "/* Copyright (c) 2014 Quanta Research Cambridge, Inc\n *\n * Permission is hereby granted, free of charge, to any person obtaining a\n * copy of this software and associated documentation files (the \"Software\"),\n * to deal in the Software without restriction, including without limitation\n * the rights to use, copy, modify, merge, publish, distribute, sublicense,\n * and/or sell copies of the Software, and to permit persons to whom the\n * Software is furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n * DEALINGS IN THE SOFTWARE.\n */\n#include <assert.h>\n#include \"SimpleRequest.h\"\n#include \"dmaManager.h\"\n#include \"manualMMUIndication.h\"\n\n#if 1\n#define TEST_ASSERT(A) assert(A)\n#else\n#define TEST_ASSERT(A) {}\n#endif\n\nuint32_t v1a = 42;\nint v2a = 2;\nint v2b = 4;\nS2 s2 = {7, 8, 9};\nS1 s1 = {3, 6};\nuint32_t v5a = 0x00000000;\nuint64_t v5b = 0xDEADBEEFFECAFECA;\nuint32_t v5c = 0x00000001;\nuint32_t v6a = 0xBBBBBBBB;\nuint64_t v6b = 0x000000EFFECAFECA;\nuint32_t v6c = 0xCCCCCCCC;\nuint32_t v7a = 0xDADADADA;\nE1 v7b = E1Choice2;\nS3 s3 = { a: v7a, e1: v7b };\n\nclass Simple : public SimpleRequestWrapper\n{  \npublic:\n  uint32_t cnt;\n  uint32_t times;\n  sem_t sem;\n  void wait() {\n    sem_wait(&sem);\n    cnt = 0;\n  }\n  void incr_cnt(){\n    if (++cnt == 7*times)\n      sem_post(&sem);\n  }\n  void say1(uint32_t a) {\n    fprintf(stderr, \"say1(%d)\\n\", a);\n    TEST_ASSERT(a == v1a);\n    incr_cnt();\n  }\n  void say2(uint16_t a, uint16_t b) {\n    fprintf(stderr, \"say2(%d %d)\\n\", a, b);\n    TEST_ASSERT(a == v2a);\n    TEST_ASSERT(b == v2b);\n    incr_cnt();\n  }\n  void say3(S1 s){\n    fprintf(stderr, \"say3(S1{a:%d,b:%d})\\n\", s.a, s.b);\n    TEST_ASSERT(s.a == s1.a);\n    TEST_ASSERT(s.b == s1.b);\n    incr_cnt();\n  }\n  void say4(S2 s){\n    fprintf(stderr, \"say4(S2{a:%d,b:%d,c:%d})\\n\", s.a,s.b,s.c);\n    TEST_ASSERT(s.a == s2.a);\n    TEST_ASSERT(s.b == s2.b);\n    TEST_ASSERT(s.c == s2.c);\n    incr_cnt();\n  }\n  void say5(uint32_t a, uint64_t b, uint32_t c) {\n    fprintf(stderr, \"say5(%08x, %016llx, %08x)\\n\", a, (long long)b, c);\n    TEST_ASSERT(a == v5a);\n    TEST_ASSERT(b == v5b);\n    TEST_ASSERT(c == v5c);\n    incr_cnt();\n  }\n  void say6(uint32_t a, uint64_t b, uint32_t c) {\n    fprintf(stderr, \"say6(%08x, %016llx, %08x)\\n\", a, (long long)b, c);\n    TEST_ASSERT(a == v6a);\n    TEST_ASSERT(b == v6b);\n    TEST_ASSERT(c == v6c);\n    incr_cnt();\n  }\n  void say7(S3 v) {\n    fprintf(stderr, \"say7(%08x, %08x)\\n\", v.a, v.e1);\n    TEST_ASSERT(v.a == v7a);\n    TEST_ASSERT(v.e1 == v7b);\n    incr_cnt();\n  }\n  void say8 ( const bsvvector_Luint32_t_L128 v ) {\n    fprintf(stderr, \"say8\\n\");\n    for (int i = 0; i < 128; i++)\n        fprintf(stderr, \"    [%d] = 0x%x\\n\", i, v[i]);\n    incr_cnt();\n  }\n  void sayv1(const int32_t*arg1, const int32_t*arg2) {\n    fprintf(stderr, \"sayv1\\n\");\n    for (int i = 0; i < 4; i++)\n        fprintf(stderr, \"    [%d] = 0x%x, 0x%x\\n\", i, arg1[i], arg2[i]);\n    incr_cnt();\n  }\n  void sayv2(const int16_t* v) {\n    fprintf(stderr, \"sayv2\\n\");\n    for (int i = 0; i < 16; i++)\n        fprintf(stderr, \"    [%d] = 0x%x\\n\", i, v[i] & 0xffff);\n    incr_cnt();\n  }\n  void sayv3(const int16_t* v, int16_t count) {\n    fprintf(stderr, \"sayv3: count 0x%x\\n\", count);\n    for (int i = 0; i < 16; i++)\n        fprintf(stderr, \"    [%d] = 0x%x\\n\", i, v[i] & 0xffff);\n    incr_cnt();\n  }\n  Simple(unsigned int id, unsigned int numtimes=1, PortalTransportFunctions *item=0, void *param = 0) : SimpleRequestWrapper(id, item, param), cnt(0), times(numtimes) {\n    sem_init(&sem, 0, 0);\n  }\n};\n\nDmaManager *dma;\nSimple *indication;\nint main(int argc, const char **argv)\n{\n    int verbose = 1;\n    int numtimes = 10;\n    int wait_per_iter = 1;\n    uint32_t alloc_sz = 32768;\n    dma = platformInit();\n\n//#define FF {dma}\n#define FF SHARED_DMA(PlatformIfcNames_MMURequestS2H, PlatformIfcNames_MMUIndicationH2S)\n    PortalSharedParam parami = {FF, alloc_sz, SHARED_HARDWARE(IfcNames_SimpleRequestPipesH2S)};\n    indication = new Simple(IfcNames_SimpleRequestH2S,\n\t\t\t    (wait_per_iter) ? 1 : numtimes\n\t\t\t    , &transportShared, &parami\n\t\t\t    );\n    PortalSharedParam paramr = {FF, alloc_sz, SHARED_HARDWARE(IfcNames_SimpleRequestPipesS2H)};\n    SimpleRequestProxy *device = new SimpleRequestProxy(IfcNames_SimpleRequestS2H, &transportShared, &paramr);\n\n    // currently no interrupts on shared memory portals, so timeout after 1ms\n    defaultPoller->timeout = 100;\n\n    for (int i = 0; i < numtimes; i++) {\n      if (verbose) fprintf(stderr, \"Main::calling say1(%d)\\n\", v1a);\n      device->say1(v1a);  \n      if (verbose) fprintf(stderr, \"Main::calling say2(%d, %d)\\n\", v2a,v2b);\n      device->say2(v2a,v2b);\n      if (verbose) fprintf(stderr, \"Main::calling say3(S1{a:%d,b:%d})\\n\", s1.a,s1.b);\n      device->say3(s1);\n      if (verbose) fprintf(stderr, \"Main::calling say4(S2{a:%d,b:%d,c:%d})\\n\", s2.a,s2.b,s2.c);\n      device->say4(s2);\n      if (verbose) fprintf(stderr, \"Main::calling say5(%08x, %016llx, %08x)\\n\", v5a, (long long)v5b, v5c);\n      device->say5(v5a, v5b, v5c);  \n      if (verbose) fprintf(stderr, \"Main::calling say6(%08x, %016llx, %08x)\\n\", v6a, (long long)v6b, v6c);\n      device->say6(v6a, v6b, v6c);  \n      if (verbose) fprintf(stderr, \"Main::calling say7(%08x, %08x)\\n\", s3.a, s3.e1);\n      device->say7(s3);  \n      if (wait_per_iter)\n\tfprintf(stderr, \"Waiting for iter %d responses\\n\", i);\n\tindication->wait();\n\tfprintf(stderr, \"Received iter %d responses\\n\", i);\n    }\n    if (!wait_per_iter)\n      indication->wait();\n    return 0;\n}\n"
  },
  {
    "path": "examples/strstr/Makefile",
    "content": "CONNECTALDIR?=../..\nS2H_INTERFACES = StrstrRequest:StrstrExample.request\nH2S_INTERFACES = StrstrExample:StrstrIndication\nMEM_READ_INTERFACES = lStrstrExample.readClients\n\nBSVFILES = $(CONNECTALDIR)/lib/strstr/bsv/Strstr.bsv StrstrExample.bsv\nCPPFILES=teststrstr.cpp\nCONNECTALFLAGS += -I $(CONNECTALDIR)/lib/strstr/cpp\n\ninclude $(CONNECTALDIR)/Makefile.connectal\n"
  },
  {
    "path": "examples/strstr/StrstrExample.bsv",
    "content": "// Copyright (c) 2016 Accelerated Tech, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\nimport Strstr::*;\nimport Vector::*;\nimport BuildVector::*;\n\nimport ConnectalMemTypes::*;\n\ninterface StrstrExample;\n   interface StrstrRequest request;\n   interface Vector#(2, MemReadClient#(64)) readClients;\nendinterface\n\nmodule mkStrstrExample#(StrstrIndication ind)(StrstrExample);\n   Strstr#(64,64) strstr <- mkStrstr(ind);\n   interface request = strstr.request;\n   interface readClients = append(strstr.config_read_client, strstr.haystack_read_client);\nendmodule\n"
  },
  {
    "path": "examples/strstr/teststrstr.cpp",
    "content": "/* Copyright (c) 2013 Quanta Research Cambridge, Inc\n *\n * Permission is hereby granted, free of charge, to any person obtaining a\n * copy of this software and associated documentation files (the \"Software\"),\n * to deal in the Software without restriction, including without limitation\n * the rights to use, copy, modify, merge, publish, distribute, sublicense,\n * and/or sell copies of the Software, and to permit persons to whom the\n * Software is furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n * DEALINGS IN THE SOFTWARE.\n */\n#include <fcntl.h>\n#include <assert.h>\n#include \"dmaManager.h\"\n#include \"StrstrIndication.h\"\n#include \"StrstrRequest.h\"\n#include \"strstr.h\"\n#include \"mp.h\"\n\nint sw_match_cnt = 0;\n\nint main(int argc, const char **argv)\n{\n  StrstrRequestProxy *device = 0;\n  StrstrIndication *deviceIndication = 0;\n\n  fprintf(stderr, \"%s %s\\n\", __DATE__, __TIME__);\n  device = new StrstrRequestProxy(IfcNames_StrstrRequestS2H);\n  deviceIndication = new StrstrIndication(IfcNames_StrstrIndicationH2S);\n    DmaManager *dma = platformInit();\n\n  if(1){\n    fprintf(stderr, \"simple tests\\n\");\n    int needleAlloc;\n    int haystackAlloc;\n    int mpNextAlloc;\n    unsigned int alloc_len = 4096;\n    \n    needleAlloc = portalAlloc(alloc_len, 0);\n    mpNextAlloc = portalAlloc(alloc_len, 0);\n    haystackAlloc = portalAlloc(alloc_len, 0);\n\n    char *needle = (char *)portalMmap(needleAlloc, alloc_len);\n    char *haystack = (char *)portalMmap(haystackAlloc, alloc_len);\n    struct MP *mpNext = (struct MP *)portalMmap(mpNextAlloc, alloc_len);\n    \n    const char *needle_text = \"ababab\";\n    const char *haystack_text = \"acabcabacababacababababababcacabcabacababacabababc\";\n    const int hmul = 1;\n    \n    assert(strlen(haystack_text)*hmul < alloc_len);\n    assert(strlen(needle_text)*4 < alloc_len);\n\n    strncpy(needle, needle_text, alloc_len);\n    for (int i = 0; i < hmul; i++)\n      strcpy(haystack+(i*strlen(haystack_text)), haystack_text);\n\n    int needle_len = strlen(needle);\n    int haystack_len = strlen(haystack);\n    int border[needle_len+1];\n\n    compute_borders(needle, border, needle_len);\n    compute_MP_next(needle, mpNext, needle_len);\n\n    assert(mpNext[1].index == 0);\n    assert(border[1] == 0);\n    for (int i = 2; i < needle_len+1; i++)\n      assert(mpNext[i].index == border[i-1]+1);\n\n    for (int i = 0; i < needle_len; i++)\n      fprintf(stderr, \"needle[%d]=%x mpNext[%d]=%d\\n\", i, needle[i], i+1, ((int *)mpNext)[i+1]);\n\n    portalTimerStart(0);\n    MP(needle, haystack, mpNext, needle_len, haystack_len, &sw_match_cnt);\n    fprintf(stderr, \"elapsed time (hw cycles): %lld\\n\", (long long)portalTimerLap(0));\n    \n    for (int i = 0; i < needle_len; i++)\n      fprintf(stderr, \"needle[%d]=%x mpNext[%d]=%x\\n\", i, needle[i], i+1, ((int *)mpNext)[i+1]);\n\n    portalCacheFlush(needleAlloc, needle, alloc_len, 1);\n    portalCacheFlush(mpNextAlloc, mpNext, alloc_len, 1);\n\n    unsigned int ref_needle = dma->reference(needleAlloc);\n    unsigned int ref_mpNext = dma->reference(mpNextAlloc);\n    unsigned int ref_haystack = dma->reference(haystackAlloc);\n\n    fprintf(stderr, \"about to invoke device ref_needle=%d ref_mpNext=%d ref_haystack=%d\\n\",\n\t    ref_needle, ref_mpNext, ref_haystack);\n    device->setup(ref_needle, ref_mpNext, needle_len);\n    sleep(2);\n    portalTimerStart(0);\n    device->search(ref_haystack, haystack_len);\n    deviceIndication->wait();\n    //uint64_t cycles = portalTimerLap(0);\n    //uint64_t beats = hostMemServerIndication->getMemoryTraffic(ChannelType_Read);\n    //fprintf(stderr, \"memory read utilization (beats/cycle): %f\\n\", ((float)beats)/((float)cycles));\n\n    close(needleAlloc);\n    close(haystackAlloc);\n    close(mpNextAlloc);\n  }\n\n  if(1){\n    fprintf(stderr, \"benchmarks\\n\");\n    int needleAlloc;\n    int haystackAlloc;\n    int mpNextAlloc;\n    const char *needle_text = \"I have control\\n\";\n#ifdef SIMULATION\n    int BENCHMARK_INPUT_SIZE = 16 << 15;\n#else\n    int BENCHMARK_INPUT_SIZE = 16 << 18;\n#endif\n    int haystack_alloc_len = BENCHMARK_INPUT_SIZE;\n    int needle_alloc_len = (strlen(needle_text)+4095)&~4095l;\n    int mpNext_alloc_len = needle_alloc_len*4;\n    \n    needleAlloc = portalAlloc(needle_alloc_len, 0);\n    haystackAlloc = portalAlloc(haystack_alloc_len, 0);\n    mpNextAlloc = portalAlloc(mpNext_alloc_len, 0);\n\n    char *needle = (char *)portalMmap(needleAlloc, needle_alloc_len);\n    char *haystack = (char *)portalMmap(haystackAlloc, haystack_alloc_len);\n    struct MP *mpNext = (struct MP *)portalMmap(mpNextAlloc, mpNext_alloc_len);\n\n    int ref_needle = dma->reference(needleAlloc);\n    int ref_haystack = dma->reference(haystackAlloc);\n    int ref_mpNext = dma->reference(mpNextAlloc);\n\n    int fp = open(\"/dev/urandom\", O_RDONLY);\n    int rv = read(fp, haystack, BENCHMARK_INPUT_SIZE);\n    if (rv != BENCHMARK_INPUT_SIZE) {\n        printf(\"[%s:%d] /dev/urandom failed?\\n\", __FUNCTION__, __LINE__);\n    }\n    strncpy(needle, needle_text, needle_alloc_len);\n    \n    int needle_len = strlen(needle);\n    int haystack_len = haystack_alloc_len;\n    int border[needle_len+1];\n\n    compute_borders(needle, border, needle_len);\n    compute_MP_next(needle, mpNext, needle_len);\n\n    assert(mpNext[1].index == 0);\n    assert(border[1] == 0);\n    for (int i = 2; i < needle_len+1; i++)\n      assert(mpNext[i].index == border[i-1]+1);\n\n    fprintf(stderr, \"about to invoke device ref_needle=%d ref_mpNext=%d ref_haystack=%d needle_len=%d needle_alloc_len=%d haystack_len=%d\\n\",\n\t    ref_needle, ref_mpNext, ref_haystack, needle_len, needle_alloc_len, haystack_len);\n\n    portalTimerStart(0);\n    MP(needle, haystack, mpNext, needle_len, haystack_len, &sw_match_cnt);\n    uint64_t sw_cycles = portalTimerLap(0);\n    fprintf(stderr, \"sw_cycles:%llx\\n\", (long long)sw_cycles);\n\n    portalCacheFlush(needleAlloc, needle, needle_alloc_len, 1);\n    portalCacheFlush(mpNextAlloc, mpNext, mpNext_alloc_len, 1);\n\n    device->setup(ref_needle, ref_mpNext, needle_len);\n    portalTimerStart(0);\n    device->search(ref_haystack, haystack_len);\n    deviceIndication->wait();\n    //uint64_t hw_cycles = portalTimerLap(0);\n    //uint64_t beats = hostMemServerIndication->getMemoryTraffic(ChannelType_Read);\n    //float read_util = (float)beats/(float)hw_cycles;\n    //fprintf(stderr, \"hw_cycles:%llx\\n\", (long long)hw_cycles);\n    //fprintf(stderr, \"memory read utilization (beats/cycle): %f\\n\", read_util);\n    //fprintf(stderr, \"speedup: %f\\n\", ((float)sw_cycles)/((float)hw_cycles));\n\n    //MonkitFile(\"perf.monkit\")\n      //.setHwCycles(hw_cycles)\n      //.setSwCycles(sw_cycles)\n      //.setReadBwUtil(read_util)\n      //.writeFile();\n  }\n  int hw_match_cnt = deviceIndication->match_cnt;\n  fprintf(stderr, \"teststrstr: Done, sw_match_cnt=%d, hw_match_cnt=%d\\n\", sw_match_cnt, hw_match_cnt);\n  return (sw_match_cnt != hw_match_cnt);\n}\n"
  },
  {
    "path": "examples/swmemcpy/Makefile",
    "content": "BASEDIR = ../../\nUTILDIR = ../../cpp/\n\ntestpa:\n\tg++ -I$(BASEDIR) testpa.cpp $(UTILDIR)/portal.c $(UTILDIR)/sock_utils.c -pthread\n\nclean:\n\trm a.out\n"
  },
  {
    "path": "examples/swmemcpy/SWmemcpy.bsv",
    "content": "// Copyright (c) 2013 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\ninterface CoreRequest;\nendinterface\n\ninterface CoreIndication;\nendinterface\n\ninterface SWmemcpyRequest;\n   interface CoreRequest coreRequest;\nendinterface\n\ninterface SWmemcpyIndication;\n   interface CoreIndication coreIndication;\nendinterface\n\nmodule mkSWmemcpyRequest#(SWmemcpyIndication indication)(SWmemcpyRequest);\n   interface CoreRequest coreRequest = ?;\nendmodule"
  },
  {
    "path": "examples/swmemcpy/testswmemcpy.cpp",
    "content": "/* Copyright (c) 2014 Quanta Research Cambridge, Inc\n *\n * Permission is hereby granted, free of charge, to any person obtaining a\n * copy of this software and associated documentation files (the \"Software\"),\n * to deal in the Software without restriction, including without limitation\n * the rights to use, copy, modify, merge, publish, distribute, sublicense,\n * and/or sell copies of the Software, and to permit persons to whom the\n * Software is furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n * DEALINGS IN THE SOFTWARE.\n */\n#include <stdio.h>\n#include <sys/mman.h>\n#include <string.h>\n#include <stdlib.h>\n#include <unistd.h>\n#include <pthread.h>\n#include <semaphore.h>\n\n#include \"portal.h\"\n#include \"dmaManager.h\"\n#include \"sock_utils.h\"\n\nint numWords = 16;\nsize_t test_sz  = numWords*sizeof(unsigned int);\nsize_t alloc_sz = test_sz;\n\nclass TestPM : public ConnectalMemory\n{\npublic:\n  virtual void sglist(uint32_t off, uint64_t addr, uint32_t len) {}\n  virtual void paref(uint32_t off, uint32_t ref) {}\n  TestPM() : ConnectalMemory(){}\n};\n\nvoid* child(void* prd_sock)\n{\n  int fd;\n  int rd_sock = *((int*)prd_sock);\n  sock_fd_read(rd_sock, &fd);\n\n  unsigned int *dstBuffer = (unsigned int *)DmaManager_mmap(fd, alloc_sz);\n  //fprintf(stderr, \"child::mmap %08x\\n\", dstBuffer);  \n\n  unsigned int sg = 0;\n  bool mismatch = false;\n  for (int i = 0; i < numWords; i++){\n    mismatch |= (dstBuffer[i] != sg++);\n    fprintf(stderr, \"%08x, %08x\\n\", dstBuffer[i], sg-1);\n  }\n  fprintf(stderr, \"child::writeDone mismatch=%d\\n\", mismatch);\n  munmap(dstBuffer, alloc_sz);\n  close(fd);\n  return NULL;\n}\n\n\nvoid* parent(void* pwr_sock)\n{\n  int wr_sock = *((int*)pwr_sock);\n  int dstAlloc;\n  unsigned int *dstBuffer = 0;\n  unsigned int *dba = 0;\n  class TestPM *pm = new TestPM();\n  \n  fprintf(stderr, \"parent::allocating memory...\\n\");\n  dstAlloc = pm->alloc(alloc_sz);\n  dstBuffer = (unsigned int *)DmaManager_mmap(dstAlloc.header.fd, alloc_sz);\n  fprintf(stderr, \"parent::mmap %p\\n\", dstBuffer);  \n\n  for (int i = 0; i < numWords; i++){\n    dstBuffer[i] = i;\n  }\n  \n  pm->dCacheFlushInval(dstAlloc, alloc_sz, dstBuffer);\n  fprintf(stderr, \"parent::flush and invalidate complete\\n\");\n\n  int rc = ioctl(pm->pa_fd, PA_DEBUG_PK, &dstAlloc);\n  fprintf(stderr, \"parent::debug ioctl complete (%d)\\n\",rc);\n\n  dba = (unsigned int *)DmaManager_mmap(dstAlloc.header.fd, alloc_sz);\n  fprintf(stderr, \"parent::mmap %p\\n\", dba);  \n\n  unsigned int sg = 0;\n  bool mismatch = false;\n  for (int i = 0; i < numWords; i++){\n    mismatch |= (dba[i] != sg++);\n    fprintf(stderr, \"%08x, %08x\\n\", dba[i], dstBuffer[i]);\n  }\n  fprintf(stderr, \"parent::writeDone mismatch=%d\\n\", mismatch);\n\n  sock_fd_write(wr_sock, NULL, 0, dstAlloc.header.fd);\n  munmap(dstBuffer, alloc_sz);\n  close(dstAlloc.header.fd);\n  return NULL;\n}\n\nint main(int argc, const char **argv)\n{\n  int sv[2];\n  int pid;\n\n  if (socketpair(AF_LOCAL, SOCK_STREAM, 0, sv) < 0) {\n    perror(\"socketpair\");\n    exit(1);\n  }\n    \n  switch ((pid = fork())) {\n  case 0:\n    close(sv[0]);\n    child(&sv[1]);\n    break;\n  case -1:\n    perror(\"fork\");\n    exit(1);\n  default:\n    close(sv[1]);\n    parent(&sv[0]);\n    break;\n  }\n}\n"
  },
  {
    "path": "examples/vectoradd_hls/Makefile",
    "content": "CONNECTALDIR?=../../\nS2H_INTERFACES = VaddRequest:Vadd.request\nH2S_INTERFACES = Vadd:VaddResponse\n\nBSVFILES = bsv/Vadd.bsv\nCPPFILES = testvadd.cpp\n\nCONNECTALFLAGS += -V solution1/impl/verilog\n\ninclude $(CONNECTALDIR)/Makefile.connectal\n"
  },
  {
    "path": "examples/vectoradd_hls/README.md",
    "content": "# Vector Add HLS Example\n\nThis is a very simple example showing how to integrate Verilog modules\ngenerated Vivado HLS into BSV.\n\n## TL;DR:\n\nHaving installed connectal, verilator and bluespec, to build and run this example:\n\n    make -j22 build.verilator ; make run.verilator\n\n## Description of the code structure\n\nThe HLS source code is:\n\n    void vectoradd(const int in0[64], const int in1[64], int out[64])\n    {\n    #pragma HLS interface ap_hs port=in0\n    #pragma HLS interface ap_hs port=in1\n    #pragma HLS interface ap_hs port=out\n\t    for (int i = 0; i < 64; i++)\n    #pragma unroll 4\n\t\t    out[i] = in0[i] + in1[i];\n    }\n\nThe Makefile does not currently run vivado_hls, but the generated\nverilog is in the repo.\n\nThe `HLS interface ap_hs` pragma directs Vivado HLS to generate a port\nwith valid/ack handshaking. It's similar to AXI stream, but I chose\nthis option because it's easier to remember that `ack` is the response\nthan `ready`.\n\nThe generated Verilog module has the following interface:\n\n    module vectoradd (\n\tinput   ap_clk,\n\tinput   ap_rst,\n\tinput   ap_start,\n\toutput   ap_done,\n\toutput   ap_idle,\n\toutput   ap_ready,\n\tinput  [31:0] in0,\n\tinput   in0_ap_vld,\n\toutput   in0_ap_ack,\n\tinput  [31:0] in1,\n\tinput   in1_ap_vld,\n\toutput   in1_ap_ack,\n\toutput  [31:0] out_r,\n\toutput   out_r_ap_vld,\n\tinput   out_r_ap_ack);\n\nConnectal's importbvi.py script produces a basic `import \"BVI\"`\ndefinition for the module so we can invoke it from BSV. Matching the\nport declarations against the Vivado HLS conventions, importbvi.py\ncould generate the following BSV interface for the module:\n\n    interface Vaddhls;\n       interface Put#(Bit#(32)) in0;\n       interface Put#(Bit#(32)) in1;\n       interface Get#(Bit#(32)) out;\n       method Action start();\n       method ActionValue#(Bit#(1)) done();\n    endinterface\n\nI write my test benches in software, which is quite easy to do with\nConnectal. So even though this is about the slowest way possible to\nrun this \"accelerator\", I wrapped it up in the following top level BSV\nmodule:\n\n    // requests from software to hardware\n    interface VaddRequest;\n       method Action data(Bit#(32) in0, Bit#(32) in1);\n       method Action start();\n    endinterface\n\n    // responses from hardware to software\n    interface VaddResponse;\n       method Action data(Bit#(32) out);\n       method Action done();\n    endinterface\n\n    interface Vadd;\n       interface VaddRequest request;\n    endinterface\n\n    module mkVadd#(VaddResponse response)(Vadd);\n       Vaddhls vaddhls <- mkVaddhls(64);\n\n       rule rl_response;\n\t  let v <- vaddhls.out.get();\n\t  response.data(v);\n       endrule\n\n       rule rl_done;\n\t  let v <- vaddhls.done();\n\t  response.done();\n       endrule\n\n       interface VaddRequest request;\n\t  method Action data(Bit#(32) in0, Bit#(32) in1);\n\t     vaddhls.in0.put(in0);\n\t     vaddhls.in1.put(in1);\n\t  endmethod\n\t  method Action start();\n\t     vaddhls.start();\n\t  endmethod\n       endinterface\n    endmodule\n\nAnd finally the test driver:\n\n    #include <stdio.h>\n    #include <VaddRequest.h>\n    #include <VaddResponse.h>\n\n    volatile int finished = 0;\n    class VaddResponse : public VaddResponseWrapper\n    {\n    private:\n      int i;\n      int received_done;\n    public:\n      virtual void data ( const uint32_t out ) {\n\tfprintf(stderr, \"data[%d] = %d\\n\", i, out);\n\ti = i + 1;\n\tif (i >= 64 && received_done)\n\t  finished = 1;\n      }\n      virtual void done() {\n\tfprintf(stderr, \"done\\n\");\n\treceived_done = 1;\n\tif (i >= 64 && received_done)\n\t  finished = 1;\n      }\n      void clear() {\n\ti = 0;\n\treceived_done = 0;\n\tfinished = 0;\n      }\n      VaddResponse(unsigned int id, PortalTransportFunctions *transport = 0, void *param = 0, PortalPoller *poller = 0)\n\t: VaddResponseWrapper(id, transport, param, poller) {\n\ti = 0;\n\treceived_done = 0;\n      }\n    };\n\n    int main(int argc, const char **argv)\n    {\n      // Instantiate response handler, which will run in a second thread\n      VaddResponse response(IfcNames_VaddResponseH2S);\n      // Instantiate the request proxy\n      VaddRequestProxy *request = new VaddRequestProxy(IfcNames_VaddRequestS2H);\n\n      // [1] Batch processing mode\n\n      // send the data to the logic\n      for (int i = 0; i < 64; i++) {\n\trequest->data(i, i*2);\n      }\n      // start the computation\n      request->start();\n\n      // wait for responses\n      while (!finished)\n\tsleep(1);\n\n      // clear the response handler so we can use it again\n      response.clear();\n\n      // [2] Pipelined processing mode\n\n      // start the computation\n      request->start();\n\n      // send the data\n      for (int i = 0; i < 64; i++) {\n\trequest->data(i, i*2);\n      }\n\n      // wait for responses\n      while (!finished)\n\tsleep(1);\n\n      return 0;\n    }\n\n"
  },
  {
    "path": "examples/vectoradd_hls/bsv/Vadd.bsv",
    "content": "\nimport GetPut::*;\nimport FIFOF::*;\nimport VaddBvi::*;\n\n// requests from software to hardware\ninterface VaddRequest;\n   method Action data(Bit#(32) in0, Bit#(32) in1);\n   method Action start();\nendinterface\n\n// responses from hardware to software\ninterface VaddResponse;\n   method Action data(Bit#(32) out);\n   method Action done();\nendinterface\n\ninterface Vadd;\n   interface VaddRequest request;\nendinterface\n\nmodule mkVadd#(VaddResponse response)(Vadd);\n   Vaddhls vaddhls <- mkVaddhls(64);\n\n   rule rl_response;\n      let v <- vaddhls.out.get();\n      response.data(v);\n   endrule\n\n   rule rl_done;\n      let v <- vaddhls.done();\n      response.done();\n   endrule\n\n   interface VaddRequest request;\n      method Action data(Bit#(32) in0, Bit#(32) in1);\n\t vaddhls.in0.put(in0);\n\t vaddhls.in1.put(in1);\n      endmethod\n      method Action start();\n\t vaddhls.start();\n      endmethod\n   endinterface\nendmodule\n"
  },
  {
    "path": "examples/vectoradd_hls/bsv/VaddBvi.bsv",
    "content": "\n/*\n   /home/jamey/connectal/generated/scripts/importbvi.py\n   -o\n   VaddBvi.bsv\n   -P\n   VaddBvi\n   -I\n   VaddBvi\n   -c\n   ap_clk\n   -r\n   ap_rst\n   verilog/vectoradd.v\n   -n\n   in0\n   -n\n   in1\n   -n\n   out\n   -n\n   ap\n*/\n\nimport Clocks::*;\nimport DefaultValue::*;\nimport XilinxCells::*;\nimport GetPut::*;\nimport AxiBits::*;\nimport FIFOF::*;\n\n(* always_ready, always_enabled *)\ninterface VaddBvi;\n    method Bit#(1)     ap_done();\n    method Bit#(1)     ap_idle();\n    method Bit#(1)     ap_ready();\n    method Action      ap_start(Bit#(1) v);\n    method Action      in0(Bit#(32) v);\n    method Bit#(1)     in0_ap_ack();\n    method Action      in0_ap_vld(Bit#(1) v);\n    method Action      in1(Bit#(32) v);\n    method Bit#(1)     in1_ap_ack();\n    method Action      in1_ap_vld(Bit#(1) v);\n    method Bit#(32)     out_r();\n    method Action      out_r_ap_ack(Bit#(1) v);\n    method Bit#(1)     out_r_ap_vld();\nendinterface\nimport \"BVI\" vectoradd =\nmodule mkVaddBvi(VaddBvi);\n   Clock ap_clk <- exposeCurrentClock;\n   Reset reset <- exposeCurrentReset;\n   Reset ap_rst <- mkResetInverter(reset);\n    default_clock ap_clk(ap_clk) = ap_clk;\n    default_reset ap_rst(ap_rst) = ap_rst;\n    method ap_done ap_done();\n    method ap_idle ap_idle();\n    method ap_ready ap_ready();\n    method ap_start(ap_start) enable((*inhigh*) EN_ap_start);\n    method in0(in0) enable((*inhigh*) EN_in0);\n    method in0_ap_ack in0_ap_ack();\n    method in0_ap_vld(in0_ap_vld) enable((*inhigh*) EN_in0_ap_vld);\n    method in1(in1) enable((*inhigh*) EN_in1);\n    method in1_ap_ack in1_ap_ack();\n    method in1_ap_vld(in1_ap_vld) enable((*inhigh*) EN_in1_ap_vld);\n    method out_r out_r();\n    method out_r_ap_ack(out_r_ap_ack) enable((*inhigh*) EN_out_r_ap_ack);\n    method out_r_ap_vld out_r_ap_vld();\n    schedule (ap_done, ap_idle, ap_ready, ap_start, in0, in0_ap_ack, in0_ap_vld, in1, in1_ap_ack, in1_ap_vld, out_r, out_r_ap_ack, out_r_ap_vld) CF (ap_done, ap_idle, ap_ready, ap_start, in0, in0_ap_ack, in0_ap_vld, in1, in1_ap_ack, in1_ap_vld, out_r, out_r_ap_ack, out_r_ap_vld);\nendmodule\n\n// This wrapper was written by hand but could be generated from the\n// HLS-generated Verilog by knowing its conventions for generating\n// module interfaces\ninterface Vaddhls;\n   interface Put#(Bit#(32)) in0;\n   interface Put#(Bit#(32)) in1;\n   interface Get#(Bit#(32)) out;\n   method Action start();\n   method ActionValue#(Bit#(1)) done();\nendinterface\n\nmodule mkVaddhls#(Integer fifoDepth)(Vaddhls);\n   VaddBvi vadd <- mkVaddBvi();\n   \n   FIFOF#(Bit#(32)) in0Fifo <- mkSizedFIFOF(fifoDepth);\n   FIFOF#(Bit#(32)) in1Fifo <- mkSizedFIFOF(fifoDepth);\n   FIFOF#(Bit#(32)) outFifo <- mkSizedFIFOF(fifoDepth);\n\n   rule rl_in0_data;\n      $display(\"in0 %d\", in0Fifo.first);\n      vadd.in0(in0Fifo.first);\n   endrule\n   rule rl_in0_hs;\n      vadd.in0_ap_vld(pack(in0Fifo.notEmpty()));\n      if (vadd.in0_ap_ack() == 1)\n\t in0Fifo.deq();\n   endrule\n   rule rl_in1_data;\n      $display(\"in1 %d\", in1Fifo.first);\n      vadd.in1(in1Fifo.first);\n   endrule\n   rule rl_in1_hs;\n      vadd.in1_ap_vld(pack(in1Fifo.notEmpty()));\n      if (vadd.in1_ap_ack() == 1)\n\t in1Fifo.deq();\n   endrule\n   rule rl_out_data;\n      if (vadd.out_r_ap_vld() == 1) begin\n\t outFifo.enq(vadd.out_r());\n\t $display(\"out %d\", vadd.out_r());\n      end\n   endrule\n   rule rl_out_hs;\n      vadd.out_r_ap_ack(pack(vadd.out_r_ap_vld() == 1 && outFifo.notFull()));\n   endrule\n\n   interface Put in0 = toPut(in0Fifo);\n   interface Put in1 = toPut(in1Fifo);\n   interface Get out = toGet(outFifo);\n\n   method Action start() if (vadd.ap_ready == 1);\n      vadd.ap_start(1);\n   endmethod\n\n   method ActionValue#(Bit#(1)) done() if (vadd.ap_done == 1);\n      return 1;\n   endmethod\n\nendmodule\n"
  },
  {
    "path": "examples/vectoradd_hls/solution1/impl/verilog/vectoradd.v",
    "content": "// ==============================================================\n// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC\n// Version: 2017.4\n// Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.\n// \n// ===========================================================\n\n`timescale 1 ns / 1 ps \n\n(* CORE_GENERATION_INFO=\"vectoradd,hls_ip_2017_4,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7z020clg484-1,HLS_INPUT_CLOCK=10.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=2.552000,HLS_SYN_LAT=65,HLS_SYN_TPT=none,HLS_SYN_MEM=0,HLS_SYN_DSP=0,HLS_SYN_FF=10,HLS_SYN_LUT=149}\" *)\n\nmodule vectoradd (\n        ap_clk,\n        ap_rst,\n        ap_start,\n        ap_done,\n        ap_idle,\n        ap_ready,\n        in0,\n        in0_ap_vld,\n        in0_ap_ack,\n        in1,\n        in1_ap_vld,\n        in1_ap_ack,\n        out_r,\n        out_r_ap_vld,\n        out_r_ap_ack\n);\n\nparameter    ap_ST_fsm_state1 = 2'd1;\nparameter    ap_ST_fsm_state2 = 2'd2;\n\ninput   ap_clk;\ninput   ap_rst;\ninput   ap_start;\noutput   ap_done;\noutput   ap_idle;\noutput   ap_ready;\ninput  [31:0] in0;\ninput   in0_ap_vld;\noutput   in0_ap_ack;\ninput  [31:0] in1;\ninput   in1_ap_vld;\noutput   in1_ap_ack;\noutput  [31:0] out_r;\noutput   out_r_ap_vld;\ninput   out_r_ap_ack;\n\nreg ap_done;\nreg ap_idle;\nreg ap_ready;\nreg in0_ap_ack;\nreg in1_ap_ack;\nreg out_r_ap_vld;\n\n(* fsm_encoding = \"none\" *) reg   [1:0] ap_CS_fsm;\nwire    ap_CS_fsm_state1;\nreg    in0_blk_n;\nwire    ap_CS_fsm_state2;\nwire   [0:0] exitcond_fu_64_p2;\nreg    in1_blk_n;\nreg    out_r_blk_n;\nwire   [6:0] i_1_fu_70_p2;\nreg    ap_block_state2;\nreg    ap_sig_ioackin_out_r_ap_ack;\nreg    ap_block_state2_io;\nreg   [6:0] i_reg_53;\nreg    ap_reg_ioackin_out_r_ap_ack;\nreg   [1:0] ap_NS_fsm;\nreg    ap_condition_100;\nreg    ap_condition_57;\n\n// power-on initialization\ninitial begin\n#0 ap_CS_fsm = 2'd1;\n#0 ap_reg_ioackin_out_r_ap_ack = 1'b0;\nend\n\nalways @ (posedge ap_clk) begin\n    if (ap_rst == 1'b1) begin\n        ap_CS_fsm <= ap_ST_fsm_state1;\n    end else begin\n        ap_CS_fsm <= ap_NS_fsm;\n    end\nend\n\nalways @ (posedge ap_clk) begin\n    if (ap_rst == 1'b1) begin\n        ap_reg_ioackin_out_r_ap_ack <= 1'b0;\n    end else begin\n        if (((exitcond_fu_64_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state2))) begin\n            if ((1'b1 == ap_condition_57)) begin\n                ap_reg_ioackin_out_r_ap_ack <= 1'b0;\n            end else if ((1'b1 == ap_condition_100)) begin\n                ap_reg_ioackin_out_r_ap_ack <= 1'b1;\n            end\n        end\n    end\nend\n\nalways @ (posedge ap_clk) begin\n    if ((~((1'b1 == ap_block_state2_io) | ((exitcond_fu_64_p2 == 1'd0) & (in1_ap_vld == 1'b0)) | ((exitcond_fu_64_p2 == 1'd0) & (in0_ap_vld == 1'b0))) & (exitcond_fu_64_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state2))) begin\n        i_reg_53 <= i_1_fu_70_p2;\n    end else if (((ap_start == 1'b1) & (1'b1 == ap_CS_fsm_state1))) begin\n        i_reg_53 <= 7'd0;\n    end\nend\n\nalways @ (*) begin\n    if ((~((1'b1 == ap_block_state2_io) | ((exitcond_fu_64_p2 == 1'd0) & (in1_ap_vld == 1'b0)) | ((exitcond_fu_64_p2 == 1'd0) & (in0_ap_vld == 1'b0))) & (exitcond_fu_64_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin\n        ap_done = 1'b1;\n    end else begin\n        ap_done = 1'b0;\n    end\nend\n\nalways @ (*) begin\n    if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin\n        ap_idle = 1'b1;\n    end else begin\n        ap_idle = 1'b0;\n    end\nend\n\nalways @ (*) begin\n    if ((~((1'b1 == ap_block_state2_io) | ((exitcond_fu_64_p2 == 1'd0) & (in1_ap_vld == 1'b0)) | ((exitcond_fu_64_p2 == 1'd0) & (in0_ap_vld == 1'b0))) & (exitcond_fu_64_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin\n        ap_ready = 1'b1;\n    end else begin\n        ap_ready = 1'b0;\n    end\nend\n\nalways @ (*) begin\n    if ((ap_reg_ioackin_out_r_ap_ack == 1'b0)) begin\n        ap_sig_ioackin_out_r_ap_ack = out_r_ap_ack;\n    end else begin\n        ap_sig_ioackin_out_r_ap_ack = 1'b1;\n    end\nend\n\nalways @ (*) begin\n    if ((~((1'b1 == ap_block_state2_io) | ((exitcond_fu_64_p2 == 1'd0) & (in1_ap_vld == 1'b0)) | ((exitcond_fu_64_p2 == 1'd0) & (in0_ap_vld == 1'b0))) & (exitcond_fu_64_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state2))) begin\n        in0_ap_ack = 1'b1;\n    end else begin\n        in0_ap_ack = 1'b0;\n    end\nend\n\nalways @ (*) begin\n    if (((exitcond_fu_64_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state2))) begin\n        in0_blk_n = in0_ap_vld;\n    end else begin\n        in0_blk_n = 1'b1;\n    end\nend\n\nalways @ (*) begin\n    if ((~((1'b1 == ap_block_state2_io) | ((exitcond_fu_64_p2 == 1'd0) & (in1_ap_vld == 1'b0)) | ((exitcond_fu_64_p2 == 1'd0) & (in0_ap_vld == 1'b0))) & (exitcond_fu_64_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state2))) begin\n        in1_ap_ack = 1'b1;\n    end else begin\n        in1_ap_ack = 1'b0;\n    end\nend\n\nalways @ (*) begin\n    if (((exitcond_fu_64_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state2))) begin\n        in1_blk_n = in1_ap_vld;\n    end else begin\n        in1_blk_n = 1'b1;\n    end\nend\n\nalways @ (*) begin\n    if ((~(((exitcond_fu_64_p2 == 1'd0) & (in1_ap_vld == 1'b0)) | ((exitcond_fu_64_p2 == 1'd0) & (in0_ap_vld == 1'b0))) & (exitcond_fu_64_p2 == 1'd0) & (ap_reg_ioackin_out_r_ap_ack == 1'b0) & (1'b1 == ap_CS_fsm_state2))) begin\n        out_r_ap_vld = 1'b1;\n    end else begin\n        out_r_ap_vld = 1'b0;\n    end\nend\n\nalways @ (*) begin\n    if (((exitcond_fu_64_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state2))) begin\n        out_r_blk_n = out_r_ap_ack;\n    end else begin\n        out_r_blk_n = 1'b1;\n    end\nend\n\nalways @ (*) begin\n    case (ap_CS_fsm)\n        ap_ST_fsm_state1 : begin\n            if (((ap_start == 1'b1) & (1'b1 == ap_CS_fsm_state1))) begin\n                ap_NS_fsm = ap_ST_fsm_state2;\n            end else begin\n                ap_NS_fsm = ap_ST_fsm_state1;\n            end\n        end\n        ap_ST_fsm_state2 : begin\n            if ((~((1'b1 == ap_block_state2_io) | ((exitcond_fu_64_p2 == 1'd0) & (in1_ap_vld == 1'b0)) | ((exitcond_fu_64_p2 == 1'd0) & (in0_ap_vld == 1'b0))) & (exitcond_fu_64_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin\n                ap_NS_fsm = ap_ST_fsm_state1;\n            end else if ((~((1'b1 == ap_block_state2_io) | ((exitcond_fu_64_p2 == 1'd0) & (in1_ap_vld == 1'b0)) | ((exitcond_fu_64_p2 == 1'd0) & (in0_ap_vld == 1'b0))) & (exitcond_fu_64_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state2))) begin\n                ap_NS_fsm = ap_ST_fsm_state2;\n            end else begin\n                ap_NS_fsm = ap_ST_fsm_state2;\n            end\n        end\n        default : begin\n            ap_NS_fsm = 'bx;\n        end\n    endcase\nend\n\nassign ap_CS_fsm_state1 = ap_CS_fsm[32'd0];\n\nassign ap_CS_fsm_state2 = ap_CS_fsm[32'd1];\n\nalways @ (*) begin\n    ap_block_state2 = (((exitcond_fu_64_p2 == 1'd0) & (in1_ap_vld == 1'b0)) | ((exitcond_fu_64_p2 == 1'd0) & (in0_ap_vld == 1'b0)));\nend\n\nalways @ (*) begin\n    ap_block_state2_io = ((exitcond_fu_64_p2 == 1'd0) & (ap_sig_ioackin_out_r_ap_ack == 1'b0));\nend\n\nalways @ (*) begin\n    ap_condition_100 = (~(((exitcond_fu_64_p2 == 1'd0) & (in1_ap_vld == 1'b0)) | ((exitcond_fu_64_p2 == 1'd0) & (in0_ap_vld == 1'b0))) & (out_r_ap_ack == 1'b1));\nend\n\nalways @ (*) begin\n    ap_condition_57 = ~((1'b1 == ap_block_state2_io) | ((exitcond_fu_64_p2 == 1'd0) & (in1_ap_vld == 1'b0)) | ((exitcond_fu_64_p2 == 1'd0) & (in0_ap_vld == 1'b0)));\nend\n\nassign exitcond_fu_64_p2 = ((i_reg_53 == 7'd64) ? 1'b1 : 1'b0);\n\nassign i_1_fu_70_p2 = (i_reg_53 + 7'd1);\n\nassign out_r = (in0 + in1);\n\nendmodule //vectoradd\n"
  },
  {
    "path": "examples/vectoradd_hls/src/vectoradd.cpp",
    "content": "\n\nvoid vectoradd(const int in0[64], const int in1[64], int out[64])\n{\n#pragma HLS interface ap_hs port=in0\n#pragma HLS interface ap_hs port=in1\n#pragma HLS interface ap_hs port=out\n\tfor (int i = 0; i < 64; i++)\n#pragma unroll 4\n\t\tout[i] = in0[i] + in1[i];\n}\n"
  },
  {
    "path": "examples/vectoradd_hls/testvadd.cpp",
    "content": "\n#include <stdio.h>\n#include <VaddRequest.h>\n#include <VaddResponse.h>\n\nvolatile int finished = 0;\nclass VaddResponse : public VaddResponseWrapper\n{\nprivate:\n  int i;\n  int received_done;\npublic:\n  virtual void data ( const uint32_t out ) {\n    fprintf(stderr, \"data[%d] = %d\\n\", i, out);\n    i = i + 1;\n    if (i >= 64 && received_done)\n      finished = 1;\n  }\n  virtual void done() {\n    fprintf(stderr, \"done\\n\");\n    received_done = 1;\n    if (i >= 64 && received_done)\n      finished = 1;\n  }\n  void clear() {\n    i = 0;\n    received_done = 0;\n    finished = 0;\n  }\n  VaddResponse(unsigned int id, PortalTransportFunctions *transport = 0, void *param = 0, PortalPoller *poller = 0)\n    : VaddResponseWrapper(id, transport, param, poller) {\n    i = 0;\n    received_done = 0;\n  }\n};\n\nint main(int argc, const char **argv)\n{\n  // Instantiate response handler, which will run in a second thread\n  VaddResponse response(IfcNames_VaddResponseH2S);\n  // Instantiate the request proxy\n  VaddRequestProxy *request = new VaddRequestProxy(IfcNames_VaddRequestS2H);\n\n  // [1] Batch processing mode\n\n  // send the data to the logic\n  for (int i = 0; i < 64; i++) {\n    request->data(i, i*2);\n  }\n  // start the computation\n  request->start();\n\n  // wait for responses\n  while (!finished)\n    sleep(1);\n\n  // clear the response handler so we can use it again\n  response.clear();\n\n  // [2] Pipelined processing mode\n\n  // start the computation\n  request->start();\n\n  // send the data\n  for (int i = 0; i < 64; i++) {\n    request->data(i, i*2);\n  }\n\n  // wait for responses\n  while (!finished)\n    sleep(1);\n\n\n  return 0;\n}\n"
  },
  {
    "path": "examples/zedboard_robot/Controller.bsv",
    "content": "\n// Copyright (c) 2014 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\nimport Vector::*;\nimport MaxSonarController::*;\nimport GyroController::*;\nimport HBridgeController::*;\nimport ConnectalSpi::*;\nimport ConnectalMemTypes::*;\nimport Leds::*;\n\ninterface ZedboardRobotPins;\n   interface MaxSonarPins maxsonar;\n   interface SpiMasterPins#(1) spi;\n   interface HBridge2Pins hbridge;\n   interface LEDS leds;\nendinterface\n\ninterface Controller;\n   interface MaxSonarCtrlRequest maxsonar_req;\n   interface GyroCtrlRequest gyro_req;\n   interface HBridgeCtrlRequest hbridge_req;\n   interface ZedboardRobotPins pins;\n   interface MemWriteClient#(64) dmaClient;\nendinterface\n\nmodule mkController#(MaxSonarCtrlIndication maxsonar_ind, GyroCtrlIndication gyro_ind, HBridgeCtrlIndication hbridge_ind)(Controller);\n   MaxSonarController msc <- mkMaxSonarController(maxsonar_ind);\n   GyroController gc <- mkGyroController(gyro_ind);\n   HBridgeController hbc <- mkHBridgeController(hbridge_ind);\n   \n   interface HBridgeCtrlRequest hbridge_req = hbc.req;\n   interface MaxSonarCtrlRequest maxsonar_req = msc.req;\n   interface GyroCtrlRequest gyro_req = gc.req;\n   interface ZedboardRobotPins pins;\n      interface maxsonar = msc.pins.maxsonar;\n      interface spi = gc.pins.spi;\n      interface hbridge = hbc.pins.hbridge;\n      interface leds = hbc.pins.leds;\n   endinterface\n   interface dmaClient = gc.dmaClient;\nendmodule\n"
  },
  {
    "path": "examples/zedboard_robot/Makefile",
    "content": "CONNECTALDIR ?= ../..\nS2H_INTERFACES += MaxSonarCtrlRequest:Controller.maxsonar_req\nS2H_INTERFACES += HBridgeCtrlRequest:Controller.hbridge_req\nS2H_INTERFACES += GyroCtrlRequest:Controller.gyro_req\nH2S_INTERFACES = Controller:MaxSonarCtrlIndication,GyroCtrlIndication,HBridgeCtrlIndication\n\nMEM_WRITE_INTERFACES = cons\\(lController.dmaClient,nil\\)\nINTERFACES += GyroSampleStream MaxSonarSampleStream\n\nZBR = $(CONNECTALDIR)/lib/zedboard_robot\nBSVFILES = Controller.bsv $(ZBR)/bsv/GyroController.bsv $(ZBR)/bsv/MaxSonarController.bsv $(ZBR)/bsv/HBridgeController.bsv\nCPPFILES= test_zedboard_robot.cpp ../maxsonar_simple/maxsonar_simple.h ../hbridge_simple/hbridge_simple.h ../gyro_simple/gyro_simple.h $(ZBR)/cpp/read_buffer.cpp\n\nPIN_TYPE = ZedboardRobotPins\nPIN_TYPE_INCLUDE = Controller\nPINOUT_FILE = pinout.json\nPIN_BINDINGS ?= pmod_sonar:pmodb pmod_gyro:pmodd pmod_hbridge:pmodc\nAUTOTOP = --interface pins:Controller.pins --portname IfcNames_GyroSampleStream --portname IfcNames_MaxSonarSampleStream\n\ninclude $(CONNECTALDIR)/Makefile.connectal\n"
  },
  {
    "path": "examples/zedboard_robot/pinout.json",
    "content": "{\n\n    \"maxsonar_range_ctrl\" : {\n\t\"PIO_DIRECTION\": \"OUTPUT\",\n\t\"pmod_sonar\" : \"J2\"\n    },\n    \"maxsonar_pulse_v\" : {\n\t\"PIO_DIRECTION\": \"INPUT\",\n\t\"pmod_sonar\" : \"J4\"\n    },\n\n    \"spi_mosi\": {\n\t\"PIO_DIRECTION\": \"OUTPUT\",\n\t\"pmod_gyro\": \"J2\"\n    },\n    \"spi_miso_v\": {\n\t\"PIO_DIRECTION\": \"INPUT\",\n\t\"pmod_gyro\": \"J3\"\n    },\n    \"spi_sel_n\": {\n\t\"PIO_DIRECTION\": \"OUTPUT\",\n\t\"pmod_gyro\": \"J1\"\n    },\n    \"CLK_spi_clock\": {\n\t\"PIO_DIRECTION\": \"OUTPUT\",\n\t\"pmod_gyro\": \"J4\"\n    },\n\n    \"hbridge_hbridge0_direction\" : {\n\t\"PIO_DIRECTION\": \"OUTPUT\",\n\t\"pmod_hbridge\" : \"J1\"\n    },\n    \"hbridge_hbridge0_enabled\" : {\n\t\"PIO_DIRECTION\": \"OUTPUT\",\n\t\"pmod_hbridge\" : \"J2\"\n    },\n    \"hbridge_hbridge1_direction\" : { \n\t\"PIO_DIRECTION\": \"OUTPUT\",\n\t\"pmod_hbridge\" : \"J7\"\n    },\n    \"hbridge_hbridge1_enabled\" : { \n\t\"PIO_DIRECTION\": \"OUTPUT\",\n\t\"pmod_hbridge\" : \"J8\"\n    },\n\n    \"leds_leds[0]\" : {\n\t\"PIO_DIRECTION\": \"OUTPUT\",\n\t\"leds\" : \"L0\"\n    },\n    \"leds_leds[1]\" : {\n\t\"PIO_DIRECTION\": \"OUTPUT\",\n\t\"leds\" : \"L1\"\n    },\n    \"leds_leds[2]\" : {\n\t\"PIO_DIRECTION\": \"OUTPUT\",\n\t\"leds\" : \"L2\"\n    },\n    \"leds_leds[3]\" : {\n\t\"PIO_DIRECTION\": \"OUTPUT\",\n\t\"leds\" : \"L3\"\n    },\n    \"leds_leds[4]\" : {\n\t\"PIO_DIRECTION\": \"OUTPUT\",\n\t\"leds\" : \"L4\"\n    },\n    \"leds_leds[5]\" : {\n\t\"PIO_DIRECTION\": \"OUTPUT\",\n\t\"leds\" : \"L5\"\n    },\n    \"leds_leds[6]\" : {\n\t\"PIO_DIRECTION\": \"OUTPUT\",\n\t\"leds\" : \"L6\"\n    },\n    \"leds_leds[7]\" : {\n\t\"PIO_DIRECTION\": \"OUTPUT\",\n\t\"leds\" : \"L7\"\n    }\n\n\n\n}\n\n\n"
  },
  {
    "path": "examples/zedboard_robot/sonarVisualize.py",
    "content": "#!/usr/bin/env python3\n\n# Copyright (c) 2013 Quanta Research Cambridge, Inc.\n\n# Permission is hereby granted, free of charge, to any person\n# obtaining a copy of this software and associated documentation\n# files (the \"Software\"), to deal in the Software without\n# restriction, including without limitation the rights to use, copy,\n# modify, merge, publish, distribute, sublicense, and/or sell copies\n# of the Software, and to permit persons to whom the Software is\n# furnished to do so, subject to the following conditions:\n\n# The above copyright notice and this permission notice shall be\n# included in all copies or substantial portions of the Software.\n\n# THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n# EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n# MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n# BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n# ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n# CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n# SOFTWARE.\n\nfrom visual import *\nimport math\n\nclass sv:\n    def __init__(self):\n        self.main_window=display(title=\"test_maxsonar\", forward=(0,0,-1), width=500, up=(0,1,0), range=(1.2,1.2,1.2))\n        self.main_window.select()\n        self.cnt = 0\n\n    def label_last(self):\n        label(pos=self.last,text=\"%d\"%(self.cnt),box=0,opacity=0)\n        self.cnt = self.cnt+1\n\n    def add_line(self,start,end):\n        curve(pos=[start,end])\n        self.last = end\n        self.label_last()\n\n    def extend_line(self,end):\n        curve(pos=[self.last,end])\n        self.last = end\n        self.label_last()\n\n    def add_ray(self,heading,length):\n        end_point_x = length*math.cos(heading)\n        end_point_y = length*math.sin(heading)\n        curve(pos=[(0,0), (end_point_x/100,end_point_y/50)])\n\nif __name__ == \"__main__\":\n    v = sv()\n    v.add_line((0,0,0),(1,1,0))\n    v.extend_line((1,0,0))\n    v.extend_line((0,0,0))\n\n    v.add_ray(0.1,1);\n    v.add_ray(0.1,1);\n    v.add_ray(0.1,1);\n    v.add_ray(0.1,1);\n    v.add_ray(0.1,1);\n    v.add_ray(0.1,1);\n"
  },
  {
    "path": "examples/zedboard_robot/test_zedboard_robot.cpp",
    "content": "\n// Copyright (c) 2014 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n#include <assert.h>\n#include <netinet/in.h>\n#include \"maxsonar_simple.h\"\n#include \"gyro_simple.h\"\n#include \"hbridge_simple.h\"\n#include \"sock_utils.h\"\n#include \"MaxSonarSampleStream.h\"\n#include \"GyroSampleStream.h\"\n#include \"HBridgeCtrlRequest.h\"\n#include \"MaxSonarCtrlRequest.h\"\n#include \"GyroCtrlRequest.h\"\n#include \"dmaManager.h\"\n#include \"read_buffer.h\"\n\nstatic int spew = 1;\nstatic int host_sw = 1;\nstatic int alloc_sz = 1<<10;\n\nvoid* drive_hbridges(void *_x)\n{\n  HBridgeCtrlRequestProxy *device = (HBridgeCtrlRequestProxy*)_x;\n  sleep(20);\n  // for(int i = 0; i < 2; i++){\n  //   MOVE_FOREWARD(POWER_5);\n  //   sleep(1);\n  //   STOP;\n    \n  //   MOVE_BACKWARD(POWER_5);\n  //   sleep(1);\n  //   STOP;\n    \n  //   TURN_RIGHT(POWER_5);\n  //   sleep(1);\n  //   STOP;\n    \n  //   TURN_LEFT(POWER_5);\n  //   sleep(1);\n  //   STOP;\n\n  //   sleep(1);\n  // }\n  for(int i = 0; i < 30; i++){\n    TURN_RIGHT(POWER_4);\n    usleep(100000);\n    STOP;\n    sleep(1);\n  }\n  STOP;\n  return NULL;\n}\n\nint send_aux(GyroSampleStreamProxy *gssp, void*b, int len, int drop, int spew, int send, MaxSonarSampleStreamProxy *msssp, int usecs)\n{\n  int16_t *ss = (int16_t*)b;\n  int i = 3+drop;\n  while(i < len/2){\n    if (send) {\n      gssp->sample(ss[(i-3)+0], ss[(i-3)+1], ss[(i-3)+2]);\n      // this is a bit wasteful, but it simplifies test_zedboard_robot.py\n      msssp->sample(usecs);\n    }\n    if (spew) fprintf(stderr, \"%8d %8d %8d\\n\", ss[(i-3)+0], ss[(i-3)+1], ss[(i-3)+2]);\n    i+=3;\n  }\n  int missing = i-(len/2);\n  return missing;\n}\n\nint main(int argc, const char **argv)\n{\n\n  // portals communicating between \"main\" running on the ARM and the logic running in the FPGA\n  HBridgeCtrlIndication hbridge_ind(IfcNames_HBridgeCtrlIndicationH2S);\n  HBridgeCtrlRequestProxy *hbridge_ctrl = new HBridgeCtrlRequestProxy(IfcNames_HBridgeCtrlRequestS2H);\n  MaxSonarCtrlIndication *maxsonar_ind = new MaxSonarCtrlIndication(IfcNames_MaxSonarCtrlIndicationH2S);\n  MaxSonarCtrlRequestProxy *maxsonar_ctrl = new MaxSonarCtrlRequestProxy(IfcNames_MaxSonarCtrlRequestS2H);\n  GyroCtrlIndication *gyro_ind = new GyroCtrlIndication(IfcNames_GyroCtrlIndicationH2S);\n  GyroCtrlRequestProxy *gyro_ctrl = new GyroCtrlRequestProxy(IfcNames_GyroCtrlRequestS2H);\n  DmaManager *dma = platformInit();\n\n  // portals communicating between \"main\" running on the ARM and SW running on a server somewhere on the network (HOST_SW)\n  PortalSocketParam param0;\n  getaddrinfo(\"0.0.0.0\", \"5000\", NULL, &param0.addr);\n  GyroSampleStreamProxy *gssp = new GyroSampleStreamProxy(IfcNames_GyroSampleStream, &transportSocketResp, &param0, &GyroSampleStreamJsonProxyReq, 1000);\n  PortalSocketParam param1;\n  getaddrinfo(\"0.0.0.0\", \"5001\", NULL, &param1.addr);\n  MaxSonarSampleStreamProxy *msssp = new MaxSonarSampleStreamProxy(IfcNames_MaxSonarSampleStream, &transportSocketResp, &param1, &MaxSonarSampleStreamJsonProxyReq, 1000);\n\n  // allocate memory for the gyro controller to write samples to\n  int dstAlloc = portalAlloc(alloc_sz, 0);\n  char *dstBuffer = (char *)portalMmap(dstAlloc, alloc_sz);\n  unsigned int ref_dstAlloc = dma->reference(dstAlloc);\n\n  // set design clock frequency (this is important since our PW modulators depend on this number)\n  long req_freq = 100000000; // 100 mHz\n  long freq = 0;\n  setClockFrequency(0, req_freq, &freq);\n  fprintf(stderr, \"Requested FCLK[0]=%ld actually %ld\\n\", req_freq, freq);\n  \n  char* snapshot = (char*)malloc(alloc_sz);\n  reader* r = new reader();\n  //r->verbose = 1;\n\n  // setup gyro registers and dma infra (setup_registers defined gyro_simple.h)\n  setup_registers(gyro_ind,gyro_ctrl, ref_dstAlloc, alloc_sz);  \n  maxsonar_ctrl->range_ctrl(1);\n  int drop = 0;\n\n  // start up the thread to drive the hbridges\n  pthread_t threaddata;\n  pthread_create(&threaddata, NULL, &drive_hbridges, (void*)hbridge_ctrl);\n  \n  while(true){\n#ifdef SIMULATION\n    sleep(5);\n#else\n    usleep(50000*2);\n#endif\n    // first read the \"current\" sonar distance\n    maxsonar_ctrl->pulse_width();\n    sem_wait(&(maxsonar_ind->pulse_width_sem));\n    float distance = ((float)maxsonar_ind->useconds)/147.0;\n\n    // now get the latest window of gyro samples.  begin by disabling gyro writes to the memory buffer\n    set_en(gyro_ind,gyro_ctrl, 0);\n    // read the memory from the circular buffer into \"snapshot\"\n    int datalen = r->read_circ_buff(alloc_sz, ref_dstAlloc, dstAlloc, dstBuffer, snapshot, gyro_ind->write_addr, gyro_ind->write_wrap_cnt); \n    // re-enable the gyro memwrite\n    set_en(gyro_ind,gyro_ctrl, 2);\n    \n    if (spew) fprintf(stderr, \"(%d microseconds == %f inches)\\n\", maxsonar_ind->useconds, distance);\n    // 'datalen' corresponds to the amount of \"new\" samples the gyro controller has written to memory.\n    drop = send_aux(gssp, snapshot, datalen, drop, spew, host_sw, msssp, maxsonar_ind->useconds);\n  }\n}\n"
  },
  {
    "path": "examples/zedboard_robot/test_zedboard_robot.py",
    "content": "#!/usr/bin/env python3\n\n# Copyright (c) 2013 Quanta Research Cambridge, Inc.\n\n# Permission is hereby granted, free of charge, to any person\n# obtaining a copy of this software and associated documentation\n# files (the \"Software\"), to deal in the Software without\n# restriction, including without limitation the rights to use, copy,\n# modify, merge, publish, distribute, sublicense, and/or sell copies\n# of the Software, and to permit persons to whom the Software is\n# furnished to do so, subject to the following conditions:\n\n# The above copyright notice and this permission notice shall be\n# included in all copies or substantial portions of the Software.\n\n# THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n# EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n# MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n# BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n# ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n# CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n# SOFTWARE.\n\nfrom __future__ import print_function\n\nimport struct\nimport sys\nimport os\nsys.path.append(os.path.abspath('../gyro_simple'))\n\nfrom sonarVisualize import *\nfrom gyroVisualize  import *\nfrom test_gyro      import *\n\nsys.path.append(os.path.abspath('../../scripts'))\nimport portalJson\nimport json\n\nsmoothe = False\nif __name__ == \"__main__\":\n    argparser = argparse.ArgumentParser('Display gyroscope data')\n    argparser.add_argument('-vg', '--visualize_gyro', help='Display gyro orientation in 3D rendering', default=False, action='store_true')\n    argparser.add_argument('-vs', '--visualize_sonar', help='Display maxsonar output in X/Y plane', default=False, action='store_true')\n    argparser.add_argument('-a', '--address', help='Device address', default=None)\n    options = argparser.parse_args()\n    spew_gyro = not options.visualize_gyro;\n    spew_sonar = not options.visualize_sonar;\n    visualize_gyro = options.visualize_gyro;\n    visualize_sonar = options.visualize_sonar;\n    print(options.address)\n    if not options.address:\n        options.address = os.environ['RUNPARAM']\n    if (visualize_gyro):\n        g_v  = gv()\n    if (visualize_sonar):\n        s_v  = sv()\n    gs = gyro_stream(smoothe)\n    gjp = portalJson.portal(options.address, 5000)\n    msjp = portalJson.portal(options.address, 5001)\n    summ = [0,0,0]\n    try:\n        while (True):\n            samples = []\n            for i in range(0,48):\n                d = json.loads(gjp.recv())\n                samples.append(d['x'])\n                samples.append(d['y'])\n                samples.append(d['z'])\n                d = json.loads(msjp.recv())\n                sonar_distance = d['v']\n            poss = gs.next_samples(samples)\n            sonar_distance = sonar_distance/147.0\n            if (spew_sonar): print(\"sonar_distance: %f\" % (sonar_distance))\n            if poss is not None:\n                for pos in poss:\n                    if (spew_gyro): print(\"%f %f %f\" % (pos[0],pos[1],pos[2]))\n                    summ[0] = summ[0]+pos[0]\n                    summ[1] = summ[1]+pos[1]\n                    summ[2] = summ[2]+pos[2]\n                    if (visualize_gyro and smoothe):\n                        g_v.update(pos, gs.sample_freq_hz)\n                if (visualize_gyro and (not smoothe)):\n                    g_v.update(summ, gs.sample_freq_hz)\n                if (visualize_sonar):\n                    s_v.add_ray(summ[2],sonar_distance)\n    except KeyboardInterrupt:\n        sc.s.close()\n        sys.exit() \n\n"
  },
  {
    "path": "examples/zynqpcie/Makefile",
    "content": "CONNECTALDIR?=../..\nINTERFACES = Simple ZynqPcieTestIndication ZynqPcieTestRequest\n\nBSVFILES = SimpleIF.bsv ZynqPcieTestIF.bsv Top.bsv\nCPPFILES=testzynqpcie.cpp\nPIN_TYPE=ZynqPcie\nPIN_TYPE_INCLUDE = ZynqPcieTestIF\nCONNECTALFLAGS += -D PcieHostIF=1 -D PCIE_NO_BSCAN=1 --bscflags=\"+RTS -K96000000 -RTS\"\nCONNECTALFLAGS += --xci=$(CONNECTALDIR)/out/$(BOARD)/pcie_7x_0/pcie_7x_0.xci -C $(BOARD)/sources/zynqpcie.xdc\nCONNECTALFLAGS += -P mkPcieHostTopSynth -P mkMemToPcie\n\n## this design would work on a Virtex board with a second PCIE port\nPIN_BINDINGS ?= -b pcie:pcie\n\ngentarget:: $(BOARD)/sources/zynqpcie.xdc\n\nprebuild:: synth-ip.tcl\n\t(cd $(BOARD); vivado -mode batch -source ../synth-ip.tcl)\n\n$(BOARD)/sources/zynqpcie.xdc: zynqpcie.json $(CONNECTALDIR)/boardinfo/$(BOARD).json\n\tmkdir -p $(BOARD)/sources\n\t$(CONNECTALDIR)/scripts/generate-constraints.py $(PIN_BINDINGS) -o $(BOARD)/sources/zynqpcie.xdc --boardfile $(CONNECTALDIR)/boardinfo/$(BOARD).json --pinoutfile zynqpcie.json\n\ninclude $(CONNECTALDIR)/Makefile.connectal\n"
  },
  {
    "path": "examples/zynqpcie/SimpleIF.bsv",
    "content": "\n// Copyright (c) 2013 Nokia, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\nimport FIFO::*;\nimport Vector::*;\n\ntypedef struct{\n   Bit#(32) a;\n   Bit#(32) b;\n   } S1 deriving (Bits);\n\ntypedef struct{\n   Bit#(32) a;\n   Bit#(16) b;\n   Bit#(7) c;\n   } S2 deriving (Bits);\n\ntypedef enum {\n   E1Choice1,\n   E1Choice2,\n   E1Choice3\n   } E1 deriving (Bits,Eq);\n\ntypedef struct{\n   Bit#(32) a;\n   E1 e1;\n   } S3 deriving (Bits);\n\ninterface Simple;\n    method Action say1(Bit#(32) v);\n    method Action say2(Bit#(16) a, Bit#(16) b);\n    method Action say3(S1 v);\n    method Action say4(S2 v);\n    method Action say5(Bit#(32)a, Bit#(64) b, Bit#(32) c);\n    method Action say6(Bit#(32)a, Bit#(40) b, Bit#(32) c);\n    method Action say7(S3 v);\n    method Action say8(Vector#(128, Bit#(32)) v);\nendinterface\n\ntypedef struct {\n    Bit#(32) a;\n    Bit#(40) b;\n    Bit#(32) c;\n} Say6ReqSimple deriving (Bits);\n\n\nmodule mkSimple#(Simple indication)(Simple);\n   \n   let verbose = False;\n   \n   method Action say1(Bit#(32) v);\n      if (verbose) $display(\"mkSimple::say1\");\n      indication.say1(v);\n   endmethod\n   \n   method Action say2(Bit#(16) a, Bit#(16) b);\n      if (verbose) $display(\"mkSimple::say2\");\n      indication.say2(a,b);\n   endmethod\n      \n   method Action say3(S1 v);\n      if (verbose) $display(\"mkSimple::say3\");\n      indication.say3(v);\n   endmethod\n   \n   method Action say4(S2 v);\n      if (verbose) $display(\"mkSimple::say4\");\n      indication.say4(v);\n   endmethod\n      \n   method Action say5(Bit#(32) a, Bit#(64) b, Bit#(32) c);\n      if (verbose) $display(\"mkSimple::say5\");\n      indication.say5(a, b, c);\n   endmethod\n\n   method Action say6(Bit#(32) a, Bit#(40) b, Bit#(32) c);\n      if (verbose) $display(\"mkSimple::say6\");\n      indication.say6(a, b, c);\n   endmethod\n\n   method Action say7(S3 v);\n      if (verbose) $display(\"mkSimple::say7\");\n      indication.say7(v);\n   endmethod\n\n   method Action say8(Vector#(128, Bit#(32)) v);\n      if (verbose) $display(\"mkSimple::say8\");\n      indication.say8(v);\n   endmethod\n\nendmodule\n"
  },
  {
    "path": "examples/zynqpcie/Top.bsv",
    "content": "/* Copyright (c) 2014 Quanta Research Cambridge, Inc\n *\n * Permission is hereby granted, free of charge, to any person obtaining a\n * copy of this software and associated documentation files (the \"Software\"),\n * to deal in the Software without restriction, including without limitation\n * the rights to use, copy, modify, merge, publish, distribute, sublicense,\n * and/or sell copies of the Software, and to permit persons to whom the\n * Software is furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n * DEALINGS IN THE SOFTWARE.\n */\n`include \"ConnectalProjectConfig.bsv\"\nimport Clocks::*;\nimport Vector::*;\nimport FIFO::*;\nimport Connectable::*;\nimport GetPutWithClocks::*;\nimport CtrlMux::*;\nimport Portal::*;\nimport ConnectalConfig::*;\nimport ConnectalMemTypes::*;\nimport PcieHost ::*;\n`ifndef SIMULATION\nimport PCIEWRAPPER          ::*;\nimport PcieEndpointX7       ::*;\nimport ConnectalXilinxCells ::*;\n`endif\nimport Simple::*;\nimport ZynqPcieTestRequest::*;\nimport ZynqPcieTestIndication::*;\nimport ZynqPcieTestIF::*;\nimport SimpleIF::*;\n\ntypedef enum {IfcNames_SimpleRequest, IfcNames_SimpleIndication, IfcNames_ZynqPcieTestRequest, IfcNames_ZynqPcieTestIndication} IfcNames deriving (Eq,Bits);\n\ninterface ZynqPcie;\n   (* prefix=\"PCIE\" *)\n   interface PciewrapPci_exp#(PcieLanes) pcie;\n   method Action pcie_sys_clk(Bit#(1) p, Bit#(1) n);\n   method Action sys_clk(Bit#(1) p, Bit#(1) n);\n   method Action pcie_sys_reset(Bit#(1) n);\n   interface Clock deleteme_unused_clockFoo;\n   interface Clock deleteme_unused_clockPortal;\n   interface Clock deleteme_unused_clock100mhz;\nendinterface\n\n//\n// This module is just to put a synthesis boundary around\n// mkPcieHostTop, which does not currently have one.  The Makefile\n// uses this line to synthesize this module into its own\n// netlist. We're not going to change it, so on subsequent rebuilds,\n// buildcache will use the previous synthesis result.\n//\n//    CONNECTALFLAGS += -P mkPcieHostTopSynth\n//\n(* synthesize *)\nmodule mkPcieHostTopSynth#(Clock pcie_sys_clk_p, Clock pcie_sys_clk_n, Clock sys_clk_p, Clock sys_clk_n, Reset pcie_sys_reset_n)(PcieHostTop);\n   (*hide*) let host <- mkPcieHostTop(pcie_sys_clk_p, pcie_sys_clk_n, sys_clk_p, sys_clk_n, pcie_sys_reset_n);\n   return host;\nendmodule\n\n//\n// This design exposes a PCIe interface via its \"pins\"\n//\nmodule mkConnectalTop(ConnectalTop);\n\n   Clock defaultClock <- exposeCurrentClock();\n   Reset defaultReset <- exposeCurrentReset();\n\n   // Clock laundering facility:\n   //\n   // Bluespec does have a way for exposed interfaces to be a source\n   // for clocks so we use B2C (bit to clock) to convert bits to\n   // clocks.\n   B2C1 b2c_pcie_sys_clk_p <- mkB2C1();\n   B2C1 b2c_pcie_sys_clk_n <- mkB2C1();\n   B2C b2c_pcie_sys_reset_n <- mkB2C();\n   B2C1 b2c_sys_clk_p <- mkB2C1();\n   B2C1 b2c_sys_clk_n <- mkB2C1();\n\n   //\n   // Instantiate a PcieHostTop, so that we can connect it to a set of portals.\n   //\n   PcieHostTop host <- mkPcieHostTopSynth(b2c_pcie_sys_clk_p.c, b2c_pcie_sys_clk_n.c, b2c_sys_clk_p.c, b2c_sys_clk_n.c, b2c_pcie_sys_reset_n.r);\n\n   // The PCIe portals and Zynq portals are in different clock domains, so synchronize bits that are provided to mkZynqPcieTest\n   SyncBitIfc#(Bit#(1)) resetBit <- mkSyncBit(b2c_pcie_sys_reset_n.c, b2c_pcie_sys_reset_n.r, defaultClock);\n   SyncBitIfc#(Bit#(1)) resetSeenBit <- mkSyncBit(b2c_pcie_sys_reset_n.c, b2c_pcie_sys_reset_n.r, defaultClock);\n   SyncBitIfc#(Bit#(1)) linkUpBit <- mkSyncBit(host.portalClock, host.portalReset, defaultClock);\n   // This register is in the PCIe portal clock domain\n   Reg#(Bit#(1)) resetSeenReg <- mkReg(0, clocked_by b2c_pcie_sys_reset_n.c, reset_by b2c_pcie_sys_reset_n.r);\n\n   // instantiate zynq-side user portals\n   ZynqPcieTestIndicationProxy zynqPcieTestIndicationProxy <- mkZynqPcieTestIndicationProxy(IfcNames_ZynqPcieTestIndication);\n   ZynqPcieTest zynqPcieTest <- mkZynqPcieTest(linkUpBit, resetBit, resetSeenBit, zynqPcieTestIndicationProxy.ifc);\n   ZynqPcieTestRequestWrapper zynqPcieTestRequestWrapper <- mkZynqPcieTestRequestWrapper(IfcNames_ZynqPcieTestRequest,zynqPcieTest.request);\n\n   // Connect the exposed BRAM client to the trace BRAM server in the PcieHost\n   mkConnectionWithClocks2(zynqPcieTest.traceBramClient, host.tpciehost.traceBramServer);\n\n   // send the value of the lnk_up signal from the PCIE endpoint to the Zynq portal clock domain\n   rule updateLinkBit;\n      linkUpBit.send(host.tep7.user.lnk_up());\n   endrule\n\n   // Construct the vector of zynq portals\n   Vector#(2,StdPortal) zynqPortals;\n   zynqPortals[0] = zynqPcieTestIndicationProxy.portalIfc;\n   zynqPortals[1] = zynqPcieTestRequestWrapper.portalIfc;\n   let ctrl_mux <- mkSlaveMux(zynqPortals);\n   \n   // LED values\n   // led0: toggles once a second as a board heartbeat\n   // led1: Indicates PCIE link is up\n   // led2: Indicates current value of the PCIE reset signal from the host\n   // led3: Indicates that a 0-to-1 transition was detected on the PCIE reset signal from the host\n   Reg#(Bit#(4)) ledsValue <- mkReg(5);\n   Reg#(Bit#(32)) remainingDuration <- mkReg(100000000);\n\n   rule updateLeds;\n      let duration = remainingDuration;\n      let bits = ledsValue;\n      bits[3] = resetSeenBit.read();\n      bits[2] = resetBit.read();\n      bits[1] = linkUpBit.read();\n      \n      if (duration == 0) begin\n\t bits[0] = ~bits[0];\n\t duration = 100000000;\n      end\n      else begin\n\t duration = duration - 1;\n      end\n      ledsValue <= bits;\n      remainingDuration <= duration;\n   endrule\n\n   //\n   // Instantiate Simple portals as the test case connected to the x86 host via PCIe\n   //\n   SimpleProxy simpleIndicationProxy <- mkSimpleProxy(IfcNames_SimpleIndication, clocked_by host.portalClock, reset_by host.portalReset);\n   Simple simpleRequest <- mkSimple(simpleIndicationProxy.ifc, clocked_by host.portalClock, reset_by host.portalReset);\n   SimpleWrapper simpleRequestWrapper <- mkSimpleWrapper(IfcNames_SimpleRequest,simpleRequest, clocked_by host.portalClock, reset_by host.portalReset);\n   \n   Vector#(2,StdPortal) pcieportals;\n   pcieportals[0] = simpleIndicationProxy.portalIfc;\n   pcieportals[1] = simpleRequestWrapper.portalIfc;\n   PhysMemSlave#(32,32) pcie_ctrl_mux <- mkSlaveMux(pcieportals, clocked_by host.portalClock, reset_by host.portalReset);\n   // manually connect the PCIe host PhysMemMaster to the pcie_ctrl_mux PhysMemSlave\n   mkConnection(host.tpciehost.master, pcie_ctrl_mux, clocked_by host.portalClock, reset_by host.portalReset);\n\n   // Construct the ZynqPcie interface\n   ZynqPcie zpcie = (interface ZynqPcie;\n\t\t     method Action pcie_sys_clk(Bit#(1) p, Bit#(1) n);\n\n\t\t        // This is a bit of sleight of hand. We depend\n\t\t        // on the way the bluespec compiler generates\n\t\t        // verilog for the following method invocation\n\t\t        // to connect the input clock signals via the\n\t\t        // B2C to the 100Mhz pcie system clock input\n\t\t        // of the PcieHost.\n\t\t\tb2c_pcie_sys_clk_p.inputclock(p);\n\t\t\tb2c_pcie_sys_clk_n.inputclock(n);\n\t\t     endmethod\n\t\t     method Action sys_clk(Bit#(1) p, Bit#(1) n);\n\t\t\t// same for the 200MHz system clock\n\t\t\tb2c_sys_clk_p.inputclock(p);\n\t\t\tb2c_sys_clk_n.inputclock(n);\n\t\t     endmethod\n\t\t     method Action pcie_sys_reset(Bit#(1) n);\n\t\t\tif (n == 1)\n\t\t\t   resetSeenReg <= 1;\n\t\t\tresetSeenBit.send(resetSeenReg);\n\t\t\tresetBit.send(n);\n\t\t\t// same for the reset\n\t\t\tb2c_pcie_sys_reset_n.inputreset(n);\n\t\t     endmethod\n\t\t     interface pcie = host.tep7.pcie;\n\t\t     // The Bluespec compiler requires that the clocks\n\t\t     // used by exported methods/pins also be\n\t\t     // exposed. Because of the b2c, some of the clock\n\t\t     // pins were not visible to the compiler, so we\n\t\t     // export them here.\n\t\t     //\n\t\t     // We do not have FPGA pins to which we want to\n\t\t     // connect them, so we rename them\n\t\t     // \"deleteme_unused_clock...\" so that the\n\t\t     // synthesis script will disconnect them from the\n\t\t     // ports of the toplevel netlist.\n\t\t     interface Clock deleteme_unused_clockFoo = b2c_pcie_sys_reset_n.c;\n\t\t     interface Clock deleteme_unused_clockPortal = host.portalClock;\n\t\t     interface Clock deleteme_unused_clock100mhz = host.tpci_clk_100mhz_buf;\n\t\t     endinterface);\n\n   // connect the standard LEDS interface\n   //LEDS ledsIF = (interface LEDS; method Bit#(LedsWidth) leds(); return truncate(ledsValue); endmethod endinterface);\n\n   // export the interfaces from the Zynq portals\n   interface interrupt = getInterruptVector(zynqPortals);\n   interface slave = ctrl_mux;\n   interface masters = nil;\n   //interface leds = ledsIF;\n   // expose the pcie interface as pins\n   interface pins = zpcie;\nendmodule : mkConnectalTop\n"
  },
  {
    "path": "examples/zynqpcie/ZynqPcieTestIF.bsv",
    "content": "\n// Copyright (c) 2014 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\nimport FIFO::*;\nimport Vector::*;\nimport Clocks::*;\nimport BRAM::*;\nimport PCIE::*;\nimport PcieTracer::*;\n\ninterface ZynqPcieTestRequest;\n   method Action getStatus(Bit#(32) v);\n   method Action getTrace(Bit#(32) offset);\nendinterface\ninterface ZynqPcieTestIndication;\n    method Action status(Bit#(32) v);\n    method Action trace(Vector#(6, Bit#(32)) offset);\nendinterface\n\ninterface ZynqPcieTest;\n   interface ZynqPcieTestRequest request;\n   interface BRAMClient#(Bit#(TAdd#(TlpTraceAddrSize,1)), TimestampedTlpData) traceBramClient;\nendinterface\n\nmodule mkZynqPcieTest#(SyncBitIfc#(Bit#(1)) lnk_up, SyncBitIfc#(Bit#(1)) resetBit, SyncBitIfc#(Bit#(1)) resetSeenBit, ZynqPcieTestIndication indication)(ZynqPcieTest);\n\n   FIFO#(BRAMRequest#(Bit#(TAdd#(TlpTraceAddrSize,1)), TimestampedTlpData)) requestFifo <- mkFIFO();\n   FIFO#(TimestampedTlpData) responseFifo <- mkFIFO();\n\n   rule respond;\n      let v <- toGet(responseFifo).get();\n      indication.trace(unpack(pack(v)));\n   endrule\n\n   interface ZynqPcieTestRequest request;\n      method Action getStatus(Bit#(32) v);\n\t indication.status(extend({lnk_up.read(), resetBit.read(), resetSeenBit.read()}));\n      endmethod\n      method Action getTrace(Bit#(32) v);\n\t requestFifo.enq(BRAMRequest {\n\t    write: False,\n\t    responseOnWrite: False,\n\t    address: truncate(v),\n\t    datain: unpack(0)\n\t });\n      endmethod\n   endinterface\n   interface BRAMClient traceBramClient;\n      interface Get request = fifoToGet(requestFifo);\n      interface Put response = fifoToPut(responseFifo);\n   endinterface\nendmodule\n"
  },
  {
    "path": "examples/zynqpcie/synth-ip.tcl",
    "content": "source board.tcl\nsource $connectaldir/scripts/connectal-synth-pcie.tcl\nset needspcie 1\nif $needspcie {\n    set pcieversion {3.0}\n    set maxlinkwidth {X8}\n    if {$boardname == {zc706}} {\n\tset maxlinkwidth {X4}\n    }\n    if {$boardname == {ac701}} {\n\tset maxlinkwidth {X4}\n    }\n    if {[version -short] == \"2013.2\"} {\n\tset pcieversion {2.1}\n    }\n    connectal_synth_ip pcie_7x $pcieversion pcie_7x_0 [list CONFIG.mode_selection {Advanced} CONFIG.ASPM_Optionality {true} CONFIG.Disable_Tx_ASPM_L0s {true} CONFIG.Buf_Opt_BMA {true} CONFIG.Bar0_64bit {true} CONFIG.Bar0_Size {16} CONFIG.Bar0_Scale {Kilobytes} CONFIG.Bar2_64bit {true} CONFIG.Bar2_Enabled {true} CONFIG.Bar2_Scale {Megabytes} CONFIG.Bar2_Size {1} CONFIG.Base_Class_Menu {Memory_controller} CONFIG.Device_ID {c100} CONFIG.IntX_Generation {false} CONFIG.MSI_Enabled {false} CONFIG.MSIx_Enabled {true} CONFIG.MSIx_PBA_Offset {1f0} CONFIG.MSIx_Table_Offset {200} CONFIG.MSIx_Table_Size {10} CONFIG.Maximum_Link_Width $maxlinkwidth CONFIG.Subsystem_ID {a705} CONFIG.Subsystem_Vendor_ID {1be7} CONFIG.Use_Class_Code_Lookup_Assistant {false} CONFIG.Vendor_ID {1be7} CONFIG.Trgt_Link_Speed {4'h2} CONFIG.Link_Speed {5.0_GT/s}]\n\n}\n"
  },
  {
    "path": "examples/zynqpcie/testsimple.cpp",
    "content": "/* Copyright (c) 2014 Quanta Research Cambridge, Inc\n *\n * Permission is hereby granted, free of charge, to any person obtaining a\n * copy of this software and associated documentation files (the \"Software\"),\n * to deal in the Software without restriction, including without limitation\n * the rights to use, copy, modify, merge, publish, distribute, sublicense,\n * and/or sell copies of the Software, and to permit persons to whom the\n * Software is furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n * DEALINGS IN THE SOFTWARE.\n */\n\n#include <stdio.h>\n#include <stdlib.h>\n#include <unistd.h>\n#include <assert.h>\n\n#include \"Simple.h\"\n#include \"GeneratedTypes.h\"\n\n\nint v1a = 42;\n\nint v2a = 2;\nint v2b = 4;\n\nS2 s2 = {7, 8, 9};\n\nS1 s1 = {3, 6};\n\nuint32_t v5a = 0x00000000;\nuint64_t v5b = 0xDEADBEEFFECAFECA;\nuint32_t v5c = 0x00000001;\n\nuint32_t v6a = 0xBBBBBBBB;\nuint64_t v6b = 0x000000EFFECAFECA;\nuint32_t v6c = 0xCCCCCCCC;\n\nuint32_t v7a = 0xDADADADA;\nE1 v7b = E1_E1Choice2;\nS3 s3 = { a: v7a, e1: v7b };\n\n\nclass Simple : public SimpleWrapper\n{  \npublic:\n  uint32_t cnt;\n  void incr_cnt(){\n    if (++cnt == 7)\n      exit(0);\n  }\n  virtual void say1(uint32_t a) {\n    fprintf(stderr, \"say1(%d)\\n\", a);\n    assert(a == v1a);\n    incr_cnt();\n  }\n  virtual void say2(uint32_t a, uint32_t b) {\n    fprintf(stderr, \"say2(%d %d)\\n\", a, b);\n    assert(a == v2a);\n    assert(b == v2b);\n    incr_cnt();\n  }\n  virtual void say3(S1 s){\n    fprintf(stderr, \"say3(S1{a:%d,b:%d})\\n\", s.a, s.b);\n    assert(s.a == s1.a);\n    assert(s.b == s1.b);\n    incr_cnt();\n  }\n  virtual void say4(S2 s){\n    fprintf(stderr, \"say4(S2{a:%d,b:%d,c:%d})\\n\", s.a,s.b,s.c);\n    assert(s.a == s2.a);\n    assert(s.b == s2.b);\n    assert(s.c == s2.c);\n    incr_cnt();\n  }\n  virtual void say5(uint32_t a, uint64_t b, uint32_t c) {\n    fprintf(stderr, \"say5(%08x, %016llx, %08x)\\n\", a, (long long)b, c);\n    assert(a == v5a);\n    assert(b == v5b);\n    assert(c == v5c);\n    incr_cnt();\n  }\n  virtual void say6(uint32_t a, uint64_t b, uint32_t c) {\n    fprintf(stderr, \"say6(%08x, %016llx, %08x)\\n\", a, (long long)b, c);\n    assert(a == v6a);\n    assert(b == v6b);\n    assert(c == v6c);\n    incr_cnt();\n  }\n  virtual void say7(S3 v) {\n    fprintf(stderr, \"say7(%08x, %08x)\\n\", v.a, v.e1);\n    assert(v.a == v7a);\n    assert(v.e1 == v7b);\n    incr_cnt();\n  }\n  virtual void say8 ( const bsvvector_Luint32_t_L128 v ) {\n    fprintf(stderr, \"say8\\n\");\n    for (int i = 0; i < 128; i++)\n        fprintf(stderr, \"    [%d] = 0x%x\\n\", i, v[i]);\n    incr_cnt();\n  }\n  Simple(unsigned int id) : SimpleWrapper(id), cnt(0){}\n};\n\n\n\nint main(int argc, const char **argv)\n{\n  Simple *indication = new Simple(IfcNames_SimpleIndication);\n  SimpleProxy *device = new SimpleProxy(IfcNames_SimpleRequest);\n  device->pint.busyType = BUSY_SPIN;   /* spin until request portal 'notFull' */\n\n  fprintf(stderr, \"Main::calling say1(%d)\\n\", v1a);\n  device->say1(v1a);  \n  fprintf(stderr, \"Main::calling say2(%d, %d)\\n\", v2a,v2b);\n  device->say2(v2a,v2b);\n  fprintf(stderr, \"Main::calling say3(S1{a:%d,b:%d})\\n\", s1.a,s1.b);\n  device->say3(s1);\n  fprintf(stderr, \"Main::calling say4(S2{a:%d,b:%d,c:%d})\\n\", s2.a,s2.b,s2.c);\n  device->say4(s2);\n  fprintf(stderr, \"Main::calling say5(%08x, %016llx, %08x)\\n\", v5a, (long long)v5b, v5c);\n  device->say5(v5a, v5b, v5c);  \n  fprintf(stderr, \"Main::calling say6(%08x, %016llx, %08x)\\n\", v6a, (long long)v6b, v6c);\n  device->say6(v6a, v6b, v6c);  \n  fprintf(stderr, \"Main::calling say7(%08x, %08x)\\n\", s3.a, s3.e1);\n  device->say7(s3);  \n  bsvvector_Luint32_t_L128 vect;\n  for (int i = 0; i < 128; i++)\n    vect[i] = -i*32;\n  fprintf(stderr, \"Main::calling say8\\n\");\n  device->say8(vect);  \n\n  fprintf(stderr, \"Main::about to go to sleep\\n\");\n  while(true){sleep(2);}\n}\n"
  },
  {
    "path": "examples/zynqpcie/testzynqpcie.cpp",
    "content": "/* Copyright (c) 2014 Quanta Research Cambridge, Inc\n *\n * Permission is hereby granted, free of charge, to any person obtaining a\n * copy of this software and associated documentation files (the \"Software\"),\n * to deal in the Software without restriction, including without limitation\n * the rights to use, copy, modify, merge, publish, distribute, sublicense,\n * and/or sell copies of the Software, and to permit persons to whom the\n * Software is furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n * DEALINGS IN THE SOFTWARE.\n */\n\n#include <stdio.h>\n#include <stdlib.h>\n#include <unistd.h>\n#include <assert.h>\n\n#include \"ZynqPcieTestIndication.h\"\n#include \"ZynqPcieTestRequest.h\"\n#include \"GeneratedTypes.h\"\n\n\nclass ZynqPcieTestIndication : public ZynqPcieTestIndicationWrapper {\npublic:\n    ZynqPcieTestIndication(int id, PortalPoller *poller = 0) : ZynqPcieTestIndicationWrapper(id, poller) {\n    };\n    ZynqPcieTestIndication(int id, PortalTransportFunctions *item, void *param, PortalPoller *poller = 0) : ZynqPcieTestIndicationWrapper(id, item, param, poller) {\n    };\n  virtual void status ( const uint32_t v ) {\n\tfprintf(stderr, \"ZynqPcieTestIndicationWrapper.status v=%x\\n\", v);\n    }\n  virtual void trace ( const uint32_t *v ) {\n      fprintf(stderr, \"ZynqPcieTestIndicationWrapper.trace %08x %08x %08x %08x %08x %08x\\n\", v[0], v[1], v[2], v[3], v[4], v[5]);\n  }\n};\n\n\nint main(int argc, const char **argv)\n{\n  ZynqPcieTestIndication *indication = new ZynqPcieTestIndication(IfcNames_ZynqPcieTestIndication);\n  ZynqPcieTestRequestProxy *device = new ZynqPcieTestRequestProxy(IfcNames_ZynqPcieTestRequest);\n  device->pint.busyType = BUSY_SPIN;   /* spin until request portal 'notFull' */\n\n  for (int i = 0; i < 2; i++) {\n      device->getStatus(0);\n      sleep(2);\n  }\n  for (int i = 0; i < 100; i++) {\n      device->getTrace(i);\n      sleep(1);\n  }\n}\n\n"
  },
  {
    "path": "examples/zynqpcie/zynqpcie.json",
    "content": "{\n    \"*PCIE_txp[0]\": {\n\t\"PIO_DIRECTION\": \"OUTPUT\",\n\t\"pcie\": \"PCIE_tx0_p\"\n    },\n    \"*PCIE_txn[0]\": {\n\t\"PIO_DIRECTION\": \"OUTPUT\",\n\t\"pcie\": \"PCIE_tx0_n\"\n    },\n    \"*PCIE_txp[1]\": {\n\t\"PIO_DIRECTION\": \"OUTPUT\",\n\t\"pcie\": \"PCIE_tx1_p\"\n    },\n    \"*PCIE_txn[1]\": {\n\t\"PIO_DIRECTION\": \"OUTPUT\",\n\t\"pcie\": \"PCIE_tx1_n\"\n    },\n    \"*PCIE_txp[1]\": {\n\t\"PIO_DIRECTION\": \"OUTPUT\",\n\t\"pcie\": \"PCIE_tx1_p\"\n    },\n    \"*PCIE_txn[2]\": {\n\t\"PIO_DIRECTION\": \"OUTPUT\",\n\t\"pcie\": \"PCIE_tx2_n\"\n    },\n    \"*PCIE_txp[3]\": {\n\t\"PIO_DIRECTION\": \"OUTPUT\",\n\t\"pcie\": \"PCIE_tx3_p\"\n    },\n    \"*PCIE_txn[3]\": {\n\t\"PIO_DIRECTION\": \"OUTPUT\",\n\t\"pcie\": \"PCIE_tx3_n\"\n    },\n    \"*PCIE_rxp[0]\": {\n\t\"PIO_DIRECTION\": \"INPUT\",\n\t\"pcie\": \"PCIE_rx0_n\"\n    },\n    \"*PCIE_rxn[0]\": {\n\t\"PIO_DIRECTION\": \"INPUT\",\n\t\"pcie\": \"PCIE_rx0_n\"\n    },\n    \"*PCIE_rxp[1]\": {\n\t\"PIO_DIRECTION\": \"INPUT\",\n\t\"pcie\": \"PCIE_rx1_n\"\n    },\n    \"*PCIE_rxn[1]\": {\n\t\"PIO_DIRECTION\": \"INPUT\",\n\t\"pcie\": \"PCIE_rx1_n\"\n    },\n    \"*PCIE_rxp[2]\": {\n\t\"PIO_DIRECTION\": \"INPUT\",\n\t\"pcie\": \"PCIE_rx2_n\"\n    },\n    \"*PCIE_rxn[2]\": {\n\t\"PIO_DIRECTION\": \"INPUT\",\n\t\"pcie\": \"PCIE_rx2_n\"\n    },\n    \"*PCIE_rxp[3]\": {\n\t\"PIO_DIRECTION\": \"INPUT\",\n\t\"pcie\": \"PCIE_rx3_n\"\n    },\n    \"*PCIE_rxn[3]\": {\n\t\"PIO_DIRECTION\": \"INPUT\",\n\t\"pcie\": \"PCIE_rx3_n\"\n    },\n    \"pcie_sys_clk_p\": {\n\t\"PIO_DIRECTION\": \"INPUT\",\n\t\"pcie\": \"PCIE_clk_q0_p\"\n    },\n    \"pcie_sys_clk_n\": {\n\t\"PIO_DIRECTION\": \"INPUT\",\n\t\"pcie\": \"PCIE_clk_q0_n\"\n    },\n    \"pcie_sys_reset_n\": {\n\t\"PIO_DIRECTION\": \"INPUT\",\n\t\"pcie\": \"PCIE_perst\"\n    }\n}"
  },
  {
    "path": "generated/altera/ALTERA_DDR3_WRAPPER.bsv",
    "content": "\n/*\n   ./importbvi.py\n   -o\n   ALTERA_DDR3_WRAPPER.bsv\n   -I\n   AvalonDdr3\n   -P\n   AvalonDdr3\n   -c\n   pll_ref_clk\n   -r\n   global_reset_n\n   -r\n   soft_reset_n\n   -c\n   afi_clk\n   -c\n   afi_half_clk\n   -r\n   afi_reset_n\n   -r\n   afi_reset_export_n\n   -f\n   mem\n   -f\n   avl\n   -f\n   status\n   -f\n   oct\n   -f\n   pll\n   /home/hwang/dev/connectal/out/de5/synthesis/altera_mem_if_ddr3_emif_wrapper/altera_mem_if_ddr3_emif_wrapper.v\n*/\n\nimport Clocks::*;\nimport DefaultValue::*;\nimport XilinxCells::*;\nimport GetPut::*;\nimport AxiBits::*;\nimport Vector::*;\n\n(* always_ready, always_enabled *)\ninterface Avalonddr3Afi;\n    interface Clock     clk;\n    interface Clock     half_clk;\n    method Reset     reset_export_n();\n    method Reset     reset_n();\nendinterface\n(* always_ready, always_enabled *)\ninterface Avalonddr3Avl;\n    method Action      addr(Bit#(25) v);\n    method Action      be(Bit#(64) v);\n    method Action      burstbegin(Bit#(1) v);\n    method Bit#(512)     rdata();\n    method Bit#(1)     rdata_valid();\n    method Action      read_req(Bit#(1) v);\n    method Bit#(1)     wait_request();\n    method Action      size(Bit#(3) v);\n    method Action      wdata(Bit#(512) v);\n    method Action      write_req(Bit#(1) v);\nendinterface\n(* always_ready, always_enabled *)\ninterface Avalonddr3status;\n    method Bit#(1)     cal_fail();\n    method Bit#(1)     cal_success();\n    method Bit#(1)     init_done();\nendinterface\n(* always_ready, always_enabled *)\ninterface Avalonddr3Mem;\n    method Bit#(15)     a();\n    method Bit#(3)     ba();\n    method Bit#(1)     cas_n();\n    method Vector#(1, Bit#(1))     ck();\n    method Bit#(1)     ck_n();\n    method Bit#(1)     cke();\n    method Bit#(1)     cs_n();\n    method Bit#(8)     dm();\n    interface Inout#(Bit#(64))     dq;\n    interface Inout#(Bit#(8))     dqs;\n    interface Inout#(Bit#(8))     dqs_n;\n    method Bit#(1)     odt();\n    method Bit#(1)     ras_n();\n    method Bit#(1)     reset_n();\n    method Bit#(1)     we_n();\nendinterface\n(* always_ready, always_enabled *)\ninterface Avalonddr3Oct;\n    (* prefix=\"\" *)\n    method Action      rzqin( (* port=\"rzq_4\" *) Bit#(1) v);\nendinterface\n(* always_ready, always_enabled *)\ninterface Avalonddr3Pll;\n    method Bit#(1)     addr_cmd_clk();\n    method Bit#(1)     avl_clk();\n    method Bit#(1)     c2p_write_clk();\n    method Bit#(1)     config_clk();\n    method Bit#(1)     hr_clk();\n    method Bit#(1)     locked();\n    method Bit#(1)     mem_clk();\n    method Bit#(1)     p2c_read_clk();\n    method Bit#(1)     write_clk();\n    method Bit#(1)     write_clk_pre_phy_clk();\nendinterface\n(* always_ready, always_enabled *)\ninterface AvalonDdr3;\n    interface Avalonddr3Afi     afi;\n    interface Avalonddr3Avl     avl;\n    interface Avalonddr3status  status;\n    interface Avalonddr3Mem     mem;\n    interface Avalonddr3Oct     oct;\n    interface Avalonddr3Pll     pll;\nendinterface\nimport \"BVI\" altera_mem_if_ddr3_emif_wrapper =\nmodule mkAvalonDdr3#(Clock pll_ref_clk, Reset global_reset_n, Reset soft_reset_n)(AvalonDdr3);\n    default_clock clk();\n    default_reset rst();\n        input_reset global_reset_n(global_reset_n) = global_reset_n;\n        input_clock pll_ref_clk(pll_ref_clk) = pll_ref_clk;\n        input_reset soft_reset_n(soft_reset_n) = soft_reset_n;\n    interface Avalonddr3Afi     afi;\n        output_clock clk(afi_clk);\n        output_clock half_clk(afi_half_clk);\n        output_reset reset_export_n(afi_reset_export_n);\n        output_reset reset_n(afi_reset_n);\n    endinterface\n    interface Avalonddr3Avl     avl;\n        method addr(avl_addr) enable((*inhigh*) EN_avl_addr);\n        method be(avl_be) enable((*inhigh*) EN_avl_be);\n        method burstbegin(avl_burstbegin) enable((*inhigh*) EN_avl_burstbegin);\n        method avl_rdata rdata();\n        method avl_rdata_valid rdata_valid();\n        method read_req(avl_read_req) enable((*inhigh*) EN_avl_read_req);\n        method avl_ready wait_request();\n        method size(avl_size) enable((*inhigh*) EN_avl_size);\n        method wdata(avl_wdata) enable((*inhigh*) EN_avl_wdata);\n        method write_req(avl_write_req) enable((*inhigh*) EN_avl_write_req);\n    endinterface\n    interface Avalonddr3status     status;\n        method status_cal_fail cal_fail();\n        method status_cal_success cal_success();\n        method status_init_done init_done();\n    endinterface\n    interface Avalonddr3Mem     mem;\n        method mem_a a();\n        method mem_ba ba();\n        method mem_cas_n cas_n();\n        method mem_ck ck();\n        method mem_ck_n ck_n();\n        method mem_cke cke();\n        method mem_cs_n cs_n();\n        method mem_dm dm();\n        ifc_inout dq(mem_dq);\n        ifc_inout dqs(mem_dqs);\n        ifc_inout dqs_n(mem_dqs_n);\n        method mem_odt odt();\n        method mem_ras_n ras_n();\n        method mem_reset_n reset_n();\n        method mem_we_n we_n();\n    endinterface\n    interface Avalonddr3Oct     oct;\n        method rzqin(oct_rzqin) enable((*inhigh*) EN_oct_rzqin);\n    endinterface\n    interface Avalonddr3Pll     pll;\n        method pll_addr_cmd_clk addr_cmd_clk() clocked_by (pll_ref_clk);\n        method pll_avl_clk avl_clk() clocked_by (pll_ref_clk);\n        method pll_c2p_write_clk c2p_write_clk() clocked_by (pll_ref_clk);\n        method pll_config_clk config_clk() clocked_by (pll_ref_clk);\n        method pll_hr_clk hr_clk() clocked_by (pll_ref_clk);\n        method pll_locked locked() clocked_by (pll_ref_clk);\n        method pll_mem_clk mem_clk() clocked_by (pll_ref_clk);\n        method pll_p2c_read_clk p2c_read_clk() clocked_by (pll_ref_clk);\n        method pll_write_clk write_clk() clocked_by (pll_ref_clk);\n        method pll_write_clk_pre_phy_clk write_clk_pre_phy_clk() clocked_by (pll_ref_clk);\n    endinterface\n    schedule (avl.addr, avl.be, avl.burstbegin, avl.rdata, avl.rdata_valid, avl.read_req, avl.wait_request, avl.size, avl.wdata, avl.write_req, status.cal_fail, status.cal_success, status.init_done, mem.a, mem.ba, mem.cas_n, mem.ck, mem.ck_n, mem.cke, mem.cs_n, mem.dm, mem.odt, mem.ras_n, mem.reset_n, mem.we_n, oct.rzqin, pll.addr_cmd_clk, pll.avl_clk, pll.c2p_write_clk, pll.config_clk, pll.hr_clk, pll.locked, pll.mem_clk, pll.p2c_read_clk, pll.write_clk, pll.write_clk_pre_phy_clk) CF (avl.addr, avl.be, avl.burstbegin, avl.rdata, avl.rdata_valid, avl.read_req, avl.wait_request, avl.size, avl.wdata, avl.write_req, status.cal_fail, status.cal_success, status.init_done, mem.a, mem.ba, mem.cas_n, mem.ck, mem.ck_n, mem.cke, mem.cs_n, mem.dm, mem.odt, mem.ras_n, mem.reset_n, mem.we_n, oct.rzqin, pll.addr_cmd_clk, pll.avl_clk, pll.c2p_write_clk, pll.config_clk, pll.hr_clk, pll.locked, pll.mem_clk, pll.p2c_read_clk, pll.write_clk, pll.write_clk_pre_phy_clk);\nendmodule\n"
  },
  {
    "path": "generated/altera/ALTERA_ETH_PMA_RECONFIG_WRAPPER.bsv",
    "content": "\n/*\n   ./importbvi.py\n   -o\n   ALTERA_ETH_PMA_RECONFIG_WRAPPER.bsv\n   -I\n   EthXcvrReconfigWrap\n   -P\n   EthXcvrReconfigWrap\n   -c\n   mgmt_clk_clk\n   -r\n   mgmt_rst_reset\n   -f\n   reconfig\n   ../../out/de5/synthesis/altera_xgbe_pma_reconfig_wrapper.v\n*/\n\nimport Clocks::*;\nimport DefaultValue::*;\nimport XilinxCells::*;\nimport GetPut::*;\n\n(* always_ready, always_enabled *)\n(* always_ready, always_enabled *)\ninterface EthxcvrreconfigwrapReconfig;\n    method Bit#(1)     busy();\n    method Action      from_xcvr(Bit#(368) v);\n    method Action      mgmt_address(Bit#(7) v);\n    method Action      mgmt_read(Bit#(1) v);\n    method Bit#(32)     mgmt_readdata();\n    method Bit#(1)     mgmt_waitrequest();\n    method Action      mgmt_write(Bit#(1) v);\n    method Action      mgmt_writedata(Bit#(32) v);\n    method Bit#(560)     to_xcvr();\nendinterface\n(* always_ready, always_enabled *)\ninterface EthXcvrReconfigWrap;\n    interface EthxcvrreconfigwrapReconfig     reconfig;\nendinterface\nimport \"BVI\" altera_xgbe_pma_reconfig_wrapper =\nmodule mkEthXcvrReconfigWrap#(Clock mgmt_clk_clk, Reset mgmt_clk_clk_reset, Reset mgmt_rst_reset)(EthXcvrReconfigWrap);\n    default_clock clk();\n    default_reset rst();\n        input_clock mgmt_clk_clk(mgmt_clk_clk) = mgmt_clk_clk;\n        input_reset mgmt_clk_clk_reset() = mgmt_clk_clk_reset; /* from clock*/\n        input_reset mgmt_rst_reset(mgmt_rst_reset) = mgmt_rst_reset;\n    interface EthxcvrreconfigwrapReconfig     reconfig;\n        method reconfig_busy busy();\n        method from_xcvr(reconfig_from_xcvr) enable((*inhigh*) EN_reconfig_from_xcvr);\n        method mgmt_address(reconfig_mgmt_address) enable((*inhigh*) EN_reconfig_mgmt_address);\n        method mgmt_read(reconfig_mgmt_read) enable((*inhigh*) EN_reconfig_mgmt_read);\n        method reconfig_mgmt_readdata mgmt_readdata();\n        method reconfig_mgmt_waitrequest mgmt_waitrequest();\n        method mgmt_write(reconfig_mgmt_write) enable((*inhigh*) EN_reconfig_mgmt_write);\n        method mgmt_writedata(reconfig_mgmt_writedata) enable((*inhigh*) EN_reconfig_mgmt_writedata);\n        method reconfig_to_xcvr to_xcvr();\n    endinterface\n    schedule (reconfig.busy, reconfig.from_xcvr, reconfig.mgmt_address, reconfig.mgmt_read, reconfig.mgmt_readdata, reconfig.mgmt_waitrequest, reconfig.mgmt_write, reconfig.mgmt_writedata, reconfig.to_xcvr) CF (reconfig.busy, reconfig.from_xcvr, reconfig.mgmt_address, reconfig.mgmt_read, reconfig.mgmt_readdata, reconfig.mgmt_waitrequest, reconfig.mgmt_write, reconfig.mgmt_writedata, reconfig.to_xcvr);\nendmodule\n"
  },
  {
    "path": "generated/altera/ALTERA_ETH_PMA_RESET_CONTROL_WRAPPER.bsv",
    "content": "\n/*\n   ./importbvi.py\n   -o\n   ALTERA_ETH_PMA_RESET_CONTROL_WRAPPER.bsv\n   -I\n   EthXcvrResetWrap\n   -P\n   EthXcvrResetWrap\n   -c\n   clock\n   -r\n   reset\n   -f\n   pll\n   -f\n   rx_r\n   -f\n   tx_r\n   -f\n   tx\n   -f\n   rx\n   ../../out/de5/synthesis/altera_xcvr_reset_control_wrapper.v\n*/\n\nimport Clocks::*;\nimport DefaultValue::*;\nimport XilinxCells::*;\nimport GetPut::*;\n\n(* always_ready, always_enabled *)\ninterface EthxcvrresetwrapPll;\n    method Action      locked(Bit#(4) v);\n    method Bit#(4)     powerdown();\n    method Action      select(Bit#(2) v);\nendinterface\n(* always_ready, always_enabled *)\ninterface EthxcvrresetwrapRx;\n    method Bit#(4)     analogreset();\n    method Action      cal_busy(Bit#(4) v);\n    method Bit#(4)     digitalreset();\n    method Action      is_lockedtodata(Bit#(4) v);\nendinterface\n(* always_ready, always_enabled *)\ninterface EthxcvrresetwrapRx_r;\n    method Bit#(4)     eady();\nendinterface\n(* always_ready, always_enabled *)\ninterface EthxcvrresetwrapTx;\n    method Bit#(4)     analogreset();\n    method Action      cal_busy(Bit#(4) v);\n    method Bit#(4)     digitalreset();\nendinterface\n(* always_ready, always_enabled *)\ninterface EthxcvrresetwrapTx_r;\n    method Bit#(4)     eady();\nendinterface\n(* always_ready, always_enabled *)\ninterface EthXcvrResetWrap;\n    interface EthxcvrresetwrapPll     pll;\n    interface EthxcvrresetwrapRx     rx;\n    interface EthxcvrresetwrapRx_r     rx_r;\n    interface EthxcvrresetwrapTx     tx;\n    interface EthxcvrresetwrapTx_r     tx_r;\nendinterface\nimport \"BVI\" altera_xcvr_reset_control_wrapper =\nmodule mkEthXcvrResetWrap#(Clock clock, Reset clock_reset, Reset reset)(EthXcvrResetWrap);\n    default_clock clk();\n    default_reset rst();\n    input_clock clock(clock) = clock;\n    input_reset clock_reset() = clock_reset; /* from clock*/\n    input_reset reset(reset) = reset;\n    interface EthxcvrresetwrapPll     pll;\n        method locked(pll_locked) enable((*inhigh*) EN_pll_locked);\n        method pll_powerdown powerdown();\n        method select(pll_select) enable((*inhigh*) EN_pll_select);\n    endinterface\n    interface EthxcvrresetwrapRx     rx;\n        method rx_analogreset analogreset();\n        method cal_busy(rx_cal_busy) enable((*inhigh*) EN_rx_cal_busy);\n        method rx_digitalreset digitalreset();\n        method is_lockedtodata(rx_is_lockedtodata) enable((*inhigh*) EN_rx_is_lockedtodata);\n    endinterface\n    interface EthxcvrresetwrapRx_r     rx_r;\n        method rx_ready eady();\n    endinterface\n    interface EthxcvrresetwrapTx     tx;\n        method tx_analogreset analogreset();\n        method cal_busy(tx_cal_busy) enable((*inhigh*) EN_tx_cal_busy);\n        method tx_digitalreset digitalreset();\n    endinterface\n    interface EthxcvrresetwrapTx_r     tx_r;\n        method tx_ready eady();\n    endinterface\n    schedule (pll.locked, pll.powerdown, pll.select, rx.analogreset, rx.cal_busy, rx.digitalreset, rx.is_lockedtodata, rx_r.eady, tx.analogreset, tx.cal_busy, tx.digitalreset, tx_r.eady) CF (pll.locked, pll.powerdown, pll.select, rx.analogreset, rx.cal_busy, rx.digitalreset, rx.is_lockedtodata, rx_r.eady, tx.analogreset, tx.cal_busy, tx.digitalreset, tx_r.eady);\nendmodule\n"
  },
  {
    "path": "generated/altera/ALTERA_ETH_PMA_WRAPPER.bsv",
    "content": "\n/*\n   ./importbvi.py\n   -o\n   ALTERA_ETH_PMA_WRAPPER.bsv\n   -I\n   EthXcvrWrap\n   -P\n   EthXcvrWrap\n   -f\n   pll\n   -f\n   tx\n   -f\n   rx\n   -f\n   reconfig\n   ../../out/de5/synthesis/altera_xcvr_native_sv_wrapper.v\n*/\n\nimport Clocks::*;\nimport DefaultValue::*;\nimport XilinxCells::*;\nimport GetPut::*;\n\n(* always_ready, always_enabled *)\ninterface EthxcvrwrapPll;\n    method Bit#(4)     locked();\n    method Action      powerdown(Bit#(4) v);\nendinterface\n(* always_ready, always_enabled *)\ninterface EthxcvrwrapReconfig;\n    method Bit#(368)     from_xcvr();\n    method Action      to_xcvr(Bit#(560) v);\nendinterface\n(* always_ready, always_enabled *)\ninterface EthxcvrwrapRx;\n    method Action      analogreset(Bit#(4) v);\n    method Bit#(4)     cal_busy();\n    method Action      cdr_refclk(Bit#(1) v);\n    method Action      digitalreset(Bit#(4) v);\n    method Bit#(4)     is_lockedtodata();\n    method Bit#(4)     is_lockedtoref();\n    method Bit#(4)     pma_clkout();\n    method Bit#(160)     pma_parallel_data();\n    method Action      serial_data(Bit#(4) v);\n    method Action      seriallpbken(Bit#(4) v);\nendinterface\n(* always_ready, always_enabled *)\ninterface EthxcvrwrapTx;\n    method Action      analogreset(Bit#(4) v);\n    method Bit#(4)     cal_busy();\n    method Action      digitalreset(Bit#(4) v);\n    method Action      pll_refclk(Bit#(1) v);\n    method Bit#(4)     pma_clkout();\n    method Action      pma_parallel_data(Bit#(160) v);\n    method Bit#(4)     serial_data();\nendinterface\n(* always_ready, always_enabled *)\ninterface EthxcvrwrapUnused;\n    method Bit#(160)     rx_pma_parallel_data();\n    method Action      tx_pma_parallel_data(Bit#(160) v);\nendinterface\n(* always_ready, always_enabled *)\ninterface EthXcvrWrap;\n    interface EthxcvrwrapPll     pll;\n    interface EthxcvrwrapReconfig     reconfig;\n    interface EthxcvrwrapRx     rx;\n    interface EthxcvrwrapTx     tx;\n    interface EthxcvrwrapUnused     unused;\nendinterface\nimport \"BVI\" altera_xcvr_native_sv_wrapper =\nmodule mkEthXcvrWrap(EthXcvrWrap);\n    default_clock clk();\n    default_reset rst();\n    interface EthxcvrwrapPll     pll;\n        method pll_locked locked();\n        method powerdown(pll_powerdown) enable((*inhigh*) EN_pll_powerdown);\n    endinterface\n    interface EthxcvrwrapReconfig     reconfig;\n        method reconfig_from_xcvr from_xcvr();\n        method to_xcvr(reconfig_to_xcvr) enable((*inhigh*) EN_reconfig_to_xcvr);\n    endinterface\n    interface EthxcvrwrapRx     rx;\n        method analogreset(rx_analogreset) enable((*inhigh*) EN_rx_analogreset);\n        method rx_cal_busy cal_busy();\n        method cdr_refclk(rx_cdr_refclk) enable((*inhigh*) EN_rx_cdr_refclk);\n        method digitalreset(rx_digitalreset) enable((*inhigh*) EN_rx_digitalreset);\n        method rx_is_lockedtodata is_lockedtodata();\n        method rx_is_lockedtoref is_lockedtoref();\n        method rx_pma_clkout pma_clkout();\n        method rx_pma_parallel_data pma_parallel_data();\n        method serial_data(rx_serial_data) enable((*inhigh*) EN_rx_serial_data);\n        method seriallpbken(rx_seriallpbken) enable((*inhigh*) EN_rx_seriallpbken);\n    endinterface\n    interface EthxcvrwrapTx     tx;\n        method analogreset(tx_analogreset) enable((*inhigh*) EN_tx_analogreset);\n        method tx_cal_busy cal_busy();\n        method digitalreset(tx_digitalreset) enable((*inhigh*) EN_tx_digitalreset);\n        method pll_refclk(tx_pll_refclk) enable((*inhigh*) EN_tx_pll_refclk);\n        method tx_pma_clkout pma_clkout();\n        method pma_parallel_data(tx_pma_parallel_data) enable((*inhigh*) EN_tx_pma_parallel_data);\n        method tx_serial_data serial_data();\n    endinterface\n    interface EthxcvrwrapUnused     unused;\n        method unused_rx_pma_parallel_data rx_pma_parallel_data();\n        method tx_pma_parallel_data(unused_tx_pma_parallel_data) enable((*inhigh*) EN_unused_tx_pma_parallel_data);\n    endinterface\n    schedule (pll.locked, pll.powerdown, reconfig.from_xcvr, reconfig.to_xcvr, rx.analogreset, rx.cal_busy, rx.cdr_refclk, rx.digitalreset, rx.is_lockedtodata, rx.is_lockedtoref, rx.pma_clkout, rx.pma_parallel_data, rx.serial_data, rx.seriallpbken, tx.analogreset, tx.cal_busy, tx.digitalreset, tx.pll_refclk, tx.pma_clkout, tx.pma_parallel_data, tx.serial_data, unused.rx_pma_parallel_data, unused.tx_pma_parallel_data) CF (pll.locked, pll.powerdown, reconfig.from_xcvr, reconfig.to_xcvr, rx.analogreset, rx.cal_busy, rx.cdr_refclk, rx.digitalreset, rx.is_lockedtodata, rx.is_lockedtoref, rx.pma_clkout, rx.pma_parallel_data, rx.serial_data, rx.seriallpbken, tx.analogreset, tx.cal_busy, tx.digitalreset, tx.pll_refclk, tx.pma_clkout, tx.pma_parallel_data, tx.serial_data, unused.rx_pma_parallel_data, unused.tx_pma_parallel_data);\nendmodule\n"
  },
  {
    "path": "generated/altera/ALTERA_PCIE_ED_WRAPPER.bsv",
    "content": "\n/*\n   ./importbvi.py\n   -o\n   ALTERA_PCIE_ED_WRAPPER.bsv\n   -I\n   PcieEdWrap\n   -P\n   PcieEdWrap\n   -c\n   coreclkout_hip\n   -c\n   pld_clk_hip\n   -f\n   serdes\n   -f\n   reset\n   -f\n   pld\n   -f\n   dl\n   -f\n   ev128\n   -f\n   ev1\n   -f\n   hotrst\n   -f\n   l2\n   -f\n   current\n   -f\n   derr\n   -f\n   lane\n   -f\n   ltssm\n   -f\n   reconfig\n   -f\n   int_s\n   -f\n   aer\n   -f\n   pex\n   -f\n   serr\n   -f\n   cpl\n   -f\n   tl\n   -f\n   pm_e\n   -f\n   pme\n   -f\n   pm\n   -f\n   tx_s\n   -f\n   rx_s\n   -f\n   tx_cred\n   -f\n   tx_par\n   -f\n   rx_par\n   -f\n   cfg_par\n   ../../out/de5/synthesis/altera_pcie_hip_ast_ed.v\n*/\n\nimport Clocks::*;\nimport DefaultValue::*;\nimport XilinxCells::*;\nimport GetPut::*;\n\n(* always_ready, always_enabled *)\ninterface PcieedwrapApp;\n    method Action      int_ack(Bit#(1) v);\n    method Bit#(1)     int_sts();\n    method Action      msi_ack(Bit#(1) v);\n    method Bit#(5)     msi_num();\n    method Bit#(1)     msi_req();\n    method Bit#(3)     msi_tc();\nendinterface\n(* always_ready, always_enabled *)\ninterface PcieedwrapCfg_par;\n    method Action      err(Bit#(1) v);\n    method Bit#(1)     err_drv();\nendinterface\n(* always_ready, always_enabled *)\n(* always_ready, always_enabled *)\ninterface PcieedwrapCpl;\n    method Bit#(7)     err();\n    method Bit#(1)     pending();\nendinterface\n(* always_ready, always_enabled *)\ninterface PcieedwrapDerr;\n    method Action      cor_ext_rcv(Bit#(1) v);\n    method Bit#(1)     cor_ext_rcv_drv();\n    method Action      cor_ext_rpl(Bit#(1) v);\n    method Bit#(1)     cor_ext_rpl_drv();\n    method Action      rpl(Bit#(1) v);\n    method Bit#(1)     rpl_drv();\nendinterface\n(* always_ready, always_enabled *)\ninterface PcieedwrapDl;\n    method Action      up(Bit#(1) v);\n    method Bit#(1)     up_drv();\n    method Action      up_exit(Bit#(1) v);\n    method Bit#(1)     up_exit_drv();\nendinterface\n(* always_ready, always_enabled *)\ninterface PcieedwrapEv1;\n    method Action      us(Bit#(1) v);\n    method Bit#(1)     us_drv();\nendinterface\n(* always_ready, always_enabled *)\ninterface PcieedwrapEv128;\n    method Action      ns(Bit#(1) v);\n    method Bit#(1)     ns_drv();\nendinterface\n(* always_ready, always_enabled *)\ninterface PcieedwrapHotrst;\n    method Action      exit(Bit#(1) v);\n    method Bit#(1)     exit_drv();\nendinterface\n(* always_ready, always_enabled *)\ninterface PcieedwrapHpg;\n    method Bit#(5)     ctrler();\nendinterface\n(* always_ready, always_enabled *)\ninterface PcieedwrapInt_s;\n    method Action      tatus(Bit#(4) v);\n    method Bit#(4)     tatus_drv();\nendinterface\n(* always_ready, always_enabled *)\ninterface PcieedwrapKo;\n    method Action      cpl_spc_data(Bit#(12) v);\n    method Bit#(12)     cpl_spc_data_drv();\n    method Action      cpl_spc_header(Bit#(8) v);\n    method Bit#(8)     cpl_spc_header_drv();\nendinterface\n(* always_ready, always_enabled *)\ninterface PcieedwrapL2;\n    method Action      exit(Bit#(1) v);\n    method Bit#(1)     exit_drv();\nendinterface\n(* always_ready, always_enabled *)\ninterface PcieedwrapLane;\n    method Action      act(Bit#(4) v);\n    method Bit#(4)     act_drv();\nendinterface\n(* always_ready, always_enabled *)\ninterface PcieedwrapLmi;\n    method Action      ack(Bit#(1) v);\n    method Bit#(12)     addr();\n    method Bit#(32)     din();\n    method Action      dout(Bit#(32) v);\n    method Bit#(1)     rden();\n    method Bit#(1)     wren();\nendinterface\n(* always_ready, always_enabled *)\ninterface PcieedwrapLtssm;\n    method Action      state(Bit#(5) v);\n    method Bit#(5)     state_drv();\nendinterface\n(* always_ready, always_enabled *)\ninterface PcieedwrapPld;\n    interface Clock     clk_hip;\n    method Action      clk_inuse(Bit#(1) v);\n    method Bit#(1)     core_ready();\nendinterface\n(* always_ready, always_enabled *)\ninterface PcieedwrapPm;\n    method Bit#(1)     auxpwr();\n    method Bit#(10)     data();\nendinterface\n(* always_ready, always_enabled *)\ninterface PcieedwrapPm_e;\n    method Bit#(1)     vent();\nendinterface\n(* always_ready, always_enabled *)\ninterface PcieedwrapPme;\n    method Bit#(1)     to_cr();\n    method Action      to_sr(Bit#(1) v);\nendinterface\n(* always_ready, always_enabled *)\ninterface PcieedwrapReset;\n    method Action      status(Bit#(1) v);\nendinterface\n(* always_ready, always_enabled *)\ninterface PcieedwrapRx_par;\n    method Action      err(Bit#(1) v);\n    method Bit#(1)     err_drv();\nendinterface\n(* always_ready, always_enabled *)\ninterface PcieedwrapRx_s;\n    method Action      t_bar(Bit#(8) v);\n    method Action      t_be(Bit#(16) v);\n    method Action      t_data(Bit#(128) v);\n    method Action      t_empty(Bit#(2) v);\n    method Action      t_eop(Bit#(1) v);\n    method Action      t_err(Bit#(1) v);\n    method Bit#(1)     t_mask();\n    method Bit#(1)     t_ready();\n    method Action      t_sop(Bit#(1) v);\n    method Action      t_valid(Bit#(1) v);\nendinterface\n(* always_ready, always_enabled *)\ninterface PcieedwrapSerdes;\n    method Action      pll_locked(Bit#(1) v);\nendinterface\n(* always_ready, always_enabled *)\ninterface PcieedwrapTestin;\n    method Action      zero(Bit#(1) v);\nendinterface\n(* always_ready, always_enabled *)\ninterface PcieedwrapTl;\n    method Action      cfg_add(Bit#(4) v);\n    method Action      cfg_ctl(Bit#(32) v);\n    method Action      cfg_sts(Bit#(53) v);\nendinterface\n(* always_ready, always_enabled *)\ninterface PcieedwrapTx_cred;\n    method Action      datafccp(Bit#(12) v);\n    method Action      datafcnp(Bit#(12) v);\n    method Action      datafcp(Bit#(12) v);\n    method Action      fchipcons(Bit#(6) v);\n    method Action      fcinfinite(Bit#(6) v);\n    method Action      hdrfccp(Bit#(8) v);\n    method Action      hdrfcnp(Bit#(8) v);\n    method Action      hdrfcp(Bit#(8) v);\nendinterface\n(* always_ready, always_enabled *)\ninterface PcieedwrapTx_par;\n    method Action      err(Bit#(2) v);\n    method Bit#(2)     err_drv();\nendinterface\n(* always_ready, always_enabled *)\ninterface PcieedwrapTx_s;\n    method Bit#(128)     t_data();\n    method Bit#(2)     t_empty();\n    method Bit#(1)     t_eop();\n    method Bit#(1)     t_err();\n    method Action      t_ready(Bit#(1) v);\n    method Bit#(1)     t_sop();\n    method Bit#(1)     t_valid();\nendinterface\n(* always_ready, always_enabled *)\ninterface PcieEdWrap;\n    interface PcieedwrapApp     app;\n    interface PcieedwrapCfg_par     cfg_par;\n    interface PcieedwrapCpl     cpl;\n    interface PcieedwrapDerr     derr;\n    interface PcieedwrapDl     dl;\n    interface PcieedwrapEv128     ev128;\n    interface PcieedwrapEv1     ev1;\n    interface PcieedwrapHotrst     hotrst;\n    interface PcieedwrapHpg     hpg;\n    interface PcieedwrapInt_s     int_s;\n    interface PcieedwrapKo     ko;\n    interface PcieedwrapL2     l2;\n    interface PcieedwrapLane     lane;\n    interface PcieedwrapLmi     lmi;\n    interface PcieedwrapLtssm     ltssm;\n    interface PcieedwrapPld     pld;\n    interface PcieedwrapPm     pm;\n    interface PcieedwrapPm_e     pm_e;\n    interface PcieedwrapPme     pme;\n    interface PcieedwrapReset     reset;\n    interface PcieedwrapRx_par     rx_par;\n    interface PcieedwrapRx_s     rx_s;\n    interface PcieedwrapSerdes     serdes;\n    interface PcieedwrapTestin     testin;\n    interface PcieedwrapTl     tl;\n    interface PcieedwrapTx_cred     tx_cred;\n    interface PcieedwrapTx_par     tx_par;\n    interface PcieedwrapTx_s     tx_s;\nendinterface\nimport \"BVI\" altera_pcie_hip_ast_ed =\nmodule mkPcieEdWrap#(Clock coreclkout_hip, Reset coreclkout_hip_reset)(PcieEdWrap);\n    default_clock clk();\n    default_reset rst();\n        input_clock coreclkout_hip(coreclkout_hip) = coreclkout_hip;\n        input_reset coreclkout_hip_reset() = coreclkout_hip_reset; /* from clock*/\n    interface PcieedwrapApp     app;\n        method int_ack(app_int_ack) clocked_by(coreclkout_hip) enable((*inhigh*) EN_app_int_ack);\n        method app_int_sts int_sts() clocked_by(coreclkout_hip);\n        method msi_ack(app_msi_ack) clocked_by(coreclkout_hip) enable((*inhigh*) EN_app_msi_ack);\n        method app_msi_num msi_num() clocked_by(coreclkout_hip);\n        method app_msi_req msi_req() clocked_by(coreclkout_hip);\n        method app_msi_tc msi_tc() clocked_by(coreclkout_hip);\n    endinterface\n    interface PcieedwrapCfg_par     cfg_par;\n        method err(cfg_par_err)clocked_by(coreclkout_hip) enable((*inhigh*) EN_cfg_par_err);\n        method cfg_par_err_drv err_drv();\n    endinterface\n    interface PcieedwrapCpl     cpl;\n        method cpl_err err()clocked_by(coreclkout_hip);\n        method cpl_pending pending()clocked_by(coreclkout_hip);\n    endinterface\n    interface PcieedwrapDerr     derr;\n        method cor_ext_rcv(derr_cor_ext_rcv) clocked_by(coreclkout_hip)enable((*inhigh*) EN_derr_cor_ext_rcv);\n        method derr_cor_ext_rcv_drv cor_ext_rcv_drv();\n        method cor_ext_rpl(derr_cor_ext_rpl) clocked_by(coreclkout_hip)enable((*inhigh*) EN_derr_cor_ext_rpl);\n        method derr_cor_ext_rpl_drv cor_ext_rpl_drv();\n        method rpl(derr_rpl)clocked_by(coreclkout_hip) enable((*inhigh*) EN_derr_rpl);\n        method derr_rpl_drv rpl_drv();\n    endinterface\n    interface PcieedwrapDl     dl;\n        method up(dlup) clocked_by(coreclkout_hip)enable((*inhigh*) EN_dlup);\n        method dlup_drv up_drv();\n        method up_exit(dlup_exit)clocked_by(coreclkout_hip) enable((*inhigh*) EN_dlup_exit);\n        method dlup_exit_drv up_exit_drv();\n    endinterface\n    interface PcieedwrapEv128     ev128;\n        method ns(ev128ns) clocked_by(coreclkout_hip)enable((*inhigh*) EN_ev128ns);\n        method ev128ns_drv ns_drv();\n    endinterface\n    interface PcieedwrapEv1     ev1;\n        method us(ev1us) clocked_by(coreclkout_hip)enable((*inhigh*) EN_ev1us);\n        method ev1us_drv us_drv();\n    endinterface\n    interface PcieedwrapHotrst     hotrst;\n        method exit(hotrst_exit) clocked_by(coreclkout_hip)enable((*inhigh*) EN_hotrst_exit);\n        method hotrst_exit_drv exit_drv();\n    endinterface\n    interface PcieedwrapHpg     hpg;\n        method hpg_ctrler ctrler() clocked_by(coreclkout_hip);\n    endinterface\n    interface PcieedwrapInt_s     int_s;\n        method tatus(int_status) clocked_by(coreclkout_hip) enable((*inhigh*) EN_int_status);\n        method int_status_drv tatus_drv();\n    endinterface\n    interface PcieedwrapKo     ko;\n        method cpl_spc_data(ko_cpl_spc_data) clocked_by(coreclkout_hip) enable((*inhigh*) EN_ko_cpl_spc_data);\n        method ko_cpl_spc_data_drv cpl_spc_data_drv();\n        method cpl_spc_header(ko_cpl_spc_header) clocked_by(coreclkout_hip) enable((*inhigh*) EN_ko_cpl_spc_header);\n        method ko_cpl_spc_header_drv cpl_spc_header_drv();\n    endinterface\n    interface PcieedwrapL2     l2;\n        method exit(l2_exit) clocked_by(coreclkout_hip) enable((*inhigh*) EN_l2_exit);\n        method l2_exit_drv exit_drv();\n    endinterface\n    interface PcieedwrapLane     lane;\n        method act(lane_act) clocked_by(coreclkout_hip) enable((*inhigh*) EN_lane_act);\n        method lane_act_drv act_drv();\n    endinterface\n    interface PcieedwrapLmi     lmi;\n        method ack(lmi_ack) clocked_by(coreclkout_hip) enable((*inhigh*) EN_lmi_ack);\n        method lmi_addr addr() clocked_by(coreclkout_hip);\n        method lmi_din din() clocked_by(coreclkout_hip);\n        method dout(lmi_dout) clocked_by(coreclkout_hip) enable((*inhigh*) EN_lmi_dout);\n        method lmi_rden rden() clocked_by(coreclkout_hip);\n        method lmi_wren wren() clocked_by(coreclkout_hip);\n    endinterface\n    interface PcieedwrapLtssm     ltssm;\n        method state(ltssmstate) clocked_by(coreclkout_hip) enable((*inhigh*) EN_ltssmstate);\n        method ltssmstate_drv state_drv();\n    endinterface\n    interface PcieedwrapPld     pld;\n        output_clock clk_hip(pld_clk_hip);\n        method clk_inuse(pld_clk_inuse) clocked_by(coreclkout_hip) enable((*inhigh*) EN_pld_clk_inuse);\n        method pld_core_ready core_ready() clocked_by(coreclkout_hip);\n    endinterface\n    interface PcieedwrapPm     pm;\n        method pm_auxpwr auxpwr() clocked_by(coreclkout_hip);\n        method pm_data data() clocked_by(coreclkout_hip);\n    endinterface\n    interface PcieedwrapPm_e     pm_e;\n        method pm_event vent() clocked_by(coreclkout_hip);\n    endinterface\n    interface PcieedwrapPme     pme;\n        method pme_to_cr to_cr();\n        method to_sr(pme_to_sr) clocked_by(coreclkout_hip) enable((*inhigh*) EN_pme_to_sr);\n    endinterface\n    interface PcieedwrapReset     reset;\n        method status(reset_status) clocked_by(coreclkout_hip) enable((*inhigh*) EN_reset_status);\n    endinterface\n    interface PcieedwrapRx_par     rx_par;\n        method err(rx_par_err) clocked_by(coreclkout_hip) enable((*inhigh*) EN_rx_par_err);\n        method rx_par_err_drv err_drv();\n    endinterface\n    interface PcieedwrapRx_s     rx_s;\n        method t_bar(rx_st_bar) clocked_by(coreclkout_hip) enable((*inhigh*) EN_rx_st_bar);\n        method t_be(rx_st_be) clocked_by(coreclkout_hip) enable((*inhigh*) EN_rx_st_be);\n        method t_data(rx_st_data) clocked_by(coreclkout_hip) enable((*inhigh*) EN_rx_st_data);\n        method t_empty(rx_st_empty) clocked_by(coreclkout_hip) enable((*inhigh*) EN_rx_st_empty);\n        method t_eop(rx_st_eop) clocked_by(coreclkout_hip) enable((*inhigh*) EN_rx_st_eop);\n        method t_err(rx_st_err) clocked_by(coreclkout_hip) enable((*inhigh*) EN_rx_st_err);\n        method rx_st_mask t_mask()clocked_by(coreclkout_hip) ;\n        method rx_st_ready t_ready()clocked_by(coreclkout_hip) ;\n        method t_sop(rx_st_sop) clocked_by(coreclkout_hip) enable((*inhigh*) EN_rx_st_sop);\n        method t_valid(rx_st_valid) clocked_by(coreclkout_hip) enable((*inhigh*) EN_rx_st_valid);\n    endinterface\n    interface PcieedwrapSerdes     serdes;\n        method pll_locked(serdes_pll_locked) clocked_by(coreclkout_hip) enable((*inhigh*) EN_serdes_pll_locked);\n    endinterface\n    interface PcieedwrapTestin     testin;\n        method zero(testin_zero) clocked_by(coreclkout_hip) enable((*inhigh*) EN_testin_zero);\n    endinterface\n    interface PcieedwrapTl     tl;\n        method cfg_add(tl_cfg_add) clocked_by(coreclkout_hip) enable((*inhigh*) EN_tl_cfg_add);\n        method cfg_ctl(tl_cfg_ctl) clocked_by(coreclkout_hip) enable((*inhigh*) EN_tl_cfg_ctl);\n        method cfg_sts(tl_cfg_sts) clocked_by(coreclkout_hip) enable((*inhigh*) EN_tl_cfg_sts);\n    endinterface\n    interface PcieedwrapTx_cred     tx_cred;\n        method datafccp(tx_cred_datafccp) clocked_by(coreclkout_hip) enable((*inhigh*) EN_tx_cred_datafccp);\n        method datafcnp(tx_cred_datafcnp) clocked_by(coreclkout_hip) enable((*inhigh*) EN_tx_cred_datafcnp);\n        method datafcp(tx_cred_datafcp) clocked_by(coreclkout_hip) enable((*inhigh*) EN_tx_cred_datafcp);\n        method fchipcons(tx_cred_fchipcons) clocked_by(coreclkout_hip) enable((*inhigh*) EN_tx_cred_fchipcons);\n        method fcinfinite(tx_cred_fcinfinite) clocked_by(coreclkout_hip) enable((*inhigh*) EN_tx_cred_fcinfinite);\n        method hdrfccp(tx_cred_hdrfccp) clocked_by(coreclkout_hip) enable((*inhigh*) EN_tx_cred_hdrfccp);\n        method hdrfcnp(tx_cred_hdrfcnp) clocked_by(coreclkout_hip) enable((*inhigh*) EN_tx_cred_hdrfcnp);\n        method hdrfcp(tx_cred_hdrfcp) clocked_by(coreclkout_hip) enable((*inhigh*) EN_tx_cred_hdrfcp);\n    endinterface\n    interface PcieedwrapTx_par     tx_par;\n        method err(tx_par_err) clocked_by(coreclkout_hip) enable((*inhigh*) EN_tx_par_err);\n        method tx_par_err_drv err_drv();\n    endinterface\n    interface PcieedwrapTx_s     tx_s;\n        method tx_st_data t_data() clocked_by(coreclkout_hip);\n        method tx_st_empty t_empty() clocked_by(coreclkout_hip);\n        method tx_st_eop t_eop() clocked_by(coreclkout_hip);\n        method tx_st_err t_err() clocked_by(coreclkout_hip);\n        method t_ready(tx_st_ready) clocked_by(coreclkout_hip) enable((*inhigh*) EN_tx_st_ready);\n        method tx_st_sop t_sop() clocked_by(coreclkout_hip);\n        method tx_st_valid t_valid() clocked_by(coreclkout_hip);\n    endinterface\n    schedule (app.int_ack, app.int_sts, app.msi_ack, app.msi_num, app.msi_req, app.msi_tc, cfg_par.err, cfg_par.err_drv, cpl.err, cpl.pending, derr.cor_ext_rcv, derr.cor_ext_rcv_drv, derr.cor_ext_rpl, derr.cor_ext_rpl_drv, derr.rpl, derr.rpl_drv, dl.up, dl.up_drv, dl.up_exit, dl.up_exit_drv, ev128.ns, ev128.ns_drv, ev1.us, ev1.us_drv, hotrst.exit, hotrst.exit_drv, hpg.ctrler, int_s.tatus, int_s.tatus_drv, ko.cpl_spc_data, ko.cpl_spc_data_drv, ko.cpl_spc_header, ko.cpl_spc_header_drv, l2.exit, l2.exit_drv, lane.act, lane.act_drv, lmi.ack, lmi.addr, lmi.din, lmi.dout, lmi.rden, lmi.wren, ltssm.state, ltssm.state_drv, pld.clk_inuse, pld.core_ready, pm.auxpwr, pm.data, pm_e.vent, pme.to_cr, pme.to_sr, reset.status, rx_par.err, rx_par.err_drv, rx_s.t_bar, rx_s.t_be, rx_s.t_data, rx_s.t_empty, rx_s.t_eop, rx_s.t_err, rx_s.t_mask, rx_s.t_ready, rx_s.t_sop, rx_s.t_valid, serdes.pll_locked, testin.zero, tl.cfg_add, tl.cfg_ctl, tl.cfg_sts, tx_cred.datafccp, tx_cred.datafcnp, tx_cred.datafcp, tx_cred.fchipcons, tx_cred.fcinfinite, tx_cred.hdrfccp, tx_cred.hdrfcnp, tx_cred.hdrfcp, tx_par.err, tx_par.err_drv, tx_s.t_data, tx_s.t_empty, tx_s.t_eop, tx_s.t_err, tx_s.t_ready, tx_s.t_sop, tx_s.t_valid) CF (app.int_ack, app.int_sts, app.msi_ack, app.msi_num, app.msi_req, app.msi_tc, cfg_par.err, cfg_par.err_drv, cpl.err, cpl.pending, derr.cor_ext_rcv, derr.cor_ext_rcv_drv, derr.cor_ext_rpl, derr.cor_ext_rpl_drv, derr.rpl, derr.rpl_drv, dl.up, dl.up_drv, dl.up_exit, dl.up_exit_drv, ev128.ns, ev128.ns_drv, ev1.us, ev1.us_drv, hotrst.exit, hotrst.exit_drv, hpg.ctrler, int_s.tatus, int_s.tatus_drv, ko.cpl_spc_data, ko.cpl_spc_data_drv, ko.cpl_spc_header, ko.cpl_spc_header_drv, l2.exit, l2.exit_drv, lane.act, lane.act_drv, lmi.ack, lmi.addr, lmi.din, lmi.dout, lmi.rden, lmi.wren, ltssm.state, ltssm.state_drv, pld.clk_inuse, pld.core_ready, pm.auxpwr, pm.data, pm_e.vent, pme.to_cr, pme.to_sr, reset.status, rx_par.err, rx_par.err_drv, rx_s.t_bar, rx_s.t_be, rx_s.t_data, rx_s.t_empty, rx_s.t_eop, rx_s.t_err, rx_s.t_mask, rx_s.t_ready, rx_s.t_sop, rx_s.t_valid, serdes.pll_locked, testin.zero, tl.cfg_add, tl.cfg_ctl, tl.cfg_sts, tx_cred.datafccp, tx_cred.datafcnp, tx_cred.datafcp, tx_cred.fchipcons, tx_cred.fcinfinite, tx_cred.hdrfccp, tx_cred.hdrfcnp, tx_cred.hdrfcp, tx_par.err, tx_par.err_drv, tx_s.t_data, tx_s.t_empty, tx_s.t_eop, tx_s.t_err, tx_s.t_ready, tx_s.t_sop, tx_s.t_valid);\nendmodule\n"
  },
  {
    "path": "generated/altera/ALTERA_PCIE_RECONFIG_DRIVER_WRAPPER.bsv",
    "content": "\n/*\n   ./importbvi.py\n   -o\n   ALTERA_PCIE_RECONFIG_DRIVER_WRAPPER.bsv\n   -I\n   PcieReconfigWrap\n   -P\n   PcieReconfigWrap\n   -c\n   reconfig_xcvr_clk\n   -c\n   pld_clk\n   -r\n   reconfig_xcvr_rst\n   -f\n   reconfig_mgmt\n   -f\n   reconfig_b\n   -f\n   current\n   -f\n   derr\n   -f\n   dlup\n   -f\n   ev128ns\n   -f\n   ev1us\n   -f\n   hotrst\n   -f\n   int_s\n   -f\n   l2\n   -f\n   lane\n   -f\n   ltssmstate\n   -f\n   dlup\n   -f\n   rx\n   -f\n   tx\n   -f\n   tx\n   -f\n   rx\n   -f\n   cfg\n   -f\n   ko\n   ../../out/de5/synthesis/altera_pcie_reconfig_driver_wrapper.v\n*/\n\nimport Clocks::*;\nimport DefaultValue::*;\nimport XilinxCells::*;\nimport GetPut::*;\n\n(* always_ready, always_enabled *)\ninterface PciereconfigwrapCfg;\n    method Action      par_err_drv(Bit#(1) v);\nendinterface\n(* always_ready, always_enabled *)\ninterface PciereconfigwrapCurrent;\n    method Action      speed(Bit#(2) v);\nendinterface\n(* always_ready, always_enabled *)\ninterface PciereconfigwrapDerr;\n    method Action      cor_ext_rcv_drv(Bit#(1) v);\n    method Action      cor_ext_rpl_drv(Bit#(1) v);\n    method Action      rpl_drv(Bit#(1) v);\nendinterface\n(* always_ready, always_enabled *)\ninterface PciereconfigwrapDlup;\n    method Action      drv(Bit#(1) v);\n    method Action      exit_drv(Bit#(1) v);\nendinterface\n(* always_ready, always_enabled *)\ninterface PciereconfigwrapEv128ns;\n    method Action      drv(Bit#(1) v);\nendinterface\n(* always_ready, always_enabled *)\ninterface PciereconfigwrapEv1us;\n    method Action      drv(Bit#(1) v);\nendinterface\n(* always_ready, always_enabled *)\ninterface PciereconfigwrapHotrst;\n    method Action      exit_drv(Bit#(1) v);\nendinterface\n(* always_ready, always_enabled *)\ninterface PciereconfigwrapInt_s;\n    method Action      tatus_drv(Bit#(4) v);\nendinterface\n(* always_ready, always_enabled *)\ninterface PciereconfigwrapKo;\n    method Action      cpl_spc_data_drv(Bit#(12) v);\n    method Action      cpl_spc_header_drv(Bit#(8) v);\nendinterface\n(* always_ready, always_enabled *)\ninterface PciereconfigwrapL2;\n    method Action      exit_drv(Bit#(1) v);\nendinterface\n(* always_ready, always_enabled *)\ninterface PciereconfigwrapLane;\n    method Action      act_drv(Bit#(4) v);\nendinterface\n(* always_ready, always_enabled *)\ninterface PciereconfigwrapLtssmstate;\n    method Action      drv(Bit#(5) v);\nendinterface\n(* always_ready, always_enabled *)\n(* always_ready, always_enabled *)\n(* always_ready, always_enabled *)\ninterface PciereconfigwrapReconfig_b;\n    method Action      usy(Bit#(1) v);\nendinterface\n(* always_ready, always_enabled *)\ninterface PciereconfigwrapReconfig_mgmt;\n    method Bit#(7)     address();\n    method Bit#(1)     read();\n    method Action      readdata(Bit#(32) v);\n    method Action      waitrequest(Bit#(1) v);\n    method Bit#(1)     write();\n    method Bit#(32)     writedata();\nendinterface\n(* always_ready, always_enabled *)\ninterface PciereconfigwrapRx;\n    method Action      par_err_drv(Bit#(1) v);\nendinterface\n(* always_ready, always_enabled *)\ninterface PciereconfigwrapTx;\n    method Action      par_err_drv(Bit#(2) v);\nendinterface\n(* always_ready, always_enabled *)\ninterface PcieReconfigWrap;\n    interface PciereconfigwrapCfg     cfg;\n    interface PciereconfigwrapCurrent     current;\n    interface PciereconfigwrapDerr     derr;\n    interface PciereconfigwrapDlup     dlup;\n    interface PciereconfigwrapEv128ns     ev128ns;\n    interface PciereconfigwrapEv1us     ev1us;\n    interface PciereconfigwrapHotrst     hotrst;\n    interface PciereconfigwrapInt_s     int_s;\n    interface PciereconfigwrapKo     ko;\n    interface PciereconfigwrapL2     l2;\n    interface PciereconfigwrapLane     lane;\n    interface PciereconfigwrapLtssmstate     ltssmstate;\n    interface PciereconfigwrapReconfig_b     reconfig_b;\n    interface PciereconfigwrapReconfig_mgmt     reconfig_mgmt;\n    interface PciereconfigwrapRx     rx;\n    interface PciereconfigwrapTx     tx;\nendinterface\nimport \"BVI\" altera_pcie_reconfig_driver_wrapper =\nmodule mkPcieReconfigWrap#(Clock pld_clk, Clock reconfig_xcvr_clk, Reset pld_clk_reset, Reset reconfig_xcvr_clk_reset, Reset reconfig_xcvr_rst)(PcieReconfigWrap);\n    default_clock clk();\n    default_reset rst();\n        input_clock pld_clk(pld_clk) = pld_clk;\n        input_reset pld_clk_reset() = pld_clk_reset; /* from clock*/\n        input_clock reconfig_xcvr_clk(reconfig_xcvr_clk) = reconfig_xcvr_clk;\n        input_reset reconfig_xcvr_clk_reset() = reconfig_xcvr_clk_reset; /* from clock*/\n        input_reset reconfig_xcvr_rst(reconfig_xcvr_rst) = reconfig_xcvr_rst;\n    interface PciereconfigwrapCfg     cfg;\n        method par_err_drv(cfg_par_err_drv) clocked_by(pld_clk) enable((*inhigh*) EN_cfg_par_err_drv);\n    endinterface\n    interface PciereconfigwrapCurrent     current;\n        method speed(currentspeed) clocked_by(pld_clk) enable((*inhigh*) EN_currentspeed);\n    endinterface\n    interface PciereconfigwrapDerr     derr;\n        method cor_ext_rcv_drv(derr_cor_ext_rcv_drv) clocked_by(pld_clk) enable((*inhigh*) EN_derr_cor_ext_rcv_drv);\n        method cor_ext_rpl_drv(derr_cor_ext_rpl_drv) clocked_by(pld_clk) enable((*inhigh*) EN_derr_cor_ext_rpl_drv);\n        method rpl_drv(derr_rpl_drv) clocked_by(pld_clk) enable((*inhigh*) EN_derr_rpl_drv);\n    endinterface\n    interface PciereconfigwrapDlup     dlup;\n        method drv(dlup_drv) clocked_by(pld_clk) enable((*inhigh*) EN_dlup_drv);\n        method exit_drv(dlup_exit_drv) clocked_by(pld_clk) enable((*inhigh*) EN_dlup_exit_drv);\n    endinterface\n    interface PciereconfigwrapEv128ns     ev128ns;\n        method drv(ev128ns_drv) clocked_by(pld_clk) enable((*inhigh*) EN_ev128ns_drv);\n    endinterface\n    interface PciereconfigwrapEv1us     ev1us;\n        method drv(ev1us_drv) clocked_by(pld_clk) enable((*inhigh*) EN_ev1us_drv);\n    endinterface\n    interface PciereconfigwrapHotrst     hotrst;\n        method exit_drv(hotrst_exit_drv) clocked_by(pld_clk) enable((*inhigh*) EN_hotrst_exit_drv);\n    endinterface\n    interface PciereconfigwrapInt_s     int_s;\n        method tatus_drv(int_status_drv) clocked_by(pld_clk) enable((*inhigh*) EN_int_status_drv);\n    endinterface\n    interface PciereconfigwrapKo     ko;\n        method cpl_spc_data_drv(ko_cpl_spc_data_drv) clocked_by(pld_clk) enable((*inhigh*) EN_ko_cpl_spc_data_drv);\n        method cpl_spc_header_drv(ko_cpl_spc_header_drv) clocked_by(pld_clk) enable((*inhigh*) EN_ko_cpl_spc_header_drv);\n    endinterface\n    interface PciereconfigwrapL2     l2;\n        method exit_drv(l2_exit_drv) clocked_by(pld_clk) enable((*inhigh*) EN_l2_exit_drv);\n    endinterface\n    interface PciereconfigwrapLane     lane;\n        method act_drv(lane_act_drv) clocked_by(pld_clk) enable((*inhigh*) EN_lane_act_drv);\n    endinterface\n    interface PciereconfigwrapLtssmstate     ltssmstate;\n        method drv(ltssmstate_drv) clocked_by(pld_clk) enable((*inhigh*) EN_ltssmstate_drv);\n    endinterface\n    interface PciereconfigwrapReconfig_b     reconfig_b;\n        method usy(reconfig_busy) enable((*inhigh*) EN_reconfig_busy);\n    endinterface\n    interface PciereconfigwrapReconfig_mgmt     reconfig_mgmt;\n        method reconfig_mgmt_address address();\n        method reconfig_mgmt_read read();\n        method readdata(reconfig_mgmt_readdata) enable((*inhigh*) EN_reconfig_mgmt_readdata);\n        method waitrequest(reconfig_mgmt_waitrequest) enable((*inhigh*) EN_reconfig_mgmt_waitrequest);\n        method reconfig_mgmt_write write();\n        method reconfig_mgmt_writedata writedata();\n    endinterface\n    interface PciereconfigwrapRx     rx;\n        method par_err_drv(rx_par_err_drv) clocked_by(pld_clk) enable((*inhigh*) EN_rx_par_err_drv);\n    endinterface\n    interface PciereconfigwrapTx     tx;\n        method par_err_drv(tx_par_err_drv) clocked_by(pld_clk) enable((*inhigh*) EN_tx_par_err_drv);\n    endinterface\n    schedule (cfg.par_err_drv, current.speed, derr.cor_ext_rcv_drv, derr.cor_ext_rpl_drv, derr.rpl_drv, dlup.drv, dlup.exit_drv, ev128ns.drv, ev1us.drv, hotrst.exit_drv, int_s.tatus_drv, ko.cpl_spc_data_drv, ko.cpl_spc_header_drv, l2.exit_drv, lane.act_drv, ltssmstate.drv, reconfig_b.usy, reconfig_mgmt.address, reconfig_mgmt.read, reconfig_mgmt.readdata, reconfig_mgmt.waitrequest, reconfig_mgmt.write, reconfig_mgmt.writedata, rx.par_err_drv, tx.par_err_drv) CF (cfg.par_err_drv, current.speed, derr.cor_ext_rcv_drv, derr.cor_ext_rpl_drv, derr.rpl_drv, dlup.drv, dlup.exit_drv, ev128ns.drv, ev1us.drv, hotrst.exit_drv, int_s.tatus_drv, ko.cpl_spc_data_drv, ko.cpl_spc_header_drv, l2.exit_drv, lane.act_drv, ltssmstate.drv, reconfig_b.usy, reconfig_mgmt.address, reconfig_mgmt.read, reconfig_mgmt.readdata, reconfig_mgmt.waitrequest, reconfig_mgmt.write, reconfig_mgmt.writedata, rx.par_err_drv, tx.par_err_drv);\nendmodule\n"
  },
  {
    "path": "generated/altera/ALTERA_PCIE_SIV_WRAPPER.bsv",
    "content": "\n/*\n   ./importbvi.py\n   -o\n   ALTERA_PCIE_SIV_WRAPPER.bsv\n   -I\n   PcieS4Wrap\n   -P\n   PcieS4Wrap\n   -r\n   pin_perst\n   -r\n   npor\n   -r\n   reset_status\n   -r\n   pcie_rstn\n   -r\n   srstn\n   -c\n   refclk\n   -c\n   core_clk_out\n   -c\n   pclk_in\n   -c\n   reconfig_clk\n   -c\n   clk250_out\n   -f\n   app\n   -f\n   pex_msi\n   -f\n   cpl\n   -f\n   rx_st\n   -f\n   tx_st\n   -f\n   fixedclk\n   -f\n   lmi\n   -f\n   tx\n   -f\n   rx\n   -f\n   phystatus\n   -f\n   pipe\n   -f\n   pm\n   -f\n   pme\n   -f\n   reconfig\n   -f\n   test\n   -f\n   lane\n   -f\n   ltssm\n   -f\n   powerdown\n   -f\n   rate\n   -f\n   rc_pll\n   -f\n   tl_cfg\n   ../../out/htg4/siv_gen2x8/siv_gen2x8_examples/chaining_dma/siv_gen2x8_plus.v\n*/\n\nimport Clocks::*;\nimport DefaultValue::*;\nimport XilinxCells::*;\nimport GetPut::*;\n\n(* always_ready, always_enabled *)\ninterface Pcies4wrapApp;\n    method Bit#(1)     int_ack();\n    method Action      int_sts(Bit#(1) v);\n    method Bit#(1)     msi_ack();\n    method Action      msi_num(Bit#(5) v);\n    method Action      msi_req(Bit#(1) v);\n    method Action      msi_tc(Bit#(3) v);\nendinterface\n(* always_ready, always_enabled *)\ninterface Pcies4wrapClk250;\n    method Bit#(1)     out;\nendinterface\n(* always_ready, always_enabled *)\ninterface Pcies4wrapClk500;\n    method Bit#(1)     out;\nendinterface\n(* always_ready, always_enabled *)\ninterface Pcies4wrapCore;\n    interface Clock     clk_out;\nendinterface\n(* always_ready, always_enabled *)\ninterface Pcies4wrapCpl;\n    method Action      err(Bit#(7) v);\n    method Action      pending(Bit#(1) v);\nendinterface\n(* always_ready, always_enabled *)\ninterface Pcies4wrapSrstn;\n    method Reset     stn();\nendinterface\n(* always_ready, always_enabled *)\ninterface Pcies4wrapLane;\n    method Bit#(4)     act();\nendinterface\n(* always_ready, always_enabled *)\ninterface Pcies4wrapLmi;\n    method Bit#(1)     ack();\n    method Action      addr(Bit#(12) v);\n    method Action      din(Bit#(32) v);\n    method Bit#(32)     dout();\n    method Action      rden(Bit#(1) v);\n    method Action      wren(Bit#(1) v);\nendinterface\ninterface Pcies4wrapPclk;\n    method Action      in(Bit#(1) v);\nendinterface\n(* always_ready, always_enabled *)\ninterface Pcies4wrapLtssm;\n    method Bit#(5)     sm();\nendinterface\n(* always_ready, always_enabled *)\ninterface Pcies4wrapPex_msi;\n    method Action      num(Bit#(5) v);\nendinterface\n(* always_ready, always_enabled *)\ninterface Pcies4wrapPhystatus;\n    method Action      ext(Bit#(1) v);\nendinterface\n(* always_ready, always_enabled *)\ninterface Pcies4wrapPipe;\n    method Action      mode(Bit#(1) v);\nendinterface\n(* always_ready, always_enabled *)\ninterface Pcies4wrapPld;\n    method Action      clk(Bit#(1) v);\nendinterface\n(* always_ready, always_enabled *)\ninterface PciewrapPm_e;\n    method Action      vent(Bit#(1) v);\nendinterface\n(* always_ready, always_enabled *)\ninterface Pcies4wrapPm;\n    method Action      auxpwr(Bit#(1) v);\n    method Action      data(Bit#(10) v);\n    method Action      e_to_cr(Bit#(1) v);\n    method Bit#(1)     e_to_sr();\nendinterface\n(* always_ready, always_enabled *)\ninterface Pcies4wrapPowerdown;\n    method Bit#(2)     ext();\nendinterface\n(* always_ready, always_enabled *)\ninterface Pcies4wrapRate;\n    method Bit#(1)     ext();\nendinterface\n(* always_ready, always_enabled *)\ninterface Pcies4wrapRc_pll;\n    method Bit#(1)     locked();\nendinterface\n(* always_ready, always_enabled *)\ninterface Pcies4wrapReconfig;\n    method Action      clk_locked(Bit#(1) v);\nendinterface\n(* always_ready, always_enabled *)\ninterface Pcies4wrapRx;\n    method Action      in0(Bit#(1) v);\n    method Action      in1(Bit#(1) v);\n    method Action      in2(Bit#(1) v);\n    method Action      in3(Bit#(1) v);\n    method Action      in4(Bit#(1) v);\n    method Action      in5(Bit#(1) v);\n    method Action      in6(Bit#(1) v);\n    method Action      in7(Bit#(1) v);\n    method Action      data0_ext(Bit#(8) v);\n    method Action      data1_ext(Bit#(8) v);\n    method Action      data2_ext(Bit#(8) v);\n    method Action      data3_ext(Bit#(8) v);\n    method Action      data4_ext(Bit#(8) v);\n    method Action      data5_ext(Bit#(8) v);\n    method Action      data6_ext(Bit#(8) v);\n    method Action      data7_ext(Bit#(8) v);\n    method Action      datak0_ext(Bit#(1) v);\n    method Action      datak1_ext(Bit#(1) v);\n    method Action      datak2_ext(Bit#(1) v);\n    method Action      datak3_ext(Bit#(1) v);\n    method Action      datak4_ext(Bit#(1) v);\n    method Action      datak5_ext(Bit#(1) v);\n    method Action      datak6_ext(Bit#(1) v);\n    method Action      datak7_ext(Bit#(1) v);\n    method Action      elecidle0_ext(Bit#(1) v);\n    method Action      elecidle1_ext(Bit#(1) v);\n    method Action      elecidle2_ext(Bit#(1) v);\n    method Action      elecidle3_ext(Bit#(1) v);\n    method Action      elecidle4_ext(Bit#(1) v);\n    method Action      elecidle5_ext(Bit#(1) v);\n    method Action      elecidle6_ext(Bit#(1) v);\n    method Action      elecidle7_ext(Bit#(1) v);\n    method Bit#(1)     polarity0_ext();\n    method Bit#(1)     polarity1_ext();\n    method Bit#(1)     polarity2_ext();\n    method Bit#(1)     polarity3_ext();\n    method Bit#(1)     polarity4_ext();\n    method Bit#(1)     polarity5_ext();\n    method Bit#(1)     polarity6_ext();\n    method Bit#(1)     polarity7_ext();\n    method Action      status0_ext(Bit#(3) v);\n    method Action      status1_ext(Bit#(3) v);\n    method Action      status2_ext(Bit#(3) v);\n    method Action      status3_ext(Bit#(3) v);\n    method Action      status4_ext(Bit#(3) v);\n    method Action      status5_ext(Bit#(3) v);\n    method Action      status6_ext(Bit#(3) v);\n    method Action      status7_ext(Bit#(3) v);\n    method Action      valid0_ext(Bit#(1) v);\n    method Action      valid1_ext(Bit#(1) v);\n    method Action      valid2_ext(Bit#(1) v);\n    method Action      valid3_ext(Bit#(1) v);\n    method Action      valid4_ext(Bit#(1) v);\n    method Action      valid5_ext(Bit#(1) v);\n    method Action      valid6_ext(Bit#(1) v);\n    method Action      valid7_ext(Bit#(1) v);\nendinterface\n(* always_ready, always_enabled *)\ninterface Pcies4wrapRx_st;\n    method Bit#(8)     bardec0();\n    method Bit#(16)    be0();\n    method Bit#(128)   data0();\n    method Bit#(1)     empty0();\n    method Bit#(1)     eop0();\n    method Bit#(1)     err0();\n    method Action      mask0(Bit#(1) v);\n    method Action      ready0(Bit#(1) v);\n    method Bit#(1)     sop0();\n    method Bit#(1)     valid0();\nendinterface\n(* always_ready, always_enabled *)\ninterface Pcies4wrapTest;\n    method Action      in(Bit#(40) v);\nendinterface\n(* always_ready, always_enabled *)\ninterface Pcies4wrapTl_cfg;\n    method Bit#(4)     add();\n    method Bit#(32)     ctl();\n    method Bit#(1)     ctl_wr();\n    method Bit#(53)     sts();\n    method Bit#(1)     sts_wr();\nendinterface\n(* always_ready, always_enabled *)\ninterface Pcies4wrapTx;\n    method Bit#(36)     cred0();\n    method Bit#(1)     fifo_empty0();\n    method Bit#(1)     out0();\n    method Bit#(1)     out1();\n    method Bit#(1)     out2();\n    method Bit#(1)     out3();\n    method Bit#(1)     out4();\n    method Bit#(1)     out5();\n    method Bit#(1)     out6();\n    method Bit#(1)     out7();\n    method Bit#(1)     compl0_ext();\n    method Bit#(1)     compl1_ext();\n    method Bit#(1)     compl2_ext();\n    method Bit#(1)     compl3_ext();\n    method Bit#(1)     compl4_ext();\n    method Bit#(1)     compl5_ext();\n    method Bit#(1)     compl6_ext();\n    method Bit#(1)     compl7_ext();\n    method Bit#(8)     data0_ext();\n    method Bit#(8)     data1_ext();\n    method Bit#(8)     data2_ext();\n    method Bit#(8)     data3_ext();\n    method Bit#(8)     data4_ext();\n    method Bit#(8)     data5_ext();\n    method Bit#(8)     data6_ext();\n    method Bit#(8)     data7_ext();\n    method Bit#(1)     datak0_ext();\n    method Bit#(1)     datak1_ext();\n    method Bit#(1)     datak2_ext();\n    method Bit#(1)     datak3_ext();\n    method Bit#(1)     datak4_ext();\n    method Bit#(1)     datak5_ext();\n    method Bit#(1)     datak6_ext();\n    method Bit#(1)     datak7_ext();\n    method Bit#(1)     detectrx_ext();\n    method Bit#(1)     elecidle0_ext();\n    method Bit#(1)     elecidle1_ext();\n    method Bit#(1)     elecidle2_ext();\n    method Bit#(1)     elecidle3_ext();\n    method Bit#(1)     elecidle4_ext();\n    method Bit#(1)     elecidle5_ext();\n    method Bit#(1)     elecidle6_ext();\n    method Bit#(1)     elecidle7_ext();\nendinterface\n(* always_ready, always_enabled *)\ninterface Pcies4wrapTx_st;\n    method Action      data0(Bit#(128) v);\n    method Action      empty0(Bit#(1) v) ;\n    method Action      eop0(Bit#(1) v)   ;\n    method Action      err0(Bit#(1) v)   ;\n    method Bit#(1)     ready0()          ;\n    method Action      sop0(Bit#(1) v)   ;\n    method Action      valid0(Bit#(1) v) ;\nendinterface\n(* always_ready, always_enabled *)\ninterface PcieS4Wrap;\n    interface Pcies4wrapApp     app;\n    interface Pcies4wrapClk250     clk250;\n    interface Pcies4wrapClk500     clk500;\n    interface Pcies4wrapCore     core;\n    interface Pcies4wrapCpl     cpl;\n    interface Pcies4wrapSrstn   sr;\n    interface Pcies4wrapLane     lane;\n    interface Pcies4wrapPclk     pclk;\n    interface Pcies4wrapLmi     lmi;\n    interface Pcies4wrapLtssm     lts;\n    interface Pcies4wrapPex_msi     pex_msi;\n    interface Pcies4wrapPhystatus     phystatus;\n    interface Pcies4wrapPipe     pipe;\n    interface Pcies4wrapPld     pld;\n    interface PciewrapPm_e     pm_e;\n    interface Pcies4wrapPm     pm;\n    interface Pcies4wrapPowerdown     powerdown;\n    interface Pcies4wrapRate     rate;\n    interface Pcies4wrapRc_pll     rc_pll;\n    interface Pcies4wrapReconfig     reconfig;\n    interface Pcies4wrapRx     rx;\n    interface Pcies4wrapRx_st     rx_st;\n    interface Pcies4wrapTest     test;\n    interface Pcies4wrapTl_cfg     tl_cfg;\n    interface Pcies4wrapTx     tx;\n    interface Pcies4wrapTx_st     tx_st;\nendinterface\nimport \"BVI\" siv_gen2x8_plus =\nmodule mkPPS4Wrap#(Clock refclk, Clock reconfig_clk, Clock fixedclk_serdes, Reset pcie_rstn, Reset local_rstn)(PcieS4Wrap);\n    default_clock clk();\n    default_reset rst();\n    input_reset pcie_rstn(pcie_rstn) = pcie_rstn;\n    input_reset local_rstn(local_rstn) = local_rstn;\n    input_clock fixedclk_serdes(fixedclk_serdes) = fixedclk_serdes;\n    input_clock reconfig_clk(reconfig_clk) = reconfig_clk;\n    input_clock refclk(refclk) = refclk;\n    interface Pcies4wrapApp     app;\n        method app_int_ack int_ack();\n        method int_sts(app_int_sts) enable((*inhigh*) EN_app_int_sts);\n        method app_msi_ack msi_ack();\n        method msi_num(app_msi_num) enable((*inhigh*) EN_app_msi_num);\n        method msi_req(app_msi_req) enable((*inhigh*) EN_app_msi_req);\n        method msi_tc(app_msi_tc) enable((*inhigh*) EN_app_msi_tc);\n    endinterface\n    interface Pcies4wrapClk250     clk250;\n        method clk250_out out();\n    endinterface\n    interface Pcies4wrapClk500     clk500;\n        method clk500_out out();\n    endinterface\n    interface Pcies4wrapCore     core;\n        output_clock clk_out(core_clk_out);\n    endinterface\n    interface Pcies4wrapCpl     cpl;\n        method err(cpl_err) enable((*inhigh*) EN_cpl_err);\n        method pending(cpl_pending) enable((*inhigh*) EN_cpl_pending);\n    endinterface\n    interface Pcies4wrapLane     lane;\n        method lane_act act();\n    endinterface\n    interface Pcies4wrapLmi     lmi;\n        method lmi_ack ack();\n        method addr(lmi_addr) enable((*inhigh*) EN_lmi_addr);\n        method din(lmi_din) enable((*inhigh*) EN_lmi_din);\n        method lmi_dout dout();\n        method rden(lmi_rden) enable((*inhigh*) EN_lmi_rden);\n        method wren(lmi_wren) enable((*inhigh*) EN_lmi_wren);\n    endinterface\n    interface Pcies4wrapPclk     pclk;\n        method in(pclk_in) enable((*inhigh*) EN_pclk_in);\n    endinterface\n    interface Pcies4wrapLtssm lts;\n        method ltssm sm();\n    endinterface\n    interface Pcies4wrapPex_msi     pex_msi;\n        method num(pex_msi_num) enable((*inhigh*) EN_pex_msi_num);\n    endinterface\n    interface Pcies4wrapPhystatus     phystatus;\n        method ext(phystatus_ext) enable((*inhigh*) EN_phystatus_ext);\n    endinterface\n    interface Pcies4wrapPipe     pipe;\n        method mode(pipe_mode) enable((*inhigh*) EN_pipe_mode);\n    endinterface\n    interface Pcies4wrapPld     pld;\n        method clk(pld_clk) enable((*inhigh*) EN_pld_clk);\n    endinterface\n    interface PciewrapPm_e     pm_e;\n        method vent(pm_event) enable((*inhigh*) EN_pm_event);\n    endinterface\n    interface Pcies4wrapPm     pm;\n        method auxpwr(pm_auxpwr) enable((*inhigh*) EN_pm_auxpwr);\n        method data(pm_data) enable((*inhigh*) EN_pm_data);\n        method e_to_cr(pme_to_cr) enable((*inhigh*) EN_pme_to_cr);\n        method pme_to_sr e_to_sr();\n    endinterface\n    interface Pcies4wrapPowerdown     powerdown;\n        method powerdown_ext ext();\n    endinterface\n    interface Pcies4wrapRate     rate;\n        method rate_ext ext();\n    endinterface\n    interface Pcies4wrapRc_pll     rc_pll;\n        method rc_pll_locked locked();\n    endinterface\n    interface Pcies4wrapReconfig     reconfig;\n        method clk_locked(reconfig_clk_locked) clocked_by (reconfig_clk) enable((*inhigh*) EN_reconfig_clk_locked);\n    endinterface\n    interface Pcies4wrapRx     rx;\n        method in0(rx_in0) enable((*inhigh*) EN_rx_in0);\n        method in1(rx_in1) enable((*inhigh*) EN_rx_in1);\n        method in2(rx_in2) enable((*inhigh*) EN_rx_in2);\n        method in3(rx_in3) enable((*inhigh*) EN_rx_in3);\n        method in4(rx_in4) enable((*inhigh*) EN_rx_in4);\n        method in5(rx_in5) enable((*inhigh*) EN_rx_in5);\n        method in6(rx_in6) enable((*inhigh*) EN_rx_in6);\n        method in7(rx_in7) enable((*inhigh*) EN_rx_in7);\n        method data0_ext(rxdata0_ext) enable((*inhigh*) EN_rxdata0_ext);\n        method data1_ext(rxdata1_ext) enable((*inhigh*) EN_rxdata1_ext);\n        method data2_ext(rxdata2_ext) enable((*inhigh*) EN_rxdata2_ext);\n        method data3_ext(rxdata3_ext) enable((*inhigh*) EN_rxdata3_ext);\n        method data4_ext(rxdata4_ext) enable((*inhigh*) EN_rxdata4_ext);\n        method data5_ext(rxdata5_ext) enable((*inhigh*) EN_rxdata5_ext);\n        method data6_ext(rxdata6_ext) enable((*inhigh*) EN_rxdata6_ext);\n        method data7_ext(rxdata7_ext) enable((*inhigh*) EN_rxdata7_ext);\n        method datak0_ext(rxdatak0_ext) enable((*inhigh*) EN_rxdatak0_ext);\n        method datak1_ext(rxdatak1_ext) enable((*inhigh*) EN_rxdatak1_ext);\n        method datak2_ext(rxdatak2_ext) enable((*inhigh*) EN_rxdatak2_ext);\n        method datak3_ext(rxdatak3_ext) enable((*inhigh*) EN_rxdatak3_ext);\n        method datak4_ext(rxdatak4_ext) enable((*inhigh*) EN_rxdatak4_ext);\n        method datak5_ext(rxdatak5_ext) enable((*inhigh*) EN_rxdatak5_ext);\n        method datak6_ext(rxdatak6_ext) enable((*inhigh*) EN_rxdatak6_ext);\n        method datak7_ext(rxdatak7_ext) enable((*inhigh*) EN_rxdatak7_ext);\n        method elecidle0_ext(rxelecidle0_ext) enable((*inhigh*) EN_rxelecidle0_ext);\n        method elecidle1_ext(rxelecidle1_ext) enable((*inhigh*) EN_rxelecidle1_ext);\n        method elecidle2_ext(rxelecidle2_ext) enable((*inhigh*) EN_rxelecidle2_ext);\n        method elecidle3_ext(rxelecidle3_ext) enable((*inhigh*) EN_rxelecidle3_ext);\n        method elecidle4_ext(rxelecidle4_ext) enable((*inhigh*) EN_rxelecidle4_ext);\n        method elecidle5_ext(rxelecidle5_ext) enable((*inhigh*) EN_rxelecidle5_ext);\n        method elecidle6_ext(rxelecidle6_ext) enable((*inhigh*) EN_rxelecidle6_ext);\n        method elecidle7_ext(rxelecidle7_ext) enable((*inhigh*) EN_rxelecidle7_ext);\n        method rxpolarity0_ext polarity0_ext();\n        method rxpolarity1_ext polarity1_ext();\n        method rxpolarity2_ext polarity2_ext();\n        method rxpolarity3_ext polarity3_ext();\n        method rxpolarity4_ext polarity4_ext();\n        method rxpolarity5_ext polarity5_ext();\n        method rxpolarity6_ext polarity6_ext();\n        method rxpolarity7_ext polarity7_ext();\n        method status0_ext(rxstatus0_ext) enable((*inhigh*) EN_rxstatus0_ext);\n        method status1_ext(rxstatus1_ext) enable((*inhigh*) EN_rxstatus1_ext);\n        method status2_ext(rxstatus2_ext) enable((*inhigh*) EN_rxstatus2_ext);\n        method status3_ext(rxstatus3_ext) enable((*inhigh*) EN_rxstatus3_ext);\n        method status4_ext(rxstatus4_ext) enable((*inhigh*) EN_rxstatus4_ext);\n        method status5_ext(rxstatus5_ext) enable((*inhigh*) EN_rxstatus5_ext);\n        method status6_ext(rxstatus6_ext) enable((*inhigh*) EN_rxstatus6_ext);\n        method status7_ext(rxstatus7_ext) enable((*inhigh*) EN_rxstatus7_ext);\n        method valid0_ext(rxvalid0_ext) enable((*inhigh*) EN_rxvalid0_ext);\n        method valid1_ext(rxvalid1_ext) enable((*inhigh*) EN_rxvalid1_ext);\n        method valid2_ext(rxvalid2_ext) enable((*inhigh*) EN_rxvalid2_ext);\n        method valid3_ext(rxvalid3_ext) enable((*inhigh*) EN_rxvalid3_ext);\n        method valid4_ext(rxvalid4_ext) enable((*inhigh*) EN_rxvalid4_ext);\n        method valid5_ext(rxvalid5_ext) enable((*inhigh*) EN_rxvalid5_ext);\n        method valid6_ext(rxvalid6_ext) enable((*inhigh*) EN_rxvalid6_ext);\n        method valid7_ext(rxvalid7_ext) enable((*inhigh*) EN_rxvalid7_ext);\n    endinterface\n    interface Pcies4wrapRx_st     rx_st;\n        method rx_st_bardec0 bardec0() clocked_by(core_clk_out) reset_by(no_reset);\n        method rx_st_be0 be0()         clocked_by(core_clk_out) reset_by(no_reset);\n        method rx_st_data0 data0()     clocked_by(core_clk_out) reset_by(no_reset);\n        method rx_st_empty0 empty0()   clocked_by(core_clk_out) reset_by(no_reset);\n        method rx_st_eop0 eop0()       clocked_by(core_clk_out) reset_by(no_reset);\n        method rx_st_err0 err0()       clocked_by(core_clk_out) reset_by(no_reset);\n        method mask0(rx_st_mask0) enable((*inhigh*) EN_rx_st_mask0) clocked_by(core_clk_out) reset_by(no_reset);\n        method ready0(rx_st_ready0) enable((*inhigh*) EN_rx_st_ready0) clocked_by(core_clk_out) reset_by(no_reset);\n        method rx_st_sop0 sop0()       clocked_by(core_clk_out) reset_by(no_reset);\n        method rx_st_valid0 valid0()   clocked_by(core_clk_out) reset_by(no_reset);\n    endinterface\n    interface Pcies4wrapSrstn   sr;\n        output_reset stn(srstn);\n    endinterface\n    interface Pcies4wrapTest     test;\n        method in(test_in) enable((*inhigh*) EN_test_in);\n    endinterface\n    interface Pcies4wrapTl_cfg     tl_cfg;\n        method tl_cfg_add add() clocked_by(core_clk_out) reset_by(no_reset);\n        method tl_cfg_ctl ctl() clocked_by(core_clk_out) reset_by(no_reset);\n        method tl_cfg_ctl_wr ctl_wr() clocked_by(core_clk_out) reset_by(no_reset);\n        method tl_cfg_sts sts() clocked_by(core_clk_out) reset_by(no_reset);\n        method tl_cfg_sts_wr sts_wr() clocked_by(core_clk_out) reset_by(no_reset);\n    endinterface\n    interface Pcies4wrapTx     tx;\n        method tx_cred0 cred0();\n        method tx_fifo_empty0 fifo_empty0();\n        method tx_out0 out0();\n        method tx_out1 out1();\n        method tx_out2 out2();\n        method tx_out3 out3();\n        method tx_out4 out4();\n        method tx_out5 out5();\n        method tx_out6 out6();\n        method tx_out7 out7();\n        method txcompl0_ext compl0_ext();\n        method txcompl1_ext compl1_ext();\n        method txcompl2_ext compl2_ext();\n        method txcompl3_ext compl3_ext();\n        method txcompl4_ext compl4_ext();\n        method txcompl5_ext compl5_ext();\n        method txcompl6_ext compl6_ext();\n        method txcompl7_ext compl7_ext();\n        method txdata0_ext data0_ext();\n        method txdata1_ext data1_ext();\n        method txdata2_ext data2_ext();\n        method txdata3_ext data3_ext();\n        method txdata4_ext data4_ext();\n        method txdata5_ext data5_ext();\n        method txdata6_ext data6_ext();\n        method txdata7_ext data7_ext();\n        method txdatak0_ext datak0_ext();\n        method txdatak1_ext datak1_ext();\n        method txdatak2_ext datak2_ext();\n        method txdatak3_ext datak3_ext();\n        method txdatak4_ext datak4_ext();\n        method txdatak5_ext datak5_ext();\n        method txdatak6_ext datak6_ext();\n        method txdatak7_ext datak7_ext();\n        method txdetectrx_ext detectrx_ext();\n        method txelecidle0_ext elecidle0_ext();\n        method txelecidle1_ext elecidle1_ext();\n        method txelecidle2_ext elecidle2_ext();\n        method txelecidle3_ext elecidle3_ext();\n        method txelecidle4_ext elecidle4_ext();\n        method txelecidle5_ext elecidle5_ext();\n        method txelecidle6_ext elecidle6_ext();\n        method txelecidle7_ext elecidle7_ext();\n    endinterface\n    interface Pcies4wrapTx_st     tx_st;\n        method data0(tx_st_data0) enable((*inhigh*) EN_tx_st_data0) clocked_by(core_clk_out) reset_by(no_reset);\n        method empty0(tx_st_empty0) enable((*inhigh*) EN_tx_st_empty0) clocked_by(core_clk_out) reset_by(no_reset);\n        method eop0(tx_st_eop0) enable((*inhigh*) EN_tx_st_eop0) clocked_by(core_clk_out) reset_by(no_reset);\n        method err0(tx_st_err0) enable((*inhigh*) EN_tx_st_err0) clocked_by(core_clk_out) reset_by(no_reset);\n        method tx_st_ready0 ready0() clocked_by(core_clk_out) reset_by(no_reset);\n        method sop0(tx_st_sop0) enable((*inhigh*) EN_tx_st_sop0) clocked_by(core_clk_out) reset_by(no_reset);\n        method valid0(tx_st_valid0) enable((*inhigh*) EN_tx_st_valid0) clocked_by(core_clk_out) reset_by(no_reset);\n    endinterface\n    schedule (app.int_ack, app.int_sts, app.msi_ack, app.msi_num, app.msi_req, app.msi_tc, cpl.err, cpl.pending, lane.act, lmi.ack, lmi.addr, lmi.din, lmi.dout, lmi.rden, lmi.wren, lts.sm, clk250.out, clk500.out, pclk.in, pex_msi.num, phystatus.ext, pipe.mode, pld.clk, pm.auxpwr, pm.data, pm_e.vent, pm.e_to_cr, pm.e_to_sr, powerdown.ext, rate.ext, rc_pll.locked, reconfig.clk_locked, rx.in0, rx.in1, rx.in2, rx.in3, rx.in4, rx.in5, rx.in6, rx.in7, rx.data0_ext, rx.data1_ext, rx.data2_ext, rx.data3_ext, rx.data4_ext, rx.data5_ext, rx.data6_ext, rx.data7_ext, rx.datak0_ext, rx.datak1_ext, rx.datak2_ext, rx.datak3_ext, rx.datak4_ext, rx.datak5_ext, rx.datak6_ext, rx.datak7_ext, rx.elecidle0_ext, rx.elecidle1_ext, rx.elecidle2_ext, rx.elecidle3_ext, rx.elecidle4_ext, rx.elecidle5_ext, rx.elecidle6_ext, rx.elecidle7_ext, rx.polarity0_ext, rx.polarity1_ext, rx.polarity2_ext, rx.polarity3_ext, rx.polarity4_ext, rx.polarity5_ext, rx.polarity6_ext, rx.polarity7_ext, rx.status0_ext, rx.status1_ext, rx.status2_ext, rx.status3_ext, rx.status4_ext, rx.status5_ext, rx.status6_ext, rx.status7_ext, rx.valid0_ext, rx.valid1_ext, rx.valid2_ext, rx.valid3_ext, rx.valid4_ext, rx.valid5_ext, rx.valid6_ext, rx.valid7_ext, rx_st.bardec0, rx_st.be0, rx_st.data0, rx_st.empty0, rx_st.eop0, rx_st.err0, rx_st.mask0, rx_st.ready0, rx_st.sop0, rx_st.valid0, test.in, tl_cfg.add, tl_cfg.ctl, tl_cfg.ctl_wr, tl_cfg.sts, tl_cfg.sts_wr, tx.cred0, tx.fifo_empty0, tx.out0, tx.out1, tx.out2, tx.out3, tx.out4, tx.out5, tx.out6, tx.out7, tx.compl0_ext, tx.compl1_ext, tx.compl2_ext, tx.compl3_ext, tx.compl4_ext, tx.compl5_ext, tx.compl6_ext, tx.compl7_ext, tx.data0_ext, tx.data1_ext, tx.data2_ext, tx.data3_ext, tx.data4_ext, tx.data5_ext, tx.data6_ext, tx.data7_ext, tx.datak0_ext, tx.datak1_ext, tx.datak2_ext, tx.datak3_ext, tx.datak4_ext, tx.datak5_ext, tx.datak6_ext, tx.datak7_ext, tx.detectrx_ext, tx.elecidle0_ext, tx.elecidle1_ext, tx.elecidle2_ext, tx.elecidle3_ext, tx.elecidle4_ext, tx.elecidle5_ext, tx.elecidle6_ext, tx.elecidle7_ext, tx_st.data0, tx_st.empty0, tx_st.eop0, tx_st.err0, tx_st.ready0, tx_st.sop0, tx_st.valid0) CF (app.int_ack, app.int_sts, app.msi_ack, app.msi_num, app.msi_req, app.msi_tc, cpl.err, cpl.pending, lane.act, lmi.ack, lmi.addr, lmi.din, lmi.dout, lmi.rden, lmi.wren, lts.sm, clk250.out, clk500.out, pclk.in, pex_msi.num, phystatus.ext, pipe.mode, pld.clk, pm.auxpwr, pm.data, pm_e.vent, pm.e_to_cr, pm.e_to_sr, powerdown.ext, rate.ext, rc_pll.locked, reconfig.clk_locked, rx.in0, rx.in1, rx.in2, rx.in3, rx.in4, rx.in5, rx.in6, rx.in7, rx.data0_ext, rx.data1_ext, rx.data2_ext, rx.data3_ext, rx.data4_ext, rx.data5_ext, rx.data6_ext, rx.data7_ext, rx.datak0_ext, rx.datak1_ext, rx.datak2_ext, rx.datak3_ext, rx.datak4_ext, rx.datak5_ext, rx.datak6_ext, rx.datak7_ext, rx.elecidle0_ext, rx.elecidle1_ext, rx.elecidle2_ext, rx.elecidle3_ext, rx.elecidle4_ext, rx.elecidle5_ext, rx.elecidle6_ext, rx.elecidle7_ext, rx.polarity0_ext, rx.polarity1_ext, rx.polarity2_ext, rx.polarity3_ext, rx.polarity4_ext, rx.polarity5_ext, rx.polarity6_ext, rx.polarity7_ext, rx.status0_ext, rx.status1_ext, rx.status2_ext, rx.status3_ext, rx.status4_ext, rx.status5_ext, rx.status6_ext, rx.status7_ext, rx.valid0_ext, rx.valid1_ext, rx.valid2_ext, rx.valid3_ext, rx.valid4_ext, rx.valid5_ext, rx.valid6_ext, rx.valid7_ext, rx_st.bardec0, rx_st.be0, rx_st.data0, rx_st.empty0, rx_st.eop0, rx_st.err0, rx_st.mask0, rx_st.ready0, rx_st.sop0, rx_st.valid0, test.in, tl_cfg.add, tl_cfg.ctl, tl_cfg.ctl_wr, tl_cfg.sts, tl_cfg.sts_wr, tx.cred0, tx.fifo_empty0, tx.out0, tx.out1, tx.out2, tx.out3, tx.out4, tx.out5, tx.out6, tx.out7, tx.compl0_ext, tx.compl1_ext, tx.compl2_ext, tx.compl3_ext, tx.compl4_ext, tx.compl5_ext, tx.compl6_ext, tx.compl7_ext, tx.data0_ext, tx.data1_ext, tx.data2_ext, tx.data3_ext, tx.data4_ext, tx.data5_ext, tx.data6_ext, tx.data7_ext, tx.datak0_ext, tx.datak1_ext, tx.datak2_ext, tx.datak3_ext, tx.datak4_ext, tx.datak5_ext, tx.datak6_ext, tx.datak7_ext, tx.detectrx_ext, tx.elecidle0_ext, tx.elecidle1_ext, tx.elecidle2_ext, tx.elecidle3_ext, tx.elecidle4_ext, tx.elecidle5_ext, tx.elecidle6_ext, tx.elecidle7_ext, tx_st.data0, tx_st.empty0, tx_st.eop0, tx_st.err0, tx_st.ready0, tx_st.sop0, tx_st.valid0);\nendmodule\n"
  },
  {
    "path": "generated/altera/ALTERA_PCIE_SV_WRAPPER.bsv",
    "content": "\n/*\n   ./importbvi.py\n   -o\n   ALTERA_PCIE_SV_WRAPPER.bsv\n   -I\n   PcieWrap\n   -P\n   PcieWrap\n   -r\n   pin_perst\n   -r\n   npor\n   -r\n   reset_status\n   -c\n   refclk\n   -c\n   coreclkout_hip\n   -f\n   serdes\n   -f\n   pld\n   -f\n   dl\n   -f\n   ev128\n   -f\n   ev1\n   -f\n   hotrst\n   -f\n   l2\n   -f\n   current\n   -f\n   derr\n   -f\n   lane\n   -f\n   ltssm\n   -f\n   reconfig\n   -f\n   tx_cred\n   -f\n   tx_par\n   -f\n   tx_s\n   -f\n   txd\n   -f\n   txe\n   -f\n   txc\n   -f\n   txm\n   -f\n   txs\n   -f\n   tx\n   -f\n   tx_cred\n   -f\n   rx_par\n   -f\n   rx_s\n   -f\n   rxd\n   -f\n   rxr\n   -f\n   rxe\n   -f\n   rxp\n   -f\n   rxs\n   -f\n   rxv\n   -f\n   rx\n   -f\n   cfg_par\n   -f\n   eidle\n   -f\n   power\n   -f\n   phy\n   -f\n   int_s\n   -f\n   cpl\n   -f\n   tl\n   -f\n   pm_e\n   -f\n   pme\n   -f\n   pm\n   -f\n   simu\n   -f\n   sim\n   -f\n   test_in\n   ../../out/de5/synthesis/altera_pcie_sv_hip_ast_wrapper.v\n*/\n\nimport Clocks::*;\nimport DefaultValue::*;\nimport XilinxCells::*;\nimport GetPut::*;\n\n(* always_ready, always_enabled *)\ninterface PciewrapApp;\n    method Bit#(1)     int_ack();\n    method Action      int_sts(Bit#(1) v);\n    method Bit#(1)     msi_ack();\n    method Action      msi_num(Bit#(5) v);\n    method Action      msi_req(Bit#(1) v);\n    method Action      msi_tc(Bit#(3) v);\nendinterface\n(* always_ready, always_enabled *)\ninterface PciewrapCfg_par;\n    method Bit#(1)     err();\nendinterface\n(* always_ready, always_enabled *)\ninterface PciewrapCoreclkout;\n    interface Clock     hip;\nendinterface\n(* always_ready, always_enabled *)\ninterface PciewrapCpl;\n    method Action      err(Bit#(7) v);\n    method Action      pending(Bit#(1) v);\nendinterface\n(* always_ready, always_enabled *)\ninterface PciewrapCurrent;\n    method Bit#(2)     speed();\nendinterface\n(* always_ready, always_enabled *)\ninterface PciewrapDerr;\n    method Bit#(1)     cor_ext_rcv();\n    method Bit#(1)     cor_ext_rpl();\n    method Bit#(1)     rpl();\nendinterface\n(* always_ready, always_enabled *)\ninterface PciewrapDl;\n    method Bit#(1)     up();\n    method Bit#(1)     up_exit();\nendinterface\n(* always_ready, always_enabled *)\ninterface PciewrapEidle;\n    method Bit#(3)     infersel0();\n    method Bit#(3)     infersel1();\n    method Bit#(3)     infersel2();\n    method Bit#(3)     infersel3();\n    method Bit#(3)     infersel4();\n    method Bit#(3)     infersel5();\n    method Bit#(3)     infersel6();\n    method Bit#(3)     infersel7();\nendinterface\n(* always_ready, always_enabled *)\ninterface PciewrapEv1;\n    method Bit#(1)     us();\nendinterface\n(* always_ready, always_enabled *)\ninterface PciewrapEv128;\n    method Bit#(1)     ns();\nendinterface\n(* always_ready, always_enabled *)\ninterface PciewrapHotrst;\n    method Bit#(1)     exit();\nendinterface\n(* always_ready, always_enabled *)\ninterface PciewrapHpg;\n    method Action      ctrler(Bit#(5) v);\nendinterface\n(* always_ready, always_enabled *)\ninterface PciewrapInt_s;\n    method Bit#(4)     tatus();\nendinterface\n(* always_ready, always_enabled *)\ninterface PciewrapKo;\n    method Bit#(12)     cpl_spc_data();\n    method Bit#(8)     cpl_spc_header();\nendinterface\n(* always_ready, always_enabled *)\ninterface PciewrapL2;\n    method Bit#(1)     exit();\nendinterface\n(* always_ready, always_enabled *)\ninterface PciewrapLane;\n    method Bit#(4)     act();\nendinterface\n(* always_ready, always_enabled *)\ninterface PciewrapLtssm;\n    method Bit#(5)     state();\nendinterface\n(* always_ready, always_enabled *)\ninterface PciewrapPhy;\n    method Action      status0(Bit#(1) v);\n    method Action      status1(Bit#(1) v);\n    method Action      status2(Bit#(1) v);\n    method Action      status3(Bit#(1) v);\n    method Action      status4(Bit#(1) v);\n    method Action      status5(Bit#(1) v);\n    method Action      status6(Bit#(1) v);\n    method Action      status7(Bit#(1) v);\nendinterface\n(* always_ready, always_enabled *)\n(* always_ready, always_enabled *)\ninterface PciewrapPld;\n    method Action      clk(Bit#(1) v);\n    method Bit#(1)     clk_inuse();\n    method Action      core_ready(Bit#(1) v);\nendinterface\n(* always_ready, always_enabled *)\ninterface PciewrapPm;\n    method Action      auxpwr(Bit#(1) v);\n    method Action      data(Bit#(10) v);\nendinterface\n(* always_ready, always_enabled *)\ninterface PciewrapPm_e;\n    method Action      vent(Bit#(1) v);\nendinterface\n(* always_ready, always_enabled *)\ninterface PciewrapPme;\n    method Action      to_cr(Bit#(1) v);\n    method Bit#(1)     to_sr();\nendinterface\n(* always_ready, always_enabled *)\ninterface PciewrapPower;\n    method Bit#(2)     down0();\n    method Bit#(2)     down1();\n    method Bit#(2)     down2();\n    method Bit#(2)     down3();\n    method Bit#(2)     down4();\n    method Bit#(2)     down5();\n    method Bit#(2)     down6();\n    method Bit#(2)     down7();\nendinterface\n(* always_ready, always_enabled *)\ninterface PciewrapReconfig;\n    method Bit#(460)     from_xcvr();\n    method Action      to_xcvr(Bit#(700) v);\nendinterface\n(* always_ready, always_enabled *)\ninterface PciewrapReset;\n    method Reset     status();\nendinterface\n(* always_ready, always_enabled *)\ninterface PciewrapRx;\n    method Action      in0(Bit#(1) v);\n    method Action      in1(Bit#(1) v);\n    method Action      in2(Bit#(1) v);\n    method Action      in3(Bit#(1) v);\n    method Action      in4(Bit#(1) v);\n    method Action      in5(Bit#(1) v);\n    method Action      in6(Bit#(1) v);\n    method Action      in7(Bit#(1) v);\n    method Action      data0(Bit#(8) v);\n    method Action      data1(Bit#(8) v);\n    method Action      data2(Bit#(8) v);\n    method Action      data3(Bit#(8) v);\n    method Action      data4(Bit#(8) v);\n    method Action      data5(Bit#(8) v);\n    method Action      data6(Bit#(8) v);\n    method Action      data7(Bit#(8) v);\n    method Action      datak0(Bit#(1) v);\n    method Action      datak1(Bit#(1) v);\n    method Action      datak2(Bit#(1) v);\n    method Action      datak3(Bit#(1) v);\n    method Action      datak4(Bit#(1) v);\n    method Action      datak5(Bit#(1) v);\n    method Action      datak6(Bit#(1) v);\n    method Action      datak7(Bit#(1) v);\n    method Action      elecidle0(Bit#(1) v);\n    method Action      elecidle1(Bit#(1) v);\n    method Action      elecidle2(Bit#(1) v);\n    method Action      elecidle3(Bit#(1) v);\n    method Action      elecidle4(Bit#(1) v);\n    method Action      elecidle5(Bit#(1) v);\n    method Action      elecidle6(Bit#(1) v);\n    method Action      elecidle7(Bit#(1) v);\n    method Bit#(1)     polarity0();\n    method Bit#(1)     polarity1();\n    method Bit#(1)     polarity2();\n    method Bit#(1)     polarity3();\n    method Bit#(1)     polarity4();\n    method Bit#(1)     polarity5();\n    method Bit#(1)     polarity6();\n    method Bit#(1)     polarity7();\n    method Action      status0(Bit#(3) v);\n    method Action      status1(Bit#(3) v);\n    method Action      status2(Bit#(3) v);\n    method Action      status3(Bit#(3) v);\n    method Action      status4(Bit#(3) v);\n    method Action      status5(Bit#(3) v);\n    method Action      status6(Bit#(3) v);\n    method Action      status7(Bit#(3) v);\n    method Action      valid0(Bit#(1) v);\n    method Action      valid1(Bit#(1) v);\n    method Action      valid2(Bit#(1) v);\n    method Action      valid3(Bit#(1) v);\n    method Action      valid4(Bit#(1) v);\n    method Action      valid5(Bit#(1) v);\n    method Action      valid6(Bit#(1) v);\n    method Action      valid7(Bit#(1) v);\nendinterface\n(* always_ready, always_enabled *)\ninterface PciewrapRx_par;\n    method Bit#(1)     err();\nendinterface\n(* always_ready, always_enabled *)\ninterface PciewrapRx_st;\n    method Bit#(8)     bar0();\n    method Bit#(16)    be0();\n    method Bit#(128)   data0();\n    method Bit#(2)     empty0();\n    method Bit#(1)     eop0();\n    method Bit#(1)     err0();\n    method Action      mask0(Bit#(1) v);\n    method Action      ready0(Bit#(1) v);\n    method Bit#(1)     sop0();\n    method Bit#(1)     valid0();\nendinterface\n(* always_ready, always_enabled *)\ninterface PciewrapSerdes;\n    method Bit#(1)     pll_locked();\nendinterface\n(* always_ready, always_enabled *)\ninterface PciewrapSim;\n    method Bit#(5)     ltssmstate();\n    method Bit#(2)     pipe_rate();\nendinterface\n(* always_ready, always_enabled *)\ninterface PciewrapTest;\n    method Action      in(Bit#(32) v);\nendinterface\n(* always_ready, always_enabled *)\ninterface PciewrapTestin;\n    method Bit#(1)     zero();\nendinterface\n(* always_ready, always_enabled *)\ninterface PciewrapTl;\n    method Bit#(4)     cfg_add();\n    method Bit#(32)     cfg_ctl();\n    method Bit#(53)     cfg_sts();\nendinterface\n(* always_ready, always_enabled *)\ninterface PciewrapTx;\n    method Bit#(1)     out0();\n    method Bit#(1)     out1();\n    method Bit#(1)     out2();\n    method Bit#(1)     out3();\n    method Bit#(1)     out4();\n    method Bit#(1)     out5();\n    method Bit#(1)     out6();\n    method Bit#(1)     out7();\n    method Bit#(1)     compl0();\n    method Bit#(1)     compl1();\n    method Bit#(1)     compl2();\n    method Bit#(1)     compl3();\n    method Bit#(1)     compl4();\n    method Bit#(1)     compl5();\n    method Bit#(1)     compl6();\n    method Bit#(1)     compl7();\n    method Bit#(8)     data0();\n    method Bit#(8)     data1();\n    method Bit#(8)     data2();\n    method Bit#(8)     data3();\n    method Bit#(8)     data4();\n    method Bit#(8)     data5();\n    method Bit#(8)     data6();\n    method Bit#(8)     data7();\n    method Bit#(1)     datak0();\n    method Bit#(1)     datak1();\n    method Bit#(1)     datak2();\n    method Bit#(1)     datak3();\n    method Bit#(1)     datak4();\n    method Bit#(1)     datak5();\n    method Bit#(1)     datak6();\n    method Bit#(1)     datak7();\n    method Bit#(1)     deemph0();\n    method Bit#(1)     deemph1();\n    method Bit#(1)     deemph2();\n    method Bit#(1)     deemph3();\n    method Bit#(1)     deemph4();\n    method Bit#(1)     deemph5();\n    method Bit#(1)     deemph6();\n    method Bit#(1)     deemph7();\n    method Bit#(1)     detectrx0();\n    method Bit#(1)     detectrx1();\n    method Bit#(1)     detectrx2();\n    method Bit#(1)     detectrx3();\n    method Bit#(1)     detectrx4();\n    method Bit#(1)     detectrx5();\n    method Bit#(1)     detectrx6();\n    method Bit#(1)     detectrx7();\n    method Bit#(1)     elecidle0();\n    method Bit#(1)     elecidle1();\n    method Bit#(1)     elecidle2();\n    method Bit#(1)     elecidle3();\n    method Bit#(1)     elecidle4();\n    method Bit#(1)     elecidle5();\n    method Bit#(1)     elecidle6();\n    method Bit#(1)     elecidle7();\n    method Bit#(3)     margin0();\n    method Bit#(3)     margin1();\n    method Bit#(3)     margin2();\n    method Bit#(3)     margin3();\n    method Bit#(3)     margin4();\n    method Bit#(3)     margin5();\n    method Bit#(3)     margin6();\n    method Bit#(3)     margin7();\n    method Bit#(1)     swing0();\n    method Bit#(1)     swing1();\n    method Bit#(1)     swing2();\n    method Bit#(1)     swing3();\n    method Bit#(1)     swing4();\n    method Bit#(1)     swing5();\n    method Bit#(1)     swing6();\n    method Bit#(1)     swing7();\nendinterface\n(* always_ready, always_enabled *)\ninterface PciewrapTx_cred;\n    method Bit#(12)     datafccp();\n    method Bit#(12)     datafcnp();\n    method Bit#(12)     datafcp();\n    method Bit#(6)     fchipcons();\n    method Bit#(6)     fcinfinite();\n    method Bit#(8)     hdrfccp();\n    method Bit#(8)     hdrfcnp();\n    method Bit#(8)     hdrfcp();\nendinterface\n(* always_ready, always_enabled *)\ninterface PciewrapTx_par;\n    method Bit#(2)     err();\nendinterface\n(* always_ready, always_enabled *)\ninterface PciewrapTx_st;\n    method Action      data0(Bit#(128) v);\n    method Action      empty0(Bit#(2) v);\n    method Action      eop0(Bit#(1) v);\n    method Action      err0(Bit#(1) v);\n    method Bit#(1)     ready0();\n    method Action      sop0(Bit#(1) v);\n    method Action      valid0(Bit#(1) v);\nendinterface\n(* always_ready, always_enabled *)\ninterface PcieS5Wrap;\n    interface PciewrapApp     app;\n    interface PciewrapCfg_par     cfg_par;\n    interface PciewrapCoreclkout     coreclkout;\n    interface PciewrapCpl     cpl;\n    interface PciewrapCurrent     current;\n    interface PciewrapDerr     derr;\n    interface PciewrapDl     dl;\n    interface PciewrapEidle     eidle;\n    interface PciewrapEv128     ev128;\n    interface PciewrapEv1     ev1;\n    interface PciewrapHotrst     hotrst;\n    interface PciewrapHpg     hpg;\n    interface PciewrapInt_s     int_s;\n    interface PciewrapKo     ko;\n    interface PciewrapL2     l2;\n    interface PciewrapLane     lane;\n    interface PciewrapLtssm     ltssm;\n    interface PciewrapPhy     phy;\n    interface PciewrapPld     pld;\n    interface PciewrapPm     pm;\n    interface PciewrapPm_e     pm_e;\n    interface PciewrapPme     pme;\n    interface PciewrapPower     power;\n    interface PciewrapReconfig     reconfig;\n    interface PciewrapReset     reset;\n    interface PciewrapRx     rx;\n    interface PciewrapRx_par     rx_par;\n    interface PciewrapRx_st     rx_st;\n    interface PciewrapSerdes     serdes;\n    interface PciewrapSim     sim;\n    interface PciewrapTest     test;\n    interface PciewrapTestin     testin;\n    interface PciewrapTl     tl;\n    interface PciewrapTx_cred     tx_cred;\n    interface PciewrapTx     tx;\n    interface PciewrapTx_par     tx_par;\n    interface PciewrapTx_st     tx_st;\nendinterface\nimport \"BVI\" altera_pcie_sv_hip_ast_wrapper =\nmodule mkPPS5Wrap#(Clock refclk, Reset npor, Reset pin_perst, Reset refclk_reset)(PcieS5Wrap);\n    default_clock clk();\n    default_reset rst();\n    input_reset npor(npor) = npor;\n        input_reset pin_perst(pin_perst) = pin_perst;\n    input_clock refclk(refclk) = refclk;\n    input_reset refclk_reset() = refclk_reset; /* from clock*/\n    interface PciewrapApp     app;\n        method app_int_ack int_ack() clocked_by(coreclkout.hip);\n        method int_sts(app_int_sts) clocked_by(coreclkout.hip) enable((*inhigh*) EN_app_int_sts);\n        method app_msi_ack msi_ack() clocked_by(coreclkout.hip);\n        method msi_num(app_msi_num) clocked_by(coreclkout.hip) enable((*inhigh*) EN_app_msi_num);\n        method msi_req(app_msi_req) clocked_by(coreclkout.hip) enable((*inhigh*) EN_app_msi_req);\n        method msi_tc(app_msi_tc) clocked_by(coreclkout.hip) enable((*inhigh*) EN_app_msi_tc);\n    endinterface\n    interface PciewrapCfg_par     cfg_par;\n        method cfg_par_err err() clocked_by(coreclkout.hip);\n    endinterface\n    interface PciewrapCoreclkout     coreclkout;\n        output_clock hip(coreclkout_hip);\n    endinterface\n    interface PciewrapCpl     cpl;\n        method err(cpl_err) clocked_by(coreclkout.hip) enable((*inhigh*) EN_cpl_err);\n        method pending(cpl_pending) clocked_by(coreclkout_hip) enable((*inhigh*) EN_cpl_pending);\n    endinterface\n    interface PciewrapCurrent     current;\n        method currentspeed speed() clocked_by(coreclkout.hip) reset_by(no_reset);\n    endinterface\n    interface PciewrapDerr     derr;\n        method derr_cor_ext_rcv cor_ext_rcv()clocked_by(coreclkout.hip);\n        method derr_cor_ext_rpl cor_ext_rpl()clocked_by(coreclkout.hip);\n        method derr_rpl rpl() clocked_by(coreclkout.hip) reset_by(no_reset);\n    endinterface\n    interface PciewrapDl     dl;\n        method dlup up() clocked_by(coreclkout.hip) reset_by(no_reset);\n        method dlup_exit up_exit() clocked_by(coreclkout.hip) reset_by(no_reset);\n    endinterface\n    interface PciewrapEidle     eidle;\n        method eidleinfersel0 infersel0();\n        method eidleinfersel1 infersel1();\n        method eidleinfersel2 infersel2();\n        method eidleinfersel3 infersel3();\n        method eidleinfersel4 infersel4();\n        method eidleinfersel5 infersel5();\n        method eidleinfersel6 infersel6();\n        method eidleinfersel7 infersel7();\n    endinterface\n    interface PciewrapEv128     ev128;\n        method ev128ns ns()clocked_by(coreclkout.hip);\n    endinterface\n    interface PciewrapEv1     ev1;\n        method ev1us us()clocked_by(coreclkout.hip);\n    endinterface\n    interface PciewrapHotrst     hotrst;\n        method hotrst_exit exit() clocked_by(coreclkout.hip) reset_by(no_reset);\n    endinterface\n    interface PciewrapHpg     hpg;\n        method ctrler(hpg_ctrler) enable((*inhigh*) EN_hpg_ctrler);\n    endinterface\n    interface PciewrapInt_s     int_s;\n        method int_status tatus() clocked_by(coreclkout.hip);\n    endinterface\n    interface PciewrapKo     ko;\n        method ko_cpl_spc_data cpl_spc_data()clocked_by(coreclkout.hip);\n        method ko_cpl_spc_header cpl_spc_header()clocked_by(coreclkout.hip);\n    endinterface\n    interface PciewrapL2     l2;\n        method l2_exit exit()clocked_by(coreclkout.hip) reset_by (no_reset);\n    endinterface\n    interface PciewrapLane     lane;\n        method lane_act act()clocked_by(coreclkout.hip) reset_by (no_reset);\n    endinterface\n    interface PciewrapLtssm     ltssm;\n        method ltssmstate state() clocked_by(coreclkout.hip) reset_by(no_reset);\n    endinterface\n    interface PciewrapPhy     phy;\n        method status0(phystatus0) enable((*inhigh*) EN_phystatus0);\n        method status1(phystatus1) enable((*inhigh*) EN_phystatus1);\n        method status2(phystatus2) enable((*inhigh*) EN_phystatus2);\n        method status3(phystatus3) enable((*inhigh*) EN_phystatus3);\n        method status4(phystatus4) enable((*inhigh*) EN_phystatus4);\n        method status5(phystatus5) enable((*inhigh*) EN_phystatus5);\n        method status6(phystatus6) enable((*inhigh*) EN_phystatus6);\n        method status7(phystatus7) enable((*inhigh*) EN_phystatus7);\n    endinterface\n    interface PciewrapPld     pld;\n        method clk(pld_clk) enable((*inhigh*) EN_pld_clk);\n        method pld_clk_inuse clk_inuse() clocked_by(coreclkout.hip);\n        method core_ready(pld_core_ready) clocked_by(coreclkout_hip) enable((*inhigh*) EN_pld_core_ready);\n    endinterface\n    interface PciewrapPm     pm;\n        method auxpwr(pm_auxpwr) enable((*inhigh*) EN_pm_auxpwr);\n        method data(pm_data) enable((*inhigh*) EN_pm_data);\n    endinterface\n    interface PciewrapPm_e     pm_e;\n        method vent(pm_event) enable((*inhigh*) EN_pm_event);\n    endinterface\n    interface PciewrapPme     pme;\n        method to_cr(pme_to_cr) enable((*inhigh*) EN_pme_to_cr);\n        method pme_to_sr to_sr();\n    endinterface\n    interface PciewrapPower     power;\n        method powerdown0 down0();\n        method powerdown1 down1();\n        method powerdown2 down2();\n        method powerdown3 down3();\n        method powerdown4 down4();\n        method powerdown5 down5();\n        method powerdown6 down6();\n        method powerdown7 down7();\n    endinterface\n    interface PciewrapReconfig     reconfig;\n        method reconfig_from_xcvr from_xcvr();\n        method to_xcvr(reconfig_to_xcvr) enable((*inhigh*) EN_reconfig_to_xcvr);\n    endinterface\n    interface PciewrapReset     reset;\n        output_reset status(reset_status);\n    endinterface\n    interface PciewrapRx     rx;\n        method in0(rx_in0) enable((*inhigh*) EN_rx_in0);\n        method in1(rx_in1) enable((*inhigh*) EN_rx_in1);\n        method in2(rx_in2) enable((*inhigh*) EN_rx_in2);\n        method in3(rx_in3) enable((*inhigh*) EN_rx_in3);\n        method in4(rx_in4) enable((*inhigh*) EN_rx_in4);\n        method in5(rx_in5) enable((*inhigh*) EN_rx_in5);\n        method in6(rx_in6) enable((*inhigh*) EN_rx_in6);\n        method in7(rx_in7) enable((*inhigh*) EN_rx_in7);\n        method data0(rxdata0) enable((*inhigh*) EN_rxdata0);\n        method data1(rxdata1) enable((*inhigh*) EN_rxdata1);\n        method data2(rxdata2) enable((*inhigh*) EN_rxdata2);\n        method data3(rxdata3) enable((*inhigh*) EN_rxdata3);\n        method data4(rxdata4) enable((*inhigh*) EN_rxdata4);\n        method data5(rxdata5) enable((*inhigh*) EN_rxdata5);\n        method data6(rxdata6) enable((*inhigh*) EN_rxdata6);\n        method data7(rxdata7) enable((*inhigh*) EN_rxdata7);\n        method datak0(rxdatak0) enable((*inhigh*) EN_rxdatak0);\n        method datak1(rxdatak1) enable((*inhigh*) EN_rxdatak1);\n        method datak2(rxdatak2) enable((*inhigh*) EN_rxdatak2);\n        method datak3(rxdatak3) enable((*inhigh*) EN_rxdatak3);\n        method datak4(rxdatak4) enable((*inhigh*) EN_rxdatak4);\n        method datak5(rxdatak5) enable((*inhigh*) EN_rxdatak5);\n        method datak6(rxdatak6) enable((*inhigh*) EN_rxdatak6);\n        method datak7(rxdatak7) enable((*inhigh*) EN_rxdatak7);\n        method elecidle0(rxelecidle0) enable((*inhigh*) EN_rxelecidle0);\n        method elecidle1(rxelecidle1) enable((*inhigh*) EN_rxelecidle1);\n        method elecidle2(rxelecidle2) enable((*inhigh*) EN_rxelecidle2);\n        method elecidle3(rxelecidle3) enable((*inhigh*) EN_rxelecidle3);\n        method elecidle4(rxelecidle4) enable((*inhigh*) EN_rxelecidle4);\n        method elecidle5(rxelecidle5) enable((*inhigh*) EN_rxelecidle5);\n        method elecidle6(rxelecidle6) enable((*inhigh*) EN_rxelecidle6);\n        method elecidle7(rxelecidle7) enable((*inhigh*) EN_rxelecidle7);\n        method rxpolarity0 polarity0();\n        method rxpolarity1 polarity1();\n        method rxpolarity2 polarity2();\n        method rxpolarity3 polarity3();\n        method rxpolarity4 polarity4();\n        method rxpolarity5 polarity5();\n        method rxpolarity6 polarity6();\n        method rxpolarity7 polarity7();\n        method status0(rxstatus0) enable((*inhigh*) EN_rxstatus0);\n        method status1(rxstatus1) enable((*inhigh*) EN_rxstatus1);\n        method status2(rxstatus2) enable((*inhigh*) EN_rxstatus2);\n        method status3(rxstatus3) enable((*inhigh*) EN_rxstatus3);\n        method status4(rxstatus4) enable((*inhigh*) EN_rxstatus4);\n        method status5(rxstatus5) enable((*inhigh*) EN_rxstatus5);\n        method status6(rxstatus6) enable((*inhigh*) EN_rxstatus6);\n        method status7(rxstatus7) enable((*inhigh*) EN_rxstatus7);\n        method valid0(rxvalid0) enable((*inhigh*) EN_rxvalid0);\n        method valid1(rxvalid1) enable((*inhigh*) EN_rxvalid1);\n        method valid2(rxvalid2) enable((*inhigh*) EN_rxvalid2);\n        method valid3(rxvalid3) enable((*inhigh*) EN_rxvalid3);\n        method valid4(rxvalid4) enable((*inhigh*) EN_rxvalid4);\n        method valid5(rxvalid5) enable((*inhigh*) EN_rxvalid5);\n        method valid6(rxvalid6) enable((*inhigh*) EN_rxvalid6);\n        method valid7(rxvalid7) enable((*inhigh*) EN_rxvalid7);\n    endinterface\n    interface PciewrapRx_par     rx_par;\n        method rx_par_err err()clocked_by(coreclkout.hip);\n    endinterface\n    interface PciewrapRx_st     rx_st;\n        method rx_st_bar   bar0() clocked_by(coreclkout.hip);\n        method rx_st_be    be0() clocked_by(coreclkout.hip);\n        method rx_st_data  data0() clocked_by(coreclkout.hip);\n        method rx_st_empty empty0() clocked_by(coreclkout.hip);\n        method rx_st_eop   eop0() clocked_by(coreclkout.hip);\n        method rx_st_err   err0() clocked_by(coreclkout.hip);\n        method mask0(rx_st_mask) clocked_by(coreclkout.hip) enable((*inhigh*) EN_rx_st_mask);\n        method ready0(rx_st_ready) clocked_by(coreclkout.hip) enable((*inhigh*) EN_rx_st_ready);\n        method rx_st_sop   sop0() clocked_by(coreclkout.hip);\n        method rx_st_valid valid0() clocked_by(coreclkout.hip);\n    endinterface\n    interface PciewrapSerdes     serdes;\n        method serdes_pll_locked pll_locked()clocked_by(coreclkout_hip);\n    endinterface\n    interface PciewrapSim     sim;\n        method sim_ltssmstate ltssmstate();\n        method sim_pipe_rate pipe_rate();\n    endinterface\n    interface PciewrapTest     test;\n        method in(test_in) enable((*inhigh*) EN_test_in);\n    endinterface\n    interface PciewrapTestin     testin;\n        method testin_zero zero();\n    endinterface\n    interface PciewrapTl     tl;\n        method tl_cfg_add cfg_add() clocked_by(coreclkout_hip) reset_by (no_reset);\n        method tl_cfg_ctl cfg_ctl() clocked_by(coreclkout_hip) reset_by (no_reset);\n        method tl_cfg_sts cfg_sts() clocked_by(coreclkout_hip) reset_by (no_reset);\n    endinterface\n    interface PciewrapTx_cred     tx_cred;\n        method tx_cred_datafccp datafccp()clocked_by(coreclkout.hip);\n        method tx_cred_datafcnp datafcnp()clocked_by(coreclkout.hip);\n        method tx_cred_datafcp datafcp()clocked_by(coreclkout.hip);\n        method tx_cred_fchipcons fchipcons()clocked_by(coreclkout.hip);\n        method tx_cred_fcinfinite fcinfinite()clocked_by(coreclkout.hip);\n        method tx_cred_hdrfccp hdrfccp()clocked_by(coreclkout.hip);\n        method tx_cred_hdrfcnp hdrfcnp()clocked_by(coreclkout.hip);\n        method tx_cred_hdrfcp hdrfcp()clocked_by(coreclkout.hip);\n    endinterface\n    interface PciewrapTx     tx;\n        method tx_out0 out0();\n        method tx_out1 out1();\n        method tx_out2 out2();\n        method tx_out3 out3();\n        method tx_out4 out4();\n        method tx_out5 out5();\n        method tx_out6 out6();\n        method tx_out7 out7();\n        method txcompl0 compl0();\n        method txcompl1 compl1();\n        method txcompl2 compl2();\n        method txcompl3 compl3();\n        method txcompl4 compl4();\n        method txcompl5 compl5();\n        method txcompl6 compl6();\n        method txcompl7 compl7();\n        method txdata0 data0();\n        method txdata1 data1();\n        method txdata2 data2();\n        method txdata3 data3();\n        method txdata4 data4();\n        method txdata5 data5();\n        method txdata6 data6();\n        method txdata7 data7();\n        method txdatak0 datak0();\n        method txdatak1 datak1();\n        method txdatak2 datak2();\n        method txdatak3 datak3();\n        method txdatak4 datak4();\n        method txdatak5 datak5();\n        method txdatak6 datak6();\n        method txdatak7 datak7();\n        method txdeemph0 deemph0();\n        method txdeemph1 deemph1();\n        method txdeemph2 deemph2();\n        method txdeemph3 deemph3();\n        method txdeemph4 deemph4();\n        method txdeemph5 deemph5();\n        method txdeemph6 deemph6();\n        method txdeemph7 deemph7();\n        method txdetectrx0 detectrx0();\n        method txdetectrx1 detectrx1();\n        method txdetectrx2 detectrx2();\n        method txdetectrx3 detectrx3();\n        method txdetectrx4 detectrx4();\n        method txdetectrx5 detectrx5();\n        method txdetectrx6 detectrx6();\n        method txdetectrx7 detectrx7();\n        method txelecidle0 elecidle0();\n        method txelecidle1 elecidle1();\n        method txelecidle2 elecidle2();\n        method txelecidle3 elecidle3();\n        method txelecidle4 elecidle4();\n        method txelecidle5 elecidle5();\n        method txelecidle6 elecidle6();\n        method txelecidle7 elecidle7();\n        method txmargin0 margin0();\n        method txmargin1 margin1();\n        method txmargin2 margin2();\n        method txmargin3 margin3();\n        method txmargin4 margin4();\n        method txmargin5 margin5();\n        method txmargin6 margin6();\n        method txmargin7 margin7();\n        method txswing0 swing0();\n        method txswing1 swing1();\n        method txswing2 swing2();\n        method txswing3 swing3();\n        method txswing4 swing4();\n        method txswing5 swing5();\n        method txswing6 swing6();\n        method txswing7 swing7();\n    endinterface\n    interface PciewrapTx_par     tx_par;\n        method tx_par_err err()clocked_by(coreclkout.hip);\n    endinterface\n    interface PciewrapTx_st     tx_st;\n        method data0(tx_st_data)    clocked_by(coreclkout.hip) enable((*inhigh*) EN_tx_st_data);\n        method empty0(tx_st_empty)  clocked_by(coreclkout.hip) enable((*inhigh*) EN_tx_st_empty);\n        method eop0(tx_st_eop)      clocked_by(coreclkout.hip) enable((*inhigh*) EN_tx_st_eop);\n        method err0(tx_st_err)      clocked_by(coreclkout_hip) enable((*inhigh*) EN_tx_st_err);\n        method tx_st_ready ready0() clocked_by(coreclkout.hip);\n        method sop0(tx_st_sop)      clocked_by(coreclkout.hip) enable((*inhigh*) EN_tx_st_sop);\n        method valid0(tx_st_valid)  clocked_by(coreclkout.hip) enable((*inhigh*) EN_tx_st_valid);\n    endinterface\n    schedule (app.int_ack, app.int_sts, app.msi_ack, app.msi_num, app.msi_req, app.msi_tc, cfg_par.err, cpl.err, cpl.pending, current.speed, derr.cor_ext_rcv, derr.cor_ext_rpl, derr.rpl, dl.up, dl.up_exit, eidle.infersel0, eidle.infersel1, eidle.infersel2, eidle.infersel3, eidle.infersel4, eidle.infersel5, eidle.infersel6, eidle.infersel7, ev128.ns, ev1.us, hotrst.exit, hpg.ctrler, int_s.tatus, ko.cpl_spc_data, ko.cpl_spc_header, l2.exit, lane.act, ltssm.state, phy.status0, phy.status1, phy.status2, phy.status3, phy.status4, phy.status5, phy.status6, phy.status7, pld.clk, pld.clk_inuse, pld.core_ready, pm.auxpwr, pm.data, pm_e.vent, pme.to_cr, pme.to_sr, power.down0, power.down1, power.down2, power.down3, power.down4, power.down5, power.down6, power.down7, reconfig.from_xcvr, reconfig.to_xcvr, rx.in0, rx.in1, rx.in2, rx.in3, rx.in4, rx.in5, rx.in6, rx.in7, rx_par.err, rx_st.bar0, rx_st.be0, rx_st.data0, rx_st.empty0, rx_st.eop0, rx_st.err0, rx_st.mask0, rx_st.ready0, rx_st.sop0, rx_st.valid0, rx.data0, rx.data1, rx.data2, rx.data3, rx.data4, rx.data5, rx.data6, rx.data7, rx.datak0, rx.datak1, rx.datak2, rx.datak3, rx.datak4, rx.datak5, rx.datak6, rx.datak7, rx.elecidle0, rx.elecidle1, rx.elecidle2, rx.elecidle3, rx.elecidle4, rx.elecidle5, rx.elecidle6, rx.elecidle7, rx.polarity0, rx.polarity1, rx.polarity2, rx.polarity3, rx.polarity4, rx.polarity5, rx.polarity6, rx.polarity7, rx.status0, rx.status1, rx.status2, rx.status3, rx.status4, rx.status5, rx.status6, rx.status7, rx.valid0, rx.valid1, rx.valid2, rx.valid3, rx.valid4, rx.valid5, rx.valid6, rx.valid7, serdes.pll_locked, sim.ltssmstate, sim.pipe_rate, test.in, testin.zero, tl.cfg_add, tl.cfg_ctl, tl.cfg_sts, tx_cred.datafccp, tx_cred.datafcnp, tx_cred.datafcp, tx_cred.fchipcons, tx_cred.fcinfinite, tx_cred.hdrfccp, tx_cred.hdrfcnp, tx_cred.hdrfcp, tx.out0, tx.out1, tx.out2, tx.out3, tx.out4, tx.out5, tx.out6, tx.out7, tx_par.err, tx_st.data0, tx_st.empty0, tx_st.eop0, tx_st.err0, tx_st.ready0, tx_st.sop0, tx_st.valid0, tx.compl0, tx.compl1, tx.compl2, tx.compl3, tx.compl4, tx.compl5, tx.compl6, tx.compl7, tx.data0, tx.data1, tx.data2, tx.data3, tx.data4, tx.data5, tx.data6, tx.data7, tx.datak0, tx.datak1, tx.datak2, tx.datak3, tx.datak4, tx.datak5, tx.datak6, tx.datak7, tx.deemph0, tx.deemph1, tx.deemph2, tx.deemph3, tx.deemph4, tx.deemph5, tx.deemph6, tx.deemph7, tx.detectrx0, tx.detectrx1, tx.detectrx2, tx.detectrx3, tx.detectrx4, tx.detectrx5, tx.detectrx6, tx.detectrx7, tx.elecidle0, tx.elecidle1, tx.elecidle2, tx.elecidle3, tx.elecidle4, tx.elecidle5, tx.elecidle6, tx.elecidle7, tx.margin0, tx.margin1, tx.margin2, tx.margin3, tx.margin4, tx.margin5, tx.margin6, tx.margin7, tx.swing0, tx.swing1, tx.swing2, tx.swing3, tx.swing4, tx.swing5, tx.swing6, tx.swing7) CF (app.int_ack, app.int_sts, app.msi_ack, app.msi_num, app.msi_req, app.msi_tc, cfg_par.err, cpl.err, cpl.pending, current.speed, derr.cor_ext_rcv, derr.cor_ext_rpl, derr.rpl, dl.up, dl.up_exit, eidle.infersel0, eidle.infersel1, eidle.infersel2, eidle.infersel3, eidle.infersel4, eidle.infersel5, eidle.infersel6, eidle.infersel7, ev128.ns, ev1.us, hotrst.exit, hpg.ctrler, int_s.tatus, ko.cpl_spc_data, ko.cpl_spc_header, l2.exit, lane.act, ltssm.state, phy.status0, phy.status1, phy.status2, phy.status3, phy.status4, phy.status5, phy.status6, phy.status7, pld.clk, pld.clk_inuse, pld.core_ready, pm.auxpwr, pm.data, pm_e.vent, pme.to_cr, pme.to_sr, power.down0, power.down1, power.down2, power.down3, power.down4, power.down5, power.down6, power.down7, reconfig.from_xcvr, reconfig.to_xcvr, rx.in0, rx.in1, rx.in2, rx.in3, rx.in4, rx.in5, rx.in6, rx.in7, rx_par.err, rx_st.bar0, rx_st.be0, rx_st.data0, rx_st.empty0, rx_st.eop0, rx_st.err0, rx_st.mask0, rx_st.ready0, rx_st.sop0, rx_st.valid0, rx.data0, rx.data1, rx.data2, rx.data3, rx.data4, rx.data5, rx.data6, rx.data7, rx.datak0, rx.datak1, rx.datak2, rx.datak3, rx.datak4, rx.datak5, rx.datak6, rx.datak7, rx.elecidle0, rx.elecidle1, rx.elecidle2, rx.elecidle3, rx.elecidle4, rx.elecidle5, rx.elecidle6, rx.elecidle7, rx.polarity0, rx.polarity1, rx.polarity2, rx.polarity3, rx.polarity4, rx.polarity5, rx.polarity6, rx.polarity7, rx.status0, rx.status1, rx.status2, rx.status3, rx.status4, rx.status5, rx.status6, rx.status7, rx.valid0, rx.valid1, rx.valid2, rx.valid3, rx.valid4, rx.valid5, rx.valid6, rx.valid7, serdes.pll_locked, sim.ltssmstate, sim.pipe_rate, test.in, testin.zero, tl.cfg_add, tl.cfg_ctl, tl.cfg_sts, tx_cred.datafccp, tx_cred.datafcnp, tx_cred.datafcp, tx_cred.fchipcons, tx_cred.fcinfinite, tx_cred.hdrfccp, tx_cred.hdrfcnp, tx_cred.hdrfcp, tx.out0, tx.out1, tx.out2, tx.out3, tx.out4, tx.out5, tx.out6, tx.out7, tx_par.err, tx_st.data0, tx_st.empty0, tx_st.eop0, tx_st.err0, tx_st.ready0, tx_st.sop0, tx_st.valid0, tx.compl0, tx.compl1, tx.compl2, tx.compl3, tx.compl4, tx.compl5, tx.compl6, tx.compl7, tx.data0, tx.data1, tx.data2, tx.data3, tx.data4, tx.data5, tx.data6, tx.data7, tx.datak0, tx.datak1, tx.datak2, tx.datak3, tx.datak4, tx.datak5, tx.datak6, tx.datak7, tx.deemph0, tx.deemph1, tx.deemph2, tx.deemph3, tx.deemph4, tx.deemph5, tx.deemph6, tx.deemph7, tx.detectrx0, tx.detectrx1, tx.detectrx2, tx.detectrx3, tx.detectrx4, tx.detectrx5, tx.detectrx6, tx.detectrx7, tx.elecidle0, tx.elecidle1, tx.elecidle2, tx.elecidle3, tx.elecidle4, tx.elecidle5, tx.elecidle6, tx.elecidle7, tx.margin0, tx.margin1, tx.margin2, tx.margin3, tx.margin4, tx.margin5, tx.margin6, tx.margin7, tx.swing0, tx.swing1, tx.swing2, tx.swing3, tx.swing4, tx.swing5, tx.swing6, tx.swing7);\nendmodule\n"
  },
  {
    "path": "generated/altera/ALTERA_PLL_WRAPPER.bsv",
    "content": "\n/*\n   ./importbvi.py\n   -o\n   ALTERA_PLL_WRAPPER.bsv\n   -I\n   PciePllWrap\n   -P\n   PciePllWrap\n   -c\n   refclk\n   -r\n   rst\n   -f\n   out\n   -f\n   locked\n   ../../out/de5/synthesis/altera_pll_wrapper.v\n*/\n\nimport Clocks::*;\nimport DefaultValue::*;\nimport XilinxCells::*;\nimport GetPut::*;\n\n(* always_ready, always_enabled *)\ninterface PciepllwrapOut;\n    method Bit#(1)     clk_0();\nendinterface\n(* always_ready, always_enabled *)\ninterface PciePllWrap;\n    method Bit#(1)     locked();\n    interface PciepllwrapOut     out;\nendinterface\nimport \"BVI\" altera_pll_wrapper =\nmodule mkPciePllWrap#(Clock refclk, Reset refclk_reset, Reset rst)(PciePllWrap);\n    default_clock clk();\n    default_reset rst();\n    input_clock refclk(refclk) = refclk;\n    input_reset refclk_reset() = refclk_reset; /* from clock*/\n    input_reset reset(rst) = rst;\n    method locked locked();\n    interface PciepllwrapOut     out;\n        method outclk_0 clk_0();\n    endinterface\n    schedule (locked, out.clk_0) CF (locked, out.clk_0);\nendmodule\n"
  },
  {
    "path": "generated/altera/ALTERA_XCVR_RECONFIG_WRAPPER.bsv",
    "content": "\n/*\n   ./importbvi.py\n   -o\n   ALTERA_XCVR_RECONFIG_WRAPPER.bsv\n   -I\n   XcvrReconfigWrap\n   -P\n   XcvrReconfigWrap\n   -c\n   mgmt_clk_clk\n   -r\n   mgmt_rst_reset\n   -f\n   reconfig_mgmt\n   -f\n   mgmt\n   ../../out/de5/synthesis/alt_xcvr_reconfig_wrapper.v\n*/\n\nimport Clocks::*;\nimport DefaultValue::*;\nimport XilinxCells::*;\nimport GetPut::*;\n\n(* always_ready, always_enabled *)\n(* always_ready, always_enabled *)\ninterface XcvrreconfigwrapReconfig;\n    method Bit#(1)     busy();\n    method Action      from_xcvr(Bit#(460) v);\n    method Bit#(700)     to_xcvr();\nendinterface\n(* always_ready, always_enabled *)\ninterface XcvrreconfigwrapReconfig_mgmt;\n    method Action      address(Bit#(7) v);\n    method Action      read(Bit#(1) v);\n    method Bit#(32)     readdata();\n    method Bit#(1)     waitrequest();\n    method Action      write(Bit#(1) v);\n    method Action      writedata(Bit#(32) v);\nendinterface\n(* always_ready, always_enabled *)\ninterface XcvrReconfigWrap;\n    interface XcvrreconfigwrapReconfig     reconfig;\n    interface XcvrreconfigwrapReconfig_mgmt     reconfig_mgmt;\nendinterface\nimport \"BVI\" alt_xcvr_reconfig_wrapper =\nmodule mkXcvrReconfigWrap#(Clock mgmt_clk_clk, Reset mgmt_clk_clk_reset, Reset mgmt_rst_reset)(XcvrReconfigWrap);\n    default_clock clk();\n    default_reset rst();\n        input_clock mgmt_clk_clk(mgmt_clk_clk) = mgmt_clk_clk;\n        input_reset mgmt_clk_clk_reset() = mgmt_clk_clk_reset; /* from clock*/\n        input_reset mgmt_rst_reset(mgmt_rst_reset) = mgmt_rst_reset;\n    interface XcvrreconfigwrapReconfig     reconfig;\n        method reconfig_busy busy();\n        method from_xcvr(reconfig_from_xcvr) enable((*inhigh*) EN_reconfig_from_xcvr);\n        method reconfig_to_xcvr to_xcvr();\n    endinterface\n    interface XcvrreconfigwrapReconfig_mgmt     reconfig_mgmt;\n        method address(reconfig_mgmt_address) enable((*inhigh*) EN_reconfig_mgmt_address);\n        method read(reconfig_mgmt_read) enable((*inhigh*) EN_reconfig_mgmt_read);\n        method reconfig_mgmt_readdata readdata();\n        method reconfig_mgmt_waitrequest waitrequest();\n        method write(reconfig_mgmt_write) enable((*inhigh*) EN_reconfig_mgmt_write);\n        method writedata(reconfig_mgmt_writedata) enable((*inhigh*) EN_reconfig_mgmt_writedata);\n    endinterface\n    schedule (reconfig.busy, reconfig.from_xcvr, reconfig.to_xcvr, reconfig_mgmt.address, reconfig_mgmt.read, reconfig_mgmt.readdata, reconfig_mgmt.waitrequest, reconfig_mgmt.write, reconfig_mgmt.writedata) CF (reconfig.busy, reconfig.from_xcvr, reconfig.to_xcvr, reconfig_mgmt.address, reconfig_mgmt.read, reconfig_mgmt.readdata, reconfig_mgmt.waitrequest, reconfig_mgmt.write, reconfig_mgmt.writedata);\nendmodule\n"
  },
  {
    "path": "generated/cpp/GeneratedTypes.h",
    "content": "#ifndef __GENERATED_TYPES__\n#define __GENERATED_TYPES__\n#include \"portal.h\"\n#ifdef __cplusplus\nextern \"C\" {\n#endif\ntypedef enum ChannelType { ChannelType_Read, ChannelType_Write } ChannelType;\ntypedef struct DmaDbgRec {\n    uint32_t x : 32;\n    uint32_t y : 32;\n    uint32_t z : 32;\n    uint32_t w : 32;\n} DmaDbgRec;\ntypedef enum DmaErrorType { DmaErrorNone, DmaErrorSGLIdOutOfRange_r, DmaErrorSGLIdOutOfRange_w, DmaErrorMMUOutOfRange_r, DmaErrorMMUOutOfRange_w, DmaErrorOffsetOutOfRange, DmaErrorSGLIdInvalid, DmaErrorTileTagOutOfRange } DmaErrorType;\ntypedef uint32_t SpecialTypeForSendingFd;\ntypedef enum TileState { Idle, Stopped, Running } TileState;\ntypedef struct TileControl {\n    uint8_t tile : 2;\n    TileState state;\n} TileControl;\ntypedef enum IfcNames { NoInterface, IfcNames_ReadTestIndicationH2S, IfcNames_MMUIndicationH2S, IfcNames_MemServerIndicationH2S, IfcNames_ReadTestRequestS2H, IfcNames_MMURequestS2H, IfcNames_MemServerRequestS2H } IfcNames;\n\n\nint MemServerRequest_addrTrans ( struct PortalInternal *p, const uint32_t sglId, const uint32_t offset );\nint MemServerRequest_setTileState ( struct PortalInternal *p, const TileControl tc );\nint MemServerRequest_stateDbg ( struct PortalInternal *p, const ChannelType rc );\nint MemServerRequest_memoryTraffic ( struct PortalInternal *p, const ChannelType rc );\nenum { CHAN_NUM_MemServerRequest_addrTrans,CHAN_NUM_MemServerRequest_setTileState,CHAN_NUM_MemServerRequest_stateDbg,CHAN_NUM_MemServerRequest_memoryTraffic};\n#define MemServerRequest_reqinfo 0x4000c\n\ntypedef struct {\n    uint32_t sglId;\n    uint32_t offset;\n} MemServerRequest_addrTransData;\ntypedef struct {\n    TileControl tc;\n} MemServerRequest_setTileStateData;\ntypedef struct {\n    ChannelType rc;\n} MemServerRequest_stateDbgData;\ntypedef struct {\n    ChannelType rc;\n} MemServerRequest_memoryTrafficData;\ntypedef union {\n    MemServerRequest_addrTransData addrTrans;\n    MemServerRequest_setTileStateData setTileState;\n    MemServerRequest_stateDbgData stateDbg;\n    MemServerRequest_memoryTrafficData memoryTraffic;\n} MemServerRequestData;\nint MemServerRequest_handleMessage(struct PortalInternal *p, unsigned int channel, int messageFd);\ntypedef struct {\n    int (*addrTrans) (  struct PortalInternal *p, const uint32_t sglId, const uint32_t offset );\n    int (*setTileState) (  struct PortalInternal *p, const TileControl tc );\n    int (*stateDbg) (  struct PortalInternal *p, const ChannelType rc );\n    int (*memoryTraffic) (  struct PortalInternal *p, const ChannelType rc );\n} MemServerRequestCb;\nextern MemServerRequestCb MemServerRequestProxyReq;\n\nint MemServerRequestJson_addrTrans ( struct PortalInternal *p, const uint32_t sglId, const uint32_t offset );\nint MemServerRequestJson_setTileState ( struct PortalInternal *p, const TileControl tc );\nint MemServerRequestJson_stateDbg ( struct PortalInternal *p, const ChannelType rc );\nint MemServerRequestJson_memoryTraffic ( struct PortalInternal *p, const ChannelType rc );\nint MemServerRequestJson_handleMessage(struct PortalInternal *p, unsigned int channel, int messageFd);\nextern MemServerRequestCb MemServerRequestJsonProxyReq;\n\nint MMURequest_sglist ( struct PortalInternal *p, const uint32_t sglId, const uint32_t sglIndex, const uint64_t addr, const uint32_t len );\nint MMURequest_region ( struct PortalInternal *p, const uint32_t sglId, const uint64_t barr12, const uint32_t index12, const uint64_t barr8, const uint32_t index8, const uint64_t barr4, const uint32_t index4, const uint64_t barr0, const uint32_t index0 );\nint MMURequest_idRequest ( struct PortalInternal *p, const SpecialTypeForSendingFd fd );\nint MMURequest_idReturn ( struct PortalInternal *p, const uint32_t sglId );\nint MMURequest_setInterface ( struct PortalInternal *p, const uint32_t interfaceId, const uint32_t sglId );\nenum { CHAN_NUM_MMURequest_sglist,CHAN_NUM_MMURequest_region,CHAN_NUM_MMURequest_idRequest,CHAN_NUM_MMURequest_idReturn,CHAN_NUM_MMURequest_setInterface};\n#define MMURequest_reqinfo 0x5002c\n\ntypedef struct {\n    uint32_t sglId;\n    uint32_t sglIndex;\n    uint64_t addr;\n    uint32_t len;\n} MMURequest_sglistData;\ntypedef struct {\n    uint32_t sglId;\n    uint64_t barr12;\n    uint32_t index12;\n    uint64_t barr8;\n    uint32_t index8;\n    uint64_t barr4;\n    uint32_t index4;\n    uint64_t barr0;\n    uint32_t index0;\n} MMURequest_regionData;\ntypedef struct {\n    SpecialTypeForSendingFd fd;\n} MMURequest_idRequestData;\ntypedef struct {\n    uint32_t sglId;\n} MMURequest_idReturnData;\ntypedef struct {\n    uint32_t interfaceId;\n    uint32_t sglId;\n} MMURequest_setInterfaceData;\ntypedef union {\n    MMURequest_sglistData sglist;\n    MMURequest_regionData region;\n    MMURequest_idRequestData idRequest;\n    MMURequest_idReturnData idReturn;\n    MMURequest_setInterfaceData setInterface;\n} MMURequestData;\nint MMURequest_handleMessage(struct PortalInternal *p, unsigned int channel, int messageFd);\ntypedef struct {\n    int (*sglist) (  struct PortalInternal *p, const uint32_t sglId, const uint32_t sglIndex, const uint64_t addr, const uint32_t len );\n    int (*region) (  struct PortalInternal *p, const uint32_t sglId, const uint64_t barr12, const uint32_t index12, const uint64_t barr8, const uint32_t index8, const uint64_t barr4, const uint32_t index4, const uint64_t barr0, const uint32_t index0 );\n    int (*idRequest) (  struct PortalInternal *p, const SpecialTypeForSendingFd fd );\n    int (*idReturn) (  struct PortalInternal *p, const uint32_t sglId );\n    int (*setInterface) (  struct PortalInternal *p, const uint32_t interfaceId, const uint32_t sglId );\n} MMURequestCb;\nextern MMURequestCb MMURequestProxyReq;\n\nint MMURequestJson_sglist ( struct PortalInternal *p, const uint32_t sglId, const uint32_t sglIndex, const uint64_t addr, const uint32_t len );\nint MMURequestJson_region ( struct PortalInternal *p, const uint32_t sglId, const uint64_t barr12, const uint32_t index12, const uint64_t barr8, const uint32_t index8, const uint64_t barr4, const uint32_t index4, const uint64_t barr0, const uint32_t index0 );\nint MMURequestJson_idRequest ( struct PortalInternal *p, const SpecialTypeForSendingFd fd );\nint MMURequestJson_idReturn ( struct PortalInternal *p, const uint32_t sglId );\nint MMURequestJson_setInterface ( struct PortalInternal *p, const uint32_t interfaceId, const uint32_t sglId );\nint MMURequestJson_handleMessage(struct PortalInternal *p, unsigned int channel, int messageFd);\nextern MMURequestCb MMURequestJsonProxyReq;\n\nint MemServerIndication_addrResponse ( struct PortalInternal *p, const uint64_t physAddr );\nint MemServerIndication_reportStateDbg ( struct PortalInternal *p, const DmaDbgRec rec );\nint MemServerIndication_reportMemoryTraffic ( struct PortalInternal *p, const uint64_t words );\nint MemServerIndication_error ( struct PortalInternal *p, const uint32_t code, const uint32_t sglId, const uint64_t offset, const uint64_t extra );\nenum { CHAN_NUM_MemServerIndication_addrResponse,CHAN_NUM_MemServerIndication_reportStateDbg,CHAN_NUM_MemServerIndication_reportMemoryTraffic,CHAN_NUM_MemServerIndication_error};\n#define MemServerIndication_reqinfo 0x4001c\n\ntypedef struct {\n    uint64_t physAddr;\n} MemServerIndication_addrResponseData;\ntypedef struct {\n    DmaDbgRec rec;\n} MemServerIndication_reportStateDbgData;\ntypedef struct {\n    uint64_t words;\n} MemServerIndication_reportMemoryTrafficData;\ntypedef struct {\n    uint32_t code;\n    uint32_t sglId;\n    uint64_t offset;\n    uint64_t extra;\n} MemServerIndication_errorData;\ntypedef union {\n    MemServerIndication_addrResponseData addrResponse;\n    MemServerIndication_reportStateDbgData reportStateDbg;\n    MemServerIndication_reportMemoryTrafficData reportMemoryTraffic;\n    MemServerIndication_errorData error;\n} MemServerIndicationData;\nint MemServerIndication_handleMessage(struct PortalInternal *p, unsigned int channel, int messageFd);\ntypedef struct {\n    int (*addrResponse) (  struct PortalInternal *p, const uint64_t physAddr );\n    int (*reportStateDbg) (  struct PortalInternal *p, const DmaDbgRec rec );\n    int (*reportMemoryTraffic) (  struct PortalInternal *p, const uint64_t words );\n    int (*error) (  struct PortalInternal *p, const uint32_t code, const uint32_t sglId, const uint64_t offset, const uint64_t extra );\n} MemServerIndicationCb;\nextern MemServerIndicationCb MemServerIndicationProxyReq;\n\nint MemServerIndicationJson_addrResponse ( struct PortalInternal *p, const uint64_t physAddr );\nint MemServerIndicationJson_reportStateDbg ( struct PortalInternal *p, const DmaDbgRec rec );\nint MemServerIndicationJson_reportMemoryTraffic ( struct PortalInternal *p, const uint64_t words );\nint MemServerIndicationJson_error ( struct PortalInternal *p, const uint32_t code, const uint32_t sglId, const uint64_t offset, const uint64_t extra );\nint MemServerIndicationJson_handleMessage(struct PortalInternal *p, unsigned int channel, int messageFd);\nextern MemServerIndicationCb MemServerIndicationJsonProxyReq;\n\nint MMUIndication_idResponse ( struct PortalInternal *p, const uint32_t sglId );\nint MMUIndication_configResp ( struct PortalInternal *p, const uint32_t sglId );\nint MMUIndication_error ( struct PortalInternal *p, const uint32_t code, const uint32_t sglId, const uint64_t offset, const uint64_t extra );\nenum { CHAN_NUM_MMUIndication_idResponse,CHAN_NUM_MMUIndication_configResp,CHAN_NUM_MMUIndication_error};\n#define MMUIndication_reqinfo 0x3001c\n\ntypedef struct {\n    uint32_t sglId;\n} MMUIndication_idResponseData;\ntypedef struct {\n    uint32_t sglId;\n} MMUIndication_configRespData;\ntypedef struct {\n    uint32_t code;\n    uint32_t sglId;\n    uint64_t offset;\n    uint64_t extra;\n} MMUIndication_errorData;\ntypedef union {\n    MMUIndication_idResponseData idResponse;\n    MMUIndication_configRespData configResp;\n    MMUIndication_errorData error;\n} MMUIndicationData;\nint MMUIndication_handleMessage(struct PortalInternal *p, unsigned int channel, int messageFd);\ntypedef struct {\n    int (*idResponse) (  struct PortalInternal *p, const uint32_t sglId );\n    int (*configResp) (  struct PortalInternal *p, const uint32_t sglId );\n    int (*error) (  struct PortalInternal *p, const uint32_t code, const uint32_t sglId, const uint64_t offset, const uint64_t extra );\n} MMUIndicationCb;\nextern MMUIndicationCb MMUIndicationProxyReq;\n\nint MMUIndicationJson_idResponse ( struct PortalInternal *p, const uint32_t sglId );\nint MMUIndicationJson_configResp ( struct PortalInternal *p, const uint32_t sglId );\nint MMUIndicationJson_error ( struct PortalInternal *p, const uint32_t code, const uint32_t sglId, const uint64_t offset, const uint64_t extra );\nint MMUIndicationJson_handleMessage(struct PortalInternal *p, unsigned int channel, int messageFd);\nextern MMUIndicationCb MMUIndicationJsonProxyReq;\n\nint ReadTestRequest_startRead ( struct PortalInternal *p, const uint32_t pointer, const uint32_t numBytes, const uint32_t burstLen, const uint32_t iterCnt );\nenum { CHAN_NUM_ReadTestRequest_startRead};\n#define ReadTestRequest_reqinfo 0x10014\n\ntypedef struct {\n    uint32_t pointer;\n    uint32_t numBytes;\n    uint32_t burstLen;\n    uint32_t iterCnt;\n} ReadTestRequest_startReadData;\ntypedef union {\n    ReadTestRequest_startReadData startRead;\n} ReadTestRequestData;\nint ReadTestRequest_handleMessage(struct PortalInternal *p, unsigned int channel, int messageFd);\ntypedef struct {\n    int (*startRead) (  struct PortalInternal *p, const uint32_t pointer, const uint32_t numBytes, const uint32_t burstLen, const uint32_t iterCnt );\n} ReadTestRequestCb;\nextern ReadTestRequestCb ReadTestRequestProxyReq;\n\nint ReadTestRequestJson_startRead ( struct PortalInternal *p, const uint32_t pointer, const uint32_t numBytes, const uint32_t burstLen, const uint32_t iterCnt );\nint ReadTestRequestJson_handleMessage(struct PortalInternal *p, unsigned int channel, int messageFd);\nextern ReadTestRequestCb ReadTestRequestJsonProxyReq;\n\nint ReadTestIndication_readDone ( struct PortalInternal *p, const uint32_t mismatchCount );\nenum { CHAN_NUM_ReadTestIndication_readDone};\n#define ReadTestIndication_reqinfo 0x10008\n\ntypedef struct {\n    uint32_t mismatchCount;\n} ReadTestIndication_readDoneData;\ntypedef union {\n    ReadTestIndication_readDoneData readDone;\n} ReadTestIndicationData;\nint ReadTestIndication_handleMessage(struct PortalInternal *p, unsigned int channel, int messageFd);\ntypedef struct {\n    int (*readDone) (  struct PortalInternal *p, const uint32_t mismatchCount );\n} ReadTestIndicationCb;\nextern ReadTestIndicationCb ReadTestIndicationProxyReq;\n\nint ReadTestIndicationJson_readDone ( struct PortalInternal *p, const uint32_t mismatchCount );\nint ReadTestIndicationJson_handleMessage(struct PortalInternal *p, unsigned int channel, int messageFd);\nextern ReadTestIndicationCb ReadTestIndicationJsonProxyReq;\n#ifdef __cplusplus\n}\n#endif\n#endif //__GENERATED_TYPES__\n"
  },
  {
    "path": "generated/cpp/MMURequest.c",
    "content": "#include \"GeneratedTypes.h\"\n\nint MMURequest_sglist ( struct PortalInternal *p, const uint32_t sglId, const uint32_t sglIndex, const uint64_t addr, const uint32_t len )\n{\n    volatile unsigned int* temp_working_addr_start = p->transport->mapchannelReq(p, CHAN_NUM_MMURequest_sglist, 6);\n    volatile unsigned int* temp_working_addr = temp_working_addr_start;\n    if (p->transport->busywait(p, CHAN_NUM_MMURequest_sglist, \"MMURequest_sglist\")) return 1;\n    p->transport->write(p, &temp_working_addr, sglId);\n    p->transport->write(p, &temp_working_addr, sglIndex);\n    p->transport->write(p, &temp_working_addr, (addr>>32));\n    p->transport->write(p, &temp_working_addr, addr);\n    p->transport->write(p, &temp_working_addr, len);\n    p->transport->send(p, temp_working_addr_start, (CHAN_NUM_MMURequest_sglist << 16) | 6, -1);\n    return 0;\n};\n\nint MMURequest_region ( struct PortalInternal *p, const uint32_t sglId, const uint64_t barr12, const uint32_t index12, const uint64_t barr8, const uint32_t index8, const uint64_t barr4, const uint32_t index4, const uint64_t barr0, const uint32_t index0 )\n{\n    volatile unsigned int* temp_working_addr_start = p->transport->mapchannelReq(p, CHAN_NUM_MMURequest_region, 11);\n    volatile unsigned int* temp_working_addr = temp_working_addr_start;\n    if (p->transport->busywait(p, CHAN_NUM_MMURequest_region, \"MMURequest_region\")) return 1;\n    p->transport->write(p, &temp_working_addr, sglId);\n    p->transport->write(p, &temp_working_addr, (barr12>>32));\n    p->transport->write(p, &temp_working_addr, barr12);\n    p->transport->write(p, &temp_working_addr, index12);\n    p->transport->write(p, &temp_working_addr, (barr8>>32));\n    p->transport->write(p, &temp_working_addr, barr8);\n    p->transport->write(p, &temp_working_addr, index8);\n    p->transport->write(p, &temp_working_addr, (barr4>>32));\n    p->transport->write(p, &temp_working_addr, barr4);\n    p->transport->write(p, &temp_working_addr, index4);\n    p->transport->write(p, &temp_working_addr, (barr0>>32));\n    p->transport->write(p, &temp_working_addr, barr0);\n    p->transport->write(p, &temp_working_addr, index0);\n    p->transport->send(p, temp_working_addr_start, (CHAN_NUM_MMURequest_region << 16) | 11, -1);\n    return 0;\n};\n\nint MMURequest_idRequest ( struct PortalInternal *p, const SpecialTypeForSendingFd fd )\n{\n    volatile unsigned int* temp_working_addr_start = p->transport->mapchannelReq(p, CHAN_NUM_MMURequest_idRequest, 2);\n    volatile unsigned int* temp_working_addr = temp_working_addr_start;\n    if (p->transport->busywait(p, CHAN_NUM_MMURequest_idRequest, \"MMURequest_idRequest\")) return 1;\n    p->transport->writefd(p, &temp_working_addr, fd);\n    p->transport->send(p, temp_working_addr_start, (CHAN_NUM_MMURequest_idRequest << 16) | 2, fd);\n    return 0;\n};\n\nint MMURequest_idReturn ( struct PortalInternal *p, const uint32_t sglId )\n{\n    volatile unsigned int* temp_working_addr_start = p->transport->mapchannelReq(p, CHAN_NUM_MMURequest_idReturn, 2);\n    volatile unsigned int* temp_working_addr = temp_working_addr_start;\n    if (p->transport->busywait(p, CHAN_NUM_MMURequest_idReturn, \"MMURequest_idReturn\")) return 1;\n    p->transport->write(p, &temp_working_addr, sglId);\n    p->transport->send(p, temp_working_addr_start, (CHAN_NUM_MMURequest_idReturn << 16) | 2, -1);\n    return 0;\n};\n\nint MMURequest_setInterface ( struct PortalInternal *p, const uint32_t interfaceId, const uint32_t sglId )\n{\n    volatile unsigned int* temp_working_addr_start = p->transport->mapchannelReq(p, CHAN_NUM_MMURequest_setInterface, 3);\n    volatile unsigned int* temp_working_addr = temp_working_addr_start;\n    if (p->transport->busywait(p, CHAN_NUM_MMURequest_setInterface, \"MMURequest_setInterface\")) return 1;\n    p->transport->write(p, &temp_working_addr, interfaceId);\n    p->transport->write(p, &temp_working_addr, sglId);\n    p->transport->send(p, temp_working_addr_start, (CHAN_NUM_MMURequest_setInterface << 16) | 3, -1);\n    return 0;\n};\n\nMMURequestCb MMURequestProxyReq = {\n    MMURequest_sglist,\n    MMURequest_region,\n    MMURequest_idRequest,\n    MMURequest_idReturn,\n    MMURequest_setInterface,\n};\nint MMURequest_handleMessage(struct PortalInternal *p, unsigned int channel, int messageFd)\n{\n    static int runaway = 0;\n    int   tmp __attribute__ ((unused));\n    int tmpfd __attribute__ ((unused));\n    MMURequestData tempdata __attribute__ ((unused));\n    volatile unsigned int* temp_working_addr = p->transport->mapchannelInd(p, channel);\n    switch (channel) {\n    case CHAN_NUM_MMURequest_sglist: {\n        \n        p->transport->recv(p, temp_working_addr, 5, &tmpfd);\n        tmp = p->transport->read(p, &temp_working_addr);\n        tempdata.sglist.sglId = (uint32_t)(((tmp)&0xfffffffful));\n        tmp = p->transport->read(p, &temp_working_addr);\n        tempdata.sglist.sglIndex = (uint32_t)(((tmp)&0xfffffffful));\n        tmp = p->transport->read(p, &temp_working_addr);\n        tempdata.sglist.addr = (uint64_t)(((uint64_t)(((tmp)&0xfffffffful))<<32));\n        tmp = p->transport->read(p, &temp_working_addr);\n        tempdata.sglist.addr |= (uint64_t)(((tmp)&0xfffffffful));\n        tmp = p->transport->read(p, &temp_working_addr);\n        tempdata.sglist.len = (uint32_t)(((tmp)&0xfffffffful));((MMURequestCb *)p->cb)->sglist(p, tempdata.sglist.sglId, tempdata.sglist.sglIndex, tempdata.sglist.addr, tempdata.sglist.len);\n      } break;\n    case CHAN_NUM_MMURequest_region: {\n        \n        p->transport->recv(p, temp_working_addr, 10, &tmpfd);\n        tmp = p->transport->read(p, &temp_working_addr);\n        tempdata.region.sglId = (uint32_t)(((tmp)&0xfffffffful));\n        tmp = p->transport->read(p, &temp_working_addr);\n        tempdata.region.barr12 = (uint64_t)(((uint64_t)(((tmp)&0xfffffffful))<<32));\n        tmp = p->transport->read(p, &temp_working_addr);\n        tempdata.region.barr12 |= (uint64_t)(((tmp)&0xfffffffful));\n        tmp = p->transport->read(p, &temp_working_addr);\n        tempdata.region.index12 = (uint32_t)(((tmp)&0xfffffffful));\n        tmp = p->transport->read(p, &temp_working_addr);\n        tempdata.region.barr8 = (uint64_t)(((uint64_t)(((tmp)&0xfffffffful))<<32));\n        tmp = p->transport->read(p, &temp_working_addr);\n        tempdata.region.barr8 |= (uint64_t)(((tmp)&0xfffffffful));\n        tmp = p->transport->read(p, &temp_working_addr);\n        tempdata.region.index8 = (uint32_t)(((tmp)&0xfffffffful));\n        tmp = p->transport->read(p, &temp_working_addr);\n        tempdata.region.barr4 = (uint64_t)(((uint64_t)(((tmp)&0xfffffffful))<<32));\n        tmp = p->transport->read(p, &temp_working_addr);\n        tempdata.region.barr4 |= (uint64_t)(((tmp)&0xfffffffful));\n        tmp = p->transport->read(p, &temp_working_addr);\n        tempdata.region.index4 = (uint32_t)(((tmp)&0xfffffffful));\n        tmp = p->transport->read(p, &temp_working_addr);\n        tempdata.region.barr0 = (uint64_t)(((uint64_t)(((tmp)&0xfffffffful))<<32));\n        tmp = p->transport->read(p, &temp_working_addr);\n        tempdata.region.barr0 |= (uint64_t)(((tmp)&0xfffffffful));\n        tmp = p->transport->read(p, &temp_working_addr);\n        tempdata.region.index0 = (uint32_t)(((tmp)&0xfffffffful));((MMURequestCb *)p->cb)->region(p, tempdata.region.sglId, tempdata.region.barr12, tempdata.region.index12, tempdata.region.barr8, tempdata.region.index8, tempdata.region.barr4, tempdata.region.index4, tempdata.region.barr0, tempdata.region.index0);\n      } break;\n    case CHAN_NUM_MMURequest_idRequest: {\n        \n        p->transport->recv(p, temp_working_addr, 1, &tmpfd);\n        tmp = p->transport->read(p, &temp_working_addr);\n        tempdata.idRequest.fd = messageFd;((MMURequestCb *)p->cb)->idRequest(p, tempdata.idRequest.fd);\n      } break;\n    case CHAN_NUM_MMURequest_idReturn: {\n        \n        p->transport->recv(p, temp_working_addr, 1, &tmpfd);\n        tmp = p->transport->read(p, &temp_working_addr);\n        tempdata.idReturn.sglId = (uint32_t)(((tmp)&0xfffffffful));((MMURequestCb *)p->cb)->idReturn(p, tempdata.idReturn.sglId);\n      } break;\n    case CHAN_NUM_MMURequest_setInterface: {\n        \n        p->transport->recv(p, temp_working_addr, 2, &tmpfd);\n        tmp = p->transport->read(p, &temp_working_addr);\n        tempdata.setInterface.interfaceId = (uint32_t)(((tmp)&0xfffffffful));\n        tmp = p->transport->read(p, &temp_working_addr);\n        tempdata.setInterface.sglId = (uint32_t)(((tmp)&0xfffffffful));((MMURequestCb *)p->cb)->setInterface(p, tempdata.setInterface.interfaceId, tempdata.setInterface.sglId);\n      } break;\n    default:\n        PORTAL_PRINTF(\"MMURequest_handleMessage: unknown channel 0x%x\\n\", channel);\n        if (runaway++ > 10) {\n            PORTAL_PRINTF(\"MMURequest_handleMessage: too many bogus indications, exiting\\n\");\n#ifndef __KERNEL__\n            exit(-1);\n#endif\n        }\n        return 0;\n    }\n    return 0;\n}\n"
  },
  {
    "path": "generated/cpp/README",
    "content": "\nGeneratedTypes.h and MMURequest.c in this directory are taken from tests/memread_manual/bluesim/jni, without modification.\n\nThey are only used when compiling dmaSendFd.h for drivers/pcieportal/pcieportal.c and drivers/zynqportal/zynqportal.c\n\n\n"
  },
  {
    "path": "generated/scripts/generate_altera_ddrbvi.sh",
    "content": "#\n#\nset -x\nset -e\n./importbvi.py -o ALTERA_DDR3_WRAPPER.bsv -I AvalonDdr3 -P AvalonDdr3 \\\n\t-c pll_ref_clk -r global_reset_n -r soft_reset_n -c afi_clk -c afi_half_clk -r afi_reset_n -r afi_reset_export_n \\\n\t-f mem -f avl -f local -f oct -f pll \\\n\t/home/hwang/dev/connectal/out/de5/synthesis/altera_mem_if_ddr3_emif_wrapper/altera_mem_if_ddr3_emif_wrapper.v\n"
  },
  {
    "path": "generated/scripts/generate_altera_ethbvi.sh",
    "content": "#\n#\nset -x\nset -e\n#./importbvi.py -o ALTERA_ETH_PMA_WRAPPER.bsv -I EthXcvrWrap -P EthXcvrWrap \\\n#    -f pll -f tx -f rx -f reconfig \\\n#    ../../out/de5/synthesis/altera_xcvr_native_sv_wrapper.v\n#\n#./importbvi.py -o ALTERA_ETH_PMA_RECONFIG_WRAPPER.bsv -I EthXcvrReconfigWrap -P EthXcvrReconfigWrap \\\n#  -c mgmt_clk_clk -r mgmt_rst_reset \\\n#  -f reconfig \\\n#  ../../out/de5/synthesis/altera_xgbe_pma_reconfig_wrapper.v\n#\n#./importbvi.py -o ALTERA_ETH_PMA_RESET_CONTROL_WRAPPER.bsv -I EthXcvrResetWrap -P EthXcvrResetWrap \\\n#\t-c clock -r reset \\\n#    -f pll -f rx_r -f tx_r -f tx -f rx \\\n#    ../../out/de5/synthesis/altera_xcvr_reset_control_wrapper.v\n\n#./importbvi.py -o ALTERA_ETH_10G_PHY.bsv -I Eth10GPhyWrap -P Eth10GPhyWrap \\\n#\t-c pll_ref_clk -r phy_mgmt_clk_reset -c phy_mgmt_clk \\\n#\t-f phy_mgmt -f tx_r -f rx_r -f tx -f rx -f reconfig \\\n#\t../../out/de5/synthesis/sv_10g_phy/sv_10g_phy.v\n\n./importbvi.py -o ALTERA_ETH_SONIC_PMA.bsv -I EthSonicPmaWrap -P EthSonicPmaWrap \\\n\t-c pll_ref_clk -r phy_mgmt_clk_reset -c phy_mgmt_clk \\\n\t-f phy_mgmt -f tx_r -f rx_r -f tx -f rx -f reconfig \\\n\t../../verilog/altera/sonic_pma_v1_05.v\n\n\n"
  },
  {
    "path": "generated/scripts/generate_altera_macbvi.sh",
    "content": "#\n#\nset -x\nset -e\n./importbvi.py -o ALTERA_MAC_WRAPPER.bsv -I MacWrap -P MacWrap \\\n    -c p0_tx_clk_clk -c p1_tx_clk_clk -c p2_tx_clk_clk -c p3_tx_clk_clk \\\n    -c p0_rx_clk_clk -c p1_rx_clk_clk -c p2_rx_clk_clk -c p3_rx_clk_clk \\\n    -c mgmt_clk_clk \\\n    -r mgmt_reset_reset_n -r jtag_reset_reset \\\n    -r p0_tx_reset_reset_n -r p1_tx_reset_reset_n -r p2_tx_reset_reset_n -r p3_tx_reset_reset_n \\\n    -r p0_rx_reset_reset_n -r p1_rx_reset_reset_n -r p2_rx_reset_reset_n -r p3_rx_reset_reset_n \\\n    -f p0_tx -f p0_rx -f p1_tx -f p1_rx -f p2_tx -f p2_rx -f p3_tx -f p3_rx \\\n    -f p0_xgmii -f p1_xgmii -f p2_xgmii -f p3_xgmii \\\n    -f p0_link_fault -f p1_link_fault -f p2_link_fault -f p3_link_fault \\\n    ../../out/de5/synthesis/altera_mac.v\n\n"
  },
  {
    "path": "generated/scripts/generate_altera_pciebvi.sh",
    "content": "#\n#\nset -x\nset -e\n#./importbvi.py -o ALTERA_PCIE_SV_WRAPPER.bsv -I PcieWrap -P PcieWrap \\\n#    -r pin_perst -r npor -r reset_status \\\n#    -c refclk -c coreclkout_hip \\\n#    -f serdes -f pld -f dl -f ev128 -f ev1 -f hotrst -f l2 -f current \\\n#    -f derr -f lane -f ltssm -f reconfig \\\n#    -f tx_cred -f tx_par -f tx_s -f txd -f txe -f txc -f txm -f txs -f tx\\\n#    -f tx_cred -f rx_par -f rx_s -f rxd -f rxr -f rxe -f rxp -f rxs -f rxv -f rx\\\n#\t-f cfg_par \\\n#    -f eidle -f power -f phy \\\n#    -f int_s -f cpl -f tl -f pm_e -f pme -f pm \\\n#    -f simu -f sim \\\n#    -f test_in \\\n#    ../../out/de5/synthesis/altera_pcie_sv_hip_ast_wrapper.v\n#\n#    #-f rxdata -f rxpolarity -f rxdatak -f rxelecidle -f rxstatus -f rxvalid \\\n#    #-f txdata -f tx_cred -f tx_out -f txcompl -f txdatak -f txdetectrx -f txelecidle -f txdeemph -f txmargin -f txswing \\\n#\n#./importbvi.py -o ALTERA_PCIE_RECONFIG_DRIVER_WRAPPER.bsv -I PcieReconfigWrap -P PcieReconfigWrap \\\n#  -c reconfig_xcvr_clk -c pld_clk -r reconfig_xcvr_rst \\\n#  -f reconfig_mgmt -f reconfig_b -f current -f derr -f dlup -f ev128ns -f ev1us -f hotrst \\\n#  -f int_s -f l2 -f lane -f ltssmstate -f dlup -f rx -f tx \\\n#  -f tx -f rx -f cfg -f ko \\\n#  ../../out/de5/synthesis/altera_pcie_reconfig_driver_wrapper.v\n#\n#./importbvi.py -o ALTERA_XCVR_RECONFIG_WRAPPER.bsv -I XcvrReconfigWrap -P XcvrReconfigWrap \\\n#\t-c mgmt_clk_clk -r mgmt_rst_reset \\\n#      -f reconfig_mgmt -f mgmt \\\n#      ../../out/de5/synthesis/alt_xcvr_reconfig_wrapper.v\n\n#./importbvi.py -o ALTERA_PCIE_ED_WRAPPER.bsv -I PcieEdWrap -P PcieEdWrap \\\n#\t-c coreclkout_hip -c pld_clk_hip \\\n#    -f serdes -f reset -f pld -f dl -f ev128 -f ev1 -f hotrst -f l2 -f current \\\n#    -f derr -f lane -f ltssm -f reconfig \\\n#    -f int_s -f aer -f pex -f serr -f cpl -f tl -f pm_e -f pme -f pm\\\n#    -f tx_s -f rx_s \\\n#\t-f tx_cred \\\n#    -f tx_par -f rx_par -f cfg_par \\\n#    ../../out/de5/synthesis/altera_pcie_hip_ast_ed.v\n\n#./importbvi.py -o ALTERA_PLL_WRAPPER.bsv -I PciePllWrap -P PciePllWrap \\\n#    -c refclk -r rst \\\n#    -f out -f locked \\\n#    ../../out/de5/synthesis/altera_pll_wrapper.v\n\n./importbvi.py -o ALTERA_PCIE_SIV_WRAPPER.bsv -I PcieS4Wrap -P PcieS4Wrap \\\n    -r pin_perst -r npor -r reset_status -r pcie_rstn -r srstn \\\n    -c refclk -c core_clk_out -c reconfig_clk -c fixedclk_serdes \\\n\t-f app -f pex_msi \\\n\t-f cpl \\\n\t-f pclk_in \\\n\t-f clk250_out \\\n\t-f clk500_out \\\n\t-f rx_st \\\n\t-f tx_st \\\n\t-f fixedclk \\\n\t-f lmi \\\n    -f tx \\\n    -f rx \\\n\t-f phystatus \\\n\t-f pipe \\\n\t-f pm \\\n\t-f pme \\\n\t-f reconfig \\\n\t-f test \\\n\t-f lane \\\n\t-f ltssm \\\n\t-f powerdown \\\n\t-f rate \\\n\t-f rc_pll \\\n\t-f tl_cfg \\\n    ../../out/htg4/siv_gen2x8/siv_gen2x8_examples/chaining_dma/siv_gen2x8_plus.v\n"
  },
  {
    "path": "generated/scripts/generate_bscane2.sh",
    "content": "#\nset -x\nset -e\nscripts/importbvi.py -o BscanE2.bsv -C BSCANE2 -I BscanE2 -P PPS7 -c DRCK -c TCK --param=JTAG_CHAIN \\\n    ../../import_components/Xilinx/Vivado/2013.2/data/parts/xilinx/zynq/zynq.lib\n\n"
  },
  {
    "path": "generated/scripts/generate_bufgcrtl.sh",
    "content": "#\nset -x\nset -e\nscripts/importbvi.py -o Bufgctrl.bsv -C BUFGCTRL -I Bufgctrl -P Bufgctrl \\\n    -c I0 -c I1 -c O \\\n    ../../import_components/Xilinx/Vivado/2013.2/data/parts/xilinx/zynq/zynq.lib\n\n"
  },
  {
    "path": "generated/scripts/generate_pcie2wrapper.sh",
    "content": "#\nset -x\nset -e\n../scripts/importbvi.py -o PCIEWRAPPER2.bsv -I PcieWrap -P PcieWrap \\\n    -n pl_link_partner_gen2_supported \\\n    -n cfg_mgmt_wr_rw1c_as_rw \\\n    -n pipe_gen3_out \\\n    -n pipe_userclk1_in \\\n    -n pipe_userclk2_in \\\n    -n pl_link_gen2_cap \\\n    -n int_userclk1_out \\\n    -n int_userclk2_out \\\n    -n int_ \\\n    -c int_userclk1_out \\\n    -c int_userclk2_out \\\n    -c int_oobclk_out \\\n    -c int_dclk_out \\\n    -c int_pclk_out_slave \\\n    -c int_pipe_rxuserclk_out \\\n    -c int_qplloutclk_out \\\n    -c int_qplloutrefclk_out \\\n    -c int_rxoutclk_out \\\n    -n user_clk_out \\\n    -n user_reset_out \\\n    -c user_clk_out -r user_reset_out \\\n    -c sys_clk -r sys_rst_n \\\n    -n cfg_dsn -n cfg_dstatus \\\n    -f cfg_aer -f cfg_ds -f cfg_err -f cfg_interrupt \\\n    -f cfg_mgmt -f cfg_msg -f cfg_pmcsr -f cfg_pm \\\n    -f cfg_root_control \\\n    -f pipe -f pl_link -f pci_exp -f pcie_drp \\\n    -p lanes \\\n    ../../out/vc707/pcie2_7x_0/pcie2_7x_0_stub.v\n\n# remove junk emitted into \"import BVI =\"\nsed -i 's/(pci_exp_txp,//' PCIEWRAPPER2.bsv\n\n# move user_clk_out and user_reset_out to top in place of boilerplate default_clock and default_reset\nsed -i 's/output_clock user_clk_out(user_clk_out);//' PCIEWRAPPER2.bsv\nsed -i 's/output_reset user_reset_out(user_reset_out);//' PCIEWRAPPER2.bsv\nsed -i 's/default_clock clk();/output_clock user_clk_out(user_clk_out);/' PCIEWRAPPER2.bsv\nsed -i 's/default_reset rst();/output_reset user_reset_out(user_reset_out);/' PCIEWRAPPER2.bsv\n# remove extra reset\nsed -i 's/Reset sys_clk_reset, //' PCIEWRAPPER2.bsv\nsed -i 's/input_reset sys_clk_reset() = sys_clk_reset;//' PCIEWRAPPER2.bsv\n\n# make sys_clk and sys_rst_n the default\nsed -i 's/input_clock sys_clk/default_clock sys_clk/' PCIEWRAPPER2.bsv\nsed -i 's/input_reset sys_rst_n/default_reset sys_rst_n/' PCIEWRAPPER2.bsv\n\n# add clocked_by reset_by to methods\nsed -i 's/method cfg[^;]*/& clocked_by (user_clk_out) reset_by (user_reset_out)/' PCIEWRAPPER2.bsv\nsed -i 's/method fc[^;]*/& clocked_by (user_clk_out) reset_by (user_reset_out)/' PCIEWRAPPER2.bsv\nsed -i 's/method m_axis[^;]*/& clocked_by (user_clk_out) reset_by (user_reset_out)/' PCIEWRAPPER2.bsv\nsed -i 's/method s_axis[^;]*/& clocked_by (user_clk_out) reset_by (user_reset_out)/' PCIEWRAPPER2.bsv\nsed -i 's/method pl_[^;]*/& clocked_by (user_clk_out) reset_by (user_reset_out)/' PCIEWRAPPER2.bsv\nsed -i 's/method np_[^;]*/& clocked_by (user_clk_out) reset_by (user_reset_out)/' PCIEWRAPPER2.bsv\nsed -i 's/method user_[^;]*/& clocked_by (user_clk_out) reset_by (user_reset_out)/' PCIEWRAPPER2.bsv\nsed -i 's/method[^;]*EN_[^;]*/& clocked_by (user_clk_out) reset_by (user_reset_out)/' PCIEWRAPPER2.bsv\n# fix the double edited lines\nsed -i 's/clocked_by (user_clk_out) reset_by (user_reset_out) clocked_by (user_clk_out) reset_by (user_reset_out)/clocked_by (user_clk_out) reset_by (user_reset_out)/'  PCIEWRAPPER2.bsv\n\n# now the pcie clocks\nsed -i 's/\\(method rx[^;]*\\)clocked_by[^;]*/\\1 clocked_by (sys_clk) reset_by (sys_rst_n)/' PCIEWRAPPER2.bsv\nsed -i 's/method pci_exp_tx[^;]*/& clocked_by (sys_clk) reset_by (sys_rst_n)/' PCIEWRAPPER2.bsv\n"
  },
  {
    "path": "generated/scripts/generate_pcie3.sh",
    "content": "#\n\nset -x\nset -e\n../scripts/importbvi.py \\\n   -I \\\n   PcieWrap \\\n   -P \\\n   pcieWrap \\\n   -n sys_reset \\\n   -r sys_reset \\\n   -n sys_clk \\\n   -c sys_clk \\\n   -n user_clk \\\n   -c user_clk \\\n   -n user_reset \\\n   -r user_reset \\\n   -n int_dclk_out \\\n   -c int_dclk_out \\\n   -n int_oobclk_out \\\n   -c int_oobclk_out \\\n   -n int_pipe_rxusrclk_out \\\n   -c int_pipe_rxusrclk_out \\\n   -n int_qplloutclk_out \\\n   -c int_qplloutclk_out \\\n   -n int_rxoutclk_out \\\n   -c int_rxoutclk_out \\\n   -n int_userclk1_out \\\n   -n int_userclk2_out \\\n   -c int_userclk1_out \\\n   -c int_userclk2_out \\\n   -n int_pclk_out_slave \\\n   -c int_pclk_out_slave \\\n   -n int_qplloutrefclk_out \\\n   -c int_qplloutrefclk_out \\\n   -f \\\n   common \\\n   -f \\\n   int_qplllock \\\n   -f \\\n   int_pclk_sel \\\n   -f \\\n   pipe_userclk1 \\\n   -f \\\n   pipe_userclk2 \\\n   -f \\\n   cfg_mgmt_type1 \\\n   -f \\\n   cfg_req_pm_transition \\\n   -f \\\n   pci_exp \\\n   -f \\\n   pipe \\\n   -f \\\n   user \\\n   -o \\\n   ../xilinx/PCIEWRAPPER3.bsv \\\n   -p lanes \\\n   ../../out/nfsume/pcie3_7x_0/pcie3_7x_0_stub.v\n\n# remove junk emitted into \"import BVI =\"\nsed -i 's/(pci_exp_txn,//' ../xilinx/PCIEWRAPPER3.bsv\n\n# move user_clk and user_reset to top in place of boilerplate default_clock and default_reset\nsed -i 's/output_clock user_clk(user_clk);//' ../xilinx/PCIEWRAPPER3.bsv\nsed -i 's/output_reset user_reset(user_reset);//' ../xilinx/PCIEWRAPPER3.bsv\nsed -i 's/default_clock clk();/output_clock user_clk(user_clk);/' ../xilinx/PCIEWRAPPER3.bsv\nsed -i 's/default_reset rst();/output_reset user_reset(user_reset);/' ../xilinx/PCIEWRAPPER3.bsv\n# remove extra reset\nsed -i 's/Reset sys_clk_reset, //' ../xilinx/PCIEWRAPPER3.bsv\nsed -i 's/input_reset sys_clk_reset() = sys_clk_reset;//' ../xilinx/PCIEWRAPPER3.bsv\n\n# make sys_clk and sys_reset the default\nsed -i 's/input_clock sys_clk/default_clock sys_clk/' ../xilinx/PCIEWRAPPER3.bsv\nsed -i 's/input_reset sys_reset/default_reset sys_reset/' ../xilinx/PCIEWRAPPER3.bsv\n\n# add clocked_by user_clk \nsed -i 's/method cfg[^;]*/& clocked_by (user_clk) reset_by (user_reset)/' ../xilinx/PCIEWRAPPER3.bsv\nsed -i 's/method ds[^;]*/& clocked_by (user_clk) reset_by (user_reset)/' ../xilinx/PCIEWRAPPER3.bsv\nsed -i 's/method m_axis[^;]*/& clocked_by (user_clk) reset_by (user_reset)/' ../xilinx/PCIEWRAPPER3.bsv\nsed -i 's/method s_axis[^;]*/& clocked_by (user_clk) reset_by (user_reset)/' ../xilinx/PCIEWRAPPER3.bsv\nsed -i 's/method pcie_[^;]*/& clocked_by (user_clk) reset_by (user_reset)/' ../xilinx/PCIEWRAPPER3.bsv\nsed -i 's/method user_[^;]*/& clocked_by (user_clk) reset_by (user_reset)/' ../xilinx/PCIEWRAPPER3.bsv\nsed -i 's/method[^;]*EN_[^;]*/& clocked_by (user_clk) reset_by (user_reset)/' ../xilinx/PCIEWRAPPER3.bsv\n# fix the double edited lines\nsed -i 's/clocked_by (user_clk) reset_by (user_reset) clocked_by (user_clk) reset_by (user_reset)/clocked_by (user_clk) reset_by (user_reset)/'  ../xilinx/PCIEWRAPPER3.bsv\n\n# now the pcie clocks\nsed -i 's/\\(method rx[^;]*\\)clocked_by[^;]*/\\1 clocked_by (sys_clk) reset_by (sys_reset)/' ../xilinx/PCIEWRAPPER3.bsv\nsed -i 's/method pci_exp_tx[^;]*/& clocked_by (sys_clk) reset_by (sys_reset)/' ../xilinx/PCIEWRAPPER3.bsv\n#sed -i 's/PciewrapPci_exp/PciewrapPci_exp#\\(numeric type lanes\\)/' ../xilinx/PCIEWRAPPER3.bsv\n\n\n"
  },
  {
    "path": "generated/scripts/generate_pcie3u.sh",
    "content": "#\n\nset -x\nset -e\n../scripts/importbvi.py \\\n   -I \\\n   PcieWrap \\\n   -P \\\n   pcieWrap \\\n   -n sys_reset \\\n   -r sys_reset \\\n   -n sys_clk \\\n   -c sys_clk \\\n   -c sys_clk_gt \\\n   -n user_clk \\\n   -c user_clk \\\n   -n user_reset \\\n   -r user_reset \\\n   -n int_dclk_out \\\n   -c int_dclk_out \\\n   -n int_oobclk_out \\\n   -c int_oobclk_out \\\n   -n int_pipe_rxusrclk_out \\\n   -c int_pipe_rxusrclk_out \\\n   -n int_qplloutclk_out \\\n   -c int_qplloutclk_out \\\n   -n int_rxoutclk_out \\\n   -c int_rxoutclk_out \\\n   -n int_userclk1_out \\\n   -n int_userclk2_out \\\n   -c int_userclk1_out \\\n   -c int_userclk2_out \\\n   -n int_pclk_out_slave \\\n   -c int_pclk_out_slave \\\n   -n int_qplloutrefclk_out \\\n   -c int_qplloutrefclk_out \\\n   -f \\\n   common \\\n   -f \\\n   int_qpll1 \\\n   -f pcie_perstn1 \\\n   -f pcie_perstn0 \\\n   -f \\\n   int_pclk_sel \\\n   -f \\\n   pipe_userclk1 \\\n   -f \\\n   pipe_userclk2 \\\n   -f \\\n   cfg_mgmt_type1 \\\n   -f \\\n   cfg_req_pm_transition \\\n   -f \\\n   pci_exp \\\n   -f \\\n   pipe \\\n   -f \\\n   user \\\n   -o \\\n   ../xilinx/PCIEWRAPPER3u.bsv \\\n   -p lanes \\\n   ../../out/vcu108/pcie3_ultrascale_0/pcie3_ultrascale_0_stub.v\n\n# remove junk emitted into \"import BVI =\"\nsed -i 's/(pci_exp_txn,//' ../xilinx/PCIEWRAPPER3u.bsv\n\n# move user_clk and user_reset to top in place of boilerplate default_clock and default_reset\nsed -i 's/output_clock user_clk(user_clk);//' ../xilinx/PCIEWRAPPER3u.bsv\nsed -i 's/output_reset user_reset(user_reset);//' ../xilinx/PCIEWRAPPER3u.bsv\nsed -i 's/default_clock clk();/output_clock user_clk(user_clk);/' ../xilinx/PCIEWRAPPER3u.bsv\nsed -i 's/default_reset rst();/output_reset user_reset(user_reset);/' ../xilinx/PCIEWRAPPER3u.bsv\n# remove extra reset\nsed -i 's/Reset sys_clk_reset, //' ../xilinx/PCIEWRAPPER3u.bsv\nsed -i 's/input_reset sys_clk_reset() = sys_clk_reset;//' ../xilinx/PCIEWRAPPER3u.bsv\n\n# make sys_clk and sys_reset the default\nsed -i 's/input_clock sys_clk/default_clock sys_clk/' ../xilinx/PCIEWRAPPER3u.bsv\nsed -i 's/input_reset sys_reset/default_reset sys_reset/' ../xilinx/PCIEWRAPPER3u.bsv\n\n# add clocked_by user_clk \nsed -i 's/method cfg[^;]*/& clocked_by (user_clk) reset_by (user_reset)/' ../xilinx/PCIEWRAPPER3u.bsv\nsed -i 's/method ds[^;]*/& clocked_by (user_clk) reset_by (user_reset)/' ../xilinx/PCIEWRAPPER3u.bsv\nsed -i 's/method m_axis[^;]*/& clocked_by (user_clk) reset_by (user_reset)/' ../xilinx/PCIEWRAPPER3u.bsv\nsed -i 's/method s_axis[^;]*/& clocked_by (user_clk) reset_by (user_reset)/' ../xilinx/PCIEWRAPPER3u.bsv\nsed -i 's/method pcie_[^;]*/& clocked_by (user_clk) reset_by (user_reset)/' ../xilinx/PCIEWRAPPER3u.bsv\nsed -i 's/method user_[^;]*/& clocked_by (user_clk) reset_by (user_reset)/' ../xilinx/PCIEWRAPPER3u.bsv\nsed -i 's/method[^;]*EN_[^;]*/& clocked_by (user_clk) reset_by (user_reset)/' ../xilinx/PCIEWRAPPER3u.bsv\n# fix the double edited lines\nsed -i 's/clocked_by (user_clk) reset_by (user_reset) clocked_by (user_clk) reset_by (user_reset)/clocked_by (user_clk) reset_by (user_reset)/'  ../xilinx/PCIEWRAPPER3u.bsv\n\n# now the pcie clocks\nsed -i 's/\\(method rx[^;]*\\)clocked_by[^;]*/\\1 clocked_by (sys_clk) reset_by (sys_reset)/' ../xilinx/PCIEWRAPPER3u.bsv\nsed -i 's/method pci_exp_tx[^;]*/& clocked_by (sys_clk) reset_by (sys_reset)/' ../xilinx/PCIEWRAPPER3u.bsv\n#sed -i 's/PciewrapPci_exp/PciewrapPci_exp#\\(numeric type lanes\\)/' ../xilinx/PCIEWRAPPER3u.bsv\n\n\n"
  },
  {
    "path": "generated/scripts/generate_pcie3uplus.sh",
    "content": "#\n\nset -x\nset -e\n../scripts/importbvi.py \\\n   -I \\\n   PcieWrap \\\n   -P \\\n   pcieWrap \\\n   -n sys_reset \\\n   -r sys_reset \\\n   -n sys_clk \\\n   -c sys_clk \\\n   -c sys_clk_gt \\\n   -n user_clk \\\n   -c user_clk \\\n   -n user_reset \\\n   -r user_reset \\\n   -n int_dclk_out \\\n   -c int_dclk_out \\\n   -n int_oobclk_out \\\n   -c int_oobclk_out \\\n   -n int_pipe_rxusrclk_out \\\n   -c int_pipe_rxusrclk_out \\\n   -n int_qplloutclk_out \\\n   -c int_qplloutclk_out \\\n   -n int_rxoutclk_out \\\n   -c int_rxoutclk_out \\\n   -n int_userclk1_out \\\n   -n int_userclk2_out \\\n   -c int_userclk1_out \\\n   -c int_userclk2_out \\\n   -n int_pclk_out_slave \\\n   -c int_pclk_out_slave \\\n   -n int_qplloutrefclk_out \\\n   -c int_qplloutrefclk_out \\\n   -f \\\n   common \\\n   -f \\\n   int_qpll1 \\\n   -f pcie_perstn1 \\\n   -f pcie_perstn0 \\\n   -f \\\n   int_pclk_sel \\\n   -f \\\n   pipe_userclk1 \\\n   -f \\\n   pipe_userclk2 \\\n   -f \\\n   cfg_mgmt_type1 \\\n   -f \\\n   cfg_req_pm_transition \\\n   -f \\\n   pci_exp \\\n   -f \\\n   pipe \\\n   -f \\\n   user \\\n   -o \\\n   ../xilinx/PCIEWRAPPER3uplus.bsv \\\n   -p lanes \\\n   ../../out/vcu118/pcie_uscale_plus_0/pcie_uscale_plus_0_stub.v\n\n# remove junk emitted into \"import BVI =\"\nsed -i 's/(pci_exp_txn,//' ../xilinx/PCIEWRAPPER3uplus.bsv\n\n# move user_clk and user_reset to top in place of boilerplate default_clock and default_reset\nsed -i 's/output_clock user_clk(user_clk);//' ../xilinx/PCIEWRAPPER3uplus.bsv\nsed -i 's/output_reset user_reset(user_reset);//' ../xilinx/PCIEWRAPPER3uplus.bsv\nsed -i 's/default_clock clk();/output_clock user_clk(user_clk);/' ../xilinx/PCIEWRAPPER3uplus.bsv\nsed -i 's/default_reset rst();/output_reset user_reset(user_reset);/' ../xilinx/PCIEWRAPPER3uplus.bsv\n# remove extra reset\nsed -i 's/Reset sys_clk_reset, //' ../xilinx/PCIEWRAPPER3uplus.bsv\nsed -i 's/input_reset sys_clk_reset() = sys_clk_reset;//' ../xilinx/PCIEWRAPPER3uplus.bsv\n\n# make sys_clk and sys_reset the default\nsed -i 's/input_clock sys_clk/default_clock sys_clk/' ../xilinx/PCIEWRAPPER3uplus.bsv\nsed -i 's/input_reset sys_reset/default_reset sys_reset/' ../xilinx/PCIEWRAPPER3uplus.bsv\n\n# add clocked_by user_clk \nsed -i 's/method cfg[^;]*/& clocked_by (user_clk) reset_by (user_reset)/' ../xilinx/PCIEWRAPPER3uplus.bsv\nsed -i 's/method ds[^;]*/& clocked_by (user_clk) reset_by (user_reset)/' ../xilinx/PCIEWRAPPER3uplus.bsv\nsed -i 's/method m_axis[^;]*/& clocked_by (user_clk) reset_by (user_reset)/' ../xilinx/PCIEWRAPPER3uplus.bsv\nsed -i 's/method s_axis[^;]*/& clocked_by (user_clk) reset_by (user_reset)/' ../xilinx/PCIEWRAPPER3uplus.bsv\nsed -i 's/method pcie_[^;]*/& clocked_by (user_clk) reset_by (user_reset)/' ../xilinx/PCIEWRAPPER3uplus.bsv\nsed -i 's/method user_[^;]*/& clocked_by (user_clk) reset_by (user_reset)/' ../xilinx/PCIEWRAPPER3uplus.bsv\nsed -i 's/method[^;]*EN_[^;]*/& clocked_by (user_clk) reset_by (user_reset)/' ../xilinx/PCIEWRAPPER3uplus.bsv\n# fix the double edited lines\nsed -i 's/clocked_by (user_clk) reset_by (user_reset) clocked_by (user_clk) reset_by (user_reset)/clocked_by (user_clk) reset_by (user_reset)/'  ../xilinx/PCIEWRAPPER3uplus.bsv\n\n# now the pcie clocks\nsed -i 's/\\(method rx[^;]*\\)clocked_by[^;]*/\\1 clocked_by (sys_clk) reset_by (sys_reset)/' ../xilinx/PCIEWRAPPER3uplus.bsv\nsed -i 's/method pci_exp_tx[^;]*/& clocked_by (sys_clk) reset_by (sys_reset)/' ../xilinx/PCIEWRAPPER3uplus.bsv\n#sed -i 's/PciewrapPci_exp/PciewrapPci_exp#\\(numeric type lanes\\)/' ../xilinx/PCIEWRAPPER3uplus.bsv\n\n\n"
  },
  {
    "path": "generated/scripts/generate_pcie_2_1.sh",
    "content": "#\nset -x\nset -e\nscripts/importbvi.py -o PCIE_2_1.bsv -C PCIE_2_1 -P PCIE -I PcieIf \\\n    -f LL2 -f PL2 -f TL2 -f PLLINK -f DBG -f DRP -f MIM -f PL -f TRN \\\n    -f CFGAER -f CFGCOMMAND -f CFGDEV -f CFGPMR -f CFGDS -f CFGERR \\\n    -f CFGFORCE -f CFGINTERRUPT -f CFGLINK -f CFGMGMT -f CFGMSG \\\n    -f CFGPM -f CFGROOT -f CFGSUBSYS -f CFGTRANS \\\n    -e C_DATA_WIDTH:64 \\\n    -e \"CFG_VEND_ID:16'h1BE7\" -e \"CFG_DEV_ID:16'hB100\" -e \"CFG_REV_ID:8'h00\" \\\n    -e \"CFG_SUBSYS_VEND_ID:16'h1BE7\" -e \"CFG_SUBSYS_ID:16'hA705\" \\\n    -e \"CLASS_CODE:24'h050000\" -e \"DSN_CAP_NEXTPTR:12'hffc\" \\\n    -e LINK_CAP_ASPM_SUPPORT:0 -e \"LINK_CAP_MAX_LINK_WIDTH:6'h8\" -e 'LINK_CAP_ASPM_OPTIONALITY:\"TRUE\"' \\\n    -e 'LL_REPLAY_TIMEOUT_EN:\"TRUE\"' -e \"LL_REPLAY_TIMEOUT:15'h001a\" -e \"LTSSM_MAX_LINK_WIDTH:6'h8\" \\\n    -e \"MSIX_CAP_PBA_OFFSET:29'ha00\" -e \"MSIX_CAP_TABLE_OFFSET:29'h800\" \\\n    -e \"MSIX_CAP_TABLE_SIZE:11'h003\" -e 'MSIX_CAP_ON:\"TRUE\"' \\\n    -e \"PCIE_CAP_NEXTPTR:8'h9C\" \\\n    -e PIPE_PIPELINE_STAGES:1 -e PL_FAST_TRAIN:PL_FAST_TRAIN -e USER_CLK_FREQ:3 \\\n    -e BAR0:BAR0 -e BAR1:BAR1 -e BAR2:BAR2 -e BAR3:BAR3 -e BAR4:BAR4 -e BAR5:BAR5 \\\n    ../../import_components/Xilinx/Vivado/2013.2/data/parts/xilinx/zynq/zynq.lib\n"
  },
  {
    "path": "generated/scripts/generate_pciewrapper.sh",
    "content": "#\nset -x\nset -e\n../scripts/importbvi.py -o PCIEWRAPPER.bsv -I PcieWrap -P PcieWrap \\\n    -n pl_link_partner_gen2_supported \\\n    -n cfg_mgmt_wr_rw1c_as_rw \\\n    -n pipe_gen3_out \\\n    -n pipe_userclk1_in \\\n    -n pipe_userclk2_in \\\n    -n pl_link_gen2_cap \\\n    -c user_clk_out -r user_reset_out \\\n    -c sys_clk -r sys_rst_n \\\n    -f cfg_aer -f cfg_ds -f cfg_err -f cfg_interrupt \\\n    -f cfg_mgmt -f cfg_msg -f cfg_pmcsr -f cfg_pm \\\n    -f cfg_root_control \\\n    -f pipe -f pl_link -f pci_exp -f pcie_drp \\\n    -p lanes \\\n    ../../out/vc707/pcie_7x_0/synth/pcie_7x_0.v\n\n#    xilinx/pcie_7x_v2_1/synth/pcie_7x_0.v\n"
  },
  {
    "path": "generated/scripts/generate_pipeclock.sh",
    "content": "#\nset -e\nset -x\n./scripts/importbvi.py -o PipeClock.bsv -P pclk -I pclk -p pcie_lane \\\n    xilinx/7x/pcie/source/pcie_7x_0_pipe_clock.v \n"
  },
  {
    "path": "generated/scripts/generate_pps7.sh",
    "content": "#\nset -e\nset -x\nscripts/importbvi.py -o PPS7.bsv -I PPS7 -P PPS7 \\\n    -p c_emio_gpio_width:gpio_width \\\n    -p c_m_axi_gp0_thread_id_width:id_width \\\n    -p c_m_axi_gp1_thread_id_width:id_width \\\n    -p c_s_axi_gp0_id_width:id_width \\\n    -p c_s_axi_gp1_id_width:id_width \\\n    -p c_s_axi_acp_id_width:id_width \\\n    -p c_s_axi_hp0_id_width:id_width \\\n    -p c_s_axi_hp0_data_width:data_width \\\n    -p c_s_axi_hp1_id_width:id_width \\\n    -p c_s_axi_hp1_data_width:data_width \\\n    -p c_s_axi_hp2_id_width:id_width \\\n    -p c_s_axi_hp2_data_width:data_width \\\n    -p c_s_axi_hp3_id_width:id_width \\\n    -p c_s_axi_hp3_data_width:data_width \\\n    -p c_mio_primitive:mio_width -p c_dm_width -p c_dq_width -p c_dqs_width \\\n    -c M_AXI_GP1_ACLK \\\n    -c M_AXI_GP0_ACLK -c FCLK_CLK0 \\\n    -c S_AXI_GP0_ACLK -c S_AXI_GP1_ACLK \\\n    -c S_AXI_ACP_ACLK \\\n    -c S_AXI_HP0_ACLK -c S_AXI_HP1_ACLK -c S_AXI_HP2_ACLK -c S_AXI_HP3_ACLK \\\n    -d DDR_ARB \\\n    -e C_NUM_F2P_INTR_INPUTS:16 \\\n    -i PS7EXTENDED:Pps7Can:Pps7Core:Pps7Dma:Pps7Enet:Pps7Event:Pps7Fclk_clktrig:Pps7Fpga:Pps7Ftmd:Pps7Ftmt:Pps7Pjtag:Pps7Sdio:Pps7Spi:Pps7Sram:Pps7Trace:Pps7Ttc:Pps7Uart:Pps7Usb:Pps7Wdt \\\n    xilinx.unused/sources/processing_system7/processing_system7.v\n\n#    -m DDR_DQS:DDR_DQS_p -m DDR_Clk:DDR_Clk_p \\\n#    -c ENET0_GMII_RX_CLK -c ENET0_GMII_TX_CLK \\\n#    -c ENET1_GMII_RX_CLK -c ENET1_GMII_TX_CLK \\\n#    -c SDIO0_CLK -c SDIO0_CLK_FB \\\n#    -c SDIO1_CLK -c SDIO1_CLK_FB \\\n#    -c TTC0_CLK0_IN -c TTC0_CLK1_IN -c TTC0_CLK2_IN \\\n#    -c TTC1_CLK0_IN -c TTC1_CLK1_IN -c TTC1_CLK2_IN \\\n#    -c WDT_CLK_IN \\\n#    -c TRACE_CLK \\\n#    -c DMA0_ACLK -c DMA1_ACLK -c DMA2_ACLK -c DMA3_ACLK \\\n#    -c FCLK_CLK3 -c FCLK_CLK2 -c FCLK_CLK1 \\\n#    -c FTMD_TRACEIN_CLK \\\n#    -c PS_CLK \\\n\n\n"
  },
  {
    "path": "generated/scripts/generate_pps7lib.sh",
    "content": "#\nset -x\nset -e\nscripts/importbvi.py -o PPS7LIB.bsv -C PS7 -I PPS7LIB -P PPS7 \\\n    -f DDR -f FTMT -f FTMD -f IRQ \\\n    -f EMIOGPIO -f EMIOPJTAG -f EMIOTRACE -f EMIOWDT -f EVENT -f PS -f SAXIACP \\\n    -c MAXIGP0ACLK -c MAXIGP1ACLK -c SAXIACPACLK \\\n    -c SAXIGP0ACLK -c SAXIGP1ACLK \\\n    -c SAXIHP0ACLK -c SAXIHP1ACLK -c SAXIHP2ACLK -c SAXIHP3ACLK \\\n    -i PS7EXTENDED:Pps7Emiocan:Pps7Emioenet:Pps7Emiopjtag:Pps7Emiosdio:Pps7Emiospi:Pps7Emiotrace:Pps7Emiottc:Pps7Emiouart:Pps7Emiousb:Pps7Emiowdt:Pps7Dma:Pps7Ftmd:Pps7Ftmt \\\n    --notdef Pps7Maxigp --notdef Pps7Saxigp --notdef Pps7Saxihp --notdef Pps7Saxiacp \\\n    ../../import_components/Xilinx/Vivado/2013.2/data/parts/xilinx/zynq/zynq.lib\n\n#    -c DMA0ACLK -c DMA1ACLK -c DMA2ACLK -c DMA3ACLK \\\n#    -c EMIOENET0GMIIRXCLK -c EMIOENET0GMIITXCLK \\\n#    -c EMIOENET1GMIIRXCLK -c EMIOENET1GMIITXCLK \\\n#    -c EMIOSDIO0CLKFB -c EMIOSDIO1CLKFB -c EMIOTRACECLK \\\n"
  },
  {
    "path": "generated/scripts/generate_zynq_mpsoc.sh",
    "content": "\n#  -c pl_clk0 -c pl_clk1 -r pl_resetn0\n../scripts/importbvi.py -c maxihpm0_fpd_aclk -c maxihpm0_fpd_aclk -c saxihpc0_fpd_aclk -c saxiacp_fpd_aclk -c saxi_lpd_aclk -c saxihp0_fpd_aclk -c saxihp1_fpd_aclk -c saxihp2_fpd_aclk -c saxihp3_fpd_aclk -c sacefpd_aclk -c maxihpm0_lpd_aclk -I PS8 -P PS8 -o ZYNQ_ULTRA.bsv ../../out/zcu102/zynq_ultra_ps_e_0/zynq_ultra_ps_e_0_stub.v\n\nsed -i 's/zynq_ultra_ps_e_0(maxihpm0_fpd_aclk,/zynq_ultra_ps_e_0/' ZYNQ_ULTRA.bsv\nsed -i 's/default_clock clk()/default_clock no_clock/' ZYNQ_ULTRA.bsv\nsed -i 's/default_reset rst()/default_reset no_reset/' ZYNQ_ULTRA.bsv\nsed -i 's/input_reset.*;//' ZYNQ_ULTRA.bsv\nsed -i 's/, Reset .*reset//' ZYNQ_ULTRA.bsv\n##sed -i 's/method maxigp0[^;]*/& clocked_by (maxihpm0_lpd_aclk) reset_by (no_reset)/' ZYNQ_ULTRA.bsv\nsed -i 's/method [a-z][^;]*/& clocked_by (maxihpm0_lpd_aclk) reset_by (no_reset)/' ZYNQ_ULTRA.bsv\n"
  },
  {
    "path": "generated/scripts/importbvi.py",
    "content": "#!/usr/bin/env python3\n# Copyright (c) 2013 Quanta Research Cambridge, Inc.\n#\n# Permission is hereby granted, free of charge, to any person\n# obtaining a copy of this software and associated documentation\n# files (the \"Software\"), to deal in the Software without\n# restriction, including without limitation the rights to use, copy,\n# modify, merge, publish, distribute, sublicense, and/or sell copies\n# of the Software, and to permit persons to whom the Software is\n# furnished to do so, subject to the following conditions:\n#\n# The above copyright notice and this permission notice shall be\n# included in all copies or substantial portions of the Software.\n#\n# THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n# EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n# MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n# BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n# ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n# CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n# SOFTWARE.\n\nfrom __future__ import print_function\nimport copy, json, optparse, os, sys, re, tokenize\n#names of tokens: tokenize.tok_name\n\nmasterlist = []\nparammap = {}\nparamnames = []\nifdefmap = {}\nconditionalcf = {}\nclock_names = []\ndeleted_interface = []\ncommoninterfaces = {}\ntokgenerator = 0\nclock_params = []\nreset_params = []\ntoknum = 0\ntokval = 0\nmodulename = ''\n\nclass PinType(object):\n    def __init__(self, mode, type, name, origname):\n        self.mode = mode\n        self.type = type\n        self.name = name.lower()\n        self.origname = origname\n        self.comment = ''\n        self.separator = ''\n        #print('PNN', self.mode, self.type, self.name, self.origname)\n#\n# parser for .lib files\n#\ndef parsenext():\n    global toknum, tokval\n    while True:\n        toknum, tokval, _, _, _ = next(tokgenerator)\n        if toknum != tokenize.NL and toknum != tokenize.NEWLINE:\n            break\n    #print('Token:', toknum, tokval)\n    if toknum == tokenize.ENDMARKER:\n        return None, None\n    return toknum, tokval\n\ndef validate_token(testval):\n    global toknum, tokval\n    if not testval:\n        print('Error:Got:', toknum, tokval)\n        sys.exit(1)\n    parsenext()\n\ndef parseparam():\n    paramstr = ''\n    validate_token(tokval == '(')\n    while tokval != ')' and toknum != tokenize.ENDMARKER:\n        paramstr = paramstr + tokval\n        parsenext()\n    validate_token(tokval == ')')\n    validate_token(tokval == '{')\n    return paramstr\n\ndef parse_item():\n    global masterlist, modulename\n    paramlist = {}\n    while tokval != '}' and toknum != tokenize.ENDMARKER:\n        paramname = tokval\n        validate_token(toknum == tokenize.NAME)\n        if paramname == 'default_intrinsic_fall' or paramname == 'default_intrinsic_rise':\n            validate_token(tokval == ':')\n            validate_token(toknum == tokenize.NUMBER)\n            continue\n        if paramname == 'bus_type':\n            validate_token(tokval == ':')\n            validate_token(toknum == tokenize.NAME)\n            continue\n        if tokval == '(':\n            paramlist['attr'] = []\n            while True:\n                paramstr = parseparam()\n                plist = parse_item()\n                if paramstr != '' and paramname != 'fpga_condition':\n                    if plist == {}:\n                        paramlist['attr'].append([paramstr])\n                    else:\n                        paramlist['attr'].append([paramstr, plist])\n                if paramname == 'cell' and paramstr == options.cell:\n                    #print('CC', paramstr)\n                    modulename = paramstr\n                    pinlist = {}\n                    for item in plist['attr']:\n                        tname = item[0]\n                        tlist = item[1]\n                        tdir = 'unknowndir'\n                        if tlist.get('direction'):\n                            tdir = tlist['direction']\n                            del tlist['direction']\n                        tsub = ''\n                        ind = tname.find('[')\n                        if ind > 0:\n                            tsub = tname[ind+1:-1]\n                            tname = tname[:ind]\n                        titem = [tdir, tsub, tlist]\n                        ttemp = pinlist.get(tname)\n                        if not ttemp:\n                            pinlist[tname] = titem\n                        elif ttemp[0] != titem[0] or ttemp[2] != titem[2]: \n                            print('different', tname, ttemp, titem)\n                        elif ttemp[1] != titem[1]: \n                            if int(titem[1]) > int(ttemp[1]):\n                                ttemp[1] = titem[1]\n                            else:\n                                print('differentindex', tname, ttemp, titem)\n                    for k, v in sorted(pinlist.items()):\n                        if v[1] == '':\n                            ptemp = 'Bit#(1)'\n                            if options.clock and k in options.clock:\n                                ptemp = 'Clock'\n                            if options.reset and k in options.reset:\n                                ptemp = 'Reset'\n                        else:\n                            ptemp = 'Bit#(' + str(int(v[1])+1) + ')'\n                        ttemp = PinType(v[0], ptemp, k, k)\n                        if v[2] != {}:\n                            ttemp.comment = v[2]\n                        masterlist.append(ttemp)\n                paramname = tokval\n                if toknum != tokenize.NAME:\n                    break\n                parsenext()\n                if tokval != '(':\n                    break\n        else:\n            validate_token(tokval == ':')\n            if paramname not in ['fpga_arc_condition', 'function', 'next_state']:\n                paramlist[paramname] = tokval\n            if toknum == tokenize.NUMBER or toknum == tokenize.NAME or toknum == tokenize.STRING:\n                parsenext()\n            else:\n                validate_token(False)\n            if tokval != '}':\n                validate_token(tokval == ';')\n    validate_token(tokval == '}')\n    if paramlist.get('attr') == []:\n        del paramlist['attr']\n    return paramlist\n\ndef parse_lib(filename):\n    global tokgenerator, masterlist\n    tokgenerator = tokenize.generate_tokens(open(filename).readline)\n    parsenext()\n    if tokval != 'library':\n        sys.exit(1)\n    validate_token(toknum == tokenize.NAME)\n    parseparam()\n    parse_item()\n    searchlist = []\n    for item in masterlist:\n        ind = item.name.find('1')\n        if ind > 0:\n            searchstr = item.name[:ind]\n            #print('II', item.name, searchstr)\n            if searchstr not in searchlist:\n                for iitem in masterlist:\n                    #print('VV', iitem.name, searchstr + '0')\n                    if iitem.name.startswith(searchstr + '0'):\n                        searchlist.append(searchstr)\n                        break\n    for item in masterlist:\n        for sitem in searchlist:\n            tname = item.name\n            if tname.startswith(sitem):\n                tname = tname[len(sitem):]\n                ind = 0\n                while tname[ind] >= '0' and tname[ind] <= '9' and ind < len(tname) - 1:\n                    ind = ind + 1\n                item.name = sitem + tname[:ind] + item.separator + tname[ind:]\n                break\n\n#\n# parser for .v files\n#\ndef processline(line, phase):\n    global masterlist\n    global paramnames, modulename\n    ind = line.find('//')\n    if ind >= 0:\n        line = line[:ind]\n    line = line.strip().strip(',').strip()\n    ind = line.find('[')\n    if ind >= 0:\n        f = line[ind+1:].split(']')\n        f.insert(0, line[:ind])\n        subs = f[1].translate(None,' ').lower()\n        if subs[-2:] == ':0':\n            subs = subs[:-2]\n        m = re.match('([^:]+):([^:]+)', subs)\n        if m:\n            i1 = int(m.group(1))\n            i2 = int(m.group(2))\n            subs = '%d' % (max(i1,i2) - min(i1,i2) + 1)\n        if subs.find('(') >= 0 and subs[-1] == ')':\n            subs = subs[1:-1]\n        if subs[-2:] == '-1':\n            subs = subs[:-2]\n        else:\n            subs = str(int(subs) + 1)\n        if subs.find('(') >= 0 and subs[-1] == ')':\n            subs = subs[1:-1]\n        ind = subs.find('/')\n        if ind > 0:\n            item = subs[:ind]\n            newitem = parammap.get(item)\n            if newitem:\n                item = newitem\n            subs = 'TDiv#('+item+','+subs[ind+1:]+')'\n        else:\n            newitem = parammap.get(subs)\n            if newitem:\n                subs = newitem\n        f[1] = subs\n        line = f\n    else:\n        line = line.split()\n    f = []\n    for ind in range(len(line)):\n        item = line[ind].strip()\n        if item[-3:] == 'reg':\n           item = item[:-3].strip()\n        if item != '' and item != 'integer' and item != '=':\n            f.append(item)\n    #print(\"ARR\", f, file=sys.stderr)\n    if len(f) > 0:\n        if f[0][-1] == ';':\n            return True\n        if f[-1][-1] == ';':\n            f[-1] = f[-1][:-1]\n        if f[0] == 'module':\n            modulename = f[1]\n        if f[0] == 'input' or f[0] == 'output' or f[0] == 'inout':\n            if len(f) == 2:\n                f = [f[0], '', '1', f[1]]\n            if len(f) == 3:\n                f = [f[0], '', f[1], f[2]]\n            # check for parameterized declarations\n            pname = f[2].strip('0123456789/')\n            if len(pname) > 0 and pname not in paramnames and pname[:4] != 'TDiv':\n                print('Missing parameter declaration', pname, file=sys.stderr)\n                paramnames.append(pname)\n            f[2] = 'Bit#(' + f[2] + ')'\n            if options.delete and f[3] in options.delete:\n                return False\n            if options.clock and f[3] in options.clock:\n                f[2] = 'Clock'\n            if options.reset and f[3] in options.reset:\n                f[2] = 'Reset'\n            #print('FF', f, file=sys.stderr)\n        elif f[0].startswith('input') or f[0].startswith('output') or f[0].startswith('inout'):\n            if len(f) == 3:\n                f = [f[0].split()[0], f[0].split()[1], f[1], f[2]]\n            # check for parameterized declarations\n            pname = f[2].strip('0123456789/')\n            if len(pname) > 0 and pname not in paramnames and pname[:4] != 'TDiv':\n                print('Missing parameter declaration', pname, file=sys.stderr)\n                paramnames.append(pname)\n            f[2] = 'Bit#(' + f[2] + ')'\n            if options.delete and f[3] in options.delete:\n                return False\n            if options.clock and f[3] in options.clock:\n                f[2] = 'Clock'\n            if options.reset and f[3] in options.reset:\n                f[2] = 'Reset'\n            #print('FE', f, file=sys.stderr)\n        elif phase == 2:\n            return True\n        if phase == 2:\n            itemfound = False\n            for item in masterlist:\n                if item.origname == f[3]:\n                    item.mode = f[0]\n                    if options.clock and f[3] in options.clock:\n                        item.type = 'Clock'\n                    elif options.reset and f[3] in options.reset:\n                        item.type = 'Reset'\n                    else:\n                        item.type = f[2]\n                    itemfound = True\n                    break\n            if not itemfound:\n                print('UNK not found', f)\n            return False\n        if len(f) == 4:\n            #print('FFDDDDD3', f, file=sys.stderr)\n            masterlist.append(PinType(f[0], f[2], f[3], f[3]))\n        elif len(f) == 2:\n            #print('FFDDDDD2', f, file=sys.stderr)\n            masterlist.append(PinType(f[0], '', f[1], f[1]))\n        else:\n            #print('FFDDDDDE', f, file=sys.stderr)\n            masterlist.append(PinType('UNK', 'FOO', f[0], f[0]))\n    return False\n\ndef parse_verilog(filename):\n    indata = open(filename).read().expandtabs().split('\\n')\n    phase = 1\n    for line in indata:\n        if processline(line, phase):\n            if phase == 2:\n               break\n            phase = 2\n\ndef generate_condition(interfacename):\n    global ifdefmap\n    for k, v in ifdefmap.items():\n        if interfacename in v:\n            print('`ifdef', k, file=options.outfile)\n            return k\n    return None\n\ndef generate_interface(interfacename, paramlist, paramval, ilist, cname):\n    global clock_names, deleted_interface\n    if interfacename in options.notdef:\n        return\n    cflag = generate_condition(interfacename)\n    print('(* always_ready, always_enabled *)', file=options.outfile)\n    methodfound = False\n    for item in ilist:\n        #print(\"GG\", item.name, item.type, item.mode)\n        if item.mode == 'input' and (item.type != 'Clock' and item.type != 'Reset'):\n            methodfound = True\n        elif item.mode == 'output':\n            methodfound = True\n        elif item.mode == 'inout':\n            methodfound = True\n        elif item.mode == 'interface':\n            methodfound = True\n    if not methodfound:\n        deleted_interface.append(interfacename)\n        return\n    print('interface ' + interfacename + paramlist + ';', file=options.outfile)\n    for item in ilist:\n        if item.mode != 'input' and item.mode != 'output' and item.mode != 'inout' and item.mode != 'interface':\n            continue\n        if item.mode == 'input':\n            if item.type != 'Clock' and item.type != 'Reset':\n                print('    method Action      '+item.name+'('+item.type+' v);', file=options.outfile)\n        elif item.mode == 'output':\n            if item.type == 'Clock' and item.type != 'Reset':\n                print('    interface Clock     '+item.name+';', file=options.outfile)\n                clock_names.append(item)\n            else:\n                print('    method '+item.type+'     '+item.name+'();', file=options.outfile)\n        elif item.mode == 'inout':\n            print('    interface Inout#('+item.type+')     '+item.name+';', file=options.outfile)\n        elif item.mode == 'interface' and item.type not in deleted_interface:\n            cflag2 = generate_condition(item.type)\n            print('    interface '+item.type+ paramval +'     '+item.name+';', file=options.outfile)\n            if cflag2:\n                print('`endif', file=options.outfile)\n    print('endinterface', file=options.outfile)\n    if cflag:\n        print('`endif', file=options.outfile)\n\ndef fixname(arg):\n    titem = arg.replace('ZZ', 'ZZA')\n    titem = titem.replace('I2C', 'ZZB')\n    titem = titem.replace('P2F', 'ZZC')\n    titem = titem.replace('F2P', 'ZZD')\n    titem = titem.replace('ev128', 'ZZE')\n    titem = titem.replace('ev1', 'ZZF')\n    titem = titem.replace('l2', 'ZZG')\n    titem = titem.replace('l0', 'ZZH')\n    titem = titem.replace('l1', 'ZZI')\n    return titem\n\ndef goback(arg):\n    titem = arg.replace('ZZB', 'I2C')\n    titem = titem.replace('ZZC', 'P2F')\n    titem = titem.replace('ZZD', 'F2P')\n    titem = titem.replace('ZZA', 'ZZ')\n    titem = titem.replace('ZZE', 'ev128')\n    titem = titem.replace('ZZF', 'ev1')\n    titem = titem.replace('ZZG', 'l2')\n    titem = titem.replace( 'ZZH','l0')\n    titem = titem.replace( 'ZZI','l1')\n    return titem\n\ndef regroup_items(masterlist):\n    global paramnames, commoninterfaces\n    paramnames.sort()\n    masterlist = sorted(masterlist, key=lambda item: item.type if item.mode == 'parameter' else item.name)\n    newlist = []\n    currentgroup = ''\n    prevlist = []\n    for item in masterlist:\n        if item.mode != 'input' and item.mode != 'output' and item.mode != 'inout':\n            newlist.append(item)\n            #print(\"DD\", item.name)\n        else:\n            litem = item.origname\n            titem = fixname(litem)\n            #m = re.search('(.+?)(\\d+)_(.+)', litem)\n            m = re.search('(.+?)(\\d+)(_?)(.+)', titem)\n            #print('OA', titem)\n            separator = '_'\n            indexname = ''\n            skipParse = False;\n            if prevlist != [] and not litem.startswith(currentgroup):\n                print('UU', currentgroup, litem, prevlist, file=sys.stderr)\n            if options.factor:\n                for tstring in options.factor:\n                    if len(litem) > len(tstring) and litem.startswith(tstring):\n                        groupname = tstring\n                        fieldname = litem[len(tstring):]\n                        if fieldname[0] == '_':\n                            fieldname = fieldname[1:]\n                            separator = '_'\n                        else:\n                            separator = ''\n                        m = None\n                        skipParse = True\n                        #print('OM', titem, groupname, fieldname, separator)\n                        break\n            if m:\n                skipcheck = False\n                for checkitem in options.notfactor:\n                    if litem.startswith(checkitem):\n                        skipcheck = True\n                if skipcheck:\n                    newlist.append(item)\n                    #print('OB', item.name)\n                    continue\n                groupname = goback(m.group(1))\n                indexname = goback(m.group(2))\n                separator = goback(m.group(3))\n                fieldname = goback(m.group(4))\n                #print('OO', item.name, [groupname, indexname, fieldname], file=sys.stderr)\n            elif separator != '' and skipParse != True:\n                m = re.search('(.+?)_(.+)', litem)\n                if not m:\n                    newlist.append(item)\n                    #print('OD', item.name)\n                    continue\n                if len(m.group(1)) == 1: # if only 1 character prefix, get more greedy\n                    m = re.search('(.+)_(.+)', litem)\n                #print('OJ', item.name, m.groups(), file=sys.stderr)\n                fieldname = m.group(2)\n                groupname = m.group(1)\n\n            skipcheck = False\n            for checkitem in options.notfactor:\n                if litem.startswith(checkitem):\n                    skipcheck = True\n            if skipcheck:\n                newlist.append(item)\n                #print('OI', item.name, file=sys.stderr)\n                continue\n            itemname = (groupname + indexname).lower()\n            if itemname in ['event']:\n                itemname = itemname + '_'\n            interfacename = options.ifprefix[0].upper() + options.ifprefix[1:].lower() + groupname[0].upper() + groupname[1:].lower()\n            if not commoninterfaces.get(interfacename):\n                commoninterfaces[interfacename] = {}\n            if not commoninterfaces[interfacename].get(indexname):\n                commoninterfaces[interfacename][indexname] = []\n                t = PinType('interface', interfacename, itemname, groupname+indexname+separator)\n                #print('OZ', interfacename, itemname, groupname+indexname+separator, file=sys.stderr)\n                t.separator = separator\n                newlist.append(t)\n            #print('OH', itemname, separator, file=sys.stderr)\n            foo = copy.copy(item)\n            foo.origname = fieldname\n            lfield = fieldname.lower()\n            if lfield in ['assert', 'do']:\n                lfield = 'zz' + lfield      # prefix prohibited names with 'zz'\n            foo.name = lfield\n            commoninterfaces[interfacename][indexname].append(foo)\n    return newlist\n\ndef generate_inter_declarations(paramlist, paramval):\n    global commoninterfaces\n    for k, v in sorted(commoninterfaces.items()):\n        #print('interface', k, file=sys.stderr)\n        for kuse, vuse in sorted(v.items()):\n            if kuse == '' or kuse == '0':\n                generate_interface(k, paramlist, paramval, vuse, [])\n            #else:\n                #print('     ', kuse, json.dumps(vuse), file=sys.stderr)\n\ndef locate_clocks(item, prefix):\n    global clock_params, reset_params\n    pname = prefix + item.name\n    if item.mode == 'input':\n        if item.type == 'Clock':\n            clock_params.append(pname.lower())\n            reset_params.append(pname.lower() + '_reset')\n        if item.type == 'Reset':\n            reset_params.append(pname.lower())\n    elif item.mode == 'interface':\n        temp = commoninterfaces[item.type].get('0')\n        if not temp:\n            temp = commoninterfaces[item.type].get('')\n        if not temp:\n            print('Missing interface definition', item.type, commoninterfaces[item.type])\n            return\n        for titem in temp:\n            locate_clocks(titem, item.origname)\n\ndef generate_clocks(item, indent, prefix):\n    prefname = prefix + item.origname\n    if item.mode == 'input':\n        if item.type == 'Clock':\n            print(indent + 'input_clock '+prefname.lower()+'('+ prefname+') = '+prefname.lower() + ';', file=options.outfile)\n            print(indent + 'input_reset '+prefname.lower()+'_reset() = '+prefname.lower() + '_reset; /* from clock*/', file=options.outfile)\n        if item.type == 'Reset':\n            print(indent + 'input_reset '+prefname.lower()+'('+ prefname +') = '+prefname.lower() + ';', file=options.outfile)\n    elif item.mode == 'interface':\n        temp = commoninterfaces[item.type].get('0')\n        if not temp:\n            temp = commoninterfaces[item.type].get('')\n        if not temp:\n            print('Missing interface clock', item.type, commoninterfaces[item.type])\n            return\n        for titem in temp:\n             generate_clocks(titem, '        ', item.origname)\n\ndef generate_instance(item, indent, prefix, clockedby_arg):\n    global deleted_interface\n    methodlist = ''\n    pname = ''\n    if prefix:\n        pname = prefix.lower()\n        if pname[-1] == '_':\n            pname = pname[:-1]\n        pname = pname + '.'\n        if pname == 'event.':\n            pname = 'event_.'\n    prefname = prefix + item.origname\n    if item.mode == 'input':\n        if item.type != 'Clock' and item.type != 'Reset':\n            print(indent + 'method '+item.name.lower()+'('+ prefname +')' + clockedby_arg + ' enable((*inhigh*) EN_'+prefname+');', file=options.outfile)\n            methodlist = methodlist + ', ' + pname + item.name.lower()\n    elif item.mode == 'output':\n        if item.type == 'Clock':\n            print(indent + 'output_clock '+ item.name.lower()+ '(' + prefname+');', file=options.outfile)\n        elif item.type == 'Reset':\n            print(indent + 'output_reset '+ item.name.lower()+ '(' + prefname+');', file=options.outfile)\n        else:\n            print(indent + 'method '+ prefname + ' ' + item.name.lower()+'()' + clockedby_arg + ';', file=options.outfile)\n            methodlist = methodlist + ', ' + pname + item.name.lower()\n    elif item.mode == 'inout':\n        print(indent + 'ifc_inout '+item.name.lower()+'('+ prefname+');', file=options.outfile)\n    elif item.mode == 'interface':\n        if item.type in deleted_interface:\n            return ''\n        cflag = generate_condition(item.type)\n        print(indent + 'interface '+item.type+'     '+item.name.lower()+';', file=options.outfile)\n        baseitem = commoninterfaces[item.type].get('0')\n        if not baseitem:\n            baseitem = commoninterfaces[item.type].get('')\n        if not baseitem:\n            print('Missing ifc', item.type)\n            return ''\n        clockedby_name = ''\n        for titem in baseitem:\n            #print(\"BB\", titem.mode, titem.type, titem.name)\n            if titem.mode == 'input' and titem.type == 'Clock':\n                clockedby_name = ' clocked_by (' + (item.origname+titem.name).lower() + ') reset_by (' + (item.origname+titem.name).lower() + '_reset)'\n        templist = ''\n        for titem in baseitem:\n            templist = templist + generate_instance(titem, '        ', item.origname, clockedby_name)\n        if cflag:\n            if not conditionalcf.get(cflag):\n                conditionalcf[cflag] = ''\n            conditionalcf[cflag] = conditionalcf[cflag] + templist\n        else:\n            methodlist = methodlist + templist\n        print('    endinterface', file=options.outfile)\n        if cflag:\n            print('`endif', file=options.outfile)\n    return methodlist\n\ndef generate_bsv():\n    global paramnames, modulename, clock_names\n    global clock_params, reset_params, options\n    # generate output file\n    print('\\n/*', file=options.outfile)\n    for item in sys.argv:\n        print('   ' + item, file=options.outfile)\n    print('*/\\n', file=options.outfile)\n    for item in ['Clocks', 'DefaultValue', 'XilinxCells', 'GetPut', 'AxiBits']:\n        print('import ' + item + '::*;', file=options.outfile)\n    print('', file=options.outfile)\n    paramlist = ''\n    for item in paramnames:\n        paramlist = paramlist + ', numeric type ' + item\n    if paramlist != '':\n        paramlist = '#(' + paramlist[2:] + ')'\n    paramval = paramlist.replace('numeric type ', '')\n    generate_inter_declarations(paramlist, paramval)\n    generate_interface(options.ifname, paramlist, paramval, masterlist, clock_names)\n    print('import \"BVI\" '+modulename + ' =', file=options.outfile)\n    temp = 'module mk' + options.ifname\n    for item in masterlist:\n        locate_clocks(item, '')\n    if clock_params != [] or reset_params != []:\n        sepstring = '#('\n        for item in clock_params:\n            temp = temp + sepstring + 'Clock ' + item\n            sepstring = ', '\n        for item in reset_params:\n            temp = temp + sepstring + 'Reset ' + item\n        temp = temp + ')'\n    temp = temp + '(' + options.ifname + paramval + ');'\n    print(temp, file=options.outfile)\n    for item in paramnames:\n        print('    let ' + item + ' = valueOf(' + item + ');', file=options.outfile)\n    print('    default_clock clk();', file=options.outfile)\n    print('    default_reset rst();', file=options.outfile)\n    #for item in masterlist:\n    #    if item.mode == 'parameter':\n    #        print('    parameter ' + item.type + ' = ' + item.name + ';', file=options.outfile)\n    if options.export:\n        for item in options.export:\n            colonind = item.find(':')\n            if colonind > 0:\n                print('    parameter ' + item[:colonind] + ' = ' + item[colonind+1:] + ';', file=options.outfile)\n    methodlist = ''\n    for item in masterlist:\n        generate_clocks(item, '    ', '')\n    for item in masterlist:\n        methodlist = methodlist + generate_instance(item, '    ', '', '')\n    if methodlist != '':\n        methodlist = methodlist[2:]\n        if conditionalcf != {}:\n            for k, v in sorted(conditionalcf.items()):\n                mtemp = '(' + methodlist + v + ')'\n                print('`ifdef', k, file=options.outfile)\n                print('    schedule '+mtemp + ' CF ' + mtemp + ';', file=options.outfile)\n                print('`else', file=options.outfile)\n        methodlist = '(' + methodlist + ')'\n        print('    schedule '+methodlist + ' CF ' + methodlist + ';', file=options.outfile)\n        if conditionalcf != {}:\n            print('`endif', file=options.outfile)\n    print('endmodule', file=options.outfile)\n\nif __name__=='__main__':\n    parser = optparse.OptionParser(\"usage: %prog [options] arg\")\n    parser.add_option(\"-o\", \"--output\", dest=\"filename\", help=\"write data to FILENAME\")\n    parser.add_option(\"-p\", \"--param\", action=\"append\", dest=\"param\")\n    parser.add_option(\"-f\", \"--factor\", action=\"append\", dest=\"factor\")\n    parser.add_option(\"-c\", \"--clock\", action=\"append\", dest=\"clock\")\n    parser.add_option(\"-r\", \"--reset\", action=\"append\", dest=\"reset\")\n    parser.add_option(\"-d\", \"--delete\", action=\"append\", dest=\"delete\")\n    parser.add_option(\"-e\", \"--export\", action=\"append\", dest=\"export\")\n    parser.add_option(\"--notdef\", action=\"append\", dest=\"notdef\")\n    parser.add_option(\"-i\", \"--ifdef\", action=\"append\", dest=\"ifdef\")\n    parser.add_option(\"-n\", \"--notfactor\", action=\"append\", dest=\"notfactor\")\n    parser.add_option(\"-C\", \"--cell\", dest=\"cell\")\n    parser.add_option(\"-P\", \"--ifprefix\", dest=\"ifprefix\")\n    parser.add_option(\"-I\", \"--ifname\", dest=\"ifname\")\n    (options, args) = parser.parse_args()\n    print('KK', options, args, file=sys.stderr)\n    if options.filename is None or len(args) == 0 or options.ifname is None or options.ifprefix is None:\n        print('Missing \"--o\" option, missing input filenames, missing ifname or missing ifprefix.  Run \" importbvi.py -h \" to see available options')\n        sys.exit(1)\n    options.outfile = open(options.filename, 'w')\n    if options.notfactor == None:\n        options.notfactor = []\n    if options.notdef == None:\n        options.notdef = []\n    if options.param:\n        for item in options.param:\n            item2 = item.split(':')\n            if len(item2) == 1:\n                if item2[0] not in paramnames:\n                    paramnames.append(item2[0])\n            else:\n                parammap[item2[0]] = item2[1]\n                if item2[1] not in paramnames:\n                    paramnames.append(item2[1])\n    if options.ifdef:\n        for item in options.ifdef:\n            item2 = item.split(':')\n            ifdefmap[item2[0]] = item2[1:]\n            print('III', ifdefmap, file=sys.stderr)\n    if len(args) != 1:\n        print(\"incorrect number of arguments\", file=sys.stderr)\n    else:\n        if args[0].endswith('.lib'):\n            parse_lib(args[0])\n        else:\n            parse_verilog(args[0])\n        masterlist = regroup_items(masterlist)\n        generate_bsv()\n"
  },
  {
    "path": "gralloc/Android.mk",
    "content": "LOCAL_PATH:= $(call my-dir)\n\ninclude $(CLEAR_VARS)\n\nLOCAL_MODULE_PATH := $(TARGET_OUT_SHARED_LIBRARIES)/hw\nLOCAL_SHARED_LIBRARIES := libcutils liblog\n\nHDMI_SRC_FILES = DmaConfigProxy.cpp DmaIndicationWrapper.cpp HdmiDisplayRequestProxy.cpp HdmiDisplayIndicationWrapper.cpp HdmiInternalRequestProxy.cpp HdmiInternalIndicationWrapper.cpp\n\nLOCAL_SRC_FILES := \t\\\n\t../cpp/portal.cpp ../cpp/dmaManager.cpp \\\n\t$(addprefix ../examples/hdmidisplay/zedboard/jni/, $(HDMI_SRC_FILES)) \\\n\t gralloc.cpp mapper.cpp\n\nLOCAL_MODULE_TAGS = optional\nLOCAL_MODULE := gralloc.portal\nLOCAL_CFLAGS:= -DZYNQ -DLOG_TAG=\\\"gralloc\\\" -I$(LOCAL_PATH)/../cpp -I$(LOCAL_PATH)/../lib/cpp -I$(LOCAL_PATH)/.. -I$(LOCAL_PATH)/../examples/hdmidisplay/zedboard/jni -I$(LOCAL_PATH)/../drivers/zynqportal\n\ninclude $(BUILD_SHARED_LIBRARY)\n"
  },
  {
    "path": "gralloc/Makefile",
    "content": "##\n## Usage: make BOARD=[zedboard,zc702] ANDROID_TOP=/path/to/android\n##\n\nall: gralloc.portal.so\n\n ../examples/hdmidisplay/$(BOARD)/jni/HdmiDisplayRequestProxy.h: ../lib/bsv/HdmiDisplay.bsv\n\t(cd ../examples/hdmidisplay; make gen.$(BOARD) build.$(BOARD))\n\tcp -v ../examples/hdmidisplay/$(BOARD)/bin/*.bin* .\n\ngralloc.portal.so: gralloc.cpp mapper.cpp Android.mk ../lib/bsv/HdmiDisplay.bsv ../examples/hdmidisplay/$(BOARD)/jni/HdmiDisplayRequestProxy.h\n\tpushd $(ANDROID_TOP); . ./build/envsetup.sh; lunch zedboard-userdebug; popd; TOP=$(ANDROID_TOP) mm showcommands\n\tcp -v $(ANDROID_TOP)/out/target/product/zedboard/system/lib/hw/gralloc.portal.so gralloc.portal.so\n"
  },
  {
    "path": "gralloc/README",
    "content": "\nTo compile the gralloc library:\n\n1. cd <top of android build tree>\n    (to build this tree, see: https://github.com/cambridgehackers/zynq-android4/wiki/ZynqAndroid4.1 )\n2. set environment variables from that build tree:\n    source ./build/envsetup.sh; lunch zedboard-userdebug\n3. cd <gralloc library directory (the directory containing this README file)\n4. Compile source:\n    TOP=<top of android build tree> mm\n    (Note that this will place the resulting library into the android build tree output directory,\n     probably in the file: out/target/product/zedboard/system/lib/hw/gralloc.portal.so )\n\nNOTE: the xilinx GLIBCXX libraries conflict with the gcc system libraries used by the GCC\n   cross compiler (xilinx versions are bad).\n   Because of this, the xilinx 'source xxxx' lines cannot be executed prior to compiling android.\n"
  },
  {
    "path": "gralloc/bitset",
    "content": "/* Copyright (c) 2014 Quanta Research Cambridge, Inc\n *\n * Permission is hereby granted, free of charge, to any person obtaining a\n * copy of this software and associated documentation files (the \"Software\"),\n * to deal in the Software without restriction, including without limitation\n * the rights to use, copy, modify, merge, publish, distribute, sublicense,\n * and/or sell copies of the Software, and to permit persons to whom the\n * Software is furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n * DEALINGS IN THE SOFTWARE.\n */\n\n// bitset stub\n\nnamespace std {\ntemplate <int size> class bitset {\npublic:\n    bitset() {};\n    ~bitset() {};\nprivate:\n    char data[(size+7)/8];\n};\n}\n"
  },
  {
    "path": "gralloc/gr.h",
    "content": "/*\n * Copyright (C) 2008 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef GR_H_\n#define GR_H_\n\n#include <stdint.h>\n#ifdef HAVE_ANDROID_OS      // just want PAGE_SIZE define\n# include <asm/page.h>\n#else\n# include <sys/user.h>\n#endif\n#include <limits.h>\n#include <sys/cdefs.h>\n#include <hardware/gralloc.h>\n#include <pthread.h>\n#include <errno.h>\n\n#include <cutils/native_handle.h>\n\n/*****************************************************************************/\n\nstruct private_module_t;\nstruct private_handle_t;\n\ninline size_t roundUpToPageSize(size_t x) {\n    return (x + (PAGE_SIZE-1)) & ~(PAGE_SIZE-1);\n}\n\nint mapFrameBufferLocked(struct private_module_t* module);\nint terminateBuffer(gralloc_module_t const* module, private_handle_t* hnd);\nint mapBuffer(gralloc_module_t const* module, private_handle_t* hnd);\n\n/*****************************************************************************/\n\nclass Locker {\n    pthread_mutex_t mutex;\npublic:\n    class Autolock {\n        Locker& locker;\n    public:\n        inline Autolock(Locker& locker) : locker(locker) {  locker.lock(); }\n        inline ~Autolock() { locker.unlock(); }\n    };\n    inline Locker()        { pthread_mutex_init(&mutex, 0); }\n    inline ~Locker()       { pthread_mutex_destroy(&mutex); }\n    inline void lock()     { pthread_mutex_lock(&mutex); }\n    inline void unlock()   { pthread_mutex_unlock(&mutex); }\n};\n\n#endif /* GR_H_ */\n"
  },
  {
    "path": "gralloc/gralloc.cpp",
    "content": "/*\n * Copyright (C) 2008 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n#include <limits.h>\n#include <fcntl.h>\n#include <errno.h>\n#include <sys/stat.h>\n#include <sys/types.h>\n#include <sys/ioctl.h>\n#include <cutils/ashmem.h>\n#include <cutils/log.h>\n#include <cutils/atomic.h>\n#include <cutils/properties.h>\n#include <hardware/hardware.h>\n#include <hardware/gralloc.h>\n\n#include \"gralloc_priv.h\"\n#include \"gr.h\"\n\n#include \"MemServerRequest.h\"\n#include \"SGListConfigRequest.h\"\n#include \"DmaIndication.h\"\n#include \"HdmiDisplayRequest.h\"\n#include \"HdmiInternalRequest.h\"\n#include \"HdmiInternalIndication.h\"\n#include \"dmaManager.h\"\n#include \"i2chdmi.h\"\n\nclass TestHdmiIndication : public HdmiInternalIndicationWrapper {\npublic:\n    virtual void vsync ( unsigned long long v ) {\nprintf(\"[%s:%d]\\n\", __FUNCTION__, __LINE__);\n    }\n};\n\n/*****************************************************************************/\n\nstruct gralloc_context_t {\n    alloc_device_t  device;\n    /* our private data here */\n    volatile int vsync;\n    pthread_mutex_t vsync_lock;\n    pthread_cond_t vsync_cond;\n    PortalPoller *poller;\n    HdmiDisplayRequestProxy *hdmiDisplay;\n    HdmiInternalRequestProxy *hdmiInternal;\n    SGListConfigRequestProxy *dmap;\n    DmaManager *dma;\n    SGListConfigIndication *dmaIndication;\n    unsigned int ref_srcAlloc;\n    uint32_t nextSegmentNumber;\n};\n\nstatic gralloc_context_t *gralloc_dev = 0;\n\nstatic int gralloc_alloc_buffer(alloc_device_t* dev,\n                                size_t size, size_t stride, int usage, buffer_handle_t* pHandle);\n\n/*****************************************************************************/\n\nint fb_device_open(hw_module_t const* module, const char* name,\n                   hw_device_t** device);\n\nstatic int gralloc_device_open(const hw_module_t* module, const char* name,\n        hw_device_t** device);\n\nextern int gralloc_lock(gralloc_module_t const* module,\n        buffer_handle_t handle, int usage,\n        int l, int t, int w, int h,\n        void** vaddr);\n\nextern int gralloc_unlock(gralloc_module_t const* module, \n        buffer_handle_t handle);\n\nextern int gralloc_register_buffer(gralloc_module_t const* module,\n        buffer_handle_t handle);\n\nextern int gralloc_unregister_buffer(gralloc_module_t const* module,\n        buffer_handle_t handle);\n\n/*****************************************************************************/\n\nstatic struct hw_module_methods_t gralloc_module_methods = {\n        open: gralloc_device_open\n};\n\nstruct private_gralloc_module_t HAL_MODULE_INFO_SYM = {\n    base: {\n        common: {\n            tag: HARDWARE_MODULE_TAG,\n            version_major: 1,\n            version_minor: 0,\n            id: GRALLOC_HARDWARE_MODULE_ID,\n            name: \"Graphics Memory Allocator Module\",\n            author: \"The Android Open Source Project\",\n            methods: &gralloc_module_methods,\n            dso: 0,\n            reserved: {0}\n        },\n        registerBuffer: gralloc_register_buffer,\n        unregisterBuffer: gralloc_unregister_buffer,\n        lock: gralloc_lock,\n        unlock: gralloc_unlock,\n        perform: 0,\n    },\n    lock: PTHREAD_MUTEX_INITIALIZER,\n    currentBuffer: 0,\n};\n\n/*****************************************************************************/\n\nstatic int gralloc_alloc_buffer(alloc_device_t* dev,\n                                size_t size, size_t stride, int usage, buffer_handle_t* pHandle)\n{\n    int err = 0;\n    int fd = -1;\n    int segmentNumber = 0;\n\n    size = roundUpToPageSize(size);\n    \n    struct gralloc_context_t *ctx = reinterpret_cast<gralloc_context_t*>(dev);\n\n    if (ctx->hdmiDisplay != 0) {\n        fd = portalAlloc(size, 0);\n        ctx->ref_srcAlloc = ctx->dma->reference(fd);\n        //ptr = portalMmap(fd, size);\n    }\n    if (fd < 0) {\n        ALOGE(\"couldn't create ashmem (%s)\", strerror(-errno));\n        err = -errno;\n    }\n\n    if (err == 0) {\n        private_handle_t* hnd = new private_handle_t(fd, size, 0);\n        hnd->stride = stride;\n        gralloc_module_t* module = reinterpret_cast<gralloc_module_t*>(\n                dev->common.module);\n        hnd->segmentNumber = segmentNumber;\n        err = mapBuffer(module, hnd);\n        if (err == 0) {\n            *pHandle = hnd;\n        }\n    }\n    \n    ALOGE_IF(err, \"gralloc failed err=%s\", strerror(-err));\n    \n    return err;\n}\n\n/*****************************************************************************/\n\nstatic int gralloc_alloc(alloc_device_t* dev,\n        int w, int h, int format, int usage,\n        buffer_handle_t* pHandle, int* pStride)\n{\n    if (!pHandle || !pStride)\n        return -EINVAL;\n\n    size_t size, stride;\n\n    int align = 32;\n    int bpp = 0;\n    switch (format) {\n        case HAL_PIXEL_FORMAT_RGBA_8888:\n        case HAL_PIXEL_FORMAT_RGBX_8888:\n        case HAL_PIXEL_FORMAT_BGRA_8888:\n            bpp = 4;\n            break;\n        case HAL_PIXEL_FORMAT_RGB_888:\n            bpp = 3;\n            break;\n        case HAL_PIXEL_FORMAT_RGB_565:\n            bpp = 2;\n            break;\n        default:\n\t  ALOGE(\"unknown pixel format %x in gralloc_alloc\\n\", format);\n            return -EINVAL;\n    }\n    size_t bpr = (w*bpp + (align-1)) & ~(align-1);\n    size = bpr * h;\n    stride = bpr / bpp;\n\n    int err;\n    err = gralloc_alloc_buffer(dev, size, stride, usage, pHandle);\n\n    if (err < 0) {\n        return err;\n    }\n\n    *pStride = stride;\n    return 0;\n}\n\nstatic int gralloc_free(alloc_device_t* dev,\n                        buffer_handle_t handle)\n{\nprintf(\"[%s:%d]\\n\", __FUNCTION__, __LINE__);\n    if (private_handle_t::validate(handle) < 0)\n        return -EINVAL;\n\n    private_handle_t const* hnd = reinterpret_cast<private_handle_t const*>(handle);\n    gralloc_module_t* module = reinterpret_cast<gralloc_module_t*>(dev->common.module);\n    struct gralloc_context_t *ctx = reinterpret_cast<gralloc_context_t*>(dev);\n\n    private_handle_t *private_handle = const_cast<private_handle_t*>(hnd);\n    if (ctx->hdmiDisplay) {\n        ALOGD(\"freeing portal buffer fd %d\\n\", private_handle->fd);\n        close(private_handle->fd);\n    } else {\n        ALOGD(\"freeing ashmem buffer %p\\n\", private_handle);\n        terminateBuffer(module, private_handle);\n    }\n\n    close(hnd->fd);\n    delete hnd;\n    return 0;\n}\n\n/*****************************************************************************/\n\nstatic int gralloc_close(struct hw_device_t *dev)\n{\nprintf(\"[%s:%d]\\n\", __FUNCTION__, __LINE__);\n    gralloc_context_t* ctx = reinterpret_cast<gralloc_context_t*>(dev);\n    if (ctx) {\n        /* TODO: keep a list of all buffer_handle_t created, and free them\n         * all here.\n         */\n        free(ctx);\n    }\n    return 0;\n}\n\nstatic int fb_setSwapInterval(struct framebuffer_device_t* dev,\n            int interval)\n{\nprintf(\"[%s:%d]\\n\", __FUNCTION__, __LINE__);\n    framebuffer_device_t* ctx = (framebuffer_device_t*)dev;\n    if (interval < dev->minSwapInterval || interval > dev->maxSwapInterval)\n        return -EINVAL;\n    // FIXME: implement fb_setSwapInterval\n    return 0;\n}\n\nclass GrallocHdmiDisplayIndications : public HdmiInternalIndicationWrapper {\n    virtual void vsync(unsigned long long v) {\nprintf(\"[%s:%d]\\n\", __FUNCTION__, __LINE__);\n        if (1)\n            ALOGD(\"vsync %llx\\n\", v);\n        pthread_mutex_lock(&gralloc_dev->vsync_lock);\n        gralloc_dev->vsync = 1;\n        pthread_cond_signal(&gralloc_dev->vsync_cond);\n        pthread_mutex_unlock(&gralloc_dev->vsync_lock);\n    }\n};\n\nstatic int fb_post(struct framebuffer_device_t* dev, buffer_handle_t buffer)\n{\nprintf(\"[%s:%d]\\n\", __FUNCTION__, __LINE__);\n    if (private_handle_t::validate(buffer) < 0)\n        return -EINVAL;\n\n    private_handle_t const* hnd = reinterpret_cast<private_handle_t const*>(buffer);\n    private_gralloc_module_t* m = reinterpret_cast<private_gralloc_module_t*>(\n            dev->common.module);\n\n    if (gralloc_dev && gralloc_dev->hdmiDisplay) {\n        ALOGD(\"fb_post segmentNumber=%d\\n\", hnd->segmentNumber);\n        pthread_mutex_lock(&gralloc_dev->vsync_lock);\n        gralloc_dev->vsync = 0;\n        gralloc_dev->hdmiInternal->waitForVsync(0);\n        gralloc_dev->hdmiDisplay->startFrameBuffer(gralloc_dev->ref_srcAlloc,\n\t\t\t\t\t\t   hnd->size/4);\n        gralloc_dev->hdmiInternal->waitForVsync(0);\n        while (!gralloc_dev->vsync) {\n            pthread_cond_wait(&gralloc_dev->vsync_cond, &gralloc_dev->vsync_lock);\n        }\n        pthread_mutex_unlock(&gralloc_dev->vsync_lock);\n        ALOGD(\"fb posted\\n\");\n    }\n\n    return 0;\n}\n\nstatic pthread_t fb_thread;\nstatic void *fb_thread_routine(void *data)\n{\nprintf(\"[%s:%d]\\n\", __FUNCTION__, __LINE__);\n    portalExec(0);\n    return data;\n}\n\nstatic int fb_close(struct hw_device_t *dev)\n{\nprintf(\"[%s:%d]\\n\", __FUNCTION__, __LINE__);\n    pthread_kill(fb_thread, SIGTERM);\n    if (dev) {\n        free(dev);\n    }\n    return 0;\n}\n\nint gralloc_device_open(const hw_module_t* module, const char* name,\n        hw_device_t** device)\n{\nprintf(\"[%s:%d]\\n\", __FUNCTION__, __LINE__);\n    int status = -EINVAL;\n    ALOGD( \"gralloc_device_open: name=%s\\n\", name);\n    init_i2c_hdmi();\n    if (!strcmp(name, \"gpu0\")) {\n        gralloc_context_t *dev;\n        dev = (gralloc_context_t*)malloc(sizeof(*dev));\n        gralloc_dev = dev;\n\n        /* initialize our state here */\n        memset(dev, 0, sizeof(*dev));\n\n        /* initialize the procs */\n        dev->device.common.tag = HARDWARE_DEVICE_TAG;\n        dev->device.common.version = 0;\n        dev->device.common.module = const_cast<hw_module_t*>(module);\n        dev->device.common.close = gralloc_close;\n\n        dev->device.alloc   = gralloc_alloc;\n        dev->device.free    = gralloc_free;\n\n        *device = &dev->device.common;\n\n        pthread_mutexattr_t attr;\n        pthread_mutexattr_init(&attr);\n        pthread_mutex_init(&dev->vsync_lock, &attr);\n        pthread_condattr_t condattr;\n        pthread_condattr_init(&condattr);\n        pthread_cond_init(&dev->vsync_cond, &condattr);\n\tdev->poller = new PortalPoller();\n        dev->hdmiDisplay = new HdmiDisplayRequestProxy(IfcNames_HdmiDisplayRequest, dev->poller);\n        dev->hdmiInternal = new HdmiInternalRequestProxy(IfcNames_HdmiInternalRequest, dev->poller);\n        dev->dma = platformInit();\n        dev->nextSegmentNumber = 0;\n\n        status = 0;\n    } else if (!strcmp(name, GRALLOC_HARDWARE_FB0)) {\n        alloc_device_t* gralloc_device;\n        status = gralloc_open(module, &gralloc_device);\n        if (status < 0)\n            return status;\n\n        /* initialize our state here */\n        framebuffer_device_t *dev = (framebuffer_device_t*)malloc(sizeof(*dev));\n        memset(dev, 0, sizeof(*dev));\n\n        /* initialize the procs */\n        dev->common.tag = HARDWARE_DEVICE_TAG;\n        dev->common.version = 0;\n        dev->common.module = const_cast<hw_module_t*>(module);\n        dev->common.close = fb_close;\n        dev->setSwapInterval = fb_setSwapInterval;\n        dev->post            = fb_post;\n        dev->setUpdateRect = 0;\n\n        pthread_t thread;\n        pthread_attr_t attr;\n        pthread_attr_init(&attr);\n        pthread_create(&thread, &attr, fb_thread_routine, 0);\n\n        private_gralloc_module_t* m = (private_gralloc_module_t*)module;\n        //status = mapFrameBuffer(m);\n        status = 0;\n        if (status >= 0) {\n            /* This table is from CEA-861-D, Table 2: Video Format Timings */\n            static struct {\n               int code;\n               int hactive;\n               int vactive;\n               int hblank;\n               int vblank;\n            } screen_types[] = { /* table only contains progressive types */\n                { 1, 640, 480, 160, 45}, // Weird\n                { 2, 720, 480, 138, 45}, { 3, 720, 480, 138, 45},\n                { 4, 1280, 720, 370, 30},\n                { 8, 1440, 240, 276, 22}, { 9, 1440, 240, 276, 22},\n                {12, 2880, 240, 552, 22}, {13, 2880, 240, 552, 22}, // Weird\n                {14, 1440, 480, 276, 45}, {15, 1440, 480, 276, 45}, // Failed\n                {16, 1920, 1080, 280, 45},\n                {17, 720, 576, 144, 49}, {18, 720, 576, 144, 49},\n                {19, 1280, 720, 700, 30}, // Failed\n                {23, 1440, 288, 288, 24}, {24, 1440, 288, 288, 24}, // Weird\n                {27, 2880, 288, 576, 24}, {28, 2880, 288, 576, 24},\n                {29, 1440, 576, 288, 49}, {30, 1440, 576, 288, 49},\n                {31, 1920, 1080, 720, 45},\n                {32, 1920, 1080, 830, 45},\n                {33, 1920, 1080, 720, 45},\n                {34, 1920, 1080, 280, 45},\n                {35, 2880, 480, 552, 45}, {36, 2880, 480, 552, 45}, // Failed\n                {37, 2880, 576, 576, 49}, {38, 2880, 576, 576, 49}, // Failed\n                {41, 1280, 720, 700, 30}, // Failed\n                {42, 720, 576, 144, 49}, {43, 720, 576, 144, 49},\n                {47, 1280, 720, 370, 30}, // Weird\n                {48, 720, 480, 138, 45}, {49, 720, 480, 138, 45},\n                {52, 720, 576, 144, 49}, {53, 720, 576, 144, 49},\n                {56, 720, 480, 138, 45}, {57, 720, 480, 138, 45}, {0, 0, 0, 0, 0}};\n            int format = HAL_PIXEL_FORMAT_RGBX_8888;\n            unsigned short vsyncwidth = 5;\n            static char screenprop[PROPERTY_VALUE_MAX];\n            int index = 0;\n\n            unsigned short nlines = 480;\n            unsigned short npixels = 720;\n            unsigned short lmin = 45;\n            unsigned short pmin = 138;\n            property_get(\"rw.screencode\", screenprop, \"2\");\n            int screen_code = atoi(screenprop);\n            while (screen_types[index].code && screen_types[index].code != screen_code)\n                index++;\n            if (screen_types[index].code) {\n                nlines = screen_types[index].vactive;\n                npixels = screen_types[index].hactive;\n                lmin = screen_types[index].vblank;\n                pmin = screen_types[index].hblank;\n            }\n            ALOGD(\"[%s:%d] code %d: %d x %d blank %d x %d\\n\", __FUNCTION__, __LINE__, screen_types[index].code, nlines, npixels, lmin, pmin);\n            unsigned short stridebytes = (npixels * 4 + 31) & ~31;\n            const_cast<uint32_t&>(dev->flags) = 0;\n            const_cast<uint32_t&>(dev->width) = npixels;\n            const_cast<uint32_t&>(dev->height) = nlines;\n            const_cast<int&>(dev->stride) = stridebytes;\n            const_cast<int&>(dev->format) = format;\n            const_cast<float&>(dev->xdpi) = 100;\n            const_cast<float&>(dev->ydpi) = 100;\n            const_cast<float&>(dev->fps) = 60;\n            const_cast<int&>(dev->minSwapInterval) = 1;\n            const_cast<int&>(dev->maxSwapInterval) = 1;\n\nvsyncwidth = 0;\n            gralloc_dev->hdmiInternal->setDeLineCountMinMax (lmin - vsyncwidth, lmin + nlines - vsyncwidth, (lmin + lmin + nlines) / 2 - vsyncwidth);\n            gralloc_dev->hdmiInternal->setDePixelCountMinMax (pmin, pmin + npixels, pmin + npixels / 2);\n\t    ALOGD(\"setting clock frequency %ld\\n\", 60l * (long)(pmin + npixels) * (long)(lmin + nlines));\n\t    setClockFrequency(1, 60l * (long)(pmin + npixels) * (long)(lmin + nlines), 0);\n            *device = &dev->common;\n        }\n    }\n    return status;\n}\n"
  },
  {
    "path": "gralloc/gralloc_priv.h",
    "content": "/*\n * Copyright (C) 2008 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef GRALLOC_PRIV_H_\n#define GRALLOC_PRIV_H_\n\n#include <stdint.h>\n#include <limits.h>\n#include <sys/cdefs.h>\n#include <hardware/gralloc.h>\n#include <pthread.h>\n#include <errno.h>\n#include <unistd.h>\n\n#include <cutils/native_handle.h>\n\n#include <linux/fb.h>\n\n/*****************************************************************************/\n\nstruct private_handle_t;\n\nstruct private_gralloc_module_t {\n    gralloc_module_t base;\n\n    pthread_mutex_t lock;\n    buffer_handle_t currentBuffer;\n\n};\n\n/*****************************************************************************/\n\n#ifdef __cplusplus\nstruct private_handle_t : public native_handle {\n#else\nstruct private_handle_t {\n    struct native_handle nativeHandle;\n#endif\n    \n    enum {\n        PRIV_FLAGS_FRAMEBUFFER = 0x00000001\n    };\n\n    // file-descriptors\n    int     fd;\n    // ints\n    int     magic;\n    int     flags;\n    int     size;\n    int     offset;\n\n    // FIXME: the attributes below should be out-of-line\n    int     base;\n    int     pid;\n    int     stride;\n    int     segmentNumber;\n\n#ifdef __cplusplus\n    static const int sNumInts = 6;\n    static const int sNumFds = 1;\n    static const int sMagic = 0x11052012;\n\n    private_handle_t(int fd, int size, int flags) :\n        fd(fd), magic(sMagic), flags(flags), size(size), offset(0),\n        base(0), pid(getpid()), stride(0), segmentNumber(0)\n    {\n        version = sizeof(native_handle);\n        numInts = sNumInts;\n        numFds = sNumFds;\n    }\n    ~private_handle_t() {\n        magic = 0;\n    }\n\n    static int validate(const native_handle* h) {\n        const private_handle_t* hnd = (const private_handle_t*)h;\n        if (!h || h->version != sizeof(native_handle) ||\n                h->numInts != sNumInts || h->numFds != sNumFds ||\n                hnd->magic != sMagic) \n        {\n            ALOGE(\"invalid gralloc handle (at %p)\", h);\n            return -EINVAL;\n        }\n        return 0;\n    }\n#endif\n};\n\n#endif /* GRALLOC_PRIV_H_ */\n"
  },
  {
    "path": "gralloc/mapper.cpp",
    "content": "/*\n * Copyright (C) 2008 The Android Open Source Project\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#include <limits.h>\n#include <errno.h>\n#include <pthread.h>\n#include <unistd.h>\n#include <string.h>\n\n#include <sys/mman.h>\n#include <sys/stat.h>\n#include <sys/types.h>\n\n#include <cutils/log.h>\n#include <cutils/atomic.h>\n\n#include <hardware/hardware.h>\n#include <hardware/gralloc.h>\n\n#include \"gralloc_priv.h\"\n\n\n/* desktop Linux needs a little help with gettid() */\n#if defined(ARCH_X86) && !defined(HAVE_ANDROID_OS)\n#define __KERNEL__\n# include <linux/unistd.h>\npid_t gettid() { return syscall(__NR_gettid);}\n#undef __KERNEL__\n#endif\n\n/*****************************************************************************/\n\nstatic int gralloc_map(gralloc_module_t const* module,\n        buffer_handle_t handle,\n        void** vaddr)\n{\n    private_handle_t* hnd = (private_handle_t*)handle;\n    if (!(hnd->flags & private_handle_t::PRIV_FLAGS_FRAMEBUFFER)) {\n        size_t size = hnd->size;\n        void* mappedAddress = mmap(0, size,\n                PROT_READ|PROT_WRITE, MAP_SHARED, hnd->fd, 0);\n        if (mappedAddress == MAP_FAILED) {\n            ALOGE(\"Could not mmap %s\", strerror(errno));\n            return -errno;\n        }\n        hnd->base = intptr_t(mappedAddress) + hnd->offset;\n        //ALOGD(\"gralloc_map() succeeded fd=%d, off=%d, size=%d, vaddr=%p\",\n        //        hnd->fd, hnd->offset, hnd->size, mappedAddress);\n    }\n    *vaddr = (void*)hnd->base;\n    return 0;\n}\n\nstatic int gralloc_unmap(gralloc_module_t const* module,\n        buffer_handle_t handle)\n{\n    private_handle_t* hnd = (private_handle_t*)handle;\n    if (!(hnd->flags & private_handle_t::PRIV_FLAGS_FRAMEBUFFER)) {\n        void* base = (void*)hnd->base;\n        size_t size = hnd->size;\n        //ALOGD(\"unmapping from %p, size=%d\", base, size);\n        if (munmap(base, size) < 0) {\n            ALOGE(\"Could not unmap %s\", strerror(errno));\n        }\n    }\n    hnd->base = 0;\n    return 0;\n}\n\n/*****************************************************************************/\n\nstatic pthread_mutex_t sMapLock = PTHREAD_MUTEX_INITIALIZER; \n\n/*****************************************************************************/\n\nint gralloc_register_buffer(gralloc_module_t const* module,\n                            buffer_handle_t handle)\n{\n    if (private_handle_t::validate(handle) < 0)\n        return -EINVAL;\n\n    // if this handle was created in this process, then we keep it as is.\n    int err = 0;\n    private_handle_t* hnd = (private_handle_t*)handle;\n    if (hnd->pid != getpid()) {\n        void *vaddr;\n        err = gralloc_map(module, handle, &vaddr);\n    }\n    return err;\n}\n\nint gralloc_unregister_buffer(gralloc_module_t const* module,\n        buffer_handle_t handle)\n{\n    if (private_handle_t::validate(handle) < 0)\n        return -EINVAL;\n\n    // never unmap buffers that were created in this process\n    private_handle_t* hnd = (private_handle_t*)handle;\n    if (hnd->pid != getpid()) {\n        if (hnd->base) {\n            gralloc_unmap(module, handle);\n        }\n    }\n    return 0;\n}\n\nint mapBuffer(gralloc_module_t const* module,\n        private_handle_t* hnd)\n{\n    void* vaddr;\n    return gralloc_map(module, hnd, &vaddr);\n}\n\nint terminateBuffer(gralloc_module_t const* module,\n        private_handle_t* hnd)\n{\n    if (hnd->base) {\n        // this buffer was mapped, unmap it now\n        gralloc_unmap(module, hnd);\n    }\n\n    return 0;\n}\n\nint gralloc_lock(gralloc_module_t const* module,\n        buffer_handle_t handle, int usage,\n        int l, int t, int w, int h,\n        void** vaddr)\n{\n    // this is called when a buffer is being locked for software\n    // access. in thin implementation we have nothing to do since\n    // not synchronization with the h/w is needed.\n    // typically this is used to wait for the h/w to finish with\n    // this buffer if relevant. the data cache may need to be\n    // flushed or invalidated depending on the usage bits and the\n    // hardware.\n\n    if (private_handle_t::validate(handle) < 0)\n        return -EINVAL;\n\n    private_handle_t* hnd = (private_handle_t*)handle;\n    *vaddr = (void*)hnd->base;\n    return 0;\n}\n\nint gralloc_unlock(gralloc_module_t const* module, \n        buffer_handle_t handle)\n{\n    // we're done with a software buffer. nothing to do in this\n    // implementation. typically this is used to flush the data cache.\n\n    if (private_handle_t::validate(handle) < 0)\n        return -EINVAL;\n    return 0;\n}\n"
  },
  {
    "path": "jtag/README",
    "content": "#\n\nOn Ubuntu 12.04:\n    wget http://downloads.sourceforge.net/project/openocd/openocd/0.7.0/openocd-0.7.0.tar.bz2\n\n    sudo apt-get install libftdi-dev\n    #? libftdipp-dev\n\n    ./configure --enable-ft2232_libftdi\n    #     --enable-verbose --enable-verbose-jtag-io --enable-verbose-usb-io --enable-verbose-usb-comms \\\n\nOn Mac:\n    port install libftdi0\n    port install openocd\n\nFor reference, the test machine has kc705 and zedboard plugged in:\n1. lsusb\n        Bus 001 Device 031: ID 0403:6014 Future Technology Devices International, Ltd FT232H Single HS USB-UART/FIFO IC\n        Bus 001 Device 013: ID 0403:6010 Future Technology Devices International, Ltd FT2232C Dual USB-UART/FIFO IC\n\n2. djtgcfg enum\n        Found 2 device(s)\n\n        Device: Zed\n            Product Name:   Digilent Zed\n            User Name:      Zed\n            Serial Number:  210248446939\n\n        Device: JtagSmt1\n            Product Name:   Digilent JTAG-SMT1\n            User Name:      JtagSmt1\n            Serial Number:  210203339470\n\n3. djtgcfg -d JtagSmt1 init\n        Initializing scan chain...\n        Found Device ID: 43651093\n        \n        Found 1 device(s):\n            Device 0: UNKNOWN\n\n4. djtgcfg -d Zed init\n        Initializing scan chain...\n        Found Device ID: 03727093\n        Found Device ID: 4ba00477\n\n        Found 2 device(s):\n            Device 0: UNKNOWN\n            Device 1: UNKNOWN\n\n# Reference info:\n#    http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,395,923&Prod=JTAG-SMT1\n#    http://wiki.analog.com/resources/eval/user-guides/ad-fmcomms1-ebz/quickstart/microblaze_kc705\n"
  },
  {
    "path": "jtag/bsd/xc7k325t_ffg900.bsd",
    "content": "-- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.\n--\n-- This file contains confidential and proprietary information\n-- of Xilinx, Inc. and is protected under U.S. and\n-- international copyright and other intellectual property\n-- laws.\n--\n-- DISCLAIMER\n-- This disclaimer is not a license and does not grant any\n-- rights to the materials distributed herewith. Except as\n-- otherwise provided in a valid license issued to you by\n-- Xilinx, and to the maximum extent permitted by applicable\n-- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n-- (2) Xilinx shall not be liable (whether in contract or tort,\n-- including negligence, or under any other theory of \n-- liability) for any loss or damage of any kind or nature\n-- releated to, arising under or in connection with these\n-- materials, including for any direct, or any indirect,\n-- special, incidental, or consequential loss or damage\n-- (including loss of data, profits, goodwill, or any type of\n-- loss or damage suffered as a result of any action brought\n-- by a third party) even if such damage or loss was\n-- reasonably foreseeable or Xilinx had been advised of the\n-- possibility of the same.\n--\n-- CRITICAL APPLICATIONS\n-- Xilinx products are not designed or intended to be fail-\n-- safe, or for use in any application requiring fail-safe\n-- performance, such as life-support or safety devices or\n-- systems, Class III medical devices, nuclear facilities,\n-- applications related to the deployment of airbags, or any\n-- other applications that could lead to death, personal\n-- injury, or severe property or environmental damage\n-- (individually and collectively, \"Critical\n-- Applications\"). Customer assumes the sole risk and\n-- liability of any use of Xilinx products in Critical\n-- Applications, subject only to applicable laws and\n-- regulations governing limitiations on product liability.\n--\n-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n-- PART OF THIS FILE AT ALL TIMES.\n--\n-- BSDL file for device XC7K325T, package FFG900\n-- Generated by bsdlnet Version 1.7\n-- Generated on Wed Dec 07, 2011  08:15:59 PST\n-- Generated using schematic at v32_top/xc7k325t/schematic\n-- Schematic date = 2011-06-29 14:44:39\n-- Schematic ICM_VARIANT = 28t_n1\n-- Package File date = # Date    : 2011-06-01 11:13:48\n------------------------------------------------------------------------\n-- Modification History\n-- | CR # N/A\n-- | Details -  Initial Release\n------------------------------------------------------------------------\n--\n-- For technical support, http://support.xilinx.com -> enter text 'bsdl'\n-- in the text search box at the left of the page.  If none of\n-- these records resolve your problem you should open a web support case\n-- or contact our technical support at:\n--\n--\tNorth America\t1-800-255-7778\t\thotline@xilinx.com\n--\tUnited Kingdom\t+44 870 7350 610\teurosupport@xilinx.com\n--\tFrance\t\t(33) 1 3463 0100\teurosupport@xilinx.com\n--\tGermany\t\t(49) 89 991 54930\teurosupport@xilinx.com\n--\tJapan\t\t(81) 3-3297-9163\tjhotline@xilinx.com\n--\n-- This BSDL file reflects the pre-configuration JTAG behavior. To reflect\n-- the post-configuration JTAG behavior (if any), edit this file as described\n-- below. Many of these changes are demonstrated by commented-out template\n-- lines preceeding the lines they would replace:\n--\n-- 1. Enable USER instructions as appropriate (see below).\n-- 2. Set disable result of all pads as configured.\n-- 3. Set safe state of boundary cells as necessary.\n-- 4. Rename entity if necessary to avoid name collisions.\n-- 5. Modify USERCODE value in USERCODE_REGISTER declaration.\n--\n-- To prevent losing the current configuration, the boundary scan\n-- test vectors should keep the PROGRAM_B pin high.\n--\n-- PROGRAM_B can only be captured, not updated.  The value\n-- at the pin is always used by the device.\n--\n-- All IOBs prior to configuration, and unused and output-only IOBs following\n-- configuration, will sense their pad values during boundary-scan with an CMOS\n-- input buffer. In order to properly capture a logic high value at one\n-- of these IOBs into its input boundary scan cell, please refer to the\n-- datasheet and user guide for proper input levels.\n--\n-- For post-configuration boundary scan only: If an IOB is configured to use\n-- an input standard that uses VREF pins, then the boundary scan test vectors\n-- must keep the used VREF pins 3-stated.\n\n----------------------------------\n\n-- BSDL File for P1149.6 Standard.\n\n----------------------------------\n-- ----------------------------------------------------------------------\n-- This BSDL file has been checked and verified by JTAG Technologies B.V.\n-- on 2011-12-08, for syntactical and semantic compliance with\n-- IEEE standards 1149.1 and 1149.6\n-- using bsdl32.dll 1.6.1.5 - 20110523 Win32\n-- copyright (c) 2009 JTAG Technologies B.V., All rights reserved\n-- ----------------------------------------------------------------------\n\nentity XC7K325T_FFG900 is\n\n-- Generic Parameter\n\ngeneric (PHYSICAL_PIN_MAP : string := \"FFG900\" );\n\n-- Logical Port Description\n\nport (\n\tCCLK_B10: inout bit; --  CCLK_0\n\tCFGBVS_L10: in bit; --  CFGBVS_0\n\tDONE_M10: inout bit; --  DONE_0\n\tGND: linkage bit_vector (1 to 173);\n\tGNDADC_0: linkage bit;\n\tINIT_B_A10: inout bit; --  INIT_B_0\n\tM0_AB5: in bit; --  M0_0\n\tM1_AB2: in bit; --  M1_0\n\tM2_AB1: in bit; --  M2_0\n\tMGTAVCC: linkage bit_vector (1 to 7);\n\tMGTAVTT: linkage bit_vector (1 to 18);\n\tMGTAVTTRCAL_115: linkage bit;\n\tMGTREFCLK0N_115: linkage bit;\n\tMGTREFCLK0N_116: linkage bit;\n\tMGTREFCLK0N_117: linkage bit;\n\tMGTREFCLK0N_118: linkage bit;\n\tMGTREFCLK0P_115: linkage bit;\n\tMGTREFCLK0P_116: linkage bit;\n\tMGTREFCLK0P_117: linkage bit;\n\tMGTREFCLK0P_118: linkage bit;\n\tMGTREFCLK1N_115: linkage bit;\n\tMGTREFCLK1N_116: linkage bit;\n\tMGTREFCLK1N_117: linkage bit;\n\tMGTREFCLK1N_118: linkage bit;\n\tMGTREFCLK1P_115: linkage bit;\n\tMGTREFCLK1P_116: linkage bit;\n\tMGTREFCLK1P_117: linkage bit;\n\tMGTREFCLK1P_118: linkage bit;\n\tMGTRREF_115: linkage bit;\n\tMGTVCCAUX: linkage bit_vector (1 to 2);\n\tMGTXRXN0_115: in bit;\n\tMGTXRXN0_116: in bit;\n\tMGTXRXN0_117: in bit;\n\tMGTXRXN0_118: in bit;\n\tMGTXRXN1_115: in bit;\n\tMGTXRXN1_116: in bit;\n\tMGTXRXN1_117: in bit;\n\tMGTXRXN1_118: in bit;\n\tMGTXRXN2_115: in bit;\n\tMGTXRXN2_116: in bit;\n\tMGTXRXN2_117: in bit;\n\tMGTXRXN2_118: in bit;\n\tMGTXRXN3_115: in bit;\n\tMGTXRXN3_116: in bit;\n\tMGTXRXN3_117: in bit;\n\tMGTXRXN3_118: in bit;\n\tMGTXRXP0_115: in bit;\n\tMGTXRXP0_116: in bit;\n\tMGTXRXP0_117: in bit;\n\tMGTXRXP0_118: in bit;\n\tMGTXRXP1_115: in bit;\n\tMGTXRXP1_116: in bit;\n\tMGTXRXP1_117: in bit;\n\tMGTXRXP1_118: in bit;\n\tMGTXRXP2_115: in bit;\n\tMGTXRXP2_116: in bit;\n\tMGTXRXP2_117: in bit;\n\tMGTXRXP2_118: in bit;\n\tMGTXRXP3_115: in bit;\n\tMGTXRXP3_116: in bit;\n\tMGTXRXP3_117: in bit;\n\tMGTXRXP3_118: in bit;\n\tMGTXTXN0_115: buffer bit;\n\tMGTXTXN0_116: buffer bit;\n\tMGTXTXN0_117: buffer bit;\n\tMGTXTXN0_118: buffer bit;\n\tMGTXTXN1_115: buffer bit;\n\tMGTXTXN1_116: buffer bit;\n\tMGTXTXN1_117: buffer bit;\n\tMGTXTXN1_118: buffer bit;\n\tMGTXTXN2_115: buffer bit;\n\tMGTXTXN2_116: buffer bit;\n\tMGTXTXN2_117: buffer bit;\n\tMGTXTXN2_118: buffer bit;\n\tMGTXTXN3_115: buffer bit;\n\tMGTXTXN3_116: buffer bit;\n\tMGTXTXN3_117: buffer bit;\n\tMGTXTXN3_118: buffer bit;\n\tMGTXTXP0_115: buffer bit;\n\tMGTXTXP0_116: buffer bit;\n\tMGTXTXP0_117: buffer bit;\n\tMGTXTXP0_118: buffer bit;\n\tMGTXTXP1_115: buffer bit;\n\tMGTXTXP1_116: buffer bit;\n\tMGTXTXP1_117: buffer bit;\n\tMGTXTXP1_118: buffer bit;\n\tMGTXTXP2_115: buffer bit;\n\tMGTXTXP2_116: buffer bit;\n\tMGTXTXP2_117: buffer bit;\n\tMGTXTXP2_118: buffer bit;\n\tMGTXTXP3_115: buffer bit;\n\tMGTXTXP3_116: buffer bit;\n\tMGTXTXP3_117: buffer bit;\n\tMGTXTXP3_118: buffer bit;\n\tPROGRAM_B: in bit; --  PROGRAM_B_0\n\tTCK: in bit; --  TCK_0\n\tTDI: in bit; --  TDI_0\n\tTDN_U14: linkage bit; --  DXN_0\n\tTDO: out bit; --  TDO_0\n\tTDP_U15: linkage bit; --  DXP_0\n\tTMS: in bit; --  TMS_0\n\tVCCADC_0: linkage bit;\n\tVCCAUX: linkage bit_vector (1 to 8);\n\tVCCBATT_0: linkage bit;\n\tVCCBRAM: linkage bit_vector (1 to 4);\n\tVCCINT: linkage bit_vector (1 to 20);\n\tVCCO_0: linkage bit_vector (1 to 2);\n\tVCCO_12: linkage bit_vector (1 to 6);\n\tVCCO_13: linkage bit_vector (1 to 6);\n\tVCCO_14: linkage bit_vector (1 to 6);\n\tVCCO_15: linkage bit_vector (1 to 6);\n\tVCCO_16: linkage bit_vector (1 to 7);\n\tVCCO_17: linkage bit_vector (1 to 7);\n\tVCCO_18: linkage bit_vector (1 to 6);\n\tVCCO_32: linkage bit_vector (1 to 6);\n\tVCCO_33: linkage bit_vector (1 to 6);\n\tVCCO_34: linkage bit_vector (1 to 7);\n\tVN_T14: linkage bit; --  VN_0\n\tVP_R15: linkage bit; --  VP_0\n\tVREFN_R14: linkage bit; --  VREFN_0\n\tVREFP_T15: linkage bit; --  VREFP_0\n\tIO_A11: inout bit; --  PAD34\n\tIO_A12: inout bit; --  PAD35\n\tIO_A13: inout bit; --  PAD45\n\tIO_A15: inout bit; --  PAD49\n\tIO_A16: inout bit; --  PAD90\n\tIO_A17: inout bit; --  PAD91\n\tIO_A18: inout bit; --  PAD95\n\tIO_A20: inout bit; --  PAD92\n\tIO_A21: inout bit; --  PAD93\n\tIO_A22: inout bit; --  PAD97\n\tIO_A23: inout bit; --  PAD103\n\tIO_A25: inout bit; --  PAD120\n\tIO_A26: inout bit; --  PAD121\n\tIO_A27: inout bit; --  PAD115\n\tIO_A28: inout bit; --  PAD119\n\tIO_A30: inout bit; --  PAD135\n\tIO_B12: inout bit; --  PAD31\n\tIO_B13: inout bit; --  PAD44\n\tIO_B14: inout bit; --  PAD48\n\tIO_B15: inout bit; --  PAD47\n\tIO_B17: inout bit; --  PAD85\n\tIO_B18: inout bit; --  PAD94\n\tIO_B19: inout bit; --  PAD99\n\tIO_B20: inout bit; --  PAD89\n\tIO_B22: inout bit; --  PAD96\n\tIO_B23: inout bit; --  PAD102\n\tIO_B24: inout bit; --  PAD117\n\tIO_B25: inout bit; --  PAD125\n\tIO_B27: inout bit; --  PAD114\n\tIO_B28: inout bit; --  PAD118\n\tIO_B29: inout bit; --  PAD131\n\tIO_B30: inout bit; --  PAD134\n\tIO_C11: inout bit; --  PAD37\n\tIO_C12: inout bit; --  PAD30\n\tIO_C14: inout bit; --  PAD43\n\tIO_C15: inout bit; --  PAD46\n\tIO_C16: inout bit; --  PAD81\n\tIO_C17: inout bit; --  PAD84\n\tIO_C19: inout bit; --  PAD98\n\tIO_C20: inout bit; --  PAD88\n\tIO_C21: inout bit; --  PAD67\n\tIO_C22: inout bit; --  PAD71\n\tIO_C24: inout bit; --  PAD116\n\tIO_C25: inout bit; --  PAD124\n\tIO_C26: inout bit; --  PAD123\n\tIO_C27: inout bit; --  PAD127\n\tIO_C29: inout bit; --  PAD130\n\tIO_C30: inout bit; --  PAD133\n\tIO_D11: inout bit; --  PAD36\n\tIO_D12: inout bit; --  PAD26\n\tIO_D13: inout bit; --  PAD27\n\tIO_D14: inout bit; --  PAD42\n\tIO_D16: inout bit; --  PAD80\n\tIO_D17: inout bit; --  PAD76\n\tIO_D18: inout bit; --  PAD77\n\tIO_D19: inout bit; --  PAD79\n\tIO_D21: inout bit; --  PAD66\n\tIO_D22: inout bit; --  PAD70\n\tIO_D23: inout bit; --  PAD105\n\tIO_D24: inout bit; --  PAD109\n\tIO_D26: inout bit; --  PAD122\n\tIO_D27: inout bit; --  PAD126\n\tIO_D28: inout bit; --  PAD129\n\tIO_D29: inout bit; --  PAD132\n\tIO_E11: inout bit; --  PAD33\n\tIO_E13: inout bit; --  PAD29\n\tIO_E14: inout bit; --  PAD40\n\tIO_E15: inout bit; --  PAD41\n\tIO_E16: inout bit; --  PAD39\n\tIO_E18: inout bit; --  PAD100\n\tIO_E19: inout bit; --  PAD78\n\tIO_E20: inout bit; --  PAD75\n\tIO_E21: inout bit; --  PAD73\n\tIO_E23: inout bit; --  PAD104\n\tIO_E24: inout bit; --  PAD108\n\tIO_E25: inout bit; --  PAD107\n\tIO_E26: inout bit; --  PAD111\n\tIO_E28: inout bit; --  PAD128\n\tIO_E29: inout bit; --  PAD136\n\tIO_E30: inout bit; --  PAD137\n\tIO_F11: inout bit; --  PAD32\n\tIO_F12: inout bit; --  PAD28\n\tIO_F13: inout bit; --  PAD25\n\tIO_F15: inout bit; --  PAD38\n\tIO_F16: inout bit; --  PAD50\n\tIO_F17: inout bit; --  PAD87\n\tIO_F18: inout bit; --  PAD83\n\tIO_F20: inout bit; --  PAD74\n\tIO_F21: inout bit; --  PAD72\n\tIO_F22: inout bit; --  PAD69\n\tIO_F23: inout bit; --  PAD101\n\tIO_F25: inout bit; --  PAD106\n\tIO_F26: inout bit; --  PAD110\n\tIO_F27: inout bit; --  PAD143\n\tIO_F28: inout bit; --  PAD141\n\tIO_F30: inout bit; --  PAD145\n\tIO_G12: inout bit; --  PAD1\n\tIO_G13: inout bit; --  PAD24\n\tIO_G14: inout bit; --  PAD23\n\tIO_G15: inout bit; --  PAD15\n\tIO_G17: inout bit; --  PAD86\n\tIO_G18: inout bit; --  PAD82\n\tIO_G19: inout bit; --  PAD51\n\tIO_G20: inout bit; --  PAD55\n\tIO_G22: inout bit; --  PAD68\n\tIO_G23: inout bit; --  PAD112\n\tIO_G24: inout bit; --  PAD113\n\tIO_G25: inout bit; --  PAD150\n\tIO_G27: inout bit; --  PAD142\n\tIO_G28: inout bit; --  PAD140\n\tIO_G29: inout bit; --  PAD144\n\tIO_G30: inout bit; --  PAD149\n\tIO_H11: inout bit; --  PAD20\n\tIO_H12: inout bit; --  PAD21\n\tIO_H14: inout bit; --  PAD22\n\tIO_H15: inout bit; --  PAD14\n\tIO_H16: inout bit; --  PAD19\n\tIO_H17: inout bit; --  PAD57\n\tIO_H19: inout bit; --  PAD59\n\tIO_H20: inout bit; --  PAD54\n\tIO_H21: inout bit; --  PAD64\n\tIO_H22: inout bit; --  PAD65\n\tIO_H24: inout bit; --  PAD138\n\tIO_H25: inout bit; --  PAD139\n\tIO_H26: inout bit; --  PAD146\n\tIO_H27: inout bit; --  PAD147\n\tIO_H29: inout bit; --  PAD165\n\tIO_H30: inout bit; --  PAD148\n\tIO_J11: inout bit; --  PAD16\n\tIO_J12: inout bit; --  PAD17\n\tIO_J13: inout bit; --  PAD9\n\tIO_J14: inout bit; --  PAD11\n\tIO_J16: inout bit; --  PAD18\n\tIO_J17: inout bit; --  PAD56\n\tIO_J18: inout bit; --  PAD53\n\tIO_J19: inout bit; --  PAD58\n\tIO_J21: inout bit; --  PAD160\n\tIO_J22: inout bit; --  PAD161\n\tIO_J23: inout bit; --  PAD152\n\tIO_J24: inout bit; --  PAD153\n\tIO_J26: inout bit; --  PAD171\n\tIO_J27: inout bit; --  PAD166\n\tIO_J28: inout bit; --  PAD167\n\tIO_J29: inout bit; --  PAD164\n\tIO_K11: inout bit; --  PAD13\n\tIO_K13: inout bit; --  PAD8\n\tIO_K14: inout bit; --  PAD10\n\tIO_K15: inout bit; --  PAD5\n\tIO_K16: inout bit; --  PAD3\n\tIO_K18: inout bit; --  PAD52\n\tIO_K19: inout bit; --  PAD62\n\tIO_K20: inout bit; --  PAD63\n\tIO_K21: inout bit; --  PAD159\n\tIO_K23: inout bit; --  PAD156\n\tIO_K24: inout bit; --  PAD157\n\tIO_K25: inout bit; --  PAD175\n\tIO_K26: inout bit; --  PAD170\n\tIO_K28: inout bit; --  PAD176\n\tIO_K29: inout bit; --  PAD177\n\tIO_K30: inout bit; --  PAD169\n\tIO_L11: inout bit; --  PAD12\n\tIO_L12: inout bit; --  PAD6\n\tIO_L13: inout bit; --  PAD7\n\tIO_L15: inout bit; --  PAD4\n\tIO_L16: inout bit; --  PAD2\n\tIO_L17: inout bit; --  PAD60\n\tIO_L18: inout bit; --  PAD61\n\tIO_L20: inout bit; --  PAD163\n\tIO_L21: inout bit; --  PAD158\n\tIO_L22: inout bit; --  PAD154\n\tIO_L23: inout bit; --  PAD155\n\tIO_L25: inout bit; --  PAD174\n\tIO_L26: inout bit; --  PAD172\n\tIO_L27: inout bit; --  PAD173\n\tIO_L28: inout bit; --  PAD179\n\tIO_L30: inout bit; --  PAD168\n\tIO_M19: inout bit; --  PAD151\n\tIO_M20: inout bit; --  PAD162\n\tIO_M22: inout bit; --  PAD198\n\tIO_M23: inout bit; --  PAD199\n\tIO_M24: inout bit; --  PAD196\n\tIO_M25: inout bit; --  PAD197\n\tIO_M27: inout bit; --  PAD183\n\tIO_M28: inout bit; --  PAD178\n\tIO_M29: inout bit; --  PAD180\n\tIO_M30: inout bit; --  PAD181\n\tIO_N19: inout bit; --  PAD188\n\tIO_N20: inout bit; --  PAD189\n\tIO_N21: inout bit; --  PAD190\n\tIO_N22: inout bit; --  PAD191\n\tIO_N24: inout bit; --  PAD193\n\tIO_N25: inout bit; --  PAD186\n\tIO_N26: inout bit; --  PAD187\n\tIO_N27: inout bit; --  PAD182\n\tIO_N29: inout bit; --  PAD184\n\tIO_N30: inout bit; --  PAD185\n\tIO_P19: inout bit; --  PAD200\n\tIO_P21: inout bit; --  PAD194\n\tIO_P22: inout bit; --  PAD195\n\tIO_P23: inout bit; --  PAD192\n\tIO_P24: inout bit; --  PAD202\n\tIO_P26: inout bit; --  PAD220\n\tIO_P27: inout bit; --  PAD216\n\tIO_P28: inout bit; --  PAD217\n\tIO_P29: inout bit; --  PAD214\n\tIO_R19: inout bit; --  PAD201\n\tIO_R20: inout bit; --  PAD204\n\tIO_R21: inout bit; --  PAD205\n\tIO_R23: inout bit; --  PAD206\n\tIO_R24: inout bit; --  PAD207\n\tIO_R25: inout bit; --  PAD203\n\tIO_R26: inout bit; --  PAD221\n\tIO_R28: inout bit; --  PAD222\n\tIO_R29: inout bit; --  PAD215\n\tIO_R30: inout bit; --  PAD218\n\tIO_T20: inout bit; --  PAD208\n\tIO_T21: inout bit; --  PAD209\n\tIO_T22: inout bit; --  PAD210\n\tIO_T23: inout bit; --  PAD211\n\tIO_T25: inout bit; --  PAD228\n\tIO_T26: inout bit; --  PAD224\n\tIO_T27: inout bit; --  PAD225\n\tIO_T28: inout bit; --  PAD223\n\tIO_T30: inout bit; --  PAD219\n\tIO_U19: inout bit; --  PAD212\n\tIO_U20: inout bit; --  PAD213\n\tIO_U22: inout bit; --  PAD242\n\tIO_U23: inout bit; --  PAD243\n\tIO_U24: inout bit; --  PAD246\n\tIO_U25: inout bit; --  PAD229\n\tIO_U27: inout bit; --  PAD226\n\tIO_U28: inout bit; --  PAD227\n\tIO_U29: inout bit; --  PAD230\n\tIO_U30: inout bit; --  PAD231\n\tIO_V19: inout bit; --  PAD238\n\tIO_V20: inout bit; --  PAD239\n\tIO_V21: inout bit; --  PAD244\n\tIO_V22: inout bit; --  PAD245\n\tIO_V24: inout bit; --  PAD247\n\tIO_V25: inout bit; --  PAD236\n\tIO_V26: inout bit; --  PAD232\n\tIO_V27: inout bit; --  PAD233\n\tIO_V29: inout bit; --  PAD234\n\tIO_V30: inout bit; --  PAD235\n\tIO_W19: inout bit; --  PAD250\n\tIO_W21: inout bit; --  PAD248\n\tIO_W22: inout bit; --  PAD249\n\tIO_W23: inout bit; --  PAD240\n\tIO_W24: inout bit; --  PAD241\n\tIO_W26: inout bit; --  PAD237\n\tIO_W27: inout bit; --  PAD254\n\tIO_W28: inout bit; --  PAD255\n\tIO_W29: inout bit; --  PAD258\n\tIO_Y10: inout bit; --  PAD409\n\tIO_Y11: inout bit; --  PAD408\n\tIO_Y13: inout bit; --  PAD401\n\tIO_Y14: inout bit; --  PAD451\n\tIO_Y15: inout bit; --  PAD499\n\tIO_Y16: inout bit; --  PAD498\n\tIO_Y18: inout bit; --  PAD481\n\tIO_Y19: inout bit; --  PAD480\n\tIO_Y20: inout bit; --  PAD301\n\tIO_Y21: inout bit; --  PAD304\n\tIO_Y23: inout bit; --  PAD302\n\tIO_Y24: inout bit; --  PAD303\n\tIO_Y25: inout bit; --  PAD251\n\tIO_Y26: inout bit; --  PAD252\n\tIO_Y28: inout bit; --  PAD256\n\tIO_Y29: inout bit; --  PAD259\n\tIO_Y30: inout bit; --  PAD266\n\tIO_AA8: inout bit; --  PAD404\n\tIO_AA10: inout bit; --  PAD411\n\tIO_AA11: inout bit; --  PAD410\n\tIO_AA12: inout bit; --  PAD402\n\tIO_AA13: inout bit; --  PAD412\n\tIO_AA15: inout bit; --  PAD490\n\tIO_AA16: inout bit; --  PAD497\n\tIO_AA17: inout bit; --  PAD496\n\tIO_AA18: inout bit; --  PAD482\n\tIO_AA20: inout bit; --  PAD312\n\tIO_AA21: inout bit; --  PAD305\n\tIO_AA22: inout bit; --  PAD308\n\tIO_AA23: inout bit; --  PAD309\n\tIO_AA25: inout bit; --  PAD262\n\tIO_AA26: inout bit; --  PAD253\n\tIO_AA27: inout bit; --  PAD260\n\tIO_AA28: inout bit; --  PAD257\n\tIO_AA30: inout bit; --  PAD267\n\tIO_AB7: inout bit; --  PAD400\n\tIO_AB8: inout bit; --  PAD405\n\tIO_AB9: inout bit; --  PAD406\n\tIO_AB10: inout bit; --  PAD414\n\tIO_AB12: inout bit; --  PAD403\n\tIO_AB13: inout bit; --  PAD413\n\tIO_AB14: inout bit; --  PAD500\n\tIO_AB15: inout bit; --  PAD491\n\tIO_AB17: inout bit; --  PAD486\n\tIO_AB18: inout bit; --  PAD483\n\tIO_AB19: inout bit; --  PAD484\n\tIO_AB20: inout bit; --  PAD313\n\tIO_AB22: inout bit; --  PAD306\n\tIO_AB23: inout bit; --  PAD307\n\tIO_AB24: inout bit; --  PAD314\n\tIO_AB25: inout bit; --  PAD263\n\tIO_AB27: inout bit; --  PAD274\n\tIO_AB28: inout bit; --  PAD261\n\tIO_AB29: inout bit; --  PAD270\n\tIO_AB30: inout bit; --  PAD271\n\tIO_AC1: inout bit; --  PAD355\n\tIO_AC2: inout bit; --  PAD354\n\tIO_AC4: inout bit; --  PAD359\n\tIO_AC5: inout bit; --  PAD358\n\tIO_AC6: inout bit; --  PAD351\n\tIO_AC7: inout bit; --  PAD362\n\tIO_AC9: inout bit; --  PAD407\n\tIO_AC10: inout bit; --  PAD415\n\tIO_AC11: inout bit; --  PAD419\n\tIO_AC12: inout bit; --  PAD418\n\tIO_AC14: inout bit; --  PAD494\n\tIO_AC15: inout bit; --  PAD493\n\tIO_AC16: inout bit; --  PAD492\n\tIO_AC17: inout bit; --  PAD487\n\tIO_AC19: inout bit; --  PAD485\n\tIO_AC20: inout bit; --  PAD310\n\tIO_AC21: inout bit; --  PAD311\n\tIO_AC22: inout bit; --  PAD316\n\tIO_AC24: inout bit; --  PAD318\n\tIO_AC25: inout bit; --  PAD315\n\tIO_AC26: inout bit; --  PAD288\n\tIO_AC27: inout bit; --  PAD275\n\tIO_AC29: inout bit; --  PAD264\n\tIO_AC30: inout bit; --  PAD265\n\tIO_AD1: inout bit; --  PAD357\n\tIO_AD2: inout bit; --  PAD356\n\tIO_AD3: inout bit; --  PAD353\n\tIO_AD4: inout bit; --  PAD352\n\tIO_AD6: inout bit; --  PAD360\n\tIO_AD7: inout bit; --  PAD363\n\tIO_AD8: inout bit; --  PAD416\n\tIO_AD9: inout bit; --  PAD420\n\tIO_AD11: inout bit; --  PAD425\n\tIO_AD12: inout bit; --  PAD424\n\tIO_AD13: inout bit; --  PAD450\n\tIO_AD14: inout bit; --  PAD495\n\tIO_AD16: inout bit; --  PAD479\n\tIO_AD17: inout bit; --  PAD478\n\tIO_AD18: inout bit; --  PAD476\n\tIO_AD19: inout bit; --  PAD470\n\tIO_AD21: inout bit; --  PAD320\n\tIO_AD22: inout bit; --  PAD317\n\tIO_AD23: inout bit; --  PAD324\n\tIO_AD24: inout bit; --  PAD319\n\tIO_AD26: inout bit; --  PAD289\n\tIO_AD27: inout bit; --  PAD272\n\tIO_AD28: inout bit; --  PAD273\n\tIO_AD29: inout bit; --  PAD268\n\tIO_AE1: inout bit; --  PAD366\n\tIO_AE3: inout bit; --  PAD371\n\tIO_AE4: inout bit; --  PAD370\n\tIO_AE5: inout bit; --  PAD372\n\tIO_AE6: inout bit; --  PAD361\n\tIO_AE8: inout bit; --  PAD417\n\tIO_AE9: inout bit; --  PAD421\n\tIO_AE10: inout bit; --  PAD428\n\tIO_AE11: inout bit; --  PAD422\n\tIO_AE13: inout bit; --  PAD438\n\tIO_AE14: inout bit; --  PAD489\n\tIO_AE15: inout bit; --  PAD488\n\tIO_AE16: inout bit; --  PAD462\n\tIO_AE18: inout bit; --  PAD477\n\tIO_AE19: inout bit; --  PAD471\n\tIO_AE20: inout bit; --  PAD350\n\tIO_AE21: inout bit; --  PAD321\n\tIO_AE23: inout bit; --  PAD322\n\tIO_AE24: inout bit; --  PAD325\n\tIO_AE25: inout bit; --  PAD332\n\tIO_AE26: inout bit; --  PAD300\n\tIO_AE28: inout bit; --  PAD278\n\tIO_AE29: inout bit; --  PAD269\n\tIO_AE30: inout bit; --  PAD282\n\tIO_AF1: inout bit; --  PAD367\n\tIO_AF2: inout bit; --  PAD365\n\tIO_AF3: inout bit; --  PAD364\n\tIO_AF5: inout bit; --  PAD373\n\tIO_AF6: inout bit; --  PAD374\n\tIO_AF7: inout bit; --  PAD390\n\tIO_AF8: inout bit; --  PAD388\n\tIO_AF10: inout bit; --  PAD429\n\tIO_AF11: inout bit; --  PAD423\n\tIO_AF12: inout bit; --  PAD446\n\tIO_AF13: inout bit; --  PAD439\n\tIO_AF15: inout bit; --  PAD458\n\tIO_AF16: inout bit; --  PAD463\n\tIO_AF17: inout bit; --  PAD474\n\tIO_AF18: inout bit; --  PAD472\n\tIO_AF20: inout bit; --  PAD338\n\tIO_AF21: inout bit; --  PAD339\n\tIO_AF22: inout bit; --  PAD326\n\tIO_AF23: inout bit; --  PAD323\n\tIO_AF25: inout bit; --  PAD333\n\tIO_AF26: inout bit; --  PAD296\n\tIO_AF27: inout bit; --  PAD297\n\tIO_AF28: inout bit; --  PAD279\n\tIO_AF30: inout bit; --  PAD283\n\tIO_AG2: inout bit; --  PAD380\n\tIO_AG3: inout bit; --  PAD369\n\tIO_AG4: inout bit; --  PAD368\n\tIO_AG5: inout bit; --  PAD375\n\tIO_AG7: inout bit; --  PAD391\n\tIO_AG8: inout bit; --  PAD389\n\tIO_AG9: inout bit; --  PAD432\n\tIO_AG10: inout bit; --  PAD426\n\tIO_AG12: inout bit; --  PAD447\n\tIO_AG13: inout bit; --  PAD448\n\tIO_AG14: inout bit; --  PAD459\n\tIO_AG15: inout bit; --  PAD454\n\tIO_AG17: inout bit; --  PAD475\n\tIO_AG18: inout bit; --  PAD473\n\tIO_AG19: inout bit; --  PAD466\n\tIO_AG20: inout bit; --  PAD344\n\tIO_AG22: inout bit; --  PAD340\n\tIO_AG23: inout bit; --  PAD327\n\tIO_AG24: inout bit; --  PAD328\n\tIO_AG25: inout bit; --  PAD336\n\tIO_AG27: inout bit; --  PAD292\n\tIO_AG28: inout bit; --  PAD293\n\tIO_AG29: inout bit; --  PAD276\n\tIO_AG30: inout bit; --  PAD286\n\tIO_AH1: inout bit; --  PAD381\n\tIO_AH2: inout bit; --  PAD382\n\tIO_AH4: inout bit; --  PAD376\n\tIO_AH5: inout bit; --  PAD379\n\tIO_AH6: inout bit; --  PAD378\n\tIO_AH7: inout bit; --  PAD392\n\tIO_AH9: inout bit; --  PAD433\n\tIO_AH10: inout bit; --  PAD427\n\tIO_AH11: inout bit; --  PAD436\n\tIO_AH12: inout bit; --  PAD449\n\tIO_AH14: inout bit; --  PAD442\n\tIO_AH15: inout bit; --  PAD455\n\tIO_AH16: inout bit; --  PAD456\n\tIO_AH17: inout bit; --  PAD460\n\tIO_AH19: inout bit; --  PAD467\n\tIO_AH20: inout bit; --  PAD345\n\tIO_AH21: inout bit; --  PAD346\n\tIO_AH22: inout bit; --  PAD341\n\tIO_AH24: inout bit; --  PAD329\n\tIO_AH25: inout bit; --  PAD337\n\tIO_AH26: inout bit; --  PAD294\n\tIO_AH27: inout bit; --  PAD295\n\tIO_AH29: inout bit; --  PAD277\n\tIO_AH30: inout bit; --  PAD287\n\tIO_AJ1: inout bit; --  PAD384\n\tIO_AJ2: inout bit; --  PAD383\n\tIO_AJ3: inout bit; --  PAD386\n\tIO_AJ4: inout bit; --  PAD377\n\tIO_AJ6: inout bit; --  PAD394\n\tIO_AJ7: inout bit; --  PAD393\n\tIO_AJ8: inout bit; --  PAD396\n\tIO_AJ9: inout bit; --  PAD430\n\tIO_AJ11: inout bit; --  PAD437\n\tIO_AJ12: inout bit; --  PAD445\n\tIO_AJ13: inout bit; --  PAD444\n\tIO_AJ14: inout bit; --  PAD443\n\tIO_AJ16: inout bit; --  PAD457\n\tIO_AJ17: inout bit; --  PAD461\n\tIO_AJ18: inout bit; --  PAD468\n\tIO_AJ19: inout bit; --  PAD464\n\tIO_AJ21: inout bit; --  PAD347\n\tIO_AJ22: inout bit; --  PAD342\n\tIO_AJ23: inout bit; --  PAD343\n\tIO_AJ24: inout bit; --  PAD330\n\tIO_AJ26: inout bit; --  PAD298\n\tIO_AJ27: inout bit; --  PAD290\n\tIO_AJ28: inout bit; --  PAD284\n\tIO_AJ29: inout bit; --  PAD285\n\tIO_AK1: inout bit; --  PAD385\n\tIO_AK3: inout bit; --  PAD387\n\tIO_AK4: inout bit; --  PAD399\n\tIO_AK5: inout bit; --  PAD398\n\tIO_AK6: inout bit; --  PAD395\n\tIO_AK8: inout bit; --  PAD397\n\tIO_AK9: inout bit; --  PAD431\n\tIO_AK10: inout bit; --  PAD435\n\tIO_AK11: inout bit; --  PAD434\n\tIO_AK13: inout bit; --  PAD441\n\tIO_AK14: inout bit; --  PAD440\n\tIO_AK15: inout bit; --  PAD453\n\tIO_AK16: inout bit; --  PAD452\n\tIO_AK18: inout bit; --  PAD469\n\tIO_AK19: inout bit; --  PAD465\n\tIO_AK20: inout bit; --  PAD348\n\tIO_AK21: inout bit; --  PAD349\n\tIO_AK23: inout bit; --  PAD334\n\tIO_AK24: inout bit; --  PAD335\n\tIO_AK25: inout bit; --  PAD331\n\tIO_AK26: inout bit; --  PAD299\n\tIO_AK28: inout bit; --  PAD291\n\tIO_AK29: inout bit; --  PAD280\n\tIO_AK30: inout bit --  PAD281\n); --end port list\n\n-- Use Statements\n\nuse STD_1149_1_2001.all;\nuse STD_1149_6_2003.all;\n\n-- Component Conformance Statement(s)\n\nattribute COMPONENT_CONFORMANCE of XC7K325T_FFG900 : entity is\n\t\"STD_1149_1_2001\";\n\n-- Device Package Pin Mappings\n\nattribute PIN_MAP of XC7K325T_FFG900 : entity is PHYSICAL_PIN_MAP;\n\nconstant FFG900: PIN_MAP_STRING:=\n\t\"CCLK_B10:B10,\" &\n\t\"CFGBVS_L10:L10,\" &\n\t\"DONE_M10:M10,\" &\n\t\"GND:(A1,A2,A5,A6,A9,A14,A24,B4,B8,B9,\" &\n\t\t\"B11,B21,C1,C2,C6,C9,C18,C28,D4,D8,\" &\n\t\t\"D9,D15,D25,E1,E2,E6,E9,E12,E22,F4,\" &\n\t\t\"F8,F9,F19,F29,G1,G2,G6,G9,G16,G26,\" &\n\t\t\"H4,H8,H9,H13,H23,J1,J2,J6,J9,J10,\" &\n\t\t\"J20,J30,K4,K8,K9,K17,K27,L1,L2,L6,\" &\n\t\t\"L9,L14,L24,M4,M8,M9,M12,M14,M16,M18,\" &\n\t\t\"M21,N1,N2,N6,N9,N11,N13,N15,N17,N28,\" &\n\t\t\"P4,P8,P9,P10,P12,P16,P18,P25,R1,R2,\" &\n\t\t\"R6,R9,R11,R13,R17,R22,T4,T8,T10,T12,\" &\n\t\t\"T16,T18,T19,T29,U1,U2,U6,U9,U11,U13,\" &\n\t\t\"U17,U26,V4,V8,V9,V10,V12,V14,V16,V18,\" &\n\t\t\"V23,W1,W2,W6,W9,W11,W13,W15,W17,W20,\" &\n\t\t\"W30,Y3,Y4,Y7,Y8,Y9,Y17,Y27,AA1,AA2,\" &\n\t\t\"AA5,AA6,AA7,AA14,AA24,AB3,AB4,AB11,AB21,AC8,\" &\n\t\t\"AC18,AC28,AD5,AD15,AD25,AE2,AE12,AE22,AF9,AF19,\" &\n\t\t\"AF29,AG6,AG16,AG26,AH3,AH13,AH23,AJ10,AJ20,AJ30,\" &\n\t\t\"AK7,AK17,AK27),\" &\n\t\"GNDADC_0:P14,\" &\n\t\"INIT_B_A10:A10,\" &\n\t\"M0_AB5:AB5,\" &\n\t\"M1_AB2:AB2,\" &\n\t\"M2_AB1:AB1,\" &\n\t\"MGTAVCC:(B7,D7,F7,H7,K7,M7,P7),\" &\n\t\"MGTAVTT:(B3,C5,D3,E5,F3,G5,H3,J5,K3,L5,\" &\n\t\t\"M3,N5,P3,R5,T3,U5,V3,W5),\" &\n\t\"MGTAVTTRCAL_115:W7,\" &\n\t\"MGTREFCLK0N_115:R7,\" &\n\t\"MGTREFCLK0N_116:L7,\" &\n\t\"MGTREFCLK0N_117:G7,\" &\n\t\"MGTREFCLK0N_118:C7,\" &\n\t\"MGTREFCLK0P_115:R8,\" &\n\t\"MGTREFCLK0P_116:L8,\" &\n\t\"MGTREFCLK0P_117:G8,\" &\n\t\"MGTREFCLK0P_118:C8,\" &\n\t\"MGTREFCLK1N_115:U7,\" &\n\t\"MGTREFCLK1N_116:N7,\" &\n\t\"MGTREFCLK1N_117:J7,\" &\n\t\"MGTREFCLK1N_118:E7,\" &\n\t\"MGTREFCLK1P_115:U8,\" &\n\t\"MGTREFCLK1P_116:N8,\" &\n\t\"MGTREFCLK1P_117:J8,\" &\n\t\"MGTREFCLK1P_118:E8,\" &\n\t\"MGTRREF_115:W8,\" &\n\t\"MGTVCCAUX:(T7,V7),\" &\n\t\"MGTXRXN0_115:AA3,\" &\n\t\"MGTXRXN0_116:T5,\" &\n\t\"MGTXRXN0_117:K5,\" &\n\t\"MGTXRXN0_118:E3,\" &\n\t\"MGTXRXN1_115:Y5,\" &\n\t\"MGTXRXN1_116:R3,\" &\n\t\"MGTXRXN1_117:H5,\" &\n\t\"MGTXRXN1_118:D5,\" &\n\t\"MGTXRXN2_115:W3,\" &\n\t\"MGTXRXN2_116:P5,\" &\n\t\"MGTXRXN2_117:G3,\" &\n\t\"MGTXRXN2_118:B5,\" &\n\t\"MGTXRXN3_115:V5,\" &\n\t\"MGTXRXN3_116:M5,\" &\n\t\"MGTXRXN3_117:F5,\" &\n\t\"MGTXRXN3_118:A7,\" &\n\t\"MGTXRXP0_115:AA4,\" &\n\t\"MGTXRXP0_116:T6,\" &\n\t\"MGTXRXP0_117:K6,\" &\n\t\"MGTXRXP0_118:E4,\" &\n\t\"MGTXRXP1_115:Y6,\" &\n\t\"MGTXRXP1_116:R4,\" &\n\t\"MGTXRXP1_117:H6,\" &\n\t\"MGTXRXP1_118:D6,\" &\n\t\"MGTXRXP2_115:W4,\" &\n\t\"MGTXRXP2_116:P6,\" &\n\t\"MGTXRXP2_117:G4,\" &\n\t\"MGTXRXP2_118:B6,\" &\n\t\"MGTXRXP3_115:V6,\" &\n\t\"MGTXRXP3_116:M6,\" &\n\t\"MGTXRXP3_117:F6,\" &\n\t\"MGTXRXP3_118:A8,\" &\n\t\"MGTXTXN0_115:Y1,\" &\n\t\"MGTXTXN0_116:P1,\" &\n\t\"MGTXTXN0_117:K1,\" &\n\t\"MGTXTXN0_118:D1,\" &\n\t\"MGTXTXN1_115:V1,\" &\n\t\"MGTXTXN1_116:N3,\" &\n\t\"MGTXTXN1_117:J3,\" &\n\t\"MGTXTXN1_118:C3,\" &\n\t\"MGTXTXN2_115:U3,\" &\n\t\"MGTXTXN2_116:M1,\" &\n\t\"MGTXTXN2_117:H1,\" &\n\t\"MGTXTXN2_118:B1,\" &\n\t\"MGTXTXN3_115:T1,\" &\n\t\"MGTXTXN3_116:L3,\" &\n\t\"MGTXTXN3_117:F1,\" &\n\t\"MGTXTXN3_118:A3,\" &\n\t\"MGTXTXP0_115:Y2,\" &\n\t\"MGTXTXP0_116:P2,\" &\n\t\"MGTXTXP0_117:K2,\" &\n\t\"MGTXTXP0_118:D2,\" &\n\t\"MGTXTXP1_115:V2,\" &\n\t\"MGTXTXP1_116:N4,\" &\n\t\"MGTXTXP1_117:J4,\" &\n\t\"MGTXTXP1_118:C4,\" &\n\t\"MGTXTXP2_115:U4,\" &\n\t\"MGTXTXP2_116:M2,\" &\n\t\"MGTXTXP2_117:H2,\" &\n\t\"MGTXTXP2_118:B2,\" &\n\t\"MGTXTXP3_115:T2,\" &\n\t\"MGTXTXP3_116:L4,\" &\n\t\"MGTXTXP3_117:F2,\" &\n\t\"MGTXTXP3_118:A4,\" &\n\t\"PROGRAM_B:K10,\" &\n\t\"TCK:E10,\" &\n\t\"TDI:H10,\" &\n\t\"TDN_U14:U14,\" &\n\t\"TDO:G10,\" &\n\t\"TDP_U15:U15,\" &\n\t\"TMS:F10,\" &\n\t\"VCCADC_0:P15,\" &\n\t\"VCCAUX:(P13,T13,V11,V13,V15,W10,W12,W14),\" &\n\t\"VCCBATT_0:C10,\" &\n\t\"VCCBRAM:(N16,R16,U16,W16),\" &\n\t\"VCCINT:(M11,M13,M15,M17,N10,N12,N14,N18,P11,P17,\" &\n\t\t\"R10,R12,R18,T11,T17,U10,U12,U18,V17,W18),\" &\n\t\"VCCO_0:(T9,AB6),\" &\n\t\"VCCO_12:(Y22,AC23,AD20,AF24,AG21,AK22),\" &\n\t\"VCCO_13:(AA29,AB26,AD30,AE27,AH28,AJ25),\" &\n\t\"VCCO_14:(P30,R27,T24,U21,V28,W25),\" &\n\t\"VCCO_15:(J25,K22,L29,M26,N23,P20),\" &\n\t\"VCCO_16:(A29,B26,C23,D30,E27,F24,H28),\" &\n\t\"VCCO_17:(A19,B16,D20,E17,G21,H18,L19),\" &\n\t\"VCCO_18:(C13,D10,F14,G11,J15,K12),\" &\n\t\"VCCO_32:(AA19,AB16,AE17,AF14,AH18,AJ15),\" &\n\t\"VCCO_33:(Y12,AA9,AC13,AD10,AG11,AK12),\" &\n\t\"VCCO_34:(AC3,AE7,AF4,AG1,AH8,AJ5,AK2),\" &\n\t\"VN_T14:T14,\" &\n\t\"VP_R15:R15,\" &\n\t\"VREFN_R14:R14,\" &\n\t\"VREFP_T15:T15,\" &\n\t\"IO_A11:A11,\" &\n\t\"IO_A12:A12,\" &\n\t\"IO_A13:A13,\" &\n\t\"IO_A15:A15,\" &\n\t\"IO_A16:A16,\" &\n\t\"IO_A17:A17,\" &\n\t\"IO_A18:A18,\" &\n\t\"IO_A20:A20,\" &\n\t\"IO_A21:A21,\" &\n\t\"IO_A22:A22,\" &\n\t\"IO_A23:A23,\" &\n\t\"IO_A25:A25,\" &\n\t\"IO_A26:A26,\" &\n\t\"IO_A27:A27,\" &\n\t\"IO_A28:A28,\" &\n\t\"IO_A30:A30,\" &\n\t\"IO_B12:B12,\" &\n\t\"IO_B13:B13,\" &\n\t\"IO_B14:B14,\" &\n\t\"IO_B15:B15,\" &\n\t\"IO_B17:B17,\" &\n\t\"IO_B18:B18,\" &\n\t\"IO_B19:B19,\" &\n\t\"IO_B20:B20,\" &\n\t\"IO_B22:B22,\" &\n\t\"IO_B23:B23,\" &\n\t\"IO_B24:B24,\" &\n\t\"IO_B25:B25,\" &\n\t\"IO_B27:B27,\" &\n\t\"IO_B28:B28,\" &\n\t\"IO_B29:B29,\" &\n\t\"IO_B30:B30,\" &\n\t\"IO_C11:C11,\" &\n\t\"IO_C12:C12,\" &\n\t\"IO_C14:C14,\" &\n\t\"IO_C15:C15,\" &\n\t\"IO_C16:C16,\" &\n\t\"IO_C17:C17,\" &\n\t\"IO_C19:C19,\" &\n\t\"IO_C20:C20,\" &\n\t\"IO_C21:C21,\" &\n\t\"IO_C22:C22,\" &\n\t\"IO_C24:C24,\" &\n\t\"IO_C25:C25,\" &\n\t\"IO_C26:C26,\" &\n\t\"IO_C27:C27,\" &\n\t\"IO_C29:C29,\" &\n\t\"IO_C30:C30,\" &\n\t\"IO_D11:D11,\" &\n\t\"IO_D12:D12,\" &\n\t\"IO_D13:D13,\" &\n\t\"IO_D14:D14,\" &\n\t\"IO_D16:D16,\" &\n\t\"IO_D17:D17,\" &\n\t\"IO_D18:D18,\" &\n\t\"IO_D19:D19,\" &\n\t\"IO_D21:D21,\" &\n\t\"IO_D22:D22,\" &\n\t\"IO_D23:D23,\" &\n\t\"IO_D24:D24,\" &\n\t\"IO_D26:D26,\" &\n\t\"IO_D27:D27,\" &\n\t\"IO_D28:D28,\" &\n\t\"IO_D29:D29,\" &\n\t\"IO_E11:E11,\" &\n\t\"IO_E13:E13,\" &\n\t\"IO_E14:E14,\" &\n\t\"IO_E15:E15,\" &\n\t\"IO_E16:E16,\" &\n\t\"IO_E18:E18,\" &\n\t\"IO_E19:E19,\" &\n\t\"IO_E20:E20,\" &\n\t\"IO_E21:E21,\" &\n\t\"IO_E23:E23,\" &\n\t\"IO_E24:E24,\" &\n\t\"IO_E25:E25,\" &\n\t\"IO_E26:E26,\" &\n\t\"IO_E28:E28,\" &\n\t\"IO_E29:E29,\" &\n\t\"IO_E30:E30,\" &\n\t\"IO_F11:F11,\" &\n\t\"IO_F12:F12,\" &\n\t\"IO_F13:F13,\" &\n\t\"IO_F15:F15,\" &\n\t\"IO_F16:F16,\" &\n\t\"IO_F17:F17,\" &\n\t\"IO_F18:F18,\" &\n\t\"IO_F20:F20,\" &\n\t\"IO_F21:F21,\" &\n\t\"IO_F22:F22,\" &\n\t\"IO_F23:F23,\" &\n\t\"IO_F25:F25,\" &\n\t\"IO_F26:F26,\" &\n\t\"IO_F27:F27,\" &\n\t\"IO_F28:F28,\" &\n\t\"IO_F30:F30,\" &\n\t\"IO_G12:G12,\" &\n\t\"IO_G13:G13,\" &\n\t\"IO_G14:G14,\" &\n\t\"IO_G15:G15,\" &\n\t\"IO_G17:G17,\" &\n\t\"IO_G18:G18,\" &\n\t\"IO_G19:G19,\" &\n\t\"IO_G20:G20,\" &\n\t\"IO_G22:G22,\" &\n\t\"IO_G23:G23,\" &\n\t\"IO_G24:G24,\" &\n\t\"IO_G25:G25,\" &\n\t\"IO_G27:G27,\" &\n\t\"IO_G28:G28,\" &\n\t\"IO_G29:G29,\" &\n\t\"IO_G30:G30,\" &\n\t\"IO_H11:H11,\" &\n\t\"IO_H12:H12,\" &\n\t\"IO_H14:H14,\" &\n\t\"IO_H15:H15,\" &\n\t\"IO_H16:H16,\" &\n\t\"IO_H17:H17,\" &\n\t\"IO_H19:H19,\" &\n\t\"IO_H20:H20,\" &\n\t\"IO_H21:H21,\" &\n\t\"IO_H22:H22,\" &\n\t\"IO_H24:H24,\" &\n\t\"IO_H25:H25,\" &\n\t\"IO_H26:H26,\" &\n\t\"IO_H27:H27,\" &\n\t\"IO_H29:H29,\" &\n\t\"IO_H30:H30,\" &\n\t\"IO_J11:J11,\" &\n\t\"IO_J12:J12,\" &\n\t\"IO_J13:J13,\" &\n\t\"IO_J14:J14,\" &\n\t\"IO_J16:J16,\" &\n\t\"IO_J17:J17,\" &\n\t\"IO_J18:J18,\" &\n\t\"IO_J19:J19,\" &\n\t\"IO_J21:J21,\" &\n\t\"IO_J22:J22,\" &\n\t\"IO_J23:J23,\" &\n\t\"IO_J24:J24,\" &\n\t\"IO_J26:J26,\" &\n\t\"IO_J27:J27,\" &\n\t\"IO_J28:J28,\" &\n\t\"IO_J29:J29,\" &\n\t\"IO_K11:K11,\" &\n\t\"IO_K13:K13,\" &\n\t\"IO_K14:K14,\" &\n\t\"IO_K15:K15,\" &\n\t\"IO_K16:K16,\" &\n\t\"IO_K18:K18,\" &\n\t\"IO_K19:K19,\" &\n\t\"IO_K20:K20,\" &\n\t\"IO_K21:K21,\" &\n\t\"IO_K23:K23,\" &\n\t\"IO_K24:K24,\" &\n\t\"IO_K25:K25,\" &\n\t\"IO_K26:K26,\" &\n\t\"IO_K28:K28,\" &\n\t\"IO_K29:K29,\" &\n\t\"IO_K30:K30,\" &\n\t\"IO_L11:L11,\" &\n\t\"IO_L12:L12,\" &\n\t\"IO_L13:L13,\" &\n\t\"IO_L15:L15,\" &\n\t\"IO_L16:L16,\" &\n\t\"IO_L17:L17,\" &\n\t\"IO_L18:L18,\" &\n\t\"IO_L20:L20,\" &\n\t\"IO_L21:L21,\" &\n\t\"IO_L22:L22,\" &\n\t\"IO_L23:L23,\" &\n\t\"IO_L25:L25,\" &\n\t\"IO_L26:L26,\" &\n\t\"IO_L27:L27,\" &\n\t\"IO_L28:L28,\" &\n\t\"IO_L30:L30,\" &\n\t\"IO_M19:M19,\" &\n\t\"IO_M20:M20,\" &\n\t\"IO_M22:M22,\" &\n\t\"IO_M23:M23,\" &\n\t\"IO_M24:M24,\" &\n\t\"IO_M25:M25,\" &\n\t\"IO_M27:M27,\" &\n\t\"IO_M28:M28,\" &\n\t\"IO_M29:M29,\" &\n\t\"IO_M30:M30,\" &\n\t\"IO_N19:N19,\" &\n\t\"IO_N20:N20,\" &\n\t\"IO_N21:N21,\" &\n\t\"IO_N22:N22,\" &\n\t\"IO_N24:N24,\" &\n\t\"IO_N25:N25,\" &\n\t\"IO_N26:N26,\" &\n\t\"IO_N27:N27,\" &\n\t\"IO_N29:N29,\" &\n\t\"IO_N30:N30,\" &\n\t\"IO_P19:P19,\" &\n\t\"IO_P21:P21,\" &\n\t\"IO_P22:P22,\" &\n\t\"IO_P23:P23,\" &\n\t\"IO_P24:P24,\" &\n\t\"IO_P26:P26,\" &\n\t\"IO_P27:P27,\" &\n\t\"IO_P28:P28,\" &\n\t\"IO_P29:P29,\" &\n\t\"IO_R19:R19,\" &\n\t\"IO_R20:R20,\" &\n\t\"IO_R21:R21,\" &\n\t\"IO_R23:R23,\" &\n\t\"IO_R24:R24,\" &\n\t\"IO_R25:R25,\" &\n\t\"IO_R26:R26,\" &\n\t\"IO_R28:R28,\" &\n\t\"IO_R29:R29,\" &\n\t\"IO_R30:R30,\" &\n\t\"IO_T20:T20,\" &\n\t\"IO_T21:T21,\" &\n\t\"IO_T22:T22,\" &\n\t\"IO_T23:T23,\" &\n\t\"IO_T25:T25,\" &\n\t\"IO_T26:T26,\" &\n\t\"IO_T27:T27,\" &\n\t\"IO_T28:T28,\" &\n\t\"IO_T30:T30,\" &\n\t\"IO_U19:U19,\" &\n\t\"IO_U20:U20,\" &\n\t\"IO_U22:U22,\" &\n\t\"IO_U23:U23,\" &\n\t\"IO_U24:U24,\" &\n\t\"IO_U25:U25,\" &\n\t\"IO_U27:U27,\" &\n\t\"IO_U28:U28,\" &\n\t\"IO_U29:U29,\" &\n\t\"IO_U30:U30,\" &\n\t\"IO_V19:V19,\" &\n\t\"IO_V20:V20,\" &\n\t\"IO_V21:V21,\" &\n\t\"IO_V22:V22,\" &\n\t\"IO_V24:V24,\" &\n\t\"IO_V25:V25,\" &\n\t\"IO_V26:V26,\" &\n\t\"IO_V27:V27,\" &\n\t\"IO_V29:V29,\" &\n\t\"IO_V30:V30,\" &\n\t\"IO_W19:W19,\" &\n\t\"IO_W21:W21,\" &\n\t\"IO_W22:W22,\" &\n\t\"IO_W23:W23,\" &\n\t\"IO_W24:W24,\" &\n\t\"IO_W26:W26,\" &\n\t\"IO_W27:W27,\" &\n\t\"IO_W28:W28,\" &\n\t\"IO_W29:W29,\" &\n\t\"IO_Y10:Y10,\" &\n\t\"IO_Y11:Y11,\" &\n\t\"IO_Y13:Y13,\" &\n\t\"IO_Y14:Y14,\" &\n\t\"IO_Y15:Y15,\" &\n\t\"IO_Y16:Y16,\" &\n\t\"IO_Y18:Y18,\" &\n\t\"IO_Y19:Y19,\" &\n\t\"IO_Y20:Y20,\" &\n\t\"IO_Y21:Y21,\" &\n\t\"IO_Y23:Y23,\" &\n\t\"IO_Y24:Y24,\" &\n\t\"IO_Y25:Y25,\" &\n\t\"IO_Y26:Y26,\" &\n\t\"IO_Y28:Y28,\" &\n\t\"IO_Y29:Y29,\" &\n\t\"IO_Y30:Y30,\" &\n\t\"IO_AA8:AA8,\" &\n\t\"IO_AA10:AA10,\" &\n\t\"IO_AA11:AA11,\" &\n\t\"IO_AA12:AA12,\" &\n\t\"IO_AA13:AA13,\" &\n\t\"IO_AA15:AA15,\" &\n\t\"IO_AA16:AA16,\" &\n\t\"IO_AA17:AA17,\" &\n\t\"IO_AA18:AA18,\" &\n\t\"IO_AA20:AA20,\" &\n\t\"IO_AA21:AA21,\" &\n\t\"IO_AA22:AA22,\" &\n\t\"IO_AA23:AA23,\" &\n\t\"IO_AA25:AA25,\" &\n\t\"IO_AA26:AA26,\" &\n\t\"IO_AA27:AA27,\" &\n\t\"IO_AA28:AA28,\" &\n\t\"IO_AA30:AA30,\" &\n\t\"IO_AB7:AB7,\" &\n\t\"IO_AB8:AB8,\" &\n\t\"IO_AB9:AB9,\" &\n\t\"IO_AB10:AB10,\" &\n\t\"IO_AB12:AB12,\" &\n\t\"IO_AB13:AB13,\" &\n\t\"IO_AB14:AB14,\" &\n\t\"IO_AB15:AB15,\" &\n\t\"IO_AB17:AB17,\" &\n\t\"IO_AB18:AB18,\" &\n\t\"IO_AB19:AB19,\" &\n\t\"IO_AB20:AB20,\" &\n\t\"IO_AB22:AB22,\" &\n\t\"IO_AB23:AB23,\" &\n\t\"IO_AB24:AB24,\" &\n\t\"IO_AB25:AB25,\" &\n\t\"IO_AB27:AB27,\" &\n\t\"IO_AB28:AB28,\" &\n\t\"IO_AB29:AB29,\" &\n\t\"IO_AB30:AB30,\" &\n\t\"IO_AC1:AC1,\" &\n\t\"IO_AC2:AC2,\" &\n\t\"IO_AC4:AC4,\" &\n\t\"IO_AC5:AC5,\" &\n\t\"IO_AC6:AC6,\" &\n\t\"IO_AC7:AC7,\" &\n\t\"IO_AC9:AC9,\" &\n\t\"IO_AC10:AC10,\" &\n\t\"IO_AC11:AC11,\" &\n\t\"IO_AC12:AC12,\" &\n\t\"IO_AC14:AC14,\" &\n\t\"IO_AC15:AC15,\" &\n\t\"IO_AC16:AC16,\" &\n\t\"IO_AC17:AC17,\" &\n\t\"IO_AC19:AC19,\" &\n\t\"IO_AC20:AC20,\" &\n\t\"IO_AC21:AC21,\" &\n\t\"IO_AC22:AC22,\" &\n\t\"IO_AC24:AC24,\" &\n\t\"IO_AC25:AC25,\" &\n\t\"IO_AC26:AC26,\" &\n\t\"IO_AC27:AC27,\" &\n\t\"IO_AC29:AC29,\" &\n\t\"IO_AC30:AC30,\" &\n\t\"IO_AD1:AD1,\" &\n\t\"IO_AD2:AD2,\" &\n\t\"IO_AD3:AD3,\" &\n\t\"IO_AD4:AD4,\" &\n\t\"IO_AD6:AD6,\" &\n\t\"IO_AD7:AD7,\" &\n\t\"IO_AD8:AD8,\" &\n\t\"IO_AD9:AD9,\" &\n\t\"IO_AD11:AD11,\" &\n\t\"IO_AD12:AD12,\" &\n\t\"IO_AD13:AD13,\" &\n\t\"IO_AD14:AD14,\" &\n\t\"IO_AD16:AD16,\" &\n\t\"IO_AD17:AD17,\" &\n\t\"IO_AD18:AD18,\" &\n\t\"IO_AD19:AD19,\" &\n\t\"IO_AD21:AD21,\" &\n\t\"IO_AD22:AD22,\" &\n\t\"IO_AD23:AD23,\" &\n\t\"IO_AD24:AD24,\" &\n\t\"IO_AD26:AD26,\" &\n\t\"IO_AD27:AD27,\" &\n\t\"IO_AD28:AD28,\" &\n\t\"IO_AD29:AD29,\" &\n\t\"IO_AE1:AE1,\" &\n\t\"IO_AE3:AE3,\" &\n\t\"IO_AE4:AE4,\" &\n\t\"IO_AE5:AE5,\" &\n\t\"IO_AE6:AE6,\" &\n\t\"IO_AE8:AE8,\" &\n\t\"IO_AE9:AE9,\" &\n\t\"IO_AE10:AE10,\" &\n\t\"IO_AE11:AE11,\" &\n\t\"IO_AE13:AE13,\" &\n\t\"IO_AE14:AE14,\" &\n\t\"IO_AE15:AE15,\" &\n\t\"IO_AE16:AE16,\" &\n\t\"IO_AE18:AE18,\" &\n\t\"IO_AE19:AE19,\" &\n\t\"IO_AE20:AE20,\" &\n\t\"IO_AE21:AE21,\" &\n\t\"IO_AE23:AE23,\" &\n\t\"IO_AE24:AE24,\" &\n\t\"IO_AE25:AE25,\" &\n\t\"IO_AE26:AE26,\" &\n\t\"IO_AE28:AE28,\" &\n\t\"IO_AE29:AE29,\" &\n\t\"IO_AE30:AE30,\" &\n\t\"IO_AF1:AF1,\" &\n\t\"IO_AF2:AF2,\" &\n\t\"IO_AF3:AF3,\" &\n\t\"IO_AF5:AF5,\" &\n\t\"IO_AF6:AF6,\" &\n\t\"IO_AF7:AF7,\" &\n\t\"IO_AF8:AF8,\" &\n\t\"IO_AF10:AF10,\" &\n\t\"IO_AF11:AF11,\" &\n\t\"IO_AF12:AF12,\" &\n\t\"IO_AF13:AF13,\" &\n\t\"IO_AF15:AF15,\" &\n\t\"IO_AF16:AF16,\" &\n\t\"IO_AF17:AF17,\" &\n\t\"IO_AF18:AF18,\" &\n\t\"IO_AF20:AF20,\" &\n\t\"IO_AF21:AF21,\" &\n\t\"IO_AF22:AF22,\" &\n\t\"IO_AF23:AF23,\" &\n\t\"IO_AF25:AF25,\" &\n\t\"IO_AF26:AF26,\" &\n\t\"IO_AF27:AF27,\" &\n\t\"IO_AF28:AF28,\" &\n\t\"IO_AF30:AF30,\" &\n\t\"IO_AG2:AG2,\" &\n\t\"IO_AG3:AG3,\" &\n\t\"IO_AG4:AG4,\" &\n\t\"IO_AG5:AG5,\" &\n\t\"IO_AG7:AG7,\" &\n\t\"IO_AG8:AG8,\" &\n\t\"IO_AG9:AG9,\" &\n\t\"IO_AG10:AG10,\" &\n\t\"IO_AG12:AG12,\" &\n\t\"IO_AG13:AG13,\" &\n\t\"IO_AG14:AG14,\" &\n\t\"IO_AG15:AG15,\" &\n\t\"IO_AG17:AG17,\" &\n\t\"IO_AG18:AG18,\" &\n\t\"IO_AG19:AG19,\" &\n\t\"IO_AG20:AG20,\" &\n\t\"IO_AG22:AG22,\" &\n\t\"IO_AG23:AG23,\" &\n\t\"IO_AG24:AG24,\" &\n\t\"IO_AG25:AG25,\" &\n\t\"IO_AG27:AG27,\" &\n\t\"IO_AG28:AG28,\" &\n\t\"IO_AG29:AG29,\" &\n\t\"IO_AG30:AG30,\" &\n\t\"IO_AH1:AH1,\" &\n\t\"IO_AH2:AH2,\" &\n\t\"IO_AH4:AH4,\" &\n\t\"IO_AH5:AH5,\" &\n\t\"IO_AH6:AH6,\" &\n\t\"IO_AH7:AH7,\" &\n\t\"IO_AH9:AH9,\" &\n\t\"IO_AH10:AH10,\" &\n\t\"IO_AH11:AH11,\" &\n\t\"IO_AH12:AH12,\" &\n\t\"IO_AH14:AH14,\" &\n\t\"IO_AH15:AH15,\" &\n\t\"IO_AH16:AH16,\" &\n\t\"IO_AH17:AH17,\" &\n\t\"IO_AH19:AH19,\" &\n\t\"IO_AH20:AH20,\" &\n\t\"IO_AH21:AH21,\" &\n\t\"IO_AH22:AH22,\" &\n\t\"IO_AH24:AH24,\" &\n\t\"IO_AH25:AH25,\" &\n\t\"IO_AH26:AH26,\" &\n\t\"IO_AH27:AH27,\" &\n\t\"IO_AH29:AH29,\" &\n\t\"IO_AH30:AH30,\" &\n\t\"IO_AJ1:AJ1,\" &\n\t\"IO_AJ2:AJ2,\" &\n\t\"IO_AJ3:AJ3,\" &\n\t\"IO_AJ4:AJ4,\" &\n\t\"IO_AJ6:AJ6,\" &\n\t\"IO_AJ7:AJ7,\" &\n\t\"IO_AJ8:AJ8,\" &\n\t\"IO_AJ9:AJ9,\" &\n\t\"IO_AJ11:AJ11,\" &\n\t\"IO_AJ12:AJ12,\" &\n\t\"IO_AJ13:AJ13,\" &\n\t\"IO_AJ14:AJ14,\" &\n\t\"IO_AJ16:AJ16,\" &\n\t\"IO_AJ17:AJ17,\" &\n\t\"IO_AJ18:AJ18,\" &\n\t\"IO_AJ19:AJ19,\" &\n\t\"IO_AJ21:AJ21,\" &\n\t\"IO_AJ22:AJ22,\" &\n\t\"IO_AJ23:AJ23,\" &\n\t\"IO_AJ24:AJ24,\" &\n\t\"IO_AJ26:AJ26,\" &\n\t\"IO_AJ27:AJ27,\" &\n\t\"IO_AJ28:AJ28,\" &\n\t\"IO_AJ29:AJ29,\" &\n\t\"IO_AK1:AK1,\" &\n\t\"IO_AK3:AK3,\" &\n\t\"IO_AK4:AK4,\" &\n\t\"IO_AK5:AK5,\" &\n\t\"IO_AK6:AK6,\" &\n\t\"IO_AK8:AK8,\" &\n\t\"IO_AK9:AK9,\" &\n\t\"IO_AK10:AK10,\" &\n\t\"IO_AK11:AK11,\" &\n\t\"IO_AK13:AK13,\" &\n\t\"IO_AK14:AK14,\" &\n\t\"IO_AK15:AK15,\" &\n\t\"IO_AK16:AK16,\" &\n\t\"IO_AK18:AK18,\" &\n\t\"IO_AK19:AK19,\" &\n\t\"IO_AK20:AK20,\" &\n\t\"IO_AK21:AK21,\" &\n\t\"IO_AK23:AK23,\" &\n\t\"IO_AK24:AK24,\" &\n\t\"IO_AK25:AK25,\" &\n\t\"IO_AK26:AK26,\" &\n\t\"IO_AK28:AK28,\" &\n\t\"IO_AK29:AK29,\" &\n\t\"IO_AK30:AK30\";\n\n\n-- Grouped Port Identification\n\nattribute PORT_GROUPING of XC7K325T_FFG900 : entity is\n\"DIFFERENTIAL_VOLTAGE (\" &\n\"(MGTXRXP0_115, MGTXRXN0_115), \" &\n\"(MGTXRXP0_116, MGTXRXN0_116), \" &\n\"(MGTXRXP0_117, MGTXRXN0_117), \" &\n\"(MGTXRXP0_118, MGTXRXN0_118), \" &\n\"(MGTXRXP1_115, MGTXRXN1_115), \" &\n\"(MGTXRXP1_116, MGTXRXN1_116), \" &\n\"(MGTXRXP1_117, MGTXRXN1_117), \" &\n\"(MGTXRXP1_118, MGTXRXN1_118), \" &\n\"(MGTXRXP2_115, MGTXRXN2_115), \" &\n\"(MGTXRXP2_116, MGTXRXN2_116), \" &\n\"(MGTXRXP2_117, MGTXRXN2_117), \" &\n\"(MGTXRXP2_118, MGTXRXN2_118), \" &\n\"(MGTXRXP3_115, MGTXRXN3_115), \" &\n\"(MGTXRXP3_116, MGTXRXN3_116), \" &\n\"(MGTXRXP3_117, MGTXRXN3_117), \" &\n\"(MGTXRXP3_118, MGTXRXN3_118), \" &\n\"(MGTXTXP0_115, MGTXTXN0_115), \" &\n\"(MGTXTXP0_116, MGTXTXN0_116), \" &\n\"(MGTXTXP0_117, MGTXTXN0_117), \" &\n\"(MGTXTXP0_118, MGTXTXN0_118), \" &\n\"(MGTXTXP1_115, MGTXTXN1_115), \" &\n\"(MGTXTXP1_116, MGTXTXN1_116), \" &\n\"(MGTXTXP1_117, MGTXTXN1_117), \" &\n\"(MGTXTXP1_118, MGTXTXN1_118), \" &\n\"(MGTXTXP2_115, MGTXTXN2_115), \" &\n\"(MGTXTXP2_116, MGTXTXN2_116), \" &\n\"(MGTXTXP2_117, MGTXTXN2_117), \" &\n\"(MGTXTXP2_118, MGTXTXN2_118), \" &\n\"(MGTXTXP3_115, MGTXTXN3_115), \" &\n\"(MGTXTXP3_116, MGTXTXN3_116), \" &\n\"(MGTXTXP3_117, MGTXTXN3_117), \" &\n\"(MGTXTXP3_118, MGTXTXN3_118))\";\n\n-- Scan Port Identification\n\nattribute TAP_SCAN_IN    of TDI : signal is true;\nattribute TAP_SCAN_MODE  of TMS : signal is true;\nattribute TAP_SCAN_OUT   of TDO : signal is true;\nattribute TAP_SCAN_CLOCK of TCK : signal is (66.0e6, BOTH);\n\n-- Compliance-Enable Description\n\nattribute COMPLIANCE_PATTERNS of XC7K325T_FFG900 : entity is\n        \"(PROGRAM_B) (1)\";\n\n-- Instruction Register Description\n\nattribute INSTRUCTION_LENGTH of XC7K325T_FFG900 : entity is 6;\n\nattribute INSTRUCTION_OPCODE of XC7K325T_FFG900 : entity is\n        \"IDCODE\t\t(001001),\" & -- DEVICE_ID\n        \"BYPASS\t\t(111111),\" & -- BYPASS\n        \"EXTEST\t\t(100110),\" & -- BOUNDARY\n        \"SAMPLE\t\t(000001),\" & -- BOUNDARY\n        \"PRELOAD\t(000001),\" & -- Same as SAMPLE\n        \"USERCODE\t(001000),\" & -- DEVICE_ID\n        \"HIGHZ\t\t(001010),\" & -- BYPASS\n        \"EXTEST_PULSE\t(111100),\" & -- BOUNDARY\n        \"EXTEST_TRAIN\t(111101),\" & -- BOUNDARY\n\t\"ISC_ENABLE\t(010000),\" & -- ISC_CONFIG\n\t\"ISC_PROGRAM\t(010001),\" & -- ISC_PDATA\n\t\"ISC_NOOP\t(010100),\" & -- ISC_DEFAULT\n\t\"XSC_READ_RSVD\t(010101),\" & -- PRIVATE\n\t\"ISC_DISABLE\t(010110),\" & -- ISC_CONFIG\n\t\"XSC_PROGRAM_KEY\t(010010),\" & -- XSC_KEY_DATA\n        \"XSC_DNA\t(010111),\" & -- DNA\n        \"CFG_OUT\t(000100),\" & -- Not available during configuration with another mode.\n        \"CFG_IN\t\t(000101),\" & -- Not available during configuration with another mode.\n        \"JPROGRAM\t(001011),\" & -- Not available during configuration with another mode.\n        \"JSTART\t\t(001100),\" & -- Not available during configuration with another mode.\n        \"JSHUTDOWN\t(001101),\" & -- Not available during configuration with another mode.\n        \"FUSE_CTS\t(110000),\" & -- PRIVATE\n        \"FUSE_KEY\t(110001),\" & -- PRIVATE\n        \"FUSE_DNA\t(110010),\" & -- PRIVATE\n        \"FUSE_USER\t(110011),\" & -- PRIVATE\n        \"FUSE_CNTL\t(110100),\" & -- PRIVATE\n        \"USER1\t\t(000010),\" & -- Not available until after configuration\n        \"USER2\t\t(000011),\" & -- Not available until after configuration\n        \"USER3\t\t(100010),\" & -- Not available until after configuration\n        \"USER4\t\t(100011),\" & -- Not available until after configuration\n        \"XADC_DRP\t(110111),\" & -- PRIVATE\n        \"INTEST_RSVD\t(000111)\"; -- PRIVATE\n\nattribute INSTRUCTION_CAPTURE of XC7K325T_FFG900 : entity is\n-- Bit 5 is 1 when DONE is released (part of startup sequence)\n-- Bit 4 is 1 if house-cleaning is complete\n-- Bit 3 is ISC_Enabled\n-- Bit 2 is ISC_Done\n        \"XXXX01\";\n\nattribute INSTRUCTION_PRIVATE of XC7K325T_FFG900 : entity is\n-- If the device is configured, and a USER instruction is implemented\n-- and not private to the FPGA designer, then it should be removed\n-- from INSTRUCTION_PRIVATE, and the target register should be defined\n-- in REGISTER_ACCESS.\n\t\"ISC_ENABLE,\" &\n\t\"ISC_PROGRAM,\" &\n\t\"ISC_NOOP,\" &\n\t\"XSC_READ_RSVD,\" &\n\t\"ISC_DISABLE,\" &\n\t\"XSC_PROGRAM_KEY,\" &\n\t\"XSC_DNA,\" &\n        \"CFG_OUT,\" &\n        \"CFG_IN,\" &\n        \"JPROGRAM,\" &\n        \"JSTART,\" &\n        \"JSHUTDOWN,\" &\n        \"FUSE_CTS,\" &\n        \"FUSE_KEY,\" &\n        \"FUSE_DNA,\" &\n        \"FUSE_USER,\" &\n        \"FUSE_CNTL,\" &\n        \"USER1,\" &\n        \"USER2,\" &\n        \"USER3,\" &\n        \"USER4,\" &\n        \"XADC_DRP,\" &\n        \"INTEST_RSVD\";\n\n-- Optional Register Description\n\nattribute IDCODE_REGISTER of XC7K325T_FFG900 : entity is\n\t\"XXXX\" &\t-- version\n\t\"0011011\" &\t-- family\n\t\"001010001\" &\t-- array size\n\t\"00001001001\" &\t-- manufacturer\n\t\"1\";\t\t-- required by 1149.1\n\n\nattribute USERCODE_REGISTER of XC7K325T_FFG900 : entity is\n        \"XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX\";\n\n-- Register Access Description\n\nattribute REGISTER_ACCESS of XC7K325T_FFG900 : entity is\n--\t\"<reg_name>[<length>] (USER1),\" &\n--\t\"<reg_name>[<length>] (USER2),\" &\n--\t\"<reg_name>[<length>] (USER3),\" &\n--\t\"<reg_name>[<length>] (USER4),\" &\n        \"DATAREG[57] (XSC_DNA),\" &\n        \"BYPASS (HIGHZ,BYPASS),\" &\n\t\"DEVICE_ID (USERCODE,IDCODE),\" &\n\t\"BOUNDARY (SAMPLE,PRELOAD,EXTEST,EXTEST_PULSE,EXTEST_TRAIN)\";\n\n-- Boundary-Scan Register Description\n\nattribute BOUNDARY_LENGTH of XC7K325T_FFG900 : entity is 1631;\n\nattribute BOUNDARY_REGISTER of XC7K325T_FFG900 : entity is\n-- cellnum (type, port, function, safe[, ccell, disval, disrslt])\n\t\"   0 (BC_2, *, controlr, 1),\" &\n\t\"   1 (BC_2, CCLK_B10, output3, X, 0, 1, Z),\" & --  CCLK_0\n\t\"   2 (BC_2, CCLK_B10, input, X),\" & --  CCLK_0\n\t\"   3 (BC_2, M0_AB5, input, X),\" &\n\t\"   4 (BC_2, M1_AB2, input, X),\" &\n\t\"   5 (BC_2, M2_AB1, input, X),\" &\n\t\"   6 (BC_2, CFGBVS_L10, input, X),\" &\n\t\"   7 (BC_2, *, internal, 1),\" & --  PROGRAM_B\n\t\"   8 (BC_2, *, controlr, 1),\" &\n\t\"   9 (BC_2, INIT_B_A10, output3, X, 8, 1, Z),\" & --  INIT_B_0\n\t\"  10 (BC_2, INIT_B_A10, input, X),\" & --  INIT_B_0\n\t\"  11 (BC_2, *, controlr, 1),\" &\n\t\"  12 (BC_2, DONE_M10, output3, X, 11, 1, Z),\" & --  DONE_0\n\t\"  13 (BC_2, DONE_M10, input, X),\" & --  DONE_0\n\t\"  14 (BC_2, *, internal, X),\" &\n\t\"  15 (BC_2, *, internal, X),\" &\n\t\"  16 (BC_2, *, internal, X),\" &\n\t\"  17 (BC_2, *, internal, X),\" &\n\t\"  18 (BC_2, *, internal, X),\" &\n\t\"  19 (BC_2, *, internal, X),\" &\n\t\"  20 (BC_2, *, internal, X),\" &\n\t\"  21 (BC_2, *, internal, X),\" &\n\t\"  22 (BC_2, *, internal, X),\" &\n\t\"  23 (BC_2, *, internal, X),\" &\n\t\"  24 (BC_2, *, internal, X),\" &\n\t\"  25 (BC_2, *, internal, X),\" &\n\t\"  26 (BC_2, *, internal, X),\" &\n\t\"  27 (BC_2, *, internal, X),\" &\n\t\"  28 (BC_2, *, internal, X),\" &\n\t\"  29 (BC_2, *, internal, X),\" &\n\t\"  30 (BC_2, *, internal, X),\" &\n\t\"  31 (BC_2, *, internal, X),\" &\n\t\"  32 (BC_2, *, internal, X),\" &\n\t\"  33 (BC_2, *, internal, X),\" &\n\t\"  34 (BC_2, *, internal, X),\" &\n\t\"  35 (BC_2, *, internal, X),\" &\n\t\"  36 (BC_2, *, internal, X),\" &\n\t\"  37 (BC_2, *, internal, X),\" &\n\t\"  38 (BC_2, *, internal, X),\" &\n\t\"  39 (BC_2, *, internal, X),\" &\n\t\"  40 (BC_2, *, internal, X),\" &\n\t\"  41 (BC_2, *, internal, X),\" &\n\t\"  42 (BC_2, *, internal, X),\" &\n\t\"  43 (BC_2, *, internal, X),\" &\n\t\"  44 (BC_2, *, controlr, 1),\" &\n\t\"  45 (BC_2, IO_AB14, output3, X, 44, 1, Z),\" & --  PAD500\n\t\"  46 (BC_2, IO_AB14, input, X),\" & --  PAD500\n\t\"  47 (BC_2, *, controlr, 1),\" &\n\t\"  48 (BC_2, IO_Y15, output3, X, 47, 1, Z),\" & --  PAD499\n\t\"  49 (BC_2, IO_Y15, input, X),\" & --  PAD499\n\t\"  50 (BC_2, *, controlr, 1),\" &\n\t\"  51 (BC_2, IO_Y16, output3, X, 50, 1, Z),\" & --  PAD498\n\t\"  52 (BC_2, IO_Y16, input, X),\" & --  PAD498\n\t\"  53 (BC_2, *, controlr, 1),\" &\n\t\"  54 (BC_2, IO_AA16, output3, X, 53, 1, Z),\" & --  PAD497\n\t\"  55 (BC_2, IO_AA16, input, X),\" & --  PAD497\n\t\"  56 (BC_2, *, controlr, 1),\" &\n\t\"  57 (BC_2, IO_AA17, output3, X, 56, 1, Z),\" & --  PAD496\n\t\"  58 (BC_2, IO_AA17, input, X),\" & --  PAD496\n\t\"  59 (BC_2, *, controlr, 1),\" &\n\t\"  60 (BC_2, IO_AD14, output3, X, 59, 1, Z),\" & --  PAD495\n\t\"  61 (BC_2, IO_AD14, input, X),\" & --  PAD495\n\t\"  62 (BC_2, *, controlr, 1),\" &\n\t\"  63 (BC_2, IO_AC14, output3, X, 62, 1, Z),\" & --  PAD494\n\t\"  64 (BC_2, IO_AC14, input, X),\" & --  PAD494\n\t\"  65 (BC_2, *, controlr, 1),\" &\n\t\"  66 (BC_2, IO_AC15, output3, X, 65, 1, Z),\" & --  PAD493\n\t\"  67 (BC_2, IO_AC15, input, X),\" & --  PAD493\n\t\"  68 (BC_2, *, controlr, 1),\" &\n\t\"  69 (BC_2, IO_AC16, output3, X, 68, 1, Z),\" & --  PAD492\n\t\"  70 (BC_2, IO_AC16, input, X),\" & --  PAD492\n\t\"  71 (BC_2, *, controlr, 1),\" &\n\t\"  72 (BC_2, IO_AB15, output3, X, 71, 1, Z),\" & --  PAD491\n\t\"  73 (BC_2, IO_AB15, input, X),\" & --  PAD491\n\t\"  74 (BC_2, *, controlr, 1),\" &\n\t\"  75 (BC_2, IO_AA15, output3, X, 74, 1, Z),\" & --  PAD490\n\t\"  76 (BC_2, IO_AA15, input, X),\" & --  PAD490\n\t\"  77 (BC_2, *, controlr, 1),\" &\n\t\"  78 (BC_2, IO_AE14, output3, X, 77, 1, Z),\" & --  PAD489\n\t\"  79 (BC_2, IO_AE14, input, X),\" & --  PAD489\n\t\"  80 (BC_2, *, controlr, 1),\" &\n\t\"  81 (BC_2, IO_AE15, output3, X, 80, 1, Z),\" & --  PAD488\n\t\"  82 (BC_2, IO_AE15, input, X),\" & --  PAD488\n\t\"  83 (BC_2, *, controlr, 1),\" &\n\t\"  84 (BC_2, IO_AC17, output3, X, 83, 1, Z),\" & --  PAD487\n\t\"  85 (BC_2, IO_AC17, input, X),\" & --  PAD487\n\t\"  86 (BC_2, *, controlr, 1),\" &\n\t\"  87 (BC_2, IO_AB17, output3, X, 86, 1, Z),\" & --  PAD486\n\t\"  88 (BC_2, IO_AB17, input, X),\" & --  PAD486\n\t\"  89 (BC_2, *, controlr, 1),\" &\n\t\"  90 (BC_2, IO_AC19, output3, X, 89, 1, Z),\" & --  PAD485\n\t\"  91 (BC_2, IO_AC19, input, X),\" & --  PAD485\n\t\"  92 (BC_2, *, controlr, 1),\" &\n\t\"  93 (BC_2, IO_AB19, output3, X, 92, 1, Z),\" & --  PAD484\n\t\"  94 (BC_2, IO_AB19, input, X),\" & --  PAD484\n\t\"  95 (BC_2, *, controlr, 1),\" &\n\t\"  96 (BC_2, IO_AB18, output3, X, 95, 1, Z),\" & --  PAD483\n\t\"  97 (BC_2, IO_AB18, input, X),\" & --  PAD483\n\t\"  98 (BC_2, *, controlr, 1),\" &\n\t\"  99 (BC_2, IO_AA18, output3, X, 98, 1, Z),\" & --  PAD482\n\t\" 100 (BC_2, IO_AA18, input, X),\" & --  PAD482\n\t\" 101 (BC_2, *, controlr, 1),\" &\n\t\" 102 (BC_2, IO_Y18, output3, X, 101, 1, Z),\" & --  PAD481\n\t\" 103 (BC_2, IO_Y18, input, X),\" & --  PAD481\n\t\" 104 (BC_2, *, controlr, 1),\" &\n\t\" 105 (BC_2, IO_Y19, output3, X, 104, 1, Z),\" & --  PAD480\n\t\" 106 (BC_2, IO_Y19, input, X),\" & --  PAD480\n\t\" 107 (BC_2, *, controlr, 1),\" &\n\t\" 108 (BC_2, IO_AD16, output3, X, 107, 1, Z),\" & --  PAD479\n\t\" 109 (BC_2, IO_AD16, input, X),\" & --  PAD479\n\t\" 110 (BC_2, *, controlr, 1),\" &\n\t\" 111 (BC_2, IO_AD17, output3, X, 110, 1, Z),\" & --  PAD478\n\t\" 112 (BC_2, IO_AD17, input, X),\" & --  PAD478\n\t\" 113 (BC_2, *, controlr, 1),\" &\n\t\" 114 (BC_2, IO_AE18, output3, X, 113, 1, Z),\" & --  PAD477\n\t\" 115 (BC_2, IO_AE18, input, X),\" & --  PAD477\n\t\" 116 (BC_2, *, controlr, 1),\" &\n\t\" 117 (BC_2, IO_AD18, output3, X, 116, 1, Z),\" & --  PAD476\n\t\" 118 (BC_2, IO_AD18, input, X),\" & --  PAD476\n\t\" 119 (BC_2, *, controlr, 1),\" &\n\t\" 120 (BC_2, IO_AG17, output3, X, 119, 1, Z),\" & --  PAD475\n\t\" 121 (BC_2, IO_AG17, input, X),\" & --  PAD475\n\t\" 122 (BC_2, *, controlr, 1),\" &\n\t\" 123 (BC_2, IO_AF17, output3, X, 122, 1, Z),\" & --  PAD474\n\t\" 124 (BC_2, IO_AF17, input, X),\" & --  PAD474\n\t\" 125 (BC_2, *, controlr, 1),\" &\n\t\" 126 (BC_2, IO_AG18, output3, X, 125, 1, Z),\" & --  PAD473\n\t\" 127 (BC_2, IO_AG18, input, X),\" & --  PAD473\n\t\" 128 (BC_2, *, controlr, 1),\" &\n\t\" 129 (BC_2, IO_AF18, output3, X, 128, 1, Z),\" & --  PAD472\n\t\" 130 (BC_2, IO_AF18, input, X),\" & --  PAD472\n\t\" 131 (BC_2, *, controlr, 1),\" &\n\t\" 132 (BC_2, IO_AE19, output3, X, 131, 1, Z),\" & --  PAD471\n\t\" 133 (BC_2, IO_AE19, input, X),\" & --  PAD471\n\t\" 134 (BC_2, *, controlr, 1),\" &\n\t\" 135 (BC_2, IO_AD19, output3, X, 134, 1, Z),\" & --  PAD470\n\t\" 136 (BC_2, IO_AD19, input, X),\" & --  PAD470\n\t\" 137 (BC_2, *, controlr, 1),\" &\n\t\" 138 (BC_2, IO_AK18, output3, X, 137, 1, Z),\" & --  PAD469\n\t\" 139 (BC_2, IO_AK18, input, X),\" & --  PAD469\n\t\" 140 (BC_2, *, controlr, 1),\" &\n\t\" 141 (BC_2, IO_AJ18, output3, X, 140, 1, Z),\" & --  PAD468\n\t\" 142 (BC_2, IO_AJ18, input, X),\" & --  PAD468\n\t\" 143 (BC_2, *, controlr, 1),\" &\n\t\" 144 (BC_2, IO_AH19, output3, X, 143, 1, Z),\" & --  PAD467\n\t\" 145 (BC_2, IO_AH19, input, X),\" & --  PAD467\n\t\" 146 (BC_2, *, controlr, 1),\" &\n\t\" 147 (BC_2, IO_AG19, output3, X, 146, 1, Z),\" & --  PAD466\n\t\" 148 (BC_2, IO_AG19, input, X),\" & --  PAD466\n\t\" 149 (BC_2, *, controlr, 1),\" &\n\t\" 150 (BC_2, IO_AK19, output3, X, 149, 1, Z),\" & --  PAD465\n\t\" 151 (BC_2, IO_AK19, input, X),\" & --  PAD465\n\t\" 152 (BC_2, *, controlr, 1),\" &\n\t\" 153 (BC_2, IO_AJ19, output3, X, 152, 1, Z),\" & --  PAD464\n\t\" 154 (BC_2, IO_AJ19, input, X),\" & --  PAD464\n\t\" 155 (BC_2, *, controlr, 1),\" &\n\t\" 156 (BC_2, IO_AF16, output3, X, 155, 1, Z),\" & --  PAD463\n\t\" 157 (BC_2, IO_AF16, input, X),\" & --  PAD463\n\t\" 158 (BC_2, *, controlr, 1),\" &\n\t\" 159 (BC_2, IO_AE16, output3, X, 158, 1, Z),\" & --  PAD462\n\t\" 160 (BC_2, IO_AE16, input, X),\" & --  PAD462\n\t\" 161 (BC_2, *, controlr, 1),\" &\n\t\" 162 (BC_2, IO_AJ17, output3, X, 161, 1, Z),\" & --  PAD461\n\t\" 163 (BC_2, IO_AJ17, input, X),\" & --  PAD461\n\t\" 164 (BC_2, *, controlr, 1),\" &\n\t\" 165 (BC_2, IO_AH17, output3, X, 164, 1, Z),\" & --  PAD460\n\t\" 166 (BC_2, IO_AH17, input, X),\" & --  PAD460\n\t\" 167 (BC_2, *, controlr, 1),\" &\n\t\" 168 (BC_2, IO_AG14, output3, X, 167, 1, Z),\" & --  PAD459\n\t\" 169 (BC_2, IO_AG14, input, X),\" & --  PAD459\n\t\" 170 (BC_2, *, controlr, 1),\" &\n\t\" 171 (BC_2, IO_AF15, output3, X, 170, 1, Z),\" & --  PAD458\n\t\" 172 (BC_2, IO_AF15, input, X),\" & --  PAD458\n\t\" 173 (BC_2, *, controlr, 1),\" &\n\t\" 174 (BC_2, IO_AJ16, output3, X, 173, 1, Z),\" & --  PAD457\n\t\" 175 (BC_2, IO_AJ16, input, X),\" & --  PAD457\n\t\" 176 (BC_2, *, controlr, 1),\" &\n\t\" 177 (BC_2, IO_AH16, output3, X, 176, 1, Z),\" & --  PAD456\n\t\" 178 (BC_2, IO_AH16, input, X),\" & --  PAD456\n\t\" 179 (BC_2, *, controlr, 1),\" &\n\t\" 180 (BC_2, IO_AH15, output3, X, 179, 1, Z),\" & --  PAD455\n\t\" 181 (BC_2, IO_AH15, input, X),\" & --  PAD455\n\t\" 182 (BC_2, *, controlr, 1),\" &\n\t\" 183 (BC_2, IO_AG15, output3, X, 182, 1, Z),\" & --  PAD454\n\t\" 184 (BC_2, IO_AG15, input, X),\" & --  PAD454\n\t\" 185 (BC_2, *, controlr, 1),\" &\n\t\" 186 (BC_2, IO_AK15, output3, X, 185, 1, Z),\" & --  PAD453\n\t\" 187 (BC_2, IO_AK15, input, X),\" & --  PAD453\n\t\" 188 (BC_2, *, controlr, 1),\" &\n\t\" 189 (BC_2, IO_AK16, output3, X, 188, 1, Z),\" & --  PAD452\n\t\" 190 (BC_2, IO_AK16, input, X),\" & --  PAD452\n\t\" 191 (BC_2, *, controlr, 1),\" &\n\t\" 192 (BC_2, IO_Y14, output3, X, 191, 1, Z),\" & --  PAD451\n\t\" 193 (BC_2, IO_Y14, input, X),\" & --  PAD451\n\t\" 194 (BC_2, *, controlr, 1),\" &\n\t\" 195 (BC_2, IO_AD13, output3, X, 194, 1, Z),\" & --  PAD450\n\t\" 196 (BC_2, IO_AD13, input, X),\" & --  PAD450\n\t\" 197 (BC_2, *, controlr, 1),\" &\n\t\" 198 (BC_2, IO_AH12, output3, X, 197, 1, Z),\" & --  PAD449\n\t\" 199 (BC_2, IO_AH12, input, X),\" & --  PAD449\n\t\" 200 (BC_2, *, controlr, 1),\" &\n\t\" 201 (BC_2, IO_AG13, output3, X, 200, 1, Z),\" & --  PAD448\n\t\" 202 (BC_2, IO_AG13, input, X),\" & --  PAD448\n\t\" 203 (BC_2, *, controlr, 1),\" &\n\t\" 204 (BC_2, IO_AG12, output3, X, 203, 1, Z),\" & --  PAD447\n\t\" 205 (BC_2, IO_AG12, input, X),\" & --  PAD447\n\t\" 206 (BC_2, *, controlr, 1),\" &\n\t\" 207 (BC_2, IO_AF12, output3, X, 206, 1, Z),\" & --  PAD446\n\t\" 208 (BC_2, IO_AF12, input, X),\" & --  PAD446\n\t\" 209 (BC_2, *, controlr, 1),\" &\n\t\" 210 (BC_2, IO_AJ12, output3, X, 209, 1, Z),\" & --  PAD445\n\t\" 211 (BC_2, IO_AJ12, input, X),\" & --  PAD445\n\t\" 212 (BC_2, *, controlr, 1),\" &\n\t\" 213 (BC_2, IO_AJ13, output3, X, 212, 1, Z),\" & --  PAD444\n\t\" 214 (BC_2, IO_AJ13, input, X),\" & --  PAD444\n\t\" 215 (BC_2, *, controlr, 1),\" &\n\t\" 216 (BC_2, IO_AJ14, output3, X, 215, 1, Z),\" & --  PAD443\n\t\" 217 (BC_2, IO_AJ14, input, X),\" & --  PAD443\n\t\" 218 (BC_2, *, controlr, 1),\" &\n\t\" 219 (BC_2, IO_AH14, output3, X, 218, 1, Z),\" & --  PAD442\n\t\" 220 (BC_2, IO_AH14, input, X),\" & --  PAD442\n\t\" 221 (BC_2, *, controlr, 1),\" &\n\t\" 222 (BC_2, IO_AK13, output3, X, 221, 1, Z),\" & --  PAD441\n\t\" 223 (BC_2, IO_AK13, input, X),\" & --  PAD441\n\t\" 224 (BC_2, *, controlr, 1),\" &\n\t\" 225 (BC_2, IO_AK14, output3, X, 224, 1, Z),\" & --  PAD440\n\t\" 226 (BC_2, IO_AK14, input, X),\" & --  PAD440\n\t\" 227 (BC_2, *, controlr, 1),\" &\n\t\" 228 (BC_2, IO_AF13, output3, X, 227, 1, Z),\" & --  PAD439\n\t\" 229 (BC_2, IO_AF13, input, X),\" & --  PAD439\n\t\" 230 (BC_2, *, controlr, 1),\" &\n\t\" 231 (BC_2, IO_AE13, output3, X, 230, 1, Z),\" & --  PAD438\n\t\" 232 (BC_2, IO_AE13, input, X),\" & --  PAD438\n\t\" 233 (BC_2, *, controlr, 1),\" &\n\t\" 234 (BC_2, IO_AJ11, output3, X, 233, 1, Z),\" & --  PAD437\n\t\" 235 (BC_2, IO_AJ11, input, X),\" & --  PAD437\n\t\" 236 (BC_2, *, controlr, 1),\" &\n\t\" 237 (BC_2, IO_AH11, output3, X, 236, 1, Z),\" & --  PAD436\n\t\" 238 (BC_2, IO_AH11, input, X),\" & --  PAD436\n\t\" 239 (BC_2, *, controlr, 1),\" &\n\t\" 240 (BC_2, IO_AK10, output3, X, 239, 1, Z),\" & --  PAD435\n\t\" 241 (BC_2, IO_AK10, input, X),\" & --  PAD435\n\t\" 242 (BC_2, *, controlr, 1),\" &\n\t\" 243 (BC_2, IO_AK11, output3, X, 242, 1, Z),\" & --  PAD434\n\t\" 244 (BC_2, IO_AK11, input, X),\" & --  PAD434\n\t\" 245 (BC_2, *, controlr, 1),\" &\n\t\" 246 (BC_2, IO_AH9, output3, X, 245, 1, Z),\" & --  PAD433\n\t\" 247 (BC_2, IO_AH9, input, X),\" & --  PAD433\n\t\" 248 (BC_2, *, controlr, 1),\" &\n\t\" 249 (BC_2, IO_AG9, output3, X, 248, 1, Z),\" & --  PAD432\n\t\" 250 (BC_2, IO_AG9, input, X),\" & --  PAD432\n\t\" 251 (BC_2, *, controlr, 1),\" &\n\t\" 252 (BC_2, IO_AK9, output3, X, 251, 1, Z),\" & --  PAD431\n\t\" 253 (BC_2, IO_AK9, input, X),\" & --  PAD431\n\t\" 254 (BC_2, *, controlr, 1),\" &\n\t\" 255 (BC_2, IO_AJ9, output3, X, 254, 1, Z),\" & --  PAD430\n\t\" 256 (BC_2, IO_AJ9, input, X),\" & --  PAD430\n\t\" 257 (BC_2, *, controlr, 1),\" &\n\t\" 258 (BC_2, IO_AF10, output3, X, 257, 1, Z),\" & --  PAD429\n\t\" 259 (BC_2, IO_AF10, input, X),\" & --  PAD429\n\t\" 260 (BC_2, *, controlr, 1),\" &\n\t\" 261 (BC_2, IO_AE10, output3, X, 260, 1, Z),\" & --  PAD428\n\t\" 262 (BC_2, IO_AE10, input, X),\" & --  PAD428\n\t\" 263 (BC_2, *, controlr, 1),\" &\n\t\" 264 (BC_2, IO_AH10, output3, X, 263, 1, Z),\" & --  PAD427\n\t\" 265 (BC_2, IO_AH10, input, X),\" & --  PAD427\n\t\" 266 (BC_2, *, controlr, 1),\" &\n\t\" 267 (BC_2, IO_AG10, output3, X, 266, 1, Z),\" & --  PAD426\n\t\" 268 (BC_2, IO_AG10, input, X),\" & --  PAD426\n\t\" 269 (BC_2, *, controlr, 1),\" &\n\t\" 270 (BC_2, IO_AD11, output3, X, 269, 1, Z),\" & --  PAD425\n\t\" 271 (BC_2, IO_AD11, input, X),\" & --  PAD425\n\t\" 272 (BC_2, *, controlr, 1),\" &\n\t\" 273 (BC_2, IO_AD12, output3, X, 272, 1, Z),\" & --  PAD424\n\t\" 274 (BC_2, IO_AD12, input, X),\" & --  PAD424\n\t\" 275 (BC_2, *, controlr, 1),\" &\n\t\" 276 (BC_2, IO_AF11, output3, X, 275, 1, Z),\" & --  PAD423\n\t\" 277 (BC_2, IO_AF11, input, X),\" & --  PAD423\n\t\" 278 (BC_2, *, controlr, 1),\" &\n\t\" 279 (BC_2, IO_AE11, output3, X, 278, 1, Z),\" & --  PAD422\n\t\" 280 (BC_2, IO_AE11, input, X),\" & --  PAD422\n\t\" 281 (BC_2, *, controlr, 1),\" &\n\t\" 282 (BC_2, IO_AE9, output3, X, 281, 1, Z),\" & --  PAD421\n\t\" 283 (BC_2, IO_AE9, input, X),\" & --  PAD421\n\t\" 284 (BC_2, *, controlr, 1),\" &\n\t\" 285 (BC_2, IO_AD9, output3, X, 284, 1, Z),\" & --  PAD420\n\t\" 286 (BC_2, IO_AD9, input, X),\" & --  PAD420\n\t\" 287 (BC_2, *, controlr, 1),\" &\n\t\" 288 (BC_2, IO_AC11, output3, X, 287, 1, Z),\" & --  PAD419\n\t\" 289 (BC_2, IO_AC11, input, X),\" & --  PAD419\n\t\" 290 (BC_2, *, controlr, 1),\" &\n\t\" 291 (BC_2, IO_AC12, output3, X, 290, 1, Z),\" & --  PAD418\n\t\" 292 (BC_2, IO_AC12, input, X),\" & --  PAD418\n\t\" 293 (BC_2, *, controlr, 1),\" &\n\t\" 294 (BC_2, IO_AE8, output3, X, 293, 1, Z),\" & --  PAD417\n\t\" 295 (BC_2, IO_AE8, input, X),\" & --  PAD417\n\t\" 296 (BC_2, *, controlr, 1),\" &\n\t\" 297 (BC_2, IO_AD8, output3, X, 296, 1, Z),\" & --  PAD416\n\t\" 298 (BC_2, IO_AD8, input, X),\" & --  PAD416\n\t\" 299 (BC_2, *, controlr, 1),\" &\n\t\" 300 (BC_2, IO_AC10, output3, X, 299, 1, Z),\" & --  PAD415\n\t\" 301 (BC_2, IO_AC10, input, X),\" & --  PAD415\n\t\" 302 (BC_2, *, controlr, 1),\" &\n\t\" 303 (BC_2, IO_AB10, output3, X, 302, 1, Z),\" & --  PAD414\n\t\" 304 (BC_2, IO_AB10, input, X),\" & --  PAD414\n\t\" 305 (BC_2, *, controlr, 1),\" &\n\t\" 306 (BC_2, IO_AB13, output3, X, 305, 1, Z),\" & --  PAD413\n\t\" 307 (BC_2, IO_AB13, input, X),\" & --  PAD413\n\t\" 308 (BC_2, *, controlr, 1),\" &\n\t\" 309 (BC_2, IO_AA13, output3, X, 308, 1, Z),\" & --  PAD412\n\t\" 310 (BC_2, IO_AA13, input, X),\" & --  PAD412\n\t\" 311 (BC_2, *, controlr, 1),\" &\n\t\" 312 (BC_2, IO_AA10, output3, X, 311, 1, Z),\" & --  PAD411\n\t\" 313 (BC_2, IO_AA10, input, X),\" & --  PAD411\n\t\" 314 (BC_2, *, controlr, 1),\" &\n\t\" 315 (BC_2, IO_AA11, output3, X, 314, 1, Z),\" & --  PAD410\n\t\" 316 (BC_2, IO_AA11, input, X),\" & --  PAD410\n\t\" 317 (BC_2, *, controlr, 1),\" &\n\t\" 318 (BC_2, IO_Y10, output3, X, 317, 1, Z),\" & --  PAD409\n\t\" 319 (BC_2, IO_Y10, input, X),\" & --  PAD409\n\t\" 320 (BC_2, *, controlr, 1),\" &\n\t\" 321 (BC_2, IO_Y11, output3, X, 320, 1, Z),\" & --  PAD408\n\t\" 322 (BC_2, IO_Y11, input, X),\" & --  PAD408\n\t\" 323 (BC_2, *, controlr, 1),\" &\n\t\" 324 (BC_2, IO_AC9, output3, X, 323, 1, Z),\" & --  PAD407\n\t\" 325 (BC_2, IO_AC9, input, X),\" & --  PAD407\n\t\" 326 (BC_2, *, controlr, 1),\" &\n\t\" 327 (BC_2, IO_AB9, output3, X, 326, 1, Z),\" & --  PAD406\n\t\" 328 (BC_2, IO_AB9, input, X),\" & --  PAD406\n\t\" 329 (BC_2, *, controlr, 1),\" &\n\t\" 330 (BC_2, IO_AB8, output3, X, 329, 1, Z),\" & --  PAD405\n\t\" 331 (BC_2, IO_AB8, input, X),\" & --  PAD405\n\t\" 332 (BC_2, *, controlr, 1),\" &\n\t\" 333 (BC_2, IO_AA8, output3, X, 332, 1, Z),\" & --  PAD404\n\t\" 334 (BC_2, IO_AA8, input, X),\" & --  PAD404\n\t\" 335 (BC_2, *, controlr, 1),\" &\n\t\" 336 (BC_2, IO_AB12, output3, X, 335, 1, Z),\" & --  PAD403\n\t\" 337 (BC_2, IO_AB12, input, X),\" & --  PAD403\n\t\" 338 (BC_2, *, controlr, 1),\" &\n\t\" 339 (BC_2, IO_AA12, output3, X, 338, 1, Z),\" & --  PAD402\n\t\" 340 (BC_2, IO_AA12, input, X),\" & --  PAD402\n\t\" 341 (BC_2, *, controlr, 1),\" &\n\t\" 342 (BC_2, IO_Y13, output3, X, 341, 1, Z),\" & --  PAD401\n\t\" 343 (BC_2, IO_Y13, input, X),\" & --  PAD401\n\t\" 344 (BC_2, *, controlr, 1),\" &\n\t\" 345 (BC_2, IO_AB7, output3, X, 344, 1, Z),\" & --  PAD400\n\t\" 346 (BC_2, IO_AB7, input, X),\" & --  PAD400\n\t\" 347 (BC_2, *, controlr, 1),\" &\n\t\" 348 (BC_2, IO_AK4, output3, X, 347, 1, Z),\" & --  PAD399\n\t\" 349 (BC_2, IO_AK4, input, X),\" & --  PAD399\n\t\" 350 (BC_2, *, controlr, 1),\" &\n\t\" 351 (BC_2, IO_AK5, output3, X, 350, 1, Z),\" & --  PAD398\n\t\" 352 (BC_2, IO_AK5, input, X),\" & --  PAD398\n\t\" 353 (BC_2, *, controlr, 1),\" &\n\t\" 354 (BC_2, IO_AK8, output3, X, 353, 1, Z),\" & --  PAD397\n\t\" 355 (BC_2, IO_AK8, input, X),\" & --  PAD397\n\t\" 356 (BC_2, *, controlr, 1),\" &\n\t\" 357 (BC_2, IO_AJ8, output3, X, 356, 1, Z),\" & --  PAD396\n\t\" 358 (BC_2, IO_AJ8, input, X),\" & --  PAD396\n\t\" 359 (BC_2, *, controlr, 1),\" &\n\t\" 360 (BC_2, IO_AK6, output3, X, 359, 1, Z),\" & --  PAD395\n\t\" 361 (BC_2, IO_AK6, input, X),\" & --  PAD395\n\t\" 362 (BC_2, *, controlr, 1),\" &\n\t\" 363 (BC_2, IO_AJ6, output3, X, 362, 1, Z),\" & --  PAD394\n\t\" 364 (BC_2, IO_AJ6, input, X),\" & --  PAD394\n\t\" 365 (BC_2, *, controlr, 1),\" &\n\t\" 366 (BC_2, IO_AJ7, output3, X, 365, 1, Z),\" & --  PAD393\n\t\" 367 (BC_2, IO_AJ7, input, X),\" & --  PAD393\n\t\" 368 (BC_2, *, controlr, 1),\" &\n\t\" 369 (BC_2, IO_AH7, output3, X, 368, 1, Z),\" & --  PAD392\n\t\" 370 (BC_2, IO_AH7, input, X),\" & --  PAD392\n\t\" 371 (BC_2, *, controlr, 1),\" &\n\t\" 372 (BC_2, IO_AG7, output3, X, 371, 1, Z),\" & --  PAD391\n\t\" 373 (BC_2, IO_AG7, input, X),\" & --  PAD391\n\t\" 374 (BC_2, *, controlr, 1),\" &\n\t\" 375 (BC_2, IO_AF7, output3, X, 374, 1, Z),\" & --  PAD390\n\t\" 376 (BC_2, IO_AF7, input, X),\" & --  PAD390\n\t\" 377 (BC_2, *, controlr, 1),\" &\n\t\" 378 (BC_2, IO_AG8, output3, X, 377, 1, Z),\" & --  PAD389\n\t\" 379 (BC_2, IO_AG8, input, X),\" & --  PAD389\n\t\" 380 (BC_2, *, controlr, 1),\" &\n\t\" 381 (BC_2, IO_AF8, output3, X, 380, 1, Z),\" & --  PAD388\n\t\" 382 (BC_2, IO_AF8, input, X),\" & --  PAD388\n\t\" 383 (BC_2, *, controlr, 1),\" &\n\t\" 384 (BC_2, IO_AK3, output3, X, 383, 1, Z),\" & --  PAD387\n\t\" 385 (BC_2, IO_AK3, input, X),\" & --  PAD387\n\t\" 386 (BC_2, *, controlr, 1),\" &\n\t\" 387 (BC_2, IO_AJ3, output3, X, 386, 1, Z),\" & --  PAD386\n\t\" 388 (BC_2, IO_AJ3, input, X),\" & --  PAD386\n\t\" 389 (BC_2, *, controlr, 1),\" &\n\t\" 390 (BC_2, IO_AK1, output3, X, 389, 1, Z),\" & --  PAD385\n\t\" 391 (BC_2, IO_AK1, input, X),\" & --  PAD385\n\t\" 392 (BC_2, *, controlr, 1),\" &\n\t\" 393 (BC_2, IO_AJ1, output3, X, 392, 1, Z),\" & --  PAD384\n\t\" 394 (BC_2, IO_AJ1, input, X),\" & --  PAD384\n\t\" 395 (BC_2, *, controlr, 1),\" &\n\t\" 396 (BC_2, IO_AJ2, output3, X, 395, 1, Z),\" & --  PAD383\n\t\" 397 (BC_2, IO_AJ2, input, X),\" & --  PAD383\n\t\" 398 (BC_2, *, controlr, 1),\" &\n\t\" 399 (BC_2, IO_AH2, output3, X, 398, 1, Z),\" & --  PAD382\n\t\" 400 (BC_2, IO_AH2, input, X),\" & --  PAD382\n\t\" 401 (BC_2, *, controlr, 1),\" &\n\t\" 402 (BC_2, IO_AH1, output3, X, 401, 1, Z),\" & --  PAD381\n\t\" 403 (BC_2, IO_AH1, input, X),\" & --  PAD381\n\t\" 404 (BC_2, *, controlr, 1),\" &\n\t\" 405 (BC_2, IO_AG2, output3, X, 404, 1, Z),\" & --  PAD380\n\t\" 406 (BC_2, IO_AG2, input, X),\" & --  PAD380\n\t\" 407 (BC_2, *, controlr, 1),\" &\n\t\" 408 (BC_2, IO_AH5, output3, X, 407, 1, Z),\" & --  PAD379\n\t\" 409 (BC_2, IO_AH5, input, X),\" & --  PAD379\n\t\" 410 (BC_2, *, controlr, 1),\" &\n\t\" 411 (BC_2, IO_AH6, output3, X, 410, 1, Z),\" & --  PAD378\n\t\" 412 (BC_2, IO_AH6, input, X),\" & --  PAD378\n\t\" 413 (BC_2, *, controlr, 1),\" &\n\t\" 414 (BC_2, IO_AJ4, output3, X, 413, 1, Z),\" & --  PAD377\n\t\" 415 (BC_2, IO_AJ4, input, X),\" & --  PAD377\n\t\" 416 (BC_2, *, controlr, 1),\" &\n\t\" 417 (BC_2, IO_AH4, output3, X, 416, 1, Z),\" & --  PAD376\n\t\" 418 (BC_2, IO_AH4, input, X),\" & --  PAD376\n\t\" 419 (BC_2, *, controlr, 1),\" &\n\t\" 420 (BC_2, IO_AG5, output3, X, 419, 1, Z),\" & --  PAD375\n\t\" 421 (BC_2, IO_AG5, input, X),\" & --  PAD375\n\t\" 422 (BC_2, *, controlr, 1),\" &\n\t\" 423 (BC_2, IO_AF6, output3, X, 422, 1, Z),\" & --  PAD374\n\t\" 424 (BC_2, IO_AF6, input, X),\" & --  PAD374\n\t\" 425 (BC_2, *, controlr, 1),\" &\n\t\" 426 (BC_2, IO_AF5, output3, X, 425, 1, Z),\" & --  PAD373\n\t\" 427 (BC_2, IO_AF5, input, X),\" & --  PAD373\n\t\" 428 (BC_2, *, controlr, 1),\" &\n\t\" 429 (BC_2, IO_AE5, output3, X, 428, 1, Z),\" & --  PAD372\n\t\" 430 (BC_2, IO_AE5, input, X),\" & --  PAD372\n\t\" 431 (BC_2, *, controlr, 1),\" &\n\t\" 432 (BC_2, IO_AE3, output3, X, 431, 1, Z),\" & --  PAD371\n\t\" 433 (BC_2, IO_AE3, input, X),\" & --  PAD371\n\t\" 434 (BC_2, *, controlr, 1),\" &\n\t\" 435 (BC_2, IO_AE4, output3, X, 434, 1, Z),\" & --  PAD370\n\t\" 436 (BC_2, IO_AE4, input, X),\" & --  PAD370\n\t\" 437 (BC_2, *, controlr, 1),\" &\n\t\" 438 (BC_2, IO_AG3, output3, X, 437, 1, Z),\" & --  PAD369\n\t\" 439 (BC_2, IO_AG3, input, X),\" & --  PAD369\n\t\" 440 (BC_2, *, controlr, 1),\" &\n\t\" 441 (BC_2, IO_AG4, output3, X, 440, 1, Z),\" & --  PAD368\n\t\" 442 (BC_2, IO_AG4, input, X),\" & --  PAD368\n\t\" 443 (BC_2, *, controlr, 1),\" &\n\t\" 444 (BC_2, IO_AF1, output3, X, 443, 1, Z),\" & --  PAD367\n\t\" 445 (BC_2, IO_AF1, input, X),\" & --  PAD367\n\t\" 446 (BC_2, *, controlr, 1),\" &\n\t\" 447 (BC_2, IO_AE1, output3, X, 446, 1, Z),\" & --  PAD366\n\t\" 448 (BC_2, IO_AE1, input, X),\" & --  PAD366\n\t\" 449 (BC_2, *, controlr, 1),\" &\n\t\" 450 (BC_2, IO_AF2, output3, X, 449, 1, Z),\" & --  PAD365\n\t\" 451 (BC_2, IO_AF2, input, X),\" & --  PAD365\n\t\" 452 (BC_2, *, controlr, 1),\" &\n\t\" 453 (BC_2, IO_AF3, output3, X, 452, 1, Z),\" & --  PAD364\n\t\" 454 (BC_2, IO_AF3, input, X),\" & --  PAD364\n\t\" 455 (BC_2, *, controlr, 1),\" &\n\t\" 456 (BC_2, IO_AD7, output3, X, 455, 1, Z),\" & --  PAD363\n\t\" 457 (BC_2, IO_AD7, input, X),\" & --  PAD363\n\t\" 458 (BC_2, *, controlr, 1),\" &\n\t\" 459 (BC_2, IO_AC7, output3, X, 458, 1, Z),\" & --  PAD362\n\t\" 460 (BC_2, IO_AC7, input, X),\" & --  PAD362\n\t\" 461 (BC_2, *, controlr, 1),\" &\n\t\" 462 (BC_2, IO_AE6, output3, X, 461, 1, Z),\" & --  PAD361\n\t\" 463 (BC_2, IO_AE6, input, X),\" & --  PAD361\n\t\" 464 (BC_2, *, controlr, 1),\" &\n\t\" 465 (BC_2, IO_AD6, output3, X, 464, 1, Z),\" & --  PAD360\n\t\" 466 (BC_2, IO_AD6, input, X),\" & --  PAD360\n\t\" 467 (BC_2, *, controlr, 1),\" &\n\t\" 468 (BC_2, IO_AC4, output3, X, 467, 1, Z),\" & --  PAD359\n\t\" 469 (BC_2, IO_AC4, input, X),\" & --  PAD359\n\t\" 470 (BC_2, *, controlr, 1),\" &\n\t\" 471 (BC_2, IO_AC5, output3, X, 470, 1, Z),\" & --  PAD358\n\t\" 472 (BC_2, IO_AC5, input, X),\" & --  PAD358\n\t\" 473 (BC_2, *, controlr, 1),\" &\n\t\" 474 (BC_2, IO_AD1, output3, X, 473, 1, Z),\" & --  PAD357\n\t\" 475 (BC_2, IO_AD1, input, X),\" & --  PAD357\n\t\" 476 (BC_2, *, controlr, 1),\" &\n\t\" 477 (BC_2, IO_AD2, output3, X, 476, 1, Z),\" & --  PAD356\n\t\" 478 (BC_2, IO_AD2, input, X),\" & --  PAD356\n\t\" 479 (BC_2, *, controlr, 1),\" &\n\t\" 480 (BC_2, IO_AC1, output3, X, 479, 1, Z),\" & --  PAD355\n\t\" 481 (BC_2, IO_AC1, input, X),\" & --  PAD355\n\t\" 482 (BC_2, *, controlr, 1),\" &\n\t\" 483 (BC_2, IO_AC2, output3, X, 482, 1, Z),\" & --  PAD354\n\t\" 484 (BC_2, IO_AC2, input, X),\" & --  PAD354\n\t\" 485 (BC_2, *, controlr, 1),\" &\n\t\" 486 (BC_2, IO_AD3, output3, X, 485, 1, Z),\" & --  PAD353\n\t\" 487 (BC_2, IO_AD3, input, X),\" & --  PAD353\n\t\" 488 (BC_2, *, controlr, 1),\" &\n\t\" 489 (BC_2, IO_AD4, output3, X, 488, 1, Z),\" & --  PAD352\n\t\" 490 (BC_2, IO_AD4, input, X),\" & --  PAD352\n\t\" 491 (BC_2, *, controlr, 1),\" &\n\t\" 492 (BC_2, IO_AC6, output3, X, 491, 1, Z),\" & --  PAD351\n\t\" 493 (BC_2, IO_AC6, input, X),\" & --  PAD351\n\t\" 494 (BC_2, *, internal, X),\" &\n\t\" 495 (BC_2, *, internal, X),\" &\n\t\" 496 (BC_2, *, internal, X),\" &\n\t\" 497 (BC_4, MGTXRXN0_115, OBSERVE_ONLY, X),\" &\n\t\" 498 (BC_4, MGTXRXP0_115, OBSERVE_ONLY, X),\" &\n\t\" 499 (AC_2, MGTXTXP0_115, OUTPUT2, X),\" &\n\t\" 500 (BC_4, MGTXRXN1_115, OBSERVE_ONLY, X),\" &\n\t\" 501 (BC_4, MGTXRXP1_115, OBSERVE_ONLY, X),\" &\n\t\" 502 (AC_2, MGTXTXP1_115, OUTPUT2, X),\" &\n\t\" 503 (BC_4, MGTXRXN2_115, OBSERVE_ONLY, X),\" &\n\t\" 504 (BC_4, MGTXRXP2_115, OBSERVE_ONLY, X),\" &\n\t\" 505 (AC_2, MGTXTXP2_115, OUTPUT2, X),\" &\n\t\" 506 (BC_4, MGTXRXN3_115, OBSERVE_ONLY, X),\" &\n\t\" 507 (BC_4, MGTXRXP3_115, OBSERVE_ONLY, X),\" &\n\t\" 508 (AC_2, MGTXTXP3_115, OUTPUT2, X),\" &\n\t\" 509 (BC_4, MGTXRXN0_116, OBSERVE_ONLY, X),\" &\n\t\" 510 (BC_4, MGTXRXP0_116, OBSERVE_ONLY, X),\" &\n\t\" 511 (AC_2, MGTXTXP0_116, OUTPUT2, X),\" &\n\t\" 512 (BC_4, MGTXRXN1_116, OBSERVE_ONLY, X),\" &\n\t\" 513 (BC_4, MGTXRXP1_116, OBSERVE_ONLY, X),\" &\n\t\" 514 (AC_2, MGTXTXP1_116, OUTPUT2, X),\" &\n\t\" 515 (BC_4, MGTXRXN2_116, OBSERVE_ONLY, X),\" &\n\t\" 516 (BC_4, MGTXRXP2_116, OBSERVE_ONLY, X),\" &\n\t\" 517 (AC_2, MGTXTXP2_116, OUTPUT2, X),\" &\n\t\" 518 (BC_4, MGTXRXN3_116, OBSERVE_ONLY, X),\" &\n\t\" 519 (BC_4, MGTXRXP3_116, OBSERVE_ONLY, X),\" &\n\t\" 520 (AC_2, MGTXTXP3_116, OUTPUT2, X),\" &\n\t\" 521 (BC_4, MGTXRXN0_117, OBSERVE_ONLY, X),\" &\n\t\" 522 (BC_4, MGTXRXP0_117, OBSERVE_ONLY, X),\" &\n\t\" 523 (AC_2, MGTXTXP0_117, OUTPUT2, X),\" &\n\t\" 524 (BC_4, MGTXRXN1_117, OBSERVE_ONLY, X),\" &\n\t\" 525 (BC_4, MGTXRXP1_117, OBSERVE_ONLY, X),\" &\n\t\" 526 (AC_2, MGTXTXP1_117, OUTPUT2, X),\" &\n\t\" 527 (BC_4, MGTXRXN2_117, OBSERVE_ONLY, X),\" &\n\t\" 528 (BC_4, MGTXRXP2_117, OBSERVE_ONLY, X),\" &\n\t\" 529 (AC_2, MGTXTXP2_117, OUTPUT2, X),\" &\n\t\" 530 (BC_4, MGTXRXN3_117, OBSERVE_ONLY, X),\" &\n\t\" 531 (BC_4, MGTXRXP3_117, OBSERVE_ONLY, X),\" &\n\t\" 532 (AC_2, MGTXTXP3_117, OUTPUT2, X),\" &\n\t\" 533 (BC_4, MGTXRXN0_118, OBSERVE_ONLY, X),\" &\n\t\" 534 (BC_4, MGTXRXP0_118, OBSERVE_ONLY, X),\" &\n\t\" 535 (AC_2, MGTXTXP0_118, OUTPUT2, X),\" &\n\t\" 536 (BC_4, MGTXRXN1_118, OBSERVE_ONLY, X),\" &\n\t\" 537 (BC_4, MGTXRXP1_118, OBSERVE_ONLY, X),\" &\n\t\" 538 (AC_2, MGTXTXP1_118, OUTPUT2, X),\" &\n\t\" 539 (BC_4, MGTXRXN2_118, OBSERVE_ONLY, X),\" &\n\t\" 540 (BC_4, MGTXRXP2_118, OBSERVE_ONLY, X),\" &\n\t\" 541 (AC_2, MGTXTXP2_118, OUTPUT2, X),\" &\n\t\" 542 (BC_4, MGTXRXN3_118, OBSERVE_ONLY, X),\" &\n\t\" 543 (BC_4, MGTXRXP3_118, OBSERVE_ONLY, X),\" &\n\t\" 544 (AC_2, MGTXTXP3_118, OUTPUT2, X),\" &\n\t\" 545 (BC_2, *, internal, X),\" &\n\t\" 546 (BC_2, *, internal, X),\" &\n\t\" 547 (BC_2, *, internal, X),\" &\n\t\" 548 (BC_2, *, internal, X),\" &\n\t\" 549 (BC_2, *, internal, X),\" &\n\t\" 550 (BC_2, *, internal, X),\" &\n\t\" 551 (BC_2, *, internal, X),\" &\n\t\" 552 (BC_2, *, internal, X),\" &\n\t\" 553 (BC_2, *, internal, X),\" &\n\t\" 554 (BC_2, *, internal, X),\" &\n\t\" 555 (BC_2, *, internal, X),\" &\n\t\" 556 (BC_2, *, internal, X),\" &\n\t\" 557 (BC_2, *, internal, X),\" &\n\t\" 558 (BC_2, *, internal, X),\" &\n\t\" 559 (BC_2, *, internal, X),\" &\n\t\" 560 (BC_2, *, internal, X),\" &\n\t\" 561 (BC_2, *, internal, X),\" &\n\t\" 562 (BC_2, *, internal, X),\" &\n\t\" 563 (BC_2, *, internal, X),\" &\n\t\" 564 (BC_2, *, internal, X),\" &\n\t\" 565 (BC_2, *, internal, X),\" &\n\t\" 566 (BC_2, *, internal, X),\" &\n\t\" 567 (BC_2, *, internal, X),\" &\n\t\" 568 (BC_2, *, internal, X),\" &\n\t\" 569 (BC_2, *, internal, X),\" &\n\t\" 570 (BC_2, *, internal, X),\" &\n\t\" 571 (BC_2, *, controlr, 1),\" &\n\t\" 572 (BC_2, IO_AE20, output3, X, 571, 1, Z),\" & --  PAD350\n\t\" 573 (BC_2, IO_AE20, input, X),\" & --  PAD350\n\t\" 574 (BC_2, *, controlr, 1),\" &\n\t\" 575 (BC_2, IO_AK21, output3, X, 574, 1, Z),\" & --  PAD349\n\t\" 576 (BC_2, IO_AK21, input, X),\" & --  PAD349\n\t\" 577 (BC_2, *, controlr, 1),\" &\n\t\" 578 (BC_2, IO_AK20, output3, X, 577, 1, Z),\" & --  PAD348\n\t\" 579 (BC_2, IO_AK20, input, X),\" & --  PAD348\n\t\" 580 (BC_2, *, controlr, 1),\" &\n\t\" 581 (BC_2, IO_AJ21, output3, X, 580, 1, Z),\" & --  PAD347\n\t\" 582 (BC_2, IO_AJ21, input, X),\" & --  PAD347\n\t\" 583 (BC_2, *, controlr, 1),\" &\n\t\" 584 (BC_2, IO_AH21, output3, X, 583, 1, Z),\" & --  PAD346\n\t\" 585 (BC_2, IO_AH21, input, X),\" & --  PAD346\n\t\" 586 (BC_2, *, controlr, 1),\" &\n\t\" 587 (BC_2, IO_AH20, output3, X, 586, 1, Z),\" & --  PAD345\n\t\" 588 (BC_2, IO_AH20, input, X),\" & --  PAD345\n\t\" 589 (BC_2, *, controlr, 1),\" &\n\t\" 590 (BC_2, IO_AG20, output3, X, 589, 1, Z),\" & --  PAD344\n\t\" 591 (BC_2, IO_AG20, input, X),\" & --  PAD344\n\t\" 592 (BC_2, *, controlr, 1),\" &\n\t\" 593 (BC_2, IO_AJ23, output3, X, 592, 1, Z),\" & --  PAD343\n\t\" 594 (BC_2, IO_AJ23, input, X),\" & --  PAD343\n\t\" 595 (BC_2, *, controlr, 1),\" &\n\t\" 596 (BC_2, IO_AJ22, output3, X, 595, 1, Z),\" & --  PAD342\n\t\" 597 (BC_2, IO_AJ22, input, X),\" & --  PAD342\n\t\" 598 (BC_2, *, controlr, 1),\" &\n\t\" 599 (BC_2, IO_AH22, output3, X, 598, 1, Z),\" & --  PAD341\n\t\" 600 (BC_2, IO_AH22, input, X),\" & --  PAD341\n\t\" 601 (BC_2, *, controlr, 1),\" &\n\t\" 602 (BC_2, IO_AG22, output3, X, 601, 1, Z),\" & --  PAD340\n\t\" 603 (BC_2, IO_AG22, input, X),\" & --  PAD340\n\t\" 604 (BC_2, *, controlr, 1),\" &\n\t\" 605 (BC_2, IO_AF21, output3, X, 604, 1, Z),\" & --  PAD339\n\t\" 606 (BC_2, IO_AF21, input, X),\" & --  PAD339\n\t\" 607 (BC_2, *, controlr, 1),\" &\n\t\" 608 (BC_2, IO_AF20, output3, X, 607, 1, Z),\" & --  PAD338\n\t\" 609 (BC_2, IO_AF20, input, X),\" & --  PAD338\n\t\" 610 (BC_2, *, controlr, 1),\" &\n\t\" 611 (BC_2, IO_AH25, output3, X, 610, 1, Z),\" & --  PAD337\n\t\" 612 (BC_2, IO_AH25, input, X),\" & --  PAD337\n\t\" 613 (BC_2, *, controlr, 1),\" &\n\t\" 614 (BC_2, IO_AG25, output3, X, 613, 1, Z),\" & --  PAD336\n\t\" 615 (BC_2, IO_AG25, input, X),\" & --  PAD336\n\t\" 616 (BC_2, *, controlr, 1),\" &\n\t\" 617 (BC_2, IO_AK24, output3, X, 616, 1, Z),\" & --  PAD335\n\t\" 618 (BC_2, IO_AK24, input, X),\" & --  PAD335\n\t\" 619 (BC_2, *, controlr, 1),\" &\n\t\" 620 (BC_2, IO_AK23, output3, X, 619, 1, Z),\" & --  PAD334\n\t\" 621 (BC_2, IO_AK23, input, X),\" & --  PAD334\n\t\" 622 (BC_2, *, controlr, 1),\" &\n\t\" 623 (BC_2, IO_AF25, output3, X, 622, 1, Z),\" & --  PAD333\n\t\" 624 (BC_2, IO_AF25, input, X),\" & --  PAD333\n\t\" 625 (BC_2, *, controlr, 1),\" &\n\t\" 626 (BC_2, IO_AE25, output3, X, 625, 1, Z),\" & --  PAD332\n\t\" 627 (BC_2, IO_AE25, input, X),\" & --  PAD332\n\t\" 628 (BC_2, *, controlr, 1),\" &\n\t\" 629 (BC_2, IO_AK25, output3, X, 628, 1, Z),\" & --  PAD331\n\t\" 630 (BC_2, IO_AK25, input, X),\" & --  PAD331\n\t\" 631 (BC_2, *, controlr, 1),\" &\n\t\" 632 (BC_2, IO_AJ24, output3, X, 631, 1, Z),\" & --  PAD330\n\t\" 633 (BC_2, IO_AJ24, input, X),\" & --  PAD330\n\t\" 634 (BC_2, *, controlr, 1),\" &\n\t\" 635 (BC_2, IO_AH24, output3, X, 634, 1, Z),\" & --  PAD329\n\t\" 636 (BC_2, IO_AH24, input, X),\" & --  PAD329\n\t\" 637 (BC_2, *, controlr, 1),\" &\n\t\" 638 (BC_2, IO_AG24, output3, X, 637, 1, Z),\" & --  PAD328\n\t\" 639 (BC_2, IO_AG24, input, X),\" & --  PAD328\n\t\" 640 (BC_2, *, controlr, 1),\" &\n\t\" 641 (BC_2, IO_AG23, output3, X, 640, 1, Z),\" & --  PAD327\n\t\" 642 (BC_2, IO_AG23, input, X),\" & --  PAD327\n\t\" 643 (BC_2, *, controlr, 1),\" &\n\t\" 644 (BC_2, IO_AF22, output3, X, 643, 1, Z),\" & --  PAD326\n\t\" 645 (BC_2, IO_AF22, input, X),\" & --  PAD326\n\t\" 646 (BC_2, *, controlr, 1),\" &\n\t\" 647 (BC_2, IO_AE24, output3, X, 646, 1, Z),\" & --  PAD325\n\t\" 648 (BC_2, IO_AE24, input, X),\" & --  PAD325\n\t\" 649 (BC_2, *, controlr, 1),\" &\n\t\" 650 (BC_2, IO_AD23, output3, X, 649, 1, Z),\" & --  PAD324\n\t\" 651 (BC_2, IO_AD23, input, X),\" & --  PAD324\n\t\" 652 (BC_2, *, controlr, 1),\" &\n\t\" 653 (BC_2, IO_AF23, output3, X, 652, 1, Z),\" & --  PAD323\n\t\" 654 (BC_2, IO_AF23, input, X),\" & --  PAD323\n\t\" 655 (BC_2, *, controlr, 1),\" &\n\t\" 656 (BC_2, IO_AE23, output3, X, 655, 1, Z),\" & --  PAD322\n\t\" 657 (BC_2, IO_AE23, input, X),\" & --  PAD322\n\t\" 658 (BC_2, *, controlr, 1),\" &\n\t\" 659 (BC_2, IO_AE21, output3, X, 658, 1, Z),\" & --  PAD321\n\t\" 660 (BC_2, IO_AE21, input, X),\" & --  PAD321\n\t\" 661 (BC_2, *, controlr, 1),\" &\n\t\" 662 (BC_2, IO_AD21, output3, X, 661, 1, Z),\" & --  PAD320\n\t\" 663 (BC_2, IO_AD21, input, X),\" & --  PAD320\n\t\" 664 (BC_2, *, controlr, 1),\" &\n\t\" 665 (BC_2, IO_AD24, output3, X, 664, 1, Z),\" & --  PAD319\n\t\" 666 (BC_2, IO_AD24, input, X),\" & --  PAD319\n\t\" 667 (BC_2, *, controlr, 1),\" &\n\t\" 668 (BC_2, IO_AC24, output3, X, 667, 1, Z),\" & --  PAD318\n\t\" 669 (BC_2, IO_AC24, input, X),\" & --  PAD318\n\t\" 670 (BC_2, *, controlr, 1),\" &\n\t\" 671 (BC_2, IO_AD22, output3, X, 670, 1, Z),\" & --  PAD317\n\t\" 672 (BC_2, IO_AD22, input, X),\" & --  PAD317\n\t\" 673 (BC_2, *, controlr, 1),\" &\n\t\" 674 (BC_2, IO_AC22, output3, X, 673, 1, Z),\" & --  PAD316\n\t\" 675 (BC_2, IO_AC22, input, X),\" & --  PAD316\n\t\" 676 (BC_2, *, controlr, 1),\" &\n\t\" 677 (BC_2, IO_AC25, output3, X, 676, 1, Z),\" & --  PAD315\n\t\" 678 (BC_2, IO_AC25, input, X),\" & --  PAD315\n\t\" 679 (BC_2, *, controlr, 1),\" &\n\t\" 680 (BC_2, IO_AB24, output3, X, 679, 1, Z),\" & --  PAD314\n\t\" 681 (BC_2, IO_AB24, input, X),\" & --  PAD314\n\t\" 682 (BC_2, *, controlr, 1),\" &\n\t\" 683 (BC_2, IO_AB20, output3, X, 682, 1, Z),\" & --  PAD313\n\t\" 684 (BC_2, IO_AB20, input, X),\" & --  PAD313\n\t\" 685 (BC_2, *, controlr, 1),\" &\n\t\" 686 (BC_2, IO_AA20, output3, X, 685, 1, Z),\" & --  PAD312\n\t\" 687 (BC_2, IO_AA20, input, X),\" & --  PAD312\n\t\" 688 (BC_2, *, controlr, 1),\" &\n\t\" 689 (BC_2, IO_AC21, output3, X, 688, 1, Z),\" & --  PAD311\n\t\" 690 (BC_2, IO_AC21, input, X),\" & --  PAD311\n\t\" 691 (BC_2, *, controlr, 1),\" &\n\t\" 692 (BC_2, IO_AC20, output3, X, 691, 1, Z),\" & --  PAD310\n\t\" 693 (BC_2, IO_AC20, input, X),\" & --  PAD310\n\t\" 694 (BC_2, *, controlr, 1),\" &\n\t\" 695 (BC_2, IO_AA23, output3, X, 694, 1, Z),\" & --  PAD309\n\t\" 696 (BC_2, IO_AA23, input, X),\" & --  PAD309\n\t\" 697 (BC_2, *, controlr, 1),\" &\n\t\" 698 (BC_2, IO_AA22, output3, X, 697, 1, Z),\" & --  PAD308\n\t\" 699 (BC_2, IO_AA22, input, X),\" & --  PAD308\n\t\" 700 (BC_2, *, controlr, 1),\" &\n\t\" 701 (BC_2, IO_AB23, output3, X, 700, 1, Z),\" & --  PAD307\n\t\" 702 (BC_2, IO_AB23, input, X),\" & --  PAD307\n\t\" 703 (BC_2, *, controlr, 1),\" &\n\t\" 704 (BC_2, IO_AB22, output3, X, 703, 1, Z),\" & --  PAD306\n\t\" 705 (BC_2, IO_AB22, input, X),\" & --  PAD306\n\t\" 706 (BC_2, *, controlr, 1),\" &\n\t\" 707 (BC_2, IO_AA21, output3, X, 706, 1, Z),\" & --  PAD305\n\t\" 708 (BC_2, IO_AA21, input, X),\" & --  PAD305\n\t\" 709 (BC_2, *, controlr, 1),\" &\n\t\" 710 (BC_2, IO_Y21, output3, X, 709, 1, Z),\" & --  PAD304\n\t\" 711 (BC_2, IO_Y21, input, X),\" & --  PAD304\n\t\" 712 (BC_2, *, controlr, 1),\" &\n\t\" 713 (BC_2, IO_Y24, output3, X, 712, 1, Z),\" & --  PAD303\n\t\" 714 (BC_2, IO_Y24, input, X),\" & --  PAD303\n\t\" 715 (BC_2, *, controlr, 1),\" &\n\t\" 716 (BC_2, IO_Y23, output3, X, 715, 1, Z),\" & --  PAD302\n\t\" 717 (BC_2, IO_Y23, input, X),\" & --  PAD302\n\t\" 718 (BC_2, *, controlr, 1),\" &\n\t\" 719 (BC_2, IO_Y20, output3, X, 718, 1, Z),\" & --  PAD301\n\t\" 720 (BC_2, IO_Y20, input, X),\" & --  PAD301\n\t\" 721 (BC_2, *, controlr, 1),\" &\n\t\" 722 (BC_2, IO_AE26, output3, X, 721, 1, Z),\" & --  PAD300\n\t\" 723 (BC_2, IO_AE26, input, X),\" & --  PAD300\n\t\" 724 (BC_2, *, controlr, 1),\" &\n\t\" 725 (BC_2, IO_AK26, output3, X, 724, 1, Z),\" & --  PAD299\n\t\" 726 (BC_2, IO_AK26, input, X),\" & --  PAD299\n\t\" 727 (BC_2, *, controlr, 1),\" &\n\t\" 728 (BC_2, IO_AJ26, output3, X, 727, 1, Z),\" & --  PAD298\n\t\" 729 (BC_2, IO_AJ26, input, X),\" & --  PAD298\n\t\" 730 (BC_2, *, controlr, 1),\" &\n\t\" 731 (BC_2, IO_AF27, output3, X, 730, 1, Z),\" & --  PAD297\n\t\" 732 (BC_2, IO_AF27, input, X),\" & --  PAD297\n\t\" 733 (BC_2, *, controlr, 1),\" &\n\t\" 734 (BC_2, IO_AF26, output3, X, 733, 1, Z),\" & --  PAD296\n\t\" 735 (BC_2, IO_AF26, input, X),\" & --  PAD296\n\t\" 736 (BC_2, *, controlr, 1),\" &\n\t\" 737 (BC_2, IO_AH27, output3, X, 736, 1, Z),\" & --  PAD295\n\t\" 738 (BC_2, IO_AH27, input, X),\" & --  PAD295\n\t\" 739 (BC_2, *, controlr, 1),\" &\n\t\" 740 (BC_2, IO_AH26, output3, X, 739, 1, Z),\" & --  PAD294\n\t\" 741 (BC_2, IO_AH26, input, X),\" & --  PAD294\n\t\" 742 (BC_2, *, controlr, 1),\" &\n\t\" 743 (BC_2, IO_AG28, output3, X, 742, 1, Z),\" & --  PAD293\n\t\" 744 (BC_2, IO_AG28, input, X),\" & --  PAD293\n\t\" 745 (BC_2, *, controlr, 1),\" &\n\t\" 746 (BC_2, IO_AG27, output3, X, 745, 1, Z),\" & --  PAD292\n\t\" 747 (BC_2, IO_AG27, input, X),\" & --  PAD292\n\t\" 748 (BC_2, *, controlr, 1),\" &\n\t\" 749 (BC_2, IO_AK28, output3, X, 748, 1, Z),\" & --  PAD291\n\t\" 750 (BC_2, IO_AK28, input, X),\" & --  PAD291\n\t\" 751 (BC_2, *, controlr, 1),\" &\n\t\" 752 (BC_2, IO_AJ27, output3, X, 751, 1, Z),\" & --  PAD290\n\t\" 753 (BC_2, IO_AJ27, input, X),\" & --  PAD290\n\t\" 754 (BC_2, *, controlr, 1),\" &\n\t\" 755 (BC_2, IO_AD26, output3, X, 754, 1, Z),\" & --  PAD289\n\t\" 756 (BC_2, IO_AD26, input, X),\" & --  PAD289\n\t\" 757 (BC_2, *, controlr, 1),\" &\n\t\" 758 (BC_2, IO_AC26, output3, X, 757, 1, Z),\" & --  PAD288\n\t\" 759 (BC_2, IO_AC26, input, X),\" & --  PAD288\n\t\" 760 (BC_2, *, controlr, 1),\" &\n\t\" 761 (BC_2, IO_AH30, output3, X, 760, 1, Z),\" & --  PAD287\n\t\" 762 (BC_2, IO_AH30, input, X),\" & --  PAD287\n\t\" 763 (BC_2, *, controlr, 1),\" &\n\t\" 764 (BC_2, IO_AG30, output3, X, 763, 1, Z),\" & --  PAD286\n\t\" 765 (BC_2, IO_AG30, input, X),\" & --  PAD286\n\t\" 766 (BC_2, *, controlr, 1),\" &\n\t\" 767 (BC_2, IO_AJ29, output3, X, 766, 1, Z),\" & --  PAD285\n\t\" 768 (BC_2, IO_AJ29, input, X),\" & --  PAD285\n\t\" 769 (BC_2, *, controlr, 1),\" &\n\t\" 770 (BC_2, IO_AJ28, output3, X, 769, 1, Z),\" & --  PAD284\n\t\" 771 (BC_2, IO_AJ28, input, X),\" & --  PAD284\n\t\" 772 (BC_2, *, controlr, 1),\" &\n\t\" 773 (BC_2, IO_AF30, output3, X, 772, 1, Z),\" & --  PAD283\n\t\" 774 (BC_2, IO_AF30, input, X),\" & --  PAD283\n\t\" 775 (BC_2, *, controlr, 1),\" &\n\t\" 776 (BC_2, IO_AE30, output3, X, 775, 1, Z),\" & --  PAD282\n\t\" 777 (BC_2, IO_AE30, input, X),\" & --  PAD282\n\t\" 778 (BC_2, *, controlr, 1),\" &\n\t\" 779 (BC_2, IO_AK30, output3, X, 778, 1, Z),\" & --  PAD281\n\t\" 780 (BC_2, IO_AK30, input, X),\" & --  PAD281\n\t\" 781 (BC_2, *, controlr, 1),\" &\n\t\" 782 (BC_2, IO_AK29, output3, X, 781, 1, Z),\" & --  PAD280\n\t\" 783 (BC_2, IO_AK29, input, X),\" & --  PAD280\n\t\" 784 (BC_2, *, controlr, 1),\" &\n\t\" 785 (BC_2, IO_AF28, output3, X, 784, 1, Z),\" & --  PAD279\n\t\" 786 (BC_2, IO_AF28, input, X),\" & --  PAD279\n\t\" 787 (BC_2, *, controlr, 1),\" &\n\t\" 788 (BC_2, IO_AE28, output3, X, 787, 1, Z),\" & --  PAD278\n\t\" 789 (BC_2, IO_AE28, input, X),\" & --  PAD278\n\t\" 790 (BC_2, *, controlr, 1),\" &\n\t\" 791 (BC_2, IO_AH29, output3, X, 790, 1, Z),\" & --  PAD277\n\t\" 792 (BC_2, IO_AH29, input, X),\" & --  PAD277\n\t\" 793 (BC_2, *, controlr, 1),\" &\n\t\" 794 (BC_2, IO_AG29, output3, X, 793, 1, Z),\" & --  PAD276\n\t\" 795 (BC_2, IO_AG29, input, X),\" & --  PAD276\n\t\" 796 (BC_2, *, controlr, 1),\" &\n\t\" 797 (BC_2, IO_AC27, output3, X, 796, 1, Z),\" & --  PAD275\n\t\" 798 (BC_2, IO_AC27, input, X),\" & --  PAD275\n\t\" 799 (BC_2, *, controlr, 1),\" &\n\t\" 800 (BC_2, IO_AB27, output3, X, 799, 1, Z),\" & --  PAD274\n\t\" 801 (BC_2, IO_AB27, input, X),\" & --  PAD274\n\t\" 802 (BC_2, *, controlr, 1),\" &\n\t\" 803 (BC_2, IO_AD28, output3, X, 802, 1, Z),\" & --  PAD273\n\t\" 804 (BC_2, IO_AD28, input, X),\" & --  PAD273\n\t\" 805 (BC_2, *, controlr, 1),\" &\n\t\" 806 (BC_2, IO_AD27, output3, X, 805, 1, Z),\" & --  PAD272\n\t\" 807 (BC_2, IO_AD27, input, X),\" & --  PAD272\n\t\" 808 (BC_2, *, controlr, 1),\" &\n\t\" 809 (BC_2, IO_AB30, output3, X, 808, 1, Z),\" & --  PAD271\n\t\" 810 (BC_2, IO_AB30, input, X),\" & --  PAD271\n\t\" 811 (BC_2, *, controlr, 1),\" &\n\t\" 812 (BC_2, IO_AB29, output3, X, 811, 1, Z),\" & --  PAD270\n\t\" 813 (BC_2, IO_AB29, input, X),\" & --  PAD270\n\t\" 814 (BC_2, *, controlr, 1),\" &\n\t\" 815 (BC_2, IO_AE29, output3, X, 814, 1, Z),\" & --  PAD269\n\t\" 816 (BC_2, IO_AE29, input, X),\" & --  PAD269\n\t\" 817 (BC_2, *, controlr, 1),\" &\n\t\" 818 (BC_2, IO_AD29, output3, X, 817, 1, Z),\" & --  PAD268\n\t\" 819 (BC_2, IO_AD29, input, X),\" & --  PAD268\n\t\" 820 (BC_2, *, controlr, 1),\" &\n\t\" 821 (BC_2, IO_AA30, output3, X, 820, 1, Z),\" & --  PAD267\n\t\" 822 (BC_2, IO_AA30, input, X),\" & --  PAD267\n\t\" 823 (BC_2, *, controlr, 1),\" &\n\t\" 824 (BC_2, IO_Y30, output3, X, 823, 1, Z),\" & --  PAD266\n\t\" 825 (BC_2, IO_Y30, input, X),\" & --  PAD266\n\t\" 826 (BC_2, *, controlr, 1),\" &\n\t\" 827 (BC_2, IO_AC30, output3, X, 826, 1, Z),\" & --  PAD265\n\t\" 828 (BC_2, IO_AC30, input, X),\" & --  PAD265\n\t\" 829 (BC_2, *, controlr, 1),\" &\n\t\" 830 (BC_2, IO_AC29, output3, X, 829, 1, Z),\" & --  PAD264\n\t\" 831 (BC_2, IO_AC29, input, X),\" & --  PAD264\n\t\" 832 (BC_2, *, controlr, 1),\" &\n\t\" 833 (BC_2, IO_AB25, output3, X, 832, 1, Z),\" & --  PAD263\n\t\" 834 (BC_2, IO_AB25, input, X),\" & --  PAD263\n\t\" 835 (BC_2, *, controlr, 1),\" &\n\t\" 836 (BC_2, IO_AA25, output3, X, 835, 1, Z),\" & --  PAD262\n\t\" 837 (BC_2, IO_AA25, input, X),\" & --  PAD262\n\t\" 838 (BC_2, *, controlr, 1),\" &\n\t\" 839 (BC_2, IO_AB28, output3, X, 838, 1, Z),\" & --  PAD261\n\t\" 840 (BC_2, IO_AB28, input, X),\" & --  PAD261\n\t\" 841 (BC_2, *, controlr, 1),\" &\n\t\" 842 (BC_2, IO_AA27, output3, X, 841, 1, Z),\" & --  PAD260\n\t\" 843 (BC_2, IO_AA27, input, X),\" & --  PAD260\n\t\" 844 (BC_2, *, controlr, 1),\" &\n\t\" 845 (BC_2, IO_Y29, output3, X, 844, 1, Z),\" & --  PAD259\n\t\" 846 (BC_2, IO_Y29, input, X),\" & --  PAD259\n\t\" 847 (BC_2, *, controlr, 1),\" &\n\t\" 848 (BC_2, IO_W29, output3, X, 847, 1, Z),\" & --  PAD258\n\t\" 849 (BC_2, IO_W29, input, X),\" & --  PAD258\n\t\" 850 (BC_2, *, controlr, 1),\" &\n\t\" 851 (BC_2, IO_AA28, output3, X, 850, 1, Z),\" & --  PAD257\n\t\" 852 (BC_2, IO_AA28, input, X),\" & --  PAD257\n\t\" 853 (BC_2, *, controlr, 1),\" &\n\t\" 854 (BC_2, IO_Y28, output3, X, 853, 1, Z),\" & --  PAD256\n\t\" 855 (BC_2, IO_Y28, input, X),\" & --  PAD256\n\t\" 856 (BC_2, *, controlr, 1),\" &\n\t\" 857 (BC_2, IO_W28, output3, X, 856, 1, Z),\" & --  PAD255\n\t\" 858 (BC_2, IO_W28, input, X),\" & --  PAD255\n\t\" 859 (BC_2, *, controlr, 1),\" &\n\t\" 860 (BC_2, IO_W27, output3, X, 859, 1, Z),\" & --  PAD254\n\t\" 861 (BC_2, IO_W27, input, X),\" & --  PAD254\n\t\" 862 (BC_2, *, controlr, 1),\" &\n\t\" 863 (BC_2, IO_AA26, output3, X, 862, 1, Z),\" & --  PAD253\n\t\" 864 (BC_2, IO_AA26, input, X),\" & --  PAD253\n\t\" 865 (BC_2, *, controlr, 1),\" &\n\t\" 866 (BC_2, IO_Y26, output3, X, 865, 1, Z),\" & --  PAD252\n\t\" 867 (BC_2, IO_Y26, input, X),\" & --  PAD252\n\t\" 868 (BC_2, *, controlr, 1),\" &\n\t\" 869 (BC_2, IO_Y25, output3, X, 868, 1, Z),\" & --  PAD251\n\t\" 870 (BC_2, IO_Y25, input, X),\" & --  PAD251\n\t\" 871 (BC_2, *, controlr, 1),\" &\n\t\" 872 (BC_2, IO_W19, output3, X, 871, 1, Z),\" & --  PAD250\n\t\" 873 (BC_2, IO_W19, input, X),\" & --  PAD250\n\t\" 874 (BC_2, *, controlr, 1),\" &\n\t\" 875 (BC_2, IO_W22, output3, X, 874, 1, Z),\" & --  PAD249\n\t\" 876 (BC_2, IO_W22, input, X),\" & --  PAD249\n\t\" 877 (BC_2, *, controlr, 1),\" &\n\t\" 878 (BC_2, IO_W21, output3, X, 877, 1, Z),\" & --  PAD248\n\t\" 879 (BC_2, IO_W21, input, X),\" & --  PAD248\n\t\" 880 (BC_2, *, controlr, 1),\" &\n\t\" 881 (BC_2, IO_V24, output3, X, 880, 1, Z),\" & --  PAD247\n\t\" 882 (BC_2, IO_V24, input, X),\" & --  PAD247\n\t\" 883 (BC_2, *, controlr, 1),\" &\n\t\" 884 (BC_2, IO_U24, output3, X, 883, 1, Z),\" & --  PAD246\n\t\" 885 (BC_2, IO_U24, input, X),\" & --  PAD246\n\t\" 886 (BC_2, *, controlr, 1),\" &\n\t\" 887 (BC_2, IO_V22, output3, X, 886, 1, Z),\" & --  PAD245\n\t\" 888 (BC_2, IO_V22, input, X),\" & --  PAD245\n\t\" 889 (BC_2, *, controlr, 1),\" &\n\t\" 890 (BC_2, IO_V21, output3, X, 889, 1, Z),\" & --  PAD244\n\t\" 891 (BC_2, IO_V21, input, X),\" & --  PAD244\n\t\" 892 (BC_2, *, controlr, 1),\" &\n\t\" 893 (BC_2, IO_U23, output3, X, 892, 1, Z),\" & --  PAD243\n\t\" 894 (BC_2, IO_U23, input, X),\" & --  PAD243\n\t\" 895 (BC_2, *, controlr, 1),\" &\n\t\" 896 (BC_2, IO_U22, output3, X, 895, 1, Z),\" & --  PAD242\n\t\" 897 (BC_2, IO_U22, input, X),\" & --  PAD242\n\t\" 898 (BC_2, *, controlr, 1),\" &\n\t\" 899 (BC_2, IO_W24, output3, X, 898, 1, Z),\" & --  PAD241\n\t\" 900 (BC_2, IO_W24, input, X),\" & --  PAD241\n\t\" 901 (BC_2, *, controlr, 1),\" &\n\t\" 902 (BC_2, IO_W23, output3, X, 901, 1, Z),\" & --  PAD240\n\t\" 903 (BC_2, IO_W23, input, X),\" & --  PAD240\n\t\" 904 (BC_2, *, controlr, 1),\" &\n\t\" 905 (BC_2, IO_V20, output3, X, 904, 1, Z),\" & --  PAD239\n\t\" 906 (BC_2, IO_V20, input, X),\" & --  PAD239\n\t\" 907 (BC_2, *, controlr, 1),\" &\n\t\" 908 (BC_2, IO_V19, output3, X, 907, 1, Z),\" & --  PAD238\n\t\" 909 (BC_2, IO_V19, input, X),\" & --  PAD238\n\t\" 910 (BC_2, *, controlr, 1),\" &\n\t\" 911 (BC_2, IO_W26, output3, X, 910, 1, Z),\" & --  PAD237\n\t\" 912 (BC_2, IO_W26, input, X),\" & --  PAD237\n\t\" 913 (BC_2, *, controlr, 1),\" &\n\t\" 914 (BC_2, IO_V25, output3, X, 913, 1, Z),\" & --  PAD236\n\t\" 915 (BC_2, IO_V25, input, X),\" & --  PAD236\n\t\" 916 (BC_2, *, controlr, 1),\" &\n\t\" 917 (BC_2, IO_V30, output3, X, 916, 1, Z),\" & --  PAD235\n\t\" 918 (BC_2, IO_V30, input, X),\" & --  PAD235\n\t\" 919 (BC_2, *, controlr, 1),\" &\n\t\" 920 (BC_2, IO_V29, output3, X, 919, 1, Z),\" & --  PAD234\n\t\" 921 (BC_2, IO_V29, input, X),\" & --  PAD234\n\t\" 922 (BC_2, *, controlr, 1),\" &\n\t\" 923 (BC_2, IO_V27, output3, X, 922, 1, Z),\" & --  PAD233\n\t\" 924 (BC_2, IO_V27, input, X),\" & --  PAD233\n\t\" 925 (BC_2, *, controlr, 1),\" &\n\t\" 926 (BC_2, IO_V26, output3, X, 925, 1, Z),\" & --  PAD232\n\t\" 927 (BC_2, IO_V26, input, X),\" & --  PAD232\n\t\" 928 (BC_2, *, controlr, 1),\" &\n\t\" 929 (BC_2, IO_U30, output3, X, 928, 1, Z),\" & --  PAD231\n\t\" 930 (BC_2, IO_U30, input, X),\" & --  PAD231\n\t\" 931 (BC_2, *, controlr, 1),\" &\n\t\" 932 (BC_2, IO_U29, output3, X, 931, 1, Z),\" & --  PAD230\n\t\" 933 (BC_2, IO_U29, input, X),\" & --  PAD230\n\t\" 934 (BC_2, *, controlr, 1),\" &\n\t\" 935 (BC_2, IO_U25, output3, X, 934, 1, Z),\" & --  PAD229\n\t\" 936 (BC_2, IO_U25, input, X),\" & --  PAD229\n\t\" 937 (BC_2, *, controlr, 1),\" &\n\t\" 938 (BC_2, IO_T25, output3, X, 937, 1, Z),\" & --  PAD228\n\t\" 939 (BC_2, IO_T25, input, X),\" & --  PAD228\n\t\" 940 (BC_2, *, controlr, 1),\" &\n\t\" 941 (BC_2, IO_U28, output3, X, 940, 1, Z),\" & --  PAD227\n\t\" 942 (BC_2, IO_U28, input, X),\" & --  PAD227\n\t\" 943 (BC_2, *, controlr, 1),\" &\n\t\" 944 (BC_2, IO_U27, output3, X, 943, 1, Z),\" & --  PAD226\n\t\" 945 (BC_2, IO_U27, input, X),\" & --  PAD226\n\t\" 946 (BC_2, *, controlr, 1),\" &\n\t\" 947 (BC_2, IO_T27, output3, X, 946, 1, Z),\" & --  PAD225\n\t\" 948 (BC_2, IO_T27, input, X),\" & --  PAD225\n\t\" 949 (BC_2, *, controlr, 1),\" &\n\t\" 950 (BC_2, IO_T26, output3, X, 949, 1, Z),\" & --  PAD224\n\t\" 951 (BC_2, IO_T26, input, X),\" & --  PAD224\n\t\" 952 (BC_2, *, controlr, 1),\" &\n\t\" 953 (BC_2, IO_T28, output3, X, 952, 1, Z),\" & --  PAD223\n\t\" 954 (BC_2, IO_T28, input, X),\" & --  PAD223\n\t\" 955 (BC_2, *, controlr, 1),\" &\n\t\" 956 (BC_2, IO_R28, output3, X, 955, 1, Z),\" & --  PAD222\n\t\" 957 (BC_2, IO_R28, input, X),\" & --  PAD222\n\t\" 958 (BC_2, *, controlr, 1),\" &\n\t\" 959 (BC_2, IO_R26, output3, X, 958, 1, Z),\" & --  PAD221\n\t\" 960 (BC_2, IO_R26, input, X),\" & --  PAD221\n\t\" 961 (BC_2, *, controlr, 1),\" &\n\t\" 962 (BC_2, IO_P26, output3, X, 961, 1, Z),\" & --  PAD220\n\t\" 963 (BC_2, IO_P26, input, X),\" & --  PAD220\n\t\" 964 (BC_2, *, controlr, 1),\" &\n\t\" 965 (BC_2, IO_T30, output3, X, 964, 1, Z),\" & --  PAD219\n\t\" 966 (BC_2, IO_T30, input, X),\" & --  PAD219\n\t\" 967 (BC_2, *, controlr, 1),\" &\n\t\" 968 (BC_2, IO_R30, output3, X, 967, 1, Z),\" & --  PAD218\n\t\" 969 (BC_2, IO_R30, input, X),\" & --  PAD218\n\t\" 970 (BC_2, *, controlr, 1),\" &\n\t\" 971 (BC_2, IO_P28, output3, X, 970, 1, Z),\" & --  PAD217\n\t\" 972 (BC_2, IO_P28, input, X),\" & --  PAD217\n\t\" 973 (BC_2, *, controlr, 1),\" &\n\t\" 974 (BC_2, IO_P27, output3, X, 973, 1, Z),\" & --  PAD216\n\t\" 975 (BC_2, IO_P27, input, X),\" & --  PAD216\n\t\" 976 (BC_2, *, controlr, 1),\" &\n\t\" 977 (BC_2, IO_R29, output3, X, 976, 1, Z),\" & --  PAD215\n\t\" 978 (BC_2, IO_R29, input, X),\" & --  PAD215\n\t\" 979 (BC_2, *, controlr, 1),\" &\n\t\" 980 (BC_2, IO_P29, output3, X, 979, 1, Z),\" & --  PAD214\n\t\" 981 (BC_2, IO_P29, input, X),\" & --  PAD214\n\t\" 982 (BC_2, *, controlr, 1),\" &\n\t\" 983 (BC_2, IO_U20, output3, X, 982, 1, Z),\" & --  PAD213\n\t\" 984 (BC_2, IO_U20, input, X),\" & --  PAD213\n\t\" 985 (BC_2, *, controlr, 1),\" &\n\t\" 986 (BC_2, IO_U19, output3, X, 985, 1, Z),\" & --  PAD212\n\t\" 987 (BC_2, IO_U19, input, X),\" & --  PAD212\n\t\" 988 (BC_2, *, controlr, 1),\" &\n\t\" 989 (BC_2, IO_T23, output3, X, 988, 1, Z),\" & --  PAD211\n\t\" 990 (BC_2, IO_T23, input, X),\" & --  PAD211\n\t\" 991 (BC_2, *, controlr, 1),\" &\n\t\" 992 (BC_2, IO_T22, output3, X, 991, 1, Z),\" & --  PAD210\n\t\" 993 (BC_2, IO_T22, input, X),\" & --  PAD210\n\t\" 994 (BC_2, *, controlr, 1),\" &\n\t\" 995 (BC_2, IO_T21, output3, X, 994, 1, Z),\" & --  PAD209\n\t\" 996 (BC_2, IO_T21, input, X),\" & --  PAD209\n\t\" 997 (BC_2, *, controlr, 1),\" &\n\t\" 998 (BC_2, IO_T20, output3, X, 997, 1, Z),\" & --  PAD208\n\t\" 999 (BC_2, IO_T20, input, X),\" & --  PAD208\n\t\"1000 (BC_2, *, controlr, 1),\" &\n\t\"1001 (BC_2, IO_R24, output3, X, 1000, 1, Z),\" & --  PAD207\n\t\"1002 (BC_2, IO_R24, input, X),\" & --  PAD207\n\t\"1003 (BC_2, *, controlr, 1),\" &\n\t\"1004 (BC_2, IO_R23, output3, X, 1003, 1, Z),\" & --  PAD206\n\t\"1005 (BC_2, IO_R23, input, X),\" & --  PAD206\n\t\"1006 (BC_2, *, controlr, 1),\" &\n\t\"1007 (BC_2, IO_R21, output3, X, 1006, 1, Z),\" & --  PAD205\n\t\"1008 (BC_2, IO_R21, input, X),\" & --  PAD205\n\t\"1009 (BC_2, *, controlr, 1),\" &\n\t\"1010 (BC_2, IO_R20, output3, X, 1009, 1, Z),\" & --  PAD204\n\t\"1011 (BC_2, IO_R20, input, X),\" & --  PAD204\n\t\"1012 (BC_2, *, controlr, 1),\" &\n\t\"1013 (BC_2, IO_R25, output3, X, 1012, 1, Z),\" & --  PAD203\n\t\"1014 (BC_2, IO_R25, input, X),\" & --  PAD203\n\t\"1015 (BC_2, *, controlr, 1),\" &\n\t\"1016 (BC_2, IO_P24, output3, X, 1015, 1, Z),\" & --  PAD202\n\t\"1017 (BC_2, IO_P24, input, X),\" & --  PAD202\n\t\"1018 (BC_2, *, controlr, 1),\" &\n\t\"1019 (BC_2, IO_R19, output3, X, 1018, 1, Z),\" & --  PAD201\n\t\"1020 (BC_2, IO_R19, input, X),\" & --  PAD201\n\t\"1021 (BC_2, *, controlr, 1),\" &\n\t\"1022 (BC_2, IO_P19, output3, X, 1021, 1, Z),\" & --  PAD200\n\t\"1023 (BC_2, IO_P19, input, X),\" & --  PAD200\n\t\"1024 (BC_2, *, controlr, 1),\" &\n\t\"1025 (BC_2, IO_M23, output3, X, 1024, 1, Z),\" & --  PAD199\n\t\"1026 (BC_2, IO_M23, input, X),\" & --  PAD199\n\t\"1027 (BC_2, *, controlr, 1),\" &\n\t\"1028 (BC_2, IO_M22, output3, X, 1027, 1, Z),\" & --  PAD198\n\t\"1029 (BC_2, IO_M22, input, X),\" & --  PAD198\n\t\"1030 (BC_2, *, controlr, 1),\" &\n\t\"1031 (BC_2, IO_M25, output3, X, 1030, 1, Z),\" & --  PAD197\n\t\"1032 (BC_2, IO_M25, input, X),\" & --  PAD197\n\t\"1033 (BC_2, *, controlr, 1),\" &\n\t\"1034 (BC_2, IO_M24, output3, X, 1033, 1, Z),\" & --  PAD196\n\t\"1035 (BC_2, IO_M24, input, X),\" & --  PAD196\n\t\"1036 (BC_2, *, controlr, 1),\" &\n\t\"1037 (BC_2, IO_P22, output3, X, 1036, 1, Z),\" & --  PAD195\n\t\"1038 (BC_2, IO_P22, input, X),\" & --  PAD195\n\t\"1039 (BC_2, *, controlr, 1),\" &\n\t\"1040 (BC_2, IO_P21, output3, X, 1039, 1, Z),\" & --  PAD194\n\t\"1041 (BC_2, IO_P21, input, X),\" & --  PAD194\n\t\"1042 (BC_2, *, controlr, 1),\" &\n\t\"1043 (BC_2, IO_N24, output3, X, 1042, 1, Z),\" & --  PAD193\n\t\"1044 (BC_2, IO_N24, input, X),\" & --  PAD193\n\t\"1045 (BC_2, *, controlr, 1),\" &\n\t\"1046 (BC_2, IO_P23, output3, X, 1045, 1, Z),\" & --  PAD192\n\t\"1047 (BC_2, IO_P23, input, X),\" & --  PAD192\n\t\"1048 (BC_2, *, controlr, 1),\" &\n\t\"1049 (BC_2, IO_N22, output3, X, 1048, 1, Z),\" & --  PAD191\n\t\"1050 (BC_2, IO_N22, input, X),\" & --  PAD191\n\t\"1051 (BC_2, *, controlr, 1),\" &\n\t\"1052 (BC_2, IO_N21, output3, X, 1051, 1, Z),\" & --  PAD190\n\t\"1053 (BC_2, IO_N21, input, X),\" & --  PAD190\n\t\"1054 (BC_2, *, controlr, 1),\" &\n\t\"1055 (BC_2, IO_N20, output3, X, 1054, 1, Z),\" & --  PAD189\n\t\"1056 (BC_2, IO_N20, input, X),\" & --  PAD189\n\t\"1057 (BC_2, *, controlr, 1),\" &\n\t\"1058 (BC_2, IO_N19, output3, X, 1057, 1, Z),\" & --  PAD188\n\t\"1059 (BC_2, IO_N19, input, X),\" & --  PAD188\n\t\"1060 (BC_2, *, controlr, 1),\" &\n\t\"1061 (BC_2, IO_N26, output3, X, 1060, 1, Z),\" & --  PAD187\n\t\"1062 (BC_2, IO_N26, input, X),\" & --  PAD187\n\t\"1063 (BC_2, *, controlr, 1),\" &\n\t\"1064 (BC_2, IO_N25, output3, X, 1063, 1, Z),\" & --  PAD186\n\t\"1065 (BC_2, IO_N25, input, X),\" & --  PAD186\n\t\"1066 (BC_2, *, controlr, 1),\" &\n\t\"1067 (BC_2, IO_N30, output3, X, 1066, 1, Z),\" & --  PAD185\n\t\"1068 (BC_2, IO_N30, input, X),\" & --  PAD185\n\t\"1069 (BC_2, *, controlr, 1),\" &\n\t\"1070 (BC_2, IO_N29, output3, X, 1069, 1, Z),\" & --  PAD184\n\t\"1071 (BC_2, IO_N29, input, X),\" & --  PAD184\n\t\"1072 (BC_2, *, controlr, 1),\" &\n\t\"1073 (BC_2, IO_M27, output3, X, 1072, 1, Z),\" & --  PAD183\n\t\"1074 (BC_2, IO_M27, input, X),\" & --  PAD183\n\t\"1075 (BC_2, *, controlr, 1),\" &\n\t\"1076 (BC_2, IO_N27, output3, X, 1075, 1, Z),\" & --  PAD182\n\t\"1077 (BC_2, IO_N27, input, X),\" & --  PAD182\n\t\"1078 (BC_2, *, controlr, 1),\" &\n\t\"1079 (BC_2, IO_M30, output3, X, 1078, 1, Z),\" & --  PAD181\n\t\"1080 (BC_2, IO_M30, input, X),\" & --  PAD181\n\t\"1081 (BC_2, *, controlr, 1),\" &\n\t\"1082 (BC_2, IO_M29, output3, X, 1081, 1, Z),\" & --  PAD180\n\t\"1083 (BC_2, IO_M29, input, X),\" & --  PAD180\n\t\"1084 (BC_2, *, controlr, 1),\" &\n\t\"1085 (BC_2, IO_L28, output3, X, 1084, 1, Z),\" & --  PAD179\n\t\"1086 (BC_2, IO_L28, input, X),\" & --  PAD179\n\t\"1087 (BC_2, *, controlr, 1),\" &\n\t\"1088 (BC_2, IO_M28, output3, X, 1087, 1, Z),\" & --  PAD178\n\t\"1089 (BC_2, IO_M28, input, X),\" & --  PAD178\n\t\"1090 (BC_2, *, controlr, 1),\" &\n\t\"1091 (BC_2, IO_K29, output3, X, 1090, 1, Z),\" & --  PAD177\n\t\"1092 (BC_2, IO_K29, input, X),\" & --  PAD177\n\t\"1093 (BC_2, *, controlr, 1),\" &\n\t\"1094 (BC_2, IO_K28, output3, X, 1093, 1, Z),\" & --  PAD176\n\t\"1095 (BC_2, IO_K28, input, X),\" & --  PAD176\n\t\"1096 (BC_2, *, controlr, 1),\" &\n\t\"1097 (BC_2, IO_K25, output3, X, 1096, 1, Z),\" & --  PAD175\n\t\"1098 (BC_2, IO_K25, input, X),\" & --  PAD175\n\t\"1099 (BC_2, *, controlr, 1),\" &\n\t\"1100 (BC_2, IO_L25, output3, X, 1099, 1, Z),\" & --  PAD174\n\t\"1101 (BC_2, IO_L25, input, X),\" & --  PAD174\n\t\"1102 (BC_2, *, controlr, 1),\" &\n\t\"1103 (BC_2, IO_L27, output3, X, 1102, 1, Z),\" & --  PAD173\n\t\"1104 (BC_2, IO_L27, input, X),\" & --  PAD173\n\t\"1105 (BC_2, *, controlr, 1),\" &\n\t\"1106 (BC_2, IO_L26, output3, X, 1105, 1, Z),\" & --  PAD172\n\t\"1107 (BC_2, IO_L26, input, X),\" & --  PAD172\n\t\"1108 (BC_2, *, controlr, 1),\" &\n\t\"1109 (BC_2, IO_J26, output3, X, 1108, 1, Z),\" & --  PAD171\n\t\"1110 (BC_2, IO_J26, input, X),\" & --  PAD171\n\t\"1111 (BC_2, *, controlr, 1),\" &\n\t\"1112 (BC_2, IO_K26, output3, X, 1111, 1, Z),\" & --  PAD170\n\t\"1113 (BC_2, IO_K26, input, X),\" & --  PAD170\n\t\"1114 (BC_2, *, controlr, 1),\" &\n\t\"1115 (BC_2, IO_K30, output3, X, 1114, 1, Z),\" & --  PAD169\n\t\"1116 (BC_2, IO_K30, input, X),\" & --  PAD169\n\t\"1117 (BC_2, *, controlr, 1),\" &\n\t\"1118 (BC_2, IO_L30, output3, X, 1117, 1, Z),\" & --  PAD168\n\t\"1119 (BC_2, IO_L30, input, X),\" & --  PAD168\n\t\"1120 (BC_2, *, controlr, 1),\" &\n\t\"1121 (BC_2, IO_J28, output3, X, 1120, 1, Z),\" & --  PAD167\n\t\"1122 (BC_2, IO_J28, input, X),\" & --  PAD167\n\t\"1123 (BC_2, *, controlr, 1),\" &\n\t\"1124 (BC_2, IO_J27, output3, X, 1123, 1, Z),\" & --  PAD166\n\t\"1125 (BC_2, IO_J27, input, X),\" & --  PAD166\n\t\"1126 (BC_2, *, controlr, 1),\" &\n\t\"1127 (BC_2, IO_H29, output3, X, 1126, 1, Z),\" & --  PAD165\n\t\"1128 (BC_2, IO_H29, input, X),\" & --  PAD165\n\t\"1129 (BC_2, *, controlr, 1),\" &\n\t\"1130 (BC_2, IO_J29, output3, X, 1129, 1, Z),\" & --  PAD164\n\t\"1131 (BC_2, IO_J29, input, X),\" & --  PAD164\n\t\"1132 (BC_2, *, controlr, 1),\" &\n\t\"1133 (BC_2, IO_L20, output3, X, 1132, 1, Z),\" & --  PAD163\n\t\"1134 (BC_2, IO_L20, input, X),\" & --  PAD163\n\t\"1135 (BC_2, *, controlr, 1),\" &\n\t\"1136 (BC_2, IO_M20, output3, X, 1135, 1, Z),\" & --  PAD162\n\t\"1137 (BC_2, IO_M20, input, X),\" & --  PAD162\n\t\"1138 (BC_2, *, controlr, 1),\" &\n\t\"1139 (BC_2, IO_J22, output3, X, 1138, 1, Z),\" & --  PAD161\n\t\"1140 (BC_2, IO_J22, input, X),\" & --  PAD161\n\t\"1141 (BC_2, *, controlr, 1),\" &\n\t\"1142 (BC_2, IO_J21, output3, X, 1141, 1, Z),\" & --  PAD160\n\t\"1143 (BC_2, IO_J21, input, X),\" & --  PAD160\n\t\"1144 (BC_2, *, controlr, 1),\" &\n\t\"1145 (BC_2, IO_K21, output3, X, 1144, 1, Z),\" & --  PAD159\n\t\"1146 (BC_2, IO_K21, input, X),\" & --  PAD159\n\t\"1147 (BC_2, *, controlr, 1),\" &\n\t\"1148 (BC_2, IO_L21, output3, X, 1147, 1, Z),\" & --  PAD158\n\t\"1149 (BC_2, IO_L21, input, X),\" & --  PAD158\n\t\"1150 (BC_2, *, controlr, 1),\" &\n\t\"1151 (BC_2, IO_K24, output3, X, 1150, 1, Z),\" & --  PAD157\n\t\"1152 (BC_2, IO_K24, input, X),\" & --  PAD157\n\t\"1153 (BC_2, *, controlr, 1),\" &\n\t\"1154 (BC_2, IO_K23, output3, X, 1153, 1, Z),\" & --  PAD156\n\t\"1155 (BC_2, IO_K23, input, X),\" & --  PAD156\n\t\"1156 (BC_2, *, controlr, 1),\" &\n\t\"1157 (BC_2, IO_L23, output3, X, 1156, 1, Z),\" & --  PAD155\n\t\"1158 (BC_2, IO_L23, input, X),\" & --  PAD155\n\t\"1159 (BC_2, *, controlr, 1),\" &\n\t\"1160 (BC_2, IO_L22, output3, X, 1159, 1, Z),\" & --  PAD154\n\t\"1161 (BC_2, IO_L22, input, X),\" & --  PAD154\n\t\"1162 (BC_2, *, controlr, 1),\" &\n\t\"1163 (BC_2, IO_J24, output3, X, 1162, 1, Z),\" & --  PAD153\n\t\"1164 (BC_2, IO_J24, input, X),\" & --  PAD153\n\t\"1165 (BC_2, *, controlr, 1),\" &\n\t\"1166 (BC_2, IO_J23, output3, X, 1165, 1, Z),\" & --  PAD152\n\t\"1167 (BC_2, IO_J23, input, X),\" & --  PAD152\n\t\"1168 (BC_2, *, controlr, 1),\" &\n\t\"1169 (BC_2, IO_M19, output3, X, 1168, 1, Z),\" & --  PAD151\n\t\"1170 (BC_2, IO_M19, input, X),\" & --  PAD151\n\t\"1171 (BC_2, *, controlr, 1),\" &\n\t\"1172 (BC_2, IO_G25, output3, X, 1171, 1, Z),\" & --  PAD150\n\t\"1173 (BC_2, IO_G25, input, X),\" & --  PAD150\n\t\"1174 (BC_2, *, controlr, 1),\" &\n\t\"1175 (BC_2, IO_G30, output3, X, 1174, 1, Z),\" & --  PAD149\n\t\"1176 (BC_2, IO_G30, input, X),\" & --  PAD149\n\t\"1177 (BC_2, *, controlr, 1),\" &\n\t\"1178 (BC_2, IO_H30, output3, X, 1177, 1, Z),\" & --  PAD148\n\t\"1179 (BC_2, IO_H30, input, X),\" & --  PAD148\n\t\"1180 (BC_2, *, controlr, 1),\" &\n\t\"1181 (BC_2, IO_H27, output3, X, 1180, 1, Z),\" & --  PAD147\n\t\"1182 (BC_2, IO_H27, input, X),\" & --  PAD147\n\t\"1183 (BC_2, *, controlr, 1),\" &\n\t\"1184 (BC_2, IO_H26, output3, X, 1183, 1, Z),\" & --  PAD146\n\t\"1185 (BC_2, IO_H26, input, X),\" & --  PAD146\n\t\"1186 (BC_2, *, controlr, 1),\" &\n\t\"1187 (BC_2, IO_F30, output3, X, 1186, 1, Z),\" & --  PAD145\n\t\"1188 (BC_2, IO_F30, input, X),\" & --  PAD145\n\t\"1189 (BC_2, *, controlr, 1),\" &\n\t\"1190 (BC_2, IO_G29, output3, X, 1189, 1, Z),\" & --  PAD144\n\t\"1191 (BC_2, IO_G29, input, X),\" & --  PAD144\n\t\"1192 (BC_2, *, controlr, 1),\" &\n\t\"1193 (BC_2, IO_F27, output3, X, 1192, 1, Z),\" & --  PAD143\n\t\"1194 (BC_2, IO_F27, input, X),\" & --  PAD143\n\t\"1195 (BC_2, *, controlr, 1),\" &\n\t\"1196 (BC_2, IO_G27, output3, X, 1195, 1, Z),\" & --  PAD142\n\t\"1197 (BC_2, IO_G27, input, X),\" & --  PAD142\n\t\"1198 (BC_2, *, controlr, 1),\" &\n\t\"1199 (BC_2, IO_F28, output3, X, 1198, 1, Z),\" & --  PAD141\n\t\"1200 (BC_2, IO_F28, input, X),\" & --  PAD141\n\t\"1201 (BC_2, *, controlr, 1),\" &\n\t\"1202 (BC_2, IO_G28, output3, X, 1201, 1, Z),\" & --  PAD140\n\t\"1203 (BC_2, IO_G28, input, X),\" & --  PAD140\n\t\"1204 (BC_2, *, controlr, 1),\" &\n\t\"1205 (BC_2, IO_H25, output3, X, 1204, 1, Z),\" & --  PAD139\n\t\"1206 (BC_2, IO_H25, input, X),\" & --  PAD139\n\t\"1207 (BC_2, *, controlr, 1),\" &\n\t\"1208 (BC_2, IO_H24, output3, X, 1207, 1, Z),\" & --  PAD138\n\t\"1209 (BC_2, IO_H24, input, X),\" & --  PAD138\n\t\"1210 (BC_2, *, controlr, 1),\" &\n\t\"1211 (BC_2, IO_E30, output3, X, 1210, 1, Z),\" & --  PAD137\n\t\"1212 (BC_2, IO_E30, input, X),\" & --  PAD137\n\t\"1213 (BC_2, *, controlr, 1),\" &\n\t\"1214 (BC_2, IO_E29, output3, X, 1213, 1, Z),\" & --  PAD136\n\t\"1215 (BC_2, IO_E29, input, X),\" & --  PAD136\n\t\"1216 (BC_2, *, controlr, 1),\" &\n\t\"1217 (BC_2, IO_A30, output3, X, 1216, 1, Z),\" & --  PAD135\n\t\"1218 (BC_2, IO_A30, input, X),\" & --  PAD135\n\t\"1219 (BC_2, *, controlr, 1),\" &\n\t\"1220 (BC_2, IO_B30, output3, X, 1219, 1, Z),\" & --  PAD134\n\t\"1221 (BC_2, IO_B30, input, X),\" & --  PAD134\n\t\"1222 (BC_2, *, controlr, 1),\" &\n\t\"1223 (BC_2, IO_C30, output3, X, 1222, 1, Z),\" & --  PAD133\n\t\"1224 (BC_2, IO_C30, input, X),\" & --  PAD133\n\t\"1225 (BC_2, *, controlr, 1),\" &\n\t\"1226 (BC_2, IO_D29, output3, X, 1225, 1, Z),\" & --  PAD132\n\t\"1227 (BC_2, IO_D29, input, X),\" & --  PAD132\n\t\"1228 (BC_2, *, controlr, 1),\" &\n\t\"1229 (BC_2, IO_B29, output3, X, 1228, 1, Z),\" & --  PAD131\n\t\"1230 (BC_2, IO_B29, input, X),\" & --  PAD131\n\t\"1231 (BC_2, *, controlr, 1),\" &\n\t\"1232 (BC_2, IO_C29, output3, X, 1231, 1, Z),\" & --  PAD130\n\t\"1233 (BC_2, IO_C29, input, X),\" & --  PAD130\n\t\"1234 (BC_2, *, controlr, 1),\" &\n\t\"1235 (BC_2, IO_D28, output3, X, 1234, 1, Z),\" & --  PAD129\n\t\"1236 (BC_2, IO_D28, input, X),\" & --  PAD129\n\t\"1237 (BC_2, *, controlr, 1),\" &\n\t\"1238 (BC_2, IO_E28, output3, X, 1237, 1, Z),\" & --  PAD128\n\t\"1239 (BC_2, IO_E28, input, X),\" & --  PAD128\n\t\"1240 (BC_2, *, controlr, 1),\" &\n\t\"1241 (BC_2, IO_C27, output3, X, 1240, 1, Z),\" & --  PAD127\n\t\"1242 (BC_2, IO_C27, input, X),\" & --  PAD127\n\t\"1243 (BC_2, *, controlr, 1),\" &\n\t\"1244 (BC_2, IO_D27, output3, X, 1243, 1, Z),\" & --  PAD126\n\t\"1245 (BC_2, IO_D27, input, X),\" & --  PAD126\n\t\"1246 (BC_2, *, controlr, 1),\" &\n\t\"1247 (BC_2, IO_B25, output3, X, 1246, 1, Z),\" & --  PAD125\n\t\"1248 (BC_2, IO_B25, input, X),\" & --  PAD125\n\t\"1249 (BC_2, *, controlr, 1),\" &\n\t\"1250 (BC_2, IO_C25, output3, X, 1249, 1, Z),\" & --  PAD124\n\t\"1251 (BC_2, IO_C25, input, X),\" & --  PAD124\n\t\"1252 (BC_2, *, controlr, 1),\" &\n\t\"1253 (BC_2, IO_C26, output3, X, 1252, 1, Z),\" & --  PAD123\n\t\"1254 (BC_2, IO_C26, input, X),\" & --  PAD123\n\t\"1255 (BC_2, *, controlr, 1),\" &\n\t\"1256 (BC_2, IO_D26, output3, X, 1255, 1, Z),\" & --  PAD122\n\t\"1257 (BC_2, IO_D26, input, X),\" & --  PAD122\n\t\"1258 (BC_2, *, controlr, 1),\" &\n\t\"1259 (BC_2, IO_A26, output3, X, 1258, 1, Z),\" & --  PAD121\n\t\"1260 (BC_2, IO_A26, input, X),\" & --  PAD121\n\t\"1261 (BC_2, *, controlr, 1),\" &\n\t\"1262 (BC_2, IO_A25, output3, X, 1261, 1, Z),\" & --  PAD120\n\t\"1263 (BC_2, IO_A25, input, X),\" & --  PAD120\n\t\"1264 (BC_2, *, controlr, 1),\" &\n\t\"1265 (BC_2, IO_A28, output3, X, 1264, 1, Z),\" & --  PAD119\n\t\"1266 (BC_2, IO_A28, input, X),\" & --  PAD119\n\t\"1267 (BC_2, *, controlr, 1),\" &\n\t\"1268 (BC_2, IO_B28, output3, X, 1267, 1, Z),\" & --  PAD118\n\t\"1269 (BC_2, IO_B28, input, X),\" & --  PAD118\n\t\"1270 (BC_2, *, controlr, 1),\" &\n\t\"1271 (BC_2, IO_B24, output3, X, 1270, 1, Z),\" & --  PAD117\n\t\"1272 (BC_2, IO_B24, input, X),\" & --  PAD117\n\t\"1273 (BC_2, *, controlr, 1),\" &\n\t\"1274 (BC_2, IO_C24, output3, X, 1273, 1, Z),\" & --  PAD116\n\t\"1275 (BC_2, IO_C24, input, X),\" & --  PAD116\n\t\"1276 (BC_2, *, controlr, 1),\" &\n\t\"1277 (BC_2, IO_A27, output3, X, 1276, 1, Z),\" & --  PAD115\n\t\"1278 (BC_2, IO_A27, input, X),\" & --  PAD115\n\t\"1279 (BC_2, *, controlr, 1),\" &\n\t\"1280 (BC_2, IO_B27, output3, X, 1279, 1, Z),\" & --  PAD114\n\t\"1281 (BC_2, IO_B27, input, X),\" & --  PAD114\n\t\"1282 (BC_2, *, controlr, 1),\" &\n\t\"1283 (BC_2, IO_G24, output3, X, 1282, 1, Z),\" & --  PAD113\n\t\"1284 (BC_2, IO_G24, input, X),\" & --  PAD113\n\t\"1285 (BC_2, *, controlr, 1),\" &\n\t\"1286 (BC_2, IO_G23, output3, X, 1285, 1, Z),\" & --  PAD112\n\t\"1287 (BC_2, IO_G23, input, X),\" & --  PAD112\n\t\"1288 (BC_2, *, controlr, 1),\" &\n\t\"1289 (BC_2, IO_E26, output3, X, 1288, 1, Z),\" & --  PAD111\n\t\"1290 (BC_2, IO_E26, input, X),\" & --  PAD111\n\t\"1291 (BC_2, *, controlr, 1),\" &\n\t\"1292 (BC_2, IO_F26, output3, X, 1291, 1, Z),\" & --  PAD110\n\t\"1293 (BC_2, IO_F26, input, X),\" & --  PAD110\n\t\"1294 (BC_2, *, controlr, 1),\" &\n\t\"1295 (BC_2, IO_D24, output3, X, 1294, 1, Z),\" & --  PAD109\n\t\"1296 (BC_2, IO_D24, input, X),\" & --  PAD109\n\t\"1297 (BC_2, *, controlr, 1),\" &\n\t\"1298 (BC_2, IO_E24, output3, X, 1297, 1, Z),\" & --  PAD108\n\t\"1299 (BC_2, IO_E24, input, X),\" & --  PAD108\n\t\"1300 (BC_2, *, controlr, 1),\" &\n\t\"1301 (BC_2, IO_E25, output3, X, 1300, 1, Z),\" & --  PAD107\n\t\"1302 (BC_2, IO_E25, input, X),\" & --  PAD107\n\t\"1303 (BC_2, *, controlr, 1),\" &\n\t\"1304 (BC_2, IO_F25, output3, X, 1303, 1, Z),\" & --  PAD106\n\t\"1305 (BC_2, IO_F25, input, X),\" & --  PAD106\n\t\"1306 (BC_2, *, controlr, 1),\" &\n\t\"1307 (BC_2, IO_D23, output3, X, 1306, 1, Z),\" & --  PAD105\n\t\"1308 (BC_2, IO_D23, input, X),\" & --  PAD105\n\t\"1309 (BC_2, *, controlr, 1),\" &\n\t\"1310 (BC_2, IO_E23, output3, X, 1309, 1, Z),\" & --  PAD104\n\t\"1311 (BC_2, IO_E23, input, X),\" & --  PAD104\n\t\"1312 (BC_2, *, controlr, 1),\" &\n\t\"1313 (BC_2, IO_A23, output3, X, 1312, 1, Z),\" & --  PAD103\n\t\"1314 (BC_2, IO_A23, input, X),\" & --  PAD103\n\t\"1315 (BC_2, *, controlr, 1),\" &\n\t\"1316 (BC_2, IO_B23, output3, X, 1315, 1, Z),\" & --  PAD102\n\t\"1317 (BC_2, IO_B23, input, X),\" & --  PAD102\n\t\"1318 (BC_2, *, controlr, 1),\" &\n\t\"1319 (BC_2, IO_F23, output3, X, 1318, 1, Z),\" & --  PAD101\n\t\"1320 (BC_2, IO_F23, input, X),\" & --  PAD101\n\t\"1321 (BC_2, *, controlr, 1),\" &\n\t\"1322 (BC_2, IO_E18, output3, X, 1321, 1, Z),\" & --  PAD100\n\t\"1323 (BC_2, IO_E18, input, X),\" & --  PAD100\n\t\"1324 (BC_2, *, controlr, 1),\" &\n\t\"1325 (BC_2, IO_B19, output3, X, 1324, 1, Z),\" & --  PAD99\n\t\"1326 (BC_2, IO_B19, input, X),\" & --  PAD99\n\t\"1327 (BC_2, *, controlr, 1),\" &\n\t\"1328 (BC_2, IO_C19, output3, X, 1327, 1, Z),\" & --  PAD98\n\t\"1329 (BC_2, IO_C19, input, X),\" & --  PAD98\n\t\"1330 (BC_2, *, controlr, 1),\" &\n\t\"1331 (BC_2, IO_A22, output3, X, 1330, 1, Z),\" & --  PAD97\n\t\"1332 (BC_2, IO_A22, input, X),\" & --  PAD97\n\t\"1333 (BC_2, *, controlr, 1),\" &\n\t\"1334 (BC_2, IO_B22, output3, X, 1333, 1, Z),\" & --  PAD96\n\t\"1335 (BC_2, IO_B22, input, X),\" & --  PAD96\n\t\"1336 (BC_2, *, controlr, 1),\" &\n\t\"1337 (BC_2, IO_A18, output3, X, 1336, 1, Z),\" & --  PAD95\n\t\"1338 (BC_2, IO_A18, input, X),\" & --  PAD95\n\t\"1339 (BC_2, *, controlr, 1),\" &\n\t\"1340 (BC_2, IO_B18, output3, X, 1339, 1, Z),\" & --  PAD94\n\t\"1341 (BC_2, IO_B18, input, X),\" & --  PAD94\n\t\"1342 (BC_2, *, controlr, 1),\" &\n\t\"1343 (BC_2, IO_A21, output3, X, 1342, 1, Z),\" & --  PAD93\n\t\"1344 (BC_2, IO_A21, input, X),\" & --  PAD93\n\t\"1345 (BC_2, *, controlr, 1),\" &\n\t\"1346 (BC_2, IO_A20, output3, X, 1345, 1, Z),\" & --  PAD92\n\t\"1347 (BC_2, IO_A20, input, X),\" & --  PAD92\n\t\"1348 (BC_2, *, controlr, 1),\" &\n\t\"1349 (BC_2, IO_A17, output3, X, 1348, 1, Z),\" & --  PAD91\n\t\"1350 (BC_2, IO_A17, input, X),\" & --  PAD91\n\t\"1351 (BC_2, *, controlr, 1),\" &\n\t\"1352 (BC_2, IO_A16, output3, X, 1351, 1, Z),\" & --  PAD90\n\t\"1353 (BC_2, IO_A16, input, X),\" & --  PAD90\n\t\"1354 (BC_2, *, controlr, 1),\" &\n\t\"1355 (BC_2, IO_B20, output3, X, 1354, 1, Z),\" & --  PAD89\n\t\"1356 (BC_2, IO_B20, input, X),\" & --  PAD89\n\t\"1357 (BC_2, *, controlr, 1),\" &\n\t\"1358 (BC_2, IO_C20, output3, X, 1357, 1, Z),\" & --  PAD88\n\t\"1359 (BC_2, IO_C20, input, X),\" & --  PAD88\n\t\"1360 (BC_2, *, controlr, 1),\" &\n\t\"1361 (BC_2, IO_F17, output3, X, 1360, 1, Z),\" & --  PAD87\n\t\"1362 (BC_2, IO_F17, input, X),\" & --  PAD87\n\t\"1363 (BC_2, *, controlr, 1),\" &\n\t\"1364 (BC_2, IO_G17, output3, X, 1363, 1, Z),\" & --  PAD86\n\t\"1365 (BC_2, IO_G17, input, X),\" & --  PAD86\n\t\"1366 (BC_2, *, controlr, 1),\" &\n\t\"1367 (BC_2, IO_B17, output3, X, 1366, 1, Z),\" & --  PAD85\n\t\"1368 (BC_2, IO_B17, input, X),\" & --  PAD85\n\t\"1369 (BC_2, *, controlr, 1),\" &\n\t\"1370 (BC_2, IO_C17, output3, X, 1369, 1, Z),\" & --  PAD84\n\t\"1371 (BC_2, IO_C17, input, X),\" & --  PAD84\n\t\"1372 (BC_2, *, controlr, 1),\" &\n\t\"1373 (BC_2, IO_F18, output3, X, 1372, 1, Z),\" & --  PAD83\n\t\"1374 (BC_2, IO_F18, input, X),\" & --  PAD83\n\t\"1375 (BC_2, *, controlr, 1),\" &\n\t\"1376 (BC_2, IO_G18, output3, X, 1375, 1, Z),\" & --  PAD82\n\t\"1377 (BC_2, IO_G18, input, X),\" & --  PAD82\n\t\"1378 (BC_2, *, controlr, 1),\" &\n\t\"1379 (BC_2, IO_C16, output3, X, 1378, 1, Z),\" & --  PAD81\n\t\"1380 (BC_2, IO_C16, input, X),\" & --  PAD81\n\t\"1381 (BC_2, *, controlr, 1),\" &\n\t\"1382 (BC_2, IO_D16, output3, X, 1381, 1, Z),\" & --  PAD80\n\t\"1383 (BC_2, IO_D16, input, X),\" & --  PAD80\n\t\"1384 (BC_2, *, controlr, 1),\" &\n\t\"1385 (BC_2, IO_D19, output3, X, 1384, 1, Z),\" & --  PAD79\n\t\"1386 (BC_2, IO_D19, input, X),\" & --  PAD79\n\t\"1387 (BC_2, *, controlr, 1),\" &\n\t\"1388 (BC_2, IO_E19, output3, X, 1387, 1, Z),\" & --  PAD78\n\t\"1389 (BC_2, IO_E19, input, X),\" & --  PAD78\n\t\"1390 (BC_2, *, controlr, 1),\" &\n\t\"1391 (BC_2, IO_D18, output3, X, 1390, 1, Z),\" & --  PAD77\n\t\"1392 (BC_2, IO_D18, input, X),\" & --  PAD77\n\t\"1393 (BC_2, *, controlr, 1),\" &\n\t\"1394 (BC_2, IO_D17, output3, X, 1393, 1, Z),\" & --  PAD76\n\t\"1395 (BC_2, IO_D17, input, X),\" & --  PAD76\n\t\"1396 (BC_2, *, controlr, 1),\" &\n\t\"1397 (BC_2, IO_E20, output3, X, 1396, 1, Z),\" & --  PAD75\n\t\"1398 (BC_2, IO_E20, input, X),\" & --  PAD75\n\t\"1399 (BC_2, *, controlr, 1),\" &\n\t\"1400 (BC_2, IO_F20, output3, X, 1399, 1, Z),\" & --  PAD74\n\t\"1401 (BC_2, IO_F20, input, X),\" & --  PAD74\n\t\"1402 (BC_2, *, controlr, 1),\" &\n\t\"1403 (BC_2, IO_E21, output3, X, 1402, 1, Z),\" & --  PAD73\n\t\"1404 (BC_2, IO_E21, input, X),\" & --  PAD73\n\t\"1405 (BC_2, *, controlr, 1),\" &\n\t\"1406 (BC_2, IO_F21, output3, X, 1405, 1, Z),\" & --  PAD72\n\t\"1407 (BC_2, IO_F21, input, X),\" & --  PAD72\n\t\"1408 (BC_2, *, controlr, 1),\" &\n\t\"1409 (BC_2, IO_C22, output3, X, 1408, 1, Z),\" & --  PAD71\n\t\"1410 (BC_2, IO_C22, input, X),\" & --  PAD71\n\t\"1411 (BC_2, *, controlr, 1),\" &\n\t\"1412 (BC_2, IO_D22, output3, X, 1411, 1, Z),\" & --  PAD70\n\t\"1413 (BC_2, IO_D22, input, X),\" & --  PAD70\n\t\"1414 (BC_2, *, controlr, 1),\" &\n\t\"1415 (BC_2, IO_F22, output3, X, 1414, 1, Z),\" & --  PAD69\n\t\"1416 (BC_2, IO_F22, input, X),\" & --  PAD69\n\t\"1417 (BC_2, *, controlr, 1),\" &\n\t\"1418 (BC_2, IO_G22, output3, X, 1417, 1, Z),\" & --  PAD68\n\t\"1419 (BC_2, IO_G22, input, X),\" & --  PAD68\n\t\"1420 (BC_2, *, controlr, 1),\" &\n\t\"1421 (BC_2, IO_C21, output3, X, 1420, 1, Z),\" & --  PAD67\n\t\"1422 (BC_2, IO_C21, input, X),\" & --  PAD67\n\t\"1423 (BC_2, *, controlr, 1),\" &\n\t\"1424 (BC_2, IO_D21, output3, X, 1423, 1, Z),\" & --  PAD66\n\t\"1425 (BC_2, IO_D21, input, X),\" & --  PAD66\n\t\"1426 (BC_2, *, controlr, 1),\" &\n\t\"1427 (BC_2, IO_H22, output3, X, 1426, 1, Z),\" & --  PAD65\n\t\"1428 (BC_2, IO_H22, input, X),\" & --  PAD65\n\t\"1429 (BC_2, *, controlr, 1),\" &\n\t\"1430 (BC_2, IO_H21, output3, X, 1429, 1, Z),\" & --  PAD64\n\t\"1431 (BC_2, IO_H21, input, X),\" & --  PAD64\n\t\"1432 (BC_2, *, controlr, 1),\" &\n\t\"1433 (BC_2, IO_K20, output3, X, 1432, 1, Z),\" & --  PAD63\n\t\"1434 (BC_2, IO_K20, input, X),\" & --  PAD63\n\t\"1435 (BC_2, *, controlr, 1),\" &\n\t\"1436 (BC_2, IO_K19, output3, X, 1435, 1, Z),\" & --  PAD62\n\t\"1437 (BC_2, IO_K19, input, X),\" & --  PAD62\n\t\"1438 (BC_2, *, controlr, 1),\" &\n\t\"1439 (BC_2, IO_L18, output3, X, 1438, 1, Z),\" & --  PAD61\n\t\"1440 (BC_2, IO_L18, input, X),\" & --  PAD61\n\t\"1441 (BC_2, *, controlr, 1),\" &\n\t\"1442 (BC_2, IO_L17, output3, X, 1441, 1, Z),\" & --  PAD60\n\t\"1443 (BC_2, IO_L17, input, X),\" & --  PAD60\n\t\"1444 (BC_2, *, controlr, 1),\" &\n\t\"1445 (BC_2, IO_H19, output3, X, 1444, 1, Z),\" & --  PAD59\n\t\"1446 (BC_2, IO_H19, input, X),\" & --  PAD59\n\t\"1447 (BC_2, *, controlr, 1),\" &\n\t\"1448 (BC_2, IO_J19, output3, X, 1447, 1, Z),\" & --  PAD58\n\t\"1449 (BC_2, IO_J19, input, X),\" & --  PAD58\n\t\"1450 (BC_2, *, controlr, 1),\" &\n\t\"1451 (BC_2, IO_H17, output3, X, 1450, 1, Z),\" & --  PAD57\n\t\"1452 (BC_2, IO_H17, input, X),\" & --  PAD57\n\t\"1453 (BC_2, *, controlr, 1),\" &\n\t\"1454 (BC_2, IO_J17, output3, X, 1453, 1, Z),\" & --  PAD56\n\t\"1455 (BC_2, IO_J17, input, X),\" & --  PAD56\n\t\"1456 (BC_2, *, controlr, 1),\" &\n\t\"1457 (BC_2, IO_G20, output3, X, 1456, 1, Z),\" & --  PAD55\n\t\"1458 (BC_2, IO_G20, input, X),\" & --  PAD55\n\t\"1459 (BC_2, *, controlr, 1),\" &\n\t\"1460 (BC_2, IO_H20, output3, X, 1459, 1, Z),\" & --  PAD54\n\t\"1461 (BC_2, IO_H20, input, X),\" & --  PAD54\n\t\"1462 (BC_2, *, controlr, 1),\" &\n\t\"1463 (BC_2, IO_J18, output3, X, 1462, 1, Z),\" & --  PAD53\n\t\"1464 (BC_2, IO_J18, input, X),\" & --  PAD53\n\t\"1465 (BC_2, *, controlr, 1),\" &\n\t\"1466 (BC_2, IO_K18, output3, X, 1465, 1, Z),\" & --  PAD52\n\t\"1467 (BC_2, IO_K18, input, X),\" & --  PAD52\n\t\"1468 (BC_2, *, controlr, 1),\" &\n\t\"1469 (BC_2, IO_G19, output3, X, 1468, 1, Z),\" & --  PAD51\n\t\"1470 (BC_2, IO_G19, input, X),\" & --  PAD51\n\t\"1471 (BC_2, *, controlr, 1),\" &\n\t\"1472 (BC_2, IO_F16, output3, X, 1471, 1, Z),\" & --  PAD50\n\t\"1473 (BC_2, IO_F16, input, X),\" & --  PAD50\n\t\"1474 (BC_2, *, controlr, 1),\" &\n\t\"1475 (BC_2, IO_A15, output3, X, 1474, 1, Z),\" & --  PAD49\n\t\"1476 (BC_2, IO_A15, input, X),\" & --  PAD49\n\t\"1477 (BC_2, *, controlr, 1),\" &\n\t\"1478 (BC_2, IO_B14, output3, X, 1477, 1, Z),\" & --  PAD48\n\t\"1479 (BC_2, IO_B14, input, X),\" & --  PAD48\n\t\"1480 (BC_2, *, controlr, 1),\" &\n\t\"1481 (BC_2, IO_B15, output3, X, 1480, 1, Z),\" & --  PAD47\n\t\"1482 (BC_2, IO_B15, input, X),\" & --  PAD47\n\t\"1483 (BC_2, *, controlr, 1),\" &\n\t\"1484 (BC_2, IO_C15, output3, X, 1483, 1, Z),\" & --  PAD46\n\t\"1485 (BC_2, IO_C15, input, X),\" & --  PAD46\n\t\"1486 (BC_2, *, controlr, 1),\" &\n\t\"1487 (BC_2, IO_A13, output3, X, 1486, 1, Z),\" & --  PAD45\n\t\"1488 (BC_2, IO_A13, input, X),\" & --  PAD45\n\t\"1489 (BC_2, *, controlr, 1),\" &\n\t\"1490 (BC_2, IO_B13, output3, X, 1489, 1, Z),\" & --  PAD44\n\t\"1491 (BC_2, IO_B13, input, X),\" & --  PAD44\n\t\"1492 (BC_2, *, controlr, 1),\" &\n\t\"1493 (BC_2, IO_C14, output3, X, 1492, 1, Z),\" & --  PAD43\n\t\"1494 (BC_2, IO_C14, input, X),\" & --  PAD43\n\t\"1495 (BC_2, *, controlr, 1),\" &\n\t\"1496 (BC_2, IO_D14, output3, X, 1495, 1, Z),\" & --  PAD42\n\t\"1497 (BC_2, IO_D14, input, X),\" & --  PAD42\n\t\"1498 (BC_2, *, controlr, 1),\" &\n\t\"1499 (BC_2, IO_E15, output3, X, 1498, 1, Z),\" & --  PAD41\n\t\"1500 (BC_2, IO_E15, input, X),\" & --  PAD41\n\t\"1501 (BC_2, *, controlr, 1),\" &\n\t\"1502 (BC_2, IO_E14, output3, X, 1501, 1, Z),\" & --  PAD40\n\t\"1503 (BC_2, IO_E14, input, X),\" & --  PAD40\n\t\"1504 (BC_2, *, controlr, 1),\" &\n\t\"1505 (BC_2, IO_E16, output3, X, 1504, 1, Z),\" & --  PAD39\n\t\"1506 (BC_2, IO_E16, input, X),\" & --  PAD39\n\t\"1507 (BC_2, *, controlr, 1),\" &\n\t\"1508 (BC_2, IO_F15, output3, X, 1507, 1, Z),\" & --  PAD38\n\t\"1509 (BC_2, IO_F15, input, X),\" & --  PAD38\n\t\"1510 (BC_2, *, controlr, 1),\" &\n\t\"1511 (BC_2, IO_C11, output3, X, 1510, 1, Z),\" & --  PAD37\n\t\"1512 (BC_2, IO_C11, input, X),\" & --  PAD37\n\t\"1513 (BC_2, *, controlr, 1),\" &\n\t\"1514 (BC_2, IO_D11, output3, X, 1513, 1, Z),\" & --  PAD36\n\t\"1515 (BC_2, IO_D11, input, X),\" & --  PAD36\n\t\"1516 (BC_2, *, controlr, 1),\" &\n\t\"1517 (BC_2, IO_A12, output3, X, 1516, 1, Z),\" & --  PAD35\n\t\"1518 (BC_2, IO_A12, input, X),\" & --  PAD35\n\t\"1519 (BC_2, *, controlr, 1),\" &\n\t\"1520 (BC_2, IO_A11, output3, X, 1519, 1, Z),\" & --  PAD34\n\t\"1521 (BC_2, IO_A11, input, X),\" & --  PAD34\n\t\"1522 (BC_2, *, controlr, 1),\" &\n\t\"1523 (BC_2, IO_E11, output3, X, 1522, 1, Z),\" & --  PAD33\n\t\"1524 (BC_2, IO_E11, input, X),\" & --  PAD33\n\t\"1525 (BC_2, *, controlr, 1),\" &\n\t\"1526 (BC_2, IO_F11, output3, X, 1525, 1, Z),\" & --  PAD32\n\t\"1527 (BC_2, IO_F11, input, X),\" & --  PAD32\n\t\"1528 (BC_2, *, controlr, 1),\" &\n\t\"1529 (BC_2, IO_B12, output3, X, 1528, 1, Z),\" & --  PAD31\n\t\"1530 (BC_2, IO_B12, input, X),\" & --  PAD31\n\t\"1531 (BC_2, *, controlr, 1),\" &\n\t\"1532 (BC_2, IO_C12, output3, X, 1531, 1, Z),\" & --  PAD30\n\t\"1533 (BC_2, IO_C12, input, X),\" & --  PAD30\n\t\"1534 (BC_2, *, controlr, 1),\" &\n\t\"1535 (BC_2, IO_E13, output3, X, 1534, 1, Z),\" & --  PAD29\n\t\"1536 (BC_2, IO_E13, input, X),\" & --  PAD29\n\t\"1537 (BC_2, *, controlr, 1),\" &\n\t\"1538 (BC_2, IO_F12, output3, X, 1537, 1, Z),\" & --  PAD28\n\t\"1539 (BC_2, IO_F12, input, X),\" & --  PAD28\n\t\"1540 (BC_2, *, controlr, 1),\" &\n\t\"1541 (BC_2, IO_D13, output3, X, 1540, 1, Z),\" & --  PAD27\n\t\"1542 (BC_2, IO_D13, input, X),\" & --  PAD27\n\t\"1543 (BC_2, *, controlr, 1),\" &\n\t\"1544 (BC_2, IO_D12, output3, X, 1543, 1, Z),\" & --  PAD26\n\t\"1545 (BC_2, IO_D12, input, X),\" & --  PAD26\n\t\"1546 (BC_2, *, controlr, 1),\" &\n\t\"1547 (BC_2, IO_F13, output3, X, 1546, 1, Z),\" & --  PAD25\n\t\"1548 (BC_2, IO_F13, input, X),\" & --  PAD25\n\t\"1549 (BC_2, *, controlr, 1),\" &\n\t\"1550 (BC_2, IO_G13, output3, X, 1549, 1, Z),\" & --  PAD24\n\t\"1551 (BC_2, IO_G13, input, X),\" & --  PAD24\n\t\"1552 (BC_2, *, controlr, 1),\" &\n\t\"1553 (BC_2, IO_G14, output3, X, 1552, 1, Z),\" & --  PAD23\n\t\"1554 (BC_2, IO_G14, input, X),\" & --  PAD23\n\t\"1555 (BC_2, *, controlr, 1),\" &\n\t\"1556 (BC_2, IO_H14, output3, X, 1555, 1, Z),\" & --  PAD22\n\t\"1557 (BC_2, IO_H14, input, X),\" & --  PAD22\n\t\"1558 (BC_2, *, controlr, 1),\" &\n\t\"1559 (BC_2, IO_H12, output3, X, 1558, 1, Z),\" & --  PAD21\n\t\"1560 (BC_2, IO_H12, input, X),\" & --  PAD21\n\t\"1561 (BC_2, *, controlr, 1),\" &\n\t\"1562 (BC_2, IO_H11, output3, X, 1561, 1, Z),\" & --  PAD20\n\t\"1563 (BC_2, IO_H11, input, X),\" & --  PAD20\n\t\"1564 (BC_2, *, controlr, 1),\" &\n\t\"1565 (BC_2, IO_H16, output3, X, 1564, 1, Z),\" & --  PAD19\n\t\"1566 (BC_2, IO_H16, input, X),\" & --  PAD19\n\t\"1567 (BC_2, *, controlr, 1),\" &\n\t\"1568 (BC_2, IO_J16, output3, X, 1567, 1, Z),\" & --  PAD18\n\t\"1569 (BC_2, IO_J16, input, X),\" & --  PAD18\n\t\"1570 (BC_2, *, controlr, 1),\" &\n\t\"1571 (BC_2, IO_J12, output3, X, 1570, 1, Z),\" & --  PAD17\n\t\"1572 (BC_2, IO_J12, input, X),\" & --  PAD17\n\t\"1573 (BC_2, *, controlr, 1),\" &\n\t\"1574 (BC_2, IO_J11, output3, X, 1573, 1, Z),\" & --  PAD16\n\t\"1575 (BC_2, IO_J11, input, X),\" & --  PAD16\n\t\"1576 (BC_2, *, controlr, 1),\" &\n\t\"1577 (BC_2, IO_G15, output3, X, 1576, 1, Z),\" & --  PAD15\n\t\"1578 (BC_2, IO_G15, input, X),\" & --  PAD15\n\t\"1579 (BC_2, *, controlr, 1),\" &\n\t\"1580 (BC_2, IO_H15, output3, X, 1579, 1, Z),\" & --  PAD14\n\t\"1581 (BC_2, IO_H15, input, X),\" & --  PAD14\n\t\"1582 (BC_2, *, controlr, 1),\" &\n\t\"1583 (BC_2, IO_K11, output3, X, 1582, 1, Z),\" & --  PAD13\n\t\"1584 (BC_2, IO_K11, input, X),\" & --  PAD13\n\t\"1585 (BC_2, *, controlr, 1),\" &\n\t\"1586 (BC_2, IO_L11, output3, X, 1585, 1, Z),\" & --  PAD12\n\t\"1587 (BC_2, IO_L11, input, X),\" & --  PAD12\n\t\"1588 (BC_2, *, controlr, 1),\" &\n\t\"1589 (BC_2, IO_J14, output3, X, 1588, 1, Z),\" & --  PAD11\n\t\"1590 (BC_2, IO_J14, input, X),\" & --  PAD11\n\t\"1591 (BC_2, *, controlr, 1),\" &\n\t\"1592 (BC_2, IO_K14, output3, X, 1591, 1, Z),\" & --  PAD10\n\t\"1593 (BC_2, IO_K14, input, X),\" & --  PAD10\n\t\"1594 (BC_2, *, controlr, 1),\" &\n\t\"1595 (BC_2, IO_J13, output3, X, 1594, 1, Z),\" & --  PAD9\n\t\"1596 (BC_2, IO_J13, input, X),\" & --  PAD9\n\t\"1597 (BC_2, *, controlr, 1),\" &\n\t\"1598 (BC_2, IO_K13, output3, X, 1597, 1, Z),\" & --  PAD8\n\t\"1599 (BC_2, IO_K13, input, X),\" & --  PAD8\n\t\"1600 (BC_2, *, controlr, 1),\" &\n\t\"1601 (BC_2, IO_L13, output3, X, 1600, 1, Z),\" & --  PAD7\n\t\"1602 (BC_2, IO_L13, input, X),\" & --  PAD7\n\t\"1603 (BC_2, *, controlr, 1),\" &\n\t\"1604 (BC_2, IO_L12, output3, X, 1603, 1, Z),\" & --  PAD6\n\t\"1605 (BC_2, IO_L12, input, X),\" & --  PAD6\n\t\"1606 (BC_2, *, controlr, 1),\" &\n\t\"1607 (BC_2, IO_K15, output3, X, 1606, 1, Z),\" & --  PAD5\n\t\"1608 (BC_2, IO_K15, input, X),\" & --  PAD5\n\t\"1609 (BC_2, *, controlr, 1),\" &\n\t\"1610 (BC_2, IO_L15, output3, X, 1609, 1, Z),\" & --  PAD4\n\t\"1611 (BC_2, IO_L15, input, X),\" & --  PAD4\n\t\"1612 (BC_2, *, controlr, 1),\" &\n\t\"1613 (BC_2, IO_K16, output3, X, 1612, 1, Z),\" & --  PAD3\n\t\"1614 (BC_2, IO_K16, input, X),\" & --  PAD3\n\t\"1615 (BC_2, *, controlr, 1),\" &\n\t\"1616 (BC_2, IO_L16, output3, X, 1615, 1, Z),\" & --  PAD2\n\t\"1617 (BC_2, IO_L16, input, X),\" & --  PAD2\n\t\"1618 (BC_2, *, controlr, 1),\" &\n\t\"1619 (BC_2, IO_G12, output3, X, 1618, 1, Z),\" & --  PAD1\n\t\"1620 (BC_2, IO_G12, input, X),\" & --  PAD1\n\t\"1621 (BC_2, *, internal, X),\" &\n\t\"1622 (BC_2, *, internal, X),\" &\n\t\"1623 (BC_2, *, internal, X),\" &\n\t\"1624 (BC_2, *, internal, X),\" &\n\t\"1625 (BC_2, *, internal, X),\" &\n\t\"1626 (BC_2, *, internal, X),\" &\n\t\"1627 (BC_2, *, internal, X),\" &\n\t\"1628 (BC_2, *, internal, X),\" &\n\t\"1629 (BC_2, *, internal, X),\" &\n\t\"1630 (BC_2, *, internal, X)\";\n\n\n-- Advanced I/O Description\n\nattribute AIO_COMPONENT_CONFORMANCE of XC7K325T_FFG900 : entity is\n\t\"STD_1149_6_2003\";\n\nattribute AIO_EXTEST_Pulse_Execution of XC7K325T_FFG900 : entity is\n\t\"Wait_Duration TCK 15\";\n\nattribute AIO_EXTEST_Train_Execution of XC7K325T_FFG900 : entity is\n\t\"train 30, maximum_time 120.0e-6\";\n\nattribute AIO_Pin_Behavior of XC7K325T_FFG900 : entity is\n\"MGTXRXP0_115 : LP_time=22.5e-9 HP_time=45.0e-9; \" &\n\"MGTXRXP0_116 : LP_time=22.5e-9 HP_time=45.0e-9; \" &\n\"MGTXRXP0_117 : LP_time=22.5e-9 HP_time=45.0e-9; \" &\n\"MGTXRXP0_118 : LP_time=22.5e-9 HP_time=45.0e-9; \" &\n\"MGTXRXP1_115 : LP_time=22.5e-9 HP_time=45.0e-9; \" &\n\"MGTXRXP1_116 : LP_time=22.5e-9 HP_time=45.0e-9; \" &\n\"MGTXRXP1_117 : LP_time=22.5e-9 HP_time=45.0e-9; \" &\n\"MGTXRXP1_118 : LP_time=22.5e-9 HP_time=45.0e-9; \" &\n\"MGTXRXP2_115 : LP_time=22.5e-9 HP_time=45.0e-9; \" &\n\"MGTXRXP2_116 : LP_time=22.5e-9 HP_time=45.0e-9; \" &\n\"MGTXRXP2_117 : LP_time=22.5e-9 HP_time=45.0e-9; \" &\n\"MGTXRXP2_118 : LP_time=22.5e-9 HP_time=45.0e-9; \" &\n\"MGTXRXP3_115 : LP_time=22.5e-9 HP_time=45.0e-9; \" &\n\"MGTXRXP3_116 : LP_time=22.5e-9 HP_time=45.0e-9; \" &\n\"MGTXRXP3_117 : LP_time=22.5e-9 HP_time=45.0e-9; \" &\n\"MGTXRXP3_118 : LP_time=22.5e-9 HP_time=45.0e-9; \" &\n\"MGTXTXP0_115; \" &\n\"MGTXTXP0_116; \" &\n\"MGTXTXP0_117; \" &\n\"MGTXTXP0_118; \" &\n\"MGTXTXP1_115; \" &\n\"MGTXTXP1_116; \" &\n\"MGTXTXP1_117; \" &\n\"MGTXTXP1_118; \" &\n\"MGTXTXP2_115; \" &\n\"MGTXTXP2_116; \" &\n\"MGTXTXP2_117; \" &\n\"MGTXTXP2_118; \" &\n\"MGTXTXP3_115; \" &\n\"MGTXTXP3_116; \" &\n\"MGTXTXP3_117; \" &\n\"MGTXTXP3_118 \";\n\n-- Design Warning Section\n\nattribute DESIGN_WARNING of XC7K325T_FFG900 : entity is\n        \"This is a preliminary BSDL file which has not been verified.\" &\n\t\"When no bitstream is loaded and GTPs are not instantiated,\" &\n\t\t\"the boundary-scan cells associated with GTPs will not\" &\n\t\t\"capture correct state information.  To model the boundary-\" &\n\t\t\"scan cell behavior correctly post-configuration, use\" &\n\t\t\"BSDLanno to modify the BSDL file.\" &\n        \"This BSDL file must be modified by the FPGA designer in order to\" &\n                \"reflect post-configuration behavior (if any).\" &\n        \"To avoid losing the current configuration, the boundary scan\" &\n                \"test vectors should keep the PROGRAM_B pin\" &\n                \"high.  If the PROGRAM_B pin goes low by any means,\" &\n                \"the configuration will be cleared.\" &\n        \"PROGRAM_B can only be captured, not updated.\" &\n                \"The value at the pin is always used by the device.\" &\n        \"In EXTEST, output and tristate values are not captured in the\" &\n                \"Capture-DR state - those register cells are unchanged.\" &\n\t\"Differential Serial IO pins do not support INTEST.\" &\n        \"In INTEST, the pin input values are not captured in the\" &\n                \"Capture-DR state - those register cells are unchanged.\" &\n        \"The output and tristate capture values are not valid until after\" &\n                \"the device is configured.\" &\n        \"The tristate control value is not captured properly when\" &\n                \"GTS is activated.\" &\n\t\"The IEEE Std 1149.6 EXTEST_PULSE and EXTEST_TRAIN instructions\" &\n\t\t\"require a minimum TCK freq of 15 MHz and min temp of 0C.\" &\n\t\"NOCONNECT pins should not be connected to any supply\" &\n\t\t\"or GND.  They should be left floating.\";\n\nend XC7K325T_FFG900;\n\n"
  },
  {
    "path": "jtag/bsd/xc7vx485t_ffg1761.bsd",
    "content": "-- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.\n--\n-- This file contains confidential and proprietary information\n-- of Xilinx, Inc. and is protected under U.S. and\n-- international copyright and other intellectual property\n-- laws.\n--\n-- DISCLAIMER\n-- This disclaimer is not a license and does not grant any\n-- rights to the materials distributed herewith. Except as\n-- otherwise provided in a valid license issued to you by\n-- Xilinx, and to the maximum extent permitted by applicable\n-- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n-- (2) Xilinx shall not be liable (whether in contract or tort,\n-- including negligence, or under any other theory of \n-- liability) for any loss or damage of any kind or nature\n-- releated to, arising under or in connection with these\n-- materials, including for any direct, or any indirect,\n-- special, incidental, or consequential loss or damage\n-- (including loss of data, profits, goodwill, or any type of\n-- loss or damage suffered as a result of any action brought\n-- by a third party) even if such damage or loss was\n-- reasonably foreseeable or Xilinx had been advised of the\n-- possibility of the same.\n--\n-- CRITICAL APPLICATIONS\n-- Xilinx products are not designed or intended to be fail-\n-- safe, or for use in any application requiring fail-safe\n-- performance, such as life-support or safety devices or\n-- systems, Class III medical devices, nuclear facilities,\n-- applications related to the deployment of airbags, or any\n-- other applications that could lead to death, personal\n-- injury, or severe property or environmental damage\n-- (individually and collectively, \"Critical\n-- Applications\"). Customer assumes the sole risk and\n-- liability of any use of Xilinx products in Critical\n-- Applications, subject only to applicable laws and\n-- regulations governing limitiations on product liability.\n--\n-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n-- PART OF THIS FILE AT ALL TIMES.\n--\n-- BSDL file for device XC7VX485T, package FFG1761\n-- Generated by bsdlnet Version 1.7\n-- Generated on Wed Dec 07, 2011  09:27:27 PST\n-- Generated using schematic at v32_top/xc7vx485t/schematic\n-- Schematic date = 2011-02-16 07:01:45\n-- Schematic ICM_VARIANT = 28t_n1\n-- Package File date = # Date    : 2011-08-22 07:43:37\n------------------------------------------------------------------------\n-- Modification History\n-- | CR # N/A\n-- | Details -  Initial Release\n------------------------------------------------------------------------\n--\n-- For technical support, http://support.xilinx.com -> enter text 'bsdl'\n-- in the text search box at the left of the page.  If none of\n-- these records resolve your problem you should open a web support case\n-- or contact our technical support at:\n--\n--\tNorth America\t1-800-255-7778\t\thotline@xilinx.com\n--\tUnited Kingdom\t+44 870 7350 610\teurosupport@xilinx.com\n--\tFrance\t\t(33) 1 3463 0100\teurosupport@xilinx.com\n--\tGermany\t\t(49) 89 991 54930\teurosupport@xilinx.com\n--\tJapan\t\t(81) 3-3297-9163\tjhotline@xilinx.com\n--\n-- This BSDL file reflects the pre-configuration JTAG behavior. To reflect\n-- the post-configuration JTAG behavior (if any), edit this file as described\n-- below. Many of these changes are demonstrated by commented-out template\n-- lines preceeding the lines they would replace:\n--\n-- 1. Enable USER instructions as appropriate (see below).\n-- 2. Set disable result of all pads as configured.\n-- 3. Set safe state of boundary cells as necessary.\n-- 4. Rename entity if necessary to avoid name collisions.\n-- 5. Modify USERCODE value in USERCODE_REGISTER declaration.\n--\n-- To prevent losing the current configuration, the boundary scan\n-- test vectors should keep the PROGRAM_B pin high.\n--\n-- PROGRAM_B can only be captured, not updated.  The value\n-- at the pin is always used by the device.\n--\n-- All IOBs prior to configuration, and unused and output-only IOBs following\n-- configuration, will sense their pad values during boundary-scan with an CMOS\n-- input buffer. In order to properly capture a logic high value at one\n-- of these IOBs into its input boundary scan cell, please refer to the\n-- datasheet and user guide for proper input levels.\n--\n-- For post-configuration boundary scan only: If an IOB is configured to use\n-- an input standard that uses VREF pins, then the boundary scan test vectors\n-- must keep the used VREF pins 3-stated.\n\n----------------------------------\n\n-- BSDL File for P1149.6 Standard.\n\n----------------------------------\n-- ----------------------------------------------------------------------\n-- This BSDL file has been checked and verified by JTAG Technologies B.V.\n-- on 2011-12-08, for syntactical and semantic compliance with\n-- IEEE standards 1149.1 and 1149.6\n-- using bsdl32.dll 1.6.1.5 - 20110523 Win32\n-- copyright (c) 2009 JTAG Technologies B.V., All rights reserved\n-- ----------------------------------------------------------------------\n\nentity XC7VX485T_FFG1761 is\n\n-- Generic Parameter\n\ngeneric (PHYSICAL_PIN_MAP : string := \"FFG1761\" );\n\n-- Logical Port Description\n\nport (\n\tCCLK_N10: inout bit; --  CCLK_0\n\tCFGBVS_AH10: in bit; --  CFGBVS_0\n\tDONE_AL11: inout bit; --  DONE_0\n\tGND: linkage bit_vector (1 to 424);\n\tGNDADC_0: linkage bit;\n\tINIT_B_AG11: inout bit; --  INIT_B_0\n\tM0_AL10: in bit; --  M0_0\n\tM1_AK10: in bit; --  M1_0\n\tM2_AJ10: in bit; --  M2_0\n\tMGTAVCC_G10: linkage bit_vector (1 to 11);\n\tMGTAVCC_G11: linkage bit_vector (1 to 5);\n\tMGTAVTTRCAL_115: linkage bit;\n\tMGTAVTT_G10: linkage bit_vector (1 to 16);\n\tMGTAVTT_G11: linkage bit_vector (1 to 11);\n\tMGTREFCLK0N_113: linkage bit;\n\tMGTREFCLK0N_114: linkage bit;\n\tMGTREFCLK0N_115: linkage bit;\n\tMGTREFCLK0N_116: linkage bit;\n\tMGTREFCLK0N_117: linkage bit;\n\tMGTREFCLK0N_118: linkage bit;\n\tMGTREFCLK0N_119: linkage bit;\n\tMGTREFCLK0P_113: linkage bit;\n\tMGTREFCLK0P_114: linkage bit;\n\tMGTREFCLK0P_115: linkage bit;\n\tMGTREFCLK0P_116: linkage bit;\n\tMGTREFCLK0P_117: linkage bit;\n\tMGTREFCLK0P_118: linkage bit;\n\tMGTREFCLK0P_119: linkage bit;\n\tMGTREFCLK1N_113: linkage bit;\n\tMGTREFCLK1N_114: linkage bit;\n\tMGTREFCLK1N_115: linkage bit;\n\tMGTREFCLK1N_116: linkage bit;\n\tMGTREFCLK1N_117: linkage bit;\n\tMGTREFCLK1N_118: linkage bit;\n\tMGTREFCLK1N_119: linkage bit;\n\tMGTREFCLK1P_113: linkage bit;\n\tMGTREFCLK1P_114: linkage bit;\n\tMGTREFCLK1P_115: linkage bit;\n\tMGTREFCLK1P_116: linkage bit;\n\tMGTREFCLK1P_117: linkage bit;\n\tMGTREFCLK1P_118: linkage bit;\n\tMGTREFCLK1P_119: linkage bit;\n\tMGTRREF_115: linkage bit;\n\tMGTVCCAUX_G10: linkage bit_vector (1 to 2);\n\tMGTVCCAUX_G11: linkage bit;\n\tMGTXRXN0_113: in bit;\n\tMGTXRXN0_114: in bit;\n\tMGTXRXN0_115: in bit;\n\tMGTXRXN0_116: in bit;\n\tMGTXRXN0_117: in bit;\n\tMGTXRXN0_118: in bit;\n\tMGTXRXN0_119: in bit;\n\tMGTXRXN1_113: in bit;\n\tMGTXRXN1_114: in bit;\n\tMGTXRXN1_115: in bit;\n\tMGTXRXN1_116: in bit;\n\tMGTXRXN1_117: in bit;\n\tMGTXRXN1_118: in bit;\n\tMGTXRXN1_119: in bit;\n\tMGTXRXN2_113: in bit;\n\tMGTXRXN2_114: in bit;\n\tMGTXRXN2_115: in bit;\n\tMGTXRXN2_116: in bit;\n\tMGTXRXN2_117: in bit;\n\tMGTXRXN2_118: in bit;\n\tMGTXRXN2_119: in bit;\n\tMGTXRXN3_113: in bit;\n\tMGTXRXN3_114: in bit;\n\tMGTXRXN3_115: in bit;\n\tMGTXRXN3_116: in bit;\n\tMGTXRXN3_117: in bit;\n\tMGTXRXN3_118: in bit;\n\tMGTXRXN3_119: in bit;\n\tMGTXRXP0_113: in bit;\n\tMGTXRXP0_114: in bit;\n\tMGTXRXP0_115: in bit;\n\tMGTXRXP0_116: in bit;\n\tMGTXRXP0_117: in bit;\n\tMGTXRXP0_118: in bit;\n\tMGTXRXP0_119: in bit;\n\tMGTXRXP1_113: in bit;\n\tMGTXRXP1_114: in bit;\n\tMGTXRXP1_115: in bit;\n\tMGTXRXP1_116: in bit;\n\tMGTXRXP1_117: in bit;\n\tMGTXRXP1_118: in bit;\n\tMGTXRXP1_119: in bit;\n\tMGTXRXP2_113: in bit;\n\tMGTXRXP2_114: in bit;\n\tMGTXRXP2_115: in bit;\n\tMGTXRXP2_116: in bit;\n\tMGTXRXP2_117: in bit;\n\tMGTXRXP2_118: in bit;\n\tMGTXRXP2_119: in bit;\n\tMGTXRXP3_113: in bit;\n\tMGTXRXP3_114: in bit;\n\tMGTXRXP3_115: in bit;\n\tMGTXRXP3_116: in bit;\n\tMGTXRXP3_117: in bit;\n\tMGTXRXP3_118: in bit;\n\tMGTXRXP3_119: in bit;\n\tMGTXTXN0_113: buffer bit;\n\tMGTXTXN0_114: buffer bit;\n\tMGTXTXN0_115: buffer bit;\n\tMGTXTXN0_116: buffer bit;\n\tMGTXTXN0_117: buffer bit;\n\tMGTXTXN0_118: buffer bit;\n\tMGTXTXN0_119: buffer bit;\n\tMGTXTXN1_113: buffer bit;\n\tMGTXTXN1_114: buffer bit;\n\tMGTXTXN1_115: buffer bit;\n\tMGTXTXN1_116: buffer bit;\n\tMGTXTXN1_117: buffer bit;\n\tMGTXTXN1_118: buffer bit;\n\tMGTXTXN1_119: buffer bit;\n\tMGTXTXN2_113: buffer bit;\n\tMGTXTXN2_114: buffer bit;\n\tMGTXTXN2_115: buffer bit;\n\tMGTXTXN2_116: buffer bit;\n\tMGTXTXN2_117: buffer bit;\n\tMGTXTXN2_118: buffer bit;\n\tMGTXTXN2_119: buffer bit;\n\tMGTXTXN3_113: buffer bit;\n\tMGTXTXN3_114: buffer bit;\n\tMGTXTXN3_115: buffer bit;\n\tMGTXTXN3_116: buffer bit;\n\tMGTXTXN3_117: buffer bit;\n\tMGTXTXN3_118: buffer bit;\n\tMGTXTXN3_119: buffer bit;\n\tMGTXTXP0_113: buffer bit;\n\tMGTXTXP0_114: buffer bit;\n\tMGTXTXP0_115: buffer bit;\n\tMGTXTXP0_116: buffer bit;\n\tMGTXTXP0_117: buffer bit;\n\tMGTXTXP0_118: buffer bit;\n\tMGTXTXP0_119: buffer bit;\n\tMGTXTXP1_113: buffer bit;\n\tMGTXTXP1_114: buffer bit;\n\tMGTXTXP1_115: buffer bit;\n\tMGTXTXP1_116: buffer bit;\n\tMGTXTXP1_117: buffer bit;\n\tMGTXTXP1_118: buffer bit;\n\tMGTXTXP1_119: buffer bit;\n\tMGTXTXP2_113: buffer bit;\n\tMGTXTXP2_114: buffer bit;\n\tMGTXTXP2_115: buffer bit;\n\tMGTXTXP2_116: buffer bit;\n\tMGTXTXP2_117: buffer bit;\n\tMGTXTXP2_118: buffer bit;\n\tMGTXTXP2_119: buffer bit;\n\tMGTXTXP3_113: buffer bit;\n\tMGTXTXP3_114: buffer bit;\n\tMGTXTXP3_115: buffer bit;\n\tMGTXTXP3_116: buffer bit;\n\tMGTXTXP3_117: buffer bit;\n\tMGTXTXP3_118: buffer bit;\n\tMGTXTXP3_119: buffer bit;\n\tNOCONNECT: linkage bit_vector (1 to 194);\n\tPROGRAM_B: in bit; --  PROGRAM_B_0\n\tTCK: in bit; --  TCK_0\n\tTDI: in bit; --  TDI_0\n\tTDN_AC20: linkage bit; --  DXN_0\n\tTDO: out bit; --  TDO_0\n\tTDP_AC21: linkage bit; --  DXP_0\n\tTMS: in bit; --  TMS_0\n\tVCCADC_0: linkage bit;\n\tVCCAUX: linkage bit_vector (1 to 29);\n\tVCCBATT_0: linkage bit;\n\tVCCBRAM: linkage bit_vector (1 to 8);\n\tVCCINT: linkage bit_vector (1 to 86);\n\tVCCO_0: linkage bit_vector (1 to 2);\n\tVCCO_12: linkage bit_vector (1 to 6);\n\tVCCO_13: linkage bit_vector (1 to 7);\n\tVCCO_14: linkage bit_vector (1 to 7);\n\tVCCO_15: linkage bit_vector (1 to 6);\n\tVCCO_16: linkage bit_vector (1 to 6);\n\tVCCO_17: linkage bit_vector (1 to 6);\n\tVCCO_18: linkage bit_vector (1 to 6);\n\tVCCO_19: linkage bit_vector (1 to 7);\n\tVCCO_31: linkage bit_vector (1 to 7);\n\tVCCO_32: linkage bit_vector (1 to 6);\n\tVCCO_33: linkage bit_vector (1 to 6);\n\tVCCO_34: linkage bit_vector (1 to 6);\n\tVCCO_35: linkage bit_vector (1 to 7);\n\tVCCO_36: linkage bit_vector (1 to 7);\n\tVCCO_37: linkage bit_vector (1 to 6);\n\tVCCO_38: linkage bit_vector (1 to 6);\n\tVCCO_39: linkage bit_vector (1 to 6);\n\tVN_AB20: linkage bit; --  VN_0\n\tVP_AA21: linkage bit; --  VP_0\n\tVREFN_AA20: linkage bit; --  VREFN_0\n\tVREFP_AB21: linkage bit; --  VREFP_0\n\tIO_A14: inout bit; --  PAD355\n\tIO_A15: inout bit; --  PAD405\n\tIO_A16: inout bit; --  PAD404\n\tIO_A17: inout bit; --  PAD409\n\tIO_A19: inout bit; --  PAD407\n\tIO_A20: inout bit; --  PAD406\n\tIO_A21: inout bit; --  PAD411\n\tIO_A22: inout bit; --  PAD455\n\tIO_A24: inout bit; --  PAD452\n\tIO_A25: inout bit; --  PAD453\n\tIO_A26: inout bit; --  PAD456\n\tIO_A27: inout bit; --  PAD457\n\tIO_A29: inout bit; --  PAD484\n\tIO_A30: inout bit; --  PAD485\n\tIO_A31: inout bit; --  PAD482\n\tIO_A32: inout bit; --  PAD483\n\tIO_A34: inout bit; --  PAD555\n\tIO_A35: inout bit; --  PAD558\n\tIO_A36: inout bit; --  PAD559\n\tIO_A37: inout bit; --  PAD553\n\tIO_A39: inout bit; --  PAD557\n\tIO_A40: inout bit; --  PAD4\n\tIO_A41: inout bit; --  PAD5\n\tIO_B14: inout bit; --  PAD354\n\tIO_B16: inout bit; --  PAD353\n\tIO_B17: inout bit; --  PAD408\n\tIO_B18: inout bit; --  PAD413\n\tIO_B19: inout bit; --  PAD403\n\tIO_B21: inout bit; --  PAD410\n\tIO_B22: inout bit; --  PAD454\n\tIO_B23: inout bit; --  PAD459\n\tIO_B24: inout bit; --  PAD463\n\tIO_B26: inout bit; --  PAD460\n\tIO_B27: inout bit; --  PAD461\n\tIO_B28: inout bit; --  PAD480\n\tIO_B29: inout bit; --  PAD481\n\tIO_B31: inout bit; --  PAD487\n\tIO_B32: inout bit; --  PAD566\n\tIO_B33: inout bit; --  PAD567\n\tIO_B34: inout bit; --  PAD554\n\tIO_B36: inout bit; --  PAD552\n\tIO_B37: inout bit; --  PAD562\n\tIO_B38: inout bit; --  PAD563\n\tIO_B39: inout bit; --  PAD556\n\tIO_B41: inout bit; --  PAD8\n\tIO_B42: inout bit; --  PAD9\n\tIO_C13: inout bit; --  PAD359\n\tIO_C14: inout bit; --  PAD357\n\tIO_C15: inout bit; --  PAD356\n\tIO_C16: inout bit; --  PAD352\n\tIO_C18: inout bit; --  PAD412\n\tIO_C19: inout bit; --  PAD402\n\tIO_C20: inout bit; --  PAD415\n\tIO_C21: inout bit; --  PAD419\n\tIO_C23: inout bit; --  PAD458\n\tIO_C24: inout bit; --  PAD462\n\tIO_C25: inout bit; --  PAD474\n\tIO_C26: inout bit; --  PAD475\n\tIO_C28: inout bit; --  PAD478\n\tIO_C29: inout bit; --  PAD479\n\tIO_C30: inout bit; --  PAD491\n\tIO_C31: inout bit; --  PAD486\n\tIO_C33: inout bit; --  PAD570\n\tIO_C34: inout bit; --  PAD571\n\tIO_C35: inout bit; --  PAD574\n\tIO_C36: inout bit; --  PAD575\n\tIO_C38: inout bit; --  PAD560\n\tIO_C39: inout bit; --  PAD561\n\tIO_C40: inout bit; --  PAD12\n\tIO_C41: inout bit; --  PAD13\n\tIO_D12: inout bit; --  PAD363\n\tIO_D13: inout bit; --  PAD358\n\tIO_D15: inout bit; --  PAD361\n\tIO_D16: inout bit; --  PAD360\n\tIO_D17: inout bit; --  PAD421\n\tIO_D18: inout bit; --  PAD420\n\tIO_D20: inout bit; --  PAD414\n\tIO_D21: inout bit; --  PAD418\n\tIO_D22: inout bit; --  PAD470\n\tIO_D23: inout bit; --  PAD471\n\tIO_D25: inout bit; --  PAD472\n\tIO_D26: inout bit; --  PAD473\n\tIO_D27: inout bit; --  PAD476\n\tIO_D28: inout bit; --  PAD477\n\tIO_D30: inout bit; --  PAD490\n\tIO_D31: inout bit; --  PAD489\n\tIO_D32: inout bit; --  PAD565\n\tIO_D33: inout bit; --  PAD569\n\tIO_D35: inout bit; --  PAD572\n\tIO_D36: inout bit; --  PAD573\n\tIO_D37: inout bit; --  PAD578\n\tIO_D38: inout bit; --  PAD579\n\tIO_D40: inout bit; --  PAD3\n\tIO_D41: inout bit; --  PAD6\n\tIO_D42: inout bit; --  PAD7\n\tIO_E12: inout bit; --  PAD362\n\tIO_E13: inout bit; --  PAD367\n\tIO_E14: inout bit; --  PAD366\n\tIO_E15: inout bit; --  PAD365\n\tIO_E17: inout bit; --  PAD417\n\tIO_E18: inout bit; --  PAD425\n\tIO_E19: inout bit; --  PAD424\n\tIO_E20: inout bit; --  PAD431\n\tIO_E22: inout bit; --  PAD467\n\tIO_E23: inout bit; --  PAD464\n\tIO_E24: inout bit; --  PAD465\n\tIO_E25: inout bit; --  PAD469\n\tIO_E27: inout bit; --  PAD492\n\tIO_E28: inout bit; --  PAD493\n\tIO_E29: inout bit; --  PAD495\n\tIO_E30: inout bit; --  PAD488\n\tIO_E32: inout bit; --  PAD564\n\tIO_E33: inout bit; --  PAD568\n\tIO_E34: inout bit; --  PAD576\n\tIO_E35: inout bit; --  PAD577\n\tIO_E37: inout bit; --  PAD588\n\tIO_E38: inout bit; --  PAD589\n\tIO_E39: inout bit; --  PAD593\n\tIO_E40: inout bit; --  PAD2\n\tIO_E42: inout bit; --  PAD11\n\tIO_F12: inout bit; --  PAD371\n\tIO_F14: inout bit; --  PAD373\n\tIO_F15: inout bit; --  PAD372\n\tIO_F16: inout bit; --  PAD364\n\tIO_F17: inout bit; --  PAD416\n\tIO_F19: inout bit; --  PAD423\n\tIO_F20: inout bit; --  PAD430\n\tIO_F21: inout bit; --  PAD451\n\tIO_F22: inout bit; --  PAD466\n\tIO_F24: inout bit; --  PAD500\n\tIO_F25: inout bit; --  PAD468\n\tIO_F26: inout bit; --  PAD496\n\tIO_F27: inout bit; --  PAD497\n\tIO_F29: inout bit; --  PAD494\n\tIO_F30: inout bit; --  PAD498\n\tIO_F31: inout bit; --  PAD499\n\tIO_F32: inout bit; --  PAD581\n\tIO_F34: inout bit; --  PAD584\n\tIO_F35: inout bit; --  PAD585\n\tIO_F36: inout bit; --  PAD582\n\tIO_F37: inout bit; --  PAD583\n\tIO_F39: inout bit; --  PAD592\n\tIO_F40: inout bit; --  PAD20\n\tIO_F41: inout bit; --  PAD21\n\tIO_F42: inout bit; --  PAD10\n\tIO_G12: inout bit; --  PAD370\n\tIO_G13: inout bit; --  PAD375\n\tIO_G14: inout bit; --  PAD374\n\tIO_G16: inout bit; --  PAD369\n\tIO_G17: inout bit; --  PAD437\n\tIO_G18: inout bit; --  PAD427\n\tIO_G19: inout bit; --  PAD422\n\tIO_G21: inout bit; --  PAD508\n\tIO_G22: inout bit; --  PAD509\n\tIO_G23: inout bit; --  PAD513\n\tIO_G24: inout bit; --  PAD503\n\tIO_G26: inout bit; --  PAD510\n\tIO_G27: inout bit; --  PAD511\n\tIO_G28: inout bit; --  PAD514\n\tIO_G29: inout bit; --  PAD515\n\tIO_G31: inout bit; --  PAD551\n\tIO_G32: inout bit; --  PAD580\n\tIO_G33: inout bit; --  PAD587\n\tIO_G34: inout bit; --  PAD600\n\tIO_G36: inout bit; --  PAD590\n\tIO_G37: inout bit; --  PAD591\n\tIO_G38: inout bit; --  PAD597\n\tIO_G39: inout bit; --  PAD17\n\tIO_G41: inout bit; --  PAD18\n\tIO_G42: inout bit; --  PAD19\n\tIO_H13: inout bit; --  PAD379\n\tIO_H14: inout bit; --  PAD377\n\tIO_H15: inout bit; --  PAD376\n\tIO_H16: inout bit; --  PAD368\n\tIO_H18: inout bit; --  PAD436\n\tIO_H19: inout bit; --  PAD426\n\tIO_H20: inout bit; --  PAD435\n\tIO_H21: inout bit; --  PAD505\n\tIO_H23: inout bit; --  PAD512\n\tIO_H24: inout bit; --  PAD502\n\tIO_H25: inout bit; --  PAD506\n\tIO_H26: inout bit; --  PAD507\n\tIO_H28: inout bit; --  PAD518\n\tIO_H29: inout bit; --  PAD519\n\tIO_H30: inout bit; --  PAD617\n\tIO_H31: inout bit; --  PAD621\n\tIO_H33: inout bit; --  PAD586\n\tIO_H34: inout bit; --  PAD612\n\tIO_H35: inout bit; --  PAD613\n\tIO_H36: inout bit; --  PAD599\n\tIO_H38: inout bit; --  PAD596\n\tIO_H39: inout bit; --  PAD16\n\tIO_H40: inout bit; --  PAD14\n\tIO_H41: inout bit; --  PAD15\n\tIO_J11: inout bit; --  PAD400\n\tIO_J12: inout bit; --  PAD381\n\tIO_J13: inout bit; --  PAD378\n\tIO_J15: inout bit; --  PAD383\n\tIO_J16: inout bit; --  PAD351\n\tIO_J17: inout bit; --  PAD433\n\tIO_J18: inout bit; --  PAD429\n\tIO_J20: inout bit; --  PAD434\n\tIO_J21: inout bit; --  PAD504\n\tIO_J22: inout bit; --  PAD535\n\tIO_J23: inout bit; --  PAD529\n\tIO_J25: inout bit; --  PAD524\n\tIO_J26: inout bit; --  PAD525\n\tIO_J27: inout bit; --  PAD521\n\tIO_J28: inout bit; --  PAD517\n\tIO_J30: inout bit; --  PAD616\n\tIO_J31: inout bit; --  PAD620\n\tIO_J32: inout bit; --  PAD604\n\tIO_J33: inout bit; --  PAD605\n\tIO_J35: inout bit; --  PAD603\n\tIO_J36: inout bit; --  PAD598\n\tIO_J37: inout bit; --  PAD594\n\tIO_J38: inout bit; --  PAD595\n\tIO_J40: inout bit; --  PAD22\n\tIO_J41: inout bit; --  PAD23\n\tIO_J42: inout bit; --  PAD31\n\tIO_K12: inout bit; --  PAD380\n\tIO_K13: inout bit; --  PAD385\n\tIO_K14: inout bit; --  PAD384\n\tIO_K15: inout bit; --  PAD382\n\tIO_K17: inout bit; --  PAD432\n\tIO_K18: inout bit; --  PAD401\n\tIO_K19: inout bit; --  PAD428\n\tIO_K20: inout bit; --  PAD450\n\tIO_K22: inout bit; --  PAD534\n\tIO_K23: inout bit; --  PAD528\n\tIO_K24: inout bit; --  PAD522\n\tIO_K25: inout bit; --  PAD523\n\tIO_K27: inout bit; --  PAD520\n\tIO_K28: inout bit; --  PAD516\n\tIO_K29: inout bit; --  PAD614\n\tIO_K30: inout bit; --  PAD615\n\tIO_K32: inout bit; --  PAD625\n\tIO_K33: inout bit; --  PAD606\n\tIO_K34: inout bit; --  PAD607\n\tIO_K35: inout bit; --  PAD602\n\tIO_K37: inout bit; --  PAD34\n\tIO_K38: inout bit; --  PAD35\n\tIO_K39: inout bit; --  PAD24\n\tIO_K40: inout bit; --  PAD25\n\tIO_K42: inout bit; --  PAD30\n\tIO_L11: inout bit; --  PAD389\n\tIO_L12: inout bit; --  PAD388\n\tIO_L14: inout bit; --  PAD391\n\tIO_L15: inout bit; --  PAD387\n\tIO_L16: inout bit; --  PAD386\n\tIO_L17: inout bit; --  PAD441\n\tIO_L19: inout bit; --  PAD449\n\tIO_L20: inout bit; --  PAD448\n\tIO_L21: inout bit; --  PAD537\n\tIO_L22: inout bit; --  PAD531\n\tIO_L24: inout bit; --  PAD527\n\tIO_L25: inout bit; --  PAD532\n\tIO_L26: inout bit; --  PAD533\n\tIO_L27: inout bit; --  PAD549\n\tIO_L29: inout bit; --  PAD618\n\tIO_L30: inout bit; --  PAD619\n\tIO_L31: inout bit; --  PAD624\n\tIO_L32: inout bit; --  PAD623\n\tIO_L34: inout bit; --  PAD608\n\tIO_L35: inout bit; --  PAD609\n\tIO_L36: inout bit; --  PAD1\n\tIO_L37: inout bit; --  PAD37\n\tIO_L39: inout bit; --  PAD26\n\tIO_L40: inout bit; --  PAD27\n\tIO_L41: inout bit; --  PAD29\n\tIO_L42: inout bit; --  PAD33\n\tIO_M11: inout bit; --  PAD399\n\tIO_M12: inout bit; --  PAD398\n\tIO_M13: inout bit; --  PAD395\n\tIO_M14: inout bit; --  PAD390\n\tIO_M16: inout bit; --  PAD393\n\tIO_M17: inout bit; --  PAD440\n\tIO_M18: inout bit; --  PAD445\n\tIO_M19: inout bit; --  PAD444\n\tIO_M21: inout bit; --  PAD536\n\tIO_M22: inout bit; --  PAD530\n\tIO_M23: inout bit; --  PAD501\n\tIO_M24: inout bit; --  PAD526\n\tIO_M26: inout bit; --  PAD550\n\tIO_M27: inout bit; --  PAD548\n\tIO_M28: inout bit; --  PAD630\n\tIO_M29: inout bit; --  PAD631\n\tIO_M31: inout bit; --  PAD627\n\tIO_M32: inout bit; --  PAD622\n\tIO_M33: inout bit; --  PAD610\n\tIO_M34: inout bit; --  PAD611\n\tIO_M36: inout bit; --  PAD36\n\tIO_M37: inout bit; --  PAD40\n\tIO_M38: inout bit; --  PAD41\n\tIO_M39: inout bit; --  PAD45\n\tIO_M41: inout bit; --  PAD28\n\tIO_M42: inout bit; --  PAD32\n\tIO_N13: inout bit; --  PAD394\n\tIO_N14: inout bit; --  PAD397\n\tIO_N15: inout bit; --  PAD396\n\tIO_N16: inout bit; --  PAD392\n\tIO_N18: inout bit; --  PAD443\n\tIO_N19: inout bit; --  PAD442\n\tIO_N20: inout bit; --  PAD447\n\tIO_N21: inout bit; --  PAD539\n\tIO_N23: inout bit; --  PAD546\n\tIO_N24: inout bit; --  PAD547\n\tIO_N25: inout bit; --  PAD544\n\tIO_N26: inout bit; --  PAD545\n\tIO_N28: inout bit; --  PAD634\n\tIO_N29: inout bit; --  PAD635\n\tIO_N30: inout bit; --  PAD626\n\tIO_N31: inout bit; --  PAD629\n\tIO_N33: inout bit; --  PAD54\n\tIO_N34: inout bit; --  PAD55\n\tIO_N35: inout bit; --  PAD51\n\tIO_N36: inout bit; --  PAD50\n\tIO_N38: inout bit; --  PAD44\n\tIO_N39: inout bit; --  PAD48\n\tIO_N40: inout bit; --  PAD49\n\tIO_N41: inout bit; --  PAD39\n\tIO_P17: inout bit; --  PAD439\n\tIO_P18: inout bit; --  PAD438\n\tIO_P20: inout bit; --  PAD446\n\tIO_P21: inout bit; --  PAD538\n\tIO_P22: inout bit; --  PAD542\n\tIO_P23: inout bit; --  PAD543\n\tIO_P25: inout bit; --  PAD540\n\tIO_P26: inout bit; --  PAD541\n\tIO_P28: inout bit; --  PAD633\n\tIO_P30: inout bit; --  PAD628\n\tIO_P31: inout bit; --  PAD637\n\tIO_P32: inout bit; --  PAD62\n\tIO_P33: inout bit; --  PAD63\n\tIO_P35: inout bit; --  PAD58\n\tIO_P36: inout bit; --  PAD59\n\tIO_P37: inout bit; --  PAD66\n\tIO_P38: inout bit; --  PAD67\n\tIO_P40: inout bit; --  PAD47\n\tIO_P41: inout bit; --  PAD38\n\tIO_P42: inout bit; --  PAD43\n\tIO_R28: inout bit; --  PAD632\n\tIO_R29: inout bit; --  PAD601\n\tIO_R30: inout bit; --  PAD636\n\tIO_R32: inout bit; --  PAD61\n\tIO_R33: inout bit; --  PAD56\n\tIO_R34: inout bit; --  PAD57\n\tIO_R35: inout bit; --  PAD53\n\tIO_R37: inout bit; --  PAD65\n\tIO_R38: inout bit; --  PAD70\n\tIO_R39: inout bit; --  PAD71\n\tIO_R40: inout bit; --  PAD46\n\tIO_R42: inout bit; --  PAD42\n\tIO_T29: inout bit; --  PAD642\n\tIO_T30: inout bit; --  PAD643\n\tIO_T31: inout bit; --  PAD639\n\tIO_T32: inout bit; --  PAD60\n\tIO_T34: inout bit; --  PAD52\n\tIO_T35: inout bit; --  PAD69\n\tIO_T36: inout bit; --  PAD64\n\tIO_T37: inout bit; --  PAD77\n\tIO_T39: inout bit; --  PAD75\n\tIO_T40: inout bit; --  PAD90\n\tIO_T41: inout bit; --  PAD91\n\tIO_T42: inout bit; --  PAD95\n\tIO_U28: inout bit; --  PAD650\n\tIO_U29: inout bit; --  PAD647\n\tIO_U31: inout bit; --  PAD638\n\tIO_U32: inout bit; --  PAD84\n\tIO_U33: inout bit; --  PAD85\n\tIO_U34: inout bit; --  PAD68\n\tIO_U36: inout bit; --  PAD76\n\tIO_U37: inout bit; --  PAD72\n\tIO_U38: inout bit; --  PAD73\n\tIO_U39: inout bit; --  PAD74\n\tIO_U41: inout bit; --  PAD94\n\tIO_U42: inout bit; --  PAD99\n\tIO_V29: inout bit; --  PAD646\n\tIO_V30: inout bit; --  PAD640\n\tIO_V31: inout bit; --  PAD641\n\tIO_V33: inout bit; --  PAD80\n\tIO_V34: inout bit; --  PAD81\n\tIO_V35: inout bit; --  PAD78\n\tIO_V36: inout bit; --  PAD79\n\tIO_V38: inout bit; --  PAD97\n\tIO_V39: inout bit; --  PAD88\n\tIO_V40: inout bit; --  PAD89\n\tIO_V41: inout bit; --  PAD98\n\tIO_W30: inout bit; --  PAD644\n\tIO_W31: inout bit; --  PAD645\n\tIO_W32: inout bit; --  PAD86\n\tIO_W33: inout bit; --  PAD87\n\tIO_W35: inout bit; --  PAD100\n\tIO_W36: inout bit; --  PAD82\n\tIO_W37: inout bit; --  PAD83\n\tIO_W38: inout bit; --  PAD96\n\tIO_W40: inout bit; --  PAD104\n\tIO_W41: inout bit; --  PAD92\n\tIO_W42: inout bit; --  PAD93\n\tIO_Y29: inout bit; --  PAD648\n\tIO_Y30: inout bit; --  PAD649\n\tIO_Y32: inout bit; --  PAD188\n\tIO_Y33: inout bit; --  PAD189\n\tIO_Y34: inout bit; --  PAD151\n\tIO_Y35: inout bit; --  PAD166\n\tIO_Y37: inout bit; --  PAD164\n\tIO_Y38: inout bit; --  PAD101\n\tIO_Y39: inout bit; --  PAD106\n\tIO_Y40: inout bit; --  PAD105\n\tIO_Y42: inout bit; --  PAD108\n\tIO_AA29: inout bit; --  PAD196\n\tIO_AA30: inout bit; --  PAD197\n\tIO_AA31: inout bit; --  PAD192\n\tIO_AA32: inout bit; --  PAD193\n\tIO_AA34: inout bit; --  PAD170\n\tIO_AA35: inout bit; --  PAD171\n\tIO_AA36: inout bit; --  PAD167\n\tIO_AA37: inout bit; --  PAD165\n\tIO_AA39: inout bit; --  PAD107\n\tIO_AA40: inout bit; --  PAD112\n\tIO_AA41: inout bit; --  PAD113\n\tIO_AA42: inout bit; --  PAD109\n\tIO_AB29: inout bit; --  PAD198\n\tIO_AB31: inout bit; --  PAD172\n\tIO_AB32: inout bit; --  PAD173\n\tIO_AB33: inout bit; --  PAD174\n\tIO_AB34: inout bit; --  PAD200\n\tIO_AB36: inout bit; --  PAD168\n\tIO_AB37: inout bit; --  PAD169\n\tIO_AB38: inout bit; --  PAD110\n\tIO_AB39: inout bit; --  PAD111\n\tIO_AB41: inout bit; --  PAD102\n\tIO_AB42: inout bit; --  PAD103\n\tIO_AC29: inout bit; --  PAD199\n\tIO_AC30: inout bit; --  PAD194\n\tIO_AC31: inout bit; --  PAD190\n\tIO_AC33: inout bit; --  PAD175\n\tIO_AC34: inout bit; --  PAD178\n\tIO_AC35: inout bit; --  PAD160\n\tIO_AC36: inout bit; --  PAD161\n\tIO_AC38: inout bit; --  PAD114\n\tIO_AC39: inout bit; --  PAD115\n\tIO_AC40: inout bit; --  PAD120\n\tIO_AC41: inout bit; --  PAD121\n\tIO_AD30: inout bit; --  PAD195\n\tIO_AD31: inout bit; --  PAD191\n\tIO_AD32: inout bit; --  PAD176\n\tIO_AD33: inout bit; --  PAD177\n\tIO_AD35: inout bit; --  PAD179\n\tIO_AD36: inout bit; --  PAD158\n\tIO_AD37: inout bit; --  PAD159\n\tIO_AD38: inout bit; --  PAD118\n\tIO_AD40: inout bit; --  PAD124\n\tIO_AD41: inout bit; --  PAD125\n\tIO_AD42: inout bit; --  PAD116\n\tIO_AE29: inout bit; --  PAD186\n\tIO_AE30: inout bit; --  PAD187\n\tIO_AE32: inout bit; --  PAD180\n\tIO_AE33: inout bit; --  PAD181\n\tIO_AE34: inout bit; --  PAD184\n\tIO_AE35: inout bit; --  PAD185\n\tIO_AE37: inout bit; --  PAD154\n\tIO_AE38: inout bit; --  PAD119\n\tIO_AE39: inout bit; --  PAD122\n\tIO_AE40: inout bit; --  PAD123\n\tIO_AE42: inout bit; --  PAD117\n\tIO_AF29: inout bit; --  PAD292\n\tIO_AF30: inout bit; --  PAD296\n\tIO_AF31: inout bit; --  PAD182\n\tIO_AF32: inout bit; --  PAD183\n\tIO_AF34: inout bit; --  PAD156\n\tIO_AF35: inout bit; --  PAD152\n\tIO_AF36: inout bit; --  PAD153\n\tIO_AF37: inout bit; --  PAD155\n\tIO_AF39: inout bit; --  PAD126\n\tIO_AF40: inout bit; --  PAD127\n\tIO_AF41: inout bit; --  PAD128\n\tIO_AF42: inout bit; --  PAD132\n\tIO_AG29: inout bit; --  PAD293\n\tIO_AG31: inout bit; --  PAD297\n\tIO_AG32: inout bit; --  PAD300\n\tIO_AG33: inout bit; --  PAD264\n\tIO_AG34: inout bit; --  PAD157\n\tIO_AG36: inout bit; --  PAD162\n\tIO_AG37: inout bit; --  PAD150\n\tIO_AG38: inout bit; --  PAD134\n\tIO_AG39: inout bit; --  PAD130\n\tIO_AG41: inout bit; --  PAD129\n\tIO_AG42: inout bit; --  PAD133\n\tIO_AH28: inout bit; --  PAD298\n\tIO_AH29: inout bit; --  PAD288\n\tIO_AH30: inout bit; --  PAD289\n\tIO_AH31: inout bit; --  PAD268\n\tIO_AH33: inout bit; --  PAD265\n\tIO_AH34: inout bit; --  PAD270\n\tIO_AH35: inout bit; --  PAD251\n\tIO_AH36: inout bit; --  PAD163\n\tIO_AH38: inout bit; --  PAD135\n\tIO_AH39: inout bit; --  PAD131\n\tIO_AH40: inout bit; --  PAD140\n\tIO_AH41: inout bit; --  PAD141\n\tIO_AJ20: inout bit; --  PAD661\n\tIO_AJ21: inout bit; --  PAD660\n\tIO_AJ22: inout bit; --  PAD656\n\tIO_AJ23: inout bit; --  PAD652\n\tIO_AJ28: inout bit; --  PAD299\n\tIO_AJ30: inout bit; --  PAD290\n\tIO_AJ31: inout bit; --  PAD269\n\tIO_AJ32: inout bit; --  PAD276\n\tIO_AJ33: inout bit; --  PAD272\n\tIO_AJ35: inout bit; --  PAD271\n\tIO_AJ36: inout bit; --  PAD254\n\tIO_AJ37: inout bit; --  PAD255\n\tIO_AJ38: inout bit; --  PAD136\n\tIO_AJ40: inout bit; --  PAD144\n\tIO_AJ41: inout bit; --  PAD145\n\tIO_AJ42: inout bit; --  PAD148\n\tIO_AK20: inout bit; --  PAD654\n\tIO_AK22: inout bit; --  PAD657\n\tIO_AK23: inout bit; --  PAD653\n\tIO_AK28: inout bit; --  PAD294\n\tIO_AK29: inout bit; --  PAD295\n\tIO_AK30: inout bit; --  PAD291\n\tIO_AK32: inout bit; --  PAD277\n\tIO_AK33: inout bit; --  PAD273\n\tIO_AK34: inout bit; --  PAD274\n\tIO_AK35: inout bit; --  PAD266\n\tIO_AK37: inout bit; --  PAD258\n\tIO_AK38: inout bit; --  PAD137\n\tIO_AK39: inout bit; --  PAD146\n\tIO_AK40: inout bit; --  PAD138\n\tIO_AK42: inout bit; --  PAD149\n\tIO_AL20: inout bit; --  PAD655\n\tIO_AL21: inout bit; --  PAD658\n\tIO_AL22: inout bit; --  PAD662\n\tIO_AL24: inout bit; --  PAD651\n\tIO_AL29: inout bit; --  PAD286\n\tIO_AL30: inout bit; --  PAD287\n\tIO_AL31: inout bit; --  PAD278\n\tIO_AL32: inout bit; --  PAD279\n\tIO_AL34: inout bit; --  PAD275\n\tIO_AL35: inout bit; --  PAD267\n\tIO_AL36: inout bit; --  PAD262\n\tIO_AL37: inout bit; --  PAD259\n\tIO_AL39: inout bit; --  PAD147\n\tIO_AL40: inout bit; --  PAD139\n\tIO_AL41: inout bit; --  PAD142\n\tIO_AL42: inout bit; --  PAD143\n\tIO_AM21: inout bit; --  PAD659\n\tIO_AM22: inout bit; --  PAD663\n\tIO_AM23: inout bit; --  PAD666\n\tIO_AM24: inout bit; --  PAD664\n\tIO_AM31: inout bit; --  PAD282\n\tIO_AM32: inout bit; --  PAD283\n\tIO_AM33: inout bit; --  PAD284\n\tIO_AM34: inout bit; --  PAD280\n\tIO_AM36: inout bit; --  PAD252\n\tIO_AM37: inout bit; --  PAD263\n\tIO_AM38: inout bit; --  PAD201\n\tIO_AM39: inout bit; --  PAD212\n\tIO_AM41: inout bit; --  PAD204\n\tIO_AM42: inout bit; --  PAD205\n\tIO_AN20: inout bit; --  PAD700\n\tIO_AN21: inout bit; --  PAD670\n\tIO_AN23: inout bit; --  PAD667\n\tIO_AN24: inout bit; --  PAD665\n\tIO_AN30: inout bit; --  PAD342\n\tIO_AN31: inout bit; --  PAD346\n\tIO_AN33: inout bit; --  PAD285\n\tIO_AN34: inout bit; --  PAD281\n\tIO_AN35: inout bit; --  PAD260\n\tIO_AN36: inout bit; --  PAD253\n\tIO_AN38: inout bit; --  PAD202\n\tIO_AN39: inout bit; --  PAD213\n\tIO_AN40: inout bit; --  PAD208\n\tIO_AN41: inout bit; --  PAD209\n\tIO_AP21: inout bit; --  PAD671\n\tIO_AP22: inout bit; --  PAD669\n\tIO_AP23: inout bit; --  PAD668\n\tIO_AP30: inout bit; --  PAD343\n\tIO_AP31: inout bit; --  PAD347\n\tIO_AP32: inout bit; --  PAD344\n\tIO_AP33: inout bit; --  PAD348\n\tIO_AP35: inout bit; --  PAD261\n\tIO_AP36: inout bit; --  PAD256\n\tIO_AP37: inout bit; --  PAD257\n\tIO_AP38: inout bit; --  PAD203\n\tIO_AP40: inout bit; --  PAD214\n\tIO_AP41: inout bit; --  PAD216\n\tIO_AP42: inout bit; --  PAD217\n\tIO_AR22: inout bit; --  PAD673\n\tIO_AR23: inout bit; --  PAD672\n\tIO_AR24: inout bit; --  PAD682\n\tIO_AR30: inout bit; --  PAD338\n\tIO_AR32: inout bit; --  PAD345\n\tIO_AR33: inout bit; --  PAD349\n\tIO_AR34: inout bit; --  PAD320\n\tIO_AR35: inout bit; --  PAD301\n\tIO_AR37: inout bit; --  PAD210\n\tIO_AR38: inout bit; --  PAD206\n\tIO_AR39: inout bit; --  PAD207\n\tIO_AR40: inout bit; --  PAD215\n\tIO_AR42: inout bit; --  PAD220\n\tIO_AT21: inout bit; --  PAD680\n\tIO_AT22: inout bit; --  PAD674\n\tIO_AT24: inout bit; --  PAD683\n\tIO_AT30: inout bit; --  PAD339\n\tIO_AT31: inout bit; --  PAD350\n\tIO_AT32: inout bit; --  PAD318\n\tIO_AT34: inout bit; --  PAD314\n\tIO_AT35: inout bit; --  PAD321\n\tIO_AT36: inout bit; --  PAD316\n\tIO_AT37: inout bit; --  PAD211\n\tIO_AT39: inout bit; --  PAD218\n\tIO_AT40: inout bit; --  PAD219\n\tIO_AT41: inout bit; --  PAD240\n\tIO_AT42: inout bit; --  PAD221\n\tIO_AU21: inout bit; --  PAD681\n\tIO_AU22: inout bit; --  PAD675\n\tIO_AU23: inout bit; --  PAD676\n\tIO_AU24: inout bit; --  PAD686\n\tIO_AU31: inout bit; --  PAD340\n\tIO_AU32: inout bit; --  PAD322\n\tIO_AU33: inout bit; --  PAD319\n\tIO_AU34: inout bit; --  PAD315\n\tIO_AU36: inout bit; --  PAD317\n\tIO_AU37: inout bit; --  PAD250\n\tIO_AU38: inout bit; --  PAD224\n\tIO_AU39: inout bit; --  PAD222\n\tIO_AU41: inout bit; --  PAD244\n\tIO_AU42: inout bit; --  PAD241\n\tIO_AV21: inout bit; --  PAD684\n\tIO_AV23: inout bit; --  PAD677\n\tIO_AV24: inout bit; --  PAD687\n\tIO_AV30: inout bit; --  PAD336\n\tIO_AV31: inout bit; --  PAD341\n\tIO_AV33: inout bit; --  PAD323\n\tIO_AV34: inout bit; --  PAD326\n\tIO_AV35: inout bit; --  PAD327\n\tIO_AV36: inout bit; --  PAD304\n\tIO_AV38: inout bit; --  PAD225\n\tIO_AV39: inout bit; --  PAD223\n\tIO_AV40: inout bit; --  PAD226\n\tIO_AV41: inout bit; --  PAD245\n\tIO_AW21: inout bit; --  PAD685\n\tIO_AW22: inout bit; --  PAD679\n\tIO_AW23: inout bit; --  PAD678\n\tIO_AW30: inout bit; --  PAD332\n\tIO_AW31: inout bit; --  PAD337\n\tIO_AW32: inout bit; --  PAD324\n\tIO_AW33: inout bit; --  PAD325\n\tIO_AW35: inout bit; --  PAD312\n\tIO_AW36: inout bit; --  PAD305\n\tIO_AW37: inout bit; --  PAD230\n\tIO_AW38: inout bit; --  PAD234\n\tIO_AW40: inout bit; --  PAD227\n\tIO_AW41: inout bit; --  PAD248\n\tIO_AW42: inout bit; --  PAD249\n\tIO_AY22: inout bit; --  PAD689\n\tIO_AY23: inout bit; --  PAD688\n\tIO_AY24: inout bit; --  PAD694\n\tIO_AY25: inout bit; --  PAD690\n\tIO_AY30: inout bit; --  PAD333\n\tIO_AY32: inout bit; --  PAD328\n\tIO_AY33: inout bit; --  PAD329\n\tIO_AY34: inout bit; --  PAD302\n\tIO_AY35: inout bit; --  PAD313\n\tIO_AY37: inout bit; --  PAD231\n\tIO_AY38: inout bit; --  PAD235\n\tIO_AY39: inout bit; --  PAD228\n\tIO_AY40: inout bit; --  PAD229\n\tIO_AY42: inout bit; --  PAD242\n\tIO_BA21: inout bit; --  PAD696\n\tIO_BA22: inout bit; --  PAD692\n\tIO_BA24: inout bit; --  PAD695\n\tIO_BA25: inout bit; --  PAD691\n\tIO_BA30: inout bit; --  PAD334\n\tIO_BA31: inout bit; --  PAD330\n\tIO_BA32: inout bit; --  PAD331\n\tIO_BA34: inout bit; --  PAD306\n\tIO_BA35: inout bit; --  PAD303\n\tIO_BA36: inout bit; --  PAD308\n\tIO_BA37: inout bit; --  PAD232\n\tIO_BA39: inout bit; --  PAD238\n\tIO_BA40: inout bit; --  PAD239\n\tIO_BA41: inout bit; --  PAD246\n\tIO_BA42: inout bit; --  PAD243\n\tIO_BB21: inout bit; --  PAD697\n\tIO_BB22: inout bit; --  PAD693\n\tIO_BB23: inout bit; --  PAD699\n\tIO_BB24: inout bit; --  PAD698\n\tIO_BB31: inout bit; --  PAD335\n\tIO_BB32: inout bit; --  PAD310\n\tIO_BB33: inout bit; --  PAD311\n\tIO_BB34: inout bit; --  PAD307\n\tIO_BB36: inout bit; --  PAD309\n\tIO_BB37: inout bit; --  PAD233\n\tIO_BB38: inout bit; --  PAD236\n\tIO_BB39: inout bit; --  PAD237\n\tIO_BB41: inout bit --  PAD247\n); --end port list\n\n-- Use Statements\n\nuse STD_1149_1_2001.all;\nuse STD_1149_6_2003.all;\n\n-- Component Conformance Statement(s)\n\nattribute COMPONENT_CONFORMANCE of XC7VX485T_FFG1761 : entity is\n\t\"STD_1149_1_2001\";\n\n-- Device Package Pin Mappings\n\nattribute PIN_MAP of XC7VX485T_FFG1761 : entity is PHYSICAL_PIN_MAP;\n\nconstant FFG1761: PIN_MAP_STRING:=\n\t\"CCLK_N10:N10,\" &\n\t\"CFGBVS_AH10:AH10,\" &\n\t\"DONE_AL11:AL11,\" &\n\t\"GND:(A2,A3,A4,A7,A8,A11,A13,A18,A28,A38,\" &\n\t\t\"B1,B2,B5,B9,B10,B12,B13,B15,B25,B35,\" &\n\t\t\"C3,C7,C11,C12,C22,C32,C42,D1,D2,D5,\" &\n\t\t\"D9,D10,D11,D19,D29,D39,E3,E7,E11,E16,\" &\n\t\t\"E26,E36,F1,F2,F5,F9,F10,F11,F13,F23,\" &\n\t\t\"F33,G3,G7,G11,G20,G30,G40,H1,H2,H5,\" &\n\t\t\"H9,H10,H11,H17,H27,H37,J3,J7,J9,J10,\" &\n\t\t\"J14,J24,J34,K1,K2,K5,K6,K9,K10,K11,\" &\n\t\t\"K21,K31,K41,L3,L7,L9,L10,L18,L28,L38,\" &\n\t\t\"M1,M2,M5,M6,M9,M15,M25,M35,N3,N7,\" &\n\t\t\"N9,N12,N22,N32,N42,P1,P2,P5,P9,P12,\" &\n\t\t\"P16,P19,P29,P39,R3,R7,R9,R11,R13,R15,\" &\n\t\t\"R17,R19,R21,R23,R25,R27,R36,T1,T2,T5,\" &\n\t\t\"T6,T9,T12,T14,T16,T18,T20,T22,T24,T26,\" &\n\t\t\"T33,U3,U4,U7,U9,U10,U11,U13,U15,U17,\" &\n\t\t\"U19,U21,U23,U25,U27,U30,U40,V1,V2,V5,\" &\n\t\t\"V6,V9,V10,V12,V14,V16,V18,V20,V22,V24,\" &\n\t\t\"V26,V28,V37,W3,W7,W11,W13,W15,W17,W19,\" &\n\t\t\"W21,W23,W25,W27,W34,Y1,Y2,Y5,Y6,Y9,\" &\n\t\t\"Y10,Y12,Y14,Y16,Y18,Y22,Y24,Y26,Y28,Y31,\" &\n\t\t\"Y41,AA3,AA7,AA9,AA11,AA13,AA15,AA17,AA19,AA23,\" &\n\t\t\"AA25,AA27,AA38,AB1,AB2,AB5,AB6,AB9,AB10,AB12,\" &\n\t\t\"AB14,AB16,AB18,AB22,AB24,AB26,AB28,AB35,AC3,AC7,\" &\n\t\t\"AC11,AC13,AC15,AC17,AC19,AC23,AC25,AC27,AC32,AC42,\" &\n\t\t\"AD1,AD2,AD5,AD6,AD9,AD10,AD12,AD14,AD16,AD18,\" &\n\t\t\"AD20,AD22,AD24,AD26,AD28,AD29,AD39,AE3,AE7,AE9,\" &\n\t\t\"AE11,AE13,AE15,AE17,AE19,AE21,AE23,AE25,AE27,AE36,\" &\n\t\t\"AF1,AF2,AF5,AF6,AF9,AF10,AF12,AF14,AF16,AF18,\" &\n\t\t\"AF20,AF22,AF24,AF26,AF33,AG3,AG4,AG7,AG8,AG9,\" &\n\t\t\"AG10,AG13,AG15,AG17,AG19,AG21,AG23,AG25,AG27,AG30,\" &\n\t\t\"AG40,AH1,AH2,AH5,AH6,AH9,AH12,AH14,AH16,AH17,\" &\n\t\t\"AH18,AH20,AH22,AH24,AH26,AH37,AJ3,AJ7,AJ9,AJ14,\" &\n\t\t\"AJ24,AJ27,AJ34,AK1,AK2,AK5,AK6,AK9,AK11,AK21,\" &\n\t\t\"AK31,AK41,AL3,AL7,AL9,AL18,AL28,AL38,AM1,AM2,\" &\n\t\t\"AM5,AM9,AM10,AM15,AM25,AM35,AN3,AN7,AN9,AN10,\" &\n\t\t\"AN12,AN22,AN32,AN42,AP1,AP2,AP5,AP9,AP10,AP19,\" &\n\t\t\"AP29,AP39,AR3,AR7,AR9,AR10,AR16,AR26,AR36,AT1,\" &\n\t\t\"AT2,AT5,AT6,AT9,AT10,AT11,AT13,AT23,AT33,AU3,\" &\n\t\t\"AU7,AU11,AU20,AU30,AU40,AV1,AV2,AV5,AV9,AV10,\" &\n\t\t\"AV11,AV17,AV27,AV37,AW3,AW7,AW11,AW14,AW24,AW34,\" &\n\t\t\"AY1,AY2,AY5,AY9,AY10,AY11,AY21,AY31,AY41,BA3,\" &\n\t\t\"BA7,BA11,BA18,BA28,BA38,BB2,BB5,BB6,BB9,BB10,\" &\n\t\t\"BB11,BB15,BB25,BB35),\" &\n\t\"GNDADC_0:Y20,\" &\n\t\"INIT_B_AG11:AG11,\" &\n\t\"M0_AL10:AL10,\" &\n\t\"M1_AK10:AK10,\" &\n\t\"M2_AJ10:AJ10,\" &\n\t\"MGTAVCC_G10:(W8,AA8,AC8,AE8,AJ8,AL8,AN8,AR8,AU8,AW8,\" &\n\t\t\"BA8),\" &\n\t\"MGTAVCC_G11:(C8,E8,G8,J8,L8),\" &\n\t\"MGTAVTTRCAL_115:A12,\" &\n\t\"MGTAVTT_G10:(R4,W4,AA4,AC4,AE4,AJ4,AL4,AM6,AN4,AP6,\" &\n\t\t\"AR4,AU4,AV6,AW4,AY6,BA4),\" &\n\t\"MGTAVTT_G11:(B6,C4,D6,E4,F6,G4,H6,J4,L4,N4,\" &\n\t\t\"P6),\" &\n\t\"MGTREFCLK0N_113:AH7,\" &\n\t\"MGTREFCLK0N_114:AD7,\" &\n\t\"MGTREFCLK0N_115:Y7,\" &\n\t\"MGTREFCLK0N_116:T7,\" &\n\t\"MGTREFCLK0N_117:K7,\" &\n\t\"MGTREFCLK0N_118:E9,\" &\n\t\"MGTREFCLK0N_119:A9,\" &\n\t\"MGTREFCLK0P_113:AH8,\" &\n\t\"MGTREFCLK0P_114:AD8,\" &\n\t\"MGTREFCLK0P_115:Y8,\" &\n\t\"MGTREFCLK0P_116:T8,\" &\n\t\"MGTREFCLK0P_117:K8,\" &\n\t\"MGTREFCLK0P_118:E10,\" &\n\t\"MGTREFCLK0P_119:A10,\" &\n\t\"MGTREFCLK1N_113:AK7,\" &\n\t\"MGTREFCLK1N_114:AF7,\" &\n\t\"MGTREFCLK1N_115:AB7,\" &\n\t\"MGTREFCLK1N_116:V7,\" &\n\t\"MGTREFCLK1N_117:M7,\" &\n\t\"MGTREFCLK1N_118:G9,\" &\n\t\"MGTREFCLK1N_119:C9,\" &\n\t\"MGTREFCLK1P_113:AK8,\" &\n\t\"MGTREFCLK1P_114:AF8,\" &\n\t\"MGTREFCLK1P_115:AB8,\" &\n\t\"MGTREFCLK1P_116:V8,\" &\n\t\"MGTREFCLK1P_117:M8,\" &\n\t\"MGTREFCLK1P_118:G10,\" &\n\t\"MGTREFCLK1P_119:C10,\" &\n\t\"MGTRREF_115:B11,\" &\n\t\"MGTVCCAUX_G10:(R8,U8),\" &\n\t\"MGTVCCAUX_G11:N8,\" &\n\t\"MGTXRXN0_113:AN5,\" &\n\t\"MGTXRXN0_114:AG5,\" &\n\t\"MGTXRXN0_115:AC5,\" &\n\t\"MGTXRXN0_116:W5,\" &\n\t\"MGTXRXN0_117:P7,\" &\n\t\"MGTXRXN0_118:H7,\" &\n\t\"MGTXRXN0_119:D7,\" &\n\t\"MGTXRXN1_113:AM7,\" &\n\t\"MGTXRXN1_114:AF3,\" &\n\t\"MGTXRXN1_115:AB3,\" &\n\t\"MGTXRXN1_116:V3,\" &\n\t\"MGTXRXN1_117:N5,\" &\n\t\"MGTXRXN1_118:G5,\" &\n\t\"MGTXRXN1_119:C5,\" &\n\t\"MGTXRXN2_113:AL5,\" &\n\t\"MGTXRXN2_114:AE5,\" &\n\t\"MGTXRXN2_115:AA5,\" &\n\t\"MGTXRXN2_116:U5,\" &\n\t\"MGTXRXN2_117:L5,\" &\n\t\"MGTXRXN2_118:F7,\" &\n\t\"MGTXRXN2_119:B7,\" &\n\t\"MGTXRXN3_113:AJ5,\" &\n\t\"MGTXRXN3_114:AD3,\" &\n\t\"MGTXRXN3_115:Y3,\" &\n\t\"MGTXRXN3_116:R5,\" &\n\t\"MGTXRXN3_117:J5,\" &\n\t\"MGTXRXN3_118:E5,\" &\n\t\"MGTXRXN3_119:A5,\" &\n\t\"MGTXRXP0_113:AN6,\" &\n\t\"MGTXRXP0_114:AG6,\" &\n\t\"MGTXRXP0_115:AC6,\" &\n\t\"MGTXRXP0_116:W6,\" &\n\t\"MGTXRXP0_117:P8,\" &\n\t\"MGTXRXP0_118:H8,\" &\n\t\"MGTXRXP0_119:D8,\" &\n\t\"MGTXRXP1_113:AM8,\" &\n\t\"MGTXRXP1_114:AF4,\" &\n\t\"MGTXRXP1_115:AB4,\" &\n\t\"MGTXRXP1_116:V4,\" &\n\t\"MGTXRXP1_117:N6,\" &\n\t\"MGTXRXP1_118:G6,\" &\n\t\"MGTXRXP1_119:C6,\" &\n\t\"MGTXRXP2_113:AL6,\" &\n\t\"MGTXRXP2_114:AE6,\" &\n\t\"MGTXRXP2_115:AA6,\" &\n\t\"MGTXRXP2_116:U6,\" &\n\t\"MGTXRXP2_117:L6,\" &\n\t\"MGTXRXP2_118:F8,\" &\n\t\"MGTXRXP2_119:B8,\" &\n\t\"MGTXRXP3_113:AJ6,\" &\n\t\"MGTXRXP3_114:AD4,\" &\n\t\"MGTXRXP3_115:Y4,\" &\n\t\"MGTXRXP3_116:R6,\" &\n\t\"MGTXRXP3_117:J6,\" &\n\t\"MGTXRXP3_118:E6,\" &\n\t\"MGTXRXP3_119:A6,\" &\n\t\"MGTXTXN0_113:AP3,\" &\n\t\"MGTXTXN0_114:AK3,\" &\n\t\"MGTXTXN0_115:AE1,\" &\n\t\"MGTXTXN0_116:U1,\" &\n\t\"MGTXTXN0_117:N1,\" &\n\t\"MGTXTXN0_118:J1,\" &\n\t\"MGTXTXN0_119:E1,\" &\n\t\"MGTXTXN1_113:AN1,\" &\n\t\"MGTXTXN1_114:AJ1,\" &\n\t\"MGTXTXN1_115:AC1,\" &\n\t\"MGTXTXN1_116:T3,\" &\n\t\"MGTXTXN1_117:M3,\" &\n\t\"MGTXTXN1_118:H3,\" &\n\t\"MGTXTXN1_119:D3,\" &\n\t\"MGTXTXN2_113:AM3,\" &\n\t\"MGTXTXN2_114:AH3,\" &\n\t\"MGTXTXN2_115:AA1,\" &\n\t\"MGTXTXN2_116:R1,\" &\n\t\"MGTXTXN2_117:L1,\" &\n\t\"MGTXTXN2_118:G1,\" &\n\t\"MGTXTXN2_119:C1,\" &\n\t\"MGTXTXN3_113:AL1,\" &\n\t\"MGTXTXN3_114:AG1,\" &\n\t\"MGTXTXN3_115:W1,\" &\n\t\"MGTXTXN3_116:P3,\" &\n\t\"MGTXTXN3_117:K3,\" &\n\t\"MGTXTXN3_118:F3,\" &\n\t\"MGTXTXN3_119:B3,\" &\n\t\"MGTXTXP0_113:AP4,\" &\n\t\"MGTXTXP0_114:AK4,\" &\n\t\"MGTXTXP0_115:AE2,\" &\n\t\"MGTXTXP0_116:U2,\" &\n\t\"MGTXTXP0_117:N2,\" &\n\t\"MGTXTXP0_118:J2,\" &\n\t\"MGTXTXP0_119:E2,\" &\n\t\"MGTXTXP1_113:AN2,\" &\n\t\"MGTXTXP1_114:AJ2,\" &\n\t\"MGTXTXP1_115:AC2,\" &\n\t\"MGTXTXP1_116:T4,\" &\n\t\"MGTXTXP1_117:M4,\" &\n\t\"MGTXTXP1_118:H4,\" &\n\t\"MGTXTXP1_119:D4,\" &\n\t\"MGTXTXP2_113:AM4,\" &\n\t\"MGTXTXP2_114:AH4,\" &\n\t\"MGTXTXP2_115:AA2,\" &\n\t\"MGTXTXP2_116:R2,\" &\n\t\"MGTXTXP2_117:L2,\" &\n\t\"MGTXTXP2_118:G2,\" &\n\t\"MGTXTXP2_119:C2,\" &\n\t\"MGTXTXP3_113:AL2,\" &\n\t\"MGTXTXP3_114:AG2,\" &\n\t\"MGTXTXP3_115:W2,\" &\n\t\"MGTXTXP3_116:P4,\" &\n\t\"MGTXTXP3_117:K4,\" &\n\t\"MGTXTXP3_118:F4,\" &\n\t\"MGTXTXP3_119:B4,\" &\n\t\"NOCONNECT:(W9,W10,AC9,AC10,AJ12,AJ13,AJ15,AJ16,AJ17,AJ18,\" &\n\t\t\"AJ25,AJ26,AK12,AK13,AK14,AK15,AK17,AK18,AK19,AK24,\" &\n\t\t\"AK25,AK27,AL12,AL14,AL15,AL16,AL17,AL19,AL25,AL26,\" &\n\t\t\"AL27,AM11,AM12,AM13,AM14,AM16,AM17,AM18,AM19,AM26,\" &\n\t\t\"AM27,AM28,AM29,AN11,AN13,AN14,AN15,AN16,AN18,AN19,\" &\n\t\t\"AN25,AN26,AN28,AN29,AP7,AP8,AP11,AP12,AP13,AP15,\" &\n\t\t\"AP16,AP17,AP18,AP20,AP25,AP26,AP27,AP28,AR1,AR2,\" &\n\t\t\"AR5,AR6,AR12,AR13,AR14,AR15,AR17,AR18,AR19,AR20,\" &\n\t\t\"AR25,AR27,AR28,AR29,AT3,AT4,AT7,AT8,AT12,AT14,\" &\n\t\t\"AT15,AT16,AT17,AT19,AT20,AT25,AT26,AT27,AT29,AU1,\" &\n\t\t\"AU2,AU5,AU6,AU9,AU10,AU12,AU13,AU14,AU16,AU17,\" &\n\t\t\"AU18,AU19,AU26,AU27,AU28,AU29,AV3,AV4,AV7,AV8,\" &\n\t\t\"AV13,AV14,AV15,AV16,AV18,AV19,AV20,AV25,AV26,AV28,\" &\n\t\t\"AV29,AW1,AW2,AW5,AW6,AW9,AW10,AW12,AW13,AW15,\" &\n\t\t\"AW16,AW17,AW18,AW20,AW25,AW26,AW27,AW28,AY3,AY4,\" &\n\t\t\"AY7,AY8,AY12,AY13,AY14,AY15,AY17,AY18,AY19,AY20,\" &\n\t\t\"AY27,AY28,AY29,BA1,BA2,BA5,BA6,BA9,BA10,BA12,\" &\n\t\t\"BA14,BA15,BA16,BA17,BA19,BA20,BA26,BA27,BA29,BB3,\" &\n\t\t\"BB4,BB7,BB8,BB12,BB13,BB14,BB16,BB17,BB18,BB19,\" &\n\t\t\"BB26,BB27,BB28,BB29),\" &\n\t\"PROGRAM_B:AJ11,\" &\n\t\"TCK:P10,\" &\n\t\"TDI:T10,\" &\n\t\"TDN_AC20:AC20,\" &\n\t\"TDO:R10,\" &\n\t\"TDP_AC21:AC21,\" &\n\t\"TMS:P11,\" &\n\t\"VCCADC_0:Y21,\" &\n\t\"VCCAUX:(R18,R26,T17,T19,T25,U18,U26,V17,V25,W18,\" &\n\t\t\"W26,Y17,Y25,AA18,AA26,AB17,AB25,AC18,AC26,AD17,\" &\n\t\t\"AD25,AE18,AE26,AF17,AF19,AF25,AG18,AG26,AH25),\" &\n\t\"VCCBATT_0:N11,\" &\n\t\"VCCBRAM:(R22,U22,W22,AA22,AC22,AE22,AG22,AH21),\" &\n\t\"VCCINT:(P13,P15,P27,R12,R14,R16,R20,R24,T13,T15,\" &\n\t\t\"T21,T23,T27,U12,U14,U16,U20,U24,V11,V13,\" &\n\t\t\"V15,V19,V21,V23,V27,W12,W14,W16,W20,W24,\" &\n\t\t\"W28,Y11,Y13,Y15,Y19,Y23,Y27,AA10,AA12,AA14,\" &\n\t\t\"AA16,AA24,AA28,AB11,AB13,AB15,AB19,AB23,AB27,AC12,\" &\n\t\t\"AC14,AC16,AC24,AC28,AD11,AD13,AD15,AD19,AD21,AD23,\" &\n\t\t\"AD27,AE10,AE12,AE14,AE16,AE20,AE24,AE28,AF11,AF13,\" &\n\t\t\"AF15,AF21,AF23,AF27,AG12,AG14,AG16,AG20,AG24,AG28,\" &\n\t\t\"AH11,AH13,AH15,AH19,AH23,AH27),\" &\n\t\"VCCO_0:(M10,T11),\" &\n\t\"VCCO_12:(AK26,AN27,AT28,AU25,AW29,AY26),\" &\n\t\"VCCO_13:(AP34,AR31,AU35,AV32,AY36,BA33,BB30),\" &\n\t\"VCCO_14:(AF28,AH32,AJ29,AK36,AL33,AM30,AN37),\" &\n\t\"VCCO_15:(AM40,AR41,AT38,AV42,AW39,BB40),\" &\n\t\"VCCO_16:(Y36,AA33,AB30,AD34,AE31,AG35),\" &\n\t\"VCCO_17:(AB40,AC37,AE41,AF38,AH42,AJ39),\" &\n\t\"VCCO_18:(P34,T38,U35,V32,V42,W39),\" &\n\t\"VCCO_19:(B40,E41,H42,J39,M40,N37,R41),\" &\n\t\"VCCO_31:(AK16,AL13,AP14,AR11,AU15,AV12,BA13),\" &\n\t\"VCCO_32:(AJ19,AN17,AT18,AW19,AY16,BB20),\" &\n\t\"VCCO_33:(AL23,AM20,AP24,AR21,AV22,BA23),\" &\n\t\"VCCO_34:(H32,L33,M30,R31,T28,W29),\" &\n\t\"VCCO_35:(A33,C37,D34,E31,F38,G35,K36),\" &\n\t\"VCCO_36:(G25,H22,J29,K26,L23,N27,P24),\" &\n\t\"VCCO_37:(A23,B30,C27,D24,E21,F28),\" &\n\t\"VCCO_38:(B20,C17,F18,J19,M20,N17),\" &\n\t\"VCCO_39:(D14,G15,H12,K16,L13,P14),\" &\n\t\"VN_AB20:AB20,\" &\n\t\"VP_AA21:AA21,\" &\n\t\"VREFN_AA20:AA20,\" &\n\t\"VREFP_AB21:AB21,\" &\n\t\"IO_A14:A14,\" &\n\t\"IO_A15:A15,\" &\n\t\"IO_A16:A16,\" &\n\t\"IO_A17:A17,\" &\n\t\"IO_A19:A19,\" &\n\t\"IO_A20:A20,\" &\n\t\"IO_A21:A21,\" &\n\t\"IO_A22:A22,\" &\n\t\"IO_A24:A24,\" &\n\t\"IO_A25:A25,\" &\n\t\"IO_A26:A26,\" &\n\t\"IO_A27:A27,\" &\n\t\"IO_A29:A29,\" &\n\t\"IO_A30:A30,\" &\n\t\"IO_A31:A31,\" &\n\t\"IO_A32:A32,\" &\n\t\"IO_A34:A34,\" &\n\t\"IO_A35:A35,\" &\n\t\"IO_A36:A36,\" &\n\t\"IO_A37:A37,\" &\n\t\"IO_A39:A39,\" &\n\t\"IO_A40:A40,\" &\n\t\"IO_A41:A41,\" &\n\t\"IO_B14:B14,\" &\n\t\"IO_B16:B16,\" &\n\t\"IO_B17:B17,\" &\n\t\"IO_B18:B18,\" &\n\t\"IO_B19:B19,\" &\n\t\"IO_B21:B21,\" &\n\t\"IO_B22:B22,\" &\n\t\"IO_B23:B23,\" &\n\t\"IO_B24:B24,\" &\n\t\"IO_B26:B26,\" &\n\t\"IO_B27:B27,\" &\n\t\"IO_B28:B28,\" &\n\t\"IO_B29:B29,\" &\n\t\"IO_B31:B31,\" &\n\t\"IO_B32:B32,\" &\n\t\"IO_B33:B33,\" &\n\t\"IO_B34:B34,\" &\n\t\"IO_B36:B36,\" &\n\t\"IO_B37:B37,\" &\n\t\"IO_B38:B38,\" &\n\t\"IO_B39:B39,\" &\n\t\"IO_B41:B41,\" &\n\t\"IO_B42:B42,\" &\n\t\"IO_C13:C13,\" &\n\t\"IO_C14:C14,\" &\n\t\"IO_C15:C15,\" &\n\t\"IO_C16:C16,\" &\n\t\"IO_C18:C18,\" &\n\t\"IO_C19:C19,\" &\n\t\"IO_C20:C20,\" &\n\t\"IO_C21:C21,\" &\n\t\"IO_C23:C23,\" &\n\t\"IO_C24:C24,\" &\n\t\"IO_C25:C25,\" &\n\t\"IO_C26:C26,\" &\n\t\"IO_C28:C28,\" &\n\t\"IO_C29:C29,\" &\n\t\"IO_C30:C30,\" &\n\t\"IO_C31:C31,\" &\n\t\"IO_C33:C33,\" &\n\t\"IO_C34:C34,\" &\n\t\"IO_C35:C35,\" &\n\t\"IO_C36:C36,\" &\n\t\"IO_C38:C38,\" &\n\t\"IO_C39:C39,\" &\n\t\"IO_C40:C40,\" &\n\t\"IO_C41:C41,\" &\n\t\"IO_D12:D12,\" &\n\t\"IO_D13:D13,\" &\n\t\"IO_D15:D15,\" &\n\t\"IO_D16:D16,\" &\n\t\"IO_D17:D17,\" &\n\t\"IO_D18:D18,\" &\n\t\"IO_D20:D20,\" &\n\t\"IO_D21:D21,\" &\n\t\"IO_D22:D22,\" &\n\t\"IO_D23:D23,\" &\n\t\"IO_D25:D25,\" &\n\t\"IO_D26:D26,\" &\n\t\"IO_D27:D27,\" &\n\t\"IO_D28:D28,\" &\n\t\"IO_D30:D30,\" &\n\t\"IO_D31:D31,\" &\n\t\"IO_D32:D32,\" &\n\t\"IO_D33:D33,\" &\n\t\"IO_D35:D35,\" &\n\t\"IO_D36:D36,\" &\n\t\"IO_D37:D37,\" &\n\t\"IO_D38:D38,\" &\n\t\"IO_D40:D40,\" &\n\t\"IO_D41:D41,\" &\n\t\"IO_D42:D42,\" &\n\t\"IO_E12:E12,\" &\n\t\"IO_E13:E13,\" &\n\t\"IO_E14:E14,\" &\n\t\"IO_E15:E15,\" &\n\t\"IO_E17:E17,\" &\n\t\"IO_E18:E18,\" &\n\t\"IO_E19:E19,\" &\n\t\"IO_E20:E20,\" &\n\t\"IO_E22:E22,\" &\n\t\"IO_E23:E23,\" &\n\t\"IO_E24:E24,\" &\n\t\"IO_E25:E25,\" &\n\t\"IO_E27:E27,\" &\n\t\"IO_E28:E28,\" &\n\t\"IO_E29:E29,\" &\n\t\"IO_E30:E30,\" &\n\t\"IO_E32:E32,\" &\n\t\"IO_E33:E33,\" &\n\t\"IO_E34:E34,\" &\n\t\"IO_E35:E35,\" &\n\t\"IO_E37:E37,\" &\n\t\"IO_E38:E38,\" &\n\t\"IO_E39:E39,\" &\n\t\"IO_E40:E40,\" &\n\t\"IO_E42:E42,\" &\n\t\"IO_F12:F12,\" &\n\t\"IO_F14:F14,\" &\n\t\"IO_F15:F15,\" &\n\t\"IO_F16:F16,\" &\n\t\"IO_F17:F17,\" &\n\t\"IO_F19:F19,\" &\n\t\"IO_F20:F20,\" &\n\t\"IO_F21:F21,\" &\n\t\"IO_F22:F22,\" &\n\t\"IO_F24:F24,\" &\n\t\"IO_F25:F25,\" &\n\t\"IO_F26:F26,\" &\n\t\"IO_F27:F27,\" &\n\t\"IO_F29:F29,\" &\n\t\"IO_F30:F30,\" &\n\t\"IO_F31:F31,\" &\n\t\"IO_F32:F32,\" &\n\t\"IO_F34:F34,\" &\n\t\"IO_F35:F35,\" &\n\t\"IO_F36:F36,\" &\n\t\"IO_F37:F37,\" &\n\t\"IO_F39:F39,\" &\n\t\"IO_F40:F40,\" &\n\t\"IO_F41:F41,\" &\n\t\"IO_F42:F42,\" &\n\t\"IO_G12:G12,\" &\n\t\"IO_G13:G13,\" &\n\t\"IO_G14:G14,\" &\n\t\"IO_G16:G16,\" &\n\t\"IO_G17:G17,\" &\n\t\"IO_G18:G18,\" &\n\t\"IO_G19:G19,\" &\n\t\"IO_G21:G21,\" &\n\t\"IO_G22:G22,\" &\n\t\"IO_G23:G23,\" &\n\t\"IO_G24:G24,\" &\n\t\"IO_G26:G26,\" &\n\t\"IO_G27:G27,\" &\n\t\"IO_G28:G28,\" &\n\t\"IO_G29:G29,\" &\n\t\"IO_G31:G31,\" &\n\t\"IO_G32:G32,\" &\n\t\"IO_G33:G33,\" &\n\t\"IO_G34:G34,\" &\n\t\"IO_G36:G36,\" &\n\t\"IO_G37:G37,\" &\n\t\"IO_G38:G38,\" &\n\t\"IO_G39:G39,\" &\n\t\"IO_G41:G41,\" &\n\t\"IO_G42:G42,\" &\n\t\"IO_H13:H13,\" &\n\t\"IO_H14:H14,\" &\n\t\"IO_H15:H15,\" &\n\t\"IO_H16:H16,\" &\n\t\"IO_H18:H18,\" &\n\t\"IO_H19:H19,\" &\n\t\"IO_H20:H20,\" &\n\t\"IO_H21:H21,\" &\n\t\"IO_H23:H23,\" &\n\t\"IO_H24:H24,\" &\n\t\"IO_H25:H25,\" &\n\t\"IO_H26:H26,\" &\n\t\"IO_H28:H28,\" &\n\t\"IO_H29:H29,\" &\n\t\"IO_H30:H30,\" &\n\t\"IO_H31:H31,\" &\n\t\"IO_H33:H33,\" &\n\t\"IO_H34:H34,\" &\n\t\"IO_H35:H35,\" &\n\t\"IO_H36:H36,\" &\n\t\"IO_H38:H38,\" &\n\t\"IO_H39:H39,\" &\n\t\"IO_H40:H40,\" &\n\t\"IO_H41:H41,\" &\n\t\"IO_J11:J11,\" &\n\t\"IO_J12:J12,\" &\n\t\"IO_J13:J13,\" &\n\t\"IO_J15:J15,\" &\n\t\"IO_J16:J16,\" &\n\t\"IO_J17:J17,\" &\n\t\"IO_J18:J18,\" &\n\t\"IO_J20:J20,\" &\n\t\"IO_J21:J21,\" &\n\t\"IO_J22:J22,\" &\n\t\"IO_J23:J23,\" &\n\t\"IO_J25:J25,\" &\n\t\"IO_J26:J26,\" &\n\t\"IO_J27:J27,\" &\n\t\"IO_J28:J28,\" &\n\t\"IO_J30:J30,\" &\n\t\"IO_J31:J31,\" &\n\t\"IO_J32:J32,\" &\n\t\"IO_J33:J33,\" &\n\t\"IO_J35:J35,\" &\n\t\"IO_J36:J36,\" &\n\t\"IO_J37:J37,\" &\n\t\"IO_J38:J38,\" &\n\t\"IO_J40:J40,\" &\n\t\"IO_J41:J41,\" &\n\t\"IO_J42:J42,\" &\n\t\"IO_K12:K12,\" &\n\t\"IO_K13:K13,\" &\n\t\"IO_K14:K14,\" &\n\t\"IO_K15:K15,\" &\n\t\"IO_K17:K17,\" &\n\t\"IO_K18:K18,\" &\n\t\"IO_K19:K19,\" &\n\t\"IO_K20:K20,\" &\n\t\"IO_K22:K22,\" &\n\t\"IO_K23:K23,\" &\n\t\"IO_K24:K24,\" &\n\t\"IO_K25:K25,\" &\n\t\"IO_K27:K27,\" &\n\t\"IO_K28:K28,\" &\n\t\"IO_K29:K29,\" &\n\t\"IO_K30:K30,\" &\n\t\"IO_K32:K32,\" &\n\t\"IO_K33:K33,\" &\n\t\"IO_K34:K34,\" &\n\t\"IO_K35:K35,\" &\n\t\"IO_K37:K37,\" &\n\t\"IO_K38:K38,\" &\n\t\"IO_K39:K39,\" &\n\t\"IO_K40:K40,\" &\n\t\"IO_K42:K42,\" &\n\t\"IO_L11:L11,\" &\n\t\"IO_L12:L12,\" &\n\t\"IO_L14:L14,\" &\n\t\"IO_L15:L15,\" &\n\t\"IO_L16:L16,\" &\n\t\"IO_L17:L17,\" &\n\t\"IO_L19:L19,\" &\n\t\"IO_L20:L20,\" &\n\t\"IO_L21:L21,\" &\n\t\"IO_L22:L22,\" &\n\t\"IO_L24:L24,\" &\n\t\"IO_L25:L25,\" &\n\t\"IO_L26:L26,\" &\n\t\"IO_L27:L27,\" &\n\t\"IO_L29:L29,\" &\n\t\"IO_L30:L30,\" &\n\t\"IO_L31:L31,\" &\n\t\"IO_L32:L32,\" &\n\t\"IO_L34:L34,\" &\n\t\"IO_L35:L35,\" &\n\t\"IO_L36:L36,\" &\n\t\"IO_L37:L37,\" &\n\t\"IO_L39:L39,\" &\n\t\"IO_L40:L40,\" &\n\t\"IO_L41:L41,\" &\n\t\"IO_L42:L42,\" &\n\t\"IO_M11:M11,\" &\n\t\"IO_M12:M12,\" &\n\t\"IO_M13:M13,\" &\n\t\"IO_M14:M14,\" &\n\t\"IO_M16:M16,\" &\n\t\"IO_M17:M17,\" &\n\t\"IO_M18:M18,\" &\n\t\"IO_M19:M19,\" &\n\t\"IO_M21:M21,\" &\n\t\"IO_M22:M22,\" &\n\t\"IO_M23:M23,\" &\n\t\"IO_M24:M24,\" &\n\t\"IO_M26:M26,\" &\n\t\"IO_M27:M27,\" &\n\t\"IO_M28:M28,\" &\n\t\"IO_M29:M29,\" &\n\t\"IO_M31:M31,\" &\n\t\"IO_M32:M32,\" &\n\t\"IO_M33:M33,\" &\n\t\"IO_M34:M34,\" &\n\t\"IO_M36:M36,\" &\n\t\"IO_M37:M37,\" &\n\t\"IO_M38:M38,\" &\n\t\"IO_M39:M39,\" &\n\t\"IO_M41:M41,\" &\n\t\"IO_M42:M42,\" &\n\t\"IO_N13:N13,\" &\n\t\"IO_N14:N14,\" &\n\t\"IO_N15:N15,\" &\n\t\"IO_N16:N16,\" &\n\t\"IO_N18:N18,\" &\n\t\"IO_N19:N19,\" &\n\t\"IO_N20:N20,\" &\n\t\"IO_N21:N21,\" &\n\t\"IO_N23:N23,\" &\n\t\"IO_N24:N24,\" &\n\t\"IO_N25:N25,\" &\n\t\"IO_N26:N26,\" &\n\t\"IO_N28:N28,\" &\n\t\"IO_N29:N29,\" &\n\t\"IO_N30:N30,\" &\n\t\"IO_N31:N31,\" &\n\t\"IO_N33:N33,\" &\n\t\"IO_N34:N34,\" &\n\t\"IO_N35:N35,\" &\n\t\"IO_N36:N36,\" &\n\t\"IO_N38:N38,\" &\n\t\"IO_N39:N39,\" &\n\t\"IO_N40:N40,\" &\n\t\"IO_N41:N41,\" &\n\t\"IO_P17:P17,\" &\n\t\"IO_P18:P18,\" &\n\t\"IO_P20:P20,\" &\n\t\"IO_P21:P21,\" &\n\t\"IO_P22:P22,\" &\n\t\"IO_P23:P23,\" &\n\t\"IO_P25:P25,\" &\n\t\"IO_P26:P26,\" &\n\t\"IO_P28:P28,\" &\n\t\"IO_P30:P30,\" &\n\t\"IO_P31:P31,\" &\n\t\"IO_P32:P32,\" &\n\t\"IO_P33:P33,\" &\n\t\"IO_P35:P35,\" &\n\t\"IO_P36:P36,\" &\n\t\"IO_P37:P37,\" &\n\t\"IO_P38:P38,\" &\n\t\"IO_P40:P40,\" &\n\t\"IO_P41:P41,\" &\n\t\"IO_P42:P42,\" &\n\t\"IO_R28:R28,\" &\n\t\"IO_R29:R29,\" &\n\t\"IO_R30:R30,\" &\n\t\"IO_R32:R32,\" &\n\t\"IO_R33:R33,\" &\n\t\"IO_R34:R34,\" &\n\t\"IO_R35:R35,\" &\n\t\"IO_R37:R37,\" &\n\t\"IO_R38:R38,\" &\n\t\"IO_R39:R39,\" &\n\t\"IO_R40:R40,\" &\n\t\"IO_R42:R42,\" &\n\t\"IO_T29:T29,\" &\n\t\"IO_T30:T30,\" &\n\t\"IO_T31:T31,\" &\n\t\"IO_T32:T32,\" &\n\t\"IO_T34:T34,\" &\n\t\"IO_T35:T35,\" &\n\t\"IO_T36:T36,\" &\n\t\"IO_T37:T37,\" &\n\t\"IO_T39:T39,\" &\n\t\"IO_T40:T40,\" &\n\t\"IO_T41:T41,\" &\n\t\"IO_T42:T42,\" &\n\t\"IO_U28:U28,\" &\n\t\"IO_U29:U29,\" &\n\t\"IO_U31:U31,\" &\n\t\"IO_U32:U32,\" &\n\t\"IO_U33:U33,\" &\n\t\"IO_U34:U34,\" &\n\t\"IO_U36:U36,\" &\n\t\"IO_U37:U37,\" &\n\t\"IO_U38:U38,\" &\n\t\"IO_U39:U39,\" &\n\t\"IO_U41:U41,\" &\n\t\"IO_U42:U42,\" &\n\t\"IO_V29:V29,\" &\n\t\"IO_V30:V30,\" &\n\t\"IO_V31:V31,\" &\n\t\"IO_V33:V33,\" &\n\t\"IO_V34:V34,\" &\n\t\"IO_V35:V35,\" &\n\t\"IO_V36:V36,\" &\n\t\"IO_V38:V38,\" &\n\t\"IO_V39:V39,\" &\n\t\"IO_V40:V40,\" &\n\t\"IO_V41:V41,\" &\n\t\"IO_W30:W30,\" &\n\t\"IO_W31:W31,\" &\n\t\"IO_W32:W32,\" &\n\t\"IO_W33:W33,\" &\n\t\"IO_W35:W35,\" &\n\t\"IO_W36:W36,\" &\n\t\"IO_W37:W37,\" &\n\t\"IO_W38:W38,\" &\n\t\"IO_W40:W40,\" &\n\t\"IO_W41:W41,\" &\n\t\"IO_W42:W42,\" &\n\t\"IO_Y29:Y29,\" &\n\t\"IO_Y30:Y30,\" &\n\t\"IO_Y32:Y32,\" &\n\t\"IO_Y33:Y33,\" &\n\t\"IO_Y34:Y34,\" &\n\t\"IO_Y35:Y35,\" &\n\t\"IO_Y37:Y37,\" &\n\t\"IO_Y38:Y38,\" &\n\t\"IO_Y39:Y39,\" &\n\t\"IO_Y40:Y40,\" &\n\t\"IO_Y42:Y42,\" &\n\t\"IO_AA29:AA29,\" &\n\t\"IO_AA30:AA30,\" &\n\t\"IO_AA31:AA31,\" &\n\t\"IO_AA32:AA32,\" &\n\t\"IO_AA34:AA34,\" &\n\t\"IO_AA35:AA35,\" &\n\t\"IO_AA36:AA36,\" &\n\t\"IO_AA37:AA37,\" &\n\t\"IO_AA39:AA39,\" &\n\t\"IO_AA40:AA40,\" &\n\t\"IO_AA41:AA41,\" &\n\t\"IO_AA42:AA42,\" &\n\t\"IO_AB29:AB29,\" &\n\t\"IO_AB31:AB31,\" &\n\t\"IO_AB32:AB32,\" &\n\t\"IO_AB33:AB33,\" &\n\t\"IO_AB34:AB34,\" &\n\t\"IO_AB36:AB36,\" &\n\t\"IO_AB37:AB37,\" &\n\t\"IO_AB38:AB38,\" &\n\t\"IO_AB39:AB39,\" &\n\t\"IO_AB41:AB41,\" &\n\t\"IO_AB42:AB42,\" &\n\t\"IO_AC29:AC29,\" &\n\t\"IO_AC30:AC30,\" &\n\t\"IO_AC31:AC31,\" &\n\t\"IO_AC33:AC33,\" &\n\t\"IO_AC34:AC34,\" &\n\t\"IO_AC35:AC35,\" &\n\t\"IO_AC36:AC36,\" &\n\t\"IO_AC38:AC38,\" &\n\t\"IO_AC39:AC39,\" &\n\t\"IO_AC40:AC40,\" &\n\t\"IO_AC41:AC41,\" &\n\t\"IO_AD30:AD30,\" &\n\t\"IO_AD31:AD31,\" &\n\t\"IO_AD32:AD32,\" &\n\t\"IO_AD33:AD33,\" &\n\t\"IO_AD35:AD35,\" &\n\t\"IO_AD36:AD36,\" &\n\t\"IO_AD37:AD37,\" &\n\t\"IO_AD38:AD38,\" &\n\t\"IO_AD40:AD40,\" &\n\t\"IO_AD41:AD41,\" &\n\t\"IO_AD42:AD42,\" &\n\t\"IO_AE29:AE29,\" &\n\t\"IO_AE30:AE30,\" &\n\t\"IO_AE32:AE32,\" &\n\t\"IO_AE33:AE33,\" &\n\t\"IO_AE34:AE34,\" &\n\t\"IO_AE35:AE35,\" &\n\t\"IO_AE37:AE37,\" &\n\t\"IO_AE38:AE38,\" &\n\t\"IO_AE39:AE39,\" &\n\t\"IO_AE40:AE40,\" &\n\t\"IO_AE42:AE42,\" &\n\t\"IO_AF29:AF29,\" &\n\t\"IO_AF30:AF30,\" &\n\t\"IO_AF31:AF31,\" &\n\t\"IO_AF32:AF32,\" &\n\t\"IO_AF34:AF34,\" &\n\t\"IO_AF35:AF35,\" &\n\t\"IO_AF36:AF36,\" &\n\t\"IO_AF37:AF37,\" &\n\t\"IO_AF39:AF39,\" &\n\t\"IO_AF40:AF40,\" &\n\t\"IO_AF41:AF41,\" &\n\t\"IO_AF42:AF42,\" &\n\t\"IO_AG29:AG29,\" &\n\t\"IO_AG31:AG31,\" &\n\t\"IO_AG32:AG32,\" &\n\t\"IO_AG33:AG33,\" &\n\t\"IO_AG34:AG34,\" &\n\t\"IO_AG36:AG36,\" &\n\t\"IO_AG37:AG37,\" &\n\t\"IO_AG38:AG38,\" &\n\t\"IO_AG39:AG39,\" &\n\t\"IO_AG41:AG41,\" &\n\t\"IO_AG42:AG42,\" &\n\t\"IO_AH28:AH28,\" &\n\t\"IO_AH29:AH29,\" &\n\t\"IO_AH30:AH30,\" &\n\t\"IO_AH31:AH31,\" &\n\t\"IO_AH33:AH33,\" &\n\t\"IO_AH34:AH34,\" &\n\t\"IO_AH35:AH35,\" &\n\t\"IO_AH36:AH36,\" &\n\t\"IO_AH38:AH38,\" &\n\t\"IO_AH39:AH39,\" &\n\t\"IO_AH40:AH40,\" &\n\t\"IO_AH41:AH41,\" &\n\t\"IO_AJ20:AJ20,\" &\n\t\"IO_AJ21:AJ21,\" &\n\t\"IO_AJ22:AJ22,\" &\n\t\"IO_AJ23:AJ23,\" &\n\t\"IO_AJ28:AJ28,\" &\n\t\"IO_AJ30:AJ30,\" &\n\t\"IO_AJ31:AJ31,\" &\n\t\"IO_AJ32:AJ32,\" &\n\t\"IO_AJ33:AJ33,\" &\n\t\"IO_AJ35:AJ35,\" &\n\t\"IO_AJ36:AJ36,\" &\n\t\"IO_AJ37:AJ37,\" &\n\t\"IO_AJ38:AJ38,\" &\n\t\"IO_AJ40:AJ40,\" &\n\t\"IO_AJ41:AJ41,\" &\n\t\"IO_AJ42:AJ42,\" &\n\t\"IO_AK20:AK20,\" &\n\t\"IO_AK22:AK22,\" &\n\t\"IO_AK23:AK23,\" &\n\t\"IO_AK28:AK28,\" &\n\t\"IO_AK29:AK29,\" &\n\t\"IO_AK30:AK30,\" &\n\t\"IO_AK32:AK32,\" &\n\t\"IO_AK33:AK33,\" &\n\t\"IO_AK34:AK34,\" &\n\t\"IO_AK35:AK35,\" &\n\t\"IO_AK37:AK37,\" &\n\t\"IO_AK38:AK38,\" &\n\t\"IO_AK39:AK39,\" &\n\t\"IO_AK40:AK40,\" &\n\t\"IO_AK42:AK42,\" &\n\t\"IO_AL20:AL20,\" &\n\t\"IO_AL21:AL21,\" &\n\t\"IO_AL22:AL22,\" &\n\t\"IO_AL24:AL24,\" &\n\t\"IO_AL29:AL29,\" &\n\t\"IO_AL30:AL30,\" &\n\t\"IO_AL31:AL31,\" &\n\t\"IO_AL32:AL32,\" &\n\t\"IO_AL34:AL34,\" &\n\t\"IO_AL35:AL35,\" &\n\t\"IO_AL36:AL36,\" &\n\t\"IO_AL37:AL37,\" &\n\t\"IO_AL39:AL39,\" &\n\t\"IO_AL40:AL40,\" &\n\t\"IO_AL41:AL41,\" &\n\t\"IO_AL42:AL42,\" &\n\t\"IO_AM21:AM21,\" &\n\t\"IO_AM22:AM22,\" &\n\t\"IO_AM23:AM23,\" &\n\t\"IO_AM24:AM24,\" &\n\t\"IO_AM31:AM31,\" &\n\t\"IO_AM32:AM32,\" &\n\t\"IO_AM33:AM33,\" &\n\t\"IO_AM34:AM34,\" &\n\t\"IO_AM36:AM36,\" &\n\t\"IO_AM37:AM37,\" &\n\t\"IO_AM38:AM38,\" &\n\t\"IO_AM39:AM39,\" &\n\t\"IO_AM41:AM41,\" &\n\t\"IO_AM42:AM42,\" &\n\t\"IO_AN20:AN20,\" &\n\t\"IO_AN21:AN21,\" &\n\t\"IO_AN23:AN23,\" &\n\t\"IO_AN24:AN24,\" &\n\t\"IO_AN30:AN30,\" &\n\t\"IO_AN31:AN31,\" &\n\t\"IO_AN33:AN33,\" &\n\t\"IO_AN34:AN34,\" &\n\t\"IO_AN35:AN35,\" &\n\t\"IO_AN36:AN36,\" &\n\t\"IO_AN38:AN38,\" &\n\t\"IO_AN39:AN39,\" &\n\t\"IO_AN40:AN40,\" &\n\t\"IO_AN41:AN41,\" &\n\t\"IO_AP21:AP21,\" &\n\t\"IO_AP22:AP22,\" &\n\t\"IO_AP23:AP23,\" &\n\t\"IO_AP30:AP30,\" &\n\t\"IO_AP31:AP31,\" &\n\t\"IO_AP32:AP32,\" &\n\t\"IO_AP33:AP33,\" &\n\t\"IO_AP35:AP35,\" &\n\t\"IO_AP36:AP36,\" &\n\t\"IO_AP37:AP37,\" &\n\t\"IO_AP38:AP38,\" &\n\t\"IO_AP40:AP40,\" &\n\t\"IO_AP41:AP41,\" &\n\t\"IO_AP42:AP42,\" &\n\t\"IO_AR22:AR22,\" &\n\t\"IO_AR23:AR23,\" &\n\t\"IO_AR24:AR24,\" &\n\t\"IO_AR30:AR30,\" &\n\t\"IO_AR32:AR32,\" &\n\t\"IO_AR33:AR33,\" &\n\t\"IO_AR34:AR34,\" &\n\t\"IO_AR35:AR35,\" &\n\t\"IO_AR37:AR37,\" &\n\t\"IO_AR38:AR38,\" &\n\t\"IO_AR39:AR39,\" &\n\t\"IO_AR40:AR40,\" &\n\t\"IO_AR42:AR42,\" &\n\t\"IO_AT21:AT21,\" &\n\t\"IO_AT22:AT22,\" &\n\t\"IO_AT24:AT24,\" &\n\t\"IO_AT30:AT30,\" &\n\t\"IO_AT31:AT31,\" &\n\t\"IO_AT32:AT32,\" &\n\t\"IO_AT34:AT34,\" &\n\t\"IO_AT35:AT35,\" &\n\t\"IO_AT36:AT36,\" &\n\t\"IO_AT37:AT37,\" &\n\t\"IO_AT39:AT39,\" &\n\t\"IO_AT40:AT40,\" &\n\t\"IO_AT41:AT41,\" &\n\t\"IO_AT42:AT42,\" &\n\t\"IO_AU21:AU21,\" &\n\t\"IO_AU22:AU22,\" &\n\t\"IO_AU23:AU23,\" &\n\t\"IO_AU24:AU24,\" &\n\t\"IO_AU31:AU31,\" &\n\t\"IO_AU32:AU32,\" &\n\t\"IO_AU33:AU33,\" &\n\t\"IO_AU34:AU34,\" &\n\t\"IO_AU36:AU36,\" &\n\t\"IO_AU37:AU37,\" &\n\t\"IO_AU38:AU38,\" &\n\t\"IO_AU39:AU39,\" &\n\t\"IO_AU41:AU41,\" &\n\t\"IO_AU42:AU42,\" &\n\t\"IO_AV21:AV21,\" &\n\t\"IO_AV23:AV23,\" &\n\t\"IO_AV24:AV24,\" &\n\t\"IO_AV30:AV30,\" &\n\t\"IO_AV31:AV31,\" &\n\t\"IO_AV33:AV33,\" &\n\t\"IO_AV34:AV34,\" &\n\t\"IO_AV35:AV35,\" &\n\t\"IO_AV36:AV36,\" &\n\t\"IO_AV38:AV38,\" &\n\t\"IO_AV39:AV39,\" &\n\t\"IO_AV40:AV40,\" &\n\t\"IO_AV41:AV41,\" &\n\t\"IO_AW21:AW21,\" &\n\t\"IO_AW22:AW22,\" &\n\t\"IO_AW23:AW23,\" &\n\t\"IO_AW30:AW30,\" &\n\t\"IO_AW31:AW31,\" &\n\t\"IO_AW32:AW32,\" &\n\t\"IO_AW33:AW33,\" &\n\t\"IO_AW35:AW35,\" &\n\t\"IO_AW36:AW36,\" &\n\t\"IO_AW37:AW37,\" &\n\t\"IO_AW38:AW38,\" &\n\t\"IO_AW40:AW40,\" &\n\t\"IO_AW41:AW41,\" &\n\t\"IO_AW42:AW42,\" &\n\t\"IO_AY22:AY22,\" &\n\t\"IO_AY23:AY23,\" &\n\t\"IO_AY24:AY24,\" &\n\t\"IO_AY25:AY25,\" &\n\t\"IO_AY30:AY30,\" &\n\t\"IO_AY32:AY32,\" &\n\t\"IO_AY33:AY33,\" &\n\t\"IO_AY34:AY34,\" &\n\t\"IO_AY35:AY35,\" &\n\t\"IO_AY37:AY37,\" &\n\t\"IO_AY38:AY38,\" &\n\t\"IO_AY39:AY39,\" &\n\t\"IO_AY40:AY40,\" &\n\t\"IO_AY42:AY42,\" &\n\t\"IO_BA21:BA21,\" &\n\t\"IO_BA22:BA22,\" &\n\t\"IO_BA24:BA24,\" &\n\t\"IO_BA25:BA25,\" &\n\t\"IO_BA30:BA30,\" &\n\t\"IO_BA31:BA31,\" &\n\t\"IO_BA32:BA32,\" &\n\t\"IO_BA34:BA34,\" &\n\t\"IO_BA35:BA35,\" &\n\t\"IO_BA36:BA36,\" &\n\t\"IO_BA37:BA37,\" &\n\t\"IO_BA39:BA39,\" &\n\t\"IO_BA40:BA40,\" &\n\t\"IO_BA41:BA41,\" &\n\t\"IO_BA42:BA42,\" &\n\t\"IO_BB21:BB21,\" &\n\t\"IO_BB22:BB22,\" &\n\t\"IO_BB23:BB23,\" &\n\t\"IO_BB24:BB24,\" &\n\t\"IO_BB31:BB31,\" &\n\t\"IO_BB32:BB32,\" &\n\t\"IO_BB33:BB33,\" &\n\t\"IO_BB34:BB34,\" &\n\t\"IO_BB36:BB36,\" &\n\t\"IO_BB37:BB37,\" &\n\t\"IO_BB38:BB38,\" &\n\t\"IO_BB39:BB39,\" &\n\t\"IO_BB41:BB41\";\n\n\n-- Grouped Port Identification\n\nattribute PORT_GROUPING of XC7VX485T_FFG1761 : entity is\n\"DIFFERENTIAL_VOLTAGE (\" &\n\"(MGTXRXP0_113, MGTXRXN0_113), \" &\n\"(MGTXRXP0_114, MGTXRXN0_114), \" &\n\"(MGTXRXP0_115, MGTXRXN0_115), \" &\n\"(MGTXRXP0_116, MGTXRXN0_116), \" &\n\"(MGTXRXP0_117, MGTXRXN0_117), \" &\n\"(MGTXRXP0_118, MGTXRXN0_118), \" &\n\"(MGTXRXP0_119, MGTXRXN0_119), \" &\n\"(MGTXRXP1_113, MGTXRXN1_113), \" &\n\"(MGTXRXP1_114, MGTXRXN1_114), \" &\n\"(MGTXRXP1_115, MGTXRXN1_115), \" &\n\"(MGTXRXP1_116, MGTXRXN1_116), \" &\n\"(MGTXRXP1_117, MGTXRXN1_117), \" &\n\"(MGTXRXP1_118, MGTXRXN1_118), \" &\n\"(MGTXRXP1_119, MGTXRXN1_119), \" &\n\"(MGTXRXP2_113, MGTXRXN2_113), \" &\n\"(MGTXRXP2_114, MGTXRXN2_114), \" &\n\"(MGTXRXP2_115, MGTXRXN2_115), \" &\n\"(MGTXRXP2_116, MGTXRXN2_116), \" &\n\"(MGTXRXP2_117, MGTXRXN2_117), \" &\n\"(MGTXRXP2_118, MGTXRXN2_118), \" &\n\"(MGTXRXP2_119, MGTXRXN2_119), \" &\n\"(MGTXRXP3_113, MGTXRXN3_113), \" &\n\"(MGTXRXP3_114, MGTXRXN3_114), \" &\n\"(MGTXRXP3_115, MGTXRXN3_115), \" &\n\"(MGTXRXP3_116, MGTXRXN3_116), \" &\n\"(MGTXRXP3_117, MGTXRXN3_117), \" &\n\"(MGTXRXP3_118, MGTXRXN3_118), \" &\n\"(MGTXRXP3_119, MGTXRXN3_119), \" &\n\"(MGTXTXP0_113, MGTXTXN0_113), \" &\n\"(MGTXTXP0_114, MGTXTXN0_114), \" &\n\"(MGTXTXP0_115, MGTXTXN0_115), \" &\n\"(MGTXTXP0_116, MGTXTXN0_116), \" &\n\"(MGTXTXP0_117, MGTXTXN0_117), \" &\n\"(MGTXTXP0_118, MGTXTXN0_118), \" &\n\"(MGTXTXP0_119, MGTXTXN0_119), \" &\n\"(MGTXTXP1_113, MGTXTXN1_113), \" &\n\"(MGTXTXP1_114, MGTXTXN1_114), \" &\n\"(MGTXTXP1_115, MGTXTXN1_115), \" &\n\"(MGTXTXP1_116, MGTXTXN1_116), \" &\n\"(MGTXTXP1_117, MGTXTXN1_117), \" &\n\"(MGTXTXP1_118, MGTXTXN1_118), \" &\n\"(MGTXTXP1_119, MGTXTXN1_119), \" &\n\"(MGTXTXP2_113, MGTXTXN2_113), \" &\n\"(MGTXTXP2_114, MGTXTXN2_114), \" &\n\"(MGTXTXP2_115, MGTXTXN2_115), \" &\n\"(MGTXTXP2_116, MGTXTXN2_116), \" &\n\"(MGTXTXP2_117, MGTXTXN2_117), \" &\n\"(MGTXTXP2_118, MGTXTXN2_118), \" &\n\"(MGTXTXP2_119, MGTXTXN2_119), \" &\n\"(MGTXTXP3_113, MGTXTXN3_113), \" &\n\"(MGTXTXP3_114, MGTXTXN3_114), \" &\n\"(MGTXTXP3_115, MGTXTXN3_115), \" &\n\"(MGTXTXP3_116, MGTXTXN3_116), \" &\n\"(MGTXTXP3_117, MGTXTXN3_117), \" &\n\"(MGTXTXP3_118, MGTXTXN3_118), \" &\n\"(MGTXTXP3_119, MGTXTXN3_119))\";\n\n-- Scan Port Identification\n\nattribute TAP_SCAN_IN    of TDI : signal is true;\nattribute TAP_SCAN_MODE  of TMS : signal is true;\nattribute TAP_SCAN_OUT   of TDO : signal is true;\nattribute TAP_SCAN_CLOCK of TCK : signal is (66.0e6, BOTH);\n\n-- Compliance-Enable Description\n\nattribute COMPLIANCE_PATTERNS of XC7VX485T_FFG1761 : entity is\n        \"(PROGRAM_B) (1)\";\n\n-- Instruction Register Description\n\nattribute INSTRUCTION_LENGTH of XC7VX485T_FFG1761 : entity is 6;\n\nattribute INSTRUCTION_OPCODE of XC7VX485T_FFG1761 : entity is\n        \"IDCODE\t\t(001001),\" & -- DEVICE_ID\n        \"BYPASS\t\t(111111),\" & -- BYPASS\n        \"EXTEST\t\t(100110),\" & -- BOUNDARY\n        \"SAMPLE\t\t(000001),\" & -- BOUNDARY\n        \"PRELOAD\t(000001),\" & -- Same as SAMPLE\n        \"USERCODE\t(001000),\" & -- DEVICE_ID\n        \"HIGHZ\t\t(001010),\" & -- BYPASS\n        \"EXTEST_PULSE\t(111100),\" & -- BOUNDARY\n        \"EXTEST_TRAIN\t(111101),\" & -- BOUNDARY\n\t\"ISC_ENABLE\t(010000),\" & -- ISC_CONFIG\n\t\"ISC_PROGRAM\t(010001),\" & -- ISC_PDATA\n\t\"ISC_NOOP\t(010100),\" & -- ISC_DEFAULT\n\t\"XSC_READ_RSVD\t(010101),\" & -- PRIVATE\n\t\"ISC_DISABLE\t(010110),\" & -- ISC_CONFIG\n\t\"XSC_PROGRAM_KEY\t(010010),\" & -- XSC_KEY_DATA\n        \"XSC_DNA\t(010111),\" & -- DNA\n        \"CFG_OUT\t(000100),\" & -- Not available during configuration with another mode.\n        \"CFG_IN\t\t(000101),\" & -- Not available during configuration with another mode.\n        \"JPROGRAM\t(001011),\" & -- Not available during configuration with another mode.\n        \"JSTART\t\t(001100),\" & -- Not available during configuration with another mode.\n        \"JSHUTDOWN\t(001101),\" & -- Not available during configuration with another mode.\n        \"FUSE_CTS\t(110000),\" & -- PRIVATE\n        \"FUSE_KEY\t(110001),\" & -- PRIVATE\n        \"FUSE_DNA\t(110010),\" & -- PRIVATE\n        \"FUSE_USER\t(110011),\" & -- PRIVATE\n        \"FUSE_CNTL\t(110100),\" & -- PRIVATE\n        \"USER1\t\t(000010),\" & -- Not available until after configuration\n        \"USER2\t\t(000011),\" & -- Not available until after configuration\n        \"USER3\t\t(100010),\" & -- Not available until after configuration\n        \"USER4\t\t(100011),\" & -- Not available until after configuration\n        \"XADC_DRP\t(110111),\" & -- PRIVATE\n        \"INTEST_RSVD\t(000111)\"; -- PRIVATE\n\nattribute INSTRUCTION_CAPTURE of XC7VX485T_FFG1761 : entity is\n-- Bit 5 is 1 when DONE is released (part of startup sequence)\n-- Bit 4 is 1 if house-cleaning is complete\n-- Bit 3 is ISC_Enabled\n-- Bit 2 is ISC_Done\n        \"XXXX01\";\n\nattribute INSTRUCTION_PRIVATE of XC7VX485T_FFG1761 : entity is\n-- If the device is configured, and a USER instruction is implemented\n-- and not private to the FPGA designer, then it should be removed\n-- from INSTRUCTION_PRIVATE, and the target register should be defined\n-- in REGISTER_ACCESS.\n\t\"ISC_ENABLE,\" &\n\t\"ISC_PROGRAM,\" &\n\t\"ISC_NOOP,\" &\n\t\"XSC_READ_RSVD,\" &\n\t\"ISC_DISABLE,\" &\n\t\"XSC_PROGRAM_KEY,\" &\n\t\"XSC_DNA,\" &\n        \"CFG_OUT,\" &\n        \"CFG_IN,\" &\n        \"JPROGRAM,\" &\n        \"JSTART,\" &\n        \"JSHUTDOWN,\" &\n        \"FUSE_CTS,\" &\n        \"FUSE_KEY,\" &\n        \"FUSE_DNA,\" &\n        \"FUSE_USER,\" &\n        \"FUSE_CNTL,\" &\n        \"USER1,\" &\n        \"USER2,\" &\n        \"USER3,\" &\n        \"USER4,\" &\n        \"XADC_DRP,\" &\n        \"INTEST_RSVD\";\n\n-- Optional Register Description\n\nattribute IDCODE_REGISTER of XC7VX485T_FFG1761 : entity is\n\t\"XXXX\" &\t-- version\n\t\"0011011\" &\t-- family\n\t\"010000111\" &\t-- array size\n\t\"00001001001\" &\t-- manufacturer\n\t\"1\";\t\t-- required by 1149.1\n\n\nattribute USERCODE_REGISTER of XC7VX485T_FFG1761 : entity is\n        \"XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX\";\n\n-- Register Access Description\n\nattribute REGISTER_ACCESS of XC7VX485T_FFG1761 : entity is\n--\t\"<reg_name>[<length>] (USER1),\" &\n--\t\"<reg_name>[<length>] (USER2),\" &\n--\t\"<reg_name>[<length>] (USER3),\" &\n--\t\"<reg_name>[<length>] (USER4),\" &\n        \"DATAREG[57] (XSC_DNA),\" &\n        \"BYPASS (HIGHZ,BYPASS),\" &\n\t\"DEVICE_ID (USERCODE,IDCODE),\" &\n\t\"BOUNDARY (SAMPLE,PRELOAD,EXTEST,EXTEST_PULSE,EXTEST_TRAIN)\";\n\n-- Boundary-Scan Register Description\n\nattribute BOUNDARY_LENGTH of XC7VX485T_FFG1761 : entity is 2401;\n\nattribute BOUNDARY_REGISTER of XC7VX485T_FFG1761 : entity is\n-- cellnum (type, port, function, safe[, ccell, disval, disrslt])\n\t\"   0 (BC_2, *, controlr, 1),\" &\n\t\"   1 (BC_2, CCLK_N10, output3, X, 0, 1, Z),\" & --  CCLK_0\n\t\"   2 (BC_2, CCLK_N10, input, X),\" & --  CCLK_0\n\t\"   3 (BC_2, M0_AL10, input, X),\" &\n\t\"   4 (BC_2, M1_AK10, input, X),\" &\n\t\"   5 (BC_2, M2_AJ10, input, X),\" &\n\t\"   6 (BC_2, CFGBVS_AH10, input, X),\" &\n\t\"   7 (BC_2, *, internal, 1),\" & --  PROGRAM_B\n\t\"   8 (BC_2, *, controlr, 1),\" &\n\t\"   9 (BC_2, INIT_B_AG11, output3, X, 8, 1, Z),\" & --  INIT_B_0\n\t\"  10 (BC_2, INIT_B_AG11, input, X),\" & --  INIT_B_0\n\t\"  11 (BC_2, *, controlr, 1),\" &\n\t\"  12 (BC_2, DONE_AL11, output3, X, 11, 1, Z),\" & --  DONE_0\n\t\"  13 (BC_2, DONE_AL11, input, X),\" & --  DONE_0\n\t\"  14 (BC_2, *, internal, X),\" &\n\t\"  15 (BC_2, *, internal, X),\" &\n\t\"  16 (BC_2, *, internal, X),\" &\n\t\"  17 (BC_2, *, internal, X),\" &\n\t\"  18 (BC_2, *, internal, X),\" &\n\t\"  19 (BC_2, *, internal, X),\" &\n\t\"  20 (BC_2, *, internal, X),\" &\n\t\"  21 (BC_2, *, internal, X),\" &\n\t\"  22 (BC_2, *, internal, X),\" &\n\t\"  23 (BC_2, *, internal, X),\" &\n\t\"  24 (BC_2, *, internal, X),\" &\n\t\"  25 (BC_2, *, internal, X),\" &\n\t\"  26 (BC_2, *, internal, X),\" &\n\t\"  27 (BC_2, *, internal, X),\" &\n\t\"  28 (BC_2, *, internal, X),\" &\n\t\"  29 (BC_2, *, internal, X),\" &\n\t\"  30 (BC_2, *, internal, X),\" &\n\t\"  31 (BC_2, *, internal, X),\" &\n\t\"  32 (BC_2, *, internal, X),\" &\n\t\"  33 (BC_2, *, internal, X),\" &\n\t\"  34 (BC_2, *, internal, X),\" &\n\t\"  35 (BC_2, *, internal, X),\" &\n\t\"  36 (BC_2, *, internal, X),\" &\n\t\"  37 (BC_2, *, internal, X),\" &\n\t\"  38 (BC_2, *, internal, X),\" &\n\t\"  39 (BC_2, *, internal, X),\" &\n\t\"  40 (BC_2, *, internal, X),\" &\n\t\"  41 (BC_2, *, internal, X),\" &\n\t\"  42 (BC_2, *, internal, X),\" &\n\t\"  43 (BC_2, *, controlr, 1),\" &\n\t\"  44 (BC_2, IO_AN20, output3, X, 43, 1, Z),\" & --  PAD700\n\t\"  45 (BC_2, IO_AN20, input, X),\" & --  PAD700\n\t\"  46 (BC_2, *, controlr, 1),\" &\n\t\"  47 (BC_2, IO_BB23, output3, X, 46, 1, Z),\" & --  PAD699\n\t\"  48 (BC_2, IO_BB23, input, X),\" & --  PAD699\n\t\"  49 (BC_2, *, controlr, 1),\" &\n\t\"  50 (BC_2, IO_BB24, output3, X, 49, 1, Z),\" & --  PAD698\n\t\"  51 (BC_2, IO_BB24, input, X),\" & --  PAD698\n\t\"  52 (BC_2, *, controlr, 1),\" &\n\t\"  53 (BC_2, IO_BB21, output3, X, 52, 1, Z),\" & --  PAD697\n\t\"  54 (BC_2, IO_BB21, input, X),\" & --  PAD697\n\t\"  55 (BC_2, *, controlr, 1),\" &\n\t\"  56 (BC_2, IO_BA21, output3, X, 55, 1, Z),\" & --  PAD696\n\t\"  57 (BC_2, IO_BA21, input, X),\" & --  PAD696\n\t\"  58 (BC_2, *, controlr, 1),\" &\n\t\"  59 (BC_2, IO_BA24, output3, X, 58, 1, Z),\" & --  PAD695\n\t\"  60 (BC_2, IO_BA24, input, X),\" & --  PAD695\n\t\"  61 (BC_2, *, controlr, 1),\" &\n\t\"  62 (BC_2, IO_AY24, output3, X, 61, 1, Z),\" & --  PAD694\n\t\"  63 (BC_2, IO_AY24, input, X),\" & --  PAD694\n\t\"  64 (BC_2, *, controlr, 1),\" &\n\t\"  65 (BC_2, IO_BB22, output3, X, 64, 1, Z),\" & --  PAD693\n\t\"  66 (BC_2, IO_BB22, input, X),\" & --  PAD693\n\t\"  67 (BC_2, *, controlr, 1),\" &\n\t\"  68 (BC_2, IO_BA22, output3, X, 67, 1, Z),\" & --  PAD692\n\t\"  69 (BC_2, IO_BA22, input, X),\" & --  PAD692\n\t\"  70 (BC_2, *, controlr, 1),\" &\n\t\"  71 (BC_2, IO_BA25, output3, X, 70, 1, Z),\" & --  PAD691\n\t\"  72 (BC_2, IO_BA25, input, X),\" & --  PAD691\n\t\"  73 (BC_2, *, controlr, 1),\" &\n\t\"  74 (BC_2, IO_AY25, output3, X, 73, 1, Z),\" & --  PAD690\n\t\"  75 (BC_2, IO_AY25, input, X),\" & --  PAD690\n\t\"  76 (BC_2, *, controlr, 1),\" &\n\t\"  77 (BC_2, IO_AY22, output3, X, 76, 1, Z),\" & --  PAD689\n\t\"  78 (BC_2, IO_AY22, input, X),\" & --  PAD689\n\t\"  79 (BC_2, *, controlr, 1),\" &\n\t\"  80 (BC_2, IO_AY23, output3, X, 79, 1, Z),\" & --  PAD688\n\t\"  81 (BC_2, IO_AY23, input, X),\" & --  PAD688\n\t\"  82 (BC_2, *, controlr, 1),\" &\n\t\"  83 (BC_2, IO_AV24, output3, X, 82, 1, Z),\" & --  PAD687\n\t\"  84 (BC_2, IO_AV24, input, X),\" & --  PAD687\n\t\"  85 (BC_2, *, controlr, 1),\" &\n\t\"  86 (BC_2, IO_AU24, output3, X, 85, 1, Z),\" & --  PAD686\n\t\"  87 (BC_2, IO_AU24, input, X),\" & --  PAD686\n\t\"  88 (BC_2, *, controlr, 1),\" &\n\t\"  89 (BC_2, IO_AW21, output3, X, 88, 1, Z),\" & --  PAD685\n\t\"  90 (BC_2, IO_AW21, input, X),\" & --  PAD685\n\t\"  91 (BC_2, *, controlr, 1),\" &\n\t\"  92 (BC_2, IO_AV21, output3, X, 91, 1, Z),\" & --  PAD684\n\t\"  93 (BC_2, IO_AV21, input, X),\" & --  PAD684\n\t\"  94 (BC_2, *, controlr, 1),\" &\n\t\"  95 (BC_2, IO_AT24, output3, X, 94, 1, Z),\" & --  PAD683\n\t\"  96 (BC_2, IO_AT24, input, X),\" & --  PAD683\n\t\"  97 (BC_2, *, controlr, 1),\" &\n\t\"  98 (BC_2, IO_AR24, output3, X, 97, 1, Z),\" & --  PAD682\n\t\"  99 (BC_2, IO_AR24, input, X),\" & --  PAD682\n\t\" 100 (BC_2, *, controlr, 1),\" &\n\t\" 101 (BC_2, IO_AU21, output3, X, 100, 1, Z),\" & --  PAD681\n\t\" 102 (BC_2, IO_AU21, input, X),\" & --  PAD681\n\t\" 103 (BC_2, *, controlr, 1),\" &\n\t\" 104 (BC_2, IO_AT21, output3, X, 103, 1, Z),\" & --  PAD680\n\t\" 105 (BC_2, IO_AT21, input, X),\" & --  PAD680\n\t\" 106 (BC_2, *, controlr, 1),\" &\n\t\" 107 (BC_2, IO_AW22, output3, X, 106, 1, Z),\" & --  PAD679\n\t\" 108 (BC_2, IO_AW22, input, X),\" & --  PAD679\n\t\" 109 (BC_2, *, controlr, 1),\" &\n\t\" 110 (BC_2, IO_AW23, output3, X, 109, 1, Z),\" & --  PAD678\n\t\" 111 (BC_2, IO_AW23, input, X),\" & --  PAD678\n\t\" 112 (BC_2, *, controlr, 1),\" &\n\t\" 113 (BC_2, IO_AV23, output3, X, 112, 1, Z),\" & --  PAD677\n\t\" 114 (BC_2, IO_AV23, input, X),\" & --  PAD677\n\t\" 115 (BC_2, *, controlr, 1),\" &\n\t\" 116 (BC_2, IO_AU23, output3, X, 115, 1, Z),\" & --  PAD676\n\t\" 117 (BC_2, IO_AU23, input, X),\" & --  PAD676\n\t\" 118 (BC_2, *, controlr, 1),\" &\n\t\" 119 (BC_2, IO_AU22, output3, X, 118, 1, Z),\" & --  PAD675\n\t\" 120 (BC_2, IO_AU22, input, X),\" & --  PAD675\n\t\" 121 (BC_2, *, controlr, 1),\" &\n\t\" 122 (BC_2, IO_AT22, output3, X, 121, 1, Z),\" & --  PAD674\n\t\" 123 (BC_2, IO_AT22, input, X),\" & --  PAD674\n\t\" 124 (BC_2, *, controlr, 1),\" &\n\t\" 125 (BC_2, IO_AR22, output3, X, 124, 1, Z),\" & --  PAD673\n\t\" 126 (BC_2, IO_AR22, input, X),\" & --  PAD673\n\t\" 127 (BC_2, *, controlr, 1),\" &\n\t\" 128 (BC_2, IO_AR23, output3, X, 127, 1, Z),\" & --  PAD672\n\t\" 129 (BC_2, IO_AR23, input, X),\" & --  PAD672\n\t\" 130 (BC_2, *, controlr, 1),\" &\n\t\" 131 (BC_2, IO_AP21, output3, X, 130, 1, Z),\" & --  PAD671\n\t\" 132 (BC_2, IO_AP21, input, X),\" & --  PAD671\n\t\" 133 (BC_2, *, controlr, 1),\" &\n\t\" 134 (BC_2, IO_AN21, output3, X, 133, 1, Z),\" & --  PAD670\n\t\" 135 (BC_2, IO_AN21, input, X),\" & --  PAD670\n\t\" 136 (BC_2, *, controlr, 1),\" &\n\t\" 137 (BC_2, IO_AP22, output3, X, 136, 1, Z),\" & --  PAD669\n\t\" 138 (BC_2, IO_AP22, input, X),\" & --  PAD669\n\t\" 139 (BC_2, *, controlr, 1),\" &\n\t\" 140 (BC_2, IO_AP23, output3, X, 139, 1, Z),\" & --  PAD668\n\t\" 141 (BC_2, IO_AP23, input, X),\" & --  PAD668\n\t\" 142 (BC_2, *, controlr, 1),\" &\n\t\" 143 (BC_2, IO_AN23, output3, X, 142, 1, Z),\" & --  PAD667\n\t\" 144 (BC_2, IO_AN23, input, X),\" & --  PAD667\n\t\" 145 (BC_2, *, controlr, 1),\" &\n\t\" 146 (BC_2, IO_AM23, output3, X, 145, 1, Z),\" & --  PAD666\n\t\" 147 (BC_2, IO_AM23, input, X),\" & --  PAD666\n\t\" 148 (BC_2, *, controlr, 1),\" &\n\t\" 149 (BC_2, IO_AN24, output3, X, 148, 1, Z),\" & --  PAD665\n\t\" 150 (BC_2, IO_AN24, input, X),\" & --  PAD665\n\t\" 151 (BC_2, *, controlr, 1),\" &\n\t\" 152 (BC_2, IO_AM24, output3, X, 151, 1, Z),\" & --  PAD664\n\t\" 153 (BC_2, IO_AM24, input, X),\" & --  PAD664\n\t\" 154 (BC_2, *, controlr, 1),\" &\n\t\" 155 (BC_2, IO_AM22, output3, X, 154, 1, Z),\" & --  PAD663\n\t\" 156 (BC_2, IO_AM22, input, X),\" & --  PAD663\n\t\" 157 (BC_2, *, controlr, 1),\" &\n\t\" 158 (BC_2, IO_AL22, output3, X, 157, 1, Z),\" & --  PAD662\n\t\" 159 (BC_2, IO_AL22, input, X),\" & --  PAD662\n\t\" 160 (BC_2, *, controlr, 1),\" &\n\t\" 161 (BC_2, IO_AJ20, output3, X, 160, 1, Z),\" & --  PAD661\n\t\" 162 (BC_2, IO_AJ20, input, X),\" & --  PAD661\n\t\" 163 (BC_2, *, controlr, 1),\" &\n\t\" 164 (BC_2, IO_AJ21, output3, X, 163, 1, Z),\" & --  PAD660\n\t\" 165 (BC_2, IO_AJ21, input, X),\" & --  PAD660\n\t\" 166 (BC_2, *, controlr, 1),\" &\n\t\" 167 (BC_2, IO_AM21, output3, X, 166, 1, Z),\" & --  PAD659\n\t\" 168 (BC_2, IO_AM21, input, X),\" & --  PAD659\n\t\" 169 (BC_2, *, controlr, 1),\" &\n\t\" 170 (BC_2, IO_AL21, output3, X, 169, 1, Z),\" & --  PAD658\n\t\" 171 (BC_2, IO_AL21, input, X),\" & --  PAD658\n\t\" 172 (BC_2, *, controlr, 1),\" &\n\t\" 173 (BC_2, IO_AK22, output3, X, 172, 1, Z),\" & --  PAD657\n\t\" 174 (BC_2, IO_AK22, input, X),\" & --  PAD657\n\t\" 175 (BC_2, *, controlr, 1),\" &\n\t\" 176 (BC_2, IO_AJ22, output3, X, 175, 1, Z),\" & --  PAD656\n\t\" 177 (BC_2, IO_AJ22, input, X),\" & --  PAD656\n\t\" 178 (BC_2, *, controlr, 1),\" &\n\t\" 179 (BC_2, IO_AL20, output3, X, 178, 1, Z),\" & --  PAD655\n\t\" 180 (BC_2, IO_AL20, input, X),\" & --  PAD655\n\t\" 181 (BC_2, *, controlr, 1),\" &\n\t\" 182 (BC_2, IO_AK20, output3, X, 181, 1, Z),\" & --  PAD654\n\t\" 183 (BC_2, IO_AK20, input, X),\" & --  PAD654\n\t\" 184 (BC_2, *, controlr, 1),\" &\n\t\" 185 (BC_2, IO_AK23, output3, X, 184, 1, Z),\" & --  PAD653\n\t\" 186 (BC_2, IO_AK23, input, X),\" & --  PAD653\n\t\" 187 (BC_2, *, controlr, 1),\" &\n\t\" 188 (BC_2, IO_AJ23, output3, X, 187, 1, Z),\" & --  PAD652\n\t\" 189 (BC_2, IO_AJ23, input, X),\" & --  PAD652\n\t\" 190 (BC_2, *, controlr, 1),\" &\n\t\" 191 (BC_2, IO_AL24, output3, X, 190, 1, Z),\" & --  PAD651\n\t\" 192 (BC_2, IO_AL24, input, X),\" & --  PAD651\n\t\" 193 (BC_2, *, controlr, 1),\" &\n\t\" 194 (BC_2, IO_U28, output3, X, 193, 1, Z),\" & --  PAD650\n\t\" 195 (BC_2, IO_U28, input, X),\" & --  PAD650\n\t\" 196 (BC_2, *, controlr, 1),\" &\n\t\" 197 (BC_2, IO_Y30, output3, X, 196, 1, Z),\" & --  PAD649\n\t\" 198 (BC_2, IO_Y30, input, X),\" & --  PAD649\n\t\" 199 (BC_2, *, controlr, 1),\" &\n\t\" 200 (BC_2, IO_Y29, output3, X, 199, 1, Z),\" & --  PAD648\n\t\" 201 (BC_2, IO_Y29, input, X),\" & --  PAD648\n\t\" 202 (BC_2, *, controlr, 1),\" &\n\t\" 203 (BC_2, IO_U29, output3, X, 202, 1, Z),\" & --  PAD647\n\t\" 204 (BC_2, IO_U29, input, X),\" & --  PAD647\n\t\" 205 (BC_2, *, controlr, 1),\" &\n\t\" 206 (BC_2, IO_V29, output3, X, 205, 1, Z),\" & --  PAD646\n\t\" 207 (BC_2, IO_V29, input, X),\" & --  PAD646\n\t\" 208 (BC_2, *, controlr, 1),\" &\n\t\" 209 (BC_2, IO_W31, output3, X, 208, 1, Z),\" & --  PAD645\n\t\" 210 (BC_2, IO_W31, input, X),\" & --  PAD645\n\t\" 211 (BC_2, *, controlr, 1),\" &\n\t\" 212 (BC_2, IO_W30, output3, X, 211, 1, Z),\" & --  PAD644\n\t\" 213 (BC_2, IO_W30, input, X),\" & --  PAD644\n\t\" 214 (BC_2, *, controlr, 1),\" &\n\t\" 215 (BC_2, IO_T30, output3, X, 214, 1, Z),\" & --  PAD643\n\t\" 216 (BC_2, IO_T30, input, X),\" & --  PAD643\n\t\" 217 (BC_2, *, controlr, 1),\" &\n\t\" 218 (BC_2, IO_T29, output3, X, 217, 1, Z),\" & --  PAD642\n\t\" 219 (BC_2, IO_T29, input, X),\" & --  PAD642\n\t\" 220 (BC_2, *, controlr, 1),\" &\n\t\" 221 (BC_2, IO_V31, output3, X, 220, 1, Z),\" & --  PAD641\n\t\" 222 (BC_2, IO_V31, input, X),\" & --  PAD641\n\t\" 223 (BC_2, *, controlr, 1),\" &\n\t\" 224 (BC_2, IO_V30, output3, X, 223, 1, Z),\" & --  PAD640\n\t\" 225 (BC_2, IO_V30, input, X),\" & --  PAD640\n\t\" 226 (BC_2, *, controlr, 1),\" &\n\t\" 227 (BC_2, IO_T31, output3, X, 226, 1, Z),\" & --  PAD639\n\t\" 228 (BC_2, IO_T31, input, X),\" & --  PAD639\n\t\" 229 (BC_2, *, controlr, 1),\" &\n\t\" 230 (BC_2, IO_U31, output3, X, 229, 1, Z),\" & --  PAD638\n\t\" 231 (BC_2, IO_U31, input, X),\" & --  PAD638\n\t\" 232 (BC_2, *, controlr, 1),\" &\n\t\" 233 (BC_2, IO_P31, output3, X, 232, 1, Z),\" & --  PAD637\n\t\" 234 (BC_2, IO_P31, input, X),\" & --  PAD637\n\t\" 235 (BC_2, *, controlr, 1),\" &\n\t\" 236 (BC_2, IO_R30, output3, X, 235, 1, Z),\" & --  PAD636\n\t\" 237 (BC_2, IO_R30, input, X),\" & --  PAD636\n\t\" 238 (BC_2, *, controlr, 1),\" &\n\t\" 239 (BC_2, IO_N29, output3, X, 238, 1, Z),\" & --  PAD635\n\t\" 240 (BC_2, IO_N29, input, X),\" & --  PAD635\n\t\" 241 (BC_2, *, controlr, 1),\" &\n\t\" 242 (BC_2, IO_N28, output3, X, 241, 1, Z),\" & --  PAD634\n\t\" 243 (BC_2, IO_N28, input, X),\" & --  PAD634\n\t\" 244 (BC_2, *, controlr, 1),\" &\n\t\" 245 (BC_2, IO_P28, output3, X, 244, 1, Z),\" & --  PAD633\n\t\" 246 (BC_2, IO_P28, input, X),\" & --  PAD633\n\t\" 247 (BC_2, *, controlr, 1),\" &\n\t\" 248 (BC_2, IO_R28, output3, X, 247, 1, Z),\" & --  PAD632\n\t\" 249 (BC_2, IO_R28, input, X),\" & --  PAD632\n\t\" 250 (BC_2, *, controlr, 1),\" &\n\t\" 251 (BC_2, IO_M29, output3, X, 250, 1, Z),\" & --  PAD631\n\t\" 252 (BC_2, IO_M29, input, X),\" & --  PAD631\n\t\" 253 (BC_2, *, controlr, 1),\" &\n\t\" 254 (BC_2, IO_M28, output3, X, 253, 1, Z),\" & --  PAD630\n\t\" 255 (BC_2, IO_M28, input, X),\" & --  PAD630\n\t\" 256 (BC_2, *, controlr, 1),\" &\n\t\" 257 (BC_2, IO_N31, output3, X, 256, 1, Z),\" & --  PAD629\n\t\" 258 (BC_2, IO_N31, input, X),\" & --  PAD629\n\t\" 259 (BC_2, *, controlr, 1),\" &\n\t\" 260 (BC_2, IO_P30, output3, X, 259, 1, Z),\" & --  PAD628\n\t\" 261 (BC_2, IO_P30, input, X),\" & --  PAD628\n\t\" 262 (BC_2, *, controlr, 1),\" &\n\t\" 263 (BC_2, IO_M31, output3, X, 262, 1, Z),\" & --  PAD627\n\t\" 264 (BC_2, IO_M31, input, X),\" & --  PAD627\n\t\" 265 (BC_2, *, controlr, 1),\" &\n\t\" 266 (BC_2, IO_N30, output3, X, 265, 1, Z),\" & --  PAD626\n\t\" 267 (BC_2, IO_N30, input, X),\" & --  PAD626\n\t\" 268 (BC_2, *, controlr, 1),\" &\n\t\" 269 (BC_2, IO_K32, output3, X, 268, 1, Z),\" & --  PAD625\n\t\" 270 (BC_2, IO_K32, input, X),\" & --  PAD625\n\t\" 271 (BC_2, *, controlr, 1),\" &\n\t\" 272 (BC_2, IO_L31, output3, X, 271, 1, Z),\" & --  PAD624\n\t\" 273 (BC_2, IO_L31, input, X),\" & --  PAD624\n\t\" 274 (BC_2, *, controlr, 1),\" &\n\t\" 275 (BC_2, IO_L32, output3, X, 274, 1, Z),\" & --  PAD623\n\t\" 276 (BC_2, IO_L32, input, X),\" & --  PAD623\n\t\" 277 (BC_2, *, controlr, 1),\" &\n\t\" 278 (BC_2, IO_M32, output3, X, 277, 1, Z),\" & --  PAD622\n\t\" 279 (BC_2, IO_M32, input, X),\" & --  PAD622\n\t\" 280 (BC_2, *, controlr, 1),\" &\n\t\" 281 (BC_2, IO_H31, output3, X, 280, 1, Z),\" & --  PAD621\n\t\" 282 (BC_2, IO_H31, input, X),\" & --  PAD621\n\t\" 283 (BC_2, *, controlr, 1),\" &\n\t\" 284 (BC_2, IO_J31, output3, X, 283, 1, Z),\" & --  PAD620\n\t\" 285 (BC_2, IO_J31, input, X),\" & --  PAD620\n\t\" 286 (BC_2, *, controlr, 1),\" &\n\t\" 287 (BC_2, IO_L30, output3, X, 286, 1, Z),\" & --  PAD619\n\t\" 288 (BC_2, IO_L30, input, X),\" & --  PAD619\n\t\" 289 (BC_2, *, controlr, 1),\" &\n\t\" 290 (BC_2, IO_L29, output3, X, 289, 1, Z),\" & --  PAD618\n\t\" 291 (BC_2, IO_L29, input, X),\" & --  PAD618\n\t\" 292 (BC_2, *, controlr, 1),\" &\n\t\" 293 (BC_2, IO_H30, output3, X, 292, 1, Z),\" & --  PAD617\n\t\" 294 (BC_2, IO_H30, input, X),\" & --  PAD617\n\t\" 295 (BC_2, *, controlr, 1),\" &\n\t\" 296 (BC_2, IO_J30, output3, X, 295, 1, Z),\" & --  PAD616\n\t\" 297 (BC_2, IO_J30, input, X),\" & --  PAD616\n\t\" 298 (BC_2, *, controlr, 1),\" &\n\t\" 299 (BC_2, IO_K30, output3, X, 298, 1, Z),\" & --  PAD615\n\t\" 300 (BC_2, IO_K30, input, X),\" & --  PAD615\n\t\" 301 (BC_2, *, controlr, 1),\" &\n\t\" 302 (BC_2, IO_K29, output3, X, 301, 1, Z),\" & --  PAD614\n\t\" 303 (BC_2, IO_K29, input, X),\" & --  PAD614\n\t\" 304 (BC_2, *, controlr, 1),\" &\n\t\" 305 (BC_2, IO_H35, output3, X, 304, 1, Z),\" & --  PAD613\n\t\" 306 (BC_2, IO_H35, input, X),\" & --  PAD613\n\t\" 307 (BC_2, *, controlr, 1),\" &\n\t\" 308 (BC_2, IO_H34, output3, X, 307, 1, Z),\" & --  PAD612\n\t\" 309 (BC_2, IO_H34, input, X),\" & --  PAD612\n\t\" 310 (BC_2, *, controlr, 1),\" &\n\t\" 311 (BC_2, IO_M34, output3, X, 310, 1, Z),\" & --  PAD611\n\t\" 312 (BC_2, IO_M34, input, X),\" & --  PAD611\n\t\" 313 (BC_2, *, controlr, 1),\" &\n\t\" 314 (BC_2, IO_M33, output3, X, 313, 1, Z),\" & --  PAD610\n\t\" 315 (BC_2, IO_M33, input, X),\" & --  PAD610\n\t\" 316 (BC_2, *, controlr, 1),\" &\n\t\" 317 (BC_2, IO_L35, output3, X, 316, 1, Z),\" & --  PAD609\n\t\" 318 (BC_2, IO_L35, input, X),\" & --  PAD609\n\t\" 319 (BC_2, *, controlr, 1),\" &\n\t\" 320 (BC_2, IO_L34, output3, X, 319, 1, Z),\" & --  PAD608\n\t\" 321 (BC_2, IO_L34, input, X),\" & --  PAD608\n\t\" 322 (BC_2, *, controlr, 1),\" &\n\t\" 323 (BC_2, IO_K34, output3, X, 322, 1, Z),\" & --  PAD607\n\t\" 324 (BC_2, IO_K34, input, X),\" & --  PAD607\n\t\" 325 (BC_2, *, controlr, 1),\" &\n\t\" 326 (BC_2, IO_K33, output3, X, 325, 1, Z),\" & --  PAD606\n\t\" 327 (BC_2, IO_K33, input, X),\" & --  PAD606\n\t\" 328 (BC_2, *, controlr, 1),\" &\n\t\" 329 (BC_2, IO_J33, output3, X, 328, 1, Z),\" & --  PAD605\n\t\" 330 (BC_2, IO_J33, input, X),\" & --  PAD605\n\t\" 331 (BC_2, *, controlr, 1),\" &\n\t\" 332 (BC_2, IO_J32, output3, X, 331, 1, Z),\" & --  PAD604\n\t\" 333 (BC_2, IO_J32, input, X),\" & --  PAD604\n\t\" 334 (BC_2, *, controlr, 1),\" &\n\t\" 335 (BC_2, IO_J35, output3, X, 334, 1, Z),\" & --  PAD603\n\t\" 336 (BC_2, IO_J35, input, X),\" & --  PAD603\n\t\" 337 (BC_2, *, controlr, 1),\" &\n\t\" 338 (BC_2, IO_K35, output3, X, 337, 1, Z),\" & --  PAD602\n\t\" 339 (BC_2, IO_K35, input, X),\" & --  PAD602\n\t\" 340 (BC_2, *, controlr, 1),\" &\n\t\" 341 (BC_2, IO_R29, output3, X, 340, 1, Z),\" & --  PAD601\n\t\" 342 (BC_2, IO_R29, input, X),\" & --  PAD601\n\t\" 343 (BC_2, *, controlr, 1),\" &\n\t\" 344 (BC_2, IO_G34, output3, X, 343, 1, Z),\" & --  PAD600\n\t\" 345 (BC_2, IO_G34, input, X),\" & --  PAD600\n\t\" 346 (BC_2, *, controlr, 1),\" &\n\t\" 347 (BC_2, IO_H36, output3, X, 346, 1, Z),\" & --  PAD599\n\t\" 348 (BC_2, IO_H36, input, X),\" & --  PAD599\n\t\" 349 (BC_2, *, controlr, 1),\" &\n\t\" 350 (BC_2, IO_J36, output3, X, 349, 1, Z),\" & --  PAD598\n\t\" 351 (BC_2, IO_J36, input, X),\" & --  PAD598\n\t\" 352 (BC_2, *, controlr, 1),\" &\n\t\" 353 (BC_2, IO_G38, output3, X, 352, 1, Z),\" & --  PAD597\n\t\" 354 (BC_2, IO_G38, input, X),\" & --  PAD597\n\t\" 355 (BC_2, *, controlr, 1),\" &\n\t\" 356 (BC_2, IO_H38, output3, X, 355, 1, Z),\" & --  PAD596\n\t\" 357 (BC_2, IO_H38, input, X),\" & --  PAD596\n\t\" 358 (BC_2, *, controlr, 1),\" &\n\t\" 359 (BC_2, IO_J38, output3, X, 358, 1, Z),\" & --  PAD595\n\t\" 360 (BC_2, IO_J38, input, X),\" & --  PAD595\n\t\" 361 (BC_2, *, controlr, 1),\" &\n\t\" 362 (BC_2, IO_J37, output3, X, 361, 1, Z),\" & --  PAD594\n\t\" 363 (BC_2, IO_J37, input, X),\" & --  PAD594\n\t\" 364 (BC_2, *, controlr, 1),\" &\n\t\" 365 (BC_2, IO_E39, output3, X, 364, 1, Z),\" & --  PAD593\n\t\" 366 (BC_2, IO_E39, input, X),\" & --  PAD593\n\t\" 367 (BC_2, *, controlr, 1),\" &\n\t\" 368 (BC_2, IO_F39, output3, X, 367, 1, Z),\" & --  PAD592\n\t\" 369 (BC_2, IO_F39, input, X),\" & --  PAD592\n\t\" 370 (BC_2, *, controlr, 1),\" &\n\t\" 371 (BC_2, IO_G37, output3, X, 370, 1, Z),\" & --  PAD591\n\t\" 372 (BC_2, IO_G37, input, X),\" & --  PAD591\n\t\" 373 (BC_2, *, controlr, 1),\" &\n\t\" 374 (BC_2, IO_G36, output3, X, 373, 1, Z),\" & --  PAD590\n\t\" 375 (BC_2, IO_G36, input, X),\" & --  PAD590\n\t\" 376 (BC_2, *, controlr, 1),\" &\n\t\" 377 (BC_2, IO_E38, output3, X, 376, 1, Z),\" & --  PAD589\n\t\" 378 (BC_2, IO_E38, input, X),\" & --  PAD589\n\t\" 379 (BC_2, *, controlr, 1),\" &\n\t\" 380 (BC_2, IO_E37, output3, X, 379, 1, Z),\" & --  PAD588\n\t\" 381 (BC_2, IO_E37, input, X),\" & --  PAD588\n\t\" 382 (BC_2, *, controlr, 1),\" &\n\t\" 383 (BC_2, IO_G33, output3, X, 382, 1, Z),\" & --  PAD587\n\t\" 384 (BC_2, IO_G33, input, X),\" & --  PAD587\n\t\" 385 (BC_2, *, controlr, 1),\" &\n\t\" 386 (BC_2, IO_H33, output3, X, 385, 1, Z),\" & --  PAD586\n\t\" 387 (BC_2, IO_H33, input, X),\" & --  PAD586\n\t\" 388 (BC_2, *, controlr, 1),\" &\n\t\" 389 (BC_2, IO_F35, output3, X, 388, 1, Z),\" & --  PAD585\n\t\" 390 (BC_2, IO_F35, input, X),\" & --  PAD585\n\t\" 391 (BC_2, *, controlr, 1),\" &\n\t\" 392 (BC_2, IO_F34, output3, X, 391, 1, Z),\" & --  PAD584\n\t\" 393 (BC_2, IO_F34, input, X),\" & --  PAD584\n\t\" 394 (BC_2, *, controlr, 1),\" &\n\t\" 395 (BC_2, IO_F37, output3, X, 394, 1, Z),\" & --  PAD583\n\t\" 396 (BC_2, IO_F37, input, X),\" & --  PAD583\n\t\" 397 (BC_2, *, controlr, 1),\" &\n\t\" 398 (BC_2, IO_F36, output3, X, 397, 1, Z),\" & --  PAD582\n\t\" 399 (BC_2, IO_F36, input, X),\" & --  PAD582\n\t\" 400 (BC_2, *, controlr, 1),\" &\n\t\" 401 (BC_2, IO_F32, output3, X, 400, 1, Z),\" & --  PAD581\n\t\" 402 (BC_2, IO_F32, input, X),\" & --  PAD581\n\t\" 403 (BC_2, *, controlr, 1),\" &\n\t\" 404 (BC_2, IO_G32, output3, X, 403, 1, Z),\" & --  PAD580\n\t\" 405 (BC_2, IO_G32, input, X),\" & --  PAD580\n\t\" 406 (BC_2, *, controlr, 1),\" &\n\t\" 407 (BC_2, IO_D38, output3, X, 406, 1, Z),\" & --  PAD579\n\t\" 408 (BC_2, IO_D38, input, X),\" & --  PAD579\n\t\" 409 (BC_2, *, controlr, 1),\" &\n\t\" 410 (BC_2, IO_D37, output3, X, 409, 1, Z),\" & --  PAD578\n\t\" 411 (BC_2, IO_D37, input, X),\" & --  PAD578\n\t\" 412 (BC_2, *, controlr, 1),\" &\n\t\" 413 (BC_2, IO_E35, output3, X, 412, 1, Z),\" & --  PAD577\n\t\" 414 (BC_2, IO_E35, input, X),\" & --  PAD577\n\t\" 415 (BC_2, *, controlr, 1),\" &\n\t\" 416 (BC_2, IO_E34, output3, X, 415, 1, Z),\" & --  PAD576\n\t\" 417 (BC_2, IO_E34, input, X),\" & --  PAD576\n\t\" 418 (BC_2, *, controlr, 1),\" &\n\t\" 419 (BC_2, IO_C36, output3, X, 418, 1, Z),\" & --  PAD575\n\t\" 420 (BC_2, IO_C36, input, X),\" & --  PAD575\n\t\" 421 (BC_2, *, controlr, 1),\" &\n\t\" 422 (BC_2, IO_C35, output3, X, 421, 1, Z),\" & --  PAD574\n\t\" 423 (BC_2, IO_C35, input, X),\" & --  PAD574\n\t\" 424 (BC_2, *, controlr, 1),\" &\n\t\" 425 (BC_2, IO_D36, output3, X, 424, 1, Z),\" & --  PAD573\n\t\" 426 (BC_2, IO_D36, input, X),\" & --  PAD573\n\t\" 427 (BC_2, *, controlr, 1),\" &\n\t\" 428 (BC_2, IO_D35, output3, X, 427, 1, Z),\" & --  PAD572\n\t\" 429 (BC_2, IO_D35, input, X),\" & --  PAD572\n\t\" 430 (BC_2, *, controlr, 1),\" &\n\t\" 431 (BC_2, IO_C34, output3, X, 430, 1, Z),\" & --  PAD571\n\t\" 432 (BC_2, IO_C34, input, X),\" & --  PAD571\n\t\" 433 (BC_2, *, controlr, 1),\" &\n\t\" 434 (BC_2, IO_C33, output3, X, 433, 1, Z),\" & --  PAD570\n\t\" 435 (BC_2, IO_C33, input, X),\" & --  PAD570\n\t\" 436 (BC_2, *, controlr, 1),\" &\n\t\" 437 (BC_2, IO_D33, output3, X, 436, 1, Z),\" & --  PAD569\n\t\" 438 (BC_2, IO_D33, input, X),\" & --  PAD569\n\t\" 439 (BC_2, *, controlr, 1),\" &\n\t\" 440 (BC_2, IO_E33, output3, X, 439, 1, Z),\" & --  PAD568\n\t\" 441 (BC_2, IO_E33, input, X),\" & --  PAD568\n\t\" 442 (BC_2, *, controlr, 1),\" &\n\t\" 443 (BC_2, IO_B33, output3, X, 442, 1, Z),\" & --  PAD567\n\t\" 444 (BC_2, IO_B33, input, X),\" & --  PAD567\n\t\" 445 (BC_2, *, controlr, 1),\" &\n\t\" 446 (BC_2, IO_B32, output3, X, 445, 1, Z),\" & --  PAD566\n\t\" 447 (BC_2, IO_B32, input, X),\" & --  PAD566\n\t\" 448 (BC_2, *, controlr, 1),\" &\n\t\" 449 (BC_2, IO_D32, output3, X, 448, 1, Z),\" & --  PAD565\n\t\" 450 (BC_2, IO_D32, input, X),\" & --  PAD565\n\t\" 451 (BC_2, *, controlr, 1),\" &\n\t\" 452 (BC_2, IO_E32, output3, X, 451, 1, Z),\" & --  PAD564\n\t\" 453 (BC_2, IO_E32, input, X),\" & --  PAD564\n\t\" 454 (BC_2, *, controlr, 1),\" &\n\t\" 455 (BC_2, IO_B38, output3, X, 454, 1, Z),\" & --  PAD563\n\t\" 456 (BC_2, IO_B38, input, X),\" & --  PAD563\n\t\" 457 (BC_2, *, controlr, 1),\" &\n\t\" 458 (BC_2, IO_B37, output3, X, 457, 1, Z),\" & --  PAD562\n\t\" 459 (BC_2, IO_B37, input, X),\" & --  PAD562\n\t\" 460 (BC_2, *, controlr, 1),\" &\n\t\" 461 (BC_2, IO_C39, output3, X, 460, 1, Z),\" & --  PAD561\n\t\" 462 (BC_2, IO_C39, input, X),\" & --  PAD561\n\t\" 463 (BC_2, *, controlr, 1),\" &\n\t\" 464 (BC_2, IO_C38, output3, X, 463, 1, Z),\" & --  PAD560\n\t\" 465 (BC_2, IO_C38, input, X),\" & --  PAD560\n\t\" 466 (BC_2, *, controlr, 1),\" &\n\t\" 467 (BC_2, IO_A36, output3, X, 466, 1, Z),\" & --  PAD559\n\t\" 468 (BC_2, IO_A36, input, X),\" & --  PAD559\n\t\" 469 (BC_2, *, controlr, 1),\" &\n\t\" 470 (BC_2, IO_A35, output3, X, 469, 1, Z),\" & --  PAD558\n\t\" 471 (BC_2, IO_A35, input, X),\" & --  PAD558\n\t\" 472 (BC_2, *, controlr, 1),\" &\n\t\" 473 (BC_2, IO_A39, output3, X, 472, 1, Z),\" & --  PAD557\n\t\" 474 (BC_2, IO_A39, input, X),\" & --  PAD557\n\t\" 475 (BC_2, *, controlr, 1),\" &\n\t\" 476 (BC_2, IO_B39, output3, X, 475, 1, Z),\" & --  PAD556\n\t\" 477 (BC_2, IO_B39, input, X),\" & --  PAD556\n\t\" 478 (BC_2, *, controlr, 1),\" &\n\t\" 479 (BC_2, IO_A34, output3, X, 478, 1, Z),\" & --  PAD555\n\t\" 480 (BC_2, IO_A34, input, X),\" & --  PAD555\n\t\" 481 (BC_2, *, controlr, 1),\" &\n\t\" 482 (BC_2, IO_B34, output3, X, 481, 1, Z),\" & --  PAD554\n\t\" 483 (BC_2, IO_B34, input, X),\" & --  PAD554\n\t\" 484 (BC_2, *, controlr, 1),\" &\n\t\" 485 (BC_2, IO_A37, output3, X, 484, 1, Z),\" & --  PAD553\n\t\" 486 (BC_2, IO_A37, input, X),\" & --  PAD553\n\t\" 487 (BC_2, *, controlr, 1),\" &\n\t\" 488 (BC_2, IO_B36, output3, X, 487, 1, Z),\" & --  PAD552\n\t\" 489 (BC_2, IO_B36, input, X),\" & --  PAD552\n\t\" 490 (BC_2, *, controlr, 1),\" &\n\t\" 491 (BC_2, IO_G31, output3, X, 490, 1, Z),\" & --  PAD551\n\t\" 492 (BC_2, IO_G31, input, X),\" & --  PAD551\n\t\" 493 (BC_2, *, controlr, 1),\" &\n\t\" 494 (BC_2, IO_M26, output3, X, 493, 1, Z),\" & --  PAD550\n\t\" 495 (BC_2, IO_M26, input, X),\" & --  PAD550\n\t\" 496 (BC_2, *, controlr, 1),\" &\n\t\" 497 (BC_2, IO_L27, output3, X, 496, 1, Z),\" & --  PAD549\n\t\" 498 (BC_2, IO_L27, input, X),\" & --  PAD549\n\t\" 499 (BC_2, *, controlr, 1),\" &\n\t\" 500 (BC_2, IO_M27, output3, X, 499, 1, Z),\" & --  PAD548\n\t\" 501 (BC_2, IO_M27, input, X),\" & --  PAD548\n\t\" 502 (BC_2, *, controlr, 1),\" &\n\t\" 503 (BC_2, IO_N24, output3, X, 502, 1, Z),\" & --  PAD547\n\t\" 504 (BC_2, IO_N24, input, X),\" & --  PAD547\n\t\" 505 (BC_2, *, controlr, 1),\" &\n\t\" 506 (BC_2, IO_N23, output3, X, 505, 1, Z),\" & --  PAD546\n\t\" 507 (BC_2, IO_N23, input, X),\" & --  PAD546\n\t\" 508 (BC_2, *, controlr, 1),\" &\n\t\" 509 (BC_2, IO_N26, output3, X, 508, 1, Z),\" & --  PAD545\n\t\" 510 (BC_2, IO_N26, input, X),\" & --  PAD545\n\t\" 511 (BC_2, *, controlr, 1),\" &\n\t\" 512 (BC_2, IO_N25, output3, X, 511, 1, Z),\" & --  PAD544\n\t\" 513 (BC_2, IO_N25, input, X),\" & --  PAD544\n\t\" 514 (BC_2, *, controlr, 1),\" &\n\t\" 515 (BC_2, IO_P23, output3, X, 514, 1, Z),\" & --  PAD543\n\t\" 516 (BC_2, IO_P23, input, X),\" & --  PAD543\n\t\" 517 (BC_2, *, controlr, 1),\" &\n\t\" 518 (BC_2, IO_P22, output3, X, 517, 1, Z),\" & --  PAD542\n\t\" 519 (BC_2, IO_P22, input, X),\" & --  PAD542\n\t\" 520 (BC_2, *, controlr, 1),\" &\n\t\" 521 (BC_2, IO_P26, output3, X, 520, 1, Z),\" & --  PAD541\n\t\" 522 (BC_2, IO_P26, input, X),\" & --  PAD541\n\t\" 523 (BC_2, *, controlr, 1),\" &\n\t\" 524 (BC_2, IO_P25, output3, X, 523, 1, Z),\" & --  PAD540\n\t\" 525 (BC_2, IO_P25, input, X),\" & --  PAD540\n\t\" 526 (BC_2, *, controlr, 1),\" &\n\t\" 527 (BC_2, IO_N21, output3, X, 526, 1, Z),\" & --  PAD539\n\t\" 528 (BC_2, IO_N21, input, X),\" & --  PAD539\n\t\" 529 (BC_2, *, controlr, 1),\" &\n\t\" 530 (BC_2, IO_P21, output3, X, 529, 1, Z),\" & --  PAD538\n\t\" 531 (BC_2, IO_P21, input, X),\" & --  PAD538\n\t\" 532 (BC_2, *, controlr, 1),\" &\n\t\" 533 (BC_2, IO_L21, output3, X, 532, 1, Z),\" & --  PAD537\n\t\" 534 (BC_2, IO_L21, input, X),\" & --  PAD537\n\t\" 535 (BC_2, *, controlr, 1),\" &\n\t\" 536 (BC_2, IO_M21, output3, X, 535, 1, Z),\" & --  PAD536\n\t\" 537 (BC_2, IO_M21, input, X),\" & --  PAD536\n\t\" 538 (BC_2, *, controlr, 1),\" &\n\t\" 539 (BC_2, IO_J22, output3, X, 538, 1, Z),\" & --  PAD535\n\t\" 540 (BC_2, IO_J22, input, X),\" & --  PAD535\n\t\" 541 (BC_2, *, controlr, 1),\" &\n\t\" 542 (BC_2, IO_K22, output3, X, 541, 1, Z),\" & --  PAD534\n\t\" 543 (BC_2, IO_K22, input, X),\" & --  PAD534\n\t\" 544 (BC_2, *, controlr, 1),\" &\n\t\" 545 (BC_2, IO_L26, output3, X, 544, 1, Z),\" & --  PAD533\n\t\" 546 (BC_2, IO_L26, input, X),\" & --  PAD533\n\t\" 547 (BC_2, *, controlr, 1),\" &\n\t\" 548 (BC_2, IO_L25, output3, X, 547, 1, Z),\" & --  PAD532\n\t\" 549 (BC_2, IO_L25, input, X),\" & --  PAD532\n\t\" 550 (BC_2, *, controlr, 1),\" &\n\t\" 551 (BC_2, IO_L22, output3, X, 550, 1, Z),\" & --  PAD531\n\t\" 552 (BC_2, IO_L22, input, X),\" & --  PAD531\n\t\" 553 (BC_2, *, controlr, 1),\" &\n\t\" 554 (BC_2, IO_M22, output3, X, 553, 1, Z),\" & --  PAD530\n\t\" 555 (BC_2, IO_M22, input, X),\" & --  PAD530\n\t\" 556 (BC_2, *, controlr, 1),\" &\n\t\" 557 (BC_2, IO_J23, output3, X, 556, 1, Z),\" & --  PAD529\n\t\" 558 (BC_2, IO_J23, input, X),\" & --  PAD529\n\t\" 559 (BC_2, *, controlr, 1),\" &\n\t\" 560 (BC_2, IO_K23, output3, X, 559, 1, Z),\" & --  PAD528\n\t\" 561 (BC_2, IO_K23, input, X),\" & --  PAD528\n\t\" 562 (BC_2, *, controlr, 1),\" &\n\t\" 563 (BC_2, IO_L24, output3, X, 562, 1, Z),\" & --  PAD527\n\t\" 564 (BC_2, IO_L24, input, X),\" & --  PAD527\n\t\" 565 (BC_2, *, controlr, 1),\" &\n\t\" 566 (BC_2, IO_M24, output3, X, 565, 1, Z),\" & --  PAD526\n\t\" 567 (BC_2, IO_M24, input, X),\" & --  PAD526\n\t\" 568 (BC_2, *, controlr, 1),\" &\n\t\" 569 (BC_2, IO_J26, output3, X, 568, 1, Z),\" & --  PAD525\n\t\" 570 (BC_2, IO_J26, input, X),\" & --  PAD525\n\t\" 571 (BC_2, *, controlr, 1),\" &\n\t\" 572 (BC_2, IO_J25, output3, X, 571, 1, Z),\" & --  PAD524\n\t\" 573 (BC_2, IO_J25, input, X),\" & --  PAD524\n\t\" 574 (BC_2, *, controlr, 1),\" &\n\t\" 575 (BC_2, IO_K25, output3, X, 574, 1, Z),\" & --  PAD523\n\t\" 576 (BC_2, IO_K25, input, X),\" & --  PAD523\n\t\" 577 (BC_2, *, controlr, 1),\" &\n\t\" 578 (BC_2, IO_K24, output3, X, 577, 1, Z),\" & --  PAD522\n\t\" 579 (BC_2, IO_K24, input, X),\" & --  PAD522\n\t\" 580 (BC_2, *, controlr, 1),\" &\n\t\" 581 (BC_2, IO_J27, output3, X, 580, 1, Z),\" & --  PAD521\n\t\" 582 (BC_2, IO_J27, input, X),\" & --  PAD521\n\t\" 583 (BC_2, *, controlr, 1),\" &\n\t\" 584 (BC_2, IO_K27, output3, X, 583, 1, Z),\" & --  PAD520\n\t\" 585 (BC_2, IO_K27, input, X),\" & --  PAD520\n\t\" 586 (BC_2, *, controlr, 1),\" &\n\t\" 587 (BC_2, IO_H29, output3, X, 586, 1, Z),\" & --  PAD519\n\t\" 588 (BC_2, IO_H29, input, X),\" & --  PAD519\n\t\" 589 (BC_2, *, controlr, 1),\" &\n\t\" 590 (BC_2, IO_H28, output3, X, 589, 1, Z),\" & --  PAD518\n\t\" 591 (BC_2, IO_H28, input, X),\" & --  PAD518\n\t\" 592 (BC_2, *, controlr, 1),\" &\n\t\" 593 (BC_2, IO_J28, output3, X, 592, 1, Z),\" & --  PAD517\n\t\" 594 (BC_2, IO_J28, input, X),\" & --  PAD517\n\t\" 595 (BC_2, *, controlr, 1),\" &\n\t\" 596 (BC_2, IO_K28, output3, X, 595, 1, Z),\" & --  PAD516\n\t\" 597 (BC_2, IO_K28, input, X),\" & --  PAD516\n\t\" 598 (BC_2, *, controlr, 1),\" &\n\t\" 599 (BC_2, IO_G29, output3, X, 598, 1, Z),\" & --  PAD515\n\t\" 600 (BC_2, IO_G29, input, X),\" & --  PAD515\n\t\" 601 (BC_2, *, controlr, 1),\" &\n\t\" 602 (BC_2, IO_G28, output3, X, 601, 1, Z),\" & --  PAD514\n\t\" 603 (BC_2, IO_G28, input, X),\" & --  PAD514\n\t\" 604 (BC_2, *, controlr, 1),\" &\n\t\" 605 (BC_2, IO_G23, output3, X, 604, 1, Z),\" & --  PAD513\n\t\" 606 (BC_2, IO_G23, input, X),\" & --  PAD513\n\t\" 607 (BC_2, *, controlr, 1),\" &\n\t\" 608 (BC_2, IO_H23, output3, X, 607, 1, Z),\" & --  PAD512\n\t\" 609 (BC_2, IO_H23, input, X),\" & --  PAD512\n\t\" 610 (BC_2, *, controlr, 1),\" &\n\t\" 611 (BC_2, IO_G27, output3, X, 610, 1, Z),\" & --  PAD511\n\t\" 612 (BC_2, IO_G27, input, X),\" & --  PAD511\n\t\" 613 (BC_2, *, controlr, 1),\" &\n\t\" 614 (BC_2, IO_G26, output3, X, 613, 1, Z),\" & --  PAD510\n\t\" 615 (BC_2, IO_G26, input, X),\" & --  PAD510\n\t\" 616 (BC_2, *, controlr, 1),\" &\n\t\" 617 (BC_2, IO_G22, output3, X, 616, 1, Z),\" & --  PAD509\n\t\" 618 (BC_2, IO_G22, input, X),\" & --  PAD509\n\t\" 619 (BC_2, *, controlr, 1),\" &\n\t\" 620 (BC_2, IO_G21, output3, X, 619, 1, Z),\" & --  PAD508\n\t\" 621 (BC_2, IO_G21, input, X),\" & --  PAD508\n\t\" 622 (BC_2, *, controlr, 1),\" &\n\t\" 623 (BC_2, IO_H26, output3, X, 622, 1, Z),\" & --  PAD507\n\t\" 624 (BC_2, IO_H26, input, X),\" & --  PAD507\n\t\" 625 (BC_2, *, controlr, 1),\" &\n\t\" 626 (BC_2, IO_H25, output3, X, 625, 1, Z),\" & --  PAD506\n\t\" 627 (BC_2, IO_H25, input, X),\" & --  PAD506\n\t\" 628 (BC_2, *, controlr, 1),\" &\n\t\" 629 (BC_2, IO_H21, output3, X, 628, 1, Z),\" & --  PAD505\n\t\" 630 (BC_2, IO_H21, input, X),\" & --  PAD505\n\t\" 631 (BC_2, *, controlr, 1),\" &\n\t\" 632 (BC_2, IO_J21, output3, X, 631, 1, Z),\" & --  PAD504\n\t\" 633 (BC_2, IO_J21, input, X),\" & --  PAD504\n\t\" 634 (BC_2, *, controlr, 1),\" &\n\t\" 635 (BC_2, IO_G24, output3, X, 634, 1, Z),\" & --  PAD503\n\t\" 636 (BC_2, IO_G24, input, X),\" & --  PAD503\n\t\" 637 (BC_2, *, controlr, 1),\" &\n\t\" 638 (BC_2, IO_H24, output3, X, 637, 1, Z),\" & --  PAD502\n\t\" 639 (BC_2, IO_H24, input, X),\" & --  PAD502\n\t\" 640 (BC_2, *, controlr, 1),\" &\n\t\" 641 (BC_2, IO_M23, output3, X, 640, 1, Z),\" & --  PAD501\n\t\" 642 (BC_2, IO_M23, input, X),\" & --  PAD501\n\t\" 643 (BC_2, *, controlr, 1),\" &\n\t\" 644 (BC_2, IO_F24, output3, X, 643, 1, Z),\" & --  PAD500\n\t\" 645 (BC_2, IO_F24, input, X),\" & --  PAD500\n\t\" 646 (BC_2, *, controlr, 1),\" &\n\t\" 647 (BC_2, IO_F31, output3, X, 646, 1, Z),\" & --  PAD499\n\t\" 648 (BC_2, IO_F31, input, X),\" & --  PAD499\n\t\" 649 (BC_2, *, controlr, 1),\" &\n\t\" 650 (BC_2, IO_F30, output3, X, 649, 1, Z),\" & --  PAD498\n\t\" 651 (BC_2, IO_F30, input, X),\" & --  PAD498\n\t\" 652 (BC_2, *, controlr, 1),\" &\n\t\" 653 (BC_2, IO_F27, output3, X, 652, 1, Z),\" & --  PAD497\n\t\" 654 (BC_2, IO_F27, input, X),\" & --  PAD497\n\t\" 655 (BC_2, *, controlr, 1),\" &\n\t\" 656 (BC_2, IO_F26, output3, X, 655, 1, Z),\" & --  PAD496\n\t\" 657 (BC_2, IO_F26, input, X),\" & --  PAD496\n\t\" 658 (BC_2, *, controlr, 1),\" &\n\t\" 659 (BC_2, IO_E29, output3, X, 658, 1, Z),\" & --  PAD495\n\t\" 660 (BC_2, IO_E29, input, X),\" & --  PAD495\n\t\" 661 (BC_2, *, controlr, 1),\" &\n\t\" 662 (BC_2, IO_F29, output3, X, 661, 1, Z),\" & --  PAD494\n\t\" 663 (BC_2, IO_F29, input, X),\" & --  PAD494\n\t\" 664 (BC_2, *, controlr, 1),\" &\n\t\" 665 (BC_2, IO_E28, output3, X, 664, 1, Z),\" & --  PAD493\n\t\" 666 (BC_2, IO_E28, input, X),\" & --  PAD493\n\t\" 667 (BC_2, *, controlr, 1),\" &\n\t\" 668 (BC_2, IO_E27, output3, X, 667, 1, Z),\" & --  PAD492\n\t\" 669 (BC_2, IO_E27, input, X),\" & --  PAD492\n\t\" 670 (BC_2, *, controlr, 1),\" &\n\t\" 671 (BC_2, IO_C30, output3, X, 670, 1, Z),\" & --  PAD491\n\t\" 672 (BC_2, IO_C30, input, X),\" & --  PAD491\n\t\" 673 (BC_2, *, controlr, 1),\" &\n\t\" 674 (BC_2, IO_D30, output3, X, 673, 1, Z),\" & --  PAD490\n\t\" 675 (BC_2, IO_D30, input, X),\" & --  PAD490\n\t\" 676 (BC_2, *, controlr, 1),\" &\n\t\" 677 (BC_2, IO_D31, output3, X, 676, 1, Z),\" & --  PAD489\n\t\" 678 (BC_2, IO_D31, input, X),\" & --  PAD489\n\t\" 679 (BC_2, *, controlr, 1),\" &\n\t\" 680 (BC_2, IO_E30, output3, X, 679, 1, Z),\" & --  PAD488\n\t\" 681 (BC_2, IO_E30, input, X),\" & --  PAD488\n\t\" 682 (BC_2, *, controlr, 1),\" &\n\t\" 683 (BC_2, IO_B31, output3, X, 682, 1, Z),\" & --  PAD487\n\t\" 684 (BC_2, IO_B31, input, X),\" & --  PAD487\n\t\" 685 (BC_2, *, controlr, 1),\" &\n\t\" 686 (BC_2, IO_C31, output3, X, 685, 1, Z),\" & --  PAD486\n\t\" 687 (BC_2, IO_C31, input, X),\" & --  PAD486\n\t\" 688 (BC_2, *, controlr, 1),\" &\n\t\" 689 (BC_2, IO_A30, output3, X, 688, 1, Z),\" & --  PAD485\n\t\" 690 (BC_2, IO_A30, input, X),\" & --  PAD485\n\t\" 691 (BC_2, *, controlr, 1),\" &\n\t\" 692 (BC_2, IO_A29, output3, X, 691, 1, Z),\" & --  PAD484\n\t\" 693 (BC_2, IO_A29, input, X),\" & --  PAD484\n\t\" 694 (BC_2, *, controlr, 1),\" &\n\t\" 695 (BC_2, IO_A32, output3, X, 694, 1, Z),\" & --  PAD483\n\t\" 696 (BC_2, IO_A32, input, X),\" & --  PAD483\n\t\" 697 (BC_2, *, controlr, 1),\" &\n\t\" 698 (BC_2, IO_A31, output3, X, 697, 1, Z),\" & --  PAD482\n\t\" 699 (BC_2, IO_A31, input, X),\" & --  PAD482\n\t\" 700 (BC_2, *, controlr, 1),\" &\n\t\" 701 (BC_2, IO_B29, output3, X, 700, 1, Z),\" & --  PAD481\n\t\" 702 (BC_2, IO_B29, input, X),\" & --  PAD481\n\t\" 703 (BC_2, *, controlr, 1),\" &\n\t\" 704 (BC_2, IO_B28, output3, X, 703, 1, Z),\" & --  PAD480\n\t\" 705 (BC_2, IO_B28, input, X),\" & --  PAD480\n\t\" 706 (BC_2, *, controlr, 1),\" &\n\t\" 707 (BC_2, IO_C29, output3, X, 706, 1, Z),\" & --  PAD479\n\t\" 708 (BC_2, IO_C29, input, X),\" & --  PAD479\n\t\" 709 (BC_2, *, controlr, 1),\" &\n\t\" 710 (BC_2, IO_C28, output3, X, 709, 1, Z),\" & --  PAD478\n\t\" 711 (BC_2, IO_C28, input, X),\" & --  PAD478\n\t\" 712 (BC_2, *, controlr, 1),\" &\n\t\" 713 (BC_2, IO_D28, output3, X, 712, 1, Z),\" & --  PAD477\n\t\" 714 (BC_2, IO_D28, input, X),\" & --  PAD477\n\t\" 715 (BC_2, *, controlr, 1),\" &\n\t\" 716 (BC_2, IO_D27, output3, X, 715, 1, Z),\" & --  PAD476\n\t\" 717 (BC_2, IO_D27, input, X),\" & --  PAD476\n\t\" 718 (BC_2, *, controlr, 1),\" &\n\t\" 719 (BC_2, IO_C26, output3, X, 718, 1, Z),\" & --  PAD475\n\t\" 720 (BC_2, IO_C26, input, X),\" & --  PAD475\n\t\" 721 (BC_2, *, controlr, 1),\" &\n\t\" 722 (BC_2, IO_C25, output3, X, 721, 1, Z),\" & --  PAD474\n\t\" 723 (BC_2, IO_C25, input, X),\" & --  PAD474\n\t\" 724 (BC_2, *, controlr, 1),\" &\n\t\" 725 (BC_2, IO_D26, output3, X, 724, 1, Z),\" & --  PAD473\n\t\" 726 (BC_2, IO_D26, input, X),\" & --  PAD473\n\t\" 727 (BC_2, *, controlr, 1),\" &\n\t\" 728 (BC_2, IO_D25, output3, X, 727, 1, Z),\" & --  PAD472\n\t\" 729 (BC_2, IO_D25, input, X),\" & --  PAD472\n\t\" 730 (BC_2, *, controlr, 1),\" &\n\t\" 731 (BC_2, IO_D23, output3, X, 730, 1, Z),\" & --  PAD471\n\t\" 732 (BC_2, IO_D23, input, X),\" & --  PAD471\n\t\" 733 (BC_2, *, controlr, 1),\" &\n\t\" 734 (BC_2, IO_D22, output3, X, 733, 1, Z),\" & --  PAD470\n\t\" 735 (BC_2, IO_D22, input, X),\" & --  PAD470\n\t\" 736 (BC_2, *, controlr, 1),\" &\n\t\" 737 (BC_2, IO_E25, output3, X, 736, 1, Z),\" & --  PAD469\n\t\" 738 (BC_2, IO_E25, input, X),\" & --  PAD469\n\t\" 739 (BC_2, *, controlr, 1),\" &\n\t\" 740 (BC_2, IO_F25, output3, X, 739, 1, Z),\" & --  PAD468\n\t\" 741 (BC_2, IO_F25, input, X),\" & --  PAD468\n\t\" 742 (BC_2, *, controlr, 1),\" &\n\t\" 743 (BC_2, IO_E22, output3, X, 742, 1, Z),\" & --  PAD467\n\t\" 744 (BC_2, IO_E22, input, X),\" & --  PAD467\n\t\" 745 (BC_2, *, controlr, 1),\" &\n\t\" 746 (BC_2, IO_F22, output3, X, 745, 1, Z),\" & --  PAD466\n\t\" 747 (BC_2, IO_F22, input, X),\" & --  PAD466\n\t\" 748 (BC_2, *, controlr, 1),\" &\n\t\" 749 (BC_2, IO_E24, output3, X, 748, 1, Z),\" & --  PAD465\n\t\" 750 (BC_2, IO_E24, input, X),\" & --  PAD465\n\t\" 751 (BC_2, *, controlr, 1),\" &\n\t\" 752 (BC_2, IO_E23, output3, X, 751, 1, Z),\" & --  PAD464\n\t\" 753 (BC_2, IO_E23, input, X),\" & --  PAD464\n\t\" 754 (BC_2, *, controlr, 1),\" &\n\t\" 755 (BC_2, IO_B24, output3, X, 754, 1, Z),\" & --  PAD463\n\t\" 756 (BC_2, IO_B24, input, X),\" & --  PAD463\n\t\" 757 (BC_2, *, controlr, 1),\" &\n\t\" 758 (BC_2, IO_C24, output3, X, 757, 1, Z),\" & --  PAD462\n\t\" 759 (BC_2, IO_C24, input, X),\" & --  PAD462\n\t\" 760 (BC_2, *, controlr, 1),\" &\n\t\" 761 (BC_2, IO_B27, output3, X, 760, 1, Z),\" & --  PAD461\n\t\" 762 (BC_2, IO_B27, input, X),\" & --  PAD461\n\t\" 763 (BC_2, *, controlr, 1),\" &\n\t\" 764 (BC_2, IO_B26, output3, X, 763, 1, Z),\" & --  PAD460\n\t\" 765 (BC_2, IO_B26, input, X),\" & --  PAD460\n\t\" 766 (BC_2, *, controlr, 1),\" &\n\t\" 767 (BC_2, IO_B23, output3, X, 766, 1, Z),\" & --  PAD459\n\t\" 768 (BC_2, IO_B23, input, X),\" & --  PAD459\n\t\" 769 (BC_2, *, controlr, 1),\" &\n\t\" 770 (BC_2, IO_C23, output3, X, 769, 1, Z),\" & --  PAD458\n\t\" 771 (BC_2, IO_C23, input, X),\" & --  PAD458\n\t\" 772 (BC_2, *, controlr, 1),\" &\n\t\" 773 (BC_2, IO_A27, output3, X, 772, 1, Z),\" & --  PAD457\n\t\" 774 (BC_2, IO_A27, input, X),\" & --  PAD457\n\t\" 775 (BC_2, *, controlr, 1),\" &\n\t\" 776 (BC_2, IO_A26, output3, X, 775, 1, Z),\" & --  PAD456\n\t\" 777 (BC_2, IO_A26, input, X),\" & --  PAD456\n\t\" 778 (BC_2, *, controlr, 1),\" &\n\t\" 779 (BC_2, IO_A22, output3, X, 778, 1, Z),\" & --  PAD455\n\t\" 780 (BC_2, IO_A22, input, X),\" & --  PAD455\n\t\" 781 (BC_2, *, controlr, 1),\" &\n\t\" 782 (BC_2, IO_B22, output3, X, 781, 1, Z),\" & --  PAD454\n\t\" 783 (BC_2, IO_B22, input, X),\" & --  PAD454\n\t\" 784 (BC_2, *, controlr, 1),\" &\n\t\" 785 (BC_2, IO_A25, output3, X, 784, 1, Z),\" & --  PAD453\n\t\" 786 (BC_2, IO_A25, input, X),\" & --  PAD453\n\t\" 787 (BC_2, *, controlr, 1),\" &\n\t\" 788 (BC_2, IO_A24, output3, X, 787, 1, Z),\" & --  PAD452\n\t\" 789 (BC_2, IO_A24, input, X),\" & --  PAD452\n\t\" 790 (BC_2, *, controlr, 1),\" &\n\t\" 791 (BC_2, IO_F21, output3, X, 790, 1, Z),\" & --  PAD451\n\t\" 792 (BC_2, IO_F21, input, X),\" & --  PAD451\n\t\" 793 (BC_2, *, controlr, 1),\" &\n\t\" 794 (BC_2, IO_K20, output3, X, 793, 1, Z),\" & --  PAD450\n\t\" 795 (BC_2, IO_K20, input, X),\" & --  PAD450\n\t\" 796 (BC_2, *, controlr, 1),\" &\n\t\" 797 (BC_2, IO_L19, output3, X, 796, 1, Z),\" & --  PAD449\n\t\" 798 (BC_2, IO_L19, input, X),\" & --  PAD449\n\t\" 799 (BC_2, *, controlr, 1),\" &\n\t\" 800 (BC_2, IO_L20, output3, X, 799, 1, Z),\" & --  PAD448\n\t\" 801 (BC_2, IO_L20, input, X),\" & --  PAD448\n\t\" 802 (BC_2, *, controlr, 1),\" &\n\t\" 803 (BC_2, IO_N20, output3, X, 802, 1, Z),\" & --  PAD447\n\t\" 804 (BC_2, IO_N20, input, X),\" & --  PAD447\n\t\" 805 (BC_2, *, controlr, 1),\" &\n\t\" 806 (BC_2, IO_P20, output3, X, 805, 1, Z),\" & --  PAD446\n\t\" 807 (BC_2, IO_P20, input, X),\" & --  PAD446\n\t\" 808 (BC_2, *, controlr, 1),\" &\n\t\" 809 (BC_2, IO_M18, output3, X, 808, 1, Z),\" & --  PAD445\n\t\" 810 (BC_2, IO_M18, input, X),\" & --  PAD445\n\t\" 811 (BC_2, *, controlr, 1),\" &\n\t\" 812 (BC_2, IO_M19, output3, X, 811, 1, Z),\" & --  PAD444\n\t\" 813 (BC_2, IO_M19, input, X),\" & --  PAD444\n\t\" 814 (BC_2, *, controlr, 1),\" &\n\t\" 815 (BC_2, IO_N18, output3, X, 814, 1, Z),\" & --  PAD443\n\t\" 816 (BC_2, IO_N18, input, X),\" & --  PAD443\n\t\" 817 (BC_2, *, controlr, 1),\" &\n\t\" 818 (BC_2, IO_N19, output3, X, 817, 1, Z),\" & --  PAD442\n\t\" 819 (BC_2, IO_N19, input, X),\" & --  PAD442\n\t\" 820 (BC_2, *, controlr, 1),\" &\n\t\" 821 (BC_2, IO_L17, output3, X, 820, 1, Z),\" & --  PAD441\n\t\" 822 (BC_2, IO_L17, input, X),\" & --  PAD441\n\t\" 823 (BC_2, *, controlr, 1),\" &\n\t\" 824 (BC_2, IO_M17, output3, X, 823, 1, Z),\" & --  PAD440\n\t\" 825 (BC_2, IO_M17, input, X),\" & --  PAD440\n\t\" 826 (BC_2, *, controlr, 1),\" &\n\t\" 827 (BC_2, IO_P17, output3, X, 826, 1, Z),\" & --  PAD439\n\t\" 828 (BC_2, IO_P17, input, X),\" & --  PAD439\n\t\" 829 (BC_2, *, controlr, 1),\" &\n\t\" 830 (BC_2, IO_P18, output3, X, 829, 1, Z),\" & --  PAD438\n\t\" 831 (BC_2, IO_P18, input, X),\" & --  PAD438\n\t\" 832 (BC_2, *, controlr, 1),\" &\n\t\" 833 (BC_2, IO_G17, output3, X, 832, 1, Z),\" & --  PAD437\n\t\" 834 (BC_2, IO_G17, input, X),\" & --  PAD437\n\t\" 835 (BC_2, *, controlr, 1),\" &\n\t\" 836 (BC_2, IO_H18, output3, X, 835, 1, Z),\" & --  PAD436\n\t\" 837 (BC_2, IO_H18, input, X),\" & --  PAD436\n\t\" 838 (BC_2, *, controlr, 1),\" &\n\t\" 839 (BC_2, IO_H20, output3, X, 838, 1, Z),\" & --  PAD435\n\t\" 840 (BC_2, IO_H20, input, X),\" & --  PAD435\n\t\" 841 (BC_2, *, controlr, 1),\" &\n\t\" 842 (BC_2, IO_J20, output3, X, 841, 1, Z),\" & --  PAD434\n\t\" 843 (BC_2, IO_J20, input, X),\" & --  PAD434\n\t\" 844 (BC_2, *, controlr, 1),\" &\n\t\" 845 (BC_2, IO_J17, output3, X, 844, 1, Z),\" & --  PAD433\n\t\" 846 (BC_2, IO_J17, input, X),\" & --  PAD433\n\t\" 847 (BC_2, *, controlr, 1),\" &\n\t\" 848 (BC_2, IO_K17, output3, X, 847, 1, Z),\" & --  PAD432\n\t\" 849 (BC_2, IO_K17, input, X),\" & --  PAD432\n\t\" 850 (BC_2, *, controlr, 1),\" &\n\t\" 851 (BC_2, IO_E20, output3, X, 850, 1, Z),\" & --  PAD431\n\t\" 852 (BC_2, IO_E20, input, X),\" & --  PAD431\n\t\" 853 (BC_2, *, controlr, 1),\" &\n\t\" 854 (BC_2, IO_F20, output3, X, 853, 1, Z),\" & --  PAD430\n\t\" 855 (BC_2, IO_F20, input, X),\" & --  PAD430\n\t\" 856 (BC_2, *, controlr, 1),\" &\n\t\" 857 (BC_2, IO_J18, output3, X, 856, 1, Z),\" & --  PAD429\n\t\" 858 (BC_2, IO_J18, input, X),\" & --  PAD429\n\t\" 859 (BC_2, *, controlr, 1),\" &\n\t\" 860 (BC_2, IO_K19, output3, X, 859, 1, Z),\" & --  PAD428\n\t\" 861 (BC_2, IO_K19, input, X),\" & --  PAD428\n\t\" 862 (BC_2, *, controlr, 1),\" &\n\t\" 863 (BC_2, IO_G18, output3, X, 862, 1, Z),\" & --  PAD427\n\t\" 864 (BC_2, IO_G18, input, X),\" & --  PAD427\n\t\" 865 (BC_2, *, controlr, 1),\" &\n\t\" 866 (BC_2, IO_H19, output3, X, 865, 1, Z),\" & --  PAD426\n\t\" 867 (BC_2, IO_H19, input, X),\" & --  PAD426\n\t\" 868 (BC_2, *, controlr, 1),\" &\n\t\" 869 (BC_2, IO_E18, output3, X, 868, 1, Z),\" & --  PAD425\n\t\" 870 (BC_2, IO_E18, input, X),\" & --  PAD425\n\t\" 871 (BC_2, *, controlr, 1),\" &\n\t\" 872 (BC_2, IO_E19, output3, X, 871, 1, Z),\" & --  PAD424\n\t\" 873 (BC_2, IO_E19, input, X),\" & --  PAD424\n\t\" 874 (BC_2, *, controlr, 1),\" &\n\t\" 875 (BC_2, IO_F19, output3, X, 874, 1, Z),\" & --  PAD423\n\t\" 876 (BC_2, IO_F19, input, X),\" & --  PAD423\n\t\" 877 (BC_2, *, controlr, 1),\" &\n\t\" 878 (BC_2, IO_G19, output3, X, 877, 1, Z),\" & --  PAD422\n\t\" 879 (BC_2, IO_G19, input, X),\" & --  PAD422\n\t\" 880 (BC_2, *, controlr, 1),\" &\n\t\" 881 (BC_2, IO_D17, output3, X, 880, 1, Z),\" & --  PAD421\n\t\" 882 (BC_2, IO_D17, input, X),\" & --  PAD421\n\t\" 883 (BC_2, *, controlr, 1),\" &\n\t\" 884 (BC_2, IO_D18, output3, X, 883, 1, Z),\" & --  PAD420\n\t\" 885 (BC_2, IO_D18, input, X),\" & --  PAD420\n\t\" 886 (BC_2, *, controlr, 1),\" &\n\t\" 887 (BC_2, IO_C21, output3, X, 886, 1, Z),\" & --  PAD419\n\t\" 888 (BC_2, IO_C21, input, X),\" & --  PAD419\n\t\" 889 (BC_2, *, controlr, 1),\" &\n\t\" 890 (BC_2, IO_D21, output3, X, 889, 1, Z),\" & --  PAD418\n\t\" 891 (BC_2, IO_D21, input, X),\" & --  PAD418\n\t\" 892 (BC_2, *, controlr, 1),\" &\n\t\" 893 (BC_2, IO_E17, output3, X, 892, 1, Z),\" & --  PAD417\n\t\" 894 (BC_2, IO_E17, input, X),\" & --  PAD417\n\t\" 895 (BC_2, *, controlr, 1),\" &\n\t\" 896 (BC_2, IO_F17, output3, X, 895, 1, Z),\" & --  PAD416\n\t\" 897 (BC_2, IO_F17, input, X),\" & --  PAD416\n\t\" 898 (BC_2, *, controlr, 1),\" &\n\t\" 899 (BC_2, IO_C20, output3, X, 898, 1, Z),\" & --  PAD415\n\t\" 900 (BC_2, IO_C20, input, X),\" & --  PAD415\n\t\" 901 (BC_2, *, controlr, 1),\" &\n\t\" 902 (BC_2, IO_D20, output3, X, 901, 1, Z),\" & --  PAD414\n\t\" 903 (BC_2, IO_D20, input, X),\" & --  PAD414\n\t\" 904 (BC_2, *, controlr, 1),\" &\n\t\" 905 (BC_2, IO_B18, output3, X, 904, 1, Z),\" & --  PAD413\n\t\" 906 (BC_2, IO_B18, input, X),\" & --  PAD413\n\t\" 907 (BC_2, *, controlr, 1),\" &\n\t\" 908 (BC_2, IO_C18, output3, X, 907, 1, Z),\" & --  PAD412\n\t\" 909 (BC_2, IO_C18, input, X),\" & --  PAD412\n\t\" 910 (BC_2, *, controlr, 1),\" &\n\t\" 911 (BC_2, IO_A21, output3, X, 910, 1, Z),\" & --  PAD411\n\t\" 912 (BC_2, IO_A21, input, X),\" & --  PAD411\n\t\" 913 (BC_2, *, controlr, 1),\" &\n\t\" 914 (BC_2, IO_B21, output3, X, 913, 1, Z),\" & --  PAD410\n\t\" 915 (BC_2, IO_B21, input, X),\" & --  PAD410\n\t\" 916 (BC_2, *, controlr, 1),\" &\n\t\" 917 (BC_2, IO_A17, output3, X, 916, 1, Z),\" & --  PAD409\n\t\" 918 (BC_2, IO_A17, input, X),\" & --  PAD409\n\t\" 919 (BC_2, *, controlr, 1),\" &\n\t\" 920 (BC_2, IO_B17, output3, X, 919, 1, Z),\" & --  PAD408\n\t\" 921 (BC_2, IO_B17, input, X),\" & --  PAD408\n\t\" 922 (BC_2, *, controlr, 1),\" &\n\t\" 923 (BC_2, IO_A19, output3, X, 922, 1, Z),\" & --  PAD407\n\t\" 924 (BC_2, IO_A19, input, X),\" & --  PAD407\n\t\" 925 (BC_2, *, controlr, 1),\" &\n\t\" 926 (BC_2, IO_A20, output3, X, 925, 1, Z),\" & --  PAD406\n\t\" 927 (BC_2, IO_A20, input, X),\" & --  PAD406\n\t\" 928 (BC_2, *, controlr, 1),\" &\n\t\" 929 (BC_2, IO_A15, output3, X, 928, 1, Z),\" & --  PAD405\n\t\" 930 (BC_2, IO_A15, input, X),\" & --  PAD405\n\t\" 931 (BC_2, *, controlr, 1),\" &\n\t\" 932 (BC_2, IO_A16, output3, X, 931, 1, Z),\" & --  PAD404\n\t\" 933 (BC_2, IO_A16, input, X),\" & --  PAD404\n\t\" 934 (BC_2, *, controlr, 1),\" &\n\t\" 935 (BC_2, IO_B19, output3, X, 934, 1, Z),\" & --  PAD403\n\t\" 936 (BC_2, IO_B19, input, X),\" & --  PAD403\n\t\" 937 (BC_2, *, controlr, 1),\" &\n\t\" 938 (BC_2, IO_C19, output3, X, 937, 1, Z),\" & --  PAD402\n\t\" 939 (BC_2, IO_C19, input, X),\" & --  PAD402\n\t\" 940 (BC_2, *, controlr, 1),\" &\n\t\" 941 (BC_2, IO_K18, output3, X, 940, 1, Z),\" & --  PAD401\n\t\" 942 (BC_2, IO_K18, input, X),\" & --  PAD401\n\t\" 943 (BC_2, *, controlr, 1),\" &\n\t\" 944 (BC_2, IO_J11, output3, X, 943, 1, Z),\" & --  PAD400\n\t\" 945 (BC_2, IO_J11, input, X),\" & --  PAD400\n\t\" 946 (BC_2, *, controlr, 1),\" &\n\t\" 947 (BC_2, IO_M11, output3, X, 946, 1, Z),\" & --  PAD399\n\t\" 948 (BC_2, IO_M11, input, X),\" & --  PAD399\n\t\" 949 (BC_2, *, controlr, 1),\" &\n\t\" 950 (BC_2, IO_M12, output3, X, 949, 1, Z),\" & --  PAD398\n\t\" 951 (BC_2, IO_M12, input, X),\" & --  PAD398\n\t\" 952 (BC_2, *, controlr, 1),\" &\n\t\" 953 (BC_2, IO_N14, output3, X, 952, 1, Z),\" & --  PAD397\n\t\" 954 (BC_2, IO_N14, input, X),\" & --  PAD397\n\t\" 955 (BC_2, *, controlr, 1),\" &\n\t\" 956 (BC_2, IO_N15, output3, X, 955, 1, Z),\" & --  PAD396\n\t\" 957 (BC_2, IO_N15, input, X),\" & --  PAD396\n\t\" 958 (BC_2, *, controlr, 1),\" &\n\t\" 959 (BC_2, IO_M13, output3, X, 958, 1, Z),\" & --  PAD395\n\t\" 960 (BC_2, IO_M13, input, X),\" & --  PAD395\n\t\" 961 (BC_2, *, controlr, 1),\" &\n\t\" 962 (BC_2, IO_N13, output3, X, 961, 1, Z),\" & --  PAD394\n\t\" 963 (BC_2, IO_N13, input, X),\" & --  PAD394\n\t\" 964 (BC_2, *, controlr, 1),\" &\n\t\" 965 (BC_2, IO_M16, output3, X, 964, 1, Z),\" & --  PAD393\n\t\" 966 (BC_2, IO_M16, input, X),\" & --  PAD393\n\t\" 967 (BC_2, *, controlr, 1),\" &\n\t\" 968 (BC_2, IO_N16, output3, X, 967, 1, Z),\" & --  PAD392\n\t\" 969 (BC_2, IO_N16, input, X),\" & --  PAD392\n\t\" 970 (BC_2, *, controlr, 1),\" &\n\t\" 971 (BC_2, IO_L14, output3, X, 970, 1, Z),\" & --  PAD391\n\t\" 972 (BC_2, IO_L14, input, X),\" & --  PAD391\n\t\" 973 (BC_2, *, controlr, 1),\" &\n\t\" 974 (BC_2, IO_M14, output3, X, 973, 1, Z),\" & --  PAD390\n\t\" 975 (BC_2, IO_M14, input, X),\" & --  PAD390\n\t\" 976 (BC_2, *, controlr, 1),\" &\n\t\" 977 (BC_2, IO_L11, output3, X, 976, 1, Z),\" & --  PAD389\n\t\" 978 (BC_2, IO_L11, input, X),\" & --  PAD389\n\t\" 979 (BC_2, *, controlr, 1),\" &\n\t\" 980 (BC_2, IO_L12, output3, X, 979, 1, Z),\" & --  PAD388\n\t\" 981 (BC_2, IO_L12, input, X),\" & --  PAD388\n\t\" 982 (BC_2, *, controlr, 1),\" &\n\t\" 983 (BC_2, IO_L15, output3, X, 982, 1, Z),\" & --  PAD387\n\t\" 984 (BC_2, IO_L15, input, X),\" & --  PAD387\n\t\" 985 (BC_2, *, controlr, 1),\" &\n\t\" 986 (BC_2, IO_L16, output3, X, 985, 1, Z),\" & --  PAD386\n\t\" 987 (BC_2, IO_L16, input, X),\" & --  PAD386\n\t\" 988 (BC_2, *, controlr, 1),\" &\n\t\" 989 (BC_2, IO_K13, output3, X, 988, 1, Z),\" & --  PAD385\n\t\" 990 (BC_2, IO_K13, input, X),\" & --  PAD385\n\t\" 991 (BC_2, *, controlr, 1),\" &\n\t\" 992 (BC_2, IO_K14, output3, X, 991, 1, Z),\" & --  PAD384\n\t\" 993 (BC_2, IO_K14, input, X),\" & --  PAD384\n\t\" 994 (BC_2, *, controlr, 1),\" &\n\t\" 995 (BC_2, IO_J15, output3, X, 994, 1, Z),\" & --  PAD383\n\t\" 996 (BC_2, IO_J15, input, X),\" & --  PAD383\n\t\" 997 (BC_2, *, controlr, 1),\" &\n\t\" 998 (BC_2, IO_K15, output3, X, 997, 1, Z),\" & --  PAD382\n\t\" 999 (BC_2, IO_K15, input, X),\" & --  PAD382\n\t\"1000 (BC_2, *, controlr, 1),\" &\n\t\"1001 (BC_2, IO_J12, output3, X, 1000, 1, Z),\" & --  PAD381\n\t\"1002 (BC_2, IO_J12, input, X),\" & --  PAD381\n\t\"1003 (BC_2, *, controlr, 1),\" &\n\t\"1004 (BC_2, IO_K12, output3, X, 1003, 1, Z),\" & --  PAD380\n\t\"1005 (BC_2, IO_K12, input, X),\" & --  PAD380\n\t\"1006 (BC_2, *, controlr, 1),\" &\n\t\"1007 (BC_2, IO_H13, output3, X, 1006, 1, Z),\" & --  PAD379\n\t\"1008 (BC_2, IO_H13, input, X),\" & --  PAD379\n\t\"1009 (BC_2, *, controlr, 1),\" &\n\t\"1010 (BC_2, IO_J13, output3, X, 1009, 1, Z),\" & --  PAD378\n\t\"1011 (BC_2, IO_J13, input, X),\" & --  PAD378\n\t\"1012 (BC_2, *, controlr, 1),\" &\n\t\"1013 (BC_2, IO_H14, output3, X, 1012, 1, Z),\" & --  PAD377\n\t\"1014 (BC_2, IO_H14, input, X),\" & --  PAD377\n\t\"1015 (BC_2, *, controlr, 1),\" &\n\t\"1016 (BC_2, IO_H15, output3, X, 1015, 1, Z),\" & --  PAD376\n\t\"1017 (BC_2, IO_H15, input, X),\" & --  PAD376\n\t\"1018 (BC_2, *, controlr, 1),\" &\n\t\"1019 (BC_2, IO_G13, output3, X, 1018, 1, Z),\" & --  PAD375\n\t\"1020 (BC_2, IO_G13, input, X),\" & --  PAD375\n\t\"1021 (BC_2, *, controlr, 1),\" &\n\t\"1022 (BC_2, IO_G14, output3, X, 1021, 1, Z),\" & --  PAD374\n\t\"1023 (BC_2, IO_G14, input, X),\" & --  PAD374\n\t\"1024 (BC_2, *, controlr, 1),\" &\n\t\"1025 (BC_2, IO_F14, output3, X, 1024, 1, Z),\" & --  PAD373\n\t\"1026 (BC_2, IO_F14, input, X),\" & --  PAD373\n\t\"1027 (BC_2, *, controlr, 1),\" &\n\t\"1028 (BC_2, IO_F15, output3, X, 1027, 1, Z),\" & --  PAD372\n\t\"1029 (BC_2, IO_F15, input, X),\" & --  PAD372\n\t\"1030 (BC_2, *, controlr, 1),\" &\n\t\"1031 (BC_2, IO_F12, output3, X, 1030, 1, Z),\" & --  PAD371\n\t\"1032 (BC_2, IO_F12, input, X),\" & --  PAD371\n\t\"1033 (BC_2, *, controlr, 1),\" &\n\t\"1034 (BC_2, IO_G12, output3, X, 1033, 1, Z),\" & --  PAD370\n\t\"1035 (BC_2, IO_G12, input, X),\" & --  PAD370\n\t\"1036 (BC_2, *, controlr, 1),\" &\n\t\"1037 (BC_2, IO_G16, output3, X, 1036, 1, Z),\" & --  PAD369\n\t\"1038 (BC_2, IO_G16, input, X),\" & --  PAD369\n\t\"1039 (BC_2, *, controlr, 1),\" &\n\t\"1040 (BC_2, IO_H16, output3, X, 1039, 1, Z),\" & --  PAD368\n\t\"1041 (BC_2, IO_H16, input, X),\" & --  PAD368\n\t\"1042 (BC_2, *, controlr, 1),\" &\n\t\"1043 (BC_2, IO_E13, output3, X, 1042, 1, Z),\" & --  PAD367\n\t\"1044 (BC_2, IO_E13, input, X),\" & --  PAD367\n\t\"1045 (BC_2, *, controlr, 1),\" &\n\t\"1046 (BC_2, IO_E14, output3, X, 1045, 1, Z),\" & --  PAD366\n\t\"1047 (BC_2, IO_E14, input, X),\" & --  PAD366\n\t\"1048 (BC_2, *, controlr, 1),\" &\n\t\"1049 (BC_2, IO_E15, output3, X, 1048, 1, Z),\" & --  PAD365\n\t\"1050 (BC_2, IO_E15, input, X),\" & --  PAD365\n\t\"1051 (BC_2, *, controlr, 1),\" &\n\t\"1052 (BC_2, IO_F16, output3, X, 1051, 1, Z),\" & --  PAD364\n\t\"1053 (BC_2, IO_F16, input, X),\" & --  PAD364\n\t\"1054 (BC_2, *, controlr, 1),\" &\n\t\"1055 (BC_2, IO_D12, output3, X, 1054, 1, Z),\" & --  PAD363\n\t\"1056 (BC_2, IO_D12, input, X),\" & --  PAD363\n\t\"1057 (BC_2, *, controlr, 1),\" &\n\t\"1058 (BC_2, IO_E12, output3, X, 1057, 1, Z),\" & --  PAD362\n\t\"1059 (BC_2, IO_E12, input, X),\" & --  PAD362\n\t\"1060 (BC_2, *, controlr, 1),\" &\n\t\"1061 (BC_2, IO_D15, output3, X, 1060, 1, Z),\" & --  PAD361\n\t\"1062 (BC_2, IO_D15, input, X),\" & --  PAD361\n\t\"1063 (BC_2, *, controlr, 1),\" &\n\t\"1064 (BC_2, IO_D16, output3, X, 1063, 1, Z),\" & --  PAD360\n\t\"1065 (BC_2, IO_D16, input, X),\" & --  PAD360\n\t\"1066 (BC_2, *, controlr, 1),\" &\n\t\"1067 (BC_2, IO_C13, output3, X, 1066, 1, Z),\" & --  PAD359\n\t\"1068 (BC_2, IO_C13, input, X),\" & --  PAD359\n\t\"1069 (BC_2, *, controlr, 1),\" &\n\t\"1070 (BC_2, IO_D13, output3, X, 1069, 1, Z),\" & --  PAD358\n\t\"1071 (BC_2, IO_D13, input, X),\" & --  PAD358\n\t\"1072 (BC_2, *, controlr, 1),\" &\n\t\"1073 (BC_2, IO_C14, output3, X, 1072, 1, Z),\" & --  PAD357\n\t\"1074 (BC_2, IO_C14, input, X),\" & --  PAD357\n\t\"1075 (BC_2, *, controlr, 1),\" &\n\t\"1076 (BC_2, IO_C15, output3, X, 1075, 1, Z),\" & --  PAD356\n\t\"1077 (BC_2, IO_C15, input, X),\" & --  PAD356\n\t\"1078 (BC_2, *, controlr, 1),\" &\n\t\"1079 (BC_2, IO_A14, output3, X, 1078, 1, Z),\" & --  PAD355\n\t\"1080 (BC_2, IO_A14, input, X),\" & --  PAD355\n\t\"1081 (BC_2, *, controlr, 1),\" &\n\t\"1082 (BC_2, IO_B14, output3, X, 1081, 1, Z),\" & --  PAD354\n\t\"1083 (BC_2, IO_B14, input, X),\" & --  PAD354\n\t\"1084 (BC_2, *, controlr, 1),\" &\n\t\"1085 (BC_2, IO_B16, output3, X, 1084, 1, Z),\" & --  PAD353\n\t\"1086 (BC_2, IO_B16, input, X),\" & --  PAD353\n\t\"1087 (BC_2, *, controlr, 1),\" &\n\t\"1088 (BC_2, IO_C16, output3, X, 1087, 1, Z),\" & --  PAD352\n\t\"1089 (BC_2, IO_C16, input, X),\" & --  PAD352\n\t\"1090 (BC_2, *, controlr, 1),\" &\n\t\"1091 (BC_2, IO_J16, output3, X, 1090, 1, Z),\" & --  PAD351\n\t\"1092 (BC_2, IO_J16, input, X),\" & --  PAD351\n\t\"1093 (BC_2, *, internal, X),\" &\n\t\"1094 (BC_2, *, internal, X),\" &\n\t\"1095 (BC_2, *, internal, X),\" &\n\t\"1096 (BC_2, *, internal, X),\" &\n\t\"1097 (BC_2, *, internal, X),\" &\n\t\"1098 (BC_2, *, internal, X),\" &\n\t\"1099 (BC_2, *, internal, X),\" &\n\t\"1100 (BC_2, *, internal, X),\" &\n\t\"1101 (BC_2, *, internal, X),\" &\n\t\"1102 (BC_2, *, internal, X),\" &\n\t\"1103 (BC_2, *, internal, X),\" &\n\t\"1104 (BC_2, *, internal, X),\" &\n\t\"1105 (BC_2, *, internal, X),\" &\n\t\"1106 (BC_2, *, internal, X),\" &\n\t\"1107 (BC_2, *, internal, X),\" &\n\t\"1108 (BC_2, *, internal, X),\" &\n\t\"1109 (BC_4, MGTXRXN0_113, OBSERVE_ONLY, X),\" &\n\t\"1110 (BC_4, MGTXRXP0_113, OBSERVE_ONLY, X),\" &\n\t\"1111 (AC_2, MGTXTXP0_113, OUTPUT2, X),\" &\n\t\"1112 (BC_4, MGTXRXN1_113, OBSERVE_ONLY, X),\" &\n\t\"1113 (BC_4, MGTXRXP1_113, OBSERVE_ONLY, X),\" &\n\t\"1114 (AC_2, MGTXTXP1_113, OUTPUT2, X),\" &\n\t\"1115 (BC_4, MGTXRXN2_113, OBSERVE_ONLY, X),\" &\n\t\"1116 (BC_4, MGTXRXP2_113, OBSERVE_ONLY, X),\" &\n\t\"1117 (AC_2, MGTXTXP2_113, OUTPUT2, X),\" &\n\t\"1118 (BC_4, MGTXRXN3_113, OBSERVE_ONLY, X),\" &\n\t\"1119 (BC_4, MGTXRXP3_113, OBSERVE_ONLY, X),\" &\n\t\"1120 (AC_2, MGTXTXP3_113, OUTPUT2, X),\" &\n\t\"1121 (BC_4, MGTXRXN0_114, OBSERVE_ONLY, X),\" &\n\t\"1122 (BC_4, MGTXRXP0_114, OBSERVE_ONLY, X),\" &\n\t\"1123 (AC_2, MGTXTXP0_114, OUTPUT2, X),\" &\n\t\"1124 (BC_4, MGTXRXN1_114, OBSERVE_ONLY, X),\" &\n\t\"1125 (BC_4, MGTXRXP1_114, OBSERVE_ONLY, X),\" &\n\t\"1126 (AC_2, MGTXTXP1_114, OUTPUT2, X),\" &\n\t\"1127 (BC_4, MGTXRXN2_114, OBSERVE_ONLY, X),\" &\n\t\"1128 (BC_4, MGTXRXP2_114, OBSERVE_ONLY, X),\" &\n\t\"1129 (AC_2, MGTXTXP2_114, OUTPUT2, X),\" &\n\t\"1130 (BC_4, MGTXRXN3_114, OBSERVE_ONLY, X),\" &\n\t\"1131 (BC_4, MGTXRXP3_114, OBSERVE_ONLY, X),\" &\n\t\"1132 (AC_2, MGTXTXP3_114, OUTPUT2, X),\" &\n\t\"1133 (BC_4, MGTXRXN0_115, OBSERVE_ONLY, X),\" &\n\t\"1134 (BC_4, MGTXRXP0_115, OBSERVE_ONLY, X),\" &\n\t\"1135 (AC_2, MGTXTXP0_115, OUTPUT2, X),\" &\n\t\"1136 (BC_4, MGTXRXN1_115, OBSERVE_ONLY, X),\" &\n\t\"1137 (BC_4, MGTXRXP1_115, OBSERVE_ONLY, X),\" &\n\t\"1138 (AC_2, MGTXTXP1_115, OUTPUT2, X),\" &\n\t\"1139 (BC_4, MGTXRXN2_115, OBSERVE_ONLY, X),\" &\n\t\"1140 (BC_4, MGTXRXP2_115, OBSERVE_ONLY, X),\" &\n\t\"1141 (AC_2, MGTXTXP2_115, OUTPUT2, X),\" &\n\t\"1142 (BC_4, MGTXRXN3_115, OBSERVE_ONLY, X),\" &\n\t\"1143 (BC_4, MGTXRXP3_115, OBSERVE_ONLY, X),\" &\n\t\"1144 (AC_2, MGTXTXP3_115, OUTPUT2, X),\" &\n\t\"1145 (BC_4, MGTXRXN0_116, OBSERVE_ONLY, X),\" &\n\t\"1146 (BC_4, MGTXRXP0_116, OBSERVE_ONLY, X),\" &\n\t\"1147 (AC_2, MGTXTXP0_116, OUTPUT2, X),\" &\n\t\"1148 (BC_4, MGTXRXN1_116, OBSERVE_ONLY, X),\" &\n\t\"1149 (BC_4, MGTXRXP1_116, OBSERVE_ONLY, X),\" &\n\t\"1150 (AC_2, MGTXTXP1_116, OUTPUT2, X),\" &\n\t\"1151 (BC_4, MGTXRXN2_116, OBSERVE_ONLY, X),\" &\n\t\"1152 (BC_4, MGTXRXP2_116, OBSERVE_ONLY, X),\" &\n\t\"1153 (AC_2, MGTXTXP2_116, OUTPUT2, X),\" &\n\t\"1154 (BC_4, MGTXRXN3_116, OBSERVE_ONLY, X),\" &\n\t\"1155 (BC_4, MGTXRXP3_116, OBSERVE_ONLY, X),\" &\n\t\"1156 (AC_2, MGTXTXP3_116, OUTPUT2, X),\" &\n\t\"1157 (BC_4, MGTXRXN0_117, OBSERVE_ONLY, X),\" &\n\t\"1158 (BC_4, MGTXRXP0_117, OBSERVE_ONLY, X),\" &\n\t\"1159 (AC_2, MGTXTXP0_117, OUTPUT2, X),\" &\n\t\"1160 (BC_4, MGTXRXN1_117, OBSERVE_ONLY, X),\" &\n\t\"1161 (BC_4, MGTXRXP1_117, OBSERVE_ONLY, X),\" &\n\t\"1162 (AC_2, MGTXTXP1_117, OUTPUT2, X),\" &\n\t\"1163 (BC_4, MGTXRXN2_117, OBSERVE_ONLY, X),\" &\n\t\"1164 (BC_4, MGTXRXP2_117, OBSERVE_ONLY, X),\" &\n\t\"1165 (AC_2, MGTXTXP2_117, OUTPUT2, X),\" &\n\t\"1166 (BC_4, MGTXRXN3_117, OBSERVE_ONLY, X),\" &\n\t\"1167 (BC_4, MGTXRXP3_117, OBSERVE_ONLY, X),\" &\n\t\"1168 (AC_2, MGTXTXP3_117, OUTPUT2, X),\" &\n\t\"1169 (BC_4, MGTXRXN0_118, OBSERVE_ONLY, X),\" &\n\t\"1170 (BC_4, MGTXRXP0_118, OBSERVE_ONLY, X),\" &\n\t\"1171 (AC_2, MGTXTXP0_118, OUTPUT2, X),\" &\n\t\"1172 (BC_4, MGTXRXN1_118, OBSERVE_ONLY, X),\" &\n\t\"1173 (BC_4, MGTXRXP1_118, OBSERVE_ONLY, X),\" &\n\t\"1174 (AC_2, MGTXTXP1_118, OUTPUT2, X),\" &\n\t\"1175 (BC_4, MGTXRXN2_118, OBSERVE_ONLY, X),\" &\n\t\"1176 (BC_4, MGTXRXP2_118, OBSERVE_ONLY, X),\" &\n\t\"1177 (AC_2, MGTXTXP2_118, OUTPUT2, X),\" &\n\t\"1178 (BC_4, MGTXRXN3_118, OBSERVE_ONLY, X),\" &\n\t\"1179 (BC_4, MGTXRXP3_118, OBSERVE_ONLY, X),\" &\n\t\"1180 (AC_2, MGTXTXP3_118, OUTPUT2, X),\" &\n\t\"1181 (BC_4, MGTXRXN0_119, OBSERVE_ONLY, X),\" &\n\t\"1182 (BC_4, MGTXRXP0_119, OBSERVE_ONLY, X),\" &\n\t\"1183 (AC_2, MGTXTXP0_119, OUTPUT2, X),\" &\n\t\"1184 (BC_4, MGTXRXN1_119, OBSERVE_ONLY, X),\" &\n\t\"1185 (BC_4, MGTXRXP1_119, OBSERVE_ONLY, X),\" &\n\t\"1186 (AC_2, MGTXTXP1_119, OUTPUT2, X),\" &\n\t\"1187 (BC_4, MGTXRXN2_119, OBSERVE_ONLY, X),\" &\n\t\"1188 (BC_4, MGTXRXP2_119, OBSERVE_ONLY, X),\" &\n\t\"1189 (AC_2, MGTXTXP2_119, OUTPUT2, X),\" &\n\t\"1190 (BC_4, MGTXRXN3_119, OBSERVE_ONLY, X),\" &\n\t\"1191 (BC_4, MGTXRXP3_119, OBSERVE_ONLY, X),\" &\n\t\"1192 (AC_2, MGTXTXP3_119, OUTPUT2, X),\" &\n\t\"1193 (BC_2, *, internal, X),\" &\n\t\"1194 (BC_2, *, internal, X),\" &\n\t\"1195 (BC_2, *, internal, X),\" &\n\t\"1196 (BC_2, *, internal, X),\" &\n\t\"1197 (BC_2, *, internal, X),\" &\n\t\"1198 (BC_2, *, internal, X),\" &\n\t\"1199 (BC_2, *, internal, X),\" &\n\t\"1200 (BC_2, *, internal, X),\" &\n\t\"1201 (BC_2, *, internal, X),\" &\n\t\"1202 (BC_2, *, internal, X),\" &\n\t\"1203 (BC_2, *, internal, X),\" &\n\t\"1204 (BC_2, *, internal, X),\" &\n\t\"1205 (BC_2, *, internal, X),\" &\n\t\"1206 (BC_2, *, internal, X),\" &\n\t\"1207 (BC_2, *, internal, X),\" &\n\t\"1208 (BC_2, *, internal, X),\" &\n\t\"1209 (BC_2, *, internal, X),\" &\n\t\"1210 (BC_2, *, internal, X),\" &\n\t\"1211 (BC_2, *, internal, X),\" &\n\t\"1212 (BC_2, *, internal, X),\" &\n\t\"1213 (BC_2, *, internal, X),\" &\n\t\"1214 (BC_2, *, internal, X),\" &\n\t\"1215 (BC_2, *, internal, X),\" &\n\t\"1216 (BC_2, *, internal, X),\" &\n\t\"1217 (BC_2, *, internal, X),\" &\n\t\"1218 (BC_2, *, internal, X),\" &\n\t\"1219 (BC_2, *, internal, X),\" &\n\t\"1220 (BC_2, *, internal, X),\" &\n\t\"1221 (BC_2, *, internal, X),\" &\n\t\"1222 (BC_2, *, internal, X),\" &\n\t\"1223 (BC_2, *, internal, X),\" &\n\t\"1224 (BC_2, *, internal, X),\" &\n\t\"1225 (BC_2, *, internal, X),\" &\n\t\"1226 (BC_2, *, internal, X),\" &\n\t\"1227 (BC_2, *, internal, X),\" &\n\t\"1228 (BC_2, *, internal, X),\" &\n\t\"1229 (BC_2, *, internal, X),\" &\n\t\"1230 (BC_2, *, controlr, 1),\" &\n\t\"1231 (BC_2, IO_AT31, output3, X, 1230, 1, Z),\" & --  PAD350\n\t\"1232 (BC_2, IO_AT31, input, X),\" & --  PAD350\n\t\"1233 (BC_2, *, controlr, 1),\" &\n\t\"1234 (BC_2, IO_AR33, output3, X, 1233, 1, Z),\" & --  PAD349\n\t\"1235 (BC_2, IO_AR33, input, X),\" & --  PAD349\n\t\"1236 (BC_2, *, controlr, 1),\" &\n\t\"1237 (BC_2, IO_AP33, output3, X, 1236, 1, Z),\" & --  PAD348\n\t\"1238 (BC_2, IO_AP33, input, X),\" & --  PAD348\n\t\"1239 (BC_2, *, controlr, 1),\" &\n\t\"1240 (BC_2, IO_AP31, output3, X, 1239, 1, Z),\" & --  PAD347\n\t\"1241 (BC_2, IO_AP31, input, X),\" & --  PAD347\n\t\"1242 (BC_2, *, controlr, 1),\" &\n\t\"1243 (BC_2, IO_AN31, output3, X, 1242, 1, Z),\" & --  PAD346\n\t\"1244 (BC_2, IO_AN31, input, X),\" & --  PAD346\n\t\"1245 (BC_2, *, controlr, 1),\" &\n\t\"1246 (BC_2, IO_AR32, output3, X, 1245, 1, Z),\" & --  PAD345\n\t\"1247 (BC_2, IO_AR32, input, X),\" & --  PAD345\n\t\"1248 (BC_2, *, controlr, 1),\" &\n\t\"1249 (BC_2, IO_AP32, output3, X, 1248, 1, Z),\" & --  PAD344\n\t\"1250 (BC_2, IO_AP32, input, X),\" & --  PAD344\n\t\"1251 (BC_2, *, controlr, 1),\" &\n\t\"1252 (BC_2, IO_AP30, output3, X, 1251, 1, Z),\" & --  PAD343\n\t\"1253 (BC_2, IO_AP30, input, X),\" & --  PAD343\n\t\"1254 (BC_2, *, controlr, 1),\" &\n\t\"1255 (BC_2, IO_AN30, output3, X, 1254, 1, Z),\" & --  PAD342\n\t\"1256 (BC_2, IO_AN30, input, X),\" & --  PAD342\n\t\"1257 (BC_2, *, controlr, 1),\" &\n\t\"1258 (BC_2, IO_AV31, output3, X, 1257, 1, Z),\" & --  PAD341\n\t\"1259 (BC_2, IO_AV31, input, X),\" & --  PAD341\n\t\"1260 (BC_2, *, controlr, 1),\" &\n\t\"1261 (BC_2, IO_AU31, output3, X, 1260, 1, Z),\" & --  PAD340\n\t\"1262 (BC_2, IO_AU31, input, X),\" & --  PAD340\n\t\"1263 (BC_2, *, controlr, 1),\" &\n\t\"1264 (BC_2, IO_AT30, output3, X, 1263, 1, Z),\" & --  PAD339\n\t\"1265 (BC_2, IO_AT30, input, X),\" & --  PAD339\n\t\"1266 (BC_2, *, controlr, 1),\" &\n\t\"1267 (BC_2, IO_AR30, output3, X, 1266, 1, Z),\" & --  PAD338\n\t\"1268 (BC_2, IO_AR30, input, X),\" & --  PAD338\n\t\"1269 (BC_2, *, controlr, 1),\" &\n\t\"1270 (BC_2, IO_AW31, output3, X, 1269, 1, Z),\" & --  PAD337\n\t\"1271 (BC_2, IO_AW31, input, X),\" & --  PAD337\n\t\"1272 (BC_2, *, controlr, 1),\" &\n\t\"1273 (BC_2, IO_AV30, output3, X, 1272, 1, Z),\" & --  PAD336\n\t\"1274 (BC_2, IO_AV30, input, X),\" & --  PAD336\n\t\"1275 (BC_2, *, controlr, 1),\" &\n\t\"1276 (BC_2, IO_BB31, output3, X, 1275, 1, Z),\" & --  PAD335\n\t\"1277 (BC_2, IO_BB31, input, X),\" & --  PAD335\n\t\"1278 (BC_2, *, controlr, 1),\" &\n\t\"1279 (BC_2, IO_BA30, output3, X, 1278, 1, Z),\" & --  PAD334\n\t\"1280 (BC_2, IO_BA30, input, X),\" & --  PAD334\n\t\"1281 (BC_2, *, controlr, 1),\" &\n\t\"1282 (BC_2, IO_AY30, output3, X, 1281, 1, Z),\" & --  PAD333\n\t\"1283 (BC_2, IO_AY30, input, X),\" & --  PAD333\n\t\"1284 (BC_2, *, controlr, 1),\" &\n\t\"1285 (BC_2, IO_AW30, output3, X, 1284, 1, Z),\" & --  PAD332\n\t\"1286 (BC_2, IO_AW30, input, X),\" & --  PAD332\n\t\"1287 (BC_2, *, controlr, 1),\" &\n\t\"1288 (BC_2, IO_BA32, output3, X, 1287, 1, Z),\" & --  PAD331\n\t\"1289 (BC_2, IO_BA32, input, X),\" & --  PAD331\n\t\"1290 (BC_2, *, controlr, 1),\" &\n\t\"1291 (BC_2, IO_BA31, output3, X, 1290, 1, Z),\" & --  PAD330\n\t\"1292 (BC_2, IO_BA31, input, X),\" & --  PAD330\n\t\"1293 (BC_2, *, controlr, 1),\" &\n\t\"1294 (BC_2, IO_AY33, output3, X, 1293, 1, Z),\" & --  PAD329\n\t\"1295 (BC_2, IO_AY33, input, X),\" & --  PAD329\n\t\"1296 (BC_2, *, controlr, 1),\" &\n\t\"1297 (BC_2, IO_AY32, output3, X, 1296, 1, Z),\" & --  PAD328\n\t\"1298 (BC_2, IO_AY32, input, X),\" & --  PAD328\n\t\"1299 (BC_2, *, controlr, 1),\" &\n\t\"1300 (BC_2, IO_AV35, output3, X, 1299, 1, Z),\" & --  PAD327\n\t\"1301 (BC_2, IO_AV35, input, X),\" & --  PAD327\n\t\"1302 (BC_2, *, controlr, 1),\" &\n\t\"1303 (BC_2, IO_AV34, output3, X, 1302, 1, Z),\" & --  PAD326\n\t\"1304 (BC_2, IO_AV34, input, X),\" & --  PAD326\n\t\"1305 (BC_2, *, controlr, 1),\" &\n\t\"1306 (BC_2, IO_AW33, output3, X, 1305, 1, Z),\" & --  PAD325\n\t\"1307 (BC_2, IO_AW33, input, X),\" & --  PAD325\n\t\"1308 (BC_2, *, controlr, 1),\" &\n\t\"1309 (BC_2, IO_AW32, output3, X, 1308, 1, Z),\" & --  PAD324\n\t\"1310 (BC_2, IO_AW32, input, X),\" & --  PAD324\n\t\"1311 (BC_2, *, controlr, 1),\" &\n\t\"1312 (BC_2, IO_AV33, output3, X, 1311, 1, Z),\" & --  PAD323\n\t\"1313 (BC_2, IO_AV33, input, X),\" & --  PAD323\n\t\"1314 (BC_2, *, controlr, 1),\" &\n\t\"1315 (BC_2, IO_AU32, output3, X, 1314, 1, Z),\" & --  PAD322\n\t\"1316 (BC_2, IO_AU32, input, X),\" & --  PAD322\n\t\"1317 (BC_2, *, controlr, 1),\" &\n\t\"1318 (BC_2, IO_AT35, output3, X, 1317, 1, Z),\" & --  PAD321\n\t\"1319 (BC_2, IO_AT35, input, X),\" & --  PAD321\n\t\"1320 (BC_2, *, controlr, 1),\" &\n\t\"1321 (BC_2, IO_AR34, output3, X, 1320, 1, Z),\" & --  PAD320\n\t\"1322 (BC_2, IO_AR34, input, X),\" & --  PAD320\n\t\"1323 (BC_2, *, controlr, 1),\" &\n\t\"1324 (BC_2, IO_AU33, output3, X, 1323, 1, Z),\" & --  PAD319\n\t\"1325 (BC_2, IO_AU33, input, X),\" & --  PAD319\n\t\"1326 (BC_2, *, controlr, 1),\" &\n\t\"1327 (BC_2, IO_AT32, output3, X, 1326, 1, Z),\" & --  PAD318\n\t\"1328 (BC_2, IO_AT32, input, X),\" & --  PAD318\n\t\"1329 (BC_2, *, controlr, 1),\" &\n\t\"1330 (BC_2, IO_AU36, output3, X, 1329, 1, Z),\" & --  PAD317\n\t\"1331 (BC_2, IO_AU36, input, X),\" & --  PAD317\n\t\"1332 (BC_2, *, controlr, 1),\" &\n\t\"1333 (BC_2, IO_AT36, output3, X, 1332, 1, Z),\" & --  PAD316\n\t\"1334 (BC_2, IO_AT36, input, X),\" & --  PAD316\n\t\"1335 (BC_2, *, controlr, 1),\" &\n\t\"1336 (BC_2, IO_AU34, output3, X, 1335, 1, Z),\" & --  PAD315\n\t\"1337 (BC_2, IO_AU34, input, X),\" & --  PAD315\n\t\"1338 (BC_2, *, controlr, 1),\" &\n\t\"1339 (BC_2, IO_AT34, output3, X, 1338, 1, Z),\" & --  PAD314\n\t\"1340 (BC_2, IO_AT34, input, X),\" & --  PAD314\n\t\"1341 (BC_2, *, controlr, 1),\" &\n\t\"1342 (BC_2, IO_AY35, output3, X, 1341, 1, Z),\" & --  PAD313\n\t\"1343 (BC_2, IO_AY35, input, X),\" & --  PAD313\n\t\"1344 (BC_2, *, controlr, 1),\" &\n\t\"1345 (BC_2, IO_AW35, output3, X, 1344, 1, Z),\" & --  PAD312\n\t\"1346 (BC_2, IO_AW35, input, X),\" & --  PAD312\n\t\"1347 (BC_2, *, controlr, 1),\" &\n\t\"1348 (BC_2, IO_BB33, output3, X, 1347, 1, Z),\" & --  PAD311\n\t\"1349 (BC_2, IO_BB33, input, X),\" & --  PAD311\n\t\"1350 (BC_2, *, controlr, 1),\" &\n\t\"1351 (BC_2, IO_BB32, output3, X, 1350, 1, Z),\" & --  PAD310\n\t\"1352 (BC_2, IO_BB32, input, X),\" & --  PAD310\n\t\"1353 (BC_2, *, controlr, 1),\" &\n\t\"1354 (BC_2, IO_BB36, output3, X, 1353, 1, Z),\" & --  PAD309\n\t\"1355 (BC_2, IO_BB36, input, X),\" & --  PAD309\n\t\"1356 (BC_2, *, controlr, 1),\" &\n\t\"1357 (BC_2, IO_BA36, output3, X, 1356, 1, Z),\" & --  PAD308\n\t\"1358 (BC_2, IO_BA36, input, X),\" & --  PAD308\n\t\"1359 (BC_2, *, controlr, 1),\" &\n\t\"1360 (BC_2, IO_BB34, output3, X, 1359, 1, Z),\" & --  PAD307\n\t\"1361 (BC_2, IO_BB34, input, X),\" & --  PAD307\n\t\"1362 (BC_2, *, controlr, 1),\" &\n\t\"1363 (BC_2, IO_BA34, output3, X, 1362, 1, Z),\" & --  PAD306\n\t\"1364 (BC_2, IO_BA34, input, X),\" & --  PAD306\n\t\"1365 (BC_2, *, controlr, 1),\" &\n\t\"1366 (BC_2, IO_AW36, output3, X, 1365, 1, Z),\" & --  PAD305\n\t\"1367 (BC_2, IO_AW36, input, X),\" & --  PAD305\n\t\"1368 (BC_2, *, controlr, 1),\" &\n\t\"1369 (BC_2, IO_AV36, output3, X, 1368, 1, Z),\" & --  PAD304\n\t\"1370 (BC_2, IO_AV36, input, X),\" & --  PAD304\n\t\"1371 (BC_2, *, controlr, 1),\" &\n\t\"1372 (BC_2, IO_BA35, output3, X, 1371, 1, Z),\" & --  PAD303\n\t\"1373 (BC_2, IO_BA35, input, X),\" & --  PAD303\n\t\"1374 (BC_2, *, controlr, 1),\" &\n\t\"1375 (BC_2, IO_AY34, output3, X, 1374, 1, Z),\" & --  PAD302\n\t\"1376 (BC_2, IO_AY34, input, X),\" & --  PAD302\n\t\"1377 (BC_2, *, controlr, 1),\" &\n\t\"1378 (BC_2, IO_AR35, output3, X, 1377, 1, Z),\" & --  PAD301\n\t\"1379 (BC_2, IO_AR35, input, X),\" & --  PAD301\n\t\"1380 (BC_2, *, controlr, 1),\" &\n\t\"1381 (BC_2, IO_AG32, output3, X, 1380, 1, Z),\" & --  PAD300\n\t\"1382 (BC_2, IO_AG32, input, X),\" & --  PAD300\n\t\"1383 (BC_2, *, controlr, 1),\" &\n\t\"1384 (BC_2, IO_AJ28, output3, X, 1383, 1, Z),\" & --  PAD299\n\t\"1385 (BC_2, IO_AJ28, input, X),\" & --  PAD299\n\t\"1386 (BC_2, *, controlr, 1),\" &\n\t\"1387 (BC_2, IO_AH28, output3, X, 1386, 1, Z),\" & --  PAD298\n\t\"1388 (BC_2, IO_AH28, input, X),\" & --  PAD298\n\t\"1389 (BC_2, *, controlr, 1),\" &\n\t\"1390 (BC_2, IO_AG31, output3, X, 1389, 1, Z),\" & --  PAD297\n\t\"1391 (BC_2, IO_AG31, input, X),\" & --  PAD297\n\t\"1392 (BC_2, *, controlr, 1),\" &\n\t\"1393 (BC_2, IO_AF30, output3, X, 1392, 1, Z),\" & --  PAD296\n\t\"1394 (BC_2, IO_AF30, input, X),\" & --  PAD296\n\t\"1395 (BC_2, *, controlr, 1),\" &\n\t\"1396 (BC_2, IO_AK29, output3, X, 1395, 1, Z),\" & --  PAD295\n\t\"1397 (BC_2, IO_AK29, input, X),\" & --  PAD295\n\t\"1398 (BC_2, *, controlr, 1),\" &\n\t\"1399 (BC_2, IO_AK28, output3, X, 1398, 1, Z),\" & --  PAD294\n\t\"1400 (BC_2, IO_AK28, input, X),\" & --  PAD294\n\t\"1401 (BC_2, *, controlr, 1),\" &\n\t\"1402 (BC_2, IO_AG29, output3, X, 1401, 1, Z),\" & --  PAD293\n\t\"1403 (BC_2, IO_AG29, input, X),\" & --  PAD293\n\t\"1404 (BC_2, *, controlr, 1),\" &\n\t\"1405 (BC_2, IO_AF29, output3, X, 1404, 1, Z),\" & --  PAD292\n\t\"1406 (BC_2, IO_AF29, input, X),\" & --  PAD292\n\t\"1407 (BC_2, *, controlr, 1),\" &\n\t\"1408 (BC_2, IO_AK30, output3, X, 1407, 1, Z),\" & --  PAD291\n\t\"1409 (BC_2, IO_AK30, input, X),\" & --  PAD291\n\t\"1410 (BC_2, *, controlr, 1),\" &\n\t\"1411 (BC_2, IO_AJ30, output3, X, 1410, 1, Z),\" & --  PAD290\n\t\"1412 (BC_2, IO_AJ30, input, X),\" & --  PAD290\n\t\"1413 (BC_2, *, controlr, 1),\" &\n\t\"1414 (BC_2, IO_AH30, output3, X, 1413, 1, Z),\" & --  PAD289\n\t\"1415 (BC_2, IO_AH30, input, X),\" & --  PAD289\n\t\"1416 (BC_2, *, controlr, 1),\" &\n\t\"1417 (BC_2, IO_AH29, output3, X, 1416, 1, Z),\" & --  PAD288\n\t\"1418 (BC_2, IO_AH29, input, X),\" & --  PAD288\n\t\"1419 (BC_2, *, controlr, 1),\" &\n\t\"1420 (BC_2, IO_AL30, output3, X, 1419, 1, Z),\" & --  PAD287\n\t\"1421 (BC_2, IO_AL30, input, X),\" & --  PAD287\n\t\"1422 (BC_2, *, controlr, 1),\" &\n\t\"1423 (BC_2, IO_AL29, output3, X, 1422, 1, Z),\" & --  PAD286\n\t\"1424 (BC_2, IO_AL29, input, X),\" & --  PAD286\n\t\"1425 (BC_2, *, controlr, 1),\" &\n\t\"1426 (BC_2, IO_AN33, output3, X, 1425, 1, Z),\" & --  PAD285\n\t\"1427 (BC_2, IO_AN33, input, X),\" & --  PAD285\n\t\"1428 (BC_2, *, controlr, 1),\" &\n\t\"1429 (BC_2, IO_AM33, output3, X, 1428, 1, Z),\" & --  PAD284\n\t\"1430 (BC_2, IO_AM33, input, X),\" & --  PAD284\n\t\"1431 (BC_2, *, controlr, 1),\" &\n\t\"1432 (BC_2, IO_AM32, output3, X, 1431, 1, Z),\" & --  PAD283\n\t\"1433 (BC_2, IO_AM32, input, X),\" & --  PAD283\n\t\"1434 (BC_2, *, controlr, 1),\" &\n\t\"1435 (BC_2, IO_AM31, output3, X, 1434, 1, Z),\" & --  PAD282\n\t\"1436 (BC_2, IO_AM31, input, X),\" & --  PAD282\n\t\"1437 (BC_2, *, controlr, 1),\" &\n\t\"1438 (BC_2, IO_AN34, output3, X, 1437, 1, Z),\" & --  PAD281\n\t\"1439 (BC_2, IO_AN34, input, X),\" & --  PAD281\n\t\"1440 (BC_2, *, controlr, 1),\" &\n\t\"1441 (BC_2, IO_AM34, output3, X, 1440, 1, Z),\" & --  PAD280\n\t\"1442 (BC_2, IO_AM34, input, X),\" & --  PAD280\n\t\"1443 (BC_2, *, controlr, 1),\" &\n\t\"1444 (BC_2, IO_AL32, output3, X, 1443, 1, Z),\" & --  PAD279\n\t\"1445 (BC_2, IO_AL32, input, X),\" & --  PAD279\n\t\"1446 (BC_2, *, controlr, 1),\" &\n\t\"1447 (BC_2, IO_AL31, output3, X, 1446, 1, Z),\" & --  PAD278\n\t\"1448 (BC_2, IO_AL31, input, X),\" & --  PAD278\n\t\"1449 (BC_2, *, controlr, 1),\" &\n\t\"1450 (BC_2, IO_AK32, output3, X, 1449, 1, Z),\" & --  PAD277\n\t\"1451 (BC_2, IO_AK32, input, X),\" & --  PAD277\n\t\"1452 (BC_2, *, controlr, 1),\" &\n\t\"1453 (BC_2, IO_AJ32, output3, X, 1452, 1, Z),\" & --  PAD276\n\t\"1454 (BC_2, IO_AJ32, input, X),\" & --  PAD276\n\t\"1455 (BC_2, *, controlr, 1),\" &\n\t\"1456 (BC_2, IO_AL34, output3, X, 1455, 1, Z),\" & --  PAD275\n\t\"1457 (BC_2, IO_AL34, input, X),\" & --  PAD275\n\t\"1458 (BC_2, *, controlr, 1),\" &\n\t\"1459 (BC_2, IO_AK34, output3, X, 1458, 1, Z),\" & --  PAD274\n\t\"1460 (BC_2, IO_AK34, input, X),\" & --  PAD274\n\t\"1461 (BC_2, *, controlr, 1),\" &\n\t\"1462 (BC_2, IO_AK33, output3, X, 1461, 1, Z),\" & --  PAD273\n\t\"1463 (BC_2, IO_AK33, input, X),\" & --  PAD273\n\t\"1464 (BC_2, *, controlr, 1),\" &\n\t\"1465 (BC_2, IO_AJ33, output3, X, 1464, 1, Z),\" & --  PAD272\n\t\"1466 (BC_2, IO_AJ33, input, X),\" & --  PAD272\n\t\"1467 (BC_2, *, controlr, 1),\" &\n\t\"1468 (BC_2, IO_AJ35, output3, X, 1467, 1, Z),\" & --  PAD271\n\t\"1469 (BC_2, IO_AJ35, input, X),\" & --  PAD271\n\t\"1470 (BC_2, *, controlr, 1),\" &\n\t\"1471 (BC_2, IO_AH34, output3, X, 1470, 1, Z),\" & --  PAD270\n\t\"1472 (BC_2, IO_AH34, input, X),\" & --  PAD270\n\t\"1473 (BC_2, *, controlr, 1),\" &\n\t\"1474 (BC_2, IO_AJ31, output3, X, 1473, 1, Z),\" & --  PAD269\n\t\"1475 (BC_2, IO_AJ31, input, X),\" & --  PAD269\n\t\"1476 (BC_2, *, controlr, 1),\" &\n\t\"1477 (BC_2, IO_AH31, output3, X, 1476, 1, Z),\" & --  PAD268\n\t\"1478 (BC_2, IO_AH31, input, X),\" & --  PAD268\n\t\"1479 (BC_2, *, controlr, 1),\" &\n\t\"1480 (BC_2, IO_AL35, output3, X, 1479, 1, Z),\" & --  PAD267\n\t\"1481 (BC_2, IO_AL35, input, X),\" & --  PAD267\n\t\"1482 (BC_2, *, controlr, 1),\" &\n\t\"1483 (BC_2, IO_AK35, output3, X, 1482, 1, Z),\" & --  PAD266\n\t\"1484 (BC_2, IO_AK35, input, X),\" & --  PAD266\n\t\"1485 (BC_2, *, controlr, 1),\" &\n\t\"1486 (BC_2, IO_AH33, output3, X, 1485, 1, Z),\" & --  PAD265\n\t\"1487 (BC_2, IO_AH33, input, X),\" & --  PAD265\n\t\"1488 (BC_2, *, controlr, 1),\" &\n\t\"1489 (BC_2, IO_AG33, output3, X, 1488, 1, Z),\" & --  PAD264\n\t\"1490 (BC_2, IO_AG33, input, X),\" & --  PAD264\n\t\"1491 (BC_2, *, controlr, 1),\" &\n\t\"1492 (BC_2, IO_AM37, output3, X, 1491, 1, Z),\" & --  PAD263\n\t\"1493 (BC_2, IO_AM37, input, X),\" & --  PAD263\n\t\"1494 (BC_2, *, controlr, 1),\" &\n\t\"1495 (BC_2, IO_AL36, output3, X, 1494, 1, Z),\" & --  PAD262\n\t\"1496 (BC_2, IO_AL36, input, X),\" & --  PAD262\n\t\"1497 (BC_2, *, controlr, 1),\" &\n\t\"1498 (BC_2, IO_AP35, output3, X, 1497, 1, Z),\" & --  PAD261\n\t\"1499 (BC_2, IO_AP35, input, X),\" & --  PAD261\n\t\"1500 (BC_2, *, controlr, 1),\" &\n\t\"1501 (BC_2, IO_AN35, output3, X, 1500, 1, Z),\" & --  PAD260\n\t\"1502 (BC_2, IO_AN35, input, X),\" & --  PAD260\n\t\"1503 (BC_2, *, controlr, 1),\" &\n\t\"1504 (BC_2, IO_AL37, output3, X, 1503, 1, Z),\" & --  PAD259\n\t\"1505 (BC_2, IO_AL37, input, X),\" & --  PAD259\n\t\"1506 (BC_2, *, controlr, 1),\" &\n\t\"1507 (BC_2, IO_AK37, output3, X, 1506, 1, Z),\" & --  PAD258\n\t\"1508 (BC_2, IO_AK37, input, X),\" & --  PAD258\n\t\"1509 (BC_2, *, controlr, 1),\" &\n\t\"1510 (BC_2, IO_AP37, output3, X, 1509, 1, Z),\" & --  PAD257\n\t\"1511 (BC_2, IO_AP37, input, X),\" & --  PAD257\n\t\"1512 (BC_2, *, controlr, 1),\" &\n\t\"1513 (BC_2, IO_AP36, output3, X, 1512, 1, Z),\" & --  PAD256\n\t\"1514 (BC_2, IO_AP36, input, X),\" & --  PAD256\n\t\"1515 (BC_2, *, controlr, 1),\" &\n\t\"1516 (BC_2, IO_AJ37, output3, X, 1515, 1, Z),\" & --  PAD255\n\t\"1517 (BC_2, IO_AJ37, input, X),\" & --  PAD255\n\t\"1518 (BC_2, *, controlr, 1),\" &\n\t\"1519 (BC_2, IO_AJ36, output3, X, 1518, 1, Z),\" & --  PAD254\n\t\"1520 (BC_2, IO_AJ36, input, X),\" & --  PAD254\n\t\"1521 (BC_2, *, controlr, 1),\" &\n\t\"1522 (BC_2, IO_AN36, output3, X, 1521, 1, Z),\" & --  PAD253\n\t\"1523 (BC_2, IO_AN36, input, X),\" & --  PAD253\n\t\"1524 (BC_2, *, controlr, 1),\" &\n\t\"1525 (BC_2, IO_AM36, output3, X, 1524, 1, Z),\" & --  PAD252\n\t\"1526 (BC_2, IO_AM36, input, X),\" & --  PAD252\n\t\"1527 (BC_2, *, controlr, 1),\" &\n\t\"1528 (BC_2, IO_AH35, output3, X, 1527, 1, Z),\" & --  PAD251\n\t\"1529 (BC_2, IO_AH35, input, X),\" & --  PAD251\n\t\"1530 (BC_2, *, controlr, 1),\" &\n\t\"1531 (BC_2, IO_AU37, output3, X, 1530, 1, Z),\" & --  PAD250\n\t\"1532 (BC_2, IO_AU37, input, X),\" & --  PAD250\n\t\"1533 (BC_2, *, controlr, 1),\" &\n\t\"1534 (BC_2, IO_AW42, output3, X, 1533, 1, Z),\" & --  PAD249\n\t\"1535 (BC_2, IO_AW42, input, X),\" & --  PAD249\n\t\"1536 (BC_2, *, controlr, 1),\" &\n\t\"1537 (BC_2, IO_AW41, output3, X, 1536, 1, Z),\" & --  PAD248\n\t\"1538 (BC_2, IO_AW41, input, X),\" & --  PAD248\n\t\"1539 (BC_2, *, controlr, 1),\" &\n\t\"1540 (BC_2, IO_BB41, output3, X, 1539, 1, Z),\" & --  PAD247\n\t\"1541 (BC_2, IO_BB41, input, X),\" & --  PAD247\n\t\"1542 (BC_2, *, controlr, 1),\" &\n\t\"1543 (BC_2, IO_BA41, output3, X, 1542, 1, Z),\" & --  PAD246\n\t\"1544 (BC_2, IO_BA41, input, X),\" & --  PAD246\n\t\"1545 (BC_2, *, controlr, 1),\" &\n\t\"1546 (BC_2, IO_AV41, output3, X, 1545, 1, Z),\" & --  PAD245\n\t\"1547 (BC_2, IO_AV41, input, X),\" & --  PAD245\n\t\"1548 (BC_2, *, controlr, 1),\" &\n\t\"1549 (BC_2, IO_AU41, output3, X, 1548, 1, Z),\" & --  PAD244\n\t\"1550 (BC_2, IO_AU41, input, X),\" & --  PAD244\n\t\"1551 (BC_2, *, controlr, 1),\" &\n\t\"1552 (BC_2, IO_BA42, output3, X, 1551, 1, Z),\" & --  PAD243\n\t\"1553 (BC_2, IO_BA42, input, X),\" & --  PAD243\n\t\"1554 (BC_2, *, controlr, 1),\" &\n\t\"1555 (BC_2, IO_AY42, output3, X, 1554, 1, Z),\" & --  PAD242\n\t\"1556 (BC_2, IO_AY42, input, X),\" & --  PAD242\n\t\"1557 (BC_2, *, controlr, 1),\" &\n\t\"1558 (BC_2, IO_AU42, output3, X, 1557, 1, Z),\" & --  PAD241\n\t\"1559 (BC_2, IO_AU42, input, X),\" & --  PAD241\n\t\"1560 (BC_2, *, controlr, 1),\" &\n\t\"1561 (BC_2, IO_AT41, output3, X, 1560, 1, Z),\" & --  PAD240\n\t\"1562 (BC_2, IO_AT41, input, X),\" & --  PAD240\n\t\"1563 (BC_2, *, controlr, 1),\" &\n\t\"1564 (BC_2, IO_BA40, output3, X, 1563, 1, Z),\" & --  PAD239\n\t\"1565 (BC_2, IO_BA40, input, X),\" & --  PAD239\n\t\"1566 (BC_2, *, controlr, 1),\" &\n\t\"1567 (BC_2, IO_BA39, output3, X, 1566, 1, Z),\" & --  PAD238\n\t\"1568 (BC_2, IO_BA39, input, X),\" & --  PAD238\n\t\"1569 (BC_2, *, controlr, 1),\" &\n\t\"1570 (BC_2, IO_BB39, output3, X, 1569, 1, Z),\" & --  PAD237\n\t\"1571 (BC_2, IO_BB39, input, X),\" & --  PAD237\n\t\"1572 (BC_2, *, controlr, 1),\" &\n\t\"1573 (BC_2, IO_BB38, output3, X, 1572, 1, Z),\" & --  PAD236\n\t\"1574 (BC_2, IO_BB38, input, X),\" & --  PAD236\n\t\"1575 (BC_2, *, controlr, 1),\" &\n\t\"1576 (BC_2, IO_AY38, output3, X, 1575, 1, Z),\" & --  PAD235\n\t\"1577 (BC_2, IO_AY38, input, X),\" & --  PAD235\n\t\"1578 (BC_2, *, controlr, 1),\" &\n\t\"1579 (BC_2, IO_AW38, output3, X, 1578, 1, Z),\" & --  PAD234\n\t\"1580 (BC_2, IO_AW38, input, X),\" & --  PAD234\n\t\"1581 (BC_2, *, controlr, 1),\" &\n\t\"1582 (BC_2, IO_BB37, output3, X, 1581, 1, Z),\" & --  PAD233\n\t\"1583 (BC_2, IO_BB37, input, X),\" & --  PAD233\n\t\"1584 (BC_2, *, controlr, 1),\" &\n\t\"1585 (BC_2, IO_BA37, output3, X, 1584, 1, Z),\" & --  PAD232\n\t\"1586 (BC_2, IO_BA37, input, X),\" & --  PAD232\n\t\"1587 (BC_2, *, controlr, 1),\" &\n\t\"1588 (BC_2, IO_AY37, output3, X, 1587, 1, Z),\" & --  PAD231\n\t\"1589 (BC_2, IO_AY37, input, X),\" & --  PAD231\n\t\"1590 (BC_2, *, controlr, 1),\" &\n\t\"1591 (BC_2, IO_AW37, output3, X, 1590, 1, Z),\" & --  PAD230\n\t\"1592 (BC_2, IO_AW37, input, X),\" & --  PAD230\n\t\"1593 (BC_2, *, controlr, 1),\" &\n\t\"1594 (BC_2, IO_AY40, output3, X, 1593, 1, Z),\" & --  PAD229\n\t\"1595 (BC_2, IO_AY40, input, X),\" & --  PAD229\n\t\"1596 (BC_2, *, controlr, 1),\" &\n\t\"1597 (BC_2, IO_AY39, output3, X, 1596, 1, Z),\" & --  PAD228\n\t\"1598 (BC_2, IO_AY39, input, X),\" & --  PAD228\n\t\"1599 (BC_2, *, controlr, 1),\" &\n\t\"1600 (BC_2, IO_AW40, output3, X, 1599, 1, Z),\" & --  PAD227\n\t\"1601 (BC_2, IO_AW40, input, X),\" & --  PAD227\n\t\"1602 (BC_2, *, controlr, 1),\" &\n\t\"1603 (BC_2, IO_AV40, output3, X, 1602, 1, Z),\" & --  PAD226\n\t\"1604 (BC_2, IO_AV40, input, X),\" & --  PAD226\n\t\"1605 (BC_2, *, controlr, 1),\" &\n\t\"1606 (BC_2, IO_AV38, output3, X, 1605, 1, Z),\" & --  PAD225\n\t\"1607 (BC_2, IO_AV38, input, X),\" & --  PAD225\n\t\"1608 (BC_2, *, controlr, 1),\" &\n\t\"1609 (BC_2, IO_AU38, output3, X, 1608, 1, Z),\" & --  PAD224\n\t\"1610 (BC_2, IO_AU38, input, X),\" & --  PAD224\n\t\"1611 (BC_2, *, controlr, 1),\" &\n\t\"1612 (BC_2, IO_AV39, output3, X, 1611, 1, Z),\" & --  PAD223\n\t\"1613 (BC_2, IO_AV39, input, X),\" & --  PAD223\n\t\"1614 (BC_2, *, controlr, 1),\" &\n\t\"1615 (BC_2, IO_AU39, output3, X, 1614, 1, Z),\" & --  PAD222\n\t\"1616 (BC_2, IO_AU39, input, X),\" & --  PAD222\n\t\"1617 (BC_2, *, controlr, 1),\" &\n\t\"1618 (BC_2, IO_AT42, output3, X, 1617, 1, Z),\" & --  PAD221\n\t\"1619 (BC_2, IO_AT42, input, X),\" & --  PAD221\n\t\"1620 (BC_2, *, controlr, 1),\" &\n\t\"1621 (BC_2, IO_AR42, output3, X, 1620, 1, Z),\" & --  PAD220\n\t\"1622 (BC_2, IO_AR42, input, X),\" & --  PAD220\n\t\"1623 (BC_2, *, controlr, 1),\" &\n\t\"1624 (BC_2, IO_AT40, output3, X, 1623, 1, Z),\" & --  PAD219\n\t\"1625 (BC_2, IO_AT40, input, X),\" & --  PAD219\n\t\"1626 (BC_2, *, controlr, 1),\" &\n\t\"1627 (BC_2, IO_AT39, output3, X, 1626, 1, Z),\" & --  PAD218\n\t\"1628 (BC_2, IO_AT39, input, X),\" & --  PAD218\n\t\"1629 (BC_2, *, controlr, 1),\" &\n\t\"1630 (BC_2, IO_AP42, output3, X, 1629, 1, Z),\" & --  PAD217\n\t\"1631 (BC_2, IO_AP42, input, X),\" & --  PAD217\n\t\"1632 (BC_2, *, controlr, 1),\" &\n\t\"1633 (BC_2, IO_AP41, output3, X, 1632, 1, Z),\" & --  PAD216\n\t\"1634 (BC_2, IO_AP41, input, X),\" & --  PAD216\n\t\"1635 (BC_2, *, controlr, 1),\" &\n\t\"1636 (BC_2, IO_AR40, output3, X, 1635, 1, Z),\" & --  PAD215\n\t\"1637 (BC_2, IO_AR40, input, X),\" & --  PAD215\n\t\"1638 (BC_2, *, controlr, 1),\" &\n\t\"1639 (BC_2, IO_AP40, output3, X, 1638, 1, Z),\" & --  PAD214\n\t\"1640 (BC_2, IO_AP40, input, X),\" & --  PAD214\n\t\"1641 (BC_2, *, controlr, 1),\" &\n\t\"1642 (BC_2, IO_AN39, output3, X, 1641, 1, Z),\" & --  PAD213\n\t\"1643 (BC_2, IO_AN39, input, X),\" & --  PAD213\n\t\"1644 (BC_2, *, controlr, 1),\" &\n\t\"1645 (BC_2, IO_AM39, output3, X, 1644, 1, Z),\" & --  PAD212\n\t\"1646 (BC_2, IO_AM39, input, X),\" & --  PAD212\n\t\"1647 (BC_2, *, controlr, 1),\" &\n\t\"1648 (BC_2, IO_AT37, output3, X, 1647, 1, Z),\" & --  PAD211\n\t\"1649 (BC_2, IO_AT37, input, X),\" & --  PAD211\n\t\"1650 (BC_2, *, controlr, 1),\" &\n\t\"1651 (BC_2, IO_AR37, output3, X, 1650, 1, Z),\" & --  PAD210\n\t\"1652 (BC_2, IO_AR37, input, X),\" & --  PAD210\n\t\"1653 (BC_2, *, controlr, 1),\" &\n\t\"1654 (BC_2, IO_AN41, output3, X, 1653, 1, Z),\" & --  PAD209\n\t\"1655 (BC_2, IO_AN41, input, X),\" & --  PAD209\n\t\"1656 (BC_2, *, controlr, 1),\" &\n\t\"1657 (BC_2, IO_AN40, output3, X, 1656, 1, Z),\" & --  PAD208\n\t\"1658 (BC_2, IO_AN40, input, X),\" & --  PAD208\n\t\"1659 (BC_2, *, controlr, 1),\" &\n\t\"1660 (BC_2, IO_AR39, output3, X, 1659, 1, Z),\" & --  PAD207\n\t\"1661 (BC_2, IO_AR39, input, X),\" & --  PAD207\n\t\"1662 (BC_2, *, controlr, 1),\" &\n\t\"1663 (BC_2, IO_AR38, output3, X, 1662, 1, Z),\" & --  PAD206\n\t\"1664 (BC_2, IO_AR38, input, X),\" & --  PAD206\n\t\"1665 (BC_2, *, controlr, 1),\" &\n\t\"1666 (BC_2, IO_AM42, output3, X, 1665, 1, Z),\" & --  PAD205\n\t\"1667 (BC_2, IO_AM42, input, X),\" & --  PAD205\n\t\"1668 (BC_2, *, controlr, 1),\" &\n\t\"1669 (BC_2, IO_AM41, output3, X, 1668, 1, Z),\" & --  PAD204\n\t\"1670 (BC_2, IO_AM41, input, X),\" & --  PAD204\n\t\"1671 (BC_2, *, controlr, 1),\" &\n\t\"1672 (BC_2, IO_AP38, output3, X, 1671, 1, Z),\" & --  PAD203\n\t\"1673 (BC_2, IO_AP38, input, X),\" & --  PAD203\n\t\"1674 (BC_2, *, controlr, 1),\" &\n\t\"1675 (BC_2, IO_AN38, output3, X, 1674, 1, Z),\" & --  PAD202\n\t\"1676 (BC_2, IO_AN38, input, X),\" & --  PAD202\n\t\"1677 (BC_2, *, controlr, 1),\" &\n\t\"1678 (BC_2, IO_AM38, output3, X, 1677, 1, Z),\" & --  PAD201\n\t\"1679 (BC_2, IO_AM38, input, X),\" & --  PAD201\n\t\"1680 (BC_2, *, controlr, 1),\" &\n\t\"1681 (BC_2, IO_AB34, output3, X, 1680, 1, Z),\" & --  PAD200\n\t\"1682 (BC_2, IO_AB34, input, X),\" & --  PAD200\n\t\"1683 (BC_2, *, controlr, 1),\" &\n\t\"1684 (BC_2, IO_AC29, output3, X, 1683, 1, Z),\" & --  PAD199\n\t\"1685 (BC_2, IO_AC29, input, X),\" & --  PAD199\n\t\"1686 (BC_2, *, controlr, 1),\" &\n\t\"1687 (BC_2, IO_AB29, output3, X, 1686, 1, Z),\" & --  PAD198\n\t\"1688 (BC_2, IO_AB29, input, X),\" & --  PAD198\n\t\"1689 (BC_2, *, controlr, 1),\" &\n\t\"1690 (BC_2, IO_AA30, output3, X, 1689, 1, Z),\" & --  PAD197\n\t\"1691 (BC_2, IO_AA30, input, X),\" & --  PAD197\n\t\"1692 (BC_2, *, controlr, 1),\" &\n\t\"1693 (BC_2, IO_AA29, output3, X, 1692, 1, Z),\" & --  PAD196\n\t\"1694 (BC_2, IO_AA29, input, X),\" & --  PAD196\n\t\"1695 (BC_2, *, controlr, 1),\" &\n\t\"1696 (BC_2, IO_AD30, output3, X, 1695, 1, Z),\" & --  PAD195\n\t\"1697 (BC_2, IO_AD30, input, X),\" & --  PAD195\n\t\"1698 (BC_2, *, controlr, 1),\" &\n\t\"1699 (BC_2, IO_AC30, output3, X, 1698, 1, Z),\" & --  PAD194\n\t\"1700 (BC_2, IO_AC30, input, X),\" & --  PAD194\n\t\"1701 (BC_2, *, controlr, 1),\" &\n\t\"1702 (BC_2, IO_AA32, output3, X, 1701, 1, Z),\" & --  PAD193\n\t\"1703 (BC_2, IO_AA32, input, X),\" & --  PAD193\n\t\"1704 (BC_2, *, controlr, 1),\" &\n\t\"1705 (BC_2, IO_AA31, output3, X, 1704, 1, Z),\" & --  PAD192\n\t\"1706 (BC_2, IO_AA31, input, X),\" & --  PAD192\n\t\"1707 (BC_2, *, controlr, 1),\" &\n\t\"1708 (BC_2, IO_AD31, output3, X, 1707, 1, Z),\" & --  PAD191\n\t\"1709 (BC_2, IO_AD31, input, X),\" & --  PAD191\n\t\"1710 (BC_2, *, controlr, 1),\" &\n\t\"1711 (BC_2, IO_AC31, output3, X, 1710, 1, Z),\" & --  PAD190\n\t\"1712 (BC_2, IO_AC31, input, X),\" & --  PAD190\n\t\"1713 (BC_2, *, controlr, 1),\" &\n\t\"1714 (BC_2, IO_Y33, output3, X, 1713, 1, Z),\" & --  PAD189\n\t\"1715 (BC_2, IO_Y33, input, X),\" & --  PAD189\n\t\"1716 (BC_2, *, controlr, 1),\" &\n\t\"1717 (BC_2, IO_Y32, output3, X, 1716, 1, Z),\" & --  PAD188\n\t\"1718 (BC_2, IO_Y32, input, X),\" & --  PAD188\n\t\"1719 (BC_2, *, controlr, 1),\" &\n\t\"1720 (BC_2, IO_AE30, output3, X, 1719, 1, Z),\" & --  PAD187\n\t\"1721 (BC_2, IO_AE30, input, X),\" & --  PAD187\n\t\"1722 (BC_2, *, controlr, 1),\" &\n\t\"1723 (BC_2, IO_AE29, output3, X, 1722, 1, Z),\" & --  PAD186\n\t\"1724 (BC_2, IO_AE29, input, X),\" & --  PAD186\n\t\"1725 (BC_2, *, controlr, 1),\" &\n\t\"1726 (BC_2, IO_AE35, output3, X, 1725, 1, Z),\" & --  PAD185\n\t\"1727 (BC_2, IO_AE35, input, X),\" & --  PAD185\n\t\"1728 (BC_2, *, controlr, 1),\" &\n\t\"1729 (BC_2, IO_AE34, output3, X, 1728, 1, Z),\" & --  PAD184\n\t\"1730 (BC_2, IO_AE34, input, X),\" & --  PAD184\n\t\"1731 (BC_2, *, controlr, 1),\" &\n\t\"1732 (BC_2, IO_AF32, output3, X, 1731, 1, Z),\" & --  PAD183\n\t\"1733 (BC_2, IO_AF32, input, X),\" & --  PAD183\n\t\"1734 (BC_2, *, controlr, 1),\" &\n\t\"1735 (BC_2, IO_AF31, output3, X, 1734, 1, Z),\" & --  PAD182\n\t\"1736 (BC_2, IO_AF31, input, X),\" & --  PAD182\n\t\"1737 (BC_2, *, controlr, 1),\" &\n\t\"1738 (BC_2, IO_AE33, output3, X, 1737, 1, Z),\" & --  PAD181\n\t\"1739 (BC_2, IO_AE33, input, X),\" & --  PAD181\n\t\"1740 (BC_2, *, controlr, 1),\" &\n\t\"1741 (BC_2, IO_AE32, output3, X, 1740, 1, Z),\" & --  PAD180\n\t\"1742 (BC_2, IO_AE32, input, X),\" & --  PAD180\n\t\"1743 (BC_2, *, controlr, 1),\" &\n\t\"1744 (BC_2, IO_AD35, output3, X, 1743, 1, Z),\" & --  PAD179\n\t\"1745 (BC_2, IO_AD35, input, X),\" & --  PAD179\n\t\"1746 (BC_2, *, controlr, 1),\" &\n\t\"1747 (BC_2, IO_AC34, output3, X, 1746, 1, Z),\" & --  PAD178\n\t\"1748 (BC_2, IO_AC34, input, X),\" & --  PAD178\n\t\"1749 (BC_2, *, controlr, 1),\" &\n\t\"1750 (BC_2, IO_AD33, output3, X, 1749, 1, Z),\" & --  PAD177\n\t\"1751 (BC_2, IO_AD33, input, X),\" & --  PAD177\n\t\"1752 (BC_2, *, controlr, 1),\" &\n\t\"1753 (BC_2, IO_AD32, output3, X, 1752, 1, Z),\" & --  PAD176\n\t\"1754 (BC_2, IO_AD32, input, X),\" & --  PAD176\n\t\"1755 (BC_2, *, controlr, 1),\" &\n\t\"1756 (BC_2, IO_AC33, output3, X, 1755, 1, Z),\" & --  PAD175\n\t\"1757 (BC_2, IO_AC33, input, X),\" & --  PAD175\n\t\"1758 (BC_2, *, controlr, 1),\" &\n\t\"1759 (BC_2, IO_AB33, output3, X, 1758, 1, Z),\" & --  PAD174\n\t\"1760 (BC_2, IO_AB33, input, X),\" & --  PAD174\n\t\"1761 (BC_2, *, controlr, 1),\" &\n\t\"1762 (BC_2, IO_AB32, output3, X, 1761, 1, Z),\" & --  PAD173\n\t\"1763 (BC_2, IO_AB32, input, X),\" & --  PAD173\n\t\"1764 (BC_2, *, controlr, 1),\" &\n\t\"1765 (BC_2, IO_AB31, output3, X, 1764, 1, Z),\" & --  PAD172\n\t\"1766 (BC_2, IO_AB31, input, X),\" & --  PAD172\n\t\"1767 (BC_2, *, controlr, 1),\" &\n\t\"1768 (BC_2, IO_AA35, output3, X, 1767, 1, Z),\" & --  PAD171\n\t\"1769 (BC_2, IO_AA35, input, X),\" & --  PAD171\n\t\"1770 (BC_2, *, controlr, 1),\" &\n\t\"1771 (BC_2, IO_AA34, output3, X, 1770, 1, Z),\" & --  PAD170\n\t\"1772 (BC_2, IO_AA34, input, X),\" & --  PAD170\n\t\"1773 (BC_2, *, controlr, 1),\" &\n\t\"1774 (BC_2, IO_AB37, output3, X, 1773, 1, Z),\" & --  PAD169\n\t\"1775 (BC_2, IO_AB37, input, X),\" & --  PAD169\n\t\"1776 (BC_2, *, controlr, 1),\" &\n\t\"1777 (BC_2, IO_AB36, output3, X, 1776, 1, Z),\" & --  PAD168\n\t\"1778 (BC_2, IO_AB36, input, X),\" & --  PAD168\n\t\"1779 (BC_2, *, controlr, 1),\" &\n\t\"1780 (BC_2, IO_AA36, output3, X, 1779, 1, Z),\" & --  PAD167\n\t\"1781 (BC_2, IO_AA36, input, X),\" & --  PAD167\n\t\"1782 (BC_2, *, controlr, 1),\" &\n\t\"1783 (BC_2, IO_Y35, output3, X, 1782, 1, Z),\" & --  PAD166\n\t\"1784 (BC_2, IO_Y35, input, X),\" & --  PAD166\n\t\"1785 (BC_2, *, controlr, 1),\" &\n\t\"1786 (BC_2, IO_AA37, output3, X, 1785, 1, Z),\" & --  PAD165\n\t\"1787 (BC_2, IO_AA37, input, X),\" & --  PAD165\n\t\"1788 (BC_2, *, controlr, 1),\" &\n\t\"1789 (BC_2, IO_Y37, output3, X, 1788, 1, Z),\" & --  PAD164\n\t\"1790 (BC_2, IO_Y37, input, X),\" & --  PAD164\n\t\"1791 (BC_2, *, controlr, 1),\" &\n\t\"1792 (BC_2, IO_AH36, output3, X, 1791, 1, Z),\" & --  PAD163\n\t\"1793 (BC_2, IO_AH36, input, X),\" & --  PAD163\n\t\"1794 (BC_2, *, controlr, 1),\" &\n\t\"1795 (BC_2, IO_AG36, output3, X, 1794, 1, Z),\" & --  PAD162\n\t\"1796 (BC_2, IO_AG36, input, X),\" & --  PAD162\n\t\"1797 (BC_2, *, controlr, 1),\" &\n\t\"1798 (BC_2, IO_AC36, output3, X, 1797, 1, Z),\" & --  PAD161\n\t\"1799 (BC_2, IO_AC36, input, X),\" & --  PAD161\n\t\"1800 (BC_2, *, controlr, 1),\" &\n\t\"1801 (BC_2, IO_AC35, output3, X, 1800, 1, Z),\" & --  PAD160\n\t\"1802 (BC_2, IO_AC35, input, X),\" & --  PAD160\n\t\"1803 (BC_2, *, controlr, 1),\" &\n\t\"1804 (BC_2, IO_AD37, output3, X, 1803, 1, Z),\" & --  PAD159\n\t\"1805 (BC_2, IO_AD37, input, X),\" & --  PAD159\n\t\"1806 (BC_2, *, controlr, 1),\" &\n\t\"1807 (BC_2, IO_AD36, output3, X, 1806, 1, Z),\" & --  PAD158\n\t\"1808 (BC_2, IO_AD36, input, X),\" & --  PAD158\n\t\"1809 (BC_2, *, controlr, 1),\" &\n\t\"1810 (BC_2, IO_AG34, output3, X, 1809, 1, Z),\" & --  PAD157\n\t\"1811 (BC_2, IO_AG34, input, X),\" & --  PAD157\n\t\"1812 (BC_2, *, controlr, 1),\" &\n\t\"1813 (BC_2, IO_AF34, output3, X, 1812, 1, Z),\" & --  PAD156\n\t\"1814 (BC_2, IO_AF34, input, X),\" & --  PAD156\n\t\"1815 (BC_2, *, controlr, 1),\" &\n\t\"1816 (BC_2, IO_AF37, output3, X, 1815, 1, Z),\" & --  PAD155\n\t\"1817 (BC_2, IO_AF37, input, X),\" & --  PAD155\n\t\"1818 (BC_2, *, controlr, 1),\" &\n\t\"1819 (BC_2, IO_AE37, output3, X, 1818, 1, Z),\" & --  PAD154\n\t\"1820 (BC_2, IO_AE37, input, X),\" & --  PAD154\n\t\"1821 (BC_2, *, controlr, 1),\" &\n\t\"1822 (BC_2, IO_AF36, output3, X, 1821, 1, Z),\" & --  PAD153\n\t\"1823 (BC_2, IO_AF36, input, X),\" & --  PAD153\n\t\"1824 (BC_2, *, controlr, 1),\" &\n\t\"1825 (BC_2, IO_AF35, output3, X, 1824, 1, Z),\" & --  PAD152\n\t\"1826 (BC_2, IO_AF35, input, X),\" & --  PAD152\n\t\"1827 (BC_2, *, controlr, 1),\" &\n\t\"1828 (BC_2, IO_Y34, output3, X, 1827, 1, Z),\" & --  PAD151\n\t\"1829 (BC_2, IO_Y34, input, X),\" & --  PAD151\n\t\"1830 (BC_2, *, controlr, 1),\" &\n\t\"1831 (BC_2, IO_AG37, output3, X, 1830, 1, Z),\" & --  PAD150\n\t\"1832 (BC_2, IO_AG37, input, X),\" & --  PAD150\n\t\"1833 (BC_2, *, controlr, 1),\" &\n\t\"1834 (BC_2, IO_AK42, output3, X, 1833, 1, Z),\" & --  PAD149\n\t\"1835 (BC_2, IO_AK42, input, X),\" & --  PAD149\n\t\"1836 (BC_2, *, controlr, 1),\" &\n\t\"1837 (BC_2, IO_AJ42, output3, X, 1836, 1, Z),\" & --  PAD148\n\t\"1838 (BC_2, IO_AJ42, input, X),\" & --  PAD148\n\t\"1839 (BC_2, *, controlr, 1),\" &\n\t\"1840 (BC_2, IO_AL39, output3, X, 1839, 1, Z),\" & --  PAD147\n\t\"1841 (BC_2, IO_AL39, input, X),\" & --  PAD147\n\t\"1842 (BC_2, *, controlr, 1),\" &\n\t\"1843 (BC_2, IO_AK39, output3, X, 1842, 1, Z),\" & --  PAD146\n\t\"1844 (BC_2, IO_AK39, input, X),\" & --  PAD146\n\t\"1845 (BC_2, *, controlr, 1),\" &\n\t\"1846 (BC_2, IO_AJ41, output3, X, 1845, 1, Z),\" & --  PAD145\n\t\"1847 (BC_2, IO_AJ41, input, X),\" & --  PAD145\n\t\"1848 (BC_2, *, controlr, 1),\" &\n\t\"1849 (BC_2, IO_AJ40, output3, X, 1848, 1, Z),\" & --  PAD144\n\t\"1850 (BC_2, IO_AJ40, input, X),\" & --  PAD144\n\t\"1851 (BC_2, *, controlr, 1),\" &\n\t\"1852 (BC_2, IO_AL42, output3, X, 1851, 1, Z),\" & --  PAD143\n\t\"1853 (BC_2, IO_AL42, input, X),\" & --  PAD143\n\t\"1854 (BC_2, *, controlr, 1),\" &\n\t\"1855 (BC_2, IO_AL41, output3, X, 1854, 1, Z),\" & --  PAD142\n\t\"1856 (BC_2, IO_AL41, input, X),\" & --  PAD142\n\t\"1857 (BC_2, *, controlr, 1),\" &\n\t\"1858 (BC_2, IO_AH41, output3, X, 1857, 1, Z),\" & --  PAD141\n\t\"1859 (BC_2, IO_AH41, input, X),\" & --  PAD141\n\t\"1860 (BC_2, *, controlr, 1),\" &\n\t\"1861 (BC_2, IO_AH40, output3, X, 1860, 1, Z),\" & --  PAD140\n\t\"1862 (BC_2, IO_AH40, input, X),\" & --  PAD140\n\t\"1863 (BC_2, *, controlr, 1),\" &\n\t\"1864 (BC_2, IO_AL40, output3, X, 1863, 1, Z),\" & --  PAD139\n\t\"1865 (BC_2, IO_AL40, input, X),\" & --  PAD139\n\t\"1866 (BC_2, *, controlr, 1),\" &\n\t\"1867 (BC_2, IO_AK40, output3, X, 1866, 1, Z),\" & --  PAD138\n\t\"1868 (BC_2, IO_AK40, input, X),\" & --  PAD138\n\t\"1869 (BC_2, *, controlr, 1),\" &\n\t\"1870 (BC_2, IO_AK38, output3, X, 1869, 1, Z),\" & --  PAD137\n\t\"1871 (BC_2, IO_AK38, input, X),\" & --  PAD137\n\t\"1872 (BC_2, *, controlr, 1),\" &\n\t\"1873 (BC_2, IO_AJ38, output3, X, 1872, 1, Z),\" & --  PAD136\n\t\"1874 (BC_2, IO_AJ38, input, X),\" & --  PAD136\n\t\"1875 (BC_2, *, controlr, 1),\" &\n\t\"1876 (BC_2, IO_AH38, output3, X, 1875, 1, Z),\" & --  PAD135\n\t\"1877 (BC_2, IO_AH38, input, X),\" & --  PAD135\n\t\"1878 (BC_2, *, controlr, 1),\" &\n\t\"1879 (BC_2, IO_AG38, output3, X, 1878, 1, Z),\" & --  PAD134\n\t\"1880 (BC_2, IO_AG38, input, X),\" & --  PAD134\n\t\"1881 (BC_2, *, controlr, 1),\" &\n\t\"1882 (BC_2, IO_AG42, output3, X, 1881, 1, Z),\" & --  PAD133\n\t\"1883 (BC_2, IO_AG42, input, X),\" & --  PAD133\n\t\"1884 (BC_2, *, controlr, 1),\" &\n\t\"1885 (BC_2, IO_AF42, output3, X, 1884, 1, Z),\" & --  PAD132\n\t\"1886 (BC_2, IO_AF42, input, X),\" & --  PAD132\n\t\"1887 (BC_2, *, controlr, 1),\" &\n\t\"1888 (BC_2, IO_AH39, output3, X, 1887, 1, Z),\" & --  PAD131\n\t\"1889 (BC_2, IO_AH39, input, X),\" & --  PAD131\n\t\"1890 (BC_2, *, controlr, 1),\" &\n\t\"1891 (BC_2, IO_AG39, output3, X, 1890, 1, Z),\" & --  PAD130\n\t\"1892 (BC_2, IO_AG39, input, X),\" & --  PAD130\n\t\"1893 (BC_2, *, controlr, 1),\" &\n\t\"1894 (BC_2, IO_AG41, output3, X, 1893, 1, Z),\" & --  PAD129\n\t\"1895 (BC_2, IO_AG41, input, X),\" & --  PAD129\n\t\"1896 (BC_2, *, controlr, 1),\" &\n\t\"1897 (BC_2, IO_AF41, output3, X, 1896, 1, Z),\" & --  PAD128\n\t\"1898 (BC_2, IO_AF41, input, X),\" & --  PAD128\n\t\"1899 (BC_2, *, controlr, 1),\" &\n\t\"1900 (BC_2, IO_AF40, output3, X, 1899, 1, Z),\" & --  PAD127\n\t\"1901 (BC_2, IO_AF40, input, X),\" & --  PAD127\n\t\"1902 (BC_2, *, controlr, 1),\" &\n\t\"1903 (BC_2, IO_AF39, output3, X, 1902, 1, Z),\" & --  PAD126\n\t\"1904 (BC_2, IO_AF39, input, X),\" & --  PAD126\n\t\"1905 (BC_2, *, controlr, 1),\" &\n\t\"1906 (BC_2, IO_AD41, output3, X, 1905, 1, Z),\" & --  PAD125\n\t\"1907 (BC_2, IO_AD41, input, X),\" & --  PAD125\n\t\"1908 (BC_2, *, controlr, 1),\" &\n\t\"1909 (BC_2, IO_AD40, output3, X, 1908, 1, Z),\" & --  PAD124\n\t\"1910 (BC_2, IO_AD40, input, X),\" & --  PAD124\n\t\"1911 (BC_2, *, controlr, 1),\" &\n\t\"1912 (BC_2, IO_AE40, output3, X, 1911, 1, Z),\" & --  PAD123\n\t\"1913 (BC_2, IO_AE40, input, X),\" & --  PAD123\n\t\"1914 (BC_2, *, controlr, 1),\" &\n\t\"1915 (BC_2, IO_AE39, output3, X, 1914, 1, Z),\" & --  PAD122\n\t\"1916 (BC_2, IO_AE39, input, X),\" & --  PAD122\n\t\"1917 (BC_2, *, controlr, 1),\" &\n\t\"1918 (BC_2, IO_AC41, output3, X, 1917, 1, Z),\" & --  PAD121\n\t\"1919 (BC_2, IO_AC41, input, X),\" & --  PAD121\n\t\"1920 (BC_2, *, controlr, 1),\" &\n\t\"1921 (BC_2, IO_AC40, output3, X, 1920, 1, Z),\" & --  PAD120\n\t\"1922 (BC_2, IO_AC40, input, X),\" & --  PAD120\n\t\"1923 (BC_2, *, controlr, 1),\" &\n\t\"1924 (BC_2, IO_AE38, output3, X, 1923, 1, Z),\" & --  PAD119\n\t\"1925 (BC_2, IO_AE38, input, X),\" & --  PAD119\n\t\"1926 (BC_2, *, controlr, 1),\" &\n\t\"1927 (BC_2, IO_AD38, output3, X, 1926, 1, Z),\" & --  PAD118\n\t\"1928 (BC_2, IO_AD38, input, X),\" & --  PAD118\n\t\"1929 (BC_2, *, controlr, 1),\" &\n\t\"1930 (BC_2, IO_AE42, output3, X, 1929, 1, Z),\" & --  PAD117\n\t\"1931 (BC_2, IO_AE42, input, X),\" & --  PAD117\n\t\"1932 (BC_2, *, controlr, 1),\" &\n\t\"1933 (BC_2, IO_AD42, output3, X, 1932, 1, Z),\" & --  PAD116\n\t\"1934 (BC_2, IO_AD42, input, X),\" & --  PAD116\n\t\"1935 (BC_2, *, controlr, 1),\" &\n\t\"1936 (BC_2, IO_AC39, output3, X, 1935, 1, Z),\" & --  PAD115\n\t\"1937 (BC_2, IO_AC39, input, X),\" & --  PAD115\n\t\"1938 (BC_2, *, controlr, 1),\" &\n\t\"1939 (BC_2, IO_AC38, output3, X, 1938, 1, Z),\" & --  PAD114\n\t\"1940 (BC_2, IO_AC38, input, X),\" & --  PAD114\n\t\"1941 (BC_2, *, controlr, 1),\" &\n\t\"1942 (BC_2, IO_AA41, output3, X, 1941, 1, Z),\" & --  PAD113\n\t\"1943 (BC_2, IO_AA41, input, X),\" & --  PAD113\n\t\"1944 (BC_2, *, controlr, 1),\" &\n\t\"1945 (BC_2, IO_AA40, output3, X, 1944, 1, Z),\" & --  PAD112\n\t\"1946 (BC_2, IO_AA40, input, X),\" & --  PAD112\n\t\"1947 (BC_2, *, controlr, 1),\" &\n\t\"1948 (BC_2, IO_AB39, output3, X, 1947, 1, Z),\" & --  PAD111\n\t\"1949 (BC_2, IO_AB39, input, X),\" & --  PAD111\n\t\"1950 (BC_2, *, controlr, 1),\" &\n\t\"1951 (BC_2, IO_AB38, output3, X, 1950, 1, Z),\" & --  PAD110\n\t\"1952 (BC_2, IO_AB38, input, X),\" & --  PAD110\n\t\"1953 (BC_2, *, controlr, 1),\" &\n\t\"1954 (BC_2, IO_AA42, output3, X, 1953, 1, Z),\" & --  PAD109\n\t\"1955 (BC_2, IO_AA42, input, X),\" & --  PAD109\n\t\"1956 (BC_2, *, controlr, 1),\" &\n\t\"1957 (BC_2, IO_Y42, output3, X, 1956, 1, Z),\" & --  PAD108\n\t\"1958 (BC_2, IO_Y42, input, X),\" & --  PAD108\n\t\"1959 (BC_2, *, controlr, 1),\" &\n\t\"1960 (BC_2, IO_AA39, output3, X, 1959, 1, Z),\" & --  PAD107\n\t\"1961 (BC_2, IO_AA39, input, X),\" & --  PAD107\n\t\"1962 (BC_2, *, controlr, 1),\" &\n\t\"1963 (BC_2, IO_Y39, output3, X, 1962, 1, Z),\" & --  PAD106\n\t\"1964 (BC_2, IO_Y39, input, X),\" & --  PAD106\n\t\"1965 (BC_2, *, controlr, 1),\" &\n\t\"1966 (BC_2, IO_Y40, output3, X, 1965, 1, Z),\" & --  PAD105\n\t\"1967 (BC_2, IO_Y40, input, X),\" & --  PAD105\n\t\"1968 (BC_2, *, controlr, 1),\" &\n\t\"1969 (BC_2, IO_W40, output3, X, 1968, 1, Z),\" & --  PAD104\n\t\"1970 (BC_2, IO_W40, input, X),\" & --  PAD104\n\t\"1971 (BC_2, *, controlr, 1),\" &\n\t\"1972 (BC_2, IO_AB42, output3, X, 1971, 1, Z),\" & --  PAD103\n\t\"1973 (BC_2, IO_AB42, input, X),\" & --  PAD103\n\t\"1974 (BC_2, *, controlr, 1),\" &\n\t\"1975 (BC_2, IO_AB41, output3, X, 1974, 1, Z),\" & --  PAD102\n\t\"1976 (BC_2, IO_AB41, input, X),\" & --  PAD102\n\t\"1977 (BC_2, *, controlr, 1),\" &\n\t\"1978 (BC_2, IO_Y38, output3, X, 1977, 1, Z),\" & --  PAD101\n\t\"1979 (BC_2, IO_Y38, input, X),\" & --  PAD101\n\t\"1980 (BC_2, *, controlr, 1),\" &\n\t\"1981 (BC_2, IO_W35, output3, X, 1980, 1, Z),\" & --  PAD100\n\t\"1982 (BC_2, IO_W35, input, X),\" & --  PAD100\n\t\"1983 (BC_2, *, controlr, 1),\" &\n\t\"1984 (BC_2, IO_U42, output3, X, 1983, 1, Z),\" & --  PAD99\n\t\"1985 (BC_2, IO_U42, input, X),\" & --  PAD99\n\t\"1986 (BC_2, *, controlr, 1),\" &\n\t\"1987 (BC_2, IO_V41, output3, X, 1986, 1, Z),\" & --  PAD98\n\t\"1988 (BC_2, IO_V41, input, X),\" & --  PAD98\n\t\"1989 (BC_2, *, controlr, 1),\" &\n\t\"1990 (BC_2, IO_V38, output3, X, 1989, 1, Z),\" & --  PAD97\n\t\"1991 (BC_2, IO_V38, input, X),\" & --  PAD97\n\t\"1992 (BC_2, *, controlr, 1),\" &\n\t\"1993 (BC_2, IO_W38, output3, X, 1992, 1, Z),\" & --  PAD96\n\t\"1994 (BC_2, IO_W38, input, X),\" & --  PAD96\n\t\"1995 (BC_2, *, controlr, 1),\" &\n\t\"1996 (BC_2, IO_T42, output3, X, 1995, 1, Z),\" & --  PAD95\n\t\"1997 (BC_2, IO_T42, input, X),\" & --  PAD95\n\t\"1998 (BC_2, *, controlr, 1),\" &\n\t\"1999 (BC_2, IO_U41, output3, X, 1998, 1, Z),\" & --  PAD94\n\t\"2000 (BC_2, IO_U41, input, X),\" & --  PAD94\n\t\"2001 (BC_2, *, controlr, 1),\" &\n\t\"2002 (BC_2, IO_W42, output3, X, 2001, 1, Z),\" & --  PAD93\n\t\"2003 (BC_2, IO_W42, input, X),\" & --  PAD93\n\t\"2004 (BC_2, *, controlr, 1),\" &\n\t\"2005 (BC_2, IO_W41, output3, X, 2004, 1, Z),\" & --  PAD92\n\t\"2006 (BC_2, IO_W41, input, X),\" & --  PAD92\n\t\"2007 (BC_2, *, controlr, 1),\" &\n\t\"2008 (BC_2, IO_T41, output3, X, 2007, 1, Z),\" & --  PAD91\n\t\"2009 (BC_2, IO_T41, input, X),\" & --  PAD91\n\t\"2010 (BC_2, *, controlr, 1),\" &\n\t\"2011 (BC_2, IO_T40, output3, X, 2010, 1, Z),\" & --  PAD90\n\t\"2012 (BC_2, IO_T40, input, X),\" & --  PAD90\n\t\"2013 (BC_2, *, controlr, 1),\" &\n\t\"2014 (BC_2, IO_V40, output3, X, 2013, 1, Z),\" & --  PAD89\n\t\"2015 (BC_2, IO_V40, input, X),\" & --  PAD89\n\t\"2016 (BC_2, *, controlr, 1),\" &\n\t\"2017 (BC_2, IO_V39, output3, X, 2016, 1, Z),\" & --  PAD88\n\t\"2018 (BC_2, IO_V39, input, X),\" & --  PAD88\n\t\"2019 (BC_2, *, controlr, 1),\" &\n\t\"2020 (BC_2, IO_W33, output3, X, 2019, 1, Z),\" & --  PAD87\n\t\"2021 (BC_2, IO_W33, input, X),\" & --  PAD87\n\t\"2022 (BC_2, *, controlr, 1),\" &\n\t\"2023 (BC_2, IO_W32, output3, X, 2022, 1, Z),\" & --  PAD86\n\t\"2024 (BC_2, IO_W32, input, X),\" & --  PAD86\n\t\"2025 (BC_2, *, controlr, 1),\" &\n\t\"2026 (BC_2, IO_U33, output3, X, 2025, 1, Z),\" & --  PAD85\n\t\"2027 (BC_2, IO_U33, input, X),\" & --  PAD85\n\t\"2028 (BC_2, *, controlr, 1),\" &\n\t\"2029 (BC_2, IO_U32, output3, X, 2028, 1, Z),\" & --  PAD84\n\t\"2030 (BC_2, IO_U32, input, X),\" & --  PAD84\n\t\"2031 (BC_2, *, controlr, 1),\" &\n\t\"2032 (BC_2, IO_W37, output3, X, 2031, 1, Z),\" & --  PAD83\n\t\"2033 (BC_2, IO_W37, input, X),\" & --  PAD83\n\t\"2034 (BC_2, *, controlr, 1),\" &\n\t\"2035 (BC_2, IO_W36, output3, X, 2034, 1, Z),\" & --  PAD82\n\t\"2036 (BC_2, IO_W36, input, X),\" & --  PAD82\n\t\"2037 (BC_2, *, controlr, 1),\" &\n\t\"2038 (BC_2, IO_V34, output3, X, 2037, 1, Z),\" & --  PAD81\n\t\"2039 (BC_2, IO_V34, input, X),\" & --  PAD81\n\t\"2040 (BC_2, *, controlr, 1),\" &\n\t\"2041 (BC_2, IO_V33, output3, X, 2040, 1, Z),\" & --  PAD80\n\t\"2042 (BC_2, IO_V33, input, X),\" & --  PAD80\n\t\"2043 (BC_2, *, controlr, 1),\" &\n\t\"2044 (BC_2, IO_V36, output3, X, 2043, 1, Z),\" & --  PAD79\n\t\"2045 (BC_2, IO_V36, input, X),\" & --  PAD79\n\t\"2046 (BC_2, *, controlr, 1),\" &\n\t\"2047 (BC_2, IO_V35, output3, X, 2046, 1, Z),\" & --  PAD78\n\t\"2048 (BC_2, IO_V35, input, X),\" & --  PAD78\n\t\"2049 (BC_2, *, controlr, 1),\" &\n\t\"2050 (BC_2, IO_T37, output3, X, 2049, 1, Z),\" & --  PAD77\n\t\"2051 (BC_2, IO_T37, input, X),\" & --  PAD77\n\t\"2052 (BC_2, *, controlr, 1),\" &\n\t\"2053 (BC_2, IO_U36, output3, X, 2052, 1, Z),\" & --  PAD76\n\t\"2054 (BC_2, IO_U36, input, X),\" & --  PAD76\n\t\"2055 (BC_2, *, controlr, 1),\" &\n\t\"2056 (BC_2, IO_T39, output3, X, 2055, 1, Z),\" & --  PAD75\n\t\"2057 (BC_2, IO_T39, input, X),\" & --  PAD75\n\t\"2058 (BC_2, *, controlr, 1),\" &\n\t\"2059 (BC_2, IO_U39, output3, X, 2058, 1, Z),\" & --  PAD74\n\t\"2060 (BC_2, IO_U39, input, X),\" & --  PAD74\n\t\"2061 (BC_2, *, controlr, 1),\" &\n\t\"2062 (BC_2, IO_U38, output3, X, 2061, 1, Z),\" & --  PAD73\n\t\"2063 (BC_2, IO_U38, input, X),\" & --  PAD73\n\t\"2064 (BC_2, *, controlr, 1),\" &\n\t\"2065 (BC_2, IO_U37, output3, X, 2064, 1, Z),\" & --  PAD72\n\t\"2066 (BC_2, IO_U37, input, X),\" & --  PAD72\n\t\"2067 (BC_2, *, controlr, 1),\" &\n\t\"2068 (BC_2, IO_R39, output3, X, 2067, 1, Z),\" & --  PAD71\n\t\"2069 (BC_2, IO_R39, input, X),\" & --  PAD71\n\t\"2070 (BC_2, *, controlr, 1),\" &\n\t\"2071 (BC_2, IO_R38, output3, X, 2070, 1, Z),\" & --  PAD70\n\t\"2072 (BC_2, IO_R38, input, X),\" & --  PAD70\n\t\"2073 (BC_2, *, controlr, 1),\" &\n\t\"2074 (BC_2, IO_T35, output3, X, 2073, 1, Z),\" & --  PAD69\n\t\"2075 (BC_2, IO_T35, input, X),\" & --  PAD69\n\t\"2076 (BC_2, *, controlr, 1),\" &\n\t\"2077 (BC_2, IO_U34, output3, X, 2076, 1, Z),\" & --  PAD68\n\t\"2078 (BC_2, IO_U34, input, X),\" & --  PAD68\n\t\"2079 (BC_2, *, controlr, 1),\" &\n\t\"2080 (BC_2, IO_P38, output3, X, 2079, 1, Z),\" & --  PAD67\n\t\"2081 (BC_2, IO_P38, input, X),\" & --  PAD67\n\t\"2082 (BC_2, *, controlr, 1),\" &\n\t\"2083 (BC_2, IO_P37, output3, X, 2082, 1, Z),\" & --  PAD66\n\t\"2084 (BC_2, IO_P37, input, X),\" & --  PAD66\n\t\"2085 (BC_2, *, controlr, 1),\" &\n\t\"2086 (BC_2, IO_R37, output3, X, 2085, 1, Z),\" & --  PAD65\n\t\"2087 (BC_2, IO_R37, input, X),\" & --  PAD65\n\t\"2088 (BC_2, *, controlr, 1),\" &\n\t\"2089 (BC_2, IO_T36, output3, X, 2088, 1, Z),\" & --  PAD64\n\t\"2090 (BC_2, IO_T36, input, X),\" & --  PAD64\n\t\"2091 (BC_2, *, controlr, 1),\" &\n\t\"2092 (BC_2, IO_P33, output3, X, 2091, 1, Z),\" & --  PAD63\n\t\"2093 (BC_2, IO_P33, input, X),\" & --  PAD63\n\t\"2094 (BC_2, *, controlr, 1),\" &\n\t\"2095 (BC_2, IO_P32, output3, X, 2094, 1, Z),\" & --  PAD62\n\t\"2096 (BC_2, IO_P32, input, X),\" & --  PAD62\n\t\"2097 (BC_2, *, controlr, 1),\" &\n\t\"2098 (BC_2, IO_R32, output3, X, 2097, 1, Z),\" & --  PAD61\n\t\"2099 (BC_2, IO_R32, input, X),\" & --  PAD61\n\t\"2100 (BC_2, *, controlr, 1),\" &\n\t\"2101 (BC_2, IO_T32, output3, X, 2100, 1, Z),\" & --  PAD60\n\t\"2102 (BC_2, IO_T32, input, X),\" & --  PAD60\n\t\"2103 (BC_2, *, controlr, 1),\" &\n\t\"2104 (BC_2, IO_P36, output3, X, 2103, 1, Z),\" & --  PAD59\n\t\"2105 (BC_2, IO_P36, input, X),\" & --  PAD59\n\t\"2106 (BC_2, *, controlr, 1),\" &\n\t\"2107 (BC_2, IO_P35, output3, X, 2106, 1, Z),\" & --  PAD58\n\t\"2108 (BC_2, IO_P35, input, X),\" & --  PAD58\n\t\"2109 (BC_2, *, controlr, 1),\" &\n\t\"2110 (BC_2, IO_R34, output3, X, 2109, 1, Z),\" & --  PAD57\n\t\"2111 (BC_2, IO_R34, input, X),\" & --  PAD57\n\t\"2112 (BC_2, *, controlr, 1),\" &\n\t\"2113 (BC_2, IO_R33, output3, X, 2112, 1, Z),\" & --  PAD56\n\t\"2114 (BC_2, IO_R33, input, X),\" & --  PAD56\n\t\"2115 (BC_2, *, controlr, 1),\" &\n\t\"2116 (BC_2, IO_N34, output3, X, 2115, 1, Z),\" & --  PAD55\n\t\"2117 (BC_2, IO_N34, input, X),\" & --  PAD55\n\t\"2118 (BC_2, *, controlr, 1),\" &\n\t\"2119 (BC_2, IO_N33, output3, X, 2118, 1, Z),\" & --  PAD54\n\t\"2120 (BC_2, IO_N33, input, X),\" & --  PAD54\n\t\"2121 (BC_2, *, controlr, 1),\" &\n\t\"2122 (BC_2, IO_R35, output3, X, 2121, 1, Z),\" & --  PAD53\n\t\"2123 (BC_2, IO_R35, input, X),\" & --  PAD53\n\t\"2124 (BC_2, *, controlr, 1),\" &\n\t\"2125 (BC_2, IO_T34, output3, X, 2124, 1, Z),\" & --  PAD52\n\t\"2126 (BC_2, IO_T34, input, X),\" & --  PAD52\n\t\"2127 (BC_2, *, controlr, 1),\" &\n\t\"2128 (BC_2, IO_N35, output3, X, 2127, 1, Z),\" & --  PAD51\n\t\"2129 (BC_2, IO_N35, input, X),\" & --  PAD51\n\t\"2130 (BC_2, *, controlr, 1),\" &\n\t\"2131 (BC_2, IO_N36, output3, X, 2130, 1, Z),\" & --  PAD50\n\t\"2132 (BC_2, IO_N36, input, X),\" & --  PAD50\n\t\"2133 (BC_2, *, controlr, 1),\" &\n\t\"2134 (BC_2, IO_N40, output3, X, 2133, 1, Z),\" & --  PAD49\n\t\"2135 (BC_2, IO_N40, input, X),\" & --  PAD49\n\t\"2136 (BC_2, *, controlr, 1),\" &\n\t\"2137 (BC_2, IO_N39, output3, X, 2136, 1, Z),\" & --  PAD48\n\t\"2138 (BC_2, IO_N39, input, X),\" & --  PAD48\n\t\"2139 (BC_2, *, controlr, 1),\" &\n\t\"2140 (BC_2, IO_P40, output3, X, 2139, 1, Z),\" & --  PAD47\n\t\"2141 (BC_2, IO_P40, input, X),\" & --  PAD47\n\t\"2142 (BC_2, *, controlr, 1),\" &\n\t\"2143 (BC_2, IO_R40, output3, X, 2142, 1, Z),\" & --  PAD46\n\t\"2144 (BC_2, IO_R40, input, X),\" & --  PAD46\n\t\"2145 (BC_2, *, controlr, 1),\" &\n\t\"2146 (BC_2, IO_M39, output3, X, 2145, 1, Z),\" & --  PAD45\n\t\"2147 (BC_2, IO_M39, input, X),\" & --  PAD45\n\t\"2148 (BC_2, *, controlr, 1),\" &\n\t\"2149 (BC_2, IO_N38, output3, X, 2148, 1, Z),\" & --  PAD44\n\t\"2150 (BC_2, IO_N38, input, X),\" & --  PAD44\n\t\"2151 (BC_2, *, controlr, 1),\" &\n\t\"2152 (BC_2, IO_P42, output3, X, 2151, 1, Z),\" & --  PAD43\n\t\"2153 (BC_2, IO_P42, input, X),\" & --  PAD43\n\t\"2154 (BC_2, *, controlr, 1),\" &\n\t\"2155 (BC_2, IO_R42, output3, X, 2154, 1, Z),\" & --  PAD42\n\t\"2156 (BC_2, IO_R42, input, X),\" & --  PAD42\n\t\"2157 (BC_2, *, controlr, 1),\" &\n\t\"2158 (BC_2, IO_M38, output3, X, 2157, 1, Z),\" & --  PAD41\n\t\"2159 (BC_2, IO_M38, input, X),\" & --  PAD41\n\t\"2160 (BC_2, *, controlr, 1),\" &\n\t\"2161 (BC_2, IO_M37, output3, X, 2160, 1, Z),\" & --  PAD40\n\t\"2162 (BC_2, IO_M37, input, X),\" & --  PAD40\n\t\"2163 (BC_2, *, controlr, 1),\" &\n\t\"2164 (BC_2, IO_N41, output3, X, 2163, 1, Z),\" & --  PAD39\n\t\"2165 (BC_2, IO_N41, input, X),\" & --  PAD39\n\t\"2166 (BC_2, *, controlr, 1),\" &\n\t\"2167 (BC_2, IO_P41, output3, X, 2166, 1, Z),\" & --  PAD38\n\t\"2168 (BC_2, IO_P41, input, X),\" & --  PAD38\n\t\"2169 (BC_2, *, controlr, 1),\" &\n\t\"2170 (BC_2, IO_L37, output3, X, 2169, 1, Z),\" & --  PAD37\n\t\"2171 (BC_2, IO_L37, input, X),\" & --  PAD37\n\t\"2172 (BC_2, *, controlr, 1),\" &\n\t\"2173 (BC_2, IO_M36, output3, X, 2172, 1, Z),\" & --  PAD36\n\t\"2174 (BC_2, IO_M36, input, X),\" & --  PAD36\n\t\"2175 (BC_2, *, controlr, 1),\" &\n\t\"2176 (BC_2, IO_K38, output3, X, 2175, 1, Z),\" & --  PAD35\n\t\"2177 (BC_2, IO_K38, input, X),\" & --  PAD35\n\t\"2178 (BC_2, *, controlr, 1),\" &\n\t\"2179 (BC_2, IO_K37, output3, X, 2178, 1, Z),\" & --  PAD34\n\t\"2180 (BC_2, IO_K37, input, X),\" & --  PAD34\n\t\"2181 (BC_2, *, controlr, 1),\" &\n\t\"2182 (BC_2, IO_L42, output3, X, 2181, 1, Z),\" & --  PAD33\n\t\"2183 (BC_2, IO_L42, input, X),\" & --  PAD33\n\t\"2184 (BC_2, *, controlr, 1),\" &\n\t\"2185 (BC_2, IO_M42, output3, X, 2184, 1, Z),\" & --  PAD32\n\t\"2186 (BC_2, IO_M42, input, X),\" & --  PAD32\n\t\"2187 (BC_2, *, controlr, 1),\" &\n\t\"2188 (BC_2, IO_J42, output3, X, 2187, 1, Z),\" & --  PAD31\n\t\"2189 (BC_2, IO_J42, input, X),\" & --  PAD31\n\t\"2190 (BC_2, *, controlr, 1),\" &\n\t\"2191 (BC_2, IO_K42, output3, X, 2190, 1, Z),\" & --  PAD30\n\t\"2192 (BC_2, IO_K42, input, X),\" & --  PAD30\n\t\"2193 (BC_2, *, controlr, 1),\" &\n\t\"2194 (BC_2, IO_L41, output3, X, 2193, 1, Z),\" & --  PAD29\n\t\"2195 (BC_2, IO_L41, input, X),\" & --  PAD29\n\t\"2196 (BC_2, *, controlr, 1),\" &\n\t\"2197 (BC_2, IO_M41, output3, X, 2196, 1, Z),\" & --  PAD28\n\t\"2198 (BC_2, IO_M41, input, X),\" & --  PAD28\n\t\"2199 (BC_2, *, controlr, 1),\" &\n\t\"2200 (BC_2, IO_L40, output3, X, 2199, 1, Z),\" & --  PAD27\n\t\"2201 (BC_2, IO_L40, input, X),\" & --  PAD27\n\t\"2202 (BC_2, *, controlr, 1),\" &\n\t\"2203 (BC_2, IO_L39, output3, X, 2202, 1, Z),\" & --  PAD26\n\t\"2204 (BC_2, IO_L39, input, X),\" & --  PAD26\n\t\"2205 (BC_2, *, controlr, 1),\" &\n\t\"2206 (BC_2, IO_K40, output3, X, 2205, 1, Z),\" & --  PAD25\n\t\"2207 (BC_2, IO_K40, input, X),\" & --  PAD25\n\t\"2208 (BC_2, *, controlr, 1),\" &\n\t\"2209 (BC_2, IO_K39, output3, X, 2208, 1, Z),\" & --  PAD24\n\t\"2210 (BC_2, IO_K39, input, X),\" & --  PAD24\n\t\"2211 (BC_2, *, controlr, 1),\" &\n\t\"2212 (BC_2, IO_J41, output3, X, 2211, 1, Z),\" & --  PAD23\n\t\"2213 (BC_2, IO_J41, input, X),\" & --  PAD23\n\t\"2214 (BC_2, *, controlr, 1),\" &\n\t\"2215 (BC_2, IO_J40, output3, X, 2214, 1, Z),\" & --  PAD22\n\t\"2216 (BC_2, IO_J40, input, X),\" & --  PAD22\n\t\"2217 (BC_2, *, controlr, 1),\" &\n\t\"2218 (BC_2, IO_F41, output3, X, 2217, 1, Z),\" & --  PAD21\n\t\"2219 (BC_2, IO_F41, input, X),\" & --  PAD21\n\t\"2220 (BC_2, *, controlr, 1),\" &\n\t\"2221 (BC_2, IO_F40, output3, X, 2220, 1, Z),\" & --  PAD20\n\t\"2222 (BC_2, IO_F40, input, X),\" & --  PAD20\n\t\"2223 (BC_2, *, controlr, 1),\" &\n\t\"2224 (BC_2, IO_G42, output3, X, 2223, 1, Z),\" & --  PAD19\n\t\"2225 (BC_2, IO_G42, input, X),\" & --  PAD19\n\t\"2226 (BC_2, *, controlr, 1),\" &\n\t\"2227 (BC_2, IO_G41, output3, X, 2226, 1, Z),\" & --  PAD18\n\t\"2228 (BC_2, IO_G41, input, X),\" & --  PAD18\n\t\"2229 (BC_2, *, controlr, 1),\" &\n\t\"2230 (BC_2, IO_G39, output3, X, 2229, 1, Z),\" & --  PAD17\n\t\"2231 (BC_2, IO_G39, input, X),\" & --  PAD17\n\t\"2232 (BC_2, *, controlr, 1),\" &\n\t\"2233 (BC_2, IO_H39, output3, X, 2232, 1, Z),\" & --  PAD16\n\t\"2234 (BC_2, IO_H39, input, X),\" & --  PAD16\n\t\"2235 (BC_2, *, controlr, 1),\" &\n\t\"2236 (BC_2, IO_H41, output3, X, 2235, 1, Z),\" & --  PAD15\n\t\"2237 (BC_2, IO_H41, input, X),\" & --  PAD15\n\t\"2238 (BC_2, *, controlr, 1),\" &\n\t\"2239 (BC_2, IO_H40, output3, X, 2238, 1, Z),\" & --  PAD14\n\t\"2240 (BC_2, IO_H40, input, X),\" & --  PAD14\n\t\"2241 (BC_2, *, controlr, 1),\" &\n\t\"2242 (BC_2, IO_C41, output3, X, 2241, 1, Z),\" & --  PAD13\n\t\"2243 (BC_2, IO_C41, input, X),\" & --  PAD13\n\t\"2244 (BC_2, *, controlr, 1),\" &\n\t\"2245 (BC_2, IO_C40, output3, X, 2244, 1, Z),\" & --  PAD12\n\t\"2246 (BC_2, IO_C40, input, X),\" & --  PAD12\n\t\"2247 (BC_2, *, controlr, 1),\" &\n\t\"2248 (BC_2, IO_E42, output3, X, 2247, 1, Z),\" & --  PAD11\n\t\"2249 (BC_2, IO_E42, input, X),\" & --  PAD11\n\t\"2250 (BC_2, *, controlr, 1),\" &\n\t\"2251 (BC_2, IO_F42, output3, X, 2250, 1, Z),\" & --  PAD10\n\t\"2252 (BC_2, IO_F42, input, X),\" & --  PAD10\n\t\"2253 (BC_2, *, controlr, 1),\" &\n\t\"2254 (BC_2, IO_B42, output3, X, 2253, 1, Z),\" & --  PAD9\n\t\"2255 (BC_2, IO_B42, input, X),\" & --  PAD9\n\t\"2256 (BC_2, *, controlr, 1),\" &\n\t\"2257 (BC_2, IO_B41, output3, X, 2256, 1, Z),\" & --  PAD8\n\t\"2258 (BC_2, IO_B41, input, X),\" & --  PAD8\n\t\"2259 (BC_2, *, controlr, 1),\" &\n\t\"2260 (BC_2, IO_D42, output3, X, 2259, 1, Z),\" & --  PAD7\n\t\"2261 (BC_2, IO_D42, input, X),\" & --  PAD7\n\t\"2262 (BC_2, *, controlr, 1),\" &\n\t\"2263 (BC_2, IO_D41, output3, X, 2262, 1, Z),\" & --  PAD6\n\t\"2264 (BC_2, IO_D41, input, X),\" & --  PAD6\n\t\"2265 (BC_2, *, controlr, 1),\" &\n\t\"2266 (BC_2, IO_A41, output3, X, 2265, 1, Z),\" & --  PAD5\n\t\"2267 (BC_2, IO_A41, input, X),\" & --  PAD5\n\t\"2268 (BC_2, *, controlr, 1),\" &\n\t\"2269 (BC_2, IO_A40, output3, X, 2268, 1, Z),\" & --  PAD4\n\t\"2270 (BC_2, IO_A40, input, X),\" & --  PAD4\n\t\"2271 (BC_2, *, controlr, 1),\" &\n\t\"2272 (BC_2, IO_D40, output3, X, 2271, 1, Z),\" & --  PAD3\n\t\"2273 (BC_2, IO_D40, input, X),\" & --  PAD3\n\t\"2274 (BC_2, *, controlr, 1),\" &\n\t\"2275 (BC_2, IO_E40, output3, X, 2274, 1, Z),\" & --  PAD2\n\t\"2276 (BC_2, IO_E40, input, X),\" & --  PAD2\n\t\"2277 (BC_2, *, controlr, 1),\" &\n\t\"2278 (BC_2, IO_L36, output3, X, 2277, 1, Z),\" & --  PAD1\n\t\"2279 (BC_2, IO_L36, input, X),\" & --  PAD1\n\t\"2280 (BC_2, *, internal, X),\" &\n\t\"2281 (BC_2, *, internal, X),\" &\n\t\"2282 (BC_2, *, internal, X),\" &\n\t\"2283 (BC_2, *, internal, X),\" &\n\t\"2284 (BC_2, *, internal, X),\" &\n\t\"2285 (BC_2, *, internal, X),\" &\n\t\"2286 (BC_2, *, internal, X),\" &\n\t\"2287 (BC_2, *, internal, X),\" &\n\t\"2288 (BC_2, *, internal, X),\" &\n\t\"2289 (BC_2, *, internal, X),\" &\n\t\"2290 (BC_2, *, internal, X),\" &\n\t\"2291 (BC_2, *, internal, X),\" &\n\t\"2292 (BC_2, *, internal, X),\" &\n\t\"2293 (BC_2, *, internal, X),\" &\n\t\"2294 (BC_2, *, internal, X),\" &\n\t\"2295 (BC_2, *, internal, X),\" &\n\t\"2296 (BC_4, *, internal, X),\" &\n\t\"2297 (BC_4, *, internal, X),\" &\n\t\"2298 (BC_4, *, internal, X),\" &\n\t\"2299 (BC_4, *, internal, X),\" &\n\t\"2300 (BC_4, *, internal, X),\" &\n\t\"2301 (BC_4, *, internal, X),\" &\n\t\"2302 (BC_4, *, internal, X),\" &\n\t\"2303 (BC_4, *, internal, X),\" &\n\t\"2304 (BC_4, *, internal, X),\" &\n\t\"2305 (BC_4, *, internal, X),\" &\n\t\"2306 (BC_4, *, internal, X),\" &\n\t\"2307 (BC_4, *, internal, X),\" &\n\t\"2308 (BC_4, *, internal, X),\" &\n\t\"2309 (BC_4, *, internal, X),\" &\n\t\"2310 (BC_4, *, internal, X),\" &\n\t\"2311 (BC_4, *, internal, X),\" &\n\t\"2312 (BC_4, *, internal, X),\" &\n\t\"2313 (BC_4, *, internal, X),\" &\n\t\"2314 (BC_4, *, internal, X),\" &\n\t\"2315 (BC_4, *, internal, X),\" &\n\t\"2316 (BC_4, *, internal, X),\" &\n\t\"2317 (BC_4, *, internal, X),\" &\n\t\"2318 (BC_4, *, internal, X),\" &\n\t\"2319 (BC_4, *, internal, X),\" &\n\t\"2320 (BC_4, *, internal, X),\" &\n\t\"2321 (BC_4, *, internal, X),\" &\n\t\"2322 (BC_4, *, internal, X),\" &\n\t\"2323 (BC_4, *, internal, X),\" &\n\t\"2324 (BC_4, *, internal, X),\" &\n\t\"2325 (BC_4, *, internal, X),\" &\n\t\"2326 (BC_4, *, internal, X),\" &\n\t\"2327 (BC_4, *, internal, X),\" &\n\t\"2328 (BC_4, *, internal, X),\" &\n\t\"2329 (BC_4, *, internal, X),\" &\n\t\"2330 (BC_4, *, internal, X),\" &\n\t\"2331 (BC_4, *, internal, X),\" &\n\t\"2332 (BC_4, *, internal, X),\" &\n\t\"2333 (BC_4, *, internal, X),\" &\n\t\"2334 (BC_4, *, internal, X),\" &\n\t\"2335 (BC_4, *, internal, X),\" &\n\t\"2336 (BC_4, *, internal, X),\" &\n\t\"2337 (BC_4, *, internal, X),\" &\n\t\"2338 (BC_4, *, internal, X),\" &\n\t\"2339 (BC_4, *, internal, X),\" &\n\t\"2340 (BC_4, *, internal, X),\" &\n\t\"2341 (BC_4, *, internal, X),\" &\n\t\"2342 (BC_4, *, internal, X),\" &\n\t\"2343 (BC_4, *, internal, X),\" &\n\t\"2344 (BC_4, *, internal, X),\" &\n\t\"2345 (BC_4, *, internal, X),\" &\n\t\"2346 (BC_4, *, internal, X),\" &\n\t\"2347 (BC_4, *, internal, X),\" &\n\t\"2348 (BC_4, *, internal, X),\" &\n\t\"2349 (BC_4, *, internal, X),\" &\n\t\"2350 (BC_4, *, internal, X),\" &\n\t\"2351 (BC_4, *, internal, X),\" &\n\t\"2352 (BC_4, *, internal, X),\" &\n\t\"2353 (BC_4, *, internal, X),\" &\n\t\"2354 (BC_4, *, internal, X),\" &\n\t\"2355 (BC_4, *, internal, X),\" &\n\t\"2356 (BC_4, *, internal, X),\" &\n\t\"2357 (BC_4, *, internal, X),\" &\n\t\"2358 (BC_4, *, internal, X),\" &\n\t\"2359 (BC_4, *, internal, X),\" &\n\t\"2360 (BC_4, *, internal, X),\" &\n\t\"2361 (BC_4, *, internal, X),\" &\n\t\"2362 (BC_4, *, internal, X),\" &\n\t\"2363 (BC_4, *, internal, X),\" &\n\t\"2364 (BC_4, *, internal, X),\" &\n\t\"2365 (BC_4, *, internal, X),\" &\n\t\"2366 (BC_4, *, internal, X),\" &\n\t\"2367 (BC_4, *, internal, X),\" &\n\t\"2368 (BC_4, *, internal, X),\" &\n\t\"2369 (BC_4, *, internal, X),\" &\n\t\"2370 (BC_4, *, internal, X),\" &\n\t\"2371 (BC_4, *, internal, X),\" &\n\t\"2372 (BC_4, *, internal, X),\" &\n\t\"2373 (BC_4, *, internal, X),\" &\n\t\"2374 (BC_4, *, internal, X),\" &\n\t\"2375 (BC_4, *, internal, X),\" &\n\t\"2376 (BC_4, *, internal, X),\" &\n\t\"2377 (BC_4, *, internal, X),\" &\n\t\"2378 (BC_4, *, internal, X),\" &\n\t\"2379 (BC_4, *, internal, X),\" &\n\t\"2380 (BC_2, *, internal, X),\" &\n\t\"2381 (BC_2, *, internal, X),\" &\n\t\"2382 (BC_2, *, internal, X),\" &\n\t\"2383 (BC_2, *, internal, X),\" &\n\t\"2384 (BC_2, *, internal, X),\" &\n\t\"2385 (BC_2, *, internal, X),\" &\n\t\"2386 (BC_2, *, internal, X),\" &\n\t\"2387 (BC_2, *, internal, X),\" &\n\t\"2388 (BC_2, *, internal, X),\" &\n\t\"2389 (BC_2, *, internal, X),\" &\n\t\"2390 (BC_2, *, internal, X),\" &\n\t\"2391 (BC_2, *, internal, X),\" &\n\t\"2392 (BC_2, *, internal, X),\" &\n\t\"2393 (BC_2, *, internal, X),\" &\n\t\"2394 (BC_2, *, internal, X),\" &\n\t\"2395 (BC_2, *, internal, X),\" &\n\t\"2396 (BC_2, *, internal, X),\" &\n\t\"2397 (BC_2, *, internal, X),\" &\n\t\"2398 (BC_2, *, internal, X),\" &\n\t\"2399 (BC_2, *, internal, X),\" &\n\t\"2400 (BC_2, *, internal, X)\";\n\n\n-- Advanced I/O Description\n\nattribute AIO_COMPONENT_CONFORMANCE of XC7VX485T_FFG1761 : entity is\n\t\"STD_1149_6_2003\";\n\nattribute AIO_EXTEST_Pulse_Execution of XC7VX485T_FFG1761 : entity is\n\t\"Wait_Duration TCK 15\";\n\nattribute AIO_EXTEST_Train_Execution of XC7VX485T_FFG1761 : entity is\n\t\"train 30, maximum_time 120.0e-6\";\n\nattribute AIO_Pin_Behavior of XC7VX485T_FFG1761 : entity is\n\"MGTXRXP0_113 : LP_time=22.5e-9 HP_time=45.0e-9; \" &\n\"MGTXRXP0_114 : LP_time=22.5e-9 HP_time=45.0e-9; \" &\n\"MGTXRXP0_115 : LP_time=22.5e-9 HP_time=45.0e-9; \" &\n\"MGTXRXP0_116 : LP_time=22.5e-9 HP_time=45.0e-9; \" &\n\"MGTXRXP0_117 : LP_time=22.5e-9 HP_time=45.0e-9; \" &\n\"MGTXRXP0_118 : LP_time=22.5e-9 HP_time=45.0e-9; \" &\n\"MGTXRXP0_119 : LP_time=22.5e-9 HP_time=45.0e-9; \" &\n\"MGTXRXP1_113 : LP_time=22.5e-9 HP_time=45.0e-9; \" &\n\"MGTXRXP1_114 : LP_time=22.5e-9 HP_time=45.0e-9; \" &\n\"MGTXRXP1_115 : LP_time=22.5e-9 HP_time=45.0e-9; \" &\n\"MGTXRXP1_116 : LP_time=22.5e-9 HP_time=45.0e-9; \" &\n\"MGTXRXP1_117 : LP_time=22.5e-9 HP_time=45.0e-9; \" &\n\"MGTXRXP1_118 : LP_time=22.5e-9 HP_time=45.0e-9; \" &\n\"MGTXRXP1_119 : LP_time=22.5e-9 HP_time=45.0e-9; \" &\n\"MGTXRXP2_113 : LP_time=22.5e-9 HP_time=45.0e-9; \" &\n\"MGTXRXP2_114 : LP_time=22.5e-9 HP_time=45.0e-9; \" &\n\"MGTXRXP2_115 : LP_time=22.5e-9 HP_time=45.0e-9; \" &\n\"MGTXRXP2_116 : LP_time=22.5e-9 HP_time=45.0e-9; \" &\n\"MGTXRXP2_117 : LP_time=22.5e-9 HP_time=45.0e-9; \" &\n\"MGTXRXP2_118 : LP_time=22.5e-9 HP_time=45.0e-9; \" &\n\"MGTXRXP2_119 : LP_time=22.5e-9 HP_time=45.0e-9; \" &\n\"MGTXRXP3_113 : LP_time=22.5e-9 HP_time=45.0e-9; \" &\n\"MGTXRXP3_114 : LP_time=22.5e-9 HP_time=45.0e-9; \" &\n\"MGTXRXP3_115 : LP_time=22.5e-9 HP_time=45.0e-9; \" &\n\"MGTXRXP3_116 : LP_time=22.5e-9 HP_time=45.0e-9; \" &\n\"MGTXRXP3_117 : LP_time=22.5e-9 HP_time=45.0e-9; \" &\n\"MGTXRXP3_118 : LP_time=22.5e-9 HP_time=45.0e-9; \" &\n\"MGTXRXP3_119 : LP_time=22.5e-9 HP_time=45.0e-9; \" &\n\"MGTXTXP0_113; \" &\n\"MGTXTXP0_114; \" &\n\"MGTXTXP0_115; \" &\n\"MGTXTXP0_116; \" &\n\"MGTXTXP0_117; \" &\n\"MGTXTXP0_118; \" &\n\"MGTXTXP0_119; \" &\n\"MGTXTXP1_113; \" &\n\"MGTXTXP1_114; \" &\n\"MGTXTXP1_115; \" &\n\"MGTXTXP1_116; \" &\n\"MGTXTXP1_117; \" &\n\"MGTXTXP1_118; \" &\n\"MGTXTXP1_119; \" &\n\"MGTXTXP2_113; \" &\n\"MGTXTXP2_114; \" &\n\"MGTXTXP2_115; \" &\n\"MGTXTXP2_116; \" &\n\"MGTXTXP2_117; \" &\n\"MGTXTXP2_118; \" &\n\"MGTXTXP2_119; \" &\n\"MGTXTXP3_113; \" &\n\"MGTXTXP3_114; \" &\n\"MGTXTXP3_115; \" &\n\"MGTXTXP3_116; \" &\n\"MGTXTXP3_117; \" &\n\"MGTXTXP3_118; \" &\n\"MGTXTXP3_119 \";\n\n-- Design Warning Section\n\nattribute DESIGN_WARNING of XC7VX485T_FFG1761 : entity is\n        \"This is a preliminary BSDL file which has not been verified.\" &\n\t\"When no bitstream is loaded and GTPs are not instantiated,\" &\n\t\t\"the boundary-scan cells associated with GTPs will not\" &\n\t\t\"capture correct state information.  To model the boundary-\" &\n\t\t\"scan cell behavior correctly post-configuration, use\" &\n\t\t\"BSDLanno to modify the BSDL file.\" &\n        \"This BSDL file must be modified by the FPGA designer in order to\" &\n                \"reflect post-configuration behavior (if any).\" &\n        \"To avoid losing the current configuration, the boundary scan\" &\n                \"test vectors should keep the PROGRAM_B pin\" &\n                \"high.  If the PROGRAM_B pin goes low by any means,\" &\n                \"the configuration will be cleared.\" &\n        \"PROGRAM_B can only be captured, not updated.\" &\n                \"The value at the pin is always used by the device.\" &\n        \"In EXTEST, output and tristate values are not captured in the\" &\n                \"Capture-DR state - those register cells are unchanged.\" &\n\t\"Differential Serial IO pins do not support INTEST.\" &\n        \"In INTEST, the pin input values are not captured in the\" &\n                \"Capture-DR state - those register cells are unchanged.\" &\n        \"The output and tristate capture values are not valid until after\" &\n                \"the device is configured.\" &\n        \"The tristate control value is not captured properly when\" &\n                \"GTS is activated.\" &\n\t\"The IEEE Std 1149.6 EXTEST_PULSE and EXTEST_TRAIN instructions\" &\n\t\t\"require a minimum TCK freq of 15 MHz and min temp of 0C.\" &\n\t\"NOCONNECT pins should not be connected to any supply\" &\n\t\t\"or GND.  They should be left floating.\";\n\nend XC7VX485T_FFG1761;\n\n"
  },
  {
    "path": "jtag/bsd/xc7vx690t_ffg1761.bsd",
    "content": "-- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.\n--\n-- This file contains confidential and proprietary information\n-- of Xilinx, Inc. and is protected under U.S. and\n-- international copyright and other intellectual property\n-- laws.\n--\n-- DISCLAIMER\n-- This disclaimer is not a license and does not grant any\n-- rights to the materials distributed herewith. Except as\n-- otherwise provided in a valid license issued to you by\n-- Xilinx, and to the maximum extent permitted by applicable\n-- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n-- (2) Xilinx shall not be liable (whether in contract or tort,\n-- including negligence, or under any other theory of \n-- liability) for any loss or damage of any kind or nature\n-- releated to, arising under or in connection with these\n-- materials, including for any direct, or any indirect,\n-- special, incidental, or consequential loss or damage\n-- (including loss of data, profits, goodwill, or any type of\n-- loss or damage suffered as a result of any action brought\n-- by a third party) even if such damage or loss was\n-- reasonably foreseeable or Xilinx had been advised of the\n-- possibility of the same.\n--\n-- CRITICAL APPLICATIONS\n-- Xilinx products are not designed or intended to be fail-\n-- safe, or for use in any application requiring fail-safe\n-- performance, such as life-support or safety devices or\n-- systems, Class III medical devices, nuclear facilities,\n-- applications related to the deployment of airbags, or any\n-- other applications that could lead to death, personal\n-- injury, or severe property or environmental damage\n-- (individually and collectively, \"Critical\n-- Applications\"). Customer assumes the sole risk and\n-- liability of any use of Xilinx products in Critical\n-- Applications, subject only to applicable laws and\n-- regulations governing limitiations on product liability.\n--\n-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n-- PART OF THIS FILE AT ALL TIMES.\n--\n-- BSDL file for device XC7VX690T, package FFG1761\n-- Generated by bsdlnet Version 1.7\n-- Generated on Wed Dec 07, 2011  09:45:28 PST\n-- Generated using schematic at v32_top/xc7vx690t/schematic\n-- Schematic date = 2011-10-18 10:03:12\n-- Schematic ICM_VARIANT = 28t_n1\n-- Package File date = # Date    : 2011-09-22 15:41:14\n------------------------------------------------------------------------\n-- Modification History\n-- | CR # N/A\n-- | Details -  Initial Release\n------------------------------------------------------------------------\n--\n-- For technical support, http://support.xilinx.com -> enter text 'bsdl'\n-- in the text search box at the left of the page.  If none of\n-- these records resolve your problem you should open a web support case\n-- or contact our technical support at:\n--\n--\tNorth America\t1-800-255-7778\t\thotline@xilinx.com\n--\tUnited Kingdom\t+44 870 7350 610\teurosupport@xilinx.com\n--\tFrance\t\t(33) 1 3463 0100\teurosupport@xilinx.com\n--\tGermany\t\t(49) 89 991 54930\teurosupport@xilinx.com\n--\tJapan\t\t(81) 3-3297-9163\tjhotline@xilinx.com\n--\n-- This BSDL file reflects the pre-configuration JTAG behavior. To reflect\n-- the post-configuration JTAG behavior (if any), edit this file as described\n-- below. Many of these changes are demonstrated by commented-out template\n-- lines preceeding the lines they would replace:\n--\n-- 1. Enable USER instructions as appropriate (see below).\n-- 2. Set disable result of all pads as configured.\n-- 3. Set safe state of boundary cells as necessary.\n-- 4. Rename entity if necessary to avoid name collisions.\n-- 5. Modify USERCODE value in USERCODE_REGISTER declaration.\n--\n-- To prevent losing the current configuration, the boundary scan\n-- test vectors should keep the PROGRAM_B pin high.\n--\n-- PROGRAM_B can only be captured, not updated.  The value\n-- at the pin is always used by the device.\n--\n-- All IOBs prior to configuration, and unused and output-only IOBs following\n-- configuration, will sense their pad values during boundary-scan with an CMOS\n-- input buffer. In order to properly capture a logic high value at one\n-- of these IOBs into its input boundary scan cell, please refer to the\n-- datasheet and user guide for proper input levels.\n--\n-- For post-configuration boundary scan only: If an IOB is configured to use\n-- an input standard that uses VREF pins, then the boundary scan test vectors\n-- must keep the used VREF pins 3-stated.\n\n----------------------------------\n\n-- BSDL File for P1149.6 Standard.\n\n----------------------------------\n-- ----------------------------------------------------------------------\n-- This BSDL file has been checked and verified by JTAG Technologies B.V.\n-- on 2011-12-08, for syntactical and semantic compliance with\n-- IEEE standards 1149.1 and 1149.6\n-- using bsdl32.dll 1.6.1.5 - 20110523 Win32\n-- copyright (c) 2009 JTAG Technologies B.V., All rights reserved\n-- ----------------------------------------------------------------------\n\n------------------------------------------------------------------------\n-- | Generated on 01/31/14\n-- | CR # 707581\n-- | Details - Removed \"Prelim\" statement.\n------------------------------------------------------------------------\nentity XC7VX690T_FFG1761 is\n\n-- Generic Parameter\n\ngeneric (PHYSICAL_PIN_MAP : string := \"FFG1761\" );\n\n-- Logical Port Description\n\nport (\n\tCCLK_N10: inout bit; --  CCLK_0\n\tCFGBVS_AH10: in bit; --  CFGBVS_0\n\tDONE_AL11: inout bit; --  DONE_0\n\tGND: linkage bit_vector (1 to 424);\n\tGNDADC_0: linkage bit;\n\tINIT_B_AG11: inout bit; --  INIT_B_0\n\tM0_AL10: in bit; --  M0_0\n\tM1_AK10: in bit; --  M1_0\n\tM2_AJ10: in bit; --  M2_0\n\tMGTAVCC_G10: linkage bit_vector (1 to 11);\n\tMGTAVCC_G11: linkage bit_vector (1 to 5);\n\tMGTAVTTRCAL_115: linkage bit;\n\tMGTAVTT_G10: linkage bit_vector (1 to 16);\n\tMGTAVTT_G11: linkage bit_vector (1 to 11);\n\tMGTHRXN0_111: in bit;\n\tMGTHRXN0_112: in bit;\n\tMGTHRXN0_113: in bit;\n\tMGTHRXN0_114: in bit;\n\tMGTHRXN0_115: in bit;\n\tMGTHRXN0_116: in bit;\n\tMGTHRXN0_117: in bit;\n\tMGTHRXN0_118: in bit;\n\tMGTHRXN0_119: in bit;\n\tMGTHRXN1_111: in bit;\n\tMGTHRXN1_112: in bit;\n\tMGTHRXN1_113: in bit;\n\tMGTHRXN1_114: in bit;\n\tMGTHRXN1_115: in bit;\n\tMGTHRXN1_116: in bit;\n\tMGTHRXN1_117: in bit;\n\tMGTHRXN1_118: in bit;\n\tMGTHRXN1_119: in bit;\n\tMGTHRXN2_111: in bit;\n\tMGTHRXN2_112: in bit;\n\tMGTHRXN2_113: in bit;\n\tMGTHRXN2_114: in bit;\n\tMGTHRXN2_115: in bit;\n\tMGTHRXN2_116: in bit;\n\tMGTHRXN2_117: in bit;\n\tMGTHRXN2_118: in bit;\n\tMGTHRXN2_119: in bit;\n\tMGTHRXN3_111: in bit;\n\tMGTHRXN3_112: in bit;\n\tMGTHRXN3_113: in bit;\n\tMGTHRXN3_114: in bit;\n\tMGTHRXN3_115: in bit;\n\tMGTHRXN3_116: in bit;\n\tMGTHRXN3_117: in bit;\n\tMGTHRXN3_118: in bit;\n\tMGTHRXN3_119: in bit;\n\tMGTHRXP0_111: in bit;\n\tMGTHRXP0_112: in bit;\n\tMGTHRXP0_113: in bit;\n\tMGTHRXP0_114: in bit;\n\tMGTHRXP0_115: in bit;\n\tMGTHRXP0_116: in bit;\n\tMGTHRXP0_117: in bit;\n\tMGTHRXP0_118: in bit;\n\tMGTHRXP0_119: in bit;\n\tMGTHRXP1_111: in bit;\n\tMGTHRXP1_112: in bit;\n\tMGTHRXP1_113: in bit;\n\tMGTHRXP1_114: in bit;\n\tMGTHRXP1_115: in bit;\n\tMGTHRXP1_116: in bit;\n\tMGTHRXP1_117: in bit;\n\tMGTHRXP1_118: in bit;\n\tMGTHRXP1_119: in bit;\n\tMGTHRXP2_111: in bit;\n\tMGTHRXP2_112: in bit;\n\tMGTHRXP2_113: in bit;\n\tMGTHRXP2_114: in bit;\n\tMGTHRXP2_115: in bit;\n\tMGTHRXP2_116: in bit;\n\tMGTHRXP2_117: in bit;\n\tMGTHRXP2_118: in bit;\n\tMGTHRXP2_119: in bit;\n\tMGTHRXP3_111: in bit;\n\tMGTHRXP3_112: in bit;\n\tMGTHRXP3_113: in bit;\n\tMGTHRXP3_114: in bit;\n\tMGTHRXP3_115: in bit;\n\tMGTHRXP3_116: in bit;\n\tMGTHRXP3_117: in bit;\n\tMGTHRXP3_118: in bit;\n\tMGTHRXP3_119: in bit;\n\tMGTHTXN0_111: buffer bit;\n\tMGTHTXN0_112: buffer bit;\n\tMGTHTXN0_113: buffer bit;\n\tMGTHTXN0_114: buffer bit;\n\tMGTHTXN0_115: buffer bit;\n\tMGTHTXN0_116: buffer bit;\n\tMGTHTXN0_117: buffer bit;\n\tMGTHTXN0_118: buffer bit;\n\tMGTHTXN0_119: buffer bit;\n\tMGTHTXN1_111: buffer bit;\n\tMGTHTXN1_112: buffer bit;\n\tMGTHTXN1_113: buffer bit;\n\tMGTHTXN1_114: buffer bit;\n\tMGTHTXN1_115: buffer bit;\n\tMGTHTXN1_116: buffer bit;\n\tMGTHTXN1_117: buffer bit;\n\tMGTHTXN1_118: buffer bit;\n\tMGTHTXN1_119: buffer bit;\n\tMGTHTXN2_111: buffer bit;\n\tMGTHTXN2_112: buffer bit;\n\tMGTHTXN2_113: buffer bit;\n\tMGTHTXN2_114: buffer bit;\n\tMGTHTXN2_115: buffer bit;\n\tMGTHTXN2_116: buffer bit;\n\tMGTHTXN2_117: buffer bit;\n\tMGTHTXN2_118: buffer bit;\n\tMGTHTXN2_119: buffer bit;\n\tMGTHTXN3_111: buffer bit;\n\tMGTHTXN3_112: buffer bit;\n\tMGTHTXN3_113: buffer bit;\n\tMGTHTXN3_114: buffer bit;\n\tMGTHTXN3_115: buffer bit;\n\tMGTHTXN3_116: buffer bit;\n\tMGTHTXN3_117: buffer bit;\n\tMGTHTXN3_118: buffer bit;\n\tMGTHTXN3_119: buffer bit;\n\tMGTHTXP0_111: buffer bit;\n\tMGTHTXP0_112: buffer bit;\n\tMGTHTXP0_113: buffer bit;\n\tMGTHTXP0_114: buffer bit;\n\tMGTHTXP0_115: buffer bit;\n\tMGTHTXP0_116: buffer bit;\n\tMGTHTXP0_117: buffer bit;\n\tMGTHTXP0_118: buffer bit;\n\tMGTHTXP0_119: buffer bit;\n\tMGTHTXP1_111: buffer bit;\n\tMGTHTXP1_112: buffer bit;\n\tMGTHTXP1_113: buffer bit;\n\tMGTHTXP1_114: buffer bit;\n\tMGTHTXP1_115: buffer bit;\n\tMGTHTXP1_116: buffer bit;\n\tMGTHTXP1_117: buffer bit;\n\tMGTHTXP1_118: buffer bit;\n\tMGTHTXP1_119: buffer bit;\n\tMGTHTXP2_111: buffer bit;\n\tMGTHTXP2_112: buffer bit;\n\tMGTHTXP2_113: buffer bit;\n\tMGTHTXP2_114: buffer bit;\n\tMGTHTXP2_115: buffer bit;\n\tMGTHTXP2_116: buffer bit;\n\tMGTHTXP2_117: buffer bit;\n\tMGTHTXP2_118: buffer bit;\n\tMGTHTXP2_119: buffer bit;\n\tMGTHTXP3_111: buffer bit;\n\tMGTHTXP3_112: buffer bit;\n\tMGTHTXP3_113: buffer bit;\n\tMGTHTXP3_114: buffer bit;\n\tMGTHTXP3_115: buffer bit;\n\tMGTHTXP3_116: buffer bit;\n\tMGTHTXP3_117: buffer bit;\n\tMGTHTXP3_118: buffer bit;\n\tMGTHTXP3_119: buffer bit;\n\tMGTREFCLK0N_111: linkage bit;\n\tMGTREFCLK0N_112: linkage bit;\n\tMGTREFCLK0N_113: linkage bit;\n\tMGTREFCLK0N_114: linkage bit;\n\tMGTREFCLK0N_115: linkage bit;\n\tMGTREFCLK0N_116: linkage bit;\n\tMGTREFCLK0N_117: linkage bit;\n\tMGTREFCLK0N_118: linkage bit;\n\tMGTREFCLK0N_119: linkage bit;\n\tMGTREFCLK0P_111: linkage bit;\n\tMGTREFCLK0P_112: linkage bit;\n\tMGTREFCLK0P_113: linkage bit;\n\tMGTREFCLK0P_114: linkage bit;\n\tMGTREFCLK0P_115: linkage bit;\n\tMGTREFCLK0P_116: linkage bit;\n\tMGTREFCLK0P_117: linkage bit;\n\tMGTREFCLK0P_118: linkage bit;\n\tMGTREFCLK0P_119: linkage bit;\n\tMGTREFCLK1N_111: linkage bit;\n\tMGTREFCLK1N_112: linkage bit;\n\tMGTREFCLK1N_113: linkage bit;\n\tMGTREFCLK1N_114: linkage bit;\n\tMGTREFCLK1N_115: linkage bit;\n\tMGTREFCLK1N_116: linkage bit;\n\tMGTREFCLK1N_117: linkage bit;\n\tMGTREFCLK1N_118: linkage bit;\n\tMGTREFCLK1N_119: linkage bit;\n\tMGTREFCLK1P_111: linkage bit;\n\tMGTREFCLK1P_112: linkage bit;\n\tMGTREFCLK1P_113: linkage bit;\n\tMGTREFCLK1P_114: linkage bit;\n\tMGTREFCLK1P_115: linkage bit;\n\tMGTREFCLK1P_116: linkage bit;\n\tMGTREFCLK1P_117: linkage bit;\n\tMGTREFCLK1P_118: linkage bit;\n\tMGTREFCLK1P_119: linkage bit;\n\tMGTRREF_115: linkage bit;\n\tMGTVCCAUX_G10: linkage bit_vector (1 to 2);\n\tMGTVCCAUX_G11: linkage bit;\n\tNOCONNECT: linkage bit_vector (1 to 4);\n\tPROGRAM_B: in bit; --  PROGRAM_B_0\n\tTCK: in bit; --  TCK_0\n\tTDI: in bit; --  TDI_0\n\tTDN_AC20: linkage bit; --  DXN_0\n\tTDO: out bit; --  TDO_0\n\tTDP_AC21: linkage bit; --  DXP_0\n\tTMS: in bit; --  TMS_0\n\tVCCADC_0: linkage bit;\n\tVCCAUX: linkage bit_vector (1 to 29);\n\tVCCBATT_0: linkage bit;\n\tVCCBRAM: linkage bit_vector (1 to 8);\n\tVCCINT: linkage bit_vector (1 to 86);\n\tVCCO_0: linkage bit_vector (1 to 2);\n\tVCCO_12: linkage bit_vector (1 to 6);\n\tVCCO_13: linkage bit_vector (1 to 7);\n\tVCCO_14: linkage bit_vector (1 to 7);\n\tVCCO_15: linkage bit_vector (1 to 6);\n\tVCCO_16: linkage bit_vector (1 to 6);\n\tVCCO_17: linkage bit_vector (1 to 6);\n\tVCCO_18: linkage bit_vector (1 to 6);\n\tVCCO_19: linkage bit_vector (1 to 7);\n\tVCCO_31: linkage bit_vector (1 to 7);\n\tVCCO_32: linkage bit_vector (1 to 6);\n\tVCCO_33: linkage bit_vector (1 to 6);\n\tVCCO_34: linkage bit_vector (1 to 6);\n\tVCCO_35: linkage bit_vector (1 to 7);\n\tVCCO_36: linkage bit_vector (1 to 7);\n\tVCCO_37: linkage bit_vector (1 to 6);\n\tVCCO_38: linkage bit_vector (1 to 6);\n\tVCCO_39: linkage bit_vector (1 to 6);\n\tVN_AB20: linkage bit; --  VN_0\n\tVP_AA21: linkage bit; --  VP_0\n\tVREFN_AA20: linkage bit; --  VREFN_0\n\tVREFP_AB21: linkage bit; --  VREFP_0\n\tIO_A14: inout bit; --  PAD505\n\tIO_A15: inout bit; --  PAD555\n\tIO_A16: inout bit; --  PAD554\n\tIO_A17: inout bit; --  PAD559\n\tIO_A19: inout bit; --  PAD557\n\tIO_A20: inout bit; --  PAD556\n\tIO_A21: inout bit; --  PAD561\n\tIO_A22: inout bit; --  PAD605\n\tIO_A24: inout bit; --  PAD602\n\tIO_A25: inout bit; --  PAD603\n\tIO_A26: inout bit; --  PAD606\n\tIO_A27: inout bit; --  PAD607\n\tIO_A29: inout bit; --  PAD634\n\tIO_A30: inout bit; --  PAD635\n\tIO_A31: inout bit; --  PAD632\n\tIO_A32: inout bit; --  PAD633\n\tIO_A34: inout bit; --  PAD705\n\tIO_A35: inout bit; --  PAD708\n\tIO_A36: inout bit; --  PAD709\n\tIO_A37: inout bit; --  PAD703\n\tIO_A39: inout bit; --  PAD707\n\tIO_A40: inout bit; --  PAD4\n\tIO_A41: inout bit; --  PAD5\n\tIO_B14: inout bit; --  PAD504\n\tIO_B16: inout bit; --  PAD503\n\tIO_B17: inout bit; --  PAD558\n\tIO_B18: inout bit; --  PAD563\n\tIO_B19: inout bit; --  PAD553\n\tIO_B21: inout bit; --  PAD560\n\tIO_B22: inout bit; --  PAD604\n\tIO_B23: inout bit; --  PAD609\n\tIO_B24: inout bit; --  PAD613\n\tIO_B26: inout bit; --  PAD610\n\tIO_B27: inout bit; --  PAD611\n\tIO_B28: inout bit; --  PAD630\n\tIO_B29: inout bit; --  PAD631\n\tIO_B31: inout bit; --  PAD637\n\tIO_B32: inout bit; --  PAD716\n\tIO_B33: inout bit; --  PAD717\n\tIO_B34: inout bit; --  PAD704\n\tIO_B36: inout bit; --  PAD702\n\tIO_B37: inout bit; --  PAD712\n\tIO_B38: inout bit; --  PAD713\n\tIO_B39: inout bit; --  PAD706\n\tIO_B41: inout bit; --  PAD8\n\tIO_B42: inout bit; --  PAD9\n\tIO_C13: inout bit; --  PAD509\n\tIO_C14: inout bit; --  PAD507\n\tIO_C15: inout bit; --  PAD506\n\tIO_C16: inout bit; --  PAD502\n\tIO_C18: inout bit; --  PAD562\n\tIO_C19: inout bit; --  PAD552\n\tIO_C20: inout bit; --  PAD565\n\tIO_C21: inout bit; --  PAD569\n\tIO_C23: inout bit; --  PAD608\n\tIO_C24: inout bit; --  PAD612\n\tIO_C25: inout bit; --  PAD624\n\tIO_C26: inout bit; --  PAD625\n\tIO_C28: inout bit; --  PAD628\n\tIO_C29: inout bit; --  PAD629\n\tIO_C30: inout bit; --  PAD641\n\tIO_C31: inout bit; --  PAD636\n\tIO_C33: inout bit; --  PAD720\n\tIO_C34: inout bit; --  PAD721\n\tIO_C35: inout bit; --  PAD724\n\tIO_C36: inout bit; --  PAD725\n\tIO_C38: inout bit; --  PAD710\n\tIO_C39: inout bit; --  PAD711\n\tIO_C40: inout bit; --  PAD12\n\tIO_C41: inout bit; --  PAD13\n\tIO_D12: inout bit; --  PAD513\n\tIO_D13: inout bit; --  PAD508\n\tIO_D15: inout bit; --  PAD511\n\tIO_D16: inout bit; --  PAD510\n\tIO_D17: inout bit; --  PAD571\n\tIO_D18: inout bit; --  PAD570\n\tIO_D20: inout bit; --  PAD564\n\tIO_D21: inout bit; --  PAD568\n\tIO_D22: inout bit; --  PAD620\n\tIO_D23: inout bit; --  PAD621\n\tIO_D25: inout bit; --  PAD622\n\tIO_D26: inout bit; --  PAD623\n\tIO_D27: inout bit; --  PAD626\n\tIO_D28: inout bit; --  PAD627\n\tIO_D30: inout bit; --  PAD640\n\tIO_D31: inout bit; --  PAD639\n\tIO_D32: inout bit; --  PAD715\n\tIO_D33: inout bit; --  PAD719\n\tIO_D35: inout bit; --  PAD722\n\tIO_D36: inout bit; --  PAD723\n\tIO_D37: inout bit; --  PAD728\n\tIO_D38: inout bit; --  PAD729\n\tIO_D40: inout bit; --  PAD3\n\tIO_D41: inout bit; --  PAD6\n\tIO_D42: inout bit; --  PAD7\n\tIO_E12: inout bit; --  PAD512\n\tIO_E13: inout bit; --  PAD517\n\tIO_E14: inout bit; --  PAD516\n\tIO_E15: inout bit; --  PAD515\n\tIO_E17: inout bit; --  PAD567\n\tIO_E18: inout bit; --  PAD575\n\tIO_E19: inout bit; --  PAD574\n\tIO_E20: inout bit; --  PAD581\n\tIO_E22: inout bit; --  PAD617\n\tIO_E23: inout bit; --  PAD614\n\tIO_E24: inout bit; --  PAD615\n\tIO_E25: inout bit; --  PAD619\n\tIO_E27: inout bit; --  PAD642\n\tIO_E28: inout bit; --  PAD643\n\tIO_E29: inout bit; --  PAD645\n\tIO_E30: inout bit; --  PAD638\n\tIO_E32: inout bit; --  PAD714\n\tIO_E33: inout bit; --  PAD718\n\tIO_E34: inout bit; --  PAD726\n\tIO_E35: inout bit; --  PAD727\n\tIO_E37: inout bit; --  PAD738\n\tIO_E38: inout bit; --  PAD739\n\tIO_E39: inout bit; --  PAD743\n\tIO_E40: inout bit; --  PAD2\n\tIO_E42: inout bit; --  PAD11\n\tIO_F12: inout bit; --  PAD521\n\tIO_F14: inout bit; --  PAD523\n\tIO_F15: inout bit; --  PAD522\n\tIO_F16: inout bit; --  PAD514\n\tIO_F17: inout bit; --  PAD566\n\tIO_F19: inout bit; --  PAD573\n\tIO_F20: inout bit; --  PAD580\n\tIO_F21: inout bit; --  PAD601\n\tIO_F22: inout bit; --  PAD616\n\tIO_F24: inout bit; --  PAD650\n\tIO_F25: inout bit; --  PAD618\n\tIO_F26: inout bit; --  PAD646\n\tIO_F27: inout bit; --  PAD647\n\tIO_F29: inout bit; --  PAD644\n\tIO_F30: inout bit; --  PAD648\n\tIO_F31: inout bit; --  PAD649\n\tIO_F32: inout bit; --  PAD731\n\tIO_F34: inout bit; --  PAD734\n\tIO_F35: inout bit; --  PAD735\n\tIO_F36: inout bit; --  PAD732\n\tIO_F37: inout bit; --  PAD733\n\tIO_F39: inout bit; --  PAD742\n\tIO_F40: inout bit; --  PAD20\n\tIO_F41: inout bit; --  PAD21\n\tIO_F42: inout bit; --  PAD10\n\tIO_G12: inout bit; --  PAD520\n\tIO_G13: inout bit; --  PAD525\n\tIO_G14: inout bit; --  PAD524\n\tIO_G16: inout bit; --  PAD519\n\tIO_G17: inout bit; --  PAD587\n\tIO_G18: inout bit; --  PAD577\n\tIO_G19: inout bit; --  PAD572\n\tIO_G21: inout bit; --  PAD658\n\tIO_G22: inout bit; --  PAD659\n\tIO_G23: inout bit; --  PAD663\n\tIO_G24: inout bit; --  PAD653\n\tIO_G26: inout bit; --  PAD660\n\tIO_G27: inout bit; --  PAD661\n\tIO_G28: inout bit; --  PAD664\n\tIO_G29: inout bit; --  PAD665\n\tIO_G31: inout bit; --  PAD701\n\tIO_G32: inout bit; --  PAD730\n\tIO_G33: inout bit; --  PAD737\n\tIO_G34: inout bit; --  PAD750\n\tIO_G36: inout bit; --  PAD740\n\tIO_G37: inout bit; --  PAD741\n\tIO_G38: inout bit; --  PAD747\n\tIO_G39: inout bit; --  PAD17\n\tIO_G41: inout bit; --  PAD18\n\tIO_G42: inout bit; --  PAD19\n\tIO_H13: inout bit; --  PAD529\n\tIO_H14: inout bit; --  PAD527\n\tIO_H15: inout bit; --  PAD526\n\tIO_H16: inout bit; --  PAD518\n\tIO_H18: inout bit; --  PAD586\n\tIO_H19: inout bit; --  PAD576\n\tIO_H20: inout bit; --  PAD585\n\tIO_H21: inout bit; --  PAD655\n\tIO_H23: inout bit; --  PAD662\n\tIO_H24: inout bit; --  PAD652\n\tIO_H25: inout bit; --  PAD656\n\tIO_H26: inout bit; --  PAD657\n\tIO_H28: inout bit; --  PAD668\n\tIO_H29: inout bit; --  PAD669\n\tIO_H30: inout bit; --  PAD767\n\tIO_H31: inout bit; --  PAD771\n\tIO_H33: inout bit; --  PAD736\n\tIO_H34: inout bit; --  PAD762\n\tIO_H35: inout bit; --  PAD763\n\tIO_H36: inout bit; --  PAD749\n\tIO_H38: inout bit; --  PAD746\n\tIO_H39: inout bit; --  PAD16\n\tIO_H40: inout bit; --  PAD14\n\tIO_H41: inout bit; --  PAD15\n\tIO_J11: inout bit; --  PAD550\n\tIO_J12: inout bit; --  PAD531\n\tIO_J13: inout bit; --  PAD528\n\tIO_J15: inout bit; --  PAD533\n\tIO_J16: inout bit; --  PAD501\n\tIO_J17: inout bit; --  PAD583\n\tIO_J18: inout bit; --  PAD579\n\tIO_J20: inout bit; --  PAD584\n\tIO_J21: inout bit; --  PAD654\n\tIO_J22: inout bit; --  PAD685\n\tIO_J23: inout bit; --  PAD679\n\tIO_J25: inout bit; --  PAD674\n\tIO_J26: inout bit; --  PAD675\n\tIO_J27: inout bit; --  PAD671\n\tIO_J28: inout bit; --  PAD667\n\tIO_J30: inout bit; --  PAD766\n\tIO_J31: inout bit; --  PAD770\n\tIO_J32: inout bit; --  PAD754\n\tIO_J33: inout bit; --  PAD755\n\tIO_J35: inout bit; --  PAD753\n\tIO_J36: inout bit; --  PAD748\n\tIO_J37: inout bit; --  PAD744\n\tIO_J38: inout bit; --  PAD745\n\tIO_J40: inout bit; --  PAD22\n\tIO_J41: inout bit; --  PAD23\n\tIO_J42: inout bit; --  PAD31\n\tIO_K12: inout bit; --  PAD530\n\tIO_K13: inout bit; --  PAD535\n\tIO_K14: inout bit; --  PAD534\n\tIO_K15: inout bit; --  PAD532\n\tIO_K17: inout bit; --  PAD582\n\tIO_K18: inout bit; --  PAD551\n\tIO_K19: inout bit; --  PAD578\n\tIO_K20: inout bit; --  PAD600\n\tIO_K22: inout bit; --  PAD684\n\tIO_K23: inout bit; --  PAD678\n\tIO_K24: inout bit; --  PAD672\n\tIO_K25: inout bit; --  PAD673\n\tIO_K27: inout bit; --  PAD670\n\tIO_K28: inout bit; --  PAD666\n\tIO_K29: inout bit; --  PAD764\n\tIO_K30: inout bit; --  PAD765\n\tIO_K32: inout bit; --  PAD775\n\tIO_K33: inout bit; --  PAD756\n\tIO_K34: inout bit; --  PAD757\n\tIO_K35: inout bit; --  PAD752\n\tIO_K37: inout bit; --  PAD34\n\tIO_K38: inout bit; --  PAD35\n\tIO_K39: inout bit; --  PAD24\n\tIO_K40: inout bit; --  PAD25\n\tIO_K42: inout bit; --  PAD30\n\tIO_L11: inout bit; --  PAD539\n\tIO_L12: inout bit; --  PAD538\n\tIO_L14: inout bit; --  PAD541\n\tIO_L15: inout bit; --  PAD537\n\tIO_L16: inout bit; --  PAD536\n\tIO_L17: inout bit; --  PAD591\n\tIO_L19: inout bit; --  PAD599\n\tIO_L20: inout bit; --  PAD598\n\tIO_L21: inout bit; --  PAD687\n\tIO_L22: inout bit; --  PAD681\n\tIO_L24: inout bit; --  PAD677\n\tIO_L25: inout bit; --  PAD682\n\tIO_L26: inout bit; --  PAD683\n\tIO_L27: inout bit; --  PAD699\n\tIO_L29: inout bit; --  PAD768\n\tIO_L30: inout bit; --  PAD769\n\tIO_L31: inout bit; --  PAD774\n\tIO_L32: inout bit; --  PAD773\n\tIO_L34: inout bit; --  PAD758\n\tIO_L35: inout bit; --  PAD759\n\tIO_L36: inout bit; --  PAD1\n\tIO_L37: inout bit; --  PAD37\n\tIO_L39: inout bit; --  PAD26\n\tIO_L40: inout bit; --  PAD27\n\tIO_L41: inout bit; --  PAD29\n\tIO_L42: inout bit; --  PAD33\n\tIO_M11: inout bit; --  PAD549\n\tIO_M12: inout bit; --  PAD548\n\tIO_M13: inout bit; --  PAD545\n\tIO_M14: inout bit; --  PAD540\n\tIO_M16: inout bit; --  PAD543\n\tIO_M17: inout bit; --  PAD590\n\tIO_M18: inout bit; --  PAD595\n\tIO_M19: inout bit; --  PAD594\n\tIO_M21: inout bit; --  PAD686\n\tIO_M22: inout bit; --  PAD680\n\tIO_M23: inout bit; --  PAD651\n\tIO_M24: inout bit; --  PAD676\n\tIO_M26: inout bit; --  PAD700\n\tIO_M27: inout bit; --  PAD698\n\tIO_M28: inout bit; --  PAD780\n\tIO_M29: inout bit; --  PAD781\n\tIO_M31: inout bit; --  PAD777\n\tIO_M32: inout bit; --  PAD772\n\tIO_M33: inout bit; --  PAD760\n\tIO_M34: inout bit; --  PAD761\n\tIO_M36: inout bit; --  PAD36\n\tIO_M37: inout bit; --  PAD40\n\tIO_M38: inout bit; --  PAD41\n\tIO_M39: inout bit; --  PAD45\n\tIO_M41: inout bit; --  PAD28\n\tIO_M42: inout bit; --  PAD32\n\tIO_N13: inout bit; --  PAD544\n\tIO_N14: inout bit; --  PAD547\n\tIO_N15: inout bit; --  PAD546\n\tIO_N16: inout bit; --  PAD542\n\tIO_N18: inout bit; --  PAD593\n\tIO_N19: inout bit; --  PAD592\n\tIO_N20: inout bit; --  PAD597\n\tIO_N21: inout bit; --  PAD689\n\tIO_N23: inout bit; --  PAD696\n\tIO_N24: inout bit; --  PAD697\n\tIO_N25: inout bit; --  PAD694\n\tIO_N26: inout bit; --  PAD695\n\tIO_N28: inout bit; --  PAD784\n\tIO_N29: inout bit; --  PAD785\n\tIO_N30: inout bit; --  PAD776\n\tIO_N31: inout bit; --  PAD779\n\tIO_N33: inout bit; --  PAD54\n\tIO_N34: inout bit; --  PAD55\n\tIO_N35: inout bit; --  PAD51\n\tIO_N36: inout bit; --  PAD50\n\tIO_N38: inout bit; --  PAD44\n\tIO_N39: inout bit; --  PAD48\n\tIO_N40: inout bit; --  PAD49\n\tIO_N41: inout bit; --  PAD39\n\tIO_P17: inout bit; --  PAD589\n\tIO_P18: inout bit; --  PAD588\n\tIO_P20: inout bit; --  PAD596\n\tIO_P21: inout bit; --  PAD688\n\tIO_P22: inout bit; --  PAD692\n\tIO_P23: inout bit; --  PAD693\n\tIO_P25: inout bit; --  PAD690\n\tIO_P26: inout bit; --  PAD691\n\tIO_P28: inout bit; --  PAD783\n\tIO_P30: inout bit; --  PAD778\n\tIO_P31: inout bit; --  PAD787\n\tIO_P32: inout bit; --  PAD62\n\tIO_P33: inout bit; --  PAD63\n\tIO_P35: inout bit; --  PAD58\n\tIO_P36: inout bit; --  PAD59\n\tIO_P37: inout bit; --  PAD66\n\tIO_P38: inout bit; --  PAD67\n\tIO_P40: inout bit; --  PAD47\n\tIO_P41: inout bit; --  PAD38\n\tIO_P42: inout bit; --  PAD43\n\tIO_R28: inout bit; --  PAD782\n\tIO_R29: inout bit; --  PAD751\n\tIO_R30: inout bit; --  PAD786\n\tIO_R32: inout bit; --  PAD61\n\tIO_R33: inout bit; --  PAD56\n\tIO_R34: inout bit; --  PAD57\n\tIO_R35: inout bit; --  PAD53\n\tIO_R37: inout bit; --  PAD65\n\tIO_R38: inout bit; --  PAD70\n\tIO_R39: inout bit; --  PAD71\n\tIO_R40: inout bit; --  PAD46\n\tIO_R42: inout bit; --  PAD42\n\tIO_T29: inout bit; --  PAD792\n\tIO_T30: inout bit; --  PAD793\n\tIO_T31: inout bit; --  PAD789\n\tIO_T32: inout bit; --  PAD60\n\tIO_T34: inout bit; --  PAD52\n\tIO_T35: inout bit; --  PAD69\n\tIO_T36: inout bit; --  PAD64\n\tIO_T37: inout bit; --  PAD77\n\tIO_T39: inout bit; --  PAD75\n\tIO_T40: inout bit; --  PAD90\n\tIO_T41: inout bit; --  PAD91\n\tIO_T42: inout bit; --  PAD95\n\tIO_U28: inout bit; --  PAD800\n\tIO_U29: inout bit; --  PAD797\n\tIO_U31: inout bit; --  PAD788\n\tIO_U32: inout bit; --  PAD84\n\tIO_U33: inout bit; --  PAD85\n\tIO_U34: inout bit; --  PAD68\n\tIO_U36: inout bit; --  PAD76\n\tIO_U37: inout bit; --  PAD72\n\tIO_U38: inout bit; --  PAD73\n\tIO_U39: inout bit; --  PAD74\n\tIO_U41: inout bit; --  PAD94\n\tIO_U42: inout bit; --  PAD99\n\tIO_V29: inout bit; --  PAD796\n\tIO_V30: inout bit; --  PAD790\n\tIO_V31: inout bit; --  PAD791\n\tIO_V33: inout bit; --  PAD80\n\tIO_V34: inout bit; --  PAD81\n\tIO_V35: inout bit; --  PAD78\n\tIO_V36: inout bit; --  PAD79\n\tIO_V38: inout bit; --  PAD97\n\tIO_V39: inout bit; --  PAD88\n\tIO_V40: inout bit; --  PAD89\n\tIO_V41: inout bit; --  PAD98\n\tIO_W30: inout bit; --  PAD794\n\tIO_W31: inout bit; --  PAD795\n\tIO_W32: inout bit; --  PAD86\n\tIO_W33: inout bit; --  PAD87\n\tIO_W35: inout bit; --  PAD100\n\tIO_W36: inout bit; --  PAD82\n\tIO_W37: inout bit; --  PAD83\n\tIO_W38: inout bit; --  PAD96\n\tIO_W40: inout bit; --  PAD104\n\tIO_W41: inout bit; --  PAD92\n\tIO_W42: inout bit; --  PAD93\n\tIO_Y29: inout bit; --  PAD798\n\tIO_Y30: inout bit; --  PAD799\n\tIO_Y32: inout bit; --  PAD188\n\tIO_Y33: inout bit; --  PAD189\n\tIO_Y34: inout bit; --  PAD151\n\tIO_Y35: inout bit; --  PAD166\n\tIO_Y37: inout bit; --  PAD164\n\tIO_Y38: inout bit; --  PAD101\n\tIO_Y39: inout bit; --  PAD106\n\tIO_Y40: inout bit; --  PAD105\n\tIO_Y42: inout bit; --  PAD108\n\tIO_AA29: inout bit; --  PAD196\n\tIO_AA30: inout bit; --  PAD197\n\tIO_AA31: inout bit; --  PAD192\n\tIO_AA32: inout bit; --  PAD193\n\tIO_AA34: inout bit; --  PAD170\n\tIO_AA35: inout bit; --  PAD171\n\tIO_AA36: inout bit; --  PAD167\n\tIO_AA37: inout bit; --  PAD165\n\tIO_AA39: inout bit; --  PAD107\n\tIO_AA40: inout bit; --  PAD112\n\tIO_AA41: inout bit; --  PAD113\n\tIO_AA42: inout bit; --  PAD109\n\tIO_AB29: inout bit; --  PAD198\n\tIO_AB31: inout bit; --  PAD172\n\tIO_AB32: inout bit; --  PAD173\n\tIO_AB33: inout bit; --  PAD174\n\tIO_AB34: inout bit; --  PAD200\n\tIO_AB36: inout bit; --  PAD168\n\tIO_AB37: inout bit; --  PAD169\n\tIO_AB38: inout bit; --  PAD110\n\tIO_AB39: inout bit; --  PAD111\n\tIO_AB41: inout bit; --  PAD102\n\tIO_AB42: inout bit; --  PAD103\n\tIO_AC29: inout bit; --  PAD199\n\tIO_AC30: inout bit; --  PAD194\n\tIO_AC31: inout bit; --  PAD190\n\tIO_AC33: inout bit; --  PAD175\n\tIO_AC34: inout bit; --  PAD178\n\tIO_AC35: inout bit; --  PAD160\n\tIO_AC36: inout bit; --  PAD161\n\tIO_AC38: inout bit; --  PAD114\n\tIO_AC39: inout bit; --  PAD115\n\tIO_AC40: inout bit; --  PAD120\n\tIO_AC41: inout bit; --  PAD121\n\tIO_AD30: inout bit; --  PAD195\n\tIO_AD31: inout bit; --  PAD191\n\tIO_AD32: inout bit; --  PAD176\n\tIO_AD33: inout bit; --  PAD177\n\tIO_AD35: inout bit; --  PAD179\n\tIO_AD36: inout bit; --  PAD158\n\tIO_AD37: inout bit; --  PAD159\n\tIO_AD38: inout bit; --  PAD118\n\tIO_AD40: inout bit; --  PAD124\n\tIO_AD41: inout bit; --  PAD125\n\tIO_AD42: inout bit; --  PAD116\n\tIO_AE29: inout bit; --  PAD186\n\tIO_AE30: inout bit; --  PAD187\n\tIO_AE32: inout bit; --  PAD180\n\tIO_AE33: inout bit; --  PAD181\n\tIO_AE34: inout bit; --  PAD184\n\tIO_AE35: inout bit; --  PAD185\n\tIO_AE37: inout bit; --  PAD154\n\tIO_AE38: inout bit; --  PAD119\n\tIO_AE39: inout bit; --  PAD122\n\tIO_AE40: inout bit; --  PAD123\n\tIO_AE42: inout bit; --  PAD117\n\tIO_AF29: inout bit; --  PAD292\n\tIO_AF30: inout bit; --  PAD296\n\tIO_AF31: inout bit; --  PAD182\n\tIO_AF32: inout bit; --  PAD183\n\tIO_AF34: inout bit; --  PAD156\n\tIO_AF35: inout bit; --  PAD152\n\tIO_AF36: inout bit; --  PAD153\n\tIO_AF37: inout bit; --  PAD155\n\tIO_AF39: inout bit; --  PAD126\n\tIO_AF40: inout bit; --  PAD127\n\tIO_AF41: inout bit; --  PAD128\n\tIO_AF42: inout bit; --  PAD132\n\tIO_AG29: inout bit; --  PAD293\n\tIO_AG31: inout bit; --  PAD297\n\tIO_AG32: inout bit; --  PAD300\n\tIO_AG33: inout bit; --  PAD264\n\tIO_AG34: inout bit; --  PAD157\n\tIO_AG36: inout bit; --  PAD162\n\tIO_AG37: inout bit; --  PAD150\n\tIO_AG38: inout bit; --  PAD134\n\tIO_AG39: inout bit; --  PAD130\n\tIO_AG41: inout bit; --  PAD129\n\tIO_AG42: inout bit; --  PAD133\n\tIO_AH28: inout bit; --  PAD298\n\tIO_AH29: inout bit; --  PAD288\n\tIO_AH30: inout bit; --  PAD289\n\tIO_AH31: inout bit; --  PAD268\n\tIO_AH33: inout bit; --  PAD265\n\tIO_AH34: inout bit; --  PAD270\n\tIO_AH35: inout bit; --  PAD251\n\tIO_AH36: inout bit; --  PAD163\n\tIO_AH38: inout bit; --  PAD135\n\tIO_AH39: inout bit; --  PAD131\n\tIO_AH40: inout bit; --  PAD140\n\tIO_AH41: inout bit; --  PAD141\n\tIO_AJ12: inout bit; --  PAD909\n\tIO_AJ13: inout bit; --  PAD908\n\tIO_AJ15: inout bit; --  PAD903\n\tIO_AJ16: inout bit; --  PAD902\n\tIO_AJ17: inout bit; --  PAD863\n\tIO_AJ18: inout bit; --  PAD862\n\tIO_AJ20: inout bit; --  PAD811\n\tIO_AJ21: inout bit; --  PAD810\n\tIO_AJ22: inout bit; --  PAD806\n\tIO_AJ23: inout bit; --  PAD802\n\tIO_AJ25: inout bit; --  PAD398\n\tIO_AJ26: inout bit; --  PAD399\n\tIO_AJ28: inout bit; --  PAD299\n\tIO_AJ30: inout bit; --  PAD290\n\tIO_AJ31: inout bit; --  PAD269\n\tIO_AJ32: inout bit; --  PAD276\n\tIO_AJ33: inout bit; --  PAD272\n\tIO_AJ35: inout bit; --  PAD271\n\tIO_AJ36: inout bit; --  PAD254\n\tIO_AJ37: inout bit; --  PAD255\n\tIO_AJ38: inout bit; --  PAD136\n\tIO_AJ40: inout bit; --  PAD144\n\tIO_AJ41: inout bit; --  PAD145\n\tIO_AJ42: inout bit; --  PAD148\n\tIO_AK12: inout bit; --  PAD912\n\tIO_AK13: inout bit; --  PAD905\n\tIO_AK14: inout bit; --  PAD904\n\tIO_AK15: inout bit; --  PAD906\n\tIO_AK17: inout bit; --  PAD854\n\tIO_AK18: inout bit; --  PAD859\n\tIO_AK19: inout bit; --  PAD858\n\tIO_AK20: inout bit; --  PAD804\n\tIO_AK22: inout bit; --  PAD807\n\tIO_AK23: inout bit; --  PAD803\n\tIO_AK24: inout bit; --  PAD394\n\tIO_AK25: inout bit; --  PAD395\n\tIO_AK27: inout bit; --  PAD390\n\tIO_AK28: inout bit; --  PAD294\n\tIO_AK29: inout bit; --  PAD295\n\tIO_AK30: inout bit; --  PAD291\n\tIO_AK32: inout bit; --  PAD277\n\tIO_AK33: inout bit; --  PAD273\n\tIO_AK34: inout bit; --  PAD274\n\tIO_AK35: inout bit; --  PAD266\n\tIO_AK37: inout bit; --  PAD258\n\tIO_AK38: inout bit; --  PAD137\n\tIO_AK39: inout bit; --  PAD146\n\tIO_AK40: inout bit; --  PAD138\n\tIO_AK42: inout bit; --  PAD149\n\tIO_AL12: inout bit; --  PAD913\n\tIO_AL14: inout bit; --  PAD907\n\tIO_AL15: inout bit; --  PAD911\n\tIO_AL16: inout bit; --  PAD910\n\tIO_AL17: inout bit; --  PAD855\n\tIO_AL19: inout bit; --  PAD852\n\tIO_AL20: inout bit; --  PAD805\n\tIO_AL21: inout bit; --  PAD808\n\tIO_AL22: inout bit; --  PAD812\n\tIO_AL24: inout bit; --  PAD801\n\tIO_AL25: inout bit; --  PAD396\n\tIO_AL26: inout bit; --  PAD397\n\tIO_AL27: inout bit; --  PAD391\n\tIO_AL29: inout bit; --  PAD286\n\tIO_AL30: inout bit; --  PAD287\n\tIO_AL31: inout bit; --  PAD278\n\tIO_AL32: inout bit; --  PAD279\n\tIO_AL34: inout bit; --  PAD275\n\tIO_AL35: inout bit; --  PAD267\n\tIO_AL36: inout bit; --  PAD262\n\tIO_AL37: inout bit; --  PAD259\n\tIO_AL39: inout bit; --  PAD147\n\tIO_AL40: inout bit; --  PAD139\n\tIO_AL41: inout bit; --  PAD142\n\tIO_AL42: inout bit; --  PAD143\n\tIO_AM11: inout bit; --  PAD917\n\tIO_AM12: inout bit; --  PAD916\n\tIO_AM13: inout bit; --  PAD914\n\tIO_AM14: inout bit; --  PAD901\n\tIO_AM16: inout bit; --  PAD860\n\tIO_AM17: inout bit; --  PAD857\n\tIO_AM18: inout bit; --  PAD856\n\tIO_AM19: inout bit; --  PAD853\n\tIO_AM21: inout bit; --  PAD809\n\tIO_AM22: inout bit; --  PAD813\n\tIO_AM23: inout bit; --  PAD816\n\tIO_AM24: inout bit; --  PAD814\n\tIO_AM26: inout bit; --  PAD392\n\tIO_AM27: inout bit; --  PAD393\n\tIO_AM28: inout bit; --  PAD388\n\tIO_AM29: inout bit; --  PAD389\n\tIO_AM31: inout bit; --  PAD282\n\tIO_AM32: inout bit; --  PAD283\n\tIO_AM33: inout bit; --  PAD284\n\tIO_AM34: inout bit; --  PAD280\n\tIO_AM36: inout bit; --  PAD252\n\tIO_AM37: inout bit; --  PAD263\n\tIO_AM38: inout bit; --  PAD201\n\tIO_AM39: inout bit; --  PAD212\n\tIO_AM41: inout bit; --  PAD204\n\tIO_AM42: inout bit; --  PAD205\n\tIO_AN11: inout bit; --  PAD920\n\tIO_AN13: inout bit; --  PAD915\n\tIO_AN14: inout bit; --  PAD919\n\tIO_AN15: inout bit; --  PAD918\n\tIO_AN16: inout bit; --  PAD861\n\tIO_AN18: inout bit; --  PAD869\n\tIO_AN19: inout bit; --  PAD868\n\tIO_AN20: inout bit; --  PAD850\n\tIO_AN21: inout bit; --  PAD820\n\tIO_AN23: inout bit; --  PAD817\n\tIO_AN24: inout bit; --  PAD815\n\tIO_AN25: inout bit; --  PAD386\n\tIO_AN26: inout bit; --  PAD387\n\tIO_AN28: inout bit; --  PAD380\n\tIO_AN29: inout bit; --  PAD351\n\tIO_AN30: inout bit; --  PAD342\n\tIO_AN31: inout bit; --  PAD346\n\tIO_AN33: inout bit; --  PAD285\n\tIO_AN34: inout bit; --  PAD281\n\tIO_AN35: inout bit; --  PAD260\n\tIO_AN36: inout bit; --  PAD253\n\tIO_AN38: inout bit; --  PAD202\n\tIO_AN39: inout bit; --  PAD213\n\tIO_AN40: inout bit; --  PAD208\n\tIO_AN41: inout bit; --  PAD209\n\tIO_AP11: inout bit; --  PAD921\n\tIO_AP12: inout bit; --  PAD930\n\tIO_AP13: inout bit; --  PAD924\n\tIO_AP15: inout bit; --  PAD950\n\tIO_AP16: inout bit; --  PAD900\n\tIO_AP17: inout bit; --  PAD865\n\tIO_AP18: inout bit; --  PAD864\n\tIO_AP20: inout bit; --  PAD866\n\tIO_AP21: inout bit; --  PAD821\n\tIO_AP22: inout bit; --  PAD819\n\tIO_AP23: inout bit; --  PAD818\n\tIO_AP25: inout bit; --  PAD384\n\tIO_AP26: inout bit; --  PAD400\n\tIO_AP27: inout bit; --  PAD378\n\tIO_AP28: inout bit; --  PAD381\n\tIO_AP30: inout bit; --  PAD343\n\tIO_AP31: inout bit; --  PAD347\n\tIO_AP32: inout bit; --  PAD344\n\tIO_AP33: inout bit; --  PAD348\n\tIO_AP35: inout bit; --  PAD261\n\tIO_AP36: inout bit; --  PAD256\n\tIO_AP37: inout bit; --  PAD257\n\tIO_AP38: inout bit; --  PAD203\n\tIO_AP40: inout bit; --  PAD214\n\tIO_AP41: inout bit; --  PAD216\n\tIO_AP42: inout bit; --  PAD217\n\tIO_AR12: inout bit; --  PAD931\n\tIO_AR13: inout bit; --  PAD925\n\tIO_AR14: inout bit; --  PAD922\n\tIO_AR15: inout bit; --  PAD932\n\tIO_AR17: inout bit; --  PAD871\n\tIO_AR18: inout bit; --  PAD870\n\tIO_AR19: inout bit; --  PAD867\n\tIO_AR20: inout bit; --  PAD851\n\tIO_AR22: inout bit; --  PAD823\n\tIO_AR23: inout bit; --  PAD822\n\tIO_AR24: inout bit; --  PAD832\n\tIO_AR25: inout bit; --  PAD385\n\tIO_AR27: inout bit; --  PAD376\n\tIO_AR28: inout bit; --  PAD379\n\tIO_AR29: inout bit; --  PAD366\n\tIO_AR30: inout bit; --  PAD338\n\tIO_AR32: inout bit; --  PAD345\n\tIO_AR33: inout bit; --  PAD349\n\tIO_AR34: inout bit; --  PAD320\n\tIO_AR35: inout bit; --  PAD301\n\tIO_AR37: inout bit; --  PAD210\n\tIO_AR38: inout bit; --  PAD206\n\tIO_AR39: inout bit; --  PAD207\n\tIO_AR40: inout bit; --  PAD215\n\tIO_AR42: inout bit; --  PAD220\n\tIO_AT12: inout bit; --  PAD934\n\tIO_AT14: inout bit; --  PAD923\n\tIO_AT15: inout bit; --  PAD933\n\tIO_AT16: inout bit; --  PAD886\n\tIO_AT17: inout bit; --  PAD874\n\tIO_AT19: inout bit; --  PAD883\n\tIO_AT20: inout bit; --  PAD882\n\tIO_AT21: inout bit; --  PAD830\n\tIO_AT22: inout bit; --  PAD824\n\tIO_AT24: inout bit; --  PAD833\n\tIO_AT25: inout bit; --  PAD382\n\tIO_AT26: inout bit; --  PAD383\n\tIO_AT27: inout bit; --  PAD377\n\tIO_AT29: inout bit; --  PAD367\n\tIO_AT30: inout bit; --  PAD339\n\tIO_AT31: inout bit; --  PAD350\n\tIO_AT32: inout bit; --  PAD318\n\tIO_AT34: inout bit; --  PAD314\n\tIO_AT35: inout bit; --  PAD321\n\tIO_AT36: inout bit; --  PAD316\n\tIO_AT37: inout bit; --  PAD211\n\tIO_AT39: inout bit; --  PAD218\n\tIO_AT40: inout bit; --  PAD219\n\tIO_AT41: inout bit; --  PAD240\n\tIO_AT42: inout bit; --  PAD221\n\tIO_AU12: inout bit; --  PAD935\n\tIO_AU13: inout bit; --  PAD927\n\tIO_AU14: inout bit; --  PAD926\n\tIO_AU16: inout bit; --  PAD887\n\tIO_AU17: inout bit; --  PAD875\n\tIO_AU18: inout bit; --  PAD872\n\tIO_AU19: inout bit; --  PAD880\n\tIO_AU21: inout bit; --  PAD831\n\tIO_AU22: inout bit; --  PAD825\n\tIO_AU23: inout bit; --  PAD826\n\tIO_AU24: inout bit; --  PAD836\n\tIO_AU26: inout bit; --  PAD374\n\tIO_AU27: inout bit; --  PAD375\n\tIO_AU28: inout bit; --  PAD372\n\tIO_AU29: inout bit; --  PAD354\n\tIO_AU31: inout bit; --  PAD340\n\tIO_AU32: inout bit; --  PAD322\n\tIO_AU33: inout bit; --  PAD319\n\tIO_AU34: inout bit; --  PAD315\n\tIO_AU36: inout bit; --  PAD317\n\tIO_AU37: inout bit; --  PAD250\n\tIO_AU38: inout bit; --  PAD224\n\tIO_AU39: inout bit; --  PAD222\n\tIO_AU41: inout bit; --  PAD244\n\tIO_AU42: inout bit; --  PAD241\n\tIO_AV13: inout bit; --  PAD928\n\tIO_AV14: inout bit; --  PAD937\n\tIO_AV15: inout bit; --  PAD936\n\tIO_AV16: inout bit; --  PAD884\n\tIO_AV18: inout bit; --  PAD873\n\tIO_AV19: inout bit; --  PAD881\n\tIO_AV20: inout bit; --  PAD890\n\tIO_AV21: inout bit; --  PAD834\n\tIO_AV23: inout bit; --  PAD827\n\tIO_AV24: inout bit; --  PAD837\n\tIO_AV25: inout bit; --  PAD368\n\tIO_AV26: inout bit; --  PAD369\n\tIO_AV28: inout bit; --  PAD373\n\tIO_AV29: inout bit; --  PAD355\n\tIO_AV30: inout bit; --  PAD336\n\tIO_AV31: inout bit; --  PAD341\n\tIO_AV33: inout bit; --  PAD323\n\tIO_AV34: inout bit; --  PAD326\n\tIO_AV35: inout bit; --  PAD327\n\tIO_AV36: inout bit; --  PAD304\n\tIO_AV38: inout bit; --  PAD225\n\tIO_AV39: inout bit; --  PAD223\n\tIO_AV40: inout bit; --  PAD226\n\tIO_AV41: inout bit; --  PAD245\n\tIO_AW12: inout bit; --  PAD940\n\tIO_AW13: inout bit; --  PAD929\n\tIO_AW15: inout bit; --  PAD938\n\tIO_AW16: inout bit; --  PAD885\n\tIO_AW17: inout bit; --  PAD879\n\tIO_AW18: inout bit; --  PAD878\n\tIO_AW20: inout bit; --  PAD891\n\tIO_AW21: inout bit; --  PAD835\n\tIO_AW22: inout bit; --  PAD829\n\tIO_AW23: inout bit; --  PAD828\n\tIO_AW25: inout bit; --  PAD364\n\tIO_AW26: inout bit; --  PAD365\n\tIO_AW27: inout bit; --  PAD370\n\tIO_AW28: inout bit; --  PAD371\n\tIO_AW30: inout bit; --  PAD332\n\tIO_AW31: inout bit; --  PAD337\n\tIO_AW32: inout bit; --  PAD324\n\tIO_AW33: inout bit; --  PAD325\n\tIO_AW35: inout bit; --  PAD312\n\tIO_AW36: inout bit; --  PAD305\n\tIO_AW37: inout bit; --  PAD230\n\tIO_AW38: inout bit; --  PAD234\n\tIO_AW40: inout bit; --  PAD227\n\tIO_AW41: inout bit; --  PAD248\n\tIO_AW42: inout bit; --  PAD249\n\tIO_AY12: inout bit; --  PAD941\n\tIO_AY13: inout bit; --  PAD945\n\tIO_AY14: inout bit; --  PAD944\n\tIO_AY15: inout bit; --  PAD939\n\tIO_AY17: inout bit; --  PAD877\n\tIO_AY18: inout bit; --  PAD876\n\tIO_AY19: inout bit; --  PAD898\n\tIO_AY20: inout bit; --  PAD894\n\tIO_AY22: inout bit; --  PAD839\n\tIO_AY23: inout bit; --  PAD838\n\tIO_AY24: inout bit; --  PAD844\n\tIO_AY25: inout bit; --  PAD840\n\tIO_AY27: inout bit; --  PAD352\n\tIO_AY28: inout bit; --  PAD353\n\tIO_AY29: inout bit; --  PAD362\n\tIO_AY30: inout bit; --  PAD333\n\tIO_AY32: inout bit; --  PAD328\n\tIO_AY33: inout bit; --  PAD329\n\tIO_AY34: inout bit; --  PAD302\n\tIO_AY35: inout bit; --  PAD313\n\tIO_AY37: inout bit; --  PAD231\n\tIO_AY38: inout bit; --  PAD235\n\tIO_AY39: inout bit; --  PAD228\n\tIO_AY40: inout bit; --  PAD229\n\tIO_AY42: inout bit; --  PAD242\n\tIO_BA12: inout bit; --  PAD948\n\tIO_BA14: inout bit; --  PAD943\n\tIO_BA15: inout bit; --  PAD942\n\tIO_BA16: inout bit; --  PAD896\n\tIO_BA17: inout bit; --  PAD892\n\tIO_BA19: inout bit; --  PAD899\n\tIO_BA20: inout bit; --  PAD895\n\tIO_BA21: inout bit; --  PAD846\n\tIO_BA22: inout bit; --  PAD842\n\tIO_BA24: inout bit; --  PAD845\n\tIO_BA25: inout bit; --  PAD841\n\tIO_BA26: inout bit; --  PAD356\n\tIO_BA27: inout bit; --  PAD357\n\tIO_BA29: inout bit; --  PAD363\n\tIO_BA30: inout bit; --  PAD334\n\tIO_BA31: inout bit; --  PAD330\n\tIO_BA32: inout bit; --  PAD331\n\tIO_BA34: inout bit; --  PAD306\n\tIO_BA35: inout bit; --  PAD303\n\tIO_BA36: inout bit; --  PAD308\n\tIO_BA37: inout bit; --  PAD232\n\tIO_BA39: inout bit; --  PAD238\n\tIO_BA40: inout bit; --  PAD239\n\tIO_BA41: inout bit; --  PAD246\n\tIO_BA42: inout bit; --  PAD243\n\tIO_BB12: inout bit; --  PAD949\n\tIO_BB13: inout bit; --  PAD947\n\tIO_BB14: inout bit; --  PAD946\n\tIO_BB16: inout bit; --  PAD897\n\tIO_BB17: inout bit; --  PAD893\n\tIO_BB18: inout bit; --  PAD889\n\tIO_BB19: inout bit; --  PAD888\n\tIO_BB21: inout bit; --  PAD847\n\tIO_BB22: inout bit; --  PAD843\n\tIO_BB23: inout bit; --  PAD849\n\tIO_BB24: inout bit; --  PAD848\n\tIO_BB26: inout bit; --  PAD360\n\tIO_BB27: inout bit; --  PAD361\n\tIO_BB28: inout bit; --  PAD358\n\tIO_BB29: inout bit; --  PAD359\n\tIO_BB31: inout bit; --  PAD335\n\tIO_BB32: inout bit; --  PAD310\n\tIO_BB33: inout bit; --  PAD311\n\tIO_BB34: inout bit; --  PAD307\n\tIO_BB36: inout bit; --  PAD309\n\tIO_BB37: inout bit; --  PAD233\n\tIO_BB38: inout bit; --  PAD236\n\tIO_BB39: inout bit; --  PAD237\n\tIO_BB41: inout bit --  PAD247\n); --end port list\n\n-- Use Statements\n\nuse STD_1149_1_2001.all;\nuse STD_1149_6_2003.all;\n\n-- Component Conformance Statement(s)\n\nattribute COMPONENT_CONFORMANCE of XC7VX690T_FFG1761 : entity is\n\t\"STD_1149_1_2001\";\n\n-- Device Package Pin Mappings\n\nattribute PIN_MAP of XC7VX690T_FFG1761 : entity is PHYSICAL_PIN_MAP;\n\nconstant FFG1761: PIN_MAP_STRING:=\n\t\"CCLK_N10:N10,\" &\n\t\"CFGBVS_AH10:AH10,\" &\n\t\"DONE_AL11:AL11,\" &\n\t\"GND:(A2,A3,A4,A7,A8,A11,A13,A18,A28,A38,\" &\n\t\t\"B1,B2,B5,B9,B10,B12,B13,B15,B25,B35,\" &\n\t\t\"C3,C7,C11,C12,C22,C32,C42,D1,D2,D5,\" &\n\t\t\"D9,D10,D11,D19,D29,D39,E3,E7,E11,E16,\" &\n\t\t\"E26,E36,F1,F2,F5,F9,F10,F11,F13,F23,\" &\n\t\t\"F33,G3,G7,G11,G20,G30,G40,H1,H2,H5,\" &\n\t\t\"H9,H10,H11,H17,H27,H37,J3,J7,J9,J10,\" &\n\t\t\"J14,J24,J34,K1,K2,K5,K6,K9,K10,K11,\" &\n\t\t\"K21,K31,K41,L3,L7,L9,L10,L18,L28,L38,\" &\n\t\t\"M1,M2,M5,M6,M9,M15,M25,M35,N3,N7,\" &\n\t\t\"N9,N12,N22,N32,N42,P1,P2,P5,P9,P12,\" &\n\t\t\"P16,P19,P29,P39,R3,R7,R9,R11,R13,R15,\" &\n\t\t\"R17,R19,R21,R23,R25,R27,R36,T1,T2,T5,\" &\n\t\t\"T6,T9,T12,T14,T16,T18,T20,T22,T24,T26,\" &\n\t\t\"T33,U3,U4,U7,U9,U10,U11,U13,U15,U17,\" &\n\t\t\"U19,U21,U23,U25,U27,U30,U40,V1,V2,V5,\" &\n\t\t\"V6,V9,V10,V12,V14,V16,V18,V20,V22,V24,\" &\n\t\t\"V26,V28,V37,W3,W7,W11,W13,W15,W17,W19,\" &\n\t\t\"W21,W23,W25,W27,W34,Y1,Y2,Y5,Y6,Y9,\" &\n\t\t\"Y10,Y12,Y14,Y16,Y18,Y22,Y24,Y26,Y28,Y31,\" &\n\t\t\"Y41,AA3,AA7,AA9,AA11,AA13,AA15,AA17,AA19,AA23,\" &\n\t\t\"AA25,AA27,AA38,AB1,AB2,AB5,AB6,AB9,AB10,AB12,\" &\n\t\t\"AB14,AB16,AB18,AB22,AB24,AB26,AB28,AB35,AC3,AC7,\" &\n\t\t\"AC11,AC13,AC15,AC17,AC19,AC23,AC25,AC27,AC32,AC42,\" &\n\t\t\"AD1,AD2,AD5,AD6,AD9,AD10,AD12,AD14,AD16,AD18,\" &\n\t\t\"AD20,AD22,AD24,AD26,AD28,AD29,AD39,AE3,AE7,AE9,\" &\n\t\t\"AE11,AE13,AE15,AE17,AE19,AE21,AE23,AE25,AE27,AE36,\" &\n\t\t\"AF1,AF2,AF5,AF6,AF9,AF10,AF12,AF14,AF16,AF18,\" &\n\t\t\"AF20,AF22,AF24,AF26,AF33,AG3,AG4,AG7,AG8,AG9,\" &\n\t\t\"AG10,AG13,AG15,AG17,AG19,AG21,AG23,AG25,AG27,AG30,\" &\n\t\t\"AG40,AH1,AH2,AH5,AH6,AH9,AH12,AH14,AH16,AH17,\" &\n\t\t\"AH18,AH20,AH22,AH24,AH26,AH37,AJ3,AJ7,AJ9,AJ14,\" &\n\t\t\"AJ24,AJ27,AJ34,AK1,AK2,AK5,AK6,AK9,AK11,AK21,\" &\n\t\t\"AK31,AK41,AL3,AL7,AL9,AL18,AL28,AL38,AM1,AM2,\" &\n\t\t\"AM5,AM9,AM10,AM15,AM25,AM35,AN3,AN7,AN9,AN10,\" &\n\t\t\"AN12,AN22,AN32,AN42,AP1,AP2,AP5,AP9,AP10,AP19,\" &\n\t\t\"AP29,AP39,AR3,AR7,AR9,AR10,AR16,AR26,AR36,AT1,\" &\n\t\t\"AT2,AT5,AT6,AT9,AT10,AT11,AT13,AT23,AT33,AU3,\" &\n\t\t\"AU7,AU11,AU20,AU30,AU40,AV1,AV2,AV5,AV9,AV10,\" &\n\t\t\"AV11,AV17,AV27,AV37,AW3,AW7,AW11,AW14,AW24,AW34,\" &\n\t\t\"AY1,AY2,AY5,AY9,AY10,AY11,AY21,AY31,AY41,BA3,\" &\n\t\t\"BA7,BA11,BA18,BA28,BA38,BB2,BB5,BB6,BB9,BB10,\" &\n\t\t\"BB11,BB15,BB25,BB35),\" &\n\t\"GNDADC_0:Y20,\" &\n\t\"INIT_B_AG11:AG11,\" &\n\t\"M0_AL10:AL10,\" &\n\t\"M1_AK10:AK10,\" &\n\t\"M2_AJ10:AJ10,\" &\n\t\"MGTAVCC_G10:(W8,AA8,AC8,AE8,AJ8,AL8,AN8,AR8,AU8,AW8,\" &\n\t\t\"BA8),\" &\n\t\"MGTAVCC_G11:(C8,E8,G8,J8,L8),\" &\n\t\"MGTAVTTRCAL_115:A12,\" &\n\t\"MGTAVTT_G10:(R4,W4,AA4,AC4,AE4,AJ4,AL4,AM6,AN4,AP6,\" &\n\t\t\"AR4,AU4,AV6,AW4,AY6,BA4),\" &\n\t\"MGTAVTT_G11:(B6,C4,D6,E4,F6,G4,H6,J4,L4,N4,\" &\n\t\t\"P6),\" &\n\t\"MGTHRXN0_111:BB7,\" &\n\t\"MGTHRXN0_112:AV7,\" &\n\t\"MGTHRXN0_113:AN5,\" &\n\t\"MGTHRXN0_114:AG5,\" &\n\t\"MGTHRXN0_115:AC5,\" &\n\t\"MGTHRXN0_116:W5,\" &\n\t\"MGTHRXN0_117:P7,\" &\n\t\"MGTHRXN0_118:H7,\" &\n\t\"MGTHRXN0_119:D7,\" &\n\t\"MGTHRXN1_111:BA5,\" &\n\t\"MGTHRXN1_112:AU5,\" &\n\t\"MGTHRXN1_113:AM7,\" &\n\t\"MGTHRXN1_114:AF3,\" &\n\t\"MGTHRXN1_115:AB3,\" &\n\t\"MGTHRXN1_116:V3,\" &\n\t\"MGTHRXN1_117:N5,\" &\n\t\"MGTHRXN1_118:G5,\" &\n\t\"MGTHRXN1_119:C5,\" &\n\t\"MGTHRXN2_111:AY7,\" &\n\t\"MGTHRXN2_112:AR5,\" &\n\t\"MGTHRXN2_113:AL5,\" &\n\t\"MGTHRXN2_114:AE5,\" &\n\t\"MGTHRXN2_115:AA5,\" &\n\t\"MGTHRXN2_116:U5,\" &\n\t\"MGTHRXN2_117:L5,\" &\n\t\"MGTHRXN2_118:F7,\" &\n\t\"MGTHRXN2_119:B7,\" &\n\t\"MGTHRXN3_111:AW5,\" &\n\t\"MGTHRXN3_112:AP7,\" &\n\t\"MGTHRXN3_113:AJ5,\" &\n\t\"MGTHRXN3_114:AD3,\" &\n\t\"MGTHRXN3_115:Y3,\" &\n\t\"MGTHRXN3_116:R5,\" &\n\t\"MGTHRXN3_117:J5,\" &\n\t\"MGTHRXN3_118:E5,\" &\n\t\"MGTHRXN3_119:A5,\" &\n\t\"MGTHRXP0_111:BB8,\" &\n\t\"MGTHRXP0_112:AV8,\" &\n\t\"MGTHRXP0_113:AN6,\" &\n\t\"MGTHRXP0_114:AG6,\" &\n\t\"MGTHRXP0_115:AC6,\" &\n\t\"MGTHRXP0_116:W6,\" &\n\t\"MGTHRXP0_117:P8,\" &\n\t\"MGTHRXP0_118:H8,\" &\n\t\"MGTHRXP0_119:D8,\" &\n\t\"MGTHRXP1_111:BA6,\" &\n\t\"MGTHRXP1_112:AU6,\" &\n\t\"MGTHRXP1_113:AM8,\" &\n\t\"MGTHRXP1_114:AF4,\" &\n\t\"MGTHRXP1_115:AB4,\" &\n\t\"MGTHRXP1_116:V4,\" &\n\t\"MGTHRXP1_117:N6,\" &\n\t\"MGTHRXP1_118:G6,\" &\n\t\"MGTHRXP1_119:C6,\" &\n\t\"MGTHRXP2_111:AY8,\" &\n\t\"MGTHRXP2_112:AR6,\" &\n\t\"MGTHRXP2_113:AL6,\" &\n\t\"MGTHRXP2_114:AE6,\" &\n\t\"MGTHRXP2_115:AA6,\" &\n\t\"MGTHRXP2_116:U6,\" &\n\t\"MGTHRXP2_117:L6,\" &\n\t\"MGTHRXP2_118:F8,\" &\n\t\"MGTHRXP2_119:B8,\" &\n\t\"MGTHRXP3_111:AW6,\" &\n\t\"MGTHRXP3_112:AP8,\" &\n\t\"MGTHRXP3_113:AJ6,\" &\n\t\"MGTHRXP3_114:AD4,\" &\n\t\"MGTHRXP3_115:Y4,\" &\n\t\"MGTHRXP3_116:R6,\" &\n\t\"MGTHRXP3_117:J6,\" &\n\t\"MGTHRXP3_118:E6,\" &\n\t\"MGTHRXP3_119:A6,\" &\n\t\"MGTHTXN0_111:BB3,\" &\n\t\"MGTHTXN0_112:AV3,\" &\n\t\"MGTHTXN0_113:AP3,\" &\n\t\"MGTHTXN0_114:AK3,\" &\n\t\"MGTHTXN0_115:AE1,\" &\n\t\"MGTHTXN0_116:U1,\" &\n\t\"MGTHTXN0_117:N1,\" &\n\t\"MGTHTXN0_118:J1,\" &\n\t\"MGTHTXN0_119:E1,\" &\n\t\"MGTHTXN1_111:BA1,\" &\n\t\"MGTHTXN1_112:AU1,\" &\n\t\"MGTHTXN1_113:AN1,\" &\n\t\"MGTHTXN1_114:AJ1,\" &\n\t\"MGTHTXN1_115:AC1,\" &\n\t\"MGTHTXN1_116:T3,\" &\n\t\"MGTHTXN1_117:M3,\" &\n\t\"MGTHTXN1_118:H3,\" &\n\t\"MGTHTXN1_119:D3,\" &\n\t\"MGTHTXN2_111:AY3,\" &\n\t\"MGTHTXN2_112:AT3,\" &\n\t\"MGTHTXN2_113:AM3,\" &\n\t\"MGTHTXN2_114:AH3,\" &\n\t\"MGTHTXN2_115:AA1,\" &\n\t\"MGTHTXN2_116:R1,\" &\n\t\"MGTHTXN2_117:L1,\" &\n\t\"MGTHTXN2_118:G1,\" &\n\t\"MGTHTXN2_119:C1,\" &\n\t\"MGTHTXN3_111:AW1,\" &\n\t\"MGTHTXN3_112:AR1,\" &\n\t\"MGTHTXN3_113:AL1,\" &\n\t\"MGTHTXN3_114:AG1,\" &\n\t\"MGTHTXN3_115:W1,\" &\n\t\"MGTHTXN3_116:P3,\" &\n\t\"MGTHTXN3_117:K3,\" &\n\t\"MGTHTXN3_118:F3,\" &\n\t\"MGTHTXN3_119:B3,\" &\n\t\"MGTHTXP0_111:BB4,\" &\n\t\"MGTHTXP0_112:AV4,\" &\n\t\"MGTHTXP0_113:AP4,\" &\n\t\"MGTHTXP0_114:AK4,\" &\n\t\"MGTHTXP0_115:AE2,\" &\n\t\"MGTHTXP0_116:U2,\" &\n\t\"MGTHTXP0_117:N2,\" &\n\t\"MGTHTXP0_118:J2,\" &\n\t\"MGTHTXP0_119:E2,\" &\n\t\"MGTHTXP1_111:BA2,\" &\n\t\"MGTHTXP1_112:AU2,\" &\n\t\"MGTHTXP1_113:AN2,\" &\n\t\"MGTHTXP1_114:AJ2,\" &\n\t\"MGTHTXP1_115:AC2,\" &\n\t\"MGTHTXP1_116:T4,\" &\n\t\"MGTHTXP1_117:M4,\" &\n\t\"MGTHTXP1_118:H4,\" &\n\t\"MGTHTXP1_119:D4,\" &\n\t\"MGTHTXP2_111:AY4,\" &\n\t\"MGTHTXP2_112:AT4,\" &\n\t\"MGTHTXP2_113:AM4,\" &\n\t\"MGTHTXP2_114:AH4,\" &\n\t\"MGTHTXP2_115:AA2,\" &\n\t\"MGTHTXP2_116:R2,\" &\n\t\"MGTHTXP2_117:L2,\" &\n\t\"MGTHTXP2_118:G2,\" &\n\t\"MGTHTXP2_119:C2,\" &\n\t\"MGTHTXP3_111:AW2,\" &\n\t\"MGTHTXP3_112:AR2,\" &\n\t\"MGTHTXP3_113:AL2,\" &\n\t\"MGTHTXP3_114:AG2,\" &\n\t\"MGTHTXP3_115:W2,\" &\n\t\"MGTHTXP3_116:P4,\" &\n\t\"MGTHTXP3_117:K4,\" &\n\t\"MGTHTXP3_118:F4,\" &\n\t\"MGTHTXP3_119:B4,\" &\n\t\"MGTREFCLK0N_111:AW9,\" &\n\t\"MGTREFCLK0N_112:AT7,\" &\n\t\"MGTREFCLK0N_113:AH7,\" &\n\t\"MGTREFCLK0N_114:AD7,\" &\n\t\"MGTREFCLK0N_115:Y7,\" &\n\t\"MGTREFCLK0N_116:T7,\" &\n\t\"MGTREFCLK0N_117:K7,\" &\n\t\"MGTREFCLK0N_118:E9,\" &\n\t\"MGTREFCLK0N_119:A9,\" &\n\t\"MGTREFCLK0P_111:AW10,\" &\n\t\"MGTREFCLK0P_112:AT8,\" &\n\t\"MGTREFCLK0P_113:AH8,\" &\n\t\"MGTREFCLK0P_114:AD8,\" &\n\t\"MGTREFCLK0P_115:Y8,\" &\n\t\"MGTREFCLK0P_116:T8,\" &\n\t\"MGTREFCLK0P_117:K8,\" &\n\t\"MGTREFCLK0P_118:E10,\" &\n\t\"MGTREFCLK0P_119:A10,\" &\n\t\"MGTREFCLK1N_111:BA9,\" &\n\t\"MGTREFCLK1N_112:AU9,\" &\n\t\"MGTREFCLK1N_113:AK7,\" &\n\t\"MGTREFCLK1N_114:AF7,\" &\n\t\"MGTREFCLK1N_115:AB7,\" &\n\t\"MGTREFCLK1N_116:V7,\" &\n\t\"MGTREFCLK1N_117:M7,\" &\n\t\"MGTREFCLK1N_118:G9,\" &\n\t\"MGTREFCLK1N_119:C9,\" &\n\t\"MGTREFCLK1P_111:BA10,\" &\n\t\"MGTREFCLK1P_112:AU10,\" &\n\t\"MGTREFCLK1P_113:AK8,\" &\n\t\"MGTREFCLK1P_114:AF8,\" &\n\t\"MGTREFCLK1P_115:AB8,\" &\n\t\"MGTREFCLK1P_116:V8,\" &\n\t\"MGTREFCLK1P_117:M8,\" &\n\t\"MGTREFCLK1P_118:G10,\" &\n\t\"MGTREFCLK1P_119:C10,\" &\n\t\"MGTRREF_115:B11,\" &\n\t\"MGTVCCAUX_G10:(R8,U8),\" &\n\t\"MGTVCCAUX_G11:N8,\" &\n\t\"NOCONNECT:(W9,W10,AC9,AC10),\" &\n\t\"PROGRAM_B:AJ11,\" &\n\t\"TCK:P10,\" &\n\t\"TDI:T10,\" &\n\t\"TDN_AC20:AC20,\" &\n\t\"TDO:R10,\" &\n\t\"TDP_AC21:AC21,\" &\n\t\"TMS:P11,\" &\n\t\"VCCADC_0:Y21,\" &\n\t\"VCCAUX:(R18,R26,T17,T19,T25,U18,U26,V17,V25,W18,\" &\n\t\t\"W26,Y17,Y25,AA18,AA26,AB17,AB25,AC18,AC26,AD17,\" &\n\t\t\"AD25,AE18,AE26,AF17,AF19,AF25,AG18,AG26,AH25),\" &\n\t\"VCCBATT_0:N11,\" &\n\t\"VCCBRAM:(R22,U22,W22,AA22,AC22,AE22,AG22,AH21),\" &\n\t\"VCCINT:(P13,P15,P27,R12,R14,R16,R20,R24,T13,T15,\" &\n\t\t\"T21,T23,T27,U12,U14,U16,U20,U24,V11,V13,\" &\n\t\t\"V15,V19,V21,V23,V27,W12,W14,W16,W20,W24,\" &\n\t\t\"W28,Y11,Y13,Y15,Y19,Y23,Y27,AA10,AA12,AA14,\" &\n\t\t\"AA16,AA24,AA28,AB11,AB13,AB15,AB19,AB23,AB27,AC12,\" &\n\t\t\"AC14,AC16,AC24,AC28,AD11,AD13,AD15,AD19,AD21,AD23,\" &\n\t\t\"AD27,AE10,AE12,AE14,AE16,AE20,AE24,AE28,AF11,AF13,\" &\n\t\t\"AF15,AF21,AF23,AF27,AG12,AG14,AG16,AG20,AG24,AG28,\" &\n\t\t\"AH11,AH13,AH15,AH19,AH23,AH27),\" &\n\t\"VCCO_0:(M10,T11),\" &\n\t\"VCCO_12:(AK26,AN27,AT28,AU25,AW29,AY26),\" &\n\t\"VCCO_13:(AP34,AR31,AU35,AV32,AY36,BA33,BB30),\" &\n\t\"VCCO_14:(AF28,AH32,AJ29,AK36,AL33,AM30,AN37),\" &\n\t\"VCCO_15:(AM40,AR41,AT38,AV42,AW39,BB40),\" &\n\t\"VCCO_16:(Y36,AA33,AB30,AD34,AE31,AG35),\" &\n\t\"VCCO_17:(AB40,AC37,AE41,AF38,AH42,AJ39),\" &\n\t\"VCCO_18:(P34,T38,U35,V32,V42,W39),\" &\n\t\"VCCO_19:(B40,E41,H42,J39,M40,N37,R41),\" &\n\t\"VCCO_31:(AK16,AL13,AP14,AR11,AU15,AV12,BA13),\" &\n\t\"VCCO_32:(AJ19,AN17,AT18,AW19,AY16,BB20),\" &\n\t\"VCCO_33:(AL23,AM20,AP24,AR21,AV22,BA23),\" &\n\t\"VCCO_34:(H32,L33,M30,R31,T28,W29),\" &\n\t\"VCCO_35:(A33,C37,D34,E31,F38,G35,K36),\" &\n\t\"VCCO_36:(G25,H22,J29,K26,L23,N27,P24),\" &\n\t\"VCCO_37:(A23,B30,C27,D24,E21,F28),\" &\n\t\"VCCO_38:(B20,C17,F18,J19,M20,N17),\" &\n\t\"VCCO_39:(D14,G15,H12,K16,L13,P14),\" &\n\t\"VN_AB20:AB20,\" &\n\t\"VP_AA21:AA21,\" &\n\t\"VREFN_AA20:AA20,\" &\n\t\"VREFP_AB21:AB21,\" &\n\t\"IO_A14:A14,\" &\n\t\"IO_A15:A15,\" &\n\t\"IO_A16:A16,\" &\n\t\"IO_A17:A17,\" &\n\t\"IO_A19:A19,\" &\n\t\"IO_A20:A20,\" &\n\t\"IO_A21:A21,\" &\n\t\"IO_A22:A22,\" &\n\t\"IO_A24:A24,\" &\n\t\"IO_A25:A25,\" &\n\t\"IO_A26:A26,\" &\n\t\"IO_A27:A27,\" &\n\t\"IO_A29:A29,\" &\n\t\"IO_A30:A30,\" &\n\t\"IO_A31:A31,\" &\n\t\"IO_A32:A32,\" &\n\t\"IO_A34:A34,\" &\n\t\"IO_A35:A35,\" &\n\t\"IO_A36:A36,\" &\n\t\"IO_A37:A37,\" &\n\t\"IO_A39:A39,\" &\n\t\"IO_A40:A40,\" &\n\t\"IO_A41:A41,\" &\n\t\"IO_B14:B14,\" &\n\t\"IO_B16:B16,\" &\n\t\"IO_B17:B17,\" &\n\t\"IO_B18:B18,\" &\n\t\"IO_B19:B19,\" &\n\t\"IO_B21:B21,\" &\n\t\"IO_B22:B22,\" &\n\t\"IO_B23:B23,\" &\n\t\"IO_B24:B24,\" &\n\t\"IO_B26:B26,\" &\n\t\"IO_B27:B27,\" &\n\t\"IO_B28:B28,\" &\n\t\"IO_B29:B29,\" &\n\t\"IO_B31:B31,\" &\n\t\"IO_B32:B32,\" &\n\t\"IO_B33:B33,\" &\n\t\"IO_B34:B34,\" &\n\t\"IO_B36:B36,\" &\n\t\"IO_B37:B37,\" &\n\t\"IO_B38:B38,\" &\n\t\"IO_B39:B39,\" &\n\t\"IO_B41:B41,\" &\n\t\"IO_B42:B42,\" &\n\t\"IO_C13:C13,\" &\n\t\"IO_C14:C14,\" &\n\t\"IO_C15:C15,\" &\n\t\"IO_C16:C16,\" &\n\t\"IO_C18:C18,\" &\n\t\"IO_C19:C19,\" &\n\t\"IO_C20:C20,\" &\n\t\"IO_C21:C21,\" &\n\t\"IO_C23:C23,\" &\n\t\"IO_C24:C24,\" &\n\t\"IO_C25:C25,\" &\n\t\"IO_C26:C26,\" &\n\t\"IO_C28:C28,\" &\n\t\"IO_C29:C29,\" &\n\t\"IO_C30:C30,\" &\n\t\"IO_C31:C31,\" &\n\t\"IO_C33:C33,\" &\n\t\"IO_C34:C34,\" &\n\t\"IO_C35:C35,\" &\n\t\"IO_C36:C36,\" &\n\t\"IO_C38:C38,\" &\n\t\"IO_C39:C39,\" &\n\t\"IO_C40:C40,\" &\n\t\"IO_C41:C41,\" &\n\t\"IO_D12:D12,\" &\n\t\"IO_D13:D13,\" &\n\t\"IO_D15:D15,\" &\n\t\"IO_D16:D16,\" &\n\t\"IO_D17:D17,\" &\n\t\"IO_D18:D18,\" &\n\t\"IO_D20:D20,\" &\n\t\"IO_D21:D21,\" &\n\t\"IO_D22:D22,\" &\n\t\"IO_D23:D23,\" &\n\t\"IO_D25:D25,\" &\n\t\"IO_D26:D26,\" &\n\t\"IO_D27:D27,\" &\n\t\"IO_D28:D28,\" &\n\t\"IO_D30:D30,\" &\n\t\"IO_D31:D31,\" &\n\t\"IO_D32:D32,\" &\n\t\"IO_D33:D33,\" &\n\t\"IO_D35:D35,\" &\n\t\"IO_D36:D36,\" &\n\t\"IO_D37:D37,\" &\n\t\"IO_D38:D38,\" &\n\t\"IO_D40:D40,\" &\n\t\"IO_D41:D41,\" &\n\t\"IO_D42:D42,\" &\n\t\"IO_E12:E12,\" &\n\t\"IO_E13:E13,\" &\n\t\"IO_E14:E14,\" &\n\t\"IO_E15:E15,\" &\n\t\"IO_E17:E17,\" &\n\t\"IO_E18:E18,\" &\n\t\"IO_E19:E19,\" &\n\t\"IO_E20:E20,\" &\n\t\"IO_E22:E22,\" &\n\t\"IO_E23:E23,\" &\n\t\"IO_E24:E24,\" &\n\t\"IO_E25:E25,\" &\n\t\"IO_E27:E27,\" &\n\t\"IO_E28:E28,\" &\n\t\"IO_E29:E29,\" &\n\t\"IO_E30:E30,\" &\n\t\"IO_E32:E32,\" &\n\t\"IO_E33:E33,\" &\n\t\"IO_E34:E34,\" &\n\t\"IO_E35:E35,\" &\n\t\"IO_E37:E37,\" &\n\t\"IO_E38:E38,\" &\n\t\"IO_E39:E39,\" &\n\t\"IO_E40:E40,\" &\n\t\"IO_E42:E42,\" &\n\t\"IO_F12:F12,\" &\n\t\"IO_F14:F14,\" &\n\t\"IO_F15:F15,\" &\n\t\"IO_F16:F16,\" &\n\t\"IO_F17:F17,\" &\n\t\"IO_F19:F19,\" &\n\t\"IO_F20:F20,\" &\n\t\"IO_F21:F21,\" &\n\t\"IO_F22:F22,\" &\n\t\"IO_F24:F24,\" &\n\t\"IO_F25:F25,\" &\n\t\"IO_F26:F26,\" &\n\t\"IO_F27:F27,\" &\n\t\"IO_F29:F29,\" &\n\t\"IO_F30:F30,\" &\n\t\"IO_F31:F31,\" &\n\t\"IO_F32:F32,\" &\n\t\"IO_F34:F34,\" &\n\t\"IO_F35:F35,\" &\n\t\"IO_F36:F36,\" &\n\t\"IO_F37:F37,\" &\n\t\"IO_F39:F39,\" &\n\t\"IO_F40:F40,\" &\n\t\"IO_F41:F41,\" &\n\t\"IO_F42:F42,\" &\n\t\"IO_G12:G12,\" &\n\t\"IO_G13:G13,\" &\n\t\"IO_G14:G14,\" &\n\t\"IO_G16:G16,\" &\n\t\"IO_G17:G17,\" &\n\t\"IO_G18:G18,\" &\n\t\"IO_G19:G19,\" &\n\t\"IO_G21:G21,\" &\n\t\"IO_G22:G22,\" &\n\t\"IO_G23:G23,\" &\n\t\"IO_G24:G24,\" &\n\t\"IO_G26:G26,\" &\n\t\"IO_G27:G27,\" &\n\t\"IO_G28:G28,\" &\n\t\"IO_G29:G29,\" &\n\t\"IO_G31:G31,\" &\n\t\"IO_G32:G32,\" &\n\t\"IO_G33:G33,\" &\n\t\"IO_G34:G34,\" &\n\t\"IO_G36:G36,\" &\n\t\"IO_G37:G37,\" &\n\t\"IO_G38:G38,\" &\n\t\"IO_G39:G39,\" &\n\t\"IO_G41:G41,\" &\n\t\"IO_G42:G42,\" &\n\t\"IO_H13:H13,\" &\n\t\"IO_H14:H14,\" &\n\t\"IO_H15:H15,\" &\n\t\"IO_H16:H16,\" &\n\t\"IO_H18:H18,\" &\n\t\"IO_H19:H19,\" &\n\t\"IO_H20:H20,\" &\n\t\"IO_H21:H21,\" &\n\t\"IO_H23:H23,\" &\n\t\"IO_H24:H24,\" &\n\t\"IO_H25:H25,\" &\n\t\"IO_H26:H26,\" &\n\t\"IO_H28:H28,\" &\n\t\"IO_H29:H29,\" &\n\t\"IO_H30:H30,\" &\n\t\"IO_H31:H31,\" &\n\t\"IO_H33:H33,\" &\n\t\"IO_H34:H34,\" &\n\t\"IO_H35:H35,\" &\n\t\"IO_H36:H36,\" &\n\t\"IO_H38:H38,\" &\n\t\"IO_H39:H39,\" &\n\t\"IO_H40:H40,\" &\n\t\"IO_H41:H41,\" &\n\t\"IO_J11:J11,\" &\n\t\"IO_J12:J12,\" &\n\t\"IO_J13:J13,\" &\n\t\"IO_J15:J15,\" &\n\t\"IO_J16:J16,\" &\n\t\"IO_J17:J17,\" &\n\t\"IO_J18:J18,\" &\n\t\"IO_J20:J20,\" &\n\t\"IO_J21:J21,\" &\n\t\"IO_J22:J22,\" &\n\t\"IO_J23:J23,\" &\n\t\"IO_J25:J25,\" &\n\t\"IO_J26:J26,\" &\n\t\"IO_J27:J27,\" &\n\t\"IO_J28:J28,\" &\n\t\"IO_J30:J30,\" &\n\t\"IO_J31:J31,\" &\n\t\"IO_J32:J32,\" &\n\t\"IO_J33:J33,\" &\n\t\"IO_J35:J35,\" &\n\t\"IO_J36:J36,\" &\n\t\"IO_J37:J37,\" &\n\t\"IO_J38:J38,\" &\n\t\"IO_J40:J40,\" &\n\t\"IO_J41:J41,\" &\n\t\"IO_J42:J42,\" &\n\t\"IO_K12:K12,\" &\n\t\"IO_K13:K13,\" &\n\t\"IO_K14:K14,\" &\n\t\"IO_K15:K15,\" &\n\t\"IO_K17:K17,\" &\n\t\"IO_K18:K18,\" &\n\t\"IO_K19:K19,\" &\n\t\"IO_K20:K20,\" &\n\t\"IO_K22:K22,\" &\n\t\"IO_K23:K23,\" &\n\t\"IO_K24:K24,\" &\n\t\"IO_K25:K25,\" &\n\t\"IO_K27:K27,\" &\n\t\"IO_K28:K28,\" &\n\t\"IO_K29:K29,\" &\n\t\"IO_K30:K30,\" &\n\t\"IO_K32:K32,\" &\n\t\"IO_K33:K33,\" &\n\t\"IO_K34:K34,\" &\n\t\"IO_K35:K35,\" &\n\t\"IO_K37:K37,\" &\n\t\"IO_K38:K38,\" &\n\t\"IO_K39:K39,\" &\n\t\"IO_K40:K40,\" &\n\t\"IO_K42:K42,\" &\n\t\"IO_L11:L11,\" &\n\t\"IO_L12:L12,\" &\n\t\"IO_L14:L14,\" &\n\t\"IO_L15:L15,\" &\n\t\"IO_L16:L16,\" &\n\t\"IO_L17:L17,\" &\n\t\"IO_L19:L19,\" &\n\t\"IO_L20:L20,\" &\n\t\"IO_L21:L21,\" &\n\t\"IO_L22:L22,\" &\n\t\"IO_L24:L24,\" &\n\t\"IO_L25:L25,\" &\n\t\"IO_L26:L26,\" &\n\t\"IO_L27:L27,\" &\n\t\"IO_L29:L29,\" &\n\t\"IO_L30:L30,\" &\n\t\"IO_L31:L31,\" &\n\t\"IO_L32:L32,\" &\n\t\"IO_L34:L34,\" &\n\t\"IO_L35:L35,\" &\n\t\"IO_L36:L36,\" &\n\t\"IO_L37:L37,\" &\n\t\"IO_L39:L39,\" &\n\t\"IO_L40:L40,\" &\n\t\"IO_L41:L41,\" &\n\t\"IO_L42:L42,\" &\n\t\"IO_M11:M11,\" &\n\t\"IO_M12:M12,\" &\n\t\"IO_M13:M13,\" &\n\t\"IO_M14:M14,\" &\n\t\"IO_M16:M16,\" &\n\t\"IO_M17:M17,\" &\n\t\"IO_M18:M18,\" &\n\t\"IO_M19:M19,\" &\n\t\"IO_M21:M21,\" &\n\t\"IO_M22:M22,\" &\n\t\"IO_M23:M23,\" &\n\t\"IO_M24:M24,\" &\n\t\"IO_M26:M26,\" &\n\t\"IO_M27:M27,\" &\n\t\"IO_M28:M28,\" &\n\t\"IO_M29:M29,\" &\n\t\"IO_M31:M31,\" &\n\t\"IO_M32:M32,\" &\n\t\"IO_M33:M33,\" &\n\t\"IO_M34:M34,\" &\n\t\"IO_M36:M36,\" &\n\t\"IO_M37:M37,\" &\n\t\"IO_M38:M38,\" &\n\t\"IO_M39:M39,\" &\n\t\"IO_M41:M41,\" &\n\t\"IO_M42:M42,\" &\n\t\"IO_N13:N13,\" &\n\t\"IO_N14:N14,\" &\n\t\"IO_N15:N15,\" &\n\t\"IO_N16:N16,\" &\n\t\"IO_N18:N18,\" &\n\t\"IO_N19:N19,\" &\n\t\"IO_N20:N20,\" &\n\t\"IO_N21:N21,\" &\n\t\"IO_N23:N23,\" &\n\t\"IO_N24:N24,\" &\n\t\"IO_N25:N25,\" &\n\t\"IO_N26:N26,\" &\n\t\"IO_N28:N28,\" &\n\t\"IO_N29:N29,\" &\n\t\"IO_N30:N30,\" &\n\t\"IO_N31:N31,\" &\n\t\"IO_N33:N33,\" &\n\t\"IO_N34:N34,\" &\n\t\"IO_N35:N35,\" &\n\t\"IO_N36:N36,\" &\n\t\"IO_N38:N38,\" &\n\t\"IO_N39:N39,\" &\n\t\"IO_N40:N40,\" &\n\t\"IO_N41:N41,\" &\n\t\"IO_P17:P17,\" &\n\t\"IO_P18:P18,\" &\n\t\"IO_P20:P20,\" &\n\t\"IO_P21:P21,\" &\n\t\"IO_P22:P22,\" &\n\t\"IO_P23:P23,\" &\n\t\"IO_P25:P25,\" &\n\t\"IO_P26:P26,\" &\n\t\"IO_P28:P28,\" &\n\t\"IO_P30:P30,\" &\n\t\"IO_P31:P31,\" &\n\t\"IO_P32:P32,\" &\n\t\"IO_P33:P33,\" &\n\t\"IO_P35:P35,\" &\n\t\"IO_P36:P36,\" &\n\t\"IO_P37:P37,\" &\n\t\"IO_P38:P38,\" &\n\t\"IO_P40:P40,\" &\n\t\"IO_P41:P41,\" &\n\t\"IO_P42:P42,\" &\n\t\"IO_R28:R28,\" &\n\t\"IO_R29:R29,\" &\n\t\"IO_R30:R30,\" &\n\t\"IO_R32:R32,\" &\n\t\"IO_R33:R33,\" &\n\t\"IO_R34:R34,\" &\n\t\"IO_R35:R35,\" &\n\t\"IO_R37:R37,\" &\n\t\"IO_R38:R38,\" &\n\t\"IO_R39:R39,\" &\n\t\"IO_R40:R40,\" &\n\t\"IO_R42:R42,\" &\n\t\"IO_T29:T29,\" &\n\t\"IO_T30:T30,\" &\n\t\"IO_T31:T31,\" &\n\t\"IO_T32:T32,\" &\n\t\"IO_T34:T34,\" &\n\t\"IO_T35:T35,\" &\n\t\"IO_T36:T36,\" &\n\t\"IO_T37:T37,\" &\n\t\"IO_T39:T39,\" &\n\t\"IO_T40:T40,\" &\n\t\"IO_T41:T41,\" &\n\t\"IO_T42:T42,\" &\n\t\"IO_U28:U28,\" &\n\t\"IO_U29:U29,\" &\n\t\"IO_U31:U31,\" &\n\t\"IO_U32:U32,\" &\n\t\"IO_U33:U33,\" &\n\t\"IO_U34:U34,\" &\n\t\"IO_U36:U36,\" &\n\t\"IO_U37:U37,\" &\n\t\"IO_U38:U38,\" &\n\t\"IO_U39:U39,\" &\n\t\"IO_U41:U41,\" &\n\t\"IO_U42:U42,\" &\n\t\"IO_V29:V29,\" &\n\t\"IO_V30:V30,\" &\n\t\"IO_V31:V31,\" &\n\t\"IO_V33:V33,\" &\n\t\"IO_V34:V34,\" &\n\t\"IO_V35:V35,\" &\n\t\"IO_V36:V36,\" &\n\t\"IO_V38:V38,\" &\n\t\"IO_V39:V39,\" &\n\t\"IO_V40:V40,\" &\n\t\"IO_V41:V41,\" &\n\t\"IO_W30:W30,\" &\n\t\"IO_W31:W31,\" &\n\t\"IO_W32:W32,\" &\n\t\"IO_W33:W33,\" &\n\t\"IO_W35:W35,\" &\n\t\"IO_W36:W36,\" &\n\t\"IO_W37:W37,\" &\n\t\"IO_W38:W38,\" &\n\t\"IO_W40:W40,\" &\n\t\"IO_W41:W41,\" &\n\t\"IO_W42:W42,\" &\n\t\"IO_Y29:Y29,\" &\n\t\"IO_Y30:Y30,\" &\n\t\"IO_Y32:Y32,\" &\n\t\"IO_Y33:Y33,\" &\n\t\"IO_Y34:Y34,\" &\n\t\"IO_Y35:Y35,\" &\n\t\"IO_Y37:Y37,\" &\n\t\"IO_Y38:Y38,\" &\n\t\"IO_Y39:Y39,\" &\n\t\"IO_Y40:Y40,\" &\n\t\"IO_Y42:Y42,\" &\n\t\"IO_AA29:AA29,\" &\n\t\"IO_AA30:AA30,\" &\n\t\"IO_AA31:AA31,\" &\n\t\"IO_AA32:AA32,\" &\n\t\"IO_AA34:AA34,\" &\n\t\"IO_AA35:AA35,\" &\n\t\"IO_AA36:AA36,\" &\n\t\"IO_AA37:AA37,\" &\n\t\"IO_AA39:AA39,\" &\n\t\"IO_AA40:AA40,\" &\n\t\"IO_AA41:AA41,\" &\n\t\"IO_AA42:AA42,\" &\n\t\"IO_AB29:AB29,\" &\n\t\"IO_AB31:AB31,\" &\n\t\"IO_AB32:AB32,\" &\n\t\"IO_AB33:AB33,\" &\n\t\"IO_AB34:AB34,\" &\n\t\"IO_AB36:AB36,\" &\n\t\"IO_AB37:AB37,\" &\n\t\"IO_AB38:AB38,\" &\n\t\"IO_AB39:AB39,\" &\n\t\"IO_AB41:AB41,\" &\n\t\"IO_AB42:AB42,\" &\n\t\"IO_AC29:AC29,\" &\n\t\"IO_AC30:AC30,\" &\n\t\"IO_AC31:AC31,\" &\n\t\"IO_AC33:AC33,\" &\n\t\"IO_AC34:AC34,\" &\n\t\"IO_AC35:AC35,\" &\n\t\"IO_AC36:AC36,\" &\n\t\"IO_AC38:AC38,\" &\n\t\"IO_AC39:AC39,\" &\n\t\"IO_AC40:AC40,\" &\n\t\"IO_AC41:AC41,\" &\n\t\"IO_AD30:AD30,\" &\n\t\"IO_AD31:AD31,\" &\n\t\"IO_AD32:AD32,\" &\n\t\"IO_AD33:AD33,\" &\n\t\"IO_AD35:AD35,\" &\n\t\"IO_AD36:AD36,\" &\n\t\"IO_AD37:AD37,\" &\n\t\"IO_AD38:AD38,\" &\n\t\"IO_AD40:AD40,\" &\n\t\"IO_AD41:AD41,\" &\n\t\"IO_AD42:AD42,\" &\n\t\"IO_AE29:AE29,\" &\n\t\"IO_AE30:AE30,\" &\n\t\"IO_AE32:AE32,\" &\n\t\"IO_AE33:AE33,\" &\n\t\"IO_AE34:AE34,\" &\n\t\"IO_AE35:AE35,\" &\n\t\"IO_AE37:AE37,\" &\n\t\"IO_AE38:AE38,\" &\n\t\"IO_AE39:AE39,\" &\n\t\"IO_AE40:AE40,\" &\n\t\"IO_AE42:AE42,\" &\n\t\"IO_AF29:AF29,\" &\n\t\"IO_AF30:AF30,\" &\n\t\"IO_AF31:AF31,\" &\n\t\"IO_AF32:AF32,\" &\n\t\"IO_AF34:AF34,\" &\n\t\"IO_AF35:AF35,\" &\n\t\"IO_AF36:AF36,\" &\n\t\"IO_AF37:AF37,\" &\n\t\"IO_AF39:AF39,\" &\n\t\"IO_AF40:AF40,\" &\n\t\"IO_AF41:AF41,\" &\n\t\"IO_AF42:AF42,\" &\n\t\"IO_AG29:AG29,\" &\n\t\"IO_AG31:AG31,\" &\n\t\"IO_AG32:AG32,\" &\n\t\"IO_AG33:AG33,\" &\n\t\"IO_AG34:AG34,\" &\n\t\"IO_AG36:AG36,\" &\n\t\"IO_AG37:AG37,\" &\n\t\"IO_AG38:AG38,\" &\n\t\"IO_AG39:AG39,\" &\n\t\"IO_AG41:AG41,\" &\n\t\"IO_AG42:AG42,\" &\n\t\"IO_AH28:AH28,\" &\n\t\"IO_AH29:AH29,\" &\n\t\"IO_AH30:AH30,\" &\n\t\"IO_AH31:AH31,\" &\n\t\"IO_AH33:AH33,\" &\n\t\"IO_AH34:AH34,\" &\n\t\"IO_AH35:AH35,\" &\n\t\"IO_AH36:AH36,\" &\n\t\"IO_AH38:AH38,\" &\n\t\"IO_AH39:AH39,\" &\n\t\"IO_AH40:AH40,\" &\n\t\"IO_AH41:AH41,\" &\n\t\"IO_AJ12:AJ12,\" &\n\t\"IO_AJ13:AJ13,\" &\n\t\"IO_AJ15:AJ15,\" &\n\t\"IO_AJ16:AJ16,\" &\n\t\"IO_AJ17:AJ17,\" &\n\t\"IO_AJ18:AJ18,\" &\n\t\"IO_AJ20:AJ20,\" &\n\t\"IO_AJ21:AJ21,\" &\n\t\"IO_AJ22:AJ22,\" &\n\t\"IO_AJ23:AJ23,\" &\n\t\"IO_AJ25:AJ25,\" &\n\t\"IO_AJ26:AJ26,\" &\n\t\"IO_AJ28:AJ28,\" &\n\t\"IO_AJ30:AJ30,\" &\n\t\"IO_AJ31:AJ31,\" &\n\t\"IO_AJ32:AJ32,\" &\n\t\"IO_AJ33:AJ33,\" &\n\t\"IO_AJ35:AJ35,\" &\n\t\"IO_AJ36:AJ36,\" &\n\t\"IO_AJ37:AJ37,\" &\n\t\"IO_AJ38:AJ38,\" &\n\t\"IO_AJ40:AJ40,\" &\n\t\"IO_AJ41:AJ41,\" &\n\t\"IO_AJ42:AJ42,\" &\n\t\"IO_AK12:AK12,\" &\n\t\"IO_AK13:AK13,\" &\n\t\"IO_AK14:AK14,\" &\n\t\"IO_AK15:AK15,\" &\n\t\"IO_AK17:AK17,\" &\n\t\"IO_AK18:AK18,\" &\n\t\"IO_AK19:AK19,\" &\n\t\"IO_AK20:AK20,\" &\n\t\"IO_AK22:AK22,\" &\n\t\"IO_AK23:AK23,\" &\n\t\"IO_AK24:AK24,\" &\n\t\"IO_AK25:AK25,\" &\n\t\"IO_AK27:AK27,\" &\n\t\"IO_AK28:AK28,\" &\n\t\"IO_AK29:AK29,\" &\n\t\"IO_AK30:AK30,\" &\n\t\"IO_AK32:AK32,\" &\n\t\"IO_AK33:AK33,\" &\n\t\"IO_AK34:AK34,\" &\n\t\"IO_AK35:AK35,\" &\n\t\"IO_AK37:AK37,\" &\n\t\"IO_AK38:AK38,\" &\n\t\"IO_AK39:AK39,\" &\n\t\"IO_AK40:AK40,\" &\n\t\"IO_AK42:AK42,\" &\n\t\"IO_AL12:AL12,\" &\n\t\"IO_AL14:AL14,\" &\n\t\"IO_AL15:AL15,\" &\n\t\"IO_AL16:AL16,\" &\n\t\"IO_AL17:AL17,\" &\n\t\"IO_AL19:AL19,\" &\n\t\"IO_AL20:AL20,\" &\n\t\"IO_AL21:AL21,\" &\n\t\"IO_AL22:AL22,\" &\n\t\"IO_AL24:AL24,\" &\n\t\"IO_AL25:AL25,\" &\n\t\"IO_AL26:AL26,\" &\n\t\"IO_AL27:AL27,\" &\n\t\"IO_AL29:AL29,\" &\n\t\"IO_AL30:AL30,\" &\n\t\"IO_AL31:AL31,\" &\n\t\"IO_AL32:AL32,\" &\n\t\"IO_AL34:AL34,\" &\n\t\"IO_AL35:AL35,\" &\n\t\"IO_AL36:AL36,\" &\n\t\"IO_AL37:AL37,\" &\n\t\"IO_AL39:AL39,\" &\n\t\"IO_AL40:AL40,\" &\n\t\"IO_AL41:AL41,\" &\n\t\"IO_AL42:AL42,\" &\n\t\"IO_AM11:AM11,\" &\n\t\"IO_AM12:AM12,\" &\n\t\"IO_AM13:AM13,\" &\n\t\"IO_AM14:AM14,\" &\n\t\"IO_AM16:AM16,\" &\n\t\"IO_AM17:AM17,\" &\n\t\"IO_AM18:AM18,\" &\n\t\"IO_AM19:AM19,\" &\n\t\"IO_AM21:AM21,\" &\n\t\"IO_AM22:AM22,\" &\n\t\"IO_AM23:AM23,\" &\n\t\"IO_AM24:AM24,\" &\n\t\"IO_AM26:AM26,\" &\n\t\"IO_AM27:AM27,\" &\n\t\"IO_AM28:AM28,\" &\n\t\"IO_AM29:AM29,\" &\n\t\"IO_AM31:AM31,\" &\n\t\"IO_AM32:AM32,\" &\n\t\"IO_AM33:AM33,\" &\n\t\"IO_AM34:AM34,\" &\n\t\"IO_AM36:AM36,\" &\n\t\"IO_AM37:AM37,\" &\n\t\"IO_AM38:AM38,\" &\n\t\"IO_AM39:AM39,\" &\n\t\"IO_AM41:AM41,\" &\n\t\"IO_AM42:AM42,\" &\n\t\"IO_AN11:AN11,\" &\n\t\"IO_AN13:AN13,\" &\n\t\"IO_AN14:AN14,\" &\n\t\"IO_AN15:AN15,\" &\n\t\"IO_AN16:AN16,\" &\n\t\"IO_AN18:AN18,\" &\n\t\"IO_AN19:AN19,\" &\n\t\"IO_AN20:AN20,\" &\n\t\"IO_AN21:AN21,\" &\n\t\"IO_AN23:AN23,\" &\n\t\"IO_AN24:AN24,\" &\n\t\"IO_AN25:AN25,\" &\n\t\"IO_AN26:AN26,\" &\n\t\"IO_AN28:AN28,\" &\n\t\"IO_AN29:AN29,\" &\n\t\"IO_AN30:AN30,\" &\n\t\"IO_AN31:AN31,\" &\n\t\"IO_AN33:AN33,\" &\n\t\"IO_AN34:AN34,\" &\n\t\"IO_AN35:AN35,\" &\n\t\"IO_AN36:AN36,\" &\n\t\"IO_AN38:AN38,\" &\n\t\"IO_AN39:AN39,\" &\n\t\"IO_AN40:AN40,\" &\n\t\"IO_AN41:AN41,\" &\n\t\"IO_AP11:AP11,\" &\n\t\"IO_AP12:AP12,\" &\n\t\"IO_AP13:AP13,\" &\n\t\"IO_AP15:AP15,\" &\n\t\"IO_AP16:AP16,\" &\n\t\"IO_AP17:AP17,\" &\n\t\"IO_AP18:AP18,\" &\n\t\"IO_AP20:AP20,\" &\n\t\"IO_AP21:AP21,\" &\n\t\"IO_AP22:AP22,\" &\n\t\"IO_AP23:AP23,\" &\n\t\"IO_AP25:AP25,\" &\n\t\"IO_AP26:AP26,\" &\n\t\"IO_AP27:AP27,\" &\n\t\"IO_AP28:AP28,\" &\n\t\"IO_AP30:AP30,\" &\n\t\"IO_AP31:AP31,\" &\n\t\"IO_AP32:AP32,\" &\n\t\"IO_AP33:AP33,\" &\n\t\"IO_AP35:AP35,\" &\n\t\"IO_AP36:AP36,\" &\n\t\"IO_AP37:AP37,\" &\n\t\"IO_AP38:AP38,\" &\n\t\"IO_AP40:AP40,\" &\n\t\"IO_AP41:AP41,\" &\n\t\"IO_AP42:AP42,\" &\n\t\"IO_AR12:AR12,\" &\n\t\"IO_AR13:AR13,\" &\n\t\"IO_AR14:AR14,\" &\n\t\"IO_AR15:AR15,\" &\n\t\"IO_AR17:AR17,\" &\n\t\"IO_AR18:AR18,\" &\n\t\"IO_AR19:AR19,\" &\n\t\"IO_AR20:AR20,\" &\n\t\"IO_AR22:AR22,\" &\n\t\"IO_AR23:AR23,\" &\n\t\"IO_AR24:AR24,\" &\n\t\"IO_AR25:AR25,\" &\n\t\"IO_AR27:AR27,\" &\n\t\"IO_AR28:AR28,\" &\n\t\"IO_AR29:AR29,\" &\n\t\"IO_AR30:AR30,\" &\n\t\"IO_AR32:AR32,\" &\n\t\"IO_AR33:AR33,\" &\n\t\"IO_AR34:AR34,\" &\n\t\"IO_AR35:AR35,\" &\n\t\"IO_AR37:AR37,\" &\n\t\"IO_AR38:AR38,\" &\n\t\"IO_AR39:AR39,\" &\n\t\"IO_AR40:AR40,\" &\n\t\"IO_AR42:AR42,\" &\n\t\"IO_AT12:AT12,\" &\n\t\"IO_AT14:AT14,\" &\n\t\"IO_AT15:AT15,\" &\n\t\"IO_AT16:AT16,\" &\n\t\"IO_AT17:AT17,\" &\n\t\"IO_AT19:AT19,\" &\n\t\"IO_AT20:AT20,\" &\n\t\"IO_AT21:AT21,\" &\n\t\"IO_AT22:AT22,\" &\n\t\"IO_AT24:AT24,\" &\n\t\"IO_AT25:AT25,\" &\n\t\"IO_AT26:AT26,\" &\n\t\"IO_AT27:AT27,\" &\n\t\"IO_AT29:AT29,\" &\n\t\"IO_AT30:AT30,\" &\n\t\"IO_AT31:AT31,\" &\n\t\"IO_AT32:AT32,\" &\n\t\"IO_AT34:AT34,\" &\n\t\"IO_AT35:AT35,\" &\n\t\"IO_AT36:AT36,\" &\n\t\"IO_AT37:AT37,\" &\n\t\"IO_AT39:AT39,\" &\n\t\"IO_AT40:AT40,\" &\n\t\"IO_AT41:AT41,\" &\n\t\"IO_AT42:AT42,\" &\n\t\"IO_AU12:AU12,\" &\n\t\"IO_AU13:AU13,\" &\n\t\"IO_AU14:AU14,\" &\n\t\"IO_AU16:AU16,\" &\n\t\"IO_AU17:AU17,\" &\n\t\"IO_AU18:AU18,\" &\n\t\"IO_AU19:AU19,\" &\n\t\"IO_AU21:AU21,\" &\n\t\"IO_AU22:AU22,\" &\n\t\"IO_AU23:AU23,\" &\n\t\"IO_AU24:AU24,\" &\n\t\"IO_AU26:AU26,\" &\n\t\"IO_AU27:AU27,\" &\n\t\"IO_AU28:AU28,\" &\n\t\"IO_AU29:AU29,\" &\n\t\"IO_AU31:AU31,\" &\n\t\"IO_AU32:AU32,\" &\n\t\"IO_AU33:AU33,\" &\n\t\"IO_AU34:AU34,\" &\n\t\"IO_AU36:AU36,\" &\n\t\"IO_AU37:AU37,\" &\n\t\"IO_AU38:AU38,\" &\n\t\"IO_AU39:AU39,\" &\n\t\"IO_AU41:AU41,\" &\n\t\"IO_AU42:AU42,\" &\n\t\"IO_AV13:AV13,\" &\n\t\"IO_AV14:AV14,\" &\n\t\"IO_AV15:AV15,\" &\n\t\"IO_AV16:AV16,\" &\n\t\"IO_AV18:AV18,\" &\n\t\"IO_AV19:AV19,\" &\n\t\"IO_AV20:AV20,\" &\n\t\"IO_AV21:AV21,\" &\n\t\"IO_AV23:AV23,\" &\n\t\"IO_AV24:AV24,\" &\n\t\"IO_AV25:AV25,\" &\n\t\"IO_AV26:AV26,\" &\n\t\"IO_AV28:AV28,\" &\n\t\"IO_AV29:AV29,\" &\n\t\"IO_AV30:AV30,\" &\n\t\"IO_AV31:AV31,\" &\n\t\"IO_AV33:AV33,\" &\n\t\"IO_AV34:AV34,\" &\n\t\"IO_AV35:AV35,\" &\n\t\"IO_AV36:AV36,\" &\n\t\"IO_AV38:AV38,\" &\n\t\"IO_AV39:AV39,\" &\n\t\"IO_AV40:AV40,\" &\n\t\"IO_AV41:AV41,\" &\n\t\"IO_AW12:AW12,\" &\n\t\"IO_AW13:AW13,\" &\n\t\"IO_AW15:AW15,\" &\n\t\"IO_AW16:AW16,\" &\n\t\"IO_AW17:AW17,\" &\n\t\"IO_AW18:AW18,\" &\n\t\"IO_AW20:AW20,\" &\n\t\"IO_AW21:AW21,\" &\n\t\"IO_AW22:AW22,\" &\n\t\"IO_AW23:AW23,\" &\n\t\"IO_AW25:AW25,\" &\n\t\"IO_AW26:AW26,\" &\n\t\"IO_AW27:AW27,\" &\n\t\"IO_AW28:AW28,\" &\n\t\"IO_AW30:AW30,\" &\n\t\"IO_AW31:AW31,\" &\n\t\"IO_AW32:AW32,\" &\n\t\"IO_AW33:AW33,\" &\n\t\"IO_AW35:AW35,\" &\n\t\"IO_AW36:AW36,\" &\n\t\"IO_AW37:AW37,\" &\n\t\"IO_AW38:AW38,\" &\n\t\"IO_AW40:AW40,\" &\n\t\"IO_AW41:AW41,\" &\n\t\"IO_AW42:AW42,\" &\n\t\"IO_AY12:AY12,\" &\n\t\"IO_AY13:AY13,\" &\n\t\"IO_AY14:AY14,\" &\n\t\"IO_AY15:AY15,\" &\n\t\"IO_AY17:AY17,\" &\n\t\"IO_AY18:AY18,\" &\n\t\"IO_AY19:AY19,\" &\n\t\"IO_AY20:AY20,\" &\n\t\"IO_AY22:AY22,\" &\n\t\"IO_AY23:AY23,\" &\n\t\"IO_AY24:AY24,\" &\n\t\"IO_AY25:AY25,\" &\n\t\"IO_AY27:AY27,\" &\n\t\"IO_AY28:AY28,\" &\n\t\"IO_AY29:AY29,\" &\n\t\"IO_AY30:AY30,\" &\n\t\"IO_AY32:AY32,\" &\n\t\"IO_AY33:AY33,\" &\n\t\"IO_AY34:AY34,\" &\n\t\"IO_AY35:AY35,\" &\n\t\"IO_AY37:AY37,\" &\n\t\"IO_AY38:AY38,\" &\n\t\"IO_AY39:AY39,\" &\n\t\"IO_AY40:AY40,\" &\n\t\"IO_AY42:AY42,\" &\n\t\"IO_BA12:BA12,\" &\n\t\"IO_BA14:BA14,\" &\n\t\"IO_BA15:BA15,\" &\n\t\"IO_BA16:BA16,\" &\n\t\"IO_BA17:BA17,\" &\n\t\"IO_BA19:BA19,\" &\n\t\"IO_BA20:BA20,\" &\n\t\"IO_BA21:BA21,\" &\n\t\"IO_BA22:BA22,\" &\n\t\"IO_BA24:BA24,\" &\n\t\"IO_BA25:BA25,\" &\n\t\"IO_BA26:BA26,\" &\n\t\"IO_BA27:BA27,\" &\n\t\"IO_BA29:BA29,\" &\n\t\"IO_BA30:BA30,\" &\n\t\"IO_BA31:BA31,\" &\n\t\"IO_BA32:BA32,\" &\n\t\"IO_BA34:BA34,\" &\n\t\"IO_BA35:BA35,\" &\n\t\"IO_BA36:BA36,\" &\n\t\"IO_BA37:BA37,\" &\n\t\"IO_BA39:BA39,\" &\n\t\"IO_BA40:BA40,\" &\n\t\"IO_BA41:BA41,\" &\n\t\"IO_BA42:BA42,\" &\n\t\"IO_BB12:BB12,\" &\n\t\"IO_BB13:BB13,\" &\n\t\"IO_BB14:BB14,\" &\n\t\"IO_BB16:BB16,\" &\n\t\"IO_BB17:BB17,\" &\n\t\"IO_BB18:BB18,\" &\n\t\"IO_BB19:BB19,\" &\n\t\"IO_BB21:BB21,\" &\n\t\"IO_BB22:BB22,\" &\n\t\"IO_BB23:BB23,\" &\n\t\"IO_BB24:BB24,\" &\n\t\"IO_BB26:BB26,\" &\n\t\"IO_BB27:BB27,\" &\n\t\"IO_BB28:BB28,\" &\n\t\"IO_BB29:BB29,\" &\n\t\"IO_BB31:BB31,\" &\n\t\"IO_BB32:BB32,\" &\n\t\"IO_BB33:BB33,\" &\n\t\"IO_BB34:BB34,\" &\n\t\"IO_BB36:BB36,\" &\n\t\"IO_BB37:BB37,\" &\n\t\"IO_BB38:BB38,\" &\n\t\"IO_BB39:BB39,\" &\n\t\"IO_BB41:BB41\";\n\n\n-- Grouped Port Identification\n\nattribute PORT_GROUPING of XC7VX690T_FFG1761 : entity is\n\"DIFFERENTIAL_VOLTAGE (\" &\n\"(MGTHRXP0_111, MGTHRXN0_111), \" &\n\"(MGTHRXP0_112, MGTHRXN0_112), \" &\n\"(MGTHRXP0_113, MGTHRXN0_113), \" &\n\"(MGTHRXP0_114, MGTHRXN0_114), \" &\n\"(MGTHRXP0_115, MGTHRXN0_115), \" &\n\"(MGTHRXP0_116, MGTHRXN0_116), \" &\n\"(MGTHRXP0_117, MGTHRXN0_117), \" &\n\"(MGTHRXP0_118, MGTHRXN0_118), \" &\n\"(MGTHRXP0_119, MGTHRXN0_119), \" &\n\"(MGTHRXP1_111, MGTHRXN1_111), \" &\n\"(MGTHRXP1_112, MGTHRXN1_112), \" &\n\"(MGTHRXP1_113, MGTHRXN1_113), \" &\n\"(MGTHRXP1_114, MGTHRXN1_114), \" &\n\"(MGTHRXP1_115, MGTHRXN1_115), \" &\n\"(MGTHRXP1_116, MGTHRXN1_116), \" &\n\"(MGTHRXP1_117, MGTHRXN1_117), \" &\n\"(MGTHRXP1_118, MGTHRXN1_118), \" &\n\"(MGTHRXP1_119, MGTHRXN1_119), \" &\n\"(MGTHRXP2_111, MGTHRXN2_111), \" &\n\"(MGTHRXP2_112, MGTHRXN2_112), \" &\n\"(MGTHRXP2_113, MGTHRXN2_113), \" &\n\"(MGTHRXP2_114, MGTHRXN2_114), \" &\n\"(MGTHRXP2_115, MGTHRXN2_115), \" &\n\"(MGTHRXP2_116, MGTHRXN2_116), \" &\n\"(MGTHRXP2_117, MGTHRXN2_117), \" &\n\"(MGTHRXP2_118, MGTHRXN2_118), \" &\n\"(MGTHRXP2_119, MGTHRXN2_119), \" &\n\"(MGTHRXP3_111, MGTHRXN3_111), \" &\n\"(MGTHRXP3_112, MGTHRXN3_112), \" &\n\"(MGTHRXP3_113, MGTHRXN3_113), \" &\n\"(MGTHRXP3_114, MGTHRXN3_114), \" &\n\"(MGTHRXP3_115, MGTHRXN3_115), \" &\n\"(MGTHRXP3_116, MGTHRXN3_116), \" &\n\"(MGTHRXP3_117, MGTHRXN3_117), \" &\n\"(MGTHRXP3_118, MGTHRXN3_118), \" &\n\"(MGTHRXP3_119, MGTHRXN3_119), \" &\n\"(MGTHTXP0_111, MGTHTXN0_111), \" &\n\"(MGTHTXP0_112, MGTHTXN0_112), \" &\n\"(MGTHTXP0_113, MGTHTXN0_113), \" &\n\"(MGTHTXP0_114, MGTHTXN0_114), \" &\n\"(MGTHTXP0_115, MGTHTXN0_115), \" &\n\"(MGTHTXP0_116, MGTHTXN0_116), \" &\n\"(MGTHTXP0_117, MGTHTXN0_117), \" &\n\"(MGTHTXP0_118, MGTHTXN0_118), \" &\n\"(MGTHTXP0_119, MGTHTXN0_119), \" &\n\"(MGTHTXP1_111, MGTHTXN1_111), \" &\n\"(MGTHTXP1_112, MGTHTXN1_112), \" &\n\"(MGTHTXP1_113, MGTHTXN1_113), \" &\n\"(MGTHTXP1_114, MGTHTXN1_114), \" &\n\"(MGTHTXP1_115, MGTHTXN1_115), \" &\n\"(MGTHTXP1_116, MGTHTXN1_116), \" &\n\"(MGTHTXP1_117, MGTHTXN1_117), \" &\n\"(MGTHTXP1_118, MGTHTXN1_118), \" &\n\"(MGTHTXP1_119, MGTHTXN1_119), \" &\n\"(MGTHTXP2_111, MGTHTXN2_111), \" &\n\"(MGTHTXP2_112, MGTHTXN2_112), \" &\n\"(MGTHTXP2_113, MGTHTXN2_113), \" &\n\"(MGTHTXP2_114, MGTHTXN2_114), \" &\n\"(MGTHTXP2_115, MGTHTXN2_115), \" &\n\"(MGTHTXP2_116, MGTHTXN2_116), \" &\n\"(MGTHTXP2_117, MGTHTXN2_117), \" &\n\"(MGTHTXP2_118, MGTHTXN2_118), \" &\n\"(MGTHTXP2_119, MGTHTXN2_119), \" &\n\"(MGTHTXP3_111, MGTHTXN3_111), \" &\n\"(MGTHTXP3_112, MGTHTXN3_112), \" &\n\"(MGTHTXP3_113, MGTHTXN3_113), \" &\n\"(MGTHTXP3_114, MGTHTXN3_114), \" &\n\"(MGTHTXP3_115, MGTHTXN3_115), \" &\n\"(MGTHTXP3_116, MGTHTXN3_116), \" &\n\"(MGTHTXP3_117, MGTHTXN3_117), \" &\n\"(MGTHTXP3_118, MGTHTXN3_118), \" &\n\"(MGTHTXP3_119, MGTHTXN3_119))\";\n\n-- Scan Port Identification\n\nattribute TAP_SCAN_IN    of TDI : signal is true;\nattribute TAP_SCAN_MODE  of TMS : signal is true;\nattribute TAP_SCAN_OUT   of TDO : signal is true;\nattribute TAP_SCAN_CLOCK of TCK : signal is (66.0e6, BOTH);\n\n-- Compliance-Enable Description\n\nattribute COMPLIANCE_PATTERNS of XC7VX690T_FFG1761 : entity is\n        \"(PROGRAM_B) (1)\";\n\n-- Instruction Register Description\n\nattribute INSTRUCTION_LENGTH of XC7VX690T_FFG1761 : entity is 6;\n\nattribute INSTRUCTION_OPCODE of XC7VX690T_FFG1761 : entity is\n        \"IDCODE\t\t(001001),\" & -- DEVICE_ID\n        \"BYPASS\t\t(111111),\" & -- BYPASS\n        \"EXTEST\t\t(100110),\" & -- BOUNDARY\n        \"SAMPLE\t\t(000001),\" & -- BOUNDARY\n        \"PRELOAD\t(000001),\" & -- Same as SAMPLE\n        \"USERCODE\t(001000),\" & -- DEVICE_ID\n        \"HIGHZ\t\t(001010),\" & -- BYPASS\n        \"EXTEST_PULSE\t(111100),\" & -- BOUNDARY\n        \"EXTEST_TRAIN\t(111101),\" & -- BOUNDARY\n\t\"ISC_ENABLE\t(010000),\" & -- ISC_CONFIG\n\t\"ISC_PROGRAM\t(010001),\" & -- ISC_PDATA\n\t\"ISC_NOOP\t(010100),\" & -- ISC_DEFAULT\n\t\"XSC_READ_RSVD\t(010101),\" & -- PRIVATE\n\t\"ISC_DISABLE\t(010110),\" & -- ISC_CONFIG\n\t\"XSC_PROGRAM_KEY\t(010010),\" & -- XSC_KEY_DATA\n        \"XSC_DNA\t(010111),\" & -- DNA\n        \"CFG_OUT\t(000100),\" & -- Not available during configuration with another mode.\n        \"CFG_IN\t\t(000101),\" & -- Not available during configuration with another mode.\n        \"JPROGRAM\t(001011),\" & -- Not available during configuration with another mode.\n        \"JSTART\t\t(001100),\" & -- Not available during configuration with another mode.\n        \"JSHUTDOWN\t(001101),\" & -- Not available during configuration with another mode.\n        \"FUSE_CTS\t(110000),\" & -- PRIVATE\n        \"FUSE_KEY\t(110001),\" & -- PRIVATE\n        \"FUSE_DNA\t(110010),\" & -- PRIVATE\n        \"FUSE_USER\t(110011),\" & -- PRIVATE\n        \"FUSE_CNTL\t(110100),\" & -- PRIVATE\n        \"USER1\t\t(000010),\" & -- Not available until after configuration\n        \"USER2\t\t(000011),\" & -- Not available until after configuration\n        \"USER3\t\t(100010),\" & -- Not available until after configuration\n        \"USER4\t\t(100011),\" & -- Not available until after configuration\n        \"XADC_DRP\t(110111),\" & -- PRIVATE\n        \"INTEST_RSVD\t(000111)\"; -- PRIVATE\n\nattribute INSTRUCTION_CAPTURE of XC7VX690T_FFG1761 : entity is\n-- Bit 5 is 1 when DONE is released (part of startup sequence)\n-- Bit 4 is 1 if house-cleaning is complete\n-- Bit 3 is ISC_Enabled\n-- Bit 2 is ISC_Done\n        \"XXXX01\";\n\nattribute INSTRUCTION_PRIVATE of XC7VX690T_FFG1761 : entity is\n-- If the device is configured, and a USER instruction is implemented\n-- and not private to the FPGA designer, then it should be removed\n-- from INSTRUCTION_PRIVATE, and the target register should be defined\n-- in REGISTER_ACCESS.\n\t\"ISC_ENABLE,\" &\n\t\"ISC_PROGRAM,\" &\n\t\"ISC_NOOP,\" &\n\t\"XSC_READ_RSVD,\" &\n\t\"ISC_DISABLE,\" &\n\t\"XSC_PROGRAM_KEY,\" &\n\t\"XSC_DNA,\" &\n        \"CFG_OUT,\" &\n        \"CFG_IN,\" &\n        \"JPROGRAM,\" &\n        \"JSTART,\" &\n        \"JSHUTDOWN,\" &\n        \"FUSE_CTS,\" &\n        \"FUSE_KEY,\" &\n        \"FUSE_DNA,\" &\n        \"FUSE_USER,\" &\n        \"FUSE_CNTL,\" &\n        \"USER1,\" &\n        \"USER2,\" &\n        \"USER3,\" &\n        \"USER4,\" &\n        \"XADC_DRP,\" &\n        \"INTEST_RSVD\";\n\n-- Optional Register Description\n\nattribute IDCODE_REGISTER of XC7VX690T_FFG1761 : entity is\n\t\"XXXX\" &\t-- version\n\t\"0011011\" &\t-- family\n\t\"010010001\" &\t-- array size\n\t\"00001001001\" &\t-- manufacturer\n\t\"1\";\t\t-- required by 1149.1\n\n\nattribute USERCODE_REGISTER of XC7VX690T_FFG1761 : entity is\n        \"XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX\";\n\n-- Register Access Description\n\nattribute REGISTER_ACCESS of XC7VX690T_FFG1761 : entity is\n--\t\"<reg_name>[<length>] (USER1),\" &\n--\t\"<reg_name>[<length>] (USER2),\" &\n--\t\"<reg_name>[<length>] (USER3),\" &\n--\t\"<reg_name>[<length>] (USER4),\" &\n        \"DATAREG[57] (XSC_DNA),\" &\n        \"BYPASS (HIGHZ,BYPASS),\" &\n\t\"DEVICE_ID (USERCODE,IDCODE),\" &\n\t\"BOUNDARY (SAMPLE,PRELOAD,EXTEST,EXTEST_PULSE,EXTEST_TRAIN)\";\n\n-- Boundary-Scan Register Description\n\nattribute BOUNDARY_LENGTH of XC7VX690T_FFG1761 : entity is 3389;\n\nattribute BOUNDARY_REGISTER of XC7VX690T_FFG1761 : entity is\n-- cellnum (type, port, function, safe[, ccell, disval, disrslt])\n\t\"   0 (BC_2, *, controlr, 1),\" &\n\t\"   1 (BC_2, CCLK_N10, output3, X, 0, 1, Z),\" & --  CCLK_0\n\t\"   2 (BC_2, CCLK_N10, input, X),\" & --  CCLK_0\n\t\"   3 (BC_2, M0_AL10, input, X),\" &\n\t\"   4 (BC_2, M1_AK10, input, X),\" &\n\t\"   5 (BC_2, M2_AJ10, input, X),\" &\n\t\"   6 (BC_2, CFGBVS_AH10, input, X),\" &\n\t\"   7 (BC_2, *, internal, 1),\" & --  PROGRAM_B\n\t\"   8 (BC_2, *, controlr, 1),\" &\n\t\"   9 (BC_2, INIT_B_AG11, output3, X, 8, 1, Z),\" & --  INIT_B_0\n\t\"  10 (BC_2, INIT_B_AG11, input, X),\" & --  INIT_B_0\n\t\"  11 (BC_2, *, controlr, 1),\" &\n\t\"  12 (BC_2, DONE_AL11, output3, X, 11, 1, Z),\" & --  DONE_0\n\t\"  13 (BC_2, DONE_AL11, input, X),\" & --  DONE_0\n\t\"  14 (BC_2, *, internal, X),\" &\n\t\"  15 (BC_2, *, internal, X),\" &\n\t\"  16 (BC_2, *, internal, X),\" &\n\t\"  17 (BC_2, *, internal, X),\" &\n\t\"  18 (BC_2, *, internal, X),\" &\n\t\"  19 (BC_2, *, internal, X),\" &\n\t\"  20 (BC_2, *, internal, X),\" &\n\t\"  21 (BC_2, *, internal, X),\" &\n\t\"  22 (BC_2, *, internal, X),\" &\n\t\"  23 (BC_2, *, internal, X),\" &\n\t\"  24 (BC_2, *, internal, X),\" &\n\t\"  25 (BC_2, *, internal, X),\" &\n\t\"  26 (BC_2, *, internal, X),\" &\n\t\"  27 (BC_2, *, internal, X),\" &\n\t\"  28 (BC_2, *, internal, X),\" &\n\t\"  29 (BC_2, *, internal, X),\" &\n\t\"  30 (BC_2, *, internal, X),\" &\n\t\"  31 (BC_2, *, internal, X),\" &\n\t\"  32 (BC_2, *, internal, X),\" &\n\t\"  33 (BC_2, *, internal, X),\" &\n\t\"  34 (BC_2, *, internal, X),\" &\n\t\"  35 (BC_2, *, internal, X),\" &\n\t\"  36 (BC_2, *, internal, X),\" &\n\t\"  37 (BC_2, *, internal, X),\" &\n\t\"  38 (BC_2, *, internal, X),\" &\n\t\"  39 (BC_2, *, internal, X),\" &\n\t\"  40 (BC_2, *, internal, X),\" &\n\t\"  41 (BC_2, *, internal, X),\" &\n\t\"  42 (BC_2, *, internal, X),\" &\n\t\"  43 (BC_2, *, internal, X),\" &\n\t\"  44 (BC_2, *, internal, X),\" &\n\t\"  45 (BC_2, *, internal, 1),\" & --  PAD1000.T\n\t\"  46 (BC_2, *, internal, X),\" & --  PAD1000.O\n\t\"  47 (BC_2, *, internal, X),\" & --  PAD1000.I\n\t\"  48 (BC_2, *, internal, 1),\" & --  PAD999.T\n\t\"  49 (BC_2, *, internal, X),\" & --  PAD999.O\n\t\"  50 (BC_2, *, internal, X),\" & --  PAD999.I\n\t\"  51 (BC_2, *, internal, 1),\" & --  PAD998.T\n\t\"  52 (BC_2, *, internal, X),\" & --  PAD998.O\n\t\"  53 (BC_2, *, internal, X),\" & --  PAD998.I\n\t\"  54 (BC_2, *, internal, 1),\" & --  PAD997.T\n\t\"  55 (BC_2, *, internal, X),\" & --  PAD997.O\n\t\"  56 (BC_2, *, internal, X),\" & --  PAD997.I\n\t\"  57 (BC_2, *, internal, 1),\" & --  PAD996.T\n\t\"  58 (BC_2, *, internal, X),\" & --  PAD996.O\n\t\"  59 (BC_2, *, internal, X),\" & --  PAD996.I\n\t\"  60 (BC_2, *, internal, 1),\" & --  PAD995.T\n\t\"  61 (BC_2, *, internal, X),\" & --  PAD995.O\n\t\"  62 (BC_2, *, internal, X),\" & --  PAD995.I\n\t\"  63 (BC_2, *, internal, 1),\" & --  PAD994.T\n\t\"  64 (BC_2, *, internal, X),\" & --  PAD994.O\n\t\"  65 (BC_2, *, internal, X),\" & --  PAD994.I\n\t\"  66 (BC_2, *, internal, 1),\" & --  PAD993.T\n\t\"  67 (BC_2, *, internal, X),\" & --  PAD993.O\n\t\"  68 (BC_2, *, internal, X),\" & --  PAD993.I\n\t\"  69 (BC_2, *, internal, 1),\" & --  PAD992.T\n\t\"  70 (BC_2, *, internal, X),\" & --  PAD992.O\n\t\"  71 (BC_2, *, internal, X),\" & --  PAD992.I\n\t\"  72 (BC_2, *, internal, 1),\" & --  PAD991.T\n\t\"  73 (BC_2, *, internal, X),\" & --  PAD991.O\n\t\"  74 (BC_2, *, internal, X),\" & --  PAD991.I\n\t\"  75 (BC_2, *, internal, 1),\" & --  PAD990.T\n\t\"  76 (BC_2, *, internal, X),\" & --  PAD990.O\n\t\"  77 (BC_2, *, internal, X),\" & --  PAD990.I\n\t\"  78 (BC_2, *, internal, 1),\" & --  PAD989.T\n\t\"  79 (BC_2, *, internal, X),\" & --  PAD989.O\n\t\"  80 (BC_2, *, internal, X),\" & --  PAD989.I\n\t\"  81 (BC_2, *, internal, 1),\" & --  PAD988.T\n\t\"  82 (BC_2, *, internal, X),\" & --  PAD988.O\n\t\"  83 (BC_2, *, internal, X),\" & --  PAD988.I\n\t\"  84 (BC_2, *, internal, 1),\" & --  PAD987.T\n\t\"  85 (BC_2, *, internal, X),\" & --  PAD987.O\n\t\"  86 (BC_2, *, internal, X),\" & --  PAD987.I\n\t\"  87 (BC_2, *, internal, 1),\" & --  PAD986.T\n\t\"  88 (BC_2, *, internal, X),\" & --  PAD986.O\n\t\"  89 (BC_2, *, internal, X),\" & --  PAD986.I\n\t\"  90 (BC_2, *, internal, 1),\" & --  PAD985.T\n\t\"  91 (BC_2, *, internal, X),\" & --  PAD985.O\n\t\"  92 (BC_2, *, internal, X),\" & --  PAD985.I\n\t\"  93 (BC_2, *, internal, 1),\" & --  PAD984.T\n\t\"  94 (BC_2, *, internal, X),\" & --  PAD984.O\n\t\"  95 (BC_2, *, internal, X),\" & --  PAD984.I\n\t\"  96 (BC_2, *, internal, 1),\" & --  PAD983.T\n\t\"  97 (BC_2, *, internal, X),\" & --  PAD983.O\n\t\"  98 (BC_2, *, internal, X),\" & --  PAD983.I\n\t\"  99 (BC_2, *, internal, 1),\" & --  PAD982.T\n\t\" 100 (BC_2, *, internal, X),\" & --  PAD982.O\n\t\" 101 (BC_2, *, internal, X),\" & --  PAD982.I\n\t\" 102 (BC_2, *, internal, 1),\" & --  PAD981.T\n\t\" 103 (BC_2, *, internal, X),\" & --  PAD981.O\n\t\" 104 (BC_2, *, internal, X),\" & --  PAD981.I\n\t\" 105 (BC_2, *, internal, 1),\" & --  PAD980.T\n\t\" 106 (BC_2, *, internal, X),\" & --  PAD980.O\n\t\" 107 (BC_2, *, internal, X),\" & --  PAD980.I\n\t\" 108 (BC_2, *, internal, 1),\" & --  PAD979.T\n\t\" 109 (BC_2, *, internal, X),\" & --  PAD979.O\n\t\" 110 (BC_2, *, internal, X),\" & --  PAD979.I\n\t\" 111 (BC_2, *, internal, 1),\" & --  PAD978.T\n\t\" 112 (BC_2, *, internal, X),\" & --  PAD978.O\n\t\" 113 (BC_2, *, internal, X),\" & --  PAD978.I\n\t\" 114 (BC_2, *, internal, 1),\" & --  PAD977.T\n\t\" 115 (BC_2, *, internal, X),\" & --  PAD977.O\n\t\" 116 (BC_2, *, internal, X),\" & --  PAD977.I\n\t\" 117 (BC_2, *, internal, 1),\" & --  PAD976.T\n\t\" 118 (BC_2, *, internal, X),\" & --  PAD976.O\n\t\" 119 (BC_2, *, internal, X),\" & --  PAD976.I\n\t\" 120 (BC_2, *, internal, 1),\" & --  PAD975.T\n\t\" 121 (BC_2, *, internal, X),\" & --  PAD975.O\n\t\" 122 (BC_2, *, internal, X),\" & --  PAD975.I\n\t\" 123 (BC_2, *, internal, 1),\" & --  PAD974.T\n\t\" 124 (BC_2, *, internal, X),\" & --  PAD974.O\n\t\" 125 (BC_2, *, internal, X),\" & --  PAD974.I\n\t\" 126 (BC_2, *, internal, 1),\" & --  PAD973.T\n\t\" 127 (BC_2, *, internal, X),\" & --  PAD973.O\n\t\" 128 (BC_2, *, internal, X),\" & --  PAD973.I\n\t\" 129 (BC_2, *, internal, 1),\" & --  PAD972.T\n\t\" 130 (BC_2, *, internal, X),\" & --  PAD972.O\n\t\" 131 (BC_2, *, internal, X),\" & --  PAD972.I\n\t\" 132 (BC_2, *, internal, 1),\" & --  PAD971.T\n\t\" 133 (BC_2, *, internal, X),\" & --  PAD971.O\n\t\" 134 (BC_2, *, internal, X),\" & --  PAD971.I\n\t\" 135 (BC_2, *, internal, 1),\" & --  PAD970.T\n\t\" 136 (BC_2, *, internal, X),\" & --  PAD970.O\n\t\" 137 (BC_2, *, internal, X),\" & --  PAD970.I\n\t\" 138 (BC_2, *, internal, 1),\" & --  PAD969.T\n\t\" 139 (BC_2, *, internal, X),\" & --  PAD969.O\n\t\" 140 (BC_2, *, internal, X),\" & --  PAD969.I\n\t\" 141 (BC_2, *, internal, 1),\" & --  PAD968.T\n\t\" 142 (BC_2, *, internal, X),\" & --  PAD968.O\n\t\" 143 (BC_2, *, internal, X),\" & --  PAD968.I\n\t\" 144 (BC_2, *, internal, 1),\" & --  PAD967.T\n\t\" 145 (BC_2, *, internal, X),\" & --  PAD967.O\n\t\" 146 (BC_2, *, internal, X),\" & --  PAD967.I\n\t\" 147 (BC_2, *, internal, 1),\" & --  PAD966.T\n\t\" 148 (BC_2, *, internal, X),\" & --  PAD966.O\n\t\" 149 (BC_2, *, internal, X),\" & --  PAD966.I\n\t\" 150 (BC_2, *, internal, 1),\" & --  PAD965.T\n\t\" 151 (BC_2, *, internal, X),\" & --  PAD965.O\n\t\" 152 (BC_2, *, internal, X),\" & --  PAD965.I\n\t\" 153 (BC_2, *, internal, 1),\" & --  PAD964.T\n\t\" 154 (BC_2, *, internal, X),\" & --  PAD964.O\n\t\" 155 (BC_2, *, internal, X),\" & --  PAD964.I\n\t\" 156 (BC_2, *, internal, 1),\" & --  PAD963.T\n\t\" 157 (BC_2, *, internal, X),\" & --  PAD963.O\n\t\" 158 (BC_2, *, internal, X),\" & --  PAD963.I\n\t\" 159 (BC_2, *, internal, 1),\" & --  PAD962.T\n\t\" 160 (BC_2, *, internal, X),\" & --  PAD962.O\n\t\" 161 (BC_2, *, internal, X),\" & --  PAD962.I\n\t\" 162 (BC_2, *, internal, 1),\" & --  PAD961.T\n\t\" 163 (BC_2, *, internal, X),\" & --  PAD961.O\n\t\" 164 (BC_2, *, internal, X),\" & --  PAD961.I\n\t\" 165 (BC_2, *, internal, 1),\" & --  PAD960.T\n\t\" 166 (BC_2, *, internal, X),\" & --  PAD960.O\n\t\" 167 (BC_2, *, internal, X),\" & --  PAD960.I\n\t\" 168 (BC_2, *, internal, 1),\" & --  PAD959.T\n\t\" 169 (BC_2, *, internal, X),\" & --  PAD959.O\n\t\" 170 (BC_2, *, internal, X),\" & --  PAD959.I\n\t\" 171 (BC_2, *, internal, 1),\" & --  PAD958.T\n\t\" 172 (BC_2, *, internal, X),\" & --  PAD958.O\n\t\" 173 (BC_2, *, internal, X),\" & --  PAD958.I\n\t\" 174 (BC_2, *, internal, 1),\" & --  PAD957.T\n\t\" 175 (BC_2, *, internal, X),\" & --  PAD957.O\n\t\" 176 (BC_2, *, internal, X),\" & --  PAD957.I\n\t\" 177 (BC_2, *, internal, 1),\" & --  PAD956.T\n\t\" 178 (BC_2, *, internal, X),\" & --  PAD956.O\n\t\" 179 (BC_2, *, internal, X),\" & --  PAD956.I\n\t\" 180 (BC_2, *, internal, 1),\" & --  PAD955.T\n\t\" 181 (BC_2, *, internal, X),\" & --  PAD955.O\n\t\" 182 (BC_2, *, internal, X),\" & --  PAD955.I\n\t\" 183 (BC_2, *, internal, 1),\" & --  PAD954.T\n\t\" 184 (BC_2, *, internal, X),\" & --  PAD954.O\n\t\" 185 (BC_2, *, internal, X),\" & --  PAD954.I\n\t\" 186 (BC_2, *, internal, 1),\" & --  PAD953.T\n\t\" 187 (BC_2, *, internal, X),\" & --  PAD953.O\n\t\" 188 (BC_2, *, internal, X),\" & --  PAD953.I\n\t\" 189 (BC_2, *, internal, 1),\" & --  PAD952.T\n\t\" 190 (BC_2, *, internal, X),\" & --  PAD952.O\n\t\" 191 (BC_2, *, internal, X),\" & --  PAD952.I\n\t\" 192 (BC_2, *, internal, 1),\" & --  PAD951.T\n\t\" 193 (BC_2, *, internal, X),\" & --  PAD951.O\n\t\" 194 (BC_2, *, internal, X),\" & --  PAD951.I\n\t\" 195 (BC_2, *, controlr, 1),\" &\n\t\" 196 (BC_2, IO_AP15, output3, X, 195, 1, Z),\" & --  PAD950\n\t\" 197 (BC_2, IO_AP15, input, X),\" & --  PAD950\n\t\" 198 (BC_2, *, controlr, 1),\" &\n\t\" 199 (BC_2, IO_BB12, output3, X, 198, 1, Z),\" & --  PAD949\n\t\" 200 (BC_2, IO_BB12, input, X),\" & --  PAD949\n\t\" 201 (BC_2, *, controlr, 1),\" &\n\t\" 202 (BC_2, IO_BA12, output3, X, 201, 1, Z),\" & --  PAD948\n\t\" 203 (BC_2, IO_BA12, input, X),\" & --  PAD948\n\t\" 204 (BC_2, *, controlr, 1),\" &\n\t\" 205 (BC_2, IO_BB13, output3, X, 204, 1, Z),\" & --  PAD947\n\t\" 206 (BC_2, IO_BB13, input, X),\" & --  PAD947\n\t\" 207 (BC_2, *, controlr, 1),\" &\n\t\" 208 (BC_2, IO_BB14, output3, X, 207, 1, Z),\" & --  PAD946\n\t\" 209 (BC_2, IO_BB14, input, X),\" & --  PAD946\n\t\" 210 (BC_2, *, controlr, 1),\" &\n\t\" 211 (BC_2, IO_AY13, output3, X, 210, 1, Z),\" & --  PAD945\n\t\" 212 (BC_2, IO_AY13, input, X),\" & --  PAD945\n\t\" 213 (BC_2, *, controlr, 1),\" &\n\t\" 214 (BC_2, IO_AY14, output3, X, 213, 1, Z),\" & --  PAD944\n\t\" 215 (BC_2, IO_AY14, input, X),\" & --  PAD944\n\t\" 216 (BC_2, *, controlr, 1),\" &\n\t\" 217 (BC_2, IO_BA14, output3, X, 216, 1, Z),\" & --  PAD943\n\t\" 218 (BC_2, IO_BA14, input, X),\" & --  PAD943\n\t\" 219 (BC_2, *, controlr, 1),\" &\n\t\" 220 (BC_2, IO_BA15, output3, X, 219, 1, Z),\" & --  PAD942\n\t\" 221 (BC_2, IO_BA15, input, X),\" & --  PAD942\n\t\" 222 (BC_2, *, controlr, 1),\" &\n\t\" 223 (BC_2, IO_AY12, output3, X, 222, 1, Z),\" & --  PAD941\n\t\" 224 (BC_2, IO_AY12, input, X),\" & --  PAD941\n\t\" 225 (BC_2, *, controlr, 1),\" &\n\t\" 226 (BC_2, IO_AW12, output3, X, 225, 1, Z),\" & --  PAD940\n\t\" 227 (BC_2, IO_AW12, input, X),\" & --  PAD940\n\t\" 228 (BC_2, *, controlr, 1),\" &\n\t\" 229 (BC_2, IO_AY15, output3, X, 228, 1, Z),\" & --  PAD939\n\t\" 230 (BC_2, IO_AY15, input, X),\" & --  PAD939\n\t\" 231 (BC_2, *, controlr, 1),\" &\n\t\" 232 (BC_2, IO_AW15, output3, X, 231, 1, Z),\" & --  PAD938\n\t\" 233 (BC_2, IO_AW15, input, X),\" & --  PAD938\n\t\" 234 (BC_2, *, controlr, 1),\" &\n\t\" 235 (BC_2, IO_AV14, output3, X, 234, 1, Z),\" & --  PAD937\n\t\" 236 (BC_2, IO_AV14, input, X),\" & --  PAD937\n\t\" 237 (BC_2, *, controlr, 1),\" &\n\t\" 238 (BC_2, IO_AV15, output3, X, 237, 1, Z),\" & --  PAD936\n\t\" 239 (BC_2, IO_AV15, input, X),\" & --  PAD936\n\t\" 240 (BC_2, *, controlr, 1),\" &\n\t\" 241 (BC_2, IO_AU12, output3, X, 240, 1, Z),\" & --  PAD935\n\t\" 242 (BC_2, IO_AU12, input, X),\" & --  PAD935\n\t\" 243 (BC_2, *, controlr, 1),\" &\n\t\" 244 (BC_2, IO_AT12, output3, X, 243, 1, Z),\" & --  PAD934\n\t\" 245 (BC_2, IO_AT12, input, X),\" & --  PAD934\n\t\" 246 (BC_2, *, controlr, 1),\" &\n\t\" 247 (BC_2, IO_AT15, output3, X, 246, 1, Z),\" & --  PAD933\n\t\" 248 (BC_2, IO_AT15, input, X),\" & --  PAD933\n\t\" 249 (BC_2, *, controlr, 1),\" &\n\t\" 250 (BC_2, IO_AR15, output3, X, 249, 1, Z),\" & --  PAD932\n\t\" 251 (BC_2, IO_AR15, input, X),\" & --  PAD932\n\t\" 252 (BC_2, *, controlr, 1),\" &\n\t\" 253 (BC_2, IO_AR12, output3, X, 252, 1, Z),\" & --  PAD931\n\t\" 254 (BC_2, IO_AR12, input, X),\" & --  PAD931\n\t\" 255 (BC_2, *, controlr, 1),\" &\n\t\" 256 (BC_2, IO_AP12, output3, X, 255, 1, Z),\" & --  PAD930\n\t\" 257 (BC_2, IO_AP12, input, X),\" & --  PAD930\n\t\" 258 (BC_2, *, controlr, 1),\" &\n\t\" 259 (BC_2, IO_AW13, output3, X, 258, 1, Z),\" & --  PAD929\n\t\" 260 (BC_2, IO_AW13, input, X),\" & --  PAD929\n\t\" 261 (BC_2, *, controlr, 1),\" &\n\t\" 262 (BC_2, IO_AV13, output3, X, 261, 1, Z),\" & --  PAD928\n\t\" 263 (BC_2, IO_AV13, input, X),\" & --  PAD928\n\t\" 264 (BC_2, *, controlr, 1),\" &\n\t\" 265 (BC_2, IO_AU13, output3, X, 264, 1, Z),\" & --  PAD927\n\t\" 266 (BC_2, IO_AU13, input, X),\" & --  PAD927\n\t\" 267 (BC_2, *, controlr, 1),\" &\n\t\" 268 (BC_2, IO_AU14, output3, X, 267, 1, Z),\" & --  PAD926\n\t\" 269 (BC_2, IO_AU14, input, X),\" & --  PAD926\n\t\" 270 (BC_2, *, controlr, 1),\" &\n\t\" 271 (BC_2, IO_AR13, output3, X, 270, 1, Z),\" & --  PAD925\n\t\" 272 (BC_2, IO_AR13, input, X),\" & --  PAD925\n\t\" 273 (BC_2, *, controlr, 1),\" &\n\t\" 274 (BC_2, IO_AP13, output3, X, 273, 1, Z),\" & --  PAD924\n\t\" 275 (BC_2, IO_AP13, input, X),\" & --  PAD924\n\t\" 276 (BC_2, *, controlr, 1),\" &\n\t\" 277 (BC_2, IO_AT14, output3, X, 276, 1, Z),\" & --  PAD923\n\t\" 278 (BC_2, IO_AT14, input, X),\" & --  PAD923\n\t\" 279 (BC_2, *, controlr, 1),\" &\n\t\" 280 (BC_2, IO_AR14, output3, X, 279, 1, Z),\" & --  PAD922\n\t\" 281 (BC_2, IO_AR14, input, X),\" & --  PAD922\n\t\" 282 (BC_2, *, controlr, 1),\" &\n\t\" 283 (BC_2, IO_AP11, output3, X, 282, 1, Z),\" & --  PAD921\n\t\" 284 (BC_2, IO_AP11, input, X),\" & --  PAD921\n\t\" 285 (BC_2, *, controlr, 1),\" &\n\t\" 286 (BC_2, IO_AN11, output3, X, 285, 1, Z),\" & --  PAD920\n\t\" 287 (BC_2, IO_AN11, input, X),\" & --  PAD920\n\t\" 288 (BC_2, *, controlr, 1),\" &\n\t\" 289 (BC_2, IO_AN14, output3, X, 288, 1, Z),\" & --  PAD919\n\t\" 290 (BC_2, IO_AN14, input, X),\" & --  PAD919\n\t\" 291 (BC_2, *, controlr, 1),\" &\n\t\" 292 (BC_2, IO_AN15, output3, X, 291, 1, Z),\" & --  PAD918\n\t\" 293 (BC_2, IO_AN15, input, X),\" & --  PAD918\n\t\" 294 (BC_2, *, controlr, 1),\" &\n\t\" 295 (BC_2, IO_AM11, output3, X, 294, 1, Z),\" & --  PAD917\n\t\" 296 (BC_2, IO_AM11, input, X),\" & --  PAD917\n\t\" 297 (BC_2, *, controlr, 1),\" &\n\t\" 298 (BC_2, IO_AM12, output3, X, 297, 1, Z),\" & --  PAD916\n\t\" 299 (BC_2, IO_AM12, input, X),\" & --  PAD916\n\t\" 300 (BC_2, *, controlr, 1),\" &\n\t\" 301 (BC_2, IO_AN13, output3, X, 300, 1, Z),\" & --  PAD915\n\t\" 302 (BC_2, IO_AN13, input, X),\" & --  PAD915\n\t\" 303 (BC_2, *, controlr, 1),\" &\n\t\" 304 (BC_2, IO_AM13, output3, X, 303, 1, Z),\" & --  PAD914\n\t\" 305 (BC_2, IO_AM13, input, X),\" & --  PAD914\n\t\" 306 (BC_2, *, controlr, 1),\" &\n\t\" 307 (BC_2, IO_AL12, output3, X, 306, 1, Z),\" & --  PAD913\n\t\" 308 (BC_2, IO_AL12, input, X),\" & --  PAD913\n\t\" 309 (BC_2, *, controlr, 1),\" &\n\t\" 310 (BC_2, IO_AK12, output3, X, 309, 1, Z),\" & --  PAD912\n\t\" 311 (BC_2, IO_AK12, input, X),\" & --  PAD912\n\t\" 312 (BC_2, *, controlr, 1),\" &\n\t\" 313 (BC_2, IO_AL15, output3, X, 312, 1, Z),\" & --  PAD911\n\t\" 314 (BC_2, IO_AL15, input, X),\" & --  PAD911\n\t\" 315 (BC_2, *, controlr, 1),\" &\n\t\" 316 (BC_2, IO_AL16, output3, X, 315, 1, Z),\" & --  PAD910\n\t\" 317 (BC_2, IO_AL16, input, X),\" & --  PAD910\n\t\" 318 (BC_2, *, controlr, 1),\" &\n\t\" 319 (BC_2, IO_AJ12, output3, X, 318, 1, Z),\" & --  PAD909\n\t\" 320 (BC_2, IO_AJ12, input, X),\" & --  PAD909\n\t\" 321 (BC_2, *, controlr, 1),\" &\n\t\" 322 (BC_2, IO_AJ13, output3, X, 321, 1, Z),\" & --  PAD908\n\t\" 323 (BC_2, IO_AJ13, input, X),\" & --  PAD908\n\t\" 324 (BC_2, *, controlr, 1),\" &\n\t\" 325 (BC_2, IO_AL14, output3, X, 324, 1, Z),\" & --  PAD907\n\t\" 326 (BC_2, IO_AL14, input, X),\" & --  PAD907\n\t\" 327 (BC_2, *, controlr, 1),\" &\n\t\" 328 (BC_2, IO_AK15, output3, X, 327, 1, Z),\" & --  PAD906\n\t\" 329 (BC_2, IO_AK15, input, X),\" & --  PAD906\n\t\" 330 (BC_2, *, controlr, 1),\" &\n\t\" 331 (BC_2, IO_AK13, output3, X, 330, 1, Z),\" & --  PAD905\n\t\" 332 (BC_2, IO_AK13, input, X),\" & --  PAD905\n\t\" 333 (BC_2, *, controlr, 1),\" &\n\t\" 334 (BC_2, IO_AK14, output3, X, 333, 1, Z),\" & --  PAD904\n\t\" 335 (BC_2, IO_AK14, input, X),\" & --  PAD904\n\t\" 336 (BC_2, *, controlr, 1),\" &\n\t\" 337 (BC_2, IO_AJ15, output3, X, 336, 1, Z),\" & --  PAD903\n\t\" 338 (BC_2, IO_AJ15, input, X),\" & --  PAD903\n\t\" 339 (BC_2, *, controlr, 1),\" &\n\t\" 340 (BC_2, IO_AJ16, output3, X, 339, 1, Z),\" & --  PAD902\n\t\" 341 (BC_2, IO_AJ16, input, X),\" & --  PAD902\n\t\" 342 (BC_2, *, controlr, 1),\" &\n\t\" 343 (BC_2, IO_AM14, output3, X, 342, 1, Z),\" & --  PAD901\n\t\" 344 (BC_2, IO_AM14, input, X),\" & --  PAD901\n\t\" 345 (BC_2, *, controlr, 1),\" &\n\t\" 346 (BC_2, IO_AP16, output3, X, 345, 1, Z),\" & --  PAD900\n\t\" 347 (BC_2, IO_AP16, input, X),\" & --  PAD900\n\t\" 348 (BC_2, *, controlr, 1),\" &\n\t\" 349 (BC_2, IO_BA19, output3, X, 348, 1, Z),\" & --  PAD899\n\t\" 350 (BC_2, IO_BA19, input, X),\" & --  PAD899\n\t\" 351 (BC_2, *, controlr, 1),\" &\n\t\" 352 (BC_2, IO_AY19, output3, X, 351, 1, Z),\" & --  PAD898\n\t\" 353 (BC_2, IO_AY19, input, X),\" & --  PAD898\n\t\" 354 (BC_2, *, controlr, 1),\" &\n\t\" 355 (BC_2, IO_BB16, output3, X, 354, 1, Z),\" & --  PAD897\n\t\" 356 (BC_2, IO_BB16, input, X),\" & --  PAD897\n\t\" 357 (BC_2, *, controlr, 1),\" &\n\t\" 358 (BC_2, IO_BA16, output3, X, 357, 1, Z),\" & --  PAD896\n\t\" 359 (BC_2, IO_BA16, input, X),\" & --  PAD896\n\t\" 360 (BC_2, *, controlr, 1),\" &\n\t\" 361 (BC_2, IO_BA20, output3, X, 360, 1, Z),\" & --  PAD895\n\t\" 362 (BC_2, IO_BA20, input, X),\" & --  PAD895\n\t\" 363 (BC_2, *, controlr, 1),\" &\n\t\" 364 (BC_2, IO_AY20, output3, X, 363, 1, Z),\" & --  PAD894\n\t\" 365 (BC_2, IO_AY20, input, X),\" & --  PAD894\n\t\" 366 (BC_2, *, controlr, 1),\" &\n\t\" 367 (BC_2, IO_BB17, output3, X, 366, 1, Z),\" & --  PAD893\n\t\" 368 (BC_2, IO_BB17, input, X),\" & --  PAD893\n\t\" 369 (BC_2, *, controlr, 1),\" &\n\t\" 370 (BC_2, IO_BA17, output3, X, 369, 1, Z),\" & --  PAD892\n\t\" 371 (BC_2, IO_BA17, input, X),\" & --  PAD892\n\t\" 372 (BC_2, *, controlr, 1),\" &\n\t\" 373 (BC_2, IO_AW20, output3, X, 372, 1, Z),\" & --  PAD891\n\t\" 374 (BC_2, IO_AW20, input, X),\" & --  PAD891\n\t\" 375 (BC_2, *, controlr, 1),\" &\n\t\" 376 (BC_2, IO_AV20, output3, X, 375, 1, Z),\" & --  PAD890\n\t\" 377 (BC_2, IO_AV20, input, X),\" & --  PAD890\n\t\" 378 (BC_2, *, controlr, 1),\" &\n\t\" 379 (BC_2, IO_BB18, output3, X, 378, 1, Z),\" & --  PAD889\n\t\" 380 (BC_2, IO_BB18, input, X),\" & --  PAD889\n\t\" 381 (BC_2, *, controlr, 1),\" &\n\t\" 382 (BC_2, IO_BB19, output3, X, 381, 1, Z),\" & --  PAD888\n\t\" 383 (BC_2, IO_BB19, input, X),\" & --  PAD888\n\t\" 384 (BC_2, *, controlr, 1),\" &\n\t\" 385 (BC_2, IO_AU16, output3, X, 384, 1, Z),\" & --  PAD887\n\t\" 386 (BC_2, IO_AU16, input, X),\" & --  PAD887\n\t\" 387 (BC_2, *, controlr, 1),\" &\n\t\" 388 (BC_2, IO_AT16, output3, X, 387, 1, Z),\" & --  PAD886\n\t\" 389 (BC_2, IO_AT16, input, X),\" & --  PAD886\n\t\" 390 (BC_2, *, controlr, 1),\" &\n\t\" 391 (BC_2, IO_AW16, output3, X, 390, 1, Z),\" & --  PAD885\n\t\" 392 (BC_2, IO_AW16, input, X),\" & --  PAD885\n\t\" 393 (BC_2, *, controlr, 1),\" &\n\t\" 394 (BC_2, IO_AV16, output3, X, 393, 1, Z),\" & --  PAD884\n\t\" 395 (BC_2, IO_AV16, input, X),\" & --  PAD884\n\t\" 396 (BC_2, *, controlr, 1),\" &\n\t\" 397 (BC_2, IO_AT19, output3, X, 396, 1, Z),\" & --  PAD883\n\t\" 398 (BC_2, IO_AT19, input, X),\" & --  PAD883\n\t\" 399 (BC_2, *, controlr, 1),\" &\n\t\" 400 (BC_2, IO_AT20, output3, X, 399, 1, Z),\" & --  PAD882\n\t\" 401 (BC_2, IO_AT20, input, X),\" & --  PAD882\n\t\" 402 (BC_2, *, controlr, 1),\" &\n\t\" 403 (BC_2, IO_AV19, output3, X, 402, 1, Z),\" & --  PAD881\n\t\" 404 (BC_2, IO_AV19, input, X),\" & --  PAD881\n\t\" 405 (BC_2, *, controlr, 1),\" &\n\t\" 406 (BC_2, IO_AU19, output3, X, 405, 1, Z),\" & --  PAD880\n\t\" 407 (BC_2, IO_AU19, input, X),\" & --  PAD880\n\t\" 408 (BC_2, *, controlr, 1),\" &\n\t\" 409 (BC_2, IO_AW17, output3, X, 408, 1, Z),\" & --  PAD879\n\t\" 410 (BC_2, IO_AW17, input, X),\" & --  PAD879\n\t\" 411 (BC_2, *, controlr, 1),\" &\n\t\" 412 (BC_2, IO_AW18, output3, X, 411, 1, Z),\" & --  PAD878\n\t\" 413 (BC_2, IO_AW18, input, X),\" & --  PAD878\n\t\" 414 (BC_2, *, controlr, 1),\" &\n\t\" 415 (BC_2, IO_AY17, output3, X, 414, 1, Z),\" & --  PAD877\n\t\" 416 (BC_2, IO_AY17, input, X),\" & --  PAD877\n\t\" 417 (BC_2, *, controlr, 1),\" &\n\t\" 418 (BC_2, IO_AY18, output3, X, 417, 1, Z),\" & --  PAD876\n\t\" 419 (BC_2, IO_AY18, input, X),\" & --  PAD876\n\t\" 420 (BC_2, *, controlr, 1),\" &\n\t\" 421 (BC_2, IO_AU17, output3, X, 420, 1, Z),\" & --  PAD875\n\t\" 422 (BC_2, IO_AU17, input, X),\" & --  PAD875\n\t\" 423 (BC_2, *, controlr, 1),\" &\n\t\" 424 (BC_2, IO_AT17, output3, X, 423, 1, Z),\" & --  PAD874\n\t\" 425 (BC_2, IO_AT17, input, X),\" & --  PAD874\n\t\" 426 (BC_2, *, controlr, 1),\" &\n\t\" 427 (BC_2, IO_AV18, output3, X, 426, 1, Z),\" & --  PAD873\n\t\" 428 (BC_2, IO_AV18, input, X),\" & --  PAD873\n\t\" 429 (BC_2, *, controlr, 1),\" &\n\t\" 430 (BC_2, IO_AU18, output3, X, 429, 1, Z),\" & --  PAD872\n\t\" 431 (BC_2, IO_AU18, input, X),\" & --  PAD872\n\t\" 432 (BC_2, *, controlr, 1),\" &\n\t\" 433 (BC_2, IO_AR17, output3, X, 432, 1, Z),\" & --  PAD871\n\t\" 434 (BC_2, IO_AR17, input, X),\" & --  PAD871\n\t\" 435 (BC_2, *, controlr, 1),\" &\n\t\" 436 (BC_2, IO_AR18, output3, X, 435, 1, Z),\" & --  PAD870\n\t\" 437 (BC_2, IO_AR18, input, X),\" & --  PAD870\n\t\" 438 (BC_2, *, controlr, 1),\" &\n\t\" 439 (BC_2, IO_AN18, output3, X, 438, 1, Z),\" & --  PAD869\n\t\" 440 (BC_2, IO_AN18, input, X),\" & --  PAD869\n\t\" 441 (BC_2, *, controlr, 1),\" &\n\t\" 442 (BC_2, IO_AN19, output3, X, 441, 1, Z),\" & --  PAD868\n\t\" 443 (BC_2, IO_AN19, input, X),\" & --  PAD868\n\t\" 444 (BC_2, *, controlr, 1),\" &\n\t\" 445 (BC_2, IO_AR19, output3, X, 444, 1, Z),\" & --  PAD867\n\t\" 446 (BC_2, IO_AR19, input, X),\" & --  PAD867\n\t\" 447 (BC_2, *, controlr, 1),\" &\n\t\" 448 (BC_2, IO_AP20, output3, X, 447, 1, Z),\" & --  PAD866\n\t\" 449 (BC_2, IO_AP20, input, X),\" & --  PAD866\n\t\" 450 (BC_2, *, controlr, 1),\" &\n\t\" 451 (BC_2, IO_AP17, output3, X, 450, 1, Z),\" & --  PAD865\n\t\" 452 (BC_2, IO_AP17, input, X),\" & --  PAD865\n\t\" 453 (BC_2, *, controlr, 1),\" &\n\t\" 454 (BC_2, IO_AP18, output3, X, 453, 1, Z),\" & --  PAD864\n\t\" 455 (BC_2, IO_AP18, input, X),\" & --  PAD864\n\t\" 456 (BC_2, *, controlr, 1),\" &\n\t\" 457 (BC_2, IO_AJ17, output3, X, 456, 1, Z),\" & --  PAD863\n\t\" 458 (BC_2, IO_AJ17, input, X),\" & --  PAD863\n\t\" 459 (BC_2, *, controlr, 1),\" &\n\t\" 460 (BC_2, IO_AJ18, output3, X, 459, 1, Z),\" & --  PAD862\n\t\" 461 (BC_2, IO_AJ18, input, X),\" & --  PAD862\n\t\" 462 (BC_2, *, controlr, 1),\" &\n\t\" 463 (BC_2, IO_AN16, output3, X, 462, 1, Z),\" & --  PAD861\n\t\" 464 (BC_2, IO_AN16, input, X),\" & --  PAD861\n\t\" 465 (BC_2, *, controlr, 1),\" &\n\t\" 466 (BC_2, IO_AM16, output3, X, 465, 1, Z),\" & --  PAD860\n\t\" 467 (BC_2, IO_AM16, input, X),\" & --  PAD860\n\t\" 468 (BC_2, *, controlr, 1),\" &\n\t\" 469 (BC_2, IO_AK18, output3, X, 468, 1, Z),\" & --  PAD859\n\t\" 470 (BC_2, IO_AK18, input, X),\" & --  PAD859\n\t\" 471 (BC_2, *, controlr, 1),\" &\n\t\" 472 (BC_2, IO_AK19, output3, X, 471, 1, Z),\" & --  PAD858\n\t\" 473 (BC_2, IO_AK19, input, X),\" & --  PAD858\n\t\" 474 (BC_2, *, controlr, 1),\" &\n\t\" 475 (BC_2, IO_AM17, output3, X, 474, 1, Z),\" & --  PAD857\n\t\" 476 (BC_2, IO_AM17, input, X),\" & --  PAD857\n\t\" 477 (BC_2, *, controlr, 1),\" &\n\t\" 478 (BC_2, IO_AM18, output3, X, 477, 1, Z),\" & --  PAD856\n\t\" 479 (BC_2, IO_AM18, input, X),\" & --  PAD856\n\t\" 480 (BC_2, *, controlr, 1),\" &\n\t\" 481 (BC_2, IO_AL17, output3, X, 480, 1, Z),\" & --  PAD855\n\t\" 482 (BC_2, IO_AL17, input, X),\" & --  PAD855\n\t\" 483 (BC_2, *, controlr, 1),\" &\n\t\" 484 (BC_2, IO_AK17, output3, X, 483, 1, Z),\" & --  PAD854\n\t\" 485 (BC_2, IO_AK17, input, X),\" & --  PAD854\n\t\" 486 (BC_2, *, controlr, 1),\" &\n\t\" 487 (BC_2, IO_AM19, output3, X, 486, 1, Z),\" & --  PAD853\n\t\" 488 (BC_2, IO_AM19, input, X),\" & --  PAD853\n\t\" 489 (BC_2, *, controlr, 1),\" &\n\t\" 490 (BC_2, IO_AL19, output3, X, 489, 1, Z),\" & --  PAD852\n\t\" 491 (BC_2, IO_AL19, input, X),\" & --  PAD852\n\t\" 492 (BC_2, *, controlr, 1),\" &\n\t\" 493 (BC_2, IO_AR20, output3, X, 492, 1, Z),\" & --  PAD851\n\t\" 494 (BC_2, IO_AR20, input, X),\" & --  PAD851\n\t\" 495 (BC_2, *, controlr, 1),\" &\n\t\" 496 (BC_2, IO_AN20, output3, X, 495, 1, Z),\" & --  PAD850\n\t\" 497 (BC_2, IO_AN20, input, X),\" & --  PAD850\n\t\" 498 (BC_2, *, controlr, 1),\" &\n\t\" 499 (BC_2, IO_BB23, output3, X, 498, 1, Z),\" & --  PAD849\n\t\" 500 (BC_2, IO_BB23, input, X),\" & --  PAD849\n\t\" 501 (BC_2, *, controlr, 1),\" &\n\t\" 502 (BC_2, IO_BB24, output3, X, 501, 1, Z),\" & --  PAD848\n\t\" 503 (BC_2, IO_BB24, input, X),\" & --  PAD848\n\t\" 504 (BC_2, *, controlr, 1),\" &\n\t\" 505 (BC_2, IO_BB21, output3, X, 504, 1, Z),\" & --  PAD847\n\t\" 506 (BC_2, IO_BB21, input, X),\" & --  PAD847\n\t\" 507 (BC_2, *, controlr, 1),\" &\n\t\" 508 (BC_2, IO_BA21, output3, X, 507, 1, Z),\" & --  PAD846\n\t\" 509 (BC_2, IO_BA21, input, X),\" & --  PAD846\n\t\" 510 (BC_2, *, controlr, 1),\" &\n\t\" 511 (BC_2, IO_BA24, output3, X, 510, 1, Z),\" & --  PAD845\n\t\" 512 (BC_2, IO_BA24, input, X),\" & --  PAD845\n\t\" 513 (BC_2, *, controlr, 1),\" &\n\t\" 514 (BC_2, IO_AY24, output3, X, 513, 1, Z),\" & --  PAD844\n\t\" 515 (BC_2, IO_AY24, input, X),\" & --  PAD844\n\t\" 516 (BC_2, *, controlr, 1),\" &\n\t\" 517 (BC_2, IO_BB22, output3, X, 516, 1, Z),\" & --  PAD843\n\t\" 518 (BC_2, IO_BB22, input, X),\" & --  PAD843\n\t\" 519 (BC_2, *, controlr, 1),\" &\n\t\" 520 (BC_2, IO_BA22, output3, X, 519, 1, Z),\" & --  PAD842\n\t\" 521 (BC_2, IO_BA22, input, X),\" & --  PAD842\n\t\" 522 (BC_2, *, controlr, 1),\" &\n\t\" 523 (BC_2, IO_BA25, output3, X, 522, 1, Z),\" & --  PAD841\n\t\" 524 (BC_2, IO_BA25, input, X),\" & --  PAD841\n\t\" 525 (BC_2, *, controlr, 1),\" &\n\t\" 526 (BC_2, IO_AY25, output3, X, 525, 1, Z),\" & --  PAD840\n\t\" 527 (BC_2, IO_AY25, input, X),\" & --  PAD840\n\t\" 528 (BC_2, *, controlr, 1),\" &\n\t\" 529 (BC_2, IO_AY22, output3, X, 528, 1, Z),\" & --  PAD839\n\t\" 530 (BC_2, IO_AY22, input, X),\" & --  PAD839\n\t\" 531 (BC_2, *, controlr, 1),\" &\n\t\" 532 (BC_2, IO_AY23, output3, X, 531, 1, Z),\" & --  PAD838\n\t\" 533 (BC_2, IO_AY23, input, X),\" & --  PAD838\n\t\" 534 (BC_2, *, controlr, 1),\" &\n\t\" 535 (BC_2, IO_AV24, output3, X, 534, 1, Z),\" & --  PAD837\n\t\" 536 (BC_2, IO_AV24, input, X),\" & --  PAD837\n\t\" 537 (BC_2, *, controlr, 1),\" &\n\t\" 538 (BC_2, IO_AU24, output3, X, 537, 1, Z),\" & --  PAD836\n\t\" 539 (BC_2, IO_AU24, input, X),\" & --  PAD836\n\t\" 540 (BC_2, *, controlr, 1),\" &\n\t\" 541 (BC_2, IO_AW21, output3, X, 540, 1, Z),\" & --  PAD835\n\t\" 542 (BC_2, IO_AW21, input, X),\" & --  PAD835\n\t\" 543 (BC_2, *, controlr, 1),\" &\n\t\" 544 (BC_2, IO_AV21, output3, X, 543, 1, Z),\" & --  PAD834\n\t\" 545 (BC_2, IO_AV21, input, X),\" & --  PAD834\n\t\" 546 (BC_2, *, controlr, 1),\" &\n\t\" 547 (BC_2, IO_AT24, output3, X, 546, 1, Z),\" & --  PAD833\n\t\" 548 (BC_2, IO_AT24, input, X),\" & --  PAD833\n\t\" 549 (BC_2, *, controlr, 1),\" &\n\t\" 550 (BC_2, IO_AR24, output3, X, 549, 1, Z),\" & --  PAD832\n\t\" 551 (BC_2, IO_AR24, input, X),\" & --  PAD832\n\t\" 552 (BC_2, *, controlr, 1),\" &\n\t\" 553 (BC_2, IO_AU21, output3, X, 552, 1, Z),\" & --  PAD831\n\t\" 554 (BC_2, IO_AU21, input, X),\" & --  PAD831\n\t\" 555 (BC_2, *, controlr, 1),\" &\n\t\" 556 (BC_2, IO_AT21, output3, X, 555, 1, Z),\" & --  PAD830\n\t\" 557 (BC_2, IO_AT21, input, X),\" & --  PAD830\n\t\" 558 (BC_2, *, controlr, 1),\" &\n\t\" 559 (BC_2, IO_AW22, output3, X, 558, 1, Z),\" & --  PAD829\n\t\" 560 (BC_2, IO_AW22, input, X),\" & --  PAD829\n\t\" 561 (BC_2, *, controlr, 1),\" &\n\t\" 562 (BC_2, IO_AW23, output3, X, 561, 1, Z),\" & --  PAD828\n\t\" 563 (BC_2, IO_AW23, input, X),\" & --  PAD828\n\t\" 564 (BC_2, *, controlr, 1),\" &\n\t\" 565 (BC_2, IO_AV23, output3, X, 564, 1, Z),\" & --  PAD827\n\t\" 566 (BC_2, IO_AV23, input, X),\" & --  PAD827\n\t\" 567 (BC_2, *, controlr, 1),\" &\n\t\" 568 (BC_2, IO_AU23, output3, X, 567, 1, Z),\" & --  PAD826\n\t\" 569 (BC_2, IO_AU23, input, X),\" & --  PAD826\n\t\" 570 (BC_2, *, controlr, 1),\" &\n\t\" 571 (BC_2, IO_AU22, output3, X, 570, 1, Z),\" & --  PAD825\n\t\" 572 (BC_2, IO_AU22, input, X),\" & --  PAD825\n\t\" 573 (BC_2, *, controlr, 1),\" &\n\t\" 574 (BC_2, IO_AT22, output3, X, 573, 1, Z),\" & --  PAD824\n\t\" 575 (BC_2, IO_AT22, input, X),\" & --  PAD824\n\t\" 576 (BC_2, *, controlr, 1),\" &\n\t\" 577 (BC_2, IO_AR22, output3, X, 576, 1, Z),\" & --  PAD823\n\t\" 578 (BC_2, IO_AR22, input, X),\" & --  PAD823\n\t\" 579 (BC_2, *, controlr, 1),\" &\n\t\" 580 (BC_2, IO_AR23, output3, X, 579, 1, Z),\" & --  PAD822\n\t\" 581 (BC_2, IO_AR23, input, X),\" & --  PAD822\n\t\" 582 (BC_2, *, controlr, 1),\" &\n\t\" 583 (BC_2, IO_AP21, output3, X, 582, 1, Z),\" & --  PAD821\n\t\" 584 (BC_2, IO_AP21, input, X),\" & --  PAD821\n\t\" 585 (BC_2, *, controlr, 1),\" &\n\t\" 586 (BC_2, IO_AN21, output3, X, 585, 1, Z),\" & --  PAD820\n\t\" 587 (BC_2, IO_AN21, input, X),\" & --  PAD820\n\t\" 588 (BC_2, *, controlr, 1),\" &\n\t\" 589 (BC_2, IO_AP22, output3, X, 588, 1, Z),\" & --  PAD819\n\t\" 590 (BC_2, IO_AP22, input, X),\" & --  PAD819\n\t\" 591 (BC_2, *, controlr, 1),\" &\n\t\" 592 (BC_2, IO_AP23, output3, X, 591, 1, Z),\" & --  PAD818\n\t\" 593 (BC_2, IO_AP23, input, X),\" & --  PAD818\n\t\" 594 (BC_2, *, controlr, 1),\" &\n\t\" 595 (BC_2, IO_AN23, output3, X, 594, 1, Z),\" & --  PAD817\n\t\" 596 (BC_2, IO_AN23, input, X),\" & --  PAD817\n\t\" 597 (BC_2, *, controlr, 1),\" &\n\t\" 598 (BC_2, IO_AM23, output3, X, 597, 1, Z),\" & --  PAD816\n\t\" 599 (BC_2, IO_AM23, input, X),\" & --  PAD816\n\t\" 600 (BC_2, *, controlr, 1),\" &\n\t\" 601 (BC_2, IO_AN24, output3, X, 600, 1, Z),\" & --  PAD815\n\t\" 602 (BC_2, IO_AN24, input, X),\" & --  PAD815\n\t\" 603 (BC_2, *, controlr, 1),\" &\n\t\" 604 (BC_2, IO_AM24, output3, X, 603, 1, Z),\" & --  PAD814\n\t\" 605 (BC_2, IO_AM24, input, X),\" & --  PAD814\n\t\" 606 (BC_2, *, controlr, 1),\" &\n\t\" 607 (BC_2, IO_AM22, output3, X, 606, 1, Z),\" & --  PAD813\n\t\" 608 (BC_2, IO_AM22, input, X),\" & --  PAD813\n\t\" 609 (BC_2, *, controlr, 1),\" &\n\t\" 610 (BC_2, IO_AL22, output3, X, 609, 1, Z),\" & --  PAD812\n\t\" 611 (BC_2, IO_AL22, input, X),\" & --  PAD812\n\t\" 612 (BC_2, *, controlr, 1),\" &\n\t\" 613 (BC_2, IO_AJ20, output3, X, 612, 1, Z),\" & --  PAD811\n\t\" 614 (BC_2, IO_AJ20, input, X),\" & --  PAD811\n\t\" 615 (BC_2, *, controlr, 1),\" &\n\t\" 616 (BC_2, IO_AJ21, output3, X, 615, 1, Z),\" & --  PAD810\n\t\" 617 (BC_2, IO_AJ21, input, X),\" & --  PAD810\n\t\" 618 (BC_2, *, controlr, 1),\" &\n\t\" 619 (BC_2, IO_AM21, output3, X, 618, 1, Z),\" & --  PAD809\n\t\" 620 (BC_2, IO_AM21, input, X),\" & --  PAD809\n\t\" 621 (BC_2, *, controlr, 1),\" &\n\t\" 622 (BC_2, IO_AL21, output3, X, 621, 1, Z),\" & --  PAD808\n\t\" 623 (BC_2, IO_AL21, input, X),\" & --  PAD808\n\t\" 624 (BC_2, *, controlr, 1),\" &\n\t\" 625 (BC_2, IO_AK22, output3, X, 624, 1, Z),\" & --  PAD807\n\t\" 626 (BC_2, IO_AK22, input, X),\" & --  PAD807\n\t\" 627 (BC_2, *, controlr, 1),\" &\n\t\" 628 (BC_2, IO_AJ22, output3, X, 627, 1, Z),\" & --  PAD806\n\t\" 629 (BC_2, IO_AJ22, input, X),\" & --  PAD806\n\t\" 630 (BC_2, *, controlr, 1),\" &\n\t\" 631 (BC_2, IO_AL20, output3, X, 630, 1, Z),\" & --  PAD805\n\t\" 632 (BC_2, IO_AL20, input, X),\" & --  PAD805\n\t\" 633 (BC_2, *, controlr, 1),\" &\n\t\" 634 (BC_2, IO_AK20, output3, X, 633, 1, Z),\" & --  PAD804\n\t\" 635 (BC_2, IO_AK20, input, X),\" & --  PAD804\n\t\" 636 (BC_2, *, controlr, 1),\" &\n\t\" 637 (BC_2, IO_AK23, output3, X, 636, 1, Z),\" & --  PAD803\n\t\" 638 (BC_2, IO_AK23, input, X),\" & --  PAD803\n\t\" 639 (BC_2, *, controlr, 1),\" &\n\t\" 640 (BC_2, IO_AJ23, output3, X, 639, 1, Z),\" & --  PAD802\n\t\" 641 (BC_2, IO_AJ23, input, X),\" & --  PAD802\n\t\" 642 (BC_2, *, controlr, 1),\" &\n\t\" 643 (BC_2, IO_AL24, output3, X, 642, 1, Z),\" & --  PAD801\n\t\" 644 (BC_2, IO_AL24, input, X),\" & --  PAD801\n\t\" 645 (BC_2, *, controlr, 1),\" &\n\t\" 646 (BC_2, IO_U28, output3, X, 645, 1, Z),\" & --  PAD800\n\t\" 647 (BC_2, IO_U28, input, X),\" & --  PAD800\n\t\" 648 (BC_2, *, controlr, 1),\" &\n\t\" 649 (BC_2, IO_Y30, output3, X, 648, 1, Z),\" & --  PAD799\n\t\" 650 (BC_2, IO_Y30, input, X),\" & --  PAD799\n\t\" 651 (BC_2, *, controlr, 1),\" &\n\t\" 652 (BC_2, IO_Y29, output3, X, 651, 1, Z),\" & --  PAD798\n\t\" 653 (BC_2, IO_Y29, input, X),\" & --  PAD798\n\t\" 654 (BC_2, *, controlr, 1),\" &\n\t\" 655 (BC_2, IO_U29, output3, X, 654, 1, Z),\" & --  PAD797\n\t\" 656 (BC_2, IO_U29, input, X),\" & --  PAD797\n\t\" 657 (BC_2, *, controlr, 1),\" &\n\t\" 658 (BC_2, IO_V29, output3, X, 657, 1, Z),\" & --  PAD796\n\t\" 659 (BC_2, IO_V29, input, X),\" & --  PAD796\n\t\" 660 (BC_2, *, controlr, 1),\" &\n\t\" 661 (BC_2, IO_W31, output3, X, 660, 1, Z),\" & --  PAD795\n\t\" 662 (BC_2, IO_W31, input, X),\" & --  PAD795\n\t\" 663 (BC_2, *, controlr, 1),\" &\n\t\" 664 (BC_2, IO_W30, output3, X, 663, 1, Z),\" & --  PAD794\n\t\" 665 (BC_2, IO_W30, input, X),\" & --  PAD794\n\t\" 666 (BC_2, *, controlr, 1),\" &\n\t\" 667 (BC_2, IO_T30, output3, X, 666, 1, Z),\" & --  PAD793\n\t\" 668 (BC_2, IO_T30, input, X),\" & --  PAD793\n\t\" 669 (BC_2, *, controlr, 1),\" &\n\t\" 670 (BC_2, IO_T29, output3, X, 669, 1, Z),\" & --  PAD792\n\t\" 671 (BC_2, IO_T29, input, X),\" & --  PAD792\n\t\" 672 (BC_2, *, controlr, 1),\" &\n\t\" 673 (BC_2, IO_V31, output3, X, 672, 1, Z),\" & --  PAD791\n\t\" 674 (BC_2, IO_V31, input, X),\" & --  PAD791\n\t\" 675 (BC_2, *, controlr, 1),\" &\n\t\" 676 (BC_2, IO_V30, output3, X, 675, 1, Z),\" & --  PAD790\n\t\" 677 (BC_2, IO_V30, input, X),\" & --  PAD790\n\t\" 678 (BC_2, *, controlr, 1),\" &\n\t\" 679 (BC_2, IO_T31, output3, X, 678, 1, Z),\" & --  PAD789\n\t\" 680 (BC_2, IO_T31, input, X),\" & --  PAD789\n\t\" 681 (BC_2, *, controlr, 1),\" &\n\t\" 682 (BC_2, IO_U31, output3, X, 681, 1, Z),\" & --  PAD788\n\t\" 683 (BC_2, IO_U31, input, X),\" & --  PAD788\n\t\" 684 (BC_2, *, controlr, 1),\" &\n\t\" 685 (BC_2, IO_P31, output3, X, 684, 1, Z),\" & --  PAD787\n\t\" 686 (BC_2, IO_P31, input, X),\" & --  PAD787\n\t\" 687 (BC_2, *, controlr, 1),\" &\n\t\" 688 (BC_2, IO_R30, output3, X, 687, 1, Z),\" & --  PAD786\n\t\" 689 (BC_2, IO_R30, input, X),\" & --  PAD786\n\t\" 690 (BC_2, *, controlr, 1),\" &\n\t\" 691 (BC_2, IO_N29, output3, X, 690, 1, Z),\" & --  PAD785\n\t\" 692 (BC_2, IO_N29, input, X),\" & --  PAD785\n\t\" 693 (BC_2, *, controlr, 1),\" &\n\t\" 694 (BC_2, IO_N28, output3, X, 693, 1, Z),\" & --  PAD784\n\t\" 695 (BC_2, IO_N28, input, X),\" & --  PAD784\n\t\" 696 (BC_2, *, controlr, 1),\" &\n\t\" 697 (BC_2, IO_P28, output3, X, 696, 1, Z),\" & --  PAD783\n\t\" 698 (BC_2, IO_P28, input, X),\" & --  PAD783\n\t\" 699 (BC_2, *, controlr, 1),\" &\n\t\" 700 (BC_2, IO_R28, output3, X, 699, 1, Z),\" & --  PAD782\n\t\" 701 (BC_2, IO_R28, input, X),\" & --  PAD782\n\t\" 702 (BC_2, *, controlr, 1),\" &\n\t\" 703 (BC_2, IO_M29, output3, X, 702, 1, Z),\" & --  PAD781\n\t\" 704 (BC_2, IO_M29, input, X),\" & --  PAD781\n\t\" 705 (BC_2, *, controlr, 1),\" &\n\t\" 706 (BC_2, IO_M28, output3, X, 705, 1, Z),\" & --  PAD780\n\t\" 707 (BC_2, IO_M28, input, X),\" & --  PAD780\n\t\" 708 (BC_2, *, controlr, 1),\" &\n\t\" 709 (BC_2, IO_N31, output3, X, 708, 1, Z),\" & --  PAD779\n\t\" 710 (BC_2, IO_N31, input, X),\" & --  PAD779\n\t\" 711 (BC_2, *, controlr, 1),\" &\n\t\" 712 (BC_2, IO_P30, output3, X, 711, 1, Z),\" & --  PAD778\n\t\" 713 (BC_2, IO_P30, input, X),\" & --  PAD778\n\t\" 714 (BC_2, *, controlr, 1),\" &\n\t\" 715 (BC_2, IO_M31, output3, X, 714, 1, Z),\" & --  PAD777\n\t\" 716 (BC_2, IO_M31, input, X),\" & --  PAD777\n\t\" 717 (BC_2, *, controlr, 1),\" &\n\t\" 718 (BC_2, IO_N30, output3, X, 717, 1, Z),\" & --  PAD776\n\t\" 719 (BC_2, IO_N30, input, X),\" & --  PAD776\n\t\" 720 (BC_2, *, controlr, 1),\" &\n\t\" 721 (BC_2, IO_K32, output3, X, 720, 1, Z),\" & --  PAD775\n\t\" 722 (BC_2, IO_K32, input, X),\" & --  PAD775\n\t\" 723 (BC_2, *, controlr, 1),\" &\n\t\" 724 (BC_2, IO_L31, output3, X, 723, 1, Z),\" & --  PAD774\n\t\" 725 (BC_2, IO_L31, input, X),\" & --  PAD774\n\t\" 726 (BC_2, *, controlr, 1),\" &\n\t\" 727 (BC_2, IO_L32, output3, X, 726, 1, Z),\" & --  PAD773\n\t\" 728 (BC_2, IO_L32, input, X),\" & --  PAD773\n\t\" 729 (BC_2, *, controlr, 1),\" &\n\t\" 730 (BC_2, IO_M32, output3, X, 729, 1, Z),\" & --  PAD772\n\t\" 731 (BC_2, IO_M32, input, X),\" & --  PAD772\n\t\" 732 (BC_2, *, controlr, 1),\" &\n\t\" 733 (BC_2, IO_H31, output3, X, 732, 1, Z),\" & --  PAD771\n\t\" 734 (BC_2, IO_H31, input, X),\" & --  PAD771\n\t\" 735 (BC_2, *, controlr, 1),\" &\n\t\" 736 (BC_2, IO_J31, output3, X, 735, 1, Z),\" & --  PAD770\n\t\" 737 (BC_2, IO_J31, input, X),\" & --  PAD770\n\t\" 738 (BC_2, *, controlr, 1),\" &\n\t\" 739 (BC_2, IO_L30, output3, X, 738, 1, Z),\" & --  PAD769\n\t\" 740 (BC_2, IO_L30, input, X),\" & --  PAD769\n\t\" 741 (BC_2, *, controlr, 1),\" &\n\t\" 742 (BC_2, IO_L29, output3, X, 741, 1, Z),\" & --  PAD768\n\t\" 743 (BC_2, IO_L29, input, X),\" & --  PAD768\n\t\" 744 (BC_2, *, controlr, 1),\" &\n\t\" 745 (BC_2, IO_H30, output3, X, 744, 1, Z),\" & --  PAD767\n\t\" 746 (BC_2, IO_H30, input, X),\" & --  PAD767\n\t\" 747 (BC_2, *, controlr, 1),\" &\n\t\" 748 (BC_2, IO_J30, output3, X, 747, 1, Z),\" & --  PAD766\n\t\" 749 (BC_2, IO_J30, input, X),\" & --  PAD766\n\t\" 750 (BC_2, *, controlr, 1),\" &\n\t\" 751 (BC_2, IO_K30, output3, X, 750, 1, Z),\" & --  PAD765\n\t\" 752 (BC_2, IO_K30, input, X),\" & --  PAD765\n\t\" 753 (BC_2, *, controlr, 1),\" &\n\t\" 754 (BC_2, IO_K29, output3, X, 753, 1, Z),\" & --  PAD764\n\t\" 755 (BC_2, IO_K29, input, X),\" & --  PAD764\n\t\" 756 (BC_2, *, controlr, 1),\" &\n\t\" 757 (BC_2, IO_H35, output3, X, 756, 1, Z),\" & --  PAD763\n\t\" 758 (BC_2, IO_H35, input, X),\" & --  PAD763\n\t\" 759 (BC_2, *, controlr, 1),\" &\n\t\" 760 (BC_2, IO_H34, output3, X, 759, 1, Z),\" & --  PAD762\n\t\" 761 (BC_2, IO_H34, input, X),\" & --  PAD762\n\t\" 762 (BC_2, *, controlr, 1),\" &\n\t\" 763 (BC_2, IO_M34, output3, X, 762, 1, Z),\" & --  PAD761\n\t\" 764 (BC_2, IO_M34, input, X),\" & --  PAD761\n\t\" 765 (BC_2, *, controlr, 1),\" &\n\t\" 766 (BC_2, IO_M33, output3, X, 765, 1, Z),\" & --  PAD760\n\t\" 767 (BC_2, IO_M33, input, X),\" & --  PAD760\n\t\" 768 (BC_2, *, controlr, 1),\" &\n\t\" 769 (BC_2, IO_L35, output3, X, 768, 1, Z),\" & --  PAD759\n\t\" 770 (BC_2, IO_L35, input, X),\" & --  PAD759\n\t\" 771 (BC_2, *, controlr, 1),\" &\n\t\" 772 (BC_2, IO_L34, output3, X, 771, 1, Z),\" & --  PAD758\n\t\" 773 (BC_2, IO_L34, input, X),\" & --  PAD758\n\t\" 774 (BC_2, *, controlr, 1),\" &\n\t\" 775 (BC_2, IO_K34, output3, X, 774, 1, Z),\" & --  PAD757\n\t\" 776 (BC_2, IO_K34, input, X),\" & --  PAD757\n\t\" 777 (BC_2, *, controlr, 1),\" &\n\t\" 778 (BC_2, IO_K33, output3, X, 777, 1, Z),\" & --  PAD756\n\t\" 779 (BC_2, IO_K33, input, X),\" & --  PAD756\n\t\" 780 (BC_2, *, controlr, 1),\" &\n\t\" 781 (BC_2, IO_J33, output3, X, 780, 1, Z),\" & --  PAD755\n\t\" 782 (BC_2, IO_J33, input, X),\" & --  PAD755\n\t\" 783 (BC_2, *, controlr, 1),\" &\n\t\" 784 (BC_2, IO_J32, output3, X, 783, 1, Z),\" & --  PAD754\n\t\" 785 (BC_2, IO_J32, input, X),\" & --  PAD754\n\t\" 786 (BC_2, *, controlr, 1),\" &\n\t\" 787 (BC_2, IO_J35, output3, X, 786, 1, Z),\" & --  PAD753\n\t\" 788 (BC_2, IO_J35, input, X),\" & --  PAD753\n\t\" 789 (BC_2, *, controlr, 1),\" &\n\t\" 790 (BC_2, IO_K35, output3, X, 789, 1, Z),\" & --  PAD752\n\t\" 791 (BC_2, IO_K35, input, X),\" & --  PAD752\n\t\" 792 (BC_2, *, controlr, 1),\" &\n\t\" 793 (BC_2, IO_R29, output3, X, 792, 1, Z),\" & --  PAD751\n\t\" 794 (BC_2, IO_R29, input, X),\" & --  PAD751\n\t\" 795 (BC_2, *, controlr, 1),\" &\n\t\" 796 (BC_2, IO_G34, output3, X, 795, 1, Z),\" & --  PAD750\n\t\" 797 (BC_2, IO_G34, input, X),\" & --  PAD750\n\t\" 798 (BC_2, *, controlr, 1),\" &\n\t\" 799 (BC_2, IO_H36, output3, X, 798, 1, Z),\" & --  PAD749\n\t\" 800 (BC_2, IO_H36, input, X),\" & --  PAD749\n\t\" 801 (BC_2, *, controlr, 1),\" &\n\t\" 802 (BC_2, IO_J36, output3, X, 801, 1, Z),\" & --  PAD748\n\t\" 803 (BC_2, IO_J36, input, X),\" & --  PAD748\n\t\" 804 (BC_2, *, controlr, 1),\" &\n\t\" 805 (BC_2, IO_G38, output3, X, 804, 1, Z),\" & --  PAD747\n\t\" 806 (BC_2, IO_G38, input, X),\" & --  PAD747\n\t\" 807 (BC_2, *, controlr, 1),\" &\n\t\" 808 (BC_2, IO_H38, output3, X, 807, 1, Z),\" & --  PAD746\n\t\" 809 (BC_2, IO_H38, input, X),\" & --  PAD746\n\t\" 810 (BC_2, *, controlr, 1),\" &\n\t\" 811 (BC_2, IO_J38, output3, X, 810, 1, Z),\" & --  PAD745\n\t\" 812 (BC_2, IO_J38, input, X),\" & --  PAD745\n\t\" 813 (BC_2, *, controlr, 1),\" &\n\t\" 814 (BC_2, IO_J37, output3, X, 813, 1, Z),\" & --  PAD744\n\t\" 815 (BC_2, IO_J37, input, X),\" & --  PAD744\n\t\" 816 (BC_2, *, controlr, 1),\" &\n\t\" 817 (BC_2, IO_E39, output3, X, 816, 1, Z),\" & --  PAD743\n\t\" 818 (BC_2, IO_E39, input, X),\" & --  PAD743\n\t\" 819 (BC_2, *, controlr, 1),\" &\n\t\" 820 (BC_2, IO_F39, output3, X, 819, 1, Z),\" & --  PAD742\n\t\" 821 (BC_2, IO_F39, input, X),\" & --  PAD742\n\t\" 822 (BC_2, *, controlr, 1),\" &\n\t\" 823 (BC_2, IO_G37, output3, X, 822, 1, Z),\" & --  PAD741\n\t\" 824 (BC_2, IO_G37, input, X),\" & --  PAD741\n\t\" 825 (BC_2, *, controlr, 1),\" &\n\t\" 826 (BC_2, IO_G36, output3, X, 825, 1, Z),\" & --  PAD740\n\t\" 827 (BC_2, IO_G36, input, X),\" & --  PAD740\n\t\" 828 (BC_2, *, controlr, 1),\" &\n\t\" 829 (BC_2, IO_E38, output3, X, 828, 1, Z),\" & --  PAD739\n\t\" 830 (BC_2, IO_E38, input, X),\" & --  PAD739\n\t\" 831 (BC_2, *, controlr, 1),\" &\n\t\" 832 (BC_2, IO_E37, output3, X, 831, 1, Z),\" & --  PAD738\n\t\" 833 (BC_2, IO_E37, input, X),\" & --  PAD738\n\t\" 834 (BC_2, *, controlr, 1),\" &\n\t\" 835 (BC_2, IO_G33, output3, X, 834, 1, Z),\" & --  PAD737\n\t\" 836 (BC_2, IO_G33, input, X),\" & --  PAD737\n\t\" 837 (BC_2, *, controlr, 1),\" &\n\t\" 838 (BC_2, IO_H33, output3, X, 837, 1, Z),\" & --  PAD736\n\t\" 839 (BC_2, IO_H33, input, X),\" & --  PAD736\n\t\" 840 (BC_2, *, controlr, 1),\" &\n\t\" 841 (BC_2, IO_F35, output3, X, 840, 1, Z),\" & --  PAD735\n\t\" 842 (BC_2, IO_F35, input, X),\" & --  PAD735\n\t\" 843 (BC_2, *, controlr, 1),\" &\n\t\" 844 (BC_2, IO_F34, output3, X, 843, 1, Z),\" & --  PAD734\n\t\" 845 (BC_2, IO_F34, input, X),\" & --  PAD734\n\t\" 846 (BC_2, *, controlr, 1),\" &\n\t\" 847 (BC_2, IO_F37, output3, X, 846, 1, Z),\" & --  PAD733\n\t\" 848 (BC_2, IO_F37, input, X),\" & --  PAD733\n\t\" 849 (BC_2, *, controlr, 1),\" &\n\t\" 850 (BC_2, IO_F36, output3, X, 849, 1, Z),\" & --  PAD732\n\t\" 851 (BC_2, IO_F36, input, X),\" & --  PAD732\n\t\" 852 (BC_2, *, controlr, 1),\" &\n\t\" 853 (BC_2, IO_F32, output3, X, 852, 1, Z),\" & --  PAD731\n\t\" 854 (BC_2, IO_F32, input, X),\" & --  PAD731\n\t\" 855 (BC_2, *, controlr, 1),\" &\n\t\" 856 (BC_2, IO_G32, output3, X, 855, 1, Z),\" & --  PAD730\n\t\" 857 (BC_2, IO_G32, input, X),\" & --  PAD730\n\t\" 858 (BC_2, *, controlr, 1),\" &\n\t\" 859 (BC_2, IO_D38, output3, X, 858, 1, Z),\" & --  PAD729\n\t\" 860 (BC_2, IO_D38, input, X),\" & --  PAD729\n\t\" 861 (BC_2, *, controlr, 1),\" &\n\t\" 862 (BC_2, IO_D37, output3, X, 861, 1, Z),\" & --  PAD728\n\t\" 863 (BC_2, IO_D37, input, X),\" & --  PAD728\n\t\" 864 (BC_2, *, controlr, 1),\" &\n\t\" 865 (BC_2, IO_E35, output3, X, 864, 1, Z),\" & --  PAD727\n\t\" 866 (BC_2, IO_E35, input, X),\" & --  PAD727\n\t\" 867 (BC_2, *, controlr, 1),\" &\n\t\" 868 (BC_2, IO_E34, output3, X, 867, 1, Z),\" & --  PAD726\n\t\" 869 (BC_2, IO_E34, input, X),\" & --  PAD726\n\t\" 870 (BC_2, *, controlr, 1),\" &\n\t\" 871 (BC_2, IO_C36, output3, X, 870, 1, Z),\" & --  PAD725\n\t\" 872 (BC_2, IO_C36, input, X),\" & --  PAD725\n\t\" 873 (BC_2, *, controlr, 1),\" &\n\t\" 874 (BC_2, IO_C35, output3, X, 873, 1, Z),\" & --  PAD724\n\t\" 875 (BC_2, IO_C35, input, X),\" & --  PAD724\n\t\" 876 (BC_2, *, controlr, 1),\" &\n\t\" 877 (BC_2, IO_D36, output3, X, 876, 1, Z),\" & --  PAD723\n\t\" 878 (BC_2, IO_D36, input, X),\" & --  PAD723\n\t\" 879 (BC_2, *, controlr, 1),\" &\n\t\" 880 (BC_2, IO_D35, output3, X, 879, 1, Z),\" & --  PAD722\n\t\" 881 (BC_2, IO_D35, input, X),\" & --  PAD722\n\t\" 882 (BC_2, *, controlr, 1),\" &\n\t\" 883 (BC_2, IO_C34, output3, X, 882, 1, Z),\" & --  PAD721\n\t\" 884 (BC_2, IO_C34, input, X),\" & --  PAD721\n\t\" 885 (BC_2, *, controlr, 1),\" &\n\t\" 886 (BC_2, IO_C33, output3, X, 885, 1, Z),\" & --  PAD720\n\t\" 887 (BC_2, IO_C33, input, X),\" & --  PAD720\n\t\" 888 (BC_2, *, controlr, 1),\" &\n\t\" 889 (BC_2, IO_D33, output3, X, 888, 1, Z),\" & --  PAD719\n\t\" 890 (BC_2, IO_D33, input, X),\" & --  PAD719\n\t\" 891 (BC_2, *, controlr, 1),\" &\n\t\" 892 (BC_2, IO_E33, output3, X, 891, 1, Z),\" & --  PAD718\n\t\" 893 (BC_2, IO_E33, input, X),\" & --  PAD718\n\t\" 894 (BC_2, *, controlr, 1),\" &\n\t\" 895 (BC_2, IO_B33, output3, X, 894, 1, Z),\" & --  PAD717\n\t\" 896 (BC_2, IO_B33, input, X),\" & --  PAD717\n\t\" 897 (BC_2, *, controlr, 1),\" &\n\t\" 898 (BC_2, IO_B32, output3, X, 897, 1, Z),\" & --  PAD716\n\t\" 899 (BC_2, IO_B32, input, X),\" & --  PAD716\n\t\" 900 (BC_2, *, controlr, 1),\" &\n\t\" 901 (BC_2, IO_D32, output3, X, 900, 1, Z),\" & --  PAD715\n\t\" 902 (BC_2, IO_D32, input, X),\" & --  PAD715\n\t\" 903 (BC_2, *, controlr, 1),\" &\n\t\" 904 (BC_2, IO_E32, output3, X, 903, 1, Z),\" & --  PAD714\n\t\" 905 (BC_2, IO_E32, input, X),\" & --  PAD714\n\t\" 906 (BC_2, *, controlr, 1),\" &\n\t\" 907 (BC_2, IO_B38, output3, X, 906, 1, Z),\" & --  PAD713\n\t\" 908 (BC_2, IO_B38, input, X),\" & --  PAD713\n\t\" 909 (BC_2, *, controlr, 1),\" &\n\t\" 910 (BC_2, IO_B37, output3, X, 909, 1, Z),\" & --  PAD712\n\t\" 911 (BC_2, IO_B37, input, X),\" & --  PAD712\n\t\" 912 (BC_2, *, controlr, 1),\" &\n\t\" 913 (BC_2, IO_C39, output3, X, 912, 1, Z),\" & --  PAD711\n\t\" 914 (BC_2, IO_C39, input, X),\" & --  PAD711\n\t\" 915 (BC_2, *, controlr, 1),\" &\n\t\" 916 (BC_2, IO_C38, output3, X, 915, 1, Z),\" & --  PAD710\n\t\" 917 (BC_2, IO_C38, input, X),\" & --  PAD710\n\t\" 918 (BC_2, *, controlr, 1),\" &\n\t\" 919 (BC_2, IO_A36, output3, X, 918, 1, Z),\" & --  PAD709\n\t\" 920 (BC_2, IO_A36, input, X),\" & --  PAD709\n\t\" 921 (BC_2, *, controlr, 1),\" &\n\t\" 922 (BC_2, IO_A35, output3, X, 921, 1, Z),\" & --  PAD708\n\t\" 923 (BC_2, IO_A35, input, X),\" & --  PAD708\n\t\" 924 (BC_2, *, controlr, 1),\" &\n\t\" 925 (BC_2, IO_A39, output3, X, 924, 1, Z),\" & --  PAD707\n\t\" 926 (BC_2, IO_A39, input, X),\" & --  PAD707\n\t\" 927 (BC_2, *, controlr, 1),\" &\n\t\" 928 (BC_2, IO_B39, output3, X, 927, 1, Z),\" & --  PAD706\n\t\" 929 (BC_2, IO_B39, input, X),\" & --  PAD706\n\t\" 930 (BC_2, *, controlr, 1),\" &\n\t\" 931 (BC_2, IO_A34, output3, X, 930, 1, Z),\" & --  PAD705\n\t\" 932 (BC_2, IO_A34, input, X),\" & --  PAD705\n\t\" 933 (BC_2, *, controlr, 1),\" &\n\t\" 934 (BC_2, IO_B34, output3, X, 933, 1, Z),\" & --  PAD704\n\t\" 935 (BC_2, IO_B34, input, X),\" & --  PAD704\n\t\" 936 (BC_2, *, controlr, 1),\" &\n\t\" 937 (BC_2, IO_A37, output3, X, 936, 1, Z),\" & --  PAD703\n\t\" 938 (BC_2, IO_A37, input, X),\" & --  PAD703\n\t\" 939 (BC_2, *, controlr, 1),\" &\n\t\" 940 (BC_2, IO_B36, output3, X, 939, 1, Z),\" & --  PAD702\n\t\" 941 (BC_2, IO_B36, input, X),\" & --  PAD702\n\t\" 942 (BC_2, *, controlr, 1),\" &\n\t\" 943 (BC_2, IO_G31, output3, X, 942, 1, Z),\" & --  PAD701\n\t\" 944 (BC_2, IO_G31, input, X),\" & --  PAD701\n\t\" 945 (BC_2, *, controlr, 1),\" &\n\t\" 946 (BC_2, IO_M26, output3, X, 945, 1, Z),\" & --  PAD700\n\t\" 947 (BC_2, IO_M26, input, X),\" & --  PAD700\n\t\" 948 (BC_2, *, controlr, 1),\" &\n\t\" 949 (BC_2, IO_L27, output3, X, 948, 1, Z),\" & --  PAD699\n\t\" 950 (BC_2, IO_L27, input, X),\" & --  PAD699\n\t\" 951 (BC_2, *, controlr, 1),\" &\n\t\" 952 (BC_2, IO_M27, output3, X, 951, 1, Z),\" & --  PAD698\n\t\" 953 (BC_2, IO_M27, input, X),\" & --  PAD698\n\t\" 954 (BC_2, *, controlr, 1),\" &\n\t\" 955 (BC_2, IO_N24, output3, X, 954, 1, Z),\" & --  PAD697\n\t\" 956 (BC_2, IO_N24, input, X),\" & --  PAD697\n\t\" 957 (BC_2, *, controlr, 1),\" &\n\t\" 958 (BC_2, IO_N23, output3, X, 957, 1, Z),\" & --  PAD696\n\t\" 959 (BC_2, IO_N23, input, X),\" & --  PAD696\n\t\" 960 (BC_2, *, controlr, 1),\" &\n\t\" 961 (BC_2, IO_N26, output3, X, 960, 1, Z),\" & --  PAD695\n\t\" 962 (BC_2, IO_N26, input, X),\" & --  PAD695\n\t\" 963 (BC_2, *, controlr, 1),\" &\n\t\" 964 (BC_2, IO_N25, output3, X, 963, 1, Z),\" & --  PAD694\n\t\" 965 (BC_2, IO_N25, input, X),\" & --  PAD694\n\t\" 966 (BC_2, *, controlr, 1),\" &\n\t\" 967 (BC_2, IO_P23, output3, X, 966, 1, Z),\" & --  PAD693\n\t\" 968 (BC_2, IO_P23, input, X),\" & --  PAD693\n\t\" 969 (BC_2, *, controlr, 1),\" &\n\t\" 970 (BC_2, IO_P22, output3, X, 969, 1, Z),\" & --  PAD692\n\t\" 971 (BC_2, IO_P22, input, X),\" & --  PAD692\n\t\" 972 (BC_2, *, controlr, 1),\" &\n\t\" 973 (BC_2, IO_P26, output3, X, 972, 1, Z),\" & --  PAD691\n\t\" 974 (BC_2, IO_P26, input, X),\" & --  PAD691\n\t\" 975 (BC_2, *, controlr, 1),\" &\n\t\" 976 (BC_2, IO_P25, output3, X, 975, 1, Z),\" & --  PAD690\n\t\" 977 (BC_2, IO_P25, input, X),\" & --  PAD690\n\t\" 978 (BC_2, *, controlr, 1),\" &\n\t\" 979 (BC_2, IO_N21, output3, X, 978, 1, Z),\" & --  PAD689\n\t\" 980 (BC_2, IO_N21, input, X),\" & --  PAD689\n\t\" 981 (BC_2, *, controlr, 1),\" &\n\t\" 982 (BC_2, IO_P21, output3, X, 981, 1, Z),\" & --  PAD688\n\t\" 983 (BC_2, IO_P21, input, X),\" & --  PAD688\n\t\" 984 (BC_2, *, controlr, 1),\" &\n\t\" 985 (BC_2, IO_L21, output3, X, 984, 1, Z),\" & --  PAD687\n\t\" 986 (BC_2, IO_L21, input, X),\" & --  PAD687\n\t\" 987 (BC_2, *, controlr, 1),\" &\n\t\" 988 (BC_2, IO_M21, output3, X, 987, 1, Z),\" & --  PAD686\n\t\" 989 (BC_2, IO_M21, input, X),\" & --  PAD686\n\t\" 990 (BC_2, *, controlr, 1),\" &\n\t\" 991 (BC_2, IO_J22, output3, X, 990, 1, Z),\" & --  PAD685\n\t\" 992 (BC_2, IO_J22, input, X),\" & --  PAD685\n\t\" 993 (BC_2, *, controlr, 1),\" &\n\t\" 994 (BC_2, IO_K22, output3, X, 993, 1, Z),\" & --  PAD684\n\t\" 995 (BC_2, IO_K22, input, X),\" & --  PAD684\n\t\" 996 (BC_2, *, controlr, 1),\" &\n\t\" 997 (BC_2, IO_L26, output3, X, 996, 1, Z),\" & --  PAD683\n\t\" 998 (BC_2, IO_L26, input, X),\" & --  PAD683\n\t\" 999 (BC_2, *, controlr, 1),\" &\n\t\"1000 (BC_2, IO_L25, output3, X, 999, 1, Z),\" & --  PAD682\n\t\"1001 (BC_2, IO_L25, input, X),\" & --  PAD682\n\t\"1002 (BC_2, *, controlr, 1),\" &\n\t\"1003 (BC_2, IO_L22, output3, X, 1002, 1, Z),\" & --  PAD681\n\t\"1004 (BC_2, IO_L22, input, X),\" & --  PAD681\n\t\"1005 (BC_2, *, controlr, 1),\" &\n\t\"1006 (BC_2, IO_M22, output3, X, 1005, 1, Z),\" & --  PAD680\n\t\"1007 (BC_2, IO_M22, input, X),\" & --  PAD680\n\t\"1008 (BC_2, *, controlr, 1),\" &\n\t\"1009 (BC_2, IO_J23, output3, X, 1008, 1, Z),\" & --  PAD679\n\t\"1010 (BC_2, IO_J23, input, X),\" & --  PAD679\n\t\"1011 (BC_2, *, controlr, 1),\" &\n\t\"1012 (BC_2, IO_K23, output3, X, 1011, 1, Z),\" & --  PAD678\n\t\"1013 (BC_2, IO_K23, input, X),\" & --  PAD678\n\t\"1014 (BC_2, *, controlr, 1),\" &\n\t\"1015 (BC_2, IO_L24, output3, X, 1014, 1, Z),\" & --  PAD677\n\t\"1016 (BC_2, IO_L24, input, X),\" & --  PAD677\n\t\"1017 (BC_2, *, controlr, 1),\" &\n\t\"1018 (BC_2, IO_M24, output3, X, 1017, 1, Z),\" & --  PAD676\n\t\"1019 (BC_2, IO_M24, input, X),\" & --  PAD676\n\t\"1020 (BC_2, *, controlr, 1),\" &\n\t\"1021 (BC_2, IO_J26, output3, X, 1020, 1, Z),\" & --  PAD675\n\t\"1022 (BC_2, IO_J26, input, X),\" & --  PAD675\n\t\"1023 (BC_2, *, controlr, 1),\" &\n\t\"1024 (BC_2, IO_J25, output3, X, 1023, 1, Z),\" & --  PAD674\n\t\"1025 (BC_2, IO_J25, input, X),\" & --  PAD674\n\t\"1026 (BC_2, *, controlr, 1),\" &\n\t\"1027 (BC_2, IO_K25, output3, X, 1026, 1, Z),\" & --  PAD673\n\t\"1028 (BC_2, IO_K25, input, X),\" & --  PAD673\n\t\"1029 (BC_2, *, controlr, 1),\" &\n\t\"1030 (BC_2, IO_K24, output3, X, 1029, 1, Z),\" & --  PAD672\n\t\"1031 (BC_2, IO_K24, input, X),\" & --  PAD672\n\t\"1032 (BC_2, *, controlr, 1),\" &\n\t\"1033 (BC_2, IO_J27, output3, X, 1032, 1, Z),\" & --  PAD671\n\t\"1034 (BC_2, IO_J27, input, X),\" & --  PAD671\n\t\"1035 (BC_2, *, controlr, 1),\" &\n\t\"1036 (BC_2, IO_K27, output3, X, 1035, 1, Z),\" & --  PAD670\n\t\"1037 (BC_2, IO_K27, input, X),\" & --  PAD670\n\t\"1038 (BC_2, *, controlr, 1),\" &\n\t\"1039 (BC_2, IO_H29, output3, X, 1038, 1, Z),\" & --  PAD669\n\t\"1040 (BC_2, IO_H29, input, X),\" & --  PAD669\n\t\"1041 (BC_2, *, controlr, 1),\" &\n\t\"1042 (BC_2, IO_H28, output3, X, 1041, 1, Z),\" & --  PAD668\n\t\"1043 (BC_2, IO_H28, input, X),\" & --  PAD668\n\t\"1044 (BC_2, *, controlr, 1),\" &\n\t\"1045 (BC_2, IO_J28, output3, X, 1044, 1, Z),\" & --  PAD667\n\t\"1046 (BC_2, IO_J28, input, X),\" & --  PAD667\n\t\"1047 (BC_2, *, controlr, 1),\" &\n\t\"1048 (BC_2, IO_K28, output3, X, 1047, 1, Z),\" & --  PAD666\n\t\"1049 (BC_2, IO_K28, input, X),\" & --  PAD666\n\t\"1050 (BC_2, *, controlr, 1),\" &\n\t\"1051 (BC_2, IO_G29, output3, X, 1050, 1, Z),\" & --  PAD665\n\t\"1052 (BC_2, IO_G29, input, X),\" & --  PAD665\n\t\"1053 (BC_2, *, controlr, 1),\" &\n\t\"1054 (BC_2, IO_G28, output3, X, 1053, 1, Z),\" & --  PAD664\n\t\"1055 (BC_2, IO_G28, input, X),\" & --  PAD664\n\t\"1056 (BC_2, *, controlr, 1),\" &\n\t\"1057 (BC_2, IO_G23, output3, X, 1056, 1, Z),\" & --  PAD663\n\t\"1058 (BC_2, IO_G23, input, X),\" & --  PAD663\n\t\"1059 (BC_2, *, controlr, 1),\" &\n\t\"1060 (BC_2, IO_H23, output3, X, 1059, 1, Z),\" & --  PAD662\n\t\"1061 (BC_2, IO_H23, input, X),\" & --  PAD662\n\t\"1062 (BC_2, *, controlr, 1),\" &\n\t\"1063 (BC_2, IO_G27, output3, X, 1062, 1, Z),\" & --  PAD661\n\t\"1064 (BC_2, IO_G27, input, X),\" & --  PAD661\n\t\"1065 (BC_2, *, controlr, 1),\" &\n\t\"1066 (BC_2, IO_G26, output3, X, 1065, 1, Z),\" & --  PAD660\n\t\"1067 (BC_2, IO_G26, input, X),\" & --  PAD660\n\t\"1068 (BC_2, *, controlr, 1),\" &\n\t\"1069 (BC_2, IO_G22, output3, X, 1068, 1, Z),\" & --  PAD659\n\t\"1070 (BC_2, IO_G22, input, X),\" & --  PAD659\n\t\"1071 (BC_2, *, controlr, 1),\" &\n\t\"1072 (BC_2, IO_G21, output3, X, 1071, 1, Z),\" & --  PAD658\n\t\"1073 (BC_2, IO_G21, input, X),\" & --  PAD658\n\t\"1074 (BC_2, *, controlr, 1),\" &\n\t\"1075 (BC_2, IO_H26, output3, X, 1074, 1, Z),\" & --  PAD657\n\t\"1076 (BC_2, IO_H26, input, X),\" & --  PAD657\n\t\"1077 (BC_2, *, controlr, 1),\" &\n\t\"1078 (BC_2, IO_H25, output3, X, 1077, 1, Z),\" & --  PAD656\n\t\"1079 (BC_2, IO_H25, input, X),\" & --  PAD656\n\t\"1080 (BC_2, *, controlr, 1),\" &\n\t\"1081 (BC_2, IO_H21, output3, X, 1080, 1, Z),\" & --  PAD655\n\t\"1082 (BC_2, IO_H21, input, X),\" & --  PAD655\n\t\"1083 (BC_2, *, controlr, 1),\" &\n\t\"1084 (BC_2, IO_J21, output3, X, 1083, 1, Z),\" & --  PAD654\n\t\"1085 (BC_2, IO_J21, input, X),\" & --  PAD654\n\t\"1086 (BC_2, *, controlr, 1),\" &\n\t\"1087 (BC_2, IO_G24, output3, X, 1086, 1, Z),\" & --  PAD653\n\t\"1088 (BC_2, IO_G24, input, X),\" & --  PAD653\n\t\"1089 (BC_2, *, controlr, 1),\" &\n\t\"1090 (BC_2, IO_H24, output3, X, 1089, 1, Z),\" & --  PAD652\n\t\"1091 (BC_2, IO_H24, input, X),\" & --  PAD652\n\t\"1092 (BC_2, *, controlr, 1),\" &\n\t\"1093 (BC_2, IO_M23, output3, X, 1092, 1, Z),\" & --  PAD651\n\t\"1094 (BC_2, IO_M23, input, X),\" & --  PAD651\n\t\"1095 (BC_2, *, controlr, 1),\" &\n\t\"1096 (BC_2, IO_F24, output3, X, 1095, 1, Z),\" & --  PAD650\n\t\"1097 (BC_2, IO_F24, input, X),\" & --  PAD650\n\t\"1098 (BC_2, *, controlr, 1),\" &\n\t\"1099 (BC_2, IO_F31, output3, X, 1098, 1, Z),\" & --  PAD649\n\t\"1100 (BC_2, IO_F31, input, X),\" & --  PAD649\n\t\"1101 (BC_2, *, controlr, 1),\" &\n\t\"1102 (BC_2, IO_F30, output3, X, 1101, 1, Z),\" & --  PAD648\n\t\"1103 (BC_2, IO_F30, input, X),\" & --  PAD648\n\t\"1104 (BC_2, *, controlr, 1),\" &\n\t\"1105 (BC_2, IO_F27, output3, X, 1104, 1, Z),\" & --  PAD647\n\t\"1106 (BC_2, IO_F27, input, X),\" & --  PAD647\n\t\"1107 (BC_2, *, controlr, 1),\" &\n\t\"1108 (BC_2, IO_F26, output3, X, 1107, 1, Z),\" & --  PAD646\n\t\"1109 (BC_2, IO_F26, input, X),\" & --  PAD646\n\t\"1110 (BC_2, *, controlr, 1),\" &\n\t\"1111 (BC_2, IO_E29, output3, X, 1110, 1, Z),\" & --  PAD645\n\t\"1112 (BC_2, IO_E29, input, X),\" & --  PAD645\n\t\"1113 (BC_2, *, controlr, 1),\" &\n\t\"1114 (BC_2, IO_F29, output3, X, 1113, 1, Z),\" & --  PAD644\n\t\"1115 (BC_2, IO_F29, input, X),\" & --  PAD644\n\t\"1116 (BC_2, *, controlr, 1),\" &\n\t\"1117 (BC_2, IO_E28, output3, X, 1116, 1, Z),\" & --  PAD643\n\t\"1118 (BC_2, IO_E28, input, X),\" & --  PAD643\n\t\"1119 (BC_2, *, controlr, 1),\" &\n\t\"1120 (BC_2, IO_E27, output3, X, 1119, 1, Z),\" & --  PAD642\n\t\"1121 (BC_2, IO_E27, input, X),\" & --  PAD642\n\t\"1122 (BC_2, *, controlr, 1),\" &\n\t\"1123 (BC_2, IO_C30, output3, X, 1122, 1, Z),\" & --  PAD641\n\t\"1124 (BC_2, IO_C30, input, X),\" & --  PAD641\n\t\"1125 (BC_2, *, controlr, 1),\" &\n\t\"1126 (BC_2, IO_D30, output3, X, 1125, 1, Z),\" & --  PAD640\n\t\"1127 (BC_2, IO_D30, input, X),\" & --  PAD640\n\t\"1128 (BC_2, *, controlr, 1),\" &\n\t\"1129 (BC_2, IO_D31, output3, X, 1128, 1, Z),\" & --  PAD639\n\t\"1130 (BC_2, IO_D31, input, X),\" & --  PAD639\n\t\"1131 (BC_2, *, controlr, 1),\" &\n\t\"1132 (BC_2, IO_E30, output3, X, 1131, 1, Z),\" & --  PAD638\n\t\"1133 (BC_2, IO_E30, input, X),\" & --  PAD638\n\t\"1134 (BC_2, *, controlr, 1),\" &\n\t\"1135 (BC_2, IO_B31, output3, X, 1134, 1, Z),\" & --  PAD637\n\t\"1136 (BC_2, IO_B31, input, X),\" & --  PAD637\n\t\"1137 (BC_2, *, controlr, 1),\" &\n\t\"1138 (BC_2, IO_C31, output3, X, 1137, 1, Z),\" & --  PAD636\n\t\"1139 (BC_2, IO_C31, input, X),\" & --  PAD636\n\t\"1140 (BC_2, *, controlr, 1),\" &\n\t\"1141 (BC_2, IO_A30, output3, X, 1140, 1, Z),\" & --  PAD635\n\t\"1142 (BC_2, IO_A30, input, X),\" & --  PAD635\n\t\"1143 (BC_2, *, controlr, 1),\" &\n\t\"1144 (BC_2, IO_A29, output3, X, 1143, 1, Z),\" & --  PAD634\n\t\"1145 (BC_2, IO_A29, input, X),\" & --  PAD634\n\t\"1146 (BC_2, *, controlr, 1),\" &\n\t\"1147 (BC_2, IO_A32, output3, X, 1146, 1, Z),\" & --  PAD633\n\t\"1148 (BC_2, IO_A32, input, X),\" & --  PAD633\n\t\"1149 (BC_2, *, controlr, 1),\" &\n\t\"1150 (BC_2, IO_A31, output3, X, 1149, 1, Z),\" & --  PAD632\n\t\"1151 (BC_2, IO_A31, input, X),\" & --  PAD632\n\t\"1152 (BC_2, *, controlr, 1),\" &\n\t\"1153 (BC_2, IO_B29, output3, X, 1152, 1, Z),\" & --  PAD631\n\t\"1154 (BC_2, IO_B29, input, X),\" & --  PAD631\n\t\"1155 (BC_2, *, controlr, 1),\" &\n\t\"1156 (BC_2, IO_B28, output3, X, 1155, 1, Z),\" & --  PAD630\n\t\"1157 (BC_2, IO_B28, input, X),\" & --  PAD630\n\t\"1158 (BC_2, *, controlr, 1),\" &\n\t\"1159 (BC_2, IO_C29, output3, X, 1158, 1, Z),\" & --  PAD629\n\t\"1160 (BC_2, IO_C29, input, X),\" & --  PAD629\n\t\"1161 (BC_2, *, controlr, 1),\" &\n\t\"1162 (BC_2, IO_C28, output3, X, 1161, 1, Z),\" & --  PAD628\n\t\"1163 (BC_2, IO_C28, input, X),\" & --  PAD628\n\t\"1164 (BC_2, *, controlr, 1),\" &\n\t\"1165 (BC_2, IO_D28, output3, X, 1164, 1, Z),\" & --  PAD627\n\t\"1166 (BC_2, IO_D28, input, X),\" & --  PAD627\n\t\"1167 (BC_2, *, controlr, 1),\" &\n\t\"1168 (BC_2, IO_D27, output3, X, 1167, 1, Z),\" & --  PAD626\n\t\"1169 (BC_2, IO_D27, input, X),\" & --  PAD626\n\t\"1170 (BC_2, *, controlr, 1),\" &\n\t\"1171 (BC_2, IO_C26, output3, X, 1170, 1, Z),\" & --  PAD625\n\t\"1172 (BC_2, IO_C26, input, X),\" & --  PAD625\n\t\"1173 (BC_2, *, controlr, 1),\" &\n\t\"1174 (BC_2, IO_C25, output3, X, 1173, 1, Z),\" & --  PAD624\n\t\"1175 (BC_2, IO_C25, input, X),\" & --  PAD624\n\t\"1176 (BC_2, *, controlr, 1),\" &\n\t\"1177 (BC_2, IO_D26, output3, X, 1176, 1, Z),\" & --  PAD623\n\t\"1178 (BC_2, IO_D26, input, X),\" & --  PAD623\n\t\"1179 (BC_2, *, controlr, 1),\" &\n\t\"1180 (BC_2, IO_D25, output3, X, 1179, 1, Z),\" & --  PAD622\n\t\"1181 (BC_2, IO_D25, input, X),\" & --  PAD622\n\t\"1182 (BC_2, *, controlr, 1),\" &\n\t\"1183 (BC_2, IO_D23, output3, X, 1182, 1, Z),\" & --  PAD621\n\t\"1184 (BC_2, IO_D23, input, X),\" & --  PAD621\n\t\"1185 (BC_2, *, controlr, 1),\" &\n\t\"1186 (BC_2, IO_D22, output3, X, 1185, 1, Z),\" & --  PAD620\n\t\"1187 (BC_2, IO_D22, input, X),\" & --  PAD620\n\t\"1188 (BC_2, *, controlr, 1),\" &\n\t\"1189 (BC_2, IO_E25, output3, X, 1188, 1, Z),\" & --  PAD619\n\t\"1190 (BC_2, IO_E25, input, X),\" & --  PAD619\n\t\"1191 (BC_2, *, controlr, 1),\" &\n\t\"1192 (BC_2, IO_F25, output3, X, 1191, 1, Z),\" & --  PAD618\n\t\"1193 (BC_2, IO_F25, input, X),\" & --  PAD618\n\t\"1194 (BC_2, *, controlr, 1),\" &\n\t\"1195 (BC_2, IO_E22, output3, X, 1194, 1, Z),\" & --  PAD617\n\t\"1196 (BC_2, IO_E22, input, X),\" & --  PAD617\n\t\"1197 (BC_2, *, controlr, 1),\" &\n\t\"1198 (BC_2, IO_F22, output3, X, 1197, 1, Z),\" & --  PAD616\n\t\"1199 (BC_2, IO_F22, input, X),\" & --  PAD616\n\t\"1200 (BC_2, *, controlr, 1),\" &\n\t\"1201 (BC_2, IO_E24, output3, X, 1200, 1, Z),\" & --  PAD615\n\t\"1202 (BC_2, IO_E24, input, X),\" & --  PAD615\n\t\"1203 (BC_2, *, controlr, 1),\" &\n\t\"1204 (BC_2, IO_E23, output3, X, 1203, 1, Z),\" & --  PAD614\n\t\"1205 (BC_2, IO_E23, input, X),\" & --  PAD614\n\t\"1206 (BC_2, *, controlr, 1),\" &\n\t\"1207 (BC_2, IO_B24, output3, X, 1206, 1, Z),\" & --  PAD613\n\t\"1208 (BC_2, IO_B24, input, X),\" & --  PAD613\n\t\"1209 (BC_2, *, controlr, 1),\" &\n\t\"1210 (BC_2, IO_C24, output3, X, 1209, 1, Z),\" & --  PAD612\n\t\"1211 (BC_2, IO_C24, input, X),\" & --  PAD612\n\t\"1212 (BC_2, *, controlr, 1),\" &\n\t\"1213 (BC_2, IO_B27, output3, X, 1212, 1, Z),\" & --  PAD611\n\t\"1214 (BC_2, IO_B27, input, X),\" & --  PAD611\n\t\"1215 (BC_2, *, controlr, 1),\" &\n\t\"1216 (BC_2, IO_B26, output3, X, 1215, 1, Z),\" & --  PAD610\n\t\"1217 (BC_2, IO_B26, input, X),\" & --  PAD610\n\t\"1218 (BC_2, *, controlr, 1),\" &\n\t\"1219 (BC_2, IO_B23, output3, X, 1218, 1, Z),\" & --  PAD609\n\t\"1220 (BC_2, IO_B23, input, X),\" & --  PAD609\n\t\"1221 (BC_2, *, controlr, 1),\" &\n\t\"1222 (BC_2, IO_C23, output3, X, 1221, 1, Z),\" & --  PAD608\n\t\"1223 (BC_2, IO_C23, input, X),\" & --  PAD608\n\t\"1224 (BC_2, *, controlr, 1),\" &\n\t\"1225 (BC_2, IO_A27, output3, X, 1224, 1, Z),\" & --  PAD607\n\t\"1226 (BC_2, IO_A27, input, X),\" & --  PAD607\n\t\"1227 (BC_2, *, controlr, 1),\" &\n\t\"1228 (BC_2, IO_A26, output3, X, 1227, 1, Z),\" & --  PAD606\n\t\"1229 (BC_2, IO_A26, input, X),\" & --  PAD606\n\t\"1230 (BC_2, *, controlr, 1),\" &\n\t\"1231 (BC_2, IO_A22, output3, X, 1230, 1, Z),\" & --  PAD605\n\t\"1232 (BC_2, IO_A22, input, X),\" & --  PAD605\n\t\"1233 (BC_2, *, controlr, 1),\" &\n\t\"1234 (BC_2, IO_B22, output3, X, 1233, 1, Z),\" & --  PAD604\n\t\"1235 (BC_2, IO_B22, input, X),\" & --  PAD604\n\t\"1236 (BC_2, *, controlr, 1),\" &\n\t\"1237 (BC_2, IO_A25, output3, X, 1236, 1, Z),\" & --  PAD603\n\t\"1238 (BC_2, IO_A25, input, X),\" & --  PAD603\n\t\"1239 (BC_2, *, controlr, 1),\" &\n\t\"1240 (BC_2, IO_A24, output3, X, 1239, 1, Z),\" & --  PAD602\n\t\"1241 (BC_2, IO_A24, input, X),\" & --  PAD602\n\t\"1242 (BC_2, *, controlr, 1),\" &\n\t\"1243 (BC_2, IO_F21, output3, X, 1242, 1, Z),\" & --  PAD601\n\t\"1244 (BC_2, IO_F21, input, X),\" & --  PAD601\n\t\"1245 (BC_2, *, controlr, 1),\" &\n\t\"1246 (BC_2, IO_K20, output3, X, 1245, 1, Z),\" & --  PAD600\n\t\"1247 (BC_2, IO_K20, input, X),\" & --  PAD600\n\t\"1248 (BC_2, *, controlr, 1),\" &\n\t\"1249 (BC_2, IO_L19, output3, X, 1248, 1, Z),\" & --  PAD599\n\t\"1250 (BC_2, IO_L19, input, X),\" & --  PAD599\n\t\"1251 (BC_2, *, controlr, 1),\" &\n\t\"1252 (BC_2, IO_L20, output3, X, 1251, 1, Z),\" & --  PAD598\n\t\"1253 (BC_2, IO_L20, input, X),\" & --  PAD598\n\t\"1254 (BC_2, *, controlr, 1),\" &\n\t\"1255 (BC_2, IO_N20, output3, X, 1254, 1, Z),\" & --  PAD597\n\t\"1256 (BC_2, IO_N20, input, X),\" & --  PAD597\n\t\"1257 (BC_2, *, controlr, 1),\" &\n\t\"1258 (BC_2, IO_P20, output3, X, 1257, 1, Z),\" & --  PAD596\n\t\"1259 (BC_2, IO_P20, input, X),\" & --  PAD596\n\t\"1260 (BC_2, *, controlr, 1),\" &\n\t\"1261 (BC_2, IO_M18, output3, X, 1260, 1, Z),\" & --  PAD595\n\t\"1262 (BC_2, IO_M18, input, X),\" & --  PAD595\n\t\"1263 (BC_2, *, controlr, 1),\" &\n\t\"1264 (BC_2, IO_M19, output3, X, 1263, 1, Z),\" & --  PAD594\n\t\"1265 (BC_2, IO_M19, input, X),\" & --  PAD594\n\t\"1266 (BC_2, *, controlr, 1),\" &\n\t\"1267 (BC_2, IO_N18, output3, X, 1266, 1, Z),\" & --  PAD593\n\t\"1268 (BC_2, IO_N18, input, X),\" & --  PAD593\n\t\"1269 (BC_2, *, controlr, 1),\" &\n\t\"1270 (BC_2, IO_N19, output3, X, 1269, 1, Z),\" & --  PAD592\n\t\"1271 (BC_2, IO_N19, input, X),\" & --  PAD592\n\t\"1272 (BC_2, *, controlr, 1),\" &\n\t\"1273 (BC_2, IO_L17, output3, X, 1272, 1, Z),\" & --  PAD591\n\t\"1274 (BC_2, IO_L17, input, X),\" & --  PAD591\n\t\"1275 (BC_2, *, controlr, 1),\" &\n\t\"1276 (BC_2, IO_M17, output3, X, 1275, 1, Z),\" & --  PAD590\n\t\"1277 (BC_2, IO_M17, input, X),\" & --  PAD590\n\t\"1278 (BC_2, *, controlr, 1),\" &\n\t\"1279 (BC_2, IO_P17, output3, X, 1278, 1, Z),\" & --  PAD589\n\t\"1280 (BC_2, IO_P17, input, X),\" & --  PAD589\n\t\"1281 (BC_2, *, controlr, 1),\" &\n\t\"1282 (BC_2, IO_P18, output3, X, 1281, 1, Z),\" & --  PAD588\n\t\"1283 (BC_2, IO_P18, input, X),\" & --  PAD588\n\t\"1284 (BC_2, *, controlr, 1),\" &\n\t\"1285 (BC_2, IO_G17, output3, X, 1284, 1, Z),\" & --  PAD587\n\t\"1286 (BC_2, IO_G17, input, X),\" & --  PAD587\n\t\"1287 (BC_2, *, controlr, 1),\" &\n\t\"1288 (BC_2, IO_H18, output3, X, 1287, 1, Z),\" & --  PAD586\n\t\"1289 (BC_2, IO_H18, input, X),\" & --  PAD586\n\t\"1290 (BC_2, *, controlr, 1),\" &\n\t\"1291 (BC_2, IO_H20, output3, X, 1290, 1, Z),\" & --  PAD585\n\t\"1292 (BC_2, IO_H20, input, X),\" & --  PAD585\n\t\"1293 (BC_2, *, controlr, 1),\" &\n\t\"1294 (BC_2, IO_J20, output3, X, 1293, 1, Z),\" & --  PAD584\n\t\"1295 (BC_2, IO_J20, input, X),\" & --  PAD584\n\t\"1296 (BC_2, *, controlr, 1),\" &\n\t\"1297 (BC_2, IO_J17, output3, X, 1296, 1, Z),\" & --  PAD583\n\t\"1298 (BC_2, IO_J17, input, X),\" & --  PAD583\n\t\"1299 (BC_2, *, controlr, 1),\" &\n\t\"1300 (BC_2, IO_K17, output3, X, 1299, 1, Z),\" & --  PAD582\n\t\"1301 (BC_2, IO_K17, input, X),\" & --  PAD582\n\t\"1302 (BC_2, *, controlr, 1),\" &\n\t\"1303 (BC_2, IO_E20, output3, X, 1302, 1, Z),\" & --  PAD581\n\t\"1304 (BC_2, IO_E20, input, X),\" & --  PAD581\n\t\"1305 (BC_2, *, controlr, 1),\" &\n\t\"1306 (BC_2, IO_F20, output3, X, 1305, 1, Z),\" & --  PAD580\n\t\"1307 (BC_2, IO_F20, input, X),\" & --  PAD580\n\t\"1308 (BC_2, *, controlr, 1),\" &\n\t\"1309 (BC_2, IO_J18, output3, X, 1308, 1, Z),\" & --  PAD579\n\t\"1310 (BC_2, IO_J18, input, X),\" & --  PAD579\n\t\"1311 (BC_2, *, controlr, 1),\" &\n\t\"1312 (BC_2, IO_K19, output3, X, 1311, 1, Z),\" & --  PAD578\n\t\"1313 (BC_2, IO_K19, input, X),\" & --  PAD578\n\t\"1314 (BC_2, *, controlr, 1),\" &\n\t\"1315 (BC_2, IO_G18, output3, X, 1314, 1, Z),\" & --  PAD577\n\t\"1316 (BC_2, IO_G18, input, X),\" & --  PAD577\n\t\"1317 (BC_2, *, controlr, 1),\" &\n\t\"1318 (BC_2, IO_H19, output3, X, 1317, 1, Z),\" & --  PAD576\n\t\"1319 (BC_2, IO_H19, input, X),\" & --  PAD576\n\t\"1320 (BC_2, *, controlr, 1),\" &\n\t\"1321 (BC_2, IO_E18, output3, X, 1320, 1, Z),\" & --  PAD575\n\t\"1322 (BC_2, IO_E18, input, X),\" & --  PAD575\n\t\"1323 (BC_2, *, controlr, 1),\" &\n\t\"1324 (BC_2, IO_E19, output3, X, 1323, 1, Z),\" & --  PAD574\n\t\"1325 (BC_2, IO_E19, input, X),\" & --  PAD574\n\t\"1326 (BC_2, *, controlr, 1),\" &\n\t\"1327 (BC_2, IO_F19, output3, X, 1326, 1, Z),\" & --  PAD573\n\t\"1328 (BC_2, IO_F19, input, X),\" & --  PAD573\n\t\"1329 (BC_2, *, controlr, 1),\" &\n\t\"1330 (BC_2, IO_G19, output3, X, 1329, 1, Z),\" & --  PAD572\n\t\"1331 (BC_2, IO_G19, input, X),\" & --  PAD572\n\t\"1332 (BC_2, *, controlr, 1),\" &\n\t\"1333 (BC_2, IO_D17, output3, X, 1332, 1, Z),\" & --  PAD571\n\t\"1334 (BC_2, IO_D17, input, X),\" & --  PAD571\n\t\"1335 (BC_2, *, controlr, 1),\" &\n\t\"1336 (BC_2, IO_D18, output3, X, 1335, 1, Z),\" & --  PAD570\n\t\"1337 (BC_2, IO_D18, input, X),\" & --  PAD570\n\t\"1338 (BC_2, *, controlr, 1),\" &\n\t\"1339 (BC_2, IO_C21, output3, X, 1338, 1, Z),\" & --  PAD569\n\t\"1340 (BC_2, IO_C21, input, X),\" & --  PAD569\n\t\"1341 (BC_2, *, controlr, 1),\" &\n\t\"1342 (BC_2, IO_D21, output3, X, 1341, 1, Z),\" & --  PAD568\n\t\"1343 (BC_2, IO_D21, input, X),\" & --  PAD568\n\t\"1344 (BC_2, *, controlr, 1),\" &\n\t\"1345 (BC_2, IO_E17, output3, X, 1344, 1, Z),\" & --  PAD567\n\t\"1346 (BC_2, IO_E17, input, X),\" & --  PAD567\n\t\"1347 (BC_2, *, controlr, 1),\" &\n\t\"1348 (BC_2, IO_F17, output3, X, 1347, 1, Z),\" & --  PAD566\n\t\"1349 (BC_2, IO_F17, input, X),\" & --  PAD566\n\t\"1350 (BC_2, *, controlr, 1),\" &\n\t\"1351 (BC_2, IO_C20, output3, X, 1350, 1, Z),\" & --  PAD565\n\t\"1352 (BC_2, IO_C20, input, X),\" & --  PAD565\n\t\"1353 (BC_2, *, controlr, 1),\" &\n\t\"1354 (BC_2, IO_D20, output3, X, 1353, 1, Z),\" & --  PAD564\n\t\"1355 (BC_2, IO_D20, input, X),\" & --  PAD564\n\t\"1356 (BC_2, *, controlr, 1),\" &\n\t\"1357 (BC_2, IO_B18, output3, X, 1356, 1, Z),\" & --  PAD563\n\t\"1358 (BC_2, IO_B18, input, X),\" & --  PAD563\n\t\"1359 (BC_2, *, controlr, 1),\" &\n\t\"1360 (BC_2, IO_C18, output3, X, 1359, 1, Z),\" & --  PAD562\n\t\"1361 (BC_2, IO_C18, input, X),\" & --  PAD562\n\t\"1362 (BC_2, *, controlr, 1),\" &\n\t\"1363 (BC_2, IO_A21, output3, X, 1362, 1, Z),\" & --  PAD561\n\t\"1364 (BC_2, IO_A21, input, X),\" & --  PAD561\n\t\"1365 (BC_2, *, controlr, 1),\" &\n\t\"1366 (BC_2, IO_B21, output3, X, 1365, 1, Z),\" & --  PAD560\n\t\"1367 (BC_2, IO_B21, input, X),\" & --  PAD560\n\t\"1368 (BC_2, *, controlr, 1),\" &\n\t\"1369 (BC_2, IO_A17, output3, X, 1368, 1, Z),\" & --  PAD559\n\t\"1370 (BC_2, IO_A17, input, X),\" & --  PAD559\n\t\"1371 (BC_2, *, controlr, 1),\" &\n\t\"1372 (BC_2, IO_B17, output3, X, 1371, 1, Z),\" & --  PAD558\n\t\"1373 (BC_2, IO_B17, input, X),\" & --  PAD558\n\t\"1374 (BC_2, *, controlr, 1),\" &\n\t\"1375 (BC_2, IO_A19, output3, X, 1374, 1, Z),\" & --  PAD557\n\t\"1376 (BC_2, IO_A19, input, X),\" & --  PAD557\n\t\"1377 (BC_2, *, controlr, 1),\" &\n\t\"1378 (BC_2, IO_A20, output3, X, 1377, 1, Z),\" & --  PAD556\n\t\"1379 (BC_2, IO_A20, input, X),\" & --  PAD556\n\t\"1380 (BC_2, *, controlr, 1),\" &\n\t\"1381 (BC_2, IO_A15, output3, X, 1380, 1, Z),\" & --  PAD555\n\t\"1382 (BC_2, IO_A15, input, X),\" & --  PAD555\n\t\"1383 (BC_2, *, controlr, 1),\" &\n\t\"1384 (BC_2, IO_A16, output3, X, 1383, 1, Z),\" & --  PAD554\n\t\"1385 (BC_2, IO_A16, input, X),\" & --  PAD554\n\t\"1386 (BC_2, *, controlr, 1),\" &\n\t\"1387 (BC_2, IO_B19, output3, X, 1386, 1, Z),\" & --  PAD553\n\t\"1388 (BC_2, IO_B19, input, X),\" & --  PAD553\n\t\"1389 (BC_2, *, controlr, 1),\" &\n\t\"1390 (BC_2, IO_C19, output3, X, 1389, 1, Z),\" & --  PAD552\n\t\"1391 (BC_2, IO_C19, input, X),\" & --  PAD552\n\t\"1392 (BC_2, *, controlr, 1),\" &\n\t\"1393 (BC_2, IO_K18, output3, X, 1392, 1, Z),\" & --  PAD551\n\t\"1394 (BC_2, IO_K18, input, X),\" & --  PAD551\n\t\"1395 (BC_2, *, controlr, 1),\" &\n\t\"1396 (BC_2, IO_J11, output3, X, 1395, 1, Z),\" & --  PAD550\n\t\"1397 (BC_2, IO_J11, input, X),\" & --  PAD550\n\t\"1398 (BC_2, *, controlr, 1),\" &\n\t\"1399 (BC_2, IO_M11, output3, X, 1398, 1, Z),\" & --  PAD549\n\t\"1400 (BC_2, IO_M11, input, X),\" & --  PAD549\n\t\"1401 (BC_2, *, controlr, 1),\" &\n\t\"1402 (BC_2, IO_M12, output3, X, 1401, 1, Z),\" & --  PAD548\n\t\"1403 (BC_2, IO_M12, input, X),\" & --  PAD548\n\t\"1404 (BC_2, *, controlr, 1),\" &\n\t\"1405 (BC_2, IO_N14, output3, X, 1404, 1, Z),\" & --  PAD547\n\t\"1406 (BC_2, IO_N14, input, X),\" & --  PAD547\n\t\"1407 (BC_2, *, controlr, 1),\" &\n\t\"1408 (BC_2, IO_N15, output3, X, 1407, 1, Z),\" & --  PAD546\n\t\"1409 (BC_2, IO_N15, input, X),\" & --  PAD546\n\t\"1410 (BC_2, *, controlr, 1),\" &\n\t\"1411 (BC_2, IO_M13, output3, X, 1410, 1, Z),\" & --  PAD545\n\t\"1412 (BC_2, IO_M13, input, X),\" & --  PAD545\n\t\"1413 (BC_2, *, controlr, 1),\" &\n\t\"1414 (BC_2, IO_N13, output3, X, 1413, 1, Z),\" & --  PAD544\n\t\"1415 (BC_2, IO_N13, input, X),\" & --  PAD544\n\t\"1416 (BC_2, *, controlr, 1),\" &\n\t\"1417 (BC_2, IO_M16, output3, X, 1416, 1, Z),\" & --  PAD543\n\t\"1418 (BC_2, IO_M16, input, X),\" & --  PAD543\n\t\"1419 (BC_2, *, controlr, 1),\" &\n\t\"1420 (BC_2, IO_N16, output3, X, 1419, 1, Z),\" & --  PAD542\n\t\"1421 (BC_2, IO_N16, input, X),\" & --  PAD542\n\t\"1422 (BC_2, *, controlr, 1),\" &\n\t\"1423 (BC_2, IO_L14, output3, X, 1422, 1, Z),\" & --  PAD541\n\t\"1424 (BC_2, IO_L14, input, X),\" & --  PAD541\n\t\"1425 (BC_2, *, controlr, 1),\" &\n\t\"1426 (BC_2, IO_M14, output3, X, 1425, 1, Z),\" & --  PAD540\n\t\"1427 (BC_2, IO_M14, input, X),\" & --  PAD540\n\t\"1428 (BC_2, *, controlr, 1),\" &\n\t\"1429 (BC_2, IO_L11, output3, X, 1428, 1, Z),\" & --  PAD539\n\t\"1430 (BC_2, IO_L11, input, X),\" & --  PAD539\n\t\"1431 (BC_2, *, controlr, 1),\" &\n\t\"1432 (BC_2, IO_L12, output3, X, 1431, 1, Z),\" & --  PAD538\n\t\"1433 (BC_2, IO_L12, input, X),\" & --  PAD538\n\t\"1434 (BC_2, *, controlr, 1),\" &\n\t\"1435 (BC_2, IO_L15, output3, X, 1434, 1, Z),\" & --  PAD537\n\t\"1436 (BC_2, IO_L15, input, X),\" & --  PAD537\n\t\"1437 (BC_2, *, controlr, 1),\" &\n\t\"1438 (BC_2, IO_L16, output3, X, 1437, 1, Z),\" & --  PAD536\n\t\"1439 (BC_2, IO_L16, input, X),\" & --  PAD536\n\t\"1440 (BC_2, *, controlr, 1),\" &\n\t\"1441 (BC_2, IO_K13, output3, X, 1440, 1, Z),\" & --  PAD535\n\t\"1442 (BC_2, IO_K13, input, X),\" & --  PAD535\n\t\"1443 (BC_2, *, controlr, 1),\" &\n\t\"1444 (BC_2, IO_K14, output3, X, 1443, 1, Z),\" & --  PAD534\n\t\"1445 (BC_2, IO_K14, input, X),\" & --  PAD534\n\t\"1446 (BC_2, *, controlr, 1),\" &\n\t\"1447 (BC_2, IO_J15, output3, X, 1446, 1, Z),\" & --  PAD533\n\t\"1448 (BC_2, IO_J15, input, X),\" & --  PAD533\n\t\"1449 (BC_2, *, controlr, 1),\" &\n\t\"1450 (BC_2, IO_K15, output3, X, 1449, 1, Z),\" & --  PAD532\n\t\"1451 (BC_2, IO_K15, input, X),\" & --  PAD532\n\t\"1452 (BC_2, *, controlr, 1),\" &\n\t\"1453 (BC_2, IO_J12, output3, X, 1452, 1, Z),\" & --  PAD531\n\t\"1454 (BC_2, IO_J12, input, X),\" & --  PAD531\n\t\"1455 (BC_2, *, controlr, 1),\" &\n\t\"1456 (BC_2, IO_K12, output3, X, 1455, 1, Z),\" & --  PAD530\n\t\"1457 (BC_2, IO_K12, input, X),\" & --  PAD530\n\t\"1458 (BC_2, *, controlr, 1),\" &\n\t\"1459 (BC_2, IO_H13, output3, X, 1458, 1, Z),\" & --  PAD529\n\t\"1460 (BC_2, IO_H13, input, X),\" & --  PAD529\n\t\"1461 (BC_2, *, controlr, 1),\" &\n\t\"1462 (BC_2, IO_J13, output3, X, 1461, 1, Z),\" & --  PAD528\n\t\"1463 (BC_2, IO_J13, input, X),\" & --  PAD528\n\t\"1464 (BC_2, *, controlr, 1),\" &\n\t\"1465 (BC_2, IO_H14, output3, X, 1464, 1, Z),\" & --  PAD527\n\t\"1466 (BC_2, IO_H14, input, X),\" & --  PAD527\n\t\"1467 (BC_2, *, controlr, 1),\" &\n\t\"1468 (BC_2, IO_H15, output3, X, 1467, 1, Z),\" & --  PAD526\n\t\"1469 (BC_2, IO_H15, input, X),\" & --  PAD526\n\t\"1470 (BC_2, *, controlr, 1),\" &\n\t\"1471 (BC_2, IO_G13, output3, X, 1470, 1, Z),\" & --  PAD525\n\t\"1472 (BC_2, IO_G13, input, X),\" & --  PAD525\n\t\"1473 (BC_2, *, controlr, 1),\" &\n\t\"1474 (BC_2, IO_G14, output3, X, 1473, 1, Z),\" & --  PAD524\n\t\"1475 (BC_2, IO_G14, input, X),\" & --  PAD524\n\t\"1476 (BC_2, *, controlr, 1),\" &\n\t\"1477 (BC_2, IO_F14, output3, X, 1476, 1, Z),\" & --  PAD523\n\t\"1478 (BC_2, IO_F14, input, X),\" & --  PAD523\n\t\"1479 (BC_2, *, controlr, 1),\" &\n\t\"1480 (BC_2, IO_F15, output3, X, 1479, 1, Z),\" & --  PAD522\n\t\"1481 (BC_2, IO_F15, input, X),\" & --  PAD522\n\t\"1482 (BC_2, *, controlr, 1),\" &\n\t\"1483 (BC_2, IO_F12, output3, X, 1482, 1, Z),\" & --  PAD521\n\t\"1484 (BC_2, IO_F12, input, X),\" & --  PAD521\n\t\"1485 (BC_2, *, controlr, 1),\" &\n\t\"1486 (BC_2, IO_G12, output3, X, 1485, 1, Z),\" & --  PAD520\n\t\"1487 (BC_2, IO_G12, input, X),\" & --  PAD520\n\t\"1488 (BC_2, *, controlr, 1),\" &\n\t\"1489 (BC_2, IO_G16, output3, X, 1488, 1, Z),\" & --  PAD519\n\t\"1490 (BC_2, IO_G16, input, X),\" & --  PAD519\n\t\"1491 (BC_2, *, controlr, 1),\" &\n\t\"1492 (BC_2, IO_H16, output3, X, 1491, 1, Z),\" & --  PAD518\n\t\"1493 (BC_2, IO_H16, input, X),\" & --  PAD518\n\t\"1494 (BC_2, *, controlr, 1),\" &\n\t\"1495 (BC_2, IO_E13, output3, X, 1494, 1, Z),\" & --  PAD517\n\t\"1496 (BC_2, IO_E13, input, X),\" & --  PAD517\n\t\"1497 (BC_2, *, controlr, 1),\" &\n\t\"1498 (BC_2, IO_E14, output3, X, 1497, 1, Z),\" & --  PAD516\n\t\"1499 (BC_2, IO_E14, input, X),\" & --  PAD516\n\t\"1500 (BC_2, *, controlr, 1),\" &\n\t\"1501 (BC_2, IO_E15, output3, X, 1500, 1, Z),\" & --  PAD515\n\t\"1502 (BC_2, IO_E15, input, X),\" & --  PAD515\n\t\"1503 (BC_2, *, controlr, 1),\" &\n\t\"1504 (BC_2, IO_F16, output3, X, 1503, 1, Z),\" & --  PAD514\n\t\"1505 (BC_2, IO_F16, input, X),\" & --  PAD514\n\t\"1506 (BC_2, *, controlr, 1),\" &\n\t\"1507 (BC_2, IO_D12, output3, X, 1506, 1, Z),\" & --  PAD513\n\t\"1508 (BC_2, IO_D12, input, X),\" & --  PAD513\n\t\"1509 (BC_2, *, controlr, 1),\" &\n\t\"1510 (BC_2, IO_E12, output3, X, 1509, 1, Z),\" & --  PAD512\n\t\"1511 (BC_2, IO_E12, input, X),\" & --  PAD512\n\t\"1512 (BC_2, *, controlr, 1),\" &\n\t\"1513 (BC_2, IO_D15, output3, X, 1512, 1, Z),\" & --  PAD511\n\t\"1514 (BC_2, IO_D15, input, X),\" & --  PAD511\n\t\"1515 (BC_2, *, controlr, 1),\" &\n\t\"1516 (BC_2, IO_D16, output3, X, 1515, 1, Z),\" & --  PAD510\n\t\"1517 (BC_2, IO_D16, input, X),\" & --  PAD510\n\t\"1518 (BC_2, *, controlr, 1),\" &\n\t\"1519 (BC_2, IO_C13, output3, X, 1518, 1, Z),\" & --  PAD509\n\t\"1520 (BC_2, IO_C13, input, X),\" & --  PAD509\n\t\"1521 (BC_2, *, controlr, 1),\" &\n\t\"1522 (BC_2, IO_D13, output3, X, 1521, 1, Z),\" & --  PAD508\n\t\"1523 (BC_2, IO_D13, input, X),\" & --  PAD508\n\t\"1524 (BC_2, *, controlr, 1),\" &\n\t\"1525 (BC_2, IO_C14, output3, X, 1524, 1, Z),\" & --  PAD507\n\t\"1526 (BC_2, IO_C14, input, X),\" & --  PAD507\n\t\"1527 (BC_2, *, controlr, 1),\" &\n\t\"1528 (BC_2, IO_C15, output3, X, 1527, 1, Z),\" & --  PAD506\n\t\"1529 (BC_2, IO_C15, input, X),\" & --  PAD506\n\t\"1530 (BC_2, *, controlr, 1),\" &\n\t\"1531 (BC_2, IO_A14, output3, X, 1530, 1, Z),\" & --  PAD505\n\t\"1532 (BC_2, IO_A14, input, X),\" & --  PAD505\n\t\"1533 (BC_2, *, controlr, 1),\" &\n\t\"1534 (BC_2, IO_B14, output3, X, 1533, 1, Z),\" & --  PAD504\n\t\"1535 (BC_2, IO_B14, input, X),\" & --  PAD504\n\t\"1536 (BC_2, *, controlr, 1),\" &\n\t\"1537 (BC_2, IO_B16, output3, X, 1536, 1, Z),\" & --  PAD503\n\t\"1538 (BC_2, IO_B16, input, X),\" & --  PAD503\n\t\"1539 (BC_2, *, controlr, 1),\" &\n\t\"1540 (BC_2, IO_C16, output3, X, 1539, 1, Z),\" & --  PAD502\n\t\"1541 (BC_2, IO_C16, input, X),\" & --  PAD502\n\t\"1542 (BC_2, *, controlr, 1),\" &\n\t\"1543 (BC_2, IO_J16, output3, X, 1542, 1, Z),\" & --  PAD501\n\t\"1544 (BC_2, IO_J16, input, X),\" & --  PAD501\n\t\"1545 (BC_2, *, internal, X),\" &\n\t\"1546 (BC_2, *, internal, X),\" &\n\t\"1547 (BC_2, *, internal, X),\" &\n\t\"1548 (BC_2, *, internal, X),\" &\n\t\"1549 (BC_2, *, internal, X),\" &\n\t\"1550 (BC_2, *, internal, X),\" &\n\t\"1551 (BC_2, *, internal, X),\" &\n\t\"1552 (BC_2, *, internal, X),\" &\n\t\"1553 (BC_2, *, internal, X),\" &\n\t\"1554 (BC_2, *, internal, X),\" &\n\t\"1555 (BC_2, *, internal, X),\" &\n\t\"1556 (BC_2, *, internal, X),\" &\n\t\"1557 (BC_2, *, internal, X),\" &\n\t\"1558 (BC_2, *, internal, X),\" &\n\t\"1559 (BC_2, *, internal, X),\" &\n\t\"1560 (BC_2, *, internal, X),\" &\n\t\"1561 (BC_2, *, internal, X),\" &\n\t\"1562 (BC_2, *, internal, X),\" &\n\t\"1563 (BC_2, *, internal, X),\" &\n\t\"1564 (BC_2, *, internal, X),\" &\n\t\"1565 (BC_2, *, internal, X),\" &\n\t\"1566 (BC_4, *, internal, X),\" &\n\t\"1567 (BC_4, *, internal, X),\" &\n\t\"1568 (BC_4, *, internal, X),\" &\n\t\"1569 (BC_4, *, internal, X),\" &\n\t\"1570 (BC_4, *, internal, X),\" &\n\t\"1571 (BC_4, *, internal, X),\" &\n\t\"1572 (BC_4, *, internal, X),\" &\n\t\"1573 (BC_4, *, internal, X),\" &\n\t\"1574 (BC_4, *, internal, X),\" &\n\t\"1575 (BC_4, *, internal, X),\" &\n\t\"1576 (BC_4, *, internal, X),\" &\n\t\"1577 (BC_4, *, internal, X),\" &\n\t\"1578 (BC_4, MGTHRXN0_111, OBSERVE_ONLY, X),\" &\n\t\"1579 (BC_4, MGTHRXP0_111, OBSERVE_ONLY, X),\" &\n\t\"1580 (AC_2, MGTHTXP0_111, OUTPUT2, X),\" &\n\t\"1581 (BC_4, MGTHRXN1_111, OBSERVE_ONLY, X),\" &\n\t\"1582 (BC_4, MGTHRXP1_111, OBSERVE_ONLY, X),\" &\n\t\"1583 (AC_2, MGTHTXP1_111, OUTPUT2, X),\" &\n\t\"1584 (BC_4, MGTHRXN2_111, OBSERVE_ONLY, X),\" &\n\t\"1585 (BC_4, MGTHRXP2_111, OBSERVE_ONLY, X),\" &\n\t\"1586 (AC_2, MGTHTXP2_111, OUTPUT2, X),\" &\n\t\"1587 (BC_4, MGTHRXN3_111, OBSERVE_ONLY, X),\" &\n\t\"1588 (BC_4, MGTHRXP3_111, OBSERVE_ONLY, X),\" &\n\t\"1589 (AC_2, MGTHTXP3_111, OUTPUT2, X),\" &\n\t\"1590 (BC_4, MGTHRXN0_112, OBSERVE_ONLY, X),\" &\n\t\"1591 (BC_4, MGTHRXP0_112, OBSERVE_ONLY, X),\" &\n\t\"1592 (AC_2, MGTHTXP0_112, OUTPUT2, X),\" &\n\t\"1593 (BC_4, MGTHRXN1_112, OBSERVE_ONLY, X),\" &\n\t\"1594 (BC_4, MGTHRXP1_112, OBSERVE_ONLY, X),\" &\n\t\"1595 (AC_2, MGTHTXP1_112, OUTPUT2, X),\" &\n\t\"1596 (BC_4, MGTHRXN2_112, OBSERVE_ONLY, X),\" &\n\t\"1597 (BC_4, MGTHRXP2_112, OBSERVE_ONLY, X),\" &\n\t\"1598 (AC_2, MGTHTXP2_112, OUTPUT2, X),\" &\n\t\"1599 (BC_4, MGTHRXN3_112, OBSERVE_ONLY, X),\" &\n\t\"1600 (BC_4, MGTHRXP3_112, OBSERVE_ONLY, X),\" &\n\t\"1601 (AC_2, MGTHTXP3_112, OUTPUT2, X),\" &\n\t\"1602 (BC_4, MGTHRXN0_113, OBSERVE_ONLY, X),\" &\n\t\"1603 (BC_4, MGTHRXP0_113, OBSERVE_ONLY, X),\" &\n\t\"1604 (AC_2, MGTHTXP0_113, OUTPUT2, X),\" &\n\t\"1605 (BC_4, MGTHRXN1_113, OBSERVE_ONLY, X),\" &\n\t\"1606 (BC_4, MGTHRXP1_113, OBSERVE_ONLY, X),\" &\n\t\"1607 (AC_2, MGTHTXP1_113, OUTPUT2, X),\" &\n\t\"1608 (BC_4, MGTHRXN2_113, OBSERVE_ONLY, X),\" &\n\t\"1609 (BC_4, MGTHRXP2_113, OBSERVE_ONLY, X),\" &\n\t\"1610 (AC_2, MGTHTXP2_113, OUTPUT2, X),\" &\n\t\"1611 (BC_4, MGTHRXN3_113, OBSERVE_ONLY, X),\" &\n\t\"1612 (BC_4, MGTHRXP3_113, OBSERVE_ONLY, X),\" &\n\t\"1613 (AC_2, MGTHTXP3_113, OUTPUT2, X),\" &\n\t\"1614 (BC_4, MGTHRXN0_114, OBSERVE_ONLY, X),\" &\n\t\"1615 (BC_4, MGTHRXP0_114, OBSERVE_ONLY, X),\" &\n\t\"1616 (AC_2, MGTHTXP0_114, OUTPUT2, X),\" &\n\t\"1617 (BC_4, MGTHRXN1_114, OBSERVE_ONLY, X),\" &\n\t\"1618 (BC_4, MGTHRXP1_114, OBSERVE_ONLY, X),\" &\n\t\"1619 (AC_2, MGTHTXP1_114, OUTPUT2, X),\" &\n\t\"1620 (BC_4, MGTHRXN2_114, OBSERVE_ONLY, X),\" &\n\t\"1621 (BC_4, MGTHRXP2_114, OBSERVE_ONLY, X),\" &\n\t\"1622 (AC_2, MGTHTXP2_114, OUTPUT2, X),\" &\n\t\"1623 (BC_4, MGTHRXN3_114, OBSERVE_ONLY, X),\" &\n\t\"1624 (BC_4, MGTHRXP3_114, OBSERVE_ONLY, X),\" &\n\t\"1625 (AC_2, MGTHTXP3_114, OUTPUT2, X),\" &\n\t\"1626 (BC_4, MGTHRXN0_115, OBSERVE_ONLY, X),\" &\n\t\"1627 (BC_4, MGTHRXP0_115, OBSERVE_ONLY, X),\" &\n\t\"1628 (AC_2, MGTHTXP0_115, OUTPUT2, X),\" &\n\t\"1629 (BC_4, MGTHRXN1_115, OBSERVE_ONLY, X),\" &\n\t\"1630 (BC_4, MGTHRXP1_115, OBSERVE_ONLY, X),\" &\n\t\"1631 (AC_2, MGTHTXP1_115, OUTPUT2, X),\" &\n\t\"1632 (BC_4, MGTHRXN2_115, OBSERVE_ONLY, X),\" &\n\t\"1633 (BC_4, MGTHRXP2_115, OBSERVE_ONLY, X),\" &\n\t\"1634 (AC_2, MGTHTXP2_115, OUTPUT2, X),\" &\n\t\"1635 (BC_4, MGTHRXN3_115, OBSERVE_ONLY, X),\" &\n\t\"1636 (BC_4, MGTHRXP3_115, OBSERVE_ONLY, X),\" &\n\t\"1637 (AC_2, MGTHTXP3_115, OUTPUT2, X),\" &\n\t\"1638 (BC_4, MGTHRXN0_116, OBSERVE_ONLY, X),\" &\n\t\"1639 (BC_4, MGTHRXP0_116, OBSERVE_ONLY, X),\" &\n\t\"1640 (AC_2, MGTHTXP0_116, OUTPUT2, X),\" &\n\t\"1641 (BC_4, MGTHRXN1_116, OBSERVE_ONLY, X),\" &\n\t\"1642 (BC_4, MGTHRXP1_116, OBSERVE_ONLY, X),\" &\n\t\"1643 (AC_2, MGTHTXP1_116, OUTPUT2, X),\" &\n\t\"1644 (BC_4, MGTHRXN2_116, OBSERVE_ONLY, X),\" &\n\t\"1645 (BC_4, MGTHRXP2_116, OBSERVE_ONLY, X),\" &\n\t\"1646 (AC_2, MGTHTXP2_116, OUTPUT2, X),\" &\n\t\"1647 (BC_4, MGTHRXN3_116, OBSERVE_ONLY, X),\" &\n\t\"1648 (BC_4, MGTHRXP3_116, OBSERVE_ONLY, X),\" &\n\t\"1649 (AC_2, MGTHTXP3_116, OUTPUT2, X),\" &\n\t\"1650 (BC_4, MGTHRXN0_117, OBSERVE_ONLY, X),\" &\n\t\"1651 (BC_4, MGTHRXP0_117, OBSERVE_ONLY, X),\" &\n\t\"1652 (AC_2, MGTHTXP0_117, OUTPUT2, X),\" &\n\t\"1653 (BC_4, MGTHRXN1_117, OBSERVE_ONLY, X),\" &\n\t\"1654 (BC_4, MGTHRXP1_117, OBSERVE_ONLY, X),\" &\n\t\"1655 (AC_2, MGTHTXP1_117, OUTPUT2, X),\" &\n\t\"1656 (BC_4, MGTHRXN2_117, OBSERVE_ONLY, X),\" &\n\t\"1657 (BC_4, MGTHRXP2_117, OBSERVE_ONLY, X),\" &\n\t\"1658 (AC_2, MGTHTXP2_117, OUTPUT2, X),\" &\n\t\"1659 (BC_4, MGTHRXN3_117, OBSERVE_ONLY, X),\" &\n\t\"1660 (BC_4, MGTHRXP3_117, OBSERVE_ONLY, X),\" &\n\t\"1661 (AC_2, MGTHTXP3_117, OUTPUT2, X),\" &\n\t\"1662 (BC_4, MGTHRXN0_118, OBSERVE_ONLY, X),\" &\n\t\"1663 (BC_4, MGTHRXP0_118, OBSERVE_ONLY, X),\" &\n\t\"1664 (AC_2, MGTHTXP0_118, OUTPUT2, X),\" &\n\t\"1665 (BC_4, MGTHRXN1_118, OBSERVE_ONLY, X),\" &\n\t\"1666 (BC_4, MGTHRXP1_118, OBSERVE_ONLY, X),\" &\n\t\"1667 (AC_2, MGTHTXP1_118, OUTPUT2, X),\" &\n\t\"1668 (BC_4, MGTHRXN2_118, OBSERVE_ONLY, X),\" &\n\t\"1669 (BC_4, MGTHRXP2_118, OBSERVE_ONLY, X),\" &\n\t\"1670 (AC_2, MGTHTXP2_118, OUTPUT2, X),\" &\n\t\"1671 (BC_4, MGTHRXN3_118, OBSERVE_ONLY, X),\" &\n\t\"1672 (BC_4, MGTHRXP3_118, OBSERVE_ONLY, X),\" &\n\t\"1673 (AC_2, MGTHTXP3_118, OUTPUT2, X),\" &\n\t\"1674 (BC_4, MGTHRXN0_119, OBSERVE_ONLY, X),\" &\n\t\"1675 (BC_4, MGTHRXP0_119, OBSERVE_ONLY, X),\" &\n\t\"1676 (AC_2, MGTHTXP0_119, OUTPUT2, X),\" &\n\t\"1677 (BC_4, MGTHRXN1_119, OBSERVE_ONLY, X),\" &\n\t\"1678 (BC_4, MGTHRXP1_119, OBSERVE_ONLY, X),\" &\n\t\"1679 (AC_2, MGTHTXP1_119, OUTPUT2, X),\" &\n\t\"1680 (BC_4, MGTHRXN2_119, OBSERVE_ONLY, X),\" &\n\t\"1681 (BC_4, MGTHRXP2_119, OBSERVE_ONLY, X),\" &\n\t\"1682 (AC_2, MGTHTXP2_119, OUTPUT2, X),\" &\n\t\"1683 (BC_4, MGTHRXN3_119, OBSERVE_ONLY, X),\" &\n\t\"1684 (BC_4, MGTHRXP3_119, OBSERVE_ONLY, X),\" &\n\t\"1685 (AC_2, MGTHTXP3_119, OUTPUT2, X),\" &\n\t\"1686 (BC_2, *, internal, X),\" &\n\t\"1687 (BC_2, *, internal, X),\" &\n\t\"1688 (BC_2, *, internal, X),\" &\n\t\"1689 (BC_2, *, internal, X),\" &\n\t\"1690 (BC_2, *, internal, X),\" &\n\t\"1691 (BC_2, *, internal, X),\" &\n\t\"1692 (BC_2, *, internal, X),\" &\n\t\"1693 (BC_2, *, internal, X),\" &\n\t\"1694 (BC_2, *, internal, X),\" &\n\t\"1695 (BC_2, *, internal, X),\" &\n\t\"1696 (BC_2, *, internal, X),\" &\n\t\"1697 (BC_2, *, internal, X),\" &\n\t\"1698 (BC_2, *, internal, X),\" &\n\t\"1699 (BC_2, *, internal, X),\" &\n\t\"1700 (BC_2, *, internal, X),\" &\n\t\"1701 (BC_2, *, internal, X),\" &\n\t\"1702 (BC_2, *, internal, X),\" &\n\t\"1703 (BC_2, *, internal, X),\" &\n\t\"1704 (BC_2, *, internal, X),\" &\n\t\"1705 (BC_2, *, internal, X),\" &\n\t\"1706 (BC_2, *, internal, X),\" &\n\t\"1707 (BC_2, *, internal, X),\" &\n\t\"1708 (BC_2, *, internal, X),\" &\n\t\"1709 (BC_2, *, internal, X),\" &\n\t\"1710 (BC_2, *, internal, X),\" &\n\t\"1711 (BC_2, *, internal, X),\" &\n\t\"1712 (BC_2, *, internal, X),\" &\n\t\"1713 (BC_2, *, internal, X),\" &\n\t\"1714 (BC_2, *, internal, X),\" &\n\t\"1715 (BC_2, *, internal, X),\" &\n\t\"1716 (BC_2, *, internal, X),\" &\n\t\"1717 (BC_2, *, internal, X),\" &\n\t\"1718 (BC_2, *, internal, X),\" &\n\t\"1719 (BC_2, *, internal, X),\" &\n\t\"1720 (BC_2, *, internal, X),\" &\n\t\"1721 (BC_2, *, internal, X),\" &\n\t\"1722 (BC_2, *, internal, X),\" &\n\t\"1723 (BC_2, *, internal, X),\" &\n\t\"1724 (BC_2, *, internal, X),\" &\n\t\"1725 (BC_2, *, internal, X),\" &\n\t\"1726 (BC_2, *, internal, 1),\" & --  PAD500.T\n\t\"1727 (BC_2, *, internal, X),\" & --  PAD500.O\n\t\"1728 (BC_2, *, internal, X),\" & --  PAD500.I\n\t\"1729 (BC_2, *, internal, 1),\" & --  PAD499.T\n\t\"1730 (BC_2, *, internal, X),\" & --  PAD499.O\n\t\"1731 (BC_2, *, internal, X),\" & --  PAD499.I\n\t\"1732 (BC_2, *, internal, 1),\" & --  PAD498.T\n\t\"1733 (BC_2, *, internal, X),\" & --  PAD498.O\n\t\"1734 (BC_2, *, internal, X),\" & --  PAD498.I\n\t\"1735 (BC_2, *, internal, 1),\" & --  PAD497.T\n\t\"1736 (BC_2, *, internal, X),\" & --  PAD497.O\n\t\"1737 (BC_2, *, internal, X),\" & --  PAD497.I\n\t\"1738 (BC_2, *, internal, 1),\" & --  PAD496.T\n\t\"1739 (BC_2, *, internal, X),\" & --  PAD496.O\n\t\"1740 (BC_2, *, internal, X),\" & --  PAD496.I\n\t\"1741 (BC_2, *, internal, 1),\" & --  PAD495.T\n\t\"1742 (BC_2, *, internal, X),\" & --  PAD495.O\n\t\"1743 (BC_2, *, internal, X),\" & --  PAD495.I\n\t\"1744 (BC_2, *, internal, 1),\" & --  PAD494.T\n\t\"1745 (BC_2, *, internal, X),\" & --  PAD494.O\n\t\"1746 (BC_2, *, internal, X),\" & --  PAD494.I\n\t\"1747 (BC_2, *, internal, 1),\" & --  PAD493.T\n\t\"1748 (BC_2, *, internal, X),\" & --  PAD493.O\n\t\"1749 (BC_2, *, internal, X),\" & --  PAD493.I\n\t\"1750 (BC_2, *, internal, 1),\" & --  PAD492.T\n\t\"1751 (BC_2, *, internal, X),\" & --  PAD492.O\n\t\"1752 (BC_2, *, internal, X),\" & --  PAD492.I\n\t\"1753 (BC_2, *, internal, 1),\" & --  PAD491.T\n\t\"1754 (BC_2, *, internal, X),\" & --  PAD491.O\n\t\"1755 (BC_2, *, internal, X),\" & --  PAD491.I\n\t\"1756 (BC_2, *, internal, 1),\" & --  PAD490.T\n\t\"1757 (BC_2, *, internal, X),\" & --  PAD490.O\n\t\"1758 (BC_2, *, internal, X),\" & --  PAD490.I\n\t\"1759 (BC_2, *, internal, 1),\" & --  PAD489.T\n\t\"1760 (BC_2, *, internal, X),\" & --  PAD489.O\n\t\"1761 (BC_2, *, internal, X),\" & --  PAD489.I\n\t\"1762 (BC_2, *, internal, 1),\" & --  PAD488.T\n\t\"1763 (BC_2, *, internal, X),\" & --  PAD488.O\n\t\"1764 (BC_2, *, internal, X),\" & --  PAD488.I\n\t\"1765 (BC_2, *, internal, 1),\" & --  PAD487.T\n\t\"1766 (BC_2, *, internal, X),\" & --  PAD487.O\n\t\"1767 (BC_2, *, internal, X),\" & --  PAD487.I\n\t\"1768 (BC_2, *, internal, 1),\" & --  PAD486.T\n\t\"1769 (BC_2, *, internal, X),\" & --  PAD486.O\n\t\"1770 (BC_2, *, internal, X),\" & --  PAD486.I\n\t\"1771 (BC_2, *, internal, 1),\" & --  PAD485.T\n\t\"1772 (BC_2, *, internal, X),\" & --  PAD485.O\n\t\"1773 (BC_2, *, internal, X),\" & --  PAD485.I\n\t\"1774 (BC_2, *, internal, 1),\" & --  PAD484.T\n\t\"1775 (BC_2, *, internal, X),\" & --  PAD484.O\n\t\"1776 (BC_2, *, internal, X),\" & --  PAD484.I\n\t\"1777 (BC_2, *, internal, 1),\" & --  PAD483.T\n\t\"1778 (BC_2, *, internal, X),\" & --  PAD483.O\n\t\"1779 (BC_2, *, internal, X),\" & --  PAD483.I\n\t\"1780 (BC_2, *, internal, 1),\" & --  PAD482.T\n\t\"1781 (BC_2, *, internal, X),\" & --  PAD482.O\n\t\"1782 (BC_2, *, internal, X),\" & --  PAD482.I\n\t\"1783 (BC_2, *, internal, 1),\" & --  PAD481.T\n\t\"1784 (BC_2, *, internal, X),\" & --  PAD481.O\n\t\"1785 (BC_2, *, internal, X),\" & --  PAD481.I\n\t\"1786 (BC_2, *, internal, 1),\" & --  PAD480.T\n\t\"1787 (BC_2, *, internal, X),\" & --  PAD480.O\n\t\"1788 (BC_2, *, internal, X),\" & --  PAD480.I\n\t\"1789 (BC_2, *, internal, 1),\" & --  PAD479.T\n\t\"1790 (BC_2, *, internal, X),\" & --  PAD479.O\n\t\"1791 (BC_2, *, internal, X),\" & --  PAD479.I\n\t\"1792 (BC_2, *, internal, 1),\" & --  PAD478.T\n\t\"1793 (BC_2, *, internal, X),\" & --  PAD478.O\n\t\"1794 (BC_2, *, internal, X),\" & --  PAD478.I\n\t\"1795 (BC_2, *, internal, 1),\" & --  PAD477.T\n\t\"1796 (BC_2, *, internal, X),\" & --  PAD477.O\n\t\"1797 (BC_2, *, internal, X),\" & --  PAD477.I\n\t\"1798 (BC_2, *, internal, 1),\" & --  PAD476.T\n\t\"1799 (BC_2, *, internal, X),\" & --  PAD476.O\n\t\"1800 (BC_2, *, internal, X),\" & --  PAD476.I\n\t\"1801 (BC_2, *, internal, 1),\" & --  PAD475.T\n\t\"1802 (BC_2, *, internal, X),\" & --  PAD475.O\n\t\"1803 (BC_2, *, internal, X),\" & --  PAD475.I\n\t\"1804 (BC_2, *, internal, 1),\" & --  PAD474.T\n\t\"1805 (BC_2, *, internal, X),\" & --  PAD474.O\n\t\"1806 (BC_2, *, internal, X),\" & --  PAD474.I\n\t\"1807 (BC_2, *, internal, 1),\" & --  PAD473.T\n\t\"1808 (BC_2, *, internal, X),\" & --  PAD473.O\n\t\"1809 (BC_2, *, internal, X),\" & --  PAD473.I\n\t\"1810 (BC_2, *, internal, 1),\" & --  PAD472.T\n\t\"1811 (BC_2, *, internal, X),\" & --  PAD472.O\n\t\"1812 (BC_2, *, internal, X),\" & --  PAD472.I\n\t\"1813 (BC_2, *, internal, 1),\" & --  PAD471.T\n\t\"1814 (BC_2, *, internal, X),\" & --  PAD471.O\n\t\"1815 (BC_2, *, internal, X),\" & --  PAD471.I\n\t\"1816 (BC_2, *, internal, 1),\" & --  PAD470.T\n\t\"1817 (BC_2, *, internal, X),\" & --  PAD470.O\n\t\"1818 (BC_2, *, internal, X),\" & --  PAD470.I\n\t\"1819 (BC_2, *, internal, 1),\" & --  PAD469.T\n\t\"1820 (BC_2, *, internal, X),\" & --  PAD469.O\n\t\"1821 (BC_2, *, internal, X),\" & --  PAD469.I\n\t\"1822 (BC_2, *, internal, 1),\" & --  PAD468.T\n\t\"1823 (BC_2, *, internal, X),\" & --  PAD468.O\n\t\"1824 (BC_2, *, internal, X),\" & --  PAD468.I\n\t\"1825 (BC_2, *, internal, 1),\" & --  PAD467.T\n\t\"1826 (BC_2, *, internal, X),\" & --  PAD467.O\n\t\"1827 (BC_2, *, internal, X),\" & --  PAD467.I\n\t\"1828 (BC_2, *, internal, 1),\" & --  PAD466.T\n\t\"1829 (BC_2, *, internal, X),\" & --  PAD466.O\n\t\"1830 (BC_2, *, internal, X),\" & --  PAD466.I\n\t\"1831 (BC_2, *, internal, 1),\" & --  PAD465.T\n\t\"1832 (BC_2, *, internal, X),\" & --  PAD465.O\n\t\"1833 (BC_2, *, internal, X),\" & --  PAD465.I\n\t\"1834 (BC_2, *, internal, 1),\" & --  PAD464.T\n\t\"1835 (BC_2, *, internal, X),\" & --  PAD464.O\n\t\"1836 (BC_2, *, internal, X),\" & --  PAD464.I\n\t\"1837 (BC_2, *, internal, 1),\" & --  PAD463.T\n\t\"1838 (BC_2, *, internal, X),\" & --  PAD463.O\n\t\"1839 (BC_2, *, internal, X),\" & --  PAD463.I\n\t\"1840 (BC_2, *, internal, 1),\" & --  PAD462.T\n\t\"1841 (BC_2, *, internal, X),\" & --  PAD462.O\n\t\"1842 (BC_2, *, internal, X),\" & --  PAD462.I\n\t\"1843 (BC_2, *, internal, 1),\" & --  PAD461.T\n\t\"1844 (BC_2, *, internal, X),\" & --  PAD461.O\n\t\"1845 (BC_2, *, internal, X),\" & --  PAD461.I\n\t\"1846 (BC_2, *, internal, 1),\" & --  PAD460.T\n\t\"1847 (BC_2, *, internal, X),\" & --  PAD460.O\n\t\"1848 (BC_2, *, internal, X),\" & --  PAD460.I\n\t\"1849 (BC_2, *, internal, 1),\" & --  PAD459.T\n\t\"1850 (BC_2, *, internal, X),\" & --  PAD459.O\n\t\"1851 (BC_2, *, internal, X),\" & --  PAD459.I\n\t\"1852 (BC_2, *, internal, 1),\" & --  PAD458.T\n\t\"1853 (BC_2, *, internal, X),\" & --  PAD458.O\n\t\"1854 (BC_2, *, internal, X),\" & --  PAD458.I\n\t\"1855 (BC_2, *, internal, 1),\" & --  PAD457.T\n\t\"1856 (BC_2, *, internal, X),\" & --  PAD457.O\n\t\"1857 (BC_2, *, internal, X),\" & --  PAD457.I\n\t\"1858 (BC_2, *, internal, 1),\" & --  PAD456.T\n\t\"1859 (BC_2, *, internal, X),\" & --  PAD456.O\n\t\"1860 (BC_2, *, internal, X),\" & --  PAD456.I\n\t\"1861 (BC_2, *, internal, 1),\" & --  PAD455.T\n\t\"1862 (BC_2, *, internal, X),\" & --  PAD455.O\n\t\"1863 (BC_2, *, internal, X),\" & --  PAD455.I\n\t\"1864 (BC_2, *, internal, 1),\" & --  PAD454.T\n\t\"1865 (BC_2, *, internal, X),\" & --  PAD454.O\n\t\"1866 (BC_2, *, internal, X),\" & --  PAD454.I\n\t\"1867 (BC_2, *, internal, 1),\" & --  PAD453.T\n\t\"1868 (BC_2, *, internal, X),\" & --  PAD453.O\n\t\"1869 (BC_2, *, internal, X),\" & --  PAD453.I\n\t\"1870 (BC_2, *, internal, 1),\" & --  PAD452.T\n\t\"1871 (BC_2, *, internal, X),\" & --  PAD452.O\n\t\"1872 (BC_2, *, internal, X),\" & --  PAD452.I\n\t\"1873 (BC_2, *, internal, 1),\" & --  PAD451.T\n\t\"1874 (BC_2, *, internal, X),\" & --  PAD451.O\n\t\"1875 (BC_2, *, internal, X),\" & --  PAD451.I\n\t\"1876 (BC_2, *, internal, 1),\" & --  PAD450.T\n\t\"1877 (BC_2, *, internal, X),\" & --  PAD450.O\n\t\"1878 (BC_2, *, internal, X),\" & --  PAD450.I\n\t\"1879 (BC_2, *, internal, 1),\" & --  PAD449.T\n\t\"1880 (BC_2, *, internal, X),\" & --  PAD449.O\n\t\"1881 (BC_2, *, internal, X),\" & --  PAD449.I\n\t\"1882 (BC_2, *, internal, 1),\" & --  PAD448.T\n\t\"1883 (BC_2, *, internal, X),\" & --  PAD448.O\n\t\"1884 (BC_2, *, internal, X),\" & --  PAD448.I\n\t\"1885 (BC_2, *, internal, 1),\" & --  PAD447.T\n\t\"1886 (BC_2, *, internal, X),\" & --  PAD447.O\n\t\"1887 (BC_2, *, internal, X),\" & --  PAD447.I\n\t\"1888 (BC_2, *, internal, 1),\" & --  PAD446.T\n\t\"1889 (BC_2, *, internal, X),\" & --  PAD446.O\n\t\"1890 (BC_2, *, internal, X),\" & --  PAD446.I\n\t\"1891 (BC_2, *, internal, 1),\" & --  PAD445.T\n\t\"1892 (BC_2, *, internal, X),\" & --  PAD445.O\n\t\"1893 (BC_2, *, internal, X),\" & --  PAD445.I\n\t\"1894 (BC_2, *, internal, 1),\" & --  PAD444.T\n\t\"1895 (BC_2, *, internal, X),\" & --  PAD444.O\n\t\"1896 (BC_2, *, internal, X),\" & --  PAD444.I\n\t\"1897 (BC_2, *, internal, 1),\" & --  PAD443.T\n\t\"1898 (BC_2, *, internal, X),\" & --  PAD443.O\n\t\"1899 (BC_2, *, internal, X),\" & --  PAD443.I\n\t\"1900 (BC_2, *, internal, 1),\" & --  PAD442.T\n\t\"1901 (BC_2, *, internal, X),\" & --  PAD442.O\n\t\"1902 (BC_2, *, internal, X),\" & --  PAD442.I\n\t\"1903 (BC_2, *, internal, 1),\" & --  PAD441.T\n\t\"1904 (BC_2, *, internal, X),\" & --  PAD441.O\n\t\"1905 (BC_2, *, internal, X),\" & --  PAD441.I\n\t\"1906 (BC_2, *, internal, 1),\" & --  PAD440.T\n\t\"1907 (BC_2, *, internal, X),\" & --  PAD440.O\n\t\"1908 (BC_2, *, internal, X),\" & --  PAD440.I\n\t\"1909 (BC_2, *, internal, 1),\" & --  PAD439.T\n\t\"1910 (BC_2, *, internal, X),\" & --  PAD439.O\n\t\"1911 (BC_2, *, internal, X),\" & --  PAD439.I\n\t\"1912 (BC_2, *, internal, 1),\" & --  PAD438.T\n\t\"1913 (BC_2, *, internal, X),\" & --  PAD438.O\n\t\"1914 (BC_2, *, internal, X),\" & --  PAD438.I\n\t\"1915 (BC_2, *, internal, 1),\" & --  PAD437.T\n\t\"1916 (BC_2, *, internal, X),\" & --  PAD437.O\n\t\"1917 (BC_2, *, internal, X),\" & --  PAD437.I\n\t\"1918 (BC_2, *, internal, 1),\" & --  PAD436.T\n\t\"1919 (BC_2, *, internal, X),\" & --  PAD436.O\n\t\"1920 (BC_2, *, internal, X),\" & --  PAD436.I\n\t\"1921 (BC_2, *, internal, 1),\" & --  PAD435.T\n\t\"1922 (BC_2, *, internal, X),\" & --  PAD435.O\n\t\"1923 (BC_2, *, internal, X),\" & --  PAD435.I\n\t\"1924 (BC_2, *, internal, 1),\" & --  PAD434.T\n\t\"1925 (BC_2, *, internal, X),\" & --  PAD434.O\n\t\"1926 (BC_2, *, internal, X),\" & --  PAD434.I\n\t\"1927 (BC_2, *, internal, 1),\" & --  PAD433.T\n\t\"1928 (BC_2, *, internal, X),\" & --  PAD433.O\n\t\"1929 (BC_2, *, internal, X),\" & --  PAD433.I\n\t\"1930 (BC_2, *, internal, 1),\" & --  PAD432.T\n\t\"1931 (BC_2, *, internal, X),\" & --  PAD432.O\n\t\"1932 (BC_2, *, internal, X),\" & --  PAD432.I\n\t\"1933 (BC_2, *, internal, 1),\" & --  PAD431.T\n\t\"1934 (BC_2, *, internal, X),\" & --  PAD431.O\n\t\"1935 (BC_2, *, internal, X),\" & --  PAD431.I\n\t\"1936 (BC_2, *, internal, 1),\" & --  PAD430.T\n\t\"1937 (BC_2, *, internal, X),\" & --  PAD430.O\n\t\"1938 (BC_2, *, internal, X),\" & --  PAD430.I\n\t\"1939 (BC_2, *, internal, 1),\" & --  PAD429.T\n\t\"1940 (BC_2, *, internal, X),\" & --  PAD429.O\n\t\"1941 (BC_2, *, internal, X),\" & --  PAD429.I\n\t\"1942 (BC_2, *, internal, 1),\" & --  PAD428.T\n\t\"1943 (BC_2, *, internal, X),\" & --  PAD428.O\n\t\"1944 (BC_2, *, internal, X),\" & --  PAD428.I\n\t\"1945 (BC_2, *, internal, 1),\" & --  PAD427.T\n\t\"1946 (BC_2, *, internal, X),\" & --  PAD427.O\n\t\"1947 (BC_2, *, internal, X),\" & --  PAD427.I\n\t\"1948 (BC_2, *, internal, 1),\" & --  PAD426.T\n\t\"1949 (BC_2, *, internal, X),\" & --  PAD426.O\n\t\"1950 (BC_2, *, internal, X),\" & --  PAD426.I\n\t\"1951 (BC_2, *, internal, 1),\" & --  PAD425.T\n\t\"1952 (BC_2, *, internal, X),\" & --  PAD425.O\n\t\"1953 (BC_2, *, internal, X),\" & --  PAD425.I\n\t\"1954 (BC_2, *, internal, 1),\" & --  PAD424.T\n\t\"1955 (BC_2, *, internal, X),\" & --  PAD424.O\n\t\"1956 (BC_2, *, internal, X),\" & --  PAD424.I\n\t\"1957 (BC_2, *, internal, 1),\" & --  PAD423.T\n\t\"1958 (BC_2, *, internal, X),\" & --  PAD423.O\n\t\"1959 (BC_2, *, internal, X),\" & --  PAD423.I\n\t\"1960 (BC_2, *, internal, 1),\" & --  PAD422.T\n\t\"1961 (BC_2, *, internal, X),\" & --  PAD422.O\n\t\"1962 (BC_2, *, internal, X),\" & --  PAD422.I\n\t\"1963 (BC_2, *, internal, 1),\" & --  PAD421.T\n\t\"1964 (BC_2, *, internal, X),\" & --  PAD421.O\n\t\"1965 (BC_2, *, internal, X),\" & --  PAD421.I\n\t\"1966 (BC_2, *, internal, 1),\" & --  PAD420.T\n\t\"1967 (BC_2, *, internal, X),\" & --  PAD420.O\n\t\"1968 (BC_2, *, internal, X),\" & --  PAD420.I\n\t\"1969 (BC_2, *, internal, 1),\" & --  PAD419.T\n\t\"1970 (BC_2, *, internal, X),\" & --  PAD419.O\n\t\"1971 (BC_2, *, internal, X),\" & --  PAD419.I\n\t\"1972 (BC_2, *, internal, 1),\" & --  PAD418.T\n\t\"1973 (BC_2, *, internal, X),\" & --  PAD418.O\n\t\"1974 (BC_2, *, internal, X),\" & --  PAD418.I\n\t\"1975 (BC_2, *, internal, 1),\" & --  PAD417.T\n\t\"1976 (BC_2, *, internal, X),\" & --  PAD417.O\n\t\"1977 (BC_2, *, internal, X),\" & --  PAD417.I\n\t\"1978 (BC_2, *, internal, 1),\" & --  PAD416.T\n\t\"1979 (BC_2, *, internal, X),\" & --  PAD416.O\n\t\"1980 (BC_2, *, internal, X),\" & --  PAD416.I\n\t\"1981 (BC_2, *, internal, 1),\" & --  PAD415.T\n\t\"1982 (BC_2, *, internal, X),\" & --  PAD415.O\n\t\"1983 (BC_2, *, internal, X),\" & --  PAD415.I\n\t\"1984 (BC_2, *, internal, 1),\" & --  PAD414.T\n\t\"1985 (BC_2, *, internal, X),\" & --  PAD414.O\n\t\"1986 (BC_2, *, internal, X),\" & --  PAD414.I\n\t\"1987 (BC_2, *, internal, 1),\" & --  PAD413.T\n\t\"1988 (BC_2, *, internal, X),\" & --  PAD413.O\n\t\"1989 (BC_2, *, internal, X),\" & --  PAD413.I\n\t\"1990 (BC_2, *, internal, 1),\" & --  PAD412.T\n\t\"1991 (BC_2, *, internal, X),\" & --  PAD412.O\n\t\"1992 (BC_2, *, internal, X),\" & --  PAD412.I\n\t\"1993 (BC_2, *, internal, 1),\" & --  PAD411.T\n\t\"1994 (BC_2, *, internal, X),\" & --  PAD411.O\n\t\"1995 (BC_2, *, internal, X),\" & --  PAD411.I\n\t\"1996 (BC_2, *, internal, 1),\" & --  PAD410.T\n\t\"1997 (BC_2, *, internal, X),\" & --  PAD410.O\n\t\"1998 (BC_2, *, internal, X),\" & --  PAD410.I\n\t\"1999 (BC_2, *, internal, 1),\" & --  PAD409.T\n\t\"2000 (BC_2, *, internal, X),\" & --  PAD409.O\n\t\"2001 (BC_2, *, internal, X),\" & --  PAD409.I\n\t\"2002 (BC_2, *, internal, 1),\" & --  PAD408.T\n\t\"2003 (BC_2, *, internal, X),\" & --  PAD408.O\n\t\"2004 (BC_2, *, internal, X),\" & --  PAD408.I\n\t\"2005 (BC_2, *, internal, 1),\" & --  PAD407.T\n\t\"2006 (BC_2, *, internal, X),\" & --  PAD407.O\n\t\"2007 (BC_2, *, internal, X),\" & --  PAD407.I\n\t\"2008 (BC_2, *, internal, 1),\" & --  PAD406.T\n\t\"2009 (BC_2, *, internal, X),\" & --  PAD406.O\n\t\"2010 (BC_2, *, internal, X),\" & --  PAD406.I\n\t\"2011 (BC_2, *, internal, 1),\" & --  PAD405.T\n\t\"2012 (BC_2, *, internal, X),\" & --  PAD405.O\n\t\"2013 (BC_2, *, internal, X),\" & --  PAD405.I\n\t\"2014 (BC_2, *, internal, 1),\" & --  PAD404.T\n\t\"2015 (BC_2, *, internal, X),\" & --  PAD404.O\n\t\"2016 (BC_2, *, internal, X),\" & --  PAD404.I\n\t\"2017 (BC_2, *, internal, 1),\" & --  PAD403.T\n\t\"2018 (BC_2, *, internal, X),\" & --  PAD403.O\n\t\"2019 (BC_2, *, internal, X),\" & --  PAD403.I\n\t\"2020 (BC_2, *, internal, 1),\" & --  PAD402.T\n\t\"2021 (BC_2, *, internal, X),\" & --  PAD402.O\n\t\"2022 (BC_2, *, internal, X),\" & --  PAD402.I\n\t\"2023 (BC_2, *, internal, 1),\" & --  PAD401.T\n\t\"2024 (BC_2, *, internal, X),\" & --  PAD401.O\n\t\"2025 (BC_2, *, internal, X),\" & --  PAD401.I\n\t\"2026 (BC_2, *, controlr, 1),\" &\n\t\"2027 (BC_2, IO_AP26, output3, X, 2026, 1, Z),\" & --  PAD400\n\t\"2028 (BC_2, IO_AP26, input, X),\" & --  PAD400\n\t\"2029 (BC_2, *, controlr, 1),\" &\n\t\"2030 (BC_2, IO_AJ26, output3, X, 2029, 1, Z),\" & --  PAD399\n\t\"2031 (BC_2, IO_AJ26, input, X),\" & --  PAD399\n\t\"2032 (BC_2, *, controlr, 1),\" &\n\t\"2033 (BC_2, IO_AJ25, output3, X, 2032, 1, Z),\" & --  PAD398\n\t\"2034 (BC_2, IO_AJ25, input, X),\" & --  PAD398\n\t\"2035 (BC_2, *, controlr, 1),\" &\n\t\"2036 (BC_2, IO_AL26, output3, X, 2035, 1, Z),\" & --  PAD397\n\t\"2037 (BC_2, IO_AL26, input, X),\" & --  PAD397\n\t\"2038 (BC_2, *, controlr, 1),\" &\n\t\"2039 (BC_2, IO_AL25, output3, X, 2038, 1, Z),\" & --  PAD396\n\t\"2040 (BC_2, IO_AL25, input, X),\" & --  PAD396\n\t\"2041 (BC_2, *, controlr, 1),\" &\n\t\"2042 (BC_2, IO_AK25, output3, X, 2041, 1, Z),\" & --  PAD395\n\t\"2043 (BC_2, IO_AK25, input, X),\" & --  PAD395\n\t\"2044 (BC_2, *, controlr, 1),\" &\n\t\"2045 (BC_2, IO_AK24, output3, X, 2044, 1, Z),\" & --  PAD394\n\t\"2046 (BC_2, IO_AK24, input, X),\" & --  PAD394\n\t\"2047 (BC_2, *, controlr, 1),\" &\n\t\"2048 (BC_2, IO_AM27, output3, X, 2047, 1, Z),\" & --  PAD393\n\t\"2049 (BC_2, IO_AM27, input, X),\" & --  PAD393\n\t\"2050 (BC_2, *, controlr, 1),\" &\n\t\"2051 (BC_2, IO_AM26, output3, X, 2050, 1, Z),\" & --  PAD392\n\t\"2052 (BC_2, IO_AM26, input, X),\" & --  PAD392\n\t\"2053 (BC_2, *, controlr, 1),\" &\n\t\"2054 (BC_2, IO_AL27, output3, X, 2053, 1, Z),\" & --  PAD391\n\t\"2055 (BC_2, IO_AL27, input, X),\" & --  PAD391\n\t\"2056 (BC_2, *, controlr, 1),\" &\n\t\"2057 (BC_2, IO_AK27, output3, X, 2056, 1, Z),\" & --  PAD390\n\t\"2058 (BC_2, IO_AK27, input, X),\" & --  PAD390\n\t\"2059 (BC_2, *, controlr, 1),\" &\n\t\"2060 (BC_2, IO_AM29, output3, X, 2059, 1, Z),\" & --  PAD389\n\t\"2061 (BC_2, IO_AM29, input, X),\" & --  PAD389\n\t\"2062 (BC_2, *, controlr, 1),\" &\n\t\"2063 (BC_2, IO_AM28, output3, X, 2062, 1, Z),\" & --  PAD388\n\t\"2064 (BC_2, IO_AM28, input, X),\" & --  PAD388\n\t\"2065 (BC_2, *, controlr, 1),\" &\n\t\"2066 (BC_2, IO_AN26, output3, X, 2065, 1, Z),\" & --  PAD387\n\t\"2067 (BC_2, IO_AN26, input, X),\" & --  PAD387\n\t\"2068 (BC_2, *, controlr, 1),\" &\n\t\"2069 (BC_2, IO_AN25, output3, X, 2068, 1, Z),\" & --  PAD386\n\t\"2070 (BC_2, IO_AN25, input, X),\" & --  PAD386\n\t\"2071 (BC_2, *, controlr, 1),\" &\n\t\"2072 (BC_2, IO_AR25, output3, X, 2071, 1, Z),\" & --  PAD385\n\t\"2073 (BC_2, IO_AR25, input, X),\" & --  PAD385\n\t\"2074 (BC_2, *, controlr, 1),\" &\n\t\"2075 (BC_2, IO_AP25, output3, X, 2074, 1, Z),\" & --  PAD384\n\t\"2076 (BC_2, IO_AP25, input, X),\" & --  PAD384\n\t\"2077 (BC_2, *, controlr, 1),\" &\n\t\"2078 (BC_2, IO_AT26, output3, X, 2077, 1, Z),\" & --  PAD383\n\t\"2079 (BC_2, IO_AT26, input, X),\" & --  PAD383\n\t\"2080 (BC_2, *, controlr, 1),\" &\n\t\"2081 (BC_2, IO_AT25, output3, X, 2080, 1, Z),\" & --  PAD382\n\t\"2082 (BC_2, IO_AT25, input, X),\" & --  PAD382\n\t\"2083 (BC_2, *, controlr, 1),\" &\n\t\"2084 (BC_2, IO_AP28, output3, X, 2083, 1, Z),\" & --  PAD381\n\t\"2085 (BC_2, IO_AP28, input, X),\" & --  PAD381\n\t\"2086 (BC_2, *, controlr, 1),\" &\n\t\"2087 (BC_2, IO_AN28, output3, X, 2086, 1, Z),\" & --  PAD380\n\t\"2088 (BC_2, IO_AN28, input, X),\" & --  PAD380\n\t\"2089 (BC_2, *, controlr, 1),\" &\n\t\"2090 (BC_2, IO_AR28, output3, X, 2089, 1, Z),\" & --  PAD379\n\t\"2091 (BC_2, IO_AR28, input, X),\" & --  PAD379\n\t\"2092 (BC_2, *, controlr, 1),\" &\n\t\"2093 (BC_2, IO_AP27, output3, X, 2092, 1, Z),\" & --  PAD378\n\t\"2094 (BC_2, IO_AP27, input, X),\" & --  PAD378\n\t\"2095 (BC_2, *, controlr, 1),\" &\n\t\"2096 (BC_2, IO_AT27, output3, X, 2095, 1, Z),\" & --  PAD377\n\t\"2097 (BC_2, IO_AT27, input, X),\" & --  PAD377\n\t\"2098 (BC_2, *, controlr, 1),\" &\n\t\"2099 (BC_2, IO_AR27, output3, X, 2098, 1, Z),\" & --  PAD376\n\t\"2100 (BC_2, IO_AR27, input, X),\" & --  PAD376\n\t\"2101 (BC_2, *, controlr, 1),\" &\n\t\"2102 (BC_2, IO_AU27, output3, X, 2101, 1, Z),\" & --  PAD375\n\t\"2103 (BC_2, IO_AU27, input, X),\" & --  PAD375\n\t\"2104 (BC_2, *, controlr, 1),\" &\n\t\"2105 (BC_2, IO_AU26, output3, X, 2104, 1, Z),\" & --  PAD374\n\t\"2106 (BC_2, IO_AU26, input, X),\" & --  PAD374\n\t\"2107 (BC_2, *, controlr, 1),\" &\n\t\"2108 (BC_2, IO_AV28, output3, X, 2107, 1, Z),\" & --  PAD373\n\t\"2109 (BC_2, IO_AV28, input, X),\" & --  PAD373\n\t\"2110 (BC_2, *, controlr, 1),\" &\n\t\"2111 (BC_2, IO_AU28, output3, X, 2110, 1, Z),\" & --  PAD372\n\t\"2112 (BC_2, IO_AU28, input, X),\" & --  PAD372\n\t\"2113 (BC_2, *, controlr, 1),\" &\n\t\"2114 (BC_2, IO_AW28, output3, X, 2113, 1, Z),\" & --  PAD371\n\t\"2115 (BC_2, IO_AW28, input, X),\" & --  PAD371\n\t\"2116 (BC_2, *, controlr, 1),\" &\n\t\"2117 (BC_2, IO_AW27, output3, X, 2116, 1, Z),\" & --  PAD370\n\t\"2118 (BC_2, IO_AW27, input, X),\" & --  PAD370\n\t\"2119 (BC_2, *, controlr, 1),\" &\n\t\"2120 (BC_2, IO_AV26, output3, X, 2119, 1, Z),\" & --  PAD369\n\t\"2121 (BC_2, IO_AV26, input, X),\" & --  PAD369\n\t\"2122 (BC_2, *, controlr, 1),\" &\n\t\"2123 (BC_2, IO_AV25, output3, X, 2122, 1, Z),\" & --  PAD368\n\t\"2124 (BC_2, IO_AV25, input, X),\" & --  PAD368\n\t\"2125 (BC_2, *, controlr, 1),\" &\n\t\"2126 (BC_2, IO_AT29, output3, X, 2125, 1, Z),\" & --  PAD367\n\t\"2127 (BC_2, IO_AT29, input, X),\" & --  PAD367\n\t\"2128 (BC_2, *, controlr, 1),\" &\n\t\"2129 (BC_2, IO_AR29, output3, X, 2128, 1, Z),\" & --  PAD366\n\t\"2130 (BC_2, IO_AR29, input, X),\" & --  PAD366\n\t\"2131 (BC_2, *, controlr, 1),\" &\n\t\"2132 (BC_2, IO_AW26, output3, X, 2131, 1, Z),\" & --  PAD365\n\t\"2133 (BC_2, IO_AW26, input, X),\" & --  PAD365\n\t\"2134 (BC_2, *, controlr, 1),\" &\n\t\"2135 (BC_2, IO_AW25, output3, X, 2134, 1, Z),\" & --  PAD364\n\t\"2136 (BC_2, IO_AW25, input, X),\" & --  PAD364\n\t\"2137 (BC_2, *, controlr, 1),\" &\n\t\"2138 (BC_2, IO_BA29, output3, X, 2137, 1, Z),\" & --  PAD363\n\t\"2139 (BC_2, IO_BA29, input, X),\" & --  PAD363\n\t\"2140 (BC_2, *, controlr, 1),\" &\n\t\"2141 (BC_2, IO_AY29, output3, X, 2140, 1, Z),\" & --  PAD362\n\t\"2142 (BC_2, IO_AY29, input, X),\" & --  PAD362\n\t\"2143 (BC_2, *, controlr, 1),\" &\n\t\"2144 (BC_2, IO_BB27, output3, X, 2143, 1, Z),\" & --  PAD361\n\t\"2145 (BC_2, IO_BB27, input, X),\" & --  PAD361\n\t\"2146 (BC_2, *, controlr, 1),\" &\n\t\"2147 (BC_2, IO_BB26, output3, X, 2146, 1, Z),\" & --  PAD360\n\t\"2148 (BC_2, IO_BB26, input, X),\" & --  PAD360\n\t\"2149 (BC_2, *, controlr, 1),\" &\n\t\"2150 (BC_2, IO_BB29, output3, X, 2149, 1, Z),\" & --  PAD359\n\t\"2151 (BC_2, IO_BB29, input, X),\" & --  PAD359\n\t\"2152 (BC_2, *, controlr, 1),\" &\n\t\"2153 (BC_2, IO_BB28, output3, X, 2152, 1, Z),\" & --  PAD358\n\t\"2154 (BC_2, IO_BB28, input, X),\" & --  PAD358\n\t\"2155 (BC_2, *, controlr, 1),\" &\n\t\"2156 (BC_2, IO_BA27, output3, X, 2155, 1, Z),\" & --  PAD357\n\t\"2157 (BC_2, IO_BA27, input, X),\" & --  PAD357\n\t\"2158 (BC_2, *, controlr, 1),\" &\n\t\"2159 (BC_2, IO_BA26, output3, X, 2158, 1, Z),\" & --  PAD356\n\t\"2160 (BC_2, IO_BA26, input, X),\" & --  PAD356\n\t\"2161 (BC_2, *, controlr, 1),\" &\n\t\"2162 (BC_2, IO_AV29, output3, X, 2161, 1, Z),\" & --  PAD355\n\t\"2163 (BC_2, IO_AV29, input, X),\" & --  PAD355\n\t\"2164 (BC_2, *, controlr, 1),\" &\n\t\"2165 (BC_2, IO_AU29, output3, X, 2164, 1, Z),\" & --  PAD354\n\t\"2166 (BC_2, IO_AU29, input, X),\" & --  PAD354\n\t\"2167 (BC_2, *, controlr, 1),\" &\n\t\"2168 (BC_2, IO_AY28, output3, X, 2167, 1, Z),\" & --  PAD353\n\t\"2169 (BC_2, IO_AY28, input, X),\" & --  PAD353\n\t\"2170 (BC_2, *, controlr, 1),\" &\n\t\"2171 (BC_2, IO_AY27, output3, X, 2170, 1, Z),\" & --  PAD352\n\t\"2172 (BC_2, IO_AY27, input, X),\" & --  PAD352\n\t\"2173 (BC_2, *, controlr, 1),\" &\n\t\"2174 (BC_2, IO_AN29, output3, X, 2173, 1, Z),\" & --  PAD351\n\t\"2175 (BC_2, IO_AN29, input, X),\" & --  PAD351\n\t\"2176 (BC_2, *, controlr, 1),\" &\n\t\"2177 (BC_2, IO_AT31, output3, X, 2176, 1, Z),\" & --  PAD350\n\t\"2178 (BC_2, IO_AT31, input, X),\" & --  PAD350\n\t\"2179 (BC_2, *, controlr, 1),\" &\n\t\"2180 (BC_2, IO_AR33, output3, X, 2179, 1, Z),\" & --  PAD349\n\t\"2181 (BC_2, IO_AR33, input, X),\" & --  PAD349\n\t\"2182 (BC_2, *, controlr, 1),\" &\n\t\"2183 (BC_2, IO_AP33, output3, X, 2182, 1, Z),\" & --  PAD348\n\t\"2184 (BC_2, IO_AP33, input, X),\" & --  PAD348\n\t\"2185 (BC_2, *, controlr, 1),\" &\n\t\"2186 (BC_2, IO_AP31, output3, X, 2185, 1, Z),\" & --  PAD347\n\t\"2187 (BC_2, IO_AP31, input, X),\" & --  PAD347\n\t\"2188 (BC_2, *, controlr, 1),\" &\n\t\"2189 (BC_2, IO_AN31, output3, X, 2188, 1, Z),\" & --  PAD346\n\t\"2190 (BC_2, IO_AN31, input, X),\" & --  PAD346\n\t\"2191 (BC_2, *, controlr, 1),\" &\n\t\"2192 (BC_2, IO_AR32, output3, X, 2191, 1, Z),\" & --  PAD345\n\t\"2193 (BC_2, IO_AR32, input, X),\" & --  PAD345\n\t\"2194 (BC_2, *, controlr, 1),\" &\n\t\"2195 (BC_2, IO_AP32, output3, X, 2194, 1, Z),\" & --  PAD344\n\t\"2196 (BC_2, IO_AP32, input, X),\" & --  PAD344\n\t\"2197 (BC_2, *, controlr, 1),\" &\n\t\"2198 (BC_2, IO_AP30, output3, X, 2197, 1, Z),\" & --  PAD343\n\t\"2199 (BC_2, IO_AP30, input, X),\" & --  PAD343\n\t\"2200 (BC_2, *, controlr, 1),\" &\n\t\"2201 (BC_2, IO_AN30, output3, X, 2200, 1, Z),\" & --  PAD342\n\t\"2202 (BC_2, IO_AN30, input, X),\" & --  PAD342\n\t\"2203 (BC_2, *, controlr, 1),\" &\n\t\"2204 (BC_2, IO_AV31, output3, X, 2203, 1, Z),\" & --  PAD341\n\t\"2205 (BC_2, IO_AV31, input, X),\" & --  PAD341\n\t\"2206 (BC_2, *, controlr, 1),\" &\n\t\"2207 (BC_2, IO_AU31, output3, X, 2206, 1, Z),\" & --  PAD340\n\t\"2208 (BC_2, IO_AU31, input, X),\" & --  PAD340\n\t\"2209 (BC_2, *, controlr, 1),\" &\n\t\"2210 (BC_2, IO_AT30, output3, X, 2209, 1, Z),\" & --  PAD339\n\t\"2211 (BC_2, IO_AT30, input, X),\" & --  PAD339\n\t\"2212 (BC_2, *, controlr, 1),\" &\n\t\"2213 (BC_2, IO_AR30, output3, X, 2212, 1, Z),\" & --  PAD338\n\t\"2214 (BC_2, IO_AR30, input, X),\" & --  PAD338\n\t\"2215 (BC_2, *, controlr, 1),\" &\n\t\"2216 (BC_2, IO_AW31, output3, X, 2215, 1, Z),\" & --  PAD337\n\t\"2217 (BC_2, IO_AW31, input, X),\" & --  PAD337\n\t\"2218 (BC_2, *, controlr, 1),\" &\n\t\"2219 (BC_2, IO_AV30, output3, X, 2218, 1, Z),\" & --  PAD336\n\t\"2220 (BC_2, IO_AV30, input, X),\" & --  PAD336\n\t\"2221 (BC_2, *, controlr, 1),\" &\n\t\"2222 (BC_2, IO_BB31, output3, X, 2221, 1, Z),\" & --  PAD335\n\t\"2223 (BC_2, IO_BB31, input, X),\" & --  PAD335\n\t\"2224 (BC_2, *, controlr, 1),\" &\n\t\"2225 (BC_2, IO_BA30, output3, X, 2224, 1, Z),\" & --  PAD334\n\t\"2226 (BC_2, IO_BA30, input, X),\" & --  PAD334\n\t\"2227 (BC_2, *, controlr, 1),\" &\n\t\"2228 (BC_2, IO_AY30, output3, X, 2227, 1, Z),\" & --  PAD333\n\t\"2229 (BC_2, IO_AY30, input, X),\" & --  PAD333\n\t\"2230 (BC_2, *, controlr, 1),\" &\n\t\"2231 (BC_2, IO_AW30, output3, X, 2230, 1, Z),\" & --  PAD332\n\t\"2232 (BC_2, IO_AW30, input, X),\" & --  PAD332\n\t\"2233 (BC_2, *, controlr, 1),\" &\n\t\"2234 (BC_2, IO_BA32, output3, X, 2233, 1, Z),\" & --  PAD331\n\t\"2235 (BC_2, IO_BA32, input, X),\" & --  PAD331\n\t\"2236 (BC_2, *, controlr, 1),\" &\n\t\"2237 (BC_2, IO_BA31, output3, X, 2236, 1, Z),\" & --  PAD330\n\t\"2238 (BC_2, IO_BA31, input, X),\" & --  PAD330\n\t\"2239 (BC_2, *, controlr, 1),\" &\n\t\"2240 (BC_2, IO_AY33, output3, X, 2239, 1, Z),\" & --  PAD329\n\t\"2241 (BC_2, IO_AY33, input, X),\" & --  PAD329\n\t\"2242 (BC_2, *, controlr, 1),\" &\n\t\"2243 (BC_2, IO_AY32, output3, X, 2242, 1, Z),\" & --  PAD328\n\t\"2244 (BC_2, IO_AY32, input, X),\" & --  PAD328\n\t\"2245 (BC_2, *, controlr, 1),\" &\n\t\"2246 (BC_2, IO_AV35, output3, X, 2245, 1, Z),\" & --  PAD327\n\t\"2247 (BC_2, IO_AV35, input, X),\" & --  PAD327\n\t\"2248 (BC_2, *, controlr, 1),\" &\n\t\"2249 (BC_2, IO_AV34, output3, X, 2248, 1, Z),\" & --  PAD326\n\t\"2250 (BC_2, IO_AV34, input, X),\" & --  PAD326\n\t\"2251 (BC_2, *, controlr, 1),\" &\n\t\"2252 (BC_2, IO_AW33, output3, X, 2251, 1, Z),\" & --  PAD325\n\t\"2253 (BC_2, IO_AW33, input, X),\" & --  PAD325\n\t\"2254 (BC_2, *, controlr, 1),\" &\n\t\"2255 (BC_2, IO_AW32, output3, X, 2254, 1, Z),\" & --  PAD324\n\t\"2256 (BC_2, IO_AW32, input, X),\" & --  PAD324\n\t\"2257 (BC_2, *, controlr, 1),\" &\n\t\"2258 (BC_2, IO_AV33, output3, X, 2257, 1, Z),\" & --  PAD323\n\t\"2259 (BC_2, IO_AV33, input, X),\" & --  PAD323\n\t\"2260 (BC_2, *, controlr, 1),\" &\n\t\"2261 (BC_2, IO_AU32, output3, X, 2260, 1, Z),\" & --  PAD322\n\t\"2262 (BC_2, IO_AU32, input, X),\" & --  PAD322\n\t\"2263 (BC_2, *, controlr, 1),\" &\n\t\"2264 (BC_2, IO_AT35, output3, X, 2263, 1, Z),\" & --  PAD321\n\t\"2265 (BC_2, IO_AT35, input, X),\" & --  PAD321\n\t\"2266 (BC_2, *, controlr, 1),\" &\n\t\"2267 (BC_2, IO_AR34, output3, X, 2266, 1, Z),\" & --  PAD320\n\t\"2268 (BC_2, IO_AR34, input, X),\" & --  PAD320\n\t\"2269 (BC_2, *, controlr, 1),\" &\n\t\"2270 (BC_2, IO_AU33, output3, X, 2269, 1, Z),\" & --  PAD319\n\t\"2271 (BC_2, IO_AU33, input, X),\" & --  PAD319\n\t\"2272 (BC_2, *, controlr, 1),\" &\n\t\"2273 (BC_2, IO_AT32, output3, X, 2272, 1, Z),\" & --  PAD318\n\t\"2274 (BC_2, IO_AT32, input, X),\" & --  PAD318\n\t\"2275 (BC_2, *, controlr, 1),\" &\n\t\"2276 (BC_2, IO_AU36, output3, X, 2275, 1, Z),\" & --  PAD317\n\t\"2277 (BC_2, IO_AU36, input, X),\" & --  PAD317\n\t\"2278 (BC_2, *, controlr, 1),\" &\n\t\"2279 (BC_2, IO_AT36, output3, X, 2278, 1, Z),\" & --  PAD316\n\t\"2280 (BC_2, IO_AT36, input, X),\" & --  PAD316\n\t\"2281 (BC_2, *, controlr, 1),\" &\n\t\"2282 (BC_2, IO_AU34, output3, X, 2281, 1, Z),\" & --  PAD315\n\t\"2283 (BC_2, IO_AU34, input, X),\" & --  PAD315\n\t\"2284 (BC_2, *, controlr, 1),\" &\n\t\"2285 (BC_2, IO_AT34, output3, X, 2284, 1, Z),\" & --  PAD314\n\t\"2286 (BC_2, IO_AT34, input, X),\" & --  PAD314\n\t\"2287 (BC_2, *, controlr, 1),\" &\n\t\"2288 (BC_2, IO_AY35, output3, X, 2287, 1, Z),\" & --  PAD313\n\t\"2289 (BC_2, IO_AY35, input, X),\" & --  PAD313\n\t\"2290 (BC_2, *, controlr, 1),\" &\n\t\"2291 (BC_2, IO_AW35, output3, X, 2290, 1, Z),\" & --  PAD312\n\t\"2292 (BC_2, IO_AW35, input, X),\" & --  PAD312\n\t\"2293 (BC_2, *, controlr, 1),\" &\n\t\"2294 (BC_2, IO_BB33, output3, X, 2293, 1, Z),\" & --  PAD311\n\t\"2295 (BC_2, IO_BB33, input, X),\" & --  PAD311\n\t\"2296 (BC_2, *, controlr, 1),\" &\n\t\"2297 (BC_2, IO_BB32, output3, X, 2296, 1, Z),\" & --  PAD310\n\t\"2298 (BC_2, IO_BB32, input, X),\" & --  PAD310\n\t\"2299 (BC_2, *, controlr, 1),\" &\n\t\"2300 (BC_2, IO_BB36, output3, X, 2299, 1, Z),\" & --  PAD309\n\t\"2301 (BC_2, IO_BB36, input, X),\" & --  PAD309\n\t\"2302 (BC_2, *, controlr, 1),\" &\n\t\"2303 (BC_2, IO_BA36, output3, X, 2302, 1, Z),\" & --  PAD308\n\t\"2304 (BC_2, IO_BA36, input, X),\" & --  PAD308\n\t\"2305 (BC_2, *, controlr, 1),\" &\n\t\"2306 (BC_2, IO_BB34, output3, X, 2305, 1, Z),\" & --  PAD307\n\t\"2307 (BC_2, IO_BB34, input, X),\" & --  PAD307\n\t\"2308 (BC_2, *, controlr, 1),\" &\n\t\"2309 (BC_2, IO_BA34, output3, X, 2308, 1, Z),\" & --  PAD306\n\t\"2310 (BC_2, IO_BA34, input, X),\" & --  PAD306\n\t\"2311 (BC_2, *, controlr, 1),\" &\n\t\"2312 (BC_2, IO_AW36, output3, X, 2311, 1, Z),\" & --  PAD305\n\t\"2313 (BC_2, IO_AW36, input, X),\" & --  PAD305\n\t\"2314 (BC_2, *, controlr, 1),\" &\n\t\"2315 (BC_2, IO_AV36, output3, X, 2314, 1, Z),\" & --  PAD304\n\t\"2316 (BC_2, IO_AV36, input, X),\" & --  PAD304\n\t\"2317 (BC_2, *, controlr, 1),\" &\n\t\"2318 (BC_2, IO_BA35, output3, X, 2317, 1, Z),\" & --  PAD303\n\t\"2319 (BC_2, IO_BA35, input, X),\" & --  PAD303\n\t\"2320 (BC_2, *, controlr, 1),\" &\n\t\"2321 (BC_2, IO_AY34, output3, X, 2320, 1, Z),\" & --  PAD302\n\t\"2322 (BC_2, IO_AY34, input, X),\" & --  PAD302\n\t\"2323 (BC_2, *, controlr, 1),\" &\n\t\"2324 (BC_2, IO_AR35, output3, X, 2323, 1, Z),\" & --  PAD301\n\t\"2325 (BC_2, IO_AR35, input, X),\" & --  PAD301\n\t\"2326 (BC_2, *, controlr, 1),\" &\n\t\"2327 (BC_2, IO_AG32, output3, X, 2326, 1, Z),\" & --  PAD300\n\t\"2328 (BC_2, IO_AG32, input, X),\" & --  PAD300\n\t\"2329 (BC_2, *, controlr, 1),\" &\n\t\"2330 (BC_2, IO_AJ28, output3, X, 2329, 1, Z),\" & --  PAD299\n\t\"2331 (BC_2, IO_AJ28, input, X),\" & --  PAD299\n\t\"2332 (BC_2, *, controlr, 1),\" &\n\t\"2333 (BC_2, IO_AH28, output3, X, 2332, 1, Z),\" & --  PAD298\n\t\"2334 (BC_2, IO_AH28, input, X),\" & --  PAD298\n\t\"2335 (BC_2, *, controlr, 1),\" &\n\t\"2336 (BC_2, IO_AG31, output3, X, 2335, 1, Z),\" & --  PAD297\n\t\"2337 (BC_2, IO_AG31, input, X),\" & --  PAD297\n\t\"2338 (BC_2, *, controlr, 1),\" &\n\t\"2339 (BC_2, IO_AF30, output3, X, 2338, 1, Z),\" & --  PAD296\n\t\"2340 (BC_2, IO_AF30, input, X),\" & --  PAD296\n\t\"2341 (BC_2, *, controlr, 1),\" &\n\t\"2342 (BC_2, IO_AK29, output3, X, 2341, 1, Z),\" & --  PAD295\n\t\"2343 (BC_2, IO_AK29, input, X),\" & --  PAD295\n\t\"2344 (BC_2, *, controlr, 1),\" &\n\t\"2345 (BC_2, IO_AK28, output3, X, 2344, 1, Z),\" & --  PAD294\n\t\"2346 (BC_2, IO_AK28, input, X),\" & --  PAD294\n\t\"2347 (BC_2, *, controlr, 1),\" &\n\t\"2348 (BC_2, IO_AG29, output3, X, 2347, 1, Z),\" & --  PAD293\n\t\"2349 (BC_2, IO_AG29, input, X),\" & --  PAD293\n\t\"2350 (BC_2, *, controlr, 1),\" &\n\t\"2351 (BC_2, IO_AF29, output3, X, 2350, 1, Z),\" & --  PAD292\n\t\"2352 (BC_2, IO_AF29, input, X),\" & --  PAD292\n\t\"2353 (BC_2, *, controlr, 1),\" &\n\t\"2354 (BC_2, IO_AK30, output3, X, 2353, 1, Z),\" & --  PAD291\n\t\"2355 (BC_2, IO_AK30, input, X),\" & --  PAD291\n\t\"2356 (BC_2, *, controlr, 1),\" &\n\t\"2357 (BC_2, IO_AJ30, output3, X, 2356, 1, Z),\" & --  PAD290\n\t\"2358 (BC_2, IO_AJ30, input, X),\" & --  PAD290\n\t\"2359 (BC_2, *, controlr, 1),\" &\n\t\"2360 (BC_2, IO_AH30, output3, X, 2359, 1, Z),\" & --  PAD289\n\t\"2361 (BC_2, IO_AH30, input, X),\" & --  PAD289\n\t\"2362 (BC_2, *, controlr, 1),\" &\n\t\"2363 (BC_2, IO_AH29, output3, X, 2362, 1, Z),\" & --  PAD288\n\t\"2364 (BC_2, IO_AH29, input, X),\" & --  PAD288\n\t\"2365 (BC_2, *, controlr, 1),\" &\n\t\"2366 (BC_2, IO_AL30, output3, X, 2365, 1, Z),\" & --  PAD287\n\t\"2367 (BC_2, IO_AL30, input, X),\" & --  PAD287\n\t\"2368 (BC_2, *, controlr, 1),\" &\n\t\"2369 (BC_2, IO_AL29, output3, X, 2368, 1, Z),\" & --  PAD286\n\t\"2370 (BC_2, IO_AL29, input, X),\" & --  PAD286\n\t\"2371 (BC_2, *, controlr, 1),\" &\n\t\"2372 (BC_2, IO_AN33, output3, X, 2371, 1, Z),\" & --  PAD285\n\t\"2373 (BC_2, IO_AN33, input, X),\" & --  PAD285\n\t\"2374 (BC_2, *, controlr, 1),\" &\n\t\"2375 (BC_2, IO_AM33, output3, X, 2374, 1, Z),\" & --  PAD284\n\t\"2376 (BC_2, IO_AM33, input, X),\" & --  PAD284\n\t\"2377 (BC_2, *, controlr, 1),\" &\n\t\"2378 (BC_2, IO_AM32, output3, X, 2377, 1, Z),\" & --  PAD283\n\t\"2379 (BC_2, IO_AM32, input, X),\" & --  PAD283\n\t\"2380 (BC_2, *, controlr, 1),\" &\n\t\"2381 (BC_2, IO_AM31, output3, X, 2380, 1, Z),\" & --  PAD282\n\t\"2382 (BC_2, IO_AM31, input, X),\" & --  PAD282\n\t\"2383 (BC_2, *, controlr, 1),\" &\n\t\"2384 (BC_2, IO_AN34, output3, X, 2383, 1, Z),\" & --  PAD281\n\t\"2385 (BC_2, IO_AN34, input, X),\" & --  PAD281\n\t\"2386 (BC_2, *, controlr, 1),\" &\n\t\"2387 (BC_2, IO_AM34, output3, X, 2386, 1, Z),\" & --  PAD280\n\t\"2388 (BC_2, IO_AM34, input, X),\" & --  PAD280\n\t\"2389 (BC_2, *, controlr, 1),\" &\n\t\"2390 (BC_2, IO_AL32, output3, X, 2389, 1, Z),\" & --  PAD279\n\t\"2391 (BC_2, IO_AL32, input, X),\" & --  PAD279\n\t\"2392 (BC_2, *, controlr, 1),\" &\n\t\"2393 (BC_2, IO_AL31, output3, X, 2392, 1, Z),\" & --  PAD278\n\t\"2394 (BC_2, IO_AL31, input, X),\" & --  PAD278\n\t\"2395 (BC_2, *, controlr, 1),\" &\n\t\"2396 (BC_2, IO_AK32, output3, X, 2395, 1, Z),\" & --  PAD277\n\t\"2397 (BC_2, IO_AK32, input, X),\" & --  PAD277\n\t\"2398 (BC_2, *, controlr, 1),\" &\n\t\"2399 (BC_2, IO_AJ32, output3, X, 2398, 1, Z),\" & --  PAD276\n\t\"2400 (BC_2, IO_AJ32, input, X),\" & --  PAD276\n\t\"2401 (BC_2, *, controlr, 1),\" &\n\t\"2402 (BC_2, IO_AL34, output3, X, 2401, 1, Z),\" & --  PAD275\n\t\"2403 (BC_2, IO_AL34, input, X),\" & --  PAD275\n\t\"2404 (BC_2, *, controlr, 1),\" &\n\t\"2405 (BC_2, IO_AK34, output3, X, 2404, 1, Z),\" & --  PAD274\n\t\"2406 (BC_2, IO_AK34, input, X),\" & --  PAD274\n\t\"2407 (BC_2, *, controlr, 1),\" &\n\t\"2408 (BC_2, IO_AK33, output3, X, 2407, 1, Z),\" & --  PAD273\n\t\"2409 (BC_2, IO_AK33, input, X),\" & --  PAD273\n\t\"2410 (BC_2, *, controlr, 1),\" &\n\t\"2411 (BC_2, IO_AJ33, output3, X, 2410, 1, Z),\" & --  PAD272\n\t\"2412 (BC_2, IO_AJ33, input, X),\" & --  PAD272\n\t\"2413 (BC_2, *, controlr, 1),\" &\n\t\"2414 (BC_2, IO_AJ35, output3, X, 2413, 1, Z),\" & --  PAD271\n\t\"2415 (BC_2, IO_AJ35, input, X),\" & --  PAD271\n\t\"2416 (BC_2, *, controlr, 1),\" &\n\t\"2417 (BC_2, IO_AH34, output3, X, 2416, 1, Z),\" & --  PAD270\n\t\"2418 (BC_2, IO_AH34, input, X),\" & --  PAD270\n\t\"2419 (BC_2, *, controlr, 1),\" &\n\t\"2420 (BC_2, IO_AJ31, output3, X, 2419, 1, Z),\" & --  PAD269\n\t\"2421 (BC_2, IO_AJ31, input, X),\" & --  PAD269\n\t\"2422 (BC_2, *, controlr, 1),\" &\n\t\"2423 (BC_2, IO_AH31, output3, X, 2422, 1, Z),\" & --  PAD268\n\t\"2424 (BC_2, IO_AH31, input, X),\" & --  PAD268\n\t\"2425 (BC_2, *, controlr, 1),\" &\n\t\"2426 (BC_2, IO_AL35, output3, X, 2425, 1, Z),\" & --  PAD267\n\t\"2427 (BC_2, IO_AL35, input, X),\" & --  PAD267\n\t\"2428 (BC_2, *, controlr, 1),\" &\n\t\"2429 (BC_2, IO_AK35, output3, X, 2428, 1, Z),\" & --  PAD266\n\t\"2430 (BC_2, IO_AK35, input, X),\" & --  PAD266\n\t\"2431 (BC_2, *, controlr, 1),\" &\n\t\"2432 (BC_2, IO_AH33, output3, X, 2431, 1, Z),\" & --  PAD265\n\t\"2433 (BC_2, IO_AH33, input, X),\" & --  PAD265\n\t\"2434 (BC_2, *, controlr, 1),\" &\n\t\"2435 (BC_2, IO_AG33, output3, X, 2434, 1, Z),\" & --  PAD264\n\t\"2436 (BC_2, IO_AG33, input, X),\" & --  PAD264\n\t\"2437 (BC_2, *, controlr, 1),\" &\n\t\"2438 (BC_2, IO_AM37, output3, X, 2437, 1, Z),\" & --  PAD263\n\t\"2439 (BC_2, IO_AM37, input, X),\" & --  PAD263\n\t\"2440 (BC_2, *, controlr, 1),\" &\n\t\"2441 (BC_2, IO_AL36, output3, X, 2440, 1, Z),\" & --  PAD262\n\t\"2442 (BC_2, IO_AL36, input, X),\" & --  PAD262\n\t\"2443 (BC_2, *, controlr, 1),\" &\n\t\"2444 (BC_2, IO_AP35, output3, X, 2443, 1, Z),\" & --  PAD261\n\t\"2445 (BC_2, IO_AP35, input, X),\" & --  PAD261\n\t\"2446 (BC_2, *, controlr, 1),\" &\n\t\"2447 (BC_2, IO_AN35, output3, X, 2446, 1, Z),\" & --  PAD260\n\t\"2448 (BC_2, IO_AN35, input, X),\" & --  PAD260\n\t\"2449 (BC_2, *, controlr, 1),\" &\n\t\"2450 (BC_2, IO_AL37, output3, X, 2449, 1, Z),\" & --  PAD259\n\t\"2451 (BC_2, IO_AL37, input, X),\" & --  PAD259\n\t\"2452 (BC_2, *, controlr, 1),\" &\n\t\"2453 (BC_2, IO_AK37, output3, X, 2452, 1, Z),\" & --  PAD258\n\t\"2454 (BC_2, IO_AK37, input, X),\" & --  PAD258\n\t\"2455 (BC_2, *, controlr, 1),\" &\n\t\"2456 (BC_2, IO_AP37, output3, X, 2455, 1, Z),\" & --  PAD257\n\t\"2457 (BC_2, IO_AP37, input, X),\" & --  PAD257\n\t\"2458 (BC_2, *, controlr, 1),\" &\n\t\"2459 (BC_2, IO_AP36, output3, X, 2458, 1, Z),\" & --  PAD256\n\t\"2460 (BC_2, IO_AP36, input, X),\" & --  PAD256\n\t\"2461 (BC_2, *, controlr, 1),\" &\n\t\"2462 (BC_2, IO_AJ37, output3, X, 2461, 1, Z),\" & --  PAD255\n\t\"2463 (BC_2, IO_AJ37, input, X),\" & --  PAD255\n\t\"2464 (BC_2, *, controlr, 1),\" &\n\t\"2465 (BC_2, IO_AJ36, output3, X, 2464, 1, Z),\" & --  PAD254\n\t\"2466 (BC_2, IO_AJ36, input, X),\" & --  PAD254\n\t\"2467 (BC_2, *, controlr, 1),\" &\n\t\"2468 (BC_2, IO_AN36, output3, X, 2467, 1, Z),\" & --  PAD253\n\t\"2469 (BC_2, IO_AN36, input, X),\" & --  PAD253\n\t\"2470 (BC_2, *, controlr, 1),\" &\n\t\"2471 (BC_2, IO_AM36, output3, X, 2470, 1, Z),\" & --  PAD252\n\t\"2472 (BC_2, IO_AM36, input, X),\" & --  PAD252\n\t\"2473 (BC_2, *, controlr, 1),\" &\n\t\"2474 (BC_2, IO_AH35, output3, X, 2473, 1, Z),\" & --  PAD251\n\t\"2475 (BC_2, IO_AH35, input, X),\" & --  PAD251\n\t\"2476 (BC_2, *, controlr, 1),\" &\n\t\"2477 (BC_2, IO_AU37, output3, X, 2476, 1, Z),\" & --  PAD250\n\t\"2478 (BC_2, IO_AU37, input, X),\" & --  PAD250\n\t\"2479 (BC_2, *, controlr, 1),\" &\n\t\"2480 (BC_2, IO_AW42, output3, X, 2479, 1, Z),\" & --  PAD249\n\t\"2481 (BC_2, IO_AW42, input, X),\" & --  PAD249\n\t\"2482 (BC_2, *, controlr, 1),\" &\n\t\"2483 (BC_2, IO_AW41, output3, X, 2482, 1, Z),\" & --  PAD248\n\t\"2484 (BC_2, IO_AW41, input, X),\" & --  PAD248\n\t\"2485 (BC_2, *, controlr, 1),\" &\n\t\"2486 (BC_2, IO_BB41, output3, X, 2485, 1, Z),\" & --  PAD247\n\t\"2487 (BC_2, IO_BB41, input, X),\" & --  PAD247\n\t\"2488 (BC_2, *, controlr, 1),\" &\n\t\"2489 (BC_2, IO_BA41, output3, X, 2488, 1, Z),\" & --  PAD246\n\t\"2490 (BC_2, IO_BA41, input, X),\" & --  PAD246\n\t\"2491 (BC_2, *, controlr, 1),\" &\n\t\"2492 (BC_2, IO_AV41, output3, X, 2491, 1, Z),\" & --  PAD245\n\t\"2493 (BC_2, IO_AV41, input, X),\" & --  PAD245\n\t\"2494 (BC_2, *, controlr, 1),\" &\n\t\"2495 (BC_2, IO_AU41, output3, X, 2494, 1, Z),\" & --  PAD244\n\t\"2496 (BC_2, IO_AU41, input, X),\" & --  PAD244\n\t\"2497 (BC_2, *, controlr, 1),\" &\n\t\"2498 (BC_2, IO_BA42, output3, X, 2497, 1, Z),\" & --  PAD243\n\t\"2499 (BC_2, IO_BA42, input, X),\" & --  PAD243\n\t\"2500 (BC_2, *, controlr, 1),\" &\n\t\"2501 (BC_2, IO_AY42, output3, X, 2500, 1, Z),\" & --  PAD242\n\t\"2502 (BC_2, IO_AY42, input, X),\" & --  PAD242\n\t\"2503 (BC_2, *, controlr, 1),\" &\n\t\"2504 (BC_2, IO_AU42, output3, X, 2503, 1, Z),\" & --  PAD241\n\t\"2505 (BC_2, IO_AU42, input, X),\" & --  PAD241\n\t\"2506 (BC_2, *, controlr, 1),\" &\n\t\"2507 (BC_2, IO_AT41, output3, X, 2506, 1, Z),\" & --  PAD240\n\t\"2508 (BC_2, IO_AT41, input, X),\" & --  PAD240\n\t\"2509 (BC_2, *, controlr, 1),\" &\n\t\"2510 (BC_2, IO_BA40, output3, X, 2509, 1, Z),\" & --  PAD239\n\t\"2511 (BC_2, IO_BA40, input, X),\" & --  PAD239\n\t\"2512 (BC_2, *, controlr, 1),\" &\n\t\"2513 (BC_2, IO_BA39, output3, X, 2512, 1, Z),\" & --  PAD238\n\t\"2514 (BC_2, IO_BA39, input, X),\" & --  PAD238\n\t\"2515 (BC_2, *, controlr, 1),\" &\n\t\"2516 (BC_2, IO_BB39, output3, X, 2515, 1, Z),\" & --  PAD237\n\t\"2517 (BC_2, IO_BB39, input, X),\" & --  PAD237\n\t\"2518 (BC_2, *, controlr, 1),\" &\n\t\"2519 (BC_2, IO_BB38, output3, X, 2518, 1, Z),\" & --  PAD236\n\t\"2520 (BC_2, IO_BB38, input, X),\" & --  PAD236\n\t\"2521 (BC_2, *, controlr, 1),\" &\n\t\"2522 (BC_2, IO_AY38, output3, X, 2521, 1, Z),\" & --  PAD235\n\t\"2523 (BC_2, IO_AY38, input, X),\" & --  PAD235\n\t\"2524 (BC_2, *, controlr, 1),\" &\n\t\"2525 (BC_2, IO_AW38, output3, X, 2524, 1, Z),\" & --  PAD234\n\t\"2526 (BC_2, IO_AW38, input, X),\" & --  PAD234\n\t\"2527 (BC_2, *, controlr, 1),\" &\n\t\"2528 (BC_2, IO_BB37, output3, X, 2527, 1, Z),\" & --  PAD233\n\t\"2529 (BC_2, IO_BB37, input, X),\" & --  PAD233\n\t\"2530 (BC_2, *, controlr, 1),\" &\n\t\"2531 (BC_2, IO_BA37, output3, X, 2530, 1, Z),\" & --  PAD232\n\t\"2532 (BC_2, IO_BA37, input, X),\" & --  PAD232\n\t\"2533 (BC_2, *, controlr, 1),\" &\n\t\"2534 (BC_2, IO_AY37, output3, X, 2533, 1, Z),\" & --  PAD231\n\t\"2535 (BC_2, IO_AY37, input, X),\" & --  PAD231\n\t\"2536 (BC_2, *, controlr, 1),\" &\n\t\"2537 (BC_2, IO_AW37, output3, X, 2536, 1, Z),\" & --  PAD230\n\t\"2538 (BC_2, IO_AW37, input, X),\" & --  PAD230\n\t\"2539 (BC_2, *, controlr, 1),\" &\n\t\"2540 (BC_2, IO_AY40, output3, X, 2539, 1, Z),\" & --  PAD229\n\t\"2541 (BC_2, IO_AY40, input, X),\" & --  PAD229\n\t\"2542 (BC_2, *, controlr, 1),\" &\n\t\"2543 (BC_2, IO_AY39, output3, X, 2542, 1, Z),\" & --  PAD228\n\t\"2544 (BC_2, IO_AY39, input, X),\" & --  PAD228\n\t\"2545 (BC_2, *, controlr, 1),\" &\n\t\"2546 (BC_2, IO_AW40, output3, X, 2545, 1, Z),\" & --  PAD227\n\t\"2547 (BC_2, IO_AW40, input, X),\" & --  PAD227\n\t\"2548 (BC_2, *, controlr, 1),\" &\n\t\"2549 (BC_2, IO_AV40, output3, X, 2548, 1, Z),\" & --  PAD226\n\t\"2550 (BC_2, IO_AV40, input, X),\" & --  PAD226\n\t\"2551 (BC_2, *, controlr, 1),\" &\n\t\"2552 (BC_2, IO_AV38, output3, X, 2551, 1, Z),\" & --  PAD225\n\t\"2553 (BC_2, IO_AV38, input, X),\" & --  PAD225\n\t\"2554 (BC_2, *, controlr, 1),\" &\n\t\"2555 (BC_2, IO_AU38, output3, X, 2554, 1, Z),\" & --  PAD224\n\t\"2556 (BC_2, IO_AU38, input, X),\" & --  PAD224\n\t\"2557 (BC_2, *, controlr, 1),\" &\n\t\"2558 (BC_2, IO_AV39, output3, X, 2557, 1, Z),\" & --  PAD223\n\t\"2559 (BC_2, IO_AV39, input, X),\" & --  PAD223\n\t\"2560 (BC_2, *, controlr, 1),\" &\n\t\"2561 (BC_2, IO_AU39, output3, X, 2560, 1, Z),\" & --  PAD222\n\t\"2562 (BC_2, IO_AU39, input, X),\" & --  PAD222\n\t\"2563 (BC_2, *, controlr, 1),\" &\n\t\"2564 (BC_2, IO_AT42, output3, X, 2563, 1, Z),\" & --  PAD221\n\t\"2565 (BC_2, IO_AT42, input, X),\" & --  PAD221\n\t\"2566 (BC_2, *, controlr, 1),\" &\n\t\"2567 (BC_2, IO_AR42, output3, X, 2566, 1, Z),\" & --  PAD220\n\t\"2568 (BC_2, IO_AR42, input, X),\" & --  PAD220\n\t\"2569 (BC_2, *, controlr, 1),\" &\n\t\"2570 (BC_2, IO_AT40, output3, X, 2569, 1, Z),\" & --  PAD219\n\t\"2571 (BC_2, IO_AT40, input, X),\" & --  PAD219\n\t\"2572 (BC_2, *, controlr, 1),\" &\n\t\"2573 (BC_2, IO_AT39, output3, X, 2572, 1, Z),\" & --  PAD218\n\t\"2574 (BC_2, IO_AT39, input, X),\" & --  PAD218\n\t\"2575 (BC_2, *, controlr, 1),\" &\n\t\"2576 (BC_2, IO_AP42, output3, X, 2575, 1, Z),\" & --  PAD217\n\t\"2577 (BC_2, IO_AP42, input, X),\" & --  PAD217\n\t\"2578 (BC_2, *, controlr, 1),\" &\n\t\"2579 (BC_2, IO_AP41, output3, X, 2578, 1, Z),\" & --  PAD216\n\t\"2580 (BC_2, IO_AP41, input, X),\" & --  PAD216\n\t\"2581 (BC_2, *, controlr, 1),\" &\n\t\"2582 (BC_2, IO_AR40, output3, X, 2581, 1, Z),\" & --  PAD215\n\t\"2583 (BC_2, IO_AR40, input, X),\" & --  PAD215\n\t\"2584 (BC_2, *, controlr, 1),\" &\n\t\"2585 (BC_2, IO_AP40, output3, X, 2584, 1, Z),\" & --  PAD214\n\t\"2586 (BC_2, IO_AP40, input, X),\" & --  PAD214\n\t\"2587 (BC_2, *, controlr, 1),\" &\n\t\"2588 (BC_2, IO_AN39, output3, X, 2587, 1, Z),\" & --  PAD213\n\t\"2589 (BC_2, IO_AN39, input, X),\" & --  PAD213\n\t\"2590 (BC_2, *, controlr, 1),\" &\n\t\"2591 (BC_2, IO_AM39, output3, X, 2590, 1, Z),\" & --  PAD212\n\t\"2592 (BC_2, IO_AM39, input, X),\" & --  PAD212\n\t\"2593 (BC_2, *, controlr, 1),\" &\n\t\"2594 (BC_2, IO_AT37, output3, X, 2593, 1, Z),\" & --  PAD211\n\t\"2595 (BC_2, IO_AT37, input, X),\" & --  PAD211\n\t\"2596 (BC_2, *, controlr, 1),\" &\n\t\"2597 (BC_2, IO_AR37, output3, X, 2596, 1, Z),\" & --  PAD210\n\t\"2598 (BC_2, IO_AR37, input, X),\" & --  PAD210\n\t\"2599 (BC_2, *, controlr, 1),\" &\n\t\"2600 (BC_2, IO_AN41, output3, X, 2599, 1, Z),\" & --  PAD209\n\t\"2601 (BC_2, IO_AN41, input, X),\" & --  PAD209\n\t\"2602 (BC_2, *, controlr, 1),\" &\n\t\"2603 (BC_2, IO_AN40, output3, X, 2602, 1, Z),\" & --  PAD208\n\t\"2604 (BC_2, IO_AN40, input, X),\" & --  PAD208\n\t\"2605 (BC_2, *, controlr, 1),\" &\n\t\"2606 (BC_2, IO_AR39, output3, X, 2605, 1, Z),\" & --  PAD207\n\t\"2607 (BC_2, IO_AR39, input, X),\" & --  PAD207\n\t\"2608 (BC_2, *, controlr, 1),\" &\n\t\"2609 (BC_2, IO_AR38, output3, X, 2608, 1, Z),\" & --  PAD206\n\t\"2610 (BC_2, IO_AR38, input, X),\" & --  PAD206\n\t\"2611 (BC_2, *, controlr, 1),\" &\n\t\"2612 (BC_2, IO_AM42, output3, X, 2611, 1, Z),\" & --  PAD205\n\t\"2613 (BC_2, IO_AM42, input, X),\" & --  PAD205\n\t\"2614 (BC_2, *, controlr, 1),\" &\n\t\"2615 (BC_2, IO_AM41, output3, X, 2614, 1, Z),\" & --  PAD204\n\t\"2616 (BC_2, IO_AM41, input, X),\" & --  PAD204\n\t\"2617 (BC_2, *, controlr, 1),\" &\n\t\"2618 (BC_2, IO_AP38, output3, X, 2617, 1, Z),\" & --  PAD203\n\t\"2619 (BC_2, IO_AP38, input, X),\" & --  PAD203\n\t\"2620 (BC_2, *, controlr, 1),\" &\n\t\"2621 (BC_2, IO_AN38, output3, X, 2620, 1, Z),\" & --  PAD202\n\t\"2622 (BC_2, IO_AN38, input, X),\" & --  PAD202\n\t\"2623 (BC_2, *, controlr, 1),\" &\n\t\"2624 (BC_2, IO_AM38, output3, X, 2623, 1, Z),\" & --  PAD201\n\t\"2625 (BC_2, IO_AM38, input, X),\" & --  PAD201\n\t\"2626 (BC_2, *, controlr, 1),\" &\n\t\"2627 (BC_2, IO_AB34, output3, X, 2626, 1, Z),\" & --  PAD200\n\t\"2628 (BC_2, IO_AB34, input, X),\" & --  PAD200\n\t\"2629 (BC_2, *, controlr, 1),\" &\n\t\"2630 (BC_2, IO_AC29, output3, X, 2629, 1, Z),\" & --  PAD199\n\t\"2631 (BC_2, IO_AC29, input, X),\" & --  PAD199\n\t\"2632 (BC_2, *, controlr, 1),\" &\n\t\"2633 (BC_2, IO_AB29, output3, X, 2632, 1, Z),\" & --  PAD198\n\t\"2634 (BC_2, IO_AB29, input, X),\" & --  PAD198\n\t\"2635 (BC_2, *, controlr, 1),\" &\n\t\"2636 (BC_2, IO_AA30, output3, X, 2635, 1, Z),\" & --  PAD197\n\t\"2637 (BC_2, IO_AA30, input, X),\" & --  PAD197\n\t\"2638 (BC_2, *, controlr, 1),\" &\n\t\"2639 (BC_2, IO_AA29, output3, X, 2638, 1, Z),\" & --  PAD196\n\t\"2640 (BC_2, IO_AA29, input, X),\" & --  PAD196\n\t\"2641 (BC_2, *, controlr, 1),\" &\n\t\"2642 (BC_2, IO_AD30, output3, X, 2641, 1, Z),\" & --  PAD195\n\t\"2643 (BC_2, IO_AD30, input, X),\" & --  PAD195\n\t\"2644 (BC_2, *, controlr, 1),\" &\n\t\"2645 (BC_2, IO_AC30, output3, X, 2644, 1, Z),\" & --  PAD194\n\t\"2646 (BC_2, IO_AC30, input, X),\" & --  PAD194\n\t\"2647 (BC_2, *, controlr, 1),\" &\n\t\"2648 (BC_2, IO_AA32, output3, X, 2647, 1, Z),\" & --  PAD193\n\t\"2649 (BC_2, IO_AA32, input, X),\" & --  PAD193\n\t\"2650 (BC_2, *, controlr, 1),\" &\n\t\"2651 (BC_2, IO_AA31, output3, X, 2650, 1, Z),\" & --  PAD192\n\t\"2652 (BC_2, IO_AA31, input, X),\" & --  PAD192\n\t\"2653 (BC_2, *, controlr, 1),\" &\n\t\"2654 (BC_2, IO_AD31, output3, X, 2653, 1, Z),\" & --  PAD191\n\t\"2655 (BC_2, IO_AD31, input, X),\" & --  PAD191\n\t\"2656 (BC_2, *, controlr, 1),\" &\n\t\"2657 (BC_2, IO_AC31, output3, X, 2656, 1, Z),\" & --  PAD190\n\t\"2658 (BC_2, IO_AC31, input, X),\" & --  PAD190\n\t\"2659 (BC_2, *, controlr, 1),\" &\n\t\"2660 (BC_2, IO_Y33, output3, X, 2659, 1, Z),\" & --  PAD189\n\t\"2661 (BC_2, IO_Y33, input, X),\" & --  PAD189\n\t\"2662 (BC_2, *, controlr, 1),\" &\n\t\"2663 (BC_2, IO_Y32, output3, X, 2662, 1, Z),\" & --  PAD188\n\t\"2664 (BC_2, IO_Y32, input, X),\" & --  PAD188\n\t\"2665 (BC_2, *, controlr, 1),\" &\n\t\"2666 (BC_2, IO_AE30, output3, X, 2665, 1, Z),\" & --  PAD187\n\t\"2667 (BC_2, IO_AE30, input, X),\" & --  PAD187\n\t\"2668 (BC_2, *, controlr, 1),\" &\n\t\"2669 (BC_2, IO_AE29, output3, X, 2668, 1, Z),\" & --  PAD186\n\t\"2670 (BC_2, IO_AE29, input, X),\" & --  PAD186\n\t\"2671 (BC_2, *, controlr, 1),\" &\n\t\"2672 (BC_2, IO_AE35, output3, X, 2671, 1, Z),\" & --  PAD185\n\t\"2673 (BC_2, IO_AE35, input, X),\" & --  PAD185\n\t\"2674 (BC_2, *, controlr, 1),\" &\n\t\"2675 (BC_2, IO_AE34, output3, X, 2674, 1, Z),\" & --  PAD184\n\t\"2676 (BC_2, IO_AE34, input, X),\" & --  PAD184\n\t\"2677 (BC_2, *, controlr, 1),\" &\n\t\"2678 (BC_2, IO_AF32, output3, X, 2677, 1, Z),\" & --  PAD183\n\t\"2679 (BC_2, IO_AF32, input, X),\" & --  PAD183\n\t\"2680 (BC_2, *, controlr, 1),\" &\n\t\"2681 (BC_2, IO_AF31, output3, X, 2680, 1, Z),\" & --  PAD182\n\t\"2682 (BC_2, IO_AF31, input, X),\" & --  PAD182\n\t\"2683 (BC_2, *, controlr, 1),\" &\n\t\"2684 (BC_2, IO_AE33, output3, X, 2683, 1, Z),\" & --  PAD181\n\t\"2685 (BC_2, IO_AE33, input, X),\" & --  PAD181\n\t\"2686 (BC_2, *, controlr, 1),\" &\n\t\"2687 (BC_2, IO_AE32, output3, X, 2686, 1, Z),\" & --  PAD180\n\t\"2688 (BC_2, IO_AE32, input, X),\" & --  PAD180\n\t\"2689 (BC_2, *, controlr, 1),\" &\n\t\"2690 (BC_2, IO_AD35, output3, X, 2689, 1, Z),\" & --  PAD179\n\t\"2691 (BC_2, IO_AD35, input, X),\" & --  PAD179\n\t\"2692 (BC_2, *, controlr, 1),\" &\n\t\"2693 (BC_2, IO_AC34, output3, X, 2692, 1, Z),\" & --  PAD178\n\t\"2694 (BC_2, IO_AC34, input, X),\" & --  PAD178\n\t\"2695 (BC_2, *, controlr, 1),\" &\n\t\"2696 (BC_2, IO_AD33, output3, X, 2695, 1, Z),\" & --  PAD177\n\t\"2697 (BC_2, IO_AD33, input, X),\" & --  PAD177\n\t\"2698 (BC_2, *, controlr, 1),\" &\n\t\"2699 (BC_2, IO_AD32, output3, X, 2698, 1, Z),\" & --  PAD176\n\t\"2700 (BC_2, IO_AD32, input, X),\" & --  PAD176\n\t\"2701 (BC_2, *, controlr, 1),\" &\n\t\"2702 (BC_2, IO_AC33, output3, X, 2701, 1, Z),\" & --  PAD175\n\t\"2703 (BC_2, IO_AC33, input, X),\" & --  PAD175\n\t\"2704 (BC_2, *, controlr, 1),\" &\n\t\"2705 (BC_2, IO_AB33, output3, X, 2704, 1, Z),\" & --  PAD174\n\t\"2706 (BC_2, IO_AB33, input, X),\" & --  PAD174\n\t\"2707 (BC_2, *, controlr, 1),\" &\n\t\"2708 (BC_2, IO_AB32, output3, X, 2707, 1, Z),\" & --  PAD173\n\t\"2709 (BC_2, IO_AB32, input, X),\" & --  PAD173\n\t\"2710 (BC_2, *, controlr, 1),\" &\n\t\"2711 (BC_2, IO_AB31, output3, X, 2710, 1, Z),\" & --  PAD172\n\t\"2712 (BC_2, IO_AB31, input, X),\" & --  PAD172\n\t\"2713 (BC_2, *, controlr, 1),\" &\n\t\"2714 (BC_2, IO_AA35, output3, X, 2713, 1, Z),\" & --  PAD171\n\t\"2715 (BC_2, IO_AA35, input, X),\" & --  PAD171\n\t\"2716 (BC_2, *, controlr, 1),\" &\n\t\"2717 (BC_2, IO_AA34, output3, X, 2716, 1, Z),\" & --  PAD170\n\t\"2718 (BC_2, IO_AA34, input, X),\" & --  PAD170\n\t\"2719 (BC_2, *, controlr, 1),\" &\n\t\"2720 (BC_2, IO_AB37, output3, X, 2719, 1, Z),\" & --  PAD169\n\t\"2721 (BC_2, IO_AB37, input, X),\" & --  PAD169\n\t\"2722 (BC_2, *, controlr, 1),\" &\n\t\"2723 (BC_2, IO_AB36, output3, X, 2722, 1, Z),\" & --  PAD168\n\t\"2724 (BC_2, IO_AB36, input, X),\" & --  PAD168\n\t\"2725 (BC_2, *, controlr, 1),\" &\n\t\"2726 (BC_2, IO_AA36, output3, X, 2725, 1, Z),\" & --  PAD167\n\t\"2727 (BC_2, IO_AA36, input, X),\" & --  PAD167\n\t\"2728 (BC_2, *, controlr, 1),\" &\n\t\"2729 (BC_2, IO_Y35, output3, X, 2728, 1, Z),\" & --  PAD166\n\t\"2730 (BC_2, IO_Y35, input, X),\" & --  PAD166\n\t\"2731 (BC_2, *, controlr, 1),\" &\n\t\"2732 (BC_2, IO_AA37, output3, X, 2731, 1, Z),\" & --  PAD165\n\t\"2733 (BC_2, IO_AA37, input, X),\" & --  PAD165\n\t\"2734 (BC_2, *, controlr, 1),\" &\n\t\"2735 (BC_2, IO_Y37, output3, X, 2734, 1, Z),\" & --  PAD164\n\t\"2736 (BC_2, IO_Y37, input, X),\" & --  PAD164\n\t\"2737 (BC_2, *, controlr, 1),\" &\n\t\"2738 (BC_2, IO_AH36, output3, X, 2737, 1, Z),\" & --  PAD163\n\t\"2739 (BC_2, IO_AH36, input, X),\" & --  PAD163\n\t\"2740 (BC_2, *, controlr, 1),\" &\n\t\"2741 (BC_2, IO_AG36, output3, X, 2740, 1, Z),\" & --  PAD162\n\t\"2742 (BC_2, IO_AG36, input, X),\" & --  PAD162\n\t\"2743 (BC_2, *, controlr, 1),\" &\n\t\"2744 (BC_2, IO_AC36, output3, X, 2743, 1, Z),\" & --  PAD161\n\t\"2745 (BC_2, IO_AC36, input, X),\" & --  PAD161\n\t\"2746 (BC_2, *, controlr, 1),\" &\n\t\"2747 (BC_2, IO_AC35, output3, X, 2746, 1, Z),\" & --  PAD160\n\t\"2748 (BC_2, IO_AC35, input, X),\" & --  PAD160\n\t\"2749 (BC_2, *, controlr, 1),\" &\n\t\"2750 (BC_2, IO_AD37, output3, X, 2749, 1, Z),\" & --  PAD159\n\t\"2751 (BC_2, IO_AD37, input, X),\" & --  PAD159\n\t\"2752 (BC_2, *, controlr, 1),\" &\n\t\"2753 (BC_2, IO_AD36, output3, X, 2752, 1, Z),\" & --  PAD158\n\t\"2754 (BC_2, IO_AD36, input, X),\" & --  PAD158\n\t\"2755 (BC_2, *, controlr, 1),\" &\n\t\"2756 (BC_2, IO_AG34, output3, X, 2755, 1, Z),\" & --  PAD157\n\t\"2757 (BC_2, IO_AG34, input, X),\" & --  PAD157\n\t\"2758 (BC_2, *, controlr, 1),\" &\n\t\"2759 (BC_2, IO_AF34, output3, X, 2758, 1, Z),\" & --  PAD156\n\t\"2760 (BC_2, IO_AF34, input, X),\" & --  PAD156\n\t\"2761 (BC_2, *, controlr, 1),\" &\n\t\"2762 (BC_2, IO_AF37, output3, X, 2761, 1, Z),\" & --  PAD155\n\t\"2763 (BC_2, IO_AF37, input, X),\" & --  PAD155\n\t\"2764 (BC_2, *, controlr, 1),\" &\n\t\"2765 (BC_2, IO_AE37, output3, X, 2764, 1, Z),\" & --  PAD154\n\t\"2766 (BC_2, IO_AE37, input, X),\" & --  PAD154\n\t\"2767 (BC_2, *, controlr, 1),\" &\n\t\"2768 (BC_2, IO_AF36, output3, X, 2767, 1, Z),\" & --  PAD153\n\t\"2769 (BC_2, IO_AF36, input, X),\" & --  PAD153\n\t\"2770 (BC_2, *, controlr, 1),\" &\n\t\"2771 (BC_2, IO_AF35, output3, X, 2770, 1, Z),\" & --  PAD152\n\t\"2772 (BC_2, IO_AF35, input, X),\" & --  PAD152\n\t\"2773 (BC_2, *, controlr, 1),\" &\n\t\"2774 (BC_2, IO_Y34, output3, X, 2773, 1, Z),\" & --  PAD151\n\t\"2775 (BC_2, IO_Y34, input, X),\" & --  PAD151\n\t\"2776 (BC_2, *, controlr, 1),\" &\n\t\"2777 (BC_2, IO_AG37, output3, X, 2776, 1, Z),\" & --  PAD150\n\t\"2778 (BC_2, IO_AG37, input, X),\" & --  PAD150\n\t\"2779 (BC_2, *, controlr, 1),\" &\n\t\"2780 (BC_2, IO_AK42, output3, X, 2779, 1, Z),\" & --  PAD149\n\t\"2781 (BC_2, IO_AK42, input, X),\" & --  PAD149\n\t\"2782 (BC_2, *, controlr, 1),\" &\n\t\"2783 (BC_2, IO_AJ42, output3, X, 2782, 1, Z),\" & --  PAD148\n\t\"2784 (BC_2, IO_AJ42, input, X),\" & --  PAD148\n\t\"2785 (BC_2, *, controlr, 1),\" &\n\t\"2786 (BC_2, IO_AL39, output3, X, 2785, 1, Z),\" & --  PAD147\n\t\"2787 (BC_2, IO_AL39, input, X),\" & --  PAD147\n\t\"2788 (BC_2, *, controlr, 1),\" &\n\t\"2789 (BC_2, IO_AK39, output3, X, 2788, 1, Z),\" & --  PAD146\n\t\"2790 (BC_2, IO_AK39, input, X),\" & --  PAD146\n\t\"2791 (BC_2, *, controlr, 1),\" &\n\t\"2792 (BC_2, IO_AJ41, output3, X, 2791, 1, Z),\" & --  PAD145\n\t\"2793 (BC_2, IO_AJ41, input, X),\" & --  PAD145\n\t\"2794 (BC_2, *, controlr, 1),\" &\n\t\"2795 (BC_2, IO_AJ40, output3, X, 2794, 1, Z),\" & --  PAD144\n\t\"2796 (BC_2, IO_AJ40, input, X),\" & --  PAD144\n\t\"2797 (BC_2, *, controlr, 1),\" &\n\t\"2798 (BC_2, IO_AL42, output3, X, 2797, 1, Z),\" & --  PAD143\n\t\"2799 (BC_2, IO_AL42, input, X),\" & --  PAD143\n\t\"2800 (BC_2, *, controlr, 1),\" &\n\t\"2801 (BC_2, IO_AL41, output3, X, 2800, 1, Z),\" & --  PAD142\n\t\"2802 (BC_2, IO_AL41, input, X),\" & --  PAD142\n\t\"2803 (BC_2, *, controlr, 1),\" &\n\t\"2804 (BC_2, IO_AH41, output3, X, 2803, 1, Z),\" & --  PAD141\n\t\"2805 (BC_2, IO_AH41, input, X),\" & --  PAD141\n\t\"2806 (BC_2, *, controlr, 1),\" &\n\t\"2807 (BC_2, IO_AH40, output3, X, 2806, 1, Z),\" & --  PAD140\n\t\"2808 (BC_2, IO_AH40, input, X),\" & --  PAD140\n\t\"2809 (BC_2, *, controlr, 1),\" &\n\t\"2810 (BC_2, IO_AL40, output3, X, 2809, 1, Z),\" & --  PAD139\n\t\"2811 (BC_2, IO_AL40, input, X),\" & --  PAD139\n\t\"2812 (BC_2, *, controlr, 1),\" &\n\t\"2813 (BC_2, IO_AK40, output3, X, 2812, 1, Z),\" & --  PAD138\n\t\"2814 (BC_2, IO_AK40, input, X),\" & --  PAD138\n\t\"2815 (BC_2, *, controlr, 1),\" &\n\t\"2816 (BC_2, IO_AK38, output3, X, 2815, 1, Z),\" & --  PAD137\n\t\"2817 (BC_2, IO_AK38, input, X),\" & --  PAD137\n\t\"2818 (BC_2, *, controlr, 1),\" &\n\t\"2819 (BC_2, IO_AJ38, output3, X, 2818, 1, Z),\" & --  PAD136\n\t\"2820 (BC_2, IO_AJ38, input, X),\" & --  PAD136\n\t\"2821 (BC_2, *, controlr, 1),\" &\n\t\"2822 (BC_2, IO_AH38, output3, X, 2821, 1, Z),\" & --  PAD135\n\t\"2823 (BC_2, IO_AH38, input, X),\" & --  PAD135\n\t\"2824 (BC_2, *, controlr, 1),\" &\n\t\"2825 (BC_2, IO_AG38, output3, X, 2824, 1, Z),\" & --  PAD134\n\t\"2826 (BC_2, IO_AG38, input, X),\" & --  PAD134\n\t\"2827 (BC_2, *, controlr, 1),\" &\n\t\"2828 (BC_2, IO_AG42, output3, X, 2827, 1, Z),\" & --  PAD133\n\t\"2829 (BC_2, IO_AG42, input, X),\" & --  PAD133\n\t\"2830 (BC_2, *, controlr, 1),\" &\n\t\"2831 (BC_2, IO_AF42, output3, X, 2830, 1, Z),\" & --  PAD132\n\t\"2832 (BC_2, IO_AF42, input, X),\" & --  PAD132\n\t\"2833 (BC_2, *, controlr, 1),\" &\n\t\"2834 (BC_2, IO_AH39, output3, X, 2833, 1, Z),\" & --  PAD131\n\t\"2835 (BC_2, IO_AH39, input, X),\" & --  PAD131\n\t\"2836 (BC_2, *, controlr, 1),\" &\n\t\"2837 (BC_2, IO_AG39, output3, X, 2836, 1, Z),\" & --  PAD130\n\t\"2838 (BC_2, IO_AG39, input, X),\" & --  PAD130\n\t\"2839 (BC_2, *, controlr, 1),\" &\n\t\"2840 (BC_2, IO_AG41, output3, X, 2839, 1, Z),\" & --  PAD129\n\t\"2841 (BC_2, IO_AG41, input, X),\" & --  PAD129\n\t\"2842 (BC_2, *, controlr, 1),\" &\n\t\"2843 (BC_2, IO_AF41, output3, X, 2842, 1, Z),\" & --  PAD128\n\t\"2844 (BC_2, IO_AF41, input, X),\" & --  PAD128\n\t\"2845 (BC_2, *, controlr, 1),\" &\n\t\"2846 (BC_2, IO_AF40, output3, X, 2845, 1, Z),\" & --  PAD127\n\t\"2847 (BC_2, IO_AF40, input, X),\" & --  PAD127\n\t\"2848 (BC_2, *, controlr, 1),\" &\n\t\"2849 (BC_2, IO_AF39, output3, X, 2848, 1, Z),\" & --  PAD126\n\t\"2850 (BC_2, IO_AF39, input, X),\" & --  PAD126\n\t\"2851 (BC_2, *, controlr, 1),\" &\n\t\"2852 (BC_2, IO_AD41, output3, X, 2851, 1, Z),\" & --  PAD125\n\t\"2853 (BC_2, IO_AD41, input, X),\" & --  PAD125\n\t\"2854 (BC_2, *, controlr, 1),\" &\n\t\"2855 (BC_2, IO_AD40, output3, X, 2854, 1, Z),\" & --  PAD124\n\t\"2856 (BC_2, IO_AD40, input, X),\" & --  PAD124\n\t\"2857 (BC_2, *, controlr, 1),\" &\n\t\"2858 (BC_2, IO_AE40, output3, X, 2857, 1, Z),\" & --  PAD123\n\t\"2859 (BC_2, IO_AE40, input, X),\" & --  PAD123\n\t\"2860 (BC_2, *, controlr, 1),\" &\n\t\"2861 (BC_2, IO_AE39, output3, X, 2860, 1, Z),\" & --  PAD122\n\t\"2862 (BC_2, IO_AE39, input, X),\" & --  PAD122\n\t\"2863 (BC_2, *, controlr, 1),\" &\n\t\"2864 (BC_2, IO_AC41, output3, X, 2863, 1, Z),\" & --  PAD121\n\t\"2865 (BC_2, IO_AC41, input, X),\" & --  PAD121\n\t\"2866 (BC_2, *, controlr, 1),\" &\n\t\"2867 (BC_2, IO_AC40, output3, X, 2866, 1, Z),\" & --  PAD120\n\t\"2868 (BC_2, IO_AC40, input, X),\" & --  PAD120\n\t\"2869 (BC_2, *, controlr, 1),\" &\n\t\"2870 (BC_2, IO_AE38, output3, X, 2869, 1, Z),\" & --  PAD119\n\t\"2871 (BC_2, IO_AE38, input, X),\" & --  PAD119\n\t\"2872 (BC_2, *, controlr, 1),\" &\n\t\"2873 (BC_2, IO_AD38, output3, X, 2872, 1, Z),\" & --  PAD118\n\t\"2874 (BC_2, IO_AD38, input, X),\" & --  PAD118\n\t\"2875 (BC_2, *, controlr, 1),\" &\n\t\"2876 (BC_2, IO_AE42, output3, X, 2875, 1, Z),\" & --  PAD117\n\t\"2877 (BC_2, IO_AE42, input, X),\" & --  PAD117\n\t\"2878 (BC_2, *, controlr, 1),\" &\n\t\"2879 (BC_2, IO_AD42, output3, X, 2878, 1, Z),\" & --  PAD116\n\t\"2880 (BC_2, IO_AD42, input, X),\" & --  PAD116\n\t\"2881 (BC_2, *, controlr, 1),\" &\n\t\"2882 (BC_2, IO_AC39, output3, X, 2881, 1, Z),\" & --  PAD115\n\t\"2883 (BC_2, IO_AC39, input, X),\" & --  PAD115\n\t\"2884 (BC_2, *, controlr, 1),\" &\n\t\"2885 (BC_2, IO_AC38, output3, X, 2884, 1, Z),\" & --  PAD114\n\t\"2886 (BC_2, IO_AC38, input, X),\" & --  PAD114\n\t\"2887 (BC_2, *, controlr, 1),\" &\n\t\"2888 (BC_2, IO_AA41, output3, X, 2887, 1, Z),\" & --  PAD113\n\t\"2889 (BC_2, IO_AA41, input, X),\" & --  PAD113\n\t\"2890 (BC_2, *, controlr, 1),\" &\n\t\"2891 (BC_2, IO_AA40, output3, X, 2890, 1, Z),\" & --  PAD112\n\t\"2892 (BC_2, IO_AA40, input, X),\" & --  PAD112\n\t\"2893 (BC_2, *, controlr, 1),\" &\n\t\"2894 (BC_2, IO_AB39, output3, X, 2893, 1, Z),\" & --  PAD111\n\t\"2895 (BC_2, IO_AB39, input, X),\" & --  PAD111\n\t\"2896 (BC_2, *, controlr, 1),\" &\n\t\"2897 (BC_2, IO_AB38, output3, X, 2896, 1, Z),\" & --  PAD110\n\t\"2898 (BC_2, IO_AB38, input, X),\" & --  PAD110\n\t\"2899 (BC_2, *, controlr, 1),\" &\n\t\"2900 (BC_2, IO_AA42, output3, X, 2899, 1, Z),\" & --  PAD109\n\t\"2901 (BC_2, IO_AA42, input, X),\" & --  PAD109\n\t\"2902 (BC_2, *, controlr, 1),\" &\n\t\"2903 (BC_2, IO_Y42, output3, X, 2902, 1, Z),\" & --  PAD108\n\t\"2904 (BC_2, IO_Y42, input, X),\" & --  PAD108\n\t\"2905 (BC_2, *, controlr, 1),\" &\n\t\"2906 (BC_2, IO_AA39, output3, X, 2905, 1, Z),\" & --  PAD107\n\t\"2907 (BC_2, IO_AA39, input, X),\" & --  PAD107\n\t\"2908 (BC_2, *, controlr, 1),\" &\n\t\"2909 (BC_2, IO_Y39, output3, X, 2908, 1, Z),\" & --  PAD106\n\t\"2910 (BC_2, IO_Y39, input, X),\" & --  PAD106\n\t\"2911 (BC_2, *, controlr, 1),\" &\n\t\"2912 (BC_2, IO_Y40, output3, X, 2911, 1, Z),\" & --  PAD105\n\t\"2913 (BC_2, IO_Y40, input, X),\" & --  PAD105\n\t\"2914 (BC_2, *, controlr, 1),\" &\n\t\"2915 (BC_2, IO_W40, output3, X, 2914, 1, Z),\" & --  PAD104\n\t\"2916 (BC_2, IO_W40, input, X),\" & --  PAD104\n\t\"2917 (BC_2, *, controlr, 1),\" &\n\t\"2918 (BC_2, IO_AB42, output3, X, 2917, 1, Z),\" & --  PAD103\n\t\"2919 (BC_2, IO_AB42, input, X),\" & --  PAD103\n\t\"2920 (BC_2, *, controlr, 1),\" &\n\t\"2921 (BC_2, IO_AB41, output3, X, 2920, 1, Z),\" & --  PAD102\n\t\"2922 (BC_2, IO_AB41, input, X),\" & --  PAD102\n\t\"2923 (BC_2, *, controlr, 1),\" &\n\t\"2924 (BC_2, IO_Y38, output3, X, 2923, 1, Z),\" & --  PAD101\n\t\"2925 (BC_2, IO_Y38, input, X),\" & --  PAD101\n\t\"2926 (BC_2, *, controlr, 1),\" &\n\t\"2927 (BC_2, IO_W35, output3, X, 2926, 1, Z),\" & --  PAD100\n\t\"2928 (BC_2, IO_W35, input, X),\" & --  PAD100\n\t\"2929 (BC_2, *, controlr, 1),\" &\n\t\"2930 (BC_2, IO_U42, output3, X, 2929, 1, Z),\" & --  PAD99\n\t\"2931 (BC_2, IO_U42, input, X),\" & --  PAD99\n\t\"2932 (BC_2, *, controlr, 1),\" &\n\t\"2933 (BC_2, IO_V41, output3, X, 2932, 1, Z),\" & --  PAD98\n\t\"2934 (BC_2, IO_V41, input, X),\" & --  PAD98\n\t\"2935 (BC_2, *, controlr, 1),\" &\n\t\"2936 (BC_2, IO_V38, output3, X, 2935, 1, Z),\" & --  PAD97\n\t\"2937 (BC_2, IO_V38, input, X),\" & --  PAD97\n\t\"2938 (BC_2, *, controlr, 1),\" &\n\t\"2939 (BC_2, IO_W38, output3, X, 2938, 1, Z),\" & --  PAD96\n\t\"2940 (BC_2, IO_W38, input, X),\" & --  PAD96\n\t\"2941 (BC_2, *, controlr, 1),\" &\n\t\"2942 (BC_2, IO_T42, output3, X, 2941, 1, Z),\" & --  PAD95\n\t\"2943 (BC_2, IO_T42, input, X),\" & --  PAD95\n\t\"2944 (BC_2, *, controlr, 1),\" &\n\t\"2945 (BC_2, IO_U41, output3, X, 2944, 1, Z),\" & --  PAD94\n\t\"2946 (BC_2, IO_U41, input, X),\" & --  PAD94\n\t\"2947 (BC_2, *, controlr, 1),\" &\n\t\"2948 (BC_2, IO_W42, output3, X, 2947, 1, Z),\" & --  PAD93\n\t\"2949 (BC_2, IO_W42, input, X),\" & --  PAD93\n\t\"2950 (BC_2, *, controlr, 1),\" &\n\t\"2951 (BC_2, IO_W41, output3, X, 2950, 1, Z),\" & --  PAD92\n\t\"2952 (BC_2, IO_W41, input, X),\" & --  PAD92\n\t\"2953 (BC_2, *, controlr, 1),\" &\n\t\"2954 (BC_2, IO_T41, output3, X, 2953, 1, Z),\" & --  PAD91\n\t\"2955 (BC_2, IO_T41, input, X),\" & --  PAD91\n\t\"2956 (BC_2, *, controlr, 1),\" &\n\t\"2957 (BC_2, IO_T40, output3, X, 2956, 1, Z),\" & --  PAD90\n\t\"2958 (BC_2, IO_T40, input, X),\" & --  PAD90\n\t\"2959 (BC_2, *, controlr, 1),\" &\n\t\"2960 (BC_2, IO_V40, output3, X, 2959, 1, Z),\" & --  PAD89\n\t\"2961 (BC_2, IO_V40, input, X),\" & --  PAD89\n\t\"2962 (BC_2, *, controlr, 1),\" &\n\t\"2963 (BC_2, IO_V39, output3, X, 2962, 1, Z),\" & --  PAD88\n\t\"2964 (BC_2, IO_V39, input, X),\" & --  PAD88\n\t\"2965 (BC_2, *, controlr, 1),\" &\n\t\"2966 (BC_2, IO_W33, output3, X, 2965, 1, Z),\" & --  PAD87\n\t\"2967 (BC_2, IO_W33, input, X),\" & --  PAD87\n\t\"2968 (BC_2, *, controlr, 1),\" &\n\t\"2969 (BC_2, IO_W32, output3, X, 2968, 1, Z),\" & --  PAD86\n\t\"2970 (BC_2, IO_W32, input, X),\" & --  PAD86\n\t\"2971 (BC_2, *, controlr, 1),\" &\n\t\"2972 (BC_2, IO_U33, output3, X, 2971, 1, Z),\" & --  PAD85\n\t\"2973 (BC_2, IO_U33, input, X),\" & --  PAD85\n\t\"2974 (BC_2, *, controlr, 1),\" &\n\t\"2975 (BC_2, IO_U32, output3, X, 2974, 1, Z),\" & --  PAD84\n\t\"2976 (BC_2, IO_U32, input, X),\" & --  PAD84\n\t\"2977 (BC_2, *, controlr, 1),\" &\n\t\"2978 (BC_2, IO_W37, output3, X, 2977, 1, Z),\" & --  PAD83\n\t\"2979 (BC_2, IO_W37, input, X),\" & --  PAD83\n\t\"2980 (BC_2, *, controlr, 1),\" &\n\t\"2981 (BC_2, IO_W36, output3, X, 2980, 1, Z),\" & --  PAD82\n\t\"2982 (BC_2, IO_W36, input, X),\" & --  PAD82\n\t\"2983 (BC_2, *, controlr, 1),\" &\n\t\"2984 (BC_2, IO_V34, output3, X, 2983, 1, Z),\" & --  PAD81\n\t\"2985 (BC_2, IO_V34, input, X),\" & --  PAD81\n\t\"2986 (BC_2, *, controlr, 1),\" &\n\t\"2987 (BC_2, IO_V33, output3, X, 2986, 1, Z),\" & --  PAD80\n\t\"2988 (BC_2, IO_V33, input, X),\" & --  PAD80\n\t\"2989 (BC_2, *, controlr, 1),\" &\n\t\"2990 (BC_2, IO_V36, output3, X, 2989, 1, Z),\" & --  PAD79\n\t\"2991 (BC_2, IO_V36, input, X),\" & --  PAD79\n\t\"2992 (BC_2, *, controlr, 1),\" &\n\t\"2993 (BC_2, IO_V35, output3, X, 2992, 1, Z),\" & --  PAD78\n\t\"2994 (BC_2, IO_V35, input, X),\" & --  PAD78\n\t\"2995 (BC_2, *, controlr, 1),\" &\n\t\"2996 (BC_2, IO_T37, output3, X, 2995, 1, Z),\" & --  PAD77\n\t\"2997 (BC_2, IO_T37, input, X),\" & --  PAD77\n\t\"2998 (BC_2, *, controlr, 1),\" &\n\t\"2999 (BC_2, IO_U36, output3, X, 2998, 1, Z),\" & --  PAD76\n\t\"3000 (BC_2, IO_U36, input, X),\" & --  PAD76\n\t\"3001 (BC_2, *, controlr, 1),\" &\n\t\"3002 (BC_2, IO_T39, output3, X, 3001, 1, Z),\" & --  PAD75\n\t\"3003 (BC_2, IO_T39, input, X),\" & --  PAD75\n\t\"3004 (BC_2, *, controlr, 1),\" &\n\t\"3005 (BC_2, IO_U39, output3, X, 3004, 1, Z),\" & --  PAD74\n\t\"3006 (BC_2, IO_U39, input, X),\" & --  PAD74\n\t\"3007 (BC_2, *, controlr, 1),\" &\n\t\"3008 (BC_2, IO_U38, output3, X, 3007, 1, Z),\" & --  PAD73\n\t\"3009 (BC_2, IO_U38, input, X),\" & --  PAD73\n\t\"3010 (BC_2, *, controlr, 1),\" &\n\t\"3011 (BC_2, IO_U37, output3, X, 3010, 1, Z),\" & --  PAD72\n\t\"3012 (BC_2, IO_U37, input, X),\" & --  PAD72\n\t\"3013 (BC_2, *, controlr, 1),\" &\n\t\"3014 (BC_2, IO_R39, output3, X, 3013, 1, Z),\" & --  PAD71\n\t\"3015 (BC_2, IO_R39, input, X),\" & --  PAD71\n\t\"3016 (BC_2, *, controlr, 1),\" &\n\t\"3017 (BC_2, IO_R38, output3, X, 3016, 1, Z),\" & --  PAD70\n\t\"3018 (BC_2, IO_R38, input, X),\" & --  PAD70\n\t\"3019 (BC_2, *, controlr, 1),\" &\n\t\"3020 (BC_2, IO_T35, output3, X, 3019, 1, Z),\" & --  PAD69\n\t\"3021 (BC_2, IO_T35, input, X),\" & --  PAD69\n\t\"3022 (BC_2, *, controlr, 1),\" &\n\t\"3023 (BC_2, IO_U34, output3, X, 3022, 1, Z),\" & --  PAD68\n\t\"3024 (BC_2, IO_U34, input, X),\" & --  PAD68\n\t\"3025 (BC_2, *, controlr, 1),\" &\n\t\"3026 (BC_2, IO_P38, output3, X, 3025, 1, Z),\" & --  PAD67\n\t\"3027 (BC_2, IO_P38, input, X),\" & --  PAD67\n\t\"3028 (BC_2, *, controlr, 1),\" &\n\t\"3029 (BC_2, IO_P37, output3, X, 3028, 1, Z),\" & --  PAD66\n\t\"3030 (BC_2, IO_P37, input, X),\" & --  PAD66\n\t\"3031 (BC_2, *, controlr, 1),\" &\n\t\"3032 (BC_2, IO_R37, output3, X, 3031, 1, Z),\" & --  PAD65\n\t\"3033 (BC_2, IO_R37, input, X),\" & --  PAD65\n\t\"3034 (BC_2, *, controlr, 1),\" &\n\t\"3035 (BC_2, IO_T36, output3, X, 3034, 1, Z),\" & --  PAD64\n\t\"3036 (BC_2, IO_T36, input, X),\" & --  PAD64\n\t\"3037 (BC_2, *, controlr, 1),\" &\n\t\"3038 (BC_2, IO_P33, output3, X, 3037, 1, Z),\" & --  PAD63\n\t\"3039 (BC_2, IO_P33, input, X),\" & --  PAD63\n\t\"3040 (BC_2, *, controlr, 1),\" &\n\t\"3041 (BC_2, IO_P32, output3, X, 3040, 1, Z),\" & --  PAD62\n\t\"3042 (BC_2, IO_P32, input, X),\" & --  PAD62\n\t\"3043 (BC_2, *, controlr, 1),\" &\n\t\"3044 (BC_2, IO_R32, output3, X, 3043, 1, Z),\" & --  PAD61\n\t\"3045 (BC_2, IO_R32, input, X),\" & --  PAD61\n\t\"3046 (BC_2, *, controlr, 1),\" &\n\t\"3047 (BC_2, IO_T32, output3, X, 3046, 1, Z),\" & --  PAD60\n\t\"3048 (BC_2, IO_T32, input, X),\" & --  PAD60\n\t\"3049 (BC_2, *, controlr, 1),\" &\n\t\"3050 (BC_2, IO_P36, output3, X, 3049, 1, Z),\" & --  PAD59\n\t\"3051 (BC_2, IO_P36, input, X),\" & --  PAD59\n\t\"3052 (BC_2, *, controlr, 1),\" &\n\t\"3053 (BC_2, IO_P35, output3, X, 3052, 1, Z),\" & --  PAD58\n\t\"3054 (BC_2, IO_P35, input, X),\" & --  PAD58\n\t\"3055 (BC_2, *, controlr, 1),\" &\n\t\"3056 (BC_2, IO_R34, output3, X, 3055, 1, Z),\" & --  PAD57\n\t\"3057 (BC_2, IO_R34, input, X),\" & --  PAD57\n\t\"3058 (BC_2, *, controlr, 1),\" &\n\t\"3059 (BC_2, IO_R33, output3, X, 3058, 1, Z),\" & --  PAD56\n\t\"3060 (BC_2, IO_R33, input, X),\" & --  PAD56\n\t\"3061 (BC_2, *, controlr, 1),\" &\n\t\"3062 (BC_2, IO_N34, output3, X, 3061, 1, Z),\" & --  PAD55\n\t\"3063 (BC_2, IO_N34, input, X),\" & --  PAD55\n\t\"3064 (BC_2, *, controlr, 1),\" &\n\t\"3065 (BC_2, IO_N33, output3, X, 3064, 1, Z),\" & --  PAD54\n\t\"3066 (BC_2, IO_N33, input, X),\" & --  PAD54\n\t\"3067 (BC_2, *, controlr, 1),\" &\n\t\"3068 (BC_2, IO_R35, output3, X, 3067, 1, Z),\" & --  PAD53\n\t\"3069 (BC_2, IO_R35, input, X),\" & --  PAD53\n\t\"3070 (BC_2, *, controlr, 1),\" &\n\t\"3071 (BC_2, IO_T34, output3, X, 3070, 1, Z),\" & --  PAD52\n\t\"3072 (BC_2, IO_T34, input, X),\" & --  PAD52\n\t\"3073 (BC_2, *, controlr, 1),\" &\n\t\"3074 (BC_2, IO_N35, output3, X, 3073, 1, Z),\" & --  PAD51\n\t\"3075 (BC_2, IO_N35, input, X),\" & --  PAD51\n\t\"3076 (BC_2, *, controlr, 1),\" &\n\t\"3077 (BC_2, IO_N36, output3, X, 3076, 1, Z),\" & --  PAD50\n\t\"3078 (BC_2, IO_N36, input, X),\" & --  PAD50\n\t\"3079 (BC_2, *, controlr, 1),\" &\n\t\"3080 (BC_2, IO_N40, output3, X, 3079, 1, Z),\" & --  PAD49\n\t\"3081 (BC_2, IO_N40, input, X),\" & --  PAD49\n\t\"3082 (BC_2, *, controlr, 1),\" &\n\t\"3083 (BC_2, IO_N39, output3, X, 3082, 1, Z),\" & --  PAD48\n\t\"3084 (BC_2, IO_N39, input, X),\" & --  PAD48\n\t\"3085 (BC_2, *, controlr, 1),\" &\n\t\"3086 (BC_2, IO_P40, output3, X, 3085, 1, Z),\" & --  PAD47\n\t\"3087 (BC_2, IO_P40, input, X),\" & --  PAD47\n\t\"3088 (BC_2, *, controlr, 1),\" &\n\t\"3089 (BC_2, IO_R40, output3, X, 3088, 1, Z),\" & --  PAD46\n\t\"3090 (BC_2, IO_R40, input, X),\" & --  PAD46\n\t\"3091 (BC_2, *, controlr, 1),\" &\n\t\"3092 (BC_2, IO_M39, output3, X, 3091, 1, Z),\" & --  PAD45\n\t\"3093 (BC_2, IO_M39, input, X),\" & --  PAD45\n\t\"3094 (BC_2, *, controlr, 1),\" &\n\t\"3095 (BC_2, IO_N38, output3, X, 3094, 1, Z),\" & --  PAD44\n\t\"3096 (BC_2, IO_N38, input, X),\" & --  PAD44\n\t\"3097 (BC_2, *, controlr, 1),\" &\n\t\"3098 (BC_2, IO_P42, output3, X, 3097, 1, Z),\" & --  PAD43\n\t\"3099 (BC_2, IO_P42, input, X),\" & --  PAD43\n\t\"3100 (BC_2, *, controlr, 1),\" &\n\t\"3101 (BC_2, IO_R42, output3, X, 3100, 1, Z),\" & --  PAD42\n\t\"3102 (BC_2, IO_R42, input, X),\" & --  PAD42\n\t\"3103 (BC_2, *, controlr, 1),\" &\n\t\"3104 (BC_2, IO_M38, output3, X, 3103, 1, Z),\" & --  PAD41\n\t\"3105 (BC_2, IO_M38, input, X),\" & --  PAD41\n\t\"3106 (BC_2, *, controlr, 1),\" &\n\t\"3107 (BC_2, IO_M37, output3, X, 3106, 1, Z),\" & --  PAD40\n\t\"3108 (BC_2, IO_M37, input, X),\" & --  PAD40\n\t\"3109 (BC_2, *, controlr, 1),\" &\n\t\"3110 (BC_2, IO_N41, output3, X, 3109, 1, Z),\" & --  PAD39\n\t\"3111 (BC_2, IO_N41, input, X),\" & --  PAD39\n\t\"3112 (BC_2, *, controlr, 1),\" &\n\t\"3113 (BC_2, IO_P41, output3, X, 3112, 1, Z),\" & --  PAD38\n\t\"3114 (BC_2, IO_P41, input, X),\" & --  PAD38\n\t\"3115 (BC_2, *, controlr, 1),\" &\n\t\"3116 (BC_2, IO_L37, output3, X, 3115, 1, Z),\" & --  PAD37\n\t\"3117 (BC_2, IO_L37, input, X),\" & --  PAD37\n\t\"3118 (BC_2, *, controlr, 1),\" &\n\t\"3119 (BC_2, IO_M36, output3, X, 3118, 1, Z),\" & --  PAD36\n\t\"3120 (BC_2, IO_M36, input, X),\" & --  PAD36\n\t\"3121 (BC_2, *, controlr, 1),\" &\n\t\"3122 (BC_2, IO_K38, output3, X, 3121, 1, Z),\" & --  PAD35\n\t\"3123 (BC_2, IO_K38, input, X),\" & --  PAD35\n\t\"3124 (BC_2, *, controlr, 1),\" &\n\t\"3125 (BC_2, IO_K37, output3, X, 3124, 1, Z),\" & --  PAD34\n\t\"3126 (BC_2, IO_K37, input, X),\" & --  PAD34\n\t\"3127 (BC_2, *, controlr, 1),\" &\n\t\"3128 (BC_2, IO_L42, output3, X, 3127, 1, Z),\" & --  PAD33\n\t\"3129 (BC_2, IO_L42, input, X),\" & --  PAD33\n\t\"3130 (BC_2, *, controlr, 1),\" &\n\t\"3131 (BC_2, IO_M42, output3, X, 3130, 1, Z),\" & --  PAD32\n\t\"3132 (BC_2, IO_M42, input, X),\" & --  PAD32\n\t\"3133 (BC_2, *, controlr, 1),\" &\n\t\"3134 (BC_2, IO_J42, output3, X, 3133, 1, Z),\" & --  PAD31\n\t\"3135 (BC_2, IO_J42, input, X),\" & --  PAD31\n\t\"3136 (BC_2, *, controlr, 1),\" &\n\t\"3137 (BC_2, IO_K42, output3, X, 3136, 1, Z),\" & --  PAD30\n\t\"3138 (BC_2, IO_K42, input, X),\" & --  PAD30\n\t\"3139 (BC_2, *, controlr, 1),\" &\n\t\"3140 (BC_2, IO_L41, output3, X, 3139, 1, Z),\" & --  PAD29\n\t\"3141 (BC_2, IO_L41, input, X),\" & --  PAD29\n\t\"3142 (BC_2, *, controlr, 1),\" &\n\t\"3143 (BC_2, IO_M41, output3, X, 3142, 1, Z),\" & --  PAD28\n\t\"3144 (BC_2, IO_M41, input, X),\" & --  PAD28\n\t\"3145 (BC_2, *, controlr, 1),\" &\n\t\"3146 (BC_2, IO_L40, output3, X, 3145, 1, Z),\" & --  PAD27\n\t\"3147 (BC_2, IO_L40, input, X),\" & --  PAD27\n\t\"3148 (BC_2, *, controlr, 1),\" &\n\t\"3149 (BC_2, IO_L39, output3, X, 3148, 1, Z),\" & --  PAD26\n\t\"3150 (BC_2, IO_L39, input, X),\" & --  PAD26\n\t\"3151 (BC_2, *, controlr, 1),\" &\n\t\"3152 (BC_2, IO_K40, output3, X, 3151, 1, Z),\" & --  PAD25\n\t\"3153 (BC_2, IO_K40, input, X),\" & --  PAD25\n\t\"3154 (BC_2, *, controlr, 1),\" &\n\t\"3155 (BC_2, IO_K39, output3, X, 3154, 1, Z),\" & --  PAD24\n\t\"3156 (BC_2, IO_K39, input, X),\" & --  PAD24\n\t\"3157 (BC_2, *, controlr, 1),\" &\n\t\"3158 (BC_2, IO_J41, output3, X, 3157, 1, Z),\" & --  PAD23\n\t\"3159 (BC_2, IO_J41, input, X),\" & --  PAD23\n\t\"3160 (BC_2, *, controlr, 1),\" &\n\t\"3161 (BC_2, IO_J40, output3, X, 3160, 1, Z),\" & --  PAD22\n\t\"3162 (BC_2, IO_J40, input, X),\" & --  PAD22\n\t\"3163 (BC_2, *, controlr, 1),\" &\n\t\"3164 (BC_2, IO_F41, output3, X, 3163, 1, Z),\" & --  PAD21\n\t\"3165 (BC_2, IO_F41, input, X),\" & --  PAD21\n\t\"3166 (BC_2, *, controlr, 1),\" &\n\t\"3167 (BC_2, IO_F40, output3, X, 3166, 1, Z),\" & --  PAD20\n\t\"3168 (BC_2, IO_F40, input, X),\" & --  PAD20\n\t\"3169 (BC_2, *, controlr, 1),\" &\n\t\"3170 (BC_2, IO_G42, output3, X, 3169, 1, Z),\" & --  PAD19\n\t\"3171 (BC_2, IO_G42, input, X),\" & --  PAD19\n\t\"3172 (BC_2, *, controlr, 1),\" &\n\t\"3173 (BC_2, IO_G41, output3, X, 3172, 1, Z),\" & --  PAD18\n\t\"3174 (BC_2, IO_G41, input, X),\" & --  PAD18\n\t\"3175 (BC_2, *, controlr, 1),\" &\n\t\"3176 (BC_2, IO_G39, output3, X, 3175, 1, Z),\" & --  PAD17\n\t\"3177 (BC_2, IO_G39, input, X),\" & --  PAD17\n\t\"3178 (BC_2, *, controlr, 1),\" &\n\t\"3179 (BC_2, IO_H39, output3, X, 3178, 1, Z),\" & --  PAD16\n\t\"3180 (BC_2, IO_H39, input, X),\" & --  PAD16\n\t\"3181 (BC_2, *, controlr, 1),\" &\n\t\"3182 (BC_2, IO_H41, output3, X, 3181, 1, Z),\" & --  PAD15\n\t\"3183 (BC_2, IO_H41, input, X),\" & --  PAD15\n\t\"3184 (BC_2, *, controlr, 1),\" &\n\t\"3185 (BC_2, IO_H40, output3, X, 3184, 1, Z),\" & --  PAD14\n\t\"3186 (BC_2, IO_H40, input, X),\" & --  PAD14\n\t\"3187 (BC_2, *, controlr, 1),\" &\n\t\"3188 (BC_2, IO_C41, output3, X, 3187, 1, Z),\" & --  PAD13\n\t\"3189 (BC_2, IO_C41, input, X),\" & --  PAD13\n\t\"3190 (BC_2, *, controlr, 1),\" &\n\t\"3191 (BC_2, IO_C40, output3, X, 3190, 1, Z),\" & --  PAD12\n\t\"3192 (BC_2, IO_C40, input, X),\" & --  PAD12\n\t\"3193 (BC_2, *, controlr, 1),\" &\n\t\"3194 (BC_2, IO_E42, output3, X, 3193, 1, Z),\" & --  PAD11\n\t\"3195 (BC_2, IO_E42, input, X),\" & --  PAD11\n\t\"3196 (BC_2, *, controlr, 1),\" &\n\t\"3197 (BC_2, IO_F42, output3, X, 3196, 1, Z),\" & --  PAD10\n\t\"3198 (BC_2, IO_F42, input, X),\" & --  PAD10\n\t\"3199 (BC_2, *, controlr, 1),\" &\n\t\"3200 (BC_2, IO_B42, output3, X, 3199, 1, Z),\" & --  PAD9\n\t\"3201 (BC_2, IO_B42, input, X),\" & --  PAD9\n\t\"3202 (BC_2, *, controlr, 1),\" &\n\t\"3203 (BC_2, IO_B41, output3, X, 3202, 1, Z),\" & --  PAD8\n\t\"3204 (BC_2, IO_B41, input, X),\" & --  PAD8\n\t\"3205 (BC_2, *, controlr, 1),\" &\n\t\"3206 (BC_2, IO_D42, output3, X, 3205, 1, Z),\" & --  PAD7\n\t\"3207 (BC_2, IO_D42, input, X),\" & --  PAD7\n\t\"3208 (BC_2, *, controlr, 1),\" &\n\t\"3209 (BC_2, IO_D41, output3, X, 3208, 1, Z),\" & --  PAD6\n\t\"3210 (BC_2, IO_D41, input, X),\" & --  PAD6\n\t\"3211 (BC_2, *, controlr, 1),\" &\n\t\"3212 (BC_2, IO_A41, output3, X, 3211, 1, Z),\" & --  PAD5\n\t\"3213 (BC_2, IO_A41, input, X),\" & --  PAD5\n\t\"3214 (BC_2, *, controlr, 1),\" &\n\t\"3215 (BC_2, IO_A40, output3, X, 3214, 1, Z),\" & --  PAD4\n\t\"3216 (BC_2, IO_A40, input, X),\" & --  PAD4\n\t\"3217 (BC_2, *, controlr, 1),\" &\n\t\"3218 (BC_2, IO_D40, output3, X, 3217, 1, Z),\" & --  PAD3\n\t\"3219 (BC_2, IO_D40, input, X),\" & --  PAD3\n\t\"3220 (BC_2, *, controlr, 1),\" &\n\t\"3221 (BC_2, IO_E40, output3, X, 3220, 1, Z),\" & --  PAD2\n\t\"3222 (BC_2, IO_E40, input, X),\" & --  PAD2\n\t\"3223 (BC_2, *, controlr, 1),\" &\n\t\"3224 (BC_2, IO_L36, output3, X, 3223, 1, Z),\" & --  PAD1\n\t\"3225 (BC_2, IO_L36, input, X),\" & --  PAD1\n\t\"3226 (BC_2, *, internal, X),\" &\n\t\"3227 (BC_2, *, internal, X),\" &\n\t\"3228 (BC_2, *, internal, X),\" &\n\t\"3229 (BC_2, *, internal, X),\" &\n\t\"3230 (BC_2, *, internal, X),\" &\n\t\"3231 (BC_2, *, internal, X),\" &\n\t\"3232 (BC_2, *, internal, X),\" &\n\t\"3233 (BC_2, *, internal, X),\" &\n\t\"3234 (BC_2, *, internal, X),\" &\n\t\"3235 (BC_2, *, internal, X),\" &\n\t\"3236 (BC_2, *, internal, X),\" &\n\t\"3237 (BC_2, *, internal, X),\" &\n\t\"3238 (BC_2, *, internal, X),\" &\n\t\"3239 (BC_2, *, internal, X),\" &\n\t\"3240 (BC_2, *, internal, X),\" &\n\t\"3241 (BC_2, *, internal, X),\" &\n\t\"3242 (BC_2, *, internal, X),\" &\n\t\"3243 (BC_2, *, internal, X),\" &\n\t\"3244 (BC_2, *, internal, X),\" &\n\t\"3245 (BC_2, *, internal, X),\" &\n\t\"3246 (BC_2, *, internal, X),\" &\n\t\"3247 (BC_4, *, internal, X),\" &\n\t\"3248 (BC_4, *, internal, X),\" &\n\t\"3249 (BC_4, *, internal, X),\" &\n\t\"3250 (BC_4, *, internal, X),\" &\n\t\"3251 (BC_4, *, internal, X),\" &\n\t\"3252 (BC_4, *, internal, X),\" &\n\t\"3253 (BC_4, *, internal, X),\" &\n\t\"3254 (BC_4, *, internal, X),\" &\n\t\"3255 (BC_4, *, internal, X),\" &\n\t\"3256 (BC_4, *, internal, X),\" &\n\t\"3257 (BC_4, *, internal, X),\" &\n\t\"3258 (BC_4, *, internal, X),\" &\n\t\"3259 (BC_4, *, internal, X),\" &\n\t\"3260 (BC_4, *, internal, X),\" &\n\t\"3261 (BC_4, *, internal, X),\" &\n\t\"3262 (BC_4, *, internal, X),\" &\n\t\"3263 (BC_4, *, internal, X),\" &\n\t\"3264 (BC_4, *, internal, X),\" &\n\t\"3265 (BC_4, *, internal, X),\" &\n\t\"3266 (BC_4, *, internal, X),\" &\n\t\"3267 (BC_4, *, internal, X),\" &\n\t\"3268 (BC_4, *, internal, X),\" &\n\t\"3269 (BC_4, *, internal, X),\" &\n\t\"3270 (BC_4, *, internal, X),\" &\n\t\"3271 (BC_4, *, internal, X),\" &\n\t\"3272 (BC_4, *, internal, X),\" &\n\t\"3273 (BC_4, *, internal, X),\" &\n\t\"3274 (BC_4, *, internal, X),\" &\n\t\"3275 (BC_4, *, internal, X),\" &\n\t\"3276 (BC_4, *, internal, X),\" &\n\t\"3277 (BC_4, *, internal, X),\" &\n\t\"3278 (BC_4, *, internal, X),\" &\n\t\"3279 (BC_4, *, internal, X),\" &\n\t\"3280 (BC_4, *, internal, X),\" &\n\t\"3281 (BC_4, *, internal, X),\" &\n\t\"3282 (BC_4, *, internal, X),\" &\n\t\"3283 (BC_4, *, internal, X),\" &\n\t\"3284 (BC_4, *, internal, X),\" &\n\t\"3285 (BC_4, *, internal, X),\" &\n\t\"3286 (BC_4, *, internal, X),\" &\n\t\"3287 (BC_4, *, internal, X),\" &\n\t\"3288 (BC_4, *, internal, X),\" &\n\t\"3289 (BC_4, *, internal, X),\" &\n\t\"3290 (BC_4, *, internal, X),\" &\n\t\"3291 (BC_4, *, internal, X),\" &\n\t\"3292 (BC_4, *, internal, X),\" &\n\t\"3293 (BC_4, *, internal, X),\" &\n\t\"3294 (BC_4, *, internal, X),\" &\n\t\"3295 (BC_4, *, internal, X),\" &\n\t\"3296 (BC_4, *, internal, X),\" &\n\t\"3297 (BC_4, *, internal, X),\" &\n\t\"3298 (BC_4, *, internal, X),\" &\n\t\"3299 (BC_4, *, internal, X),\" &\n\t\"3300 (BC_4, *, internal, X),\" &\n\t\"3301 (BC_4, *, internal, X),\" &\n\t\"3302 (BC_4, *, internal, X),\" &\n\t\"3303 (BC_4, *, internal, X),\" &\n\t\"3304 (BC_4, *, internal, X),\" &\n\t\"3305 (BC_4, *, internal, X),\" &\n\t\"3306 (BC_4, *, internal, X),\" &\n\t\"3307 (BC_4, *, internal, X),\" &\n\t\"3308 (BC_4, *, internal, X),\" &\n\t\"3309 (BC_4, *, internal, X),\" &\n\t\"3310 (BC_4, *, internal, X),\" &\n\t\"3311 (BC_4, *, internal, X),\" &\n\t\"3312 (BC_4, *, internal, X),\" &\n\t\"3313 (BC_4, *, internal, X),\" &\n\t\"3314 (BC_4, *, internal, X),\" &\n\t\"3315 (BC_4, *, internal, X),\" &\n\t\"3316 (BC_4, *, internal, X),\" &\n\t\"3317 (BC_4, *, internal, X),\" &\n\t\"3318 (BC_4, *, internal, X),\" &\n\t\"3319 (BC_4, *, internal, X),\" &\n\t\"3320 (BC_4, *, internal, X),\" &\n\t\"3321 (BC_4, *, internal, X),\" &\n\t\"3322 (BC_4, *, internal, X),\" &\n\t\"3323 (BC_4, *, internal, X),\" &\n\t\"3324 (BC_4, *, internal, X),\" &\n\t\"3325 (BC_4, *, internal, X),\" &\n\t\"3326 (BC_4, *, internal, X),\" &\n\t\"3327 (BC_4, *, internal, X),\" &\n\t\"3328 (BC_4, *, internal, X),\" &\n\t\"3329 (BC_4, *, internal, X),\" &\n\t\"3330 (BC_4, *, internal, X),\" &\n\t\"3331 (BC_4, *, internal, X),\" &\n\t\"3332 (BC_4, *, internal, X),\" &\n\t\"3333 (BC_4, *, internal, X),\" &\n\t\"3334 (BC_4, *, internal, X),\" &\n\t\"3335 (BC_4, *, internal, X),\" &\n\t\"3336 (BC_4, *, internal, X),\" &\n\t\"3337 (BC_4, *, internal, X),\" &\n\t\"3338 (BC_4, *, internal, X),\" &\n\t\"3339 (BC_4, *, internal, X),\" &\n\t\"3340 (BC_4, *, internal, X),\" &\n\t\"3341 (BC_4, *, internal, X),\" &\n\t\"3342 (BC_4, *, internal, X),\" &\n\t\"3343 (BC_4, *, internal, X),\" &\n\t\"3344 (BC_4, *, internal, X),\" &\n\t\"3345 (BC_4, *, internal, X),\" &\n\t\"3346 (BC_4, *, internal, X),\" &\n\t\"3347 (BC_4, *, internal, X),\" &\n\t\"3348 (BC_4, *, internal, X),\" &\n\t\"3349 (BC_4, *, internal, X),\" &\n\t\"3350 (BC_4, *, internal, X),\" &\n\t\"3351 (BC_4, *, internal, X),\" &\n\t\"3352 (BC_4, *, internal, X),\" &\n\t\"3353 (BC_4, *, internal, X),\" &\n\t\"3354 (BC_4, *, internal, X),\" &\n\t\"3355 (BC_4, *, internal, X),\" &\n\t\"3356 (BC_4, *, internal, X),\" &\n\t\"3357 (BC_4, *, internal, X),\" &\n\t\"3358 (BC_4, *, internal, X),\" &\n\t\"3359 (BC_4, *, internal, X),\" &\n\t\"3360 (BC_4, *, internal, X),\" &\n\t\"3361 (BC_4, *, internal, X),\" &\n\t\"3362 (BC_4, *, internal, X),\" &\n\t\"3363 (BC_4, *, internal, X),\" &\n\t\"3364 (BC_4, *, internal, X),\" &\n\t\"3365 (BC_4, *, internal, X),\" &\n\t\"3366 (BC_4, *, internal, X),\" &\n\t\"3367 (BC_2, *, internal, X),\" &\n\t\"3368 (BC_2, *, internal, X),\" &\n\t\"3369 (BC_2, *, internal, X),\" &\n\t\"3370 (BC_2, *, internal, X),\" &\n\t\"3371 (BC_2, *, internal, X),\" &\n\t\"3372 (BC_2, *, internal, X),\" &\n\t\"3373 (BC_2, *, internal, X),\" &\n\t\"3374 (BC_2, *, internal, X),\" &\n\t\"3375 (BC_2, *, internal, X),\" &\n\t\"3376 (BC_2, *, internal, X),\" &\n\t\"3377 (BC_2, *, internal, X),\" &\n\t\"3378 (BC_2, *, internal, X),\" &\n\t\"3379 (BC_2, *, internal, X),\" &\n\t\"3380 (BC_2, *, internal, X),\" &\n\t\"3381 (BC_2, *, internal, X),\" &\n\t\"3382 (BC_2, *, internal, X),\" &\n\t\"3383 (BC_2, *, internal, X),\" &\n\t\"3384 (BC_2, *, internal, X),\" &\n\t\"3385 (BC_2, *, internal, X),\" &\n\t\"3386 (BC_2, *, internal, X),\" &\n\t\"3387 (BC_2, *, internal, X),\" &\n\t\"3388 (BC_2, *, internal, X)\";\n\n\n-- Advanced I/O Description\n\nattribute AIO_COMPONENT_CONFORMANCE of XC7VX690T_FFG1761 : entity is\n\t\"STD_1149_6_2003\";\n\nattribute AIO_EXTEST_Pulse_Execution of XC7VX690T_FFG1761 : entity is\n\t\"Wait_Duration TCK 15\";\n\nattribute AIO_EXTEST_Train_Execution of XC7VX690T_FFG1761 : entity is\n\t\"train 30, maximum_time 120.0e-6\";\n\nattribute AIO_Pin_Behavior of XC7VX690T_FFG1761 : entity is\n\"MGTHRXP0_111 : LP_time=22.5e-9 HP_time=45.0e-9; \" &\n\"MGTHRXP0_112 : LP_time=22.5e-9 HP_time=45.0e-9; \" &\n\"MGTHRXP0_113 : LP_time=22.5e-9 HP_time=45.0e-9; \" &\n\"MGTHRXP0_114 : LP_time=22.5e-9 HP_time=45.0e-9; \" &\n\"MGTHRXP0_115 : LP_time=22.5e-9 HP_time=45.0e-9; \" &\n\"MGTHRXP0_116 : LP_time=22.5e-9 HP_time=45.0e-9; \" &\n\"MGTHRXP0_117 : LP_time=22.5e-9 HP_time=45.0e-9; \" &\n\"MGTHRXP0_118 : LP_time=22.5e-9 HP_time=45.0e-9; \" &\n\"MGTHRXP0_119 : LP_time=22.5e-9 HP_time=45.0e-9; \" &\n\"MGTHRXP1_111 : LP_time=22.5e-9 HP_time=45.0e-9; \" &\n\"MGTHRXP1_112 : LP_time=22.5e-9 HP_time=45.0e-9; \" &\n\"MGTHRXP1_113 : LP_time=22.5e-9 HP_time=45.0e-9; \" &\n\"MGTHRXP1_114 : LP_time=22.5e-9 HP_time=45.0e-9; \" &\n\"MGTHRXP1_115 : LP_time=22.5e-9 HP_time=45.0e-9; \" &\n\"MGTHRXP1_116 : LP_time=22.5e-9 HP_time=45.0e-9; \" &\n\"MGTHRXP1_117 : LP_time=22.5e-9 HP_time=45.0e-9; \" &\n\"MGTHRXP1_118 : LP_time=22.5e-9 HP_time=45.0e-9; \" &\n\"MGTHRXP1_119 : LP_time=22.5e-9 HP_time=45.0e-9; \" &\n\"MGTHRXP2_111 : LP_time=22.5e-9 HP_time=45.0e-9; \" &\n\"MGTHRXP2_112 : LP_time=22.5e-9 HP_time=45.0e-9; \" &\n\"MGTHRXP2_113 : LP_time=22.5e-9 HP_time=45.0e-9; \" &\n\"MGTHRXP2_114 : LP_time=22.5e-9 HP_time=45.0e-9; \" &\n\"MGTHRXP2_115 : LP_time=22.5e-9 HP_time=45.0e-9; \" &\n\"MGTHRXP2_116 : LP_time=22.5e-9 HP_time=45.0e-9; \" &\n\"MGTHRXP2_117 : LP_time=22.5e-9 HP_time=45.0e-9; \" &\n\"MGTHRXP2_118 : LP_time=22.5e-9 HP_time=45.0e-9; \" &\n\"MGTHRXP2_119 : LP_time=22.5e-9 HP_time=45.0e-9; \" &\n\"MGTHRXP3_111 : LP_time=22.5e-9 HP_time=45.0e-9; \" &\n\"MGTHRXP3_112 : LP_time=22.5e-9 HP_time=45.0e-9; \" &\n\"MGTHRXP3_113 : LP_time=22.5e-9 HP_time=45.0e-9; \" &\n\"MGTHRXP3_114 : LP_time=22.5e-9 HP_time=45.0e-9; \" &\n\"MGTHRXP3_115 : LP_time=22.5e-9 HP_time=45.0e-9; \" &\n\"MGTHRXP3_116 : LP_time=22.5e-9 HP_time=45.0e-9; \" &\n\"MGTHRXP3_117 : LP_time=22.5e-9 HP_time=45.0e-9; \" &\n\"MGTHRXP3_118 : LP_time=22.5e-9 HP_time=45.0e-9; \" &\n\"MGTHRXP3_119 : LP_time=22.5e-9 HP_time=45.0e-9; \" &\n\"MGTHTXP0_111; \" &\n\"MGTHTXP0_112; \" &\n\"MGTHTXP0_113; \" &\n\"MGTHTXP0_114; \" &\n\"MGTHTXP0_115; \" &\n\"MGTHTXP0_116; \" &\n\"MGTHTXP0_117; \" &\n\"MGTHTXP0_118; \" &\n\"MGTHTXP0_119; \" &\n\"MGTHTXP1_111; \" &\n\"MGTHTXP1_112; \" &\n\"MGTHTXP1_113; \" &\n\"MGTHTXP1_114; \" &\n\"MGTHTXP1_115; \" &\n\"MGTHTXP1_116; \" &\n\"MGTHTXP1_117; \" &\n\"MGTHTXP1_118; \" &\n\"MGTHTXP1_119; \" &\n\"MGTHTXP2_111; \" &\n\"MGTHTXP2_112; \" &\n\"MGTHTXP2_113; \" &\n\"MGTHTXP2_114; \" &\n\"MGTHTXP2_115; \" &\n\"MGTHTXP2_116; \" &\n\"MGTHTXP2_117; \" &\n\"MGTHTXP2_118; \" &\n\"MGTHTXP2_119; \" &\n\"MGTHTXP3_111; \" &\n\"MGTHTXP3_112; \" &\n\"MGTHTXP3_113; \" &\n\"MGTHTXP3_114; \" &\n\"MGTHTXP3_115; \" &\n\"MGTHTXP3_116; \" &\n\"MGTHTXP3_117; \" &\n\"MGTHTXP3_118; \" &\n\"MGTHTXP3_119 \";\n\n-- Design Warning Section\n\nattribute DESIGN_WARNING of XC7VX690T_FFG1761 : entity is\n\t\"When no bitstream is loaded and GTPs are not instantiated,\" &\n\t\t\"the boundary-scan cells associated with GTPs will not\" &\n\t\t\"capture correct state information.  To model the boundary-\" &\n\t\t\"scan cell behavior correctly post-configuration, use\" &\n\t\t\"BSDLanno to modify the BSDL file.\" &\n        \"This BSDL file must be modified by the FPGA designer in order to\" &\n                \"reflect post-configuration behavior (if any).\" &\n        \"To avoid losing the current configuration, the boundary scan\" &\n                \"test vectors should keep the PROGRAM_B pin\" &\n                \"high.  If the PROGRAM_B pin goes low by any means,\" &\n                \"the configuration will be cleared.\" &\n        \"PROGRAM_B can only be captured, not updated.\" &\n                \"The value at the pin is always used by the device.\" &\n        \"In EXTEST, output and tristate values are not captured in the\" &\n                \"Capture-DR state - those register cells are unchanged.\" &\n\t\"Differential Serial IO pins do not support INTEST.\" &\n        \"In INTEST, the pin input values are not captured in the\" &\n                \"Capture-DR state - those register cells are unchanged.\" &\n        \"The output and tristate capture values are not valid until after\" &\n                \"the device is configured.\" &\n        \"The tristate control value is not captured properly when\" &\n                \"GTS is activated.\" &\n\t\"The IEEE Std 1149.6 EXTEST_PULSE and EXTEST_TRAIN instructions\" &\n\t\t\"require a minimum TCK freq of 15 MHz and min temp of 0C.\" &\n\t\"NOCONNECT pins should not be connected to any supply\" &\n\t\t\"or GND.  They should be left floating.\";\n\nend XC7VX690T_FFG1761;\n\n"
  },
  {
    "path": "jtag/bsd/xc7z020_clg484.bsd",
    "content": "-- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.\n--\n-- This file contains confidential and proprietary information\n-- of Xilinx, Inc. and is protected under U.S. and\n-- international copyright and other intellectual property\n-- laws.\n--\n-- DISCLAIMER\n-- This disclaimer is not a license and does not grant any\n-- rights to the materials distributed herewith. Except as\n-- otherwise provided in a valid license issued to you by\n-- Xilinx, and to the maximum extent permitted by applicable\n-- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n-- (2) Xilinx shall not be liable (whether in contract or tort,\n-- including negligence, or under any other theory of \n-- liability) for any loss or damage of any kind or nature\n-- releated to, arising under or in connection with these\n-- materials, including for any direct, or any indirect,\n-- special, incidental, or consequential loss or damage\n-- (including loss of data, profits, goodwill, or any type of\n-- loss or damage suffered as a result of any action brought\n-- by a third party) even if such damage or loss was\n-- reasonably foreseeable or Xilinx had been advised of the\n-- possibility of the same.\n--\n-- CRITICAL APPLICATIONS\n-- Xilinx products are not designed or intended to be fail-\n-- safe, or for use in any application requiring fail-safe\n-- performance, such as life-support or safety devices or\n-- systems, Class III medical devices, nuclear facilities,\n-- applications related to the deployment of airbags, or any\n-- other applications that could lead to death, personal\n-- injury, or severe property or environmental damage\n-- (individually and collectively, \"Critical\n-- Applications\"). Customer assumes the sole risk and\n-- liability of any use of Xilinx products in Critical\n-- Applications, subject only to applicable laws and\n-- regulations governing limitiations on product liability.\n--\n-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n-- PART OF THIS FILE AT ALL TIMES.\n--\n-- BSDL file for device XC7Z020, package CLG484\n-- Generated by bsdlnet Version 1.10\n-- Generated on Fri Apr 06, 2012  09:30:32 IST\n-- Generated using schematic at v32_top/xc7z020/schematic\n-- Schematic date = 2011-08-03 17:24:25\n-- Schematic ICM_VARIANT = 28t_n1\n-- Package File date = # Date    : 2011-09-22 10:22:08\n------------------------------------------------------------------------\n-- Modification History\n-- | CR # N/A\n-- | Details -  Initial Release\n------------------------------------------------------------------------\n--\n-- For technical support, http://support.xilinx.com -> enter text 'bsdl'\n-- in the text search box at the left of the page.  If none of\n-- these records resolve your problem you should open a web support case\n-- or contact our technical support at:\n--\n--\tNorth America\t1-800-255-7778\t\thotline@xilinx.com\n--\tUnited Kingdom\t+44 870 7350 610\teurosupport@xilinx.com\n--\tFrance\t\t(33) 1 3463 0100\teurosupport@xilinx.com\n--\tGermany\t\t(49) 89 991 54930\teurosupport@xilinx.com\n--\tJapan\t\t(81) 3-3297-9163\tjhotline@xilinx.com\n--\n-- This BSDL file reflects the pre-configuration JTAG behavior. To reflect\n-- the post-configuration JTAG behavior (if any), edit this file as described\n-- below. Many of these changes are demonstrated by commented-out template\n-- lines preceeding the lines they would replace:\n--\n-- 1. Enable USER instructions as appropriate (see below).\n-- 2. Set disable result of all pads as configured.\n-- 3. Set safe state of boundary cells as necessary.\n-- 4. Rename entity if necessary to avoid name collisions.\n-- 5. Modify USERCODE value in USERCODE_REGISTER declaration.\n--\n-- To prevent losing the current configuration, the boundary scan\n-- test vectors should keep the PROGRAM_B pin high.\n--\n-- PROGRAM_B can only be captured, not updated.  The value\n-- at the pin is always used by the device.\n--\n-- All IOBs prior to configuration, and unused and output-only IOBs following\n-- configuration, will sense their pad values during boundary-scan with an CMOS\n-- input buffer. In order to properly capture a logic high value at one\n-- of these IOBs into its input boundary scan cell, please refer to the\n-- datasheet and user guide for proper input levels.\n--\n-- For post-configuration boundary scan only: If an IOB is configured to use\n-- an input standard that uses VREF pins, then the boundary scan test vectors\n-- must keep the used VREF pins 3-stated.\n\n----------------------------------\n\n-- BSDL File for P1149.6 Standard.\n\n----------------------------------\n-- ----------------------------------------------------------------------\n-- This BSDL file has been checked and verified by JTAG Technologies B.V.\n-- on 2012-04-09, for syntactical and semantic compliance with\n-- IEEE standards 1149.1 and 1149.6\n-- using bsdl32.dll 1.6.1.5 - 20110523 Win32\n-- copyright (c) 2009 JTAG Technologies B.V., All rights reserved\n-- ----------------------------------------------------------------------\n\nentity XC7Z020_CLG484 is\n\n-- Generic Parameter\n\ngeneric (PHYSICAL_PIN_MAP : string := \"CLG484\" );\n\n-- Logical Port Description\n\nport (\n\tRSVDGND_G10: inout bit; --  RSVDGND_0\n\tCFGBVS_T13: in bit; --  CFGBVS_0\n\tDONE_T12: inout bit; --  DONE_0\n\tGND: linkage bit_vector (1 to 63);\n\tGNDADC_0: linkage bit;\n\tINIT_B_T14: inout bit; --  INIT_B_0\n\tRSVD0VCC_T10: in bit; --  RSVD0VCC_0\n\tRSVD1VCC_T8: in bit; --  RSVD1VCC_0\n\tRSVD2VCC_T7: in bit; --  RSVD2VCC_0\n\tPROGRAM_B: in bit; --  PROGRAM_B_0\n\tPS_CLK: in bit;\n\tPS_DDR_A0: inout bit;\n\tPS_DDR_A1: inout bit;\n\tPS_DDR_A10: inout bit;\n\tPS_DDR_A11: inout bit;\n\tPS_DDR_A12: inout bit;\n\tPS_DDR_A13: inout bit;\n\tPS_DDR_A14: inout bit;\n\tPS_DDR_A2: inout bit;\n\tPS_DDR_A3: inout bit;\n\tPS_DDR_A4: inout bit;\n\tPS_DDR_A5: inout bit;\n\tPS_DDR_A6: inout bit;\n\tPS_DDR_A7: inout bit;\n\tPS_DDR_A8: inout bit;\n\tPS_DDR_A9: inout bit;\n\tPS_DDR_BA0: inout bit;\n\tPS_DDR_BA1: inout bit;\n\tPS_DDR_BA2: inout bit;\n\tPS_DDR_CAS_B: inout bit;\n\tPS_DDR_CKE: inout bit;\n\tPS_DDR_CKN: inout bit;\n\tPS_DDR_CKP: inout bit;\n\tPS_DDR_CS_B: inout bit;\n\tPS_DDR_DM0: inout bit;\n\tPS_DDR_DM1: inout bit;\n\tPS_DDR_DM2: inout bit;\n\tPS_DDR_DM3: inout bit;\n\tPS_DDR_DQ0: inout bit;\n\tPS_DDR_DQ1: inout bit;\n\tPS_DDR_DQ10: inout bit;\n\tPS_DDR_DQ11: inout bit;\n\tPS_DDR_DQ12: inout bit;\n\tPS_DDR_DQ13: inout bit;\n\tPS_DDR_DQ14: inout bit;\n\tPS_DDR_DQ15: inout bit;\n\tPS_DDR_DQ16: inout bit;\n\tPS_DDR_DQ17: inout bit;\n\tPS_DDR_DQ18: inout bit;\n\tPS_DDR_DQ19: inout bit;\n\tPS_DDR_DQ2: inout bit;\n\tPS_DDR_DQ20: inout bit;\n\tPS_DDR_DQ21: inout bit;\n\tPS_DDR_DQ22: inout bit;\n\tPS_DDR_DQ23: inout bit;\n\tPS_DDR_DQ24: inout bit;\n\tPS_DDR_DQ25: inout bit;\n\tPS_DDR_DQ26: inout bit;\n\tPS_DDR_DQ27: inout bit;\n\tPS_DDR_DQ28: inout bit;\n\tPS_DDR_DQ29: inout bit;\n\tPS_DDR_DQ3: inout bit;\n\tPS_DDR_DQ30: inout bit;\n\tPS_DDR_DQ31: inout bit;\n\tPS_DDR_DQ4: inout bit;\n\tPS_DDR_DQ5: inout bit;\n\tPS_DDR_DQ6: inout bit;\n\tPS_DDR_DQ7: inout bit;\n\tPS_DDR_DQ8: inout bit;\n\tPS_DDR_DQ9: inout bit;\n\tPS_DDR_DQS_N0: inout bit;\n\tPS_DDR_DQS_N1: inout bit;\n\tPS_DDR_DQS_N2: inout bit;\n\tPS_DDR_DQS_N3: inout bit;\n\tPS_DDR_DQS_P0: inout bit;\n\tPS_DDR_DQS_P1: inout bit;\n\tPS_DDR_DQS_P2: inout bit;\n\tPS_DDR_DQS_P3: inout bit;\n\tPS_DDR_DRST_B: inout bit;\n\tPS_DDR_ODT: inout bit;\n\tPS_DDR_RAS_B: inout bit;\n\tPS_DDR_VREF0_502: linkage bit;\n\tPS_DDR_VREF1_502: linkage bit;\n\tPS_DDR_VRN: inout bit;\n\tPS_DDR_VRP: inout bit;\n\tPS_DDR_WE_B: inout bit;\n\tPS_MIO0: inout bit;\n\tPS_MIO1: inout bit;\n\tPS_MIO10: inout bit;\n\tPS_MIO11: inout bit;\n\tPS_MIO12: inout bit;\n\tPS_MIO13: inout bit;\n\tPS_MIO14: inout bit;\n\tPS_MIO15: inout bit;\n\tPS_MIO16: inout bit;\n\tPS_MIO17: inout bit;\n\tPS_MIO18: inout bit;\n\tPS_MIO19: inout bit;\n\tPS_MIO2: inout bit;\n\tPS_MIO20: inout bit;\n\tPS_MIO21: inout bit;\n\tPS_MIO22: inout bit;\n\tPS_MIO23: inout bit;\n\tPS_MIO24: inout bit;\n\tPS_MIO25: inout bit;\n\tPS_MIO26: inout bit;\n\tPS_MIO27: inout bit;\n\tPS_MIO28: inout bit;\n\tPS_MIO29: inout bit;\n\tPS_MIO3: inout bit;\n\tPS_MIO30: inout bit;\n\tPS_MIO31: inout bit;\n\tPS_MIO32: inout bit;\n\tPS_MIO33: inout bit;\n\tPS_MIO34: inout bit;\n\tPS_MIO35: inout bit;\n\tPS_MIO36: inout bit;\n\tPS_MIO37: inout bit;\n\tPS_MIO38: inout bit;\n\tPS_MIO39: inout bit;\n\tPS_MIO4: inout bit;\n\tPS_MIO40: inout bit;\n\tPS_MIO41: inout bit;\n\tPS_MIO42: inout bit;\n\tPS_MIO43: inout bit;\n\tPS_MIO44: inout bit;\n\tPS_MIO45: inout bit;\n\tPS_MIO46: inout bit;\n\tPS_MIO47: inout bit;\n\tPS_MIO48: inout bit;\n\tPS_MIO49: inout bit;\n\tPS_MIO5: inout bit;\n\tPS_MIO50: inout bit;\n\tPS_MIO51: inout bit;\n\tPS_MIO52: inout bit;\n\tPS_MIO53: inout bit;\n\tPS_MIO6: inout bit;\n\tPS_MIO7: inout bit;\n\tPS_MIO8: inout bit;\n\tPS_MIO9: inout bit;\n\tPS_MIO_VREF: in bit;\n\tPS_POR_B: in bit;\n\tPS_SRST_B: in bit;\n\tTCK: in bit; --  TCK_0\n\tTDI: in bit; --  TDI_0\n\tTDN_N12: linkage bit; --  DXN_0\n\tTDO: out bit; --  TDO_0\n\tTDP_N11: linkage bit; --  DXP_0\n\tTMS: in bit; --  TMS_0\n\tVCCADC_0: linkage bit;\n\tVCCAUX: linkage bit_vector (1 to 4);\n\tVCCBATT_0: linkage bit;\n\tVCCBRAM: linkage bit_vector (1 to 2);\n\tVCCINT: linkage bit_vector (1 to 8);\n\tVCCO_0: linkage bit;\n\tVCCO_13: linkage bit_vector (1 to 7);\n\tVCCO_33: linkage bit_vector (1 to 6);\n\tVCCO_34: linkage bit_vector (1 to 6);\n\tVCCO_35: linkage bit_vector (1 to 7);\n\tVCCO_DDR_502: linkage bit_vector (1 to 9);\n\tVCCO_MIO0_500: linkage bit_vector (1 to 2);\n\tVCCO_MIO1_501: linkage bit_vector (1 to 4);\n\tVCCPAUX: linkage bit_vector (1 to 4);\n\tVCCPINT: linkage bit_vector (1 to 6);\n\tVCCPLL: linkage bit;\n\tVN_M12: linkage bit; --  VN_0\n\tVP_L11: linkage bit; --  VP_0\n\tVREFN_L12: linkage bit; --  VREFN_0\n\tVREFP_M11: linkage bit; --  VREFP_0\n\tIO_A16: inout bit; --  PAD68\n\tIO_A17: inout bit; --  PAD69\n\tIO_A18: inout bit; --  PAD70\n\tIO_A19: inout bit; --  PAD71\n\tIO_A21: inout bit; --  PAD80\n\tIO_A22: inout bit; --  PAD81\n\tIO_B15: inout bit; --  PAD65\n\tIO_B16: inout bit; --  PAD66\n\tIO_B17: inout bit; --  PAD67\n\tIO_B19: inout bit; --  PAD76\n\tIO_B20: inout bit; --  PAD77\n\tIO_B21: inout bit; --  PAD86\n\tIO_B22: inout bit; --  PAD87\n\tIO_C15: inout bit; --  PAD64\n\tIO_C17: inout bit; --  PAD72\n\tIO_C18: inout bit; --  PAD73\n\tIO_C19: inout bit; --  PAD75\n\tIO_C20: inout bit; --  PAD79\n\tIO_C22: inout bit; --  PAD83\n\tIO_D15: inout bit; --  PAD57\n\tIO_D16: inout bit; --  PAD54\n\tIO_D17: inout bit; --  PAD55\n\tIO_D18: inout bit; --  PAD74\n\tIO_D20: inout bit; --  PAD78\n\tIO_D21: inout bit; --  PAD85\n\tIO_D22: inout bit; --  PAD82\n\tIO_E15: inout bit; --  PAD56\n\tIO_E16: inout bit; --  PAD53\n\tIO_E18: inout bit; --  PAD61\n\tIO_E19: inout bit; --  PAD92\n\tIO_E20: inout bit; --  PAD93\n\tIO_E21: inout bit; --  PAD84\n\tIO_F16: inout bit; --  PAD52\n\tIO_F17: inout bit; --  PAD63\n\tIO_F18: inout bit; --  PAD60\n\tIO_F19: inout bit; --  PAD91\n\tIO_F21: inout bit; --  PAD96\n\tIO_F22: inout bit; --  PAD97\n\tIO_G15: inout bit; --  PAD58\n\tIO_G16: inout bit; --  PAD59\n\tIO_G17: inout bit; --  PAD62\n\tIO_G19: inout bit; --  PAD90\n\tIO_G20: inout bit; --  PAD94\n\tIO_G21: inout bit; --  PAD95\n\tIO_G22: inout bit; --  PAD99\n\tIO_H15: inout bit; --  PAD101\n\tIO_H17: inout bit; --  PAD51\n\tIO_H18: inout bit; --  PAD100\n\tIO_H19: inout bit; --  PAD88\n\tIO_H20: inout bit; --  PAD89\n\tIO_H22: inout bit; --  PAD98\n\tIO_J15: inout bit; --  PAD102\n\tIO_J16: inout bit; --  PAD104\n\tIO_J17: inout bit; --  PAD105\n\tIO_J18: inout bit; --  PAD114\n\tIO_J20: inout bit; --  PAD118\n\tIO_J21: inout bit; --  PAD116\n\tIO_J22: inout bit; --  PAD117\n\tIO_K15: inout bit; --  PAD103\n\tIO_K16: inout bit; --  PAD106\n\tIO_K18: inout bit; --  PAD115\n\tIO_K19: inout bit; --  PAD122\n\tIO_K20: inout bit; --  PAD123\n\tIO_K21: inout bit; --  PAD119\n\tIO_L16: inout bit; --  PAD107\n\tIO_L17: inout bit; --  PAD108\n\tIO_L18: inout bit; --  PAD124\n\tIO_L19: inout bit; --  PAD125\n\tIO_L21: inout bit; --  PAD120\n\tIO_L22: inout bit; --  PAD121\n\tIO_M15: inout bit; --  PAD112\n\tIO_M16: inout bit; --  PAD113\n\tIO_M17: inout bit; --  PAD109\n\tIO_M19: inout bit; --  PAD126\n\tIO_M20: inout bit; --  PAD127\n\tIO_M21: inout bit; --  PAD130\n\tIO_M22: inout bit; --  PAD131\n\tIO_N15: inout bit; --  PAD138\n\tIO_N17: inout bit; --  PAD110\n\tIO_N18: inout bit; --  PAD111\n\tIO_N19: inout bit; --  PAD128\n\tIO_N20: inout bit; --  PAD129\n\tIO_N22: inout bit; --  PAD132\n\tIO_P15: inout bit; --  PAD139\n\tIO_P16: inout bit; --  PAD148\n\tIO_P17: inout bit; --  PAD140\n\tIO_P18: inout bit; --  PAD141\n\tIO_P20: inout bit; --  PAD136\n\tIO_P21: inout bit; --  PAD137\n\tIO_P22: inout bit; --  PAD133\n\tIO_R6: inout bit; --  PAD38\n\tIO_R7: inout bit; --  PAD1\n\tIO_R15: inout bit; --  PAD150\n\tIO_R16: inout bit; --  PAD149\n\tIO_R18: inout bit; --  PAD146\n\tIO_R19: inout bit; --  PAD144\n\tIO_R20: inout bit; --  PAD134\n\tIO_R21: inout bit; --  PAD135\n\tIO_T4: inout bit; --  PAD40\n\tIO_T6: inout bit; --  PAD39\n\tIO_T16: inout bit; --  PAD142\n\tIO_T17: inout bit; --  PAD143\n\tIO_T18: inout bit; --  PAD147\n\tIO_T19: inout bit; --  PAD145\n\tIO_T21: inout bit; --  PAD152\n\tIO_T22: inout bit; --  PAD154\n\tIO_U4: inout bit; --  PAD41\n\tIO_U5: inout bit; --  PAD45\n\tIO_U6: inout bit; --  PAD44\n\tIO_U7: inout bit; --  PAD50\n\tIO_U9: inout bit; --  PAD13\n\tIO_U10: inout bit; --  PAD12\n\tIO_U11: inout bit; --  PAD11\n\tIO_U12: inout bit; --  PAD10\n\tIO_U14: inout bit; --  PAD200\n\tIO_U15: inout bit; --  PAD180\n\tIO_U16: inout bit; --  PAD181\n\tIO_U17: inout bit; --  PAD182\n\tIO_U19: inout bit; --  PAD151\n\tIO_U20: inout bit; --  PAD160\n\tIO_U21: inout bit; --  PAD153\n\tIO_U22: inout bit; --  PAD155\n\tIO_V4: inout bit; --  PAD43\n\tIO_V5: inout bit; --  PAD42\n\tIO_V7: inout bit; --  PAD46\n\tIO_V8: inout bit; --  PAD4\n\tIO_V9: inout bit; --  PAD3\n\tIO_V10: inout bit; --  PAD2\n\tIO_V12: inout bit; --  PAD8\n\tIO_V13: inout bit; --  PAD190\n\tIO_V14: inout bit; --  PAD188\n\tIO_V15: inout bit; --  PAD189\n\tIO_V17: inout bit; --  PAD183\n\tIO_V18: inout bit; --  PAD162\n\tIO_V19: inout bit; --  PAD163\n\tIO_V20: inout bit; --  PAD161\n\tIO_V22: inout bit; --  PAD156\n\tIO_W5: inout bit; --  PAD49\n\tIO_W6: inout bit; --  PAD48\n\tIO_W7: inout bit; --  PAD47\n\tIO_W8: inout bit; --  PAD5\n\tIO_W10: inout bit; --  PAD7\n\tIO_W11: inout bit; --  PAD6\n\tIO_W12: inout bit; --  PAD9\n\tIO_W13: inout bit; --  PAD191\n\tIO_W15: inout bit; --  PAD192\n\tIO_W16: inout bit; --  PAD178\n\tIO_W17: inout bit; --  PAD176\n\tIO_W18: inout bit; --  PAD177\n\tIO_W20: inout bit; --  PAD158\n\tIO_W21: inout bit; --  PAD159\n\tIO_W22: inout bit; --  PAD157\n\tIO_Y4: inout bit; --  PAD36\n\tIO_Y5: inout bit; --  PAD27\n\tIO_Y6: inout bit; --  PAD26\n\tIO_Y8: inout bit; --  PAD25\n\tIO_Y9: inout bit; --  PAD24\n\tIO_Y10: inout bit; --  PAD21\n\tIO_Y11: inout bit; --  PAD20\n\tIO_Y13: inout bit; --  PAD196\n\tIO_Y14: inout bit; --  PAD194\n\tIO_Y15: inout bit; --  PAD193\n\tIO_Y16: inout bit; --  PAD179\n\tIO_Y18: inout bit; --  PAD174\n\tIO_Y19: inout bit; --  PAD172\n\tIO_Y20: inout bit; --  PAD168\n\tIO_Y21: inout bit; --  PAD169\n\tIO_AA4: inout bit; --  PAD37\n\tIO_AA6: inout bit; --  PAD29\n\tIO_AA7: inout bit; --  PAD28\n\tIO_AA8: inout bit; --  PAD23\n\tIO_AA9: inout bit; --  PAD22\n\tIO_AA11: inout bit; --  PAD16\n\tIO_AA12: inout bit; --  PAD14\n\tIO_AA13: inout bit; --  PAD197\n\tIO_AA14: inout bit; --  PAD195\n\tIO_AA16: inout bit; --  PAD186\n\tIO_AA17: inout bit; --  PAD184\n\tIO_AA18: inout bit; --  PAD175\n\tIO_AA19: inout bit; --  PAD173\n\tIO_AA21: inout bit; --  PAD166\n\tIO_AA22: inout bit; --  PAD164\n\tIO_AB1: inout bit; --  PAD31\n\tIO_AB2: inout bit; --  PAD30\n\tIO_AB4: inout bit; --  PAD33\n\tIO_AB5: inout bit; --  PAD32\n\tIO_AB6: inout bit; --  PAD35\n\tIO_AB7: inout bit; --  PAD34\n\tIO_AB9: inout bit; --  PAD19\n\tIO_AB10: inout bit; --  PAD18\n\tIO_AB11: inout bit; --  PAD17\n\tIO_AB12: inout bit; --  PAD15\n\tIO_AB14: inout bit; --  PAD198\n\tIO_AB15: inout bit; --  PAD199\n\tIO_AB16: inout bit; --  PAD187\n\tIO_AB17: inout bit; --  PAD185\n\tIO_AB19: inout bit; --  PAD170\n\tIO_AB20: inout bit; --  PAD171\n\tIO_AB21: inout bit; --  PAD167\n\tIO_AB22: inout bit --  PAD165\n); --end port list\n\n-- Use Statements\n\nuse STD_1149_1_2001.all;\nuse STD_1149_6_2003.all;\n\n-- Component Conformance Statement(s)\n\nattribute COMPONENT_CONFORMANCE of XC7Z020_CLG484 : entity is\n\t\"STD_1149_1_2001\";\n\n-- Device Package Pin Mappings\n\nattribute PIN_MAP of XC7Z020_CLG484 : entity is PHYSICAL_PIN_MAP;\n\nconstant CLG484: PIN_MAP_STRING:=\n\t\"RSVDGND_G10:G10,\" &\n\t\"CFGBVS_T13:T13,\" &\n\t\"DONE_T12:T12,\" &\n\t\"GND:(A5,A15,B8,B18,C1,C11,C21,D4,D14,E7,\" &\n\t\t\"E17,F10,F20,G3,H6,H8,H12,H14,H16,J9,\" &\n\t\t\"J11,J13,J19,K2,K8,K10,K14,K22,L5,L9,\" &\n\t\t\"L13,L15,M8,M10,M14,M18,N1,N9,N13,N21,\" &\n\t\t\"P4,P8,P10,P12,P14,R9,R11,R13,R17,T20,\" &\n\t\t\"U3,U13,V6,V16,W9,W19,Y2,Y12,Y22,AA5,\" &\n\t\t\"AA15,AB8,AB18),\" &\n\t\"GNDADC_0:K12,\" &\n\t\"INIT_B_T14:T14,\" &\n\t\"RSVD0VCC_T10:T10,\" &\n\t\"RSVD1VCC_T8:T8,\" &\n\t\"RSVD2VCC_T7:T7,\" &\n\t\"PROGRAM_B:T11,\" &\n\t\"PS_CLK:F7,\" &\n\t\"PS_DDR_A0:M4,\" &\n\t\"PS_DDR_A1:M5,\" &\n\t\"PS_DDR_A10:J3,\" &\n\t\"PS_DDR_A11:G5,\" &\n\t\"PS_DDR_A12:H4,\" &\n\t\"PS_DDR_A13:F4,\" &\n\t\"PS_DDR_A14:G4,\" &\n\t\"PS_DDR_A2:K4,\" &\n\t\"PS_DDR_A3:L4,\" &\n\t\"PS_DDR_A4:K6,\" &\n\t\"PS_DDR_A5:K5,\" &\n\t\"PS_DDR_A6:J7,\" &\n\t\"PS_DDR_A7:J6,\" &\n\t\"PS_DDR_A8:J5,\" &\n\t\"PS_DDR_A9:H5,\" &\n\t\"PS_DDR_BA0:L7,\" &\n\t\"PS_DDR_BA1:L6,\" &\n\t\"PS_DDR_BA2:M6,\" &\n\t\"PS_DDR_CAS_B:P3,\" &\n\t\"PS_DDR_CKE:V3,\" &\n\t\"PS_DDR_CKN:N5,\" &\n\t\"PS_DDR_CKP:N4,\" &\n\t\"PS_DDR_CS_B:P6,\" &\n\t\"PS_DDR_DM0:B1,\" &\n\t\"PS_DDR_DM1:H3,\" &\n\t\"PS_DDR_DM2:P1,\" &\n\t\"PS_DDR_DM3:AA2,\" &\n\t\"PS_DDR_DQ0:D1,\" &\n\t\"PS_DDR_DQ1:C3,\" &\n\t\"PS_DDR_DQ10:L1,\" &\n\t\"PS_DDR_DQ11:L2,\" &\n\t\"PS_DDR_DQ12:L3,\" &\n\t\"PS_DDR_DQ13:K1,\" &\n\t\"PS_DDR_DQ14:J1,\" &\n\t\"PS_DDR_DQ15:K3,\" &\n\t\"PS_DDR_DQ16:M1,\" &\n\t\"PS_DDR_DQ17:T3,\" &\n\t\"PS_DDR_DQ18:N3,\" &\n\t\"PS_DDR_DQ19:T1,\" &\n\t\"PS_DDR_DQ2:B2,\" &\n\t\"PS_DDR_DQ20:R3,\" &\n\t\"PS_DDR_DQ21:T2,\" &\n\t\"PS_DDR_DQ22:M2,\" &\n\t\"PS_DDR_DQ23:R1,\" &\n\t\"PS_DDR_DQ24:AA3,\" &\n\t\"PS_DDR_DQ25:U1,\" &\n\t\"PS_DDR_DQ26:AA1,\" &\n\t\"PS_DDR_DQ27:U2,\" &\n\t\"PS_DDR_DQ28:W1,\" &\n\t\"PS_DDR_DQ29:Y3,\" &\n\t\"PS_DDR_DQ3:D3,\" &\n\t\"PS_DDR_DQ30:W3,\" &\n\t\"PS_DDR_DQ31:Y1,\" &\n\t\"PS_DDR_DQ4:E3,\" &\n\t\"PS_DDR_DQ5:E1,\" &\n\t\"PS_DDR_DQ6:F2,\" &\n\t\"PS_DDR_DQ7:F1,\" &\n\t\"PS_DDR_DQ8:G2,\" &\n\t\"PS_DDR_DQ9:G1,\" &\n\t\"PS_DDR_DQS_N0:D2,\" &\n\t\"PS_DDR_DQS_N1:J2,\" &\n\t\"PS_DDR_DQS_N2:P2,\" &\n\t\"PS_DDR_DQS_N3:W2,\" &\n\t\"PS_DDR_DQS_P0:C2,\" &\n\t\"PS_DDR_DQS_P1:H2,\" &\n\t\"PS_DDR_DQS_P2:N2,\" &\n\t\"PS_DDR_DQS_P3:V2,\" &\n\t\"PS_DDR_DRST_B:F3,\" &\n\t\"PS_DDR_ODT:P5,\" &\n\t\"PS_DDR_RAS_B:R5,\" &\n\t\"PS_DDR_VREF0_502:H7,\" &\n\t\"PS_DDR_VREF1_502:P7,\" &\n\t\"PS_DDR_VRN:M7,\" &\n\t\"PS_DDR_VRP:N7,\" &\n\t\"PS_DDR_WE_B:R4,\" &\n\t\"PS_MIO0:G6,\" &\n\t\"PS_MIO1:A1,\" &\n\t\"PS_MIO10:G7,\" &\n\t\"PS_MIO11:B4,\" &\n\t\"PS_MIO12:C5,\" &\n\t\"PS_MIO13:A6,\" &\n\t\"PS_MIO14:B6,\" &\n\t\"PS_MIO15:E6,\" &\n\t\"PS_MIO16:D6,\" &\n\t\"PS_MIO17:E9,\" &\n\t\"PS_MIO18:A7,\" &\n\t\"PS_MIO19:E10,\" &\n\t\"PS_MIO2:A2,\" &\n\t\"PS_MIO20:A8,\" &\n\t\"PS_MIO21:F11,\" &\n\t\"PS_MIO22:A14,\" &\n\t\"PS_MIO23:E11,\" &\n\t\"PS_MIO24:B7,\" &\n\t\"PS_MIO25:F12,\" &\n\t\"PS_MIO26:A13,\" &\n\t\"PS_MIO27:D7,\" &\n\t\"PS_MIO28:A12,\" &\n\t\"PS_MIO29:E8,\" &\n\t\"PS_MIO3:F6,\" &\n\t\"PS_MIO30:A11,\" &\n\t\"PS_MIO31:F9,\" &\n\t\"PS_MIO32:C7,\" &\n\t\"PS_MIO33:G13,\" &\n\t\"PS_MIO34:B12,\" &\n\t\"PS_MIO35:F14,\" &\n\t\"PS_MIO36:A9,\" &\n\t\"PS_MIO37:B14,\" &\n\t\"PS_MIO38:F13,\" &\n\t\"PS_MIO39:C13,\" &\n\t\"PS_MIO4:E4,\" &\n\t\"PS_MIO40:E14,\" &\n\t\"PS_MIO41:C8,\" &\n\t\"PS_MIO42:D8,\" &\n\t\"PS_MIO43:B11,\" &\n\t\"PS_MIO44:E13,\" &\n\t\"PS_MIO45:B9,\" &\n\t\"PS_MIO46:D12,\" &\n\t\"PS_MIO47:B10,\" &\n\t\"PS_MIO48:D11,\" &\n\t\"PS_MIO49:C14,\" &\n\t\"PS_MIO5:A3,\" &\n\t\"PS_MIO50:D13,\" &\n\t\"PS_MIO51:C10,\" &\n\t\"PS_MIO52:D10,\" &\n\t\"PS_MIO53:C12,\" &\n\t\"PS_MIO6:A4,\" &\n\t\"PS_MIO7:D5,\" &\n\t\"PS_MIO8:E5,\" &\n\t\"PS_MIO9:C4,\" &\n\t\"PS_MIO_VREF:F8,\" &\n\t\"PS_POR_B:B5,\" &\n\t\"PS_SRST_B:C9,\" &\n\t\"TCK:G11,\" &\n\t\"TDI:H13,\" &\n\t\"TDN_N12:N12,\" &\n\t\"TDO:G14,\" &\n\t\"TDP_N11:N11,\" &\n\t\"TMS:G12,\" &\n\t\"VCCADC_0:K11,\" &\n\t\"VCCAUX:(L10,N10,P11,R10),\" &\n\t\"VCCBATT_0:G9,\" &\n\t\"VCCBRAM:(H11,J10),\" &\n\t\"VCCINT:(J12,J14,K13,L14,M13,N14,P13,R14),\" &\n\t\"VCCO_0:R12,\" &\n\t\"VCCO_13:(T5,U8,V11,W4,Y7,AA10,AB3),\" &\n\t\"VCCO_33:(U18,V21,W14,Y17,AA20,AB13),\" &\n\t\"VCCO_34:(K17,L20,N16,P19,R22,T15),\" &\n\t\"VCCO_35:(A20,C16,D19,E22,F15,G18,H21),\" &\n\t\"VCCO_DDR_502:(E2,F5,H1,J4,K7,M3,N6,R2,V1),\" &\n\t\"VCCO_MIO0_500:(B3,C6),\" &\n\t\"VCCO_MIO1_501:(A10,B13,D9,E12),\" &\n\t\"VCCPAUX:(K9,M9,P9,T9),\" &\n\t\"VCCPINT:(G8,H9,J8,L8,N8,R8),\" &\n\t\"VCCPLL:H10,\" &\n\t\"VN_M12:M12,\" &\n\t\"VP_L11:L11,\" &\n\t\"VREFN_L12:L12,\" &\n\t\"VREFP_M11:M11,\" &\n\t\"IO_A16:A16,\" &\n\t\"IO_A17:A17,\" &\n\t\"IO_A18:A18,\" &\n\t\"IO_A19:A19,\" &\n\t\"IO_A21:A21,\" &\n\t\"IO_A22:A22,\" &\n\t\"IO_B15:B15,\" &\n\t\"IO_B16:B16,\" &\n\t\"IO_B17:B17,\" &\n\t\"IO_B19:B19,\" &\n\t\"IO_B20:B20,\" &\n\t\"IO_B21:B21,\" &\n\t\"IO_B22:B22,\" &\n\t\"IO_C15:C15,\" &\n\t\"IO_C17:C17,\" &\n\t\"IO_C18:C18,\" &\n\t\"IO_C19:C19,\" &\n\t\"IO_C20:C20,\" &\n\t\"IO_C22:C22,\" &\n\t\"IO_D15:D15,\" &\n\t\"IO_D16:D16,\" &\n\t\"IO_D17:D17,\" &\n\t\"IO_D18:D18,\" &\n\t\"IO_D20:D20,\" &\n\t\"IO_D21:D21,\" &\n\t\"IO_D22:D22,\" &\n\t\"IO_E15:E15,\" &\n\t\"IO_E16:E16,\" &\n\t\"IO_E18:E18,\" &\n\t\"IO_E19:E19,\" &\n\t\"IO_E20:E20,\" &\n\t\"IO_E21:E21,\" &\n\t\"IO_F16:F16,\" &\n\t\"IO_F17:F17,\" &\n\t\"IO_F18:F18,\" &\n\t\"IO_F19:F19,\" &\n\t\"IO_F21:F21,\" &\n\t\"IO_F22:F22,\" &\n\t\"IO_G15:G15,\" &\n\t\"IO_G16:G16,\" &\n\t\"IO_G17:G17,\" &\n\t\"IO_G19:G19,\" &\n\t\"IO_G20:G20,\" &\n\t\"IO_G21:G21,\" &\n\t\"IO_G22:G22,\" &\n\t\"IO_H15:H15,\" &\n\t\"IO_H17:H17,\" &\n\t\"IO_H18:H18,\" &\n\t\"IO_H19:H19,\" &\n\t\"IO_H20:H20,\" &\n\t\"IO_H22:H22,\" &\n\t\"IO_J15:J15,\" &\n\t\"IO_J16:J16,\" &\n\t\"IO_J17:J17,\" &\n\t\"IO_J18:J18,\" &\n\t\"IO_J20:J20,\" &\n\t\"IO_J21:J21,\" &\n\t\"IO_J22:J22,\" &\n\t\"IO_K15:K15,\" &\n\t\"IO_K16:K16,\" &\n\t\"IO_K18:K18,\" &\n\t\"IO_K19:K19,\" &\n\t\"IO_K20:K20,\" &\n\t\"IO_K21:K21,\" &\n\t\"IO_L16:L16,\" &\n\t\"IO_L17:L17,\" &\n\t\"IO_L18:L18,\" &\n\t\"IO_L19:L19,\" &\n\t\"IO_L21:L21,\" &\n\t\"IO_L22:L22,\" &\n\t\"IO_M15:M15,\" &\n\t\"IO_M16:M16,\" &\n\t\"IO_M17:M17,\" &\n\t\"IO_M19:M19,\" &\n\t\"IO_M20:M20,\" &\n\t\"IO_M21:M21,\" &\n\t\"IO_M22:M22,\" &\n\t\"IO_N15:N15,\" &\n\t\"IO_N17:N17,\" &\n\t\"IO_N18:N18,\" &\n\t\"IO_N19:N19,\" &\n\t\"IO_N20:N20,\" &\n\t\"IO_N22:N22,\" &\n\t\"IO_P15:P15,\" &\n\t\"IO_P16:P16,\" &\n\t\"IO_P17:P17,\" &\n\t\"IO_P18:P18,\" &\n\t\"IO_P20:P20,\" &\n\t\"IO_P21:P21,\" &\n\t\"IO_P22:P22,\" &\n\t\"IO_R6:R6,\" &\n\t\"IO_R7:R7,\" &\n\t\"IO_R15:R15,\" &\n\t\"IO_R16:R16,\" &\n\t\"IO_R18:R18,\" &\n\t\"IO_R19:R19,\" &\n\t\"IO_R20:R20,\" &\n\t\"IO_R21:R21,\" &\n\t\"IO_T4:T4,\" &\n\t\"IO_T6:T6,\" &\n\t\"IO_T16:T16,\" &\n\t\"IO_T17:T17,\" &\n\t\"IO_T18:T18,\" &\n\t\"IO_T19:T19,\" &\n\t\"IO_T21:T21,\" &\n\t\"IO_T22:T22,\" &\n\t\"IO_U4:U4,\" &\n\t\"IO_U5:U5,\" &\n\t\"IO_U6:U6,\" &\n\t\"IO_U7:U7,\" &\n\t\"IO_U9:U9,\" &\n\t\"IO_U10:U10,\" &\n\t\"IO_U11:U11,\" &\n\t\"IO_U12:U12,\" &\n\t\"IO_U14:U14,\" &\n\t\"IO_U15:U15,\" &\n\t\"IO_U16:U16,\" &\n\t\"IO_U17:U17,\" &\n\t\"IO_U19:U19,\" &\n\t\"IO_U20:U20,\" &\n\t\"IO_U21:U21,\" &\n\t\"IO_U22:U22,\" &\n\t\"IO_V4:V4,\" &\n\t\"IO_V5:V5,\" &\n\t\"IO_V7:V7,\" &\n\t\"IO_V8:V8,\" &\n\t\"IO_V9:V9,\" &\n\t\"IO_V10:V10,\" &\n\t\"IO_V12:V12,\" &\n\t\"IO_V13:V13,\" &\n\t\"IO_V14:V14,\" &\n\t\"IO_V15:V15,\" &\n\t\"IO_V17:V17,\" &\n\t\"IO_V18:V18,\" &\n\t\"IO_V19:V19,\" &\n\t\"IO_V20:V20,\" &\n\t\"IO_V22:V22,\" &\n\t\"IO_W5:W5,\" &\n\t\"IO_W6:W6,\" &\n\t\"IO_W7:W7,\" &\n\t\"IO_W8:W8,\" &\n\t\"IO_W10:W10,\" &\n\t\"IO_W11:W11,\" &\n\t\"IO_W12:W12,\" &\n\t\"IO_W13:W13,\" &\n\t\"IO_W15:W15,\" &\n\t\"IO_W16:W16,\" &\n\t\"IO_W17:W17,\" &\n\t\"IO_W18:W18,\" &\n\t\"IO_W20:W20,\" &\n\t\"IO_W21:W21,\" &\n\t\"IO_W22:W22,\" &\n\t\"IO_Y4:Y4,\" &\n\t\"IO_Y5:Y5,\" &\n\t\"IO_Y6:Y6,\" &\n\t\"IO_Y8:Y8,\" &\n\t\"IO_Y9:Y9,\" &\n\t\"IO_Y10:Y10,\" &\n\t\"IO_Y11:Y11,\" &\n\t\"IO_Y13:Y13,\" &\n\t\"IO_Y14:Y14,\" &\n\t\"IO_Y15:Y15,\" &\n\t\"IO_Y16:Y16,\" &\n\t\"IO_Y18:Y18,\" &\n\t\"IO_Y19:Y19,\" &\n\t\"IO_Y20:Y20,\" &\n\t\"IO_Y21:Y21,\" &\n\t\"IO_AA4:AA4,\" &\n\t\"IO_AA6:AA6,\" &\n\t\"IO_AA7:AA7,\" &\n\t\"IO_AA8:AA8,\" &\n\t\"IO_AA9:AA9,\" &\n\t\"IO_AA11:AA11,\" &\n\t\"IO_AA12:AA12,\" &\n\t\"IO_AA13:AA13,\" &\n\t\"IO_AA14:AA14,\" &\n\t\"IO_AA16:AA16,\" &\n\t\"IO_AA17:AA17,\" &\n\t\"IO_AA18:AA18,\" &\n\t\"IO_AA19:AA19,\" &\n\t\"IO_AA21:AA21,\" &\n\t\"IO_AA22:AA22,\" &\n\t\"IO_AB1:AB1,\" &\n\t\"IO_AB2:AB2,\" &\n\t\"IO_AB4:AB4,\" &\n\t\"IO_AB5:AB5,\" &\n\t\"IO_AB6:AB6,\" &\n\t\"IO_AB7:AB7,\" &\n\t\"IO_AB9:AB9,\" &\n\t\"IO_AB10:AB10,\" &\n\t\"IO_AB11:AB11,\" &\n\t\"IO_AB12:AB12,\" &\n\t\"IO_AB14:AB14,\" &\n\t\"IO_AB15:AB15,\" &\n\t\"IO_AB16:AB16,\" &\n\t\"IO_AB17:AB17,\" &\n\t\"IO_AB19:AB19,\" &\n\t\"IO_AB20:AB20,\" &\n\t\"IO_AB21:AB21,\" &\n\t\"IO_AB22:AB22\";\n\n\n-- Grouped Port Identification\n\n\n\n-- Scan Port Identification\n\nattribute TAP_SCAN_IN    of TDI : signal is true;\nattribute TAP_SCAN_MODE  of TMS : signal is true;\nattribute TAP_SCAN_OUT   of TDO : signal is true;\nattribute TAP_SCAN_CLOCK of TCK : signal is (66.0e6, BOTH);\n\n-- Compliance-Enable Description\n\nattribute COMPLIANCE_PATTERNS of XC7Z020_CLG484 : entity is\n        \"(PROGRAM_B) (1)\";\n\n-- Instruction Register Description\n\nattribute INSTRUCTION_LENGTH of XC7Z020_CLG484 : entity is 6;\n\nattribute INSTRUCTION_OPCODE of XC7Z020_CLG484 : entity is\n        \"IDCODE\t\t(001001),\" & -- DEVICE_ID\n        \"BYPASS\t\t(111111),\" & -- BYPASS\n        \"EXTEST\t\t(100110),\" & -- BOUNDARY\n        \"SAMPLE\t\t(000001),\" & -- BOUNDARY\n        \"PRELOAD\t(000001),\" & -- Same as SAMPLE\n        \"USERCODE\t(001000),\" & -- DEVICE_ID\n        \"HIGHZ\t\t(001010),\" & -- BYPASS\n        \"EXTEST_PULSE\t(111100),\" & -- BOUNDARY\n        \"EXTEST_TRAIN\t(111101),\" & -- BOUNDARY\n\t\"ISC_ENABLE\t(010000),\" & -- ISC_CONFIG\n\t\"ISC_PROGRAM\t(010001),\" & -- ISC_PDATA\n\t\"ISC_NOOP\t(010100),\" & -- ISC_DEFAULT\n\t\"XSC_READ_RSVD\t(010101),\" & -- PRIVATE\n\t\"ISC_DISABLE\t(010110),\" & -- ISC_CONFIG\n\t\"XSC_PROGRAM_KEY\t(010010),\" & -- XSC_KEY_DATA\n        \"XSC_DNA\t(010111),\" & -- DNA\n        \"CFG_OUT\t(000100),\" & -- Not available during configuration with another mode.\n        \"CFG_IN\t\t(000101),\" & -- Not available during configuration with another mode.\n        \"JPROGRAM\t(001011),\" & -- Not available during configuration with another mode.\n        \"JSTART\t\t(001100),\" & -- Not available during configuration with another mode.\n        \"JSHUTDOWN\t(001101),\" & -- Not available during configuration with another mode.\n        \"FUSE_CTS\t(110000),\" & -- PRIVATE\n        \"FUSE_KEY\t(110001),\" & -- PRIVATE\n        \"FUSE_DNA\t(110010),\" & -- PRIVATE\n        \"FUSE_USER\t(110011),\" & -- PRIVATE\n        \"FUSE_CNTL\t(110100),\" & -- PRIVATE\n        \"USER1\t\t(000010),\" & -- Not available until after configuration\n        \"USER2\t\t(000011),\" & -- Not available until after configuration\n        \"USER3\t\t(100010),\" & -- Not available until after configuration\n        \"USER4\t\t(100011),\" & -- Not available until after configuration\n        \"XADC_DRP\t(110111),\" & -- PRIVATE\n        \"INTEST_RSVD\t(000111)\"; -- PRIVATE\n\nattribute INSTRUCTION_CAPTURE of XC7Z020_CLG484 : entity is\n-- Bit 5 is 1 when DONE is released (part of startup sequence)\n-- Bit 4 is 1 if house-cleaning is complete\n-- Bit 3 is ISC_Enabled\n-- Bit 2 is ISC_Done\n        \"XXXX01\";\n\nattribute INSTRUCTION_PRIVATE of XC7Z020_CLG484 : entity is\n-- If the device is configured, and a USER instruction is implemented\n-- and not private to the FPGA designer, then it should be removed\n-- from INSTRUCTION_PRIVATE, and the target register should be defined\n-- in REGISTER_ACCESS.\n\t\"ISC_ENABLE,\" &\n\t\"ISC_PROGRAM,\" &\n\t\"ISC_NOOP,\" &\n\t\"XSC_READ_RSVD,\" &\n\t\"ISC_DISABLE,\" &\n\t\"XSC_PROGRAM_KEY,\" &\n\t\"XSC_DNA,\" &\n        \"CFG_OUT,\" &\n        \"CFG_IN,\" &\n        \"JPROGRAM,\" &\n        \"JSTART,\" &\n        \"JSHUTDOWN,\" &\n        \"FUSE_CTS,\" &\n        \"FUSE_KEY,\" &\n        \"FUSE_DNA,\" &\n        \"FUSE_USER,\" &\n        \"FUSE_CNTL,\" &\n        \"USER1,\" &\n        \"USER2,\" &\n        \"USER3,\" &\n        \"USER4,\" &\n        \"XADC_DRP,\" &\n        \"INTEST_RSVD\";\n\n-- Optional Register Description\n\nattribute IDCODE_REGISTER of XC7Z020_CLG484 : entity is\n\t\"XXXX\" &\t-- version\n\t\"0011011\" &\t-- family\n\t\"100100111\" &\t-- array size\n\t\"00001001001\" &\t-- manufacturer\n\t\"1\";\t\t-- required by 1149.1\n\n\nattribute USERCODE_REGISTER of XC7Z020_CLG484 : entity is\n        \"XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX\";\n\n-- Register Access Description\n\nattribute REGISTER_ACCESS of XC7Z020_CLG484 : entity is\n--\t\"<reg_name>[<length>] (USER1),\" &\n--\t\"<reg_name>[<length>] (USER2),\" &\n--\t\"<reg_name>[<length>] (USER3),\" &\n--\t\"<reg_name>[<length>] (USER4),\" &\n        \"DATAREG[57] (XSC_DNA),\" &\n        \"BYPASS (HIGHZ,BYPASS),\" &\n\t\"DEVICE_ID (USERCODE,IDCODE),\" &\n\t\"BOUNDARY (SAMPLE,PRELOAD,EXTEST,EXTEST_PULSE,EXTEST_TRAIN)\";\n\n-- Boundary-Scan Register Description\n\nattribute BOUNDARY_LENGTH of XC7Z020_CLG484 : entity is 1077;\n\nattribute BOUNDARY_REGISTER of XC7Z020_CLG484 : entity is\n-- cellnum (type, port, function, safe[, ccell, disval, disrslt])\n\t\"   0 (BC_2, *, controlr, 1),\" &\n\t\"   1 (BC_2, RSVDGND_G10, output3, X, 0, 1, Z),\" & --  RSVDGND_0\n\t\"   2 (BC_2, RSVDGND_G10, input, X),\" & --  RSVDGND_0\n\t\"   3 (BC_2, RSVD0VCC_T10, input, X),\" &\n\t\"   4 (BC_2, RSVD1VCC_T8, input, X),\" &\n\t\"   5 (BC_2, RSVD2VCC_T7, input, X),\" &\n\t\"   6 (BC_2, CFGBVS_T13, input, X),\" &\n\t\"   7 (BC_2, *, internal, 1),\" & --  PROGRAM_B\n\t\"   8 (BC_2, *, controlr, 1),\" &\n\t\"   9 (BC_2, INIT_B_T14, output3, X, 8, 1, Z),\" & --  INIT_B_0\n\t\"  10 (BC_2, INIT_B_T14, input, X),\" & --  INIT_B_0\n\t\"  11 (BC_2, *, controlr, 1),\" &\n\t\"  12 (BC_2, DONE_T12, output3, X, 11, 1, Z),\" & --  DONE_0\n\t\"  13 (BC_2, DONE_T12, input, X),\" & --  DONE_0\n\t\"  14 (BC_2, *, internal, X),\" &\n\t\"  15 (BC_2, *, internal, X),\" &\n\t\"  16 (BC_2, *, internal, X),\" &\n\t\"  17 (BC_2, *, internal, X),\" &\n\t\"  18 (BC_2, *, internal, X),\" &\n\t\"  19 (BC_2, *, internal, X),\" &\n\t\"  20 (BC_2, *, internal, X),\" &\n\t\"  21 (BC_2, *, internal, X),\" &\n\t\"  22 (BC_2, *, internal, X),\" &\n\t\"  23 (BC_2, *, internal, X),\" &\n\t\"  24 (BC_2, *, internal, X),\" &\n\t\"  25 (BC_2, *, internal, X),\" &\n\t\"  26 (BC_2, *, controlr, 1),\" &\n\t\"  27 (BC_2, IO_U14, output3, X, 26, 1, Z),\" & --  PAD200\n\t\"  28 (BC_2, IO_U14, input, X),\" & --  PAD200\n\t\"  29 (BC_2, *, controlr, 1),\" &\n\t\"  30 (BC_2, IO_AB15, output3, X, 29, 1, Z),\" & --  PAD199\n\t\"  31 (BC_2, IO_AB15, input, X),\" & --  PAD199\n\t\"  32 (BC_2, *, controlr, 1),\" &\n\t\"  33 (BC_2, IO_AB14, output3, X, 32, 1, Z),\" & --  PAD198\n\t\"  34 (BC_2, IO_AB14, input, X),\" & --  PAD198\n\t\"  35 (BC_2, *, controlr, 1),\" &\n\t\"  36 (BC_2, IO_AA13, output3, X, 35, 1, Z),\" & --  PAD197\n\t\"  37 (BC_2, IO_AA13, input, X),\" & --  PAD197\n\t\"  38 (BC_2, *, controlr, 1),\" &\n\t\"  39 (BC_2, IO_Y13, output3, X, 38, 1, Z),\" & --  PAD196\n\t\"  40 (BC_2, IO_Y13, input, X),\" & --  PAD196\n\t\"  41 (BC_2, *, controlr, 1),\" &\n\t\"  42 (BC_2, IO_AA14, output3, X, 41, 1, Z),\" & --  PAD195\n\t\"  43 (BC_2, IO_AA14, input, X),\" & --  PAD195\n\t\"  44 (BC_2, *, controlr, 1),\" &\n\t\"  45 (BC_2, IO_Y14, output3, X, 44, 1, Z),\" & --  PAD194\n\t\"  46 (BC_2, IO_Y14, input, X),\" & --  PAD194\n\t\"  47 (BC_2, *, controlr, 1),\" &\n\t\"  48 (BC_2, IO_Y15, output3, X, 47, 1, Z),\" & --  PAD193\n\t\"  49 (BC_2, IO_Y15, input, X),\" & --  PAD193\n\t\"  50 (BC_2, *, controlr, 1),\" &\n\t\"  51 (BC_2, IO_W15, output3, X, 50, 1, Z),\" & --  PAD192\n\t\"  52 (BC_2, IO_W15, input, X),\" & --  PAD192\n\t\"  53 (BC_2, *, controlr, 1),\" &\n\t\"  54 (BC_2, IO_W13, output3, X, 53, 1, Z),\" & --  PAD191\n\t\"  55 (BC_2, IO_W13, input, X),\" & --  PAD191\n\t\"  56 (BC_2, *, controlr, 1),\" &\n\t\"  57 (BC_2, IO_V13, output3, X, 56, 1, Z),\" & --  PAD190\n\t\"  58 (BC_2, IO_V13, input, X),\" & --  PAD190\n\t\"  59 (BC_2, *, controlr, 1),\" &\n\t\"  60 (BC_2, IO_V15, output3, X, 59, 1, Z),\" & --  PAD189\n\t\"  61 (BC_2, IO_V15, input, X),\" & --  PAD189\n\t\"  62 (BC_2, *, controlr, 1),\" &\n\t\"  63 (BC_2, IO_V14, output3, X, 62, 1, Z),\" & --  PAD188\n\t\"  64 (BC_2, IO_V14, input, X),\" & --  PAD188\n\t\"  65 (BC_2, *, controlr, 1),\" &\n\t\"  66 (BC_2, IO_AB16, output3, X, 65, 1, Z),\" & --  PAD187\n\t\"  67 (BC_2, IO_AB16, input, X),\" & --  PAD187\n\t\"  68 (BC_2, *, controlr, 1),\" &\n\t\"  69 (BC_2, IO_AA16, output3, X, 68, 1, Z),\" & --  PAD186\n\t\"  70 (BC_2, IO_AA16, input, X),\" & --  PAD186\n\t\"  71 (BC_2, *, controlr, 1),\" &\n\t\"  72 (BC_2, IO_AB17, output3, X, 71, 1, Z),\" & --  PAD185\n\t\"  73 (BC_2, IO_AB17, input, X),\" & --  PAD185\n\t\"  74 (BC_2, *, controlr, 1),\" &\n\t\"  75 (BC_2, IO_AA17, output3, X, 74, 1, Z),\" & --  PAD184\n\t\"  76 (BC_2, IO_AA17, input, X),\" & --  PAD184\n\t\"  77 (BC_2, *, controlr, 1),\" &\n\t\"  78 (BC_2, IO_V17, output3, X, 77, 1, Z),\" & --  PAD183\n\t\"  79 (BC_2, IO_V17, input, X),\" & --  PAD183\n\t\"  80 (BC_2, *, controlr, 1),\" &\n\t\"  81 (BC_2, IO_U17, output3, X, 80, 1, Z),\" & --  PAD182\n\t\"  82 (BC_2, IO_U17, input, X),\" & --  PAD182\n\t\"  83 (BC_2, *, controlr, 1),\" &\n\t\"  84 (BC_2, IO_U16, output3, X, 83, 1, Z),\" & --  PAD181\n\t\"  85 (BC_2, IO_U16, input, X),\" & --  PAD181\n\t\"  86 (BC_2, *, controlr, 1),\" &\n\t\"  87 (BC_2, IO_U15, output3, X, 86, 1, Z),\" & --  PAD180\n\t\"  88 (BC_2, IO_U15, input, X),\" & --  PAD180\n\t\"  89 (BC_2, *, controlr, 1),\" &\n\t\"  90 (BC_2, IO_Y16, output3, X, 89, 1, Z),\" & --  PAD179\n\t\"  91 (BC_2, IO_Y16, input, X),\" & --  PAD179\n\t\"  92 (BC_2, *, controlr, 1),\" &\n\t\"  93 (BC_2, IO_W16, output3, X, 92, 1, Z),\" & --  PAD178\n\t\"  94 (BC_2, IO_W16, input, X),\" & --  PAD178\n\t\"  95 (BC_2, *, controlr, 1),\" &\n\t\"  96 (BC_2, IO_W18, output3, X, 95, 1, Z),\" & --  PAD177\n\t\"  97 (BC_2, IO_W18, input, X),\" & --  PAD177\n\t\"  98 (BC_2, *, controlr, 1),\" &\n\t\"  99 (BC_2, IO_W17, output3, X, 98, 1, Z),\" & --  PAD176\n\t\" 100 (BC_2, IO_W17, input, X),\" & --  PAD176\n\t\" 101 (BC_2, *, controlr, 1),\" &\n\t\" 102 (BC_2, IO_AA18, output3, X, 101, 1, Z),\" & --  PAD175\n\t\" 103 (BC_2, IO_AA18, input, X),\" & --  PAD175\n\t\" 104 (BC_2, *, controlr, 1),\" &\n\t\" 105 (BC_2, IO_Y18, output3, X, 104, 1, Z),\" & --  PAD174\n\t\" 106 (BC_2, IO_Y18, input, X),\" & --  PAD174\n\t\" 107 (BC_2, *, controlr, 1),\" &\n\t\" 108 (BC_2, IO_AA19, output3, X, 107, 1, Z),\" & --  PAD173\n\t\" 109 (BC_2, IO_AA19, input, X),\" & --  PAD173\n\t\" 110 (BC_2, *, controlr, 1),\" &\n\t\" 111 (BC_2, IO_Y19, output3, X, 110, 1, Z),\" & --  PAD172\n\t\" 112 (BC_2, IO_Y19, input, X),\" & --  PAD172\n\t\" 113 (BC_2, *, controlr, 1),\" &\n\t\" 114 (BC_2, IO_AB20, output3, X, 113, 1, Z),\" & --  PAD171\n\t\" 115 (BC_2, IO_AB20, input, X),\" & --  PAD171\n\t\" 116 (BC_2, *, controlr, 1),\" &\n\t\" 117 (BC_2, IO_AB19, output3, X, 116, 1, Z),\" & --  PAD170\n\t\" 118 (BC_2, IO_AB19, input, X),\" & --  PAD170\n\t\" 119 (BC_2, *, controlr, 1),\" &\n\t\" 120 (BC_2, IO_Y21, output3, X, 119, 1, Z),\" & --  PAD169\n\t\" 121 (BC_2, IO_Y21, input, X),\" & --  PAD169\n\t\" 122 (BC_2, *, controlr, 1),\" &\n\t\" 123 (BC_2, IO_Y20, output3, X, 122, 1, Z),\" & --  PAD168\n\t\" 124 (BC_2, IO_Y20, input, X),\" & --  PAD168\n\t\" 125 (BC_2, *, controlr, 1),\" &\n\t\" 126 (BC_2, IO_AB21, output3, X, 125, 1, Z),\" & --  PAD167\n\t\" 127 (BC_2, IO_AB21, input, X),\" & --  PAD167\n\t\" 128 (BC_2, *, controlr, 1),\" &\n\t\" 129 (BC_2, IO_AA21, output3, X, 128, 1, Z),\" & --  PAD166\n\t\" 130 (BC_2, IO_AA21, input, X),\" & --  PAD166\n\t\" 131 (BC_2, *, controlr, 1),\" &\n\t\" 132 (BC_2, IO_AB22, output3, X, 131, 1, Z),\" & --  PAD165\n\t\" 133 (BC_2, IO_AB22, input, X),\" & --  PAD165\n\t\" 134 (BC_2, *, controlr, 1),\" &\n\t\" 135 (BC_2, IO_AA22, output3, X, 134, 1, Z),\" & --  PAD164\n\t\" 136 (BC_2, IO_AA22, input, X),\" & --  PAD164\n\t\" 137 (BC_2, *, controlr, 1),\" &\n\t\" 138 (BC_2, IO_V19, output3, X, 137, 1, Z),\" & --  PAD163\n\t\" 139 (BC_2, IO_V19, input, X),\" & --  PAD163\n\t\" 140 (BC_2, *, controlr, 1),\" &\n\t\" 141 (BC_2, IO_V18, output3, X, 140, 1, Z),\" & --  PAD162\n\t\" 142 (BC_2, IO_V18, input, X),\" & --  PAD162\n\t\" 143 (BC_2, *, controlr, 1),\" &\n\t\" 144 (BC_2, IO_V20, output3, X, 143, 1, Z),\" & --  PAD161\n\t\" 145 (BC_2, IO_V20, input, X),\" & --  PAD161\n\t\" 146 (BC_2, *, controlr, 1),\" &\n\t\" 147 (BC_2, IO_U20, output3, X, 146, 1, Z),\" & --  PAD160\n\t\" 148 (BC_2, IO_U20, input, X),\" & --  PAD160\n\t\" 149 (BC_2, *, controlr, 1),\" &\n\t\" 150 (BC_2, IO_W21, output3, X, 149, 1, Z),\" & --  PAD159\n\t\" 151 (BC_2, IO_W21, input, X),\" & --  PAD159\n\t\" 152 (BC_2, *, controlr, 1),\" &\n\t\" 153 (BC_2, IO_W20, output3, X, 152, 1, Z),\" & --  PAD158\n\t\" 154 (BC_2, IO_W20, input, X),\" & --  PAD158\n\t\" 155 (BC_2, *, controlr, 1),\" &\n\t\" 156 (BC_2, IO_W22, output3, X, 155, 1, Z),\" & --  PAD157\n\t\" 157 (BC_2, IO_W22, input, X),\" & --  PAD157\n\t\" 158 (BC_2, *, controlr, 1),\" &\n\t\" 159 (BC_2, IO_V22, output3, X, 158, 1, Z),\" & --  PAD156\n\t\" 160 (BC_2, IO_V22, input, X),\" & --  PAD156\n\t\" 161 (BC_2, *, controlr, 1),\" &\n\t\" 162 (BC_2, IO_U22, output3, X, 161, 1, Z),\" & --  PAD155\n\t\" 163 (BC_2, IO_U22, input, X),\" & --  PAD155\n\t\" 164 (BC_2, *, controlr, 1),\" &\n\t\" 165 (BC_2, IO_T22, output3, X, 164, 1, Z),\" & --  PAD154\n\t\" 166 (BC_2, IO_T22, input, X),\" & --  PAD154\n\t\" 167 (BC_2, *, controlr, 1),\" &\n\t\" 168 (BC_2, IO_U21, output3, X, 167, 1, Z),\" & --  PAD153\n\t\" 169 (BC_2, IO_U21, input, X),\" & --  PAD153\n\t\" 170 (BC_2, *, controlr, 1),\" &\n\t\" 171 (BC_2, IO_T21, output3, X, 170, 1, Z),\" & --  PAD152\n\t\" 172 (BC_2, IO_T21, input, X),\" & --  PAD152\n\t\" 173 (BC_2, *, controlr, 1),\" &\n\t\" 174 (BC_2, IO_U19, output3, X, 173, 1, Z),\" & --  PAD151\n\t\" 175 (BC_2, IO_U19, input, X),\" & --  PAD151\n\t\" 176 (BC_2, *, controlr, 1),\" &\n\t\" 177 (BC_2, IO_R15, output3, X, 176, 1, Z),\" & --  PAD150\n\t\" 178 (BC_2, IO_R15, input, X),\" & --  PAD150\n\t\" 179 (BC_2, *, controlr, 1),\" &\n\t\" 180 (BC_2, IO_R16, output3, X, 179, 1, Z),\" & --  PAD149\n\t\" 181 (BC_2, IO_R16, input, X),\" & --  PAD149\n\t\" 182 (BC_2, *, controlr, 1),\" &\n\t\" 183 (BC_2, IO_P16, output3, X, 182, 1, Z),\" & --  PAD148\n\t\" 184 (BC_2, IO_P16, input, X),\" & --  PAD148\n\t\" 185 (BC_2, *, controlr, 1),\" &\n\t\" 186 (BC_2, IO_T18, output3, X, 185, 1, Z),\" & --  PAD147\n\t\" 187 (BC_2, IO_T18, input, X),\" & --  PAD147\n\t\" 188 (BC_2, *, controlr, 1),\" &\n\t\" 189 (BC_2, IO_R18, output3, X, 188, 1, Z),\" & --  PAD146\n\t\" 190 (BC_2, IO_R18, input, X),\" & --  PAD146\n\t\" 191 (BC_2, *, controlr, 1),\" &\n\t\" 192 (BC_2, IO_T19, output3, X, 191, 1, Z),\" & --  PAD145\n\t\" 193 (BC_2, IO_T19, input, X),\" & --  PAD145\n\t\" 194 (BC_2, *, controlr, 1),\" &\n\t\" 195 (BC_2, IO_R19, output3, X, 194, 1, Z),\" & --  PAD144\n\t\" 196 (BC_2, IO_R19, input, X),\" & --  PAD144\n\t\" 197 (BC_2, *, controlr, 1),\" &\n\t\" 198 (BC_2, IO_T17, output3, X, 197, 1, Z),\" & --  PAD143\n\t\" 199 (BC_2, IO_T17, input, X),\" & --  PAD143\n\t\" 200 (BC_2, *, controlr, 1),\" &\n\t\" 201 (BC_2, IO_T16, output3, X, 200, 1, Z),\" & --  PAD142\n\t\" 202 (BC_2, IO_T16, input, X),\" & --  PAD142\n\t\" 203 (BC_2, *, controlr, 1),\" &\n\t\" 204 (BC_2, IO_P18, output3, X, 203, 1, Z),\" & --  PAD141\n\t\" 205 (BC_2, IO_P18, input, X),\" & --  PAD141\n\t\" 206 (BC_2, *, controlr, 1),\" &\n\t\" 207 (BC_2, IO_P17, output3, X, 206, 1, Z),\" & --  PAD140\n\t\" 208 (BC_2, IO_P17, input, X),\" & --  PAD140\n\t\" 209 (BC_2, *, controlr, 1),\" &\n\t\" 210 (BC_2, IO_P15, output3, X, 209, 1, Z),\" & --  PAD139\n\t\" 211 (BC_2, IO_P15, input, X),\" & --  PAD139\n\t\" 212 (BC_2, *, controlr, 1),\" &\n\t\" 213 (BC_2, IO_N15, output3, X, 212, 1, Z),\" & --  PAD138\n\t\" 214 (BC_2, IO_N15, input, X),\" & --  PAD138\n\t\" 215 (BC_2, *, controlr, 1),\" &\n\t\" 216 (BC_2, IO_P21, output3, X, 215, 1, Z),\" & --  PAD137\n\t\" 217 (BC_2, IO_P21, input, X),\" & --  PAD137\n\t\" 218 (BC_2, *, controlr, 1),\" &\n\t\" 219 (BC_2, IO_P20, output3, X, 218, 1, Z),\" & --  PAD136\n\t\" 220 (BC_2, IO_P20, input, X),\" & --  PAD136\n\t\" 221 (BC_2, *, controlr, 1),\" &\n\t\" 222 (BC_2, IO_R21, output3, X, 221, 1, Z),\" & --  PAD135\n\t\" 223 (BC_2, IO_R21, input, X),\" & --  PAD135\n\t\" 224 (BC_2, *, controlr, 1),\" &\n\t\" 225 (BC_2, IO_R20, output3, X, 224, 1, Z),\" & --  PAD134\n\t\" 226 (BC_2, IO_R20, input, X),\" & --  PAD134\n\t\" 227 (BC_2, *, controlr, 1),\" &\n\t\" 228 (BC_2, IO_P22, output3, X, 227, 1, Z),\" & --  PAD133\n\t\" 229 (BC_2, IO_P22, input, X),\" & --  PAD133\n\t\" 230 (BC_2, *, controlr, 1),\" &\n\t\" 231 (BC_2, IO_N22, output3, X, 230, 1, Z),\" & --  PAD132\n\t\" 232 (BC_2, IO_N22, input, X),\" & --  PAD132\n\t\" 233 (BC_2, *, controlr, 1),\" &\n\t\" 234 (BC_2, IO_M22, output3, X, 233, 1, Z),\" & --  PAD131\n\t\" 235 (BC_2, IO_M22, input, X),\" & --  PAD131\n\t\" 236 (BC_2, *, controlr, 1),\" &\n\t\" 237 (BC_2, IO_M21, output3, X, 236, 1, Z),\" & --  PAD130\n\t\" 238 (BC_2, IO_M21, input, X),\" & --  PAD130\n\t\" 239 (BC_2, *, controlr, 1),\" &\n\t\" 240 (BC_2, IO_N20, output3, X, 239, 1, Z),\" & --  PAD129\n\t\" 241 (BC_2, IO_N20, input, X),\" & --  PAD129\n\t\" 242 (BC_2, *, controlr, 1),\" &\n\t\" 243 (BC_2, IO_N19, output3, X, 242, 1, Z),\" & --  PAD128\n\t\" 244 (BC_2, IO_N19, input, X),\" & --  PAD128\n\t\" 245 (BC_2, *, controlr, 1),\" &\n\t\" 246 (BC_2, IO_M20, output3, X, 245, 1, Z),\" & --  PAD127\n\t\" 247 (BC_2, IO_M20, input, X),\" & --  PAD127\n\t\" 248 (BC_2, *, controlr, 1),\" &\n\t\" 249 (BC_2, IO_M19, output3, X, 248, 1, Z),\" & --  PAD126\n\t\" 250 (BC_2, IO_M19, input, X),\" & --  PAD126\n\t\" 251 (BC_2, *, controlr, 1),\" &\n\t\" 252 (BC_2, IO_L19, output3, X, 251, 1, Z),\" & --  PAD125\n\t\" 253 (BC_2, IO_L19, input, X),\" & --  PAD125\n\t\" 254 (BC_2, *, controlr, 1),\" &\n\t\" 255 (BC_2, IO_L18, output3, X, 254, 1, Z),\" & --  PAD124\n\t\" 256 (BC_2, IO_L18, input, X),\" & --  PAD124\n\t\" 257 (BC_2, *, controlr, 1),\" &\n\t\" 258 (BC_2, IO_K20, output3, X, 257, 1, Z),\" & --  PAD123\n\t\" 259 (BC_2, IO_K20, input, X),\" & --  PAD123\n\t\" 260 (BC_2, *, controlr, 1),\" &\n\t\" 261 (BC_2, IO_K19, output3, X, 260, 1, Z),\" & --  PAD122\n\t\" 262 (BC_2, IO_K19, input, X),\" & --  PAD122\n\t\" 263 (BC_2, *, controlr, 1),\" &\n\t\" 264 (BC_2, IO_L22, output3, X, 263, 1, Z),\" & --  PAD121\n\t\" 265 (BC_2, IO_L22, input, X),\" & --  PAD121\n\t\" 266 (BC_2, *, controlr, 1),\" &\n\t\" 267 (BC_2, IO_L21, output3, X, 266, 1, Z),\" & --  PAD120\n\t\" 268 (BC_2, IO_L21, input, X),\" & --  PAD120\n\t\" 269 (BC_2, *, controlr, 1),\" &\n\t\" 270 (BC_2, IO_K21, output3, X, 269, 1, Z),\" & --  PAD119\n\t\" 271 (BC_2, IO_K21, input, X),\" & --  PAD119\n\t\" 272 (BC_2, *, controlr, 1),\" &\n\t\" 273 (BC_2, IO_J20, output3, X, 272, 1, Z),\" & --  PAD118\n\t\" 274 (BC_2, IO_J20, input, X),\" & --  PAD118\n\t\" 275 (BC_2, *, controlr, 1),\" &\n\t\" 276 (BC_2, IO_J22, output3, X, 275, 1, Z),\" & --  PAD117\n\t\" 277 (BC_2, IO_J22, input, X),\" & --  PAD117\n\t\" 278 (BC_2, *, controlr, 1),\" &\n\t\" 279 (BC_2, IO_J21, output3, X, 278, 1, Z),\" & --  PAD116\n\t\" 280 (BC_2, IO_J21, input, X),\" & --  PAD116\n\t\" 281 (BC_2, *, controlr, 1),\" &\n\t\" 282 (BC_2, IO_K18, output3, X, 281, 1, Z),\" & --  PAD115\n\t\" 283 (BC_2, IO_K18, input, X),\" & --  PAD115\n\t\" 284 (BC_2, *, controlr, 1),\" &\n\t\" 285 (BC_2, IO_J18, output3, X, 284, 1, Z),\" & --  PAD114\n\t\" 286 (BC_2, IO_J18, input, X),\" & --  PAD114\n\t\" 287 (BC_2, *, controlr, 1),\" &\n\t\" 288 (BC_2, IO_M16, output3, X, 287, 1, Z),\" & --  PAD113\n\t\" 289 (BC_2, IO_M16, input, X),\" & --  PAD113\n\t\" 290 (BC_2, *, controlr, 1),\" &\n\t\" 291 (BC_2, IO_M15, output3, X, 290, 1, Z),\" & --  PAD112\n\t\" 292 (BC_2, IO_M15, input, X),\" & --  PAD112\n\t\" 293 (BC_2, *, controlr, 1),\" &\n\t\" 294 (BC_2, IO_N18, output3, X, 293, 1, Z),\" & --  PAD111\n\t\" 295 (BC_2, IO_N18, input, X),\" & --  PAD111\n\t\" 296 (BC_2, *, controlr, 1),\" &\n\t\" 297 (BC_2, IO_N17, output3, X, 296, 1, Z),\" & --  PAD110\n\t\" 298 (BC_2, IO_N17, input, X),\" & --  PAD110\n\t\" 299 (BC_2, *, controlr, 1),\" &\n\t\" 300 (BC_2, IO_M17, output3, X, 299, 1, Z),\" & --  PAD109\n\t\" 301 (BC_2, IO_M17, input, X),\" & --  PAD109\n\t\" 302 (BC_2, *, controlr, 1),\" &\n\t\" 303 (BC_2, IO_L17, output3, X, 302, 1, Z),\" & --  PAD108\n\t\" 304 (BC_2, IO_L17, input, X),\" & --  PAD108\n\t\" 305 (BC_2, *, controlr, 1),\" &\n\t\" 306 (BC_2, IO_L16, output3, X, 305, 1, Z),\" & --  PAD107\n\t\" 307 (BC_2, IO_L16, input, X),\" & --  PAD107\n\t\" 308 (BC_2, *, controlr, 1),\" &\n\t\" 309 (BC_2, IO_K16, output3, X, 308, 1, Z),\" & --  PAD106\n\t\" 310 (BC_2, IO_K16, input, X),\" & --  PAD106\n\t\" 311 (BC_2, *, controlr, 1),\" &\n\t\" 312 (BC_2, IO_J17, output3, X, 311, 1, Z),\" & --  PAD105\n\t\" 313 (BC_2, IO_J17, input, X),\" & --  PAD105\n\t\" 314 (BC_2, *, controlr, 1),\" &\n\t\" 315 (BC_2, IO_J16, output3, X, 314, 1, Z),\" & --  PAD104\n\t\" 316 (BC_2, IO_J16, input, X),\" & --  PAD104\n\t\" 317 (BC_2, *, controlr, 1),\" &\n\t\" 318 (BC_2, IO_K15, output3, X, 317, 1, Z),\" & --  PAD103\n\t\" 319 (BC_2, IO_K15, input, X),\" & --  PAD103\n\t\" 320 (BC_2, *, controlr, 1),\" &\n\t\" 321 (BC_2, IO_J15, output3, X, 320, 1, Z),\" & --  PAD102\n\t\" 322 (BC_2, IO_J15, input, X),\" & --  PAD102\n\t\" 323 (BC_2, *, controlr, 1),\" &\n\t\" 324 (BC_2, IO_H15, output3, X, 323, 1, Z),\" & --  PAD101\n\t\" 325 (BC_2, IO_H15, input, X),\" & --  PAD101\n\t\" 326 (BC_2, *, controlr, 1),\" &\n\t\" 327 (BC_2, IO_H18, output3, X, 326, 1, Z),\" & --  PAD100\n\t\" 328 (BC_2, IO_H18, input, X),\" & --  PAD100\n\t\" 329 (BC_2, *, controlr, 1),\" &\n\t\" 330 (BC_2, IO_G22, output3, X, 329, 1, Z),\" & --  PAD99\n\t\" 331 (BC_2, IO_G22, input, X),\" & --  PAD99\n\t\" 332 (BC_2, *, controlr, 1),\" &\n\t\" 333 (BC_2, IO_H22, output3, X, 332, 1, Z),\" & --  PAD98\n\t\" 334 (BC_2, IO_H22, input, X),\" & --  PAD98\n\t\" 335 (BC_2, *, controlr, 1),\" &\n\t\" 336 (BC_2, IO_F22, output3, X, 335, 1, Z),\" & --  PAD97\n\t\" 337 (BC_2, IO_F22, input, X),\" & --  PAD97\n\t\" 338 (BC_2, *, controlr, 1),\" &\n\t\" 339 (BC_2, IO_F21, output3, X, 338, 1, Z),\" & --  PAD96\n\t\" 340 (BC_2, IO_F21, input, X),\" & --  PAD96\n\t\" 341 (BC_2, *, controlr, 1),\" &\n\t\" 342 (BC_2, IO_G21, output3, X, 341, 1, Z),\" & --  PAD95\n\t\" 343 (BC_2, IO_G21, input, X),\" & --  PAD95\n\t\" 344 (BC_2, *, controlr, 1),\" &\n\t\" 345 (BC_2, IO_G20, output3, X, 344, 1, Z),\" & --  PAD94\n\t\" 346 (BC_2, IO_G20, input, X),\" & --  PAD94\n\t\" 347 (BC_2, *, controlr, 1),\" &\n\t\" 348 (BC_2, IO_E20, output3, X, 347, 1, Z),\" & --  PAD93\n\t\" 349 (BC_2, IO_E20, input, X),\" & --  PAD93\n\t\" 350 (BC_2, *, controlr, 1),\" &\n\t\" 351 (BC_2, IO_E19, output3, X, 350, 1, Z),\" & --  PAD92\n\t\" 352 (BC_2, IO_E19, input, X),\" & --  PAD92\n\t\" 353 (BC_2, *, controlr, 1),\" &\n\t\" 354 (BC_2, IO_F19, output3, X, 353, 1, Z),\" & --  PAD91\n\t\" 355 (BC_2, IO_F19, input, X),\" & --  PAD91\n\t\" 356 (BC_2, *, controlr, 1),\" &\n\t\" 357 (BC_2, IO_G19, output3, X, 356, 1, Z),\" & --  PAD90\n\t\" 358 (BC_2, IO_G19, input, X),\" & --  PAD90\n\t\" 359 (BC_2, *, controlr, 1),\" &\n\t\" 360 (BC_2, IO_H20, output3, X, 359, 1, Z),\" & --  PAD89\n\t\" 361 (BC_2, IO_H20, input, X),\" & --  PAD89\n\t\" 362 (BC_2, *, controlr, 1),\" &\n\t\" 363 (BC_2, IO_H19, output3, X, 362, 1, Z),\" & --  PAD88\n\t\" 364 (BC_2, IO_H19, input, X),\" & --  PAD88\n\t\" 365 (BC_2, *, controlr, 1),\" &\n\t\" 366 (BC_2, IO_B22, output3, X, 365, 1, Z),\" & --  PAD87\n\t\" 367 (BC_2, IO_B22, input, X),\" & --  PAD87\n\t\" 368 (BC_2, *, controlr, 1),\" &\n\t\" 369 (BC_2, IO_B21, output3, X, 368, 1, Z),\" & --  PAD86\n\t\" 370 (BC_2, IO_B21, input, X),\" & --  PAD86\n\t\" 371 (BC_2, *, controlr, 1),\" &\n\t\" 372 (BC_2, IO_D21, output3, X, 371, 1, Z),\" & --  PAD85\n\t\" 373 (BC_2, IO_D21, input, X),\" & --  PAD85\n\t\" 374 (BC_2, *, controlr, 1),\" &\n\t\" 375 (BC_2, IO_E21, output3, X, 374, 1, Z),\" & --  PAD84\n\t\" 376 (BC_2, IO_E21, input, X),\" & --  PAD84\n\t\" 377 (BC_2, *, controlr, 1),\" &\n\t\" 378 (BC_2, IO_C22, output3, X, 377, 1, Z),\" & --  PAD83\n\t\" 379 (BC_2, IO_C22, input, X),\" & --  PAD83\n\t\" 380 (BC_2, *, controlr, 1),\" &\n\t\" 381 (BC_2, IO_D22, output3, X, 380, 1, Z),\" & --  PAD82\n\t\" 382 (BC_2, IO_D22, input, X),\" & --  PAD82\n\t\" 383 (BC_2, *, controlr, 1),\" &\n\t\" 384 (BC_2, IO_A22, output3, X, 383, 1, Z),\" & --  PAD81\n\t\" 385 (BC_2, IO_A22, input, X),\" & --  PAD81\n\t\" 386 (BC_2, *, controlr, 1),\" &\n\t\" 387 (BC_2, IO_A21, output3, X, 386, 1, Z),\" & --  PAD80\n\t\" 388 (BC_2, IO_A21, input, X),\" & --  PAD80\n\t\" 389 (BC_2, *, controlr, 1),\" &\n\t\" 390 (BC_2, IO_C20, output3, X, 389, 1, Z),\" & --  PAD79\n\t\" 391 (BC_2, IO_C20, input, X),\" & --  PAD79\n\t\" 392 (BC_2, *, controlr, 1),\" &\n\t\" 393 (BC_2, IO_D20, output3, X, 392, 1, Z),\" & --  PAD78\n\t\" 394 (BC_2, IO_D20, input, X),\" & --  PAD78\n\t\" 395 (BC_2, *, controlr, 1),\" &\n\t\" 396 (BC_2, IO_B20, output3, X, 395, 1, Z),\" & --  PAD77\n\t\" 397 (BC_2, IO_B20, input, X),\" & --  PAD77\n\t\" 398 (BC_2, *, controlr, 1),\" &\n\t\" 399 (BC_2, IO_B19, output3, X, 398, 1, Z),\" & --  PAD76\n\t\" 400 (BC_2, IO_B19, input, X),\" & --  PAD76\n\t\" 401 (BC_2, *, controlr, 1),\" &\n\t\" 402 (BC_2, IO_C19, output3, X, 401, 1, Z),\" & --  PAD75\n\t\" 403 (BC_2, IO_C19, input, X),\" & --  PAD75\n\t\" 404 (BC_2, *, controlr, 1),\" &\n\t\" 405 (BC_2, IO_D18, output3, X, 404, 1, Z),\" & --  PAD74\n\t\" 406 (BC_2, IO_D18, input, X),\" & --  PAD74\n\t\" 407 (BC_2, *, controlr, 1),\" &\n\t\" 408 (BC_2, IO_C18, output3, X, 407, 1, Z),\" & --  PAD73\n\t\" 409 (BC_2, IO_C18, input, X),\" & --  PAD73\n\t\" 410 (BC_2, *, controlr, 1),\" &\n\t\" 411 (BC_2, IO_C17, output3, X, 410, 1, Z),\" & --  PAD72\n\t\" 412 (BC_2, IO_C17, input, X),\" & --  PAD72\n\t\" 413 (BC_2, *, controlr, 1),\" &\n\t\" 414 (BC_2, IO_A19, output3, X, 413, 1, Z),\" & --  PAD71\n\t\" 415 (BC_2, IO_A19, input, X),\" & --  PAD71\n\t\" 416 (BC_2, *, controlr, 1),\" &\n\t\" 417 (BC_2, IO_A18, output3, X, 416, 1, Z),\" & --  PAD70\n\t\" 418 (BC_2, IO_A18, input, X),\" & --  PAD70\n\t\" 419 (BC_2, *, controlr, 1),\" &\n\t\" 420 (BC_2, IO_A17, output3, X, 419, 1, Z),\" & --  PAD69\n\t\" 421 (BC_2, IO_A17, input, X),\" & --  PAD69\n\t\" 422 (BC_2, *, controlr, 1),\" &\n\t\" 423 (BC_2, IO_A16, output3, X, 422, 1, Z),\" & --  PAD68\n\t\" 424 (BC_2, IO_A16, input, X),\" & --  PAD68\n\t\" 425 (BC_2, *, controlr, 1),\" &\n\t\" 426 (BC_2, IO_B17, output3, X, 425, 1, Z),\" & --  PAD67\n\t\" 427 (BC_2, IO_B17, input, X),\" & --  PAD67\n\t\" 428 (BC_2, *, controlr, 1),\" &\n\t\" 429 (BC_2, IO_B16, output3, X, 428, 1, Z),\" & --  PAD66\n\t\" 430 (BC_2, IO_B16, input, X),\" & --  PAD66\n\t\" 431 (BC_2, *, controlr, 1),\" &\n\t\" 432 (BC_2, IO_B15, output3, X, 431, 1, Z),\" & --  PAD65\n\t\" 433 (BC_2, IO_B15, input, X),\" & --  PAD65\n\t\" 434 (BC_2, *, controlr, 1),\" &\n\t\" 435 (BC_2, IO_C15, output3, X, 434, 1, Z),\" & --  PAD64\n\t\" 436 (BC_2, IO_C15, input, X),\" & --  PAD64\n\t\" 437 (BC_2, *, controlr, 1),\" &\n\t\" 438 (BC_2, IO_F17, output3, X, 437, 1, Z),\" & --  PAD63\n\t\" 439 (BC_2, IO_F17, input, X),\" & --  PAD63\n\t\" 440 (BC_2, *, controlr, 1),\" &\n\t\" 441 (BC_2, IO_G17, output3, X, 440, 1, Z),\" & --  PAD62\n\t\" 442 (BC_2, IO_G17, input, X),\" & --  PAD62\n\t\" 443 (BC_2, *, controlr, 1),\" &\n\t\" 444 (BC_2, IO_E18, output3, X, 443, 1, Z),\" & --  PAD61\n\t\" 445 (BC_2, IO_E18, input, X),\" & --  PAD61\n\t\" 446 (BC_2, *, controlr, 1),\" &\n\t\" 447 (BC_2, IO_F18, output3, X, 446, 1, Z),\" & --  PAD60\n\t\" 448 (BC_2, IO_F18, input, X),\" & --  PAD60\n\t\" 449 (BC_2, *, controlr, 1),\" &\n\t\" 450 (BC_2, IO_G16, output3, X, 449, 1, Z),\" & --  PAD59\n\t\" 451 (BC_2, IO_G16, input, X),\" & --  PAD59\n\t\" 452 (BC_2, *, controlr, 1),\" &\n\t\" 453 (BC_2, IO_G15, output3, X, 452, 1, Z),\" & --  PAD58\n\t\" 454 (BC_2, IO_G15, input, X),\" & --  PAD58\n\t\" 455 (BC_2, *, controlr, 1),\" &\n\t\" 456 (BC_2, IO_D15, output3, X, 455, 1, Z),\" & --  PAD57\n\t\" 457 (BC_2, IO_D15, input, X),\" & --  PAD57\n\t\" 458 (BC_2, *, controlr, 1),\" &\n\t\" 459 (BC_2, IO_E15, output3, X, 458, 1, Z),\" & --  PAD56\n\t\" 460 (BC_2, IO_E15, input, X),\" & --  PAD56\n\t\" 461 (BC_2, *, controlr, 1),\" &\n\t\" 462 (BC_2, IO_D17, output3, X, 461, 1, Z),\" & --  PAD55\n\t\" 463 (BC_2, IO_D17, input, X),\" & --  PAD55\n\t\" 464 (BC_2, *, controlr, 1),\" &\n\t\" 465 (BC_2, IO_D16, output3, X, 464, 1, Z),\" & --  PAD54\n\t\" 466 (BC_2, IO_D16, input, X),\" & --  PAD54\n\t\" 467 (BC_2, *, controlr, 1),\" &\n\t\" 468 (BC_2, IO_E16, output3, X, 467, 1, Z),\" & --  PAD53\n\t\" 469 (BC_2, IO_E16, input, X),\" & --  PAD53\n\t\" 470 (BC_2, *, controlr, 1),\" &\n\t\" 471 (BC_2, IO_F16, output3, X, 470, 1, Z),\" & --  PAD52\n\t\" 472 (BC_2, IO_F16, input, X),\" & --  PAD52\n\t\" 473 (BC_2, *, controlr, 1),\" &\n\t\" 474 (BC_2, IO_H17, output3, X, 473, 1, Z),\" & --  PAD51\n\t\" 475 (BC_2, IO_H17, input, X),\" & --  PAD51\n\t\" 476 (BC_2, *, internal, X),\" &\n\t\" 477 (BC_2, *, internal, X),\" &\n\t\" 478 (BC_2, *, internal, X),\" &\n\t\" 479 (BC_2, *, internal, X),\" &\n\t\" 480 (BC_2, *, internal, X),\" &\n\t\" 481 (BC_2, *, internal, X),\" &\n\t\" 482 (BC_2, *, internal, X),\" &\n\t\" 483 (BC_2, *, internal, X),\" &\n\t\" 484 (BC_2, *, internal, X),\" &\n\t\" 485 (BC_2, *, internal, X),\" &\n\t\" 486 (BC_2, *, internal, X),\" &\n\t\" 487 (BC_2, *, internal, X),\" &\n\t\" 488 (BC_2, *, internal, X),\" &\n\t\" 489 (BC_2, *, internal, X),\" &\n\t\" 490 (BC_2, *, internal, X),\" &\n\t\" 491 (BC_2, *, internal, X),\" &\n\t\" 492 (BC_2, *, internal, X),\" &\n\t\" 493 (BC_2, *, internal, X),\" &\n\t\" 494 (BC_2, *, internal, X),\" &\n\t\" 495 (BC_2, *, internal, X),\" &\n\t\" 496 (BC_2, *, internal, X),\" &\n\t\" 497 (BC_2, *, controlr, 1),\" &\n\t\" 498 (BC_2, IO_U7, output3, X, 497, 1, Z),\" & --  PAD50\n\t\" 499 (BC_2, IO_U7, input, X),\" & --  PAD50\n\t\" 500 (BC_2, *, controlr, 1),\" &\n\t\" 501 (BC_2, IO_W5, output3, X, 500, 1, Z),\" & --  PAD49\n\t\" 502 (BC_2, IO_W5, input, X),\" & --  PAD49\n\t\" 503 (BC_2, *, controlr, 1),\" &\n\t\" 504 (BC_2, IO_W6, output3, X, 503, 1, Z),\" & --  PAD48\n\t\" 505 (BC_2, IO_W6, input, X),\" & --  PAD48\n\t\" 506 (BC_2, *, controlr, 1),\" &\n\t\" 507 (BC_2, IO_W7, output3, X, 506, 1, Z),\" & --  PAD47\n\t\" 508 (BC_2, IO_W7, input, X),\" & --  PAD47\n\t\" 509 (BC_2, *, controlr, 1),\" &\n\t\" 510 (BC_2, IO_V7, output3, X, 509, 1, Z),\" & --  PAD46\n\t\" 511 (BC_2, IO_V7, input, X),\" & --  PAD46\n\t\" 512 (BC_2, *, controlr, 1),\" &\n\t\" 513 (BC_2, IO_U5, output3, X, 512, 1, Z),\" & --  PAD45\n\t\" 514 (BC_2, IO_U5, input, X),\" & --  PAD45\n\t\" 515 (BC_2, *, controlr, 1),\" &\n\t\" 516 (BC_2, IO_U6, output3, X, 515, 1, Z),\" & --  PAD44\n\t\" 517 (BC_2, IO_U6, input, X),\" & --  PAD44\n\t\" 518 (BC_2, *, controlr, 1),\" &\n\t\" 519 (BC_2, IO_V4, output3, X, 518, 1, Z),\" & --  PAD43\n\t\" 520 (BC_2, IO_V4, input, X),\" & --  PAD43\n\t\" 521 (BC_2, *, controlr, 1),\" &\n\t\" 522 (BC_2, IO_V5, output3, X, 521, 1, Z),\" & --  PAD42\n\t\" 523 (BC_2, IO_V5, input, X),\" & --  PAD42\n\t\" 524 (BC_2, *, controlr, 1),\" &\n\t\" 525 (BC_2, IO_U4, output3, X, 524, 1, Z),\" & --  PAD41\n\t\" 526 (BC_2, IO_U4, input, X),\" & --  PAD41\n\t\" 527 (BC_2, *, controlr, 1),\" &\n\t\" 528 (BC_2, IO_T4, output3, X, 527, 1, Z),\" & --  PAD40\n\t\" 529 (BC_2, IO_T4, input, X),\" & --  PAD40\n\t\" 530 (BC_2, *, controlr, 1),\" &\n\t\" 531 (BC_2, IO_T6, output3, X, 530, 1, Z),\" & --  PAD39\n\t\" 532 (BC_2, IO_T6, input, X),\" & --  PAD39\n\t\" 533 (BC_2, *, controlr, 1),\" &\n\t\" 534 (BC_2, IO_R6, output3, X, 533, 1, Z),\" & --  PAD38\n\t\" 535 (BC_2, IO_R6, input, X),\" & --  PAD38\n\t\" 536 (BC_2, *, controlr, 1),\" &\n\t\" 537 (BC_2, IO_AA4, output3, X, 536, 1, Z),\" & --  PAD37\n\t\" 538 (BC_2, IO_AA4, input, X),\" & --  PAD37\n\t\" 539 (BC_2, *, controlr, 1),\" &\n\t\" 540 (BC_2, IO_Y4, output3, X, 539, 1, Z),\" & --  PAD36\n\t\" 541 (BC_2, IO_Y4, input, X),\" & --  PAD36\n\t\" 542 (BC_2, *, controlr, 1),\" &\n\t\" 543 (BC_2, IO_AB6, output3, X, 542, 1, Z),\" & --  PAD35\n\t\" 544 (BC_2, IO_AB6, input, X),\" & --  PAD35\n\t\" 545 (BC_2, *, controlr, 1),\" &\n\t\" 546 (BC_2, IO_AB7, output3, X, 545, 1, Z),\" & --  PAD34\n\t\" 547 (BC_2, IO_AB7, input, X),\" & --  PAD34\n\t\" 548 (BC_2, *, controlr, 1),\" &\n\t\" 549 (BC_2, IO_AB4, output3, X, 548, 1, Z),\" & --  PAD33\n\t\" 550 (BC_2, IO_AB4, input, X),\" & --  PAD33\n\t\" 551 (BC_2, *, controlr, 1),\" &\n\t\" 552 (BC_2, IO_AB5, output3, X, 551, 1, Z),\" & --  PAD32\n\t\" 553 (BC_2, IO_AB5, input, X),\" & --  PAD32\n\t\" 554 (BC_2, *, controlr, 1),\" &\n\t\" 555 (BC_2, IO_AB1, output3, X, 554, 1, Z),\" & --  PAD31\n\t\" 556 (BC_2, IO_AB1, input, X),\" & --  PAD31\n\t\" 557 (BC_2, *, controlr, 1),\" &\n\t\" 558 (BC_2, IO_AB2, output3, X, 557, 1, Z),\" & --  PAD30\n\t\" 559 (BC_2, IO_AB2, input, X),\" & --  PAD30\n\t\" 560 (BC_2, *, controlr, 1),\" &\n\t\" 561 (BC_2, IO_AA6, output3, X, 560, 1, Z),\" & --  PAD29\n\t\" 562 (BC_2, IO_AA6, input, X),\" & --  PAD29\n\t\" 563 (BC_2, *, controlr, 1),\" &\n\t\" 564 (BC_2, IO_AA7, output3, X, 563, 1, Z),\" & --  PAD28\n\t\" 565 (BC_2, IO_AA7, input, X),\" & --  PAD28\n\t\" 566 (BC_2, *, controlr, 1),\" &\n\t\" 567 (BC_2, IO_Y5, output3, X, 566, 1, Z),\" & --  PAD27\n\t\" 568 (BC_2, IO_Y5, input, X),\" & --  PAD27\n\t\" 569 (BC_2, *, controlr, 1),\" &\n\t\" 570 (BC_2, IO_Y6, output3, X, 569, 1, Z),\" & --  PAD26\n\t\" 571 (BC_2, IO_Y6, input, X),\" & --  PAD26\n\t\" 572 (BC_2, *, controlr, 1),\" &\n\t\" 573 (BC_2, IO_Y8, output3, X, 572, 1, Z),\" & --  PAD25\n\t\" 574 (BC_2, IO_Y8, input, X),\" & --  PAD25\n\t\" 575 (BC_2, *, controlr, 1),\" &\n\t\" 576 (BC_2, IO_Y9, output3, X, 575, 1, Z),\" & --  PAD24\n\t\" 577 (BC_2, IO_Y9, input, X),\" & --  PAD24\n\t\" 578 (BC_2, *, controlr, 1),\" &\n\t\" 579 (BC_2, IO_AA8, output3, X, 578, 1, Z),\" & --  PAD23\n\t\" 580 (BC_2, IO_AA8, input, X),\" & --  PAD23\n\t\" 581 (BC_2, *, controlr, 1),\" &\n\t\" 582 (BC_2, IO_AA9, output3, X, 581, 1, Z),\" & --  PAD22\n\t\" 583 (BC_2, IO_AA9, input, X),\" & --  PAD22\n\t\" 584 (BC_2, *, controlr, 1),\" &\n\t\" 585 (BC_2, IO_Y10, output3, X, 584, 1, Z),\" & --  PAD21\n\t\" 586 (BC_2, IO_Y10, input, X),\" & --  PAD21\n\t\" 587 (BC_2, *, controlr, 1),\" &\n\t\" 588 (BC_2, IO_Y11, output3, X, 587, 1, Z),\" & --  PAD20\n\t\" 589 (BC_2, IO_Y11, input, X),\" & --  PAD20\n\t\" 590 (BC_2, *, controlr, 1),\" &\n\t\" 591 (BC_2, IO_AB9, output3, X, 590, 1, Z),\" & --  PAD19\n\t\" 592 (BC_2, IO_AB9, input, X),\" & --  PAD19\n\t\" 593 (BC_2, *, controlr, 1),\" &\n\t\" 594 (BC_2, IO_AB10, output3, X, 593, 1, Z),\" & --  PAD18\n\t\" 595 (BC_2, IO_AB10, input, X),\" & --  PAD18\n\t\" 596 (BC_2, *, controlr, 1),\" &\n\t\" 597 (BC_2, IO_AB11, output3, X, 596, 1, Z),\" & --  PAD17\n\t\" 598 (BC_2, IO_AB11, input, X),\" & --  PAD17\n\t\" 599 (BC_2, *, controlr, 1),\" &\n\t\" 600 (BC_2, IO_AA11, output3, X, 599, 1, Z),\" & --  PAD16\n\t\" 601 (BC_2, IO_AA11, input, X),\" & --  PAD16\n\t\" 602 (BC_2, *, controlr, 1),\" &\n\t\" 603 (BC_2, IO_AB12, output3, X, 602, 1, Z),\" & --  PAD15\n\t\" 604 (BC_2, IO_AB12, input, X),\" & --  PAD15\n\t\" 605 (BC_2, *, controlr, 1),\" &\n\t\" 606 (BC_2, IO_AA12, output3, X, 605, 1, Z),\" & --  PAD14\n\t\" 607 (BC_2, IO_AA12, input, X),\" & --  PAD14\n\t\" 608 (BC_2, *, controlr, 1),\" &\n\t\" 609 (BC_2, IO_U9, output3, X, 608, 1, Z),\" & --  PAD13\n\t\" 610 (BC_2, IO_U9, input, X),\" & --  PAD13\n\t\" 611 (BC_2, *, controlr, 1),\" &\n\t\" 612 (BC_2, IO_U10, output3, X, 611, 1, Z),\" & --  PAD12\n\t\" 613 (BC_2, IO_U10, input, X),\" & --  PAD12\n\t\" 614 (BC_2, *, controlr, 1),\" &\n\t\" 615 (BC_2, IO_U11, output3, X, 614, 1, Z),\" & --  PAD11\n\t\" 616 (BC_2, IO_U11, input, X),\" & --  PAD11\n\t\" 617 (BC_2, *, controlr, 1),\" &\n\t\" 618 (BC_2, IO_U12, output3, X, 617, 1, Z),\" & --  PAD10\n\t\" 619 (BC_2, IO_U12, input, X),\" & --  PAD10\n\t\" 620 (BC_2, *, controlr, 1),\" &\n\t\" 621 (BC_2, IO_W12, output3, X, 620, 1, Z),\" & --  PAD9\n\t\" 622 (BC_2, IO_W12, input, X),\" & --  PAD9\n\t\" 623 (BC_2, *, controlr, 1),\" &\n\t\" 624 (BC_2, IO_V12, output3, X, 623, 1, Z),\" & --  PAD8\n\t\" 625 (BC_2, IO_V12, input, X),\" & --  PAD8\n\t\" 626 (BC_2, *, controlr, 1),\" &\n\t\" 627 (BC_2, IO_W10, output3, X, 626, 1, Z),\" & --  PAD7\n\t\" 628 (BC_2, IO_W10, input, X),\" & --  PAD7\n\t\" 629 (BC_2, *, controlr, 1),\" &\n\t\" 630 (BC_2, IO_W11, output3, X, 629, 1, Z),\" & --  PAD6\n\t\" 631 (BC_2, IO_W11, input, X),\" & --  PAD6\n\t\" 632 (BC_2, *, controlr, 1),\" &\n\t\" 633 (BC_2, IO_W8, output3, X, 632, 1, Z),\" & --  PAD5\n\t\" 634 (BC_2, IO_W8, input, X),\" & --  PAD5\n\t\" 635 (BC_2, *, controlr, 1),\" &\n\t\" 636 (BC_2, IO_V8, output3, X, 635, 1, Z),\" & --  PAD4\n\t\" 637 (BC_2, IO_V8, input, X),\" & --  PAD4\n\t\" 638 (BC_2, *, controlr, 1),\" &\n\t\" 639 (BC_2, IO_V9, output3, X, 638, 1, Z),\" & --  PAD3\n\t\" 640 (BC_2, IO_V9, input, X),\" & --  PAD3\n\t\" 641 (BC_2, *, controlr, 1),\" &\n\t\" 642 (BC_2, IO_V10, output3, X, 641, 1, Z),\" & --  PAD2\n\t\" 643 (BC_2, IO_V10, input, X),\" & --  PAD2\n\t\" 644 (BC_2, *, controlr, 1),\" &\n\t\" 645 (BC_2, IO_R7, output3, X, 644, 1, Z),\" & --  PAD1\n\t\" 646 (BC_2, IO_R7, input, X),\" & --  PAD1\n\t\" 647 (BC_2, *, controlr, 1),\" &\n\t\" 648 (BC_2, PS_DDR_DQ31, output3, X, 647, 1, Z),\" &\n\t\" 649 (BC_2, PS_DDR_DQ31, input, X),\" &\n\t\" 650 (BC_2, *, controlr, 1),\" &\n\t\" 651 (BC_2, PS_DDR_DQ30, output3, X, 650, 1, Z),\" &\n\t\" 652 (BC_2, PS_DDR_DQ30, input, X),\" &\n\t\" 653 (BC_2, *, controlr, 1),\" &\n\t\" 654 (BC_2, PS_DDR_DQ29, output3, X, 653, 1, Z),\" &\n\t\" 655 (BC_2, PS_DDR_DQ29, input, X),\" &\n\t\" 656 (BC_2, *, controlr, 1),\" &\n\t\" 657 (BC_2, PS_DDR_DQ28, output3, X, 656, 1, Z),\" &\n\t\" 658 (BC_2, PS_DDR_DQ28, input, X),\" &\n\t\" 659 (BC_2, *, controlr, 1),\" &\n\t\" 660 (BC_2, PS_DDR_DQS_N3, output3, X, 659, 1, Z),\" &\n\t\" 661 (BC_2, PS_DDR_DQS_N3, input, X),\" &\n\t\" 662 (BC_2, *, controlr, 1),\" &\n\t\" 663 (BC_2, PS_DDR_DQS_P3, output3, X, 662, 1, Z),\" &\n\t\" 664 (BC_2, PS_DDR_DQS_P3, input, X),\" &\n\t\" 665 (BC_2, *, internal, 1),\" &\n\t\" 666 (BC_2, *, internal, X),\" &\n\t\" 667 (BC_2, *, internal, X),\" &\n\t\" 668 (BC_2, *, controlr, 1),\" &\n\t\" 669 (BC_2, PS_DDR_DM3, output3, X, 668, 1, Z),\" &\n\t\" 670 (BC_2, PS_DDR_DM3, input, X),\" &\n\t\" 671 (BC_2, *, controlr, 1),\" &\n\t\" 672 (BC_2, PS_DDR_DQ27, output3, X, 671, 1, Z),\" &\n\t\" 673 (BC_2, PS_DDR_DQ27, input, X),\" &\n\t\" 674 (BC_2, *, controlr, 1),\" &\n\t\" 675 (BC_2, PS_DDR_DQ26, output3, X, 674, 1, Z),\" &\n\t\" 676 (BC_2, PS_DDR_DQ26, input, X),\" &\n\t\" 677 (BC_2, *, controlr, 1),\" &\n\t\" 678 (BC_2, PS_DDR_DQ25, output3, X, 677, 1, Z),\" &\n\t\" 679 (BC_2, PS_DDR_DQ25, input, X),\" &\n\t\" 680 (BC_2, *, controlr, 1),\" &\n\t\" 681 (BC_2, PS_DDR_DQ24, output3, X, 680, 1, Z),\" &\n\t\" 682 (BC_2, PS_DDR_DQ24, input, X),\" &\n\t\" 683 (BC_2, *, internal, X),\" &\n\t\" 684 (BC_2, *, internal, X),\" &\n\t\" 685 (BC_2, *, internal, X),\" &\n\t\" 686 (BC_2, *, internal, 1),\" &\n\t\" 687 (BC_2, *, internal, X),\" &\n\t\" 688 (BC_2, *, internal, X),\" &\n\t\" 689 (BC_2, *, controlr, 1),\" &\n\t\" 690 (BC_2, PS_DDR_DQ23, output3, X, 689, 1, Z),\" &\n\t\" 691 (BC_2, PS_DDR_DQ23, input, X),\" &\n\t\" 692 (BC_2, *, controlr, 1),\" &\n\t\" 693 (BC_2, PS_DDR_DQ22, output3, X, 692, 1, Z),\" &\n\t\" 694 (BC_2, PS_DDR_DQ22, input, X),\" &\n\t\" 695 (BC_2, *, controlr, 1),\" &\n\t\" 696 (BC_2, PS_DDR_DQ21, output3, X, 695, 1, Z),\" &\n\t\" 697 (BC_2, PS_DDR_DQ21, input, X),\" &\n\t\" 698 (BC_2, *, controlr, 1),\" &\n\t\" 699 (BC_2, PS_DDR_DQ20, output3, X, 698, 1, Z),\" &\n\t\" 700 (BC_2, PS_DDR_DQ20, input, X),\" &\n\t\" 701 (BC_2, *, controlr, 1),\" &\n\t\" 702 (BC_2, PS_DDR_DQS_N2, output3, X, 701, 1, Z),\" &\n\t\" 703 (BC_2, PS_DDR_DQS_N2, input, X),\" &\n\t\" 704 (BC_2, *, controlr, 1),\" &\n\t\" 705 (BC_2, PS_DDR_DQS_P2, output3, X, 704, 1, Z),\" &\n\t\" 706 (BC_2, PS_DDR_DQS_P2, input, X),\" &\n\t\" 707 (BC_2, *, internal, 1),\" &\n\t\" 708 (BC_2, *, internal, X),\" &\n\t\" 709 (BC_2, *, internal, X),\" &\n\t\" 710 (BC_2, *, controlr, 1),\" &\n\t\" 711 (BC_2, PS_DDR_DM2, output3, X, 710, 1, Z),\" &\n\t\" 712 (BC_2, PS_DDR_DM2, input, X),\" &\n\t\" 713 (BC_2, *, controlr, 1),\" &\n\t\" 714 (BC_2, PS_DDR_DQ19, output3, X, 713, 1, Z),\" &\n\t\" 715 (BC_2, PS_DDR_DQ19, input, X),\" &\n\t\" 716 (BC_2, *, controlr, 1),\" &\n\t\" 717 (BC_2, PS_DDR_DQ18, output3, X, 716, 1, Z),\" &\n\t\" 718 (BC_2, PS_DDR_DQ18, input, X),\" &\n\t\" 719 (BC_2, *, controlr, 1),\" &\n\t\" 720 (BC_2, PS_DDR_DQ17, output3, X, 719, 1, Z),\" &\n\t\" 721 (BC_2, PS_DDR_DQ17, input, X),\" &\n\t\" 722 (BC_2, *, controlr, 1),\" &\n\t\" 723 (BC_2, PS_DDR_DQ16, output3, X, 722, 1, Z),\" &\n\t\" 724 (BC_2, PS_DDR_DQ16, input, X),\" &\n\t\" 725 (BC_2, *, controlr, 1),\" &\n\t\" 726 (BC_2, PS_DDR_RAS_B, output3, X, 725, 1, Z),\" &\n\t\" 727 (BC_2, PS_DDR_RAS_B, input, X),\" &\n\t\" 728 (BC_2, *, controlr, 1),\" &\n\t\" 729 (BC_2, PS_DDR_CAS_B, output3, X, 728, 1, Z),\" &\n\t\" 730 (BC_2, PS_DDR_CAS_B, input, X),\" &\n\t\" 731 (BC_2, *, controlr, 1),\" &\n\t\" 732 (BC_2, PS_DDR_WE_B, output3, X, 731, 1, Z),\" &\n\t\" 733 (BC_2, PS_DDR_WE_B, input, X),\" &\n\t\" 734 (BC_2, *, controlr, 1),\" &\n\t\" 735 (BC_2, PS_DDR_CKE, output3, X, 734, 1, Z),\" &\n\t\" 736 (BC_2, PS_DDR_CKE, input, X),\" &\n\t\" 737 (BC_2, *, controlr, 1),\" &\n\t\" 738 (BC_2, PS_DDR_CS_B, output3, X, 737, 1, Z),\" &\n\t\" 739 (BC_2, PS_DDR_CS_B, input, X),\" &\n\t\" 740 (BC_2, *, controlr, 1),\" &\n\t\" 741 (BC_2, PS_DDR_ODT, output3, X, 740, 1, Z),\" &\n\t\" 742 (BC_2, PS_DDR_ODT, input, X),\" &\n\t\" 743 (BC_2, *, controlr, 1),\" &\n\t\" 744 (BC_2, PS_DDR_BA0, output3, X, 743, 1, Z),\" &\n\t\" 745 (BC_2, PS_DDR_BA0, input, X),\" &\n\t\" 746 (BC_2, *, controlr, 1),\" &\n\t\" 747 (BC_2, PS_DDR_BA1, output3, X, 746, 1, Z),\" &\n\t\" 748 (BC_2, PS_DDR_BA1, input, X),\" &\n\t\" 749 (BC_2, *, controlr, 1),\" &\n\t\" 750 (BC_2, PS_DDR_BA2, output3, X, 749, 1, Z),\" &\n\t\" 751 (BC_2, PS_DDR_BA2, input, X),\" &\n\t\" 752 (BC_2, *, controlr, 1),\" &\n\t\" 753 (BC_2, PS_DDR_A0, output3, X, 752, 1, Z),\" &\n\t\" 754 (BC_2, PS_DDR_A0, input, X),\" &\n\t\" 755 (BC_2, *, controlr, 1),\" &\n\t\" 756 (BC_2, PS_DDR_A1, output3, X, 755, 1, Z),\" &\n\t\" 757 (BC_2, PS_DDR_A1, input, X),\" &\n\t\" 758 (BC_2, *, controlr, 1),\" &\n\t\" 759 (BC_2, PS_DDR_A2, output3, X, 758, 1, Z),\" &\n\t\" 760 (BC_2, PS_DDR_A2, input, X),\" &\n\t\" 761 (BC_2, *, controlr, 1),\" &\n\t\" 762 (BC_2, PS_DDR_CKN, output3, X, 761, 1, Z),\" &\n\t\" 763 (BC_2, PS_DDR_CKN, input, X),\" &\n\t\" 764 (BC_2, *, controlr, 1),\" &\n\t\" 765 (BC_2, PS_DDR_CKP, output3, X, 764, 1, Z),\" &\n\t\" 766 (BC_2, PS_DDR_CKP, input, X),\" &\n\t\" 767 (BC_2, *, controlr, 1),\" &\n\t\" 768 (BC_2, PS_DDR_VRN, output3, X, 767, 1, Z),\" &\n\t\" 769 (BC_2, PS_DDR_VRN, input, X),\" &\n\t\" 770 (BC_2, *, controlr, 1),\" &\n\t\" 771 (BC_2, PS_DDR_VRP, output3, X, 770, 1, Z),\" &\n\t\" 772 (BC_2, PS_DDR_VRP, input, X),\" &\n\t\" 773 (BC_2, *, controlr, 1),\" &\n\t\" 774 (BC_2, PS_DDR_A3, output3, X, 773, 1, Z),\" &\n\t\" 775 (BC_2, PS_DDR_A3, input, X),\" &\n\t\" 776 (BC_2, *, controlr, 1),\" &\n\t\" 777 (BC_2, PS_DDR_A4, output3, X, 776, 1, Z),\" &\n\t\" 778 (BC_2, PS_DDR_A4, input, X),\" &\n\t\" 779 (BC_2, *, controlr, 1),\" &\n\t\" 780 (BC_2, PS_DDR_A5, output3, X, 779, 1, Z),\" &\n\t\" 781 (BC_2, PS_DDR_A5, input, X),\" &\n\t\" 782 (BC_2, *, controlr, 1),\" &\n\t\" 783 (BC_2, PS_DDR_A6, output3, X, 782, 1, Z),\" &\n\t\" 784 (BC_2, PS_DDR_A6, input, X),\" &\n\t\" 785 (BC_2, *, controlr, 1),\" &\n\t\" 786 (BC_2, PS_DDR_A7, output3, X, 785, 1, Z),\" &\n\t\" 787 (BC_2, PS_DDR_A7, input, X),\" &\n\t\" 788 (BC_2, *, controlr, 1),\" &\n\t\" 789 (BC_2, PS_DDR_A8, output3, X, 788, 1, Z),\" &\n\t\" 790 (BC_2, PS_DDR_A8, input, X),\" &\n\t\" 791 (BC_2, *, controlr, 1),\" &\n\t\" 792 (BC_2, PS_DDR_A9, output3, X, 791, 1, Z),\" &\n\t\" 793 (BC_2, PS_DDR_A9, input, X),\" &\n\t\" 794 (BC_2, *, controlr, 1),\" &\n\t\" 795 (BC_2, PS_DDR_A10, output3, X, 794, 1, Z),\" &\n\t\" 796 (BC_2, PS_DDR_A10, input, X),\" &\n\t\" 797 (BC_2, *, controlr, 1),\" &\n\t\" 798 (BC_2, PS_DDR_A11, output3, X, 797, 1, Z),\" &\n\t\" 799 (BC_2, PS_DDR_A11, input, X),\" &\n\t\" 800 (BC_2, *, controlr, 1),\" &\n\t\" 801 (BC_2, PS_DDR_A12, output3, X, 800, 1, Z),\" &\n\t\" 802 (BC_2, PS_DDR_A12, input, X),\" &\n\t\" 803 (BC_2, *, controlr, 1),\" &\n\t\" 804 (BC_2, PS_DDR_A13, output3, X, 803, 1, Z),\" &\n\t\" 805 (BC_2, PS_DDR_A13, input, X),\" &\n\t\" 806 (BC_2, *, controlr, 1),\" &\n\t\" 807 (BC_2, PS_DDR_A14, output3, X, 806, 1, Z),\" &\n\t\" 808 (BC_2, PS_DDR_A14, input, X),\" &\n\t\" 809 (BC_2, *, controlr, 1),\" &\n\t\" 810 (BC_2, PS_DDR_DQ15, output3, X, 809, 1, Z),\" &\n\t\" 811 (BC_2, PS_DDR_DQ15, input, X),\" &\n\t\" 812 (BC_2, *, controlr, 1),\" &\n\t\" 813 (BC_2, PS_DDR_DQ14, output3, X, 812, 1, Z),\" &\n\t\" 814 (BC_2, PS_DDR_DQ14, input, X),\" &\n\t\" 815 (BC_2, *, controlr, 1),\" &\n\t\" 816 (BC_2, PS_DDR_DQ13, output3, X, 815, 1, Z),\" &\n\t\" 817 (BC_2, PS_DDR_DQ13, input, X),\" &\n\t\" 818 (BC_2, *, controlr, 1),\" &\n\t\" 819 (BC_2, PS_DDR_DQ12, output3, X, 818, 1, Z),\" &\n\t\" 820 (BC_2, PS_DDR_DQ12, input, X),\" &\n\t\" 821 (BC_2, *, controlr, 1),\" &\n\t\" 822 (BC_2, PS_DDR_DQS_N1, output3, X, 821, 1, Z),\" &\n\t\" 823 (BC_2, PS_DDR_DQS_N1, input, X),\" &\n\t\" 824 (BC_2, *, controlr, 1),\" &\n\t\" 825 (BC_2, PS_DDR_DQS_P1, output3, X, 824, 1, Z),\" &\n\t\" 826 (BC_2, PS_DDR_DQS_P1, input, X),\" &\n\t\" 827 (BC_2, *, internal, 1),\" &\n\t\" 828 (BC_2, *, internal, X),\" &\n\t\" 829 (BC_2, *, internal, X),\" &\n\t\" 830 (BC_2, *, controlr, 1),\" &\n\t\" 831 (BC_2, PS_DDR_DM1, output3, X, 830, 1, Z),\" &\n\t\" 832 (BC_2, PS_DDR_DM1, input, X),\" &\n\t\" 833 (BC_2, *, controlr, 1),\" &\n\t\" 834 (BC_2, PS_DDR_DQ11, output3, X, 833, 1, Z),\" &\n\t\" 835 (BC_2, PS_DDR_DQ11, input, X),\" &\n\t\" 836 (BC_2, *, controlr, 1),\" &\n\t\" 837 (BC_2, PS_DDR_DQ10, output3, X, 836, 1, Z),\" &\n\t\" 838 (BC_2, PS_DDR_DQ10, input, X),\" &\n\t\" 839 (BC_2, *, controlr, 1),\" &\n\t\" 840 (BC_2, PS_DDR_DQ9, output3, X, 839, 1, Z),\" &\n\t\" 841 (BC_2, PS_DDR_DQ9, input, X),\" &\n\t\" 842 (BC_2, *, controlr, 1),\" &\n\t\" 843 (BC_2, PS_DDR_DQ8, output3, X, 842, 1, Z),\" &\n\t\" 844 (BC_2, PS_DDR_DQ8, input, X),\" &\n\t\" 845 (BC_2, *, internal, X),\" &\n\t\" 846 (BC_2, *, internal, X),\" &\n\t\" 847 (BC_2, *, internal, X),\" &\n\t\" 848 (BC_2, *, internal, 1),\" &\n\t\" 849 (BC_2, *, internal, X),\" &\n\t\" 850 (BC_2, *, internal, X),\" &\n\t\" 851 (BC_2, *, controlr, 1),\" &\n\t\" 852 (BC_2, PS_DDR_DQ7, output3, X, 851, 1, Z),\" &\n\t\" 853 (BC_2, PS_DDR_DQ7, input, X),\" &\n\t\" 854 (BC_2, *, controlr, 1),\" &\n\t\" 855 (BC_2, PS_DDR_DQ6, output3, X, 854, 1, Z),\" &\n\t\" 856 (BC_2, PS_DDR_DQ6, input, X),\" &\n\t\" 857 (BC_2, *, controlr, 1),\" &\n\t\" 858 (BC_2, PS_DDR_DQ5, output3, X, 857, 1, Z),\" &\n\t\" 859 (BC_2, PS_DDR_DQ5, input, X),\" &\n\t\" 860 (BC_2, *, controlr, 1),\" &\n\t\" 861 (BC_2, PS_DDR_DQ4, output3, X, 860, 1, Z),\" &\n\t\" 862 (BC_2, PS_DDR_DQ4, input, X),\" &\n\t\" 863 (BC_2, *, controlr, 1),\" &\n\t\" 864 (BC_2, PS_DDR_DQS_N0, output3, X, 863, 1, Z),\" &\n\t\" 865 (BC_2, PS_DDR_DQS_N0, input, X),\" &\n\t\" 866 (BC_2, *, controlr, 1),\" &\n\t\" 867 (BC_2, PS_DDR_DQS_P0, output3, X, 866, 1, Z),\" &\n\t\" 868 (BC_2, PS_DDR_DQS_P0, input, X),\" &\n\t\" 869 (BC_2, *, internal, 1),\" &\n\t\" 870 (BC_2, *, internal, X),\" &\n\t\" 871 (BC_2, *, internal, X),\" &\n\t\" 872 (BC_2, *, controlr, 1),\" &\n\t\" 873 (BC_2, PS_DDR_DM0, output3, X, 872, 1, Z),\" &\n\t\" 874 (BC_2, PS_DDR_DM0, input, X),\" &\n\t\" 875 (BC_2, *, controlr, 1),\" &\n\t\" 876 (BC_2, PS_DDR_DQ3, output3, X, 875, 1, Z),\" &\n\t\" 877 (BC_2, PS_DDR_DQ3, input, X),\" &\n\t\" 878 (BC_2, *, controlr, 1),\" &\n\t\" 879 (BC_2, PS_DDR_DQ2, output3, X, 878, 1, Z),\" &\n\t\" 880 (BC_2, PS_DDR_DQ2, input, X),\" &\n\t\" 881 (BC_2, *, controlr, 1),\" &\n\t\" 882 (BC_2, PS_DDR_DQ1, output3, X, 881, 1, Z),\" &\n\t\" 883 (BC_2, PS_DDR_DQ1, input, X),\" &\n\t\" 884 (BC_2, *, controlr, 1),\" &\n\t\" 885 (BC_2, PS_DDR_DQ0, output3, X, 884, 1, Z),\" &\n\t\" 886 (BC_2, PS_DDR_DQ0, input, X),\" &\n\t\" 887 (BC_2, *, controlr, 1),\" &\n\t\" 888 (BC_2, PS_DDR_DRST_B, output3, X, 887, 1, Z),\" &\n\t\" 889 (BC_2, PS_DDR_DRST_B, input, X),\" &\n\t\" 890 (BC_2, *, controlr, 1),\" &\n\t\" 891 (BC_2, PS_MIO0, output3, X, 890, 1, Z),\" &\n\t\" 892 (BC_2, PS_MIO0, input, X),\" &\n\t\" 893 (BC_2, *, controlr, 1),\" &\n\t\" 894 (BC_2, PS_MIO1, output3, X, 893, 1, Z),\" &\n\t\" 895 (BC_2, PS_MIO1, input, X),\" &\n\t\" 896 (BC_2, *, controlr, 1),\" &\n\t\" 897 (BC_2, PS_MIO2, output3, X, 896, 1, Z),\" &\n\t\" 898 (BC_2, PS_MIO2, input, X),\" &\n\t\" 899 (BC_2, *, controlr, 1),\" &\n\t\" 900 (BC_2, PS_MIO3, output3, X, 899, 1, Z),\" &\n\t\" 901 (BC_2, PS_MIO3, input, X),\" &\n\t\" 902 (BC_2, *, controlr, 1),\" &\n\t\" 903 (BC_2, PS_MIO4, output3, X, 902, 1, Z),\" &\n\t\" 904 (BC_2, PS_MIO4, input, X),\" &\n\t\" 905 (BC_2, *, controlr, 1),\" &\n\t\" 906 (BC_2, PS_MIO5, output3, X, 905, 1, Z),\" &\n\t\" 907 (BC_2, PS_MIO5, input, X),\" &\n\t\" 908 (BC_2, *, controlr, 1),\" &\n\t\" 909 (BC_2, PS_MIO6, output3, X, 908, 1, Z),\" &\n\t\" 910 (BC_2, PS_MIO6, input, X),\" &\n\t\" 911 (BC_2, *, controlr, 1),\" &\n\t\" 912 (BC_2, PS_MIO7, output3, X, 911, 1, Z),\" &\n\t\" 913 (BC_2, PS_MIO7, input, X),\" &\n\t\" 914 (BC_2, *, controlr, 1),\" &\n\t\" 915 (BC_2, PS_MIO8, output3, X, 914, 1, Z),\" &\n\t\" 916 (BC_2, PS_MIO8, input, X),\" &\n\t\" 917 (BC_2, *, controlr, 1),\" &\n\t\" 918 (BC_2, PS_MIO9, output3, X, 917, 1, Z),\" &\n\t\" 919 (BC_2, PS_MIO9, input, X),\" &\n\t\" 920 (BC_2, *, controlr, 1),\" &\n\t\" 921 (BC_2, PS_MIO10, output3, X, 920, 1, Z),\" &\n\t\" 922 (BC_2, PS_MIO10, input, X),\" &\n\t\" 923 (BC_2, *, controlr, 1),\" &\n\t\" 924 (BC_2, PS_MIO11, output3, X, 923, 1, Z),\" &\n\t\" 925 (BC_2, PS_MIO11, input, X),\" &\n\t\" 926 (BC_2, *, controlr, 1),\" &\n\t\" 927 (BC_2, PS_MIO12, output3, X, 926, 1, Z),\" &\n\t\" 928 (BC_2, PS_MIO12, input, X),\" &\n\t\" 929 (BC_2, *, controlr, 1),\" &\n\t\" 930 (BC_2, PS_MIO13, output3, X, 929, 1, Z),\" &\n\t\" 931 (BC_2, PS_MIO13, input, X),\" &\n\t\" 932 (BC_2, *, controlr, 1),\" &\n\t\" 933 (BC_2, PS_MIO14, output3, X, 932, 1, Z),\" &\n\t\" 934 (BC_2, PS_MIO14, input, X),\" &\n\t\" 935 (BC_2, *, controlr, 1),\" &\n\t\" 936 (BC_2, PS_MIO15, output3, X, 935, 1, Z),\" &\n\t\" 937 (BC_2, PS_MIO15, input, X),\" &\n\t\" 938 (BC_2, *, internal, 1),\" &\n\t\" 939 (BC_2, *, internal, X),\" &\n\t\" 940 (BC_2, PS_POR_B, input, X),\" &\n\t\" 941 (BC_2, *, internal, 1),\" &\n\t\" 942 (BC_2, *, internal, X),\" &\n\t\" 943 (BC_2, PS_CLK, input, X),\" &\n\t\" 944 (BC_2, *, controlr, 1),\" &\n\t\" 945 (BC_2, PS_MIO16, output3, X, 944, 1, Z),\" &\n\t\" 946 (BC_2, PS_MIO16, input, X),\" &\n\t\" 947 (BC_2, *, controlr, 1),\" &\n\t\" 948 (BC_2, PS_MIO17, output3, X, 947, 1, Z),\" &\n\t\" 949 (BC_2, PS_MIO17, input, X),\" &\n\t\" 950 (BC_2, *, controlr, 1),\" &\n\t\" 951 (BC_2, PS_MIO18, output3, X, 950, 1, Z),\" &\n\t\" 952 (BC_2, PS_MIO18, input, X),\" &\n\t\" 953 (BC_2, *, controlr, 1),\" &\n\t\" 954 (BC_2, PS_MIO19, output3, X, 953, 1, Z),\" &\n\t\" 955 (BC_2, PS_MIO19, input, X),\" &\n\t\" 956 (BC_2, *, controlr, 1),\" &\n\t\" 957 (BC_2, PS_MIO20, output3, X, 956, 1, Z),\" &\n\t\" 958 (BC_2, PS_MIO20, input, X),\" &\n\t\" 959 (BC_2, *, controlr, 1),\" &\n\t\" 960 (BC_2, PS_MIO21, output3, X, 959, 1, Z),\" &\n\t\" 961 (BC_2, PS_MIO21, input, X),\" &\n\t\" 962 (BC_2, *, controlr, 1),\" &\n\t\" 963 (BC_2, PS_MIO22, output3, X, 962, 1, Z),\" &\n\t\" 964 (BC_2, PS_MIO22, input, X),\" &\n\t\" 965 (BC_2, *, controlr, 1),\" &\n\t\" 966 (BC_2, PS_MIO23, output3, X, 965, 1, Z),\" &\n\t\" 967 (BC_2, PS_MIO23, input, X),\" &\n\t\" 968 (BC_2, *, controlr, 1),\" &\n\t\" 969 (BC_2, PS_MIO24, output3, X, 968, 1, Z),\" &\n\t\" 970 (BC_2, PS_MIO24, input, X),\" &\n\t\" 971 (BC_2, *, controlr, 1),\" &\n\t\" 972 (BC_2, PS_MIO25, output3, X, 971, 1, Z),\" &\n\t\" 973 (BC_2, PS_MIO25, input, X),\" &\n\t\" 974 (BC_2, *, controlr, 1),\" &\n\t\" 975 (BC_2, PS_MIO26, output3, X, 974, 1, Z),\" &\n\t\" 976 (BC_2, PS_MIO26, input, X),\" &\n\t\" 977 (BC_2, *, controlr, 1),\" &\n\t\" 978 (BC_2, PS_MIO27, output3, X, 977, 1, Z),\" &\n\t\" 979 (BC_2, PS_MIO27, input, X),\" &\n\t\" 980 (BC_2, *, controlr, 1),\" &\n\t\" 981 (BC_2, PS_MIO28, output3, X, 980, 1, Z),\" &\n\t\" 982 (BC_2, PS_MIO28, input, X),\" &\n\t\" 983 (BC_2, *, controlr, 1),\" &\n\t\" 984 (BC_2, PS_MIO29, output3, X, 983, 1, Z),\" &\n\t\" 985 (BC_2, PS_MIO29, input, X),\" &\n\t\" 986 (BC_2, *, controlr, 1),\" &\n\t\" 987 (BC_2, PS_MIO30, output3, X, 986, 1, Z),\" &\n\t\" 988 (BC_2, PS_MIO30, input, X),\" &\n\t\" 989 (BC_2, *, controlr, 1),\" &\n\t\" 990 (BC_2, PS_MIO31, output3, X, 989, 1, Z),\" &\n\t\" 991 (BC_2, PS_MIO31, input, X),\" &\n\t\" 992 (BC_2, *, controlr, 1),\" &\n\t\" 993 (BC_2, PS_MIO32, output3, X, 992, 1, Z),\" &\n\t\" 994 (BC_2, PS_MIO32, input, X),\" &\n\t\" 995 (BC_2, *, controlr, 1),\" &\n\t\" 996 (BC_2, PS_MIO33, output3, X, 995, 1, Z),\" &\n\t\" 997 (BC_2, PS_MIO33, input, X),\" &\n\t\" 998 (BC_2, *, controlr, 1),\" &\n\t\" 999 (BC_2, PS_MIO34, output3, X, 998, 1, Z),\" &\n\t\"1000 (BC_2, PS_MIO34, input, X),\" &\n\t\"1001 (BC_2, *, controlr, 1),\" &\n\t\"1002 (BC_2, PS_MIO35, output3, X, 1001, 1, Z),\" &\n\t\"1003 (BC_2, PS_MIO35, input, X),\" &\n\t\"1004 (BC_2, *, controlr, 1),\" &\n\t\"1005 (BC_2, PS_MIO36, output3, X, 1004, 1, Z),\" &\n\t\"1006 (BC_2, PS_MIO36, input, X),\" &\n\t\"1007 (BC_2, *, internal, 1),\" &\n\t\"1008 (BC_2, *, internal, X),\" &\n\t\"1009 (BC_2, PS_MIO_VREF, input, X),\" &\n\t\"1010 (BC_2, *, controlr, 1),\" &\n\t\"1011 (BC_2, PS_MIO37, output3, X, 1010, 1, Z),\" &\n\t\"1012 (BC_2, PS_MIO37, input, X),\" &\n\t\"1013 (BC_2, *, controlr, 1),\" &\n\t\"1014 (BC_2, PS_MIO38, output3, X, 1013, 1, Z),\" &\n\t\"1015 (BC_2, PS_MIO38, input, X),\" &\n\t\"1016 (BC_2, *, controlr, 1),\" &\n\t\"1017 (BC_2, PS_MIO39, output3, X, 1016, 1, Z),\" &\n\t\"1018 (BC_2, PS_MIO39, input, X),\" &\n\t\"1019 (BC_2, *, controlr, 1),\" &\n\t\"1020 (BC_2, PS_MIO40, output3, X, 1019, 1, Z),\" &\n\t\"1021 (BC_2, PS_MIO40, input, X),\" &\n\t\"1022 (BC_2, *, controlr, 1),\" &\n\t\"1023 (BC_2, PS_MIO41, output3, X, 1022, 1, Z),\" &\n\t\"1024 (BC_2, PS_MIO41, input, X),\" &\n\t\"1025 (BC_2, *, controlr, 1),\" &\n\t\"1026 (BC_2, PS_MIO42, output3, X, 1025, 1, Z),\" &\n\t\"1027 (BC_2, PS_MIO42, input, X),\" &\n\t\"1028 (BC_2, *, controlr, 1),\" &\n\t\"1029 (BC_2, PS_MIO43, output3, X, 1028, 1, Z),\" &\n\t\"1030 (BC_2, PS_MIO43, input, X),\" &\n\t\"1031 (BC_2, *, controlr, 1),\" &\n\t\"1032 (BC_2, PS_MIO44, output3, X, 1031, 1, Z),\" &\n\t\"1033 (BC_2, PS_MIO44, input, X),\" &\n\t\"1034 (BC_2, *, controlr, 1),\" &\n\t\"1035 (BC_2, PS_MIO45, output3, X, 1034, 1, Z),\" &\n\t\"1036 (BC_2, PS_MIO45, input, X),\" &\n\t\"1037 (BC_2, *, controlr, 1),\" &\n\t\"1038 (BC_2, PS_MIO46, output3, X, 1037, 1, Z),\" &\n\t\"1039 (BC_2, PS_MIO46, input, X),\" &\n\t\"1040 (BC_2, *, controlr, 1),\" &\n\t\"1041 (BC_2, PS_MIO47, output3, X, 1040, 1, Z),\" &\n\t\"1042 (BC_2, PS_MIO47, input, X),\" &\n\t\"1043 (BC_2, *, controlr, 1),\" &\n\t\"1044 (BC_2, PS_MIO48, output3, X, 1043, 1, Z),\" &\n\t\"1045 (BC_2, PS_MIO48, input, X),\" &\n\t\"1046 (BC_2, *, controlr, 1),\" &\n\t\"1047 (BC_2, PS_MIO49, output3, X, 1046, 1, Z),\" &\n\t\"1048 (BC_2, PS_MIO49, input, X),\" &\n\t\"1049 (BC_2, *, controlr, 1),\" &\n\t\"1050 (BC_2, PS_MIO50, output3, X, 1049, 1, Z),\" &\n\t\"1051 (BC_2, PS_MIO50, input, X),\" &\n\t\"1052 (BC_2, *, controlr, 1),\" &\n\t\"1053 (BC_2, PS_MIO51, output3, X, 1052, 1, Z),\" &\n\t\"1054 (BC_2, PS_MIO51, input, X),\" &\n\t\"1055 (BC_2, *, controlr, 1),\" &\n\t\"1056 (BC_2, PS_MIO52, output3, X, 1055, 1, Z),\" &\n\t\"1057 (BC_2, PS_MIO52, input, X),\" &\n\t\"1058 (BC_2, *, controlr, 1),\" &\n\t\"1059 (BC_2, PS_MIO53, output3, X, 1058, 1, Z),\" &\n\t\"1060 (BC_2, PS_MIO53, input, X),\" &\n\t\"1061 (BC_2, *, internal, 1),\" &\n\t\"1062 (BC_2, *, internal, X),\" &\n\t\"1063 (BC_2, PS_SRST_B, input, X),\" &\n\t\"1064 (BC_2, *, internal, X),\" &\n\t\"1065 (BC_2, *, internal, X),\" &\n\t\"1066 (BC_2, *, internal, X),\" &\n\t\"1067 (BC_2, *, internal, X),\" &\n\t\"1068 (BC_2, *, internal, X),\" &\n\t\"1069 (BC_2, *, internal, X),\" &\n\t\"1070 (BC_2, *, internal, X),\" &\n\t\"1071 (BC_2, *, internal, X),\" &\n\t\"1072 (BC_2, *, internal, X),\" &\n\t\"1073 (BC_2, *, internal, X),\" &\n\t\"1074 (BC_2, *, internal, X),\" &\n\t\"1075 (BC_2, *, internal, X),\" &\n\t\"1076 (BC_2, *, internal, X)\";\n\n\n-- Advanced I/O Description\n\nattribute AIO_COMPONENT_CONFORMANCE of XC7Z020_CLG484 : entity is\n\t\"STD_1149_6_2003\";\n\nattribute AIO_EXTEST_Pulse_Execution of XC7Z020_CLG484 : entity is\n\t\"Wait_Duration TCK 15\";\n\nattribute AIO_EXTEST_Train_Execution of XC7Z020_CLG484 : entity is\n\t\"train 30, maximum_time 120.0e-6\";\n\n\n\n-- Design Warning Section\n\nattribute DESIGN_WARNING of XC7Z020_CLG484 : entity is\n        \"This is a preliminary BSDL file which has not been verified.\" &\n\t\"When no bitstream is loaded and GTPs are not instantiated,\" &\n\t\t\"the boundary-scan cells associated with GTPs will not\" &\n\t\t\"capture correct state information.  To model the boundary-\" &\n\t\t\"scan cell behavior correctly post-configuration, use\" &\n\t\t\"BSDLanno to modify the BSDL file.\" &\n        \"This BSDL file must be modified by the FPGA designer in order to\" &\n                \"reflect post-configuration behavior (if any).\" &\n        \"To avoid losing the current configuration, the boundary scan\" &\n                \"test vectors should keep the PROGRAM_B pin\" &\n                \"high.  If the PROGRAM_B pin goes low by any means,\" &\n                \"the configuration will be cleared.\" &\n        \"PROGRAM_B can only be captured, not updated.\" &\n                \"The value at the pin is always used by the device.\" &\n        \"In EXTEST, output and tristate values are not captured in the\" &\n                \"Capture-DR state - those register cells are unchanged.\" &\n\t\"Differential Serial IO pins do not support INTEST.\" &\n        \"In INTEST, the pin input values are not captured in the\" &\n                \"Capture-DR state - those register cells are unchanged.\" &\n        \"The output and tristate capture values are not valid until after\" &\n                \"the device is configured.\" &\n        \"The tristate control value is not captured properly when\" &\n                \"GTS is activated.\" &\n\t\"The IEEE Std 1149.6 EXTEST_PULSE and EXTEST_TRAIN instructions\" &\n\t\t\"require a minimum TCK freq of 15 MHz and min temp of 0C.\" &\n\t\"NOCONNECT pins should not be connected to any supply\" &\n\t\t\"or GND.  They should be left floating.\" &\n\t\"PSS IOs do not support INTEST\" &\n\t\"PSS IOs do not support cfg_ts which is asserted for TSC instructions\" &\n\t\"BSCAN is not available if the PSS power supplies are not applied\" &\n\t\"PS_POR_B can only be captured, not updated.\" &\n\t\t\"The value at the pin is always used by the device.\";\n\nend XC7Z020_CLG484;\n\n"
  },
  {
    "path": "jtag/digilent-hs1.cfg",
    "content": "#\n# Digilent HS1\n#\n# The Digilent HS1 is a high-speed FT2232H-based adapter, compliant with the\n# Xilinx JTAG 14-pin pinout.\n# It does not support ARM reset signals (SRST and TRST) but can still be used for\n# hardware debugging, with some limitations.\n#\n# http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,395,922&Prod=JTAG-HS1\n#\n\ninterface ft2232\nft2232_device_desc \"Digilent Adept USB Device\"\nft2232_layout digilent-hs1\nft2232_vid_pid 0x0403 0x6010\nadapter_khz 100\n"
  },
  {
    "path": "jtag/digilent-hs2.cfg",
    "content": "#\n# high-speed FT232H-based adapter, compliant with the\n# Xilinx JTAG 14-pin pinout.\n#\n\ninterface ft2232\nft2232_layout digilent-hs1\nft2232_vid_pid 0x0403 0x6014\nadapter_khz 100\n"
  },
  {
    "path": "jtag/dumptrace.py",
    "content": "#!/usr/bin/env python3\n# Copyright (c) 2013 Quanta Research Cambridge, Inc.\n#\n# Permission is hereby granted, free of charge, to any person\n# obtaining a copy of this software and associated documentation\n# files (the \"Software\"), to deal in the Software without\n# restriction, including without limitation the rights to use, copy,\n# modify, merge, publish, distribute, sublicense, and/or sell copies\n# of the Software, and to permit persons to whom the Software is\n# furnished to do so, subject to the following conditions:\n#\n# The above copyright notice and this permission notice shall be\n# included in all copies or substantial portions of the Software.\n#\n# THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n# EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n# MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n# BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n# ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n# CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n# SOFTWARE.\n\nfrom __future__ import print_function\nimport sys\n\nprint('dumptrace: opening', sys.argv[1])\nlines =  open(sys.argv[1]).readlines()\nprint('len', len(lines))\naddressarr = []\nfor thisline in lines:\n    thisline = thisline.strip()\n    if thisline.find(' ') >= 0 or thisline.startswith('http:'):\n        continue\n    #print('LL', thisline)\n    addressarr.append(int(thisline, 16))\nif addressarr.pop() != 0xaaaabbbb or addressarr.pop() != 0xdeadbeef:\n    printf('dumptrace: incomplete read of trace data')\n    sys.exit(1)\nwhile len(addressarr) > 0 and addressarr[0] == 0xdeadbeef:\n    #remove leading entries in case the trace buffer was never really full\n    addressarr.pop(0)\nfor item in addressarr:\n    transname = ['REQ ', 'REQR', '                   IND ', '                   INDR'];\n    topbits = item >> 18\n    fpganumber = (item >> 16) & 0x7\n    transtype = (item >> 14) & 0x3\n    channel = (item >> 8) & 0x3f\n    bottombits = item & 0xff\n    if topbits != 0x1b90:\n        print('dumptrace: address is not in m_axi_gp[0] range', format(topbits, '05x'))\n    fpganame = 'Dir  '\n    channelname = '         '\n    if fpganumber != 0:\n        fpganame = 'fpga'+format(fpganumber, 'x')\n        channelname = 'channel ' + format(channel, 'x')\n    elif channel != 2:\n        channelname = 'channel ' + format(channel, 'x')\n    if bottombits & 0x3 != 0:\n        print('dumptrace: LSB are not 32 word aligned')\n    print(fpganame, transname[transtype], channelname, format(bottombits >> 2, '2x'))\n"
  },
  {
    "path": "jtag/kc705.cfg",
    "content": "source digilent-hs1.cfg\n\njtag newtap kc705 tap -irlen 6 -ircapture 0x01 -expected-id  0x43651093\n\nverify_jtag\n\ninit\nscan_chain\n#drscan kc705\nirscan kc705.tap 9\nset idreg [drscan kc705.tap 64 0]\n#runtest 10\nirscan kc705.tap 1\nset usrreg [drscan kc705.tap 64 0]\necho \"idreg \"$idreg\necho \"usrreg \"$usrreg\nirscan kc705.tap 2\necho \"USER1 \"[drscan kc705.tap 64 00]\necho \"USER1 \"[drscan kc705.tap 64 00]\necho \"USER1 \"[drscan kc705.tap 64 00]\necho \"USER1 \"[drscan kc705.tap 64 00]\necho \"USER1 \"[drscan kc705.tap 64 00]\necho \"USER1 \"[drscan kc705.tap 64 00]\necho \"USER1 \"[drscan kc705.tap 64 00]\necho \"USER1 \"[drscan kc705.tap 64 00]\necho \"USER1 \"[drscan kc705.tap 64 00]\necho \"USER1 \"[drscan kc705.tap 64 00]\necho \"USER1 \"[drscan kc705.tap 64 00]\necho \"USER1 \"[drscan kc705.tap 64 00]\necho \"USER1 \"[drscan kc705.tap 64 00]\necho \"USER1 \"[drscan kc705.tap 64 00]\necho \"USER1 \"[drscan kc705.tap 64 00]\necho \"USER1 \"[drscan kc705.tap 64 00]\nirscan kc705.tap 3\necho \"USER2 \"[drscan kc705.tap 64 0]\n#svf -tap kc705.tap foo.test\nshutdown\n"
  },
  {
    "path": "jtag/kc705program.cfg",
    "content": "\nsource digilent-hs1.cfg\n\njtag newtap kc705 tap -irlen 6 -ircapture 0x01 -expected-id  0x43651093\n\n# configuration sequence from ug470_7Series_Config.pdf,\n# Chapter5: Configuration Details; Section: Configuration Sequence\n# pp 74-81\n#\n\ninit\nscan_chain\n# Clear Configuration Memory (Step 2, Initialization)\n# JPROGRAM\nirscan kc705.tap 0xb\necho \"JPROGRAM \"[drscan kc705.tap 64 0]\n# Check Device ID (Step 5)\nirscan kc705.tap 9\necho \"IDCODE \"[drscan kc705.tap 32 0]\nverify_jtag disable\n# Load Configuration Data Frames (Step 6)\nirscan kc705.tap 5\ndrscan kc705.tap -infile mkPcieTop.bin\nverify_jtag enable\n#check IDCODE again....\nirscan kc705.tap 9\necho \"IDCODE \"[drscan kc705.tap 32 0]\n# Cyclic Redundancy Check (Step 7)\n# Startup (Step 8)\nirscan kc705.tap 0xc\necho \"STARTUP \"[drscan kc705.tap 32 0]\n#check IDCODE again....\nirscan kc705.tap 9\necho \"IDCODE \"[drscan kc705.tap 32 0]\nshutdown\n#        \"BYPASS         (111111),\" & -- BYPASS\n#        \"EXTEST         (100110),\" & -- BOUNDARY\n#        \"SAMPLE         (000001),\" & -- BOUNDARY\n#        \"PRELOAD        (000001),\" & -- Same as SAMPLE\n#        \"USERCODE       (001000),\" & -- DEVICE_ID\n#        \"HIGHZ          (001010),\" & -- BYPASS\n#        \"EXTEST_PULSE   (111100),\" & -- BOUNDARY\n#        \"EXTEST_TRAIN   (111101),\" & -- BOUNDARY\n#        \"ISC_ENABLE     (010000),\" & -- ISC_CONFIG\n#        \"ISC_PROGRAM    (010001),\" & -- ISC_PDATA\n#        \"ISC_NOOP       (010100),\" & -- ISC_DEFAULT\n#        \"XSC_READ_RSVD  (010101),\" & -- PRIVATE\n#        \"ISC_DISABLE    (010110),\" & -- ISC_CONFIG\n#        \"XSC_PROGRAM_KEY        (010010),\" & -- XSC_KEY_DATA\n#        \"XSC_DNA        (010111),\" & -- DNA\n#        \"CFG_OUT        (000100),\" & -- Not available during configuration with another mode.\n#        \"CFG_IN         (000101),\" & -- Not available during configuration with another mode.\n#        \"JSTART         (001100),\" & -- Not available during configuration with another mode.\n#        \"JSHUTDOWN      (001101),\" & -- Not available during configuration with another mode.\n#        \"XADC_DRP       (110111),\" & -- PRIVATE\n#        \"INTEST_RSVD    (000111)\"; -- PRIVATE\n"
  },
  {
    "path": "jtag/pcietrace.cfg",
    "content": "#\n# Digilent HS1\n#\n# The Digilent HS1 is a high-speed FT2232H-based adapter, compliant with the\n# Xilinx JTAG 14-pin pinout.\n# It does not support ARM reset signals (SRST and TRST) but can still be used for\n# hardware debugging, with some limitations.\n#\n# http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,395,922&Prod=JTAG-HS1\n#\n\ninterface ft2232\nft2232_device_desc \"Digilent Adept USB Device\"\nft2232_layout digilent-hs1\nft2232_vid_pid 0x0403 0x6010\nadapter_khz 100\nsource digilent-hs1.cfg\n\njtag newtap kc705 tap -irlen 6 -ircapture 0x01 -expected-id  0x43651093\n\nverify_jtag\n\ninit\nscan_chain\n#drscan kc705\nirscan kc705.tap 9\nset idreg [drscan kc705.tap 64 0]\n#runtest 10\nirscan kc705.tap 1\nset usrreg [drscan kc705.tap 64 0]\necho \"idreg \"$idreg\necho \"usrreg \"$usrreg\nirscan kc705.tap 2\nfor {set i 0} {$i < 2048} {incr i} {\n    echo \"USER1 \"[drscan kc705.tap 192 00]\n}\nirscan kc705.tap 3\necho \"USER2 \"[drscan kc705.tap 192 0]\n#svf -tap kc705.tap foo.test\nshutdown\n"
  },
  {
    "path": "jtag/readll.py",
    "content": "#!/usr/bin/env python3\n# Copyright (c) 2013 Quanta Research Cambridge, Inc.\n#\n# Permission is hereby granted, free of charge, to any person\n# obtaining a copy of this software and associated documentation\n# files (the \"Software\"), to deal in the Software without\n# restriction, including without limitation the rights to use, copy,\n# modify, merge, publish, distribute, sublicense, and/or sell copies\n# of the Software, and to permit persons to whom the Software is\n# furnished to do so, subject to the following conditions:\n#\n# The above copyright notice and this permission notice shall be\n# included in all copies or substantial portions of the Software.\n#\n# THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n# EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n# MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n# BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n# ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n# CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n# SOFTWARE.\n\nfrom __future__ import print_function\nimport sys\n\ndef getbit(lastx, lasty):\n    toff = 36 * int((lastx - 14)/2)\n    if lastx >= 54:\n        toff = toff + 2 + 4 * 28\n    elif lastx >= 50: # column X1\n        toff = toff + 2 + 3 * 28\n    elif lastx >= 36:\n        toff = toff + 2 * 28\n    elif lastx >= 32:\n        toff = toff + 28\n    if lasty <= 49:   # row Y0\n        toff = toff + 2 * 2 * 1283\n    elif lasty <= 99: # row Y1\n        toff = toff + 2 * 1283\n    return toff\n\ndef printval(starty, lastx, lasty, lastval):\n    if starty == -1:\n        return ''\n    return ' %3d-%3d/%d' % (starty, lasty, lastval - getbit(lastx, lasty))\n\nprint('readll: opening', sys.argv[1])\nlines =  open(sys.argv[1]).readlines()\nprint('len', len(lines))\ni = 0\ntoplist = {}\ntopoffset = {}\ntopref = {}\nfor thisline in lines:\n    if thisline[0] == ';':\n        continue\n    iteml = thisline.split()\n    if iteml[0] != 'Bit' or not iteml[4].startswith('Block=SLICE_X'):\n        print('Non-Bit line', thisline.strip())\n        continue\n    for i in range(3):\n        iteml[i+1] = int(iteml[i+1], 0)\n    bitoff = iteml[1]\n    frameoffset = iteml[3]\n    temp = iteml[4][13:]\n    ind = temp.find('Y')\n    coordx = int(temp[:ind])\n    coordy = int(temp[ind+1:])\n    itemtype = iteml[5]\n    if itemtype.startswith('Ram='):\n        continue\n    if not itemtype.endswith('MUX'):\n        itemtype = itemtype[:6] + '   ' + itemtype[6:]\n    if not topoffset.get(itemtype):\n        topoffset[itemtype] = {}\n    if not topoffset[itemtype].get(frameoffset):\n        topoffset[itemtype][frameoffset] = 0\n    topoffset[itemtype][frameoffset] = topoffset[itemtype][frameoffset] + 1\n    ftemp = frameoffset % 32\n    fmult = int(frameoffset/32)\n    if not topref.get(ftemp):\n        topref[ftemp] = {}\n    if not topref[ftemp].get(itemtype):\n        topref[ftemp][itemtype] = {}\n    if not topref[ftemp][itemtype].get(fmult):\n        topref[ftemp][itemtype][fmult] = 0\n    topref[ftemp][itemtype][fmult] = topref[ftemp][itemtype][fmult] + 1\n    toplist['%4d_%4d_%5d' % (coordx, coordy, frameoffset)] = [ coordx, coordy, (bitoff - frameoffset)/ 3232.0 - 467]\nlastx = 0\noutstring = ''\nstarty = -1\nlasty = -1\nlastval = -1\nfor key, value in sorted(toplist.items()):\n    if value[0] != lastx:\n        outstring = outstring + printval(starty, lastx, lasty, lastval)\n        lastx = value[0]\n        print(outstring)\n        outstring = '%3d:' % value[0]\n        starty = -1\n    if lastval != value[2]:\n        outstring = outstring + printval(starty, lastx, lasty, lastval)\n        starty = value[1]\n    lasty = value[1]\n    lastval = value[2]\noutstring = outstring + printval(starty, lastx, lasty, lastval)\nprint(outstring)\n#for key, value in sorted(topoffset.items()):\n#    outstring = key + ': '\n#    for vkey, vvalue in sorted(value.items()):\n#        if vvalue != 1:\n#            outstring = outstring + ' ' + str(vkey) + '/' + str(vvalue)\n#    print(outstring)\nprint('ref')\nfor key, value in sorted(topref.items()):\n    #print(key, value)\n    for vkey, vvalue in sorted(value.items()):\n        outstringhead = str(key) + '=' + vkey[6:].strip() + ':'\n        outstring = outstringhead\n        prevrkey = -1\n        for rkey, rvalue in sorted(vvalue.items()):\n            if prevrkey != -1 and rkey != prevrkey + 2:\n                print(outstring)\n                outstring = '    ' + outstringhead\n                prevrkey = -1\n            outstring = outstring + ' ' + str(rkey)\n            if rvalue != 1:\n                outstring = outstring + '/' + str(rvalue)\n            prevrkey = rkey\n    print(outstring)\n"
  },
  {
    "path": "jtag/run_jtag.sh",
    "content": "#\nset -e\nset -x\n#openocd  -f kc705.cfg \nopenocd  -f zedboard.cfg \n"
  },
  {
    "path": "jtag/run_trace.sh",
    "content": "#/bin/bash\nset -x\nset -e\nopenocd -f zedtrace.cfg 2>trace.xx.tempfile\nsed -e\"s/\\(.\\)\\(...\\)\\(....\\)/\\1 \\2 \\3 /\" <trace.xx.tempfile  \\\n| sed -e\"s/^0/0 0/\" -e\"s/^1/0 1/\" -e\"s/^2/1 0/\" -e\"s/^3/1 1/\" \\\n      -e\"s/^4/2 0/\" -e\"s/^5/2 1/\" -e\"s/^6/3 0/\" -e\"s/^7/3 1/\" \\\n      -e\"s/^8/4 0/\" -e\"s/^9/4 1/\" -e\"s/^A/5 0/\" -e\"s/^B/5 1/\" >trace.log\n#rm -f trace.xx.tempfile\n"
  },
  {
    "path": "jtag/zedboard.cfg",
    "content": "source digilent-hs2.cfg\n\njtag newtap zed tap -irlen 6 -ircapture 0x01 -expected-id  0x03727093\njtag newtap cortex tap -irlen 4 -ircapture 0x01 -expected-id  0x4ba00477\n\n# targets cortex_a\n\nverify_jtag\n\ninit\nscan_chain\n\n# clear bscan.sel() by setting IR to a different register\nirscan zed.tap 9\n\n# try reading out USER1 register 000010\nirscan zed.tap 2\necho \"USER1=\"[drscan zed.tap 32 0xdeadbeef]\nirscan zed.tap 2\necho \"USER1=\"[drscan zed.tap 32 0x12345678]\nirscan zed.tap 2\necho \"USER1=\"[drscan zed.tap 32 0xabcdef01]\n\n# clear bscan.sel() by setting IR to a different register\nirscan zed.tap 9\n\n# try reading out USER1 register 000010\nirscan zed.tap 2\necho \"USER1=\"[drscan zed.tap 32 0xaaaabbbb]\nirscan zed.tap 2\necho \"USER1=\"[drscan zed.tap 32 0xccccdddd]\nirscan zed.tap 2\necho \"USER1=\"[drscan zed.tap 32 0xeeeeffff]\n\n# clear bscan.sel() by setting IR to a different register\nirscan zed.tap 9\n\n#svf -tap zed.tap foo.test\n#runtest 10\nshutdown\n"
  },
  {
    "path": "jtag/zedtrace.cfg",
    "content": "source digilent-hs2.cfg\n\njtag newtap zed tap -irlen 6 -ircapture 0x01 -expected-id  0x03727093\njtag newtap cortex tap -irlen 4 -ircapture 0x01 -expected-id  0x4ba00477\n\n# targets cortex_a\n\nverify_jtag\n\ninit\nscan_chain\n\n# clear bscan.sel() by setting IR to a different register\nirscan zed.tap 9\n\n#echo [drscan zed.tap 64 0xffffffffffffffff]\n#echo [drscan zed.tap 64 0xffffffffffffffff]\n#echo [drscan zed.tap 64 0x0000000000000000]\n#echo [drscan zed.tap 64 0x0000000000000000]\n#echo [drscan zed.tap 64 0x00000000000000f0]\nfor {set j 0} {$j < 4} {incr j} {\n# try reading out USER2 register 000011\nirscan zed.tap 3\nfor {set i 0} {$i < 256 + 2} {incr i} {\n    echo [drscan zed.tap 64 0xdeadbeefbeefdead]\n}\nsleep 1000\n}\n\n# clear bscan.sel() by setting IR to a different register\nirscan zed.tap 9\n\nshutdown\n\n"
  },
  {
    "path": "lib/bsv/Arith.bsv",
    "content": "\n// Copyright (c) 2014 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\nimport Vector::*;\n\nfunction Bool booland(Bool x1, Bool x2); return x1 && x2; endfunction\nfunction Bool boolor(Bool x1, Bool x2); return x1 || x2; endfunction\n\nfunction Bool eq(a x1, a x2) provisos (Eq#(a)); return x1 == x2; endfunction\n\nfunction a add(a x1, a x2) provisos (Arith#(a)); return x1 + x2; endfunction\nfunction a mul(a x1, a x2) provisos (Arith#(a)); return x1 * x2; endfunction\nfunction Bit#(b) rshift(Bit#(b) x1, Integer i); return x1 >> i; endfunction\nfunction Vector#(n, a) vadd(Vector#(n, a) x1, Vector#(n, a) x2) provisos (Arith#(a));\n   return map(uncurry(add), zip(x1, x2));\nendfunction\nfunction Vector#(n, a) vmul(Vector#(n, a) x1, Vector#(n, a) x2) provisos (Arith#(a));\n   return map(uncurry(mul), zip(x1, x2));\nendfunction\nfunction Vector#(n, Bit#(b)) vrshift(Vector#(n, Bit#(b)) x1, Integer i);\n   return map(flip(rshift)(i), x1);\nendfunction\n\nfunction a bitwiseor(a x1, a x2) provisos (Bitwise#(a)); return x1 | x2; endfunction\nfunction a bitwiseand(a x1, a x2) provisos (Bitwise#(a)); return x1 & x2; endfunction\n"
  },
  {
    "path": "lib/bsv/BRAMFIFOFLevel.bsv",
    "content": "// Copyright (c) 2013 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\n\nimport GetPut::*;\nimport BRAMFIFO::*;\nimport FIFOF::*;\n\ninterface Counter#(numeric type count_sz);\n   method Action reset();\n   method Action increment();\n   method Action decrement();\n   method Bit#(count_sz) read();\nendinterface\n\nmodule mkCounter#(Bit#(count_sz) init_val)(Counter#(count_sz));\n   PulseWire inc_wire <- mkPulseWire;\n   PulseWire dec_wire <- mkPulseWire;\n   PulseWire rst_wire <- mkPulseWire;\n   Reg#(Bit#(count_sz)) cnt <- mkReg(init_val);\n   (* fire_when_enabled *)\n   rule react;\n      if (rst_wire)\n\t cnt <= 0;\n      else if (inc_wire && dec_wire)\n\t noAction;\n      else if (inc_wire)\n\t cnt <= cnt+1;\n      else if (dec_wire)\n\t cnt <= cnt-1;\n      else\n\t noAction;\n   endrule\n   method Action increment = inc_wire.send;\n   method Action decrement = dec_wire.send;\n   method Action reset = rst_wire.send;\n   method Bit#(count_sz) read = cnt._read;\nendmodule\n\ninterface FIFOFLevel#(type element_type, numeric type fifo_depth);\n   interface FIFOF#(element_type) fifo;\n   method Bool highWater(Bit#(TAdd#(1,TLog#(fifo_depth))) mark);\n   method Bool lowWater(Bit#(TAdd#(1,TLog#(fifo_depth))) mark);\nendinterface\n\ninstance ToGet#(FIFOFLevel#(a,b), a);\n   function Get#(a) toGet(FIFOFLevel#(a,b) f) = toGet(f.fifo);\nendinstance\n\ninstance ToPut#(FIFOFLevel#(a,b), a);\n   function Put#(a) toPut(FIFOFLevel#(a,b) f) = toPut(f.fifo);\nendinstance\n\nmodule mkBRAMFIFOFLevel(FIFOFLevel#(element_type, fifo_depth))\n   provisos(Log#(fifo_depth, log_fifo_depth),\n\t    Add#(log_fifo_depth,1,mark_width),\n\t    Bits#(element_type, __a),\n\t    Add#(1, a__, __a));\n\n   Counter#(mark_width) cnt <- mkCounter(0);\n   FIFOF#(element_type) fif <- mkSizedBRAMFIFOF(valueOf(fifo_depth));\n   \n   method Bool highWater(Bit#(mark_width) mark);\n      return (cnt.read >= mark);\n   endmethod\n   \n   method Bool lowWater(Bit#(mark_width) mark);\n      return (fromInteger(valueOf(fifo_depth))-cnt.read >= mark);\n   endmethod\n  \n   interface FIFOF fifo;\n      method Action enq (element_type x);\n\t cnt.increment;\n\t fif.enq(x);\n      endmethod\n      method Action deq;\n\t cnt.decrement;\n\t fif.deq;\n      endmethod\n      method Action clear;\n\t cnt.reset;\n\t fif.clear;\n      endmethod\n      method element_type first = fif.first;\n      method Bool notFull = fif.notFull;\n      method Bool notEmpty = fif.notEmpty;\n   endinterface\n   \nendmodule\n\nmodule mkFIFOFLevel(FIFOFLevel#(element_type, fifo_depth))\n   provisos(Log#(fifo_depth, log_fifo_depth),\n\t    Add#(log_fifo_depth,1,mark_width),\n\t    Bits#(element_type, __a),\n\t    Add#(1, a__, __a));\n\n   Counter#(mark_width) cnt <- mkCounter(0);\n   FIFOF#(element_type) fif <- mkSizedFIFOF(valueOf(fifo_depth));\n\n   method Bool highWater(Bit#(mark_width) mark);\n      return (cnt.read >= mark);\n   endmethod\n\n   method Bool lowWater(Bit#(mark_width) mark);\n      return (fromInteger(valueOf(fifo_depth))-cnt.read >= mark);\n   endmethod\n\n   interface FIFOF fifo;\n      method Action enq (element_type x);\n\t cnt.increment;\n\t fif.enq(x);\n      endmethod\n      method Action deq;\n\t cnt.decrement;\n\t fif.deq;\n      endmethod\n      method Action clear;\n\t cnt.reset;\n\t fif.clear;\n      endmethod\n      method element_type first = fif.first;\n      method Bool notFull = fif.notFull;\n      method Bool notEmpty = fif.notEmpty;\n   endinterface\n\nendmodule\n"
  },
  {
    "path": "lib/bsv/BlueScope.bsv",
    "content": "\n// Copyright (c) 2013 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\nimport Clocks::*;\nimport FIFO::*;\nimport FIFOF::*;\nimport BRAMFIFO::*;\nimport GetPut::*;\nimport Connectable::*;\n\nimport ConnectalMemTypes::*;\nimport MemWriteEngine::*;\nimport ClientServer::*;\n\ninterface BlueScopeIndication;\n   method Action triggerFired();\n   method Action done();\nendinterface\n\ninterface BlueScopeRequest;\n   method Action start(Bit#(32) pointer, Bit#(32) len);\n   method Action reset();\n   method Action setTriggerMask(Bit#(64) mask);\n   method Action setTriggerValue(Bit#(64) value);\nendinterface\n\ninterface BlueScope#(numeric type dataWidth);\n   method Action dataIn(Bit#(dataWidth) d, Bit#(dataWidth) t);\n   interface BlueScopeRequest requestIfc;\n   interface MemWriteClient#(dataWidth) writeClient;\nendinterface\n\ntypedef enum { Idle, Enabled, Triggered } State deriving (Bits,Eq);\n\nmodule mkBlueScope#(Integer samples, BlueScopeIndication indication)(BlueScope#(dataWidth))\n   provisos(Add#(a__,dataWidth,64),\n\t    Mul#(TDiv#(dataWidth, 8), 8, dataWidth),\n\t    Add#(1,b__,dataWidth));\n   \n   let clk <- exposeCurrentClock;\n   let rst <- exposeCurrentReset;\n   let rv  <- mkSyncBlueScope(samples, indication, clk, rst, clk,rst);\n   return rv;\nendmodule\n\nmodule mkSyncBlueScope#(Integer samples, BlueScopeIndication indication, Clock sClk, Reset sRst, Clock dClk, Reset dRst)(BlueScope#(dataWidth))\n   provisos(Add#(a__,dataWidth,64),\n\t    Add#(1,b__,dataWidth),\n\t    Mul#(dataBytes, 8, dataWidth),\n\t    Div#(dataWidth,8,dataBytes));\n\n   SyncFIFOIfc#(Bit#(dataWidth)) dfifo <- mkSyncBRAMFIFO(samples, sClk, sRst, dClk, dRst);\n   Reg#(Bit#(dataWidth))       maskReg <- mkSyncReg(0, dClk, dRst, sClk);\n   Reg#(Bit#(dataWidth))      valueReg <- mkSyncReg(0, dClk, dRst, sClk);\n   Reg#(Bit#(1))          triggeredReg <- mkReg(0,    clocked_by sClk, reset_by sRst);   \n   Reg#(State)                stateReg <- mkReg(Idle, clocked_by sClk, reset_by sRst);\n   Reg#(Bit#(32))             countReg <- mkReg(0,    clocked_by sClk, reset_by sRst);\n   Reg#(Bit#(MemOffsetSize)) writeOffsetReg <- mkReg(0,    clocked_by dClk, reset_by dRst);\n   \n   SyncPulseIfc             startPulse <- mkSyncPulse(dClk, dRst, sClk);\n   SyncPulseIfc             resetPulse <- mkSyncPulse(dClk, dRst, sClk);\n   SyncPulseIfc         triggeredPulse <- mkSyncPulse(sClk, sRst, dClk);\n   SyncPulseIfc              donePulse <- mkSyncPulse(sClk, sRst, dClk);\n   \n   MemWriteEngine#(dataWidth,dataWidth,2,1) mwriter <- mkMemWriteEngine;\n   \n   (* descending_urgency = \"resetState, startState\" *)\n   rule resetState if (resetPulse.pulse);\n      stateReg <= Idle;\n      countReg <= 0;\n   endrule\n\n   rule startState if (startPulse.pulse && !resetPulse.pulse);\n      stateReg <= Enabled;\n   endrule\n\n   mkConnection(toGet(dfifo), toPut(mwriter.writeServers[0].data));\n\n   rule writeDone;\n      let tag <- mwriter.writeServers[0].done.get();\n   endrule\n   \n   rule triggerRule if (triggeredPulse.pulse);\n      indication.triggerFired;\n   endrule\n   rule doneRule if (donePulse.pulse);\n      indication.done;\n   endrule\n   \n   method Action dataIn(Bit#(dataWidth) data, Bit#(dataWidth) trigger);// if (stateReg != Idle);\n      let e = False;\n      let s = stateReg;\n      let c = countReg;\n      let t = False;\n      let d = False;\n \n      // if 'Enabled', we can transition to 'Triggered'\n      if (s == Enabled && ((trigger & maskReg) == (valueReg & maskReg) && dfifo.notFull()))\n      \t begin\n      \t    s = Triggered;\n\t    e = True;\n\t    c = c + 1;\n      \t    t = True;\n         end\n      // if 'Triggered', we can transition to 'Enabled'\n      else if (s == Triggered && c == fromInteger(samples))\n      \t begin\n\t    s = Idle;\n      \t    e = False;\n\t    c = 0;\n      \t    t = False;\n\t    d = True;\n      \t end\n      // if 'Triggered', we can remain in 'Triggered'\n      else if (s == Triggered && c < fromInteger(samples))\n      \t begin\n      \t    s = Triggered;\n      \t    e = True;\n\t    c = c + 1;\n      \t    t = False;\n      \t end\n      // else we must be enabled waiting for a Trigger\n      else \n      \t begin\n      \t    s = s;\n      \t    e = e;\n\t    c = c;\n      \t    t = t;\n      \t end\n   \n      if (e) begin\n\t if (dfifo.notFull())\n\t    dfifo.enq(data);\n\t else\n\t    $display(\"bluescope.stall c=%d\", c);\n      end\n      if(t)\n      \t triggeredPulse.send();\n      if(d)\n      \t donePulse.send();\n      countReg <= c;\n      stateReg <= s;\n   endmethod\n   \n   interface BlueScopeRequest requestIfc;\n      method Action start(Bit#(32) pointer, Bit#(32) len);\n\t mwriter.writeServers[0].request.put(MemengineCmd {sglId: pointer, base: 0, burstLen: 8*fromInteger(valueOf(TDiv#(dataWidth,8))), len: len, tag: 0});\n\t startPulse.send();\n      endmethod\n\n      method Action reset();\n          resetPulse.send();\n      endmethod\n\n      method Action setTriggerMask(Bit#(64) mask);\n\t maskReg <= truncate(mask);\n      endmethod\n\n      method Action setTriggerValue(Bit#(64) value);\n\t valueReg <= truncate(value);\n      endmethod\n   endinterface\n   interface writeClient = mwriter.dmaClient;\nendmodule\n"
  },
  {
    "path": "lib/bsv/BlueScopeEvent.bsv",
    "content": "// Copyright (c) 2013 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\n// Idea:\n// BlueScopeEvent allows one to record values only when they change,\n// along with timestamps of the time of change.\n// The input is some collection of bits, in some clock domain\n// A trigger signal is generated when the input, anded with a trigger\n// mask, changes from clock to clock\n// Whenever the trigger happens, the new value and a timestamp are saved\n// into a SyncBRAMFiFo.  The output of the FiFo is in the system clock\n// domain, as is a counter value that says how many events have happened.\n// One can request a DMA write from the FiFo to system memory, at a given\n// address, for a given count.\n// One can reset the fifo and counter.\nimport Clocks::*;\nimport FIFO::*;\nimport FIFOF::*;\nimport BRAMFIFO::*;\nimport GetPut::*;\nimport Connectable::*;\nimport ConnectalMemTypes::*;\nimport MemWriteEngine::*;\nimport ClientServer::*;\n\n// This version records timestamped events\ninterface BlueScopeEventRequest;\n   // emtpy fifo and reset event counter\n   method Action doReset();\n   // changes in bits selected by the mask will trigger events\n   method Action setTriggerMask(Bit#(32) mask);\n   // generate a report pointer indication\n   method Action getCounterValue();\n   // copy from fifo to memory\n   method Action startDma(Bit#(32) pointer, Bit#(32) len);\nendinterface\n\ninterface BlueScopeEventIndication;\n   // report number of events since last reset,\n   method Action counterValue(Bit#(32) v);\n   // dma operation complete\n   method Action dmaDone();\nendinterface\n\ninterface BlueScopeEvent#(numeric type dataWidth);\n   method Action dataIn(Bit#(dataWidth) d);\nendinterface\n   \ninterface BlueScopeEventControl#(numeric type dataWidth);\n   interface BlueScopeEvent#(dataWidth) bse;\n   interface BlueScopeEventRequest requestIfc;\n   interface MemWriteClient#(64) writeClient;\nendinterface\n\nmodule mkBlueScopeEvent#(Integer samples, BlueScopeEventIndication indication)(BlueScopeEventControl#(dataWidth))\n   provisos(Add#(0,dataWidth,32));\n   \n   let clk <- exposeCurrentClock;\n   let rst <- exposeCurrentReset;\n   let rv  <- mkSyncBlueScopeEvent(samples, indication, clk, rst, clk,rst);\n   return rv;\nendmodule\n\n// sClk is the source? sample? side, input samples come here\n// dClk is the destination? dma? side, this will generally be the system clock\n\nmodule mkSyncBlueScopeEvent#(Integer samples, BlueScopeEventIndication indication, Clock sClk, Reset sRst, Clock dClk, Reset dRst)(BlueScopeEventControl#(dataWidth))\n   provisos(Add#(0, dataWidth, 32));\n\n   // the idea here is that we let events pour into the Bram continually,\n   // then reset them before starting an acquisition interval\n   // we reset both halves of the fifo, not clear that is needed\n   MakeResetIfc sFifoReset <- mkReset(2, True, sClk);\n   MakeResetIfc dFifoReset <- mkReset(2, True, dClk);\n   SyncFIFOIfc#(Bit#(64)) dfifo <- mkSyncBRAMFIFO(samples, sClk, sFifoReset.new_rst, dClk, dFifoReset.new_rst);\n   // mask reg is set from a request in the dClk domain but used in the\n   // sClk domain to determine triggering\n   Reg#(Bit#(dataWidth))       maskReg <- mkSyncReg(0, dClk, dRst, sClk);\n   // freeClockReg counts cycles to timestamp events\n   Reg#(Bit#(32)) freeClockReg <- mkReg(0, clocked_by sClk, reset_by sRst);\n   // countReg counts accumulated samples\n   Reg#(Bit#(32)) countReg <- mkReg(0, clocked_by sClk, reset_by sRst);\n   // countSyncReg repeats that value into the dClk domain\n   Reg#(Bit#(32)) countSyncReg <- mkSyncReg(0, sClk, sFifoReset.new_rst, dClk);\n   // oldData is used in the sample domain, to save the previous value\n   Reg#(Bit#(dataWidth)) olddata <- mkReg(0, clocked_by sClk, reset_by sRst);\n\n\n   MemWriteEngine#(64,64,2,1) mwriter <- mkMemWriteEngine;\n   \n//   (* descending_urgency = \"resetState, startState\" *)\n\n   mkConnection(toGet(dfifo), toPut(mwriter.writeServers[0].data));\n\n   rule writeDone;\n      let tag <- mwriter.writeServers[0].done.get();\n      indication.dmaDone;\n   endrule\n\n   rule freeClock;\n      freeClockReg <= freeClockReg + 1;\n   endrule\n   \n   interface BlueScopeEvent bse;\n   \n      method Action dataIn(Bit#(dataWidth) data);// if (stateReg != Idle);\n\t let c = countReg;\n\t if ((maskReg & (data ^ olddata)) != 0)\n            begin\n\t       if (dfifo.notFull())\n\t\t  begin\n\t\t     dfifo.enq({data, freeClockReg});\n\t\t     countReg <= c + 1;\n\t\t     countSyncReg <= c + 1;\n\t\t  end\n\t       else\n\t\t  $display(\"bluescope.stall c=%d\", c);\n\t    end\n\t olddata <= data;\n      endmethod\n\n     endinterface\n      \n   interface BlueScopeEventRequest requestIfc;\n\n      method Action doReset();\n\t sFifoReset.assertReset();\n\t dFifoReset.assertReset();\n      endmethod\n      \n      method Action setTriggerMask(Bit#(32) mask);\n\t maskReg <= truncate(mask);\n      endmethod\n\n      method Action getCounterValue();\n         indication.counterValue(countSyncReg);\n      endmethod\n\n      method Action startDma(Bit#(32) pointer, Bit#(32) len);\n\t mwriter.writeServers[0].request.put(MemengineCmd {sglId: pointer, base: 0, burstLen: 8*fromInteger(valueOf(TDiv#(dataWidth,8))), len: len, tag: ?});\n      endmethod\n\n   endinterface\n   interface writeClient = mwriter.dmaClient;\nendmodule\n\n"
  },
  {
    "path": "lib/bsv/BlueScopeEventPIO.bsv",
    "content": "// Copyright (c) 2014 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\n// Idea:\n// BlueScopeEventPIO allows one to record values only when they change,\n// along with timestamps of the time of change.\n// The input is some collection of bits, in some clock domain\n// A trigger signal is generated when the input, anded with a trigger\n// mask, changes from clock to clock\n// Whenever the trigger happens, the new value and a timestamp are saved\n// into a SyncBRAMFiFo.  The output of the FiFo is in the system clock\n// domain, as is a counter value that says how many events have happened.\n// When enabled, the events in the fifo are reported by indication\n\n// A very similar module is BlueScopeEventPIO.bsv, which reports by DMA.\n// It supports a much higher data rate, but is more trouble to set up and use\n\nimport Clocks::*;\nimport FIFO::*;\nimport FIFOF::*;\nimport BRAMFIFO::*;\n\n// This version records timestamped events\ninterface BlueScopeEventPIORequest;\n   // emtpy fifo and reset event counter\n   method Action doReset();\n   // changes in bits selected by the mask will trigger events\n   method Action setTriggerMask(Bit#(32) mask);\n   // generate a report pointer indication\n   method Action getCounterValue();\n   // copy from fifo to memory\n   method Action enableIndications(Bit#(32) en);\nendinterface\n\ninterface BlueScopeEventPIOIndication;\n   // report number of events since last reset,\n   method Action counterValue(Bit#(32) v);\n   // report an event\n   method Action reportEvent(Bit#(32) value, Bit#(32) timestamp);\nendinterface\n\n// This interface is used by the device under test to report events\n// Reported events are actually recorded only if they meet the trigger\n// conditions\ninterface BlueScopeEventPIO#(numeric type dataWidth);\n   method Action dataIn(Bit#(dataWidth) d);\nendinterface\n   \ninterface BlueScopeEventPIOControl#(numeric type dataWidth);\n   interface BlueScopeEventPIO#(dataWidth) bse;\n   interface BlueScopeEventPIORequest requestIfc;\nendinterface\n\nmodule mkBlueScopeEventPIO#(Integer samples, BlueScopeEventPIOIndication indication)(BlueScopeEventPIOControl#(dataWidth))\n   provisos(Add#(0,dataWidth,32));\n   \n   let clk <- exposeCurrentClock;\n   let rst <- exposeCurrentReset;\n   let rv  <- mkSyncBlueScopeEventPIO(samples, indication, clk, rst, clk,rst);\n   return rv;\nendmodule\n\n// sClk is the source? sample? side, input samples come here\n// dClk is the destination? dma? side, this will generally be the system clock\n\nmodule mkSyncBlueScopeEventPIO#(Integer samples, BlueScopeEventPIOIndication indication, Clock sClk, Reset sRst, Clock dClk, Reset dRst)(BlueScopeEventPIOControl#(dataWidth))\n   provisos(Add#(0, dataWidth, 32));\n\n   // the idea here is that we let events pour into the Bram continually,\n   // then reset them before starting an acquisition interval\n   // we reset both halves of the fifo, not clear that is needed\n   MakeResetIfc sFifoReset <- mkReset(2, True, sClk);\n   MakeResetIfc dFifoReset <- mkReset(2, True, dClk);\n   SyncFIFOIfc#(Bit#(64)) dfifo <- mkSyncBRAMFIFO(samples, sClk, sFifoReset.new_rst, dClk, dFifoReset.new_rst);\n   // mask reg is set from a request in the dClk domain but used in the\n   // sClk domain to determine triggering\n   Reg#(Bit#(dataWidth))       maskReg <- mkSyncReg(0, dClk, dRst, sClk);\n   // freeClockReg counts cycles to timestamp events\n   Reg#(Bit#(32)) freeClockReg <- mkReg(0, clocked_by sClk, reset_by sRst);\n   // countReg counts accumulated samples\n   Reg#(Bit#(32)) countReg <- mkReg(0, clocked_by sClk, reset_by sRst);\n   // countSyncReg repeats that value into the dClk domain\n   Reg#(Bit#(32)) countSyncReg <- mkSyncReg(0, sClk, sFifoReset.new_rst, dClk);\n   // oldData is used in the sample domain, to save the previous value\n   Reg#(Bit#(dataWidth)) olddata <- mkReg(0, clocked_by sClk, reset_by sRst);\n   Reg#(Bit#(1)) enableIndicationReg <- mkReg(0);\n   \n   rule doIndication (enableIndicationReg == 1);\n      let v = dfifo.first();\n      indication.reportEvent(v[63:32], v[31:0]);\n      dfifo.deq();\n   endrule\n  \n   rule freeClock;\n      freeClockReg <= freeClockReg + 1;\n   endrule\n   \n   interface BlueScopeEventPIO bse;\n   \n      method Action dataIn(Bit#(dataWidth) data);// if (stateReg != Idle);\n\t let c = countReg;\n\t if ((maskReg & (data ^ olddata)) != 0)\n            begin\n\t       if (dfifo.notFull())\n\t\t  begin\n\t\t     dfifo.enq({data, freeClockReg});\n\t\t     countReg <= c + 1;\n\t\t     countSyncReg <= c + 1;\n\t\t  end\n\t       else\n\t\t  $display(\"bluescope.stall c=%d\", c);\n\t    end\n\t olddata <= data;\n      endmethod\n\n     endinterface\n      \n   interface BlueScopeEventPIORequest requestIfc;\n\n      method Action doReset();\n\t sFifoReset.assertReset();\n\t dFifoReset.assertReset();\n      endmethod\n      \n      method Action setTriggerMask(Bit#(32) mask);\n\t maskReg <= truncate(mask);\n      endmethod\n\n      method Action getCounterValue();\n         indication.counterValue(countSyncReg);\n      endmethod\n\n      method Action enableIndications(Bit#(32) en);\n\t enableIndicationReg <= en[0];\n      endmethod\n\n   endinterface\nendmodule\n\n"
  },
  {
    "path": "lib/bsv/Bscan.bsv",
    "content": "\n// Copyright (c) 2014 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\n`include \"ConnectalProjectConfig.bsv\"\nimport FIFOF::*;\nimport Clocks::*;\nimport Vector::*;\nimport BRAM::*;\nimport BscanE2::*;\nimport GetPut::*;\nimport XilinxCells::*;\nimport SyncBits::*;\n\n// From: http://siliconexposed.blogspot.com/2013/10/soc-framework-part-5.html\n// Example usage: http://www.pld.ttu.ee/~vadim/tty/IAY0570/video_pipeline/psram_app/program_rom.v\n// Example usage: http://ohm.bu.edu/~dean/G-2TrackerWORKING/uart_test.vhd\n\ninterface BscanTop;\n   interface Reset    rst;\n   interface Clock    tck;\n   method Bit#(1)     reset();\n   method Bit#(1)     capture();\n   method Bit#(1)     shift();\n   method Bit#(1)     tdi();\n   method Action      tdo(Bit#(1) v);\n   method Bit#(1)     update();\n   method Bool        first();\nendinterface\n`ifdef SIMULATION\nmodule mkBscanTop#(Integer bus)(BscanTop);\n   Clock defaultClock <- exposeCurrentClock();\n   Reset defaultReset <- exposeCurrentReset();\n   interface tck = defaultClock;\n   interface rst = defaultReset;\n   method reset();\n       return 0;\n   endmethod\n   method tdi;\n       return 0;\n   endmethod\n   method Action tdo(Bit#(1) v);\n   endmethod\n   method capture;\n       return 0;\n   endmethod\n   method shift;\n       return 0;\n   endmethod\n   method update;\n       return 0;\n   endmethod\n   method first();\n      return False;\n   endmethod\nendmodule\n`else\nmodule mkBscanTop#(Integer bus)(BscanTop);\n   Clock defaultClock <- exposeCurrentClock();\n   Reset defaultReset <- exposeCurrentReset();\n   BscanE2 bscan <- mkBscanE2(bus);\n   Clock mytck <- mkClockBUFG(clocked_by bscan.tck);\n   Reset myrst <- mkAsyncReset(2, defaultReset, mytck);\n   SyncBitIfc#(Bool) selected <- mkSyncBits(False, mytck, myrst, defaultClock, defaultReset);\n   Reg#(Bool) selectdelay <- mkReg(False);\n\n   rule updater;\n       selected.send(bscan.sel() == 1);\n   endrule\n   rule writed;\n       selectdelay <= selected.read();\n   endrule\n\n   interface tck = mytck;\n   interface rst = myrst;\n   method reset = bscan.reset;\n   method tdi = bscan.tdi;\n   method tdo = bscan.tdo;\n   method capture;\n       return bscan.sel & bscan.capture;\n   endmethod\n   method shift;\n       return bscan.sel & bscan.shift;\n   endmethod\n   method update;\n       return bscan.sel & bscan.update;\n   endmethod\n   method first();\n      return selected.read() && !selectdelay;\n   endmethod\nendmodule\n`endif\n\ninterface BscanLocal;\n   interface Vector#(2, BscanTop) loc;\nendinterface\n\nmodule mkBscanLocal#(BscanTop bscan)(BscanLocal);\n   Vector#(2, Wire#(Bit#(1))) tdo_wire <- replicateM(mkDWire(0));\n   //Wire#(Bit#(1)) tdo_wire2 <- mkDWire(0);\n\n   rule tdo_rule;\n       bscan.tdo(tdo_wire[0] | tdo_wire[1]);\n   endrule\n   Vector#(2, BscanTop) vloc;\n   for (Integer i = 0; i < 2; i = i + 1) begin\n     vloc[i] =\n      (interface BscanTop;\n         method rst = bscan.rst;\n         method tck = bscan.tck;\n         method reset = bscan.reset;\n         method capture = bscan.capture;\n         method shift = bscan.shift;\n         method tdi = bscan.tdi;\n         method update = bscan.update;\n         method first = bscan.first;\n         method Action tdo(Bit#(1) v);\n             tdo_wire[i] <= v;\n         endmethod\n      endinterface);\n   end\n   interface loc = vloc;\nendmodule\n\ninterface BscanBram#(type atype, type dtype);\n   interface BRAMClient#(atype, dtype) bramClient;\n   method Bit#(1) data_out();\nendinterface\n\nmodule mkBscanBram#(Integer id, atype addr, BscanTop bscan)(BscanBram#(atype, dtype))\n   provisos (Bits#(atype, asz), Bits#(dtype,dsz), Add#(1, a__, dsz));\n   let asz = valueOf(asz);\n   let dsz = valueOf(dsz);\n\n   Clock defaultClock <- exposeCurrentClock();\n   Reset defaultReset <- exposeCurrentReset();\n\n   Reg#(Bit#(asz)) addrReg <- mkReg(0);\n   Reg#(Bool) readData <- mkReg(False);\n   Reg#(Bool) firstItem <- mkReg(False);\n   Reg#(Bool) selected <- mkReg(False);\n   SyncBitIfc#(Bool) selectedj <- mkSyncBits(False, defaultClock, defaultReset, bscan.tck, bscan.rst);\n\n   Reg#(Bit#(dsz)) shiftReg <- mkReg(0, clocked_by bscan.tck, reset_by bscan.rst);\n   SyncBitIfc#(Bit#(dsz)) tojtag <- mkSyncBits(0, defaultClock, defaultReset, bscan.tck, bscan.rst);\n   SyncBitIfc#(Bit#(dsz)) fromjtag <- mkSyncBits(0, bscan.tck, bscan.rst, defaultClock, defaultReset);\n   SyncPulseIfc startWrite <- mkSyncHandshake(bscan.tck, bscan.rst, defaultClock);\n\n   rule captureRule if(bscan.capture() == 1);\n       shiftReg <= tojtag.read();\n   endrule\n   rule shiftRule if (bscan.shift() == 1);\n       shiftReg <= { bscan.tdi(), shiftReg[dsz-1:1] };\n   endrule\n   rule updateRule if(bscan.update() == 1);\n       startWrite.send();\n       fromjtag.send(shiftReg);\n   endrule\n\n   rule firstRule if (bscan.first());\n       firstItem <= True;\n       selected <= False;\n       selectedj.send(False);\n       tojtag.send(0);\n   endrule\n   rule addrRule if (startWrite.pulse());\n       let v = fromInteger(0);  // first time USER1, reset address\n       if (firstItem) begin\n           selected <= fromjtag.read() == fromInteger(id);\n           selectedj.send(fromjtag.read() == fromInteger(id));\n       end\n       else\n           v = addrReg + 1;\n       addrReg <= v;\n       firstItem <= False;\n   endrule\n   rule readdataRule;\n       readData <= startWrite.pulse();\n   endrule\n\n   interface BRAMClient bramClient;\n      interface Get request;\n\t method ActionValue#(BRAMRequest#(atype,dtype)) get() if ((selected && startWrite.pulse()) || readData);\n            return BRAMRequest {write:!readData, responseOnWrite:False, address:unpack(addrReg), datain:unpack(fromjtag.read())};\n\t endmethod\n      endinterface\n      interface Put response;\n\t method Action put(dtype d);\n            tojtag.send(pack(d));\n\t endmethod\n      endinterface\n   endinterface\n   method Bit#(1) data_out();\n      // the output lines are all OR'ed together when going back to the BSCAN core\n      if (selectedj.read())\n          return shiftReg[0];\n      else\n          return 0;\n   endmethod\nendmodule\n"
  },
  {
    "path": "lib/bsv/ConfigCounter.bsv",
    "content": "// Copyright (c) 2013 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\nimport GetPut::*;\n\ninterface ConfigCounter#(numeric type count_sz);\n   method Action decrement(UInt#(count_sz) x);\n   method ActionValue#(Bool) maybeDecrement(UInt#(count_sz) x);\n   method Action increment(UInt#(count_sz) x);\n   method UInt#(count_sz) read();\n   //method UInt#(count_sz) read_bypass();\n   method Bool positive();\nendinterface\n\nmodule mkConfigCounter#(UInt#(count_sz) init_val)(ConfigCounter#(count_sz));\n   Wire#(UInt#(count_sz)) inc_wire <- mkDWire(0);\n   Wire#(UInt#(count_sz)) dec_wire <- mkDWire(0);\n   Reg#(UInt#(count_sz)) cnt <- mkReg(init_val);\n   Reg#(Bool) positive_reg <- mkReg(False);\n   (* fire_when_enabled *)\n   rule react;\n      let new_count = (cnt + inc_wire) - dec_wire;\n      cnt <= new_count;\n      positive_reg <= (new_count > 0);\n   endrule\n   method Action increment(UInt#(count_sz) x);\n      inc_wire <= x;\n   endmethod\n   method Action decrement(UInt#(count_sz) x);\n      dec_wire <= x;\n   endmethod\n   method ActionValue#(Bool) maybeDecrement(UInt#(count_sz) x);\n      if (cnt >= x) begin\n\t dec_wire <= x;\n\t return True;\n      end\n      else\n\t return False;\n   endmethod\n   method UInt#(count_sz) read = cnt._read;\n   method Bool positive = positive_reg._read;\nendmodule\n"
  },
  {
    "path": "lib/bsv/ConnectalSpi.bsv",
    "content": "\n// Copyright (c) 2013-2014 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\n\nimport Clocks      :: *;\nimport GetPut      :: *;\nimport FIFOF       :: *;\nimport Probe       :: *;\nimport Connectable :: *;\nimport SpecialFIFOs:: *;\nimport SyncBits    :: *;\nimport StmtFSM     :: *;\nimport Assert      :: *;\nimport XilinxCells :: *;\nimport Vector      :: *;\nimport ConnectalClocks :: *;\n\n(* always_enabled *)\ninterface SpiMasterPins#(numeric type num_cs);\n    method Bit#(1) mosi();\n    method Bit#(num_cs) sel_n();\n    method Action miso(Bit#(1) v);\n    interface Clock clock;\n    interface Clock deleteme_unused_clock;\n    interface Reset deleteme_unused_reset;\nendinterface: SpiMasterPins\n\n(* always_enabled *)\ninterface SpiSlavePins#(numeric type num_cs);\n    method Action mosi(Bit#(1) v);\n    method Action sel_n(Bit#(num_cs) v);\n    method Bit#(1) miso();\n    method Action clock(Bit#(1) v);\n    interface Clock deleteme_unused_clock;\n    interface Reset deleteme_unused_reset;\nendinterface\n\ninterface SPIMaster#(type a, numeric type num_cs);\n   interface Vector#(num_cs, Put#(a)) request;\n   interface Vector#(num_cs, Get#(a)) response;\n   interface SpiMasterPins#(num_cs) pins;\nendinterface\n\ninterface SPISlave#(type a, numeric type num_cs);\n   interface Vector#(num_cs, Get#(a)) request;\n   interface Vector#(num_cs, Put#(a)) response;\n   interface SpiSlavePins#(num_cs) pins;\nendinterface\n\nmodule mkSpiMasterShifter#(Bool invert_clk) (SPIMaster#(a,num_cs)) provisos(Bits#(a,awidth),Add#(1,awidth1,awidth),Log#(awidth,logawidth));\n\n   Clock defaultClock <- exposeCurrentClock;\n   Reset defaultReset <- exposeCurrentReset;\n   ClockDividerIfc clockInverter <- mkClockInverter;\n   Clock spiClock = clockInverter.slowClock;\n   Reset spiReset <-  mkAsyncResetFromCR(2, clockInverter.slowClock);\n   Reg#(Bit#(awidth)) shiftreg <- mkReg(unpack(0));\n   Reg#(Bit#(num_cs)) selreg <- mkReg(maxBound);\n   Reg#(Bit#(TAdd#(logawidth,1))) countreg <- mkReg(0);\n   Reg#(Bit#(TLog#(num_cs))) ifcnumreg <- mkReg(0);\n   Vector#(num_cs, FIFOF#(a)) requestFifo <- replicateM(mkFIFOF);\n   Vector#(num_cs, FIFOF#(a)) resultFifo <- replicateM(mkFIFOF);\n\n   Clock outputClock = invert_clk ? clockInverter.slowClock : defaultClock;\n   Reset outputReset = defaultReset;\n   ReadOnly#(Bit#(awidth)) sync_shiftreg <- mkNullCrossingWire(outputClock, shiftreg);\n\n   Wire#(Bit#(1)) misoWire <- mkDWire(0);\n   let verbose = False;\n   \n   rule running if (countreg > 0);\n      countreg <= countreg - 1;\n      Bit#(awidth) newshiftreg = { shiftreg[valueOf(awidth)-2:0], misoWire };\n      if(verbose) $display(\"newshiftreg = %08h\", newshiftreg);\n      shiftreg <= newshiftreg;\n      if (countreg == 1 && resultFifo[ifcnumreg].notFull) begin\n\t resultFifo[ifcnumreg].enq(unpack(newshiftreg));\n\t selreg <= maxBound;\n      end\n   endrule\n\n   for (Integer i = 0; i < valueOf(num_cs); i = i + 1)\n      rule start_request if (countreg == 0);\n\t let v <- toGet(requestFifo[i]).get();\n\t ifcnumreg <= fromInteger(i);\n\t selreg <= ~(1 << fromInteger(i));\n\t shiftreg <= pack(v);\n\t countreg <= fromInteger(valueOf(awidth));\n      endrule\n\n   interface Vector request = map(toPut, requestFifo);\n   interface Vector response = map(toGet, resultFifo);\n\n   interface SpiMasterPins pins;\n      method Bit#(1) mosi();\n         return sync_shiftreg[valueOf(awidth)-1];\n      endmethod\n      method Bit#(num_cs) sel_n();\n\t return selreg;\n      endmethod\n      method Action miso(Bit#(1) v);\n         misoWire <= v;\n      endmethod\n      interface Clock clock = outputClock;\n      interface Clock deleteme_unused_clock = invert_clk ? defaultClock : clockInverter.slowClock;\n      interface Reset deleteme_unused_reset = defaultReset;\n   endinterface: pins\nendmodule: mkSpiMasterShifter\n\nmodule mkSpiSlaveShifter#(ReadOnly#(Bit#(1)) mosi,\n\t\t\t  ReadOnly#(Bit#(num_cs)) seln)(SPISlave#(a, num_cs))\n   provisos(Bits#(a,awidth),\n\t    Add#(__a,1,awidth),\n\t    Add#(TLog#(awidth),1,cwidth));\n   \n   let awidth = valueOf(awidth);\n   Reg#(Bit#(awidth)) shift_reg <- mkReg(0);\n   Reg#(Bit#(cwidth)) cnt_reg <- mkReg(0);\n\n   Vector#(num_cs, FIFOF#(a)) req_fifo <- replicateM(mkFIFOF);\n   Vector#(num_cs, FIFOF#(a)) resp_fifo <- replicateM(mkFIFOF);\n   \n   for (Integer i = 0; i < valueOf(num_cs); i = i + 1)\n      (* fire_when_enabled *)\n      rule mosi_rule if (seln._read[i] == 0);\n\t let s = shift_reg;\n\t if (cnt_reg == 0 && resp_fifo[i].notEmpty) begin\n\t    s = pack(resp_fifo[i].first);\n\t    resp_fifo[0].deq;\n\t end\n\t let new_s = {s[awidth-2:0],mosi._read};\n\t if (cnt_reg+1 == fromInteger(awidth) && req_fifo[i].notFull) begin\n\t    cnt_reg <= 0;\n\t    req_fifo[i].enq(unpack(new_s));\n\t end\n\t else begin\n\t    cnt_reg <= cnt_reg+1;\n\t    shift_reg <= new_s;\n\t end\n      endrule\n\n   interface request = map(toGet, req_fifo);\n   interface response = map(toPut, resp_fifo);\n   interface SpiSlavePins pins;\n      method Bit#(1) miso();\n\t return shift_reg[awidth-1];\n      endmethod\n   endinterface\n   \nendmodule : mkSpiSlaveShifter\n\nmodule mkSPISlave(SPISlave#(a, num_cs))\n   provisos(Bits#(a,awidth),\n\t    Add#(__a,1,awidth));\n\n   B2C1 b2c <- mkB2C1();\n   Clock def_clk <- exposeCurrentClock;\n   Clock spi_clk <- mkClockBUFG(clocked_by b2c.c);\n   Reset spi_rst <- mkAsyncResetFromCR(2, spi_clk);\n\n   Wire#(Bit#(1)) mosi_wire <- mkDWire(0);\n   Wire#(Bit#(num_cs)) seln_wire <- mkDWire(1);\n   Wire#(Bit#(1)) clk_wire  <- mkDWire(0);\n   \n   ReadOnly#(Bit#(1)) mosi_sync <- mkNullCrossingWire(spi_clk, mosi_wire);\n   ReadOnly#(Bit#(num_cs)) seln_sync <- mkNullCrossingWire(spi_clk, seln_wire);\n   SPISlave#(a,num_cs) shifter <- mkSpiSlaveShifter(mosi_sync, seln_sync, clocked_by spi_clk, reset_by spi_rst);\n   ReadOnly#(Bit#(1)) miso_sync <- mkNullCrossingWire(def_clk, shifter.pins.miso);\n\n   Vector#(num_cs, SyncFIFOIfc#(a)) responseFifo <- replicateM(mkSyncFIFOFromCC(1, spi_clk));\n   Vector#(num_cs, SyncFIFOIfc#(a)) requestFifo  <- replicateM(mkSyncFIFOToCC(1, spi_clk, spi_rst));\n   zipWithM(mkConnection, map(toPut, requestFifo),  shifter.request);\n   zipWithM(mkConnection, map(toGet, responseFifo), shifter.response);\n   \n   rule clk_rule;\n      b2c.inputclock(clk_wire);\n   endrule\n   \n   interface request = map(toGet, requestFifo); \n   interface response = map(toPut, responseFifo); \n   interface SpiSlavePins pins;\n      method Action mosi(Bit#(1) v);\n\t mosi_wire._write(v);\n      endmethod\n      method Action sel_n(Bit#(num_cs) v);\n\t seln_wire._write(v);\n      endmethod\n      method Bit#(1) miso();\n\t return miso_sync._read();\n      endmethod\n      method Action clock(Bit#(1) v);\n\t clk_wire._write(v);\n      endmethod\n      interface Clock deleteme_unused_clock = spi_clk;\n      interface Reset deleteme_unused_reset = spi_rst;\n   endinterface: pins\nendmodule : mkSPISlave\n\nmodule mkSPIMaster#(Integer divisor, Bool invert_clk)(SPIMaster#(a,num_cs))\n   provisos(Bits#(a,awidth),Add#(1,awidth1,awidth),Log#(awidth,logawidth));\n   ClockDividerIfc clockDivider <- mkClockDivider(divisor);\n   Reset slowReset <- mkAsyncResetFromCR(2, clockDivider.slowClock);\n   SPIMaster#(a, num_cs) spi <- mkSpiMasterShifter(invert_clk, clocked_by clockDivider.slowClock, reset_by slowReset);\n\n   Vector#(num_cs, SyncFIFOIfc#(a)) requestFifo <- replicateM(mkSyncFIFOFromCC(1, clockDivider.slowClock));\n   Vector#(num_cs, SyncFIFOIfc#(a)) responseFifo <- replicateM(mkSyncFIFOToCC(1, clockDivider.slowClock, slowReset));\n\n   zipWithM(mkConnection, map(toGet, requestFifo), spi.request);\n   zipWithM(mkConnection, spi.response, map(toPut, responseFifo));\n\n   //interface spiClock = spi.spiClock;\n   interface request = map(toPut, requestFifo);\n   interface response = map(toGet, responseFifo);\n   interface pins = spi.pins;\nendmodule: mkSPIMaster\n\nmodule mkSPI20(SPIMaster#(Bit#(20),1));\n   SPIMaster#(Bit#(20),1) spi <- mkSPIMaster(200, True);\n   return spi;\nendmodule\n\nmodule mkSpiTestBench(Empty);\n\n   Clock defaultClock <- exposeCurrentClock;\n   Reset defaultReset <- exposeCurrentReset;\n\n   Bit#(20) slaveV = 20'h96ed5;\n   Bit#(20) masterV = 20'h8baeb;\n   let verbose = False;\n\n   SPIMaster#(Bit#(20),1) spi <- mkSPIMaster(4, False);\n   Reg#(Bit#(20)) slaveCount <- mkReg(20, clocked_by spi.pins.clock, reset_by spi.pins.deleteme_unused_reset);\n   Reg#(Bit#(20)) slaveValue <- mkReg(slaveV, clocked_by spi.pins.clock, reset_by spi.pins.deleteme_unused_reset);\n   Reg#(Bit#(20)) responseValue <- mkReg(0, clocked_by spi.pins.clock, reset_by spi.pins.deleteme_unused_reset);\n   SyncBitIfc#(Bit#(1)) sync_sel_n <- mkSyncBits(0, defaultClock, defaultReset, spi.pins.clock, spi.pins.deleteme_unused_reset);\n\n   Probe#(Bit#(1)) probeSelN <- mkProbe(clocked_by spi.pins.clock, reset_by spi.pins.deleteme_unused_reset);\n   Probe#(Bit#(1)) probeMiso <- mkProbe(clocked_by spi.pins.clock, reset_by spi.pins.deleteme_unused_reset);\n   Probe#(Bit#(1)) probeMosi <- mkProbe(clocked_by spi.pins.clock, reset_by spi.pins.deleteme_unused_reset);\n\n   rule probePins;\n      probeSelN <= spi.pins.sel_n;\n      probeMosi <= spi.pins.mosi;\n   endrule\n\n   rule slaveIn if (spi.pins.sel_n == 0);\n      slaveCount <= slaveCount - 1;\n      slaveValue <= (slaveValue << 1);\n   endrule\n\n   rule miso if (spi.pins.sel_n == 0);\n      probeMiso <= slaveValue[19];\n      spi.pins.miso(slaveValue[19]);\n   endrule\n\n   rule spipins if (spi.pins.sel_n == 0);\n      if(verbose) $display(\"miso=%d mosi=%d sel=%d\", slaveValue[19], spi.pins.mosi, sync_sel_n.read());\n      responseValue <= { responseValue[18:0], spi.pins.mosi };\n   endrule\n\n   rule displaySlaveValue if (slaveCount == 0);\n      if(verbose) $display(\"slave received %h\", responseValue);\n      dynamicAssert(responseValue == masterV, \"wrong value received by slave\");\n   endrule\n\n   rule finished;\n      let result <- spi.response[0].get();\n      if(verbose) $display(\"master received %h\", result);\n      dynamicAssert(result == slaveV, \"wrong value received by master\");\n      $finish(0);\n   endrule\n\n   let once <- mkOnce(action\n      if(verbose) $display(\"master sending %h; slave sending %h\", masterV, slaveV);\n      $dumpvars();\n      spi.request[0].put(masterV);\n      endaction);\n   rule foobar;\n      once.start();\n   endrule\n\nendmodule\n"
  },
  {
    "path": "lib/bsv/Dma2BRAM.bsv",
    "content": "// Copyright (c) 2013 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\nimport BRAM::*;\nimport FIFO::*;\nimport Vector::*;\nimport Gearbox::*;\nimport FIFOF::*;\nimport SpecialFIFOs::*;\nimport GetPut::*;\nimport ClientServer::*;\nimport ConnectalMemTypes::*;\nimport MemWriteEngine::*;\nimport ConnectalMemUtils::*;\nimport Pipe::*;\n\ninterface BRAMWriter#(numeric type bramIdxWidth, numeric type busWidth);\n   method Action start(SGLId h, Bit#(MemOffsetSize) base, Bit#(bramIdxWidth) start_idx, Bit#(bramIdxWidth) finish_idx);\n   method ActionValue#(Bool) finish();\nendinterface\n   \ninterface BRAMReadClient#(numeric type bramIdxWidth, numeric type busWidth);\n   method Action start(SGLId h, Bit#(MemOffsetSize) base, Bit#(bramIdxWidth) start_idx, Bit#(bramIdxWidth) finish_idx);\n   method ActionValue#(Bool) finish();\n   interface MemReadClient#(busWidth) dmaClient;\nendinterface\n\ninterface BRAMWriteClient#(numeric type bramIdxWidth, numeric type busWidth);\n   method Action start(SGLId h, Bit#(MemOffsetSize) base, Bit#(bramIdxWidth) start_idx, Bit#(bramIdxWidth) finish_idx);\n   method ActionValue#(Bool) finish();\n   interface MemWriteClient#(busWidth) dmaClient;\nendinterface\n\ninterface BRAMPipeIn#(numeric type bramIdxWidth, numeric type busWidth);\n   interface PipeIn#(MemDataF#(busWidth)) pipe;\nendinterface\n\nmodule mkBRAMReadClient#(BRAMServer#(Bit#(bramIdxWidth),d) br)(BRAMReadClient#(bramIdxWidth,busWidth))\n   provisos(Bits#(d,dsz),\n\t    Div#(busWidth,dsz,nd),\n\t    Mul#(nd,dsz,busWidth),\n\t    Add#(1,a__,nd),\n\t    Add#(1,bramIdxWidth,cntW),\n\t    Mul#(TDiv#(busWidth, 8), 8, busWidth));\n   \n   Clock clk <- exposeCurrentClock;\n   Reset rst <- exposeCurrentReset;\n   FIFO#(void) f <- mkSizedFIFO(1);\n   Reg#(Bit#(cntW)) i <- mkReg(maxBound);\n   Reg#(Bit#(cntW)) j <- mkReg(maxBound);\n   Reg#(Bit#(cntW)) n <- mkReg(0);\n   Reg#(SGLId) ptr <- mkReg(0);\n   Reg#(Bit#(MemOffsetSize)) off <- mkReg(0);\n   Gearbox#(nd,1,d) gb <- mkNto1Gearbox(clk,rst,clk,rst); \n   \n   let bus_width_in_bytes = fromInteger(valueOf(busWidth)/8);\n   MemReader#(busWidth) re <- mkMemReader;\n   \n   rule feed_gearbox;\n      let v <- re.readServer.readData.get;\n      //$display(\"mkBRAMReadClient::readData.get %x\", v.data);\n      gb.enq(unpack(v.data));\n   endrule\n   \n   rule loadReq(i <= n);\n      re.readServer.readReq.put(MemRequest{sglId:ptr, offset:off, burstLen:bus_width_in_bytes, tag:0});\n      off <= off+bus_width_in_bytes;\n      //$display(\"mkBRAMReadClient::readReq.put %x, %x\", i, n);\n      i <= i+fromInteger(valueOf(nd));\n   endrule\n      \n   rule load(j <= n);\n      br.request.put(BRAMRequest{write:True, responseOnWrite:False, address:truncate(j), datain:gb.first[0]});\n      gb.deq;\n      j <= j+1;\n      //$display(\"mkBRAMReadClient::bramserver put write %x, %x\", j, n);\n      if (j == n)\n\t f.enq(?);\n   endrule\n   \n   rule discard(j > n);\n      gb.deq;\n   endrule\n   \n   method Action start(SGLId h, Bit#(MemOffsetSize) b, Bit#(bramIdxWidth) start_idx, Bit#(bramIdxWidth) finish_idx);\n      $display(\"mkBRAMReadClient::start(%h, %h, %h %h)\", h, b, start_idx, finish_idx);\n      i <= extend(start_idx);\n      j <= extend(start_idx);\n      n <= extend(finish_idx);\n      ptr <= h;\n      off <= b;\n   endmethod\n   \n   method ActionValue#(Bool) finish();\n      $display(\"mkBRAMReadClient::finish\");\n      f.deq;\n      return True;\n   endmethod\n   \n   interface dmaClient = re.readClient;\n\nendmodule\n\n\nmodule mkBRAMWriter#(Integer id,\n\t\t     BRAMServer#(Bit#(bramIdxWidth),d) br, \n\t\t     MemReadEngineServer#(busWidth) readServer)(BRAMWriter#(bramIdxWidth,busWidth))\n   provisos(Bits#(d,dsz),\n\t    Div#(busWidth,dsz,nd),\n\t    Mul#(nd,dsz,busWidth),\n\t    Add#(1,a__,nd),\n\t    Add#(1,bramIdxWidth,cntW),\n\t    Div#(busWidth,8,bwbytes),\n\t    Mul#(bwbytes, 8, busWidth),\n\t    Add#(b__, bramIdxWidth, 32),\n\t    Add#(c__, TLog#(nd), 32));\n\n   let verbose = False;\n   Clock clk <- exposeCurrentClock;\n   Reset rst <- exposeCurrentReset;\n   Reg#(Bit#(cntW)) j <- mkReg(maxBound);\n   Reg#(Bit#(cntW)) n <- mkReg(0);\n   Gearbox#(nd,1,d) gb <- mkNto1Gearbox(clk,rst,clk,rst);\n   Reg#(Bool) running <- mkReg(False);\n   FIFO#(void) doneFifo <- mkFIFO;\n   \n   rule feed_gearbox if (running);\n      let v <- toGet(readServer.data).get;\n      if(verbose) $display(\"mkBRAMWriter::feed_gearbox (%d) %x\", id, v.data);\n      gb.enq(unpack(v.data));\n      if (v.last)\n          doneFifo.enq(?);\n   endrule\n   \n   rule load(j <= n);\n      br.request.put(BRAMRequest{write:True, responseOnWrite:False, address:truncate(j), datain:gb.first[0]});\n      gb.deq;\n      j <= j+1;\n      if(verbose) $display(\"mkBRAMWriter::load (%d) %x, %x\", id, j, n);\n   endrule\n   \n   rule discard(j > n);\n      gb.deq;\n      if(verbose) $display(\"mkBRAMWriter::discard (%d) %x\", id, j);\n   endrule\n\n   method Action start(SGLId h, Bit#(MemOffsetSize) b, Bit#(bramIdxWidth) start_idx, Bit#(bramIdxWidth) finish_idx) if (!running);\n      if(verbose) $display(\"mkBRAMWriter::start (%d) %d, %d, %d %d\", id, h, b, start_idx, finish_idx);\n      Bit#(BurstLenSize) burst_len_bytes = fromInteger(valueOf(bwbytes));\n\n      Bit#(32) req_len_ds = extend(finish_idx-start_idx)+fromInteger(valueOf(nd));\n      Bit#(TLog#(nd)) zeros = 0;\n      Bit#(32) req_len_bytes = {zeros,req_len_ds[31:valueOf(TLog#(nd))]} * fromInteger(valueOf(bwbytes));\n\n      readServer.request.put(MemengineCmd{sglId:h, base:truncate(b), len:req_len_bytes, burstLen:burst_len_bytes, tag: 0});\n      if(verbose) $display(\"mkBRAMWriter::start id=%d offset=%d len=%d burstLen=%d\", id, b, req_len_bytes, burst_len_bytes);\n      j <= extend(start_idx);\n      n <= extend(finish_idx);\n      running <= True;\n   endmethod\n\n   method ActionValue#(Bool) finish() if (running);\n      if(verbose) $display(\"mkBRAMWriter::finish (%d)\", id);\n      doneFifo.deq;\n      running <= False;\n      return True;\n   endmethod\n   \nendmodule\n\nmodule mkBRAMWriteClient#(BRAMServer#(Bit#(bramIdxWidth),d) br)(BRAMWriteClient#(bramIdxWidth,busWidth))\n   provisos(Bits#(d,dsz),\n\t    Div#(busWidth,dsz,nd),\n\t    Mul#(nd,dsz,busWidth),\n\t    Add#(1,a__,nd),\n\t    Add#(1, d__, busWidth),\n\t    Add#(1, b__, TMul#(2, nd)),\n\t    Add#(nd, c__, TMul#(2, nd)),\n\t    Add#(1,bramIdxWidth,cntW),\n\t    Mul#(TDiv#(busWidth, 8), 8, busWidth));\n   \n   Clock clk <- exposeCurrentClock;\n   Reset rst <- exposeCurrentReset;\n   FIFO#(void) f <- mkSizedFIFO(1);\n   Reg#(Bit#(cntW)) i <- mkReg(maxBound);\n   Reg#(Bit#(cntW)) j <- mkReg(maxBound);\n   Reg#(Bit#(cntW)) n <- mkReg(0);\n   Reg#(SGLId) ptr <- mkReg(0);\n   Reg#(Bit#(MemOffsetSize)) off <- mkReg(0);\n   Gearbox#(1,nd,Bit#(dsz)) gb <- mk1toNGearbox(clk,rst,clk,rst);\n   \n   MemWriteEngine#(busWidth,busWidth,1,1) we <- mkMemWriteEngine;\n   Bit#(MemOffsetSize) bus_width_in_bytes = fromInteger(valueOf(busWidth)/8);\n      \n   rule drain_geatbox;\n      Vector#(nd,Bit#(dsz)) v = gb.first;\n      we.writeServers[0].data.enq(pack(v));\n      gb.deq;\n   endrule\n   \n   rule bramReq(j <= n);\n      //$display(\"mkBRAMWriteClient::bramReq %h\", j);\n      br.request.put(BRAMRequest{write:False, responseOnWrite:False, address:truncate(j), datain:?});\n      j <= j+1;\n   endrule\n\n   rule bramResp;\n      d rv <- br.response.get;\n      gb.enq(cons(pack(rv), nil));\n   endrule\n   \n   rule loadReq(i <= n);\n      we.writeServers[0].request.put(MemengineCmd{sglId:ptr, base:truncate(off), len:truncate(bus_width_in_bytes), burstLen:truncate(bus_width_in_bytes), tag: 0});\n      off <= off+bus_width_in_bytes;\n      i <= i+fromInteger(valueOf(nd));\n      //$display(\"mkBRAMWriteClient::loadReq %h\", i);\n   endrule\n   \n   rule loadResp;\n      let __x <- we.writeServers[0].done.get;\n      if (i > n)\n\t f.enq(?);\n   endrule\n   \n   method Action start(SGLId h, Bit#(MemOffsetSize) b, Bit#(bramIdxWidth) start_idx, Bit#(bramIdxWidth) finish_idx);\n      $display(\"mkBRAMWriteClient::start(%h, %h, %h %h)\", h, b, start_idx, finish_idx);\n      i <= extend(start_idx);\n      j <= extend(start_idx);\n      n <= extend(finish_idx);\n      ptr <= h;\n      off <= b;\n   endmethod\n   \n   method ActionValue#(Bool) finish();\n      $display(\"mkBRAMWriteClient::finish\");\n      f.deq;\n      return True;\n   endmethod\n   interface dmaClient = we.dmaClient;\nendmodule\n\nmodule mkBRAMPipeIn#(Integer id,\n\t\t     BRAMServer#(Bit#(bramIdxWidth),d) br)(BRAMPipeIn#(bramIdxWidth,busWidth))\n   provisos(Bits#(d,dsz),\n\t    Div#(busWidth,dsz,nd),\n\t    Mul#(nd,dsz,busWidth),\n\t    Add#(1,a__,nd),\n\t    Add#(1,bramIdxWidth,cntW),\n\t    Div#(busWidth,8,bwbytes),\n\t    Mul#(bwbytes, 8, busWidth),\n\t    Add#(b__, bramIdxWidth, 32),\n\t    Add#(c__, TLog#(nd), 32));\n\n   let verbose = False;\n   Clock clk <- exposeCurrentClock;\n   Reset rst <- exposeCurrentReset;\n   Reg#(Bit#(cntW)) j <- mkReg(0);\n   Reg#(Bit#(cntW)) n <- mkReg(0);\n   Gearbox#(nd,1,MemDataF#(dsz)) gb <- mkNto1Gearbox(clk,rst,clk,rst);\n   Reg#(Bool) running <- mkReg(False);\n   FIFO#(void) doneFifo <- mkFIFO;\n   FIFOF#(MemDataF#(busWidth)) dataFifo <- mkFIFOF();\n   \n   rule feed_gearbox;\n      let md <- toGet(dataFifo).get;\n      if(verbose) $display(\"mkBRAMWriter::feed_gearbox (%d) %x\", id, md.data);\n      Vector#(nd,Bit#(dsz)) ds = unpack(md.data);\n      Vector#(nd,MemDataF#(dsz)) mds = unpack(0);\n      for (Integer i = 0; i < valueOf(nd); i = i + 1)\n\t mds[i].data = ds[i];\n      if (md.last)\n\t mds[valueOf(nd)-1].last = True;\n      gb.enq(mds);\n   endrule\n   \n   rule load;\n      let md = gb.first[0];\n      $display(\"load id=%d j=%d data=%h\", id, j, md.data);\n      br.request.put(BRAMRequest{write:True, responseOnWrite:False, address:truncate(j), datain:unpack(md.data)});\n      gb.deq;\n      let nextj = j + 1;\n      if (md.last) begin\n\t nextj = 0;\n\t $display(\"end of stream j=%d\", j);\n\t end\n      j <= nextj;\n      if(verbose) $display(\"mkBRAMWriter::load (%d) %x, %x\", id, j, n);\n   endrule\n   \n   interface PipeIn pipe = toPipeIn(dataFifo);\n\nendmodule\n"
  },
  {
    "path": "lib/bsv/FrequencyCounter.bsv",
    "content": "// Copyright (c) 2014 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\nimport Clocks::*;\nimport FIFO::*;\nimport StmtFSM::*;\n\n\ninterface FrequencyCounter;\n   method Action start(Bit#(32) periodA);\n   method ActionValue#(Bit#(32)) elapsedCycles();\nendinterface\n\nmodule mkFrequencyCounter#(Clock clock, Reset reset)(FrequencyCounter);\n    Clock defaultClock <- exposeCurrentClock();\n    Reset defaultReset <- exposeCurrentReset();\n\n   Reg#(Bit#(32)) counter <- mkReg(0, clocked_by clock, reset_by reset);\n   SyncPulseIfc startElapsed <- mkSyncHandshake(defaultClock, defaultReset, clock);\n   SyncPulseIfc getElapsed <- mkSyncHandshake(defaultClock, defaultReset, clock);\n   SyncFIFOIfc#(Bit#(32)) elapsedFifo <- mkSyncFIFO(2, clock, reset, defaultClock);\n\n   rule cyclecount;\n      let c = counter + 1;\n      if (startElapsed.pulse())\n\t c = 0;\n      counter <= c;\n   endrule\n   rule calcElapsed if (getElapsed.pulse());\n      elapsedFifo.enq(counter);\n   endrule\n\n   Reg#(Bit#(32)) counterALimit <- mkReg(0);\n   Reg#(Bit#(32)) counterA      <- mkReg(0);\n   rule periodACount if (counterA < counterALimit);\n      counterA <= counterA + 1;\n      if (counterA == counterALimit - 1)\n\t getElapsed.send();\n   endrule\n\n   method Action start(Bit#(32) periodA);\n      counterA <= 0;\n      counterALimit <= periodA;\n      startElapsed.send();\n   endmethod\n   method ActionValue#(Bit#(32)) elapsedCycles();\n      elapsedFifo.deq();\n      return elapsedFifo.first();\n   endmethod\nendmodule\n\nmodule mkTB(Empty);\n   Clock c <- exposeCurrentClock();\n   Reset r <- exposeCurrentReset();\n   let fc <- mkFrequencyCounter(c,r);\n   \n   Stmt test =\n   (seq\n       delay(10);\n       fc.start(10);\n       action\n\t  let v <- fc.elapsedCycles;\n\t  $display(v);\n       endaction\n    endseq);\n   mkAutoFSM(test);\nendmodule"
  },
  {
    "path": "lib/bsv/HDMI.bsv",
    "content": "\n// Copyright (c) 2013 Nokia, Inc.\n// Copyright (c) 2013 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\n`include \"ConnectalProjectConfig.bsv\"\nimport Vector::*;\nimport Clocks::*;\nimport FIFO::*;\nimport FIFOF::*;\nimport SpecialFIFOs::*;\nimport GetPut::*;\nimport SyncBits::*;\nimport YUV::*;\nimport Arith::*;\n\n`ifdef ZC706\ntypedef 24 HdmiBits;\n`else\ntypedef 16 HdmiBits;\n`endif\n\ninterface HDMI#(type pixelType);\n    method Bit#(1) hdmi_vsync;\n    method Bit#(1) hdmi_hsync;\n    method Bit#(1) hdmi_de;\n    method pixelType hdmi_data;\n    interface Clock hdmi_clock_if;\n    interface Reset deleteme_unused_reset;\nendinterface\n\ninterface HdmiGeneratorRequest;\n    method Action setTestPattern(Bit#(1) v);\n    method Action setPatternColor(Bit#(32) v);\n    method Action setDePixel(Bit#(12) frontPorch, Bit#(12) syncWidth, Bit#(12) visible, Bit#(12) last, Bit#(12) mid);\n    method Action setDeLine(Bit#(11) frontPorch, Bit#(11) syncWidth, Bit#(11) visible, Bit#(11) last, Bit#(11) mid);\n    method Action waitForVsync(Bit#(32) unused);\nendinterface\ninterface HdmiGeneratorIndication;\n    method Action vsync(Bit#(64) v, Bit#(32) vs);\nendinterface\n\ninterface HdmiGenerator#(type pixelType);\n    interface HdmiGeneratorRequest request;\n    interface Get#(VideoData#(pixelType)) rgb888;\n    interface Put#(Bit#(32)) pdata;\nendinterface\n\nmodule mkHdmiGenerator#(Clock axi_clock, Reset axi_reset,\n   SyncPulseIfc startDMA, HdmiGeneratorIndication indication)(HdmiGenerator#(Rgb888));\n    let verbose = True;\n    Clock defaultClock <- exposeCurrentClock();\n    Reset defaultReset <- exposeCurrentReset();\n    // 1920 * 1080\n    // horiz: frontPorch:87, sync: 44, backPorch:148, pixel:1920\n    // vert: frontPorch:3, sync:5, backPorch:36, lines:1080\n`define hFront   87\n`define hSync    44\n`define hBack   148\n`define hPixel 1920\n`define vFront    3\n`define vSync     5\n`define vBack    36\n`define vLines 1080\n//`define hFront   88\n//`define hSync    44\n//`define hBack   280\n//`define hPixel 1920\n//`define vFront    4\n//`define vSync     5\n//`define vBack    45\n//`define vLines 1080\n    Reg#(Bit#(12)) dePixelStartSync <- mkSyncReg(              `hFront, axi_clock, axi_reset, defaultClock);\n    Reg#(Bit#(12)) dePixelEndSync <- mkSyncReg(           `hSync + `hFront, axi_clock, axi_reset, defaultClock);\n    Reg#(Bit#(12)) dePixelStartVisible <- mkSyncReg(`hBack + `hSync + `hFront, axi_clock, axi_reset, defaultClock);\n    Reg#(Bit#(12)) dePixelEnd <- mkSyncReg(  `hPixel + `hBack + `hSync + `hFront, axi_clock, axi_reset, defaultClock);\n    Reg#(Bit#(12)) dePixelMid <- mkSyncReg((`hPixel/2) + `hBack + `hSync, axi_clock, axi_reset, defaultClock);\n\n    Reg#(Bit#(11)) deLineStartSync <- mkSyncReg(              `vFront, axi_clock, axi_reset, defaultClock);\n    Reg#(Bit#(11)) deLineEndSync <- mkSyncReg(            `vSync + `vFront, axi_clock, axi_reset, defaultClock);\n    Reg#(Bit#(11)) deLineStartVisible <- mkSyncReg(  `vBack + `vSync + `vFront, axi_clock, axi_reset, defaultClock);\n    Reg#(Bit#(11)) deLineEnd <- mkSyncReg(    `vLines + `vBack + `vSync + `vFront, axi_clock, axi_reset, defaultClock);\n    Reg#(Bit#(11)) deLineMid <- mkSyncReg((`vLines/2) + `vBack + `vSync, axi_clock, axi_reset, defaultClock);\n\n    Vector#(4, Reg#(Bit#(24))) patternRegs <- replicateM(mkSyncReg(24'h00FFFFFF, axi_clock, axi_reset, defaultClock));\n    Reg#(Bit#(1)) shadowTestPatternEnabled <- mkSyncReg(1, axi_clock, axi_reset, defaultClock);\n    Reg#(Bool) waitingForVsync <- mkSyncReg(False, axi_clock, axi_reset, defaultClock);\n    SyncPulseIfc sendVsyncIndication <- mkSyncHandshake(defaultClock, defaultReset, axi_clock);\n\n    Reg#(Bit#(11)) lineCount <- mkReg(0);\n    Reg#(Bit#(12)) pixelCount <- mkReg(0);\n    Reg#(Bit#(1)) patternIndex0 <- mkReg(0);\n    Reg#(Bit#(1)) patternIndex1 <- mkReg(0);\n    Reg#(Bit#(1)) testPatternEnabled <- mkReg(1);\n    Reg#(Bool) dataEnable <- mkReg(False);\n    Reg#(Bool) lineVisible <- mkReg(False);\n    Reg#(Bit#(1)) vsync <- mkReg(0);\n    Reg#(Bit#(1)) hsync <- mkReg(0);\n    Reg#(Bit#(32)) vsyncCounter <- mkReg(0);\n\n    Reg#(VideoData#(Rgb888)) rgb888StageReg <- mkReg(unpack(0));\n    Reg#(Bool) evenOddPixelReg <- mkReg(False);\n\n    Reg#(Bit#(32)) underflowCount <- mkReg(0);\n    Reg#(Bit#(32)) underflowCountAxi <- mkSyncReg(0, defaultClock, defaultReset, axi_clock);\n    Reg#(Bit#(32)) counter <- mkReg(0, clocked_by axi_clock, reset_by axi_reset);\n    Reg#(Bit#(32)) elapsed <- mkReg(0, clocked_by axi_clock, reset_by axi_reset);\n    Reg#(Bit#(32)) elapsedVsync <- mkReg(0, clocked_by axi_clock, reset_by axi_reset);\n    SyncBitIfc#(Bit#(32)) vsyncCounters <- mkSyncBits(0, defaultClock, defaultReset, axi_clock, axi_reset);\n    Wire#(Bool) gotDataWire <- mkDWire(False);\n\n    rule vsyncaxi;\n       vsyncCounters.send(vsyncCounter);\n    endrule\n\n    rule axicyclecount;\n       counter <= counter + 1;\n    endrule\n      \n    rule vsyncReceived if (sendVsyncIndication.pulse());\n       $display(\"HDMI: sending vsync\");\n       elapsed <= counter;\n       elapsedVsync <= vsyncCounters.read();\n       indication.vsync(extend(elapsed - counter), vsyncCounter - vsyncCounter);\n       waitingForVsync <= False;\n    endrule\n\n    rule init_pattern;\n        patternRegs[1] <= 24'h00FF0000; // blue\n        patternRegs[2] <= 24'h0000FF00; // green\n        patternRegs[3] <= 24'h000000FF; // red\n        //patternRegs[1] <= 32'h80ff80ff; // yuv422 white\n        //patternRegs[2] <= 32'h2c961596; // yuv422 green\n        //patternRegs[3] <= 32'hff1d6b1d; // yuv422 red\n    endrule\n\n    rule inc_counters;\n        if (pixelCount == dePixelEnd) begin\n           if (testPatternEnabled == 0 && verbose)\n               $display(\"HDMI: endofline %d\", lineCount);\n           pixelCount <= 0; \n           dataEnable <= False;\n           patternIndex0 <= 0;\n           if (lineCount == deLineEnd) begin\n               lineCount <= 0;\n               patternIndex1 <= 0;\n               lineVisible <= False;\n               if (verbose)\n                   $display(\"HDMI: lineVisible off\");\n               testPatternEnabled <= shadowTestPatternEnabled;\n               $display(\"HDMI: lineend %d\", waitingForVsync);\n               if (waitingForVsync)\n\t          sendVsyncIndication.send();\n           end\n           else begin\n               if (lineCount == deLineStartVisible) begin\n                   lineVisible <= True;\n                   if (verbose)\n                       $display(\"HDMI: lineVisible on\");\n               end\n               lineCount <= lineCount+1;\n               if (lineCount >= deLineMid)\n                   patternIndex1 <= 1;\n           end\n        end\n        else begin\n           if (lineCount == deLineStartSync) begin\n              vsync <= 1;\n              if (pixelCount == 0 && testPatternEnabled == 0) begin\n                  vsyncCounter <= vsyncCounter+1;\n                  startDMA.send();\n                  $display(\"HDMI:vsync %d\", lineCount);\n              end\n           end\n           else if (lineCount == deLineEndSync)\n              vsync <= 0;\n           if (pixelCount == dePixelStartSync)\n              hsync <= 1;\n           else if (pixelCount == dePixelEndSync)\n              hsync <= 0;\n           if (pixelCount == dePixelStartVisible)\n               dataEnable <= lineVisible;\n           pixelCount <= pixelCount + 1;\n           if (pixelCount == dePixelMid)\n               patternIndex0 <= 1;\n        end\n    endrule\n\n    rule output_data_rule if (!dataEnable);\n        rgb888StageReg <= VideoData {de: 0, pixel: unpack(0), vsync: vsync, hsync: hsync };\n    endrule\n\n    rule testpattern_rule if (testPatternEnabled != 0 && dataEnable);\n        rgb888StageReg <= VideoData {de: 1, vsync: 0, hsync: 0, pixel: unpack(patternRegs[{patternIndex1, patternIndex0}])};\n    endrule\n\n    rule gdr if (testPatternEnabled == 0 && dataEnable && !gotDataWire);\n        $display(\"HDMI::nodata [%d:%d]\", lineCount, pixelCount);\n    endrule\n\n    interface Put pdata;\n        method Action put(Bit#(32) v) if (testPatternEnabled == 0 && dataEnable);\n           rgb888StageReg <= VideoData {de: 1, vsync: 0, hsync: 0, pixel: unpack(v[23:0])};\n           gotDataWire <= True;\n           //if (verbose)\n               //$display(\"HDMI::pdata         [%d:%d] = %x\", lineCount, pixelCount, v);\n        endmethod\n    endinterface\n\n    interface HdmiGeneratorRequest request;\n        method Action setPatternColor(Bit#(32) v);\n            patternRegs[0] <= v[23:0]; \n        endmethod\n        method Action setTestPattern(Bit#(1) v);\n            shadowTestPatternEnabled <= v;\n        endmethod\n        method Action setDePixel(Bit#(12) frontPorch, Bit#(12) syncWidth, Bit#(12) visible, Bit#(12) last, Bit#(12) mid);\n            dePixelStartSync <= frontPorch;\n            dePixelEndSync <= syncWidth;\n            dePixelStartVisible <= visible;\n            dePixelEnd <= last;\n            dePixelMid <= mid;\n        endmethod\n        method Action setDeLine(Bit#(11) frontPorch, Bit#(11) syncWidth, Bit#(11) visible, Bit#(11) last, Bit#(11) mid);\n            deLineStartSync <= frontPorch;\n            deLineEndSync <= syncWidth;\n            deLineStartVisible <= visible;\n            deLineEnd <= last;\n            deLineMid <= mid;\n        endmethod\n        method Action waitForVsync(Bit#(32) unused);\n            waitingForVsync <= True;\n            $display(\"HDMI: waitForVsync set\");\n        endmethod\n    endinterface\n   interface Get rgb888;\n      method ActionValue#(VideoData#(Rgb888)) get();\n\t return rgb888StageReg;\n      endmethod\n   endinterface\nendmodule\n\nmodule mkHDMI#(Get#(VideoData#(pixelType)) videoInput)(HDMI#(Bit#(pixelsz)))\n   provisos (Bits#(VideoData#(pixelType), a__), Bits#(pixelType,pixelsz));\n   Clock defaultClock <- exposeCurrentClock();\n   Reset defaultReset <- exposeCurrentReset();\n   Wire#(VideoData#(pixelType)) video <- mkDWire(unpack(0));\n   rule getvideo;\n      let v <- videoInput.get();\n      video <= v;\n   endrule\n\n   method Bit#(1) hdmi_vsync;\n      return video.vsync;\n   endmethod\n   method Bit#(1) hdmi_hsync;\n      return video.hsync;\n   endmethod\n   method Bit#(1) hdmi_de;\n      return video.de;\n   endmethod\n   method Bit#(pixelsz) hdmi_data;\n      return pack(video.pixel);\n   endmethod\n   interface hdmi_clock_if = defaultClock;\n   interface deleteme_unused_reset = defaultReset;\nendmodule\n\ninterface Rgb888ToYyuv;\n   interface Put#(VideoData#(Rgb888)) rgb888;\n   interface Get#(VideoData#(Yyuv)) yyuv;\nendinterface\n\n(* synthesize *)\nmodule mkRgb888ToYyuv(Rgb888ToYyuv);\n    Reg#(VideoData#(Rgb888))                        stage0Reg <- mkReg(unpack(0));\n    Reg#(VideoData#(Yuv444Intermediates))           stage1Reg <- mkReg(unpack(0));\n    Reg#(VideoData#(Vector#(2,Vector#(3,Bit#(16))))) stage2Reg <- mkReg(unpack(0));\n    Reg#(VideoData#(Yuv444))                        stage3Reg <- mkReg(unpack(0));\n    Reg#(VideoData#(Yyuv))                          stage4Reg <- mkReg(unpack(0));\n    Reg#(Bool) evenOddPixelReg <- mkReg(False);\n   \n    rule stage1_rule;\n        let previous = stage0Reg;\n        let pixel = previous.pixel;\n        stage1Reg <= VideoData {\n            vsync: previous.vsync, hsync: previous.hsync, de: previous.de,\n            pixel: (previous.de != 0) ? rgbToYuvIntermediates(pixel) : unpack(0)\n        };\n    endrule\n\n    rule stage2_rule;\n        let previous = stage1Reg;\n       Vector#(4, Vector#(3, Bit#(16))) vprev = previous.pixel;\n       Vector#(2, Vector#(3, Bit#(16))) vnext;\n       vnext[0] = vadd(vprev[0], vprev[1]);\n       vnext[1] = vadd(vprev[2], vprev[3]);\n\n       stage2Reg <= VideoData {\n            vsync: previous.vsync, hsync: previous.hsync, de: previous.de,\n\t    pixel: (previous.de != 0) ? vnext : unpack(0)\n        };\n    endrule\n\n   rule stage3_rule;\n      let previous = stage2Reg;\n       Vector#(2, Vector#(3, Bit#(16))) vprev = previous.pixel;\n      Yuv444 pixel = yuv444FromVector(vrshift(vadd(vprev[0], vprev[1]), 8));\n\n      stage3Reg <= VideoData {\n            vsync: previous.vsync, hsync: previous.hsync, de: previous.de,\n\t pixel: (previous.de != 0) ? pixel : unpack(0) };\n   endrule\n\n    rule stage4_rule;\n        let previous = stage3Reg;\n        if (previous.de != 0)\n            evenOddPixelReg <= !evenOddPixelReg;\n        Yyuv data = Yyuv { uv: evenOddPixelReg ? previous.pixel.u : previous.pixel.v,\n                           yy: previous.pixel.y };\n        stage4Reg <= VideoData {\n            vsync: previous.vsync, hsync: previous.hsync, de: previous.de,\n            pixel: data\n        };\n    endrule\n\n   interface Put rgb888;\n      method Action put(VideoData#(Rgb888) v);\n\t stage0Reg <= v;\n      endmethod\n   endinterface\n   interface Get yyuv;\n      method ActionValue#(VideoData#(Yyuv)) get();\n\t return stage4Reg;\n      endmethod\n   endinterface\nendmodule\n"
  },
  {
    "path": "lib/bsv/HdmiDisplay.bsv",
    "content": "// Copyright (c) 2012 Nokia, Inc.\n// Copyright (c) 2013 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n`include \"ConnectalProjectConfig.bsv\"\nimport FIFO::*;\nimport BRAMFIFO::*;\nimport Vector::*;\nimport Clocks::*;\nimport GetPut::*;\nimport ClientServer::*;\nimport Connectable::*;\nimport ConnectalMemTypes::*;\nimport MemReadEngine::*;\nimport HDMI::*;\nimport XADC::*;\nimport YUV::*;\nimport BlueScope::*;\n\ninterface HdmiDisplayRequest;\n   method Action startFrameBuffer(Int#(32) base, UInt#(32) byteCount);\n   method Action stopFrameBuffer();\n   method Action getTransferStats();\n   method Action setTraceTransfers(Bit#(1) trace);\nendinterface\ninterface HdmiDisplayIndication;\n   method Action transferStarted(Bit#(32) count);\n   method Action transferFinished(Bit#(32) count, Bit#(32) byteLen);\n   method Action transferStats(Bit#(32) count, Bit#(32) transferCycles, Bit#(64) sumOfCycles);\nendinterface\n\ninterface HdmiDisplay;\n`ifdef HDMI_BLUESCOPE\n   interface BlueScopeRequest  bluescopeRequest;\n   interface MemWriteClient#(64) bluescopeWriteClient;\n`endif\n    interface HdmiDisplayRequest displayRequest;\n    interface HdmiGeneratorRequest internalRequest;\n    interface Vector#(1, MemReadClient#(64)) dmaClient;\n    interface HDMI#(Bit#(HdmiBits)) hdmi;\n    interface XADC xadc;\nendinterface\n\ntypedef 3 NumOutstandingRequests;\ntypedef 64 FrameBufferBurstLenInBytes;\n\nmodule mkHdmiDisplay#(Clock hdmi_clock,\n\t\t      HdmiDisplayIndication hdmiDisplayIndication,\n\t\t      HdmiGeneratorIndication hdmiGeneratorIndication\n`ifdef HDMI_BLUESCOPE\n\t\t      , BlueScopeIndication bluescopeIndication\n`endif\n                      )(HdmiDisplay);\n   let verbose = False;\n   Clock defaultClock <- exposeCurrentClock;\n   Reset defaultReset <- exposeCurrentReset;\n   Reset hdmi_reset <- mkAsyncReset(2, defaultReset, hdmi_clock);\n   MakeResetIfc fifo_reset <- mkReset(2, True, defaultClock);\n   Reset fifo_reset_hdmi <- mkAsyncReset(2, fifo_reset.new_rst, hdmi_clock);\n\n   Reg#(UInt#(24)) byteCountReg <- mkReg(1080*1920);\n   Reg#(Bit#(24)) frameByte <- mkReg(99, clocked_by hdmi_clock, reset_by hdmi_reset);\n   Reg#(Bit#(24)) frameByteSaved <- mkSyncReg(1234, hdmi_clock, hdmi_reset, defaultClock);\n   Reg#(Bool) frameByteReady <- mkReg(False, clocked_by hdmi_clock, reset_by hdmi_reset);\n\n   Reg#(Bool) sendVsyncIndication <- mkReg(False);\n   SyncPulseIfc startDMA <- mkSyncHandshake(hdmi_clock, hdmi_reset, defaultClock);\n   Reg#(Bit#(1)) bozobit <- mkReg(0, clocked_by hdmi_clock, reset_by hdmi_reset);\n\n   Reg#(Maybe#(Bit#(32))) referenceReg <- mkReg(tagged Invalid);\n   MemReadEngine#(64,64,NumOutstandingRequests,1) memreadEngine <- mkMemReadEngine;\n\n   HdmiGenerator#(Rgb888) hdmiGen <- mkHdmiGenerator(defaultClock, defaultReset,\n\t\t\tstartDMA, hdmiGeneratorIndication, clocked_by hdmi_clock, reset_by hdmi_reset);\n`ifndef ZC706\n   Rgb888ToYyuv converter <- mkRgb888ToYyuv(clocked_by hdmi_clock, reset_by fifo_reset_hdmi);\n   mkConnection(hdmiGen.rgb888, converter.rgb888);\n   HDMI#(Bit#(HdmiBits)) hdmisignals <- mkHDMI(converter.yyuv, clocked_by hdmi_clock, reset_by hdmi_reset);\n`else\n   HDMI#(Bit#(HdmiBits)) hdmisignals <- mkHDMI(hdmiGen.rgb888, clocked_by hdmi_clock, reset_by hdmi_reset);\n`endif   \n`ifdef HDMI_BLUESCOPE\n   let bluescope <- mkSyncBlueScope(65536, bluescopeIndication, hdmi_clock, hdmi_reset, defaultClock, defaultReset);\n   MIMO#(1, 16, 64, Bit#(4)) mimo <- mkMIMO(MIMOConfiguration { unguarded: False, bram_based: False }, clocked_by hdmi_clock, reset_by hdmi_reset);\n   Reg#(Bool) triggered <- mkReg(False, clocked_by hdmi_clock, reset_by hdmi_reset);\n   rule toGearbox if ((hdmisignals.hdmi_vsync == 1) || triggered);\n      Bit#(4) v = 0;\n      v[0] = hdmisignals.hdmi_vsync;\n      v[1] = hdmisignals.hdmi_de;\n      v[2] = hdmisignals.hdmi_hsync;\n      v[3] = hdmisignals.hdmi_vsync;\n      triggered <= True;\n      if (mimo.enqReadyN(1))\n\t mimo.enq(1, cons(v,nil));\n      else\n\t $display(\"mimo.stalled mimo.count=%d\", mimo.count);\n   endrule\n   rule gearboxToBlueScope if (mimo.deqReadyN(16));\n      Bit#(64) v = pack(mimo.first());\n      mimo.deq(16);\n      bluescope.dataIn(v, v);\n   endrule\n`endif\n   rule toSaved if (hdmisignals.hdmi_vsync == 1);\n      if (frameByteReady && frameByte != 0) begin\n         frameByteSaved <= frameByte;\n         frameByte <= 0;\n      end\n      frameByteReady <= False;\n   endrule\n   rule endsync if (hdmisignals.hdmi_vsync != 1);\n      frameByteReady <= True;\n   endrule\n\n   SyncFIFOIfc#(Bit#(64)) synchronizer <- mkSyncBRAMFIFO(1024, defaultClock, fifo_reset.new_rst, hdmi_clock, fifo_reset_hdmi);\n   //SyncFIFOIfc#(Bit#(64)) synchronizer <- mkSyncFIFO(16, defaultClock, fifo_reset.new_rst, hdmi_clock);\n   Reg#(Bool) evenOdd <- mkReg(True, clocked_by hdmi_clock, reset_by fifo_reset_hdmi);\n   Reg#(Bit#(32)) savedPixelReg <- mkReg(0, clocked_by hdmi_clock, reset_by fifo_reset_hdmi);\n\n   Reg#(Bit#(32)) transferCount <- mkReg(0);\n   Reg#(Bit#(32)) transferCyclesSnapshot <- mkReg(0);\n   Reg#(Bit#(32)) transferCycles <- mkReg(0);\n   Reg#(Bit#(48)) transferSumOfCycles<- mkReg(0);\n   Reg#(UInt#(24)) transferWord <- mkReg(0);\n   Reg#(Bit#(32)) transferLast <- mkReg(0);\n   ClockDividerIfc slowClock <- mkClockDivider(64);\n   Reset slowReset <- mkAsyncReset(2, defaultReset, slowClock.slowClock);\n   SyncPulseIfc dmastartPulse <- mkSyncPulse(defaultClock, defaultReset, slowClock.slowClock);\n   SyncPulseIfc dmaendPulse <- mkSyncPulse(defaultClock, defaultReset, slowClock.slowClock);\n   Reg#(Bool) dmastart <- mkReg(False, clocked_by slowClock.slowClock, reset_by slowReset);\n   Reg#(Bool) dmaend <- mkReg(False, clocked_by slowClock.slowClock, reset_by slowReset);\n   Reg#(Bool) dmaendDelay <- mkReg(False, clocked_by slowClock.slowClock, reset_by slowReset);\n   Reg#(Bit#(3)) dmaCount <- mkReg(0);\n   Reg#(Bool) traceTransfers <- mkReg(False);\n   Reg#(Bool) dumpstarted <- mkReg(False);\n   Reg#(Bool) dumpover <- mkReg(False);\n   Reg#(Bool) duringDma <- mkReg(False);\n   //Reg#(Bool) dmaReady <- mkReg(False);\n   FIFO#(void)  doneFifo <- mkFIFO;\n\n   rule dmaPulserule;\n      dmastart <= dmastartPulse.pulse;\n      dmaend <= dmaendPulse.pulse;\n      dmaendDelay <= dmaend;\n   endrule\n   rule fromMemread;\n      let v <- toGet(memreadEngine.readServers[0].data).get;\n      synchronizer.enq(v.data);\n      if (verbose)\n          $display(\"hdmiDisplay: dmadata [%d]=%x cycle %d\", transferWord, v.data, transferCycles - transferCyclesSnapshot);\n      transferWord <= transferWord + 1;\n      transferLast <= transferCycles;\n      if (v.last)\n         doneFifo.enq(?);\n   endrule\n\n   rule doPut1 if (evenOdd);\n      Vector#(2,Bit#(32)) doublePixel = unpack(synchronizer.first);\n      synchronizer.deq;\n      savedPixelReg <= doublePixel[1];\n      frameByte <= frameByte + 1;\n      //if (dmaReady) begin\n         //if (verbose)\n            //$display(\"hdmiDisplay: SKIP     sync.deq %x:%x cycle %d\", doublePixel[0], doublePixel[1], transferCycles - transferCyclesSnapshot);\n      //end\n      //else begin\n         if (verbose)\n            $display(\"hdmiDisplay: even     sync.deq %x:%x cycle %d\", doublePixel[0], doublePixel[1], transferCycles - transferCyclesSnapshot);\n         hdmiGen.pdata.put(doublePixel[0]);\n         evenOdd <= !evenOdd;\n      //end\n   endrule      \n   rule doPut2 if (!evenOdd);\n      if (verbose)\n          $display(\"hdmiDisplay:     odd                             cycle %d\", transferCycles - transferCyclesSnapshot);\n      hdmiGen.pdata.put(savedPixelReg);\n      evenOdd <= !evenOdd;\n   endrule      \n\n   rule vsyncrule if (startDMA.pulse());\n      fifo_reset.assertReset();\n   endrule\n\n   rule startTransfer if (startDMA.pulse() &&& referenceReg matches tagged Valid .reference);\n   //   /dmaReady <= True;\n   ///endrule\n   //rule startd if (dmaReady && !duringDma &&& referenceReg matches tagged Valid .reference);\n      memreadEngine.readServers[0].request.put(MemengineCmd{sglId:reference, base:0, len:pack(extend(byteCountReg)), burstLen:fromInteger(valueOf(FrameBufferBurstLenInBytes)), tag: 0});\n      if (traceTransfers)\n\t hdmiDisplayIndication.transferStarted(transferCount);\n      transferCyclesSnapshot <= transferCycles;\n      transferWord <= 0;\n      $display(\"hdmiDisplay: startdma %d residual %d gap %d\", transferCycles - transferCyclesSnapshot,\n           byteCountReg - 8 * transferWord, transferCycles - transferLast);\n      dmastartPulse.send();\n      dmaCount <= dmaCount + 1;\n      if (dmaCount == 7 && !dumpover) begin\n         $dumpoff;\n         dumpover <= True;\n      end\n      //dmaReady <= False;\n      duringDma <= True;\n   endrule\n   rule countCycles;\n      transferCycles <= transferCycles + 1;\n   endrule\n   rule finishTransferRule;\n      doneFifo.deq;\n      transferCount <= transferCount + 1;\n      let tc = transferCycles - transferCyclesSnapshot;\n      transferSumOfCycles <= transferSumOfCycles + extend(tc);\n      if (traceTransfers)\n\t hdmiDisplayIndication.transferFinished(transferCount, extend(frameByteSaved));\n      $display(\"hdmiDisplay: enddma %d\", transferCycles - transferCyclesSnapshot);\n      dmaendPulse.send();\n      duringDma <= False;\n      if (!dumpstarted) begin\n         //$dumpfile(\"dump.vcd\");\n         $dumpvars;\n         $dumpon;\n         $display(\"VCDDUMP starting\");\n         dumpstarted <= True;\n      end\n   endrule\n\n    rule bozobit_rule;\n        bozobit <= ~bozobit;\n    endrule\n\n    interface HdmiDisplayRequest displayRequest;\n\tmethod Action startFrameBuffer(Int#(32) base, UInt#(32) byteCount);\n\t   byteCountReg <= truncate(byteCount);\n\t   $display(\"startFrameBuffer base %x count %d\", base, byteCount);\n           referenceReg <= tagged Valid truncate(pack(base));\n\tendmethod\n       method Action stopFrameBuffer();\n\t  referenceReg <= tagged Invalid;\n       endmethod\n       method Action getTransferStats();\n          hdmiDisplayIndication.transferStats(transferCount, transferCycles-transferCyclesSnapshot, extend(transferSumOfCycles));\n       endmethod\n       method Action setTraceTransfers(Bit#(1) trace);\n\t  traceTransfers <= unpack(trace);\n       endmethod\n    endinterface: displayRequest\n\n    interface MemReadClient dmaClient = cons(memreadEngine.dmaClient, nil);\n    interface HDMI hdmi = hdmisignals;\n    interface HdmiGeneratorRequest internalRequest = hdmiGen.request;\n`ifdef HDMI_BLUESCOPE\n    interface BlueScopeRequest bluescopeRequest = bluescope.requestIfc;\n    interface MemWriteClient bluescopeWriteClient = bluescope.writeClient;\n`endif\n    interface XADC xadc;\n        method Bit#(4) gpio;\n            return { bozobit, hdmisignals.hdmi_vsync,\n                //hdmisignals.hdmi_data[8], hdmisignals.hdmi_data[0]};\n                hdmisignals.hdmi_hsync, hdmisignals.hdmi_de};\n        endmethod\n    endinterface: xadc\nendmodule\n"
  },
  {
    "path": "lib/bsv/ImageonVita.bsv",
    "content": "// Copyright (c) 2013 Quanta Research Cambridge, Inc.\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n`include \"ConnectalProjectConfig.bsv\"\nimport Vector::*;\nimport Clocks::*;\nimport DefaultValue::*;\nimport XilinxCells::*;\nimport ConnectalClocks::*;\nimport ConnectalXilinxCells::*;\n\ntypedef struct {\n     Bool increment;\n     Bit#(1) ce;\n     Bit#(1) bitslip;\n} SerdesStart deriving (Bits);\n\ninterface IserdesCore;\n    method Action io_vita_data_p(Bit#(1) v);\n    method Action io_vita_data_n(Bit#(1) v);\n    method Bit#(10) data();\nendinterface: IserdesCore\n\nmodule mkIserdesCore#(Clock serdes_clock, Reset serdes_reset, Clock serdest,\n      Clock serdest_inverted, Bit#(1) astate_reset, SerdesStart param)(IserdesCore);\n    Wire#(Bit#(1)) vita_data_p <- mkDWire(0);\n    Wire#(Bit#(1)) vita_data_n <- mkDWire(0);\n`ifndef SIMULATION\n    Clock defaultClock <- exposeCurrentClock();\n    Reset defaultReset <- exposeCurrentReset();\n    IdelayE2 delaye2 <- mkIDELAYE2(IDELAYE2_Config {\n        cinvctrl_sel: \"FALSE\", delay_src: \"IDATAIN\",\n        high_performance_mode: \"TRUE\",\n        idelay_type: \"VARIABLE\", idelay_value: 0,\n        pipe_sel: \"FALSE\", refclk_frequency: 200, signal_pattern: \"DATA\"},\n        defaultClock, clocked_by serdes_clock);\n    Vector#(2, IserdesE2) iserdes_v;\n    iserdes_v[0] <- mkISERDESE2( ISERDESE2_Config{\n        data_rate: \"DDR\", data_width: 10,\n        dyn_clk_inv_en: \"FALSE\", dyn_clkdiv_inv_en: \"FALSE\",\n        interface_type: \"NETWORKING\", num_ce: 2, ofb_used: \"FALSE\",\n        init_q1: 0, init_q2: 0, init_q3: 0, init_q4: 0,\n        srval_q1: 0, srval_q2: 0, srval_q3: 0, srval_q4: 0,\n        serdes_mode: \"MASTER\", iobdelay: \"IFD\"},\n        serdest, serdest_inverted, clocked_by serdes_clock, reset_by serdes_reset);\n    iserdes_v[1] <- mkISERDESE2( ISERDESE2_Config{\n        data_rate: \"DDR\", data_width: 10,\n        dyn_clk_inv_en: \"FALSE\", dyn_clkdiv_inv_en: \"FALSE\",\n        interface_type: \"NETWORKING\", num_ce: 2, ofb_used: \"FALSE\",\n        init_q1: 0, init_q2: 0, init_q3: 0, init_q4: 0,\n        srval_q1: 0, srval_q2: 0, srval_q3: 0, srval_q4: 0,\n        serdes_mode: \"SLAVE\", iobdelay: \"NONE\"},\n        serdest, serdest_inverted, clocked_by serdes_clock, reset_by serdes_reset);\n    ReadOnly#(Bit#(1))ibufds_v <- mkIBUFDS(vita_data_p, vita_data_n);\n\n    (* no_implicit_conditions *)\n    rule setruledata;\n        delaye2.idatain(ibufds_v);\n    endrule\n    (* no_implicit_conditions *)\n    rule setrule;\n        delaye2.reset(astate_reset);\n        delaye2.cinvctrl(0);\n        delaye2.cntvaluein(0);\n        delaye2.ld(0);\n        delaye2.ldpipeen(0);\n        delaye2.datain(0);\n        delaye2.inc(param.increment);\n        delaye2.ce(param.ce);\n        for (Integer i = 0; i < 2; i = i + 1)\n            begin\n            iserdes_v[i].d(0);\n            iserdes_v[i].bitslip(param.bitslip);\n            iserdes_v[i].ce1(1);\n            iserdes_v[i].ce2(1);\n            iserdes_v[i].ofb(0);\n            iserdes_v[i].dynclkdivsel(0);\n            iserdes_v[i].dynclksel(0);\n            iserdes_v[i].oclk(0);\n            iserdes_v[i].oclkb(0);\n            iserdes_v[i].reset(astate_reset);\n            end\n        iserdes_v[0].ddly(delaye2.dataout());\n        iserdes_v[0].shiftin1(0);\n        iserdes_v[0].shiftin2(0);\n        iserdes_v[1].ddly(0);\n        iserdes_v[1].shiftin1(iserdes_v[0].shiftout1());\n        iserdes_v[1].shiftin2(iserdes_v[0].shiftout2());\n    endrule\n    method Bit#(10) data();\n        return {iserdes_v[1].q4(), iserdes_v[1].q3(), iserdes_v[0].q8(),\n           iserdes_v[0].q7(), iserdes_v[0].q6(), iserdes_v[0].q5(),\n           iserdes_v[0].q4(), iserdes_v[0].q3(), iserdes_v[0].q2(), iserdes_v[0].q1()};\n`else\n    method Bit#(10) data();\n        return 0;\n`endif\n    endmethod\n    method Action io_vita_data_p(Bit#(1) v);\n        vita_data_p <= v;\n    endmethod\n    method Action io_vita_data_n(Bit#(1) v);\n        vita_data_n <= v;\n    endmethod\nendmodule\n\ninterface SerdesClock;\n    interface Clock serdes_clkif;\n    interface Reset serdes_resetif;\n    interface Clock serdest_clkif;\n    method Action io_vita_clk_p(Bit#(1) v);\n    method Action io_vita_clk_n(Bit#(1) v);\nendinterface\n(* synthesize *)\nmodule mkSerdesClock(SerdesClock);\n    Clock defaultClock <- exposeCurrentClock();\n    Reset defaultReset <- exposeCurrentReset();\n`ifdef SIMULATION\n    Wire#(Bit#(1)) vita_clk_p <- mkDWire(0);\n    Wire#(Bit#(1)) vita_clk_n <- mkDWire(0);\n    interface Clock serdes_clkif = defaultClock;\n    interface Reset serdes_resetif = defaultReset;\n    interface Clock serdest_clkif = defaultClock;\n    method Action io_vita_clk_p(Bit#(1) v);\n    endmethod\n    method Action io_vita_clk_n(Bit#(1) v);\n    endmethod\n`else\n    B2C1 vita_clk_p <- mkB2C1();\n    B2C1 vita_clk_n <- mkB2C1();\n    Clock ibufds_clk <- mkClockIBUFDS(\n`ifdef ClockDefaultParam\n        defaultValue,\n`endif\n        vita_clk_p.c, vita_clk_n.c);\n    ClockGenIfc serdes_clk <- mkBUFR5(ibufds_clk);\n    ClockGenIfc serdest_clk <- mkBUFIO(ibufds_clk);\n    Reset serdes_reset <- mkAsyncReset(2, defaultReset, serdes_clk.gen_clk);\n    interface Clock serdes_clkif = serdes_clk.gen_clk;\n    interface Reset serdes_resetif = serdes_reset;\n    interface Clock serdest_clkif = serdest_clk.gen_clk;\n    method Action io_vita_clk_p(Bit#(1) v);\n        vita_clk_p.inputclock(v);\n    endmethod\n    method Action io_vita_clk_n(Bit#(1) v);\n        vita_clk_n.inputclock(v);\n    endmethod\n`endif\nendmodule\n\ninterface ImageClocks;\n   interface Clock imageon;\n   interface Clock hdmi;\nendinterface\n(* synthesize *)\nmodule mkImageClocks#(Clock fmc_imageon_clk1)(ImageClocks);\n`ifndef SIMULATION\n   ClockGenerator7AdvParams clockParams = defaultValue;\n   clockParams.bandwidth          = \"OPTIMIZED\";\n   clockParams.compensation       = \"ZHOLD\";\n   clockParams.clkfbout_mult_f    = 8.000;\n   clockParams.clkfbout_phase     = 0.0;\n   clockParams.clkin1_period      = 6.734007; // 148.5 MHz\n   clockParams.clkin2_period      = 6.734007;\n   clockParams.clkout0_divide_f   = 8.000;    // 148.5 MHz\n   clockParams.clkout0_duty_cycle = 0.5;\n   clockParams.clkout0_phase      = 0.0000;\n   clockParams.clkout1_divide     = 32;       // 37.125 MHz\n   clockParams.clkout1_duty_cycle = 0.5;\n   clockParams.clkout1_phase      = 0.0000;\n   clockParams.divclk_divide      = 1;\n   clockParams.ref_jitter1        = 0.010;\n   clockParams.ref_jitter2        = 0.010;\n   XClockGenerator7 clockGen <- mkClockGenerator7Adv(clockParams, clocked_by fmc_imageon_clk1);\n   C2B c2b_fb <- mkC2B(clockGen.clkfbout, clocked_by clockGen.clkfbout);\n   rule txoutrule5;\n      clockGen.clkfbin(c2b_fb.o());\n   endrule\n   Clock hdmi_clock <- mkClockBUFG(clocked_by clockGen.clkout0);    // 148.5   MHz\n   Clock imageon_clock <- mkClockBUFG(clocked_by clockGen.clkout1); //  37.125 MHz\n`else\n   Clock defaultClock <- exposeCurrentClock();\n   Clock hdmi_clock = defaultClock;\n   Clock imageon_clock = defaultClock;\n`endif\n   interface hdmi = hdmi_clock;\n   interface imageon = imageon_clock;\nendmodule\n"
  },
  {
    "path": "lib/bsv/IserdesDatadeser.bsv",
    "content": "\n// Copyright (c) 2013 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\nimport Vector::*;\nimport Clocks::*;\nimport FIFO::*;\nimport FIFOF::*;\nimport SyncBits::*;\nimport ImageonVita::*;\nimport IserdesDatadeserIF::*;\n\ntypedef Vector#(10, Reg#(Bit#(10))) TrainRotate;\n\ntypedef enum { AIdle, AReset, AEdge, AWait, AShift,\n     ARotated, AFirst, ASecond, AFound, AAlign} AState deriving (Bits,Eq);\n\n//(* synthesize *)\nmodule mkIserdesDatadeser#(Clock serdes_clock, Reset serdes_reset, Clock serdest, Bit#(1) align_start,\n    Bit#(1) autoalign, Bit#(10) training, Bit#(10) manual_tap, TrainRotate trainrot, Bool bvi_reset_reg,\n    Bool fifo_wren_sync)(IserdesDatadeser);\n\n    Clock defaultClock <- exposeCurrentClock();\n    Reset defaultReset <- exposeCurrentReset();\n    FIFOF#(Bit#(10)) dfifo <- mkFIFOF(clocked_by serdes_clock, reset_by serdes_reset);\n    SyncBitIfc#(Bit#(10)) dfifo_data <-  mkSyncBits(0, serdes_clock, serdes_reset, defaultClock, defaultReset);\n    SyncBitIfc#(Bit#(1)) dfifo_empty <-  mkSyncBit(serdes_clock, serdes_reset, defaultClock);\n    SyncBitIfc#(Bool) bvi_resets_reg <- mkSyncBit(serdes_clock, serdes_reset, defaultClock);\n    Reg#(Bit#(3)) ctrl_sample <- mkReg(0);\n\n    Reg#(AState)  astate <- mkReg(AIdle);\n    Reg#(Bit#(1)) astate_reset <- mkSyncReg(0, defaultClock, defaultReset, serdes_clock);\n    Reg#(Bit#(10)) data_init1 <- mkReg(0);\n    Reg#(Bit#(10)) data_init2 <- mkReg(0);\n    Reg#(Bit#(10)) edge_init <- mkReg(0);\n    Reg#(Bit#(10)) edge_int <- mkSyncReg(0, serdes_clock, serdes_reset, defaultClock);\n    Reg#(Bit#(11)) maxcount <- mkReg(0);\n    Reg#(Bit#(10)) windowcount <- mkReg(0);\n    Reg#(Bit#(16)) retrycounter <- mkReg(0);\n    Reg#(Bit#(16)) gencounter <- mkReg(0);\n\n    SyncFIFOIfc#(SerdesStart) serdes_start <- mkSyncFIFO(2, defaultClock, defaultReset, serdes_clock);\n    SyncFIFOIfc#(Bit#(1)) serdes_end <- mkSyncFIFO(2, serdes_clock, serdes_reset, defaultClock);\n    Reg#(Bit#(1)) serdes_running <- mkReg(0, clocked_by serdes_clock, reset_by serdes_reset);\n    Reg#(Bit#(10)) serdes_data <- mkReg(0, clocked_by serdes_clock, reset_by serdes_reset);\n    Reg#(SerdesStart) syncparam <- mkReg(unpack(0), clocked_by serdes_clock, reset_by serdes_reset);\n    Reg#(Bit#(3)) sync_counter <- mkReg(0, clocked_by serdes_clock, reset_by serdes_reset);\n    Reg#(Bit#(10)) ctrl_data <- mkSyncReg(0, serdes_clock, serdes_reset, defaultClock);\n    ClockDividerIfc serdest_inverted <- mkClockInverter(clocked_by serdest);\n    IserdesCore core <- mkIserdesCore(serdes_clock, serdes_reset, serdest,\n        serdest_inverted.slowClock, astate_reset, syncparam);\n\n    //*************************** alignment operation FSM *****************\n    rule afsminit_rule if (!bvi_resets_reg.read());\n        ctrl_sample <= 0;\n        edge_init <= 0;\n        data_init1 <= 0;\n        data_init2 <= 0;\n        maxcount <= -1;\n        windowcount <= 0;\n        retrycounter <= -1;\n        gencounter <= -1;\n        astate <= AIdle;\n    endrule\n\n    rule afsmidle2_rule if (bvi_resets_reg.read() && astate == AIdle && align_start == 1);\n        windowcount <= 0;\n        retrycounter <= 'h7ffd;\n        ctrl_sample <= 0;\n        astate <= AReset;\n        serdes_start.enq(SerdesStart{increment: False, ce:0, bitslip:0});\n    endrule\n    rule afsmdelay_rule if (bvi_resets_reg.read() && astate == AReset);\n        serdes_end.deq();\n        let gc = 15;\n        if (autoalign == 0)\n            begin\n            gc = {6'b0, manual_tap};\n            astate <= AFound;\n            end\n        else\n            astate <= AEdge;\n        maxcount <= 31;\n        gencounter <= gc;\n        serdes_start.enq(SerdesStart{increment: False, ce:~autoalign, bitslip:0});\n    endrule\n    rule afsmcedge1_rule if (bvi_resets_reg.read() && astate == AEdge\n            && retrycounter < 'h8000);\n        serdes_end.deq();\n        astate <= AIdle;\n    endrule\n    rule afsmcedge2_rule if (bvi_resets_reg.read() && astate == AEdge\n            && retrycounter >= 'h8000);\n        serdes_end.deq();\n        let mc = maxcount;\n        let inctemp = False;\n        if (edge_int != 0)\n            begin\n            data_init1 <= rotateBitsBy(ctrl_data, 10-1);\n            data_init2 <= rotateBitsBy(ctrl_data, 10-2);\n            edge_init <= edge_int;\n            astate <= AWait;\n            end\n        else if (maxcount[10] == 1)\n            astate <= AReset;\n        else\n            begin\n            maxcount <= maxcount - 1;\n            inctemp = True;\n            astate <= AEdge;\n            end\n        retrycounter <= retrycounter - 1;\n        serdes_start.enq(SerdesStart{increment: inctemp, ce:pack(inctemp), bitslip:0});\n    endrule\n    rule afsmwait_rule if (bvi_resets_reg.read() && astate == AWait);\n        serdes_end.deq();\n        let gc = gencounter - 1;\n        if (gencounter >= 'h8000)\n            begin\n            gc = 9;\n            astate <= AShift;\n            end\n        else\n            begin\n            let inctemp = False;\n            if (edge_init != edge_int)\n                begin\n                if (maxcount[10] == 1)\n                    astate <= AReset;\n                else\n                    begin\n                    gc = 14;\n                    inctemp = True;\n                    astate <= AEdge;\n                    end\n                retrycounter <= retrycounter - 1;\n                maxcount <= maxcount - 1;\n                end\n            serdes_start.enq(SerdesStart{increment: inctemp, ce:pack(inctemp), bitslip:0});\n            end\n        gencounter <= gc;\n    endrule\n    rule afsmcompare_rule if (bvi_resets_reg.read() && astate == AShift);\n        let gc = gencounter - 1;\n        if (gencounter >= 'h8000)\n            begin\n            let inctemp = False;\n            if (maxcount[10] == 1)\n                astate <= AReset;\n            else\n                begin\n                retrycounter <= retrycounter - 1;\n                gc = 14;\n                inctemp = True;\n                astate <= AEdge;\n                end\n            serdes_start.enq(SerdesStart{increment: inctemp, ce:pack(inctemp), bitslip:0});\n            end\n        else if (ctrl_data == trainrot[gencounter])\n            begin\n            let csamplein = 3'b001;\n            if (gencounter == 9)\n                csamplein = 3'b010;\n            else if (gencounter == 8)\n                csamplein = 3'b100;\n            ctrl_sample <= csamplein;\n            astate <= ARotated;\n            serdes_start.enq(SerdesStart{increment: True, ce:1, bitslip:0});\n            end\n        gencounter <= gc;\n        maxcount <= maxcount - 1;\n    endrule\n    rule afsm1changed_rule if (bvi_resets_reg.read() && astate == ARotated);\n        serdes_end.deq();\n        let inctemp = False;\n        if (ctrl_data == data_init1)\n            begin\n            gencounter <= 15;\n            astate <= AFirst;\n            end\n        else if (maxcount[10] == 1)\n            astate <= AReset;\n        else\n            begin\n            inctemp = True;\n            maxcount <= maxcount - 1;\n            end\n        serdes_start.enq(SerdesStart{increment: inctemp, ce:pack(inctemp), bitslip:0});\n    endrule\n    rule afsm1stable_rule if (bvi_resets_reg.read() && astate == AFirst);\n        serdes_end.deq();\n        let mc = maxcount;\n        let inctemp = True;\n        if (gencounter >= 'h8000)\n            begin\n            windowcount <= windowcount + 1;\n            mc = mc - 1;\n            astate <= ASecond;\n            end\n        else\n            begin\n            let gc = gencounter - 1;\n            if (ctrl_data == data_init1)\n                inctemp = False;\n            else\n                begin\n                mc = mc - 1;\n                gc = 15;\n                astate <= ARotated;\n                end\n            gencounter <= gc;\n            end\n        maxcount <= mc;\n        serdes_start.enq(SerdesStart{increment: inctemp, ce:pack(inctemp), bitslip:0});\n    endrule\n    rule afsmsecond_rule if (bvi_resets_reg.read() && astate == ASecond);\n        serdes_end.deq();\n        let inctemp = False;\n        if (ctrl_data == data_init2)\n            begin\n            gencounter <= {7'b0, windowcount[9:1]} - 16'b10;\n            astate <= AFound;\n            end\n        else if (maxcount[10] == 1)\n            astate <= AReset;\n        else\n            begin\n            windowcount <= windowcount + 1;\n            inctemp = True;\n            maxcount <= maxcount - 1;\n            end\n        serdes_start.enq(SerdesStart{increment: inctemp, ce:pack(inctemp), bitslip:0});\n    endrule\n    rule afsmfound_rule if (bvi_resets_reg.read() && astate == AFound);\n        serdes_end.deq();\n        let gc = gencounter;\n        if (gencounter >= 'h8000)\n            begin\n            if (ctrl_data != training)\n                begin\n                gc = 8;\n                astate <= AAlign;\n                serdes_start.enq(SerdesStart{increment: False, ce:1, bitslip:0});\n                end\n            else\n                astate <= AIdle;\n            end\n        else\n            begin\n            gc = gc - 1;\n            serdes_start.enq(SerdesStart{increment: autoalign == 1, ce:1, bitslip:0});\n            end\n        gencounter <= gc;\n    endrule\n    rule afsmalign_rule if (bvi_resets_reg.read() && astate == AAlign);\n        serdes_end.deq();\n        if (ctrl_data == training || gencounter >= 'h8000)\n            astate <= AIdle;\n        else\n            begin\n            gencounter <= gencounter - 1;\n            serdes_start.enq(SerdesStart{increment: False, ce:0, bitslip:1});\n            end\n    endrule\n\n    //*************************** serdes setting FSM *****************\n    rule serdes_idle_rule if (bvi_reset_reg);\n        if (serdes_start.notEmpty) begin\n            serdes_start.deq();\n            syncparam <= serdes_start.first;\n            serdes_running <= 1;\n            sync_counter <= 3;\n        end\n        else begin\n            syncparam <= unpack(0);\n            sync_counter <= sync_counter - 1;\n        end\n    endrule\n\n    rule serdes_running2_rule if (bvi_reset_reg && serdes_running == 1\n            && sync_counter[2] == 1);\n        ctrl_data <= serdes_data;\n        Bit#(10) edgeo = 0;\n        for (Integer i = 0; i < 9; i = i + 1)\n            edgeo[i] = serdes_data[i] ^ serdes_data[i+1];\n        edgeo[9] = serdes_data[0] ^ serdes_data[9];\n        edge_int <= edgeo;\n        serdes_end.enq(1);\n        serdes_running <= 0;\n    endrule\n\n    rule reset_clock_rule;\n        bvi_resets_reg.send(bvi_reset_reg);\n    endrule\n\n    rule qfsmall;\n        astate_reset <= pack(astate == AReset);\n    endrule\n    rule serdesreset_rule if (!bvi_reset_reg);\n        syncparam <= unpack(0);\n        serdes_running <= 0;\n        dfifo.clear();\n    endrule\n\n    rule clear_fifo if (astate_reset == 1);\n        dfifo.clear();\n    endrule\n\n    rule serdesda2_rule;\n        let dout = core.data();\n        serdes_data <= dout;\n        if (fifo_wren_sync)\n            dfifo.enq(dout);\n    endrule\n\n    rule serdesrule;\n        dfifo_data.send(dfifo.first);\n        dfifo.deq();\n    endrule\n    rule fifoe_rule;\n        dfifo_empty.send(pack(!dfifo.notEmpty()));\n    endrule\n\n    SyncBitIfc#(Bit#(14)) serdes_capture <-  mkSyncBits(0, serdes_clock,\n        serdes_reset, defaultClock, defaultReset);\n    Reg#(Bool) startCapture <- mkReg(False);\n    rule startcap;\n        if (bvi_resets_reg.read())\n            startCapture <= True;\n    endrule\n\n    rule capstateser;\n        serdes_capture.send({pack(syncparam), pack(fifo_wren_sync), serdes_data});\n    endrule\n\n    method Bit#(64) capture() if (startCapture); // early time capture\n        return {edge_int, windowcount[4:0], pack(astate), ctrl_data, gencounter, ctrl_sample, align_start, autoalign,\n            serdes_capture.read};\n    endmethod\n    method Bit#(1)                align_busy();\n        return pack(astate != AIdle);\n    endmethod\n    method Bit#(3)                samplein();\n        return ctrl_sample;\n    endmethod\n    method Bit#(1)                empty();\n        return dfifo_empty.read();\n    endmethod\n    method Bit#(10)               dataout();\n        return dfifo_data.read();\n    endmethod\n    method io_vita_data_p = core.io_vita_data_p;\n    method io_vita_data_n = core.io_vita_data_n;\nendmodule: mkIserdesDatadeser\n\f\nmodule mkISerdes#(Clock axi_clock, Reset axi_reset, ImageonSerdesIndication indication)(ISerdes);\n    Clock defaultClock <- exposeCurrentClock();\n    Reset defaultReset <- exposeCurrentReset();\n\n    SerdesClock coreClock <- mkSerdesClock();\n    Clock serdes_clock = coreClock.serdes_clkif;\n    Reset serdes_reset = coreClock.serdes_resetif;\n\n    Reg#(Bit#(1)) decoder_enable_reg <- mkSyncReg(0, axi_clock, axi_reset, defaultClock);\n    Reg#(Bit#(1)) serdes_auto_align_reg <- mkSyncReg(0, axi_clock, axi_reset, defaultClock);\n    Reg#(Bit#(1)) serdes_align_start_reg <- mkSyncReg(0, axi_clock, axi_reset, defaultClock);\n    Reg#(Bit#(1)) serdes_fifo_enable_reg <- mkSyncReg(0, axi_clock, axi_reset, defaultClock);\n    ReadOnly#(Bit#(1)) serdes_fifo_enable_null <- mkNullCrossingWire(serdes_clock, serdes_fifo_enable_reg);\n    Reg#(Bit#(10)) serdes_manual_tap_reg <- mkSyncReg(0, axi_clock, axi_reset, defaultClock);\n    Reg#(Bit#(10)) serdes_training_reg <- mkSyncReg(0, axi_clock, axi_reset, defaultClock);\n    Reg#(Bit#(1)) serdes_reset_reg <- mkSyncReg(1, axi_clock, axi_reset, defaultClock);\n    ReadOnly#(Bit#(1)) serdes_reset_null <- mkNullCrossingWire(serdes_clock, serdes_reset_reg);\n    Wire#(Bit#(50)) raw_data_wire <- mkDWire(0);\n    Wire#(Bit#(1)) empty_wire <- mkDWire(0);\n\n    SyncBitIfc#(Bit#(1)) serdes_align_busy_reg <- mkSyncBit(defaultClock, defaultReset, axi_clock);\n    Reg#(Bit#(1)) new_raw_empty_reg <- mkReg(1);\n    TrainRotate trainrot <- replicateM(mkSyncReg(0, axi_clock, axi_reset, defaultClock));\n    Vector#(5, IserdesDatadeser) pin_v <- replicateM(mkIserdesDatadeser(serdes_clock, serdes_reset, coreClock.serdest_clkif,\n\t  serdes_align_start_reg, serdes_auto_align_reg, serdes_training_reg,\n\t  serdes_manual_tap_reg, trainrot, serdes_reset_null != 0, serdes_fifo_enable_null != 0));\n\n    Reg#(Bit#(25)) control_data <- mkReg(0);\n    Reg#(Bit#(50)) dump_data <- mkReg(0);\n    rule sendup_imageon_clock;\n       Bit#(5) alignbusyw = 0;\n       Bit#(5) emptyw = 0;\n       Bit#(15) samplein = 0;\n       Bit#(50) rawdataw = 0;\n       for (Bit#(8) i = 0; i < 5; i = i+1) begin\n\t  alignbusyw[i] = pin_v[i].align_busy();\n\t  emptyw[i] = pin_v[i].empty();\n          samplein[(i+1)*3-1: i*3] = pin_v[i].samplein();\n\t  rawdataw[(i+1)*10-1: i*10] = pin_v[i].dataout();\n       end\n       serdes_align_busy_reg.send(pack(~alignbusyw == 0));\n       //bittest_wire <= pack(samplein == 3'b110);\n       empty_wire <= pack(emptyw != 0);\n       raw_data_wire <= rawdataw;\n       control_data <= {alignbusyw, emptyw, samplein};\n       dump_data <= rawdataw;\n    endrule\n\n    rule serdes_calc2;\n        new_raw_empty_reg <= empty_wire;\n    endrule\n    //rule clear_align if (serdes_align_busy_reg.read() == 1);\n        //serdes_align_start_reg <= 0;\n    //endrule\n\n    Reg#(Bool) runCapture <- mkSyncReg(False, axi_clock, axi_reset, defaultClock);\n    interface ImageonSerdesRequest request;\n\tmethod Action set_serdes_manual_tap(Bit#(10) v);\n\t    serdes_manual_tap_reg <= v;\n\tendmethod\n\tmethod Action set_serdes_training(Bit#(10) v);\n\t    serdes_training_reg <= v;\n            for (UInt#(4) i = 0; i < 10; i = i + 1)\n                trainrot[i] <= rotateBitsBy(v, i+6);\n\tendmethod\n\tmethod Action set_iserdes_control(Bit#(32) v);\n\t    serdes_reset_reg <= ~v[0];\n\t    serdes_auto_align_reg <= v[1];\n\t    serdes_align_start_reg <= v[2];\n\t    serdes_fifo_enable_reg <= v[3];\n\tendmethod\n        method Action get_iserdes_control();\n\t    let v = 0;\n\t    v[9] = serdes_align_busy_reg.read();\n            indication.iserdes_control_value(v);\n\tendmethod\n\tmethod Action set_decoder_control(Bit#(32) v);\n\t    decoder_enable_reg <= v[1];\n\tendmethod\n    endinterface\n\n    interface ImageonSerdesPins pins;\n        method Action io_vita_sync_p(Bit#(1) v);\n            pin_v[0].io_vita_data_p(v);\n        endmethod\n        method Action io_vita_sync_n(Bit#(1) v);\n            pin_v[0].io_vita_data_n(v);\n        endmethod\n        method Action io_vita_data_p(Bit#(4) v);\n            for (Integer i = 0; i < 4; i = i + 1)\n                pin_v[i+1].io_vita_data_p(v[i]);\n        endmethod\n        method Action io_vita_data_n(Bit#(4) v);\n            for (Integer i = 0; i < 4; i = i + 1)\n                pin_v[i+1].io_vita_data_n(v[i]);\n        endmethod\n        method io_vita_clk_p = coreClock.io_vita_clk_p;\n        method io_vita_clk_n = coreClock.io_vita_clk_n;\n    endinterface\n    interface SerdesData data;\n        method Reg#(Bit#(1)) reset();\n            return serdes_reset_reg;\n        endmethod\n        method Vector#(5, Bit#(10)) raw_data() if (new_raw_empty_reg == 0 && serdes_reset_reg != 0);\n            Vector#(5, Bit#(10)) in = unpack(raw_data_wire);\n            return in;\n\tendmethod\n        method Bit#(64) capture(); // late-time capture if (runCapture);\n            return pin_v[0].capture(); //{control_data, dump_data[38:0]};\n\tendmethod\n        method Action start_capture();\n            runCapture <= True;\n        endmethod\n    endinterface\nendmodule\n"
  },
  {
    "path": "lib/bsv/IserdesDatadeserIF.bsv",
    "content": "\n// Copyright (c) 2013 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\nimport Vector::*;\n\ninterface IserdesDatadeser;\n    method Bit#(1)          align_busy();\n    method Bit#(3)          samplein();\n    method Bit#(1)          empty();\n    method Bit#(10)         dataout();\n    method Action io_vita_data_p(Bit#(1) v);\n    method Action io_vita_data_n(Bit#(1) v);\n    method Bit#(64) capture();\nendinterface: IserdesDatadeser\n\n(* always_enabled *)\ninterface ImageonSerdesPins;\n    method Action io_vita_sync_p(Bit#(1) v);\n    method Action io_vita_sync_n(Bit#(1) v);\n    method Action io_vita_data_p(Bit#(4) v);\n    method Action io_vita_data_n(Bit#(4) v);\n    method Action io_vita_clk_p(Bit#(1) v);\n    method Action io_vita_clk_n(Bit#(1) v);\nendinterface\n\ninterface ImageonSerdesRequest;\n    method Action set_decoder_control(Bit#(32) v);\n    method Action set_iserdes_control(Bit#(32) v);\n    method Action set_serdes_manual_tap(Bit#(10) v);\n    method Action set_serdes_training(Bit#(10) v);\n    method Action get_iserdes_control();\nendinterface\ninterface ImageonSerdesIndication;\n    method Action iserdes_control_value(Bit#(32) v);\n    method Action iserdes_dma(Bit#(32) v);\nendinterface\n\ninterface SerdesData;\n    method Reg#(Bit#(1)) reset();\n    method Vector#(5, Bit#(10)) raw_data();\n    method Bit#(64) capture();\n    method Action start_capture();\nendinterface\n\ninterface ISerdes;\n    interface ImageonSerdesRequest request;\n    interface ImageonSerdesPins pins;\n    interface SerdesData data;\nendinterface\n"
  },
  {
    "path": "lib/bsv/Leds.bsv",
    "content": "\n// Copyright (c) 2013 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\n`include \"ConnectalProjectConfig.bsv\"\n`ifdef NUMBER_OF_LEDS\ntypedef `NUMBER_OF_LEDS LedsWidth;\n`else\n`ifdef XILINX\n`ifdef Artix7\ntypedef 4 LedsWidth;\n`else\n`ifdef BOARD_zybo\ntypedef 4 LedsWidth;\n`else\n`ifdef BOARD_zc706\ntypedef 4 LedsWidth;\n`else\n`ifdef BOARD_nfsume\ntypedef 2 LedsWidth;\n`else\ntypedef 8 LedsWidth;\n`endif\n`endif\n`endif\n`endif\n`elsif ALTERA\ntypedef 4 LedsWidth;\n`elsif VSIM\ntypedef 4 LedsWidth;\n`else\ntypedef 8 LedsWidth;\n`endif\n`endif\n\ninterface LEDS;\n    method Bit#(LedsWidth) leds;\nendinterface\n"
  },
  {
    "path": "lib/bsv/PipeMul.bsv",
    "content": "/* Copyright (c) 2014 Quanta Research Cambridge, Inc\n *\n * Permission is hereby granted, free of charge, to any person obtaining a\n * copy of this software and associated documentation files (the \"Software\"),\n * to deal in the Software without restriction, including without limitation\n * the rights to use, copy, modify, merge, publish, distribute, sublicense,\n * and/or sell copies of the Software, and to permit persons to whom the\n * Software is furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n * DEALINGS IN THE SOFTWARE.\n */\nimport FIFO::*;\nimport SpecialFIFOs::*;\nimport Complex::*;\nimport FIFOF::*;\nimport Vector::*;\nimport StmtFSM::*;\n\n\ninterface PipeMul#(numeric type stages, numeric type dsz, type marker);\n   method Action put(UInt#(dsz) x, UInt#(dsz) y, marker m);\n   method ActionValue#(Tuple2#(UInt#(dsz),marker)) get();\nendinterface\t     \n\nmodule mkPipeMul(PipeMul#(stages,dsz,marker))\n   provisos(Mul#(2,dsz,buff_width),\n\t    Add#(a__,dsz,buff_width),\n\t    Bits#(marker, b__));\n\n   Vector#(stages, Reg#(UInt#(buff_width))) mul_data <- replicateM(mkReg(0));\n   Vector#(TAdd#(stages,1),FIFO#(marker)) mul_ctrl <- replicateM(mkLFIFO);\n\t    \n   Reg#(UInt#(dsz))  a <- mkRegU;\n   Reg#(UInt#(dsz))  b <- mkRegU;\n   FIFO#(UInt#(dsz)) out <- mkLFIFO;\n   FIFO#(Tuple3#(UInt#(dsz),UInt#(dsz),marker)) inf <- mkLFIFO;\n   FIFO#(Tuple2#(UInt#(dsz),marker)) outf <- mkLFIFO;\n      \n   rule do_mul;\n      UInt#(buff_width) bits = extend(b) * extend(a);\n      mul_data[0] <= bits;\n      for(Integer i = 1; i < valueOf(stages); i = i+1)\n      \t mul_data[i] <= mul_data[i-1];\n   endrule\n   \n   for(Integer i = 0; i < valueOf(stages); i = i+1)\n      rule do_ctrl;\n   \t mul_ctrl[i+1].enq(mul_ctrl[i].first);\n   \t mul_ctrl[i].deq;\n      endrule\n   \n   rule final_xfer;\n      mul_ctrl[valueOf(stages)].deq;\n      UInt#(buff_width) bits = mul_data[valueOf(stages)-1];\n      UInt#(dsz) rv  = truncate(bits);\n      outf.enq(tuple2(rv,mul_ctrl[valueOf(stages)].first));\n   endrule\n   \n   rule start;\n      inf.deq;\n      a <= tpl_1(inf.first);\n      b <= tpl_2(inf.first);\n      mul_ctrl[0].enq(tpl_3(inf.first));\n   endrule\n\n   method Action put(UInt#(dsz) x, UInt#(dsz) y, marker m);\n      inf.enq(tuple3(x,y,m));\n   endmethod\n   \n   method ActionValue#(Tuple2#(UInt#(dsz),marker)) get();\n      outf.deq;\n      return outf.first;\n   endmethod\n   \nendmodule\n\ninterface PipeMul2#(numeric type stages, numeric type dsz, type marker);\n   method Action put(UInt#(dsz) x, UInt#(dsz) y, marker m);\n   method ActionValue#(Tuple2#(UInt#(TMul#(dsz,2)),marker)) get();\nendinterface\t     \n\nmodule mkPipeMul2(PipeMul2#(2,dsz,marker))\n   provisos(Add#(2,0,stages),\n\t    Mul#(2,dsz,odsz),\n\t    Add#(16,aszm16,dsz),\n\t    Add#(16,c__,odsz),\n\t    Add#(a__,dsz,odsz),\n\t    Bits#(marker, b__));\n\n   Vector#(stages, Reg#(Tuple2#(UInt#(odsz),UInt#(odsz)))) mul_data <- replicateM(mkReg(unpack(0)));\n   Vector#(TAdd#(stages,1),FIFO#(marker)) mul_ctrl <- replicateM(mkLFIFO);\n\t    \n   Reg#(UInt#(dsz))  a <- mkRegU;\n   Reg#(UInt#(dsz))  b <- mkRegU;\n   FIFO#(UInt#(dsz)) out <- mkLFIFO;\n   FIFO#(Tuple3#(UInt#(dsz),UInt#(dsz),marker)) inf <- mkLFIFO;\n   FIFO#(Tuple2#(UInt#(odsz),marker)) outf <- mkLFIFO;\n      \n   rule do_mul;\n      UInt#(odsz) lsbits = extend(b) * extend(unpack(pack(a)[15:0]));\n      UInt#(odsz) amsbits = unpack(pack(a)[valueOf(dsz)-1:16]);\n      UInt#(odsz) msbits = extend(b) * amsbits;\n      mul_data[0] <= tuple2(lsbits,msbits);\n   endrule\n   rule do_add;\n      match { .lsbits, .msbits } = mul_data[0];\n      UInt#(odsz) prod = lsbits + (msbits << 16);\n      mul_data[1] <= tuple2(0, prod);\n   endrule\n   \n   for(Integer i = 0; i < valueOf(stages); i = i+1)\n      rule do_ctrl;\n   \t mul_ctrl[i+1].enq(mul_ctrl[i].first);\n   \t mul_ctrl[i].deq;\n      endrule\n   \n   rule final_xfer;\n      mul_ctrl[valueOf(stages)].deq;\n      match { .zero, .rv } = mul_data[valueOf(stages)-1];\n      outf.enq(tuple2(rv,mul_ctrl[valueOf(stages)].first));\n   endrule\n   \n   rule start;\n      inf.deq;\n      a <= tpl_1(inf.first);\n      b <= tpl_2(inf.first);\n      mul_ctrl[0].enq(tpl_3(inf.first));\n   endrule\n\n   method Action put(UInt#(dsz) x, UInt#(dsz) y, marker m);\n      inf.enq(tuple3(x,y,m));\n   endmethod\n   \n   method ActionValue#(Tuple2#(UInt#(odsz),marker)) get();\n      outf.deq;\n      return outf.first;\n   endmethod\n   \nendmodule\n\n// module mkTestBench();\n//    PipeMul#(1,FixedPoint#(8,24)) multiplier <- mkPipeMul;\n//    Stmt test = \n//    seq\n//       multiplier.put(fromReal(-1.0),fromReal(2.0));\n//       action\n// \t let rv <- multiplier.get;\n// \t $write(\"mul: \");\n// \t dispFP824(rv);\n//       endaction\n//    endseq;\n//    mkAutoFSM(test);\n// endmodule\n\n\n"
  },
  {
    "path": "lib/bsv/SharedMemoryFifo.bsv",
    "content": "// Copyright (c) 2014 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\nimport Vector::*;\nimport BuildVector::*;\nimport GetPut::*;\nimport ClientServer::*;\nimport Gearbox::*;\nimport DefaultValue::*;\nimport FIFO::*;\nimport FIFOF::*;\nimport MIMO::*;\nimport Pipe::*;\nimport Portal::*;\nimport ConnectalMemTypes::*;\nimport ConnectalMemory::*;\n\ninterface SharedMemoryPipeOut#(numeric type dataBusWidth, numeric type pipeCount);\n   interface SharedMemoryPortalConfig cfg;\n   interface PipeOut#(Bit#(32)) data;\nendinterface\ninterface SharedMemoryPipeIn#(numeric type dataBusWidth);\n   interface SharedMemoryPortalConfig cfg;\nendinterface\n\n\ntypedef enum {\n   Idle,\n   WrPtrRequested, // 1\n   RdPtrRequested, // 2\n   RequestMessage, // 3\n   MessageHeaderRequested, // 4\n   MessageRequested, // 5\n   Drain,\n   UpdateRdPtr,\n   UpdateWrPtr,\n   UpdateWrPtr2,\n   Waiting,\n   SendHeader,\n   SendMessage,\n   SendPadding,\n   Stop\n   } SharedMemoryPortalState deriving (Bits,Eq);\n\nmodule mkSharedMemoryPipeOut#(Vector#(2, MemReadEngineServer#(64)) readEngine, Vector#(2, MemWriteEngineServer#(64)) writeEngine)(SharedMemoryPipeOut#(64,pipeCount));\n   // read the wrPtr and rdPtr pointers, if they are different, then read a request\n   Reg#(Bit#(32)) limitReg <- mkReg(0);\n   Reg#(Bit#(32)) wrPtrReg <- mkReg(0);\n   Reg#(Bit#(32)) rdPtrReg <- mkReg(0);\n   Reg#(Bit#(16)) countReg <- mkReg(0);\n   Reg#(Bit#(16)) messageWordsReg <- mkReg(0);\n   Reg#(Bit#(16)) methodIdReg <- mkReg(0);\n   Reg#(SharedMemoryPortalState) state <- mkReg(Idle);\n   Reg#(Bit#(32)) sglIdReg <- mkReg(0);\n   Reg#(Bool)     readyReg   <- mkReg(False);\n   MIMOConfiguration mimoConfig = defaultValue;\n   MIMO#(2,1,2,Bit#(32)) readMimo <- mkMIMO(mimoConfig);\n   FIFOF#(Bit#(32)) dataFifo <- mkFIFOF();\n\n   let verbose = False;\n\n   rule updateReqRdWrPtr if (state == Idle && readyReg);\n      if (verbose) $display(\"updateReqRdWrPtr\");\n      readEngine[0].request.put(\n          MemengineCmd {sglId: sglIdReg, base: 0, burstLen: 16, len: 16, tag: 0});\n      state <= WrPtrRequested;\n   endrule\n\n   rule receiveReqRdWrPtr if (state == WrPtrRequested || state == RdPtrRequested);\n      let v <- toGet(readEngine[0].data).get();\n      let w0 = v.data[31:0];\n      let w1 = v.data[63:32];\n      let wrPtr = wrPtrReg;\n      let rdPtr = rdPtrReg;\n      let limit = limitReg;\n      if (state == WrPtrRequested) begin\n\t limit = w0;\n         limitReg <= w0;\n         wrPtrReg <= w1;\n         wrPtr = w1;\n         state <= RdPtrRequested;\n      end\n      else begin\n         if (rdPtrReg == 0) begin\n            rdPtr = w0;\n            rdPtrReg <= rdPtr;\n         end\n         if (rdPtr != wrPtrReg)\n            state <= RequestMessage;\n         else\n            state <= Idle;\n      end\n      if (verbose)\n         $display(\"receiveReqRdWrPtr state=%d w0=%x w1=%x wrPtr=%d rdPtr=%d limit=%d\", state, w0, w1, wrPtr, rdPtr, limit);\n   endrule\n\n   rule requestMessage if (state == RequestMessage);\n      Bit#(32) wordCount = wrPtrReg - rdPtrReg;\n      if ((rdPtrReg & 1) == 1) begin\n         $display(\"WARNING requestMessage: reqRdPtr=%d is odd.\", rdPtrReg);\n      end\n      let rdPtr = rdPtrReg + wordCount;\n      if (wrPtrReg < rdPtrReg) begin\n         $display(\"requestMessage wrapped: wrPtr=%d rdPtr=%d\", wrPtrReg, rdPtrReg);\n         wordCount = limitReg - rdPtrReg;\n         rdPtr = 4;\n      end\n      if (verbose) $display(\"requestMessage id=%d rdPtr=%d wrPtr=%d wordCount=%d\", sglIdReg, rdPtrReg, wrPtrReg, wordCount);\n      rdPtrReg <= rdPtr;\n      countReg <= truncate(wordCount);\n      readEngine[1].request.put( MemengineCmd\n          {sglId: sglIdReg, base: extend(rdPtrReg << 2), burstLen: 16, len: wordCount << 2, tag: 0});\n      state <= MessageHeaderRequested;\n   endrule\n\n   let enqCount = 2;\n   rule demuxwords if (readMimo.enqReadyN(enqCount));\n      let v <- toGet(readEngine[1].data).get();\n      Vector#(2,Bit#(32)) dvec = unpack(v.data);\n      readMimo.enq(enqCount, dvec);\n   endrule\n\n   rule receiveMessageHeader if (state == MessageHeaderRequested);\n      let vec <- toGet(toPipeOut(readMimo)).get();\n      let hdr = vec[0];\n      let methodId = hdr[31:16];\n      let messageWords = hdr[15:0];\n\n      if (verbose)\n         $display(\"receiveMessageHeader hdr=%x methodId=%x messageWords=%d wordCount=%d\", hdr, methodId, messageWords, countReg);\n\n      methodIdReg <= methodId;\n      countReg <= countReg - 1;\n      messageWordsReg <= messageWords - 1;\n      dataFifo.enq(hdr);\n\n      if (hdr == 0) begin\n         if (countReg == 1)\n            state <= UpdateRdPtr;\n         else\n            state <= Drain;\n      end\n      else if (countReg == 1)\n         state <= UpdateRdPtr;\n      else if (messageWords == 1)\n         state <= MessageHeaderRequested;\n      else\n         state <= MessageRequested;\n   endrule\n\n   rule drain if (state == Drain);\n      let vec <- toGet(readMimo).get();\n      if (countReg == 1)\n         state <= UpdateRdPtr;\n      countReg <= countReg - 1;\n   endrule\n\n   rule receiveMessage if (state == MessageRequested);\n      let vec <- toGet(toPipeOut(readMimo)).get();\n      let data = vec[0];\n      if (verbose)\n         $display(\"receiveMessage data=%x messageWords=%d wordCount=%d\", data, messageWordsReg, countReg);\n      if (methodIdReg != 16'hFFFF)\n         dataFifo.enq(data);\n      messageWordsReg <= messageWordsReg - 1;\n      countReg <= countReg - 1;\n      if (countReg <= 1)\n         state <= UpdateRdPtr;\n      else if (messageWordsReg == 1)\n         state <= MessageHeaderRequested;\n   endrule\n\n   rule updateRdPtr if (state == UpdateRdPtr);\n      if (verbose)\n         $display(\"updateRdPtr: rdPtr=%d\", rdPtrReg);\n      // update the rdPtr pointer\n      writeEngine[0].request.put(\n          MemengineCmd {sglId: sglIdReg, base: 8, len: 8, burstLen: 8, tag: 0});\n      writeEngine[0].data.enq(extend(rdPtrReg));\n      state <= Waiting;\n   endrule\n\n   rule waiting if (state == Waiting);\n      let done <- writeEngine[0].done.get();\n      state <= Idle;\n   endrule\n\n   interface SharedMemoryPortalConfig cfg;\n      method Action setSglId(Bit#(32) id);\n\t if (verbose) $display(\"setSglId id=%d\", id);\n         sglIdReg <= id;\n         readyReg <= True;\n      endmethod\n   endinterface\n   interface data = toPipeOut(dataFifo);\nendmodule\n\nmodule mkSharedMemoryPipeIn#(PipeOut#(Bit#(32)) pipe,\n    Vector#(2,MemReadEngineServer#(64)) readEngine, Vector#(2, MemWriteEngineServer#(64)) writeEngine)(SharedMemoryPipeIn#(64));\n   let defaultClock <- exposeCurrentClock;\n   let defaultReset <- exposeCurrentReset;\n   // read the wrPtr and rdPtr pointers, if they are different, then read a request\n   Reg#(Bit#(16)) limitReg <- mkReg(0);\n   Reg#(Bit#(16)) wrPtrReg <- mkReg(0);\n   Reg#(Bit#(16)) rdPtrReg <- mkReg(0);\n   Reg#(Bit#(16)) messageWordsReg <- mkReg(0);\n   Reg#(Bit#(16)) methodIdReg <- mkReg(0);\n   Reg#(Bool) paddingReg <- mkReg(False);\n   Reg#(SharedMemoryPortalState) state <- mkReg(Idle);\n   Reg#(Bit#(32)) sglIdReg <- mkReg(0);\n   Reg#(Bool)     readyReg   <- mkReg(False);\n   function Bool pipeOutNotEmpty(PipeOut#(a) po); return po.notEmpty(); endfunction\n   Gearbox#(1,2,Bit#(32)) gb <- mk1toNGearbox(defaultClock, defaultReset, defaultClock, defaultReset);\n\n   let verbose = False;\n\n   rule updateIndRdWrPtr if (state == Idle && readyReg);\n      readEngine[0].request.put(\n          MemengineCmd {sglId: sglIdReg, base: 0, burstLen: 16, len: 16, tag: 0});\n      state <= WrPtrRequested;\n   endrule\n\n   rule receiveIndRdWrPtr if (state == WrPtrRequested || state == RdPtrRequested);\n      let md <- toGet(readEngine[0].data).get();\n      let data = md.data;\n      let w0 = data[31:0];\n      let w1 = data[63:32];\n      let wrPtr = wrPtrReg;\n      let rdPtr = rdPtrReg;\n      if (state == WrPtrRequested) begin\n         limitReg <= truncate(w0);\n         wrPtrReg <= truncate(w1);\n         wrPtr = truncate(w1);\n         state <= RdPtrRequested;\n      end\n      else begin\n         if (rdPtrReg == 0) begin\n            rdPtr = truncate(w0);\n            rdPtrReg <= rdPtr;\n         end\n         //if (rdPtr != wrPtrReg)\n            state <= SendHeader;\n         //else\n            //state <= Idle;\n      end\n      if (verbose)\n         $display(\"receiveIndRdWrPtr state=%d w0=%x w1=%x wrPtr=%d rdPtr=%d limit=%d\", state, w0, w1, wrPtr, rdPtr, limitReg);\n   endrule\n\n   rule send64bits;\n      let v = gb.first;\n      gb.deq();\n      if (verbose) $display(\"send64bits v=%h\", v);\n      writeEngine[0].data.enq(pack(v));\n   endrule\n\n   rule sendHeader if (state == SendHeader);\n      Bit#(32) hdr <- toGet(pipe).get();\n      Bit#(16) totalWords = hdr[15:0];\n      let messageWords = totalWords-1;\n      let padding      = totalWords[0] == 1;\n      let paddedWords = (padding) ? totalWords+1 : totalWords;\n      let wrPtr = wrPtrReg + paddedWords;\n      if (wrPtr > limitReg) begin\n\t $display(\"wrPtr wrapping\");\n\t wrPtr = 4;\n      end\n\n      $display(\"sendHeader hdr=%h messageWords=%d totalWords=%d paddingReg=%d wrPtrReg=%d wrPtr=%d\", hdr, messageWords, totalWords, paddingReg, wrPtrReg, wrPtr);\n      wrPtrReg <= wrPtr;\n      messageWordsReg <= messageWords;\n      paddingReg      <= padding;\n      gb.enq(vec(hdr));\n      writeEngine[0].request.put( MemengineCmd\n          {sglId: sglIdReg, base: extend(wrPtrReg) << 2, burstLen: 8, len: extend(paddedWords) << 2, tag: 0});\n      state <= SendMessage;\n   endrule\n\n   rule sendMessage if (state == SendMessage);\n      messageWordsReg <= messageWordsReg - 1;\n      let v <- toGet(pipe).get();\n      gb.enq(vec(v));\n      $display(\"sendMessage v=%h messageWords=%d paddingReg=%d\", v, messageWordsReg, paddingReg);\n      if (messageWordsReg == 1) begin\n         if (paddingReg)\n            state <= SendPadding;\n         else\n            state <= UpdateWrPtr;\n      end\n   endrule\n\n   rule sendPadding if (state == SendPadding);\n      $display(\"sendPadding\");\n      gb.enq(vec(32'hffff0001));\n      state <= UpdateWrPtr;\n   endrule\n\n   rule updateWrPtr if (state == UpdateWrPtr);\n      $display(\"updateWrPtr limit=%d wrPtr=%d\", limitReg, wrPtrReg);\n      Bit#(64) metadata = extend(limitReg);\n      gb.enq(vec(extend(limitReg)));\n      writeEngine[0].request.put(\n             MemengineCmd {sglId: sglIdReg, base: 0 << 2, burstLen: 8, len: 2 << 2, tag: 0});\n      state <= UpdateWrPtr2;\n   endrule\n\n   rule updateWrPtr2 if (state == UpdateWrPtr2);\n      $display(\"updateWrPtr2\");\n      gb.enq(vec(extend(wrPtrReg)));\n      state <= SendHeader;\n   endrule\n\n   rule done;\n      let done <- writeEngine[0].done.get();\n   endrule\n   rule done2;\n      let done <- writeEngine[1].done.get();\n   endrule\n\n   interface SharedMemoryPortalConfig cfg;\n      method Action setSglId(Bit#(32) id);\n         sglIdReg <= id;\n         readyReg <= True;\n      endmethod\n   endinterface\nendmodule\n"
  },
  {
    "path": "lib/bsv/SharedMemoryPortal.bsv",
    "content": "// Copyright (c) 2014 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\nimport BuildVector::*;\nimport ClientServer::*;\nimport Connectable::*;\nimport DefaultValue::*;\nimport FIFOF::*;\nimport Gearbox::*;\nimport GetPut::*;\nimport MIMO::*;\nimport Probe::*;\nimport Vector::*;\n\nimport Pipe::*;\nimport Portal::*;\nimport ConnectalMemTypes::*;\nimport ConnectalMemory::*;\nimport SharedMemoryFifo::*;\n\nmodule mkSharedMemoryRequestPortal#(PipePortal#(numRequests, numIndications, 32) portal,\n   function Bit#(16) messageSize(Bit#(16) methodNumber),\n   Vector#(2, MemReadEngineServer#(64)) readEngine, Vector#(2, MemWriteEngineServer#(64)) writeEngine)(SharedMemoryPortal#(64));\n   SharedMemoryPipeOut#(64,numRequests) pipeOut <- mkSharedMemoryPipeOut(readEngine, writeEngine);\n   SerialPortalDemux#(numRequests) demux <- mkSerialPortalDemux(Method);\n   mkConnection(pipeOut.data, demux.inputPipe);\n   mapM_(uncurry(mkConnection), zip(demux.data, portal.requests));\n\n   interface SharedMemoryPortalConfig cfg = pipeOut.cfg;\nendmodule\n\n// adds a header word to each message out of an indication pipe\nmodule mkFramedMessagePipe#(Integer portalNumber,\n\t\t\t    PipePortal#(numRequests,numIndications,32) pipePortal,\n\t\t\t    function Bit#(16) messageSize(Bit#(16) methodNumber),\n\t\t\t    Integer i)(PipeOut#(Bit#(32)));\n\n   let pipeOut = pipePortal.indications[i];\n   Bit#(16) messageBits = messageSize(fromInteger(i));\n   Bit#(16) roundup = messageBits[4:0] == 0 ? 0 : 1;\n   Bit#(16) numWords = (messageBits >> 5) + roundup;\n   Bit#(16) totalWords = numWords + 1;\n   Bit#(32) hdr = (fromInteger(portalNumber) << 24) | (fromInteger(i) << 16) | extend(numWords + 1);\n   let sendHeader <- mkReg(True);\n   Reg#(Bit#(16)) burstLenReg <- mkReg(0);\n   PipeOut#(Bit#(32)) framedPipe = (interface PipeOut;\n\t      method Bit#(32) first() if (pipeOut.notEmpty());\n\t         if (sendHeader)\n\t\t    return hdr;\n\t\t else\n\t\t    return pipeOut.first();\n\t      endmethod\n\t      method Action deq() if (pipeOut.notEmpty());\n\t         if (sendHeader) begin\n\t\t    sendHeader <= False;\n\t\t    burstLenReg <= numWords;\n\t\t end\n\t\t else begin\n\t\t    pipeOut.deq();\n\t\t    burstLenReg <= burstLenReg - 1;\n\t\t    if (burstLenReg == 1)\n\t\t       sendHeader <= True;\n\t\t end\n\t      endmethod\n\t      method Bool notEmpty(); return pipeOut.notEmpty(); endmethod\n\t   endinterface);\n   if (False) begin // optional pipeline stage\n      FIFOF#(Bit#(32)) framedFifo <- mkFIFOF();\n      mkConnection(framedPipe, toPipeIn(framedFifo));\n      return toPipeOut(framedFifo);\n   end\n   else begin\n      return framedPipe;\n   end\nendmodule\n\nmodule mkSharedMemoryIndicationPortal#(PipePortal#(numRequests,numIndications,32) pipePortal,\n\t\t\t\t       function Bit#(16) messageSize(Bit#(16) methodNumber),\n\t\t\t\t       Vector#(2, MemReadEngineServer#(64)) readEngines, Vector#(2, MemWriteEngineServer#(64)) writeEngines)\n   (SharedMemoryPortal#(64));\n\n   Vector#(numIndications, PipeOut#(Bit#(32))) indicationPipes <- genWithM(mkFramedMessagePipe(0,pipePortal,messageSize));\n\n   SerialPortalMux#(numIndications) serialPortalMux <- mkSerialPortalMux();\n   mkConnection(indicationPipes, serialPortalMux.data);\n   SharedMemoryPipeIn#(64) pipeIn <- mkSharedMemoryPipeIn(serialPortalMux.outputPipe, readEngines, writeEngines);\n   interface SharedMemoryPortalConfig cfg = pipeIn.cfg;\nendmodule\n\ninterface SerialPortalDemux#(numeric type pipeCount);\n   interface Vector#(pipeCount, PipeOut#(Bit#(32))) data;\n   interface PipeIn#(Bit#(32))                      inputPipe;\nendinterface\ninterface SerialPortalMux#(numeric type pipeCount);\n   interface Vector#(pipeCount, PipeIn#(Bit#(32))) data;\n   interface PipeOut#(Bit#(32))                    outputPipe;\nendinterface\n\ntypedef enum {\n   Idle,\n   MessageHeader,\n   MessageBody,\n   Stop\n   } SerialPortalState deriving (Bits,Eq);\n\ntypedef enum {\n   Portal,\n   Method\n   } SerialPortalDemuxLevel deriving (Bits,Eq);\n\nmodule mkSerialPortalDemux#(SerialPortalDemuxLevel portalDemux)(SerialPortalDemux#(pipeCount));\n   let clock <- exposeCurrentClock();\n   let reset <- exposeCurrentReset();\n   Reg#(Bit#(16)) messageWordsReg <- mkReg(0);\n   Reg#(Bit#(8))  selectorReg <- mkReg(0);\n   Reg#(SerialPortalState) state <- mkReg(Idle);\n   FIFOF#(Bit#(32)) inputFifo <- mkFIFOF();\n   Vector#(pipeCount, FIFOF#(Bit#(32))) dataFifo <- replicateM(mkFIFOF);\n\n   let verbose = False;\n\n   rule idle if (state == Idle);\n      state <= MessageHeader;\n   endrule\n\n   rule receiveMessageHeader if (state == MessageHeader);\n      let hdr <- toGet(inputFifo).get();\n      let selector = (portalDemux == Portal) ? hdr[31:24] : hdr[23:16];\n      let messageWords = hdr[15:0];\n      selectorReg <= selector;\n      if (verbose)\n         $display(\"receiveMessageHeader hdr=%x selector=%x messageWords=%d\", hdr, selector, messageWords);\n      if (portalDemux == Portal) // methodDemux need the header\n         dataFifo[selector].enq(hdr);\n      messageWordsReg <= messageWords - 1;\n      if (messageWords == 1)\n         state <= MessageHeader;\n      else\n         state <= MessageBody;\n   endrule\n\n   rule receiveMessage if (state == MessageBody);\n      let data <- toGet(inputFifo).get();\n      if (verbose)\n         $display(\"receiveMessage data=%x messageWords=%d\", data, messageWordsReg);\n      if (selectorReg != 8'hFF)\n         dataFifo[selectorReg].enq(data);\n      messageWordsReg <= messageWordsReg - 1;\n      if (messageWordsReg == 1)\n         state <= MessageHeader;\n   endrule\n\n   interface data      = map(toPipeOut, dataFifo);\n   interface inputPipe = toPipeIn(inputFifo);\nendmodule\n\nmodule mkSerialPortalMux(SerialPortalMux#(pipeCount));\n   let clock <- exposeCurrentClock;\n   let reset <- exposeCurrentReset;\n   Reg#(Bit#(16)) messageWordsReg <- mkReg(0);\n   Reg#(Bit#(16)) readyChannelReg <- mkReg(0);\n   Reg#(Bool)     interruptStatusReg <- mkReg(False);\n   Reg#(Bool) paddingReg <- mkReg(False);\n   Reg#(SerialPortalState) state <- mkReg(Idle);\n   Reg#(Bit#(32)) sglIdReg <- mkReg(0);\n\n   function Bool fifoNotEmpty(FIFOF#(a) fifo); return fifo.notEmpty(); endfunction\n\n   Vector#(pipeCount, FIFOF#(Bit#(32)))   inputFifos <- replicateM(mkFIFOF());\n   Vector#(pipeCount, PipeOut#(Bit#(32))) pipes      = map(toPipeOut, inputFifos);\n   Vector#(pipeCount, Bool)               readyBits  = map(fifoNotEmpty, inputFifos);\n   Bool      interruptStatus = False;\n   Bit#(16)  readyChannel = -1;\n   FIFOF#(Bit#(32)) outputFifo <- mkFIFOF();\n\n   let verbose = True;\n   let stateProbe <- mkProbe();\n   let messageWordsProbe <- mkProbe();\n   let messageDataProbe <- mkProbe();\n\n   for (Integer i = valueOf(pipeCount) - 1; i >= 0; i = i - 1) begin\n      if (readyBits[i]) begin\n         interruptStatus = True;\n         readyChannel = fromInteger(i);\n      end\n   end\n\n   rule idle if (state == Idle);\n      readyChannelReg <= readyChannel;\n      interruptStatusReg <= interruptStatus;\n      SerialPortalState nextState = Idle;\n      if (interruptStatus)\n\t nextState = MessageHeader;\n\n      state <= nextState;\n      stateProbe <= nextState;\n   endrule\n\n   rule sendHeader if (state == MessageHeader && interruptStatusReg);\n      Bit#(32) hdr <- toGet(inputFifos[readyChannelReg]).get();\n      Bit#(16) totalWords = hdr[15:0];\n      let messageWords = totalWords-1;\n      messageWordsProbe <= messageWords;\n\n      messageWordsReg <= messageWords;\n      outputFifo.enq(hdr);\n      state <= MessageBody;\n      stateProbe <= MessageBody;\n      messageDataProbe <= hdr;\n   endrule\n\n   rule sendMessage if (state == MessageBody);\n      messageWordsReg <= messageWordsReg - 1;\n      let v <- toGet(inputFifos[readyChannelReg]).get();\n      outputFifo.enq(v);\n      $display(\"sendMessage v=%h messageWords=%d paddingReg=%d\", v, messageWordsReg, paddingReg);\n      if (messageWordsReg == 1) begin\n         state <= Idle;\n\t stateProbe <= Idle;\n      end\n      messageDataProbe <= v;\n   endrule\n\n   interface data       = map(toPipeIn, inputFifos);\n   interface outputPipe = toPipeOut(outputFifo);\nendmodule\n"
  },
  {
    "path": "lib/bsv/SpiRoot.bsv",
    "content": "// Copyright (c) 2014 Quanta Research Cambridge, Inc.\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\nimport FIFO::*;\nimport SpiTap::*;\n\ntypedef struct {\n   Bit#(32) a;\n   Bit#(32) d;\n   } SpiItem deriving(Bits);\n\nmodule mkSpiRoot#(SpiTap root)(FIFO#(SpiItem));\n   FIFO#(SpiItem) request <- mkSizedFIFO(8);\n   FIFO#(SpiItem) response <- mkSizedFIFO(8);\n\n   Reg#(Bit#(6)) countin <- mkReg(0);   /* overflow at 63 -> 0 */\n   Reg#(Bit#(6)) countout <- mkReg(0);\n   Reg#(Bit#(64)) shifter <- mkReg(0);\n   Wire#(bit) framedrive <- mkDWire(0);\n   \n   /* implicit dependence on request fifo not empty */\n   rule send_item;\n      if (countin < 32)\n\t begin\n\t    root.in.data(request.first.a[countin&31]);\n\t    framedrive <= 1;\n\t    countin <= countin + 1;\n\t end\n      else\n\t begin\n\t    root.in.data(request.first.d[countin&31]);\n\t    framedrive <= 1;\n\t    countin <= countin + 1;\n\t end\n      if (countin == 63)\n\t request.deq();\n      endrule\n   \n   rule genframe;\n      root.in.frame(framedrive);\n   endrule\n   \n   rule handleFrame;\n      Bit#(64) tmp;\n      if (root.out.frame() == 0)\n\t begin\n\t    tmp = 0;\n\t    countout <= 0;\n\t end\n      else\n\t begin\n\t    countout <= countout + 1;\n\t    tmp = shifter;\n\t    tmp = tmp >> 1;\n\t    tmp[63] = root.out.data();\n\t    shifter <= tmp;\n\t end\n      if (countout == 63)\n\t    response.enq(SpiItem{a: tmp[31:0], d: tmp[63:32]});\n   endrule\n   // method Action enq = request.enq;\n   \n   \n   method Action enq(SpiItem x);\n      request.enq(x);\n   endmethod\n   \n   method Action deq();\n      response.deq();\n   endmethod\n   \n   method SpiItem first();\n      return response.first();\n   endmethod\n   \n   method Action clear();\n      request.clear();\n      response.clear();\n      countout <= 0;\n   endmethod\n\nendmodule\n\n"
  },
  {
    "path": "lib/bsv/SpiTap.bsv",
    "content": "// Copyright (c) 2014 Quanta Research Cambridge, Inc.\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\nimport Connectable::*;\n\n/* This is a simple serial bus\n * The frame bit indicates the valid period of a message\n * \n */\n\ninterface SpiTapIn;\n   method Action frame(bit f);\n   method Action data(bit d);\nendinterface\n\ninterface SpiTapOut;\n   method bit frame();\n   method bit data();\nendinterface\n\ninterface SpiTap;\n   interface SpiTapIn in;\n   interface SpiTapOut out;\nendinterface\n\ninterface SpiReg#(type a);\n   interface SpiTap tap;\n   interface Reg#(a) r;\nendinterface\n\ninstance Connectable#(SpiTapOut, SpiTapIn);\n   module mkConnection#(SpiTapOut out, SpiTapIn in)(Empty);\n      rule move_data;\n\t in.frame(out.frame());\n\t in.data(out.data());\n\t endrule\n   endmodule\nendinstance\n\nmodule mkSpiReg#(Bit#(32) id)(SpiReg#(a))\n   provisos(Bits#(a,asize),\n      Add#(a__, asize, 32));\n   Reg#(bit) frameinbit <- mkReg(0);\n   Reg#(bit) datainbit <- mkReg(0);\n   Wire#(bit) dataoutwire <- mkDWire(0);\n   \n   Reg#(Bit#(6)) count <- mkReg(0);\n   Reg#(Bit#(32)) shifter <- mkReg(0);\n   Reg#(Bool) addressmatch <- mkReg(False);\n   Reg#(Bool) iswrite <- mkReg(False);\n   Reg#(Bit#(asize)) data <- mkReg(0);\n   \n   rule handleFrame (frameinbit == 0);\n      count <= 0;\n      addressmatch <= False;\n   endrule\n   \n   rule handleShift (frameinbit == 1);\n      Bit#(32) tmp = shifter;\n      tmp = tmp >> 1;\n      tmp[31] = datainbit;\n      shifter <= tmp;\n      if (count == 31) \n\t begin\n\t    iswrite <= tmp[0] == 1;\n            addressmatch <= (id[31:1] == tmp[31:1]);\n         end\n      if ((count == 63) && addressmatch && iswrite)\n\t data <= truncate(tmp);\n      if ((count[5] == 1) && addressmatch && (!iswrite))\n          begin\n\t     if (valueof(asize) == 32)\n\t\tdataoutwire <= data[count & 31];\n\t     else\n\t\tbegin\n\t\t   if ((count & 31) < fromInteger(valueof(asize)))\n                      dataoutwire <= data[count & 31];\n\t\tend\n\t  end\n      else\n\t dataoutwire <= datainbit;\n      count <= count + 1;\n   endrule\n\n   interface SpiTap tap;\n   \n      interface SpiTapIn in;\n   \n\t method Action frame(bit i );\n\t    frameinbit <= i ;\n\t endmethod\n   \n\t method Action data( bit i );\n\t    datainbit <= i;\n\t endmethod\n\n      endinterface\n   \n      interface SpiTapOut out;\n      \n\t method bit frame();\n\t    return frameinbit;\n\t endmethod\n      \n\t method bit data();\n\t    return dataoutwire;\n\t endmethod\n   \n      endinterface\n   \n   endinterface\n\n   interface Reg r;\n\n      method Action _write(a v);\n\t data <= pack(v);\n      endmethod\n   \n      method a _read();\n\t return(unpack(data));\n      endmethod\n\n   endinterface\n\nendmodule\n\n"
  },
  {
    "path": "lib/bsv/Stack.bsv",
    "content": "// Copyright (c) 2014 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\n/*\n * Implementation of:\n *    simple stack\n */\n\nimport BRAM::*;\n\n\n/* the methods for load are split.  loadstart puts a request to the BRAM\n * and loadfinish gets the result\n */\n\ninterface Stack#(numeric type stackSize, numeric type frameSize, type a);\n   method Action store(Bit#(TLog#(frameSize)) offset, a v);\n   method Action loadstart(Bit#(TLog#(frameSize)) offset);\n   method ActionValue#(a) loadfinish();\n   method Action push();\n   method Action pop();\n   method Action reset();\nendinterface\n\nmodule mkStack#(int stackSize, int frameSize)(Stack#(stackSize, frameSize, a))\n   provisos(Log#(stackSize, fpBits),\n\t    Log#(frameSize, frameBits),\n\t    Add#(fpBits, frameBits, addressBits),\n            Literal#(a),\n            Bits#(a, a__));\n\n   BRAM1Port#(Bit#(addressBits), a) stack  <- mkBRAM1Server(defaultValue);\n   Reg#(UInt#(fpBits)) fp <- mkReg(0);\n   \n   method Action reset();\n      fp <= 0;\n   endmethod\n\n   method Action push();\n      fp <= min(fp+1, maxBound);\n   endmethod\n\n   method Action pop();\n      fp <= max(fp-1, 0);\n   endmethod\n\n   method Action store(Bit#(TLog#(frameSize)) offset, a v);\n     stack.portA.request.put(BRAMRequest{write: True, \n\tresponseOnWrite: False, \n\taddress: {pack(fp), offset}, datain: v});\n   endmethod\n   \n   /* read a value from current stack frame */\n   method Action loadstart(Bit#(TLog#(frameSize)) offset);\n      stack.portA.request.put(BRAMRequest{write: False, \n\t responseOnWrite: False, \n\t address: {pack(fp), offset}, datain: 0});\n   endmethod\n   \n   /* maybe this should just expose a server interface? */\n   \n   method ActionValue#(a) loadfinish();\n      let v = ?;\n      v <- stack.portA.response.get();\n      return(v);\n   endmethod\n   \n\nendmodule\n"
  },
  {
    "path": "lib/bsv/StackReg.bsv",
    "content": "// Copyright (c) 2014 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\n/*\n * Implementation of:\n *    simple stack for a type\n * \n * Single cycle push and pop, provided that consecutive pops aren't\n * too far apart\n */\n\nimport BRAM::*;\n\ninterface StackReg#(numeric type stackSize, type pctype, type argstype, type varstype);\n   method Action doreturn();\n   method Action docall(pctype jumpto, pctype returnto, argstype args, varstype vars);\n   method Action nextpc(pctype jumpto);\n   method Bit#(16) setjmp();\n   method Action longjump(Bit#(16) where);\n   interface Reg#(pctype) pc;\n   interface Reg#(argstype) args;\n   interface Reg#(varstype) vars;\nendinterface\n\nmodule mkStackReg#(int stackSize, pctype initialpc)(StackReg#(stackSize, pctype, argstype, varstype))\n   provisos(Log#(stackSize, addressBits),\n      Bits#(pctype, a__),\n      Bits#(argstype, b__),\n      Bits#(varstype, c__));\n\n   BRAM1Port#(Bit#(addressBits), pctype) pcstack  <- mkBRAM1Server(defaultValue);\n   BRAM1Port#(Bit#(addressBits), argstype) argsstack  <- mkBRAM1Server(defaultValue);\n   BRAM1Port#(Bit#(addressBits), varstype) varsstack  <- mkBRAM1Server(defaultValue);\n   Reg#(pctype) pctop <- mkReg(initialpc);\n   Reg#(pctype) pcnext <- mkReg(?);\n   Reg#(argstype) argstop <- mkReg(?);\n   Reg#(argstype) argsnext <- mkReg(?);\n   Reg#(varstype) varstop <- mkReg(?);\n   Reg#(varstype) varsnext <- mkReg(?);\n   Reg#(Bit#(addressBits)) fp <- mkReg(0);\n   PulseWire calling <- mkPulseWire();\n   PulseWire returning <- mkPulseWire();\n   Reg#(Bool) returningd1 <- mkReg(False);\n\n/* The \"next\" registers are there to compensate for the pipelined reads\n * of the BRAMs.  \n * A return in isolation pops next to top, and then replaces the contents of\n * next the following cycle when the BRAM read completes.\n * In the event that there are multiple returns in consecutive cycles, the\n * first return values are fed from the next registers into top, and the\n * following values are bypassed from the BRAMs direct to TOP.\n * Once return cycles stop happening, the final pending BRAM read data is\n * loaded into next\n * \n * If a call happens in the cycle after a return, the BRAM read <into> next and\n * the bram write <from> next are both supressed, and next is pushed from top\n * \n * The wire calling says there is a call in the current cycle. The signal\n * returning says there is a return in the current cycle. The signal returningd1\n * says there was a return in the previous cycle.\n */\n\n/*\n   Reg#(Bit#(8)) cyc <- mkReg(0);\n   \n   rule cc;\n      cyc <= cyc + 1;\n   endrule\n  */ \n   \n   /* The pop rules fire exactly when returningd1 is true */\n   rule poppc;\n     let v = ?;\n      //$display(\"%d poppc (c %d)\", cyc, calling);\n      v <- pcstack.portA.response.get();\n      if (!calling) pcnext <= v;\n      if (returning) pctop <= v;\n   endrule\n\n   rule popargs;\n     let v = ?;\n      v <- argsstack.portA.response.get();\n      if (!calling) argsnext <= v;\n      if (returning) argstop <= v;\n   endrule\n   \n   rule popvars;\n     let v = ?;\n      v <- varsstack.portA.response.get();\n      if (!calling) varsnext <= v;\n      if (returning) varstop <= v;\n   endrule\n   \n   (* fire_when_enabled, no_implicit_conditions *)\n   rule returning_delay;\n      returningd1 <= returning;\n   endrule\n\n   method Action docall(pctype jumpto, pctype returnto, argstype args, varstype vars);\n      fp <= min(fp+1, maxBound);\n      calling.send();\n      //$display(\"%d docall jumpto %d returnto %d (d1 %d)\", cyc, jumpto, returnto, returningd1);\n      if (! returningd1) \n\t begin\n\t    pcstack.portA.request.put(BRAMRequest{write: True, \n\t       responseOnWrite: False, \n\t       address: fp, datain: pcnext});\n\t    argsstack.portA.request.put(BRAMRequest{write: True, \n\t       responseOnWrite: False, \n\t       address: fp, datain: argsnext});\n\t    varsstack.portA.request.put(BRAMRequest{write: True, \n\t       responseOnWrite: False, \n\t       address: fp, datain: varsnext});\n\t end\n      pcnext <= returnto;\n      pctop <= jumpto;\n      argsnext <= argstop;\n      argstop <= args;\n      varsnext <= vars;\n      varstop <= vars;\n   endmethod\n\n   method Action doreturn();\n      fp <= max(fp-1, 0);\n      returning.send();\n      \n      pcstack.portA.request.put(BRAMRequest{write: False, \n\t responseOnWrite: False, \n\t address: fp-1, datain: ?});\n      argsstack.portA.request.put(BRAMRequest{write: False, \n\t responseOnWrite: False, \n\t address: fp-1, datain: ?});\n      varsstack.portA.request.put(BRAMRequest{write: False, \n\t responseOnWrite: False, \n\t address: fp-1, datain: ?});\n      //$display(\"%d doreturn pctop getting %d\", cyc, pcnext);\n     if (!returningd1)\n\tbegin\n\t   pctop <= pcnext;\n\t   argstop <= argsnext;\n\t   varstop <= varsnext;\n\tend\n   endmethod\n\n   method Action nextpc(pctype jumpto);\n      pctop <= jumpto;\n   endmethod\n\n   method Bit#(16) setjmp();\n      return 0;\n   endmethod\n\n   method Action longjump(Bit#(16) where);\n   // set fp <= where and pop? something like that\n   endmethod\n\n   \ninterface pc = pctop;\ninterface args = argstop;\ninterface vars = varstop;\n   \n   \n\nendmodule\n"
  },
  {
    "path": "lib/bsv/XADC.bsv",
    "content": "// Copyright (c) 2013 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\ninterface XADC;\n    method Bit#(4) gpio;\nendinterface\n\n"
  },
  {
    "path": "lib/bsv/XilinxVirtex7PCIE.bsv",
    "content": "////////////////////////////////////////////////////////////////////////////////\n// Copyright (c) 2012  Bluespec, Inc.  ALL RIGHTS RESERVED.\n// $Revision$\n// $Date$\n////////////////////////////////////////////////////////////////////////////////\n//  Filename      : XilinxVirtex7PCIE.bsv\n//  Description   :\n////////////////////////////////////////////////////////////////////////////////\npackage XilinxVirtex7PCIE;\n\n// Notes :\n// PART 1 of this file is pre-2014-10, for PCIE Gen 1&2, for VC707 etc.\n// PART 2 of this file is 2014-11, for PCIE3 (Gen 3), for VC709 etc.\n// (search for \"PART 1: PCIE\" and \"PART 2: PCIE3\"\n\n////////////////////////////////////////////////////////////////////////////////\n/// Imports\n////////////////////////////////////////////////////////////////////////////////\nimport Clocks            ::*;\nimport Vector            ::*;\nimport Connectable       ::*;\nimport GetPut            ::*;\nimport Reserved          ::*;\nimport TieOff            ::*;\nimport DefaultValue      ::*;\nimport DReg              ::*;\nimport Gearbox           ::*;\nimport FIFO              ::*;\nimport FIFOF             ::*;\nimport SpecialFIFOs      ::*;\nimport BRAMFIFO          ::*;\nimport ClientServer      ::*;\nimport BUtils            ::*;\n\nimport XilinxCells       ::*;\nimport XilinxClocks      ::*;\nimport PCIE              ::*;\n\n////////////////////////////////////////////////////////////////////////////////\n/// PART 1: PCIE (Gen 1 and 2, for VC707 etc.)\n/// This code existed in 2014-10\n////////////////////////////////////////////////////////////////////////////////\n\n////////////////////////////////////////////////////////////////////////////////\n/// Types\n////////////////////////////////////////////////////////////////////////////////\n\ntypedef struct {\n   Bit#(22)      user;\n   Bool          last;\n   Bit#(8)       keep;\n   Bit#(64)      data;\n} AxiRx deriving (Bits, Eq);\n\ntypedef struct {\n   Bool          last;\n   Bit#(8)       keep;\n   Bit#(64)      data;\n} AxiTx deriving (Bits, Eq);\n\n////////////////////////////////////////////////////////////////////////////////\n/// Interfaces PCIE: raw interface from wrapped verilog endpoint\n////////////////////////////////////////////////////////////////////////////////\n(* always_ready, always_enabled *)\ninterface PCIE_V7#(numeric type lanes);\n   interface PCIE_EXP#(lanes) pcie;\n   interface PCIE_TRN_V7      trn;\n   interface PCIE_AXI_TX_V7   axi_tx;\n   interface PCIE_AXI_RX_V7   axi_rx;\n   interface PCIE_PL_V7       pl;\n   interface PCIE_CFG_V7      cfg;\n   interface PCIE_INT_V7      cfg_interrupt;\n   interface PCIE_ERR_V7      cfg_err;\nendinterface\n\n(* always_ready, always_enabled *)\ninterface PCIE_TRN_V7;\n   interface Clock            clk;\n   interface Reset            reset;\n   method    Bool             lnk_up;\n   method    Bit#(8)          fc_ph;\n   method    Bit#(12)         fc_pd;\n   method    Bit#(8)          fc_nph;\n   method    Bit#(12)         fc_npd;\n   method    Bit#(8)          fc_cplh;\n   method    Bit#(12)         fc_cpld;\n   method    Action           fc_sel(FlowControlInfoSelect i);\nendinterface\n\n(* always_ready, always_enabled *)\ninterface PCIE_AXI_TX_V7;\n   method    Action           tlast(Bool i);\n   method    Action           tdata(Bit#(64) i);\n   method    Action           tkeep(Bit#(8) i);\n   method    Action           tvalid(Bool i);\n   method    Bool             tready();\n   method    Action           tuser(Bit#(4) i);\n   method    Bit#(6)          tbuf_av();\n   method    Bool             terr_drop();\n   method    Bool             tcfg_req();\n   method    Action           tcfg_gnt(Bool i);\nendinterface\n\n(* always_ready, always_enabled *)\ninterface PCIE_AXI_RX_V7;\n   method    Bool             rlast();\n   method    Bit#(64)         rdata();\n   method    Bit#(8)          rkeep();\n   method    Bit#(22)         ruser();\n   method    Bool             rvalid();\n   method    Action           rready(Bool i);\n   method    Action           rnp_ok(Bool i);\n   method    Action           rnp_req(Bool i);\nendinterface\n\n(* always_ready, always_enabled *)\ninterface PCIE_PL_V7;\n   method    Bit#(3)     initial_link_width;\n   method    Bool        phy_link_up;\n   method    Bit#(2)     lane_reversal_mode;\n   method    Bit#(1)     link_gen2_capable;\n   method    Bit#(1)     link_partner_gen2_supported;\n   method    Bit#(1)     link_upcfg_capable;\n   method    Bit#(1)     sel_link_rate;\n   method    Bit#(2)     sel_link_width;\n   method    Bit#(6)     ltssm_state;\n   method    Bit#(2)     rx_pm_state;\n   method    Bit#(3)     tx_pm_state;\n   method    Action      directed_link_auton(Bit#(1) i);\n   method    Action      directed_link_change(Bit#(2) i);\n   method    Action      directed_link_speed(Bit#(1) i);\n   method    Action      directed_link_width(Bit#(2) i);\n   method    Bit#(1)     directed_change_done;\n   method    Action      upstream_prefer_deemph(Bit#(1) i);\n   method    Bit#(1)     received_hot_rst;\nendinterface\n\n(* always_ready, always_enabled *)\ninterface PCIE_CFG_V7;\n   method    Bit#(32)    dout;\n   method    Bit#(1)     rd_wr_done;\n   method    Action      di(Bit#(32) i);\n   method    Action      dwaddr(Bit#(10) i);\n   method    Action      byte_en(Bit#(4) i);\n   method    Action      wr_en(Bit#(1) i);\n   method    Action      rd_en(Bit#(1) i);\n   method    Action      wr_readonly(Bit#(1) i);\n   method    Bit#(8)     bus_number;\n   method    Bit#(5)     device_number;\n   method    Bit#(3)     function_number;\n   method    Bit#(16)    status;\n   method    Bit#(16)    command;\n   method    Bit#(16)    dstatus;\n   method    Bit#(16)    dcommand;\n   method    Bit#(16)    dcommand2;\n   method    Bit#(16)    lstatus;\n   method    Bit#(16)    lcommand;\n   method    Bit#(1)     aer_ecrc_gen_en;\n   method    Bit#(1)     aer_ecrc_check_en;\n   method    Bit#(3)     pcie_link_state;\n   method    Action      trn_pending(Bit#(1) i);\n   method    Action      dsn(Bit#(64) i);\n   method    Bit#(1)     pmcsr_pme_en;\n   method    Bit#(1)     pmcsr_pme_status;\n   method    Bit#(2)     pmcsr_powerstate;\n   method    Action      pm_halt_aspm_l0s(Bit#(1) i);\n   method    Action      pm_halt_aspm_l1(Bit#(1) i);\n   method    Action      pm_force_state(Bit#(2) i);\n   method    Action      pm_force_state_en(Bit#(1) i);\n   method    Bit#(1)     received_func_lvl_rst;\n   method    Bit#(7)     vc_tcvc_map;\n   method    Bit#(1)     to_turnoff;\n   method    Action      turnoff_ok(Bit#(1) i);\n   method    Action      pm_wake(Bit#(1) i);\nendinterface\n\n(* always_ready, always_enabled *)\ninterface PCIE_INT_V7;\n   method    Action      req(Bit#(1) i);\n   method    Bit#(1)     rdy;\n   method    Action      assrt(Bit#(1) i);\n   method    Action      di(Bit#(8) i);\n   method    Bit#(8)     dout;\n   method    Bit#(3)     mmenable;\n   method    Bit#(1)     msienable;\n   method    Bit#(1)     msixenable;\n   method    Bit#(1)     msixfm;\n   method    Action      pciecap_msgnum(Bit#(5) i);\n   method    Action      stat(Bit#(1) i);\nendinterface\n\n(* always_ready, always_enabled *)\ninterface PCIE_ERR_V7;\n   method    Action      ecrc(Bit#(1) i);\n   method    Action      ur(Bit#(1) i);\n   method    Action      cpl_timeout(Bit#(1) i);\n   method    Action      cpl_unexpect(Bit#(1) i);\n   method    Action      cpl_abort(Bit#(1) i);\n   method    Action      posted(Bit#(1) i);\n   method    Action      cor(Bit#(1) i);\n   method    Action      atomic_egress_blocked(Bit#(1) i);\n   method    Action      internal_cor(Bit#(1) i);\n   method    Action      internal_uncor(Bit#(1) i);\n   method    Action      malformed(Bit#(1) i);\n   method    Action      mc_blocked(Bit#(1) i);\n   method    Action      poisoned(Bit#(1) i);\n   method    Action      no_recovery(Bit#(1) i);\n   method    Action      tlp_cpl_header(Bit#(48) i);\n   method    Bit#(1)     cpl_rdy;\n   method    Action      locked(Bit#(1) i);\n   method    Action      aer_headerlog(Bit#(128) i);\n   method    Bit#(1)     aer_headerlog_set;\n   method    Action      aer_interrupt_msgnum(Bit#(5) i);\n   method    Action      acs(Bit#(1) i);\nendinterface\n\n////////////////////////////////////////////////////////////////////////////////\n////////////////////////////////////////////////////////////////////////////////\n///\n/// Implementation: original PCIE (pre-PCIE3)\n///\n////////////////////////////////////////////////////////////////////////////////\n////////////////////////////////////////////////////////////////////////////////\nimport \"BVI\" xilinx_v7_pcie_wrapper =\nmodule vMkVirtex7PCIExpress#(PCIEParams params)(PCIE_V7#(lanes))\n   provisos( Add#(1, z, lanes));\n\n   let sys_reset <- invertCurrentReset;\n\n   default_clock clk(sys_clk); // 100 MHz refclk\n   default_reset rstn(sys_reset) = sys_reset;\n\n   parameter PL_FAST_TRAIN = (params.fast_train_sim_only) ? \"TRUE\" : \"FALSE\";\n   parameter PCIE_EXT_CLK  = \"TRUE\";\n\n   interface PCIE_EXP pcie;\n      method                            rxp(pci_exp_rxp) enable((*inhigh*)en0)                              reset_by(no_reset);\n      method                            rxn(pci_exp_rxn) enable((*inhigh*)en1)                              reset_by(no_reset);\n      method pci_exp_txp                txp                                                                 reset_by(no_reset);\n      method pci_exp_txn                txn                                                                 reset_by(no_reset);\n   endinterface\n\n   interface PCIE_TRN_V7 trn;\n      output_clock                      clk(user_clk_out);\n      output_reset                      reset(user_reset_out);\n      method user_lnk_up                lnk_up                                                              clocked_by(no_clock) reset_by(no_reset); /* semi-static */\n      method fc_ph                      fc_ph                                                               clocked_by(trn_clk)  reset_by(no_reset);\n      method fc_pd                      fc_pd                                                               clocked_by(trn_clk)  reset_by(no_reset);\n      method fc_nph                     fc_nph                                                              clocked_by(trn_clk)  reset_by(no_reset);\n      method fc_npd                     fc_npd                                                              clocked_by(trn_clk)  reset_by(no_reset);\n      method fc_cplh                    fc_cplh                                                             clocked_by(trn_clk)  reset_by(no_reset);\n      method fc_cpld                    fc_cpld                                                             clocked_by(trn_clk)  reset_by(no_reset);\n      method                            fc_sel(fc_sel)                               enable((*inhigh*)en01) clocked_by(trn_clk)  reset_by(no_reset);\n   endinterface\n\n   interface PCIE_AXI_TX_V7 axi_tx;\n      method                            tlast(s_axis_tx_tlast)                       enable((*inhigh*)en02) clocked_by(trn_clk)  reset_by(no_reset);\n      method                            tdata(s_axis_tx_tdata)                       enable((*inhigh*)en03) clocked_by(trn_clk)  reset_by(no_reset);\n      method                            tkeep(s_axis_tx_tkeep)                       enable((*inhigh*)en04) clocked_by(trn_clk)  reset_by(no_reset);\n      method                            tvalid(s_axis_tx_tvalid)                     enable((*inhigh*)en05) clocked_by(trn_clk)  reset_by(no_reset);\n      method s_axis_tx_tready           tready                                                              clocked_by(trn_clk)  reset_by(no_reset);\n      method                            tuser(s_axis_tx_tuser)                       enable((*inhigh*)en06) clocked_by(trn_clk)  reset_by(no_reset);\n      method tx_buf_av                  tbuf_av                                                             clocked_by(trn_clk)  reset_by(no_reset);\n      method tx_err_drop                terr_drop                                                           clocked_by(trn_clk)  reset_by(no_reset);\n      method tx_cfg_req                 tcfg_req                                                            clocked_by(trn_clk)  reset_by(no_reset);\n      method                            tcfg_gnt(tx_cfg_gnt)                         enable((*inhigh*)en07) clocked_by(trn_clk)  reset_by(no_reset);\n   endinterface\n\n   interface PCIE_AXI_RX_V7 axi_rx;\n      method m_axis_rx_tlast            rlast                                                               clocked_by(trn_clk)  reset_by(no_reset);\n      method m_axis_rx_tdata            rdata                                                               clocked_by(trn_clk)  reset_by(no_reset);\n      method m_axis_rx_tkeep            rkeep                                                               clocked_by(trn_clk)  reset_by(no_reset);\n      method m_axis_rx_tuser            ruser                                                               clocked_by(trn_clk)  reset_by(no_reset);\n      method m_axis_rx_tvalid           rvalid                                                              clocked_by(trn_clk)  reset_by(no_reset);\n      method                            rready(m_axis_rx_tready)                     enable((*inhigh*)en08) clocked_by(trn_clk)  reset_by(no_reset);\n      method                            rnp_ok(rx_np_ok)                             enable((*inhigh*)en09) clocked_by(trn_clk)  reset_by(no_reset);\n      method                            rnp_req(rx_np_req)                           enable((*inhigh*)en10) clocked_by(trn_clk)  reset_by(no_reset);\n   endinterface\n\n   interface PCIE_PL_V7 pl;\n      method pl_initial_link_width      initial_link_width                                                       clocked_by(trn_clk)  reset_by(no_reset);\n      method pl_phy_lnk_up              phy_link_up                                                              clocked_by(trn_clk)  reset_by(no_reset);\n      method pl_lane_reversal_mode      lane_reversal_mode                                                       clocked_by(trn_clk)  reset_by(no_reset);\n      method pl_link_gen2_cap           link_gen2_capable                                                        clocked_by(trn_clk)  reset_by(no_reset);\n      method pl_link_partner_gen2_supported link_partner_gen2_supported                                          clocked_by(trn_clk)  reset_by(no_reset);\n      method pl_link_upcfg_cap          link_upcfg_capable                                                       clocked_by(trn_clk)  reset_by(no_reset);\n      method pl_sel_lnk_rate            sel_link_rate                                                            clocked_by(trn_clk)  reset_by(no_reset);\n      method pl_sel_lnk_width           sel_link_width                                                           clocked_by(trn_clk)  reset_by(no_reset);\n      method pl_ltssm_state             ltssm_state                                                              clocked_by(trn_clk)  reset_by(no_reset);\n      method pl_rx_pm_state             rx_pm_state                                                              clocked_by(trn_clk)  reset_by(no_reset);\n      method pl_tx_pm_state             tx_pm_state                                                              clocked_by(trn_clk)  reset_by(no_reset);\n      method                            directed_link_auton(pl_directed_link_auton)       enable((*inhigh*)en13) clocked_by(trn_clk)  reset_by(no_reset);\n      method                            directed_link_change(pl_directed_link_change)     enable((*inhigh*)en14) clocked_by(trn_clk)  reset_by(no_reset);\n      method                            directed_link_speed(pl_directed_link_speed)       enable((*inhigh*)en15) clocked_by(trn_clk)  reset_by(no_reset);\n      method                            directed_link_width(pl_directed_link_width)       enable((*inhigh*)en16) clocked_by(trn_clk)  reset_by(no_reset);\n      method pl_directed_change_done    directed_change_done                                                     clocked_by(trn_clk)  reset_by(no_reset);\n      method                            upstream_prefer_deemph(pl_upstream_prefer_deemph) enable((*inhigh*)en17) clocked_by(trn_clk)  reset_by(no_reset);\n      method pl_received_hot_rst        received_hot_rst                                                         clocked_by(trn_clk)  reset_by(no_reset);\n   endinterface\n\n   interface PCIE_CFG_V7 cfg;\n      method cfg_mgmt_do                dout                                                                     clocked_by(trn_clk) reset_by(no_reset);\n      method cfg_mgmt_rd_wr_done        rd_wr_done                                                               clocked_by(trn_clk) reset_by(no_reset);\n      method                            di(cfg_mgmt_di)                                   enable((*inhigh*)en18) clocked_by(trn_clk) reset_by(no_reset);\n      method                            dwaddr(cfg_mgmt_dwaddr)                           enable((*inhigh*)en19) clocked_by(trn_clk) reset_by(no_reset);\n      method                            byte_en(cfg_mgmt_byte_en)                         enable((*inhigh*)en20) clocked_by(trn_clk) reset_by(no_reset);\n      method                            wr_en(cfg_mgmt_wr_en)                             enable((*inhigh*)en21) clocked_by(trn_clk) reset_by(no_reset);\n      method                            rd_en(cfg_mgmt_rd_en)                             enable((*inhigh*)en22) clocked_by(trn_clk) reset_by(no_reset);\n      method                            wr_readonly(cfg_mgmt_wr_readonly)                 enable((*inhigh*)en23) clocked_by(trn_clk) reset_by(no_reset);\n      method cfg_bus_number             bus_number                                                               clocked_by(no_clock) reset_by(no_reset);\n      method cfg_device_number          device_number                                                            clocked_by(no_clock) reset_by(no_reset);\n      method cfg_function_number        function_number                                                          clocked_by(no_clock) reset_by(no_reset);\n      method cfg_status                 status                                                                   clocked_by(trn_clk) reset_by(no_reset);\n      method cfg_command                command                                                                  clocked_by(trn_clk) reset_by(no_reset);\n      method cfg_dstatus                dstatus                                                                  clocked_by(trn_clk) reset_by(no_reset);\n      method cfg_dcommand               dcommand                                                                 clocked_by(trn_clk) reset_by(no_reset);\n      method cfg_dcommand2              dcommand2                                                                clocked_by(trn_clk) reset_by(no_reset);\n      method cfg_lstatus                lstatus                                                                  clocked_by(trn_clk) reset_by(no_reset);\n      method cfg_lcommand               lcommand                                                                 clocked_by(trn_clk) reset_by(no_reset);\n      method cfg_aer_ecrc_gen_en        aer_ecrc_gen_en                                                          clocked_by(trn_clk) reset_by(no_reset);\n      method cfg_aer_ecrc_check_en      aer_ecrc_check_en                                                        clocked_by(trn_clk) reset_by(no_reset);\n      method cfg_pcie_link_state        pcie_link_state                                                          clocked_by(trn_clk) reset_by(no_reset);\n      method                            trn_pending(cfg_trn_pending)                      enable((*inhigh*)en24) clocked_by(trn_clk) reset_by(no_reset);\n      method                            dsn(cfg_dsn)                                      enable((*inhigh*)en25) clocked_by(trn_clk) reset_by(no_reset);\n      method cfg_pmcsr_pme_en           pmcsr_pme_en                                                             clocked_by(trn_clk) reset_by(no_reset);\n      method cfg_pmcsr_pme_status       pmcsr_pme_status                                                         clocked_by(trn_clk) reset_by(no_reset);\n      method cfg_pmcsr_powerstate       pmcsr_powerstate                                                         clocked_by(trn_clk) reset_by(no_reset);\n      method                            pm_halt_aspm_l0s(cfg_pm_halt_aspm_l0s)            enable((*inhigh*)en26) clocked_by(trn_clk) reset_by(no_reset);\n      method                            pm_halt_aspm_l1(cfg_pm_halt_aspm_l1)              enable((*inhigh*)en27) clocked_by(trn_clk) reset_by(no_reset);\n      method                            pm_force_state(cfg_pm_force_state)                enable((*inhigh*)en28) clocked_by(trn_clk) reset_by(no_reset);\n      method                            pm_force_state_en(cfg_pm_force_state_en)          enable((*inhigh*)en29) clocked_by(trn_clk) reset_by(no_reset);\n      method cfg_received_func_lvl_rst  received_func_lvl_rst                                                    clocked_by(trn_clk) reset_by(no_reset);\n      method cfg_vc_tcvc_map            vc_tcvc_map                                                              clocked_by(trn_clk) reset_by(no_reset);\n      method cfg_to_turnoff             to_turnoff                                                               clocked_by(trn_clk) reset_by(no_reset);\n      method                            turnoff_ok(cfg_turnoff_ok)                        enable((*inhigh*)en30) clocked_by(trn_clk) reset_by(no_reset);\n      method                            pm_wake(cfg_pm_wake)                              enable((*inhigh*)en31) clocked_by(trn_clk) reset_by(no_reset);\n   endinterface\n\n   interface PCIE_INT_V7 cfg_interrupt;\n      method                            req(cfg_interrupt)                                enable((*inhigh*)en32) clocked_by(trn_clk) reset_by(no_reset);\n      method cfg_interrupt_rdy          rdy                                                                      clocked_by(trn_clk) reset_by(no_reset);\n      method                            assrt(cfg_interrupt_assert)                       enable((*inhigh*)en33) clocked_by(trn_clk) reset_by(no_reset);\n      method                            di(cfg_interrupt_di)                              enable((*inhigh*)en34) clocked_by(trn_clk) reset_by(no_reset);\n      method cfg_interrupt_do           dout                                                                     clocked_by(trn_clk) reset_by(no_reset);\n      method cfg_interrupt_mmenable     mmenable                                                                 clocked_by(trn_clk) reset_by(no_reset);\n      method cfg_interrupt_msienable    msienable                                                                clocked_by(trn_clk) reset_by(no_reset);\n      method cfg_interrupt_msixenable   msixenable                                                               clocked_by(trn_clk) reset_by(no_reset);\n      method cfg_interrupt_msixfm       msixfm                                                                   clocked_by(trn_clk) reset_by(no_reset);\n      method                            pciecap_msgnum(cfg_pciecap_interrupt_msgnum)      enable((*inhigh*)en35) clocked_by(trn_clk) reset_by(no_reset);\n      method                            stat(cfg_interrupt_stat)                          enable((*inhigh*)en36) clocked_by(trn_clk) reset_by(no_reset);\n   endinterface\n\n   interface PCIE_ERR_V7 cfg_err;\n      method                            ecrc(cfg_err_ecrc)                           \t  enable((*inhigh*)en37) clocked_by(trn_clk) reset_by(no_reset);\n      method                            ur(cfg_err_ur)                               \t  enable((*inhigh*)en38) clocked_by(trn_clk) reset_by(no_reset);\n      method                            cpl_timeout(cfg_err_cpl_timeout)             \t  enable((*inhigh*)en39) clocked_by(trn_clk) reset_by(no_reset);\n      method                            cpl_unexpect(cfg_err_cpl_unexpect)           \t  enable((*inhigh*)en40) clocked_by(trn_clk) reset_by(no_reset);\n      method                            cpl_abort(cfg_err_cpl_abort)                 \t  enable((*inhigh*)en41) clocked_by(trn_clk) reset_by(no_reset);\n      method                            posted(cfg_err_posted)                       \t  enable((*inhigh*)en42) clocked_by(trn_clk) reset_by(no_reset);\n      method                            cor(cfg_err_cor)                             \t  enable((*inhigh*)en43) clocked_by(trn_clk) reset_by(no_reset);\n      method          \t\t\tatomic_egress_blocked(cfg_err_atomic_egress_blocked) enable((*inhigh*)en44) clocked_by(trn_clk) reset_by(no_reset);\n      method          \t\t\tinternal_cor(cfg_err_internal_cor)           \t  enable((*inhigh*)en45) clocked_by(trn_clk) reset_by(no_reset);\n      method          \t\t\tinternal_uncor(cfg_err_internal_uncor)       \t  enable((*inhigh*)en46) clocked_by(trn_clk) reset_by(no_reset);\n      method          \t\t\tmalformed(cfg_err_malformed)                 \t  enable((*inhigh*)en47) clocked_by(trn_clk) reset_by(no_reset);\n      method          \t\t\tmc_blocked(cfg_err_mc_blocked)               \t  enable((*inhigh*)en48) clocked_by(trn_clk) reset_by(no_reset);\n      method          \t\t\tpoisoned(cfg_err_poisoned)                   \t  enable((*inhigh*)en49) clocked_by(trn_clk) reset_by(no_reset);\n      method          \t\t\tno_recovery(cfg_err_norecovery)             \t  enable((*inhigh*)en50) clocked_by(trn_clk) reset_by(no_reset);\n      method                            tlp_cpl_header(cfg_err_tlp_cpl_header)       \t  enable((*inhigh*)en51) clocked_by(trn_clk) reset_by(no_reset);\n      method cfg_err_cpl_rdy            cpl_rdy                                      \t                         clocked_by(trn_clk) reset_by(no_reset);\n      method                            locked(cfg_err_locked)                       \t  enable((*inhigh*)en52) clocked_by(trn_clk) reset_by(no_reset);\n      method         \t\t\taer_headerlog(cfg_err_aer_headerlog)         \t  enable((*inhigh*)en53) clocked_by(trn_clk) reset_by(no_reset);\n      method cfg_err_aer_headerlog_set  aer_headerlog_set                                                        clocked_by(trn_clk) reset_by(no_reset);\n      method         \t\t\taer_interrupt_msgnum(cfg_aer_interrupt_msgnum)    enable((*inhigh*)en54) clocked_by(trn_clk) reset_by(no_reset);\n      method         \t\t\tacs(cfg_err_acs)                                  enable((*inhigh*)en55) clocked_by(trn_clk) reset_by(no_reset);\n   endinterface\n\n   schedule (trn_lnk_up, trn_fc_ph, trn_fc_pd, trn_fc_nph, trn_fc_npd, trn_fc_cplh, trn_fc_cpld, trn_fc_sel, axi_tx_tlast,\n\t     axi_tx_tdata, axi_tx_tkeep, axi_tx_tvalid, axi_tx_tready, axi_tx_tuser, axi_tx_tbuf_av, axi_tx_terr_drop,\n\t     axi_tx_tcfg_req, axi_tx_tcfg_gnt, axi_rx_rlast, axi_rx_rdata, axi_rx_rkeep, axi_rx_ruser, axi_rx_rvalid,\n\t     axi_rx_rready, axi_rx_rnp_ok, axi_rx_rnp_req, pl_initial_link_width, pl_phy_link_up, pl_lane_reversal_mode,\n\t     pl_link_gen2_capable, pl_link_partner_gen2_supported, pl_link_upcfg_capable, pl_sel_link_rate, pl_sel_link_width,\n\t     pl_ltssm_state, pl_rx_pm_state, pl_tx_pm_state, pl_directed_link_auton, pl_directed_link_change,\n\t     pl_directed_link_speed, pl_directed_link_width, pl_directed_change_done, pl_upstream_prefer_deemph,\n\t     pl_received_hot_rst, cfg_dout, cfg_rd_wr_done, cfg_di, cfg_dwaddr, cfg_byte_en, cfg_wr_en, cfg_rd_en,\n\t     cfg_wr_readonly, cfg_bus_number, cfg_device_number, cfg_function_number, cfg_status, cfg_command, cfg_dstatus,\n\t     cfg_dcommand, cfg_dcommand2, cfg_lstatus, cfg_lcommand, cfg_aer_ecrc_gen_en, cfg_aer_ecrc_check_en,\n\t     cfg_pcie_link_state, cfg_trn_pending, cfg_dsn, cfg_pmcsr_pme_en, cfg_pmcsr_pme_status, cfg_pmcsr_powerstate,\n\t     cfg_pm_halt_aspm_l0s, cfg_pm_halt_aspm_l1, cfg_pm_force_state, cfg_pm_force_state_en, cfg_received_func_lvl_rst,\n\t     cfg_vc_tcvc_map, cfg_to_turnoff, cfg_turnoff_ok, cfg_pm_wake,\n\t     cfg_interrupt_req, cfg_interrupt_rdy,\n\t     cfg_interrupt_assrt, cfg_interrupt_di, cfg_interrupt_dout, cfg_interrupt_mmenable, cfg_interrupt_msienable,\n\t     cfg_interrupt_msixenable, cfg_interrupt_msixfm, cfg_interrupt_pciecap_msgnum, cfg_interrupt_stat,\n\t     cfg_err_ecrc, cfg_err_ur, cfg_err_cpl_timeout, cfg_err_cpl_unexpect, cfg_err_cpl_abort, cfg_err_posted,\n\t     cfg_err_cor, cfg_err_atomic_egress_blocked, cfg_err_internal_cor, cfg_err_internal_uncor, cfg_err_malformed,\n\t     cfg_err_mc_blocked, cfg_err_poisoned, cfg_err_no_recovery, cfg_err_tlp_cpl_header, cfg_err_cpl_rdy, cfg_err_locked,\n\t     cfg_err_aer_headerlog, cfg_err_aer_headerlog_set, cfg_err_aer_interrupt_msgnum, cfg_err_acs,\n\t     pcie_txp, pcie_txn, pcie_rxp, pcie_rxn\n\t     ) CF\n            (trn_lnk_up, trn_fc_ph, trn_fc_pd, trn_fc_nph, trn_fc_npd, trn_fc_cplh, trn_fc_cpld, trn_fc_sel, axi_tx_tlast,\n\t     axi_tx_tdata, axi_tx_tkeep, axi_tx_tvalid, axi_tx_tready, axi_tx_tuser, axi_tx_tbuf_av, axi_tx_terr_drop,\n\t     axi_tx_tcfg_req, axi_tx_tcfg_gnt, axi_rx_rlast, axi_rx_rdata, axi_rx_rkeep, axi_rx_ruser, axi_rx_rvalid,\n\t     axi_rx_rready, axi_rx_rnp_ok, axi_rx_rnp_req, pl_initial_link_width, pl_phy_link_up, pl_lane_reversal_mode,\n\t     pl_link_gen2_capable, pl_link_partner_gen2_supported, pl_link_upcfg_capable, pl_sel_link_rate, pl_sel_link_width,\n\t     pl_ltssm_state, pl_rx_pm_state, pl_tx_pm_state, pl_directed_link_auton, pl_directed_link_change,\n\t     pl_directed_link_speed, pl_directed_link_width, pl_directed_change_done, pl_upstream_prefer_deemph,\n\t     pl_received_hot_rst, cfg_dout, cfg_rd_wr_done, cfg_di, cfg_dwaddr, cfg_byte_en, cfg_wr_en, cfg_rd_en,\n\t     cfg_wr_readonly, cfg_bus_number, cfg_device_number, cfg_function_number, cfg_status, cfg_command, cfg_dstatus,\n\t     cfg_dcommand, cfg_dcommand2, cfg_lstatus, cfg_lcommand, cfg_aer_ecrc_gen_en, cfg_aer_ecrc_check_en,\n\t     cfg_pcie_link_state, cfg_trn_pending, cfg_dsn, cfg_pmcsr_pme_en, cfg_pmcsr_pme_status, cfg_pmcsr_powerstate,\n\t     cfg_pm_halt_aspm_l0s, cfg_pm_halt_aspm_l1, cfg_pm_force_state, cfg_pm_force_state_en, cfg_received_func_lvl_rst,\n\t     cfg_vc_tcvc_map, cfg_to_turnoff, cfg_turnoff_ok, cfg_pm_wake,\n\t     cfg_interrupt_req, cfg_interrupt_rdy,\n\t     cfg_interrupt_assrt, cfg_interrupt_di, cfg_interrupt_dout, cfg_interrupt_mmenable, cfg_interrupt_msienable,\n\t     cfg_interrupt_msixenable, cfg_interrupt_msixfm, cfg_interrupt_pciecap_msgnum, cfg_interrupt_stat,\n\t     cfg_err_ecrc, cfg_err_ur, cfg_err_cpl_timeout, cfg_err_cpl_unexpect, cfg_err_cpl_abort, cfg_err_posted,\n\t     cfg_err_cor, cfg_err_atomic_egress_blocked, cfg_err_internal_cor, cfg_err_internal_uncor, cfg_err_malformed,\n\t     cfg_err_mc_blocked, cfg_err_poisoned, cfg_err_no_recovery, cfg_err_tlp_cpl_header, cfg_err_cpl_rdy, cfg_err_locked,\n\t     cfg_err_aer_headerlog, cfg_err_aer_headerlog_set, cfg_err_aer_interrupt_msgnum, cfg_err_acs,\n\t     pcie_txp, pcie_txn, pcie_rxp, pcie_rxn\n             );\n\nendmodule: vMkVirtex7PCIExpress\n\n////////////////////////////////////////////////////////////////////////////////\n/// Interfaces original PCIE (pre-PCIE3) TRN for bridge\n////////////////////////////////////////////////////////////////////////////////\ninterface PCIE_TRN_COMMON_V7;\n   interface Clock       clk;\n   interface Clock       clk2;\n   interface Reset       reset_n;\n   method    Bool        link_up;\nendinterface\n\ninterface PCIE_TRN_XMIT_V7;\n   method    Action      xmit(TLPData#(8) data);\n   method    Action      discontinue(Bool i);\n   method    Action      ecrc_generate(Bool i);\n   method    Action      error_forward(Bool i);\n   method    Action      cut_through_mode(Bool i);\n   method    Bool        dropped;\n   method    Bit#(6)     buffers_available;\n   method    Bool        configuration_completion_request;\n   method    Action      configuration_completion_grant(Bool i);\nendinterface\n\ninterface PCIE_TRN_RECV_V7;\n   method    ActionValue#(Tuple3#(Bool, Bool, TLPData#(8))) recv();\n   method    Action      non_posted_ok(Bool i);\n   method    Action      non_posted_req(Bool i);\nendinterface\n\ninterface PCIExpressV7#(numeric type lanes);\n   interface PCIE_EXP#(lanes)   pcie;\n   interface PCIE_TRN_COMMON_V7 trn;\n   interface PCIE_TRN_XMIT_V7   trn_tx;\n   interface PCIE_TRN_RECV_V7   trn_rx;\n   interface PCIE_CFG_V7        cfg;\n   interface PCIE_INT_V7        cfg_interrupt;\n   interface PCIE_ERR_V7        cfg_err;\n   interface PCIE_PL_V7         pl;\n   interface XilinxClkServer    clks;\n   interface Clock              scemi_clk;\nendinterface\n\ninterface PCIExpressNoClkV7#(numeric type lanes);\n   interface PCIE_EXP#(lanes)   pcie;\n   interface PCIE_TRN_COMMON_V7 trn;\n   interface PCIE_TRN_XMIT_V7   trn_tx;\n   interface PCIE_TRN_RECV_V7   trn_rx;\n   interface PCIE_CFG_V7        cfg;\n   interface PCIE_INT_V7        cfg_interrupt;\n   interface PCIE_ERR_V7        cfg_err;\n   interface PCIE_PL_V7         pl;\nendinterface\n\n////////////////////////////////////////////////////////////////////////////////\n/// For original PCIE (pre-PCIE3)\n/// Typeclass to select vMkVirtex7PCIExpress() for 1, 4, 8 lanes\n////////////////////////////////////////////////////////////////////////////////\n\ntypeclass SelectVirtex7PCIE#(numeric type lanes);\n   module selectVirtex7PCIE(PCIEParams params, PCIE_V7#(lanes) ifc);\nendtypeclass\n\ninstance SelectVirtex7PCIE#(8);\n   module selectVirtex7PCIE(PCIEParams params, PCIE_V7#(8) ifc);\n      let _ifc <- vMkVirtex7PCIExpress(params);\n      return _ifc;\n   endmodule\nendinstance\n\ninstance SelectVirtex7PCIE#(4);\n   module selectVirtex7PCIE(PCIEParams params, PCIE_V7#(4) ifc);\n      let _ifc <- vMkVirtex7PCIExpress(params);\n      return _ifc;\n   endmodule\nendinstance\n\ninstance SelectVirtex7PCIE#(1);\n   module selectVirtex7PCIE(PCIEParams params, PCIE_V7#(1) ifc);\n      let _ifc <- vMkVirtex7PCIExpress(params);\n      return _ifc;\n   endmodule\nendinstance\n\n////////////////////////////////////////////////////////////////\n// The BSV PCIE endpoint  (original pre-PCIE3 version)\n////////////////////////////////////////////////////////////////\n\nmodule mkPCIExpressEndpointV7#(PCIEParams params)(PCIExpressV7#(lanes))\n   provisos(Add#(1, z, lanes), SelectVirtex7PCIE#(lanes));\n\n   ////////////////////////////////////////////////////////////////////////////////\n   /// Design Elements\n   ////////////////////////////////////////////////////////////////////////////////\n   PCIE_V7#(lanes)                           pcie_ep             <- selectVirtex7PCIE(params);\n\n   Clock                                     user_clk             = pcie_ep.trn.clk;\n   Reset                                     user_reset_n        <- mkResetInverter(pcie_ep.trn.reset);\n\n   Wire#(Bit#(1))                            wDiscontinue        <- mkDWire(0, clocked_by user_clk, reset_by noReset);\n   Wire#(Bit#(1))                            wEcrcGen            <- mkDWire(0, clocked_by user_clk, reset_by noReset);\n   Wire#(Bit#(1))                            wErrFwd             <- mkDWire(0, clocked_by user_clk, reset_by noReset);\n   Wire#(Bit#(1))                            wCutThrough         <- mkDWire(0, clocked_by user_clk, reset_by noReset);\n\n   Wire#(Bool)                               wAxiTxValid         <- mkDWire(False, clocked_by user_clk, reset_by noReset);\n   Wire#(Bool)                               wAxiTxLast          <- mkDWire(False, clocked_by user_clk, reset_by noReset);\n   Wire#(Bit#(64))                           wAxiTxData          <- mkDWire(0, clocked_by user_clk, reset_by noReset);\n   Wire#(Bit#(8))                            wAxiTxKeep          <- mkDWire(0, clocked_by user_clk, reset_by noReset);\n   FIFO#(AxiTx)                              fAxiTx              <- mkBypassFIFO(clocked_by user_clk, reset_by noReset);\n\n   FIFOF#(AxiRx)                             fAxiRx              <- mkBypassFIFOF(clocked_by user_clk, reset_by noReset);\n   Wire#(Bool)                               wAxiRxReady         <- mkDWire(False, clocked_by user_clk, reset_by noReset);\n\n   ClockGenerator7Params                     clk_params           = defaultValue;\n   clk_params.clkin1_period    = 4.000;\n   clk_params.clkin_buffer     = False;\n   clk_params.clkfbout_mult_f  = 4.000;\n   clk_params.clkout0_divide_f = 8.000;\n   ClockGenerator7                           clkgen              <- mkClockGenerator7(clk_params, clocked_by user_clk, reset_by user_reset_n);\n   Clock                                     user_clk_half        = clkgen.clkout0;\n   Reset                                     user_reset_half     <- mkAsyncReset(1, user_reset_n, user_clk_half);\n\n   XilinxClockParams                         scemiclk_params      = defaultValue;\n   scemiclk_params.e_type           = E2;\n   scemiclk_params.clkin1_period    = 8.000;\n   scemiclk_params.clkfbout_mult_f  = 8.000;\n   scemiclk_params.clkout0_divide_f = params.clock_period;\n   XilinxClockController                     scemi_clkgen        <- mkXilinxClockController(scemiclk_params, user_clk_half, clocked_by user_clk_half, reset_by user_reset_half);\n\n   ////////////////////////////////////////////////////////////////////////////////\n   /// Rules\n   ////////////////////////////////////////////////////////////////////////////////\n   (* fire_when_enabled, no_implicit_conditions *)\n   rule others;\n      pcie_ep.trn.fc_sel(RECEIVE_BUFFER_AVAILABLE_SPACE);\n   endrule\n\n   (* fire_when_enabled, no_implicit_conditions *)\n   rule drive_axi_tx;\n      pcie_ep.axi_tx.tuser({ wDiscontinue, wCutThrough, wErrFwd, wEcrcGen });\n      pcie_ep.axi_tx.tvalid(wAxiTxValid);\n      pcie_ep.axi_tx.tlast(wAxiTxLast);\n      pcie_ep.axi_tx.tdata(wAxiTxData);\n      pcie_ep.axi_tx.tkeep(wAxiTxKeep);\n   endrule\n\n   (* fire_when_enabled *)\n   rule drive_axi_tx_info if (pcie_ep.axi_tx.tready);\n      let info <- toGet(fAxiTx).get;\n      wAxiTxValid <= True;\n      wAxiTxLast  <= info.last;\n      wAxiTxData  <= info.data;\n      wAxiTxKeep  <= info.keep;\n   endrule\n\n   (* fire_when_enabled, no_implicit_conditions *)\n   rule drive_axi_rx_ready;\n      pcie_ep.axi_rx.rready(fAxiRx.notFull);\n   endrule\n\n   (* fire_when_enabled *)\n   rule sink_axi_rx if (pcie_ep.axi_rx.rvalid);\n      let info = AxiRx {\n\t user:    pcie_ep.axi_rx.ruser,\n\t last:    pcie_ep.axi_rx.rlast,\n\t keep:    pcie_ep.axi_rx.rkeep,\n\t data:    pcie_ep.axi_rx.rdata\n\t };\n      fAxiRx.enq(info);\n   endrule\n\n   ////////////////////////////////////////////////////////////////////////////////\n   /// Interface Connections / Methods\n   ////////////////////////////////////////////////////////////////////////////////\n   interface pcie = pcie_ep.pcie;\n\n   interface PCIE_TRN_COMMON_V7 trn;\n      interface clk     = user_clk;\n      interface clk2    = user_clk_half;\n      interface reset_n = user_reset_n;\n      method    link_up = pcie_ep.trn.lnk_up;\n   endinterface\n\n   interface PCIE_TRN_XMIT_V7 trn_tx;\n      method Action xmit(data);\n\t fAxiTx.enq(AxiTx { last: data.eof, keep: dwordSwap64BE(data.be), data: dwordSwap64(data.data) });\n      endmethod\n      method discontinue(i)                    = wDiscontinue._write(pack(i));\n      method ecrc_generate(i)          \t       = wEcrcGen._write(pack(i));\n      method error_forward(i)          \t       = wErrFwd._write(pack(i));\n      method cut_through_mode(i)       \t       = wCutThrough._write(pack(i));\n      method dropped                   \t       = pcie_ep.axi_tx.terr_drop;\n      method buffers_available         \t       = pcie_ep.axi_tx.tbuf_av;\n      method configuration_completion_request  = pcie_ep.axi_tx.tcfg_req;\n      method configuration_completion_grant(i) = pcie_ep.axi_tx.tcfg_gnt(i);\n   endinterface\n\n   interface PCIE_TRN_RECV_V7 trn_rx;\n      method ActionValue#(Tuple3#(Bool, Bool, TLPData#(8))) recv();\n\t let info <- toGet(fAxiRx).get;\n\t TLPData#(8) retval = defaultValue;\n\t retval.sof  = (info.user[14] == 1);\n\t retval.eof  = info.last;\n\t retval.hit  = info.user[8:2];\n\t retval.be   = dwordSwap64BE(info.keep);\n\t retval.data = dwordSwap64(info.data);\n\t return tuple3(info.user[1] == 1, info.user[0] == 1, retval);\n      endmethod\n      method non_posted_ok(i)  = pcie_ep.axi_rx.rnp_ok(i);\n      method non_posted_req(i) = pcie_ep.axi_rx.rnp_req(i);\n   endinterface\n\n   interface pl = pcie_ep.pl;\n   interface cfg = pcie_ep.cfg;\n   interface cfg_interrupt = pcie_ep.cfg_interrupt;\n   interface cfg_err = pcie_ep.cfg_err;\n   interface scemi_clk = scemi_clkgen.clkout0;\n   interface XilinxClkServer clks;\n      interface Put request;\n\t method Action put(Bit#(32) x);\n\t    let request = XilinxClockRequest {\n\t       rnw:  unpack(x[31]),\n\t       addr: x[20:16],\n\t       data: x[15:0]\n\t       };\n\t    scemi_clkgen.csr.request.put(request);\n\t endmethod\n      endinterface\n      interface Get response;\n\t method ActionValue#(Bit#(32)) get;\n\t    let response <- scemi_clkgen.csr.response.get;\n\t    return cExtend(response);\n\t endmethod\n      endinterface\n   endinterface\nendmodule: mkPCIExpressEndpointV7\n\n\n// The BSV PCIE endpoint, without exported clocks  (original pre-PCIE3 version)\nmodule mkPCIExpressEndpointNoClkV7#(PCIEParams params)(PCIExpressNoClkV7#(lanes))\n   provisos(Add#(1, z, lanes), SelectVirtex7PCIE#(lanes));\n\n   ////////////////////////////////////////////////////////////////////////////////\n   /// Design Elements\n   ////////////////////////////////////////////////////////////////////////////////\n   PCIE_V7#(lanes)                           pcie_ep             <- selectVirtex7PCIE(params);\n\n   Clock                                     user_clk             = pcie_ep.trn.clk;\n   Reset                                     user_reset_n        <- mkResetInverter(pcie_ep.trn.reset);\n\n   Wire#(Bit#(1))                            wDiscontinue        <- mkDWire(0, clocked_by user_clk, reset_by noReset);\n   Wire#(Bit#(1))                            wEcrcGen            <- mkDWire(0, clocked_by user_clk, reset_by noReset);\n   Wire#(Bit#(1))                            wErrFwd             <- mkDWire(0, clocked_by user_clk, reset_by noReset);\n   Wire#(Bit#(1))                            wCutThrough         <- mkDWire(0, clocked_by user_clk, reset_by noReset);\n\n   Wire#(Bool)                               wAxiTxValid         <- mkDWire(False, clocked_by user_clk, reset_by noReset);\n   Wire#(Bool)                               wAxiTxLast          <- mkDWire(False, clocked_by user_clk, reset_by noReset);\n   Wire#(Bit#(64))                           wAxiTxData          <- mkDWire(0, clocked_by user_clk, reset_by noReset);\n   Wire#(Bit#(8))                            wAxiTxKeep          <- mkDWire(0, clocked_by user_clk, reset_by noReset);\n   FIFO#(AxiTx)                              fAxiTx              <- mkBypassFIFO(clocked_by user_clk, reset_by noReset);\n\n   FIFOF#(AxiRx)                             fAxiRx              <- mkBypassFIFOF(clocked_by user_clk, reset_by noReset);\n   Wire#(Bool)                               wAxiRxReady         <- mkDWire(False, clocked_by user_clk, reset_by noReset);\n\n   ClockGenerator7Params                     clk_params           = defaultValue;\n   clk_params.clkin1_period    = 4.000;\n   clk_params.clkin_buffer     = False;\n   clk_params.clkfbout_mult_f  = 4.000;\n   clk_params.clkout0_divide_f = 8.000;\n   ClockGenerator7                           clkgen              <- mkClockGenerator7(clk_params, clocked_by user_clk, reset_by user_reset_n);\n   Clock                                     user_clk_half        = clkgen.clkout0;\n\n   ////////////////////////////////////////////////////////////////////////////////\n   /// Rules\n   ////////////////////////////////////////////////////////////////////////////////\n   (* fire_when_enabled, no_implicit_conditions *)\n   rule others;\n      pcie_ep.trn.fc_sel(RECEIVE_BUFFER_AVAILABLE_SPACE);\n   endrule\n\n   (* fire_when_enabled, no_implicit_conditions *)\n   rule drive_axi_tx;\n      pcie_ep.axi_tx.tuser({ wDiscontinue, wCutThrough, wErrFwd, wEcrcGen });\n      pcie_ep.axi_tx.tvalid(wAxiTxValid);\n      pcie_ep.axi_tx.tlast(wAxiTxLast);\n      pcie_ep.axi_tx.tdata(wAxiTxData);\n      pcie_ep.axi_tx.tkeep(wAxiTxKeep);\n   endrule\n\n   (* fire_when_enabled *)\n   rule drive_axi_tx_info if (pcie_ep.axi_tx.tready);\n      let info <- toGet(fAxiTx).get;\n      wAxiTxValid <= True;\n      wAxiTxLast  <= info.last;\n      wAxiTxData  <= info.data;\n      wAxiTxKeep  <= info.keep;\n   endrule\n\n   (* fire_when_enabled, no_implicit_conditions *)\n   rule drive_axi_rx_ready;\n      pcie_ep.axi_rx.rready(fAxiRx.notFull);\n   endrule\n\n   (* fire_when_enabled *)\n   rule sink_axi_rx if (pcie_ep.axi_rx.rvalid);\n      let info = AxiRx {\n\t user:    pcie_ep.axi_rx.ruser,\n\t last:    pcie_ep.axi_rx.rlast,\n\t keep:    pcie_ep.axi_rx.rkeep,\n\t data:    pcie_ep.axi_rx.rdata\n\t };\n      fAxiRx.enq(info);\n   endrule\n\n   ////////////////////////////////////////////////////////////////////////////////\n   /// Interface Connections / Methods\n   ////////////////////////////////////////////////////////////////////////////////\n   interface pcie = pcie_ep.pcie;\n\n   interface PCIE_TRN_COMMON_V7 trn;\n      interface clk     = user_clk;\n      interface clk2    = user_clk_half;\n      interface reset_n = user_reset_n;\n      method    link_up = pcie_ep.trn.lnk_up;\n   endinterface\n\n   interface PCIE_TRN_XMIT_V7 trn_tx;\n      method Action xmit(data);\n\t fAxiTx.enq(AxiTx { last: data.eof, keep: dwordSwap64BE(data.be), data: dwordSwap64(data.data) });\n      endmethod\n      method discontinue(i)                    = wDiscontinue._write(pack(i));\n      method ecrc_generate(i)          \t       = wEcrcGen._write(pack(i));\n      method error_forward(i)          \t       = wErrFwd._write(pack(i));\n      method cut_through_mode(i)       \t       = wCutThrough._write(pack(i));\n      method dropped                   \t       = pcie_ep.axi_tx.terr_drop;\n      method buffers_available         \t       = pcie_ep.axi_tx.tbuf_av;\n      method configuration_completion_request  = pcie_ep.axi_tx.tcfg_req;\n      method configuration_completion_grant(i) = pcie_ep.axi_tx.tcfg_gnt(i);\n   endinterface\n\n   interface PCIE_TRN_RECV_V7 trn_rx;\n      method ActionValue#(Tuple3#(Bool, Bool, TLPData#(8))) recv();\n\t let info <- toGet(fAxiRx).get;\n\t TLPData#(8) retval = defaultValue;\n\t retval.sof  = (info.user[14] == 1);\n\t retval.eof  = info.last;\n\t retval.hit  = info.user[8:2];\n\t retval.be   = dwordSwap64BE(info.keep);\n\t retval.data = dwordSwap64(info.data);\n\t return tuple3(info.user[1] == 1, info.user[0] == 1, retval);\n      endmethod\n      method non_posted_ok(i)  = pcie_ep.axi_rx.rnp_ok(i);\n      method non_posted_req(i) = pcie_ep.axi_rx.rnp_req(i);\n   endinterface\n\n   interface pl = pcie_ep.pl;\n   interface cfg = pcie_ep.cfg;\n   interface cfg_interrupt = pcie_ep.cfg_interrupt;\n   interface cfg_err = pcie_ep.cfg_err;\nendmodule: mkPCIExpressEndpointNoClkV7\n\n////////////////////////////////////////////////////////////////////////////////\n/// Connection Instances\n////////////////////////////////////////////////////////////////////////////////\n\n// Basic TLPData#(8) connections to PCIE endpoint\ninstance Connectable#(Get#(TLPData#(8)), PCIE_TRN_XMIT_V7);\n   module mkConnection#(Get#(TLPData#(8)) g, PCIE_TRN_XMIT_V7 p)(Empty);\n      rule every;\n         p.cut_through_mode(False);\n         p.configuration_completion_grant(True);  // Core gets to choose\n         p.error_forward(False);\n\t p.ecrc_generate(False);\n\t p.discontinue(False);\n      endrule\n      rule connect;\n         let data <- g.get;\n         p.xmit(data);\n      endrule\n   endmodule\nendinstance\n\ninstance Connectable#(PCIE_TRN_XMIT_V7, Get#(TLPData#(8)));\n   module mkConnection#(PCIE_TRN_XMIT_V7 p, Get#(TLPData#(8)) g)(Empty);\n      mkConnection(g, p);\n   endmodule\nendinstance\n\ninstance Connectable#(Put#(TLPData#(8)), PCIE_TRN_RECV_V7);\n   module mkConnection#(Put#(TLPData#(8)) p, PCIE_TRN_RECV_V7 r)(Empty);\n      (* no_implicit_conditions, fire_when_enabled *)\n      rule every;\n         r.non_posted_ok(True);\n\t r.non_posted_req(True);\n      endrule\n      rule connect;\n         let data <- r.recv;\n         p.put(tpl_3(data));\n      endrule\n   endmodule\nendinstance\n\ninstance Connectable#(PCIE_TRN_RECV_V7, Put#(TLPData#(8)));\n   module mkConnection#(PCIE_TRN_RECV_V7 r, Put#(TLPData#(8)) p)(Empty);\n      mkConnection(p, r);\n   endmodule\nendinstance\n\n// Connections between TLPData#(16) and a PCIE endpoint.\n// These are all using the same clock, so the TLPData#(16) accesses\n// will not be back-to-back.\n\ninstance Connectable#(Get#(TLPData#(16)), PCIE_TRN_XMIT_V7);\n   module mkConnection#(Get#(TLPData#(16)) g, PCIE_TRN_XMIT_V7 t)(Empty);\n      FIFO#(TLPData#(8)) outFifo <- mkFIFO();\n\n      (* no_implicit_conditions, fire_when_enabled *)\n      rule every;\n         t.cut_through_mode(False);\n         t.configuration_completion_grant(True);  // True means core gets to choose\n         t.error_forward(False);\n\t t.ecrc_generate(False);\n\t t.discontinue(False);\n      endrule\n\n      rule connect;\n         let data = outFifo.first; outFifo.deq;\n         if (data.be != 0)\n            t.xmit(data);\n      endrule\n\n      Put#(TLPData#(8)) p = fifoToPut(outFifo);\n      mkConnection(g,p);\n   endmodule\nendinstance\n\ninstance Connectable#(PCIE_TRN_XMIT_V7, Get#(TLPData#(16)));\n   module mkConnection#(PCIE_TRN_XMIT_V7 p, Get#(TLPData#(16)) g)(Empty);\n      mkConnection(g, p);\n   endmodule\nendinstance\n\ninstance Connectable#(Put#(TLPData#(16)), PCIE_TRN_RECV_V7);\n   module mkConnection#(Put#(TLPData#(16)) p, PCIE_TRN_RECV_V7 r)(Empty);\n      FIFO#(TLPData#(8)) inFifo <- mkFIFO();\n\n      (* no_implicit_conditions, fire_when_enabled *)\n      rule every;\n         r.non_posted_ok(True);\n\t r.non_posted_req(True);\n      endrule\n\n      rule connect;\n         let data <- r.recv;\n         inFifo.enq(tpl_3(data));\n      endrule\n\n      Get#(TLPData#(8)) g = fifoToGet(inFifo);\n      mkConnection(g,p);\n   endmodule\nendinstance\n\ninstance Connectable#(PCIE_TRN_RECV_V7, Put#(TLPData#(16)));\n   module mkConnection#(PCIE_TRN_RECV_V7 r, Put#(TLPData#(16)) p)(Empty);\n      mkConnection(p, r);\n   endmodule\nendinstance\n\n// Connections between TLPData#(16) and a PCIE endpoint, using a gearbox\n// to match data rates between the endpoint and design clocks.\n\ninstance ConnectableWithClocks#(PCIE_TRN_XMIT_V7, Get#(TLPData#(16)));\n   module mkConnectionWithClocks#(PCIE_TRN_XMIT_V7 p, Get#(TLPData#(16)) g,\n                                  Clock fastClock, Reset fastReset,\n                                  Clock slowClock, Reset slowReset)(Empty);\n\n      ////////////////////////////////////////////////////////////////////////////////\n      /// Design Elements\n      ////////////////////////////////////////////////////////////////////////////////\n      FIFO#(TLPData#(8))                     outFifo             <- mkFIFO(clocked_by fastClock, reset_by fastReset);\n      Gearbox#(2, 1, TLPData#(8))            fifoTxData          <- mkNto1Gearbox(slowClock, slowReset, fastClock, fastReset);\n\n      ////////////////////////////////////////////////////////////////////////////////\n      /// Rules\n      ////////////////////////////////////////////////////////////////////////////////\n      (* no_implicit_conditions, fire_when_enabled *)\n      rule every;\n         p.cut_through_mode(False);\n         p.configuration_completion_grant(True);  // Means the core gets to choose\n         p.error_forward(False);\n\t p.ecrc_generate(False);\n\t p.discontinue(False);\n      endrule\n\n      rule get_data;\n         function Vector#(2, TLPData#(8)) split(TLPData#(16) in);\n            Vector#(2, TLPData#(8)) v = defaultValue;\n            v[0].sof  = in.sof;\n            v[0].eof  = (in.be[7:0] == 0) ? in.eof : False;\n            v[0].hit  = in.hit;\n            v[0].be   = in.be[15:8];\n            v[0].data = in.data[127:64];\n            v[1].sof  = False;\n            v[1].eof  = in.eof;\n            v[1].hit  = in.hit;\n            v[1].be   = in.be[7:0];\n            v[1].data = in.data[63:0];\n            return v;\n         endfunction\n\n         let data <- g.get;\n         fifoTxData.enq(split(data));\n      endrule\n\n      rule process_outgoing_packets;\n         let data = fifoTxData.first; fifoTxData.deq;\n         outFifo.enq(head(data));\n      endrule\n\n      rule send_data;\n         let data = outFifo.first; outFifo.deq;\n         // filter out TLPs with 00 byte enable\n         if (data.be != 0)\n            p.xmit(data);\n      endrule\n\n   endmodule\nendinstance\n\ninstance ConnectableWithClocks#(Get#(TLPData#(16)), PCIE_TRN_XMIT_V7);\n   module mkConnectionWithClocks#(Get#(TLPData#(16)) g, PCIE_TRN_XMIT_V7 p,\n                                  Clock fastClock, Reset fastReset,\n                                  Clock slowClock, Reset slowReset)(Empty);\n\n      mkConnectionWithClocks(p, g, fastClock, fastReset, slowClock, slowReset);\n   endmodule\nendinstance\n\ninstance ConnectableWithClocks#(Put#(TLPData#(16)), PCIE_TRN_RECV_V7);\n   module mkConnectionWithClocks#(Put#(TLPData#(16)) p, PCIE_TRN_RECV_V7 g,\n                                  Clock fastClock, Reset fastReset,\n                                  Clock slowClock, Reset slowReset)(Empty);\n\n      ////////////////////////////////////////////////////////////////////////////////\n      /// Design Elements\n      ////////////////////////////////////////////////////////////////////////////////\n      FIFO#(TLPData#(8))                        inFifo              <- mkFIFO(clocked_by fastClock, reset_by fastReset);\n      Gearbox#(1, 2, TLPData#(8))               fifoRxData          <- mk1toNGearbox(fastClock, fastReset, slowClock, slowReset);\n\n      Reg#(Bool)                                rOddBeat            <- mkRegA(False, clocked_by fastClock, reset_by fastReset);\n      Reg#(Bool)                                rSendInvalid        <- mkRegA(False, clocked_by fastClock, reset_by fastReset);\n\n      ////////////////////////////////////////////////////////////////////////////////\n      /// Rules\n      ////////////////////////////////////////////////////////////////////////////////\n      (* no_implicit_conditions, fire_when_enabled *)\n      rule every;\n         g.non_posted_ok(True);\n\t g.non_posted_req(True);\n      endrule\n\n      rule accept_data;\n         let data <- g.recv;\n         inFifo.enq(tpl_3(data));\n      endrule\n\n      rule process_incoming_packets(!rSendInvalid);\n         let data = inFifo.first; inFifo.deq;\n         rOddBeat     <= !rOddBeat;\n         rSendInvalid <= !rOddBeat && data.eof;\n         Vector#(1, TLPData#(8)) v = defaultValue;\n         v[0] = data;\n         fifoRxData.enq(v);\n      endrule\n\n      rule send_invalid_packets(rSendInvalid);\n         rOddBeat     <= !rOddBeat;\n         rSendInvalid <= False;\n         Vector#(1, TLPData#(8)) v = defaultValue;\n         v[0].eof = True;\n         v[0].be  = 0;\n         fifoRxData.enq(v);\n      endrule\n\n      rule send_data;\n         function TLPData#(16) combine(Vector#(2, TLPData#(8)) in);\n            return TLPData {\n                            sof:   in[0].sof,\n                            eof:   in[1].eof,\n                            hit:   in[0].hit,\n                            be:    { in[0].be,   in[1].be },\n                            data:  { in[0].data, in[1].data }\n                            };\n         endfunction\n\n         fifoRxData.deq;\n         p.put(combine(fifoRxData.first));\n      endrule\n\n   endmodule\nendinstance\n\ninstance ConnectableWithClocks#(PCIE_TRN_RECV_V7, Put#(TLPData#(16)));\n   module mkConnectionWithClocks#(PCIE_TRN_RECV_V7 g, Put#(TLPData#(16)) p,\n                                  Clock fastClock, Reset fastReset,\n                                  Clock slowClock, Reset slowReset)(Empty);\n      mkConnectionWithClocks(p, g, fastClock, fastReset, slowClock, slowReset);\n   endmodule\nendinstance\n\n// interface tie-offs\n\n\ninstance TieOff#(PCIE_CFG_V7);\n   module mkTieOff#(PCIE_CFG_V7 ifc)(Empty);\n      rule tie_off_inputs;\n\t ifc.di(0);\n\t ifc.dwaddr(0);\n\t ifc.byte_en(0);\n\t ifc.wr_en(0);\n\t ifc.rd_en(0);\n\t ifc.wr_readonly(0);\n\t ifc.trn_pending(0);\n\t ifc.dsn({ 32'h0000_0001, {{ 8'h1 } , 24'h000A35 }});\n\t ifc.pm_halt_aspm_l0s(0);\n\t ifc.pm_halt_aspm_l1(0);\n\t ifc.pm_force_state(0);\n\t ifc.pm_force_state_en(0);\n\t ifc.turnoff_ok(0);\n\t ifc.pm_wake(0);\n      endrule\n   endmodule\nendinstance\n\ninstance TieOff#(PCIE_INT_V7);\n   module mkTieOff#(PCIE_INT_V7 ifc)(Empty);\n      rule tie_off_inputs;\n\t ifc.req(0);\n\t ifc.assrt(0);\n\t ifc.di(0);\n\t ifc.pciecap_msgnum(0);\n\t ifc.stat(0);\n      endrule\n   endmodule\nendinstance\n\ninstance TieOff#(PCIE_ERR_V7);\n   module mkTieOff#(PCIE_ERR_V7 ifc)(Empty);\n      rule tie_off_inputs;\n\t ifc.ecrc(0);\n\t ifc.ur(0);\n\t ifc.cpl_timeout(0);\n\t ifc.cpl_unexpect(0);\n\t ifc.cpl_abort(0);\n\t ifc.posted(0);\n\t ifc.cor(0);\n\t ifc.atomic_egress_blocked(0);\n\t ifc.internal_cor(0);\n\t ifc.internal_uncor(0);\n\t ifc.malformed(0);\n\t ifc.mc_blocked(0);\n\t ifc.poisoned(0);\n\t ifc.no_recovery(0);\n\t ifc.tlp_cpl_header(0);\n\t ifc.locked(0);\n\t ifc.aer_headerlog(0);\n\t ifc.aer_interrupt_msgnum(0);\n\t ifc.acs(0);\n      endrule\n   endmodule\nendinstance\n\ninstance TieOff#(PCIE_PL_V7);\n   module mkTieOff#(PCIE_PL_V7 ifc)(Empty);\n      rule tie_off_inputs;\n\t ifc.directed_link_auton(0);\n\t ifc.directed_link_change(0);\n\t ifc.directed_link_speed(0);\n\t ifc.directed_link_width(0);\n\t ifc.upstream_prefer_deemph(1);\n      endrule\n   endmodule\nendinstance\n\n////////////////////////////////////////////////////////////////////////////////\n/// PART 2: PCIE3 (PCIE3, for VC709 etc.)\n/// This code was initially created in 2014-11\n////////////////////////////////////////////////////////////////////////////////\n\n// ================================================================\n// Types of PCIE3 info connecting to bridge (mkPCIE3toBNocFull) via gearboxes etc.\n\ntypedef struct {\n   Bit #(64)     data;\n   Bool          sop;\n   Bool          eop;\n   Bit #(2)      keep;\n   TLPFirstDWBE  first_be;\n   TLPFirstDWBE  last_be;\n} AxiStCq deriving (Bits, Eq);\n\ntypedef struct {\n   Bit #(64)     data;\n   Bit #(2)      keep;\n   Bool          last;\n} AxiStCc deriving (Bits, Eq);\n\ntypedef struct {\n   Bit #(64)     data;\n   Bool          last;\n   Bit #(2)      keep;\n   Bit #(4)      first_be;\n   Bit #(4)      last_be;\n} AxiStRq deriving (Bits, Eq);\n\ntypedef struct {\n   Bit #(64)     data;\n   Bool          sop;\n   Bool          eop;\n   Bit #(2)      keep;\n   Bit #(8)      be;\n} AxiStRc deriving (Bits, Eq);\n\n// ================================================================\n/// Raw interface from wrapped verilog PCIE3 endpoint\n\n(* always_ready, always_enabled *)\ninterface PCIE3_V7#(numeric type lanes);\n   interface PCIE_EXP#(lanes) pcie;\n   interface Clock            user_clk;\n   interface Reset            user_reset;\n   interface PCIE3_STATUS_V7  status;\n   interface PCIE3_AXI_RQ_V7  axi_rq;\n   interface PCIE3_AXI_RC_V7  axi_rc;\n   interface PCIE3_AXI_CQ_V7  axi_cq;\n   interface PCIE3_AXI_CC_V7  axi_cc;\n   interface PCIE3_INT_V7     cfg_interrupt;\n   interface PCIE3_INT_MSIX_V7 cfg_interrupt_msix;\nendinterface\n\n(* always_ready, always_enabled *)\ninterface PCIE3_STATUS_V7;\n   method    Bool             lnk_up;\n   method    Bool             app_rdy;\n   method    Bit#(3)          max_payload;\n   method    Bit#(3)          max_read_req;\n   method    Bit#(2)          rcb_status;\n   method    Bit#(8)          function_status;\nendinterface\n\n(* always_ready, always_enabled *)\ninterface PCIE3_AXI_RQ_V7;\n   method    Action           tlast(Bool i);\n   method    Action           tdata(Bit#(64) i);\n   method    Action           tuser(Bit#(60) i);\n   method    Action           tkeep(Bit#(2) i);\n   method    Bit#(4)          tready();\n   method    Action           tvalid(Bool i);\nendinterface\n\n(* always_ready, always_enabled *)\ninterface PCIE3_AXI_RC_V7;\n   method    Bit#(64)         tdata();\n   method    Bit#(75)         tuser();\n   method    Bool             tlast();\n   method    Bit#(2)          tkeep();\n   method    Bool             tvalid();\n   method    Action           tready(Bit#(22) i);\nendinterface\n\n(* always_ready, always_enabled *)\ninterface PCIE3_AXI_CQ_V7;\n   method    Bit#(64)         tdata();\n   method    Bit#(85)         tuser();\n   method    Bool             tlast();\n   method    Bit#(2)          tkeep();\n   method    Bool             tvalid();\n   method    Action           tready(Bit#(22) i);\nendinterface\n\n(* always_ready, always_enabled *)\ninterface PCIE3_AXI_CC_V7;\n   method    Action           tlast(Bool i);\n   method    Action           tdata(Bit#(64) i);\n   method    Action           tuser(Bit#(33) i);\n   method    Action           tkeep(Bit#(2) i);\n   method    Bit#(4)          tready();\n   method    Action           tvalid(Bool i);\nendinterface\n\n(* always_ready, always_enabled *)\ninterface PCIE3_INT_V7;\n   method    Action           int_vect(Bit#(4) i);\n   method    Action           pending(Bit#(2) i);\n   method    Bool             sent();\nendinterface\n\n(* always_ready, always_enabled *)\ninterface PCIE3_INT_MSI_V7;\n   method     Bit#(2)         enabled();\n   method     Bit#(6)         vf_enable();\n   method     Bit#(6)         mmenable();\n   method     Bool            mask_update();\n   method     Bit#(32)        data();\n   method     Action          select(Bit#(4) i);\n   method     Action          valid(Bit#(32) i);\n   method     Action          pending_status(Bit#(64) i);\n   method     Bool            sent();\n   method     Bool            fail();\n\n   method     Action          attr(Bit#(3) i);\n   method     Action          tph_present(Bool i);\n   method     Action          tph_type(Bit#(2) i);\n   method     Action          tph_st_tag(Bit#(9) i);\n   method     Action          function_number(Bit#(3) i);\nendinterface\n\n(* always_ready, always_enabled *)\ninterface PCIE3_INT_MSIX_V7;\n   method     Bit#(2)         enabled();\n   method     Bit#(2)         mask();\n   method     Bit#(6)         vf_enable();\n   method     Bit#(6)         vf_mask();\n   method     Action          data(Bit#(32) i);\n   method     Action          address(Bit#(64) i);\n   method     Action          valid(Bit#(1) i); // int\n   method     Bool            sent();\n   method     Bool            fail();\nendinterface\n\n// ================================================================\n// Immediate wrapper for imported Verilog PCIE3 endpoint\n\nimport \"BVI\" xilinx_v7_pcie3_wrapper =\nmodule vMkVirtex7PCIExpress3#(PCIEParams params)(PCIE3_V7#(lanes))\n   provisos( Add#(1, z, lanes) );\n\n   let sys_reset <- invertCurrentReset;\n\n   default_clock sys_clk(sys_clk);  // 100 MHz refclk\n   default_reset sys_rstn(sys_reset) = sys_reset;\n\n   interface PCIE_EXP pcie;\n      method                            rxp(pci_exp_rxp) enable((*inhigh*)en0)                              reset_by(no_reset);\n      method                            rxn(pci_exp_rxn) enable((*inhigh*)en1)                              reset_by(no_reset);\n      method pci_exp_txp                txp                                                                 reset_by(no_reset);\n      method pci_exp_txn                txn                                                                 reset_by(no_reset);\n   endinterface\n\n   output_clock                         user_clk(user_clk);\n   output_reset                         user_reset(user_reset);\n\n   interface PCIE3_STATUS_V7 status;\n      method user_lnk_up                lnk_up                                                              clocked_by(no_clock) reset_by(no_reset); /* semi-static */\n      method user_app_rdy               app_rdy                                                             clocked_by(user_clk) reset_by(no_reset);\n      method cfg_max_payload            max_payload                                                         clocked_by(user_clk) reset_by(no_reset);\n      method cfg_max_read_req           max_read_req                                                        clocked_by(user_clk) reset_by(no_reset);\n      method cfg_rcb_status             rcb_status                                                          clocked_by(user_clk) reset_by(no_reset);\n      method cfg_function_status        function_status                                                     clocked_by(user_clk) reset_by(no_reset);\n   endinterface\n\n   interface PCIE3_AXI_RQ_V7 axi_rq;\n      method                            tlast(s_axis_rq_tlast)                       enable((*inhigh*)en01) clocked_by(user_clk)  reset_by(no_reset);\n      method                            tdata(s_axis_rq_tdata)                       enable((*inhigh*)en02) clocked_by(user_clk)  reset_by(no_reset);\n      method                            tuser(s_axis_rq_tuser)                       enable((*inhigh*)en03) clocked_by(user_clk)  reset_by(no_reset);\n      method                            tkeep(s_axis_rq_tkeep)                       enable((*inhigh*)en04) clocked_by(user_clk)  reset_by(no_reset);\n      method s_axis_rq_tready           tready                                                              clocked_by(user_clk) reset_by(no_reset);\n      method                            tvalid(s_axis_rq_tvalid)                     enable((*inhigh*)en05) clocked_by(user_clk)  reset_by(no_reset);\n   endinterface\n\n   interface PCIE3_AXI_RC_V7 axi_rc;\n      method m_axis_rc_tdata            tdata                                                               clocked_by(user_clk) reset_by(no_reset);\n      method m_axis_rc_tuser            tuser                                                               clocked_by(user_clk) reset_by(no_reset);\n      method m_axis_rc_tlast            tlast                                                               clocked_by(user_clk) reset_by(no_reset);\n      method m_axis_rc_tkeep            tkeep                                                               clocked_by(user_clk) reset_by(no_reset);\n      method m_axis_rc_tvalid           tvalid                                                              clocked_by(user_clk) reset_by(no_reset);\n      method                            tready(m_axis_rc_tready)                     enable((*inhigh*)en06) clocked_by(user_clk) reset_by(no_reset);\n   endinterface\n\n   interface PCIE3_AXI_CQ_V7 axi_cq;\n      method m_axis_cq_tdata            tdata                                                               clocked_by(user_clk) reset_by(no_reset);\n      method m_axis_cq_tuser            tuser                                                               clocked_by(user_clk) reset_by(no_reset);\n      method m_axis_cq_tlast            tlast                                                               clocked_by(user_clk) reset_by(no_reset);\n      method m_axis_cq_tkeep            tkeep                                                               clocked_by(user_clk) reset_by(no_reset);\n      method m_axis_cq_tvalid           tvalid                                                              clocked_by(user_clk) reset_by(no_reset);\n      method                            tready(m_axis_cq_tready)                     enable((*inhigh*)en07) clocked_by(user_clk) reset_by(no_reset);\n   endinterface\n\n   interface PCIE3_AXI_CC_V7 axi_cc;\n      method                            tlast(s_axis_cc_tlast)                       enable((*inhigh*)en08) clocked_by(user_clk)  reset_by(no_reset);\n      method                            tdata(s_axis_cc_tdata)                       enable((*inhigh*)en09) clocked_by(user_clk)  reset_by(no_reset);\n      method                            tuser(s_axis_cc_tuser)                       enable((*inhigh*)en10) clocked_by(user_clk)  reset_by(no_reset);\n      method                            tkeep(s_axis_cc_tkeep)                       enable((*inhigh*)en11) clocked_by(user_clk)  reset_by(no_reset);\n      method s_axis_cc_tready           tready                                                              clocked_by(user_clk) reset_by(no_reset);\n      method                            tvalid(s_axis_cc_tvalid)                     enable((*inhigh*)en12) clocked_by(user_clk)  reset_by(no_reset);\n   endinterface\n\n   interface PCIE3_INT_V7 cfg_interrupt;\n      method                            int_vect(cfg_interrupt_int)                  enable((*inhigh*)en13) clocked_by(user_clk)  reset_by(no_reset);\n      method                            pending(cfg_interrupt_pending)               enable((*inhigh*)en14) clocked_by(user_clk)  reset_by(no_reset);\n      method cfg_interrupt_sent         sent                                                                clocked_by(user_clk) reset_by(no_reset);\n   endinterface\n\n   interface PCIE3_INT_MSIX_V7 cfg_interrupt_msix;\n      method cfg_interrupt_msix_enable  enabled                                                             clocked_by(user_clk)  reset_by(no_reset);\n      method cfg_interrupt_msix_mask    mask                                                                clocked_by(user_clk)  reset_by(no_reset);\n      method cfg_interrupt_msix_vf_enable vf_enable                                                         clocked_by(user_clk)  reset_by(no_reset);\n      method cfg_interrupt_msix_vf_mask vf_mask                                                             clocked_by(user_clk)  reset_by(no_reset);\n      method                            data(cfg_interrupt_msix_data)                enable((*inhigh*)en23) clocked_by(user_clk)  reset_by(no_reset);\n      method                            address(cfg_interrupt_msix_address)          enable((*inhigh*)en24) clocked_by(user_clk)  reset_by(no_reset);\n      method                            valid(cfg_interrupt_msix_int)                enable((*inhigh*)en25) clocked_by(user_clk)  reset_by(no_reset);\n      method cfg_interrupt_msix_sent    sent                                                                clocked_by(user_clk)  reset_by(no_reset);\n      method cfg_interrupt_msix_fail    fail                                                                clocked_by(user_clk)  reset_by(no_reset);\n   endinterface\n\n   schedule (status_lnk_up, status_app_rdy, axi_rq_tlast, axi_rq_tdata, axi_rq_tuser, axi_rq_tkeep, axi_rq_tready,\n\t     axi_rq_tvalid, axi_rc_tdata, axi_rc_tuser, axi_rc_tlast, axi_rc_tkeep, axi_rc_tvalid, axi_rc_tready,\n\t     axi_cq_tdata, axi_cq_tuser, axi_cq_tlast, axi_cq_tkeep, axi_cq_tvalid, axi_cq_tready, axi_cc_tlast,\n\t     axi_cc_tdata, axi_cc_tuser, axi_cc_tkeep, axi_cc_tready, axi_cc_tvalid, cfg_interrupt_int_vect,\n\t     cfg_interrupt_pending, cfg_interrupt_sent, cfg_interrupt_msix_enabled, cfg_interrupt_msix_mask, cfg_interrupt_msix_vf_enable,\n\t     cfg_interrupt_msix_vf_mask, cfg_interrupt_msix_data, cfg_interrupt_msix_address, cfg_interrupt_msix_valid,\n\t     cfg_interrupt_msix_sent, cfg_interrupt_msix_fail, pcie_txp, pcie_txn, pcie_rxp, pcie_rxn,\n\t     status_max_payload, status_max_read_req, status_rcb_status, status_function_status) CF\n            (status_lnk_up, status_app_rdy, axi_rq_tlast, axi_rq_tdata, axi_rq_tuser, axi_rq_tkeep, axi_rq_tready,\n\t     axi_rq_tvalid, axi_rc_tdata, axi_rc_tuser, axi_rc_tlast, axi_rc_tkeep, axi_rc_tvalid, axi_rc_tready,\n\t     axi_cq_tdata, axi_cq_tuser, axi_cq_tlast, axi_cq_tkeep, axi_cq_tvalid, axi_cq_tready, axi_cc_tlast,\n\t     axi_cc_tdata, axi_cc_tuser, axi_cc_tkeep, axi_cc_tready, axi_cc_tvalid, cfg_interrupt_int_vect,\n\t     cfg_interrupt_pending, cfg_interrupt_sent, cfg_interrupt_msix_enabled, cfg_interrupt_msix_mask, cfg_interrupt_msix_vf_enable,\n\t     cfg_interrupt_msix_vf_mask, cfg_interrupt_msix_data, cfg_interrupt_msix_address, cfg_interrupt_msix_valid,\n\t     cfg_interrupt_msix_sent, cfg_interrupt_msix_fail, pcie_txp, pcie_txn, pcie_rxp, pcie_rxn,\n\t     status_max_payload, status_max_read_req, status_rcb_status, status_function_status);\nendmodule\n\n// ================================================================\n// Interfaces PCIE3 for bridge\n\ninterface PCIExpress3V7 #(numeric type lanes);\n   interface PCIE_EXP#(lanes)    pcie;\n   interface Clock               uclk;\n   interface Reset               ureset;\n   interface Clock               uclk_half;\n   interface Reset               ureset_half;\n   interface PCIE3_STATUS_V7     status;\n   interface Get #(AxiStCq)      cq_recv;\n   interface Put #(AxiStCc)      cc_xmit;\n   interface Put #(AxiStRq)      rq_xmit;\n   interface Get #(AxiStRc)      rc_recv;\n   interface PCIE3_INT_V7        cfg_interrupt;\n   interface PCIE3_INT_MSIX_V7   cfg_interrupt_msix;\n   interface XilinxClkServer     clks;\n   interface Clock               cclk;\nendinterface\n\n////////////////////////////////////////////////////////////////////////////////\n/// For PCIE3\n/// Typeclass to select vMkVirtex7PCIExpress3() for 1, 4, 8 lanes\n////////////////////////////////////////////////////////////////////////////////\n\ntypeclass SelectVirtex7PCIE3#(numeric type lanes);\n   module selectVirtex7PCIE3(PCIEParams params, PCIE3_V7#(lanes) ifc);\nendtypeclass\n\ninstance SelectVirtex7PCIE3#(8);\n   module selectVirtex7PCIE3(PCIEParams params, PCIE3_V7#(8) ifc);\n      let _ifc <- vMkVirtex7PCIExpress3(params);\n      return _ifc;\n   endmodule\nendinstance\n\ninstance SelectVirtex7PCIE3#(4);\n   module selectVirtex7PCIE3(PCIEParams params, PCIE3_V7#(4) ifc);\n      let _ifc <- vMkVirtex7PCIExpress3(params);\n      return _ifc;\n   endmodule\nendinstance\n\ninstance SelectVirtex7PCIE3#(1);\n   module selectVirtex7PCIE3(PCIEParams params, PCIE3_V7#(1) ifc);\n      let _ifc <- vMkVirtex7PCIExpress3(params);\n      return _ifc;\n   endmodule\nendinstance\n\n////////////////////////////////////////////////////////////////\n// The BSV PCIE3 endpoint\n////////////////////////////////////////////////////////////////\n\nmodule mkPCIExpress3EndpointV7 #(PCIEParams params) (PCIExpress3V7 #(lanes))\n   provisos(Add #(1, z, lanes), SelectVirtex7PCIE3 #(lanes));\n\n   // Instantiate Vivado-generated, wrapped Verilog endpoint\n   PCIE3_V7 #(lanes)                         pcie_ep             <- selectVirtex7PCIE3 (params);\n\n   Clock                                     user_clk             = pcie_ep.user_clk;\n   Reset                                     user_reset_raw      <- mkResetInverter (pcie_ep.user_reset, clocked_by user_clk);\n   Reset                                     user_reset          <- mkAsyncReset(4, user_reset_raw, user_clk);\n\n   ClockGenerator7Params                     clk_params           = defaultValue;\n   clk_params.clkin1_period    = 4.000;\n   clk_params.clkin_buffer     = False;\n   clk_params.clkfbout_mult_f  = 4.000;\n   clk_params.clkout0_divide_f = 8.000;\n   ClockGenerator7                           clkgen              <- mkClockGenerator7 (clk_params,\n\t\t\t\t\t\t\t\t\t\t       clocked_by user_clk,\n\t\t\t\t\t\t\t\t\t\t       reset_by user_reset_raw);\n   Clock                                     user_clk_half        = clkgen.clkout0;\n   Reset                                     user_reset_half     <- mkAsyncReset(4, user_reset_raw, user_clk_half);\n\n   XilinxClockParams                         cclk_params          = defaultValue;\n   cclk_params.e_type           = E2;\n   cclk_params.clkin1_period    = 8.000;\n   cclk_params.clkfbout_mult_f  = 8.000;\n   cclk_params.clkout0_divide_f = params.clock_period;\n   // XXX Can we use \"user_reset_half\" here?\n   Reset                                     cclk_clkgen_reset   <- mkAsyncReset(1, user_reset_raw, user_clk_half);\n   XilinxClockController                     cclk_clkgen         <- mkXilinxClockController (cclk_params,\n\t\t\t\t\t\t\t\t\t\t\t     user_clk_half,\n\t\t\t\t\t\t\t\t\t\t\t     clocked_by user_clk_half,\n\t\t\t\t\t\t\t\t\t\t\t     reset_by cclk_clkgen_reset);\n\n   // ----------------\n   // FIFOs that drain the CQ and RC AXI Stream interfaces\n\n   FIFOF #(AxiStCq)  fAxiCq          <- mkBypassFIFOF (clocked_by user_clk, reset_by user_reset);\n\n   // RC\n   FIFOF #(AxiStRc)  fAxiRc          <- mkBypassFIFOF (clocked_by user_clk, reset_by user_reset);\n\n   // ----------------\n   // FIFOs that feed the CC and RQ AXI Stream interfaces\n\n   // CC\n   FIFO#(AxiStCc)    fAxiCc          <- mkCCBuffer(clocked_by user_clk, reset_by user_reset);\n   Wire#(Bit#(64))   wAxiCcData      <- mkDWire(0, clocked_by user_clk, reset_by user_reset);\n   Wire#(Bool)       wAxiCcLast      <- mkDWire(False, clocked_by user_clk, reset_by user_reset);\n   Wire#(Bit#(2))    wAxiCcKeep      <- mkDWire(0, clocked_by user_clk, reset_by user_reset);\n   Wire#(Bit #(33))  wAxiCcUser      <- mkDWire(0, clocked_by user_clk, reset_by user_reset);\n   Wire#(Bool)       wAxiCcValid     <- mkDWire(False, clocked_by user_clk, reset_by user_reset);\n\n   // RQ\n   FIFO#(AxiStRq)    fAxiRq          <- mkRQBuffer(clocked_by user_clk, reset_by user_reset);\n   Wire#(Bit#(64))   wAxiRqData      <- mkDWire(0, clocked_by user_clk, reset_by user_reset);\n   Wire#(Bool)       wAxiRqLast      <- mkDWire(False, clocked_by user_clk, reset_by user_reset);\n   Wire#(Bit#(2))    wAxiRqKeep      <- mkDWire(0, clocked_by user_clk, reset_by user_reset);\n   Wire#(Bit#(60))   wAxiRqUser      <- mkDWire(0, clocked_by user_clk, reset_by user_reset);\n   Wire#(Bool)       wAxiRqValid     <- mkDWire(False, clocked_by user_clk, reset_by user_reset);\n\n   // ----------------------------------------------------------------\n   // RULES\n\n   // ----------------\n   // CQ (requests from host): here at 250 MHz we only collect the\n   // info we need and pass it on; the actual parsing of descriptors\n   // and payloads happens in the 125 MHz domain which can accommodate\n   // more complex circuits.\n\n   // Collect cq from AXI into FIFO fAxiCq\n   (* fire_when_enabled, no_implicit_conditions *)\n   rule drive_axi_cq_ready;\n      pcie_ep.axi_cq.tready (duplicate (pack (fAxiCq.notFull)));\n   endrule\n\n   rule process_ax_cq_beat (pcie_ep.axi_cq.tvalid && fAxiCq.notFull);\n      let cq = AxiStCq {data:     pcie_ep.axi_cq.tdata,\n\t\t\tsop:      unpack (pcie_ep.axi_cq.tuser [40]),  // tuser.sop\n\t\t\teop:      pcie_ep.axi_cq.tlast,\n\t\t\tkeep:     pcie_ep.axi_cq.tkeep,\n\t\t\tfirst_be: pcie_ep.axi_cq.tuser [3:0],    // tuser.first_be,\n\t\t\tlast_be:  pcie_ep.axi_cq.tuser [7:4]};   // tuser.last_be\n      fAxiCq.enq (cq);\n   endrule\n\n   // ----------------\n   // RC (completions from host): here at 250 MHz we only collect the\n   // info we need and pass it on; the actual parsing of descriptors\n   // and payloads happens in the 125 MHz domain which can accommodate\n   // more complex circuits\n\n   (* fire_when_enabled, no_implicit_conditions *)\n   rule drive_axi_rc_ready;\n      pcie_ep.axi_rc.tready (duplicate (pack (fAxiRc.notFull)));\n   endrule\n\n   rule process_ax_rc_beat (pcie_ep.axi_rc.tvalid && fAxiRc.notFull);\n      let rc = AxiStRc {data:pcie_ep.axi_rc.tdata,\n\t\t\tsop: unpack (pcie_ep.axi_rc.tuser [32]),         // tuser.is_sof_0\n\t\t\teop: pcie_ep.axi_rc.tlast,\n\t\t\tkeep:pcie_ep.axi_rc.tkeep,\n\t\t\tbe:  truncate (pcie_ep.axi_rc.tuser [31:0])};    // tuser.byte_en\n      fAxiRc.enq (rc);\n   endrule\n\n   // Move rc from FIFO fAxiRc_a to fAxiRc_b, injecting an 'empty'\n   // pad, if necessary, to ensure that sop is on an even enq\n\n   // ----------------\n   // CC (completions to host): here at 250 MHz we just pass on the\n   // info we get from the bridge, which was created at 125 MHz.\n\n   (* fire_when_enabled, no_implicit_conditions *)\n   rule drive_axi_cc;\n      pcie_ep.axi_cc.tdata  (wAxiCcData);\n      pcie_ep.axi_cc.tkeep  (wAxiCcKeep);\n      pcie_ep.axi_cc.tlast  (wAxiCcLast);\n      pcie_ep.axi_cc.tuser  (wAxiCcUser);\n      pcie_ep.axi_cc.tvalid (wAxiCcValid);\n   endrule\n\n   (* fire_when_enabled *)\n   rule drive_axi_cc_info (pcie_ep.axi_cc.tready != 0);\n      let cc <- toGet (fAxiCc).get;\n      wAxiCcValid <= True;\n      wAxiCcLast  <= cc.last;\n      wAxiCcData  <= cc.data;\n      wAxiCcKeep  <= cc.keep;\n      wAxiCcUser  <= 0;        // tuser.discontinue and tuser.parity[31:0]\n   endrule\n\n   // ----------------\n   // RQ (requests to host): here at 250 MHz we just pass on the\n   // info we get from the bridge, which was created at 125 MHz.\n\n   (* fire_when_enabled, no_implicit_conditions *)\n   rule drive_axi_rq;\n      pcie_ep.axi_rq.tdata  (wAxiRqData);\n      pcie_ep.axi_rq.tkeep  (wAxiRqKeep);\n      pcie_ep.axi_rq.tlast  (wAxiRqLast);\n      pcie_ep.axi_rq.tuser  (wAxiRqUser);\n      pcie_ep.axi_rq.tvalid (wAxiRqValid);\n   endrule\n\n   (* fire_when_enabled *)\n   rule drive_axi_rq_info (pcie_ep.axi_rq.tready != 0);\n      let rq <- toGet (fAxiRq).get;\n      wAxiRqValid <= True;\n      wAxiRqData  <= rq.data;\n      wAxiRqLast  <= rq.last;\n      wAxiRqKeep  <= rq.keep;\n      wAxiRqUser  <= { 0, rq.last_be, rq.first_be};\n   endrule\n\n   ////////////////////////////////////////////////////////////////////////////////\n   /// Interface Connections / Methods\n   ////////////////////////////////////////////////////////////////////////////////\n\n   interface pcie = pcie_ep.pcie;\n\n   interface uclk        = user_clk;\n   interface ureset      = user_reset;\n\n   interface uclk_half   = user_clk_half;\n   interface ureset_half = user_reset_half;\n\n   interface PCIE3_STATUS_V7 status;\n      method    lnk_up = pcie_ep.status.lnk_up;\n      method    app_rdy = pcie_ep.status.app_rdy;\n      method    max_payload = pcie_ep.status.max_payload;\n      method    max_read_req = pcie_ep.status.max_read_req;\n      method    rcb_status = pcie_ep.status.rcb_status;\n      method    function_status = pcie_ep.status.function_status;\n   endinterface\n\n   interface cq_recv = toGet (fAxiCq);\n   interface rc_recv = toGet (fAxiRc);\n\n   interface cc_xmit = toPut (fAxiCc);\n   interface rq_xmit = toPut (fAxiRq);\n\n   interface cfg_interrupt      = pcie_ep.cfg_interrupt;\n   interface cfg_interrupt_msix = pcie_ep.cfg_interrupt_msix;\n\n   interface cclk = cclk_clkgen.clkout0;\n\n   interface XilinxClkServer clks;\n      interface Put request;\n\t method Action put(Bit#(32) x);\n\t    let request = XilinxClockRequest {\n\t       rnw:  unpack(x[31]),\n\t       addr: x[20:16],\n\t       data: x[15:0]\n\t       };\n\t    cclk_clkgen.csr.request.put(request);\n\t endmethod\n      endinterface\n      interface Get response;\n\t method ActionValue#(Bit#(32)) get;\n\t    let response <- cclk_clkgen.csr.response.get;\n\t    return cExtend(response);\n\t endmethod\n      endinterface\n   endinterface\nendmodule\n\nmodule mkPCIExpress3EndpointNoClkV7 #(PCIEParams params) (PCIExpress3V7 #(lanes))\n   provisos(Add #(1, z, lanes), SelectVirtex7PCIE3 #(lanes));\n\n   // Instantiate Vivado-generated, wrapped Verilog endpoint\n   PCIE3_V7 #(lanes)                         pcie_ep             <- selectVirtex7PCIE3 (params);\n\n   Clock                                     user_clk             = pcie_ep.user_clk;\n   Reset                                     user_reset_raw      <- mkResetInverter (pcie_ep.user_reset, clocked_by user_clk);\n   Reset                                     user_reset          <- mkAsyncReset(4, user_reset_raw, user_clk);\n\n   ClockGenerator7Params                     clk_params           = defaultValue;\n   clk_params.clkin1_period    = 4.000;\n   clk_params.clkin_buffer     = False;\n   clk_params.clkfbout_mult_f  = 4.000;\n   clk_params.clkout0_divide_f = 8.000;\n   ClockGenerator7                           clkgen              <- mkClockGenerator7 (clk_params,\n\t\t\t\t\t\t\t\t\t\t       clocked_by user_clk,\n\t\t\t\t\t\t\t\t\t\t       reset_by user_reset_raw);\n   Clock                                     user_clk_half        = clkgen.clkout0;\n   Reset                                     user_reset_half     <- mkAsyncReset(4, user_reset_raw, user_clk_half);\n\n   // ----------------\n   // FIFOs that drain the CQ and RC AXI Stream interfaces\n\n   FIFOF #(AxiStCq)  fAxiCq          <- mkBypassFIFOF (clocked_by user_clk, reset_by user_reset);\n\n   // RC\n   FIFOF #(AxiStRc)  fAxiRc          <- mkBypassFIFOF (clocked_by user_clk, reset_by user_reset);\n\n   // ----------------\n   // FIFOs that feed the CC and RQ AXI Stream interfaces\n\n   // CC\n   FIFO#(AxiStCc)    fAxiCc          <- mkCCBuffer(clocked_by user_clk, reset_by user_reset);\n   Wire#(Bit#(64))   wAxiCcData      <- mkDWire(0, clocked_by user_clk, reset_by user_reset);\n   Wire#(Bool)       wAxiCcLast      <- mkDWire(False, clocked_by user_clk, reset_by user_reset);\n   Wire#(Bit#(2))    wAxiCcKeep      <- mkDWire(0, clocked_by user_clk, reset_by user_reset);\n   Wire#(Bit #(33))  wAxiCcUser      <- mkDWire(0, clocked_by user_clk, reset_by user_reset);\n   Wire#(Bool)       wAxiCcValid     <- mkDWire(False, clocked_by user_clk, reset_by user_reset);\n\n   // RQ\n   FIFO#(AxiStRq)    fAxiRq          <- mkRQBuffer(clocked_by user_clk, reset_by user_reset);\n   Wire#(Bit#(64))   wAxiRqData      <- mkDWire(0, clocked_by user_clk, reset_by user_reset);\n   Wire#(Bool)       wAxiRqLast      <- mkDWire(False, clocked_by user_clk, reset_by user_reset);\n   Wire#(Bit#(2))    wAxiRqKeep      <- mkDWire(0, clocked_by user_clk, reset_by user_reset);\n   Wire#(Bit#(60))   wAxiRqUser      <- mkDWire(0, clocked_by user_clk, reset_by user_reset);\n   Wire#(Bool)       wAxiRqValid     <- mkDWire(False, clocked_by user_clk, reset_by user_reset);\n\n   // ----------------------------------------------------------------\n   // RULES\n\n   // ----------------\n   // CQ (requests from host): here at 250 MHz we only collect the\n   // info we need and pass it on; the actual parsing of descriptors\n   // and payloads happens in the 125 MHz domain which can accommodate\n   // more complex circuits.\n\n   // Collect cq from AXI into FIFO fAxiCq\n   (* fire_when_enabled, no_implicit_conditions *)\n   rule drive_axi_cq_ready;\n      pcie_ep.axi_cq.tready (duplicate (pack (fAxiCq.notFull)));\n   endrule\n\n   rule process_ax_cq_beat (pcie_ep.axi_cq.tvalid && fAxiCq.notFull);\n      let cq = AxiStCq {data:     pcie_ep.axi_cq.tdata,\n\t\t\tsop:      unpack (pcie_ep.axi_cq.tuser [40]),  // tuser.sop\n\t\t\teop:      pcie_ep.axi_cq.tlast,\n\t\t\tkeep:     pcie_ep.axi_cq.tkeep,\n\t\t\tfirst_be: pcie_ep.axi_cq.tuser [3:0],    // tuser.first_be,\n\t\t\tlast_be:  pcie_ep.axi_cq.tuser [7:4]};   // tuser.last_be\n      fAxiCq.enq (cq);\n   endrule\n\n   // ----------------\n   // RC (completions from host): here at 250 MHz we only collect the\n   // info we need and pass it on; the actual parsing of descriptors\n   // and payloads happens in the 125 MHz domain which can accommodate\n   // more complex circuits\n\n   (* fire_when_enabled, no_implicit_conditions *)\n   rule drive_axi_rc_ready;\n      pcie_ep.axi_rc.tready (duplicate (pack (fAxiRc.notFull)));\n   endrule\n\n   rule process_ax_rc_beat (pcie_ep.axi_rc.tvalid && fAxiRc.notFull);\n      let rc = AxiStRc {data:pcie_ep.axi_rc.tdata,\n\t\t\tsop: unpack (pcie_ep.axi_rc.tuser [32]),         // tuser.is_sof_0\n\t\t\teop: pcie_ep.axi_rc.tlast,\n\t\t\tkeep:pcie_ep.axi_rc.tkeep,\n\t\t\tbe:  truncate (pcie_ep.axi_rc.tuser [31:0])};    // tuser.byte_en\n      fAxiRc.enq (rc);\n   endrule\n\n   // Move rc from FIFO fAxiRc_a to fAxiRc_b, injecting an 'empty'\n   // pad, if necessary, to ensure that sop is on an even enq\n\n   // ----------------\n   // CC (completions to host): here at 250 MHz we just pass on the\n   // info we get from the bridge, which was created at 125 MHz.\n\n   (* fire_when_enabled, no_implicit_conditions *)\n   rule drive_axi_cc;\n      pcie_ep.axi_cc.tdata  (wAxiCcData);\n      pcie_ep.axi_cc.tkeep  (wAxiCcKeep);\n      pcie_ep.axi_cc.tlast  (wAxiCcLast);\n      pcie_ep.axi_cc.tuser  (wAxiCcUser);\n      pcie_ep.axi_cc.tvalid (wAxiCcValid);\n   endrule\n\n   (* fire_when_enabled *)\n   rule drive_axi_cc_info (pcie_ep.axi_cc.tready != 0);\n      let cc <- toGet (fAxiCc).get;\n      wAxiCcValid <= True;\n      wAxiCcLast  <= cc.last;\n      wAxiCcData  <= cc.data;\n      wAxiCcKeep  <= cc.keep;\n      wAxiCcUser  <= 0;        // tuser.discontinue and tuser.parity[31:0]\n   endrule\n\n   // ----------------\n   // RQ (requests to host): here at 250 MHz we just pass on the\n   // info we get from the bridge, which was created at 125 MHz.\n\n   (* fire_when_enabled, no_implicit_conditions *)\n   rule drive_axi_rq;\n      pcie_ep.axi_rq.tdata  (wAxiRqData);\n      pcie_ep.axi_rq.tkeep  (wAxiRqKeep);\n      pcie_ep.axi_rq.tlast  (wAxiRqLast);\n      pcie_ep.axi_rq.tuser  (wAxiRqUser);\n      pcie_ep.axi_rq.tvalid (wAxiRqValid);\n   endrule\n\n   (* fire_when_enabled *)\n   rule drive_axi_rq_info (pcie_ep.axi_rq.tready != 0);\n      let rq <- toGet (fAxiRq).get;\n      wAxiRqValid <= True;\n      wAxiRqData  <= rq.data;\n      wAxiRqLast  <= rq.last;\n      wAxiRqKeep  <= rq.keep;\n      wAxiRqUser  <= { 0, rq.last_be, rq.first_be};\n   endrule\n\n   ////////////////////////////////////////////////////////////////////////////////\n   /// Interface Connections / Methods\n   ////////////////////////////////////////////////////////////////////////////////\n\n   interface pcie = pcie_ep.pcie;\n\n   interface uclk        = user_clk;\n   interface ureset      = user_reset;\n\n   interface uclk_half   = user_clk_half;\n   interface ureset_half = user_reset_half;\n\n   interface PCIE3_STATUS_V7 status;\n      method    lnk_up = pcie_ep.status.lnk_up;\n      method    app_rdy = pcie_ep.status.app_rdy;\n      method    max_payload = pcie_ep.status.max_payload;\n      method    max_read_req = pcie_ep.status.max_read_req;\n      method    rcb_status = pcie_ep.status.rcb_status;\n      method    function_status = pcie_ep.status.function_status;\n   endinterface\n\n   interface cq_recv = toGet (fAxiCq);\n   interface rc_recv = toGet (fAxiRc);\n\n   interface cc_xmit = toPut (fAxiCc);\n   interface rq_xmit = toPut (fAxiRq);\n\n   interface cfg_interrupt      = pcie_ep.cfg_interrupt;\n   interface cfg_interrupt_msix = pcie_ep.cfg_interrupt_msix;\nendmodule\n\n// ================================================================\n// Connecting/converting stream AxiCq ==> stream TLPData#(16)\n\ninstance ConnectableWithClocks #(Get #(AxiStCq), Put #(TLPData #(16)));\n   module mkConnectionWithClocks #(Get #(AxiStCq) g, Put #(TLPData #(16)) p,\n\t\t\t\t   Clock fastClock, Reset fastReset,\n\t\t\t\t   Clock slowClock, Reset slowReset) (Empty);\n\n      // Data path: g -> gearbox_1_2 -> f_cq -> p\n\n      Reg #(Bool) rg_even_enq     <- mkReg (True, clocked_by fastClock, reset_by fastReset);\n      Reg #(Bool) rg_pad_odd_tail <- mkReg (False, clocked_by fastClock, reset_by fastReset);\n\n      // Buffer incoming messages for timing\n      FIFO #(AxiStCq) in_buf <- mkFIFO(clocked_by fastClock, reset_by fastReset);\n      mkConnection(g, toPut(in_buf));\n      let g_buf = toGet(in_buf);\n\n      Gearbox #(1, 2, AxiStCq) gearbox <- mk1toNGearbox (fastClock, fastReset, slowClock, slowReset);\n\n      // f_cq provides one extra level of buffering, allowing us to\n      // examine 3 AxiStCqs (two at head of f_cq, and one at head of\n      // gearbox). This is needed for write packets, where we have to\n      // look descriptor (64b,64b) + 32b data (1st. half of 3rd 64b)\n\n      FIFOF #(Vector #(2, AxiStCq)) f_cq   <- mkPipelineFIFOF (clocked_by slowClock,\n\t\t\t\t\t\t\t       reset_by slowReset);\n\n      // ----------------\n      // g -> gearbox\n\n      // If eop happens on an even enq, we insert a dummy odd enq, for two reasons:\n      // (1) sop is always an even enq, so it is in element [0] of the gearbox output\n      // (2) to avoid deadlock/delay: the gearbox output does not show\n      //       up until it has received both an even and an odd enq\n\n      // Incoming AxiStCq: g ==> gearbox (fast clock)\n      rule rl_g_to_gearbox (! rg_pad_odd_tail);\n\t let cq <- g_buf.get;\n\t // Assert: cq.sop => rg_even_enq\n\t Vector #(1, AxiStCq) v1 = replicate (cq);\n\t gearbox.enq (v1);\n\t rg_pad_odd_tail <= (cq.eop && rg_even_enq);\n\t rg_even_enq     <= ! rg_even_enq;\n      endrule\n\n      rule rl_g_to_gearbox_pad_odd_tail (rg_pad_odd_tail);\n\t AxiStCq cq = unpack (0);\n\t Vector #(1, AxiStCq) v1 = replicate (cq);\n\t gearbox.enq (v1);\n\t rg_pad_odd_tail <= False;\n\t rg_even_enq     <= True;\n      endrule\n\n      // ----------------\n      // gearbox -> f_cq (slow clock)\n\n      rule rl_slowclock;\n\t Vector #(2, AxiStCq) v2 = gearbox.first;\n\t gearbox.deq;\n\t f_cq.enq (v2);\n      endrule\n\n      Reg #(DWCount)     rg_dwcount <- mkRegU (clocked_by slowClock, reset_by slowReset);\n\n      CQDescriptor cq_desc = unpack ({ f_cq.first [1].data, f_cq.first [0].data });\n\n      // 'Write' headers\n      rule rl_wr_header (f_cq.first [0].sop\n\t\t\t && ((cq_desc.reqtype == MEMORY_WRITE) || (cq_desc.reqtype == IO_WRITE)));\n\n\t // Consume 1st 32b of data of next axi beat (head of gearbox FIFO)\n\t // Note: gearbox.first will move into f_cq, where remaining 32 bits will be consumed\n\t Bit #(32) data = gearbox.first [0].data [31:0];\n\n\t // this takes the data in the Xilinx byte order and converts it\n\t TLPData #(16) tlp16 = convertCQDescriptorToTLP16 (cq_desc,\n\t\t\t\t\t\t\t   data,\n\t\t\t\t\t\t\t   f_cq.first [0].first_be,\n\t\t\t\t\t\t\t   f_cq.first [0].last_be);\n\t p.put (tlp16);\n\n\t rg_dwcount  <= cq_desc.dwcount - 1;    // Since first DW is in the tlp16\n\t f_cq.deq;\n      endrule\n\n      // 'Read' headers\n      rule rl_rd_header (f_cq.first [0].sop\n\t\t\t && ((cq_desc.reqtype == MEMORY_READ) || (cq_desc.reqtype == IO_READ)));\n\n\t Bit #(32) data = 0;    // don't care, but set to 0 for deterministic debugging\n\n\t TLPData #(16) tlp16 = convertCQDescriptorToTLP16 (cq_desc,\n\t\t\t\t\t\t\t   data,\n\t\t\t\t\t\t\t   f_cq.first [0].first_be,\n\t\t\t\t\t\t\t   f_cq.first [0].last_be);\n\t p.put (tlp16);\n\n\t f_cq.deq;\n      endrule\n\n      // 'Write' data payload; no data remaining\n      rule rl_data_0 ((! f_cq.first [0].sop) && (rg_dwcount == 0));\n\t // f_cq.first [0].data [31:0] already consumed\n\t // f_cq.first [0].data [64:32] and f_cq.first [1].data [64:0] are just padding\n\t f_cq.deq;\n      endrule\n\n      // 'Write' data payload 1 to 3 DWs remaining\n      rule rl_data_1_to_3 ((! f_cq.first [0].sop) && (rg_dwcount > 0) && (rg_dwcount < 4));\n\t Bit #(16) be16 = 0;\n\t case (rg_dwcount)\n\t    1: be16 = 16'hF000;\n\t    2: be16 = 16'hFF00;\n\t    3: be16 = 16'hFFF0;\n\t endcase\n\t Vector#(4, Bit#(32)) data_vec = replicate(0);\n\t data_vec[3] = convertDW(f_cq.first [0].data [63:32]) ;\n\t data_vec[2] = convertDW(f_cq.first [1].data [31:0]) ;\n\t data_vec[1] = convertDW(f_cq.first [1].data [63:32]) ;\n\t TLPData #(16) tlp16 = TLPData {sof: False,\n\t\t\t\t\teof: True,\n\t\t\t\t\thit: 0,\n\t\t\t\t\tbe:  be16,\n\t\t\t\t\tdata: pack(data_vec)};\n\t p.put (tlp16);\n\t f_cq.deq;\n\t rg_dwcount <= 0;\n      endrule\n\n      // 'Write' data payload >= 4 DWs remaining\n      rule rl_data_4 ((! f_cq.first [0].sop) && (rg_dwcount > 3));\n\t Vector#(4, Bit#(32)) data_vec;\n\t data_vec[3] = convertDW(f_cq.first [0].data [63:32]) ;\n\t data_vec[2] = convertDW(f_cq.first [1].data [31:0]) ;\n\t data_vec[1] = convertDW(f_cq.first [1].data [63:32]) ;\n\t data_vec[0] = convertDW(gearbox.first [0].data [31:0]) ;\n\t TLPData #(16) tlp16 = TLPData {sof: False,\n\t\t\t\t\teof: (rg_dwcount == 4),\n\t\t\t\t\thit: 0,\n\t\t\t\t\tbe:  '1,\n\t\t\t\t\tdata: pack(data_vec)};\n\t p.put (tlp16);\n\t f_cq.deq;\n\t rg_dwcount <= rg_dwcount - 4;\n      endrule\n\n   endmodule\nendinstance\n\ninstance ConnectableWithClocks #(Put #(TLPData #(16)), Get #(AxiStCq));\n   module mkConnectionWithClocks #(Put #(TLPData #(16)) p, Get #(AxiStCq) g,\n\t\t\t\t   Clock fastClock, Reset fastReset,\n\t\t\t\t   Clock slowClock, Reset slowReset) (Empty);\n      mkConnectionWithClocks (g, p, fastClock, fastReset, slowClock, slowReset);\n   endmodule\nendinstance\n\n// ================================================================\n// Connecting/converting stream AxiCc <== stream TLPData#(16)\n\ninstance ConnectableWithClocks #(Get #(TLPData #(16)), Put #(AxiStCc));\n   module mkConnectionWithClocks #(Get #(TLPData #(16)) g, Put #(AxiStCc) p,\n\t\t\t\t   Clock fastClock, Reset fastReset,\n\t\t\t\t   Clock slowClock, Reset slowReset) (Empty);\n\n      // Data path: p <- gearbox_1_2 <- f_tlps <- g\n\n      FIFOF #(TLPData #(16)) f_tlps <- mkPipelineFIFOF (clocked_by slowClock, reset_by slowReset);\n      Gearbox #(2, 1, AxiStCc) gearbox <- mkNto1Gearbox (slowClock, slowReset, fastClock, fastReset);\n\n      Reg #(DWCount) rg_dwcount <- mkReg (0, clocked_by slowClock, reset_by slowReset);\n\n      // ----------------\n      // f_tlps <== g\n      // This step would not be necessary if we could examine the .sof\n      // of g.get tlp without dequeueing.\n      // TODO: is this redundant with rg_dwcount == 0? i.e., does sof <=> (rg_dwcount == 0)?\n\n      rule rl_get_tlps;    // (slow clock)\n\t let tlp <- g.get;\n\t f_tlps.enq (tlp);\n      endrule\n\n      // ----------------\n      // gearbox <== f_tlps    for completion header (slow clock)\n\n      rule rl_header (f_tlps.first.sof);\n\t Vector #(2, AxiStCc) v2 = newVector;\n\n\t // this returns the data in the Xilinx byte order\n\t match { .cc_desc, .dw } = convertTLP16ToCCDescriptor (f_tlps.first);\n\t rg_dwcount <= cc_desc.dwcount - 1;    // since AxiStCC contains first DW\n\n\t v2[0] = AxiStCc {data: pack (cc_desc) [63:0],\n\t\t\t  last: False,\n\t\t\t  keep: 2'b11 };\n\t v2[1] = AxiStCc {data: { dw, pack (cc_desc) [95:64] },\n\t\t\t  last: f_tlps.first.eof,\n\t\t\t  keep: 2'b11 };\n\t gearbox.enq (v2);\n\t f_tlps.deq;\n      endrule\n\n      // ----------------\n      // gearbox <== f_tlps    for data (slow clock)\n\n      rule rl_data ((! f_tlps.first.sof) && (rg_dwcount != 0));\n\t Vector #(2, AxiStCc) v2 = newVector;\n\t Bit #(128) x = f_tlps.first.data;\n\t v2[0] = AxiStCc {data: { convertDW(x[95:64]), convertDW(x[127:96]) },\n\t\t\t  last: (rg_dwcount <= 2),\n\t\t\t  keep: ((rg_dwcount == 1) ? 2'b01 : 2'b11) };\n\t v2[1] = AxiStCc {data: { convertDW(x[31:0]), convertDW(x[63:32]) },\n\t\t\t  last: (rg_dwcount <= 4),\n\t\t\t  keep: ((rg_dwcount <= 2) ? 2'b00\n\t\t\t\t : ((rg_dwcount == 3) ? 2'b01 : 2'b11)) };\n\t gearbox.enq (v2);\n\t rg_dwcount <= ((rg_dwcount < 4) ? 0 : (rg_dwcount - 4));\n\t f_tlps.deq;\n      endrule\n\n      // ----------------\n      // Move out of head of gearbox (fast clock)\n\n      rule rl_fastclock;\n\t AxiStCc x = gearbox.first[0];\n\t gearbox.deq;\n\t // do not propagate empty beats\n\t if (x.keep != 0)\n\t   p.put (x);\n      endrule\n\n   endmodule\nendinstance\n\ninstance ConnectableWithClocks #(Put #(AxiStCc), Get #(TLPData #(16)));\n   module mkConnectionWithClocks #(Put #(AxiStCc) p, Get #(TLPData #(16)) g,\n\t\t\t\t   Clock fastClock, Reset fastReset,\n\t\t\t\t   Clock slowClock, Reset slowReset) (Empty);\n      mkConnectionWithClocks (g, p, fastClock, fastReset, slowClock, slowReset);\n   endmodule\nendinstance\n\n// ================================================================\n// Connecting/converting stream AxiRq <== stream TLPData#(16)\n\ninstance ConnectableWithClocks #(Get #(TLPData #(16)), Put #(AxiStRq));\n   module mkConnectionWithClocks #(Get #(TLPData #(16)) g, Put #(AxiStRq) p,\n\t\t\t\t   Clock fastClock, Reset fastReset,\n\t\t\t\t   Clock slowClock, Reset slowReset) (Empty);\n\n      // Data path: p <- gearbox_1_2 <- f_tlps <- g\n\n      FIFOF #(TLPData #(16)) f_tlps <- mkPipelineFIFOF (clocked_by slowClock, reset_by   slowReset);\n      Gearbox #(2, 1, AxiStRq) gearbox <- mkNto1Gearbox (slowClock, slowReset, fastClock, fastReset);\n\n      Reg #(DWCount)             rg_dwcount <- mkReg (0, clocked_by slowClock, reset_by slowReset);\n      // This stores an extra data word, in the converted Xilinx byte order\n      Reg #(Maybe #(Bit #(32)))  rg_mdw     <- mkRegU (clocked_by slowClock, reset_by slowReset);\n\n      // Record the first and last BE from header\n      // so that we hold the value for the entire packet\n      Reg #(Bit# (4))            rg_first_be <- mkRegU (clocked_by slowClock, reset_by slowReset);\n      Reg #(Bit# (4))            rg_last_be <- mkRegU (clocked_by slowClock, reset_by slowReset);\n\n      // ----------------\n      // Move tlps from g into f_tlps\n      // This step would not be necessary if we could examine the .sof\n      // of g.get tlp without dequeueing.\n      // TODO: is this redundant with rg_dwcount == 0? i.e., does sof <=> (rg_dwcount == 0)?\n\n      rule rl_get_tlps;    // (slow clock)\n\t let tlp <- g.get;\n\t f_tlps.enq (tlp);\n      endrule\n\n      // ----------------\n      // Move header into gearbox (slow clock)\n\n      rule rl_header (rg_mdw matches tagged Invalid &&& f_tlps.first.sof);\n\t Vector #(2, AxiStRq) v2 = newVector;\n\n\t // this returns the data in the Xilinx byte order\n\t match { .rq_desc, .first_be, .last_be, .mdata } = convertTLP16ToRQDescriptor (f_tlps.first);\n\t rg_dwcount  <= ((rq_desc.reqtype == MEMORY_WRITE) ? rq_desc.dwcount : 0);\n\t rg_mdw      <= mdata;\n\t rg_first_be <= first_be;\n\t rg_last_be  <= last_be;\n\n\t v2[0] = AxiStRq {data: pack (rq_desc) [63:0],\n\t\t\t  last: False,\n\t\t\t  keep: 2'b11,\n\t\t\t  first_be: first_be,\n\t\t\t  last_be: last_be };\n\t v2[1] = AxiStRq {data: pack (rq_desc) [127:64],\n\t\t\t  last: f_tlps.first.eof && !isValid(mdata),\n\t\t\t  keep: 2'b11,\n\t\t\t  first_be: first_be,\n\t\t\t  last_be: last_be };\n\t gearbox.enq (v2);\n\t f_tlps.deq;\n      endrule\n\n      // ----------------\n      // Move write-payload into gearbox (slow clock)\n\n      // rg_mdw contains last DW\n      rule rl_data_a (rg_mdw matches tagged Valid .dw &&& (rg_dwcount == 1));\n\t Vector #(2, AxiStRq) v2 = newVector;\n\t v2[0] = AxiStRq {data: { 32'b0, dw },\n\t\t\t  last: True,\n\t\t\t  keep: 2'b01,\n\t\t\t  first_be: rg_first_be,\n\t\t\t  last_be: rg_last_be };\n\t v2[1] = AxiStRq {data: 0,\n\t\t\t  last: True,\n\t\t\t  keep: 2'b00,\n\t\t\t  first_be: rg_first_be,\n\t\t\t  last_be: rg_last_be };\n\t gearbox.enq (v2);\n\t rg_dwcount <= 0;\n\t rg_mdw <= tagged Invalid;\n      endrule\n\n      // rg_mdw contains DW, and there are more DWs\n      rule rl_data_b (rg_mdw matches tagged Valid .dw &&& (rg_dwcount != 1));\n\t Vector #(2, AxiStRq) v2 = newVector;\n\t Bit #(128) x = f_tlps.first.data;\n\t v2[0] = AxiStRq {data: { convertDW(x[127:96]), dw },\n\t\t\t  last: (rg_dwcount == 2),\n\t\t\t  keep: 2'b11,\n\t\t\t  first_be: rg_first_be,\n\t\t\t  last_be: rg_last_be };\n\t v2[1] = AxiStRq {data: { convertDW(x[63:32]), convertDW(x[95:64]) },\n\t\t\t  last: (rg_dwcount <= 4),\n\t\t\t  keep: ((rg_dwcount == 2) ? 2'b00\n\t\t\t\t : ((rg_dwcount == 3) ? 2'b01 : 2'b11)),\n\t\t\t  first_be: rg_first_be,\n\t\t\t  last_be: rg_last_be };\n\t gearbox.enq (v2);\n\t if (rg_dwcount <= 4) begin\n\t   rg_dwcount <= 0;\n\t   rg_mdw <= tagged Invalid;\n\t end\n         else begin\n\t   rg_dwcount <= rg_dwcount - 4;\n\t   rg_mdw <= tagged Valid convertDW(x [31:0]);\n         end\n\t f_tlps.deq;\n      endrule\n\n      // rg_mdw is Invalid, and there are more DWs\n      rule rl_data_c (rg_mdw matches tagged Invalid &&& (! f_tlps.first.sof)\n                      &&& (rg_dwcount != 0));\n\t Vector #(2, AxiStRq) v2 = newVector;\n\t Bit #(128) x = f_tlps.first.data;\n\t v2[0] = AxiStRq {data: { convertDW(x[95:64]), convertDW(x[127:96]) },\n\t\t\t  last: (rg_dwcount <= 2),\n\t\t\t  keep: ((rg_dwcount == 1) ? 2'b01 : 2'b11),\n\t\t\t  first_be: rg_first_be,\n\t\t\t  last_be: rg_last_be };\n\t v2[1] = AxiStRq {data: { convertDW(x[31:0]), convertDW(x[63:32]) },\n\t\t\t  last: (rg_dwcount <= 4),\n\t\t\t  keep: ((rg_dwcount <= 2) ? 2'b00\n\t\t\t\t : ((rg_dwcount == 3) ? 2'b01 : 2'b11)),\n\t\t\t  first_be: rg_first_be,\n\t\t\t  last_be: rg_last_be };\n\t gearbox.enq (v2);\n\t rg_dwcount <= ((rg_dwcount < 4) ? 0 : (rg_dwcount - 4));\n\t f_tlps.deq;\n      endrule\n\n      // ----------------\n      // Move out of head of gearbox (fast clock)\n\n      rule rl_fastclock;\n\t AxiStRq x = gearbox.first[0];\n\t gearbox.deq;\n\t // do not propagate empty beats\n\t if (x.keep != 0)\n\t   p.put (x);\n      endrule\n\n   endmodule\nendinstance\n\ninstance ConnectableWithClocks #(Put #(AxiStRq), Get #(TLPData #(16)));\n   module mkConnectionWithClocks #( Put #(AxiStRq) p, Get #(TLPData #(16)) g,\n\t\t\t\t   Clock fastClock, Reset fastReset,\n\t\t\t\t   Clock slowClock, Reset slowReset) (Empty);\n      mkConnectionWithClocks (g, p, fastClock, fastReset, slowClock, slowReset);\n   endmodule\nendinstance\n\n// ================================================================\n// Connecting/converting stream AxiRc ==> stream TLPData#(16)\n\ninstance ConnectableWithClocks #(Get #(AxiStRc), Put #(TLPData #(16)));\n   module mkConnectionWithClocks #(Get #(AxiStRc) g, Put #(TLPData #(16)) p,\n\t\t\t\t   Clock fastClock, Reset fastReset,\n\t\t\t\t   Clock slowClock, Reset slowReset) (Empty);\n\n      // Data path: g -> gearbox_1_2 -> p\n\n      Reg #(Bool) rg_even_enq     <- mkReg (True, clocked_by fastClock, reset_by fastReset);\n      Reg #(Bool) rg_pad_odd_tail <- mkReg (False, clocked_by fastClock, reset_by fastReset);\n\n      // Buffer incoming messages for timing\n      FIFO #(AxiStRc) in_buf <- mkFIFO(clocked_by fastClock, reset_by fastReset);\n      mkConnection(g, toPut(in_buf));\n      let g_buf = toGet(in_buf);\n\n      Gearbox #(1, 2, AxiStRc) gearbox <- mk1toNGearbox (fastClock, fastReset, slowClock, slowReset);\n\n      // ----------------\n      // g -> gearbox\n\n      // If eop happens on an even enq, we insert a dummy odd enq, for two reasons:\n      // (1) sop is always an even enq, so it is in element [0] of the gearbox output\n      // (2) to avoid deadlock/delay: the gearbox output does not show\n      //       up until it has received both an even and an odd enq\n\n      // Incoming AxiStRc: g ==> gearbox (fast clock)\n      rule rl_g_to_gearbox (! rg_pad_odd_tail);\n\t let rc <- g_buf.get;\n\t // Assert: rc.sop => rg_even_enq\n\t Vector #(1, AxiStRc) v1 = replicate (rc);\n\t gearbox.enq (v1);\n\t rg_pad_odd_tail <= (rc.eop && rg_even_enq);\n\t rg_even_enq     <= ! rg_even_enq;\n      endrule\n\n      rule rl_g_to_gearbox_pad_odd_tail (rg_pad_odd_tail);\n\t AxiStRc rc = unpack (0);\n\t Vector #(1, AxiStRc) v1 = replicate (rc);\n\t gearbox.enq (v1);\n\t rg_pad_odd_tail <= False;\n\t rg_even_enq     <= True;\n      endrule\n\n      // ----------------\n      // gearbox -> f_cq (slow clock)\n\n      Reg #(DWCount)     rg_dwcount <- mkRegU (clocked_by slowClock, reset_by slowReset);\n\n      // 3DW Header + 1DW data: gearbox ==> p\n      rule rl_header (gearbox.first [0].sop);\n\t RCDescriptor rc_desc = unpack ({ gearbox.first [1].data [31:0], gearbox.first [0].data });\n\t Bit #(32) data = gearbox.first [1].data [63:32];\n\n\t // this takes the data in Xilinx byte order and converts it\n\t TLPData #(16) tlp16 = convertRCDescriptorToTLP16 (rc_desc, data);\n\t p.put (tlp16);\n\n\t rg_dwcount <= (rc_desc.dwcount == 0) ? 0 : rc_desc.dwcount - 1;\n\t gearbox.deq;\n      endrule\n\n      // Data payload: gearbox => p\n      rule rl_data_a ((! (gearbox.first [0].sop)) && (rg_dwcount != 0));\n\t Bit #(16) be16;\n\t case (rg_dwcount)\n\t    1: be16 = 16'hF000;\n\t    2: be16 = 16'hFF00;\n\t    3: be16 = 16'hFFF0;\n\t    default: be16 = 16'hFFFF;\n\t endcase\n\t Vector#(4, Bit#(32)) data_vec;\n\t data_vec[3] = convertDW(gearbox.first [0].data [31:0]);\n\t data_vec[2] = convertDW(gearbox.first [0].data [63:32]);\n\t data_vec[1] = convertDW(gearbox.first [1].data [31:0]);\n\t data_vec[0] = convertDW(gearbox.first [1].data [63:32]);\n\t TLPData #(16) tlp16 = TLPData {sof: False,\n\t\t\t\t\teof: (rg_dwcount <= 4),\n\t\t\t\t\thit: 0,\n\t\t\t\t\tbe: be16,\n\t\t\t\t\tdata: pack(data_vec)};\n\t p.put (tlp16);\n\t gearbox.deq;\n\t rg_dwcount <= ((rg_dwcount < 4) ? 0 : rg_dwcount - 4);\n      endrule\n\n   endmodule\nendinstance\n\ninstance ConnectableWithClocks #(Put #(TLPData #(16)), Get #(AxiStRc));\n   module mkConnectionWithClocks #(Put #(TLPData #(16)) p, Get #(AxiStRc) g,\n\t\t\t\t   Clock fastClock, Reset fastReset,\n\t\t\t\t   Clock slowClock, Reset slowReset) (Empty);\n      mkConnectionWithClocks (g, p, fastClock, fastReset, slowClock, slowReset);\n   endmodule\nendinstance\n\n// ================================================================\n// Tie-offs for unused interfaces\n\ninstance TieOff #(PCIE3_INT_V7);\n   module mkTieOff #(PCIE3_INT_V7 ifc) (Empty);\n      rule tie_off_inputs;\n\t ifc.int_vect (0);\n\t ifc.pending (0);\n      endrule\n   endmodule\nendinstance\n\ninstance TieOff #(PCIE3_INT_MSIX_V7);\n   module mkTieOff #(PCIE3_INT_MSIX_V7 ifc) (Empty);\n      rule tie_off_inputs;\n\t ifc.valid (0);\n\t ifc.data (0);\n\t ifc.address (0);\n      endrule\n   endmodule\nendinstance\n\n// ================================================================\n// PCIE3 AXI-Stream Descriptor Formats\n\ntypedef struct {\n   ReservedZero#(1)         r1;\n   TLPAttrIDBasedOrdering   idbased;\n   TLPAttrRelaxedOrdering   relaxed;\n   TLPAttrNoSnoop           nosnoop;\n   TLPTrafficClass          tclass;\n   BARAperture              aperture;\n   BARID                    barid;\n   TargetFunction           targetfn;\n   TLPTag                   tag;\n   PciId                    reqid;\n   ReservedZero#(1)         r2;\n   RequestType              reqtype;\n   DWCount                  dwcount;\n   DWAddress64              address;\n   TLPAddressType           addrtype;\n} CQDescriptor deriving (Bits, Eq);\n\ntypedef struct {\n   Bool                     forceecrc;\n   TLPAttrIDBasedOrdering   idbased;\n   TLPAttrRelaxedOrdering   relaxed;\n   TLPAttrNoSnoop           nosnoop;\n   TLPTrafficClass          tclass;\n   Bool                     compliden;\n   PciId                    complid;\n   TLPTag                   tag;\n   PciId                    reqid;\n   ReservedZero#(1)         r1;\n   TLPPoison                poisoned;\n   TLPCompletionStatus      status;\n   DWCount                  dwcount;\n   ReservedZero#(2)         r2;\n   Bool                     lockedcmpl;\n   ByteCount                bytecount;\n   ReservedZero#(6)         r3;\n   TLPAddressType           addrtype;\n   ReservedZero#(1)         r4;\n   TLPLowerAddr             loweraddr;\n} CCDescriptor deriving (Bits, Eq);\n\ntypedef struct {\n   Bool                     forceecrc;\n   TLPAttrIDBasedOrdering   idbased;\n   TLPAttrRelaxedOrdering   relaxed;\n   TLPAttrNoSnoop           nosnoop;\n   TLPTrafficClass          tclass;\n   Bool                     reqiden;\n   PciId                    complid;\n   TLPTag                   tag;\n   PciId                    reqid;\n   TLPPoison                poisoned;\n   RequestType              reqtype;\n   DWCount                  dwcount;\n   DWAddress64              address;\n   TLPAddressType           addrtype;\n} RQDescriptor deriving (Bits, Eq);\n\ntypedef struct {\n   ReservedZero#(1)         r1;\n   TLPAttrIDBasedOrdering   idbased;\n   TLPAttrRelaxedOrdering   relaxed;\n   TLPAttrNoSnoop           nosnoop;\n   TLPTrafficClass          tclass;\n   ReservedZero#(1)         r2;\n   PciId                    complid;\n   TLPTag                   tag;\n   PciId                    reqid;\n   ReservedZero#(1)         r3;\n   TLPPoison                poisoned;\n   TLPCompletionStatus      status;\n   DWCount                  dwcount;\n   ReservedZero#(1)         r4;\n   Bool                     reqcompleted;\n   Bool                     lockedcmpl;\n   ByteCount                bytecount;\n   ErrorCode                errcode;\n   Bit#(12)                 loweraddr;\n} RCDescriptor deriving (Bits, Eq);\n\n// -------------------------\n\n// Conversion functions for PCIE3 AXI-Stream descriptors.  One thing to note\n// here is that the TLPData#(n).be field is only ever set in the logic that\n// utilizes these functions.  It was a required field for the original PCIE\n// design by Xilinx, but is no longer used for PCIE3.  Therefore, the .be\n// field will not be assigned in the TLPData#(n) type for traffic going to\n// the DMA and CSR blocks.\n\nfunction TLPData#(16) convertCQDescriptorToTLP16(CQDescriptor desc, Bit#(32) data, TLPFirstDWBE first, TLPLastDWBE last);\n   TLPMemoryIO3DWHeader header = defaultValue;\n   header.format     = tpl_1(convertCQReqTypeToTLPFmtType(desc.reqtype));\n   header.pkttype    = tpl_2(convertCQReqTypeToTLPFmtType(desc.reqtype));\n   header.tclass     = desc.tclass;\n   header.relaxed    = desc.relaxed;\n   header.nosnoop    = desc.nosnoop;\n   header.length     = (desc.dwcount == 1024) ? 0 : truncate(desc.dwcount);\n   header.reqid      = desc.reqid;\n   header.tag        = desc.tag;\n   header.lastbe     = last;\n   header.firstbe    = first;\n   header.addr       = truncate(desc.address);\n   header.data       = convertDW(data);\n\n   Bool is3DW = isReadReqType(desc.reqtype);\n   Bool is3Or4DW = isReadReqType(desc.reqtype) || (desc.dwcount == 1);\n\n   TLPData#(16) retval = defaultValue;\n   retval.sof   = True;\n   retval.eof   = is3Or4DW;\n   retval.hit   = (1 << pack(desc.barid));\n   retval.data  = pack(header);\n   retval.be    = (is3DW ? 16'hFFF0 : 16'hFFFF);\n\n   return retval;\nendfunction\n\n// this only expects Memory and IO types\nfunction Bool isReadReqType(RequestType t);\n   return ((t == MEMORY_READ) || (t == IO_READ));\nendfunction\n\n// this only expects Memory and IO types\nfunction Tuple2#(TLPPacketFormat,TLPPacketType) convertCQReqTypeToTLPFmtType(RequestType t);\n   case (t)\n     MEMORY_READ : return tuple2(MEM_READ_3DW_NO_DATA, MEMORY_READ_WRITE);\n     MEMORY_WRITE : return tuple2(MEM_WRITE_3DW_DATA, MEMORY_READ_WRITE);\n     IO_READ : return tuple2(MEM_READ_3DW_NO_DATA, IO_REQUEST);\n     IO_WRITE : return tuple2(MEM_WRITE_3DW_DATA, IO_REQUEST);\n     default : return ?;\n   endcase\nendfunction\n\nfunction Tuple2#(CCDescriptor, Bit#(32)) convertTLP16ToCCDescriptor(TLPData#(16) header);\n   TLPCompletionHeader cmplheader = unpack(header.data);\n   CCDescriptor desc = unpack(0);\n   desc.relaxed      = cmplheader.relaxed;\n   desc.nosnoop      = cmplheader.nosnoop;\n   desc.tclass       = cmplheader.tclass;\n   desc.compliden    = False;\n   desc.complid      = cmplheader.cmplid;\n   desc.tag          = cmplheader.tag;\n   desc.reqid        = cmplheader.reqid;\n   desc.poisoned     = cmplheader.poison;\n   desc.status       = cmplheader.cstatus;\n   desc.dwcount      = (cmplheader.length == 0) ? 1024 : zeroExtend(cmplheader.length);\n   desc.lockedcmpl   = False;\n   desc.bytecount    = (cmplheader.bytecount == 0) ? 4096 : zeroExtend(cmplheader.bytecount);\n   desc.loweraddr    = cmplheader.loweraddr;\n\n   return tuple2(desc, convertDW(cmplheader.data));\nendfunction\n\nfunction TLPData#(16) convertRCDescriptorToTLP16(RCDescriptor desc, Bit#(32) data);\n   TLPCompletionHeader header = defaultValue;\n   header.tclass    = desc.tclass;\n   header.relaxed   = desc.relaxed;\n   header.nosnoop   = desc.nosnoop;\n   header.cmplid    = desc.complid;\n   header.tag       = desc.tag;\n   header.reqid     = desc.reqid;\n   header.poison    = desc.poisoned;\n   header.cstatus   = desc.status;\n   header.length    = (desc.dwcount == 1024) ? 0 : truncate(desc.dwcount);\n   header.bytecount = (desc.bytecount == 4096) ? 0 : truncate(desc.bytecount);\n   header.loweraddr = truncate(desc.loweraddr);\n   header.data      = convertDW(data);\n\n   Bool is3DW = (desc.dwcount == 0);\n   Bool is3Or4DW = (desc.dwcount == 0) || (desc.dwcount == 1);\n   TLPData#(16) retval = defaultValue;\n   retval.sof   = True;\n   retval.eof   = is3Or4DW;\n   retval.hit   = 1; // XXX\n   retval.data  = pack(header);\n   retval.be    = (is3DW ? 16'hFFF0 : 16'hFFFF);\n\n   return retval;\nendfunction\n\nfunction Tuple4 #(RQDescriptor,\n\t\t  TLPFirstDWBE,\n\t\t  TLPLastDWBE,\n\t\t  Maybe#(Bit#(32)))\n         convertTLP16ToRQDescriptor (TLPData #(16) header);\n\n   // Note: other than .addr and .data, remaining fields are same for\n   // the two header formats below\n   TLPMemoryIO3DWHeader header3dw = unpack(header.data);\n   TLPMemory4DWHeader   header4dw = unpack(header.data);\n   RQDescriptor desc = unpack(0);\n   Maybe#(Bit#(32)) data = tagged Invalid;\n\n   desc.relaxed      = header4dw.relaxed;\n   desc.nosnoop      = header4dw.nosnoop;\n   desc.tclass       = header4dw.tclass;\n   desc.reqiden      = False;\n   desc.tag          = header4dw.tag;\n   desc.reqid        = header4dw.reqid;\n   desc.poisoned     = header4dw.poison;\n   case(header4dw.format)\n      MEM_READ_3DW_NO_DATA: desc.reqtype = MEMORY_READ;\n      MEM_READ_4DW_NO_DATA: desc.reqtype = MEMORY_READ;\n      MEM_WRITE_3DW_DATA:   desc.reqtype = MEMORY_WRITE;\n      MEM_WRITE_4DW_DATA:   desc.reqtype = MEMORY_WRITE;\n      default:              desc.reqtype = MEMORY_READ;\n   endcase\n   desc.dwcount      = (header4dw.length == 0) ? 1024 : zeroExtend(header4dw.length);\n\n   if (header4dw.format == MEM_WRITE_4DW_DATA || header4dw.format == MEM_READ_4DW_NO_DATA) begin\n      desc.address      = header4dw.addr;\n   end\n   else begin\n      desc.address      = zeroExtend(header3dw.addr);\n      if (header3dw.format == MEM_WRITE_3DW_DATA) begin\n\t data           = tagged Valid convertDW(header3dw.data);\n      end\n   end\n\n   return tuple4 (desc, header4dw.firstbe, header4dw.lastbe, data);\nendfunction\n\n\n// Functions to convert between the byte order inside data words of\n// Xilinx AXI packets and PCIe TLP packets\n\nfunction Bit#(32) convertDW(Bit#(32) dw);\n  Vector#(4, Bit#(8)) bytes = unpack(dw);\n  return pack(reverse(bytes));\nendfunction\n\n// -------------------------\n\n// Buffer to hold at least one maximum size CC packet.\n// Max size = 3 Dword header + 1024 Dwords = 1027 Dwords.\n// At 64-bit beats, a buffer of 514 beats is needed.\n//\nmodule mkCCBuffer(FIFO#(AxiStCc));\n  function Bool isEOF(AxiStCc x) = x.last;\n  (* hide *)\n  let _buf <- mkAXISBuffer(516, isEOF);\n  return _buf;\nendmodule\n\n// Buffer to hold at least one maximum size RQ packet.\n// Max size = 4 Dword header + 256 Dwords = 260 Dwords.\n// At 64-bit beats, a buffer of 130 beats is needed.\n//\nmodule mkRQBuffer(FIFO#(AxiStRq));\n  function Bool isEOF(AxiStRq x) = x.last;\n  (* hide *)\n  let _buf <- mkAXISBuffer(132, isEOF);\n  return _buf;\nendmodule\n\n// The timing is tight through the core module, so we try to reduce the\n// path length with this wrapper that adds a buffer on both the\n// input and output.\nmodule mkAXISBuffer#( Integer depth\n                    , function Bool isEOF(t x) )\n                   (FIFO#(t))\n                   provisos (Bits#(t,tsz), Add#(1, j, tsz));\n\n  (* hide *)\n  FIFO#(t)  _core   <- mkAXISBufferCore(depth, isEOF);\n  FIFO#(t)  in_buf  <- mkFIFO;\n  FIFO#(t)  out_buf <- mkFIFO;\n\n  (* fire_when_enabled *)\n  rule moveIn;\n    _core.enq(in_buf.first);\n    in_buf.deq;\n  endrule\n\n  (* fire_when_enabled *)\n  rule moveOut;\n    out_buf.enq(_core.first);\n    _core.deq;\n  endrule\n\n  method enq(x)  = in_buf.enq(x);\n\n  method first() = out_buf.first;\n  method deq()   = out_buf.deq;\n\n  method Action clear();\n    _core.clear;\n    in_buf.clear;\n    out_buf.clear;\n  endmethod\n\nendmodule\n\nmodule mkAXISBufferCore#( Integer depth\n                        , function Bool isEOF(t x) )\n                       (FIFO#(t))\n                       provisos (Bits#(t,tsz), Add#(1, j, tsz));\n\n  FIFO#(t)      data_buf <- mkSizedBRAMFIFO(depth);\n  FIFOF#(void)  eof_buf  <- mkSizedFIFOF(4);\n\n  Bool has_data = eof_buf.notEmpty;\n\n  method Action enq(t x);\n    data_buf.enq(x);\n    if (isEOF(x))\n      eof_buf.enq(?);\n  endmethod\n\n  method t first() if (has_data) = data_buf.first;\n\n  method Action deq() if (has_data);\n    data_buf.deq;\n    if (isEOF(data_buf.first))\n      eof_buf.deq();\n  endmethod\n\n  method Action clear();\n    data_buf.clear;\n    eof_buf.clear;\n  endmethod\n\nendmodule\n\n// -------------------------\n\nendpackage: XilinxVirtex7PCIE\n"
  },
  {
    "path": "lib/bsv/YUV.bsv",
    "content": "\n// Copyright (c) 2013 Nokia, Inc.\n// Copyright (c) 2013 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\nimport Vector::*;\nimport Arith::*;\n\n// little endian RGB\ntypedef struct {\n    Bit#(8) r;\n    Bit#(8) b;\n    Bit#(8) g;\n} Rgb888 deriving (Bits);\n\ntypedef struct {\n    Bit#(1) vsync;\n    Bit#(1) hsync;\n    Bit#(1) de;\n    pixelType pixel;\n} VideoData#(type pixelType) deriving (Bits);\n\ntypedef struct {\n    Bit#(8) y;\n    Bit#(8) u;\n    Bit#(8) v;\n} Yuv444 deriving (Bits);\n\ntypedef struct {\n    Bit#(8) y1;\n    Bit#(8) u;\n    Bit#(8) y2;\n    Bit#(8) v;\n} Yuv422 deriving (Bits);\n\ntypedef struct {\n    Bit#(8) uv;\n    Bit#(8) yy;\n} Yyuv deriving (Bits);\n\ninterface Rgb888ToYuv422;\n    method Action putRgb888(Rgb888 rgb888);\n    method ActionValue#(Yuv422) getYuv422();\nendinterface\n\nfunction Yuv444 rgbtoyuv(Rgb888 rgb);\n    Bit#(16) y = 77*extend(rgb.r) + 150 * extend(rgb.g) + 29 * extend(rgb.b) + 0;\n    Bit#(16) u = -43*extend(rgb.r) - 85*extend(rgb.g) + 128*extend(rgb.b) + 128;\n    Bit#(16) v = 128*extend(rgb.r) - 107*extend(rgb.g) - 21*extend(rgb.b) + 128;\n    return Yuv444 { y: truncate(y>>8), u: truncate(u >> 8), v: truncate(v >> 8) };\nendfunction\n\ntypedef Vector#(4, Vector#(3, Bit#(16))) Yuv444Intermediates;\n\nfunction Vector#(3, Bit#(n)) rgbToVector(Rgb888 rgb) provisos (Add#(a__, 8, n));\n   Vector#(3, Bit#(n)) vec;\n   vec[0] = zeroExtend(rgb.r);\n   vec[1] = zeroExtend(rgb.g);\n   vec[2] = zeroExtend(rgb.b);\n   return vec;\nendfunction   \nfunction Yuv444 yuv444FromVector(Vector#(3, Bit#(n)) vec) provisos (Add#(a__, 8, n));\n   return Yuv444 { y: truncate(vec[0]), u: truncate(vec[1]), v: truncate(vec[2]) };\nendfunction\n\nfunction Yuv444Intermediates rgbToYuvIntermediates(Rgb888 rgb);\n   Vector#(3, Vector#(4, Bit#(16))) rgbv = replicate(append(rgbToVector(rgb), replicate(1)));\n   Vector#(3, Vector#(4, Bit#(16))) coeffs = replicate(newVector());\n   coeffs[0][0] =  77; coeffs[0][1] =  150; coeffs[0][2] =  29; coeffs[0][3] = 0;\n   coeffs[1][0] = -43; coeffs[1][1] =  -85; coeffs[1][2] = 128; coeffs[1][3] = 128;\n   coeffs[2][0] = 128; coeffs[2][1] = -107; coeffs[2][2] = -21; coeffs[2][3] = 128;\n   return transpose(map(uncurry(vmul), zip(rgbv, coeffs)));\nendfunction\n\nfunction Yuv444 yuvIntermediatesToYuv444(Yuv444Intermediates w);\n   Vector#(3, Bit#(16)) v0 = vadd(w[0], w[1]);\n   Vector#(3, Bit#(16)) v1 = vadd(w[2], w[3]);\n   return yuv444FromVector(vrshift(vadd(vadd(w[0], w[1]), vadd(w[2], w[3])), 8));\nendfunction\n\nfunction Yuv422 yuv444toyuv422(Yuv444 yuv0, Yuv444 yuv1);\n    Bit#(9) u = (extend(yuv0.u) + extend(yuv1.u)) >> 1;\n    Bit#(9) v = (extend(yuv0.u) + extend(yuv1.v)) >> 1;\n    return Yuv422 { y1: yuv0.y, u: truncate(u), y2: yuv1.y, v: truncate(v) };\nendfunction\n"
  },
  {
    "path": "lib/cpp/connectal_conv.cpp",
    "content": "// Copyright (c) 2015 The Connectal Project\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n#include \"ConvIndication.h\"\n#include \"ConvRequest.h\"\n#include \"dmaManager.h\"\n#include \"connectal_conv.h\"\n\n#define COUNTER_INTERVAL 100000\n#define MIN_XFER 8\n\nstatic ConvRequestProxy *convRequest;\nstatic DmaManager *dma;\nstatic sem_t outputp_sem;\n\nclass ConvIndication : public ConvIndicationWrapper\n{\n    ParamStruct *param;\npublic:\n    void outputp(uint32_t addr, float v) {\n        if (param->elementSize_ == sizeof(float))\n            *(float *)(param->basePtr + addr) = v;\n        else\n            *(double *)(param->basePtr + addr) = v;\n        sem_post(&outputp_sem);\n    }\n    ConvIndication(unsigned int id, ParamStruct *p) : ConvIndicationWrapper(id), param(p) {}\n};\nstatic ConvIndication *indication;\n\nstatic void forward_kernel_hardware(ParamStruct *param, uint32_t p_limit,\n     uint32_t q_limit, float temp, uint32_t bpx, uint32_t wpx, uint32_t outputp)\n{\n    static int once = 1;\n    if (once) {\n        once = 0;\nprintf(\"[%s:%d] create proxy\\n\", __FUNCTION__, __LINE__);\n        indication = new ConvIndication(IfcNames_ConvIndicationH2S, param);\n        convRequest = new ConvRequestProxy(IfcNames_ConvRequestS2H);\n        dma = platformInit();\n    }\n    if (param->objectId_ == -1) {\n        param->objectId_ = dma->reference(param->portalFd_);\n        ConnectalParamType hparam;\n        hparam.bottom_hw = param->conv_in_height_ * param->conv_in_width_ * param->elementSize_;\n        hparam.kernel_hw = param->kernel_h_ * param->kernel_w_ * param->elementSize_;\n        hparam.in_group_size = param->conv_in_channels_ / param->group_;\n        hparam.baseSize = param->elementSize_;\n        hparam.conv_in_width = param->conv_in_width_ * param->elementSize_;\n        hparam.kernel_w = param->kernel_w_ * param->elementSize_;\n        hparam.objectId = param->objectId_;\n        convRequest->init(hparam);\n    }\n    int len = q_limit* param->elementSize_;\n    int alen = ((len + MIN_XFER - 1) / MIN_XFER) * MIN_XFER;\n    convRequest->forward_kernel(p_limit, alen, alen != len, temp, bpx, wpx, outputp);\n    sem_wait(&outputp_sem);\n}\n\n#define MIN(A,B) (((int)(A) < (int)(B)) ? (A) : (B))\n#define MAX(A,B) (((int)(A) > (int)(B)) ? (A) : (B))\ntemplate <typename Dtype>\nvoid forward_kernel(const ParamType<Dtype> *param, int p_limit, int q_limit, float temp,\n    CPtr bpx, CPtr wpx, CPtr outputp, int run_hardware)\n{\n  int bottom_hw = param->conv_in_height_ * param->conv_in_width_ * param->elementSize_;\n  int kernel_hw = param->kernel_h_ * param->kernel_w_ * param->elementSize_;\n  int in_group_size = param->conv_in_channels_ / param->group_;\n  // for each 'in_group', add contribution into convolution\n  for (int k = 0; k < in_group_size; k++) {\n    CPtr bpk = bpx, wpk = wpx;\n    // Calculate single 2D filter convolution\n    for (int p = 0; p < p_limit; p++) {\n      CPtr bp = bpk, wp = wpk;\n      for (int q = 0; q < q_limit; q++) {\n        temp += *CACCESS(bp) * *CACCESS(wp);\n        bp += param->elementSize_;\n        wp += param->elementSize_;\n      }\n      bpk += param->conv_in_width_ * param->elementSize_;\n      wpk += param->kernel_w_ * param->elementSize_;\n    }\n    bpx += bottom_hw;\n    wpx += kernel_hw;\n  }\n  // Write convolution result into output (image, channel, y, x)\n  if (run_hardware) {\n     if (*CACCESS(outputp) != temp)\n         printf(\"[%s:%d] [%lx] hardware %f software %f\\n\", __FUNCTION__, __LINE__, outputp, (double)*CACCESS(outputp), (double)temp);\n  }\n  else\n  *CACCESS(outputp) = temp;\n}\ntemplate <typename Dtype>\nvoid ParamType<Dtype>::forward_process(void)\n{\nParamType<Dtype> *param = this;\n  int out_group_size = conv_out_channels_ / group_;\n  int in_group_size = conv_in_channels_ / group_;\n  int bottom_hw = in_group_size * conv_in_height_ * conv_in_width_ * elementSize_;\n  int kernel_hw = in_group_size * kernel_h_ * kernel_w_ * elementSize_;\n  int output_hw = out_group_size * height_out_ * width_out_ * elementSize_;\n  static int counter = 0;\n  // For each input, ...\n  CPtr bottom_data = bottom[0];\n  CPtr top_data = top[0];\n  for (int imageind_unused = 0; imageind_unused < bottom_size; ++imageind_unused) {\n    // For each image in input batch\n    for (int nunused = 0; nunused < num_; ++nunused) {\n      CPtr biasptr = bias;\n      // if group_ > 1, restrict connectivity to a subset of inputs\n      CPtr wp_base = weight;\n      for (int g = 0; g < group_; ++g) {\n        CPtr outputp = top_data;\n        CPtr wp_item = wp_base;\n        // for each 'out_group', calculate convolution over input data\n        for (int ounused = 0; ounused < out_group_size; ounused++) {\n          CPtr bpg = bottom_data;\n          const Dtype bias_val = bias ? *CACCESS(biasptr) : 0;\n          if (bias)\n              biasptr += elementSize_;\n          // Scan over source 2D input data\n          for (int y = 0; y < height_out_; y++) {\n            CPtr bpx = bpg;\n            for (int x = 0; x < width_out_; x++) {\n              int run_hardware = (counter-- <= 0);\n              int p_limit = MIN(kernel_h_ - pad_h_, conv_in_height_ - y * stride_h_);\n              int q_limit = MIN(kernel_w_ - pad_w_, conv_in_width_ - x * stride_w_);\n              if (run_hardware) {\n                  forward_kernel_hardware(this, p_limit, q_limit, bias_val, bpx, wp_item, outputp);\n                  counter = COUNTER_INTERVAL;\n              }\n              forward_kernel<Dtype>(this, p_limit, q_limit, bias_val, bpx, wp_item, outputp, run_hardware);\n              outputp += elementSize_;\n              bpx += stride_w_ * elementSize_;\n            }\n            bpg += conv_in_width_ * stride_h_ * elementSize_;\n          }\n          wp_item += kernel_hw;\n        }\n        bottom_data += bottom_hw;\n        top_data += output_hw;\n        wp_base += weight_offset_ * elementSize_;\n      }\n    }\n  }\n}\ntemplate <typename Dtype>\nvoid backward_bias(const ParamType<Dtype> *param, CPtr tptr)\n{\n  int output_hw = param->height_out_ * param->width_out_ * param->elementSize_;\n  for (int j = 0; j < param->num_output_ * param->elementSize_; j += param->elementSize_) {\n    Dtype temp = 0;\n    for (int i = 0; i < output_hw; i += param->elementSize_) {\n      temp += *CACCESS(tptr) * *CACCESS(param->bias_multiplier_ + i);\n      tptr += param->elementSize_;\n    }\n    *CACCESS(param->bias_diff + j) += temp;\n  }\n}\ntemplate <typename Dtype>\nvoid backward_kernel(const ParamType<Dtype> *param, int pad_x, int pad_y, int gchan, int wchan, Dtype chain_grad, CPtr bottom_bp, CPtr bottom_diff_bp)\n{\n  int p_start = MAX(0, pad_y);\n  int p_limit = MIN(param->kernel_h_ * param->elementSize_, param->conv_in_height_ * param->elementSize_ + pad_y);\n  int q_start = MAX(0, pad_x);\n  int q_limit = MIN(param->kernel_w_ * param->elementSize_, param->conv_in_width_ * param->elementSize_ + pad_x);\n  for (int p = p_start; p < p_limit; p += param->elementSize_) {\n    for (int q = q_start; q < q_limit; q += param->elementSize_) {\n      int belement = gchan + p * param->conv_in_width_ + q;\n      int welement = wchan + p * param->kernel_w_ + q;\n      // gradient w.r.t. weight. Note that we will accumulate diffs.\n      if (param->weight_diff)\n        *CACCESS(param->weight_diff + welement) += *CACCESS(bottom_bp + belement) * chain_grad;\n      // gradient w.r.t. bottom data, if necessary.\n      if (bottom_diff_bp)\n        *CACCESS(bottom_diff_bp + belement) += *CACCESS(param->weight + welement) * chain_grad;\n    }\n  }\n}\ntemplate <typename Dtype>\nvoid ParamType<Dtype>::backward_process(void)\n{\nParamType<Dtype> *param = this;\n  int out_group_size = conv_out_channels_ / group_;\n  int in_group_size = conv_in_channels_ / group_;\n  int bottom_hw = conv_in_height_ * conv_in_width_ * elementSize_;\n  int kernel_hw = kernel_h_ * kernel_w_ * elementSize_;\n  int output_hw = height_out_ * width_out_ * elementSize_;\n  int usable_height = conv_in_height_ + 2 * pad_h_ - kernel_h_;\n  int usable_width = conv_in_width_ + 2 * pad_w_ - kernel_w_;\n  memset(CACCESS(zero_region), 0, zero_region_len);\n  // For all images\n  CPtr toff = top_diff[0];\n  CPtr bottom_ptr = bottom[0];\n  CPtr bottom_diff_ptr = bottom_diff[0];\n  for (int imageind_unused = 0; imageind_unused < top_size; ++imageind_unused) {\n    int gbase = 0;\n    for (int n = 0; n < num_; ++n) {\n      // Bias gradient, if necessary.\n      if (bias_diff)\n        backward_bias<Dtype>(this, toff);\n      int wbase = 0;\n      for (int g = 0; g < group_; ++g) {\n        int wchan = wbase;\n        for (int outindex = 0; outindex < out_group_size; ++outindex) {\n          int gchan = gbase;\n          for (int cchan = 0; cchan < in_group_size; ++cchan) {\n            for (int y = 0; y <= usable_height; y += stride_h_){\n              for (int x = 0; x <= usable_width; x += stride_w_) {\n                Dtype chain_grad = *CACCESS(toff + ((y * (usable_width + stride_w_) / stride_h_ + x) / stride_w_) * elementSize_);\n                int pad_x = (pad_w_ - x) * elementSize_;\n                int pad_y = (pad_h_ - y) * elementSize_;\n                if (chain_grad != 0.0)\n                    backward_kernel<Dtype>(this, pad_x, pad_y,\n                     gchan - pad_y * conv_in_width_ - pad_x, wchan, chain_grad, bottom_ptr, bottom_diff_ptr);\n              }\n            }\n            wchan += kernel_hw;\n            gchan += bottom_hw;\n          }\n          toff += output_hw;\n        }\n        gbase += in_group_size * bottom_hw;\n        wbase += weight_offset_ * elementSize_;\n      }\n    }\n    bottom_ptr += num_ * in_group_size * bottom_hw;\n    bottom_diff_ptr += num_ * in_group_size * bottom_hw;\n  }\n}\n\nextern \"C\" void *alloc_connectal_conv(int size)\n{\n    if (size == sizeof(float))\n        return new ParamType<float>(size);\n    else\n        return new ParamType<double>(size);\n}\nextern \"C\" void *alloc_portalMem(size_t size, int cached, int *fdptr)\n{\n    int fd = portalAlloc(size, cached);\n    if (fdptr)\n        *fdptr = fd;\n    return portalMmap(fd, size);\n}\n//int portalCacheFlush(int fd, void *__p, long size, int flush)\n"
  },
  {
    "path": "lib/cpp/connectal_conv.h",
    "content": "// Copyright (c) 2015 The Connectal Project\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\n#ifndef __CONNECTAL_CONV_H__\n#define __CONNECTAL_CONV_H__\n#include <stdlib.h>\n#include <dlfcn.h>\n\n#define CACCESS(A) ((Dtype *)(param->basePtr + (A)))\ntypedef unsigned long CPtr;\nclass ParamStruct {\npublic:\n    volatile uint8_t *basePtr;\n    CPtr *bottom;\n    CPtr *top_diff;\n    CPtr *bottom_diff;\n    CPtr *top;\n    CPtr bias_multiplier_;\n    CPtr weight;\n    CPtr bias;\n    CPtr weight_diff;\n    CPtr bias_diff;\n    CPtr zero_region;\n    int zero_region_len;\n    int top_size;\n    int bottom_size;\n    int weight_diff_count;\n    int num_;\n    int num_output_;\n    int group_;\n    int height_out_, width_out_;\n    int kernel_h_, kernel_w_;\n    int conv_in_height_, conv_in_width_;\n    int conv_in_channels_, conv_out_channels_;\n    int weight_offset_;\n    int pad_h_, pad_w_;\n    int stride_h_, stride_w_;\n    int portalFd_;\n    int propdone_;\n    int objectId_;\n    int elementSize_;\n    ParamStruct(): bottom(NULL), top_diff(NULL), bottom_diff(NULL), top(NULL),\n        bias_multiplier_(0), weight(0), bias(0), weight_diff(0), bias_diff(0),\n        zero_region(0), zero_region_len(0),\n        top_size(0), bottom_size(0), weight_diff_count(0),\n        num_(0), num_output_(0), group_(0), height_out_(0), width_out_(0),\n        kernel_h_(0), kernel_w_(0), conv_in_height_(0), conv_in_width_(0),\n        conv_in_channels_(0), conv_out_channels_(0),\n        weight_offset_(0), pad_h_(0), pad_w_(0),\n        stride_h_(0), stride_w_(0), portalFd_(-1), propdone_(0), objectId_(-1),\n        elementSize_(0)\n        { }\n};\n\ntemplate <typename Dtype>\nclass ParamType: public ParamStruct {\npublic:\n    ParamType(int size) {\n        elementSize_ = size;\n    }\n    virtual void forward_process(void);\n    virtual void backward_process(void);\n};\nclass ConnectalMemory {\n public:\n  ConnectalMemory()\n      : buffer_ptr_(NULL), cpu_ptr_(NULL), size_(0), head_(UNINITIALIZED),\n        own_cpu_data_(false), controlFd_(-1) {}\n  explicit ConnectalMemory(size_t size)\n      : buffer_ptr_(NULL), cpu_ptr_(NULL), size_(size), head_(UNINITIALIZED),\n        own_cpu_data_(false), controlFd_(-1) {}\n  ~ConnectalMemory();\n  const void* cpu_data();\n  void set_cpu_data(void* data);\n  const void* gpu_data() {\n      printf(\"[%s:%d]\\n\", __FUNCTION__, __LINE__);\n      exit(-1);\n      return NULL;\n  }\n  void* mutable_cpu_data();\n  void* mutable_gpu_data() {\n      printf(\"[%s:%d]\\n\", __FUNCTION__, __LINE__);\n      exit(-1);\n      return NULL;\n  }\n  enum ConnectalHead { UNINITIALIZED, HEAD_AT_CPU, SYNCED };\n  ConnectalHead head() { return head_; }\n  size_t size() { return size_; }\n\n private:\n  void to_cpu();\n  void to_gpu();\n  void* buffer_ptr_;\n  void* cpu_ptr_;\n  size_t size_;\n  ConnectalHead head_;\n  bool own_cpu_data_;\n  int  controlFd_;\nprivate:\n  // Disable the copy and assignment operator for a class.\n  ConnectalMemory(const ConnectalMemory&);\n  ConnectalMemory& operator=(const ConnectalMemory&);\n};  // class ConnectalMemory\nvoid init_connectal_conv_library(int size);\nvoid *connectal_conv_library_param(int size);\nvoid *alloc_portal_memory(size_t size, int cached, int *fdptr);\n\n#ifdef DECLARE_CONNECTAL_CONV\ntypedef void *(*ALLOCPARAM)(int size);\ntypedef void *(*ALLOCMEM)(size_t size, int cached, int *fdptr);\nstatic ALLOCPARAM creatme;\nstatic ALLOCMEM pAlloc;\nvoid init_connectal_conv_library()\n{\n    static void *handle;\n    if (!handle) {\n        char *libname = getenv(\"CONNECTAL_CONV_LIBRARY\");\n        if (!libname) {\n            printf(\"%s: The environment variable CONNECTAL_CONV_LIBRARY must contain the filename of the shared library for connectal conv support\\n\", __FUNCTION__);\n            exit(-1);\n        }\n        printf(\"%s: libname is %s\\n\", __FUNCTION__, libname);\n        handle = dlopen(libname, RTLD_NOW);\n        if (handle) {\n            creatme = (ALLOCPARAM)dlsym(handle,\"alloc_connectal_conv\");\n            pAlloc = (ALLOCMEM)dlsym(handle,\"alloc_portalMem\");\n        }\n        else {\n           printf(\"%s: dlopen(%s) failed, %s\", __FUNCTION__, libname, dlerror());\n           exit(-1);\n        }\n        if (!creatme || !pAlloc) {\n           printf(\"%s: dlsym('alloc_connectal_conv') failed, %s\", __FUNCTION__, dlerror());\n           exit(-1);\n        }\n    }\n}\nvoid *connectal_conv_library_param(int size)\n{\n    init_connectal_conv_library();\n    return creatme(size);\n}\nConnectalMemory::~ConnectalMemory() {\n  if (cpu_ptr_ && own_cpu_data_) {\n    free(buffer_ptr_);\n    buffer_ptr_ = NULL;\n  }\n}\n\ninline void ConnectalMemory::to_cpu() {\n  switch (head_) {\n  case UNINITIALIZED:\n    buffer_ptr_ = malloc(size_);\n    cpu_ptr_ = buffer_ptr_;\n    memset(cpu_ptr_, 0, size_);\n    head_ = HEAD_AT_CPU;\n    own_cpu_data_ = true;\n    break;\n  case HEAD_AT_CPU:\n  case SYNCED:\n    break;\n  }\n}\nconst void* ConnectalMemory::cpu_data() {\n  to_cpu();\n  return (const void*)cpu_ptr_;\n}\nvoid ConnectalMemory::set_cpu_data(void* data) {\n  CHECK(data);\n//printf(\"[%s:%d] prev %p new %p\\n\", __FUNCTION__, __LINE__, cpu_ptr_, data);\n  if (buffer_ptr_)\n    memcpy(data, buffer_ptr_, size_);\n  if (own_cpu_data_) {\n    free(buffer_ptr_);\n    buffer_ptr_ = NULL;\n    //close(controlFd_);\n  }\n  cpu_ptr_ = data;\n  head_ = HEAD_AT_CPU;\n  own_cpu_data_ = false;\n}\nvoid* ConnectalMemory::mutable_cpu_data() {\n  to_cpu();\n  head_ = HEAD_AT_CPU;\n  return cpu_ptr_;\n}\nvoid *alloc_portal_memory(size_t size, int cached, int *fdptr)\n{\n    init_connectal_conv_library();\n    return pAlloc(size, cached, fdptr);\n}\n#endif\n#endif // __CONNECTAL_CONV_H__\n"
  },
  {
    "path": "lib/cpp/connectal_convmm.cpp",
    "content": "// Copyright (c) 2015 The Connectal Project\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n#include <stdio.h>\n#include <string.h>\n#include <cblas.h>\n#include \"connectal_conv.h\"\n\ntemplate <typename Dtype>\nvoid ParamType<Dtype>::im2col_cpu(const Dtype* data_im) {\n  int height_col = (conv_in_height_ + 2 * pad_h_ - kernel_h_) / stride_h_ + 1;\n  int width_col = (conv_in_width_ + 2 * pad_w_ - kernel_w_) / stride_w_ + 1;\n  int channels_col = conv_in_channels_ * kernel_h_ * kernel_w_;\n  for (int c = 0; c < channels_col; ++c) {\n    int w_offset = c % kernel_w_;\n    int h_offset = (c / kernel_w_) % kernel_h_;\n    int c_im = c / kernel_h_ / kernel_w_;\n    for (int h = 0; h < height_col; ++h) {\n      for (int w = 0; w < width_col; ++w) {\n        int h_pad = h * stride_h_ - pad_h_ + h_offset;\n        int w_pad = w * stride_w_ - pad_w_ + w_offset;\n        if (h_pad >= 0 && h_pad < conv_in_height_ && w_pad >= 0 && w_pad < conv_in_width_)\n          col_buffer_[(c * height_col + h) * width_col + w] =\n            data_im[(c_im * conv_in_height_ + h_pad) * conv_in_width_ + w_pad];\n        else\n          col_buffer_[(c * height_col + h) * width_col + w] = 0;\n      }\n    }\n  }\n}\n\ntemplate <typename Dtype> void caffe_cpu_gemm(const CBLAS_TRANSPOSE TransA, const CBLAS_TRANSPOSE TransB, const int M, const int N, const int K, const Dtype* A, const Dtype* B, const Dtype beta, Dtype* C); \ntemplate<> void caffe_cpu_gemm<float>(const CBLAS_TRANSPOSE TransA, const CBLAS_TRANSPOSE TransB, const int M, const int N, const int K, const float* A, const float* B, const float beta, float* C) {\n  cblas_sgemm(CblasRowMajor, TransA, TransB, M, N, K, 1., A, (TransA == CblasNoTrans) ? K : M, B, (TransB == CblasNoTrans) ? N : K, beta, C, N);\n}\n\ntemplate<> void caffe_cpu_gemm<double>(const CBLAS_TRANSPOSE TransA, const CBLAS_TRANSPOSE TransB, const int M, const int N, const int K, const double* A, const double* B, const double beta, double* C) {\n  cblas_dgemm(CblasRowMajor, TransA, TransB, M, N, K, 1., A, (TransA == CblasNoTrans) ? K : M, B, (TransB == CblasNoTrans) ? N : K, beta, C, N);\n}\n\ntemplate <typename Dtype>\nvoid ParamType<Dtype>::forward_process(void)\n{\n  // For each input, ...\n  for (int i = 0; i < bottom_size; ++i) {\n    const Dtype* bottom_data = bottom[i];\n    Dtype* top_data = top[i];\n      // Convolution\n    // For each image in input batch\n    for (int n = 0; n < num_; ++n) {\n      int kernel_dim_ = conv_in_channels_ * kernel_h_ * kernel_w_;\n      const Dtype* col_buff = bottom_data + bottom_mult * n;\n      if (!is_1x1_) {\n        im2col_cpu(col_buff);\n        col_buff = col_buffer_;\n      }\n      for (int g = 0; g < group_; ++g) {\n        caffe_cpu_gemm<Dtype>(CblasNoTrans, CblasNoTrans, conv_out_channels_/group_, conv_out_spatial_dim_, kernel_dim_ / group_,\n            weight + weight_offset_ * g, col_buff + col_offset_ * g,\n            (Dtype)0., top_data + top_mult * n + output_offset_ * g);\n      }\n      // Bias\n      if (bias) {\n        caffe_cpu_gemm<Dtype>(CblasNoTrans, CblasNoTrans, num_output_, height_out_ * width_out_, 1,\n            bias, bias_multiplier_,\n            (Dtype)1., top_data + top_mult * n);\n      }\n    }\n  }\n}\n\ntemplate <typename Dtype> void caffe_cpu_gemv(const int M, const int N, const Dtype* A, const Dtype* x, Dtype* y);\ntemplate <> void caffe_cpu_gemv<float>(const int M, const int N, const float* A, const float* x, float* y) {\n  cblas_sgemv(CblasRowMajor, CblasNoTrans, M, N, 1., A, N, x, 1, 1., y, 1);\n}\ntemplate <> void caffe_cpu_gemv<double>(const int M, const int N, const double* A, const double* x, double* y) {\n  cblas_dgemv(CblasRowMajor, CblasNoTrans, M, N, 1., A, N, x, 1, 1., y, 1);\n}\ntemplate <typename Dtype>\nvoid ParamType<Dtype>::backward_process(void)\n{\n  if (weight_diff)\n    memset(weight_diff, 0, weight_diff_count);\n  if (bias_diff)\n    memset(bias_diff, 0, bias_diff_count);\n  // For all images\n  for (int i = 0; i < top_size; ++i) {\n    int kernel_dim_ = conv_in_channels_ * kernel_h_ * kernel_w_;\n    // Bias gradient, if necessary.\n    if (bias && this->param_propagate_down_[1]) {\n      for (int n = 0; n < num_; ++n) {\n        caffe_cpu_gemv<Dtype>(num_output_, height_out_ * width_out_, top_diff[i] + top_mult * n, bias_multiplier_, bias_diff);\n      }\n    }\n    if (this->param_propagate_down_[0] || propagate_down[i]) {\n      for (int n = 0; n < num_; ++n) {\n        // gradient w.r.t. weight. Note that we will accumulate diffs.\n        if (this->param_propagate_down_[0]) {\n          const Dtype* col_buff = bottom[i] + bottom_mult * n;\n          if (!is_1x1_) {\n            im2col_cpu(col_buff);\n            col_buff = col_buffer_;\n          }\n          for (int g = 0; g < group_; ++g) {\n            caffe_cpu_gemm<Dtype>(CblasNoTrans, CblasTrans, conv_out_channels_ / group_,\n                kernel_dim_ / group_, conv_out_spatial_dim_,\n                top_diff[i] + top_mult * n + output_offset_ * g, col_buff + col_offset_ * g,\n                (Dtype)1., weight_diff + weight_offset_ * g);\n          }\n        }\n        // gradient w.r.t. bottom data, if necessary.\n        if (propagate_down[i]) {\n          Dtype* col_buff = col_buffer_;\n          if (is_1x1_)\n            col_buff = bottom_diff[i] + bottom_mult * n;\n          for (int g = 0; g < group_; ++g) {\n            caffe_cpu_gemm<Dtype>(CblasTrans, CblasNoTrans, kernel_dim_ / group_,\n                conv_out_spatial_dim_, conv_out_channels_ / group_,\n                weight + weight_offset_ * g, top_diff[i] + top_mult * n + output_offset_ * g,\n                (Dtype)0., col_buff + col_offset_ * g);\n          }\n          if (!is_1x1_) {\n            Dtype *data_im = bottom_diff[i] + bottom_mult * n;\n            memset(data_im, 0, sizeof(Dtype) * conv_in_height_ * conv_in_width_ * conv_in_channels_);\n            int height_col = (conv_in_height_ + 2 * pad_h_ - kernel_h_) / stride_h_ + 1;\n            int width_col = (conv_in_width_ + 2 * pad_w_ - kernel_w_) / stride_w_ + 1;\n            int channels_col = conv_in_channels_ * kernel_h_ * kernel_w_;\n            for (int c = 0; c < channels_col; ++c) {\n              int w_offset = c % kernel_w_;\n              int h_offset = (c / kernel_w_) % kernel_h_;\n              int c_im = c / kernel_h_ / kernel_w_;\n              for (int h = 0; h < height_col; ++h) {\n                for (int w = 0; w < width_col; ++w) {\n                  int h_pad = h * stride_h_ - pad_h_ + h_offset;\n                  int w_pad = w * stride_w_ - pad_w_ + w_offset;\n                  if (h_pad >= 0 && h_pad < conv_in_height_ && w_pad >= 0 && w_pad < conv_in_width_)\n                    data_im[(c_im * conv_in_height_ + h_pad) * conv_in_width_ + w_pad] +=\n                        col_buff[(c * height_col + h) * width_col + w];\n                }\n              }\n            }\n          }\n        }\n      }\n    }\n  }\n}\n\nextern \"C\" void *alloc_connectal_conv(int size)\n{\n    if (size == sizeof(float))\n        return new ParamType<float>;\n    else\n        return new ParamType<double>;\n}\n"
  },
  {
    "path": "lib/cpp/edid.h",
    "content": "/* Copyright (c) 2014 Quanta Research Cambridge, Inc\n *\n * Permission is hereby granted, free of charge, to any person obtaining a\n * copy of this software and associated documentation files (the \"Software\"),\n * to deal in the Software without restriction, including without limitation\n * the rights to use, copy, modify, merge, publish, distribute, sublicense,\n * and/or sell copies of the Software, and to permit persons to whom the\n * Software is furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n * DEALINGS IN THE SOFTWARE.\n */\n#include <stdio.h>\n#include <string.h>\n\nstruct edid {\n  unsigned char raw[256];\n  struct edid_timing {\n  } simple_timing[8];\n  struct edid_detailed_timing {\n    unsigned short pixclk;\n    unsigned short npixels;\n    unsigned short bpixels;\n    unsigned short nlines;\n    unsigned short blines;\n    unsigned short hsyncoff;\n    unsigned short hsyncwidth;\n    unsigned short vsyncoff;\n    unsigned short vsyncwidth;\n    unsigned short widthmm;\n    unsigned short heightmm;\n    unsigned char  hborderpxls;\n    unsigned char  vborderpxls;\n    unsigned char features;\n  } timing[4];\n};\n\nstatic void parseEdid(struct edid &edid)\n{\n  for (int i = 0; i < 4; i++) {\n    unsigned char *rec = &edid.raw[54+18*i];\n    memset(&edid.timing[i], 0, sizeof(edid.timing[i]));\n\n    if (*(unsigned short*)&rec[0] == 0) {\n      unsigned char descriptor_type = rec[3];\n      switch (descriptor_type) {\n      case 0xFF: // monitor serial number\n\tfprintf(stderr, \"monitor serial number %13.13s\\n\", &rec[5]);\n\tbreak;\n      case 0xFE: // text\n\tfprintf(stderr, \"monitor text %.13s\\n\", &rec[5]);\n\tbreak;\n      case 0xFC: // monitor name\n\tfprintf(stderr, \"monitor name %.13s\\n\", &rec[5]);\n\tbreak;\n      case 0xFA: // more standard timing identifiers\n\tfprintf(stderr, \"standard timing identifiers\\n\");\n\tbreak;\n\n      }\n      continue;\n    }\n    edid.timing[i].pixclk = *(unsigned short*)&rec[0];\n    edid.timing[i].npixels = rec[2] | ((rec[4] >> 4) << 8);\n    edid.timing[i].bpixels = rec[3] | ((rec[4] & 0xF) << 8);\n    edid.timing[i].nlines = rec[5] | ((rec[7] >> 4) << 8);\n    edid.timing[i].blines = rec[6] | ((rec[7] & 0xF) << 8);\n    edid.timing[i].hsyncoff = rec[8] | ((rec[11] >> 6) << 8);\n    edid.timing[i].hsyncwidth = rec[9] | (((rec[11] & 0x30) >> 4) << 8);\n    edid.timing[i].vsyncoff = (rec[10] >>  4) | (((rec[11] & 0x0c) >> 2) << 4);\n    edid.timing[i].vsyncwidth = (rec[10] & 0xf) | (((rec[11] & 0x03) >> 0) << 4);\n    edid.timing[i].widthmm   = rec[12] | ((rec[14] >>  4) << 8);\n    edid.timing[i].heightmm  = rec[13] | ((rec[14] & 0xf) << 8);\n    edid.timing[i].hborderpxls = rec[15];\n    edid.timing[i].vborderpxls = rec[16];\n    edid.timing[i].features = rec[17];\n  }\n  for (int i = 0; i < 4; i++)\n    if (edid.timing[i].pixclk) {\n      fprintf(stderr, \"pixclk=%d w=%dmm h=%dmm features=%x\\n\",\n\t      edid.timing[i].pixclk, edid.timing[i].widthmm, edid.timing[i].heightmm, edid.timing[i].features);\n      fprintf(stderr, \"    npixels=%d bpixels=%d hsyncoff=%d hsyncwidth=%d hbpxls=%d\\n\",\n\t      edid.timing[i].npixels, edid.timing[i].bpixels,\n\t      edid.timing[i].hsyncoff, edid.timing[i].hsyncwidth, edid.timing[i].hborderpxls);\n      fprintf(stderr, \"    nlines=%d blines=%d vsyncoff=%d vsyncwidth=%d vbpxls=%d\\n\",\n\t      edid.timing[i].nlines, edid.timing[i].blines,\n\t      edid.timing[i].vsyncoff, edid.timing[i].vsyncwidth, edid.timing[i].vborderpxls);\n    }\n  fprintf(stderr, \"\\n\");\n}\n"
  },
  {
    "path": "lib/cpp/i2chdmi.h",
    "content": "/* Copyright (c) 2014 Quanta Research Cambridge, Inc\n *\n * Permission is hereby granted, free of charge, to any person obtaining a\n * copy of this software and associated documentation files (the \"Software\"),\n * to deal in the Software without restriction, including without limitation\n * the rights to use, copy, modify, merge, publish, distribute, sublicense,\n * and/or sell copies of the Software, and to permit persons to whom the\n * Software is furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n * DEALINGS IN THE SOFTWARE.\n */\n#include <stdio.h>\n#include <linux/types.h>\n#include <fcntl.h>\n#include <sys/ioctl.h>\n#include <errno.h>\n#include \"/usr/include/linux/i2c.h\"\n#include \"/usr/include/linux/i2c-dev.h\"\n\n#define I2C_HDMI_ADDR         (0x72/2) // == 0x39 (LSB is just 'W/nR', so elided on linux)\n//#define I2C_EDID_ADDR         0x3f\n#define I2C_ZC702_MUX_ADDR 0x74\nstatic int i2c_write_array(int fd, int device, unsigned char *datap, int size, int byte_write)\n{\n    struct i2c_smbus_ioctl_data args;\n    union i2c_smbus_data ioctl_data;\n    args.read_write = I2C_SMBUS_WRITE;\n    args.size = I2C_SMBUS_BYTE_DATA;\n    args.data = &ioctl_data;\n\n    int status = ioctl(fd, I2C_SLAVE, device);\n    if (status != 0) {\n\t fprintf(stderr, \"[i2chdmi] i2c_write_array: ioctl I2C_SLAVE status=%d errno=%d\\n\", status, errno);\n         return -1;\n    }\n    while (size) {\n        args.command = *datap++ | byte_write;\n        ioctl_data.byte = *datap++;\n        status = ioctl(fd, I2C_SMBUS, &args);\n\tif (status != 0) {\n\t     fprintf(stderr, \"[i2chdmi] i2c_write_array: ioctl I2C_SMBUS status=%d errno=%d\\n\", status, errno);\n             return -1;\n        }\n        size -= 2;\n    }\n    return 0;\n}\nunsigned char i2c_read_reg(int fd, int device, unsigned char reg)\n{\n    struct i2c_smbus_ioctl_data args;\n    union i2c_smbus_data ioctl_data;\n    args.read_write = I2C_SMBUS_READ;\n    args.size = I2C_SMBUS_BYTE_DATA;\n    args.data = &ioctl_data;\n\n    int status = ioctl(fd, I2C_SLAVE, device);\n    if (status != 0)\n\t fprintf(stderr, \"[i2chdmi] i2c_read_reg: ioctl I2C_SLAVE status=%d errno=%d\\n\", status, errno);\n\n    args.command = reg;\n    ioctl_data.byte = 0;\n    status = ioctl(fd, I2C_SMBUS, &args);\n    if (status != 0)\n      fprintf(stderr, \"[i2chdmi] i2c_read_reg: ioctl I2C_SMBUS status=%d errno=%d\\n\", status, errno);\n    return ioctl_data.byte;\n}\nvoid init_i2c_hdmi(void)\n{\nstatic unsigned char muxdata[] = {2, 2};\nstatic unsigned char hdmidata[] = {\n#if 1\n    0x01, 0x00, // Set N Value(6144)\n    0x02, 0x18, // Set N Value(6144)\n    0x03, 0x00, // Set N Value(6144)\n    0x41, 0x10, /* Powerup the Tx */\n    0xA1, 0x3c, // power off TMDS clock and data\n    0xD6, 0xC0 | 0x10, /* HPD control (and TMDS CLK soft turn on) */\n    // Fixed registers that must be set on powerup\n    0x98, 0x03,   0x9A, 0xE0,   0x9C, 0x30,  0x9D, 0x61,\n    0xA2, 0xA4,   0xA3, 0xA4,   0xE0, 0xD0,  0xF9, 0x00,\n\n    /* Coefficient Update */\n    0x1A, 0x08,   0x1B, 0x00,   0x1C, 0x00,   0x1D, 0x00,\n    0x1E, 0x1A,   0x1F, 0x86,   0x20, 0x1A,   0x21, 0x49,\n    0x22, 0x08,   0x23, 0x00,   0x24, 0x1D,   0x25, 0x3F,\n    0x26, 0x04,   0x27, 0x22,   0x28, 0x00,   0x29, 0x00,\n    0x2A, 0x08,   0x2B, 0x00,   0x2C, 0x0E,   0x2D, 0x2D,\n    0x2E, 0x19,   0x2F, 0x14,\n    0x48, 0x08, /* video input justification */\n    0x55, 0x00,   0x56, 0x28, /* AVI InfoFrame */\n    // Fixed registers that must be set on powerup\n    0xAF, 0x04,\n    0xDE, 0x9C, // ADI required write\n    0xE4, 0x60, // ADI required Write\n\n#else\n    0x15, 0x00, // Input 444 (RGB or YCrCb) with Separate Syncs\n    0x16, 0x61, // 44.1kHz fs, YPrPb 444\n    0x18, 0x46, // CSC disabled\n    0x40, 0x80, // General Control Packet Enable\n    0x41, 0x10, // Power Down control\n    0x48, 0x48, // Reverse bus, Data right justified\n    0x48, 0xA8, // Set Dither_mode - 12-to-10 bit\n    0x4C, 0x06, // 12 bit Output\n    0x55, 0x00, // Set RGB444 in AVinfo Frame\n    0x55, 0x08, // Set active format Aspect\n    0x96, 0x20, // HPD Interrupt clear\n    0x9D, 0x61, // Set clock divide\n    0xAF, 0x16, // Set HDMI Mode\n    0xBA, 0x60, // No clock delay\n    0xFA, 0x7D // Nbr of times to search for good phase\n#endif\n    };\n\nprintf(\"[%s:%d]\\n\", __FUNCTION__, __LINE__);\n    int fd = open(\"/dev/i2c-0\", O_RDWR);\n    if (fd < 0)\n        printf(\"[%s] open failed\\n\", __FUNCTION__);\n#ifndef BOARD_zedboard     // only initialize mux if not a zedboard\n    //set mux for hdmi\n    if (i2c_write_array(fd, I2C_ZC702_MUX_ADDR, muxdata, sizeof(muxdata), 0))\n        printf(\"[%s] write mux failed\\n\", __FUNCTION__);\n#endif\n    //set hdmi data\n    if (i2c_write_array(fd, I2C_HDMI_ADDR, hdmidata, sizeof(hdmidata), 0))\n        printf(\"[%s] write data failed\\n\", __FUNCTION__);\n    close(fd);\n}\n\nvoid i2c_hdmi_start(void)\n{\nstatic unsigned char hdmidata[] = {\n    0x15, 0x01,   0x16, 0x38, /* Video input mode */\n    0x18, 0xAB,   0x19, 0x37, /* Video output mode */\n    0xA1, 0x00 // power on TMDS clock and data\n};\n\nprintf(\"[%s:%d]\\n\", __FUNCTION__, __LINE__);\n    int fd = open(\"/dev/i2c-0\", O_RDWR);\n    if (fd < 0)\n        printf(\"[%s] open failed\\n\", __FUNCTION__);\n    //set hdmi data\n    if (i2c_write_array(fd, I2C_HDMI_ADDR, hdmidata, sizeof(hdmidata), 0))\n        printf(\"[%s] write data failed\\n\", __FUNCTION__);\n    for (int i = 0; i <= 0x8; i++) {\n        int val = i2c_read_reg(fd, I2C_HDMI_ADDR, i);\nprintf(\"[%s:%d] HDMI [%x] = %x\\n\", __FUNCTION__, __LINE__, i, val);\n    }\n    close(fd);\n}\n\nvoid init_i2c_hdmi_rgb24(void)\n{\nstatic unsigned char muxdata[] = {2, 2};\nstatic unsigned char hdmidata[] = {\n    0x41, 0x10,  0xD6, 0xC0,  0x15, 0x00,  0x16, 0x38,\n    0x18, 0xAB,  0x19, 0x37,  0x1A, 0x08,  0x1B, 0x00,\n    0x1C, 0x00,  0x1D, 0x00,  0x1E, 0x1A,  0x1F, 0x86,\n    0x20, 0x1A,  0x21, 0x49,  0x22, 0x08,  0x23, 0x00,\n    0x24, 0x1D,  0x25, 0x3F,  0x26, 0x04,  0x27, 0x22,\n    0x28, 0x00,  0x29, 0x00,  0x2A, 0x08,  0x2B, 0x00,\n    0x2C, 0x0E,  0x2D, 0x2D,  0x2E, 0x19,  0x2F, 0x14,\n    0x48, 0x08,  0x55, 0x00,  0x56, 0x28,  0x98, 0x03,\n    0x9A, 0xE0,  0x9C, 0x30,  0x9D, 0x61,  0xA2, 0xA4,\n    0xA3, 0xA4,  0xAF, 0x04,  0xE0, 0xD0,  0xF9, 0x00};\n\n    int fd = open(\"/dev/i2c-0\", O_RDWR);\n    if (fd < 0)\n        printf(\"[%s] open failed\\n\", __FUNCTION__);\n    //set mux for hdmi\n    if (i2c_write_array(fd, I2C_ZC702_MUX_ADDR, muxdata, sizeof(muxdata), 0))\n        printf(\"[%s] write mux failed\\n\", __FUNCTION__);\n    //set hdmi data\n    if (i2c_write_array(fd, I2C_HDMI_ADDR, hdmidata, sizeof(hdmidata), 0))\n        printf(\"[%s] write data failed\\n\", __FUNCTION__);\n    close(fd);\n}\n"
  },
  {
    "path": "lib/cpp/printfInd.h",
    "content": "/* Copyright (c) 2013 Quanta Research Cambridge, Inc\n *\n * Permission is hereby granted, free of charge, to any person obtaining a\n * copy of this software and associated documentation files (the \"Software\"),\n * to deal in the Software without restriction, including without limitation\n * the rights to use, copy, modify, merge, publish, distribute, sublicense,\n * and/or sell copies of the Software, and to permit persons to whom the\n * Software is furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n * DEALINGS IN THE SOFTWARE.\n */\n/* Dummy stub for when printf not enabled */\nclass DisplayInd : public DisplayIndWrapper\n{\npublic:\n    DisplayInd(unsigned int id, PortalPoller *poller) : DisplayIndWrapper(id, poller) {}\n};\n"
  },
  {
    "path": "lib/cpp/userReference.h",
    "content": "/* Copyright (c) 2014 Quanta Research Cambridge, Inc\n *\n * Permission is hereby granted, free of charge, to any person obtaining a\n * copy of this software and associated documentation files (the \"Software\"),\n * to deal in the Software without restriction, including without limitation\n * the rights to use, copy, modify, merge, publish, distribute, sublicense,\n * and/or sell copies of the Software, and to permit persons to whom the\n * Software is furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n * DEALINGS IN THE SOFTWARE.\n */\n\n#define PAGE_SHIFT0 12\n#define PAGE_SHIFT4 16\n#define PAGE_SHIFT8 20\nstatic int shifts[] = {PAGE_SHIFT8, PAGE_SHIFT4, PAGE_SHIFT0, 0};\n\n#include \"dmaManager.h\"\n#include \"drivers/portalmem/portalmem.h\" // PortalAlloc\n\n#ifdef CONNECTAL_DRIVER_CODE\n#include \"DmaConfigProxy.c\"\nstatic int trace_memory = 1;\n#endif\n\n#include \"GeneratedTypes.h\" // generated in project directory\n#define DMAsglist(P, A, B, C, D) MMURequest_sglist((P), (A), (B), (C), (D));\n#define DMAregion(P, PTR, B12, I12, B8, I8, B4, I4, B0, I0) MMURequest_region((P), (PTR), (B12), (I12), (B8), (I8), (B4), (I4), (B0), (I0))\n\ntypedef struct {\n    long dma_address;\n    long length;\n} RegionRef;\n\nint send_reference_to_portal(PortalInternal *device, int numEntries, RegionRef *data, int id)\n{\n    int rc = 0;\n    int i, j;\n    uint32_t regions[3] = {0,0,0};\n    uint64_t border = 0;\n    unsigned char entryCount = 0;\n    uint64_t borderVal[3];\n    uint32_t indexVal[3];\n    unsigned char idxOffset;\n  rc = id;\n  PORTAL_PRINTF(\"[%s:%d] num %d\\n\", __FUNCTION__, __LINE__, numEntries);\n  for(i = 0; i < numEntries; i++) {\n    long addr = data[i].dma_address;\n    long len = data[i].length;\n\n    for(j = 0; j < 3; j++)\n        if (len == 1<<shifts[j]) {\n          regions[j]++;\n          if (addr & ((1L<<shifts[j]) - 1))\n              PORTAL_PRINTF(\"%s: addr %lx shift %x *********\\n\", __FUNCTION__, addr, shifts[j]);\n          addr >>= shifts[j];\n          break;\n        }\n    if (j >= 3)\n      PORTAL_PRINTF(\"DmaManager:unsupported sglist size %lx\\n\", len);\n    if (trace_memory)\n      PORTAL_PRINTF(\"DmaManager:sglist(id=%08x, i=%d dma_addr=%08lx, len=%08lx)\\n\", id, i, (long)addr, len);\n    DMAsglist(device, id, i, addr, len);\n  }\n\n  // HW interprets zeros as end of sglist\n  if (trace_memory)\n    PORTAL_PRINTF(\"DmaManager:sglist(id=%08x, i=%d end of list)\\n\", id, i);\n  DMAsglist(device, id, i, 0, 0); // end list\n\n  for(i = 0; i < 3; i++){\n    idxOffset = entryCount - border;\n    entryCount += regions[i];\n    border += regions[i];\n    borderVal[i] = border;\n    indexVal[i] = idxOffset;\n    border <<= (shifts[i] - shifts[i+1]);\n  }\n  if (trace_memory) {\n    PORTAL_PRINTF(\"regions %d (%x %x %x)\\n\", id,regions[0], regions[1], regions[2]);\n    PORTAL_PRINTF(\"borders %d (%\"PRIx64\" %\"PRIx64\" %\"PRIx64\")\\n\", id,borderVal[0], borderVal[1], borderVal[2]);\n  }\n  DMAregion(device, id, 0, 0, borderVal[0], indexVal[0], borderVal[1], indexVal[1], borderVal[2], indexVal[2]);\n\n    return rc;\n}\n"
  },
  {
    "path": "lib/deprecated/BurstFunnel.bsv",
    "content": "// Copyright (c) 2015 The Connectal Project\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\nimport Vector::*;\nimport FIFOF::*;\nimport FIFO::*;\nimport GetPut::*;\nimport ClientServer::*;\nimport BRAM::*;\nimport BRAMFIFO::*;\nimport Connectable::*;\nimport ConfigCounter::*;\nimport ConnectalMemory::*;\nimport ConnectalMemTypes::*;\nimport Pipe::*;\nimport ConnectalMemUtils::*;\n\ntypedef struct {\n   Bit#(busWidth)  data;\n   Bool            last;\n} BFunnelData#(numeric type busWidth) deriving (Bits, Eq);\ntypedef struct {\n   Bit#(nameWidth)        name;\n   BFunnelData#(busWidth) data;\n} BFunnelNameData#(numeric type nameWidth, numeric type busWidth) deriving (Bits, Eq);\ntypedef struct {\n   Bit#(nameWidth)        name;\n   Bit#(busWidth)         data;\n} BFunnelFunnel#(numeric type nameWidth, numeric type busWidth) deriving (Bits, Eq);\ntypedef struct {\n   Bit#(oldWidth) oldName;\n   Bit#(newWidth) newName;\n} BFunnelRename#(numeric type oldWidth, numeric type newWidth) deriving (Bits, Eq);\n\ninterface BurstFunnel#(numeric type k, numeric type w);\n   method Action loadIdx(Bit#(TLog#(k)) i);\n   interface Vector#(k, PipeIn#(Bit#(w))) dataIn;\n   interface Vector#(k, Reg#(Bit#(BurstLenSize))) burstLen;\n   interface PipeOut#(BFunnelFunnel#(TLog#(k),w)) dataOut;\nendinterface\n\nmodule mkBurstFunnel#(Integer maxBurstLen)(BurstFunnel#(k,w))\n   provisos( Log#(k,logk)\n\t    ,Min#(2,logk,bpc)\n\t    ,FunnelPipesPipelined#(1, k, BFunnelNameData#(2,w), bpc)\n\t    );\n\n   Reg#(Bit#(2)) nameGen <- mkReg(0);\n   UGBramFifos#(4,16,BFunnelData#(w)) complBuff <- mkUGBramFifos;\n   Vector#(4, ConfigCounter#(16)) compCnts <- replicateM(mkConfigCounter(0));\n   Vector#(k,FIFOF#(BFunnelNameData#(2, w))) data_in <- replicateM(mkFIFOF);\n   Vector#(k,Reg#(Bit#(BurstLenSize))) burst_len <- replicateM(mkReg(0));\n   Vector#(k,Reg#(Bit#(BurstLenSize))) drain_cnt <- replicateM(mkReg(0));\n   Reg#(Bit#(BurstLenSize)) inj_ctrl <- mkReg(0);\n   FIFO#(BFunnelRename#(TAdd#(1,logk),2)) loadIdxs <- mkSizedBRAMFIFO(32);\n   FIFO#(BFunnelRename#(TAdd#(1,logk),2)) inFlight <- mkSizedBRAMFIFO(4);\n   FunnelPipe#(1, k, BFunnelNameData#(2,w),bpc) data_in_funnel <- mkFunnelPipesPipelined(map(toPipeOut,data_in));\n   Reg#(Bit#(BurstLenSize)) drainCnt <- mkReg(0);\n   FIFOF#(BFunnelFunnel#(TLog#(k),w)) exit_data <- mkFIFOF;\n   FIFO#(Bit#(logk)) drainRename <- mkFIFO;\n   \n   Reg#(Bit#(32)) cycle <- mkReg(0);\n   Reg#(Bit#(32)) last_entry <- mkReg(0);\n   \n   rule cyc;\n      cycle <= cycle+1;\n   endrule\n   \n   function PipeIn#(Bit#(w)) enter_data(FIFOF#(BFunnelNameData#(2, w)) f, Integer i) = \n      (interface PipeIn;\n   \t  method Bool notFull = f.notFull;\n          method Action enq(Bit#(w) data) if (loadIdxs.first.oldName == fromInteger(i));\n\t     last_entry <= cycle;\n\t     let first = inj_ctrl == 0;\n\t     let cnt = first ? burst_len[i] : inj_ctrl;\n\t     let new_cnt = cnt-1;\n\t     let last = new_cnt == 0;\n\t     inj_ctrl <= new_cnt;\n\t     if (first)\n\t\tinFlight.enq(loadIdxs.first);\n\t     if (last) \n\t\tloadIdxs.deq;\n\t     f.enq(BFunnelNameData{name:loadIdxs.first.newName, data:BFunnelData{data:data, last:last}});\n\t     //$display(\"%d enq %d\", cycle-last_entry, i);\n\t  endmethod\n       endinterface);\n   Vector#(k, PipeIn#(Bit#(w))) data_in_pipes = zipWith(enter_data, data_in, genVector);\n\n   function Reg#(Bit#(BurstLenSize)) check(Reg#(Bit#(BurstLenSize)) r) =\n      (interface Reg;\n\t  method Action _write(Bit#(BurstLenSize) v);\n\t     if(v > 16) begin\n\t\t$display(\"ERROR mkBurstFunnel: burstLen too large\");\n\t\t$finish;\n\t     end\n\t     r <= v;\n\t  endmethod\n\t  method Bit#(BurstLenSize) _read = r._read;\n       endinterface);\n\n   rule drain_funnel;\n      let v <- toGet(data_in_funnel[0]).get;\n      complBuff.enq(v.name,v.data);\n      compCnts[v.name].increment(1);\n   endrule\n      \n   \n   rule drain_req (compCnts[inFlight.first.newName].read > 0);\n      let new_drainCnt = drainCnt-1;\n      if (drainCnt == 0) begin\n\t new_drainCnt = burst_len[inFlight.first.oldName]-1;\n\t drainRename.enq(truncate(inFlight.first.oldName));\n      end\n      if (new_drainCnt == 0) begin\n\t inFlight.deq;\n      end\n      complBuff.first_req(inFlight.first.newName);\n      drainCnt <= new_drainCnt;\n      compCnts[inFlight.first.newName].decrement(1);\n      complBuff.deq(inFlight.first.newName);\n   endrule\n      \n   rule drain_resp;\n      let v <- complBuff.first_resp;\n      if (v.last)\n\t drainRename.deq;\n      exit_data.enq(BFunnelFunnel{name:drainRename.first,data:v.data});\n   endrule\n      \n   method Action loadIdx(Bit#(logk) idx);\n      loadIdxs.enq(BFunnelRename{oldName:extend(idx), newName: nameGen});\n      nameGen <= nameGen+1;\n   endmethod\n   interface burstLen = map(check,burst_len);\n   interface dataIn = data_in_pipes;\n   interface PipeOut dataOut = toPipeOut(exit_data);\nendmodule\n"
  },
  {
    "path": "lib/deprecated/DirectoryRF.bsv",
    "content": "\n// Copyright (c) 2013-2014 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\n// bsv libraries\nimport Vector::*;\nimport FIFO::*;\nimport RegFile::*;\nimport SpecialFIFOs::*;\n\n//Connectal libraries\nimport Portal::*;\nimport ConnectalMemTypes::*;\nimport RegFileA::*;\n\ninterface Directory#(numeric type _n,\n\t\t     numeric type _a, \n\t\t     numeric type _d);\n   interface Portal#(_a,_d) portalIfc;\nendinterface\n\ntypedef Directory#(16,16,32) StdDirectory;\n\nmodule mkStdDirectoryPortalIfc#(RegFileA#(Bit#(16), Bit#(32)) rf)(StdPortal);\n   MemSlave#(16,32) ctrl <- mkMemSlaveFromRegFile(rf);\n   method Bit#(32) ifcId();\n      return 0;\n   endmethod\n   method Bit#(32) ifcType();\n      return 0;\n   endmethod\n   interface MemSlave slave = ctrl;\n   interface ReadOnly interrupt;\n      method Bool _read;\n\t return False;\n      endmethod\n   endinterface\nendmodule\n\nmodule mkStdDirectory#(Vector#(n,StdPortal) portals) (StdDirectory);\n\n   Reg#(Bit#(64)) cycle_count <- mkReg(0);\n   Reg#(Bit#(32)) snapshot    <- mkReg(0);\n\n   rule count;\n      cycle_count <= cycle_count+1;\n   endrule\n   \n   let rf = (interface RegFileA#(Bit#(16), Bit#(32));\n\t\tmethod Action upd(Bit#(16) addr, Bit#(32) data);\n\t\t   noAction;\n\t\tendmethod\n\t\tmethod ActionValue#(Bit#(32)) sub(Bit#(16) _addr);\n\t\t   let base = 128;\n\t\t   let cco = fromInteger(valueOf(TAdd#(TMul#(2,n),4)))+base;\n\t\t   let addr = _addr[15:0]; \n\t\t   if (addr == 0+base)\n\t\t      return 1; // directory version\n\t\t   else if (addr == 1+base)\n\t\t      return `TimeStamp;\n\t\t   else if (addr == 2+base)\n\t\t      return fromInteger(valueOf(n));\n\t\t   else if (addr == 3+base)\n\t\t      return 16; // portal Addr bits\n\t\t   else if (addr < cco) begin\n\t\t      let idx = (addr-4-base);\n\t\t      if (idx[0] == 0)\n\t\t   \t return portals[idx>>1].ifcId;\n\t\t      else\n\t\t   \t return portals[idx>>1].ifcType;\n\t\t   end\n\t\t   else if (addr == cco) begin\n\t\t      snapshot <= truncate(cycle_count);\n\t\t      return cycle_count[63:32];\n\t\t   end\n\t\t   else if (addr == cco+1)\n\t\t      return snapshot;\n\t\t   else begin\n      \t\t      $display(\"directory addr out bounds %d\", addr);\n\t\t      return 0;\n\t\t   end\n\t\tendmethod\n      \t     endinterface);\n   let ifc <- mkStdDirectoryPortalIfc(rf);\n   interface StdPortal portalIfc = ifc;\nendmodule\n\n\n\n"
  },
  {
    "path": "lib/deprecated/DmaUtils.bsv",
    "content": "// Copyright (c) 2013 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\n\nimport BRAM::*;\nimport FIFO::*;\nimport Vector::*;\nimport Gearbox::*;\nimport FIFOF::*;\nimport SpecialFIFOs::*;\n\nimport ConfigCounter::*;\nimport BRAMFIFOFLevel::*;\nimport GetPut::*;\nimport ConnectalMemTypes::*;\n\nfunction MemReadClient#(dataWidth) orc(DmaReadBuffer#(dataWidth,bufferDepth) rb) = rb.dmaClient;\nfunction MemWriteClient#(dataWidth) owc(DmaWriteBuffer#(dataWidth,bufferDepth) wb) = wb.dmaClient;\nfunction MemReadServer#(dataWidth) ors(DmaReadBuffer#(dataWidth,bufferDepth) rb) = rb.dmaServer;\nfunction MemWriteServer#(dataWidth) ows(DmaWriteBuffer#(dataWidth,bufferDepth) wb) = wb.dmaServer;\n\n//\n// @brief A buffer for reading from a bus of width dataWidth.\n//\n// @param dataWidth The number of bits in the bus.\n// @param bufferDepth The depth of the internal buffer\n//\ninterface DmaReadBuffer#(numeric type dataWidth, numeric type bufferDepth);\n   interface MemReadServer #(dataWidth) dmaServer;\n   interface MemReadClient#(dataWidth) dmaClient;\nendinterface\n\n//\n// @brief A buffer for writing to a bus of width dataWidth.\n//\n// @param dataWidth The number of bits in the bus.\n// @param bufferDepth The depth of the internal buffer\n//\ninterface DmaWriteBuffer#(numeric type dataWidth, numeric type bufferDepth);\n   interface MemWriteServer#(dataWidth) dmaServer;\n   interface MemWriteClient#(dataWidth) dmaClient;\nendinterface\n\n\n\n//\n// @brief Makes a Dma buffer for reading wordSize words from memory.\n//\n// @param dataWidth The width of the bus in bits.\n// @param bufferDepth The depth of the internal buffer\n//\nmodule mkDmaReadBuffer(DmaReadBuffer#(dataWidth, bufferDepth))\n   provisos(Add#(b__, TAdd#(1,TLog#(bufferDepth)), BurstLenSize),\n\t    Div#(dataWidth,8,dataWidthBytes),\n\t    Mul#(dataWidthBytes,8,dataWidth),\n\t    Log#(dataWidthBytes,beatShift));\n\n   FIFOFLevel#(MemData#(dataWidth),bufferDepth)  readBuffer <- mkBRAMFIFOFLevel;\n   FIFOF#(MemRequest)        reqOutstanding <- mkFIFOF();\n   ConfigCounter#(TAdd#(1,TLog#(bufferDepth))) unfulfilled <- mkConfigCounter(0);\n   let beat_shift = fromInteger(valueOf(beatShift));\n   \n   // only issue the readRequest when sufficient buffering is available.  This includes the bufering we have already comitted.\n   Bit#(TAdd#(1,TLog#(bufferDepth))) sreq = pack(satPlus(Sat_Bound, unpack(truncate(reqOutstanding.first.burstLen>>beat_shift)), unfulfilled.read()));\n\n   interface MemReadServer dmaServer;\n      interface Put readReq = toPut(reqOutstanding);\n      interface Get readData = toGet(readBuffer);\n   endinterface\n   interface MemReadClient dmaClient;\n      interface Get readReq;\n\t method ActionValue#(MemRequest) get if (readBuffer.lowWater(sreq));\n\t    reqOutstanding.deq;\n\t    unfulfilled.increment(unpack(truncate(reqOutstanding.first.burstLen>>beat_shift)));\n\t    return reqOutstanding.first;\n\t endmethod\n      endinterface\n      interface Put readData;\n\t method Action put(MemData#(dataWidth) x);\n\t    readBuffer.fifo.enq(x);\n\t    unfulfilled.decrement(1);\n\t endmethod\n      endinterface\n   endinterface\nendmodule\n\n//\n// @brief Makes a Dma channel for writing wordSize words from memory.\n//\n// @param dataWidth The width of the bus in bits.\n// @param bufferDepth The depth of the internal buffer\n//\nmodule mkDmaWriteBuffer(DmaWriteBuffer#(dataWidth, bufferDepth))\n   provisos(Add#(b__, TAdd#(1, TLog#(bufferDepth)), BurstLenSize),\n\t    Div#(dataWidth,8,dataWidthBytes),\n\t    Mul#(dataWidthBytes,8,dataWidth),\n\t    Log#(dataWidthBytes,beatShift));\n\n   FIFOFLevel#(MemData#(dataWidth),bufferDepth) writeBuffer <- mkBRAMFIFOFLevel;\n   FIFOF#(MemRequest)        reqOutstanding <- mkFIFOF();\n   FIFOF#(Bit#(6))                        doneTags <- mkFIFOF();\n   ConfigCounter#(TAdd#(1,TLog#(bufferDepth)))  unfulfilled <- mkConfigCounter(0);\n   let beat_shift = fromInteger(valueOf(beatShift));\n   \n   // only issue the writeRequest when sufficient data is available.  This includes the data we have already comitted.\n   Bit#(TAdd#(1,TLog#(bufferDepth))) sreq = pack(satPlus(Sat_Bound, unpack(truncate(reqOutstanding.first.burstLen>>beat_shift)), unfulfilled.read()));\n\n   interface MemWriteServer dmaServer;\n      interface Put writeReq = toPut(reqOutstanding);\n      interface Put writeData = toPut(writeBuffer);\n      interface Get writeDone = toGet(doneTags);\n   endinterface\n   interface MemWriteClient dmaClient;\n      interface Get writeReq;\n\t method ActionValue#(MemRequest) get if (writeBuffer.highWater(sreq));\n\t    reqOutstanding.deq;\n\t    unfulfilled.increment(unpack(truncate(reqOutstanding.first.burstLen>>beat_shift)));\n\t    return reqOutstanding.first;\n\t endmethod\n      endinterface\n      interface Get writeData;\n\t method ActionValue#(MemData#(dataWidth)) get();\n\t    unfulfilled.decrement(1);\n\t    writeBuffer.fifo.deq;\n\t    return writeBuffer.fifo.first;\n\t endmethod\n      endinterface\n      interface Put writeDone = toPut(doneTags);\n   endinterface\nendmodule\n   \n   \nmodule mkDmaReadMux#(Vector#(numClients,MemReadClient#(dataWidth)) readClients)(MemReadClient#(dataWidth))\n   provisos(Log#(numClients,tagsz),\n\t    Add#(tagsz,a__,MemTagSize));\n\n   FIFO#(MemRequest)          readReqFifo  <- mkFIFO();\n   FIFO#(MemData#(dataWidth)) readRespFifo <- mkFIFO();\n\n   for (Integer i = 0; i < valueOf(numClients); i = i + 1) begin\n      // assume fixed tag per client\n      Reg#(Bit#(MemTagSize)) tagReg <- mkReg(0);\n      rule getreq;\n\t   let req <- readClients[i].readReq.get();\n\t   tagReg <= req.tag;\n\t   req.tag = fromInteger(i);\n\t   readReqFifo.enq(req);\n      endrule\n      rule sendresp if (readRespFifo.first.tag == fromInteger(i));\n\t   let resp <- toGet(readRespFifo).get();\n\t   resp.tag = tagReg;\n\t   readClients[i].readData.put(resp);\n      endrule\n   end\n\n   interface Get readReq = toGet(readReqFifo);\n   interface Put readData = toPut(readRespFifo);\nendmodule\n\nmodule mkDmaWriteMux#(Vector#(numClients,MemWriteClient#(dataWidth)) writeClients)(MemWriteClient#(dataWidth))\n   provisos(Log#(numClients,tagsz),\n       Add#(tagsz,a__,MemTagSize));\n\n   FIFO#(MemRequest)          writeReqFifo  <- mkFIFO();\n   FIFO#(MemData#(dataWidth)) writeDataFifo <- mkFIFO();\n   FIFO#(Bit#(MemTagSize))    writeDoneFifo <- mkFIFO();\n   FIFO#(Bit#(MemTagSize))    arbFifo       <- mkFIFO();\n\n   for (Integer i = 0; i < valueOf(numClients); i = i + 1) begin\n      // assume fixed tag per client\n      Reg#(Bit#(MemTagSize)) tagReg <- mkReg(0);\n      rule getreq;\n\t   let req <- writeClients[i].writeReq.get();\n\t   tagReg <= req.tag;\n\t   req.tag = fromInteger(i);\n\t   writeReqFifo.enq(req);\n\t   arbFifo.enq(req.tag);\n      endrule\n      rule senddata if (fromInteger(i) == arbFifo.first);\n\t   let data <- writeClients[i].writeData.get();\n\t   data.tag = tagReg;\n\t   writeDataFifo.enq(data);\n      endrule\n      rule senddone if (writeDoneFifo.first == fromInteger(i));\n\t   arbFifo.deq();\n\t   let done <- toGet(writeDoneFifo).get();\n\t   writeClients[i].writeDone.put(tagReg);\n      endrule\n   end\n\n   interface Get writeReq = toGet(writeReqFifo);\n   interface Get writeData = toGet(writeDataFifo);\n   interface Put writeDone = toPut(writeDoneFifo);\nendmodule\n"
  },
  {
    "path": "lib/deprecated/OldMemServer.bsv",
    "content": "// Copyright (c) 2013 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\n// BSV Libraries\n`include \"ConnectalProjectConfig.bsv\"\nimport FIFO::*;\nimport Vector::*;\nimport GetPut::*;\nimport ClientServer::*;\nimport Assert::*;\n\n// CONNECTAL Libraries\nimport ConnectalMemTypes::*;\nimport ConnectalMemory::*;\nimport ConnectalMMU::*;\n\n`ifdef SIMULATION\nimport \"BDPI\" function ActionValue#(Bit#(32)) pareff(Bit#(32) handle, Bit#(32) size);\n`endif\n\ninterface MemServer#(numeric type addrWidth, numeric type dataWidth);\n   interface DmaConfig request;\n   interface MemMaster#(addrWidth, dataWidth) master;\nendinterface\n\ninterface MemWriteInternal#(numeric type addrWidth, numeric type dataWidth);\n   interface DmaDbg dbg;\n   interface MemWriteClient#(addrWidth,dataWidth) write_client;\n   interface Get#(Tuple2#(Bit#(6),Bit#(6))) tagMismatch;\nendinterface\n\ninterface MemReadInternal#(numeric type addrWidth, numeric type dataWidth);\n   interface DmaDbg dbg;\n   interface MemReadClient#(addrWidth,dataWidth) read_client;\n   interface Get#(Tuple2#(Bit#(6),Bit#(6))) tagMismatch;\nendinterface\n\nfunction Bool bad_pointer(SGLId p);\n   return (p > fromInteger(valueOf(MaxNumSGLists)) || p == 0);\nendfunction\n\ntypedef struct {MemRequest req;\n\t\tBit#(6) rename_tag;\n\t\tBit#(addrWidth) pa;\n\t\tDmaChannelId chan; } IRec#(type addrWidth) deriving(Bits);\n\t\t \nmodule mkMemReadInternal#(Vector#(numReadClients, MemReadClient#(dataWidth)) readClients, \n\t\t\t     DmaIndication dmaIndication,\n\t\t\t     Server#(Tuple2#(SGListId,Bit#(MemOffsetSize)),Bit#(addrWidth)) sgl) \n   (MemReadInternal#(addrWidth, dataWidth))\n\n   provisos(Add#(b__, addrWidth, 64), \n\t    Add#(c__, 12, addrWidth), \n\t    Add#(1, c__, d__),\n\t    Div#(dataWidth,8,dataWidthBytes),\n\t    Mul#(dataWidthBytes,8,dataWidth),\n\t    Log#(dataWidthBytes,beatShift));\n   \n   FIFO#(IRec#(addrWidth)) lreqFifo <- mkSizedFIFO(1);\n   FIFO#(IRec#(addrWidth))  reqFifo <- mkSizedFIFO(1);\n   FIFO#(IRec#(addrWidth)) dreqFifo <- mkSizedFIFO(32);\n\n   Reg#(Bit#(8))           burstReg <- mkReg(0);\n   Vector#(numReadClients, Reg#(Bit#(64))) beatCounts <- replicateM(mkReg(0));\n   let beat_shift = fromInteger(valueOf(beatShift));\n\n   // report a tag mismatch for oo completions (in which \n   // case we will need to introduce completion buffers)\n   FIFO#(Tuple2#(Bit#(6),Bit#(6))) tag_mismatch <- mkSizedFIFO(32);\n\n`ifdef\tINTERVAL_ANAlYSIS\n   Reg#(Bit#(32)) bin1 <- mkReg(0);\n   Reg#(Bit#(32)) bin4 <- mkReg(0);\n   Reg#(Bit#(32)) binx <- mkReg(0);\n   Reg#(Bit#(64)) cycle_cnt <- mkReg(0);\n   Reg#(Bit#(64)) last_resp_read <- mkReg(0);\n   (* fire_when_enabled *)\n   rule cycle;\n      cycle_cnt <= cycle_cnt+1;\n   endrule\n`endif\n      \n   for (Integer selectReg = 0; selectReg < valueOf(numReadClients); selectReg = selectReg + 1)\n      rule loadChannel;\n\t MemRequest req <- readClients[selectReg].readReq.get();\n\t //$display(\"dmaread.loadChannel activeChan=%d handle=%h addr=%h burst=%h\", selectReg, req.sglId, req.offset, req.burstLen);\n\t if (bad_pointer(req.sglId))\n\t    dmaIndication.badPointer(req.sglId);\n\t else begin\n\t    lreqFifo.enq(IRec{req:req, rename_tag:?, pa:?, chan:fromInteger(selectReg)});\n\t    sgl.request.put(tuple2(truncate(req.sglId),req.offset));\n\t end\n      endrule\n   \n   rule checkSglResp;\n      let physAddr <- sgl.response.get;\n      let req = lreqFifo.first.req;\n      let chan = lreqFifo.first.chan;\n      lreqFifo.deq();\n      if (physAddr <= (1 << valueOf(SGListPageShift0))) begin\n\t // squash request\n\t $display(\"dmaRead: badAddr pointer=%d offset=%h physAddr=%h\", req.sglId, req.offset, physAddr);\n\t dmaIndication.badAddr(req.sglId, extend(req.offset), extend(physAddr));\n      end\n      else begin\n\t if (False && physAddr[31:24] != 0)\n\t    $display(\"checkSglResp: funny physAddr req.sglId=%d req.offset=%h physAddr=%h\", req.sglId, req.offset, physAddr);\n\t reqFifo.enq(IRec{req:req, rename_tag:truncate(chan), pa:physAddr, chan:chan});\n      end\n   endrule\n\n   interface DmaDbg dbg;\n      method ActionValue#(DmaDbgRec) dbg();\n`ifdef INTERVAL_ANAlYSIS\n\t return DmaDbgRec{x:fromInteger(valueOf(numReadClients)), y:bin1, z:bin4, w:binx};\n`else\n\t return DmaDbgRec{x:fromInteger(valueOf(numReadClients)), y:0, z:0, w:0};\n`endif\n      endmethod\n      method ActionValue#(Bit#(64)) getMemoryTraffic(Bit#(32) client);\n\t return (valueOf(numReadClients) > 0 && client < fromInteger(valueOf(numReadClients))) ? beatCounts[client] : 0;\n      endmethod\n   endinterface\n\n   interface MemReadClient read_client;\n      interface Get readReq;\n\t method ActionValue#(PhysMemRequest#(addrWidth)) get;\n\t    let req = reqFifo.first.req;\n\t    let physAddr = reqFifo.first.pa;\n\t    let rename_tag = reqFifo.first.rename_tag;\n\t    reqFifo.deq;\n\t    //$display(\"mkMemReadInternal::req_ar tag=%d rename_tag=%d len=%d activeChan=%d\", req.tag, rename_tag, req.burstLen, reqFifo.first.chan);\n\t    if (False && physAddr[31:24] != 0)\n\t       $display(\"req_ar: funny physAddr req.sglId=%d req.offset=%h physAddr=%h\", req.sglId, req.offset, physAddr);\n\t    dreqFifo.enq(reqFifo.first);\n\t    return PhysMemRequest{addr:physAddr, burstLen:req.burstLen, tag:rename_tag};\n\t endmethod\n      endinterface\n      interface Put readData;\n\t method Action put(MemData#(dataWidth) response);\n\t    let activeChan = dreqFifo.first.chan;\n\t    let req = dreqFifo.first.req;\n\t    let rename_tag = dreqFifo.first.rename_tag;\n\t    if (valueOf(numReadClients) > 0)\n\t       readClients[activeChan].readData.put(MemData { data: response.data, tag: req.tag});\n\n\t    let burstLen = burstReg;\n\t    if (burstLen == 0)\n\t       burstLen = req.burstLen >> beat_shift;\n\n\t    if (burstLen == 1)\n\t       dreqFifo.deq();\n   \n\t    if (response.tag != rename_tag) begin\n\t       tag_mismatch.enq(tuple2(response.tag,rename_tag));\n\t       $display(\"mkMemReadInternal::tag_mismatch %d %d\", response.tag, rename_tag);\n\t    end\n\t    //$display(\"mkMemReadInternal::resp_read rename_tag=%d response.tag=%d burstLen=%d activeChan=%d\", rename_tag, response.tag, burstLen, activeChan);\n\t    burstReg <= burstLen-1;\n\n\t    if(valueOf(numReadClients) > 0)\n\t       beatCounts[activeChan] <= beatCounts[activeChan]+1;\n`ifdef INTERVAL_ANAlYSIS\n\t    last_resp_read <= cycle_cnt;\n\t    let interval = cycle_cnt - last_resp_read;\n\t    if (interval <= 1)\n\t       bin1 <= bin1+1;\n\t    else if (interval <= 4)\n\t       bin4 <= bin4+1;\n\t    else\n\t       binx <= binx+1;\n`endif\n\t endmethod\n      endinterface\n   endinterface\n   interface Get tagMismatch = fifoToGet(tag_mismatch);\nendmodule\n\n\nmodule mkMemWriteInternal#(Vector#(numWriteClients, MemWriteClient#(dataWidth)) writeClients,\n\t\t\t      DmaIndication dmaIndication, \n\t\t\t      Server#(Tuple2#(SGListId,Bit#(MemOffsetSize)),Bit#(addrWidth)) sgl)\n\n   (MemWriteInternal#(addrWidth, dataWidth))\n   \n   provisos(Add#(b__, addrWidth, 64), \n\t    Add#(c__, 12, addrWidth), \n\t    Add#(1, c__, d__),\n\t    Div#(dataWidth,8,dataWidthBytes),\n\t    Mul#(dataWidthBytes,8,dataWidth),\n\t    Log#(dataWidthBytes,beatShift));\n   \n   FIFO#(IRec#(addrWidth)) lreqFifo <- mkSizedFIFO(1);\n   FIFO#(IRec#(addrWidth))  reqFifo <- mkSizedFIFO(1);\n   FIFO#(IRec#(addrWidth)) dreqFifo <- mkSizedFIFO(32);\n   FIFO#(IRec#(addrWidth)) respFifo <- mkSizedFIFO(32);\n\n   Reg#(Bit#(8))         burstReg <- mkReg(0);   \n   Vector#(numWriteClients, Reg#(Bit#(64))) beatCounts <- replicateM(mkReg(0));\n   let beat_shift = fromInteger(valueOf(beatShift));\n   \n   // report a tag mismatch for oo completions (in which \n   // case we will need to introduce completion buffers)\n   FIFO#(Tuple2#(Bit#(6),Bit#(6))) tag_mismatch <- mkSizedFIFO(32);\n\n   for (Integer selectReg = 0; selectReg < valueOf(numWriteClients); selectReg = selectReg + 1)\n       rule loadChannel;\n\t  MemRequest req <- writeClients[selectReg].writeReq.get();\n\t  //$display(\"dmawrite.loadChannel activeChan=%d handle=%h addr=%h burst=%h debugReq=%d\", selectReg, req.sglId, req.offset, req.burstLen, debugReg);\n\t  if (bad_pointer(req.sglId))\n\t     dmaIndication.badPointer(req.sglId);\n\t  else begin\n\t     lreqFifo.enq(IRec{req:req, rename_tag:?, pa:?, chan:fromInteger(selectReg)});\n\t     sgl.request.put(tuple2(truncate(req.sglId),req.offset));\n\t  end\n       endrule\n   \n   rule checkSglResp;\n      let physAddr <- sgl.response.get;\n      let req = lreqFifo.first.req;\n      let chan = lreqFifo.first.chan;\n      lreqFifo.deq();\n      if (physAddr <= (1 << valueOf(SGListPageShift0))) begin\n\t // squash request\n\t $display(\"dmaWrite: badAddr handle=%d addr=%h physAddr=%h\", req.sglId, req.offset, physAddr);\n\t dmaIndication.badAddr(req.sglId, extend(req.offset), extend(physAddr));\n      end\n      else begin\n\t reqFifo.enq(IRec{req:req, rename_tag:truncate(chan), pa:physAddr, chan:chan});\n      end\n   endrule\n\n   interface DmaDbg dbg;\n      method ActionValue#(DmaDbgRec) dbg();\n\t return DmaDbgRec{x:fromInteger(valueOf(numWriteClients)), y:?, z:?, w:?};\n      endmethod\n      method ActionValue#(Bit#(64)) getMemoryTraffic(Bit#(32) client);\n\t return (valueOf(numWriteClients) > 0 && client < fromInteger(valueOf(numWriteClients))) ? beatCounts[client] : 0;\n      endmethod\n   endinterface\n   \n   interface MemWriteClient write_client;\n      interface Get writeReq;\n\t method ActionValue#(PhysMemRequest#(addrWidth)) get();\n\t    let req = reqFifo.first.req;\n\t    let physAddr = reqFifo.first.pa;\n\t    let rename_tag = reqFifo.first.rename_tag;\n\t    reqFifo.deq;\n\t    //$display(\"dmaWrite addr physAddr=%h burstReg=%d\", physAddr, req.burstLen);\n   \n\t    dreqFifo.enq(reqFifo.first);\n\t    return PhysMemRequest{addr:physAddr, burstLen:req.burstLen, tag:rename_tag};\n\t endmethod\n      endinterface\n      interface Get writeData;\n\t method ActionValue#(MemData#(dataWidth)) get();\n\t    let activeChan = dreqFifo.first.chan;\n\t    let req = dreqFifo.first.req;\n\t    let rename_tag = dreqFifo.first.rename_tag;\n\t    MemData#(dataWidth) tagdata = unpack(0);\n\t    if (valueOf(numWriteClients) > 0)\n\t       tagdata <- writeClients[activeChan].writeData.get();\n\t    let burstLen = burstReg;\n\t    if (burstLen == 0)\n\t       burstLen = req.burstLen >> beat_shift;\n\n\t    if (burstLen == 1) begin\n\t       dreqFifo.deq();\n\t       respFifo.enq(dreqFifo.first);\n\t    end\n\n\t    //$display(\"dmaWrite data data=%h burstLen=%d\", tagdata.data, burstLen);\n\t    burstReg <= burstLen-1;\n\t    if(valueOf(numWriteClients) > 0)\n\t       beatCounts[activeChan] <= beatCounts[activeChan]+1;\n\t    \n\t    return MemData { data: tagdata.data,  tag: rename_tag };\n\t endmethod\n      endinterface\n      interface Put writeDone;\n\t method Action put(Bit#(6) resp);\n\t    let activeChan = respFifo.first.chan;\n\t    let rename_tag = respFifo.first.rename_tag;\n\t    let orig_tag = respFifo.first.req.tag;\n\t    if (resp != rename_tag) begin\n\t       tag_mismatch.enq(tuple2(resp,rename_tag));\n\t       $display(\"mkMemWriteInternal::tag_mismatch %d %d\", resp, rename_tag);\n\t    end\n\t    respFifo.deq();\n\t    if (valueOf(numWriteClients) > 0) begin\n\t       writeClients[activeChan].writeDone.put(orig_tag);\n\t    end\n\t endmethod\n      endinterface\n   endinterface\n   interface Get tagMismatch = fifoToGet(tag_mismatch);\nendmodule\n\n//\n// @brief Creates a Dma controller for Dma read and write clients\n//\n// @param dmaIndication Interface for notifying software\n// @param readClients The read clients.\n// @param writeClients The writeclients.\n//\nmodule mkMemServer#(DmaIndication dmaIndication,\n\t\t    Vector#(numReadClients, MemReadClient#(dataWidth)) readClients,\n\t\t    Vector#(numWriteClients, MemWriteClient#(dataWidth)) writeClients)\n\n   (MemServer#(addrWidth, dataWidth))\n   \n   provisos (Add#(1,a__,dataWidth),\n\t     Add#(b__, TSub#(addrWidth, 12), 32),\n\t     Add#(c__, 12, addrWidth),\n\t     Add#(d__, addrWidth, 64),\n\t     Add#(e__, TSub#(addrWidth, 12), MemOffsetSize),\n\t     Add#(f__, c__, MemOffsetSize),\n\t     Add#(g__, addrWidth, 40),\n\t     Mul#(TDiv#(dataWidth, 8), 8, dataWidth));\n   \n   MMU#(addrWidth) sgl <- mkMMU(dmaIndication);\n   FIFO#(void)   addrReqFifo <- mkFIFO;\n\n   MemReadInternal#(addrWidth, dataWidth) reader <- mkMemReadInternal(readClients, dmaIndication, sgl.addr[0]);\n   MemWriteInternal#(addrWidth, dataWidth) writer <- mkMemWriteInternal(writeClients, dmaIndication, sgl.addr[1]);\n   \n   rule tag_mismatch_read;\n      let rv <- reader.tagMismatch.get;\n      dmaIndication.tagMismatch(ChannelType_Read, extend(tpl_1(rv)), extend(tpl_2(rv)));\n   endrule\n   \n   rule tag_mismatch_write;\n      let rv <- writer.tagMismatch.get;\n      dmaIndication.tagMismatch(ChannelType_Write, extend(tpl_1(rv)), extend(tpl_2(rv)));\n   endrule\n\n   rule sglistEntry;\n      addrReqFifo.deq;\n      let physAddr <- sgl.addr[0].response.get;\n      dmaIndication.addrResponse(zeroExtend(physAddr));\n   endrule\n   \n   interface DmaConfig request;\n      method Action getStateDbg(ChannelType rc);\n\t let rv = ?;\n\t if (rc == ChannelType_Read)\n\t    rv <- reader.dbg.dbg;\n\t else\n\t    rv <- writer.dbg.dbg;\n\t dmaIndication.reportStateDbg(rv);\n      endmethod\n      method Action getMemoryTraffic(ChannelType rc, Bit#(32) client);\n\t if (rc == ChannelType_Read) begin\n\t    let rv <- reader.dbg.getMemoryTraffic(client);\n\t    dmaIndication.reportMemoryTraffic(rv);\n\t end\n\t else begin\n\t    let rv <- writer.dbg.getMemoryTraffic(client);\n\t    dmaIndication.reportMemoryTraffic(rv);\n\t end\n      endmethod\n      method Action sglist(Bit#(32) pref, Bit#(MemOffsetSize) addr, Bit#(32) len);\n\t if (bad_pointer(pref))\n\t    dmaIndication.badPointer(pref);\n`ifdef SIMULATION\n\t let va <- pareff(pref, len);\n         addr[39:32] = truncate(pref);\n`endif\n\t sgl.sglist(pref, addr, len);\n      endmethod\n      method Action region(Bit#(32) pointer, Bit#(40) barr8, Bit#(8) off8, Bit#(40) barr4, Bit#(8) off4, Bit#(40) barr0, Bit#(8) off0);\n\t sgl.region(pointer,barr8,off8,barr4,off4,barr0,off0);\n      endmethod\n      method Action addrRequest(Bit#(32) pointer, Bit#(32) offset);\n\t addrReqFifo.enq(?);\n\t sgl.addr[0].request.put(tuple2(truncate(pointer), extend(offset)));\n      endmethod\n   endinterface\n\n   interface MemMaster master;\n      interface MemReadClient read_client = reader.read_client;\n      interface MemWriteClient write_client = writer.write_client;\n   endinterface\nendmodule\n\n"
  },
  {
    "path": "lib/deprecated/RegFileA.bsv",
    "content": "// Copyright (c) 2013 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\nimport FIFOF::*;\nimport FIFO::*;\nimport GetPut::*;\nimport Connectable::*;\nimport RegFile::*;\nimport ConnectalMemTypes::*;\n\n\ninterface RegFileA#(type index_t, type data_t);\n   method Action upd(index_t addr, data_t d);\n   method ActionValue#(data_t) sub(index_t addr);\nendinterface\n\ntypedef struct {\n   Bit#(addrWidth) addr;\n   Bit#(8) bc;\n   Bit#(6) tag;\n   Bool    last;\n   } AddrBeat#(numeric type addrWidth) deriving (Bits);\n\ninterface AddressGenerator#(numeric type addrWidth);\n   interface Put#(PhysMemRequest#(addrWidth)) request;\n   interface Get#(AddrBeat#(addrWidth)) addrBeat;\nendinterface\n\nmodule mkAddressGenerator(AddressGenerator#(addrWidth));\n   FIFOF#(PhysMemRequest#(addrWidth)) requestFifo <- mkFIFOF();\n   FIFOF#(AddrBeat#(addrWidth)) addrBeatFifo <- mkFIFOF();\n   Reg#(Bit#(addrWidth)) addrReg <- mkReg(0);\n   Reg#(Bit#(8)) burstCountReg <- mkReg(0);\n   Reg#(Bool) isLastReg <- mkReg(False);\n\n   rule addrBeatRule;\n      let req = requestFifo.first();\n      let addr = addrReg;\n      let burstCount = burstCountReg;\n      let isLast = isLastReg;\n\n      let nextIsLast = burstCount == 2;\n      let nextBurstCount = burstCount - 1;\n\n      addrReg <= addr + 1;\n      burstCountReg <= nextBurstCount;\n      isLastReg <= nextIsLast;\n      if (isLast) begin\n\t requestFifo.deq();\n      end\n      addrBeatFifo.enq(AddrBeat { addr: addr, bc: burstCount, last: isLast, tag: req.tag});\n   endrule\n\n   interface Put request;\n      method Action put(PhysMemRequest#(addrWidth) req);\n\t requestFifo.enq(req);\n\t addrReg <= req.addr;\n\t burstCountReg <= req.burstLen;\n\t isLastReg <= (req.burstLen == 1);\n      endmethod\n   endinterface\n   interface Get addrBeat;\n      method ActionValue#(AddrBeat#(addrWidth)) get();\n\t addrBeatFifo.deq();\n\t return addrBeatFifo.first();\n      endmethod\n   endinterface\nendmodule\n\nmodule mkMemSlaveFromRegFile#(RegFileA#(Bit#(regFileAddrWidth), Bit#(busDataWidth)) rf) (MemSlave#(busAddrWidth, busDataWidth))\n   provisos(Add#(a__, regFileAddrWidth, busAddrWidth));\n\n   Reg#(Bit#(regFileAddrWidth)) writeAddrReg <- mkReg(0);\n   Reg#(Bit#(8)) writeBurstCountReg <- mkReg(0);\n   FIFOF#(void) writeRespFifo <- mkFIFOF();\n   FIFOF#(Bit#(6)) writeTagFifo <- mkFIFOF();\n   FIFO#(PhysMemRequest#(busAddrWidth)) req_aw_fifo <- mkSizedFIFO(1);\n   \n   AddressGenerator#(busAddrWidth) readAddrGenerator <- mkAddressGenerator();\n\n   Bool verbose = False;\n   interface MemReadServer read_server;\n      interface Put readReq;\n\t method Action put(PhysMemRequest#(busAddrWidth) req);\n            if (verbose) $display(\"axiSlave.read.readAddr %h bc %d\", req.addr, req.burstLen);\n\t    readAddrGenerator.request.put(req);\n\t endmethod\n      endinterface\n      interface Get readData;\n\t method ActionValue#(MemData#(busDataWidth)) get();\n\t    let addrBeat <- readAddrGenerator.addrBeat.get();\n   \t    let addr = addrBeat.addr;\n   \t    let tag = addrBeat.tag;\n   \t    let burstCount = addrBeat.bc;\n            Bit#(regFileAddrWidth) regFileAddr = truncate(addr/fromInteger(valueOf(TDiv#(busDataWidth,8))));\n            let data <- rf.sub(regFileAddr);\n            if (verbose) $display(\"read_server.readData %h %h %d\", addr, data, burstCount);\n            return MemData { data: data, tag: tag, last: addrBeat.last };\n\t endmethod\n      endinterface\n   endinterface\n   interface MemWriteServer write_server;\n      interface Put writeReq;\n\t method Action put(PhysMemRequest#(busAddrWidth) req);\n            req_aw_fifo.enq(req);\n            if (verbose) $display(\"write_server.writeAddr %h bc %d\", req.addr, req.burstLen);\n\t endmethod\n      endinterface\n      interface Put writeData;\n\t method Action put(MemData#(busDataWidth) resp);\n\t    let addr = writeAddrReg;\n            let burstCount = writeBurstCountReg;\n            if (burstCount == 0) begin\n\t       let req = req_aw_fifo.first;\n               addr = truncate(req.addr/fromInteger(valueOf(TDiv#(busDataWidth,8))));\n               burstCount = req.burstLen;\n               writeTagFifo.enq(req.tag);\n\t       req_aw_fifo.deq;\n\t    end\n            if (verbose) $display(\"writeData %h %h %d\", addr, resp.data, burstCount);\n            rf.upd(addr, resp.data);\n            writeAddrReg <= addr + 1;\n            writeBurstCountReg <= burstCount - 1;\n            if (verbose) $display(\"write_server.writeData %h %h %d\", addr, resp.data, burstCount);\n            if (burstCount == 1)\n               writeRespFifo.enq(?);\n\t endmethod\n      endinterface\n      interface Get writeDone;\n\t method ActionValue#(Bit#(6)) get();\n            writeRespFifo.deq;\n\t    writeTagFifo.deq;\n            return writeTagFifo.first;\n\t endmethod\n      endinterface\n   endinterface\nendmodule\n\n"
  },
  {
    "path": "lib/deprecated/SGListComb.bsv",
    "content": "// Copyright (c) 2013 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\n// BSV Libraries\nimport RegFile::*;\nimport FIFO::*;\nimport FIFOF::*;\nimport Vector::*;\nimport GetPut::*;\nimport BRAMFIFO::*;\nimport BRAM::*;\nimport ConnectalMemTypes::*;\nimport StmtFSM::*;\nimport ClientServer::*;\nimport ConnectalMemory::*;\n\ntypedef 32 MaxNumSGLists;\ntypedef Bit#(TLog#(MaxNumSGLists)) SGListId;\ntypedef 12 SGListPageShift0;\ntypedef 16 SGListPageShift4;\ntypedef 20 SGListPageShift8;\ntypedef Bit#(TLog#(MaxNumSGLists)) RegionsIdx;\ntypedef Tuple2#(SGListId,Bit#(MemOffsetSize)) ReqTup;\n\ninterface MMU#(numeric type addrWidth);\n   method Action sglist(Bit#(32) pointer, Bit#(40) paddr, Bit#(32) len);\n   method Action region(Bit#(32) ptr, Bit#(40) barr8, Bit#(8) off8, Bit#(40) barr4, Bit#(8) off4, Bit#(40) barr0, Bit#(8) off0);\n   interface Vector#(2,Server#(ReqTup,Bit#(addrWidth))) addr;\nendinterface\n\ntypedef union tagged{\n   Bit#(SGListPageShift0) OOrd0;\n   Bit#(SGListPageShift4) OOrd4;\n   Bit#(SGListPageShift8) OOrd8;\n} Offset deriving (Eq,Bits,FShow);\n\ntypedef union tagged{\n   Bit#(TSub#(MemOffsetSize,SGListPageShift0)) POrd0;\n   Bit#(TSub#(MemOffsetSize,SGListPageShift4)) POrd4;\n   Bit#(TSub#(MemOffsetSize,SGListPageShift8)) POrd8;\n} Page deriving (Eq,Bits,FShow);\n\ntypedef struct {\n   Bit#(MemOffsetSize) barrier;\n   Bit#(8) idxOffset;\n   } Region deriving (Eq,Bits,FShow);\n\nmodule mkMMU#(DmaIndication dmaIndication)(MMU#(addrWidth))\n   \n   provisos(Log#(MaxNumSGLists, listIdxSize),\n\t    Add#(listIdxSize,8, entryIdxSize),\n\t    Add#(c__, addrWidth, MemOffsetSize));\n\n   BRAM_Configure bramConfig = defaultValue;\n   bramConfig.latency        = 1;\n   BRAM2Port#(Bit#(entryIdxSize),Page) pages <- mkBRAM2Server(bramConfig);\n   BRAM2Port#(RegionsIdx, Region)       reg8 <- mkBRAM2Server(bramConfig);\n   BRAM2Port#(RegionsIdx, Region)       reg4 <- mkBRAM2Server(bramConfig);\n   BRAM2Port#(RegionsIdx, Region)       reg0 <- mkBRAM2Server(bramConfig);\n\n   Vector#(2,FIFOF#(Bit#(entryIdxSize)))  rp <- replicateM(mkFIFOF);\n   Vector#(2,FIFOF#(Offset))            offs <- replicateM(mkFIFOF);\n   Vector#(2,FIFOF#(ReqTup))            reqs <- replicateM(mkFIFOF);\n   Reg#(Bit#(8))                      idxReg <- mkReg(0);\n   \n   let page_shift0 = fromInteger(valueOf(SGListPageShift0));\n   let page_shift4 = fromInteger(valueOf(SGListPageShift4));\n   let page_shift8 = fromInteger(valueOf(SGListPageShift8));\n   \n   let ord0 = 40'd1 << page_shift0;\n   let ord4 = 40'd1 << page_shift4;\n   let ord8 = 40'd1 << page_shift8;\n\n   function BRAMServer#(a,b) portsel(BRAM2Port#(a,b) x, Integer i);\n      if(i==0)\n\t return x.portA;\n      else\n\t return x.portB;\n   endfunction\n\n   FIFO#(Tuple4#(RegionsIdx,Region,Region,Region)) regionFifo <- mkFIFO();\n\n   for(Integer i = 0; i < 2; i=i+1) begin\n      rule req;\n\t Region region8 <- portsel(reg8,i).response.get;\n\t Region region4 <- portsel(reg4,i).response.get;\n\t Region region0 <- portsel(reg0,i).response.get;\n\n\t reqs[i].deq;\n\t let ptr = tpl_1(reqs[i].first);\n\t let off = tpl_2(reqs[i].first);\n\t Offset o = tagged OOrd0 0;\n\t Bit#(8) pbase = 0;\n\t Bit#(8) idxOffset = 0;\n\n\t Bit#(40) barrier8 = region8.barrier;\n\t Bit#(40) barrier4 = region4.barrier;\n\t Bit#(40) barrier0 = region0.barrier;\n\n\t Bit#(3) pageSize = 0;\n\t if (off < barrier8) begin\n\t    //$display(\"request: ptr=%h off=%h barrier8=%h\", ptr, off, barrier8);\n\t    o = tagged OOrd8 truncate(off);\n\t    pbase = truncate(off>>page_shift8);\n\t    pageSize = 3;\n\t    idxOffset = region8.idxOffset;\n\t end\n\t else if (off < barrier4) begin\n\t    //$display(\"request: ptr=%h off=%h barrier4=%h\", ptr, off, barrier4);\n\t    o = tagged OOrd4 truncate(off);\n\t    pbase = truncate(off>>page_shift4);\n\t    pageSize = 2;\n\t    idxOffset = region4.idxOffset;\n\t end\n\t else if (off < barrier0) begin\n\t    //$display(\"request: ptr=%h off=%h barrier0=%h\", ptr, off, barrier0);\n\t    o = tagged OOrd0 truncate(off);\n\t    pbase = truncate(off>>page_shift0);\n\t    pageSize = 1;\n\t    idxOffset = region0.idxOffset;\n\t end\n\t else begin\n\t    pageSize = 0;\n\t    //dmaIndication.badAddrTrans(extend(ptr), extend(off), barrier0);\n\t end\n\t offs[i].enq(o);\n\t Bit#(8) p = pbase + idxOffset;\n\t if (pageSize == 3) begin\n\t    //$display(\"request: ptr=%h off=%h barrier8=%h\", ptr, off, barrier8);\n\t end\n\t else if (pageSize == 2) begin\n\t end\n\t else if (pageSize == 1) begin\n\t end\n\t else if (pageSize == 0) begin\n\t    //FIXME offset\n\t    //$display(\"mkMMU.addr[%d].request.put: ERROR   ptr=%h off=%h\\n\", i, ptr, off);\n\t    dmaIndication.badAddrTrans(extend(ptr), -1, 0);\n\t end\n\t let address = {ptr-1,p};\n\t //$display(\"pages[%d].read %h\", i, rp[i].first());\n\t portsel(pages, i).request.put(BRAMRequest{write:False, responseOnWrite:False, address:address, datain:?});\n      endrule\n   end\n\n   Vector#(2,Server#(ReqTup,Bit#(addrWidth))) addrServers;\n   for(Integer i = 0; i < 2; i=i+1)\n      addrServers[i] =\n      (interface Server#(ReqTup,Bit#(addrWidth));\n\t  interface Put request;\n\t     method Action put(ReqTup req);\n\t     \t match { .ptr, .off } = req;\n\t \t portsel(reg8, i).request.put(BRAMRequest{write:False, responseOnWrite:False, address:truncate(ptr-1), datain:?});\n\t \t portsel(reg4, i).request.put(BRAMRequest{write:False, responseOnWrite:False, address:truncate(ptr-1), datain:?});\n\t \t portsel(reg0, i).request.put(BRAMRequest{write:False, responseOnWrite:False, address:truncate(ptr-1), datain:?});\n\t \t reqs[i].enq(req);\n\t     endmethod\n\t  endinterface\n\t  interface Get response;\n\t     method ActionValue#(Bit#(addrWidth)) get();\n\t     \t    let page <- portsel(pages, i).response.get;\n    \t      \t    let offset <- toGet(offs[i]).get();\n\t  \t    //$display(\"pages[%d].response page=%h offset=%h\", i, page, offset);\n\t \t    Bit#(MemOffsetSize) rv = 0;\n\t            case (offset) matches\n\t            tagged OOrd0 .o:\n        \t       begin\n        \t\t  case (page) matches\n        \t\t     tagged POrd4 .p:\n        \t\t\t$display(\"OOrd0 vs POrd4\");\n        \t\t     tagged POrd8 .p:\n        \t\t\t$display(\"OOrd0 vs POrd8\");\n        \t\t  endcase\n        \t\t  rv = {page.POrd0,o};\n        \t       end\n        \t    tagged OOrd4 .o:\n        \t       begin\n        \t\t  case (page) matches\n        \t\t     tagged POrd0 .p:\n        \t\t\t$display(\"OOrd4 vs POrd0\");\n        \t\t     tagged POrd8 .p:\n        \t\t\t$display(\"OOrd4 vs POrd8\");\n        \t\t  endcase\n        \t\t  rv = {page.POrd4,o};\n        \t       end\n        \t    tagged OOrd8 .o:\n        \t       begin\n        \t\t  case (page) matches\n        \t\t     tagged POrd0 .p:\n        \t\t\t$display(\"OOrd8 vs POrd0\");\n        \t\t     tagged POrd4 .p:\n        \t\t\t$display(\"OOrd8 vs POrd4\");\n        \t\t  endcase\n        \t\t  rv = {page.POrd8,o};\n        \t       end\n        \tendcase\n\t\treturn truncate(rv);\n\t     endmethod\n\t  endinterface\n       endinterface);\n\n   FIFO#(Tuple2#(SGListId,Bit#(40))) configRespFifo <- mkFIFO;\n   rule sendConfigResp;\n      match { .ptr, .barr0 } <- toGet(configRespFifo).get();\n      dmaIndication.configResp(extend(ptr), barr0);\n   endrule\n\n   FIFO#(Tuple3#(SGListId,Bit#(40),Bit#(32))) sglistFifo <- mkFIFO();\n   rule sglistRule;\n      match { .ptr, .paddr, .len } <- toGet(sglistFifo).get();\n\n      // $display(\"sglist(ptr=%d, paddr=%h, len=%h\", ptr, paddr,len);\n      if (idxReg+1 == 0) begin\n\t $display(\"sglist: exceeded maximun length of sglist\");\n\t dmaIndication.badNumberEntries(extend(ptr),len, extend(idxReg));\n      end\n      else begin\n\t Page page = tagged POrd0 0;\n\t if (len == 0) begin\n\t    idxReg <= 0;\n\t end\n\t else begin\n\t    idxReg <= idxReg+1;\n\t    if (extend(len) == ord0) begin\n\t       page = tagged POrd0 truncate(paddr>>page_shift0);\n\t    end\n\t    else if (extend(len) == ord4) begin\n\t       page = tagged POrd4 truncate(paddr>>page_shift4);\n\t    end\n\t    else if (extend(len) == ord8) begin\n\t       page = tagged POrd8 truncate(paddr>>page_shift8);\n\t    end\n\t    if (extend(len) > ord8) begin\n\t       $display(\"mkMMU::sglist unsupported length %h\", len);\n\t       dmaIndication.badPageSize(extend(ptr), len);\n\t    end\n\t end\n\t configRespFifo.enq(tuple2(truncate(ptr), 40'haaaaaaaa));\n\t portsel(pages, 0).request.put(BRAMRequest{write:True, responseOnWrite:False, address:{truncate(ptr-1),idxReg}, datain:page});\n      end\n   endrule\n\n   rule regionRule;\n      match { .ptr, .region8, .region4, .region0 } <- toGet(regionFifo).get();\n      let idx = ptr-1;\n      portsel(reg8, 0).request.put(BRAMRequest{write:True, responseOnWrite:False, address: idx, datain: region8});\n      portsel(reg4, 0).request.put(BRAMRequest{write:True, responseOnWrite:False, address: idx, datain: region4});\n      portsel(reg0, 0).request.put(BRAMRequest{write:True, responseOnWrite:False, address: idx, datain: region0});\n      //$display(\"region ptr=%d off8=%h off4=%h off0=%h\", ptr, off8, off4, off0);\n      configRespFifo.enq(tuple2(ptr, region0.barrier));\n   endrule\n\n   // FIXME: split this into three methods?\n   method Action region(Bit#(32) ptr, Bit#(40) barr8, Bit#(8) off8, Bit#(40) barr4, Bit#(8) off4, Bit#(40) barr0, Bit#(8) off0);\n      Region region8 = Region { barrier: barr8, idxOffset: off8 };\n      Region region4 = Region { barrier: barr4, idxOffset: off4 };\n      Region region0 = Region { barrier: barr0, idxOffset: off0 };\n      regionFifo.enq(tuple4(truncate(ptr),region8,region4,region0));\n   endmethod\n\n   method Action sglist(Bit#(32) ptr, Bit#(40) paddr, Bit#(32) len);\n      sglistFifo.enq(tuple3(truncate(ptr), paddr, len));\n   endmethod\n\n   interface addr = addrServers;\n\nendmodule\n\ninterface SglAddrServer#(numeric type addrWidth, numeric type numServers);\n   interface Vector#(numServers,Server#(ReqTup,Bit#(addrWidth))) servers;\nendinterface\n\nmodule mkSglAddrServer#(Server#(ReqTup,Bit#(addrWidth)) server) (SglAddrServer#(addrWidth,numServers));\n   \n   FIFOF#(Bit#(TAdd#(1,TLog#(numServers)))) tokFifo <- mkSizedFIFOF(3);\n   Vector#(numServers, Server#(ReqTup,Bit#(addrWidth))) addrServers;\n   Reg#(Bit#(TLog#(numServers))) arb <- mkReg(0);\n\n   // this is a very crude arbiter.  something more sophisticated may be required (mdk)\n   rule inc_arb;\n      arb <= arb+1;\n   endrule\n   \n   for(Integer i = 0; i < valueOf(numServers); i=i+1)\n      addrServers[i] = \n      (interface Server#(ReqTup,Bit#(addrWidth));\n\t  interface Put request;\n\t     method Action put(ReqTup req) if (arb == fromInteger(i));\n\t\ttokFifo.enq(fromInteger(i));\n\t\tserver.request.put(req);\n\t     endmethod\n\t  endinterface\n\t  interface Get response;\n\t     method ActionValue#(Bit#(addrWidth)) get() if (tokFifo.first == fromInteger(i));\n\t\ttokFifo.deq;\n\t\tlet rv <- server.response.get;\n\t\treturn rv;\n\t     endmethod\n\t  endinterface\n       endinterface);\n\n   interface servers = addrServers;\n\nendmodule\n"
  },
  {
    "path": "lib/deprecated/bsv_Makefile",
    "content": "\n\ntest: testspi testAdapter\n\ntestspi: ConnectalSpi.bsv\n\tbsc -check-assert -sim -u -g mkSpiTestBench ConnectalSpi.bsv\n\tbsc -check-assert -sim -u -e mkSpiTestBench -o spiTestBench mkSpiTestBench.ba\n\t./spiTestBench -V spi.vcd\n\ntestgearbox: GearboxTb.bsv\n\tbsc -sim -u -g mkGearboxTb GearboxTb.bsv\n\tbsc -sim -u -e mkGearboxTb -o testGearbox mkGearboxTb.ba\n\t./testGearbox\n\nmkGearboxTb.v: GearboxTb.bsv\n\tbsc -verilog -u -g mkGearboxTb GearboxTb.bsv\n\ntestAdapter: Adapter.bsv\n\tbsc -p +:../lib/bsv -check-assert -sim -u -g mkAdapterTb Adapter.bsv\n\tbsc -check-assert -sim -u -e mkAdapterTb -o testAdapter mkAdapterTb.ba\n\t./testAdapter\n\ntestConnectalReadyQueue: ConnectalReadyQueue.bsv\n\tbsc -check-assert -sim -u -g mkRQTB ConnectalReadyQueue.bsv\n\tbsc -check-assert -sim -u -e mkRQTB -o testConnectalReadyQueue mkRQTB.ba\n\t./testConnectalReadyQueue\n\nmkSPI20.v: ConnectalSpi.bsv\n\tbsc -verilog -u -g mkSPI20 ConnectalSpi.bsv\n"
  },
  {
    "path": "lib/deprecated/pcietestbench/Makefile",
    "content": "INTERFACES = PcieTestBenchRequest PcieTestBenchIndication\n\nBSVFILES = PcieTestBench.bsv Top.bsv\nCPPFILES=testpcie.cpp\n\ninclude ../../Makefile.common\n"
  },
  {
    "path": "lib/deprecated/pcietestbench/PcieTestBench.bsv",
    "content": "\n// Copyright (c) 2014 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\nimport Clocks            :: *;\nimport Connectable       :: *;\nimport DefaultValue      :: *;\nimport FIFO              :: *;\nimport GetPut            :: *;\nimport PCIE              :: *;\n\nimport AxiCsr            :: *;\nimport AxiSlaveEngine    :: *;\nimport AxiMasterEngine   :: *;\nimport PcieSplitter      :: *;\n\n// copied from PCIE.bsv because connectalgen cannot handle TMul#()\ntypedef struct {\n   Bit#(1)               sof;\n   Bit#(1)               eof;\n   Bit#(7)               hit;\n   Bit#(16)              be;\n   Bit#(32)              data0;\n   Bit#(32)              data1;\n   Bit#(32)              data2;\n   Bit#(32)              data3;\n} TLPData16 deriving (Bits, Eq);\n\n// copied from PCIE.bsv because connectalgen cannot parse the file\ntypedef enum {\n   MEM_READ_3DW_NO_DATA = 0,\n   MEM_READ_4DW_NO_DATA = 1,\n   MEM_WRITE_3DW_DATA   = 2,\n   MEM_WRITE_4DW_DATA   = 3\n   } TLPPacketFormat deriving (Bits, Eq);\n\n// copied from PCIE.bsv because connectalgen cannot parse the file\ntypedef enum {\n   MEMORY_READ_WRITE   = 0,\n   MEMORY_READ_LOCKED  = 1,\n   IO_REQUEST          = 2,\n   UNKNOWN_TYPE_3      = 3,\n   CONFIG_0_READ_WRITE = 4,\n   CONFIG_1_READ_WRITE = 5,\n   UNKNOWN_TYPE_6      = 6,\n   UNKNOWN_TYPE_7      = 7,\n   UNKNOWN_TYPE_8      = 8,\n   UNKNOWN_TYPE_9      = 9,\n   COMPLETION          = 10,\n   COMPLETION_LOCKED   = 11,\n   UNKNOWN_TYPE_12     = 12,\n   UNKNOWN_TYPE_13     = 13,\n   UNKNOWN_TYPE_14     = 14,\n   UNKNOWN_TYPE_15     = 15,\n   MSG_ROUTED_TO_ROOT  = 16,\n   MSG_ROUTED_BY_ADDR  = 17,\n   MSG_ROUTED_BY_ID    = 18,\n   MSG_ROOT_BROADCAST  = 19,\n   MSG_LOCAL           = 20,\n   MSG_GATHER          = 21,\n   UNKNOWN_TYPE_22     = 22,\n   UNKNOWN_TYPE_23     = 23,\n   UNKNOWN_TYPE_24     = 24,\n   UNKNOWN_TYPE_25     = 25,\n   UNKNOWN_TYPE_26     = 26,\n   UNKNOWN_TYPE_27     = 27,\n   UNKNOWN_TYPE_28     = 28,\n   UNKNOWN_TYPE_29     = 29,\n   UNKNOWN_TYPE_30     = 30,\n   UNKNOWN_TYPE_31     = 31\n   } TLPPacketType deriving (Bits, Eq);\n\n// copied from PCIE.bsv because connectalgen cannot parse the file\ntypedef struct {Bit#(8) hit;\n\t\tBit#(8) sof;\n\t\tBit#(8) eof;\n\t\tBit#(16) tlpbe;\n\t\tBit#(16) tag;\n\t\tBit#(16) length;\n\t\tTLPPacketType pkttype;\n\t\tTLPPacketFormat format;\n\t\tBit#(8) firstbe;\n\t\tBit#(8) lastbe;\n\t\tBit#(32) addr;\n   Bit#(32) data;\n   } Pcie3dwHeader deriving (Bits);\n\ninterface PcieTestBenchIndication;\n   method Action tlpout(TLPData16 tlp);\nendinterface\n\ninterface PcieTestBenchRequest;\n   method Action sendReadRequest(Bit#(8) hit, Bit#(32) addr, Bit#(8) length, Bit#(8) tag);\nendinterface\n\n\nmodule mkPcieTestBenchRequest#(PcieTestBenchIndication indication)(PcieTestBenchRequest);\n\n   Clock defaultClock <- exposeCurrentClock();\n   Reset defaultReset <- exposeCurrentReset();\n   MakeResetIfc portalResetIfc <- mkReset(10, False, defaultClock);\n   PciId my_id = PciId { bus: 1, dev: 1, func: 0};\n   Bit#(64) board_content_id = 'hdeadbeefd00df00d;\n   Reg#(Bit#(32)) tlp_portal_drop_count <- mkReg(0);\n   Reg#(Bit#(32)) tlp_axi_drop_count <- mkReg(0);\n\n\n   AxiMasterEngine axiMasterEngine <- mkAxiMasterEngine(my_id);\n   AxiControlAndStatusRegs axiCsr  <- mkAxiControlAndStatusRegs( board_content_id,\n\t\t\t\t\t\t\t\tmy_id,\n\t\t\t\t\t\t\t\t0,\n\t\t\t\t\t\t\t\t0,\n\t\t\t\t\t\t\t\ttlp_portal_drop_count,\n\t\t\t\t\t\t\t\ttlp_axi_drop_count,\n\t\t\t\t\t\t\t\tportalResetIfc);\n   Reg#(Bit#(32)) timestamp <- mkReg(0);\n   rule timebase;\n      timestamp <= timestamp + 1;\n   endrule\n   mkConnection(axiMasterEngine.master, axiCsr.slave);\n   rule tlp_out;\n      let tlp <- axiMasterEngine.tlp_out.get();\n      TimestampedTlpData ttd = TimestampedTlpData { timestamp: timestamp, source: 4, tlp: tlp };\n      $display(\"%h\", ttd);\n      indication.tlpout(unpack(pack(tlp)));\n   endrule\n   \n   method Action sendReadRequest(Bit#(8) hit, Bit#(32) addr, Bit#(8) length, Bit#(8) tag);\n      $display(\"send3dwRequest hit=%d addr=%h length=%h tag=%d\", hit, addr, length, tag);\n      TLPMemoryIO3DWHeader hdr = defaultValue;\n      hdr.tag = truncate(tag);\n      hdr.length = extend(length);\n      hdr.format = PCIE::MEM_READ_3DW_NO_DATA;\n      hdr.pkttype = PCIE::MEMORY_READ_WRITE;\n      hdr.firstbe = 4'hf;\n      hdr.lastbe = (length == 1) ? 0 : 4'hf;\n      hdr.addr = truncate(addr >> 2);\n      hdr.data = 0;\n      TLPData#(16) tlp;\n      tlp.be = 16'hfff0;\n      tlp.sof = True;\n      tlp.eof = True;\n      tlp.hit = truncate(hit);\n      tlp.data = pack(hdr);\n      $display(\"tlp_in=%h\", tlp);\n      axiMasterEngine.tlp_in.put(tlp);\n   endmethod\nendmodule"
  },
  {
    "path": "lib/deprecated/pcietestbench/Top.bsv",
    "content": "import Vector::*;\nimport FIFO::*;\nimport Connectable::*;\nimport Directory::*;\nimport CtrlMux::*;\nimport Portal::*;\nimport ConnectalMemTypes::*;\nimport PcieTestBenchIndicationProxy::*;\nimport PcieTestBenchRequestWrapper::*;\nimport PcieTestBench::*;\n\ntypedef enum {IfcNames_PcieTestBenchIndication, IfcNames_PcieTestBenchRequest} IfcNames deriving (Eq,Bits);\n\nmodule mkConnectalTop(StdConnectalTop#(addrWidth));\n   PcieTestBenchIndicationProxy pcieTestBenchIndicationProxy <- mkPcieTestBenchIndicationProxy(IfcNames_PcieTestBenchIndication);\n   PcieTestBenchRequest pcieTestBenchRequest <- mkPcieTestBenchRequest(pcieTestBenchIndicationProxy.ifc);\n   PcieTestBenchRequestWrapper pcieTestBenchRequestWrapper <- mkPcieTestBenchRequestWrapper(IfcNames_PcieTestBenchRequest,pcieTestBenchRequest);\n   \n   Vector#(2,StdPortal) portals;\n   portals[0] = pcieTestBenchRequestWrapper.portalIfc; \n   portals[1] = pcieTestBenchIndicationProxy.portalIfc;\n   StdDirectory dir <- mkStdDirectory(portals);\n   let ctrl_mux <- mkSlaveMux(dir,portals);\n   \n   interface interrupt = getInterruptVector(portals);\n   interface slave = ctrl_mux;\n   interface masters = nil;\nendmodule : mkConnectalTop\n\n\n"
  },
  {
    "path": "lib/deprecated/pcietestbench/testpcie.cpp",
    "content": "\n#include <stdio.h>\n#include <stdlib.h>\n#include <unistd.h>\n#include <assert.h>\n#include <semaphore.h>\n\n#include \"PcieTestBenchIndication.h\"\n#include \"PcieTestBenchRequest.h\"\n#include \"GeneratedTypes.h\"\n\n\n\n\nclass PcieTestBenchIndication : public PcieTestBenchIndicationWrapper\n{  \n  sem_t sem;\npublic:\n  uint32_t cnt;\n  void incr_cnt(){\n    if (++cnt == 7)\n      exit(0);\n  }\n  void tlpout(const TLPData16 &tlp) {\n    fprintf(stderr, \"Received tlp: %08x%08x%08x%08x\\n\", tlp.data3, tlp.data2, tlp.data1, tlp.data0);\n    sem_post(&sem);\n  }\n  PcieTestBenchIndication(unsigned int id) : PcieTestBenchIndicationWrapper(id), cnt(0)\n  {\n    sem_init(&sem, 0, 0);\n  }\n  void wait() {\n    sem_wait(&sem);\n  }\n};\n\n\n\nint main(int argc, const char **argv)\n{\n  PcieTestBenchIndication *indication = new PcieTestBenchIndication(IfcNames_PcieTestBenchIndication);\n  PcieTestBenchRequestProxy *device = new PcieTestBenchRequestProxy(IfcNames_PcieTestBenchRequest);\n\n  device->sendReadRequest(1, 4, 1, 5);\n  indication->wait();\n  device->sendReadRequest(1, 0, 2, 7);\n  indication->wait();\n  device->sendReadRequest(1, 0, 3, 9);\n  indication->wait();\n  device->sendReadRequest(1, 0, 4, 10);\n  indication->wait();\n  device->sendReadRequest(1, 0, 5, 11);\n  indication->wait();\n  device->sendReadRequest(1, 0, 6, 12);\n  indication->wait();\n  device->sendReadRequest(1, 0, 7, 12);\n  indication->wait();\n  device->sendReadRequest(1, 0, 8, 12);\n  indication->wait();\n\n}\n"
  },
  {
    "path": "lib/deprecated/pcietestbench_dma_io/Makefile",
    "content": "INTERFACES = PcieTestBenchRequest PcieTestBenchIndication\n\nBSVFILES = PcieTestBench.bsv Top.bsv\nCPPFILES=testpcie.cpp\n\ninclude ../../Makefile.common\n"
  },
  {
    "path": "lib/deprecated/pcietestbench_dma_io/Memread.bsv",
    "content": "// Copyright (c) 2013 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\nimport FIFO::*;\nimport FIFOF::*;\nimport Vector::*;\nimport ConnectalMemTypes::*;\nimport MemReadEngine::*;\n\ninterface MemreadRequest;\n   method Action startRead(Bit#(32) pointer, Bit#(32) numWords, Bit#(32) burstLen, Bit#(32) iterCnt);\n   method Action getStateDbg();   \nendinterface\n\ninterface Memread;\n   interface MemreadRequest request;\n   interface MemReadClient#(64) dmaClient;\nendinterface\n\ninterface MemreadIndication;\n   method Action started(Bit#(32) numWords);\n   method Action reportStateDbg(Bit#(32) streamRdCnt, Bit#(32) mismatchCount);\n   method Action readDone(Bit#(32) mismatchCount);\nendinterface\n\nmodule mkMemread#(MemreadIndication indication) (Memread);\n\n   Reg#(SGLId)        pointer <- mkReg(0);\n   Reg#(Bit#(32))         numWords <- mkReg(0);\n   Reg#(Bit#(32))         burstLen <- mkReg(0);\n   Reg#(Bit#(32))          iterCnt <- mkReg(0);\n   \n   Reg#(Bit#(32))           srcGen <- mkReg(0);\n   Reg#(Bit#(32))    mismatchCount <- mkReg(0);\n   FIFOF#(Bit#(64))       readFifo <- mkFIFOF;\n   let                          re <- mkMemReadEngine(1, readFifo);\n   \n   rule start (iterCnt > 0);\n      iterCnt <= iterCnt-1;\n      re.start(pointer, 0, numWords*4, burstLen*4);\n   endrule\n   \n   rule finish;\n      let rv <- re.finish;\n      if (iterCnt == 0)\n\t indication.readDone(mismatchCount);\n   endrule\n   \n   rule check;\n      readFifo.deq;\n      let v = readFifo.first;\n      let expectedV = {srcGen+1,srcGen};\n      let misMatch = v != expectedV;\n      mismatchCount <= mismatchCount + (misMatch ? 1 : 0);\n      if (srcGen+2 == numWords)\n\t srcGen <= 0;\n      else\n\t srcGen <= srcGen+2;\n   endrule\n   \n   interface MemReadClient dmaClient = re.dmaClient;\n   interface MemreadRequest request;\n      method Action startRead(Bit#(32) rp, Bit#(32) nw, Bit#(32) bl, Bit#(32) ic);\n\t $display(\"startRead rdPointer=%d numWords=%h burstLen=%d iterCnt=%d\", rp, nw, bl, ic);\n\t indication.started(nw);\n\t pointer <= rp;\n\t numWords  <= nw;\n\t burstLen  <= bl;\n\t iterCnt <= ic;\n\t mismatchCount <= 0;\n\t srcGen <= 0;\n      endmethod\n      method Action getStateDbg();\n\t indication.reportStateDbg(iterCnt, mismatchCount);\n      endmethod\n   endinterface\nendmodule\n"
  },
  {
    "path": "lib/deprecated/pcietestbench_dma_io/PcieTestBench.bsv",
    "content": "// Copyright (c) 2014 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n`include \"ConnectalProjectConfig.bsv\"\nimport Clocks            :: *;\nimport Connectable       :: *;\nimport DefaultValue      :: *;\nimport FIFO              :: *;\nimport GetPut            :: *;\nimport FIFOF             :: *;\nimport Vector            :: *;\nimport AxiCsr            :: *;\nimport PCIE              :: *;\nimport AxiSlaveEngine    :: *;\nimport Portal            :: *;\nimport MemServer         :: *;\nimport SGList::*;\nimport MemReadEngine     :: *;\nimport AxiDma            :: *;\nimport ConnectalMemTypes          :: *;\nimport AxiMasterSlave    :: *;\nimport MemServerRequestWrapper::*;\nimport SGListConfigRequestWrapper::*;\nimport MemServerIndicationProxy::*;\nimport SGListConfigIndicationProxy::*;\n\n// copied from PCIE.bsv because connectalgen cannot handle TMul#()\ntypedef struct {\n   Bit#(32)              data0;\n   Bit#(32)              data1;\n   Bit#(32)              data2;\n   Bit#(32)              data3;\n   Bit#(32)              data4;\n   Bit#(32)              data5;\n} TsTLPData16 deriving (Bits, Eq);\n\n// copied from PCIE.bsv because connectalgen cannot parse the file\ntypedef enum {\n   MEM_READ_3DW_NO_DATA = 0,\n   MEM_READ_4DW_NO_DATA = 1,\n   MEM_WRITE_3DW_DATA   = 2,\n   MEM_WRITE_4DW_DATA   = 3\n   } TLPPacketFormat deriving (Bits, Eq);\n\n// copied from PCIE.bsv because connectalgen cannot parse the file\ntypedef enum {\n   MEMORY_READ_WRITE   = 0,\n   MEMORY_READ_LOCKED  = 1,\n   IO_REQUEST          = 2,\n   UNKNOWN_TYPE_3      = 3,\n   CONFIG_0_READ_WRITE = 4,\n   CONFIG_1_READ_WRITE = 5,\n   UNKNOWN_TYPE_6      = 6,\n   UNKNOWN_TYPE_7      = 7,\n   UNKNOWN_TYPE_8      = 8,\n   UNKNOWN_TYPE_9      = 9,\n   COMPLETION          = 10,\n   COMPLETION_LOCKED   = 11,\n   UNKNOWN_TYPE_12     = 12,\n   UNKNOWN_TYPE_13     = 13,\n   UNKNOWN_TYPE_14     = 14,\n   UNKNOWN_TYPE_15     = 15,\n   MSG_ROUTED_TO_ROOT  = 16,\n   MSG_ROUTED_BY_ADDR  = 17,\n   MSG_ROUTED_BY_ID    = 18,\n   MSG_ROOT_BROADCAST  = 19,\n   MSG_LOCAL           = 20,\n   MSG_GATHER          = 21,\n   UNKNOWN_TYPE_22     = 22,\n   UNKNOWN_TYPE_23     = 23,\n   UNKNOWN_TYPE_24     = 24,\n   UNKNOWN_TYPE_25     = 25,\n   UNKNOWN_TYPE_26     = 26,\n   UNKNOWN_TYPE_27     = 27,\n   UNKNOWN_TYPE_28     = 28,\n   UNKNOWN_TYPE_29     = 29,\n   UNKNOWN_TYPE_30     = 30,\n   UNKNOWN_TYPE_31     = 31\n   } TLPPacketType deriving (Bits, Eq);\n\n// copied from PCIE.bsv because connectalgen cannot parse the file\ntypedef struct {Bit#(8) hit;\n\t\tBit#(8) sof;\n\t\tBit#(8) eof;\n\t\tBit#(16) tlpbe;\n\t\tBit#(16) tag;\n\t\tBit#(16) length;\n\t\tTLPPacketType pkttype;\n\t\tTLPPacketFormat format;\n\t\tBit#(8) firstbe;\n\t\tBit#(8) lastbe;\n\t\tBit#(32) addr;\n   Bit#(32) data;\n   } Pcie3dwHeader deriving (Bits);\n\ninterface PcieTestBenchIndication;\n   method Action tlpout(TsTLPData16 tlp);\n   method Action started(Bit#(32) numWords);\n   method Action finished(Bit#(32) v);\nendinterface\n\ninterface PcieTestBenchRequest;\n   method Action tlpin(TsTLPData16 tlp);\n   method Action startRead(Bit#(32) pointer, Bit#(32) numWords, Bit#(32) burstLen);\nendinterface\n\ninterface PcieTestBench#(numeric type addrWidth, numeric type dataWidth);\n   interface PcieTestBenchRequest request;\n   interface StdPortal dmaConfig;\n   interface StdPortal dmaIndication;\n   interface Vector#(1,MemMaster#(addrWidth,dataWidth)) masters;\nendinterface\n\ntypedef enum {TestBenchIndication, TestBenchRequest, HostmemMemServerIndication, HostmemMemServerRequest, HostmemSGListConfigRequest, HostmemSGListConfigIndication} IfcNames deriving (Eq,Bits);\n\n//`define SANITY\n\nmodule mkPcieTestBench#(PcieTestBenchIndication indication)(PcieTestBench#(40,64));\n   \n   // memread state\n   FIFOF#(Bit#(64)) readFifo <- mkFIFOF;\n   let     re <- mkMemReadEngine(1, readFifo);\n   \n   // dma state\n   SGListConfigIndicationProxy hostmemSGListConfigIndicationProxy <- mkSGListConfigIndicationProxy(HostmemSGListConfigIndication);\n   SGListMMU#(PhysAddrWidth) hostmemSGList <- mkSGListMMU(0, True, hostmemSGListConfigIndicationProxy.ifc);\n   SGListConfigRequestWrapper hostmemSGListConfigRequestWrapper <- mkSGListConfigRequestWrapper(HostmemSGListConfigRequest, hostmemSGList.request);\n\n   MemServerIndicationProxy hostmemMemServerIndicationProxy <- mkMemServerIndicationProxy(HostmemMemServerIndication);\n   MemServer#(PhysAddrWidth,64,1) dma <- mkMemServer(cons(re.dmaClient,nil), nil, hostmemSGList, hostmemMemServerIndicationProxy.ifc);\n   MemServerRequestWrapper hostmemMemServerRequestWrapper <- mkMemServerRequestWrapper(HostmemMemServerRequest, dma.request);\n`ifdef SANITY\n   Axi3Master#(40,64,6) m_axi = ?;\n`else   \n   Axi3Master#(40,64,6)  m_axi <- mkAxiDmaMaster(dma.masters[0]);\n`endif\n   \n   // tlp state\n   PciId my_id = PciId { bus: 1, dev: 1, func: 0};\n   Bit#(64) board_content_id = 'hdeadbeefd00df00d;\n   Reg#(Bit#(32)) tlp_portal_drop_count <- mkReg(0);\n   Reg#(Bit#(32)) tlp_axi_drop_count <- mkReg(0);\n   AxiSlaveEngine#(64) axiSlaveEngine <- mkAxiSlaveEngine(my_id);\n   Reg#(Bit#(32)) timestamp <- mkReg(0);\n   mkConnection(m_axi, axiSlaveEngine.slave);\n   FIFO#(TimestampedTlpData) tlpin_fifo <- mkSizedFIFO(20);\n   \n   // tlp rules\n   rule timebase;\n      timestamp <= timestamp + 1;\n   endrule\n   \n   rule tlp_out;\n      let tlp <- tpl_1(axiSlaveEngine.tlps).get();\n      TimestampedTlpData ttd = TimestampedTlpData { timestamp: timestamp, source: 4, tlp: tlp };\n      indication.tlpout(unpack(pack(ttd)));\n      //$display(\"%h\",ttd);\n   endrule\n\n   rule tlp_in;\n      let ttd = tlpin_fifo.first;\n      tlpin_fifo.deq;\n      tpl_2(axiSlaveEngine.tlps).put(unpack(pack(ttd.tlp)));\n   endrule\n   \n   // memread rules\n   rule finish;\n      let rv <- re.finish;\n      indication.finished(0);\n   endrule\n   \n   rule drain;\n      readFifo.deq;\n   endrule\n   \n   interface PcieTestBenchRequest request;\n      method Action startRead(Bit#(32) rp, Bit#(32) nw, Bit#(32) bl);\n\t $display(\"startRead rdPointer=%d numWords=%h burstLen=%d\", rp, nw, bl);\n\t indication.started(nw);\n\t re.start(rp, 0, nw*4, bl*4);\n      endmethod\n      method Action tlpin(TsTLPData16 tstlp);\n\t TimestampedTlpData ttd = unpack(pack(tstlp));\n\t tlpin_fifo.enq(ttd);\n      endmethod\n   endinterface\n   interface StdPortal dmaConfig = hostmemMemServerRequestWrapper.portalIfc;\n   interface StdPortal dmaIndication = hostmemMemServerIndicationProxy.portalIfc;\n   //portals[z] = hostmemSGListConfigRequestWrapper.portalIfc;\n   //portals[z] = hostmemSGListConfigIndicationProxy.portalIfc;\n\n`ifdef SANITY\n   interface masters = dma.masters;\n`else\n   interface masters = ?;\n`endif\nendmodule\n"
  },
  {
    "path": "lib/deprecated/pcietestbench_dma_io/Top.bsv",
    "content": "import Vector::*;\nimport FIFO::*;\nimport Connectable::*;\nimport Directory::*;\nimport CtrlMux::*;\nimport Portal::*;\nimport ConnectalMemTypes::*;\nimport PcieTestBenchIndicationProxy::*;\nimport PcieTestBenchRequestWrapper::*;\nimport PcieTestBench::*;\n\nmodule mkConnectalTop(StdConnectalDmaTop#(40));\n   PcieTestBenchIndicationProxy pcieTestBenchIndicationProxy <- mkPcieTestBenchIndicationProxy(IfcNames_TestBenchIndication);\n   PcieTestBench#(40,64) pcieTestBench <- mkPcieTestBench(pcieTestBenchIndicationProxy.ifc);\n   PcieTestBenchRequestWrapper pcieTestBenchRequestWrapper <- mkPcieTestBenchRequestWrapper(IfcNames_TestBenchRequest,pcieTestBench.request);\n   \n   Vector#(4,StdPortal) portals;\n   portals[0] = pcieTestBenchRequestWrapper.portalIfc; \n   portals[1] = pcieTestBenchIndicationProxy.portalIfc;\n   portals[2] = pcieTestBench.dmaConfig;\n   portals[3] = pcieTestBench.dmaIndication;\n   \n   // instantiate system directory\n   StdDirectory dir <- mkStdDirectory(portals);\n   let ctrl_mux <- mkSlaveMux(dir,portals);\n   \n   interface interrupt = getInterruptVector(portals);\n   interface slave = ctrl_mux;\n   interface masters = pcieTestBench.masters;\nendmodule : mkConnectalTop\n\n\n"
  },
  {
    "path": "lib/deprecated/pcietestbench_dma_io/memread_nobuff_io.tstlp",
    "content": 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  },
  {
    "path": "lib/deprecated/pcietestbench_dma_io/testpcie.cpp",
    "content": "\n#include <assert.h>\n#include <fstream>\n\n#include \"dmaManager.h\"\n#include \"SGListConfigRequest.h\"\n#include \"PcieTestBenchIndication.h\"\n#include \"PcieTestBenchRequest.h\"\n\nsem_t test_sem;\nsem_t tlp_sem;\nsem_t tlp_ack;\nint numWords = 64; \nsize_t test_sz  = numWords*sizeof(unsigned int);\nsize_t alloc_sz = test_sz;\nint burstLen = 16;\n\n\nuint32_t scan_int(const char *str)\n{\n  uint32_t rv;\n  sscanf(str, \"%x\", &rv);\n  return rv;\n}\n\nenum PktClass {trace, MCont, SCont, MResp, SWReq, SReq, SResp, MWReq, MReq, Misc};\n\nPktClass pktClassification(uint32_t tlpsof, uint32_t tlpeof, uint32_t tlpbe, uint32_t pktformat, uint32_t pkttype, uint32_t portnum)\n{\n  if (tlpbe == 0)\n    return trace;\n  if (tlpsof == 0)\n    if (portnum == 4)\n      return MCont;\n    else\n      return SCont;\n  if (portnum == 4)\n    if (pkttype == 10) // COMPLETION\n      return MResp;\n    else\n      if (pktformat == 2 or pktformat == 3)\n\treturn SWReq;\n      else\n\treturn SReq;\n  else if(portnum == 8)\n    if (pkttype == 10) // COMPLETION\n      return SResp;\n    else\n      if (pktformat == 2 or pktformat == 3)\n\treturn MWReq;\n      else\n\treturn MReq;\n  else\n    return Misc;\n}\n\n\nclass PcieTestBenchIndication : public PcieTestBenchIndicationWrapper\n{  \npublic:\n  virtual void finished(uint32_t v){\n    fprintf(stderr, \"finished(%x)\\n\", v);\n    sem_post(&test_sem);\n  }\n  virtual void started(uint32_t words){\n    fprintf(stderr, \"started(%x)\\n\", words);\n  }\n  void tlpout(const TsTLPData16 &tlp) {\n    //fprintf(stderr, \"Received data= %08x%08x%08x%08x%08x%08x\\n\", tlp.data0, tlp.data1, tlp.data2, tlp.data3, tlp.data4, tlp.data5);\n    sem_post(&tlp_sem);\n    sem_wait(&tlp_ack);\n  }\n  PcieTestBenchIndication(unsigned int id) : PcieTestBenchIndicationWrapper(id){}\n};\n\n\n\nint main(int argc, const char **argv)\n{\n  PcieTestBenchRequestProxy *device = new PcieTestBenchRequestProxy(IfcNames_TestBenchRequest);\n  PcieTestBenchIndication *deviceIndication = new PcieTestBenchIndication(IfcNames_TestBenchIndication);\n  DmaManager *dma = platformInit();\n  int srcAlloc;\n  unsigned int *srcBuffer = 0;\n\n  std::ifstream infile(\"../memread_nobuff_io.tstlp\");\n\n  srcAlloc = portalAlloc(alloc_sz, 0);\n  srcBuffer = (unsigned int *)portalMmap(srcAlloc, alloc_sz);\n  for (int i = 0; i < numWords; i++)\n    srcBuffer[i] = i;\n\n  portalCacheFlush(srcAlloc, srcBuffer, alloc_sz, 1);\n  unsigned int ref_srcAlloc = dma->reference(srcAlloc);\n\n  device->startRead(ref_srcAlloc, numWords, burstLen);\n  \n#ifndef SANITY\n  int i;\n  while(i++ < 4){\n    sem_wait(&tlp_sem);\n    uint32_t cnt = 0;\n    while(cnt < 5){\n      std::string line;\n      std::getline(infile,line); \n      uint32_t tlpsof = scan_int(line.substr(48-39,1).c_str()) & 1;\n      uint32_t tlpeof = scan_int(line.substr(48-38,2).c_str()) >> 7;\n      uint32_t tlpbe  = scan_int(line.substr(48-36,4).c_str());\n      uint32_t tlphit = scan_int(line.substr(48-38,2).c_str()) & 0x7f;\n      uint32_t pktformat = (scan_int(line.substr(48-32,1).c_str()) >> 1) & 3;\n      uint32_t pkttype = (scan_int(line.substr(48-32,2).c_str()) & 0x1f);\n      uint32_t portnum = scan_int(line.substr(48-40,2).c_str()) >> 1;\n      PktClass pc = pktClassification(tlpsof, tlpeof, tlpbe, pktformat, pkttype, portnum);\n      if(pc == MResp || pc == MCont){\n\tTsTLPData16 rv;\n\tuint32_t tmp;\n\trv.data0 = scan_int(line.substr(0 ,8).c_str());\n\trv.data1 = scan_int(line.substr(8 ,8).c_str());\n\trv.data2 = scan_int(line.substr(16,8).c_str());\n\trv.data3 = scan_int(line.substr(24,8).c_str());\n\trv.data4 = scan_int(line.substr(32,8).c_str());\n\trv.data5 = scan_int(line.substr(40,8).c_str());\n\t//fprintf(stdout, \"%08x%08x%08x%08x%08x%08x\\n\", rv.data0, rv.data1, rv.data2, rv.data3, rv.data4, rv.data5);\n\t//fprintf(stdout, \"%s\\n\", line.c_str());\n\tdevice->tlpin(rv);\n\tcnt++;\n      }\n    }\n    sem_post(&tlp_ack);\n  }\n#endif\n\n  sem_wait(&test_sem);\n}\n"
  },
  {
    "path": "lib/deprecated/pcietestbench_dma_oo/Makefile",
    "content": "\nINTERFACES = PcieTestBenchRequest PcieTestBenchIndication\nBSVFILES = PcieTestBench.bsv Top.bsv ../../lib/deprecated/DmaUtils.bsv\nCPPFILES=testpcie.cpp\n\ninclude ../../Makefile.common\n"
  },
  {
    "path": "lib/deprecated/pcietestbench_dma_oo/Memread.bsv",
    "content": "// Copyright (c) 2013 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\nimport FIFO::*;\nimport FIFOF::*;\nimport Vector::*;\nimport ConnectalMemTypes::*;\nimport MemReadEngine::*;\n\ninterface MemreadRequest;\n   method Action startRead(Bit#(32) pointer, Bit#(32) numWords, Bit#(32) burstLen, Bit#(32) iterCnt);\n   method Action getStateDbg();   \nendinterface\n\ninterface Memread;\n   interface MemreadRequest request;\n   interface MemReadClient#(64) dmaClient;\nendinterface\n\ninterface MemreadIndication;\n   method Action started(Bit#(32) numWords);\n   method Action reportStateDbg(Bit#(32) streamRdCnt, Bit#(32) mismatchCount);\n   method Action readDone(Bit#(32) mismatchCount);\nendinterface\n\nmodule mkMemread#(MemreadIndication indication) (Memread);\n\n   Reg#(SGLId)        pointer <- mkReg(0);\n   Reg#(Bit#(32))         numWords <- mkReg(0);\n   Reg#(Bit#(32))         burstLen <- mkReg(0);\n   Reg#(Bit#(32))          iterCnt <- mkReg(0);\n   \n   Reg#(Bit#(32))           srcGen <- mkReg(0);\n   Reg#(Bit#(32))    mismatchCount <- mkReg(0);\n   FIFOF#(Bit#(64))       readFifo <- mkFIFOF;\n   let                          re <- mkMemReadEngine(1, readFifo);\n   \n   rule start (iterCnt > 0);\n      iterCnt <= iterCnt-1;\n      re.start(pointer, 0, numWords*4, burstLen*4);\n   endrule\n   \n   rule finish;\n      let rv <- re.finish;\n      if (iterCnt == 0)\n\t indication.readDone(mismatchCount);\n   endrule\n   \n   rule check;\n      readFifo.deq;\n      let v = readFifo.first;\n      let expectedV = {srcGen+1,srcGen};\n      let misMatch = v != expectedV;\n      mismatchCount <= mismatchCount + (misMatch ? 1 : 0);\n      if (srcGen+2 == numWords)\n\t srcGen <= 0;\n      else\n\t srcGen <= srcGen+2;\n   endrule\n   \n   interface MemReadClient dmaClient = re.dmaClient;\n   interface MemreadRequest request;\n      method Action startRead(Bit#(32) rp, Bit#(32) nw, Bit#(32) bl, Bit#(32) ic);\n\t $display(\"startRead rdPointer=%d numWords=%h burstLen=%d iterCnt=%d\", rp, nw, bl, ic);\n\t indication.started(nw);\n\t pointer <= rp;\n\t numWords  <= nw;\n\t burstLen  <= bl;\n\t iterCnt <= ic;\n\t mismatchCount <= 0;\n\t srcGen <= 0;\n      endmethod\n      method Action getStateDbg();\n\t indication.reportStateDbg(iterCnt, mismatchCount);\n      endmethod\n   endinterface\nendmodule\n\n\n"
  },
  {
    "path": "lib/deprecated/pcietestbench_dma_oo/PcieTestBench.bsv",
    "content": "// Copyright (c) 2014 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n`include \"ConnectalProjectConfig.bsv\"\nimport Clocks            :: *;\nimport Connectable       :: *;\nimport DefaultValue      :: *;\nimport FIFO              :: *;\nimport GetPut            :: *;\nimport FIFOF             :: *;\nimport Vector            :: *;\nimport AxiCsr            :: *;\nimport PCIE              :: *;\nimport AxiSlaveEngine    :: *;\nimport Portal            :: *;\nimport MemServer         :: *;\nimport SGList::*;\nimport MemReadEngine     :: *;\nimport AxiDma            :: *;\nimport ConnectalMemTypes          :: *;\nimport AxiMasterSlave    :: *;\nimport DmaUtils          :: *;\n\nimport MemServerRequestWrapper::*;\nimport SGListConfigRequestWrapper::*;\nimport MemServerIndicationProxy::*;\nimport SGListConfigIndicationProxy::*;\n\n// copied from PCIE.bsv because connectalgen cannot handle TMul#()\ntypedef struct {\n   Bit#(32)              data0;\n   Bit#(32)              data1;\n   Bit#(32)              data2;\n   Bit#(32)              data3;\n   Bit#(32)              data4;\n   Bit#(32)              data5;\n} TsTLPData16 deriving (Bits, Eq);\n\n// copied from PCIE.bsv because connectalgen cannot parse the file\ntypedef enum {\n   MEM_READ_3DW_NO_DATA = 0,\n   MEM_READ_4DW_NO_DATA = 1,\n   MEM_WRITE_3DW_DATA   = 2,\n   MEM_WRITE_4DW_DATA   = 3\n   } TLPPacketFormat deriving (Bits, Eq);\n\n// copied from PCIE.bsv because connectalgen cannot parse the file\ntypedef enum {\n   MEMORY_READ_WRITE   = 0,\n   MEMORY_READ_LOCKED  = 1,\n   IO_REQUEST          = 2,\n   UNKNOWN_TYPE_3      = 3,\n   CONFIG_0_READ_WRITE = 4,\n   CONFIG_1_READ_WRITE = 5,\n   UNKNOWN_TYPE_6      = 6,\n   UNKNOWN_TYPE_7      = 7,\n   UNKNOWN_TYPE_8      = 8,\n   UNKNOWN_TYPE_9      = 9,\n   COMPLETION          = 10,\n   COMPLETION_LOCKED   = 11,\n   UNKNOWN_TYPE_12     = 12,\n   UNKNOWN_TYPE_13     = 13,\n   UNKNOWN_TYPE_14     = 14,\n   UNKNOWN_TYPE_15     = 15,\n   MSG_ROUTED_TO_ROOT  = 16,\n   MSG_ROUTED_BY_ADDR  = 17,\n   MSG_ROUTED_BY_ID    = 18,\n   MSG_ROOT_BROADCAST  = 19,\n   MSG_LOCAL           = 20,\n   MSG_GATHER          = 21,\n   UNKNOWN_TYPE_22     = 22,\n   UNKNOWN_TYPE_23     = 23,\n   UNKNOWN_TYPE_24     = 24,\n   UNKNOWN_TYPE_25     = 25,\n   UNKNOWN_TYPE_26     = 26,\n   UNKNOWN_TYPE_27     = 27,\n   UNKNOWN_TYPE_28     = 28,\n   UNKNOWN_TYPE_29     = 29,\n   UNKNOWN_TYPE_30     = 30,\n   UNKNOWN_TYPE_31     = 31\n   } TLPPacketType deriving (Bits, Eq);\n\n// copied from PCIE.bsv because connectalgen cannot parse the file\ntypedef struct {Bit#(8) hit;\n\t\tBit#(8) sof;\n\t\tBit#(8) eof;\n\t\tBit#(16) tlpbe;\n\t\tBit#(16) tag;\n\t\tBit#(16) length;\n\t\tTLPPacketType pkttype;\n\t\tTLPPacketFormat format;\n\t\tBit#(8) firstbe;\n\t\tBit#(8) lastbe;\n\t\tBit#(32) addr;\n   Bit#(32) data;\n   } Pcie3dwHeader deriving (Bits);\n\ninterface PcieTestBenchIndication;\n   method Action tlpout(TsTLPData16 tlp);\n   method Action started(Bit#(32) numWords);\n   method Action finished(Bit#(32) v);\nendinterface\n\ninterface PcieTestBenchRequest;\n   method Action tlpin(TsTLPData16 tlp);\n   method Action startRead(Bit#(32) pointer, Bit#(32) numWords, Bit#(32) burstLen);\nendinterface\n\ninterface PcieTestBench#(numeric type addrWidth, numeric type dataWidth);\n   interface PcieTestBenchRequest request;\n   interface StdPortal dmaConfig;\n   interface StdPortal dmaIndication;\n   interface Vector#(1,MemMaster#(addrWidth,dataWidth)) masters;\nendinterface\n\ntypedef enum {TestBenchIndication, TestBenchRequest, HostmemMemServerIndication, HostmemMemServerRequest, HostmemSGListConfigRequest, HostmemSGListConfigIndication} IfcNames deriving (Eq,Bits);\n\n//`define SANITY\n\nmodule mkPcieTestBench#(PcieTestBenchIndication indication)(PcieTestBench#(40,64));\n   \n   // memread state\n   Reg#(SGLId)     rdPointer <- mkReg(0);\n   Reg#(Bit#(8))            burstLen <- mkReg(0);\n   Reg#(Bit#(32))             reqLen <- mkReg(0);\n\n   Reg#(Bit#(3))               rdTag <- mkReg(0);\n   Reg#(Bit#(32))            respCnt <- mkReg(0);\n   Reg#(Bit#(32))              rdOff <- mkReg(0);\n   DmaReadBuffer#(64, 32) rb <- mkDmaReadBuffer();\n   \n   // dma state\n   SGListConfigIndicationProxy hostmemSGListConfigIndicationProxy <- mkSGListConfigIndicationProxy(HostmemSGListConfigIndication);\n   SGListMMU#(PhysAddrWidth) hostmemSGList <- mkSGListMMU(0, True, hostmemSGListConfigIndicationProxy.ifc);\n   SGListConfigRequestWrapper hostmemSGListConfigRequestWrapper <- mkSGListConfigRequestWrapper(HostmemSGListConfigRequest, hostmemSGList.request);\n\n   MemServerIndicationProxy hostmemMemServerIndicationProxy <- mkMemServerIndicationProxy(HostmemMemServerIndication);\n   MemServer#(PhysAddrWidth,64,1) dma <- mkMemServerOOR(hostmemMemServerIndicationProxy.ifc, cons(rb.dmaClient,nil), hostmemSGList);\n   MemServerRequestWrapper hostmemMemServerRequestWrapper <- mkMemServerRequestWrapper(HostmemMemServerRequest, dma.request);\n`ifdef SANITY\n   Axi3Master#(40,64,6) m_axi = ?;\n`else   \n   Axi3Master#(40,64,6)  m_axi <- mkAxiDmaMaster(dma.masters[0]);\n`endif\n   \n   // tlp state\n   PciId my_id = PciId { bus: 1, dev: 1, func: 0};\n   Bit#(64) board_content_id = 'hdeadbeefd00df00d;\n   Reg#(Bit#(32)) tlp_portal_drop_count <- mkReg(0);\n   Reg#(Bit#(32)) tlp_axi_drop_count <- mkReg(0);\n   AxiSlaveEngine#(64) axiSlaveEngine <- mkAxiSlaveEngine(my_id);\n   Reg#(Bit#(32)) timestamp <- mkReg(0);\n   mkConnection(m_axi, axiSlaveEngine.slave);\n   FIFO#(TimestampedTlpData) tlpin_fifo <- mkSizedFIFO(20);\n   \n   // tlp rules\n   rule timebase;\n      timestamp <= timestamp + 1;\n   endrule\n   \n   rule tlp_out;\n      let tlp <- tpl_1(axiSlaveEngine.tlps).get();\n      TimestampedTlpData ttd = TimestampedTlpData { timestamp: timestamp, source: 4, tlp: tlp };\n      indication.tlpout(unpack(pack(ttd)));\n      //$display(\"%h\",ttd);\n   endrule\n\n   rule tlp_in;\n      let ttd = tlpin_fifo.first;\n      tlpin_fifo.deq;\n      tpl_2(axiSlaveEngine.tlps).put(unpack(pack(ttd.tlp)));\n   endrule\n   \n   // memread rules\n   rule rdReq if (rdOff < reqLen);\n      rdOff <= rdOff + extend(burstLen);\n      rb.dmaServer.readReq.put(MemRequest { sglId: rdPointer, offset: extend(rdOff), burstLen: burstLen, tag: extend(rdTag) });\n      rdTag <= rdTag+1;\n   endrule\n   \n   rule rdData;\n      MemData#(64) d <- rb.dmaServer.readData.get;\n      let new_respCnt = respCnt+(64/8);\n      respCnt <= new_respCnt;\n      if (new_respCnt >= reqLen)\n\t indication.finished(0);\n   endrule\n   \n   interface PcieTestBenchRequest request;\n      method Action startRead(Bit#(32) rp, Bit#(32) nw, Bit#(32) bl);\n\t $display(\"startRead rdPointer=%d numWords=%h burstLen=%d\", rp, nw, bl);\n\t indication.started(nw);\n\t rdPointer <= rp;\n\t burstLen  <= truncate(bl*4);\n\t reqLen    <= nw*4;\n\t respCnt   <= 0;\n\t rdOff     <= 0;\n      endmethod\n      method Action tlpin(TsTLPData16 tstlp);\n\t TimestampedTlpData ttd = unpack(pack(tstlp));\n\t tlpin_fifo.enq(ttd);\n      endmethod\n   endinterface\n   interface StdPortal dmaConfig = hostmemMemServerRequestWrapper.portalIfc;\n   interface StdPortal dmaIndication = hostmemMemServerIndicationProxy.portalIfc;\n   //portals[z] = hostmemSGListConfigRequestWrapper.portalIfc;\n   //portals[z] = hostmemSGListConfigIndicationProxy.portalIfc;\n\n`ifdef SANITY\n   interface masters = dma.masters;\n`else\n   interface masters = ?;\n`endif\nendmodule\n"
  },
  {
    "path": "lib/deprecated/pcietestbench_dma_oo/Top.bsv",
    "content": "import Vector::*;\nimport FIFO::*;\nimport Connectable::*;\nimport Directory::*;\nimport CtrlMux::*;\nimport Portal::*;\nimport ConnectalMemTypes::*;\nimport PcieTestBenchIndicationProxy::*;\nimport PcieTestBenchRequestWrapper::*;\nimport PcieTestBench::*;\n\nmodule mkConnectalTop(StdConnectalDmaTop#(40));\n\n   // instantiate user portals\n   PcieTestBenchIndicationProxy pcieTestBenchIndicationProxy <- mkPcieTestBenchIndicationProxy(IfcNames_TestBenchIndication);\n   PcieTestBench#(40,64) pcieTestBench <- mkPcieTestBench(pcieTestBenchIndicationProxy.ifc);\n   PcieTestBenchRequestWrapper pcieTestBenchRequestWrapper <- mkPcieTestBenchRequestWrapper(IfcNames_TestBenchRequest,pcieTestBench.request);\n   \n   Vector#(4,StdPortal) portals;\n   portals[0] = pcieTestBenchRequestWrapper.portalIfc; \n   portals[1] = pcieTestBenchIndicationProxy.portalIfc;\n   portals[2] = pcieTestBench.dmaConfig;\n   portals[3] = pcieTestBench.dmaIndication;\n   \n   StdDirectory dir <- mkStdDirectory(portals);\n   let ctrl_mux <- mkSlaveMux(dir,portals);\n   \n   interface interrupt = getInterruptVector(portals);\n   interface slave = ctrl_mux;\n   interface masters = pcieTestBench.masters;\nendmodule : mkConnectalTop\n\n\n"
  },
  {
    "path": "lib/deprecated/pcietestbench_dma_oo/memread_nobuff_oo.tstlp",
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  {
    "path": "lib/deprecated/pcietestbench_dma_oo/testpcie.cpp",
    "content": "\n#include <assert.h>\n#include <fstream>\n\n#include \"dmaManager.h\"\n#include \"SGListConfigRequest.h\"\n#include \"PcieTestBenchIndication.h\"\n#include \"PcieTestBenchRequest.h\"\n\n\nsem_t test_sem;\nsem_t tlp_sem;\nsem_t tlp_ack;\nint numWords = 64; \nsize_t test_sz  = numWords*sizeof(unsigned int);\nsize_t alloc_sz = test_sz;\nint burstLen = 16;\n\n\nuint32_t scan_int(const char *str)\n{\n  uint32_t rv;\n  sscanf(str, \"%x\", &rv);\n  return rv;\n}\n\nenum PktClass {trace, MCont, SCont, MResp, SWReq, SReq, SResp, MWReq, MReq, Misc};\n\nPktClass pktClassification(uint32_t tlpsof, uint32_t tlpeof, uint32_t tlpbe, uint32_t pktformat, uint32_t pkttype, uint32_t portnum)\n{\n  if (tlpbe == 0)\n    return trace;\n  if (tlpsof == 0)\n    if (portnum == 4)\n      return MCont;\n    else\n      return SCont;\n  if (portnum == 4)\n    if (pkttype == 10) // COMPLETION\n      return MResp;\n    else\n      if (pktformat == 2 or pktformat == 3)\n\treturn SWReq;\n      else\n\treturn SReq;\n  else if(portnum == 8)\n    if (pkttype == 10) // COMPLETION\n      return SResp;\n    else\n      if (pktformat == 2 or pktformat == 3)\n\treturn MWReq;\n      else\n\treturn MReq;\n  else\n    return Misc;\n}\n\n\nclass PcieTestBenchIndication : public PcieTestBenchIndicationWrapper\n{  \npublic:\n  virtual void finished(uint32_t v){\n    fprintf(stderr, \"finished(%x)\\n\", v);\n    sem_post(&test_sem);\n  }\n  virtual void started(uint32_t words){\n    fprintf(stderr, \"started(%x)\\n\", words);\n  }\n  void tlpout(const TsTLPData16 &tlp) {\n    //fprintf(stderr, \"Received data= %08x%08x%08x%08x%08x%08x\\n\", tlp.data0, tlp.data1, tlp.data2, tlp.data3, tlp.data4, tlp.data5);\n    sem_post(&tlp_sem);\n    sem_wait(&tlp_ack);\n  }\n  PcieTestBenchIndication(unsigned int id) : PcieTestBenchIndicationWrapper(id){}\n};\n\n\n\nint main(int argc, const char **argv)\n{\n  PcieTestBenchRequestProxy *device = new PcieTestBenchRequestProxy(IfcNames_TestBenchRequest);\n  PcieTestBenchIndication *deviceIndication = new PcieTestBenchIndication(IfcNames_TestBenchIndication);\n  DmaManager *dma = platformInit();\n  int srcAlloc;\n  unsigned int *srcBuffer = 0;\n\n  std::ifstream infile(\"../memread_nobuff_oo.tstlp\");\n\n  srcAlloc = portalAlloc(alloc_sz, 0);\n  srcBuffer = (unsigned int *)portalMmap(srcAlloc, alloc_sz);\n  for (int i = 0; i < numWords; i++)\n    srcBuffer[i] = i;\n\n  portalCacheFlush(srcAlloc, srcBuffer, alloc_sz, 1);\n  unsigned int ref_srcAlloc = dma->reference(srcAlloc);\n\n  device->startRead(ref_srcAlloc, numWords, burstLen);\n  \n#ifndef SANITY\n  int i;\n  while(i++ < 4){\n    sem_wait(&tlp_sem);\n    uint32_t cnt = 0;\n    while(cnt < 5){\n      std::string line;\n      std::getline(infile,line); \n      uint32_t tlpsof = scan_int(line.substr(48-39,1).c_str()) & 1;\n      uint32_t tlpeof = scan_int(line.substr(48-38,2).c_str()) >> 7;\n      uint32_t tlpbe  = scan_int(line.substr(48-36,4).c_str());\n      uint32_t tlphit = scan_int(line.substr(48-38,2).c_str()) & 0x7f;\n      uint32_t pktformat = (scan_int(line.substr(48-32,1).c_str()) >> 1) & 3;\n      uint32_t pkttype = (scan_int(line.substr(48-32,2).c_str()) & 0x1f);\n      uint32_t portnum = scan_int(line.substr(48-40,2).c_str()) >> 1;\n      PktClass pc = pktClassification(tlpsof, tlpeof, tlpbe, pktformat, pkttype, portnum);\n      if(pc == MResp || pc == MCont){\n\tTsTLPData16 rv;\n\tuint32_t tmp;\n\trv.data0 = scan_int(line.substr(0 ,8).c_str());\n\trv.data1 = scan_int(line.substr(8 ,8).c_str());\n\trv.data2 = scan_int(line.substr(16,8).c_str());\n\trv.data3 = scan_int(line.substr(24,8).c_str());\n\trv.data4 = scan_int(line.substr(32,8).c_str());\n\trv.data5 = scan_int(line.substr(40,8).c_str());\n\t//fprintf(stdout, \"%08x%08x%08x%08x%08x%08x\\n\", rv.data0, rv.data1, rv.data2, rv.data3, rv.data4, rv.data5);\n\t//fprintf(stdout, \"%s\\n\", line.c_str());\n\tdevice->tlpin(rv);\n\tcnt++;\n      }\n    }\n    sem_post(&tlp_ack);\n  }\n#endif\n\n  sem_wait(&test_sem);\n}\n"
  },
  {
    "path": "lib/matmul/bar.m",
    "content": "source(\"foo.m\");\n\nom3 = m1*m2;\n\nmax_error_m3  = 0.0;\nmax_error_tm3 = 0.0;\nmax_error_om3 = 0.0;\n\n#calculate a few dot products along the diagonal\n#see if the dot products agree with m3 and tm3\nfor i = 1:size(m1)(1)\n  printf(\"dp: %d\\n\", i);\n  dp = m1(i,:)*m2(:,i);\n  max_error_m3  = max(abs(m3(i,i)-dp),max_error_m3);\n  max_error_tm3 = max(abs(tm3(i,i)-dp),max_error_tm3);\n  max_error_om3 = max(abs(om3(i,i)-dp),max_error_om3);\nendfor\n\n\nmax_error_m3\nmax_error_tm3\nmax_error_om3\n\n\n"
  },
  {
    "path": "lib/matmul/bsv/DotProdServer.bsv",
    "content": "// Copyright (c) 2014 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n`include \"ConnectalProjectConfig.bsv\"\nimport FIFO::*;\nimport FIFOF::*;\nimport MIMO::*;\nimport DefaultValue::*;\nimport SpecialFIFOs::*;\nimport Vector::*;\nimport BRAM::*;\nimport ConnectalMemory::*;\nimport ConnectalMemTypes::*;\nimport MemReadEngine::*;\nimport MemWriteEngine::*;\nimport ConnectalMemUtils::*;\nimport FloatingPoint::*;\nimport Pipe::*;\nimport Arith::*;\nimport FloatOps::*;\nimport Timer::*;\nimport RbmTypes::*;\nimport Assert::*;\nimport Connectable::*;\nimport Clocks::*;\nimport Gearbox::*;\nimport XilinxCells::*;\nimport HostInterface::*;\n\ninterface SharedDotProdDebug#(numeric type k);\n   interface PipeOut#(Bit#(32)) macCount;\nendinterface\n\ninterface SharedDotProdServer#(numeric type k);\n   interface Put#(MmToken)                 aInput;\n   interface Put#(MmToken)                 bInput;\n   interface Vector#(k, PipeOut#(MmToken)) pipes;\n   interface SharedDotProdDebug#(k) debug;\nendinterface\n\ntypedef struct {\n`ifdef TAGGED_TOKENS\n   UInt#(32) row;\n   UInt#(32) col;\n`endif\n   Float v;\n   Bool first;\n   Bool last;\n} MmToken deriving (Eq,Bits);\n\ntypedef 8 UB_MulLat; // upper bound on MUL latency?\ntypedef 8 UB_AddLat; // upper bound on ADD latency?\n\t   \n(* synthesize *)\nmodule  mkSharedInterleavedDotProdServer#(UInt#(TLog#(TMul#(J,K))) label)(SharedDotProdServer#(K));\n   let rv <- mkSharedInterleavedDotProdServerConfig(label);\n   return rv;\nendmodule\n\n\nmodule  mkSharedInterleavedDotProdServerConfig#(UInt#(TLog#(TMul#(J,K))) label)(SharedDotProdServer#(k))\n   provisos(Div#(UB_AddLat,k,gatherSz));\n    \n   let ub_MulLat = valueOf(UB_MulLat);\n   let ub_AddLat = valueOf(UB_AddLat);\n   let kk = valueOf(k);\n\n   Bool verbose = False; //label == 0;\n   \n   Reg#(UInt#(20)) countReg     <- mkReg(0);\n\n   FloatAlu mul   <- mkFloatMultiplier(defaultValue);\n   FloatAlu adder <- mkFloatAdder(defaultValue);\n   FIFOF#(Float) adder_buffer <- mkSizedFIFOF(valueOf(TMul#(k,gatherSz)));\n   \n`ifdef TAGGED_TOKENS\n   FIFO#(Tuple2#(UInt#(32),UInt#(32))) tag_fifo <- mkSizedFIFO(ub_MulLat); \n   Vector#(k,Reg#(Tuple2#(UInt#(32),UInt#(32)))) tag_regs <- replicateM(mkRegU);\n`endif   \n   \n   Reg#(Bit#(32)) cycles <- mkReg(0);\n   rule countCycles;\n      cycles <= cycles + 1;\n   endrule\n\n   FIFOF#(MmToken)                          afifo   <- mkFIFOF();\n   PipeOut#(MmToken)                        aFunnel = toPipeOut(afifo);\n\n   FIFOF#(MmToken)                          bfifo <- mkFIFOF();\n   PipeOut#(MmToken)                        bFunnel = toPipeOut(bfifo);\n\n   Reg#(Bit#(16)) firstCnt <- mkReg(0);\n   Reg#(Bool)         gReg <- mkReg(False);\n   FIFOF#(Float)     gFifo <- mkSizedFIFOF(kk);\n   Reg#(Bit#(16))  lastCnt <- mkReg(0);\n   Reg#(Bit#(16))gatherCnt <- mkReg(0);\n   Reg#(Bool) gather_phase <- mkReg(False);\n   //invariant: gather_phase = lastCnt == fromInteger(kk);\n   Reg#(Bool) lastPassReg <- mkReg((0+1) == fromInteger(valueOf(gatherSz)));\n\n   FIFOF#(Tuple2#(Bool,Bool))    flFifo <- mkSizedFIFOF(ub_MulLat);\n   Vector#(k,FIFOF#(MmToken))    dotfifos <- replicateM(mkFIFOF1);\n   Reg#(Bit#(TAdd#(1,TLog#(k)))) rowReg <- mkReg(0);\n   Reg#(Bool)                lastRowReg <- mkReg(False);\n      \n   Reg#(Bit#(32)) lastMul <- mkReg(0);\n   Reg#(Bit#(32)) lastAcc <- mkReg(0);\n   Reg#(Bit#(32)) lastGather <- mkReg(0);\n   Reg#(Bit#(32)) macs <- mkReg(0);\n   \n   \n   (* fire_when_enabled *)\n   rule connect_adder_buffer;\n      match {.acc,.*} <- adder.response.get();\n      adder_buffer.enq(acc);\n      macs <= macs+1;\n   endrule\n   \n   (* fire_when_enabled *)\n   rule multiply;\n      lastMul <= cycles;\n      let a <- toGet(aFunnel).get();\n      let b <- toGet(bFunnel).get();\n      flFifo.enq(tuple2(a.first,a.last));\n      if (a.first != b.first) \n\t $display(\"****\\n    Warning: a.first=%d != b.first=%d\\n****\", a.first, b.first);\n      if (a.last != b.last) \n\t $display(\"****\\n    Warning: a.last=%d != b.last=%d\\n****\", a.last, b.last);\n      if (verbose) \n\t $display(\"%08d multiply: label=%d mulin first=%d last=%d\", cycles-lastMul, label, a.first, a.last);\n      mul.request.put(tuple2(a.v, b.v));\n`ifdef TAGGED_TOKENS\n      if(label==0) $display(\"%d (%d,%d)(%d,%d)\", label, a.row, a.col, b.row, b.col);\n      tag_fifo.enq(tuple2(a.row,b.col));\n`endif\n   endrule\n   \n   function Action incrementRowReg = \n      (action\n\t  // I have to do this check (instead of relying on wrap-around) because\n\t  // rowReg has an extra bit to compenseate for bsc's silly Bit#(0) handling\n\t  if (rowReg+1 == fromInteger(kk)) begin\n\t     rowReg <= 0;\n\t     lastRowReg <= (0 == fromInteger(kk-1));\n\t  end\n\t  else begin\n\t     rowReg <= rowReg+1;\n\t     lastRowReg <= (rowReg == fromInteger(kk-2));\n\t  end\n       endaction);\n\n   \n   (* fire_when_enabled *)\n   rule accumulate if (!gather_phase);\n      incrementRowReg;\n      lastAcc <= cycles;\n      match {.first, .last} <- toGet(flFifo).get();\n      if (verbose) $display(\"%08d accumulate: label=%d mulout first=%d last=%d firstCnt=%d lastCnt=%d\", \n\t\t\t    cycles-lastAcc, label, first, last, firstCnt, lastCnt);\n      match {.resp,.*} <- mul.response.get;\n      let acc = unpack(0);\n      if (firstCnt == fromInteger(valueOf(TMul#(k,gatherSz))))\n\t acc <- toGet(adder_buffer).get;\n      else begin\n\t firstCnt <= firstCnt+1;\n      end\n      adder.request.put(tuple2(resp,acc));\n      if(last) begin\n\t lastCnt <= lastCnt+1;\n\t gather_phase <= (lastCnt == fromInteger(kk)-1);\n      end\n`ifdef TAGGED_TOKENS\n      let row = rowReg;\n      let t <- toGet(tag_fifo).get;\n      tag_regs[row] <= t;\n`endif\n   endrule\n\n   rule checkInvariant;\n      if (lastPassReg != ((gatherCnt+1) == fromInteger(valueOf(gatherSz)))) begin\n\t $display(\"last_pass invariant failure: last_pass=%d %d gatherCnt=%d gatherSz=%d\",\n\t\t  lastPassReg, ((gatherCnt+1) == fromInteger(valueOf(gatherSz))), gatherCnt, fromInteger(valueOf(gatherSz)));\n\t $finish();\n      end\n      dynamicAssert(lastPassReg == (gatherCnt+1 == fromInteger(valueOf(gatherSz))), \"gatherCnt invariant\");\n   endrule\n\n   (* fire_when_enabled *)\n   rule gather if (gather_phase);\n      incrementRowReg;\n      lastGather <= cycles;\n      let row = rowReg;\n      let last_row = lastRowReg;\n      let last_pass = lastPassReg; // invariant: lastPassReg == (gatherCnt+1 == fromInteger(valueOf(gatherSz));)\n      if (verbose)\n\t $display(\"%08d gather: gather=%d row=%d last_pass=%d last_row=%d, gReg=%d\", \n\t\t  cycles-lastGather, gatherCnt, row, last_pass, last_row, gReg);\n      let x <- toGet(adder_buffer).get;\n      if (!last_pass) begin\n\t if (last_row) begin\n\t    if (gReg) begin\n\t       gatherCnt <= gatherCnt+1;\n\t       lastPassReg <= ((gatherCnt+2) == fromInteger(valueOf(gatherSz)));\n\t    end\n\t    gReg <= !gReg;\n\t end\n\t if(gReg) begin\n\t    let y <- toGet(gFifo).get;\n\t    adder.request.put(tuple2(x,y));\n\t end\n\t else begin\n\t    gFifo.enq(x);\n\t end\n      end\n      else begin\n`ifdef TAGGED_TOKENS\n      \t let row = tpl_1(tag_regs[row]);\n      \t let col = tpl_2(tag_regs[row]);\n\t dotfifos[row].enq(MmToken{row:row, col:col, v:x});\n`else\n\t dotfifos[row].enq(MmToken{v:x, last:False, first:False});\n`endif      \n\t if (last_row) begin\n\t    gatherCnt <= 0;\n\t    lastPassReg <= ((0+1) == fromInteger(valueOf(gatherSz)));\n\t    lastCnt <= 0;\n\t    firstCnt <= 0;\n\t    gather_phase <= False;\n\t end \n      end\n   endrule   \n\n   Vector#(k,PipeOut#(MmToken)) dotpipes = map(toPipeOut, dotfifos);\n\n   interface Put aInput;\n      method Action put(MmToken a);\n   \t afifo.enq(a);\n\t countReg <= countReg+1;\n      endmethod\n   endinterface\n   interface Put bInput   = toPut(bfifo);\n   interface Vector pipes = dotpipes;\n   interface SharedDotProdDebug debug;\n      interface PipeOut  macCount = toPipeOut(macs._read);\n   endinterface\nendmodule : mkSharedInterleavedDotProdServerConfig\n\n\n\ninterface MmTileDebug;\n   interface PipeOut#(Bit#(32)) macCount;\nendinterface\n\ninterface MmTile;\n   interface Vector#(RowsPerTile, Put#(MmToken)) aInputs;\n   interface Vector#(RowsPerTile, Put#(MmToken)) bInputs;\n   interface Vector#(RowsPerTile, PipeOut#(Vector#(N, MmToken))) fxPipes;\n   interface MmTileDebug debug;\nendinterface\n\nfunction Put#(a) toCountedPut(Reg#(Bit#(n)) r, Put#(a) p);\n   return (interface Put#(a);\n      method Action put(a v);\n\t r <= r+1;\n\t p.put(v);\n      endmethod\n      endinterface);\nendfunction\n\n(* synthesize *)\nmodule  mkMmTile#(Clock slowClock, Reset slowReset, UInt#(TLog#(T)) tile)(MmTile);\n\n   let rowsPerTile = valueOf(RowsPerTile);\n   let kk = valueOf(K);\n\n   Vector#(RowsPerTile, Reg#(Bit#(32))) aMmTokensPutRegs <- replicateM(mkReg(0));\n   Vector#(RowsPerTile, Reg#(Bit#(32))) bMmTokensPutRegs <- replicateM(mkReg(0));\n   Vector#(RowsPerTile, Reg#(Bit#(32))) aMmTokensReadRegs <- replicateM(mkReg(0));\n   Vector#(RowsPerTile, Reg#(Bit#(32))) bMmTokensReadRegs <- replicateM(mkReg(0));\n\n   Vector#(RowsPerTile, FIFOF#(MmToken))   aFifos <- replicateM(mkFIFOF);\n   Vector#(RowsPerTile, PipeOut#(MmToken)) aPipes = zipWith(toCountedPipeOut, aMmTokensReadRegs, map(toPipeOut, aFifos));\n   Vector#(RowsPerTile,  FIFOF#(MmToken))   bFifos <- replicateM(mkFIFOF);\n   Vector#(RowsPerTile,  PipeOut#(MmToken)) bPipes = zipWith(toCountedPipeOut, bMmTokensReadRegs, map(toPipeOut, bFifos));\n\n   function Vector#(k,PipeOut#(MmToken)) getDotProdServerPipes(SharedDotProdServer#(k) s); return s.pipes; endfunction\n   Vector#(RowsPerTile, SharedDotProdServer#(K)) fxdotprods <- mapM(mkSharedInterleavedDotProdServer, map(fromInteger,genVector));\n   Vector#(RowsPerTile, Vector#(K, PipeOut#(MmToken))) fxpipes = map(getDotProdServerPipes, fxdotprods);\n//`define USE_MIMO_DFIFOS // this version is faster\n   let fastClock <- exposeCurrentClock();\n   let fastReset <- exposeCurrentReset();\n`ifndef USE_MIMO_DFIFOS\n   Vector#(RowsPerTile, PipeOut#(Vector#(K, MmToken))) fxPipesK <- mapM(mkJoinVector(id), fxpipes);\n   Vector#(RowsPerTile, PipeOut#(MmToken)) fxPipes1MmToken <- mapM(mkFunnel1, fxPipesK);\n   Vector#(RowsPerTile, PipeOut#(Vector#(1, MmToken))) fxPipes1 = map(mapPipe(replicate), fxPipes1MmToken);\n`else\n   MIMOConfiguration mimoCfg = defaultValue;\n   Vector#(RowsPerTile, MIMO#(K,1,TAdd#(K,1),MmToken)) dfifos <- replicateM(mkMIMO(mimoCfg));\n   Vector#(RowsPerTile, PipeOut#(Vector#(1, MmToken))) fxPipes1 = map(toPipeOut, dfifos);\n`endif\n   Vector#(RowsPerTile, Gearbox#(1, N, MmToken)) gearboxes <- replicateM(mk1toNGearbox(fastClock, fastReset, slowClock, slowReset));\n   Vector#(RowsPerTile, PipeIn#(Vector#(1,MmToken))) toGearboxes = map(toPipeIn, gearboxes);\n   Vector#(RowsPerTile, PipeOut#(Vector#(N, MmToken))) fromGearboxes = map(toPipeOut, gearboxes);\n   mapM(uncurry(mkConnection), zip(fxPipes1, toGearboxes));\n   // introduce a buffer to help vivado meet timing on vc707\n   Vector#(RowsPerTile, FIFOF#(Vector#(N,MmToken)))    tokenfifos <- replicateM(mkFIFOF(clocked_by slowClock, reset_by slowReset));\n   Vector#(RowsPerTile, PipeIn#(Vector#(N,MmToken))) toMmTokenFifos = map(toPipeIn, tokenfifos);\n   mapM(uncurry(mkConnection), zip(fromGearboxes, toMmTokenFifos), clocked_by slowClock, reset_by slowReset);\n   Vector#(RowsPerTile, PipeOut#(Vector#(N, MmToken))) fxPipesN = map(toPipeOut, tokenfifos);\n\n   FirstLastPipe#(UInt#(MMSize)) firstLastPipe          <- mkFirstLastPipe();\n   Vector#(2, PipeOut#(Tuple2#(Bool,Bool))) firstLastPipes <- mkForkVector(firstLastPipe.pipe);\n\n   for (Integer j = 0; j < rowsPerTile; j = j + 1) begin\n      //mkConnection(toGet(aPipes[j]), fxdotprods[j].aInput);\n      //mkConnection(toGet(bPipes[j]), fxdotprods[j].bInput);\n      (* fire_when_enabled *)\n      rule connectA;\n\t let x <- toGet(aPipes[j]).get;\n\t fxdotprods[j].aInput.put(x);\n      endrule\n      (* fire_when_enabled *)\n      rule connectB;\n\t let x <- toGet(bPipes[j]).get;\n\t fxdotprods[j].bInput.put(x);\n      endrule\n   end\n\n`ifdef USE_MIMO_DFIFOS\n   for (Integer j = 0; j < rowsPerTile; j = j + 1) begin\n      rule dotProdValue;\n\t Vector#(K,MmToken) vs;\n\t for (Integer k = 0; k < kk; k = k + 1) begin\n\t    let v <- toGet(fxpipes[j][k]).get();\n\t    vs[k] = v;\n\t end\t    \n\t dfifos[j].enq(fromInteger(kk), vs);\n      endrule\n   end\n`endif\n\n   function Bool fifofNotEmpty(FIFOF#(a) fifof); return fifof.notEmpty(); endfunction\n   function PipeOut#(Bit#(32)) dotProdMacCount(SharedDotProdServer#(K) dotprodserver); return dotprodserver.debug.macCount; endfunction\n   PipeOut#(Bit#(32)) macCountPipe <- mkReducePipes(uncurry(add), map(dotProdMacCount, fxdotprods));\n\n   interface Vector aInputs = zipWith(toCountedPut, aMmTokensPutRegs, map(toPut, aFifos));\n   interface Vector bInputs = zipWith(toCountedPut, bMmTokensPutRegs, map(toPut, bFifos));\n   interface Vector fxPipes = fxPipesN;\n   interface MmTileDebug debug;\n      interface PipeOut macCount = macCountPipe;\n   endinterface\nendmodule : mkMmTile\n\ntypedef struct {\n   SGLId sglId;\n   addrtype base;\n   addrtype numRows;\n   addrtype numColumns;\n} MatrixDescriptor#(type addrtype) deriving (Bits);\n\ninterface DmaMatrixMultiplyDebug;\n   method Bit#(32) macCount();\nendinterface\n"
  },
  {
    "path": "lib/matmul/bsv/FloatOps.bsv",
    "content": "/* Copyright (c) 2014 Quanta Research Cambridge, Inc\n *\n * Permission is hereby granted, free of charge, to any person obtaining a\n * copy of this software and associated documentation files (the \"Software\"),\n * to deal in the Software without restriction, including without limitation\n * the rights to use, copy, modify, merge, publish, distribute, sublicense,\n * and/or sell copies of the Software, and to permit persons to whom the\n * Software is furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n * DEALINGS IN THE SOFTWARE.\n */\n`include \"ConnectalProjectConfig.bsv\"\nimport FIFOF::*;\nimport GetPut::*;\nimport ClientServer::*;\nimport FloatingPoint::*;\nimport DefaultValue::*;\nimport Randomizable::*;\nimport Vector::*;\nimport StmtFSM::*;\nimport Pipe::*;\nimport FIFO::*;\nimport FpMac::*;\n\n`ifdef SIMULATION\n`ifndef BOARD_xsim\n`define USE_BSV_FP\n`endif // xsim\n`else // !SIMULATION\n`ifndef XILINX\n`define USE_BSV_FP\n`endif // !XILINX\n`endif // !SIMULATION\n\ninterface FloatAlu;\n   interface Put#(Tuple2#(Float,Float)) request;\n   interface Get#(Tuple2#(Float,Exception)) response;\nendinterface\n\n(* synthesize *)\nmodule mkDoubleToFloat(Server#(Double,Float));\n   FIFO#(Double) requestFifo <- mkFIFO();\n   FIFO#(Float) responseFifo <- mkFIFO();\n   rule cvt;\n      Double d <- toGet(requestFifo).get();\n      Tuple2#(Float,Exception) tpl = convert(d, defaultValue, False);\n      match { .f, .exc } = tpl;\n      responseFifo.enq(f);\n   endrule\n   interface Put request = toPut(requestFifo);\n   interface Get response = toGet(responseFifo);\nendmodule\n\n(* synthesize *)\nmodule mkFloatToDouble(Server#(Float,Double));\n   FIFO#(Float)  requestFifo <- mkFIFO();\n   FIFO#(Double) responseFifo <- mkFIFO();\n   rule cvt;\n      Float f <- toGet(requestFifo).get();\n      Tuple2#(Double,Exception) tpl = convert(f, defaultValue, False);\n      match { .d, .exc } = tpl;\n      responseFifo.enq(d);\n   endrule\n   interface Put request = toPut(requestFifo);\n   interface Get response = toGet(responseFifo);\nendmodule\n\n(* synthesize *)\nmodule mkFloatAdder#(RoundMode rmode)(FloatAlu);\n`ifdef USE_BSV_FP\n   let adder <- mkFPAdder(rmode);\n`else\n   let adder <- mkXilinxFPAdder(rmode);\n`endif\n   interface Put request;\n      method Action put(Tuple2#(Float,Float) req);\n\t match { .a, .b } = req;\n\t let tpl3 = tuple3(a, b, rmode);\n         adder.request.put(req);\n      endmethod\n   endinterface\n   interface Get response;\n      method ActionValue#(Tuple2#(Float,Exception)) get();\n\t let resp <- adder.response.get();\n\t return resp;\n      endmethod\n   endinterface\nendmodule\n\nmodule mkFloatAddPipe#(PipeOut#(Tuple2#(Float,Float)) xypipe)(PipeOut#(Float));\n   let adder <- mkFloatAdder(defaultValue);\n   FIFOF#(Float) fifo <- mkFIFOF();\n   rule consumexy;\n      let xy = xypipe.first();\n      xypipe.deq;\n      adder.request.put(tuple2(tpl_1(xy),tpl_2(xy)));\n   endrule\n   rule enqout;\n      let resp <- adder.response.get();\n      fifo.enq(tpl_1(resp));\n   endrule\n   return toPipeOut(fifo);\nendmodule\n\n(* synthesize *)\nmodule mkFloatSubtracter#(RoundMode rmode)(FloatAlu);\n`ifdef USE_BSV_FP\n   let adder <- mkFPAdder(rmode);\n`else\n   let adder <- mkXilinxFPAdder(rmode);\n`endif\n   interface Put request;\n      method Action put(Tuple2#(Float,Float) req);\n\t match { .a, .b } = req;\n\t let tpl3 = tuple3(a, negate(b), rmode);\n         adder.request.put(req);\n      endmethod\n   endinterface\n   interface Get response;\n      method ActionValue#(Tuple2#(Float,Exception)) get();\n\t let resp <- adder.response.get();\n\t return resp;\n      endmethod\n   endinterface\nendmodule\n\nmodule mkFloatSubPipe#(PipeOut#(Tuple2#(Float,Float)) xypipe)(PipeOut#(Float));\n   let subtracter <- mkFloatSubtracter(defaultValue);\n   FIFOF#(Float) fifo <- mkFIFOF();\n   rule consumexy;\n      let xy = xypipe.first();\n      xypipe.deq;\n      subtracter.request.put(tuple2(tpl_1(xy),tpl_2(xy)));\n   endrule\n   rule enqout;\n      let resp <- subtracter.response.get();\n      fifo.enq(tpl_1(resp));\n   endrule\n   return toPipeOut(fifo);\nendmodule\n\n(* synthesize *)\nmodule mkFloatMultiplier#(RoundMode rmode)(FloatAlu);\n`ifdef USE_BSV_FP\n   let multiplier <- mkFPMultiplier(rmode);\n`else\n   let multiplier <- mkXilinxFPMultiplier(rmode);\n`endif\n   interface Put request;\n      method Action put(Tuple2#(Float,Float) req);\n         multiplier.request.put(req);\n      endmethod\n   endinterface\n   interface Get response;\n      method ActionValue#(Tuple2#(Float,Exception)) get();\n\t let resp <- multiplier.response.get();\n\t return resp;\n      endmethod\n   endinterface\nendmodule\n/*********** missing fromInt32()\n(* synthesize *)\nmodule mkRandomPipe(PipeOut#(Float));\n   let randomizer <- mkConstrainedRandomizer(0, 1024);\n\n   Reg#(Bool) initted <- mkReg(False);\n   rule first if (!initted);\n      randomizer.cntrl.init();\n      initted <= True;\n   endrule\n\n   let pipe_out <- mkPipeOut(interface Get#(Float);\n\t\t\t\tmethod ActionValue#(Float) get();\n\t\t\t\t   let v <- randomizer.next();\n\t\t\t\t   Float f = fromInt32(v); \n\t\t\t\t   return f;\n\t\t\t\tendmethod\n\t\t\t     endinterface);\n   return pipe_out;\nendmodule\n*/\n\n"
  },
  {
    "path": "lib/matmul/bsv/FpAdd.bsv",
    "content": "/* Copyright (c) 2014 Quanta Research Cambridge, Inc\n *\n * Permission is hereby granted, free of charge, to any person obtaining a\n * copy of this software and associated documentation files (the \"Software\"),\n * to deal in the Software without restriction, including without limitation\n * the rights to use, copy, modify, merge, publish, distribute, sublicense,\n * and/or sell copies of the Software, and to permit persons to whom the\n * Software is furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n * DEALINGS IN THE SOFTWARE.\n */\n\n/*\n   /home/jamey/connectal/scripts/importbvi.py\n   -o\n   FpAdd.bsv\n   -c\n   aclk\n   -f\n   s_axis_a\n   -f\n   s_axis_b\n   -f\n   m_axis_result\n   -I\n   FpAdd\n   -P\n   FpAdd\n   fp_add_stub.v\n*/\n\nimport Clocks::*;\nimport DefaultValue::*;\nimport XilinxCells::*;\nimport GetPut::*;\n\n(* always_ready, always_enabled *)\ninterface FpaddM_axis_result;\n    method Bit#(32)     tdata();\n    method Action      tready(Bit#(1) v);\n    method Bit#(1)     tvalid();\nendinterface\n(* always_ready, always_enabled *)\ninterface FpaddS_axis_a;\n    method Action      tdata(Bit#(32) v);\n    method Bit#(1)     tready();\n    method Action      tvalid(Bit#(1) v);\nendinterface\n(* always_ready, always_enabled *)\ninterface FpaddS_axis_b;\n    method Action      tdata(Bit#(32) v);\n    method Bit#(1)     tready();\n    method Action      tvalid(Bit#(1) v);\nendinterface\n(* always_ready, always_enabled *)\ninterface FpaddS_axis_operation;\n    method Action      tdata(Bit#(8) v);\n    method Bit#(1)     tready();\n    method Action      tvalid(Bit#(1) v);\nendinterface\n(* always_ready, always_enabled *)\ninterface FpAdd;\n    interface FpaddM_axis_result     m_axis_result;\n    interface FpaddS_axis_a     s_axis_a;\n    interface FpaddS_axis_b     s_axis_b;\n    interface FpaddS_axis_operation     s_axis_operation;\nendinterface\nimport \"BVI\" fp_add =\nmodule mkFpAdd(FpAdd);\n    default_clock aclk(aclk);\n    default_reset aresetn(aresetn);\n    interface FpaddM_axis_result     m_axis_result;\n        method m_axis_result_tdata tdata();\n        method tready(m_axis_result_tready) enable((*inhigh*) EN_m_axis_result_tready);\n        method m_axis_result_tvalid tvalid();\n    endinterface\n    interface FpaddS_axis_a     s_axis_a;\n        method tdata(s_axis_a_tdata) enable((*inhigh*) EN_s_axis_a_tdata);\n        method s_axis_a_tready tready();\n        method tvalid(s_axis_a_tvalid) enable((*inhigh*) EN_s_axis_a_tvalid);\n    endinterface\n    interface FpaddS_axis_b     s_axis_b;\n        method tdata(s_axis_b_tdata) enable((*inhigh*) EN_s_axis_b_tdata);\n        method s_axis_b_tready tready();\n        method tvalid(s_axis_b_tvalid) enable((*inhigh*) EN_s_axis_b_tvalid);\n    endinterface\n    interface FpaddS_axis_operation     s_axis_operation;\n        method tdata(s_axis_operation_tdata) enable((*inhigh*) EN_s_axis_operation_tdata);\n        method s_axis_operation_tready tready();\n        method tvalid(s_axis_operation_tvalid) enable((*inhigh*) EN_s_axis_operation_tvalid);\n    endinterface\n    schedule (m_axis_result.tdata, m_axis_result.tready, m_axis_result.tvalid, s_axis_a.tdata, s_axis_a.tready, s_axis_a.tvalid, s_axis_b.tdata, s_axis_b.tready, s_axis_b.tvalid, s_axis_operation.tdata, s_axis_operation.tready, s_axis_operation.tvalid) CF (m_axis_result.tdata, m_axis_result.tready, m_axis_result.tvalid, s_axis_a.tdata, s_axis_a.tready, s_axis_a.tvalid, s_axis_b.tdata, s_axis_b.tready, s_axis_b.tvalid, s_axis_operation.tdata, s_axis_operation.tready, s_axis_operation.tvalid);\nendmodule\n"
  },
  {
    "path": "lib/matmul/bsv/FpMac.bsv",
    "content": "/* Copyright (c) 2014 Quanta Research Cambridge, Inc\n *\n * Permission is hereby granted, free of charge, to any person obtaining a\n * copy of this software and associated documentation files (the \"Software\"),\n * to deal in the Software without restriction, including without limitation\n * the rights to use, copy, modify, merge, publish, distribute, sublicense,\n * and/or sell copies of the Software, and to permit persons to whom the\n * Software is furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n * DEALINGS IN THE SOFTWARE.\n */\nimport FIFOF::*;\nimport GetPut::*;\nimport ClientServer::*;\nimport FloatingPoint::*;\nimport DefaultValue::*;\nimport Randomizable::*;\nimport Vector::*;\nimport StmtFSM::*;\nimport Pipe::*;\nimport FIFO::*;\nimport BUtils::*;\nimport PipeMul::*;\nimport FpMul::*;\nimport FpAdd::*;\n\n////////////////////////////////////////////////////////////////////////////////\n/// Floating point fused multiple accumulate\n////////////////////////////////////////////////////////////////////////////////\n///\n/// copied from FloatingPoint.bsv and modified.\n/// this version is no longer IEEE compliant :)\n///\n////////////////////////////////////////////////////////////////////////////////\n\ntypedef struct {\n   Maybe#(FloatingPoint#(e,m)) res;\n   Exception exc;\n   RoundMode rmode;\n   } CommonState#(numeric type e, numeric type m) deriving (Bits, Eq);\n\nfunction Bit#(e) unbias( FloatingPoint#(e,m) din );\n   return (din.exp - fromInteger(bias(din)));\nendfunction\n\nfunction Bit#(m) zExtendLSB(Bit#(n) value)\n   provisos( Add#(n,m,k) );\n   Bit#(k) out = { value, 0 };\n   return out[valueof(k)-1:valueof(n)];\nendfunction\n\nfunction Integer minexp( FloatingPoint#(e,m) din );\n  return 1-bias(din);\nendfunction\n\nfunction Bit#(1) getHiddenBit( FloatingPoint#(e,m) din );\n   return (isSubNormal(din)) ? 0 : 1;\nendfunction\n\nfunction Integer bias( FloatingPoint#(e,m) din );\n   return (2 ** (valueof(e)-1)) - 1;\nendfunction\n\nfunction Integer minexp_subnormal( FloatingPoint#(e,m) din );\n   return minexp(din)-valueof(m);\nendfunction\n\nfunction Integer maxexp( FloatingPoint#(e,m) din );\n   return bias(din);\nendfunction\n\nfunction Tuple2#(FloatingPoint#(e,m),Exception) round( RoundMode rmode, FloatingPoint#(e,m) din, Bit#(2) guard )\n   provisos(  Add#(m, 1, m1)\n\t    , Add#(m, 2, m2)\n\t    );\n\n   FloatingPoint#(e,m) out = defaultValue;\n   Exception exc = defaultValue;\n\n   if (isNaNOrInfinity(din)) begin\n      out = din;\n   end\n   else begin\n      let din_inc = din;\n\n      Bit#(TAdd#(m,2)) sfd = unpack({1'b0, getHiddenBit(din), din.sfd}) + 1;\n\n      if (msb(sfd) == 1) begin\n\t if (din.exp == fromInteger(maxexp(din) + bias(out))) begin\n\t    din_inc = infinity(din_inc.sign);\n\t end\n\t else begin\n\t    din_inc.exp = din_inc.exp + 1;\n\t    din_inc.sfd = truncate(sfd >> 1);\n\t end\n      end\n      else if ((din.exp == 0) && (truncateLSB(sfd) == 2'b01)) begin\n\t din_inc.exp = 1;\n\t din_inc.sfd = truncate(sfd);\n      end\n      else begin\n\t din_inc.sfd = truncate(sfd);\n      end\n\n      if (guard != 0) begin\n\t exc.inexact = True;\n      end\n\n      case(rmode)\n\t Rnd_Nearest_Even:\n\t begin\n\t    case (guard)\n\t       'b00: out = din;\n\t       'b01: out = din;\n\t       'b10: out = (lsb(din.sfd) == 1) ? din_inc : din;\n\t       'b11: out = din_inc;\n\t    endcase\n\t end\n\n\t Rnd_Nearest_Away_Zero:\n\t begin\n\t    case (guard)\n\t       'b00: out = din;\n\t       'b01: out = din_inc;\n\t       'b10: out = din_inc;\n\t       'b11: out = din_inc;\n\t    endcase\n\t end\n\n\t Rnd_Plus_Inf:\n\t begin\n\t    if (guard == 0)\n\t       out = din;\n\t    else if (din.sign)\n\t       out = din;\n\t    else\n\t       out = din_inc;\n\t end\n\n\t Rnd_Minus_Inf:\n\t begin\n\t    if (guard == 0)\n\t       out = din;\n\t    else if (din.sign)\n\t       out = din_inc;\n\t    else\n\t       out = din;\n\t end\n\n\t Rnd_Zero:\n\t begin\n\t    out = din;\n\t end\n      endcase\n   end\n\n   if (isInfinity(out)) begin\n      exc.overflow = True;\n   end\n\n   return tuple2(out,exc);\nendfunction\n\nfunction Tuple3#(FloatingPoint#(e,m),Bit#(2),Exception) normalize( FloatingPoint#(e,m) din, Bit#(x) sfdin )\n   provisos(\n      Add#(1, a__, x),\n      Add#(m, b__, x),\n      // per request of bsc\n      Add#(c__, TLog#(TAdd#(1, x)), TAdd#(e, 1))\n      );\n\n   FloatingPoint#(e,m) out = din;\n   Bit#(2) guard = 0;\n   Exception exc = defaultValue;\n\n   Int#(TAdd#(e,1)) exp = isSubNormal(out) ? fromInteger(minexp(out)) : signExtend(unpack(unbias(out)));\n   let zeros = countZerosMSB(sfdin);\n\n   if ((zeros == 0) && (exp == fromInteger(maxexp(out)))) begin\n      out.exp = maxBound - 1;\n      out.sfd = maxBound;\n      guard = '1;\n      exc.overflow = True;\n      exc.inexact = True;\n   end\n   else begin\n      if (zeros == 0) begin\n\t // carry, no sfd adjust necessary\n\n\t if (out.exp == 0)\n\t    out.exp = 2;\n\t else\n\t    out.exp = out.exp + 1;\n\n\t // carry bit\n\t sfdin = sfdin << 1;\n      end\n      else if (zeros == 1) begin\n\t // already normalized\n\n\t if (out.exp == 0)\n\t    out.exp = 1;\n\n\t // carry, hidden bits\n\t sfdin = sfdin << 2;\n      end\n      else if (zeros == fromInteger(valueOf(x))) begin\n\t // exactly zero\n\t out.exp = 0;\n      end\n      else begin\n\t // try to normalize\n\t Int#(TAdd#(e,1)) shift = zeroExtend(unpack(pack(zeros - 1)));\n\t Int#(TAdd#(e,1)) maxshift = exp - fromInteger(minexp(out));\n\n\t if (shift > maxshift) begin\n\t    // result will be subnormal\n\n\t    sfdin = sfdin << maxshift;\n\t    out.exp = 0;\n\t end\n\t else begin\n\t    // result will be normal\n\n\t    sfdin = sfdin << shift;\n\t    out.exp = out.exp - truncate(pack(shift));\n\t end\n\n \t // carry, hidden bits\n\t sfdin = sfdin << 2;\n      end\n\n      out.sfd = unpack(truncateLSB(sfdin));\n      sfdin = sfdin << fromInteger(valueOf(m));\n\n      guard[1] = unpack(truncateLSB(sfdin));\n      sfdin = sfdin << 1;\n\n      guard[0] = |sfdin;\n   end\n\n   if ((out.exp == 0) && (guard != 0))\n      exc.underflow = True;\n\n   return tuple3(out,guard,exc);\nendfunction\n\nfunction Bool isNaNOrInfinity( FloatingPoint#(e,m) din );\n   return (din.exp == '1);\nendfunction\n\n////////////////////////////////////////////////////////////////////////////////\n/// Pipelined Floating Point Adder\n////////////////////////////////////////////////////////////////////////////////\n\nmodule mkFPAdder#(RoundMode rmode)(Server#(Tuple2#(FloatingPoint#(e,m), FloatingPoint#(e,m)), Tuple2#(FloatingPoint#(e,m),Exception)))\n   provisos(\n      // per request of bsc\n      Add#(a__, TLog#(TAdd#(1, TAdd#(m, 5))), TAdd#(e, 1))\n      );\n\n   ////////////////////////////////////////////////////////////////////////////////\n   /// S0\n   ////////////////////////////////////////////////////////////////////////////////\n   FIFOF#(Tuple2#(FloatingPoint#(e,m),\n\t\t  FloatingPoint#(e,m)))                 fOperands_S0        <- mkLFIFOF;\n\n   ////////////////////////////////////////////////////////////////////////////////\n   /// S1 - subtract exponents\n   ////////////////////////////////////////////////////////////////////////////////\n   Reg#(Tuple7#(CommonState#(e,m),\n\t\tBit#(TAdd#(m,5)),\n\t\tBit#(TAdd#(m,5)),\n\t\tBool,\n\t\tBool,\n\t\tBit#(e),\n\t\tBit#(e))) rState_S1 <- mkReg(unpack(0));\n   Reg#(Bool) rValid_S1 <- mkReg(False);\n\n   Reg#(Tuple6#(CommonState#(e,m),\n\t\tBit#(TAdd#(m,5)),\n\t\tBit#(TAdd#(m,5)),\n\t\tBool,\n\t\tBool,\n\t\tBit#(e))) rState_S2 <- mkReg(unpack(0));\n   Reg#(Bool) rValid_S2 <- mkReg(False);\n\n   Reg#(Tuple6#(CommonState#(e,m),\n\t\tBit#(TAdd#(m,5)),\n\t\tBit#(TAdd#(m,5)),\n\t\tBool,\n\t\tBool,\n\t\tBit#(e))) rState_S3 <- mkReg(unpack(0));\n   Reg#(Bool) rValid_S3 <- mkReg(False);\n\n   Reg#(Tuple4#(CommonState#(e,m),\n\t\tFloatingPoint#(e,m),\n\t\tBit#(2),\n\t\tBool)) rState_S4 <- mkReg(unpack(0));\n   Reg#(Bool) rValid_S4 <- mkReg(False);\n\n   FIFO#(Tuple2#(FloatingPoint#(e,m),Exception)) fResult_S5          <- mkFIFO;\n\n   rule s1_stage;\n      begin\n\t let req = unpack(0);\n\t let valid = False;\n\t if (fOperands_S0.notEmpty) begin\n\t    req <- toGet(fOperands_S0).get;\n\t    valid = True;\n\t end\n\t match { .opA, .opB } = req;\n\t CommonState#(e,m) s = CommonState {\n\t    res: tagged Invalid,\n\t    exc: defaultValue,\n\t    rmode: rmode\n\t    };\n\n\t Int#(TAdd#(e,2)) expA = isSubNormal(opA) ? fromInteger(minexp(opA)) : signExtend(unpack(unbias(opA)));\n\t Int#(TAdd#(e,2)) expB = isSubNormal(opB) ? fromInteger(minexp(opB)) : signExtend(unpack(unbias(opB)));\n\n\t Bit#(TAdd#(m,5)) sfdA = {1'b0, getHiddenBit(opA), opA.sfd, 3'b0};\n\t Bit#(TAdd#(m,5)) sfdB = {1'b0, getHiddenBit(opB), opB.sfd, 3'b0};\n\n\t Bit#(TAdd#(m,5)) x;\n\t Bit#(TAdd#(m,5)) y;\n\t Bool sgn;\n\t Bool sub;\n\t Bit#(e) exp;\n\t Bit#(e) expdiff;\n\n\t if ((expB > expA) || ((expB == expA) && (sfdB > sfdA))) begin\n\t    exp = opB.exp;\n\t    expdiff = truncate(pack(expB - expA));\n\t    x = sfdB;\n\t    y = sfdA;\n\t    sgn = opB.sign;\n\t    sub = (opB.sign != opA.sign);\n\t end\n\t else begin\n\t    exp = opA.exp;\n\t    expdiff = truncate(pack(expA - expB));\n\t    x = sfdA;\n\t    y = sfdB;\n\t    sgn = opA.sign;\n\t    sub = (opA.sign != opB.sign);\n\t end\n\n\t if (isSNaN(opA)) begin\n\t    s.res = tagged Valid nanQuiet(opA);\n\t    s.exc.invalid_op = True;\n\t end\n\t else if (isSNaN(opB)) begin\n\t    s.res = tagged Valid nanQuiet(opB);\n\t    s.exc.invalid_op = True;\n\t end\n\t else if (isQNaN(opA)) begin\n\t    s.res = tagged Valid opA;\n\t end\n\t else if (isQNaN(opB)) begin\n\t    s.res = tagged Valid opB;\n\t end\n\t else if (isInfinity(opA) && isInfinity(opB)) begin\n\t    if (opA.sign == opB.sign)\n\t       s.res = tagged Valid infinity(opA.sign);\n\t    else begin\n\t       s.res = tagged Valid qnan();\n\t       s.exc.invalid_op = True;\n\t    end\n\t end\n\t else if (isInfinity(opA)) begin\n\t    s.res = tagged Valid opA;\n\t end\n\t else if (isInfinity(opB)) begin\n\t    s.res = tagged Valid opB;\n\t end\n\n\t rState_S1 <= tuple7(s,\n\t\t\t     x,\n\t\t\t     y,\n\t\t\t     sgn,\n\t\t\t     sub,\n\t\t\t     exp,\n\t\t\t     expdiff);\n\t rValid_S1 <= valid;\n      end\n   //endrule\n\n   ////////////////////////////////////////////////////////////////////////////////\n   /// S2 - align significands\n   ////////////////////////////////////////////////////////////////////////////////\n\n   //rule s2_stage;\n      begin\n\t match {.s, .opA, .opB, .sign, .subtract, .exp, .diff} = rState_S1;\n\t let valid = rValid_S1;\n\n\t if (s.res matches tagged Invalid) begin\n\t    if (diff < fromInteger(valueOf(m) + 5)) begin\n\t       Bit#(TAdd#(m,5)) guard = opB;\n\n\t       guard = opB << (fromInteger(valueOf(m) + 5) - diff);\n\t       opB = opB >> diff;\n\t       opB[0] = opB[0] | (|guard);\n\t    end\n\t    else if (|opB == 1) begin\n\t       opB = 1;\n\t    end\n\t end\n\n\t rState_S2 <= tuple6(s,\n\t\t\t     opA,\n\t\t\t     opB,\n\t\t\t     sign,\n\t\t\t     subtract,\n\t\t\t     exp);\n\t rValid_S2 <= valid;\n      end\n   //endrule\n\n   ////////////////////////////////////////////////////////////////////////////////\n   /// S3 - add/subtract significands\n   ////////////////////////////////////////////////////////////////////////////////\n\n   //rule s3_stage;\n      begin\n\t match {.s, .a, .b, .sign, .subtract, .exp} = rState_S2;\n\t let valid = rValid_S2;\n\n\t let sum = a + b;\n\t let diff = a - b;\n\n\t rState_S3 <= tuple6(s,\n\t\t\t     sum,\n\t\t\t     diff,\n\t\t\t     sign,\n\t\t\t     subtract,\n\t\t\t     exp);\n\t rValid_S3 <= valid;\n      end\n   //endrule\n\n   ////////////////////////////////////////////////////////////////////////////////\n   /// S4 - normalize\n   ////////////////////////////////////////////////////////////////////////////////\n   //rule s4_stage;\n      begin\n\t match {.s, .addres, .subres, .sign, .subtract, .exp} = rState_S3;\n\t let valid = rValid_S3;\n\n\t FloatingPoint#(e,m) out = defaultValue;\n\t Bit#(2) guard = 0;\n\n\t if (s.res matches tagged Invalid) begin\n\t    Bit#(TAdd#(m,5)) result;\n\n\t    if (subtract) begin\n\t       result = subres;\n\t    end\n\t    else begin\n               result = addres;\n\t    end\n\n\t    out.sign = sign;\n\t    out.exp = exp;\n\n\t    // $display(\"out = \", fshow(out));\n\t    // $display(\"result = 'h%x\", result);\n\t    // $display(\"zeros = %d\", countZerosMSB(result));\n\n\t    let y = normalize(out, result);\n\t    out = tpl_1(y);\n\t    guard = tpl_2(y);\n\t    s.exc = s.exc | tpl_3(y);\n\t end\n\n\t rState_S4 <= tuple4(s,\n\t\t\t     out,\n\t\t\t     guard,\n\t\t\t     subtract);\n\t rValid_S4 <= valid;\n      end\n   //endrule\n\n   ////////////////////////////////////////////////////////////////////////////////\n   /// S5 - round result\n   ////////////////////////////////////////////////////////////////////////////////\n\n   //rule s5_stage;\n      begin\n\t match {.s, .rnd, .guard, .subtract} = rState_S4;\n\t let valid = rValid_S4;\n\t FloatingPoint#(e,m) out = rnd;\n\n\t if (s.res matches tagged Valid .x) begin\n\t    out = x;\n\t end\n\t else begin\n\t    let y = round(s.rmode, out, guard);\n\t    out = tpl_1(y);\n\t    s.exc = s.exc | tpl_2(y);\n\t end\n\n\t // adjust sign for exact zero result\n\t if (isZero(out) && !s.exc.inexact && subtract) begin\n\t    out.sign = (s.rmode == Rnd_Minus_Inf);\n\t end\n\n\t if (valid)\n\t    fResult_S5.enq(tuple2(out,s.exc));\n      end\n   endrule\n\n   ////////////////////////////////////////////////////////////////////////////////\n   /// Interface Connections / Methods\n   ////////////////////////////////////////////////////////////////////////////////\n   interface request = toPut(fOperands_S0);\n   interface response = toGet(fResult_S5);\n\nendmodule: mkFPAdder\n\n////////////////////////////////////////////////////////////////////////////////\n/// Pipelined Floating Point Multiplier\n////////////////////////////////////////////////////////////////////////////////\nmodule mkFPMultiplier#(RoundMode rmode)(Server#(Tuple2#(FloatingPoint#(e,m), FloatingPoint#(e,m)), Tuple2#(FloatingPoint#(e,m),Exception)))\n   provisos(\n      // per request of bsc\n      Add#(a__, TLog#(TAdd#(1, TAdd#(TAdd#(m, 1), TAdd#(m, 1)))), TAdd#(e, 1)),\n      Add#(b__, 16, TAdd#(m, 1))\n      );\n\n   let implementSubnormal = False;\n\n   ////////////////////////////////////////////////////////////////////////////////\n   /// S0\n   ////////////////////////////////////////////////////////////////////////////////\n   FIFOF#(Tuple2#(FloatingPoint#(e,m),\n\t\t  FloatingPoint#(e,m)))                 fOperands_S0        <- mkLFIFOF;\n\n   ////////////////////////////////////////////////////////////////////////////////\n   /// S1 - calculate the new exponent/sign\n   ////////////////////////////////////////////////////////////////////////////////\n   Reg#(Tuple5#(CommonState#(e,m),\n\t\tBit#(TAdd#(m,1)),\n\t\tBit#(TAdd#(m,1)),\n\t\tInt#(TAdd#(e,2)),\n\t\tBool)) rState_S1 <- mkReg(unpack(0));\n   Reg#(Bool) rValid_S1 <- mkReg(False);\n\n   Reg#(Tuple3#(CommonState#(e,m),\n\t\tInt#(TAdd#(e,2)),\n\t\tBool)) rState_S2 <- mkReg(unpack(0));\n   Reg#(Tuple3#(Bool, Bool, Bool)) rCond_S3 <- mkReg(unpack(0));\n   Reg#(Int#(TAdd#(e,2))) rShift_S3 <- mkReg(0);\n   Reg#(UInt#(TAdd#(TAdd#(m,1),TAdd#(m,1)))) rsfdres_S2_lsb <- mkReg(0);\n   Reg#(UInt#(TAdd#(TAdd#(m,1),TAdd#(m,1)))) rsfdres_S2_msb <- mkReg(0);\n\n   Reg#(Bool) rValid_S2 <- mkReg(False);\n\n   Reg#(Tuple3#(CommonState#(e,m),\n\t\t Int#(TAdd#(e,2)),\n\t\t Bool)) rState_S3 <- mkReg(unpack(0));\n   Reg#(UInt#(TAdd#(TAdd#(m,1),TAdd#(m,1)))) rsfdres_S3 <- mkReg(0);\n   Reg#(Bool) rValid_S3 <- mkReg(False);\n\n   Reg#(Tuple3#(CommonState#(e,m),\n\t\tFloatingPoint#(e,m),\n\t\tBit#(2))) rState_S4 <- mkReg(unpack(0));\n   Reg#(Bool) rValid_S4 <- mkReg(False);\n\n   FIFO#(Tuple2#(FloatingPoint#(e,m),Exception)) fResult_S5  <- mkFIFO;\n\n   rule s1_stage;\n      begin\n\t let req = unpack(0);\n\t let valid = False;\n\t if (fOperands_S0.notEmpty()) begin\n\t    req <- toGet(fOperands_S0).get;\n\t    valid = True;\n\t end\n\t match { .opA, .opB } = req;\n\n\t CommonState#(e,m) s = CommonState {\n\t    res: tagged Invalid,\n\t    exc: defaultValue,\n\t    rmode: rmode\n\t    };\n\n\t Int#(TAdd#(e,2)) expA = isSubNormal(opA) ? fromInteger(minexp(opA)) : signExtend(unpack(unbias(opA)));\n\t Int#(TAdd#(e,2)) expB = isSubNormal(opB) ? fromInteger(minexp(opB)) : signExtend(unpack(unbias(opB)));\n\t Int#(TAdd#(e,2)) newexp = expA + expB;\n\n\t Bool sign = (opA.sign != opB.sign);\n\n\t Bit#(TAdd#(m,1)) opAsfd = { getHiddenBit(opA), opA.sfd };\n\t Bit#(TAdd#(m,1)) opBsfd = { getHiddenBit(opB), opB.sfd };\n\n\t if (isSNaN(opA)) begin\n\t    s.res = tagged Valid nanQuiet(opA);\n\t    s.exc.invalid_op = True;\n\t end\n\t else if (isSNaN(opB)) begin\n\t    s.res = tagged Valid nanQuiet(opB);\n\t    s.exc.invalid_op = True;\n\t end\n\t else if (isQNaN(opA)) begin\n\t    s.res = tagged Valid opA;\n\t end\n\t else if (isQNaN(opB)) begin\n\t    s.res = tagged Valid opB;\n\t end\n\t else if ((isInfinity(opA) && isZero(opB)) || (isZero(opA) && isInfinity(opB))) begin\n\t    s.res = tagged Valid qnan();\n\t    s.exc.invalid_op = True;\n\t end\n\t else if (isInfinity(opA) || isInfinity(opB)) begin\n\t    s.res = tagged Valid infinity(opA.sign != opB.sign);\n\t end\n\t else if (isZero(opA) || isZero(opB)) begin\n\t    s.res = tagged Valid zero(opA.sign != opB.sign);\n\t end\n\t else if (newexp > fromInteger(maxexp(opA))) begin\n\t    FloatingPoint#(e,m) out;\n\t    out.sign = (opA.sign != opB.sign);\n\t    out.exp = maxBound - 1;\n\t    out.sfd = maxBound;\n\n\t    s.exc.overflow = True;\n\t    s.exc.inexact = True;\n\n\t    let y = round(rmode, out, '1);\n\t    s.res = tagged Valid tpl_1(y);\n\t    s.exc = s.exc | tpl_2(y);\n\t end\n\t else if (newexp < (fromInteger(minexp_subnormal(opA))-2)) begin\n\t    FloatingPoint#(e,m) out;\n\t    out.sign = (opA.sign != opB.sign);\n\t    out.exp = 0;\n\t    out.sfd = 0;\n\n\t    s.exc.underflow = True;\n\t    s.exc.inexact = True;\n\n\t    let y = round(rmode, out, 'b01);\n\t    s.res = tagged Valid tpl_1(y);\n\t    s.exc = s.exc | tpl_2(y);\n\t end\n\n\t rState_S1 <= tuple5(s,\n\t\t\t     opAsfd,\n\t\t\t     opBsfd,\n\t\t\t     newexp,\n\t\t\t     sign);\n\t rValid_S1 <= valid;\n      end\n   //endrule\n\n   ////////////////////////////////////////////////////////////////////////////////\n   /// S2\n   ////////////////////////////////////////////////////////////////////////////////\n   //rule s2_stage;\n      begin\n\t match {.s, .opAsfd, .opBsfd, .exp, .sign} = rState_S1;\n\t let valid = rValid_S1;\n\n\t //Bit#(TAdd#(TAdd#(m,1),TAdd#(m,1))) sfdres = primMul(opAsfd, opBsfd);\n\t UInt#(TAdd#(m,1)) opBsfd_lsb = extend(unpack(opBsfd[15:0]));\n\t UInt#(TSub#(TAdd#(m,1),16)) opBsfd_msb  = unpack(opBsfd[valueOf(TAdd#(m,1))-1:16]);\n\t rsfdres_S2_lsb <= extend(unpack(opAsfd))*extend(opBsfd_lsb);\n\t rsfdres_S2_msb <= extend(unpack(opAsfd))*extend(opBsfd_msb);\n\n\t rState_S2 <= tuple3(s,\n\t\t\t     exp,\n\t\t\t     sign);\n\t rValid_S2 <= valid;\n      end\n   //endrule\n\n   ////////////////////////////////////////////////////////////////////////////////\n   /// S3\n   ////////////////////////////////////////////////////////////////////////////////\n\n   //rule s3_stage;\n      begin\n\t let x = rState_S2;\n\t let valid = rValid_S2;\n\t rsfdres_S3 <= (rsfdres_S2_msb << 16) + rsfdres_S2_lsb;\n\t rState_S3 <= x;\n\t rValid_S3 <= valid;\n\n\t match {.s, .exp, .sign} = x;\n\t FloatingPoint#(e,m) result = defaultValue;\n\t Bit#(2) guard = ?;\n\n\t let sresInvalid = False;\n\t let subnormal = False;\n\t let inbounds = False;\n\t let shift = fromInteger(minexp(result)) - exp;\n\t \n\t if (s.res matches tagged Invalid) begin\n\t    sresInvalid = True;\n\t    if (shift > 0) begin\n\t       subnormal = True;\n\t       // subnormal\n\t    end\n\t    else begin\n\t       inbounds = True;\n\t    end\n\t end\n\t rCond_S3 <= tuple3(sresInvalid, subnormal, inbounds);\n\t if (implementSubnormal)\n\t    rShift_S3 <= shift;\n      end\n   //endrule\n\n   ////////////////////////////////////////////////////////////////////////////////\n   /// S4\n   ////////////////////////////////////////////////////////////////////////////////\n   //rule s4_stage;\n      begin\n\t match {.s, .exp, .sign} = rState_S3;\n\t match {.sresInvalid, .subnormal, .inbounds} = rCond_S3;\n\t let shift = 0;\n\t if (implementSubnormal)\n\t    shift = rShift_S3;\n\t let sfdres = pack(rsfdres_S3);\n\t let valid = rValid_S3;\n\n\t FloatingPoint#(e,m) result = defaultValue;\n\t Bit#(2) guard = ?;\n\n\t //if (s.res matches tagged Invalid) begin\n\t if (sresInvalid) begin\n\t    //$display(\"sfdres = 'h%x\", sfdres);\n\n\t    //let shift = fromInteger(minexp(result)) - exp;\n\t    //if (shift > 0) begin\n\t    if (subnormal) begin\n\t       // subnormal\n\t       if (implementSubnormal) begin\n\t\t  Bit#(1) sfdlsb = |(sfdres << (fromInteger(valueOf(TAdd#(TAdd#(m,1),TAdd#(m,1)))) - shift));\n\n\t\t  //$display(\"sfdlsb = |'h%x = 'b%b\", (sfdres << (fromInteger(valueOf(TAdd#(TAdd#(m,1),TAdd#(m,1)))) - shift)), sfdlsb);\n\n\t\t  sfdres = sfdres >> shift;\n\t\t  sfdres[0] = sfdres[0] | sfdlsb;\n\t       end\n\t       else begin\n\t\t  sfdres = 0;\n\t       end\n\n\t       result.exp = 0;\n\t    end\n\t    else begin\n\t       // inbounds\n\t       result.exp = cExtend(exp + fromInteger(bias(result)));\n\t    end\n\n\t    // $display(\"shift = %d\", shift);\n\t    // $display(\"sfdres = 'h%x\", sfdres);\n\t    // $display(\"result = \", fshow(result));\n\t    // $display(\"exc = 'b%b\", pack(exc));\n\t    // $display(\"zeros = %d\", countZerosMSB(sfdres));\n\n\t    result.sign = sign;\n\t    let y = normalize(result, sfdres);\n\t    result = tpl_1(y);\n\t    guard = tpl_2(y);\n\t    s.exc = s.exc | tpl_3(y);\n\n\t    // $display(\"result = \", fshow(result));\n\t    // $display(\"exc = 'b%b\", pack(exc));\n\t end\n\n\t rState_S4 <= tuple3(s,\n\t\t\t     result,\n\t\t\t     guard);\n\t rValid_S4 <= valid;\n      end\n   //endrule\n\n   ////////////////////////////////////////////////////////////////////////////////\n   /// S5\n   ////////////////////////////////////////////////////////////////////////////////\n\n   //rule s5_stage;\n      begin\n\t match {.s, .rnd, .guard} = rState_S4;\n\t let valid = rValid_S4;\n\n\t FloatingPoint#(e,m) out = rnd;\n\n\t if (s.res matches tagged Valid .x)\n\t    out = x;\n\t else begin\n\t    let y = round(s.rmode, out, guard);\n\t    out = tpl_1(y);\n\t    s.exc = s.exc | tpl_2(y);\n\t end\n\n\t if (valid)\n\t    fResult_S5.enq(tuple2(out,s.exc));\n      end\n   endrule\n\n   ////////////////////////////////////////////////////////////////////////////////\n   /// Interface Connections / Methods\n   ////////////////////////////////////////////////////////////////////////////////\n   interface request = toPut(fOperands_S0);\n   interface response = toGet(fResult_S5);\n\nendmodule: mkFPMultiplier\n////////////////////////////////////////////////////////////////////////////////\n\n////////////////////////////////////////////////////////////////////////////////\n/// Wrap Xilinx FP MUL\n////////////////////////////////////////////////////////////////////////////////\nmodule mkXilinxFPMultiplier#(RoundMode rmode)(Server#(Tuple2#(Float,Float), Tuple2#(Float,Exception)));\n\n   let clock <- exposeCurrentClock();\n   let reset <- exposeCurrentReset();\n\n   let fpMul <- mkFpMul();\n   Wire#(Bit#(1)) s_axis_ab_ready <- mkDWire(0);\n   Wire#(Bit#(1)) m_axis_tready <- mkDWire(0);\n   rule ab_ready;\n      fpMul.s_axis_a.tvalid(s_axis_ab_ready);\n      fpMul.s_axis_b.tvalid(s_axis_ab_ready);\n   endrule\n   rule c_ready;\n      fpMul.m_axis_result.tready(m_axis_tready);\n   endrule\n\n   ////////////////////////////////////////////////////////////////////////////////\n   /// Interface Connections / Methods\n   ////////////////////////////////////////////////////////////////////////////////\n   interface Put request;\n      method Action put(Tuple2#(Float,Float) req) if (fpMul.s_axis_a.tready() == 1 && fpMul.s_axis_b.tready() == 1);\n\t match { .a, .b } = req;\n\t fpMul.s_axis_a.tdata(pack(a));\n\t fpMul.s_axis_b.tdata(pack(b));\n\t s_axis_ab_ready <= 1;\n      endmethod\n   endinterface\n   interface Get response;\n      method ActionValue#(Tuple2#(Float,Exception)) get() if (fpMul.m_axis_result.tvalid() == 1);\n\t m_axis_tready <= 1;\n\t return tuple2(unpack(fpMul.m_axis_result.tdata()), defaultValue);\n      endmethod\n   endinterface\nendmodule: mkXilinxFPMultiplier\n////////////////////////////////////////////////////////////////////////////////\n\n////////////////////////////////////////////////////////////////////////////////\n/// Wrap Xilinx FP ADD\n////////////////////////////////////////////////////////////////////////////////\nmodule mkXilinxFPAdder#(RoundMode rmode)(Server#(Tuple2#(Float, Float), Tuple2#(Float,Exception)));\n\n   let clock <- exposeCurrentClock();\n   let reset <- exposeCurrentReset();\n\n   let fpAdd <- mkFpAdd();\n   Wire#(Bit#(1)) s_axis_ab_ready <- mkDWire(0);\n   Wire#(Bit#(1)) m_axis_tready <- mkDWire(0);\n   rule ab_ready;\n      fpAdd.s_axis_a.tvalid(s_axis_ab_ready);\n      fpAdd.s_axis_b.tvalid(s_axis_ab_ready);\n      fpAdd.s_axis_operation.tvalid(s_axis_ab_ready);\n   endrule\n   rule c_ready;\n      fpAdd.m_axis_result.tready(m_axis_tready);\n   endrule\n\n   ////////////////////////////////////////////////////////////////////////////////\n   /// Interface Connections / Methods\n   ////////////////////////////////////////////////////////////////////////////////\n   interface Put request;\n      method Action put(Tuple2#(Float,Float) req) if (fpAdd.s_axis_a.tready() == 1 && fpAdd.s_axis_b.tready() == 1);\n\t match { .a, .b } = req;\n\t fpAdd.s_axis_a.tdata(pack(a));\n\t fpAdd.s_axis_b.tdata(pack(b));\n\t fpAdd.s_axis_operation.tdata(0);\n\t s_axis_ab_ready <= 1;\n      endmethod\n   endinterface\n   interface Get response;\n      method ActionValue#(Tuple2#(Float,Exception)) get() if (fpAdd.m_axis_result.tvalid() == 1);\n\t m_axis_tready <= 1;\n\t return tuple2(unpack(fpAdd.m_axis_result.tdata()), defaultValue);\n      endmethod\n   endinterface\nendmodule: mkXilinxFPAdder\n////////////////////////////////////////////////////////////////////////////////\n\n"
  },
  {
    "path": "lib/matmul/bsv/FpMacTb.bsv",
    "content": "/* Copyright (c) 2014 Quanta Research Cambridge, Inc\n *\n * Permission is hereby granted, free of charge, to any person obtaining a\n * copy of this software and associated documentation files (the \"Software\"),\n * to deal in the Software without restriction, including without limitation\n * the rights to use, copy, modify, merge, publish, distribute, sublicense,\n * and/or sell copies of the Software, and to permit persons to whom the\n * Software is furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n * DEALINGS IN THE SOFTWARE.\n */\n// bsv libraries\nimport SpecialFIFOs::*;\nimport Vector::*;\nimport StmtFSM::*;\nimport FIFO::*;\nimport Connectable::*;\nimport FloatingPoint::*;\nimport ClientServer::*;\nimport GetPut::*;\nimport DefaultValue::*;\nimport FIFOF::*;\n\n// Connectal libraries\nimport RbmTypes::*;\nimport FpMac::*;\nimport FloatOps::*;\n\ninterface FpMacRequest;\n   method Action mac(Bit#(32) x, Bit#(32) y);\nendinterface\n\ninterface FpMacIndication;\n   method Action res(Bit#(32) v, Bit#(32) e);\nendinterface\n\nmodule mkFpMacRequest#(FpMacIndication indication) (FpMacRequest);\n   \n   let fpmac <- mkFloatMac(Rnd_Nearest_Even); //defaultValue\n   Reg#(Float) accum <- mkReg(0);\n   \n   rule res;\n      let resp <- fpmac.response.get;\n      accum <= tpl_1(resp);\n      indication.res(pack(tpl_1(resp)), extend(pack(tpl_2(resp))));\n   endrule\n   \n   method Action mac(Bit#(32) x, Bit#(32) y);\n      fpmac.request.put(tuple3(tagged Valid accum, unpack(x), unpack(y)));\n   endmethod\n\nendmodule\n\n\ninterface FpMulRequest;\n   method Action mul_req(Bit#(32) x, Bit#(32) y);\nendinterface\n\ninterface FpMulIndication;\n   method Action mul_resp(Bit#(32) v);\nendinterface\n\nmodule mkFpMulRequest#(FpMulIndication indication) (FpMulRequest);\n   \n   FloatAlu mul   <- mkFloatMultiplier(defaultValue);\n   Reg#(Float) accum <- mkReg(0);\n   Reg#(int) cycles <- mkReg(0);\n   Reg#(int) last_mul <- mkReg(0);\n   Reg#(int) num_reqs <- mkReg(0);\n   Reg#(int) num_resps <- mkReg(0);\n   let req_fifo <- mkFIFOF;\n   \n   rule cycle;\n      cycles <= cycles+1;\n   endrule\n   \n   rule feed if (num_reqs > 0);\n      num_reqs <= num_reqs-1;\n      mul.request.put(req_fifo.first);\n   endrule\n   \n   rule drain;\n      match {.resp,.*} <- mul.response.get;\n      accum <= resp;      \n      num_resps <= num_resps-1;\n      last_mul <= cycles;\n      $display(\"drain %d\", cycles-last_mul);\n   endrule\n      \n   rule res if (num_reqs == 0 && req_fifo.notEmpty);\n      indication.mul_resp(pack(accum));\n      req_fifo.deq;\n   endrule\n   \n   method Action mul_req(Bit#(32) x, Bit#(32) y);\n      req_fifo.enq(tuple2(unpack(x), unpack(y)));\n      num_reqs <= 64;\n      num_resps <= 64;\n   endmethod\n\nendmodule\n\n"
  },
  {
    "path": "lib/matmul/bsv/FpMul.bsv",
    "content": "/* Copyright (c) 2014 Quanta Research Cambridge, Inc\n *\n * Permission is hereby granted, free of charge, to any person obtaining a\n * copy of this software and associated documentation files (the \"Software\"),\n * to deal in the Software without restriction, including without limitation\n * the rights to use, copy, modify, merge, publish, distribute, sublicense,\n * and/or sell copies of the Software, and to permit persons to whom the\n * Software is furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n * DEALINGS IN THE SOFTWARE.\n */\n\n/*\n   /home/jamey/connectal/scripts/importbvi.py\n   -o\n   FpMul.bsv\n   -c\n   aclk\n   -f\n   s_axis_a\n   -f\n   s_axis_b\n   -f\n   m_axis_result\n   -I\n   FpMul\n   -P\n   FpMul\n   fp_mul_stub.v\n*/\n\nimport Clocks::*;\nimport DefaultValue::*;\nimport XilinxCells::*;\nimport GetPut::*;\n\n(* always_ready, always_enabled *)\ninterface FpmulM_axis_result;\n    method Bit#(32)     tdata();\n    method Action      tready(Bit#(1) v);\n    method Bit#(1)     tvalid();\nendinterface\n(* always_ready, always_enabled *)\ninterface FpmulS_axis_a;\n    method Action      tdata(Bit#(32) v);\n    method Bit#(1)     tready();\n    method Action      tvalid(Bit#(1) v);\nendinterface\n(* always_ready, always_enabled *)\ninterface FpmulS_axis_b;\n    method Action      tdata(Bit#(32) v);\n    method Bit#(1)     tready();\n    method Action      tvalid(Bit#(1) v);\nendinterface\n(* always_ready, always_enabled *)\ninterface FpMul;\n    interface FpmulM_axis_result     m_axis_result;\n    interface FpmulS_axis_a     s_axis_a;\n    interface FpmulS_axis_b     s_axis_b;\nendinterface\nimport \"BVI\" fp_mul =\nmodule mkFpMul(FpMul);\n    default_clock aclk(aclk);\n    default_reset aresetn(aresetn);\n    interface FpmulM_axis_result     m_axis_result;\n        method m_axis_result_tdata tdata();\n        method tready(m_axis_result_tready) enable((*inhigh*) EN_m_axis_result_tready);\n        method m_axis_result_tvalid tvalid();\n    endinterface\n    interface FpmulS_axis_a     s_axis_a;\n        method tdata(s_axis_a_tdata) enable((*inhigh*) EN_s_axis_a_tdata);\n        method s_axis_a_tready tready();\n        method tvalid(s_axis_a_tvalid) enable((*inhigh*) EN_s_axis_a_tvalid);\n    endinterface\n    interface FpmulS_axis_b     s_axis_b;\n        method tdata(s_axis_b_tdata) enable((*inhigh*) EN_s_axis_b_tdata);\n        method s_axis_b_tready tready();\n        method tvalid(s_axis_b_tvalid) enable((*inhigh*) EN_s_axis_b_tvalid);\n    endinterface\n    schedule (m_axis_result.tdata, m_axis_result.tready, m_axis_result.tvalid, s_axis_a.tdata, s_axis_a.tready, s_axis_a.tvalid, s_axis_b.tdata, s_axis_b.tready, s_axis_b.tvalid) CF (m_axis_result.tdata, m_axis_result.tready, m_axis_result.tvalid, s_axis_a.tdata, s_axis_a.tready, s_axis_a.tvalid, s_axis_b.tdata, s_axis_b.tready, s_axis_b.tvalid);\nendmodule\n"
  },
  {
    "path": "lib/matmul/bsv/MatrixNT.bsv",
    "content": "// Copyright (c) 2014 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n`include \"ConnectalProjectConfig.bsv\"\nimport FIFO::*;\nimport FIFOF::*;\nimport MIMO::*;\nimport DefaultValue::*;\nimport SpecialFIFOs::*;\nimport Vector::*;\nimport BRAM::*;\nimport ConnectalMemory::*;\nimport ConnectalMemTypes::*;\nimport MemReadEngine::*;\nimport MemWriteEngine::*;\nimport ConnectalMemUtils::*;\nimport FloatingPoint::*;\nimport Pipe::*;\nimport Arith::*;\nimport FloatOps::*;\nimport Timer::*;\nimport RbmTypes::*;\nimport Assert::*;\nimport Connectable::*;\nimport Clocks::*;\nimport Gearbox::*;\nimport XilinxCells::*;\nimport HostInterface::*;\nimport DotProdServer::*;\nimport DmaVector::*;\n\ninterface RowColSource#(numeric type dsz, type a);\n   interface PipeOut#(a) pipe;\n   method Action start(SGLId h, Bit#(MemOffsetSize) a, Bit#(MemOffsetSize) l, UInt#(32) tag);\n   method ActionValue#(Bool) finish();\nendinterface\n\ninterface RowColSink#(numeric type dsz, type a);\n   interface PipeIn#(a) pipe;\n   method Action start(SGLId h, Bit#(MemOffsetSize) a, Bit#(MemOffsetSize) l);\n   method ActionValue#(Bool) finish();\nendinterface\n\nfunction PipeOut#(dtype) getRowColSourcePipe(RowColSource#(dsz,dtype) vs); return vs.pipe; endfunction\nfunction PipeIn#(a) getRowColSinkPipe(RowColSink#(n,a) vs) = vs.pipe;\n\nmodule mkRowColSink#(VectorSink#(TMul#(N,32),Vector#(N,Float)) vs) (RowColSink#(TMul#(N,32), Vector#(N,MmToken)));\n   function Float tokenValue(MmToken v) = v.v;\n   method Action start(SGLId p, Bit#(MemOffsetSize) a, Bit#(MemOffsetSize) l);\n      vs.start(p,a,l);\n   endmethod\n   method finish = vs.finish;\n   interface PipeIn pipe;\n      method Action enq(Vector#(N,MmToken) v);\n\t vs.pipe.enq(map(tokenValue,v));\n      endmethod\n      method Bool notFull = vs.pipe.notFull;\n   endinterface\nendmodule\n\nmodule mkRowSource#(VectorSource#(TMul#(N,32),Vector#(N,Float)) vs) (RowColSource#(TMul#(N,32), Vector#(N,MmToken)));\n`ifdef TAGGED_TOKENS\n   Reg#(UInt#(32)) col <- mkReg(0);\n   FIFOF#(UInt#(32)) tagFifo <- mkSizedFIFOF(4);\n`endif\n   // perhaps memreadengine could do the labeling\n   Reg#(Bit#(MemOffsetSize)) countReg <- mkReg(0);\n   FIFOF#(Bit#(MemOffsetSize)) cmdFifo <- mkSizedFIFOF(4);\n\n   method Action start(SGLId h, Bit#(MemOffsetSize) a, Bit#(MemOffsetSize) l, UInt#(32) tag);\n`ifdef TAGGED_TOKENS\n      tagFifo.enq(tag);\n`endif\n      vs.start(h,a,l);\n      cmdFifo.enq(l);\n   endmethod \n   method ActionValue#(Bool) finish;\n      let rv <- vs.finish;\n      return rv;\n   endmethod\n   interface PipeOut pipe;\n      method Vector#(N,MmToken) first;\n\t Vector#(N,MmToken) rv;\n`ifdef TAGGED_TOKENS\n\t for(Integer i = 0; i < valueOf(N); i=i+1)\n\t    rv[i] = MmToken{row:tagFifo.first, col:col+fromInteger(i), v:vs.pipe.first[i], first:False, last:False};\n`else\n\t for(Integer i = 0; i < valueOf(N); i=i+1)\n\t    rv[i] = MmToken{v:vs.pipe.first[i], first:False, last:False};\n`endif\n\t if (countReg==0)\n\t    rv[0].first = True;\n\t if (countReg+1==cmdFifo.first)\n\t    rv[valueOf(N)-1].last = True;\n\t return rv;\n      endmethod\n      method Action deq;\n\t vs.pipe.deq;\n\t //$display(\"mkRowSource count=%d first=%d last=%d\", countReg, firstReg, lastReg);\n\t if(countReg+1==cmdFifo.first) begin\n\t    countReg <= 0;\n\t    cmdFifo.deq;\n`ifdef TAGGED_TOKENS\n\t    tagFifo.deq;\n\t    col <= 0;\n`endif      \n\t end\n\t else begin\n`ifdef TAGGED_TOKENS\n\t    col <= col+fromInteger(valueOf(N));\n`endif\n\t    countReg <= countReg + 1;\n\t end\n      endmethod\n      method Bool notEmpty;\n`ifdef TAGGED_TOKENS\n\t return (tagFifo.notEmpty && vs.pipe.notEmpty);\n`else\n\t return (vs.pipe.notEmpty);\n`endif\n      endmethod\n   endinterface\nendmodule\n\nmodule mkColSource#(VectorSource#(TMul#(N,32),Vector#(N,Float)) vs) (RowColSource#(TMul#(N,32), Vector#(N,MmToken)));\n`ifdef TAGGED_TOKENS\n   Reg#(UInt#(32)) row <- mkReg(0);\n   FIFOF#(UInt#(32)) tagFifo <- mkSizedFIFOF(4);\n`endif\n   // perhaps memreadengine could do the labeling\n   Reg#(Bit#(MemOffsetSize)) countReg <- mkReg(0);\n   FIFOF#(Bit#(MemOffsetSize)) cmdFifo <- mkSizedFIFOF(4);\n\n   method Action start(SGLId h, Bit#(MemOffsetSize) a, Bit#(MemOffsetSize) l, UInt#(32) tag);\n`ifdef TAGGED_TOKENS\n      tagFifo.enq(tag);\n`endif\n      vs.start(h,a,l);\n      cmdFifo.enq(l);\n   endmethod\n   method ActionValue#(Bool) finish;\n      let rv <- vs.finish;\n      return rv;\n   endmethod\n   interface PipeOut pipe;\n      method Vector#(N,MmToken) first;\n\t Vector#(N,MmToken) rv;\n`ifdef TAGGED_TOKENS\n\t for(Integer i = 0; i < valueOf(N); i=i+1)\n\t    rv[i] = MmToken{row:row+fromInteger(i), col:tagFifo.first, v:vs.pipe.first[i], first:False, last:False};\n`else\n\t for(Integer i = 0; i < valueOf(N); i=i+1)\n\t    rv[i] = MmToken{v:vs.pipe.first[i], first:False, last:False};\n`endif\n\t if (countReg==0)\n\t    rv[0].first = True;\n\t if (countReg+1==cmdFifo.first)\n\t    rv[valueOf(N)-1].last = True;\n\t return rv;\n      endmethod\n      method Action deq;\n\t vs.pipe.deq;\n\t if(countReg+1==cmdFifo.first) begin\n\t    countReg <= 0;\n\t    cmdFifo.deq;\n`ifdef TAGGED_TOKENS\n\t    tagFifo.deq;\n\t    row <= 0;\n`endif      \n\t end\n\t else begin\n`ifdef TAGGED_TOKENS\n\t    row <= row+fromInteger(valueOf(N));\n`endif\n\t    countReg <= countReg+1;\n\t end\n      endmethod\n      method Bool notEmpty;\n`ifdef TAGGED_TOKENS\n\t return (tagFifo.notEmpty && vs.pipe.notEmpty);\n`else\n\t return (vs.pipe.notEmpty);\n`endif\n      endmethod\n   endinterface\nendmodule: mkColSource\n   \n// row major layout\ninterface DmaMatrixMultiplyIfc#(numeric type addrwidth, numeric type dsz);\n   method Action start(SGLId pointerA, UInt#(addrwidth) numRowsA, UInt#(addrwidth) numColumnsA,\n\t\t       SGLId pointerB, UInt#(addrwidth) numRowsB, UInt#(addrwidth) numColumnsB,\n\t\t       SGLId pointerC,\n\t\t       UInt#(addrwidth) numRowsA_x_numColumnsA, UInt#(addrwidth) numColumnsA_x_J,\n\t\t       UInt#(addrwidth) numRowsB_x_numColumnsB, UInt#(addrwidth) numColumnsB_x_K,\n\t\t       UInt#(addrwidth) numRowsA_x_numRowsB,    UInt#(addrwidth) numRowsB_x_J);\n   method ActionValue#(Bool) finish();\n   interface DmaMatrixMultiplyDebug debug;\nendinterface\n\ntypedef enum {\n   Idle, Ready, Running, Done\n   } MMState deriving (Bits, Eq);\n\n/*!\n * Multiplies two matrices A and B and writes the result to memory.\n * Fetches J rows at a time from A and K rows at a time from B.\n * Each cycle, it can fetch N elements of a row or column.\n *\n * Just considering memory bandwidth, every J+K cycles it is ready to perform J*K*N multiply accumulates.\n *\n */\nmodule  mkDmaMatrixMultiply#(Vector#(J, VectorSource#(dsz, Vector#(N, Float))) sA,\n\t\t\t     Vector#(K, VectorSource#(dsz, Vector#(N, Float))) sB,\n\t\t\t     Vector#(J, VectorSink#(dsz, Vector#(N,Float)))    ss,\n\t\t\t     HostInterface host\n\t\t\t     )(DmaMatrixMultiplyIfc#(addrwidth, dsz))\n   provisos (  Mul#(N,n__,K) // K must be an integer multiple of N\n\t     , Mul#(N,m__,J) // J must be an integer multiple of N\n             , Add#(1,o__,J)\n\t     , Log#(N,nshift)\n\t     , FShow#(Float)\n\t     , Arith#(Float)\n\t     , Bits#(Vector#(N, Float), dsz)\n\t     , Bits#(MatrixDescriptor#(UInt#(addrwidth)), mdsz)\n\t     , Bits#(Tuple2#(UInt#(addrwidth), UInt#(addrwidth)), tplsz)\n\t     , Add#(b__, 20, addrwidth)\n\t     , Add#(a__, addrwidth, MemOffsetSize)\n\t     , Add#(c__, addrwidth, 32)\n\t     , Max#(1, TDiv#(TLog#(J),2), bpc_j)\n\t     , Max#(1, TDiv#(TLog#(K),2), bpc_k)\n      );\n\n   let n = valueOf(N);\n   let jj = valueOf(J);\n   let kk = valueOf(K);\n   let tt = valueOf(T);\n   let nshift = valueOf(nshift);\n   Bool verbose = False;\n   Bool verbose1 = False;\n   Bool timing = False;\n\n   let defaultClock <- exposeCurrentClock();\n   let defaultReset <- exposeCurrentReset();\n\n   let derivedClock = host.derivedClock;\n   let currentReset <- exposeCurrentReset;\n   let derivedReset <- mkAsyncReset(2, currentReset, derivedClock);\n\n   Reg#(UInt#(32)) cycles <- mkReg(0);\n   Reg#(Bool) doneReg <- mkReg(False);\n   FIFOF#(MatrixDescriptor#(UInt#(addrwidth))) descFifoA <- mkSizedFIFOF(1);\n   FIFOF#(MatrixDescriptor#(UInt#(addrwidth))) descFifoB <- mkSizedFIFOF(1);\n   FIFOF#(MatrixDescriptor#(UInt#(addrwidth))) descFifoC <- mkSizedFIFOF(1);\n   UnFunnelPipe#(1,J,MatrixDescriptor#(UInt#(addrwidth)),bpc_j) descriptorA <- mkPipelinedForkVector(toPipeOut(descFifoA), 0);\n   UnFunnelPipe#(1,K,MatrixDescriptor#(UInt#(addrwidth)),bpc_k) descriptorB <- mkPipelinedForkVector(toPipeOut(descFifoB), 1);\n   UnFunnelPipe#(1,J,MatrixDescriptor#(UInt#(addrwidth)),bpc_j) descriptorC <- mkPipelinedForkVector(toPipeOut(descFifoC), 2);\n   Reg#(UInt#(addrwidth)) dotprodCount <- mkReg(0);\n   \n   Vector#(J, RowColSource#(TMul#(N,32), Vector#(N,MmToken))) sourceA <- mapM(mkRowSource, sA);\n   Vector#(K, RowColSource#(TMul#(N,32), Vector#(N,MmToken))) sourceB <- mapM(mkColSource, sB);\n   Vector#(J, RowColSink#(TMul#(N,32),   Vector#(N,MmToken))) sinks   <- mapM(mkRowColSink,ss);\n   Vector#(J, PipeOut#(MmToken))       aPipes <- mapM(mkFunnelGB1(defaultClock, defaultReset, derivedClock, derivedReset), map(getRowColSourcePipe, sourceA));\n   Vector#(K, PipeOut#(MmToken))       bPipes <- mapM(mkFunnelGB1(defaultClock, defaultReset, derivedClock, derivedReset), map(getRowColSourcePipe, sourceB));\n   PipeOut#(MmToken)                  bFunnel <- mkFunnelPipes1(bPipes, clocked_by derivedClock, reset_by derivedReset);\n   Vector#(J, PipeOut#(MmToken)) bFunnelPipes <- mkForkVector(bFunnel, clocked_by derivedClock, reset_by derivedReset);\n\n   rule countCycles;\n      cycles <= cycles+1;\n   endrule\n\n   UInt#(TAdd#(TLog#(K),1)) repetitions = fromInteger(valueOf(K));\n   Vector#(J, PipeOut#(MmToken)) aRepeaters <- mapM(mkRepeat(repetitions), aPipes, clocked_by derivedClock, reset_by derivedReset);\n\n   Vector#(T, MmTile) mmTiles <- mapM(mkMmTile(defaultClock, defaultReset), map(fromInteger,genVector), clocked_by derivedClock, reset_by derivedReset);\n   Vector#(J, PipeOut#(Vector#(N,MmToken))) fxpipes;\n   for (Integer t = 0; t < valueOf(T); t = t+1) begin\n      for (Integer i = 0; i < valueof(RowsPerTile); i = i+1) begin\n\t let j = t*valueOf(RowsPerTile) + i;\n\t mkConnection(toGet(aRepeaters[j]), mmTiles[t].aInputs[i], clocked_by derivedClock, reset_by derivedReset);\n\t mkConnection(toGet(bFunnelPipes[j]), mmTiles[t].bInputs[i], clocked_by derivedClock, reset_by derivedReset);\n\t fxpipes[j] = mmTiles[t].fxPipes[i];\n      end\n   end\n   \n   zipWithM(mkConnection, fxpipes, map(getRowColSinkPipe, sinks));\n   \n   XYIteratorIfc#(UInt#(addrwidth)) indexpipeifc <- mkXYIterator();\n   XYIteratorIfc#(UInt#(addrwidth)) offsetpipeA <- mkXYIterator();\n   XYIteratorIfc#(UInt#(addrwidth)) offsetpipeB <- mkXYIterator();\n   XYIteratorIfc#(UInt#(addrwidth)) offsetpipeC <- mkXYIterator();\n\n   Vector#(TAdd#(J,K), PipeOut#(Tuple2#(UInt#(addrwidth),UInt#(addrwidth)))) indexpipes <- mkForkVector(indexpipeifc.pipe);\n   Vector#(J, PipeOut#(Tuple2#(UInt#(addrwidth),UInt#(addrwidth))))        offsetpipesA <- mkForkVector(offsetpipeA.pipe);\n   Vector#(K, PipeOut#(Tuple2#(UInt#(addrwidth),UInt#(addrwidth))))        offsetpipesB <- mkForkVector(offsetpipeB.pipe);\n   Vector#(J, PipeOut#(Tuple2#(UInt#(addrwidth),UInt#(addrwidth))))        offsetpipesC <- mkForkVector(offsetpipeC.pipe);\n   \n   Vector#(J, Reg#(UInt#(32))) lastStartAs <- replicateM(mkReg(0));\n   Vector#(K, Reg#(UInt#(32))) lastStartBs <- replicateM(mkReg(0));\n   Vector#(K, Reg#(UInt#(32))) lastStartCs <- replicateM(mkReg(0));\n      \n   Reg#(Bool) running <- mkReg(False);\n   FIFOF#(Bool) doneFifo <- mkFIFOF();\n   FIFOF#(Bool) initNumEltsFifo <- mkFIFOF();\n   \n   Vector#(J, Reg#(UInt#(addrwidth))) startAOffset <- replicateM(mkReg(0));\n   Vector#(K, Reg#(UInt#(addrwidth))) startBOffset <- replicateM(mkReg(0));\n   Vector#(J, Reg#(UInt#(addrwidth))) startCOffset <- replicateM(mkReg(0));\n\n   Vector#(K, FIFO#(void)) controlDependenceB <- replicateM(mkFIFO);\n   for (Integer k = 0; k < kk; k = k + 1) begin\n      rule startSourceB if (!initNumEltsFifo.notEmpty);\n\t \n\t if(k > 0)\n\t    controlDependenceB[k-1].deq;\n\t if(k < kk-1)\n\t    controlDependenceB[k].enq(?);\n\n\t Tuple2#(UInt#(addrwidth),UInt#(addrwidth)) index <- toGet(indexpipes[k]).get();\n\t match { .unusedB, .startBBase } <- toGet(offsetpipesB[k]).get();\n\n\t int kint = fromInteger(k);\n\n\t let row = tpl_1(index);\n\t let col = tpl_2(index)+fromInteger(k);\n\n\t let startB = startBBase + startBOffset[k];\n\t \n\t lastStartBs[k] <= cycles;\n\t let interval = cycles-lastStartBs[k];\n\n\t if (timing || verbose) $display($format(fshow(interval)+fshow(\"    startB index=\")+fshow(tuple2(row,col))\n\t    +fshow(\" startB=\")+fshow(startB)\n\t    +fshow(\" k=\")+fshow(kint)));\n\n\t if (verbose || verbose1) $display($format(fshow(cycles)+fshow(\"    sourceB[\")+fshow(kint)+fshow(\"].start\")+fshow(startB)));\n\n\t sourceB[k].start(descriptorB[k].first.sglId, pack(extend(startB>>nshift)), pack(extend(descriptorB[k].first.numColumns>>nshift)), extend(col));\n\n      endrule\n      rule finishSourceB;\n\t UInt#(TLog#(K)) in = fromInteger(k);\n\t int kint = fromInteger(k);\n\t if (timing || verbose || verbose1) $display($format(fshow(cycles)+fshow(\"    sourceB[\")+fshow(kint)+fshow(\"].finish\")));\n\t let b <- sourceB[k].finish();\n      endrule\n   end\n   Vector#(J, FIFO#(void)) controlDependenceA <- replicateM(mkFIFO);\n   for (Integer j = 0; j < jj; j = j + 1) begin\n\n      int jint = fromInteger(j);\n      rule startSourceAndSink if (!initNumEltsFifo.notEmpty);\n\t \n\t if(j > 0)\n\t    controlDependenceA[j-1].deq;\n\t if(j < jj-1)\n\t    controlDependenceA[j].enq(?);\n\n\t Tuple2#(UInt#(addrwidth),UInt#(addrwidth)) index <- toGet(indexpipes[j+kk]).get();\n\t \n\t let row = tpl_1(index)+fromInteger(j);\n\t let col = tpl_2(index);\n\t \n\t match { .startABase, .unusedA } <- toGet(offsetpipesA[j]).get();\n\t match { .startCBase, .offsetC } <- toGet(offsetpipesC[j]).get();\n\t let startA = startABase + startAOffset[j];\n\t let startC = startCBase + startCOffset[j] + offsetC;\n\t \n\t int jint = fromInteger(j);\n\t if (timing || verbose) $display($format(fshow(cycles)+fshow(\"    start A index=\")+fshow(tuple2(row,col))\n\t\t\t\t\t\t +fshow(\" startA=\")+fshow(startA)\n\t\t\t\t\t\t +fshow(\" startC=\")+fshow(startC)\n\t\t\t\t\t\t +fshow(\" j=\")+fshow(jint)));\n\t \n\t sourceA[j].start(descriptorA[j].first.sglId, pack(extend(startA>>nshift)), pack(extend(descriptorA[j].first.numColumns>>nshift)), extend(row));\n\t if (verbose || verbose1) $display($format(fshow(cycles)+fshow(\"    sourceA[\")+fshow(jint)+fshow(\"].start\")+fshow(startA)));\n\t sinks[j].start(descriptorC[j].first.sglId, pack(extend(startC>>nshift)), fromInteger(kk/n));\n\t if (verbose || verbose1) $display($format(fshow(cycles)+fshow(\"      sinks[\")+fshow(jint)+fshow(\"].start\")+fshow(startC)));\n\t \n      endrule\n\n      rule finishSourceA;\n\t if (timing || verbose || verbose1) $display($format(fshow(cycles)+fshow(\"    sourceA[\")+fshow(jint)+fshow(\"].finish \")));\n\t let b <- sourceA[j].finish();\n      endrule\n\n      rule finishSink;\n\t $dumpoff();\n\t // each time we write a burst of k values via sinks\n\t //let index <- toGet(indexpipes[jj+kk+1]).get();\n\t let b <- sinks[j].finish();\n\t let c = dotprodCount-fromInteger(kk);\n\t int jint = fromInteger(j);\n\t if (timing || verbose1) $display($format(fshow(cycles)+fshow(\"    finishSink c\")+fshow(c)+fshow(\" j=\")+fshow(jint)));\n\t dotprodCount <= c;\n\t if (c == 0) begin\n\t    running <= False;\n\t    doneFifo.enq(?);\n\t    for(Integer i = 0; i < kk; i=i+1)\n\t       descriptorB[i].deq;\n\t    for(Integer i = 0; i < jj; i=i+1) begin\n\t       descriptorA[i].deq;\n\t       descriptorC[i].deq;\n\t    end\n\t end\n      endrule\n   end\n\n   rule dotProdsNumElts;\n      initNumEltsFifo.deq();\n      let numColumnsA = descriptorA[0].first.numColumns;\n      let numColumnsB = descriptorB[0].first.numColumns;\n      let numRowsB    = descriptorB[0].first.numRows;\n      for (Integer j = 0; j < jj; j = j + 1) begin\n\t startAOffset[j] <= fromInteger(j)*numColumnsA;\n\t startCOffset[j] <= fromInteger(j)*numRowsB;\n      end\n      for (Integer k = 0; k < kk; k = k + 1) begin\n\t startBOffset[k] <= fromInteger(k)*numColumnsB;\n      end\n  endrule\n\n   function PipeOut#(Bit#(32)) mmTileMacCount(MmTile mmtile); return mmtile.debug.macCount; endfunction\n   Vector#(T, PipeOut#(Vector#(2,Bit#(32)))) macCountPipes <- mapM(mkUnfunnelGB(defaultClock, defaultReset, derivedClock, derivedReset),\n\t\t\t\t\t\t\t\t   map(mapPipe(replicate),\n\t\t\t\t\t\t\t\t       map(mmTileMacCount, mmTiles)));\n   PipeOut#(Bit#(32)) macCountPipe <- mkReducePipes(uncurry(add), map(mapPipe(head),macCountPipes));\n   Reg#(Bit#(32)) macCountReg <- mkReg(0);\n   rule updateMacCount;\n      let mc <- toGet(macCountPipe).get();\n      macCountReg <= mc;\n   endrule\n\n   function Bool pipeNotEmpty(RowColSource#(asz, a) vs); return vs.pipe.notEmpty(); endfunction\n\n   method Action start(SGLId pointerA, UInt#(addrwidth) numRowsA, UInt#(addrwidth) numColumnsA,\n\t\t       SGLId pointerB, UInt#(addrwidth) numRowsB, UInt#(addrwidth) numColumnsB,\n\t\t       SGLId pointerC,\n\t\t       UInt#(addrwidth) numRowsA_x_numColumnsA, UInt#(addrwidth) numColumnsA_x_J,\n\t\t       UInt#(addrwidth) numRowsB_x_numColumnsB, UInt#(addrwidth) numColumnsB_x_K,\n\t\t       UInt#(addrwidth) numRowsA_x_numRowsB,    UInt#(addrwidth) numRowsB_x_J\n\t\t       ) if (!running);\n      XYIteratorConfig#(UInt#(addrwidth)) indexcfg  = XYIteratorConfig {xbase: 0, xlimit: numRowsA, xstep: fromInteger(jj),\n\t\t\t\t\t\t\t\t  ybase: 0, ylimit: numRowsB, ystep: fromInteger(kk) };\n      XYIteratorConfig#(UInt#(addrwidth)) offsetcfgA = XYIteratorConfig {xbase: 0, xlimit: numRowsA_x_numColumnsA, xstep: numColumnsA_x_J,\n\t\t\t\t\t\t\t\t  ybase: 0, ylimit: numRowsB, ystep: fromInteger(kk) };\n      XYIteratorConfig#(UInt#(addrwidth)) offsetcfgB = XYIteratorConfig {xbase: 0, xlimit: numRowsA, xstep: fromInteger(jj),\n\t\t\t\t\t\t\t\t  ybase: 0, ylimit: numRowsB_x_numColumnsB, ystep: numColumnsB_x_K };\n      XYIteratorConfig#(UInt#(addrwidth)) offsetcfgC = XYIteratorConfig {xbase: 0, xlimit: numRowsA_x_numRowsB, xstep: numRowsB_x_J,\n\t\t\t\t\t\t\t\t  ybase: 0, ylimit: numRowsB, ystep: fromInteger(kk) };\n      descFifoA.enq(MatrixDescriptor { sglId: pointerA, base: 0, numRows: numRowsA, numColumns: numColumnsA});\n      descFifoB.enq(MatrixDescriptor { sglId: pointerB, base: 0, numRows: numRowsB, numColumns: numColumnsB});\n      descFifoC.enq(MatrixDescriptor { sglId: pointerC, base: 0, numRows: numRowsA, numColumns: numRowsB});\n      dotprodCount <= numRowsA_x_numRowsB;\n      running <= True;\n\n      if (verbose) $display(\"mm pointerA=%d pointerB=%d pointerC=%d\\n\", pointerA, pointerB, pointerC);\n      if (verbose) $display(\"mm.start ra=%d ca=%d rb=%d cb=%d dotprodCount=%d\", numRowsA, numColumnsA, numRowsB, numColumnsB, dotprodCount);\n      if (verbose) $display($format(fshow(\"mm.start \")+fshow(indexcfg)));\n      if (verbose) $display($format(fshow(\"offsetcfgA \")+fshow(offsetcfgA)));\n      if (verbose) $display($format(fshow(\"offsetcfgB \")+fshow(offsetcfgB)));\n      if (verbose) $display($format(fshow(\"offsetcfgC \")+fshow(offsetcfgC)));\n\n      indexpipeifc.start(indexcfg);\n      offsetpipeA.start(offsetcfgA);\n      offsetpipeB.start(offsetcfgB);\n      offsetpipeC.start(offsetcfgC);\n\n      $display(\"initNumElts\");\n      initNumEltsFifo.enq(True);\n\n      //$dumpfile(\"test.vcd\");\n      //$dumpvars();\n   endmethod\n   method ActionValue#(Bool) finish();\n      if (verbose) $display(\"mm.finish()\");\n      doneFifo.deq();\n      return True;\n   endmethod\n   interface DmaMatrixMultiplyDebug debug;\n      method Bit#(32) macCount(); return macCountReg; endmethod\n    endinterface\nendmodule : mkDmaMatrixMultiply\n\ninterface DramMatrixMultiply#(numeric type n, numeric type dmasz, numeric type nm);\n   interface Vector#(nm, MemReadClient#(dmasz)) readClients;\n   interface Vector#(nm, MemWriteClient#(dmasz)) writeClients;\n   method Action start(SGLId pointerA, UInt#(MMSize) numRowsA, UInt#(MMSize) numColumnsA,\n\t\t       SGLId pointerB, UInt#(MMSize) numRowsB, UInt#(MMSize) numColumnsB,\n\t\t       SGLId pointerC,\n\t\t       UInt#(MMSize) numRowsA_x_numColumnsA, UInt#(MMSize) numColumnsA_x_J,\n\t\t       UInt#(MMSize) numRowsB_x_numColumnsB, UInt#(MMSize) numColumnsB_x_K,\n\t\t       UInt#(MMSize) numRowsA_x_numRowsB,    UInt#(MMSize) numRowsB_x_J);\n   method ActionValue#(Bool) finish();\n   interface DmaMatrixMultiplyDebug debug;\nendinterface\n\nmodule  mkDramMatrixMultiply#(HostInterface host)(DramMatrixMultiply#(N,TMul#(N,32),2));\n   MemWriteEngine#(TMul#(N,32),TMul#(N,32),2, J)   writeEngine <- mkMemWriteEngine();\n   MemReadEngine#(TMul#(N,32), TMul#(N,32), 2, J) rowReadEngine <- mkMemReadEngineBuff(512);\n   MemReadEngine#(TMul#(N,32), TMul#(N,32), 2, K) colReadEngine <- mkMemReadEngineBuff(512);\n   \n   Vector#(J, MemReadServer#(TMul#(N,32))) rowReadServers = rowReadEngine.readServers;\n   Vector#(K, MemReadServer#(TMul#(N,32))) colReadServers = colReadEngine.readServers;\n      \n   MemWriter#(TMul#(32,N)) bogusWriter <- mkMemWriter;\n   \n   Vector#(J, VectorSource#(DmaSz, Vector#(N,Float))) xvfsources <- mapM(mkMemReadVectorSource, rowReadServers);\n   Vector#(K, VectorSource#(DmaSz, Vector#(N,Float))) yvfsources <- mapM(mkMemReadVectorSource, colReadServers);\n   Vector#(J,   VectorSink#(DmaSz, Vector#(N,Float)))      sinks <- mapM(mkMemWriteVectorSink, writeEngine);\n   \n   DmaMatrixMultiplyIfc#(MMSize,DmaSz) dmaMMF <- mkDmaMatrixMultiply(xvfsources, yvfsources, sinks, host);\n   interface Vector readClients  = cons(rowReadEngine.dmaClient, cons(colReadEngine.dmaClient, nil));\n   interface Vector writeClients = cons(writeEngine.dmaClient,   cons(bogusWriter.writeClient, nil));\n   method start = dmaMMF.start;\n   method finish = dmaMMF.finish;\n   interface DmaMatrixMultiplyDebug debug = dmaMMF.debug;\nendmodule\n   \ninterface MmNT#(numeric type n);\n   interface MmRequestNT mmRequest;\n   interface TimerRequest timerRequest;\n   interface Vector#(2, MemReadClient#(TMul#(32,n)))  readClients;\n   interface Vector#(2, MemWriteClient#(TMul#(32,n))) writeClients;\nendinterface\n\nmodule  mkMmNT#(MmIndication ind, TimerIndication timerInd, HostInterface host)(MmNT#(N))\n   provisos (Add#(1,a__,N),\n\t     Add#(N,0,n),\n\t     Mul#(N,32,DmaSz)\n\t     );\n\n   let n = valueOf(n);\n\n   DramMatrixMultiply#(N,TMul#(N,32),2) dmaMMF <- mkDramMatrixMultiply(host);\n\n   Reg#(Bit#(64)) mmfCycles <- mkReg(0);\n   rule countMmfCycles;\n      mmfCycles <= mmfCycles + 1;\n   endrule\n\n   FIFOF#(Bool) busyFifo <- mkFIFOF();\n   rule mmfDone;\n      let d <- dmaMMF.finish();\n      busyFifo.deq();\n      ind.mmfDone(mmfCycles);\n   endrule\n\n   FIFOF#(Bool) timerRunning <- mkFIFOF();\n   Reg#(Bit#(64)) cycleCount <- mkReg(0);\n   Reg#(Bit#(64)) idleCount <- mkReg(0);\n   rule countCycles if (timerRunning.notEmpty());\n      cycleCount <= cycleCount + 1;\n      if (!busyFifo.notEmpty())\n\t idleCount <= idleCount + 1;\n   endrule\n\n   interface TimerRequest timerRequest;\n      method Action startTimer() if (!timerRunning.notEmpty());\n\t cycleCount <= 0;\n\t idleCount <= 0;\n\t timerRunning.enq(True);\n      endmethod\n      method Action stopTimer();\n\t timerRunning.deq();\n\t timerInd.elapsedCycles(cycleCount, idleCount);\n      endmethod\n   endinterface\n\n   interface MmRequestNT mmRequest;\n      method Action mmf(Bit#(32) h1, Bit#(32) r1, Bit#(32) c1,\n\t\t\tBit#(32) h2, Bit#(32) r2, Bit#(32) c2,\n\t\t\tBit#(32) h3,\n\t\t\tBit#(32) r1_x_c1, Bit#(32) c1_x_j,\n\t\t\tBit#(32) r2_x_c2, Bit#(32) c2_x_k,\n\t\t\tBit#(32) r1_x_r2, Bit#(32) r2_x_j);\n\t check_dimension(r1);\n\t check_dimension(c1);\n\t check_dimension(r2);\n\t check_dimension(c2);\n\t dmaMMF.start(h1, unpack(truncate(r1)), unpack(truncate(c1)),\n\t\t      h2, unpack(truncate(r2)), unpack(truncate(c2)),\n\t\t      h3,\n\t\t      unpack(truncate(r1_x_c1)), unpack(truncate(c1_x_j)),\n\t\t      unpack(truncate(r2_x_c2)), unpack(truncate(c2_x_k)),\n\t\t      unpack(truncate(r1_x_r2)), unpack(truncate(r2_x_j)));\n\n\t mmfCycles <= 0;\n\t busyFifo.enq(True);\n      endmethod\n      method Action debug();\n\t let macCount = dmaMMF.debug.macCount();\n\t ind.debug(macCount);\n      endmethod\n   endinterface\n\n   interface Vector readClients = dmaMMF.readClients;\n   interface Vector writeClients =  dmaMMF.writeClients;\n\nendmodule\n"
  },
  {
    "path": "lib/matmul/bsv/MatrixTN.bsv",
    "content": "// Copyright (c) 2014 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\n`include \"ConnectalProjectConfig.bsv\"\nimport BRAMFIFO::*;\nimport FIFO::*;\nimport FIFOF::*;\nimport MIMO::*;\nimport DefaultValue::*;\nimport SpecialFIFOs::*;\nimport Vector::*;\nimport ConnectalMemory::*;\nimport ConnectalMemTypes::*;\nimport ConnectalMemUtils::*;\nimport FloatingPoint::*;\nimport Pipe::*;\nimport Arith::*;\nimport FloatOps::*;\nimport Timer::*;\nimport RbmTypes::*;\nimport Assert::*;\nimport Connectable::*;\nimport Clocks::*;\nimport Gearbox::*;\nimport XilinxCells::*;\nimport HostInterface::*;\nimport DotProdServer::*;\nimport ClientServer::*;\nimport GetPut::*;\n\ninterface RowColSource#(numeric type dsz, type a);\n   interface PipeOut#(a) pipe;\n   method Action start(SGLId h, Bit#(MemOffsetSize) a, Bit#(MemOffsetSize) l, UInt#(32) tag);\nendinterface\n\ninterface RowColSink#(numeric type dsz, type a);\n   interface PipeIn#(a) pipe;\n   method Action start(SGLId h, Bit#(MemOffsetSize) a, Bit#(MemOffsetSize) l);\n   method ActionValue#(Bool) finish();\nendinterface\n\ntypedef struct {\n   a xbase;\n   a xlimit;\n   a xstep;\n   a ybase;\n   a ylimit;\n   a ystep;\n   a zbase;\n   a zlimit;\n   a zstep;\n} XYZIteratorConfig#(type a) deriving (Bits, FShow);\n\ninterface XYZIteratorIfc#(type a);\n   interface PipeOut#(Tuple2#(a,a)) pipe;\n   method Action start(XYZIteratorConfig#(a) cfg);\n   method Action display();\nendinterface\n\ntypedef enum {RangeA,RangeB,RangeC} RangeBehavior deriving (Eq); \n\nmodule mkXYZIterator#(RangeBehavior alt) (XYZIteratorIfc#(a)) provisos (Arith#(a), Bits#(a,awidth), Eq#(a), Ord#(a));\n   Reg#(a) x <- mkReg(0);\n   Reg#(a) y <- mkReg(0);\n   Reg#(a) z <- mkReg(0);\n   Reg#(a) xbase <- mkReg(0);\n   Reg#(a) ybase <- mkReg(0);\n   Reg#(a) zbase <- mkReg(0);\n   Reg#(a) xstep <- mkReg(0);\n   Reg#(a) ystep <- mkReg(0);\n   Reg#(a) zstep <- mkReg(0);\n   Reg#(a) xlimit <- mkReg(0);\n   Reg#(a) ylimit <- mkReg(0);\n   Reg#(a) zlimit <- mkReg(0);\n   \n   let guard = (x < xlimit && y < ylimit && z < zlimit);\n   \n   interface PipeOut pipe;\n      method Tuple2#(a,a) first() if (guard);\n\t if (alt==RangeA)\n\t    return tuple2(x,z);\n\t else if (alt == RangeB)\n\t    return tuple2(x,y);\n\t else //if (alt == RangeC)\n\t    return tuple2(x+y,z);\n      endmethod\n      method Action deq if (guard);\n\t let newx = x+xstep;\n\t let newy = y;\n\t let newz = z;\n\t if (newx >= xlimit) begin\n\t    newx = xbase;\n\t    newy = y + ystep;\n\t    if (newy >= ylimit) begin\n\t       newy = ybase;\n\t       newz = z + zstep;\n\t    end\n\t end\n\t x <= newx;\n\t y <= newy;\n\t z <= newz;\n      endmethod\n      method Bool notEmpty();\n\t return guard;\n      endmethod\n   endinterface\n   method Action start(XYZIteratorConfig#(a) cfg) if (!guard);\n      x <= cfg.xbase;\n      y <= cfg.ybase;\n      z <= cfg.zbase;\n      xbase <= cfg.xbase;\n      ybase <= cfg.ybase;\n      zbase <= cfg.zbase;\n      xstep <= cfg.xstep;\n      ystep <= cfg.ystep;\n      zstep <= cfg.zstep;\n      xlimit <= cfg.xlimit;\n      ylimit <= cfg.ylimit;\n      zlimit <= cfg.zlimit;\n   endmethod\n   method Action display();\n      $display(\"XYZIterator x=%d xlimit=%d y=%d ylimit=%d z=%d zlimit=%d xstep=%d ystep=%d zstep=%d\", x, xlimit, y, ylimit, z, zlimit,  xstep, ystep, zstep);\n   endmethod\nendmodule: mkXYZIterator\n\nmodule mkRowSource#(MemReadServer#(TMul#(N,32)) vs, Reg#(UInt#(addrwidth)) numRows, Bit#(MemTagSize) id) (RowColSource#(TMul#(N,32), Vector#(N,MmToken)))\n   provisos (Bits#(Vector#(N,Float),asz),\n      Div#(asz,8,abytes),\n      Log#(abytes,ashift),\n      Mul#(abytes, 8, asz)\n      );\n   \n   let cmd_buffer_depth = 32;\n   \n   let verbose = False;   \n   let ashift = valueOf(ashift);\n`ifdef TAGGED_TOKENS\n   Reg#(UInt#(32)) row <- mkReg(0);\n   FIFOF#(UInt#(32)) tagFifo <- mkSizedBRAMFIFOF(cmd_buffer_depth);\n`endif\n   // perhaps memreadengine could do the labeling\n   Reg#(Bit#(MemOffsetSize)) countReg <- mkReg(0);\n   Reg#(UInt#(addrwidth)) cmdCountReg <- mkReg(0);\n   FIFOF#(Bit#(MemOffsetSize)) cmdFifo <- mkSizedBRAMFIFOF(cmd_buffer_depth);\n   FIFOF#(Vector#(N,Float)) read_data_buffer <- mkFIFOF;\n   \n   rule read_data;\n      let foo <- vs.readData.get;\n      read_data_buffer.enq(unpack(foo.data));\n   endrule\n   \n   method Action start(SGLId h, Bit#(MemOffsetSize) a, Bit#(MemOffsetSize) l, UInt#(32) tag);\n`ifdef TAGGED_TOKENS\n      tagFifo.enq(tag);\n`endif\n      let cmd = MemRequest{sglId:h, offset:a<<ashift, burstLen:truncate(l<<ashift), tag:id};\n      vs.readReq.put(cmd); //start(h,a,l);\n      if(verbose) $display(\"mkRowSource.start %d %d\", cmd.offset, cmd.burstLen);\n      cmdFifo.enq(l);\n   endmethod\n   interface PipeOut pipe;\n      method Vector#(N,MmToken) first;\n\t Vector#(N,MmToken) rv;\n\t Vector#(N,Float) foo = read_data_buffer.first;\n`ifdef TAGGED_TOKENS\n\t for(Integer i = 0; i < valueOf(N); i=i+1)\n\t    rv[i] = MmToken{row:row+fromInteger(i), col:tagFifo.first, v:foo[i], first:False, last:False};\n`else\n\t for(Integer i = 0; i < valueOf(N); i=i+1)\n\t    rv[i] = MmToken{v:foo[i], first:False, last:False};\n`endif\n\t if (cmdCountReg == 0)  \n\t    for(Integer i = 0; i < valueOf(N); i=i+1)\n\t       rv[i].first = True;\n\n\t if (cmdCountReg+1 == numRows)\n\t    for(Integer i = 0; i < valueOf(N); i=i+1)\n\t       rv[i].last = True;\n\t return rv;\n      endmethod\n      method Action deq;\n\t if(verbose) $display(\"mkRowSource.deq %d %d\", countReg+1==cmdFifo.first, cmdCountReg+1==numRows);\n\t read_data_buffer.deq;\n\t if(countReg+1==cmdFifo.first) begin\n\t    countReg <= 0;\n\t    cmdFifo.deq;\n\t    if (cmdCountReg+1 == numRows)\n\t       cmdCountReg <= 0;\n\t    else\n\t       cmdCountReg <= cmdCountReg+1;\n`ifdef TAGGED_TOKENS\n\t    tagFifo.deq;\n\t    row <= 0;\n`endif      \n\t end\n\t else begin\n`ifdef TAGGED_TOKENS\n\t    row <= row+fromInteger(valueOf(N));\n`endif\n\t    countReg <= countReg+1;\n\t end\n      endmethod\n      method Bool notEmpty;\n`ifdef TAGGED_TOKENS\n\t return (tagFifo.notEmpty && vs.readServers[0].data.notEmpty);\n`else\n\t return (read_data_buffer.notEmpty);\n`endif\n      endmethod\n   endinterface\nendmodule: mkRowSource\n\nmodule mkRowColSink#(MemWriteServer#(TMul#(N,32)) vs, Bit#(MemTagSize) id) (RowColSink#(TMul#(N,32), Vector#(N,MmToken)))\n   provisos (Bits#(Vector#(N,Float),asz),\n      Div#(asz,8,abytes),\n      Log#(abytes,ashift),\n      Mul#(abytes, 8, asz)\n      );\n   let ashift = valueOf(ashift);\n   let write_data_buffer <- mkFIFOF;\n   rule write_data;\n      let foo <- toGet(write_data_buffer).get;\n      vs.writeData.put(foo);\n   endrule\n   function Float tokenValue(MmToken v) = v.v;\n   method Action start(SGLId h, Bit#(MemOffsetSize) a, Bit#(MemOffsetSize) l);\n      let cmd = MemRequest{sglId:h, offset:a<<ashift, burstLen:truncate(l<<ashift), tag:id};\n      vs.writeReq.put(cmd);\n   endmethod\n   interface PipeIn pipe;\n      method Action enq(Vector#(N,MmToken) v);\n\t write_data_buffer.enq(MemData{data:pack(map(tokenValue,v)),tag:id,last:True});\n      endmethod\n      method Bool notFull = write_data_buffer.notFull;\n   endinterface\n   method ActionValue#(Bool) finish();\n      let rv <- vs.writeDone.get;\n      return True;\n   endmethod\nendmodule\n   \n// row major layout\ninterface DmaMatrixMultiplyIfc#(numeric type addrwidth, numeric type dsz);\n   method Action start(SGLId pointerA, UInt#(addrwidth) numRowsA, UInt#(addrwidth) numColumnsA,\n\t\t       SGLId pointerB, UInt#(addrwidth) numRowsB, UInt#(addrwidth) numColumnsB,\n\t\t       SGLId pointerC,\n\t\t       UInt#(addrwidth) numRowsA_x_numColumnsA, UInt#(addrwidth) numColumnsA_x_J,\n\t\t       UInt#(addrwidth) numRowsA_x_numColumnsB, UInt#(addrwidth) numColumnsB_x_K,\n\t\t       UInt#(addrwidth) numColumnsA_x_numColumnsB,    UInt#(addrwidth) numRowsB_x_J);\n   method ActionValue#(Bool) finish();\n   interface DmaMatrixMultiplyDebug debug;\nendinterface\n\ntypedef enum {\n   Idle, Ready, Running, Done\n   } MMState deriving (Bits, Eq);\n\n/*!\n * Multiplies two matrices A and B and writes the result to memory.\n * Simultaneously fetches J rows from A and K rows from B. Each cycle, \n * it can fetch N elements from either matrix.\n *\n * Just considering memory bandwidth, every J+K cycles it is ready to \n * perform J*K*N multiply accumulates.\n *\n */\nmodule  mkDmaMatrixMultiply#(MemReadServer#(TMul#(N,32)) sA,\n\t\t\t     MemReadServer#(TMul#(N,32)) sB,\n\t\t\t     MemWriteServer#(TMul#(N,32))ss,\n\t\t\t     HostInterface host\n\t\t\t     )(DmaMatrixMultiplyIfc#(addrwidth, dsz))\n   provisos (  Mul#(N,n__,K) // K must be an integer multiple of N\n\t     , Mul#(N,m__,J) // J must be an integer multiple of N\n             , Add#(1,o__,J)\n\t     , Log#(N,nshift)\n\t     , FShow#(Float)\n\t     , Arith#(Float)\n\t     , Bits#(Vector#(N, Float), dsz)\n\t     , Bits#(MatrixDescriptor#(UInt#(addrwidth)), mdsz)\n\t     , Bits#(Tuple2#(UInt#(addrwidth), UInt#(addrwidth)), tplsz)\n\t     , Add#(b__, 20, addrwidth)\n\t     , Add#(a__, addrwidth, MemOffsetSize)\n\t     , Add#(c__, addrwidth, 32)\n      );\n\n   let n = valueOf(N);\n   let jj = valueOf(J);\n   let kk = valueOf(K);\n   let tt = valueOf(T);\n   let nshift = valueOf(nshift);\n   Bool verbose = False;\n\n   let defaultClock <- exposeCurrentClock();\n   let defaultReset <- exposeCurrentReset();\n\n   let derivedClock = host.derivedClock;\n   let currentReset <- exposeCurrentReset;\n   let derivedReset <- mkAsyncReset(2, currentReset, derivedClock);\n\n   Reg#(UInt#(32)) cycles <- mkReg(0);\n   Reg#(MatrixDescriptor#(UInt#(addrwidth))) descriptorC <- mkReg(unpack(0));\n   Reg#(MatrixDescriptor#(UInt#(addrwidth))) descriptorA <- mkReg(unpack(0));\n   Reg#(MatrixDescriptor#(UInt#(addrwidth))) descriptorB <- mkReg(unpack(0));\n   Reg#(UInt#(addrwidth)) sinkCnt <- mkReg(0);\n   \n   Reg#(UInt#(addrwidth)) numRowsAReg <- mkReg(0);\n   Reg#(UInt#(addrwidth)) numRowsBReg <- mkReg(0);\n   RowColSource#(TMul#(N,32), Vector#(N,MmToken)) sourceA <- mkRowSource(sA, numRowsAReg, 0);\n   RowColSource#(TMul#(N,32), Vector#(N,MmToken)) sourceB <- mkRowSource(sB, numRowsBReg, 1);\n   RowColSink#(TMul#(N,32),   Vector#(N,MmToken))    sink <- mkRowColSink(ss, 0);\n\n   PipeOut#(MmToken) aPipe <- mkFunnelGB1(defaultClock, defaultReset, derivedClock, derivedReset, sourceA.pipe);\n   UnFunnelPipe#(1,J,MmToken,1) aPipes <- mkUnFunnelPipesPipelinedRR(clocked_by derivedClock, reset_by derivedReset, cons(aPipe,nil), 1);\n   PipeOut#(MmToken) bFunnel <- mkFunnelGB1(defaultClock, defaultReset, derivedClock, derivedReset, sourceB.pipe);\n   Vector#(J, PipeOut#(MmToken)) bPipes <- mkForkVector(bFunnel, clocked_by derivedClock, reset_by derivedReset);\n   \n   rule countCycles;\n      cycles <= cycles+1;\n   endrule\n\n   UInt#(TAdd#(TLog#(K),1)) repetitions = fromInteger(valueOf(K));\n   Vector#(J, PipeOut#(MmToken)) aRepeaters <- mapM(mkRepeat(repetitions), aPipes, clocked_by derivedClock, reset_by derivedReset);\n\n   Vector#(T, MmTile) mmTiles <- mapM(mkMmTile(defaultClock, defaultReset), map(fromInteger,genVector), clocked_by derivedClock, reset_by derivedReset);\n   Vector#(J, PipeOut#(Vector#(N,MmToken))) fxpipes;\n   for (Integer t = 0; t < valueOf(T); t = t+1) begin\n      for (Integer i = 0; i < valueof(RowsPerTile); i = i+1) begin\n   \t let j = t*valueOf(RowsPerTile) + i;\n   \t mkConnection(toGet(aRepeaters[j]), mmTiles[t].aInputs[i], clocked_by derivedClock, reset_by derivedReset);\n   \t mkConnection(toGet(bPipes[j]), mmTiles[t].bInputs[i], clocked_by derivedClock, reset_by derivedReset);\n   \t fxpipes[j] = mmTiles[t].fxPipes[i];\n      end\n   end\n   FunnelPipe#(1,J,Vector#(N,MmToken),2) sinks <- mkFunnelPipesPipelinedRR(fxpipes,kk/valueOf(N));\n   mkConnection(sinks[0],sink.pipe);\n\n   XYZIteratorIfc#(UInt#(addrwidth)) offsetpipeC <- mkXYZIterator(RangeC);\n   XYZIteratorIfc#(UInt#(addrwidth)) offsetpipeA <- mkXYZIterator(RangeA);\n   XYZIteratorIfc#(UInt#(addrwidth)) offsetpipeB <- mkXYZIterator(RangeB);\n   \n   Reg#(UInt#(32)) lastStartA <- mkReg(0);\n   Reg#(UInt#(32)) lastStartB <- mkReg(0);\n   Reg#(UInt#(32)) lastStartC <- mkReg(0);\n      \n   Reg#(Bool) running <- mkReg(False);\n   FIFOF#(Bool) doneFifo <- mkFIFOF();\n   \n   rule startSourceB;\n      match { .startBBase, .startBOffset } <- toGet(offsetpipeB.pipe).get();\n      let startB = startBBase + startBOffset;\n      lastStartB <= cycles;\n      let interval = cycles-lastStartB;\n      if ( verbose) $display($format(fshow(interval)+fshow(\" startB=\")+fshow(startB)));\n      sourceB.start(descriptorB.sglId, pack(extend(startB>>nshift)), fromInteger(kk)>>nshift, 0);\n   endrule\n   \n   rule startSourceA;\n      match { .startABase, .startAOffset } <- toGet(offsetpipeA.pipe).get();\n      let startA = startABase + startAOffset;\n      lastStartA <= cycles;\n      let interval = cycles-lastStartA;\n      if ( verbose) $display($format(fshow(interval)+fshow(\" startA=\")+fshow(startA)));\n      sourceA.start(descriptorA.sglId, pack(extend(startA>>nshift)), fromInteger(jj)>>nshift, 1);      \n   endrule\n   \n   rule startSink;\n      match { .startCBase, .offsetC } <- toGet(offsetpipeC.pipe).get();\n      let startC = startCBase + offsetC;\n      lastStartC <= cycles;\n      let interval = cycles-lastStartC;\n      if ( verbose) $display($format(fshow(interval)+fshow(\" startC=\")+fshow(startC)));\n      sink.start(descriptorC.sglId, pack(extend(startC>>nshift)), fromInteger(kk)>>nshift);\n   endrule\n\n   rule finishSink;\n      let b <- sink.finish();\n      let c = sinkCnt-1;\n      sinkCnt <= c;\n      if (c == 0) begin\n\t if (verbose) $display(\"finishSink %d\", c);\n\t running <= False;\n\t doneFifo.enq(?);\n      end\n   endrule\n\n   function PipeOut#(Bit#(32)) mmTileMacCount(MmTile mmtile); return mmtile.debug.macCount; endfunction\n   Vector#(T, PipeOut#(Vector#(2,Bit#(32)))) macCountPipes <- mapM(mkUnfunnelGB(defaultClock, defaultReset, derivedClock, derivedReset),\n\t\t\t\t\t\t\t\t   map(mapPipe(replicate),\n\t\t\t\t\t\t\t\t       map(mmTileMacCount, mmTiles)));\n   PipeOut#(Bit#(32)) macCountPipe <- mkReducePipes(uncurry(add), map(mapPipe(head),macCountPipes));\n   Reg#(Bit#(32)) macCountReg <- mkReg(0);\n   rule updateMacCount;\n      let mc <- toGet(macCountPipe).get();\n      macCountReg <= mc;\n   endrule\n\n   function Bool pipeNotEmpty(RowColSource#(asz, a) vs); return vs.pipe.notEmpty(); endfunction\n\n   method Action start(SGLId pointerA, UInt#(addrwidth) numRowsA, UInt#(addrwidth) numColumnsA,\n\t\t       SGLId pointerB, UInt#(addrwidth) numRowsB, UInt#(addrwidth) numColumnsB,\n\t\t       SGLId pointerC,\n\t\t       UInt#(addrwidth) numRowsA_x_numColumnsA,UInt#(addrwidth) numColumnsA_x_J,\n\t\t       UInt#(addrwidth) numRowsA_x_numColumnsB,UInt#(addrwidth) numColumnsB_x_J,\n\t\t       UInt#(addrwidth) numColumnsA_x_numColumnsB,UInt#(addrwidth) numRowsB_x_numColumnsB\n\t\t       ) if (!running);\n\n      XYZIteratorConfig#(UInt#(addrwidth)) offsetcfgA = XYZIteratorConfig {xbase: 0, xlimit: numRowsA_x_numColumnsA, xstep: numColumnsA,\n\t\t\t\t\t\t\t\t     ybase: 0, ylimit: numColumnsB,            ystep: fromInteger(kk),\n\t\t\t\t\t\t\t\t     zbase: 0, zlimit: numColumnsA,            zstep: fromInteger(jj)};\n\n      XYZIteratorConfig#(UInt#(addrwidth)) offsetcfgB = XYZIteratorConfig {xbase: 0, xlimit: numRowsB_x_numColumnsB, xstep: numColumnsB,\n\t\t\t\t\t\t\t\t     ybase: 0, ylimit: numColumnsB,            ystep: fromInteger(kk),\n\t\t\t\t\t\t\t\t     zbase: 0, zlimit: numColumnsA,            zstep: fromInteger(jj)};\n\n      XYZIteratorConfig#(UInt#(addrwidth)) offsetcfgC = XYZIteratorConfig {xbase: 0, xlimit: numColumnsB_x_J,           xstep: numColumnsB,\n\t\t\t\t\t\t\t\t     ybase: 0, ylimit: numColumnsB,               ystep: fromInteger(kk),\n\t\t\t\t\t\t\t\t     zbase: 0, zlimit: numColumnsA_x_numColumnsB, zstep: numColumnsB_x_J };\n\n      descriptorA <= MatrixDescriptor { sglId: pointerA, base: 0, numRows: numRowsA,    numColumns: numColumnsA};\n      descriptorB <= MatrixDescriptor { sglId: pointerB, base: 0, numRows: numRowsB,    numColumns: numColumnsB};\n      descriptorC <= MatrixDescriptor { sglId: pointerC, base: 0, numRows: numColumnsA, numColumns: numColumnsB};\n      sinkCnt <= numColumnsA_x_numColumnsB/fromInteger(kk);\n      numRowsBReg <= numRowsB;\n      numRowsAReg <= numRowsA;\n      running <= True;\n\n      if (verbose) $display(\"mm pointerA=%d pointerB=%d pointerC=%d\", pointerA, pointerB, pointerC);\n      if (verbose) $display(\"mm.start ra=%d ca=%d rb=%d cb=%d\", numRowsA, numColumnsA, numRowsB, numColumnsB);\n      if (verbose) $display($format(fshow(\"offsetcfgA \")+fshow(offsetcfgA)));\n      if (verbose) $display($format(fshow(\"offsetcfgB \")+fshow(offsetcfgB)));\n      if (verbose) $display($format(fshow(\"offsetcfgC \")+fshow(offsetcfgC)));\n      offsetpipeA.start(offsetcfgA);\n      offsetpipeC.start(offsetcfgC);\n      offsetpipeB.start(offsetcfgB);\n      \n      //$dumpfile(\"test.vcd\");\n      //$dumpvars();\n   endmethod\n   method ActionValue#(Bool) finish();\n      if (verbose) $display(\"mm.finish()\");\n      doneFifo.deq();\n      return True;\n   endmethod\n   interface DmaMatrixMultiplyDebug debug;\n      method Bit#(32) macCount(); return macCountReg; endmethod\n    endinterface\nendmodule : mkDmaMatrixMultiply\n\ninterface DramMatrixMultiply#(numeric type n, numeric type dmasz);\n   interface Vector#(2, MemReadClient#(dmasz)) readClients;\n   interface Vector#(2, MemWriteClient#(dmasz)) writeClients;\n   method Action start(SGLId pointerA, UInt#(MMSize) numRowsA, UInt#(MMSize) numColumnsA,\n\t\t       SGLId pointerB, UInt#(MMSize) numRowsB, UInt#(MMSize) numColumnsB,\n\t\t       SGLId pointerC,\n\t\t       UInt#(MMSize) numRowsA_x_numColumnsA, UInt#(MMSize) numColumnsA_x_J,\n\t\t       UInt#(MMSize) numRowsA_x_numColumnsB, UInt#(MMSize) numColumnsB_x_J,\n\t\t       UInt#(MMSize) numColumnsA_x_numColumnsB, UInt#(MMSize) numRowsB_x_J);\n   method ActionValue#(Bool) finish();\n   interface DmaMatrixMultiplyDebug debug;\nendinterface\n      \nmodule  mkDramMatrixMultiply#(HostInterface host)(DramMatrixMultiply#(N,TMul#(N,32)));\n\n   MemWriterBuff#(TMul#(N,32),128)    writer <- mkMemWriterBuff;\n   MemReaderBuff#(TMul#(N,32),256) rowReader <- mkMemReaderBuff;\n   MemReaderBuff#(TMul#(N,32),256) colReader <- mkMemReaderBuff;\n   MemWriter#(TMul#(32,N))       bogusWriter <- mkMemWriter;\n   \n   DmaMatrixMultiplyIfc#(MMSize,DmaSz) dmaMMF <- mkDmaMatrixMultiply(rowReader.readServer, colReader.readServer, writer.writeServer, host);\n   interface Vector readClients  = cons(rowReader.readClient, cons(colReader.readClient,    nil));\n   interface Vector writeClients = cons(writer.writeClient,   cons(bogusWriter.writeClient, nil));\n   method start = dmaMMF.start;\n   method finish = dmaMMF.finish;\n   interface DmaMatrixMultiplyDebug debug = dmaMMF.debug;\nendmodule\n   \ninterface MatrixTN#(numeric type n);\n   interface MmRequestTN mmRequest;\n   interface TimerRequest timerRequest;\n   interface Vector#(2, MemReadClient#(TMul#(32,n)))  readClients;\n   interface Vector#(2, MemWriteClient#(TMul#(32,n))) writeClients;\nendinterface\n\ninterface MmTNInternal#(numeric type n);\n   interface MmRequestTN mmRequest;\n   interface Vector#(2, MemReadClient#(TMul#(32,n)))  readClients;\n   interface Vector#(2, MemWriteClient#(TMul#(32,n))) writeClients;\n   method ActionValue#(Bit#(64)) mmfDone(); \n   method ActionValue#(Bit#(32)) debugDone(); \nendinterface\n\nmodule  mkMmTNInternal#(HostInterface host)(MmTNInternal#(N))\n   provisos (Add#(1,a__,N),\n\t     Add#(N,0,n),\n\t     Mul#(N,32,DmaSz)\n\t     );\n   \n   let verbose = False;\n   let n = valueOf(n);\n   DramMatrixMultiply#(N, TMul#(N,32)) dmaMMF <- mkDramMatrixMultiply(host);\n   FIFO#(void) mcReqs <- mkFIFO;\n\n   Reg#(Bit#(64)) mmfCycles <- mkReg(0);\n   rule countCycles;\n      mmfCycles <= mmfCycles + 1;\n   endrule\n\n   method ActionValue#(Bit#(64)) mmfDone;\n      let d <- dmaMMF.finish();\n      if(verbose) $display(\"mkMmTN.mmfDone\");\n      return mmfCycles;\n   endmethod\n\n   method ActionValue#(Bit#(32)) debugDone;\n      mcReqs.deq;\n      return dmaMMF.debug.macCount();\n   endmethod\n   \n   interface MmRequestTN mmRequest;\n      method Action mmf(Bit#(32) h1, Bit#(32) r1, Bit#(32) c1,\n\t\t\tBit#(32) h2, Bit#(32) r2, Bit#(32) c2,\n\t\t\tBit#(32) h3,\n\t\t\tBit#(32) r1_x_c1, Bit#(32) c1_x_j,\n\t\t\tBit#(32) r1_x_c2, Bit#(32) c2_x_j,\n\t\t\tBit#(32) c1_x_c2, Bit#(32) r2_x_c2);\n\t if(verbose) $display(\"mkMmTN.start\");\n\t check_dimension(r1);\n\t check_dimension(c1);\n\t check_dimension(r2);\n\t check_dimension(c2);\n\t dmaMMF.start(h1, unpack(truncate(r1)), unpack(truncate(c1)),\n\t\t      h2, unpack(truncate(r2)), unpack(truncate(c2)),\n\t\t      h3,\n\t\t      unpack(truncate(r1_x_c1)), unpack(truncate(c1_x_j)),\n\t\t      unpack(truncate(r1_x_c2)), unpack(truncate(c2_x_j)),\n\t\t      unpack(truncate(c1_x_c2)), unpack(truncate(r2_x_c2)));\n\t mmfCycles <= 0;\n      endmethod\n      method Action debug();\n\t mcReqs.enq(?);\n      endmethod\n   endinterface\n   interface Vector readClients = dmaMMF.readClients;\n   interface Vector writeClients =  dmaMMF.writeClients;\nendmodule\n\nmodule  mkMatrixTN#(HostInterface host, MmIndication ind, TimerIndication timerInd)(MatrixTN#(N))\n   provisos (Add#(1,a__,N),\n\t     Add#(N,0,n),\n\t     Mul#(N,32,DmaSz)\n\t     );\n   \n   MmTNInternal#(N) mmTnInt <- mkMmTNInternal(host);\n   FIFOF#(Bool) busyFifo <- mkFIFOF();\n   FIFOF#(Bool) timerRunning <- mkFIFOF();\n   Reg#(Bit#(64)) cycleCount <- mkReg(0);\n   Reg#(Bit#(64)) idleCount <- mkReg(0);\n\n   rule countCycles if (timerRunning.notEmpty());\n      cycleCount <= cycleCount + 1;\n      if (!busyFifo.notEmpty())\n\t idleCount <= idleCount + 1;\n   endrule\n\n   rule mmfDone;\n      let d <- mmTnInt.mmfDone;\n      busyFifo.deq();\n      ind.mmfDone(d);\n   endrule\n   \n   rule debugDone;\n      let d <- mmTnInt.debugDone;\n      ind.debug(d);\n   endrule\n   \n   interface TimerRequest timerRequest;\n      method Action startTimer() if (!timerRunning.notEmpty());\n\t cycleCount <= 0;\n\t idleCount <= 0;\n\t timerRunning.enq(True);\n      endmethod\n      method Action stopTimer();\n\t timerRunning.deq();\n\t timerInd.elapsedCycles(cycleCount, idleCount);\n      endmethod\n   endinterface\n   interface MmRequestTN mmRequest;\n      method Action mmf(Bit#(32) h1, Bit#(32) r1, Bit#(32) c1,\n\t\t\tBit#(32) h2, Bit#(32) r2, Bit#(32) c2,\n\t\t\tBit#(32) h3,\n\t\t\tBit#(32) r1_x_c1, Bit#(32) c1_x_j,\n\t\t\tBit#(32) r1_x_c2, Bit#(32) c2_x_j,\n\t\t\tBit#(32) c1_x_c2, Bit#(32) r2_x_c2);\n\t mmTnInt.mmRequest.mmf(h1,r1,c1,\n\t\t\t       h2,r2,c2,\n\t\t\t       h3,\n\t\t\t       r1_x_c1, c1_x_j,\n\t\t\t       r1_x_c2, c2_x_j,\n\t\t\t       c1_x_c2, r2_x_c2);\n\t busyFifo.enq(True);\n      endmethod\n      method Action debug = mmTnInt.mmRequest.debug;\n   endinterface\n   interface Vector readClients = mmTnInt.readClients;\n   interface Vector writeClients =  mmTnInt.writeClients;\nendmodule\n\n"
  },
  {
    "path": "lib/matmul/cpp/cuda.cpp",
    "content": "\n// Copyright (c) 2014 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\n\n#include <stdio.h>\n#include <sys/time.h>\n#include <opencv2/gpu/gpu.hpp>\n\n\nvoid cuda_test()\n{\n\n  struct timeval tv0;\n  struct timeval tv1;\n  struct timezone tz; \n\n  int A = 100;\n  int B = 100;\n\n  cv::Mat src1(A,B,CV_32F);\n  cv::Mat src2(A,B,CV_32F);\n  cv::Mat src3(A,B,CV_32F);\n  cv::Mat dst(A,B,CV_32F);\n\n  cv::gpu::GpuMat d_src1, d_src2, d_src3, d_dst;\n  \n  for(int a = 0; a < A; a++){\n    for(int b = 0; b < B; b++){\n      src1.at<float>(a,b) = a*b;\n      src2.at<float>(a,b) = a*b;\n      src3.at<float>(a,b) = 0;\n      dst.at<float>(a,b)  = 0;\n    }\n  }\n\n  cv::gemm(src1, src2, 1.0, src3, 1.0, dst);\n\n  assert(!gettimeofday(&tv0, &tz));\n  cv::gemm(src1, src2, 1.0, src3, 1.0, dst);\n  assert(!gettimeofday(&tv1, &tz));\n\n  fprintf(stderr, \"cpu time: %d (usec)\\n\", tv1.tv_usec-tv0.tv_usec);\n\n  d_src1.upload(src1);\n  d_src2.upload(src2);\n  d_src3.upload(src3);\n  \n  cv::gpu::gemm(d_src1, d_src2, 1.0, d_src3, 1.0, d_dst);\n  \n  assert(!gettimeofday(&tv0, &tz));\n  cv::gpu::gemm(d_src1, d_src2, 1.0, d_src3, 1.0, d_dst);\n  assert(!gettimeofday(&tv1, &tz));\n\n  fprintf(stderr, \"gpu time: %d (usec)\\n\", tv1.tv_usec-tv0.tv_usec);\n}\n\nlong int cuda_mm(cv::Mat& src1, cv::Mat& src2, cv::Mat& dst)\n{\n\n  struct timeval tv0;\n  struct timeval tv1;\n  struct timezone tz; \n\n  cv::Mat src3 = cv::Mat::zeros(src1.rows,src2.cols,CV_32F);\n  cv::gpu::GpuMat d_src1, d_src2, d_src3, d_dst;\n  \n  d_src1.upload(src1);\n  d_src2.upload(src2);\n  d_src3.upload(src3);\n  d_dst.upload(dst);\n  \n  cv::gpu::gemm(d_src1, d_src2, 1.0, d_src3, 1.0, d_dst);\n  \n  assert(!gettimeofday(&tv0, &tz));\n  cv::gpu::gemm(d_src1, d_src2, 1.0, d_src3, 1.0, d_dst);\n  assert(!gettimeofday(&tv1, &tz));\n\n  d_dst.download(dst);\n\n  long int rv = tv1.tv_usec-tv0.tv_usec;\n  fprintf(stderr, \"gpu time: %d (usec)\\n\", rv);\n  return rv;\n}\n\n\n"
  },
  {
    "path": "lib/matmul/cpp/portalmat.cpp",
    "content": "\n// Copyright (c) 2014 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n#include \"dmaManager.h\"\n#include \"portalmat.h\"\n\nPortalMatAllocator *matAllocator = 0;\nsem_t mul_sem;\n\nvoid PortalMatAllocator::allocate(int dims, const int* sizes, int type, int*& refcount,\n\t\t\t\t  uchar*& datastart, uchar*& data, size_t* step)\n{\n  size_t arraysize = step[0]*sizes[0];\n  size_t totalsize = cv::alignSize(arraysize, 4096);\n  int arraynum = numarrays++;\n  int fd = portalAlloc(totalsize, 0);\n  struct arrayInfo *info = &arrayInfo[arraynum];\n  info->fd = fd;\n  info->refcount = 1;\n  info->totalsize = totalsize;\n  info->data = (uchar*)portalMmap(fd, totalsize);\n  info->ref = 0;\n\n  data = datastart = (uchar*)info->data;\n  refcount = (int*)info;\n  fprintf(stderr, \"PortalMatAllocator::allocate   arraynum=%d arraysize=%ld totalsize=%ld datastart=%p refcount=%p end of data=%p\\n\",\n\t  arraynum, (long)arraysize, (long)totalsize, datastart, refcount, datastart+totalsize);\n}\n\nvoid PortalMatAllocator::deallocate(int* refcount, uchar* datastart, uchar* data)\n{\n  struct arrayInfo *info = (struct arrayInfo *)refcount;\n  size_t totalsize = info->totalsize;\n  fprintf(stderr, \"PortalMatAllocator::deallocate datastart=%p size=%ld ref=%d\\n\",\n\t  datastart, (long)totalsize, info->ref);\n  munmap(datastart, totalsize);\n  dma->dereference(info->ref);\n  close(info->fd);\n  memset(info, 0, sizeof(struct arrayInfo));\n}\n\nint PortalMatAllocator::reference(int* refcount, uchar* datastart, uchar* data)\n{\n  struct arrayInfo *info = (struct arrayInfo *)refcount;\n  int ref = info->ref;\n  if (!ref) {\n    ref = dma->reference(info->fd);\n    info->ref = ref;\n  }\n  //fprintf(stderr, \"PortalMatAllocator::reference returning %d\\n\", ref);\n  return ref;\n}\n\nvoid PortalMatAllocator::cacheFlushInvalidate(int* refcount, uchar* datastart, uchar* data)\n{\n  struct arrayInfo *info = (struct arrayInfo *)refcount;\n  portalCacheFlush(info->fd, datastart, info->totalsize, 1);\n}\n\nPortalMat::PortalMat()\n    : cv::Mat() \n{\n    allocator = matAllocator;\n    fprintf(stderr, \"PortalMat::PortalMat() this=%p datastart=%p\\n\", this, datastart);\n}\n\nPortalMat::PortalMat(int rows, int cols, int type)\n    : cv::Mat()\n{\n    allocator = matAllocator;\n    create(rows, cols, type);\n    fprintf(stderr, \"PortalMat::PortalMat(rows,cols) this=%p datastart=%p\\n\", this, datastart);\n}\n\nPortalMat::PortalMat(int rows, int cols, int type, const cv::Scalar& s)\n    : cv::Mat()\n{\n    allocator = matAllocator;\n    create(rows, cols, type);\n    *(cv::Mat*)this = s;\n    fprintf(stderr, \"PortalMat::PortalMat(Scalar&) this=%p datastart=%p\\n\", this, datastart);\n}\n\nPortalMat::PortalMat(const PortalMat &m)\n  : Mat()\n{\n    allocator = matAllocator;\n    create(m.rows, m.cols, CV_32F);\n    //*(cv::Mat*)this = m;\n    for (int i = 0; i < m.rows; i++)\n\tfor (int j = 0; j < m.cols; j++) {\n\t    this->at<float>(i,j) = m.at<float>(i,j);\n\t}\n    fprintf(stderr, \"PortalMat::PortalMat(PortalMat&) this=%p datastart=%p\\n\", this, datastart);\n}\n\nPortalMat::PortalMat(const cv::Mat &m)\n    : Mat()\n{\n    allocator = matAllocator;\n    create(m.rows, m.cols, CV_32F);\n    //*(cv::Mat*)this = m;\n    for (int i = 0; i < m.rows; i++)\n\tfor (int j = 0; j < m.cols; j++) {\n\t    this->at<float>(i,j) = m.at<float>(i,j);\n\t}\n    fprintf(stderr, \"PortalMat::PortalMat(Mat&) this=%p datastart=%p\\n\", this, datastart);\n}\n\nPortalMat::~PortalMat() {}\n\nPortalMat& PortalMat::operator = (const cv::MatExpr& expr)\n{\n    *(cv::Mat*)this = expr;\n    fprintf(stderr, \"PortalMat::operator=(MatExpr&) this=%p datastart=%p\\n\", this, datastart);\n    return *this;\n}\n\nPortalMat& PortalMat::operator = (const cv::Mat& o)\n{\n    *(cv::Mat*)this = o;\n    fprintf(stderr, \"PortalMat::operator=(Mat&) this=%p datastart=%p\\n\", this, datastart);\n    return *this;\n}\n\nint PortalMat::reference()\n{\n    int ref = 0;\n    //fprintf(stderr, \"PortalMat::reference this=%p datastart=%p\\n\", this, datastart);\n    ref = matAllocator->reference(refcount, datastart, data);\n    return ref;\n}\n\nvoid PortalMat::cacheFlushInvalidate()\n{\n    matAllocator->cacheFlushInvalidate(refcount, datastart, data);\n}\n\nbool PortalMat::copy(cv::Mat &other)\n{\n    create(other.rows, other.cols, CV_32F);\n    for (int i = 0; i < rows; i++) {\n\tfor (int j = 0; j < cols; j++) {\n\t    at<float>(i, j) = other.at<float>(i, j);\n\t}\n    }\n    return true;\n}\n\nbool PortalMat::copy(cv::MatExpr other)\n{\n    cv::Mat m(other);\n    create(m.rows, m.cols, CV_32F);\n    for (int i = 0; i < rows; i++) {\n\tfor (int j = 0; j < cols; j++) {\n\t    at<float>(i, j) = m.at<float>(i, j);\n\t}\n    }\n    return true;\n}\n\nbool PortalMat::transpose(cv::Mat &other)\n{\n    create(other.cols, other.rows, CV_32F);\n    for (int i = 0; i < rows; i++) {\n\tfor (int j = 0; j < cols; j++) {\n\t    at<float>(i, j) = other.at<float>(j, i);\n\t}\n    }\n    return true;\n}\n\nbool PortalMat::compare(Mat &refMat, const char *file, int line, float epsilon, Mat *pm, bool verbose)\n{\n    if (0)\n\tfprintf(stderr, \"PortalMat.compare rows=%d cols=%d refMat.rows=%d refMat.cols=%d\\n\",\n\t\trows, cols, refMat.rows, refMat.cols);\n\n    if (rows != refMat.rows || cols != refMat.cols) {\n\tfprintf(stderr, \"PortalMat.compare dimension mismatch rows=%d cols=%d refMat.rows=%d refMat.cols=%d\\n\",\n\t\trows, cols, refMat.rows, refMat.cols);\n\treturn false;\n    }\n    bool rv = true;\n    bool first = true;\n    for (int i = 0; i < rows; i++) {\n\tfor (int j = 0; j < cols; j++) {\n\t    float v = at<float>(i, j);\n\t    float refVal = refMat.at<float>(i, j);\n\t    float relativeError = fabs((v - refVal) / refVal);\n\t    if (relativeError > epsilon) {\n\t      if (verbose || first) {\n\t\tif (file)\n\t\t  fprintf(stderr, \"%s:%d: \", file, line);\n\t\tfprintf(stderr, \"mismatch[%d,%d] expected %f got %f error=%f)\", i, j, refVal, v, relativeError);\n\t\tif (pm) {\n\t\t  float pmv = pm->at<float>(i,j);\n\t\t  fprintf(stderr, \" pm[%d,%d]=%f %08x\", i, j, pmv, *(int*)&pmv);\n\t\t}\n\t\tfprintf(stderr, \"\\n\");\n\t      }\n\t      rv = false;\n\t      first = false;\n\t    }\n\t}\n    }\n    \n    if (!rv) {\n      if (file)\n\tfprintf(stderr, \"%s:%d: \", file, line);\n      fprintf(stderr, \"PortalMat::compare detected a mismatch\\n\");\n    }\n    return rv;\n}\n\n\nvoid PortalMat::naive_mul(cv::Mat &a, cv::Mat &b, FILE *f)\n{\n\n  fprintf(stderr, \"a:(%d x %d) b:(%d x %d)\", a.rows, a.cols, b.rows, b.cols);\n  assert(a.cols == b.rows);\n  create(a.rows, b.cols, CV_32F);\n  for (int i = 0; i < rows; i++) {\n    for (int j = 0; j < cols; j++) {\n      double c = 0.0;\n#ifndef __FOO\n      bool last = (i==(rows-1) && j==(cols-1));\n      if(last) fprintf(f, \"c = 0.0;\\n\");\n      for(int l = 0; l < a.cols; l++) {\n\tdouble x = (double)a.at<float>(i,l);\n\tdouble y = (double)b.at<float>(l,j);\n\tdouble p = x*y;\n\tif(last){\n\t  fprintf(f, \"assert(c==%f);\\n\", c);\n\t}\n      \tc = c + p;\n\tif(last){\n\t  fprintf(f, \"p = %f*%f;\\n\", x, y);\n\t  fprintf(f, \"assert(p==%f);\\n\", p);\n\t  fprintf(f, \"c = c + p;\\n\");\n\t  fprintf(f, \"disp([c, %f])\\n\", c);\n\t  fprintf(f, \"assert(c==%f)\\n\", c);\n\t}\n      }\n      at<float>(i, j) = (float)c;\n      if (last) fprintf(f, \"rez = %f;\\n\", c);\n#else\n      int K = 2;\n      int gatherSz = 8/K;\n      float c_ij[gatherSz];\n      for(int k = 0; k < gatherSz; k++)\n\tc_ij[k] = 0.0;\n      for(int l = 0; l < a.cols; l+=gatherSz)\n\tfor(int k = 0; k < gatherSz; k++)\n\t  c_ij[k] += a.at<float>(i,l+k) * b.at<float>(l+k,j);\n      for(int k = 0; k < gatherSz; k++)\n\tc += c_ij[k];\n      at<float>(i, j) = c;\n#endif\n    }\n  }\n}\n\n\n#ifdef MATRIX_NT\nvoid PortalMat::multf(PortalMat &a, PortalMat &b_transpose,  MmIndication *mmind)\n{\n    create(a.rows, b_transpose.rows, CV_32F);\n    cacheFlushInvalidate();\n    if (a.cols != b_transpose.cols) {\n\tfprintf(stderr, \"Mismatched matrices: a.rows=%d a.cols=%d b.rows=%d b.cols=%d\\n\", a.rows, a.cols, b_transpose.rows, b_transpose.cols);\n\treturn;\n    }\n    long aref = a.reference();\n    long bref = b_transpose.reference();\n    long cref = reference();\n    if (0)\n    fprintf(stderr, \"mult: ref=%d rows=%d cols=%d a.ref=%d a.rows=%d a.cols=%d b.ref=%d b.rows=%d b.cols=%d\\n\",\n\t    cref, rows, cols,\n\t    aref, a.rows, a.cols,\n\t    bref, b_transpose.rows, b_transpose.cols);\n    mmdevice->mmf(aref, a.rows, a.cols,\n\t\t  bref, b_transpose.rows, b_transpose.cols,\n\t\t  cref,\n\t\t  a.rows*a.cols, a.cols*J_VALUE,\n\t\t  b_transpose.rows*b_transpose.cols, b_transpose.cols*K_VALUE,\n\t\t  a.rows*b_transpose.rows, b_transpose.rows*J_VALUE);\n\n    sem_wait(&mul_sem);\n    if(mmind) {\n      int macs = a.rows*a.cols*b_transpose.rows;\n      if (0)\n\tfprintf(stderr, \"macs %d cycles %f lap_timer %f macs/cycle: %f\\n\", macs, (float)mmind->ccnt, (float)portalTimerLap(0), ((float)macs)/((float)mmind->ccnt));\n    }\n}\n\n\n#else\n#ifdef MATRIX_TN\nvoid PortalMat::multf(PortalMat &a_transpose, PortalMat &b,  MmIndication *mmind)\n{\n    create(a_transpose.cols, b.cols, CV_32F);\n    cacheFlushInvalidate();\n\n    if (a_transpose.rows != b.rows) {\n\tfprintf(stderr, \"Mismatched matrices: a.rows=%d a.cols=%d b.rows=%d b.cols=%d\\n\", a_transpose.rows, a_transpose.cols, b.rows, b.cols);\n\treturn;\n    }\n    long aref = a_transpose.reference();\n    long bref = b.reference();\n    long cref = reference();\n    fprintf(stderr, \"mult: ref=%ld rows=%d cols=%d a.ref=%ld a.rows=%d a.cols=%d b.ref=%ld b.rows=%d b.cols=%d\\n\",\n\t    cref, rows, cols,\n\t    aref, a_transpose.rows, a_transpose.cols,\n\t    bref, b.rows, b.cols);\n    mmdevice->mmf(aref, a_transpose.rows, a_transpose.cols,\n\t\t  bref, b.rows, b.cols,\n\t\t  cref,\n\t\t  a_transpose.rows*a_transpose.cols, a_transpose.cols*J_VALUE,\n\t\t  a_transpose.rows*b.cols, b.cols*J_VALUE,\n\t\t  a_transpose.cols*b.cols, b.rows*b.cols);\n    sem_wait(&mul_sem);\n    if(mmind) {\n      int macs = a_transpose.rows*a_transpose.cols*b.rows;\n      if (0)\n\tfprintf(stderr, \"macs %d cycles %f lap_timer %f macs/cycle: %f\\n\", macs, (float)mmind->ccnt, (float)portalTimerLap(0), ((float)macs)/((float)mmind->ccnt));\n    }\n}\n\n#endif\n#endif\n\n\ntemplate<typename T>\nvoid dumpMatF(const char *prefix, const char *fmt, const cv::Mat &mat, FILE *ofile)\n{\n  fprintf(ofile, \"%s: rows=%d cols=%d mat=%p\\n\", prefix, mat.rows, mat.cols, &mat);\n  for (int i = 0; i < mat.rows; i++) {\n    fprintf(ofile, \"%s: %03d:\", prefix, i);\n    for (int j = 0; j < mat.cols; j++) {\n      fprintf(ofile, \" \");\n      fprintf(ofile, fmt, mat.at<T>(i, j));\n    }\n    fprintf(ofile, \"\\n\");\n  }\n}\ntemplate void dumpMatF<float>(const char *prefix, const char *fmt, const cv::Mat &mat, FILE *ofile);\n\ntemplate<typename T>\nvoid dumpMatOctave(const char *name, const char *fmt, const cv::Mat &mat, FILE *ofile)\n{\n  fprintf(ofile, \"%s=[\", name);\n  for (int i = 0; i < mat.rows; i++) {\n    for (int j = 0; j < mat.cols; j++) {\n      fprintf(ofile, \" \");\n      fprintf(ofile, fmt, mat.at<T>(i, j));\n      if(j+1 < mat.cols)\n\tfprintf(ofile, \",\");\n    }\n    if(i+1 < mat.rows)\n      fprintf(ofile, \";\");\n  }\n  fprintf(ofile,\"];\\n\");\n}\ntemplate void dumpMatOctave<float>(const char *name, const char *fmt, const cv::Mat &mat, FILE *ofile);\n\ntemplate<typename T>\nvoid dumpMat(const char *prefix, const char *fmt, const cv::Mat &mat)\n{\n  dumpMatF<T>(prefix,fmt,mat,stderr);\n}\ntemplate void dumpMat<float>(const char *prefix, const char *fmt, const cv::Mat &mat);\ntemplate void dumpMat<int>(const char *prefix, const char *fmt, const cv::Mat &mat);\ntemplate void dumpMat<unsigned char>(const char *prefix, const char *fmt, const cv::Mat &mat);\n\nvoid dynamicRange(cv::Mat mat, int *pmin_exp, int *pmax_exp, float *pmin_val, float *pmax_val)\n{\n  int min_exp = 0;\n  int max_exp = 0;\n  float min_val = 0.0;\n  float max_val = 0.0;\n  \n  for (int i = 0; i < mat.rows; i++) {\n    for (int j = 0; j < mat.cols; j++) {\n      float f = mat.at<float>(i,j);\n      int exp = 0;\n      //float mantissa = frexpf(f, &exp);\n      min_val = std::min<float>(min_val, f);\n      max_val = std::max<float>(max_val, f);\n      min_exp = std::min<int>(min_exp, exp);\n      max_exp = std::max<int>(max_exp, exp);\n    }\n  }\n  if (pmin_exp)\n    *pmin_exp = min_exp;\n  if (pmax_exp)\n    *pmax_exp = max_exp;\n  if (pmin_val)\n    *pmin_val = min_val;\n  if (pmax_val)\n    *pmax_val = max_val;\n}\n"
  },
  {
    "path": "lib/matmul/cpp/portalmat.h",
    "content": "// Copyright (c) 2014 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\n#ifndef _PORTALMAT_H_\n#define _PORTALMAT_H_\n\n#include <opencv2/core/core.hpp>\n#include <semaphore.h>\n#include <stdio.h>\n#include <sys/mman.h>\n\n#include <portal.h>\n#include \"dmaManager.h\"\n#include \"MemServerRequest.h\"\n#include \"MMURequest.h\"\n\n#ifdef MATRIX_NT\n#include \"MmRequestNT.h\"\nextern MmRequestNTProxy *mmdevice;\n#else\n#ifdef MATRIX_TN\n#include \"MmRequestTN.h\"\nextern MmRequestTNProxy *mmdevice;\n#endif\n#endif\n \n#include \"MmIndication.h\"\n#include \"TimerRequest.h\"\n#include \"TimerIndication.h\"\n\nextern TimerRequestProxy *timerdevice;\nextern sem_t mul_sem;\n\nclass PortalMatAllocator : public cv::MatAllocator {\npublic:\n  PortalMatAllocator(DmaManager *dma) : numarrays(1), dma(dma) {}\n  virtual ~PortalMatAllocator() {}\n  virtual void allocate(int dims, const int* sizes, int type, int*& refcount,\n\t\t\tuchar*& datastart, uchar*& data, size_t* step);\n  virtual void deallocate(int* refcount, uchar* datastart, uchar* data);\n  int reference(int* refcount, uchar* datastart, uchar* data);\n  void cacheFlushInvalidate(int* refcount, uchar* datastart, uchar* data);\nprivate:\n  struct arrayInfo {\n    // refcount goes first\n    int refcount;\n    int fd;\n    uchar *data;\n    size_t totalsize;\n    int ref;\n  } arrayInfo[128];\n  int numarrays;\n  DmaManager *dma;\n};\n\nextern PortalMatAllocator *matAllocator;\nclass MmIndication;\n\nclass PortalMat : public cv::Mat {\npublic:\n  PortalMat();\n  PortalMat(int rows, int cols, int type);\n  PortalMat(int rows, int cols, int type, const cv::Scalar& s);\n  PortalMat(const PortalMat &m);\n  PortalMat(const cv::Mat &m);\n  ~PortalMat();\n  PortalMat& operator = (const cv::MatExpr& expr);\n  PortalMat& operator = (const cv::Mat& o);\n  int reference();\n  void cacheFlushInvalidate();\n  bool copy(cv::Mat &other);\n  bool copy(cv::MatExpr other);\n  bool transpose(cv::Mat &other);\n  bool compare(Mat &other, const char *file=0, int line=0, float epsilon=0.01, Mat *pm = 0, bool verbose = false);\n  void naive_mul(cv::Mat &a, cv::Mat &b, FILE *f);\n  void multf(PortalMat &a, PortalMat &b_transpose, MmIndication *mmind = NULL);\n};\n\nclass MmIndication : public MmIndicationWrapper\n{\npublic:\n  uint64_t ccnt;\n MmIndication(int id) : MmIndicationWrapper(id) {\n    ccnt = 0;\n  }\n  virtual ~MmIndication() {}\n  virtual void mmfDone(uint64_t cycles) {\n    ccnt = cycles;\n    fprintf(stderr, \"mmfDone cycles=%ld\\n\", (long)cycles);\n    sem_post(&mul_sem);\n  }\n  void dpsVal(uint32_t v) {\n    fprintf(stderr, \"dpsVal v=%x %f\\n\", v, *(float *)&v);\n    sem_post(&mul_sem);\n  }\n  void started() {\n    fprintf(stderr, \"mm.started:\\n\");\n  }\n  virtual void startSourceAndSink ( const unsigned int startA, const unsigned int startC, const int jint ) {\n    fprintf(stderr, \"mm.startSourceAndSink: startA=%6d startC=%06d jint=%d\\n\", startA, startC, jint);\n  }\n  virtual void debug ( uint32_t macCount) {\n    fprintf(stderr, \"mm.debug: macCount=%d\\n\", macCount);\n  }\n};\n\nclass TimerIndication : public TimerIndicationWrapper\n{\npublic:\n TimerIndication(int id) : TimerIndicationWrapper(id) {\n  }\n  virtual ~TimerIndication() {}\n  virtual void elapsedCycles(uint64_t cycles, uint64_t idleCycles) {\n    fprintf(stderr, \"elapsedCycles %lld idle %lld idle %f\\n\", (long long)cycles, (long long)idleCycles, (double)idleCycles / (double)cycles);\n  }\n};\n\ntemplate<typename T>\n  void dumpMat(const char *prefix, const char *fmt, const cv::Mat &mat);\n\ntemplate<typename T>\n  void dumpMatF(const char *prefix, const char *fmt, const cv::Mat &mat, FILE *ofile);\n\ntemplate<typename T>\n  void dumpMatOctave(const char *name, const char *fmt, const cv::Mat &mat, FILE *ofile);\n\nvoid dynamicRange(cv::Mat mat, int *pmin_exp, int *pmax_exp, float *pmin_val=0, float *pmax_val=0);\n\n#endif // _PORTALMAT_H_\n\n"
  },
  {
    "path": "lib/nandsim/bsv/NandSim.bsv",
    "content": "// Copyright (c) 2014 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\nimport FIFO::*;\nimport FIFOF::*;\nimport GetPut::*;\nimport Vector::*;\nimport BRAM::*;\nimport GetPut::*;\nimport Connectable::*;\n\nimport ConnectalConfig::*;\nimport ConnectalMemory::*;\nimport Pipe::*;\nimport ConnectalMemTypes::*;\nimport HostInterface::*;\nimport MemReadEngine::*;\nimport MemWriteEngine::*;\n\ninterface NandCfgRequest;\n   method Action startRead(Bit#(32) drampointer, Bit#(32) dramOffset, Bit#(32) nandAddr, Bit#(32) numBytes, Bit#(32) burstLen);\n   method Action startWrite(Bit#(32) drampointer, Bit#(32) dramOffset, Bit#(32) nandAddr, Bit#(32) numBytes, Bit#(32) burstLen);\n   method Action startErase(Bit#(32) nandAddr, Bit#(32) numBytes);\n   method Action configureNand(Bit#(32) ptr, Bit#(32) numBytes);\nendinterface\n\ninterface NandCfgIndication;\n   method Action readDone(Bit#(32) tag);\n   method Action writeDone(Bit#(32) tag);\n   method Action eraseDone(Bit#(32) tag);\n   method Action configureNandDone();\nendinterface\n\ninterface NandSim;\n   interface NandCfgRequest request;\n   interface PhysMemSlave#(PhysAddrWidth,64) memSlave;\n   interface Vector#(1, MemReadClient#(64)) readClient;\n   interface Vector#(1, MemWriteClient#(64)) writeClient;\nendinterface\n\ninterface NandSimControl;\n   interface NandCfgRequest request;\n   interface ReadOnly#(Bit#(32)) nandPtr;\nendinterface\n\nmodule mkNandSim#(NandCfgIndication indication) (NandSim);\n   let verbose = False;\n\n   MemReadEngine#(64,64,1,3)  re <- mkMemReadEngine();\n   MemWriteEngine#(64,64,1,4)  we <- mkMemWriteEngine();\n   NandSimControl ns <- mkNandSimControl(take(re.readServers), take(we.writeServers), indication);\n   let slave_read_server  = re.readServers[2];\n   let slave_write_server = we.writeServers[3];\n   FIFO#(Bit#(MemTagSize))    slaveWriteTag <- mkSizedFIFO(1);\n   FIFO#(Bit#(MemTagSize))    slaveReadTag <- mkSizedFIFO(1);\n   Reg#(Bit#(BurstLenSize))   slaveReadCnt <- mkReg(0);\n\n   interface PhysMemSlave memSlave;\n      interface PhysMemWriteServer write_server;\n\t interface Put writeReq;\n\t    method Action put(PhysMemRequest#(PhysAddrWidth,64) req);\n\t       if (verbose) $display(\"mkNandSim.memSlave::writeReq %d %d %d\", req.addr, req.burstLen, req.tag);\n\t       slave_write_server.request.put(MemengineCmd{sglId:ns.nandPtr, base:truncate(req.addr), burstLen:req.burstLen, len:extend(req.burstLen), tag: 0});\n\t       slaveWriteTag.enq(req.tag);\n            endmethod\n\t endinterface\n\t interface Put writeData;\n\t    method Action put(MemData#(64) wdata);\n\t       slave_write_server.data.enq(wdata.data);\n            endmethod\n\t endinterface\n\t interface Get writeDone;\n\t    method ActionValue#(Bit#(MemTagSize)) get();\n\t       let rv <- slave_write_server.done.get;\n\t       slaveWriteTag.deq;\n\t       return slaveWriteTag.first;\n            endmethod\n\t endinterface\n      endinterface\n      interface PhysMemReadServer read_server;\n\t interface Put readReq;\n\t    method Action put(PhysMemRequest#(PhysAddrWidth,64) req) if (slaveReadCnt == 0);\n\t       if (verbose) $display(\"mkNandSim.memSlave::readReq %d %d %d\", req.addr, req.burstLen, req.tag);\n\t       slave_read_server.request.put(MemengineCmd{sglId:ns.nandPtr, base:truncate(req.addr), burstLen:req.burstLen, len:extend(req.burstLen), tag: 0});\n\t       slaveReadTag.enq(req.tag);\n\t       slaveReadCnt <= req.burstLen;\n\t    endmethod\n\t endinterface\n\t interface Get  readData;\n\t    method ActionValue#(MemData#(64)) get() if (slaveReadCnt != 0);\n\t       let rv <- toGet(slave_read_server.data).get;\n\t       let new_slaveReadCnt = slaveReadCnt-8;\n\t       let last = new_slaveReadCnt==0;\n\t       slaveReadCnt <= new_slaveReadCnt;\n               if (rv.last)\n                  slaveReadTag.deq;\n\t       if (verbose) $display(\"mkNandSim.memSlave::readData %d %d %h %d\", slaveReadTag.first, last, rv.data, slaveReadCnt);\n\t       return MemData{data:rv.data, tag:slaveReadTag.first,last:last};\n            endmethod\n\t endinterface\n      endinterface\n   endinterface\n   interface request = ns.request;\n   interface MemReadClient readClient = cons(re.dmaClient, nil);\n   interface MemWriteClient writeClient = cons(we.dmaClient, nil);\n\nendmodule\n\nmodule mkNandSimControl#(Vector#(2, MemReadEngineServer#(64)) readSrvs, Vector#(3, MemWriteEngineServer#(64)) writeSrvs,\n\t\t\t  NandCfgIndication indication) (NandSimControl);\n   let dramReadServer = readSrvs[0];\n   let nandReadServer = readSrvs[1];\n   let dramWriteServer = writeSrvs[0];\n   let nandWriteServer = writeSrvs[1];\n   let nandEraseServer = writeSrvs[2];\n\n   Reg#(Maybe#(Bit#(32)))  nandPointer <- mkReg(tagged Invalid);\n   Reg#(Bit#(32))  nandLen       <- mkReg(0);\n\n   FIFOF#(Bit#(32))  readReqFifo <- mkFIFOF();\n   FIFOF#(Bit#(32)) writeReqFifo <- mkFIFOF();\n   Reg#(Bit#(32))   readCountReg <- mkReg(0);\n   Reg#(Bit#(32))  writeCountReg <- mkReg(0);\n   FIFOF#(Bool)     readDoneFifo <- mkFIFOF();\n   FIFOF#(Bool)    writeDoneFifo <- mkFIFOF();\n   FIFO#(void)      dramReadDone <- mkFIFO;\n   FIFO#(void)      nandReadDone <- mkFIFO;\n\n   rule countNandWrite;\n      let v <- toGet(dramReadServer.data).get();\n      let count = writeCountReg;\n      if (count == 0)\n\t count = writeReqFifo.first();\n      //$display(\"write v=%h count=%d\", v, count);\n      writeSrvs[1].data.enq(v.data);\n      if (count == 8) begin\n\t writeReqFifo.deq();\n\t writeDoneFifo.enq(True);\n      end\n      writeCountReg <= count-8;\n      if (v.last)\n         dramReadDone.enq(?);\n   endrule\n\n   rule countNandRead;\n      let v <- toGet(nandReadServer.data).get();\n      let count = readCountReg;\n      if (count == 0)\n\t count = readReqFifo.first();\n      //$display(\"read v=%h count=%d\", v, count);\n      writeSrvs[0].data.enq(v.data);\n      if (count == 8) begin\n\t readReqFifo.deq();\n\t readDoneFifo.enq(True);\n      end\n      readCountReg <= count-8;\n      if (v.last)\n         nandReadDone.enq(?);\n   endrule\n\n   PipeOut#(Bit#(64)) erasePipe = (interface PipeOut#(Bit#(64));\n\t\t\t\t       method Bit#(64) first(); return fromInteger(-1); endmethod\n\t\t\t\t       method Action deq(); endmethod\n\t\t\t\t       method Bool notEmpty(); return True; endmethod\n\t\t\t\t   endinterface);\n   mkConnection(erasePipe, writeSrvs[2].data);\n\n   rule eraseDone;\n      let done <- nandEraseServer.done.get();\n      $display(\"eraseDone\");\n      indication.eraseDone(0);\n   endrule\n\n   rule writeDone;\n      let nandWriteDone <- nandWriteServer.done.get();\n      dramReadDone.deq;\n      let v <- toGet(writeDoneFifo).get();\n      $display(\"writeDone\");\n      indication.writeDone(0);\n   endrule\n\n   rule readDone;\n      nandReadDone.deq;\n      let dramWriteDone <- dramWriteServer.done.get();\n      let v <- toGet(readDoneFifo).get();\n      $display(\"readDone\");\n      indication.readDone(0);\n   endrule\n\n   interface NandCfgRequest request;\n      /*!\n      * Reads from NAND and writes to DRAM\n      */\n      method Action startRead(Bit#(32) pointer, Bit#(32) dramOffset, Bit#(32) nandAddr,Bit#(32) numBytes, Bit#(32) burstLen);\n\t $display(\"startRead numBytes=%d burstLen=%d\", numBytes, burstLen);\n\t readReqFifo.enq(numBytes);\n\t nandReadServer.request.put(MemengineCmd {sglId: fromMaybe(0,nandPointer), base: extend(nandAddr), burstLen: truncate(burstLen), len: extend(numBytes), tag: 0});\n\t dramWriteServer.request.put(MemengineCmd {sglId: pointer, base: extend(dramOffset), burstLen: truncate(burstLen), len: extend(numBytes), tag: 0});\n      endmethod\n\n      /*!\n      * Reads from DRAM and writes to NAND\n      */\n      method Action startWrite(Bit#(32) pointer, Bit#(32) dramOffset, Bit#(32) nandAddr,Bit#(32) numBytes, Bit#(32) burstLen);\n\t $display(\"startWrite numBytes=%d burstLen=%d\", numBytes, burstLen);\n\t writeReqFifo.enq(numBytes);\n\t nandWriteServer.request.put(MemengineCmd {sglId: fromMaybe(0,nandPointer), base: extend(nandAddr), burstLen: truncate(burstLen), len: extend(numBytes), tag: 0});\n\t dramReadServer.request.put(MemengineCmd {sglId: pointer, base: extend(dramOffset), burstLen: truncate(burstLen), len: extend(numBytes), tag: 0});\n      endmethod\n\n      method Action startErase(Bit#(32) nandAddr, Bit#(32) numBytes);\n\t $display(\"startErase numBytes=%d burstLen=%d\", numBytes, 16);\n\t nandEraseServer.request.put(MemengineCmd {sglId: fromMaybe(0,nandPointer), base: extend(nandAddr), burstLen: 16, len: extend(numBytes), tag: 0});\n      endmethod\n\n      method Action configureNand(Bit#(32) ptr, Bit#(32) numBytes);\n\t nandPointer <= tagged Valid ptr;\n\t nandLen <= numBytes;\n\t indication.configureNandDone();\n\t $display(\"configureNand ptr=%d\", ptr);\n      endmethod\n   endinterface\n   interface ReadOnly nandPtr;\n      method Bit#(32) _read if (isValid(nandPointer));\n\t return fromMaybe(0,nandPointer);\n      endmethod\n   endinterface\nendmodule\n"
  },
  {
    "path": "lib/nandsim/bsv/NandSimNames.bsv",
    "content": "/* Copyright (c) 2014 Quanta Research Cambridge, Inc\n *\n * Permission is hereby granted, free of charge, to any person obtaining a\n * copy of this software and associated documentation files (the \"Software\"),\n * to deal in the Software without restriction, including without limitation\n * the rights to use, copy, modify, merge, publish, distribute, sublicense,\n * and/or sell copies of the Software, and to permit persons to whom the\n * Software is furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n * DEALINGS IN THE SOFTWARE.\n */\n\n\ntypedef enum {\n\n   IfcNames_MemServerRequestS2H,\n   IfcNames_MemServerIndicationH2S,\n\n   IfcNames_NandMemServerRequestS2H,\n   IfcNames_NandMemServerIndicationH2S,\n\t\n   IfcNames_BackingStoreMMURequestS2H,\n   IfcNames_BackingStoreMMUIndicationH2S,\n\n   IfcNames_MMURequestS2H,\n   IfcNames_MMUIndicationH2S,\n   IfcNames_AlgoMMURequestS2H,\n   IfcNames_AlgoMMUIndicationH2S,\n\n   IfcNames_NandMMURequestS2H,\n   IfcNames_NandMMUIndicationH2S,\n\n   IfcNames_NandCfgRequestS2H,\n   IfcNames_NandCfgIndicationH2S,\n\n   IfcNames_AlgoRequestS2H,\n   IfcNames_AlgoIndicationH2S\n\n   } IfcNames deriving (Eq,Bits);\n\n"
  },
  {
    "path": "lib/nandsim/cpp/nandsim.h",
    "content": "/* Copyright (c) 2013 Quanta Research Cambridge, Inc\n *\n * Permission is hereby granted, free of charge, to any person obtaining a\n * copy of this software and associated documentation files (the \"Software\"),\n * to deal in the Software without restriction, including without limitation\n * the rights to use, copy, modify, merge, publish, distribute, sublicense,\n * and/or sell copies of the Software, and to permit persons to whom the\n * Software is furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n * DEALINGS IN THE SOFTWARE.\n */\n\n#include <errno.h>\nstatic int sockfd = -1;\n#define SOCK_NAME \"socket_for_nandsim\"\nvoid wait_for_connect_nandsim_exe()\n{\n  int listening_socket;\n\n  if ((listening_socket = socket(AF_UNIX, SOCK_STREAM, 0)) == -1) {\n    fprintf(stderr, \"%s: socket error %s\",__FUNCTION__, strerror(errno));\n    exit(1);\n  }\n\n  struct sockaddr_un local;\n  local.sun_family = AF_UNIX;\n  strcpy(local.sun_path, SOCK_NAME);\n  unlink(local.sun_path);\n  int len = strlen(local.sun_path) + sizeof(local.sun_family);\n  if (bind(listening_socket, (struct sockaddr *)&local, len) == -1) {\n    fprintf(stderr, \"%s[%d]: bind error %s\\n\",__FUNCTION__, listening_socket, strerror(errno));\n    exit(1);\n  }\n\n  if (listen(listening_socket, 5) == -1) {\n    fprintf(stderr, \"%s[%d]: listen error %s\\n\",__FUNCTION__, listening_socket, strerror(errno));\n    exit(1);\n  }\n  \n  //fprintf(stderr, \"%s[%d]: waiting for a connection...\\n\",__FUNCTION__, listening_socket);\n  if ((sockfd = accept(listening_socket, NULL, NULL)) == -1) {\n    fprintf(stderr, \"%s[%d]: accept error %s\\n\",__FUNCTION__, listening_socket, strerror(errno));\n    exit(1);\n  }\n  remove(SOCK_NAME);  // we are connected now, so we can remove named socket\n}\n\nunsigned int read_from_nandsim_exe()\n{\n  unsigned int rv;\n  if(recv(sockfd, &rv, sizeof(rv), 0) == -1){\n    fprintf(stderr, \"%s recv error\\n\",__FUNCTION__);\n    exit(1);\t  \n  }\n  return rv;\n}\n\nvoid connect_to_algo_exe(void)\n{\n  int connect_attempts = 0;\n\n  if (sockfd != -1)\n    return;\n  if ((sockfd = socket(AF_UNIX, SOCK_STREAM, 0)) == -1) {\n    fprintf(stderr, \"%s (%s) socket error %s\\n\",__FUNCTION__, SOCK_NAME, strerror(errno));\n    exit(1);\n  }\n\n  //fprintf(stderr, \"%s (%s) trying to connect...\\n\",__FUNCTION__, SOCK_NAME);\n  struct sockaddr_un local;\n  local.sun_family = AF_UNIX;\n  strcpy(local.sun_path, SOCK_NAME);\n  while (connect(sockfd, (struct sockaddr *)&local, strlen(local.sun_path) + sizeof(local.sun_family)) == -1) {\n    if(connect_attempts++ > 100){\n      fprintf(stderr,\"%s (%s) connect error %s\\n\",__FUNCTION__, SOCK_NAME, strerror(errno));\n      exit(1);\n    }\n    fprintf(stderr, \"%s (%s) retrying connection\\n\",__FUNCTION__, SOCK_NAME);\n    sleep(5);\n  }\n  fprintf(stderr, \"%s (%s) connected\\n\",__FUNCTION__, SOCK_NAME);\n}\n\n\nvoid write_to_algo_exe(unsigned int x)\n{\n  int retry = 0;\n  while (retry++ < 10){\n    if (send(sockfd, &x, sizeof(x), 0) == -1) {\n      fprintf(stderr, \"%s send error\\n\",__FUNCTION__);\n      sleep(1);\n    } else {\n      retry = 0;\n      break;\n    }\n  }\n  if(retry){\n    fprintf(stderr, \"%s send failed\\n\",__FUNCTION__);\n    exit(1);\n  }\n}\n"
  },
  {
    "path": "lib/nvme/bsv/AxiPcie3RootPort.bsv",
    "content": "\n/*\n   ../../generated/scripts/importbvi.py\n   -I\n   APRP\n   -P\n   APRP\n   -c\n   userclk\n   -r\n   sys_rst_n\n   -r\n   axi_aresetn\n   -c\n   axi_aclk\n   -c\n   axi_ctl_aclk\n   -r\n   axi_ctl_aresetn\n   -c\n   refclk\n   -o\n   AxiPcie3RootPort.bsv\n   cores/vc709/axi_pcie_rp/axi_pcie_rp_stub.v\n*/\n\nimport Clocks::*;\nimport DefaultValue::*;\nimport XilinxCells::*;\nimport GetPut::*;\nimport AxiBits::*;\n\n(* always_ready, always_enabled *)\ninterface AprpAxi;\n    interface Clock     aclk;\n    method Reset     aresetn();\n    method Reset     ctl_aresetn();\nendinterface\n(* always_ready, always_enabled *)\ninterface AprpCfg;\n    method Bit#(6)     ltssm_state();\nendinterface\n(* always_ready, always_enabled *)\ninterface AprpInterrupt;\n    method Bit#(1)     out();\nendinterface\n(* always_ready, always_enabled *)\ninterface AprpIntx;\n    method Bit#(1)     msi_grant();\n    method Action      msi_request(Bit#(1) v);\nendinterface\n(* always_ready, always_enabled *)\ninterface AprpM_axi;\n    method Bit#(32)     araddr();\n    method Bit#(2)     arburst();\n    method Bit#(4)     arcache();\n    method Bit#(3)     arid();\n    method Bit#(8)     arlen();\n    method Bit#(1)     arlock();\n    method Bit#(3)     arprot();\n    method Action      arready(Bit#(1) v);\n    method Bit#(3)     arsize();\n    method Bit#(1)     arvalid();\n    method Bit#(32)     awaddr();\n    method Bit#(2)     awburst();\n    method Bit#(4)     awcache();\n    method Bit#(3)     awid();\n    method Bit#(8)     awlen();\n    method Bit#(1)     awlock();\n    method Bit#(3)     awprot();\n    method Action      awready(Bit#(1) v);\n    method Bit#(3)     awsize();\n    method Bit#(1)     awvalid();\n    method Action      bid(Bit#(3) v);\n    method Bit#(1)     bready();\n    method Action      bresp(Bit#(2) v);\n    method Action      bvalid(Bit#(1) v);\n    method Action      rdata(Bit#(128) v);\n    method Action      rid(Bit#(3) v);\n    method Action      rlast(Bit#(1) v);\n    method Bit#(1)     rready();\n    method Action      rresp(Bit#(2) v);\n    method Action      ruser(Bit#(32) v);\n    method Action      rvalid(Bit#(1) v);\n    method Bit#(128)     wdata();\n    method Bit#(1)     wlast();\n    method Action      wready(Bit#(1) v);\n    method Bit#(16)     wstrb();\n    method Bit#(32)     wuser();\n    method Bit#(1)     wvalid();\nendinterface\n(* always_ready, always_enabled *)\ninterface AprpMsi;\n    method Bit#(1)     enable();\n    method Action      vector_num(Bit#(5) v);\n    method Bit#(3)     vector_width();\nendinterface\n(* always_ready, always_enabled *)\ninterface AprpPci;\n    method Action      exp_rxn(Bit#(4) v);\n    method Action      exp_rxp(Bit#(4) v);\n    method Bit#(4)     exp_txn();\n    method Bit#(4)     exp_txp();\nendinterface\n(* always_ready, always_enabled *)\ninterface AprpS_axi;\n    method Action      araddr(Bit#(32) v);\n    method Action      arburst(Bit#(2) v);\n    method Action      arid(Bit#(4) v);\n    method Action      arlen(Bit#(8) v);\n    method Bit#(1)     arready();\n    method Action      arregion(Bit#(4) v);\n    method Action      arsize(Bit#(3) v);\n    method Action      arvalid(Bit#(1) v);\n    method Action      awaddr(Bit#(32) v);\n    method Action      awburst(Bit#(2) v);\n    method Action      awid(Bit#(4) v);\n    method Action      awlen(Bit#(8) v);\n    method Bit#(1)     awready();\n    method Action      awregion(Bit#(4) v);\n    method Action      awsize(Bit#(3) v);\n    method Action      awvalid(Bit#(1) v);\n    method Bit#(4)     bid();\n    method Action      bready(Bit#(1) v);\n    method Bit#(2)     bresp();\n    method Bit#(1)     bvalid();\n    method Bit#(128)     rdata();\n    method Bit#(4)     rid();\n    method Bit#(1)     rlast();\n    method Action      rready(Bit#(1) v);\n    method Bit#(2)     rresp();\n    method Bit#(32)     ruser();\n    method Bit#(1)     rvalid();\n    method Action      wdata(Bit#(128) v);\n    method Action      wlast(Bit#(1) v);\n    method Bit#(1)     wready();\n    method Action      wstrb(Bit#(16) v);\n    method Action      wuser(Bit#(32) v);\n    method Action      wvalid(Bit#(1) v);\nendinterface\n(* always_ready, always_enabled *)\ninterface AprpS_axi_ctl;\n    method Action      araddr(Bit#(28) v);\n    method Bit#(1)     arready();\n    method Action      arvalid(Bit#(1) v);\n    method Action      awaddr(Bit#(28) v);\n    method Bit#(1)     awready();\n    method Action      awvalid(Bit#(1) v);\n    method Action      bready(Bit#(1) v);\n    method Bit#(2)     bresp();\n    method Bit#(1)     bvalid();\n    method Bit#(32)     rdata();\n    method Action      rready(Bit#(1) v);\n    method Bit#(2)     rresp();\n    method Bit#(1)     rvalid();\n    method Action      wdata(Bit#(32) v);\n    method Bit#(1)     wready();\n    method Action      wstrb(Bit#(4) v);\n    method Action      wvalid(Bit#(1) v);\nendinterface\n(* always_ready, always_enabled *)\n(* always_ready, always_enabled *)\ninterface AprpUser;\n    method Bit#(1)     link_up();\nendinterface\n(* always_ready, always_enabled *)\ninterface APRP;\n    interface AprpAxi     axi;\n    interface AprpCfg     cfg;\n    interface AprpInterrupt     interrupt;\n    interface AprpIntx     intx;\n    interface AprpM_axi     m_axi;\n    interface AprpMsi     msi;\n    interface AprpPci     pci;\n    interface AprpS_axi     s_axi;\n    interface AprpS_axi_ctl     s_axi_ctl;\n    interface AprpUser     user;\nendinterface\nimport \"BVI\" axi_pcie_rp =\nmodule mkAPRP#(Clock axi_aclk_in, Reset axi_aresetn_in, Clock refclk, Reset sys_rst_n)(APRP);\n    default_clock clk();\n    default_reset rst();\n        input_clock axi_ctl_aclk(axi_ctl_aclk) = axi_aclk_in;\n    input_clock refclk(refclk) = refclk;\n        input_reset sys_rst_n(sys_rst_n) = sys_rst_n;\n   input_clock axi_aclk_in() = axi_aclk_in;\n   input_reset axi_aresetn_in() clocked_by (axi_aclk_in) = axi_aresetn_in;\n    interface AprpAxi     axi;\n        output_clock aclk(axi_aclk);\n        output_reset aresetn(axi_aresetn) clocked_by (axi_aclk_in);\n        output_reset ctl_aresetn(axi_ctl_aresetn) clocked_by (axi_aclk_in);\n    endinterface\n    interface AprpCfg     cfg;\n       method cfg_ltssm_state ltssm_state();\n    endinterface\n    interface AprpInterrupt     interrupt;\n        method interrupt_out out() clocked_by (axi_aclk_in) reset_by (axi_aresetn_in);\n    endinterface\n    interface AprpIntx     intx;\n        method intx_msi_grant msi_grant() clocked_by (axi_aclk_in) reset_by (axi_aresetn_in);\n        method msi_request(intx_msi_request) enable((*inhigh*) EN_intx_msi_request) clocked_by (axi_aclk_in) reset_by (axi_aresetn_in);\n    endinterface\n    interface AprpM_axi     m_axi;\n        method m_axi_araddr araddr()  clocked_by (axi_aclk_in) reset_by (axi_aresetn_in);\n        method m_axi_arburst arburst()  clocked_by (axi_aclk_in) reset_by (axi_aresetn_in);\n        method m_axi_arcache arcache() clocked_by (axi_aclk_in) reset_by (axi_aresetn_in);\n        method m_axi_arid arid() clocked_by (axi_aclk_in) reset_by (axi_aresetn_in);\n        method m_axi_arlen arlen() clocked_by (axi_aclk_in) reset_by (axi_aresetn_in);\n        method m_axi_arlock arlock() clocked_by (axi_aclk_in) reset_by (axi_aresetn_in);\n        method m_axi_arprot arprot() clocked_by (axi_aclk_in) reset_by (axi_aresetn_in);\n        method arready(m_axi_arready) enable((*inhigh*) EN_m_axi_arready) clocked_by (axi_aclk_in) reset_by (axi_aresetn_in);\n        method m_axi_arsize arsize() clocked_by (axi_aclk_in) reset_by (axi_aresetn_in);\n        method m_axi_arvalid arvalid() clocked_by (axi_aclk_in) reset_by (axi_aresetn_in);\n        method m_axi_awaddr awaddr() clocked_by (axi_aclk_in) reset_by (axi_aresetn_in);\n        method m_axi_awburst awburst() clocked_by (axi_aclk_in) reset_by (axi_aresetn_in);\n        method m_axi_awcache awcache() clocked_by (axi_aclk_in) reset_by (axi_aresetn_in);\n        method m_axi_awid awid() clocked_by (axi_aclk_in) reset_by (axi_aresetn_in);\n        method m_axi_awlen awlen() clocked_by (axi_aclk_in) reset_by (axi_aresetn_in);\n        method m_axi_awlock awlock() clocked_by (axi_aclk_in) reset_by (axi_aresetn_in);\n        method m_axi_awprot awprot() clocked_by (axi_aclk_in) reset_by (axi_aresetn_in);\n        method awready(m_axi_awready) enable((*inhigh*) EN_m_axi_awready) clocked_by (axi_aclk_in) reset_by (axi_aresetn_in);\n        method m_axi_awsize awsize() clocked_by (axi_aclk_in) reset_by (axi_aresetn_in);\n        method m_axi_awvalid awvalid() clocked_by (axi_aclk_in) reset_by (axi_aresetn_in);\n        method bid(m_axi_bid) enable((*inhigh*) EN_m_axi_bid) clocked_by (axi_aclk_in) reset_by (axi_aresetn_in);\n        method m_axi_bready bready() clocked_by (axi_aclk_in) reset_by (axi_aresetn_in);\n        method bresp(m_axi_bresp) enable((*inhigh*) EN_m_axi_bresp) clocked_by (axi_aclk_in) reset_by (axi_aresetn_in);\n        method bvalid(m_axi_bvalid) enable((*inhigh*) EN_m_axi_bvalid) clocked_by (axi_aclk_in) reset_by (axi_aresetn_in);\n        method rdata(m_axi_rdata) enable((*inhigh*) EN_m_axi_rdata) clocked_by (axi_aclk_in) reset_by (axi_aresetn_in);\n        method rid(m_axi_rid) enable((*inhigh*) EN_m_axi_rid) clocked_by (axi_aclk_in) reset_by (axi_aresetn_in);\n        method rlast(m_axi_rlast) enable((*inhigh*) EN_m_axi_rlast) clocked_by (axi_aclk_in) reset_by (axi_aresetn_in);\n        method m_axi_rready rready() clocked_by (axi_aclk_in) reset_by (axi_aresetn_in);\n        method rresp(m_axi_rresp) enable((*inhigh*) EN_m_axi_rresp) clocked_by (axi_aclk_in) reset_by (axi_aresetn_in);\n        method ruser(m_axi_ruser) enable((*inhigh*) EN_m_axi_ruser) clocked_by (axi_aclk_in) reset_by (axi_aresetn_in);\n        method rvalid(m_axi_rvalid) enable((*inhigh*) EN_m_axi_rvalid) clocked_by (axi_aclk_in) reset_by (axi_aresetn_in);\n        method m_axi_wdata wdata() clocked_by (axi_aclk_in) reset_by (axi_aresetn_in);\n        method m_axi_wlast wlast() clocked_by (axi_aclk_in) reset_by (axi_aresetn_in);\n        method wready(m_axi_wready) enable((*inhigh*) EN_m_axi_wready) clocked_by (axi_aclk_in) reset_by (axi_aresetn_in);\n        method m_axi_wstrb wstrb() clocked_by (axi_aclk_in) reset_by (axi_aresetn_in);\n        method m_axi_wuser wuser() clocked_by (axi_aclk_in) reset_by (axi_aresetn_in);\n        method m_axi_wvalid wvalid() clocked_by (axi_aclk_in) reset_by (axi_aresetn_in);\n    endinterface\n    interface AprpMsi     msi;\n        method msi_enable enable() clocked_by (axi_aclk_in) reset_by (axi_aresetn_in);\n        method vector_num(msi_vector_num) enable((*inhigh*) EN_msi_vector_num) clocked_by (axi_aclk_in) reset_by (axi_aresetn_in);\n        method msi_vector_width vector_width() clocked_by (axi_aclk_in) reset_by (axi_aresetn_in);\n    endinterface\n    interface AprpPci     pci;\n        method exp_rxn(pci_exp_rxn) enable((*inhigh*) EN_pci_exp_rxn);\n        method exp_rxp(pci_exp_rxp) enable((*inhigh*) EN_pci_exp_rxp);\n        method pci_exp_txn exp_txn();\n        method pci_exp_txp exp_txp();\n    endinterface\n    interface AprpS_axi     s_axi;\n        method araddr(s_axi_araddr) enable((*inhigh*) EN_s_axi_araddr) clocked_by (axi_aclk_in) reset_by (axi_aresetn_in);\n        method arburst(s_axi_arburst) enable((*inhigh*) EN_s_axi_arburst) clocked_by (axi_aclk_in) reset_by (axi_aresetn_in);\n        method arid(s_axi_arid) enable((*inhigh*) EN_s_axi_arid) clocked_by (axi_aclk_in) reset_by (axi_aresetn_in);\n        method arlen(s_axi_arlen) enable((*inhigh*) EN_s_axi_arlen) clocked_by (axi_aclk_in) reset_by (axi_aresetn_in);\n        method s_axi_arready arready() clocked_by (axi_aclk_in) reset_by (axi_aresetn_in);\n        method arregion(s_axi_arregion) enable((*inhigh*) EN_s_axi_arregion) clocked_by (axi_aclk_in) reset_by (axi_aresetn_in);\n        method arsize(s_axi_arsize) enable((*inhigh*) EN_s_axi_arsize) clocked_by (axi_aclk_in) reset_by (axi_aresetn_in);\n        method arvalid(s_axi_arvalid) enable((*inhigh*) EN_s_axi_arvalid) clocked_by (axi_aclk_in) reset_by (axi_aresetn_in);\n        method awaddr(s_axi_awaddr) enable((*inhigh*) EN_s_axi_awaddr) clocked_by (axi_aclk_in) reset_by (axi_aresetn_in);\n        method awburst(s_axi_awburst) enable((*inhigh*) EN_s_axi_awburst) clocked_by (axi_aclk_in) reset_by (axi_aresetn_in);\n        method awid(s_axi_awid) enable((*inhigh*) EN_s_axi_awid) clocked_by (axi_aclk_in) reset_by (axi_aresetn_in);\n        method awlen(s_axi_awlen) enable((*inhigh*) EN_s_axi_awlen) clocked_by (axi_aclk_in) reset_by (axi_aresetn_in);\n        method s_axi_awready awready() clocked_by (axi_aclk_in) reset_by (axi_aresetn_in);\n        method awregion(s_axi_awregion) enable((*inhigh*) EN_s_axi_awregion) clocked_by (axi_aclk_in) reset_by (axi_aresetn_in);\n        method awsize(s_axi_awsize) enable((*inhigh*) EN_s_axi_awsize) clocked_by (axi_aclk_in) reset_by (axi_aresetn_in);\n        method awvalid(s_axi_awvalid) enable((*inhigh*) EN_s_axi_awvalid) clocked_by (axi_aclk_in) reset_by (axi_aresetn_in);\n        method s_axi_bid bid() clocked_by (axi_aclk_in) reset_by (axi_aresetn_in);\n        method bready(s_axi_bready) enable((*inhigh*) EN_s_axi_bready) clocked_by (axi_aclk_in) reset_by (axi_aresetn_in);\n        method s_axi_bresp bresp() clocked_by (axi_aclk_in) reset_by (axi_aresetn_in);\n        method s_axi_bvalid bvalid() clocked_by (axi_aclk_in) reset_by (axi_aresetn_in);\n        method s_axi_rdata rdata() clocked_by (axi_aclk_in) reset_by (axi_aresetn_in);\n        method s_axi_rid rid() clocked_by (axi_aclk_in) reset_by (axi_aresetn_in);\n        method s_axi_rlast rlast() clocked_by (axi_aclk_in) reset_by (axi_aresetn_in);\n        method rready(s_axi_rready) enable((*inhigh*) EN_s_axi_rready) clocked_by (axi_aclk_in) reset_by (axi_aresetn_in);\n        method s_axi_rresp rresp() clocked_by (axi_aclk_in) reset_by (axi_aresetn_in);\n        method s_axi_ruser ruser() clocked_by (axi_aclk_in) reset_by (axi_aresetn_in);\n        method s_axi_rvalid rvalid() clocked_by (axi_aclk_in) reset_by (axi_aresetn_in);\n        method wdata(s_axi_wdata) enable((*inhigh*) EN_s_axi_wdata) clocked_by (axi_aclk_in) reset_by (axi_aresetn_in);\n        method wlast(s_axi_wlast) enable((*inhigh*) EN_s_axi_wlast) clocked_by (axi_aclk_in) reset_by (axi_aresetn_in);\n        method s_axi_wready wready() clocked_by (axi_aclk_in) reset_by (axi_aresetn_in);\n        method wstrb(s_axi_wstrb) enable((*inhigh*) EN_s_axi_wstrb) clocked_by (axi_aclk_in) reset_by (axi_aresetn_in);\n        method wuser(s_axi_wuser) enable((*inhigh*) EN_s_axi_wuser) clocked_by (axi_aclk_in) reset_by (axi_aresetn_in);\n        method wvalid(s_axi_wvalid) enable((*inhigh*) EN_s_axi_wvalid) clocked_by (axi_aclk_in) reset_by (axi_aresetn_in);\n    endinterface\n    interface AprpS_axi_ctl     s_axi_ctl;\n        method araddr(s_axi_ctl_araddr) enable((*inhigh*) EN_s_axi_ctl_araddr) clocked_by (axi_aclk_in) reset_by (axi_aresetn_in);\n        method s_axi_ctl_arready arready() clocked_by (axi_aclk_in) reset_by (axi_aresetn_in);\n        method arvalid(s_axi_ctl_arvalid) enable((*inhigh*) EN_s_axi_ctl_arvalid) clocked_by (axi_aclk_in) reset_by (axi_aresetn_in);\n        method awaddr(s_axi_ctl_awaddr) enable((*inhigh*) EN_s_axi_ctl_awaddr) clocked_by (axi_aclk_in) reset_by (axi_aresetn_in);\n        method s_axi_ctl_awready awready() clocked_by (axi_aclk_in) reset_by (axi_aresetn_in);\n        method awvalid(s_axi_ctl_awvalid) enable((*inhigh*) EN_s_axi_ctl_awvalid) clocked_by (axi_aclk_in) reset_by (axi_aresetn_in);\n        method bready(s_axi_ctl_bready) enable((*inhigh*) EN_s_axi_ctl_bready) clocked_by (axi_aclk_in) reset_by (axi_aresetn_in);\n        method s_axi_ctl_bresp bresp() clocked_by (axi_aclk_in) reset_by (axi_aresetn_in);\n        method s_axi_ctl_bvalid bvalid() clocked_by (axi_aclk_in) reset_by (axi_aresetn_in);\n        method s_axi_ctl_rdata rdata() clocked_by (axi_aclk_in) reset_by (axi_aresetn_in);\n        method rready(s_axi_ctl_rready) enable((*inhigh*) EN_s_axi_ctl_rready) clocked_by (axi_aclk_in) reset_by (axi_aresetn_in);\n        method s_axi_ctl_rresp rresp() clocked_by (axi_aclk_in) reset_by (axi_aresetn_in);\n        method s_axi_ctl_rvalid rvalid() clocked_by (axi_aclk_in) reset_by (axi_aresetn_in);\n        method wdata(s_axi_ctl_wdata) enable((*inhigh*) EN_s_axi_ctl_wdata) clocked_by (axi_aclk_in) reset_by (axi_aresetn_in);\n        method s_axi_ctl_wready wready() clocked_by (axi_aclk_in) reset_by (axi_aresetn_in);\n        method wstrb(s_axi_ctl_wstrb) enable((*inhigh*) EN_s_axi_ctl_wstrb) clocked_by (axi_aclk_in) reset_by (axi_aresetn_in);\n        method wvalid(s_axi_ctl_wvalid) enable((*inhigh*) EN_s_axi_ctl_wvalid) clocked_by (axi_aclk_in) reset_by (axi_aresetn_in);\n    endinterface\n    interface AprpUser     user;\n       method user_link_up link_up();\n    endinterface\n    schedule (cfg.ltssm_state, interrupt.out, intx.msi_grant, intx.msi_request, m_axi.araddr, m_axi.arburst, m_axi.arcache, m_axi.arid, m_axi.arlen, m_axi.arlock, m_axi.arprot, m_axi.arready, m_axi.arsize, m_axi.arvalid, m_axi.awaddr, m_axi.awburst, m_axi.awcache, m_axi.awid, m_axi.awlen, m_axi.awlock, m_axi.awprot, m_axi.awready, m_axi.awsize, m_axi.awvalid, m_axi.bid, m_axi.bready, m_axi.bresp, m_axi.bvalid, m_axi.rdata, m_axi.rid, m_axi.rlast, m_axi.rready, m_axi.rresp, m_axi.ruser, m_axi.rvalid, m_axi.wdata, m_axi.wlast, m_axi.wready, m_axi.wstrb, m_axi.wuser, m_axi.wvalid, msi.enable, msi.vector_num, msi.vector_width, pci.exp_rxn, pci.exp_rxp, pci.exp_txn, pci.exp_txp, s_axi.araddr, s_axi.arburst, s_axi.arid, s_axi.arlen, s_axi.arready, s_axi.arregion, s_axi.arsize, s_axi.arvalid, s_axi.awaddr, s_axi.awburst, s_axi.awid, s_axi.awlen, s_axi.awready, s_axi.awregion, s_axi.awsize, s_axi.awvalid, s_axi.bid, s_axi.bready, s_axi.bresp, s_axi.bvalid, s_axi.rdata, s_axi.rid, s_axi.rlast, s_axi.rready, s_axi.rresp, s_axi.ruser, s_axi.rvalid, s_axi.wdata, s_axi.wlast, s_axi.wready, s_axi.wstrb, s_axi.wuser, s_axi.wvalid, s_axi_ctl.araddr, s_axi_ctl.arready, s_axi_ctl.arvalid, s_axi_ctl.awaddr, s_axi_ctl.awready, s_axi_ctl.awvalid, s_axi_ctl.bready, s_axi_ctl.bresp, s_axi_ctl.bvalid, s_axi_ctl.rdata, s_axi_ctl.rready, s_axi_ctl.rresp, s_axi_ctl.rvalid, s_axi_ctl.wdata, s_axi_ctl.wready, s_axi_ctl.wstrb, s_axi_ctl.wvalid, user.link_up) CF (cfg.ltssm_state, interrupt.out, intx.msi_grant, intx.msi_request, m_axi.araddr, m_axi.arburst, m_axi.arcache, m_axi.arid, m_axi.arlen, m_axi.arlock, m_axi.arprot, m_axi.arready, m_axi.arsize, m_axi.arvalid, m_axi.awaddr, m_axi.awburst, m_axi.awcache, m_axi.awid, m_axi.awlen, m_axi.awlock, m_axi.awprot, m_axi.awready, m_axi.awsize, m_axi.awvalid, m_axi.bid, m_axi.bready, m_axi.bresp, m_axi.bvalid, m_axi.rdata, m_axi.rid, m_axi.rlast, m_axi.rready, m_axi.rresp, m_axi.ruser, m_axi.rvalid, m_axi.wdata, m_axi.wlast, m_axi.wready, m_axi.wstrb, m_axi.wuser, m_axi.wvalid, msi.enable, msi.vector_num, msi.vector_width, pci.exp_rxn, pci.exp_rxp, pci.exp_txn, pci.exp_txp, s_axi.araddr, s_axi.arburst, s_axi.arid, s_axi.arlen, s_axi.arready, s_axi.arregion, s_axi.arsize, s_axi.arvalid, s_axi.awaddr, s_axi.awburst, s_axi.awid, s_axi.awlen, s_axi.awready, s_axi.awregion, s_axi.awsize, s_axi.awvalid, s_axi.bid, s_axi.bready, s_axi.bresp, s_axi.bvalid, s_axi.rdata, s_axi.rid, s_axi.rlast, s_axi.rready, s_axi.rresp, s_axi.ruser, s_axi.rvalid, s_axi.wdata, s_axi.wlast, s_axi.wready, s_axi.wstrb, s_axi.wuser, s_axi.wvalid, s_axi_ctl.araddr, s_axi_ctl.arready, s_axi_ctl.arvalid, s_axi_ctl.awaddr, s_axi_ctl.awready, s_axi_ctl.awvalid, s_axi_ctl.bready, s_axi_ctl.bresp, s_axi_ctl.bvalid, s_axi_ctl.rdata, s_axi_ctl.rready, s_axi_ctl.rresp, s_axi_ctl.rvalid, s_axi_ctl.wdata, s_axi_ctl.wready, s_axi_ctl.wstrb, s_axi_ctl.wvalid, user.link_up);\nendmodule\n"
  },
  {
    "path": "lib/nvme/bsv/AxiPcieRootPort.bsv",
    "content": "\n/*\n   ../../generated/scripts/importbvi.py\n   -I\n   APRP\n   -P\n   APRP\n   -r\n   axi_aresetn\n   -c\n   axi_aclk_out\n   -c\n   axi_ctl_aclk_out\n   -c\n   REFCLK\n   -o\n   AxiPcieRootPort.bsv\n   /home/jamey/miniitx100/miniitx100.srcs/sources_1/ip/axi_pcie_0/axi_pcie_0_stub.v\n*/\n\nimport Clocks::*;\nimport DefaultValue::*;\nimport XilinxCells::*;\nimport GetPut::*;\nimport AxiBits::*;\nimport NvmeIfc::*; // for PcieDataBusWidth\n\n(* always_ready, always_enabled *)\ninterface AprpAxi;\n    interface Clock     aclk_out;\n    interface Clock     ctl_aclk_out;\nendinterface\n(* always_ready, always_enabled *)\ninterface AprpInterrupt;\n    method Bit#(1)     out();\nendinterface\n(* always_ready, always_enabled *)\ninterface AprpIntx;\n    method Bit#(1)     msi_grant();\n    method Action      msi_request(Bit#(1) v);\nendinterface\n(* always_ready, always_enabled *)\ninterface AprpM_axi;\n    method Bit#(32)     araddr();\n    method Bit#(2)     arburst();\n    method Bit#(4)     arcache();\n    method Bit#(8)     arlen();\n    method Bit#(1)     arlock();\n    method Bit#(3)     arprot();\n    method Action      arready(Bit#(1) v);\n    method Bit#(3)     arsize();\n    method Bit#(1)     arvalid();\n    method Bit#(32)     awaddr();\n    method Bit#(2)     awburst();\n    method Bit#(4)     awcache();\n    method Bit#(8)     awlen();\n    method Bit#(1)     awlock();\n    method Bit#(3)     awprot();\n    method Action      awready(Bit#(1) v);\n    method Bit#(3)     awsize();\n    method Bit#(1)     awvalid();\n    method Bit#(1)     bready();\n    method Action      bresp(Bit#(2) v);\n    method Action      bvalid(Bit#(1) v);\n    method Action      rdata(Bit#(PcieDataBusWidth) v);\n    method Action      rlast(Bit#(1) v);\n    method Bit#(1)     rready();\n    method Action      rresp(Bit#(2) v);\n    method Action      rvalid(Bit#(1) v);\n    method Bit#(PcieDataBusWidth)     wdata();\n    method Bit#(1)     wlast();\n    method Action      wready(Bit#(1) v);\n    method Bit#(TDiv#(PcieDataBusWidth,8))     wstrb();\n    method Bit#(1)     wvalid();\nendinterface\n(* always_ready, always_enabled *)\ninterface AprpMmcm;\n    method Bit#(1)     lock();\nendinterface\n(* always_ready, always_enabled *)\ninterface AprpMsi;\n    method Bit#(1)     enable();\n    method Action      vector_num(Bit#(5) v);\n    method Bit#(3)     vector_width();\nendinterface\n(* always_ready, always_enabled *)\ninterface AprpPci;\n    method Action      exp_rxn(Bit#(4) v);\n    method Action      exp_rxp(Bit#(4) v);\n    method Bit#(4)     exp_txn();\n    method Bit#(4)     exp_txp();\nendinterface\n(* always_ready, always_enabled *)\ninterface AprpS_axi;\n    method Action      araddr(Bit#(32) v);\n    method Action      arburst(Bit#(2) v);\n    method Action      arid(Bit#(4) v);\n    method Action      arlen(Bit#(8) v);\n    method Bit#(1)     arready();\n    method Action      arregion(Bit#(4) v);\n    method Action      arsize(Bit#(3) v);\n    method Action      arvalid(Bit#(1) v);\n    method Action      awaddr(Bit#(32) v);\n    method Action      awburst(Bit#(2) v);\n    method Action      awid(Bit#(4) v);\n    method Action      awlen(Bit#(8) v);\n    method Bit#(1)     awready();\n    method Action      awregion(Bit#(4) v);\n    method Action      awsize(Bit#(3) v);\n    method Action      awvalid(Bit#(1) v);\n    method Bit#(4)     bid();\n    method Action      bready(Bit#(1) v);\n    method Bit#(2)     bresp();\n    method Bit#(1)     bvalid();\n    method Bit#(PcieDataBusWidth)     rdata();\n    method Bit#(4)     rid();\n    method Bit#(1)     rlast();\n    method Action      rready(Bit#(1) v);\n    method Bit#(2)     rresp();\n    method Bit#(1)     rvalid();\n    method Action      wdata(Bit#(PcieDataBusWidth) v);\n    method Action      wlast(Bit#(1) v);\n    method Bit#(1)     wready();\n    method Action      wstrb(Bit#(TDiv#(PcieDataBusWidth,8)) v);\n    method Action      wvalid(Bit#(1) v);\nendinterface\n(* always_ready, always_enabled *)\ninterface AprpS_axi_ctl;\n    method Action      araddr(Bit#(32) v);\n    method Bit#(1)     arready();\n    method Action      arvalid(Bit#(1) v);\n    method Action      awaddr(Bit#(32) v);\n    method Bit#(1)     awready();\n    method Action      awvalid(Bit#(1) v);\n    method Action      bready(Bit#(1) v);\n    method Bit#(2)     bresp();\n    method Bit#(1)     bvalid();\n    method Bit#(32)     rdata();\n    method Action      rready(Bit#(1) v);\n    method Bit#(2)     rresp();\n    method Bit#(1)     rvalid();\n    method Action      wdata(Bit#(32) v);\n    method Bit#(1)     wready();\n    method Action      wstrb(Bit#(4) v);\n    method Action      wvalid(Bit#(1) v);\nendinterface\n(* always_ready, always_enabled *)\ninterface APRP;\n    interface AprpAxi     axi;\n    interface AprpInterrupt     interrupt;\n    interface AprpIntx     intx;\n    interface AprpM_axi     m_axi;\n    interface AprpMmcm     mmcm;\n    interface AprpMsi     msi;\n    interface AprpPci     pci;\n    interface AprpS_axi     s_axi;\n    interface AprpS_axi_ctl     s_axi_ctl;\nendinterface\nimport \"BVI\" axi_pcie_rp =\nmodule mkAPRP#(Clock refclk, Reset reset, Clock axi_aclk, Reset axi_aresetn, Clock axi_ctl_aclk, Reset axi_ctl_aresetn)(APRP);\n    default_clock clk();\n    default_reset rst();\n    input_clock axi_aclk() = axi_aclk;\n    input_clock axi_ctl_aclk() = axi_ctl_aclk;\n        input_reset reset(axi_aresetn) = reset;\n        input_reset axi_aresetn() clocked_by (axi_aclk) = axi_aresetn;\n\tinput_reset axi_ctl_aresetn() clocked_by (axi_ctl_aclk) = axi_ctl_aresetn;\n    input_clock refclk(REFCLK) = refclk;\n    interface AprpAxi     axi;\n        output_clock aclk_out(axi_aclk_out);\n        output_clock ctl_aclk_out(axi_ctl_aclk_out);\n    endinterface\n    interface AprpInterrupt     interrupt;\n        method interrupt_out out();\n    endinterface\n    interface AprpIntx     intx;\n        method INTX_MSI_Grant msi_grant();\n        method msi_request(INTX_MSI_Request) enable((*inhigh*) EN_INTX_MSI_Request);\n    endinterface\n    interface AprpM_axi     m_axi;\n        method m_axi_araddr araddr();\n        method m_axi_arburst arburst();\n        method m_axi_arcache arcache();\n        method m_axi_arlen arlen();\n        method m_axi_arlock arlock();\n        method m_axi_arprot arprot();\n        method arready(m_axi_arready) enable((*inhigh*) EN_m_axi_arready);\n        method m_axi_arsize arsize();\n        method m_axi_arvalid arvalid();\n        method m_axi_awaddr awaddr();\n        method m_axi_awburst awburst();\n        method m_axi_awcache awcache();\n        method m_axi_awlen awlen();\n        method m_axi_awlock awlock();\n        method m_axi_awprot awprot();\n        method awready(m_axi_awready) enable((*inhigh*) EN_m_axi_awready);\n        method m_axi_awsize awsize();\n        method m_axi_awvalid awvalid();\n        method m_axi_bready bready();\n        method bresp(m_axi_bresp) enable((*inhigh*) EN_m_axi_bresp);\n        method bvalid(m_axi_bvalid) enable((*inhigh*) EN_m_axi_bvalid);\n        method rdata(m_axi_rdata) enable((*inhigh*) EN_m_axi_rdata);\n        method rlast(m_axi_rlast) enable((*inhigh*) EN_m_axi_rlast);\n        method m_axi_rready rready();\n        method rresp(m_axi_rresp) enable((*inhigh*) EN_m_axi_rresp);\n        method rvalid(m_axi_rvalid) enable((*inhigh*) EN_m_axi_rvalid);\n        method m_axi_wdata wdata();\n        method m_axi_wlast wlast();\n        method wready(m_axi_wready) enable((*inhigh*) EN_m_axi_wready);\n        method m_axi_wstrb wstrb();\n        method m_axi_wvalid wvalid();\n    endinterface\n    interface AprpMmcm     mmcm;\n        method mmcm_lock lock();\n    endinterface\n    interface AprpMsi     msi;\n        method MSI_enable enable();\n        method vector_num(MSI_Vector_Num) enable((*inhigh*) EN_MSI_Vector_Num);\n        method MSI_Vector_Width vector_width();\n    endinterface\n    interface AprpPci     pci;\n        method exp_rxn(pci_exp_rxn) enable((*inhigh*) EN_pci_exp_rxn);\n        method exp_rxp(pci_exp_rxp) enable((*inhigh*) EN_pci_exp_rxp);\n        method pci_exp_txn exp_txn();\n        method pci_exp_txp exp_txp();\n    endinterface\n    interface AprpS_axi     s_axi;\n        method araddr(s_axi_araddr) enable((*inhigh*) EN_s_axi_araddr) clocked_by(axi_aclk) reset_by (axi_aresetn);\n        method arburst(s_axi_arburst) enable((*inhigh*) EN_s_axi_arburst) clocked_by(axi_aclk) reset_by (axi_aresetn);\n        method arid(s_axi_arid) enable((*inhigh*) EN_s_axi_arid) clocked_by(axi_aclk) reset_by (axi_aresetn);\n        method arlen(s_axi_arlen) enable((*inhigh*) EN_s_axi_arlen) clocked_by(axi_aclk) reset_by (axi_aresetn);\n        method s_axi_arready arready() clocked_by(axi_aclk) reset_by (axi_aresetn);\n        method arregion(s_axi_arregion) enable((*inhigh*) EN_s_axi_arregion) clocked_by(axi_aclk) reset_by (axi_aresetn);\n        method arsize(s_axi_arsize) enable((*inhigh*) EN_s_axi_arsize) clocked_by(axi_aclk) reset_by (axi_aresetn);\n        method arvalid(s_axi_arvalid) enable((*inhigh*) EN_s_axi_arvalid) clocked_by(axi_aclk) reset_by (axi_aresetn);\n        method awaddr(s_axi_awaddr) enable((*inhigh*) EN_s_axi_awaddr) clocked_by(axi_aclk) reset_by (axi_aresetn);\n        method awburst(s_axi_awburst) enable((*inhigh*) EN_s_axi_awburst) clocked_by(axi_aclk) reset_by (axi_aresetn);\n        method awid(s_axi_awid) enable((*inhigh*) EN_s_axi_awid) clocked_by(axi_aclk) reset_by (axi_aresetn);\n        method awlen(s_axi_awlen) enable((*inhigh*) EN_s_axi_awlen) clocked_by(axi_aclk) reset_by (axi_aresetn);\n        method s_axi_awready awready() clocked_by(axi_aclk) reset_by (axi_aresetn);\n        method awregion(s_axi_awregion) enable((*inhigh*) EN_s_axi_awregion) clocked_by(axi_aclk) reset_by (axi_aresetn);\n        method awsize(s_axi_awsize) enable((*inhigh*) EN_s_axi_awsize) clocked_by(axi_aclk) reset_by (axi_aresetn);\n        method awvalid(s_axi_awvalid) enable((*inhigh*) EN_s_axi_awvalid) clocked_by(axi_aclk) reset_by (axi_aresetn);\n        method s_axi_bid bid() clocked_by(axi_aclk) reset_by (axi_aresetn);\n        method bready(s_axi_bready) enable((*inhigh*) EN_s_axi_bready) clocked_by(axi_aclk) reset_by (axi_aresetn);\n        method s_axi_bresp bresp() clocked_by(axi_aclk) reset_by (axi_aresetn);\n        method s_axi_bvalid bvalid() clocked_by(axi_aclk) reset_by (axi_aresetn);\n        method s_axi_rdata rdata() clocked_by(axi_aclk) reset_by (axi_aresetn);\n        method s_axi_rid rid() clocked_by(axi_aclk) reset_by (axi_aresetn);\n        method s_axi_rlast rlast() clocked_by(axi_aclk) reset_by (axi_aresetn);\n        method rready(s_axi_rready) enable((*inhigh*) EN_s_axi_rready) clocked_by(axi_aclk) reset_by (axi_aresetn);\n        method s_axi_rresp rresp() clocked_by(axi_aclk) reset_by (axi_aresetn);\n        method s_axi_rvalid rvalid() clocked_by(axi_aclk) reset_by (axi_aresetn);\n        method wdata(s_axi_wdata) enable((*inhigh*) EN_s_axi_wdata) clocked_by(axi_aclk) reset_by (axi_aresetn);\n        method wlast(s_axi_wlast) enable((*inhigh*) EN_s_axi_wlast) clocked_by(axi_aclk) reset_by (axi_aresetn);\n        method s_axi_wready wready() clocked_by(axi_aclk) reset_by (axi_aresetn);\n        method wstrb(s_axi_wstrb) enable((*inhigh*) EN_s_axi_wstrb) clocked_by(axi_aclk) reset_by (axi_aresetn);\n        method wvalid(s_axi_wvalid) enable((*inhigh*) EN_s_axi_wvalid) clocked_by(axi_aclk) reset_by (axi_aresetn);\n    endinterface\n    interface AprpS_axi_ctl     s_axi_ctl;\n        method araddr(s_axi_ctl_araddr) enable((*inhigh*) EN_s_axi_ctl_araddr) clocked_by(axi_ctl_aclk) reset_by(axi_ctl_aresetn);\n        method s_axi_ctl_arready arready() clocked_by(axi_ctl_aclk) reset_by(axi_ctl_aresetn);\n        method arvalid(s_axi_ctl_arvalid) enable((*inhigh*) EN_s_axi_ctl_arvalid) clocked_by(axi_ctl_aclk) reset_by(axi_ctl_aresetn);\n        method awaddr(s_axi_ctl_awaddr) enable((*inhigh*) EN_s_axi_ctl_awaddr) clocked_by(axi_ctl_aclk) reset_by(axi_ctl_aresetn);\n        method s_axi_ctl_awready awready() clocked_by(axi_ctl_aclk) reset_by(axi_ctl_aresetn);\n        method awvalid(s_axi_ctl_awvalid) enable((*inhigh*) EN_s_axi_ctl_awvalid) clocked_by(axi_ctl_aclk) reset_by(axi_ctl_aresetn);\n        method bready(s_axi_ctl_bready) enable((*inhigh*) EN_s_axi_ctl_bready) clocked_by(axi_ctl_aclk) reset_by(axi_ctl_aresetn);\n        method s_axi_ctl_bresp bresp() clocked_by(axi_ctl_aclk) reset_by(axi_ctl_aresetn);\n        method s_axi_ctl_bvalid bvalid() clocked_by(axi_ctl_aclk) reset_by(axi_ctl_aresetn);\n        method s_axi_ctl_rdata rdata() clocked_by(axi_ctl_aclk) reset_by(axi_ctl_aresetn);\n        method rready(s_axi_ctl_rready) enable((*inhigh*) EN_s_axi_ctl_rready) clocked_by(axi_ctl_aclk) reset_by(axi_ctl_aresetn);\n        method s_axi_ctl_rresp rresp() clocked_by(axi_ctl_aclk) reset_by(axi_ctl_aresetn);\n        method s_axi_ctl_rvalid rvalid() clocked_by(axi_ctl_aclk) reset_by(axi_ctl_aresetn);\n        method wdata(s_axi_ctl_wdata) enable((*inhigh*) EN_s_axi_ctl_wdata) clocked_by(axi_ctl_aclk) reset_by(axi_ctl_aresetn);\n        method s_axi_ctl_wready wready() clocked_by(axi_ctl_aclk) reset_by(axi_ctl_aresetn);\n        method wstrb(s_axi_ctl_wstrb) enable((*inhigh*) EN_s_axi_ctl_wstrb) clocked_by(axi_ctl_aclk) reset_by(axi_ctl_aresetn);\n        method wvalid(s_axi_ctl_wvalid) enable((*inhigh*) EN_s_axi_ctl_wvalid) clocked_by(axi_ctl_aclk) reset_by(axi_ctl_aresetn);\n    endinterface\n    schedule (interrupt.out, intx.msi_grant, intx.msi_request, m_axi.araddr, m_axi.arburst, m_axi.arcache, m_axi.arlen, m_axi.arlock, m_axi.arprot, m_axi.arready, m_axi.arsize, m_axi.arvalid, m_axi.awaddr, m_axi.awburst, m_axi.awcache, m_axi.awlen, m_axi.awlock, m_axi.awprot, m_axi.awready, m_axi.awsize, m_axi.awvalid, m_axi.bready, m_axi.bresp, m_axi.bvalid, m_axi.rdata, m_axi.rlast, m_axi.rready, m_axi.rresp, m_axi.rvalid, m_axi.wdata, m_axi.wlast, m_axi.wready, m_axi.wstrb, m_axi.wvalid, mmcm.lock, msi.enable, msi.vector_num, msi.vector_width, pci.exp_rxn, pci.exp_rxp, pci.exp_txn, pci.exp_txp, s_axi.araddr, s_axi.arburst, s_axi.arid, s_axi.arlen, s_axi.arready, s_axi.arregion, s_axi.arsize, s_axi.arvalid, s_axi.awaddr, s_axi.awburst, s_axi.awid, s_axi.awlen, s_axi.awready, s_axi.awregion, s_axi.awsize, s_axi.awvalid, s_axi.bid, s_axi.bready, s_axi.bresp, s_axi.bvalid, s_axi.rdata, s_axi.rid, s_axi.rlast, s_axi.rready, s_axi.rresp, s_axi.rvalid, s_axi.wdata, s_axi.wlast, s_axi.wready, s_axi.wstrb, s_axi.wvalid, s_axi_ctl.araddr, s_axi_ctl.arready, s_axi_ctl.arvalid, s_axi_ctl.awaddr, s_axi_ctl.awready, s_axi_ctl.awvalid, s_axi_ctl.bready, s_axi_ctl.bresp, s_axi_ctl.bvalid, s_axi_ctl.rdata, s_axi_ctl.rready, s_axi_ctl.rresp, s_axi_ctl.rvalid, s_axi_ctl.wdata, s_axi_ctl.wready, s_axi_ctl.wstrb, s_axi_ctl.wvalid) CF (interrupt.out, intx.msi_grant, intx.msi_request, m_axi.araddr, m_axi.arburst, m_axi.arcache, m_axi.arlen, m_axi.arlock, m_axi.arprot, m_axi.arready, m_axi.arsize, m_axi.arvalid, m_axi.awaddr, m_axi.awburst, m_axi.awcache, m_axi.awlen, m_axi.awlock, m_axi.awprot, m_axi.awready, m_axi.awsize, m_axi.awvalid, m_axi.bready, m_axi.bresp, m_axi.bvalid, m_axi.rdata, m_axi.rlast, m_axi.rready, m_axi.rresp, m_axi.rvalid, m_axi.wdata, m_axi.wlast, m_axi.wready, m_axi.wstrb, m_axi.wvalid, mmcm.lock, msi.enable, msi.vector_num, msi.vector_width, pci.exp_rxn, pci.exp_rxp, pci.exp_txn, pci.exp_txp, s_axi.araddr, s_axi.arburst, s_axi.arid, s_axi.arlen, s_axi.arready, s_axi.arregion, s_axi.arsize, s_axi.arvalid, s_axi.awaddr, s_axi.awburst, s_axi.awid, s_axi.awlen, s_axi.awready, s_axi.awregion, s_axi.awsize, s_axi.awvalid, s_axi.bid, s_axi.bready, s_axi.bresp, s_axi.bvalid, s_axi.rdata, s_axi.rid, s_axi.rlast, s_axi.rready, s_axi.rresp, s_axi.rvalid, s_axi.wdata, s_axi.wlast, s_axi.wready, s_axi.wstrb, s_axi.wvalid, s_axi_ctl.araddr, s_axi_ctl.arready, s_axi_ctl.arvalid, s_axi_ctl.awaddr, s_axi_ctl.awready, s_axi_ctl.awvalid, s_axi_ctl.bready, s_axi_ctl.bresp, s_axi_ctl.bvalid, s_axi_ctl.rdata, s_axi_ctl.rready, s_axi_ctl.rresp, s_axi_ctl.rvalid, s_axi_ctl.wdata, s_axi_ctl.wready, s_axi_ctl.wstrb, s_axi_ctl.wvalid);\nendmodule\n"
  },
  {
    "path": "lib/nvme/bsv/Nvme.bsv",
    "content": "// Copyright (c) 2016 Connectal Project\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\nimport Arbitrate::*;\nimport BRAM::*;\nimport BRAMFIFO::*;\nimport BuildVector::*;\nimport Clocks::*;\nimport Connectable::*;\nimport FIFOF::*;\nimport Gearbox::*;\nimport GetPut::*;\nimport Probe::*;\nimport StmtFSM::*;\nimport Vector::*;\n\nimport AddressGenerator::*;\nimport AxiBits::*;\nimport AxiStream::*;\nimport ConnectalClocks::*;\nimport ConnectalConfig::*;\nimport DefaultValue::*;\nimport GearboxGetPut::*;\nimport GetPutWithClocks::*;\nimport HostInterface::*;\nimport MemReadEngine::*;\nimport ConnectalMemTypes::*;\nimport PhysMemSlaveFromBram::*;\nimport Pipe::*;\nimport TraceMemClient::*;\nimport XilinxCells::*;\n\n`include \"ConnectalProjectConfig.bsv\"\n\n`ifndef PCIE3\nimport AxiPcieRootPort::*;\n`else\nimport AxiPcie3RootPort::*;\n`endif\nimport NvmeIfc::*;\nimport NvmePins::*;\n\n`ifndef TOP_SOURCES_PORTAL_CLOCK\nimport ConnectalBramFifo::*;\n`else\nimport BRAMFIFO::*;\nmodule mkDualClockBramFIFOF#(Clock clock1, Reset reset1, Clock clock2, Reset reset2)(FIFOF#(a))\n   provisos (Bits#(a, asz), Add#(1, a__, asz));\n   FIFOF#(a) fifo <- mkSizedBRAMFIFOF(512, clocked_by clock1, reset_by reset1);\n   return fifo;\nendmodule\n`endif\n\n\nfunction PipeIn#(t) sinkPipe();\n   return (interface PipeIn#(a);\n\t      method Action enq(t v); endmethod\n\t      method Bool notFull(); return False; endmethod\n\t   endinterface);\nendfunction\n\ninstance ArbRequestTC#(BRAMRequest#(a,b));\n   function Bool isReadRequest(BRAMRequest#(a,b) x); return !x.write; endfunction\n   function Bool isWriteRequest(BRAMRequest#(a,b) x); return x.write; endfunction\nendinstance\n\ninterface Nvme;\n   interface NvmeRequest request;\n   interface NvmeDriverRequest driverRequest;\n   interface MemServerPortalRequest bramRequest;\n   interface NvmeTrace trace;\n   interface NvmePins pins;\n`ifndef NVME_ACCELERATOR_INTERFACE\n   interface PipeIn#(MemData#(PcieDataBusWidth)) dataToNvme;\n   interface PipeOut#(MemData#(PcieDataBusWidth)) dataFromNvme;\n`endif\n   interface Vector#(1, MemReadClient#(DataBusWidth)) dmaReadClient;\n   interface Vector#(1, MemWriteClient#(DataBusWidth)) dmaWriteClient;\n`ifdef TOP_SOURCES_PORTAL_CLOCK\n   interface Clock portalClockSource;\n`endif\nendinterface\n\nmodule mkNvme#(NvmeIndication nvmeInd, NvmeDriverIndication driverInd, NvmeTrace trace, MemServerPortalIndication bramIndication)(Nvme);\n   let clock <- exposeCurrentClock;\n   let reset <- exposeCurrentReset;\n   let refclk_p <- mkB2C1();\n   let refclk_n <- mkB2C1();\n   let pcie_clk_100mhz_buf <- mkClockIBUFDS_GTE2(\n`ifdef ClockDefaultParam\n       defaultValue,\n`endif\n      True, refclk_p.c, refclk_n.c);\n`ifndef TOP_SOURCES_PORTAL_CLOCK\n   let axiClockB2C    <- mkB2C1();\n   let axiCtlClockB2C <- mkB2C1();\n   let axiClock = axiClockB2C.c;\n   let axiCtlClock = axiClock; //axiCtlClockB2C.c;\n   let axiReset <- mkSyncReset(10, reset, axiClock);\n   let axiCtlReset = axiReset; //mkSyncReset(10, reset, axiCtlClock);\n`else\n   let axiClock = clock;\n   let axiCtlClock = clock;\n   let axiReset = reset;\n   let axiCtlReset = reset;\n`endif\n\n   Reg#(Bool) inSetup <- mkReg(False);\n\n   Reg#(Bit#(8)) sysResetCount <- mkReg(0);\n   Reg#(Bit#(8)) nvmeResetCount <- mkReg(0);\n`ifndef PCIE3\n   let axiRootPort <- mkAPRP(pcie_clk_100mhz_buf, reset, axiClock, axiReset, axiCtlClock, axiCtlReset);\n`ifndef TOP_SOURCES_PORTAL_CLOCK\n   let axiClockC2B <- mkC2B(axiRootPort.axi.aclk_out);\n   rule rl_connect_clocks;\n      axiClockB2C.inputclock(axiClockC2B.o);\n      axiCtlClockB2C.inputclock(axiClockC2B.o);\n   endrule\n`endif\n`else\n   let sys_rst_n <- mkReset(10, True, clock);\n   let nvme_rst_n <- mkReset(10, True, clock);\n   let axiRootPort <- mkAPRP(axiClock, axiReset, pcie_clk_100mhz_buf, sys_rst_n.new_rst);\n   let axiClockC2B <- mkC2B(axiRootPort.axi.aclk);\n   rule rl_connect_clocks;\n      axiClockB2C.inputclock(axiClockC2B.o);\n      axiCtlClockB2C.inputclock(axiClockC2B.o);\n   endrule\n   rule rl_sys_reset if (sysResetCount > 0);\n      sys_rst_n.assertReset();\n      sysResetCount <= sysResetCount - 1;\n   endrule\n   rule rl_nvme_reset if (nvmeResetCount > 0);\n      nvme_rst_n.assertReset();\n      nvmeResetCount <= nvmeResetCount - 1;\n   endrule\n`endif\n\n   FIFOF#(Bit#(32)) dfifoCtl <- mkFIFOF();\n   Axi4SlaveBits#(32,PcieDataBusWidth,4,Empty) axiRootPortSlave = toAxi4SlaveBits(axiRootPort.s_axi);\n   Axi4SlaveLiteBits#(32,32)                axiRootPortSlaveCtl = toAxi4SlaveBits(axiRootPort.s_axi_ctl);\n   PhysMemSlave#(32,PcieDataBusWidth)       axiRootPortMemSlave <- mkPhysMemSlave(axiRootPortSlave, clocked_by axiClock, reset_by axiReset);\n   PhysMemSlave#(32,32)                  axiRootPortMemSlaveCtl <- mkPhysMemSlave(axiRootPortSlaveCtl, clocked_by axiCtlClock, reset_by axiCtlReset);\n\n   FIFOF#(PhysMemRequest#(32,PcieDataBusWidth)) araddrFifo <- mkFIFOF();\n   FIFOF#(PhysMemRequest#(32,PcieDataBusWidth)) awaddrFifo <- mkFIFOF();\n   FIFOF#(MemData#(PcieDataBusWidth))           rdataFifo <- mkFIFOF();\n   FIFOF#(MemData#(PcieDataBusWidth))           wdataFifo <- mkFIFOF();\n   FIFOF#(Bit#(6))                           doneFifo <- mkFIFOF();\n\n`ifndef PCIE\n   let axiRootArAddrCnx <- mkConnection(toGet(araddrFifo), axiRootPortMemSlave.read_server.readReq);\n   let axiRootAwAddrCnx <- mkConnection(toGet(awaddrFifo), axiRootPortMemSlave.write_server.writeReq);\n   let axiRootRDataCnx  <- mkConnection(axiRootPortMemSlave.read_server.readData, toPut(rdataFifo));\n   let axiRootWDataCnx  <- mkConnection(toGet(wdataFifo), axiRootPortMemSlave.write_server.writeData);\n   let axiRootWDoneCnx   <- mkConnection(axiRootPortMemSlave.write_server.writeDone, toPut(doneFifo));\n`else\n   let axiRootArAddrCnx <- GetPutWithClocks::mkConnectionWithClocks(clock, reset, axiClock, axiReset, toPipeOut(araddrFifo), axiRootPortMemSlave.read_server.readReq);\n   let axiRootAwAddrCnx <- GetPutWithClocks::mkConnectionWithClocks(clock, reset, axiClock, axiReset, toPipeOut(awaddrFifo), axiRootPortMemSlave.write_server.writeReq);\n   let axiRootRDataCnx  <- GetPutWithClocks::mkConnectionWithClocks(axiClock, axiReset, clock, reset, axiRootPortMemSlave.read_server.readData, toPipeIn(rdataFifo));\n   let axiRootWDataCnx  <- GetPutWithClocks::mkConnectionWithClocks(clock, reset, axiClock, axiReset, toPipeOut(wdataFifo), axiRootPortMemSlave.write_server.writeData);\n   let axiRootWDoneCnx   <- GetPutWithClocks::mkConnectionWithClocks(axiClock, axiReset, clock, reset, axiRootPortMemSlave.write_server.writeDone, toPipeIn(doneFifo));\n`endif\n\n   rule rl_rdata if (!inSetup);\n      let rdata <- toGet(rdataFifo).get();\n      if (rdata.tag == 0)\n\t driverInd.readDone(truncate(rdata.data));\n   endrule\n\n   rule rl_writeDone if (!inSetup);\n      let tag <- toGet(doneFifo).get();\n      if (tag == 0)\n\t driverInd.writeDone();\n   endrule\n\n   FIFOF#(PhysMemRequest#(32,32)) araddrFifoCtl <- mkFIFOF();\n   FIFOF#(PhysMemRequest#(32,32)) awaddrFifoCtl <- mkFIFOF();\n   FIFOF#(MemData#(32))           rdataFifoCtl <- mkFIFOF();\n   FIFOF#(MemData#(32))           wdataFifoCtl <- mkFIFOF();\n   FIFOF#(Bit#(6))                doneFifoCtl <- mkFIFOF();\n\n`ifndef PCIE\n   let axiCtlArAddrCnx <- mkConnection(toGet(araddrFifoCtl), axiRootPortMemSlaveCtl.read_server.readReq);\n   let axiCtlAwAddrCnx <- mkConnection(toGet(awaddrFifoCtl), axiRootPortMemSlaveCtl.write_server.writeReq);\n   let axiCtlRDataCnx  <- mkConnection(axiRootPortMemSlaveCtl.read_server.readData, toPut(rdataFifoCtl));\n   let axiCtlWDataCnx  <- mkConnection(toGet(wdataFifoCtl), axiRootPortMemSlaveCtl.write_server.writeData);\n   let axiCtlDoneCnx   <- mkConnection(axiRootPortMemSlaveCtl.write_server.writeDone, toPut(doneFifoCtl));\n`else\n   let axiCtlArAddrCnx <- GetPutWithClocks::mkConnectionWithClocks(clock, reset, axiClock, axiReset, toPipeOut(araddrFifoCtl), axiRootPortMemSlaveCtl.read_server.readReq);\n   let axiCtlAwAddrCnx <- GetPutWithClocks::mkConnectionWithClocks(clock, reset, axiClock, axiReset, toPipeOut(awaddrFifoCtl), axiRootPortMemSlaveCtl.write_server.writeReq);\n   let axiCtlRDataCnx  <- GetPutWithClocks::mkConnectionWithClocks(axiClock, axiReset, clock, reset, axiRootPortMemSlaveCtl.read_server.readData, toPipeIn(rdataFifoCtl));\n   let axiCtlWDataCnx  <- GetPutWithClocks::mkConnectionWithClocks(clock, reset, axiClock, axiReset, toPipeOut(wdataFifoCtl), axiRootPortMemSlaveCtl.write_server.writeData);\n   let axiCtlWDoneCnx   <- GetPutWithClocks::mkConnectionWithClocks(axiClock, axiReset, clock, reset, axiRootPortMemSlaveCtl.write_server.writeDone, toPipeIn(doneFifoCtl));\n`endif\n\n   rule rl_rdata_ctl if (!inSetup);\n      let rdata <- toGet(rdataFifoCtl).get();\n      driverInd.readDone(extend(rdata.data));\n   endrule\n\n   rule rl_writeDone_ctl if (!inSetup);\n      let tag <- toGet(doneFifoCtl).get();\n      driverInd.writeDone();\n   endrule\n\n   let requestSize = 64;\n   let responseSize = 16;\n   let bytesPerEntry = valueOf(TDiv#(PcieDataBusWidth,8));\n   let wordsPerEntry = valueOf(TDiv#(PcieDataBusWidth,32));\n\n   BRAM_Configure bramConfig = defaultValue;\n   bramConfig.latency = 2;\n   bramConfig.memorySize = 4096*4/bytesPerEntry; // 4 pages\n   BRAM2Port#(Bit#(32),Bit#(PcieDataBusWidth)) bram <- mkBRAM2Server(bramConfig);\n\n   let arbIfc <- mkFixedPriority();\n   Arbiter#(4, BRAMRequest#(Bit#(32),Bit#(PcieDataBusWidth)),Bit#(PcieDataBusWidth)) arbiter <- mkArbiter(arbIfc,2);\n   let arbCnx <- mkConnection(arbiter.master, bram.portB);\n\n   MemServer#(PcieDataBusWidth)            bramMemA <- mkMemServerFromBram(bram.portA);\n   PhysMemSlave#(32,PcieDataBusWidth)      bramMemB <- mkPhysMemSlaveFromBram(arbiter.users[0]);\n   MemServerPortal          bramMemServerPortal <- mkPhysMemSlavePortal(bramMemB,bramIndication);\n\n   let portB1 = arbiter.users[1];\n   let portB2 = arbiter.users[2];\n   let portB3 = arbiter.users[3];\n\n// was 18\n   Vector#(1,Tuple3#(Bit#(2), Bit#(32),Bit#(PcieDataBusWidth))) initCtlValues = vec( \n      //  tuple3(0, 32'h00000004, 'h00000147)\n      // ,tuple3(0, 32'h00000018, 'h00070100)\n      // ,tuple3(0, 32'h00000010, 'h00000000) // Bridge BAR0\n      // ,tuple3(0, 32'h00000014, 'h00000000) // Bridge BAR1\n      // ,tuple3(0, 32'h00100004, 'h00000147) // enable card I/O, Memory, bus master, parity and SERR\n      // ,tuple3(0, 32'h00100010, 'h00000000) // Card BAR0\n      // ,tuple3(0, 32'h00100014, 'h00000000) // Card BAR1\n      // ,tuple3(0, 32'h00100018, 'h02200000) // Card BAR2\n      // ,tuple3(0, 32'h0010001c, 'h00000000) // Card BAR3\n      // ,tuple3(0, 32'h00000148, 'h00000001) // enable bridge\n      // ,tuple3(0, 32'h00000140, 'h00010000) // enable bridge\n\n      // ,tuple3(1, 32'h00000014, 'h00460000)\n      // ,tuple3(1, 0, 0) // skip the rest for now\n      // ,tuple3(1, 32'h00000028, 'h00000000) // admin submission queue in BRAM\n      // ,tuple3(1, 32'h00000030, 'h00000000) // admin response queue in BRAM\n      // ,tuple3(1, 32'h00000024, 'h003f003f) // queue sizes?\n      // ,tuple3(1, 32'h00000014, 'h00460001) // enable the admin queues\n      //,\n      tuple3(1, 0, 0));\n\n   let index <- mkReg(0);\n   let kindReg <- mkReg(0);\n   let addrReg <- mkReg(0);\n   let dataReg <- mkReg(0);\n   let setupFsm <- mkFSMWithPred(seq\n      index <= 0;\n      while (tpl_2(initCtlValues[index]) != 32'h0) seq\n\t action\n\t    match { .kind, .addr, .data } = initCtlValues[index];\n\t    kindReg <= kind;\n\t    addrReg <= addr;\n\t    dataReg <= data;\n\t endaction\n\t action\n\t    let kind = kindReg;\n\t    let addr = addrReg;\n\t    let data = dataReg;\n      \n\t    if (kind == 0) awaddrFifoCtl.enq(PhysMemRequest {addr: addr, burstLen: 4, tag: index });\n\t    if (kind == 1) awaddrFifo.enq(PhysMemRequest {addr: addr, burstLen: 4, tag: index });\n\t    if (kind == 2) portB3.request.put(BRAMRequest { address: addr, write: True, responseOnWrite: True, datain: data });\n\t endaction\n\t action\n\t    //match { .kind, .addr, .data } = initCtlValues[index];\n\t    let kind = kindReg;\n\t    let addr = addrReg;\n\t    let data = dataReg;\n\t    if (kind == 0) wdataFifoCtl.enq(MemData {data: truncate(data), tag: index, last: True });\n\t    if (kind == 1) wdataFifo.enq(MemData {data: data, tag: index, last: True });\n\t endaction\n\t action\n\t    //match { .kind, .addr, .data } = initCtlValues[index];\n\t    let kind = kindReg;\n\t    let addr = addrReg;\n\t    let data = dataReg;\n\t    let tag = 0;\n\t    if (kind == 0) doneFifoCtl.deq();\n\t    if (kind == 1) doneFifo.deq();\n\t    if (kind == 2) \n\t       tag <- portB3.response.get();\n\t    index <= index + 1;\n\t endaction\n      endseq\n      driverInd.setupDone();\n      inSetup <= False;\n      endseq,\n      inSetup);\n\n   Axi4MasterBits#(32,PcieDataBusWidth,MemTagSize,Empty) m_axi_mm = toAxi4MasterBits(axiRootPort.m_axi);\n   let getObjId = (interface GetObjId;\n\t\t   method SGLId objId(Bit#(32) addr); return extend(addr[31:24]); endmethod\n\t\t   method Bit#(MemOffsetSize) addr(Bit#(32) axiAddr); return extend(axiAddr[23:0]); endmethod\n\t\t   endinterface);\n   let memReadClient  <- mkMemReadClient(getObjId, m_axi_mm);\n   let memWriteClient <- mkMemWriteClient(getObjId, m_axi_mm);\n\n   Reg#(Bool) traceEnabled <- mkReg(False);\n\n   FIFOF#(Tuple4#(DmaChannel,Bool,MemRequest,Bit#(32))) traceFifo <- mkSizedBRAMFIFOF(128);\n   PipeIn#(Tuple4#(DmaChannel,Bool,MemRequest,Bit#(32))) tracePipe = traceEnabled ? toPipeIn(traceFifo) : sinkPipe();\n   FIFOF#(Tuple4#(DmaChannel,Bool,MemData#(PcieDataBusWidth),Bit#(32))) traceDataFifo <- mkSizedBRAMFIFOF(128);\n   PipeIn#(Tuple4#(DmaChannel,Bool,MemData#(PcieDataBusWidth),Bit#(32))) traceDataPipe = traceEnabled ? toPipeIn(traceDataFifo) : sinkPipe();\n   FIFOF#(Tuple2#(DmaChannel,Bit#(32)))                              traceDoneFifo <- mkSizedBRAMFIFOF(128);\n   PipeIn#(Tuple2#(DmaChannel,Bit#(32)))                             traceDonePipe = traceEnabled ? toPipeIn(traceDoneFifo) : sinkPipe();\n\n   rule rl_trace1;\n      match { .chan, .write, .req, .timestamp } <- toGet(traceFifo).get();\n      trace.traceDmaRequest(chan, write, truncate(req.sglId), truncate(req.offset), extend(req.burstLen), extend(req.tag), timestamp);\n   endrule\n   rule rl_trace_data;\n      match { .chan, .write, .md, .timestamp } <- toGet(traceDataFifo).get();\n      trace.traceDmaData(chan, write, unpack(md.data), md.last, extend(md.tag), timestamp);\n   endrule\n   rule rl_trace_done;\n      match { .chan, .timestamp } <- toGet(traceDoneFifo).get();\n      trace.traceDmaDone(chan, 0, timestamp);\n   endrule\n\n   let traceReadClient <- mkTraceReadClient(tracePipe,traceDataPipe,DMA_TX,memReadClient);\n   let traceWriteClient <- mkTraceWriteClient(tracePipe,traceDataPipe,traceDonePipe,DMA_RX,memWriteClient);\n   let traceClient = (interface MemClient#(PcieDataBusWidth);\n\t\t\t interface readClient = traceReadClient;\n\t\t\t interface writeClient = traceWriteClient;\n\t\t      endinterface);\n\n   SplitMemServer#(PcieDataBusWidth) splitter <- mkSplitMemServer();\n   MemServerGearbox#(PcieDataBusWidth,DataBusWidth) axiGearbox <- mk1toNMemServerGearbox();\n   let gearboxCnx <- mkConnection(splitter.busClient, axiGearbox.server);\n\n   Reg#(Bit#(16)) requestId <- mkReg(0);\n   Reg#(Bit#(16)) responseId <- mkReg(0);\n   Reg#(Bit#(16)) requestQueueEntryCount <- mkReg(8);\n   Reg#(Bool) requestSlotAvailable <- mkReg(True);\n   Reg#(Bool) requestInProgress <- mkReg(True);\n   Reg#(Vector#(16,Bit#(32))) ioCommand <- mkReg(unpack(0));\n   Reg#(Bit#(32)) requestStartTimestamp <- mkReg(0);\n\n   FIFOF#(NvmeIoCommand) ioCommandFifo <- mkFIFOF();\n   FIFOF#(NvmeIoCommand) ioSegmentFifo <- mkFIFOF(); // max request size 32\n`ifdef NVME_ACCELERATOR_INTERFACE\n   FIFOF#(NvmeIoCommand) ioCommandFifoAccel <- mkFIFOF();\n   FIFOF#(NvmeIoResponse) ioResponseFifoAccel <- mkFIFOF();\n`endif\n\n   FIFOF#(Bit#(1)) ioCommandSourceFifo <- mkFIFOF();\n   FIFOF#(Bit#(1)) ioSegmentSourceFifo <- mkFIFOF();\n   FIFOF#(Bit#(1)) ioResponseSourceFifo <- mkSizedFIFOF(8);\n\n   Reg#(Bit#(32)) cycles <- mkReg(0);\n   rule rl_cycles;\n      cycles <= cycles + 1;\n   endrule\n\n   IteratorWithContext#(Bit#(32),NvmeIoCommand) ioIterator <- mkIteratorWithContext();\n   let segmenterFsm <- mkAutoFSM(seq\n      while (True) seq\n\t action\n\t    NvmeIoCommand command = unpack(0);\n\t    Bit#(1) commandSource = 0;\n\t    Bool commandValid = False;\n\t    if (ioCommandFifo.notEmpty) begin\n\t       command <- toGet(ioCommandFifo).get();\n\t       commandValid = True;\n\t       commandSource = 0;\n\t    end\n`ifdef NVME_ACCELERATOR_INTERFACE\n\t    else if (ioCommandFifoAccel.notEmpty) begin\n\t       command <- toGet(ioCommandFifoAccel).get();\n\t       commandValid = True;\n\t       commandSource = 1;\n\t    end\n`endif\n\t    if (commandValid) begin\n\t       ioIterator.start(IteratorConfig {xbase: 0,\n\t\t\t\t\t\txlimit: command.numBlocks,\n\t\t\t\t\t\txstep: `BlocksPerRequest},\n\t\t\t\tcommand);\n\t       ioCommandSourceFifo.enq(commandSource);\n\t    end\n\t endaction\n         while (ioIterator.ivpipe.notEmpty()) seq\n\t    action\n\t       let v <- toGet(ioIterator.ivpipe).get();\n\t       let command = v.ctxt;\n\t       if (v.last) begin\n\t\t  command.numBlocks = command.numBlocks - v.value; //fixme\n\t\t  ioCommandSourceFifo.deq();\n\t       end\n\t       else begin\n\t\t  command.numBlocks = `BlocksPerRequest;\n\t       end\n\t       command.startBlock = command.startBlock + extend(v.value);\n\t       ioSegmentFifo.enq(command);\n\t       ioSegmentSourceFifo.enq(ioCommandSourceFifo.first);\n\n\t    endaction\n\t endseq\n      endseq // while True\n      endseq);\n\n   Reg#(Bit#(32)) i <- mkReg(0);\n\n   let requestFsm <- mkAutoFSM(seq\n      while (True) seq\n\t action\n\t    let req <- toGet(ioSegmentFifo).get();\n\t    let source <- toGet(ioSegmentSourceFifo).get();\n\t    Vector#(16,Bit#(32)) command = unpack(0);\n\t    command[0] = { requestId, req.flags, req.opcode };\n\t    command[1] = 1; // nsid\n\t    // prp1: send data to fifo\n\t    command[6] = 32'h30000000;\n\t    // p2p2: read PRP list from BRAM at offset 0x2000\n\t    command[8] = 32'h20002000;\n\t    command[10] = req.startBlock[31:0];\n\t    command[11] = 0; //req.startBlock[63:32];\n\t    command[12] = req.numBlocks-1;\n\t    command[13] = req.dsm;\n\t    //requestId <= req.requestId;\n\t    ioCommand <= command;\n\n\t    requestSlotAvailable <= False;\n\t    ioResponseSourceFifo.enq(source);\n\t endaction\n\n\t while (!requestSlotAvailable) seq // wait for open request slot\n\t    portB1.request.put(BRAMRequest {address: (extend(requestId[2:0]) * fromInteger(responseSize/bytesPerEntry)) + fromInteger(12/bytesPerEntry),\n\t\t\t\t\t    write: False, responseOnWrite: False, datain: 0});\n\t    action\n\t       let response <- portB1.response.get();\n\t       let phase = ~requestId[3];\n\t       if (response[16+(3*32 % valueOf(PcieDataBusWidth))] == ~phase) begin\n\t\t  requestSlotAvailable <= True;\n\t       end\n\t    endaction\n\t endseq // wait for open request slot\n\n\t // write a IO read request to BRAM\n         for (i <= 0; i < fromInteger(requestSize/bytesPerEntry); i <= i + 1) seq\n\t    portB1.request.put(BRAMRequest {address: 'h1000/fromInteger(bytesPerEntry) + (extend(requestId[2:0]) * fromInteger(requestSize/bytesPerEntry)) + i,\n\t\t\t\t\t    write: True, responseOnWrite: False,\n\t\t\t\t\t    datain: truncate(pack(ioCommand) >> (i*fromInteger(valueOf(PcieDataBusWidth)))) });\n         endseq\n\n\t // tell the NVME the new submission queue tail pointer\n\t action\n\t    awaddrFifo.enq(PhysMemRequest { addr: 'h1000 + (2*2+0)*(4<<0), burstLen: 4, tag: 1 });\n\t    wdataFifo.enq(MemData{data: zeroExtend((requestId+1)[2:0]), tag: 1, last: True});\n\t    requestInProgress <= True;\n\t    requestStartTimestamp <= cycles;\n\t    trace.traceData(unpack(0), False, truncate(requestId), cycles);\n\t    requestId <= requestId + 1;\n\t endaction\n      endseq // while True\n      endseq);\n\n   let responseFsm <- mkAutoFSM(seq\n\t // wait for response queue to be updated\n      while (True) seq\n\t requestInProgress <= True;\n\t while (requestInProgress) seq\n\t    portB2.request.put(BRAMRequest {address: (extend(responseId[2:0]) * fromInteger(responseSize/bytesPerEntry)) + fromInteger(12/bytesPerEntry),\n\t\t\t\t\t    write: False, responseOnWrite: False, datain: 0});\n\t    action\n\t       let response <- portB2.response.get();\n\t       let phase = ~responseId[3];\n\t       if (response[16+(3*32 % valueOf(PcieDataBusWidth))] == phase) begin\n\t\t  // if status field written by NVME\n\t\t  let source <- toGet(ioResponseSourceFifo).get();\n`ifdef NVME_ACCELERATOR_INTERFACE\n\t\t  if (source == 1)\n\t\t     ioResponseFifoAccel.enq(NvmeIoResponse {requestId: responseId, statusCode: 'h5a5a, statusCodeType: 'h5a5a });\n\t\t  else\n`endif\n\t\t     nvmeInd.transferCompleted(responseId, truncate(response), cycles - requestStartTimestamp);\n\t\t  requestInProgress <= False;\n\t       end\n\t    endaction\n\t endseq // while requestInProgress\n\n\t // tell the NVME the new response queue head pointer\n\t action\n\t    let nextRequestId = (responseId + 1);\n\t    responseId <= nextRequestId;\n\t    awaddrFifo.enq(PhysMemRequest { addr: 'h1000 + (2*2+1)*(4<<0), burstLen: 4, tag: 1 });\n\t    wdataFifo.enq(MemData{data: zeroExtend((nextRequestId)[2:0]), tag: 1, last: True});\n\t endaction\n      endseq // while True\n      endseq);\n\n   let traceMemCnx <- mkConnection(traceClient, splitter.server);\n   let bramMemCnx  <- mkConnection(splitter.bramClient, bramMemA);\n\n`ifdef NVME_ACCELERATOR_INTERFACE\n   FIFOF#(MemData#(32)) msgToSoftwareFifo <- mkSizedFIFOF(128);\n   FIFOF#(MemData#(32)) msgFromSoftwareFifo <- mkSizedFIFOF(16);\n   AxiStreamSlave#(32)                msgToSoftwareStream <- mkAxiStream(msgToSoftwareFifo);\n   AxiStreamMaster#(32)               msgFromSoftwareStream <- mkAxiStream(msgFromSoftwareFifo);\n   AxiStreamMaster#(PcieDataBusWidth) dataFromNvmeStream <- mkAxiStream(splitter.dataFromNvme);\n   AxiStreamSlave#(PcieDataBusWidth)  dataToNvmeStream   <- mkAxiStream(splitter.dataToNvme);\n   AxiStreamSlave#(SizeOf#(NvmeIoCommand))     requestStream      <- mkAxiStream(mapPipeIn(unpack,toPipeIn(ioCommandFifoAccel)));\n   AxiStreamMaster#(SizeOf#(NvmeIoResponse))   responseStream     <- mkAxiStream(mapPipe(pack,toPipeOut(ioResponseFifoAccel)));\n\n   rule rl_msgToSoftware;\n      let msg <- toGet(msgToSoftwareFifo).get();\n      nvmeInd.msgToSoftware(msg.data, pack(msg.last));\n   endrule\n`endif\n\n   let ltssm <- mkProbe();\n   let userLinkUp <- mkProbe();\n   rule rl_probe;\n      ltssm <= axiRootPort.cfg.ltssm_state();\n      userLinkUp <= axiRootPort.user.link_up();\n   endrule\n\n   //let pcie_sys_reset_n <- mkResetInverter(axiRootPort.axi.aresetn, clocked_by axiClock);\n   let pcie_sys_reset_n <- mkResetInverter(nvme_rst_n.new_rst, clocked_by axiClock);\n\n   interface MemServerPortalRequest bramRequest = bramMemServerPortal.request;\n   interface NvmeDriverRequest driverRequest;\n      method Action reset(Bit#(8) count) if (sysResetCount == 0);\n\t sysResetCount <= count;\n      endmethod\n      method Action nvmeReset(Bit#(8) count) if (nvmeResetCount == 0);\n\t nvmeResetCount <= count;\n      endmethod\n      method Action setup();\n\t inSetup <= True;\n         setupFsm.start();\n      endmethod\n      method Action status();\n`ifndef PCIE3\n\t let mmcmLock = axiRootPort.mmcm.lock();\n\t let ltssm_state = 1'd0;\n`else\n\t let mmcmLock = axiRootPort.user.link_up();\n\t let ltssm_state = axiRootPort.cfg.ltssm_state();\n`endif\n         driverInd.status(mmcmLock, extend(ltssm_state));\n      endmethod\n      method Action trace(Bool enabled);\n\t traceEnabled <= enabled;\n      endmethod\n      method Action read32(Bit#(32) addr) if (!inSetup);\n\t araddrFifo.enq(PhysMemRequest { addr: addr, burstLen: 4, tag: 0 });\n      endmethod\n      method Action write32(Bit#(32) addr, Bit#(32) value) if (!inSetup);\n\t awaddrFifo.enq(PhysMemRequest { addr: addr, burstLen: 4, tag: 0 });\n\t wdataFifo.enq(MemData {data: extend(value), tag: 0, last: True});\n      endmethod\n      method Action read64(Bit#(32) addr) if (!inSetup);\n\t araddrFifo.enq(PhysMemRequest { addr: addr, burstLen: 8, tag: 0 });\n      endmethod\n      method Action write64(Bit#(32) addr, Bit#(64) value) if (!inSetup);\n\t awaddrFifo.enq(PhysMemRequest { addr: addr, burstLen: 8, tag: 0 });\n\t wdataFifo.enq(MemData {data: extend(value), tag: 0, last: True});\n      endmethod\n      method Action write128(Bit#(32) addr, Bit#(64) uvalue, Bit#(64) lvalue) if (!inSetup);\n\t awaddrFifo.enq(PhysMemRequest { addr: addr, burstLen: 16, tag: 0 });\n\t wdataFifo.enq(MemData {data: {uvalue,lvalue}, tag: 0, last: True});\n      endmethod\n      method Action read(Bit#(32) addr) if (!inSetup);\n\t araddrFifo.enq(PhysMemRequest { addr: addr, burstLen: fromInteger(valueOf(TDiv#(DataBusWidth,8))), tag: 0 });\n      endmethod\n      method Action write(Bit#(32) addr, Bit#(DataBusWidth) value) if (!inSetup);\n\t awaddrFifo.enq(PhysMemRequest { addr: addr, burstLen: fromInteger(valueOf(TDiv#(DataBusWidth,8))), tag: 0 });\n\t wdataFifo.enq(MemData {data: extend(value), tag: 0, last: True});\n      endmethod\n\n      method Action readCtl(Bit#(32) addr) if (!inSetup);\n\t araddrFifoCtl.enq(PhysMemRequest { addr: addr, burstLen: 4, tag: 0 });\n      endmethod\n      method Action writeCtl(Bit#(32) addr, Bit#(DataBusWidth) value) if (!inSetup);\n\t awaddrFifoCtl.enq(PhysMemRequest { addr: addr, burstLen: 4, tag: 0 });\n\t wdataFifoCtl.enq(MemData {data: truncate(value), tag: 0, last: True});\n      endmethod\n   endinterface\n   interface NvmeRequest request;\n      method Action startTransfer(Bit#(8) opcode, Bit#(8) flags, Bit#(16) requestId, Bit#(32) startBlock, Bit#(32) numBlocks, Bit#(32) dsm);\n\t ioCommandFifo.enq(NvmeIoCommand{opcode: opcode, flags: flags, requestId: requestId, startBlock: startBlock, numBlocks: numBlocks, dsm: dsm });\n      endmethod\n      method Action msgFromSoftware(Bit#(32) value, Bit#(1) last);\n`ifdef NVME_ACCELERATOR_INTERFACE\n\t msgFromSoftwareFifo.enq(MemData { data:value, last: unpack(last), tag: 0 });\n`endif\n      endmethod\n   endinterface\n`ifdef TOP_SOURCES_PORTAL_CLOCK\n   interface Clock portalClockSource = axiRootPort.axi.aclk_out;\n`endif\n`ifndef NVME_ACCELERATOR_INTERFACE\n   interface PipeOut dataFromNvme = splitter.dataFromNvme;\n   interface PipeOut dataToNvme  = splitter.dataToNvme;\n`endif\n   interface NvmePins pins;\n      interface deleteme_unused_clock = clock;\n      interface pcie_sys_reset_n = pcie_sys_reset_n;\n      interface pcie = axiRootPort.pci;\n      method Action pcie_refclk(Bit#(1) p, Bit#(1) n);\n         refclk_p.inputclock(p);\n         refclk_n.inputclock(n);\n      endmethod\n`ifdef NVME_ACCELERATOR_INTERFACE\n      interface NvmeAccelerator accel;\n\t interface msgToSoftware = msgToSoftwareStream;\n\t interface msgFromSoftware = msgFromSoftwareStream;\n\t interface dataFromNvme = dataFromNvmeStream;\n         interface dataToNvme = dataToNvmeStream;\n         interface request = requestStream;\n         interface response = responseStream;\n         interface clock = clock;\n         interface reset = reset;\n      endinterface\n`endif\n   endinterface\n   interface Vector dmaReadClient = vec(axiGearbox.client.readClient);\n   interface Vector dmaWriteClient = vec(axiGearbox.client.writeClient);\nendmodule\n\ninterface NvmeAcceleratorModule;\n   interface NvmeAccelerator accelerator;\n   interface NvmePins pins;\nendinterface\n\ninstance ToAxi4SlaveBits#(Axi4SlaveBits#(32,PcieDataBusWidth,4,Empty), AprpS_axi);\n   function Axi4SlaveBits#(32,PcieDataBusWidth,4,Empty) toAxi4SlaveBits(AprpS_axi s);\n      return (interface Axi4SlaveBits#(32,PcieDataBusWidth,4,Empty);\n\t method araddr = compose(s.araddr, extend);\n\t method arburst = s.arburst;\n\t //method arcache = s.arcache;\n\t method arid = s.arid;\n\t method arlen = s.arlen;\n\t //method arlock = s.arlock;\n\t //method arprot = s.arprot;\n\t //method arqos = s.arqos;\n\t method arready = s.arready;\n\t method arsize = s.arsize;\n\t method arvalid = s.arvalid;\n\t \n\t method awaddr = compose(s.awaddr, extend);\n\t method awburst = s.awburst;\n\t //method awcache = s.awcache;\n\t method awid = s.awid;\n\t method awlen = s.awlen;\n\t //method awlock = s.awlock;\n\t //method awprot = s.awprot;\n\t //method awqos = s.awqos;\n\t method awready = s.awready;\n\t method awsize = s.awsize;\n\t method awvalid = s.awvalid;\n\n\t method bid = s.bid;\n\t method bready = s.bready;\n\t method bresp = s.bresp;\n\t method bvalid = s.bvalid;\n\t method rdata = s.rdata;\n\t method rid = s.rid;\n\t method rlast = s.rlast;\n\t method rready = s.rready;\n\t method rresp = s.rresp;\n\t method rvalid = s.rvalid;\n\t method wdata = s.wdata;\n\t method wlast = s.wlast;\n\t method wready = s.wready;\n\t method wvalid = s.wvalid;\n\t method wstrb = s.wstrb;\n\t endinterface);\n   endfunction\nendinstance\n\ninstance ToAxi4SlaveBits#(Axi4SlaveLiteBits#(32,32), AprpS_axi_ctl);\n   function Axi4SlaveLiteBits#(32,32) toAxi4SlaveBits(AprpS_axi_ctl s);\n      return (interface Axi4SlaveLiteBits#(32,32);\n\t method araddr = compose(s.araddr, truncate);\n\t method arready = s.arready;\n\t method arvalid = s.arvalid;\n\n\t method awaddr = compose(s.awaddr, truncate);\n\t method awready = s.awready;\n\t method awvalid = s.awvalid;\n\n\t method bready = s.bready;\n\t method bresp = s.bresp;\n\t method bvalid = s.bvalid;\n\t method rdata = s.rdata;\n\t method rready = s.rready;\n\t method rresp = s.rresp;\n\t method rvalid = s.rvalid;\n\t method wdata = s.wdata;\n\t method wready = s.wready;\n\t method Action      wvalid(Bit#(1) v);\n\t    s.wvalid(v);\n\t    s.wstrb(pack(replicate(v)));\n\t endmethod\n\t endinterface);\n   endfunction\nendinstance\n\ninstance ToAxi4MasterBits#(Axi4MasterBits#(32,PcieDataBusWidth,tagWidth,Empty), AprpM_axi);\nfunction Axi4MasterBits#(32,PcieDataBusWidth,tagWidth,Empty) toAxi4MasterBits(AprpM_axi m);\n   return (interface Axi4MasterBits#(32,PcieDataBusWidth,tagWidth,Empty);\n\t   method araddr = m.araddr;\n\t   method arburst = m.arburst;\n\t   method arcache = m.arcache;\n\t   method arlen = m.arlen;\n\t   method arlock = extend(m.arlock);\n\t   method arready = m.arready;\n\t   method arsize = m.arsize;\n\t   method arvalid = m.arvalid;\n\t   method Bit#(1) aresetn(); return 1; endmethod\n\t   method Bit#(tagWidth)     arid(); return 0; endmethod\n\t   method arprot = m.arprot;\n\t   method arqos = 0;\n\t   method awaddr = m.awaddr;\n\t   method awburst = m.awburst;\n\t   method awcache = m.awcache;\n\t   method Bit#(tagWidth)     awid(); return 0; endmethod\n\t   method awlen = m.awlen;\n\t   method awlock = extend(m.awlock);\n\t   method awprot = m.awprot;\n\t   method awready = m.awready;\n\t   method Bit#(4)     awqos(); return 0; endmethod\n\t   method awsize = m.awsize;\n\t   method awvalid = m.awvalid;\n\t   method Action      bid(Bit#(tagWidth) v); endmethod\n\t   method bready = m.bready;\n\t   method bresp = m.bresp;\n\t   method bvalid = m.bvalid;\n\t   method rdata = m.rdata;\n\t   method Action      rid(Bit#(tagWidth) v); endmethod\n\t   method rlast = m.rlast;\n\t   method rready = m.rready;\n\t   method rresp = m.rresp;\n\t   method rvalid = m.rvalid;\n\t   method wdata = m.wdata;\n\t   method Bit#(tagWidth)     wid(); return 0; endmethod\n\t   method wlast = m.wlast;\n\t   method wready = m.wready;\n\t   method wstrb = m.wstrb;\n\t   method wvalid = m.wvalid;\n\t interface extra = ?;   \n\t endinterface);\n   endfunction\nendinstance\n\ninterface SplitMemServer#(numeric type dataBusWidth);\n   interface MemServer#(dataBusWidth) server;\n   interface MemClient#(dataBusWidth) busClient;\n   interface MemClient#(dataBusWidth) bramClient;\n   interface PipeOut#(MemData#(dataBusWidth)) dataFromNvme;\n   interface PipeIn#(MemData#(dataBusWidth))  dataToNvme;\nendinterface\n\n`ifndef DATA_FIFO_DEPTH\ntypedef 16 DataFifoDepth;\n`else\ntypedef `DATA_FIFO_DEPTH DataFifoDepth;\n`endif\n\nmodule mkSplitMemServer(SplitMemServer#(dataBusWidth));\n   let readReqFifo   <- mkFIFOF();\n   let readDataFifo  <- mkFIFOF();\n   let writeReqFifo  <- mkFIFOF();\n   let writeDataFifo <- mkFIFOF();\n   let writeDoneFifo <- mkFIFOF();\n\n   let busReadReqFifo   <- mkFIFOF();\n   let busReadDataFifo  <- mkSizedBRAMFIFOF(16);\n   let busWriteReqFifo  <- mkFIFOF();\n   let busWriteDataFifo <- mkSizedBRAMFIFOF(16);\n   let busWriteDoneFifo <- mkFIFOF();\n\n   let bramReadReqFifo   <- mkFIFOF();\n   let bramReadDataFifo  <- mkSizedBRAMFIFOF(16);\n   let bramWriteReqFifo  <- mkFIFOF();\n   let bramWriteDataFifo <- mkSizedBRAMFIFOF(16);\n   let bramWriteDoneFifo <- mkFIFOF();\n\n   let doneFifo <- mkFIFOF();\n\n   let dataFromNvmeFifo <- mkSizedBRAMFIFOF(valueOf(DataFifoDepth));\n   let dataToNvmeFifo <- mkSizedBRAMFIFOF(valueOf(DataFifoDepth));\n   let readDestFifo <- mkFIFOF();\n   let writeDestFifo <- mkFIFOF();\n\n   rule rl_rd_req;\n      MemRequest req <- toGet(readReqFifo).get();\n      let dest = req.sglId[5:4];\n      if (dest == 2)\n\t bramReadReqFifo.enq(req);\n      else if (dest == 3) begin\n\t // reading from dataToNvmeFifo\n      end\n      else\n\t busReadReqFifo.enq(req);\n      readDestFifo.enq(dest);\n   endrule\n\n   rule rl_rd_data;\n      let dest = readDestFifo.first();\n      MemData#(dataBusWidth) md;\n      if (dest == 2)\n\t md <- toGet(bramReadDataFifo).get();\n      else if (dest == 3)\n\t md <- toGet(dataToNvmeFifo).get();\n      else\n\t md <- toGet(busReadDataFifo).get();\n      if (md.last)\n\t readDestFifo.deq();\n      readDataFifo.enq(md);\n   endrule\n\n   rule rl_wr_req;\n      MemRequest req <- toGet(writeReqFifo).get();\n      Bit#(2) dest = req.sglId[5:4];\n      if (dest == 2)\n\t bramWriteReqFifo.enq(req);\n      else if (dest == 3) begin\n\t // no need to send the request\n      end else\n\t busWriteReqFifo.enq(req);\n      writeDestFifo.enq(dest);\n   endrule\n   \n   rule rl_wr_data;\n      let dest = writeDestFifo.first();\n      MemData#(dataBusWidth) md <- toGet(writeDataFifo).get();\n      if (dest == 2)\n\t bramWriteDataFifo.enq(md);\n      else if (dest == 3)\n\t dataFromNvmeFifo.enq(md);\n      else\n\t busWriteDataFifo.enq(md);\n      if (md.last) begin\n\t writeDestFifo.deq();\n\t doneFifo.enq(tuple2(dest, md.tag));\n      end\n   endrule\n\n   rule rl_wr_done;\n      match { .dest, .tag } <- toGet(doneFifo).get();\n      Bit#(MemTagSize) doneTag;\n      if (dest == 2)\n\t doneTag <- toGet(bramWriteDoneFifo).get();\n      else if (dest == 3)\n\t doneTag = 0;\n      else\n\t doneTag <- toGet(busWriteDoneFifo).get();\n      writeDoneFifo.enq(doneTag);\n   endrule\n\n   interface MemServer server;\n      interface MemReadServer readServer;\n\t interface readReq  = toPut(readReqFifo);\n\t interface readData = toGet(readDataFifo);\n      endinterface\n      interface MemWriteServer writeServer;\n\t interface writeReq  = toPut(writeReqFifo);\n\t interface writeData = toPut(writeDataFifo);\n\t interface writeDone = toGet(writeDoneFifo);\n      endinterface\n   endinterface\n   interface MemClient busClient;\n      interface MemReadClient readClient;\n\t interface readReq  = toGet(busReadReqFifo);\n\t interface Put readData;\n\t    method Action put(MemData#(dataBusWidth) md);\n\t       busReadDataFifo.enq(md);\n\t    endmethod\n\t endinterface\n      endinterface\n      interface MemWriteClient writeClient;\n\t interface writeReq  = toGet(busWriteReqFifo);\n\t interface writeData = toGet(busWriteDataFifo);\n\t interface writeDone = toPut(busWriteDoneFifo);\n      endinterface\n   endinterface\n   interface MemClient bramClient;\n      interface MemReadClient readClient;\n\t interface readReq  = toGet(bramReadReqFifo);\n\t interface readData = toPut(bramReadDataFifo);\n      endinterface\n      interface MemWriteClient writeClient;\n\t interface writeReq  = toGet(bramWriteReqFifo);\n\t interface writeData = toGet(bramWriteDataFifo);\n\t interface writeDone = toPut(bramWriteDoneFifo);\n      endinterface\n   endinterface\n   interface PipeOut dataFromNvme = toPipeOut(dataFromNvmeFifo);\n   interface PipeOut dataToNvme  = toPipeIn(dataToNvmeFifo);\nendmodule\n\ninterface MemServerGearbox#(numeric type serverDataBusWidth, numeric type clientDataBusWidth);\n   interface MemServer#(serverDataBusWidth) server;\n   interface MemClient#(clientDataBusWidth) client;\nendinterface\n\nmodule mk1toNMemServerGearbox(MemServerGearbox#(serverDataBusWidth, clientDataBusWidth))\n   provisos (Div#(serverDataBusWidth,clientDataBusWidth,k)\n\t     ,Mul#(clientDataBusWidth,k,serverDataBusWidth)\n\t     ,Add#(1, a__, TMul#(2, k))\n\t     ,Add#(k, b__, TMul#(2, k))\n\t     ,Add#(1, c__, k)\n\t     );\n   let clock <- exposeCurrentClock();\n   let reset <- exposeCurrentReset();\n\n   let readReqFifo   <- mkFIFOF();\n   let writeReqFifo  <- mkFIFOF();\n   let writeDoneFifo <- mkFIFOF();\n\n   Gearbox#(1,k,MemData#(clientDataBusWidth)) readDataGearbox <- mk1toNGearbox(clock, reset, clock, reset);\n   Gearbox#(k,1,MemData#(clientDataBusWidth)) writeDataGearbox <- mkNto1Gearbox(clock, reset, clock, reset);\n\n   FIFOF#(MemData#(clientDataBusWidth)) busReadDataFifo  <- mkSizedBRAMFIFOF(16);\n   FIFOF#(MemData#(clientDataBusWidth)) busWriteDataFifo <- mkSizedBRAMFIFOF(16);\n\n   rule readDataCnx;\n      let md <- toGet(busReadDataFifo).get();\n      readDataGearbox.enq(vec(md));\n   endrule\n   rule writeDataCnx;\n      let md = writeDataGearbox.first[0];\n      writeDataGearbox.deq();\n      busWriteDataFifo.enq(md);\n   endrule\n\n   interface MemServer server;\n      interface MemReadServer readServer;\n\t interface readReq  = toPut(readReqFifo);\n\t interface Get readData;\n\t    method ActionValue#(MemData#(serverDataBusWidth)) get();\n\t       let mds = readDataGearbox.first();\n\t       readDataGearbox.deq();\n\t       let md = MemData { data: pack(map(memDataData, mds)), tag: mds[0].tag, last: mds[valueOf(k)-1].last };\n\t       return md;\n\t    endmethod\n\t endinterface\n      endinterface\n      interface MemWriteServer writeServer;\n\t interface writeReq  = toPut(writeReqFifo);\n\t interface Put writeData;\n\t    method Action put(MemData#(serverDataBusWidth) md);\n\t       Vector#(k, Bit#(clientDataBusWidth)) datavec = unpack(md.data);\n\t       Vector#(k, MemData#(clientDataBusWidth)) mds = newVector;\n\t       for (Integer i = 0; i < valueOf(k); i = i + 1)\n\t\t  mds[i] = MemData { data: datavec[i], tag: md.tag, last: (i == valueOf(k)-1) && md.last };\n\t       writeDataGearbox.enq(mds);\n\t    endmethod\n\t endinterface\n\t interface writeDone = toGet(writeDoneFifo);\n      endinterface\n   endinterface\n   interface MemClient client;\n      interface MemReadClient readClient;\n\t interface readReq  = toGet(readReqFifo);\n\t interface Put readData;\n\t    method Action put(MemData#(clientDataBusWidth) md);\n\t       busReadDataFifo.enq(md);\n\t       //busReadDataData <= md.data;\n\t       //busReadDataLast <= md.last;\n\t    endmethod\n\t endinterface\n      endinterface\n      interface MemWriteClient writeClient;\n\t interface writeReq  = toGet(writeReqFifo);\n\t interface writeData = toGet(busWriteDataFifo);\n\t interface writeDone = toPut(writeDoneFifo);\n      endinterface\n   endinterface\n\nendmodule\n\n\ninterface MemServerPortal;\n   interface MemServerPortalRequest request;\nendinterface\n\nmodule mkPhysMemSlavePortal#(PhysMemSlave#(32,dataBusWidth) ms, MemServerPortalIndication ind)(MemServerPortal)\n   provisos (Add#(dataBusWidth,7,a__)\n\t     ,Add#(b__,64,dataBusWidth)\n\t     ,Bits#(ConnectalMemTypes::MemData#(dataBusWidth), a__));\n\n   FIFOF#(PhysMemRequest#(32,dataBusWidth)) araddrFifo <- mkFIFOF();\n   FIFOF#(PhysMemRequest#(32,dataBusWidth)) awaddrFifo <- mkFIFOF();\n   FIFOF#(MemData#(dataBusWidth))           rdataFifo <- mkFIFOF();\n   FIFOF#(MemData#(dataBusWidth))           wdataFifo <- mkFIFOF();\n   FIFOF#(Bit#(6))                doneFifo <- mkFIFOF();\n\n   let araddrCnx <- mkConnection(toGet(araddrFifo), ms.read_server.readReq);\n   let awaddrCnx <- mkConnection(toGet(awaddrFifo), ms.write_server.writeReq);\n   let rdataCnx  <- mkConnection(ms.read_server.readData, toPut(rdataFifo));\n   let wdataCnx  <- mkConnection(toGet(wdataFifo), ms.write_server.writeData);\n   let doneCnx   <- mkConnection(ms.write_server.writeDone, toPut(doneFifo));\n\n   rule rl_rdata;\n      let rdata <- toGet(rdataFifo).get();\n      ind.readDone(truncate(rdata.data));\n   endrule\n\n   rule rl_writeDone;\n      let tag <- toGet(doneFifo).get();\n      ind.writeDone();\n   endrule\n\n   interface MemServerPortalRequest request;\n      method Action read(Bit#(32) addr);\n\t araddrFifo.enq(PhysMemRequest { addr: addr, burstLen: fromInteger(valueOf(TDiv#(dataBusWidth,8))), tag: 0 });\n      endmethod\n      method Action write(Bit#(32) addr, Bit#(DataBusWidth) value);\n\t awaddrFifo.enq(PhysMemRequest { addr: addr, burstLen: fromInteger(valueOf(TDiv#(dataBusWidth,8))), tag: 0 });\n\t wdataFifo.enq(MemData {data: extend(value), tag: 0, last: True});\n      endmethod\n   endinterface\nendmodule\n"
  },
  {
    "path": "lib/nvme/bsv/NvmeIfc.bsv",
    "content": "// Copyright (c) 2016 Connectal Project\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\nimport AxiStream::*;\nimport Vector::*;\nimport ConnectalConfig::*;\n`include \"ConnectalProjectConfig.bsv\"\n\ntypedef `PcieDataBusWidth PcieDataBusWidth;\n\ntypedef enum { DMA_RX, DMA_TX, DMA_SG } DmaChannel deriving (Bits,Eq);\n\ninterface MemServerPortalRequest;\n   method Action read(Bit#(32) addr);\n   method Action write(Bit#(32) addr, Bit#(DataBusWidth) data);\nendinterface\n\ninterface MemServerPortalIndication;\n   method Action readDone(Bit#(DataBusWidth) data);\n   method Action writeDone();\nendinterface\n\ntypedef enum {\n    NvmeFlush = 0,\n    NvmeWrite = 1,\n    NvmeRead = 2,\n    NvmeWriteUncorrectable = 4,\n    NvmeCompare = 5,\n    NvmeWriteZeros = 8,\n    NvmeManageDataset = 9,\n    NvmeRegisterReservation = 13,\n    NvmeReportReservation = 14,\n    NvmeAcquireReservation = 17,\n    NvmeReleaseReservation = 21\n   }  NvmeOpcode deriving (Bits,Eq,FShow);\n\ninterface NvmeRequest;\n   method Action startTransfer(Bit#(8) opcode, Bit#(8) flags, Bit#(16) requestId, Bit#(32) startBlock, Bit#(32) numBlocks, Bit#(32) dsm);\n   method Action msgFromSoftware(Bit#(32) value, Bit#(1) last);\nendinterface\n\ninterface NvmeIndication;\n   method Action transferCompleted(Bit#(16) requestId, Bit#(64) sc, Bit#(32) cycles);\n   method Action msgToSoftware(Bit#(32) value, Bit#(1) last);\nendinterface\n\n// internal interfaces\ninterface NvmeDriverRequest;\n   method Action reset(Bit#(8) count);\n   method Action nvmeReset(Bit#(8) count);\n   method Action setup();\n   method Action read32(Bit#(32) addr);\n   method Action write32(Bit#(32) addr, Bit#(32) data);\n   method Action read64(Bit#(32) addr);\n   method Action write64(Bit#(32) addr, Bit#(64) data);\n   method Action read128(Bit#(32) addr);\n   method Action write128(Bit#(32) addr, Bit#(64) udata, Bit#(64) ldata);\n   method Action read(Bit#(32) addr);\n   method Action write(Bit#(32) addr, Bit#(DataBusWidth) data);\n   method Action readCtl(Bit#(32) addr);\n   method Action writeCtl(Bit#(32) addr, Bit#(DataBusWidth) data);\n   method Action status();\n   method Action trace(Bool enabled);\nendinterface\n\ninterface NvmeDriverIndication;\n   method Action setupDone();\n   method Action readDone(Bit#(DataBusWidth) data);\n   method Action writeDone();\n   method Action status(Bit#(1) mmcm_lock, Bit#(32) dataCounter);\n   method Action setupComplete();\nendinterface\n\ninterface NvmeTrace;\n   method Action traceDmaRequest(DmaChannel channel, Bool write, Bit#(16) objId, Bit#(32) offset, Bit#(16) burstLen, Bit#(8) tag, Bit#(32) timestamp);\n   method Action traceDmaData(DmaChannel channel, Bool write, Vector#(TDiv#(PcieDataBusWidth,32),Bit#(32)) data, Bool last, Bit#(8) tag, Bit#(32) timestamp);\n   method Action traceDmaDone(DmaChannel channel, Bit#(8) tag, Bit#(32) timestamp);\n   method Action traceData(Vector#(TDiv#(PcieDataBusWidth,32),Bit#(32)) data, Bool last, Bit#(8) tag, Bit#(32) timestamp);\nendinterface\n\ntypedef struct {\n   Bit#(8)  opcode;\n   Bit#(8)  flags;\n   Bit#(16) requestId;\n   Bit#(32) startBlock;\n   Bit#(32) numBlocks;\n   Bit#(32) dsm;\n   } NvmeIoCommand deriving (Bits);\n\ntypedef struct {\n   Bit#(16) requestId;\n   Bit#(16) statusCode;\n   Bit#(16) statusCodeType;\n   } NvmeIoResponse deriving (Bits);\n\n// these ports exposed to a verilog wrapper module\ninterface NvmeAccelerator;\n   interface AxiStreamMaster#(32) msgFromSoftware;\n   interface AxiStreamSlave#(32) msgToSoftware;\n   interface AxiStreamMaster#(PcieDataBusWidth) dataFromNvme;\n   interface AxiStreamSlave#(PcieDataBusWidth) dataToNvme;\n   interface AxiStreamSlave#(SizeOf#(NvmeIoCommand)) request;\n   interface AxiStreamMaster#(SizeOf#(NvmeIoResponse)) response;\n   interface Clock clock;\n   interface Reset reset;\nendinterface\n\ninterface NvmeAcceleratorClient;\n   interface AxiStreamSlave#(32) msgFromSoftware;\n   interface AxiStreamMaster#(32) msgToSoftware;\n   interface AxiStreamSlave#(PcieDataBusWidth) dataFromNvme;\n   interface AxiStreamMaster#(PcieDataBusWidth) dataToNvme;\n   interface AxiStreamMaster#(SizeOf#(NvmeIoCommand)) request;\n   interface AxiStreamSlave#(SizeOf#(NvmeIoResponse)) response;\nendinterface\n"
  },
  {
    "path": "lib/nvme/bsv/NvmePins.bsv",
    "content": "\n// Copyright (c) 2016 Connectal Project\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\n`include \"ConnectalProjectConfig.bsv\"\n\n`ifndef PCIE3\nimport AxiPcieRootPort::*;\n`else\nimport AxiPcie3RootPort::*;\n`endif\nimport NvmeIfc::*;\n\ninterface NvmePins;\n   interface AprpPci pcie;\n   (* always_ready, always_enabled *)\n   method Action pcie_refclk(Bit#(1) p, Bit#(1) n);\n   interface Clock deleteme_unused_clock;\n   interface Reset pcie_sys_reset_n;\n`ifdef NVME_ACCELERATOR_INTERFACE\n   interface NvmeAccelerator accel;\n`endif\nendinterface\n\nexport NvmePins(..);\n"
  },
  {
    "path": "lib/nvme/cpp/nvme.cpp",
    "content": "#include <stdio.h>\n#include <queue>\n#include \"nvme.h\"\n\n#include <ConnectalProjectConfig.h> // PcieDataBusWidth\n\n// queue size in create I/O completion/submission queue is specified as a 0 based value\nstatic const int queueSizeDelta = 1;\n\nclass NvmeTrace : public NvmeTraceWrapper {\n  std::multimap<int,std::string> traceValues;\npublic:\n    void traceDmaRequest(const DmaChannel chan, const int write, const uint16_t objId, const uint32_t offset, const uint16_t burstLen, const uint8_t tag, const uint32_t timestamp) {\n\tchar msg[128];\n\tsnprintf(msg, sizeof(msg), \"%08x: traceDmaRequest chan=%d write=%d objId=%d offset=%08lx burstLen=%d tag=%x\\n\", timestamp, chan, write, objId, (long)offset, burstLen, tag);\n\ttraceValues.insert(std::pair<int, std::string>(timestamp, std::string(msg)));\n    }\n    void traceDmaData ( const DmaChannel chan, const int write, const bsvvector_Luint32_t_L4 data, const int last, const uint8_t tag, const uint32_t timestamp ) {\n\tchar msg[128];\n\tchar datastr[128];\n\tint offset = 0;\n\tfor (int i = 0; i < PcieDataBusWidth/32; i++)\n\t    offset += snprintf(datastr+offset, sizeof(datastr)-offset-1, \" %08x\", data[i]);\n\n\tsnprintf(msg, sizeof(msg), \"%08x: traceDmaData chan=%d write=%d data=%s last=%d tag=%x\\n\",\n\t\ttimestamp, chan, write, datastr, last, tag);\n\ttraceValues.insert(std::pair<int, std::string>(timestamp, std::string(msg)));\n    }\n    virtual void traceDmaDone ( const DmaChannel chan, const uint8_t tag, const uint32_t timestamp ) {\n\tchar msg[128];\n\tsnprintf(msg, sizeof(msg), \"%08x: traceDmaDone chan=%d tag=%x\\n\", timestamp, chan, tag);\n\ttraceValues.insert(std::pair<int, std::string>(timestamp, std::string(msg)));\n    }\n    void traceData ( const bsvvector_Luint32_t_L4 data, const int last, const uint8_t tag, const uint32_t timestamp ) {\n\tchar datastr[128];\n\tint offset = 0;\n\tfor (int i = 0; i < PcieDataBusWidth/32; i++)\n\t    offset += snprintf(datastr+offset, sizeof(datastr)-offset-1, \" %08x\", data[i]);\n\tchar msg[128];\n\tsnprintf(msg, sizeof(msg), \"traceData data=%s last=%d tag=%x\\n\", datastr, last, tag);\n\ttraceValues.insert(std::pair<int,std::string>(timestamp, std::string(msg)));\n    }\n\n    void dumpTrace() {\n\tint prev = 0;\n\tfprintf(stderr, \"%ld traceValues\\n\", traceValues.size());\n\tfor (auto it=traceValues.begin(); it!=traceValues.end(); ++it) {\n\t    fprintf(stderr, \"%08d %4d %s\", it->first, it->first - prev, it->second.c_str());\n\t    prev = it->first;\n\t}\n\ttraceValues.clear();\n    }\n\n    NvmeTrace(int id, PortalPoller *poller = 0) : NvmeTraceWrapper(id, poller) {\n    }\n};\n\nclass NvmeIndication : public NvmeIndicationWrapper {\n    sem_t sem;\n    pthread_cond_t cond;\n    pthread_mutex_t mutex;\n    std::queue<int> msgs;\n    std::queue<int> lastmsgs;\n    int waiters;\npublic:\n    uint64_t value;\n    uint32_t requests;\n    uint32_t cycles;\n  virtual void msgIn ( const uint32_t value ) {\n  }\n\n  virtual void transferCompleted ( const uint16_t requestId, const uint64_t status, const uint32_t cycles ) {\n      fprintf(stderr, \"%s:%d requestId=%08x status=%08llx cycles=%d\\n\", __FUNCTION__, __LINE__, requestId, (long long)status, cycles);\n      value = status;\n      this->requests++;\n      this->cycles += cycles;\n      sem_post(&sem);\n    }\n\n    virtual void msgToSoftware ( const uint32_t msg, uint8_t last ) {\n\tfprintf(stderr, \"%s:%d msg=%x\\n\", __FUNCTION__, __LINE__, msg);\n\tpthread_mutex_lock(&mutex);\n\tmsgs.push(msg);\n\tlastmsgs.push(last);\n\tif (waiters)\n\t    pthread_cond_signal(&cond);\n\tpthread_mutex_unlock(&mutex);\n    }\n    bool messageToSoftware(uint32_t *msg, bool *last, bool nonBlocking=true) {\n\tbool hasMsg = false;\n\tpthread_mutex_lock(&mutex);\n\tdo {\n\t    hasMsg = !msgs.empty();\n\t    if (msgs.size()) {\n\t\tif (*msg)\n\t\t    *msg = msgs.front();\n\t\tif (last)\n\t\t    *last = lastmsgs.front();\n\t\tmsgs.pop();\n\t\tlastmsgs.pop();\n\t    } else if (!nonBlocking) {\n\t\twaiters++;\n\t\tpthread_cond_wait(&cond, &mutex);\n\t\twaiters--;\n\t    }\n\t} while (!hasMsg);\n      pthread_mutex_unlock(&mutex);\n      return hasMsg;\n    }\n    void wait() {\n\tsem_wait(&sem);\n    }\n    NvmeIndication(int id, PortalPoller *poller = 0) : NvmeIndicationWrapper(id, poller), waiters(0), value(0), requests(0), cycles(0) {\n\tsem_init(&sem, 0, 0);\n\tpthread_mutex_init(&mutex, 0);\n\tpthread_cond_init(&cond, 0);\n    }\n  \n};\n\nclass NvmeDriverIndication : public NvmeDriverIndicationWrapper {\n    sem_t sem, wsem;\n    \npublic:\n    uint64_t value;\n    uint32_t requests;\n    uint32_t cycles;\n    virtual void setupDone (  ) {\n\tfprintf(stderr, \"%s:%d\\n\", __FUNCTION__, __LINE__);\n\tsem_post(&sem);\n    }\n\n    virtual void readDone ( const uint64_t data ) {\n\t//fprintf(stderr, \"%s:%d data=%08llx\\n\", __FUNCTION__, __LINE__, (long long)data);\n\tvalue = data;\n\tsem_post(&sem);\n    }\n    virtual void writeDone (  ) {\n\t//fprintf(stderr, \"%s:%d\\n\", __FUNCTION__, __LINE__);\n\tsem_post(&wsem);\n    }\n    virtual void status ( const uint8_t mmcm_lock, const uint32_t counter ) {\n\tfprintf(stderr, \"%s:%d mmcm_lock=%d counter=%d\\n\", __FUNCTION__, __LINE__, mmcm_lock, counter);\n\tsem_post(&sem);\n    }\t\n    virtual void setupComplete() {\n\tfprintf(stderr, \"%s\\n\", __FUNCTION__);\n\tsem_post(&sem);\n    }\n    virtual void strstrLoc ( const uint32_t loc ) {\n\tfprintf(stderr, \"strstr loc loc=%d\\n\", loc);\n    }\n\n  virtual void transferCompleted ( const uint16_t requestId, const uint64_t status, const uint32_t cycles ) {\n      fprintf(stderr, \"%s:%d requestId=%08x status=%08llx cycles=%d\\n\", __FUNCTION__, __LINE__, requestId, (long long)status, cycles);\n      value = status;\n      this->requests++;\n      this->cycles += cycles;\n      sem_post(&sem);\n    }\n\n    void wait() {\n\tsem_wait(&sem);\n    }\n    void waitwrite() {\n\tsem_wait(&wsem);\n    }\n\n    NvmeDriverIndication(int id, PortalPoller *poller = 0) : NvmeDriverIndicationWrapper(id, poller), value(0), requests(0), cycles(0) {\n\tsem_init(&sem, 0, 0);\n\tsem_init(&wsem, 0, 0);\n    }\n  \n};\n\nclass MemServerPortalIndication : public MemServerPortalIndicationWrapper {\n    sem_t sem;\n    sem_t wsem;\npublic:\n    uint64_t value;\n    MemServerPortalIndication(int id, PortalPoller *poller = 0)\n\t: MemServerPortalIndicationWrapper(id, poller) {\n\tsem_init(&sem, 0, 0);\n\tsem_init(&wsem, 0, 0);\n    }\n    virtual void readDone ( const uint64_t data ) {\n\tvalue = data;\n\tsem_post(&sem);\n    }\n    virtual void writeDone (  ) {\n\tsem_post(&wsem);\n    }\n    void wait() {\n\tsem_wait(&sem);\n    }\n    void waitw() {\n\tsem_wait(&sem);\n    }\n};\n\nuint32_t Nvme::readCtl(uint32_t addr)\n{\n    // if (verbose) fprintf(stderr, \"readCtl %x\\n\", addr);\n    driverRequest.readCtl(addr);\n    driverIndication->wait();\n    return (uint32_t)driverIndication->value;\n}\nvoid Nvme::writeCtl(uint32_t addr, uint32_t data)\n{\n    //if (verbose) fprintf(stderr, \"writeCtl %x\\n\", addr);\n    driverRequest.writeCtl(addr, data);\n    driverIndication->waitwrite();\n}\nuint64_t Nvme::read(uint32_t addr)\n{\n    driverRequest.read64(addr);\n    driverIndication->wait();\n    return driverIndication->value;\n}\nvoid Nvme::write(uint32_t addr, uint64_t data)\n{\n    driverRequest.write64(addr, data);\n    driverIndication->waitwrite();\n}\nuint32_t Nvme::read32(uint32_t addr)\n{\n    driverRequest.read32(addr);\n    driverIndication->wait();\n    uint64_t v = driverIndication->value;\n    return (uint32_t)(v >> ((addr & 4) ? 32 : 0));\n    //return v;\n}\nvoid Nvme::write32(uint32_t addr, uint32_t data)\n{\n    uint64_t v = data;\n    //fixme byte enables\n    //driverRequest.write(addr & ~7, v << ((addr & 4) ? 32 : 0));\n    driverRequest.write32(addr, v);\n    driverIndication->waitwrite();\n}\nuint64_t Nvme::read64(uint32_t addr)\n{\n    driverRequest.read64(addr);\n    driverIndication->wait();\n    uint64_t v = driverIndication->value;\n    return v;\n}\nvoid Nvme::write64(uint32_t addr, uint64_t data)\n{\n    uint64_t v = data;\n    //fixme byte enables\n    driverRequest.write64(addr, v);\n    driverIndication->waitwrite();\n}\nvoid Nvme::write128(uint32_t addr, uint64_t udata, uint64_t ldata)\n{\n    driverRequest.write128(addr, udata, ldata);\n    driverIndication->waitwrite();\n}\nuint64_t Nvme::bramRead(uint32_t addr)\n{\n    bram.read(addr);\n    bramIndication->wait();\n    return bramIndication->value;\n}\nvoid Nvme::bramWrite(uint32_t addr, uint64_t data)\n{\n    bram.write(addr, data);\n    //bramIndication->wait();\n}\n\nNvme::Nvme(bool verbose)\n    : Nvme(BlocksPerRequest*512, verbose) {\n  fprintf(stderr, \"Nvme verbose=%d\\n\", verbose);\n}\n\n\nNvme::Nvme(int transferBufferSize, bool verbose)\n    : verbose(verbose)\n    , requestProxy(IfcNames_NvmeRequestS2H)\n    , indication(new NvmeIndication(IfcNames_NvmeIndicationH2S))\n    , driverRequest(IfcNames_NvmeDriverRequestS2H)\n    , driverIndication(new NvmeDriverIndication(IfcNames_NvmeDriverIndicationH2S))\n    , trace(new NvmeTrace(IfcNames_NvmeTraceH2S))\n    , bram(IfcNames_MemServerPortalRequestS2H)\n    , bramIndication(new MemServerPortalIndication(IfcNames_MemServerPortalIndicationH2S))\n    , adminRequestNumber(0)\n    , adminBuffer(4096)\n    , transferBuffer(transferBufferSize)\n    , adminSubmissionQueue(4096)\n    , adminCompletionQueue(4096)\n    , ioSubmissionQueue(ioQueueSize)\n    , ioCompletionQueue(ioQueueSize)\n    , needleBuffer(8192)\n    , mpNextBuffer(8192)\n{\n\t\n    memset(ioRequestNumber, 0, sizeof(ioRequestNumber));\n\n    adminBufferRef = adminBuffer.reference();\n    transferBufferRef = transferBuffer.reference();\n    adminSubmissionQueueRef = adminSubmissionQueue.reference();\n    adminCompletionQueueRef = adminCompletionQueue.reference();\n    if (verbose) fprintf(stderr, \"adminSubmissionQueue %d\\n\", adminSubmissionQueue.reference());\n    if (verbose) fprintf(stderr, \"adminCompletionQueue %d\\n\", adminCompletionQueue.reference());\n    ioSubmissionQueueRef = ioSubmissionQueue.reference();\n    ioCompletionQueueRef = ioCompletionQueue.reference();\n    needleRef = needleBuffer.reference();\n    mpNextRef = mpNextBuffer.reference();\n    if (verbose) fprintf(stderr, \"ioSubmissionQueue %d\\n\", ioSubmissionQueue.reference());\n    if (verbose) fprintf(stderr, \"ioCompletionQueue %d\\n\", ioCompletionQueue.reference());\n    driverRequest.status();\n    driverIndication->wait();\n    driverRequest.trace(0);\n}\n\nvoid Nvme::setup()\n{\n    driverRequest.reset(16);\n    sleep(1);\n    driverRequest.nvmeReset(16);\n    sleep(1);\n    driverRequest.setup();\n    driverIndication->wait();\n\n    if (1) {\n    if (verbose) fprintf(stderr, \"Enabling I/O and Memory, bus master, parity and SERR\\n\");\n    writeCtl(0x004, 0x147);\n    if (verbose) fprintf(stderr, \"bridge control %08x\\n\", readCtl(0x004));\n    // required\n    writeCtl(0x18, 0x00070100);\n    writeCtl(0x10, 0xFFFFFFFF);\n    writeCtl(0x14, 0xFFFFFFFF);\n    fprintf(stderr, \"Root Port BAR0: %08x\\n\", readCtl((0 << 20) + 0x10));\n    fprintf(stderr, \"Root Port BAR1: %08x\\n\", readCtl((0 << 20) + 0x14));\n    writeCtl(0x10, 0x0);\n    writeCtl(0x14, 0x0);\n    if (verbose) fprintf(stderr, \"Enabling card I/O and Memory, bus master, parity and SERR\\n\");\n    writeCtl((1 << 20) + 4, 0x147);\n    if (verbose) fprintf(stderr, \"card bridge control %08x\\n\", readCtl((1 << 20) + 4));\n    if (verbose)\n\tfor (int i = 0; i < 6; i++)\n\t    fprintf(stderr, \"Card BAR%d: %08x\\n\", i, readCtl((1 << 20) + 0x10 + i*4));\n    if (verbose) fprintf(stderr, \"probing card BAR\\n\");\n    for (int i = 0; i < 6; i++) {\n\twriteCtl((1 << 20) + 0x10 + 4*i, 0xffffffff);\n\tif (verbose) fprintf(stderr, \"Card BAR%d: %08x\\n\", i, readCtl((1 << 20) + 0x10 + 4*i));\n    }\n    writeCtl((1 << 20) + 0x10, 0x00000000); // initialize to offset 0\n    writeCtl((1 << 20) + 0x14, 0x00000000);\n    writeCtl((1 << 20) + 0x18, 0x02200000); // BAR2 unused\n    writeCtl((1 << 20) + 0x1c, 0x00000000);\n    writeCtl((1 << 20) + 0x10+5*4, 0); // sata card\n    if (verbose) {\n\tfprintf(stderr, \"reading card BARs\\n\");\n\tfor (int i = 0; i < 6; i++) {\n\t    fprintf(stderr, \"Card BAR%d: %08x\\n\", i, readCtl((1 << 20) + 0x10 + 4*i));\n\t}\n    }\n\n    fprintf(stderr, \"PHY Status/Control: %08x\\n\", readCtl(0x144));\n    fprintf(stderr, \"Configuration Control (should be zero): %08x\\n\", readCtl(0x168));\n    for (int i = 0; i < 6; i++)\n\tfprintf(stderr, \"AXI Bar%d %08x.%08x\\n\", i, readCtl(0x208 + i*8), readCtl(0x208 + i*8+4));\n    if (verbose) fprintf(stderr, \"Enabling bridge\\n\");\n    fprintf(stderr, \"0x148: %08x\\n\", readCtl(0x148));\n    writeCtl(0x140, 0x00000100);\n    fprintf(stderr, \"Bus Location Register: %08x\\n\", readCtl(0x140));\n    writeCtl(0x148, 1);\n    fprintf(stderr, \"0x148: %08x\\n\", readCtl(0x148));\n\n    fprintf(stderr, \"before: contents of 0x30 %08lx.%08lx\\n\", read64(0x38), read64(0x30));\n    write128(0x30, 0x11ffeeddccbbaa99l, 0x8877665544332211);\n    fprintf(stderr, \"after:  contents of 0x30 %08lx.%08lx\\n\", read64(0x38), read64(0x30));\n    write64(0x30, 0x8877665544332211);\n    write64(0x38, 0x11ffeeddccbbaa99l);\n    fprintf(stderr, \"after2: contents of 0x30 %08lx.%08lx\\n\", read64(0x38), read64(0x30));\n    write64(0x20, 0x8877665544332211);\n    write64(0x28, 0x11ffeeddccbbaa99l);\n    fprintf(stderr, \"after3: contents of 0x20 %08lx.%08lx\\n\", read64(0x28), read64(0x20));\n\n    if (verbose) {\n\tfprintf(stderr, \"Reading card memory space\\n\");\n\tfor (int i = 0; i < 16; i++)\n\t    fprintf(stderr, \"CARDMEM[%02x]=%08x\\n\", i*4, read32(0x00000000 + i*4));\n\tfor (int i = 0; i < 16; i += 2)\n\t    fprintf(stderr, \"CARDMEM[%02x]=%08lx\\n\", i*4, read64(0x00000000 + i*8));\n    }\n    }\n    uint64_t cardcap = read64(0);\n    fprintf(stderr, \"cardcap=%08lx\\n\", cardcap);\n    int mpsmax = (cardcap >> 52)&0xF;\n    int mpsmin = (cardcap >> 48)&0xF;\n    if (verbose) fprintf(stderr, \"MPSMAX=%0x %#x bytes\\n\", mpsmax, 1 << (12+mpsmax));\n    if (verbose) fprintf(stderr, \"MPSMIN=%0x %#x bytes\\n\", mpsmin, 1 << (12+mpsmin));\n\n    write32(0x1c, 0x10); // clear reset bit\n    if (verbose) fprintf(stderr, \"0x1c reset %08x\\n\", read32(0x1c));\n    if (verbose) fprintf(stderr, \"0x14 %08llx\\n\", (long long)read(0x14));\n    if (verbose) fprintf(stderr, \"0x18 %08llx\\n\", (long long)read(0x18));\n\n    // initialize CC.IOCQES and CC.IOSQES\n    write32(0x14, 0x00460000); // completion queue entry size 2^4, submission queue entry size 2^6\n\n    if (verbose) {\n      fprintf(stderr, \"CMB size     %08x\\n\", read32(0x38));\n      fprintf(stderr, \"CMB location %08x\\n\", read32(0x3c));\n    }\n    uint64_t adminCompletionBaseAddress = adminCompletionQueueRef << 24;\n    uint64_t adminSubmissionBaseAddress = adminSubmissionQueueRef << 24;\n    if (verbose) fprintf(stderr, \"Setting up Admin submission and completion queues %llx %llx\\n\",\n\t\t\t (long long)adminCompletionBaseAddress, (long long)adminSubmissionBaseAddress);\n    write64(0x28, adminSubmissionBaseAddress);\n    if (verbose) fprintf(stderr, \"AdminSubmissionBaseAddress %08llx\\n\", (long long)read(0x28));\n    write64(0x30, adminCompletionBaseAddress);\n    if (verbose) fprintf(stderr, \"AdminCompletionBaseAddress %08llx\\n\", (long long)read(0x30));\n    write32(0x24, 0x003f003f);\n\n    // CC.enable\n    if (verbose) fprintf(stderr, \"****************************************\\n\");\n    if (verbose) fprintf(stderr, \"CSTS %08x \\n\", read32(0x1c));\n    if (verbose) fprintf(stderr, \"read64 0x18 %08lx\\n\", read64(0x18));\n    write32(0x14, 0x00460000);\n    if (verbose) fprintf(stderr, \"CC.enable %08x (expected 0x00460001)\\n\", read32(0x14));\n    write32(0x14, 0x00460001);\n    if (verbose) fprintf(stderr, \"read64 0x010 %08llx\\n\", (long long)read64(0x10));\n    if (verbose) fprintf(stderr, \"read32 0x014 %08llx\\n\", (long long)read32(0x14));\n    if (verbose) fprintf(stderr, \"****************************************\\n\");\n\tfor (int i = 0; i < 10; i++)\n\t    fprintf(stderr, \"CARDMEM[%02x]=%08x\\n\", i*4, read32(0x00000000 + i*4));\n\n}\n\nvoid Nvme::memserverWrite()\n{\n    Nvme *nvme = this;\n    // identify portals\n    int numTiles = nvme->read32(0x02200000 + 0x08);\n    int numPortals = nvme->read32(0x02200000 + 0x14);\n    fprintf(stderr, \"numTiles=%x numPortals=%x\\n\", numTiles, numPortals);\n    for (int p = 0; p < numPortals; p++) {\n\tfprintf(stderr, \"Platform Portal[%d].id=%x\\n\", p, nvme->read32(0x02200000 + p*0x1000 + 0x10));\n    }\n\n    numTiles = nvme->read32(0x02200000 + 0x40000 + 0x08);\n    numPortals = nvme->read32(0x02200000 + 0x40000 + 0x14);\n    fprintf(stderr, \"numTiles=%x numPortals=%x\\n\", numTiles, numPortals);\n    for (int p = 0; p < numPortals; p++) {\n\tfprintf(stderr, \"Portal[%d].id=%x\\n\", p, nvme->read32(0x02200000 + 0x40000 + p*0x1000 + 0x10));\n    }\n\n    if (1) {\n\t// pause for vivado to connect\n\tfprintf(stderr, \"type enter to continue:\\n\");\n\tchar line[100];\n\tchar *str = fgets(line, sizeof(line), stdin);\n\tif (str == 0)\n\t  fprintf(stderr, \"Failed to read continuation line\\n\");\n    }\n\n    // start write test\n    int pointer = 1;\n    int numWords = 0x1000;\n    int burstLen = 64;\n    int numReqs = numWords / burstLen;\n    int byteEnable = 0xff;\n    nvme->write32(0x02200000 + 0x41000 + 0x20, (pointer>>24));\n    nvme->write32(0x02200000 + 0x41000 + 0x20, (numWords>>24)|(((unsigned long)pointer)<<8));\n    nvme->write32(0x02200000 + 0x41000 + 0x20, (numReqs>>24)|(((unsigned long)numWords)<<8));\n    nvme->write32(0x02200000 + 0x41000 + 0x20, (burstLen>>24)|(((unsigned long)numReqs)<<8));\n    nvme->write32(0x02200000 + 0x41000 + 0x20, byteEnable|(((unsigned long)burstLen)<<8));\n}\n\nvoid Nvme::status() {\n    driverRequest.status();\n    driverIndication->wait();\n}\n\nvoid Nvme::transferStats()\n{\n    uint32_t cycles = driverIndication->cycles;\n    uint32_t requests = driverIndication->requests;\n    fprintf(stderr, \"transfer stats: requests=%d cycles=%d average cycles/request=%5.2f\\n\",\n\t    requests, cycles, (double)cycles/(double)requests);\n}\n\nvoid Nvme::dumpTrace()\n{\n    trace->dumpTrace();\n}\n\nint Nvme::adminCommand(nvme_admin_cmd *cmd, nvme_completion *completion)\n{\n    nvme_admin_cmd *requests = (nvme_admin_cmd *)adminSubmissionQueue.buffer();\n    int requestNumber        = adminRequestNumber % (4096 / sizeof(nvme_admin_cmd));\n    nvme_admin_cmd *request  = &requests[requestNumber];\n    int *responses           = (int *)adminCompletionQueue.buffer();\n    int responseNumber       = adminRequestNumber % (4096 / 16);\n    int *response            = &responses[responseNumber * 4];\n\n    driverRequest.trace(1);\n\n    if (verbose) fprintf(stderr, \"%s:%d requestNumber=%d responseNumber = %d\\n\", __FUNCTION__, __LINE__, requestNumber, responseNumber);\n\n    cmd->cid = adminRequestNumber++;\n    *request = *cmd;\n    write32(0x1000 + ((2*0 + 0) * (4 << 0)), requestNumber+1);\n    fprintf(stderr, \"doorbell value: %08x\\n\", read32(0x1000 + ((2*0 + 0) * (4 << 0))));\n\n    adminSubmissionQueue.cacheInvalidate(4096, 1);\n    adminCompletionQueue.cacheInvalidate(4096, 0);\n\n    // update submission queue tail\n    write32(0x1000 + ((2*0 + 0) * (4 << 0)), requestNumber+1);\n    sleep(1);\n    dumpTrace();\n\n    if (verbose) {\n\tfor (int i = 0; i < 4; i++)\n\t    fprintf(stderr, \"    response[%02x]=%08x\\n\", i*4, response[i]);\n    }\n    int status = response[3];\n    int more = (status >> 30) & 1;\n    int sc = (status >> 17) & 0xff;\n    int sct = (status >> 25) & 0x7;\n    write32(0x1000 + ((2*0 + 1) * (4 << 0)), responseNumber+1);\n    fprintf(stderr, \"doorbell value: %08x\\n\", read32(0x1000 + ((2*0 + 1) * (4 << 0))));\n    if (verbose) fprintf(stderr, \"status=%08x more=%d sc=%x sct=%x\\n\", status, more, sc, sct);\n    return sc;\n}\n\nint Nvme::ioCommand(nvme_io_cmd *cmd, nvme_completion *completion, int queue, int dotrace)\n{\n    nvme_io_cmd *requests = (nvme_io_cmd *)ioSubmissionQueue.buffer();\n    int requestNumber        = ioRequestNumber[queue] % (Nvme::ioQueueSize / sizeof(nvme_io_cmd));\n    nvme_io_cmd *request  = &requests[requestNumber];\n    int *responses           = (int *)ioCompletionQueue.buffer();\n    int responseNumber       = ioRequestNumber[queue] % (Nvme::ioQueueSize / 16);\n    int *response            = &responses[responseNumber * 4];\n    int responseBuffer[4];\n\n    fprintf(stderr, \"%s:%d requestNumber=%d responseNumber = %d requestOffset=%lx io request objid=%d\\n\",\n\t    __FUNCTION__, __LINE__, requestNumber, responseNumber, (long)(requestNumber*sizeof(nvme_io_cmd)), ioSubmissionQueueRef);\n\n    cmd->cid = ioRequestNumber[queue]++;\n\n    driverRequest.trace(dotrace);\n\n    if (queue == 2) {\n\tfprintf(stderr, \"%s:%d starting transfer opcode=%d\\n\", __FUNCTION__, __LINE__, cmd->opcode);\n\n\tint numBlocks = cmd->cdw12+1;\n\trequestProxy.startTransfer(/* read */ cmd->opcode, /* flags */ 0, cmd->cid, cmd->cdw10, numBlocks, /* dsm */0x71);\n\t//sleep(1);\n\n\tif (0) {\n\t    for (int i = 0; i < 16; i++) {\n\t      fprintf(stderr, \"requestbuffer[%02x]=%016llx\\n\", i, (long long)bramRead(0x1000 + i*8));\n\t    }\n\t    for (int i = 0; i < 4; i++) {\n\t      fprintf(stderr, \"responsebuffer[%02x]=%016llx\\n\", i, (long long)bramRead(i*8));\n\t    }\n\t}\n\n\tfor (int i = 0; i < numBlocks/BlocksPerRequest; i++) {\n\t  fprintf(stderr, \"%s:%d waiting for completion numBlocks=%d\\n\", __FUNCTION__, __LINE__, numBlocks);\n\t  indication->wait();\n\t}\n\tdumpTrace();\n\tint status = driverIndication->value >> 32;\n\tint more = (status >> 30) & 1;\n\tint sc = (status >> 17) & 0xff;\n\tint sct = (status >> 25) & 0x7;\n\tfprintf(stderr, \"status=%08x more=%d sc=%x sct=%x\\n\", status, more, sc, sct);\n\treturn sc;\n    }\n\n    if (queue == 1) {\n\tioSubmissionQueue.cacheInvalidate(Nvme::ioQueueSize, 0);\n\n\t*request = *cmd;\n\n\tioSubmissionQueue.cacheInvalidate(Nvme::ioQueueSize, 1);\n\tioCompletionQueue.cacheInvalidate(Nvme::ioQueueSize, 0);\n    } else {\n\trequestNumber = cmd->cid % 8;\n\tuint32_t bramRequestBase = 0x1000 + requestNumber*sizeof(nvme_io_cmd);\n\tfor (uint32_t i = 0; i < sizeof(nvme_io_cmd); i += DataBusBytes) {\n\t    bramWrite(bramRequestBase+i, ((uint64_t *)cmd)[i/8]);\n\t    uint64_t val = bramRead(bramRequestBase+i);\n\t    fprintf(stderr, \"bramRequest[%02x]=%08x.%08x\\n\", bramRequestBase+i, (uint32_t)(val >> 32), (uint32_t)val);\n\t}\n    }\n\n    if (0 && requestNumber==7) {\n\tfprintf(stderr, \"enabling DMA trace\\n\");\n\tdriverRequest.trace(1);\n\tsleep(1);\n    }\n\n    // update submission queue tail\n    write32(0x1000+(2*queue*(4<<0)), requestNumber+1);\n\n    sleep(1);\n\n    if (queue != 1) {\n\t// read response from BRAM\n\tresponse = responseBuffer;\n\tresponseNumber = cmd->cid % 8;\n\tfprintf(stderr, \"cmd->cid=%x\\n\", cmd->cid);\n\tfor (uint32_t i = 0; i < sizeof(nvme_completion); i += DataBusBytes) {\n\t  uint64_t val = bramRead(responseNumber*sizeof(nvme_completion) + i);\n\t  fprintf(stderr, \"i=%02x val=%016llx\\n\", i, (long long)val);\n\t  ((uint64_t *)responseBuffer)[i/DataBusBytes] = val;\n\t}\n    }\n\n    for (int i = 0; i < 4; i++) {\n\tfprintf(stderr, \"    response[%02x]=%08x\\n\", i*4, response[i]);\n    }\n    int status = response[3];\n    int more = (status >> 30) & 1;\n    int sc = (status >> 17) & 0xff;\n    int sct = (status >> 25) & 0x7;\n    // clear status field so we can detect when NVME updates it\n    if (queue == 1) {\n\tresponse[3] = 0;\n    } else {\n      // clear status field\n\tbramWrite(responseNumber*sizeof(nvme_completion) + 1, 0);\n    }\n    // notify NVME that we processed this response\n    write32(0x1000 + ((2*queue + 1) * (4 << 0)), responseNumber+1);\n    fprintf(stderr, \"status=%08x more=%d sc=%x sct=%x\\n\", status, more, sc, sct);\n    return status ? sc : -1;\n}\n\nvoid Nvme::identify()\n{\n    Nvme *nvme = this;\n    fprintf(stderr, \"sizeof(nvmd_id_cmd)=%ld\\n\", (long)sizeof(nvme_admin_cmd));\n    // write an identify command\n    nvme_completion completion;\n    nvme_admin_cmd buffer;\n    nvme_admin_cmd *cmd = &buffer;\n    memset(cmd, 0, sizeof(*cmd));\n    cmd->opcode = nvme_identify;\n    cmd->nsid = 0;\n    cmd->prp1 = (nvme->transferBufferRef << 24) + 0;\n    cmd->prp2 = (nvme->transferBufferRef << 24) + 4096;\n    cmd->cdw10 = 1;\n\n    nvme->adminCommand(cmd, &completion);\n\n    {\n\tchar *cbuffer = (char *)(nvme->transferBuffer.buffer() + 0);\n\t//int *buffer = (int *)(nvme->transferBuffer.buffer() + 0);\n\tchar str[128];\n\tfprintf(stderr, \"PCI vendorid %02x\\n\", *(unsigned short *)&cbuffer[0]);\n\tfprintf(stderr, \"PCI deviceid %02x\\n\", *(unsigned short *)&cbuffer[2]);\n\tsnprintf(str, 20, \"%s\", &cbuffer[4]);\n\tfprintf(stderr, \"serial number '%s'\\n\", str);\n\tsnprintf(str, 40, \"%s\", &cbuffer[24]);\n\tfprintf(stderr, \"model number  '%s'\\n\", str);\n\tsnprintf(str, 8, \"%s\", &cbuffer[64]);\n\tfprintf(stderr, \"firmware rev  '%s'\\n\", str);\n\tfprintf(stderr, \"host buffer preferred size %x\\n\", *(int *)&cbuffer[272]);\n\tfprintf(stderr, \"host buffer min size       %x\\n\", *(int *)&cbuffer[276]);\n\tfprintf(stderr, \"nvm submission queue entry size %d\\n\", cbuffer[512]);\n\tfprintf(stderr, \"nvm completion queue entry size %d\\n\", cbuffer[513]);\n\tfprintf(stderr, \"maximum data transfer size: %d pages\\n\", cbuffer[77] ? (1 << cbuffer[77]) : -1);\n\tfprintf(stderr, \"controller id: %d\\n\", *(unsigned short *)&cbuffer[78]);\n\tfprintf(stderr, \"OACS: %x\\n\", *(unsigned short *)&cbuffer[256]);\n\tfprintf(stderr, \"log page attributes: %x\\n\", cbuffer[261]);\n\tfprintf(stderr, \"error log page entries %d\\n\", cbuffer[262]);\n\tfprintf(stderr, \"host memory buffer preferred size: %x\\n\", *(unsigned int *)&cbuffer[272]);\n\tfprintf(stderr, \"host memory buffer minimum size: %x\\n\", *(unsigned int *)&cbuffer[272]);\n\tfprintf(stderr, \"nvm capacity: %08llx %08llx\\n\", *(long long *)&cbuffer[288], *(long long *)&cbuffer[280]);\n\tfprintf(stderr, \"unallocated capacity: %08llx %08llx\\n\", *(long long *)&cbuffer[304], *(long long *)&cbuffer[296]);\n\tfprintf(stderr, \"number of namespaces: %x\\n\", *(unsigned int *)&cbuffer[516]);\n\tfprintf(stderr, \"ONCS: %x\\n\", *(unsigned short *)&cbuffer[520]);\n\tfprintf(stderr, \"supports SGL: %x\\n\", *(int *)&cbuffer[536]);\n    }\n}\n\nvoid Nvme::getFeatures(FeatureId featureId)\n{\n    Nvme *nvme = this;\n    fprintf(stderr, \"sizeof(nvmd_id_cmd)=%ld\\n\", (long)sizeof(nvme_admin_cmd));\n    nvme_completion completion;\n    nvme_admin_cmd buffer;\n    nvme_admin_cmd *cmd = &buffer;\n    memset(cmd, 0, sizeof(*cmd));\n    cmd->opcode = 0xa;\n    cmd->nsid = 0;\n    //cmd->prp1 = (nvme->transferBufferRef << 24) + 0;\n    //cmd->prp2 = (nvme->transferBufferRef << 24) + 4096;\n    cmd->cdw10 = featureId;\n\n    nvme->adminCommand(cmd, &completion);\n\n    {\n\tchar *cbuffer = (char *)(nvme->transferBuffer.buffer() + 0);\n\t//int *buffer = (int *)(nvme->transferBuffer.buffer() + 0);\n\t//char str[128];\n\tfprintf(stderr, \"foo %x\\n\", *(unsigned short *)&cbuffer[0]);\n    }\n}\n\nvoid Nvme::allocIOQueues(int entry)\n{\n    Nvme *nvme = this;\n\n    nvme_completion completion;\n    nvme_admin_cmd buffer;\n    nvme_admin_cmd *cmd = &buffer;\n\n    fprintf(stderr, \"%s:%d allocating completion queue with %d entries\\n\", __FUNCTION__, __LINE__, (Nvme::ioQueueSize / 16));\n    // create I/O completion queue\n    memset(cmd, 0, sizeof(*cmd));\n    cmd->opcode = nvme_create_completion_queue; //5;\n    cmd->nsid = 0;\n    cmd->prp1 = (nvme->ioCompletionQueueRef << 24) + 0;\n    cmd->cdw10 = ((Nvme::ioQueueSize / 16 - queueSizeDelta) << 16) | 1; // size, completion queue 1\n    cmd->cdw11 = 1; // physically contiguous\n    nvme->adminCommand(cmd, &completion);\n\n    fprintf(stderr, \"%s:%d allocating request queue with %d entries\\n\", __FUNCTION__, __LINE__, (Nvme::ioQueueSize / 64));\n    // create I/O submission queue\n    memset(cmd, 0, sizeof(*cmd));\n    cmd->opcode = nvme_create_submission_queue; //1;\n    cmd->nsid = 0;\n    cmd->prp1 = (nvme->ioSubmissionQueueRef << 24) + 0;\n    cmd->cdw10 = ((Nvme::ioQueueSize / 64 - queueSizeDelta) << 16) | 1; // size, submission queue 1\n    cmd->cdw11 = (1 << 16) | 1; // completion queue 1, physically contiguous\n    nvme->adminCommand(cmd, &completion);\n\n    int numBramEntries = 8;\n    //int responseQueueOffset = 0;\n    //int submissionQueueOffset = numBramEntries * 16;\n    fprintf(stderr, \"%s:%d allocating completion queue with %d entries\\n\", __FUNCTION__, __LINE__, numBramEntries);\n    // create I/O completion queue\n    memset(cmd, 0, sizeof(*cmd));\n    cmd->opcode = nvme_create_completion_queue;\n    cmd->nsid = 0;\n    cmd->prp1 = (0x20 << 24) + 0;\n    cmd->cdw10 = ((numBramEntries-queueSizeDelta)<<16) | 2; // size, completion queue 2\n    cmd->cdw11 = 1; // physically contiguous\n    nvme->adminCommand(cmd, &completion);\n\n    fprintf(stderr, \"%s:%d allocating request queue with %d entries\\n\", __FUNCTION__, __LINE__, numBramEntries);\n    // create I/O submission queue\n    memset(cmd, 0, sizeof(*cmd));\n    cmd->opcode = nvme_create_submission_queue;\n    cmd->nsid = 0;\n    cmd->prp1 = (0x20 << 24) + 0x1000;\n    cmd->cdw10 = ((numBramEntries-queueSizeDelta)<<16) | 2; // size, submission queue 2\n    cmd->cdw11 = (2 << 16) | 1; // completion queue 2, physically contiguous\n    nvme->adminCommand(cmd, &completion);\n\n}\n\nint Nvme::doIO(nvme_io_opcode opcode, int startBlock, int numBlocks, int queue, int dotrace)\n{\n    Nvme *nvme = this;\n    int blocksPerPage = 4096 / 512;\n    int transferBufferId = (queue == 1) ? nvme->transferBufferRef : 2;\n    uint32_t bramBuffer = (2 << 24) + 0x2000;\n    // clear transfer buffer\n    {\n\tint *buffer = (int *)nvme->ioCompletionQueue.buffer();\n\tmemset(buffer, 0, numBlocks*512);\n    }\n\n    // let's do a read\n    nvme_io_cmd cmd;\n    nvme_completion completion;\n    memset(&cmd, 0, sizeof(cmd));\n    cmd.opcode = opcode;\n    cmd.nsid = 1;\n    cmd.flags = 0x00; // PRP used for this transfer\n    if (queue == 2)\n      cmd.prp1 = 0x30000000ul; // send data to the FIFO\n    else\n      cmd.prp1 = (transferBufferId << 24);\n    fprintf(stderr, \"cmd.prp1=%llx\\n\", (long long)cmd.prp1);\n    cmd.prp2 = (transferBufferId << 24) + 0;\n    if (queue == 1) { \n      uint64_t *prplist = (uint64_t *)nvme->adminBuffer.buffer();\n      for (int i = 0; i < numBlocks/blocksPerPage; i++) {\n\tif (opcode == nvme_read)\n\t  prplist[i] = (uint64_t)(0x30000000ul + 0x1000*i + 0x1000); // enqueue/dequeue FIFO data\n\telse\n\t  prplist[i] = (uint64_t)((transferBufferId << 24) + 0x1000*i + 0x1000); // read/write DRAM data\n      }\n\n      nvme->transferBuffer.cacheInvalidate(8*512, 1);\n    } else {\n      for (int i = 0; i < numBlocks/blocksPerPage; i++) {\n\tnvme->bramWrite(bramBuffer+i, (uint64_t)(0x30000000ul + 0x1000*i + 0x1000)); // send data to the FIFO\n\tfprintf(stderr, \"bramRead[%02x]=%08llx\\n\", i, (long long)nvme->bramRead(bramBuffer+i));\n      }\n    }\n\n    cmd.cdw10 = startBlock; // starting LBA.lower\n    cmd.cdw11 = 0; // starting LBA.upper\n    cmd.cdw12 = numBlocks-1; // read N blocks\n\n    fprintf(stderr, \"IO cmd opcode=%02x flags=%02x cid=%04x %08x\\n\", cmd.opcode, cmd.flags, cmd.cid, *(int *)&cmd);\n\n    int sc = nvme->ioCommand(&cmd, &completion, queue, dotrace);\n    if (sc) {\n\tint *buffer = (int *)nvme->transferBuffer.buffer();\n\tfor (int i = 0; i < numBlocks*512/4; i++) {\n\t    if (buffer[i])\n\t\tfprintf(stderr, \"data read [%02x]=%08x\\n\", i*4, buffer[i]);\n\t}\n    }\n    return sc;\n}\n\nvoid Nvme::messageFromSoftware(uint32_t msg, bool last)\n{\n  requestProxy.msgFromSoftware(msg, last);\n}\n\nbool Nvme::messageToSoftware(uint32_t *msgp, bool *lastp, bool nonBlocking)\n{\n    return indication->messageToSoftware(msgp, lastp, nonBlocking);\n}\n"
  },
  {
    "path": "lib/nvme/cpp/nvme.h",
    "content": "#pragma once\n\n#include <map>\n#include <string>\n\n#include \"DmaBuffer.h\"\n#include \"portal.h\"\n#include \"dmaManager.h\"\n#include \"NvmeDriverIndication.h\"\n#include \"NvmeDriverRequest.h\"\n#include \"NvmeIndication.h\"\n#include \"NvmeRequest.h\"\n#include \"NvmeTrace.h\"\n#include \"MemServerPortalRequest.h\"\n#include \"MemServerPortalIndication.h\"\n//#include \"ConnectalProjectConfig.h\"\n\nconst int DataBusWidth = 64;\nconst int DataBusBytes = DataBusWidth/8;\n\nenum nvme_admin_opcode {\n    nvme_create_submission_queue = 1,\n    nvme_create_completion_queue = 5,\n    nvme_identify     = 6,\n    nvme_get_features = 10,\n};\n\nenum nvme_io_opcode {\n    nvme_flush = 0,\n    nvme_write = 1,\n    nvme_read = 2,\n    nvme_write_uncorrectable = 4,\n    nvme_compare = 5,\n    nvme_write_zeroes = 8,\n    nvme_manage_dataset = 9,\n    nvme_register_reservation = 13,\n    nvme_report_reservation = 14,\n    nvme_acquire_reservation = 17,\n    nvme_release_reservation = 21\n};\n\nstruct nvme_admin_cmd {\n    uint8_t opcode;\n    uint8_t flags;\n    uint16_t cid;\n    uint32_t nsid;\n    uint32_t reserved0;\n    uint32_t reserved1;\n    uint64_t mptr;\n    uint64_t prp1;\n    uint64_t prp2;\n    uint32_t cdw10;\n    uint32_t cdw11;\n    uint32_t cdw12;\n    uint32_t cdw13;\n    uint32_t cdw14;\n    uint32_t cdw15;\n};\n\nstruct nvme_io_cmd {\n    uint8_t opcode;     // offset: 00\n    uint8_t flags;\n    uint16_t cid;\n    uint32_t nsid;      // offset 04\n    uint64_t reserved0; // offset 08\n    uint64_t mptr;      // offset 16\n    uint64_t prp1;      // offset 24\n    uint64_t prp2;      // offset 32\n    uint32_t cdw10;     // offset 40\n    uint32_t cdw11;     // offset 44\n    uint32_t cdw12;\n    uint32_t cdw13;\n    uint32_t cdw14;\n    uint32_t cdw15;\n};\n\nstruct nvme_completion {\n    int cdw0;\n    int cdw1;\n    int cdw2;\n    int cdw3;\n};\n\nstruct sgl_data_block_descriptor {\n    uint64_t address;\n    uint32_t length;\n    uint8_t reserved[3];\n    uint8_t sglid;\n};\n\nenum FeatureId {\n    FID_NumberOfQueues = 7\n};\n\nclass NvmeTrace;\nclass NvmeIndication;\nclass NvmeDriverIndication;\nclass MemServerPortalIndication;\n\nclass Nvme {\n    bool verbose;\n    NvmeRequestProxy requestProxy;\n    NvmeIndication  *indication;\n    NvmeDriverRequestProxy driverRequest;\n    NvmeDriverIndication  *driverIndication;\n    NvmeTrace       *trace;\n    MemServerPortalRequestProxy bram;\n    MemServerPortalIndication   *bramIndication;\n    int adminRequestNumber;\n    int ioRequestNumber[3]; // per queue, io queue 0 unused\npublic:\n    DmaBuffer adminBuffer;\n    DmaBuffer transferBuffer;\n    DmaBuffer adminSubmissionQueue;\n    DmaBuffer adminCompletionQueue;\n    DmaBuffer ioSubmissionQueue;\n    DmaBuffer ioCompletionQueue;\n    DmaBuffer needleBuffer;\n    DmaBuffer mpNextBuffer;\n    int adminBufferRef;\n    int transferBufferRef;\n    int adminSubmissionQueueRef;\n    int adminCompletionQueueRef;\n    int ioSubmissionQueueRef;\n    int ioCompletionQueueRef;\n    int needleRef;\n    int mpNextRef;\n\n    static const int ioQueueSize = 4096;\n\n    Nvme(int transferBuffeSize = BlocksPerRequest*512, bool verbose=false);\n    Nvme(bool verbose);\n    void setup();\n\n    int adminCommand(nvme_admin_cmd *cmd, nvme_completion *completion);\n    int ioCommand(nvme_io_cmd *cmd, nvme_completion *completion, int queue=1, int dotrace=0);\n    void status();\n    void transferStats();\n    void dumpTrace();\n\n    void identify();\n    void getFeatures(FeatureId featureId=FID_NumberOfQueues);\n    void allocIOQueues(int entry=0);\n\n    int doIO(nvme_io_opcode opcode, int startBlock, int numBlocks, int queue=1, int dotrace=0);\n\n    void messageFromSoftware(uint32_t msg, bool last=false);\n    bool messageToSoftware(uint32_t *msg, bool *last, bool nonBlocking=false);\n\n    // private:\n    uint32_t readCtl(uint32_t addr);\n    void writeCtl(uint32_t addr, uint32_t data);\n    uint64_t read(uint32_t addr);\n    void write(uint32_t addr, uint64_t data);\n    uint32_t read32(uint32_t addr);\n    void write32(uint32_t addr, uint32_t data);\n    uint64_t read64(uint32_t addr);\n    void write64(uint32_t addr, uint64_t data);\n    void write128(uint32_t addr, uint64_t udata, uint64_t ldata);\n    uint64_t bramRead(uint32_t addr);\n    void bramWrite(uint32_t addr, uint64_t data);\n\n    void memserverWrite();\n};\n\n"
  },
  {
    "path": "lib/nvme/tcl/package.tcl",
    "content": "#-----------------------------------------------------------\n# Vivado v2016.2 (64-bit)\n# SW Build 1577090 on Thu Jun  2 16:32:35 MDT 2016\n# IP Build 1577682 on Fri Jun  3 12:00:54 MDT 2016\n# Start of session at: Tue Aug  2 13:39:27 2016\n# Process ID: 17294\n# Current directory: /home/jamey/connectal/tests/nvme_strstr\n# Command line: vivado\n# Log file: /home/jamey/connectal/tests/nvme_strstr/vivado.log\n# Journal file: /home/jamey/connectal/tests/nvme_strstr/vivado.jou\n#-----------------------------------------------------------\nstart_gui\ncreate_project accel /home/jamey/connectal/tests/nvme_strstr/accel -part xc7vx485tffg1157-1\nadd_files -norecurse /home/jamey/connectal/tests/nvme_strstr/miniitx100/verilog/mkNvmeAccelerator.v\nupdate_compile_order -fileset sources_1\nupdate_compile_order -fileset sim_1\nipx::package_project -root_dir /home/jamey/connectal/tests/nvme_strstr/miniitx100 -vendor user.org -library user -taxonomy /UserIP\nipx::add_port_map TREADY [ipx::get_bus_interfaces dataOut -of_objects [ipx::current_core]]\nipx::add_port_map TVALID [ipx::get_bus_interfaces dataOut -of_objects [ipx::current_core]]\nipx::add_port_map TLAST [ipx::get_bus_interfaces dataOut -of_objects [ipx::current_core]]\nipx::add_port_map TDATA [ipx::get_bus_interfaces dataOut -of_objects [ipx::current_core]]\nipx::add_port_map TKEEP [ipx::get_bus_interfaces dataOut -of_objects [ipx::current_core]]\nset_property physical_name dataOut_tready_v [ipx::get_port_maps TREADY -of_objects [ipx::get_bus_interfaces dataOut -of_objects [ipx::current_core]]]\nset_property physical_name dataOut_tvalid [ipx::get_port_maps TVALID -of_objects [ipx::get_bus_interfaces dataOut -of_objects [ipx::current_core]]]\nset_property physical_name dataOut_tlast [ipx::get_port_maps TLAST -of_objects [ipx::get_bus_interfaces dataOut -of_objects [ipx::current_core]]]\nset_property physical_name dataOut_tdata [ipx::get_port_maps TDATA -of_objects [ipx::get_bus_interfaces dataOut -of_objects [ipx::current_core]]]\nset_property physical_name dataOut_tkeep [ipx::get_port_maps TKEEP -of_objects [ipx::get_bus_interfaces dataOut -of_objects [ipx::current_core]]]\nipx::associate_bus_interfaces -busif dataOut -clock CLK [ipx::current_core]\nipx::add_port_map TREADY [ipx::get_bus_interfaces msgOut -of_objects [ipx::current_core]]\nset_property physical_name msgOut_tready_v [ipx::get_port_maps TREADY -of_objects [ipx::get_bus_interfaces msgOut -of_objects [ipx::current_core]]]\nipx::add_bus_interface msgIn [ipx::current_core]\nset_property abstraction_type_vlnv xilinx.com:interface:axis_rtl:1.0 [ipx::get_bus_interfaces msgIn -of_objects [ipx::current_core]]\nset_property bus_type_vlnv xilinx.com:interface:axis:1.0 [ipx::get_bus_interfaces msgIn -of_objects [ipx::current_core]]\nipx::add_port_map TVALID [ipx::get_bus_interfaces msgIn -of_objects [ipx::current_core]]\nset_property physical_name msgIn_tvalid_v [ipx::get_port_maps TVALID -of_objects [ipx::get_bus_interfaces msgIn -of_objects [ipx::current_core]]]\nipx::add_port_map TLAST [ipx::get_bus_interfaces msgIn -of_objects [ipx::current_core]]\nset_property physical_name msgIn_tlast_v [ipx::get_port_maps TLAST -of_objects [ipx::get_bus_interfaces msgIn -of_objects [ipx::current_core]]]\nipx::add_port_map TDATA [ipx::get_bus_interfaces msgIn -of_objects [ipx::current_core]]\nset_property physical_name msgIn_tdata_v [ipx::get_port_maps TDATA -of_objects [ipx::get_bus_interfaces msgIn -of_objects [ipx::current_core]]]\nipx::add_port_map TKEEP [ipx::get_bus_interfaces msgIn -of_objects [ipx::current_core]]\nset_property physical_name msgIn_tkeep_v [ipx::get_port_maps TKEEP -of_objects [ipx::get_bus_interfaces msgIn -of_objects [ipx::current_core]]]\nipx::add_port_map TREADY [ipx::get_bus_interfaces msgIn -of_objects [ipx::current_core]]\nset_property physical_name msgIn_tready [ipx::get_port_maps TREADY -of_objects [ipx::get_bus_interfaces msgIn -of_objects [ipx::current_core]]]\nipx::associate_bus_interfaces -busif msgIn -clock CLK [ipx::current_core]\nipx::associate_bus_interfaces -busif msgOut -clock CLK [ipx::current_core]\nipx::associate_bus_interfaces -busif dataOut -clock CLK [ipx::current_core]\nipx::infer_bus_interface RST_N xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]\nipx::add_bus_interface nvme_pcie_mgt [ipx::current_core]\nset_property abstraction_type_vlnv xilinx.com:interface:pcie_7x_mgt_rtl:1.0 [ipx::get_bus_interfaces nvme_pcie_mgt -of_objects [ipx::current_core]]\nset_property bus_type_vlnv xilinx.com:interface:pcie_7x_mgt:1.0 [ipx::get_bus_interfaces nvme_pcie_mgt -of_objects [ipx::current_core]]\nset_property interface_mode master [ipx::get_bus_interfaces nvme_pcie_mgt -of_objects [ipx::current_core]]\nipx::add_port_map rxn [ipx::get_bus_interfaces nvme_pcie_mgt -of_objects [ipx::current_core]]\nset_property physical_name pins_pcie_exp_rxn_v [ipx::get_port_maps rxn -of_objects [ipx::get_bus_interfaces nvme_pcie_mgt -of_objects [ipx::current_core]]]\nipx::add_port_map txn [ipx::get_bus_interfaces nvme_pcie_mgt -of_objects [ipx::current_core]]\nset_property physical_name pins_pcie_exp_txn [ipx::get_port_maps txn -of_objects [ipx::get_bus_interfaces nvme_pcie_mgt -of_objects [ipx::current_core]]]\nipx::add_port_map rxp [ipx::get_bus_interfaces nvme_pcie_mgt -of_objects [ipx::current_core]]\nset_property physical_name pins_pcie_exp_rxp_v [ipx::get_port_maps rxp -of_objects [ipx::get_bus_interfaces nvme_pcie_mgt -of_objects [ipx::current_core]]]\nipx::add_port_map txp [ipx::get_bus_interfaces nvme_pcie_mgt -of_objects [ipx::current_core]]\nset_property physical_name pins_pcie_exp_txp [ipx::get_port_maps txp -of_objects [ipx::get_bus_interfaces nvme_pcie_mgt -of_objects [ipx::current_core]]]\nipx::add_bus_interface pcie_ref_clk [ipx::current_core]\nset_property abstraction_type_vlnv xilinx.com:interface:diff_clock_rtl:1.0 [ipx::get_bus_interfaces pcie_ref_clk -of_objects [ipx::current_core]]\nset_property bus_type_vlnv xilinx.com:interface:diff_clock:1.0 [ipx::get_bus_interfaces pcie_ref_clk -of_objects [ipx::current_core]]\nset_property interface_mode master [ipx::get_bus_interfaces pcie_ref_clk -of_objects [ipx::current_core]]\nset_property interface_mode slave [ipx::get_bus_interfaces pcie_ref_clk -of_objects [ipx::current_core]]\nipx::add_port_map CLK_P [ipx::get_bus_interfaces pcie_ref_clk -of_objects [ipx::current_core]]\nset_property physical_name pins_pcie_refclk_p [ipx::get_port_maps CLK_P -of_objects [ipx::get_bus_interfaces pcie_ref_clk -of_objects [ipx::current_core]]]\nipx::add_port_map CLK_N [ipx::get_bus_interfaces pcie_ref_clk -of_objects [ipx::current_core]]\nset_property physical_name pins_pcie_refclk_n [ipx::get_port_maps CLK_N -of_objects [ipx::get_bus_interfaces pcie_ref_clk -of_objects [ipx::current_core]]]\nipx::add_bus_interface pcie_sys_reset_n [ipx::current_core]\nset_property abstraction_type_vlnv xilinx.com:signal:reset_rtl:1.0 [ipx::get_bus_interfaces pcie_sys_reset_n -of_objects [ipx::current_core]]\nset_property bus_type_vlnv xilinx.com:signal:reset:1.0 [ipx::get_bus_interfaces pcie_sys_reset_n -of_objects [ipx::current_core]]\nset_property interface_mode master [ipx::get_bus_interfaces pcie_sys_reset_n -of_objects [ipx::current_core]]\nipx::add_port_map RST [ipx::get_bus_interfaces pcie_sys_reset_n -of_objects [ipx::current_core]]\nset_property physical_name RST_N_pins_pcie_sys_reset_n [ipx::get_port_maps RST -of_objects [ipx::get_bus_interfaces pcie_sys_reset_n -of_objects [ipx::current_core]]]\n\nset_property core_revision 2 [ipx::current_core]\nipx::create_xgui_files [ipx::current_core]\nipx::update_checksums [ipx::current_core]\nipx::save_core [ipx::current_core]\nset_property  ip_repo_paths  /home/jamey/connectal/tests/nvme_strstr/miniitx100 [current_project]\nupdate_ip_catalog\nipx::check_integrity -quiet [ipx::current_core]\n#ipx::archive_core /home/jamey/connectal/tests/nvme_strstr/miniitx100/user.org_user_mkNvmeAccelerator_1.0.zip [ipx::current_core]\n"
  },
  {
    "path": "lib/qemu/fpgadev.cpp",
    "content": "\n#include <fcntl.h>\n#include <sys/mman.h>\n#include <sys/types.h>\n#include <sys/stat.h>\n#include <sys/time.h>\n#include <time.h>\n#include <unistd.h>\n#include <errno.h>\n#include <queue>\n#include <thread>\n#include <mutex>\n\n#include <GeneratedTypes.h>\n#include <BlockDevResponse.h>\n#include <BlockDevRequest.h>\n#include <MemServerPortalResponse.h>\n#include <MemServerPortalRequest.h>\n#include <QemuAccelRequest.h>\n#include <QemuAccelIndication.h>\n#include <SerialRequest.h>\n#include <SerialIndication.h>\n#include \"dmaManager.h\"\n#include \"fpgadev.h\"\n#ifdef REGISTER_SPIKE_DEVICES\n#include <functional>\n#include <riscv/sim.h>\n#include <riscv/devices.h>\n#endif\n\n\nint verbose = 0;\nstd::mutex mutex;\n\nvoid sem_wait_with_timeout(sem_t *sem)\n{\n    struct timespec timeout;\n\n    for (int tries = 0; tries < 10; tries++) {\n\tclock_gettime(CLOCK_REALTIME, &timeout);\n\ttimeout.tv_sec += 1;\n\tint status = sem_timedwait(sem, &timeout);\n\tif (status == 0) {\n\t    return;\n\t} else if (errno == ETIMEDOUT) {\n\t    if (tries > 5)\n\t\tfprintf(stderr, \"%s:%d: try %d timed out waiting for response status=%d errno=%d:%s\\n\", __FILE__, __LINE__, tries, status, errno, strerror(errno));\n\t} else {\n\t    fprintf(stderr, \"%s:%d errno=%d:%s\\n\", __FUNCTION__, __LINE__, errno, strerror(errno));\n\t    return;\n\t}\n    }\n    fprintf(stderr, \"%s:%d timed out waiting for semaphore\\n\", __FUNCTION__, __LINE__);\n}\n\nint readReq;\nint readCount;\nclass MemServerPortalResponse : public MemServerPortalResponseWrapper\n{\n    sem_t sem;\npublic:\n    int irq;\n    uint32_t buf[16];\n    IrqCallback irqCallback;\n\n    void wait() {\n\tsem_wait_with_timeout(&sem);\n    }\n\n    void read32Done ( const uint32_t value ) {\n\tbuf[0] = value;\n\tif (0 || verbose) fprintf(stderr, \"readDone value=%08x count=%d\\n\", value, readCount++);\n\tsem_post(&sem);\n    }\n\n    void read64Done ( const uint64_t value ) {\n\t*(uint64_t *)buf = value;\n\tif (0 || verbose) fprintf(stderr, \"readDone value=%08llx count=%d\\n\", (long long)value, readCount++);\n\tsem_post(&sem);\n    }\n\n    void writeDone (  ) {\n\tif (verbose) fprintf(stderr, \"writeDone\\n\");\n\tsem_post(&sem);\n    }\n\n    MemServerPortalResponse(unsigned int id, IrqCallback callback=0) : MemServerPortalResponseWrapper(id), irq(0), irqCallback(callback) {\n      sem_init(&sem, 0, 0);\n    }\n};\n\nclass QemuAccelIndication : public QemuAccelIndicationWrapper {\nprivate:\n    sem_t sem;\npublic:\n    QemuAccelIndication(int id, PortalPoller *poller = 0) : QemuAccelIndicationWrapper(id, poller) {\n      sem_init(&sem, 0, 0);\n    }\n    virtual ~QemuAccelIndication() {}\n    virtual void started (  ) {\n    }\n    virtual void wait() {\n\tsem_wait_with_timeout(&sem);\n    }\n};\n\nclass SerialIndication : public SerialIndicationWrapper {\nprivate:\npublic:\n    SerialIndication(int id, PortalPoller *poller = 0) : SerialIndicationWrapper(id, poller) {\n    }\n    virtual ~SerialIndication() {}\n    virtual void rx (const uint8_t ch) {\n\tfprintf(stderr, \"%c\", ch);\n    }\n};\n\nclass BlockDevRequest;\n\nclass BlockDevRequest : public BlockDevRequestWrapper {\nprivate:\n    FpgaDev               *fpgaDev;\n    BlockDevResponseProxy *response;\n    int                   driveFd;\n    std::queue<uint32_t> responseQueue;\n    sem_t              worker_sem;\n    std::mutex         rqmutex;\n    std::thread        rqthread;\n    static void blockDevWorker(BlockDevRequest *blockdev);\n\npublic:\n  BlockDevRequest(FpgaDev *fpgaDev, BlockDevResponseProxy *response, int id, PortalPoller *poller = 0)\n      : BlockDevRequestWrapper(id, poller), fpgaDev(fpgaDev), response(response)\n  {\n    const char *driveName = getenv(\"FPGADEV_BLOCKDEV_FILE\");\n    if (driveName) {\n      driveFd = open(driveName, O_RDWR);\n      fprintf(stderr, \"Opened blockdev %s fd %d\\n\", driveName, driveFd);\n    }\n    sem_init(&worker_sem, 0, 0);\n    rqthread = std::thread(blockDevWorker, this);\n  }\n    virtual ~BlockDevRequest() {}\n  virtual void transfer ( const BlockDevOp op, const uint32_t dramaddr, const uint32_t offset, const uint32_t size, const uint32_t tag );\n};\n\nvoid BlockDevRequest::blockDevWorker(BlockDevRequest *blockdev)\n{\n    fprintf(stderr, \"%s:%d started\\n\", __FUNCTION__, __LINE__);\n    while (1) {\n\tint tag = -1;\n\tsem_wait(&blockdev->worker_sem);\n\t{\n\t    std::lock_guard<std::mutex> lock(blockdev->rqmutex);\n\t    tag = blockdev->responseQueue.front();\n\t    blockdev->responseQueue.pop();\n\t}\n\tif (tag != -1) {\n\t    //std::lock_guard<std::mutex> lock(mutex);\n\t    blockdev->response->transferDone(tag);\n\t}\n    }\n}\n\nvoid BlockDevRequest::transfer ( const BlockDevOp op, const uint32_t dramaddr, const uint32_t offset, const uint32_t size, const uint32_t tag )\n{\n  if (0) fprintf(stderr, \"BlockDevRequest::transfer op=%x dramaddr=%x offset=%x size=%x tag=%x\\n\", op, dramaddr, offset, size, tag);\n  if (fpgaDev->mainMemBuf) {\n    if (op == BlockDevRead) {\n      int numBytes = pread(driveFd, fpgaDev->mainMemBuf + dramaddr, size, offset);\n      if (numBytes != (long)size)\n\tfprintf(stderr, \"Read error size=%d numBytes=%d errno=%d:%s\\n\", size, numBytes, errno, strerror(errno));\n    } else {\n      int numBytes = pwrite(driveFd, fpgaDev->mainMemBuf + dramaddr, size, offset);\n      if (numBytes != (long)size)\n\tfprintf(stderr, \"Read error size=%d numBytes=%d errno=%d:%s\\n\", size, numBytes, errno, strerror(errno));\n    }\n  }\n  {\n      std::lock_guard<std::mutex> lock(rqmutex);\n      responseQueue.push(tag);\n      sem_post(&worker_sem);\n  }\n\n}\n\nMemServerPortalRequestProxy *request;\nMemServerPortalResponse *indication;\n\nFpgaDev::FpgaDev(IrqCallback callback)\n    : request(0), indication(0), dmaManager(0), didReset(false), mainMemFd(0)\n{\n    request = new MemServerPortalRequestProxy(IfcNames_MemServerPortalRequestS2H);\n    indication = new MemServerPortalResponse(IfcNames_MemServerPortalResponseH2S, callback);\n    qemuAccelRequest    = new QemuAccelRequestProxy(IfcNames_QemuAccelRequestS2H);\n    qemuAccelIndication = new QemuAccelIndication(IfcNames_QemuAccelIndicationH2S);\n    serialRequest    = new SerialRequestProxy(IfcNames_SerialRequestS2H);\n    serialIndication = new SerialIndication(IfcNames_SerialIndicationH2S);\n    blockDevResponse = new BlockDevResponseProxy(IfcNames_BlockDevResponseS2H); // responses to the risc-v\n    blockDevRequest   = new BlockDevRequest(this, blockDevResponse, IfcNames_BlockDevRequestH2S);       // requests from the risc-v\n    dmaManager = platformInit();\n\n    //std::lock_guard<std::mutex> lock(mutex);\n\n    qemuAccelRequest->reset();\n    fprintf(stderr, \"FpgaDev::FpgaDev\\n\");\n    for (int i = 0; i < 20; i++) {\n\trequest->write32(0xc0003020, '*');\n\tindication->wait();\n    }\n\n}\n\nFpgaDev::~FpgaDev()\n{\n  //delete request;\n  //delete indication;\n  request = 0;\n  indication = 0;\n}\n\nvoid FpgaDev::maybeReset()\n{\n    if (0)\n    if (!didReset) {\n      //std::lock_guard<std::mutex> lock(mutex);\n\n\tqemuAccelRequest->reset();\n\tqemuAccelIndication->wait();\n\n\t//request->setParameters(50, 0);\n\tdidReset = true;\n    }\n}\n\nvoid FpgaDev::status()\n{\n    //std::lock_guard<std::mutex> lock(mutex);\n    qemuAccelRequest->status();\n    qemuAccelIndication->wait();\n}\n\nvoid FpgaDev::setupDma(uint32_t memfd)\n{\n    //std::lock_guard<std::mutex> lock(mutex);\n    int memref = dmaManager->reference(memfd);\n    fprintf(stderr, \"FpgaDev::setupDma memfd=%d memref=%d\\n\", memfd, memref);\n    qemuAccelRequest->setupDma(memref);\n}\n\nvoid FpgaDev::read(unsigned long offset, uint8_t *buf)\n{\n    maybeReset();\n\n    //std::lock_guard<std::mutex> lock(mutex);\n    int count = readReq++;\n    if (0 || verbose) fprintf(stderr, \"FpgaDev::read offset=%lx count=%d\\n\", offset, count);\n    request->read32(offset);\n    indication->wait();\n    if (0 || verbose) fprintf(stderr, \"FpgaDev::read offset=%lx value=%x count=%d\\n\", offset, *(uint32_t *)indication->buf, count);\n    memcpy(buf, indication->buf, 4);\n}\n\nvoid FpgaDev::write(unsigned long offset, const uint8_t *buf)\n{\n    maybeReset();\n\n    //std::lock_guard<std::mutex> lock(mutex);\n    if (verbose) fprintf(stderr, \"FpgaDev::write offset=%lx value=%x\\n\", offset, *(uint32_t *)buf);\n    request->write32(offset, *(uint32_t *)buf);\n    indication->wait();\n    //request->status();\n    //indication->wait();\n}\n\nuint32_t FpgaDev::read(unsigned long offset)\n{\n    maybeReset();\n\n    //std::lock_guard<std::mutex> lock(mutex);\n    int count = readReq++;\n    if (0 || verbose) fprintf(stderr, \"FpgaDev::read offset=%08lx count=%d\\n\", offset, count);\n    request->read32(offset);\n    indication->wait();\n    if (0 || verbose) fprintf(stderr, \"FpgaDev::read done value=%x count=%d\\n\", *(uint32_t *)indication->buf, count);\n    return *(uint32_t *)indication->buf;\n}\n\nvoid FpgaDev::write(unsigned long offset, const uint32_t value)\n{\n    maybeReset();\n\n    //std::lock_guard<std::mutex> lock(mutex);\n    if (verbose) fprintf(stderr, \"FpgaDev::write offset=%08lx value=%x\\n\", offset, value);\n    request->write32(offset, value);\n    indication->wait();\n    if (verbose) fprintf(stderr, \"FpgaDev::write done\\n\");\n}\n\nbool FpgaDev::hasInterrupt()\n{\n    return indication->irq; \n}\nvoid FpgaDev::clearInterrupt()\n{\n    indication->irq = 0;\n}\n\nchar *FpgaDev::allocate_mem(size_t memsz)\n{\n    int memfd = portalAlloc(memsz, 1);\n    if (memfd < 0)\n\treturn 0;\n    char *buf = (char *)portalMmap(memfd, memsz);\n    if (buf == MAP_FAILED) {\n\tclose(memfd);\n\treturn 0;\n    }\n    fprintf(stderr, \"FpgaDev::allocate_mem memsz=%lx memfd=%d buf=%p\\n\", memsz, memfd, buf);\n    if (!mainMemFd) {\n\tsetupDma(memfd);\n\tmainMemFd = memfd;\n\tmainMemBuf = buf;\n\tfprintf(stderr, \"FpgaDev::allocate_mem mainMemFd=%d\\n\", memfd);\n    }\n    return buf;\n}\n\nFpgaDev *fpgaDev;\n\n#ifdef REGISTER_SPIKE_DEVICES\nclass spikehw_device_t : public abstract_device_t {\npublic:\n  spikehw_device_t();\n  bool has_interrupt();\n  bool load(reg_t addr, size_t len, uint8_t* bytes);\n  bool store(reg_t addr, size_t len, const uint8_t* bytes);\n  static abstract_device_t *make_device();\n};\n\nspikehw_device_t::spikehw_device_t()\n{\n  if (!fpgaDev)\n    fpgaDev = new FpgaDev();\n}\n\nbool spikehw_device_t::has_interrupt()\n{\n    if (fpgaDev->hasInterrupt()) {\n\tfpgaDev->clearInterrupt();\n\treturn true;\n    }\n    return false;\n}\n\nbool spikehw_device_t::load(reg_t addr, size_t len, uint8_t* bytes)\n{\n    int count=readReq++;\n    fprintf(stderr, \"%s:%d addr=%x count=%d\\n\", __FUNCTION__, __LINE__, addr, count);\n    fpgaDev->read32(addr, bytes); // always reads 4 bytes\n    fprintf(stderr, \"%s:%d addr=%x -> value %x count=%d\\n\", __FUNCTION__, __LINE__, addr, *(int *)bytes, count);\n    return true;\n}\n\nbool spikehw_device_t::store(reg_t addr, size_t len, const uint8_t* bytes)\n{\n    fpgaDev->write32(addr, bytes);\n    return true;\n}\n\nabstract_device_t *spikehw_device_t::make_device()\n{\n    std::cerr << \"make_device called\" << std::endl;\n    return new spikehw_device_t();\n}\n\nclass spikeflash_device_t : public abstract_device_t {\npublic:\n  spikeflash_device_t();\n  bool load(reg_t addr, size_t len, uint8_t* bytes);\n  bool store(reg_t addr, size_t len, const uint8_t* bytes);\n  static abstract_device_t *make_device();\n};\n\nspikeflash_device_t::spikeflash_device_t()\n{\n  if (!fpgaDev)\n    fpgaDev = new FpgaDev();\n}\n\nbool spikeflash_device_t::load(reg_t addr, size_t len, uint8_t* bytes)\n{\n    if (addr & 1 && len != 1) fprintf(stderr, \"spikeflash::load addr=%08lx len=%ld\\n\", addr, len);\n    if (addr & 1) {\n\tuint8_t data[2];\n\tfpgaDev->readFlash(addr, data); // always reads 4 bytes\n\tbytes[0] = data[1];\n\tif (len > 1)\n\t    return false;\n\telse\n\t    return true;\n    }\n\n    while (len) {\n\tfpgaDev->readFlash(addr, bytes); // always reads 4 bytes\n\tif (len < 2)\n\t    break;\n\taddr  += 2;\n\tbytes += 2;\n\tlen   -= 2;\n    }\n    return true;\n}\n\nbool spikeflash_device_t::store(reg_t addr, size_t len, const uint8_t* bytes)\n{\n    //fprintf(stderr, \"spikeflash::store addr=%08lx len=%ld bytes=%02x\\n\", addr, len, *(uint16_t *)bytes);\n    if (len != 2)\n      return false;\n    fpgaDev->writeFlash(addr, bytes);\n    return true;\n}\n\nabstract_device_t *spikeflash_device_t::make_device()\n{\n    std::cerr << \"spikeflash_device_t::make_device called\" << std::endl;\n    return new spikeflash_device_t();\n}\n\nclass devicetree_device_t : public abstract_device_t {\npublic:\n    devicetree_device_t();\n    bool load(reg_t addr, size_t len, uint8_t* bytes);\n    bool store(reg_t addr, size_t len, const uint8_t* bytes);\n    static abstract_device_t *make_device();\nprivate:\n    const char *dtb;\n    size_t dtbsz;\n};\n\ndevicetree_device_t::devicetree_device_t()\n{\n    int fd = open(\"devicetree.dtb\", O_RDONLY);\n    if (fd > 0) {\n\tstruct stat statbuf;\n\tint status = fstat(fd, &statbuf);\n\tfprintf(stderr, \"fstat status %d size %ld\\n\", status, statbuf.st_size);\n\tif (status == 0) {\n\t    dtb = (const char *)mmap(0, statbuf.st_size, PROT_READ, MAP_SHARED, fd, 0);\n\t    dtbsz = statbuf.st_size;\n\t    fprintf(stderr, \"mapped dtb at %p (%ld bytes)\\n\", dtb, dtbsz);\n\t}\n\tclose(fd);\n    } else {\n\tfprintf(stderr, \"Could not open devicetree.dtb\\n\");\n    }\n}\n\nbool devicetree_device_t::load(reg_t addr, size_t len, uint8_t* bytes)\n{\n    if (dtb && dtb != MAP_FAILED) {\n\tif ((addr < dtbsz) && (bytes != 0)) {\n\t    memcpy(bytes, dtb + addr, len);\n\t    return true;\n\t}\n    }\n    return false;\n}\n\nbool devicetree_device_t::store(reg_t addr, size_t len, const uint8_t* bytes)\n{\n    return true;\n}\n\nabstract_device_t *devicetree_device_t::make_device()\n{\n    std::cerr << \"devicetree_device_t::make_device called\" << std::endl;\n    return new devicetree_device_t();\n}\n\n//REGISTER_MEM_ALLOCATOR(FpgaDev::allocate_mem);\nREGISTER_DEVICE(devicetree, 0x04080000, devicetree_device_t::make_device);\nREGISTER_DEVICE(spikehw,    0x04100000, spikehw_device_t::make_device);\nREGISTER_DEVICE(spikeflash, 0x08000000, spikeflash_device_t::make_device);\n#endif\n\n#ifndef REGISTER_SPIKE_DEVICES\nextern \"C\" {\n\n    struct FpgaOps {\n\tuint64_t (*read)(uint64_t addr);\n\tvoid (*write)(uint64_t addr, uint64_t value);\n\tvoid (*close)();\n        void *(*alloc_mem)(size_t size);\n    };\n\n    uint64_t fpga_read(uint64_t addr)\n    {\n      uint64_t val = fpgaDev->read(0x100000 + addr);\n      return val;\n    }\n\n    void fpga_write(uint64_t addr, uint64_t value)\n    {\n\tfpgaDev->write(0x100000 + addr, value);\n    }\n\n    void fpga_close()\n    {\n    }\n\n    void *fpga_alloc_mem(size_t size)\n    {\n\treturn (void *)fpgaDev->allocate_mem(size);;\n    }\n\n    void *fpgadev_init(void (*irqCallback)(int irq)) {\n\tfprintf(stderr, \"connectal.so init called\\n\");\n\tif (!fpgaDev)\n\t    fpgaDev = new FpgaDev(irqCallback);\n\tstruct FpgaOps *ops = (struct FpgaOps *)malloc(sizeof(struct FpgaOps));\n\tops->read = fpga_read;\n\tops->write = fpga_write;\n\tops->close = fpga_close;\n\tops->alloc_mem = fpga_alloc_mem;\n\treturn ops;\n    }\n}\n#endif\n"
  },
  {
    "path": "lib/qemu/fpgadev.h",
    "content": "#ifndef SPIKEHW_H\n#define SPIKEHW_H\n\n#include <stdint.h>\n\nclass BlockDevResponseProxy; // responses sent to the risc-v\nclass BlockDevRequest;       // requests received from the risc-v\nclass MemServerPortalRequestProxy;\nclass MemServerPortalResponse;\nclass DmaManager;\nclass QemuAccelRequestProxy;\nclass QemuAccelIndication;\nclass SerialIndication;\nclass SerialRequest;\ntypedef void (*IrqCallback)(int irq);\n\n\nclass FpgaDev {\n public:\n  FpgaDev(IrqCallback callback=0);\n  ~FpgaDev();\n  int irq ( const uint8_t newLevel );\n  void status();\n  void read(unsigned long offset, uint8_t *buf);\n  void write(unsigned long offset, const uint8_t *buf);\n  uint32_t read(unsigned long offset);\n  void write(unsigned long offset, const uint32_t value);\n  void setFlashParameters(unsigned long cycles);\n  void readFlash(unsigned long offset, uint8_t *buf);\n  void writeFlash(unsigned long offset, const uint8_t *buf);\n  bool hasInterrupt();\n  void clearInterrupt();\n  char *allocate_mem(size_t memsz);\n private:\n  void setupDma( uint32_t memfd );\n\n  BlockDevResponseProxy       *blockDevResponse;\n  BlockDevRequest             *blockDevRequest;\n  MemServerPortalRequestProxy *request;\n  MemServerPortalResponse     *indication;\n  QemuAccelRequestProxy       *qemuAccelRequest;\n  QemuAccelIndication         *qemuAccelIndication;\n  SerialRequestProxy          *serialRequest;\n  SerialIndication            *serialIndication;\n  DmaManager                  *dmaManager;\n  bool didReset;\n  int mainMemFd;\n  char *mainMemBuf;\n\n  void maybeReset();\n  friend class BlockDevRequest;\n};\n\n#endif\n"
  },
  {
    "path": "lib/rbm/bsv/DmaVector.bsv",
    "content": "// Copyright (c) 2013 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\nimport Connectable::*;\nimport GetPut::*;\nimport ClientServer::*;\nimport FIFOF::*;\nimport ConnectalMemory::*;\nimport ConnectalMemTypes::*;\nimport MemReadEngine::*;\nimport MemWriteEngine::*;\nimport Adapter::*;\nimport BRAM::*;\nimport Pipe::*;\nimport RbmTypes::*;\nimport ConnectalMemTypes::*;\n\ntypedef 8 BurstLen;\n\ninterface VectorSource#(numeric type dsz, type a);\n   interface PipeOut#(a) pipe;\n   method Action start(SGLId h, Bit#(MemOffsetSize) a, Bit#(MemOffsetSize) l);\n   method ActionValue#(Bool) finish();\nendinterface\n\nmodule  mkMemReadVectorSource#(MemReadEngineServer#(asz) memreadServer)(VectorSource#(asz, a))\n   provisos (Bits#(a,asz),\n\t     Div#(asz,8,abytes),\n\t     Log#(abytes,ashift),\n\t     Mul#(abytes, 8, asz)\n\t     );\n   Bool verbose = False;\n   let asz = valueOf(asz);\n   let ashift = valueOf(ashift);\n   function Bit#(dataWidth) memData_data(MemDataF#(dataWidth) d); return d.data; endfunction\n\n   method Action start(SGLId p, Bit#(MemOffsetSize) a, Bit#(MemOffsetSize) l);\n      if (verbose) $display(\"mkMemReadVectorSource: start h=%d a=%h l=%h ashift=%d\", p, a, l, ashift);\n      memreadServer.request.put(MemengineCmd { sglId: p, base: a << ashift, len: truncate(l << ashift), burstLen: (fromInteger(valueOf(BurstLen)) << ashift), tag: 0});\n   endmethod\n   method ActionValue#(Bool) finish();\n      return memreadServer.data.first().last;\n   endmethod\n   interface PipeOut pipe = mapPipe(unpack, mapPipe(memData_data, memreadServer.data));\nendmodule\n\ninterface VectorSink#(numeric type dsz, type a);\n   interface PipeIn#(a) pipe;\n   method Action start(SGLId h, Bit#(MemOffsetSize) a, Bit#(MemOffsetSize) l);\n   method ActionValue#(Bool) finish();\nendinterface\n\nmodule  mkMemWriteVectorSink#(MemWriteEngineServer#(asz) memwriteServer)(VectorSink#(asz, a))\n   provisos (Bits#(a,asz),\n\t     Div#(asz,8,abytes),\n\t     Log#(abytes,ashift),\n\t     Mul#(abytes, 8, asz)\n\t     );\n   Bool verbose = False;\n   let asz = valueOf(asz);\n   let ashift = valueOf(ashift);\n\n   method Action start(SGLId p, Bit#(MemOffsetSize) a, Bit#(MemOffsetSize) l);\n      if (verbose) $display(\"mkMemWriteVectorSink: start h=%d a=%h l=%h ashift=%d\", p, a, l, ashift);\n      // I set burstLen==1 so that testmm works for all J,K,N. If we want burst writes we will need to rethink this (mdk)\n      let cmd = MemengineCmd { sglId: p, base: a << ashift, len: truncate(l << ashift), burstLen: fromInteger(valueOf(abytes)), tag: 0};\n      memwriteServer.request.put(cmd);\n      //$display(\"mkMemWriteVectorSink: %d %d %d %d\", cmd.sglId, cmd.base, cmd.len, cmd.burstLen);\n   endmethod\n   method finish = memwriteServer.done.get;\n   interface PipeIn pipe = mapPipeIn(pack, memwriteServer.data);\nendmodule\n"
  },
  {
    "path": "lib/rbm/bsv/Rbm.bsv",
    "content": "// Copyright (c) 2014 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\nimport Vector::*;\nimport FIFO::*;\nimport FIFOF::*;\nimport DefaultValue::*;\nimport GetPut::*;\nimport ClientServer::*;\nimport Connectable::*;\nimport FloatingPoint::*;\nimport BRAM::*;\nimport ConnectalMemory::*;\nimport ConnectalMemTypes::*;\nimport DmaVector::*;\nimport HostInterface::*;\nimport MemReadEngine::*;\nimport MemWriteEngine::*;\nimport MatrixTN::*;\nimport Timer::*;\nimport Sigmoid::*;\nimport FloatOps::*;\nimport Pipe::*;\nimport RbmTypes::*;\nimport DotProdServer::*;\n\nfunction Float tokenValue(MmToken v) = v.v;\n\ninterface StatesPipe#(numeric type n, numeric type dmasz);\n   method Action start(Bit#(32) readPointer, Bit#(32) readOffset,\n\t\t       Bit#(32) readPointer2, Bit#(32) readOffset2,\n\t\t       Bit#(32) writePointer, Bit#(32) writeOffset, Bit#(32) numElts);\n   method ActionValue#(Bool) finish();\nendinterface\n   \n   \nmodule  mkComputeStatesPipe#(PipeOut#(Vector#(n, Float)) pipe_in, \n\t\t\t     PipeOut#(Vector#(n, Float)) randomPipe,\n\t\t\t     PipeIn#(Vector#(n,Float))   writePipe)(PipeOut#(Vector#(n, Float)))\n   provisos(Add#(a__, 1, n));\n   function Float greater(Float a, Float b);\n      if (compareFP(a, b) == GT)\n\t return 1.0;\n      else\n\t return 0.0;\n   endfunction\n   function Vector#(n, Float) vgreater(Vector#(n, Float) x, Vector#(n, Float) y);\n      return map(uncurry(greater), zip(x, y));\n   endfunction\n   rule foo;\n      let vs <- toGet(pipe_in).get;\n      let rs <- toGet(randomPipe).get;\n      let gs = vgreater(vs, rs); \n      //$display($format(fshow(\"vs=\")+fshow(pack(vs)) + fshow(\" rs=\") + fshow(pack(rs)) + fshow(\" states=\") + fshow(gs)));\n      writePipe.enq(gs);\n   endrule\nendmodule\n   \n   \n   \nmodule  mkStatesPipe#(Vector#(2,MemReadEngineServer#(TMul#(N,32))) readSrvrs,\n\t\t      Vector#(1,MemWriteEngineServer#(TMul#(N,32))) writeSrvrs)(StatesPipe#(N, DmaSz))\n   provisos ( Bits#(Vector#(N, Float), DmaSz)\n\t     ,Log#(N,nshift));\n   \n   let verbose = True;\n   let nshift = valueOf(nshift);\n   \n   Vector#(2, VectorSource#(DmaSz, Vector#(N,Float))) statesources <- mapM(mkMemReadVectorSource, readSrvrs);\n   VectorSink#(DmaSz, Vector#(N, Float)) dmaStatesSink <- mkMemWriteVectorSink(writeSrvrs[0]);\n   PipeOut#(Vector#(N, Float)) dmaStatesPipe <- mkComputeStatesPipe(statesources[0].pipe, statesources[1].pipe, dmaStatesSink.pipe);\n\n   method Action start(Bit#(32) readPointer, Bit#(32) readOffset,\n\t\t       Bit#(32) readPointer2, Bit#(32) readOffset2,\n\t\t       Bit#(32) writePointer, Bit#(32) writeOffset, Bit#(32) numElts);\n      statesources[0].start(readPointer, extend(readOffset), extend(unpack(numElts)>>nshift));\n      statesources[1].start(readPointer2, extend(readOffset2), extend(unpack(numElts)>>nshift));\n      dmaStatesSink.start(writePointer, extend(writeOffset), extend(unpack(numElts)>>nshift));\n      if (verbose) $display(\"mkStatesPipe::start(%d %d %d %d %d %d)\", readPointer, readOffset, readPointer2, readOffset2, writePointer, writeOffset, numElts);\n   endmethod\n   method ActionValue#(Bool) finish();\n      let x0 <- statesources[0].finish;\n      let x1 <- statesources[1].finish;\n      let b <- dmaStatesSink.finish;\n      return b;\n   endmethod\nendmodule\n\ninterface UpdateWeights#(numeric type n, numeric type dmasz);\n   method Action start(Bit#(32) posAssociationsPointer, Bit#(32) negAssociationsPointer, \n\t\t       Bit#(32) weightsPointer, Bit#(32) numElts, Float learningRateOverNumExamples);\n   method ActionValue#(Bool) finish();\nendinterface\n\nmodule  mkUpdateWeights#(Vector#(3,MemReadEngineServer#(TMul#(N,32))) readSrvrs,\n\t\t\t    Vector#(1,MemWriteEngineServer#(TMul#(N,32))) writeSrvrs)(UpdateWeights#(N, DmaSz))\n   provisos ( Bits#(Vector#(N, Float), DmaSz)\n\t     ,Log#(N,nshift));\n\n   Vector#(3, VectorSource#(DmaSz, Vector#(N,Float))) sources <- mapM(mkMemReadVectorSource, readSrvrs);\n\n   let n = valueOf(N);\n   let nshift = valueOf(nshift);\n\n   Reg#(Float) learningRateOverNumExamples <- mkReg(defaultValue);\n\n   Vector#(N, FloatAlu) adders <- replicateM(mkFloatAdder(defaultValue));\n   Vector#(N, FloatAlu) adders2 <- replicateM(mkFloatAdder(defaultValue));\n   Vector#(N, FloatAlu) multipliers <- replicateM(mkFloatMultiplier(defaultValue));\n   VectorSink#(DmaSz, Vector#(N, Float)) sink <- mkMemWriteVectorSink(writeSrvrs[0]);\n\n// weights += learningRate * (pos_associations - neg_associations) / num_examples;\n   rule sub;\n      let pa = sources[0].pipe.first();\n      sources[0].pipe.deq();\n      let na = sources[1].pipe.first();\n      sources[1].pipe.deq();\n      for (Integer i = 0; i < n; i = i+1) begin\n\t adders[i].request.put(tuple2(pa[i], -na[i]));\n      end\n   endrule\n   rule mul;\n      for (Integer i = 0; i < n; i = i+1) begin\n\t let sumexc <- adders[i].response.get();\n\t multipliers[i].request.put(tuple2(learningRateOverNumExamples, tpl_1(sumexc)));\n      end\n   endrule\n   rule add;\n      let weights = sources[2].pipe.first();\n      sources[2].pipe.deq();\n      for (Integer i = 0; i < n; i = i+1) begin\n\t let resultexc <- multipliers[i].response.get();\n\t adders2[i].request.put(tuple2(weights[i], tpl_1(resultexc)));\n      end\n   endrule\n   rule result;\n      Vector#(N, Float) r;\n      for (Integer i = 0; i < n; i = i+1) begin\n\t let resultexc <- adders2[i].response.get();\n\t r[i] = tpl_1(resultexc);\n      end\n      sink.pipe.enq(r);\n   endrule\n\n   for (Integer i = 0; i < 3; i = i + 1)\n      rule finishSources;\n\t let b <- sources[i].finish();\n      endrule\n\n   method Action start(Bit#(32) posAssociationsPointer, Bit#(32) negAssociationsPointer, Bit#(32) weightsPointer, Bit#(32) numElts, Float lrone);\n      learningRateOverNumExamples <= lrone;\n      sources[0].start(posAssociationsPointer, 0, extend(numElts)>>nshift);\n      sources[1].start(negAssociationsPointer, 0, extend(numElts)>>nshift);\n      sources[2].start(weightsPointer, 0, extend(numElts)>>nshift);\n      sink.start(weightsPointer, 0, extend(numElts)>>nshift);\n   endmethod\n   method ActionValue#(Bool) finish();\n      let b <- sink.finish();\n      return b;\n   endmethod\nendmodule\n   \ninterface SumOfErrorSquaredDebug;\n   interface PipeOut#(Bit#(32)) macCount;\nendinterface\n\ninterface SumOfErrorSquared#(numeric type n, numeric type dmasz);\n   interface PipeOut#(Float) pipe;\n   method Action start(Bit#(32) dataPointer, Bit#(32) predPointer, Bit#(32) numElts);\n   interface SumOfErrorSquaredDebug debug;\nendinterface\n\nmodule  mkSumOfErrorSquared#(Vector#(2,MemReadEngineServer#(TMul#(N,32))) readSrvrs)(SumOfErrorSquared#(N, DmaSz))\n   provisos ( Bits#(Vector#(N, Float), DmaSz)\n\t     ,Log#(N,nshift));\n   \n   Vector#(2, VectorSource#(DmaSz, Vector#(N,Float))) sources <- mapM(mkMemReadVectorSource, readSrvrs);\n   let n = valueOf(N);\n   let nshift = valueOf(nshift);\n   SharedDotProdServer#(1) dotprod <- mkSharedInterleavedDotProdServerConfig(0);\n\n   FirstLastPipe#(Bit#(MemOffsetSize)) firstlastPipe <- mkFirstLastPipe();\n   PipeOut#(Float) aPipe <- mkFunnel1(sources[0].pipe);\n   PipeOut#(Float) bPipe <- mkFunnel1(sources[1].pipe);\n   let joinPipe <- mkJoin(tuple2, aPipe, bPipe);\n   let subPipe <- mkFloatSubPipe(joinPipe);\n   rule fromsub;\n      match {.first, .last} <- toGet(firstlastPipe.pipe).get();\n      let diff <- toGet(subPipe).get();\n      MmToken t = MmToken { v: diff, first: first, last: last };\n      dotprod.aInput.put(t);\n      dotprod.bInput.put(t);\n      //$display(\"%d %d\", first, last);\n   endrule\n\n   for (Integer i = 0; i < 2; i = i + 1)\n      rule finishSources;\n\t let b <- sources[i].finish();\n      endrule\n\n   interface PipeOut pipe = mapPipe(tokenValue, dotprod.pipes[0]);\n   method Action start(Bit#(32) dataPointer, Bit#(32) predPointer, Bit#(32) numElts);\n      sources[0].start(dataPointer, 0, extend(numElts)>>nshift);\n      sources[1].start(predPointer, 0, extend(numElts)>>nshift);\n      firstlastPipe.start(extend(numElts));\n   endmethod\n   interface SumOfErrorSquaredDebug debug;\n      interface PipeOut macCount = dotprod.debug.macCount;\n   endinterface\nendmodule: mkSumOfErrorSquared\n\ninterface Rbm#(numeric type n);\n   interface RbmRequest rbmRequest;\n   interface SigmoidRequest sigmoidRequest;\n   interface MmRequestTN mmRequest;\n   interface TimerRequest timerRequest;\n   interface Vector#(3,MemReadClient#(TMul#(32,n))) readClients;\n   interface Vector#(3,MemWriteClient#(TMul#(32,n))) writeClients;\nendinterface\n\nmodule  mkRbm#(HostInterface host, RbmIndication rbmInd, SigmoidIndication sigmoidInd, MmIndication mmInd, TimerIndication timerInd)(Rbm#(N))\n   provisos (Add#(1,a__,N),\n\t     Add#(N,0,n),\n\t     Mul#(N,32,DmaSz));\n   let n = valueOf(n);\n   \n   // TODO: figure out the correct amount of buffering required\n   MemReadEngine#(TMul#(n,32),TMul#(n,32),2, 9) readEngine  <- mkMemReadEngine;\n   MemWriteEngine#(TMul#(n,32),TMul#(n,32),2, 3) writeEngine <- mkMemWriteEngine;\n   \n   let res = readEngine.readServers;\n   let wes = writeEngine.writeServers;\n   \n   SigmoidIfc#(TMul#(32,n)) sigmoid <- mkSigmoid(takeAt(0,res), takeAt(0,wes)); // 2 read, 1 write\n   StatesPipe#(N, DmaSz) states <- mkStatesPipe(takeAt(2,res), takeAt(1,wes));  // 2 read, 1 write\n   UpdateWeights#(N, DmaSz) updateWeights <- mkUpdateWeights(takeAt(4,res), takeAt(2,wes)); // 3 read, 1 write\n   SumOfErrorSquared#(N, DmaSz) sumOfErrorSquared <- mkSumOfErrorSquared(takeAt(7,res));       // 2 read, 0 write\n   MmTNInternal#(N) mm <- mkMmTNInternal(host);\n   \n   ///////////////////////////////////////////////\n   // timing cruft\n\n   FIFOF#(Bool) busyFifo <- mkFIFOF();\n   FIFOF#(Bool) timerRunning <- mkFIFOF();\n   Reg#(Bit#(64)) cycleCount <- mkReg(0);\n   Reg#(Bit#(64)) idleCount <- mkReg(0);\n   rule countCycles if (timerRunning.notEmpty());\n      cycleCount <= cycleCount + 1;\n      if (!busyFifo.notEmpty())\n\t idleCount <= idleCount + 1;\n   endrule\n\n   ///////////////////////////////////////////////\n   \n   ///////////////////////////////////////////////\n   // sigmoid indication\n   \n   rule sigmoidDone;\n      sigmoid.sigmoidDone();\n      sigmoidInd.sigmoidDone();\n      busyFifo.deq;\n   endrule\n   \n   rule sigmoidTableUpdateDone;\n      let b <- sigmoid.updateDone();\n      sigmoidInd.tableUpdated(0);\n      busyFifo.deq;\n   endrule\n   \n   ///////////////////////////////////////////////\n   \n   ///////////////////////////////////////////////\n   // mm indication\n\n   rule mmfDone;\n      let d <- mm.mmfDone;\n      busyFifo.deq();\n      mmInd.mmfDone(d);\n   endrule\n   \n   rule mmDebugDone;\n      let d <- mm.debugDone;\n      mmInd.debug(d);\n   endrule\n\n   FIFO#(Bit#(32)) sumOfErrorSquaredDebugFifo <- mkFIFO();\n   rule sumOfErrorSquaredDebugRule;\n      let unused <- toGet(sumOfErrorSquaredDebugFifo).get();\n      let macCount <- toGet(sumOfErrorSquared.debug.macCount).get();\n      rbmInd.sumOfErrorSquaredDebug(macCount);\n   endrule\n\n   ///////////////////////////////////////////////\n   \n   ///////////////////////////////////////////////\n   // rbm indication\n\n   rule statesDone;\n      $display(\"statesDone\");\n      let b <- states.finish();\n      rbmInd.statesDone();\n      busyFifo.deq;\n   endrule\n\n   rule updateWeightsDone;\n      $display(\"updateWeightsDone\");\n      let b <- updateWeights.finish();\n      rbmInd.updateWeightsDone();\n      busyFifo.deq;\n   endrule\n\n   rule sumOfErrorSquaredDone;\n      $display(\"sumOfErrorSquaredDone\");\n      sumOfErrorSquared.pipe.deq();\n      rbmInd.sumOfErrorSquared(pack(sumOfErrorSquared.pipe.first()));\n      busyFifo.deq;\n   endrule\n   \n   ///////////////////////////////////////////////\n   \n   interface TimerRequest timerRequest;\n      method Action startTimer() if (!timerRunning.notEmpty());\n\t cycleCount <= 0;\n\t idleCount <= 0;\n\t timerRunning.enq(True);\n      endmethod\n      method Action stopTimer();\n\t timerRunning.deq();\n\t timerInd.elapsedCycles(cycleCount, idleCount);\n      endmethod\n   endinterface\n   interface MmRequestTN mmRequest;\n      method Action mmf(Bit#(32) h1, Bit#(32) r1, Bit#(32) c1,\n\t\t\tBit#(32) h2, Bit#(32) r2, Bit#(32) c2,\n\t\t\tBit#(32) h3,\n\t\t\tBit#(32) r1_x_c1, Bit#(32) c1_x_j,\n\t\t\tBit#(32) r1_x_c2, Bit#(32) c2_x_j,\n\t\t\tBit#(32) c1_x_c2, Bit#(32) r2_x_c2);\n\t mm.mmRequest.mmf(h1,r1,c1,\n\t\t\t  h2,r2,c2,\n\t\t\t  h3,\n\t\t\t  r1_x_c1, c1_x_j,\n\t\t\t  r1_x_c2, c2_x_j,\n\t\t\t  c1_x_c2, r2_x_c2);\n\t busyFifo.enq(True);\n      endmethod\n      method Action debug = mm.mmRequest.debug;\n   endinterface\n   interface RbmRequest rbmRequest;\n      method Action finish();\n\t $finish(0);\n      endmethod\n      method Action computeStates(Bit#(32) readPointer, Bit#(32) readOffset,\n\t\t\t\t  Bit#(32) readPointer2, Bit#(32) readOffset2,\n\t\t\t\t  Bit#(32) writePointer, Bit#(32) writeOffset, Bit#(32) numElts);\n\t states.start(readPointer, readOffset,\n\t\t      readPointer2, readOffset2,\n\t\t      writePointer,writeOffset, numElts);\n\t busyFifo.enq(True);\n      endmethod\n      method Action updateWeights(Bit#(32) posAssociationsPointer,\n\t Bit#(32) negAssociationsPointer,\n\t\t\t\t  Bit#(32) weightsPointer,\n\t\t\t\t  Bit#(32) numElts,\n\t\t\t\t  Bit#(32) learningRateOverNumExamples);\n\t updateWeights.start(posAssociationsPointer, negAssociationsPointer, \n\t\t\t     weightsPointer, numElts, \n\t\t\t     unpack(learningRateOverNumExamples));\n\t busyFifo.enq(True);\n      endmethod\n      method Action sumOfErrorSquared(Bit#(32) dataPointer, Bit#(32) predPointer, Bit#(32) numElts);\n\t sumOfErrorSquared.start(dataPointer, predPointer, numElts);\n\t busyFifo.enq(True);\n      endmethod\n      method Action sumOfErrorSquaredDebug();\n\t sumOfErrorSquaredDebugFifo.enq(0);\n      endmethod\n   endinterface   \n   interface SigmoidRequest sigmoidRequest;\n      method Action sigmoid(Bit#(32) readPointer, Bit#(32) readOffset,\n   \t\t\t    Bit#(32) writePointer, Bit#(32) writeOffset, Bit#(32) numvalues);\n\t sigmoid.sigmoidRequest.sigmoid(readPointer, readOffset, writePointer, writeOffset, numvalues);\n\t busyFifo.enq(True);\n      endmethod\n      method Action setLimits(Bit#(32) rscale, Bit#(32) llimit, Bit#(32) ulimit);\n\t sigmoid.sigmoidRequest.setLimits(rscale, llimit, ulimit);\n      endmethod\n      method Action updateTable(Bit#(32) readPointer, Bit#(32) readOffset, Bit#(32) numvalues);\n\t sigmoid.sigmoidRequest.updateTable(readPointer, readOffset, numvalues);\n\t busyFifo.enq(True);\n      endmethod\n      method Action tableSize();\n\t sigmoidInd.tableSize(sigmoid.tableSize);\n      endmethod\n   endinterface\n   interface Vector readClients = cons(readEngine.dmaClient,mm.readClients);\n   interface Vector writeClients = cons(writeEngine.dmaClient,mm.writeClients);\nendmodule\n"
  },
  {
    "path": "lib/rbm/bsv/RbmTypes.bsv",
    "content": "// Copyright (c) 2014 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\n\n`include \"ConnectalProjectConfig.bsv\"\nimport FloatingPoint::*;\n\ntypedef 20 MMSize;\n\n`ifdef DataBusWidth\ntypedef TDiv#(`DataBusWidth,32) N;\n`else\n`ifndef N_VALUE\ntypedef 1 N;\n`else\ntypedef `N_VALUE N;\n`endif\n`endif\n\n`ifndef J_VALUE\ntypedef 1 J;\n`else\ntypedef `J_VALUE J;\n`endif\n`ifndef K_VALUE\ntypedef 1 K;\n`else\ntypedef `K_VALUE K;\n`endif\n\ntypedef `NumberOfMasters NumberOfMasters;\n\ntypedef TMin#(4,J) RowsPerTile;\ntypedef TDiv#(J,RowsPerTile) T;\ntypedef TMul#(32,N) DmaSz;\n\ninterface MmIndication;\n   method Action started();\n   method Action startSourceAndSink(UInt#(32) startA, UInt#(32) startC, Int#(32) jint);\n   method Action debug(Bit#(32) macCount);\n   method Action mmfDone(Bit#(64) cycles);\nendinterface\n\ninterface MmRequestNT;\n   method Action debug();\n   method Action mmf(Bit#(32) inPointer1, Bit#(32) r1, Bit#(32) c1,\n\t\t     Bit#(32) inPointer2, Bit#(32) r2, Bit#(32) c2,\n\t\t     Bit#(32) outPointer,\n\t\t     Bit#(32) r1_x_c1, Bit#(32) c1_x_j,\n\t\t     Bit#(32) r2_x_c2, Bit#(32) c2_x_k,\n\t\t     Bit#(32) r1_x_r1, Bit#(32) r2_x_j);\nendinterface\n\ninterface MmRequestTN;\n   method Action debug();\n   method Action mmf(Bit#(32) inPointer1, Bit#(32) r1, Bit#(32) c1,\n\t\t     Bit#(32) inPointer2, Bit#(32) r2, Bit#(32) c2,\n\t\t     Bit#(32) outPointer,\n\t\t     Bit#(32) r1_x_c1, Bit#(32) c1_x_j,\n\t\t     Bit#(32) r1_x_c2, Bit#(32) c2_x_j,\n\t\t     Bit#(32) c1_x_c2, Bit#(32) r2_x_c2);\nendinterface\n\ninterface SigmoidIndication;\n   method Action sigmoidDone();\n   method Action tableSize(Bit#(32) size);\n   method Action tableUpdated(Bit#(32) addr);\nendinterface\n\ninterface SigmoidRequest;\n    method Action sigmoid(Bit#(32) readPointer, Bit#(32) readOffset, Bit#(32) writePointer, Bit#(32) writeOffset, Bit#(32) numElts);\n    method Action setLimits(Bit#(32) rscale, Bit#(32) llimit, Bit#(32) ulimit);\n    method Action tableSize();\n    method Action updateTable(Bit#(32) readPointer, Bit#(32) readOffset, Bit#(32) numElts);\nendinterface\n\ninterface RbmIndication;\n   method Action statesDone();\n   method Action updateWeightsDone();\n   method Action sumOfErrorSquared(Bit#(32) error);\n   method Action sumOfErrorSquaredDebug(Bit#(32) macCount);\n   method Action dbg(Bit#(32) a, Bit#(32) b, Bit#(32) c, Bit#(32) d);\nendinterface\n\ninterface RbmRequest;\n   //method Action sglist(Bit#(32) off, Bit#(40) addr, Bit#(32) len);\n   method Action paref(Bit#(32) addr, Bit#(32) len);\n   method Action computeStates(Bit#(32) readPointer, Bit#(32) readOffset,\n\t\t\t       Bit#(32) readPointer2, Bit#(32) readOffset2,\n\t\t\t       Bit#(32) writePointer, Bit#(32) writeOffset, Bit#(32) numElts);\n   method Action updateWeights(Bit#(32) posAssociationsPointer, Bit#(32) negAssociationsPointer,\n\t\t\t       Bit#(32) weightsPointer, Bit#(32) numElts, Bit#(32) learningRateOverNumExamples);\n   method Action sumOfErrorSquared(Bit#(32) dataPointer, Bit#(32) predPointer, Bit#(32) numElts);\n   method Action sumOfErrorSquaredDebug();\n   method Action finish(); // for bsim only\nendinterface\n\nfunction Action check_dimension(Bit#(32) d);\n   return (action\n      Bit#(32) x = d/fromInteger(valueOf(N));\n      Bit#(32) y = x*fromInteger(valueOf(N));\n      if (y != d) begin\n      \t $display(\"matrix dimension %d is not a multiple of %d\", d, valueOf(N));\n      \t $finish(1);\n      end\n      endaction);\nendfunction\n"
  },
  {
    "path": "lib/rbm/bsv/Sigmoid.bsv",
    "content": "/* Copyright (c) 2014 Quanta Research Cambridge, Inc\n *\n * Permission is hereby granted, free of charge, to any person obtaining a\n * copy of this software and associated documentation files (the \"Software\"),\n * to deal in the Software without restriction, including without limitation\n * the rights to use, copy, modify, merge, publish, distribute, sublicense,\n * and/or sell copies of the Software, and to permit persons to whom the\n * Software is furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n * DEALINGS IN THE SOFTWARE.\n */\nimport RegFile::*;\nimport FIFO::*;\nimport FIFOF::*;\nimport Vector::*;\nimport Connectable::*;\nimport ClientServer::*;\nimport Memory::*;\nimport BRAM::*;\nimport DefaultValue::*;\nimport FloatingPoint::*;\nimport Real::*;\nimport ConnectalMemory::*;\nimport ConnectalMemTypes::*;\nimport DmaVector::*;\nimport Pipe::*;\nimport FloatOps::*;\nimport RbmTypes::*;\nimport BUtils::*;\n\ninterface SigmoidTable#(numeric type tsz);\n   interface Vector#(2, BRAMServer#(Bit#(tsz), Vector#(3,Float))) ports;\n   interface ReadOnly#(Float) rscale;\n   interface ReadOnly#(Float) llimit;\n   interface ReadOnly#(Float) ulimit;\n   method Action setSigmoidLimits(Float rscale, Float llimit, Float ulimit);\n   method Action updateSigmoidTable(Bit#(tsz) addr, Vector#(3,Float) v);\n   method Bit#(32) tableSize();\nendinterface\n\nmodule mkSigmoidTable(SigmoidTable#(tsz));\n   let tsz = valueOf(tsz);\n   BRAM_Configure bramCfg = defaultValue;\n   let memorySize = 2**tsz;\n   bramCfg.memorySize = memorySize;\n   BRAM2Port#(Bit#(tsz), Vector#(3, Float)) sigmoidTable <- mkBRAM2Server(bramCfg);\n\n   Reg#(Float) rscaleReg <- mkReg(fromReal(0.0));\n   Reg#(Float) llimitReg <- mkReg(fromReal(0.0));\n   Reg#(Float) ulimitReg <- mkReg(fromReal(0.0));\n\n   Vector#(2, BRAMServer#(Bit#(tsz), Vector#(3,Float))) bramPorts;\n   bramPorts[0] = sigmoidTable.portA;\n   bramPorts[1] = sigmoidTable.portB;\n\n   interface ReadOnly rscale = regToReadOnly(rscaleReg);\n   interface ReadOnly llimit = regToReadOnly(llimitReg);\n   interface ReadOnly ulimit = regToReadOnly(ulimitReg);\n   interface Vector ports = bramPorts;\n   method Action setSigmoidLimits(Float _rscale, Float _llimit, Float _ulimit);\n      $display(\"setSigmoidLimits memorySize=%d\\n\", memorySize);\n      rscaleReg <= _rscale;\n      llimitReg <= _llimit;\n      ulimitReg <= _ulimit;\n      $display($format(\"rscale=\", fshow(_rscale), \"pack(rscale)=\", fshow(pack(_rscale)), \" llimit=\", fshow(_llimit), \" ulimit=\", fshow(_ulimit)));\n   endmethod\n   method Action updateSigmoidTable(Bit#(tsz) addr, Vector#(3,Float) v);\n      sigmoidTable.portB.request.put(BRAMRequest{ write: True, responseOnWrite: False, address: addr, datain: v});\n   endmethod\n   method Bit#(32) tableSize();\n      return (1 << tsz);\n   endmethod\nendmodule\n\n// Why was this not picked up from FloatingPoint.bsv???\nfunction Integer bias( FloatingPoint#(e,m) din );\n   return (2 ** (valueof(e)-1)) - 1;\nendfunction\n\nfunction Int#(32) toInt32(FloatingPoint#(e,m) din);\n   Int#(32) res = 0;\n\n   if (isNaN(din))\n      res = 0;\n   else if (isInfinity(din))\n      res = (din.sign) ? unpack('h80000000) : unpack('h7FFFFFFF);\n   else begin\n      // if the quantity is less than +/-1, it is zero.\n      if (din.exp >= fromInteger(bias(din))) begin\n\t // be sure to re-add the hidden bit when converting.\n\t Bit#(TAdd#(m,1)) y = { 1, din.sfd };\n\t y = y >> (fromInteger(bias(din)) + fromInteger(valueOf(m)) - din.exp);\n\t Bit#(32) r = cExtend(y);\n\n\t if (din.sign) res = unpack(~r + 1);\n\t else          res = unpack(r);\n      end\n   end\n   return res;\nendfunction\n\nmodule mkSigmoidServer#(Integer id, SigmoidTable#(tsz) sigmoidTable)(Server#(Float,Float))\n   provisos (Add#(tsz,2,usz),\n\t     Add#(a__, usz, 32)\n\t     );\n   let tsz = valueOf(tsz);\n   Int#(usz) numEntries = 1<<fromInteger(tsz);\n   // linear approximation around in range [-8,8]\n\n   Bool verbose = False;\n   FIFOF#(Float) angleFifo <- mkSizedFIFOF(4);\n   Vector#(2,FloatAlu) mul   <- replicateM(mkFloatMultiplier(defaultValue));\n   Vector#(2,FloatAlu) adder <- replicateM(mkFloatAdder(defaultValue));\n   let adder_fifo <- mkFIFO;\n   \n   rule lookupEntry;\n      let response <- mul[1].response.get();\n      Float scaled_angle = tpl_1(response);\n      Exception e = tpl_2(response);\n      if (verbose && pack(e) != 0) $display(\"lookup.exception e=%h scaled_angle=%h\", e, pack(scaled_angle));\n      \n      Int#(usz) i = truncate(toInt32(scaled_angle));\n      Bit#(tsz) index = truncate(pack(i + numEntries/2));\n      if (i > (numEntries/2-1))\n\t index = truncate(pack(numEntries-1));\n      if (i < -numEntries/2)\n\t index = 0;\n      if (verbose) $display(\"sigmoid lookupEntry i=%d index=%d numEntries=%d\", i, index, numEntries);\n      sigmoidTable.ports[0].request.put(BRAMRequest{ write: False, responseOnWrite: False, address: index, datain: ?});\n   endrule\n\n   FIFOF#(Vector#(3, Float)) vFifo <- mkFIFOF();\n   rule computeDelta;\n      let vs <- sigmoidTable.ports[0].response.get();\n      let angle <- toGet(angleFifo).get;\n      if (verbose) $display(\"computeDelta angle=%h vs[0]=%h\", pack(angle), pack(vs[0]));\n      adder[1].request.put(tuple2(angle, vs[0]));\n      vFifo.enq(vs);\n   endrule\n\n   rule interpolate;\n      let vs <- toGet(vFifo).get;\n      let result <- adder[1].response.get();\n      let delta = tpl_1(result);\n      Exception e = tpl_2(result);\n      if (verbose && pack(e) != 0) $display(\"interpolate.exception e=%h delta=%h\", e, pack(delta));\n      if (verbose) $display(\"sigmoid interpolate delta=%h vs[1]=%h vs[2]\", pack(delta), pack(vs[1]), pack(vs[2]));\n      mul[0].request.put(tuple2(vs[2],delta));\n      adder_fifo.enq(vs[1]);\n   endrule\n   \n   rule accumulate;\n      match {.p, .*} <- mul[0].response.get;\n      let v <- toGet(adder_fifo).get;\n      adder[0].request.put(tuple2(v,p));\n   endrule\n   \n   interface Put request;\n      method Action put(Float angle);\n\t let c = compareFP(angle, sigmoidTable.llimit);\n\t let d = compareFP(angle, sigmoidTable.ulimit);\n\t if (c == LT)\n\t    angle = sigmoidTable.llimit;\n\t if (d == GT)\n\t    angle = sigmoidTable.ulimit;\n\t angleFifo.enq(angle);\n\t mul[1].request.put(tuple2(angle, sigmoidTable.rscale));\n\t if (verbose) $display(\"sigmoid request.put\");\n      endmethod\n   endinterface\n   interface Get response;\n      method ActionValue#(Float) get();\n\t match {.v,.e} <- adder[0].response.get();\n\t if (verbose && pack(e) != 0) $display(\"adder[0].exception e=%h v=%h\", e, pack(v));\n\t if (verbose) $display(\"sigmoid response.get\");\n\treturn v;\n     endmethod\n   endinterface\nendmodule\n\ninterface SigmoidIfc#(numeric type dsz);\n   interface SigmoidRequest sigmoidRequest;\n   method Action sigmoidDone;\n   method Action updateDone;\n   method Bit#(32) tableSize;\nendinterface\n\nmodule  mkSigmoid#(Vector#(2,MemReadEngineServer#(TMul#(N,32))) readSrvrs,\n\t\t   Vector#(1,MemWriteEngineServer#(TMul#(N,32))) writeSrvrs) (SigmoidIfc#(dsz))\n   provisos (Bits#(Float, fsz)\n\t     , Add#(N,0,n)\n\t     , Mul#(fsz,N,dmasz)\n\t     , Bits#(Vector#(N,Float), dsz)\n\t     , Mul#(dbytes, 8, dsz)\n\t     , Div#(dsz, 8, dbytes)\n\t     , Log#(n,nshift)\n\t     );\n   let nshift = valueOf(nshift);\n   Bool verbose = False;\n   VectorSource#(dmasz, Vector#(n,Float)) source <- mkMemReadVectorSource(readSrvrs[0]);\n   VectorSource#(dmasz, Vector#(n,Float)) tabsrc <- mkMemReadVectorSource(readSrvrs[1]);\n\n   Vector#(n, SigmoidTable#(6)) sigmoidTables <- replicateM(mkSigmoidTable);\n   Vector#(n, Server#(Float,Float)) sigmoidServers <- mapM(uncurry(mkSigmoidServer), zip(genVector,sigmoidTables));\n\n   Reg#(Bool) updatingSigmoidTable <- mkReg(False);\n   Reg#(Bit#(6)) entryNumber <- mkReg(0);\n\n   PipeOut#(Vector#(4, Float)) tabsrcs <- mkUnfunnel(tabsrc.pipe);\n   Reg#(Bit#(32)) count <- mkReg(0);\n   VectorSink#(TMul#(N,32),Vector#(N,Float)) sinkC <- mkMemWriteVectorSink(writeSrvrs[0]);\n\n   rule updateSigmoidTableRule if (updatingSigmoidTable);\n      let vs <- toGet(tabsrcs).get;\n      if (verbose) $display(\"updateSigmaTableRule vs[0]=%h entryNumber=%d\", vs[0], entryNumber);\n      Vector#(3,Float) vs3 = take(vs);\n      for (Integer i = 0; i < valueOf(n); i = i + 1) begin\n\t sigmoidTables[i].updateSigmoidTable(entryNumber, vs3);\n      end\n      entryNumber <= entryNumber + 1;\n   endrule\n\n   Reg#(Bit#(32)) countInput <- mkReg(0);\n   rule consumeInput if (!updatingSigmoidTable);\n      let vs <- toGet(source.pipe).get;\n      for (Integer i = 0; i < valueOf(n); i = i + 1) begin\n         sigmoidServers[i].request.put(vs[i]);\n      end\n      if (verbose) $display(\"consumeInput countInput=%d vs[0]=%h\", countInput+1, vs[0]);\n      countInput <= countInput + 1;\n   endrule\n\n   rule enqResult;\n      Vector#(n, Float) vs;\n      for (Integer i = 0; i < valueOf(n); i = i + 1) begin\n         let v <- sigmoidServers[i].response.get();\n\t vs[i] = v;\n      end\n      if (verbose) $display(\"sigmoid count=%d value=%h\", count+1, vs);\n      count <= count + 1;\n      sinkC.pipe.enq(vs);\n   endrule\n\n   method Action sigmoidDone;\n      let b <- sinkC.finish();\n   endmethod\n\n   method Action updateDone;\n      let b <- tabsrc.finish();\n      updatingSigmoidTable <= False;\n   endmethod\n\n   method Bit#(32) tableSize;\n      return sigmoidTables[0].tableSize;\n   endmethod\n\n   interface SigmoidRequest sigmoidRequest;\n      method Action sigmoid(Bit#(32) readPointer, Bit#(32) readOffset,\n   \t\t\t    Bit#(32) writePointer, Bit#(32) writeOffset, Bit#(32) numvalues);\n\t source.start(readPointer, 0, unpack(extend(numvalues))>>nshift);\n\t sinkC.start(writePointer, 0, unpack(extend(numvalues))>>nshift);\n\t if (verbose) $display(\"sigmoid.start numvalues=%d\", numvalues);\n      endmethod\n      method Action setLimits(Bit#(32) rscale, Bit#(32) llimit, Bit#(32) ulimit);\n\t for (Integer i = 0; i < valueOf(n); i = i + 1) begin\n\t    sigmoidTables[i].setSigmoidLimits(unpack(rscale), unpack(llimit), unpack(ulimit));\n\t end\n      endmethod\n      method Action updateTable(Bit#(32) readPointer, Bit#(32) readOffset, Bit#(32) numvalues);\n\t entryNumber <= 0;\n\t updatingSigmoidTable <= True;\n\t tabsrc.start(readPointer, extend(readOffset), (4*extend(numvalues))>>nshift);\n\t if (verbose) $display(\"sigmoid.updateSigmoidTable %d %d %d\", readPointer, readOffset, numvalues);\n      endmethod\n      method Action tableSize();\n\t noAction;\n      endmethod\n   endinterface\nendmodule\n"
  },
  {
    "path": "lib/rbm/bsv/Timer.bsv",
    "content": "// Copyright (c) 2014 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\ninterface TimerRequest;\n   method Action startTimer();\n   method Action stopTimer();\nendinterface\n\ninterface TimerIndication;\n   method Action elapsedCycles(Bit#(64) cycles, Bit#(64) idleCycles);\nendinterface\n"
  },
  {
    "path": "lib/rbm/cpp/mnist.h",
    "content": "/* Copyright (c) 2014 Quanta Research Cambridge, Inc\n *\n * Permission is hereby granted, free of charge, to any person obtaining a\n * copy of this software and associated documentation files (the \"Software\"),\n * to deal in the Software without restriction, including without limitation\n * the rights to use, copy, modify, merge, publish, distribute, sublicense,\n * and/or sell copies of the Software, and to permit persons to whom the\n * Software is furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n * DEALINGS IN THE SOFTWARE.\n */\n#ifndef _MNIST_H_\n#define _MNIST_H_\n\n#include <arpa/inet.h>\n#include <errno.h>\n#include <fcntl.h>\n#include <stdio.h>\n#include <string.h>\n#include <sys/mman.h>\n#include <sys/stat.h>\n#include <sys/types.h>\n#include <unistd.h>\n#include <opencv2/core/core.hpp>\n\nclass MnistImageFile {\npublic:\n  MnistImageFile(const char *name) : name(name), fd(0), mapping(0), len(0) {}\n  ~MnistImageFile() { \n    if (mapping)\n      munmap((void*)mapping, len);\n    if (fd)\n      close(fd);\n  }\n\n  void open() {\n    fd = ::open(name, O_RDONLY);\n    if (fd < 0) {\n      fprintf(stderr, \"Failed to open %s errno=%d:%s\\n\", name, errno, strerror(errno));\n    }\n    mapping = (const char *)mmap(0, 4096, PROT_READ, MAP_SHARED, fd, 0);\n    if (mapping == MAP_FAILED) {\n      fprintf(stderr, \"mmap failed on file %s errno=%d:%s\\n\", name, errno, strerror(errno));\n    }\n    int magic = *(int *)mapping;\n    int dtype = mapping[2];\n    int dims = mapping[3];\n    int *nosizes = (int *)(mapping + 4);\n    int size = 0;\n    switch (dtype) {\n    case 8:\n    case 9:\n      size = 1;\n      break;\n    case 0xb:\n      size = 2;\n      break;\n    case 0xc:\n      size = 4;\n      break;\n    case 0xe:\n      size = 8;\n      break;\n    default:\n      fprintf(stderr, \"Unknown data type %x\\n\", dtype);\n    }\n    for (int i = 0; i < dims; i++) {\n      sizes[i] = ntohl(nosizes[i]);\n      size = size * sizes[i];\n    }\n    dataOffset = 4+dims*4;\n    elementSize = size / sizes[0];\n\n    len = cv::alignSize(size + dataOffset, 4096);\n    fprintf(stderr, \"magic=%x dtype=%x dims=%d size=%d elementSize=%d len=%d\\n\", ntohl(magic), dtype, dims, size, elementSize, len);\n    munmap((void*)mapping, 4096);\n    mapping = (const char *)mmap(0, len, PROT_READ, MAP_SHARED, fd, 0);\n    if (mapping == MAP_FAILED) {\n      fprintf(stderr, \"mmap failed on file %s errno=%d:%s\\n\", name, errno, strerror(errno));\n    }\n\n  }\n\n  int numEntries() const {\n    return sizes[0];\n  }\n  int rows() const {\n    return sizes[1];\n  }\n  int cols() const {\n    return sizes[2];\n  }\n\n  cv::Mat mat(int i) const {\n    const char *data = mapping + dataOffset + elementSize*i;\n    int rows = sizes[1];\n    int cols = sizes[2];\n    //fprintf(stderr, \"image %d rows=%d cols=%d offset=%d\\n\", i, rows, cols, dataOffset + elementSize*i);\n    cv::Mat m(rows, cols, CV_8U);\n    for (int i = 0; i < rows; i++) {\n      for (int j = 0; j < cols; j++) {\n\tm.at<unsigned char>(i,j) = (unsigned char)data[i*cols + j];\n      }\n    }\n    return m;\n  }\n\nprivate:\n  const char *name;\n  int fd;\n  const char *mapping;\n  int sizes[3];\n  int len;\n  int dataOffset;\n  int elementSize;\n};\n\n#endif\n"
  },
  {
    "path": "lib/rbm/cpp/rbm.cpp",
    "content": "\n// Copyright (c) 2014 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\n#undef NDEBUG\n#include \"portalmat.h\"\n#include \"rbm.h\"\n#include \"mnist.h\"\n\nfloat sigmoid(float x)\n{\n  if (x < -8.0)\n    x = -8.0;\n  if (x > 8.0)\n    x = 8.0;\n  return 1 / (1 + expf(-x));\n}\n\nvoid configureSigmoidTable()\n{\n  sigmoiddevice->tableSize();\n  sem_wait(&mul_sem);\n\n  int num_entries = sigmoidindication->tableSize();\n  int addrsize = log((double)num_entries) / log(2.0);\n\n  float range = 16.0;\n  float lowest_angle = - range/2.0;\n  double fincr = (float)num_entries / range;\n  double fscale = num_entries / range;\n  fprintf(stderr, \"configureSigmoidTable: num_entries=%d addrsize=%d fscale=%f fincr=%f\\n\", num_entries, addrsize, fscale, fincr);\n\n  RbmMat sigmoidTable;\n  // each entry consists of [-angle, sigmoid(angle), derivative, 0]\n  sigmoidTable.create(1, 4*num_entries, CV_32F);\n\n  // v = (index-num_entries/2) / fscale\n  // index = v * fscale + num_entries/2\n\n  float fxscale = fscale;\n  float fxllimit = (float)lowest_angle;\n  float fxulimit = (float)-lowest_angle;\n  fprintf(stderr, \"configureSigmoidTable num_entries=%d rscale=%f %x llimit=%f %x rlimit=%f %x\\n\",\n\t  num_entries, fxscale, *(int*)&fxscale, fxllimit, *(int*)&fxllimit, fxulimit, *(int*)&fxulimit);\n  sigmoiddevice->setLimits(*(int*)&fxscale, *(int*)&fxllimit, *(int*)&fxulimit);\n\n  int incr = 1;\n  fprintf(stderr, \"filling sigmoid table pointer=%x\\n\", sigmoidTable.reference());\n  for (int ai = 0; ai < num_entries; ai += incr) {\n    float angle = (ai - num_entries / 2) / fscale;\n    //int index = (int)(angle*fscale);\n    float s = sigmoid(angle);\n    //fprintf(stderr, \"ai=%d angle=%f entry_angle=%f sigmoid=%f\\n\", ai, angle, angle * fscale + num_entries/2, s);\n    sigmoidTable.at<float>(0, 4*ai+0) = -angle;\n    sigmoidTable.at<float>(0, 4*ai+1) = s;\n    if (ai == num_entries-1) {\n      sigmoidTable.at<float>(0, 4*ai+2) = 0;\n    } else if (ai > 0) {\n      float angle_prev = (ai - 1 - num_entries/2) / fscale;\n      float s_prev = sigmoidTable.at<float>(0,4*(ai-1)+1);\n      float dangle = angle - angle_prev;\n      float ds = s - s_prev;\n      float slope = ds / dangle;\n      //fprintf(stderr, \"angle=%f angle_prev=%f s=%f s_prev=%f ds=%f dangle=%f slope=%f\\n\", angle, angle_prev, s, s_prev, ds, dangle, slope);\n      sigmoidTable.at<float>(0, 4*ai+2) = slope;\n    }\n    sigmoidTable.at<float>(0, 4*ai+3) = 0;\n  }\n  fprintf(stderr, \"updating sigmoid table pointer=%x\\n\", sigmoidTable.reference());\n  sigmoiddevice->updateTable(sigmoidTable.reference(), 0, num_entries);\n  sem_wait(&mul_sem);\n  fprintf(stderr, \"sigmoid table updated\\n\");\n}\n\n\nvoid RbmMat::sigmoid(RbmMat &a)\n{\n    create(a.rows, a.cols, CV_32F);\n    fprintf(stderr, \"RbmMat::sigmoid() %d %d\\n\", a.rows, a.cols);\n    reference();\n    cacheFlushInvalidate();\n    //fprintf(stderr, \"sigmoid: a.ref=%d a.rows=%d a.cols=%d\\n\", a.reference(), a.rows, a.cols);\n    //fprintf(stderr, \"sigmoiddevice->sigmoid\\n\");\n    sigmoiddevice->sigmoid(a.reference(), 0, reference(), 0, a.rows*a.cols);\n    sem_wait(&mul_sem);\n}\n\nvoid RbmMat::hiddenStates(RbmMat &a, RbmMat &rand)\n{\n    create(a.rows, a.cols, CV_32F);\n    fprintf(stderr, \"hiddenStates: a.ref=%d a.rows=%d a.cols=%d\\n\", a.reference(), a.rows, a.cols);\n    rand.reference();\n    reference();\n    cacheFlushInvalidate();\n    fprintf(stderr, \"rbmdevice->computeStates ptr=%d randPtr=%d\\n\", a.reference(), rand.reference());\n    rbmdevice->computeStates(a.reference(), 0, rand.reference(), 0, reference(), 0, a.rows*a.cols);\n    sem_wait(&mul_sem);\n}\n\n// weights += learningRate * (pos_associations - neg_associations) / num_examples;\nvoid RbmMat::updateWeights(RbmMat &posAssociations, RbmMat &negAssociations, float learningRateOverNumExamples)\n{\n    fprintf(stderr, \"rbmdevice->updateWeights pa.ref=%d na.ref=%d\\n\", posAssociations.reference(), negAssociations.reference());\n    cacheFlushInvalidate();\n    rbmdevice->updateWeights(posAssociations.reference(), negAssociations.reference(), reference(), rows*cols, *(int*)&learningRateOverNumExamples);\n    sem_wait(&mul_sem);\n}\n\nvoid RbmMat::sumOfErrorSquared(RbmMat &pred)\n{\n    if (rows != pred.rows || cols != pred.cols) {\n\tfprintf(stderr, \"Mismatched data and pred: data.rows=%d data.cols=%d  pred.rows=%d pred.cols=%d\\n\",\n\t\trows, cols, pred.rows, pred.cols);\n\texit(-1);\n    }\n    fprintf(stderr, \"sumOfErrorSquared called numElts=%d\\n\", rows*cols);\n    cacheFlushInvalidate();\n    rbmdevice->sumOfErrorSquared(reference(), pred.reference(), rows*cols);\n    sem_wait(&mul_sem);\n}\n\nvoid printDynamicRange(const char *label, cv::Mat m)\n{\n  int min_exp = 0;\n  int max_exp = 0;\n  float min_val = 0.0;\n  float max_val = 0.0;\n  dynamicRange(m, &min_exp, &max_exp, &min_val, &max_val);\n  printf(\"dynamic range: max_exp=%d min_exp=%d max_val=%f min_val=%f  %s\\n\", max_exp, min_exp, max_val, min_val, label);\n}\n\nfloat sumOfErrorSquared(cv::Mat &a, cv::Mat &b)\n{\n  cv::Mat diff = a - b;\n  float error = diff.dot(diff);\n  return error;\n}\n\nvoid RBM::train(int numVisible, int numHidden, const cv::Mat &trainingData)\n{\n  bool verify = false;\n#ifdef SIMULATION\n  int numEpochs = 10;\n#else\n  int numEpochs = 100;\n#endif\n  if (verify)\n    numEpochs = 1;\n  float sum_of_errors_squareds[numEpochs];\n  bool verbose = false;\n  bool dynamicRange = true;\n  //int numExamples = trainingData.rows;\n\n  if (verbose) dumpMat<float>(\"trainingData\", \"%5.6f\", trainingData);\n  if (dynamicRange) printDynamicRange(\"trainingData\", trainingData);\n\n  cv::Mat weights;\n  weights.create(numVisible+1, numHidden+1, CV_32F);\n  for (int i = 0; i < numVisible+1; i++) {\n    for (int j = 0; j < numHidden+1; j++) {\n      float w = 0.1 * drand48();\n      if (w < 0 || w > 1.0)\n\tprintf(\"w out of range %f\\n\", w);\n      weights.at<float>(i,j) = w;\n    }\n  }\n  if (dynamicRange) printDynamicRange(\"weights\", weights);\n\n  // insert bias units of 1 into first column of data\n  cv::Mat data;\n  data.create(trainingData.rows, trainingData.cols+1, CV_32F);\n  trainingData.copyTo(data.colRange(1, data.cols));\n  for (int i = 0; i < data.rows; i++)\n    data.at<float>(i, 0) = 1.0;\n\n  RbmMat pmData(data);\n  RbmMat pmDataT(pmData.t());\n  RbmMat pmWeights(weights);\n  RbmMat pmWeightsT;\n  RbmMat pm_pos_hidden_activations;\n  RbmMat pm_pos_hidden_probs;\n  RbmMat pm_rand_mat;\n  RbmMat pm_pos_hidden_states;\n  RbmMat pm_pos_hidden_probsT;\n  RbmMat pm_pos_associations;\n  RbmMat pm_neg_visible_activations;\n  RbmMat pm_neg_visible_probs;\n  RbmMat pm_neg_hidden_activations;\n  RbmMat pm_neg_hidden_probs;\n  RbmMat pm_neg_visible_probsT;\n  RbmMat pm_neg_hidden_probsT;\n  RbmMat pm_neg_associations;\n  RbmMat pm_pos_hidden_statesT;\n\n  if (verbose) dumpMat<float>(\"data\", \"%5.6f\", data);\n  if (verbose) dumpMat<float>(\"weights\", \"%5.6f\", weights);\n\n  portalTimerStart(0);\n  for (int epoch = 0; epoch < numEpochs; epoch++) {\n\n    timerdevice->startTimer();\n    cv::Mat pos_hidden_activations = data * pmWeights;\n    if (dynamicRange) printDynamicRange(\"pos_hidden_activations\", pos_hidden_activations);\n    // fixme transpose\n    pmWeightsT.transpose(pmWeights);\n    if (verbose) dumpMat<float>(\"pmWeightsT\", \"%5.1f\", pmWeightsT);\n\n    //RbmMat pm_pos_hidden_activations;\n    pm_pos_hidden_activations.multf(pmDataT, pmWeights);\n    if (verbose) dumpMat<float>(\"pm_pos_hidden_activations\", \"%5.1f\", pm_pos_hidden_activations);\n    if (verbose) dumpMat<float>(\"   pos_hidden_activations\", \"%5.1f\", pos_hidden_activations);\n\n    if (verify) assert(pm_pos_hidden_activations.compare(pos_hidden_activations, __FILE__, __LINE__));\n    // RbmMat pm_pos_hidden_probs;\n    pm_pos_hidden_probs.sigmoid(pm_pos_hidden_activations);\n    if (dynamicRange) printDynamicRange(\"pm_pos_hidden_probs\", pm_pos_hidden_probs);\n\n    cv::Mat pos_hidden_probs(pm_pos_hidden_activations);\n    for (int i = 0; i < pm_pos_hidden_activations.rows; i++) {\n      for (int j = 0; j < pm_pos_hidden_activations.cols; j++) {\n\tpos_hidden_probs.at<float>(i,j) = sigmoid(pm_pos_hidden_activations.at<float>(i,j));\n      }\n    }\n    if (verbose) dumpMat<float>(\"pm_pos_hidden_probs\", \"%5.1f\", pm_pos_hidden_probs);\n    if (verbose) dumpMat<float>(\"   pos_hidden_probs\", \"%5.1f\", pos_hidden_probs);\n    if (verify) assert(pm_pos_hidden_probs.compare(pos_hidden_probs, __FILE__, __LINE__));\n\n    // RbmMat pm_rand_mat;\n    pm_rand_mat.create(pm_pos_hidden_probs.rows, pm_pos_hidden_probs.cols, CV_32F);\n    for (int i = 0; i < pm_pos_hidden_probs.rows; i++) {\n      for (int j = 0; j < pm_pos_hidden_probs.cols; j++) {\n\tpm_rand_mat.at<float>(i,j) = (float)drand48();\n      }\n    }\n    if (verbose) dumpMat<float>(\"pm_rand_mat\", \"%5.1f\", pm_rand_mat);\n    if (dynamicRange) printDynamicRange(\"pm_rand_mat\", pm_rand_mat);\n    cv::Mat pos_hidden_states;\n    pos_hidden_states.create(pm_pos_hidden_probs.rows, pm_pos_hidden_probs.cols, CV_32F);\n    for (int i = 0; i < pm_pos_hidden_probs.rows; i++) {\n      for (int j = 0; j < pm_pos_hidden_probs.cols; j++) {\n\tfloat val = 0.0;\n\tif (pm_pos_hidden_probs.at<float>(i,j) > pm_rand_mat.at<float>(i,j))\n\t  val = 1.0;\n\tpos_hidden_states.at<float>(i,j) = val;\n      }\n    }\n    if (dynamicRange) printDynamicRange(\"pos_hidden_states\", pos_hidden_states);\n\n    // RbmMat pm_pos_hidden_states;\n    pm_pos_hidden_states.hiddenStates(pm_pos_hidden_probs, pm_rand_mat);\n\n    if (verbose) dumpMat<float>(\"pm_pos_hidden_states\", \"%5.1f\", pm_pos_hidden_states);\n    if (verbose) dumpMat<float>(\"   pos_hidden_states\", \"%5.1f\", pos_hidden_states);\n    if (verify) assert(pm_pos_hidden_states.compare(pos_hidden_states, __FILE__, __LINE__));\n    if (verbose) dumpMat<float>(\"pmDataT\", \"%5.1f\", pmDataT);\n\n    //RbmMat pmWeights(weights); // back to non-transposed\n    //pmWeights.copy(weights);\n    if (verbose) dumpMat<float>(\"pmWeights\", \"%5.1f\", pmWeights);\n\n    pm_pos_hidden_probsT.transpose(pm_pos_hidden_probs);\n    if (verbose) dumpMat<float>(\"pos_hidden_probsT\", \"%5.1f\", pm_pos_hidden_probsT);\n\n    cv::Mat pos_associations = pmDataT * pm_pos_hidden_probs;\n\n    //RbmMat pm_pos_associations;\n    pm_pos_associations.multf(pmData, pm_pos_hidden_probs);\n    if (verbose) dumpMat<float>(\"pos_associations\", \"%5.1f\", pm_pos_associations);\n    if (dynamicRange) printDynamicRange(\"pm_pos_associations\", pm_pos_associations);\n\n    // check results\n    if (verify) assert(pm_pos_associations.compare(pos_associations, __FILE__, __LINE__));\n\n    // RbmMat pm_neg_visible_activations;\n    pm_pos_hidden_statesT.transpose(pm_pos_hidden_states);\n    pm_neg_visible_activations.multf(pm_pos_hidden_statesT, pmWeightsT);\n    if (verbose) dumpMat<float>(\"neg_visible_activations\", \"%5.1f\", pm_neg_visible_activations);\n    if (dynamicRange) printDynamicRange(\"pm_neg_visible_activations\", pm_neg_visible_activations);\n\n    cv::Mat neg_visible_probs;\n    neg_visible_probs.create(pm_neg_visible_activations.rows, pm_neg_visible_activations.cols, CV_32F);\n    for (int i = 0; i < pm_neg_visible_activations.rows; i++) {\n      for (int j = 0; j < pm_neg_visible_activations.cols; j++) {\n\tneg_visible_probs.at<float>(i,j) = sigmoid(pm_neg_visible_activations.at<float>(i,j));\n      }\n    }\n\n    // RbmMat pm_neg_visible_probs;\n    pm_neg_visible_probs.sigmoid(pm_neg_visible_activations);\n    pm_neg_visible_probsT.transpose(pm_neg_visible_probs);\n    if (verbose) dumpMat<float>(\"neg_visible_probs\", \"%5.1f\", pm_neg_visible_probs);\n\n    // pm_neg_visible_probs[:0] = 1;\n    for (int i = 0; i < pm_neg_visible_probs.rows; i++) {\n      pm_neg_visible_probs.at<float>(i,0) = 1.0;\n      neg_visible_probs.at<float>(i,0) = 1.0;\n    }\n    if (dynamicRange) printDynamicRange(\"pm_neg_visible_probs\", pm_neg_visible_probs);\n    if (verify) assert(pm_neg_visible_probs.compare(neg_visible_probs, __FILE__, __LINE__));\n\n    // RbmMat pm_neg_hidden_activations;\n    pm_neg_hidden_activations.multf(pm_neg_visible_probsT, pmWeights);\n    if (verbose) dumpMat<float>(\"pm_neg_hidden_activations\", \"%5.1f\", pm_neg_hidden_activations);\n    if (dynamicRange) printDynamicRange(\"pm_neg_hidden_activations\", pm_neg_hidden_activations);\n\n    cv::Mat neg_hidden_activations = pm_neg_visible_probs * pmWeights;\n    if (verbose) dumpMat<float>(\"   neg_hidden_activations\", \"%5.1f\", neg_hidden_activations);\n    if (verify) assert(pm_neg_hidden_activations.compare(neg_hidden_activations, __FILE__, __LINE__, 0.05));\n\n    // RbmMat pm_neg_hidden_probs;\n    pm_neg_hidden_probs.sigmoid(pm_neg_hidden_activations);\n    if (verbose) dumpMat<float>(\"pm_neg_hidden_probs\", \"%5.1f\", pm_neg_hidden_probs);\n    if (dynamicRange) printDynamicRange(\"pm_neg_hidden_probs\", pm_neg_hidden_probs);\n\n    pm_neg_visible_probsT.transpose(pm_neg_visible_probs);\n    if (verbose) dumpMat<float>(\"pm_neg_visible_probsT\", \"%5.1f\", pm_neg_visible_probsT);\n    if (dynamicRange) printDynamicRange(\"pm_neg_visible_probs\", pm_neg_visible_probs);\n\n    pm_neg_hidden_probsT.transpose(pm_neg_hidden_probs);\n    //RbmMat pm_neg_associations;\n    pm_neg_associations.multf(pm_neg_visible_probs, pm_neg_hidden_probs);\n    if (verbose) dumpMat<float>(\"pm_neg_associations\", \"%5.1f\", pm_neg_associations);\n    cv::Mat neg_associations = pm_neg_visible_probsT * pm_neg_hidden_probs;\n    if (verbose) dumpMat<float>(\"   neg_associations\", \"%5.1f\", neg_associations);\n    if (dynamicRange) printDynamicRange(\"pm_neg_associations\", pm_neg_associations);\n\n    if (verbose) dumpMat<float>(\"pmWeights.before\", \"%5.1f\", pmWeights);\n    // weights += learningRate * (pos_associations - neg_associations) / num_examples;\n    float learningRate = 1.0;\n    float num_examples = data.rows;\n    pmWeights.updateWeights(pm_pos_associations, pm_neg_associations, learningRate / num_examples);\n    if (verbose) dumpMat<float>(\"pmWeights.after \", \"%5.1f\", pmWeights);\n    if (dynamicRange) printDynamicRange(\"weights\", weights);\n\nfprintf(stderr, \"========== %s:%d\\n\", __FILE__, __LINE__);\n    // error = np.sum((data - neg_visible_probs) ** 2)\n    pmData.sumOfErrorSquared(pm_neg_visible_probs);\n    float error = sumOfErrorSquared(data, pm_neg_visible_probs);\nfprintf(stderr, \"========== %s:%d\\n\", __FILE__, __LINE__);\n    fprintf(stderr, \"completed epoch %d sumOfErrorSquared=%f\\n\", epoch, error);\n    sum_of_errors_squareds[epoch] = rbmDeviceIndication->sum_of_errors_squared;\n    timerdevice->stopTimer();\n  }\n  //uint64_t total_cycles = portalTimerLap(0);\n  //uint64_t beats = hostMemServerIndication->getMemoryTraffic(ChannelType_Read);\n  //fprintf(stderr, \"total_cycles=%ld beats=%ld utilization=%f\\n\", (long)total_cycles, (long)beats, (float)beats / (float)total_cycles);\n  for(int i = 0; i < numEpochs; i++)\n    fprintf(stderr, \"(%d) %f\\n\", i, sum_of_errors_squareds[i]);\n}\n\nvoid RBM::run()\n{\n  cv::Mat trainingData = (cv::Mat_<float>(6,6) <<\n\t\t\t  1,1,1,0,0,0,\n\t\t\t  1,0,1,0,0,0,\n\t\t\t  1,1,1,0,0,0,\n\t\t\t  0,0,1,1,1,0,\n\t\t\t  0,0,1,1,0,0,\n\t\t\t  0,0,1,1,1,0);\n\n  char name_buff[256];\n  snprintf(name_buff, 256, \"../train-images-idx3-ubyte\");\n  fprintf(stderr, \"reading image data from %s\\n\", name_buff);\n  MnistImageFile imagefile(name_buff);\n  imagefile.open();\n  int numImages = imagefile.numEntries();\n  int numPixels = imagefile.rows()*imagefile.cols();\n  \n  numImages = 200;\n  int cols = 783; // one more column is added below to make the total 784.\n#ifdef SIMULATION\n  numImages = 32;\n  cols = 31; // one more column is added to make the total 32\n#endif\n  if (!cols || numPixels < cols)\n    cols = numPixels;\n  fprintf(stderr, \"numImages=%d numPixels=%d imagefile.rows=%d imagefile.cols=%d\\n\", numImages, numPixels, imagefile.rows(), imagefile.cols());\n  \n  //numVisible = imagefile.rows()*imagefile.cols();\n  int numVisible = cols;\n  int numHidden = numVisible / 2;\n  \n  trainingData.create(numImages, cols, CV_32F);\n  \n  for (int i = 0; i < numImages; i++) {\n    //fprintf(stderr, \"Reading mat %d\\n\", i);\n    cv::Mat m = imagefile.mat(i);\n    //dumpMat<unsigned char>(\"foo\", \"%02x\", m);\n    for (int j = 0; j < imagefile.rows(); j++) {\n      for (int k = 0; k < imagefile.cols(); k++) {\n\tint offset = j*imagefile.cols() + k;\n\tif (offset < cols) {\n\t  float f = (float)m.at<unsigned char>(k,j);\n\t  trainingData.at<float>(i, offset) = f;\n\t}\n      }\n    }\n  }\n\n  fprintf(stderr, \"RBM::run() invoking train\\n\");\n  train(numVisible, numHidden, trainingData);\n  fprintf(stderr, \"trainingData.rows=%d trainingData.cols=%d\\n\", trainingData.rows, trainingData.cols);\n}\n"
  },
  {
    "path": "lib/rbm/cpp/rbm.h",
    "content": "/* Copyright (c) 2014 Quanta Research Cambridge, Inc\n *\n * Permission is hereby granted, free of charge, to any person obtaining a\n * copy of this software and associated documentation files (the \"Software\"),\n * to deal in the Software without restriction, including without limitation\n * the rights to use, copy, modify, merge, publish, distribute, sublicense,\n * and/or sell copies of the Software, and to permit persons to whom the\n * Software is furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n * DEALINGS IN THE SOFTWARE.\n */\n#ifndef _RBM_H_\n#define _RBM_H_\n#include \"RbmRequest.h\"\n#include \"RbmIndication.h\"\n#include \"SigmoidRequest.h\"\n#include \"SigmoidIndication.h\"\n#include \"dmaManager.h\"\n\nclass SigmoidIndication;\nclass RbmIndication;\n\nextern RbmRequestProxy *rbmdevice;\nextern SigmoidRequestProxy *sigmoiddevice;\nextern SigmoidIndication *sigmoidindication;\nextern RbmIndication *rbmDeviceIndication;\n\nclass RbmIndication : public RbmIndicationWrapper\n{\npublic:\n RbmIndication(int id) : RbmIndicationWrapper(id) {\n  }\n  virtual ~RbmIndication() {}\n  virtual void bramMmfDone() {\n    //fprintf(stderr, \"bramMmfDone\\n\");\n    sem_post(&mul_sem);\n  }\n  virtual void toBramDone() {\n    //fprintf(stderr, \"toBramDone\\n\");\n    sem_post(&mul_sem);\n  }\n  virtual void fromBramDone() {\n    //fprintf(stderr, \"fromBramDone\\n\");\n    sem_post(&mul_sem);\n  }\n  virtual void statesDone() {\n    //fprintf(stderr, \"statesDone\\n\");\n    sem_post(&mul_sem);\n  }\n  virtual void updateWeightsDone() {\n    //fprintf(stderr, \"updateWeightsDone\\n\");\n    sem_post(&mul_sem);\n  }\n  virtual void sumOfErrorSquared(uint32_t x) {\n    sum_of_errors_squared = *(float *)&x;\n    fprintf(stderr, \"sumOfErrorSquared error=%f\\n\", sum_of_errors_squared);\n    sem_post(&mul_sem);\n  }\n  virtual void sumOfErrorSquaredDebug(uint32_t macCount) {\n    fprintf(stderr, \"sumOfErrorSquared debug macCount=%d\\n\", macCount);\n  }\n  virtual void dbg(uint32_t a, uint32_t b, uint32_t c, uint32_t d) {\n    fprintf(stderr, \"rbm dbg a=%x b=%x c=%x d=%x\\n\", a, b, c, d);\n  }\n  float sum_of_errors_squared;\n};\n\nclass SigmoidIndication : public SigmoidIndicationWrapper\n{\npublic:\n SigmoidIndication(int id) : SigmoidIndicationWrapper(id) {\n  }\n  virtual ~SigmoidIndication() {}\n  virtual void sigmoidDone() {\n    //fprintf(stderr, \"sigmoidDone\\n\");\n    sem_post(&mul_sem);\n  }\n  virtual void tableUpdated(uint32_t addr) {\n    sem_post(&mul_sem);\n  }\n  uint32_t tableSize() { return tableSize_; }\n  virtual void tableSize(uint32_t size) {\n    fprintf(stderr, \"sigmoidTableSize %d\\n\", size);\n    tableSize_ = size;\n    sem_post(&mul_sem);\n  }\n private:\n  uint32_t tableSize_;\n};\n\nvoid sigmoid(PortalMat &a);\n\nfloat sigmoid(float x);\nvoid configureSigmoidTable();\n\nclass RBM {\n public:\n  RBM(DmaManager *dma) : dma(dma) {}\n  void train(int numVisible, int numHidden, const cv::Mat &trainingData);\n  void run();\n private:\n  DmaManager *dma;\n};\n\nclass RbmMat : public PortalMat {\n public:\n  RbmMat() : PortalMat() {};\n  RbmMat(const RbmMat &m) : PortalMat(m) {};\n  RbmMat(const cv::Mat &m) : PortalMat(m) {};\n  void sigmoid(RbmMat &a);\n  void hiddenStates(RbmMat &a, RbmMat &rand);\n  // weights += learningRate * (pos_associations - neg_associations) / num_examples;\n  void updateWeights(RbmMat &posAssociations, RbmMat &negAssociations, float learningRateOverNumExamples);\n  void sumOfErrorSquared(RbmMat &pred);\n};\n\n#endif // _RBM_H_\n"
  },
  {
    "path": "lib/regexp/bsv/Regexp.bsv",
    "content": "// Copyright (c) 2013 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\nimport FIFO::*;\nimport FIFOF::*;\nimport SpecialFIFOs::*;\nimport Vector::*;\nimport BRAM::*;\nimport Gearbox::*;\nimport StmtFSM::*;\nimport ClientServer::*;\nimport GetPut::*;\nimport Connectable::*;\nimport ConnectalMemTypes::*;\nimport MemReadEngine::*;\nimport Pipe::*;\nimport Dma2BRAM::*;\nimport RegexpEngine::*;\n\n`include \"ConnectalProjectConfig.bsv\"\n\ninterface RegexpRequest;\n   method Action setup(Bit#(32) mapSGLId, Bit#(32) mapLen);\n   method Action search(Bit#(32) token, Bit#(32) haystackSGLId, Bit#(32) haystackLen);\n   method Action retire(Bit#(32) token);\nendinterface\n\ninterface RegexpIndication;\n   method Action setupComplete(Bit#(32) token);\n   method Action searchResult(Bit#(32) token, Int#(32) v);\nendinterface\n\ninterface Regexp#(numeric type busWidth);\n   interface RegexpRequest request;\n   interface Vector#(1, MemReadClient#(busWidth)) config_read_client;\n   interface Vector#(1, MemReadClient#(busWidth)) haystack_read_client;\nendinterface\n\ntypedef `DEGPAR DegPar;\n\ntypedef enum {Config_charMap, Config_stateMap, Config_stateTransitions} RegexpState deriving (Eq,Bits);\n\nmodule mkRegexp#(RegexpIndication indication)(Regexp#(64))\n   provisos( Log#(`MAX_NUM_STATES,5)\n\t    ,Log#(`MAX_NUM_CHARS,5)\n\t    ,Div#(64,8,nc)\n\t    ,Mul#(nc,8,64)\n\t    ,Add#(0,DegPar,p)\n\t    ,Log#(p,lp)\n\t    );\n\n   MemReadEngine#(64,64,1,p) config_re <- mkMemReadEngine;\n   MemReadEngine#(64,64,2,p) haystack_re <- mkMemReadEngine;\n   let read_servers = zip(config_re.readServers,haystack_re.readServers);\n   Vector#(p, RegexpEngine#(lp)) rees <- mapM(uncurry(mkRegexpEngine), zip(read_servers,genVector));\n   Reg#(RegexpState) state <- mkReg(Config_charMap);\n\n   let readyFIFO <- mkSizedFIFOF(valueOf(p));\n   Vector#(p, PipeOut#(LDR#(lp))) ldrPipes;   \n   \n   FIFOF#(Tuple2#(Bit#(lp), SSV#(lp))) setsearchFIFO <- mkFIFOF;\n   UnFunnelPipe#(1,p,SSV#(lp),1) setsearchPipeUnFunnel <- mkUnFunnelPipesPipelined(cons(toPipeOut(setsearchFIFO),nil));\n\n   for(Integer i = 0; i < valueOf(p); i=i+1) begin\n      ldrPipes[i] = rees[i].ldr;\n      mkConnection(setsearchPipeUnFunnel[i],rees[i].setsearch);\n   end\n   FunnelPipe#(1,p,LDR#(lp),1) ldr <- mkFunnelPipesPipelined(ldrPipes);\n   \n   rule ldrr;\n      let rv <- toGet(ldr[0]).get;\n      case (rv) matches\n   \t tagged Ready  .r : readyFIFO.enq(r);\n   \t tagged Done   .d : indication.searchResult(extend(d), -1);\n   \t tagged Loc    .l : indication.searchResult(extend(tpl_1(l)), tpl_2(l));\n   \t tagged Config .c : indication.setupComplete(extend(c));\n      endcase\n   endrule\n\n   let setupFIFO <- mkSizedFIFO(4);\n   rule setup_r;\n      match {.sglId, .len} <- toGet(setupFIFO).get;\n      $display(\"mkRegexp::setup(%d) %d %d %d\", readyFIFO.first,sglId, len, state);\n      case (state) matches\n\t Config_charMap:  \n\t begin\n\t    state <= Config_stateMap;\n\t    setsearchFIFO.enq(tuple2(readyFIFO.first,tagged CharMap tuple2(sglId,len)));\n\t end\n\t Config_stateMap: \n\t begin\n\t    state <= Config_stateTransitions;\n\t    setsearchFIFO.enq(tuple2(readyFIFO.first,tagged StateMap tuple2(sglId,len)));\n\t end\n\t Config_stateTransitions:  \n\t begin\n\t    readyFIFO.deq;\n\t    state <= Config_charMap;\n\t    setsearchFIFO.enq(tuple2(readyFIFO.first,tagged StateTransitions tuple2(sglId,len)));\n\t end\n      endcase      \n   endrule\n\n   interface config_read_client = cons(config_re.dmaClient, nil);\n   interface haystack_read_client = cons(haystack_re.dmaClient, nil);\n      \n   interface RegexpRequest request;\n      method Action setup(Bit#(32) sglId, Bit#(32) len);\t \n\t setupFIFO.enq(tuple2(sglId,len));\n      endmethod\n      method Action search(Bit#(32) token, Bit#(32) sglId, Bit#(32) len);\n\t $display(\"mkRegexp::search %d %d %d\", token, sglId, len);\n\t setsearchFIFO.enq(tuple2(truncate(token),tagged Search tuple2(sglId,len)));\n      endmethod\n      method Action retire(Bit#(32) token);\n\t Bit#(lp) tok = truncate(token);\n\t $display(\"mkRegexp::retire(%d)\", tok);\n\t setsearchFIFO.enq(tuple2(tok,tagged Retire tok));\n      endmethod\n   endinterface\n\nendmodule\n"
  },
  {
    "path": "lib/regexp/bsv/RegexpEngine.bsv",
    "content": "// Copyright (c) 2013 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\nimport FIFO::*;\nimport FIFOF::*;\nimport SpecialFIFOs::*;\nimport Vector::*;\nimport BRAM::*;\nimport Gearbox::*;\nimport StmtFSM::*;\nimport ClientServer::*;\nimport GetPut::*;\nimport Probe::*;\nimport ConnectalMemTypes::*;\nimport MemReadEngine::*;\nimport Pipe::*;\nimport Dma2BRAM::*;\n\n`include \"ConnectalProjectConfig.bsv\"\n\ntypedef union tagged {\n   Tuple2#(Bit#(t),Int#(32)) Loc;\n   Bit#(t) Done;\n   Bit#(t) Ready;\n   Bit#(t) Config;\n   } LDR#(numeric type t) deriving (Eq,Bits);\n\ntypedef union tagged{\n   Pair#(Bit#(32)) CharMap;\n   Pair#(Bit#(32)) StateMap;\n   Pair#(Bit#(32)) StateTransitions;\n   Pair#(Bit#(32)) Search;\n   Bit#(t) Retire;\n  } SSV#(numeric type t) deriving (Eq,Bits);\n   \ninterface RegexpEngine#(numeric type tw);\n   interface PipeIn#(SSV#(tw)) setsearch;\n   interface PipeOut#(LDR#(tw)) ldr;\nendinterface\n\ntypedef Bit#(8) Char;\ntypedef Bit#(64) DWord;\ntypedef Bit#(32) Word;\n\nmodule mkRegexpEngine#(Pair#(MemReadEngineServer#(64)) readers, Integer iid)(RegexpEngine#(tw))\n   provisos(Log#(`MAX_NUM_STATES,5),\n\t    Log#(`MAX_NUM_CHARS,5),\n\t    Div#(64,8,nc),\n\t    Mul#(nc,8,64)\n\t    );\n\n   let debug = False;\n   let verbose = True;\n   let timing = False;\n   let config_re = tpl_1(readers);\n   let haystack_re = tpl_2(readers);\n   FIFO#(Bool) conff <- mkSizedFIFO(1);\n\n   Reg#(Bool) readyr <- mkReg(True);\n   FIFOF#(SSV#(tw)) setsearchFIFO <- mkSizedFIFOF(4);\n   Probe#(Bool) ssfp <- mkProbe();\n   FIFOF#(LDR#(tw)) ldrFIFO <- mkFIFOF;\n   \n   BRAM1Port#(Bit#(8), Bit#(8)) charMap <- mkBRAM1Server(defaultValue);\n   BRAM1Port#(Bit#(5), Bit#(8)) stateMap <- mkBRAM1Server(defaultValue);\n   BRAM1Port#(Bit#(10),Bit#(8)) stateTransitions <- mkBRAM1Server(defaultValue);\n\n   BRAMWriter#(8,64) charMapWriter <- mkBRAMWriter(0, charMap.portA, config_re);\n   BRAMWriter#(5,64) stateMapWriter <- mkBRAMWriter(1, stateMap.portA, config_re);\n   BRAMWriter#(10,64) stateTransitionsWriter <- mkBRAMWriter(2, stateTransitions.portA, config_re);\n\t          \n   let clk <- exposeCurrentClock;\n   let rst <- exposeCurrentReset;\n   Gearbox#(nc,1,Char) haystack <- mkNto1Gearbox(clk,rst,clk,rst);\n\n   Reg#(Bit#(32)) cycleCnt <- mkReg(0);\n   Reg#(Bit#(32)) lastHD <- mkReg(0);\n   \n   FIFO#(Bit#(5)) fsmState <- mkBypassFIFO;\n   Reg#(Bit#(64))  charCnt <- mkReg(0);\n   Reg#(Bit#(64))   resCnt <- mkReg(0);\n   Reg#(Bool)     accepted <- mkReg(False);\n   FIFO#(void)    doneFifo <- mkFIFO;\n   \n   rule countCycles;\n      if (timing) $display(\"******************************************** %d\", cycleCnt);\n      cycleCnt <= cycleCnt+1;\n      //$dumpvars();\n   endrule\n\n   rule set_ssfp;\n      ssfp <= setsearchFIFO.notEmpty;\n   endrule\n   \n   rule haystackResp;\n      let rv <- toGet(haystack_re.data).get;\n      haystack.enq(unpack(rv.data));\n      if (rv.last)\n         doneFifo.enq(?);\n   endrule\n   \n   rule haystackFinish if (!haystack.notEmpty);\n      doneFifo.deq;\n      ldrFIFO.enq(tagged Done fromInteger(iid));\n      conff.deq;\n      fsmState.deq;\n      if (verbose) $display(\"haystackFinish\");\n   endrule\n   \n   rule finishCharMapWriter;\n      conff.deq;\n      let rv <- charMapWriter.finish;\n      if (verbose) $display(\"finishCharMapWriter\");\n   endrule\n   \n   rule finishStateMapWriter;\n      conff.deq;\n      let rv <- stateMapWriter.finish;\n      if (verbose) $display(\"finishStateMapWriter\");\n   endrule\n\n   rule finishStateTransitionsWriter;\n      conff.deq;\n      let rv <- stateTransitionsWriter.finish;\n      if (verbose) $display(\"finishStateTransitionsWriter\");\n      ldrFIFO.enq(tagged Config fromInteger(iid));\n   endrule\n   \n   rule lookup_state;\n      lastHD <= cycleCnt;\n      if (debug) $display(\"deq haystack(%d)\", cycleCnt-lastHD);\n      haystack.deq;\n      charCnt <= charCnt+1;\n      let fsm_addr <- toGet(fsmState).get;\n      charMap.portA.request.put(BRAMRequest{write:False, responseOnWrite:False, address:haystack.first[0], datain:?});\n      stateMap.portA.request.put(BRAMRequest{write:False, responseOnWrite:False, address:fsm_addr, datain:?});\n   endrule\n   \n   rule resolve_state;\n      let mapped_char <- charMap.portA.response.get;\n      let mapped_state <- stateMap.portA.response.get;\n      Bit#(10) ns_addr = {mapped_state[4:0],mapped_char[4:0]};\n      let accept = mapped_state[7]==1;\n      resCnt <= resCnt+1;\n      if (accept) begin\n\t if (debug) $display(\"accept %d\", resCnt);\n\t ldrFIFO.enq(tagged Loc tuple2(fromInteger(iid),unpack(truncate(resCnt))));\n\t accepted <= accept;\n\t fsmState.enq(0);\n      end\n      else begin\n\t stateTransitions.portA.request.put(BRAMRequest{write:False, responseOnWrite:False, address:ns_addr, datain:?});\n      end\n   endrule\n      \n   rule next_state;\n      let new_state <- stateTransitions.portA.response.get;\n      fsmState.enq(truncate(new_state));\n   endrule\n   \n   // the following case statement is much cleaner, but bsc doesn't compiler it\n   // correctly.  As a result, I broke it up into four rules, which seems to work (mdk)\n   //\n   // rule setsearch_r;\n   //    let ssv <- toGet(setsearchFIFO).get;\n   //    conff.enq(True);\n   //    case (ssv) matches\n   // \t tagged CharMap .p:\n   // \t begin\n   // \t    match {.pointer, .len}  = p;\n   // \t    if (verbose) $display(\"setupCharMap %d %h\", pointer, len);\n   // \t    charMapWriter.start(pointer, 0, minBound, maxBound);\n   // \t end\n   // \t tagged StateMap .p:\n   // \t begin\n   // \t    match {.pointer, .len}  = p;\n   // \t    if (verbose) $display(\"setupStateMap %d %h\", pointer, len);\n   // \t    stateMapWriter.start(pointer, 0, minBound, maxBound);\n   // \t end\n   // \t tagged StateTransitions .p:\n   // \t begin\n   // \t    match {.pointer, .len}  = p;\n   // \t    if (verbose) $display(\"setupStateTransitions %d %h\", pointer, len);\n   // \t    stateTransitionsWriter.start(pointer, 0, minBound, maxBound);\n   // \t end\n   // \t tagged Search .p:\n   // \t begin\n   // \t    match {.pointer, .len}  = p;\n   // \t    if (verbose) $display(\"setupSearch %d %d\", pointer, len);\n   // \t    haystack_re.request.put(MemengineCmd{sglId:pointer, base:0, len:len, burstLen:16*fromInteger(valueOf(nc))});\n   // \t    charCnt <= 0;\n   // \t    resCnt <= 0;\n   // \t    fsmState.enq(0);\n   // \t end\n   // \t tagged Retire .r:\n   // \t begin\n   // \t    readyr <= True;\n   // \t    if (verbose) $display(\"Retire %d\", r);\n   // \t end\n   //    endcase\n   // endrule\n\n   rule setsearch_r_0 if (setsearchFIFO.first matches tagged CharMap .p);\n      setsearchFIFO.deq;\n      conff.enq(True);\n      match {.pointer, .len}  = p;\n      if (verbose) $display(\"setupCharMap %d %h\", pointer, len);\n      charMapWriter.start(pointer, 0, minBound, maxBound);\n   endrule\n   rule setsearch_r_1 if (setsearchFIFO.first matches tagged StateMap .p);\n      setsearchFIFO.deq;\n      conff.enq(True);\n      match {.pointer, .len}  = p;\n      if (verbose) $display(\"setupStateMap %d %h\", pointer, len);\n      stateMapWriter.start(pointer, 0, minBound, maxBound);\n   endrule\n   rule setsearch_r_2 if (setsearchFIFO.first matches tagged StateTransitions .p);\n      setsearchFIFO.deq;\n      conff.enq(True);\n      match {.pointer, .len}  = p;\n      if (verbose) $display(\"setupStateTransitions %d %h\", pointer, len);\n      stateTransitionsWriter.start(pointer, 0, minBound, maxBound);\n   endrule\n   rule setsearch_r_3 if (setsearchFIFO.first matches tagged Search .p);\n      setsearchFIFO.deq;\n      conff.enq(True);\n      match {.pointer, .len}  = p;\n      if (verbose) $display(\"setupSearch %d %d\", pointer, len);\n      haystack_re.request.put(MemengineCmd{sglId:pointer, base:0, len:len, burstLen:16*fromInteger(valueOf(nc)), tag: 0});\n      charCnt <= 0;\n      resCnt <= 0;\n      fsmState.enq(0);\n   endrule\n   rule setsearch_r_4 if (setsearchFIFO.first matches tagged Retire .r);\n      setsearchFIFO.deq;\n      readyr <= True;\n      if (verbose) $display(\"Retire %d\", r);\n   endrule\n\n   rule ready_r if (readyr);\n      ldrFIFO.enq(tagged  Ready fromInteger(iid));\n      readyr <= False;\n   endrule\n\n   interface PipeIn setsearch = toPipeIn(setsearchFIFO);\n   interface PipeOut ldr = toPipeOut(ldrFIFO);\n\nendmodule\n"
  },
  {
    "path": "lib/regexp/cpp/regexp_utils.h",
    "content": "/* Copyright (c) 2013 Quanta Research Cambridge, Inc\n *\n * Permission is hereby granted, free of charge, to any person obtaining a\n * copy of this software and associated documentation files (the \"Software\"),\n * to deal in the Software without restriction, including without limitation\n * the rights to use, copy, modify, merge, publish, distribute, sublicense,\n * and/or sell copies of the Software, and to permit persons to whom the\n * Software is furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n * DEALINGS IN THE SOFTWARE.\n */\n#include <sys/mman.h>\n#include <iostream>\n#include <fstream>\n\nsem_t test_sem;\nint sw_match_cnt = 0;\nint hw_match_cnt = 0;\n\n#define num_tests (DEGPAR*2)\n#define max_num_tokens (DEGPAR)\nint token_map[max_num_tokens];\n\ntypedef struct P {\n  unsigned int ref;\n  int alloc;\n  int length;\n  char *mem;\n}P;\n\nP haystackP[num_tests];\n\nDmaManager *haystack_dma;\n//MMURequestProxy *haystack_mmu;\nRegexpRequestProxy *regexp;\n\nusing namespace std;\n\nclass RegexpIndication : public RegexpIndicationWrapper\n{\npublic:\n  RegexpIndication(unsigned int id) : RegexpIndicationWrapper(id),done_cnt(0){};\n  virtual void setupComplete(uint32_t t){\n    fprintf(stderr, \"setupComplete = %d\\n\", t);\n    sem_post(&test_sem);\n    token = t;\n  }\n  virtual void searchResult (uint32_t t, int v){\n    if (v == -1 ){\n      fprintf(stderr, \"searchComplete = (%d, %d)\\n\", t, v);\n#ifndef ALGO_NANDSIM\n      // in ALGO_NANDSIM we are just re-usng the same haystack which \n      // has been written to the nandsim backing store by nandsim_exe \n      munmap(haystackP[token_map[t]].mem, haystackP[token_map[t]].length);\n      close(haystackP[token_map[t]].alloc);\n      //haystack_mmu->idReturn(haystackP[token_map[t]].ref);\n#endif\n      regexp->retire(t);\n      if(++done_cnt == num_tests){\n\tfprintf(stderr, \"donzo\\n\");\n\tsem_post(&test_sem);\n      }\n    }else if (v >= 0){ \n      fprintf(stderr, \"searchResult = (%d, %d)\\n\", t, v);\n      hw_match_cnt++;\n    }\n  }\n  int token;\n  int done_cnt;\n};\n\nint readfile(const char *fname, P* pP)\n{\n  int rc = 0;\n  ifstream binFile(fname, ios::in|ios::binary|ios::ate);\n  if (!binFile.good()) {\n    fprintf(stderr, \"%s: error opening %s\\n\", __FUNCTION__, fname);\n  }\n  pP->length = binFile.tellg();\n  pP->alloc = portalAlloc(pP->length, 0);\n  pP->mem = (char *)portalMmap(pP->alloc, pP->length);\n  pP->ref = haystack_dma->reference(pP->alloc);\n  binFile.seekg (0, ios::beg);\n  if(!binFile.read(pP->mem, pP->length)){\n    fprintf(stderr, \"error reading %s\\n\", fname);\n    rc = -1;\n  }\n  binFile.close();\n  return rc;\n}\n\n\nint sw_ref(P *haystack, P *charMap, P *stateMap, P *stateTransitions)\n{\n  int matches = 0;\n  int state = 0;\n  for(int i = 0; i < haystack->length; i++){\n    unsigned int c = haystack->mem[i];\n    unsigned int mapped_c = charMap->mem[c];\n    unsigned int mapped_state = stateMap->mem[state];\n    if (mapped_state & (1<<7)){\n      matches++;\n      mapped_state = 0;\n    }\n    state = stateTransitions->mem[(mapped_state<<5) | mapped_c];\n  }\n  return matches;\n}\n\n"
  },
  {
    "path": "lib/strstr/bsv/MPEngine.bsv",
    "content": "// Copyright (c) 2013 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\n/*\n * Implementation of:\n *    MP algorithm on pages 7-11 from \"Pattern Matching Algorithms\" by\n *       Alberto Apostolico, Zvi Galil, 1997\n */\n\n`include \"ConnectalProjectConfig.bsv\"\nimport FIFO::*;\nimport FIFOF::*;\nimport SpecialFIFOs::*;\nimport Vector::*;\nimport BRAM::*;\nimport Gearbox::*;\nimport Connectable::*;\nimport ConfigReg::*;\nimport StmtFSM::*;\nimport Probe::*;\n\nimport ConnectalMemUtils::*;\nimport ConnectalMemTypes::*;\nimport Dma2BRAM::*;\nimport Pipe::*;\nimport OldEHR::*;\n\ninterface MPEngine#(numeric type haystackBusWidth, numeric type configBusWidth);\n   interface PipeIn#(Triplet#(Bit#(32))) setsearch;\n   interface PipeOut#(Int#(32)) locdone;\nendinterface\n\ninterface MPStreamEngine#(numeric type haystackBusWidth, numeric type configBusWidth);\n   interface PipeIn#(MemDataF#(configBusWidth)) needle;\n   interface PipeIn#(MemDataF#(configBusWidth)) mpNext;\n   interface PipeIn#(MemDataF#(haystackBusWidth)) haystack;\n   interface PipeOut#(Int#(32)) locdone;\n   method Action clear();\n   method Action start(Bit#(32) needleLen);\nendinterface\n\ntypedef Bit#(8) Char;\ntypedef Bit#(64) DWord;\ntypedef Bit#(32) Word;\n\ntypedef 1024 MaxNeedleLen;\ntypedef TLog#(MaxNeedleLen) NeedleIdxWidth;\ntypedef Bit#(NeedleIdxWidth) NeedleIdx;\n\ntypedef enum {Config_needle, Config_mpNext, Initialized, Search} Stage deriving (Eq, Bits);\n\n\n\nmodule mkMPEngine#(MemReadEngineServer#(haystackBusWidth) haystackReader,\n\t\t   MemReadEngineServer#(configBusWidth) configReader) (MPEngine#(haystackBusWidth,configBusWidth))\n\n   provisos(Add#(a__, 8, haystackBusWidth),\n\t    Div#(haystackBusWidth,8,haystackBusBytes),\n\t    Mul#(haystackBusBytes,8,haystackBusWidth),\n\t    Add#(1, b__, haystackBusBytes),\n\t    Add#(c__, 32, haystackBusWidth),\n\t    Add#(1, d__, TDiv#(haystackBusWidth, 32)),\n\t    Mul#(TDiv#(haystackBusWidth, 32), 32, haystackBusWidth),\n\t    Add#(e__, TLog#(haystackBusBytes), 32),\n\t    Add#(f__, TLog#(TDiv#(haystackBusWidth, 32)), 32)\n\t    ,Mul#(TDiv#(configBusWidth, 8), 8, configBusWidth)\n\t    ,Add#(1, g__, TDiv#(configBusWidth, 8))\n\t    ,Add#(h__, TLog#(TDiv#(configBusWidth, 8)), 32)\n\t    ,Add#(i__, TLog#(TDiv#(configBusWidth, 32)), 32)\n\t    ,Add#(1, j__, TDiv#(configBusWidth, 32))\n\t    ,Mul#(TDiv#(configBusWidth, 32), 32, configBusWidth)\n\t    );\n   \n\n\n   \n   FIFOF#(Int#(32)) locf <- mkFIFOF;\n   FIFO#(Bool) conff <- mkSizedFIFO(1);\n   \n   let verbose = True;\n   let debug = False;\n\n   Clock clk <- exposeCurrentClock;\n   Reset rst <- exposeCurrentReset;\n   BRAM2Port#(NeedleIdx, Char) needle  <- mkBRAM2Server(defaultValue);\n   BRAM2Port#(NeedleIdx, Bit#(32)) mpNext <- mkBRAM2Server(defaultValue);\n   Gearbox#(haystackBusBytes,1,Char) haystack <- mkNto1Gearbox(clk,rst,clk,rst);\n\n   Reg#(Bit#(32)) cycleCnt <- mkReg(0);\n   Reg#(Bit#(32)) lastHD <- mkReg(0);\n   \n   Reg#(Stage)    stage <- mkReg(Config_needle);\n   Reg#(Bit#(32)) needleLenReg <- mkReg(0);\n   Reg#(Bit#(32)) haystackLenReg <- mkReg(0);\n   Reg#(Bit#(32)) haystackBase <- mkReg(0);\n   Reg#(Bit#(32)) jReg <- mkReg(0); // offset in haystack\n   Reg#(Bit#(32)) iReg <- mkReg(0); // offset in needle\n   Reg#(Bit#(2))  epochReg <- mkReg(0);\n\n   BRAMWriter#(NeedleIdxWidth,configBusWidth) n2b <- mkBRAMWriter(0, needle.portB, configReader);\n   BRAMWriter#(NeedleIdxWidth,configBusWidth) mp2b <- mkBRAMWriter(1, mpNext.portB, configReader);\n\n   FIFOF#(Tuple2#(Bit#(2),Bit#(32))) efifo <- mkSizedFIFOF(2);\n   FIFOF#(Triplet#(Bit#(32))) ssfifo <- mkFIFOF;\n   FIFO#(void) doneFifo <- mkFIFO;\n   \n   rule countCycles;\n      if (debug) $display(\"******************************************** %d\", cycleCnt);\n      cycleCnt <= cycleCnt+1;\n   endrule\n   \n   rule haystackResp;\n      if (debug) $display(\"mkMPEngine::haystackResp\");\n      let rv <- toGet(haystackReader.data).get;\n      haystack.enq(unpack(rv.data));\n      if (rv.last)\n         conff.deq;\n   endrule\n   \n   rule haystackDrain(stage != Search);\n      if (debug) $display(\"mkMPEngine::haystackDrain\");\n      haystack.deq;\n   endrule\n   \n   rule bramDrain(stage != Search);\n      if (debug) $display(\"mkMPEngine::mpNextDrain\");\n      let x <- mpNext.portA.response.get;\n      let y <- needle.portA.response.get;\n      efifo.deq;\n   endrule\n  \n   \n`define OPTIMIZE_MISMATCH\n`ifdef OPTIMIZE_MISMATCH\n   rule matchNeedleReq(stage == Search);\n      if (debug) $display(\"mkMPEngine::matchNeedleReq %d %d\", epochReg, iReg);\n      needle.portA.request.put(BRAMRequest{write:False, address: truncate(iReg-1), datain:?, responseOnWrite:?});\n      mpNext.portA.request.put(BRAMRequest{write:False, address: truncate(iReg), datain:?, responseOnWrite:?});\n      efifo.enq(tuple2(epochReg,iReg));\n      iReg <= 1;\n   endrule\n         \n   rule matchNeedleResp(stage == Search);\n      let nv <- needle.portA.response.get;\n      let mp <- mpNext.portA.response.get;\n      let epoch = tpl_1(efifo.first);\n      efifo.deq;\n      if (debug) $display(\"mkMPEngine::matchNeedleResp %d %d\", epochReg, epoch);\n      if (epoch == epochReg) begin\n\t Bool deq_haystack = False;\n\t let n = haystackLenReg;\n\t let m = needleLenReg;\n\t let hv = haystack.first;\n\t let i = tpl_2(efifo.first);\n\t let j = jReg;\n\t if (debug) $display(\"mkMPEngine::feck %d %d %d %d %x %x\", n, m, i, j, hv[0], nv);\n\t if (j > n) begin\n\t    // jReg points to the end of the haystack; we are done\n\t    stage <= Config_needle;\n\t    if (debug) $display(\"mkMPEngine::end of search %d\", j);\n\t    locf.enq(-1);\n\t end\n\t else if (i==m+1) begin\n\t    // iReg points to the end of the needle; we have a match\n\t    if (debug) $display(\"mkMPEngine::string match %d\", j);\n\t    locf.enq(unpack(haystackBase+j-i));\n\t end\n\t else if (nv != hv[0]) begin\n\t    // mismatch betwen head of haystack and head of needle; rewind iReg\n\t    if (debug) $display(\"mkMPEngine::char mismatch %d %d MP_Next[i]=%d\", i, j, mp);\n\t    if (mp == 0) begin\n\t       iReg <= 1;\n\t       jReg <= j+1;\n\t       deq_haystack = True;\n\t    end\n\t    else begin\n\t       epochReg <= epochReg + 1;\n\t       iReg <= mp;\n\t    end\n\t end\n\t else begin\n\t    // match between head of needle and head of haystack; increment haystack\n\t    if (debug) $display(\"mkMPEngine::char match(%d) %d %d\", (nv == hv[0]), i, j);\n\t    deq_haystack = True;\n\t    jReg <= j+1;\n\t    epochReg <= epochReg + 1;\n\t    iReg <= i+1;\n\t end\n\t if (deq_haystack) begin\n\t    haystack.deq;\n\t    lastHD <= cycleCnt;\n\t    if (debug) $display(\"mkMPEngine:: deq haystack(%d)\", cycleCnt-lastHD);\n\t end\n      end\n      else begin\n\t if (debug) $display(\"mkMPEngine::discard\");\n\t noAction;\n      end\n   endrule\n`else\n   rule matchNeedleReq(stage == Search);\n      if (debug) $display(\"mkMPEngine::matchNeedleReq %d %d\", epochReg, iReg);\n      needle.portA.request.put(BRAMRequest{write:False, address: truncate(iReg-1), datain:?, responseOnWrite:?});\n      mpNext.portA.request.put(BRAMRequest{write:False, address: truncate(iReg), datain:?, responseOnWrite:?});\n      efifo.enq(tuple2(epochReg,iReg));\n      iReg <= iReg+1;\n   endrule\n         \n   rule matchNeedleResp(stage == Search);\n      let nv <- needle.portA.response.get;\n      let mp <- mpNext.portA.response.get;\n      let epoch = tpl_1(efifo.first);\n      efifo.deq;\n      if (debug) $display(\"mkMPEngine::matchNeedleResp %d %d\", epochReg, epoch);\n      if (epoch == epochReg) begin\n\t Bool deq_haystack = False;\n\t let n = haystackLenReg;\n\t let m = needleLenReg;\n\t let hv = haystack.first;\n\t let i = tpl_2(efifo.first);\n\t let j = jReg;\n\t if (debug) $display(\"mkMPEngine::feck %d %d %d %d %x %x\", n, m, i, j, hv[0], nv);\n\t if (j > n) begin\n\t    // jReg points to the end of the haystack; we are done\n\t    stage <= Config_needle;\n\t    if (debug) $display(\"mkMPEngine::end of search %d\", j);\n\t end\n\t else if (i==m+1) begin\n\t    // iReg points to the end of the needle; we have a match\n\t    if (debug) $display(\"mkMPEngine::string match %d\", j);\n\t    locf.enq(unpack(haystackBase+j-i));\n\t    epochReg <= epochReg + 1;\n\t    iReg <= 1;\n\t end\n\t else if (nv != hv[0]) begin\n\t    // mismatch betwen head of haystack and head of needle; rewind iReg\n\t    if (debug) $display(\"mkMPEngine::char mismatch %d %d MP_Next[i]=%d\", i, j, mp);\n\t    epochReg <= epochReg + 1;\n\t    if (mp == 0) begin\n\t       iReg <= 1;\n\t       jReg <= j+1;\n\t       deq_haystack = True;\n\t    end\n\t    else begin\n\t       iReg <= mp;\n\t    end\n\t end\n\t else begin\n\t    // match between head of needle and head of haystack; increment haystack\n\t    if (debug) $display(\"mkMPEngine::char match(%d) %d %d\", (nv == hv[0]), i, j);\n\t    deq_haystack = True;\n\t    jReg <= j+1;\n\t end\n\t if (deq_haystack) begin\n\t    haystack.deq;\n\t    lastHD <= cycleCnt;\n\t    if (debug) $display(\"mkMPEngine:: deq haystack(%d)\", cycleCnt-lastHD);\n\t end\n      end\n      else begin\n\t if (debug) $display(\"mkMPEngine::discard\");\n\t noAction;\n      end\n   endrule\n`endif \n  \n   rule finish_setup_n2b;\n      if (verbose) $display(\"mkMPEngine::finish_setup_n2b\");\n      let x <- n2b.finish;\n      conff.deq;\n      stage <= Config_mpNext;\n   endrule\n\n   rule finish_setup_mp2b;\n      if (verbose) $display(\"mkMPEngine::finish_setup_mp2b\");\n      let y <- mp2b.finish;\n      conff.deq;\n      stage <= Initialized;\n   endrule\n      \n   rule setup_needle (stage == Config_needle);\n      conff.enq(True);\n      match {.needle_sglId, .mpNext_sglId, .needle_len} = ssfifo.first;\n      needleLenReg <= extend(needle_len);\n      if (verbose) $display(\"mkMPEngine::setup_needle %d %d\", needle_sglId, needle_len);\n      n2b.start(needle_sglId, 0, 0, pack(truncate(needle_len)));\n   endrule\n   \n   rule setup_mpNext (stage == Config_mpNext);\n      conff.enq(True);\n      match {.needle_sglId, .mpNext_sglId, .needle_len} = ssfifo.first;\n      needleLenReg <= extend(needle_len);\n      if (verbose) $display(\"mkMPEngine::setup_mpNext %d %d\", mpNext_sglId, needle_len);\n      mp2b.start(mpNext_sglId, 0, 0, pack(truncate(needle_len)));\n      ssfifo.deq;\n   endrule\n\n   rule search (stage == Initialized && !efifo.notEmpty && !haystack.notEmpty);\n      stage <= Search;\n      conff.enq(True);\n      match {.haystack_sglId, .haystack_len, .haystack_base} <- toGet(ssfifo).get;\n      haystackLenReg <= extend(haystack_len);\n      haystackBase <= extend(haystack_base);\n      iReg <= 1;\n      jReg <= 1;\n      epochReg <= 0;\n      Bit#(32) haystack_len_ds = haystack_len+fromInteger(valueOf(haystackBusBytes)-1);\n      Bit#(TLog#(haystackBusBytes)) zeros = 0;\n      Bit#(32) haystack_len_bytes = {zeros,haystack_len_ds[31:valueOf(TLog#(haystackBusBytes))]} * fromInteger(valueOf(haystackBusBytes));\n      $display(\"haystack read offset=%d burstLen=%d\", haystack_base, fromInteger(8*valueOf(haystackBusBytes)));\n      haystackReader.request.put(MemengineCmd{sglId:haystack_sglId, base:extend(haystack_base), len:haystack_len_bytes, burstLen:fromInteger(8*valueOf(haystackBusBytes)), tag: 0});\n      if (verbose) $display(\"mkMPEngine::search %d %d %d\",  haystack_sglId, haystack_base, haystack_len_bytes);\n   endrule\n   \n   interface PipeIn setsearch = toPipeIn(ssfifo);   \n   interface PipeOut locdone = toPipeOut(locf);\n\nendmodule\n\nmodule mkMPStreamEngine(MPStreamEngine#(haystackBusWidth,configBusWidth))\n\n   provisos(Add#(a__, 8, haystackBusWidth),\n\t    Div#(haystackBusWidth,8,haystackBusBytes),\n\t    Mul#(haystackBusBytes,8,haystackBusWidth),\n\t    Add#(1, b__, haystackBusBytes),\n\t    Add#(c__, 32, haystackBusWidth),\n\t    Add#(1, d__, TDiv#(haystackBusWidth, 32)),\n\t    Mul#(TDiv#(haystackBusWidth, 32), 32, haystackBusWidth),\n\t    Add#(e__, TLog#(haystackBusBytes), 32),\n\t    Add#(f__, TLog#(TDiv#(haystackBusWidth, 32)), 32)\n\t    ,Mul#(TDiv#(configBusWidth, 8), 8, configBusWidth)\n\t    ,Add#(1, g__, TDiv#(configBusWidth, 8))\n\t    ,Add#(h__, TLog#(TDiv#(configBusWidth, 8)), 32)\n\t    ,Add#(i__, TLog#(TDiv#(configBusWidth, 32)), 32)\n\t    ,Add#(1, j__, TDiv#(configBusWidth, 32))\n\t    ,Mul#(TDiv#(configBusWidth, 32), 32, configBusWidth)\n\t    );\n   \n   FIFOF#(Int#(32)) locf <- mkFIFOF;\n   \n   let verbose = True;\n   let debug = True;\n\n   Clock clk <- exposeCurrentClock;\n   Reset rst <- exposeCurrentReset;\n   BRAM2Port#(NeedleIdx, Char) needleBram  <- mkBRAM2Server(defaultValue);\n   BRAM2Port#(NeedleIdx, Bit#(32)) mpNextBram <- mkBRAM2Server(defaultValue);\n   FIFOF#(MemDataF#(haystackBusWidth)) haystackFifo <- mkFIFOF();\n   Gearbox#(haystackBusBytes,1,Char) haystackGb <- mkNto1Gearbox(clk,rst,clk,rst);\n\n   Reg#(Bit#(32)) cycleCnt <- mkReg(0);\n   Reg#(Bit#(32)) lastHD <- mkReg(0);\n   \n   Reg#(Stage)    stage <- mkReg(Initialized);\n   Reg#(Bit#(32)) needleLenReg <- mkReg(0);\n   Reg#(Bit#(32)) jReg <- mkReg(1); // offset in haystack\n   Reg#(Bit#(32)) iReg <- mkReg(1); // offset in needle\n\n   BRAMPipeIn#(NeedleIdxWidth,configBusWidth) n2b <- mkBRAMPipeIn(0, needleBram.portB);\n   BRAMPipeIn#(NeedleIdxWidth,configBusWidth) mp2b <- mkBRAMPipeIn(1, mpNextBram.portB);\n\n   FIFOF#(Tuple2#(Bit#(2),Bit#(32))) efifo <- mkSizedFIFOF(2);\n   FIFO#(void) doneFifo <- mkFIFO;\n   \n   rule countCycles;\n      //if (debug) $display(\"******************************************** %d\", cycleCnt);\n      cycleCnt <= cycleCnt+1;\n   endrule\n   \n   rule haystackResp;\n      let rv <- toGet(haystackFifo).get;\n      if (debug) $display(\"mkMPEngine::haystackResp rv=%h\", rv.data);\n      haystackGb.enq(unpack(rv.data));\n   endrule\n   \n   let x_i <- mkReg(0);\n   let t_j <- mkReg(0);\n   let m = needleLenReg;\n   let i = iReg;\n   let iReg_minus_1 <- mkReg(0);\n   let matchFsm <- mkAutoFSM(seq\n      while (stage != Search) seq\n\t iReg <= 1;\n      endseq\n      action\n\t iReg <= 1;\n\t jReg <= 1;\n\t let t = haystackGb.first[0]; haystackGb.deq();\n\t t_j <= t;\n         iReg_minus_1 <= iReg-1;\n      endaction\n      action\n\t needleBram.portA.request.put(BRAMRequest{write:False, address: truncate(iReg_minus_1), datain:?, responseOnWrite:?});\n      endaction\n      action\n\t let xNext <- needleBram.portA.response.get();\n\t x_i <= xNext;\n      endaction\n      while (stage == Search) seq\n\t $display(\"initial i=%d j=%d x_i=%h t_j=%h\", iReg, jReg, x_i, t_j);\n\t while ((i == m + 1) || (i > 0 && x_i != t_j)) seq\n\t    action\n\t       mpNextBram.portA.request.put(BRAMRequest{write:False, address: truncate(iReg), datain:?, responseOnWrite:?});\n      \t    endaction\n\t    action\n\t       Bit#(32) mpNext <- mpNextBram.portA.response.get();\n\t       let iNext = mpNext[15:0];\n\t       let xNext = mpNext[31:16];\n\t       iReg <= extend(iNext);\n\t       x_i <= truncate(xNext);\n\t       $display(\"i=%d iNext=%d m+1=%d x_i=%h t_j=%h mpNext=%h\", i, iNext, m+1, xNext, t_j, mpNext);\n\t    endaction\n\t endseq\n\t action\n\t    iReg <= iReg + 1;\n\t    jReg <= jReg + 1;\n\t    needleBram.portA.request.put(BRAMRequest{write:False, address: truncate(iReg+1-1), datain:?, responseOnWrite:?});\n\t    let t = haystackGb.first[0]; haystackGb.deq();\n\t    t_j <= t;\n      endaction\n      action\n\t    if (t_j == 0) begin\n\t       $display(\"iReg=%d jReg=%d t==0 locf.enq(-1)\", iReg-1, jReg-1, t_j);\n\t       locf.enq(-1); // this seems to be needed for the strstr example to terminate\n\t    end\n\t endaction\n\t action\n\t    let xNext <- needleBram.portA.response.get();\n\t    x_i <= xNext;\n\t    $display(\"step    i=%d j=%d x_i=%h t_j=%h\", iReg, jReg, xNext, t_j);\n\t    if (iReg == m + 1) begin\n\t       $display(\"match at j=%d\", jReg - iReg);\n\t       locf.enq(unpack(jReg - iReg));\n\t    end\n\t endaction\n      endseq // stage == Search\n      endseq);\n  \n   interface PipeIn needle = n2b.pipe;\n   interface PipeIn mpNext = mp2b.pipe;\n   interface PipeIn haystack = toPipeIn(haystackFifo);\n   interface PipeOut locdone = toPipeOut(locf);\n\n   method Action clear();\n      stage <= Initialized;\n   endmethod\n   method Action start(Bit#(32) needleLen);\n      stage <= Search;\n      jReg <= 1;\n      iReg <= 1;\n      needleLenReg <= needleLen;\n   endmethod\n\nendmodule\n"
  },
  {
    "path": "lib/strstr/bsv/Strstr.bsv",
    "content": "// Copyright (c) 2013 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\nimport FIFO::*;\nimport FIFOF::*;\nimport SpecialFIFOs::*;\nimport Vector::*;\nimport BuildVector::*;\nimport BRAM::*;\nimport Gearbox::*;\nimport Connectable::*;\nimport StmtFSM::*;\nimport ConnectalMemTypes::*;\nimport MPEngine::*;\nimport MemReadEngine::*;\nimport Pipe::*;\n\ninterface StrstrRequest;\n   method Action setup(Bit#(32) needleSGLId, Bit#(32) mpNextSGLId, Bit#(32) needle_len);\n   method Action search(Bit#(32) haystackSGLId, Bit#(32) haystack_len);\nendinterface\n\ninterface StrstrIndication;\n   method Action searchResult(Int#(32) v);\nendinterface\n\ninterface Strstr#(numeric type haystackBusWidth, numeric type configBusWidth);\n   interface StrstrRequest request;\n   interface Vector#(1, MemReadClient#(haystackBusWidth)) haystack_read_client;\n   interface Vector#(1, MemReadClient#(configBusWidth)) config_read_client;\nendinterface\n\n// I can't belive we still have to do this shit\nfunction Bool my_or(Bool a, Bool b) = a || b;\n   \nmodule mkStrstr#(StrstrIndication indication)(Strstr#(haystackBusWidth, configBusWidth))\n   provisos (\n   Mul#(TDiv#(configBusWidth, 8), 8, configBusWidth)\n   ,Mul#(TDiv#(haystackBusWidth, 8), 8, haystackBusWidth)\n   ,Add#(1, a__, TDiv#(haystackBusWidth, 8))\n   ,Add#(b__, TLog#(TDiv#(haystackBusWidth, 8)), 32)\n   ,Mul#(TDiv#(configBusWidth, 32), 32, configBusWidth)\n   ,Add#(1, c__, TDiv#(configBusWidth, 32))\n   ,Add#(d__, TLog#(TDiv#(configBusWidth, 32)), 32)\n   ,Add#(e__, TLog#(TDiv#(configBusWidth, 8)), 32)\n   ,Add#(1, f__, TDiv#(configBusWidth, 8))\n   ,Add#(g__, TLog#(TDiv#(haystackBusWidth, 32)), 32)\n   ,Mul#(TDiv#(haystackBusWidth, 32), 32, haystackBusWidth)\n   ,Add#(1, h__, TDiv#(haystackBusWidth, 32))\n   ,Add#(i__, 32, haystackBusWidth)\n   ,Add#(j__, 8, haystackBusWidth)\n\t    );\n   \n   let verbose = True;\n\n   Reg#(Bit#(32)) needleLen <- mkReg(0);\n   MemReadEngine#(haystackBusWidth,haystackBusWidth,1,1) haystack_re <- mkMemReadEngineBuff(1024);\n   MemReadEngine#(configBusWidth,configBusWidth,1,2) config_re <- mkMemReadEngineBuff(1024);\n   \n   Reg#(Bit#(32)) needleSGLId <- mkReg(0);\n   Reg#(Bit#(32)) mpNextSGLId <- mkReg(0);\n   Reg#(Bit#(32)) haystackSGLId <- mkReg(0);\n   Reg#(Bit#(32)) haystackLen <- mkReg(0);\n   Reg#(Bit#(32)) startCnt <- mkReg(0);\n   Reg#(Bit#(32)) startBase <- mkReg(0);\n   Reg#(Bit#(32)) setupCnt <- mkReg(0);\n   Reg#(Bit#(32)) doneCnt <- mkReg(0);\n\n   MPStreamEngine#(haystackBusWidth,configBusWidth) engine <- mkMPStreamEngine;\n   mkConnection(config_re.readServers[0].data, engine.needle);\n   mkConnection(config_re.readServers[1].data, engine.mpNext);\n   mkConnection(haystack_re.readServers[0].data, engine.haystack);\n\n   rule resr;\n      let rv <- toGet(engine.locdone).get;\n      // send results back to SW\n      indication.searchResult(rv);\n      if (verbose) $display(\"strstr search result %d\", rv);\n   endrule\n      \n   interface StrstrRequest request;\n      method Action setup(Bit#(32) needle_sglId, Bit#(32) mpNext_sglId, Bit#(32) needle_len);\n\t if (verbose) $display(\"mkStrstr::setup %d %d %d\", needle_sglId, mpNext_sglId, needle_len);\n\t needleLen <= needle_len;\n\t needleSGLId <= needle_sglId;\n\t mpNextSGLId <= mpNext_sglId;\n\t let burstLen = fromInteger(valueOf(configBusWidth)/8);\n\t let mask = burstLen - 1;\n\t needle_len = (needle_len + mask) & ~mask;\n\t $display(\"needle_len %d\", needle_len);\n\t config_re.readServers[0].request.put(MemengineCmd {sglId: needle_sglId, base: 0, burstLen: burstLen, len: needle_len, tag: 0});\n\t config_re.readServers[1].request.put(MemengineCmd {sglId: mpNext_sglId, base: 0, burstLen: burstLen, len: needle_len*4, tag: 0});\n\n\t engine.clear();\n      endmethod\n   \n      method Action search(Bit#(32) haystack_sglId, Bit#(32) haystack_len);\n\t if (verbose) $display(\"mkStrstr::search %d %d\", haystack_sglId, haystack_len);\n\t haystackLen <= haystack_len;\n\t haystackSGLId <= haystack_sglId;\n\t let burstLen = fromInteger(valueOf(haystackBusWidth)/8);\n\t let mask = burstLen - 1;\n\t haystack_len = (haystack_len + mask) & ~mask;\n\t haystack_re.readServers[0].request.put(MemengineCmd {sglId: haystack_sglId, base: 0, burstLen: burstLen, len: haystack_len, tag: 0});\n\n\t engine.start(needleLen);\n      endmethod\n   endinterface\n   interface config_read_client = vec(config_re.dmaClient);\n   interface haystack_read_client = vec(haystack_re.dmaClient);\nendmodule\n"
  },
  {
    "path": "lib/strstr/cpp/mp.h",
    "content": "/* Copyright (c) 2013 Quanta Research Cambridge, Inc\n *\n * Permission is hereby granted, free of charge, to any person obtaining a\n * copy of this software and associated documentation files (the \"Software\"),\n * to deal in the Software without restriction, including without limitation\n * the rights to use, copy, modify, merge, publish, distribute, sublicense,\n * and/or sell copies of the Software, and to permit persons to whom the\n * Software is furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n * DEALINGS IN THE SOFTWARE.\n */\n\n/*\n * Implementation of:\n *    MP algorithm on pages 7-11 from \"Pattern Matching Algorithms\" by\n *       Alberto Apostolico, Zvi Galil, 1997\n *\n *    pattern x of length m\n *    text    t of length n\n *\n *    procedure MP(x, t: string; m, n: integer);\n *    begin\n *        i := 1; j := 1;\n *        while j <= n do begin\n *            while (i = m + 1) or (i > 0 and x[i] != t[j]) do i := MP_next[i];\n *            i := i + 1; j := j + 1;\n *            if i = m + 1 then writeln('x occurs in t at position ', j - i + 1);\n *        end;\n *    end;\n *    \n *    procedure Compute_borders(x: string; m: integer);\n *    begin\n *        Border[0] := -1;\n *        for i := 1 to m do begin\n *            j := Border[i - 1];\n *            while j >= 0 and x[i] != x[j + 1] do j := Border[j];\n *            Border[i] := j + 1;\n *        end;\n *    end;\n *    \n *    procedure Compute_MP_next(x: string; m: integer);\n *    begin\n *        MP_next[i] := 0; j := 0;\n *        for i := 1 to m do begin\n *            { at this point, we have j = MP_next[i] }\n *            while j > 0 and x[i] != x[j] do j := MP_next[j];\n *            j := j + 1;\n *            MP_next[i + 1] := j;\n *        end;\n *    end;\n *\n */\n\n#ifndef _MP_H_\n#define _MP_H_\n\nvoid compute_borders(const char *x, int *border, int m)\n{\n  border[0] = -1;\n  for(int i = 1; i <=m; i++){\n    int j = border[i-1];\n    while ((j>=0) && (x[i] != x[j+1]))\n      j = border[j];\n    border[i] = j+1;\n  }\n}\n\nstruct MP {\nMP(uint16_t x, uint16_t index) : index(index), x(x) {}\n  uint16_t index;\n  uint16_t x;\n};\n\nvoid compute_MP_next(const char *x, struct MP *MP_next, int m)\n{\n  MP_next[1] = MP(0, 0);\n  int j = 0;\n  for(int i = 1; i <= m; i++){\n    while ((j>0) && (x[i] != x[j]))\n      j = MP_next[j].index;\n    j = j+1;\n    MP_next[i+1] = MP(x[j-1], j);\n  }\n}\n\nvoid MP(const char *x, const char *t, struct MP *MP_next, int m, int n, int *match_cnt)\n{\n  int i = 1;\n  int j = 1;\n  fprintf(stderr, \"MP starting\\n\");\n  while (j <= n) {\n    while ((i==m+1) || ((i>0) && (x[i-1] != t[j-1]))){\n      //fprintf(stderr, \"char mismatch %d %d MP_next[i]=%d\\n\", i,j,MP_next[i]);\n      i = MP_next[i].index;\n    }\n    //fprintf(stderr, \"   char match %d %d\\n\", i, j);\n    i = i+1;\n    j = j+1;\n    if (i==m+1){\n      fprintf(stderr, \"%s occurs in t at position %d\\n\", x, j-i);\n      i = 1;\n      (*match_cnt)++;\n    }\n  }\n  fprintf(stderr, \"MP exiting\\n\");\n}\n\n#endif // _MP_H_\n"
  },
  {
    "path": "lib/strstr/cpp/strstr.h",
    "content": "/* Copyright (c) 2014 Quanta Research Cambridge, Inc\n *\n * Permission is hereby granted, free of charge, to any person obtaining a\n * copy of this software and associated documentation files (the \"Software\"),\n * to deal in the Software without restriction, including without limitation\n * the rights to use, copy, modify, merge, publish, distribute, sublicense,\n * and/or sell copies of the Software, and to permit persons to whom the\n * Software is furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n * DEALINGS IN THE SOFTWARE.\n */\n\n\nclass StrstrIndication : public StrstrIndicationWrapper\n{\npublic:\n  StrstrIndication(unsigned int id) : StrstrIndicationWrapper(id){\n    sem_init(&sem, 0, 0);\n    match_cnt = 0;\n  };\n  virtual void setupComplete() {\n    fprintf(stderr, \"Strstr::setupComplete\\n\");\n    sem_post(&sem);\n  }\n  virtual void searchResult (int v){\n    fprintf(stderr, \"searchResult = %d\\n\", v);\n    if (v == -1)\n      sem_post(&sem);\n    else \n      match_cnt++;\n  }\n  void wait() {\n    fprintf(stderr, \"Strstr::wait for semaphore\\n\");\n    sem_wait(&sem);\n  }\n  int match_cnt;\nprivate:\n  sem_t sem;\n};\n"
  },
  {
    "path": "lib/zedboard_robot/bsv/GyroController.bsv",
    "content": "// Copyright (c) 2014 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n`include \"ConnectalProjectConfig.bsv\"\nimport GetPut::*;\nimport Vector::*;\nimport StmtFSM::*;\nimport FIFO::*;\nimport SpecialFIFOs::*;\nimport Gearbox::*;\nimport ClientServer::*;\nimport ConnectalMemTypes::*;\nimport Leds::*;\nimport ConnectalSpi::*;\nimport MemWriteEngine::*;\nimport Pipe::*;\n\ninterface GyroCtrlRequest;\n   method Action write_reg_req(Bit#(8) addr, Bit#(8) val);\n   method Action read_reg_req(Bit#(8) addr);\n   method Action sample(Bit#(32) sgl_id, Bit#(32) alloc_sz, Bit#(32) sample_freq);\n   method Action set_en(Bit#(32) en);\nendinterface\n\ninterface GyroCtrlIndication;\n   method Action read_reg_resp(Bit#(8) val);\n   method Action write_reg_resp(Bit#(8) addr);\n   method Action memwrite_status(Bit#(32) addr, Bit#(32) wrap_cnt);\nendinterface\n\ninterface GyroSampleStream;\n   method Action sample(Int#(16) x, Int#(16) y, Int#(16) z);\nendinterface\n\ninterface GyroSimplePins;\n   interface SpiMasterPins#(1) spi;\n   interface LEDS leds;\nendinterface\n\ninterface GyroController;\n   interface GyroCtrlRequest req;\n   interface GyroSimplePins pins;\n   interface MemWriteClient#(64) dmaClient;\nendinterface\n\nmodule mkGyroController#(GyroCtrlIndication ind)(GyroController);\n\n   SPIMaster#(Bit#(16), 1)  spiCtrl    <- mkSPIMaster(1000, True);\n   FIFO#(Bool)     spi_aux    <- mkPipelineFIFO;\n   Reg#(Bit#(32))  sampleFreq <- mkReg(0);\n   Reg#(Bit#(32))  sampleCnt  <- mkReg(0);\n   FIFO#(Bool)     rc_fifo    <- mkFIFO1;\n`ifdef SIMULATION\n   Reg#(Bit#(8))   bsim_cnt   <- mkReg(0);\n`endif\n   let clk <- exposeCurrentClock;\n   let rst <- exposeCurrentReset;\n   Gearbox#(1,8,Bit#(8)) gb   <- mk1toNGearbox(clk,rst,clk,rst);\n   MemWriteEngine#(64,64,1,1) we <- mkMemWriteEngine;\n\n   \n   Reg#(Bit#(32))  en_memwr   <- mkReg(maxBound);\n   Reg#(Bit#(32))  cWrapCnt    <- mkReg(0);\n   Reg#(Bit#(32))  sglId      <- mkReg(0);\n   Reg#(Bit#(32))  allocSz    <- mkReg(0);\n   Reg#(Bit#(32))  writePtr   <- mkReg(0);\n   Reg#(Bit#(32))  cWritePtr  <- mkReg(0);\n\n   \n   let out_X_L = 'h28;\n   let out_X_H = 'h29;\n   let out_Y_L = 'h2A;\n   let out_Y_H = 'h2B;\n   let out_Z_L = 'h2C;\n   let out_Z_H = 'h2D;\n   let verbose = False;\n   \n   rule read_reg_resp;\n      let rv <- spiCtrl.response[0].get;\n      if (rc_fifo.first)\n\t ind.read_reg_resp(truncate(rv));\n      rc_fifo.deq;\n   endrule\n      \n   rule sample_req(sampleFreq > 0);\n      let new_sampleCnt = sampleCnt+1; \n      let sampling = True;\n      if (new_sampleCnt == sampleFreq-5) begin\n\t spiCtrl.request[0].put({1'b1,1'b0,out_X_L,8'h00});\n\t if(verbose) $display(\"sample_x_l\");\n      end\n      else if (new_sampleCnt == sampleFreq-4) begin\n\t spiCtrl.request[0].put({1'b1,1'b0,out_X_H,8'h00});\n\t if(verbose) $display(\"sample_x_h\");\n      end\n      else if (new_sampleCnt == sampleFreq-3) begin\n\t spiCtrl.request[0].put({1'b1,1'b0,out_Y_L,8'h00});\n\t if(verbose) $display(\"sample_y_l\");\n      end\n      else if (new_sampleCnt == sampleFreq-2) begin\n\t spiCtrl.request[0].put({1'b1,1'b0,out_Y_H,8'h00});\n\t if(verbose) $display(\"sample_y_h\");\n      end\n      else if (new_sampleCnt == sampleFreq-1) begin\n\t spiCtrl.request[0].put({1'b1,1'b0,out_Z_L,8'h00});\n\t if(verbose) $display(\"sample_z_l\");\n      end\n      else if (new_sampleCnt >= sampleFreq-0) begin\n\t spiCtrl.request[0].put({1'b1,1'b0,out_Z_H,8'h00});\n\t if(verbose) $display(\"sample_z_h\");\n\t new_sampleCnt = 0;\n      end\n      else begin\n\t sampling = False;\n      end\n      if(sampling) spi_aux.enq(True);\n      sampleCnt <= new_sampleCnt;\n   endrule\n   \n   rule sample_resp(sampleFreq > 0);\n      spi_aux.deq;\n      if(verbose) $display(\"sample_resp\");\n      let rv <- spiCtrl.response[0].get;\n`ifdef SIMULATION\n      bsim_cnt <= (bsim_cnt == 5) ? 0 : bsim_cnt+1;\n      let bsim_val = bsim_cnt[0]==1'b0 ? bsim_cnt+1 : 0;\n      gb.enq(cons(bsim_val,nil));\n`else\n      gb.enq(cons(truncate(rv),nil));\n`endif\n   endrule\n   \n   rule we_cmd_enq if (en_memwr != 0 && allocSz > 0);\n      Bit#(32) new_writePtr = writePtr + 8;\n      if (new_writePtr >= allocSz) begin\n         new_writePtr = 0;\n         en_memwr <= en_memwr-1;\n      end\n      writePtr <= new_writePtr;      \n      we.writeServers[0].request.put(MemengineCmd{sglId:sglId, base:extend(writePtr), burstLen:8, len:8, tag:0});\n   endrule\n   rule we_cmd_deq;\n      let rv <- we.writeServers[0].done.get;\n      Bit#(32) new_cWritePtr = cWritePtr + 8;\n      if(new_cWritePtr >= allocSz) begin\n\t new_cWritePtr = 0;\n\t cWrapCnt <= cWrapCnt+1;\n      end\n      cWritePtr <= new_cWritePtr;\n   endrule\n   \n   rule we_data_enq;\n      gb.deq;\n      we.writeServers[0].data.enq(pack(gb.first));\n   endrule\n   \n   interface GyroCtrlRequest req;\n      method Action write_reg_req(Bit#(8) addr, Bit#(8) val);\n\t spiCtrl.request[0].put({1'b0,1'b0,addr[5:0],val});\n\t ind.write_reg_resp(addr);\n\t rc_fifo.enq(False);\n      endmethod\n      method Action read_reg_req(Bit#(8) addr);\n\t spiCtrl.request[0].put({1'b1,1'b0,addr[5:0],8'h00});\n\t rc_fifo.enq(True);\n      endmethod\n      method Action sample(Bit#(32) sgl_id, Bit#(32) alloc_sz, Bit#(32) sample_freq);\n\t $display(\"sample %d %d %d\", sgl_id, alloc_sz, sample_freq);\n\t sampleFreq <= sample_freq;\n\t sampleCnt <= 0;\n\t allocSz <= alloc_sz;\n\t sglId <= sgl_id;\n      endmethod\n      method Action set_en(Bit#(32) en);\n\t en_memwr <= en;\n\t if(en == 0) ind.memwrite_status(cWritePtr, cWrapCnt);\n      endmethod\n   endinterface\n   \n   interface GyroSimplePins pins;\n      interface SpiMasterPins spi = spiCtrl.pins;\n      interface LEDS leds;\n         method Bit#(LedsWidth) leds() = truncate(pack(cWrapCnt));\n      endinterface\n   endinterface\n   interface dmaClient = we.dmaClient;\nendmodule\n"
  },
  {
    "path": "lib/zedboard_robot/bsv/HBridgeController.bsv",
    "content": "\n// Copyright (c) 2014 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\nimport Leds::*;\nimport Vector::*;\nimport FIFOF::*;\nimport Arith::*;\n\ninterface HBridgeCtrlRequest;\n   method Action ctrl(Vector#(2,Bit#(11)) power, Vector#(2,Bit#(1)) direction);\nendinterface\n\ninterface HBridgeCtrlIndication;\n   method Action hbc_event(Bit#(32) e);\nendinterface\n\ninterface HBridgePins;\n   method Bit#(1) direction();\n   method Bit#(1) enabled();\nendinterface\n\ninterface HBridge2Pins;\n   interface HBridgePins hbridge0;\n   interface HBridgePins hbridge1;\nendinterface\n\ninterface HBridgeSimplePins;\n   interface HBridge2Pins hbridge;\n   interface LEDS leds;\nendinterface\n \ninterface HBridgeController;\n   interface HBridgeCtrlRequest req;\n   interface HBridgeSimplePins pins;\nendinterface\n\ntypedef enum {HBridgeCtrlEvent_Stopped, HBridgeCtrlEvent_Started} HBridgeCtrlEvent deriving (Eq,Bits);\n\nmodule mkHBridgeController#(HBridgeCtrlIndication ind)(HBridgeController);\n   \n   Vector#(2, Reg#(Bit#(1))) direction <- replicateM(mkReg(0));\n   Vector#(2, Reg#(Bit#(1)))   enabled <- replicateM(mkReg(0));\n   Vector#(2, Reg#(Bit#(11)))    power <- replicateM(mkReg(0));\n   Vector#(2, Reg#(Bool))           pz <- replicateM(mkReg(True));\n   FIFOF#(Bit#(32))         event_fifo <- mkSizedFIFOF(4);\n   Bit#(8) leds_val =  {enabled[0],enabled[1],1'b0,1'b0,1'b0,1'b0,direction[0],direction[1]};  \n   \n   // more information on the Digilent PmodHB5:\n   // https://digilentinc.com/Data/Products/PMOD-HB5/PmodHB5_RevD_rm.pdf\n\n   // frequency of design: 100 mHz  \n   // frequency of PWM System: 2 kHz \n   // 2k design cycles == 1 PWM cycle\n   Reg#(Bit#(11)) fcnt <- mkReg(0);\n      \n   rule detect_event;\n      Vector#(2,Bool) npz;\n      for(int i = 0; i < 2; i=i+1) \n\t npz[i] = power[i]==0;\n      Bool started =  fold(booland, readVReg(pz)) && !fold(booland, npz);\n      Bool stopped = !fold(booland, readVReg(pz)) &&  fold(booland, npz);\n      Bit#(32) e = 0;\n      e = e | (extend(pack(stopped)) << pack(HBridgeCtrlEvent_Stopped));\n      e = e | (extend(pack(started)) << pack(HBridgeCtrlEvent_Started));\n      if (e != 0 && event_fifo.notFull) \n\t event_fifo.enq(e);\n      writeVReg(pz,npz);\n   endrule\n   \n   rule report_event;\n      ind.hbc_event(event_fifo.first);\n      event_fifo.deq;\n   endrule\n   \n   rule pwm;\n      for(Integer i = 0; i < 2; i=i+1)\n\t enabled[i] <= ((power[i] > 0) && (fcnt <= power[i])) ? 1 : 0;\n      fcnt <= fcnt+1;\n   endrule\n   \n   interface HBridgeCtrlRequest req;\n      method Action ctrl(Vector#(2,Bit#(11)) p, Vector#(2,Bit#(1)) d);\n\t for(Integer i = 0; i < 2; i=i+1) begin\n\t    direction[i] <= d[i];\n\t    power[i]     <= p[i];\n\t end\n      endmethod\n   endinterface\n   \n   interface HBridgeSimplePins pins;\n   interface HBridge2Pins hbridge;\n      interface HBridgePins hbridge0;\n\t method Bit#(1) enabled();\n\t    return enabled[0];\n\t endmethod\n\t method Bit#(1) direction();\n\t    return direction[0];\n\t endmethod\n      endinterface\n      interface HBridgePins hbridge1;\n\t method Bit#(1) enabled();\n\t    return enabled[1];\n\t endmethod\n\t method Bit#(1) direction();\n\t    return direction[1];\n\t endmethod\n      endinterface\n   endinterface\n   \n   interface LEDS leds;\n      method Bit#(LedsWidth) leds() = leds_val;\n   endinterface\n   endinterface\n\nendmodule\n"
  },
  {
    "path": "lib/zedboard_robot/bsv/MaxSonarController.bsv",
    "content": "\n// Copyright (c) 2014 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\n`include \"ConnectalProjectConfig.bsv\"\nimport Leds::*;\nimport Vector::*;\nimport ConnectalMemTypes::*;\nimport GetPut::*;\nimport Gearbox::*;\nimport FIFO::*;\n\ninterface MaxSonarPins;\n   method Bit#(1) range_ctrl();\n   method Action pulse(Bit#(1) v);\nendinterface\n\ninterface MaxSonarCtrlRequest;\n   method Action pulse_width();\n   method Action range_ctrl(Bit#(1) v);\nendinterface\n\ninterface MaxSonarCtrlIndication;\n   method Action range_ctrl(Bit#(1) v);\n   method Action pulse_width(Bit#(32) v);\nendinterface\n\ninterface MaxSonarSampleStream;\n   method Action sample(Bit#(32) v);\nendinterface\n\ninterface MaxSonarSimplePins;\n   interface MaxSonarPins maxsonar;\n   interface LEDS leds;\nendinterface\n\ninterface MaxSonarController;\n   interface MaxSonarCtrlRequest req;\n   interface MaxSonarSimplePins pins;\nendinterface\n\nmodule mkMaxSonarController#(MaxSonarCtrlIndication ind)(MaxSonarController);\n   \n   Reg#(Bit#(1)) range_ctrl_reg <- mkReg(0);\n   Vector#(2,Reg#(Bit#(32))) high_cnt <- replicateM(mkReg(0));\n   Reg#(Bit#(1)) last_pulse <- mkReg(0);\n   Reg#(Bool) end_pulse <- mkReg(False);\n   FIFO#(Bool)     pw_fifo    <- mkSizedFIFO(1);\n`ifdef SIMULATION\n   Reg#(Bit#(32))  bsim_cnt   <- mkReg(0);\n   Reg#(Bit#(32))  bsim_pulse <- mkReg(0);\n`endif\n   let clk <- exposeCurrentClock;\n   let rst <- exposeCurrentReset;\n   Gearbox#(1,2,Bit#(32)) gb   <- mk1toNGearbox(clk,rst,clk,rst);\n   let verbose = True;\n   \n`ifdef SIMULATION\n   rule bsim_pulse_rule if (!end_pulse);\n      if (bsim_pulse[10] == 1) begin\n\t bsim_cnt <= bsim_cnt+1;\n\t high_cnt[1] <= bsim_cnt+1;\n\t end_pulse <= True;\n\t bsim_pulse <= 0;\n      end \n      else begin\n\t bsim_pulse <= bsim_pulse+1;\n      end\n   endrule\n`endif   \n\n   rule fill_gb if (end_pulse);\n      end_pulse <= False;\n      gb.enq(cons(high_cnt[1],nil));\n   endrule\n   \n   interface MaxSonarCtrlRequest req;\n      method Action range_ctrl(Bit#(1) v);\n\t range_ctrl_reg <= v;\n\t ind.range_ctrl(v);\n      endmethod\n      method Action pulse_width();\n\t ind.pulse_width(high_cnt[1]);\n      endmethod\n   endinterface\n   \n   interface MaxSonarSimplePins pins;\n   // pulse width modulation\n   interface MaxSonarPins maxsonar;\n      method Bit#(1) range_ctrl();\n\t return range_ctrl_reg;\n      endmethod\n      method Action pulse(Bit#(1) v);\n\t last_pulse <= v;\n\t if (last_pulse == 1 && v == 0) begin // end of pulse\n\t    high_cnt[1] <= high_cnt[0];\n\t    high_cnt[0] <= 0;\n\t    end_pulse <= True;\n\t end\n\t else if (v == 1) begin\n\t    high_cnt[0] <= high_cnt[0]+1;\n\t end\n      endmethod\n   endinterface\n   \n   interface LEDS leds;\n      method Bit#(LedsWidth) leds() = extend(range_ctrl_reg);\n   endinterface\n   endinterface\n   \nendmodule\n"
  },
  {
    "path": "lib/zedboard_robot/cpp/read_buffer.cpp",
    "content": "// Copyright (c) 2013-2014 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n#include <stdio.h>\n#include <stdlib.h>\n#include <errno.h>\n#include <string.h>\n#include <unistd.h>\n#include <sys/types.h>\n#include <sys/socket.h>\n#include <sys/un.h>\n#include <semaphore.h>\n#include <pthread.h>\n#include <assert.h>\n#include <netdb.h>\n#include <arpa/inet.h>\n#include <signal.h>\n\n#include \"dmaManager.h\"\n#include \"read_buffer.h\"\n\n\nint reader::read_circ_buff(int buff_len, unsigned int ref_dstAlloc, int dstAlloc, char* dstBuffer, char *snapshot, int write_addr, int write_wrap_cnt)\n{\n  int dwc = write_wrap_cnt - wrap_cnt;\n  int two,top,bottom,datalen=0;\n  if(dwc == 0){\n    assert(addr <= write_addr);\n    two = false;\n    top = write_addr;\n    bottom = addr;\n    datalen = write_addr - addr;\n  } else if (dwc == 1 && addr > write_addr) {\n    two = true;\n    top = addr;\n    bottom = write_addr;\n    datalen = (buff_len-top)+bottom;\n  } else if (write_addr == 0) {\n    two = false;\n    top = buff_len;\n    bottom = 0;\n    datalen = buff_len;\n  } else {\n    two = true;\n    top = write_addr;\n    bottom = write_addr;\n    datalen = buff_len;\n    fprintf(stderr, \"WARNING: sock_server::read_circ_buffer dwc>1\\n\");\n  }\n  portalCacheFlush(dstAlloc, dstBuffer, buff_len, 1);\n  if (verbose) fprintf(stderr, \"bottom:%4x, top:%4x, two:%d, datalen:%4x, dwc:%d\\n\", bottom,top,two,datalen,dwc);\n  if (datalen){\n    if (two) {\n      memcpy(snapshot,                  dstBuffer+top,    datalen-bottom);\n      memcpy(snapshot+(datalen-bottom), dstBuffer,        bottom        );\n    } else {\n      memcpy(snapshot,                  dstBuffer+bottom, datalen       );\n  }\n  }\n  addr = write_addr;\n  wrap_cnt = write_wrap_cnt;\n  return datalen;\n}\n"
  },
  {
    "path": "lib/zedboard_robot/cpp/read_buffer.h",
    "content": "// Copyright (c) 2013-2014 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\nclass reader\n{\n private:\n  int wrap_cnt;\n  int addr;\n public:\n  int verbose;\n  reader(): wrap_cnt(0), addr(0){}\n  int read_circ_buff(int buff_len, unsigned int ref_dstAlloc, int dstAlloc, char* dstBuffer,char *snapshot, int write_addr, int write_wrap_cnt);\n};\n"
  },
  {
    "path": "pcie/Makefile",
    "content": "# Copyright (c) 2014 Quanta Research Cambridge, Inc\n#\n# Permission is hereby granted, free of charge, to any person obtaining a\n# copy of this software and associated documentation files (the \"Software\"),\n# to deal in the Software without restriction, including without limitation\n# the rights to use, copy, modify, merge, publish, distribute, sublicense,\n# and/or sell copies of the Software, and to permit persons to whom the\n# Software is furnished to do so, subject to the following conditions:\n#\n# The above copyright notice and this permission notice shall be included\n# in all copies or substantial portions of the Software.\n#\n# THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n# OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n# DEALINGS IN THE SOFTWARE.\n#\n\nifeq (\"$(DESTDIR)\",\"\")\nPREFIX?=/usr/local\nelse\nPREFIX?=/usr\nendif\n\nall:\n\ninstall:\n\tinstall -D -m755 pcieflat $(DESTDIR)$(PREFIX)/bin/pcieflat\n\nclean:\n"
  },
  {
    "path": "pcie/pcieflat",
    "content": "#!/usr/bin/env python3\n# Copyright (c) 2014 Quanta Research Cambridge, Inc\n#\n# Permission is hereby granted, free of charge, to any person obtaining a\n# copy of this software and associated documentation files (the \"Software\"),\n# to deal in the Software without restriction, including without limitation\n# the rights to use, copy, modify, merge, publish, distribute, sublicense,\n# and/or sell copies of the Software, and to permit persons to whom the\n# Software is furnished to do so, subject to the following conditions:\n#\n# The above copyright notice and this permission notice shall be included\n# in all copies or substantial portions of the Software.\n#\n# THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n# OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n# DEALINGS IN THE SOFTWARE.\n#\n\nfrom __future__ import print_function\n\nimport fcntl, glob, json, struct, subprocess, sys\nfrom gmpy import mpz\nBNOC_TRACE = 0xc008b508\nTrace_len = 144\nstruct_traceData = '@ L I I 16I 16I'\nBNOC_GET_TLP = 0x8008b507\nTlp_len = 24\nBNOC_ENABLE_TRACE = 0x8008b508\nEnable_len = 4\nPCIE_CHANGE_ENTRY = 0x8008b50f\nstruct_changeEntry = '@ I I'\nChangeEntry_len = 8\n\n# 64-bit BAR\ntlpdatalog = [\n    '000000011184ffff4a000001020000040018001068470000',\n    '000000020984fff0000000010018000fdf508000e775b7be',\n    '000000031184ffff4a0000010200000400180000bad0dada',\n    '000000040984fff0000000010018000fdf5040002c7bdba8',\n    '000000051184ffff4a0000010200000400180000005a05a0',\n    '000000060984fff0000000010018000fdf5000001ce1d27f',\n    '000000071184ffff4a0000010200000400180000005b05b0',\n    '000000080984fff0000000010018000fdf5040009c773d52',\n    '000000091184ffff4a0000010200000400180000005a05a0',\n    '0000000a0984fff0000000010018000fdf50c0107d93c3c9',\n    '0000000b1184ffff4a000001020000040018001068470000',\n    '0000000c0984fff0000000010018000fdf50800099159bf9',\n    '0000000d1184ffff4a0000010200000400180000bad0dada',\n    '0000000e0984fff0000000010018000fdf5040008fc4124f',\n    '0000000f1184ffff4a0000010200000400180000005a05a0',\n    '000000100984fff0000000010018000fdf5000000f52fd62',\n]\n\nTlpPacketType = [\n    'MRW', # 'MEMORY_READ_WRITE'\n    'MEMORY_READ_LOCKED',\n    'IO_REQUEST',\n    'UNKNOWN_TYPE_3',\n    'CONFIG_0_READ_WRITE',\n    'CONFIG_1_READ_WRITE',\n    'UNKNOWN_TYPE_6',\n    'UNKNOWN_TYPE_7',\n    'UNKNOWN_TYPE_8',\n    'UNKNOWN_TYPE_9',\n    'COMP',\n    'COMPLETION_LOCKED',\n    'UNKNOWN_TYPE_12',\n    'UNKNOWN_TYPE_13',\n    'UNKNOWN_TYPE_14',\n    'UNKNOWN_TYPE_15',\n    'MSG_ROUTED_TO_ROOT',\n    'MSG_ROUTED_BY_ADDR',\n    'MSG_ROUTED_BY_ID',\n    'MSG_ROOT_BROADCAST',\n    'MSG_LOCAL',\n    'MSG_GATHER',\n    'UNKNOWN_TYPE_22',\n    'UNKNOWN_TYPE_23',\n    'UNKNOWN_TYPE_24',\n    'UNKNOWN_TYPE_25',\n    'UNKNOWN_TYPE_26',\n    'UNKNOWN_TYPE_27',\n    'UNKNOWN_TYPE_28',\n    'UNKNOWN_TYPE_29',\n    'UNKNOWN_TYPE_30',\n    'UNKNOWN_TYPE_31'\n]\n\nTlpPacketFormat = [\n    'MEM_READ__3DW     ',\n    'MEM_READ__4DW     ',\n    'MEM_WRITE_3DW_DATA',\n    'MEM_WRITE_4DW_DATA',\n    'TLP Prefix',\n    'UNKNOWN_FMT_5',\n    'UNKNOWN_FMT_6',\n    'UNKNOWN_FMT_7',\n]\n\nPcie3ChangeSrc = [\n    'none',\n    'current_speed',\n    'dpa_substate_change',\n    'err_cor_out',\n    'err_fatal_out',\n    'err_nonfatal_out',\n    'flr_in_process',\n    'function_power_state',\n    'function_status',\n    'hot_reset_out',\n    'link_power_state',\n    'ltr_enable',\n    'ltssm_state',\n    'max_payload',\n    'max_read_req',\n    'negotiated_width',\n    'obff_enable',\n    'phy_link_down',\n    'phy_link_status',\n    'pl_status_change',\n    'power_state_change_interrupt',\n    'rcb_status',\n    'backpressure_count'\n]\n\nfirst_vcd_timestamp = mpz(0)\nlast_vcd_timestamp = mpz(0)\nlast_vcd_pktclass_code = None\n\ndef byteswap(be):\n    return '%s%s%s%s' % (be[6:8],be[4:6],be[2:4],be[0:2])\n\npktclassCodes = {\n    'CpuRReq': 'S',\n    'CpuWReq': 'T',\n    'CpuRResp': 's',\n    '(to) slave continuation': 'c',\n    'DmaWReq': 'W',\n    'DmaRReq': 'M',\n    'DmaRResp': 'm',\n    '(to) master continuation': 'C',\n    'trace': 't',\n}\n\nvcd_header_template='''\n$version\n   tlp.py\n$end\n$comment\n$end\n$timescale 8ns $end\n$scope module logic $end\n%(vars)s\n$upscope $end\n$enddefinitions $end\n'''\n\nunused='''\n$dumpvars\n%(dumpvars)s\n$end\n'''\n\ndef emit_vcd_header(f):\n    f.write(vcd_header_template\n            % { 'vars': '\\n'.join(['$var wire 1 %s %s $end' % (pktclassCodes[k], k.lower().replace(' ', '_')) for k in pktclassCodes]),\n                'dumpvars': '\\n'.join(['0%s' % pktclassCodes[k] for k in pktclassCodes])\n            })\n\ndef emit_vcd_entry(f, timestamp, pktclass):\n    global first_vcd_timestamp, last_vcd_timestamp, last_vcd_pktclass_code\n    if not timestamp:\n        return\n    if not first_vcd_timestamp:\n        first_vcd_timestamp = timestamp\n    #print last_vcd_timestamp, timestamp, (timestamp < last_vcd_timestamp)\n    if last_vcd_timestamp and (timestamp < last_vcd_timestamp):\n        f.write('$comment %s %s %s $end\\n' % (hex(last_vcd_timestamp), hex(timestamp), hex(timestamp + mpz('100000000', 16))))\n        timestamp = timestamp + mpz('100000000', 16)\n        f.write('$comment %s %s $end\\n' % (hex(timestamp), hex(timestamp - first_vcd_timestamp)))\n\n    #timestamp = timestamp - first_vcd_timestamp\n\n    if last_vcd_timestamp and timestamp > (last_vcd_timestamp+1):\n        f.write('#%s\\n0%s\\n' % ((last_vcd_timestamp+mpz(1)), last_vcd_pktclass_code))\n    if pktclass in pktclassCodes:\n        pktclass_code = pktclassCodes[pktclass]\n        f.write('#%s\\n' % timestamp)\n        f.write('1%s\\n' % pktclass_code)\n        if last_vcd_pktclass_code and last_vcd_pktclass_code != pktclass_code:\n            f.write('0%s\\n' % last_vcd_pktclass_code)\n        last_vcd_pktclass_code = pktclass_code\n        last_vcd_timestamp = timestamp\n    else:\n        f.write('$comment %s $end\\n' % pktclass)\n\ndef pktClassification(tlpsof, tlpeof, tlpbe, pktformat, pkttype, portnum, address):\n    ## altera does not fill in the BE bits\n    #if tlpbe == '0000':\n    #return 'trace'\n    if tlpsof == 0:\n        if portnum == 4:\n            return 'DmaRCon'\n        else:\n            return 'CpuRCon'\n    if portnum == 4:\n        if pkttype == 10: # COMPLETION\n            return 'DmaRRsp'\n        else:\n            if pktformat == 2 or pktformat == 3:\n                return 'CpuWReq'\n            else:\n                return 'CpuRReq'\n    elif portnum == 8:\n        if pkttype == 10: # COMPLETION\n            return 'CpuRRsp'\n        else:\n            if pktformat == 2 or pktformat == 3:\n                if (address[0:3] == 'fee'):\n                    return 'Interru'\n                else:\n                    return 'DmaWReq'\n            else:\n                return 'DmaRReq'\n    else:\n        return '   Misc'\n\nclassCounts = {}\nlast_seqno = mpz(-1)\n\ndef interfaceId(interfaceNumber):\n    if (interfaceNumber >= 0 and interfaceNumber < len(fooMap)):\n        return fooMap[interfaceNumber]\n    else:\n        return '%x' % interfaceNumber\n\ndef interfaceName(interfaceNumber):\n    if (interfaceNumber >= 0 and interfaceNumber < len(fooMap)):\n        return interfaceMap[fooMap[interfaceNumber]]\n    else:\n        return '%x' % interfaceNumber\n\ndef print_tlp(tlpdata, f=None):\n    global last_seqno\n    def segment(i):\n        return tlpdata[i*8:i*8+8]\n    def byteswap(w):\n        def byte(i):\n            return w[i*2:i*2+2]\n        return ''.join(map(byte, [3,2,1,0]))\n\n    words = map(segment, [0,1,2,3,4,5])\n\n    seqno = mpz(tlpdata[0:8],16)\n    if last_seqno >= 0:\n        delta = seqno - last_seqno\n    else:\n        delta = 0\n    tlpsof = int(tlpdata[9:10],16) & 1\n    tlpeof = int(tlpdata[10:12],16) >> 7\n    tlpbe  = tlpdata[12:16]\n    tlphit = int(tlpdata[10:12],16) & 0x7f\n    pktformat = (int(tlpdata[16:17],16) >> 1) & 7\n    pkttype = (int(tlpdata[16:18],16) & 0x1f)\n\n    address=0\n    if TlpPacketFormat[pktformat] == 'MEM_READ__4DW     ' or TlpPacketFormat[pktformat] == 'MEM_WRITE_4DW_DATA':\n        address = tlpdata[32:]\n    elif TlpPacketFormat[pktformat] == 'MEM_READ__3DW     ' or TlpPacketFormat[pktformat] == 'MEM_WRITE_3DW_DATA':\n        address = tlpdata[32:40]\n\n    portnum = int(tlpdata[8:10],16) >> 1\n    pktclass = pktClassification(tlpsof, tlpeof, tlpbe, pktformat, pkttype, portnum, address)\n    if pktclass in classCounts:\n       classCounts[pktclass] += 1\n    else:\n       classCounts[pktclass] = 1\n\n    if f:\n        emit_vcd_entry(f, seqno, pktclass)\n\n    headerstr = tlpdata\n    headerstr = ''\n    headerstr = headerstr + '%6s' % (pktclass)\n    if tlpsof:\n        headerstr = headerstr + ':%4s:%18s' % (TlpPacketType[pkttype], TlpPacketFormat[pktformat])\n    else:\n        headerstr = headerstr + '                        '\n    headerstr = headerstr + ' ' + tlpdata[8:10] + ' ' + hex(int(tlpdata[8:10],16) >> 1)\n    headerstr = headerstr + ' tlp(%s %d %d %d)' % (tlpbe, tlphit, tlpeof, tlpsof)\n    address = -1\n    if tlpsof == 0:\n        headerstr = headerstr + '                            data:' + tlpdata[16:]\n    elif TlpPacketFormat[pktformat] == 'MEM_WRITE_3DW_DATA' and TlpPacketType[pkttype] == 'COMP':\n        headerstr = headerstr + '                        tag:' + tlpdata[36:38]\n        headerstr = headerstr + ' ' + tlpdata[32:36]\n        headerstr = headerstr + ' ' + tlpdata[24:28]\n        headerstr = headerstr + ' ' + tlpdata[28:29]\n        headerstr = headerstr + ' ' + tlpdata[20:21] + str(int(tlpdata[20:21],16) >> 3)\n        headerstr = headerstr + ' ' + tlpdata[29:32]\n        headerstr = headerstr + ' ' + tlpdata[38:40]\n        headerstr = headerstr + ' %3d' % (int(tlpdata[21:24],16) & 0x3ff)\n        headerstr = headerstr + ' ' + byteswap(tlpdata[40:])\n    elif TlpPacketFormat[pktformat] == 'MEM_READ__3DW     ' or TlpPacketFormat[pktformat] == 'MEM_WRITE_3DW_DATA':\n        address = tlpdata[32:40]\n        headerstr = headerstr + '  ' + address\n        address = int(address,16)\n        headerstr = headerstr + ' %4x'% ((address >> 2) % 8192)\n        headerstr = headerstr + ' be(' + tlpdata[31:32] + ' ' + tlpdata[30:31] + ')'\n        headerstr = headerstr + ' tag:' + tlpdata[28:30]\n        headerstr = headerstr + ' ' + tlpdata[24:28]\n        headerstr = headerstr + '                  %3d' % (int(tlpdata[21:24],16) & 0x3ff)\n        if TlpPacketFormat[pktformat] == 'MEM_WRITE_3DW_DATA':\n            headerstr = headerstr + ' ' + byteswap(tlpdata[40:])\n    elif TlpPacketFormat[pktformat] == 'MEM_READ__4DW     ' or TlpPacketFormat[pktformat] == 'MEM_WRITE_4DW_DATA':\n        address = tlpdata[32:]\n        headerstr = headerstr + ' address: ' + address\n        address = int(address,16)\n        headerstr = headerstr + ' be(1st: ' + tlpdata[31:32] + ' last:' + tlpdata[30:31] + ')'\n        headerstr = headerstr + ' tag:' + tlpdata[28:30]\n        headerstr = headerstr + ' reqid:' + tlpdata[24:28]\n        headerstr = headerstr + ' length:' + str(int(tlpdata[21:24],16) & 0x3ff)\n    elif TlpPacketFormat[pktformat] == 'TLP Prefix':\n        headerstr = headerstr + tlpdata\n    else:\n        headerstr = headerstr + '  tlp data:' + tlpdata[40:]\n        headerstr = headerstr + 'lower addr:' + tlpdata[38:40]\n        headerstr = headerstr + '       tag:' + tlpdata[36:38]\n        headerstr = headerstr + '     reqid:' + tlpdata[34:36]\n        headerstr = headerstr + ' bytecount:' + '0x' + tlpdata[33:34]\n        headerstr = headerstr + '       bcm:' + str(int(tlpdata[32:33], 16) & 1)\n        headerstr = headerstr + '   cstatus:' + str((int(tlpdata[32:33], 16) >> 1) & 7)\n        headerstr = headerstr + '    cmplid:' + tlpdata[30:32]\n        headerstr = headerstr + '    cmplen:' + tlpdata[27:30]\n        headerstr = headerstr + '   nosnoop:' + str(int(tlpdata[26:27],16) & 1)\n        headerstr = headerstr + '   relaxed:' + str(int(tlpdata[26:27],16) & 2)\n        headerstr = headerstr + '   poison:' + str(int(tlpdata[26:27],16) & 4)\n        headerstr = headerstr + '   digest:' + str(int(tlpdata[26:27],16) & 8)\n        headerstr = headerstr + '     zero:' + tlpdata[25:26]\n        headerstr = headerstr + '   tclass:' + tlpdata[24:25]\n        headerstr = headerstr + '  pkttype:' + str(int(tlpdata[22:24],16) & 0x1f) + ' ' + TlpPacketType[int(tlpdata[22:24],16) & 0x1f]\n        headerstr = headerstr + '  format:' + str((int(tlpdata[22:24],16) >> 1) & 3) + ' ' + TlpPacketFormat[(int(tlpdata[22:24],16) >> 1) & 3]\n    if portnum == 4:\n        dir = 'RX'\n    elif portnum == 8:\n        dir = 'TX'\n    else:\n        dir = '__'\n    if tlpsof == 0:\n        dir = dir + 'cc'    # continuation\n    elif pkttype == 10: \n        dir = dir + 'pp'    # response\n    else:\n        dir = dir + 'qq'    # request\n    smeth = ''\n    if address != -1 and address < baseLimit and interfaceMap != {}:\n        address = address - base\n        interfaceNumber = address / 0x10000\n        offset = address - interfaceNumber * 0x10000\n        methodNumber = offset / 0x100\n        #print 'AA', \"%6x\" % address, \"%2x\" % interfaceNumber, \"%2x\" % methodNumber\n        t = interfaceName(interfaceNumber)\n        if methodNumber == 0:\n            smeth = '/dir'\n        elif methodNumber <= len(t):\n            offset = offset - methodNumber * 0x100\n            smeth = '/'+t[methodNumber-1]\n        smeth = ('%02d' % interfaceNumber) + '/' + interfaceId(interfaceNumber) + smeth + '/' + \"%x\" % (offset/4)\n    print(dir, '%10d %10d %s' % (seqno, delta, headerstr), smeth)\n    #print '                      ' + tlpdata[0:8] + ' ' + tlpdata[8:]\n    if len(tlpdata) != 48:\n        print('bogus len', len(tlpdata))\n        sys.exit(1)\n    last_seqno = seqno\n\ndef print_tlp_log(tlplog, f=None, lf=None):\n    if f:\n        emit_vcd_header(f)\n    #ts     delta           response   foo XXX tlp(be hit eof sof) pkttype format             address  off be(1st last) tag req clid stat nosnoop bcnt laddr length data \n    print('             ts     delta   response                     XXX          tlp          address  off   be       tag     clid  nosnp  laddr        data')\n    print('                                pkttype format               foo (be hit eof sof)            (1st last)        req     stat  bcnt    length')\n    for tlpdata in tlplog:\n        if tlpdata.startswith('00000000') or tlpdata == '':\n            continue\n        if lf:\n            lf.write(tlpdata+'\\n')\n        print_tlp(tlpdata, f)\n\nif __name__ == '__main__':\n    argindex = 1\n    argcount = len(sys.argv)\n    jsondata = {}\n    interfaceMap = {}\n    if argcount >= 2 and sys.argv[argindex] == '-j':\n        fooMap = sys.argv[argindex+1].split(':')\n        print('FFF', fooMap)\n        j2file = open(sys.argv[argindex + 2]).read()\n        jsondata = json.loads(j2file)\n        argindex = argindex + 3\n        argcount = argcount - 3\n        for item in jsondata['interfaces']:\n            interfaceMap[item['name']] = [mitem['name'] for mitem in item['decls']]\n    devfilenames = glob.glob('/dev/portal_*')\n    print('pcieflat: devices are', devfilenames)\n    if argcount == 2:\n        tlplog = open(sys.argv[argindex]).read().split('\\n')\n        base = 0\n    elif False:\n        tlplog = subprocess.check_output(['connectalutil', devfilenames[0]]).split('\\n')\n        tlpfirst = tlplog.pop(0)\n        base = int(tlpfirst[0:16],16)\n        base = int(tlpfirst[0:8],16)\n    else:\n        fd = open(devfilenames[0], 'rw')\n        try:\n            while 1:\n                buf = fcntl.ioctl(fd, PCIE_CHANGE_ENTRY, ' ' * ChangeEntry_len)\n                (ts,v) = struct.unpack_from(struct_changeEntry, buf)\n                if (v == 0 or v == 0xbad0add0 or ts == 0xbad0add0):\n                    break\n                src = v & 0xff\n                value = v >> 8\n                print('pcie status change: %12d src=%20s:%02d value=%#06x' % (ts, Pcie3ChangeSrc[src], src, value))\n                pass\n        except:\n            pass\n        buf = fcntl.ioctl(fd, BNOC_TRACE, ' ' * Trace_len)\n        traceData = struct.unpack_from(struct_traceData, buf)\n        #print 'SSS', traceData\n        base = traceData[0]\n        #print ('base %x' % base), 'trace', traceData[1], 'len', traceData[2], 'intval', ['%x' % p for p in traceData[3:3+16]], 'name', traceData[19:19+16]\n        tlplog = []\n        tlplog.append('%016x' % traceData[0])\n        counter = traceData[2]\n        while counter > 0:\n            counter = counter - 1\n            buf = fcntl.ioctl(fd, BNOC_GET_TLP, ' ' * Tlp_len)\n            foo = ''\n            for x in buf:\n                foo = \"%02x\" % ord( x ) + foo\n            tlplog.append(foo)\n        fcntl.ioctl(fd, BNOC_ENABLE_TRACE, 1)\n        #for foo in tlplog:\n        #    print foo\n        #sys.exit(1)\n    tlplog.sort()\n    lf = open('tlp.log', 'w')\n    f = open('tlp.vcd', 'w')\n    baseLimit = base + 16 * 0x10000\n    print_tlp_log(tlplog, f, lf)\n    print(classCounts)\n    print(sum([ classCounts[k] for k in classCounts]))\n    f.close()\n    lf.close()\n"
  },
  {
    "path": "pcie/tlp.py",
    "content": "#!/usr/bin/env python3\n\nfrom __future__ import print_function\n\nimport os\nimport re\nimport sys\nimport subprocess\nfrom gmpy import mpz\n\n# 64-bit BAR\ntlpdatalog = [\n    '000000011184ffff4a000001020000040018001068470000',\n    '000000020984fff0000000010018000fdf508000e775b7be',\n    '000000031184ffff4a0000010200000400180000bad0dada',\n    '000000040984fff0000000010018000fdf5040002c7bdba8',\n    '000000051184ffff4a0000010200000400180000005a05a0',\n    '000000060984fff0000000010018000fdf5000001ce1d27f',\n    '000000071184ffff4a0000010200000400180000005b05b0',\n    '000000080984fff0000000010018000fdf5040009c773d52',\n    '000000091184ffff4a0000010200000400180000005a05a0',\n    '0000000a0984fff0000000010018000fdf50c0107d93c3c9',\n    '0000000b1184ffff4a000001020000040018001068470000',\n    '0000000c0984fff0000000010018000fdf50800099159bf9',\n    '0000000d1184ffff4a0000010200000400180000bad0dada',\n    '0000000e0984fff0000000010018000fdf5040008fc4124f',\n    '0000000f1184ffff4a0000010200000400180000005a05a0',\n    '000000100984fff0000000010018000fdf5000000f52fd62',\n]\n\nTlpPacketType = [\n    'MEMORY_READ_WRITE',\n    'MEMORY_READ_LOCKED',\n    'IO_REQUEST',\n    'UNKNOWN_TYPE_3',\n    'CONFIG_0_READ_WRITE',\n    'CONFIG_1_READ_WRITE',\n    'UNKNOWN_TYPE_6',\n    'UNKNOWN_TYPE_7',\n    'UNKNOWN_TYPE_8',\n    'UNKNOWN_TYPE_9',\n    'COMPLETION',\n    'COMPLETION_LOCKED',\n    'UNKNOWN_TYPE_12',\n    'UNKNOWN_TYPE_13',\n    'UNKNOWN_TYPE_14',\n    'UNKNOWN_TYPE_15',\n    'MSG_ROUTED_TO_ROOT',\n    'MSG_ROUTED_BY_ADDR',\n    'MSG_ROUTED_BY_ID',\n    'MSG_ROOT_BROADCAST',\n    'MSG_LOCAL',\n    'MSG_GATHER',\n    'UNKNOWN_TYPE_22',\n    'UNKNOWN_TYPE_23',\n    'UNKNOWN_TYPE_24',\n    'UNKNOWN_TYPE_25',\n    'UNKNOWN_TYPE_26',\n    'UNKNOWN_TYPE_27',\n    'UNKNOWN_TYPE_28',\n    'UNKNOWN_TYPE_29',\n    'UNKNOWN_TYPE_30',\n    'UNKNOWN_TYPE_31'\n]\n\nTlpPacketFormat = [\n    'MEM_READ_3DW_NO_DATA',\n    'MEM_READ_4DW_NO_DATA',\n    'MEM_WRITE_3DW_DATA',\n    'MEM_WRITE_4DW_DATA'\n]\n\nfirst_vcd_timestamp = mpz(0)\nlast_vcd_timestamp = mpz(0)\nlast_vcd_pktclass_code = None\n\npktclassCodes = {\n    'Slave Request': 'S',\n    'Slave Write Request': 'T',\n    'Slave Response': 's',\n    'slave continuation': 'c',\n    'Master Write Request': 'W',\n    'Master Request': 'M',\n    'Master Response': 'm',\n    'master continuation': 'C',\n    'trace': 't',\n}\n\nvcd_header_template='''\n$version\n   tlp.py\n$end\n$comment\n$end\n$timescale 8ns $end\n$scope module logic $end\n%(vars)s\n$upscope $end\n$enddefinitions $end\n'''\n\nunused='''\n$dumpvars\n%(dumpvars)s\n$end\n'''\n\ndef emit_vcd_header(f):\n    f.write(vcd_header_template\n            % { 'vars': '\\n'.join(['$var wire 1 %s %s $end' % (pktclassCodes[k], k.lower().replace(' ', '_')) for k in pktclassCodes]),\n                'dumpvars': '\\n'.join(['0%s' % pktclassCodes[k] for k in pktclassCodes])\n            })\n\ndef emit_vcd_entry(f, timestamp, pktclass):\n    global first_vcd_timestamp, last_vcd_timestamp, last_vcd_pktclass_code\n    if not timestamp:\n        return\n    if not first_vcd_timestamp:\n        first_vcd_timestamp = timestamp\n    print(last_vcd_timestamp, timestamp, (timestamp < last_vcd_timestamp))\n    if last_vcd_timestamp and (timestamp < last_vcd_timestamp):\n        f.write('$comment %s %s %s $end\\n' % (hex(last_vcd_timestamp), hex(timestamp), hex(timestamp + mpz('100000000', 16))))\n        timestamp = timestamp + mpz('100000000', 16)\n        f.write('$comment %s %s $end\\n' % (hex(timestamp), hex(timestamp - first_vcd_timestamp)))\n\n    #timestamp = timestamp - first_vcd_timestamp\n\n    if last_vcd_timestamp and timestamp > (last_vcd_timestamp+1):\n        f.write('#%s\\n0%s\\n' % ((last_vcd_timestamp+mpz(1)), last_vcd_pktclass_code))\n    if pktclass in pktclassCodes:\n        pktclass_code = pktclassCodes[pktclass]\n        f.write('#%s\\n' % timestamp)\n        f.write('1%s\\n' % pktclass_code)\n        if last_vcd_pktclass_code and last_vcd_pktclass_code != pktclass_code:\n            f.write('0%s\\n' % last_vcd_pktclass_code)\n        last_vcd_pktclass_code = pktclass_code\n        last_vcd_timestamp = timestamp\n    else:\n        f.write('$comment %s $end\\n' % pktclass)\n\ndef pktClassification(tlpsof, tlpeof, tlpbe, pktformat, pkttype, portnum):\n    if tlpbe == '0000':\n        return 'trace'\n    if tlpsof == 0:\n        if portnum == 4:\n            return 'master continuation'\n        else:\n            return 'slave continuation'\n    if portnum == 4:\n        if pkttype == 10: # COMPLETION\n            return 'Master Response'\n        else:\n            if pktformat == 2 or pktformat == 3:\n                return 'Slave Write Request'\n            else:\n                return 'Slave Request'\n    elif portnum == 8:\n        if pkttype == 10: # COMPLETION\n            return 'Slave Response'\n        else:\n            if pktformat == 2 or pktformat == 3:\n                return 'Master Write Request'\n            else:\n                return 'Master Request'\n    else:\n        return 'Misc'\n\nclassCounts = {}\nlast_seqno = mpz(-1)\n\ndef print_tlp(tlpdata, f=None):\n    global last_seqno\n    def segment(i):\n        return tlpdata[i*8:i*8+8]\n    def byteswap(w):\n        def byte(i):\n            return w[i*2:i*2+2]\n        return ''.join(map(byte, [3,2,1,0]))\n\n    words = map(segment, [0,1,2,3,4,5])\n\n    seqno = mpz(tlpdata[-48:-40],16)\n    if last_seqno >= 0:\n        delta = seqno - last_seqno\n    else:\n        delta = 0\n    tlpsof = int(tlpdata[-39:-38],16) & 1\n    tlpeof = int(tlpdata[-38:-36],16) >> 7\n    tlpbe  = tlpdata[-36:-32]\n    tlphit = int(tlpdata[-38:-36],16) & 0x7f\n    pktformat = (int(tlpdata[-32:-31],16) >> 1) & 3\n    pkttype = (int(tlpdata[-32:-30],16) & 0x1f)\n\n    portnum = int(tlpdata[-40:-38],16) >> 1\n    pktclass = pktClassification(tlpsof, tlpeof, tlpbe, pktformat, pkttype, portnum)\n    if pktclass in classCounts:\n       classCounts[pktclass] += 1\n    else:\n       classCounts[pktclass] = 1\n\n    if f:\n        emit_vcd_entry(f, seqno, pktclass)\n\n    print(tlpdata)\n    print('timestamp:', seqno)\n    print('    delta:', delta)\n    last_seqno = seqno\n    print('   ', pktclass)\n    print('    foo:', tlpdata[-40:-38], hex(int(tlpdata[-40:-38],16) >> 1))\n    print('    tlpbe:', tlpbe)\n    print('    tlphit:', tlphit)\n    print('    tlpeof:', tlpeof)\n    print('    tlpsof:', tlpsof)\n    if tlpsof:\n        print('    format:', tlpdata[-32:-31], pktformat, TlpPacketFormat[pktformat])\n        print('   pkttype:', tlpdata[-32:-30], pkttype, TlpPacketType[pkttype])\n\n    if tlpsof == 0:\n        print('     data:', tlpdata[-32:])\n    elif TlpPacketFormat[pktformat] == 'MEM_WRITE_3DW_DATA' and TlpPacketType[pkttype] == 'COMPLETION':\n        print('      tag:', tlpdata[-12:-10])\n        print('    reqid:', tlpdata[-16:-12])\n        print('   cmplid:', tlpdata[-24:-20])\n        print('   status:', tlpdata[-20:-19])\n        print('  nosnoop:', tlpdata[-28:-27], int(tlpdata[-28:-27],16) >> 3)\n        print('bytecount:', tlpdata[-19:-16])\n        print('loweraddr:', tlpdata[-10:-8])\n        print('  length:', int(tlpdata[-27:-24],16) & 0x3ff)\n        print('    data:', tlpdata[-8:])\n    elif TlpPacketFormat[pktformat] == 'MEM_READ_3DW_NO_DATA' or TlpPacketFormat[pktformat] == 'MEM_WRITE_3DW_DATA':\n        print(' address:', tlpdata[-16:-8], (int(tlpdata[-16:-8],16) >> 2) % 8192)\n        print('  1st be:', tlpdata[-17:-16])\n        print(' last be:', tlpdata[-18:-17])\n        print('     tag:', tlpdata[-20:-18])\n        print('   reqid:', tlpdata[-24:-20])\n        print('  length:', int(tlpdata[-27:-24],16) & 0x3ff)\n        if TlpPacketFormat[pktformat] == 'MEM_WRITE_3DW_DATA':\n            print('    data:', tlpdata[-8:])\n    elif TlpPacketFormat[pktformat] == 'MEM_READ_4DW_NO_DATA' or TlpPacketFormat[pktformat] == 'MEM_WRITE_4DW_DATA':\n        print(' address:', tlpdata[-16:])\n        print('  1st be:', tlpdata[-17:-16])\n        print(' last be:', tlpdata[-18:-17])\n        print('     tag:', tlpdata[-20:-18])\n        print('   reqid:', tlpdata[-24:-20])\n        print('  length:', int(tlpdata[-27:-24],16) & 0x3ff)\n    else:\n        print('  tlp data:', tlpdata[-8:])\n        print('lower addr:', tlpdata[-10:-8])\n        print('       tag:', tlpdata[-12:-10])\n        print('     reqid:', tlpdata[-14:-12])\n        print(' bytecount:', '0x' + tlpdata[-15:-14])\n        print('       bcm:', int(tlpdata[-16:-15], 16) & 1)\n        print('   cstatus:', (int(tlpdata[-16:-15], 16) >> 1) & 7)\n        print('    cmplid:', tlpdata[-18:-16])\n        print('    cmplen:', tlpdata[-21:-18])\n        print('   nosnoop:', int(tlpdata[-22:-21],16) & 1)\n        print('   relaxed:', int(tlpdata[-22:-21],16) & 2)\n        print('   poison:', int(tlpdata[-22:-21],16) & 4)\n        print('   digest:', int(tlpdata[-22:-21],16) & 8)\n        print('     zero:', tlpdata[-23:-22])\n        print('   tclass:', tlpdata[-24:-23])\n        print('  pkttype:', int(tlpdata[-26:-24],16) & 0x1f, TlpPacketType[int(tlpdata[-26:-24],16) & 0x1f])\n        print('  format:', (int(tlpdata[-26:-24],16) >> 1) & 3, TlpPacketFormat[(int(tlpdata[-26:-24],16) >> 1) & 3])\n    print()\n\ndef print_tlp_log(tlplog, f=None):\n    if f:\n        emit_vcd_header(f)\n    for tlpdata in tlplog:\n        if tlpdata == '000000000000000000000000000000000000000000000000':\n            continue\n        m = re.match('^([0-9A-Fa-f]+)$', tlpdata)\n        if m:\n            print_tlp(tlpdata, f)\n\nif __name__ == '__main__':\n    f = open('tlp.vcd', 'w')\n    if len(sys.argv) > 1 and sys.argv[1] == 'openocd':\n        os.chdir('/scratch/jamey/connectal/jtag')\n        tlplog = subprocess.check_output(['openocd', '-f', 'pcietrace.cfg'], stderr=subprocess.STDOUT).split('\\n')\n    elif len(sys.argv) > 1:\n        tlplog = open(sys.argv[1]).read().split('\\n')\n    else:\n        tlplog = subprocess.check_output(['connectalutil', 'tlp', '/dev/portal0']).split('\\n')\n    print_tlp_log(tlplog[0:-1], f)\n    print(classCounts)\n    print(sum([ classCounts[k] for k in classCounts]))\n"
  },
  {
    "path": "scripts/AST.py",
    "content": "# Copyright (c) 2014 Quanta Research Cambridge, Inc\n#\n# Permission is hereby granted, free of charge, to any person obtaining a\n# copy of this software and associated documentation files (the \"Software\"),\n# to deal in the Software without restriction, including without limitation\n# the rights to use, copy, modify, merge, publish, distribute, sublicense,\n# and/or sell copies of the Software, and to permit persons to whom the\n# Software is furnished to do so, subject to the following conditions:\n#\n# The above copyright notice and this permission notice shall be included\n# in all copies or substantial portions of the Software.\n#\n# THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n# OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n# DEALINGS IN THE SOFTWARE.\n#\n\nfrom __future__ import print_function\n\nimport math\nimport re\nimport functools\nimport json\nimport os\nimport sys\nimport traceback\n\nimport AST\nimport globalv\nimport util\n\nverbose = False\ntempFilename = 'generatedDesignInterfaceFile.json'\nlookupTable = {}\n\nclass InterfaceMixin:\n    def getSubinterface(self, name):\n        subinterfaceName = name\n        if not subinterfaceName in globalv.globalvars:\n            return None\n        subinterface = globalv.globalvars[subinterfaceName]\n        #print('subinterface', subinterface, subinterface)\n        return subinterface\n    def parentClass(self, default):\n        rv = default if (len(self.typeClassInstances)==0) else (self.typeClassInstances[0])\n        return rv\n\ndef dtInfo(arg):\n    rc = {}\n    if hasattr(arg, 'name'):\n        rc['name'] = arg.name\n        if lookupTable.get(arg.name):\n            rc['name'] = lookupTable[arg.name]\n    if hasattr(arg, 'type') and arg.type != 'Type':\n        rc['type'] = arg.type\n        if lookupTable.get(arg.type):\n            rc['type'] = lookupTable[arg.type]\n    if hasattr(arg, 'params'):\n        if arg.params is not None and arg.params != []:\n            rc['params'] = [dtInfo(p) for p in arg.params]\n    if hasattr(arg, 'elements'):\n        if arg.type == 'Enum':\n            rc['elements'] = arg.elements\n        else:\n            rc['elements'] = [piInfo(p) for p in arg.elements]\n    return rc\n\ndef piInfo(pitem):\n    rc = {}\n    rc['pname'] = pitem.name\n    rc['ptype'] = dtInfo(pitem.type)\n    if hasattr(pitem, 'oldtype'):\n        rc['oldtype'] = dtInfo(pitem.oldtype)\n    return rc\n\ndef declInfo(mitem):\n    rc = {}\n    rc['dname'] = mitem.name\n    rc['dparams'] = []\n    for pitem in mitem.params:\n        rc['dparams'].append(piInfo(pitem))\n    return rc\n\ndef classInfo(item):\n    rc = {\n        'Package': os.path.splitext(os.path.basename(item.package))[0],\n        'cname': item.name,\n        'cdecls': [],\n    }\n    for mitem in item.decls:\n        rc['cdecls'].append(declInfo(mitem))\n    return rc\n\ndef serialize_json(interfaces, globalimports, bsvdefines):\n    global verbose\n    itemlist = []\n    for item in interfaces:\n        itemlist.append(classInfo(item))\n    jfile = open(tempFilename, 'w')\n    toplevel = {}\n    toplevel['interfaces'] = itemlist\n    gdlist = []\n    for item in globalv.globaldecls:\n        if item.type == 'TypeDef':\n            newitem = {'dtype': item.type}\n            newitem['tname'] = item.name\n            newitem['tdtype'] = dtInfo(item.tdtype)\n            if item.params:\n                 newitem['tparams'] = item.params\n            if verbose:\n                print('TYPEDEF globaldecl:', item, newitem)\n            gdlist.append(newitem)\n        elif verbose:\n            print('Unprocessed globaldecl:', item)\n    toplevel['globaldecls'] = gdlist\n    toplevel['globalimports'] = globalimports\n    toplevel['bsvdefines'] = bsvdefines\n    if True:\n        try:\n            json.dump(toplevel, jfile, sort_keys = True, indent = 4)\n            jfile.close()\n            j2file = open(tempFilename).read()\n            toplevelnew = json.loads(j2file)\n        except:\n            print('Unable to encode json file', tempFilename)\n            #print('WWWW', toplevel)\n            sys.exit(-1)\n    return toplevel\n\nclass Method:\n    def __init__(self, name, return_type, params):\n        self.type = 'Method'\n        self.name = name\n        self.return_type = return_type\n        self.params = params\n    def __repr__(self):\n        sparams = [p.__repr__() for p in self.params]\n        return '<method: %s %s %s>' % (self.name, self.return_type, sparams)\n    def instantiate(self, paramBindings):\n        #print('instantiate method', self.name, self.params)\n        return Method(self.name,\n                      self.return_type.instantiate(paramBindings),\n                      [ p.instantiate(paramBindings) for p in self.params])\n\nclass Function:\n    def __init__(self, name, return_type, params):\n        self.type = 'Function'\n        self.name = name\n        self.return_type = return_type\n        self.params = params\n    def __repr__(self):\n        if not self.params:\n            return '<function: %s %s NONE>' % (self.name, self.return_type)\n        sparams = list(map(str, self.params))\n        return '<function: %s %s %s>' % (self.name, self.return_type, sparams)\n\nclass Variable:\n    def __init__(self, name, t, value):\n        self.type = 'Variable'\n        self.name = name\n        self.type = t\n        self.value = value\n        if t and t.type == 'Type' and t.name == 'Integer' and value and value.type == 'Type':\n            lookupTable[name] = value.name\n    def __repr__(self):\n        return '<variable: %s : %s>' % (self.name, self.type)\n\nclass Interface(InterfaceMixin):\n    def __init__(self, name, params, decls, subinterfacename, packagename):\n        self.type = 'Interface'\n        self.name = name\n        self.params = params\n        self.decls = decls\n        self.subinterfacename = subinterfacename\n        self.typeClassInstances = []\n        self.package = packagename\n    def interfaceType(self):\n        return Type(self.name,self.params)\n    def __repr__(self):\n        return '{interface: %s (%s) : %s}' % (self.name, self.params, self.typeClassInstances)\n    def instantiate(self, paramBindings):\n        newInterface = Interface(self.name, [],\n                                 [d.instantiate(paramBindings) for d in self.decls],\n                                 self.subinterfacename,\n                                 self.package)\n        newInterface.typeClassInstances = self.typeClassInstances\n        return newInterface\n\nclass Typeclass:\n    def __init__(self, name):\n        self.name = name\n        self.type = 'TypeClass'\n    def __repr__(self):\n        return '{typeclass %s}' % (self.name)\n\nclass TypeclassInstance:\n    def __init__(self, name, params, provisos, decl):\n        self.name = name\n        self.params = params\n        self.provisos = provisos\n        self.decl = decl\n        self.type = 'TypeclassInstance'\n    def __repr__(self):\n        return '{typeclassinstance %s %s}' % (self.name, self.params)\n\nclass Module:\n    def __init__(self, moduleContext, name, params, interface, provisos, decls):\n        self.type = 'Module'\n        self.name = name\n        self.moduleContext = moduleContext\n        self.interface = interface\n        self.params = params\n        self.provisos = provisos\n        self.decls = decls\n    def __repr__(self):\n        return '{module: %s %s}' % (self.name, self.decls)\n\nclass EnumElement:\n    def __init__(self, name, qualifiers, value):\n        self.qualifiers = qualifiers\n        self.value = value\n    def __repr__(self):\n        return '{enumelt: %s}' % (self.name)\n\nclass Enum:\n    def __init__(self, elements):\n        self.type = 'Enum'\n        self.elements = elements\n    def __repr__(self):\n        return '{enum: %s}' % (self.elements)\n    def instantiate(self, paramBindings):\n        return self\n\nclass StructMember:\n    def __init__(self, t, name):\n        self.type = t\n        self.name = name\n    def __repr__(self):\n        return '{field: %s %s}' % (self.type, self.name)\n    def instantiate(self, paramBindings):\n        return StructMember(self.type.instantiate(paramBindings), self.name)\n\nclass Struct:\n    def __init__(self, elements):\n        self.type = 'Struct'\n        self.elements = elements\n    def __repr__(self):\n        return '{struct: %s}' % (self.elements)\n    def instantiate(self, paramBindings):\n        return Struct([e.instantiate(paramBindings) for e in self.elements])\n\nclass TypeDef:\n    def __init__(self, tdtype, name, params):\n        self.name = name\n        self.params = params\n        self.type = 'TypeDef'\n        self.tdtype = tdtype\n        if tdtype and tdtype.type != 'Type':\n            tdtype.name = name\n        self.type = 'TypeDef'\n    def __repr__(self):\n        return '{typedef: %s %s}' % (self.tdtype, self.name)\n\nclass Param:\n    def __init__(self, name, t):\n        self.name = name\n        self.type = t\n    def __repr__(self):\n        return '{param %s: %s}' % (self.name, self.type)\n    def instantiate(self, paramBindings):\n        return Param(self.name,\n                     self.type.instantiate(paramBindings))\n\nclass Type:\n    def __init__(self, name, params):\n        self.type = 'Type'\n        self.name = name\n        if params:\n            self.params = params\n        else:\n            self.params = []\n    def __repr__(self):\n        sparams = list(map(str, self.params))\n        return '{type: %s %s}' % (self.name, sparams)\n    def instantiate(self, paramBindings):\n        #print('Type.instantiate', self.name, paramBindings)\n        if self.name in paramBindings:\n            return paramBindings[self.name]\n        else:\n            return Type(self.name, [p.instantiate(paramBindings) for p in self.params])\n"
  },
  {
    "path": "scripts/Doxyfile",
    "content": "# Doxyfile 1.7.6.1\n\n# This file describes the settings to be used by the documentation system\n# doxygen (www.doxygen.org) for a project.\n#\n# All text after a hash (#) is considered a comment and will be ignored.\n# The format is:\n#       TAG = value [value, ...]\n# For lists items can also be appended using:\n#       TAG += value [value, ...]\n# Values that contain spaces should be placed between quotes (\" \").\n\n#---------------------------------------------------------------------------\n# Project related configuration options\n#---------------------------------------------------------------------------\n\n# This tag specifies the encoding used for all characters in the config file\n# that follow. The default is UTF-8 which is also the encoding used for all\n# text before the first occurrence of this tag. Doxygen uses libiconv (or the\n# iconv built into libc) for the transcoding. See\n# http://www.gnu.org/software/libiconv for the list of possible encodings.\n\nDOXYFILE_ENCODING      = UTF-8\n\n# The PROJECT_NAME tag is a single word (or sequence of words) that should\n# identify the project. Note that if you do not use Doxywizard you need\n# to put quotes around the project name if it contains spaces.\n\nPROJECT_NAME           = \"CONNECTAL\"\n\n# The PROJECT_NUMBER tag can be used to enter a project or revision number.\n# This could be handy for archiving the generated documentation or\n# if some version control system is used.\n\nPROJECT_NUMBER         =\n\n# Using the PROJECT_BRIEF tag one can provide an optional one line description\n# for a project that appears at the top of each page and should give viewer\n# a quick idea about the purpose of the project. Keep the description short.\n\nPROJECT_BRIEF          =\n\n# With the PROJECT_LOGO tag one can specify an logo or icon that is\n# included in the documentation. The maximum height of the logo should not\n# exceed 55 pixels and the maximum width should not exceed 200 pixels.\n# Doxygen will copy the logo to the output directory.\n\nPROJECT_LOGO           =\n\n# The OUTPUT_DIRECTORY tag is used to specify the (relative or absolute)\n# base path where the generated documentation will be put.\n# If a relative path is entered, it will be relative to the location\n# where doxygen was started. If left blank the current directory will be used.\n\nOUTPUT_DIRECTORY       = doxygen\n\n# If the CREATE_SUBDIRS tag is set to YES, then doxygen will create\n# 4096 sub-directories (in 2 levels) under the output directory of each output\n# format and will distribute the generated files over these directories.\n# Enabling this option can be useful when feeding doxygen a huge amount of\n# source files, where putting all generated files in the same directory would\n# otherwise cause performance problems for the file system.\n\nCREATE_SUBDIRS         = YES\n\n# The OUTPUT_LANGUAGE tag is used to specify the language in which all\n# documentation generated by doxygen is written. Doxygen will use this\n# information to generate all constant output in the proper language.\n# The default language is English, other supported languages are:\n# Afrikaans, Arabic, Brazilian, Catalan, Chinese, Chinese-Traditional,\n# Croatian, Czech, Danish, Dutch, Esperanto, Farsi, Finnish, French, German,\n# Greek, Hungarian, Italian, Japanese, Japanese-en (Japanese with English\n# messages), Korean, Korean-en, Lithuanian, Norwegian, Macedonian, Persian,\n# Polish, Portuguese, Romanian, Russian, Serbian, Serbian-Cyrillic, Slovak,\n# Slovene, Spanish, Swedish, Ukrainian, and Vietnamese.\n\nOUTPUT_LANGUAGE        = English\n\n# If the BRIEF_MEMBER_DESC tag is set to YES (the default) Doxygen will\n# include brief member descriptions after the members that are listed in\n# the file and class documentation (similar to JavaDoc).\n# Set to NO to disable this.\n\nBRIEF_MEMBER_DESC      = YES\n\n# If the REPEAT_BRIEF tag is set to YES (the default) Doxygen will prepend\n# the brief description of a member or function before the detailed description.\n# Note: if both HIDE_UNDOC_MEMBERS and BRIEF_MEMBER_DESC are set to NO, the\n# brief descriptions will be completely suppressed.\n\nREPEAT_BRIEF           = YES\n\n# This tag implements a quasi-intelligent brief description abbreviator\n# that is used to form the text in various listings. Each string\n# in this list, if found as the leading text of the brief description, will be\n# stripped from the text and the result after processing the whole list, is\n# used as the annotated text. Otherwise, the brief description is used as-is.\n# If left blank, the following values are used (\"$name\" is automatically\n# replaced with the name of the entity): \"The $name class\" \"The $name widget\"\n# \"The $name file\" \"is\" \"provides\" \"specifies\" \"contains\"\n# \"represents\" \"a\" \"an\" \"the\"\n\nABBREVIATE_BRIEF       =\n\n# If the ALWAYS_DETAILED_SEC and REPEAT_BRIEF tags are both set to YES then\n# Doxygen will generate a detailed section even if there is only a brief\n# description.\n\nALWAYS_DETAILED_SEC    = NO\n\n# If the INLINE_INHERITED_MEMB tag is set to YES, doxygen will show all\n# inherited members of a class in the documentation of that class as if those\n# members were ordinary class members. Constructors, destructors and assignment\n# operators of the base classes will not be shown.\n\nINLINE_INHERITED_MEMB  = NO\n\n# If the FULL_PATH_NAMES tag is set to YES then Doxygen will prepend the full\n# path before files name in the file list and in the header files. If set\n# to NO the shortest path that makes the file name unique will be used.\n\nFULL_PATH_NAMES        = YES\n\n# If the FULL_PATH_NAMES tag is set to YES then the STRIP_FROM_PATH tag\n# can be used to strip a user-defined part of the path. Stripping is\n# only done if one of the specified strings matches the left-hand part of\n# the path. The tag can be used to show relative paths in the file list.\n# If left blank the directory from which doxygen is run is used as the\n# path to strip.\n\nSTRIP_FROM_PATH        =\n\n# The STRIP_FROM_INC_PATH tag can be used to strip a user-defined part of\n# the path mentioned in the documentation of a class, which tells\n# the reader which header file to include in order to use a class.\n# If left blank only the name of the header file containing the class\n# definition is used. Otherwise one should specify the include paths that\n# are normally passed to the compiler using the -I flag.\n\nSTRIP_FROM_INC_PATH    =\n\n# If the SHORT_NAMES tag is set to YES, doxygen will generate much shorter\n# (but less readable) file names. This can be useful if your file system\n# doesn't support long names like on DOS, Mac, or CD-ROM.\n\nSHORT_NAMES            = NO\n\n# If the JAVADOC_AUTOBRIEF tag is set to YES then Doxygen\n# will interpret the first line (until the first dot) of a JavaDoc-style\n# comment as the brief description. If set to NO, the JavaDoc\n# comments will behave just like regular Qt-style comments\n# (thus requiring an explicit @brief command for a brief description.)\n\nJAVADOC_AUTOBRIEF      = NO\n\n# If the QT_AUTOBRIEF tag is set to YES then Doxygen will\n# interpret the first line (until the first dot) of a Qt-style\n# comment as the brief description. If set to NO, the comments\n# will behave just like regular Qt-style comments (thus requiring\n# an explicit \\brief command for a brief description.)\n\nQT_AUTOBRIEF           = NO\n\n# The MULTILINE_CPP_IS_BRIEF tag can be set to YES to make Doxygen\n# treat a multi-line C++ special comment block (i.e. a block of //! or ///\n# comments) as a brief description. This used to be the default behaviour.\n# The new default is to treat a multi-line C++ comment block as a detailed\n# description. Set this tag to YES if you prefer the old behaviour instead.\n\nMULTILINE_CPP_IS_BRIEF = NO\n\n# If the INHERIT_DOCS tag is set to YES (the default) then an undocumented\n# member inherits the documentation from any documented member that it\n# re-implements.\n\nINHERIT_DOCS           = YES\n\n# If the SEPARATE_MEMBER_PAGES tag is set to YES, then doxygen will produce\n# a new page for each member. If set to NO, the documentation of a member will\n# be part of the file/class/namespace that contains it.\n\nSEPARATE_MEMBER_PAGES  = NO\n\n# The TAB_SIZE tag can be used to set the number of spaces in a tab.\n# Doxygen uses this value to replace tabs by spaces in code fragments.\n\nTAB_SIZE               = 8\n\n# This tag can be used to specify a number of aliases that acts\n# as commands in the documentation. An alias has the form \"name=value\".\n# For example adding \"sideeffect=\\par Side Effects:\\n\" will allow you to\n# put the command \\sideeffect (or @sideeffect) in the documentation, which\n# will result in a user-defined paragraph with heading \"Side Effects:\".\n# You can put \\n's in the value part of an alias to insert newlines.\n\nALIASES                =\n\n# This tag can be used to specify a number of word-keyword mappings (TCL only).\n# A mapping has the form \"name=value\". For example adding\n# \"class=itcl::class\" will allow you to use the command class in the\n# itcl::class meaning.\n\nTCL_SUBST              =\n\n# Set the OPTIMIZE_OUTPUT_FOR_C tag to YES if your project consists of C\n# sources only. Doxygen will then generate output that is more tailored for C.\n# For instance, some of the names that are used will be different. The list\n# of all members will be omitted, etc.\n\nOPTIMIZE_OUTPUT_FOR_C  = NO\n\n# Set the OPTIMIZE_OUTPUT_JAVA tag to YES if your project consists of Java\n# sources only. Doxygen will then generate output that is more tailored for\n# Java. For instance, namespaces will be presented as packages, qualified\n# scopes will look different, etc.\n\nOPTIMIZE_OUTPUT_JAVA   = NO\n\n# Set the OPTIMIZE_FOR_FORTRAN tag to YES if your project consists of Fortran\n# sources only. Doxygen will then generate output that is more tailored for\n# Fortran.\n\nOPTIMIZE_FOR_FORTRAN   = NO\n\n# Set the OPTIMIZE_OUTPUT_VHDL tag to YES if your project consists of VHDL\n# sources. Doxygen will then generate output that is tailored for\n# VHDL.\n\nOPTIMIZE_OUTPUT_VHDL   = NO\n\n# Doxygen selects the parser to use depending on the extension of the files it\n# parses. With this tag you can assign which parser to use for a given extension.\n# Doxygen has a built-in mapping, but you can override or extend it using this\n# tag. The format is ext=language, where ext is a file extension, and language\n# is one of the parsers supported by doxygen: IDL, Java, Javascript, CSharp, C,\n# C++, D, PHP, Objective-C, Python, Fortran, VHDL, C, C++. For instance to make\n# doxygen treat .inc files as Fortran files (default is PHP), and .f files as C\n# (default is Fortran), use: inc=Fortran f=C. Note that for custom extensions\n# you also need to set FILE_PATTERNS otherwise the files are not read by doxygen.\n\nEXTENSION_MAPPING      =\n\n# If you use STL classes (i.e. std::string, std::vector, etc.) but do not want\n# to include (a tag file for) the STL sources as input, then you should\n# set this tag to YES in order to let doxygen match functions declarations and\n# definitions whose arguments contain STL classes (e.g. func(std::string); v.s.\n# func(std::string) {}). This also makes the inheritance and collaboration\n# diagrams that involve STL classes more complete and accurate.\n\nBUILTIN_STL_SUPPORT    = NO\n\n# If you use Microsoft's C++/CLI language, you should set this option to YES to\n# enable parsing support.\n\nCPP_CLI_SUPPORT        = NO\n\n# Set the SIP_SUPPORT tag to YES if your project consists of sip sources only.\n# Doxygen will parse them like normal C++ but will assume all classes use public\n# instead of private inheritance when no explicit protection keyword is present.\n\nSIP_SUPPORT            = NO\n\n# For Microsoft's IDL there are propget and propput attributes to indicate getter\n# and setter methods for a property. Setting this option to YES (the default)\n# will make doxygen replace the get and set methods by a property in the\n# documentation. This will only work if the methods are indeed getting or\n# setting a simple type. If this is not the case, or you want to show the\n# methods anyway, you should set this option to NO.\n\nIDL_PROPERTY_SUPPORT   = YES\n\n# If member grouping is used in the documentation and the DISTRIBUTE_GROUP_DOC\n# tag is set to YES, then doxygen will reuse the documentation of the first\n# member in the group (if any) for the other members of the group. By default\n# all members of a group must be documented explicitly.\n\nDISTRIBUTE_GROUP_DOC   = NO\n\n# Set the SUBGROUPING tag to YES (the default) to allow class member groups of\n# the same type (for instance a group of public functions) to be put as a\n# subgroup of that type (e.g. under the Public Functions section). Set it to\n# NO to prevent subgrouping. Alternatively, this can be done per class using\n# the \\nosubgrouping command.\n\nSUBGROUPING            = YES\n\n# When the INLINE_GROUPED_CLASSES tag is set to YES, classes, structs and\n# unions are shown inside the group in which they are included (e.g. using\n# @ingroup) instead of on a separate page (for HTML and Man pages) or\n# section (for LaTeX and RTF).\n\nINLINE_GROUPED_CLASSES = NO\n\n# When the INLINE_SIMPLE_STRUCTS tag is set to YES, structs, classes, and\n# unions with only public data fields will be shown inline in the documentation\n# of the scope in which they are defined (i.e. file, namespace, or group\n# documentation), provided this scope is documented. If set to NO (the default),\n# structs, classes, and unions are shown on a separate page (for HTML and Man\n# pages) or section (for LaTeX and RTF).\n\nINLINE_SIMPLE_STRUCTS  = NO\n\n# When TYPEDEF_HIDES_STRUCT is enabled, a typedef of a struct, union, or enum\n# is documented as struct, union, or enum with the name of the typedef. So\n# typedef struct TypeS {} TypeT, will appear in the documentation as a struct\n# with name TypeT. When disabled the typedef will appear as a member of a file,\n# namespace, or class. And the struct will be named TypeS. This can typically\n# be useful for C code in case the coding convention dictates that all compound\n# types are typedef'ed and only the typedef is referenced, never the tag name.\n\nTYPEDEF_HIDES_STRUCT   = NO\n\n# The SYMBOL_CACHE_SIZE determines the size of the internal cache use to\n# determine which symbols to keep in memory and which to flush to disk.\n# When the cache is full, less often used symbols will be written to disk.\n# For small to medium size projects (<1000 input files) the default value is\n# probably good enough. For larger projects a too small cache size can cause\n# doxygen to be busy swapping symbols to and from disk most of the time\n# causing a significant performance penalty.\n# If the system has enough physical memory increasing the cache will improve the\n# performance by keeping more symbols in memory. Note that the value works on\n# a logarithmic scale so increasing the size by one will roughly double the\n# memory usage. The cache size is given by this formula:\n# 2^(16+SYMBOL_CACHE_SIZE). The valid range is 0..9, the default is 0,\n# corresponding to a cache size of 2^16 = 65536 symbols.\n\nSYMBOL_CACHE_SIZE      = 0\n\n# Similar to the SYMBOL_CACHE_SIZE the size of the symbol lookup cache can be\n# set using LOOKUP_CACHE_SIZE. This cache is used to resolve symbols given\n# their name and scope. Since this can be an expensive process and often the\n# same symbol appear multiple times in the code, doxygen keeps a cache of\n# pre-resolved symbols. If the cache is too small doxygen will become slower.\n# If the cache is too large, memory is wasted. The cache size is given by this\n# formula: 2^(16+LOOKUP_CACHE_SIZE). The valid range is 0..9, the default is 0,\n# corresponding to a cache size of 2^16 = 65536 symbols.\n\nLOOKUP_CACHE_SIZE      = 0\n\n#---------------------------------------------------------------------------\n# Build related configuration options\n#---------------------------------------------------------------------------\n\n# If the EXTRACT_ALL tag is set to YES doxygen will assume all entities in\n# documentation are documented, even if no documentation was available.\n# Private class members and static file members will be hidden unless\n# the EXTRACT_PRIVATE and EXTRACT_STATIC tags are set to YES\n\nEXTRACT_ALL            = YES\n\n# If the EXTRACT_PRIVATE tag is set to YES all private members of a class\n# will be included in the documentation.\n\nEXTRACT_PRIVATE        = NO\n\n# If the EXTRACT_STATIC tag is set to YES all static members of a file\n# will be included in the documentation.\n\nEXTRACT_STATIC         = NO\n\n# If the EXTRACT_LOCAL_CLASSES tag is set to YES classes (and structs)\n# defined locally in source files will be included in the documentation.\n# If set to NO only classes defined in header files are included.\n\nEXTRACT_LOCAL_CLASSES  = YES\n\n# This flag is only useful for Objective-C code. When set to YES local\n# methods, which are defined in the implementation section but not in\n# the interface are included in the documentation.\n# If set to NO (the default) only methods in the interface are included.\n\nEXTRACT_LOCAL_METHODS  = NO\n\n# If this flag is set to YES, the members of anonymous namespaces will be\n# extracted and appear in the documentation as a namespace called\n# 'anonymous_namespace{file}', where file will be replaced with the base\n# name of the file that contains the anonymous namespace. By default\n# anonymous namespaces are hidden.\n\nEXTRACT_ANON_NSPACES   = NO\n\n# If the HIDE_UNDOC_MEMBERS tag is set to YES, Doxygen will hide all\n# undocumented members of documented classes, files or namespaces.\n# If set to NO (the default) these members will be included in the\n# various overviews, but no documentation section is generated.\n# This option has no effect if EXTRACT_ALL is enabled.\n\nHIDE_UNDOC_MEMBERS     = NO\n\n# If the HIDE_UNDOC_CLASSES tag is set to YES, Doxygen will hide all\n# undocumented classes that are normally visible in the class hierarchy.\n# If set to NO (the default) these classes will be included in the various\n# overviews. This option has no effect if EXTRACT_ALL is enabled.\n\nHIDE_UNDOC_CLASSES     = NO\n\n# If the HIDE_FRIEND_COMPOUNDS tag is set to YES, Doxygen will hide all\n# friend (class|struct|union) declarations.\n# If set to NO (the default) these declarations will be included in the\n# documentation.\n\nHIDE_FRIEND_COMPOUNDS  = NO\n\n# If the HIDE_IN_BODY_DOCS tag is set to YES, Doxygen will hide any\n# documentation blocks found inside the body of a function.\n# If set to NO (the default) these blocks will be appended to the\n# function's detailed documentation block.\n\nHIDE_IN_BODY_DOCS      = NO\n\n# The INTERNAL_DOCS tag determines if documentation\n# that is typed after a \\internal command is included. If the tag is set\n# to NO (the default) then the documentation will be excluded.\n# Set it to YES to include the internal documentation.\n\nINTERNAL_DOCS          = NO\n\n# If the CASE_SENSE_NAMES tag is set to NO then Doxygen will only generate\n# file names in lower-case letters. If set to YES upper-case letters are also\n# allowed. This is useful if you have classes or files whose names only differ\n# in case and if your file system supports case sensitive file names. Windows\n# and Mac users are advised to set this option to NO.\n\nCASE_SENSE_NAMES       = YES\n\n# If the HIDE_SCOPE_NAMES tag is set to NO (the default) then Doxygen\n# will show members with their full class and namespace scopes in the\n# documentation. If set to YES the scope will be hidden.\n\nHIDE_SCOPE_NAMES       = NO\n\n# If the SHOW_INCLUDE_FILES tag is set to YES (the default) then Doxygen\n# will put a list of the files that are included by a file in the documentation\n# of that file.\n\nSHOW_INCLUDE_FILES     = YES\n\n# If the FORCE_LOCAL_INCLUDES tag is set to YES then Doxygen\n# will list include files with double quotes in the documentation\n# rather than with sharp brackets.\n\nFORCE_LOCAL_INCLUDES   = NO\n\n# If the INLINE_INFO tag is set to YES (the default) then a tag [inline]\n# is inserted in the documentation for inline members.\n\nINLINE_INFO            = YES\n\n# If the SORT_MEMBER_DOCS tag is set to YES (the default) then doxygen\n# will sort the (detailed) documentation of file and class members\n# alphabetically by member name. If set to NO the members will appear in\n# declaration order.\n\nSORT_MEMBER_DOCS       = YES\n\n# If the SORT_BRIEF_DOCS tag is set to YES then doxygen will sort the\n# brief documentation of file, namespace and class members alphabetically\n# by member name. If set to NO (the default) the members will appear in\n# declaration order.\n\nSORT_BRIEF_DOCS        = NO\n\n# If the SORT_MEMBERS_CTORS_1ST tag is set to YES then doxygen\n# will sort the (brief and detailed) documentation of class members so that\n# constructors and destructors are listed first. If set to NO (the default)\n# the constructors will appear in the respective orders defined by\n# SORT_MEMBER_DOCS and SORT_BRIEF_DOCS.\n# This tag will be ignored for brief docs if SORT_BRIEF_DOCS is set to NO\n# and ignored for detailed docs if SORT_MEMBER_DOCS is set to NO.\n\nSORT_MEMBERS_CTORS_1ST = NO\n\n# If the SORT_GROUP_NAMES tag is set to YES then doxygen will sort the\n# hierarchy of group names into alphabetical order. If set to NO (the default)\n# the group names will appear in their defined order.\n\nSORT_GROUP_NAMES       = NO\n\n# If the SORT_BY_SCOPE_NAME tag is set to YES, the class list will be\n# sorted by fully-qualified names, including namespaces. If set to\n# NO (the default), the class list will be sorted only by class name,\n# not including the namespace part.\n# Note: This option is not very useful if HIDE_SCOPE_NAMES is set to YES.\n# Note: This option applies only to the class list, not to the\n# alphabetical list.\n\nSORT_BY_SCOPE_NAME     = NO\n\n# If the STRICT_PROTO_MATCHING option is enabled and doxygen fails to\n# do proper type resolution of all parameters of a function it will reject a\n# match between the prototype and the implementation of a member function even\n# if there is only one candidate or it is obvious which candidate to choose\n# by doing a simple string match. By disabling STRICT_PROTO_MATCHING doxygen\n# will still accept a match between prototype and implementation in such cases.\n\nSTRICT_PROTO_MATCHING  = NO\n\n# The GENERATE_TODOLIST tag can be used to enable (YES) or\n# disable (NO) the todo list. This list is created by putting \\todo\n# commands in the documentation.\n\nGENERATE_TODOLIST      = YES\n\n# The GENERATE_TESTLIST tag can be used to enable (YES) or\n# disable (NO) the test list. This list is created by putting \\test\n# commands in the documentation.\n\nGENERATE_TESTLIST      = YES\n\n# The GENERATE_BUGLIST tag can be used to enable (YES) or\n# disable (NO) the bug list. This list is created by putting \\bug\n# commands in the documentation.\n\nGENERATE_BUGLIST       = YES\n\n# The GENERATE_DEPRECATEDLIST tag can be used to enable (YES) or\n# disable (NO) the deprecated list. This list is created by putting\n# \\deprecated commands in the documentation.\n\nGENERATE_DEPRECATEDLIST= YES\n\n# The ENABLED_SECTIONS tag can be used to enable conditional\n# documentation sections, marked by \\if sectionname ... \\endif.\n\nENABLED_SECTIONS       =\n\n# The MAX_INITIALIZER_LINES tag determines the maximum number of lines\n# the initial value of a variable or macro consists of for it to appear in\n# the documentation. If the initializer consists of more lines than specified\n# here it will be hidden. Use a value of 0 to hide initializers completely.\n# The appearance of the initializer of individual variables and macros in the\n# documentation can be controlled using \\showinitializer or \\hideinitializer\n# command in the documentation regardless of this setting.\n\nMAX_INITIALIZER_LINES  = 30\n\n# Set the SHOW_USED_FILES tag to NO to disable the list of files generated\n# at the bottom of the documentation of classes and structs. If set to YES the\n# list will mention the files that were used to generate the documentation.\n\nSHOW_USED_FILES        = YES\n\n# If the sources in your project are distributed over multiple directories\n# then setting the SHOW_DIRECTORIES tag to YES will show the directory hierarchy\n# in the documentation. The default is NO.\n\nSHOW_DIRECTORIES       = NO\n\n# Set the SHOW_FILES tag to NO to disable the generation of the Files page.\n# This will remove the Files entry from the Quick Index and from the\n# Folder Tree View (if specified). The default is YES.\n\nSHOW_FILES             = YES\n\n# Set the SHOW_NAMESPACES tag to NO to disable the generation of the\n# Namespaces page.\n# This will remove the Namespaces entry from the Quick Index\n# and from the Folder Tree View (if specified). The default is YES.\n\nSHOW_NAMESPACES        = YES\n\n# The FILE_VERSION_FILTER tag can be used to specify a program or script that\n# doxygen should invoke to get the current version for each file (typically from\n# the version control system). Doxygen will invoke the program by executing (via\n# popen()) the command <command> <input-file>, where <command> is the value of\n# the FILE_VERSION_FILTER tag, and <input-file> is the name of an input file\n# provided by doxygen. Whatever the program writes to standard output\n# is used as the file version. See the manual for examples.\n\nFILE_VERSION_FILTER    = \n\n# The LAYOUT_FILE tag can be used to specify a layout file which will be parsed\n# by doxygen. The layout file controls the global structure of the generated\n# output files in an output format independent way. The create the layout file\n# that represents doxygen's defaults, run doxygen with the -l option.\n# You can optionally specify a file name after the option, if omitted\n# DoxygenLayout.xml will be used as the name of the layout file.\n\nLAYOUT_FILE            =\n\n# The CITE_BIB_FILES tag can be used to specify one or more bib files\n# containing the references data. This must be a list of .bib files. The\n# .bib extension is automatically appended if omitted. Using this command\n# requires the bibtex tool to be installed. See also\n# http://en.wikipedia.org/wiki/BibTeX for more info. For LaTeX the style\n# of the bibliography can be controlled using LATEX_BIB_STYLE. To use this\n# feature you need bibtex and perl available in the search path.\n\nCITE_BIB_FILES         =\n\n#---------------------------------------------------------------------------\n# configuration options related to warning and progress messages\n#---------------------------------------------------------------------------\n\n# The QUIET tag can be used to turn on/off the messages that are generated\n# by doxygen. Possible values are YES and NO. If left blank NO is used.\n\nQUIET                  = NO\n\n# The WARNINGS tag can be used to turn on/off the warning messages that are\n# generated by doxygen. Possible values are YES and NO. If left blank\n# NO is used.\n\nWARNINGS               = YES\n\n# If WARN_IF_UNDOCUMENTED is set to YES, then doxygen will generate warnings\n# for undocumented members. If EXTRACT_ALL is set to YES then this flag will\n# automatically be disabled.\n\nWARN_IF_UNDOCUMENTED   = YES\n\n# If WARN_IF_DOC_ERROR is set to YES, doxygen will generate warnings for\n# potential errors in the documentation, such as not documenting some\n# parameters in a documented function, or documenting parameters that\n# don't exist or using markup commands wrongly.\n\nWARN_IF_DOC_ERROR      = YES\n\n# The WARN_NO_PARAMDOC option can be enabled to get warnings for\n# functions that are documented, but have no documentation for their parameters\n# or return value. If set to NO (the default) doxygen will only warn about\n# wrong or incomplete parameter documentation, but not about the absence of\n# documentation.\n\nWARN_NO_PARAMDOC       = NO\n\n# The WARN_FORMAT tag determines the format of the warning messages that\n# doxygen can produce. The string should contain the $file, $line, and $text\n# tags, which will be replaced by the file and line number from which the\n# warning originated and the warning text. Optionally the format may contain\n# $version, which will be replaced by the version of the file (if it could\n# be obtained via FILE_VERSION_FILTER)\n\nWARN_FORMAT            = \"$file:$line: $text\"\n\n# The WARN_LOGFILE tag can be used to specify a file to which warning\n# and error messages should be written. If left blank the output is written\n# to stderr.\n\nWARN_LOGFILE           =\n\n#---------------------------------------------------------------------------\n# configuration options related to the input files\n#---------------------------------------------------------------------------\n\n# The INPUT tag can be used to specify the files and/or directories that contain\n# documented source files. You may enter file names like \"myfile.cpp\" or\n# directories like \"/usr/src/myproject\". Separate the files or directories\n# with spaces.\n\nINPUT                  = bsv\n\n# This tag can be used to specify the character encoding of the source files\n# that doxygen parses. Internally doxygen uses the UTF-8 encoding, which is\n# also the default input encoding. Doxygen uses libiconv (or the iconv built\n# into libc) for the transcoding. See http://www.gnu.org/software/libiconv for\n# the list of possible encodings.\n\nINPUT_ENCODING         = UTF-8\n\n# If the value of the INPUT tag contains directories, you can use the\n# FILE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp\n# and *.h) to filter out the source-files in the directories. If left\n# blank the following patterns are tested:\n# *.c *.cc *.cxx *.cpp *.c++ *.d *.java *.ii *.ixx *.ipp *.i++ *.inl *.h *.hh\n# *.hxx *.hpp *.h++ *.idl *.odl *.cs *.php *.php3 *.inc *.m *.mm *.dox *.py\n# *.f90 *.f *.for *.vhd *.vhdl\n\nFILE_PATTERNS          = *.bsv\n\n# The RECURSIVE tag can be used to turn specify whether or not subdirectories\n# should be searched for input files as well. Possible values are YES and NO.\n# If left blank NO is used.\n\nRECURSIVE              = NO\n\n# The EXCLUDE tag can be used to specify files and/or directories that should be\n# excluded from the INPUT source files. This way you can easily exclude a\n# subdirectory from a directory tree whose root is specified with the INPUT tag.\n# Note that relative paths are relative to the directory from which doxygen is\n# run.\n\nEXCLUDE                =\n\n# The EXCLUDE_SYMLINKS tag can be used to select whether or not files or\n# directories that are symbolic links (a Unix file system feature) are excluded\n# from the input.\n\nEXCLUDE_SYMLINKS       = NO\n\n# If the value of the INPUT tag contains directories, you can use the\n# EXCLUDE_PATTERNS tag to specify one or more wildcard patterns to exclude\n# certain files from those directories. Note that the wildcards are matched\n# against the file with absolute path, so to exclude all test directories\n# for example use the pattern */test/*\n\nEXCLUDE_PATTERNS       =\n\n# The EXCLUDE_SYMBOLS tag can be used to specify one or more symbol names\n# (namespaces, classes, functions, etc.) that should be excluded from the\n# output. The symbol name can be a fully qualified name, a word, or if the\n# wildcard * is used, a substring. Examples: ANamespace, AClass,\n# AClass::ANamespace, ANamespace::*Test\n\nEXCLUDE_SYMBOLS        =\n\n# The EXAMPLE_PATH tag can be used to specify one or more files or\n# directories that contain example code fragments that are included (see\n# the \\include command).\n\nEXAMPLE_PATH           =\n\n# If the value of the EXAMPLE_PATH tag contains directories, you can use the\n# EXAMPLE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp\n# and *.h) to filter out the source-files in the directories. If left\n# blank all files are included.\n\nEXAMPLE_PATTERNS       =\n\n# If the EXAMPLE_RECURSIVE tag is set to YES then subdirectories will be\n# searched for input files to be used with the \\include or \\dontinclude\n# commands irrespective of the value of the RECURSIVE tag.\n# Possible values are YES and NO. If left blank NO is used.\n\nEXAMPLE_RECURSIVE      = NO\n\n# The IMAGE_PATH tag can be used to specify one or more files or\n# directories that contain image that are included in the documentation (see\n# the \\image command).\n\nIMAGE_PATH             =\n\n# The INPUT_FILTER tag can be used to specify a program that doxygen should\n# invoke to filter for each input file. Doxygen will invoke the filter program\n# by executing (via popen()) the command <filter> <input-file>, where <filter>\n# is the value of the INPUT_FILTER tag, and <input-file> is the name of an\n# input file. Doxygen will then use the output that the filter program writes\n# to standard output.\n# If FILTER_PATTERNS is specified, this tag will be\n# ignored.\n\nINPUT_FILTER           = scripts/bsv.filter\n\n# The FILTER_PATTERNS tag can be used to specify filters on a per file pattern\n# basis.\n# Doxygen will compare the file name with each pattern and apply the\n# filter if there is a match.\n# The filters are a list of the form:\n# pattern=filter (like *.cpp=my_cpp_filter). See INPUT_FILTER for further\n# info on how filters are used. If FILTER_PATTERNS is empty or if\n# non of the patterns match the file name, INPUT_FILTER is applied.\n\nFILTER_PATTERNS        =\n\n# If the FILTER_SOURCE_FILES tag is set to YES, the input filter (if set using\n# INPUT_FILTER) will be used to filter the input files when producing source\n# files to browse (i.e. when SOURCE_BROWSER is set to YES).\n\nFILTER_SOURCE_FILES    = NO\n\n# The FILTER_SOURCE_PATTERNS tag can be used to specify source filters per file\n# pattern. A pattern will override the setting for FILTER_PATTERN (if any)\n# and it is also possible to disable source filtering for a specific pattern\n# using *.ext= (so without naming a filter). This option only has effect when\n# FILTER_SOURCE_FILES is enabled.\n\nFILTER_SOURCE_PATTERNS =\n\n#---------------------------------------------------------------------------\n# configuration options related to source browsing\n#---------------------------------------------------------------------------\n\n# If the SOURCE_BROWSER tag is set to YES then a list of source files will\n# be generated. Documented entities will be cross-referenced with these sources.\n# Note: To get rid of all source code in the generated output, make sure also\n# VERBATIM_HEADERS is set to NO.\n\nSOURCE_BROWSER         = NO\n\n# Setting the INLINE_SOURCES tag to YES will include the body\n# of functions and classes directly in the documentation.\n\nINLINE_SOURCES         = NO\n\n# Setting the STRIP_CODE_COMMENTS tag to YES (the default) will instruct\n# doxygen to hide any special comment blocks from generated source code\n# fragments. Normal C and C++ comments will always remain visible.\n\nSTRIP_CODE_COMMENTS    = YES\n\n# If the REFERENCED_BY_RELATION tag is set to YES\n# then for each documented function all documented\n# functions referencing it will be listed.\n\nREFERENCED_BY_RELATION = NO\n\n# If the REFERENCES_RELATION tag is set to YES\n# then for each documented function all documented entities\n# called/used by that function will be listed.\n\nREFERENCES_RELATION    = NO\n\n# If the REFERENCES_LINK_SOURCE tag is set to YES (the default)\n# and SOURCE_BROWSER tag is set to YES, then the hyperlinks from\n# functions in REFERENCES_RELATION and REFERENCED_BY_RELATION lists will\n# link to the source code.\n# Otherwise they will link to the documentation.\n\nREFERENCES_LINK_SOURCE = YES\n\n# If the USE_HTAGS tag is set to YES then the references to source code\n# will point to the HTML generated by the htags(1) tool instead of doxygen\n# built-in source browser. The htags tool is part of GNU's global source\n# tagging system (see http://www.gnu.org/software/global/global.html). You\n# will need version 4.8.6 or higher.\n\nUSE_HTAGS              = NO\n\n# If the VERBATIM_HEADERS tag is set to YES (the default) then Doxygen\n# will generate a verbatim copy of the header file for each class for\n# which an include is specified. Set to NO to disable this.\n\nVERBATIM_HEADERS       = YES\n\n#---------------------------------------------------------------------------\n# configuration options related to the alphabetical class index\n#---------------------------------------------------------------------------\n\n# If the ALPHABETICAL_INDEX tag is set to YES, an alphabetical index\n# of all compounds will be generated. Enable this if the project\n# contains a lot of classes, structs, unions or interfaces.\n\nALPHABETICAL_INDEX     = YES\n\n# If the alphabetical index is enabled (see ALPHABETICAL_INDEX) then\n# the COLS_IN_ALPHA_INDEX tag can be used to specify the number of columns\n# in which this list will be split (can be a number in the range [1..20])\n\nCOLS_IN_ALPHA_INDEX    = 5\n\n# In case all classes in a project start with a common prefix, all\n# classes will be put under the same header in the alphabetical index.\n# The IGNORE_PREFIX tag can be used to specify one or more prefixes that\n# should be ignored while generating the index headers.\n\nIGNORE_PREFIX          =\n\n#---------------------------------------------------------------------------\n# configuration options related to the HTML output\n#---------------------------------------------------------------------------\n\n# If the GENERATE_HTML tag is set to YES (the default) Doxygen will\n# generate HTML output.\n\nGENERATE_HTML          = YES\n\n# The HTML_OUTPUT tag is used to specify where the HTML docs will be put.\n# If a relative path is entered the value of OUTPUT_DIRECTORY will be\n# put in front of it. If left blank `html' will be used as the default path.\n\nHTML_OUTPUT            = html\n\n# The HTML_FILE_EXTENSION tag can be used to specify the file extension for\n# each generated HTML page (for example: .htm,.php,.asp). If it is left blank\n# doxygen will generate files with .html extension.\n\nHTML_FILE_EXTENSION    = .html\n\n# The HTML_HEADER tag can be used to specify a personal HTML header for\n# each generated HTML page. If it is left blank doxygen will generate a\n# standard header. Note that when using a custom header you are responsible\n#  for the proper inclusion of any scripts and style sheets that doxygen\n# needs, which is dependent on the configuration options used.\n# It is advised to generate a default header using \"doxygen -w html\n# header.html footer.html stylesheet.css YourConfigFile\" and then modify\n# that header. Note that the header is subject to change so you typically\n# have to redo this when upgrading to a newer version of doxygen or when\n# changing the value of configuration settings such as GENERATE_TREEVIEW!\n\nHTML_HEADER            =\n\n# The HTML_FOOTER tag can be used to specify a personal HTML footer for\n# each generated HTML page. If it is left blank doxygen will generate a\n# standard footer.\n\nHTML_FOOTER            =\n\n# The HTML_STYLESHEET tag can be used to specify a user-defined cascading\n# style sheet that is used by each HTML page. It can be used to\n# fine-tune the look of the HTML output. If the tag is left blank doxygen\n# will generate a default style sheet. Note that doxygen will try to copy\n# the style sheet file to the HTML output directory, so don't put your own\n# style sheet in the HTML output directory as well, or it will be erased!\n\nHTML_STYLESHEET        =\n\n# The HTML_EXTRA_FILES tag can be used to specify one or more extra images or\n# other source files which should be copied to the HTML output directory. Note\n# that these files will be copied to the base HTML output directory. Use the\n# $relpath$ marker in the HTML_HEADER and/or HTML_FOOTER files to load these\n# files. In the HTML_STYLESHEET file, use the file name only. Also note that\n# the files will be copied as-is; there are no commands or markers available.\n\nHTML_EXTRA_FILES       =\n\n# The HTML_COLORSTYLE_HUE tag controls the color of the HTML output.\n# Doxygen will adjust the colors in the style sheet and background images\n# according to this color. Hue is specified as an angle on a colorwheel,\n# see http://en.wikipedia.org/wiki/Hue for more information.\n# For instance the value 0 represents red, 60 is yellow, 120 is green,\n# 180 is cyan, 240 is blue, 300 purple, and 360 is red again.\n# The allowed range is 0 to 359.\n\nHTML_COLORSTYLE_HUE    = 220\n\n# The HTML_COLORSTYLE_SAT tag controls the purity (or saturation) of\n# the colors in the HTML output. For a value of 0 the output will use\n# grayscales only. A value of 255 will produce the most vivid colors.\n\nHTML_COLORSTYLE_SAT    = 100\n\n# The HTML_COLORSTYLE_GAMMA tag controls the gamma correction applied to\n# the luminance component of the colors in the HTML output. Values below\n# 100 gradually make the output lighter, whereas values above 100 make\n# the output darker. The value divided by 100 is the actual gamma applied,\n# so 80 represents a gamma of 0.8, The value 220 represents a gamma of 2.2,\n# and 100 does not change the gamma.\n\nHTML_COLORSTYLE_GAMMA  = 80\n\n# If the HTML_TIMESTAMP tag is set to YES then the footer of each generated HTML\n# page will contain the date and time when the page was generated. Setting\n# this to NO can help when comparing the output of multiple runs.\n\nHTML_TIMESTAMP         = YES\n\n# If the HTML_ALIGN_MEMBERS tag is set to YES, the members of classes,\n# files or namespaces will be aligned in HTML using tables. If set to\n# NO a bullet list will be used.\n\nHTML_ALIGN_MEMBERS     = YES\n\n# If the HTML_DYNAMIC_SECTIONS tag is set to YES then the generated HTML\n# documentation will contain sections that can be hidden and shown after the\n# page has loaded. For this to work a browser that supports\n# JavaScript and DHTML is required (for instance Mozilla 1.0+, Firefox\n# Netscape 6.0+, Internet explorer 5.0+, Konqueror, or Safari).\n\nHTML_DYNAMIC_SECTIONS  = NO\n\n# If the GENERATE_DOCSET tag is set to YES, additional index files\n# will be generated that can be used as input for Apple's Xcode 3\n# integrated development environment, introduced with OSX 10.5 (Leopard).\n# To create a documentation set, doxygen will generate a Makefile in the\n# HTML output directory. Running make will produce the docset in that\n# directory and running \"make install\" will install the docset in\n# ~/Library/Developer/Shared/Documentation/DocSets so that Xcode will find\n# it at startup.\n# See http://developer.apple.com/tools/creatingdocsetswithdoxygen.html\n# for more information.\n\nGENERATE_DOCSET        = NO\n\n# When GENERATE_DOCSET tag is set to YES, this tag determines the name of the\n# feed. A documentation feed provides an umbrella under which multiple\n# documentation sets from a single provider (such as a company or product suite)\n# can be grouped.\n\nDOCSET_FEEDNAME        = \"Doxygen generated docs\"\n\n# When GENERATE_DOCSET tag is set to YES, this tag specifies a string that\n# should uniquely identify the documentation set bundle. This should be a\n# reverse domain-name style string, e.g. com.mycompany.MyDocSet. Doxygen\n# will append .docset to the name.\n\nDOCSET_BUNDLE_ID       = org.doxygen.Project\n\n# When GENERATE_PUBLISHER_ID tag specifies a string that should uniquely identify\n# the documentation publisher. This should be a reverse domain-name style\n# string, e.g. com.mycompany.MyDocSet.documentation.\n\nDOCSET_PUBLISHER_ID    = org.doxygen.Publisher\n\n# The GENERATE_PUBLISHER_NAME tag identifies the documentation publisher.\n\nDOCSET_PUBLISHER_NAME  = Publisher\n\n# If the GENERATE_HTMLHELP tag is set to YES, additional index files\n# will be generated that can be used as input for tools like the\n# Microsoft HTML help workshop to generate a compiled HTML help file (.chm)\n# of the generated HTML documentation.\n\nGENERATE_HTMLHELP      = NO\n\n# If the GENERATE_HTMLHELP tag is set to YES, the CHM_FILE tag can\n# be used to specify the file name of the resulting .chm file. You\n# can add a path in front of the file if the result should not be\n# written to the html output directory.\n\nCHM_FILE               =\n\n# If the GENERATE_HTMLHELP tag is set to YES, the HHC_LOCATION tag can\n# be used to specify the location (absolute path including file name) of\n# the HTML help compiler (hhc.exe). If non-empty doxygen will try to run\n# the HTML help compiler on the generated index.hhp.\n\nHHC_LOCATION           =\n\n# If the GENERATE_HTMLHELP tag is set to YES, the GENERATE_CHI flag\n# controls if a separate .chi index file is generated (YES) or that\n# it should be included in the master .chm file (NO).\n\nGENERATE_CHI           = NO\n\n# If the GENERATE_HTMLHELP tag is set to YES, the CHM_INDEX_ENCODING\n# is used to encode HtmlHelp index (hhk), content (hhc) and project file\n# content.\n\nCHM_INDEX_ENCODING     =\n\n# If the GENERATE_HTMLHELP tag is set to YES, the BINARY_TOC flag\n# controls whether a binary table of contents is generated (YES) or a\n# normal table of contents (NO) in the .chm file.\n\nBINARY_TOC             = NO\n\n# The TOC_EXPAND flag can be set to YES to add extra items for group members\n# to the contents of the HTML help documentation and to the tree view.\n\nTOC_EXPAND             = NO\n\n# If the GENERATE_QHP tag is set to YES and both QHP_NAMESPACE and\n# QHP_VIRTUAL_FOLDER are set, an additional index file will be generated\n# that can be used as input for Qt's qhelpgenerator to generate a\n# Qt Compressed Help (.qch) of the generated HTML documentation.\n\nGENERATE_QHP           = NO\n\n# If the QHG_LOCATION tag is specified, the QCH_FILE tag can\n# be used to specify the file name of the resulting .qch file.\n# The path specified is relative to the HTML output folder.\n\nQCH_FILE               =\n\n# The QHP_NAMESPACE tag specifies the namespace to use when generating\n# Qt Help Project output. For more information please see\n# http://doc.trolltech.com/qthelpproject.html#namespace\n\nQHP_NAMESPACE          = org.doxygen.Project\n\n# The QHP_VIRTUAL_FOLDER tag specifies the namespace to use when generating\n# Qt Help Project output. For more information please see\n# http://doc.trolltech.com/qthelpproject.html#virtual-folders\n\nQHP_VIRTUAL_FOLDER     = doc\n\n# If QHP_CUST_FILTER_NAME is set, it specifies the name of a custom filter to\n# add. For more information please see\n# http://doc.trolltech.com/qthelpproject.html#custom-filters\n\nQHP_CUST_FILTER_NAME   =\n\n# The QHP_CUST_FILT_ATTRS tag specifies the list of the attributes of the\n# custom filter to add. For more information please see\n# <a href=\"http://doc.trolltech.com/qthelpproject.html#custom-filters\">\n# Qt Help Project / Custom Filters</a>.\n\nQHP_CUST_FILTER_ATTRS  =\n\n# The QHP_SECT_FILTER_ATTRS tag specifies the list of the attributes this\n# project's\n# filter section matches.\n# <a href=\"http://doc.trolltech.com/qthelpproject.html#filter-attributes\">\n# Qt Help Project / Filter Attributes</a>.\n\nQHP_SECT_FILTER_ATTRS  =\n\n# If the GENERATE_QHP tag is set to YES, the QHG_LOCATION tag can\n# be used to specify the location of Qt's qhelpgenerator.\n# If non-empty doxygen will try to run qhelpgenerator on the generated\n# .qhp file.\n\nQHG_LOCATION           =\n\n# If the GENERATE_ECLIPSEHELP tag is set to YES, additional index files\n#  will be generated, which together with the HTML files, form an Eclipse help\n# plugin. To install this plugin and make it available under the help contents\n# menu in Eclipse, the contents of the directory containing the HTML and XML\n# files needs to be copied into the plugins directory of eclipse. The name of\n# the directory within the plugins directory should be the same as\n# the ECLIPSE_DOC_ID value. After copying Eclipse needs to be restarted before\n# the help appears.\n\nGENERATE_ECLIPSEHELP   = NO\n\n# A unique identifier for the eclipse help plugin. When installing the plugin\n# the directory name containing the HTML and XML files should also have\n# this name.\n\nECLIPSE_DOC_ID         = org.doxygen.Project\n\n# The DISABLE_INDEX tag can be used to turn on/off the condensed index (tabs)\n# at top of each HTML page. The value NO (the default) enables the index and\n# the value YES disables it. Since the tabs have the same information as the\n# navigation tree you can set this option to NO if you already set\n# GENERATE_TREEVIEW to YES.\n\nDISABLE_INDEX          = NO\n\n# The GENERATE_TREEVIEW tag is used to specify whether a tree-like index\n# structure should be generated to display hierarchical information.\n# If the tag value is set to YES, a side panel will be generated\n# containing a tree-like index structure (just like the one that\n# is generated for HTML Help). For this to work a browser that supports\n# JavaScript, DHTML, CSS and frames is required (i.e. any modern browser).\n# Windows users are probably better off using the HTML help feature.\n# Since the tree basically has the same information as the tab index you\n# could consider to set DISABLE_INDEX to NO when enabling this option.\n\nGENERATE_TREEVIEW      = NO\n\n# The ENUM_VALUES_PER_LINE tag can be used to set the number of enum values\n# (range [0,1..20]) that doxygen will group on one line in the generated HTML\n# documentation. Note that a value of 0 will completely suppress the enum\n# values from appearing in the overview section.\n\nENUM_VALUES_PER_LINE   = 4\n\n# By enabling USE_INLINE_TREES, doxygen will generate the Groups, Directories,\n# and Class Hierarchy pages using a tree view instead of an ordered list.\n\nUSE_INLINE_TREES       = NO\n\n# If the treeview is enabled (see GENERATE_TREEVIEW) then this tag can be\n# used to set the initial width (in pixels) of the frame in which the tree\n# is shown.\n\nTREEVIEW_WIDTH         = 250\n\n# When the EXT_LINKS_IN_WINDOW option is set to YES doxygen will open\n# links to external symbols imported via tag files in a separate window.\n\nEXT_LINKS_IN_WINDOW    = NO\n\n# Use this tag to change the font size of Latex formulas included\n# as images in the HTML documentation. The default is 10. Note that\n# when you change the font size after a successful doxygen run you need\n# to manually remove any form_*.png images from the HTML output directory\n# to force them to be regenerated.\n\nFORMULA_FONTSIZE       = 10\n\n# Use the FORMULA_TRANPARENT tag to determine whether or not the images\n# generated for formulas are transparent PNGs. Transparent PNGs are\n# not supported properly for IE 6.0, but are supported on all modern browsers.\n# Note that when changing this option you need to delete any form_*.png files\n# in the HTML output before the changes have effect.\n\nFORMULA_TRANSPARENT    = YES\n\n# Enable the USE_MATHJAX option to render LaTeX formulas using MathJax\n# (see http://www.mathjax.org) which uses client side Javascript for the\n# rendering instead of using prerendered bitmaps. Use this if you do not\n# have LaTeX installed or if you want to formulas look prettier in the HTML\n# output. When enabled you also need to install MathJax separately and\n# configure the path to it using the MATHJAX_RELPATH option.\n\nUSE_MATHJAX            = NO\n\n# When MathJax is enabled you need to specify the location relative to the\n# HTML output directory using the MATHJAX_RELPATH option. The destination\n# directory should contain the MathJax.js script. For instance, if the mathjax\n# directory is located at the same level as the HTML output directory, then\n# MATHJAX_RELPATH should be ../mathjax. The default value points to the\n# mathjax.org site, so you can quickly see the result without installing\n# MathJax, but it is strongly recommended to install a local copy of MathJax\n# before deployment.\n\nMATHJAX_RELPATH        = http://www.mathjax.org/mathjax\n\n# The MATHJAX_EXTENSIONS tag can be used to specify one or MathJax extension\n# names that should be enabled during MathJax rendering.\n\nMATHJAX_EXTENSIONS     =\n\n# When the SEARCHENGINE tag is enabled doxygen will generate a search box\n# for the HTML output. The underlying search engine uses javascript\n# and DHTML and should work on any modern browser. Note that when using\n# HTML help (GENERATE_HTMLHELP), Qt help (GENERATE_QHP), or docsets\n# (GENERATE_DOCSET) there is already a search function so this one should\n# typically be disabled. For large projects the javascript based search engine\n# can be slow, then enabling SERVER_BASED_SEARCH may provide a better solution.\n\nSEARCHENGINE           = YES\n\n# When the SERVER_BASED_SEARCH tag is enabled the search engine will be\n# implemented using a PHP enabled web server instead of at the web client\n# using Javascript. Doxygen will generate the search PHP script and index\n# file to put on the web server. The advantage of the server\n# based approach is that it scales better to large projects and allows\n# full text search. The disadvantages are that it is more difficult to setup\n# and does not have live searching capabilities.\n\nSERVER_BASED_SEARCH    = NO\n\n#---------------------------------------------------------------------------\n# configuration options related to the LaTeX output\n#---------------------------------------------------------------------------\n\n# If the GENERATE_LATEX tag is set to YES (the default) Doxygen will\n# generate Latex output.\n\nGENERATE_LATEX         = YES\n\n# The LATEX_OUTPUT tag is used to specify where the LaTeX docs will be put.\n# If a relative path is entered the value of OUTPUT_DIRECTORY will be\n# put in front of it. If left blank `latex' will be used as the default path.\n\nLATEX_OUTPUT           = latex\n\n# The LATEX_CMD_NAME tag can be used to specify the LaTeX command name to be\n# invoked. If left blank `latex' will be used as the default command name.\n# Note that when enabling USE_PDFLATEX this option is only used for\n# generating bitmaps for formulas in the HTML output, but not in the\n# Makefile that is written to the output directory.\n\nLATEX_CMD_NAME         = latex\n\n# The MAKEINDEX_CMD_NAME tag can be used to specify the command name to\n# generate index for LaTeX. If left blank `makeindex' will be used as the\n# default command name.\n\nMAKEINDEX_CMD_NAME     = makeindex\n\n# If the COMPACT_LATEX tag is set to YES Doxygen generates more compact\n# LaTeX documents. This may be useful for small projects and may help to\n# save some trees in general.\n\nCOMPACT_LATEX          = NO\n\n# The PAPER_TYPE tag can be used to set the paper type that is used\n# by the printer. Possible values are: a4, letter, legal and\n# executive. If left blank a4wide will be used.\n\nPAPER_TYPE             = a4\n\n# The EXTRA_PACKAGES tag can be to specify one or more names of LaTeX\n# packages that should be included in the LaTeX output.\n\nEXTRA_PACKAGES         =\n\n# The LATEX_HEADER tag can be used to specify a personal LaTeX header for\n# the generated latex document. The header should contain everything until\n# the first chapter. If it is left blank doxygen will generate a\n# standard header. Notice: only use this tag if you know what you are doing!\n\nLATEX_HEADER           =\n\n# The LATEX_FOOTER tag can be used to specify a personal LaTeX footer for\n# the generated latex document. The footer should contain everything after\n# the last chapter. If it is left blank doxygen will generate a\n# standard footer. Notice: only use this tag if you know what you are doing!\n\nLATEX_FOOTER           =\n\n# If the PDF_HYPERLINKS tag is set to YES, the LaTeX that is generated\n# is prepared for conversion to pdf (using ps2pdf). The pdf file will\n# contain links (just like the HTML output) instead of page references\n# This makes the output suitable for online browsing using a pdf viewer.\n\nPDF_HYPERLINKS         = YES\n\n# If the USE_PDFLATEX tag is set to YES, pdflatex will be used instead of\n# plain latex in the generated Makefile. Set this option to YES to get a\n# higher quality PDF documentation.\n\nUSE_PDFLATEX           = YES\n\n# If the LATEX_BATCHMODE tag is set to YES, doxygen will add the \\\\batchmode.\n# command to the generated LaTeX files. This will instruct LaTeX to keep\n# running if errors occur, instead of asking the user for help.\n# This option is also used when generating formulas in HTML.\n\nLATEX_BATCHMODE        = NO\n\n# If LATEX_HIDE_INDICES is set to YES then doxygen will not\n# include the index chapters (such as File Index, Compound Index, etc.)\n# in the output.\n\nLATEX_HIDE_INDICES     = NO\n\n# If LATEX_SOURCE_CODE is set to YES then doxygen will include\n# source code with syntax highlighting in the LaTeX output.\n# Note that which sources are shown also depends on other settings\n# such as SOURCE_BROWSER.\n\nLATEX_SOURCE_CODE      = NO\n\n# The LATEX_BIB_STYLE tag can be used to specify the style to use for the\n# bibliography, e.g. plainnat, or ieeetr. The default style is \"plain\". See\n# http://en.wikipedia.org/wiki/BibTeX for more info.\n\nLATEX_BIB_STYLE        = plain\n\n#---------------------------------------------------------------------------\n# configuration options related to the RTF output\n#---------------------------------------------------------------------------\n\n# If the GENERATE_RTF tag is set to YES Doxygen will generate RTF output\n# The RTF output is optimized for Word 97 and may not look very pretty with\n# other RTF readers or editors.\n\nGENERATE_RTF           = NO\n\n# The RTF_OUTPUT tag is used to specify where the RTF docs will be put.\n# If a relative path is entered the value of OUTPUT_DIRECTORY will be\n# put in front of it. If left blank `rtf' will be used as the default path.\n\nRTF_OUTPUT             = rtf\n\n# If the COMPACT_RTF tag is set to YES Doxygen generates more compact\n# RTF documents. This may be useful for small projects and may help to\n# save some trees in general.\n\nCOMPACT_RTF            = NO\n\n# If the RTF_HYPERLINKS tag is set to YES, the RTF that is generated\n# will contain hyperlink fields. The RTF file will\n# contain links (just like the HTML output) instead of page references.\n# This makes the output suitable for online browsing using WORD or other\n# programs which support those fields.\n# Note: wordpad (write) and others do not support links.\n\nRTF_HYPERLINKS         = NO\n\n# Load style sheet definitions from file. Syntax is similar to doxygen's\n# config file, i.e. a series of assignments. You only have to provide\n# replacements, missing definitions are set to their default value.\n\nRTF_STYLESHEET_FILE    =\n\n# Set optional variables used in the generation of an rtf document.\n# Syntax is similar to doxygen's config file.\n\nRTF_EXTENSIONS_FILE    =\n\n#---------------------------------------------------------------------------\n# configuration options related to the man page output\n#---------------------------------------------------------------------------\n\n# If the GENERATE_MAN tag is set to YES (the default) Doxygen will\n# generate man pages\n\nGENERATE_MAN           = NO\n\n# The MAN_OUTPUT tag is used to specify where the man pages will be put.\n# If a relative path is entered the value of OUTPUT_DIRECTORY will be\n# put in front of it. If left blank `man' will be used as the default path.\n\nMAN_OUTPUT             = man\n\n# The MAN_EXTENSION tag determines the extension that is added to\n# the generated man pages (default is the subroutine's section .3)\n\nMAN_EXTENSION          = .3\n\n# If the MAN_LINKS tag is set to YES and Doxygen generates man output,\n# then it will generate one additional man file for each entity\n# documented in the real man page(s). These additional files\n# only source the real man page, but without them the man command\n# would be unable to find the correct page. The default is NO.\n\nMAN_LINKS              = NO\n\n#---------------------------------------------------------------------------\n# configuration options related to the XML output\n#---------------------------------------------------------------------------\n\n# If the GENERATE_XML tag is set to YES Doxygen will\n# generate an XML file that captures the structure of\n# the code including all documentation.\n\nGENERATE_XML           = NO\n\n# The XML_OUTPUT tag is used to specify where the XML pages will be put.\n# If a relative path is entered the value of OUTPUT_DIRECTORY will be\n# put in front of it. If left blank `xml' will be used as the default path.\n\nXML_OUTPUT             = xml\n\n# The XML_SCHEMA tag can be used to specify an XML schema,\n# which can be used by a validating XML parser to check the\n# syntax of the XML files.\n\nXML_SCHEMA             =\n\n# The XML_DTD tag can be used to specify an XML DTD,\n# which can be used by a validating XML parser to check the\n# syntax of the XML files.\n\nXML_DTD                =\n\n# If the XML_PROGRAMLISTING tag is set to YES Doxygen will\n# dump the program listings (including syntax highlighting\n# and cross-referencing information) to the XML output. Note that\n# enabling this will significantly increase the size of the XML output.\n\nXML_PROGRAMLISTING     = YES\n\n#---------------------------------------------------------------------------\n# configuration options for the AutoGen Definitions output\n#---------------------------------------------------------------------------\n\n# If the GENERATE_AUTOGEN_DEF tag is set to YES Doxygen will\n# generate an AutoGen Definitions (see autogen.sf.net) file\n# that captures the structure of the code including all\n# documentation. Note that this feature is still experimental\n# and incomplete at the moment.\n\nGENERATE_AUTOGEN_DEF   = NO\n\n#---------------------------------------------------------------------------\n# configuration options related to the Perl module output\n#---------------------------------------------------------------------------\n\n# If the GENERATE_PERLMOD tag is set to YES Doxygen will\n# generate a Perl module file that captures the structure of\n# the code including all documentation. Note that this\n# feature is still experimental and incomplete at the\n# moment.\n\nGENERATE_PERLMOD       = NO\n\n# If the PERLMOD_LATEX tag is set to YES Doxygen will generate\n# the necessary Makefile rules, Perl scripts and LaTeX code to be able\n# to generate PDF and DVI output from the Perl module output.\n\nPERLMOD_LATEX          = NO\n\n# If the PERLMOD_PRETTY tag is set to YES the Perl module output will be\n# nicely formatted so it can be parsed by a human reader.\n# This is useful\n# if you want to understand what is going on.\n# On the other hand, if this\n# tag is set to NO the size of the Perl module output will be much smaller\n# and Perl will parse it just the same.\n\nPERLMOD_PRETTY         = YES\n\n# The names of the make variables in the generated doxyrules.make file\n# are prefixed with the string contained in PERLMOD_MAKEVAR_PREFIX.\n# This is useful so different doxyrules.make files included by the same\n# Makefile don't overwrite each other's variables.\n\nPERLMOD_MAKEVAR_PREFIX =\n\n#---------------------------------------------------------------------------\n# Configuration options related to the preprocessor\n#---------------------------------------------------------------------------\n\n# If the ENABLE_PREPROCESSING tag is set to YES (the default) Doxygen will\n# evaluate all C-preprocessor directives found in the sources and include\n# files.\n\nENABLE_PREPROCESSING   = YES\n\n# If the MACRO_EXPANSION tag is set to YES Doxygen will expand all macro\n# names in the source code. If set to NO (the default) only conditional\n# compilation will be performed. Macro expansion can be done in a controlled\n# way by setting EXPAND_ONLY_PREDEF to YES.\n\nMACRO_EXPANSION        = NO\n\n# If the EXPAND_ONLY_PREDEF and MACRO_EXPANSION tags are both set to YES\n# then the macro expansion is limited to the macros specified with the\n# PREDEFINED and EXPAND_AS_DEFINED tags.\n\nEXPAND_ONLY_PREDEF     = NO\n\n# If the SEARCH_INCLUDES tag is set to YES (the default) the includes files\n# pointed to by INCLUDE_PATH will be searched when a #include is found.\n\nSEARCH_INCLUDES        = YES\n\n# The INCLUDE_PATH tag can be used to specify one or more directories that\n# contain include files that are not input files but should be processed by\n# the preprocessor.\n\nINCLUDE_PATH           =\n\n# You can use the INCLUDE_FILE_PATTERNS tag to specify one or more wildcard\n# patterns (like *.h and *.hpp) to filter out the header-files in the\n# directories. If left blank, the patterns specified with FILE_PATTERNS will\n# be used.\n\nINCLUDE_FILE_PATTERNS  =\n\n# The PREDEFINED tag can be used to specify one or more macro names that\n# are defined before the preprocessor is started (similar to the -D option of\n# gcc). The argument of the tag is a list of macros of the form: name\n# or name=definition (no spaces). If the definition and the = are\n# omitted =1 is assumed. To prevent a macro definition from being\n# undefined via #undef or recursively expanded use the := operator\n# instead of the = operator.\n\nPREDEFINED             =\n\n# If the MACRO_EXPANSION and EXPAND_ONLY_PREDEF tags are set to YES then\n# this tag can be used to specify a list of macro names that should be expanded.\n# The macro definition that is found in the sources will be used.\n# Use the PREDEFINED tag if you want to use a different macro definition that\n# overrules the definition found in the source code.\n\nEXPAND_AS_DEFINED      =\n\n# If the SKIP_FUNCTION_MACROS tag is set to YES (the default) then\n# doxygen's preprocessor will remove all references to function-like macros\n# that are alone on a line, have an all uppercase name, and do not end with a\n# semicolon, because these will confuse the parser if not removed.\n\nSKIP_FUNCTION_MACROS   = YES\n\n#---------------------------------------------------------------------------\n# Configuration::additions related to external references\n#---------------------------------------------------------------------------\n\n# The TAGFILES option can be used to specify one or more tagfiles.\n# Optionally an initial location of the external documentation\n# can be added for each tagfile. The format of a tag file without\n# this location is as follows:\n#\n# TAGFILES = file1 file2 ...\n# Adding location for the tag files is done as follows:\n#\n# TAGFILES = file1=loc1 \"file2 = loc2\" ...\n# where \"loc1\" and \"loc2\" can be relative or absolute paths or\n# URLs. If a location is present for each tag, the installdox tool\n# does not have to be run to correct the links.\n# Note that each tag file must have a unique name\n# (where the name does NOT include the path)\n# If a tag file is not located in the directory in which doxygen\n# is run, you must also specify the path to the tagfile here.\n\nTAGFILES               =\n\n# When a file name is specified after GENERATE_TAGFILE, doxygen will create\n# a tag file that is based on the input files it reads.\n\nGENERATE_TAGFILE       =\n\n# If the ALLEXTERNALS tag is set to YES all external classes will be listed\n# in the class index. If set to NO only the inherited external classes\n# will be listed.\n\nALLEXTERNALS           = NO\n\n# If the EXTERNAL_GROUPS tag is set to YES all external groups will be listed\n# in the modules index. If set to NO, only the current project's groups will\n# be listed.\n\nEXTERNAL_GROUPS        = YES\n\n# The PERL_PATH should be the absolute path and name of the perl script\n# interpreter (i.e. the result of `which perl').\n\nPERL_PATH              = /usr/bin/perl\n\n#---------------------------------------------------------------------------\n# Configuration options related to the dot tool\n#---------------------------------------------------------------------------\n\n# If the CLASS_DIAGRAMS tag is set to YES (the default) Doxygen will\n# generate a inheritance diagram (in HTML, RTF and LaTeX) for classes with base\n# or super classes. Setting the tag to NO turns the diagrams off. Note that\n# this option also works with HAVE_DOT disabled, but it is recommended to\n# install and use dot, since it yields more powerful graphs.\n\nCLASS_DIAGRAMS         = YES\n\n# You can define message sequence charts within doxygen comments using the \\msc\n# command. Doxygen will then run the mscgen tool (see\n# http://www.mcternan.me.uk/mscgen/) to produce the chart and insert it in the\n# documentation. The MSCGEN_PATH tag allows you to specify the directory where\n# the mscgen tool resides. If left empty the tool is assumed to be found in the\n# default search path.\n\nMSCGEN_PATH            =\n\n# If set to YES, the inheritance and collaboration graphs will hide\n# inheritance and usage relations if the target is undocumented\n# or is not a class.\n\nHIDE_UNDOC_RELATIONS   = YES\n\n# If you set the HAVE_DOT tag to YES then doxygen will assume the dot tool is\n# available from the path. This tool is part of Graphviz, a graph visualization\n# toolkit from AT&T and Lucent Bell Labs. The other options in this section\n# have no effect if this option is set to NO (the default)\n\nHAVE_DOT               = NO\n\n# The DOT_NUM_THREADS specifies the number of dot invocations doxygen is\n# allowed to run in parallel. When set to 0 (the default) doxygen will\n# base this on the number of processors available in the system. You can set it\n# explicitly to a value larger than 0 to get control over the balance\n# between CPU load and processing speed.\n\nDOT_NUM_THREADS        = 0\n\n# By default doxygen will use the Helvetica font for all dot files that\n# doxygen generates. When you want a differently looking font you can specify\n# the font name using DOT_FONTNAME. You need to make sure dot is able to find\n# the font, which can be done by putting it in a standard location or by setting\n# the DOTFONTPATH environment variable or by setting DOT_FONTPATH to the\n# directory containing the font.\n\nDOT_FONTNAME           = Helvetica\n\n# The DOT_FONTSIZE tag can be used to set the size of the font of dot graphs.\n# The default size is 10pt.\n\nDOT_FONTSIZE           = 10\n\n# By default doxygen will tell dot to use the Helvetica font.\n# If you specify a different font using DOT_FONTNAME you can use DOT_FONTPATH to\n# set the path where dot can find it.\n\nDOT_FONTPATH           =\n\n# If the CLASS_GRAPH and HAVE_DOT tags are set to YES then doxygen\n# will generate a graph for each documented class showing the direct and\n# indirect inheritance relations. Setting this tag to YES will force the\n# CLASS_DIAGRAMS tag to NO.\n\nCLASS_GRAPH            = YES\n\n# If the COLLABORATION_GRAPH and HAVE_DOT tags are set to YES then doxygen\n# will generate a graph for each documented class showing the direct and\n# indirect implementation dependencies (inheritance, containment, and\n# class references variables) of the class with other documented classes.\n\nCOLLABORATION_GRAPH    = YES\n\n# If the GROUP_GRAPHS and HAVE_DOT tags are set to YES then doxygen\n# will generate a graph for groups, showing the direct groups dependencies\n\nGROUP_GRAPHS           = YES\n\n# If the UML_LOOK tag is set to YES doxygen will generate inheritance and\n# collaboration diagrams in a style similar to the OMG's Unified Modeling\n# Language.\n\nUML_LOOK               = NO\n\n# If set to YES, the inheritance and collaboration graphs will show the\n# relations between templates and their instances.\n\nTEMPLATE_RELATIONS     = NO\n\n# If the ENABLE_PREPROCESSING, SEARCH_INCLUDES, INCLUDE_GRAPH, and HAVE_DOT\n# tags are set to YES then doxygen will generate a graph for each documented\n# file showing the direct and indirect include dependencies of the file with\n# other documented files.\n\nINCLUDE_GRAPH          = YES\n\n# If the ENABLE_PREPROCESSING, SEARCH_INCLUDES, INCLUDED_BY_GRAPH, and\n# HAVE_DOT tags are set to YES then doxygen will generate a graph for each\n# documented header file showing the documented files that directly or\n# indirectly include this file.\n\nINCLUDED_BY_GRAPH      = YES\n\n# If the CALL_GRAPH and HAVE_DOT options are set to YES then\n# doxygen will generate a call dependency graph for every global function\n# or class method. Note that enabling this option will significantly increase\n# the time of a run. So in most cases it will be better to enable call graphs\n# for selected functions only using the \\callgraph command.\n\nCALL_GRAPH             = NO\n\n# If the CALLER_GRAPH and HAVE_DOT tags are set to YES then\n# doxygen will generate a caller dependency graph for every global function\n# or class method. Note that enabling this option will significantly increase\n# the time of a run. So in most cases it will be better to enable caller\n# graphs for selected functions only using the \\callergraph command.\n\nCALLER_GRAPH           = NO\n\n# If the GRAPHICAL_HIERARCHY and HAVE_DOT tags are set to YES then doxygen\n# will generate a graphical hierarchy of all classes instead of a textual one.\n\nGRAPHICAL_HIERARCHY    = YES\n\n# If the DIRECTORY_GRAPH, SHOW_DIRECTORIES and HAVE_DOT tags are set to YES\n# then doxygen will show the dependencies a directory has on other directories\n# in a graphical way. The dependency relations are determined by the #include\n# relations between the files in the directories.\n\nDIRECTORY_GRAPH        = YES\n\n# The DOT_IMAGE_FORMAT tag can be used to set the image format of the images\n# generated by dot. Possible values are svg, png, jpg, or gif.\n# If left blank png will be used. If you choose svg you need to set\n# HTML_FILE_EXTENSION to xhtml in order to make the SVG files\n# visible in IE 9+ (other browsers do not have this requirement).\n\nDOT_IMAGE_FORMAT       = png\n\n# If DOT_IMAGE_FORMAT is set to svg, then this option can be set to YES to\n# enable generation of interactive SVG images that allow zooming and panning.\n# Note that this requires a modern browser other than Internet Explorer.\n# Tested and working are Firefox, Chrome, Safari, and Opera. For IE 9+ you\n# need to set HTML_FILE_EXTENSION to xhtml in order to make the SVG files\n# visible. Older versions of IE do not have SVG support.\n\nINTERACTIVE_SVG        = NO\n\n# The tag DOT_PATH can be used to specify the path where the dot tool can be\n# found. If left blank, it is assumed the dot tool can be found in the path.\n\nDOT_PATH               =\n\n# The DOTFILE_DIRS tag can be used to specify one or more directories that\n# contain dot files that are included in the documentation (see the\n# \\dotfile command).\n\nDOTFILE_DIRS           =\n\n# The MSCFILE_DIRS tag can be used to specify one or more directories that\n# contain msc files that are included in the documentation (see the\n# \\mscfile command).\n\nMSCFILE_DIRS           =\n\n# The DOT_GRAPH_MAX_NODES tag can be used to set the maximum number of\n# nodes that will be shown in the graph. If the number of nodes in a graph\n# becomes larger than this value, doxygen will truncate the graph, which is\n# visualized by representing a node as a red box. Note that doxygen if the\n# number of direct children of the root node in a graph is already larger than\n# DOT_GRAPH_MAX_NODES then the graph will not be shown at all. Also note\n# that the size of a graph can be further restricted by MAX_DOT_GRAPH_DEPTH.\n\nDOT_GRAPH_MAX_NODES    = 50\n\n# The MAX_DOT_GRAPH_DEPTH tag can be used to set the maximum depth of the\n# graphs generated by dot. A depth value of 3 means that only nodes reachable\n# from the root by following a path via at most 3 edges will be shown. Nodes\n# that lay further from the root node will be omitted. Note that setting this\n# option to 1 or 2 may greatly reduce the computation time needed for large\n# code bases. Also note that the size of a graph can be further restricted by\n# DOT_GRAPH_MAX_NODES. Using a depth of 0 means no depth restriction.\n\nMAX_DOT_GRAPH_DEPTH    = 0\n\n# Set the DOT_TRANSPARENT tag to YES to generate images with a transparent\n# background. This is disabled by default, because dot on Windows does not\n# seem to support this out of the box. Warning: Depending on the platform used,\n# enabling this option may lead to badly anti-aliased labels on the edges of\n# a graph (i.e. they become hard to read).\n\nDOT_TRANSPARENT        = NO\n\n# Set the DOT_MULTI_TARGETS tag to YES allow dot to generate multiple output\n# files in one run (i.e. multiple -o and -T options on the command line). This\n# makes dot run faster, but since only newer versions of dot (>1.8.10)\n# support this, this feature is disabled by default.\n\nDOT_MULTI_TARGETS      = YES\n\n# If the GENERATE_LEGEND tag is set to YES (the default) Doxygen will\n# generate a legend page explaining the meaning of the various boxes and\n# arrows in the dot generated graphs.\n\nGENERATE_LEGEND        = YES\n\n# If the DOT_CLEANUP tag is set to YES (the default) Doxygen will\n# remove the intermediate dot files that are used to generate\n# the various graphs.\n\nDOT_CLEANUP            = YES\n"
  },
  {
    "path": "scripts/Makefile.connectal.application",
    "content": "# Copyright (c) 2015 The Connectal Project\n#\n# Permission is hereby granted, free of charge, to any person obtaining a\n# copy of this software and associated documentation files (the \"Software\"),\n# to deal in the Software without restriction, including without limitation\n# the rights to use, copy, modify, merge, publish, distribute, sublicense,\n# and/or sell copies of the Software, and to permit persons to whom the\n# Software is furnished to do so, subject to the following conditions:\n#\n# The above copyright notice and this permission notice shall be included\n# in all copies or substantial portions of the Software.\n#\n# THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n# OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n# DEALINGS IN THE SOFTWARE.\n#\nexport V=0\nifeq ($(V),0)\nQ=@\nelse\nQ=\nendif\n\ninclude $(DTOP)/jni/Makefile.generated_files\n\nPORTAL_INFRA := portal.c transportHardware.c transportSocket.c transportShared.c transportSerial.c portalJson.c portalPrintf.c poller.cpp sock_utils.c timer.c\nPORTAL_SRC_FILES := $(addprefix $(CONNECTALDIR)/cpp/, $(PORTAL_INFRA)) \\\n      $(addprefix $(DTOP)/jni/,  $(GENERATED_CPP))\n\nBSIM_EXE_CXX_FILES := TlpReplay.cpp\nBSIM_EXE_CXX := $(addprefix $(CONNECTALDIR)/cpp/, $(BSIM_EXE_CXX_FILES))\n"
  },
  {
    "path": "scripts/Makefile.connectal.build",
    "content": "# Copyright (c) 2014 Quanta Research Cambridge, Inc\n#\n# Permission is hereby granted, free of charge, to any person obtaining a\n# copy of this software and associated documentation files (the \"Software\"),\n# to deal in the Software without restriction, including without limitation\n# the rights to use, copy, modify, merge, publish, distribute, sublicense,\n# and/or sell copies of the Software, and to permit persons to whom the\n# Software is furnished to do so, subject to the following conditions:\n#\n# The above copyright notice and this permission notice shall be included\n# in all copies or substantial portions of the Software.\n#\n# THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n# OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n# DEALINGS IN THE SOFTWARE.\n#\n#\n# File: Makefile.build\n#\n\nV?=0\nifeq ($(V),0)\n  Q=@\n  BSC_QUIET=-no-show-compiles\n  CONNECTAL_NDK_PARAM=\"NDK_HOST_ECHO=true\"\n  FPGAMAKE_VERBOSE=\nelse\n  Q=\n  BSC_QUIET=\n  CONNECTAL_NDK_PARAM=\n  FPGAMAKE_VERBOSE=-v\nendif\nNDK_OBJCOPY=$(shell $(NDKPATH)ndk-which objcopy)\n\nifneq ($(XILINX),)\nifeq ($(OS),android)\nOBJCOPY?=$(NDK_OBJCOPY)\nBINFILE?=bin/mkTop.xdevcfg.bin.gz\nelse #!android\nOBJCOPY?=$(TOOLCHAIN)objcopy\nBINFILE?=bin/mkTop.bin.gz\nendif #!android\nelse #!XILINX\nOBJCOPY?= objcopy\nBINFILE?=bin/mkTop.sof.gz\nendif #!XILINX\n\nCONNECTAL_EXENAME?=ubuntu.exe\nCONNECTAL_EXENAME2?=ubuntu.exe2\nifneq ($(CONNECTAL_SHARED),)\nEXENAME=connectal.so\nelse\nEXENAME=$(CONNECTAL_EXENAME)\nendif\nEXENAME2=$(CONNECTAL_EXENAME2)\n\nifeq ($(CONNECTAL_DEBUG),1)\nGDB=gdb\nGDB2=gdb\nelse\nGDB= LD_PRELOAD=libSegFault.so SEGFAULT_USE_ALTSTACK=1 SEGFAULT_OUTPUT_NAME=bin/bsimexe-segv-output.txt\nGDB2= LD_PRELOAD=libSegFault.so SEGFAULT_USE_ALTSTACK=1 SEGFAULT_OUTPUT_NAME=bin/bsimexe2-segv-output.txt\nendif\n\nGDB_BSIM= LD_PRELOAD=libSegFault.so SEGFAULT_USE_ALTSTACK=1 SEGFAULT_OUTPUT_NAME=bin/bsim-segv-output.txt\n\n\nBLUESPECDIR?=$(shell bsc --help | grep 'Bluespec directory:' | sed 's/Bluespec directory: //')\nBSCVERSION=$(shell bsc -v |grep version | sed -e \"s/.*version //\" -e \"s/ .*//\")\nBSCMAJOR=$(shell bsc -v |grep version | sed -e \"s/.*version //\" -e \"s/\\..*//\")\nifeq ($(BSCVERSION),)\n\tBSIM_LIBRARY_DIR = $(BLUESPECDIR)/Bluesim\nelse ifeq ($(shell test $(BSCMAJOR) -le 2019 &>/dev/null && echo obsolete),obsolete)\n\tBSIM_LIBRARY_DIR = $(BLUESPECDIR)/Bluesim/g++4_64\n\tCXXFLAGS_BSIM += -DBSC_OBSOLETE\nelse\n\tBSIM_LIBRARY_DIR = $(BLUESPECDIR)/Bluesim\nendif\n\nifneq ($(BSCMAJOR), 2013)\n    # S0015: The use of a mkSyncReset may not always result in a reset\n    #        signal being seen on the destination side. Recommend\n    #        replacement with mkAsyncReset.\n    BSCWARNFLAGS += -demote-errors G0066:G0045 -suppress-warnings G0046:G0020:S0015:S0080:S0039:T0127\nelse\n    #BSCFLAGS_COMMON += -D ExportUnusedClocksAndResets\nendif\nifneq ($(BSCMAJOR), 2013)\n    BSCFLAGS_COMMON += -D ClockDefaultParam\nendif\nifeq ($(BOARD),bluesim)\n    BSCFLAGS_COMMON += -sim\nelse\n    BSCFLAGS_COMMON += -verilog -remove-dollar\nendif\n\n# Add -wait-for-license if bsc supports it\nBSCFLAGS_COMMON += $(shell bsc -help | grep -q wait-for-license && echo -wait-for-license)\n\nBSCOPTFLAGS= -show-schedule -aggressive-conditions -show-method-bvi\nBSCPATHFLAGS=  -bdir $(DTOP)/obj -vdir $(DTOP)/verilog -simdir $(DTOP)/obj -info-dir $(DTOP)/obj\nBSCFLAGS_COMMON += $(BSCWARNFLAGS) $(BSCOPTFLAGS) $(BSCPATHFLAGS)\nPROF_FLAGS= #-pg\nexport SIM_CFLAGS= $(CFLAGS_PROJECT) -fPIC -Ijni -I $(CONNECTALDIR)/cpp -I $(CONNECTALDIR) -I $(CONNECTALDIR)/lib/json -O $(PROF_FLAGS)\nexport SIM_CXXFLAGS= $(CXXFLAGS_PROJECT) -fPIC -Ijni -I $(CONNECTALDIR)/cpp -I $(CONNECTALDIR) -O $(PROF_FLAGS)\nSIM_CXX_COMMON = $(addprefix $(CONNECTALDIR)/cpp/, TlpReplay.cpp BsimDma.cpp sock_utils.c portalPrintf.c XsimTop.cpp poller.cpp transportSocket.c transportHardware.c transportXsim.c portal.c)\nSIM_CXX_LOCAL = $(SIM_CXX_COMMON) $(DTOP)/jni/XsimMsgRequest.c $(DTOP)/jni/XsimMsgIndication.c $(DTOP)/jni/GeneratedCppCallbacks.cpp\n\nifneq ($(ALTERA),)\nBLUESPEC_VERILOG+=$(BLUESPECDIR)/Verilog.Quartus\nendif\nifneq ($(XILINX),)\nBLUESPEC_VERILOG+=$(BLUESPECDIR)/Verilog.Vivado\nendif #XILINX\nBLUESPEC_VERILOG+=$(BLUESPECDIR)/Verilog\n\nVIVADO=$(shell which vivado)\nifneq ($(VIVADO), )\nexport VIVADODIR=$(shell dirname $(shell dirname $(VIVADO))))\nVIVADOFLAGS= -notrace\nXVLOGFLAGS =\nendif\n\nMODELSIM=$(shell which vsim)\nifneq ($(MODELSIM), )\nendif\n\nQUARTUS=$(shell which quartus_sh)\nifneq ($(QUARTUS), )\nexport QUARTUSDIR=$(shell dirname $(shell dirname $(QUARTUS)))\nendif\n\nifeq ($(USE_BUILDCACHE),1)\nBUILDCACHE=$(shell cd $(CONNECTALDIR)/..; /bin/pwd)/buildcache/buildcache\nifeq (\"$(BUILDCACHE_CACHEDIR)\", \"\")\nBUILDCACHE_CACHEDIR=$(shell cd $(CONNECTALDIR)/..; /bin/pwd)/fpgamake-cache\nendif\nendif\n\nEXTRABSVPATH = $(shell test -d $(BLUESPECDIR)/Libraries/FPGA && echo -p +:$(BLUESPECDIR)/Libraries/FPGA/Xilinx:$(BLUESPECDIR)/Libraries/FPGA/Altera:$(BLUESPECDIR)/Libraries/FPGA/Misc)\n\nifneq ($(BSC_LM_LICENSE_FILE),)\nRUN_BSC_LM_LICENSE_FILE=LM_LICENSE_FILE=$(BSC_LM_LICENSE_FILE)\nendif\nRUN_BSC = $(RUN_BSC_LM_LICENSE_FILE) BUILDCACHE_CACHEDIR=$(BUILDCACHE_CACHEDIR) $(BUILDCACHE) bsc $(BSC_QUIET) $(BSVDEFINES) $(BSCFLAGS_COMMON) $(BSCFLAGS_PROJECT) $(BSCFLAGS_EXTRA) -p +:$(BSVPATH) $(EXTRABSVPATH)\nVFILE=verilog/$(MKTOP).v\n\nall: exe bits extratarget\n\nextratarget::\n# placeholder for variant targets\n\nifeq ($(RUNSOURCE2),)\n    exe: $(EXENAME)\nelse\n    exe: $(EXENAME) $(EXENAME2)\nendif\n\nubuntu.exe: prepare_bin_target\n\t@echo \"ubuntu.exe\"\n\t$(Q)cd jni; $(MAKE) --no-print-directory -f Ubuntu.mk ubuntu.exe\n\t@cp -v jni/ubuntu.exe bin\n\t@echo \"ubuntu.exe done\"\n\nubuntu.exe2: prepare_bin_target\n\t$(Q)cd jni; $(MAKE) --no-print-directory -f Ubuntu.mk ubuntu.exe2\n\t@cp -v jni/ubuntu.exe2 bin\n\nconnectal.so: prepare_bin_target\nifneq ($(OS),android)\n\t$(Q)cd jni; $(MAKE) --no-print-directory -f Ubuntu.mk connectal.so\n\t@cp -v jni/connectal.so bin\nelse\n\t+ndk-build $(CONNECTAL_NDK_PARAM)\n\t@cp -v libs/armeabi/libconnectal.so bin/connectal.so\nendif\n\t$(Q)if [ -f $(BINFILE) ] ; then $(OBJCOPY) --remove-section fpgadata bin/connectal.so; fi\n\t$(Q)if [ -f $(BINFILE) ] ; then $(OBJCOPY) --add-section fpgadata=$(BINFILE) bin/connectal.so; fi\n\nifneq ($(BOARD),bluesim)\nifneq ($(OS),android)\nprogram:\n\tfpgajtag bin/mkTop.bin.gz\n\tsleep 1\n\nprogramflash:\n\tvivado -mode batch -source $(dir $(FPGAMAKE))/tcl/program_bpi_flash.tcl\nendif\nendif\n\nifneq ($(CONNECTAL_NOHARDWARE),1)\nBITS_DEPENDENCES ?= $(CONNECTAL_BITS_DEPENDENCES)\nendif #hw/mkTop.bit prepare_bin_target\n\nbits: $(BITS_DEPENDENCES) prepare_bin_target\nifneq ($(XILINX),)\nifeq ($(OS),android)\n\t@echo \"zipping android\"\n\t$(CONNECTALDIR)/scripts/reorderbytes.py hw/mkTop.bin bin/mkTop.xdevcfg.bin\n\tgzip -f bin/mkTop.xdevcfg.bin\nelse\nifneq ($(SIMULATION),)\n\t@echo \"not zipping xilinx\"\nelse\nifneq ($(AWSF1),)\n\t@echo \"not zipping awsf1\"\nelse\n\t@echo \"zipping xilinx\"\n\tgzip -c hw/mkTop.bin > bin/mkTop.bin.gz\nendif # AWSF1\nendif #xsim\nendif #android\nelse #!xilinx\nifneq ($(ALTERA),)\n\tgzip -c $(MKTOP).sof > bin/$(MKTOP).sof.gz\nendif #\nendif #!xilinx\n\t$(Q)if [ -f bin/$(EXENAME) -a -f \"$(BINFILE)\" ]; then $(OBJCOPY) --remove-section fpgadata bin/$(EXENAME); fi\n\t$(Q)if [ -f bin/$(EXENAME) -a -f \"$(BINFILE)\" ]; then $(OBJCOPY) --add-section fpgadata=$(BINFILE) bin/$(EXENAME); fi\n\t$(Q)if [ -f Impl/TopDown/top-post-route.dcp ]; then cp -f Impl/TopDown/top-post-route.dcp bin; fi\n\t$(Q)if [ -f Impl/TopDown/top-post-route-timing-summary.rpt ]; then $(CONNECTALDIR)/scripts/check-timing.py Impl/TopDown/top-post-route-timing-summary.rpt; fi\n\t$(Q)if [ -f Impl/TopDown/top-post-route-timing-summary.txt ]; then $(CONNECTALDIR)/scripts/check-timing.py Impl/TopDown/top-post-route-timing-summary.txt; fi\n\nandroid.exe: prepare_bin_target\n\t+ndk-build $(CONNECTAL_NDK_PARAM)\n\t@cp -fv libs/armeabi/android.exe bin\n\t$(Q)if [ -f bin/mkTop.xdevcfg.bin.gz ]; then $(NDK_OBJCOPY) --remove-section fpgadata bin/android.exe; fi\n\t$(Q)if [ -f bin/mkTop.xdevcfg.bin.gz ]; then $(NDK_OBJCOPY) --add-section fpgadata=bin/mkTop.xdevcfg.bin.gz bin/android.exe; fi\n\nandroid.debug.exe: prepare_bin_target\n\t+ndk-build $(CONNECTAL_NDK_PARAM) -B V=1 NDK_DEBUG=1\n\t@cp -v libs/armeabi/android.exe bin\n\t$(Q)if [ -f bin/mkTop.xdevcfg.bin.gz ]; then $(NDK_OBJCOPY) --remove-section fpgadata bin/android.exe; fi\n\t$(Q)if [ -f bin/mkTop.xdevcfg.bin.gz ]; then $(NDK_OBJCOPY) --add-section fpgadata=bin/mkTop.xdevcfg.bin.gz bin/android.exe; fi\n    \nandroid.exe2: prepare_bin_target\n\t+ndk-build $(CONNECTAL_NDK_PARAM)\n\t@cp -fv libs/armeabi/android.exe2 bin\n\nRUN_SCRIPT?=$(CONNECTAL_RUN_SCRIPT)\n\nrun:\nifeq ($(CONNECTAL_SHARED),1)\n\t$(RUN_BSC_LM_LICENSE_FILE) $(GDB) $(RUN_SCRIPT) ./bin/$(EXENAME2) $(RUN_ARGS); retcode=$$?; exit $$retcode\nelse\n    ifeq ($(RUNSOURCE2),)\n\t$(RUN_BSC_LM_LICENSE_FILE) $(GDB) $(RUN_SCRIPT) ./bin/$(EXENAME) $(RUN_ARGS); retcode=$$?; exit $$retcode\n    else\n\t$(RUN_BSC_LM_LICENSE_FILE) $(GDB2) $(RUN_SCRIPT) ./bin/$(EXENAME2)& bsim2pid=$$!; $(RUN_SCRIPT) $(GDB) ./bin/$(EXENAME) $(RUN_ARGS); retcode=$$?; kill $$bsim2pid; exit $$retcode\n    endif\nendif # CONNECTAL_SHARED\n\n\ndefine SIM_C_RULE\n$1/$(notdir $(basename $3)).o: $3\n\tmkdir -p $1\n\t$(CC) -c $2 -o $1/$(notdir $(basename $3)).o $3\nendef\ndefine SIM_CXX_RULE\n$1/$(notdir $(basename $3)).o: $3\n\tmkdir -p $1\n\t$(CXX) -c $2 -o $1/$(notdir $(basename $3)).o $3\nendef\n\n$(foreach src, $(filter %.c, $(SIM_CXX_LOCAL) $(SIM_CXX_PROJECT)), $(eval $(call SIM_C_RULE, $(DTOP)/lib, $(SIM_CFLAGS), $(src))))\n$(foreach src, $(filter %.cpp, $(SIM_CXX_LOCAL) $(SIM_CXX_PROJECT)), $(eval $(call SIM_CXX_RULE, $(DTOP)/lib, $(SIM_CXXFLAGS), $(src))))\nSIM_OBJECTS = $(addprefix $(DTOP)/lib/, $(addsuffix .o, $(basename $(notdir $(SIM_CXX_LOCAL) $(SIM_CXX_PROJECT)))))\n\nVIVADODIR=$(realpath $(shell dirname $(VIVADO))/..)\nXSC_CFLAGS= -Wa,-W -fPIC -m64  -I\"$(VIVADODIR)/data/xsim/include\" -DSYSTEM_VERILOG -DBOARD_xsim -I$(CONNECTALDIR)/cpp -I$(CONNECTALDIR) -Ijni\n\nXVLOGDEFINES = $(subst -D,-d,$(BSVDEFINES))\n\nSVLOG = $(addprefix -svlog $(CONNECTALDIR)/verilog/, xsimtop.sv XsimDmaReadWrite.sv XsimLink.sv XsimSink.sv XsimSource.sv)\n\nXCIDIRS = $(basename $(XCIFILES))\nVLOG_PRJ_FILE = $(wildcard $(addsuffix /xsim/vlog.prj, $(XCIDIRS)))\nVHDL_PRJ_FILE = $(wildcard $(addsuffix /xsim/vhdl.prj, $(XCIDIRS)))\n# phony targets to trigger calls to xvlog and xvhdl\nVLOG_PRJ_BLD  = $(addsuffix .bld, $(VLOG_PRJ_FILE))\nVHDL_PRJ_BLD  = $(addsuffix .bld, $(VHDL_PRJ_FILE))\n\n%/vlog.prj.bld: %/vlog.prj\n\tsed -i s/xil_defaultlib/work/ $(*)/vlog.prj\n\txvlog $(XVLOGFLAGS) -prj $(*)/vlog.prj\n\n%/vhdl.prj.bld: %/vhdl.prj\n\tsed -i s/xil_defaultlib/work/ $(*)/vhdl.prj\n\txvhdl $(XVLOGFLAGS) -prj $(*)/vhdl.prj\n\nxsim: verilog $(SIM_OBJECTS) $(VLOG_PRJ_BLD) $(VHDL_PRJ_BLD)\n\txvlog $(XVLOGFLAGS) $(XVLOGDEFINES) $(VERILOG_PATH:%=--sourcelibdir %) --sourcelibext .v verilog/*.v $(VERILOG_FILES)\nifneq ($(VHDL_FILES),)\n\txvhdl $(XVHDLFLAGS) $(VHDL_FILES)\nendif\n\txvlog $(XVLOGDEFINES) --sv $(CONNECTALDIR)/verilog/*.sv ## not needed because these all get passed to xelab because they use DPI\n\tls -l $(SIM_OBJECTS)\n\txsc -v  -cc gcc -link $(SIM_OBJECTS) -o xsimtop || echo xsc failed\n\txelab -timescale 1ns/1ps --stats $(XVLOGDEFINES) -cc gcc $(SVLOG) --dpiheader XsimTop.h --debug wave -L unisim -L unifast -L unimacro work.xsimtop -sv_lib xsimtop || echo xelab failed\n\ttrue\n\nCVC64 ?= cvc64\nCVC_DEFINES = $(addprefix +define+, $(BSVDEFINES_LIST))\nCVC_TRACE_ARGS = +printstats +fstvars\nCVC_ARGS ?= \nCVC_SOURCES = $(addprefix -v , $(wildcard $(BLUESPECDIR)/Verilog/*.v $(DTOP)/verilog/*.v))\ncvcsim: bin/cvcsim\n\nbin/cvcsim: $(DTOP)/bin/libconnectal-sim.so verilog bin/cvcsim\n\t$(CVC64) $(CVC_DEFINES) $(CVC_ARGS) -y $(CONNECTALDIR)/verilog $(CVC_SOURCES) -sv $(CONNECTALDIR)/verilog/XsimSink.sv  $(CONNECTALDIR)/verilog/XsimSource.sv $(CONNECTALDIR)/verilog/XsimDmaReadWrite.sv -sv $(CONNECTALDIR)/verilog/xsimtop.sv -sv_lib $(DTOP)/bin/libconnectal-sim.so -o bin/cvcsim\n\nvlsim:  $(DTOP)/obj_dir/vlsim\n\nVERILATOR_ARGS?= -O3 -CFLAGS \"-I$(CONNECTALDIR)/cpp -I$(DTOP)/jni -O $(PROF_FLAGS)\" -LDFLAGS \"-O $(PROF_FLAGS)\" --profile-cfuncs --output-split 20000\nVERILATOR_ARGS += $(VERILATOR_PROJECT_ARGS)\n\n$(DTOP)/obj_dir/vlsim.mk: $(DTOP)/bin/libconnectal-sim.so verilog\n\trm -fr $(DTOP)/obj_dir\n\tverilator -o vlsim --prefix vlsim $(VERILATOR_ARGS) -cc -exe $(DTOP)/verilog/mkXsimTop.v -DMainClockPeriod=4 -DDerivedClockPeriod=4 --top-module mkXsimTop $(VERILOG_PATH:%=-y %) -Wno-fatal $(CONNECTALDIR)/cpp/verilatortop.cpp -LDFLAGS -L$(DTOP)/bin\n\n$(DTOP)/obj_dir/vlsim: $(DTOP)/obj_dir/vlsim.mk\n\t+$(MAKE) USER_LDLIBS=\"-lconnectal-sim -lpthread\" VM_PARALLEL_BUILDS=1 -C obj_dir -f vlsim.mk\n\tcp obj_dir/vlsim bin/vlsim\n\nvcssim:  bin/simv\n\nVCS_DEFINES = $(addprefix +define+, $(BSVDEFINES_LIST))\nVCS_ARGS?= -CFLAGS \"-I$(CONNECTALDIR)/cpp -I$(CONNECTALDIR) -I$(DTOP)/jni\"\nVCS_ARGS += +define+SVA_ON -assert svaext+enable_diag\nVCS_ARGS += -debug_acc+all\nVCS_ARGS += -kdb -fsdb\nVCS_ARGS += $(VCS_PROJECT_ARGS)\n\nbin/simv: $(DTOP)/bin/libconnectal-sim.so verilog\n\tvcs -full64  -sverilog $(VCS_DEFINES) $(VCS_ARGS) -o $(DTOP)/bin/simv \\\n\t\t$(CONNECTALDIR)/verilog/xsimtop.sv $(SIM_CXX_LOCAL) \\\n\t\t+libext+.v+.sv $(VERILOG_PATH:%=-y %)\n\nMODELSIMDIR=$(realpath $(dir $(MODELSIM))/..)\nVSIM_CFLAGS= $(CFLAGS_PROJECT) -Wa,-W -fPIC -m64 -I\"$(MODELSIMDIR)/include\" -DSYSTEM_VERILOG -DBOARD_vsim -I$(CONNECTALDIR)/cpp -I$(CONNECTALDIR) -Ijni\nVSIM_CXXFLAGS= $(CXXFLAGS_PROJECT) -Wa,-W -fPIC -m64 -I\"$(MODELSIMDIR)/include\" -DSYSTEM_VERILOG -DBOARD_vsim -I$(CONNECTALDIR)/cpp -I$(CONNECTALDIR) -Ijni\n\n$(foreach src, $(filter %.c, $(SIM_CXX_LOCAL) $(SIM_CXX_PROJECT)), $(eval $(call SIM_C_RULE, vsim.dir/xsc, $(VSIM_CFLAGS), $(src))))\n$(foreach src, $(filter %.cpp, $(SIM_CXX_LOCAL) $(SIM_CXX_PROJECT)), $(eval $(call SIM_CXX_RULE, vsim.dir/xsc, $(VSIM_CXXFLAGS), $(src))))\nVSIM_OBJECTS = $(addprefix vsim.dir/xsc/, $(addsuffix .o, $(basename $(notdir $(SIM_CXX_LOCAL) $(SIM_CXX_PROJECT)))))\n\nVSIM_DEFINES = $(subst -D ,+define+,$(BSVDEFINES))\nVSIM_SV = $(addprefix -sv $(CONNECTALDIR)/verilog/, xsimtop.sv XsimDmaReadWrite.sv XsimLink.sv XsimSink.sv XsimSource.sv)\nSV_SEARCH_PATH = $(addprefix -y , $(VERILOG_PATH))\nSV_SEARCH_PATH += $(addprefix -y , $(addsuffix /submodules, $(VERILOG_PATH)))\nSV_SEARCH_PATH += $(addprefix -y , $(addsuffix /submodules/mentor, $(VERILOG_PATH)))\nVSIM_LIBRARY_FILES += $(addprefix -sv $(QUARTUSDIR)/eda/sim_lib/, altera_lnsim.sv)\nVSIM_LIBRARY_FILES += $(addprefix -v $(QUARTUSDIR)/eda/sim_lib/, altera_mf.v 220model.v sgate.v altera_primitives.v mentor/stratixv_atoms_ncrypt.v stratixv_atoms.v mentor/stratixv_hssi_atoms_ncrypt.v stratixv_hssi_atoms.v)\nVSIM_MISC_FILES = $(addprefix -sv , $(MODELSIM_FILES))\n\nvsim: verilog $(VSIM_OBJECTS)\n\trm -rf work\n\tvlib work\n\tvlog -timescale 1ns/1ps -dpiheader XsimTop.h $(VSIM_DEFINES) $(VSIM_SV) $(VSIM_LIBRARY_FILES) $(VSIM_MISC_FILES) +libext+.sv+.v $(SV_SEARCH_PATH) $(VERILOG_PATH:%=-y %) -sv verilog/*.v\n\t$(CXX) $(CXXFLAGS_PROJECT) -O -g -I$(DTOP)/jni -shared -fPIC -g -o xsimtop.so $(VSIM_OBJECTS)\n\nobj/%.bvi: verilog/%.v\n\t$(CONNECTALDIR)/scripts/extract-bvi-schedule.py -d obj verilog/$(*).v\n\ndefine BSV_BO_RULE\n$(1): $(2) $(3) $(4)\n\t$(Q)mkdir -p $(DTOP)/obj verilog\n\t@echo BSV_BO  [$(2)]\n\t$(Q)MAKEFLAGS=\"\" $(RUN_BSC) $(2)\nendef\n\ndefine BSV_V_RULE\n$(2): $(3) $(4) $(5)\n\t$(Q)mkdir -p $(DTOP)/obj verilog\n\t@echo BSCVERILOG [$(1)]\n\tcd generatedbsv; MAKEFLAGS=\"\" $(RUN_BSC) -g $(1) $(3)\n\t$(Q)sed -i 's|// On .*|// timestamp removed|' verilog/*.v\n\t$(Q)sed -i 's|Prelude_inst_changeSpecialWires|csw|g' verilog/*.v\n\t$(Q)sed -i 's|  reg.*PROBE[,;]|(* mark_debug=\"true\" *)&|' verilog/*.v \n\t$(Q)sed -i 's|  wire.*PROBE[,;]|(* mark_debug=\"true\" *)&|' verilog/*.v \n\t$(Q)sed -i 's|  wire.*PROBE_VALID[,;]|(* mark_debug=\"true\" *)&|' verilog/*.v \nendef\n\ninclude obj/Makefile\n\nobj/mkXsimTop.ba: $(addprefix obj/, $(patsubst %.bsv, %.bo, $(notdir $(TOPBSVFILE))))\n\t$(Q)mkdir -p $(DTOP)/obj\n\t@echo BSCSIM [mkXsimTop.ba]\n\t$(Q)cd generatedbsv; MAKEFLAGS=\"\" $(RUN_BSC) -g $(MKTOP) $(TOPBSVFILE)\n\n$(VFILE): $(addprefix obj/, $(patsubst %.bsv, %.bo, $(notdir $(TOPBSVFILE))))\n\t$(Q)mkdir -p verilog $(DTOP)/obj\n\t@echo BSCVERILOG [$(VFILE)]\n\t$(Q)cd generatedbsv; MAKEFLAGS=\"\" $(RUN_BSC) -g $(MKTOP) $(TOPBSVFILE)\n\t$(Q)sed -i 's|// On .*|// timestamp removed|' verilog/*.v\n\t$(Q)sed -i 's|Prelude_inst_changeSpecialWires|csw|g' verilog/*.v\n\t$(Q)sed -i 's|  reg.*PROBE[,;]|(* mark_debug=\"true\" *)&|' verilog/*.v \n\t$(Q)sed -i 's|  wire.*PROBE[,;]|(* mark_debug=\"true\" *)&|' verilog/*.v \n\t$(Q)sed -i 's|  wire.*PROBE_VALID[,;]|(* mark_debug=\"true\" *)&|' verilog/*.v\n\t$(Q)sed -i '/assign/{N; s|^\\s*assign\\s\\+CLK_.*_deleteme_unused_clock =.*;|\\/\\/deleteme CLK ports disconnected from nets|}' verilog/$(MKTOP).v\n\nobj/Makefile: $(OBJMAKEFILE_DEP) syntax.timestamp\n\t@mkdir -p obj\n\t$(CONNECTALDIR)/scripts/bsvdepend.py -o obj/Makefile $(BSVDEFINES) --bsvpath=$(BSVPATH) --bluespecdir=$(BLUESPECDIR) --all $(TOPBSVFILE)\n\n$(DTOP)/bin/libconnectal-sim.so: $(SIM_OBJECTS) prepare_bin_target\n\t$(Q)mkdir -p $(DTOP)/bin\n\t$(CXX) -O -g -I$(DTOP)/jni -shared -fpic $(SIM_CXXFLAGS) -g -o $(DTOP)/bin/libconnectal-sim.so $(SIM_OBJECTS)\n\nbsim: prepare_bin_target $(DTOP)/bin/libconnectal-sim.so obj/mkXsimTop.ba\n\t$(Q)mkdir -p $(DTOP)/obj verilog\n\t@echo BSCBSIM [$(DTOP)]\n\t$(Q)cd generatedbsv; MAKEFLAGS=\"\" $(RUN_BSC) -O -L $(DTOP)/bin  -l connectal-sim -sim -e $(MKTOP) -o bsim $(DTOP)/obj/*.ba\n\tg++ -O -g $(CXXFLAGS_BSIM) -o bin/bsim -Iobj -I$(BLUESPECDIR)/Bluesim obj/*.o $(CONNECTALDIR)/cpp/bluesim_main.cxx -L$(BSIM_LIBRARY_DIR) -lbskernel -lbsprim -lpthread -L bin -lconnectal-sim\n\n\nbuild/checkpoints/to_aws/mkTop.SH_CL_routed.dcp: verilog\n\tCONNECTALDIR=$(CONNECTALDIR) $(CONNECTALDIR)/scripts/aws/build.sh $(AWSFLAGS)\n\nsyntax.timestamp: $(BSVFILES)\n\t@#$syntax.py uses environment variables: V INTERFACES BSVDEFINES_LIST DTOP DUT_NAME\n\t$(Q)BSVPATH=$(BSVPATH) $(CONNECTALDIR)/scripts/syntax.py $(BSVFILES)\n\t$(Q)touch syntax.timestamp\n\nverilog: $(VFILE) syntax.timestamp\n\t@echo \"verilog\"\n\nlint: $(VFILE)\n\tverilator --error-limit 200 --lint-only -Igeneratedbsv -Igeneratedbsv/source $(VFILE)\n\nprepare_bin_target: syntax.timestamp\n\t@echo \"prepare_bin_target\"\n\t@mkdir -p bin jni\n\t@(git rev-parse HEAD 2> /dev/null || echo not a git repo) > bin/githash\n\t@(git diff 2>/dev/null || echo not a git repo) | gzip -c > bin/gitdiff.patch.gz\n\nhwclean:\n\trm -fr obj hw vivado*.jou vivado*.log fsm_encoding.os .Xil\n\nclean: hwclean\n\trm -fr verilog\n\n"
  },
  {
    "path": "scripts/adb/LICENSE",
    "content": "\n                                 Apache License\n                           Version 2.0, January 2004\n                        http://www.apache.org/licenses/\n\n   TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION\n\n   1. Definitions.\n\n      \"License\" shall mean the terms and conditions for use, reproduction,\n      and distribution as defined by Sections 1 through 9 of this document.\n\n      \"Licensor\" shall mean the copyright owner or entity authorized by\n      the copyright owner that is granting the License.\n\n      \"Legal Entity\" shall mean the union of the acting entity and all\n      other entities that control, are controlled by, or are under common\n      control with that entity. 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  },
  {
    "path": "scripts/adb/README.rst",
    "content": "python-adb\n==========\n\nThis repository contains a pure-python implementation of the ADB and Fastboot\nprotocols, using libusb1 for USB communications.\n\nThis is a complete replacement and rearchitecture of the Android project's ADB\nand fastboot code available at\nhttps://github.com/android/platform_system_core/tree/master/adb\n\nThis code is mainly targeted to users that need to communicate with Android\ndevices in an automated fashion, such as in automated testing. It does not have\na daemon between the client and the device, and therefore does not support\nmultiple simultaneous commands to the same device. It does support any number of\ndevices and never communicates with a device that it wasn't intended to, unlike\nthe Android project's ADB.\n\nPros:\n  * Simpler code due to use of libusb1 and Python.\n  * API can be used by other Python code easily.\n  * Errors are propagated with tracebacks, helping debug connectivity issues.\n\nCons:\n  * Technically slower due to Python, mitigated by no daemon.\n  * Only one command per device at a time.\n  * More dependencies than Android's ADB.\n\nDependencies:\n  * libusb1 (1.0.16+)\n  * python-libusb1 (1.2.0+)\n  * python-progressbar (for fastboot_debug, 2.3+)\n  * python-m2crypto (0.21.1+)\n\n"
  },
  {
    "path": "scripts/adb/__init__.py",
    "content": ""
  },
  {
    "path": "scripts/adb/adb_commands.py",
    "content": "# Copyright 2014 Google Inc. All rights reserved.\n#\n# Licensed under the Apache License, Version 2.0 (the \"License\");\n# you may not use this file except in compliance with the License.\n# You may obtain a copy of the License at\n#\n#     http://www.apache.org/licenses/LICENSE-2.0\n#\n# Unless required by applicable law or agreed to in writing, software\n# distributed under the License is distributed on an \"AS IS\" BASIS,\n# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n# See the License for the specific language governing permissions and\n# limitations under the License.\n\"\"\"A libusb1-based ADB reimplementation.\n\nADB was giving us trouble with its client/server architecture, which is great\nfor users and developers, but not so great for reliable scripting. This will\nallow us to more easily catch errors as Python exceptions instead of checking\nrandom exit codes, and all the other great benefits from not going through\nsubprocess and a network socket.\n\nAll timeouts are in milliseconds.\n\"\"\"\n\ntry:\n  import cStringIO\nexcept ImportError:\n  import io as cStringIO  # Python 3 compatibility\nimport os\nimport socket\n\nfrom . import adb_protocol\nfrom . import common\nfrom . import filesync_protocol\n\ntry:\n    basestring\nexcept NameError:\n    basestring = str  # Python 3 compatibility\n\ntry:\n    import libusb1\n    # From adb.h\n    CLASS = 0xFF\n    SUBCLASS = 0x42\n    PROTOCOL = 0x01\n    # pylint: disable=invalid-name\n    DeviceIsAvailable = common.InterfaceMatcher(CLASS, SUBCLASS, PROTOCOL)\nexcept:\n    # no libusb1 support\n    pass\n\ntry:\n    from M2Crypto import RSA\n\n    class M2CryptoSigner(adb_protocol.AuthSigner):\n      \"\"\"AuthSigner using M2Crypto.\"\"\"\n\n      def __init__(self, rsa_key_path):\n        with open(rsa_key_path + '.pub') as rsa_pub_file:\n          self.public_key = rsa_pub_file.read()\n\n        self.rsa_key = RSA.load_key(rsa_key_path)\n\n      def Sign(self, data):\n        return self.rsa_key.sign(data, 'sha1')\n\n      def GetPublicKey(self):\n        return self.public_key\nexcept:\n  #print 'Install M2Crypto in order to use adb debug'\n  pass\n\nclass AdbCommands(object):\n  \"\"\"Exposes adb-like methods for use.\n\n  Some methods are more-pythonic and/or have more options.\n  \"\"\"\n  protocol_handler = adb_protocol.AdbMessage\n  filesync_handler = filesync_protocol.FilesyncProtocol\n\n  @classmethod\n  def ConnectDevice(\n      cls, port_path=None, serial=None, default_timeout_ms=None, **kwargs):\n    \"\"\"Convenience function to get an adb device from usb path or serial.\n    \n    Args:\n      port_path: The filename of usb port to use.\n      serial: The serial number of the device to use.\n      default_timeout_ms: The default timeout in milliseconds to use.\n\n    If serial specifies a TCP address:port, then a TCP connection is\n    used instead of a USB connection.\n    \"\"\"\n    if serial and ':' in serial:\n        handle = common.TcpHandle(serial)\n    else:\n        handle = common.UsbHandle.FindAndOpen(\n            DeviceIsAvailable, port_path=port_path, serial=serial,\n            timeout_ms=default_timeout_ms)\n    return cls.Connect(handle, **kwargs)\n\n  def __init__(self, handle, device_state):\n    self._handle = handle\n    self._device_state = device_state\n\n  @property\n  def usb_handle(self):\n    return self._handle\n\n  def Close(self):\n    self._handle.Close()\n\n  @classmethod\n  def Connect(cls, usb, banner=None, **kwargs):\n    \"\"\"Connect to the device.\n\n    Args:\n      usb: UsbHandle or TcpHandle instance to use.\n      banner: See protocol_handler.Connect.\n      **kwargs: See protocol_handler.Connect for kwargs. Includes rsa_keys,\n          and auth_timeout_ms.\n    Returns:\n      An instance of this class if the device connected successfully.\n    \"\"\"\n    if not banner:\n      banner = socket.gethostname()\n    device_state = cls.protocol_handler.Connect(usb, banner=banner, **kwargs)\n    # Remove banner and colons after device state (state::banner)\n    device_state = device_state.split(':')[0]\n    return cls(usb, device_state)\n\n  @classmethod\n  def Devices(cls):\n    \"\"\"Get a generator of UsbHandle for devices available.\"\"\"\n    return common.UsbHandle.FindDevices(DeviceIsAvailable)\n\n  def GetState(self):\n    return self._device_state\n\n  def Install(self, apk_path, destination_dir=None, timeout_ms=None):\n    \"\"\"Install apk to device.\n\n    Doesn't support verifier file, instead allows destination directory to be\n    overridden.\n\n    Arguments:\n      apk_path: Local path to apk to install.\n      destination_dir: Optional destination directory. Use /system/app/ for\n        persistent applications.\n      timeout_ms: Expected timeout for pushing and installing.\n\n    Returns:\n      The pm install output.\n    \"\"\"\n    if not destination_dir:\n      destination_dir = '/data/local/tmp/'\n    basename = os.path.basename(apk_path)\n    destination_path = destination_dir + basename\n    self.Push(apk_path, destination_path, timeout_ms=timeout_ms)\n    return self.Shell('pm install -r \"%s\"' % destination_path,\n                      timeout_ms=timeout_ms)\n\n  def Push(self, source_file, device_filename, mtime='0', timeout_ms=None):\n    \"\"\"Push source_file to file on device.\n\n    Arguments:\n      source_file: Either a filename or file-like object to push to the device.\n      device_filename: The filename on the device to write to.\n      mtime: Optional, modification time to set on the file.\n      timeout_ms: Expected timeout for any part of the push.\n    \"\"\"\n    connection = self.protocol_handler.Open(\n        self._handle, destination='sync:',\n        timeout_ms=timeout_ms)\n    if isinstance(source_file, basestring):\n      source_file = open(source_file)\n    self.filesync_handler.Push(connection, source_file, device_filename,\n                               mtime=int(mtime))\n    connection.Close()\n\n  def Pull(self, device_filename, dest_file=None, timeout_ms=None):\n    \"\"\"Pull file from device.\n\n    Arguments:\n      device_filename: The filename on the device to pull.\n      dest_file: If set, a filename or writable file-like object.\n      timeout_ms: Expected timeout for any part of the pull.\n\n    Returns:\n      The file data if dest_file is not set.\n    \"\"\"\n    if isinstance(dest_file, basestring):\n      dest_file = open(dest_file, 'w')\n    elif not dest_file:\n      dest_file = cStringIO.StringIO()\n    connection = self.protocol_handler.Open(\n        self._handle, destination='sync:',\n        timeout_ms=timeout_ms)\n    self.filesync_handler.Pull(connection, device_filename, dest_file)\n    connection.Close()\n    try:\n      # An empty call to cStringIO.StringIO returns an instance of\n      # cStringIO.OutputType on Python 2.\n      StringIOType = cStringIO.OutputType\n    except AttributeError:\n      # On Python 3, this object just an instance of StringIO.\n      StringIOType = cStringIO.StringIO\n    if isinstance(dest_file, StringIOType):\n      return dest_file.getvalue()\n\n  def Stat(self, device_filename):\n    \"\"\"Get a file's stat() information.\"\"\"\n    connection = self.protocol_handler.Open(self._handle, destination='sync:')\n    mode, size, mtime = self.filesync_handler.Stat(\n        connection, device_filename)\n    connection.Close()\n    return mode, size, mtime\n\n  def List(self, device_path):\n    \"\"\"Return a directory listing of the given path.\"\"\"\n    connection = self.protocol_handler.Open(self._handle, destination='sync:')\n    listing = self.filesync_handler.List(connection, device_path)\n    connection.Close()\n    return listing\n\n  def Reboot(self, destination=''):\n    \"\"\"Reboot device, specify 'bootloader' for fastboot.\"\"\"\n    self.protocol_handler.Open(self._handle, 'reboot:%s' % destination)\n\n  def RebootBootloader(self):\n    \"\"\"Reboot device into fastboot.\"\"\"\n    self.Reboot('bootloader')\n\n  def Remount(self):\n    \"\"\"Remount / as read-write.\"\"\"\n    return self.protocol_handler.Command(self._handle, service='remount')\n\n  def Root(self):\n    \"\"\"Restart adbd as root on device.\"\"\"\n    return self.protocol_handler.Command(self._handle, service='root')\n\n  def Shell(self, command, timeout_ms=None):\n    \"\"\"Run command on the device, returning the output.\"\"\"\n    return self.protocol_handler.Command(\n        self._handle, service='shell', command=command,\n        timeout_ms=timeout_ms)\n\n  def StreamingShell(self, command, timeout_ms=None):\n    \"\"\"Run command on the device, returning the output.\n\n    Args:\n      command: the command to run on the target.\n      timeout_ms: Maximum time to allow the command to run.\n\n    Yields:\n      The responses from the shell command.\n    \"\"\"\n    return self.protocol_handler.StreamingCommand(\n        self._handle, service='shell', command=command,\n        timeout_ms=timeout_ms)\n\n  def Logcat(self, options, timeout_ms=None):\n    \"\"\"Run 'shell logcat' and stream the output to stdout.\"\"\"\n    return self.protocol_handler.StreamingCommand(\n        self._handle, service='shell', command='logcat %s' % options,\n        timeout_ms=timeout_ms)\n"
  },
  {
    "path": "scripts/adb/adb_debug.py",
    "content": "# Copyright 2014 Google Inc. All rights reserved.\n#\n# Licensed under the Apache License, Version 2.0 (the \"License\");\n# you may not use this file except in compliance with the License.\n# You may obtain a copy of the License at\n#\n#     http://www.apache.org/licenses/LICENSE-2.0\n#\n# Unless required by applicable law or agreed to in writing, software\n# distributed under the License is distributed on an \"AS IS\" BASIS,\n# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n# See the License for the specific language governing permissions and\n# limitations under the License.\n\"\"\"ADB debugging binary.\n\nCall it similar to how you call android's adb. Takes either --serial or\n--port_path to connect to a device.\n\"\"\"\nfrom __future__ import print_function\n\nimport os\nimport sys\n\nimport gflags\n\nfrom . import adb_commands\nfrom . import common_cli\n\ngflags.ADOPT_module_key_flags(common_cli)\n\ngflags.DEFINE_multistring('rsa_key_path', '~/.android/adbkey',\n                         'RSA key(s) to use')\ngflags.DEFINE_integer('auth_timeout_s', 60,\n                     'Seconds to wait for the dialog to be accepted when using '\n                     'authenticated ADB.')\nFLAGS = gflags.FLAGS\n\n\ndef GetRSAKwargs():\n  if FLAGS.rsa_key_path:\n    try:\n      return {\n        'rsa_keys': [adb_commands.M2CryptoSigner(os.path.expanduser(path))\n                     for path in FLAGS.rsa_key_path],\n        'auth_timeout_ms': int(FLAGS.auth_timeout_s * 1000.0),\n        }\n    except:\n        print('Install M2Crypto in order to use adb debug')\n  return {}\n\n\ndef main(argv):\n  common_cli.StartCli(\n      argv, adb_commands.AdbCommands.ConnectDevice,\n      list_callback=adb_commands.AdbCommands.Devices, **GetRSAKwargs())\n\n\nif __name__ == '__main__':\n  main(FLAGS(sys.argv))\n"
  },
  {
    "path": "scripts/adb/adb_protocol.py",
    "content": "# Copyright 2014 Google Inc. All rights reserved.\n#\n# Licensed under the Apache License, Version 2.0 (the \"License\");\n# you may not use this file except in compliance with the License.\n# You may obtain a copy of the License at\n#\n#     http://www.apache.org/licenses/LICENSE-2.0\n#\n# Unless required by applicable law or agreed to in writing, software\n# distributed under the License is distributed on an \"AS IS\" BASIS,\n# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n# See the License for the specific language governing permissions and\n# limitations under the License.\n\"\"\"ADB protocol implementation.\n\nImplements the ADB protocol as seen in android's adb/adbd binaries, but only the\nhost side.\n\"\"\"\n\nimport struct\nimport time\n\nfrom . import usb_exceptions\n\n\n# Maximum amount of data in an ADB packet.\nMAX_ADB_DATA = 4096\n# ADB protocol version.\nVERSION = 0x01000000\n\n# AUTH constants for arg0.\nAUTH_TOKEN = 1\nAUTH_SIGNATURE = 2\nAUTH_RSAPUBLICKEY = 3\n\n\nclass InvalidCommandError(Exception):\n  \"\"\"Got an invalid command over USB.\"\"\"\n\n  def __init__(self, message, response_header, response_data):\n    if response_header == 'FAIL':\n      message = 'Command failed, device said so. (%s)' % message\n    super(InvalidCommandError, self).__init__(\n        message, response_header, response_data)\n\n\nclass InvalidResponseError(Exception):\n  \"\"\"Got an invalid response to our command.\"\"\"\n\n\nclass InvalidChecksumError(Exception):\n  \"\"\"Checksum of data didn't match expected checksum.\"\"\"\n\n\nclass InterleavedDataError(Exception):\n  \"\"\"We only support command sent serially.\"\"\"\n\n\ndef MakeWireIDs(ids):\n  id_to_wire = {\n      cmd_id: sum(ord(c) << (i * 8) for i, c in enumerate(cmd_id))\n      for cmd_id in ids\n  }\n  wire_to_id = {wire: cmd_id for cmd_id, wire in id_to_wire.items()}\n  return id_to_wire, wire_to_id\n\n\nclass AuthSigner(object):\n  \"\"\"Signer for use with authenticated ADB, introduced in 4.4.x/KitKat.\"\"\"\n\n  def Sign(self, data):\n    \"\"\"Signs given data using a private key.\"\"\"\n    raise NotImplementedError()\n\n  def GetPublicKey(self):\n    \"\"\"Returns the public key in PEM format without headers or newlines.\"\"\"\n    raise NotImplementedError()\n\n\nclass _AdbConnection(object):\n  \"\"\"ADB Connection.\"\"\"\n\n  def __init__(self, usb, local_id, remote_id, timeout_ms):\n    self.usb = usb\n    self.local_id = local_id\n    self.remote_id = remote_id\n    self.timeout_ms = timeout_ms\n\n  def _Send(self, command, arg0, arg1, data=''):\n    message = AdbMessage(command, arg0, arg1, data)\n    message.Send(self.usb, self.timeout_ms)\n\n  def Write(self, data):\n    \"\"\"Write a packet and expect an Ack.\"\"\"\n    self._Send('WRTE', arg0=self.local_id, arg1=self.remote_id, data=data)\n    # Expect an ack in response.\n    cmd, okay_data = self.ReadUntil('OKAY')\n    if cmd != 'OKAY':\n      if cmd == 'FAIL':\n        raise usb_exceptions.AdbCommandFailureException(\n            'Command failed.', okay_data)\n      raise InvalidCommandError(\n          'Expected an OKAY in response to a WRITE, got %s (%s)',\n          cmd, okay_data)\n    return len(data)\n\n  def Okay(self):\n    self._Send('OKAY', arg0=self.local_id, arg1=self.remote_id)\n\n  def ReadUntil(self, *expected_cmds):\n    \"\"\"Read a packet, Ack any write packets.\"\"\"\n    cmd, remote_id, local_id, data = AdbMessage.Read(\n        self.usb, expected_cmds, self.timeout_ms)\n    if local_id != 0 and self.local_id != local_id:\n      raise InterleavedDataError(\"We don't support multiple streams...\")\n    if remote_id != 0 and self.remote_id != remote_id:\n      raise InvalidResponseError(\n          'Incorrect remote id, expected %s got %s' % (\n              self.remote_id, remote_id))\n    # Ack write packets.\n    if cmd == 'WRTE':\n      self.Okay()\n    return cmd, data\n\n  def ReadUntilClose(self):\n    \"\"\"Yield packets until a Close packet is received.\"\"\"\n    while True:\n      cmd, data = self.ReadUntil('CLSE', 'WRTE')\n      if cmd == 'CLSE':\n        self._Send('CLSE', arg0=self.local_id, arg1=self.remote_id)\n        break\n      if cmd != 'WRTE':\n        if cmd == 'FAIL':\n          raise usb_exceptions.AdbCommandFailureException(\n              'Command failed.', data)\n        raise InvalidCommandError('Expected a WRITE or a CLOSE, got %s (%s)',\n                                  cmd, data)\n      yield data\n\n  def Close(self):\n    self._Send('CLSE', arg0=self.local_id, arg1=self.remote_id)\n    cmd, data = self.ReadUntil('CLSE')\n    if cmd != 'CLSE':\n      if cmd == 'FAIL':\n        raise usb_exceptions.AdbCommandFailureException('Command failed.', data)\n      raise InvalidCommandError('Expected a CLSE response, got %s (%s)',\n                                cmd, data)\n\n\nclass AdbMessage(object):\n  \"\"\"ADB Protocol and message class.\n\n  Protocol Notes\n\n  local_id/remote_id:\n    Turns out the documentation is host/device ambidextrous, so local_id is the\n    id for 'the sender' and remote_id is for 'the recipient'. So since we're\n    only on the host, we'll re-document with host_id and device_id:\n\n    OPEN(host_id, 0, 'shell:XXX')\n    READY/OKAY(device_id, host_id, '')\n    WRITE(0, host_id, 'data')\n    CLOSE(device_id, host_id, '')\n  \"\"\"\n\n  ids = ['SYNC', 'CNXN', 'AUTH', 'OPEN', 'OKAY', 'CLSE', 'WRTE']\n  commands, constants = MakeWireIDs(ids)\n  # An ADB message is 6 words in little-endian.\n  format = '<6I'\n\n  connections = 0\n\n  def __init__(self, command=None, arg0=None, arg1=None, data=''):\n    self.command = self.commands[command]\n    self.magic = self.command ^ 0xFFFFFFFF\n    self.arg0 = arg0\n    self.arg1 = arg1\n    self.data = data\n\n  @property\n  def checksum(self):\n    return self.CalculateChecksum(self.data)\n\n  @staticmethod\n  def CalculateChecksum(data):\n    # The checksum is just a sum of all the bytes. I swear.\n    return sum(map(ord, data)) & 0xFFFFFFFF\n\n  def Pack(self):\n    \"\"\"Returns this message in an over-the-wire format.\"\"\"\n    return struct.pack(self.format, self.command, self.arg0, self.arg1,\n                       len(self.data), self.checksum, self.magic)\n\n  @classmethod\n  def Unpack(cls, message):\n    try:\n      cmd, arg0, arg1, data_length, data_checksum, unused_magic = struct.unpack(\n          cls.format, message)\n    except struct.error as e:\n      raise ValueError('Unable to unpack ADB command.', cls.format, message, e)\n    return cmd, arg0, arg1, data_length, data_checksum\n\n  def Send(self, usb, timeout_ms=None):\n    \"\"\"Send this message over USB.\"\"\"\n    usb.BulkWrite(self.Pack(), timeout_ms)\n    usb.BulkWrite(self.data, timeout_ms)\n\n  @classmethod\n  def Read(cls, usb, expected_cmds, timeout_ms=None, total_timeout_ms=None):\n    \"\"\"Receive a response from the device.\"\"\"\n    total_timeout_ms = usb.Timeout(total_timeout_ms)\n    start = time.time()\n    while True:\n      msg = usb.BulkRead(24, timeout_ms)\n      cmd, arg0, arg1, data_length, data_checksum = cls.Unpack(msg)\n      command = cls.constants.get(cmd)\n      if not command:\n        raise InvalidCommandError(\n            'Unknown command: %x' % cmd, cmd, (arg0, arg1))\n      if command in expected_cmds:\n        break\n\n      if time.time() - start > total_timeout_ms:\n        raise InvalidCommandError(\n            'Never got one of the expected responses (%s)' % expected_cmds,\n            cmd, (timeout_ms, total_timeout_ms))\n\n    if data_length > 0:\n      data = ''\n      while data_length > 0:\n          temp = usb.BulkRead(data_length, timeout_ms)\n          data += temp\n          data_length -= len(temp)\n      actual_checksum = cls.CalculateChecksum(data)\n      if actual_checksum != data_checksum:\n        raise InvalidChecksumError(\n            'Received checksum %s != %s', (actual_checksum, data_checksum))\n    else:\n      data = ''\n    return command, arg0, arg1, data\n\n  @classmethod\n  def Connect(cls, usb, banner='notadb', rsa_keys=None, auth_timeout_ms=100):\n    \"\"\"Establish a new connection to the device.\n\n    Args:\n      usb: A USBHandle with BulkRead and BulkWrite methods.\n      banner: A string to send as a host identifier.\n      rsa_keys: List of AuthSigner subclass instances to be used for\n          authentication. The device can either accept one of these via the Sign\n          method, or we will send the result of GetPublicKey from the first one\n          if the device doesn't accept any of them.\n      auth_timeout_ms: Timeout to wait for when sending a new public key. This\n          is only relevant when we send a new public key. The device shows a\n          dialog and this timeout is how long to wait for that dialog. If used\n          in automation, this should be low to catch such a case as a failure\n          quickly; while in interactive settings it should be high to allow\n          users to accept the dialog. We default to automation here, so it's low\n          by default.\n\n    Returns:\n      The device's reported banner. Always starts with the state (device,\n          recovery, or sideload), sometimes includes information after a : with\n          various product information.\n\n    Raises:\n      usb_exceptions.DeviceAuthError: When the device expects authentication,\n          but we weren't given any valid keys.\n      InvalidResponseError: When the device does authentication in an\n          unexpected way.\n    \"\"\"\n    msg = cls(\n        command='CNXN', arg0=VERSION, arg1=MAX_ADB_DATA,\n        data='host::%s\\0' % banner)\n    msg.Send(usb)\n    cmd, arg0, arg1, banner = cls.Read(usb, ['CNXN', 'AUTH'])\n    if cmd == 'AUTH':\n      if not rsa_keys:\n        raise usb_exceptions.DeviceAuthError(\n            'Device authentication required, no keys available.')\n      # Loop through our keys, signing the last 'banner' or token.\n      for rsa_key in rsa_keys:\n        if arg0 != AUTH_TOKEN:\n          raise InvalidResponseError(\n              'Unknown AUTH response: %s %s %s' % (arg0, arg1, banner))\n\n        signed_token = rsa_key.Sign(banner)\n        msg = cls(\n            command='AUTH', arg0=AUTH_SIGNATURE, arg1=0, data=signed_token)\n        msg.Send(usb)\n        cmd, arg0, unused_arg1, banner = cls.Read(usb, ['CNXN', 'AUTH'])\n        if cmd == 'CNXN':\n          return banner\n      # None of the keys worked, so send a public key.\n      msg = cls(\n          command='AUTH', arg0=AUTH_RSAPUBLICKEY, arg1=0,\n          data=rsa_keys[0].GetPublicKey() + '\\0')\n      msg.Send(usb)\n      try:\n        cmd, arg0, unused_arg1, banner = cls.Read(\n            usb, ['CNXN'], timeout_ms=auth_timeout_ms)\n      except usb_exceptions.BulkReadFailedError as e:\n        if e.usb_error.value == -7:  # Timeout.\n          raise usb_exceptions.DeviceAuthError(\n              'Accept auth key on device, then retry.')\n        raise\n      # This didn't time-out, so we got a CNXN response.\n      return banner\n    return banner\n\n  @classmethod\n  def Open(cls, usb, destination, timeout_ms=None):\n    \"\"\"Opens a new connection to the device via an OPEN message.\n\n    Not the same as the posix 'open' or any other google3 Open methods.\n\n    Args:\n      usb: USB device handle with BulkRead and BulkWrite methods.\n      destination: The service:command string.\n      timeout_ms: Timeout in milliseconds for USB packets.\n\n    Raises:\n      InvalidResponseError: Wrong local_id sent to us.\n      InvalidCommandError: Didn't get a ready response.\n\n    Returns:\n      The local connection id.\n    \"\"\"\n    local_id = 1\n    msg = cls(\n        command='OPEN', arg0=local_id, arg1=0,\n        data=destination + '\\0')\n    msg.Send(usb, timeout_ms)\n    cmd, remote_id, their_local_id, _ = cls.Read(usb, ['CLSE', 'OKAY'],\n                                                 timeout_ms=timeout_ms)\n    if local_id != their_local_id:\n      raise InvalidResponseError(\n          'Expected the local_id to be %s, got %s' % (local_id, their_local_id))\n    if cmd == 'CLSE':\n      # Device doesn't support this service.\n      return None\n    if cmd != 'OKAY':\n      raise InvalidCommandError('Expected a ready response, got %s' % cmd,\n                                cmd, (remote_id, their_local_id))\n    return _AdbConnection(usb, local_id, remote_id, timeout_ms)\n\n  @classmethod\n  def Command(cls, usb, service, command='', timeout_ms=None):\n    \"\"\"One complete set of USB packets for a single command.\n\n    Sends service:command in a new connection, reading the data for the\n    response. All the data is held in memory, large responses will be slow and\n    can fill up memory.\n\n    Args:\n      usb: USB device handle with BulkRead and BulkWrite methods.\n      service: The service on the device to talk to.\n      command: The command to send to the service.\n      timeout_ms: Timeout for USB packets, in milliseconds.\n\n    Raises:\n      InterleavedDataError: Multiple streams running over usb.\n      InvalidCommandError: Got an unexpected response command.\n\n    Returns:\n      The response from the service.\n    \"\"\"\n    return ''.join(cls.StreamingCommand(usb, service, command, timeout_ms))\n\n  @classmethod\n  def StreamingCommand(cls, usb, service, command='', timeout_ms=None):\n    \"\"\"One complete set of USB packets for a single command.\n\n    Sends service:command in a new connection, reading the data for the\n    response. All the data is held in memory, large responses will be slow and\n    can fill up memory.\n\n    Args:\n      usb: USB device handle with BulkRead and BulkWrite methods.\n      service: The service on the device to talk to.\n      command: The command to send to the service.\n      timeout_ms: Timeout for USB packets, in milliseconds.\n\n    Raises:\n      InterleavedDataError: Multiple streams running over usb.\n      InvalidCommandError: Got an unexpected response command.\n\n    Yields:\n      The responses from the service.\n    \"\"\"\n    connection = cls.Open(usb, destination='%s:%s' % (service, command),\n                          timeout_ms=timeout_ms)\n    for data in connection.ReadUntilClose():\n      yield data\n"
  },
  {
    "path": "scripts/adb/adb_test.py",
    "content": "# Copyright 2014 Google Inc. All rights reserved.\n#\n# Licensed under the Apache License, Version 2.0 (the \"License\");\n# you may not use this file except in compliance with the License.\n# You may obtain a copy of the License at\n#\n#     http://www.apache.org/licenses/LICENSE-2.0\n#\n# Unless required by applicable law or agreed to in writing, software\n# distributed under the License is distributed on an \"AS IS\" BASIS,\n# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n# See the License for the specific language governing permissions and\n# limitations under the License.\n\"\"\"Tests for adb.\"\"\"\n\ntry:\n  import cStringIO\nexcept ImportError:\n  import io as cStringIO  # Python 3 compatibility\nimport struct\nimport unittest\n\nfrom . import adb_commands\nfrom . import adb_protocol\nfrom . import common_stub\n\n\nBANNER = 'blazetest'\nLOCAL_ID = 1\nREMOTE_ID = 2\n\n\nclass BaseAdbTest(unittest.TestCase):\n\n  @classmethod\n  def _ExpectWrite(cls, usb, command, arg0, arg1, data):\n    usb.ExpectWrite(cls._MakeHeader(command, arg0, arg1, data))\n    usb.ExpectWrite(data)\n    if command == 'WRTE':\n      cls._ExpectRead(usb, 'OKAY', 0, 0)\n\n  @classmethod\n  def _ExpectRead(cls, usb, command, arg0, arg1, data=''):\n    usb.ExpectRead(cls._MakeHeader(command, arg0, arg1, data))\n    if data:\n      usb.ExpectRead(data)\n    if command == 'WRTE':\n      cls._ExpectWrite(usb, 'OKAY', LOCAL_ID, REMOTE_ID, '')\n\n  @classmethod\n  def _ConvertCommand(cls, command):\n    return sum(ord(c) << (i * 8) for i, c in enumerate(command))\n\n  @classmethod\n  def _MakeHeader(cls, command, arg0, arg1, data):\n    command = cls._ConvertCommand(command)\n    magic = command ^ 0xFFFFFFFF\n    checksum = adb_protocol.AdbMessage.CalculateChecksum(data)\n    return struct.pack('<6I', command, arg0, arg1, len(data), checksum, magic)\n\n  @classmethod\n  def _ExpectConnection(cls, usb):\n    cls._ExpectWrite(usb, 'CNXN', 0x01000000, 4096, 'host::%s\\0' % BANNER)\n    cls._ExpectRead(usb, 'CNXN', 0, 0, 'device::\\0')\n\n  @classmethod\n  def _ExpectOpen(cls, usb, service):\n    cls._ExpectWrite(usb, 'OPEN', LOCAL_ID, 0, service)\n    cls._ExpectRead(usb, 'OKAY', REMOTE_ID, LOCAL_ID)\n\n  @classmethod\n  def _ExpectClose(cls, usb):\n    cls._ExpectRead(usb, 'CLSE', REMOTE_ID, 0)\n    cls._ExpectWrite(usb, 'CLSE', LOCAL_ID, REMOTE_ID, '')\n\n  @classmethod\n  def _Connect(cls, usb):\n    return adb_commands.AdbCommands.Connect(usb, BANNER)\n\n\nclass AdbTest(BaseAdbTest):\n\n  @classmethod\n  def _ExpectCommand(cls, service, command, *responses):\n    usb = common_stub.StubUsb()\n    cls._ExpectConnection(usb)\n    cls._ExpectOpen(usb, '%s:%s\\0' % (service, command))\n\n    for response in responses:\n      cls._ExpectRead(usb, 'WRTE', REMOTE_ID, 0, response)\n    cls._ExpectClose(usb)\n    return usb\n\n  def testConnect(self):\n    usb = common_stub.StubUsb()\n    self._ExpectConnection(usb)\n\n    adb_commands.AdbCommands.Connect(usb, BANNER)\n\n  def testSmallResponseShell(self):\n    command = 'keepin it real'\n    response = 'word.'\n    usb = self._ExpectCommand('shell', command, response)\n\n    adb_commands = self._Connect(usb)\n    self.assertEqual(response, adb_commands.Shell(command))\n\n  def testBigResponseShell(self):\n    command = 'keepin it real big'\n    # The data doesn't have to be big, the point is that it just concatenates\n    # the data from different WRTEs together.\n    responses = ['other stuff, ', 'and some words.']\n\n    usb = self._ExpectCommand('shell', command, *responses)\n\n    adb_commands = self._Connect(usb)\n    self.assertEqual(''.join(responses), adb_commands.Shell(command))\n\n  def testReboot(self):\n    usb = self._ExpectCommand('reboot', '', '')\n    adb_commands = self._Connect(usb)\n    adb_commands.Reboot()\n\n  def testRebootBootloader(self):\n    usb = self._ExpectCommand('reboot', 'bootloader', '')\n    adb_commands = self._Connect(usb)\n    adb_commands.RebootBootloader()\n\n  def testRemount(self):\n    usb = self._ExpectCommand('remount', '', '')\n    adb_commands = self._Connect(usb)\n    adb_commands.Remount()\n\n  def testRoot(self):\n    usb = self._ExpectCommand('root', '', '')\n    adb_commands = self._Connect(usb)\n    adb_commands.Root()\n\n\nclass FilesyncAdbTest(BaseAdbTest):\n\n  @classmethod\n  def _MakeSyncHeader(cls, command, *int_parts):\n    command = cls._ConvertCommand(command)\n    return struct.pack('<%dI' % (len(int_parts) + 1), command, *int_parts)\n\n  @classmethod\n  def _MakeWriteSyncPacket(cls, command, data='', size=None):\n    return cls._MakeSyncHeader(command, size or len(data)) + data\n\n  @classmethod\n  def _ExpectSyncCommand(cls, write_commands, read_commands):\n    usb = common_stub.StubUsb()\n    cls._ExpectConnection(usb)\n    cls._ExpectOpen(usb, 'sync:\\0')\n\n    while write_commands or read_commands:\n      if write_commands:\n        command = write_commands.pop(0)\n        cls._ExpectWrite(usb, 'WRTE', LOCAL_ID, REMOTE_ID, command)\n\n      if read_commands:\n        command = read_commands.pop(0)\n        cls._ExpectRead(usb, 'WRTE', REMOTE_ID, LOCAL_ID, command)\n\n    cls._ExpectClose(usb)\n    return usb\n\n  def testPush(self):\n    filedata = 'alo there, govnah'\n    mtime = 100\n\n    send = [\n        self._MakeWriteSyncPacket('SEND', '/data,33272'),\n        self._MakeWriteSyncPacket('DATA', filedata),\n        self._MakeWriteSyncPacket('DONE', size=mtime),\n    ]\n    data = 'OKAY\\0\\0\\0\\0'\n    usb = self._ExpectSyncCommand([''.join(send)], [data])\n\n    adb_commands = self._Connect(usb)\n    adb_commands.Push(cStringIO.StringIO(filedata), '/data', mtime=mtime)\n\n  def testPull(self):\n    filedata = \"g'ddayta, govnah\"\n\n    recv = self._MakeWriteSyncPacket('RECV', '/data')\n    data = [\n        self._MakeWriteSyncPacket('DATA', filedata),\n        self._MakeWriteSyncPacket('DONE'),\n    ]\n    usb = self._ExpectSyncCommand([recv], [''.join(data)])\n    adb_commands = self._Connect(usb)\n    self.assertEqual(filedata, adb_commands.Pull('/data'))\n\nif __name__ == '__main__':\n  unittest.main()\n"
  },
  {
    "path": "scripts/adb/common.py",
    "content": "# Copyright 2014 Google Inc. All rights reserved.\n#\n# Licensed under the Apache License, Version 2.0 (the \"License\");\n# you may not use this file except in compliance with the License.\n# You may obtain a copy of the License at\n#\n#     http://www.apache.org/licenses/LICENSE-2.0\n#\n# Unless required by applicable law or agreed to in writing, software\n# distributed under the License is distributed on an \"AS IS\" BASIS,\n# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n# See the License for the specific language governing permissions and\n# limitations under the License.\n\"\"\"Common code for ADB and Fastboot.\n\nCommon usb browsing, and usb communication.\n\"\"\"\nimport logging\nimport socket\nimport threading\nimport weakref\n\ntry:\n  basestring\nexcept NameError:\n  basestring = str  # Python 3 compatibility\n\ntry:\n  import libusb1\n  import usb1\n\n  from . import usb_exceptions\n\n  DEFAULT_TIMEOUT_MS = 1000\n\n  _LOG = logging.getLogger('android_usb')\n\n\n  def GetInterface(setting):\n    \"\"\"Get the class, subclass, and protocol for the given USB setting.\"\"\"\n    return (setting.getClass(), setting.getSubClass(), setting.getProtocol())\n\n\n  def InterfaceMatcher(clazz, subclass, protocol):\n    \"\"\"Returns a matcher that returns the setting with the given interface.\"\"\"\n    interface = (clazz, subclass, protocol)\n    def Matcher(device):\n      for setting in device.iterSettings():\n        if GetInterface(setting) == interface:\n          return setting\n    return Matcher\n\n\n  class UsbHandle(object):\n    \"\"\"USB communication object. Not thread-safe.\n\n    Handles reading and writing over USB with the proper endpoints, exceptions,\n    and interface claiming.\n\n    Important methods:\n      FlushBuffers()\n      BulkRead(int length)\n      BulkWrite(bytes data)\n    \"\"\"\n\n    _HANDLE_CACHE = weakref.WeakValueDictionary()\n    _HANDLE_CACHE_LOCK = threading.Lock()\n\n    def __init__(self, device, setting, usb_info=None, timeout_ms=None):\n      \"\"\"Initialize USB Handle.\n\n      Arguments:\n        device: libusb_device to connect to.\n        setting: libusb setting with the correct endpoints to communicate with.\n        usb_info: String describing the usb path/serial/device, for debugging.\n        timeout_ms: Timeout in milliseconds for all I/O.\n      \"\"\"\n      self._setting = setting\n      self._device = device\n      self._handle = None\n\n      self._usb_info = usb_info or ''\n      self._timeout_ms = timeout_ms or DEFAULT_TIMEOUT_MS\n\n    @property\n    def usb_info(self):\n      try:\n        sn = self.serial_number\n      except libusb1.USBError:\n        sn = ''\n      if sn and sn != self._usb_info:\n        return '%s %s' % (self._usb_info, sn)\n      return self._usb_info\n\n    def Open(self):\n      \"\"\"Opens the USB device for this setting, and claims the interface.\"\"\"\n      # Make sure we close any previous handle open to this usb device.\n      port_path = tuple(self.port_path)\n      with self._HANDLE_CACHE_LOCK:\n        old_handle = self._HANDLE_CACHE.get(port_path)\n        if old_handle is not None:\n          old_handle.Close()\n\n      self._read_endpoint = None\n      self._write_endpoint = None\n\n      for endpoint in self._setting.iterEndpoints():\n        address = endpoint.getAddress()\n        if address & libusb1.USB_ENDPOINT_DIR_MASK:\n          self._read_endpoint = address\n          self._max_read_packet_len = endpoint.getMaxPacketSize()\n        else:\n          self._write_endpoint = address\n\n      assert self._read_endpoint is not None\n      assert self._write_endpoint is not None\n\n      handle = self._device.open()\n      iface_number = self._setting.getNumber()\n      try:\n        if handle.kernelDriverActive(iface_number):\n          handle.detachKernelDriver(iface_number)\n      except libusb1.USBError as e:\n        if e.value == libusb1.LIBUSB_ERROR_NOT_FOUND:\n          _LOG.warning('Kernel driver not found for interface: %s.', iface_number)\n        else:\n          raise\n      handle.claimInterface(iface_number)\n      self._handle = handle\n      self._interface_number = iface_number\n\n      with self._HANDLE_CACHE_LOCK:\n        self._HANDLE_CACHE[port_path] = self\n      # When this object is deleted, make sure it's closed.\n      weakref.ref(self, self.Close)\n\n    @property\n    def serial_number(self):\n      return self._device.getSerialNumber()\n\n    @property\n    def port_path(self):\n      return [self._device.getBusNumber()] + self._device.getPortNumberList()\n\n    def Close(self):\n      if self._handle is None:\n        return\n      try:\n        self._handle.releaseInterface(self._interface_number)\n        self._handle.close()\n      except libusb1.USBError:\n        _LOG.info('USBError while closing handle %s: ',\n                  self.usb_info, exc_info=True)\n      finally:\n        self._handle = None\n\n    def Timeout(self, timeout_ms):\n      return timeout_ms if timeout_ms is not None else self._timeout_ms\n\n    def FlushBuffers(self):\n      while True:\n        try:\n          self.BulkRead(self._max_read_packet_len, timeout_ms=10)\n        except usb_exceptions.ReadFailedError as e:\n          if e.usb_error.value == libusb1.LIBUSB_ERROR_TIMEOUT:\n            break\n          raise\n\n    def BulkWrite(self, data, timeout_ms=None):\n      if self._handle is None:\n        raise usb_exceptions.WriteFailedError(\n            'This handle has been closed, probably due to another being opened.',\n            None)\n      try:\n        return self._handle.bulkWrite(\n            self._write_endpoint, data, timeout=self.Timeout(timeout_ms))\n      except libusb1.USBError as e:\n        raise usb_exceptions.WriteFailedError(\n            'Could not send data to %s (timeout %sms)' % (\n                self.usb_info, self.Timeout(timeout_ms)), e)\n\n    def BulkRead(self, length, timeout_ms=None):\n      if self._handle is None:\n        raise usb_exceptions.ReadFailedError(\n            'This handle has been closed, probably due to another being opened.',\n            None)\n      try:\n        return self._handle.bulkRead(\n            self._read_endpoint, length, timeout=self.Timeout(timeout_ms))\n      except libusb1.USBError as e:\n        raise usb_exceptions.ReadFailedError(\n            'Could not receive data from %s (timeout %sms)' % (\n                self.usb_info, self.Timeout(timeout_ms)), e)\n\n    def PortPathMatcher(cls, port_path):\n      \"\"\"Returns a device matcher for the given port path.\"\"\"\n      if isinstance(port_path, basestring):\n        # Convert from sysfs path to port_path.\n        port_path = [int(part) for part in SYSFS_PORT_SPLIT_RE.split(port_path)]\n      return lambda device: device.port_path == port_path\n\n    @classmethod\n    def SerialMatcher(cls, serial):\n      \"\"\"Returns a device matcher for the given serial.\"\"\"\n      return lambda device: device.serial_number == serial\n\n    @classmethod\n    def FindAndOpen(cls, setting_matcher,\n                    port_path=None, serial=None, timeout_ms=None):\n      dev = cls.Find(\n          setting_matcher, port_path=port_path, serial=serial,\n          timeout_ms=timeout_ms)\n      dev.Open()\n      dev.FlushBuffers()\n      return dev\n\n    @classmethod\n    def Find(cls, setting_matcher, port_path=None, serial=None, timeout_ms=None):\n      \"\"\"Gets the first device that matches according to the keyword args.\"\"\"\n      if port_path:\n        device_matcher = cls.PortPathMatcher(port_path)\n        usb_info = port_path\n      elif serial:\n        device_matcher = cls.SerialMatcher(serial)\n        usb_info = serial\n      else:\n        device_matcher = None\n        usb_info = 'first'\n      return cls.FindFirst(setting_matcher, device_matcher,\n                           usb_info=usb_info, timeout_ms=timeout_ms)\n\n    @classmethod\n    def FindFirst(cls, setting_matcher, device_matcher=None, **kwargs):\n      \"\"\"Find and return the first matching device.\n\n      Args:\n        setting_matcher: See cls.FindDevices.\n        device_matcher: See cls.FindDevices.\n        **kwargs: See cls.FindDevices.\n\n      Returns:\n        An instance of UsbHandle.\n\n      Raises:\n        DeviceNotFoundError: Raised if the device is not available.\n      \"\"\"\n      try:\n        return next(cls.FindDevices(\n            setting_matcher, device_matcher=device_matcher, **kwargs))\n      except StopIteration:\n        raise usb_exceptions.DeviceNotFoundError(\n            'No device available, or it is in the wrong configuration.')\n\n    @classmethod\n    def FindDevices(cls, setting_matcher, device_matcher=None,\n                    usb_info='', timeout_ms=None):\n      \"\"\"Find and yield the devices that match.\n\n      Args:\n        setting_matcher: Function that returns the setting to use given a\n          usb1.USBDevice, or None if the device doesn't have a valid setting.\n        device_matcher: Function that returns True if the given UsbHandle is\n          valid. None to match any device.\n        usb_info: Info string describing device(s).\n        timeout_ms: Default timeout of commands in milliseconds.\n\n      Yields:\n        UsbHandle instances\n      \"\"\"\n      ctx = usb1.USBContext()\n      for device in ctx.getDeviceList(skip_on_error=True):\n        setting = setting_matcher(device)\n        if setting is None:\n          continue\n\n        handle = cls(device, setting, usb_info=usb_info, timeout_ms=timeout_ms)\n        if device_matcher is None or device_matcher(handle):\n          yield handle\nexcept:\n  pass\n\nclass TcpHandle(object):\n  \"\"\"TCP connection object.\n\n     Provides same interface as UsbHandle but ignores timeout.\"\"\"\n\n  def __init__(self, serial):\n    \"\"\"Initialize the TCP Handle.\n    Arguments:\n      serial: Android device serial of the form host or host:port.\n\n    Host may be an IP address or a host name.\n    \"\"\"\n    if ':' in serial:\n      (host, port) = serial.split(':')\n    else:\n      host = serial\n      port = 5555\n\n    self._connection = socket.create_connection((host, port))\n\n  def BulkWrite(self, data, timeout=None):\n      return self._connection.sendall(data)\n\n  def BulkRead(self, numbytes, timeout=None):\n      return self._connection.recv(numbytes)\n\n  def Timeout(self, timeout_ms):\n      return timeout_ms\n\n  def Close(self):\n      return self._connection.close()\n"
  },
  {
    "path": "scripts/adb/common_cli.py",
    "content": "# Copyright 2014 Google Inc. All rights reserved.\n#\n# Licensed under the Apache License, Version 2.0 (the \"License\");\n# you may not use this file except in compliance with the License.\n# You may obtain a copy of the License at\n#\n#     http://www.apache.org/licenses/LICENSE-2.0\n#\n# Unless required by applicable law or agreed to in writing, software\n# distributed under the License is distributed on an \"AS IS\" BASIS,\n# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n# See the License for the specific language governing permissions and\n# limitations under the License.\n\"\"\"Common code for ADB and Fastboot CLI.\n\nUsage introspects the given class for methods, args, and docs to show the user.\n\nStartCli handles connecting to a device, calling the expected method, and\noutputting the results.\n\"\"\"\n\nfrom __future__ import print_function\n\ntry:\n  import cStringIO\nexcept ImportError:\n  import io as cStringIO  # Python 3 compatibility\nimport inspect\nimport re\nimport sys\nimport types\n\nimport gflags\n\nfrom . import usb_exceptions\n\ngflags.DEFINE_integer('timeout_ms', 10000, 'Timeout in milliseconds.')\ngflags.DEFINE_list('port_path', [], 'USB port path integers (eg 1,2 or 2,1,1)')\ngflags.DEFINE_string('serial', None, 'Device serial to look for (host:port or USB serial)', short_name='s')\n\ngflags.DEFINE_bool('output_port_path', False,\n                   'Affects the devices command only, outputs the port_path '\n                   'alongside the serial if true.')\n\nFLAGS = gflags.FLAGS\n\n_BLACKLIST = {\n    'Connect',\n    'Close',\n    'ConnectDevice',\n    'DeviceIsAvailable',\n}\n\n\ndef Uncamelcase(name):\n  parts = re.split(r'([A-Z][a-z]+)', name)[1:-1:2]\n  return ('-'.join(parts)).lower()\n\n\ndef Camelcase(name):\n  return name.replace('-', ' ').title().replace(' ', '')\n\n\ndef Usage(adb_dev):\n  methods = inspect.getmembers(adb_dev, inspect.ismethod)\n  print('Methods:')\n  for name, method in methods:\n    if name.startswith('_'):\n      continue\n    if not method.__doc__:\n      continue\n    if name in _BLACKLIST:\n      continue\n\n    argspec = inspect.getargspec(method)\n    args = argspec.args[1:] or ''\n    # Surround default'd arguments with []\n    defaults = argspec.defaults or []\n    if args:\n      args = (args[:-len(defaults)] +\n              ['[%s]' % arg for arg in args[-len(defaults):]])\n\n      args = ' ' + ' '.join(args)\n\n    print('  %s%s:' % (Uncamelcase(name), args))\n    print('    %s' % method.__doc__)\n\n\ndef StartCli(argv, device_callback, kwarg_callback=None, list_callback=None,\n             **device_kwargs):\n  \"\"\"Starts a common CLI interface for this usb path and protocol.\"\"\"\n  argv = argv[1:]\n\n  if len(argv) == 1 and argv[0] == 'devices' and list_callback is not None:\n    # To mimic 'adb devices' output like:\n    # ------------------------------\n    # List of devices attached\n    # 015DB7591102001A        device\n    # Or with --output_port_path:\n    # 015DB7591102001A        device        1,2\n    # ------------------------------\n    for device in list_callback():\n      if FLAGS.output_port_path:\n        print('%s\\tdevice\\t%s' % (\n            device.serial_number,\n            ','.join(str(port) for port in device.port_path)))\n      else:\n        print('%s\\tdevice' % device.serial_number)\n    return\n\n  port_path = [int(part) for part in FLAGS.port_path]\n  serial = FLAGS.serial\n\n  device_kwargs.setdefault('default_timeout_ms', FLAGS.timeout_ms)\n  try:\n    dev = device_callback(\n        port_path=port_path, serial=serial, **device_kwargs)\n  except usb_exceptions.DeviceNotFoundError as e:\n    print('No device found: %s' % e, file=sys.stderr)\n    return\n  except usb_exceptions.CommonUsbError as e:\n    print('Could not connect to device: %s' % e, file=sys.stderr)\n    raise\n\n  if not argv:\n    Usage(dev)\n    return\n\n  kwargs = {}\n\n  # CamelCase method names, eg reboot-bootloader -> RebootBootloader\n  method_name = Camelcase(argv[0])\n  method = getattr(dev, method_name)\n  argspec = inspect.getargspec(method)\n  num_args = len(argspec.args) - 1  # self is the first one.\n  num_args -= len(argspec.defaults or [])\n  # Handle putting the remaining command line args into the last normal arg.\n  argv.pop(0)\n\n  # Flags -> Keyword args\n  if kwarg_callback:\n    kwarg_callback(kwargs, argspec)\n\n  try:\n    if num_args == 1:\n      # Only one argument, so join them all with spaces\n      result = method(' '.join(argv), **kwargs)\n    else:\n      result = method(*argv, **kwargs)\n\n    if result is not None:\n      try:\n        # An empty call to cStringIO.StringIO returns an instance of\n        # cStringIO.OutputType on Python 2.\n        StringIOType = cStringIO.OutputType\n      except AttributeError:\n        # On Python 3, this object is just an instance of StringIO.\n        StringIOType = cStringIO.StringIO\n      if isinstance(result, StringIOType):\n        sys.stdout.write(result.getvalue())\n      elif isinstance(result, (list, types.GeneratorType)):\n        for r in result:\n          r = str(r)\n          sys.stdout.write(r)\n          if not r.endswith('\\n'):\n            sys.stdout.write('\\n')\n      else:\n        sys.stdout.write(result)\n    sys.stdout.write('\\n')\n  except Exception as e:  # pylint: disable=broad-except\n    sys.stdout.write(str(e))\n    return\n  finally:\n    dev.Close()\n\n"
  },
  {
    "path": "scripts/adb/common_stub.py",
    "content": "\"\"\"Stubs for tests using common's usb handling.\"\"\"\n\nimport binascii\nimport string\n\nPRINTABLE_DATA = set(string.printable) - set(string.whitespace)\n\n\ndef _Dotify(data):\n  return ''.join(char if char in PRINTABLE_DATA else '.' for char in data)\n\n\nclass StubUsb(object):\n  \"\"\"UsbHandle stub.\"\"\"\n\n  def __init__(self):\n    self.written_data = []\n    self.read_data = []\n    self.timeout_ms = 0\n\n  def BulkWrite(self, data, unused_timeout_ms=None):\n    expected_data = self.written_data.pop(0)\n    if expected_data != data:\n      raise ValueError('Expected %s, got %s (%s)' % (\n          _Dotify(expected_data), binascii.hexlify(data), _Dotify(data)))\n\n  def BulkRead(self, length,\n               timeout_ms=None):  # pylint: disable=unused-argument\n    data = self.read_data.pop(0)\n    if length < len(data):\n      raise ValueError(\n          'Overflow packet length. Read %d bytes, got %d bytes: %s',\n          length, len(data))\n    return data\n\n  def ExpectWrite(self, data):\n    self.written_data.append(data)\n\n  def ExpectRead(self, data):\n    self.read_data.append(data)\n\n  def Timeout(self, timeout_ms):\n    return timeout_ms if timeout_ms is not None else self.timeout_ms\n"
  },
  {
    "path": "scripts/adb/fastboot.py",
    "content": "# Copyright 2014 Google Inc. All rights reserved.\n#\n# Licensed under the Apache License, Version 2.0 (the \"License\");\n# you may not use this file except in compliance with the License.\n# You may obtain a copy of the License at\n#\n#     http://www.apache.org/licenses/LICENSE-2.0\n#\n# Unless required by applicable law or agreed to in writing, software\n# distributed under the License is distributed on an \"AS IS\" BASIS,\n# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n# See the License for the specific language governing permissions and\n# limitations under the License.\n\"\"\"A libusb1-based fastboot implementation.\"\"\"\n\nimport binascii\nimport collections\ntry:\n  import cStringIO\nexcept ImportError:\n  import io as cStringIO  # Python 3 compatibility\nimport logging\nimport os\nimport struct\n\nimport gflags\n\nfrom . import common\nfrom . import usb_exceptions\n\ntry:\n  basestring\nexcept NameError:\n  basestring = str  # Python 3 compatibility\n\nFLAGS = gflags.FLAGS\ngflags.DEFINE_integer('fastboot_write_chunk_size_kb', 4,\n                      'The size of packets to write to usb, this is set to 4 '\n                      \"for legacy reasons.  We've had success with 1MB \"\n                      'DRASTICALLY increasing flashing times.')\n\n_LOG = logging.getLogger('fastboot')\n\nDEFAULT_MESSAGE_CALLBACK = lambda m: logging.info('Got %s from device', m)\nFastbootMessage = collections.namedtuple(  # pylint: disable=invalid-name\n    'FastbootMessage', ['message', 'header'])\n\n# From fastboot.c\nVENDORS = {0x18D1, 0x0451, 0x0502, 0x0FCE, 0x05C6, 0x22B8, 0x0955,\n           0x413C, 0x2314, 0x0BB4, 0x8087}\nCLASS = 0xFF\nSUBCLASS = 0x42\nPROTOCOL = 0x03\n# pylint: disable=invalid-name\nDeviceIsAvailable = common.InterfaceMatcher(CLASS, SUBCLASS, PROTOCOL)\n\n\n# pylint doesn't understand cross-module exception baseclasses.\n# pylint: disable=nonstandard-exception\nclass FastbootTransferError(usb_exceptions.FormatMessageWithArgumentsException):\n  \"\"\"Transfer error.\"\"\"\n\n\nclass FastbootRemoteFailure(usb_exceptions.FormatMessageWithArgumentsException):\n  \"\"\"Remote error.\"\"\"\n\n\nclass FastbootStateMismatch(usb_exceptions.FormatMessageWithArgumentsException):\n  \"\"\"Fastboot and uboot's state machines are arguing. You Lose.\"\"\"\n\n\nclass FastbootInvalidResponse(\n    usb_exceptions.FormatMessageWithArgumentsException):\n  \"\"\"Fastboot responded with a header we didn't expect.\"\"\"\n\n\nclass FastbootProtocol(object):\n  \"\"\"Encapsulates the fastboot protocol.\"\"\"\n  FINAL_HEADERS = {'OKAY', 'DATA'}\n\n  def __init__(self, usb):\n    \"\"\"Constructs a FastbootProtocol instance.\n\n    Arguments:\n      usb: UsbHandle instance.\n    \"\"\"\n    self.usb = usb\n\n  @property\n  def usb_handle(self):\n    return self.usb\n\n  def SendCommand(self, command, arg=None):\n    \"\"\"Sends a command to the device.\n\n    Args:\n      command: The command to send.\n      arg: Optional argument to the command.\n    \"\"\"\n    if arg is not None:\n      command = '%s:%s' % (command, arg)\n    self._Write(cStringIO.StringIO(command), len(command))\n\n  def HandleSimpleResponses(\n      self, timeout_ms=None, info_cb=DEFAULT_MESSAGE_CALLBACK):\n    \"\"\"Accepts normal responses from the device.\n\n    Args:\n      timeout_ms: Timeout in milliseconds to wait for each response.\n      info_cb: Optional callback for text sent from the bootloader.\n\n    Returns:\n      OKAY packet's message.\n    \"\"\"\n    return self._AcceptResponses('OKAY', info_cb, timeout_ms=timeout_ms)\n\n  def HandleDataSending(self, source_file, source_len,\n                        info_cb=DEFAULT_MESSAGE_CALLBACK,\n                        progress_callback=None, timeout_ms=None):\n    \"\"\"Handles the protocol for sending data to the device.\n\n    Arguments:\n      source_file: File-object to read from for the device.\n      source_len: Amount of data, in bytes, to send to the device.\n      info_cb: Optional callback for text sent from the bootloader.\n      progress_callback: Callback that takes the current and the total progress\n        of the current file.\n      timeout_ms: Timeout in milliseconds to wait for each response.\n\n    Raises:\n      FastbootTransferError: When fastboot can't handle this amount of data.\n      FastbootStateMismatch: Fastboot responded with the wrong packet type.\n      FastbootRemoteFailure: Fastboot reported failure.\n      FastbootInvalidResponse: Fastboot responded with an unknown packet type.\n\n    Returns:\n      OKAY packet's message.\n    \"\"\"\n    accepted_size = self._AcceptResponses(\n        'DATA', info_cb, timeout_ms=timeout_ms)\n\n    accepted_size = binascii.unhexlify(accepted_size[:8])\n    accepted_size, = struct.unpack('>I', accepted_size)\n    if accepted_size != source_len:\n      raise FastbootTransferError(\n          'Device refused to download %s bytes of data (accepts %s bytes)',\n          source_len, accepted_size)\n    self._Write(source_file, accepted_size, progress_callback)\n    return self._AcceptResponses('OKAY', info_cb, timeout_ms=timeout_ms)\n\n  def _AcceptResponses(self, expected_header, info_cb, timeout_ms=None):\n    \"\"\"Accepts responses until the expected header or a FAIL.\n\n    Arguments:\n      expected_header: OKAY or DATA\n      info_cb: Optional callback for text sent from the bootloader.\n      timeout_ms: Timeout in milliseconds to wait for each response.\n\n    Raises:\n      FastbootStateMismatch: Fastboot responded with the wrong packet type.\n      FastbootRemoteFailure: Fastboot reported failure.\n      FastbootInvalidResponse: Fastboot responded with an unknown packet type.\n\n    Returns:\n      OKAY packet's message.\n    \"\"\"\n    while True:\n      response = self.usb.BulkRead(64, timeout_ms=timeout_ms)\n      header = response[:4]\n      remaining = response[4:]\n\n      if header == 'INFO':\n        info_cb(FastbootMessage(remaining, header))\n      elif header in self.FINAL_HEADERS:\n        if header != expected_header:\n          raise FastbootStateMismatch(\n              'Expected %s, got %s', expected_header, header)\n        if header == 'OKAY':\n          info_cb(FastbootMessage(remaining, header))\n        return remaining\n      elif header == 'FAIL':\n        info_cb(FastbootMessage(remaining, header))\n        raise FastbootRemoteFailure('FAIL: %s', remaining)\n      else:\n        raise FastbootInvalidResponse(\n            'Got unknown header %s and response %s', header, remaining)\n\n  def _HandleProgress(self, total, progress_callback):\n    \"\"\"Calls the callback with the current progress and total .\"\"\"\n    current = 0\n    while True:\n      current += yield\n      try:\n        progress_callback(current, total)\n      except Exception:  # pylint: disable=broad-except\n        _LOG.exception('Progress callback raised an exception. %s',\n                       progress_callback)\n        continue\n\n  def _Write(self, data, length, progress_callback=None):\n    \"\"\"Sends the data to the device, tracking progress with the callback.\"\"\"\n    if progress_callback:\n      progress = self._HandleProgress(length, progress_callback)\n      next(progress)\n    while length:\n      tmp = data.read(FLAGS.fastboot_write_chunk_size_kb * 1024)\n      length -= len(tmp)\n      self.usb.BulkWrite(tmp)\n\n      if progress_callback:\n        progress.send(len(tmp))\n\n\nclass FastbootCommands(object):\n  \"\"\"Encapsulates the fastboot commands.\"\"\"\n  protocol_handler = FastbootProtocol\n\n  def __init__(self, usb):\n    \"\"\"Constructs a FastbootCommands instance.\n\n    Arguments:\n      usb: UsbHandle instance.\n    \"\"\"\n    self._usb = usb\n    self._protocol = self.protocol_handler(usb)\n\n  @property\n  def usb_handle(self):\n    return self._usb\n\n  def Close(self):\n    self._usb.Close()\n\n  @classmethod\n  def ConnectDevice(\n      cls, port_path=None, serial=None, default_timeout_ms=None):\n    \"\"\"Convenience function to get an adb device from usb path or serial.\"\"\"\n    usb = common.UsbHandle.FindAndOpen(\n        DeviceIsAvailable, port_path=port_path, serial=serial,\n        timeout_ms=default_timeout_ms)\n    return cls(usb)\n\n  @classmethod\n  def Devices(cls):\n    \"\"\"Get a generator of UsbHandle for devices available.\"\"\"\n    return common.UsbHandle.FindDevices(DeviceIsAvailable)\n\n  def _SimpleCommand(self, command, arg=None, **kwargs):\n    self._protocol.SendCommand(command, arg)\n    return self._protocol.HandleSimpleResponses(**kwargs)\n\n  def FlashFromFile(self, partition, source_file, source_len=0,\n                    info_cb=DEFAULT_MESSAGE_CALLBACK, progress_callback=None):\n    \"\"\"Flashes a partition from the file on disk.\n\n    Args:\n      partition: Partition name to flash to.\n      source_file: Filename to download to the device.\n      source_len: Optional length of source_file, uses os.stat if not provided.\n      info_cb: See Download.\n      progress_callback: See Download.\n\n    Returns:\n      Download and flash responses, normally nothing.\n    \"\"\"\n    if source_len == 0:\n      # Fall back to stat.\n      source_len = os.stat(source_file).st_size\n    download_response = self.Download(\n        source_file, source_len=source_len, info_cb=info_cb,\n        progress_callback=progress_callback)\n    flash_response = self.Flash(partition, info_cb=info_cb)\n    return download_response + flash_response\n\n  def Download(self, source_file, source_len=0,\n               info_cb=DEFAULT_MESSAGE_CALLBACK, progress_callback=None):\n    \"\"\"Downloads a file to the device.\n\n    Args:\n      source_file: A filename or file-like object to download to the device.\n      source_len: Optional length of source_file. If source_file is a file-like\n          object and source_len is not provided, source_file is read into\n          memory.\n      info_cb: Optional callback accepting FastbootMessage for text sent from\n          the bootloader.\n      progress_callback: Optional callback called with the percent of the\n          source_file downloaded. Note, this doesn't include progress of the\n          actual flashing.\n\n    Returns:\n      Response to a download request, normally nothing.\n    \"\"\"\n    if isinstance(source_file, basestring):\n      source_len = os.stat(source_file).st_size\n      source_file = open(source_file)\n\n    if source_len == 0:\n      # Fall back to storing it all in memory :(\n      data = source_file.read()\n      source_file = cStringIO.StringIO(data)\n      source_len = len(data)\n\n    self._protocol.SendCommand('download', '%08x' % source_len)\n    return self._protocol.HandleDataSending(\n        source_file, source_len, info_cb, progress_callback=progress_callback)\n\n  def Flash(self, partition, timeout_ms=0, info_cb=DEFAULT_MESSAGE_CALLBACK):\n    \"\"\"Flashes the last downloaded file to the given partition.\n\n    Args:\n      partition: Partition to flash.\n      timeout_ms: Optional timeout in milliseconds to wait for it to finish.\n      info_cb: See Download. Usually no messages.\n\n    Returns:\n      Response to a download request, normally nothing.\n    \"\"\"\n    return self._SimpleCommand('flash', arg=partition, info_cb=info_cb,\n                               timeout_ms=timeout_ms)\n\n  def Erase(self, partition, timeout_ms=None):\n    \"\"\"Erases the given partition.\"\"\"\n    self._SimpleCommand('erase', arg=partition, timeout_ms=timeout_ms)\n\n  def Getvar(self, var, info_cb=DEFAULT_MESSAGE_CALLBACK):\n    \"\"\"Returns the given variable's definition.\n\n    Args:\n      var: A variable the bootloader tracks, such as version.\n      info_cb: See Download. Usually no messages.\n    Returns:\n      Value of var according to the current bootloader.\n    \"\"\"\n    return self._SimpleCommand('getvar', arg=var, info_cb=info_cb)\n\n  def Oem(self, command, timeout_ms=None, info_cb=DEFAULT_MESSAGE_CALLBACK):\n    \"\"\"Executes an OEM command on the device.\n\n    Args:\n      command: The command to execute, such as 'poweroff' or 'bootconfig read'.\n      timeout_ms: Optional timeout in milliseconds to wait for a response.\n      info_cb: See Download. Messages vary based on command.\n    Returns:\n      The final response from the device.\n    \"\"\"\n    return self._SimpleCommand(\n        'oem %s' % command, timeout_ms=timeout_ms, info_cb=info_cb)\n\n  def Continue(self):\n    \"\"\"Continues execution past fastboot into the system.\"\"\"\n    return self._SimpleCommand('continue')\n\n  def Reboot(self, target_mode=None, timeout_ms=None):\n    \"\"\"Reboots the device.\n\n    Args:\n        target_mode: Normal reboot when unspecified (or None). Can specify\n            other target modes, such as 'recovery' or 'bootloader'.\n        timeout_ms: Optional timeout in milliseconds to wait for a response.\n    Returns:\n        Usually the empty string. Depends on the bootloader and the target_mode.\n    \"\"\"\n    return self._SimpleCommand('reboot', arg=target_mode, timeout_ms=timeout_ms)\n\n  def RebootBootloader(self, timeout_ms=None):\n    \"\"\"Reboots into the bootloader, usually equiv to Reboot('bootloader').\"\"\"\n    return self._SimpleCommand('reboot-bootloader', timeout_ms=timeout_ms)\n"
  },
  {
    "path": "scripts/adb/fastboot_debug.py",
    "content": "# Copyright 2014 Google Inc. All rights reserved.\n#\n# Licensed under the Apache License, Version 2.0 (the \"License\");\n# you may not use this file except in compliance with the License.\n# You may obtain a copy of the License at\n#\n#     http://www.apache.org/licenses/LICENSE-2.0\n#\n# Unless required by applicable law or agreed to in writing, software\n# distributed under the License is distributed on an \"AS IS\" BASIS,\n# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n# See the License for the specific language governing permissions and\n# limitations under the License.\n\"\"\"Fastboot debugging binary.\n\nCall it similar to how you call android's fastboot. Call it similar to how you\ncall android's fastboot, but this only accepts usb paths and no serials.\n\"\"\"\nimport sys\n\nimport gflags\nimport progressbar\n\nfrom . import common_cli\nfrom . import fastboot\n\ngflags.ADOPT_module_key_flags(common_cli)\n\nFLAGS = gflags.FLAGS\n\n\ndef KwargHandler(kwargs, argspec):\n\n  if 'info_cb' in argspec.args:\n    # Use an unbuffered version of stdout.\n    def InfoCb(message):\n      if not message.message:\n        return\n      sys.stdout.write('%s: %s\\n' % (message.header, message.message))\n      sys.stdout.flush()\n    kwargs['info_cb'] = InfoCb\n  if 'progress_callback' in argspec.args:\n    bar = progressbar.ProgessBar(\n        widgets=[progressbar.Bar(), progressbar.Percentage()])\n    bar.start()\n    def SetProgress(current, total):\n      bar.update(current / total * 100.0)\n      if current == total:\n        bar.finish()\n    kwargs['progress_callback'] = SetProgress\n\n\ndef main(argv):\n  common_cli.StartCli(\n      argv, fastboot.FastbootCommands.ConnectDevice,\n      list_callback=fastboot.FastbootCommands.Devices,\n      kwarg_callback=KwargHandler)\n\n\nif __name__ == '__main__':\n  main(FLAGS(sys.argv))\n"
  },
  {
    "path": "scripts/adb/fastboot_protocol.txt",
    "content": "Fastboot Protocol Documentation\n\nFastboot's protocol is similar to ADB in only a few ways. However, to make the\ncode simpler to be inside a bootloader, it basically was completely altered.\n\nCommands:\n  getvar:%(variable)s\n  download:%08x\n  verify:%08x\n  flash:%(partition)s\n  erase:%(partition)s\n  oem %(stuff)s\n  boot\n  continue\n  reboot\n  reboot-bootloader\n\n\nResponses:\n  These are 4-64 bytes long. The first 4 bytes is the header, the rest is\n  header-specific but only up to 60 bytes.\n\n  INFO + data[0-60]\n    Arbitrary data returned from the bootloader.\n  OKAY + reason[0-60]\n    Last response, says the command succeeded.\n  FAIL + reason[0-60]\n    Last response, says the command failed.\n  DATA + size[8]\n    Only in response to a download command, says the bootloader is ready to\n    accept `size` amount of data.\n\n"
  },
  {
    "path": "scripts/adb/fastboot_test.py",
    "content": "# Copyright 2014 Google Inc. All rights reserved.\n#\n# Licensed under the Apache License, Version 2.0 (the \"License\");\n# you may not use this file except in compliance with the License.\n# You may obtain a copy of the License at\n#\n#     http://www.apache.org/licenses/LICENSE-2.0\n#\n# Unless required by applicable law or agreed to in writing, software\n# distributed under the License is distributed on an \"AS IS\" BASIS,\n# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n# See the License for the specific language governing permissions and\n# limitations under the License.\n\"\"\"Tests for adb.fastboot.\"\"\"\n\ntry:\n  import cStringIO\nexcept ImportError:\n  import io as cStringIO  # Python 3 compatibility\nimport os\nimport tempfile\nimport unittest\n\nimport gflags\n\nfrom . import common_stub\nfrom . import fastboot\n\nFLAGS = gflags.FLAGS\n\nclass FastbootTest(unittest.TestCase):\n\n  def setUp(self):\n    self.usb = common_stub.StubUsb()\n\n  @staticmethod\n  def _SumLengths(items):\n    return sum(len(item) for item in items)\n\n  def ExpectDownload(self, writes, succeed=True, accept_data=True):\n    self.usb.ExpectWrite('download:%08x' % self._SumLengths(writes))\n\n    if accept_data:\n      self.usb.ExpectRead('DATA%08x' % self._SumLengths(writes))\n    else:\n      self.usb.ExpectRead('DATA%08x' % (self._SumLengths(writes) - 2))\n\n    for data in writes:\n      self.usb.ExpectWrite(data)\n\n    if succeed:\n      self.usb.ExpectRead('OKAYResult')\n    else:\n      self.usb.ExpectRead('FAILResult')\n\n  def ExpectFlash(self, partition, succeed=True):\n    self.usb.ExpectWrite('flash:%s' % partition)\n    self.usb.ExpectRead('INFORandom info from the bootloader')\n    if succeed:\n      self.usb.ExpectRead('OKAYDone')\n    else:\n      self.usb.ExpectRead('FAILDone')\n\n  def testDownload(self):\n    raw = 'aoeuidhtnsqjkxbmwpyfgcrl'\n    data = cStringIO.StringIO(raw)\n\n    self.ExpectDownload([raw])\n    commands = fastboot.FastbootCommands(self.usb)\n\n    response = commands.Download(data)\n    self.assertEqual('Result', response)\n\n  def testDownloadFail(self):\n    raw = 'aoeuidhtnsqjkxbmwpyfgcrl'\n    data = cStringIO.StringIO(raw)\n\n    self.ExpectDownload([raw], succeed=False)\n    commands = fastboot.FastbootCommands(self.usb)\n    with self.assertRaises(fastboot.FastbootRemoteFailure):\n      commands.Download(data)\n\n    data = cStringIO.StringIO(raw)\n    self.ExpectDownload([raw], accept_data=False)\n    with self.assertRaises(fastboot.FastbootTransferError):\n      commands.Download(data)\n\n  def testFlash(self):\n    partition = 'yarr'\n\n    self.ExpectFlash(partition)\n    commands = fastboot.FastbootCommands(self.usb)\n\n    output = cStringIO.StringIO()\n    def InfoCb(message):\n      if message.header == 'INFO':\n        output.write(message.message)\n    response = commands.Flash(partition, info_cb=InfoCb)\n    self.assertEqual('Done', response)\n    self.assertEqual('Random info from the bootloader', output.getvalue())\n\n  def testFlashFail(self):\n    partition = 'matey'\n\n    self.ExpectFlash(partition, succeed=False)\n    commands = fastboot.FastbootCommands(self.usb)\n\n    with self.assertRaises(fastboot.FastbootRemoteFailure):\n      commands.Flash(partition)\n\n  def testFlashFromFile(self):\n    partition = 'somewhere'\n    # More than one packet, ends somewhere into the 3rd packet.\n    raw = 'SOMETHING' * 1086\n    tmp = tempfile.NamedTemporaryFile(delete=False)\n    tmp.write(raw)\n    tmp.close()\n    progresses = []\n\n    pieces = []\n    chunk_size = FLAGS.fastboot_write_chunk_size_kb * 1024\n    while raw:\n      pieces.append(raw[:chunk_size])\n      raw = raw[chunk_size:]\n    self.ExpectDownload(pieces)\n    self.ExpectFlash(partition)\n\n    cb = lambda progress, total: progresses.append((progress, total))\n\n    commands = fastboot.FastbootCommands(self.usb)\n    commands.FlashFromFile(\n        partition, tmp.name, progress_callback=cb)\n    self.assertEqual(len(pieces), len(progresses))\n    os.remove(tmp.name)\n\n  def testSimplerCommands(self):\n    commands = fastboot.FastbootCommands(self.usb)\n\n    self.usb.ExpectWrite('erase:vector')\n    self.usb.ExpectRead('OKAY')\n    commands.Erase('vector')\n\n    self.usb.ExpectWrite('getvar:variable')\n    self.usb.ExpectRead('OKAYstuff')\n    self.assertEqual('stuff', commands.Getvar('variable'))\n\n    self.usb.ExpectWrite('continue')\n    self.usb.ExpectRead('OKAY')\n    commands.Continue()\n\n    self.usb.ExpectWrite('reboot')\n    self.usb.ExpectRead('OKAY')\n    commands.Reboot()\n\n    self.usb.ExpectWrite('reboot-bootloader')\n    self.usb.ExpectRead('OKAY')\n    commands.RebootBootloader()\n\n    self.usb.ExpectWrite('oem a little somethin')\n    self.usb.ExpectRead('OKAYsomethin')\n    self.assertEqual('somethin', commands.Oem('a little somethin'))\n\n  def testVariousFailures(self):\n    commands = fastboot.FastbootCommands(self.usb)\n\n    self.usb.ExpectWrite('continue')\n    self.usb.ExpectRead('BLEH')\n    with self.assertRaises(fastboot.FastbootInvalidResponse):\n      commands.Continue()\n\n    self.usb.ExpectWrite('continue')\n    self.usb.ExpectRead('DATA000000')\n    with self.assertRaises(fastboot.FastbootStateMismatch):\n      commands.Continue()\n\n\nif __name__ == '__main__':\n  unittest.main()\n"
  },
  {
    "path": "scripts/adb/filesync_protocol.py",
    "content": "# Copyright 2014 Google Inc. All rights reserved.\n#\n# Licensed under the Apache License, Version 2.0 (the \"License\");\n# you may not use this file except in compliance with the License.\n# You may obtain a copy of the License at\n#\n#     http://www.apache.org/licenses/LICENSE-2.0\n#\n# Unless required by applicable law or agreed to in writing, software\n# distributed under the License is distributed on an \"AS IS\" BASIS,\n# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n# See the License for the specific language governing permissions and\n# limitations under the License.\n\"\"\"ADB protocol implementation.\n\nImplements the ADB protocol as seen in android's adb/adbd binaries, but only the\nhost side.\n\"\"\"\n\nimport collections\nimport stat\nimport struct\nimport time\n\nfrom . import adb_protocol\nfrom . import usb_exceptions\n\n# Default mode for pushed files.\nDEFAULT_PUSH_MODE = stat.S_IFREG | stat.S_IRWXU | stat.S_IRWXG\n# Maximum size of a filesync DATA packet.\nMAX_PUSH_DATA = 2*1024\n\n\nclass InvalidChecksumError(Exception):\n  \"\"\"Checksum of data didn't match expected checksum.\"\"\"\n\n\nclass InterleavedDataError(Exception):\n  \"\"\"We only support command sent serially.\"\"\"\n\n\nclass PushFailedError(Exception):\n  \"\"\"Pushing a file failed for some reason.\"\"\"\n\n\nDeviceFile = collections.namedtuple('DeviceFile', [\n    'filename', 'mode', 'size', 'mtime'])\n\n\nclass FilesyncProtocol(object):\n  \"\"\"Implements the FileSync protocol as described in sync.txt.\"\"\"\n\n  @staticmethod\n  def Stat(connection, filename):\n    cnxn = FileSyncConnection(connection, '<4I')\n    cnxn.Send('STAT', filename)\n    command, (mode, size, mtime) = cnxn.Read(('STAT',), read_data=False)\n\n    if command != 'STAT':\n      raise adb_protocol.InvalidResponseError(\n          'Expected STAT response to STAT, got %s' % command)\n    return mode, size, mtime\n\n  @classmethod\n  def List(cls, connection, path):\n    cnxn = FileSyncConnection(connection, '<5I')\n    cnxn.Send('LIST', path)\n    files = []\n    for cmd_id, header, filename in cnxn.ReadUntil(('DENT',), 'DONE'):\n      if cmd_id == 'DONE':\n        break\n      mode, size, mtime = header\n      files.append(DeviceFile(filename, mode, size, mtime))\n    return files\n\n  @classmethod\n  def Pull(cls, connection, filename, dest_file):\n    \"\"\"Pull a file from the device into the file-like dest_file.\"\"\"\n    cnxn = FileSyncConnection(connection, '<2I')\n    cnxn.Send('RECV', filename)\n    for cmd_id, _, data in cnxn.ReadUntil(('DATA',), 'DONE'):\n      if cmd_id == 'DONE':\n        break\n      dest_file.write(data)\n\n  @classmethod\n  def Push(cls, connection, datafile, filename,\n           st_mode=DEFAULT_PUSH_MODE, mtime=0):\n    \"\"\"Push a file-like object to the device.\n\n    Args:\n      connection: ADB connection\n      datafile: File-like object for reading from\n      filename: Filename to push to\n      st_mode: stat mode for filename\n      mtime: modification time\n\n    Raises:\n      PushFailedError: Raised on push failure.\n    \"\"\"\n    fileinfo = '%s,%s' % (filename, st_mode)\n\n    cnxn = FileSyncConnection(connection, '<2I')\n    cnxn.Send('SEND', fileinfo)\n\n    while True:\n      data = datafile.read(MAX_PUSH_DATA)\n      if not data:\n        break\n      cnxn.Send('DATA', data)\n\n    if mtime == 0:\n      mtime = int(time.time())\n    # DONE doesn't send data, but it hides the last bit of data in the size\n    # field.\n    cnxn.Send('DONE', size=mtime)\n    for cmd_id, _, data in cnxn.ReadUntil((), 'OKAY', 'FAIL'):\n      if cmd_id == 'OKAY':\n        return\n      raise PushFailedError(data)\n\n\nclass FileSyncConnection(object):\n  \"\"\"Encapsulate a FileSync service connection.\"\"\"\n\n  ids = [\n      'STAT', 'LIST', 'SEND', 'RECV', 'DENT', 'DONE', 'DATA', 'OKAY',\n      'FAIL', 'QUIT',\n  ]\n  id_to_wire, wire_to_id = adb_protocol.MakeWireIDs(ids)\n\n  def __init__(self, adb_connection, recv_header_format):\n    self.adb = adb_connection\n\n    # Sending\n    self.send_buffer = ''\n    self.send_header_len = struct.calcsize('<2I')\n\n    # Receiving\n    self.recv_buffer = ''\n    self.recv_header_format = recv_header_format\n    self.recv_header_len = struct.calcsize(recv_header_format)\n\n  def Send(self, command_id, data='', size=0):\n    \"\"\"Send/buffer FileSync packets.\n\n    Packets are buffered and only flushed when this connection is read from. All\n    messages have a response from the device, so this will always get flushed.\n\n    Args:\n      command_id: Command to send.\n      data: Optional data to send, must set data or size.\n      size: Optionally override size from len(data).\n    \"\"\"\n    if data:\n      size = len(data)\n\n    if not self._CanAddToSendBuffer(len(data)):\n      self._Flush()\n\n    header = struct.pack('<2I', self.id_to_wire[command_id], size)\n    self.send_buffer += header + data\n\n  def Read(self, expected_ids, read_data=True):\n    \"\"\"Read ADB messages and return FileSync packets.\"\"\"\n    if self.send_buffer:\n      self._Flush()\n\n    # Read one filesync packet off the recv buffer.\n    header_data = self._ReadBuffered(self.recv_header_len)\n    header = struct.unpack(self.recv_header_format, header_data)\n    # Header is (ID, ...).\n    command_id = self.wire_to_id[header[0]]\n\n    if command_id not in expected_ids:\n      if command_id == 'FAIL':\n        raise usb_exceptions.AdbCommandFailureException('Command failed.')\n      raise adb_protocol.InvalidResponseError(\n          'Expected one of %s, got %s' % (expected_ids, command_id))\n\n    if not read_data:\n      return command_id, header[1:]\n\n    # Header is (ID, ..., size).\n    size = header[-1]\n    data = self._ReadBuffered(size)\n    return command_id, header[1:-1], data\n\n  def ReadUntil(self, expected_ids, *finish_ids):\n    \"\"\"Useful wrapper around Read.\"\"\"\n    while True:\n      cmd_id, header, data = self.Read(expected_ids + finish_ids)\n      yield cmd_id, header, data\n      if cmd_id in finish_ids:\n        break\n\n  def _CanAddToSendBuffer(self, data_len):\n    added_len = self.send_header_len + data_len\n    return len(self.send_buffer) + added_len < adb_protocol.MAX_ADB_DATA\n\n  def _Flush(self):\n    self.adb.Write(self.send_buffer)\n    self.send_buffer = ''\n\n  def _ReadBuffered(self, size):\n    # Ensure recv buffer has enough data.\n    while len(self.recv_buffer) < size:\n      _, data = self.adb.ReadUntil('WRTE')\n      self.recv_buffer += data\n\n    result = self.recv_buffer[:size]\n    self.recv_buffer = self.recv_buffer[size:]\n    return result\n\n"
  },
  {
    "path": "scripts/adb/filesync_protocol.txt",
    "content": "The missing sync.txt from android's ADB.\n\nMessage Format:\n  Every message starts with a single 32-bit word. (Everything is little-endian).\n  Depending on that first word, the rest of the data can have various meanings.\n  Messages from the host/desktop to the device always start with a 'request'\n    message of a u32 command, u32 size, and size more bytes that's a filename,\n    directory or symlink.\n  The command here is referred to as 'id' in the code and the 4-letter codes\n    are prefixed by ID_, eg ID_STAT.\n\n  STAT:\n    request:\n      u32 command = 'STAT' == 0x53544154\n      u32 size = len(filename) < 1024\n      u8 data[size] = filename (no null)\n\n    response:\n      struct stat st = lstat(filename)\n      u32 command = 'STAT'\n      u32 mode = st.st_mode\n      u32 size = st.st_size\n      u32 time = st.st_mtime\n\n  LIST:\n    request:\n      u32 command = 'LIST' == 0x4C495354\n      u32 size = len(path) < 1024\n      u8 data[size] = path (no null)\n\n    response:\n    for each filename in listing of path:\n      struct stat st = lstat(filename)\n      u32 command = 'DENT' == 0x44454E54\n      u32 mode = st.st_mode\n      u32 size = st.st_size\n      u32 time = st.st_mtime\n      u32 namelen = len(filename)\n      u8 data[namelen] = filename\n\n    done (device -> host):\n      u32 command = 'DONE' == 0x444F4E45\n      u32[4] = 0\n\n  SEND:\n    struct stat st = lstat(filename)\n    request:\n      fileinfo = sprintf(',%d', st.st_mode)\n      u32 command = 'SEND' == 0x53454E44\n      u32 size = len(filename) + len(fileinfo) < 1024\n      u8 data[size] = filename + fileinfo\n\n    repeated data command (host -> device):\n      u32 command = 'DATA' == 0x44415441\n      u32 size < (64 * 1024)\n      u8 data[size] = file contents\n\n    finish command (host -> device):\n      u32 command = 'DONE' == 0x444F4E45\n      u32 timestamp = st.st_mtime\n\n    response (device -> host):\n      u32 command = 'OKAY' == 0x4F4B4159 or 'FAIL' == 0x4641494C\n      u32 size = 0 if 'OKAY' else len(fail_message)\n      u8 data[] = fail_message\n\n  RECV:\n    request:\n      u32 command = 'RECV' == 0x52454356\n      u32 size = len(filename)\n      u8 data[size] = filename\n\n    repeated data response (device -> host):\n      u32 command = 'DATA' == 0x44415441\n      u32 size < (64 * 1024)\n      u8 data[size] = file contents\n\n    finish response (device -> host):\n      u32 command = 'DONE' == 0x444F4E45\n      u32 size = 0\n\n"
  },
  {
    "path": "scripts/adb/usb_exceptions.py",
    "content": "# Copyright 2014 Google Inc. All rights reserved.\n#\n# Licensed under the Apache License, Version 2.0 (the \"License\");\n# you may not use this file except in compliance with the License.\n# You may obtain a copy of the License at\n#\n#     http://www.apache.org/licenses/LICENSE-2.0\n#\n# Unless required by applicable law or agreed to in writing, software\n# distributed under the License is distributed on an \"AS IS\" BASIS,\n# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n# See the License for the specific language governing permissions and\n# limitations under the License.\n\"\"\"Common exceptions for ADB and Fastboot.\"\"\"\n\n\nclass CommonUsbError(Exception):\n  \"\"\"Base class for usb communication errors.\"\"\"\n\n\nclass FormatMessageWithArgumentsException(CommonUsbError):\n  \"\"\"Exception that both looks good and is functional.\n\n  Okay, not that kind of functional, it's still a class.\n\n  This interpolates the message with the given arguments to make it\n  human-readable, but keeps the arguments in case other code try-excepts it.\n  \"\"\"\n\n  def __init__(self, message, *args):\n    message %= args\n    super(FormatMessageWithArgumentsException, self).__init__(message, *args)\n\n\nclass DeviceNotFoundError(FormatMessageWithArgumentsException):\n  \"\"\"Device isn't on USB.\"\"\"\n\n\nclass DeviceAuthError(FormatMessageWithArgumentsException):\n  \"\"\"Device authentication failed.\"\"\"\n\n\nclass LibusbWrappingError(CommonUsbError):\n  \"\"\"Wraps libusb1 errors while keeping its original usefulness.\n\n  Attributes:\n    usb_error: Instance of libusb1.USBError\n  \"\"\"\n\n  def __init__(self, msg, usb_error):\n    super(LibusbWrappingError, self).__init__(msg)\n    self.usb_error = usb_error\n\n  def __str__(self):\n    return '%s: %s' % (\n        super(LibusbWrappingError, self).__str__(), str(self.usb_error))\n\n\nclass WriteFailedError(LibusbWrappingError):\n  \"\"\"Raised when the device doesn't accept our command.\"\"\"\n\n\nclass ReadFailedError(LibusbWrappingError):\n  \"\"\"Raised when the device doesn't respond to our commands.\"\"\"\n\n\nclass AdbCommandFailureException(Exception):\n  \"\"\"ADB Command returned a FAIL.\"\"\"\n\n\nclass AdbOperationException(Exception):\n  \"\"\"Failed to communicate over adb with device after multiple retries.\"\"\"\n"
  },
  {
    "path": "scripts/aws/build.sh",
    "content": "#!/bin/bash\n\nscriptname=`which $0`\nscriptdir=`dirname $scriptname`\nscriptdir=`dirname $scriptdir`\nexport CONNECTALDIR=`dirname $scriptdir`\necho \"CONNECTALDIR=$CONNECTALDIR\"\n\nif [ \"$AWS_FPGA_BUCKET\" == \"\" ]; then\n    AWS_FPGA_BUCKET=aws-fpga\nfi\n\nif [ \"$AWS_FPGA_REPO_DIR\" == \"\" ]; then\n    if [ -d `dirname $CONNECTALDIR`/aws-fpga ]; then\n\tpushd `dirname $CONNECTALDIR`/aws-fpga\n\t. hdk_setup.sh\n\tpopd\n    fi\n    if [ -d ~/aws-fpga ]; then\n\tpushd ~/aws-fpga\n\t. hdk_setup.sh\n\tpopd\n    fi\nfi\n\nBUILD_DIR=`pwd`\necho BUILD_DIR=$BUILD_DIR\nif [ `basename $BUILD_DIR` = 'scripts' ]; then\n  cd ../..\nelse\n  mkdir -p design\n  mkdir -p build/checkpoints/to_aws\n  mkdir -p build/constraints\n  mkdir -p build/reports\n  mkdir -p build/scripts\n  mkdir -p build/src_post_encryption\n  BUILD_DIR=`pwd`/build/scripts\n  echo BUILD_DIR=$BUILD_DIR\nfi\n\n## copy the scripts into the build directory so we don't have to worry about paths\nrsync -v $CONNECTALDIR/scripts/aws/* $BUILD_DIR\n\nif [ ! -f $CONNECTALDIR/out/awsf1/ila_connectal_1/ila_connectal_1.xci ]; then\n    echo\n    echo 'Generating Integrated Logic Analyzer core'\n    echo\n    vivado -mode batch -source $CONNECTALDIR/scripts/connectal-synth-ila.tcl\n    echo \n    echo 'Finished generating Integrated Logic Analyzer core'\n    echo\nfi\nif [ ! -f $CONNECTALDIR/out/awsf1/axi_protocol_checker_0/axi_protocol_checker_0.xci ]; then\n    echo\n    echo 'Generating AXI Protocol Checker core'\n    echo\n    vivado -mode batch -source $CONNECTALDIR/scripts/connectal-synth-axichecker.tcl\n    echo\n    echo 'Finished generating AXI Protocol Checker core'\n    echo\nfi\n\nexport CL_DIR=`pwd`\ncd $BUILD_DIR\necho CL_DIR=$CL_DIR\necho BUILD_DIR=$BUILD_DIR\n\ncp -fv $CONNECTALDIR/verilog/cl_id_defines.vh $BUILD_DIR/../../design\n\necho '#placeholder' > ../constraints/cl_pnr_user.xdc\necho '#placeholder' > ../constraints/cl_synth_user.xdc\n\n## run Vivado to build the FPGA image\n$AWS_FPGA_REPO_DIR/hdk/common/shell_stable/build/scripts/aws_build_dcp_from_cl.sh -ignore_memory_requirement -notify -foreground \"$@\"\n\nPROJECT_DIR=`dirname $CL_DIR`\nPROJECT_NAME=`basename $PROJECT_DIR`\necho PROJECT_NAME=${PROJECT_NAME}\n\n## return to $CL_DIR\ncd $CL_DIR\n## and now should be in awsf1 subdirectory of $PROJECT_DIR\npwd\n\nlast_log=`realpath build/scripts/last_log`\necho last_log=${last_log}\nbuild_timestamp=`basename ${last_log} .vivado.log`\necho build_timestamp=${build_timestamp}\n\n##\n## if build completed successfully, request AWS to create an FPGA image\n##\nif [ -f build/checkpoints/to_aws/${build_timestamp}.Developer_CL.tar ]; then\n    ## request AWS to create an AWS FPGA image\n    $CONNECTALDIR/scripts/aws/create-fpga-image.sh $PROJECT_NAME $build_timestamp $AWS_FPGA_BUCKET \\\n\t&& ( sleep 1; \n\t     ## query AWS to make sure the FPGA image is building\n\t     $CONNECTALDIR/scripts/aws/describe-latest-fpga-image.sh )\nfi\n\nif [ \"$EMAIL\" != \"\" ]; then\n    echo \"Connectal AWS FPGA: - Calling notification script to send e-mail to $EMAIL\";\n    ${CONNECTALDIR}/scripts/aws/notify_via_sns.py --build-project ${PROJECT_NAME} --filename ${filename} --timestamp ${build_timestamp} --fpga-image-ids `cat latest-fpga-image.json`\nfi\n\n"
  },
  {
    "path": "scripts/aws/create-fpga-image.sh",
    "content": "#!/bin/bash\n\nname=$1\ntimestamp=$2\nbucket=\"aws-fpga\"\n\nif [ \"$AWS_FPGA_BUCKET\" != \"\" ]; then\n    bucket=\"$AWS_FPGA_BUCKET\"\nfi\n\nif [ \"$name\" == \"\" -o \"$timestamp\" == \"\" ]; then\n    echo \"usage: $0 <name> <timestamp> [s3 bucket]\" >&2\n    exit -1\nfi\n\nif [ \"$3\" != \"\" ]; then\n    bucket=\"$3\"\nfi\n\nif [ -d \"build/checkpoints\" ]; then\n    CHECKPOINTS_DIR=\"build/checkpoints\"\nfi\nif [ -d \"awsf1/build/checkpoints\" ]; then\n    CHECKPOINTS_DIR=\"awsf1/build/checkpoints\"\nfi\n\naws s3 cp $CHECKPOINTS_DIR/to_aws/$timestamp.Developer_CL.tar s3://$bucket/$name/\naws s3 cp $CHECKPOINTS_DIR/$timestamp.debug_probes.ltx s3://$bucket/$name/\naws ec2 create-fpga-image --name $name --description $timestamp --input-storage-location Bucket=$bucket,Key=$name/$timestamp.Developer_CL.tar --logs-storage-location Bucket=$bucket,Key=logs-folder | tee latest-fpga-image.json\n"
  },
  {
    "path": "scripts/aws/create_dcp_from_cl.tcl",
    "content": "# Amazon FPGA Hardware Development Kit\n#\n# Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved.\n#\n# Licensed under the Amazon Software License (the \"License\"). You may not use\n# this file except in compliance with the License. A copy of the License is\n# located at\n#\n#    http://aws.amazon.com/asl/\n#\n# or in the \"license\" file accompanying this file. This file is distributed on\n# an \"AS IS\" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or\n# implied. See the License for the specific language governing permissions and\n# limitations under the License.\n\npackage require tar\n\n## Do not edit $TOP\nset TOP top_sp\n\n## Replace with the name of your module\nset CL_MODULE awsf1\n\n#################################################\n## Command-line Arguments\n#################################################\nset timestamp           [lindex $argv  0]\nset strategy            [lindex $argv  1]\nset hdk_version         [lindex $argv  2]\nset shell_version       [lindex $argv  3]\nset device_id           [lindex $argv  4]\nset vendor_id           [lindex $argv  5]\nset subsystem_id        [lindex $argv  6]\nset subsystem_vendor_id [lindex $argv  7]\nset clock_recipe_a      [lindex $argv  8]\nset clock_recipe_b      [lindex $argv  9]\nset clock_recipe_c      [lindex $argv 10]\nset uram_option         [lindex $argv 11]\nset notify_via_sns      [lindex $argv 12]\n\n##################################################\n## Flow control variables \n##################################################\nset cl.synth   1\nset implement  1\n\n#################################################\n## Generate CL_routed.dcp (Done by User)\n#################################################\nputs \"AWS FPGA Scripts\";\nputs \"Creating Design Checkpoint from Custom Logic source code\";\nputs \"HDK Version:            $hdk_version\";\nputs \"Shell Version:          $shell_version\";\nputs \"Vivado Script Name:     $argv0\";\nputs \"Strategy:               $strategy\";\nputs \"PCI Device ID           $device_id\";\nputs \"PCI Vendor ID           $vendor_id\";\nputs \"PCI Subsystem ID        $subsystem_id\";\nputs \"PCI Subsystem Vendor ID $subsystem_vendor_id\";\nputs \"Clock Recipe A:         $clock_recipe_a\";\nputs \"Clock Recipe B:         $clock_recipe_b\";\nputs \"Clock Recipe C:         $clock_recipe_c\";\nputs \"URAM option:            $uram_option\";\nputs \"Notify when done:       $notify_via_sns\";\n\n#checking if CL_DIR env variable exists\nif { [info exists ::env(CL_DIR)] } {\n        set CL_DIR $::env(CL_DIR)\n        puts \"Using CL directory $CL_DIR\";\n} else {\n        puts \"Error: CL_DIR environment variable not defined ! \";\n        puts \"Use export CL_DIR=Your_Design_Root_Directory\"\n        exit 2\n}\n\n#checking if HDK_SHELL_DIR env variable exists\nif { [info exists ::env(HDK_SHELL_DIR)] } {\n        set HDK_SHELL_DIR $::env(HDK_SHELL_DIR)\n        puts \"Using Shell directory $HDK_SHELL_DIR\";\n} else {\n        puts \"Error: HDK_SHELL_DIR environment variable not defined ! \";\n        puts \"Run the hdk_setup.sh script from the root directory of aws-fpga\";\n        exit 2\n}\n\n#checking if HDK_SHELL_DESIGN_DIR env variable exists\nif { [info exists ::env(HDK_SHELL_DESIGN_DIR)] } {\n        set HDK_SHELL_DESIGN_DIR $::env(HDK_SHELL_DESIGN_DIR)\n        puts \"Using Shell design directory $HDK_SHELL_DESIGN_DIR\";\n} else {\n        puts \"Error: HDK_SHELL_DESIGN_DIR environment variable not defined ! \";\n        puts \"Run the hdk_setup.sh script from the root directory of aws-fpga\";\n        exit 2\n}\n\nif [info exists ::env(BUILD_PROJECT)] {\n    set projname $::env(BUILD_PROJECT)\n} else {\n    set projname [file tail [file dirname $CL_DIR]]\n}\nif [info exists ::env(BUILD_USER)] {\n    set build_user $::env(BUILD_USER)\n    set imagename \"${build_user} ${projname}\"\n} elseif [info exists ::env(USER)] {\n    set build_user $::env(USER)\n    set imagename \"${build_user} ${projname}\"\n} else {\n    set build_user \"default\"\n    set imagename \"${projname}\"\n}\n\nset s3_key \"${build_user}/${projname}\"\nset s3_folder \"s3://aws-fpga/${s3_key}\"\nputs \"BUILD_USER ${build_user} BUILD_PROJECT ${projname} S3_FOLDER ${s3_folder}\"\n\n##################################################\n### Output Directories used by step_user.tcl\n##################################################\nset implDir   $CL_DIR/build/checkpoints\nset rptDir    $CL_DIR/build/reports\nset cacheDir  $HDK_SHELL_DESIGN_DIR/cache/ddr4_phy\n\nputs \"All reports and intermediate results will be time stamped with $timestamp\";\n\nset_msg_config -id {Chipscope 16-3} -suppress\nset_msg_config -string {AXI_QUAD_SPI} -suppress\n\n# Suppress Warnings\n# These are to avoid warning messages that may not be real issues. A developer\n# may comment them out if they wish to see more information from warning\n# messages.\nset_msg_config -id {Common 17-55}        -suppress\nset_msg_config -id {Vivado 12-4739}      -suppress\nset_msg_config -id {Constraints 18-4866} -suppress\nset_msg_config -id {IP_Flow 19-2162}     -suppress\nset_msg_config -id {Route 35-328}        -suppress\nset_msg_config -id {Vivado 12-1008}      -suppress\nset_msg_config -id {Vivado 12-508}       -suppress\nset_msg_config -id {filemgmt 56-12}      -suppress\nset_msg_config -id {DRC CKLD-1}          -suppress\nset_msg_config -id {DRC CKLD-2}          -suppress\nset_msg_config -id {IP_Flow 19-2248}     -suppress\nset_msg_config -id {Vivado 12-1580}      -suppress\nset_msg_config -id {Constraints 18-550}  -suppress\nset_msg_config -id {Synth 8-3295}        -suppress\nset_msg_config -id {Synth 8-3321}        -suppress\nset_msg_config -id {Synth 8-3331}        -suppress\nset_msg_config -id {Synth 8-3332}        -suppress\nset_msg_config -id {Synth 8-6014}        -suppress\nset_msg_config -id {Timing 38-436}       -suppress\nset_msg_config -id {DRC REQP-1853}       -suppress\nset_msg_config -id {Synth 8-350}         -suppress\nset_msg_config -id {Synth 8-3848}        -suppress\nset_msg_config -id {Synth 8-3917}        -suppress\n\nputs \"AWS FPGA: ([clock format [clock seconds] -format %T]) Calling the encrypt.tcl.\";\n\n# Check that an email address has been set, else unset notify_via_sns\n\nif {[string compare $notify_via_sns \"1\"] == 0} {\n  if {![info exists env(EMAIL)]} {\n    puts \"AWS FPGA: ([clock format [clock seconds] -format %T]) EMAIL variable empty!  Completition notification will *not* be sent!\";\n    set notify_via_sns 0;\n  } else {\n    puts \"AWS FPGA: ([clock format [clock seconds] -format %T]) EMAIL address for completion notification set to $env(EMAIL).\";\n  }\n}\n\n##################################################\n### Strategy options \n##################################################\nswitch $strategy {\n    \"BASIC\" {\n        puts \"BASIC strategy.\"\n        source $HDK_SHELL_DIR/build/scripts/strategy_BASIC.tcl\n    }\n    \"EXPLORE\" {\n        puts \"EXPLORE strategy.\"\n        source $HDK_SHELL_DIR/build/scripts/strategy_EXPLORE.tcl\n    }\n    \"TIMING\" {\n        puts \"TIMING strategy.\"\n        source $HDK_SHELL_DIR/build/scripts/strategy_TIMING.tcl\n    }\n    \"CONGESTION\" {\n        puts \"CONGESTION strategy.\"\n        source $HDK_SHELL_DIR/build/scripts/strategy_CONGESTION.tcl\n    }\n    \"DEFAULT\" {\n        puts \"DEFAULT strategy.\"\n        source $HDK_SHELL_DIR/build/scripts/strategy_DEFAULT.tcl\n    }\n    default {\n        puts \"$strategy is NOT a valid strategy. Defaulting to strategy DEFAULT.\"\n        source $HDK_SHELL_DIR/build/scripts/strategy_DEFAULT.tcl\n    }\n}\nif { [file exists $CL_DIR/strategy_OVERRIDES.tcl] } {\n    puts \"Custom OVERRIDES for strategy.\"\n    source $CL_DIR/strategy_OVERRIDES.tcl\n}\n\n#Encrypt source code\nsource encrypt.tcl\n\n#Set the Device Type\nsource $HDK_SHELL_DIR/build/scripts/device_type.tcl\n\n#Procedure for running various implementation steps (impl_step)\nsource $HDK_SHELL_DIR/build/scripts/step_user.tcl -notrace\n\n########################################\n## Generate clocks based on Recipe \n########################################\n\nputs \"AWS FPGA: ([clock format [clock seconds] -format %T]) Calling aws_gen_clk_constraints.tcl to generate clock constraints from developer's specified recipe.\";\n\nsource $HDK_SHELL_DIR/build/scripts/aws_gen_clk_constraints.tcl\n\n##################################################\n### CL XPR OOC Synthesis\n##################################################\nif {${cl.synth}} {\n   source -notrace ./synth_${CL_MODULE}.tcl\n}\n\n##################################################\n### Implementation\n##################################################\nif {$implement} {\n\n   ########################\n   # Link Design\n   ########################\n   if {$link} {\n      ####Create in-memory prjoect and setup IP cache location\n      create_project -part [DEVICE_TYPE] -in_memory\n      set_property IP_REPO_PATHS $cacheDir [current_project]\n      puts \"\\nAWS FPGA: ([clock format [clock seconds] -format %T]) - Combining Shell and CL design checkpoints\";\n      add_files $HDK_SHELL_DIR/build/checkpoints/from_aws/SH_CL_BB_routed.dcp\n      add_files $CL_DIR/build/checkpoints/${timestamp}.CL.post_synth.dcp\n      set_property SCOPED_TO_CELLS {WRAPPER_INST/CL} [get_files $CL_DIR/build/checkpoints/${timestamp}.CL.post_synth.dcp]\n\n      #Read the constraints, note *DO NOT* read cl_clocks_aws (clocks originating from AWS shell)\n      read_xdc [ list \\\n         $CL_DIR/build/constraints/cl_pnr_user.xdc\n      ]\n      set_property PROCESSING_ORDER late [get_files cl_pnr_user.xdc]\n\n      puts \"\\nAWS FPGA: ([clock format [clock seconds] -format %T]) - Running link_design\";\n      link_design -top $TOP -part [DEVICE_TYPE] -reconfig_partitions {WRAPPER_INST/SH WRAPPER_INST/CL}\n      report_timing -cell WRAPPER_INST/CL -delay_type max -max_paths 10 -sort_by group -input_pins -file  $rptDir/${timestamp}.postlinkdesign_timing_max.rpt\n      report_timing -cell WRAPPER_INST/CL -delay_type min -max_paths 10 -sort_by group -input_pins -file  $rptDir/${timestamp}.postlinkdesign_timing_min.rpt\n\n      puts \"\\nAWS FPGA: ([clock format [clock seconds] -format %T]) - PLATFORM.IMPL==[get_property PLATFORM.IMPL [current_design]]\";\n      ##################################################\n      # Apply Clock Properties for Clock Table Recipes\n      ##################################################\n      puts \"AWS FPGA: ([clock format [clock seconds] -format %T]) - Sourcing aws_clock_properties.tcl to apply properties to clocks. \";\n      \n      # Apply properties to clocks\n      source $HDK_SHELL_DIR/build/scripts/aws_clock_properties.tcl\n\n      # Write post-link checkpoint\n      puts \"\\nAWS FPGA: ([clock format [clock seconds] -format %T]) - Writing post-link_design checkpoint ${timestamp}.post_link.dcp\";\n      write_checkpoint -force $CL_DIR/build/checkpoints/${timestamp}.post_link.dcp\n   }\n\n   ########################\n   # CL Optimize\n   ########################\n   if {$opt} {\n      puts \"\\nAWS FPGA: ([clock format [clock seconds] -format %T]) - Running optimization\";\n      impl_step opt_design $TOP $opt_options $opt_directive $opt_preHookTcl $opt_postHookTcl\n      if {$psip} {\n         impl_step opt_design $TOP \"-merge_equivalent_drivers -sweep\"\n      }\n   }\n\n# Constraints for TCK<->Main Clock\n#set_clock_groups -name tck_clk_main_a0 -asynchronous -group [get_clocks -of_objects [get_pins static_sh/SH_DEBUG_BRIDGE/inst/bsip/inst/USE_SOFTBSCAN.U_TAP_TCKBUFG/O]] -group [get_clocks -of_objects [get_pins SH/kernel_clks_i/clkwiz_sys_clk/inst/CLK_CORE_DRP_I/clk_inst/mmcme3_adv_inst/CLKOUT0]]\n#set_clock_groups -name tck_drck -asynchronous -group [get_clocks -of_objects [get_pins static_sh/SH_DEBUG_BRIDGE/inst/bsip/inst/USE_SOFTBSCAN.U_TAP_TCKBUFG/O]] -group [get_clocks drck]\n#set_clock_groups -name tck_userclk -asynchronous -group [get_clocks -of_objects [get_pins static_sh/SH_DEBUG_BRIDGE/inst/bsip/inst/USE_SOFTBSCAN.U_TAP_TCKBUFG/O]] -group [get_clocks -of_objects [get_pins static_sh/pcie_inst/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_userclk/O]]\n\n\n   ########################\n   # CL Place\n   ########################\n   if {$place} {\n      puts \"\\nAWS FPGA: ([clock format [clock seconds] -format %T]) - Running placement\";\n      if {$psip} {\n         append place_options \" -fanout_opt\"\n      }\n      impl_step place_design $TOP $place_options $place_directive $place_preHookTcl $place_postHookTcl\n   }\n\n   ##############################\n   # CL Post-Place Optimization\n   ##############################\n   if {$phys_opt} {\n      puts \"\\nAWS FPGA: ([clock format [clock seconds] -format %T]) - Running post-place optimization\";\n      impl_step phys_opt_design $TOP $phys_options $phys_directive $phys_preHookTcl $phys_postHookTcl\n   }\n\n   ########################\n   # CL Route\n   ########################\n   if {$route} {\n      puts \"\\nAWS FPGA: ([clock format [clock seconds] -format %T]) - Routing design\";\n      impl_step route_design $TOP $route_options $route_directive $route_preHookTcl $route_postHookTcl\n   }\n\n   ##############################\n   # CL Post-Route Optimization\n   ##############################\n   set SLACK [get_property SLACK [get_timing_paths]]\n   #Post-route phys_opt will not be run if slack is positive or greater than -200ps.\n   if {$route_phys_opt && $SLACK > -0.400 && $SLACK < 0} {\n      puts \"\\nAWS FPGA: ([clock format [clock seconds] -format %T]) - Running post-route optimization\";\n      impl_step route_phys_opt_design $TOP $post_phys_options $post_phys_directive $post_phys_preHookTcl $post_phys_postHookTcl\n   }\n\n   ##############################\n   # Final Implmentation Steps\n   ##############################\n   # Report final timing\n   report_timing_summary -file $CL_DIR/build/reports/${timestamp}.SH_CL_final_timing_summary.rpt\n\n   # This is what will deliver to AWS\n   puts \"AWS FPGA: ([clock format [clock seconds] -format %T]) - Writing final DCP to to_aws directory.\";\n\n   write_checkpoint -force $CL_DIR/build/checkpoints/to_aws/${timestamp}.SH_CL_routed.dcp\n\n   # Generate debug probes file\n   write_debug_probes -force -no_partial_ltxfile -file $CL_DIR/build/checkpoints/${timestamp}.debug_probes.ltx\n\n   close_project\n}\n\n# ################################################\n# Create Manifest and Tarball for delivery\n# ################################################\n\n# Create a zipped tar file, that would be used for createFpgaImage EC2 API\n\nputs \"AWS FPGA: ([clock format [clock seconds] -format %T]) - Compress files for sending to AWS. \"\n\n# Create manifest file\nset manifest_file [open \"$CL_DIR/build/checkpoints/to_aws/${timestamp}.manifest.txt\" w]\nset hash [lindex [split [exec sha256sum $CL_DIR/build/checkpoints/to_aws/${timestamp}.SH_CL_routed.dcp] ] 0]\nset vivado_version [string range [version -short] 0 5]\nputs \"vivado_version is $vivado_version\\n\"\n\nputs $manifest_file \"manifest_format_version=2\\n\"\nputs $manifest_file \"pci_vendor_id=$vendor_id\\n\"\nputs $manifest_file \"pci_device_id=$device_id\\n\"\nputs $manifest_file \"pci_subsystem_id=$subsystem_id\\n\"\nputs $manifest_file \"pci_subsystem_vendor_id=$subsystem_vendor_id\\n\"\nputs $manifest_file \"dcp_hash=$hash\\n\"\nputs $manifest_file \"shell_version=$shell_version\\n\"\nputs $manifest_file \"tool_version=v$vivado_version\\n\"\nputs $manifest_file \"dcp_file_name=${timestamp}.SH_CL_routed.dcp\\n\"\nputs $manifest_file \"hdk_version=$hdk_version\\n\"\nputs $manifest_file \"date=$timestamp\\n\"\nputs $manifest_file \"clock_recipe_a=$clock_recipe_a\\n\"\nputs $manifest_file \"clock_recipe_b=$clock_recipe_b\\n\"\nputs $manifest_file \"clock_recipe_c=$clock_recipe_c\\n\"\n\nclose $manifest_file\n\n# Delete old tar file with same name\nif { [file exists $CL_DIR/build/checkpoints/to_aws/${timestamp}.Developer_CL.tar] } {\n        puts \"Deleting old tar file with same name.\";\n        file delete -force $CL_DIR/build/checkpoints/to_aws/${timestamp}.Developer_CL.tar\n}\n\n# Tar checkpoint to aws\ncd $CL_DIR/build/checkpoints\ntar::create to_aws/${timestamp}.Developer_CL.tar [glob to_aws/${timestamp}*]\nputs \"AWS FPGA: ([clock format [clock seconds] -format %T]) - Finished creating final tar file in to_aws directory.\";\n\nputs \"AWS FPGA: ([clock format [clock seconds] -format %T]) - Build complete.\";\n\n\n"
  },
  {
    "path": "scripts/aws/describe-latest-fpga-image.sh",
    "content": "#!/bin/bash\n\nif [ -f awsf1/latest-fpga-image.json ]; then\n    aws ec2 describe-fpga-images --fpga-image-ids `jq -r .FpgaImageId < awsf1/latest-fpga-image.json`\nfi\nif [ -f latest-fpga-image.json ]; then\n    aws ec2 describe-fpga-images --fpga-image-ids `jq -r .FpgaImageId < latest-fpga-image.json`\nfi\n\n"
  },
  {
    "path": "scripts/aws/encrypt.tcl",
    "content": "# Amazon FPGA Hardware Development Kit\n#\n# Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved.\n#\n# Licensed under the Amazon Software License (the \"License\"). You may not use\n# this file except in compliance with the License. A copy of the License is\n# located at\n#\n#    http://aws.amazon.com/asl/\n#\n# or in the \"license\" file accompanying this file. This file is distributed on\n# an \"AS IS\" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or\n# implied. See the License for the specific language governing permissions and\n# limitations under the License.\n\n# TODO:\n# Add check if CL_DIR and HDK_SHELL_DIR directories exist\n# Add check if /build and /build/src_port_encryption directories exist\n# Add check if the vivado_keyfile exist\n\nset HDK_SHELL_DIR $::env(HDK_SHELL_DIR)\nset HDK_SHELL_DESIGN_DIR $::env(HDK_SHELL_DESIGN_DIR)\nset CL_DIR $::env(CL_DIR)\nset TARGET_DIR $CL_DIR/build/src_post_encryption\nset UNUSED_TEMPLATES_DIR $HDK_SHELL_DESIGN_DIR/interfaces\nset BLUESPECDIR $::env(BLUESPECDIR)\nset CONNECTALDIR $::env(CONNECTALDIR)\n\n# Remove any previously encrypted files, that may no longer be used\nexec rm -f $TARGET_DIR/*\n\n#---- Developr would replace this section with design files ----\n\n## Change file names and paths below to reflect your CL area.  DO NOT include AWS RTL files.\n\nforeach {file} [glob -nocomplain -- $CL_DIR/verilog/*.v $CL_DIR/verilog/*.sv $CL_DIR/verilog/*.vh $CL_DIR/generatedbsv/ConnectalProjectConfig.bsv] {\n    file copy -force $file            $TARGET_DIR\n}\nforeach {dir} \"$BLUESPECDIR/Verilog $BLUESPECDIR/Verilog.Vivado $CONNECTALDIR/verilog $HDK_SHELL_DIR/design/interfaces\" {\n    puts \"Looking in directory $dir\"\n    foreach {pat} {FIFO BRAM Reg Counter Reset Sync cl_ unused aws} {\n\tforeach {file} [glob -nocomplain -- $dir/*$pat*.v $dir/*$pat*.vh $dir/*$pat*.inc $dir/*$pat*.sv] {\n\t    puts \"Copying file $file\"\n\t    file copy -force $file            $TARGET_DIR\n\t}\n    }\n}\n\n#---- End of section replaced by Developr ---\n\n# Make sure files have write permissions for the encryption\nexec chmod +w {*}[glob $TARGET_DIR/*]\n\n# encrypt .v/.sv/.vh/inc as verilog files\n# encrypt -k $HDK_SHELL_DIR/build/scripts/vivado_keyfile.txt -lang verilog  [glob -nocomplain -- $TARGET_DIR/*.{v,sv}]\n## [glob -nocomplain -- $TARGET_DIR/*.vh] [glob -nocomplain -- $TARGET_DIR/*.inc]\n\n# encrypt *vhdl files\n# encrypt -k $HDK_SHELL_DIR/build/scripts/vivado_vhdl_keyfile.txt -lang vhdl -quiet [ glob -nocomplain -- $TARGET_DIR/*.vhd? ]\n\n\n"
  },
  {
    "path": "scripts/aws/notify_via_sns.py",
    "content": "#!/usr/bin/env python33\n\n# Amazon FPGA Hardware Development Kit\n#\n# Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved.\n#\n# Licensed under the Amazon Software License (the \"License\"). You may not use\n# this file except in compliance with the License. A copy of the License is\n# located at\n#\n#    http://aws.amazon.com/asl/\n#\n# or in the \"license\" file accompanying this file. This file is distributed on\n# an \"AS IS\" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or\n# implied. See the License for the specific language governing permissions and\n# limitations under the License.\n\nfrom __future__ import print_function\n\nimport argparse\nimport base64\nimport boto3\nimport json\nimport os\nimport sys\nimport requests\nimport hmac\n\nargparser = argparse.ArgumentParser(description=\"Notify via email or HTTP that FPGA CL build is complete\")\nargparser.add_argument('--email', help='Email to notify', default=os.environ.get('SNS_NOTIFY_EMAIL', None))\nargparser.add_argument('--sns-notify-url', help='url to notify via SNS', default=os.environ.get('SNS_NOTIFY_URL', None))\nargparser.add_argument('--notify-url', help='url to notify via POST', default=os.environ.get('NOTIFY_URL', None))\nargparser.add_argument('--secret-key-file', help='File containing base64 encoded secret key for signing message sent to notify_url', default=os.environ.get('NOTIFY_SECRET_KEY_FILE', None))\nargparser.add_argument('--build-user', help='User performing build', default=os.environ.get('BUILD_USER', 'default'))\nargparser.add_argument('--build-project', help='Name of project built', default=os.environ.get('BUILD_PROJECT', None))\nargparser.add_argument('--filename', help='Name of checkpoint archive', default=None)\nargparser.add_argument('--timestamp', help='Timestamp of build', default=None)\nargparser.add_argument('--sourcehash', help='md5sum of the RTL', default=None)\nargparser.add_argument('--fpga-image-ids', help='JSON output from aws ec2 create-fpga-image', default=None)\noptions = argparser.parse_args()\n\nsns = boto3.client('sns')\ntopic_resp = sns.create_topic(Name=\"FPGA_CL_BUILD_%s\" % options.build_user)\nprint(topic_resp['TopicArn'])\n\nif options.sns_notify_url:\n    topic_resp_json = sns.create_topic(Name=\"FPGA_CL_BUILD_JSON\")\n    list_resp_json = sns.list_subscriptions_by_topic(TopicArn=topic_resp_json['TopicArn'])\n    if not any(i['Endpoint'] == options.sns_notify_url for i in list_resp_json.get('Subscriptions')):\n        print(\"Subscribing to the FPGA_CL_BUILD topic\")\n        sub_resp_json = sns.subscribe(TopicArn=topic_resp_json['TopicArn'], Protocol='http', Endpoint=options.sns_notify_url)\n        print(sub_resp_json)\n\nlist_resp = sns.list_subscriptions_by_topic(TopicArn=topic_resp['TopicArn'])\n\nif list_resp.get('Subscriptions'):\n    print(list_resp.get('Subscriptions'))\n\nif options.email is None:\n    print('Please set your EMAIL environment variable to your email address.')\n    sys.exit(1)\n\nprint(\"Using email address: %s\" % options.email)\n\n# subscribe if email is not in list\nif not any(i['Endpoint'] == options.email for i in list_resp.get('Subscriptions')):\n    print(\"Subscribing to the FPGA_CL_BUILD topic\")\n    sub_resp = sns.subscribe(TopicArn=topic_resp['TopicArn'], Protocol='email', Endpoint=options.email)\n    print(sub_resp)\n\nmessage_dict = { 'subject': 'Your FPGA CL build is complete.',\n                 'user': options.build_user,\n                 'email': options.email,\n                 'project': options.build_project,\n                 'filename': options.filename,\n                 'timestamp': options.timestamp,\n                 'sourceHash': options.sourcehash,\n                 'fpgaImageId': '',\n                 'fpgaImageGlobalId': '',\n}\nif options.fpga_image_ids:\n    fpga_image_ids = json.loads(options.fpga_image_ids)\n    message_dict['fpgaImageId'] = fpga_image_ids.get('FpgaImageId', '')\n    message_dict['fpgaImageGlobalId'] = fpga_image_ids.get('FpgaImageGlobalId', '')\n\nemail_message_template = '''\nYour FPGA CL build is complete:\n    Project: %(project)s\n    Timestamp: %(timestamp)s\n    FPGA Image Id: %(fpgaImageId)s \n    FPGA Image Global Id: %(fpgaImageGlobalId)s\n'''\n\npub_resp = sns.publish(TopicArn=topic_resp['TopicArn'],\n                       Message=email_message_template % message_dict,\n                       Subject='Your FPGA CL build is complete.')\nif options.sns_notify_url:\n    print('notifying %s' % options.sns_notify_url);\n    imageIds = json.loads(options.fpga_image_ids) if options.fpga_image_ids else None\n    pub_resp = sns.publish(TopicArn=topic_resp_json['TopicArn'],\n                           Message=json.dumps(message_dict),\n                           Subject='Your FPGA CL build is complete.')\n\nif options.notify_url:\n    message = bytes(json.dumps(message_dict), 'utf8')\n    signature = None\n    if options.secret_key_file:\n        secret_key_b64 = open(options.secret_key_file, 'r').read()\n        secret_key = base64.b64decode(secret_key_b64)\n        signature = hmac.new(secret_key, message).hexdigest()\n    data = {'message': message, 'signature': signature }\n    resp = requests.post(options.notify_url, data=data)\n    print('Posting to url %s \\n data %s' % (options.notify_url, data))\n    print('Posted to url %s got response %s' % (options.notify_url, resp))\n    print(json.dumps({'message': message.decode('utf8'), 'signature': signature }))\n\nsys.exit(0)\n"
  },
  {
    "path": "scripts/aws/run.awsf1",
    "content": "#!/bin/bash\n#set -x\nset -e\nexport SCRIPT_DIR=\"$( cd \"$( dirname \"$0\" )\" && pwd )\"\necho \"run.awsf1 parameters are:\" $*\nSSHPARAM=\" -o StrictHostKeyChecking=no\"\n\nif [ \"$1\" == \"\" ]; then\n    echo \"usage: $0 ubuntu.exe\" >&2\n    exit -1\nfi\n\nif [ \"$RUNTIMELIMIT\" != \"\" ]; then\n    TIMELIMIT=$RUNTIMELIMIT\nelse\n    TIMELIMIT=3m\nfi\n\nENV=\"\"\nif [ \"$RUNENV\" != \"\" ]; then\n    for e in `env | grep $RUNENV | grep -v RUNENV | sed 's/=(.*)/=\\\"$1\\\"/'`; do\n\tENV=\"$ENV $e\"\n    done\nfi\n\nif [ \"$RUNPARAM\" != \"\" ]; then\n    if [ \"$ENV\" != \"\" ]; then\n\techo \"sending environment variables $ENV\"\n    fi\n    RUNPARAMTEMP=$RUNPARAM:22\n    array=(${RUNPARAMTEMP//:/ })\n    RUNIP=${array[0]}\n    RUNPORT=${array[1]}\n    TEMPDIR=/tmp/`uname -n`-$PPID-pcie\n\n    if [ \"$INSTANCE_ID\" != \"\" ]; then\n\taws ec2 start-instances --instance-ids $INSTANCE_ID\n\twhile true; do\n\t    ssh -o ConnectTimeout=10 -p $RUNPORT $RUNIP uptime && break\n\tdone\n    fi\n\n    ssh $SSHPARAM -p $RUNPORT $RUNIP \"rm -rf $TEMPDIR; mkdir -p $TEMPDIR\" || exit 1\n    EXE=$1\n    EXENAME=`basename $1`\n    ARGS=\"\"\n    shift\n\n    scp -P $RUNPORT $EXE $RUNIP:$TEMPDIR || exit 2\n    for arg in $*; do\n\tif [ -f \"$arg\" ]; then\n\t    scp -P $RUNPORT $arg $RUNIP:$TEMPDIR || exit 2\n\t    arg_basename=`basename \"$arg\"`\n\t    ARGS=\"$ARGS $TEMPDIR/$arg_basename\"\n\telse\n\t    ARGS=\"$ARGS $arg\"\n\tfi\n    done\n    for f in $RUNFILES; do\n\tscp -P $RUNPORT $f $RUNIP:$TEMPDIR || exit 2\n    done\n    echo \"ARGS=$*\"\n    ssh $SSHPARAM -p $RUNPORT $RUNIP \"$ENV timeout $TIMELIMIT sudo fpga-load-local-image -S 0 -I $AGFI\"; status=$?\n    ssh $SSHPARAM -p $RUNPORT $RUNIP \"$ENV timeout $TIMELIMIT pciescanportal\"; status=$?\n    ssh $SSHPARAM -p $RUNPORT $RUNIP \"$ENV timeout $TIMELIMIT sudo modprobe portalmem\"; status=$?\n    ssh $SSHPARAM -p $RUNPORT $RUNIP \"$ENV timeout $TIMELIMIT sudo modprobe pcieportal\"; status=$?\n    #ssh $SSHPARAM -p $RUNPORT $RUNIP \"$ENV timeout $TIMELIMIT dmesg | tail -40\"; status=$?\n    ssh $SSHPARAM -p $RUNPORT $RUNIP \"cd $TEMPDIR; LD_LIBRARY_PATH=$TEMPDIR $ENV timeout $TIMELIMIT catchsegv $TEMPDIR/$EXENAME $ARGS\"; status=$?\n    ssh $SSHPARAM -p $RUNPORT $RUNIP \"rm -rf $TEMPDIR\"\n\n    if [ \"$INSTANCE_ID\" != \"\" ]; then\n\techo \"\"\n\techo \"Stopping instance $INSTANCE_ID\"\n\taws ec2 stop-instances --instance-ids $INSTANCE_ID\n    fi\n\n    exit $status\nelse\n    ## FIXME\n    timeout 3m catchsegv $1; status=$?\n    exit $status\nfi\n"
  },
  {
    "path": "scripts/aws/synth_awsf1.tcl",
    "content": "#Param needed to avoid clock name collisions\nset_param sta.enableAutoGenClkNamePersistence 0\nset CL_MODULE $CL_MODULE\n\ncreate_project -in_memory -part [DEVICE_TYPE] -force\n\nsource {../../board.tcl}\n\nif [info exists AWSF1_DDR_A] {\n    if {$AWSF1_DDR_A == \"\"} {\n\tset AWSF1_DDR_A 1\n    }\n    puts \"AWSF1_DDR_A=$AWSF1_DDR_A\"\n} else {\n    set AWSF1_DDR_A 0\n}\nif [info exists AWSF1_CL_DEBUG_BRIDGE] {\n    if {$AWSF1_CL_DEBUG_BRIDGE == \"\"} {\n\tset AWSF1_CL_DEBUG_BRIDGE 1\n    }\n    puts \"AWSF1_CL_DEBUG_BRIDGE=$AWSF1_CL_DEBUG_BRIDGE\"\n} else {\n    set AWSF1_CL_DEBUG_BRIDGE 0\n}\n\n\n########################################\n## Generate clocks based on Recipe \n########################################\n\nputs \"AWS FPGA: ([clock format [clock seconds] -format %T]) Calling aws_gen_clk_constraints.tcl to generate clock constraints from developer's specified recipe.\";\n\nsource $HDK_SHELL_DIR/build/scripts/aws_gen_clk_constraints.tcl\n\n#############################\n## Read design files\n#############################\n\n#Convenience to set the root of the RTL directory\nset ENC_SRC_DIR $CL_DIR/build/src_post_encryption\n\nputs \"AWS FPGA: ([clock format [clock seconds] -format %T]) Reading developer's Custom Logic files post encryption.\";\n\n#---- User would replace this section -----\n\n# Reading the .sv and .v files, as proper designs would not require\n# reading .v, .vh, nor .inc files\n\nread_verilog -sv [glob $ENC_SRC_DIR/*.sv] [glob $ENC_SRC_DIR/*.v]\n\nif {$AWSF1_CL_DEBUG_BRIDGE} {\n    puts \"Reading connectal ILA IP\"\n    read_ip [list \\\n\t     \"$CONNECTALDIR/out/awsf1/ila_connectal_1/ila_connectal_1.xci\" \\\n\t     \"$CONNECTALDIR/out/awsf1/ila_connectal_2/ila_connectal_2.xci\" \\\n\t     \"$CONNECTALDIR/out/awsf1/ila_connectal_3/ila_connectal_3.xci\" \\\n\t     \"$CONNECTALDIR/out/awsf1/axi_protocol_checker_0/axi_protocol_checker_0.xci\" \\\n\t    ]\n}\n\n#---- End of section replaced by User ----\n\nputs \"AWS FPGA: Reading AWS Shell design\";\n\n#Read AWS Design files\nread_verilog [list \\\n\t\t  $HDK_SHELL_DESIGN_DIR/lib/lib_pipe.sv \\\n\t\t  $HDK_SHELL_DESIGN_DIR/lib/bram_2rw.sv \\\n\t\t  $HDK_SHELL_DESIGN_DIR/lib/flop_fifo.sv \\\n\t\t  $HDK_SHELL_DESIGN_DIR/interfaces/cl_ports.vh \\\n\t\t  $HDK_SHELL_DESIGN_DIR/sh_ddr/synth/sync.v \\\n\t\t  $HDK_SHELL_DESIGN_DIR/sh_ddr/synth/flop_ccf.sv \\\n\t\t  $HDK_SHELL_DESIGN_DIR/sh_ddr/synth/ccf_ctl.v \\\n\t\t  $HDK_SHELL_DESIGN_DIR/sh_ddr/synth/mgt_acc_axl.sv \\\n\t\t  $HDK_SHELL_DESIGN_DIR/sh_ddr/synth/mgt_gen_axl.sv \\\n\t\t  $HDK_SHELL_DESIGN_DIR/sh_ddr/synth/sh_ddr.sv \\\n\t\t ]\n\nputs \"AWS FPGA: Reading IP blocks\";\n\n#Read DDR IP\nif {$AWSF1_DDR_A} {\n    read_ip [ list \\\n\t\t  $HDK_SHELL_DESIGN_DIR/ip/ddr4_core/ddr4_core.xci  \\\n\t     ]\n\n    # Additional IP's that might be needed if using the DDR\n    read_bd [list \\\n\t     $HDK_SHELL_DESIGN_DIR/ip/cl_axi_interconnect/cl_axi_interconnect.bd \\\n\t    ]\n}\n\n#Read IP for axi register slices\nread_ip [ list \\\n  $HDK_SHELL_DESIGN_DIR/ip/src_register_slice/src_register_slice.xci \\\n  $HDK_SHELL_DESIGN_DIR/ip/dest_register_slice/dest_register_slice.xci \\\n  $HDK_SHELL_DESIGN_DIR/ip/axi_clock_converter_0/axi_clock_converter_0.xci \\\n  $HDK_SHELL_DESIGN_DIR/ip/axi_register_slice/axi_register_slice.xci \\\n  $HDK_SHELL_DESIGN_DIR/ip/axi_register_slice_light/axi_register_slice_light.xci\n]\n\n#Read IP for virtual jtag / ILA/VIO\nread_ip [ list \\\n  $HDK_SHELL_DESIGN_DIR/ip/cl_debug_bridge/cl_debug_bridge.xci \\\n  $HDK_SHELL_DESIGN_DIR/ip/ila_1/ila_1.xci \\\n  $HDK_SHELL_DESIGN_DIR/ip/ila_0/ila_0.xci \\\n  $HDK_SHELL_DESIGN_DIR/ip/ila_vio_counter/ila_vio_counter.xci \\\n  $HDK_SHELL_DESIGN_DIR/ip/vio_0/vio_0.xci\n]\n\nputs \"AWS FPGA: Reading AWS constraints\";\n\n#Read all the constraints\n#\n#  cl_clocks_aws.xdc  - AWS auto-generated clock constraint.   ***DO NOT MODIFY***\n#  cl_ddr.xdc         - AWS provided DDR pin constraints.      ***DO NOT MODIFY***\n#  cl_synth_user.xdc  - Developer synthesis constraints.\nread_xdc [ list \\\n   $CL_DIR/build/constraints/cl_clocks_aws.xdc \\\n   $HDK_SHELL_DIR/build/constraints/cl_ddr.xdc \\\n   $HDK_SHELL_DIR/build/constraints/cl_synth_aws.xdc \\\n   $CL_DIR/build/constraints/cl_synth_user.xdc\n]\n\n#Do not propagate local clock constraints for clocks generated in the SH\nset_property USED_IN {synthesis implementation OUT_OF_CONTEXT} [get_files cl_clocks_aws.xdc]\nset_property PROCESSING_ORDER EARLY  [get_files cl_clocks_aws.xdc]\n\n########################\n# CL Synthesis\n########################\nputs \"AWS FPGA: ([clock format [clock seconds] -format %T]) Start design synthesis.\";\n\nupdate_compile_order -fileset sources_1\nputs \"\\nRunning synth_design for $CL_MODULE $CL_DIR/build/scripts \\[[clock format [clock seconds] -format {%a %b %d %H:%M:%S %Y}]\\]\"\neval [concat synth_design -top $CL_MODULE -verilog_define XSDB_SLV_DIS -part [DEVICE_TYPE] -mode out_of_context $synth_options -directive $synth_directive]\n\nset failval [catch {exec grep \"FAIL\" failfast.csv}]\nif { $failval==0 } {\n\tputs \"AWS FPGA: FATAL ERROR--Resource utilization error; check failfast.csv for details\"\n\texit 1\n}\n\nputs \"AWS FPGA: ([clock format [clock seconds] -format %T]) writing post synth checkpoint.\";\nwrite_checkpoint -force $CL_DIR/build/checkpoints/${timestamp}.CL.post_synth.dcp\n\nclose_project\n#Set param back to default value\nset_param sta.enableAutoGenClkNamePersistence 1\n"
  },
  {
    "path": "scripts/aws/upload.sh",
    "content": "#!/bin/bash\n\nfilename=$1\nif [ \"$filename\" = \"\" ]; then\n    echo Usage: $0 filename\n    exit 1\nfi\n\nbasename=`basename $filename .Developer_CL.tar`\necho \"basename=$basename\"\n\naws s3 cp ../checkpoints/to_aws/$filename s3://aws-fpga/simple/$filename\naws s3 cp ../checkpoints.$basename.debug_probes.ltx s3://aws-fpga/simple/$filename\naws ec2 create-fpga-image --name simple --description \"$filename\" --input-storage-location Bucket=aws-fpga,Key=simple/$filename --logs-storage-location Bucket=aws-fpga,Key=logs-folder\n"
  },
  {
    "path": "scripts/aws/wait_for_afi.py",
    "content": "#!/usr/bin/env python3\n\n# Amazon FPGA Hardware Development Kit\n#\n# Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved.\n#\n# Licensed under the Amazon Software License (the \"License\"). You may not use\n# this file except in compliance with the License. A copy of the License is\n# located at\n#\n#    http://aws.amazon.com/asl/\n#\n# or in the \"license\" file accompanying this file. This file is distributed on\n# an \"AS IS\" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or\n# implied. See the License for the specific language governing permissions and\n# limitations under the License.\n\nfrom __future__ import print_function\nimport argparse\nimport boto3\nimport datetime\nfrom datetime import datetime, timedelta\nimport logging\nimport json\nimport os\nimport re\nimport sys\nimport time\nimport traceback\ntry:\n    import aws_fpga_utils\n    logger = aws_fpga_utils.get_logger(__file__)\nexcept ImportError as e:\n    traceback.print_tb(sys.exc_info()[2])\n    print(\"warning: {}\\nMake sure to source hdk_setup.sh\".format(sys.exc_info()[1]))\n    logging.basicConfig(stream=sys.stderr, level=logging.INFO)\n    logger = logging.getLogger('aws-fpga')\n    aws_fpga_utils = None\n\nSLEEP_SECONDS = 60\nDEFAULT_MAX_DURATION_HOURS = 6\n\ndescription = '''\nWaits for AFI generation to complete.\n\nOptionally notifies an email address subscribed to an SNS topic.\nIf --notify is used then --email is required.\n'''\n\nif __name__ == '__main__':\n    parser = argparse.ArgumentParser(description=description)\n    parser.add_argument('--afi', action='store', required=True, help=\"AFI ID (not Global AFI ID)\")\n    parser.add_argument('--max-minutes', action='store', required=False, default=(DEFAULT_MAX_DURATION_HOURS * 60), help=\"Maximum minutes to wait. Default={}\".format(DEFAULT_MAX_DURATION_HOURS * 60))\n    parser.add_argument('--notify', action='store_true', default=False, required=False, help=\"Notify SNS topic when AFI generation completes.\")\n    parser.add_argument('--sns-topic', action='store', required=False, default='CREATE_AFI', help=\"SNS topic name to create/use for notification. Defaults to CREATE_AFI)\")\n    parser.add_argument('--email', action='store', required=False, default=None, help=\"Email address to subscribe to the SNS topic.\")\n    parser.add_argument('--debug', action='store_true', default=False, help=\"Enable debug messages\")\n    args = parser.parse_args()\n\n    if args.debug:\n        logger.setLevel(logging.DEBUG)\n\n    if args.afi.endswith('.json'):\n        with open(args.afi) as f:\n            ids = json.loads(f.read())\n            args.afi = ids.get('FpgaImageId').decode('utf8')\n\n    start_time = datetime.utcnow()\n\n    max_duration = timedelta(minutes=args.max_minutes)\n\n    logger.info(\"Waiting for {} generation to complete.\".format(args.afi))\n\n    if args.notify:\n        if not args.email:\n            logger.error(\"--email required with --notify.\")\n            sys.exit(1)\n        email = args.email\n        topic_name = args.sns_topic\n        logger.info(\"Will subscribe {} to SNS topic {} and notify the topic when complete\".format(email, topic_name))\n\n        if aws_fpga_utils:\n            topic_arn = aws_fpga_utils.create_sns_subscription(topic_name, email)\n\n    # Wait for create-fpga-image to complete\n    ec2_client = boto3.client('ec2')\n    create_fpga_image_complete = False\n    while not create_fpga_image_complete:\n        afi_info = ec2_client.describe_fpga_images(FpgaImageIds=[args.afi])['FpgaImages'][0]\n        afi_state = afi_info['State']['Code']\n        logger.debug(\"State={}\".format(afi_state))\n        if afi_state != 'pending':\n            if afi_state == 'available':\n                logger.info('AFI generation passed and AFI is available')\n            else:\n                afi_message = afi_info['State']['Message']\n                logger.error(\"AFI generation failed. State={} Message={}\".format(afi_state, afi_message))\n            create_fpga_image_complete = True\n        else:\n            current_time = datetime.utcnow()\n            if (current_time - start_time) > max_duration:\n                logger.error(\"Timed out waiting for AFI generation to complete.\")\n                sys.exit(1)\n            time.sleep(SLEEP_SECONDS)\n    passed = afi_state == 'available'\n\n    if args.notify:\n        if passed:\n            subject = \"create-fpga-image of {} passed\".format(args.afi)\n            message = \"State={}\".format(afi_state)\n        else:\n            subject = \"create-fpga-image of {} failed\".format(args.afi)\n            message = \"State={} Messsage={}\".format(afi_state, afi_message)\n        sns_client = boto3.client('sns')\n        pub_resp = sns_client.publish(TopicArn=topic_arn,\n                                      Subject=subject,\n                                      Message=message)\n    if passed:\n        sys.exit(0)\n    sys.exit(1)\n"
  },
  {
    "path": "scripts/boardinfo.py",
    "content": "#!/usr/bin/env python3\n# Copyright (c) 2014 Quanta Research Cambridge, Inc.\n#\n# Permission is hereby granted, free of charge, to any person\n# obtaining a copy of this software and associated documentation\n# files (the \"Software\"), to deal in the Software without\n# restriction, including without limitation the rights to use, copy,\n# modify, merge, publish, distribute, sublicense, and/or sell copies\n# of the Software, and to permit persons to whom the Software is\n# furnished to do so, subject to the following conditions:\n#\n# The above copyright notice and this permission notice shall be\n# included in all copies or substantial portions of the Software.\n#\n# THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n# EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n# MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n# BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n# ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n# CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n# SOFTWARE.\n\nfrom __future__ import print_function\nimport json, os, sys\n\nscripthome = os.path.dirname(os.path.abspath(__file__))\n\ndef attribute(boardname, name): \n    filename = scripthome + '/../boardinfo/' + boardname + '.json'\n    if not os.path.exists(filename):\n        print('boardinfo: The boardinfo file for the specified architecture does not exist \\'' + boardname + '\\'')\n        sys.exit(-1)\n    boardInfo = json.loads(open(filename).read())\n    return boardInfo[name]\n\nif __name__=='__main__':\n    print(attribute(sys.argv[1], 'options'))\n"
  },
  {
    "path": "scripts/bsv.filter",
    "content": "#!/usr/bin/env python3\n# Usage doxyfilter_bsv.psv < infile.bsv > outfile.java\n\nimport fileinput\nimport os\nimport sys\nimport re\nimport argparse\n\nargparser = argparse.ArgumentParser(\"Generate doxygen-ready Java from BSV.\")\nargparser.add_argument('bsvfile', help='BSV files to process', nargs='*')\nargparser.add_argument('-d', '--outdir', default=None, help='Directory for output files')\n\n\n\ndef filter_bsv(bsvin, out):\n    processing_module = 0\n    module_start = \"\"\n    prev_line = \"\"\n    continue_template = 0\n    important_comment = 0\n    in_interface = 0\n    in_module = 0\n    in_instance = 0\n    in_license = 0\n    in_section_break = 0\n    in_enum = 0\n    in_struct = 0\n    documented_construct = 0\n    \n    # define groups to bundle interfaces and modules\n    out.write(\"/** @defgroup BSVInterface Interfaces */ \\n\")\n    out.write(\"/** @defgroup BSVModule Modules */ \\n\")\n\n    for line in bsvin:\n        # Skip the license section\n        if \"Copyright\" in line:\n            # Print the line without modification\n            out.write(line)\n            in_license = 1\n            continue\n        if in_license:\n            # All comments in the license section should be printed without modification\n            if \"//\" in line:\n                out.write(line)\n                continue\n            # if in license and the current line is not a comment then \n            # end the license section\n            in_license = 0\n            important_comment = 0\n            documented_construct = 0\n    \n        # Skip the section break marked by // =============\n        comment_re = re.compile(r\"\"\"[\\s]*       # white space at the start of the line\n                                    //          # start of the comment\n                                    [\\s]*       # one or more white spaces\n                                    ===         # section break marked by a line of =\n                                 \"\"\", re.X)\n        if comment_re.match(line):\n            # if a section break found then print the line without modification\n            out.write(line)\n            # if beginning of section break comment then set in_section_break to 1\n            # if end of section break comment then set in_section_break to 0\n            in_section_break = in_section_break ^ 1\n            continue\n        if in_section_break:\n            # All comments in section break comment should be printed without modification\n            if \"//\" in line:\n                out.write(line)\n                continue\n        \n\n        # Check if it is the beginning of an important comment \n        # //<space><End of Line>\n        comment_re = re.compile(r\"\"\"[\\s]*    # white space before the comment\n                                    //       # start of comment      \n                                    [\\s]*    # immediately followed by 0 or more white space\n                                    \\n       # end of line\n                                \"\"\", re.X)\n        if comment_re.search(line):\n            # if this is the beginning of an important comment then change double slashes to\n            # triple slashes and set important_comment\n            line = re.sub(r'//', r'///', line)\n            important_comment = 1\n            documented_construct = 1   \n            out.write(line)\n            continue\n\n        if important_comment:\n            # If inside an important comment then change double slashes to \n            # triple slashes\n            comment_re = re.compile(r\"\"\"[\\s]*   # white space before the comment\n                                        //      # start of a comment\n                                     \"\"\", re.X)\n            if comment_re.search(line):\n                line = re.sub(r'//', r'///', line)\n                out.write(line)\n                continue\n             \n        important_comment = 0\n        #FIXME\n        # Check to see if it is the second highest priority comment \n        # //<space><text>\n        #comment_re = re.compile(r\"\"\"[\\s]*   # white space before the comment\n        #                            //      # start of comment\n        #                            [\\s]*   # white space before the start of the text\n        #                            (.+)    # comment text\n        #                         \"\"\", re.X)\n        #if comment_re.search(line):\n        #    line = re.sub(r'//', r'///', line)\n        \n        # All comments with or without space/newline in the first line\n        # are important within a module or interface\n        if in_module or in_interface or in_instance:\n            comment_re = re.compile(r\"\"\"[\\s]+   # white space before the comment\n                                        //      # start of comment\n                                        (?!/)   # should not be followed by a 3rd slash\n                                     \"\"\", re.X)\n            if comment_re.search(line):\n               line = re.sub(r'//', r'/// ', line)\n    \n        # Replace #() with <> \n        comment_re = re.compile(\"\"\"#\\(              # start of the template parameter\n                                   ([\\w\\s,<>]+?)    # non greedy search for template parameters\n                                   \\)               # End of the template parameter \n                                \"\"\", re.X)\n        # If the template parameter did not find a closing parantheses in the last line\n        # then process the last line along with this line\n        if continue_template:\n            line = prev_line + line\n            prev_line = \"\"\n        if re.search(r'#\\(', line):\n            prev_line = line\n            continue_template = 1\n            while re.search(r'#\\(([\\w\\s,<>]+?)\\)', line):\n                line = re.sub(r'#\\(([\\w\\s,<>]+?)\\)', r'<\\1>', line)\n                if not re.search(r'#\\(', line):\n                    prev_line = \"\"\n                    continue_template = 0\n        if continue_template:\n            continue\n        \n        # handle interface definitions\n        comment_re = re.compile(\"\"\"interface\\s  # interface keyword followed by white space\n                                   [\\w]+        # interface name\n                                   [\\s]*        # 0 or more white spaces after the name\n                                   (<           # Start of template\n                                   [\\w\\s,<>]+   # Template parameters - may be nested\n                                   >)*          # End of template - may not be present and hence the *\n                                   ;            # end of interface declaration statement\n                                \"\"\", re.X)\n        if comment_re.search(line):\n            line = re.sub(r'\\binterface\\b', r'class', line)\n            if documented_construct:\n                line = \"/** @ingroup BSVInterface */ \" + line\n            line = line.replace(';', ' {');\n            in_interface = 1\n        if re.search(r'endinterface', line):\n            line = line.replace('endinterface', '};', re.DOTALL)\n            in_interface = 0\n            documented_construct = 0\n\n        # handle module definitions\n        comment_re = re.compile(\"\"\"^(\\s)*         # start of string followed by white space\n                                   module(\\s)+    # module keyword followed by white spaces\n                                   (\\[[\\w]+\\])*   # [module type] may or may not be present\n                                   [\\s]*          # white space\n                                   ([\\w]+)        # module name\n                                   (<             # Start of template\n                                   [\\w\\s,<>]+     # Template parameters - may be nested\n                                   >)*            # End of template may not be present and hence the *\n                                   (\\(.*\\))*      # interface name may or may not be present on the same line\n                                \"\"\", re.X)\n        if comment_re.search(line):\n            line = re.sub(r'\\bmodule\\b', r'class', line)\n            line = re.sub(r'\\[[\\w]+\\]', r'', line)\n            line = re.sub(r'\\n$', ' {\\n', line)         # the $ sign denotes the end of line. In case module declaration span multiple lines\n            if documented_construct:\n                line = \"/** @ingroup BSVModule */ \" + line \n            line = line.replace(';', '');\n            # remove interface name from the definition\n            line = re.sub(r'\\(.*\\)', r' ', line)\n            in_module = 1\n\n        # substitute the end module statement with a closing curly brace\n        if re.search(r'endmodule', line):\n            line = line.replace('endmodule', '};', re.DOTALL)\n            in_module = 0\n            documented_construct = 0\n        \n        # handle methods\n        comment_re = re.compile(\"\"\"^(\\s)*       # start of the string followed by white space\n                           method(\\s)+          # method keyword followed by white space\n                           ([\\w<>,]+)(\\s)+       # method type followed by white space\n                           ([\\w]+)              # method name\n                           \"\"\", re.X)\n        if in_module:\n            if comment_re.search(line):\n                line = re.sub(r'\\bmethod\\b', r'', line)\n                line = line.replace(';', '');\n                line = re.sub(r'\\n', ' {\\n', line)\n            line = line.replace('endmethod', '}')\n\n\n        #FIXME        \n        # handle  functions\n        #comment_re = re.compile(\"\"\"^(\\s)*           # start of a string followed by white space\n        #                        function(\\s)+       # function keyword followed by white space\n        #                        ([\\w<>,]+)(\\s)+      # function return type followed by white space\n        #                        ([\\w]+)             # function name\n        #                        \"\"\", re.X)\n  \n        #if comment_re.search(line):\n        #    if documented_construct:\n        #        line = \"/** @ingroup BSVFunctions */ \" + line\n        #    line = re.sub(r'\\bfunction\\b', r'', line)\n        #    line = line.replace(';', '')\n        #    line = re.sub(r'\\n', ' {\\n', line)\n        #line = line.replace('endfunction', '}')\n        \n\n        # handle the special \"deriving\" enum case\n        comment_re = re.compile(\"\"\"^(\\s)*           # start of a string followed by white space\n                                typedef(\\s)+        # typedef keyword followed by white space\n                                enum(\\s)+           # enum keyword followed by white space\n                                \"\"\", re.X)\n        if comment_re.search(line):\n            in_enum = 1\n\n        comment_re = re.compile(\"\"\"(\\s)+            # white space\n                                deriving(\\s)+       # keyword derving followed by white space \n                                \\([\\w,\\s]+\\)          # Parameters inside parantheses\n                                \"\"\", re.X)\n        if in_enum:\n            if comment_re.search(line):\n                line = re.sub(r'deriving(.)*', ';', line)\n                in_enum = 0;\n                documented_construct = 0\n\n        # handle the special \"deriving\" struct case\n        comment_re = re.compile(\"\"\"^(\\s)*           # start of a string followed by white space\n                                typedef(\\s)+        # typedef keyword followed by white space\n                                struct(\\s)+         # struct keyword followed by white space\n                                \"\"\", re.X)\n        if comment_re.search(line):\n            in_struct = 1\n\n        comment_re = re.compile(\"\"\"(\\s)+            # white space\n                                deriving(\\s)+       # keyword derving followed by white space \n                                \\([\\w,\\s]+\\)          # Parameters inside parantheses\n                                \"\"\", re.X)\n        if in_struct:\n            if comment_re.search(line):\n                line = re.sub(r'deriving(.)*', ';', line)\n                in_struct = 0;\n                documented_construct = 0\n\n        import_re = re.compile(\"\"\"(\\s)*            # white space\n                                import(\\s)+         # keyword import followed by white space \n                                .*          # Parameters inside parantheses\n                                \"\"\", re.X)\n        if import_re.search(line):\n            continue\n\n        out.write(line)\n    out.close()\n\nif __name__=='__main__':\n    exename = os.path.abspath(sys.argv[0])\n    connectaldir = os.path.dirname(exename)\n    namespace = argparser.parse_args()\n    if namespace.outdir and not os.path.exists(namespace.outdir):\n        os.makedirs(namespace.outdir)\n    if not namespace.outdir:\n        filter_bsv(open(namespace.bsvfile[0], 'r'), sys.stdout)\n    else:\n        for bsvfile in namespace.bsvfile:\n            if not namespace.outdir:\n                ofile = bsvfile.replace('.bsv', '.java')\n            else:\n                basename = os.path.basename(bsvfile).replace('.bsv', '.java')\n                ofile = os.path.join(namespace.outdir, basename)\n            bsvin = open(bsvfile, 'r')\n            out = open(ofile, 'w')\n            filter_bsv(bsvin, out)\n"
  },
  {
    "path": "scripts/bsvdepend.py",
    "content": "#!/usr/bin/env python3\n# Copyright (c) 2015 Connectal Project\n#\n# Permission is hereby granted, free of charge, to any person obtaining a\n# copy of this software and associated documentation files (the \"Software\"),\n# to deal in the Software without restriction, including without limitation\n# the rights to use, copy, modify, merge, publish, distribute, sublicense,\n# and/or sell copies of the Software, and to permit persons to whom the\n# Software is furnished to do so, subject to the following conditions:\n#\n# The above copyright notice and this permission notice shall be included\n# in all copies or substantial portions of the Software.\n#\n# THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n# OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n# DEALINGS IN THE SOFTWARE.\n#\n\nimport os, sys\nimport glob\nimport argparse\nimport re\nimport bsvpreprocess\nimport bsvdependencies\n\ndefault_bluespecdir=None\nif 'BLUESPECDIR' in os.environ:\n    default_bluespecdir = os.environ['BLUESPECDIR']\n\nargparser = argparse.ArgumentParser(\"Writes a makefile for a dependence build of the BSV files.\")\nargparser.add_argument('bsvfile', help='BSV files to process', nargs='*')\nargparser.add_argument('-D', '--bsvdefine', default=[], help='BSV define', action='append')\nargparser.add_argument('--bsvpath', default=[], help='directories to add to bsc search path', action='append')\nargparser.add_argument('--bluespecdir', default=default_bluespecdir, help='BSC bluespec dir')\nargparser.add_argument('-o', '--output', help='Output Makefile', default='Makefile.bsv')\nargparser.add_argument('--all', help='Generate entries for all BSV files on path.', default=False, action='store_true')\n\nmakefiletemplate='''\n%(name)s_BO  = obj/%(name)s.bo\n%(name)s_DEP = %(dependences)s\n%(name)s_INC = %(includes)s\n%(name)s_BSV = %(bsvfilename)s\n\n$(eval $(call BSV_BO_RULE, $(%(name)s_BO), $(%(name)s_BSV), $(%(name)s_DEP), $(%(name)s_INC)))\n'''\n\nsynthmoduletemplate = '''\n%(name)s_MOD = %(module)s\n%(name)s_V   = verilog/%(module)s.v\n%(name)s_BO  = obj/%(name)s.bo\n%(name)s_BSV = %(bsvfilename)s\n%(name)s_DEP = %(dependences)s\n%(name)s_INC = %(includes)s\n\n$(eval $(call BSV_V_RULE, $(%(name)s_MOD), $(%(name)s_V), $(%(name)s_BSV), $(%(name)s_DEP), $(%(name)s_INC)))\n'''\n\nif __name__=='__main__':\n    options = argparser.parse_args()\n    (bsvdep,bsvpath) = bsvdependencies.bsvDependencies(options.bsvfile,\n                                                       options.all,\n                                                       options.bluespecdir,\n                                                       options.bsvpath,\n                                                       options.bsvdefine)\n\n    makef = open(options.output, 'w')\n    makef.write('# BSV dependences\\n')\n    for bsvdef in options.bsvdefine:\n        makef.write('#  -D%s\\n' % bsvdef)\n    makef.write('OBJMAKEFILE_DEP = %s\\n' % ' '.join(['$(wildcard %s/*.bsv)' % path for path in bsvpath]))\n    makef.write('\\n')\n    for bsvfilename,packages,includes,synthesizedModules in bsvdep:\n        basename = os.path.basename(bsvfilename)\n        (name, ext) = os.path.splitext(basename)\n        makef.write(makefiletemplate % {\n                'name': name,\n                'bsvfilename': bsvfilename,\n                'dependences': ' '.join(['obj/%s.bo' % pkg for pkg in packages]),\n                'includes':    ' '.join(includes)\n                })\n        for mod in synthesizedModules:\n            makef.write(synthmoduletemplate % {\n                    'module': mod,\n                    'name': name,\n                    'bsvfilename': bsvfilename,\n                    'dependences': ' '.join(['obj/%s.bo' % pkg for pkg in packages]),\n                    'includes':    ' '.join(includes)\n                    })\n        pass\n    makef.close()\n"
  },
  {
    "path": "scripts/bsvdependencies.py",
    "content": "#!/usr/bin/env python3\n# Copyright (c) 2015 Connectal Project\n#\n# Permission is hereby granted, free of charge, to any person obtaining a\n# copy of this software and associated documentation files (the \"Software\"),\n# to deal in the Software without restriction, including without limitation\n# the rights to use, copy, modify, merge, publish, distribute, sublicense,\n# and/or sell copies of the Software, and to permit persons to whom the\n# Software is furnished to do so, subject to the following conditions:\n#\n# The above copyright notice and this permission notice shall be included\n# in all copies or substantial portions of the Software.\n#\n# THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n# OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n# DEALINGS IN THE SOFTWARE.\n#\n\nimport os, sys\nimport glob\nimport argparse\nimport re\nimport bsvpreprocess\nimport subprocess\n\ndef getBsvPackages(bluespecdir):\n    \"\"\"BLUESPECDIR is expected to be the path to the bluespec distribution.\n    The function GETBSVPACKAGES returns a list of all\n    the packages in the prelude library of this distribution.\n    \"\"\"\n    pkgs = []\n    for f in glob.glob('%s/Prelude/*.bo' % bluespecdir) + glob.glob('%s/Libraries/*.bo' % bluespecdir) + glob.glob('%s/Libraries/*/*.bo' % bluespecdir) + glob.glob('%s/Libraries/*/*/*.bo' % bluespecdir):\n        pkgs.append(os.path.splitext(os.path.basename(f))[0])\n    return pkgs\n\ndef bsvDependencies(bsvfile, allBsv=False, bluespecdir=None, argbsvpath=[], bsvdefine=[]):\n    \"\"\"Return the list of dependencies\n    [(NAME,BSVFILENAME,PACKAGES,INCLUDES,SYNTHESIZEDMODULES)] of\n    BSVFILE, adding the list BSVPATH to the directories to explore for\n    dependencies.\n\n    The boolean ALLBSV will generate entries for all\n    BSV files on path.\n\n    The string BLUESPECDIR will add the Prelude of\n    Bsv in packages.\n\n    The BSVDEFINE argument is passed to the\n    preprocessor.\n\n    \"\"\"\n    bsvpath = []\n    for p in argbsvpath:\n        ps = p.split(':')\n        bsvpath.extend(ps)\n    bsvpackages = getBsvPackages(bluespecdir)\n    project_packages = {}\n    if allBsv:\n        for d in bsvpath:\n            for bsvfilename in glob.glob('%s/*.bsv' % d):\n                package_name = os.path.basename(bsvfilename)\n                if bsvfilename not in bsvfile and package_name not in project_packages:\n                    bsvfile.append(bsvfilename)\n                    project_packages[package_name] = bsvfilename\n    abspaths = {}\n    for f in bsvfile:\n        abspaths[os.path.basename(f)] = f\n    for d in bsvpath:\n        for f in glob.glob('%s/*' % d):\n            abspaths[os.path.basename(f)] = f\n    generated = []\n    for bsvfilename in bsvfile:\n        vf = open(bsvfilename, 'r')\n        basename = os.path.basename(bsvfilename)\n        (name, ext) = os.path.splitext(basename)\n        source = vf.read()\n        ##preprocessed = bsvpreprocess.preprocess(bsvfilename, source, bsvdefine, bsvpath)\n        bsc_search_path = '+:' + ':'.join(bsvpath)\n        bsc_define_args = []\n        for var in bsvdefine:\n            bsc_define_args.append('-D')\n            bsc_define_args.append(var)\n        cp = subprocess.check_output(['bsc', '-E', '-p', bsc_search_path] + bsc_define_args + [bsvfilename])\n        preprocessed = cp.decode('utf8')\n        packages = []\n        includes = []\n        synthesizedModules = []\n        synthesize = False\n        for line in preprocessed.split('\\n'):\n            m = re.match('//`include \"([^\\\"]+)\"', line)\n            m1 = re.match('//`include(.*)', line)\n            if m:\n                iname = m.group(1)\n                if iname in abspaths:\n                    iname = abspaths[iname]\n                else:\n                    iname = 'obj/%s' % iname\n                includes.append(iname)\n            elif m1:\n                sys.stderr.write('bsvdepend %s: unhandled `include %s\\n' % (bsvfilename, m1.group(1)))\n\n            if re.match('^//', line):\n                continue\n            m = re.match('import\\s+([A-Za-z0-9_]+)\\w*', re.sub(\"`line\\(.*\\)\", \" \", line))\n            if m:\n                pkg = m.group(1)\n                if pkg not in packages and pkg not in bsvpackages:\n                    packages.append(pkg)\n            if synthesize:\n                m = re.match('\\s*module\\s+([A-Za-z0-9_]+)', line)\n                if m:\n                    synthesizedModules.append(m.group(1))\n                else:\n                    sys.stderr.write('bsvdepend: in %s expecting module: %s\\n' % (bsvfilename, line))\n            synth = line.find('(* synthesize *)')\n            attr = line.find('(* ')\n            if synth >= 0:\n                synthesize = True\n            elif attr >= 0:\n                pass # no change to synthesize\n            else:\n                synthesize = False\n            pass\n        generated.append((bsvfilename,packages,includes,synthesizedModules))\n        vf.close()\n    return (generated,bsvpath)\n"
  },
  {
    "path": "scripts/bsvgen.py",
    "content": "##\n## Copyright (C) 2012-2013 Nokia, Inc\n## Copyright (c) 2013-2014 Quanta Research Cambridge, Inc.\n\n## Permission is hereby granted, free of charge, to any person\n## obtaining a copy of this software and associated documentation\n## files (the \"Software\"), to deal in the Software without\n## restriction, including without limitation the rights to use, copy,\n## modify, merge, publish, distribute, sublicense, and/or sell copies\n## of the Software, and to permit persons to whom the Software is\n## furnished to do so, subject to the following conditions:\n\n## The above copyright notice and this permission notice shall be\n## included in all copies or substantial portions of the Software.\n\n## THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n## EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n## MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n## NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n## BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n## ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n## CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n## SOFTWARE.\n\n##\nfrom __future__ import print_function\n\nimport os\nimport math\nimport re\nimport hashlib\n\nimport AST\nimport string\nimport util\n\ntry:\n    xrange\nexcept NameError:\n    xrange = range  # Python 3 compatibility\n\npreambleTemplate='''\nimport FIFO::*;\nimport FIFOF::*;\nimport GetPut::*;\nimport Connectable::*;\nimport Clocks::*;\nimport FloatingPoint::*;\nimport Adapter::*;\nimport Leds::*;\nimport Vector::*;\nimport SpecialFIFOs::*;\nimport ConnectalConfig::*;\nimport ConnectalMemory::*;\nimport Portal::*;\nimport CtrlMux::*;\nimport ConnectalMemTypes::*;\nimport Pipe::*;\nimport HostInterface::*;\nimport LinkerLib::*;\n%(extraImports)s\n\n'''\n\nrequestStructTemplate='''\ntypedef struct {\n%(paramStructDeclarations)s\n} %(MethodName)s_Message deriving (Bits);\n'''\n\nrequestOutputPipeInterfaceTemplate='''\\\n    interface PipeOut#(%(MethodName)s_Message) %(methodName)s_PipeOut;\n'''\n\nexposedProxyInterfaceTemplate='''\n// exposed proxy interface\ntypedef PipePortal#(0, %(channelCount)s, SlaveDataBusWidth) %(Ifc)sPortalOutput;\ninterface %(Ifc)sOutput;\n    interface %(Ifc)sPortalOutput portalIfc;\n    interface %(Package)s%(Ifc)s ifc;\nendinterface\ninterface %(Dut)s;\n    interface StdPortal portalIfc;\n    interface %(Package)s%(Ifc)s ifc;\nendinterface\n\ninterface %(Ifc)sOutputPipeMethods;\n%(indicationMethodDecls)s\nendinterface\n\ninterface %(Ifc)sOutputPipes;\n    interface %(Ifc)sOutputPipeMethods methods;\n    interface %(Ifc)sPortalOutput portalIfc;\nendinterface\n\nfunction Bit#(16) get%(Ifc)sMessageSize(Bit#(16) methodNumber);\n    case (methodNumber)%(messageSizes)s\n    endcase\nendfunction\n\n(* synthesize *)\nmodule mk%(Ifc)sOutputPipes(%(Ifc)sOutputPipes);\n    Vector#(%(channelCount)s, PipeOut#(Bit#(SlaveDataBusWidth))) indicationPipes;\n%(indicationMethodRules)s\n    PortalInterrupt#(SlaveDataBusWidth) intrInst <- mkPortalInterrupt(indicationPipes);\n    interface %(Ifc)sOutputPipeMethods methods;\n%(indicationMethodAssigns)s\n    endinterface\n    interface PipePortal portalIfc;\n        interface PortalSize messageSize;\n            method size = get%(Ifc)sMessageSize;\n        endinterface\n        interface Vector requests = nil;\n        interface Vector indications = indicationPipes;\n        interface PortalInterrupt intr = intrInst;\n    endinterface\nendmodule\n\n(* synthesize *)\nmodule mk%(Ifc)sOutput(%(Ifc)sOutput);\n    let indicationPipes <- mk%(Ifc)sOutputPipes;\n    interface %(Package)s%(Ifc)s ifc;\n%(indicationMethods)s\n    endinterface\n    interface PipePortal portalIfc = indicationPipes.portalIfc;\nendmodule\ninstance PortalMessageSize#(%(Ifc)sOutput);\n   function Bit#(16) portalMessageSize(%(Ifc)sOutput p, Bit#(16) methodNumber);\n      return get%(Ifc)sMessageSize(methodNumber);\n   endfunction\nendinstance\n\n\ninterface %(Ifc)sInverse;\n%(indicationInverseMethodDecls)s\nendinterface\n\ninterface %(Ifc)sInverter;\n    interface %(Package)s%(Ifc)s ifc;\n    interface %(Ifc)sInverse inverseIfc;\nendinterface\n\ninstance Connectable#(%(Ifc)sInverse, %(Ifc)sOutputPipeMethods);\n   module mkConnection#(%(Ifc)sInverse in, %(Ifc)sOutputPipeMethods out)(Empty);\n%(indicationInverseConnect)s\n   endmodule\nendinstance\n\n(* synthesize *)\nmodule mk%(Ifc)sInverter(%(Ifc)sInverter);\n%(inverseIndicationMethodRules)s\n    interface %(Package)s%(Ifc)s ifc;\n%(inverseIndicationMethods)s\n    endinterface\n    interface %(Ifc)sInverse inverseIfc;\n%(inverseIndicationInverseMethods)s\n    endinterface\nendmodule\n\n(* synthesize *)\nmodule mk%(Ifc)sInverterV(%(Ifc)sInverter);\n%(wInverseIndicationMethodRules)s\n    interface %(Package)s%(Ifc)s ifc;\n%(wInverseIndicationMethods)s\n    endinterface\n    interface %(Ifc)sInverse inverseIfc;\n%(wInverseIndicationInverseMethods)s\n    endinterface\nendmodule\n\n// synthesizeable proxy MemPortal\n(* synthesize *)\nmodule mk%(Dut)sSynth#(Bit#(SlaveDataBusWidth) id)(%(Dut)s);\n  let dut <- mk%(Ifc)sOutput();\n  PortalCtrlMemSlave#(SlaveControlAddrWidth,SlaveDataBusWidth) ctrlPort <- mkPortalCtrlMemSlave(id, dut.portalIfc.intr);\n  let memslave  <- mkMemMethodMuxOut(ctrlPort.memSlave,dut.portalIfc.indications);\n  interface MemPortal portalIfc = (interface MemPortal;\n      interface PhysMemSlave slave = memslave;\n      interface ReadOnly interrupt = ctrlPort.interrupt;\n      interface WriteOnly num_portals = ctrlPort.num_portals;\n    endinterface);\n  interface %(Package)s%(Ifc)s ifc = dut.ifc;\nendmodule\n\n// exposed proxy MemPortal\nmodule mk%(Dut)s#(idType id)(%(Dut)s)\n   provisos (Bits#(idType, a__),\n\t     Add#(b__, a__, SlaveDataBusWidth));\n   let rv <- mk%(Dut)sSynth(extend(pack(id)));\n   return rv;\nendmodule\n'''\n\nexposedWrapperInterfaceTemplate='''\n%(requestElements)s\n// exposed wrapper portal interface\ninterface %(Ifc)sInputPipes;\n%(requestOutputPipeInterfaces)s\nendinterface\ntypedef PipePortal#(%(channelCount)s, 0, SlaveDataBusWidth) %(Ifc)sPortalInput;\ninterface %(Ifc)sInput;\n    interface %(Ifc)sPortalInput portalIfc;\n    interface %(Ifc)sInputPipes pipes;\nendinterface\ninterface %(Dut)sPortal;\n    interface %(Ifc)sPortalInput portalIfc;\nendinterface\n// exposed wrapper MemPortal interface\ninterface %(Dut)s;\n    interface StdPortal portalIfc;\nendinterface\n\ninstance Connectable#(%(Ifc)sInputPipes,%(Ifc)s);\n   module mkConnection#(%(Ifc)sInputPipes pipes, %(Ifc)s ifc)(Empty);\n%(mkConnectionMethodRules)s\n   endmodule\nendinstance\n\n// exposed wrapper Portal implementation\n(* synthesize *)\nmodule mk%(Ifc)sInput(%(Ifc)sInput);\n    Vector#(%(channelCount)s, PipeIn#(Bit#(SlaveDataBusWidth))) requestPipeIn;\n%(methodRules)s\n    interface PipePortal portalIfc;\n        interface PortalSize messageSize;\n        method Bit#(16) size(Bit#(16) methodNumber);\n            case (methodNumber)%(messageSizes)s\n            endcase\n        endmethod\n        endinterface\n        interface Vector requests = requestPipeIn;\n        interface Vector indications = nil;\n        interface PortalInterrupt intr;\n           method Bool status();\n              return False;\n           endmethod\n           method Bit#(dataWidth) channel();\n              return -1;\n           endmethod\n        endinterface\n    endinterface\n    interface %(Ifc)sInputPipes pipes;\n%(outputPipes)s\n    endinterface\nendmodule\n\nmodule mk%(Dut)sPortal#(%(Ifc)s ifc)(%(Dut)sPortal);\n    let dut <- mk%(Ifc)sInput;\n    mkConnection(dut.pipes, ifc);\n    interface PipePortal portalIfc = dut.portalIfc;\nendmodule\n\ninterface %(Dut)sMemPortalPipes;\n    interface %(Ifc)sInputPipes pipes;\n    interface MemPortal#(12,32) portalIfc;\nendinterface\n\n(* synthesize *)\nmodule mk%(Dut)sMemPortalPipes#(Bit#(SlaveDataBusWidth) id)(%(Dut)sMemPortalPipes);\n\n  let dut <- mk%(Ifc)sInput;\n  PortalCtrlMemSlave#(SlaveControlAddrWidth,SlaveDataBusWidth) ctrlPort <- mkPortalCtrlMemSlave(id, dut.portalIfc.intr);\n  let memslave  <- mkMemMethodMuxIn(ctrlPort.memSlave,dut.portalIfc.requests);\n  interface %(Ifc)sInputPipes pipes = dut.pipes;\n  interface MemPortal portalIfc = (interface MemPortal;\n      interface PhysMemSlave slave = memslave;\n      interface ReadOnly interrupt = ctrlPort.interrupt;\n      interface WriteOnly num_portals = ctrlPort.num_portals;\n    endinterface);\nendmodule\n\n// exposed wrapper MemPortal implementation\nmodule mk%(Dut)s#(idType id, %(Ifc)s ifc)(%(Dut)s)\n   provisos (Bits#(idType, a__),\n\t     Add#(b__, a__, SlaveDataBusWidth));\n  let dut <- mk%(Dut)sMemPortalPipes(zeroExtend(pack(id)));\n  mkConnection(dut.pipes, ifc);\n  interface MemPortal portalIfc = dut.portalIfc;\nendmodule\n'''\n\nrequestRuleTemplate='''\n    AdapterFromBus#(SlaveDataBusWidth,%(MethodName)s_Message) %(methodName)s_requestAdapter <- mkAdapterFromBus();\n    requestPipeIn[%(channelNumber)s] = %(methodName)s_requestAdapter.in;\n'''\n\nmethodDefTemplate='''\n    method Action %(methodName)s(%(formals)s);'''\n\ninterfaceDefTemplate = '''\ninterface %(Ifc)s;%(methodDef)s\nendinterface\n'''\n\nmessageSizeTemplate='''\n            %(channelNumber)s: return fromInteger(valueOf(SizeOf#(%(MethodName)s_Message)));'''\n\nmkConnectionMethodTemplate='''\n    rule handle_%(methodName)s_request;\n        let request <- toGet(pipes.%(methodName)s_PipeOut).get();\n        ifc.%(methodName)s(%(paramsForCall)s);\n    endrule\n'''\n\nindicationRuleTemplate='''\n    AdapterToBus#(SlaveDataBusWidth,%(MethodName)s_Message) %(methodName)s_responseAdapter <- mkAdapterToBus();\n    indicationPipes[%(channelNumber)s] = %(methodName)s_responseAdapter.out;\n'''\n\nindicationDeclTemplate='''    interface PipeIn#(%(MethodName)s_Message) %(methodName)s;\n'''\n\nindicationAssignTemplate='''    interface %(methodName)s = %(methodName)s_responseAdapter.in;\n'''\n\nindicationMethodTemplate='''\n    method Action %(methodName)s(%(formals)s);\n        indicationPipes.methods.%(methodName)s.enq(%(MethodName)s_Message {%(structElements)s});\n        //$display(\\\"indicationMethod \\'%(methodName)s\\' invoked\\\");\n    endmethod'''\n\nindicationInverseDeclTemplate='''    method ActionValue#(%(MethodName)s_Message) %(methodName)s;\n'''\n\ninverseIndicationRuleTemplate='''    FIFOF#(%(MethodName)s_Message) fifo_%(methodName)s <- mkFIFOF();\n'''\n\ninverseIndicationMethodTemplate='''\n    method Action %(methodName)s(%(formals)s);\n        fifo_%(methodName)s.enq(%(MethodName)s_Message {%(structElements)s});\n    endmethod'''\n\ninverseIndicationInverseMethodTemplate='''\n    method ActionValue#(%(MethodName)s_Message) %(methodName)s;\n        fifo_%(methodName)s.deq;\n        return fifo_%(methodName)s.first;\n    endmethod'''\n\nindicationInverseConnectTemplate='''    mkConnection(in.%(methodName)s, out.%(methodName)s);\n'''\n\nwInverseIndicationRuleTemplate='''    PutInverter#(%(MethodName)s_Message) inv_%(methodName)s <- mkPutInverter();\n'''\n\nwInverseIndicationMethodTemplate='''\n    method Action %(methodName)s(%(formals)s);\n        inv_%(methodName)s.mod.put(%(MethodName)s_Message {%(structElements)s});\n    endmethod'''\n\nwInverseIndicationInverseMethodTemplate='''\n    method ActionValue#(%(MethodName)s_Message) %(methodName)s;\n        let v <- inv_%(methodName)s.inverse.get;\n        return v;\n    endmethod'''\n\ndef toBsvType(titem, oitem):\n    if oitem and oitem['name'].startswith('Tuple'):\n        titem = oitem\n    if titem.get('params') and len(titem['params']):\n        return '%s#(%s)' % (titem['name'], ','.join([str(toBsvType(p, None)) for p in titem['params']]))\n    elif titem['name'] == 'fixed32':\n        return 'Bit#(32)'\n    else:\n        return titem['name']\n\ndef collectElements(mlist, workerfn, name):\n    methods = []\n    mindex = 0\n    for item in mlist:\n        if verbose:\n            print('collectEl', item)\n            for p in item['dparams']:\n                print('collectEl/param', p)\n                break\n        sub = { 'dut': util.decapitalize(name),\n          'Dut': util.capitalize(name),\n          'methodName': item['dname'],\n          'MethodName': util.capitalize(item['dname']),\n          'channelNumber': mindex}\n        paramStructDeclarations = ['    %s %s;' % (toBsvType(p['ptype'], p.get('oldtype')), p['pname']) for p in item['dparams']]\n        sub['paramType'] = ', '.join(['%s' % toBsvType(p['ptype'], p.get('oldtype')) for p in item['dparams']])\n        sub['formals'] = ', '.join(['%s %s' % (toBsvType(p['ptype'], p.get('oldtype')), p['pname']) for p in item['dparams']])\n        structElements = ['%s: %s' % (p['pname'], p['pname']) for p in item['dparams']]\n        if not item['dparams']:\n            paramStructDeclarations = ['    %s %s;' % ('Bit#(32)', 'padding')]\n            structElements = ['padding: 0']\n        sub['paramStructDeclarations'] = '\\n'.join(paramStructDeclarations)\n        sub['structElements'] = ', '.join(structElements)\n        methods.append(workerfn % sub)\n        mindex = mindex + 1\n    return ''.join(methods)\n\ndef fixupSubsts(item, suffix):\n    name = item['cname']+suffix\n    dlist = item['cdecls']\n    mkConnectionMethodRules = []\n    outputPipes = []\n    for m in dlist:\n        if verbose:\n            print('fixupSubsts', m)\n        paramsForCall = ['request.%s' % p['pname'] for p in m['dparams']]\n        msubs = {'methodName': m['dname'],\n                 'paramsForCall': ', '.join(paramsForCall)}\n        mkConnectionMethodRules.append(mkConnectionMethodTemplate % msubs)\n        outputPipes.append('        interface %(methodName)s_PipeOut = %(methodName)s_requestAdapter.out;' % msubs)\n    substs = {\n        'Package': '',\n        'channelCount': len(dlist),\n        'Ifc': item['cname'],\n        'dut': util.decapitalize(name),\n        'Dut': util.capitalize(name),\n    }\n    if not generateInterfaceDefs:\n        substs['Package'] = item['Package'] + '::'\n    substs['requestOutputPipeInterfaces'] = ''.join(\n        [requestOutputPipeInterfaceTemplate % {'methodName': m['dname'],\n                                               'MethodName': util.capitalize(m['dname'])} for m in dlist])\n    substs['outputPipes'] = '\\n'.join(outputPipes)\n    substs['mkConnectionMethodRules'] = ''.join(mkConnectionMethodRules)\n    substs['indicationMethodRules'] = collectElements(dlist, indicationRuleTemplate, name)\n    substs['indicationMethodDecls'] = collectElements(dlist, indicationDeclTemplate, name)\n    substs['indicationMethodAssigns'] = collectElements(dlist, indicationAssignTemplate, name)\n    substs['indicationMethods'] = collectElements(dlist, indicationMethodTemplate, name)\n    substs['indicationInverseMethodDecls'] = collectElements(dlist, indicationInverseDeclTemplate, name)\n    substs['inverseIndicationMethodRules'] = collectElements(dlist, inverseIndicationRuleTemplate, name)\n    substs['inverseIndicationMethods'] = collectElements(dlist, inverseIndicationMethodTemplate, name)\n    substs['inverseIndicationInverseMethods'] = collectElements(dlist, inverseIndicationInverseMethodTemplate, name)\n    substs['indicationInverseConnect'] = collectElements(dlist, indicationInverseConnectTemplate, name)\n    substs['wInverseIndicationMethodRules'] = collectElements(dlist, wInverseIndicationRuleTemplate, name)\n    substs['wInverseIndicationMethods'] = collectElements(dlist, wInverseIndicationMethodTemplate, name)\n    substs['wInverseIndicationInverseMethods'] = collectElements(dlist, wInverseIndicationInverseMethodTemplate, name)\n    substs['requestElements'] = collectElements(dlist, requestStructTemplate, name)\n    substs['methodRules'] = collectElements(dlist, requestRuleTemplate, name)\n    substs['methodDef'] = collectElements(dlist, methodDefTemplate, name)\n    substs['messageSizes'] = collectElements(dlist, messageSizeTemplate, name)\n    return substs\n\ndef indent(f, indentation):\n    for i in xrange(indentation):\n        f.write(' ')\n\ndef bemitStructMember(item, f, indentation):\n    if verbose:\n        print('emitSM', item)\n    indent(f, indentation)\n    f.write('%s %s' % (toBsvType(item['ptype'], item.get('oldtype')), item['pname']))\n    #if hasBitWidth(item['ptype']):\n    #    f.write(' : %d' % typeBitWidth(item['ptype']))\n    f.write(';\\n')\n\ndef bemitStruct(item, name, f, indentation):\n    indent(f, indentation)\n    if (indentation == 0):\n        f.write('typedef ')\n    f.write('struct {\\n')\n    for e in item['elements']:\n        bemitStructMember(e, f, indentation+4)\n    indent(f, indentation)\n    f.write('}')\n    if (indentation == 0):\n        f.write(' %s deriving (Bits);' % name)\n    f.write('\\n')\n\ndef bemitType(item, name, f, indentation):\n    indent(f, indentation)\n    tmp = toBsvType(item, None)\n    if re.match('[0-9]+', tmp):\n        if True or verbose:\n            print('bsvgen/bemitType: INFO ignore numeric typedef for', tmp)\n        return\n    if not tmp or tmp[0] == '`' or tmp == 'Empty' or tmp[-2:] == '_P':\n        if True or verbose:\n            print('bsvgen/bemitType: INFO ignore typedef for', tmp)\n        return\n    if (indentation == 0):\n        f.write('typedef ')\n    f.write(tmp)\n    if (indentation == 0):\n        f.write(' %s deriving (Bits);' % name)\n    f.write('\\n')\n\ndef bemitEnum(item, name, f, indentation):\n    indent(f, indentation)\n    if (indentation == 0):\n        f.write('typedef ')\n    f.write('enum %s { ' % name)\n    indent(f, indentation)\n    f.write(', '.join(['%s_%s' % (name, e) for e in item['elements']]))\n    indent(f, indentation)\n    f.write(' }')\n    if (indentation == 0):\n        f.write(' %s deriving (Bits);' % name)\n    f.write('\\n')\n\ndef emitBDef(item, generated_hpp, indentation):\n    if verbose:\n        print('bsvgen/emitBDef:', item)\n    n = item['tname']\n    td = item['tdtype']\n    t = td.get('type')\n    if t == 'Enum':\n        bemitEnum(td, n, generated_hpp, indentation)\n    elif t == 'Struct':\n        bemitStruct(td, n, generated_hpp, indentation)\n    elif t == 'Type' or t == None:\n        bemitType(td, n, generated_hpp, indentation)\n    else:\n        print('EMITCD', n, t, td)\n\ndef generate_bsv(project_dir, noisyFlag, aGenDef, jsondata):\n    global generateInterfaceDefs,verbose\n    verbose = noisyFlag\n    generateInterfaceDefs = aGenDef\n    generatedPackageNames = []\n    if generateInterfaceDefs:\n        fname = os.path.join(project_dir, 'generatedbsv', 'GeneratedTypes.bsv')\n        if_file = util.createDirAndOpen(fname, 'w')\n        for v in jsondata['globaldecls']:\n            if v['dtype'] == 'TypeDef':\n                if v.get('tparams'):\n                    print('Skipping BSV declaration for parameterized type', v['tname'])\n                    continue\n                emitBDef(v, if_file, 0)\n        if_file.write('\\n')\n    for item in jsondata['interfaces']:\n        if verbose:\n            print('genbsv', item)\n        pname = item['cname']\n        if pname in generatedPackageNames:\n            continue\n        generatedPackageNames.append(pname)\n        fname = os.path.join(project_dir, 'generatedbsv', '%s.bsv' % pname)\n        bsv_file = util.createDirAndOpen(fname, 'w')\n        bsv_file.write('package %s;\\n' % pname)\n        if generateInterfaceDefs:\n            extraImports = ['HostInterface', 'GeneratedTypes']\n        else:\n            extraImports = [item['Package']]\n            extraImports += [i for i in jsondata['globalimports'] if not i in generatedPackageNames]\n        bsv_file.write(preambleTemplate % {'extraImports' : ''.join(['import %s::*;\\n' % pn for pn in extraImports])})\n        if verbose:\n            print('Writing file ', fname)\n        if generateInterfaceDefs:\n            if_file.write(interfaceDefTemplate % fixupSubsts(item, ''))\n        \n        bsv_file.write(exposedWrapperInterfaceTemplate % fixupSubsts(item, 'Wrapper'))\n        bsv_file.write(exposedProxyInterfaceTemplate % fixupSubsts(item, 'Proxy'))\n        bsv_file.write('endpackage: %s\\n' % pname)\n        bsv_file.close()\n    if generateInterfaceDefs:\n        if_file.close()\n\n"
  },
  {
    "path": "scripts/bsvpreprocess.py",
    "content": "#!/usr/bin/env python3\n# Copyright (c) 2014-2015 Quanta Research Cambridge, Inc\n# Copyright (c) 2015 Connectal Project\n#\n# Permission is hereby granted, free of charge, to any person obtaining a\n# copy of this software and associated documentation files (the \"Software\"),\n# to deal in the Software without restriction, including without limitation\n# the rights to use, copy, modify, merge, publish, distribute, sublicense,\n# and/or sell copies of the Software, and to permit persons to whom the\n# Software is furnished to do so, subject to the following conditions:\n#\n# The above copyright notice and this permission notice shall be included\n# in all copies or substantial portions of the Software.\n#\n# THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n# OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n# DEALINGS IN THE SOFTWARE.\n#\n\nfrom __future__ import print_function\n\nimport os, sys, re, string\nimport argparse\n\nargparser = argparse.ArgumentParser(\"Preprocess BSV files.\")\nargparser.add_argument('bsvfile', help='BSV files to parse', nargs='+')\nargparser.add_argument('-D', '--bsvdefine', default=[], help='BSV define', action='append')\nargparser.add_argument('-I', '--include', help='Specify import/include directories', default=[], action='append')\nargparser.add_argument('--bsvpath', default=[], help='directories to add to bsc search path', action='append')\nargparser.add_argument('-v', '--verbose', help='Display verbose information messages', action='store_true')\n\ndef preprocess(sourcefilename, source, defs, bsvpath):\n    # convert defs to a dict\n    # defs could be a list of symbol or symbol=value\n    if type(defs) == list:\n        d = {}\n        for sym in defs:\n            if '=' in sym:\n                (s, val) = sym.split('=')\n                d[s] = val\n            else:\n                d[sym] = ''\n        defs = d\n    stack = [(True,True)]\n    def nexttok(s):\n        k = re.search('[^A-Za-z0-9~_]', s)\n        if k:\n            sym = s[:k.start()]\n            s = s[k.end():]\n            return (sym, s)\n        else:\n            return (s, '')\n    lines = source.splitlines()\n    outlines = []\n    noncomment = ''\n    # true if a previous line started a block comment and didn't finish it\n    multilinecomment = False\n    while lines:\n        line = lines[0]\n        lines = lines[1:]\n        cond  = stack[-1][0]\n        valid = stack[-1][1]\n\n        # FIXME\n        if (line.endswith('\\\\')):\n            noncomment += line[:-1]\n            continue\n\n        remaining = line\n        comment = ''\n        noncomment = ''\n\n        if multilinecomment:\n            commentEnd = remaining.find('*/')\n            if commentEnd >= 0:\n                comment += remaining[0:commentEnd+2]\n                remaining = remaining[commentEnd+2:]\n                multilinecomment = False\n            else:\n                comment += remaining\n                remaining = ''\n\n        while len(remaining):\n            commentStart = remaining.find('/')\n            if commentStart >= 0:\n                noncomment += remaining[0:commentStart]\n                restofline = remaining[commentStart:]\n                if restofline.startswith('/*'):\n                    commentEnd = restofline.find('*/')\n                    if commentEnd >= 0:\n                        comment += restofline[0:commentEnd+2]\n                        remaining = restofline[commentEnd+2:]\n                    else:\n                        comment += restofline\n                        remaining = ''\n                        multilinecomment = True\n                elif restofline.startswith('//'):\n                    comment += remaining\n                    remaining = ''\n                else:\n                    noncomment += restofline[0]\n                    remaining = remaining[1:]\n            else:\n                noncomment += remaining\n                remaining = ''\n        i = noncomment.find('`')\n        if i < 0:\n            if valid:\n                outlines.append(line)\n            else:\n                outlines.append('//SKIPPED %s' % line)\n            continue\n\n        s = noncomment[i+1:]\n        (tok, s) = nexttok(s)\n        if tok == 'ifdef':\n            (sym, s) = nexttok(s)\n            new_cond = sym in defs\n            new_valid = new_cond and valid\n            #sys.stderr.write('ifdef %s new_cond=%d new_valid=%d cond=%d valid=%d\\n' % (sym, new_cond, new_valid, cond, valid))\n            stack.append((new_cond,new_valid))\n        elif tok == 'ifndef':\n            (sym, s) = nexttok(s)\n            new_cond = not sym in defs\n            new_valid = valid and new_cond\n            #sys.stderr.write('ifndef %s new_cond=%d new_valid=%d cond=%d valid=%d\\n' % (sym, new_cond, new_valid, cond, valid))\n            stack.append((new_cond,new_valid))\n        elif tok == 'else':\n            stack.pop()\n            try:\n                valid = stack[-1][1]\n            except:\n                sys.stderr.write('Failed to preprocess %s\\n' % sourcefilename)\n                sys.exit(1)\n            new_cond = not cond\n            new_valid = new_cond and valid\n            #sys.stderr.write('else %s new_cond=%d new_valid=%d cond=%d valid=%d\\n' % (sym, new_cond, new_valid, cond, valid))\n            stack.append((new_cond,new_valid))\n        elif tok == 'elsif':\n            stack.pop()\n            valid = stack[-1][1]\n            (sym, s) = nexttok(s)\n            new_cond = sym in defs\n            new_valid = new_cond and valid\n            stack.append((new_cond,new_valid))\n        elif tok == 'endif':\n            stack.pop()\n            try:\n                valid = stack[-1][1]\n            except:\n                sys.stderr.write('Failed to preprocess %s\\n' % sourcefilename)\n                sys.exit(1)\n        elif tok == 'define':\n            (sym, s) = nexttok(s)\n            if s:\n                defs[sym] = s\n            else:\n                defs[sym] = ''\n        elif tok == 'include':\n            m = re.search('\"?([-_A-Za-z0-9.]+)\"?', s)\n            if not m:\n                sys.stderr.write('syntax.preprocess %s: could not find file in line {%s}\\n' % (sourcefilename, s))\n                break\n            filename = m.group(1)\n            inc = ''\n            for d in bsvpath:\n                fn = os.path.join(d, filename)\n                if os.path.exists(fn):\n                    inc = open(fn).read()\n                    break\n            if not inc:\n                sys.stderr.write('syntax.preprocess %s: did not find included file %s in path\\n' % (sourcefilename, filename))\n            outlines.append('//`include \"%s\"' % filename)\n            lines = inc.splitlines() + lines\n            continue\n        elif tok:\n            while '`' in noncomment:\n                ## must be an undefined variable\n                i = noncomment.find('`')\n                (tok, s) = nexttok(noncomment[i+1:])\n                #sys.stderr.write('syntax.preprocess %s: preprocessor variable `%s\\n' % (sourcefilename, tok))\n                if tok in defs:\n                    val = defs[tok]\n                else:\n                    val = ''\n                #sys.stderr.write('sym=%s val=%s\\n' % (tok, val))\n                noncomment = noncomment.replace('`%s' % tok, val)\n            prefix='//SKIPPED ' if not valid else ''\n            outlines.append('//PREPROCESSED: %s' % line)\n            outlines.append(prefix + noncomment + comment)\n            continue\n        else:\n            sys.stderr.write('syntax.preprocess %s: unhandled preprocessor token %s\\n' % (sourcefilename, tok))\n            sys.stderr.write('line: %s\\n' % line)\n            assert(tok in ['ifdef', 'ifndef', 'else', 'endif', 'define', ''])\n        outlines.append('//PREPROCESSED: %s' % line)\n\n    return '%s\\n' % '\\n'.join(outlines)\n\nif __name__=='__main__':\n    options = argparser.parse_args()\n    for bsvfile in options.bsvfile:\n        preprocessed = preprocess(bsvfile, open(bsvfile).read(), options.bsvdefine, options.include + options.bsvpath)\n        print(preprocessed)\n\n"
  },
  {
    "path": "scripts/cadb",
    "content": "#!/usr/bin/env python3\n# Copyright (c) 2015 Quanta Research Cambridge, Inc.\n\n# Permission is hereby granted, free of charge, to any person\n# obtaining a copy of this software and associated documentation\n# files (the \"Software\"), to deal in the Software without\n# restriction, including without limitation the rights to use, copy,\n# modify, merge, publish, distribute, sublicense, and/or sell copies\n# of the Software, and to permit persons to whom the Software is\n# furnished to do so, subject to the following conditions:\n\n# The above copyright notice and this permission notice shall be\n# included in all copies or substantial portions of the Software.\n\n# THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n# EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n# MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n# BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n# ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n# CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n# SOFTWARE.\n\nfrom __future__ import print_function\n\nimport os, sys, time\nfrom adb import adb_commands\nfrom adb import common\n\ntimebound = 5\n#scriptdir=os.path.dirname(sys.argv[0])\n#sys.path.append(scriptdir)\ncommand_list = ['shell', 'push', 'pull', 'root', 'reboot']\n\nif __name__ == '__main__':\n    if len(sys.argv) < 2:\n        print('cadb <ipaddr> <command> <args>')\n        sys.exit(-1)\n    ipaddr = ''\n    args = sys.argv[1:]\n    if args[0] not in command_list:\n        ipaddr = args[0]\n        args = args[1:]\n    if 'RUNPARAM' in os.environ:\n        ipaddr=os.environ['RUNPARAM']\n    if ipaddr == '':\n         print('cadb: missing address')\n         sys.exit(-1)\n    print('connecting to %s' % ipaddr)\n    starttime = time.clock()\n    count = 0\n    while True:\n        try:\n            connection = adb_commands.AdbCommands.ConnectDevice(serial=ipaddr)\n            print('connect ok', count, time.clock() - starttime)\n            break\n        except:\n            pass\n        if time.clock() - starttime > timebound:\n            print('cadb: connection attempt timed out')\n            sys.exit(-1)\n        count += 1\n    try:\n        if args[0] == 'shell':\n            for line in connection.StreamingShell(' '.join(args[1:])):\n                sys.stdout.write(line)\n        elif args[0] == 'push':\n            for filename in args[1:-1]:\n                connection.Push(filename, args[-1])\n        elif args[0] == 'pull':\n            connection.Pull(args[1], args[2])\n        elif args[0] == 'root':\n            try:\n                connection.Root()\n            except:\n                pass    # connection always fails as adbd reboots...\n        elif args[0] == 'reboot':\n            connection.Reboot()\n        connection.Close()\n    except:\n        print('cadb: operation failed', args[0])\n        sys.exit(-1)\n    sys.exit(0)\n"
  },
  {
    "path": "scripts/check-timing.py",
    "content": "#!/usr/bin/env python3\n\nfrom __future__ import print_function\n\nimport sys, re\n\nfailed = 0\nfor timingreport in sys.argv[1:]:\n    print_lines = 0\n    for line in open(timingreport):\n        re_no_clock = re.compile('\\s*There are (\\d+) register/latch pins with no clock(.*)')\n        re_constant_clock = re.compile('\\s*There are (\\d+) .*constant_clock(.*)')\n        re_violated = re.compile('.*VIOLATED.*-([.0-9]+)')\n\n        m = re_no_clock.match(line)\n        if m and int(m.group(1)):\n            print('*** no clock pins ***')\n            print(line)\n            failed = 1\n        m = re_constant_clock.match(line)\n        if m and int(m.group(1)):\n            print('*** constant clock pins ***')\n            print(line)\n            failed = 1\n        m = re_violated.match(line)\n        if m and float(m.group(1)) >= 0.1:\n            print('*** timing violation ***')\n            print(line[0:-1])\n            failed = 1\n            print_lines = 4\n            continue\n        if print_lines:\n            print(line[0:-1])\n            print_lines -= 1\n            if not print_lines:\n                print()\nif failed:\n    sys.exit(-11)\n\n\n"
  },
  {
    "path": "scripts/connectal-make",
    "content": "#!/bin/sh\n\nmake CONNECTALDIR=/usr/share/connectal $*\n\n"
  },
  {
    "path": "scripts/connectal-synth-avalonddr3.tcl",
    "content": "# Copyright (c) 2015 Connectal Project\n# Permission is hereby granted, free of charge, to any person obtaining a\n# copy of this software and associated documentation files (the \"Software\"),\n# to deal in the Software without restriction, including without limitation\n# the rights to use, copy, modify, merge, publish, distribute, sublicense,\n# and/or sell copies of the Software, and to permit persons to whom the\n# Software is furnished to do so, subject to the following conditions:\n#\n# The above copyright notice and this permission notice shall be included\n# in all copies or substantial portions of the Software.\n#\n# THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n# OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n# DEALINGS IN THE SOFTWARE.\n\nsource \"board.tcl\"\nsource \"$connectaldir/scripts/connectal-synth-ip.tcl\"\n\nproc create_altera_de5_ddr3 {} {\n    set core_name {altera_mem_if_ddr3_emif}\n    set core_version {14.0}\n    set ip_name {altera_mem_if_ddr3_emif_wrapper}\n\n\tset params [ dict create ]\n\n    dict set params MEM_VENDOR                          \"JEDEC\"\n    dict set params MEM_FORMAT                          \"UNBUFFERED\"\n    dict set params RDIMM_CONFIG                        0\n    dict set params LRDIMM_EXTENDED_CONFIG              \"0x000000000000000000\"\n    dict set params DISCRETE_FLY_BY                     \"true\"\n    dict set params DEVICE_DEPTH                        1\n    dict set params MEM_MIRROR_ADDRESSING               0\n    dict set params MEM_CLK_FREQ_MAX                    \"800.0\"\n    dict set params MEM_ROW_ADDR_WIDTH                  15\n    dict set params MEM_COL_ADDR_WIDTH                  10\n    dict set params MEM_DQ_WIDTH                        64\n    dict set params MEM_DQ_PER_DQS                      8\n    dict set params MEM_BANKADDR_WIDTH                  3\n    dict set params MEM_IF_DM_PINS_EN                   \"true\"\n    dict set params MEM_IF_DQSN_EN                      \"true\"\n    dict set params MEM_NUMBER_OF_DIMMS                 1\n    dict set params MEM_NUMBER_OF_RANKS_PER_DIMM        1\n    dict set params MEM_NUMBER_OF_RANKS_PER_DEVICE      1\n    dict set params MEM_RANK_MULTIPLICATION_FACTOR      1\n    dict set params MEM_CK_WIDTH                        1\n    dict set params MEM_CS_WIDTH                        1\n    dict set params MEM_CLK_EN_WIDTH                    1\n    dict set params ALTMEMPHY_COMPATIBLE_MODE           \"false\"\n    dict set params NEXTGEN                             \"true\"\n    dict set params MEM_IF_BOARD_BASE_DELAY             10\n    dict set params MEM_IF_SIM_VALID_WINDOW             0\n    dict set params MEM_GUARANTEED_WRITE_INIT           \"false\"\n    dict set params MEM_VERBOSE                         \"true\"\n    dict set params PINGPONGPHY_EN                      \"false\"\n    dict set params REFRESH_BURST_VALIDATION            \"false\"\n    dict set params MEM_BL                              \"OTF\"\n    dict set params MEM_BT                              \"Sequential\"\n    dict set params MEM_ASR                             \"Manual\"\n    dict set params MEM_SRT                             \"Normal\"\n    dict set params MEM_PD                              \"DLL off\"\n    dict set params MEM_DRV_STR                         \"RZQ/7\"\n    dict set params MEM_DLL_EN                          \"true\"\n    dict set params MEM_RTT_NOM                         \"RZQ/6\"\n    dict set params MEM_RTT_WR                          \"RZQ/4\"\n    dict set params MEM_WTCL                            8\n    dict set params MEM_ATCL                            \"Disabled\"\n    dict set params MEM_TCL                             11\n    dict set params MEM_AUTO_LEVELING_MODE              \"true\"\n    dict set params MEM_USER_LEVELING_MODE              \"Leveling\"\n    dict set params MEM_INIT_EN                         \"false\"\n    dict set params DAT_DATA_WIDTH                      32\n    dict set params TIMING_TIS                          170\n    dict set params TIMING_TIH                          120\n    dict set params TIMING_TDS                          10\n    dict set params TIMING_TDH                          45\n    dict set params TIMING_TDQSQ                        100\n    dict set params TIMING_TQH                          \"0.38\"\n    dict set params TIMING_TDQSCK                       225\n    dict set params TIMING_TDQSCKDS                     450\n    dict set params TIMING_TDQSCKDM                     900\n    dict set params TIMING_TDQSCKDL                     1200\n    dict set params TIMING_TDQSS                        \"0.25\"\n    dict set params TIMING_TQSH                         \"0.4\"\n    dict set params TIMING_TDSH                         \"0.18\"\n    dict set params TIMING_TDSS                         \"0.18\"\n    dict set params MEM_TINIT_US                        500\n    dict set params MEM_TMRD_CK                         4\n    dict set params MEM_TRAS_NS                         \"35.0\"\n    dict set params MEM_TRCD_NS                         \"13.75\"\n    dict set params MEM_TRP_NS                          \"13.75\"\n    dict set params MEM_TREFI_US                        \"7.8\"\n    dict set params MEM_TRFC_NS                         \"160.0\"\n    dict set params CFG_TCCD_NS                         \"2.5\"\n    dict set params MEM_TWR_NS                          \"15.0\"\n    dict set params MEM_TWTR                            \"6\"\n    dict set params MEM_TFAW_NS                         \"30.0\"\n    dict set params MEM_TRRD_NS                         \"6.0\"\n    dict set params MEM_TRTP_NS                         \"7.5\"\n    dict set params RATE                                \"Quarter\"\n    dict set params MEM_CLK_FREQ                        \"800.0\"\n    dict set params USE_MEM_CLK_FREQ                    \"false\"\n    dict set params SYS_INFO_DEVICE_FAMILY              \"Stratix V\"\n    dict set params SPEED_GRADE                         2\n    dict set params PACKAGE_DESKEW                      \"true\"\n    dict set params AC_PACKAGE_DESKEW                   \"true\"\n    dict set params TIMING_BOARD_MAX_CK_DELAY           \"1.33\"\n    dict set params TIMING_BOARD_MAX_DQS_DELAY          \"0.61\"\n    dict set params TIMING_BOARD_SKEW_CKDQS_DIMM_MIN    \"0.0\"\n    dict set params TIMING_BOARD_SKEW_CKDQS_DIMM_MAX    \"0.0\"\n    dict set params TIMING_BOARD_SKEW_BETWEEN_DIMMS     \"0.05\"\n    dict set params TIMING_BOARD_SKEW_WITHIN_DQS        \"0.0070\"\n    dict set params TIMING_BOARD_SKEW_BETWEEN_DQS       \"0.09\"\n    dict set params TIMING_BOARD_DQ_TO_DQS_SKEW         \"0.0020\"\n    dict set params TIMING_BOARD_AC_SKEW                \"0.05\"\n    dict set params TIMING_BOARD_AC_TO_CK_SKEW          \"0.012\"\n    dict set params REF_CLK_FREQ                        \"50.0\"\n    dict set params REF_CLK_FREQ_PARAM_VALID            \"false\"\n    dict set params REF_CLK_FREQ_MIN_PARAM              \"0.0\"\n    dict set params REF_CLK_FREQ_MAX_PARAM              \"0.0\"\n    dict set params PHY_ONLY                            \"false\"\n\n#    dict set params PLL_SHARING_MODE                    \"Master\"\n#    dict set params NUM_PLL_SHARING_INTERFACES          \"1\"\n#    dict set params DLL_SHARING_MODE                    \"Master\"\n#    dict set params NUM_DLL_SHARING_INTERFACES          \"1\"\n#    dict set params OCT_SHARING_MODE                    \"Master\"\n#    dict set params NUM_OCT_SHARING_INTERFACES          \"1\"\n\n    set component_parameters {}\n\tforeach item [dict keys $params] {\n\t\tset val [dict get $params $item]\n\t\tlappend component_parameters --component-parameter=$item=$val\n\t}\n\n    connectal_altera_synth_ip $core_name $core_version $ip_name $component_parameters\n}\n\ncreate_altera_de5_ddr3\n"
  },
  {
    "path": "scripts/connectal-synth-axichecker.tcl",
    "content": "source \"board.tcl\"\nsource \"$connectaldir/scripts/connectal-synth-ip.tcl\"\n\nputs $boardname\nset prj_boardname $boardname\nif [string match \"*g2\" $boardname] {set prj_boardname [string trimright $boardname \"g2\"]}\n\nconnectal_synth_ip axi_protocol_checker 2.0 axi_protocol_checker_0 [list \\\n    CONFIG.ADDR_WIDTH 64 \\\n    CONFIG.DATA_WIDTH 512 \\\n    CONFIG.HAS_WSTRB 1 \\\n    CONFIG.ID_WIDTH 6 \\\n    CONFIG.ARUSER_WIDTH 0 \\\n    CONFIG.AWUSER_WIDTH 0 \\\n    CONFIG.BUSER_WIDTH 0 \\\n    CONFIG.RUSER_WIDTH 0 \\\n    CONFIG.WUSER_WIDTH 0 \\\n    CONFIG.MAX_AR_WAITS 500 \\\n    CONFIG.MAX_AW_WAITS 500 \\\n    CONFIG.MAX_B_WAITS 500 \\\n    CONFIG.MAX_R_WAITS 500 \\\n    CONFIG.MAX_W_WAITS 500 \\\n    ]\n\n# create_project -name local_synthesized_ip -in_memory\n# set_property PART {xcvu9p-flgb2104-2-i} [current_project]\n# create_ip -name axi_protocol_checker -version 2.0 -vendor xilinx.com -library ip -module_name axi_protocol_checker_0 -dir /home/ubuntu/connectal/out/awsf1/axi_protocol_checker_0\n# report_property -file /home/ubuntu/connectal/out/awsf1/axi_protocol_checker_0.properties.log [get_ips axi_protocol_checker_0]\n"
  },
  {
    "path": "scripts/connectal-synth-axiddr3.tcl",
    "content": "source \"board.tcl\"\nsource \"$connectaldir/scripts/connectal-synth-ip.tcl\"\n\nset prj_boardname $boardname\nif [string match \"*g2\" $boardname] {set prj_boardname [string trimright $boardname \"g2\"]}\n\nconnectal_synth_ip mig_7series 4.0 axiddr3 [list CONFIG.XML_INPUT_FILE \"$connectaldir/constraints/xilinx/$prj_boardname-axiddr3.prj\" CONFIG.RESET_BOARD_INTERFACE {Custom} CONFIG.MIG_DONT_TOUCH_PARAM {Custom} CONFIG.BOARD_MIG_PARAM {Custom}]\n"
  },
  {
    "path": "scripts/connectal-synth-axidma.tcl",
    "content": "source \"board.tcl\"\nsource \"$connectaldir/scripts/connectal-synth-ip.tcl\"\n\nset prj_boardname $boardname\nif [string match \"*g2\" $boardname] {set prj_boardname [string trimright $boardname \"g2\"]}\n\nconnectal_synth_ip axi_dma 7.1 axi_dma_0 [list CONFIG.c_sg_include_stscntrl_strm {1} CONFIG.c_m_axi_mm2s_data_width {32} CONFIG.c_m_axi_s2mm_data_width {32} CONFIG.c_mm2s_burst_size {8} CONFIG.c_s2mm_burst_size {8}]\n\n"
  },
  {
    "path": "scripts/connectal-synth-axieth.tcl",
    "content": "source \"board.tcl\"\nsource \"$connectaldir/scripts/connectal-synth-ip.tcl\"\n\nset prj_boardname $boardname\nif [string match \"*g2\" $boardname] {set prj_boardname [string trimright $boardname \"g2\"]}\n\nconnectal_synth_ip axi_ethernet 7.0 axi_ethernet_0 [list CONFIG.ETHERNET_BOARD_INTERFACE {sfp_sfp1} CONFIG.DIFFCLK_BOARD_INTERFACE {sfp_mgt_clk} CONFIG.axiliteclkrate {250.0} CONFIG.axisclkrate {250.0} CONFIG.PHY_TYPE {1000BaseX}]\n\n"
  },
  {
    "path": "scripts/connectal-synth-axiintc.tcl",
    "content": "source \"board.tcl\"\nsource \"$connectaldir/scripts/connectal-synth-ip.tcl\"\n\nputs $boardname\nset prj_boardname $boardname\nif [string match \"*g2\" $boardname] {set prj_boardname [string trimright $boardname \"g2\"]}\n\nconnectal_synth_ip axi_intc 4.1 axi_intc_0 [list CONFIG.C_NUM_INTR_INPUTS {16} CONFIG.C_S_AXI_ACLK_FREQ_MHZ {250.0} CONFIG.C_NUM_SW_INTR {0}]\n"
  },
  {
    "path": "scripts/connectal-synth-eth.tcl",
    "content": "source \"board.tcl\"\nsource \"$connectaldir/scripts/connectal-synth-ip.tcl\"\n\n# PMA-Direct Transceiver, No PCS\nproc create_altera_10gbe_pma {channels} {\n    set core_name {altera_xcvr_native_sv}\n    set core_version {14.0}\n    set ip_name {altera_xcvr_native_sv_wrapper}\n\n\tset params [ dict create ]\n\n    dict set params tx_enable                           1\n    dict set params rx_enable                           1\n    dict set params enable_std                          0\n    dict set params enable_teng                         0\n    dict set params data_path_select                    \"pma_direct\"\n    dict set params channels                            4\n    dict set params bonded_mode                         \"non_bonded\"\n    dict set params enable_simple_interface             1\n    dict set params set_data_rate                       \"10312.5\"\n    dict set params pma_direct_width                    40\n    dict set params tx_pma_clk_div                      1\n    dict set params pll_reconfig_enable                 0\n    dict set params pll_external_enable                 0\n    dict set params plls                                1\n    dict set params pll_select                          0\n    dict set params pll_refclk_cnt                      1\n    dict set params gui_pll_reconfig_pll0_pll_type      \"CMU\"\n    dict set params gui_pll_reconfig_pll1_pll_type      \"CMU\"\n    dict set params gui_pll_reconfig_pll2_pll_type      \"CMU\"\n    dict set params gui_pll_reconfig_pll3_pll_type      \"CMU\"\n    dict set params gui_pll_reconfig_pll0_data_rate     \"1250\"\n    dict set params gui_pll_reconfig_pll1_data_rate     \"1250\"\n    dict set params gui_pll_reconfig_pll2_data_rate     \"1250\"\n    dict set params gui_pll_reconfig_pll3_data_rate     \"1250\"\n    dict set params gui_pll_reconfig_pll0_refclk_freq   \"644.53125 MHz\"\n    dict set params gui_pll_reconfig_pll1_refclk_freq   \"125.0\"\n    dict set params gui_pll_reconfig_pll2_refclk_freq   \"125.0\"\n    dict set params gui_pll_reconfig_pll3_refclk_freq   \"125.0\"\n    dict set params gui_pll_reconfig_pll0_refclk_sel    0\n    dict set params gui_pll_reconfig_pll1_refclk_sel    0\n    dict set params gui_pll_reconfig_pll2_refclk_sel    0\n    dict set params gui_pll_reconfig_pll3_refclk_sel    0\n    dict set params gui_pll_reconfig_pll0_clk_network   \"x1\"\n    dict set params gui_pll_reconfig_pll1_clk_network   \"x1\"\n    dict set params gui_pll_reconfig_pll2_clk_network   \"x1\"\n    dict set params gui_pll_reconfig_pll3_clk_network   \"x1\"\n    dict set params cdr_reconfig_enable                 0\n    dict set params cdr_refclk_cnt                      1\n    dict set params cdr_refclk_select                   0\n    dict set params set_cdr_refclk_freq                 \"644.53125 MHz\"\n    dict set params rx_ppm_detect_threshold             100\n    dict set params enable_port_tx_pma_qpipullup        0\n    dict set params enable_port_tx_pma_qpipulldn        0\n    dict set params enable_port_tx_pma_txdetectrx       0\n    dict set params enable_port_tx_pma_rxfound          0\n    dict set params enable_port_tx_pma_pclk             0\n    dict set params enable_port_rx_pma_qpipulldn        0\n    dict set params enable_port_rx_pma_clkout           1\n    dict set params enable_port_rx_pma_pclk             0\n    dict set params enable_port_rx_is_lockedtodata      1\n    dict set params enable_port_rx_is_lockedtoref       1\n    dict set params enable_ports_rx_manual_cdr_mode     0\n    dict set params rx_clkslip_enable                   0\n    dict set params enable_port_rx_signaldetect         0\n    dict set params enable_port_rx_seriallpbken         1\n    dict set params std_protocol_hint                   \"basic\"\n    dict set params std_pcs_pma_width                   10\n    dict set params std_low_latency_bypass_enable       0\n    dict set params std_tx_pcfifo_mode                  \"low_latency\"\n    dict set params std_rx_pcfifo_mode                  \"low_latency\"\n    dict set params enable_port_tx_std_pcfifo_full      0\n    dict set params enable_port_tx_std_pcfifo_empty     0\n    dict set params enable_port_rx_std_pcfifo_full      0\n    dict set params enable_port_rx_std_pcfifo_empty     0\n    dict set params std_rx_byte_order_enable            0\n    dict set params std_rx_byte_order_mode              \"manual\"\n    dict set params std_rx_byte_order_symbol_count      1\n    dict set params std_rx_byte_order_pattern           0\n    dict set params std_rx_byte_order_pad               0\n    dict set params enable_port_rx_std_byteorder_ena    0\n    dict set params enable_port_rx_std_byteorder_flag   0\n    dict set params std_tx_byte_ser_enable              0\n    dict set params std_rx_byte_deser_enable            0\n    dict set params std_tx_8b10b_enable                 0\n    dict set params std_tx_8b10b_disp_ctrl_enable       0\n    dict set params std_rx_8b10b_enable                 0\n    dict set params std_rx_rmfifo_enable                0\n    dict set params std_rx_rmfifo_pattern_p             00000\n    dict set params std_rx_rmfifo_pattern_n             00000\n    dict set params enable_port_rx_std_rmfifo_full      0\n    dict set params enable_port_rx_std_rmfifo_empty     0\n    dict set params std_tx_bitslip_enable               0\n    dict set params enable_port_tx_std_bitslipboundarysel           0\n    dict set params std_rx_word_aligner_mode            \"bit_slip\"\n    dict set params std_rx_word_aligner_pattern_len     7\n    dict set params std_rx_word_aligner_pattern         0000000000\n    dict set params std_rx_word_aligner_rknumber        3\n    dict set params std_rx_word_aligner_renumber        3\n    dict set params std_rx_word_aligner_rgnumber        3\n    dict set params std_rx_run_length_val               0\n    dict set params enable_port_rx_std_wa_patternalign  0\n    dict set params enable_port_rx_std_wa_a1a2size           0\n    dict set params enable_port_rx_std_bitslipboundarysel    0\n    dict set params enable_port_rx_std_bitslip          0\n    dict set params enable_port_rx_std_runlength_err    0\n    dict set params std_tx_bitrev_enable                0\n    dict set params std_rx_bitrev_enable                0\n    dict set params std_tx_byterev_enable               0\n    dict set params std_rx_byterev_enable               0\n    dict set params std_tx_polinv_enable                0\n    dict set params std_rx_polinv_enable                0\n    dict set params enable_port_rx_std_bitrev_ena       0\n    dict set params enable_port_rx_std_byterev_ena      0\n    dict set params enable_port_tx_std_polinv           0\n    dict set params enable_port_rx_std_polinv           0\n    dict set params enable_port_tx_std_elecidle         0\n    dict set params enable_port_rx_std_signaldetect     0\n    dict set params enable_port_rx_std_prbs_status      0\n    dict set params teng_protocol_hint                  \"basic\"\n    dict set params teng_pcs_pma_width                  40\n    dict set params teng_pld_pcs_width                  40\n    dict set params teng_txfifo_mode                    \"phase_comp\"\n    dict set params teng_txfifo_full                    31\n    dict set params teng_txfifo_empty                   0\n    dict set params teng_txfifo_pfull                   23\n    dict set params teng_txfifo_pempty                  2\n    dict set params enable_port_tx_10g_fifo_full        0\n    dict set params enable_port_tx_10g_fifo_pfull       0\n    dict set params enable_port_tx_10g_fifo_empty       0\n    dict set params enable_port_tx_10g_fifo_pempty      0\n    dict set params enable_port_tx_10g_fifo_del         0\n    dict set params enable_port_tx_10g_fifo_insert      0\n    dict set params teng_rxfifo_mode                    \"phase_comp\"\n    dict set params teng_rxfifo_full                    31\n    dict set params teng_rxfifo_empty                   0\n    dict set params teng_rxfifo_pfull                   23\n    dict set params teng_rxfifo_pempty                  7\n    dict set params teng_rxfifo_align_del               0\n    dict set params teng_rxfifo_control_del             0\n    dict set params enable_port_rx_10g_data_valid       0\n    dict set params enable_port_rx_10g_fifo_full        0\n    dict set params enable_port_rx_10g_fifo_pfull       0\n    dict set params enable_port_rx_10g_fifo_empty       0\n    dict set params enable_port_rx_10g_fifo_pempty      0\n    dict set params enable_port_rx_10g_fifo_del         0\n    dict set params enable_port_rx_10g_fifo_insert      0\n    dict set params enable_port_rx_10g_fifo_rd_en       0\n    dict set params enable_port_rx_10g_fifo_align_val   0\n    dict set params enable_port_rx_10g_fifo_align_clr   0\n    dict set params enable_port_rx_10g_fifo_align_en    0\n    dict set params enable_port_rx_10g_clk33out         0\n    dict set params teng_tx_frmgen_user_length          2048\n    dict set params teng_tx_frmgen_burst_enable         0\n    dict set params enable_port_tx_10g_frame            0\n    dict set params enable_port_tx_10g_frame_diag_status       0\n    dict set params enable_port_tx_10g_frame_burst_en          0\n    dict set params teng_rx_frmsync_user_length         2048\n    dict set params enable_port_rx_10g_frame            0\n    dict set params enable_port_rx_10g_frame_lock       0\n    dict set params enable_port_rx_10g_frame_mfrm_err   0\n    dict set params enable_port_rx_10g_frame_sync_err   0\n    dict set params enable_port_rx_10g_frame_pyld_ins   0\n    dict set params enable_port_rx_10g_frame_skip_ins   0\n    dict set params enable_port_rx_10g_frame_skip_err   0\n    dict set params enable_port_rx_10g_frame_diag_err   0\n    dict set params enable_port_rx_10g_frame_diag_status   0\n    dict set params teng_tx_sh_err                         0\n    dict set params enable_port_rx_10g_crc32_err           0\n    dict set params enable_port_rx_10g_highber             0\n    dict set params enable_port_rx_10g_highber_clr_cnt     0\n    dict set params enable_port_rx_10g_clr_errblk_count    0\n    dict set params teng_tx_scram_user_seed                000000000000000\n    dict set params enable_port_rx_10g_descram_err         0\n    dict set params enable_port_rx_10g_blk_lock            0\n    dict set params enable_port_rx_10g_blk_sh_err          0\n    dict set params teng_tx_polinv_enable                  0\n    dict set params teng_tx_bitslip_enable                 0\n    dict set params teng_rx_polinv_enable                  0\n    dict set params teng_rx_bitslip_enable                 0\n    dict set params enable_port_tx_10g_bitslip             0\n    dict set params enable_port_rx_10g_bitslip             0\n    dict set params enable_port_rx_teng_prbs_status        0\n\n    set component_parameters {}\n\tforeach item [dict keys $params] {\n\t\tset val [dict get $params $item]\n\t\tlappend component_parameters --component-parameter=$item=$val\n\t}\n\n    connectal_altera_synth_ip $core_name $core_version $ip_name $component_parameters\n}\n\nproc create_xcvr_reset {channels} {\n    set core_name {altera_xcvr_reset_control}\n    set core_version {14.0}\n    set ip_name {altera_xcvr_reset_control_wrapper}\n\n\tdict set params CHANNELS              $channels\n\tdict set params PLLS                  4\n\tdict set params SYS_CLK_IN_MHZ        125\n\tdict set params SYNCHRONIZE_RESET     1\n\tdict set params REDUCED_SIM_TIME      1\n\tdict set params TX_PLL_ENABLE         1\n\tdict set params T_PLL_POWERDOWN       1000\n\tdict set params SYNCHRONIZE_PLL_RESET 0\n\tdict set params TX_ENABLE             1\n\tdict set params TX_PER_CHANNEL        0\n\tdict set params T_TX_DIGITALRESET     20\n\tdict set params T_PLL_LOCK_HYST       0\n\tdict set params RX_ENABLE             1\n\tdict set params RX_PER_CHANNEL        0\n\tdict set params T_RX_ANALOGRESET      40\n\tdict set params T_RX_DIGITALRESET     4000\n\n    set component_parameters {}\n\tforeach item [dict keys $params] {\n\t\tset val [dict get $params $item]\n\t\tlappend component_parameters --component-parameter=$item=$val\n\t}\n\n    connectal_altera_synth_ip $core_name $core_version $ip_name $component_parameters\n}\n\nif {$NUMBER_OF_10G_PORTS != \"\"} {\nset v [expr \"$NUMBER_OF_10G_PORTS * 2\"]\ncreate_altera_10gbe_pma $NUMBER_OF_10G_PORTS\ncreate_xcvr_reconfig alt_xcvr_reconfig 14.0 altera_xgbe_pma_reconfig_wrapper $v\ncreate_xcvr_reset $NUMBER_OF_10G_PORTS\n}\n"
  },
  {
    "path": "scripts/connectal-synth-ila.tcl",
    "content": "source \"board.tcl\"\nsource \"$connectaldir/scripts/connectal-synth-ip.tcl\"\n\n# for monitoring the slave connection to the portal\nconnectal_synth_ip ila 6.2 ila_connectal_1 [list CONFIG.C_PROBE12_WIDTH {16} CONFIG.C_PROBE11_WIDTH {16} CONFIG.C_PROBE10_WIDTH {32} CONFIG.C_PROBE7_WIDTH {32} CONFIG.C_PROBE4_WIDTH {32} CONFIG.C_PROBE1_WIDTH {32} CONFIG.C_DATA_DEPTH {4096} CONFIG.C_NUM_OF_PROBES {14} CONFIG.C_EN_STRG_QUAL {1} CONFIG.C_PROBE7_MU_CNT {2} CONFIG.C_PROBE6_MU_CNT {2} CONFIG.C_PROBE5_MU_CNT {2} CONFIG.C_PROBE4_MU_CNT {2} CONFIG.C_PROBE3_MU_CNT {2} CONFIG.C_PROBE2_MU_CNT {2} CONFIG.C_PROBE1_MU_CNT {2} CONFIG.C_PROBE0_MU_CNT {2} CONFIG.ALL_PROBE_SAME_MU_CNT {2}]\n\n# for monitoring the memory master connection from the portal, including 19 bit aruser and awuser for AwsF1\nconnectal_synth_ip ila 6.2 ila_connectal_2 [list \\\n    CONFIG.ALL_PROBE_SAME_MU_CNT {2} \\\n    CONFIG.C_DATA_DEPTH {4096} \\\n    CONFIG.C_EN_STRG_QUAL {1} \\\n    CONFIG.C_NUM_OF_PROBES {25} \\\n    CONFIG.C_PROBE0_MU_CNT {2} \\\n    CONFIG.C_PROBE1_MU_CNT {2} \\\n    CONFIG.C_PROBE1_WIDTH {64} \\\n    CONFIG.C_PROBE2_MU_CNT {2} \\\n    CONFIG.C_PROBE3_MU_CNT {2} \\\n    CONFIG.C_PROBE4_MU_CNT {2} \\\n    CONFIG.C_PROBE4_WIDTH {64} \\\n    CONFIG.C_PROBE5_MU_CNT {2} \\\n    CONFIG.C_PROBE6_MU_CNT {2} \\\n    CONFIG.C_PROBE7_MU_CNT {2} \\\n    CONFIG.C_PROBE7_WIDTH {512} \\\n    CONFIG.C_PROBE10_WIDTH {512} \\\n    CONFIG.C_PROBE12_WIDTH {64} \\\n    CONFIG.C_PROBE13_WIDTH {19} \\\n    CONFIG.C_PROBE14_WIDTH {19} \\\n    CONFIG.C_PROBE15_WIDTH {8} \\\n    CONFIG.C_PROBE16_WIDTH {8} \\\n    CONFIG.C_PROBE17_WIDTH {3} \\\n    CONFIG.C_PROBE18_WIDTH {3} \\\n    CONFIG.C_PROBE19_WIDTH {16} \\\n    CONFIG.C_PROBE20_WIDTH {16} \\\n    CONFIG.C_PROBE21_WIDTH {16} \\\n    CONFIG.C_PROBE22_WIDTH {2} \\\n    CONFIG.C_PROBE23_WIDTH {1} \\\n    CONFIG.C_PROBE24_WIDTH {1} \\\n    ]\n\nconnectal_synth_ip ila 6.2 ila_connectal_3 [list \\\n    CONFIG.ALL_PROBE_SAME_MU_CNT {2} \\\n    CONFIG.C_DATA_DEPTH {4096} \\\n    CONFIG.C_EN_STRG_QUAL {1} \\\n    CONFIG.C_NUM_OF_PROBES {26} \\\n    CONFIG.C_PROBE0_MU_CNT {2} \\\n    CONFIG.C_PROBE1_MU_CNT {2} \\\n    CONFIG.C_PROBE1_WIDTH {64} \\\n    CONFIG.C_PROBE2_MU_CNT {2} \\\n    CONFIG.C_PROBE3_MU_CNT {2} \\\n    CONFIG.C_PROBE4_MU_CNT {2} \\\n    CONFIG.C_PROBE4_WIDTH {64} \\\n    CONFIG.C_PROBE5_MU_CNT {2} \\\n    CONFIG.C_PROBE6_MU_CNT {2} \\\n    CONFIG.C_PROBE7_MU_CNT {2} \\\n    CONFIG.C_PROBE7_WIDTH {512} \\\n    CONFIG.C_PROBE10_WIDTH {512} \\\n    CONFIG.C_PROBE12_WIDTH {64} \\\n    CONFIG.C_PROBE13_WIDTH {19} \\\n    CONFIG.C_PROBE14_WIDTH {19} \\\n    CONFIG.C_PROBE15_WIDTH {8} \\\n    CONFIG.C_PROBE16_WIDTH {8} \\\n    CONFIG.C_PROBE17_WIDTH {3} \\\n    CONFIG.C_PROBE18_WIDTH {3} \\\n    CONFIG.C_PROBE19_WIDTH {16} \\\n    CONFIG.C_PROBE20_WIDTH {16} \\\n    CONFIG.C_PROBE21_WIDTH {16} \\\n    CONFIG.C_PROBE22_WIDTH {2} \\\n    CONFIG.C_PROBE23_WIDTH {1} \\\n    CONFIG.C_PROBE24_WIDTH {1} \\\n    CONFIG.C_PROBE25_WIDTH {160} \\\n    ]\n"
  },
  {
    "path": "scripts/connectal-synth-ip.tcl",
    "content": "# Copyright (c) 2014 Quanta Research Cambridge, Inc\n#\n# Permission is hereby granted, free of charge, to any person obtaining a\n# copy of this software and associated documentation files (the \"Software\"),\n# to deal in the Software without restriction, including without limitation\n# the rights to use, copy, modify, merge, publish, distribute, sublicense,\n# and/or sell copies of the Software, and to permit persons to whom the\n# Software is furnished to do so, subject to the following conditions:\n#\n# The above copyright notice and this permission notice shall be included\n# in all copies or substantial portions of the Software.\n#\n# THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n# OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n# DEALINGS IN THE SOFTWARE.\n\nset scriptsdir [file dirname [info script] ]\nsource \"$scriptsdir/../../fpgamake/tcl/ipcore.tcl\"\n\n# Altera Specific\nproc create_xcvr_reconfig {core_name core_version ip_name n_interface} {\n \tset params [ dict create ]\n\tdict set params number_of_reconfig_interfaces $n_interface\n\tset component_parameters {}\n\tforeach item [dict keys $params] {\n\t\tset val [dict get $params $item]\n\t\tlappend component_parameters --component-parameter=$item=$val\n\t}\n    fpgamake_altera_ipcore $core_name $core_version $ip_name QUARTUS_SYNTH $component_parameters\n}\n\nproc connectal_synth_ip {core_name core_version ip_name params} {\n   fpgamake_ipcore $core_name $core_version $ip_name $params\n}\n\nproc connectal_altera_synth_ip {core_name core_version ip_name params} {\n   fpgamake_altera_ipcore $core_name $core_version $ip_name QUARTUS_SYNTH $params\n}\n\nproc connectal_altera_simu_ip {core_name core_version ip_name params} {\n   fpgamake_altera_ipcore $core_name $core_version $ip_name SIM_VERILOG $params\n}\n\n"
  },
  {
    "path": "scripts/connectal-synth-pcie-rp.tcl",
    "content": "source \"board.tcl\"\nsource \"$connectaldir/scripts/connectal-synth-ip.tcl\"\nsource \"$scriptsdir/../../fpgamake/tcl/ipcore.tcl\"\n\nif {$need_pcie == \"x7_gen2x8\"} {\nconnectal_synth_ip pcie_7x 3.0 pcie_7x_rp [list CONFIG.Device_Port_Type {Root_Port_of_PCI_Express_Root_Complex} CONFIG.Maximum_Link_Width {X8} CONFIG.Link_Speed {5.0_GT/s} CONFIG.PCIe_Cap_Slot_Implemented {true} CONFIG.Xlnx_Ref_Board {VC707} CONFIG.en_ext_pipe_interface {true}]\n}\n\nif {$need_pcie == \"x7_gen3x8\"} {\n    if {[version -short] >= \"2015.3\"} {\n\tset pcieversion {4.1}\n    } elseif {[version -short] >= \"2015.2\"} {\n\tset pcieversion {4.0}\n    } else {\n\tset pcieversion {3.0}\n    }\n    set maxlinkwidth {X8}\n    connectal_synth_ip pcie3_7x $pcieversion pcie3_7x_rp [list CONFIG.device_port_type {Root_Port_of_PCI_Express_Root_Complex} CONFIG.PL_LINK_CAP_MAX_LINK_WIDTH {X8} CONFIG.PL_LINK_CAP_MAX_LINK_SPEED {8.0_GT/s} CONFIG.axisten_if_enable_client_tag {false} CONFIG.AXISTEN_IF_RC_STRADDLE {false} CONFIG.pf0_bar0_size {8} CONFIG.PF0_DEV_CAP2_TPH_COMPLETER_SUPPORT {true} CONFIG.pf0_dsn_enabled {true} CONFIG.mode_selection {Advanced} CONFIG.pipe_mode_sim {Enable_External_PIPE_Interface} CONFIG.en_ext_clk {false} CONFIG.shared_logic_in_core {true} CONFIG.pcie_blk_locn {X0Y0} CONFIG.tandem_mode {None} CONFIG.axisten_if_width {256_bit} CONFIG.PF0_DEVICE_ID {7138} CONFIG.pf0_class_code_base {06} CONFIG.PF0_CLASS_CODE {068000} CONFIG.pf0_base_class_menu {Bridge_device} CONFIG.pf0_sub_class_interface_menu {InfiniBand_to_PCI_host_bridge} CONFIG.PF1_DEVICE_ID {7011} CONFIG.pf1_class_code_base {06} CONFIG.PF1_CLASS_CODE {068000} CONFIG.pf1_base_class_menu {Bridge_device} CONFIG.pf1_sub_class_interface_menu {InfiniBand_to_PCI_host_bridge} CONFIG.pf0_bar0_type {Memory} CONFIG.pf0_bar1_type {N/A} CONFIG.pf0_bar2_type {N/A} CONFIG.pf0_bar3_type {N/A} CONFIG.pf0_bar4_type {N/A} CONFIG.pf0_bar5_type {N/A} CONFIG.pf1_bar0_type {N/A} CONFIG.pf1_bar1_type {N/A} CONFIG.pf1_bar2_type {N/A} CONFIG.pf1_bar3_type {N/A} CONFIG.pf1_bar4_type {N/A} CONFIG.pf1_bar5_type {N/A} CONFIG.pf0_sriov_bar0_type {Memory} CONFIG.pf0_sriov_bar1_type {N/A} CONFIG.pf0_sriov_bar2_type {N/A} CONFIG.pf0_sriov_bar3_type {N/A} CONFIG.pf0_sriov_bar4_type {N/A} CONFIG.pf0_sriov_bar5_type {N/A} CONFIG.pf1_sriov_bar0_type {Memory} CONFIG.pf1_sriov_bar1_type {N/A} CONFIG.pf1_sriov_bar2_type {N/A} CONFIG.pf1_sriov_bar3_type {N/A} CONFIG.pf1_sriov_bar4_type {N/A} CONFIG.pf1_sriov_bar5_type {N/A} CONFIG.silicon_rev {Production} CONFIG.pipe_sim {false} CONFIG.axisten_freq {250} CONFIG.aspm_support {No_ASPM} CONFIG.en_ext_pipe_interface {true}]\n}\n"
  },
  {
    "path": "scripts/connectal-synth-pcie.tcl",
    "content": "source \"board.tcl\"\nsource \"$connectaldir/scripts/connectal-synth-ip.tcl\"\nsource \"$scriptsdir/../../fpgamake/tcl/ipcore.tcl\"\n\nif {\"$XILINX\" == \"1\"} {\n    set x7_pcie_version 2.1\n    if {[version -short] == \"2013.2\"} {\n\tset x7_pcieversion {2.1}\n    }\n    if {[version -short] >= \"2015.1\"} {\n\tset x7_pcieversion {3.1}\n    }\n    if {[version -short] >= \"2015.3\"} {\n\tset x7_pcieversion {3.2}\n    }\n    if {[version -short] >= \"2016.1\"} {\n\tset x7_pcieversion {3.3}\n    }\n}\n\nif {$need_pcie == \"x7_gen1x8\"} {\n    set maxlinkwidth {X8}\n    if {$boardname == {zc706}} {\n\tset maxlinkwidth {X4}\n    }\n    if {$boardname == {ac701}} {\n\tset maxlinkwidth {X4}\n    }\n\n    ##\n    ## MSIX Table and PBA offset here is multiplied by 8, so 0x200 -> 4096\n    connectal_synth_ip pcie_7x $x7_pcieversion pcie_7x_0 [list CONFIG.mode_selection {Advanced} CONFIG.ASPM_Optionality {true} CONFIG.Disable_Tx_ASPM_L0s {true} CONFIG.Buf_Opt_BMA {true} CONFIG.Bar0_64bit {true} CONFIG.Bar0_Size {16} CONFIG.Bar0_Scale {Kilobytes} CONFIG.Bar2_64bit {true} CONFIG.Bar2_Enabled {true} CONFIG.Bar2_Scale {Megabytes} CONFIG.Bar2_Size {1} CONFIG.Base_Class_Menu {Memory_controller} CONFIG.Device_ID {c100} CONFIG.IntX_Generation {false} CONFIG.MSI_Enabled {false} CONFIG.MSIx_Enabled {true} CONFIG.MSIx_PBA_Offset {1f0} CONFIG.MSIx_Table_Offset {200} CONFIG.MSIx_Table_Size {10} CONFIG.Maximum_Link_Width $maxlinkwidth CONFIG.Subsystem_ID {a705} CONFIG.Subsystem_Vendor_ID {1be7} CONFIG.Use_Class_Code_Lookup_Assistant {false} CONFIG.Vendor_ID {1be7} ]\n}\n\nif {$need_pcie == \"x7_gen2x8\"} {\n    set maxlinkwidth \"X$PcieLanes\"\n    set maxinterfacebits [expr 16 * $PcieLanes]\n    set maxinterfacewidth \"${maxinterfacebits}_bit\"\n    set linkspeed {5.0_GT/s}\n    ## MSIX Table and PBA offset here is multiplied by 8, so 0x200 -> 4096\n    connectal_synth_ip pcie_7x $x7_pcieversion pcie2_7x_0 [list CONFIG.mode_selection {Advanced} CONFIG.ASPM_Optionality {true} CONFIG.Disable_Tx_ASPM_L0s {true} CONFIG.Buf_Opt_BMA {true} CONFIG.Bar0_64bit {true} CONFIG.Bar0_Size {16} CONFIG.Bar0_Scale {Kilobytes} CONFIG.Bar2_64bit {true} CONFIG.Bar2_Enabled {true} CONFIG.Bar2_Scale {Megabytes} CONFIG.Bar2_Size {1} CONFIG.Base_Class_Menu {Memory_controller} CONFIG.Device_ID {c100} CONFIG.IntX_Generation {false} CONFIG.MSI_Enabled {false} CONFIG.MSIx_Enabled {true} CONFIG.MSIx_PBA_Offset {1f0} CONFIG.MSIx_Table_Offset {200} CONFIG.MSIx_Table_Size {10} CONFIG.Maximum_Link_Width $maxlinkwidth CONFIG.Subsystem_ID {a705} CONFIG.Subsystem_Vendor_ID {1be7} CONFIG.Use_Class_Code_Lookup_Assistant {false} CONFIG.Vendor_ID {1be7} CONFIG.Link_Speed $linkspeed CONFIG.Interface_Width $maxinterfacewidth CONFIG.en_ext_clk {false} CONFIG.PCIe_Debug_Ports {false} CONFIG.shared_logic_in_core {true} \\\nCONFIG.VC_Cap_Enabled {true} \\\nCONFIG.AER_Enabled {true} CONFIG.AER_Multiheader {true} CONFIG.AER_Permit_Root_Error_Update {true} CONFIG.AER_Completion_Timeout {true} CONFIG.AER_Uncorrectable_Internal_Error {true} CONFIG.AER_MC_Blocked_TLP {true} CONFIG.AER_Receiver_Overflow {true} CONFIG.AER_TLP_Prefix_Blocked {true}  CONFIG.Optional_Error_Support {059400}]\n}\n\nif {$need_pcie == \"x7_gen3x8\"} {\n\n    if {[version -short] >= \"2017.1\"} {\n\tset x7_pcieversion {4.3}\n    }\n\n    set maxlinkwidth {X8}\n    connectal_synth_ip pcie3_7x $x7_pcieversion pcie3_7x_0 [list \\\n\t\t\t\t\t\t\t CONFIG.PL_LINK_CAP_MAX_LINK_WIDTH {X8} CONFIG.PL_LINK_CAP_MAX_LINK_SPEED {8.0_GT/s} \\\n\t\t\t\t\t\t\t CONFIG.TL_PF_ENABLE_REG {false} CONFIG.vendor_id {1be7} CONFIG.PF0_DEVICE_ID {c100} \\\n\t\t\t\t\t\t\t CONFIG.PF0_SUBSYSTEM_VENDOR_ID {1be7} CONFIG.PF0_SUBSYSTEM_ID {a705} \\\n\t\t\t\t\t\t\t CONFIG.PF0_Use_Class_Code_Lookup_Assistant {false} CONFIG.pf0_base_class_menu \\\n\t\t\t\t\t\t\t {Memory_controller} CONFIG.pf0_bar0_64bit {true} CONFIG.pf0_bar0_size {16} \\\n\t\t\t\t\t\t\t CONFIG.pf0_bar2_enabled {true} CONFIG.pf0_bar2_64bit {true} CONFIG.pf0_bar2_scale \\\n\t\t\t\t\t\t\t {Megabytes} CONFIG.pf0_bar2_size {1} CONFIG.PF0_INTERRUPT_PIN {NONE} \\\n\t\t\t\t\t\t\t CONFIG.pf0_msi_enabled {false} CONFIG.pf0_msix_enabled {true} \\\n\t\t\t\t\t\t\t CONFIG.PF0_MSIX_CAP_TABLE_SIZE {010} CONFIG.PF0_MSIX_CAP_TABLE_OFFSET {00001000} \\\n\t\t\t\t\t\t\t CONFIG.PF0_MSIX_CAP_PBA_OFFSET {00000f80} CONFIG.axisten_if_width {256_bit} \\\n\t\t\t\t\t\t\t CONFIG.AXISTEN_IF_RC_STRADDLE {false} CONFIG.AXISTEN_IF_ENABLE_CLIENT_TAG {false} \\\n\t\t\t\t\t\t\t CONFIG.cfg_ctl_if {true} CONFIG.cfg_ext_if {false} CONFIG.cfg_fc_if {false} \\\n\t\t\t\t\t\t\t CONFIG.cfg_mgmt_if {false} CONFIG.cfg_status_if {true} CONFIG.cfg_tx_msg_if \\\n\t\t\t\t\t\t\t {false} CONFIG.en_ext_clk {false} CONFIG.axisten_freq {250} \\\n\t\t\t\t\t\t\t CONFIG.PF0_PM_CAP_SUPP_D1_STATE {false} CONFIG.pf0_dsn_enabled {true} \\\n\t\t\t\t\t\t\t CONFIG.mode_selection {Advanced} CONFIG.pcie_blk_locn {X0Y1} \\\n\t\t\t\t\t\t\t CONFIG.per_func_status_if {false} CONFIG.en_ext_clk {false} CONFIG.rcv_msg_if \\\n\t\t\t\t\t\t\t {false} CONFIG.tx_fc_if {false} CONFIG.shared_logic_in_core {true} \\\n\t\t\t\t\t\t\t CONFIG.en_msi_per_vec_masking {false} \\\n\t\t\t\t\t\t\t CONFIG.pf0_vc_cap_enabled {true} ]\n# add the following to enable PF1:\n# CONFIG.TL_PF_ENABLE_REG {true} CONFIG.PF1_DEVICE_ID {c100} \\\n# CONFIG.pf1_bar0_64bit {true} CONFIG.pf1_bar0_size {16} \\\n# CONFIG.pf1_bar2_enabled {true} CONFIG.pf1_bar2_64bit {true} \\\n# CONFIG.pf1_bar2_scale {Megabytes} CONFIG.pf1_bar2_size {1} \\\n# CONFIG.pf1_msix_enabled {true} CONFIG.PF1_MSIX_CAP_TABLE_OFFSET \\\n# {00000400} CONFIG.PF1_MSIX_CAP_PBA_OFFSET {00000500} \\\n# CONFIG.pf1_dsn_enabled {true} CONFIG.pf1_bar0_enabled {true} \\\n# CONFIG.pf1_bar0_type {Memory} CONFIG.pf1_bar0_scale {Kilobytes} \\\n# CONFIG.pf1_bar2_type {Memory} CONFIG.pf1_bar2_size {1} \\\n# CONFIG.PF1_MSIX_CAP_TABLE_SIZE {010} \\\n# CONFIG.PF1_MSIX_CAP_TABLE_OFFSET {00000200} \\\n# CONFIG.PF1_MSIX_CAP_PBA_OFFSET {000001f0} \\\n\n}\n\nif {$need_pcie == \"xu_gen3x8\"} {\n    if {[version -short] >= \"2017.1\"} {\n\tset ultrascale_pcieversion {4.4}\n    } elseif {[version -short] >= \"2016.2\"} {\n\tset ultrascale_pcieversion {4.2}\n    }\n    set maxlinkwidth {X8}\n    connectal_synth_ip pcie3_ultrascale $ultrascale_pcieversion pcie3_ultrascale_0 [list \\\n\t\t\t\t\t\t\t\t\t     CONFIG.PF0_DEVICE_ID {c100} \\\n\t\t\t\t\t\t\t\t\t     CONFIG.PF0_MSIX_CAP_PBA_BIR {BAR_1:0} \\\n\t\t\t\t\t\t\t\t\t     CONFIG.PF0_MSIX_CAP_PBA_OFFSET {00000f80} \\\n\t\t\t\t\t\t\t\t\t     CONFIG.PF0_MSIX_CAP_TABLE_BIR {BAR_1:0} \\\n\t\t\t\t\t\t\t\t\t     CONFIG.PF0_MSIX_CAP_TABLE_OFFSET {00001000} \\\n\t\t\t\t\t\t\t\t\t     CONFIG.PF0_MSIX_CAP_TABLE_SIZE {16} \\\n\t\t\t\t\t\t\t\t\t     CONFIG.PF0_SUBSYSTEM_ID {a705} \\\n\t\t\t\t\t\t\t\t\t     CONFIG.PF0_SUBSYSTEM_VENDOR_ID {1be7} \\\n\t\t\t\t\t\t\t\t\t     CONFIG.PF1_DEVICE_ID {8011} \\\n\t\t\t\t\t\t\t\t\t     CONFIG.PF1_MSIX_CAP_PBA_BIR {BAR_0} \\\n\t\t\t\t\t\t\t\t\t     CONFIG.PF1_MSIX_CAP_TABLE_BIR {BAR_0} \\\n\t\t\t\t\t\t\t\t\t     CONFIG.PL_LINK_CAP_MAX_LINK_SPEED {8.0_GT/s} \\\n\t\t\t\t\t\t\t\t\t     CONFIG.PL_LINK_CAP_MAX_LINK_WIDTH {X8} \\\n\t\t\t\t\t\t\t\t\t     CONFIG.aspm_support {No_ASPM} \\\n\t\t\t\t\t\t\t\t\t     CONFIG.axisten_freq {250} \\\n\t\t\t\t\t\t\t\t\t     CONFIG.axisten_if_width {256_bit} \\\n\t\t\t\t\t\t\t\t\t     CONFIG.coreclk_freq {250} \\\n\t\t\t\t\t\t\t\t\t     CONFIG.mode_selection {Advanced} \\\n\t\t\t\t\t\t\t\t\t     CONFIG.pf0_bar0_64bit {true} \\\n\t\t\t\t\t\t\t\t\t     CONFIG.pf0_bar0_scale {Kilobytes} \\\n\t\t\t\t\t\t\t\t\t     CONFIG.pf0_bar0_size {16} \\\n\t\t\t\t\t\t\t\t\t     CONFIG.pf0_bar2_enabled {true} \\\n\t\t\t\t\t\t\t\t\t     CONFIG.pf0_bar2_scale {Megabytes} \\\n\t\t\t\t\t\t\t\t\t     CONFIG.pf0_bar2_size {1} \\\n\t\t\t\t\t\t\t\t\t     CONFIG.pf0_bar2_type {Memory} \\\n\t\t\t\t\t\t\t\t\t     CONFIG.pf0_dev_cap_max_payload {1024_bytes} \\\n\t\t\t\t\t\t\t\t\t     CONFIG.pf0_dsn_enabled {true} \\\n\t\t\t\t\t\t\t\t\t     CONFIG.pf0_msix_enabled {true} \\\n\t\t\t\t\t\t\t\t\t     CONFIG.plltype {QPLL1} \\\n\t\t\t\t\t\t\t\t\t     CONFIG.vendor_id {1be7} \\\n                                         CONFIG.xlnx_ref_board {VCU108} \\\n                                         CONFIG.AXISTEN_IF_RC_STRADDLE {false}\n\t\t\t\t\t\t\t\t\t    ]\n# add the following to enable PF1:\n# CONFIG.TL_PF_ENABLE_REG {true} CONFIG.PF1_DEVICE_ID {c100} \\\n# CONFIG.pf1_bar0_64bit {true} CONFIG.pf1_bar0_size {16} \\\n# CONFIG.pf1_bar2_enabled {true} CONFIG.pf1_bar2_64bit {true} \\\n# CONFIG.pf1_bar2_scale {Megabytes} CONFIG.pf1_bar2_size {1} \\\n# CONFIG.pf1_msix_enabled {true} CONFIG.PF1_MSIX_CAP_TABLE_OFFSET \\\n# {00000400} CONFIG.PF1_MSIX_CAP_PBA_OFFSET {00000500} \\\n# CONFIG.pf1_dsn_enabled {true} CONFIG.pf1_bar0_enabled {true} \\\n# CONFIG.pf1_bar0_type {Memory} CONFIG.pf1_bar0_scale {Kilobytes} \\\n# CONFIG.pf1_bar2_type {Memory} CONFIG.pf1_bar2_size {1} \\\n# CONFIG.PF1_MSIX_CAP_TABLE_SIZE {010} \\\n# CONFIG.PF1_MSIX_CAP_TABLE_OFFSET {00000200} \\\n# CONFIG.PF1_MSIX_CAP_PBA_OFFSET {000001f0} \\\n\n}\n\nif {$need_pcie == \"xuplus_gen3x8\"} {\n    if {[version -short] >= \"2017.4\"} {\n\tset ultrascale_pcieversion {1.3}\n    }\n    set maxlinkwidth $PcieLanes\n    connectal_synth_ip pcie4_uscale_plus $ultrascale_pcieversion pcie_uscale_plus_0 \\\n        [list \\\n             CONFIG.PF0_DEVICE_ID {c100} \\\n             CONFIG.PF0_MSIX_CAP_PBA_BIR {BAR_1:0} \\\n             CONFIG.PF0_MSIX_CAP_PBA_OFFSET {00000f80} \\\n             CONFIG.PF0_MSIX_CAP_TABLE_BIR {BAR_1:0} \\\n             CONFIG.PF0_MSIX_CAP_TABLE_OFFSET {00001000} \\\n             CONFIG.PF0_MSIX_CAP_TABLE_SIZE {16} \\\n             CONFIG.PF0_SUBSYSTEM_ID {a705} \\\n             CONFIG.PF0_SUBSYSTEM_VENDOR_ID {1be7} \\\n             CONFIG.PF1_DEVICE_ID {8011} \\\n             CONFIG.MSI_X_OPTIONS {MSI-X_External} \\\n             CONFIG.PF1_MSIX_CAP_PBA_BIR {BAR_0} \\\n             CONFIG.PF1_MSIX_CAP_TABLE_BIR {BAR_0} \\\n             CONFIG.PL_LINK_CAP_MAX_LINK_SPEED {8.0_GT/s} \\\n             CONFIG.PL_LINK_CAP_MAX_LINK_WIDTH {X8} \\\n             CONFIG.aspm_support {No_ASPM} \\\n             CONFIG.axisten_freq {250} \\\n             CONFIG.axisten_if_width {256_bit} \\\n             CONFIG.coreclk_freq {250} \\\n             CONFIG.mode_selection {Advanced} \\\n             CONFIG.pf0_bar0_64bit {true} \\\n             CONFIG.pf0_bar0_scale {Kilobytes} \\\n             CONFIG.pf0_bar0_size {16} \\\n             CONFIG.pf0_bar2_enabled {true} \\\n             CONFIG.pf0_bar2_scale {Megabytes} \\\n             CONFIG.pf0_bar2_size {1} \\\n             CONFIG.pf0_bar2_type {Memory} \\\n             CONFIG.pf0_dev_cap_max_payload {1024_bytes} \\\n             CONFIG.pf0_dsn_enabled {true} \\\n             CONFIG.pf0_msix_enabled {true} \\\n             CONFIG.plltype {QPLL1} \\\n             CONFIG.vendor_id {1be7} \\\n             CONFIG.xlnx_ref_board {VCU118} \\\n             CONFIG.AXISTEN_IF_RC_STRADDLE {false} \\\n             CONFIG.extended_tag_field {false} \\\n             CONFIG.axisten_if_enable_client_tag {true}\n        ]\n\n}\n\nproc create_pcie_sv_hip_ast {mode} {\n    global boardname\n    set pcieversion {2.1}\n    set maxlinkwidth {x8}\n    set core_name {altera_pcie_sv_hip_ast}\n    set core_version {14.0}\n    set ip_name {altera_pcie_sv_hip_ast_wrapper}\n\n    set vendor_id {0x1be7}\n    set device_id {0xc100}\n    set class_code {0xde5000}\n\n\tset params [ dict create ]\n\tdict set params lane_mask_hwtcl                      $maxlinkwidth\n\tdict set params gen123_lane_rate_mode_hwtcl          \"Gen2 (5.0 Gbps)\"\n\tdict set params port_type_hwtcl                      \"Native endpoint\"\n\tdict set params pcie_spec_version_hwtcl              $pcieversion\n\tdict set params ast_width_hwtcl                      \"Avalon-ST 128-bit\"\n\tdict set params rxbuffer_rxreq_hwtcl                 \"Low\"\n\tdict set params pll_refclk_freq_hwtcl                \"100 MHz\"\n\tdict set params set_pld_clk_x1_625MHz_hwtcl          0\n    # use_rx_be_hwtcl is a deprecated signal\n\tdict set params use_rx_st_be_hwtcl                   1\n\tdict set params use_ast_parity                       0\n\tdict set params multiple_packets_per_cycle_hwtcl     0\n\tdict set params in_cvp_mode_hwtcl                    0\n\tdict set params use_tx_cons_cred_sel_hwtcl           0\n\tdict set params use_config_bypass_hwtcl              0\n\tdict set params hip_reconfig_hwtcl                   0\n\tdict set params hip_tag_checking_hwtcl               1\n\tdict set params enable_power_on_rst_pulse_hwtcl      0\n\n\tdict set params bar0_type_hwtcl                      1\n\tdict set params bar0_size_mask_hwtcl                 14\n\tdict set params bar0_io_space_hwtcl                  \"Disabled\"\n\tdict set params bar0_64bit_mem_space_hwtcl           \"Enabled\"\n\tdict set params bar0_prefetchable_hwtcl              \"Disabled\"\n\n\tdict set params bar1_type_hwtcl                      0\n\tdict set params bar1_size_mask_hwtcl                 0\n\tdict set params bar1_io_space_hwtcl                  \"Disabled\"\n\tdict set params bar1_prefetchable_hwtcl              \"Disabled\"\n\n\tdict set params bar2_type_hwtcl                      1\n\tdict set params bar2_size_mask_hwtcl                 20\n\tdict set params bar2_io_space_hwtcl                  \"Disabled\"\n\tdict set params bar2_64bit_mem_space_hwtcl           \"Enabled\"\n\tdict set params bar2_prefetchable_hwtcl              \"Disabled\"\n\n\tdict set params bar3_type_hwtcl                          0\n\tdict set params\tbar3_size_mask_hwtcl                     0\n\tdict set params\tbar3_io_space_hwtcl                      \"Disabled\"\n\tdict set params\tbar3_prefetchable_hwtcl                  \"Disabled\"\n\n\tdict set params\tbar4_size_mask_hwtcl                     0\n\tdict set params\tbar4_io_space_hwtcl                      \"Disabled\"\n\tdict set params\tbar4_64bit_mem_space_hwtcl               \"Disabled\"\n\tdict set params\tbar4_prefetchable_hwtcl                  \"Disabled\"\n\n\tdict set params\tbar5_size_mask_hwtcl                     0\n\tdict set params\tbar5_io_space_hwtcl                      \"Disabled\"\n\tdict set params\tbar5_prefetchable_hwtcl                  \"Disabled\"\n\tdict set params\texpansion_base_address_register_hwtcl    0\n\tdict set params\tio_window_addr_width_hwtcl               0\n\tdict set params\tprefetchable_mem_window_addr_width_hwtcl 0\n\n\tdict set params\tvendor_id_hwtcl                          $vendor_id\n\tdict set params\tdevice_id_hwtcl                          $device_id\n\tdict set params\trevision_id_hwtcl                        1\n\tdict set params\tclass_code_hwtcl                         $class_code\n\tdict set params\tsubsystem_vendor_id_hwtcl                $vendor_id\n\tdict set params\tsubsystem_device_id_hwtcl                $device_id\n\tdict set params\tmax_payload_size_hwtcl                   512\n\tdict set params\textend_tag_field_hwtcl                   \"64\"\n\tdict set params\tcompletion_timeout_hwtcl                 \"ABCD\"\n\tdict set params\tenable_completion_timeout_disable_hwtcl  1\n\n\tdict set params use_aer_hwtcl                            0\n\tdict set params ecrc_check_capable_hwtcl                 0\n\tdict set params ecrc_gen_capable_hwtcl                   0\n\tdict set params use_crc_forwarding_hwtcl                 0\n\tdict set params port_link_number_hwtcl                   1\n\tdict set params dll_active_report_support_hwtcl          0\n\tdict set params surprise_down_error_support_hwtcl        0\n\tdict set params slotclkcfg_hwtcl                         1\n\tdict set params msi_multi_message_capable_hwtcl          \"1\"\n\tdict set params msi_64bit_addressing_capable_hwtcl       \"true\"\n\tdict set params msi_masking_capable_hwtcl                \"false\"\n\tdict set params msi_support_hwtcl                        \"true\"\n\tdict set params enable_function_msix_support_hwtcl       1\n\tdict set params msix_table_size_hwtcl                    16\n\tdict set params msix_table_offset_hwtcl                  \"4096\"\n\tdict set params msix_table_bir_hwtcl                     0\n\tdict set params msix_pba_offset_hwtcl                    \"3968\"\n\tdict set params msix_pba_bir_hwtcl                       0\n\n\tset component_parameters {}\n\tforeach item [dict keys $params] {\n\t\tset val [dict get $params $item]\n\t\tlappend component_parameters --component-parameter=$item=$val\n\t}\n\n    if { [string match \"SIMULATION\" $mode]} {\n        connectal_altera_simu_ip $core_name $core_version $ip_name $component_parameters\n    } else {\n        connectal_altera_synth_ip $core_name $core_version $ip_name $component_parameters\n    }\n}\n\nproc create_pcie_reconfig {mode} {\n    set core_name {altera_pcie_reconfig_driver}\n    set core_version {14.0}\n    set ip_name {altera_pcie_reconfig_driver_wrapper}\n\n    set params [ dict create ]\n\tdict set params INTENDED_DEVICE_FAMILY        \"Stratix V\"\n\tdict set params gen123_lane_rate_mode_hwtcl   \"Gen2 (5.0 Gbps)\"\n\tdict set params number_of_reconfig_interfaces 10\n\n\tset component_parameters {}\n\tforeach item [dict keys $params ] {\n\t\tset val [dict get $params $item]\n\t\tlappend component_parameters --component-parameter=$item=$val\n\t}\n\n    if {[string match \"SIMULATION\" $mode]} {\n        connectal_altera_simu_ip $core_name $core_version $ip_name $component_parameters\n    } else {\n        connectal_altera_synth_ip $core_name $core_version $ip_name $component_parameters\n    }\n}\n\nproc create_pcie_hip_ast_ed {} {\n    set core_name {altera_pcie_hip_ast_ed}\n    set core_version {14.0}\n    set ip_name {altera_pcie_hip_ast_ed}\n\n    set params [ dict create ]\n\n    dict set params device_family_hwtcl              \"Stratix V\"\n    dict set params lane_mask_hwtcl                  \"x8\"\n    dict set params gen123_lane_rate_mode_hwtcl      \"Gen2 (5.0 Gbps)\"\n    dict set params pld_clockrate_hwtcl              250000000\n    dict set params port_type_hwtcl                  \"Native endpoint\"\n    dict set params ast_width_hwtcl                  \"Avalon-ST 128-bit\"\n    dict set params extend_tag_field_hwtcl           32\n    dict set params max_payload_size_hwtcl           256\n    dict set params num_of_func_hwtcl                1\n    dict set params multiple_packets_per_cycle_hwtcl 0\n    dict set params port_width_be_hwtcl              16\n    dict set params port_width_data_hwtcl            128\n    dict set params avalon_waddr_hwltcl              12\n    dict set params check_bus_master_ena_hwtcl       1\n    dict set params check_rx_buffer_cpl_hwtcl        1\n    dict set params use_crc_forwarding_hwtcl         0\n\n\tset component_parameters {}\n\tforeach item [dict keys $params ] {\n\t\tset val [dict get $params $item]\n\t\tlappend component_parameters --component-parameter=$item=$val\n\t}\n\n    connectal_altera_synth_ip $core_name $core_version $ip_name $component_parameters\n}\n\nproc create_pcie_xcvr_reconfig {mode core_name core_version ip_name n_interface} {\n \tset params [ dict create ]\n\tdict set params number_of_reconfig_interfaces $n_interface\n\tdict set params device_family                 \"Stratix V\"\n\tdict set params enable_offset                 1\n\tdict set params enable_lc                     1\n\tdict set params enable_dcd                    0\n\tdict set params enable_dcd_power_up           1\n\tdict set params enable_analog                 1\n\tdict set params enable_eyemon                 0\n\tdict set params enable_ber                    0\n\tdict set params enable_dfe                    0\n\tdict set params enable_adce                   1\n\tdict set params enable_mif                    0\n\tdict set params enable_pll                    0\n\n\tset component_parameters {}\n\tforeach item [dict keys $params] {\n\t\tset val [dict get $params $item]\n\t\tlappend component_parameters --component-parameter=$item=$val\n\t}\n    if {[string match \"SIMULATION\" $mode]} {\n        connectal_altera_simu_ip $core_name $core_version $ip_name $component_parameters\n    } else {\n        connectal_altera_synth_ip $core_name $core_version $ip_name $component_parameters\n    }\n}\n\nif {$need_pcie == \"s5_gen2x8\"} {\n    create_pcie_sv_hip_ast SYNTHESIS\n    create_pcie_xcvr_reconfig SYNTHESIS alt_xcvr_reconfig 14.0 alt_xcvr_reconfig_wrapper 10\n    create_pcie_reconfig SYNTHESIS\n    create_pcie_hip_ast_ed\n}\n\n# Stratix IV PCIe requires use of Megawizard\nif {$need_pcie == \"s4_gen2x8\"} {\n\tfpgamake_altera_qmegawiz $connectaldir/verilog/altera/siv_gen2x8 siv_gen2x8\n}\n"
  },
  {
    "path": "scripts/connectal-synth-pll.tcl",
    "content": "source \"board.tcl\"\nsource \"$connectaldir/scripts/connectal-synth-ip.tcl\"\n\nproc create_custom_pll {name refclk args} {\n    global ipdir boardname partname\n    set num [llength $args]\n\n    if {$num == 0} {\n        set error {wrong # args: should be at least \"create_custom_pll [refclk] [genclk0] ...\"}\n        error $error\n    }\n\n    puts \"Generating PLL with ref clock $refclk and output clock $args...\"\n\n    set params [ dict create ]\n    dict set params gui_reference_clock_frequency $refclk\n    dict set params gui_operation_mode            \"normal\"\n    dict set params gui_number_of_clocks          $num\n    dict set params gui_use_locked                \"false\"\n\n    set m 0\n    while {$m < 18} {\n        set key0 gui_output_clock_frequency$m\n        set key1 gui_phase_shift$m\n        set key2 gui_duty_cycle$m\n\n        if {$m < $num} {\n            dict set params $key0 [lindex $args $m]\n            dict set params $key1 0\n            dict set params $key2 50\n        } else {\n            dict set params $key0 0\n            dict set params $key1 0\n            dict set params $key2 50\n        }\n\n        incr m\n    }\n\n    set component_parameters {}\n\tforeach item [dict keys $params] {\n\t\tset val [dict get $params $item]\n\t\tlappend component_parameters --component-param=$item=$val\n\t}\n\n    set core_name {altera_pll}\n    set core_version {14.0}\n    set ip_name $name\n\n    exec -ignorestderr -- ip-generate \\\n            --project-directory=$ipdir/$boardname                            \\\n            --output-directory=$ipdir/$boardname/synthesis/$ip_name                   \\\n            --file-set=QUARTUS_SYNTH                                         \\\n            --report-file=html:$ipdir/$boardname/$ip_name.html               \\\n            --report-file=sopcinfo:$ipdir/$boardname/$ip_name.sopcinfo       \\\n            --report-file=cmp:$ipdir/$boardname/$ip_name.cmp                 \\\n            --report-file=svd:$ipdir/$boardname/synthesis/$ip_name/$ip_name.svd       \\\n            --report-file=qip:$ipdir/$boardname/synthesis/$ip_name/altera_$ip_name.qip     \\\n            --report-file=regmap:$ipdir/$boardname/synthesis/$ip_name/$ip_name.regmap \\\n            --report-file=xml:$ipdir/$boardname/$ip_name.xml                 \\\n            --system-info=DEVICE_FAMILY=StratixV                             \\\n            --system-info=DEVICE=$partname                                   \\\n            --system-info=DEVICE_SPEEDGRADE=2_H2                             \\\n            --language=VERILOG                                               \\\n            {*}$component_parameters\\\n            --component-name=$core_name                                      \\\n            --output-name=$ip_name\n}\n\ncreate_custom_pll pll_156 644.53125 156.25\n"
  },
  {
    "path": "scripts/connectal-synth-zynq-mpsoc.tcl",
    "content": "source \"board.tcl\"\nsource \"$connectaldir/scripts/connectal-synth-ip.tcl\"\n\nset prj_boardname $boardname\n\nif {\"$XILINX\" == \"1\"} {\n    set zynq_ultra_ps_version 2.0\n    if {[version -short] == \"2022.2\"} {\n        set zynq_ultra_ps_version {3.4}\n    }\n    if {[version -short] == \"2022.1\"} {\n        set zynq_ultra_ps_version {3.4}\n    }\n    if {[version -short] == \"2019.1\"} {\n        set zynq_ultra_ps_version {3.3}\n    }\n}\n\nconnectal_synth_ip zynq_ultra_ps_e ${zynq_ultra_ps_version} zynq_ultra_ps_e_0 [list \\\n\t\t\t\t\t\t\t  CONFIG.PSU__FPGA_PL1_ENABLE {1} \\\n\t\t\t\t\t\t\t  CONFIG.PSU__USE__M_AXI_GP0 {1} \\\n\t\t\t\t\t\t\t  CONFIG.PSU__USE__IRQ0 {1} \\\n\t\t\t\t\t\t\t  CONFIG.PSU__CRL_APB__PL0_REF_CTRL__FREQMHZ {200} \\\n\t\t\t\t\t\t\t  CONFIG.PSU__CRL_APB__PL1_REF_CTRL__FREQMHZ {200} \\\n\t\t\t\t\t\t\t  CONFIG.PSU__USE__S_AXI_GP0 {1} \\\n\t\t\t\t\t\t\t  CONFIG.PSU__USE__S_AXI_GP1 {1} \\\n\t\t\t\t\t\t\t  CONFIG.PSU__USE__S_AXI_GP2 {1} \\\n\t\t\t\t\t\t\t  CONFIG.PSU__USE__S_AXI_GP3 {1} \\\n\t\t\t\t\t\t\t  CONFIG.PSU__USE__S_AXI_GP4 {1} \\\n\t\t\t\t\t\t\t  CONFIG.PSU__USE__S_AXI_GP5 {1} \\\n\t\t\t\t\t\t\t  CONFIG.PSU__USE__S_AXI_GP6 {1} \\\n\t\t\t\t\t\t\t  CONFIG.PSU__USE__S_AXI_ACP {1} \\\n\t\t\t\t\t\t\t  CONFIG.PSU__USE__S_AXI_ACE {1} \\\n\t\t\t\t\t\t\t ]\n"
  },
  {
    "path": "scripts/cppgen.py",
    "content": "##\n## Copyright (C) 2013 Nokia, Inc\n## Copyright (c) 2013-2014 Quanta Research Cambridge, Inc.\n\n## Permission is hereby granted, free of charge, to any person\n## obtaining a copy of this software and associated documentation\n## files (the \"Software\"), to deal in the Software without\n## restriction, including without limitation the rights to use, copy,\n## modify, merge, publish, distribute, sublicense, and/or sell copies\n## of the Software, and to permit persons to whom the Software is\n## furnished to do so, subject to the following conditions:\n\n## The above copyright notice and this permission notice shall be\n## included in all copies or substantial portions of the Software.\n\n## THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n## EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n## MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n## NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n## BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n## ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n## CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n## SOFTWARE.\n\nfrom __future__ import print_function\n\nimport functools, json, math, os, re, sys, util\n\ntry:\n    basestring\nexcept NameError:\n    basestring = str  # Python 3 compatibility\n\ngeneratedSubdirectory = 'jni'\nverbose = False\ngenerateJson = True\ngeneratePacketOnly = False\nsuppressGeneratedMakefile = False\nsynchronousInvoke = False\nsizeofUint32_t = 4\ngeneratedVectors = []\nitypeNames = ['int', 'int8_t', 'uint8_t', 'int16_t', 'uint16_t', 'int32_t', 'uint32_t', 'uint64_t', 'SpecialTypeForSendingFd', 'ChannelType', 'DmaDbgRec']\n\nproxyClassPrefixTemplate='''\nclass %(className)sProxy : public Portal {\n    %(classNameOrig)sCb *cb;\npublic:\n    %(className)sProxy(int id, int tile = DEFAULT_TILE, %(classNameOrig)sCb *cbarg = &%(className)sProxyReq, int bufsize = %(classNameOrig)s_reqinfo, PortalPoller *poller = 0) :\n        Portal(id, tile, bufsize, %(handlerName)s, NULL, this, poller), cb(cbarg) {%(initName)s};\n    %(className)sProxy(int id, PortalTransportFunctions *transport, void *param, %(classNameOrig)sCb *cbarg = &%(className)sProxyReq, int bufsize = %(classNameOrig)s_reqinfo, PortalPoller *poller = 0) :\n        Portal(id, DEFAULT_TILE, bufsize, %(handlerName)s, NULL, transport, param, this, poller), cb(cbarg) {%(initName)s};\n    %(className)sProxy(int id, PortalPoller *poller) :\n        Portal(id, DEFAULT_TILE, %(classNameOrig)s_reqinfo, %(handlerName)s, NULL, NULL, NULL, this, poller), cb(&%(className)sProxyReq) {%(initName)s};\n'''\n\nsyncProxyTemplate='''\nprivate:\n    static int __internalHandleMessage(struct PortalInternal *p, unsigned int channel, int messageFd) {\n        return ((%(className)sProxy *)p->parent)->__internalResponse(p, channel);\n    }\n    sem_t *__internalWaitSemaphore;\n    sem_t __internalWaitSemaphoreBody;\n    uint64_t __internalWaitResult;\n    unsigned int __internalWaitMethod;\n    int __internalWaitSize;\n    void __internalInit() {\n        if ((__internalWaitSemaphore = sem_open(\"/semaphore\", O_CREAT, 0644, 0)) == SEM_FAILED) {\n            __internalWaitSemaphore = &__internalWaitSemaphoreBody;\n            if (sem_init(__internalWaitSemaphore, 1, 0) == 0)\n                return;\n            perror(\"sem_open failed\");\n            exit(-1);\n        }\n    }\n    int __internalResponse(struct PortalInternal *p, unsigned int channel) {\n        int tmpfd __attribute__ ((unused));\n        volatile unsigned int* temp_working_addr = p->transport->mapchannelInd(p, channel);\n        int offset = 0, remain = 1;\n        p->transport->recv(p, temp_working_addr, 1, &tmpfd);\n        uint32_t temp = p->transport->read(p, &temp_working_addr);\n        offset++;\n        int messageSize = temp & 0xffff;\n        temp = temp >> 16;\n        if (channel != __internalWaitMethod || __internalWaitSize != messageSize)\n             printf(\"%(className)sProxy: channel %%d/%%d waitSize %%d messageSize %%d\\\\n\", channel, __internalWaitMethod, __internalWaitSize, messageSize);\n        __internalWaitResult = 0;\n        uint16_t *dest = (uint16_t *)&__internalWaitResult;\n        while (messageSize > 0) {\n            if (remain == 0) {\n                p->transport->recv(p, temp_working_addr, 1, &tmpfd);\n                temp = p->transport->read(p, &temp_working_addr);\n                offset++;\n                remain = 2;\n            }\n            *dest++ = temp & 0xffff;\n            temp = temp >> 16;\n            messageSize -= 16;\n            --remain;\n        }\n        sem_post(__internalWaitSemaphore);\n        return 0;\n    }\n    uint64_t __internalWaitReturn(int method, int size) {\n        __internalWaitMethod = method;\n        __internalWaitSize = size;\n        sem_wait(__internalWaitSemaphore);\n        return __internalWaitResult;\n    }\n'''\n\nwrapperClassPrefixTemplate='''\nextern %(classNameOrig)sCb %(className)s_cbTable;\nclass %(className)sWrapper : public Portal {\npublic:\n    %(className)sWrapper(int id, int tile = DEFAULT_TILE, PORTAL_INDFUNC cba = %(className)s_handleMessage, int bufsize = %(classNameOrig)s_reqinfo, PortalPoller *poller = 0) :\n           Portal(id, tile, bufsize, cba, (void *)&%(className)s_cbTable, this, poller) {\n    };\n    %(className)sWrapper(int id, PortalTransportFunctions *transport, void *param, PORTAL_INDFUNC cba = %(className)s_handleMessage, int bufsize = %(classNameOrig)s_reqinfo, PortalPoller *poller=0):\n           Portal(id, DEFAULT_TILE, bufsize, cba, (void *)&%(className)s_cbTable, transport, param, this, poller) {\n    };\n    %(className)sWrapper(int id, PortalPoller *poller) :\n           Portal(id, DEFAULT_TILE, %(classNameOrig)s_reqinfo, %(className)s_handleMessage, (void *)&%(className)s_cbTable, this, poller) {\n    };\n    %(className)sWrapper(int id, PortalTransportFunctions *transport, void *param, PortalPoller *poller):\n           Portal(id, DEFAULT_TILE, %(classNameOrig)s_reqinfo, %(className)s_handleMessage, (void *)&%(className)s_cbTable, transport, param, this, poller) {\n    };\n    virtual void disconnect(void) {\n        printf(\"%(className)sWrapper.disconnect called %%d\\\\n\", pint.client_fd_number);\n    };\n'''\n\nhandleMessageTemplateDecl='''\nint %(className)s_handleMessage(struct PortalInternal *p, unsigned int channel, int messageFd)'''\n\nmessageStructTemplate='''\ntypedef struct {\n    %(paramStructDeclarations)s\n} %(channelName)sData;'''\n\nportalStructTemplate='''\ntypedef union {\n    %(messageStructDeclarations)s\n} %(className)sData;'''\n\nhandleMessageTemplateTmpDecl='''\n    int   tmp __attribute__ ((unused));'''\n\nhandleMessageTemplate1='''\n{\n    static int runaway = 0;%(tmpDecl)s\n    int tmpfd __attribute__ ((unused));\n    %(classNameOrig)sData tempdata __attribute__ ((unused));\n    memset(&tempdata, 0, sizeof(tempdata));\n    %(handleStartup)s\n    switch (channel) {'''\n\nhandleMessagePrepRecv='''\n        p->transport->recv(p, temp_working_addr, %(wordLen)s, &tmpfd);'''\nhandleMessagePrep='''\n        %(paramStructDemarshall)s'''\n\nhandleMessageCase='''\n    case %(channelNumber)s: {%(responseCase)s\n      } break;'''\n\nhandleMessageTemplate2='''\n    default:\n        PORTAL_PRINTF(\"%(className)s_handleMessage: unknown channel 0x%%x\\\\n\", channel);\n        if (runaway++ > 10) {\n            PORTAL_PRINTF(\"%(className)s_handleMessage: too many bogus indications, exiting\\\\n\");\n#ifndef __KERNEL__\n            exit(-1);\n#endif\n        }\n        return 0;\n    }\n    return 0;\n}\n'''\n\nproxyMethodTableDecl='''\n%(classNameOrig)sCb %(className)sProxyReq = {\n    %(methodTable)s\n};\n%(classNameOrig)sCb *p%(className)sProxyReq = &%(className)sProxyReq;\n'''\n\nproxyMethodTemplateDecl='''\nint %(className)s_%(methodName)s (%(paramProxyDeclarations)s )'''\n\nproxyMethodTemplateProlog='''\n    volatile unsigned int* temp_working_addr_start = p->transport->mapchannelReq(p, %(channelNumber)s, %(wordLenP1)s);\n    volatile unsigned int* temp_working_addr = temp_working_addr_start;\n    if (p->transport->busywait(p, %(channelNumber)s, \"%(className)s_%(methodName)s\")) return 1;'''\n\nproxyMethodTemplatePrologPacket='''\n    unsigned int temp_working_addr_start[%(wordLenP1)s + 1] = {0, (%(channelNumber)s << 16) | %(wordLenP1)s,'''\n\nproxyMethodTemplate='''\n{%(prolog)s\n    %(paramStructMarshall)s\n    p->transport->send(p, %(temp)s, (%(channelNumber)s << 16) | %(wordLenP1)s, %(fdName)s);\n    return 0;\n};\n'''\n\nproxyJMethodTemplate='''\n{\n    Json::Value request;\n    request.append(Json::Value(\"%(methodName)s\"));\n    %(paramStructMarshall)s\n\n    std::string requestjson = Json::FastWriter().write(request);;\n    connectalJsonSend(p, requestjson.c_str(), (int)%(channelNumber)s);\n    return 0;\n};\n'''\n\ndef indent(f, indentation):\n    for i in range(indentation):\n        f.write(' ')\n\ndef cName(x):\n    if isinstance(x, basestring):\n        x = x.replace(' ', '')\n        x = x.replace('.', '$')\n        return x\n    else:\n        return x.cName()\n\nclass paramInfo:\n    def __init__(self, name, width, shifted, datatype, assignOp):\n        self.name = name\n        self.width = width\n        self.shifted = shifted\n        self.datatype = datatype\n        self.assignOp = assignOp\n\n# resurse interface types and flattening all structs into a list of types\ndef collectMembers(scope, pitem):\n    if verbose:\n        print('collectM', pitem)\n    membtype = pitem['ptype']\n    while 1:\n        if membtype['name'] == 'Bit' or membtype['name'] == 'Int' or membtype['name'] == 'UInt' \\\n            or membtype['name'] == 'Float' or membtype['name'] == 'Bool' or membtype['name'] == 'fixed32':\n            return [('%s%s'%(scope,pitem['pname']),membtype)]\n        elif membtype['name'] == 'SpecialTypeForSendingFd':\n            return [('%s%s'%(scope,pitem['pname']),membtype)]\n        elif membtype['name'] == 'Vector':\n            nElt = typeNumeric(membtype['params'][0])\n            retitem = []\n            ind = 0;\n            while ind < nElt:\n                retitem.append([('%s%s'%(scope,pitem['pname']+'['+str(ind)+']'),membtype['params'][1])])\n                ind = ind + 1\n            return sum(retitem, [])\n        else:\n            td = globalv_globalvars[membtype['name']]\n            #print('instantiate', membtype['params'])\n            tdtype = td['tdtype']\n            #print('           ', membtype)\n            if tdtype.get('type') == 'Struct':\n                ns = '%s%s.' % (scope,pitem['pname'])\n                rv = map(functools.partial(collectMembers, ns), tdtype['elements'])\n                return sum(rv,[])\n            membtype = tdtype\n            if tdtype.get('type') == 'Enum':\n                return [('%s%s'%(scope,pitem['pname']),membtype)]\n            #print('resolved to type', membtype.get('type'), membtype['name'], membtype)\n\ndef typeNumeric(item):\n    global bsvdefines\n    tstr = item.get('name')\n    if tstr in globalv_globalvars:\n        decl = globalv_globalvars[tstr]\n        if decl.get('dtype') == 'TypeDef':\n            return typeNumeric(decl['tdtype'])\n    elif tstr in ['TAdd', 'TSub', 'TMul', 'TDiv', 'TLog', 'TExp', 'TMax', 'TMin']:\n        values = [typeNumeric(p) for p in item['params']]\n        if tstr == 'TAdd':\n            return values[0] + values[1]\n        elif tstr == 'TSub':\n            return values[0] - values[1]\n        elif tstr == 'TMul':\n            return values[0] * values[1]\n        elif tstr == 'TDiv':\n            return int(math.ceil(values[0] / float(values[1])))\n        elif tstr == 'TLog':\n            return int(math.ceil(math.log(values[0], 2)))\n        elif tstr == 'TExp':\n            return math.pow(2, values[0])\n        elif tstr == 'TMax':\n            return max(values[0], values[1])\n        elif tstr == 'TMax':\n            return min(values[0], values[1])\n    if tstr[0] == '`':\n        var = tstr[1:]\n        if var in bsvdefines:\n            return int(bsvdefines[var])\n    if tstr[0] >= 'A' and tstr[0] <= 'Z':\n        return tstr\n    return int(tstr)\n\ndef typeCName(item):\n    global generatedVectors\n    if item.get('type') == None:\n        cid = item['name'].replace(' ', '')\n        if cid == 'Bit':\n            numbits = typeNumeric(item['params'][0])\n            if numbits <= 8:\n                return 'uint8_t'\n            elif numbits <= 16:\n                return 'uint16_t'\n            elif numbits <= 32:\n                return 'uint32_t'\n            elif numbits <= 64:\n                return 'uint64_t'\n            else:\n                return 'char * /* %d bytes */' % ((numbits+7) / 8)\n        elif cid == 'bit':\n            return 'int'\n        elif cid == 'Bool':\n            return 'int'\n        elif cid == 'Int':\n            numbits = typeNumeric(item['params'][0])\n            if numbits <= 8:\n                return 'int8_t'\n            elif numbits <= 16:\n                return 'int16_t'\n            elif numbits <= 32:\n                return 'int32_t'\n            elif numbits <= 64:\n                return 'int64_t'\n            else:\n                assert(False)\n        elif cid == 'UInt':\n            numbits = typeNumeric(item['params'][0])\n            if numbits <= 8:\n                return 'uint8_t'\n            if numbits <= 16:\n                return 'uint16_t'\n            elif numbits <= 32:\n                return 'uint32_t'\n            elif numbits <= 64:\n                return 'uint64_t'\n            else:\n                assert(False)\n        elif cid == 'Float':\n            return 'float'\n        elif cid == 'Vector':\n            t = [typeNumeric(item['params'][0]), typeCName(item['params'][1])]\n            if t not in generatedVectors:\n                generatedVectors.append(t)\n            return 'bsvvector_L%s_L%d' % (t[1], t[0])\n        elif cid == 'Action':\n            return 'int'\n        elif cid == 'ActionValue':\n            assert(False)\n        if item.get('params'):\n            name = '%sL_%s_P' % (cid, '_'.join([typeCName(t) for t in item['params'] if t]))\n        else:\n            name = cid\n        return name\n    return item['name']\n\ndef signCName(item):\n    global generatedVectors\n    if item.get('type') == None:\n        cid = item['name'].replace(' ', '')\n        if cid == 'Bool':\n            return '1L'\n        elif cid == 'Int':\n            numbits = typeNumeric(item['params'][0])\n            if numbits <= 16:\n                return '0xffffL'\n            elif numbits <= 32:\n                return '0xffffffffL'\n    return None\n\ndef typeJson(item):\n    tname = typeCName(item)\n    if tname not in itypeNames:\n        #print('typeJson.other', tname, tname in itypeNames)\n        return 'other'\n    return tname\n\ndef hasBitWidth(item):\n    return item['name'] in ['Bit', 'Int', 'UInt', 'fixed32', 'bit']\n\ndef getNumeric(item):\n   if item['name'] in globalv_globalvars:\n       decl = globalv_globalvars[item['name']]\n       if decl.get('dtype') == 'TypeDef':\n           return getNumeric(decl['tdtype'])\n   elif item['name'] in ['TAdd', 'TSub', 'TMul', 'TDiv', 'TLog', 'TExp', 'TMax', 'TMin']:\n       values = [getNumeric(p) for p in item['params']]\n       if item['name'] == 'TAdd':\n           return values[0] + values[1]\n       elif item['name'] == 'TSub':\n           return values[0] - values[1]\n       elif item['name'] == 'TMul':\n           return values[0] * values[1]\n       elif item['name'] == 'TDiv':\n           return math.ceil(values[0] / float(values[1]))\n       elif item['name'] == 'TLog':\n           return math.ceil(math.log(values[0], 2))\n       elif item['name'] == 'TExp':\n           return math.pow(2, values[0])\n       elif item['name'] == 'TMax':\n           return max(values[0], values[1])\n       elif item['name'] == 'TMax':\n           return min(values[0], values[1])\n   elif item['name'].startswith('`'):\n       return int(bsvdefines[item['name'][1:]])\n   return int(item['name'])\n\ndef typeBitWidth(item):\n    if item['name'] == 'Bool':\n        return 1\n    if item['name'] == 'bit':\n        return 1\n    if item['name'] == 'Float':\n        return 32\n    if item['name'] == 'fixed32':\n        return 32\n    if item['name'] == 'SpecialTypeForSendingFd':\n        return 32\n    if item.get('type') == 'Enum':\n        enum_width = int(math.ceil(math.log(len(item['elements']), 2)))\n        # determines that the element is a scoped enum\n        if any([element[1] is not None for element in item['elements']]):\n            # calculate the maximum bit width among all enum items\n            enum_width = max([int(math.ceil(math.log(int(element[1] or i) + 1, 2)))\n                              for i, element in enumerate(item['elements'])])\n        return enum_width\n\n    if hasBitWidth(item):\n        width = item['params'][0]['name']\n        while width in globalv_globalvars:\n            decl = globalv_globalvars[width]\n            if decl.get('type') != 'TypeDef':\n                break\n            print('Resolving width', width, decl['tdtype'])\n            width = decl['tdtype']['name']\n        if re.match('[0-9]+', width):\n            return int(width)\n        return getNumeric(decl['tdtype'])\n    return 0\n\n# pack flattened struct-member list into 32-bit wide bins.  If a type is wider than 32-bits or\n# crosses a 32-bit boundary, it will appear in more than one bin (though with different ranges).\n# This is intended to mimick exactly Bluespec struct packing.  The padding must match the code\n# in Adapter.bsv.  the argument s is a list of bins, atoms is the flattened list, and pro represents\n# the number of bits already consumed from atoms[0].\ndef accumWords(s, pro, memberList):\n    if len(memberList) == 0:\n        if len(s) == 0:\n             return []\n        else:\n             return [s]\n    w = sum([x.width-x.shifted for x in s])\n    mitem = memberList[0]\n    name = mitem[0]\n    thisType = mitem[1]\n    aw = typeBitWidth(thisType)\n    #print('%d %d %d' %(aw, pro, w))\n    if (aw-pro+w == 32):\n        s.append(paramInfo(name,aw,pro,thisType,'='))\n        #print('%s (0)'% (name))\n        return [s]+accumWords([],0,memberList[1:])\n    if (aw-pro+w < 32):\n        s.append(paramInfo(name,aw,pro,thisType,'='))\n        #print('%s (1)'% (name))\n        return accumWords(s,0,memberList[1:])\n    else:\n        s.append(paramInfo(name,pro+(32-w),pro,thisType,'|='))\n        #print('%s (2)'% (name))\n        return [s]+accumWords([],pro+(32-w), memberList)\n\ndef generate_marshall(pfmt, argWords):\n    global fdName\n    retList = []\n    for w in argWords:\n        off = 0\n        fields = []\n        fmt = pfmt\n        outstr = ''\n        for e in w:\n            field = e.name\n            if typeCName(e.datatype) == 'float':\n                return pfmt % ('*(int*)&' + e.name)\n            mask = signCName(e.datatype)\n            if mask:\n                field = '(%s & %s)' % (field, mask)\n            if e.shifted:\n                field = '(%s>>%s)' % (field, e.shifted)\n            if off:\n                field = '(((unsigned long)%s)<<%s)' % (field, off)\n            if typeBitWidth(e.datatype) > 64:\n                field = '(const %s & std::bitset<%d>(0xFFFFFFFF)).to_ulong()' % (field, typeBitWidth(e.datatype))\n            fields.append(field)\n            off = off+e.width-e.shifted\n            if typeCName(e.datatype) == 'SpecialTypeForSendingFd':\n                fdName = field\n                fmt = 'p->transport->writefd(p, &temp_working_addr, %s);'\n                if generatePacketOnly:\n                    print('generate_marshall: when using \"generatePacketOnly\", fd items cannot be sent')\n                    sys.exit(-1)\n        retList.append(fmt % (''.join(util.intersperse('|', fields))))\n    return retList\n\ndef generate_demarshall(fmt, methodName, argWords):\n    retList = []\n    itemIndex = 0\n    for w in argWords:\n        off = 0\n        statements = []\n        if (fmt != ''):\n            statements.append(fmt)\n        for e in w:\n            # print(e.name+' (d)')\n            if generatePacketOnly:\n                field = 'temp_working_addr[%d]' % itemIndex\n            else:\n                field = 'tmp'\n            if typeCName(e.datatype) == 'float':\n                statements.append('tempdata.%s.%s %s *(float *)&(%s);'%(methodName, e.name, e.assignOp, field))\n                continue\n            if off:\n                field = '%s>>%s' % (field, off)\n            #print('JJJ', e.name, '{{'+field+'}}', typeBitWidth(e.datatype), e.shifted, e.assignOp, off)\n            fieldWidth = 32 - off     # number of valid data bits in source\n            fieldWidth += e.shifted   # number of valid data bits after shifting\n            if fieldWidth > typeBitWidth(e.datatype): # if num bits in type < num of valid bits\n                fieldWidth = typeBitWidth(e.datatype)\n            field = '((%s)&0x%xul)' % (field, ((1 << (fieldWidth - e.shifted))-1))\n            if e.shifted:\n                field = '((%s)(%s)<<%s)' % (typeCName(e.datatype),field, e.shifted)\n            if typeCName(e.datatype) == 'SpecialTypeForSendingFd':\n                if generatePacketOnly:\n                    print('generate_demarshall: when using \"generatePacketOnly\", fd items cannot be sent')\n                    sys.exit(-1)\n                statements.append('tempdata.%s.%s %s messageFd;'%(methodName, e.name, e.assignOp))\n            elif e.datatype.get('type') == 'Enum' and e.assignOp == '|=':\n                statements.append('tempdata.%s.%s = (%s)((int)tempdata.%s.%s | %s);'%(methodName, e.name, typeCName(e.datatype), methodName, e.name, field))\n            else:\n                statements.append('tempdata.%s.%s %s (%s)(%s);'%(methodName, e.name, e.assignOp, typeCName(e.datatype), field))\n            off = off+e.width-e.shifted\n        retList.append('\\n        '.join(statements))\n        itemIndex += 1\n    return retList\n\ndef formalParameters(params, insertPortal):\n    rc = [ 'const %s %s' % (typeCName(pitem['ptype']), pitem['pname']) for pitem in params]\n    if insertPortal:\n        rc.insert(0, ' struct PortalInternal *p')\n    return ', '.join(rc)\n\ntoJsonVerbose = False\ndef genToJson(var, name, prefix, ptype, appendto=False):\n    typename = ptype['name']\n    if toJsonVerbose: print('genToJson', name, typename, ptype, appendto)\n    if typename in ['Bit', 'Int', 'UInt', 'Bool']:\n        if typename == 'Int':\n            cast = 'Json::Int64'\n        else:\n            cast = 'Json::UInt64'\n        if appendto:\n            return ['%s.append((%s)%s);' % (var, cast, prefix)]\n        else:\n            return ['%s[\"%s\"] = (%s)%s;' % (var, name, cast, prefix)]\n\n    if 'type' not in ptype and typename != 'Vector':\n        typedef = globalv_globalvars[typename]\n        if toJsonVerbose: print('    dereferencing typedef', typedef)\n        if typedef['dtype'] == 'TypeDef':\n            tdtype = typedef['tdtype']\n            return genToJson(var, name, prefix, tdtype, appendto)\n\n    result = []\n    if typename == 'Vector':\n        ptype_type = 'Vector'\n    else:\n        ptype_type = ptype['type']\n\n    if ptype_type == 'Struct':\n        if toJsonVerbose: print('elements', ptype['elements'])\n        structvar = '_%sValue' % name\n        result.append('Json::Value %s;' % structvar)\n        result.append('%s[\"__type__\"]=\"%s\";' % (structvar, typename))\n        for elt in ptype['elements']:\n            result.extend(genToJson(structvar, elt['pname'], '%s.%s' % (name, elt['pname']), elt['ptype']))\n        expr = structvar\n    elif ptype_type == 'Enum':\n        expr = '(int)%s' % prefix\n    elif ptype_type == 'Vector':\n        vectorSize = typeNumeric(ptype['params'][0])\n        vectorType = ptype['params'][1]\n        vectorName = '%sVector' % cName(prefix)\n        result.append('Json::Value %s;' % vectorName)\n        for i in range(0,vectorSize):\n            result.extend(genToJson(vectorName,None,('%s[%d]' % (prefix,i)),vectorType,True))\n        expr = vectorName\n    else:\n        print('genToJson cannot handle', name, prefix, ptype)\n        expr = prefix\n    if appendto:\n        result.append('%s.append(%s);' % (var, expr))\n    else:\n        result.append('%s[\"%s\"] = %s;' % (var, name, expr))\n    if toJsonVerbose: print('result', result)\n    return result\n\ndef gatherMethodInfo(mname, params, itemname, classNameOrig, classVariant):\n    global fdName\n\n    className = cName(itemname)\n    methodName = cName(mname)\n    argAtoms = sum(map(functools.partial(collectMembers, ''), params), [])\n    argAtoms.reverse()\n    argWords  = accumWords([], 0, argAtoms)\n    argWords.reverse()\n    fdName = '-1'\n\n    if generatePacketOnly:\n        paramStructMarshallStr = '        (unsigned int)(%s),'\n        paramStructDemarshallStr = ''\n    else:\n        paramStructMarshallStr = 'p->transport->write(p, &temp_working_addr, %s);'\n        paramStructDemarshallStr = 'tmp = p->transport->read(p, &temp_working_addr);'\n\n    if argWords == []:\n        if generatePacketOnly:\n            paramStructMarshall = []\n        else:\n            paramStructMarshall = [paramStructMarshallStr % '0']\n        paramStructDemarshall = [paramStructDemarshallStr]\n    else:\n        paramStructMarshall = generate_marshall(paramStructMarshallStr, argWords)\n        paramStructDemarshall = generate_demarshall(paramStructDemarshallStr, methodName, argWords)\n\n    chname = '%s_%s' % (classNameOrig, methodName)\n    if verbose:\n        for pitem in params:\n            print('gatherMI', pitem)\n            break\n    if classVariant:\n        paramStructMarshall = []\n        itemNumber = 0\n        for pitem in params:\n            pname = pitem['pname']\n            ptype = pitem['ptype']\n            titems = genToJson('request', pname, pname, pitem['ptype'], True)\n            paramStructMarshall.extend(titems)\n            itemNumber = itemNumber + 1\n    paramStructDeclarations = [ '%s %s;' % (typeCName(pitem['ptype']), pitem['pname']) for pitem in params]\n    paramJsonDeclarations = [ '{\"%s\", Connectaloffsetof(%sData,%s), ITYPE_%s},' % \\\n        (pitem['pname'], chname, pitem['pname'], typeJson(pitem['ptype'])) for pitem in params]\n    if not params:\n        paramStructDeclarations = ['    int padding;\\n']\n        paramJsonDeclarations = ['']\n    respParams = ['tempdata.%s.%s' % (methodName, pitem['pname']) for pitem in params]\n    respParams.insert(0, 'p')\n    substs = {\n        'methodName': methodName,\n        'paramDeclarations': formalParameters(params, False),\n        'paramProxyDeclarations': formalParameters(params, True),\n        'paramStructDeclarations': '\\n    '.join(paramStructDeclarations),\n        'paramStructMarshall': '\\n    '.join(paramStructMarshall),\n        'paramJsonDeclarations': '\\n        '.join(paramJsonDeclarations),\n        'paramStructDemarshall': '\\n        '.join(paramStructDemarshall),\n        'paramNames': ', '.join(['msg->%s' % pitem['pname'] for pitem in params]),\n        'wordLen': len(argWords),\n        'wordLenP1': len(argWords) + 1,\n        'fdName': fdName,\n        'className': className,\n        'classNameOrig': classNameOrig,\n        'channelName': chname,\n        'channelNumber': 'CHAN_NUM_%s' % chname,\n        'name': mname,\n        'params': ', '.join(respParams),\n        }\n# 'className' : classNameOrig,\n    respCase = '\\n        ((%(classNameOrig)sCb *)p->cb)->%(name)s(%(params)s);'\n    if not classVariant:\n        respCase = handleMessagePrep + respCase\n        if not generatePacketOnly:\n            respCase = handleMessagePrepRecv + respCase\n    substs['responseCase'] = respCase % substs\n    return substs, len(argWords)\n\ndef emitMethodDeclaration(mname, params, f, className, methodIndex, returnType):\n    paramValues = [pitem['pname'] for pitem in params]\n    paramValues.insert(0, '&pint')\n    methodName = cName(mname)\n    indent(f, 4)\n    if className == '':\n        f.write('virtual void')\n    elif synchronousInvoke:\n        if returnType is not None:\n            f.write(typeCName(returnType))\n        else:\n            f.write('void')\n    else:\n        f.write('int')\n    f.write((' %s ( ' % methodName) + formalParameters(params, False) + ' ) ')\n    if className == '':\n        f.write('= 0;\\n')\n    elif synchronousInvoke:\n        f.write('{ cb->%s (' % methodName)\n        f.write(', '.join(paramValues) + ');')\n        if returnType is not None:\n            f.write(' return __internalWaitReturn(%d, %d);' % (methodIndex, typeBitWidth(returnType)))\n        f.write(' };\\n')\n    else:\n        f.write('{ return cb->%s (' % methodName)\n        f.write(', '.join(paramValues) + '); };\\n')\n\nwrapperStartTemplate = '''\n/************** Start of %(className)sWrapper CPP ***********/\n#include \"%(classNameOrig)s.h\"\nint %(classNameOrig)sdisconnect_cb (struct PortalInternal *p) {\n    (static_cast<%(classNameOrig)sWrapper *>(p->parent))->disconnect();\n    return 0;\n};\n'''\n\ndef generate_class(classNameOrig, classVariant, declList, generatedCFiles, create_cpp_file, generated_hpp, generated_cpp, direction):\n    global generatedVectors\n    className = classNameOrig + classVariant\n    classCName = cName(className)\n    generateProxy = True\n    generateWrapper = True\n    if direction == '0':\n        generateWrapper = False\n        print('JJJJJJJJJJJJJJJJJJJJJJJJJJJJJJJJJJJJ Proxy ', className)\n    if direction == '1':\n        generateProxy = False\n        print('JJJJJJJJJJJJJJJJJJJJJJJJJJJJJJJJJJJJ Wrapper ', className)\n    if classVariant == 'Json':\n        cppname = '%s.cpp' % className\n    else:\n        cppname = '%s.c' % className\n    hppname = '%s.h' % className\n    if cppname in generatedCFiles:\n        return\n    generatedCFiles.append(cppname)\n    cpp = create_cpp_file(cppname)\n    if classVariant:\n        cpp.write('#ifdef PORTAL_JSON\\n')\n        cpp.write('#include \"jsoncpp/json/json.h\"\\n')\n    maxSize = 0\n    reqChanNums = []\n    methodList = []\n    cnSubst = {'className': className, 'classNameOrig': classNameOrig}\n    if not classVariant:\n        hpp = create_cpp_file(hppname)\n        hpp.write('#ifndef _%(name)s_H_\\n#define _%(name)s_H_\\n' % {'name': className.upper()})\n        hpp.write('#include \"portal.h\"\\n')\n    if (not classVariant) and generateWrapper:\n        generated_cpp.write(wrapperStartTemplate % cnSubst)\n    for mitem in declList:\n        if verbose:\n            print('gcl/mitem', mitem)\n        substs, t = gatherMethodInfo(mitem['dname'], mitem['dparams'], className, classNameOrig, classVariant)\n        if t > maxSize:\n            maxSize = t\n        methodList.append(substs['methodName'])\n        reqChanNums.append(substs['channelNumber'])\n    methodJsonDeclarations = ['{\"%(methodName)s\", %(classNameOrig)s_%(methodName)sInfo},' % {'methodName': p, 'classNameOrig': classNameOrig} for p in methodList]\n    if generateProxy:\n        for mitem in declList:\n            substs, t = gatherMethodInfo(mitem['dname'], mitem['dparams'], className, classNameOrig, classVariant)\n            if generatePacketOnly:\n                substs['temp'] = 'temp_working_addr_start + 2'\n                substs['prolog'] = proxyMethodTemplatePrologPacket % substs\n                substs['paramStructMarshall'] = substs['paramStructMarshall'][0: len(substs['paramStructMarshall']) - 1] + \"};\"\n            else:\n                substs['temp'] = 'temp_working_addr_start'\n                substs['prolog'] = proxyMethodTemplateProlog % substs\n            if classVariant:\n                cpp.write((proxyMethodTemplateDecl + proxyJMethodTemplate) % substs)\n            else:\n                cpp.write((proxyMethodTemplateDecl + proxyMethodTemplate) % substs)\n                for t in generatedVectors:\n                    #'Vector'\n                    generated_hpp.write('\\ntypedef %s bsvvector_L%s_L%d[%d];' % (t[1], t[1], t[0], t[0]))\n                generatedVectors = []\n        for mitem in declList:\n            substs, t = gatherMethodInfo(mitem['dname'], mitem['dparams'], className, classNameOrig, classVariant)\n            generated_hpp.write((proxyMethodTemplateDecl % substs) + ';')\n        methodTable = ['%(className)s_%(methodName)s,' % {'methodName': p, 'className': className} for p in methodList]\n        cpp.write(proxyMethodTableDecl % {'className': className, 'classNameOrig': classNameOrig, 'methodTable': '\\n    '.join(['portal_disconnect,'] + methodTable)})\n    subs = {'className': classCName, 'maxSize': (maxSize+1) * sizeofUint32_t,\n        'reqInfo': '0x%x' % ((len(declList) << 16) + (maxSize+1) * sizeofUint32_t),\n        'classNameOrig': classNameOrig, 'tmpDecl': handleMessageTemplateTmpDecl}\n    if classVariant:\n        subs['handleStartup'] = 'Json::Value msg = Json::Value(connectalJsonReceive(p));' % subs\n    else:\n        if generatePacketOnly:\n            subs['handleStartup'] = 'volatile unsigned int* temp_working_addr = &p->map_base[1];'\n            subs['tmpDecl'] = ''\n        else:\n            subs['handleStartup'] = 'volatile unsigned int* temp_working_addr = p->transport->mapchannelInd(p, channel);'\n        generated_hpp.write('\\nenum { ' + ','.join(reqChanNums) + '};\\n' % subs)\n        generated_hpp.write('extern const uint32_t %(className)s_reqinfo;\\n' % subs)\n        cpp.write('\\nconst uint32_t %(className)s_reqinfo = %(reqInfo)s;\\n' % subs)\n        if generateProxy:\n            generateHandler = False\n            for mitem in declList:\n                if mitem.get('rtype') is not None:\n                    generateHandler = True\n            if generateHandler:\n                hpp.write('#include <fcntl.h>\\n')\n                hpp.write('#include <semaphore.h>\\n')\n                subs['handlerName'] = '__internalHandleMessage'\n                subs['initName'] = '__internalInit();'\n            else:\n                subs['handlerName'] = 'NULL'\n                subs['initName'] = ''\n            hpp.write(proxyClassPrefixTemplate % subs)\n            dindex = 0\n            for mitem in declList:\n                emitMethodDeclaration(mitem['dname'], mitem['dparams'], hpp, classCName, dindex, mitem.get('rtype'))\n                dindex = dindex + 1\n            if generateHandler:\n                hpp.write(syncProxyTemplate % subs)\n            hpp.write('};\\n')\n    if generateWrapper:\n        cpp.write('const char * %(className)s_methodSignatures()\\n{\\n' % subs)\n        signatures = dict([(mitem['dname'], ['long' for param in mitem['dparams']]) for mitem in declList])\n        cpp.write('    return %s;\\n}\\n' % json.dumps(json.dumps(signatures)))\n        cpp.write((handleMessageTemplateDecl % subs))\n        cpp.write(handleMessageTemplate1 % subs)\n        for mitem in declList:\n            substs, t = gatherMethodInfo(mitem['dname'], mitem['dparams'], className, classNameOrig, classVariant)\n            if not classVariant:\n                generated_hpp.write(messageStructTemplate % substs)\n            cpp.write(handleMessageCase % substs)\n        if not classVariant:\n            elemList = []\n            for mitem in declList:\n                substs, t = gatherMethodInfo(mitem['dname'], mitem['dparams'], className, className, classVariant)\n                elemList.append('%(channelName)sData %(methodName)s;' % substs)\n            generated_hpp.write(portalStructTemplate % {'className': classCName, 'messageStructDeclarations': '\\n    '.join(elemList)})\n        cpp.write(handleMessageTemplate2 % subs)\n        generated_hpp.write((handleMessageTemplateDecl % subs)+ ';\\n')\n    if (not classVariant) and generateWrapper:\n        hpp.write(wrapperClassPrefixTemplate % subs)\n        dindex = 0\n        for mitem in declList:\n            emitMethodDeclaration(mitem['dname'], mitem['dparams'], hpp, '', dindex, mitem.get('rtype'))\n            dindex = dindex + 1\n        hpp.write('};\\n')\n    cCNSubst = { 'classCName': classCName}\n    if not classVariant:\n        generated_hpp.write('typedef struct {\\n    PORTAL_DISCONNECT disconnect;\\n')\n        for mitem in declList:\n            if verbose:\n                for pitem in mitem['dparams']:\n                    print('generatecl/dparam', pitem)\n                    break\n            paramValues = ', '.join([pitem['pname'] for pitem in mitem['dparams']])\n            formalParamStr = formalParameters(mitem['dparams'], True)\n            methodName = cName(mitem['dname'])\n            generated_hpp.write(('    int (*%s) ( ' % methodName) + formalParamStr + ' );\\n')\n            if generateWrapper:\n                generated_cpp.write(('int %s%s_cb ( ' % (classCName, methodName)) + formalParamStr + ' ) {\\n')\n                indent(generated_cpp, 4)\n                generated_cpp.write(('(static_cast<%sWrapper *>(p->parent))->%s ( ' % (classCName, methodName)) + paramValues + ');\\n')\n                indent(generated_cpp, 4)\n                generated_cpp.write('return 0;\\n};\\n')\n        generated_hpp.write('} %(classCName)sCb;\\n' % cCNSubst)\n    if (not classVariant) and generateWrapper:\n        generated_cpp.write('%(classCName)sCb %(classCName)s_cbTable = {\\n    %(classCName)sdisconnect_cb,\\n' % cCNSubst)\n        for mitem in declList:\n            generated_cpp.write('    %s%s_cb,\\n' % (classCName, mitem['dname']))\n        generated_cpp.write('};\\n')\n    if not classVariant:\n        hpp.write('#endif // _%(name)s_H_\\n' % {'name': className.upper()})\n        hpp.close()\n    if generateProxy:\n        generated_hpp.write('extern %(classNameOrig)sCb %(className)sProxyReq;\\n' % subs)\n    if classVariant:\n        cpp.write('#endif /* PORTAL_JSON */\\n')\n    cpp.close()\n\ndef emitStructMember(item, f, indentation):\n    if verbose:\n        print('emitSM', item)\n    indent(f, indentation)\n    f.write('%s %s' % (typeCName(item['ptype']), item['pname']))\n    if hasBitWidth(item['ptype']):\n        f.write(' : %d' % typeBitWidth(item['ptype']))\n    f.write(';\\n')\n\ndef emitStruct(item, name, f, indentation):\n    indent(f, indentation)\n    if (indentation == 0):\n        f.write('typedef ')\n    f.write('struct %s {\\n' % name)\n    for e in item['elements']:\n        emitStructMember(e, f, indentation+4)\n    indent(f, indentation)\n    f.write('}')\n    if (indentation == 0):\n        f.write(' %s;' % name)\n    f.write('\\n')\n\ndef emitType(item, name, f, indentation):\n    indent(f, indentation)\n    tmp = typeCName(item)\n    if re.match('[0-9]+', tmp):\n        if True or verbose:\n            print('cppgen/emitType: INFO ignore numeric typedef for', tmp)\n        return\n    if not tmp or tmp[0] == '`' or tmp == 'Empty' or tmp[-2:] == '_P':\n        if True or verbose:\n            print('cppgen/emitType: INFO ignore typedef for', tmp)\n        return\n    if (indentation == 0):\n        f.write('typedef ')\n    f.write(tmp)\n    if (indentation == 0):\n        f.write(' %s;' % name)\n    f.write('\\n')\n\ndef convertVerilogNumber(n):\n    if \"'\" in n:\n        width, n = n.split(\"'\")\n        base = 10\n        if n[0] in ['h', 'd', 'o', 'b']:\n            if n[0] == 'h': base = 16\n            if n[0] == 'd': base = 10\n            if n[0] == 'o': base = 8\n            if n[0] == 'b': base = 2\n            n = n[1:]\n            n = hex(int(n, base))\n    return n\n\ndef emitEnum(item, name, f, indentation):\n    indent(f, indentation)\n    if (indentation == 0):\n        f.write('typedef ')\n    f.write('enum %s { ' % name)\n    indent(f, indentation)\n    for val in item['elements']:\n        temp = val[0]\n        if val[1] != None:\n            temp += '=' + convertVerilogNumber(val[1])\n        f.write(temp + ', ')\n    indent(f, indentation)\n    f.write(' }')\n    if (indentation == 0):\n        f.write(' %s;' % name)\n    f.write('\\n')\n\ndef emitCD(item, generated_hpp, indentation):\n    if verbose:\n        print('cppgen/emitCD:', item)\n    n = item['tname']\n    td = item['tdtype']\n    t = td.get('type')\n    if t == 'Enum':\n        emitEnum(td, n, generated_hpp, indentation)\n    elif t == 'Struct':\n        emitStruct(td, n, generated_hpp, indentation)\n    elif t == 'Type' or t == None:\n        emitType(td, n, generated_hpp, indentation)\n    else:\n        print('EMITCD', n, t, td)\n\ndef generate_cpp(project_dir, noisyFlag, jsondata):\n    global globalv_globalvars, verbose, bsvdefines\n    def create_cpp_file(name):\n        fname = os.path.join(project_dir, generatedSubdirectory, name)\n        f = util.createDirAndOpen(fname, 'w')\n        if verbose:\n            print(\"Writing file \",fname)\n        f.write('#include \"GeneratedTypes.h\"\\n')\n        return f\n\n    verbose = noisyFlag\n    bsvdefines = {}\n    for binding in jsondata['bsvdefines']:\n        if '=' in binding:\n            print('split', binding.split('='))\n            var,val = binding.split('=')\n            bsvdefines[var] = val\n        else:\n            bsvdefines[binding] = binding\n    generatedCFiles = []\n    globalv_globalvars = {}\n    hname = os.path.join(project_dir, generatedSubdirectory, 'GeneratedTypes.h')\n    generated_hpp = util.createDirAndOpen(hname, 'w')\n    generated_hpp.write('#ifndef __GENERATED_TYPES__\\n')\n    generated_hpp.write('#define __GENERATED_TYPES__\\n')\n    generated_hpp.write('#include \"portal.h\"\\n')\n    generated_hpp.write('#ifdef __cplusplus\\n')\n    generated_hpp.write('extern \"C\" {\\n')\n    generated_hpp.write('#endif\\n')\n    # global type declarations used by interface mthods\n    for v in jsondata['globaldecls']:\n        if v['dtype'] == 'TypeDef':\n            globalv_globalvars[v['tname']] = v\n            if v.get('tparams'):\n                print('Skipping C++ declaration for parameterized type', v['tname'])\n                continue\n            emitCD(v, generated_hpp, 0)\n    generated_hpp.write('\\n')\n    cppname = 'GeneratedCppCallbacks.cpp'\n    generated_cpp = create_cpp_file(cppname)\n    generatedCFiles.append(cppname)\n    generated_cpp.write('\\n#ifndef NO_CPP_PORTAL_CODE\\n')\n    for decl in jsondata['globaldecls']:\n        if decl['tname'] == 'IfcNames':\n            ifcnames = decl['tdtype']['elements']\n            for (ifcname,ifcvalue) in ifcnames:\n                generated_cpp.write('extern const uint32_t %s = %s;\\n' % (util.decapitalize(ifcname), ifcname))\n    for item in jsondata['interfaces']:\n        if verbose:\n            print('generateclass', item)\n        generate_class(item['cname'],     '', item['cdecls'], generatedCFiles, create_cpp_file, generated_hpp, generated_cpp, item.get('direction'))\n        if generateJson:\n            generate_class(item['cname'], 'Json', item['cdecls'], generatedCFiles, create_cpp_file, generated_hpp, generated_cpp, item.get('direction'))\n    generated_cpp.write('#endif //NO_CPP_PORTAL_CODE\\n')\n    generated_cpp.close()\n    generated_hpp.write('#ifdef __cplusplus\\n')\n    generated_hpp.write('}\\n')\n    generated_hpp.write('#endif\\n')\n    generated_hpp.write('#endif //__GENERATED_TYPES__\\n')\n    generated_hpp.close()\n    if not suppressGeneratedMakefile:\n        gen_makefile = util.createDirAndOpen(os.path.join(project_dir, generatedSubdirectory, 'Makefile.generated_files'), 'w')\n        gen_makefile.write('\\nGENERATED_CPP=' + ' '.join(generatedCFiles)+'\\n')\n        gen_makefile.close()\n    return generatedCFiles\n"
  },
  {
    "path": "scripts/deprecated/mkpcietop-partial-reconfiguration.tcl",
    "content": "\n# NOTE: typical usage would be \"vivado -mode tcl -source create_mkPcieTop_batch.tcl\" \n#\n# STEP#0: define output directory area.\n#\nset outputDir ./hw\nfile mkdir $outputDir\n\nif [file exists {board.tcl}] {\n    source {board.tcl}\n} else {\n    set boardname vc707\n    set partname {xc7vx485tffg1761-2}\n}\n\nif [file exists $outputDir/mkpcietop_static_routed.dcp] {\n    read_checkpoint $outputDir/mkpcietop_static_routed.dcp\n    lock_design -level routing\n} else {\n    read_checkpoint $outputDir/mkpcietop_post_synth.dcp\n    read_xdc constraints/$boardname.xdc\n}\n#start_gui\n\n#\n# STEP#3: run placement and logic optimization, report utilization and timing estimates, write checkpoint design\n#\n\nread_checkpoint -cell top_portalTop hw/portaltop_post_synth.dcp\nif [file exists $outputDir/mkpcietop_static_routed.dcp] {\n} else {\n    read_xdc $connectaldir/xilinx/constraints/$boardname-portal-pblock.xdc\n    set_property HD.RECONFIGURABLE TRUE [get_cells top_portalTop]\n    ## if the pblock is aligned to a reconfigurable frame, can use the following\n    #set_property RESET_AFTER_RECONFIG true [get_pblocks top_portalTop]\n}\n\nopt_design\n# power_opt_design\nplace_design\n#phys_opt_design\nwrite_checkpoint -force $outputDir/mkpcietop_post_place.dcp\nreport_timing_summary -file $outputDir/mkpcietop_post_place_timing_summary.rpt\n\n#\n# STEP#4: run router, report actual utilization and timing, write checkpoint design, run drc, write verilog and xdc out\n#\nroute_design\nwrite_checkpoint -force $outputDir/mkpcietop_post_route.dcp\nreport_timing_summary -file $outputDir/mkpcietop_post_route_timing_summary.rpt\nreport_timing -sort_by group -max_paths 100 -path_type summary -file $outputDir/mkpcietop_post_route_timing.rpt\nreport_clock_utilization -file $outputDir/mkpcietop_clock_util.rpt\nreport_utilization -file $outputDir/mkpcietop_post_route_util.rpt\n#report_power -file $outputDir/mkpcietop_post_route_power.rpt\nreport_drc -file $outputDir/mkpcietop_post_imp_drc.rpt\n#write_verilog -force $outputDir/mkpcietop_impl_netlist.v\nwrite_xdc -no_fixed_only -force $outputDir/mkpcietop_post_route.xdc\n#\n# STEP#5: generate a bitstream\n# \nwrite_bitstream -force -bin_file $outputDir/mkPcieTop.bit\nif [file exists $outputDir/mkpcietop_static_routed.dcp] {\n    pr_verify $outputDir/mkpcietop_static_routed.dcp $outputDir/mkpcietop_post_route.dcp\n} else {\n    update_design -cells [get_cells top_portalTop] -black_box\n    write_checkpoint -force $outputDir/mkpcietop_static_routed.dcp\n}\n\n"
  },
  {
    "path": "scripts/deprecated/mkpcietop-synth.tcl",
    "content": "\n# NOTE: typical usage would be \"vivado -mode tcl -source create_mkPcieTop_batch.tcl\" \n#\n# STEP#0: define output directory area.\n#\nif [file exists {board.tcl}] {\n    source {board.tcl}\n} else {\n    set boardname vc707\n    set partname {xc7vx485tffg1761-2}\n}\n\nset outputDir ./hw\nfile mkdir $outputDir\n#\n# STEP#1: setup design sources and constraints\n#\nread_verilog [ glob {verilog/top/*.v} ]\nread_verilog [ glob $connectaldir/xilinx/pcie_7x_v2_1/pcie_7x_0/source/*.v ]\nread_verilog [ glob $connectaldir/xilinx/7x/pcie/source/*.v ]\nread_xdc constraints/$boardname.xdc\n\n# STEP#2: run synthesis, report utilization and timing estimates, write checkpoint design\n#\nsynth_design -name mkPcieTop -top mkPcieTop -part $partname -flatten rebuilt\n\nwrite_checkpoint -force $outputDir/mkpcietop_post_synth\n"
  },
  {
    "path": "scripts/deprecated/portaltop-impl.tcl",
    "content": "\n# NOTE: typical usage would be \"vivado -mode tcl -source create_mkPcieTop_batch.tcl\" \n#\n# STEP#0: define output directory area.\n#\nif [file exists {board.tcl}] {\n    source {board.tcl}\n} else {\n    set boardname vc707\n    set partname {xc7vx485tffg1761-2}\n}\n\nset outputDir ./hw\nfile mkdir $outputDir\n#\n# STEP#1: setup design sources and constraints\n#\nread_verilog [ glob {verilog/lib/*.v} ]\nread_verilog [ glob {verilog/portal/*.v} ]\n\n# STEP#2: run synthesis, report utilization and timing estimates, write checkpoint design\n#\nsynth_design -mode out_of_context -name mkConnectalTopForPcie -top mkConnectalTopForPcie -part $partname -flatten rebuilt\n\nwrite_checkpoint -force $outputDir/portaltop_post_synth\n\nread_xdc $connectaldir/constraints/$boardname-portal-pblock.xdc\n\nplace_design\nroute_design\n\nwrite_checkpoint -force $outputDir/portaltop_post_route\n"
  },
  {
    "path": "scripts/deprecated/portaltop-synth.tcl",
    "content": "\n# NOTE: typical usage would be \"vivado -mode tcl -source create_mkPcieTop_batch.tcl\" \n#\n# STEP#0: define output directory area.\n#\nif [file exists {board.tcl}] {\n    source {board.tcl}\n} else {\n    set boardname vc707\n    set partname {xc7vx485tffg1761-2}\n}\n\nset outputDir ./hw\nfile mkdir $outputDir\n#\n# STEP#1: setup design sources and constraints\n#\nread_verilog [ glob {verilog/top/*.v} ]\nread_verilog [ glob {verilog/portal/*.v} ]\n\n# STEP#2: run synthesis, report utilization and timing estimates, write checkpoint design\n#\nsynth_design -mode out_of_context -name mkSynthesizeableConnectalTop -top mkSynthesizeableConnectalTop -part $partname -flatten rebuilt\n\nwrite_checkpoint -force $outputDir/portaltop_post_synth\n"
  },
  {
    "path": "scripts/discover_icmp.py",
    "content": "#!/usr/bin/env python3\n\n# Copyright (c) 2013 Quanta Research Cambridge, Inc.\n\n# Permission is hereby granted, free of charge, to any person\n# obtaining a copy of this software and associated documentation\n# files (the \"Software\"), to deal in the Software without\n# restriction, including without limitation the rights to use, copy,\n# modify, merge, publish, distribute, sublicense, and/or sell copies\n# of the Software, and to permit persons to whom the Software is\n# furnished to do so, subject to the following conditions:\n\n# The above copyright notice and this permission notice shall be\n# included in all copies or substantial portions of the Software.\n\n# THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n# EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n# MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n# BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n# ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n# CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n# SOFTWARE.\n\nfrom __future__ import print_function\n\nimport sys\nimport os\nimport socket\nimport struct\nimport select\nimport time\nimport threading\nimport argparse\nimport netifaces\n\nfrom adb import adb_commands\nfrom adb import common\n\ndef connect_with_adb(ipaddr):\n    connected = False\n    device_serial = '%s:5555' % (ipaddr)\n    print('connecting to android device %s' % device_serial)\n    while not connected:\n        try:\n            connection = adb_commands.AdbCommands.ConnectDevice(serial=device_serial)\n            connected = True\n        except socket.error:\n            pass\n    if 'hostname' in connection.Shell('ls /mnt/sdcard/'):\n        name = connection.Shell('cat /mnt/sdcard/hostname') \n        print(name)\n        return (ipaddr, name)\n    else:\n        print(\"/mnt/sdcard/hostname not found\")\n\n\ndef calcsum(source_string):\n    sum = 0\n    for i in range(0,len(source_string),2):\n        sum = sum + ord(source_string[i+1])*256 + ord(source_string[i])\n    sum = (sum >> 16) + (sum & 0xFFFF)\n    sum += (sum >> 16)\n    sum = (~sum) & 0xFFFF\n    return sum >> 8 | (sum << 8 & 0xFF00)\n\ndef receive_ping(timeout):\n    global recv_cnt\n    rem = timeout\n    while True:\n        a = time.time()\n        b = select.select([icmp_socket], [], [], rem)\n        c = (time.time() - a)\n        if b[0] == []:\n            return\n        rp, addr = icmp_socket.recvfrom(1024)\n        icmpHeader = rp[20:28]\n        type, code, checksum, packetID, sequence = struct.unpack(\n            \"bbHHh\", icmpHeader\n        )\n        if packetID == icmp_id:\n            recv_cnt = recv_cnt+1\n            # print \"recv_cnt: %x\" % recv_cnt\n            return addr\n        rem = rem - c\n        if rem <= 0:\n            return\n\n\ndef send_ping(dest_addr):\n    global send_cnt\n    send_cnt = send_cnt+1\n    dest_addr  =  socket.gethostbyname(dest_addr)\n    header = struct.pack(\"bbHHh\", 8, 0, 0, icmp_id, 1)\n    header = struct.pack(\"bbHHh\", 8, 0, socket.htons(calcsum(header)), icmp_id, 1)\n    try:\n        # print header.encode('hex')\n        # if (send_cnt > 1024):\n        #     time.sleep(0.1)\n        icmp_socket.sendto(header, (dest_addr, 1))\n    except socket.error as e:\n        print((dest_addr,e))\n        raise\n      \ndef check_adb_port(dest_addr):\n    sock = socket.socket(socket.AF_INET, socket.SOCK_STREAM)\n    sock.settimeout(0.1)\n    result = sock.connect_ex((dest_addr,5555))\n    return result == 0\n\ndef ping_request(dest_addr):\n    try:\n        send_ping(dest_addr)\n    except socket.gaierror as e:\n        print(\"%s failed. (socket error: '%s')\" % (dest_addr, e[1]))\n\ndef ping_response(timeout = 0.1):\n    try:\n        addr = receive_ping(timeout)\n    except socket.gaierror as e:\n        print(\"failed. (socket error: '%s')\" % e[1])\n    if (addr != None):\n        responders.append(addr[0])\n\ndef ip2int(addr):                                                               \n    return struct.unpack(\"!I\", socket.inet_aton(addr))[0]                       \n\ndef int2ip(addr):                                                               \n    return socket.inet_ntoa(struct.pack(\"!I\", addr))\n\ndef send_pings():\n    for i in range(low_addr,high_addr+1):\n        ping_request(int2ip(i))\n\ndef get_pings():\n    while (not stop):\n        ping_response(0)\n\ndef do_work(start, end):\n    global responders\n    global stop\n    global low_addr\n    global high_addr\n    global icmp_socket\n    global icmp_id\n    global zedboards\n    global send_cnt\n    global recv_cnt\n\n    send_cnt = 0\n    recv_cnt = 0\n    responders = []\n    stop = False\n    low_addr = start\n    high_addr = end\n    print(\"pinging \"+int2ip(low_addr)+\" to \"+int2ip(high_addr))\n\n    icmp = socket.getprotobyname(\"icmp\")\n    icmp_socket = socket.socket(socket.AF_INET, socket.SOCK_RAW, icmp)\n    icmp_socket.setsockopt(socket.SOL_SOCKET, socket.SO_SNDBUF, (start-end)*64)\n    icmp_id = os.getpid() & 0xFFFF\n\n    t0 = threading.Thread(target=send_pings)\n    t1 = threading.Thread(target=get_pings)\n    \n    t0.start()\n    t1.start()\n        \n    t0.join()\n    time.sleep(3)\n    stop = True\n    t1.join()\n\n    open = []\n    for r in responders:\n        if check_adb_port(r):\n            open.append(r)\n\n    for o in open:\n        zedboards.append(connect_with_adb(o))\n\n    icmp_socket.close()\n\nargparser = argparse.ArgumentParser(\"Discover Zedboards on a network\")\nargparser.add_argument('-n', '--network', help='xxx.xxx.xxx.xxx/N')\n\ndef detect_network():\n    global zedboards\n    zedboards = []\n    for ifc in netifaces.interfaces():\n        ifaddrs = netifaces.ifaddresses(ifc)\n        if netifaces.AF_INET in ifaddrs.keys():\n            af_inet = ifaddrs[netifaces.AF_INET]\n            for i in af_inet: \n                if i.get('addr') == '127.0.0.1':\n                    print('skipping localhost')\n                else:\n                    addr = ip2int(i.get('addr'))\n                    netmask = ip2int(i.get('netmask'))\n                    start = addr & netmask\n                    end = start + (netmask ^ 0xffffffff) \n                    print((int2ip(start), int2ip(end)))\n                    do_work(start, end) \n\nif __name__ ==  '__main__':\n    zedboards = []\n    options = argparser.parse_args()\n    if options.network == None:\n        detect_network()\n    else:\n        nw = options.network.split(\"/\")\n        start = ip2int(nw[0])\n        end = start+(1<<int(nw[1]))-2\n        do_work(start+1,end)\n"
  },
  {
    "path": "scripts/discover_tcp.py",
    "content": "#!/usr/bin/env python3\n\n# Copyright (c) 2013-2015 Quanta Research Cambridge, Inc.\n\n# Permission is hereby granted, free of charge, to any person\n# obtaining a copy of this software and associated documentation\n# files (the \"Software\"), to deal in the Software without\n# restriction, including without limitation the rights to use, copy,\n# modify, merge, publish, distribute, sublicense, and/or sell copies\n# of the Software, and to permit persons to whom the Software is\n# furnished to do so, subject to the following conditions:\n\n# The above copyright notice and this permission notice shall be\n# included in all copies or substantial portions of the Software.\n\n# THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n# EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n# MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n# BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n# ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n# CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n# SOFTWARE.\n\nfrom __future__ import print_function\n\nimport sys\nimport os\nimport socket\nimport struct\nimport select\nimport time\nimport threading\nimport argparse\nimport netifaces\n\nfrom adb import adb_commands\nfrom adb import common\n\ndeviceAddresses = []\n\ndef ip2int(addr):\n    return struct.unpack(\"!I\", socket.inet_aton(addr))[0]\n\ndef int2ip(addr):\n    return socket.inet_ntoa(struct.pack(\"!I\", addr))\n\ndef connect_with_adb(ipaddr,port):\n    global deviceAddresses\n    device_serial = '%s:%d' % (ipaddr,port)\n    cnt = 0\n    while cnt < 5:\n        try:\n            connection = adb_commands.AdbCommands.ConnectDevice(serial=device_serial)\n        except:\n            #print 'discover_tcp: connection error to', device_serial\n            pass\n        else:\n            if 'hostname.txt' in connection.Shell('ls /mnt/sdcard/'):\n                name = connection.Shell('cat /mnt/sdcard/hostname.txt').strip()\n                connection.Close()\n                print('discover_tcp: ', ipaddr, name)\n                deviceAddresses[ipaddr] = name\n                return\n            else:\n                print('discover_tcp: ', ipaddr, \" /mnt/sdcard/hostname.txt not found\")\n                deviceAddresses[ipaddr] =  ipaddr\n                return\n        cnt = cnt+1\n\ndef open_adb_socket(dest_addr,port):\n    sock = socket.socket(socket.AF_INET, socket.SOCK_STREAM)\n    sock.setblocking(0)\n    sock.connect_ex((dest_addr,port))\n    return sock\n\n# non-Darwin version\ndef do_work_poll(start, end, port, get_hostname):\n    print(\"scanning \"+int2ip(start)+\" to \"+int2ip(end))\n    connected = []\n    total = end-start\n\n    READ_ONLY = select.POLLIN | select.POLLPRI | select.POLLHUP | select.POLLERR\n    READ_WRITE = READ_ONLY | select.POLLOUT\n    poller = select.poll()\n\n    while (start <= end):\n        fd_map = {}\n        while (start <= end):\n            try:\n                s = open_adb_socket(int2ip(start),port)\n            except:\n                break\n            else:\n                fd_map[s.fileno()] = (start,s)\n                start = start+1\n                poller.register(s, READ_WRITE)\n        time.sleep(0.2)\n        events = poller.poll(0.1)\n        for fd,flag in events:\n            (addr,sock) = fd_map[fd]\n            if sock.getsockopt(socket.SOL_SOCKET, socket.SO_ERROR) == 0:\n                print('ADDCON', fd, int2ip(addr))\n                connected.append(int2ip(addr))\n        try:\n            fd_map_items = fd_map.iteritems()\n        except AttributeError:\n            fd_map_items = fd_map.items()  # Python 3 compatibility\n        for fd,t in fd_map_items:\n            poller.unregister(t[1])\n            t[1].close()\n        sys.stdout.write(\"\\r%d/%d\" % (total-(end-start),total))\n        sys.stdout.flush()\n    print()\n    if get_hostname:\n        for c in connected:\n            connect_with_adb(c,port)\n\n# Darwin version\ndef do_work_kqueue(start, end, port, get_hostname):\n    print(\"kqueue scanning \"+int2ip(start)+\" to \"+int2ip(end))\n    connected = []\n    total = end-start\n\n    while (start <= end):\n        kq = select.kqueue()\n        fd_map = {}\n        kevents = []\n        while (start <= end):\n            try:\n                s = open_adb_socket(int2ip(start),port)\n            except:\n                break\n            else:\n                fd_map[s.fileno()] = (start,s)\n                start = start+1\n                kevents.append(select.kevent(s,filter=select.KQ_FILTER_WRITE))\n        kq.control(kevents,0,0)\n        time.sleep(0.2)\n        for k in kq.control([],len(kevents),0.1):\n            w = fd_map[k.ident][1]\n            addr = fd_map[w.fileno()][0]\n            if w.getsockopt(socket.SOL_SOCKET, socket.SO_ERROR) == 0:\n                print('ADDCON2', k.ident, w.fileno(), int2ip(addr), fd_map[w.fileno()])\n                connected.append(int2ip(addr))\n        try:\n            fd_map_items = fd_map.iteritems()\n        except AttributeError:\n            fd_map_items = fd_map.items()  # Python 3 compatibility\n        for fd,t in fd_map_items:\n            t[1].close()\n        sys.stdout.write(\"\\r%d/%d\" % (total-(end-start),total))\n        sys.stdout.flush()\n    print()\n    if get_hostname:\n        for c in connected:\n            connect_with_adb(c,port)\n\n\nargparser = argparse.ArgumentParser(\"Discover Zedboards on a network\")\nargparser.add_argument('-n', '--network', help='xxx.xxx.xxx.xxx/N')\nargparser.add_argument('-p', '--port', default=5555, help='Port to probe')\nargparser.add_argument('-g', '--get_hostname', default=True, help='Get hostname with adb')\n\ndef do_work(start,end,port,get_hostname):\n    if sys.platform == 'darwin':\n        do_work_kqueue(start,end,port,get_hostname)\n    else:\n        do_work_poll(start,end,port,get_hostname)\n\ndef detect_network(network=None, port=5555, get_hostname=True):\n    global deviceAddresses\n    deviceAddresses = {}\n    if network:\n        nw = network.split(\"/\")\n        start = ip2int(nw[0])\n        if len(nw) != 2:\n            print('Usage: discover_tcp.py ipaddr/prefix_width')\n            sys.exit(-1)\n        end = start + (1 << (32-int(nw[1])) ) - 2\n        do_work(start+1,end,port,get_hostname)\n    else:\n        for ifc in netifaces.interfaces():\n            ifaddrs = netifaces.ifaddresses(ifc)\n            if netifaces.AF_INET in ifaddrs.keys():\n                af_inet = ifaddrs[netifaces.AF_INET]\n                for i in af_inet:\n                    if i.get('addr') == '127.0.0.1':\n                        print('skipping localhost')\n                    else:\n                        addr = ip2int(i.get('addr'))\n                        netmask = ip2int(i.get('netmask'))\n                        start = addr & netmask\n                        end = start + (netmask ^ 0xffffffff)\n                        start = start+1\n                        end = end-1\n                        print((int2ip(start), int2ip(end)))\n                        do_work(start, end,port,get_hostname)\n\nif __name__ ==  '__main__':\n    options = argparser.parse_args()\n    detect_network(options.network,options.port,options.get_hostname)\n"
  },
  {
    "path": "scripts/driver_signature.sed",
    "content": "s/  */ /g\ns/\\(.*\\) \\(.*\\)/{\"\\1\", \"\\2\"},/\ns/ \".*\\// \"/\n\n"
  },
  {
    "path": "scripts/extract-bvi-schedule.py",
    "content": "#!/usr/bin/env python3\n# Copyright (c) 2015 Connectal Project\n#\n# Permission is hereby granted, free of charge, to any person obtaining a\n# copy of this software and associated documentation files (the \"Software\"),\n# to deal in the Software without restriction, including without limitation\n# the rights to use, copy, modify, merge, publish, distribute, sublicense,\n# and/or sell copies of the Software, and to permit persons to whom the\n# Software is furnished to do so, subject to the following conditions:\n#\n# The above copyright notice and this permission notice shall be included\n# in all copies or substantial portions of the Software.\n#\n# THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n# OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n# DEALINGS IN THE SOFTWARE.\n#\n\nimport os, sys\nimport argparse\nimport re\nimport util\n\nargparser = argparse.ArgumentParser(\"Extract BVI schedule lines from bsc-generated verilog.\")\nargparser.add_argument('vfile', help='Verilog files to process', nargs='+')\nargparser.add_argument('-d', '--dir', help='Output directory', default='.')\n\nif __name__=='__main__':\n    options = argparser.parse_args()\n    for vfilename in options.vfile:\n        vf = open(vfilename, 'r')\n        basename = os.path.basename(vfilename)\n        (name, ext) = os.path.splitext(basename)\n        bvifname = os.path.join(options.dir, '%s.bvi' % name)\n        bvif = open(bvifname + '.new', 'w')\n        bvif.write('// BVI Schedule from %s\\n' % vfilename)\n        inschedule = False\n        for line in vf:\n            if re.match('^// BVI format method schedule info:', line):\n                inschedule = True\n            elif re.match('^// Ports:', line):\n                inschedule = False\n            elif inschedule:\n                # skip the comment characters\n                bvif.write(line[2:])\n            else:\n                pass\n            pass\n        bvif.close()\n        ## only update the file if it changed, to help out make\n        util.replaceIfChanged(bvifname, bvifname + '.new')\n        vf.close()\n"
  },
  {
    "path": "scripts/generate-constraints.py",
    "content": "#!/usr/bin/env python3\n# Copyright (c) 2013 Quanta Research Cambridge, Inc.\n#\n# Permission is hereby granted, free of charge, to any person\n# obtaining a copy of this software and associated documentation\n# files (the \"Software\"), to deal in the Software without\n# restriction, including without limitation the rights to use, copy,\n# modify, merge, publish, distribute, sublicense, and/or sell copies\n# of the Software, and to permit persons to whom the Software is\n# furnished to do so, subject to the following conditions:\n#\n# The above copyright notice and this permission notice shall be\n# included in all copies or substantial portions of the Software.\n#\n# THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n# EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n# MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n# BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n# ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n# CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n# SOFTWARE.\n\nfrom __future__ import print_function\nimport argparse, json, sys\nfrom collections import OrderedDict\nimport copy\n\nbindings = {\n    #'pins': 'pins',\n    'pin_name': 'pins' # legacy\n    }\nerrorDetected = False\n\ndef newArgparser():\n    argparser = argparse.ArgumentParser(\"Generate constraints file for board.\")\n    argparser.add_argument('--boardfile', help='Board description file (json)')\n    argparser.add_argument('--pinoutfile', default=[], help='Project description file (json)', action='append')\n    argparser.add_argument('-b', '--bind', default=[], help='Bind signal group to pin group', action='append')\n    argparser.add_argument('-o', '--output', default=None, help='Write output to file')\n    argparser.add_argument('-f', '--fpga', default=\"xilinx\", help='Target FPGA Vendor')\n    return argparser\n\n\nif __name__=='__main__':\n    argparser=newArgparser()\n    options = argparser.parse_args()\n\n    for binding in options.bind:\n        split = binding.split(':')\n        bindings[split[0]] = split[1]\n\n    boardInfo = json.loads(open(options.boardfile).read())\n    print(options.fpga)\n    if options.fpga == \"xilinx\":\n        template='''\\\n    set_property PACKAGE_PIN \"%(PACKAGE_PIN)s\" [get_ports \"%(name)s\"]\n    set_property PIO_DIRECTION \"%(PIO_DIRECTION)s\" [get_ports \"%(name)s\"]\n        '''\n        setPropertyTemplate='''\\\n        set_property %(prop)s \"%(val)s\" [get_ports \"%(name)s\"]\n        '''\n    elif options.fpga == \"altera\":\n        template='''\\\n    set_location_assignment \"%(LOC)s\" -to \"%(name)s\"\n    '''\n        setPropertyTemplate='''\\\n    set_instance_assignment -name %(prop)s \"%(val)s\" -to \"%(name)s\"\n    '''\n\n    out = sys.stdout\n    if options.output:\n        out = open(options.output, 'w')\n\n    for filename in options.pinoutfile:\n        print('generate-constraints: processing file \"' + filename + '\"')\n        pinstr = open(filename).read()\n        pinout = json.loads(pinstr, object_pairs_hook=OrderedDict)\n        for pin in pinout:\n            projectPinInfo = pinout[pin]\n            loc = 'TBD'\n            iodir = 'TBD'\n            used = []\n            boardPinInfo = {}\n            pinName = ''\n            #print('PPP', projectPinInfo)\n            for groupName in bindings:\n                if groupName in projectPinInfo:\n                    used.append(groupName)\n                    pinName = projectPinInfo[groupName]\n                    #print('LLL', groupName, pinName, bindings[groupName])\n                    boardPinInfo = boardInfo[bindings[groupName]]\n                    break\n            if pinName == '':\n                for prop in projectPinInfo:\n                    #print('JJJJ', prop)\n                    if boardInfo.get(prop):\n                        used.append(prop)\n                        pinName = projectPinInfo[prop]\n                        boardPinInfo = boardInfo[prop]\n                        #print('FFF', prop, pinName, boardPinInfo, pinName in boardPinInfo, boardPinInfo.get(pinName))\n                        break\n            if boardPinInfo == {}:\n                print('Missing group description for', pin, pinName, projectPinInfo, file=sys.stderr)\n                errorDetected = True\n            pinInfo = {}\n            if pinName in boardPinInfo:\n                pinInfo = copy.copy(boardPinInfo[pinName])\n            else:\n                print('Missing pin description for', pin, pinName, projectPinInfo, file=sys.stderr)\n                pinInfo['PACKAGE_PIN'] = 'fmc.%s' % (pinName)\n                errorDetected = True\n            pinInfo[u'name'] = pin\n            for prop in projectPinInfo:\n                if prop in projectPinInfo:\n                    pinInfo[prop] = projectPinInfo[prop]\n            try:\n                out.write(template % pinInfo)\n            except:\n                print('missing attributes for pin ', pinName)\n                print(template)\n                print(pinInfo)\n            for k in pinInfo:\n                if k in used+['name', 'PACKAGE_PIN', 'PIO_DIRECTION']: continue\n                out.write(setPropertyTemplate % {\n                        'name': pin,\n                        'prop': k,\n                        'val': pinInfo[k],\n                        })\n    if errorDetected:\n        sys.exit(-1);\n"
  },
  {
    "path": "scripts/globalv.py",
    "content": "#!/usr/bin/env python3\n\nglobaldecls = []\nglobalvars = {}\n\ndef add_new(decl):\n    if decl:\n        globaldecls.append(decl)\n        globalvars[decl.name] = decl\n"
  },
  {
    "path": "scripts/makefilegen.py",
    "content": "#!/usr/bin/env python3\n## Copyright (c) 2013-2014 Quanta Research Cambridge, Inc.\n\n## Permission is hereby granted, free of charge, to any person\n## obtaining a copy of this software and associated documentation\n## files (the \"Software\"), to deal in the Software without\n## restriction, including without limitation the rights to use, copy,\n## modify, merge, publish, distribute, sublicense, and/or sell copies\n## of the Software, and to permit persons to whom the Software is\n## furnished to do so, subject to the following conditions:\n\n## The above copyright notice and this permission notice shall be\n## included in all copies or substantial portions of the Software.\n\n## THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n## EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n## MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n## NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n## BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n## ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n## CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n## SOFTWARE.\n\nfrom __future__ import print_function\n\nimport os, sys, shutil, string\nimport argparse\nimport subprocess\nimport glob\nimport time\nimport syntax\nimport util\nimport boardinfo\nimport pprint\nimport json\nimport re\n\nsupported_os = ['android', 'ubuntu']\nsupported_stl = ['stlport_static', 'stlport_shared', 'gnustl_static', 'gnustl_shared', 'c++_static', 'c++_shared', 'gabi++_static', 'gabi++_shared']\n\nargparser = argparse.ArgumentParser(\"Generate C++/BSV/Xilinx stubs for an interface.\")\nargparser.add_argument('bsvfile', help='BSV files to parse', nargs='+')\nargparser.add_argument('-B', '--board', help='Target Board for compilation', default='zc702')\nargparser.add_argument('-O', '--OS', choices=supported_os, help='Target operating system', default=None)\nargparser.add_argument('-interfaces', '--interfaces', help='BSV interface', action='append', default=[])\nargparser.add_argument(      '--project-dir', help='xps project directory', default='./xpsproj')\nargparser.add_argument(      '--pinfo', help='Project description file (json)', default=None)\nargparser.add_argument(      '--protobuf', help='Interface description in protobuf', action='append', default=[])\nargparser.add_argument('-s', '--source', help='C++ source files', action='append', default=[])\nargparser.add_argument(      '--source2', help='C++ second program source files', action='append', default=[])\nargparser.add_argument(      '--cflags', help='CFLAGS', action='append', default=[])\nargparser.add_argument(      '--cxxflags', help='CXXFLAGS', action='append', default=[])\nargparser.add_argument(      '--pinout', help='project pinout file', action='append', default=[])\nargparser.add_argument(      '--shared', help='Make a shared library', action='store_true')\nargparser.add_argument(      '--nohardware', help='Do not generate hardware for the design', action='store_true')\nargparser.add_argument(      '--contentid', help='Specify 64-bit contentid for PCIe designs')\nargparser.add_argument('-I', '--cinclude', help='Specify C++ include directories', action='append', default=[])\nargparser.add_argument('-V', '--verilog', help='Additional verilog sources', action='append', default=[])\nargparser.add_argument(      '--modelsim', help='Additional modelsim sources', action='append', default=[])\nargparser.add_argument(      '--xci', help='Additional IP sources', action='append', default=[])\nargparser.add_argument(      '--qip', help='Additional QIP sources', action='append', default=[])\nargparser.add_argument(      '--qsf', help='Altera Quartus settings', action='append', default=[])\nargparser.add_argument(      '--chipscope', help='Onchip scope settings', action='append', default=[])\nargparser.add_argument('-C', '--constraint', help='Additional constraint files', action='append', default=[])\nargparser.add_argument(      '--implconstraint', help='Physical constraint files', action='append', default=[])\nargparser.add_argument(      '--unmanaged-implconstraint', help='Unmanaged physical constraint files', action='append', default=[])\nargparser.add_argument('-M', '--make', help='Run make on the specified targets', action='append', default=[])\nargparser.add_argument('-D', '--bsvdefine', help='BSV define', action='append', default=[])\nargparser.add_argument('-D2', '--bsvdefine2', help='BSV define2', action='append', default=[])\nargparser.add_argument(      '--pin-binding', help='pin binding translations for generate-constraints.py', action='append', default=[])\nargparser.add_argument('-l', '--clib', help='C++ libary', action='append', default=[])\nargparser.add_argument('-S', '--clibfiles', help='C++ libary file', action='append', default=[])\nargparser.add_argument('-L', '--clibdir', help='C++ libary', action='append', default=[])\nargparser.add_argument('-T', '--tcl', help='Vivado tcl script', action='append', default=[])\nargparser.add_argument('-m', '--bsimsource', help='Bsim C++ source files', action='append', default=[])\nargparser.add_argument(      '--verilatorflags', help='Options to verilator project flags', action='append', default=[])\nargparser.add_argument('-b', '--bscflags', help='Options to pass to the BSV compiler', action='append', default=[])\nargparser.add_argument('--xelabflags', help='Options to pass to the xelab compiler', action='append', default=[])\nargparser.add_argument('--xsimflags', help='Options to pass to the xsim simulator', action='append', default=[])\nargparser.add_argument('--awsflags', help='Options to pass to aws_build_dcp_from_cl.sh', action='append', default=[])\nargparser.add_argument('--ipdir', help='Directory in which to store generated IP')\nargparser.add_argument('-q', '--qtused', help='Qt used in simulator test application', action='store_true')\nargparser.add_argument('--stl', help='STL implementation to use for Android builds', default=None, choices=supported_stl)\nargparser.add_argument('--android-platform', help='Android platform to use for Android builds', type=int, default='16')\nargparser.add_argument('--android-toolchain', help='NDK toolchain to use for Android builds', default='4.9')\nargparser.add_argument('--floorplan', help='Floorplan XDC', default=None)\nargparser.add_argument('-P', '--partition-module', help='Modules to separately synthesize/place/route', action='append', default=[])\nargparser.add_argument('--cachedir', help='Cache directory for fpgamake to use', default=None)\nargparser.add_argument('--nocache', help='dont use buildcache with fpgamake', action='store_true')\nargparser.add_argument('-v', '--verbose', help='Display verbose information messages', action='store_true')\nargparser.add_argument(      '--dump_map', help='List of portals passed to pcieflat for PCIe trace debug info')\nargparser.add_argument('--nonstrict', help='If nonstrict, pass -Wall to gcc, otherwise -Werror', default=False, action='store_true')\nargparser.add_argument('--prtop', help='Filename of previously synthesized top level for partial reconfiguration', default=None)\nargparser.add_argument('--prvariant', help='name of a variant for partial reconfiguration', action='append', default=[])\nargparser.add_argument('--reconfig', help='partial reconfig module names', action='append', default=[])\nargparser.add_argument('--bsvpath', help='directories to add to bsc search path', action='append', default=[])\nargparser.add_argument('--mainclockperiod', help='Clock period of default clock, in nanoseconds', type=int, default=10)\nargparser.add_argument('--derivedclockperiod', help='Clock period of derivedClock, in nanoseconds', type=float, default=5.0)\nargparser.add_argument('--pcieclockperiod', help='Clock period of PCIE clock, in nanoseconds', type=int, default=None)\nargparser.add_argument('--run-args', help='Argument to pass via RUN_ARGS when running application', action='append', default=[])\n\nnoisyFlag=False\n\ntclReadVerilogTemplate='read_verilog [ glob %(verilog)s%(pattern)s ]'\ntclReadXciTemplate='''\ngenerate_target {Synthesis} [get_files %(xci)s]\nread_ip %(xci)s\n'''\n\ntclboardTemplate='''\nset partname {%(partname)s}\nset boardname {%(boardname)s}\n## for compatibility with older fpgamake. will be removed.\nset xbsvipdir {%(ipdir)s}\nset ipdir {%(ipdir)s}\nset connectaldir {%(connectaldir)s}\nset need_pcie {%(need_pcie)s}\nset connectal_dut {%(Dut)s}\n%(tcldefines)s\n'''\n\ntclzynqrewireclock = '''\nforeach {pat} {CLK_GATE_hdmi_clock_if CLK_*deleteme_unused_clock* CLK_GATE_*deleteme_unused_clock* RST_N_*deleteme_unused_reset*} {\n    foreach {net} [get_nets -quiet $pat] {\n        puts \"disconnecting net $net\"\n        disconnect_net -net $net -objects [get_pins -quiet -of_objects $net]\n    }\n}\n'''\n\nfpgamakeRuleTemplate='''\nexport VERILOG_PATH=verilog %(verilog)s $(BLUESPEC_VERILOG)\nMODELSIM_FILES= %(modelsim)s\nFPGAMAKE=$(CONNECTALDIR)/../fpgamake/fpgamake\nfpgamake.mk: $(VFILE) Makefile prepare_bin_target\n\t$(Q)if [ -f ../synth-ip.tcl ]; then vivado -mode batch -source ../synth-ip.tcl; fi\n\t$(Q)$(FPGAMAKE) $(FPGAMAKE_VERBOSE) -o fpgamake.mk --board=%(boardname)s --part=%(partname)s %(partitions)s --floorplan=%(floorplan)s %(xdc)s %(xci)s %(sourceTcl)s %(qsf)s %(chipscope)s -t $(MKTOP) %(FPGAMAKE_DEFINE)s %(cachedir)s -b hw/mkTop.bit %(prtop)s %(reconfig)s $(VERILOG_PATH)\n\nsynth.%%:fpgamake.mk\n\t$(MAKE) -f fpgamake.mk Synth/$*/$*-synth.dcp\n\nhw/mkTop.bit: prepare_bin_target %(genxdc_dep)s fpgamake.mk\n\t$(Q)mkdir -p hw\n\t$(Q)$(MAKE) -f fpgamake.mk\nifneq ($(XILINX),)\n\t$(Q)rsync -rav --include=\"*/\" --include=\"*.rpt\" --exclude=\"*\" Impl/ bin\nelse ifneq ($(ALTERA),)\n\t$(Q)cp -f $(MKTOP).sof bin\nendif\n\n%(genxdc)s\n\n'''\n\nmakefileTemplate='''\n\n##    run: run the program\n##         pass parameters to software via 'make RUN_ARGS= run'\nRUN_ARGS?=%(run_args)s\n\nexport DTOP=%(project_dir)s\nCONNECTALDIR=%(connectaldir)s\nBSVPATH = %(bsvpath)s\n\nBOARD=%(boardname)s\nPROJECTDIR=%(project_dir)s\nMKTOP=%(topbsvmod)s\nOS=%(OS)s\nTOOLCHAIN?=%(toolchain)s\nDUT=%(dut)s\n\nexport INTERFACES = %(interfaces)s\nBSVFILES = %(bsvfiles)s\nXCIFILES = %(xcifiles)s\n\nBSCFLAGS_PROJECT = %(bscflags)s\nSIM_CXX_PROJECT = %(bsimsource)s\nVERILATOR_PROJECT_ARGS = %(verilatorflags)s\nCFLAGS_PROJECT = %(cflags)s\nCXXFLAGS_PROJECT = %(cxxflags)s\nXELABFLAGS = %(xelabflags)s\nXSIMFLAGS  = %(xsimflags)s\nAWSFLAGS   = %(awsflags)s\nTOPBSVFILE = %(topbsvfile)s\nBSVDEFINES = %(bsvdefines)s\nQTUSED = %(qtused)s\nexport BSVDEFINES_LIST = %(bsvdefines_list)s\nexport DUT_NAME = %(Dut)s\n%(runsource2)s\n%(shared)s\n%(nohardware)s\n%(protobuf)s\n\n%(mdefines)s\n%(dump_map)s\n\ninclude $(CONNECTALDIR)/scripts/Makefile.connectal.build\n\n%(bitsmake)s\n'''\n\nvariantTemplate='''\nextratarget::\n\t$(MAKE) -C ../variant%(varname)s\n'''\n\nandroidmk_template='''\ninclude $(CLEAR_VARS)\nDTOP?=%(project_dir)s\nCONNECTALDIR?=%(connectaldir)s\nLOCAL_ARM_MODE := arm\ninclude $(CONNECTALDIR)/scripts/Makefile.connectal.application\nLOCAL_SRC_FILES := %(source)s $(PORTAL_SRC_FILES)\n\nLOCAL_PATH :=\nLOCAL_MODULE := %(android_local_module)s\nLOCAL_MODULE_TAGS := optional\nLOCAL_LDLIBS := -llog %(clibdirs)s %(clibs)s %(clibfiles)s\nLOCAL_CPPFLAGS := \"-march=armv7-a\"\nLOCAL_CFLAGS := %(cflags)s %(werr)s\nLOCAL_CXXFLAGS := %(cxxflags)s %(werr)s\nLOCAL_CFLAGS2 := $(cdefines2)s\n\ninclude $(%(android_build_type)s)\n'''\n\nandroidmk2_template='''\ninclude $(CLEAR_VARS)\nLOCAL_CPPFLAGS := \"-march=armv7-a\"\nLOCAL_CFLAGS := %(cflags)s %(werr)s\nLOCAL_CXXFLAGS := %(cxxflags)s %(werr)s\nLOCAL_SRC_FILES= %(source2)s\nLOCAL_MODULE := android.exe2\ninclude $(BUILD_EXECUTABLE)\n'''\n\ngenxdc_template='''\n\nPIN_BINDING=%(pin_binding)s\n\n%(genxdc_dep)s: %(pinout_dep_file)s $(CONNECTALDIR)/boardinfo/%(boardname)s.json\n\tmkdir -p %(project_dir)s/sources\n\t$(CONNECTALDIR)/scripts/generate-constraints.py -f %(fpga_vendor)s $(PIN_BINDING) -o %(genxdc_dep)s --boardfile $(CONNECTALDIR)/boardinfo/%(boardname)s.json %(pinout_file)s\n'''\n\nlinuxmakefile_template='''\nCONNECTALDIR?=%(connectaldir)s\nDTOP?=%(project_dir)s\n\nTOOLCHAIN?=%(toolchain)s\nifneq ($(TOOLCHAIN),)\nCC=$(TOOLCHAIN)gcc\nCXX=$(TOOLCHAIN)g++\nendif\nCFLAGS_COMMON = -O -g %(cflags)s -Wall %(werr)s %(cxxflags)s\nCFLAGS = $(CFLAGS_COMMON)\nCFLAGS2 = %(cdefines2)s\n\ninclude $(DTOP)/Makefile.autotop\ninclude $(CONNECTALDIR)/scripts/Makefile.connectal.application\nSOURCES = %(source)s $(PORTAL_SRC_FILES)\nSOURCES2 = %(source2)s $(PORTAL_SRC_FILES)\nXSOURCES = $(CONNECTALDIR)/cpp/XsimTop.cpp $(PORTAL_SRC_FILES)\nLDLIBS := %(clibdirs)s %(clibs)s %(clibfiles)s -lpthread\n\nubuntu.exe: $(SOURCES)\n\t$(Q)$(CXX) $(CFLAGS) -o ubuntu.exe $(SOURCES) $(LDLIBS)\n\t$(Q)[ ! -f ../bin/mkTop.bin.gz ] || $(TOOLCHAIN)objcopy --add-section fpgadata=../bin/mkTop.bin.gz ubuntu.exe\n\nconnectal.so: $(SOURCES)\n\t$(Q)$(CXX) -shared -fpic $(CFLAGS) -o connectal.so $(SOURCES) $(LDLIBS)\n\nubuntu.exe2: $(SOURCES2)\n\t$(Q)$(CXX) $(CFLAGS) $(CFLAGS2) -o ubuntu.exe2 $(SOURCES2) $(LDLIBS)\n\nxsim: $(XSOURCES)\n\t$(CXX) $(CFLAGS) -o xsim $(XSOURCES)\n'''\n\nif __name__=='__main__':\n    connectaldir = os.path.dirname((os.path.normpath(os.path.abspath(sys.argv[0])+'/../')))\n    options = argparser.parse_args()\n\n    boardname = options.board.lower()\n    option_info = boardinfo.attribute(boardname, 'options')\n\n    if options.pinfo:\n        pinstr = open(options.pinfo).read()\n        pinout = json.loads(pinstr)\n        for key in pinout['options']:\n            if isinstance(option_info[key], (list)):\n                option_info[key] += pinout['options'][key]\n            else:\n                option_info[key] = pinout['options'][key]\n\n    # parse additional options together with sys.argv\n    if option_info['CONNECTALFLAGS']:\n        options=argparser.parse_args(option_info['CONNECTALFLAGS'] + sys.argv[1:])\n\n    if options.verbose:\n        noisyFlag = True\n    if not options.xsimflags:\n        options.xsimflags = ['-R']\n\n    if noisyFlag:\n        pprint.pprint(option_info)\n    project_dir = os.path.abspath(os.path.expanduser(options.project_dir))\n\n    # remove intermediate files generated by parser generator\n    # this is necessary due to silent failures when syntax.py is compiled\n    os.path.exists('./out/parser.out')   and os.remove('./out/parser.out')\n    os.path.exists('./out/parsetab.pyc') and os.remove('./out/parsetab.pyc')\n    os.path.exists('./out/parsetab.py')  and os.remove('./out/parsetab.py')\n\n    bsvdefines = options.bsvdefine\n    bsvdefines.append('project_dir=$(DTOP)')\n    print(bsvdefines)\n    bsvdefines.append('MainClockPeriod=%d' % options.mainclockperiod)\n    bsvdefines.append('DerivedClockPeriod=%f' % options.derivedclockperiod)\n    if options.pcieclockperiod:\n        bsvdefines.append('PcieClockPeriod=%d' % options.pcieclockperiod)\n    print(bsvdefines)\n\n    rewireclockstring = tclzynqrewireclock\n    if 'rewireclockstring' in option_info and option_info['rewireclockstring'] != '':\n        rewireclockstring = option_info['rewireclockstring']\n\n    dutname = 'mk' + option_info['TOP']\n    topbsv = connectaldir + '/bsv/' + option_info['TOP'] + '.bsv'\n    if not os.path.isfile(topbsv):\n        topbsv = project_dir + \"/../\" + option_info['TOP'] + '.bsv'\n        if not os.path.isfile(topbsv):\n            print(\"ERROR: File %s not found\" % (option_info['TOP'] + '.bsv'))\n            sys.exit(1)\n\n    need_pcie = None\n    if 'need_pcie' in option_info:\n        need_pcie = option_info['need_pcie']\n\n    partname = option_info['partname']\n    if noisyFlag:\n        print('makefilegen: partname', partname)\n    if not 'os' in options:\n        options.os = option_info['os']\n\n    bdef = option_info.get('bsvdefines')\n    if bdef:\n        bsvdefines += bdef\n\n    # 'constraints' is a list of files\n    cstr = option_info.get('constraints')\n    if cstr:\n        ## preserve the order of items\n        options.constraint = [os.path.join(connectaldir, item) for item in cstr] + options.constraint\n    cstr = option_info.get('implconstraints')\n    if cstr:\n        ## preserve the order of items\n        options.implconstraint = [os.path.join(connectaldir, item) for item in cstr] + options.implconstraint\n    cstr = option_info.get('unmanaged-implconstraints')\n    if cstr:\n        ## preserve the order of items\n        options.unmanaged_implconstraint= [os.path.join(connectaldir, item) for item in cstr] + options.unmanaged_implconstraint\n\n    bsvdefines += ['BOARD_'+boardname]\n\n\n    # bsvdefines is a list of definitions, not a dictionary, so need to include the \"=1\"\n    if 'ALTERA=1' in bsvdefines:\n        fpga_vendor = 'altera'\n        suffix = 'sdc'\n    elif 'XILINX=1' in bsvdefines:\n        fpga_vendor = 'xilinx'\n        suffix = 'xdc'\n        options.tcl.append(os.path.join(connectaldir, 'constraints', 'xilinx', 'cdc.tcl'))\n    else:\n        fpga_vendor = None\n        suffix = None\n\n    print('fpga_vendor', fpga_vendor)\n    if fpga_vendor:\n        options.verilog.append(os.path.join(connectaldir, 'verilog', fpga_vendor))\n    options.verilog.append(os.path.join(connectaldir, 'verilog'))\n\n    if noisyFlag:\n        pprint.pprint(options.__dict__)\n\n    tclboardname = os.path.join(project_dir, 'board.tcl')\n    tclsynthname = os.path.join(project_dir, '%s-synth.tcl' % dutname.lower())\n    makename = os.path.join(project_dir, 'Makefile')\n\n    androidmkname = os.path.join(project_dir, 'jni', 'Android.mk')\n    linuxmkname = os.path.join(project_dir, 'jni', 'Ubuntu.mk')\n\n    if noisyFlag:\n        print('Writing Android.mk', androidmkname)\n    substs = {\n        #android\n        'project_dir': project_dir,\n        #ubuntu\n        'sourceincludes': ' '.join(['-I%s' % os.path.dirname(os.path.abspath(sf)) for sf in options.source]) if options.source else '',\n        #common\n        'source': ' '.join([os.path.abspath(sf) for sf in options.source]) if options.source else '',\n        'source2': ' '.join([os.path.abspath(sf) for sf in options.source2]) if options.source2 else '',\n        'connectaldir': connectaldir,\n        'clibs': ' '.join(['-l%s' % l for l in options.clib]),\n        'clibfiles': ' '.join(['%s' % l for l in options.clibfiles]),\n        'clibdirs': ' '.join([ '-L%s' % os.path.abspath(l) for l in options.clibdir ]),\n        'cdefines': '', #' '.join([ '-D%s' % d for d in bsvdefines ]),\n        'cdefines2': '', #' '.join([ '-D%s' % d for d in options.bsvdefine2 ]),\n        'cincludes': ' '.join([ '-I%s' % os.path.abspath(i) for i in options.cinclude ]),\n        'werr': '-Werror' if not options.nonstrict else '-Wall'\n    }\n    includelist = ['-I$(DTOP)/jni', '-I$(CONNECTALDIR)', \\\n                   '-I$(CONNECTALDIR)/cpp', '-I$(CONNECTALDIR)/lib/cpp', \\\n                   #'%(sourceincludes)s',\n                   '%(cincludes)s']\n    substs['toolchain'] = option_info['toolchain'] if 'toolchain' in option_info else ''\n    substs['cflags'] = util.escapequotes('%s %s' % ((' '.join(includelist) % substs), ' '.join(options.cflags)))\n    substs['cxxflags'] = util.escapequotes('%s %s' % ((' '.join(includelist) % substs), ' '.join(options.cxxflags)))\n    substs['android_build_type'] = 'BUILD_SHARED_LIBRARY' if options.shared else 'BUILD_EXECUTABLE'\n    substs['android_local_module'] = 'connectal' if options.shared else 'android.exe'\n    f = util.createDirAndOpen(androidmkname, 'w')\n    f.write(androidmk_template % substs)\n    if options.source2:\n        f.write(androidmk2_template % substs)\n    f.close()\n    f = util.createDirAndOpen(linuxmkname, 'w')\n    f.write(linuxmakefile_template % substs)\n    f.close()\n    if options.stl or options.android_platform or options.android_toolchain:\n            f = util.createDirAndOpen(os.path.join(project_dir, 'jni', 'Application.mk'), 'w')\n            if options.stl:\n                f.write('APP_STL                 := %s\\n' % options.stl)\n            if options.android_platform:\n                f.write('APP_PLATFORM             := android-%s\\n' % options.android_platform)\n            if options.android_toolchain:\n                f.write('NDK_TOOLCHAIN_VERSION    := %s\\n' % options.android_toolchain)\n            f.close()\n\n    tclsubsts = {'dut': dutname.lower(),\n                 'Dut': dutname,\n                 'rewire_clock': rewireclockstring,\n                 'project_dir': project_dir,\n                 'partname': partname,\n                 'boardname': boardname,\n                 'connectaldir': connectaldir,\n                 'read_verilog': '\\n'.join([tclReadVerilogTemplate\n                                            % { 'verilog': os.path.abspath(f),\n                                                'pattern': '/*.*v' if os.path.isdir(f) else ''} for f in options.verilog]),\n                 'read_xci': '\\n'.join([tclReadXciTemplate\n                                        % { 'xci': f } for f in options.xci]),\n                 'need_pcie': need_pcie,\n                 'tcldefines': '\\n'.join(['set %s {%s}' % (var,val) for (var,val) in map(util.splitBinding, bsvdefines)]),\n                 'ipdir': os.path.abspath(options.ipdir) if options.ipdir else connectaldir\n                 }\n    tcl = util.createDirAndOpen(tclboardname, 'w')\n    tcl.write(tclboardTemplate % tclsubsts)\n    tcl.close()\n\n    if noisyFlag:\n        print('Writing Makefile', makename)\n    make = util.createDirAndOpen(makename + '.new', 'w')\n\n    genxdc_dep = ''\n    if options.pinout:\n        genxdc_dep = '%s/sources/pinout-%s.xdc' % (project_dir,boardname)\n        options.constraint.append(genxdc_dep)\n        options.implconstraint.append(genxdc_dep)\n    else:\n       options.pinout = []\n\n    # ignore partition_module until altera flow support generate separate netlist.\n    if (fpga_vendor == 'altera'):\n        options.partition_module = []\n\n    if options.nocache:\n        cachearg = '--cachedir=\"\"'\n    else:\n        cachearg = '--cachedir=%s' % os.path.abspath(options.cachedir) if options.cachedir else ''\n    substs = {'partitions': ' '.join(['-s %s' % p for p in options.partition_module]),\n                                         'boardname': boardname,\n                                         'partname': partname,\n                     'fpga_vendor': fpga_vendor,\n                                         'project_dir' : project_dir,\n                                         'pinout_file' : ' '.join([('--pinoutfile ' + os.path.abspath(p)) for p in options.pinout]),\n                                         'pinout_dep_file' : ' '.join([os.path.abspath(p) for p in options.pinout]),\n                                         'genxdc_dep' : genxdc_dep,\n                                         'floorplan': os.path.abspath(options.floorplan) if options.floorplan else '',\n                                         'xdc': ' '.join(['--constraint=%s' % os.path.abspath(xdc) for xdc in options.constraint]\n                                                         + ['--implconstraint=%s' % os.path.abspath(xdc) for xdc in options.implconstraint]\n                                                         + ['--unmanaged-implconstraint=%s' % os.path.abspath(xdc) for xdc in options.unmanaged_implconstraint]),\n                                         'xci': ' '.join(['--xci=%s' % os.path.abspath(xci) for xci in options.xci]),\n                                         'qsf': ' '.join(['--qsf=%s' % os.path.abspath(qsf) for qsf in options.qsf]),\n                                         'chipscope': ' '.join(['--chipscope=%s' % os.path.abspath(chipscope) for chipscope in options.chipscope]),\n                                         'sourceTcl': ' '.join(['--tcl=%s' % os.path.abspath(tcl) for tcl in options.tcl]),\n                                         'verilog': ' '.join([os.path.abspath(f) for f in options.verilog]),\n                                         'modelsim': ' '.join([os.path.abspath(f) for f in options.modelsim]),\n                                         'cachedir': cachearg,\n                                         'pin_binding' : ' '.join(['-b %s' % s for s in options.pin_binding]),\n                                         'reconfig' : ' '.join(['--reconfig=%s' % rname for rname in options.reconfig]),\n                                         'prtop' : ('--prtop=%s' % options.prtop) if options.prtop else ''\n                                         }\n    substs['genxdc'] = (genxdc_template % substs) if options.pinout else ''\n    substs['FPGAMAKE_DEFINE'] = '-D BSV_POSITIVE_RESET' if 'BSV_POSITIVE_RESET' in options.bsvdefine else ''\n    bitsmake=fpgamakeRuleTemplate % substs\n\n    ## make list of unique bsvpaths, in the order they were given\n    unique_bsvpaths = []\n    for l in [[os.path.dirname(os.path.abspath(bsvfile)) for bsvfile in (options.bsvfile + [project_dir])],\n              [os.path.abspath(bsvpath) for bsvpath in options.bsvpath],\n              [os.path.join(connectaldir, 'bsv')],\n              [os.path.join(connectaldir, 'lib/bsv')],\n              [os.path.join(connectaldir, 'generated/xilinx')],\n              [os.path.join(connectaldir, 'generated/altera')]]:\n        for p in l:\n            if p not in unique_bsvpaths:\n                unique_bsvpaths.append(p)\n\n    if options.protobuf:\n        protolist = [os.path.abspath(fn) for fn in options.protobuf]\n    make.write(makefileTemplate % {'connectaldir': connectaldir,\n                                   'bsvpath': ':'.join(unique_bsvpaths),\n                                   'bsvdefines': util.foldl((lambda e,a: e+' -D '+a), '', bsvdefines),\n                                   'boardname': boardname,\n                                   'OS': options.os,\n                                   'qtused': 'cd jni; qmake ../..; make' if options.qtused else '',\n                                   'interfaces': ' '.join(options.interfaces),\n                                   'bsvfiles': ' '.join([ os.path.abspath(bsvfile) for bsvfile in options.bsvfile]),\n                                   'xcifiles': ' '.join([ os.path.abspath(xci) for xci in options.xci]),\n                                   'bsimsource': ' '.join([os.path.abspath(bsimsource) for bsimsource in options.bsimsource]) if options.bsimsource else '',\n                                   'includepath': ' '.join(['-I%s' % os.path.dirname(os.path.abspath(source)) for source in options.source]) if options.source else '',\n                                   'runsource2': 'RUNSOURCE2=1' if options.source2 else '',\n                                   'project_dir': project_dir,\n                                   'topbsvfile' : topbsv,\n                                   'topbsvmod'  : dutname,\n                                   'dut' : dutname.lower(),\n                                   'Dut': dutname,\n                                   'clibs': ' '.join(['-l%s' % l for l in options.clib]),\n                                   'cdefines': '', #' '.join([ '-D%s' % d for d in bsvdefines ]),\n                                   'mdefines': '\\n'.join(['%s=%s' % (var,val or var) for (var,val) in map(util.splitBinding, bsvdefines)]),\n                                   'dump_map': ('export PORTAL_DUMP_MAP=' + options.dump_map + '\\n') if options.dump_map else '',\n                                   'bscflags': ' '.join(options.bscflags),\n                                   'xelabflags': ' '.join(options.xelabflags),\n                                   'xsimflags': ' '.join(options.xsimflags),\n                                   'awsflags': ' '.join(options.awsflags),\n                                   'verilatorflags': ' ' .join(options.verilatorflags),\n                                   'cflags': ' ' .join(options.cflags),\n                                   'cxxflags': ' ' .join(options.cxxflags),\n                                   'bsvdefines_list': ' '.join(bsvdefines),\n                                   'shared': 'CONNECTAL_SHARED=1' if options.shared else '',\n                                   'nohardware': 'CONNECTAL_NOHARDWARE=1' if options.nohardware else '',\n                                   'protobuf': ('export PROTODEBUG=%s' % ' '.join(protolist)) if options.protobuf else '',\n                                   'bitsmake': bitsmake,\n                                   'run_args': ' '.join(options.run_args),\n                                   'toolchain': option_info['toolchain'] if 'toolchain' in option_info else ''\n                                   })\n    if not options.prtop:\n        for name in options.prvariant:\n            make.write(variantTemplate % {'varname': name})\n    make.close()\n    util.replaceIfChanged(makename, makename + '.new')\n\n    configbsvname = os.path.join(project_dir, 'generatedbsv', 'ConnectalProjectConfig.bsv')\n    configbsv = util.createDirAndOpen(configbsvname + '.new', 'w')\n    for (var, val) in map(util.splitBinding, bsvdefines):\n        configbsv.write('`define %(var)s %(val)s\\n' % { 'var': var, 'val': val })\n    configbsv.close()\n    util.replaceIfChanged(configbsvname, configbsvname + '.new')\n\n    confighname = os.path.join(project_dir, 'jni', 'ConnectalProjectConfig.h')\n    configh = util.createDirAndOpen(confighname + '.new', 'w')\n    configh.write('#ifndef _ConnectalProjectConfig_h\\n')\n    configh.write('#define _ConnectalProjectConfig_h\\n')\n    configh.write('\\n')\n    for (var, val) in map(util.splitBinding, bsvdefines):\n        if re.match(\"^[0-9]+(.[0-9]*)?$\", val):\n            configh.write('#define %(var)s %(val)s\\n' % { 'var': var, 'val': val })\n        else:\n            configh.write('#define %(var)s \"%(val)s\"\\n' % { 'var': var, 'val': val })\n    configh.write('\\n')\n    configh.write('#endif // _ConnectalProjectConfig_h\\n')\n    configh.close()\n    util.replaceIfChanged(confighname, confighname + '.new')\n\n    if options.make:\n        os.chdir(project_dir)\n        os.putenv('PWD', subprocess.check_output(['pwd'])[0:-1])\n        subprocess.call(['make'] + options.make)\n"
  },
  {
    "path": "scripts/packagesource.py",
    "content": "#!/usr/bin/env python3\n\nfrom __future__ import print_function\n\nimport os, sys\nimport glob\nimport argparse\nimport re\n\nimport bsvdependencies\n\nfrom shutil import copyfile\nfrom sets import Set\n\ndefault_bluespecdir=None\nif 'BLUESPECDIR' in os.environ:\n    default_bluespecdir = os.environ['BLUESPECDIR']\n\nargparser = argparse.ArgumentParser(\"Quick and dirty packager for BSV projects. Copy all the bsv dependencies required to compile the BSVFILE from all the directory in the BSVPATH, and paste them in the directory OUTPUT.\")\n\nargparser.add_argument('bsvfile', help='BSV files to process', nargs='*')\nargparser.add_argument('-D', '--bsvdefine', default=[], help='BSV define for preprocessing', action='append')\nargparser.add_argument('--bsvpath', default=[], help='directories to add to bsc search path', action='append')\nargparser.add_argument('--bluespecdir', default=default_bluespecdir, help='BSC bluespec dir')\nargparser.add_argument('-o', '--output', help='Output directory', default='./bsvFiles/')\n\ndef find(name, path):\n    for root, dirs, files in os.walk(path):\n        if name in files:\n            return os.path.join(root, name)\n\ndef getBsvPackages(bluespecdir):\n    \"\"\"BLUESPECDIR is expected to be the path to the bluespec distribution.\n    The function GETBSVPACKAGES returns a list of all\n    the packages in the prelude library of this distribution.\n    \"\"\"\n    pkgs = []\n    for f in glob.glob('%s/Prelude/*.bo' % bluespecdir) + glob.glob('%s/Libraries/*.bo' % bluespecdir):\n        pkgs.append(os.path.splitext(os.path.basename(f))[0])\n    return pkgs\n\n\n\ndef expandPackages(bsvfile):\n    newpackage, bsvpat = bsvdependencies.bsvDependencies(bsvfile,\n                                                         False,\n                                                         default_bluespecdir,\n                                                         options.bsvpath,\n                                                         [])\n    setPkg = Set(bsvfile)\n    for _,pkgs,_,_ in newpackage:\n        for pkg in pkgs:\n            for pth in options.bsvpath:\n                pkgFile = find(\"%s.bsv\" % pkg, pth)\n                if pkgFile != None:\n                    subSet = expandPackages([pkgFile])\n                    setPkg = subSet | setPkg\n    for _,_,includes,_ in newpackage:\n        setPkg = Set(includes) | setPkg\n    return setPkg\n\nif __name__=='__main__':\n    options = argparser.parse_args()\n    pkgPrelude = getBsvPackages(options.bluespecdir)\n    filesProject = expandPackages(options.bsvfile)\n    if not os.path.exists(options.output):\n        os.makedirs(options.output)\n    print(filesProject)\n    for file in filesProject:\n        copyfile(file, os.path.join(options.output,os.path.basename(file)))\n\n\n\n"
  },
  {
    "path": "scripts/parse_qsf.py",
    "content": "#!/usr/bin/env python3\n\nfrom __future__ import print_function\nimport sys\nimport json\nimport re\nimport argparse\n\nargparser = argparse.ArgumentParser(\"Parse QSF to Json\")\nargparser.add_argument('-q', '--qsf', help='Input QSF File')\nargparser.add_argument('-g', '--group', default=[], help='Signal Group', action='append')\nargparser.add_argument('-o', '--output', default=None, help='Write output to file')\n\noptions = argparser.parse_args()\nqsffile = options.qsf\n\ngroups = {}\nfor group in options.group:\n    split = group.split(':')\n    groups[split[0]] = split[1]\n\nqsflines = open(qsffile).readlines()\n\nout = sys.stdout\nif options.output:\n    out = open(options.output, 'w')\n\ngroup=''\npins={}\nfor line in qsflines:\n    # Skip comments\n    m = re.search(\"#*=\", line)\n    if m:\n        continue\n\n    # Find group name\n    m = re.search('#', line)\n    if m:\n        group = line.replace('#','').strip()\n        groups.update({group:{}})\n\n    # Find pin name\n    m = re.search('set_instance_assignment', line)\n    if m:\n        n = re.search('-to', line)\n        if n:\n            r = line.split('-to')[0].strip()\n            name = line.split('-to')[1].strip()\n\n            io = re.search('IO_STANDARD', r)\n            if io:\n                standard = r.split('IO_STANDARD')[1].strip().replace(\"\\\"\", '')\n                if name in pins:\n                    pins[name].update({'IO_STANDARD': standard})\n                    pins[name].update({'GROUP': group})\n                else:\n                    pins.update({name: {'IO_STANDARD': standard}})\n                    pins[name].update({'GROUP': group})\n\n    # Find pin location\n    m = re.search('set_location_assignment', line)\n    if m:\n        n = re.search('-to', line)\n        if n:\n            r = line.split('-to')[0].strip()\n            name = line.split('-to')[1].strip()\n\n            loc = re.search('PIN_[A-Z]+[0-9]+', r)\n            if loc:\n                location = loc.group(0)\n                if name in pins:\n                    pins[name].update({'LOC': location})\n                else:\n                    pins.update({name:{'LOC': location}})\n\nfor n in pins:\n    groups[pins[n]['GROUP']].update({n: {'IOSTANDARD': pins[n]['IO_STANDARD'], 'LOC': pins[n]['LOC']}})\n\nprint(json.dumps(groups, indent=4, sort_keys=True), file=out)\n"
  },
  {
    "path": "scripts/parse_xdc.py",
    "content": "#!/usr/bin/env python3\n\n# parse xdc pin assignment to json\n\nfrom __future__ import print_function\nimport sys\nimport json\nimport re\nimport argparse\n\nargparser = argparse.ArgumentParser(\"Parse XDC to Json\")\nargparser.add_argument('-x', '--xdc', help='Input XDC File')\nargparser.add_argument('-g', '--group', default=[], help='Signal Group', action='append')\nargparser.add_argument('-o', '--output', default=None, help='Write output to file')\n\noptions = argparser.parse_args()\nxdcfile = options.xdc\n\ngroups = {}\nfor group in options.group:\n    split = group.split(':')\n    groups[split[0]] = split[1]\n\nxdclines = open(xdcfile).readlines()\n\nout = sys.stdout\nif options.output:\n    out = open(options.output, 'w')\n\ngroup=''\npins={}\nfor line in xdclines:\n    # Find group name\n    m = re.search('^#', line)\n    if m:\n        group = line.replace('#','').strip()\n        groups.update({group:{}})\n\n    # Find pin name and location\n    m = re.search('^set_property', line)\n    if m:\n        n = re.search('-dict', line)\n        if n:\n            r = line.split('-dict')[0].strip()\n            line = line.split('-dict')[1].strip()\n            name = line.split('get_ports')[1].split('{')[1].split('}')[0].strip()\n\n            loc = re.search('PACKAGE_PIN', line)\n            if loc:\n                pin = line.split('PACKAGE_PIN')[1].split()[0].strip().replace(\"\\\"\", '')\n                if name in pins:\n                    pins[name].update({'LOC': pin})\n                    pins[name].update({'GROUP': group})\n                else:\n                    pins.update({name:{'LOC': pin}})\n                    pins[name].update({'GROUP': group})\n\n            io = re.search('IOSTANDARD', line)\n            if io:\n                standard = line.split('IOSTANDARD')[1].split()[0].strip().replace(\"\\\"\", '')\n                if standard in pins:\n                    pins[name].update({'IOSTANDARD': standard})\n                else:\n                    pins[name].update({'IOSTANDARD': standard})\n\nfor n in pins:\n    groups[pins[n]['GROUP']].update({n: {'IOSTANDARD': pins[n]['IOSTANDARD'], 'LOC': pins[n]['LOC']}})\n\nprint(json.dumps(groups, indent=4, sort_keys=True), file=out)\n"
  },
  {
    "path": "scripts/portal.py",
    "content": "#!/usr/bin/env python3\n# Copyright (c) 2016 Connectal Project\n#\n# Permission is hereby granted, free of charge, to any person obtaining a\n# copy of this software and associated documentation files (the \"Software\"),\n# to deal in the Software without restriction, including without limitation\n# the rights to use, copy, modify, merge, publish, distribute, sublicense,\n# and/or sell copies of the Software, and to permit persons to whom the\n# Software is furnished to do so, subject to the following conditions:\n#\n# The above copyright notice and this permission notice shall be included\n# in all copies or substantial portions of the Software.\n#\n# THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n# OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n# DEALINGS IN THE SOFTWARE.\n#\n\nimport ctypes, json, os, sys, threading, time\n\nif 'LD_LIBRARY_PATH' in os.environ:\n    connectal = ctypes.CDLL('connectal.so')\nelse:\n    connectal = ctypes.CDLL('./connectal.so')\n\nclass JsonObject:\n    def __init__(self, d=None, **kwargs):\n        if d:\n            for k in d:\n                setattr(self, k, d[k])\n        if kwargs:\n            for k in kwargs:\n                setattr(self, k, kwargs[k])\n\ndef json_object_hook(d, encoding=None):\n    result = JsonObject(d)\n    return result\n\nclass NativeProxy:\n    def __init__(self, interfaceName, handler, responseInterface=None, rpc=False, multithreaded=False):\n        self.interfaceName = interfaceName\n        self.handler = handler\n        self.rpc = rpc\n        self.multithreaded = multithreaded\n        if rpc:\n            if multithreaded:\n                self.sem_response = threading.Semaphore(0)\n                self._response = False\n        self.stopPolling = False\n        self.methods = {}\n        newRequestPortal = connectal.newRequestPortal\n        newRequestPortal.restype = ctypes.c_void_p\n        newIndicationPortal = connectal.newIndicationPortal\n        newIndicationPortal.restype = ctypes.c_void_p\n        reqifcname = ctypes.c_int.in_dll(connectal, 'ifcNames_%sS2H' % interfaceName)\n        reqinfo = ctypes.c_int.in_dll(connectal, '%s_reqinfo' % interfaceName)\n        #print('reqifcname=', reqifcname, ' reqinfo=', reqinfo)\n        self.requestPortal = newRequestPortal(reqifcname, reqinfo)\n        respifcname = ctypes.c_int.in_dll(connectal, 'ifcNames_%sH2S' % responseInterface)\n        respinfo = ctypes.c_int.in_dll(connectal, '%s_reqinfo' % responseInterface)\n        resphandlemessage = getattr(connectal, '%s_handleMessage' % responseInterface)\n        respproxyreq = ctypes.c_long.in_dll(connectal, 'p%sJsonProxyReq' % responseInterface)\n        #print('respproxyreq=', respproxyreq)\n        self.responsePortal = newIndicationPortal(respifcname, respinfo, resphandlemessage, respproxyreq)\n        connectal.set_callback(self.responsePortal, ctypes.py_object(self))\n        #print('JJ', '%x' % self.requestPortal, '%x' % self.responsePortal)\n        if multithreaded:\n            self.t1 = threading.Thread(target=self.worker)\n            self.t1.start()\n\n    def callback(self, a):\n        ## use json_object_hook to convert JSON dictionaries to python objects\n        vec = json.loads(a.strip(), None, None, json_object_hook)\n        #print('callback called!!!', a, vec)\n        if hasattr(self.handler, vec[0]):\n            getattr(self.handler, vec[0])(*vec[1:])\n            if self.rpc:\n                if self.multithreaded:\n                    self.sem_response.release()\n                else:\n                    self._response = True\n\n    def worker(self):\n        while not self.stopPolling:\n            connectal.portal_event(ctypes.c_void_p(self.responsePortal))\n\n    def __getattr__(self, name, default=None):\n        #print('__getattr__', name, default)\n        if name in self.methods:\n            return self.methods[name]\n        m = getattr(connectal, '%s_%s' % (self.interfaceName, name), None)\n        if m:\n            def fcn (*args):\n                requestPortal = ctypes.c_void_p(self.requestPortal)\n                #print(m, args)\n                if len(args) == 1:\n                    m(requestPortal, args[0])\n                elif len(args) == 2:\n                    m(requestPortal, args[0], args[1])\n                if self.rpc:\n                    if self.multithreaded:\n                        self.sem_response.acquire()\n                    else:\n                        self._response = False\n                        while not self._response:\n                            connectal.portal_event(ctypes.c_void_p(self.responsePortal))\n            self.methods[name] = fcn\n            return fcn\n        else:\n            return default\n"
  },
  {
    "path": "scripts/portalJson.py",
    "content": "#!/usr/bin/env python3\n\n# Copyright (c) 2013 Quanta Research Cambridge, Inc.\n\n# Permission is hereby granted, free of charge, to any person\n# obtaining a copy of this software and associated documentation\n# files (the \"Software\"), to deal in the Software without\n# restriction, including without limitation the rights to use, copy,\n# modify, merge, publish, distribute, sublicense, and/or sell copies\n# of the Software, and to permit persons to whom the Software is\n# furnished to do so, subject to the following conditions:\n\n# The above copyright notice and this permission notice shall be\n# included in all copies or substantial portions of the Software.\n\n# THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n# EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n# MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n# BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n# ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n# CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n# SOFTWARE.\n\nimport math\nimport socket\nimport struct\nimport ctypes\nimport json\n\nclass portal:\n    def __init__(self, devaddr, devport):\n        self.s = socket.socket(socket.AF_INET, socket.SOCK_STREAM)\n        self.s.connect((devaddr, devport))\n        self.llen = ctypes.sizeof(ctypes.c_int);\n    def recv(self):\n        bytes_recd = 0\n        while bytes_recd < self.llen:\n            chunk = self.s.recv(self.llen)\n            bytes_recd = len(chunk)\n        liw = struct.unpack(\"hh\", chunk)[0]\n        blen = (liw-1)*self.llen\n        bytes_recd = 0\n        buffer = []\n        while bytes_recd < blen:\n            chunk = self.s.recv(blen)\n            bytes_recd += len(chunk) \n            buffer.append(chunk)\n        rv = buffer[0]\n        for b in buffer[1:]:\n            rv = rv + b\n        return rv\n    def send(self, d):\n        data = json.dumps(d, separators=(',',':'), sort_keys=True)\n        liw = math.ceil(len(data)/4.0)\n        padding = ''.join([' ' for i in range(len(data), int(liw*4))])\n        self.s.send(struct.pack(\"@i\", (1+liw))+data+padding)\n    def shutdown(self):\n        self.s.shutdown(socket.SHUT_RDWR)\n        self.s.close()\n"
  },
  {
    "path": "scripts/power.py",
    "content": "#! /usr/bin/env python3\n# Copyright (c) 2014 Quanta Research Cambridge, Inc\n# Original author John Ankcorn\n#\n# Permission is hereby granted, free of charge, to any person obtaining a\n# copy of this software and associated documentation files (the \"Software\"),\n# to deal in the Software without restriction, including without limitation\n# the rights to use, copy, modify, merge, publish, distribute, sublicense,\n# and/or sell copies of the Software, and to permit persons to whom the\n# Software is furnished to do so, subject to the following conditions:\n#\n# The above copyright notice and this permission notice shall be included\n# in all copies or substantial portions of the Software.\n#\n# THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n# OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n# DEALINGS IN THE SOFTWARE.\n\n# This is a control program for and NP-02B ethernet power switch from synaccess-net.com.\n#\n# The API is documented at:\n#    http://www.synaccess-net.com/downloadDoc/NPStartup-B.pdf\n#\n\nfrom __future__ import print_function\nimport socket,sys,time\n\nif sys.argv[1] == 'discover':\n    import discover_tcp\n    discover_tcp.detect_network(None,23,False)\n    sys.exit(0)\n\nif len(sys.argv) < 3:\n    print('power.py <ipaddress> <command> ...')\n    print('Where <command> is:')\n    print('    pset n v    Sets outlet #n to v(value 1-on,0-off)')\n    print('    mac         Displays Ethernet port Mac address')\n    print('    nwshow      Displays network Status')\n    print('    pshow       Displays outlet status')\n    print('    sysshow     Displays system information')\n    print('    time        Displays current time')\n    print('    ver         Displays hardware and software versions')\n    sys.exit(1)\n\nlines = []\ns = socket.socket(socket.AF_INET, socket.SOCK_STREAM)\ns.connect((sys.argv[1], 23))\ninline = ''\nfor item in sys.argv[2:]:\n    inline = inline + item + ' '\ns.send(inline + '\\r\\nlogout\\r\\n')\ninline = ''\nwhile True:\n    data = s.recv(1000)\n    if not data:\n        break\n    for c in data:\n        if c == '\\r' or c == '\\n':\n            if inline != '':\n                print(inline)\n            inline = ''\n        else:\n            inline = inline + c\ns.close()\nif inline != '':\n    print(inline)\nprint('connection ended')\n"
  },
  {
    "path": "scripts/preprocess_trace.py",
    "content": "#! /usr/bin/env python3\n# Copyright (c) 2014 Quanta Research Cambridge, Inc\n# Original author John Ankcorn\n#\n# Permission is hereby granted, free of charge, to any person obtaining a\n# copy of this software and associated documentation files (the \"Software\"),\n# to deal in the Software without restriction, including without limitation\n# the rights to use, copy, modify, merge, publish, distribute, sublicense,\n# and/or sell copies of the Software, and to permit persons to whom the\n# Software is furnished to do so, subject to the following conditions:\n#\n# The above copyright notice and this permission notice shall be included\n# in all copies or substantial portions of the Software.\n#\n# THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n# OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n# DEALINGS IN THE SOFTWARE.\n\nfrom __future__ import print_function\nimport sys\n\nprint('preprocess_trace.py:', sys.argv)\ncppind = []\nbsvind = []\nfor filename in sys.argv[2:]:\n    data = open(filename).readlines()\n    hasdisplay = False\n    hasdispind = False\n    for line in data:\n        if line.find('$display') >= 0:\n            hasdisplay = True\n        if line.find('printfInd') >= 0:\n            hasdispind = True\n    if hasdisplay and hasdispind:\n        fname = sys.argv[1] + '/generatedbsv/' + filename\n        fh = open(fname, 'w')\n        for line in data:\n            ind = line.find('$display')\n            if ind >= 0:\n                param = line[ind+8:].strip()[1:][:-2].strip()\n                formatstr = ''\n                pitem = ''\n                level = 0\n                informat = True\n                pactual = []\n                for ch in param[1:]:\n                    if informat:\n                        if ch == '\"':\n                            if level == 0:\n                                informat = False\n                        else:\n                            formatstr = formatstr + ch\n                    elif ch == ',':\n                        if pitem != '':\n                            pactual.append(pitem.strip())\n                        pitem = ''\n                    else:\n                        pitem = pitem + ch\n                pactual.append(pitem.strip())\n                freplace = 'printfind_'\n                lastch = ''\n                plist = []\n                for ch in formatstr:\n                    if lastch == '%':\n                        if ch == 'x':\n                            plist.append('Bit#(32)')\n                        else:\n                            print('unknown format char', ch)\n                    if ch == '-':\n                        freplace = freplace + '__'\n                    elif (ch >= 'A' and ch <= 'Z') or (ch >= 'a' and ch <= 'z') or (ch >= '0' and ch <= '9'):\n                        freplace = freplace + ch\n                    else:\n                        freplace = freplace + '_' + '{:02x}'.format(ord(ch))\n                    lastch = ch\n                line = line[:ind] + 'printfInd.' + freplace + '(' + ','.join(pactual) + ');\\n'\n                pformal = ''\n                pactual = ''\n                pbsv = ''\n                pcount = 1\n                for item in plist:\n                    if pcount > 1:\n                        pformal = pformal + ', '\n                        pactual = pactual + ', '\n                        pbsv = pbsv + ', '\n                    pvar = 'v%d' % pcount\n                    pcount = pcount + 1\n                    if item == 'Bit#(32)':\n                        pformal = pformal + 'uint32_t ' + pvar\n                        pactual = pactual + pvar\n                    pbsv = pbsv + item + ' ' + pvar\n                cppind.append('    void ' + freplace + '(' + pformal + ') { printf(\"' + formatstr + '\\\\n\", ' + pactual + '); }\\n')\n                bsvind.append('    method Action ' + freplace + '(' + pbsv + ');\\n')\n            fh.write(line)\n        fh.close()\nif cppind != []:\n    fname = sys.argv[1] + '/jni/printfInd.h'\n    fh = open(fname, 'w')\n    fh.write('class DisplayInd : public DisplayIndWrapper\\n')\n    fh.write('{\\n')\n    fh.write('public:\\n')\n    fh.write('    DisplayInd(unsigned int id, PortalPoller *poller) : DisplayIndWrapper(id, poller) {}\\n')\n    for item in cppind:\n        fh.write(item)\n    fh.write('};\\n')\n    fh.close()\nif bsvind != []:\n    fname = sys.argv[1] + '/generatedbsv/DisplayInd.bsv'\n    fh = open(fname, 'w')\n    fh.write('interface DisplayInd;\\n')\n    for item in bsvind:\n        fh.write(item)\n    fh.write('endinterface\\n')\n    fh.close()\nsys.exit(0)\n"
  },
  {
    "path": "scripts/reorderbytes.py",
    "content": "#!/usr/bin/env python3\n# Copyright (c) 2014 Quanta Research Cambridge, Inc.\n#\n# Permission is hereby granted, free of charge, to any person\n# obtaining a copy of this software and associated documentation\n# files (the \"Software\"), to deal in the Software without\n# restriction, including without limitation the rights to use, copy,\n# modify, merge, publish, distribute, sublicense, and/or sell copies\n# of the Software, and to permit persons to whom the Software is\n# furnished to do so, subject to the following conditions:\n#\n# The above copyright notice and this permission notice shall be\n# included in all copies or substantial portions of the Software.\n#\n# THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n# EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n# MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n# BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n# ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n# CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n# SOFTWARE.\n\nfrom __future__ import print_function\nimport sys, array\n\nif __name__=='__main__':\n    if len(sys.argv) != 3:\n        print('reorderbytes <infile> <outfile>')\n        sys.exit(1)\n    filename = sys.argv[1]\n    if filename == '-':\n        infile = sys.stdin\n    else:\n        infile = open(filename, 'rb')\n    readarr = array.array('I', infile.read())\n    readarr.byteswap()\n    open(sys.argv[2], 'wb').write(readarr.tostring())\n"
  },
  {
    "path": "scripts/run.android",
    "content": "#!/usr/bin/env python3\n\n# Copyright (c) 2013 Quanta Research Cambridge, Inc.\n\n# Permission is hereby granted, free of charge, to any person\n# obtaining a copy of this software and associated documentation\n# files (the \"Software\"), to deal in the Software without\n# restriction, including without limitation the rights to use, copy,\n# modify, merge, publish, distribute, sublicense, and/or sell copies\n# of the Software, and to permit persons to whom the Software is\n# furnished to do so, subject to the following conditions:\n\n# The above copyright notice and this permission notice shall be\n# included in all copies or substantial portions of the Software.\n\n# THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n# EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n# MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n# BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n# ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n# CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n# SOFTWARE.\n\nfrom __future__ import print_function\n\nimport argparse\nimport os\nimport socket\nimport subprocess\nimport sys\nimport discover_tcp\n\nscriptdir=os.path.dirname(sys.argv[0])\nsys.path.append(scriptdir)\n\nfrom adb import adb_commands\nfrom adb import common\nfrom argparse import RawTextHelpFormatter\n\ntimelimit=600\nif 'RUNTIMELIMIT' in os.environ:\n    timelimit = int(os.environ['RUNTIMELIMIT'])\nbuildbot_build=None\nif 'BUILDBOT_BUILD_NUMBER' in os.environ:\n    buildbot_build = os.environ['BUILDBOT_BUILD_NUMBER']\n\nif 'RUNPARAM' in os.environ:\n    ipaddr = os.environ['RUNPARAM']\nelse:\n    ipaddr = None\n\nbuildbot_url='http://connectalbuild.qrclab.com/archive/'\nif 'BUILDBOT_URL' in os.environ:\n    buildbot_url=os.environ['BUILDBOT_URL']\n\nepilog = '''\nWill download the bit file and executable from buildbot if\nbuildbot-url, project, and build-number are specified.\n\nThe buildbot-url defaults to %(buildbot_url)s.\n\nWill download the bit file and executable from an arbitrary location \nusing rsync if rsync-path is specified. If you require a non-default \nidentity file for rsync, add the  following lines to ~/.ssh/config:\n\n   Host <hostname>\n   HostName <url>\n   User <username>\n   Port 22\n   IdentityFile <path_to_key>\n\n---\n''' % {\n    'buildbot_url': buildbot_url\n}\n\nargparser = argparse.ArgumentParser(\"Run Connectal apps on Android Zynq boards.\",\n                                    epilog=epilog, formatter_class=RawTextHelpFormatter)\nargparser.add_argument('androidexe', help='Android executable for the Zynq', nargs='?')\nargparser.add_argument('push', help='Additional files to push to the target before execution', nargs='*', default=[])\nargparser.add_argument('--pull', help='Additional files to pull from the target after execution', nargs='*', default=[])\nargparser.add_argument('-t', '--timelimit', type=int, default=timelimit, help='Time limit for jobs running on the zedboard. Defaults to value of environment variable RUNTIMELIMIT or 600 seconds.')\nargparser.add_argument('-a', '--ipaddr', default=ipaddr, help='IP address of target board')\nargparser.add_argument('-u', '--buildbot-url', default=buildbot_url, help='Base URL of buildbot.')\nargparser.add_argument('-p', '--project', help='Name of project on buildbot.')\nargparser.add_argument('-b', '--build-number', help='Build number on buildbot.')\nargparser.add_argument('-n', '--board-name', help='String in \\'hostname\\' on the SDCard')\nargparser.add_argument('-r', '--rsync-path', help='rsync path to android.exe (hostname:/home/.../zedboard/bin/)')\n\n\ndef run_android(androidexe, pushFiles, pullFiles=[]):\n    ipaddr = options.ipaddr\n\n    if ipaddr:\n        if ipaddr.find(':') == -1:\n            ipaddr = ipaddr + ':5555'\n    else:\n        if (options.board_name):\n            found = False\n            discover_tcp.detect_network()\n            for ip,name in discover_tcp.zedboards:\n                if options.board_name == name:\n                    ipaddr = ip\n                    found = True\n                    print(\"found %s at %s\" %(name,ip))\n            if not found:\n                print(\"unable to find %s on your subnet\" % name)\n        else:\n            p = subprocess.Popen('checkip')\n            ipaddr = p.stdout.read()\n            ipaddr = ipaddr.replace('\\n', '')\n            ipaddr = ipaddr.replace('\\r', '')\n            ipaddr = ipaddr + ':5555'\n\n    device_serial = ipaddr\n\n    print('connecting to %s' % device_serial)\n    connected = False\n    while not connected:\n        try:\n            connection = adb_commands.AdbCommands.ConnectDevice(serial=device_serial)\n            connected = True\n        except socket.error:\n            #print('socket.error', sys.exc_info())\n            pass\n\n    print('Reconnecting')\n    connected = False\n    while not connected:\n        try:\n            connection = adb_commands.AdbCommands.ConnectDevice(serial=device_serial)\n            connected = True\n        except socket.error:\n            #print('socket.error', sys.exc_info())\n            pass\n\n    params = { 'time': options.timelimit,\n               'env': '',\n               'exe': os.path.basename(androidexe),\n               'args': ' '.join([os.path.basename(f) for f in pushFiles]),\n             }\n    nofpgajtag = os.environ.get('NOFPGAJTAG')\n    if nofpgajtag != None:\n         params['env'] += 'NOFPGAJTAG= '\n    print('Sending files to the zedboard')\n    connection.Push(androidexe, '/mnt/sdcard/tmp/%(exe)s' % params)\n    connection.Shell('chmod agu+rx /mnt/sdcard/tmp/%(exe)s' % params)\n    for f in pushFiles:\n        print('Pushing file %s' % f)\n        connection.Push(f, '/mnt/sdcard/tmp/%s' % os.path.basename(f))\n    connection.Shell(\"touch /mnt/sdcard/tmp/perf.monkit\")\n    print('Running %(exe)s with timelimit %(time)d' % params)\n    cmd = (\"cd /mnt/sdcard/tmp/; rm -f /mnt/sdcard/tmp/exit.status; %(env)s /mnt/sdcard/timelimit -t %(time)d ./%(exe)s %(args)s; echo $? > /mnt/sdcard/tmp/exit.status\"\n           % params)\n    for line in connection.StreamingShell(cmd):\n        sys.stdout.write(line)\n    connection.Pull('/mnt/sdcard/tmp/exit.status', 'exit.status')\n    connection.Pull('/mnt/sdcard/tmp/perf.monkit', 'perf.monkit')\n    for f in pullFiles:\n        print('pulling %s' % f)\n        connection.Pull('/mnt/sdcard/tmp/%s' % f, f)\n    connection.Shell('rm -vf %s' % ' '.join([os.path.basename(f) for f in [androidexe] + pushFiles]))\n    status = int(open('exit.status').read())\n    print('status=%d' % status)\n    sys.exit(status)\n\nif __name__ == '__main__':\n    options = argparser.parse_args()\n    if options.buildbot_url and options.project and options.build_number:\n        # download android.exe\n        options.androidexe = 'android.exe'\n        url = '%s/%s/%s/bin/android.exe' % (options.buildbot_url, options.project, options.build_number)\n        print('downloading', url)\n        status = subprocess.call(['curl', '-f', '-O', url])\n        if status != 0:\n            #print 'curl returned error', status\n            sys.exit(status)\n    elif options.rsync_path:\n        options.androidexe = 'android.exe'\n        status = subprocess.call(['rsync', '-av', '%s/android.exe' % (options.rsync_path), '.'])\n        if status != 0:\n            sys.exit(status)\n    if not options.androidexe:\n        argparser.print_help()\n        sys.exit(1)\n    run_android(options.androidexe, options.push, options.pull)\n"
  },
  {
    "path": "scripts/run.android.sh",
    "content": "#\nset -x\nset -e\nexport SCRIPT_DIR=\"$( cd \"$( dirname \"$0\" )\" && pwd )\"\necho \"run.android parameters are:\" $*\nandroidexe=$1\nif [ \"$BUILDBOT_URL\" == \"\" ]; then\n   BUILDBOT_URL=\"http://sj9.qrclab.com/archive\"\nfi\nif [ \"$BUILDBOT_BUILD\" != \"\" ]; then\n   mkdir -p zedboard/bin\n   (cd zedboard/bin; \\\n   curl -v -O $BUILDBOT_URL/$BUILDBOT_BUILD/bin/android.exe ; \\\n   curl -v -O $BUILDBOT_URL/$BUILDBOT_BUILD/bin/mkTop.xdevcfg.bin.gz)\n   chmod agu+rx zedboard/bin/android.exe\n   androidexe=zedboard/bin/android.exe\nfi\nif [ \"$RUNPARAM\" != \"\" ]; then\n    ZEDBOARD_IPADDR=$RUNPARAM\nelse\n    ZEDBOARD_IPADDR=`checkip`\nfi\nif [ \"$RUNTIMELIMIT\" != \"\" ]; then\n    TIMELIMIT=$RUNTIMELIMIT\nelse\n    TIMELIMIT=180\nfi\nANDROID_SERIAL=$ZEDBOARD_IPADDR:5555\nexename=`basename $androidexe`\nadb -s $ANDROID_SERIAL disconnect $ZEDBOARD_IPADDR\nsleep 2\nadb connect $ZEDBOARD_IPADDR\nadb -s $ANDROID_SERIAL root\nsleep 2\nadb connect $ZEDBOARD_IPADDR\n## sometimes /mnt/sdcard is readonly:\nadb -s $ANDROID_SERIAL shell mount -o remount,rw /mnt/sdcard\nadb -s $ANDROID_SERIAL shell mkdir -p /mnt/sdcard/tmp\nadb -s $ANDROID_SERIAL shell mount -t tmpfs tmpfs /mnt/sdcard/tmp\nadb -s $ANDROID_SERIAL push $androidexe /mnt/sdcard/tmp\nfor f in $RUNFILES; do\n    adb -s $ANDROID_SERIAL push $f /mnt/sdcard/tmp\ndone\nadb -s $ANDROID_SERIAL shell rmmod portalmem\nadb -s $ANDROID_SERIAL shell rmmod zynqportal\nadb -s $ANDROID_SERIAL shell insmod /mnt/sdcard/portalmem.ko\nadb -s $ANDROID_SERIAL shell insmod /mnt/sdcard/zynqportal.ko\nadb -s $ANDROID_SERIAL shell \"pwd\"\nadb -s $ANDROID_SERIAL shell touch /mnt/sdcard/tmp/perf.monkit\nif [ \"$CONNECTAL_DEBUG\" != \"\" ]; then\nadb -s $ANDROID_SERIAL forward tcp:5039 tcp:5039   \nadb -s $ANDROID_SERIAL shell gdbserver :5039 /mnt/sdcard/tmp/android.exe &\nTEMP=`dirname $androidexe`/../..\nTEMPDIR=$TEMP/obj/local/armeabi\nTEMPSCRIPT=$TEMP/xxfoo\necho set solib-search-path $TEMPDIR >$TEMPSCRIPT\necho target remote :5039 >>$TEMPSCRIPT\n`ndk-which gdb` --command=$TEMPSCRIPT $TEMPDIR/android.exe\nelse\nadb -s $ANDROID_SERIAL shell \"cd /mnt/sdcard/tmp/; rm -f /mnt/sdcard/tmp/exit.status; /mnt/sdcard/timelimit -t $TIMELIMIT ./$exename $3; echo \\$? > /mnt/sdcard/tmp/exit.status\"\nadb -s $ANDROID_SERIAL pull /mnt/sdcard/tmp/exit.status ./\nadb -s $ANDROID_SERIAL pull /mnt/sdcard/tmp/perf.monkit `dirname $androidexe`\nfi\nadb -s $ANDROID_SERIAL shell rm -f /mnt/sdcard/tmp/`basename $androidexe` /mnt/sdcard/tmp/perf.monkit\npwd\nstatus=`cat exit.status`\nif [ \"$status\" != \"0\" ]; then\n  status=1\nfi\nexit $status\n"
  },
  {
    "path": "scripts/run.parallella.sh",
    "content": "#\n# push programs to a parallella board\n# running linux, and execute\nset -x\nset -e\nexport SCRIPT_DIR=\"$( cd \"$( dirname \"$0\" )\" && pwd )\"\necho \"run.parallella.sh parameters are:\" $*\nbitfile=$1\nubuntuexe=$2\nparallellahost=$3\nif [ \"$RUNTIMELIMIT\" != \"\" ]; then\n    TIMELIMIT=$RUNTIMELIMIT\nelse\n    TIMELIMIT=180\nfi\nexename=`basename $ubuntuexe`\nfor f in $RUNFILES; do\n    scp $f $parallellahost:/mnt/sdcard/tmp\ndone\nscp $bitfile $parallellahost:/tmp\nscp $ubuntuexe $parallellahost:/tmp\nscp $CONNECTALDIR/drivers/portalmem/portalmem.ko $parallellahost:/tmp\nscp $CONNECTALDIR/drivers/zynqportal/zynqportal.ko $parallellahost:/tmp\nset +e\nssh $parallellahost sudo rmmod portalmem\nssh $parallellahost sudo rmmod zynqportal\nset -e\nssh $parallellahost sudo insmod /tmp/portalmem.ko\nssh $parallellahost sudo insmod /tmp/zynqportal.ko\nssh $parallellahost sudo \"gzip -dc /tmp/`basename $bitfile` >/dev/xdevcfg\"\nssh $parallellahost sudo cat /dev/connectal\n\nssh $parallellahost sudo /tmp/$exename\n\nstatus=0\nif [ \"$status\" != \"0\" ]; then\n  status=1\nfi\nexit $status\n"
  },
  {
    "path": "scripts/run.pcietest",
    "content": "#!/bin/bash\n#set -x\nset -e\nexport SCRIPT_DIR=\"$( cd \"$( dirname \"$0\" )\" && pwd )\"\necho \"run.pcie parameters are:\" $*\nSSHPARAM=\" -o StrictHostKeyChecking=no\"\n\nif [ \"$1\" == \"\" ]; then\n    echo \"usage: $0 ubuntu.exe\" >&2\n    exit -1\nfi\n\nif [ \"$SERIALNO\" != \"\" ]; then\n    BOARD_SERIAL=\"SERIALNO=$SERIALNO\"\nelse\n    BOARD_SERIAL=\"\"\nfi\nif [ \"$RUNTIMELIMIT\" != \"\" ]; then\n    TIMELIMIT=$RUNTIMELIMIT\nelse\n    TIMELIMIT=3m\nfi\n\nENV=\"\"\nif [ \"$RUNENV\" != \"\" ]; then\n    for e in `env | grep $RUNENV | grep -v RUNENV | sed 's/=(.*)/=\\\"$1\\\"/'`; do\n\tENV=\"$ENV $e\"\n    done\nfi\n\nif [ \"$RUNPARAM\" != \"\" ]; then\n    if [ \"$ENV\" != \"\" ]; then\n\techo \"sending environment variables $ENV\"\n    fi\n    RUNPARAMTEMP=$RUNPARAM:22\n    array=(${RUNPARAMTEMP//:/ })\n    RUNIP=${array[0]}\n    RUNPORT=${array[1]}\n    TEMPDIR=/tmp/`uname -n`-$PPID-pcie\n    ssh $SSHPARAM -p $RUNPORT $RUNIP \"rm -rf $TEMPDIR; mkdir -p $TEMPDIR\" || exit 1\n    scp -P $RUNPORT $* $RUNIP:$TEMPDIR || exit 2\n    EXE=$1\n    EXENAME=`basename $1`\n    ARGS=\"\"\n    shift\n    echo \"ARGS=$*\"\n    for arg in $*; do arg_basename=`basename $arg`; ARGS=\"$ARGS $TEMPDIR/$arg_basename\"; done\n    ssh $SSHPARAM -p $RUNPORT $RUNIP \"$BOARD_SERIAL $ENV timeout $TIMELIMIT catchsegv $TEMPDIR/$EXENAME $ARGS\"; status=$?\n    ssh $SSHPARAM -p $RUNPORT $RUNIP \"pcieflat > $TEMPDIR/pcieflat.txt\"\n    scp -P $RUNPORT $RUNIP:$TEMPDIR/pcieflat.txt `dirname $EXE`\n    ssh $SSHPARAM -p $RUNPORT $RUNIP \"rm -rf $TEMPDIR\"\n    exit $status\nelse\n    timeout 3m catchsegv $1; status=$?\n    if [ \"$PORTAL_DUMP_MAP\" != \"\" ]; then\n        pcieflat -j $PORTAL_DUMP_MAP generatedDesignInterfaceFile.json > bin/pcieflat.txt\n    else\n        pcieflat > bin/pcieflat.txt\n    fi\n    exit $status\nfi\n"
  },
  {
    "path": "scripts/run.pcietest.altera",
    "content": "#\nset -x\nset -e\nexport SCRIPT_DIR=\"$( cd \"$( dirname \"$0\" )\" && pwd )\"\necho \"run.de5test parameters are:\" $*\nSSHPARAM=\" -o StrictHostKeyChecking=no\"\n\nif [ \"$SERIALNO\" != \"\" ]; then\n    BOARD_USB=\"-c $SERIALNO\"\nelse\n    BOARD_USB=\"-c 1\"\nfi\nif [ \"$RUNTIMELIMIT\" != \"\" ]; then\n    TIMELIMIT=$RUNTIMELIMIT\nelse\n    TIMELIMIT=3m\nfi\n\nif [ \"$RUNPARAM\" != \"\" ]; then\n    TEMPDIR=/tmp/`uname -n`-$PPID-pcie\n    ssh $SSHPARAM $RUNPARAM \"rm -rf $TEMPDIR; mkdir -p $TEMPDIR\"\n    scp $1 $2 $RUNPARAM:$TEMPDIR\n    BINNAME=`basename $1`\n    EXENAME=`basename $2`\n    if [ \"$NOPROGRAM\" != \"1\" ]; then\n        ssh $SSHPARAM $RUNPARAM \"fpgajtag $BOARD_USB $TEMPDIR/$BINNAME\"\n    else\n        echo \"not programming $BOARD\"\n    fi\nelse\n    if [ \"$NOPROGRAM\" != \"1\" ]; then\n\t    echo $1\n        quartus_pgm $BOARD_USB -m jtag -o p\\;$1\n        sleep 1\n    fi\nfi\n"
  },
  {
    "path": "scripts/run_on_daffodil",
    "content": "#! /bin/bash\n\n./run.android --buildbot-url=http://connectalbuild.qrclab.com/archive --project=connectal-simple/zedboard --build-number=10  --board-name=daffodil_zedboard\n"
  },
  {
    "path": "scripts/syntax.py",
    "content": "#!/usr/bin/env python3\n# Copyright (c) 2014 Quanta Research Cambridge, Inc\n#\n# Permission is hereby granted, free of charge, to any person obtaining a\n# copy of this software and associated documentation files (the \"Software\"),\n# to deal in the Software without restriction, including without limitation\n# the rights to use, copy, modify, merge, publish, distribute, sublicense,\n# and/or sell copies of the Software, and to permit persons to whom the\n# Software is furnished to do so, subject to the following conditions:\n#\n# The above copyright notice and this permission notice shall be included\n# in all copies or substantial portions of the Software.\n#\n# THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n# OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n# DEALINGS IN THE SOFTWARE.\n#\n\nfrom __future__ import print_function\n\nimport ply.lex as lex\nimport AST\nimport json, os, re, sys\n\nimport bsvpreprocess\nimport globalv\nimport cppgen, bsvgen\n\nscripthome = os.path.dirname(os.path.abspath(__file__))\nnoisyFlag=True\nparseDebugFlag=False\nparseTrace=False\n\ntokens = (\n    'AMPER',\n    'AMPERAMPER',\n    'AMPERAMPERAMPER',\n    'APOSTROPHE',\n    'BANG',\n    'BAR',\n    'BARBAR',\n    'BUILTINVAR',\n    'CARET',\n    'COLON',\n    'COLONCOLON',\n    'COMMA',\n    'DOT',\n    'EQEQ',\n    'EQUAL',\n    'GEQ',\n    'GREATER',\n    'GREATERGREATER',\n    'HASH',\n    'LARROW',\n    'LBRACE',\n    'LBRACKET',\n    'LEQ',\n    'LESS',\n    'LESSLESS',\n    'LPAREN',\n    'LPARENSTAR',\n    'MINUS',\n    'NEQ',\n    'NUM',\n    'PERCENT',\n    'PLUS',\n    'QUESTION',\n    'RBRACE',\n    'RBRACKET',\n    'RPAREN',\n    'RPARENSTAR',\n    'SEMICOLON',\n    'SLASH',\n    'STAR',\n    'STARSTAR',\n    'STR',\n    'TILDE',\n    'TILDEAMPER',\n    'TILDEBAR',\n    'TILDECARET',\n    'VAR'\n)\n\nreserved = {\n    'action': 'TOKACTION',\n    'Action': 'TOKUACTION',\n    'actionvalue': 'TOKACTIONVALUE',\n    'BDPI': 'TOKBDPI',\n    'begin': 'TOKBEGIN',\n    'BVI': 'TOKBVI',\n    'C': 'TOKC',\n    'case': 'TOKCASE',\n    'CF': 'TOKCF',\n    'clocked_by': 'TOKCLOCKED_BY',\n    'default': 'TOKDEFAULT',\n    'default_clock': 'TOKDEFAULT_CLOCK',\n    'default_reset': 'TOKDEFAULT_RESET',\n    '`define': 'TOKTICKDEFINE',\n    'dependencies': 'TOKDEPENDENCIES',\n    'deriving': 'TOKDERIVING',\n    'determines': 'TOKDETERMINES',\n    'else': 'TOKELSE',\n    'enable': 'TOKENABLE',\n    'end': 'TOKEND',\n    'endaction': 'TOKENDACTION',\n    'endactionvalue': 'TOKENDACTIONVALUE',\n    'endcase': 'TOKENDCASE',\n    'endfunction': 'TOKENDFUNCTION',\n    'endinstance': 'TOKENDINSTANCE',\n    'endinterface': 'TOKENDINTERFACE',\n    'endmethod': 'TOKENDMETHOD',\n    'endmodule': 'TOKENDMODULE',\n    'endpackage': 'TOKENDPACKAGE',\n    'endpar': 'TOKENDPAR',\n    'endrule': 'TOKENDRULE',\n    'endrules': 'TOKENDRULES',\n    'endseq': 'TOKENDSEQ',\n    'endtypeclass': 'TOKENDTYPECLASS',\n    'enum': 'TOKENUM',\n    'export': 'TOKEXPORT',\n    'for': 'TOKFOR',\n    'function': 'TOKFUNCTION',\n    'if': 'TOKIF',\n    'import': 'TOKIMPORT',\n#    'in': 'TOKIN',\n    'input_clock': 'TOKINPUT_CLOCK',\n    'input_reset': 'TOKINPUT_RESET',\n    'instance': 'TOKINSTANCE',\n    'interface': 'TOKINTERFACE',\n    'let': 'TOKLET',\n    'match': 'TOKMATCH',\n    'matches': 'TOKMATCHES',\n    'method': 'TOKMETHOD',\n    'module': 'TOKMODULE',\n    'no_reset': 'TOKNO_RESET',\n    'numeric': 'TOKNUMERIC',\n    'output_clock': 'TOKOUTPUT_CLOCK',\n    'output_reset': 'TOKOUTPUT_RESET',\n    'package': 'TOKPACKAGE',\n    'par': 'TOKPAR',\n    'port': 'TOKPORT',\n    'parameter': 'TOKPARAMETER',\n    'port': 'TOKPORT',\n    'provisos': 'TOKPROVISOS',\n    'ready': 'TOKREADY',\n    'reset_by': 'TOKRESET_BY',\n    'return': 'TOKRETURN',\n    'rule': 'TOKRULE',\n    'rules': 'TOKRULES',\n    'SB': 'TOKSB',\n    'SBR': 'TOKSBR',\n    'schedule': 'TOKSCHEDULE',\n    'seq': 'TOKSEQ',\n    '_when_': 'TOKWHEN',\n    'Stmt' : 'TOKSTMT',\n    'struct': 'TOKSTRUCT',\n    'tagged': 'TOKTAGGED',\n    'type': 'TOKTYPE',\n    'typeclass': 'TOKTYPECLASS',\n    'typedef': 'TOKTYPEDEF',\n    'union': 'TOKUNION',\n    'while': 'TOKWHILE',\n}\n\nfor tok in reserved.values():\n    tokens = tokens + (tok,)\n\nt_AMPER = r'&'\nt_AMPERAMPER = r'&&'\nt_AMPERAMPERAMPER = r'&&&'\nt_APOSTROPHE = r'\\''\nt_BANG = r'!'\nt_BAR = r'\\|'\nt_BARBAR = r'\\|\\|'\nt_CARET = r'\\^'\nt_COLON = r':'\nt_COLONCOLON = r'::'\nt_COMMA = r','\nt_DOT = r'[\\.]'\nt_EQEQ = r'=='\nt_EQUAL = r'='\nt_GEQ = r'>='\nt_GREATER = r'>'\nt_GREATERGREATER = r'>>'\nt_HASH = r'\\#'\nt_LARROW = r'<-'\nt_LBRACE = r'{'\nt_LBRACKET = r'\\['\nt_LEQ = r'<='\nt_LESS = r'<'\nt_LESSLESS = r'<<'\nt_LPAREN = r'\\('\nt_LPARENSTAR = r'\\(\\*'\nt_MINUS = r'[-]'\nt_NEQ = r'!='\nt_NUM = r'(([0-9]+\\'?[bdh\\.]?[0-9a-zA-Z?]*)|(\\'[bdh\\.]?[0-9a-zA-Z?]+))'\nt_PERCENT = r'%'\nt_PLUS = r'\\+'\nt_QUESTION = r'\\?'\nt_RBRACE = r'}'\nt_RBRACKET = r'\\]'\nt_RPAREN = r'\\)'\nt_RPARENSTAR = r'\\*\\)'\nt_SEMICOLON = r';'\nt_SLASH = r'/'\nt_STAR = r'\\*'\nt_STARSTAR = r'\\*\\*'\nt_STR = r'\"[^\\\"]*\"'\nt_TILDE = r'~'\nt_TILDEAMPER = r'~\\&'\nt_TILDEBAR = r'~\\|'\nt_TILDECARET = r'~^'\n\nt_ignore = ' \\t\\f'\n\ndef t_error(t):\n    print(\"Illegal character '%s' in file '%s'\" % (t.value[0], globalfilename))\n    t.lexer.skip(1)\n\ndef p_error(errtoken):\n    if hasattr(errtoken, 'lineno'):\n        sys.stderr.write(\"%s:%d: Syntax error, token=%s\\n\" % (globalfilename, errtoken.lineno, errtoken.type))\n    else:\n        sys.stderr.write(\"%s: Syntax error, token=%s\\n\" % (globalfilename, errtoken))\n    return None\n    \ndef t_VAR(t):\n    r'`?([a-zA-Z_][$a-zA-Z0-9_]*)|(\\\\[-+*/|^&][*]?)'\n    t.type = reserved.get(t.value,'VAR')    \n    return t\n\nt_BUILTINVAR = r'\\$[a-zA-Z_][a-zA-Z0-9_]*'\n\ndef t_newline(t):\n    r'\\n+'\n    t.lexer.lineno += len(t.value)\n\ndef t_COMMENT(t):\n    r'//.*'\n    pass\n\ndef t_MCOMMENT(t):\n    r'/\\*(.|\\n)*?\\*/'\n    #print(t.value, t.value.count('\\n'), t.lineno)\n    t.lineno += t.value.count('\\n')\n\nimport ply.yacc as yacc\n\ndef p_goal(p):\n    'goal : package '\n    p[0] = p[1]\n\ndef p_typeParams(p):\n    '''typeParams :\n                  | type\n                  | typeParams COMMA type'''\n    if len(p) == 2:\n        p[0] = [p[1]]\n    elif len(p) == 4:\n        p[0] = p[1] + [p[3]]\n    else:\n        p[0] = []\n\ndef p_type(p):\n    '''type : VAR\n            | VAR COLONCOLON VAR\n            | NUM\n            | TOKUACTION\n            | VAR HASH LPAREN typeParams RPAREN\n            | VAR COLONCOLON VAR HASH LPAREN typeParams RPAREN'''\n    if len(p) == 2:\n        p[0] = AST.Type(p[1], [])\n    elif len(p) == 4:\n        p[0] = p[3]\n    elif len(p) == 8:\n        p[0] = AST.Type(p[3], p[6])\n    else:\n        p[0] = AST.Type(p[1], p[4])\n\ndef p_expressions(p):\n    '''expressions : expression\n                   | \n                   | expressions COMMA expression'''\n\nprecedence = (\n    ('left', 'STAR', 'SLASH', 'PERCENT'),\n    ('left', 'PLUS', 'MINUS'),\n    ('left', 'GREATERGREATER', 'LESSLESS'),\n    ('left', 'LEQ', 'GEQ', 'LESS', 'GREATER'),\n    ('left', 'EQEQ', 'NEQ'),\n    ('left', 'AMPER'),\n    ('left', 'CARET'),\n    ('left', 'TILDECARET'),\n    ('left', 'BAR'),\n    ('left', 'AMPERAMPER'),\n    ('left', 'BARBAR'),\n    ('left', 'AMPERAMPERAMPER')\n)\n\ndef p_colonVar(p):\n    '''colonVar :\n                | COLON VAR'''\n\ndef p_expression(p):\n    '''expression : caseExpr\n                  | binaryExpression'''\n    p[0] = p[1]\n\ndef p_caseExprItem(p):\n    '''caseExprItem : pattern COLON expression SEMICOLON'''\n\ndef p_caseExprItems(p):\n    '''caseExprItems :\n                 | caseExprItems caseExprItem'''\n\ndef p_defaultExprItem(p):\n    '''defaultExprItem :\n                   | TOKDEFAULT expression SEMICOLON\n                   | TOKDEFAULT COLON expression SEMICOLON'''\n\ndef p_caseExpr(p):\n    '''caseExpr : TOKCASE LPAREN expression RPAREN caseExprItems defaultExprItem TOKENDCASE\n                | TOKCASE LPAREN expression RPAREN TOKMATCHES caseExprItems defaultExprItem TOKENDCASE'''\n\ndef p_binaryExpression(p):\n    '''binaryExpression : unaryExpression\n                        | binaryExpression AMPERAMPERAMPER binaryExpression\n                        | binaryExpression MINUS binaryExpression\n                        | binaryExpression PLUS binaryExpression\n                        | binaryExpression STAR binaryExpression\n                        | binaryExpression STARSTAR binaryExpression\n                        | binaryExpression APOSTROPHE binaryExpression\n                        | binaryExpression SLASH binaryExpression\n                        | binaryExpression CARET binaryExpression\n                        | binaryExpression LESS binaryExpression\n                        | binaryExpression GREATER binaryExpression\n                        | binaryExpression GEQ binaryExpression\n                        | binaryExpression LESSLESS binaryExpression\n                        | binaryExpression LEQ binaryExpression\n                        | binaryExpression GREATERGREATER binaryExpression\n                        | binaryExpression EQEQ binaryExpression\n                        | binaryExpression NEQ binaryExpression\n                        | binaryExpression AMPER binaryExpression\n                        | binaryExpression AMPERAMPER binaryExpression\n                        | binaryExpression BAR binaryExpression\n                        | binaryExpression BARBAR binaryExpression\n                        | binaryExpression PERCENT binaryExpression'''\n    p[0] = p[1]\n\ndef p_unaryExpression(p):\n    '''unaryExpression : term\n                       | PLUS term\n                       | MINUS term\n                       | BANG term\n                       | TILDE term\n                       | AMPER term\n                       | TILDEAMPER term\n                       | BAR term\n                       | TILDEBAR term\n                       | CARET term\n                       | TILDECARET term\n                       | TOKACTION colonVar expressionStmts TOKENDACTION colonVar\n                       | TOKACTIONVALUE colonVar expressionStmts TOKENDACTIONVALUE colonVar\n                       '''\n    p[0] = p[1]\n\ndef p_term(p):\n    '''term : type\n            | type LBRACKET expression RBRACKET\n            | type LBRACKET expression COLON expression RBRACKET\n            | STR\n            | QUESTION\n            | term QUESTION expression\n            | term QUESTION expression COLON expression\n            | LPAREN expression RPAREN\n            | TOKINTERFACE VAR interfaceHashParams SEMICOLON expressionStmts TOKENDINTERFACE colonVar\n            | TOKINTERFACE VAR COLONCOLON VAR interfaceHashParams SEMICOLON expressionStmts TOKENDINTERFACE colonVar\n            | TOKINTERFACE VAR expressionStmts TOKENDINTERFACE colonVar\n            | TOKINTERFACE VAR COLONCOLON VAR expressionStmts TOKENDINTERFACE colonVar\n            | BUILTINVAR\n            | TOKCLOCKED_BY expression\n            | TOKRESET_BY expression\n            | TOKTAGGED VAR\n            | TOKTAGGED VAR expression\n            | TOKTAGGED VAR LBRACE structInits RBRACE\n            | term LBRACE structInits RBRACE\n            | term TOKMATCHES pattern\n            | LBRACE expressions RBRACE\n            | term DOT VAR\n            | term LBRACKET expression RBRACKET DOT term\n            | term LBRACKET expression RBRACKET\n            | term LBRACKET expression COLON expression RBRACKET\n            | term LPAREN params RPAREN DOT term\n            | term LPAREN params RPAREN'''\n    if len(p) > 2 and type(p[1]) == str:\n        p[0] = p[2]\n    else:\n        p[0] = p[1]\n\ndef p_structInits(p):\n    '''structInits : \n                   | structInits COMMA VAR COLON expression\n                   | structInits COMMA VAR COLON DOT VAR\n                   | VAR COLON expression\n                   | VAR COLON DOT VAR'''\n\ndef p_structPatternElements(p):\n    '''structPatternElements : VAR COLON pattern\n                             | structPatternElements COMMA VAR COLON pattern '''\n\ndef p_pattern(p):\n    '''pattern : TOKTAGGED VAR\n               | TOKTAGGED VAR DOT VAR\n               | TOKTAGGED VAR LBRACE structPatternElements RBRACE\n               | LBRACE patterns RBRACE\n               | DOT VAR\n               | DOT STAR\n               | NUM'''\n\ndef p_patterns(p):\n    '''patterns : pattern\n                | patterns COMMA pattern'''\n\ndef p_importDecl(p):\n    'importDecl : TOKIMPORT VAR COLONCOLON STAR SEMICOLON'\n    if not p[2] in globalimports:\n        globalimports.append(p[2])\n    p[0] = p[2]\n\ndef p_importDecls(p):\n    '''importDecls : \n                   | importDecls importDecl'''\n\ndef p_exportDecl(p):\n    '''exportDecl : TOKEXPORT VAR LPAREN DOT DOT RPAREN SEMICOLON\n                  | TOKEXPORT VAR SEMICOLON\n                  | TOKEXPORT VAR COLONCOLON STAR SEMICOLON'''\n    p[0] = p[2]\n\ndef p_exportDecls(p):\n    '''exportDecls :\n                   | exportDecls exportDecl'''\n\ndef p_interfaceFormalParam(p):\n    '''interfaceFormalParam : TOKTYPE VAR\n                            | VAR interfaceHashParams\n                            | NUM\n                            | TOKNUMERIC TOKTYPE VAR'''\n    if len(p) == 2:\n        p[0] = p[1]\n    elif len(p) == 3:\n        p[0] = p[2]\n    else:\n        p[0] = p[3]\n\ndef p_interfaceFormalParams(p):\n    '''interfaceFormalParams : interfaceFormalParam\n                             | interfaceFormalParams COMMA interfaceFormalParam'''\n    if len(p) == 2:\n        p[0] = [p[1]]\n    else:\n        p[0] = p[1] + [p[3]]\n\ndef p_interfaceHashParams(p):\n    '''interfaceHashParams :\n                           | HASH LPAREN interfaceFormalParams RPAREN'''\n    if len(p) == 5:\n        p[0] = p[3]\n    else:\n        p[0] = []\n\ndef p_instanceAttributes(p):\n    '''instanceAttributes :\n                          | instanceAttributes LPARENSTAR attrSpecs RPARENSTAR'''\n\ndef p_subinterfaceDecl(p):\n    '''subinterfaceDecl : instanceAttributes TOKINTERFACE type VAR SEMICOLON\n                        | type VAR SEMICOLON'''\n    if len(p) == 6:\n        name = p[4]\n        t = p[3]\n    elif len(p) == 5:\n        name = p[3]\n        t = p[2]\n    else:\n        name = p[2]\n        t = p[1]\n    p[0] = AST.Interface(t.name, t.params, [], name, globalfilename) \n\ndef p_parenthesizedFormalParams(p):\n    '''parenthesizedFormalParams : \n                                 |  LPAREN RPAREN\n                                 |  LPAREN moduleFormalParams RPAREN'''\n    if len(p) < 4:\n        p[0] = []\n    else:\n        p[0] = p[2]\n\ndef p_methodDecl(p):\n    '''methodDecl : TOKMETHOD type VAR parenthesizedFormalParams SEMICOLON'''\n    p[0] = AST.Method(p[3], p[2], p[4])\n\ndef p_interfaceStmt(p):\n    '''interfaceStmt : subinterfaceDecl\n                     | methodDecl '''\n    p[0] = p[1]\n\ndef p_interfaceStmts(p):\n    '''interfaceStmts :\n                      | interfaceStmts interfaceStmt'''\n    if len(p) == 3:\n        p[0] = p[1] + [p[2]]\n    else:\n        p[0] = []\n\ndef p_interfaceDecl(p):\n    '''interfaceDecl : instanceAttributes TOKINTERFACE VAR interfaceHashParams SEMICOLON interfaceStmts TOKENDINTERFACE colonVar'''\n    interface = AST.Interface(p[3], p[4], p[6], None, globalfilename)\n    p[0] = interface\n\n\n# the token '[' signifies an array type \ndef p_arrayDecl(p):\n    '''arrayDecl : type VAR LBRACKET NUM RBRACKET'''\n    arr_t = AST.Type(p[3],p[1])\n    p[0] = AST.Variable(p[2], arr_t, None)\n\ndef p_varDecl(p):\n    '''varDecl : arrayDecl\n               | type VAR'''\n    if len(p)==3:\n        p[0] = AST.Variable(p[2], p[1], None)\n    else:\n        p[0] = p[1]\n\ndef p_params(p):\n    '''params : expressions\n              | TOKSEQ fsmStmts TOKENDSEQ'''\n\ndef p_lvalue(p):\n    '''lvalue : VAR\n              | LPAREN lvalue RPAREN\n              | lvalue DOT VAR\n              | TOKACTION fsmStmts TOKENDACTION\n              | lvalue LBRACKET expression RBRACKET\n              | lvalue LBRACKET expression COLON expression RBRACKET\n              | TOKMATCH pattern'''\n\ndef p_varAssign1(p):\n    '''varAssign1 : TOKLET VAR EQUAL expression\n                  | TOKLET VAR LARROW expression'''\n    p[0] = AST.Variable(p[2], None, p[4])\n\ndef p_varAssign2(p):\n    '''varAssign2 : type VAR EQUAL expression\n                  | type VAR LBRACKET expression RBRACKET EQUAL expression\n                  | type VAR LBRACKET expression RBRACKET LBRACKET NUM RBRACKET EQUAL expression\n                  | type VAR LARROW expression'''\n    p[0] = AST.Variable(p[2], p[1], p[4])\n\ndef p_varAssign3(p):\n    '''varAssign3 : lvalue EQUAL expression\n                  | lvalue LEQ expression\n                  | lvalue LARROW expression'''\n    p[0] = AST.Variable(p[2], p[1], None)\n\ndef p_varAssign(p):\n    '''varAssign : varAssign1\n                 | varAssign2\n                 | varAssign3'''\n\ndef p_ruleCond(p):\n    '''ruleCond : LPAREN expression RPAREN'''\n\ndef p_implicitCond(p):\n    '''implicitCond :\n                    | TOKIF LPAREN expression RPAREN'''\n\ndef p_rule(p):\n    '''rule : TOKRULE VAR implicitCond SEMICOLON expressionStmts TOKENDRULE colonVar\n            | TOKRULE VAR ruleCond implicitCond SEMICOLON expressionStmts TOKENDRULE colonVar'''\n\ndef p_ifStmt(p):\n    '''ifStmt : TOKIF LPAREN expression RPAREN fsmStmt\n              | TOKIF LPAREN expression RPAREN fsmStmt TOKELSE fsmStmt'''\n\ndef p_caseItem(p):\n    '''caseItem : expressions COLON expressionStmt'''\n\ndef p_caseItems(p):\n    '''caseItems :\n                 | caseItems caseItem'''\n\ndef p_defaultItem(p):\n    '''defaultItem :\n                   | TOKDEFAULT expressionStmt\n                   | TOKDEFAULT COLON expressionStmt'''\n\ndef p_caseStmt(p):\n    '''caseStmt : TOKCASE LPAREN expression RPAREN caseItems defaultItem TOKENDCASE\n                | TOKCASE LPAREN expression RPAREN TOKMATCHES caseItems defaultItem TOKENDCASE'''\n\ndef p_forStmt(p):\n    '''forStmt : TOKFOR LPAREN varAssign SEMICOLON expression SEMICOLON varAssign RPAREN fsmStmt'''\n\ndef p_whenStmt(p):\n    '''whenStmt : TOKWHEN LPAREN expression RPAREN LPAREN expression RPAREN SEMICOLON'''\n\ndef p_beginStmt(p):\n    '''beginStmt : TOKBEGIN expressionStmts TOKEND'''\n\ndef p_expressionStmt(p):\n    '''expressionStmt : TOKRETURN expression SEMICOLON\n                      | fsmStmtDef\n                      | whenStmt\n                      | lvalue SEMICOLON\n                      | lvalue LPAREN params RPAREN DOT expression SEMICOLON\n                      | lvalue LPAREN params RPAREN SEMICOLON\n                      | BUILTINVAR LPAREN expressions RPAREN SEMICOLON\n                      | varAssign SEMICOLON\n                      | varDecl SEMICOLON\n                      | beginStmt\n                      | ifStmt\n                      | caseStmt\n                      | forStmt\n                      | interfaceDef\n                      | functionDef\n                      | methodDef\n                      | moduleDef\n                      | TOKACTION colonVar expressionStmts TOKENDACTION colonVar\n                      | TOKACTIONVALUE colonVar expressionStmts TOKENDACTIONVALUE colonVar\n                      | typeDef\n                      | instanceAttributes rule\n                      | TOKACTION fsmStmts TOKENDACTION\n                      '''\n    if parseTrace:\n        print('ENDSTATEMENT', [pitem for pitem in p])\n\ndef p_expressionStmts(p):\n    '''expressionStmts : expressionStmts expressionStmt\n                       | '''\n\ndef p_provisos(p):\n    '''provisos :\n                | TOKPROVISOS LPAREN typeParams RPAREN'''\n    if len(p) == 5:\n        p[0] = p[3]\n    else:\n        p[0] = []\n\ndef p_endFunction(p):\n    '''endFunction : TOKENDFUNCTION colonVar'''\n\ndef p_functionBody(p):\n    '''functionBody : SEMICOLON expressionStmts endFunction''' \n\ndef p_functionValue(p):\n    '''functionValue : EQUAL expression SEMICOLON'''\n\ndef p_functionFormal(p):\n    '''functionFormal : type VAR\n                      | VAR'''\n\ndef p_functionFormals(p):\n    '''functionFormals :\n                       | functionFormal\n                       | functionFormals COMMA functionFormal '''\ndef p_fsmStmt(p):\n    '''fsmStmt : TOKSEQ fsmStmts TOKENDSEQ\n               | TOKPAR fsmStmts TOKENDPAR\n               | TOKWHILE ruleCond fsmStmt\n               | expressionStmt'''\n\ndef p_fsmStmts(p):\n    '''fsmStmts : fsmStmt fsmStmts\n                | fsmStmt'''\n\ndef p_fsmStmtDef(p):\n    '''fsmStmtDef : TOKSTMT VAR EQUAL fsmStmts SEMICOLON'''\n\ndef p_functionDef(p):\n    '''functionDef : instanceAttributes TOKFUNCTION type VAR LPAREN functionFormals RPAREN provisos functionBody\n                   | instanceAttributes TOKFUNCTION      VAR LPAREN functionFormals RPAREN provisos functionBody\n                   | instanceAttributes TOKFUNCTION type VAR LPAREN functionFormals RPAREN provisos functionValue\n                   | instanceAttributes TOKFUNCTION      VAR LPAREN functionFormals RPAREN provisos functionValue\n                   '''\n    if len(p) == 9:\n        # no type\n        p[0] = AST.Function(p[3], None, p[5])\n    else:\n        p[0] = AST.Function(p[4], p[3], p[6])\n\ndef p_methodDef(p):\n    '''methodDef : TOKMETHOD type VAR LPAREN functionFormals RPAREN implicitCond SEMICOLON methodBody\n                 | TOKMETHOD type VAR implicitCond SEMICOLON methodBody\n                 | TOKMETHOD type VAR EQUAL expression SEMICOLON\n                 | TOKMETHOD type VAR LPAREN functionFormals RPAREN EQUAL expression SEMICOLON\n                 | TOKMETHOD VAR LPAREN functionFormals RPAREN EQUAL expression SEMICOLON\n                 | TOKMETHOD VAR EQUAL expression SEMICOLON'''\n    returnType = p[2]\n    name = p[3]\n    params = []\n    p[0] = AST.Method(name, returnType, params)\n\ndef p_methodBody(p):\n    '''methodBody : expressionStmts endMethod\n                  | endMethod'''\n\ndef p_endMethod(p):\n    '''endMethod : TOKENDMETHOD colonVar'''\n\ndef p_unionMember(p):\n    '''unionMember : type VAR SEMICOLON\n                   | subStruct VAR SEMICOLON\n                   | subUnion VAR SEMICOLON'''\n\ndef p_subStruct(p):\n    '''subStruct : TOKSTRUCT LBRACE structMembers RBRACE'''\n\ndef p_structMembers(p):\n    '''structMembers :\n                     | structMember\n                     | structMembers structMember'''\n    if len(p) == 1:\n        p[0] = []\n    elif len(p) == 2:\n        p[0] = [p[1]]\n    elif len(p) == 3:\n        p[0] = p[1] + [p[2]]\n\ndef p_structMember(p):\n    '''structMember : type VAR SEMICOLON\n                    | subUnion VAR SEMICOLON'''\n    p[0] = AST.StructMember(p[1], p[2])\n\ndef p_subUnion(p):\n    '''subUnion : TOKUNION TOKTAGGED LBRACE unionMembers RBRACE'''\n\ndef p_unionMembers(p):\n    '''unionMembers : unionMember\n                    | unionMembers unionMember'''\n\ndef p_taggedUnionDef(p):\n    '''taggedUnionDef : TOKUNION TOKTAGGED LBRACE unionMembers RBRACE'''\n\ndef p_structDef(p):\n    '''structDef : TOKSTRUCT LBRACE structMembers RBRACE'''\n    p[0] = AST.Struct(p[3])\n\ndef p_enumRange(p):\n    '''enumRange : \n                 | LBRACKET NUM RBRACKET\n                 | LBRACKET NUM COLON NUM RBRACKET'''\n                 \n\ndef p_enumElement(p):\n    '''enumElement : VAR enumRange\n                   | VAR enumRange EQUAL NUM'''\n    if len(p) == 3:\n        p[0] = [p[1], None]\n    else:\n        p[0] = [p[1], p[4]]\n\ndef p_enumElements(p):\n    '''enumElements : enumElement\n                    | enumElements COMMA enumElement'''\n    if len(p) == 2:\n        p[0] = [p[1]]\n    else:\n        p[0] = p[1] + [p[3]]\n\ndef p_enumDef(p):\n    '''enumDef : TOKENUM LBRACE enumElements RBRACE'''\n    p[0] = AST.Enum(p[3])\n\ndef p_vardot(p):\n    '''vardot : VAR\n            | vardot DOT VAR'''\n    if len(p) == 2:\n        p[0] = p[1]\n    else:\n        p[0] = p[3]\n\ndef p_vars(p):\n    '''vars : vardot\n            | vars COMMA vardot'''\n    if len(p) == 2:\n        p[0] = [p[1]]\n    else:\n        p[0] = p[1] + [p[3]]\n\ndef p_deriving(p):\n    '''deriving : \n                | TOKDERIVING LPAREN vars RPAREN'''\n    if len(p) == 5:\n        p[0] = p[3]\n    else:\n        p[0] = []\n\ndef p_macroDef(p):\n    '''macroDef : TOKTICKDEFINE VAR expression'''\n\n\ndef p_typeDefBody(p):\n    '''typeDefBody : taggedUnionDef\n                   | structDef\n                   | enumDef\n                   | type'''\n    p[0] = p[1]\n\ndef p_typeDef(p):\n    '''typeDef : TOKTYPEDEF typeDefBody VAR deriving SEMICOLON\n               | TOKTYPEDEF typeDefBody VAR interfaceHashParams deriving SEMICOLON'''\n    if len(p) == 6:\n        p[0] = AST.TypeDef(p[2], p[3], [])\n    else:\n        p[0] = AST.TypeDef(p[2], p[3], p[4])\n\n\ndef p_interfaceDef(p):\n    '''interfaceDef : TOKINTERFACE type VAR SEMICOLON expressionStmts TOKENDINTERFACE colonVar\n                    | TOKINTERFACE type VAR EQUAL expression SEMICOLON\n                    | TOKINTERFACE VAR EQUAL expression SEMICOLON'''\n    if parseTrace:\n        print('ENDINTERFACE', [pitem for pitem in p])\n\ndef p_formalParam(p):\n    '''formalParam : type VAR'''\n    param = AST.Param(p[2], p[1])\n    p[0] = param\n\ndef p_moduleFormalParams(p):\n    '''moduleFormalParams : formalParam\n                          | TOKFUNCTION type VAR parenthesizedFormalParams\n                          | moduleFormalParams COMMA formalParam\n                          |'''\n    if len(p) == 1:\n        p[0] = []\n    elif len(p) == 2:\n        p[0] = [p[1]]\n    elif len(p) == 5:\n        p[0] = p[2]\n    elif len(p) == 4:\n        p[0] = p[1] + [p[3]]\n\ndef p_moduleFormalArg(p):\n    '''moduleFormalArg : instanceAttributes type\n                       | instanceAttributes type VAR'''\n\ndef p_moduleFormalArgs(p):\n    '''moduleFormalArgs :\n                        | moduleFormalArg\n                        | moduleFormalArgs COMMA moduleFormalArg'''\n    if len(p) == 2:\n        p[0] = [p[1]]\n    else:\n        p[0] = p[1] + [p[3]]\n\ndef p_moduleParamsArgs(p):\n    '''moduleParamsArgs :\n                        | HASH LPAREN moduleFormalParams RPAREN\n                        | HASH LPAREN moduleFormalParams RPAREN LPAREN moduleFormalArgs RPAREN\n                        | LPAREN moduleFormalArgs RPAREN'''\n    if len(p) == 8:\n        p[0] = [ p[3], p[6] ]\n    elif len(p) == 5:\n        p[0] = [ p[3], None ]\n    else:\n        p[0] = [ None, p[2] ]\n\ndef p_attrSpec(p):\n    '''attrSpec : VAR\n                | VAR EQUAL expression'''\n\ndef p_attrSpecs(p):\n    '''attrSpecs : attrSpec\n                 | attrSpecs COMMA attrSpec'''\n\ndef p_moduleContext(p):\n    '''moduleContext : \n                     | LBRACKET VAR RBRACKET'''\n    if len(p) > 2:\n        p[0] = p[2]\n\ndef p_moduleDefHeader(p):\n    '''moduleDefHeader : instanceAttributes TOKMODULE moduleContext VAR moduleParamsArgs provisos SEMICOLON'''\n    p[0] = [p[3], p[4], p[5][0], p[5][1], p[6]]\n\ndef p_moduleDef(p):\n    '''moduleDef : moduleDefHeader expressionStmts TOKENDMODULE colonVar'''\n    if parseTrace:\n        print('ENDMODULE', [pitem for pitem in p])\n    p[0] = AST.Module(p[1][0], p[1][1], p[1][2], p[1][3], p[1][4], p[2])\n\ndef p_importBviDef(p):\n    '''importBviDef : TOKIMPORT STR VAR EQUAL bviModuleDef\n            | TOKIMPORT STR TOKFUNCTION TOKUACTION VAR LPAREN functionFormals RPAREN SEMICOLON'''\n    p[0] = p[5]\n    if len(p) > 6:\n        p[0] = AST.Module(None, p[5], None, None, None, None)\n\ndef p_bviModuleDef(p):\n    '''bviModuleDef : instanceAttributes TOKMODULE moduleContext VAR moduleParamsArgs provisos SEMICOLON bviExpressionStmts TOKENDMODULE colonVar'''\n    p[0] = AST.Module(p[3], p[4], p[5][0], p[5][1], p[6], p[8])\n\ndef p_bviExpressionStmts(p):\n    '''bviExpressionStmts : bviExpressionStmts bviExpressionStmt\n                          | bviExpressionStmt '''\n\ndef p_bviExpressionStmt(p):\n    '''bviExpressionStmt : TOKRETURN expression SEMICOLON\n                         | fsmStmtDef\n                         | whenStmt\n                         | lvalue SEMICOLON\n                         | lvalue LPAREN expressions RPAREN SEMICOLON\n                         | BUILTINVAR LPAREN expressions RPAREN SEMICOLON\n                         | varAssign SEMICOLON\n                         | varDecl SEMICOLON\n                         | beginStmt\n                         | ifStmt\n                         | caseStmt\n                         | forStmt\n                         | bviInterfaceDef\n                         | functionDef\n                         | bviMethodDef\n                         | moduleDef\n                         | TOKACTION colonVar expressionStmts TOKENDACTION colonVar\n                         | typeDef\n                         | instanceAttributes rule\n                         | TOKSEQ fsmStmts TOKENDSEQ\n                         | TOKPORT VAR EQUAL expression SEMICOLON\n                         | TOKPARAMETER VAR EQUAL expression SEMICOLON\n                         | TOKDEFAULT_CLOCK VAR LPAREN RPAREN SEMICOLON\n                         | TOKDEFAULT_CLOCK VAR LPAREN VAR RPAREN SEMICOLON\n                         | TOKDEFAULT_RESET VAR LPAREN RPAREN SEMICOLON\n                         | TOKDEFAULT_RESET TOKNO_RESET SEMICOLON\n                         | TOKDEFAULT_RESET VAR LPAREN VAR RPAREN SEMICOLON\n                         | TOKINPUT_CLOCK VAR LPAREN VAR RPAREN EQUAL expression SEMICOLON\n                         | TOKINPUT_RESET VAR LPAREN VAR RPAREN EQUAL expression SEMICOLON\n                         | TOKINPUT_RESET VAR LPAREN RPAREN EQUAL expression SEMICOLON\n                         | TOKOUTPUT_CLOCK VAR LPAREN VAR RPAREN SEMICOLON\n                         | TOKOUTPUT_RESET VAR LPAREN VAR RPAREN SEMICOLON\n                         | TOKSCHEDULE LPAREN vars RPAREN schedOp LPAREN vars RPAREN SEMICOLON'''\n\ndef p_schedOp(p):\n    '''schedOp : TOKCF\n               | TOKC\n               | TOKSB\n               | TOKSBR'''\n\ndef p_bviInterfaceDef(p):\n    '''bviInterfaceDef : TOKINTERFACE type VAR SEMICOLON bviExpressionStmts TOKENDINTERFACE colonVar\n                       | TOKINTERFACE type VAR EQUAL expression SEMICOLON\n                       | TOKINTERFACE VAR EQUAL expression SEMICOLON'''\n\ndef p_bviMethodAttributes(p):\n    '''bviMethodAttributes :\n                           | bviMethodAttributes bviMethodAttribute'''\ndef p_bviMethodAttribute(p):\n    '''bviMethodAttribute :\n                          | TOKENABLE LPAREN instanceAttributes VAR RPAREN\n                          | TOKCLOCKED_BY LPAREN instanceAttributes VAR RPAREN\n                          | TOKRESET_BY LPAREN instanceAttributes VAR RPAREN'''\n\ndef p_bviMethodDef(p):\n    '''bviMethodDef : TOKMETHOD VAR LPAREN VAR RPAREN bviMethodAttributes SEMICOLON\n                    | TOKMETHOD VAR VAR LPAREN RPAREN bviMethodAttributes SEMICOLON'''\n\ndef p_instanceDeclStmt(p):\n    '''instanceDeclStmt : varAssign SEMICOLON\n                        | functionDef\n                        | moduleDef'''\n    p[0] = p[1]\n\ndef p_instanceDeclStmts(p):\n    '''instanceDeclStmts : \n                         | instanceDeclStmt\n                         | instanceDeclStmts instanceDeclStmt'''\n\ndef p_instanceDecl(p):\n    '''instanceDecl : TOKINSTANCE VAR HASH LPAREN typeParams RPAREN provisos SEMICOLON instanceDeclStmts TOKENDINSTANCE'''\n    p[0] = AST.TypeclassInstance(p[2], p[5], p[7], p[9])\n\ndef p_typeClassDeclStmts(p):\n    '''typeClassDeclStmts : \n                          | moduleDefHeader'''\n\ndef p_typeClassDecl(p):\n    '''typeClassDecl : TOKTYPECLASS VAR HASH LPAREN interfaceFormalParams RPAREN provisos SEMICOLON typeClassDeclStmts TOKENDTYPECLASS'''\n    p[0] = AST.Typeclass(p[2])\n\nglobalimports = []\nglobalfilename = None\n\ndef p_packageStmt(p):\n    '''packageStmt : interfaceDecl\n                   | typeClassDecl\n                   | functionDef\n                   | instanceDecl\n                   | varDecl SEMICOLON\n                   | varAssign SEMICOLON\n                   | moduleDef\n                   | macroDef\n                   | typeDef\n                   | importBviDef'''\n    globalv.add_new(p[1])\n\ndef p_packageStmts(p):\n    '''packageStmts :\n                    | packageStmts packageStmt exportDecls'''\n\ndef p_beginPackage(p):\n    '''beginPackage :\n                    | TOKPACKAGE VAR SEMICOLON'''\n\ndef p_endPackage(p):\n    '''endPackage :\n                  | TOKENDPACKAGE colonVar'''\n\ndef p_package(p):\n    '''package : beginPackage exportDecls importDecls packageStmts exportDecls endPackage'''\n    p[0] = p[4]\n\ndef syntax_parse(argdata, inputfilename, bsvdefines, bsvpath):\n    global globalfilename\n    globalfilename = inputfilename\n    data = bsvpreprocess.preprocess(inputfilename, argdata + '\\n', bsvdefines, bsvpath)\n    lexer = lex.lex(errorlog=lex.NullLogger())\n    parserdir=scripthome+'/syntax'\n    if not os.path.isdir(parserdir):\n        os.makedirs(parserdir)\n    if not (parserdir in sys.path):\n        sys.path.append(parserdir)\n    parser = yacc.yacc(optimize=1,errorlog=yacc.NullLogger(),outputdir=parserdir,debugfile=parserdir+'/parser.out')\n    if noisyFlag:\n        print('Parsing:', inputfilename)\n    if parseDebugFlag:\n        return parser.parse(data,debug=1)\n    return  parser.parse(data)\n\ndef generate_bsvcpp(filelist, project_dir, bsvdefines, interfaces, bsvpath):\n    for inputfile in filelist:\n        syntax_parse(open(inputfile).read(), inputfile, bsvdefines, bsvpath)\n    ## code generation pass\n    ilist = []\n    for i in interfaces:\n        ifc = globalv.globalvars.get(i)\n        if not ifc:\n            print('Connectal: Unable to locate the interface:', i)\n            for keys in globalv.globalvars:\n                print('    ', keys)\n            sys.exit(1)\n        ifc = ifc.instantiate(dict(zip(ifc.params, ifc.params)))\n        ilist.append(ifc)\n        for ditem in ifc.decls:\n            for pitem in ditem.params:\n                thisType = pitem.type\n                p = globalv.globalvars.get(thisType.name)\n                if p and thisType.params and p.params:\n                    myName = '%sL_%s_P' % (thisType.name, '_'.join([t.name for t in thisType.params if t]))\n                    pitem.oldtype = pitem.type\n                    pitem.type = AST.Type(myName, [])\n                    if not globalv.globalvars.get(myName):\n                        globalv.add_new(AST.TypeDef(p.tdtype.instantiate(dict(zip(p.params, thisType.params))), myName, []))\n    jsondata = AST.serialize_json(ilist, globalimports, bsvdefines)\n    if project_dir:\n        cppgen.generate_cpp(project_dir, noisyFlag, jsondata)\n        bsvgen.generate_bsv(project_dir, noisyFlag, False, jsondata)\n    \nif __name__=='__main__':\n    if len(sys.argv) == 1:\n        parserdir=scripthome+'/syntax'\n        sys.path.append(parserdir)\n        if not os.path.isdir(parserdir):\n            os.makedirs(parserdir)\n        parser = yacc.yacc(outputdir=parserdir,debugfile=parserdir+'/parser.out')\n        import parsetab\n        sys.exit(0)\n    ifitems = []\n    t = os.environ.get('INTERFACES')\n    if t:\n        t = t.split()\n        for item in t:\n            if item not in ifitems:\n                ifitems.append(item)\n    deflist = []\n    t = os.environ.get('BSVDEFINES_LIST')\n    if t:\n        deflist = t.split()\n    noisyFlag = os.environ.get('D') == '1'\n    if os.environ.get('D'):\n        parseDebugFlag=True\n    if noisyFlag:\n        parseTrace=True\n    project_dir =  os.environ.get('DTOP')\n    tmp = os.environ.get('PROTODEBUG')\n    if tmp:\n        print('JSONNN', tmp)\n        j2file = open(tmp).read()\n        jsondata = json.loads(j2file)\n        cppgen.generate_cpp(project_dir, noisyFlag, jsondata)\n        bsvgen.generate_bsv(project_dir, noisyFlag, True, jsondata)\n    else:\n        bsvpath = os.environ.get('BSVPATH', []).split(':')\n        generate_bsvcpp(sys.argv[1:], project_dir, deflist, ifitems, bsvpath)\n\n"
  },
  {
    "path": "scripts/topgen.py",
    "content": "#!/usr/bin/env python3\n## Copyright (c) 2013-2014 Quanta Research Cambridge, Inc.\n\n## Permission is hereby granted, free of charge, to any person\n## obtaining a copy of this software and associated documentation\n## files (the \"Software\"), to deal in the Software without\n## restriction, including without limitation the rights to use, copy,\n## modify, merge, publish, distribute, sublicense, and/or sell copies\n## of the Software, and to permit persons to whom the Software is\n## furnished to do so, subject to the following conditions:\n\n## The above copyright notice and this permission notice shall be\n## included in all copies or substantial portions of the Software.\n\n## THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n## EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n## MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n## NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n## BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n## ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n## CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n## SOFTWARE.\nfrom __future__ import print_function\n\nimport os, sys, shutil, string\nimport argparse\nimport util\n\ndef newArgparser():\n    argparser = argparse.ArgumentParser(\"Generate Top.bsv for an project.\")\n    argparser.add_argument('--project-dir', help='project directory')\n    argparser.add_argument('--filename', default='Top.bsv', help='name of generated file')\n    argparser.add_argument('--topname', default='mkConnectalTop', help='name of generated module')\n    argparser.add_argument('--ifcnames', default='IfcNames', help='name of interface names enum type and file')\n    argparser.add_argument('--pintype', default=[], help='Type of pins interface', action='append')\n    argparser.add_argument('--interface', default=[], help='exported interface declaration', action='append')\n    argparser.add_argument('--portalclock', help='Portal clock source', default=None)\n    argparser.add_argument('--importfiles', default=[], help='added imports', action='append')\n    argparser.add_argument('--portname', default=[], help='added portal names to enum list', action='append')\n    argparser.add_argument('--wrapper', default=[], help='exported wrapper interfaces', action='append')\n    argparser.add_argument('--proxy', default=[], help='exported proxy interfaces', action='append')\n    argparser.add_argument('--memread', default=[], help='memory read interfaces', action='append')\n    argparser.add_argument('--memwrite', default=[], help='memory read interfaces', action='append')\n    argparser.add_argument('--cnoc', help='generate mkCnocTop', action='store_true')\n    argparser.add_argument('--integratedIndication', help='indication pipes instantiated in user module', action='store_true')\n    return argparser\n\nargparser = newArgparser()\n\ntopTemplate='''\nimport ConnectalConfig::*;\nimport Vector::*;\nimport BuildVector::*;\nimport Portal::*;\nimport CtrlMux::*;\nimport HostInterface::*;\nimport Connectable::*;\nimport MemReadEngine::*;\nimport MemWriteEngine::*;\nimport ConnectalMemTypes::*;\nimport MemServer::*;\n`include \"ConnectalProjectConfig.bsv\"\nimport %(ifcnames)s::*;\n%(generatedImport)s\n\n%(pinsInterfaceDecl)s\n\n`ifndef IMPORT_HOSTIF\n(* synthesize *)\n`endif\nmodule %(topname)s\n`ifdef IMPORT_HOSTIF // no synthesis boundary\n      #(HostInterface host)\n`else\n`ifdef IMPORT_HOST_CLOCKS // enables synthesis boundary\n       #(Clock derivedClockIn, Reset derivedResetIn)\n`else\n// otherwise no params\n`endif\n`endif\n       (%(moduleParam)s);\n   Clock defaultClock <- exposeCurrentClock();\n   Reset defaultReset <- exposeCurrentReset();\n`ifdef IMPORT_HOST_CLOCKS // enables synthesis boundary\n   HostInterface host = (interface HostInterface;\n                           interface Clock derivedClock = derivedClockIn;\n                           interface Reset derivedReset = derivedResetIn;\n                         endinterface);\n`endif\n%(pipeInstantiate)s\n\n%(portalInstantiate)s\n%(connectInstantiate)s\n\n   Vector#(%(portalCount)s,StdPortal) portals;\n%(portalList)s\n   let ctrl_mux <- mkSlaveMux(portals);\n   Vector#(NumWriteClients,MemWriteClient#(DataBusWidth)) nullWriters = replicate(null_mem_write_client());\n   Vector#(NumReadClients,MemReadClient#(DataBusWidth)) nullReaders = replicate(null_mem_read_client());\n   interface interrupt = getInterruptVector(portals);\n   interface slave = ctrl_mux;\n   interface readers = take(%(portalReaders)s);\n   interface writers = take(%(portalWriters)s);\n`ifdef TOP_SOURCES_PORTAL_CLOCK\n   interface portalClockSource = %(portalclock)s;\n`endif\n%(pinsInterface)s\n%(exportedInterfaces)s\nendmodule : %(topname)s\n%(exportedNames)s\n'''\n\nifcnamesTemplate='''\ntypedef enum {%(ifcnames)sNone=0,\n%(enumList)s\n} %(ifcnames)s deriving (Eq,Bits);\n'''\n\ntopNocTemplate='''\nimport ConnectalConfig::*;\nimport Vector::*;\nimport BuildVector::*;\nimport Portal::*;\nimport CnocPortal::*;\nimport Connectable::*;\nimport HostInterface::*;\nimport ConnectalMemTypes::*;\n`include \"ConnectalProjectConfig.bsv\"\nimport %(ifcnames)s::*;\n%(generatedImport)s\n\n%(generatedTypedefs)s\n\n`ifndef IMPORT_HOSTIF\n(* synthesize *)\n`endif\nmodule mkCnocTop\n`ifdef IMPORT_HOSTIF\n       #(HostInterface host)\n`else\n`ifdef IMPORT_HOST_CLOCKS // enables synthesis boundary\n       #(Clock derivedClockIn, Reset derivedResetIn)\n`else\n// otherwise no params\n`endif\n`endif\n       (%(moduleParam)s);\n   Clock defaultClock <- exposeCurrentClock();\n   Reset defaultReset <- exposeCurrentReset();\n`ifdef IMPORT_HOST_CLOCKS // enables synthesis boundary\n   HostInterface host = (interface HostInterface;\n                           interface Clock derivedClock = derivedClockIn;\n                           interface Reset derivedReset = derivedResetIn;\n                         endinterface);\n`endif\n%(pipeInstantiate)s\n\n%(portalInstantiate)s\n%(connectInstantiate)s\n\n%(portalList)s\n   Vector#(NumWriteClients,MemWriteClient#(DataBusWidth)) nullWriters = replicate(null_mem_write_client());\n   Vector#(NumReadClients,MemReadClient#(DataBusWidth)) nullReaders = replicate(null_mem_read_client());\n\n   interface requests = %(requestList)s;\n   interface indications = %(indicationList)s;\n   interface readers = take(%(portalReaders)s);\n   interface writers = take(%(portalWriters)s);\n`ifdef TOP_SOURCES_PORTAL_CLOCK\n   interface portalClockSource = %(portalclock)s;\n`endif\n%(pinsInterface)s\n%(exportedInterfaces)s\nendmodule : mkCnocTop\n%(exportedNames)s\n'''\n\ntopEnumTemplate='''\ntypedef enum {NoInterface, %(enumList)s} %(ifcnames)s;\n'''\n\nportalTemplate = '''   PortalCtrlMemSlave#(SlaveControlAddrWidth,SlaveDataBusWidth) ctrlPort_%(count)s <- mkPortalCtrlMemSlave(extend(pack(%(enumVal)s)), %(ifcName)s.intr);\n   let memslave_%(count)s <- mkMemMethodMux%(slaveType)s(ctrlPort_%(count)s.memSlave,%(ifcName)s.%(itype)s);\n   portals[%(count)s] = (interface MemPortal;\n       interface PhysMemSlave slave = memslave_%(count)s;\n       interface ReadOnly interrupt = ctrlPort_%(count)s.interrupt;\n       interface WriteOnly num_portals = ctrlPort_%(count)s.num_portals;\n       endinterface);'''\n\nportalNocTemplate = '''   let %(ifcNameNoc)s <- mkPortalMsg%(direction)s(extend(pack(%(enumVal)s)), %(ifcName)s.%(itype)s%(messageSize)s);'''\n\ndef addPortal(outputPrefix, enumVal, ifcName, direction):\n    global portalCount\n    iName = ifcName + '.portalIfc'\n    if outputPrefix != '':\n        iName = outputPrefix + ifcName\n    portParam = {'count': portalCount, 'enumVal': enumVal, 'ifcName': iName, 'ifcNameNoc': ifcName + 'Noc', 'direction': direction}\n    if direction == 'Request':\n        requestList.append('%(ifcNameNoc)s' % portParam)\n        portParam['itype'] = 'requests'\n        portParam['slaveType'] = 'In'\n        portParam['intrParam'] = ''\n        portParam['messageSize'] = ''\n    else:\n        indicationList.append('%(ifcNameNoc)s' % portParam)\n        portParam['itype'] = 'indications'\n        portParam['slaveType'] = 'Out'\n        portParam['intrParam'] = ', %(ifcName)s.intr' % portParam\n        portParam['messageSize'] = ', %(ifcName)s.messageSize' % portParam\n    p = portalNocTemplate if options.cnoc else portalTemplate\n    portalList.append(p % portParam)\n    portalCount = portalCount + 1\n\nclass iReq:\n    def __init__(self):\n        self.inst = ''\n        self.args = []\n\nmemShareInst = '''   SharedMemoryPortalConfigInput%(tparam)s l%(modname)sCW <- mkSharedMemoryPortalConfigInput;'''\n\nmemEngineInst = '''   MemReadEngine#(64,64,2,%(clientCount)s) lSharereadEngine <- mkMemReadEngine();\n   MemWriteEngine#(64,64,2,%(clientCount)s) lSharewriteEngine <- mkMemWriteEngine();'''\n\nmemModuleInstantiation = '''   SharedMemoryPortal#(64) l%(modname)sShare <- mkSharedMemory%(stype)sPortal(l%(modname)s%(number)s.portalIfc,\n           get%(modnamebase)sMessageSize,\n           takeAt(%(clientCount)s, lSharereadEngine.readServers), takeAt(%(clientCount)s, lSharewriteEngine.writeServers));'''\n\nmemConnection = '''   mkConnection(l%(modname)sCW.pipes, l%(modname)sShare.cfg);'''\n\nconnectUser = '''   mkConnection(lSimpleRequestInput.pipes, %(args)s);'''\n\nconnectIndication = '''   mkConnection(l%(usermod)s.inverseIfc, l%(modname)s.methods);'''\n\npipeInstantiation = '''   %(modname)s%(inverse)s%(tparam)s l%(modname)s%(number)s <- mk%(modname)s%(inverse)s;'''\n\nconnectInstantiation = '''   mkConnection(l%(modname)s%(number)s.pipes, l%(userIf)s);'''\n\ndef instMod(pmap, args, modname, modext, constructor, tparam, memFlag, inverseFlag):\n    global clientCount\n    if not modname:\n        return\n    map = pmap.copy()\n    pmap['tparam'] = tparam\n    pmap['modname'] = modname + modext\n    pmap['modnamebase'] = modname\n    tstr = 'S2H'\n    if modext == 'Output':\n        tstr = 'H2S'\n    if modext:\n        args = modname + tstr\n    pmap['args'] = args % pmap\n    if modext:\n        options.portname.append('%s_%s%s%s' % (options.ifcnames, modname, tstr, pmap['number']))\n        pmap['argsConfig'] = modname + memFlag + tstr\n        outputPrefix = ''\n        if modext == 'Output':\n            pmap['stype'] = 'Indication';\n        else:\n            pmap['stype'] = 'Request';\n        if memFlag:\n            if modext == 'Output':\n                pmap['args'] = '';\n            else:\n                pmap['args'] = 'l%(userIf)s' % pmap\n            pmap['clientCount'] = clientCount;\n            pipeInstantiate.append(pipeInstantiation % pmap)\n            pipeInstantiate.append(memShareInst % pmap)\n            portalInstantiate.append(memModuleInstantiation % pmap)\n            connectInstantiate.append(memConnection % pmap)\n            if modext != 'Output':\n                connectInstantiate.append(connectUser % pmap)\n            clientCount += 2\n        elif modext == 'Output':\n            if options.integratedIndication:\n                outputPrefix = 'l' + pmap['usermod'] + '.'\n            else:\n                pipeInstantiate.append(pipeInstantiation % pmap)\n            if inverseFlag:\n                connectInstantiate.append(connectIndication % pmap)\n        else:\n            pipeInstantiate.append(pipeInstantiation % pmap)\n            connectInstantiate.append(connectInstantiation % pmap)\n        if memFlag:\n            options.portname.append('%s_%s%s%s%s' % (options.ifcnames, modname, memFlag, tstr, pmap['number']))\n            addPortal('', options.ifcnames + '_' + pmap['argsConfig'], 'l%(modname)sCW' % pmap, 'Request')\n        else:\n            addPortal(outputPrefix, options.ifcnames + '_' + pmap['args'] + pmap['number'], 'l%(modname)s%(number)s' % pmap, pmap['stype'])\n    else:\n        if not instantiateRequest.get(pmap['modname']):\n            instantiateRequest[pmap['modname']] = iReq()\n            pmap['hostif'] = ''\n            instantiateRequest[pmap['modname']].inst = '   let l%(modname)s <- mk%(modname)s(%(hostif)s%%s);' % pmap\n        instantiateRequest[pmap['modname']].args.append(pmap['args'])\n    if pmap['modname'] not in instantiatedModules:\n        instantiatedModules.append(pmap['modname'])\n    options.importfiles.append(modname)\n\ndef flushModules(key):\n        temp = instantiateRequest.get(key)\n        if temp:\n            portalInstantiate.append(temp.inst % ','.join(temp.args))\n            del instantiateRequest[key]\n\ndef toVectorLiteral(l):\n    if l:\n        return 'vec(%s)' % ', '.join(l)\n    else:\n        return 'nil'\n\ndef appendVectors(l):\n    if len(l) > 1:\n        return 'append(%s,%s)' % (l[0], appendVectors(l[1:]))\n    elif len(l) == 1:\n        return l[0]\n    else:\n        return 'nil'\n\ndef parseParam(pitem, proxy):\n    p = pitem.split(':')\n    pmap = {'tparam': '', 'xparam': '', 'uparam': '', 'memFlag': 'Pipes' if p[0][0] == '/' else '', 'inverse': 'Pipes' if p[0][0] == '!' else ''}\n    pmap['usermod'] = p[0].replace('/','').replace('!','')\n    pmap['name'] = p[1]\n    ind = pmap['usermod'].find('#')\n    if ind > 0:\n        pmap['xparam'] = pmap['usermod'][ind:]\n        pmap['usermod'] = pmap['usermod'][:ind]\n    if len(p) > 2 and p[2]:\n        pmap['uparam'] = p[2] + ', '\n    return pmap\n\nif __name__=='__main__':\n    print('topgen', sys.argv)\n    options = argparser.parse_args()\n\n    if not options.project_dir:\n        print(\"topgen: --project-dir option missing\")\n        sys.exit(1)\n    project_dir = os.path.abspath(os.path.expanduser(options.project_dir))\n    clientCount = 0\n    userFiles = []\n    portalInstantiate = []\n    pipeInstantiate = []\n    connectInstantiate = []\n    instantiateRequest = {}\n    for item in ['Platform%s_MemServerRequestS2H', 'Platform%s_MMURequestS2H', 'Platform%s_MemServerIndicationH2S', 'Platform%s_MMUIndicationH2S']:\n        options.portname.append(item % options.ifcnames)\n    requestList = []\n    indicationList = []\n    portalList = []\n    portalCount = 0\n    instantiatedModules = []\n    exportedNames = []\n    options.importfiles.append('`PinTypeInclude')\n    if options.cnoc:\n        exportedNames.extend(['export mkCnocTop;', 'export NumberOfRequests;', 'export NumberOfIndications;'])\n    else:\n        exportedNames.extend(['export %s;' % options.topname])\n    if options.importfiles:\n        for item in options.importfiles:\n             exportedNames.append('export %s::*;' % item)\n    interfaceList = []\n\n    modcount = {}\n    for pitem in options.proxy:\n        print('options.proxy: %s' % options.proxy)\n        pmap = parseParam(pitem, True)\n        ptemp = pmap['name'].split(',')\n        for pmap['name'] in ptemp:\n            pmap['number'] = ''\n            if (ptemp.count(pmap['name']) > 1):\n                if pmap['name'] in modcount:\n                    pmap['number'] = str(modcount[pmap['name']])\n                    modcount[pmap['name']] += 1\n                else:\n                    modcount[pmap['name']] = 1\n                    pmap['number'] = str(0)\n            instMod(pmap, '', pmap['name'], 'Output', '', '', pmap['memFlag'], pmap['inverse'])\n            argstr = pmap['uparam']\n            if not options.integratedIndication:\n                argstr += ('l%(name)sOutput%(number)s.ifc' if not pmap['inverse'] else '')\n            if pmap['uparam'] and pmap['uparam'][0] == '/':\n                argstr = 'l%(name)sOutput%(number)s.ifc, ' + pmap['uparam'][1:-2]\n            instMod(pmap, argstr, pmap['usermod'], '', '', pmap['xparam'], False, pmap['inverse'])\n            pmap['uparam'] = ''\n    modcount = {}\n    for pitem in options.wrapper:\n        pmap = parseParam(pitem, False)\n        print('options.wrapper: %s %s' % (pitem, pmap))\n        pmap['userIf'] = pmap['name']\n        pmap['name'] = pmap['usermod']\n        pmap['number'] = ''\n        modintf_list = pmap['userIf'].split(',')\n        number = 0\n        for pmap['userIf'] in modintf_list:\n            if len(modintf_list) > 1:\n                pmap['number'] = str(number)\n            number += 1\n            pmap['usermod'] = pmap['userIf'].split('.')[0]\n            if pmap['usermod'] not in instantiatedModules:\n                instMod(pmap, pmap['uparam'], pmap['usermod'], '', '', pmap['xparam'], False, False)\n            flushModules(pmap['usermod'])\n            instMod(pmap, '', pmap['name'], 'Input', '', '', pmap['memFlag'], pmap['inverse'])\n            portalInstantiate.append('')\n    for key in instantiatedModules:\n        flushModules(key)\n    if len(options.pintype) > 1:\n        interfaceList.append('   interface Pins pins;')\n    for i,pitem in enumerate(options.interface):\n        p = pitem.split(':')\n        if len(options.pintype) > 1:\n            interfaceList.append('      interface pins%d = l%s;' % (i, p[1]))\n        else:\n            interfaceList.append('      interface %s = l%s;' % (p[0], p[1]))\n    if len(options.pintype) > 1:\n        interfaceList.append('   endinterface ')\n\n    memory_flag = 'MemServer' in instantiatedModules\n    if clientCount:\n        pipeInstantiate.append(memEngineInst % {'clientCount': clientCount})\n    pintype = '`PinType'\n    pinsInterfaceDecl = ''\n    if len(options.pintype) == 1:\n        pintype = options.pintype[0]\n    elif len(options.pintype) > 1:\n        pintype = 'Pins'\n        subifcs = []\n        for (i,ifc) in enumerate(options.pintype):\n            subifcs.append('    interface %s pins%d;\\n' % (ifc, i))\n        pinsInterfaceDecl = 'interface Pins;\\n %s endinterface\\n' % '\\n'.join(subifcs)\n        exportedNames.append('export Pins(..);')\n    topsubsts = {'enumList': ',\\n'.join(['%s=%d' % (name, i+1) for i,name in enumerate(options.portname)]),\n                 'generatedImport': '\\n'.join(['import %s::*;' % p for p in options.importfiles]),\n                 'generatedTypedefs': '\\n'.join(['typedef %d NumberOfRequests;' % len(requestList),\n                                                 'typedef %d NumberOfIndications;' % len(indicationList)]),\n                 'ifcnames': options.ifcnames,\n                 'pipeInstantiate' : '\\n'.join(sorted(pipeInstantiate)),\n                 'connectInstantiate' : '\\n'.join(sorted(connectInstantiate)),\n                 'portalInstantiate' : '\\n'.join(portalInstantiate),\n                 'portalList': '\\n'.join(portalList),\n                 'portalCount': portalCount,\n                 'requestList': toVectorLiteral(requestList),\n                 'indicationList': toVectorLiteral(indicationList),\n                 'exportedInterfaces' : '\\n'.join(interfaceList),\n                 'exportedNames' : '\\n'.join(exportedNames),\n                 'portalReaders' : appendVectors(options.memread + ['nullReaders']),\n                 'portalWriters' : appendVectors(options.memwrite + ['nullWriters']),\n                 'portalMaster' : 'lMemServer.masters' if memory_flag else 'nil',\n#Use e.g., --interface pins:Ddr3Test.ddr3\n                 'pinsInterface' : '    interface pins = l%(usermod)s.pins;\\n' % pmap if False else '',\n                 'pinsInterfaceDecl' : pinsInterfaceDecl,\n                 'moduleParam' : 'ConnectalTop#(%s)' % pintype if not options.cnoc \\\n                     else 'CnocTop#(NumberOfRequests,NumberOfIndications,PhysAddrWidth,DataBusWidth,%s,NumberOfMasters)' % pintype,\n                 'portalclock': options.portalclock,\n                 'topname': options.topname\n                 }\n    topFilename = project_dir + '/' + options.filename\n    print('Writing:', topFilename)\n    top = util.createDirAndOpen(topFilename, 'w')\n    if options.cnoc:\n        top.write(topNocTemplate % topsubsts)\n    else:\n        top.write(topTemplate % topsubsts)\n    top.close()\n    topFilename = project_dir + '/' + options.ifcnames + '.bsv'\n    print('Writing:', topFilename)\n    top = util.createDirAndOpen(topFilename, 'w')\n    top.write(ifcnamesTemplate % topsubsts)\n    top.close()\n    topFilename = project_dir + '/../jni/topEnum.h'\n    print('Writing:', topFilename)\n    top = util.createDirAndOpen(topFilename, 'w')\n    top.write(topEnumTemplate % topsubsts)\n    top.close()\n"
  },
  {
    "path": "scripts/util.py",
    "content": "##\n## Copyright (c) 2013 Quanta Research Cambridge, Inc.\n\n## Permission is hereby granted, free of charge, to any person\n## obtaining a copy of this software and associated documentation\n## files (the \"Software\"), to deal in the Software without\n## restriction, including without limitation the rights to use, copy,\n## modify, merge, publish, distribute, sublicense, and/or sell copies\n## of the Software, and to permit persons to whom the Software is\n## furnished to do so, subject to the following conditions:\n\n## The above copyright notice and this permission notice shall be\n## included in all copies or substantial portions of the Software.\n\n## THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n## EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n## MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n## NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n## BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n## ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n## CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n## SOFTWARE.\nfrom __future__ import print_function\n\nimport os\nimport filecmp\nimport string\n\ndef createDirAndOpen(f, m):\n    (d, name) = os.path.split(f)\n    if not os.path.exists(d):\n        os.makedirs(d)\n    return open(f, m)\n\ndef replaceIfChanged(name, replacement):\n    if not os.path.isfile(name):\n        print('os.rename(%s, %s)' % (replacement, name))\n        os.rename(replacement, name)\n        return\n    if filecmp.cmp(name, replacement):\n        print('os.unlink(%s)' % replacement)\n        os.unlink(replacement)\n    else:\n        print('os.rename(%s, %s)' % (replacement, name))\n        os.rename(replacement, name)\n\n## for camelcase preservation\ndef capitalize(s):\n    return '%s%s' % (s[0].upper(), s[1:])\ndef decapitalize(s):\n    return '%s%s' % (s[0].lower(), s[1:])\n\n## things I thought would have been in functools (mdk)\nintersperse = lambda e,l: sum([[x, e] for x in l],[])[:-1]\ndef foldl(f, x, l):\n    if len(l) == 0:\n        return x\n    return foldl(f, f(x, l[0]), l[1:])\n\n## Given a string V, V=, or V=VAL returns (V,VAL)\ndef splitBinding(s):\n    if '=' in s:\n        return s.split('=')\n    else:\n        return (s,'')\n\ndef escapequotes(s):\n    s = s.replace('\\\"', '\\\\\\\"')\n    return s\n"
  },
  {
    "path": "tests/adapter/Makefile",
    "content": "CONNECTALDIR?=../..\nS2H_INTERFACES = TestRequest:Test.request\nH2S_INTERFACES = Test:TestIndication\n\nBSVFILES = Test.bsv\nCPPFILES=test.cpp\n\ninclude $(CONNECTALDIR)/Makefile.connectal\n"
  },
  {
    "path": "tests/adapter/Test.bsv",
    "content": "// Copyright (c) 2013 Nokia, Inc.\n// Copyright (c) 2013 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\nimport Adapter::*;\n\ninterface TestIndication;\n    method Action done();\nendinterface\n\ninterface TestRequest;\n    method Action start();\nendinterface\n\ninterface Test;\n    interface TestRequest request;\nendinterface\n\nmodule mkTest#(TestIndication indication)(Test);\n    let dummy <- mkAdapterTb(interface AdapterIndication;\n                                 method Action done = indication.done;\n                             endinterface);\n    interface TestRequest request;\n        method Action start();\n            dummy.start();\n        endmethod\n    endinterface\nendmodule\n"
  },
  {
    "path": "tests/adapter/test.cpp",
    "content": "/* Copyright (c) 2014 Quanta Research Cambridge, Inc\n *\n * Permission is hereby granted, free of charge, to any person obtaining a\n * copy of this software and associated documentation files (the \"Software\"),\n * to deal in the Software without restriction, including without limitation\n * the rights to use, copy, modify, merge, publish, distribute, sublicense,\n * and/or sell copies of the Software, and to permit persons to whom the\n * Software is furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n * DEALINGS IN THE SOFTWARE.\n */\n#include \"TestRequest.h\"\n#include \"TestIndication.h\"\n\nclass TestIndication : public TestIndicationWrapper\n{\npublic:\n    void done() {\n        printf(\"Test: all done\\n\");\n        exit(0);\n    }\n    TestIndication(unsigned int id) : TestIndicationWrapper(id) {}\n};\n\nint main(int argc, const char **argv)\n{\n    TestIndication *testIndication = new TestIndication(IfcNames_TestIndicationH2S);\n    TestRequestProxy *testRequest = new TestRequestProxy(IfcNames_TestRequestS2H);\n\n    printf(\"Test: start\\n\");\n    testRequest->start();\n    sleep(100);\n    printf(\"Test: timed out\\n\");\n    return 0;\n}\n"
  },
  {
    "path": "tests/aecho/Echo.orig.bsv",
    "content": "// Copyright (c) 2013 Nokia, Inc.\n// Copyright (c) 2013 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\nimport EchoReq::*;\nimport EchoIndication::*;\nimport L_class_OC_Fifo1::*;\n\ninterface Echo;\n   interface EchoRequest request;\n   interface EchoIndicationPortalOutput lEchoIndicationOutput;\nendinterface\n\n(*synthesize*)\nmodule mkEcho(Echo);\n    EchoIndicationOutput myEchoIndicationOutput <- mkEchoIndicationOutput;\n    EchoIndication indication = myEchoIndicationOutput.ifc;\n    //FIFO#(Bit#(32)) delay <- mkSizedFIFO(8);\n    L_class_OC_Fifo1 delay <- mkL_class_OC_Fifo1;\n    rule heard;\n        delay.deq;\n        indication.heard(delay.first);\n    endrule\n\n    interface EchoIndicationPortalOutput lEchoIndicationOutput = myEchoIndicationOutput.portalIfc;\n    interface EchoRequest request;\n       method Action say(Bit#(32) v);\n\t  delay.enq(v);\n       endmethod\n    endinterface\nendmodule\n"
  },
  {
    "path": "tests/aecho/EchoReq.bsv",
    "content": "// Copyright (c) 2015 The Connectal Project\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\ninterface EchoIndication;\n    method Action heard(Bit#(32) v);\nendinterface\n\ninterface EchoRequest;\n   method Action say(Bit#(32) v);\nendinterface\n"
  },
  {
    "path": "tests/aecho/Makefile",
    "content": "CONNECTALDIR?=../..\nS2H_INTERFACES = EchoRequest:Echo.request\nH2S_INTERFACES = Echo:EchoIndication\n\nLTDIR = $(CONNECTALDIR)/../llvm-translate/\nLLVMT = $(LTDIR)/Debug+Asserts/bin/llvm-translate\nACCDIR = $(CONNECTALDIR)/../atomicc/examples/echo\nGENDIR = generated\nBSVFILES = EchoReq.bsv\nCPPFILES = testecho.cpp\nCONNECTALFLAGS += --verilog $(GENDIR) --bsvpath $(GENDIR)\nBSCFLAGS += -show-bvi\nAUTOTOP += --integratedIndication\n\nprebuild::\n\t$(LLVMT) --odir=$(GENDIR) $(ACCDIR)/fifo.ll\n\t$(LLVMT) --odir=$(GENDIR) $(ACCDIR)/echo.ll $(ACCDIR)/atomicc.ll\n\t$(LTDIR)/linker.py --directory generated --output Echo l_class_OC_Echo\n\ninclude $(CONNECTALDIR)/Makefile.connectal\n"
  },
  {
    "path": "tests/aecho/generated/Echo.bsv",
    "content": "\nimport ConnectalConfig::*;\nimport Portal::*;\nimport Pipe::*;\nimport Vector::*;\nimport EchoReq::*;\nimport EchoIndication::*;\n\ninterface Echo;\n   interface EchoRequest request;\n   interface EchoIndicationPortalOutput lEchoIndicationOutput;\nendinterface\ninterface EchoBVI;\n   interface EchoRequest request;\n   interface PortalSize messageSize;\n   interface PipeOut#(Bit#(SlaveDataBusWidth)) indications;\n   interface PortalInterrupt#(SlaveDataBusWidth) intr;\nendinterface\n\nimport \"BVI\" EchoVerilog =\nmodule mkEchoBVI(EchoBVI);\n    default_clock clk();\n    default_reset rst();\n    interface EchoRequest request;\n        method say(request_say_v) ready(RDY_request_say) enable(EN_request_say);\n    endinterface\n    interface PortalSize messageSize;\n        method messageSize_size size(messageSize_size_methodNumber) ready(RDY_messageSize_size);\n    endinterface\n    interface PipeOut indications;\n        method deq() enable(EN_indications_0_deq) ready(RDY_indications_0_deq);\n        method indications_0_notEmpty notEmpty() ready(RDY_indications_0_notEmpty);\n        method indications_0_first first() ready(RDY_indications_0_first);\n    endinterface\n    interface PortalInterrupt intr;\n        method intr_status status() ready(RDY_intr_status);\n        method intr_channel channel() ready(RDY_intr_channel);\n    endinterface\nendmodule\n\n(*synthesize*)\nmodule mkEcho(Echo);\n    let bvi <- mkEchoBVI;\n    Vector#(1, PipeOut#(Bit#(SlaveDataBusWidth))) tmpInd;\n    tmpInd[0] = bvi.indications;\n    interface EchoRequest request = bvi.request;\n    interface EchoIndicationPortalOutput lEchoIndicationOutput;\n        interface PortalSize messageSize = bvi.messageSize;\n        interface Vector indications = tmpInd;\n        interface PortalInterrupt intr = bvi.intr;\n    endinterface\nendmodule\n"
  },
  {
    "path": "tests/aecho/generated/EchoVerilog.v",
    "content": "\nmodule EchoVerilog(input CLK,\ninput RST_N,\noutput RDY_indications_0_deq, input EN_indications_0_deq,\n input [31:0]request_say_v,\noutput RDY_request_say, input EN_request_say,\noutput RDY_indications_0_notEmpty, output indications_0_notEmpty,\noutput RDY_indications_0_first, output [31:0]indications_0_first,\noutput RDY_intr_status, output intr_status,\noutput RDY_intr_channel, output [31:0]intr_channel,\n output RDY_messageSize_size, input[15:0] messageSize_size_methodNumber, output[15:0] messageSize_size\n );\n\n wire [31:0]ifc_heard_v;\n wire RDY_ifc_heard, EN_ifc_heard;\n\n l_class_OC_Echo lEcho(.CLK(CLK),\n.nRST(RST_N),\n.say__RDY(RDY_request_say), .say__ENA(EN_request_say),\n .say_v(request_say_v),\n .ind$heard_heard_v(ifc_heard_v), .respond_rule__ENA(1));\n mkEchoIndicationOutput myEchoIndicationOutput(.CLK(CLK),\n   .RST_N(RST_N),\n   .RDY_portalIfc_indications_0_deq(RDY_indications_0_deq), .EN_portalIfc_indications_0_deq(EN_indications_0_deq),\n   .RDY_portalIfc_indications_0_notEmpty(RDY_indications_0_notEmpty), .portalIfc_indications_0_notEmpty(indications_0_notEmpty),\n   .RDY_portalIfc_indications_0_first(RDY_indications_0_first), .portalIfc_indications_0_first(indications_0_first),\n   .RDY_portalIfc_intr_status(RDY_intr_status), .portalIfc_intr_status(intr_status),\n   .RDY_portalIfc_intr_channel(RDY_intr_channel), .portalIfc_intr_channel(intr_channel),\n    .ifc_heard_v(ifc_heard_v),\n   .RDY_ifc_heard(RDY_ifc_heard), .EN_ifc_heard(EN_ifc_heard),\n   .RDY_portalIfc_messageSize_size(RDY_messageSize_size), .portalIfc_messageSize_size_methodNumber(messageSize_size_methodNumber), .portalIfc_messageSize_size(messageSize_size));\nendmodule  // mkEcho\n"
  },
  {
    "path": "tests/aecho/generated/L_class_OC_Echo.bsv",
    "content": "interface L_class_OC_Echo;\n    method Action respond_rule();\n    method Action say(Bit#(32) say_v);\nendinterface\nimport \"BVI\" l_class_OC_Echo =\nmodule mkL_class_OC_Echo(L_class_OC_Echo);\n    default_reset rst(nRST);\n    default_clock clk(CLK);\n    method respond_rule() enable(respond_rule__ENA) ready(respond_rule__RDY);\n    method say(say_v) enable(say__ENA) ready(say__RDY);\n    schedule (respond_rule, say) CF (respond_rule, say);\nendmodule\n"
  },
  {
    "path": "tests/aecho/generated/L_class_OC_Fifo.bsv",
    "content": "interface L_class_OC_Fifo;\n    method Action in_enq(Bit#(32) in_enq_v);\n    method Action out_deq();\n    method Bit#(32) out_first();\nendinterface\nimport \"BVI\" l_class_OC_Fifo =\nmodule mkL_class_OC_Fifo(L_class_OC_Fifo);\n    default_reset rst(nRST);\n    default_clock clk(CLK);\n    method in_enq(in_enq_v) enable(in_enq__ENA) ready(in_enq__RDY);\n    method out_deq() enable(out_deq__ENA) ready(out_deq__RDY);\n    method out_first out_first() ready(out_first__RDY);\n    schedule (in_enq, out_deq, out_first) CF (in_enq, out_deq, out_first);\nendmodule\n"
  },
  {
    "path": "tests/aecho/generated/L_class_OC_Fifo1.bsv",
    "content": "interface L_class_OC_Fifo1;\n    method Action in_enq(Bit#(32) in_enq_v);\n    method Action out_deq();\n    method Bit#(32) out_first();\nendinterface\nimport \"BVI\" l_class_OC_Fifo1 =\nmodule mkL_class_OC_Fifo1(L_class_OC_Fifo1);\n    default_reset rst(nRST);\n    default_clock clk(CLK);\n    method in_enq(in_enq_v) enable(in_enq__ENA) ready(in_enq__RDY);\n    method out_deq() enable(out_deq__ENA) ready(out_deq__RDY);\n    method out_first out_first() ready(out_first__RDY);\n    schedule (in_enq, out_deq, out_first) CF (in_enq, out_deq, out_first);\nendmodule\n"
  },
  {
    "path": "tests/aecho/generated/l_class_OC_Echo.cpp",
    "content": "#include \"l_class_OC_Echo.h\"\nvoid l_class_OC_Echo::respond_rule(void) {\n        unsigned int call = fifo.out_first();\n        fifo.out_deq();\n        ind->heard(call);\n}\nbool l_class_OC_Echo::respond_rule__RDY(void) {\n        bool tmp__1 = fifo.out_first__RDY();\n        bool tmp__2 = fifo.out_deq__RDY();\n        bool tmp__3 = ind->heard__RDY();\n        return (tmp__1 & tmp__2) & tmp__3;\n}\nvoid l_class_OC_Echo::say(unsigned int say_v) {\n        fifo.in_enq(say_v);\n}\nbool l_class_OC_Echo::say__RDY(void) {\n        bool tmp__1 = fifo.in_enq__RDY();\n        return tmp__1;\n}\nvoid l_class_OC_Echo::run()\n{\n    if (respond_rule__RDY()) respond_rule();\n}\n"
  },
  {
    "path": "tests/aecho/generated/l_class_OC_Echo.h",
    "content": "#ifndef __l_class_OC_Echo_H__\n#define __l_class_OC_Echo_H__\n#include \"l_class_OC_Fifo1.h\"\n#include \"l_class_OC_EchoIndication.h\"\nclass l_class_OC_Echo {\n  class l_class_OC_Fifo1 fifo;\n  class l_class_OC_EchoIndication *ind;\n  unsigned int pipetemp;\npublic:\n  void respond_rule(void);\n  bool respond_rule__RDY(void);\n  void say(unsigned int say_v);\n  bool say__RDY(void);\n  void run();\n  void setind(class l_class_OC_EchoIndication *v) { ind = v; }\n};\n#endif  // __l_class_OC_Echo_H__\n"
  },
  {
    "path": "tests/aecho/generated/l_class_OC_Echo.v",
    "content": "module l_class_OC_Echo (\n    input CLK,\n    input nRST,\n    input respond_rule__ENA,\n    output respond_rule__RDY,\n    input say__ENA,\n    input [31:0]say_v,\n    output say__RDY,\n    output ind$heard__ENA,\n    output [31:0]ind$heard_heard_v,\n    input ind$heard__RDY);\n    wire respond_rule__RDY_internal;\n    wire respond_rule__ENA_internal = respond_rule__ENA && respond_rule__RDY_internal;\n    assign respond_rule__RDY = respond_rule__RDY_internal;\n    wire say__RDY_internal;\n    wire say__ENA_internal = say__ENA && say__RDY_internal;\n    assign say__RDY = say__RDY_internal;\n    wire fifo$out_deq__RDY;\n    wire fifo$out_first__RDY;\n    l_class_OC_Fifo1 fifo (\n        CLK,\n        nRST,\n        say__ENA_internal,\n        say_v,\n        say__RDY,\n        respond_rule__ENA_internal,\n        fifo$out_deq__RDY,\n        ind$heard_heard_v,\n        fifo$out_first__RDY);\n    reg[31:0] pipetemp;\n    assign ind$heard__ENA = respond_rule__ENA_internal;\n    assign respond_rule__RDY_internal = (fifo$out_first__RDY & fifo$out_deq__RDY) & ind$heard__RDY;\n\n    always @( posedge CLK) begin\n      if (!nRST) begin\n        pipetemp <= 0;\n      end // nRST\n    end // always @ (posedge CLK)\nendmodule \n\n//METAGUARD; respond_rule__RDY;         (fifo$out_first__RDY & fifo$out_deq__RDY) & ind$heard__RDY;\n//METAGUARD; say__RDY;         fifo$in_enq__RDY;\n//METAINVOKE; respond_rule; :;fifo$out_deq:;ind$heard:;fifo$out_first;\n//METAINVOKE; say; :;fifo$in_enq;\n//METAINTERNAL; fifo; l_class_OC_Fifo1;\n//METAEXTERNAL; ind; l_class_OC_EchoIndication;\n"
  },
  {
    "path": "tests/aecho/generated/l_class_OC_EchoIndication.cpp",
    "content": "#include \"l_class_OC_EchoIndication.h\"\nvoid l_class_OC_EchoIndication::heard(unsigned int heard_v) {\n        stop_main_program = 1;\n        (\"Heard an echo: %d\\n\")->(heard_v);\n}\nbool l_class_OC_EchoIndication::heard__RDY(void) {\n        return 1;\n}\n"
  },
  {
    "path": "tests/aecho/generated/l_class_OC_EchoIndication.h",
    "content": "#ifndef __l_class_OC_EchoIndication_H__\n#define __l_class_OC_EchoIndication_H__\nclass l_class_OC_EchoIndication {\npublic:\n  void heard(unsigned int heard_v);\n  bool heard__RDY(void);\n};\n#endif  // __l_class_OC_EchoIndication_H__\n"
  },
  {
    "path": "tests/aecho/generated/l_class_OC_EchoRequest.cpp",
    "content": "#include \"l_class_OC_EchoRequest.h\"\nvoid l_class_OC_EchoRequest::say(unsigned int say_v) {\n}\nbool l_class_OC_EchoRequest::say__RDY(void) {\n        return 1;\n}\n"
  },
  {
    "path": "tests/aecho/generated/l_class_OC_EchoRequest.h",
    "content": "#ifndef __l_class_OC_EchoRequest_H__\n#define __l_class_OC_EchoRequest_H__\nclass l_class_OC_EchoRequest {\npublic:\n  void say(unsigned int say_v);\n  bool say__RDY(void);\n};\n#endif  // __l_class_OC_EchoRequest_H__\n"
  },
  {
    "path": "tests/aecho/generated/l_class_OC_EchoTest.cpp",
    "content": "#include \"l_class_OC_EchoTest.h\"\n"
  },
  {
    "path": "tests/aecho/generated/l_class_OC_EchoTest.h",
    "content": "#ifndef __l_class_OC_EchoTest_H__\n#define __l_class_OC_EchoTest_H__\n#include \"l_class_OC_Echo.h\"\nclass l_class_OC_EchoTest {\n  class l_class_OC_Echo *echo;\n  unsigned int x;\npublic:\n  void setecho(class l_class_OC_Echo *v) { echo = v; }\n};\n#endif  // __l_class_OC_EchoTest_H__\n"
  },
  {
    "path": "tests/aecho/generated/l_class_OC_Fifo.cpp",
    "content": "#include \"l_class_OC_Fifo.h\"\nvoid l_class_OC_Fifo::in_enq(unsigned int in_enq_v) {\n}\nbool l_class_OC_Fifo::in_enq__RDY(void) {\n        return 0;\n}\nvoid l_class_OC_Fifo::out_deq(void) {\n}\nbool l_class_OC_Fifo::out_deq__RDY(void) {\n        return 0;\n}\nunsigned int l_class_OC_Fifo::out_first(void) {\n        return 0;\n}\nbool l_class_OC_Fifo::out_first__RDY(void) {\n        return 0;\n}\n"
  },
  {
    "path": "tests/aecho/generated/l_class_OC_Fifo.h",
    "content": "#ifndef __l_class_OC_Fifo_H__\n#define __l_class_OC_Fifo_H__\nclass l_class_OC_Fifo {\npublic:\n  void in_enq(unsigned int in_enq_v);\n  bool in_enq__RDY(void);\n  void out_deq(void);\n  bool out_deq__RDY(void);\n  unsigned int out_first(void);\n  bool out_first__RDY(void);\n};\n#endif  // __l_class_OC_Fifo_H__\n"
  },
  {
    "path": "tests/aecho/generated/l_class_OC_Fifo.v",
    "content": "module l_class_OC_Fifo (\n    input CLK,\n    input nRST,\n    input in_enq__ENA,\n    input [31:0]in_enq_v,\n    output in_enq__RDY,\n    input out_deq__ENA,\n    output out_deq__RDY,\n    output [31:0]out_first,\n    output out_first__RDY);\n    wire in_enq__RDY_internal;\n    wire in_enq__ENA_internal = in_enq__ENA && in_enq__RDY_internal;\n    assign in_enq__RDY = in_enq__RDY_internal;\n    wire out_deq__RDY_internal;\n    wire out_deq__ENA_internal = out_deq__ENA && out_deq__RDY_internal;\n    assign out_deq__RDY = out_deq__RDY_internal;\n    assign in_enq__RDY_internal = 0;\n    assign out_deq__RDY_internal = 0;\n    assign out_first = 0;\n    assign out_first__RDY_internal = 0;\nendmodule \n\n//METAGUARD; in_enq__RDY;         0;\n//METAGUARD; out_deq__RDY;         0;\n//METAGUARD; out_first__RDY;         0;\n"
  },
  {
    "path": "tests/aecho/generated/l_class_OC_Fifo1.cpp",
    "content": "#include \"l_class_OC_Fifo1.h\"\nvoid l_class_OC_Fifo1::in_enq(unsigned int in_enq_v) {\n        element = in_enq_v;\n        full = 1;\n}\nbool l_class_OC_Fifo1::in_enq__RDY(void) {\n        return full ^ 1;\n}\nvoid l_class_OC_Fifo1::out_deq(void) {\n        full = 0;\n}\nbool l_class_OC_Fifo1::out_deq__RDY(void) {\n        return full;\n}\nunsigned int l_class_OC_Fifo1::out_first(void) {\n        return element;\n}\nbool l_class_OC_Fifo1::out_first__RDY(void) {\n        return full;\n}\n"
  },
  {
    "path": "tests/aecho/generated/l_class_OC_Fifo1.h",
    "content": "#ifndef __l_class_OC_Fifo1_H__\n#define __l_class_OC_Fifo1_H__\nclass l_class_OC_Fifo1 {\n  unsigned int element;\n  bool full;\npublic:\n  void in_enq(unsigned int in_enq_v);\n  bool in_enq__RDY(void);\n  void out_deq(void);\n  bool out_deq__RDY(void);\n  unsigned int out_first(void);\n  bool out_first__RDY(void);\n};\n#endif  // __l_class_OC_Fifo1_H__\n"
  },
  {
    "path": "tests/aecho/generated/l_class_OC_Fifo1.v",
    "content": "module l_class_OC_Fifo1 (\n    input CLK,\n    input nRST,\n    input in_enq__ENA,\n    input [31:0]in_enq_v,\n    output in_enq__RDY,\n    input out_deq__ENA,\n    output out_deq__RDY,\n    output [31:0]out_first,\n    output out_first__RDY);\n    wire in_enq__RDY_internal;\n    wire in_enq__ENA_internal = in_enq__ENA && in_enq__RDY_internal;\n    assign in_enq__RDY = in_enq__RDY_internal;\n    wire out_deq__RDY_internal;\n    wire out_deq__ENA_internal = out_deq__ENA && out_deq__RDY_internal;\n    assign out_deq__RDY = out_deq__RDY_internal;\n    reg[31:0] element;\n    reg full;\n    assign in_enq__RDY_internal = full ^ 1;\n    assign out_deq__RDY_internal = full;\n    assign out_first = element;\n    assign out_first__RDY_internal = full;\n\n    always @( posedge CLK) begin\n      if (!nRST) begin\n        element <= 0;\n        full <= 0;\n      end // nRST\n      else begin\n        if (in_enq__ENA_internal) begin\n            element <= in_enq_v;\n            full <= 1;\n        end; // End of in_enq\n        if (out_deq__ENA_internal) begin\n            full <= 0;\n        end; // End of out_deq\n      end\n    end // always @ (posedge CLK)\nendmodule \n\n//METAGUARD; in_enq__RDY;         full ^ 1;\n//METAGUARD; out_deq__RDY;         full;\n//METAGUARD; out_first__RDY;         full;\n//METAWRITE; in_enq; :;element:;full;\n//METAWRITE; out_deq; :;full;\n//METAREAD; out_first; :;element;\n"
  },
  {
    "path": "tests/aecho/generated/output.cpp",
    "content": "void l_class_OC_Echo::respond_rule(void) {\n        unsigned int call = fifo.first();\n        fifo.deq();\n        ind->heard(call);\n}\nbool l_class_OC_Echo::respond_rule__RDY(void) {\n        bool tmp__1 = fifo.first__RDY();\n        bool tmp__2 = fifo.deq__RDY();\n        bool tmp__3 = ind->heard__RDY();\n        return (tmp__1 & tmp__2) & tmp__3;\n}\nvoid l_class_OC_Echo::say(unsigned int say_v) {\n        fifo.enq(say_v);\n}\nbool l_class_OC_Echo::say__RDY(void) {\n        bool tmp__1 = fifo.enq__RDY();\n        return tmp__1;\n}\nvoid l_class_OC_Echo::run()\n{\n    if (respond_rule__RDY()) respond_rule();\n}\n"
  },
  {
    "path": "tests/aecho/generated/output.h",
    "content": "class l_class_OC_EchoRequest {\nprivate:\npublic:\n  void say(unsigned int say_v);\n  bool say__RDY(void);\n};\n\nclass l_class_OC_EchoIndication {\nprivate:\npublic:\n  void heard(unsigned int heard_v);\n  bool heard__RDY(void);\n};\n\nclass l_class_OC_Echo {\nprivate:\n  class l_class_OC_Fifo1 fifo;\n  class l_class_OC_EchoIndication *ind;\n  unsigned int pipetemp;\npublic:\n  void respond_rule(void);\n  bool respond_rule__RDY(void);\n  void say(unsigned int say_v);\n  bool say__RDY(void);\n  void run();\n  void setind(class l_class_OC_EchoIndication *v) { ind = v; }\n};\n\nclass l_class_OC_EchoTest {\nprivate:\n  class l_class_OC_Echo *echo;\n  unsigned int x;\npublic:\n  void setecho(class l_class_OC_Echo *v) { echo = v; }\n};\n\n"
  },
  {
    "path": "tests/aecho/testecho.cpp",
    "content": "/* Copyright (c) 2014 Quanta Research Cambridge, Inc\n *\n * Permission is hereby granted, free of charge, to any person obtaining a\n * copy of this software and associated documentation files (the \"Software\"),\n * to deal in the Software without restriction, including without limitation\n * the rights to use, copy, modify, merge, publish, distribute, sublicense,\n * and/or sell copies of the Software, and to permit persons to whom the\n * Software is furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n * DEALINGS IN THE SOFTWARE.\n */\n#include \"EchoIndication.h\"\n#include \"EchoRequest.h\"\n\nstatic EchoRequestProxy *echoRequestProxy = 0;\n\nclass EchoIndication : public EchoIndicationWrapper\n{\npublic:\n    virtual void heard(uint32_t v) {\n        printf(\"heard an echo: %d\\n\", v);\n    }\n    EchoIndication(unsigned int id) : EchoIndicationWrapper(id) {}\n};\n\nstatic void call_say(int v)\n{\n    printf(\"[%s:%d] %d\\n\", __FUNCTION__, __LINE__, v);\n    echoRequestProxy->say(v);\n}\n\nint main(int argc, const char **argv)\n{\n    EchoIndication echoIndication(IfcNames_EchoIndicationH2S);\n    echoRequestProxy = new EchoRequestProxy(IfcNames_EchoRequestS2H);\n\n    int v = 42;\n    printf(\"Saying %d\\n\", v);\n    call_say(v);\n    call_say(v*5);\n    call_say(v*17);\n    call_say(v*93);\n    printf(\"TEST TYPE: SEM\\n\");\n    return 0;\n}\n"
  },
  {
    "path": "tests/algo1_flashmodel/AuroraCommon.bsv",
    "content": "package AuroraCommon;\n\n\n`include \"ConnectalProjectConfig.bsv\"\nimport FIFO::*;\nimport Clocks :: *;\nimport DefaultValue :: *;\nimport Xilinx :: *;\nimport XilinxCells :: *;\nimport ConnectalXilinxCells::*;\n\ntypedef 8 AuroraExtCount;\n\n(* always_enabled, always_ready *)\ninterface Aurora_Clock_Pins;\n\t//(* prefix = \"\", result = \"\" *)\n\tmethod Action gtx_clk_p(Bit#(1) v);\n\t//(* prefix = \"\", result = \"\" *)\n\tmethod Action gtx_clk_n(Bit#(1) v);\n\t\n\tinterface Clock gtx_clk_p_deleteme_unused_clock;\n\tinterface Clock gtx_clk_n_deleteme_unused_clock;\nendinterface\n\ninterface AuroraExtImportIfc#(numeric type lanes);\n\tinterface Clock aurora_clk0;\n\tinterface Clock aurora_clk1;\n\tinterface Clock aurora_clk2;\n\tinterface Clock aurora_clk3;\n\tinterface Reset aurora_rst0;\n\tinterface Reset aurora_rst1;\n\tinterface Reset aurora_rst2;\n\tinterface Reset aurora_rst3;\n\n\t(* prefix = \"\" *)\n\tinterface Aurora_Pins#(1) aurora0;\n\t(* prefix = \"\" *)\n\tinterface Aurora_Pins#(1) aurora1;\n\t(* prefix = \"\" *)\n\tinterface Aurora_Pins#(1) aurora2;\n\t(* prefix = \"\" *)\n\tinterface Aurora_Pins#(1) aurora3;\n\t(* prefix = \"\" *)\n\tinterface AuroraControllerIfc#(64) user0;\n\t(* prefix = \"\" *)\n\tinterface AuroraControllerIfc#(64) user1;\n\t(* prefix = \"\" *)\n\tinterface AuroraControllerIfc#(64) user2;\n\t(* prefix = \"\" *)\n\tinterface AuroraControllerIfc#(64) user3;\nendinterface\n\ninterface AuroraImportIfc#(numeric type lanes);\n\tinterface Clock aurora_clk;\n\tinterface Reset aurora_rst;\n\t(* prefix = \"\" *)\n\tinterface Aurora_Pins#(lanes) aurora;\n\t(* prefix = \"\" *)\n\tinterface AuroraControllerIfc#(TMul#(lanes,32)) user;\nendinterface\n\ninterface AuroraControllerIfc#(numeric type width);\n\tinterface Reset aurora_rst_n;\n\t\t\n\tmethod Bit#(1) channel_up;\n\tmethod Bit#(1) lane_up;\n\tmethod Bit#(1) hard_err;\n\tmethod Bit#(1) soft_err;\n\tmethod Bit#(8) data_err_count;\n\n\tmethod Action send(Bit#(width) tx);\n\tmethod ActionValue#(Bit#(width)) receive();\nendinterface\n\n(* always_enabled, always_ready *)\ninterface Aurora_Pins#(numeric type lanes);\n\t(* prefix = \"\", result = \"RXN\" *)\n\tmethod Action rxn_in(Bit#(lanes) rxn_i);\n\t(* prefix = \"\", result = \"RXP\" *)\n\tmethod Action rxp_in(Bit#(lanes) rxp_i);\n\n\t(* prefix = \"\", result = \"TXN\" *)\n\tmethod Bit#(lanes) txn_out();\n\t(* prefix = \"\", result = \"TXP\" *)\n\tmethod Bit#(lanes) txp_out();\nendinterface\n\ninterface GtxClockImportIfc;\n\tinterface Aurora_Clock_Pins aurora_clk;\n\tinterface Clock gtx_clk_p_ifc;\n\tinterface Clock gtx_clk_n_ifc;\nendinterface\n\n(* synthesize *)\nmodule mkGtxClockImport (GtxClockImportIfc);\n`ifndef SIMULATION\n\tB2C i_gtx_clk_p <- mkB2C();\n\tB2C i_gtx_clk_n <- mkB2C();\n\n\tinterface Aurora_Clock_Pins aurora_clk;\n\tmethod Action gtx_clk_p(Bit#(1) v);\n\t\ti_gtx_clk_p.inputclock(v);\n\tendmethod\n\tmethod Action gtx_clk_n(Bit#(1) v);\n\t\ti_gtx_clk_n.inputclock(v);\n\tendmethod\n\tinterface Clock gtx_clk_p_deleteme_unused_clock = i_gtx_clk_p.c; // These clocks are deleted from the netlist by the synth.tcl script\n\tinterface Clock gtx_clk_n_deleteme_unused_clock = i_gtx_clk_n.c;\n\tendinterface\n\t//interface Clock gtx_clk = gtx_clk_i;\n\tinterface Clock gtx_clk_p_ifc = i_gtx_clk_p.c;\n\tinterface Clock gtx_clk_n_ifc = i_gtx_clk_n.c;\n`else\n\tClock clk <- exposeCurrentClock;\n\t\n\tinterface Aurora_Clock_Pins aurora_clk;\n\tinterface Clock gtx_clk_p_deleteme_unused_clock = clk; // These clocks are deleted from the netlist by the synth.tcl script\n\tinterface Clock gtx_clk_n_deleteme_unused_clock = clk;\n\tendinterface\n\t//interface Clock gtx_clk = gtx_clk_i;\n\tinterface Clock gtx_clk_p_ifc = clk;\n\tinterface Clock gtx_clk_n_ifc = clk;\n`endif\nendmodule\n\n\nendpackage: AuroraCommon\n"
  },
  {
    "path": "tests/algo1_flashmodel/AuroraGearbox.bsv",
    "content": "import FIFO::*;\nimport FIFOF::*;\nimport Clocks :: *;\n\ntypedef 8 HeaderSz;\ntypedef TSub#(128,8) BodySz;\ntypedef TMul#(2,TSub#(128,HeaderSz)) DataIfcSz;\ntypedef Bit#(DataIfcSz) DataIfc;\ntypedef Bit#(6) PacketType;\ntypedef 128 AuroraWidth;\n\n\ninterface AuroraGearboxIfc;\n\tmethod Action send(DataIfc data, PacketType ptype);\n\tmethod ActionValue#(Tuple2#(DataIfc, PacketType)) recv;\n\n\tmethod Action auroraRecv(Bit#(AuroraWidth) word);\n\tmethod ActionValue#(Bit#(AuroraWidth)) auroraSend;\n\n\t//method Action resetLink;\nendinterface\n\nmodule mkAuroraGearbox#(Clock aclk, Reset arst) (AuroraGearboxIfc);\n\tSyncFIFOIfc#(Tuple2#(DataIfc,PacketType)) sendQ <- mkSyncFIFOFromCC(4, aclk);\n\n\tInteger recvQDepth = 128;\n\tInteger windowSize = 64;\n\tSyncFIFOIfc#(Tuple2#(DataIfc,PacketType)) recvQ <- mkSyncFIFOToCC(4, aclk, arst);\n\tFIFO#(Tuple2#(DataIfc,PacketType)) recvBufferQ <- mkSizedFIFO(recvQDepth, clocked_by aclk, reset_by arst);\n\tReg#(Bit#(16)) maxInFlightUp <- mkReg(0, clocked_by aclk, reset_by arst);\n\tReg#(Bit#(16)) maxInFlightDown <- mkReg(0, clocked_by aclk, reset_by arst);\n\tReg#(Bit#(16)) curInQUp <- mkReg(0, clocked_by aclk, reset_by arst);\n\tReg#(Bit#(16)) curInQDown <- mkReg(0, clocked_by aclk, reset_by arst);\n\tFIFOF#(Bit#(8)) flowControlQ <- mkFIFOF(clocked_by aclk, reset_by arst);\n\trule emitFlowControlPacket\n\t\t((maxInFlightUp-maxInFlightDown)\n\t\t+(curInQUp-curInQDown)\n\t\t+fromInteger(windowSize) < fromInteger(recvQDepth));\n\n\t\tflowControlQ.enq(fromInteger(windowSize));\n\t\tmaxInFlightUp <= maxInFlightUp + fromInteger(windowSize);\n\tendrule\n\n\tReg#(Bit#(16)) curSendBudgetUp <- mkReg(0, clocked_by aclk, reset_by arst);\n\tReg#(Bit#(16)) curSendBudgetDown <- mkReg(0, clocked_by aclk, reset_by arst);\n\n\tFIFO#(Bit#(AuroraWidth)) auroraOutQ <- mkFIFO(clocked_by aclk, reset_by arst);\n\tReg#(Maybe#(Tuple2#(Bit#(BodySz), PacketType))) packetSendBuffer <- mkReg(tagged Invalid, clocked_by aclk, reset_by arst);\n\trule sendPacketPart;\n\t\tlet curSendBudget = curSendBudgetUp - curSendBudgetDown;\n\t\tif ( flowControlQ.notEmpty ) begin\n\t\t\tflowControlQ.deq;\n\t\t\tPacketType ptype = 0;\n\t\t\tauroraOutQ.enq({2'b01, ptype, zeroExtend(flowControlQ.first)});\n\t\t\t$display(\"AuroraOutQ: flowControl packet: %d\", flowControlQ.first);\n\t\t\t$display(\"send budget = %d\", curSendBudget);\n\t\tend else\n\t\tif ( curSendBudget > 0 ) begin\n\t\t\tif ( isValid(packetSendBuffer) ) begin\n\t\t\t\tlet btpl = fromMaybe(?, packetSendBuffer);\n\t\t\t\t//auroraIntraImport.user.send({2'b10,\n\t\t\t\tauroraOutQ.enq({2'b10,\n\t\t\t\t\ttpl_2(btpl), tpl_1(btpl)\n\t\t\t\t\t});\n\t\t\t\tpacketSendBuffer <= tagged Invalid;\n\t\t\t\tcurSendBudgetDown <= curSendBudgetDown + 1;\n\t\t\t\t$display(\"AuroraOutQ: data packet VALID: data=%x, type=%x\", tpl_1(btpl), tpl_2(btpl));\n\t\t\tend else begin\n\t\t\t\tsendQ.deq;\n\t\t\t\tlet data = sendQ.first;\n\t\t\t\tpacketSendBuffer <= tagged Valid \n\t\t\t\t\ttuple2(\n\t\t\t\t\t\ttruncate(tpl_1(data)>>valueOf(BodySz)),\n\t\t\t\t\t\ttpl_2(data)\n\t\t\t\t\t);\n\t\t\t\tauroraOutQ.enq({2'b00, tpl_2(data),truncate(tpl_1(data))});\n\t\t\t\t$display(\"AuroraOutQ: data packet INVALID: data=%x, type=%x\", tpl_1(data), tpl_2(data));\n\t\t\tend\n\t\t\t$display(\"send budget = %d\", curSendBudget);\n\t\tend\n\tendrule\n\n\tFIFO#(Bit#(AuroraWidth)) auroraInQ <- mkFIFO(clocked_by aclk, reset_by arst);\n\tReg#(Maybe#(Bit#(BodySz))) packetRecvBuffer <- mkReg(tagged Invalid, clocked_by aclk, reset_by arst);\n\tReg#(Bit#(1)) curRecvOffset <- mkReg(0, clocked_by aclk, reset_by arst);\n\trule recvPacketPart;\n\t\tlet crdata = auroraInQ.first;\n\t\tauroraInQ.deq;\n\t\tBit#(BodySz) cdata = truncate(crdata);\n\t\tBit#(8) header = truncate(crdata>>valueOf(BodySz));\n\t\tBit#(1) idx = header[7];\n\t\tBit#(1) control = header[6];\n\t\tPacketType ptype = truncate(header);\n\n\t\tif ( control == 1 ) begin\n\t\t\tcurSendBudgetUp <= curSendBudgetUp + truncate(cdata);\n\t\tend \n\t\telse if ( isValid(packetRecvBuffer) ) begin\n\t\t\tlet pdata = fromMaybe(0, packetRecvBuffer);\n\t\t\tif ( idx == 1 ) begin\n\t\t\t\tpacketRecvBuffer <= tagged Invalid;\n\t\t\t\trecvBufferQ.enq( tuple2({cdata, pdata}, ptype) );\n\n\t\t\t\tmaxInFlightDown <= maxInFlightDown + 1;\n\t\t\t\tcurInQUp <= curInQUp + 1;\n\t\t\tend\n\t\t\telse begin\n\t\t\t\tpacketRecvBuffer <= tagged Valid cdata;\n\t\t\tend\n\t\tend\n\t\telse begin\n\t\t\tif ( idx == 0 ) \n\t\t\t\tpacketRecvBuffer <= tagged Valid cdata;\n\t\tend\n\tendrule\n\trule flushReadBuffer;\n\t\tcurInQDown <= curInQDown + 1;\n\n\t\trecvBufferQ.deq;\n\t\trecvQ.enq(recvBufferQ.first);\n\tendrule\n\n\tmethod Action send(DataIfc data, PacketType ptype);\n\t\tsendQ.enq(tuple2(data, ptype));\n\tendmethod\n\tmethod ActionValue#(Tuple2#(DataIfc, PacketType)) recv;\n\n\t\trecvQ.deq;\n\t\treturn recvQ.first;\n\tendmethod\n\n\tmethod Action auroraRecv(Bit#(AuroraWidth) word);\n\t\tauroraInQ.enq(word);\n\tendmethod\n\tmethod ActionValue#(Bit#(AuroraWidth)) auroraSend;\n\t\tauroraOutQ.deq;\n\t\treturn auroraOutQ.first;\n\tendmethod\n\t\n\t/*\n\tmethod Action resetLink;\n\t\tmaxInFlightUp <= 0;\n\t\tmaxInFlightDown <= 0;\n\t\tcurInQUp <= 0;\n\t\tcurInQDown <= 0;\n\tendmethod\n\t*/\nendmodule\n"
  },
  {
    "path": "tests/algo1_flashmodel/AuroraImportFmc1.bsv",
    "content": "package AuroraImportFmc1;\n\n`include \"ConnectalProjectConfig.bsv\"\nimport FIFO::*;\nimport FIFOF::*;\nimport Clocks :: *;\nimport DefaultValue :: *;\nimport Xilinx :: *;\nimport XilinxCells :: *;\nimport ConnectalXilinxCells::*;\n\nimport AuroraCommon::*;\n\nimport AuroraGearbox::*;\n\ninterface AuroraIfc;\n\tmethod Action send(DataIfc data, PacketType ptype);\n\tmethod ActionValue#(Tuple2#(DataIfc, PacketType)) receive;\n\tmethod Tuple4#(Bit#(32), Bit#(32), Bit#(32), Bit#(32)) getDebugCnts;\n\n\tinterface Clock clk;\n\tinterface Reset rst;\n\n\tmethod Bit#(1) channel_up;\n\tmethod Bit#(1) lane_up;\n\tmethod Bit#(1) hard_err;\n\tmethod Bit#(1) soft_err;\n\tmethod Bit#(8) data_err_count;\n\t\n\t(* prefix = \"\" *)\n\tinterface Aurora_Pins#(4) aurora;\nendinterface\n\n(* synthesize *)\nmodule mkAuroraIntra#(Clock gtx_clk_p, Clock gtx_clk_n, Clock clk250) (AuroraIfc);\n\n\tClock cur_clk <- exposeCurrentClock; // assuming 200MHz clock\n\tReset cur_rst <- exposeCurrentReset;\n\t\n\n`ifndef SIMULATION\n\tClockDividerIfc auroraIntraClockDiv4 <- mkDCMClockDivider(5, 4, clocked_by clk250);\n\t//ClockDividerIfc auroraIntraClockDiv4 <- mkDCMClockDivider(4, 5);\n\tReset defaultReset <- exposeCurrentReset;\n\tClock clk50 = auroraIntraClockDiv4.slowClock;\n\t//MakeResetIfc rst50ifc <- mkReset(8, True, clk50);\n\tMakeResetIfc rst50ifc2 <- mkReset(8, True, clk50);\n\t//Reset rst50 = rst50ifc.new_rst;\n\tReset rst50 <- mkAsyncReset(2, defaultReset, clk50);\n\tReset rst50_2 = rst50ifc2.new_rst;\n\tReset rst50_2a <- mkAsyncReset(2, rst50_2, clk50);\n\tClock fmc1_gtx_clk_i <- mkClockIBUFDS_GTE2(True, gtx_clk_p, gtx_clk_n);\n\tAuroraImportIfc#(4) auroraIntraImport <- mkAuroraImport_8b10b_fmc1(fmc1_gtx_clk_i, clk50, rst50, rst50);//rst50_2a);\n`else\n\t//Clock gtx_clk = cur_clk;\n\tAuroraImportIfc#(4) auroraIntraImport <- mkAuroraImport_8b10b_bsim;\n`endif\n\n\n\tClock aclk = auroraIntraImport.aurora_clk;\n\tReset arst = auroraIntraImport.aurora_rst;\n\n\n\tReg#(Bit#(32)) gearboxSendCnt <- mkReg(0);\n\tReg#(Bit#(32)) gearboxRecCnt <- mkReg(0);\n\tReg#(Bit#(32)) auroraSendCnt <- mkReg(0, clocked_by aclk, reset_by arst);\n\tReg#(Bit#(32)) auroraRecCnt <- mkReg(0, clocked_by aclk, reset_by arst);\n\tReg#(Bit#(32)) auroraSendCntCC <- mkSyncRegToCC(0, aclk, arst);\n\tReg#(Bit#(32)) auroraRecCntCC <- mkSyncRegToCC(0, aclk, arst);\n\trule syncCnt;\n\t\tauroraSendCntCC <= auroraSendCnt;\n\t\tauroraRecCntCC <= auroraRecCnt;\n\tendrule\n\n\n\tAuroraGearboxIfc auroraGearbox <- mkAuroraGearbox(aclk, arst);\n\trule auroraOut if (auroraIntraImport.user.channel_up==1);\n\t\tlet d <- auroraGearbox.auroraSend;\n\t\t//if ( auroraIntraImport.user.channel_up == 1 ) begin\n\t\t\t$display(\"Gearbox send out: %x\", d);\n\t\t\tauroraSendCnt <= auroraSendCnt + 1;\n\t\t\tauroraIntraImport.user.send(d);\n\t\t//end\n\tendrule\n\t/*\n\trule resetDeadLink ( auroraIntraImport.user.channel_up == 0 );\n\t\tauroraGearbox.resetLink;\n\t\t$display(\"Gearbox reset link\");\n\tendrule\n\t*/\n\trule auroraIn;\n\t\tlet d <- auroraIntraImport.user.receive;\n\t\t$display(\"Gearbox received: %x\", d);\n\t\tauroraRecCnt <= auroraRecCnt + 1;\n\t\tauroraGearbox.auroraRecv(d);\n\tendrule\n\t\t\n\n\tmethod Tuple4#(Bit#(32), Bit#(32), Bit#(32), Bit#(32)) getDebugCnts;\n\t\treturn tuple4(gearboxSendCnt, gearboxRecCnt, auroraSendCntCC, auroraRecCntCC);\n\tendmethod\n\n\n\tmethod Action send(DataIfc data, PacketType ptype);\n\t\tauroraGearbox.send(data, ptype);\n\t\tgearboxSendCnt <= gearboxSendCnt + 1;\n\tendmethod\n\tmethod ActionValue#(Tuple2#(DataIfc, PacketType)) receive;\n\t\tlet d <- auroraGearbox.recv;\n\t\tgearboxRecCnt <= gearboxRecCnt + 1;\n\t\treturn d;\n\tendmethod\n\n\tmethod channel_up = auroraIntraImport.user.channel_up;\n\tmethod lane_up = auroraIntraImport.user.lane_up;\n\tmethod hard_err = auroraIntraImport.user.hard_err;\n\tmethod soft_err = auroraIntraImport.user.soft_err;\n\tmethod data_err_count = auroraIntraImport.user.data_err_count;\n\n\tinterface Clock clk = auroraIntraImport.aurora_clk;\n\tinterface Reset rst = auroraIntraImport.aurora_rst;\n\n\tinterface Aurora_Pins aurora = auroraIntraImport.aurora;\nendmodule\n\nmodule mkAuroraImport_8b10b_bsim (AuroraImportIfc#(4));\n\tClock clk <- exposeCurrentClock;\n\tReset rst <- exposeCurrentReset;\n\n\tFIFOF#(Bit#(128)) mirrorQ <- mkSizedFIFOF(2);\n\tReg#(Bit#(1)) laneUpR <- mkReg(0);\n\tReg#(Bit#(32)) laneUpDelay <- mkReg(500);\n\n\trule updateLaneUp;\n\t\tif (laneUpDelay ==0) begin\n\t\t\tlaneUpR <= 1;\n\t\tend\n\t\telse begin\n\t\t\tlaneUpDelay <= laneUpDelay - 1;\n\t\tend\n\tendrule\n\n\n\trule detectFull if (!mirrorQ.notFull);\n\t\t$display(\"WARNING: mirrorQ is full!\");\n\tendrule\n\n\tinterface aurora_clk = clk;\n\tinterface aurora_rst = rst;\n\tinterface AuroraControllerIfc user;\n\t\tinterface Reset aurora_rst_n = rst;\n\n\t\tmethod Bit#(1) channel_up;\n\t\t\treturn laneUpR; \n\t\tendmethod\n\t\tmethod Bit#(1) lane_up;\n\t\t\treturn laneUpR;\n\t\tendmethod\n\t\tmethod Bit#(1) hard_err;\n\t\t\treturn 0;\n\t\tendmethod\n\t\tmethod Bit#(1) soft_err;\n\t\t\treturn 0;\n\t\tendmethod\n\t\tmethod Bit#(8) data_err_count;\n\t\t\treturn 0;\n\t\tendmethod\n\n\t\tmethod Action send(Bit#(128) data);\n\t\t\tmirrorQ.enq(data);\n\t\tendmethod\n\t\tmethod ActionValue#(Bit#(128)) receive;\n\t\t\tmirrorQ.deq;\n\t\t\treturn mirrorQ.first;\n\t\tendmethod\n\tendinterface\nendmodule\n\nimport \"BVI\" aurora_8b10b_fmc1_exdes =\nmodule mkAuroraImport_8b10b_fmc1#(Clock gtx_clk_in, Clock init_clk, Reset init_rst_n, Reset gt_rst_n) (AuroraImportIfc#(4));\n\tdefault_clock no_clock;\n\tdefault_reset no_reset;\n\n\tinput_clock (INIT_CLK_IN) = init_clk;\n\tinput_reset (RESET_N) = init_rst_n;\n\tinput_reset (GT_RESET_N) = gt_rst_n;\n\n\toutput_clock aurora_clk(USER_CLK);\n\toutput_reset aurora_rst(USER_RST_N) clocked_by (aurora_clk);\n\n\tinput_clock (GTX_CLK) = gtx_clk_in;\n\n\tinterface Aurora_Pins aurora;\n\t\tmethod rxn_in(RXN) enable((*inhigh*) rx_n_en) reset_by(no_reset) clocked_by(gtx_clk_in);\n\t\tmethod rxp_in(RXP) enable((*inhigh*) rx_p_en) reset_by(no_reset) clocked_by(gtx_clk_in);\n\t\tmethod TXN txn_out() reset_by(no_reset) clocked_by(gtx_clk_in); \n\t\tmethod TXP txp_out() reset_by(no_reset) clocked_by(gtx_clk_in);\n\tendinterface\n\n\tinterface AuroraControllerIfc user;\n\t\toutput_reset aurora_rst_n(USER_RST) clocked_by (aurora_clk);\n\n\t\tmethod CHANNEL_UP channel_up;\n\t\tmethod LANE_UP lane_up;\n\t\tmethod HARD_ERR hard_err;\n\t\tmethod SOFT_ERR soft_err;\n\t\tmethod ERR_COUNT data_err_count;\n\n\t\tmethod send(TX_DATA) enable(tx_en) ready(tx_rdy) clocked_by(aurora_clk) reset_by(aurora_rst);\n\t\tmethod RX_DATA receive() enable((*inhigh*) rx_en) ready(rx_rdy) clocked_by(aurora_clk) reset_by(aurora_rst);\n\tendinterface\n\t\n\tschedule (aurora_rxn_in, aurora_rxp_in, aurora_txn_out, aurora_txp_out, user_channel_up, user_lane_up, user_hard_err, user_soft_err, user_data_err_count) CF \n\t(aurora_rxn_in, aurora_rxp_in, aurora_txn_out, aurora_txp_out, user_channel_up, user_lane_up, user_hard_err, user_soft_err, user_data_err_count);\n\tschedule (user_send) CF (aurora_rxn_in, aurora_rxp_in, aurora_txn_out, aurora_txp_out, user_channel_up, user_lane_up, user_hard_err, user_soft_err, user_data_err_count);\n\n\tschedule (user_receive) CF (aurora_rxn_in, aurora_rxp_in, aurora_txn_out, aurora_txp_out, user_channel_up, user_lane_up, user_hard_err, user_soft_err, user_data_err_count);\n\n\tschedule (user_receive) SB (user_send);\n\tschedule (user_send) C (user_send);\n\tschedule (user_receive) C (user_receive);\n\nendmodule\n\nendpackage: AuroraImportFmc1\n"
  },
  {
    "path": "tests/algo1_flashmodel/ChipscopeWrapper.bsv",
    "content": "\ntypedef 4 NumDbgIlas;\n\ninterface DebugVIO;\n\tmethod Action setDebugVin (Bit#(64) i);\n\tmethod Bit#(64) getDebugVout();\nendinterface\n\ninterface DebugILA;\n\tmethod Action setDebug0 (Bit#(16) i);\n\tmethod Action setDebug1 (Bit#(16) i);\n\tmethod Action setDebug2 (Bit#(16) i);\n\tmethod Action setDebug3 (Bit#(16) i);\n\tmethod Action setDebug4 (Bit#(16) i);\n\tmethod Action setDebug5_64 (Bit#(64) i);\n\tmethod Action setDebug6_64 (Bit#(64) i);\nendinterface\n\n\ninterface CSDebugIfc; \n\tinterface DebugVIO vio;\n\tinterface DebugILA ila0;\n\tinterface DebugILA ila1;\n\tinterface DebugILA ila2;\n\tinterface DebugILA ila3;\n\tinterface DebugILA ila4;\n\tinterface DebugILA ila5;\n\tinterface DebugILA ila6;\n\tinterface DebugILA ila7;\nendinterface \n\nimport \"BVI\" chipscope_debug_viv =  //TODO change for Vivado or ISE IP\nmodule mkChipscopeDebug(CSDebugIfc);\n\tdefault_clock clk0;\n\tdefault_reset rst0;\n\n\tinput_clock clk0(v_clk0) <- exposeCurrentClock;\n\tinput_reset rst0(v_rst0) <- exposeCurrentReset;\n\ninterface DebugVIO vio;\n\tmethod setDebugVin (v_debug_vin) enable((*inhigh*)en38);\n\tmethod v_debug_vout getDebugVout;\nendinterface \n\ninterface DebugILA ila0;\n\t\tmethod setDebug0 (v_debug0_0) enable((*inhigh*)en0_0);\n\t\tmethod setDebug1 (v_debug0_1) enable((*inhigh*)en0_1);\n\t\tmethod setDebug2 (v_debug0_2) enable((*inhigh*)en0_2);\n\t\tmethod setDebug3 (v_debug0_3) enable((*inhigh*)en0_3);\n\t\tmethod setDebug4 (v_debug0_4) enable((*inhigh*)en0_4);\n\t\tmethod setDebug5_64 (v_debug0_5_64) enable((*inhigh*)en0_5);\n\t\tmethod setDebug6_64 (v_debug0_6_64) enable((*inhigh*)en0_6);\nendinterface\n\ninterface DebugILA ila1;\n\t\tmethod setDebug0 (v_debug1_0) enable((*inhigh*)en1_0);\n\t\tmethod setDebug1 (v_debug1_1) enable((*inhigh*)en1_1);\n\t\tmethod setDebug2 (v_debug1_2) enable((*inhigh*)en1_2);\n\t\tmethod setDebug3 (v_debug1_3) enable((*inhigh*)en1_3);\n\t\tmethod setDebug4 (v_debug1_4) enable((*inhigh*)en1_4);\n\t\tmethod setDebug5_64 (v_debug1_5_64) enable((*inhigh*)en1_5);\n\t\tmethod setDebug6_64 (v_debug1_6_64) enable((*inhigh*)en1_6);\nendinterface\n\ninterface DebugILA ila2;\n\t\tmethod setDebug0 (v_debug2_0) enable((*inhigh*)en2_0);\n\t\tmethod setDebug1 (v_debug2_1) enable((*inhigh*)en2_1);\n\t\tmethod setDebug2 (v_debug2_2) enable((*inhigh*)en2_2);\n\t\tmethod setDebug3 (v_debug2_3) enable((*inhigh*)en2_3);\n\t\tmethod setDebug4 (v_debug2_4) enable((*inhigh*)en2_4);\n\t\tmethod setDebug5_64 (v_debug2_5_64) enable((*inhigh*)en2_5);\n\t\tmethod setDebug6_64 (v_debug2_6_64) enable((*inhigh*)en2_6);\nendinterface\n\ninterface DebugILA ila3;\n\t\tmethod setDebug0 (v_debug3_0) enable((*inhigh*)en3_0);\n\t\tmethod setDebug1 (v_debug3_1) enable((*inhigh*)en3_1);\n\t\tmethod setDebug2 (v_debug3_2) enable((*inhigh*)en3_2);\n\t\tmethod setDebug3 (v_debug3_3) enable((*inhigh*)en3_3);\n\t\tmethod setDebug4 (v_debug3_4) enable((*inhigh*)en3_4);\n\t\tmethod setDebug5_64 (v_debug3_5_64) enable((*inhigh*)en3_5);\n\t\tmethod setDebug6_64 (v_debug3_6_64) enable((*inhigh*)en3_6);\nendinterface\n\ninterface DebugILA ila4;\n\t\tmethod setDebug0 (v_debug4_0) enable((*inhigh*)en4_0);\n\t\tmethod setDebug1 (v_debug4_1) enable((*inhigh*)en4_1);\n\t\tmethod setDebug2 (v_debug4_2) enable((*inhigh*)en4_2);\n\t\tmethod setDebug3 (v_debug4_3) enable((*inhigh*)en4_3);\n\t\tmethod setDebug4 (v_debug4_4) enable((*inhigh*)en4_4);\n\t\tmethod setDebug5_64 (v_debug4_5_64) enable((*inhigh*)en4_5);\n\t\tmethod setDebug6_64 (v_debug4_6_64) enable((*inhigh*)en4_6);\nendinterface\n\n\ninterface DebugILA ila5;\n\t\tmethod setDebug0 (v_debug5_0) enable((*inhigh*)en5_0);\n\t\tmethod setDebug1 (v_debug5_1) enable((*inhigh*)en5_1);\n\t\tmethod setDebug2 (v_debug5_2) enable((*inhigh*)en5_2);\n\t\tmethod setDebug3 (v_debug5_3) enable((*inhigh*)en5_3);\n\t\tmethod setDebug4 (v_debug5_4) enable((*inhigh*)en5_4);\n\t\tmethod setDebug5_64 (v_debug5_5_64) enable((*inhigh*)en5_5);\n\t\tmethod setDebug6_64 (v_debug5_6_64) enable((*inhigh*)en5_6);\nendinterface\n\ninterface DebugILA ila6;\n\t\tmethod setDebug0 (v_debug6_0) enable((*inhigh*)en6_0);\n\t\tmethod setDebug1 (v_debug6_1) enable((*inhigh*)en6_1);\n\t\tmethod setDebug2 (v_debug6_2) enable((*inhigh*)en6_2);\n\t\tmethod setDebug3 (v_debug6_3) enable((*inhigh*)en6_3);\n\t\tmethod setDebug4 (v_debug6_4) enable((*inhigh*)en6_4);\n\t\tmethod setDebug5_64 (v_debug6_5_64) enable((*inhigh*)en6_5);\n\t\tmethod setDebug6_64 (v_debug6_6_64) enable((*inhigh*)en6_6);\nendinterface\n\n\ninterface DebugILA ila7;\n\t\tmethod setDebug0 (v_debug7_0) enable((*inhigh*)en7_0);\n\t\tmethod setDebug1 (v_debug7_1) enable((*inhigh*)en7_1);\n\t\tmethod setDebug2 (v_debug7_2) enable((*inhigh*)en7_2);\n\t\tmethod setDebug3 (v_debug7_3) enable((*inhigh*)en7_3);\n\t\tmethod setDebug4 (v_debug7_4) enable((*inhigh*)en7_4);\n\t\tmethod setDebug5_64 (v_debug7_5_64) enable((*inhigh*)en7_5);\n\t\tmethod setDebug6_64 (v_debug7_6_64) enable((*inhigh*)en7_6);\nendinterface\n\nschedule \n(\n\tila0_setDebug0, ila0_setDebug1, ila0_setDebug2, ila0_setDebug3, ila0_setDebug4, ila0_setDebug5_64, ila0_setDebug6_64,\n\tila1_setDebug0, ila1_setDebug1, ila1_setDebug2, ila1_setDebug3, ila1_setDebug4, ila1_setDebug5_64, ila1_setDebug6_64,\n\tila2_setDebug0, ila2_setDebug1, ila2_setDebug2, ila2_setDebug3, ila2_setDebug4, ila2_setDebug5_64, ila2_setDebug6_64,\n\tila3_setDebug0, ila3_setDebug1, ila3_setDebug2, ila3_setDebug3, ila3_setDebug4, ila3_setDebug5_64, ila3_setDebug6_64,\n\tila4_setDebug0, ila4_setDebug1, ila4_setDebug2, ila4_setDebug3, ila4_setDebug4, ila4_setDebug5_64, ila4_setDebug6_64,\n\tila5_setDebug0, ila5_setDebug1, ila5_setDebug2, ila5_setDebug3, ila5_setDebug4, ila5_setDebug5_64, ila5_setDebug6_64,\n\tila6_setDebug0, ila6_setDebug1, ila6_setDebug2, ila6_setDebug3, ila6_setDebug4, ila6_setDebug5_64, ila6_setDebug6_64,\n\tila7_setDebug0, ila7_setDebug1, ila7_setDebug2, ila7_setDebug3, ila7_setDebug4, ila7_setDebug5_64, ila7_setDebug6_64,\n\tvio_setDebugVin, vio_getDebugVout\n)\nCF\n(\n\tila0_setDebug0, ila0_setDebug1, ila0_setDebug2, ila0_setDebug3, ila0_setDebug4, ila0_setDebug5_64, ila0_setDebug6_64,\n\tila1_setDebug0, ila1_setDebug1, ila1_setDebug2, ila1_setDebug3, ila1_setDebug4, ila1_setDebug5_64, ila1_setDebug6_64,\n\tila2_setDebug0, ila2_setDebug1, ila2_setDebug2, ila2_setDebug3, ila2_setDebug4, ila2_setDebug5_64, ila2_setDebug6_64,\n\tila3_setDebug0, ila3_setDebug1, ila3_setDebug2, ila3_setDebug3, ila3_setDebug4, ila3_setDebug5_64, ila3_setDebug6_64,\n\tila4_setDebug0, ila4_setDebug1, ila4_setDebug2, ila4_setDebug3, ila4_setDebug4, ila4_setDebug5_64, ila4_setDebug6_64,\n\tila5_setDebug0, ila5_setDebug1, ila5_setDebug2, ila5_setDebug3, ila5_setDebug4, ila5_setDebug5_64, ila5_setDebug6_64,\n\tila6_setDebug0, ila6_setDebug1, ila6_setDebug2, ila6_setDebug3, ila6_setDebug4, ila6_setDebug5_64, ila6_setDebug6_64,\n\tila7_setDebug0, ila7_setDebug1, ila7_setDebug2, ila7_setDebug3, ila7_setDebug4, ila7_setDebug5_64, ila7_setDebug6_64,\n\tvio_setDebugVin, vio_getDebugVout\n);\n\nendmodule\n"
  },
  {
    "path": "tests/algo1_flashmodel/ControllerTypes.bsv",
    "content": "`include \"ConnectalProjectConfig.bsv\"\nimport FShow::*;\n\n//**********************************************************\n// Type definitions of the flash controller and submodules\n//**********************************************************\n\n//NAND geometry\n//Actual page size is 8640B, but we don't need the last 40B for ECC\n//Valid Data: 2 x (243B x 16 + 208B) = 8192B; \n//With ECC: 2 x (255B x 16 + 220B) = 8600\ntypedef 8600 \t\t\tPageSize;\ntypedef 8192 \t\t\tPageSizeUser;\ntypedef 17 \t\t\t\tPageECCBlks; //16 blocks of k=243; 1 block of k=208\n`ifdef SIMULATION\n\ttypedef 16 \t\t\tPagesPerBlock;\n\ttypedef 128\t\t\tBlocksPerCE;\n\ttypedef 8 \t\t\tChipsPerBus;\n`elsif SLC\n\ttypedef 128 \t\tPagesPerBlock;\n\ttypedef 8192 \t\tBlocksPerCE;\n\ttypedef 4 \t\t\tChipsPerBus;\n`else //MLC\n\ttypedef 256\t\t \tPagesPerBlock;\n\ttypedef 4096 \t\tBlocksPerCE;\n\ttypedef 8 \t\t\tChipsPerBus;\n`endif \n\ntypedef 2\t\t\t\t\t\t\t\t\t\t\tBusWordBytes;\ntypedef TMul#(8, BusWordBytes) \t\t\t\tBusWordSz;\ntypedef 16 \t\t\t\t\t\t\t\t\t\t\tWordBytes;\ntypedef TLog#(WordBytes)\t\t\t\t\t\tWordBytesLog;\ntypedef TMul#(8,WordBytes) \t\t\t\t\tWordSz;\n//Each burst is 128 bits via the controller interface\ntypedef TDiv#(PageSizeUser, WordBytes) \tPageWords;\ntypedef TMul#(TMul#(BlocksPerCE, PagesPerBlock), PageWords) WordsPerChip;\n\ntypedef WordSz FlashDataWidth;\ntypedef 44  FlashAddrWidth;\n\nInteger pageSize \t\t\t= valueOf(PageSize); //bytes\nInteger pageSizeUser \t= valueOf(PageSizeUser); //usable page size is 8k\nInteger pageECCBlks \t\t= valueOf(PageECCBlks); //16 blocks of k=243; 1 block of k=208\nInteger pagesPerBlock \t= valueOf(PagesPerBlock);\nInteger blocksPerCE \t\t= valueOf(BlocksPerCE);\nInteger chipsPerBus\t\t= valueOf(ChipsPerBus);\nInteger wordBytes \t\t= valueOf(WordBytes);\nInteger pageWords \t\t= valueOf(PageWords);\n//Integer blocksPerPlane = 2048;\n//Integer planesPerLun = 2;\n//Integer lunsPerTarget = 1; //1 for SLC, 2 for MLC\n\n\n`ifdef NAND_SIM\n\ttypedef 1 NUM_CHIPBUSES;\n`else\n\ttypedef 4 NUM_CHIPBUSES; \n`endif\n\t\ntypedef 2 BUSES_PER_CHIPBUS;\ntypedef TMul#(NUM_CHIPBUSES, BUSES_PER_CHIPBUS) NUM_BUSES;\n\ntypedef 8 NUM_DEBUG_ILAS;\n\ntypedef TMul#(NUM_BUSES, ChipsPerBus) NUM_TOTAL_CHIPS;\n\n\ntypedef 128 NumTags;\n//typedef Bit#(TLog#(TDiv#(NumTags, NUM_BUSES))) BusTagT;\ntypedef Bit#(TLog#(NumTags)) TagT;\ntypedef Bit#(TLog#(ChipsPerBus)) ChipT;\ntypedef Bit#(TLog#(NUM_BUSES)) BusT;\n\nInteger num_tags = valueOf(NumTags);\nInteger num_buses = valueOf(NUM_BUSES);\n\ntypedef enum {\n\tSRC_HOST,\n\tSRC_USER_HW\n} SourceT deriving (Bits, Eq, FShow);\n\ntypedef enum {\n\tERASE_ERROR, \n   ERASE_DONE, \n\tWRITE_DONE\n} StatusT deriving (Bits, Eq);\n\n\n\n//----------------------\n//Aurora related types\n//----------------------\ntypedef enum {\n\tF_CMD,\n\tF_DATA,\n\tF_ACK,\n\tF_WR_REQ\n} PacketClass deriving (Bits, Eq);\n\n\n//----------------------\n//Phy related types\n//----------------------\ntypedef enum {\n\tPHY_CHIP_SEL,\n\tPHY_DESELECT_ALL,\n\tPHY_CMD,\n\tPHY_READ,\n\tPHY_WRITE,\n\tPHY_ADDR,\n\tPHY_SYNC_CALIB,\n\tPHY_ENABLE_NAND_CLK\n} PhyCycle deriving (Bits, Eq);\n\ntypedef enum {\n\tN_RESET = 8'hFF,\n\tN_READ_STATUS = 8'h70,\n\tN_SET_FEATURES = 8'hEF,\n\tN_PROGRAM_PAGE = 8'h80,\n\tN_PROGRAM_PAGE_END = 8'h10,\n\tN_READ_MODE = 8'h00,\n\tN_READ_PAGE_END = 8'h30,\n\tN_ERASE_BLOCK = 8'h60,\n\tN_ERASE_BLOCK_END = 8'hD0,\n\tN_READ_ID = 8'h90\n\n} ONFICmd deriving (Bits, Eq);\n\n//using tagged union\ntypedef union tagged {\n\tONFICmd OnfiCmd;\n\tChipT ChipSel;\n} NandCmd deriving (Bits);\n\ntypedef struct {\n\tBool inSyncMode;\n\tPhyCycle phyCycle;\n\tNandCmd nandCmd;\n\tBit#(16) numBurst;\n\tBit#(32) postCmdWait; //number of cycles to wait after the command\n} PhyCmd deriving (Bits);\n\n\n\n\n//---------------------------------\n// Bus controller related types\n//---------------------------------\ntypedef enum {\n\t//INIT_BUS,\n\t//EN_SYNC,\n\t//INIT_SYNC,\n\t//READ_DATA,\n\tREAD_CMD,\n\tGET_STATUS_READ_DATA,\n\tWRITE_DATA_BUF_REQ,\n\tWRITE_CMD_DATA,\n\tWRITE_GET_STATUS, \n\tERASE_CMD,\n\tERASE_GET_STATUS,\n\tINVALID\n} BusOp deriving (Bits, Eq);\n\ntypedef struct {\n\tTagT tag;\n\tBusOp busOp;\n\tChipT chip;\n\tBit#(16) block;\n\tBit#(8) page;\n} BusCmd deriving (Bits, Eq);\n\n\n//---------------------------------\n// Flash controller related types\n//---------------------------------\n\ntypedef enum {\n\tINIT_BUS,\n\tEN_SYNC,\n\tINIT_SYNC,\n\tREAD_PAGE,\n\tWRITE_PAGE,\n\tERASE_BLOCK,\n\tINVALID\n} FlashOp deriving (Bits, Eq);\n\ntypedef struct {\n\tTagT tag;\n\tFlashOp op;\n\tBusT bus; //3\n\tChipT chip; //3\n\tBit#(16) block;\n\tBit#(8) page;\n} FlashCmd deriving (Bits, Eq);\n\ntypedef struct {\n\tBit#(8) page;\n\tBit#(16) block;\n\tChipT chip;\n\tBusT bus;\n} FlashAddr deriving (Bits, Eq);\n\n// Flash Controller User Ifc\ninterface FlashCtrlUser;\n\tmethod Action sendCmd (FlashCmd cmd);\n\tmethod Action writeWord (Tuple2#(Bit#(128), TagT) taggedData);\n\tmethod ActionValue#(Tuple2#(Bit#(128), TagT)) readWord (); \n\tmethod ActionValue#(TagT) writeDataReq(); \n\tmethod ActionValue#(Tuple2#(TagT, StatusT)) ackStatus (); \nendinterface\n\ninstance FShow#(BusOp);\n\tfunction Fmt fshow (BusOp label);\n\t\tcase(label)\n\t\t\tREAD_CMD: return fshow(\"BUSOP READ_CMD\");\n\t\t\tGET_STATUS_READ_DATA: return fshow(\"BUSOP GET_STATUS_READ_DATA\");\n\t\t\tWRITE_CMD_DATA: return fshow(\"BUSOP WRITE_CMD_DATA\");\n\t\t\tERASE_CMD: return fshow(\"BUSOP ERASE_CMD\");\n\t\t\tWRITE_GET_STATUS: return fshow(\"BUSOP WRITE_GET_STATUS\");\n\t\t\tWRITE_DATA_BUF_REQ: return fshow(\"BUSOP WRITE_DATA_BUF_REQ\");\n\t\t\tERASE_GET_STATUS: return fshow(\"BUSOP ERASE_GET_STATUS\");\n\t\t\tINVALID: return fshow(\"BUSOP INVALID\");\n\t\tendcase\n\tendfunction\nendinstance\n\n\n"
  },
  {
    "path": "tests/algo1_flashmodel/FlashBusModel.bsv",
    "content": "import FIFOF::*;\nimport FIFO::*;\nimport BRAMFIFO::*;\nimport BRAM::*;\nimport GetPut::*;\nimport ClientServer::*;\nimport Vector::*;\nimport RegFile::*;\n\nimport ControllerTypes::*;\n\n//For SIMULATION: use hashed read data (so we don't have to write before read)\ntypedef 1 SIMULATION_USE_HASHED_DATA; \n\ntypedef enum {\n\tST_CMD,\n\tST_OP_DELAY,\n\tST_BUS_RESERVE,\n\tST_WRITE_BUS_RESERVE,\n\tST_WRITE_REQ,\n\tST_ERASE,\n\tST_ERROR,\n\tST_READ_TRANSFER,\n\tST_WRITE_DATA,\n\tST_WRITE_ACK,\n\tST_READ_DATA\n} ChipState deriving (Bits, Eq);\n\n\nfunction Bit#(TLog#(WordsPerChip)) getRegAddr (Bit#(16) block, Bit#(8) page, Bit#(16) burstCnt);\n\tBit#(64) blockExt = zeroExtend(block);\n\tBit#(64) pageExt = zeroExtend(page);\n\tBit#(64) burstCntExt = zeroExtend(burstCnt);\n\tBit#(64) regAddr = (blockExt<<(log2(pageWords*pagesPerBlock))) + (pageExt<<log2(pageWords)) + burstCntExt;\n\treturn truncate(regAddr);\nendfunction\n\n\n\nfunction Bit#(128) getDataHash (Bit#(16) dataCnt, Bit#(8) page, Bit#(16) block, ChipT chip, BusT bus);\n\t/*\n\tBit#(8) dataCntTrim = truncate(dataCnt << 3);\n\tBit#(8) blockTrim = truncate(block);\n\tBit#(8) chipTrim = zeroExtend(chip);\n\tBit#(8) busTrim = zeroExtend(bus);\n\n\tVector#(8, Bit#(16)) dataAggr = newVector();\n\tfor (Integer i=7; i >= 0; i=i-1) begin\n\t\tBit#(8) dataHi = truncate(dataCntTrim + fromInteger(i) + 8'hA0 + (blockTrim<<4)+ (chipTrim<<2) + (busTrim<<6));\n\t\tBit#(8) dataLow = truncate( (~dataHi) + blockTrim );\n\t\tdataAggr[i] = {dataHi, dataLow};\n\tend\n\treturn pack(dataAggr);\n\t*/\n\t//FIXME tmp hashing for debug\n\tBit#(128) busEx = zeroExtend(bus);\n\tBit#(128) chipEx = zeroExtend(chip);\n\tBit#(128) blockEx = zeroExtend(block);\n\tBit#(128) pageEx = zeroExtend(page);\n\tBit#(128) dataCntEx = zeroExtend(dataCnt);\n\tBit#(128) dataRet = zeroExtend( (busEx<<64) + (chipEx<<48) + (blockEx<<32) + (pageEx<<16) + dataCntEx );\n\treturn dataRet;\n\n\nendfunction\n\n\ninterface FlashBusModelIfc;\n\tmethod Action sendCmd(FlashCmd cmd);\n\tmethod Action writeWord (Tuple2#(Bit#(128), TagT) taggedData);\n\tmethod ActionValue#(Tuple2#(Bit#(128), TagT)) readWord ();\n\tmethod ActionValue#(TagT) writeDataReq();\n\tmethod ActionValue#(Tuple2#(TagT, StatusT)) ackStatus ();\nendinterface\n\n(* synthesize *)\n(* descending_urgency = \"chipWriteAck, chipWriteAck_1, chipWriteAck_2, chipWriteAck_3, chipWriteAck_4, chipWriteAck_5, chipWriteAck_6, chipWriteAck_7\" *) \nmodule mkFlashBusModel(FlashBusModelIfc);\n\t\n\tInteger t_Read = 750; //read delay\n\tInteger t_Write = 5000; //write delay\n\tInteger t_Erase = 15000; //erase delay\n\tInteger burstDelay = 7; //read bursts 128 bits every 8 cycles //TODO adjust this \n\n\t//Create a regfile per chip\n\tVector#(ChipsPerBus, RegFile#(Bit#(TLog#(WordsPerChip)), Bit#(128))) flashArr <- replicateM(mkRegFileFull());\n\n\t\n\t//enq commands to each chip (emulated sb)\n\tVector#(ChipsPerBus, FIFO#(FlashCmd)) flashChipCmdQs <- replicateM(mkSizedFIFO(16));\n\tFIFO#(Tuple2#(Bit#(WordSz), TagT)) busReadQ <- mkFIFO();\n\tReg#(Bool) busInUse <- mkReg(False);\n\tReg#(ChipT) busReservedChipIdx <- mkReg(0);\n\tFIFO#(Tuple2#(TagT, StatusT)) ackQ <- mkSizedFIFO(valueOf(NumTags));\n\tFIFOF#(TagT) writeReqQ <- mkSizedFIFOF(3); \n\tReg#(Bit#(4)) writeDataReqIssued <- mkReg(0);\n\tReg#(Bit#(4)) writeDataReqProcessed <- mkReg(0);\n\t//2 page buffer\n\tFIFOF#(Tuple2#(Bit#(WordSz), TagT)) writeBuffer <- mkSizedFIFOF(pageWords*2+1);\n\t//simulate the round robin sb using a counter\n\tReg#(Bit#(16)) chipSel <- mkReg(0);\n\tReg#(Bit#(64)) cycleCnt <- mkReg(0);\n\t\n\trule incCycleCnt;\n\t\tcycleCnt <= cycleCnt + 1;\n\tendrule\n\n\trule checkWriteReqFull if (!writeReqQ.notFull);\n\t\t$display(\"**ERROR: FlashBusModel: Write data request buffer should never be full\");\n\tendrule\n\n\trule checkWriteBufferFull if (!writeBuffer.notFull);\n\t\t$display(\"**ERROR: FlashBusModel: Write buffer should never be full\");\n\tendrule\n\n\trule chipSelIncr;\n\t\tif (chipSel == fromInteger(chipsPerBus-1)) begin\n\t\t\tchipSel <= 0;\n\t\tend\n\t\telse begin\n\t\t\tchipSel <= chipSel + 1;\n\t\tend\n\t\t//$display(\"chipSel=%d\", chipSel);\n\tendrule\n\n\n\tfor (Integer c=0; c<chipsPerBus; c=c+1) begin\n\t\tReg#(ChipState) chipSt <- mkReg(ST_CMD);\n\t\tReg#(ChipState) chipStReturn <- mkReg(ST_CMD);\n\t\tReg#(Bit#(32)) delayCnt <- mkReg(0);\n\t\tReg#(Bit#(16)) readDlyCnt <- mkReg(fromInteger(burstDelay));\n\t\tReg#(Bit#(16)) wrDlyCnt <- mkReg(fromInteger(burstDelay));\n\t\tReg#(Bit#(16)) readBurstCnt <- mkReg(0);\n\t\tReg#(Bit#(16)) writeBurstCnt <-  mkReg(0);\n\n\t\trule chipHandleCmd if (chipSt==ST_CMD);\n\t\t\tlet cmd = flashChipCmdQs[c].first;\n\t\t\tif (cmd.page > fromInteger(pagesPerBlock-1)) begin\n\t\t\t\t$display(\"**ERROR: cmd page exceeds simulation pages available. Sim pages=%d\", pagesPerBlock);\n\t\t\t\tchipSt <= ST_ERROR;\n\t\t\tend\n\t\t\telse if (cmd.block > fromInteger(blocksPerCE-1)) begin\n\t\t\t\t$display(\"**ERROR: cmd block exceeds simulation blocks available. Sim blocks=%d\", blocksPerCE);\n\t\t\t\tchipSt <= ST_ERROR;\n\t\t\tend\n\t\t\telse begin\n\t\t\t\tcase (cmd.op) \n\t\t\t\t\tREAD_PAGE: \n\t\t\t\t\t\tbegin\n\t\t\t\t\t\t\tdelayCnt <= fromInteger(t_Read);\n\t\t\t\t\t\t\tchipSt <= ST_OP_DELAY;\n\t\t\t\t\t\t\tchipStReturn <= ST_BUS_RESERVE;\n\t\t\t\t\t\t\t$display(\"@%d %m FlashBus chip[%d] starting READ cmd...\", cycleCnt, cmd.chip);\n\t\t\t\t\t\tend\n\t\t\t\t\tWRITE_PAGE:\n\t\t\t\t\t\tbegin\n\t\t\t\t\t\t\tchipSt <= ST_WRITE_REQ;\n\t\t\t\t\t\t\tdelayCnt <= fromInteger(t_Write);\n\t\t\t\t\t\t\t$display(\"@%d %m FlashBus chip[%d] starting WRITE cmd...\", cycleCnt, cmd.chip);\n\t\t\t\t\t\tend\n\t\t\t\t\tERASE_BLOCK:\n\t\t\t\t\t\tbegin\n\t\t\t\t\t\t\tchipSt <= ST_OP_DELAY;\n\t\t\t\t\t\t\tchipStReturn <= ST_ERASE;\n\t\t\t\t\t\t\tdelayCnt <= fromInteger(t_Erase);\n\t\t\t\t\t\t\t$display(\"@%d %m FlashBus chip[%d] starting ERASE cmd...\", cycleCnt, cmd.chip);\n\t\t\t\t\t\tend\n\t\t\t\t\tdefault: \n\t\t\t\t\t\tbegin\n\t\t\t\t\t\t\tchipSt <= ST_ERROR;//throw error TODO\n\t\t\t\t\t\t\t$display(\"**ERROR: FlashBusModel invalid op\");\n\t\t\t\t\t\tend\n\t\t\t\tendcase\n\t\t\tend\n\t\tendrule\n\n\t\t\t\n\n\t\t//wait rule (tRead, tWrite, tErase)\n\t\trule chipOpDelay if (chipSt==ST_OP_DELAY);\n\t\t\tif (delayCnt==0) begin\n\t\t\t\tchipSt <= chipStReturn;\n\t\t\t\t$display(\"%m FlashBus chip[%d] op delay done\", c);\n\t\t\tend\n\t\t\telse begin\n\t\t\t\tdelayCnt <= delayCnt-1;\n\t\t\tend\n\t\tendrule\n\n\t\t//READ: take control of bus\n\t\trule chipReadBusReserve if (chipSt==ST_BUS_RESERVE && !busInUse && chipSel==fromInteger(c));\n\t\t\tbusReservedChipIdx <= fromInteger(c);\n\t\t\tbusInUse <= True;\n\t\t\tchipSt <= ST_READ_TRANSFER;\n\t\t\t$display(\"@%d %m FlashBus reserved bus for chip = %d\", cycleCnt, c);\n\t\tendrule\n\n\t\t//READ: transfer read only if selected and bus is reserved\n\t\trule chipReadTransfer if (chipSt==ST_READ_TRANSFER && busInUse && busReservedChipIdx==fromInteger(c));\n\t\t\tlet cmd = flashChipCmdQs[c].first;\n\t\t\t//transfer 128bits every 8 cycles (to emulate flash behavior)\n\t\t\tif (readDlyCnt > 0) begin\n\t\t\t\treadDlyCnt <= readDlyCnt - 1;\n\t\t\tend\n\t\t\telse begin\n\t\t\t\treadDlyCnt <= fromInteger(burstDelay);\n\t\t\t\tif (valueOf(BSIM_USE_HASHED_DATA)==1) begin\n\t\t\t\t\tlet dataHashed = getDataHash (readBurstCnt, cmd.page, cmd.block, cmd.chip, cmd.bus);\n\t\t\t\t\tbusReadQ.enq(tuple2(dataHashed, cmd.tag));\n\t\t\t\t\t$display(\"@%d %m FlashBus chip[%d] read data tag=%d @ [%d][%d][%d] = %x\", cycleCnt, c, cmd.tag, cmd.block, cmd.page, readBurstCnt, dataHashed);\n\t\t\t\tend\n\t\t\t\telse begin\n\t\t\t\t\t//compute addr in regfile\n\t\t\t\t\tlet regAddr = getRegAddr(cmd.block, cmd.page, readBurstCnt); \n\t\t\t\t\tlet rdata = flashArr[c].sub(regAddr);\n\n\t\t\t\t\tbusReadQ.enq(tuple2(rdata, cmd.tag));\n\t\t\t\t\t$display(\"@%d %m FlashBus chip[%d] read data tag=%d @ regAddr=%d [%d][%d][%d] = %x\", cycleCnt, c, regAddr, cmd.tag, cmd.block, cmd.page, readBurstCnt, rdata);\n\t\t\t\tend\n\t\t\t\tif (readBurstCnt==fromInteger(pageWords-1)) begin\n\t\t\t\t\tflashChipCmdQs[c].deq;\n\t\t\t\t\treadBurstCnt <= 0;\n\t\t\t\t\tchipSt <= ST_CMD;\n\t\t\t\t\tbusInUse <= False;\n\t\t\t\t\t$display(\"@%d %m FlashBus chip[%d] done read\", cycleCnt, cmd.chip);\n\t\t\t\tend\n\t\t\t\telse begin\n\t\t\t\t\treadBurstCnt <= readBurstCnt + 1;\n\t\t\t\tend\n\t\t\tend\n\n\t\tendrule\n\n\t\t//write request for data; when selected and have enough page buffers\n\t\trule chipWriteDataReq if (chipSt==ST_WRITE_REQ && chipSel==fromInteger(c) \n\t\t\t\t\t\t\t\t\t\t\t&& (writeDataReqIssued - writeDataReqProcessed) < 2);\n\t\t\tlet cmd = flashChipCmdQs[c].first;\n\t\t\twriteReqQ.enq(cmd.tag);\n\t\t\tchipSt <= ST_WRITE_BUS_RESERVE;\n\t\t\twriteDataReqIssued <= writeDataReqIssued + 1;\n\t\t\t$display(\"@%d %m FlashBus chip[%d] writeDataReq issued, tag=%d\", cycleCnt, c, cmd.tag);\n\t\tendrule\n\n\t\t//write data reserve bus\n\t\trule chipWriteBusReserve if (chipSt==ST_WRITE_BUS_RESERVE && !busInUse \n\t\t\t\t\t\t\t\t\t\t\t\t&& flashChipCmdQs[c].first.tag==tpl_2(writeBuffer.first)\n\t\t\t\t\t\t\t\t\t\t\t\t&& chipSel==fromInteger(c)\t);\n\t\t\tbusReservedChipIdx <= fromInteger(c);\n\t\t\tbusInUse <= True;\n\t\t\tchipSt <= ST_WRITE_DATA;\n\t\t\t$display(\"@%d %m FlashBus chip[%d] write bus reserved\", cycleCnt, c);\n\t\tendrule\n\t\n\t\t//write data every 8 cycles\n\t\trule chipWriteData if (chipSt==ST_WRITE_DATA && busInUse && busReservedChipIdx==fromInteger(c));\n\t\t\tlet cmd = flashChipCmdQs[c].first;\n\t\t\tif (wrDlyCnt > 0) begin\n\t\t\t\twrDlyCnt <= wrDlyCnt - 1;\n\t\t\tend\n\t\t\telse begin\n\t\t\t\twrDlyCnt <= fromInteger(burstDelay);\n\t\t\t\tif (cmd.tag==tpl_2(writeBuffer.first)) begin\n\t\t\t\t\tlet regAddr = getRegAddr(cmd.block, cmd.page, writeBurstCnt); \n\t\t\t\t\tflashArr[c].upd(regAddr, tpl_1(writeBuffer.first));\n\t\t\t\t\twriteBuffer.deq;\n\t\t\t\t\t$display(\"@%d %m FlashBus chip[%d] wrote data @ regAddr=%d [%d][%d][%d] = %x\", cycleCnt, c,regAddr, cmd.block, cmd.page, writeBurstCnt, tpl_1(writeBuffer.first));\n\t\t\t\tend\n\t\t\t\telse begin\n\t\t\t\t\t$display(\"**ERROR: FlashBusModel incorrect burst received. Cmd tag=%d, burst tag=%d\",\n\t\t\t\t\t\t\t\tflashChipCmdQs[c].first.tag, tpl_2(writeBuffer.first));\n\t\t\t\tend\n\n\t\t\t\tif (writeBurstCnt==fromInteger(pageWords-1)) begin //done transfer\n\t\t\t\t\t$display(\"@%d %m FlashBus chip[%d] write done transfer\", cycleCnt, c);\n\t\t\t\t\t//wait tWrite\n\t\t\t\t\tchipSt <= ST_OP_DELAY;\n\t\t\t\t\tchipStReturn <= ST_WRITE_ACK;\n\t\t\t\t\twriteDataReqProcessed <= writeDataReqProcessed + 1;\n\t\t\t\t\tbusInUse <= False;\n\t\t\t\t\twriteBurstCnt <= 0;\n\t\t\t\tend\n\t\t\t\telse begin\n\t\t\t\t\twriteBurstCnt <= writeBurstCnt + 1;\n\t\t\t\tend\n\t\t\tend\n\t\tendrule\n\n\t\t//write ack\n\t\trule chipWriteAck if (chipSt==ST_WRITE_ACK);\n\t\t\tlet cmd = flashChipCmdQs[c].first;\n\t\t\tflashChipCmdQs[c].deq;\n\t\t\tackQ.enq(tuple2(cmd.tag, WRITE_DONE));\n\t\t\tchipSt <= ST_CMD;\n\t\t\t$display(\"%m FlashBus chip[%d] write ack tag=%d\", c, cmd.tag);\n\t\tendrule\n\n\t\t//erase\n\t\tReg#(Bit#(16)) eraseWordCnt <- mkReg(0);\n\t\tReg#(Bit#(8)) erasePageCnt <- mkReg(0);\n\t\trule chipErase if (chipSt==ST_ERASE);\n\t\t\tlet cmd = flashChipCmdQs[c].first;\n\t\t\t//erase entire block\n\t\t\tlet regAddr = getRegAddr(cmd.block, erasePageCnt, eraseWordCnt);\n\t\t\tflashArr[c].upd(regAddr, -1);\n\t\t\t$display(\"%m FlashBus chip[%d] erasing tag=%d, blk = %d, pageCnt = %d, wordCnt = %d\", c, cmd.tag, cmd.block, erasePageCnt, eraseWordCnt);\n\n\t\t\tif (eraseWordCnt == fromInteger(pageWords-1)) begin //done page\n\t\t\t\teraseWordCnt <= 0;\n\t\t\t\tif (erasePageCnt == fromInteger(pagesPerBlock-1)) begin //done block\n\t\t\t\t\tflashChipCmdQs[c].deq;\n\t\t\t\t\terasePageCnt <= 0;\n\t\t\t\t\tackQ.enq(tuple2(cmd.tag, ERASE_DONE));\n\t\t\t\t\tchipSt <= ST_CMD;\n\t\t\t\tend\n\t\t\t\telse begin\n\t\t\t\t\terasePageCnt <= erasePageCnt + 1;\n\t\t\t\tend\n\t\t\tend\n\t\t\telse begin\n\t\t\t\teraseWordCnt <= eraseWordCnt + 1;\n\t\t\tend\n\t\tendrule\n\n\t\trule errorState if (chipSt==ST_ERROR);\n\t\t\t$display(\"**ERROR: FlashBusModel chip[%d] in error state\", c);\n\t\tendrule\n\tend //chipsPerBus\n\n\tmethod Action sendCmd(FlashCmd cmd);\n\t\tflashChipCmdQs[cmd.chip].enq(cmd);\n\tendmethod\n\n\tmethod Action writeWord (Tuple2#(Bit#(128), TagT) taggedData);\n\t\twriteBuffer.enq(taggedData);\n\tendmethod\n\n\tmethod ActionValue#(Tuple2#(Bit#(128), TagT)) readWord ();\n\t\tbusReadQ.deq;\n\t\treturn busReadQ.first;\n\tendmethod\n\n\tmethod ActionValue#(TagT) writeDataReq();\n\t\twriteReqQ.deq;\n\t\treturn writeReqQ.first;\n\tendmethod\n\n\tmethod ActionValue#(Tuple2#(TagT, StatusT)) ackStatus ();\n\t\tackQ.deq;\n\t\treturn ackQ.first;\n\tendmethod\n\n\n\nendmodule\n"
  },
  {
    "path": "tests/algo1_flashmodel/FlashCtrlModel.bsv",
    "content": "import FIFOF::*;\nimport FIFO::*;\nimport BRAMFIFO::*;\nimport BRAM::*;\nimport GetPut::*;\nimport ClientServer::*;\nimport Vector::*;\nimport RegFile::*;\n\n\nimport AuroraCommon::*;\nimport AuroraGearbox::*;\nimport AuroraImportFmc1::*;\nimport ControllerTypes::*;\n//import FlashCtrlVirtex::*;\nimport FlashBusModel::*;\n\n//simulator options\n//Integer SIMULATION_CHIPS_PER_BUS \t= 2;\n//Integer SIMULATION_BLOCKS_PER_CHIP \t= 2;\n//Integer SIMULATION_PAGES_PER_BLOCK\t= 2;\n//Integer SIMULATION_BUSES\t\t\t\t= 4;\n\n//use hashed read data (so we don't have to write before read)\n//Integer SIMULATION_USE_HASHED_DATA\t= 1; \n\n/*\ninterface FlashCtrlUser;\n\tmethod Action sendCmd (FlashCmd cmd);\n\tmethod Action writeWord (Bit#(128) data, TagT tag);\n\tmethod ActionValue#(Tuple2#(Bit#(128), TagT)) readWord ();\n\tmethod ActionValue#(TagT) writeDataReq();\n\tmethod ActionValue#(Tuple2#(TagT, StatusT)) ackStatus ();\nendinterface\ninterface FlashCtrlVirtexIfc;\n\tinterface FlashCtrlUser user;\n\tinterface Aurora_Pins#(4) aurora;\n\tinterface FCVirtexDebug debug;\nendinterface\n*/\n\n\ninterface FCVirtexDebug;\n\tmethod Tuple2#(DataIfc, PacketType) debugRecPacket();\n\tmethod Tuple4#(Bit#(32), Bit#(32), Bit#(32), Bit#(32)) getDebugCnts;\nendinterface\n\ninterface FlashCtrlVirtexIfc;\n\tinterface FlashCtrlUser user;\n\tinterface Aurora_Pins#(4) aurora;\n\tinterface FCVirtexDebug debug;\nendinterface\n\n\n(* synthesize *)\n(* descending_urgency = \"forwardReads, forwardReads_1, forwardReads_2, forwardReads_3, forwardReads_4, forwardReads_5, forwardReads_6, forwardReads_7\" *) \n(* descending_urgency = \"forwardWrDataReq, forwardWrDataReq_1, forwardWrDataReq_2, forwardWrDataReq_3, forwardWrDataReq_4, forwardWrDataReq_5, forwardWrDataReq_6, forwardWrDataReq_7\" *)\n(* descending_urgency = \"forwardAck, forwardAck_1, forwardAck_2, forwardAck_3, forwardAck_4, forwardAck_5, forwardAck_6, forwardAck_7\" *)\nmodule mkFlashCtrlModel#(\n\tClock gtx_clk_p, Clock gtx_clk_n, Clock clk250) (FlashCtrlVirtexIfc);\n\n\t//Flash bus models\n\tVector#(NUM_BUSES, FlashBusModelIfc) flashBuses <- replicateM(mkFlashBusModel());\n\n\tRegFile#(TagT, FlashCmd) tagTable <- mkRegFileFull();\n\tFIFO#(Tuple2#(Bit#(WordSz), TagT)) rdDataQ <- mkSizedFIFO(16); //TODO size?\n\tFIFO#(TagT) wrDataReqQ <- mkSizedFIFO(16);\n\tFIFO#(Tuple2#(TagT, StatusT)) ackQ <- mkSizedFIFO(16);\n\t\n\t//GTX-GTP Aurora. Unused in model\n\tAuroraIfc auroraIntra <- mkAuroraIntra(gtx_clk_p, gtx_clk_n, clk250);\n\n\n\t//handle reads, acks, writedataReq\n\tfor (Integer b=0; b < valueOf(NUM_BUSES); b=b+1) begin\n\t\trule forwardReads;\n\t\t\tlet rd <- flashBuses[b].readWord();\n\t\t\trdDataQ.enq(rd);\n\t\tendrule\n\n\t\trule forwardWrDataReq;\n\t\t\tlet req <- flashBuses[b].writeDataReq();\n\t\t\twrDataReqQ.enq(req);\n\t\tendrule\n\t\n\t\trule forwardAck;\n\t\t\tlet ack <- flashBuses[b].ackStatus();\n\t\t\tackQ.enq(ack);\n\t\tendrule\n\tend\n\n\n\tinterface FlashCtrlUser user;\n\t\tmethod Action sendCmd (FlashCmd cmd);\n\t\t\ttagTable.upd(cmd.tag, cmd);\n\t\t\tflashBuses[cmd.bus].sendCmd(cmd);\n\t\t\t$display(\"FlashEmu: received cmd: tag=%d, bus=%d, chip=%d, blk=%d, page=%d\", cmd.tag, cmd.bus, cmd.chip, cmd.block, cmd.page);\n\t\tendmethod\n\t\tmethod Action writeWord (Tuple2#(Bit#(WordSz), TagT) taggedData);\n\t\t\tFlashCmd cmd = tagTable.sub(tpl_2(taggedData));\n\t\t\tflashBuses[cmd.bus].writeWord(taggedData);\n\t\tendmethod\n\t\t\t\n\t\tmethod ActionValue#(Tuple2#(Bit#(WordSz), TagT)) readWord ();\n\t\t\trdDataQ.deq();\n\t\t\treturn rdDataQ.first();\n\t\tendmethod\n\n\t\tmethod ActionValue#(TagT) writeDataReq();\n\t\t\twrDataReqQ.deq();\n\t\t\treturn wrDataReqQ.first();\n\t\tendmethod\n\n\t\tmethod ActionValue#(Tuple2#(TagT, StatusT)) ackStatus();\n\t\t\tackQ.deq();\n\t\t\treturn ackQ.first();\n\t\tendmethod\n\tendinterface\n\n\tinterface FCVirtexDebug debug = ?;\n\n\tinterface Aurora_Pins aurora = auroraIntra.aurora;\n\nendmodule\n\n\n\n\t/*\n\trule doHandleCmd if (state==SEND_DATA);\n\t\tFlashCmd cmd = flashCmdQ.first;\n\t\tBit#(16) data0 = truncate(rdataCnt);\n\t\tBit#(16) data1 = zeroExtend(cmd.tag);\n\t\tBit#(16) data2 = zeroExtend(cmd.bus);\n\t\tBit#(16) data3 = zeroExtend(cmd.chip);\n\t\tBit#(16) data4 = zeroExtend(cmd.block);\n\t\tBit#(16) data5 = zeroExtend(cmd.page);\n\t\tBit#(128) rData = zeroExtend({data0, data1, data2, data3, data4, data5});\n\t\trdDataQ.enq(tuple2(rData, cmd.tag));\n\t\t$display(\"@%t: Flash Emu enqueued cnt=%d, tag=%x, data=%x\", $time, rdataCnt, cmd.tag, rData);\n\n\t\tif (rdataCnt == fromInteger(pageSizeUser/16)-1) begin\n\t\t\tstate <= FINISHED_CMD;\n\t\t\trdataCnt <= 0;\n\t\tend\n\t\telse begin\n\t\t\tstate <= WAIT;\n\t\t\trdataCnt <= rdataCnt + 1;\n\t\tend\n\n\tendrule\n\n\trule doWait if (state==WAIT);\n\t\tif (waitCnt == 0) begin\n\t\t\tstate <= SEND_DATA;\n\t\t\twaitCnt <= fromInteger(waitCycles);\n\t\tend\n\t\telse begin\n\t\t\twaitCnt <= waitCnt - 1;\n\t\tend\n\tendrule\n\n\n\trule doFinish if (state==FINISHED_CMD);\n\t\tflashCmdQ.deq;\n\t\tlet cmd = flashCmdQ.first;\n\t\tstate <= SEND_DATA;\n\t\t$display(\"@%t: Flash Emu: finished command tag=%x, bus=%x, chip=%x, block=%x, page=%x\", $time,\n\t\t\tcmd.tag, cmd.bus, cmd.chip, cmd.block, cmd.page);\t\n\tendrule\n\t*/\n"
  },
  {
    "path": "tests/algo1_flashmodel/FlashTop.bsv",
    "content": "// Copyright (c) 2013 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n`include \"ConnectalProjectConfig.bsv\"\nimport FIFOF::*;\nimport FIFO::*;\nimport FIFOLevel::*;\nimport BRAMFIFO::*;\nimport BRAM::*;\nimport GetPut::*;\nimport ClientServer::*;\nimport Vector::*;\nimport BuildVector::*;\nimport List::*;\nimport ConnectalMemory::*;\nimport ConnectalMemTypes::*;\nimport MemReadEngine::*;\nimport MemWriteEngine::*;\nimport Pipe::*;\nimport Clocks :: *;\nimport Xilinx       :: *;\n`ifndef SIMULATION\nimport XilinxCells ::*;\n`endif\nimport AuroraImportFmc1::*;\nimport AuroraCommon::*;\nimport ControllerTypes::*;\nimport ControllerTypes::*;\nimport FlashCtrlModel::*;\nimport PageBuffers::*;\n\ninterface FlashRequest;\n\tmethod Action readPage(Bit#(32) bus, Bit#(32) chip, Bit#(32) block, Bit#(32) page, Bit#(32) tag);\n\tmethod Action writePage(Bit#(32) bus, Bit#(32) chip, Bit#(32) block, Bit#(32) page, Bit#(32) tag);\n\tmethod Action eraseBlock(Bit#(32) bus, Bit#(32) chip, Bit#(32) block, Bit#(32) tag);\n\tmethod Action addDmaReadRefs(Bit#(32) sglId, Bit#(32) offset, Bit#(32) tag);\n\tmethod Action addDmaWriteRefs(Bit#(32) sglId, Bit#(32) offset, Bit#(32) tag);\n\tmethod Action start(Bit#(32) dummy);\n\tmethod Action debugDumpReq(Bit#(32) dummy);\n\tmethod Action setDebugVals (Bit#(32) flag, Bit#(32) debugDelay); \nendinterface\n\ninterface FlashIndication;\n\tmethod Action readDone(Bit#(32) tag);\n\tmethod Action writeDone(Bit#(32) tag);\n\tmethod Action eraseDone(Bit#(32) tag, Bit#(32) status);\n\tmethod Action debugDumpResp(Bit#(32) debug0, Bit#(32) debug1, Bit#(32) debug2, Bit#(32) debug3);\nendinterface\n\n// NumDmaChannels each for flash i/o and emualted i/o\n//typedef TAdd#(NumDmaChannels, NumDmaChannels) NumObjectClients;\n//typedef NumDmaChannels NumObjectClients;\ntypedef 128 DmaBurstBytes; \nInteger dmaBurstBytes = valueOf(DmaBurstBytes);\nInteger dmaBurstWords = dmaBurstBytes/wordBytes; //128/16 = 8\nInteger dmaBurstsPerPage = pageSizeUser/dmaBurstBytes;\n\ninterface FlashTop;\n\tinterface FlashRequest request;\n\tinterface Vector#(1, MemWriteClient#(WordSz)) hostMemWriteClient;\n\tinterface Vector#(1, MemReadClient#(WordSz)) hostMemReadClient;\n        interface PhysMemSlave#(FlashAddrWidth, 128) memSlave;    \n\tinterface Aurora_Pins#(4) aurora_fmc1;\n\tinterface Aurora_Clock_Pins aurora_clk_fmc1;\nendinterface\n\nmodule mkFlashTop#(FlashIndication indication, Clock clk250, Reset rst250)(FlashTop);\n\n\tClock curClk <- exposeCurrentClock;\n\tReset curRst <- exposeCurrentReset;\n\n\n\tReg#(Bool) started <- mkReg(False);\n\tReg#(Bit#(64)) cycleCnt <- mkReg(0);\n\n\tFIFO#(Tuple2#(FlashCmd, SourceT)) flashCmdQ <- mkSizedFIFO(valueOf(NumTags));\n\tVector#(NumTags, Reg#(Tuple2#(BusT, SourceT))) tag2busNsrcTable <- replicateM(mkRegU());\n\tVector#(NumTags, Reg#(Tuple2#(Bit#(32),Bit#(32)))) dmaWriteRefs <- replicateM(mkRegU());\n\tVector#(NumTags, Reg#(Tuple2#(Bit#(32),Bit#(32)))) dmaReadRefs <- replicateM(mkRegU());\n\tVector#(NUM_BUSES, FIFO#(Tuple2#(Bit#(WordSz), TagT))) dmaWriteBuf <- replicateM(mkSizedBRAMFIFO(dmaBurstWords*2));\n\t//FIFO#(Tuple3#(Bit#(WordSz), TagT, Bool)) memSlaveReadBuf <- mkSizedBRAMFIFO(128); //doesn't matter size?\n\tVector#(NUM_BUSES, FIFO#(Tuple2#(Bit#(WordSz), TagT))) dmaWriteBufOut <- replicateM(mkFIFO());\n\n\tGtxClockImportIfc gtx_clk_fmc1 <- mkGtxClockImport;\n\t`ifdef SIMULATION\n\t\tFlashCtrlVirtexIfc flashCtrl <- mkFlashCtrlModel(gtx_clk_fmc1.gtx_clk_p_ifc, gtx_clk_fmc1.gtx_clk_n_ifc, clk250);\n\t`else\n\t\tFlashCtrlVirtexIfc flashCtrl <- mkFlashCtrlVirtex(gtx_clk_fmc1.gtx_clk_p_ifc, gtx_clk_fmc1.gtx_clk_n_ifc, clk250);\n\t`endif\n\n\t//Page Buffers for MemSlave\n\tPageBuffers pageBufs <- mkPageBuffers();\n\n\n\t//Create read/write engines with NUM_BUSES memservers\n\tMemReadEngine#(WordSz,WordSz,1, NUM_BUSES) re <- mkMemReadEngine;\n\tMemWriteEngine#(WordSz,WordSz,1, NUM_BUSES) we <- mkMemWriteEngine;\n\n\tVector#(NUM_BUSES, Reg#(Bit#(16))) dmaWBurstCnts <- replicateM(mkReg(0));\n\tVector#(NUM_BUSES, Reg#(Bit#(16))) memSlaveCnts <- replicateM(mkReg(0));\n\tVector#(NUM_BUSES, FIFO#(TagT)) dmaReqQs <- replicateM(mkSizedFIFO(valueOf(NumTags)));//TODO make bigger?\n\tVector#(NUM_BUSES, FIFO#(Tuple2#(TagT, Bit#(32)))) dmaReq2RespQ <- replicateM(mkSizedFIFO(valueOf(NumTags))); //TODO make bigger?\n\tVector#(NUM_BUSES, Reg#(Bit#(32))) dmaWrReqCnts <- replicateM(mkReg(0));\n\tVector#(NUM_BUSES, Reg#(TagT)) currTags <- replicateM(mkReg(0));\n\tFIFO#(Tuple2#(Bit#(WordSz), TagT)) dataFlash2DmaQ <- mkFIFO();\n\n\trule incCycle;\n\t\tcycleCnt <= cycleCnt + 1;\n\tendrule\n\n\trule driveFlashCmd/* (started)*/;\n\t\tlet cmdNsrc = flashCmdQ.first;\n\t\tflashCmdQ.deq;\n\t\tlet cmd = tpl_1(cmdNsrc);\n\t\tlet src = tpl_2(cmdNsrc);\n\t\ttag2busNsrcTable[cmd.tag] <= tuple2(cmd.bus, src);\n\t\tflashCtrl.user.sendCmd(cmd); //forward cmd to flash ctrl FIXME DEBUG\n\t\t$display(\"@%d: Main.bsv: received cmd tag=%d @%x %x %x %x\", \n\t\t\t\t\t\tcycleCnt, cmd.tag, cmd.bus, cmd.chip, cmd.block, cmd.page);\n\tendrule\n\n\tReg#(Bit#(32)) delayRegSet <- mkReg(0);\n\tReg#(Bit#(32)) delayReg <- mkReg(0);\n\tReg#(Bit#(32)) debugFlag <- mkReg(0);\n\n\n\t//--------------------------------------------\n\t// Reads from Flash (DMA Write)\n\t//--------------------------------------------\n\n\trule doEnqReadFromFlash;\n\t\tif (delayReg==0) begin\n\t\t\tlet taggedRdata <- flashCtrl.user.readWord();\n\t\t\tif (debugFlag==0) begin\n\t\t\t\tdataFlash2DmaQ.enq(taggedRdata);\n\t\t\tend\n\t\t\tdelayReg <= delayRegSet;\n\t\tend\n\t\telse begin\n\t\t\tdelayReg <= delayReg - 1;\n\t\tend\n\tendrule\n\n\trule doDistributeReadFromFlash;\n\t\tlet taggedRdata = dataFlash2DmaQ.first;\n\t\tdataFlash2DmaQ.deq;\n\t\tlet tag = tpl_2(taggedRdata);\n\t\tlet data = tpl_1(taggedRdata);\n\t\tlet busNsrc = tag2busNsrcTable[tag];\n\t\tlet bus = tpl_1(busNsrc);\n\t\tlet src = tpl_2(busNsrc);\n\t\tif (src==SRC_HOST) begin\n\t\t\tdmaWriteBuf[bus].enq(taggedRdata);\n\t\tend\n\t\telse if (src==SRC_USER_HW) begin\n\t\t\tpageBufs.readResp.put(taggedRdata);\n\t\t\t/*\n\t\t\tBool last = False;\n\t\t\tif (memSlaveCnts[bus]==fromInteger(pageWords-1)) begin\n\t\t\t\tmemSlaveCnts[bus] <= 0;\n\t\t\t\tlast = True;\n\t\t\tend\n\t\t\telse begin\n\t\t\t\tmemSlaveCnts[bus] <= memSlaveCnts[bus] + 1;\n\t\t\tend\n\t\t\tmemSlaveReadBuf.enq(tuple3(data, tag, last));\n\t\t\t*/\n\t\tend\n\t\telse begin\n\t\t\t$display(\"ERROR: flashTop: incorrect source\");\n\t\tend\n\n\t\t$display(\"@%d Main.bsv: rdata tag=%d, bus=%d, data[%d]=%x\", cycleCnt, tag, bus, dmaWBurstCnts[bus], data);\n\tendrule\n\n\tfor (Integer b=0; b<valueOf(NUM_BUSES); b=b+1) begin\n\t\trule doReqDMAStart;\n\t\t\tdmaWriteBuf[b].deq;\n\t\t\tlet taggedRdata = dmaWriteBuf[b].first;\n\t\t\tdmaWriteBufOut[b].enq(taggedRdata);\n\t\t\tlet tag = tpl_2(taggedRdata);\n\t\t\t//for each bus, every dmaBurstWords bursts, request for init DMA\n\t\t\tif (dmaWBurstCnts[b]==0) begin\n\t\t\t\tdmaReqQs[b].enq(tag);\n\t\t\t\tcurrTags[b] <= tag;\n\t\t\t\tdmaWBurstCnts[b] <= dmaWBurstCnts[b] + 1;\n\t\t\tend\n\t\t\telse if (dmaWBurstCnts[b]==fromInteger(dmaBurstWords-1)) begin\n\t\t\t\tif (tag != currTags[b]) begin\n\t\t\t\t\t$display(\"main.bsv: **ERROR: tag bursts do not match!\");\n\t\t\t\tend\n\t\t\t\tdmaWBurstCnts[b] <= 0;\n\t\t\tend\n\t\t\telse begin\n\t\t\t\tif (tag != currTags[b]) begin\n\t\t\t\t\t$display(\"main.bsv: **ERROR: tag bursts do not match!\");\n\t\t\t\tend\n\t\t\t\tdmaWBurstCnts[b] <= dmaWBurstCnts[b] + 1;\n\t\t\tend\n\t\tendrule\n\n\n\t\t//initiate dma\n\t\trule initiateDmaWrite;\n\t\t\tdmaReqQs[b].deq;\n\t\t\tlet tag = dmaReqQs[b].first;\n\t\t\tlet sglId = tpl_1(dmaWriteRefs[tag]);\n\t\t\tlet offset = tpl_2(dmaWriteRefs[tag]);\n\t\t\tBit#(32) burstOffset = (dmaWrReqCnts[b]<<log2(dmaBurstBytes)) + offset;\n\t\t\tlet dmaCmd = MemengineCmd {\n\t\t\t\t\t\t\t\ttag: 0, //TODO: this was added in the new connectal\n\t\t\t\t\t\t\t\tsglId: sglId, \n\t\t\t\t\t\t\t\tbase: zeroExtend(burstOffset),\n\t\t\t\t\t\t\t\tlen:fromInteger(dmaBurstBytes), \n\t\t\t\t\t\t\t\tburstLen:fromInteger(dmaBurstBytes)\n\t\t\t\t\t\t\t};\n\t\t\twe.writeServers[b].request.put(dmaCmd);\n\t\t\tdmaReq2RespQ[b].enq(tuple2(tag, dmaWrReqCnts[b]));\n\t\t\t\n\t\t\t$display(\"@%d Main.bsv: init dma write tag=%d, bus=%d, addr=0x%x 0x%x\", \n\t\t\t\t\t\t\tcycleCnt, tag, b, sglId, burstOffset);\n\t\t\tif (dmaWrReqCnts[b] == fromInteger(dmaBurstsPerPage-1)) begin\n\t\t\t\tdmaWrReqCnts[b] <= 0;\n\t\t\tend\n\t\t\telse begin\n\t\t\t\tdmaWrReqCnts[b] <= dmaWrReqCnts[b] + 1;\n\t\t\tend\n\t\tendrule\n\n\t\t//send data\n\t\trule sendDmaWriteData;\n\t\t\t//TODO: is it safe to send this data right away, before the request\n\t\t\t//looks ok?\n\t\t\tlet taggedRdata = dmaWriteBufOut[b].first;\n\t\t\tlet data = tpl_1(taggedRdata);\n\t\t\tdmaWriteBufOut[b].deq;\n\t\t\twe.writeServers[b].data.enq(data);\n\t\tendrule\n\n\t\t//dma response.get done; when enough has accumulated, send ack to sw\n\t\trule dmaWriterGetResponse;\n\t\t\tlet dummy <- we.writeServers[b].done.get;\n\t\t\tlet tagCnt = dmaReq2RespQ[b].first;\n\t\t\tdmaReq2RespQ[b].deq;\n\t\t\t$display(\"@%d Main.bsv: dma resp [%d] tag=%d\", cycleCnt, tpl_2(tagCnt), tpl_1(tagCnt));\n\t\t\tif (tpl_2(tagCnt)==fromInteger(dmaBurstsPerPage-1)) begin\n\t\t\t\tindication.readDone(zeroExtend(tpl_1(tagCnt)));\n\t\t\tend\n\t\tendrule\n\tend //for each bus\n\n\n\n\t//--------------------------------------------\n\t// Writes to Flash (DMA Reads)\n\t//--------------------------------------------\n\n\tFIFO#(Tuple2#(TagT, BusT)) wrToDmaReqQ <- mkFIFO();\n\tVector#(NUM_BUSES, FIFO#(TagT)) dmaRdReq2RespQ <- replicateM(mkSizedFIFO(valueOf(NumTags))); //TODO sz\n\tVector#(NUM_BUSES, Reg#(Bit#(32))) dmaReadBurstCount <- replicateM(mkReg(0));\n\tVector#(NUM_BUSES, FIFO#(TagT)) dmaReadReqQ <- replicateM(mkSizedFIFO(valueOf(NumTags)));\n\tVector#(NUM_BUSES, Reg#(Bit#(32))) dmaRdReqCnts <- replicateM(mkReg(0));\n\n\t//Handle write data requests from controller\n\trule handleWriteDataRequestFromFlash;\n\t\tTagT tag <- flashCtrl.user.writeDataReq();\n\t\t//check which bus it's from\n\t\tlet bus = tpl_1(tag2busNsrcTable[tag]);\n\t\twrToDmaReqQ.enq(tuple2(tag, bus));\n\tendrule\n\n\trule distrDmaReadReq;\n\t\twrToDmaReqQ.deq;\n\t\tlet r = wrToDmaReqQ.first;\n\t\tlet tag = tpl_1(r);\n\t\tlet bus = tpl_2(r);\n\t\tdmaReadReqQ[bus].enq(tag);\n\t\tdmaRdReq2RespQ[bus].enq(tag);\n\tendrule\n\n\tfor (Integer b=0; b<valueOf(NUM_BUSES); b=b+1) begin\n\t\trule initDmaRead;\n\t\t\tlet tag = dmaReadReqQ[b].first;\n\t\t\tlet sglId = tpl_1(dmaReadRefs[tag]);\n\t\t\tlet offset = tpl_2(dmaReadRefs[tag]);\n\t\t\tBit#(32) burstOffset = (dmaRdReqCnts[b]<<log2(dmaBurstBytes)) + offset;\n\t\t\tlet dmaCmd = MemengineCmd {\n\t\t\t\t\t\t\t\ttag: 0, //TODO: this was added in the new connectal\n\t\t\t\t\t\t\t\tsglId: sglId, \n\t\t\t\t\t\t\t\tbase: zeroExtend(burstOffset),\n\t\t\t\t\t\t\t\tlen:fromInteger(dmaBurstBytes), \n\t\t\t\t\t\t\t\tburstLen:fromInteger(dmaBurstBytes)\n\t\t\t\t\t\t\t};\n\t\t\tre.readServers[b].request.put(dmaCmd);\n\t\t\t$display(\"Main.bsv: dma read cmd issued: sglId=%x, burstOffset=%d\", sglId, burstOffset);\n\n\t\t\tif (dmaRdReqCnts[b] == fromInteger(dmaBurstsPerPage-1)) begin\n\t\t\t\tdmaRdReqCnts[b] <= 0;\n\t\t\t\tdmaReadReqQ[b].deq; //done with this req\n\t\t\tend\n\t\t\telse begin\n\t\t\t\tdmaRdReqCnts[b] <= dmaRdReqCnts[b] + 1;\n\t\t\tend\n\t\tendrule\n\n\t\t//forward data\n\t\trule forwardDmaRdData;\n\t\t\tlet d <- toGet(re.readServers[b].data).get;\n\t\t\tlet tag = dmaRdReq2RespQ[b].first;\n\t\t\tflashCtrl.user.writeWord(tuple2(d.data, tag));\n\t\t\t$display(\"Main.bsv: forwarded dma read data [%d]: tag=%d, data=%x\", dmaReadBurstCount[b],\n\t\t\t\t\t\t\ttag, d.data);\n\n\t\t\tif (dmaReadBurstCount[b] == fromInteger(pageWords-1)) begin\n\t\t\t\tdmaRdReq2RespQ[b].deq;\n\t\t\t\tdmaReadBurstCount[b] <= 0;\n\t\t\tend\n\t\t\telse begin\n\t\t\t\tdmaReadBurstCount[b] <= dmaReadBurstCount[b] + 1;\n\t\t\tend\n\t\tendrule\n\tend //for each bus\n\n\t//--------------------------------------------\n\t// Writes/Erase Acks\n\t//--------------------------------------------\n\n\t//Handle acks from controller\n\tFIFO#(Tuple2#(TagT, StatusT)) ackQ <- mkFIFO;\n\trule handleControllerAck;\n\t\tlet ackStatus <- flashCtrl.user.ackStatus();\n\t\tackQ.enq(ackStatus);\n\tendrule\n\n\trule indicateControllerAck;\n\t\tackQ.deq;\n\t\tTagT tag = tpl_1(ackQ.first);\n\t\tStatusT st = tpl_2(ackQ.first);\n\t\tcase (st)\n\t\t\tWRITE_DONE: indication.writeDone(zeroExtend(tag));\n\t\t\tERASE_DONE: indication.eraseDone(zeroExtend(tag), 0);\n\t\t\tERASE_ERROR: indication.eraseDone(zeroExtend(tag), 1);\n\t\tendcase\n\tendrule\n\n\t//--------------------------------------------\n\t// PageBuffer flash cmd requests\n\t//--------------------------------------------\n\trule pageBufFlashReq; \n\t\tlet cmd <- pageBufs.flashReq.get;\n\t\t$display(\"FlashTop: page buf cmd received\");\n\t\tflashCmdQ.enq(tuple2(cmd, SRC_USER_HW));\n\tendrule\n\n\n\n\t//--------------------------------------------\n\t// Debug\n\t//--------------------------------------------\n\n\tFIFO#(Bit#(1)) debugReqQ <- mkFIFO();\n\trule doDebugDump;\n\t\t$display(\"Main.bsv: debug dump request received\");\n\t\tdebugReqQ.deq;\n\t\tlet debugCnts = flashCtrl.debug.getDebugCnts(); \n\t\tlet gearboxSendCnt = tpl_1(debugCnts);         \n\t\tlet gearboxRecCnt = tpl_2(debugCnts);   \n\t\tlet auroraSendCntCC = tpl_3(debugCnts);     \n\t\tlet auroraRecCntCC = tpl_4(debugCnts);  \n\t\tindication.debugDumpResp(gearboxSendCnt, gearboxRecCnt, auroraSendCntCC, auroraRecCntCC);\n\tendrule\n\n\n\n\t//--------------------------------------------\n\t// Interfaces\n\t//--------------------------------------------\n\t//Vector#(1, MemWriteClient#(WordSz)) dmaWriteClientVec;\n\t//Vector#(1, MemReadClient#(WordSz)) dmaReadClientVec;\n\t//dmaWriteClientVec[0] = we.dmaClient;\n\t//dmaReadClientVec[0] = re.dmaClient;\n\t\n\t/*\n\tReg#(Bit#(1)) getPhase <- mkReg(0);\n\n   interface PhysMemSlave memSlave;\n\t\tinterface PhysMemReadServer read_server;\n\t\t\tinterface Put readReq;\n\t\t\t\tmethod Action put(PhysMemRequest#(FlashAddrWidth) req);\n\t\t\t\t\t//req.addr; //bus, chip, blk, page\n\t\t\t\t\t//req.burstLen; //should always be 8k\n\t\t\t\t\t//req.tag; //6 bit (64 tags)\n\t\t\t\t\tBit#(8) page = req.addr[7:0];\n\t\t\t\t\tBit#(16) block = req.addr[23:8];\n\t\t\t\t\tChipT chip = truncate(req.addr>>(16+8));\n\t\t\t\t\tBusT bus = truncate(req.addr>>(16+8+valueOf(TLog#(ChipsPerBus))));\n\t\t\t\t\tTagT tag = zeroExtend(req.tag);\n\n\t\t\t\t\tFlashCmd fcmd = FlashCmd{\n\t\t\t\t\t\ttag: tag,\n\t\t\t\t\t\top: READ_PAGE,\n\t\t\t\t\t\tbus: bus,\n\t\t\t\t\t\tchip: chip,\n\t\t\t\t\t\tblock: block,\n\t\t\t\t\t\tpage: page\n\t\t\t\t\t\t};\n\t\t\t\t\tflashCmdQ.enq(tuple2(fcmd, SRC_USER_HW));\n\t\t\t\tendmethod\n\t\t\tendinterface\n\t\t\tinterface Get readData;\n\t\t\t\tmethod ActionValue#(MemData#(128)) get();\n\t\t\t\t\tlet taggedRdataLast = memSlaveReadBuf.first;\n\t\t\t\t\tBit#(WordSz) data = tpl_1(taggedRdataLast);\n\t\t\t\t\tTagT tag = tpl_2(taggedRdataLast);\n\t\t\t\t\tBool last = tpl_3(taggedRdataLast);\n\n\t\t\t\t\tmemSlaveReadBuf.deq;\n\t\t\t\t\tMemData#(128) memData = MemData { \n\t\t\t\t\t\t\tdata: data, \n\t\t\t\t\t\t\ttag: truncate(tag), \t//FIXME DANGEROUS\n\t\t\t\t\t\t\tlast: last\t\t\t\t\n\t\t\t\t\t\t};\n\t\t\t\t\treturn memData;\n\t\t\t\tendmethod\n\t\t\tendinterface\n\t\tendinterface\n\t\tinterface PhysMemWriteServer write_server = ?;\n\tendinterface\n\t*/\n\n\tinterface PhysMemSlave memSlave = pageBufs.memSlave;\n\n   interface FlashRequest request;\n\t\tmethod Action readPage(Bit#(32) bus, Bit#(32) chip, Bit#(32) block, Bit#(32) page, Bit#(32) tag);\n\t\t\tFlashCmd fcmd = FlashCmd{\n\t\t\t\ttag: truncate(tag),\n\t\t\t\top: READ_PAGE,\n\t\t\t\tbus: truncate(bus),\n\t\t\t\tchip: truncate(chip),\n\t\t\t\tblock: truncate(block),\n\t\t\t\tpage: truncate(page)\n\t\t\t\t};\n\n\t\t\tflashCmdQ.enq(tuple2(fcmd, SRC_HOST));\n\t\tendmethod\n\t\t\n\t\tmethod Action writePage(Bit#(32) bus, Bit#(32) chip, Bit#(32) block, Bit#(32) page, Bit#(32) tag);\n\t\t\tFlashCmd fcmd = FlashCmd{\n\t\t\t\ttag: truncate(tag),\n\t\t\t\top: WRITE_PAGE,\n\t\t\t\tbus: truncate(bus),\n\t\t\t\tchip: truncate(chip),\n\t\t\t\tblock: truncate(block),\n\t\t\t\tpage: truncate(page)\n\t\t\t\t};\n\n\t\t\tflashCmdQ.enq(tuple2(fcmd, SRC_HOST));\n\t\tendmethod\n\n\t\tmethod Action eraseBlock(Bit#(32) bus, Bit#(32) chip, Bit#(32) block, Bit#(32) tag);\n\t\t\tFlashCmd fcmd = FlashCmd{\n\t\t\t\ttag: truncate(tag),\n\t\t\t\top: ERASE_BLOCK,\n\t\t\t\tbus: truncate(bus),\n\t\t\t\tchip: truncate(chip),\n\t\t\t\tblock: truncate(block),\n\t\t\t\tpage: 0\n\t\t\t\t};\n\t\t\tflashCmdQ.enq(tuple2(fcmd, SRC_HOST));\n\t\tendmethod\n\n\t\tmethod Action addDmaReadRefs(Bit#(32) sglId, Bit#(32) offset, Bit#(32) tag);\n\t\t\tdmaReadRefs[tag] <= tuple2(sglId, offset);\n\t\tendmethod\n\n\t\tmethod Action addDmaWriteRefs(Bit#(32) sglId, Bit#(32) offset, Bit#(32) tag);\n\t\t\tdmaWriteRefs[tag] <= tuple2(sglId, offset);\n\t\tendmethod\n\n\t\tmethod Action start(Bit#(32) dummy);\n\t\t\tstarted <= True;\n\t\tendmethod\n\n\t\tmethod Action debugDumpReq(Bit#(32) dummy);\n\t\t\tdebugReqQ.enq(1);\n\t\tendmethod\n\n\t\tmethod Action setDebugVals (Bit#(32) flag, Bit#(32) debugDelay); \n\t\t\tdelayRegSet <= debugDelay;\n\t\t\tdebugFlag <= flag;\n\t\tendmethod\n\n\tendinterface //FlashRequest\n\n   interface MemWriteClient hostMemWriteClient = vec(we.dmaClient);\n   interface MemReadClient hostMemReadClient = vec(re.dmaClient);\n   interface Aurora_Pins aurora_fmc1 = flashCtrl.aurora;\n   interface Aurora_Clock_Pins aurora_clk_fmc1 = gtx_clk_fmc1.aurora_clk;\nendmodule\n"
  },
  {
    "path": "tests/algo1_flashmodel/Makefile",
    "content": "\nCONNECTALDIR?=../..\nINTERFACES = StrstrRequest StrstrIndication FlashRequest FlashIndication\nBSVFILES = $(CONNECTALDIR)/lib/strstr/bsv/Strstr.bsv $(CONNECTALDIR)/lib/nandsim/bsv/NandSimNames.bsv Top.bsv FlashTop.bsv\n#CPPFILES2=$(CONNECTALDIR)/examples/algo1_nandsim/test.cpp\nCPPFILES=test.cpp\nCONNECTALFLAGS += -D DEGPAR=2\nCONNECTALFLAGS += -I$(CONNECTALDIR)/lib/strstr/cpp\nCONNECTALFLAGS += -I$(CONNECTALDIR)/lib/nandsim/cpp\nPIN_TYPE = Top_Pins\nPIN_TYPE_INCLUDE = TopPins\nCONNECTALFLAGS += -D IMPORT_HOSTIF --bscflags \" -D DataBusWidth=128 \" --clib rt\ninclude $(CONNECTALDIR)/Makefile.connectal\n\n# #Note: for some reason, xbsv can't parase ControllerTypes.bsv properly. So a soft link in current directory is created\n# BSVFILES = Main.bsv Top.bsv \\\n# \t../../xilinx/aurora_8b10b_fmc1/AuroraImportFmc1.bsv \\\n# \t../../src/lib/AuroraCommon.bsv \\\n# \t../../controller/src/common/FlashBusModel.bsv \\\n# \t../../controller/src/model_virtex/FlashCtrlModel.bsv \\\n# \t../../controller/src/hw_virtex/FlashCtrlVirtex.bsv\n\n# CPPFILES=main.cpp\n# #CONNECTALFLAGS=--bscflags \" -D TRACE_AXI\"\n\n\n\n\n# ifeq ($(BOARD), vc707)\n# CONNECTALFLAGS += \\\n# \t--verilog ../../xilinx/aurora_8b10b_fmc1/ \\\n# \t--xci $(CONNECTALDIR)/out/$(BOARD)/aurora_8b10b_fmc1/aurora_8b10b_fmc1.xci \\\n# \t--constraint ../../xilinx/aurora_8b10b_fmc1/aurora_8b10b_fmc1_exdes.xdc \n\n# \t#--verilog ../../../xbsv/xilinx/ddr3_v1_7/ \\\n# \t--constraint ../../xilinx/ddr3_v2_0/vc707_ddr3_sx.xdc \\\n# \t--constraint $(CONNECTALDIR)/xilinx/constraints/vc707_ddr3.xdc \\\n# \t--verilog $(BLUESPECDIR)/board_support/bluenoc/xilinx/VC707/verilog/ddr3_v2_0/ddr3_v2_0/user_design/rtl/ \\\n# \t--verilog $(BLUESPECDIR)/board_support/bluenoc/xilinx/VC707/verilog/ddr3_v2_0/ddr3_v2_0/user_design/rtl/clocking \\\n# \t--verilog $(BLUESPECDIR)/board_support/bluenoc/xilinx/VC707/verilog/ddr3_v2_0/ddr3_v2_0/user_design/rtl/controller \\\n# \t--verilog $(BLUESPECDIR)/board_support/bluenoc/xilinx/VC707/verilog/ddr3_v2_0/ddr3_v2_0/user_design/rtl/ecc \\\n# \t--verilog $(BLUESPECDIR)/board_support/bluenoc/xilinx/VC707/verilog/ddr3_v2_0/ddr3_v2_0/user_design/rtl/ip_top \\\n# \t--verilog $(BLUESPECDIR)/board_support/bluenoc/xilinx/VC707/verilog/ddr3_v2_0/ddr3_v2_0/user_design/rtl/phy \\\n# \t--verilog $(BLUESPECDIR)/board_support/bluenoc/xilinx/VC707/verilog/ddr3_v2_0/ddr3_v2_0/user_design/rtl/ui \\\n# AURORA_INTRA = $(CONNECTALDIR)/out/$(BOARD)/aurora_8b10b_fmc1/aurora_8b10b_fmc1_stub.v\n# prebuild:: $(AURORA_INTRA)\n\n# $(AURORA_INTRA): core-scripts/synth-aurora-intra.tcl\n# \t(cd $(BOARD); vivado -mode batch -source ../core-scripts/synth-aurora-intra.tcl)\n# endif\n\n# include $(CONNECTALDIR)/Makefile.connectal\n"
  },
  {
    "path": "tests/algo1_flashmodel/NandSimMod.bsv",
    "content": "// Copyright (c) 2014 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\nimport BRAMFIFO::*;\nimport FIFO::*;\nimport FIFOF::*;\nimport GetPut::*;\nimport Vector::*;\nimport BRAM::*;\nimport GetPut::*;\nimport Connectable::*;\nimport Pipe::*;\nimport ConnectalMemTypes::*;\nimport MemReadEngine::*;\nimport MemWriteEngine::*;\nimport FlashCtrlModel::*;\n\ninterface NandCfgRequest;\n   method Action startRead(Bit#(32) drampointer, Bit#(32) dramOffset, Bit#(32) nandAddr, Bit#(32) numBytes, Bit#(32) burstLen);\n   method Action startWrite(Bit#(32) drampointer, Bit#(32) dramOffset, Bit#(32) nandAddr, Bit#(32) numBytes, Bit#(32) burstLen);\n   method Action startErase(Bit#(32) nandAddr, Bit#(32) numBytes);\nendinterface\n\ninterface NandCfgIndication;\n   method Action readDone(Bit#(32) tag);\n   method Action writeDone(Bit#(32) tag);\n   method Action eraseDone(Bit#(32) tag);\nendinterface\n\ninterface NandSimMod#(numeric type numSlaves, numeric type memengineOuts);\n   interface NandCfgRequest request;\n   interface Vector#(numSlaves,PhysMemSlave#(PhysAddrWidth,64)) memSlaves;\nendinterface\n\ninterface NandSimControl;\n   interface NandCfgRequest request;   \nendinterface\n\n\nmodule mkNandSimMod#(NandCfgIndication indication,\n\t\t     MemReadServer#(64) nand_ctrl_host_rs,\n\t\t     MemWriteServer#(64) nand_ctrl_host_ws) (NandSimMod#(numSlaves,memengineOuts))\n   provisos(\n\n    Add#(a__, TLog#(TAdd#(numSlaves, 1)), 6)\n,    Add#(b__, TLog#(TAdd#(numSlaves, 1)), TLog#(TMul#(4, TAdd#(numSlaves,\n    1))))\n,    Pipe::FunnelPipesPipelined#(1, TAdd#(numSlaves, 1), Tuple2#(Bit#(64),\n    Bool), TMin#(2, TLog#(TAdd#(numSlaves, 1))))\n,    Pipe::FunnelPipesPipelined#(1, TAdd#(numSlaves, 1),\n    Tuple2#(Bit#(TLog#(TAdd#(numSlaves, 1))), MemTypes::MemengineCmd),\n    TMin#(2, TLog#(TAdd#(numSlaves, 1))))\n,    Add#(c__, TLog#(TAdd#(numSlaves, 1)), TAdd#(1, TLog#(TMul#(4,\n    TAdd#(numSlaves, 1)))))\n,    Add#(d__, TLog#(TAdd#(numSlaves, 2)), 6)\n,    Pipe::FunnelPipesPipelined#(1, TAdd#(numSlaves, 2),\n    Tuple3#(Bit#(TLog#(TAdd#(numSlaves, 2))), Bit#(64), Bool), TMin#(2,\n    TLog#(TAdd#(numSlaves, 2))))\n,    Pipe::FunnelPipesPipelined#(1, TAdd#(numSlaves, 2), Tuple3#(Bit#(2),\n    Bit#(64), Bool), TMin#(2, TLog#(TAdd#(numSlaves, 2))))\n,    Add#(e__, TLog#(TAdd#(numSlaves, 2)), TLog#(TMul#(4, TAdd#(numSlaves,\n    2))))\n,    Pipe::FunnelPipesPipelined#(1, TAdd#(numSlaves, 2), Tuple2#(Bit#(64),\n    Bool), TMin#(2, TLog#(TAdd#(numSlaves, 2))))\n,    Pipe::FunnelPipesPipelined#(1, TAdd#(numSlaves, 2),\n    Tuple2#(Bit#(TLog#(TAdd#(numSlaves, 2))), MemTypes::MemengineCmd),\n    TMin#(2, TLog#(TAdd#(numSlaves, 2))))\n,    Add#(f__, TLog#(TAdd#(numSlaves, 2)), TAdd#(1, TLog#(TMul#(4,\n    TAdd#(numSlaves, 2)))))\n,   Add#(g__, TLog#(TAdd#(numSlaves, 1)), TLog#(TMul#(memengineOuts,\n\t\t\t\t\t\t  TAdd#(numSlaves, 1))))\n,   Add#(h__, TLog#(TAdd#(numSlaves, 1)), TAdd#(1, TLog#(TMul#(memengineOuts,\n\t\t\t\t\t\t\t   TAdd#(numSlaves, 1)))))\n,   Add#(i__, TLog#(TAdd#(numSlaves, 2)), TLog#(TMul#(memengineOuts,\n\t\t\t\t\t\t  TAdd#(numSlaves, 2))))\n,   Add#(j__, TLog#(TAdd#(numSlaves, 2)), TAdd#(1, TLog#(TMul#(memengineOuts,\n\t\t\t\t\t\t\t   TAdd#(numSlaves, 2)))))\n      );\n   \n   let verbose = False;\n   \n   MemReadEngine#(64,64,memengineOuts,  TAdd#(numSlaves,1))  re <- mkMemReadEngine();\n   MemWriteEngine#(64,64,memengineOuts, TAdd#(numSlaves,2))  we <- mkMemWriteEngine();\n   NandSimControl ns <- mkNandSimControl(nand_ctrl_host_rs, re.readServers[0],\n\t nand_ctrl_host_ws, we.writeServers[0], we.writeServers[1], indication);\n   \n   Vector#(numSlaves,MemReadServer#(64)) slave_read_servers  = takeTail(re.readServers);\n   Vector#(numSlaves,MemWriteServer#(MemengineCmd,Bool)) slave_write_servers = takeTail(we.writeServers);\n   Vector#(numSlaves,FIFO#(Bit#(MemTagSize)))    slaveWriteTags <- replicateM(mkSizedBRAMFIFO(valueOf(memengineOuts)));\n   Vector#(numSlaves,FIFO#(Bit#(MemTagSize)))    slaveReadTags <- replicateM(mkSizedBRAMFIFO(valueOf(memengineOuts)));\n   Vector#(numSlaves,Reg#(Bit#(BurstLenSize)))   slaveReadCnts <- replicateM(mkReg(0));\n\n   connectToFlashModel(re.dmaClient,we.dmaClient);\n   \n   function PhysMemSlave#(PhysAddrWidth,64) mms(Integer i);\n      return (\n   interface PhysMemSlave;\n      interface PhysMemWriteServer write_server; \n\t interface Put writeReq;\n\t    method Action put(PhysMemRequest#(PhysAddrWidth) req);\n\t       slave_write_servers[i].request.put(MemengineCmd{sglId:0, base:extend(req.addr), burstLen:req.burstLen, len:extend(req.burstLen), tag:req.tag});\n\t       slaveWriteTags[i].enq(req.tag);\n            endmethod\n\t endinterface\n\t interface Put writeData;\n\t    method Action put(MemData#(64) wdata);\n\t       slave_write_servers[i].data.enq(wdata.data);\n            endmethod\n\t endinterface\n\t interface Get writeDone;\n\t    method ActionValue#(Bit#(MemTagSize)) get();\n\t       let rv <- slave_write_servers[i].done.get;\n\t       slaveWriteTags[i].deq;\n\t       return slaveWriteTags[i].first;\n            endmethod\n\t endinterface\n      endinterface\n      interface PhysMemReadServer read_server;\n\t interface Put readReq;\n\t    method Action put(PhysMemRequest#(PhysAddrWidth) req);\n\t       if (verbose) $display(\"mkNandSim.memSlave::readReq %d %d %d (%d)\", req.addr, req.burstLen, req.tag, i);\n\t       slave_read_servers[i].request.put(MemengineCmd{sglId:0, base:extend(req.addr), burstLen:req.burstLen, len:extend(req.burstLen), tag:req.tag});\n\t       slaveReadTags[i].enq(req.tag);\n\t       slaveReadCnts[i] <= req.burstLen;\n\t    endmethod\n\t endinterface\n\t interface Get  readData;\n\t    method ActionValue#(MemData#(64)) get();\n\t       let rv <- toGet(slave_read_servers[i].data).get;\n\t       let new_slaveReadCnt = slaveReadCnts[i]-8;\n\t       let last = new_slaveReadCnt==0;\n\t       slaveReadCnts[i] <= new_slaveReadCnt;\n\t       if (verbose) $display(\"mkNandSim.memSlave::readData %d %d %d %d (%d)\", slaveReadTags[i].first, last, rv.data, slaveReadCnts[i], i);\n               if (rv.last)\n\t          slaveReadTags[i].deq;\n\t       return MemData{data:rv.data, tag:slaveReadTags[i].first,last:last};\n            endmethod\n\t endinterface\n      endinterface\n   endinterface\n\t      );\n   endfunction\n   interface memSlaves = map(mms,genVector);\n   interface request = ns.request;\nendmodule\n\nmodule mkNandSimControl#(MemReadServer#(64) dram_read_server, MemReadServer#(64) nand_read_server,\n    MemWriteServer#(64) dram_write_server, MemWriteServer#(64) nand_write_server,\n    MemWriteServer#(64) nand_erase_server, NandCfgIndication indication) (NandSimControl);\n   FIFOF#(Bit#(32))  readReqFifo <- mkFIFOF();\n   FIFOF#(Bit#(32)) writeReqFifo <- mkFIFOF();\n   Reg#(Bit#(32))   readCountReg <- mkReg(0);\n   Reg#(Bit#(32))  writeCountReg <- mkReg(0);\n   FIFOF#(Bool)     readDoneFifo <- mkFIFOF();\n   FIFOF#(Bool)    writeDoneFifo <- mkFIFOF();\n   FIFO#(void)     dram_read_done <- mkFIFO;\n   FIFO#(void)     nand_read_done <- mkFIFO;\n\n   rule countNandWrite;\n      let v <- toGet(dram_read_server.data).get();\n      let count = writeCountReg;\n      if (count == 0)\n\t count = writeReqFifo.first();\n      //$display(\"write v=%h count=%d\", v.data, count);\n      nand_write_server.data.enq(v.data);\n      if (count == 8) begin\n\t writeReqFifo.deq();\n\t writeDoneFifo.enq(True);\n      end\n      writeCountReg <= count-8;\n      if (v.last)\n         dram_read_done.enq(?);\n   endrule\n\n   rule countNandRead;\n      let v <- toGet(nand_read_server.data).get();\n      let count = readCountReg;\n      if (count == 0)\n\t count = readReqFifo.first();\n      //$display(\"read v=%h count=%d\", v.data, count);\n      dram_write_server.data.enq(v.data);\n      if (count == 8) begin\n\t readReqFifo.deq();\n\t readDoneFifo.enq(True);\n      end\n      readCountReg <= count-8;\n      if (v.last)\n         nand_read_done.enq(?);\n   endrule\n\n   PipeOut#(Bit#(64)) erasePipe = (interface PipeOut#(Bit#(64));\n\t\t\t\t       method Bit#(64) first(); return fromInteger(-1); endmethod\n\t\t\t\t       method Action deq(); endmethod\n\t\t\t\t       method Bool notEmpty(); return True; endmethod\n\t\t\t\t   endinterface);\n   rule eraseRule;\n      let v <- toGet(nand_erase_server.data).get;\n      toPut(erasePipe).put(v.data);\n   endrule\n\n   rule eraseDone;\n      let done <- nand_erase_server.done.get();\n      $display(\"eraseDone\");\n      indication.eraseDone(0);\n   endrule\n   \n   rule writeDone;\n      let nandWriteDone <-  nand_write_server.done.get();\n      dram_read_done.deq;\n      let v <- toGet(writeDoneFifo).get();\n      $display(\"writeDone\");\n      indication.writeDone(0);\n   endrule\n\n   rule readDone;\n      nand_read_done.deq;\n      let dramWriteDone <- dram_write_server.done.get();\n      let v <- toGet(readDoneFifo).get();\n      $display(\"readDone\");\n      indication.readDone(0);\n   endrule\n   \n   interface NandCfgRequest request;\n      /*!\n      * Reads from NAND and writes to DRAM\n      */\n      method Action startRead(Bit#(32) pointer, Bit#(32) dramOffset, Bit#(32) nandAddr,Bit#(32) numBytes, Bit#(32) burstLen);\n\t $display(\"startRead numBytes=%d burstLen=%d\", numBytes, burstLen);\n\t readReqFifo.enq(numBytes);\n\t  nand_read_server.request.put(MemengineCmd {sglId: 0, base: extend(nandAddr), burstLen: truncate(burstLen), len: extend(numBytes), tag:0});\n\t dram_write_server.request.put(MemengineCmd {sglId: pointer, base: extend(dramOffset), burstLen: truncate(burstLen), len: extend(numBytes), tag:0});\n      endmethod\n\n      /*!\n      * Reads from DRAM and writes to NAND\n      */\n      method Action startWrite(Bit#(32) pointer, Bit#(32) dramOffset, Bit#(32) nandAddr,Bit#(32) numBytes, Bit#(32) burstLen);\n\t $display(\"startWrite numBytes=%d burstLen=%d\", numBytes, burstLen);\n\t writeReqFifo.enq(numBytes);\n\t  nand_write_server.request.put(MemengineCmd {sglId: 0, base: extend(nandAddr), burstLen: truncate(burstLen), len: extend(numBytes), tag:0});\n\t  dram_read_server.request.put(MemengineCmd {sglId: pointer, base: extend(dramOffset), burstLen: truncate(burstLen), len: extend(numBytes), tag:0});\n      endmethod\n\n      method Action startErase(Bit#(32) nandAddr, Bit#(32) numBytes);\n\t $display(\"startErase numBytes=%d burstLen=%d\", numBytes, 16);\n\t nand_erase_server.request.put(MemengineCmd {sglId: 0, base: extend(nandAddr), burstLen: 16, len: extend(numBytes), tag:0});\n      endmethod\n   endinterface\nendmodule\n"
  },
  {
    "path": "tests/algo1_flashmodel/NullResetN.bsv",
    "content": "package NullResetN;\n\ninterface NullResetNIfc;\n\tinterface Reset rst_n;\nendinterface\n\nimport \"BVI\" null_reset_n =\nmodule mkNullResetN (NullResetNIfc);\n\tdefault_clock no_clock;\n\tdefault_reset no_reset;\n\n\toutput_reset rst_n(RESET_N);\nendmodule\n\nendpackage: NullResetN\n"
  },
  {
    "path": "tests/algo1_flashmodel/PageBuffers.bsv",
    "content": "import FIFOF::*;\nimport FIFO::*;\nimport FIFOLevel::*;\nimport BRAMFIFO::*;\nimport BRAM::*;\nimport GetPut::*;\nimport ClientServer::*;\nimport Arbiter::*;\nimport Vector::*;\nimport List::*;\n\nimport ConnectalMemTypes::*;\nimport ControllerTypes::*;\n\n\ninterface PageBuffers;\n\tinterface PhysMemSlave#(FlashAddrWidth, 128) memSlave; //to user hw\n\tinterface Get#(FlashCmd) flashReq;\n\tinterface Put#(Tuple2#(Bit#(WordSz), TagT)) readResp;\nendinterface\n\ntypedef TLog#(PageWords) PageOffsetSz;\n\ntypedef enum {\n\tST_INIT,\n\tST_CMD,\n\tST_HIT,\n\tST_MISS,\n\tST_MISS_READDATA\n} BufOpState deriving (Bits, Eq);\n\ntypedef struct {\n\tBool valid;\n\tFlashAddr faddr;\n} PageBufferEntry deriving (Bits, Eq);\n\ntypedef struct {\n\tFlashAddr faddr;\n\tBit#(PageOffsetSz) offset;\n} PageAddrOff deriving (Bits, Eq);\n\nfunction PageAddrOff decodePhysMemAddr(Bit#(FlashAddrWidth) addr);\n\t//byte addressible\n\tTuple2#(PageAddrOff, Bit#(TLog#(WordBytes))) decodedAddr = unpack(truncate(addr));\n\treturn tpl_1(decodedAddr);\n\t//PageAddrOff decodedAddr = unpack(truncate(addr)); //FIXME FIXME FIXME\n\t//return decodedAddr;\nendfunction\n\n\nfunction TagT splitTagsByBus(Integer id, Bit#(32) cnt);\n\tBit#(32) group = fromInteger(id * (valueOf(NumTags)/valueOf(NUM_BUSES)));\n\treturn truncate(group + cnt);\nendfunction\n\nfunction BusT tag2bus(TagT tag);\n\treturn truncate( tag>>(log2(num_tags/num_buses)) );\nendfunction\n\n//TODO: for now assumes that the request does not cross page boundaries\n(* synthesize *)\nmodule mkPageBuffers(PageBuffers);\n\n\t//Page Buffers\n\tVector#(NUM_BUSES, PageBuffers) pageBuffers = newVector();\n\tfor (Integer bus=0; bus<valueOf(NUM_BUSES); bus=bus+1) begin\n\t\tpageBuffers[bus] <- mkSinglePageBuffer(bus);\n\tend\n\n\t//Arbiter\n\tArbiter_IFC#(NUM_BUSES) arb <- mkStickyArbiter();\n\n\tFIFO#(Tuple2#(Bit#(WordSz), TagT)) flashReadAggrQ <- mkFIFO();\n\tFIFO#(FlashCmd) flashCmdAggrQ <- mkFIFO();\n\tFIFO#(MemData#(128)) slaveRespAggrQ <- mkFIFO;\n\t\n\n\trule distrFlashRead;\n\t\tflashReadAggrQ.deq;\n\t\tlet tdata = flashReadAggrQ.first;\n\t\tlet tag = tpl_2(tdata);\n\t\tlet bus = tag2bus(tag);\n\t\tpageBuffers[bus].readResp.put(tdata);\n\tendrule\n\n\n\t//Handle flash cmd and data\n\tfor (Integer bus=0; bus<valueOf(NUM_BUSES); bus=bus+1) begin\n\t\trule funnelFlashCmd;\n\t\t\tlet cmd <- pageBuffers[bus].flashReq.get();\n\t\t\tflashCmdAggrQ.enq(cmd);\n\t\t\t$display(\"PageBufferTop: flashCmdAggrQ enq\");\n\t\tendrule\n\n\t\t//Handle mem slave read data arbitration\n\t\tFIFOF#(MemData#(128)) slaveRespBufs <- mkFIFOF;\n\t\trule getBuffSlaveData;\n\t\t\tlet rd <- pageBuffers[bus].memSlave.read_server.readData.get();\n\t\t\tslaveRespBufs.enq(rd);\n\t\tendrule\n\n\t\tReg#(Bool) granted <- mkReg(False);\n\t\trule arbReq if (slaveRespBufs.notEmpty && !granted);\n\t\t\tarb.clients[bus].request();\n\t\t\tif (arb.clients[bus].grant) begin\n\t\t\t\tgranted <= True;\n\t\t\tend\n\t\tendrule\n\n\t\trule holdGrant if (granted);\n\t\t\tarb.clients[bus].request();\n\t\tendrule\n\n\t\trule send if (granted);\n\t\t\tslaveRespBufs.deq;\n\t\t\tslaveRespAggrQ.enq(slaveRespBufs.first);\n\t\t\tif (slaveRespBufs.first.last) begin\n\t\t\t\tgranted <= False;\n\t\t\tend\n\t\tendrule\n\n\tend //for buses\n\n\n\tinterface PhysMemSlave memSlave;\n\t\tinterface PhysMemReadServer read_server;\n\t\t\tinterface Put readReq;\n\t\t\t\tmethod Action put(PhysMemRequest#(FlashAddrWidth) req);\n\t\t\t\t\t//distribute each request to each buffer by bus\n\t\t\t\t\tPageAddrOff decAddr = decodePhysMemAddr(req.addr);\n\t\t\t\t\tpageBuffers[decAddr.faddr.bus].memSlave.read_server.readReq.put(req);\n\t\t\t\tendmethod\n\t\t\tendinterface\n\t\t\tinterface Get readData = toGet(slaveRespAggrQ);\n\t\tendinterface\n\t\tinterface PhysMemWriteServer write_server = ?;\n\tendinterface\n\n\tinterface Get flashReq = toGet(flashCmdAggrQ);\n\tinterface Put readResp = toPut(flashReadAggrQ);\nendmodule\n\t\n\n\n\n\n\n\n\nmodule mkSinglePageBuffer#(Integer busId)(PageBuffers);\n\n\t//BRAM\n\tBRAM2Port#(Bit#(PageOffsetSz), Bit#(WordSz)) pageBuffer <- mkBRAM2Server(defaultValue);\n\tReg#(PageBufferEntry) pageBufEntry <- mkReg(unpack(0));\n\tFIFO#(Tuple2#(Bit#(WordSz), TagT)) flashReadQ <- mkFIFO();\n\tFIFO#(FlashCmd) flashCmdQ <- mkFIFO();\n\tReg#(Bit#(BurstLenSize)) reqRemain <- mkReg(0); \n\tReg#(Bit#(BurstLenSize)) respRemain <- mkReg(0); \n\tReg#(Bit#(PageOffsetSz)) writePtr <- mkReg(0);\n\n\tFIFO#(MemData#(128)) slaveRespQ <- mkFIFO;\n\tFIFO#(TagT) freeTagQ <- mkSizedFIFO(num_tags);\n\tFIFO#(PhysMemRequest#(FlashAddrWidth)) slaveReqQ <- mkSizedFIFO(valueOf(NumTags)/valueOf(NUM_BUSES));\n\tReg#(BufOpState) state <- mkReg(ST_INIT);\n\n\t//split tags among these buffers\n\tReg#(Bit#(32)) tagCnt <- mkReg(0); //initialize to the id of this buffer\n\trule init (state==ST_INIT);\n\t\tlet tag = splitTagsByBus(busId, tagCnt);\n\t\tfreeTagQ.enq(tag);\n\t\t$display(\"FreeTag enq: %d\", tag);\n\t\tif (tagCnt == fromInteger(num_tags/num_buses-1)) begin\n\t\t\tstate <= ST_CMD;\n\t\t\ttagCnt <= 0;\n\t\tend\n\t\telse begin\n\t\t\ttagCnt <= tagCnt + 1;\n\t\tend\n\tendrule\n\n\t//decode address\n\tlet currReq = slaveReqQ.first;\n\tPageAddrOff addrOff = decodePhysMemAddr(currReq.addr);\n\trule handleSlaveReq (state==ST_CMD); \n\t\t$display(\"PageBuffers: Received slave command: addr=%x, len=%d, tag=%d\", currReq.addr,\n\t\t\tcurrReq.burstLen, currReq.tag);\n\t\t//slaveReqQ.deq; //FIXME: debug\n\t\t//look up in cache\n\t\tlet bus = addrOff.faddr.bus;\n\t\tif (pageBufEntry.valid && pageBufEntry.faddr==addrOff.faddr) begin\n\t\t\t//if hit, make request to BRAM\n\t\t\t$display(\"PageBuffers: hit\");\n\t\t\tstate <= ST_HIT;\n\t\t\treqRemain <= currReq.burstLen>>fromInteger(valueOf(WordBytesLog));\n\t\t\trespRemain <= currReq.burstLen>>fromInteger(valueOf(WordBytesLog));\n\t\tend\n\t\telse begin\n\t\t\t//if miss, make request to flash controller\n\t\t\t$display(\"PageBuffers: miss\");\n\t\t\tstate <= ST_MISS;\n\t\t\tpageBufEntry.valid <= False;\n\t\tend\n\t\t\n\tendrule\n\n\trule handleHit (state==ST_HIT && reqRemain>0);\n\t\tBit#(32) burstOffset = zeroExtend((currReq.burstLen>>fromInteger(valueOf(WordBytesLog))) - reqRemain); \n\t\tif (burstOffset >= fromInteger(pageWords)) begin\n\t\t\t$display(\"PageBuffer: **ERROR burstOffset exceeds number of pageWords\");\n\t\tend\n\t\tBit#(PageOffsetSz) baddr = addrOff.offset + truncate(burstOffset); //safe truncation\n\t\t$display(\"PageBuffer: portB read req addrOff=%x, burstOffset=%x, baddr= %x\", addrOff.offset, burstOffset, baddr);\n\t\tpageBuffer.portB.request.put(\n\t\t\tBRAMRequest{\n\t\t\t\twrite: False,\n\t\t\t\tresponseOnWrite: ?,\n\t\t\t\taddress: baddr,\n\t\t\t\tdatain: ?}\n\t\t);\n\t\treqRemain <= reqRemain - 1;\n\tendrule\n\t\n\trule handleHitData (state==ST_HIT);\n\t\tlet data <- pageBuffer.portB.response.get();\t\n\t\tBool last = (respRemain==1);\n\t\tslaveRespQ.enq( MemData { data: data, tag: currReq.tag, last: last} );\n\t\t$display(\"PageBuffer: hit data=%x, tag=%d, last=%d\", data, currReq.tag, last);\n\t\tif (respRemain==1) begin\n\t\t\tstate <= ST_CMD;\n\t\t\tslaveReqQ.deq; \n\t\tend\n\t\telse begin\n\t\t\trespRemain <= respRemain - 1;\n\t\tend\n\tendrule\n\n\n\trule missFlashRequest (state==ST_MISS);\n\t\t//get free tag\n\t\tfreeTagQ.deq;\n\t\tlet ftag = freeTagQ.first;\n\t\tFlashCmd fcmd = FlashCmd {\n\t\t\ttag: ftag,\n\t\t\top: READ_PAGE,\n\t\t\tbus: addrOff.faddr.bus,\n\t\t\tchip: addrOff.faddr.chip,\n\t\t\tblock: addrOff.faddr.block,\n\t\t\tpage: addrOff.faddr.page\n\t\t};\n\t\tflashCmdQ.enq(fcmd);\n\t\t$display(\"PageBuffers: missFlashRequest issued for: ftag=%d, bus=%d, chip=%d, blk=%d, page=%d\", \n\t\t\t\t\tftag, addrOff.faddr.bus, addrOff.faddr.chip, addrOff.faddr.block, addrOff.faddr.page);\n\t\tstate <= ST_MISS_READDATA;\n\tendrule\n\n\trule missGetFlashRead (state==ST_MISS_READDATA);\n\t\t//TODO: only one buffer, so no reordering per bus\n\t\tflashReadQ.deq;\n\t\tlet data = tpl_1(flashReadQ.first);\n\t\tlet tag = tpl_2(flashReadQ.first);\n\t\t$display(\"PageBuffers: got read data from flash: tag=%d, data=%x\", tag, data);\n\t\tpageBuffer.portA.request.put(\n\t\t\t\tBRAMRequest{ write:True, \n\t\t\t\t\t\t\tresponseOnWrite:False, \n\t\t\t\t\t\t\taddress:writePtr ,\n\t\t\t\t\t\t\tdatain: data } \n\t\t\t\t\t\t);\n\t\tif (writePtr==fromInteger(pageWords-1)) begin\n\t\t\t//update metadata about what's in the buffer\n\t\t\tpageBufEntry <= PageBufferEntry { valid: True, faddr: addrOff.faddr};\n\t\t\tfreeTagQ.enq(tag);\n\t\t\tstate <= ST_CMD; //reattempt command\n\t\t\twritePtr <= 0;\n\t\tend\n\t\telse begin\n\t\t\twritePtr <= writePtr + 1;\n\t\tend\n\tendrule\n\n\tinterface PhysMemSlave memSlave;\n\t\tinterface PhysMemReadServer read_server;\n\t\t\tinterface Put readReq = toPut(slaveReqQ);\n\t\t\tinterface Get readData = toGet(slaveRespQ);\n\t\tendinterface\n\t\tinterface PhysMemWriteServer write_server = ?;\n\tendinterface\n\n\tinterface Get flashReq = toGet(flashCmdQ);\n\tinterface Put readResp = toPut(flashReadQ);\n\n\nendmodule\n"
  },
  {
    "path": "tests/algo1_flashmodel/Top.bsv",
    "content": "/* Copyright (c) 2014 Quanta Research Cambridge, Inc\n *\n * Permission is hereby granted, free of charge, to any person obtaining a\n * copy of this software and associated documentation files (the \"Software\"),\n * to deal in the Software without restriction, including without limitation\n * the rights to use, copy, modify, merge, publish, distribute, sublicense,\n * and/or sell copies of the Software, and to permit persons to whom the\n * Software is furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n * DEALINGS IN THE SOFTWARE.\n */\nimport ConnectalConfig::*;\nimport SpecialFIFOs::*;\nimport Vector::*;\nimport BuildVector::*;\nimport StmtFSM::*;\nimport FIFO::*;\nimport BRAM::*;\nimport DefaultValue::*;\nimport Connectable::*;\nimport CtrlMux::*;\nimport Portal::*;\nimport HostInterface::*;\nimport ConnectalMemory::*;\nimport ConnectalMemTypes::*;\nimport MemServer::*;\nimport MemServerInternal::*;\nimport ConnectalMMU::*;\nimport MemReadEngine::*;\nimport MemWriteEngine::*;\nimport MMURequest::*;\nimport StrstrRequest::*;\nimport MemServerIndication::*;\nimport MMUIndication::*;\nimport StrstrIndication::*;\nimport NandSimNames::*;\nimport Strstr::*;\nimport AuroraCommon::*;\nimport FlashTop::*;\nimport ControllerTypes::*;\nimport FlashRequest::*;\nimport FlashIndication::*;\nimport TopPins::*;\n\nmodule mkConnectalTop#(HostInterface host)(ConnectalTop);\n   \n   Clock clk250 = host.derivedClock;\n   Reset rst250 = host.derivedReset;\n\t\n   // strstr algo\n   StrstrIndicationProxy strstrIndicationProxy <- mkStrstrIndicationProxy(IfcNames_AlgoIndicationH2S);\n   Strstr#(128,128) strstr <- mkStrstr(strstrIndicationProxy.ifc);\n   StrstrRequestWrapper strstrRequestWrapper <- mkStrstrRequestWrapper(IfcNames_AlgoRequestS2H,strstr.request);\n   \n   // algo mmu\n   MMUIndicationProxy algoMMUIndicationProxy <- mkMMUIndicationProxy(IfcNames_AlgoMMUIndicationH2S);\n   MMU#(PhysAddrWidth) algoMMU <- mkMMU(0, True, algoMMUIndicationProxy.ifc);\n   MMURequestWrapper algoMMURequestWrapper <- mkMMURequestWrapper(IfcNames_AlgoMMURequestS2H, algoMMU.request);\n\n   // backing store mmu\n   MMUIndicationProxy backingMMUIndicationProxy <- mkMMUIndicationProxy(IfcNames_BackingStoreMMUIndicationH2S);\n   MMU#(PhysAddrWidth) backingMMU <- mkMMU(1, True, backingMMUIndicationProxy.ifc);\n   MMURequestWrapper backingMMURequestWrapper <- mkMMURequestWrapper(IfcNames_BackingStoreMMURequestS2H, backingMMU.request);\n   \n   // nand mmu\n   MMUIndicationProxy nandMMUIndicationProxy <- mkMMUIndicationProxy(IfcNames_NandMMUIndicationH2S);\n   MMU#(FlashAddrWidth) nandMMU <- mkMMU(0, False, nandMMUIndicationProxy.ifc);\n   MMURequestWrapper nandMMURequestWrapper <- mkMMURequestWrapper(IfcNames_NandMMURequestS2H, nandMMU.request);\n\n   // flash top\n   FlashIndicationProxy flashIndicationProxy <- mkFlashIndicationProxy(IfcNames_NandCfgIndicationH2S);\n   FlashTop flashtop <- mkFlashTop(flashIndicationProxy.ifc, clk250, rst250);\n   FlashRequestWrapper flashRequestWrapper <- mkFlashRequestWrapper(IfcNames_NandCfgRequestS2H,flashtop.request);\n   \n   // host memory server\n   MemServerIndicationProxy hostMemServerIndicationProxy <- mkMemServerIndicationProxy(IfcNames_MemServerIndicationH2S);\n   let rcs = append(strstr.config_read_client,flashtop.hostMemReadClient);\n   let wcs = flashtop.hostMemWriteClient;\n   MemServer#(PhysAddrWidth,DataBusWidth,1) hostMemServer <- mkMemServer(rcs,wcs,vec(algoMMU,backingMMU), hostMemServerIndicationProxy.ifc);\n\n   // flash memory read server\n   MemServerIndicationProxy flashMemServerIndicationProxy <- mkMemServerIndicationProxy(IfcNames_NandMemServerIndicationH2S);\n   MemServer#(FlashAddrWidth,FlashDataWidth,1) flashMemServer <- mkMemServer(strstr.haystack_read_client, nil, vec(nandMMU),\n\t\t\t\t\t\t\t\t\t     flashMemServerIndicationProxy.ifc);\n   mkConnection(flashMemServer.masters[0], flashtop.memSlave);\n   \n   Vector#(12,StdPortal) portals;\n\n   portals[0] = strstrRequestWrapper.portalIfc;\n   portals[1] = strstrIndicationProxy.portalIfc; \n\n   portals[2] = algoMMURequestWrapper.portalIfc;\n   portals[3] = algoMMUIndicationProxy.portalIfc;\n   \n   portals[4] = nandMMURequestWrapper.portalIfc;\n   portals[5] = nandMMUIndicationProxy.portalIfc; \n   \n   portals[6] = flashRequestWrapper.portalIfc;\n   portals[7] = flashIndicationProxy.portalIfc;\n   \n   portals[8] = hostMemServerIndicationProxy.portalIfc;\n   //portals[9] = hostMemServerRequestWrapper.portalIfc;\n   portals[9] = flashMemServerIndicationProxy.portalIfc;\n   \n   portals[10] = backingMMURequestWrapper.portalIfc;\n   portals[11] = backingMMUIndicationProxy.portalIfc;\n\n\n   let ctrl_mux <- mkSlaveMux(portals);\n   \n   interface interrupt = getInterruptVector(portals);\n   interface slave = ctrl_mux;\n   interface masters = hostMemServer.masters;\n   interface Top_Pins pins;\n      interface Aurora_Pins aurora_fmc1 = flashtop.aurora_fmc1;\n      interface Aurora_Clock_Pins aurora_clk_fmc1 = flashtop.aurora_clk_fmc1;\n   endinterface\nendmodule : mkConnectalTop\n"
  },
  {
    "path": "tests/algo1_flashmodel/TopPins.bsv",
    "content": "/* Copyright (c) 2014 Quanta Research Cambridge, Inc\n *\n * Permission is hereby granted, free of charge, to any person obtaining a\n * copy of this software and associated documentation files (the \"Software\"),\n * to deal in the Software without restriction, including without limitation\n * the rights to use, copy, modify, merge, publish, distribute, sublicense,\n * and/or sell copies of the Software, and to permit persons to whom the\n * Software is furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n * DEALINGS IN THE SOFTWARE.\n */\nimport AuroraCommon::*;\n\ninterface Top_Pins;\n\tinterface Aurora_Pins#(4) aurora_fmc1;\n\tinterface Aurora_Clock_Pins aurora_clk_fmc1;\nendinterface\n"
  },
  {
    "path": "tests/algo1_flashmodel/flashaccess.cpp",
    "content": "// Copyright (c) 2015 The Connectal Project\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n#include <monkit.h>\n#include <list>\n#include <time.h>\n#include \"dmaManager.h\"\n#include \"FlashIndication.h\"\n#include \"FlashRequest.h\"\n\nstatic int trace_memory = 0;\nextern \"C\" {\n#include \"userReference.h\"\n}\n\n\n#define BLOCKS_PER_CHIP 2\n#define CHIPS_PER_BUS 8\n#define NUM_BUSES 8\n\n#define PAGE_SIZE 8192\n#define NUM_TAGS 128\n\ntypedef enum {\n\tUNINIT,\n\tERASED,\n\tWRITTEN\n} FlashStatusT;\n\ntypedef struct {\n\tbool busy;\n\tint bus;\n\tint chip;\n\tint block;\n} TagTableEntry;\n\nFlashRequestProxy *device;\n\npthread_mutex_t flashReqMutex;\npthread_cond_t flashFreeTagCond;\n\n//8k * 128\nsize_t dstAlloc_sz = PAGE_SIZE * NUM_TAGS *sizeof(unsigned char);\nsize_t srcAlloc_sz = PAGE_SIZE * NUM_TAGS *sizeof(unsigned char);\nint dstAlloc;\nint srcAlloc;\nunsigned int ref_dstAlloc; \nunsigned int ref_srcAlloc; \nunsigned int* dstBuffer;\nunsigned int* srcBuffer;\nunsigned int* readBuffers[NUM_TAGS];\nunsigned int* writeBuffers[NUM_TAGS];\nTagTableEntry readTagTable[NUM_TAGS]; \nTagTableEntry writeTagTable[NUM_TAGS]; \nTagTableEntry eraseTagTable[NUM_TAGS]; \nFlashStatusT flashStatus[NUM_BUSES][CHIPS_PER_BUS][BLOCKS_PER_CHIP];\n\nint testPass = 1;\nbool verbose = true;\nint curReadsInFlight = 0;\nint curWritesInFlight = 0;\nint curErasesInFlight = 0;\n\ndouble timespec_diff_sec( timespec start, timespec end ) {\n\tdouble t = end.tv_sec - start.tv_sec;\n\tt += ((double)(end.tv_nsec - start.tv_nsec)/1000000000L);\n\treturn t;\n}\n\n\nunsigned int hashAddrToData(int bus, int chip, int blk, int word) {\n\treturn ((bus<<24) + (chip<<20) + (blk<<16) + word);\n}\n\n\nbool checkReadData(int tag) {\n\tTagTableEntry e = readTagTable[tag];\n\tint goldenData;\n\tif (flashStatus[e.bus][e.chip][e.block]==WRITTEN) {\n\t\tint numErrors = 0;\n\t\tfor (int word=0; word<PAGE_SIZE/sizeof(unsigned int); word++) {\n\t\t\tgoldenData = hashAddrToData(e.bus, e.chip, e.block, word);\n\t\t\tif (goldenData != readBuffers[tag][word]) {\n\t\t\t\tfprintf(stderr, \"LOG: **ERROR: read data mismatch! Expected: %x, read: %x\\n\", goldenData, readBuffers[tag][word]);\n\t\t\t\tnumErrors++; \n\t\t\t\ttestPass = 0;\n\t\t\t}\n\t\t}\n\t\tif (numErrors==0) {\n\t\t\tfprintf(stderr, \"LOG: Read data check passed on tag=%d!\\n\", tag);\n\t\t}\n\t}\n\telse if (flashStatus[e.bus][e.chip][e.block]==ERASED) {\n\t\t//only check first word. It may return 0 if bad block, or -1 if erased\n\t\tif (readBuffers[tag][0]==-1) {\n\t\t\tfprintf(stderr, \"LOG: Read check pass on erased block!\\n\");\n\t\t}\n\t\telse if (readBuffers[tag][0]==0) {\n\t\t\tfprintf(stderr, \"LOG: Warning: potential bad block, read erased data 0\\n\");\n\t\t}\n\t\telse {\n\t\t\tfprintf(stderr, \"LOG: **ERROR: read data mismatch! Expected: ERASED, read: %x\\n\", readBuffers[tag][0]);\n\t\t\ttestPass = 0;\n\t\t}\n\t}\n\telse {\n\t\tfprintf(stderr, \"LOG: **ERROR: flash block state unknown. Did you erase before write?\\n\");\n\t\ttestPass = 0;\n\t}\n}\n\nclass FlashIndication : public FlashIndicationWrapper\n{\n\n\tpublic:\n\t\tFlashIndication(unsigned int id) : FlashIndicationWrapper(id){}\n\n\t\tvirtual void readDone(unsigned int tag) {\n\n\t\t\tif ( verbose ) {\n\t\t\t\t//printf( \"%s received read page buffer: %d %d\\n\", log_prefix, rbuf, curReadsInFlight );\n\t\t\t\tprintf( \"LOG: pagedone: tag=%d; inflight=%d\\n\", tag, curReadsInFlight );\n\t\t\t\tfflush(stdout);\n\t\t\t}\n\n\t\t\t//check \n\t\t\tcheckReadData(tag);\n\n\t\t\tpthread_mutex_lock(&flashReqMutex);\n\t\t\tcurReadsInFlight --;\n\t\t\tif ( curReadsInFlight < 0 ) {\n\t\t\t\tfprintf(stderr, \"LOG: **ERROR: Read requests in flight cannot be negative %d\\n\", curReadsInFlight );\n\t\t\t\tcurReadsInFlight = 0;\n\t\t\t}\n\t\t\tif ( readTagTable[tag].busy == false ) {\n\t\t\t\tfprintf(stderr, \"LOG: **ERROR: received unused buffer read done %d\\n\", tag);\n\t\t\t\ttestPass = 0;\n\t\t\t}\n\t\t\treadTagTable[tag].busy = false;\n\t\t\t//pthread_cond_broadcast(&flashFreeTagCond);\n\t\t\tpthread_mutex_unlock(&flashReqMutex);\n\t\t}\n\n\t\tvirtual void writeDone(unsigned int tag) {\n\t\t\tprintf(\"LOG: writedone, tag=%d\\n\", tag); fflush(stdout);\n\t\t\t//TODO probably should use a diff lock\n\t\t\tpthread_mutex_lock(&flashReqMutex);\n\t\t\tcurWritesInFlight--;\n\t\t\tif ( curWritesInFlight < 0 ) {\n\t\t\t\tfprintf(stderr, \"LOG: **ERROR: Write requests in flight cannot be negative %d\\n\", curWritesInFlight );\n\t\t\t\tcurWritesInFlight = 0;\n\t\t\t}\n\t\t\tif ( writeTagTable[tag].busy == false ) {\n\t\t\t\tfprintf(stderr, \"LOG: **ERROR: received unused buffer Write done %d\\n\", tag);\n\t\t\t\ttestPass = 0;\n\t\t\t}\n\t\t\twriteTagTable[tag].busy = false;\n\t\t\tpthread_mutex_unlock(&flashReqMutex);\n\t\t}\n\n\t\tvirtual void eraseDone(unsigned int tag, unsigned int status) {\n\t\t\tprintf(\"LOG: eraseDone, tag=%d, status=%d\\n\", tag, status); fflush(stdout);\n\t\t\tif (status != 0) {\n\t\t\t\tprintf(\"LOG: detected bad block with tag = %d\\n\", tag);\n\t\t\t}\n\n\t\t\tpthread_mutex_lock(&flashReqMutex);\n\t\t\tcurErasesInFlight--;\n\t\t\tif ( curErasesInFlight < 0 ) {\n\t\t\t\tfprintf(stderr, \"LOG: **ERROR: erase requests in flight cannot be negative %d\\n\", curErasesInFlight );\n\t\t\t\tcurErasesInFlight = 0;\n\t\t\t}\n\t\t\tif ( eraseTagTable[tag].busy == false ) {\n\t\t\t\tfprintf(stderr, \"LOG: **ERROR: received unused tag erase done %d\\n\", tag);\n\t\t\t\ttestPass = 0;\n\t\t\t}\n\t\t\teraseTagTable[tag].busy = false;\n\t\t\tpthread_mutex_unlock(&flashReqMutex);\n\t\t}\n\n\t\tvirtual void debugDumpResp (unsigned int debug0, unsigned int debug1,  unsigned int debug2, unsigned int debug3) {\n\t\t\t//uint64_t cntHi = debugRdCntHi;\n\t\t\t//uint64_t rdCnt = (cntHi<<32) + debugRdCntLo;\n\t\t\tfprintf(stderr, \"LOG: DEBUG DUMP: gearSend = %d, gearRec = %d, aurSend = %d, aurRec = %d\\n\", debug0, debug1, debug2, debug3);\n\t\t}\n\n\n};\n\n\n\n\nint getNumReadsInFlight() { return curReadsInFlight; }\nint getNumWritesInFlight() { return curWritesInFlight; }\nint getNumErasesInFlight() { return curErasesInFlight; }\n\n\n\n//TODO: more efficient locking\nint waitIdleEraseTag() {\n\tint tag = -1;\n\twhile ( tag < 0 ) {\n\tpthread_mutex_lock(&flashReqMutex);\n\n\t\tfor ( int t = 0; t < NUM_TAGS; t++ ) {\n\t\t\tif ( !eraseTagTable[t].busy ) {\n\t\t\t\teraseTagTable[t].busy = true;\n\t\t\t\ttag = t;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\tpthread_mutex_unlock(&flashReqMutex);\n\t\t/*\n\t\tif (tag < 0) {\n\t\t\tpthread_cond_wait(&flashFreeTagCond, &flashReqMutex);\n\t\t}\n\t\telse {\n\t\t\tpthread_mutex_unlock(&flashReqMutex);\n\t\t\treturn tag;\n\t\t}\n\t\t*/\n\t}\n\treturn tag;\n}\n\n\n//TODO: more efficient locking\nint waitIdleWriteBuffer() {\n\tint tag = -1;\n\twhile ( tag < 0 ) {\n\tpthread_mutex_lock(&flashReqMutex);\n\n\t\tfor ( int t = 0; t < NUM_TAGS; t++ ) {\n\t\t\tif ( !writeTagTable[t].busy) {\n\t\t\t\twriteTagTable[t].busy = true;\n\t\t\t\ttag = t;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\tpthread_mutex_unlock(&flashReqMutex);\n\t\t/*\n\t\tif (tag < 0) {\n\t\t\tpthread_cond_wait(&flashFreeTagCond, &flashReqMutex);\n\t\t}\n\t\telse {\n\t\t\tpthread_mutex_unlock(&flashReqMutex);\n\t\t\treturn tag;\n\t\t}\n\t\t*/\n\t}\n\treturn tag;\n}\n\n\n\n//TODO: more efficient locking\nint waitIdleReadBuffer() {\n\tint tag = -1;\n\twhile ( tag < 0 ) {\n\tpthread_mutex_lock(&flashReqMutex);\n\n\t\tfor ( int t = 0; t < NUM_TAGS; t++ ) {\n\t\t\tif ( !readTagTable[t].busy ) {\n\t\t\t\treadTagTable[t].busy = true;\n\t\t\t\ttag = t;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\tpthread_mutex_unlock(&flashReqMutex);\n\t\t/*\n\t\tif (tag < 0) {\n\t\t\tpthread_cond_wait(&flashFreeTagCond, &flashReqMutex);\n\t\t}\n\t\telse {\n\t\t\tpthread_mutex_unlock(&flashReqMutex);\n\t\t\treturn tag;\n\t\t}\n\t\t*/\n\t}\n\treturn tag;\n}\n\n\nvoid eraseBlock(int bus, int chip, int block, int tag) {\n\tpthread_mutex_lock(&flashReqMutex);\n\tcurErasesInFlight ++;\n\tflashStatus[bus][chip][block] = ERASED;\n\tpthread_mutex_unlock(&flashReqMutex);\n\n\tif ( verbose ) fprintf(stderr, \"LOG: sending erase block request with tag=%d @%d %d %d 0\\n\", tag, bus, chip, block );\n\tdevice->eraseBlock(bus,chip,block,tag);\n}\n\n\n\nvoid writePage(int bus, int chip, int block, int page, int tag) {\n\tpthread_mutex_lock(&flashReqMutex);\n\tcurWritesInFlight ++;\n\tflashStatus[bus][chip][block] = WRITTEN;\n\tpthread_mutex_unlock(&flashReqMutex);\n\n\tif ( verbose ) fprintf(stderr, \"LOG: sending write page request with tag=%d @%d %d %d %d\\n\", tag, bus, chip, block, page );\n\tdevice->writePage(bus,chip,block,page,tag);\n}\n\nvoid readPage(int bus, int chip, int block, int page, int tag) {\n\tpthread_mutex_lock(&flashReqMutex);\n\tcurReadsInFlight ++;\n\treadTagTable[tag].bus = bus;\n\treadTagTable[tag].chip = chip;\n\treadTagTable[tag].block = block;\n\tpthread_mutex_unlock(&flashReqMutex);\n\n\tif ( verbose ) fprintf(stderr, \"LOG: sending read page request with tag=%d @%d %d %d %d\\n\", tag, bus, chip, block, page );\n\tdevice->readPage(bus,chip,block,page,tag);\n}\n\n\nint main(int argc, const char **argv)\n{\n        DmaManager *dma = platformInit();\n\tfprintf(stderr, \"Main::allocating memory...\\n\");\n\n\tdevice = new FlashRequestProxy(IfcNames_NandCfgRequest);\n\tFlashIndication *deviceIndication = new FlashIndication(IfcNames_NandCfgIndication);\n\t\n\tsrcAlloc = portalAlloc(srcAlloc_sz, 0);\n\tdstAlloc = portalAlloc(dstAlloc_sz, 0);\n\tsrcBuffer = (unsigned int *)portalMmap(srcAlloc, srcAlloc_sz);\n\tdstBuffer = (unsigned int *)portalMmap(dstAlloc, dstAlloc_sz);\n\n\tfprintf(stderr, \"dstAlloc = %x\\n\", dstAlloc); \n\tfprintf(stderr, \"srcAlloc = %x\\n\", srcAlloc); \n\t\n\tpthread_mutex_init(&flashReqMutex, NULL);\n\tpthread_cond_init(&flashFreeTagCond, NULL);\n\n\tprintf( \"Done initializing hw interfaces\\n\" ); fflush(stdout);\n\n\tportalCacheFlush(dstAlloc, dstBuffer, dstAlloc_sz, 1);\n\tportalCacheFlush(srcAlloc, srcBuffer, srcAlloc_sz, 1);\n\tref_dstAlloc = dma->reference(dstAlloc);\n\tref_srcAlloc = dma->reference(srcAlloc);\n\n\tfor (int t = 0; t < NUM_TAGS; t++) {\n\t\treadTagTable[t].busy = false;\n\t\twriteTagTable[t].busy = false;\n\t\tint byteOffset = t * PAGE_SIZE;\n\t\tdevice->addDmaWriteRefs(ref_dstAlloc, byteOffset, t);\n\t\tdevice->addDmaReadRefs(ref_srcAlloc, byteOffset, t);\n\t\treadBuffers[t] = dstBuffer + byteOffset/sizeof(unsigned int);\n\t\twriteBuffers[t] = srcBuffer + byteOffset/sizeof(unsigned int);\n\t}\n\t\n\tfor (int blk=0; blk<BLOCKS_PER_CHIP; blk++) {\n\t\tfor (int c=0; c<CHIPS_PER_BUS; c++) {\n\t\t\tfor (int bus=0; bus< CHIPS_PER_BUS; bus++) {\n\t\t\t\tflashStatus[bus][c][blk] = UNINIT;\n\t\t\t}\n\t\t}\n\t}\n\n\n\tfor (int t = 0; t < NUM_TAGS; t++) {\n\t\tfor ( int i = 0; i < PAGE_SIZE/sizeof(unsigned int); i++ ) {\n\t\t\treadBuffers[t][i] = 0;\n\t\t\twriteBuffers[t][i] = 0;\n\t\t}\n\t}\n\n\tdevice->start(0);\n\tdevice->setDebugVals(0,0); //flag, delay\n\n\tdevice->debugDumpReq(0);\n\tsleep(1);\n\tdevice->debugDumpReq(0);\n\tsleep(1);\n\t//TODO: test writes and erases\n\t\n\n\n\t//test erases\n\tfor (int blk = 0; blk < BLOCKS_PER_CHIP; blk++){\n\t\tfor (int chip = 0; chip < CHIPS_PER_BUS; chip++){\n\t\t\tfor (int bus = 0; bus < NUM_BUSES; bus++){\n\t\t\t\teraseBlock(bus, chip, blk, waitIdleEraseTag());\n\t\t\t}\n\t\t}\n\t}\n\n\twhile (true) {\n\t\tusleep(100);\n\t\tif ( getNumErasesInFlight() == 0 ) break;\n\t}\n\t\n\t//read back erased pages\n\tfor (int blk = 0; blk < BLOCKS_PER_CHIP; blk++){\n\t\tfor (int chip = 0; chip < CHIPS_PER_BUS; chip++){\n\t\t\tfor (int bus = 0; bus < NUM_BUSES; bus++){\n\t\t\t\tint page = 0;\n\t\t\t\treadPage(bus, chip, blk, page, waitIdleReadBuffer());\n\t\t\t}\n\t\t}\n\t}\n\twhile (true) {\n\t\tusleep(100);\n\t\tif ( getNumReadsInFlight() == 0 ) break;\n\t}\n\n\n\t//write pages\n\t//FIXME: in old xbsv, simulatneous DMA reads using multiple readers cause kernel panic\n\t//Issue each bus separately for now\n\tfor (int bus = 0; bus < NUM_BUSES; bus++){\n\t\n\t\tfor (int blk = 0; blk < BLOCKS_PER_CHIP; blk++){\n\t\t\tfor (int chip = 0; chip < CHIPS_PER_BUS; chip++){\n\t\t\t\tint page = 0;\n\t\t\t\t//get free tag\n\t\t\t\tint freeTag = waitIdleWriteBuffer();\n\t\t\t\t//fill write memory\n\t\t\t\tfor (int w=0; w<PAGE_SIZE/sizeof(unsigned int); w++) {\n\t\t\t\t\twriteBuffers[freeTag][w] = hashAddrToData(bus, chip, blk, w);\n\t\t\t\t}\n\t\t\t\t//send request\n\t\t\t\twritePage(bus, chip, blk, page, freeTag);\n\t\t\t}\n\t\t}\n\t\t\n\t\t\n\t\twhile (true) {\n\t\t\tusleep(100);\n\t\t\tif ( getNumWritesInFlight() == 0 ) break;\n\t\t}\n\t} //each bus\n\t\n\n\ttimespec start, now;\n\tclock_gettime(CLOCK_REALTIME, & start);\n\n\tfor (int repeat = 0; repeat < 1; repeat++){\n\t\tfor (int blk = 0; blk < BLOCKS_PER_CHIP; blk++){\n\t\t\tfor (int chip = 0; chip < CHIPS_PER_BUS; chip++){\n\t\t\t\tfor (int bus = 0; bus < NUM_BUSES; bus++){\n\n\t\t\t\t//int blk = rand() % 1024;\n\t\t\t\t//int chip = rand() % 8;\n\t\t\t\t//int bus = rand() % 8;\n\t\t\t\t\tint page = 0;\n\t\t\t\t\treadPage(bus, chip, blk, page, waitIdleReadBuffer());\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t}\n\t\n\tint elapsed = 0;\n\twhile (true) {\n\t\tusleep(100);\n\t\tif (elapsed == 0) {\n\t\t\telapsed=10000;\n\t\t\tdevice->debugDumpReq(0);\n\t\t}\n\t\telse {\n\t\t\telapsed--;\n\t\t}\n\t\tif ( getNumReadsInFlight() == 0 ) break;\n\t}\n\tdevice->debugDumpReq(0);\n\n\tclock_gettime(CLOCK_REALTIME, & now);\n\tfprintf(stderr, \"LOG: finished reading from page! %f\\n\", timespec_diff_sec(start, now) );\n\n\tfor ( int t = 0; t < NUM_TAGS; t++ ) {\n\t\tfor ( int i = 0; i < PAGE_SIZE/sizeof(unsigned int); i++ ) {\n\t\t\tfprintf(stderr,  \"%x %x %x\\n\", t, i, readBuffers[t][i] );\n\t\t}\n\t}\n\tif (testPass==1) {\n\t\tfprintf(stderr, \"LOG: TEST PASSED!\\n\");\n\t}\n\telse {\n\t\tfprintf(stderr, \"LOG: **ERROR: TEST FAILED!\\n\");\n\t}\n\n\n}\n"
  },
  {
    "path": "tests/algo1_flashmodel/test.cpp",
    "content": "/* Copyright (c) 2014 Quanta Research Cambridge, Inc\n *\n * Permission is hereby granted, free of charge, to any person obtaining a\n * copy of this software and associated documentation files (the \"Software\"),\n * to deal in the Software without restriction, including without limitation\n * the rights to use, copy, modify, merge, publish, distribute, sublicense,\n * and/or sell copies of the Software, and to permit persons to whom the\n * Software is furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n * DEALINGS IN THE SOFTWARE.\n */\n#include <fstream>\n#include <iostream>\n#include <errno.h>\n#include <sys/types.h>\n#include <sys/socket.h>\n#include <sys/un.h>\n#include <sys/mman.h>\n#include <assert.h>\n#include <mp.h>\n#include \"dmaManager.h\"\n#include \"StrstrIndication.h\"\n#include \"StrstrRequest.h\"\n#include \"MMURequest.h\"\n#include \"MMUIndication.h\"\n#include \"MemServerRequest.h\"\n#include \"MemServerIndication.h\"\n\nstatic int trace_memory = 1;\nextern \"C\" {\n#include \"sys/ioctl.h\"\n#include \"drivers/portalmem/portalmem.h\"\n#include \"sock_utils.h\"\n#include \"userReference.h\"\n}\n\n#include \"nandsim.h\"\n#include \"strstr.h\"\n\nclass MMUIndication : public MMUIndicationWrapper\n{\n  DmaManager *portalMemory;\n public:\n  MMUIndication(DmaManager *pm, unsigned int  id, int tile=DEFAULT_TILE) : MMUIndicationWrapper(id,tile), portalMemory(pm) {}\n  MMUIndication(DmaManager *pm, unsigned int  id, PortalTransportFunctions *item, void *param) : MMUIndicationWrapper(id, item, param), portalMemory(pm) {}\n  virtual void configResp(uint32_t pointer){\n    fprintf(stderr, \"MMUIndication::configResp: %x\\n\", pointer);\n    portalMemory->confResp(pointer);\n  }\n  virtual void error (uint32_t code, uint32_t pointer, uint64_t offset, uint64_t extra) {\n    fprintf(stderr, \"MMUIndication::error(code=0x%x:%s, pointer=0x%x, offset=0x%\"PRIx64\" extra=0x%\"PRIx64\"\\n\", code, dmaErrors[code], pointer, offset, extra);\n    if (--mmu_error_limit < 0)\n        exit(-1);\n  }\n  virtual void idResponse(uint32_t sglId){\n    portalMemory->sglIdResp(sglId);\n  }\n};\n\nclass MemServerIndication : public MemServerIndicationWrapper\n{\n  MemServerRequestProxy *memServerRequestProxy;\n  sem_t mtSem;\n  uint64_t mtCnt;\n  void init(){\n    if (sem_init(&mtSem, 0, 0))\n      PORTAL_PRINTF(\"MemServerIndication::init failed to init mtSem\\n\");\n  }\n public:\n  MemServerIndication(unsigned int  id, int tile=DEFAULT_TILE) : MemServerIndicationWrapper(id,tile), memServerRequestProxy(NULL) {init();}\n  MemServerIndication(MemServerRequestProxy *p, unsigned int  id, int tile=DEFAULT_TILE) : MemServerIndicationWrapper(id,tile), memServerRequestProxy(p) {init();}\n  virtual void addrResponse(uint64_t physAddr){\n    fprintf(stderr, \"DmaIndication::addrResponse(physAddr=%\"PRIx64\")\\n\", physAddr);\n  }\n  virtual void reportStateDbg(const DmaDbgRec rec){\n    fprintf(stderr, \"MemServerIndication::reportStateDbg: {x:%08x y:%08x z:%08x w:%08x}\\n\", rec.x,rec.y,rec.z,rec.w);\n  }\n  virtual void reportMemoryTraffic(uint64_t words){\n    //fprintf(stderr, \"reportMemoryTraffic: words=%\"PRIx64\"\\n\", words);\n    mtCnt = words;\n    sem_post(&mtSem);\n  }\n  virtual void error (uint32_t code, uint32_t pointer, uint64_t offset, uint64_t extra) {\n    fprintf(stderr, \"MemServerIndication::error(code=%x, pointer=%x, offset=%\"PRIx64\" extra=%\"PRIx64\"\\n\", code, pointer, offset, extra);\n    if (--mem_error_limit < 0)\n      exit(-1);\n  }\n  uint64_t receiveMemoryTraffic(){\n    sem_wait(&mtSem);\n    return mtCnt; \n  }\n  uint64_t getMemoryTraffic(const ChannelType rc){\n    assert(memServerRequestProxy);\n    memServerRequestProxy->memoryTraffic(rc);\n    return receiveMemoryTraffic();\n  }\n};\n\nsize_t numBytes = 1 << 10;\n\nint main(int argc, const char **argv)\n{\n  fprintf(stderr, \"Main::%s %s\\n\", __DATE__, __TIME__);\n  DmaManager *hostDma = platformInit();\n  MMURequestProxy *nandsimMMURequest = new MMURequestProxy(IfcNames_NandMMURequestS2H);\n  DmaManager *nandsimDma = new DmaManager(nandsimMMURequest);\n  MMUIndication nandsimMMUIndication(nandsimDma,IfcNames_NandMMUIndicationH2S);\n\n  StrstrRequestProxy *strstrRequest = new StrstrRequestProxy(IfcNames_AlgoRequestS2H);\n  StrstrIndication *strstrIndication = new StrstrIndication(IfcNames_AlgoIndicationH2S);\n  \n  MemServerIndication hostMemServerIndication(IfcNames_MemServerIndicationH2S);\n  MemServerIndication nandsimMemServerIndication(IfcNames_NandMemServerIndicationH2S);\n\n  fprintf(stderr, \"Main::allocating memory...\\n\");\n\n  // allocate memory for strstr data\n  int needleAlloc = portalAlloc(numBytes, 0);\n  int mpNextAlloc = portalAlloc(numBytes, 0);\n  int ref_needleAlloc = hostDma->reference(needleAlloc);\n  int ref_mpNextAlloc = hostDma->reference(mpNextAlloc);\n\n  fprintf(stderr, \"%08x %08x\\n\", ref_needleAlloc, ref_mpNextAlloc);\n\n  char *needle = (char *)portalMmap(needleAlloc, numBytes);\n  int *mpNext = (int *)portalMmap(mpNextAlloc, numBytes);\n\n  const char *needle_text = \"ababab\";\n  int needle_len = strlen(needle_text);\n  strncpy(needle, needle_text, needle_len);\n  compute_MP_next(needle, mpNext, needle_len);\n\n  // fprintf(stderr, \"mpNext=[\");\n  // for(int i= 0; i <= needle_len; i++) \n  //   fprintf(stderr, \"%d \", mpNext[i]);\n  // fprintf(stderr, \"]\\nneedle=[\");\n  // for(int i= 0; i < needle_len; i++) \n  //   fprintf(stderr, \"%d \", needle[i]);\n  // fprintf(stderr, \"]\\n\");\n\n  portalCacheFlush(needleAlloc, needle, numBytes, 1);\n  portalCacheFlush(mpNextAlloc, mpNext, numBytes, 1);\n  fprintf(stderr, \"Main::flush and invalidate complete\\n\");\n\n // fprintf(stderr, \"Main::waiting to connect to nandsim_exe\\n\");\n // wait_for_connect_nandsim_exe();\n // fprintf(stderr, \"Main::connected to nandsim_exe\\n\");\n  // base of haystack in \"flash\" memory\n  // this is read from nandsim_exe, but could also come from kernel driver\n  //int haystack_base = read_from_nandsim_exe();\n  //int haystack_len  = read_from_nandsim_exe();\n  int haystack_len  = 0x100;\n\n  // request the next sglist identifier from the sglistMMU hardware module\n  // which is used by the mem server accessing flash memory.\n  int id = 0;\n  MMURequest_idRequest(nandsimDma->priv.sglDevice, 0);\n  sem_wait(&nandsimDma->priv.sglIdSem);\n  id = nandsimDma->priv.sglId;\n  // pairs of ('offset','size') pointing to space in nandsim memory\n  // this is unsafe.  To do it properly, we should get this list from\n  // nandsim_exe or from the kernel driver.  This code here might overrun\n  // the backing store allocated by nandsim_exe.\n // RegionRef region[] = {{0, 0x100000}, {0x100000, 0x100000}};\n  RegionRef region[] = {{0x100000, 0x100000}};\n  printf(\"[%s:%d]\\n\", __FUNCTION__, __LINE__);\n  int ref_haystackInNandMemory = send_reference_to_portal(nandsimDma->priv.sglDevice, sizeof(region)/sizeof(region[0]), region, id);\n  sem_wait(&(nandsimDma->priv.confSem));\n  fprintf(stderr, \"%08x\\n\", ref_haystackInNandMemory);\n\n  // at this point, ref_needleAlloc and ref_mpNextAlloc are valid sgListIds for use by \n  // the host memory dma hardware, and ref_haystackInNandMemory is a valid sgListId for\n  // use by the nandsim dma hardware\n\n  fprintf(stderr, \"about to setup device %d %d\\n\", ref_needleAlloc, ref_mpNextAlloc);\n  strstrRequest->setup(ref_needleAlloc, ref_mpNextAlloc, needle_len);\n  fprintf(stderr, \"about to invoke search %d\\n\", ref_haystackInNandMemory);\n  strstrRequest->search(ref_haystackInNandMemory, haystack_len);\n  strstrIndication->wait();  \n  fprintf(stderr, \"algo1_flashmodel: Done\\n\");\n  sleep(2);\n\n  exit(!(strstrIndication->match_cnt==3));\n}\n"
  },
  {
    "path": "tests/algo1_nandsim_manual/Makefile",
    "content": "\nCONNECTALDIR?=../..\nINTERFACES = NandCfgRequest StrstrRequest NandCfgIndication StrstrIndication\nBSVFILES = $(CONNECTALDIR)/lib/nandsim/bsv/NandSim.bsv $(CONNECTALDIR)/lib/strstr/bsv/Strstr.bsv $(CONNECTALDIR)/examples/algo1_nandsim/Top.bsv $(CONNECTALDIR)/lib/nandsim/bsv/NandSimNames.bsv\nCPPFILES=algo1.cpp\nCPPFILES2=nandsim_manual.c\nCONNECTALFLAGS += -D2 NO_CPP_PORTAL_CODE -lm\nCONNECTALFLAGS += -D DEGPAR=2\n# -lblkid\nCONNECTALFLAGS += -I$(CONNECTALDIR)/lib/strstr/cpp\nCONNECTALFLAGS += -DNO_POLLER_SUPPORT\n\ninclude $(CONNECTALDIR)/Makefile.connectal\n"
  },
  {
    "path": "tests/algo1_nandsim_manual/algo1.cpp",
    "content": "/* Copyright (c) 2014 Quanta Research Cambridge, Inc\n *\n * Permission is hereby granted, free of charge, to any person obtaining a\n * copy of this software and associated documentation files (the \"Software\"),\n * to deal in the Software without restriction, including without limitation\n * the rights to use, copy, modify, merge, publish, distribute, sublicense,\n * and/or sell copies of the Software, and to permit persons to whom the\n * Software is furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n * DEALINGS IN THE SOFTWARE.\n */\n#include <fstream>\n#include <iostream>\n#include <errno.h>\n#include <sys/types.h>\n#include <sys/socket.h>\n#include <sys/un.h>\n#include <sys/mman.h>\n#include <assert.h>\n#include <mp.h>\n#include \"dmaManager.h\"\n#include \"NandCfgIndication.h\"\n#include \"NandCfgRequest.h\"\n#include \"StrstrIndication.h\"\n#include \"StrstrRequest.h\"\n\nstatic int trace_memory = 1;\nextern \"C\" {\n#include \"sys/ioctl.h\"\n#include \"drivers/portalmem/portalmem.h\"\n#include \"sock_utils.h\"\n#include \"userReference.h\"\n}\n\nsize_t numBytes = 1 << 12;\n#ifndef BOARD_bluesim\nsize_t nandBytes = 1 << 24;\n#else\nsize_t nandBytes = 1 << 14;\n#endif\n\nclass NandCfgIndication : public NandCfgIndicationWrapper\n{\npublic:\n  unsigned int rDataCnt;\n  virtual void readDone(uint32_t v){\n    fprintf(stderr, \"NandSim::readDone v=%x\\n\", v);\n    sem_post(&sem);\n  }\n  virtual void writeDone(uint32_t v){\n    fprintf(stderr, \"NandSim::writeDone v=%x\\n\", v);\n    sem_post(&sem);\n  }\n  virtual void eraseDone(uint32_t v){\n    fprintf(stderr, \"NandSim::eraseDone v=%x\\n\", v);\n    sem_post(&sem);\n  }\n  virtual void configureNandDone(){\n    fprintf(stderr, \"NandSim::configureNandDone\\n\");\n    sem_post(&sem);\n  }\n\n  NandCfgIndication(int id) : NandCfgIndicationWrapper(id) {\n    sem_init(&sem, 0, 0);\n  }\n  void wait() {\n    fprintf(stderr, \"NandSim::wait for semaphore\\n\");\n    sem_wait(&sem);\n  }\nprivate:\n  sem_t sem;\n};\n\nclass StrstrIndication : public StrstrIndicationWrapper\n{\npublic:\n  StrstrIndication(unsigned int id) : StrstrIndicationWrapper(id){\n    sem_init(&sem, 0, 0);\n    match_cnt = 0;\n  };\n  virtual void setupComplete() {\n    fprintf(stderr, \"Strstr::setupComplete\\n\");\n    sem_post(&sem);\n  }\n  virtual void searchResult (int v){\n    fprintf(stderr, \"searchResult = %d\\n\", v);\n    if (v == -1)\n      sem_post(&sem);\n    else \n      match_cnt++;\n  }\n  void wait() {\n    fprintf(stderr, \"Strstr::wait for semaphore\\n\");\n    sem_wait(&sem);\n  }\n  int match_cnt;\nprivate:\n  sem_t sem;\n};\n\n\n\n\nint main(int argc, const char **argv)\n{\n  fprintf(stderr, \"Main::%s %s\\n\", __DATE__, __TIME__);\n  DmaManager *dma = platformInit();\n  MMURequestProxy *nandMMURequest = new MMURequestProxy(IfcNames_NandMMURequest);\n  DmaManager *nandsimDma = new DmaManager(nandMMURequest);\n  MMUIndication *nandMMUIndication = new MMUIndication(nandsimDma,IfcNames_NandMMUIndication);\n\n  StrstrRequestProxy *strstrRequest = new StrstrRequestProxy(IfcNames_AlgoRequest);\n  StrstrIndication *strstrIndication = new StrstrIndication(IfcNames_AlgoIndication);\n\n  fprintf(stderr, \"Main::allocating memory...\\n\");\n\n  // allocate memory for strstr data\n  int needleAlloc = portalAlloc(numBytes, 0);\n  int mpNextAlloc = portalAlloc(numBytes, 0);\n  int ref_needleAlloc = hostDma->reference(needleAlloc);\n  int ref_mpNextAlloc = hostDma->reference(mpNextAlloc);\n\n  fprintf(stderr, \"%08x %08x\\n\", ref_needleAlloc, ref_mpNextAlloc);\n\n  char *needle = (char *)portalMmap(needleAlloc, numBytes);\n  int *mpNext = (int *)portalMmap(mpNextAlloc, numBytes);\n\n  const char *needle_text = \"ababab\";\n  int needle_len = strlen(needle_text);\n  strncpy(needle, needle_text, needle_len);\n  compute_MP_next(needle, mpNext, needle_len);\n\n  // fprintf(stderr, \"mpNext=[\");\n  // for(int i= 0; i <= needle_len; i++) \n  //   fprintf(stderr, \"%d \", mpNext[i]);\n  // fprintf(stderr, \"]\\nneedle=[\");\n  // for(int i= 0; i < needle_len; i++) \n  //   fprintf(stderr, \"%d \", needle[i]);\n  // fprintf(stderr, \"]\\n\");\n\n  portalCacheFlush(needleAlloc, needle, numBytes, 1);\n  portalCacheFlush(mpNextAlloc, mpNext, numBytes, 1);\n  fprintf(stderr, \"Main::flush and invalidate complete\\n\");\n\n  // base of haystack in \"flash\" memory\n  // this is read from nandsim_exe, but could also come from kernel driver\n  int haystack_base = 0;\n  int haystack_len  = 64;\n\n  // request the next sglist identifier from the sglistMMU hardware module\n  // which is used by the mem server accessing flash memory.\n  int id = 0;\n  MMURequest_idRequest(nandsimDma->priv.sglDevice, -1);\n  sem_wait(&nandsimDma->priv.sglIdSem);\n  id = nandsimDma->priv.sglId;\n  // pairs of ('offset','size') pointing to space in nandsim memory\n  // this is unsafe.  To do it properly, we should get this list from\n  // nandsim_exe or from the kernel driver.  This code here might overrun\n  // the backing store allocated by nandsim_exe.\n  RegionRef region[] = {{0, 0x100000}, {0x100000, 0x100000}};\n  printf(\"[%s:%d]\\n\", __FUNCTION__, __LINE__);\n  int ref_haystackInNandMemory = send_reference_to_portal(nandsimDma->priv.sglDevice, sizeof(region)/sizeof(region[0]), region, id);\n  sem_wait(&(nandsimDma->priv.confSem));\n  fprintf(stderr, \"%08x\\n\", ref_haystackInNandMemory);\n\n  // at this point, ref_needleAlloc and ref_mpNextAlloc are valid sgListIds for use by \n  // the host memory dma hardware, and ref_haystackInNandMemory is a valid sgListId for\n  // use by the nandsim dma hardware\n\n  fprintf(stderr, \"about to setup device %d %d\\n\", ref_needleAlloc, ref_mpNextAlloc);\n  strstrRequest->setup(ref_needleAlloc, ref_mpNextAlloc, needle_len);\n  strstrIndication->wait();\n\n  fprintf(stderr, \"about to invoke search %d\\n\", ref_haystackInNandMemory);\n  strstrRequest->search(ref_haystackInNandMemory, haystack_len);\n  strstrIndication->wait();  \n\n  exit(!(strstrIndication->match_cnt==3));\n}\n"
  },
  {
    "path": "tests/algo1_nandsim_manual/haystack.txt",
    "content": "acabcabacababacababababababcacabcabacababacabababc\n012345678912\n"
  },
  {
    "path": "tests/algo1_nandsim_manual/kernel/Makefile",
    "content": "\n# grep get_pcie_portal_descriptor /proc/kallsyms \n\n###################### Flags for using KC705   ###################\n#BOARD=kc705\n###################### Flags for using VC707   ###################\nBOARD=vc707\n###################### Flags for using zedboard ##################\n#BOARD=zedboard\n###################### Flags for using Bluesim ###################\n#BOARD=bluesim\n###################### End of target h/w flags ###################\n\nifeq ($(BOARD),bluesim)\n    HARDWARE_FLAGS=-DBSIM\nendif\n\nexport KROOT=/lib/modules/$(shell uname -r)/build\nCPPDIR=../../../cpp\nBOARDDIR=../$(BOARD)/jni\nDRIVERDIR=$(src)/../../../drivers\n\nKBUILD_EXTRA_SYMBOLS := $(DRIVERDIR)/pcieportal/Module.symvers $(DRIVERDIR)/portalmem/Module.symvers\n\n   #$(BOARDDIR)/DmaConfigProxy.o \\\n     #$(BOARDDIR)/DmaIndicationWrapper.o \\\n\n\nkernel_exe-y := ../nandsim_manual.o \\\n     $(BOARDDIR)/MMURequestProxy.o \\\n     $(BOARDDIR)/MMUIndicationWrapper.o \\\n     $(BOARDDIR)/MemServerRequestProxy.o \\\n     $(BOARDDIR)/MemServerIndicationWrapper.o \\\n     $(BOARDDIR)/NandCfgIndicationWrapper.o \\\n     $(BOARDDIR)/NandCfgRequestProxy.o \\\n     $(CPPDIR)/portal.o \\\n     $(CPPDIR)/dmaManager.o \\\n     $(CPPDIR)/kernel_module.o\n\nifeq ($(BOARD),bluesim)\nkernel_exe-y += $(CPPDIR)/sock_utils.o\nendif\n\nobj-m := kernel_exe.o\n\nccflags-y := -I$(src)/.. -I$(DRIVERDIR)/pcieportal -I$(DRIVERDIR)/portalmem -I$(src)/$(CPPDIR) -I$(src)/$(BOARDDIR) $(HARDWARE_FLAGS) -DBOARD_$(BOARD)\n\ndefault:\n\t$(MAKE) -C $(KROOT) M=$(PWD) modules\n\nclean:\n\t$(MAKE) -C $(KROOT) M=$(PWD) clean\n\trm -f $(kernel_exe-y) a.out bsim_relay\n\nCURRENTMOD=$(shell lsmod | grep kernel_exe)\n\nrun: host\nifeq ($(BOARD),bluesim)\n\t@echo running bsim\n\t../bluesim/bin/bsim& echo $$! >tmp.bluesim.makefile.pid\nelse\n\tfpgajtag ../$(BOARD)/bin/mkTop.bin.gz\nendif\nifneq (\"$(CURRENTMOD)\", \"\")\n\tsudo rmmod kernel_exe\n\t#sudo rmmod bdbm_drv\nendif\n\tsudo insmod kernel_exe.ko\n\t#sudo insmod bdbm_drv.ko\nifeq ($(BOARD),bluesim)\n\t./bsim_relay\n\tkill `cat tmp.bluesim.makefile.pid`\n\t#killall bluetcl\nendif\n\tsudo rmmod kernel_exe\n\t#sudo rmmod bdbm_drv\n\tdmesg | tail -30\n\t@rm -f tmp.bluesim.makefile.pid\n\n#\n# Target for making userspace bsim_relay program\nCPPDIR=../../../cpp\nHOSTSOURCES=$(CPPDIR)/bsim_relay.c $(CPPDIR)/sock_utils.c\n\nhost: $(HOSTSOURCES)\nifeq ($(BOARD),bluesim)\n\tgcc -o bsim_relay -g -I$(CPPDIR) $(HOSTSOURCES) -lpthread\nendif\n"
  },
  {
    "path": "tests/algo1_nandsim_manual/nandsim_manual.c",
    "content": "/* Copyright (c) 2014 Sungjin Lee, MIT\n *\n * Permission is hereby granted, free of charge, to any person obtaining a\n * copy of this software and associated documentation files (the \"Software\"),\n * to deal in the Software without restriction, including without limitation\n * the rights to use, copy, modify, merge, publish, distribute, sublicense,\n * and/or sell copies of the Software, and to permit persons to whom the\n * Software is furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n * DEALINGS IN THE SOFTWARE.\n */\n\n#ifdef __KERNEL__\n#include <linux/delay.h>  // msleep\n#include <linux/kthread.h>\n#else\n#include <string.h>\n#include <sys/mman.h>\n#include <pthread.h>\n#include <fcntl.h>\n#include <sys/select.h>\n#endif\n\n#include \"dmaManager.h\"\n#include \"sock_utils.h\"  // bsim_poll_interrupt()\n#include \"GeneratedTypes.h\" \n\n#include \"drivers/portalmem/portalmem.h\"\n\nstatic int trace_memory;// = 1;\n\n#define MAX_INDARRAY 4\nstatic PortalInternal intarr[MAX_INDARRAY];\n\nstatic sem_t test_sem;\nstatic int burstLen = 16;\n#ifndef SIMULATION\n#define numWords 0x1240000/4 // make sure to allocate at least one entry of each size\n#else\n#define numWords 0x1240/4\n#endif\nstatic long back_sz  = numWords*sizeof(unsigned int);\nstatic DmaManagerPrivate priv;\n\nint NandCfgIndicationWrappereraseDone_cb (  struct PortalInternal *p, const uint32_t tag )\n{\n  PORTAL_PRINTF( \"cb: NandSim_eraseDone(tag = %x)\\n\", tag);\n  sem_post(&test_sem);\n}\n\nint NandCfgIndicationWrapperwriteDone_cb (  struct PortalInternal *p, const uint32_t tag )\n{\n  PORTAL_PRINTF( \"cb: NandSim_writeDone(tag = %x)\\n\", tag);\n  sem_post(&test_sem);\n}\n\nint NandCfgIndicationWrapperreadDone_cb (  struct PortalInternal *p, const uint32_t tag )\n{\n  PORTAL_PRINTF( \"cb: NandSim_readDone(tag = %x)\\n\", tag);\n  sem_post(&test_sem);\n}\n\nint NandCfgIndicationWrapperconfigureNandDone_cb (  struct PortalInternal *p )\n{\n  PORTAL_PRINTF( \"cb: NandSim_NandDone\\n\");\n  sem_post(&test_sem);\n}\n\nint MMUIndicationWrapperconfigResp_cb (  struct PortalInternal *p, const uint32_t pointer )\n{\n  PORTAL_PRINTF(\"cb: MMUIndicationWrapperconfigResp_cb(physAddr=%x)\\n\", pointer);\n  sem_post(&priv.confSem);\n}\n\nint MMUIndicationWrapperidResponse_cb (  struct PortalInternal *p, const uint32_t sglId ) \n{\n  PORTAL_PRINTF(\"cb: MMUIndicationWrapperidResponse_cb\\n\");\n  priv.sglId = sglId;\n  sem_post(&priv.sglIdSem);\n}\n\nint MMUIndicationWrappererror_cb (  struct PortalInternal *p, const uint32_t code, const uint32_t pointer, const uint64_t offset, const uint64_t extra ) \n{\n  PORTAL_PRINTF(\"cb: MMUIndicationWrappererror_cb\\n\");\n}\n\nvoid manual_event(void)\n{\n    int i;\n    for (i = 0; i < MAX_INDARRAY; i++)\n      event_hardware(&intarr[i]);\n}\n\n#ifdef __KERNEL__\nDECLARE_COMPLETION(worker_completion);\n#endif\nstatic void *pthread_worker(void *p)\n{\n    void *rc = NULL;\n    while (1) {\n#if defined(BSIM) && !defined(__KERNEL__)\n        if (bsim_poll_interrupt())\n#endif\n        manual_event();\n#ifdef __KERNEL__\n        msleep(10);\n        if (kthread_should_stop()) {\n\t\t    PORTAL_PRINTF (\"pthread_worker ends\\n\");\n            break;\n\t\t}\n#else ///////////////////////// userspace version\n        struct timeval timeout;\n        timeout.tv_sec = 0;\n        timeout.tv_usec = 10000;\n        select(0, NULL, NULL, NULL, &timeout);\n#endif\n    }\n#ifdef __KERNEL__\n    complete(&worker_completion);\n#endif\n    return rc;\n}\nNandCfgIndicationCb NandCfgIndication_cbTable = {\n    NandCfgIndicationWrappereraseDone_cb,\n    NandCfgIndicationWrapperwriteDone_cb,\n    NandCfgIndicationWrapperreadDone_cb,\n    NandCfgIndicationWrapperconfigureNandDone_cb,\n};\nMMUIndicationCb MMUIndication_cbTable = {\n    MMUIndicationWrapperconfigResp_cb,\n    MMUIndicationWrapperidResponse_cb,\n    MMUIndicationWrappererror_cb,\n};\nint main(int argc, const char **argv)\n{\n  int srcAlloc;\n  int backAlloc;\n  unsigned int *srcBuffer;\n  unsigned int ref_srcAlloc;\n  unsigned int *backBuffer;\n  unsigned int ref_backAlloc;\n  int rc = 0, i;\n  pthread_t tid = 0;\n\n\n  init_portal_internal(&intarr[2], IfcNames_BackingStoreMMURequest, NULL, NULL, NULL, NULL, MMURequest_reqinfo);         // fpga3\n  init_portal_internal(&intarr[0], IfcNames_BackingStoreMMUIndication, MMUIndication_handleMessage, &MMUIndication_cbTable, NULL, NULL, MMUIndication_reqinfo);     // fpga1\n  init_portal_internal(&intarr[3], IfcNames_NandCfgRequest, NULL, NULL, NULL, NULL, NandCfgRequest_reqinfo);    // fpga4\n  init_portal_internal(&intarr[1], IfcNames_NandCfgIndication, NandCfgIndication_handleMessage, &NandCfgIndication_cbTable, NULL, NULL, NandCfgIndication_reqinfo); // fpga2\n\n  DmaManager_init(&priv, &intarr[2]);\n  sem_init(&test_sem, 0, 0);\n\n  PORTAL_PRINTF( \"Main: creating exec thread - %lu\\n\", sizeof (unsigned int) );\n  if(pthread_create(&tid, NULL, pthread_worker, NULL)){\n   PORTAL_PRINTF( \"error creating exec thread\\n\");\n   return -1;\n  }\n\n  backAlloc = portalAlloc (back_sz, 0);\n  PORTAL_PRINTF(\"backAlloc=%d\\n\", backAlloc);\n\n  ref_backAlloc = DmaManager_reference(&priv, backAlloc);\n  PORTAL_PRINTF(\"ref_backAlloc=%d\\n\", ref_backAlloc);\n\n  backBuffer = (unsigned int*)portalMmap(backAlloc, back_sz); \n  portalCacheFlush(backAlloc, backBuffer, back_sz, 1);\n\n  NandCfgRequest_configureNand (&intarr[3], ref_backAlloc, back_sz);\n  PORTAL_PRINTF(\"Main::configure NAND fd=%d ref=%d\\n\", backAlloc, ref_backAlloc);\n  sem_wait(&test_sem);\n\n  srcAlloc = portalAlloc(back_sz, 0);\n  srcBuffer = (unsigned int *)portalMmap(srcAlloc, back_sz);\n  ref_srcAlloc = DmaManager_reference(&priv, srcAlloc);\n\n  PORTAL_PRINTF(\"about to start write\\n\");\n  //write data to \"flash\" memory\n  strcpy((char*)srcBuffer, \"acabcabacababacababababababcacabcabacababacabababc\\n012345678912\");\n  NandCfgRequest_startWrite(&intarr[3], ref_srcAlloc, 0, 0, 1024, 8);\n  sem_wait(&test_sem);\n\n  // at this point, if we were synchronizing with the algo_exe, we\n  // could tell it that it was OK to start searching\n  PORTAL_PRINTF (\"initialization of data in \\\"flash\\\" memory complete\\n\");\n\n#ifdef __KERNEL__\n  if (tid && !kthread_stop (tid)) {\n    PORTAL_PRINTF (\"kthread stops\\n\");\n  }\n  wait_for_completion(&worker_completion);\n  msleep(20000);\n#else\n  sleep(20);\n#endif\n\n\n#ifdef __KERNEL__\n  portalmem_dmabuffer_destroy(backAlloc);\n  portalmem_dmabuffer_destroy(srcAlloc);\n#endif\n\n  PORTAL_PRINTF (\"Main: ends\\n\");\n  return 0;\n}\n"
  },
  {
    "path": "tests/avalon_mm/AvalonBfmWrapper.bsv",
    "content": "\n/*\n   /home/hwang/dev/connectal/generated/scripts/importbvi.py\n   -I\n   AvalonMM\n   -P\n   AvalonMM\n   -c\n   clk_clk\n   -r\n   reset_reset_n\n   -f\n   master_0\n   -f\n   slave_0\n   -o\n   AvalonBfmWrapper.bsv\n   avlm_avls_1x1.v\n*/\n\nimport Clocks::*;\nimport DefaultValue::*;\nimport XilinxCells::*;\nimport GetPut::*;\nimport AvalonBits::*;\n\n(* always_ready, always_enabled *)\ninterface AvalonBfmWrapper#(numeric type addrWidth, numeric type dataWidth);\n    //interface AvalonMMasterBits#(addrWidth, dataWidth) master_0;\n    interface AvalonMSlaveBits#(addrWidth, dataWidth)  slave_0;\nendinterface\nimport \"BVI\" avlm_avls_1x1 =\nmodule mkAvalonBfmWrapper(AvalonBfmWrapper#(addrWidth, dataWidth));\n    default_clock clk();\n    default_reset rst();\n        input_clock (clk_clk) <- exposeCurrentClock;\n        input_reset (reset_reset_n) <- exposeCurrentReset;\n//    interface AvalonMMasterBits     master_0;\n//        method master_0_m0_address address();\n//        method master_0_m0_burstcount burstcount();\n//        method master_0_m0_byteenable byteenable();\n//        method master_0_m0_read read();\n//        method readdata(master_0_m0_readdata) enable((*inhigh*) EN_master_0_m0_readdata);\n//        method readdatavalid(master_0_m0_readdatavalid) enable((*inhigh*) EN_master_0_m0_readdatavalid);\n//        method waitrequest(master_0_m0_waitrequest) enable((*inhigh*) EN_master_0_m0_waitrequest);\n//        method master_0_m0_write write();\n//        method master_0_m0_writedata writedata();\n//    endinterface\n    interface AvalonMSlaveBits     slave_0;\n        method address(slave_0_s0_address) enable((*inhigh*) EN_slave_0_s0_address);\n        method burstcount(slave_0_s0_burstcount) enable((*inhigh*) EN_slave_0_s0_burstcount);\n        method byteenable(slave_0_s0_byteenable) enable((*inhigh*) EN_slave_0_s0_byteenable);\n        method read(slave_0_s0_read) enable((*inhigh*) EN_slave_0_s0_read);\n        method slave_0_s0_readdata readdata();\n        method slave_0_s0_readdatavalid readdatavalid();\n        method slave_0_s0_waitrequest waitrequest();\n        method write(slave_0_s0_write) enable((*inhigh*) EN_slave_0_s0_write);\n        method writedata(slave_0_s0_writedata) enable((*inhigh*) EN_slave_0_s0_writedata);\n    endinterface\n    //schedule (master_0.address, master_0.burstcount, master_0.byteenable, master_0.read, master_0.readdata, master_0.readdatavalid, master_0.waitrequest, master_0.write, master_0.writedata, slave_0.address, slave_0.burstcount, slave_0.byteenable, slave_0.read, slave_0.readdata, slave_0.readdatavalid, slave_0.waitrequest, slave_0.write, slave_0.writedata) CF (master_0.address, master_0.burstcount, master_0.byteenable, master_0.read, master_0.readdata, master_0.readdatavalid, master_0.waitrequest, master_0.write, master_0.writedata, slave_0.address, slave_0.burstcount, slave_0.byteenable, slave_0.read, slave_0.readdata, slave_0.readdatavalid, slave_0.waitrequest, slave_0.write, slave_0.writedata);\n    schedule (slave_0.address, slave_0.burstcount, slave_0.byteenable, slave_0.read, slave_0.readdata, slave_0.readdatavalid, slave_0.waitrequest, slave_0.write, slave_0.writedata) CF (slave_0.address, slave_0.burstcount, slave_0.byteenable, slave_0.read, slave_0.readdata, slave_0.readdatavalid, slave_0.waitrequest, slave_0.write, slave_0.writedata);\nendmodule\n"
  },
  {
    "path": "tests/avalon_mm/Echo.bsv",
    "content": "// Copyright (c) 2013 Nokia, Inc.\n// Copyright (c) 2013 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\nimport Connectable::*;\nimport FIFO::*;\nimport GetPut::*;\nimport Vector::*;\nimport TestProgram::*;\nimport AvalonBfmWrapper::*;\nimport AvalonMasterSlave::*;\nimport AvalonBits::*;\nimport AvalonDma::*;\nimport AvalonGather::*;\nimport ConnectalMemTypes::*;\nimport MemServerIndication::*;\nimport MMUIndication::*;\n\ninterface EchoIndication;\n   method Action heard(Bit#(32) v);\n   method Action heard2(Bit#(16) a, Bit#(16) b);\nendinterface\n\ninterface EchoRequest;\n   method Action writeData(Bit#(16) addr, Bit#(64) data);\n   method Action readData(Bit#(16) addr, Bit#(64) data);\nendinterface\n\ninterface Echo;\n   interface EchoRequest request;\nendinterface\n\ntypedef 12 AddressWidth;\ntypedef 32 DataWidth;\ntypedef TDiv#(DataWidth, 32) WordsPerBeat;\n\nmodule mkEcho#(EchoIndication indication)(Echo);\n   FIFO#(Bit#(32)) delay <- mkSizedFIFO(8);\n\n   // read client interface\n   FIFO#(PhysMemRequest#(AddressWidth, DataWidth)) readReqFifo <- mkSizedFIFO(4);\n   FIFO#(MemData#(DataWidth)) readDataFifo <- mkSizedFIFO(32);\n   PhysMemReadClient#(AddressWidth, DataWidth) readClient = (interface PhysMemReadClient;\n      interface Get readReq = toGet(readReqFifo);\n      interface Put readData = toPut(readDataFifo);\n   endinterface);\n\n   // write client interface\n   FIFO#(PhysMemRequest#(AddressWidth, DataWidth)) writeReqFifo <- mkSizedFIFO(4);\n   FIFO#(MemData#(DataWidth)) writeDataFifo <- mkSizedFIFO(32);\n   FIFO#(Bit#(MemTagSize)) writeDoneFifo <- mkSizedFIFO(4);\n   PhysMemWriteClient#(AddressWidth, DataWidth) writeClient = (interface PhysMemWriteClient;\n      interface Get writeReq = toGet(writeReqFifo);\n      interface Get writeData = toGet(writeDataFifo);\n      interface Put writeDone = toPut(writeDoneFifo);\n   endinterface);\n\n   // PhysMemMaster interface\n   PhysMemMaster#(AddressWidth, DataWidth) memMaster = (interface PhysMemMaster;\n      interface read_client = readClient;\n      interface write_client = writeClient;\n   endinterface);\n\n   Empty test_program <- mkTestProgram();\n   AvalonBfmWrapper#(AddressWidth, DataWidth) dut <- mkAvalonBfmWrapper();\n   AvalonMSlave#(AddressWidth, DataWidth) slaveGather <- mkAvalonMSlaveGather(dut.slave_0);\n   AvalonMMaster#(AddressWidth, DataWidth) master <- mkAvalonDmaMaster(memMaster);\n   mkConnection(master, slaveGather);\n\n   interface EchoRequest request;\n      method Action writeData(Bit#(16) addr, Bit#(64) data);\n         writeReqFifo.enq(PhysMemRequest{ addr: truncate(addr),\n                                          burstLen: 4,\n                                          tag: 0});\n         function Bit#(8) plusi(Integer i); return fromInteger(i); endfunction\n         Vector#(TMul#(4, WordsPerBeat), Bit#(8)) v = genWith(plusi);\n         writeDataFifo.enq(MemData {data: pack(v), tag: 0, last: True});\n      endmethod\n      method Action readData(Bit#(16) addr, Bit#(64) data);\n         readReqFifo.enq(PhysMemRequest{addr: truncate(addr),\n                                        burstLen: 16,\n                                        tag: 0});\n      endmethod\n   endinterface\nendmodule\n"
  },
  {
    "path": "tests/avalon_mm/Makefile",
    "content": "CONNECTALDIR?=../..\nS2H_INTERFACES = EchoRequest:Echo.request\nH2S_INTERFACES = Echo:EchoIndication\n\nBSVFILES = Echo.bsv\nCPPFILES= testecho.cpp\n\nCONNECTALFLAGS += --verilog verilog\nCONNECTALFLAGS += --systemverilog $(IPDIR)/$(BOARD)/synthesis/avlm_avls_1x1\n\nprebuild::\n\tcd $(BOARD); BUILDCACHE_CACHEDIR=$(BUILDCACHE_CACHEDIR) $(BUILDCACHE) ip-generate \\\n\t    --project-directory=$(IPDIR)/$(BOARD) \\\n\t    --output-directory=$(IPDIR)/$(BOARD)/synthesis/avlm_avls_1x1 \\\n\t    --report-file=spd \\\n\t    --file-set=SIM_VERILOG \\\n\t    ../avlm_avls_1x1.qsys; \\\n\t    BUILDCACHE_CACHEDIR=$(BUILDCACHE_CACHEDIR) $(BUILDCACHE) ip-make-simscript \\\n\t    --spd=$(IPDIR)/$(BOARD)/synthesis/avlm_avls_1x1/avlm_avls_1x1.spd \\\n\t    --compile-to-work \\\n\t    --output-directory=$(IPDIR)/$(BOARD)/synthesis/avlm_avls_1x1;\n\ninclude $(CONNECTALDIR)/Makefile.connectal\n\n"
  },
  {
    "path": "tests/avalon_mm/Readme.md",
    "content": "### Tests for Avalon memory-mapped protocol \n\nAvalon memory-mapped interface is used by Altera device for access memories, such as DDR3 controller.\n\nThis test is related to the following files in connectal/bsv directory, modelled after Axi protocol:\n* AvalonBit.bsv : Raw Avalon-MM interface bits\n* AvalonGather.bsv : Converting raw bits to Get/Put interface.\n* AvalonMasterSlave.bsv : Definition for AvalonMMaster and AvalonMSlave interface\n* AvalonSplitter.bsv : Avalon has a shared bus for both read and write operation, this module is an arbiter to enable sharing, modelled after Pcie arbiter.\n* AvalonDma.bsv : Converting PhysMemRequest to AvalonMMRequest\n\nAvalonMM messages are verified using Altera's BFM verification IP, hence this test will only run in modelsim. You can run tests with the following commands.\n```\nmake build.vsim\nmake run.vsim\n```\n\nProject structure:\n* avlm_avls_1x1.qsys : Qsys project to instantiate a single Avalon-MM slave, taken from avalon verification ip simulation example.\n* AvalonBfmWrapper.bsv : Bluespec wrapper for generated avlm_avls_1x1.v\n* verilog/test_program.sv : Test case written in system verilog to handle AvalonMM requests in BFM model. Currently only handle slave.\n* TestProgram.bsv : Bluespec wrapper for test_program.sv\n* Echo.bsv, testecho.cpp : Top-level connectal project files.\n"
  },
  {
    "path": "tests/avalon_mm/TestProgram.bsv",
    "content": "import Clocks::*;\nimport DefaultValue::*;\n\nimport \"BVI\" test_program =\nmodule mkTestProgram(Empty);\n    default_clock clk();\n    default_reset rst();\nendmodule\n"
  },
  {
    "path": "tests/avalon_mm/avlm_avls_1x1.qsys",
    "content": "<?xml version=\"1.0\" encoding=\"UTF-8\"?>\n<system name=\"$${FILENAME}\">\n <component\n   name=\"$${FILENAME}\"\n   displayName=\"$${FILENAME}\"\n   version=\"1.0\"\n   description=\"\"\n   tags=\"\"\n   categories=\"System\" />\n <parameter name=\"bonusData\"><![CDATA[bonusData \n{\n   element $${FILENAME}\n   {\n   }\n   element clk\n   {\n      datum _sortIndex\n      {\n         value = \"0\";\n         type = \"int\";\n      }\n   }\n   element mm_monitor_0\n   {\n      datum _sortIndex\n      {\n         value = \"2\";\n         type = \"int\";\n      }\n   }\n   element slave_0.s0\n   {\n      datum baseAddress\n      {\n         value = \"0\";\n         type = \"String\";\n      }\n   }\n   element slave_0\n   {\n      datum _sortIndex\n      {\n         value = \"1\";\n         type = \"int\";\n      }\n   }\n}\n]]></parameter>\n <parameter name=\"clockCrossingAdapter\" value=\"HANDSHAKE\" />\n <parameter name=\"device\" value=\"5SGXEA7N3F45C2\" />\n <parameter name=\"deviceFamily\" value=\"Stratix V\" />\n <parameter name=\"deviceSpeedGrade\" value=\"2_H3\" />\n <parameter name=\"fabricMode\" value=\"QSYS\" />\n <parameter name=\"generateLegacySim\" value=\"false\" />\n <parameter name=\"generationId\" value=\"0\" />\n <parameter name=\"globalResetBus\" value=\"false\" />\n <parameter name=\"hdlLanguage\" value=\"VERILOG\" />\n <parameter name=\"hideFromIPCatalog\" value=\"false\" />\n <parameter name=\"maxAdditionalLatency\" value=\"1\" />\n <parameter name=\"projectName\" value=\"\" />\n <parameter name=\"sopcBorderPoints\" value=\"false\" />\n <parameter name=\"systemHash\" value=\"0\" />\n <parameter name=\"testBenchDutName\" value=\"\" />\n <parameter name=\"timeStamp\" value=\"0\" />\n <parameter name=\"useTestBenchNamingPattern\" value=\"false\" />\n <instanceScript></instanceScript>\n <interface name=\"clk\" internal=\"clk.clk_in\" type=\"clock\" dir=\"end\" />\n <interface name=\"reset\" internal=\"clk.clk_in_reset\" type=\"reset\" dir=\"end\" />\n <interface name=\"slave_0_s0\" internal=\"mm_monitor_0.s0\" type=\"avalon\" dir=\"end\" />\n <module\n   kind=\"altera_avalon_mm_slave_bfm\"\n   version=\"14.0\"\n   enabled=\"1\"\n   name=\"slave_0\">\n  <parameter name=\"AV_ADDRESS_W\" value=\"12\" />\n  <parameter name=\"AV_SYMBOL_W\" value=\"8\" />\n  <parameter name=\"AV_NUMSYMBOLS\" value=\"4\" />\n  <parameter name=\"AV_BURSTCOUNT_W\" value=\"4\" />\n  <parameter name=\"AV_READRESPONSE_W\" value=\"8\" />\n  <parameter name=\"AV_WRITERESPONSE_W\" value=\"8\" />\n  <parameter name=\"USE_READ\" value=\"1\" />\n  <parameter name=\"USE_WRITE\" value=\"1\" />\n  <parameter name=\"USE_ADDRESS\" value=\"1\" />\n  <parameter name=\"USE_BYTE_ENABLE\" value=\"1\" />\n  <parameter name=\"USE_BURSTCOUNT\" value=\"1\" />\n  <parameter name=\"USE_READ_DATA\" value=\"1\" />\n  <parameter name=\"USE_READ_DATA_VALID\" value=\"1\" />\n  <parameter name=\"USE_WRITE_DATA\" value=\"1\" />\n  <parameter name=\"USE_BEGIN_TRANSFER\" value=\"0\" />\n  <parameter name=\"USE_BEGIN_BURST_TRANSFER\" value=\"0\" />\n  <parameter name=\"USE_ARBITERLOCK\" value=\"0\" />\n  <parameter name=\"USE_LOCK\" value=\"0\" />\n  <parameter name=\"USE_DEBUGACCESS\" value=\"0\" />\n  <parameter name=\"USE_WAIT_REQUEST\" value=\"1\" />\n  <parameter name=\"USE_TRANSACTIONID\" value=\"0\" />\n  <parameter name=\"USE_WRITERESPONSE\" value=\"0\" />\n  <parameter name=\"USE_READRESPONSE\" value=\"0\" />\n  <parameter name=\"USE_CLKEN\" value=\"0\" />\n  <parameter name=\"ASSERT_HIGH_RESET\" value=\"1\" />\n  <parameter name=\"ASSERT_HIGH_WAITREQUEST\" value=\"1\" />\n  <parameter name=\"ASSERT_HIGH_READ\" value=\"1\" />\n  <parameter name=\"ASSERT_HIGH_WRITE\" value=\"1\" />\n  <parameter name=\"ASSERT_HIGH_BYTEENABLE\" value=\"1\" />\n  <parameter name=\"ASSERT_HIGH_READDATAVALID\" value=\"1\" />\n  <parameter name=\"ASSERT_HIGH_ARBITERLOCK\" value=\"1\" />\n  <parameter name=\"ASSERT_HIGH_LOCK\" value=\"1\" />\n  <parameter name=\"AV_BURST_LINEWRAP\" value=\"0\" />\n  <parameter name=\"AV_BURST_BNDR_ONLY\" value=\"0\" />\n  <parameter name=\"AV_MAX_PENDING_READS\" value=\"8\" />\n  <parameter name=\"AV_MAX_PENDING_WRITES\" value=\"0\" />\n  <parameter name=\"AV_FIX_READ_LATENCY\" value=\"0\" />\n  <parameter name=\"AV_READ_WAIT_TIME\" value=\"1\" />\n  <parameter name=\"AV_WRITE_WAIT_TIME\" value=\"0\" />\n  <parameter name=\"REGISTER_WAITREQUEST\" value=\"0\" />\n  <parameter name=\"AV_REGISTERINCOMINGSIGNALS\" value=\"0\" />\n  <parameter name=\"ADDRESS_UNITS\" value=\"SYMBOLS\" />\n  <parameter name=\"VHDL_ID\" value=\"0\" />\n </module>\n <module kind=\"clock_source\" version=\"14.0\" enabled=\"1\" name=\"clk\">\n  <parameter name=\"clockFrequency\" value=\"50000000\" />\n  <parameter name=\"clockFrequencyKnown\" value=\"true\" />\n  <parameter name=\"inputClockFrequency\" value=\"0\" />\n  <parameter name=\"resetSynchronousEdges\" value=\"DEASSERT\" />\n </module>\n <module\n   kind=\"altera_avalon_mm_monitor\"\n   version=\"14.0\"\n   enabled=\"1\"\n   name=\"mm_monitor_0\">\n  <parameter name=\"AV_ADDRESS_W\" value=\"12\" />\n  <parameter name=\"AV_SYMBOL_W\" value=\"8\" />\n  <parameter name=\"AV_NUMSYMBOLS\" value=\"4\" />\n  <parameter name=\"AV_BURSTCOUNT_W\" value=\"4\" />\n  <parameter name=\"USE_READ\" value=\"1\" />\n  <parameter name=\"USE_WRITE\" value=\"1\" />\n  <parameter name=\"USE_ADDRESS\" value=\"1\" />\n  <parameter name=\"USE_BYTE_ENABLE\" value=\"1\" />\n  <parameter name=\"USE_BURSTCOUNT\" value=\"1\" />\n  <parameter name=\"USE_READ_DATA\" value=\"1\" />\n  <parameter name=\"USE_READ_DATA_VALID\" value=\"1\" />\n  <parameter name=\"USE_WRITE_DATA\" value=\"1\" />\n  <parameter name=\"USE_BEGIN_TRANSFER\" value=\"0\" />\n  <parameter name=\"USE_BEGIN_BURST_TRANSFER\" value=\"0\" />\n  <parameter name=\"USE_WAIT_REQUEST\" value=\"1\" />\n  <parameter name=\"AV_CONSTANT_BURST_BEHAVIOR\" value=\"1\" />\n  <parameter name=\"AV_BURST_LINEWRAP\" value=\"0\" />\n  <parameter name=\"AV_BURST_BNDR_ONLY\" value=\"0\" />\n  <parameter name=\"AV_ALWAYS_BURST_MAX_BURST\" value=\"0\" />\n  <parameter name=\"AV_READ_TIMEOUT\" value=\"100\" />\n  <parameter name=\"AV_WRITE_TIMEOUT\" value=\"100\" />\n  <parameter name=\"AV_WAITREQUEST_TIMEOUT\" value=\"1024\" />\n  <parameter name=\"AV_MAX_PENDING_READS\" value=\"1\" />\n  <parameter name=\"AV_MAX_PENDING_WRITES\" value=\"0\" />\n  <parameter name=\"AV_FIX_READ_LATENCY\" value=\"0\" />\n  <parameter name=\"AV_MAX_READ_LATENCY\" value=\"100\" />\n  <parameter name=\"AV_MAX_WAITREQUESTED_READ\" value=\"100\" />\n  <parameter name=\"AV_MAX_WAITREQUESTED_WRITE\" value=\"100\" />\n  <parameter name=\"MASTER_ADDRESS_TYPE\" value=\"SYMBOLS\" />\n  <parameter name=\"SLAVE_ADDRESS_TYPE\" value=\"WORDS\" />\n  <parameter name=\"VHDL_ID\" value=\"0\" />\n  <parameter name=\"AV_READRESPONSE_W\" value=\"8\" />\n  <parameter name=\"AV_WRITERESPONSE_W\" value=\"8\" />\n  <parameter name=\"USE_ARBITERLOCK\" value=\"0\" />\n  <parameter name=\"USE_LOCK\" value=\"0\" />\n  <parameter name=\"USE_DEBUGACCESS\" value=\"0\" />\n  <parameter name=\"USE_TRANSACTIONID\" value=\"0\" />\n  <parameter name=\"USE_WRITERESPONSE\" value=\"0\" />\n  <parameter name=\"USE_READRESPONSE\" value=\"0\" />\n  <parameter name=\"USE_CLKEN\" value=\"0\" />\n  <parameter name=\"AV_MAX_CONTINUOUS_READ\" value=\"5\" />\n  <parameter name=\"AV_MAX_CONTINUOUS_WRITE\" value=\"5\" />\n  <parameter name=\"AV_MAX_CONTINUOUS_WAITREQUEST\" value=\"5\" />\n  <parameter name=\"AV_MAX_CONTINUOUS_READDATAVALID\" value=\"5\" />\n  <parameter name=\"AV_READ_WAIT_TIME\" value=\"1\" />\n  <parameter name=\"AV_WRITE_WAIT_TIME\" value=\"0\" />\n  <parameter name=\"REGISTER_WAITREQUEST\" value=\"0\" />\n  <parameter name=\"AV_REGISTERINCOMINGSIGNALS\" value=\"0\" />\n </module>\n <connection kind=\"clock\" version=\"14.0\" start=\"clk.clk\" end=\"slave_0.clk\" />\n <connection\n   kind=\"reset\"\n   version=\"14.0\"\n   start=\"clk.clk_reset\"\n   end=\"slave_0.clk_reset\" />\n <connection kind=\"avalon\" version=\"14.0\" start=\"mm_monitor_0.m0\" end=\"slave_0.s0\">\n  <parameter name=\"arbitrationPriority\" value=\"1\" />\n  <parameter name=\"baseAddress\" value=\"0x0000\" />\n  <parameter name=\"defaultConnection\" value=\"false\" />\n </connection>\n <connection kind=\"clock\" version=\"14.0\" start=\"clk.clk\" end=\"mm_monitor_0.clk\" />\n <connection\n   kind=\"reset\"\n   version=\"14.0\"\n   start=\"clk.clk_reset\"\n   end=\"mm_monitor_0.clk_reset\" />\n <interconnectRequirement for=\"$system\" name=\"qsys_mm.clockCrossingAdapter\" value=\"HANDSHAKE\" />\n <interconnectRequirement for=\"$system\" name=\"qsys_mm.maxAdditionalLatency\" value=\"1\" />\n <interconnectRequirement for=\"$system\" name=\"qsys_mm.insertDefaultSlave\" value=\"FALSE\" />\n</system>\n"
  },
  {
    "path": "tests/avalon_mm/testecho.cpp",
    "content": "/* Copyright (c) 2014 Quanta Research Cambridge, Inc\n *\n * Permission is hereby granted, free of charge, to any person obtaining a\n * copy of this software and associated documentation files (the \"Software\"),\n * to deal in the Software without restriction, including without limitation\n * the rights to use, copy, modify, merge, publish, distribute, sublicense,\n * and/or sell copies of the Software, and to permit persons to whom the\n * Software is furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n * DEALINGS IN THE SOFTWARE.\n */\n\n#include <errno.h>\n#include <stdio.h>\n#include \"EchoIndication.h\"\n#include \"EchoRequest.h\"\n#include \"GeneratedTypes.h\"\n\nstatic EchoRequestProxy *echoRequestProxy = 0;\nstatic sem_t sem_heard2;\n\nclass EchoIndication : public EchoIndicationWrapper\n{\npublic:\n    virtual void heard(uint32_t v) {\n        printf(\"heard an echo: %d\\n\", v);\n    }\n    virtual void heard2(uint16_t a, uint16_t b) {\n        sem_post(&sem_heard2);\n        //printf(\"heard an echo2: %ld %ld\\n\", a, b);\n    }\n    EchoIndication(unsigned int id) : EchoIndicationWrapper(id) {}\n};\n\nstatic void call_say(int v)\n{\n    printf(\"[%s:%d] %d\\n\", __FUNCTION__, __LINE__, v);\n    echoRequestProxy->writeData(0x100, 0xdeadbeef);\n    echoRequestProxy->readData(0x140, 0xdeadbeef);\n}\n\nint main(int argc, const char **argv)\n{\n    EchoIndication echoIndication(IfcNames_EchoIndicationH2S);\n    echoRequestProxy = new EchoRequestProxy(IfcNames_EchoRequestS2H);\n\n    int v = 42;\n    printf(\"Saying %d\\n\", v);\n    call_say(v);\n    sleep(1);\n    printf(\"TEST TYPE: SEM\\n\");\n    return 0;\n}\n"
  },
  {
    "path": "tests/avalon_mm/verilog/tb.sv",
    "content": "`timescale 1ps / 1ps\r\n\r\nmodule tb ();\r\n\r\n   reg clk    = 1'b0;\r\n   reg reset  = 1'b1;\r\n   \r\n   localparam  CLOCK_PERIOD            = 100; // Clock period in ps\r\n   localparam  INITIAL_RESET_CYCLES    = 10;  // Number of cycles to reset when simulation starts\r\n   \r\n   avlm_avls_1x1 dut(\r\n      .clk_clk(clk),\r\n      .reset_reset_n(~reset)\r\n   );\r\n   \r\n   test_program  tp();\r\n   \r\n   // Clock signal generator\r\n   always begin\r\n      #(CLOCK_PERIOD / 2);\r\n      clk = ~clk;\r\n   end\r\n   \r\n   // Initial reset\r\n   initial begin\r\n      repeat(INITIAL_RESET_CYCLES) @(posedge clk);\r\n      reset = 1'b0;\r\n   end\r\n\r\nendmodule "
  },
  {
    "path": "tests/avalon_mm/verilog/test_program.v",
    "content": "//---------------------------------------------------\r\n// Macro definition\r\n//---------------------------------------------------\r\n`define NUM_MASTERS  1\r\n`define NUM_SLAVES   1\r\n\r\n`define TB        $root.xsimtop.xsimtop.top.lEcho_dut\r\n`define MASTER0   $root.xsimtop.xsimtop.top.lEcho_dut.master_0\r\n`define SLAVE0    $root.xsimtop.xsimtop.top.lEcho_dut.slave_0\r\n\r\nmodule test_program ();\r\n\r\n   import verbosity_pkg::*;\r\n   import avalon_mm_pkg::*;\r\n\r\n//---------------------------------------------------\r\n// Constants\r\n//---------------------------------------------------\r\n   localparam ADDR_W                   = 12;\r\n            \r\n   localparam SYMBOL_W                 = 8;\r\n   localparam NUM_SYMBOLS              = 4;\r\n   localparam DATA_W                   = NUM_SYMBOLS * SYMBOL_W;\r\n            \r\n   localparam BURST_W                  = 4;\r\n   localparam MAX_BURST                = 8;\r\n   \r\n   localparam SLAVE_SPAN               = 32'h1000;\r\n   \r\n   localparam MAX_COMMAND_IDLE         = 5;\r\n   localparam MAX_COMMAND_BACKPRESSURE = 2;\r\n   localparam MAX_DATA_IDLE            = 3;\r\n\r\n//---------------------------------------------------\r\n// Data structures\r\n//---------------------------------------------------\r\n   typedef logic [BURST_W-1:0]      Burstcount;\r\n\r\n   typedef enum bit\r\n   {\r\n       WRITE = 0,\r\n       READ  = 1\r\n   } Transaction;\r\n   \r\n   typedef enum bit\r\n   {\r\n       NOBURST = 0,\r\n       BURST   = 1\r\n   } Burstmode;\r\n\r\n   typedef struct \r\n   {\r\n       Transaction                  trans;\r\n       Burstcount                   burstcount;\r\n       logic [ADDR_W-1: 0]          addr;\r\n       logic [DATA_W-1:0]           data       [MAX_BURST-1:0];\r\n       logic [NUM_SYMBOLS-1:0]      byteenable [MAX_BURST-1:0];\r\n       bit [31:0]                   cmd_delay;\r\n       bit [31:0]                   data_idles [MAX_BURST-1:0];\r\n   } Command;\r\n\r\n   typedef struct\r\n   {\r\n      Burstcount                    burstcount;\r\n      logic [DATA_W-1:0]            data     [MAX_BURST-1:0];\r\n      bit [31:0]                    latency  [MAX_BURST-1:0];\r\n   } Response;\r\n\r\n//---------------------------------------------------\r\n// Command and Response Queues\r\n//---------------------------------------------------\r\n// master command queue\r\nCommand  write_command_queue_master[`NUM_MASTERS][$];\r\nCommand  read_command_queue_master[`NUM_MASTERS][$];\r\n\r\n// slave command queue\r\nCommand  write_command_queue_slave[`NUM_SLAVES][$];\r\nCommand  read_command_queue_slave[`NUM_SLAVES][$];\r\n\r\n// slave response queue\r\nResponse read_response_queue_slave[`NUM_SLAVES][$];\r\n\r\n//---------------------------------------------------\r\n// Macro Definitions\r\n//---------------------------------------------------\r\n`define MACRO_CONFIGURE_AND_PUSH_COMMAND_TO_MASTER(MASTER_ID) \\\r\n   task automatic configure_and_push_command_to_master_``MASTER_ID ( \\\r\n      Command  cmd \\\r\n   ); \\\r\n      `MASTER``MASTER_ID.set_command_address(cmd.addr); \\\r\n      `MASTER``MASTER_ID.set_command_burst_count(cmd.burstcount); \\\r\n      `MASTER``MASTER_ID.set_command_burst_size(cmd.burstcount); \\\r\n      `MASTER``MASTER_ID.set_command_init_latency(cmd.cmd_delay); \\\r\n\\\r\n      if (cmd.trans == WRITE) begin \\\r\n         `MASTER``MASTER_ID.set_command_request(REQ_WRITE); \\\r\n         for (int i = 0; i < cmd.burstcount; i++) begin \\\r\n            `MASTER``MASTER_ID.set_command_data(cmd.data[i], i); \\\r\n            `MASTER``MASTER_ID.set_command_byte_enable(cmd.byteenable[i], i); \\\r\n            `MASTER``MASTER_ID.set_command_idle(cmd.data_idles[i], i); \\\r\n         end \\\r\n      end else begin \\\r\n         `MASTER``MASTER_ID.set_command_request(REQ_READ); \\\r\n         `MASTER``MASTER_ID.set_command_idle(cmd.data_idles[0], 0); \\\r\n      end \\\r\n\\\r\n      `MASTER``MASTER_ID.push_command(); \\\r\n   endtask\r\n\r\n// Get command received by slave, verify command.\r\n// If command is read command, send out response\r\n`define MACRO_SLAVE_THREAD(SLAVE_ID) \\\r\n   always @(`SLAVE``SLAVE_ID.signal_command_received) begin \\\r\n\\\r\n      Command     actual_cmd, exp_cmd; \\\r\n      Response    rsp; \\\r\n      string      msg; \\\r\n\\\r\n      automatic int backpressure_cycles; \\\r\n\\\r\n      // set random backpressure cycles for next command \\\r\n      for (int i = 0; i < MAX_BURST; i++) begin \\\r\n         backpressure_cycles = $urandom_range(0, MAX_COMMAND_BACKPRESSURE); \\\r\n         `SLAVE``SLAVE_ID.set_interface_wait_time(backpressure_cycles, i); \\\r\n      end \\\r\n\\\r\n      actual_cmd = get_command_from_slave_``SLAVE_ID(); \\\r\n\\\r\n      // set read response \\\r\n      if (actual_cmd.trans == READ) begin \\\r\n      $sformat(msg, \"read command %x %x\", actual_cmd.burstcount, actual_cmd.addr); \\\r\n      print(VERBOSITY_INFO, msg); \\\r\n         rsp = create_response(actual_cmd.burstcount); \\\r\n         configure_and_push_response_to_slave_``SLAVE_ID(rsp); \\\r\n         read_response_queue_slave[``SLAVE_ID].push_back(rsp); \\\r\n      end \\\r\n   end\r\n   \r\n`define MACRO_GET_COMMAND_FROM_SLAVE(SLAVE_ID) \\\r\n   function automatic Command get_command_from_slave_``SLAVE_ID (); \\\r\n\\\r\n      Command cmd; \\\r\n\\\r\n      `SLAVE``SLAVE_ID.pop_command(); \\\r\n      cmd.burstcount          = `SLAVE``SLAVE_ID.get_command_burst_count(); \\\r\n      cmd.addr                = `SLAVE``SLAVE_ID.get_command_address(); \\\r\n\\\r\n      if (`SLAVE``SLAVE_ID.get_command_request() == REQ_WRITE) begin \\\r\n         cmd.trans = WRITE; \\\r\n         for(int i = 0; i < cmd.burstcount; i++) begin \\\r\n            cmd.data[i]       =`SLAVE``SLAVE_ID.get_command_data(i); \\\r\n            cmd.byteenable[i] =`SLAVE``SLAVE_ID.get_command_byte_enable(i); \\\r\n         end \\\r\n      end else begin \\\r\n         cmd.trans = READ; \\\r\n      end \\\r\n\\\r\n      return cmd; \\\r\n   endfunction\r\n   \r\n`define MACRO_PENDING_READ_CYCLES(SLAVE_ID) \\\r\n   int pending_read_cycles_slave_``SLAVE_ID = 0; \\\r\n   always @(posedge `TB.clk_clk) begin \\\r\n      if (pending_read_cycles_slave_``SLAVE_ID > 0) begin \\\r\n         pending_read_cycles_slave_``SLAVE_ID--; \\\r\n      end \\\r\n   end\r\n\r\n`define MACRO_CONFIGURE_AND_PUSH_RESPONSE_TO_SLAVE(SLAVE_ID) \\\r\ntask automatic configure_and_push_response_to_slave_``SLAVE_ID ( \\\r\n      Response rsp \\\r\n   ); \\\r\n\\\r\n      int read_response_latency; \\\r\n\\\r\n      `SLAVE``SLAVE_ID.set_response_request(REQ_READ); \\\r\n      `SLAVE``SLAVE_ID.set_response_burst_size(rsp.burstcount); \\\r\n      for (int i = 0; i < rsp.burstcount; i++) begin \\\r\n         `SLAVE``SLAVE_ID.set_response_data(rsp.data[i], i); \\\r\n\\\r\n         if (i == 0) begin \\\r\n            `SLAVE``SLAVE_ID.set_response_latency(rsp.latency[i] + pending_read_cycles_slave_``SLAVE_ID, i); \\\r\n            read_response_latency = rsp.latency[i]; \\\r\n         end else begin \\\r\n            `SLAVE``SLAVE_ID.set_response_latency(rsp.latency[i], i); \\\r\n            read_response_latency = rsp.latency[i] + read_response_latency; \\\r\n         end \\\r\n\\\r\n      end \\\r\n      `SLAVE``SLAVE_ID.push_response(); \\\r\n      pending_read_cycles_slave_``SLAVE_ID = pending_read_cycles_slave_``SLAVE_ID + read_response_latency + rsp.burstcount + 2; \\\r\n   endtask\r\n\r\n`define MACRO_MASTER_RESPONSE_THREAD(MASTER_ID) \\\r\n   // Get read response received by master and verify read response \\\r\n   always @(`MASTER``MASTER_ID.signal_read_response_complete) begin \\\r\n\\\r\n      Command  cmd; \\\r\n      Response actual_rsp, exp_rsp; \\\r\n\\\r\n      cmd = read_command_queue_master[``MASTER_ID].pop_front(); \\\r\n      actual_rsp = get_read_response_from_master_``MASTER_ID(); \\\r\n      exp_rsp = get_expected_read_response(cmd); \\\r\n      verify_response(actual_rsp, exp_rsp); \\\r\n   end \\\r\n\\\r\n   // Flush out response for write command created by master bfm \\\r\n   always @(`MASTER``MASTER_ID.signal_write_response_complete) begin \\\r\n      `MASTER``MASTER_ID.pop_response(); \\\r\n   end\r\n\r\n`define MACRO_GET_READ_RESPONSE_FROM_MASTER(MASTER_ID) \\\r\n   function automatic Response get_read_response_from_master_``MASTER_ID (); \\\r\n\\\r\n      Response rsp; \\\r\n\\\r\n      `MASTER``MASTER_ID.pop_response(); \\\r\n      rsp.burstcount    = `MASTER``MASTER_ID.get_response_burst_size(); \\\r\n      for (int i = 0; i < rsp.burstcount; i++) begin \\\r\n         rsp.data[i]    = `MASTER``MASTER_ID.get_response_data(i); \\\r\n      end \\\r\n\\\r\n      return rsp; \\\r\n   endfunction\r\n\r\n//---------------------------------------------------\r\n// Macro Instantiations\r\n//---------------------------------------------------\r\n// master 0\r\n//`MACRO_CONFIGURE_AND_PUSH_COMMAND_TO_MASTER(0)\r\n//`MACRO_MASTER_RESPONSE_THREAD(0)\r\n//`MACRO_GET_READ_RESPONSE_FROM_MASTER(0)\r\n\r\n// slave 0\r\n`MACRO_SLAVE_THREAD(0)\r\n`MACRO_GET_COMMAND_FROM_SLAVE(0)\r\n`MACRO_PENDING_READ_CYCLES(0)\r\n`MACRO_CONFIGURE_AND_PUSH_RESPONSE_TO_SLAVE(0)\r\n\r\n//---------------------------------------------------\r\n// Test status checking\r\n//---------------------------------------------------\r\nbit test_success = 1;\r\n\r\n//---------------------------------------------------\r\n// Events\r\n//---------------------------------------------------\r\nevent assert_fail;\r\n\r\n//---------------------------------------------------\r\n// Test program\r\n//---------------------------------------------------\r\n   // master test program\r\n   initial begin\r\n      set_verbosity(VERBOSITY_INFO);\r\n      $display(\"Starting master test program\");\r\n\r\n      wait (`TB.reset_reset_n == 1);\r\n      //$display(\"Master sending out non bursting write commands\");\r\n      //master_send_commands(10, WRITE, NOBURST);\r\n      //\r\n      //$display(\"Master sending out non bursting read commands\");\r\n      //master_send_commands(10, READ, NOBURST);\r\n      //\r\n      //$display(\"Master sending out burst write commands\");\r\n      //master_send_commands(10, WRITE, BURST);\r\n      //\r\n      //$display(\"Master sending out burst read commands\");\r\n      //master_send_commands(10, READ, BURST);\r\n      //\r\n      //$display(\"Master has sent out all commands\");\r\n   end\r\n   \r\n   task automatic master_send_commands (\r\n      int            num_command,\r\n      Transaction    trans,\r\n      Burstmode      burstmode\r\n   );\r\n\r\n      Command     cmd;\r\n      Response    rsp, exp_rsp;\r\n      int         master_id, slave_id;\r\n      \r\n      master_id   = 0;\r\n      slave_id    = 0;\r\n      \r\n      for (int i = 0; i < num_command; i++) begin\r\n         \r\n         cmd = create_command (\r\n            .trans(trans),\r\n            .burstmode(burstmode),\r\n            .slave_id(slave_id)\r\n         );\r\n         queue_command(cmd, master_id, slave_id);\r\n      end\r\n\r\n   endtask\r\n   \r\n   function automatic Command create_command (\r\n      Transaction    trans,\r\n      Burstmode      burstmode,\r\n      int            slave_id\r\n   );\r\n\r\n      Command cmd;\r\n      \r\n      if (burstmode == BURST) begin\r\n         cmd.burstcount             = randomize_burstcount();\r\n      end else begin\r\n         cmd.burstcount             = 1;\r\n      end\r\n      \r\n      cmd.trans                  = trans;\r\n      cmd.addr                   = generate_random_aligned_address(slave_id);\r\n      cmd.cmd_delay              = $urandom_range(0, MAX_COMMAND_IDLE);\r\n      \r\n      if (trans == WRITE) begin\r\n         for (int i = 0; i < cmd.burstcount; i++) begin\r\n            cmd.data[i]          = $random;\r\n            cmd.byteenable[i]    = {NUM_SYMBOLS{1'b1}};\r\n            cmd.data_idles[i]    = $urandom_range(0, MAX_DATA_IDLE);\r\n         end\r\n      end else begin\r\n         cmd.data_idles[0]       = $urandom_range(0, MAX_DATA_IDLE);\r\n      end\r\n      \r\n      return cmd;\r\n   endfunction\r\n   \r\n   function automatic Burstcount randomize_burstcount ();\r\n      \r\n      Burstcount burstcount;\r\n      \r\n      burstcount = $urandom_range(1, MAX_BURST);\r\n      return burstcount;\r\n   endfunction\r\n   \r\n   function automatic logic [ADDR_W-1: 0] generate_random_aligned_address (\r\n      int slave_id\r\n   );\r\n      logic [ADDR_W-1:0] base_addr, addr;\r\n      \r\n      base_addr = slave_id * SLAVE_SPAN;\r\n      addr = base_addr + ($random % SLAVE_SPAN);\r\n      \r\n      return (addr / NUM_SYMBOLS) * NUM_SYMBOLS;\r\n   endfunction\r\n   \r\n   task automatic queue_command (\r\n      Command  cmd,\r\n      int      master_id,\r\n      int      slave_id\r\n   );\r\n      \r\n      //save_command_master(cmd, master_id);\r\n      save_command_slave(cmd, slave_id);\r\n      //configure_and_push_command_to_master(cmd, master_id);\r\n   endtask\r\n   \r\n//   task automatic save_command_master( \r\n//      Command  cmd,\r\n//      int      master_id\r\n//   );\r\n//\r\n//         if (cmd.trans == WRITE) begin\r\n//            write_command_queue_master[master_id].push_back(cmd);\r\n//         end else begin\r\n//            read_command_queue_master[master_id].push_back(cmd);\r\n//         end\r\n//\r\n//   endtask\r\n   \r\n   task automatic save_command_slave(\r\n      Command  cmd,\r\n      int      slave_id\r\n   );\r\n   \r\n      if (cmd.trans == WRITE) begin\r\n         write_command_queue_slave[slave_id].push_back(cmd);\r\n      end else begin\r\n         read_command_queue_slave[slave_id].push_back(cmd);\r\n      end\r\n   \r\n   endtask\r\n   \r\n//   task automatic configure_and_push_command_to_master (\r\n//      Command  cmd,\r\n//      int      master_id\r\n//   );\r\n//      if (master_id == 0) begin\r\n//         configure_and_push_command_to_master_0(cmd);\r\n//      end\r\n//      \r\n//   endtask\r\n   \r\n   function automatic Command get_expected_command_for_slave (\r\n      Command cmd,\r\n      int     slave_id\r\n   );\r\n\r\n      Command exp_cmd;\r\n      int found = 0;\r\n\r\n      if (cmd.trans == WRITE) begin\r\n         foreach (write_command_queue_slave[slave_id, i]) begin\r\n            exp_cmd = write_command_queue_slave[slave_id][i];\r\n            if (exp_cmd.addr == cmd.addr) begin\r\n               write_command_queue_slave[slave_id].delete(i);\r\n               found = 1;\r\n               break;\r\n            end\r\n         end\r\n         if (found == 0) begin\r\n            exp_cmd = write_command_queue_slave[slave_id].pop_front();\r\n         end \r\n      end else begin\r\n         foreach (read_command_queue_slave[slave_id, i]) begin\r\n            exp_cmd = read_command_queue_slave[slave_id][i];\r\n            if (exp_cmd.addr == cmd.addr) begin\r\n               read_command_queue_slave[slave_id].delete(i);\r\n               found = 1;\r\n               break;\r\n            end\r\n         end\r\n         if (found == 0) begin\r\n            exp_cmd = read_command_queue_slave[slave_id].pop_front();\r\n         end\r\n      end\r\n\r\n      return exp_cmd;\r\n   endfunction\r\n   \r\n   task automatic verify_command (\r\n      Command actual_cmd, exp_cmd\r\n   );\r\n   \r\n      assert_equals(\"wrong address\", exp_cmd.addr, actual_cmd.addr);\r\n      assert_equals(\"wrong burstcount\", exp_cmd.burstcount, actual_cmd.burstcount);\r\n      \r\n      if (actual_cmd.trans == WRITE) begin\r\n         for (int i = 0; i < actual_cmd.burstcount; i++) begin\r\n            assert_equals(\"wrong write data\", exp_cmd.data[i], actual_cmd.data[i]);\r\n            assert_equals(\"wrong byteenable\", exp_cmd.byteenable[i], actual_cmd.byteenable[i]);\r\n         end\r\n      end\r\n   \r\n   endtask\r\n   \r\n   task automatic assert_equals(\r\n      string message,\r\n      logic [1023:0] expected_obj,\r\n      logic [1023:0] actual_obj\r\n   );\r\n      string data_comparison_msg;\r\n\r\n      begin\r\n         if (actual_obj == expected_obj) begin\r\n         // Success case.  Code it this way because in Verilog, \r\n         //   1) \"!=\" and \"==\" give 'x' if either operand contains 'x' or 'z'\r\n         //   2) 'x' evaluated as a boolean is false\r\n         end else begin\r\n            $sformat(data_comparison_msg, \"%s, expected %0x got %0x\",\r\n               message,\r\n               expected_obj,\r\n               actual_obj);\r\n            print(VERBOSITY_ERROR, data_comparison_msg);\r\n            test_success = 0;                \r\n            -> assert_fail;\r\n         end\r\n      end\r\n   endtask\r\n\r\n   function automatic Response create_response (\r\n      Burstcount burstcount\r\n   );\r\n   \r\n      Response rsp;\r\n      \r\n      rsp.burstcount       = burstcount;\r\n      for (int i = 0;i < burstcount; i++) begin\r\n         rsp.data[i]       = $random;\r\n         rsp.latency[i]    = $urandom_range(0, MAX_DATA_IDLE);\r\n      end\r\n      \r\n      return rsp;\r\n   endfunction\r\n   \r\n   function automatic Response get_expected_read_response (\r\n      Command cmd\r\n   );\r\n      \r\n      Response rsp;\r\n      int      slave_id = cmd.addr / SLAVE_SPAN;\r\n      \r\n      rsp = read_response_queue_slave[slave_id].pop_front();\r\n      \r\n      return rsp;\r\n   endfunction\r\n   \r\n   task automatic verify_response (\r\n      Response actual_rsp, exp_rsp\r\n   );\r\n      \r\n      assert_equals(\"wrong burstcount\", exp_rsp.burstcount, actual_rsp.burstcount);\r\n      for (int i = 0; i < actual_rsp.burstcount; i++) begin\r\n         assert_equals(\"wrong read data\", exp_rsp.data[i], actual_rsp.data[i]);\r\n      end\r\n      \r\n   endtask\r\n   \r\nendmodule \r\n"
  },
  {
    "path": "tests/axieth/AxiEth.bsv",
    "content": "\nimport BuildVector::*;\nimport Connectable::*;\nimport GetPut::*;\nimport FIFOF::*;\nimport BRAM::*;\nimport Probe::*;\nimport StmtFSM::*;\nimport TriState::*;\nimport Vector::*;\n\nimport ConnectalXilinxCells::*;\nimport ConnectalConfig::*;\nimport CtrlMux::*;\nimport HostInterface::*;\nimport ConnectalMemTypes::*;\nimport AxiBits::*;\n\nimport AxiIntcBvi::*;\nimport AxiEthBvi::*;\nimport AxiDmaBvi::*;\nimport EthPins::*;\n\ninterface AxiEthTestRequest;\n   method Action reset();\n   method Action setupDma(Bit#(32) memref);\n   method Action status();\n   method Action read(Bit#(32) addr);\n   method Action write(Bit#(32) addr, Bit#(32) value);\nendinterface\n\ninterface AxiEthTestIndication;\n   method Action irqChanged(Bit#(1) newIrq, Bit#(4) intrSources);\n   method Action readDone(Bit#(32) value); \n   method Action writeDone(); \n   method Action resetDone();\n   method Action status(Bit#(1) mmcm_locked, Bit#(1) irq, Bit#(4) intrSources);\nendinterface\n\ninterface AxiEth;\n   interface AxiEthTestRequest request;\n   interface Vector#(2, MemReadClient#(DataBusWidth)) dmaReadClient;\n   interface Vector#(2, MemWriteClient#(DataBusWidth)) dmaWriteClient;\n   interface AxiEthPins pins;\nendinterface\n\nmodule mkAxiEth#(HostInterface host, AxiEthTestIndication ind)(AxiEth);\n\n   let clock <- exposeCurrentClock();\n   let reset <- exposeCurrentReset();\n\n   let axiIntcBvi <- mkAxiIntcBvi(clock, reset);\n   let axiDmaBvi <- mkAxiDmaBvi(clock,clock,clock,clock,reset);\n   let axiEthBvi <- mkAxiEthBvi(host.tsys_clk_200mhz_buf,\n\t\t\t\tclock, reset, clock,\n\t\t\t\treset, reset, reset, reset);\n\n   Reg#(Bit#(32)) objId <- mkReg(0);\n\n   let irqLevel <- mkReg(0);\n   let intrLevel <- mkReg(0);\n   Bit#(4) intr = {\n      axiDmaBvi.s2mm.introut(),\n      axiDmaBvi.mm2s.introut(),\n      axiEthBvi.mac.irq(),\n      axiEthBvi.interrupt()\n      };\n\n   rule rl_intr;\n      axiIntcBvi.intr(intr);\n   endrule\n\n   rule rl_intr_indication;\n      let irq = axiIntcBvi.irq;\n      irqLevel <= irq;\n      intrLevel <= intr;\n\n      if (irq != irqLevel || intr != intrLevel) begin\n\t ind.irqChanged(irq, intr);\n\t $display(\"irq changed irq=%h intr sources %h\", irq, intr);\n      end\n   endrule\n   Reg#(Bit#(32)) cycles <- mkReg(0);\n   Reg#(Bool)     mmcm_lock <- mkReg(False);\n   rule rl_cycles;\n      cycles <= cycles+1;\n   endrule\n   rule rl_mmcm_lock if (!mmcm_lock);\n      if (axiEthBvi.mmcm.locked_out() == 1) begin\n\t mmcm_lock <= True;\n\t $display(\"%d mmcm locked\", cycles);\n      end\n   endrule\n\n   FIFOF#(BRAMRequest#(Bit#(32),Bit#(32))) reqFifo <- mkFIFOF();\n   FIFOF#(Bit#(32))                       dataFifo <- mkFIFOF();\n   // packet data and status from the ethernet\n   mkConnection(axiEthBvi.m_axis_rxd, axiDmaBvi.s_axis_s2mm);\n   mkConnection(axiEthBvi.m_axis_rxs, axiDmaBvi.s_axis_s2mm_sts);\n\n   // packet data and control to the ethernet\n   mkConnection(axiDmaBvi.m_axis_mm2s,       axiEthBvi.s_axis_txd);\n   mkConnection(axiDmaBvi.m_axis_mm2s_cntrl, axiEthBvi.s_axis_txc);\n\n   Axi4MasterBits#(32,32,MemTagSize,Empty) m_axi_mm2s = toAxi4MasterBits(axiDmaBvi.m_axi_mm2s);\n   Axi4MasterBits#(32,32,MemTagSize,Empty) m_axi_s2mm = toAxi4MasterBits(axiDmaBvi.m_axi_s2mm);\n   Axi4MasterBits#(32,32,MemTagSize,Empty) m_axi_sg = toAxi4MasterBits(axiDmaBvi.m_axi_sg);\n\n   Axi4SlaveLiteBits#(9,32) axiIntcSlaveLite = toAxi4SlaveBits(axiIntcBvi.s_axi);\n   PhysMemSlave#(18,32) axiIntcMemSlave <- mkPhysMemSlave(axiIntcSlaveLite);\n   PhysMemSlave#(18,32) axiDmaMemSlave <- mkPhysMemSlave(axiDmaBvi.s_axi_lite);\n   Axi4SlaveLiteBits#(18,32) axiEthSlaveLite = toAxi4SlaveBits(axiEthBvi.s_axi);\n   PhysMemSlave#(18,32) axiEthMemSlave <- mkPhysMemSlave(axiEthSlaveLite);\n   PhysMemSlave#(20,32) memSlaveMux    <- mkPhysMemSlaveMux(vec(axiIntcMemSlave, axiDmaMemSlave, axiEthMemSlave));\n\n   FIFOF#(Bit#(32)) dfifo <- mkFIFOF();\n\n   rule rl_axieth;\n      axiEthBvi.signal.detect(1); // drive to 1 if not using optical transceiver, else use signal from transceiver\n   endrule\n\n   rule rl_rdata;\n      let rdata <- memSlaveMux.read_server.readData.get();\n      ind.readDone(rdata.data);\n   endrule\n\n   rule rl_wdata;\n      let wdata <- toGet(dfifo).get();\n       memSlaveMux.write_server.writeData.put(MemData {data: wdata, tag: 0});\n   endrule\n\n   rule rl_writeDone;\n      let tag <- memSlaveMux.write_server.writeDone.get();\n      ind.writeDone();\n   endrule\n\n   interface AxiEthTestRequest request;\n      method Action reset();\n      endmethod\n      method Action setupDma(Bit#(32) memref);\n\t objId <= memref;\n      endmethod\n      method Action read(Bit#(32) addr);\n\t memSlaveMux.read_server.readReq.put(PhysMemRequest { addr: truncate(addr), burstLen: 4, tag: 0 });\n      endmethod\n      method Action write(Bit#(32) addr, Bit#(32) value);\n\t memSlaveMux.write_server.writeReq.put(PhysMemRequest { addr: truncate(addr), burstLen: 4, tag: 0 });\n\t dfifo.enq(value);\n      endmethod\n      method Action status();\n\t ind.status(axiEthBvi.mmcm.locked_out(), axiIntcBvi.irq, intr);\n      endmethod\n   endinterface\n   interface AxiEthPins pins;\n      interface EthPins eth;\n\t interface AxiethbviMgt mgt   = axiEthBvi.mgt;\n\t interface AxiethbviMdio sfp = axiEthBvi.sfp;\n\t interface Clock deleteme_unused_clock = clock;\n\t interface Reset deleteme_unused_reset = reset;\n      endinterface\n   endinterface\n   interface Vector dmaReadClient = map(toMemReadClient(objId), vec(m_axi_mm2s, m_axi_sg));\n   interface Vector dmaWriteClient = map(toMemWriteClient(objId), vec(m_axi_s2mm, m_axi_sg));\nendmodule\n"
  },
  {
    "path": "tests/axieth/EthPins.bsv",
    "content": "\nimport AxiEthBvi::*;\n\ninterface EthPins;\n   interface AxiethbviSfp sfp;\n   interface AxiethbviMgt mgt;\n   interface Clock deleteme_unused_clock;\n   interface Reset deleteme_unused_reset;\nendinterface\n\n(* always_ready, always_enabled *)\ninterface AxiEthPins;\n   interface EthPins eth;\nendinterface"
  },
  {
    "path": "tests/axieth/Makefile",
    "content": "CONNECTALDIR?=../..\nS2H_INTERFACES = AxiEthTestRequest:AxiEth.request\nH2S_INTERFACES = AxiEth:AxiEthTestIndication:host\nMEM_READ_INTERFACES = lAxiEth.dmaReadClient\nMEM_WRITE_INTERFACES = lAxiEth.dmaWriteClient\n\nCONNECTALFLAGS+= -P mkConnectalTop\nCONNECTALFLAGS+= --shared\n\n\nBSVFILES = AxiEth.bsv\nCPPFILES=testaxieth.cpp\n\nCONNECTALFLAGS+= -DDataBusWidth=32\n## ethernet uses the 200MHz SYS clock\nCONNECTALFLAGS += -D XILINX_SYS_CLK -D IMPORT_HOSTIF\nCONNECTALFLAGS+= --xci=$(IPDIR)/$(BOARD)/axi_intc_0/axi_intc_0.xci\nCONNECTALFLAGS+= --xci=$(IPDIR)/$(BOARD)/axi_dma_0/axi_dma_0.xci\nCONNECTALFLAGS+= --xci=$(IPDIR)/$(BOARD)/axi_ethernet_0/axi_ethernet_0.xci\nCONNECTALFLAGS += --constraint=axieth.xdc --implconstraint=axieth.xdc\n\nifneq ($(BOARD),xsim)\nPINOUT_FILE += axieth.json\nendif\nPIN_TYPE = AxiEthPins\nPIN_TYPE_INCLUDE = EthPins\nAUTOTOP = --interface pins:AxiEth.pins\n\ninclude $(CONNECTALDIR)/Makefile.connectal\n"
  },
  {
    "path": "tests/axieth/axieth.h",
    "content": "#ifndef AXIETH_H\n#define AXIETH_H\n\nclass AxiEthTestRequestProxy;\nclass AxiEthTestIndication;\nclass DmaManager;\n\nclass AxiEth {\n public:\n  AxiEth();\n  ~AxiEth();\n  int irq ( const uint8_t newLevel );\n  void status();\n  void setupDma( uint32_t memref );\n  void read(unsigned long offset, uint8_t *buf);\n  void write(unsigned long offset, const uint8_t *buf);\n private:\n  AxiEthTestRequestProxy *request;\n  AxiEthTestIndication *indication;\n  DmaManager           *dmaManager;\n  bool didReset;\n\n  void maybeReset();\n};\n\n#endif\n"
  },
  {
    "path": "tests/axieth/axieth.json",
    "content": "{\n    \"eth_mgt_clk_clk_p_v\": {\n\t\"pins\": \"si5324_clk_p\"\n    },\n    \"eth_mgt_clk_clk_n_v\": {\n\t\"pins\": \"si5324_clk_n\"\n    },\n    \"eth_sfp_rxp_v\": {\n\t\"sfp1\": \"rxp\"\n    },\n    \"eth_sfp_rxn_v\": {\n\t\"sfp1\": \"rxn\"\n    },\n    \"eth_sfp_txp\": {\n\t\"sfp1\": \"txp\"\n    },\n    \"eth_sfp_txn\": {\n\t\"sfp1\": \"txn\"\n    }\n}\n"
  },
  {
    "path": "tests/axieth/axieth.xdc",
    "content": "create_clock -name eth_mgt_clk_clk -period 8.000 [get_ports eth_mgt_clk_clk_p_v]\n"
  },
  {
    "path": "tests/axieth/testaxieth.cpp",
    "content": "\n#include <AxiEthTestIndication.h>\n#include <AxiEthTestRequest.h>\n#include \"dmaManager.h\"\n#include \"axieth.h\"\n\nint verbose = 1;\n\nclass AxiEthTestIndication : public AxiEthTestIndicationWrapper\n{\n  sem_t sem;\npublic:\n    uint32_t buf[16];\n\n  void irqChanged( const uint8_t irqLevel, const uint8_t intrSources ) {\n      fprintf(stderr, \"irqLevel %d intr sources %x\\n\", irqLevel, intrSources);\n    }\n    virtual void resetDone() {\n\tfprintf(stderr, \"reset done\\n\");\n\tsem_post(&sem);\n    }\n    virtual void status ( const uint8_t mmcm_locked, const uint8_t irq, const uint8_t intrSources ) {\n\tfprintf(stderr, \"axi eth status mmcm_locked=%d irq=%d intr sources=%x\\n\", mmcm_locked, irq, intrSources);\n\tsem_post(&sem);\n    }\n\n    void wait() {\n\tif (verbose) fprintf(stderr, \"  waiting ...\");\n\tsem_wait(&sem);\n\tif (verbose) fprintf(stderr, \"  done\\n\");\n    }\n\n    void readDone ( const uint32_t value ) {\n\tbuf[0] = value;\n\tif (verbose) fprintf(stderr, \"readDone value=%08x\\n\", value);\n\tsem_post(&sem);\n    }\n\n    void writeDone (  ) {\n\tif (verbose) fprintf(stderr, \"writeDone\\n\");\n\tsem_post(&sem);\n    }\n\n    AxiEthTestIndication(unsigned int id) : AxiEthTestIndicationWrapper(id) {\n      sem_init(&sem, 0, 0);\n    }\n};\n\n\nAxiEthTestRequestProxy *request;\nAxiEthTestIndication *indication;\n\n#ifdef STANDALONE\nint main(int argc, const char **argv)\n{\n    request = new AxiEthTestRequestProxy(IfcNames_AxiEthTestRequestS2H);\n    indication = new AxiEthTestIndication(IfcNames_AxiEthTestIndicationH2S);\n    fprintf(stderr, \"Reading ID register\\n\");\n    request->read((1<<18) + 0x4f8);\n    indication->wait();\n    for (int i = 0; i < 16; i++) {\n      fprintf(stderr, \"register %04x\\n\", i*4);\n      request->read((1<<18) + i*4);\n      indication->wait();\n      fprintf(stderr, \"now writing ...\\n\");\n      request->write((1<<18) + i*4, 0xbeef);\n      indication->wait();\n      request->read((1<<18) + i*4);\n      indication->wait();\n    }\n    return 0;\n}\n\n#else\nAxiEth::AxiEth()\n    : request(0), indication(0), dmaManager(0), didReset(false)\n{\n    request = new AxiEthTestRequestProxy(IfcNames_AxiEthTestRequestS2H);\n    indication = new AxiEthTestIndication(IfcNames_AxiEthTestIndicationH2S);\n    dmaManager = platformInit();\n}\n\nAxiEth::~AxiEth()\n{\n  //delete request;\n  //delete indication;\n  request = 0;\n  indication = 0;\n}\n\nvoid AxiEth::maybeReset()\n{\n    if (0)\n    if (!didReset) {\n\tfprintf(stderr, \"resetting flash\\n\");\n\trequest->reset();\n\tindication->wait();\n\t//request->setParameters(50, 0);\n\tfprintf(stderr, \"done resetting flash\\n\");\n\tdidReset = true;\n    }\n}\n\nvoid AxiEth::status()\n{\n    request->status();\n    indication->wait();\n}\n\nvoid AxiEth::setupDma(uint32_t memfd)\n{\n    int memref = dmaManager->reference(memfd);\n    request->setupDma(memref);\n}\n\nvoid AxiEth::read(unsigned long offset, uint8_t *buf)\n{\n    maybeReset();\n\n    if (verbose) fprintf(stderr, \"AxiEth::read offset=%lx\\n\", offset);\n    request->read(offset);\n    indication->wait();\n    if (verbose) fprintf(stderr, \"AxiEth::read offset=%lx value=%x\\n\", offset, *(short *)indication->buf);\n    memcpy(buf, indication->buf, 4);\n}\n\nvoid AxiEth::write(unsigned long offset, const uint8_t *buf)\n{\n    maybeReset();\n\n    if (verbose) fprintf(stderr, \"AxiEth::write offset=%lx value=%x\\n\", offset, *(short *)buf);\n    request->write(offset, *(uint32_t *)buf);\n    indication->wait();\n    request->status();\n    indication->wait();\n}\n#endif\n"
  },
  {
    "path": "tests/axieth/xsim_export.tcl",
    "content": "\nset partname {xc7vx690tffg1761-2}\n\ncreate_project -in_memory -name fooproject\nset_property PART $partname [current_project]\n\nread_ip /home/jamey/connectal/out/vc709/axi_ethernet_0/axi_ethernet_0.xci\ngenerate_target simulation [get_ips axi_ethernet_0]\n\nread_ip /home/jamey/connectal/out/vc709/axi_dma_0/axi_dma_0.xci\ngenerate_target simulation [get_ips axi_dma_0]\n\nread_ip /home/jamey/connectal/out/vc709/axi_intc_0/axi_intc_0.xci\ngenerate_target simulation [get_ips axi_intc_0]\n\n#puts [get_files -compile_order sources -used_in simulation -of_objects [get_ips axi_ethernet_0]]\n\nadd_files [glob /home/jamey/connectal/verilog/*.sv]\nadd_files [glob xsim/verilog/*.v]\nadd_files [glob /home/jamey/connectal/verilog/*.v]\nadd_files [glob /scratch/bluespec/Bluespec-2015.09.beta2/lib/Verilog.Vivado/*.v]\nadd_files [glob /scratch/bluespec/Bluespec-2015.09.beta2/lib/Verilog/FIFO1.v]\nadd_files [glob /scratch/bluespec/Bluespec-2015.09.beta2/lib/Verilog/FIFO2.v]\n\nadd_files [get_files -compile_order sources -used_in simulation -of_objects [get_ips axi_ethernet_0]]\nadd_files [get_files -compile_order sources -used_in simulation -of_objects [get_ips axi_dma_0]]\nadd_files [get_files -compile_order sources -used_in simulation -of_objects [get_ips axi_intc_0]]\nset_property TOP xsimtop [get_filesets sim_1]\nexport_simulation -simulator xsim\n"
  },
  {
    "path": "tests/bluecheck-bram/Bram2Example.bsv",
    "content": "/* \n * Copyright 2015 Matthew Naylor\n * All rights reserved.\n *\n * This software was developed by SRI International and the University of\n * Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-10-C-0237\n * (\"CTSRD\"), as part of the DARPA CRASH research programme.\n *\n * This software was developed by SRI International and the University of\n * Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-11-C-0249\n * (\"MRC2\"), as part of the DARPA MRC research programme.\n *\n * This software was developed by the University of Cambridge Computer\n * Laboratory as part of the Rigorous Engineering of Mainstream\n * Systems (REMS) project, funded by EPSRC grant EP/K008528/1.\n *\n * @BERI_LICENSE_HEADER_START@\n *\n * Licensed to BERI Open Systems C.I.C. (BERI) under one or more contributor\n * license agreements.  See the NOTICE file distributed with this work for\n * additional information regarding copyright ownership.  BERI licenses this\n * file to you under the BERI Hardware-Software License, Version 1.0 (the\n * \"License\"); you may not use this file except in compliance with the\n * License.  You may obtain a copy of the License at:\n *\n *   http://www.beri-open-systems.org/legal/license-1-0.txt\n *\n * Unless required by applicable law or agreed to in writing, Work distributed\n * under the License is distributed on an \"AS IS\" BASIS, WITHOUT WARRANTIES OR\n * CONDITIONS OF ANY KIND, either express or implied.  See the License for the\n * specific language governing permissions and limitations under the License.\n *\n * @BERI_LICENSE_HEADER_END@\n */\n\nimport Vector    :: *;\nimport BRAMCore  :: *;\nimport BlueCheck :: *;\nimport FShow     :: *;\nimport StmtFSM   :: *;\nimport Clocks    :: *;\nimport RegFile   :: *;\nimport GetPut    :: *;\nimport BRAM      :: *;\nimport FIFO      :: *;\nimport DefaultValue::*;\n\nimport ConnectalBram::*;\n\n///////////////\n// Interface //\n///////////////\n\n//////////////////\n// Specfication //\n//////////////////\n\n/* Make a stack with space for 2^n elements of type a */\nmodule mkBramSpec (BRAM2Port#(addr, data))\n   provisos(Bits#(addr, asz), Bits#(data, dsz), Bounded#(addr));\n\n   RegFile#(addr, data) regFile <- mkRegFileFull();\n   Vector#(2,FIFO#(BRAMRequest#(addr,data))) reqFifo <- replicateM(mkFIFO());\n   Vector#(2, FIFO#(data))              responseFifo <- replicateM(mkFIFO());\n\n   for (Integer i = 0; i < 2; i = i + 1)\n       rule process;\n\t  let req <- toGet(reqFifo[i]).get();\n\t  if (req.write) begin\n\t     //$display(\"mkBramSpec: write address=%h data=%h\", req.address, req.datain);\n\t     regFile.upd(req.address, req.datain);\n\t     if (req.responseOnWrite)\n\t\tresponseFifo[i].enq(req.datain);\n\t  end\n\t  else begin\n\t     let d = regFile.sub(req.address);\n\t     //$display(\"mkBramSpec: read address=%h data=%h\", req.address, d);\n\t     responseFifo[i].enq(d);\n\t     end\n       endrule\n   interface Server portA;\n      interface Put request = toPut(reqFifo[0]);\n      interface Get response = toGet(responseFifo[0]);\n   endinterface\n   interface Server portB;\n      interface Put request = toPut(reqFifo[1]);\n      interface Get response = toGet(responseFifo[1]);\n   endinterface\n\nendmodule\n\n////////////////////\n// Implementation //\n////////////////////\n\nmodule mkBramStd(BRAM2Port#(addr,data))\n   provisos(Bits#(addr, asz), Bits#(data, dsz));\n   let cfg = defaultValue;\n   cfg.latency = 2;\n   let bram <- mkBRAM2Server(cfg);\n   return bram;\nendmodule\n\nmodule mkBramImpl(BRAM2Port#(addr,data))\n   provisos(Bits#(addr, asz), Bits#(data, dsz));\n   let cfg = defaultValue;\n   cfg.latency = 2;\n   let bram <- ConnectalBram::mkBRAM2Server(cfg);\n   return bram;\nendmodule\n\n/////////////////////////\n// Equivalence testing //\n/////////////////////////\n\ninstance FShow#(BRAMRequest#(a, d)) provisos (FShow#(a), FShow#(d), Bits#(a, asz), Bits#(d, dsz));\n   function Fmt fshow(BRAMRequest#(a, d) req);\n      return $format(\"<BRAMRequest \", req.write ? \"write \" : \"read \", \n\t\t     req.responseOnWrite ? \"response \" : \"\",\n\t\t     fshow(req.address),\n\t\t     req.write ? (fshow(\" data=\")+fshow(req.datain)) : fshow(\"\"), \">\");\n   endfunction\nendinstance\n\n\nmodule [BlueCheck] checkBram ();\n  /* Specification instance */\n  BRAM2Port#(Bit#(2),Bit#(8)) spec <- mkBramStd();\n\n  /* Implmentation instance */\n  BRAM2Port#(Bit#(2),Bit#(8)) imp <- mkBramImpl();\n\n   Ensure ensure <- getEnsure;\n\n   equivf(4, \"reqA\"    , spec.portA.request.put    , imp.portA.request.put);\n   equivf(2, \"respA\"   , spec.portA.response.get   , imp.portA.response.get);\n   equivf(4, \"reqB\"    , spec.portB.request.put    , imp.portB.request.put);\n   equivf(2, \"respB\"   , spec.portB.response.get   , imp.portB.response.get);\n   // prop(\"prop1\"  , prop1); // deadlocks\n   parallel(list(\"reqA\", \"reqB\"));\nendmodule\n\nmodule [Module] testBram ();\n  blueCheck(checkBram);\nendmodule\nmodule [Module] testBramID ();\n  Clock clk <- exposeCurrentClock;\n  MakeResetIfc r <- mkReset(0, True, clk);\n  blueCheckID(checkBram(reset_by r.new_rst), r);\nendmodule\n"
  },
  {
    "path": "tests/bluecheck-bram/BramExample.bsv",
    "content": "/* \n * Copyright 2015 Matthew Naylor\n * All rights reserved.\n *\n * This software was developed by SRI International and the University of\n * Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-10-C-0237\n * (\"CTSRD\"), as part of the DARPA CRASH research programme.\n *\n * This software was developed by SRI International and the University of\n * Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-11-C-0249\n * (\"MRC2\"), as part of the DARPA MRC research programme.\n *\n * This software was developed by the University of Cambridge Computer\n * Laboratory as part of the Rigorous Engineering of Mainstream\n * Systems (REMS) project, funded by EPSRC grant EP/K008528/1.\n *\n * @BERI_LICENSE_HEADER_START@\n *\n * Licensed to BERI Open Systems C.I.C. (BERI) under one or more contributor\n * license agreements.  See the NOTICE file distributed with this work for\n * additional information regarding copyright ownership.  BERI licenses this\n * file to you under the BERI Hardware-Software License, Version 1.0 (the\n * \"License\"); you may not use this file except in compliance with the\n * License.  You may obtain a copy of the License at:\n *\n *   http://www.beri-open-systems.org/legal/license-1-0.txt\n *\n * Unless required by applicable law or agreed to in writing, Work distributed\n * under the License is distributed on an \"AS IS\" BASIS, WITHOUT WARRANTIES OR\n * CONDITIONS OF ANY KIND, either express or implied.  See the License for the\n * specific language governing permissions and limitations under the License.\n *\n * @BERI_LICENSE_HEADER_END@\n */\n\nimport Vector    :: *;\nimport BRAMCore  :: *;\nimport BlueCheck :: *;\nimport FShow     :: *;\nimport StmtFSM   :: *;\nimport Clocks    :: *;\nimport RegFile   :: *;\nimport GetPut    :: *;\nimport BRAM      :: *;\nimport FIFO      :: *;\nimport DefaultValue::*;\n\nimport ConnectalBram::*;\n\n///////////////\n// Interface //\n///////////////\n\n//////////////////\n// Specfication //\n//////////////////\n\n/* Make a stack with space for 2^n elements of type a */\nmodule mkBramSpec (BRAMServer#(addr, data))\n   provisos(Bits#(addr, asz), Bits#(data, dsz), Bounded#(addr));\n\n   RegFile#(addr, data) regFile <- mkRegFileFull();\n   FIFO#(BRAMRequest#(addr,data)) reqFifo <- mkFIFO();\n   FIFO#(data)     responseFifo <- mkFIFO();\n\n   rule process;\n      let req <- toGet(reqFifo).get();\n      if (req.write) begin\n\t //$display(\"mkBramSpec: write address=%h data=%h\", req.address, req.datain);\n\t regFile.upd(req.address, req.datain);\n\t if (req.responseOnWrite)\n\t    responseFifo.enq(req.datain);\n      end\n      else begin\n\t let d = regFile.sub(req.address);\n\t //$display(\"mkBramSpec: read address=%h data=%h\", req.address, d);\n\t responseFifo.enq(d);\n\t end\n   endrule\n   interface Put request = toPut(reqFifo);\n   interface Get response = toGet(responseFifo);\n\nendmodule\n\n////////////////////\n// Implementation //\n////////////////////\n\nmodule mkBramImpl(BRAMServer#(addr,data))\n   provisos(Bits#(addr, asz), Bits#(data, dsz));\n   let cfg = defaultValue;\n   cfg.latency = 2;\n   let bram <- ConnectalBram::mkBRAM2Server(cfg);\n   interface request = bram.portA.request;\n   interface response = bram.portA.response;\nendmodule\n\n/////////////////////////\n// Equivalence testing //\n/////////////////////////\n\ninstance FShow#(BRAMRequest#(a, d)) provisos (FShow#(a), FShow#(d), Bits#(a, asz), Bits#(d, dsz));\n   function Fmt fshow(BRAMRequest#(a, d) req);\n      return $format(\"<BRAMRequest \", req.write ? \"write \" : \"read \", \n\t\t     req.responseOnWrite ? \"response \" : \"\",\n\t\t     fshow(req.address),\n\t\t     req.write ? (fshow(\" data=\")+fshow(req.datain)) : fshow(\"\"), \">\");\n   endfunction\nendinstance\n\n\nmodule [BlueCheck] checkBram ();\n  /* Specification instance */\n  BRAMServer#(Bit#(2),Bit#(8)) spec <- mkBramSpec();\n\n  /* Implmentation instance */\n  BRAMServer#(Bit#(2),Bit#(8)) imp <- mkBramImpl();\n\n   Ensure ensure <- getEnsure;\n\n   function Stmt prop1(BRAMRequest#(Bit#(2),Bit#(8)) req);\n      return\n      seq\n\t spec.request.put(req);\n\t imp.request.put(req);\n\t if (!req.write || req.responseOnWrite)\n\t action\n\t    let vspec <- spec.response.get();\n\t    let vimp  <- imp.response.get();\n\t    ensure(vspec == vimp);\n\t endaction\n      endseq;\n   endfunction\n\n   equiv(\"req\"    , spec.request.put    , imp.request.put);\n   equiv(\"resp\"   , spec.response.get   , imp.response.get);\n   // prop(\"prop1\"  , prop1); // deadlocks\n   parallel(list(\"req\", \"resp\"));\nendmodule\n\nmodule [Module] testBram ();\n  blueCheck(checkBram);\nendmodule\nmodule [Module] testBramID ();\n  Clock clk <- exposeCurrentClock;\n  MakeResetIfc r <- mkReset(0, True, clk);\n  blueCheckID(checkBram(reset_by r.new_rst), r);\nendmodule\n"
  },
  {
    "path": "tests/bluecheck-bram/make.sh",
    "content": "#!/bin/bash\n#\n# Copyright (c) 2015 Matthew Naylor\n# All rights reserved.\n#\n# This software was developed by SRI International and the University of\n# Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-10-C-0237\n# (\"CTSRD\"), as part of the DARPA CRASH research programme.\n#\n# This software was developed by SRI International and the University of\n# Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-11-C-0249\n# (\"MRC2\"), as part of the DARPA MRC research programme.\n#\n# This software was developed by the University of Cambridge Computer\n# Laboratory as part of the Rigorous Engineering of Mainstream\n# Systems (REMS) project, funded by EPSRC grant EP/K008528/1.\n#\n# @BERI_LICENSE_HEADER_START@\n#\n# Licensed to BERI Open Systems C.I.C. (BERI) under one or more contributor\n# license agreements.  See the NOTICE file distributed with this work for\n# additional information regarding copyright ownership.  BERI licenses this\n# file to you under the BERI Hardware-Software License, Version 1.0 (the\n# \"License\"); you may not use this file except in compliance with the\n# License.  You may obtain a copy of the License at:\n#\n#   http://www.beri-open-systems.org/legal/license-1-0.txt\n#\n# Unless required by applicable law or agreed to in writing, Work distributed\n# under the License is distributed on an \"AS IS\" BASIS, WITHOUT WARRANTIES OR\n# CONDITIONS OF ANY KIND, either express or implied.  See the License for the\n# specific language governing permissions and limitations under the License.\n#\n# @BERI_LICENSE_HEADER_END@\n#\n\nBSC=\"bsc\"\nBSCFLAGS=\"-keep-fires -cross-info -aggressive-conditions \\\n          -wait-for-license -suppress-warnings G0043 \\\n          -steps-warn-interval 300000 \\\n          -simdir bluesim -bdir bluesim -info-dir bluesim \\\n          -p +:../../../bluecheck:../../bsv:../../lib/bsv\"\nSUFFIXES=\n\n# UI\n# ==\n\necho \"(11) BRAM\"\necho \"(12) BRAM2Port\"\n\n#read OPTION\nOPTION=12\ncase \"$OPTION\" in\n 11) TOPFILE=BramExample.bsv\n     TOPMOD=testBram\n     ;;\n 12) TOPFILE=Bram2Example.bsv\n     TOPMOD=testBram\n     ;;\n  *) echo \"Option not recognised\"\n     exit\n     ;;\nesac\n  \n# Build it\n# ========\n\nmkdir -p bluesim\necho Compiling $TOPMOD in file $TOPFILE\nif [ \"$SYNTH\" = \"1\" ]\nthen\n  bsc -suppress-warnings G0043 -u -verilog -g $TOPMOD $TOPFILE\nelse\n  if $BSC $BSCFLAGS -sim -g $TOPMOD -u $TOPFILE\n  then\n    if $BSC $BSCFLAGS -sim -o $TOPMOD -e $TOPMOD  bluesim/$TOPMOD.ba\n    then\n        ./$TOPMOD\n    else\n        echo Failed to generate executable simulation model\n    fi\n  else\n    echo Failed to compile\n  fi\nfi\n"
  },
  {
    "path": "tests/bluecheck-sharedmemfifo/ConnectalProjectConfig.bsv",
    "content": "`define ConnectalVersion 15.10.3\n`define NumberOfMasters 1\n`define PinType Empty\n`define PinTypeInclude Misc\n`define NumberOfUserTiles 1\n`define SlaveDataBusWidth 32\n`define SlaveControlAddrWidth 5\n`define BurstLenSize 8\n`define project_dir $(DTOP)\n`define MainClockPeriod 20\n`define DerivedClockPeriod 10.000000\n`define BsimHostInterface \n`define PhysAddrWidth 40\n`define SIMULATION \n`define BOARD_bluesim \n"
  },
  {
    "path": "tests/bluecheck-sharedmemfifo/SharedMemoryFifoCheck.bsv",
    "content": "// Copyright (c) 2015 The Connectal Project\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\nimport Vector    :: *;\nimport BRAMCore  :: *;\nimport BlueCheck :: *;\nimport FShow     :: *;\nimport StmtFSM   :: *;\nimport Clocks    :: *;\nimport GetPut    :: *;\nimport FIFO      :: *;\nimport RegFile   :: *;\nimport DefaultValue::*;\nimport Pipe      :: *;\nimport SharedMemoryFifo::*;\nimport ConnectalMemTypes  :: *;\nimport Portal    :: *;\nimport MemReadEngine :: *;\nimport MemWriteEngine :: *;\n\n////////////////////\n// Implementation //\n////////////////////\n\ninterface RegFileMemory;\n   method Action write(Bit#(10) addr, Bit#(64) data);\n   method Bit#(64) read(Bit#(10) addr);\nendinterface\n\nmodule mkMemory#(MemReadClient#(64) readClient, MemWriteClient#(64) writeClient)(RegFileMemory);\n   RegFile#(Bit#(10), Bit#(64)) regFile <- mkRegFileFull();\n\n   Reg#(Bit#(MemOffsetSize)) readAddr <- mkReg(0);\n   Reg#(Bit#(BurstLenSize)) readLen   <- mkReg(0);\n   Reg#(Bit#(MemTagSize))   readTag   <- mkReg(0);\n\n   Reg#(Bit#(MemOffsetSize)) writeAddr <- mkReg(0);\n   Reg#(Bit#(BurstLenSize))  writeLen  <- mkReg(0);\n   Reg#(Bit#(MemTagSize))    writeTag  <- mkReg(0);\n   FIFO#(Bit#(MemTagSize))   writeDoneFifo <- mkFIFO();\n   let verbose = True;\n\n   rule readAddrRule if (readLen == 0 && writeLen == 0);\n      let req <- readClient.readReq.get();\n      if (verbose) $display(\"readAddrRule addr=%h\", req.offset);\n      readAddr <= req.offset;\n      readLen  <= req.burstLen;\n      readTag  <= req.tag;\n   endrule\n   rule readDataRule if (readLen > 0);\n      if (verbose) $display(\"readDataRule addr=%h data=%h\", readAddr, regFile.sub(truncate(readAddr)));\n      readClient.readData.put(MemData { data: regFile.sub(truncate(readAddr)), tag: readTag, last: readLen <= 8 });\n      readAddr <= readAddr + 8;\n      readLen <= readLen - 8;\n   endrule\n\n   (* descending_urgency = \"writeAddrRule,readAddrRule\" *)\n   rule writeAddrRule if (readLen == 0 && writeLen == 0);\n      let req <- writeClient.writeReq.get();\n      if (verbose) $display(\"writeAddrRule addr=%h burstLen=%d\", req.offset, req.burstLen);\n      writeAddr <= req.offset;\n      writeLen  <= req.burstLen;\n      writeTag  <= req.tag;\n   endrule\n   rule writeDataRule if (writeLen > 0);\n      let md <- writeClient.writeData.get();\n      if (verbose) $display(\"writeDataRule addr=%h data=%h\", writeAddr, md.data);\n      regFile.upd(truncate(writeAddr), md.data);\n      if (writeLen <= 8)\n\t writeDoneFifo.enq(writeTag); // NOTE: this rule deadlocks if it calls writeClient.writeDone.put directly\n      writeLen <= writeLen - 8;\n   endrule\n   rule writeDoneRule;\n      let tag <- toGet(writeDoneFifo).get();\n      writeClient.writeDone.put(tag);\n   endrule\n   method Action write(Bit#(10) addr, Bit#(64) data);\n      if (verbose) $display(\"mem.write addr=%h data=%h\", addr, data);\n      regFile.upd(addr, data);\n   endmethod\n   method Bit#(64) read(Bit#(10) addr);\n      return regFile.sub(addr);\n   endmethod\n\nendmodule\n\nmodule mkSharedMemoryFifoImpl(FIFO#(Bit#(32)));\n   FIFO#(Bit#(32)) dataFifo <- mkFIFO();\n\n   MemReadEngine#(64,64,4, 2)  readEngine <- mkMemReadEngine();\n   MemWriteEngine#(64,64,4, 2) writeEngine <- mkMemWriteEngine();\n   let mem <- mkMemory(readEngine.dmaClient, writeEngine.dmaClient);\n\n   Reg#(Bit#(32)) dataReg <- mkReg(0);\n   Reg#(Bit#(32)) wrPtrReg <- mkReg(16);\n   Reg#(Bit#(32)) rdPtrReg[2] <- mkCReg(2,16);\n   \n   Bit#(32) limitPtr = 8*8;\n\n   SharedMemoryPipeOut#(64,1) dut <- mkSharedMemoryPipeOut(readEngine.readServers, writeEngine.writeServers);\n\n   Reg#(Bool) notFull <- mkReg(True);\n   rule rdPtrRule if (!notFull);\n      let v = mem.read(8);\n      rdPtrReg[0] <= v[31:0] << 2;\n      //$display(\"updating rdPtr %d\", rdPtrReg[0]);\n   endrule\n   rule notFullRule;\n      let nf = (wrPtrReg != (rdPtrReg[1]+8));\n      if (wrPtrReg == 16)\n\t nf = (rdPtrReg[1] != (limitPtr - 8));\n      $display(\"notFullRule nf=%d wrPtr %d rdPtr %d limitPtr %d\", nf, wrPtrReg, rdPtrReg[1], limitPtr);\n      notFull <= nf;\n   endrule\n\n   let fsm <- mkAutoFSM(seq\n\t\t\tmem.write(0, { wrPtrReg>>2, limitPtr });\n\t\t\tmem.write(8, { 0, rdPtrReg[1]>>2 });\n\t\t\tdut.cfg.setSglId(22);\n      $display(\"wrote fifo wrPtr/rdPtr ptr\");\n\t\t\twhile (True) seq\n\t\t\t   await(notFull);\n\t\t\t   dataReg <= dataFifo.first();\n\t\t\t   dataFifo.deq();\n\t\t\t   mem.write(truncate(wrPtrReg+0), {dataReg, 2});\n\t\t\t   mem.write(0, { wrPtrReg>>2, 32 });\n\t\t\t   action\n\t\t\t       let wrPtr = wrPtrReg + 8;\n\t\t\t       if (wrPtr >= limitPtr) begin\n\t\t\t\t  wrPtr = 16;\n\t\t\t       $display(\"wrapped around wrPtr=%d limitPtr=%d\", wrPtr, limitPtr);\n\t\t\t       end\n\t\t\t       wrPtrReg <= wrPtr;\n\t\t\t   endaction\n\t\t\t   endseq\n\t\t\tendseq\n\t\t\t);\n\n   method enq = dataFifo.enq;\n   method first = dut.data[0].first;\n   method deq   = dut.data[0].deq;\nendmodule\n\n/////////////////////////\n// Equivalence testing //\n/////////////////////////\n\nmodule [BlueCheck] checkSharedMemoryFifo ();\n  /* Specification instance */\n   FIFO#(Bit#(32)) spec <- mkSizedFIFO(32);\n\n   /* Implmentation instance */\n   FIFO#(Bit#(32)) imp <- mkSharedMemoryFifoImpl();\n\n   Ensure ensure <- getEnsure;\n\n  equiv(\"first\"  , spec.first, imp.first);\n  equiv(\"enq\"    , spec.enq,    imp.enq);\n  equiv(\"deq\"    , spec.deq,    imp.deq);\nendmodule\n\nmodule [Module] testSharedMemoryFifo ();\n  blueCheck(checkSharedMemoryFifo);\nendmodule\n"
  },
  {
    "path": "tests/bluecheck-sharedmemfifo/make.sh",
    "content": "#!/bin/bash\n#\n# Copyright (c) 2015 Matthew Naylor\n# All rights reserved.\n#\n# This software was developed by SRI International and the University of\n# Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-10-C-0237\n# (\"CTSRD\"), as part of the DARPA CRASH research programme.\n#\n# This software was developed by SRI International and the University of\n# Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-11-C-0249\n# (\"MRC2\"), as part of the DARPA MRC research programme.\n#\n# This software was developed by the University of Cambridge Computer\n# Laboratory as part of the Rigorous Engineering of Mainstream\n# Systems (REMS) project, funded by EPSRC grant EP/K008528/1.\n#\n# @BERI_LICENSE_HEADER_START@\n#\n# Licensed to BERI Open Systems C.I.C. (BERI) under one or more contributor\n# license agreements.  See the NOTICE file distributed with this work for\n# additional information regarding copyright ownership.  BERI licenses this\n# file to you under the BERI Hardware-Software License, Version 1.0 (the\n# \"License\"); you may not use this file except in compliance with the\n# License.  You may obtain a copy of the License at:\n#\n#   http://www.beri-open-systems.org/legal/license-1-0.txt\n#\n# Unless required by applicable law or agreed to in writing, Work distributed\n# under the License is distributed on an \"AS IS\" BASIS, WITHOUT WARRANTIES OR\n# CONDITIONS OF ANY KIND, either express or implied.  See the License for the\n# specific language governing permissions and limitations under the License.\n#\n# @BERI_LICENSE_HEADER_END@\n#\n\nBSC=\"bsc\"\nBSCFLAGS=\"-keep-fires -cross-info -aggressive-conditions \\\n          -wait-for-license -suppress-warnings G0043 \\\n          -steps-warn-interval 300000 \\\n          -simdir bluesim -bdir bluesim -info-dir bluesim \\\n          -show-schedule \\\n          -D PinTypeInclude=HostInterface -D PinType=Empty -D BurstLenSize=8 -D PhysAddrWidth=16 -D NumberOfMasters=1 \\\n          -D SlaveDataBusWidth=32 -D SlaveControlAddrWidth=16 -D NumberOfUserTiles=16 \\\n          -p +:../../../bluecheck:../../lib/bsv:../../bsv\"\nSUFFIXES=\n\n# UI\n# ==\n\necho \"(11) SharedMemoryFifo\"\necho \"(12) SharedMemoryFifo Iterative Deepening\"\n\n#read OPTION\nOPTION=11\ncase \"$OPTION\" in\n 11) TOPFILE=SharedMemoryFifoCheck.bsv\n     TOPMOD=testSharedMemoryFifo\n     ;;\n 12) TOPFILE=SharedMemoryFifoCheck.bsv\n     TOPMOD=testSharedMemoryFifoID\n     ;;\n  *) echo \"Option not recognised\"\n     exit\n     ;;\nesac\n  \n# Build it\n# ========\n\nmkdir -p bluesim\necho Compiling $TOPMOD in file $TOPFILE\nif [ \"$SYNTH\" = \"1\" ]\nthen\n  bsc -suppress-warnings G0043 -u -verilog -g $TOPMOD $TOPFILE\nelse\n  if $BSC $BSCFLAGS -sim -g $TOPMOD -u $TOPFILE\n  then\n    if $BSC $BSCFLAGS -sim -o $TOPMOD -e $TOPMOD  bluesim/$TOPMOD.ba\n    then\n        ./$TOPMOD\n    else\n        echo Failed to generate executable simulation model\n    fi\n  else\n    echo Failed to compile\n  fi\nfi\n"
  },
  {
    "path": "tests/bluecheck_harness/Harness.bsv",
    "content": "import AxiBits::*;\n\n\ninterface HarnessRequest;\n   method Action startTest(Bit#(16) v);\nendinterface\ninterface HarnessResponse;\n   method Action testStarted(Bit#(16) v);\nendinterface\n\ninterface Harness;\n   interface HarnessRequest request;\nendinterface\n\nmodule [Module] mkHarness#(HarnessResponse response)(Harness);\n   let checker <- mkMkPhysMemSlaveChecker();\n\n   interface HarnessRequest request;\n      method Action startTest(Bit#(16) v);\n\t $display(\"startTest %x is a no op\", v);\n\t response.testStarted(v);\n      endmethod\n   endinterface\nendmodule\n"
  },
  {
    "path": "tests/bluecheck_harness/Makefile",
    "content": "CONNECTALDIR?=../..\nS2H_INTERFACES = HarnessRequest:Harness.request\nH2S_INTERFACES = Harness:HarnessResponse\n\nBSVFILES = Harness.bsv\nPYFILES  = physmemrequest.py\n\nCONNECTALFLAGS += -D BLUECHECK --bsvpath=$(CONNECTALDIR)/../bluecheck\n\ninclude $(CONNECTALDIR)/Makefile.connectal\n\n"
  },
  {
    "path": "tests/bluecheck_harness/harness.py",
    "content": "#!/usr/bin/env python3\n# Copyright (c) 2016 Connectal Project\n#\n# Permission is hereby granted, free of charge, to any person obtaining a\n# copy of this software and associated documentation files (the \"Software\"),\n# to deal in the Software without restriction, including without limitation\n# the rights to use, copy, modify, merge, publish, distribute, sublicense,\n# and/or sell copies of the Software, and to permit persons to whom the\n# Software is furnished to do so, subject to the following conditions:\n#\n# The above copyright notice and this permission notice shall be included\n# in all copies or substantial portions of the Software.\n#\n# THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n# OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n# DEALINGS IN THE SOFTWARE.\n#\nfrom __future__ import print_function\n\nimport portal\n\nclass BlueCheck:\n    def __init__(self):\n        self.proxy = portal.NativeProxy('HarnessRequest', self, responseInterface='HarnessResponse', rpc=True)\n        self.response = None\n\n    def startTest(self, v):\n        self.proxy.startTest(v)\n\nbc = BlueCheck()\nprint(\"test started\")\n\nbc.startTest(22)\n\n"
  },
  {
    "path": "tests/bpiflash/BpiFlashTest.bsv",
    "content": "\n`include \"ConnectalProjectConfig.bsv\"\nimport Connectable::*;\nimport GetPut::*;\nimport FIFOF::*;\nimport BRAM::*;\nimport Probe::*;\nimport StmtFSM::*;\nimport TriState::*;\nimport Vector::*;\nimport ConnectalXilinxCells::*;\nimport BpiFlash::*;\n`ifdef SIMULATION\nimport I28F512P33::*;\n`endif\n\ninterface BpiFlashTestRequest;\n   method Action reset();\n   method Action read(Bit#(25) addr);\n   method Action write(Bit#(25) addr, Bit#(16) data);\n   method Action setParameters(Bit#(16) cycles, Bool stallOnWaitIn);\nendinterface\n\ninterface BpiFlashTestIndication;\n   method Action resetDone();\n   method Action readDone(Bit#(16) data);\n   method Action writeDone();\nendinterface\n\ninterface BpiFlashTest;\n   interface BpiFlashTestRequest request;\n   interface BpiPins pins;\nendinterface\n\nmodule mkBpiFlashTest#(BpiFlashTestIndication ind)(BpiFlashTest);\n\n   let defaultClock <- exposeCurrentClock();\n   let defaultReset <- exposeCurrentReset();\n\n   Reg#(Bit#(1)) rst_o <- mkReg(0);\n   Reg#(Bit#(1)) ce <- mkReg(1);\n   Reg#(Bit#(1)) we <- mkReg(1);\n   Reg#(Bit#(1)) oe <- mkReg(1);\n   Reg#(Bit#(1)) adv <- mkReg(1);\n   Reg#(Bit#(16)) data_o <- mkReg(0);\n   Reg#(Bit#(25)) addr_o <- mkReg(0);\n   Reg#(Bit#(16)) delayReg <- mkReg(10);\n   Reg#(Bool)     stallOnWaitReg  <- mkReg(False);\n   Reg#(BRAMRequest#(Bit#(25),Bit#(16))) reqReg <- mkReg(unpack(0));\n   FIFOF#(BRAMRequest#(Bit#(25),Bit#(16))) reqFifo <- mkFIFOF();\n   FIFOF#(Bit#(16)) dataFifo <- mkFIFOF();\n   FIFOF#(Bool)     doneFifo <- mkFIFOF();\n\n`ifndef SIMULATION\n   Wire#(Bit#(1)) wait_in_b <- mkDWire(0);\n   module mkDataIobuf#(Integer i)(IOBUF);\n      (* hide *)\n      let iobuf <- mkIOBUF(we, data_o[i]);\n      return iobuf;\n   endmodule\n   function Inout#(Bit#(1)) iobuf_io(IOBUF iobuf); return iobuf.io; endfunction\n   function Bit#(1) iobuf_o(IOBUF iobuf); return iobuf.o; endfunction\n   Vector#(16, IOBUF) iobuf <- genWithM(mkDataIobuf);\n   let dataIn = pack(map(iobuf_o, iobuf));\n`endif\n\n`ifdef SIMULATION\n   let flash <- mkI28f512p33Load(\"flash.hex\");\n   let dataTristate <- mkTriState(oe == 1, data_o);\n   mkConnection(dataTristate.io, flash.dq);\n   let wait_in_b = flash.waitout();\n   let dataIn = dataTristate;\n   rule rl_flash_inputs;\n      flash.addr(addr_o);\n      flash.advneg(adv);\n      flash.ceneg(ce);\n      flash.oeneg(oe);\n      flash.weneg(we);\n      flash.wpneg(1);\n      flash.vpp(0);\n   endrule\n`endif\n\n   Reg#(Bit#(10)) i <- mkReg(0);\n\n   let readFsm <- mkFSM(seq\n\t\t\t   $dumpfile(\"bpiflash.vcd\");\n\t\t\t   $dumpvars();\n\t\t\t   $dumpoff();\n\t\t\twhile (True) seq\n\t\t\t   action\n\t\t\t      $dumpon();\n\n\t\t\t      reqFifo.deq();\n\t\t\t      let req = reqFifo.first();\n\t\t\t      reqReg <= req;\n\t\t\t      addr_o <= req.address >> 1;\n\t\t\t      data_o <= req.datain;\n\t\t\t      adv <= 0;\n\t\t\t      ce <= 0;\n\t\t\t   endaction\n\t\t\t   delay(delayReg);\n\t\t\t   adv <= 1;\n\t\t\t   delay(delayReg);\n\t\t\t   action\n\t\t\t      if (reqReg.write)\n\t\t\t\t we <= 0;\n\t\t\t      else\n\t\t\t\t oe <= 0;\n\t\t\t   endaction\n\t\t\t   delay(delayReg);\n      $display(\"addr_o=%x\\n\", addr_o);\n      $display(\"wait_in_b=%d dataIn=%x\", wait_in_b, dataIn);\n\t\t\t   if (reqReg.write)\n\t\t\t      we <= 1;\n\t\t\t   if (!reqReg.write && stallOnWaitReg) await (wait_in_b == 1);\n      $display(\"wait_in_b=%d dataIn=%x\", wait_in_b, dataIn);\n\t\t\t   if (reqReg.write)\n\t\t\t      doneFifo.enq(True);\n\t\t\t   else\n\t\t\t      dataFifo.enq(dataIn);\n\t\t\t   delay(delayReg);\n\t\t\t   ce <= 1;\n\t\t\t   oe <= 1;\n\t\t\t   delay(delayReg);\n\t\t\t   endseq\n      $dumpoff();\n      $dumpflush();\n\t\t\tendseq);\n   \n   let resetFsm <- mkFSM(seq\n\t\t\t rst_o <= 0;\n\t\t\t delay(20);\n\t\t\t rst_o <= 1;\n\t\t\t ind.resetDone();\n\t\t\t readFsm.start();\n\t\t\t endseq);\n\n   rule rl_readDone;\n      let v <- toGet(dataFifo).get();\n      ind.readDone(v);\n   endrule\n   rule rl_writeDone;\n      let v <- toGet(doneFifo).get();\n      ind.writeDone();\n   endrule\n\n   let probe_addr <- mkProbe();\n   let probe_adv <- mkProbe();\n   let probe_ce <- mkProbe();\n   let probe_oe <- mkProbe();\n   let probe_we <- mkProbe();\n   let probe_data_in <- mkProbe();\n   let probe_data_out <- mkProbe();\n   let probe_wait_in <- mkProbe();\n   rule rl_probe;\n      probe_addr <= addr_o;\n      probe_adv <= adv;\n      probe_ce <= ce;\n      probe_oe <= oe;\n      probe_we <= we;\n      probe_data_in <= dataIn;\n      probe_data_out <= data_o;\n      probe_wait_in <= wait_in_b;\n   endrule\n\n   interface BpiFlashTestRequest request;\n      method Action reset();\n\t resetFsm.start();\n      endmethod\n      method Action read(Bit#(25) addr);\n\t reqFifo.enq(BRAMRequest {address: addr, write: False, responseOnWrite: False, datain: 0});\n      endmethod\n      method Action write(Bit#(25) addr, Bit#(16) data);\n\t reqFifo.enq(BRAMRequest {address: addr, write: True, responseOnWrite: False, datain: data});\n      endmethod\n      method Action setParameters(Bit#(16) cycles, Bool stallOnWaitIn);\n\t delayReg <= cycles;\n\t stallOnWaitReg <= stallOnWaitIn;\n      endmethod\n\n   endinterface\n`ifndef SIMULATION\n   interface BpiPins pins;\n       interface BpiFlashPins flash;\n\t  interface deleteme_unused_clock = defaultClock;\n//          interface rst = defaultReset;\n\t  interface data = map(iobuf_io, iobuf);\n\t  method Bit#(25) addr = addr_o;\n\t  method Bit#(1) adv_b = adv;\n\t  method Bit#(1) ce_b = ce;\n\t  method Bit#(1) oe_b = oe;\n\t  method Bit#(1) we_b = we;\n`ifdef BPI_HAS_WP\n\t  method Bit#(1) wp_b = 1;\n`endif\n`ifdef BPI_HAS_VPP\n\t  method Bit#(1) vpp = 0;\n`endif\n\t  method Action wait_in(Bit#(1) b);\n\t     wait_in_b <= b;\n\t  endmethod\n       endinterface\n   endinterface\n`endif\nendmodule\n"
  },
  {
    "path": "tests/bpiflash/I28F512P33.bsv",
    "content": "\n/*\n   ../../generated/scripts/importbvi.py\n   -o\n   I28F512P33.bsv\n   -I\n   I28f512p33\n   -P\n   StrataFlash\n   -c\n   CLK\n   -r\n   RSTNeg\n   i28f512p33.v\n*/\n\nimport Clocks::*;\nimport DefaultValue::*;\nimport XilinxCells::*;\nimport GetPut::*;\nimport AxiBits::*;\n\n(* always_ready, always_enabled *)\ninterface I28f512p33;\n    method Action      addr(Bit#(25) v);\n    method Action      advneg(Bit#(1) v);\n    method Action      ceneg(Bit#(1) v);\n    interface Inout#(Bit#(16))     dq;\n    method Action      oeneg(Bit#(1) v);\n    method Action      vpp(Bit#(1) v);\n    method Bit#(1)     waitout();\n    method Action      weneg(Bit#(1) v);\n    method Action      wpneg(Bit#(1) v);\nendinterface\nimport \"BVI\" i28f512p33 =\nmodule mkI28f512p33Load#(String memFileName)(I28f512p33);\n    parameter mem_file_name = memFileName;\n    parameter mem_file_name_1 = memFileName;\n    parameter UserPreload = 1;\n    default_clock clk(CLK);\n    default_reset rstneg(RSTNeg);\n    method addr(Addr) enable((*inhigh*) EN_Addr);\n    method advneg(ADVNeg) enable((*inhigh*) EN_ADVNeg);\n    method ceneg(CENeg) enable((*inhigh*) EN_CENeg);\n    ifc_inout dq(DQ);\n    method oeneg(OENeg) enable((*inhigh*) EN_OENeg);\n    method vpp(VPP) enable((*inhigh*) EN_VPP);\n    method WAITOut waitout();\n    method weneg(WENeg) enable((*inhigh*) EN_WENeg);\n    method wpneg(WPNeg) enable((*inhigh*) EN_WPNeg);\n    schedule (addr, advneg, ceneg, oeneg, vpp, waitout, weneg, wpneg) CF (addr, advneg, ceneg, oeneg, vpp, waitout, weneg, wpneg);\nendmodule\n\nmodule mkI28f512p33(I28f512p33);\n   (* hide *)let flash <- mkI28f512p33Load(\"none\");\n   return flash;\nendmodule"
  },
  {
    "path": "tests/bpiflash/Makefile",
    "content": "CONNECTALDIR?=../..\nS2H_INTERFACES = BpiFlashTestRequest:BpiFlashTest.request\nH2S_INTERFACES = BpiFlashTest:BpiFlashTestIndication\n\nCONNECTALFLAGS+= -P mkConnectalTop\nCONNECTALFLAGS+= --shared\n\n\nBSVFILES = BpiFlashTest.bsv\nCPPFILES=testbpiflash.cpp\n\nifneq ($(BOARD),vc709)\nCONNECTALFLAGS+= --verilog=i28f512p33.v\nendif\n\nifeq ($(BOARD),vc709)\nPINOUT_FILE += bpiflash.json\nPIN_TYPE = BpiPins\nPIN_TYPE_INCLUDE = BpiFlash\nAUTOTOP = --interface pins:BpiFlashTest.pins\nendif\n\nflash.mcs: flash.hex\n\tvivado -mode batch -source genmcs.tcl\n\ninclude $(CONNECTALDIR)/Makefile.connectal\n"
  },
  {
    "path": "tests/bpiflash/bpiflash.h",
    "content": "#ifndef BPIFLASH_H\n#define BPIFLASH_H\n\nclass BpiFlashTestRequestProxy;\nclass BpiFlashTestIndication;\n\nclass BpiFlash {\n public:\n  BpiFlash();\n  ~BpiFlash();\n  void read(unsigned long offset, uint8_t *buf);\n  void write(unsigned long offset, const uint8_t *buf);\n private:\n  BpiFlashTestRequestProxy *request;\n  BpiFlashTestIndication *indication;\n  bool didReset;\n\n  void maybeReset();\n};\n\n#endif\n\n"
  },
  {
    "path": "tests/bpiflash/bpiflash.json",
    "content": "{\n    \"flash_data_0\": {\n\t\"bpi_flash\": \"data[0]\"\n    },\n    \"flash_data_1\": {\n\t\"bpi_flash\": \"data[1]\"\n    },\n    \"flash_data_2\": {\n\t\"bpi_flash\": \"data[2]\"\n    },\n    \"flash_data_3\": {\n\t\"bpi_flash\": \"data[3]\"\n    },\n    \"flash_data_4\": {\n\t\"bpi_flash\": \"data[4]\"\n    },\n    \"flash_data_5\": {\n\t\"bpi_flash\": \"data[5]\"\n    },\n    \"flash_data_6\": {\n\t\"bpi_flash\": \"data[6]\"\n    },\n    \"flash_data_7\": {\n\t\"bpi_flash\": \"data[7]\"\n    },\n    \"flash_data_8\": {\n\t\"bpi_flash\": \"data[8]\"\n    },\n    \"flash_data_9\": {\n\t\"bpi_flash\": \"data[9]\"\n    },\n    \"flash_data_10\": {\n\t\"bpi_flash\": \"data[10]\"\n    },\n    \"flash_data_11\": {\n\t\"bpi_flash\": \"data[11]\"\n    },\n    \"flash_data_12\": {\n\t\"bpi_flash\": \"data[12]\"\n    },\n    \"flash_data_13\": {\n\t\"bpi_flash\": \"data[13]\"\n    },\n    \"flash_data_14\": {\n\t\"bpi_flash\": \"data[14]\"\n    },\n    \"flash_data_15\": {\n\t\"bpi_flash\": \"data[15]\"\n    },\n    \"flash_addr[0]\": {\n\t\"bpi_flash\": \"addr[0]\"\n    },\n    \"flash_addr[1]\": {\n\t\"bpi_flash\": \"addr[1]\"\n    },\n    \"flash_addr[2]\": {\n\t\"bpi_flash\": \"addr[2]\"\n    },\n    \"flash_addr[3]\": {\n\t\"bpi_flash\": \"addr[3]\"\n    },\n    \"flash_addr[4]\": {\n\t\"bpi_flash\": \"addr[4]\"\n    },\n    \"flash_addr[5]\": {\n\t\"bpi_flash\": \"addr[5]\"\n    },\n    \"flash_addr[6]\": {\n\t\"bpi_flash\": \"addr[6]\"\n    },\n    \"flash_addr[7]\": {\n\t\"bpi_flash\": \"addr[7]\"\n    },\n    \"flash_addr[8]\": {\n\t\"bpi_flash\": \"addr[8]\"\n    },\n    \"flash_addr[9]\": {\n\t\"bpi_flash\": \"addr[9]\"\n    },\n    \"flash_addr[10]\": {\n\t\"bpi_flash\": \"addr[10]\"\n    },\n    \"flash_addr[11]\": {\n\t\"bpi_flash\": \"addr[11]\"\n    },\n    \"flash_addr[12]\": {\n\t\"bpi_flash\": \"addr[12]\"\n    },\n    \"flash_addr[13]\": {\n\t\"bpi_flash\": \"addr[13]\"\n    },\n    \"flash_addr[14]\": {\n\t\"bpi_flash\": \"addr[14]\"\n    },\n    \"flash_addr[15]\": {\n\t\"bpi_flash\": \"addr[15]\"\n    },\n    \"flash_addr[16]\": {\n\t\"bpi_flash\": \"addr[16]\"\n    },\n    \"flash_addr[17]\": {\n\t\"bpi_flash\": \"addr[17]\"\n    },\n    \"flash_addr[18]\": {\n\t\"bpi_flash\": \"addr[18]\"\n    },\n    \"flash_addr[19]\": {\n\t\"bpi_flash\": \"addr[19]\"\n    },\n    \"flash_addr[20]\": {\n\t\"bpi_flash\": \"addr[20]\"\n    },\n    \"flash_addr[21]\": {\n\t\"bpi_flash\": \"addr[21]\"\n    },\n    \"flash_addr[22]\": {\n\t\"bpi_flash\": \"addr[22]\"\n    },\n    \"flash_addr[23]\": {\n\t\"bpi_flash\": \"addr[23]\"\n    },\n    \"flash_addr[24]\": {\n\t\"bpi_flash\": \"addr[24]\"\n    },\n    \"flash_oe_b\": {\n\t\"bpi_flash\": \"oe_b\"\n    },\n    \"flash_ce_b\": {\n\t\"bpi_flash\": \"ce_b\"\n    },\n    \"flash_adv_b\": {\n\t\"bpi_flash\": \"adv_b\"\n    },\n    \"flash_we_b\": {\n\t\"bpi_flash\": \"we_b\"\n    },\n    \"flash_wait_in_b\": {\n\t\"bpi_flash\": \"wait_in_b\"\n    }\n}\n"
  },
  {
    "path": "tests/bpiflash/i28f512p33.v",
    "content": "//////////////////////////////////////////////////////////////////////////////\n//  File name : i28f512p33.v\n//////////////////////////////////////////////////////////////////////////////\n//  Copyright (C) 2007-2009 Free Model Foundry; http://www.FreeModelFoundry.com\n//\n//  This program is free software; you can redistribute it and/or modify\n//  it under the terms of the GNU General Public License version 2 as\n//  published by the Free Software Foundation.\n//\n//  MODIFICATION HISTORY:\n//\n//  version: |    author:      |  mod date: | changes made:\n//  V1.0       I.Milutinovic     07 Jun 13   Initial Release\n//  V1.1       J.Stoickov        09 Apr 01   Write mode corrected for the WENeg\n//                                           and CENeg signals rise at same time\n//  V1.2       S.Petrovic        09 Apr 15   ADV LOW is removed as condition\n//                                           for write address latching\n//\n//  Downloaded from http://www.freemodelfoundry.com/fmf_vlog_models/flash/i28f512p33.v\n//////////////////////////////////////////////////////////////////////////////\n//  PART DESCRIPTION:\n//\n//  Library:     FLASH\n//  Technology:  FLASH MEMORY\n//  Part:        I28F512P33\n//\n//  Description: 2 x 256 Mbit Intel Strata Flash Memory (P33) Family\n//\n//////////////////////////////////////////////////////////////////////////////\n//  Comments :\n//\n//////////////////////////////////////////////////////////////////////////////\n//  Known Bugs:\n//\n//////////////////////////////////////////////////////////////////////////////\n\n`timescale 1 ns/1 ns\n\n//////////////////////////////////////////////////////////////////////////////\n// TOP MODULE DECLARATION, Top and Bottom Parameter Block Configuration     //\n//////////////////////////////////////////////////////////////////////////////\nmodule i28f512p33\n    (\n    input [25:0]    Addr,\n    input [15:0]    DQ,\n\n    input  ADVNeg,\n    input  CENeg,\n    input  CLK,\n    input  OENeg,\n    input  RSTNeg,\n    input  WENeg,\n    input  WPNeg,\n    input  VPP,\n\t  \n    output WAITOut\n     );\n\n    // parameter declaration\n    parameter mem_file_name     = \"none\";\n    parameter mem_file_name_1   = \"none\";\n    parameter otp_blocks_file   = \"none\";\n    parameter otp_blocks_file_1 = \"none\";\n    parameter prot_reg_file     = \"none\";\n    parameter prot_reg_file_1   = \"none\";\n    parameter UserPreload       = 1'b0;\n    parameter TimingModel       = \"defaulttimingmodel\";\n    parameter VPP_voltage       = 9;\n\n    wire CENeg1;\n    wire CENeg2;\n\n   wire [26:1] A;\n   assign A[26:1] = Addr[25:0];\n\n    assign CENeg1 = (~CENeg && A[25]) ? 1'b0 : 1'b1;\n    assign CENeg2 = (~CENeg && ~A[25]) ? 1'b0 : 1'b1;\n\n    // Instance of flash memory, Top Parameter Block Configuration\n    i28f256p33_1 #(mem_file_name, otp_blocks_file, prot_reg_file,\n                 UserPreload , TimingModel, VPP_voltage) UPPER_DIE\n        (\n            .A24(A[24]),\n            .A23(A[23]),\n            .A22(A[22]),\n            .A21(A[21]),\n            .A20(A[20]),\n            .A19(A[19]),\n            .A18(A[18]),\n            .A17(A[17]),\n            .A16(A[16]),\n            .A15(A[15]),\n            .A14(A[14]),\n            .A13(A[13]),\n            .A12(A[12]),\n            .A11(A[11]),\n            .A10(A[10]),\n            .A9(A[9]),\n            .A8(A[8]),\n            .A7(A[7]),\n            .A6(A[6]),\n            .A5(A[5]),\n            .A4(A[4]),\n            .A3(A[3]),\n            .A2(A[2]),\n            .A1(A[1]),\n\n            .DQ15(DQ[15]),\n            .DQ14(DQ[14]),\n            .DQ13(DQ[13]),\n            .DQ12(DQ[12]),\n            .DQ11(DQ[11]),\n            .DQ10(DQ[10]),\n            .DQ9(DQ[9]),\n            .DQ8(DQ[8]),\n            .DQ7(DQ[7]),\n            .DQ6(DQ[6]),\n            .DQ5(DQ[5]),\n            .DQ4(DQ[4]),\n            .DQ3(DQ[3]),\n            .DQ2(DQ[2]),\n            .DQ1(DQ[1]),\n            .DQ0(DQ[0]),\n\n            .ADVNeg (ADVNeg),\n            .CENeg  (CENeg1),\n            .CLK    (CLK   ),\n            .OENeg  (OENeg ),\n            .RSTNeg (RSTNeg),\n            .WENeg  (WENeg ),\n            .WPNeg  (WPNeg ),\n            .VPP    (VPP   ),\n\n            .WAITOut(WAITOut)\n        );\n\n    // Instance of flash memory, Bottom Parameter Block Configuration\n    i28f256p33_2 #(mem_file_name_1, otp_blocks_file_1, prot_reg_file_1,\n                 UserPreload, TimingModel ,VPP_voltage) LOWER_DIE\n        (\n            .A24(A[24]),\n            .A23(A[23]),\n            .A22(A[22]),\n            .A21(A[21]),\n            .A20(A[20]),\n            .A19(A[19]),\n            .A18(A[18]),\n            .A17(A[17]),\n            .A16(A[16]),\n            .A15(A[15]),\n            .A14(A[14]),\n            .A13(A[13]),\n            .A12(A[12]),\n            .A11(A[11]),\n            .A10(A[10]),\n            .A9(A[9]),\n            .A8(A[8]),\n            .A7(A[7]),\n            .A6(A[6]),\n            .A5(A[5]),\n            .A4(A[4]),\n            .A3(A[3]),\n            .A2(A[2]),\n            .A1(A[1]),\n\n            .DQ15(DQ[15]),\n            .DQ14(DQ[14]),\n            .DQ13(DQ[13]),\n            .DQ12(DQ[12]),\n            .DQ11(DQ[11]),\n            .DQ10(DQ[10]),\n            .DQ9(DQ[9]),\n            .DQ8(DQ[8]),\n            .DQ7(DQ[7]),\n            .DQ6(DQ[6]),\n            .DQ5(DQ[5]),\n            .DQ4(DQ[4]),\n            .DQ3(DQ[3]),\n            .DQ2(DQ[2]),\n            .DQ1(DQ[1]),\n            .DQ0(DQ[0]),\n\n            .ADVNeg (ADVNeg),\n            .CENeg  (CENeg2),\n            .CLK    (CLK   ),\n            .OENeg  (OENeg ),\n            .RSTNeg (RSTNeg),\n            .WENeg  (WENeg ),\n            .WPNeg  (WPNeg ),\n            .VPP    (VPP   ),\n\n            .WAITOut(WAITOut)\n        );\n\nendmodule\n\n//////////////////////////////////////////////////////////////////////////////\n// MODULE DECLARATION, Top Parameter Block Configuration                    //\n//////////////////////////////////////////////////////////////////////////////\nmodule i28f256p33_1\n    (\n        A24             ,\n        A23             ,\n        A22             ,\n        A21             ,\n        A20             ,\n        A19             ,\n        A18             ,\n        A17             ,\n        A16             ,\n        A15             ,\n        A14             ,\n        A13             ,\n        A12             ,\n        A11             ,\n        A10             ,\n        A9              ,\n        A8              ,\n        A7              ,\n        A6              ,\n        A5              ,\n        A4              ,\n        A3              ,\n        A2              ,\n        A1              ,\n\n        DQ15            ,\n        DQ14            ,\n        DQ13            ,\n        DQ12            ,\n        DQ11            ,\n        DQ10            ,\n        DQ9             ,\n        DQ8             ,\n        DQ7             ,\n        DQ6             ,\n        DQ5             ,\n        DQ4             ,\n        DQ3             ,\n        DQ2             ,\n        DQ1             ,\n        DQ0             ,\n\n        ADVNeg          ,\n        CENeg           ,\n        CLK             ,\n        OENeg           ,\n        RSTNeg          ,\n        WENeg           ,\n        WPNeg           ,\n        VPP             ,\n\n        WAITOut\n     );\n\n////////////////////////////////////////////////////////////////////////\n// Port / Part Pin Declarations\n////////////////////////////////////////////////////////////////////////\n    input  A24             ;\n    input  A23             ;\n    input  A22             ;\n    input  A21             ;\n    input  A20             ;\n    input  A19             ;\n    input  A18             ;\n    input  A17             ;\n    input  A16             ;\n    input  A15             ;\n    input  A14             ;\n    input  A13             ;\n    input  A12             ;\n    input  A11             ;\n    input  A10             ;\n    input  A9              ;\n    input  A8              ;\n    input  A7              ;\n    input  A6              ;\n    input  A5              ;\n    input  A4              ;\n    input  A3              ;\n    input  A2              ;\n    input  A1              ;\n\n    inout  DQ15            ;\n    inout  DQ14            ;\n    inout  DQ13            ;\n    inout  DQ12            ;\n    inout  DQ11            ;\n    inout  DQ10            ;\n    inout  DQ9             ;\n    inout  DQ8             ;\n    inout  DQ7             ;\n    inout  DQ6             ;\n    inout  DQ5             ;\n    inout  DQ4             ;\n    inout  DQ3             ;\n    inout  DQ2             ;\n    inout  DQ1             ;\n    inout  DQ0             ;\n\n    input  ADVNeg          ;\n    input  CENeg           ;\n    input  CLK             ;\n    input  OENeg           ;\n    input  RSTNeg          ;\n    input  WENeg           ;\n    input  WPNeg           ;\n    input  VPP             ;\n\n    output WAITOut         ;\n\n    // interconnect path delay signals\n    wire  A24_ipd  ;\n    wire  A23_ipd  ;\n    wire  A22_ipd  ;\n    wire  A21_ipd  ;\n    wire  A20_ipd  ;\n    wire  A19_ipd  ;\n    wire  A18_ipd  ;\n    wire  A17_ipd  ;\n    wire  A16_ipd  ;\n    wire  A15_ipd  ;\n    wire  A14_ipd  ;\n    wire  A13_ipd  ;\n    wire  A12_ipd  ;\n    wire  A11_ipd  ;\n    wire  A10_ipd  ;\n    wire  A9_ipd   ;\n    wire  A8_ipd   ;\n    wire  A7_ipd   ;\n    wire  A6_ipd   ;\n    wire  A5_ipd   ;\n    wire  A4_ipd   ;\n    wire  A3_ipd   ;\n    wire  A2_ipd   ;\n    wire  A1_ipd   ;\n\n    wire [23 : 0] A;\n    assign A = {\n                A24_ipd,\n                A23_ipd,\n                A22_ipd,\n                A21_ipd,\n                A20_ipd,\n                A19_ipd,\n                A18_ipd,\n                A17_ipd,\n                A16_ipd,\n                A15_ipd,\n                A14_ipd,\n                A13_ipd,\n                A12_ipd,\n                A11_ipd,\n                A10_ipd,\n                A9_ipd,\n                A8_ipd,\n                A7_ipd,\n                A6_ipd,\n                A5_ipd,\n                A4_ipd,\n                A3_ipd,\n                A2_ipd,\n                A1_ipd };\n\n    wire  DQ15_ipd  ;\n    wire  DQ14_ipd  ;\n    wire  DQ13_ipd  ;\n    wire  DQ12_ipd  ;\n    wire  DQ11_ipd  ;\n    wire  DQ10_ipd  ;\n    wire  DQ9_ipd   ;\n    wire  DQ8_ipd   ;\n    wire  DQ7_ipd   ;\n    wire  DQ6_ipd   ;\n    wire  DQ5_ipd   ;\n    wire  DQ4_ipd   ;\n    wire  DQ3_ipd   ;\n    wire  DQ2_ipd   ;\n    wire  DQ1_ipd   ;\n    wire  DQ0_ipd   ;\n\n    wire [15 : 0 ] DQIn;\n    assign DQIn = {DQ15_ipd,\n                   DQ14_ipd,\n                   DQ13_ipd,\n                   DQ12_ipd,\n                   DQ11_ipd,\n                   DQ10_ipd,\n                   DQ9_ipd,\n                   DQ8_ipd,\n                   DQ7_ipd,\n                   DQ6_ipd,\n                   DQ5_ipd,\n                   DQ4_ipd,\n                   DQ3_ipd,\n                   DQ2_ipd,\n                   DQ1_ipd,\n                   DQ0_ipd };\n\n    wire [15 : 0 ] DQOut;\n    assign DQOut = {DQ15,\n                    DQ14,\n                    DQ13,\n                    DQ12,\n                    DQ11,\n                    DQ10,\n                    DQ9,\n                    DQ8,\n                    DQ7,\n                    DQ6,\n                    DQ5,\n                    DQ4,\n                    DQ3,\n                    DQ2,\n                    DQ1,\n                    DQ0 };\n\n    wire  ADVNeg_ipd      ;\n    wire  CENeg_ipd       ;\n    wire  CLK_ipd         ;\n    wire  OENeg_ipd       ;\n    wire  RSTNeg_ipd      ;\n    wire  WENeg_ipd       ;\n    wire  WPNeg_ipd       ;\n\n    wire  DQ15_zd  ;\n    wire  DQ14_zd  ;\n    wire  DQ13_zd  ;\n    wire  DQ12_zd  ;\n    wire  DQ11_zd  ;\n    wire  DQ10_zd  ;\n    wire  DQ9_zd   ;\n    wire  DQ8_zd   ;\n    wire  DQ7_zd   ;\n    wire  DQ6_zd   ;\n    wire  DQ5_zd   ;\n    wire  DQ4_zd   ;\n    wire  DQ3_zd   ;\n    wire  DQ2_zd   ;\n    wire  DQ1_zd   ;\n    wire  DQ0_zd   ;\n\n    wire  DQ15_Pass  ;\n    wire  DQ14_Pass  ;\n    wire  DQ13_Pass  ;\n    wire  DQ12_Pass  ;\n    wire  DQ11_Pass  ;\n    wire  DQ10_Pass  ;\n    wire  DQ9_Pass   ;\n    wire  DQ8_Pass   ;\n    wire  DQ7_Pass   ;\n    wire  DQ6_Pass   ;\n    wire  DQ5_Pass   ;\n    wire  DQ4_Pass   ;\n    wire  DQ3_Pass   ;\n    wire  DQ2_Pass   ;\n    wire  DQ1_Pass   ;\n    wire  DQ0_Pass   ;\n\n    reg [15 : 0] DQOut_zd = 16'bz;\n    reg [15 : 0] DQOut_Pass = 16'bz;\n\n    assign {DQ15_zd,\n            DQ14_zd,\n            DQ13_zd,\n            DQ12_zd,\n            DQ11_zd,\n            DQ10_zd,\n            DQ9_zd,\n            DQ8_zd,\n            DQ7_zd,\n            DQ6_zd,\n            DQ5_zd,\n            DQ4_zd,\n            DQ3_zd,\n            DQ2_zd,\n            DQ1_zd,\n            DQ0_zd  } = DQOut_zd;\n\n    assign {DQ15_Pass,\n            DQ14_Pass,\n            DQ13_Pass,\n            DQ12_Pass,\n            DQ11_Pass,\n            DQ10_Pass,\n            DQ9_Pass,\n            DQ8_Pass,\n            DQ7_Pass,\n            DQ6_Pass,\n            DQ5_Pass,\n            DQ4_Pass,\n            DQ3_Pass,\n            DQ2_Pass,\n            DQ1_Pass,\n            DQ0_Pass  } = DQOut_Pass;\n\n    reg WAITOut_zd = 1'bz;\n\n    parameter mem_file_name   = \"none\";\n    parameter otp_blocks_file = \"none\";\n    parameter prot_reg_file   = \"none\";\n    parameter UserPreload     = 1'b0;\n    parameter TimingModel     = \"DefaultTimingModel\";\n    parameter VPP_voltage = 9;    // this parameter specifies if\n                                  // 9V or 2V is applied to Vpp pin\n                                  // (when VPP pin is 1'b1)\n\n    parameter MaxData            = 16'hFFFF;\n    parameter HiAddrBit          = 23;\n    parameter MemSize            = 32'hFFFFFF;\n    parameter BlockNum           = 258;\n    parameter DeviceID_B         = 16'h8922;\n    parameter DeviceID_T         = 16'h891F;\n    parameter MainBlockSize      = 32'h10000;\n    parameter ParameterBlockSize = 32'h04000;\n\n    // If speedsimulation is needed uncomment following line\n\n//       `define SPEEDSIM;\n\n    // FSM states\n    parameter        RESET_POWER_DOWN    = 5'd0;\n    parameter        READY               = 5'd1;\n    parameter        LOCK_SETUP          = 5'd2;\n    parameter        OTP_SETUP           = 5'd3;\n    parameter        OTP_BUSY            = 5'd4;\n    parameter        PROG_SETUP          = 5'd5;\n    parameter        PROG_BUSY           = 5'd6;\n    parameter        PROG_SUSP           = 5'd7;\n    parameter        BP_SETUP            = 5'd8;\n    parameter        BP_LOAD             = 5'd9;\n    parameter        BP_CONFIRM          = 5'd10;\n    parameter        BP_BUSY             = 5'd11;\n    parameter        BP_SUSP             = 5'd12;\n    parameter        ERASE_SETUP         = 5'd13;\n    parameter        ERASE_BUSY          = 5'd14;\n    parameter        ERS_SUSP            = 5'd15;\n    parameter        PROG_SETUP_ERS_SUSP = 5'd16;\n    parameter        PROG_BUSY_ERS_SUSP  = 5'd17;\n    parameter        PROG_SUSP_ERS_SUSP  = 5'd18;\n    parameter        BP_SETUP_ERS_SUSP   = 5'd19;\n    parameter        BP_LOAD_ERS_SUSP    = 5'd20;\n    parameter        BP_CONFIRM_ERS_SUSP = 5'd21;\n    parameter        BP_BUSY_ERS_SUSP    = 5'd22;\n    parameter        BP_SUSP_ERS_SUSP    = 5'd23;\n    parameter        LOCK_SETUP_ERS_SUSP = 5'd24;\n    parameter        BEFP_SETUP          = 5'd25;\n    parameter        BEFP_LOAD           = 5'd26;\n    parameter        BEFP_BUSY           = 5'd27;\n\n    // read mode\n    parameter        READ_ARRAY   = 2'd0;\n    parameter        READ_ID      = 2'd1;\n    parameter        READ_QUERY   = 2'd2;\n    parameter        READ_STATUS  = 2'd3;\n\n    reg [5:0]      current_state;\n    reg [5:0]      next_state;\n\n    reg [1:0]      read_state;\n\n    reg            deq;\n\n    // Memory declaration\n    integer MemData[0:MemSize];\n\n    // internal delays\n    reg WordProgram_in         = 1'b0;\n    reg WordProgram_out        = 1'b0;\n    reg BuffProgram_in         = 1'b0;\n    reg BuffProgram_out        = 1'b0;\n    reg BEFP_in                = 1'b0;\n    reg BEFP_out               = 1'b0;\n    reg BEFPsetup_in           = 1'b0;\n    reg BEFPsetup_out          = 1'b0;\n    reg ParameterErase_in      = 1'b0;\n    reg MainErase_in           = 1'b0;\n    reg ParameterErase_out     = 1'b0;\n    reg MainErase_out          = 1'b0;\n    reg ProgramSuspend_in      = 1'b0;\n    reg ProgramSuspend_out     = 1'b0;\n    reg EraseSuspend_in        = 1'b0;\n    reg EraseSuspend_out       = 1'b0;\n    reg RstDuringErsPrg_in     = 1'b0;\n    reg RstDuringErsPrg_out    = 1'b0;\n\n    // event control registers\n    reg falling_edge_ADVNeg = 1'b0;\n    reg falling_edge_RSTNeg = 1'b0;\n    reg falling_edge_BEFPsetup_out = 1'b0;\n    reg falling_edge_BEFP_out = 1'b0;\n    reg falling_edge_Read  = 1'b0;\n    reg falling_edge_OENeg = 1'b0;\n    reg falling_edge_CENeg = 1'b0;\n    reg rising_edge_ADVNeg = 1'b0;\n    reg rising_edge_CLOCK  = 1'b0;\n    reg rising_edge_WENeg  = 1'b0;\n    reg rising_edge_CENeg  = 1'b0;\n    reg rising_edge_RSTNeg = 1'b0;\n    reg rising_edge_Write  = 1'b0;\n    reg rising_edge_Read   = 1'b0;\n    reg RstDuringErsPrg_out_event = 1'b0;\n    reg WordProgram_out_event    = 1'b0;\n    reg abort_event              = 1'b0;\n    reg ProgramSuspend_out_event = 1'b0;\n    reg BuffProgram_out_event    = 1'b0;\n    reg ExtendProgTime_event     = 1'b0;\n    reg ParameterErase_out_event = 1'b0;\n    reg falling_edge_MainErase_out    = 1'b0;\n    reg falling_edge_EraseSuspend_out = 1'b0;\n    reg Ahigh_event           = 1'b0;\n    reg Alow_event            = 1'b0;\n    reg A_event               = 1'b0;\n    reg rising_edge_OENeg     = 1'b0;\n    reg AssertWAITOut_event   = 1'b0;\n    reg DeassertWAITOut_event = 1'b0;\n    reg rising_edge_MainErase_in      = 1'b0;\n    reg rising_edge_ParameterErase_in = 1'b0;\n    reg EraseSuspend_event            = 1'b0;\n    reg rising_edge_MainEraseResume   = 1'b0;\n    reg rising_edge_ParameterEraseResume = 1'b0;\n\n    integer i,j;\n\n    // Bus cycle decode\n    reg CLOCK = 1'b0;\n\n    reg Write = 1'b0;\n    reg Read  = 1'b0;\n\n    reg Pmode = 1'b0;\n\n    // Functional\n    reg abort           = 1'b0;\n\n    reg ExtendProgTime  = 1'b0;\n\n    reg AssertWAITOut   = 1'b0;\n    reg DeassertWAITOut = 1'b0;\n\n    //Block Lock Status\n    parameter UNLOCKED    = 2'd0;\n    parameter LOCKED      = 2'd1;\n    parameter LOCKED_DOWN = 2'd2;\n    integer Block_Lock[BlockNum:0];\n    reg [BlockNum:0] BlockLockBit;\n    reg [BlockNum:0] BlockLockDownBit;\n    reg OTP[0:BlockNum];\n\n    // Status Register\n    reg[7:0]    SR   = 8'b10000000;\n\n    // Read Configuration Register\n    reg[15:0]   RCR   = 16'b1011111111001111;\n\n    // Protection registers\n    integer PR[9'h80:9'h109];\n\n    // CFI array\n    integer CFI_array[9'h10:9'h156];\n\n    reg LATCHED = 1'b0;\n    reg [15:0] LatchedData;\n    reg [HiAddrBit:0] LatchedAddr;\n    integer ReadAddr;\n\n    integer DataBuff[0:31];\n    integer AddrBuff[0:31];\n\n    integer burst_cntr;\n    integer BurstLength;\n    integer BurstDelay;\n    integer DataHold;\n\n    integer WCount;\n    integer word_cntr;\n    integer word_cnt;\n    integer word_number;\n    integer block_number;\n    integer erasing_block;\n\n    integer lowest_addr;\n    integer highest_addr;\n    integer start_addr;\n\n    integer BEFP_addr;\n    integer BEFP_block;\n    integer BEFP_block2;\n\n    reg [15:0] mem_bits;\n    reg [15:0] prog_bits;\n\n    reg [15:0] DQOut_tmp;\n    reg read_out = 1'b0;\n\n    reg suspended_bp = 1'b0;\n    reg suspended_erase = 1'b0;\n\n    reg aborted ;\n    integer block_size;\n\n    reg ParameterEraseResume;\n    reg MainEraseResume;\n    reg WordProgramResume;\n    reg BP_ProgramResume;\n    time merase_duration;\n    time perase_duration;\n    time melapsed;\n    time pelapsed;\n    time mstart;\n    time pstart;\n    event merase_event;\n    event perase_event;\n\n    // timing check violation\n    reg Viol = 1'b0;\n\n    //TPD_XX_DATA\n    time           OEDQ_t;\n    time           CEDQ_t;\n    time           ADDRDQ_t;\n    time           OENeg_event;\n    time           CENeg_event;\n    time           ADDR_event;\n    reg            FROMOE;\n    reg            FROMCE;\n    reg            FROMADDR;\n    reg            OPENLATCH;\n    integer        OEDQ_01;\n    integer        CEDQ_01;\n    integer        ADDRDQIN_01;\n    integer        ADDRDQPAGE_01;\n    reg [15:0]     TempData;\n\n    wire InitialPageAccess;\n    assign InitialPageAccess = FROMADDR && ~Pmode;\n\n    wire SubsequentPageAccess;\n    assign SubsequentPageAccess = FROMADDR && Pmode;\n\n    wire CLK_rising;\n    assign CLK_rising = RCR[6] && ~CENeg_ipd;\n\n    wire CLK_falling;\n    assign CLK_falling = ~(RCR[6]) && ~CENeg_ipd;\n\n///////////////////////////////////////////////////////////////////////////////\n//Interconnect Path Delay Section\n///////////////////////////////////////////////////////////////////////////////\n    buf   (A24_ipd, A24);\n    buf   (A23_ipd, A23);\n    buf   (A22_ipd, A22);\n    buf   (A21_ipd, A21);\n    buf   (A20_ipd, A20);\n    buf   (A19_ipd, A19);\n    buf   (A18_ipd, A18);\n    buf   (A17_ipd, A17);\n    buf   (A16_ipd, A16);\n    buf   (A15_ipd, A15);\n    buf   (A14_ipd, A14);\n    buf   (A13_ipd, A13);\n    buf   (A12_ipd, A12);\n    buf   (A11_ipd, A11);\n    buf   (A10_ipd, A10);\n    buf   (A9_ipd , A9 );\n    buf   (A8_ipd , A8 );\n    buf   (A7_ipd , A7 );\n    buf   (A6_ipd , A6 );\n    buf   (A5_ipd , A5 );\n    buf   (A4_ipd , A4 );\n    buf   (A3_ipd , A3 );\n    buf   (A2_ipd , A2 );\n    buf   (A1_ipd , A1 );\n\n    buf   (DQ15_ipd, DQ15);\n    buf   (DQ14_ipd, DQ14);\n    buf   (DQ13_ipd, DQ13);\n    buf   (DQ12_ipd, DQ12);\n    buf   (DQ11_ipd, DQ11);\n    buf   (DQ10_ipd, DQ10);\n    buf   (DQ9_ipd , DQ9 );\n    buf   (DQ8_ipd , DQ8 );\n    buf   (DQ7_ipd , DQ7 );\n    buf   (DQ6_ipd , DQ6 );\n    buf   (DQ5_ipd , DQ5 );\n    buf   (DQ4_ipd , DQ4 );\n    buf   (DQ3_ipd , DQ3 );\n    buf   (DQ2_ipd , DQ2 );\n    buf   (DQ1_ipd , DQ1 );\n    buf   (DQ0_ipd , DQ0 );\n\n    buf   (RSTNeg_ipd , RSTNeg );\n    buf   (ADVNeg_ipd , ADVNeg );\n    buf   (CLK_ipd    , CLK );\n    buf   (CENeg_ipd  , CENeg );\n    buf   (OENeg_ipd  , OENeg );\n    buf   (WENeg_ipd  , WENeg );\n    buf   (WPNeg_ipd  , WPNeg );\n\n///////////////////////////////////////////////////////////////////////////////\n// Propagation  delay Section\n///////////////////////////////////////////////////////////////////////////////\n    nmos   (DQ15,   DQ15_Pass , 1);\n    nmos   (DQ14,   DQ14_Pass , 1);\n    nmos   (DQ13,   DQ13_Pass , 1);\n    nmos   (DQ12,   DQ12_Pass , 1);\n    nmos   (DQ11,   DQ11_Pass , 1);\n    nmos   (DQ10,   DQ10_Pass , 1);\n    nmos   (DQ9 ,   DQ9_Pass  , 1);\n    nmos   (DQ8 ,   DQ8_Pass  , 1);\n    nmos   (DQ7 ,   DQ7_Pass  , 1);\n    nmos   (DQ6 ,   DQ6_Pass  , 1);\n    nmos   (DQ5 ,   DQ5_Pass  , 1);\n    nmos   (DQ4 ,   DQ4_Pass  , 1);\n    nmos   (DQ3 ,   DQ3_Pass  , 1);\n    nmos   (DQ2 ,   DQ2_Pass  , 1);\n    nmos   (DQ1 ,   DQ1_Pass  , 1);\n    nmos   (DQ0 ,   DQ0_Pass  , 1);\n\n    nmos   (WAITOut, WAITOut_zd, 1);\n\n    wire deg;\n\nspecify\n    // tipd delays: interconnect path delays , mapped to input port delays.\n    // In Verilog is not necessary to declare any tipd_ delay variables,\n    // they can be taken from SDF file\n    // With all the other delays real delays would be taken from SDF file\n\n    // tpd delays\n    specparam           tpd_A1_DQ0             =1;\n    specparam           tpd_A1_DQ1             =1;\n    specparam           tpd_A1_DQ2             =1;\n    specparam           tpd_A1_DQ3             =1;\n    specparam           tpd_A1_DQ4             =1;\n    specparam           tpd_A1_DQ5             =1;\n    specparam           tpd_A1_DQ6             =1;\n    specparam           tpd_A1_DQ7             =1;\n    specparam           tpd_A1_DQ8             =1;\n    specparam           tpd_A1_DQ9             =1;\n    specparam           tpd_A1_DQ10            =1;\n    specparam           tpd_A1_DQ11            =1;\n    specparam           tpd_A1_DQ12            =1;\n    specparam           tpd_A1_DQ13            =1;\n    specparam           tpd_A1_DQ14            =1;\n    specparam           tpd_A1_DQ15            =1;\n    specparam           tpd_A2_DQ0             =1;\n    specparam           tpd_A2_DQ1             =1;\n    specparam           tpd_A2_DQ2             =1;\n    specparam           tpd_A2_DQ3             =1;\n    specparam           tpd_A2_DQ4             =1;\n    specparam           tpd_A2_DQ5             =1;\n    specparam           tpd_A2_DQ6             =1;\n    specparam           tpd_A2_DQ7             =1;\n    specparam           tpd_A2_DQ8             =1;\n    specparam           tpd_A2_DQ9             =1;\n    specparam           tpd_A2_DQ10            =1;\n    specparam           tpd_A2_DQ11            =1;\n    specparam           tpd_A2_DQ12            =1;\n    specparam           tpd_A2_DQ13            =1;\n    specparam           tpd_A2_DQ14            =1;\n    specparam           tpd_A2_DQ15            =1;\n    specparam           tpd_A3_DQ0             =1;\n    specparam           tpd_A3_DQ1             =1;\n    specparam           tpd_A3_DQ2             =1;\n    specparam           tpd_A3_DQ3             =1;\n    specparam           tpd_A3_DQ4             =1;\n    specparam           tpd_A3_DQ5             =1;\n    specparam           tpd_A3_DQ6             =1;\n    specparam           tpd_A3_DQ7             =1;\n    specparam           tpd_A3_DQ8             =1;\n    specparam           tpd_A3_DQ9             =1;\n    specparam           tpd_A3_DQ10            =1;\n    specparam           tpd_A3_DQ11            =1;\n    specparam           tpd_A3_DQ12            =1;\n    specparam           tpd_A3_DQ13            =1;\n    specparam           tpd_A3_DQ14            =1;\n    specparam           tpd_A3_DQ15            =1;\n    specparam           tpd_A4_DQ0             =1;\n    specparam           tpd_A4_DQ1             =1;\n    specparam           tpd_A4_DQ2             =1;\n    specparam           tpd_A4_DQ3             =1;\n    specparam           tpd_A4_DQ4             =1;\n    specparam           tpd_A4_DQ5             =1;\n    specparam           tpd_A4_DQ6             =1;\n    specparam           tpd_A4_DQ7             =1;\n    specparam           tpd_A4_DQ8             =1;\n    specparam           tpd_A4_DQ9             =1;\n    specparam           tpd_A4_DQ10            =1;\n    specparam           tpd_A4_DQ11            =1;\n    specparam           tpd_A4_DQ12            =1;\n    specparam           tpd_A4_DQ13            =1;\n    specparam           tpd_A4_DQ14            =1;\n    specparam           tpd_A4_DQ15            =1;\n    specparam           tpd_A5_DQ0             =1;\n    specparam           tpd_A5_DQ1             =1;\n    specparam           tpd_A5_DQ2             =1;\n    specparam           tpd_A5_DQ3             =1;\n    specparam           tpd_A5_DQ4             =1;\n    specparam           tpd_A5_DQ5             =1;\n    specparam           tpd_A5_DQ6             =1;\n    specparam           tpd_A5_DQ7             =1;\n    specparam           tpd_A5_DQ8             =1;\n    specparam           tpd_A5_DQ9             =1;\n    specparam           tpd_A5_DQ10            =1;\n    specparam           tpd_A5_DQ11            =1;\n    specparam           tpd_A5_DQ12            =1;\n    specparam           tpd_A5_DQ13            =1;\n    specparam           tpd_A5_DQ14            =1;\n    specparam           tpd_A5_DQ15            =1;\n    specparam           tpd_A6_DQ0             =1;\n    specparam           tpd_A6_DQ1             =1;\n    specparam           tpd_A6_DQ2             =1;\n    specparam           tpd_A6_DQ3             =1;\n    specparam           tpd_A6_DQ4             =1;\n    specparam           tpd_A6_DQ5             =1;\n    specparam           tpd_A6_DQ6             =1;\n    specparam           tpd_A6_DQ7             =1;\n    specparam           tpd_A6_DQ8             =1;\n    specparam           tpd_A6_DQ9             =1;\n    specparam           tpd_A6_DQ10            =1;\n    specparam           tpd_A6_DQ11            =1;\n    specparam           tpd_A6_DQ12            =1;\n    specparam           tpd_A6_DQ13            =1;\n    specparam           tpd_A6_DQ14            =1;\n    specparam           tpd_A6_DQ15            =1;\n    specparam           tpd_A7_DQ0             =1;\n    specparam           tpd_A7_DQ1             =1;\n    specparam           tpd_A7_DQ2             =1;\n    specparam           tpd_A7_DQ3             =1;\n    specparam           tpd_A7_DQ4             =1;\n    specparam           tpd_A7_DQ5             =1;\n    specparam           tpd_A7_DQ6             =1;\n    specparam           tpd_A7_DQ7             =1;\n    specparam           tpd_A7_DQ8             =1;\n    specparam           tpd_A7_DQ9             =1;\n    specparam           tpd_A7_DQ10            =1;\n    specparam           tpd_A7_DQ11            =1;\n    specparam           tpd_A7_DQ12            =1;\n    specparam           tpd_A7_DQ13            =1;\n    specparam           tpd_A7_DQ14            =1;\n    specparam           tpd_A7_DQ15            =1;\n    specparam           tpd_A8_DQ0             =1;\n    specparam           tpd_A8_DQ1             =1;\n    specparam           tpd_A8_DQ2             =1;\n    specparam           tpd_A8_DQ3             =1;\n    specparam           tpd_A8_DQ4             =1;\n    specparam           tpd_A8_DQ5             =1;\n    specparam           tpd_A8_DQ6             =1;\n    specparam           tpd_A8_DQ7             =1;\n    specparam           tpd_A8_DQ8             =1;\n    specparam           tpd_A8_DQ9             =1;\n    specparam           tpd_A8_DQ10            =1;\n    specparam           tpd_A8_DQ11            =1;\n    specparam           tpd_A8_DQ12            =1;\n    specparam           tpd_A8_DQ13            =1;\n    specparam           tpd_A8_DQ14            =1;\n    specparam           tpd_A8_DQ15            =1;\n    specparam           tpd_A9_DQ0             =1;\n    specparam           tpd_A9_DQ1             =1;\n    specparam           tpd_A9_DQ2             =1;\n    specparam           tpd_A9_DQ3             =1;\n    specparam           tpd_A9_DQ4             =1;\n    specparam           tpd_A9_DQ5             =1;\n    specparam           tpd_A9_DQ6             =1;\n    specparam           tpd_A9_DQ7             =1;\n    specparam           tpd_A9_DQ8             =1;\n    specparam           tpd_A9_DQ9             =1;\n    specparam           tpd_A9_DQ10            =1;\n    specparam           tpd_A9_DQ11            =1;\n    specparam           tpd_A9_DQ12            =1;\n    specparam           tpd_A9_DQ13            =1;\n    specparam           tpd_A9_DQ14            =1;\n    specparam           tpd_A9_DQ15            =1;\n    specparam           tpd_A10_DQ0            =1;\n    specparam           tpd_A10_DQ1            =1;\n    specparam           tpd_A10_DQ2            =1;\n    specparam           tpd_A10_DQ3            =1;\n    specparam           tpd_A10_DQ4            =1;\n    specparam           tpd_A10_DQ5            =1;\n    specparam           tpd_A10_DQ6            =1;\n    specparam           tpd_A10_DQ7            =1;\n    specparam           tpd_A10_DQ8            =1;\n    specparam           tpd_A10_DQ9            =1;\n    specparam           tpd_A10_DQ10           =1;\n    specparam           tpd_A10_DQ11           =1;\n    specparam           tpd_A10_DQ12           =1;\n    specparam           tpd_A10_DQ13           =1;\n    specparam           tpd_A10_DQ14           =1;\n    specparam           tpd_A10_DQ15           =1;\n    specparam           tpd_A11_DQ0            =1;\n    specparam           tpd_A11_DQ1            =1;\n    specparam           tpd_A11_DQ2            =1;\n    specparam           tpd_A11_DQ3            =1;\n    specparam           tpd_A11_DQ4            =1;\n    specparam           tpd_A11_DQ5            =1;\n    specparam           tpd_A11_DQ6            =1;\n    specparam           tpd_A11_DQ7            =1;\n    specparam           tpd_A11_DQ8            =1;\n    specparam           tpd_A11_DQ9            =1;\n    specparam           tpd_A11_DQ10           =1;\n    specparam           tpd_A11_DQ11           =1;\n    specparam           tpd_A11_DQ12           =1;\n    specparam           tpd_A11_DQ13           =1;\n    specparam           tpd_A11_DQ14           =1;\n    specparam           tpd_A11_DQ15           =1;\n    specparam           tpd_A12_DQ0            =1;\n    specparam           tpd_A12_DQ1            =1;\n    specparam           tpd_A12_DQ2            =1;\n    specparam           tpd_A12_DQ3            =1;\n    specparam           tpd_A12_DQ4            =1;\n    specparam           tpd_A12_DQ5            =1;\n    specparam           tpd_A12_DQ6            =1;\n    specparam           tpd_A12_DQ7            =1;\n    specparam           tpd_A12_DQ8            =1;\n    specparam           tpd_A12_DQ9            =1;\n    specparam           tpd_A12_DQ10           =1;\n    specparam           tpd_A12_DQ11           =1;\n    specparam           tpd_A12_DQ12           =1;\n    specparam           tpd_A12_DQ13           =1;\n    specparam           tpd_A12_DQ14           =1;\n    specparam           tpd_A12_DQ15           =1;\n    specparam           tpd_A13_DQ0            =1;\n    specparam           tpd_A13_DQ1            =1;\n    specparam           tpd_A13_DQ2            =1;\n    specparam           tpd_A13_DQ3            =1;\n    specparam           tpd_A13_DQ4            =1;\n    specparam           tpd_A13_DQ5            =1;\n    specparam           tpd_A13_DQ6            =1;\n    specparam           tpd_A13_DQ7            =1;\n    specparam           tpd_A13_DQ8            =1;\n    specparam           tpd_A13_DQ9            =1;\n    specparam           tpd_A13_DQ10           =1;\n    specparam           tpd_A13_DQ11           =1;\n    specparam           tpd_A13_DQ12           =1;\n    specparam           tpd_A13_DQ13           =1;\n    specparam           tpd_A13_DQ14           =1;\n    specparam           tpd_A13_DQ15           =1;\n    specparam           tpd_A14_DQ0            =1;\n    specparam           tpd_A14_DQ1            =1;\n    specparam           tpd_A14_DQ2            =1;\n    specparam           tpd_A14_DQ3            =1;\n    specparam           tpd_A14_DQ4            =1;\n    specparam           tpd_A14_DQ5            =1;\n    specparam           tpd_A14_DQ6            =1;\n    specparam           tpd_A14_DQ7            =1;\n    specparam           tpd_A14_DQ8            =1;\n    specparam           tpd_A14_DQ9            =1;\n    specparam           tpd_A14_DQ10           =1;\n    specparam           tpd_A14_DQ11           =1;\n    specparam           tpd_A14_DQ12           =1;\n    specparam           tpd_A14_DQ13           =1;\n    specparam           tpd_A14_DQ14           =1;\n    specparam           tpd_A14_DQ15           =1;\n    specparam           tpd_A15_DQ0            =1;\n    specparam           tpd_A15_DQ1            =1;\n    specparam           tpd_A15_DQ2            =1;\n    specparam           tpd_A15_DQ3            =1;\n    specparam           tpd_A15_DQ4            =1;\n    specparam           tpd_A15_DQ5            =1;\n    specparam           tpd_A15_DQ6            =1;\n    specparam           tpd_A15_DQ7            =1;\n    specparam           tpd_A15_DQ8            =1;\n    specparam           tpd_A15_DQ9            =1;\n    specparam           tpd_A15_DQ10           =1;\n    specparam           tpd_A15_DQ11           =1;\n    specparam           tpd_A15_DQ12           =1;\n    specparam           tpd_A15_DQ13           =1;\n    specparam           tpd_A15_DQ14           =1;\n    specparam           tpd_A15_DQ15           =1;\n    specparam           tpd_A16_DQ0            =1;\n    specparam           tpd_A16_DQ1            =1;\n    specparam           tpd_A16_DQ2            =1;\n    specparam           tpd_A16_DQ3            =1;\n    specparam           tpd_A16_DQ4            =1;\n    specparam           tpd_A16_DQ5            =1;\n    specparam           tpd_A16_DQ6            =1;\n    specparam           tpd_A16_DQ7            =1;\n    specparam           tpd_A16_DQ8            =1;\n    specparam           tpd_A16_DQ9            =1;\n    specparam           tpd_A16_DQ10           =1;\n    specparam           tpd_A16_DQ11           =1;\n    specparam           tpd_A16_DQ12           =1;\n    specparam           tpd_A16_DQ13           =1;\n    specparam           tpd_A16_DQ14           =1;\n    specparam           tpd_A16_DQ15           =1;\n    specparam           tpd_A17_DQ0            =1;\n    specparam           tpd_A17_DQ1            =1;\n    specparam           tpd_A17_DQ2            =1;\n    specparam           tpd_A17_DQ3            =1;\n    specparam           tpd_A17_DQ4            =1;\n    specparam           tpd_A17_DQ5            =1;\n    specparam           tpd_A17_DQ6            =1;\n    specparam           tpd_A17_DQ7            =1;\n    specparam           tpd_A17_DQ8            =1;\n    specparam           tpd_A17_DQ9            =1;\n    specparam           tpd_A17_DQ10           =1;\n    specparam           tpd_A17_DQ11           =1;\n    specparam           tpd_A17_DQ12           =1;\n    specparam           tpd_A17_DQ13           =1;\n    specparam           tpd_A17_DQ14           =1;\n    specparam           tpd_A17_DQ15           =1;\n    specparam           tpd_A18_DQ0            =1;\n    specparam           tpd_A18_DQ1            =1;\n    specparam           tpd_A18_DQ2            =1;\n    specparam           tpd_A18_DQ3            =1;\n    specparam           tpd_A18_DQ4            =1;\n    specparam           tpd_A18_DQ5            =1;\n    specparam           tpd_A18_DQ6            =1;\n    specparam           tpd_A18_DQ7            =1;\n    specparam           tpd_A18_DQ8            =1;\n    specparam           tpd_A18_DQ9            =1;\n    specparam           tpd_A18_DQ10           =1;\n    specparam           tpd_A18_DQ11           =1;\n    specparam           tpd_A18_DQ12           =1;\n    specparam           tpd_A18_DQ13           =1;\n    specparam           tpd_A18_DQ14           =1;\n    specparam           tpd_A18_DQ15           =1;\n    specparam           tpd_A19_DQ0            =1;\n    specparam           tpd_A19_DQ1            =1;\n    specparam           tpd_A19_DQ2            =1;\n    specparam           tpd_A19_DQ3            =1;\n    specparam           tpd_A19_DQ4            =1;\n    specparam           tpd_A19_DQ5            =1;\n    specparam           tpd_A19_DQ6            =1;\n    specparam           tpd_A19_DQ7            =1;\n    specparam           tpd_A19_DQ8            =1;\n    specparam           tpd_A19_DQ9            =1;\n    specparam           tpd_A19_DQ10           =1;\n    specparam           tpd_A19_DQ11           =1;\n    specparam           tpd_A19_DQ12           =1;\n    specparam           tpd_A19_DQ13           =1;\n    specparam           tpd_A19_DQ14           =1;\n    specparam           tpd_A19_DQ15           =1;\n    specparam           tpd_A20_DQ0            =1;\n    specparam           tpd_A20_DQ1            =1;\n    specparam           tpd_A20_DQ2            =1;\n    specparam           tpd_A20_DQ3            =1;\n    specparam           tpd_A20_DQ4            =1;\n    specparam           tpd_A20_DQ5            =1;\n    specparam           tpd_A20_DQ6            =1;\n    specparam           tpd_A20_DQ7            =1;\n    specparam           tpd_A20_DQ8            =1;\n    specparam           tpd_A20_DQ9            =1;\n    specparam           tpd_A20_DQ10           =1;\n    specparam           tpd_A20_DQ11           =1;\n    specparam           tpd_A20_DQ12           =1;\n    specparam           tpd_A20_DQ13           =1;\n    specparam           tpd_A20_DQ14           =1;\n    specparam           tpd_A20_DQ15           =1;\n    specparam           tpd_A21_DQ0            =1;\n    specparam           tpd_A21_DQ1            =1;\n    specparam           tpd_A21_DQ2            =1;\n    specparam           tpd_A21_DQ3            =1;\n    specparam           tpd_A21_DQ4            =1;\n    specparam           tpd_A21_DQ5            =1;\n    specparam           tpd_A21_DQ6            =1;\n    specparam           tpd_A21_DQ7            =1;\n    specparam           tpd_A21_DQ8            =1;\n    specparam           tpd_A21_DQ9            =1;\n    specparam           tpd_A21_DQ10           =1;\n    specparam           tpd_A21_DQ11           =1;\n    specparam           tpd_A21_DQ12           =1;\n    specparam           tpd_A21_DQ13           =1;\n    specparam           tpd_A21_DQ14           =1;\n    specparam           tpd_A21_DQ15           =1;\n    specparam           tpd_A22_DQ0            =1;\n    specparam           tpd_A22_DQ1            =1;\n    specparam           tpd_A22_DQ2            =1;\n    specparam           tpd_A22_DQ3            =1;\n    specparam           tpd_A22_DQ4            =1;\n    specparam           tpd_A22_DQ5            =1;\n    specparam           tpd_A22_DQ6            =1;\n    specparam           tpd_A22_DQ7            =1;\n    specparam           tpd_A22_DQ8            =1;\n    specparam           tpd_A22_DQ9            =1;\n    specparam           tpd_A22_DQ10           =1;\n    specparam           tpd_A22_DQ11           =1;\n    specparam           tpd_A22_DQ12           =1;\n    specparam           tpd_A22_DQ13           =1;\n    specparam           tpd_A22_DQ14           =1;\n    specparam           tpd_A22_DQ15           =1;\n    specparam           tpd_A23_DQ0            =1;\n    specparam           tpd_A23_DQ1            =1;\n    specparam           tpd_A23_DQ2            =1;\n    specparam           tpd_A23_DQ3            =1;\n    specparam           tpd_A23_DQ4            =1;\n    specparam           tpd_A23_DQ5            =1;\n    specparam           tpd_A23_DQ6            =1;\n    specparam           tpd_A23_DQ7            =1;\n    specparam           tpd_A23_DQ8            =1;\n    specparam           tpd_A23_DQ9            =1;\n    specparam           tpd_A23_DQ10           =1;\n    specparam           tpd_A23_DQ11           =1;\n    specparam           tpd_A23_DQ12           =1;\n    specparam           tpd_A23_DQ13           =1;\n    specparam           tpd_A23_DQ14           =1;\n    specparam           tpd_A23_DQ15           =1;\n    specparam           tpd_A24_DQ0            =1;\n    specparam           tpd_A24_DQ1            =1;\n    specparam           tpd_A24_DQ2            =1;\n    specparam           tpd_A24_DQ3            =1;\n    specparam           tpd_A24_DQ4            =1;\n    specparam           tpd_A24_DQ5            =1;\n    specparam           tpd_A24_DQ6            =1;\n    specparam           tpd_A24_DQ7            =1;\n    specparam           tpd_A24_DQ8            =1;\n    specparam           tpd_A24_DQ9            =1;\n    specparam           tpd_A24_DQ10           =1;\n    specparam           tpd_A24_DQ11           =1;\n    specparam           tpd_A24_DQ12           =1;\n    specparam           tpd_A24_DQ13           =1;\n    specparam           tpd_A24_DQ14           =1;\n    specparam           tpd_A24_DQ15           =1;\n\n    specparam           tpd_CENeg_DQ0           =1;\n    specparam           tpd_CENeg_DQ1           =1;\n    specparam           tpd_CENeg_DQ2           =1;\n    specparam           tpd_CENeg_DQ3           =1;\n    specparam           tpd_CENeg_DQ4           =1;\n    specparam           tpd_CENeg_DQ5           =1;\n    specparam           tpd_CENeg_DQ6           =1;\n    specparam           tpd_CENeg_DQ7           =1;\n    specparam           tpd_CENeg_DQ8           =1;\n    specparam           tpd_CENeg_DQ9           =1;\n    specparam           tpd_CENeg_DQ10          =1;\n    specparam           tpd_CENeg_DQ11          =1;\n    specparam           tpd_CENeg_DQ12          =1;\n    specparam           tpd_CENeg_DQ13          =1;\n    specparam           tpd_CENeg_DQ14          =1;\n    specparam           tpd_CENeg_DQ15          =1;\n\n    specparam           tpd_OENeg_DQ0           =1;\n    specparam           tpd_OENeg_DQ1           =1;\n    specparam           tpd_OENeg_DQ2           =1;\n    specparam           tpd_OENeg_DQ3           =1;\n    specparam           tpd_OENeg_DQ4           =1;\n    specparam           tpd_OENeg_DQ5           =1;\n    specparam           tpd_OENeg_DQ6           =1;\n    specparam           tpd_OENeg_DQ7           =1;\n    specparam           tpd_OENeg_DQ8           =1;\n    specparam           tpd_OENeg_DQ9           =1;\n    specparam           tpd_OENeg_DQ10          =1;\n    specparam           tpd_OENeg_DQ11          =1;\n    specparam           tpd_OENeg_DQ12          =1;\n    specparam           tpd_OENeg_DQ13          =1;\n    specparam           tpd_OENeg_DQ14          =1;\n    specparam           tpd_OENeg_DQ15          =1;\n\n    specparam           tpd_CLK_DQ0              =1;\n    specparam           tpd_CLK_DQ1              =1;\n    specparam           tpd_CLK_DQ2              =1;\n    specparam           tpd_CLK_DQ3              =1;\n    specparam           tpd_CLK_DQ4              =1;\n    specparam           tpd_CLK_DQ5              =1;\n    specparam           tpd_CLK_DQ6              =1;\n    specparam           tpd_CLK_DQ7              =1;\n    specparam           tpd_CLK_DQ8              =1;\n    specparam           tpd_CLK_DQ9              =1;\n    specparam           tpd_CLK_DQ10             =1;\n    specparam           tpd_CLK_DQ11             =1;\n    specparam           tpd_CLK_DQ12             =1;\n    specparam           tpd_CLK_DQ13             =1;\n    specparam           tpd_CLK_DQ14             =1;\n    specparam           tpd_CLK_DQ15             =1;\n\n    specparam           tpd_CE0Neg_WAITOut       =1;\n    specparam           tpd_OE0Neg_WAITOut       =1;\n    specparam           tpd_CLK_WAITOut          =1;\n\n    //tsetup values\n    specparam           tsetup_A1_ADVNeg               =1;\n    specparam           tsetup_A2_ADVNeg               =1;\n    specparam           tsetup_A3_ADVNeg               =1;\n    specparam           tsetup_A4_ADVNeg               =1;\n    specparam           tsetup_A5_ADVNeg               =1;\n    specparam           tsetup_A6_ADVNeg               =1;\n    specparam           tsetup_A7_ADVNeg               =1;\n    specparam           tsetup_A8_ADVNeg               =1;\n    specparam           tsetup_A9_ADVNeg               =1;\n    specparam           tsetup_A10_ADVNeg              =1;\n    specparam           tsetup_A11_ADVNeg              =1;\n    specparam           tsetup_A12_ADVNeg              =1;\n    specparam           tsetup_A13_ADVNeg              =1;\n    specparam           tsetup_A14_ADVNeg              =1;\n    specparam           tsetup_A15_ADVNeg              =1;\n    specparam           tsetup_A16_ADVNeg              =1;\n    specparam           tsetup_A17_ADVNeg              =1;\n    specparam           tsetup_A18_ADVNeg              =1;\n    specparam           tsetup_A19_ADVNeg              =1;\n    specparam           tsetup_A20_ADVNeg              =1;\n    specparam           tsetup_A21_ADVNeg              =1;\n    specparam           tsetup_A22_ADVNeg              =1;\n    specparam           tsetup_A23_ADVNeg              =1;\n    specparam           tsetup_A24_ADVNeg              =1;\n\n    specparam           tsetup_CENeg_ADVNeg            =1;\n    specparam           tsetup_RSTNeg_ADVNeg           =1;\n    specparam           tsetup_CLK_ADVNeg              =1;\n    specparam           tsetup_WENeg_ADVNeg            =1;\n\n    specparam           tsetup_A1_CLK                  =1;\n    specparam           tsetup_A2_CLK                  =1;\n    specparam           tsetup_A3_CLK                  =1;\n    specparam           tsetup_A4_CLK                  =1;\n    specparam           tsetup_A5_CLK                  =1;\n    specparam           tsetup_A6_CLK                  =1;\n    specparam           tsetup_A7_CLK                  =1;\n    specparam           tsetup_A8_CLK                  =1;\n    specparam           tsetup_A9_CLK                  =1;\n    specparam           tsetup_A10_CLK                 =1;\n    specparam           tsetup_A11_CLK                 =1;\n    specparam           tsetup_A12_CLK                 =1;\n    specparam           tsetup_A13_CLK                 =1;\n    specparam           tsetup_A14_CLK                 =1;\n    specparam           tsetup_A15_CLK                 =1;\n    specparam           tsetup_A16_CLK                 =1;\n    specparam           tsetup_A17_CLK                 =1;\n    specparam           tsetup_A18_CLK                 =1;\n    specparam           tsetup_A19_CLK                 =1;\n    specparam           tsetup_A20_CLK                 =1;\n    specparam           tsetup_A21_CLK                 =1;\n    specparam           tsetup_A22_CLK                 =1;\n    specparam           tsetup_A23_CLK                 =1;\n    specparam           tsetup_A24_CLK                 =1;\n\n    specparam           tsetup_ADVNeg_CLK              =1;\n    specparam           tsetup_CENeg_CLK               =1;\n    specparam           tsetup_WENeg_CLK               =1;\n\n    specparam           tsetup_CENeg_WENeg             =1;\n\n    specparam           tsetup_DQ0_WENeg               =1;\n    specparam           tsetup_DQ1_WENeg               =1;\n    specparam           tsetup_DQ2_WENeg               =1;\n    specparam           tsetup_DQ3_WENeg               =1;\n    specparam           tsetup_DQ4_WENeg               =1;\n    specparam           tsetup_DQ5_WENeg               =1;\n    specparam           tsetup_DQ6_WENeg               =1;\n    specparam           tsetup_DQ7_WENeg               =1;\n    specparam           tsetup_DQ8_WENeg               =1;\n    specparam           tsetup_DQ9_WENeg               =1;\n    specparam           tsetup_DQ10_WENeg              =1;\n    specparam           tsetup_DQ11_WENeg              =1;\n    specparam           tsetup_DQ12_WENeg              =1;\n    specparam           tsetup_DQ13_WENeg              =1;\n    specparam           tsetup_DQ14_WENeg              =1;\n    specparam           tsetup_DQ15_WENeg              =1;\n\n    specparam           tsetup_A1_WENeg                =1;\n    specparam           tsetup_A2_WENeg                =1;\n    specparam           tsetup_A3_WENeg                =1;\n    specparam           tsetup_A4_WENeg                =1;\n    specparam           tsetup_A5_WENeg                =1;\n    specparam           tsetup_A6_WENeg                =1;\n    specparam           tsetup_A7_WENeg                =1;\n    specparam           tsetup_A8_WENeg                =1;\n    specparam           tsetup_A9_WENeg                =1;\n    specparam           tsetup_A10_WENeg               =1;\n    specparam           tsetup_A11_WENeg               =1;\n    specparam           tsetup_A12_WENeg               =1;\n    specparam           tsetup_A13_WENeg               =1;\n    specparam           tsetup_A14_WENeg               =1;\n    specparam           tsetup_A15_WENeg               =1;\n    specparam           tsetup_A16_WENeg               =1;\n    specparam           tsetup_A17_WENeg               =1;\n    specparam           tsetup_A18_WENeg               =1;\n    specparam           tsetup_A19_WENeg               =1;\n    specparam           tsetup_A20_WENeg               =1;\n    specparam           tsetup_A21_WENeg               =1;\n    specparam           tsetup_A22_WENeg               =1;\n    specparam           tsetup_A23_WENeg               =1;\n    specparam           tsetup_A24_WENeg               =1;\n\n    specparam           tsetup_WPNeg_WENeg             =1;\n    specparam           tsetup_ADVNeg_WENeg            =1;\n    specparam           tsetup_CLK_WENeg               =1;\n\n    specparam           tsetup_WENeg_OENeg             =1;\n\n    // thold values: hold times\n    specparam           thold_A1_ADVNeg                =1;\n    specparam           thold_A2_ADVNeg                =1;\n    specparam           thold_A3_ADVNeg                =1;\n    specparam           thold_A4_ADVNeg                =1;\n    specparam           thold_A5_ADVNeg                =1;\n    specparam           thold_A6_ADVNeg                =1;\n    specparam           thold_A7_ADVNeg                =1;\n    specparam           thold_A8_ADVNeg                =1;\n    specparam           thold_A9_ADVNeg                =1;\n    specparam           thold_A10_ADVNeg               =1;\n    specparam           thold_A11_ADVNeg               =1;\n    specparam           thold_A12_ADVNeg               =1;\n    specparam           thold_A13_ADVNeg               =1;\n    specparam           thold_A14_ADVNeg               =1;\n    specparam           thold_A15_ADVNeg               =1;\n    specparam           thold_A16_ADVNeg               =1;\n    specparam           thold_A17_ADVNeg               =1;\n    specparam           thold_A18_ADVNeg               =1;\n    specparam           thold_A19_ADVNeg               =1;\n    specparam           thold_A20_ADVNeg               =1;\n    specparam           thold_A21_ADVNeg               =1;\n    specparam           thold_A22_ADVNeg               =1;\n    specparam           thold_A23_ADVNeg               =1;\n    specparam           thold_A24_ADVNeg               =1;\n\n    specparam           thold_A1_CLK                   =1;\n    specparam           thold_A2_CLK                   =1;\n    specparam           thold_A3_CLK                   =1;\n    specparam           thold_A4_CLK                   =1;\n    specparam           thold_A5_CLK                   =1;\n    specparam           thold_A6_CLK                   =1;\n    specparam           thold_A7_CLK                   =1;\n    specparam           thold_A8_CLK                   =1;\n    specparam           thold_A9_CLK                   =1;\n    specparam           thold_A10_CLK                  =1;\n    specparam           thold_A11_CLK                  =1;\n    specparam           thold_A12_CLK                  =1;\n    specparam           thold_A13_CLK                  =1;\n    specparam           thold_A14_CLK                  =1;\n    specparam           thold_A15_CLK                  =1;\n    specparam           thold_A16_CLK                  =1;\n    specparam           thold_A17_CLK                  =1;\n    specparam           thold_A18_CLK                  =1;\n    specparam           thold_A19_CLK                  =1;\n    specparam           thold_A20_CLK                  =1;\n    specparam           thold_A21_CLK                  =1;\n    specparam           thold_A22_CLK                  =1;\n    specparam           thold_A23_CLK                  =1;\n    specparam           thold_A24_CLK                  =1;\n\n    specparam           thold_CENeg_WENeg              =1;\n\n    specparam           thold_DQ0_WENeg                =1;\n    specparam           thold_DQ1_WENeg                =1;\n    specparam           thold_DQ2_WENeg                =1;\n    specparam           thold_DQ3_WENeg                =1;\n    specparam           thold_DQ4_WENeg                =1;\n    specparam           thold_DQ5_WENeg                =1;\n    specparam           thold_DQ6_WENeg                =1;\n    specparam           thold_DQ7_WENeg                =1;\n    specparam           thold_DQ8_WENeg                =1;\n    specparam           thold_DQ9_WENeg                =1;\n    specparam           thold_DQ10_WENeg               =1;\n    specparam           thold_DQ11_WENeg               =1;\n    specparam           thold_DQ12_WENeg               =1;\n    specparam           thold_DQ13_WENeg               =1;\n    specparam           thold_DQ14_WENeg               =1;\n    specparam           thold_DQ15_WENeg               =1;\n\n    specparam           thold_A1_WENeg                 =1;\n    specparam           thold_A2_WENeg                 =1;\n    specparam           thold_A3_WENeg                 =1;\n    specparam           thold_A4_WENeg                 =1;\n    specparam           thold_A5_WENeg                 =1;\n    specparam           thold_A6_WENeg                 =1;\n    specparam           thold_A7_WENeg                 =1;\n    specparam           thold_A8_WENeg                 =1;\n    specparam           thold_A9_WENeg                 =1;\n    specparam           thold_A10_WENeg                =1;\n    specparam           thold_A11_WENeg                =1;\n    specparam           thold_A12_WENeg                =1;\n    specparam           thold_A13_WENeg                =1;\n    specparam           thold_A14_WENeg                =1;\n    specparam           thold_A15_WENeg                =1;\n    specparam           thold_A16_WENeg                =1;\n    specparam           thold_A17_WENeg                =1;\n    specparam           thold_A18_WENeg                =1;\n    specparam           thold_A19_WENeg                =1;\n    specparam           thold_A20_WENeg                =1;\n    specparam           thold_A21_WENeg                =1;\n    specparam           thold_A22_WENeg                =1;\n    specparam           thold_A23_WENeg                =1;\n    specparam           thold_A24_WENeg                =1;\n\n    //tpw values\n    specparam       tpw_CENeg_posedge    = 1;\n\n    specparam       tpw_ADVNeg_posedge   = 1;\n    specparam       tpw_ADVNeg_negedge   = 1;\n\n    specparam       tpw_WENeg_negedge    = 1;\n    specparam       tpw_WENeg_posedge    = 1;\n\n    specparam       tpw_RSTNeg_negedge   = 1;\n\n    specparam       tpw_CLK_posedge      = 1;\n    specparam       tpw_CLK_negedge      = 1;\n    specparam       tperiod_CLK          = 1;\n\n    // tdevice values: values for internal delays\n    `ifdef SPEEDSIM\n        // Program BUffProgram\n        specparam   tdevice_BuffProgram             = 88000;\n        // Program BUffProgram\n        specparam   tdevice_BuffProgram9V           = 68000;\n        // Program BEFP\n        specparam   tdevice_BEFP                    = 32000;\n        // Program EraseParameter\n        specparam   tdevice_EraseParameter_td       = 2500;\n        // Program EraseMain\n        specparam   tdevice_EraseMain_td            = 4000;\n    `else\n        // Program BUffProgram\n        specparam   tdevice_BuffProgram             = 880000;\n        // Program BUffProgram\n        specparam   tdevice_BuffProgram9V           = 680000;\n        // Program BEFP\n        specparam   tdevice_BEFP                    = 320000;\n        // Program EraseParameter\n        specparam   tdevice_EraseParameter_td       = 2500000;\n        // Program EraseMain\n        specparam   tdevice_EraseMain_td            = 4000000;\n    `endif // SPEEDSIM\n\n    // Program Word\n    specparam   tdevice_WordProgram             = 200000;\n    // Program Word\n    specparam   tdevice_WordProgram9V           = 190000;\n    // Program BEFPsetup\n    specparam   tdevice_BEFPsetup               = 5000;\n    // Program ProgramSuspend\n    specparam   tdevice_ProgramSuspend          = 25000;\n    // Program ProgramSuspend\n    specparam   tdevice_EraseSuspend            = 25000;\n    // Reset during Program or Erase\n    specparam   tdevice_RstDuringErsPrg         = 25000;\n\n///////////////////////////////////////////////////////////////////////////////\n// Input Port  Delays  don't require Verilog description\n///////////////////////////////////////////////////////////////////////////////\n// Path delays                                                               //\n///////////////////////////////////////////////////////////////////////////////\n    if (InitialPageAccess) (A1 *> DQ0)  = tpd_A1_DQ0;\n    if (InitialPageAccess) (A1 *> DQ1)  = tpd_A1_DQ1;\n    if (InitialPageAccess) (A1 *> DQ2)  = tpd_A1_DQ2;\n    if (InitialPageAccess) (A1 *> DQ3)  = tpd_A1_DQ3;\n    if (InitialPageAccess) (A1 *> DQ4)  = tpd_A1_DQ4;\n    if (InitialPageAccess) (A1 *> DQ5)  = tpd_A1_DQ5;\n    if (InitialPageAccess) (A1 *> DQ6)  = tpd_A1_DQ6;\n    if (InitialPageAccess) (A1 *> DQ7)  = tpd_A1_DQ7;\n    if (InitialPageAccess) (A1 *> DQ8)  = tpd_A1_DQ8;\n    if (InitialPageAccess) (A1 *> DQ9)  = tpd_A1_DQ9;\n    if (InitialPageAccess) (A1 *> DQ10) = tpd_A1_DQ10;\n    if (InitialPageAccess) (A1 *> DQ11) = tpd_A1_DQ11;\n    if (InitialPageAccess) (A1 *> DQ12) = tpd_A1_DQ12;\n    if (InitialPageAccess) (A1 *> DQ13) = tpd_A1_DQ13;\n    if (InitialPageAccess) (A1 *> DQ14) = tpd_A1_DQ14;\n    if (InitialPageAccess) (A1 *> DQ15) = tpd_A1_DQ15;\n    if (InitialPageAccess) (A2 *> DQ0)  = tpd_A2_DQ0;\n    if (InitialPageAccess) (A2 *> DQ1)  = tpd_A2_DQ1;\n    if (InitialPageAccess) (A2 *> DQ2)  = tpd_A2_DQ2;\n    if (InitialPageAccess) (A2 *> DQ3)  = tpd_A2_DQ3;\n    if (InitialPageAccess) (A2 *> DQ4)  = tpd_A2_DQ4;\n    if (InitialPageAccess) (A2 *> DQ5)  = tpd_A2_DQ5;\n    if (InitialPageAccess) (A2 *> DQ6)  = tpd_A2_DQ6;\n    if (InitialPageAccess) (A2 *> DQ7)  = tpd_A2_DQ7;\n    if (InitialPageAccess) (A2 *> DQ8)  = tpd_A2_DQ8;\n    if (InitialPageAccess) (A2 *> DQ9)  = tpd_A2_DQ9;\n    if (InitialPageAccess) (A2 *> DQ10) = tpd_A2_DQ10;\n    if (InitialPageAccess) (A2 *> DQ11) = tpd_A2_DQ11;\n    if (InitialPageAccess) (A2 *> DQ12) = tpd_A2_DQ12;\n    if (InitialPageAccess) (A2 *> DQ13) = tpd_A2_DQ13;\n    if (InitialPageAccess) (A2 *> DQ14) = tpd_A2_DQ14;\n    if (InitialPageAccess) (A2 *> DQ15) = tpd_A2_DQ15;\n    if (InitialPageAccess) (A3 *> DQ0)  = tpd_A3_DQ0;\n    if (InitialPageAccess) (A3 *> DQ1)  = tpd_A3_DQ1;\n    if (InitialPageAccess) (A3 *> DQ2)  = tpd_A3_DQ2;\n    if (InitialPageAccess) (A3 *> DQ3)  = tpd_A3_DQ3;\n    if (InitialPageAccess) (A3 *> DQ4)  = tpd_A3_DQ4;\n    if (InitialPageAccess) (A3 *> DQ5)  = tpd_A3_DQ5;\n    if (InitialPageAccess) (A3 *> DQ6)  = tpd_A3_DQ6;\n    if (InitialPageAccess) (A3 *> DQ7)  = tpd_A3_DQ7;\n    if (InitialPageAccess) (A3 *> DQ8)  = tpd_A3_DQ8;\n    if (InitialPageAccess) (A3 *> DQ9)  = tpd_A3_DQ9;\n    if (InitialPageAccess) (A3 *> DQ10) = tpd_A3_DQ10;\n    if (InitialPageAccess) (A3 *> DQ11) = tpd_A3_DQ11;\n    if (InitialPageAccess) (A3 *> DQ12) = tpd_A3_DQ12;\n    if (InitialPageAccess) (A3 *> DQ13) = tpd_A3_DQ13;\n    if (InitialPageAccess) (A3 *> DQ14) = tpd_A3_DQ14;\n    if (InitialPageAccess) (A3 *> DQ15) = tpd_A3_DQ15;\n    if (InitialPageAccess) (A4 *> DQ0)  = tpd_A4_DQ0;\n    if (InitialPageAccess) (A4 *> DQ1)  = tpd_A4_DQ1;\n    if (InitialPageAccess) (A4 *> DQ2)  = tpd_A4_DQ2;\n    if (InitialPageAccess) (A4 *> DQ3)  = tpd_A4_DQ3;\n    if (InitialPageAccess) (A4 *> DQ4)  = tpd_A4_DQ4;\n    if (InitialPageAccess) (A4 *> DQ5)  = tpd_A4_DQ5;\n    if (InitialPageAccess) (A4 *> DQ6)  = tpd_A4_DQ6;\n    if (InitialPageAccess) (A4 *> DQ7)  = tpd_A4_DQ7;\n    if (InitialPageAccess) (A4 *> DQ8)  = tpd_A4_DQ8;\n    if (InitialPageAccess) (A4 *> DQ9)  = tpd_A4_DQ9;\n    if (InitialPageAccess) (A4 *> DQ10) = tpd_A4_DQ10;\n    if (InitialPageAccess) (A4 *> DQ11) = tpd_A4_DQ11;\n    if (InitialPageAccess) (A4 *> DQ12) = tpd_A4_DQ12;\n    if (InitialPageAccess) (A4 *> DQ13) = tpd_A4_DQ13;\n    if (InitialPageAccess) (A4 *> DQ14) = tpd_A4_DQ14;\n    if (InitialPageAccess) (A4 *> DQ15) = tpd_A4_DQ15;\n    if (InitialPageAccess) (A5 *> DQ0)  = tpd_A5_DQ0;\n    if (InitialPageAccess) (A5 *> DQ1)  = tpd_A5_DQ1;\n    if (InitialPageAccess) (A5 *> DQ2)  = tpd_A5_DQ2;\n    if (InitialPageAccess) (A5 *> DQ3)  = tpd_A5_DQ3;\n    if (InitialPageAccess) (A5 *> DQ4)  = tpd_A5_DQ4;\n    if (InitialPageAccess) (A5 *> DQ5)  = tpd_A5_DQ5;\n    if (InitialPageAccess) (A5 *> DQ6)  = tpd_A5_DQ6;\n    if (InitialPageAccess) (A5 *> DQ7)  = tpd_A5_DQ7;\n    if (InitialPageAccess) (A5 *> DQ8)  = tpd_A5_DQ8;\n    if (InitialPageAccess) (A5 *> DQ9)  = tpd_A5_DQ9;\n    if (InitialPageAccess) (A5 *> DQ10) = tpd_A5_DQ10;\n    if (InitialPageAccess) (A5 *> DQ11) = tpd_A5_DQ11;\n    if (InitialPageAccess) (A5 *> DQ12) = tpd_A5_DQ12;\n    if (InitialPageAccess) (A5 *> DQ13) = tpd_A5_DQ13;\n    if (InitialPageAccess) (A5 *> DQ14) = tpd_A5_DQ14;\n    if (InitialPageAccess) (A5 *> DQ15) = tpd_A5_DQ15;\n    if (InitialPageAccess) (A6 *> DQ0)  = tpd_A6_DQ0;\n    if (InitialPageAccess) (A6 *> DQ1)  = tpd_A6_DQ1;\n    if (InitialPageAccess) (A6 *> DQ2)  = tpd_A6_DQ2;\n    if (InitialPageAccess) (A6 *> DQ3)  = tpd_A6_DQ3;\n    if (InitialPageAccess) (A6 *> DQ4)  = tpd_A6_DQ4;\n    if (InitialPageAccess) (A6 *> DQ5)  = tpd_A6_DQ5;\n    if (InitialPageAccess) (A6 *> DQ6)  = tpd_A6_DQ6;\n    if (InitialPageAccess) (A6 *> DQ7)  = tpd_A6_DQ7;\n    if (InitialPageAccess) (A6 *> DQ8)  = tpd_A6_DQ8;\n    if (InitialPageAccess) (A6 *> DQ9)  = tpd_A6_DQ9;\n    if (InitialPageAccess) (A6 *> DQ10) = tpd_A6_DQ10;\n    if (InitialPageAccess) (A6 *> DQ11) = tpd_A6_DQ11;\n    if (InitialPageAccess) (A6 *> DQ12) = tpd_A6_DQ12;\n    if (InitialPageAccess) (A6 *> DQ13) = tpd_A6_DQ13;\n    if (InitialPageAccess) (A6 *> DQ14) = tpd_A6_DQ14;\n    if (InitialPageAccess) (A6 *> DQ15) = tpd_A6_DQ15;\n    if (InitialPageAccess) (A7 *> DQ0)  = tpd_A7_DQ0;\n    if (InitialPageAccess) (A7 *> DQ1)  = tpd_A7_DQ1;\n    if (InitialPageAccess) (A7 *> DQ2)  = tpd_A7_DQ2;\n    if (InitialPageAccess) (A7 *> DQ3)  = tpd_A7_DQ3;\n    if (InitialPageAccess) (A7 *> DQ4)  = tpd_A7_DQ4;\n    if (InitialPageAccess) (A7 *> DQ5)  = tpd_A7_DQ5;\n    if (InitialPageAccess) (A7 *> DQ6)  = tpd_A7_DQ6;\n    if (InitialPageAccess) (A7 *> DQ7)  = tpd_A7_DQ7;\n    if (InitialPageAccess) (A7 *> DQ8)  = tpd_A7_DQ8;\n    if (InitialPageAccess) (A7 *> DQ9)  = tpd_A7_DQ9;\n    if (InitialPageAccess) (A7 *> DQ10) = tpd_A7_DQ10;\n    if (InitialPageAccess) (A7 *> DQ11) = tpd_A7_DQ11;\n    if (InitialPageAccess) (A7 *> DQ12) = tpd_A7_DQ12;\n    if (InitialPageAccess) (A7 *> DQ13) = tpd_A7_DQ13;\n    if (InitialPageAccess) (A7 *> DQ14) = tpd_A7_DQ14;\n    if (InitialPageAccess) (A7 *> DQ15) = tpd_A7_DQ15;\n    if (InitialPageAccess) (A8 *> DQ0)  = tpd_A8_DQ0;\n    if (InitialPageAccess) (A8 *> DQ1)  = tpd_A8_DQ1;\n    if (InitialPageAccess) (A8 *> DQ2)  = tpd_A8_DQ2;\n    if (InitialPageAccess) (A8 *> DQ3)  = tpd_A8_DQ3;\n    if (InitialPageAccess) (A8 *> DQ4)  = tpd_A8_DQ4;\n    if (InitialPageAccess) (A8 *> DQ5)  = tpd_A8_DQ5;\n    if (InitialPageAccess) (A8 *> DQ6)  = tpd_A8_DQ6;\n    if (InitialPageAccess) (A8 *> DQ7)  = tpd_A8_DQ7;\n    if (InitialPageAccess) (A8 *> DQ8)  = tpd_A8_DQ8;\n    if (InitialPageAccess) (A8 *> DQ9)  = tpd_A8_DQ9;\n    if (InitialPageAccess) (A8 *> DQ10) = tpd_A8_DQ10;\n    if (InitialPageAccess) (A8 *> DQ11) = tpd_A8_DQ11;\n    if (InitialPageAccess) (A8 *> DQ12) = tpd_A8_DQ12;\n    if (InitialPageAccess) (A8 *> DQ13) = tpd_A8_DQ13;\n    if (InitialPageAccess) (A8 *> DQ14) = tpd_A8_DQ14;\n    if (InitialPageAccess) (A8 *> DQ15) = tpd_A8_DQ15;\n    if (InitialPageAccess) (A9 *> DQ0)  = tpd_A9_DQ0;\n    if (InitialPageAccess) (A9 *> DQ1)  = tpd_A9_DQ1;\n    if (InitialPageAccess) (A9 *> DQ2)  = tpd_A9_DQ2;\n    if (InitialPageAccess) (A9 *> DQ3)  = tpd_A9_DQ3;\n    if (InitialPageAccess) (A9 *> DQ4)  = tpd_A9_DQ4;\n    if (InitialPageAccess) (A9 *> DQ5)  = tpd_A9_DQ5;\n    if (InitialPageAccess) (A9 *> DQ6)  = tpd_A9_DQ6;\n    if (InitialPageAccess) (A9 *> DQ7)  = tpd_A9_DQ7;\n    if (InitialPageAccess) (A9 *> DQ8)  = tpd_A9_DQ8;\n    if (InitialPageAccess) (A9 *> DQ9)  = tpd_A9_DQ9;\n    if (InitialPageAccess) (A9 *> DQ10) = tpd_A9_DQ10;\n    if (InitialPageAccess) (A9 *> DQ11) = tpd_A9_DQ11;\n    if (InitialPageAccess) (A9 *> DQ12) = tpd_A9_DQ12;\n    if (InitialPageAccess) (A9 *> DQ13) = tpd_A9_DQ13;\n    if (InitialPageAccess) (A9 *> DQ14) = tpd_A9_DQ14;\n    if (InitialPageAccess) (A9 *> DQ15) = tpd_A9_DQ15;\n    if (InitialPageAccess) (A10 *> DQ0) = tpd_A10_DQ0;\n    if (InitialPageAccess) (A10 *> DQ1) = tpd_A10_DQ1;\n    if (InitialPageAccess) (A10 *> DQ2) = tpd_A10_DQ2;\n    if (InitialPageAccess) (A10 *> DQ3) = tpd_A10_DQ3;\n    if (InitialPageAccess) (A10 *> DQ4) = tpd_A10_DQ4;\n    if (InitialPageAccess) (A10 *> DQ5) = tpd_A10_DQ5;\n    if (InitialPageAccess) (A10 *> DQ6) = tpd_A10_DQ6;\n    if (InitialPageAccess) (A10 *> DQ7) = tpd_A10_DQ7;\n    if (InitialPageAccess) (A10 *> DQ8) = tpd_A10_DQ8;\n    if (InitialPageAccess) (A10 *> DQ9) = tpd_A10_DQ9;\n    if (InitialPageAccess) (A10 *> DQ10) = tpd_A10_DQ10;\n    if (InitialPageAccess) (A10 *> DQ11) = tpd_A10_DQ11;\n    if (InitialPageAccess) (A10 *> DQ12) = tpd_A10_DQ12;\n    if (InitialPageAccess) (A10 *> DQ13) = tpd_A10_DQ13;\n    if (InitialPageAccess) (A10 *> DQ14) = tpd_A10_DQ14;\n    if (InitialPageAccess) (A10 *> DQ15) = tpd_A10_DQ15;\n    if (InitialPageAccess) (A11 *> DQ0)  = tpd_A11_DQ0;\n    if (InitialPageAccess) (A11 *> DQ1)  = tpd_A11_DQ1;\n    if (InitialPageAccess) (A11 *> DQ2)  = tpd_A11_DQ2;\n    if (InitialPageAccess) (A11 *> DQ3)  = tpd_A11_DQ3;\n    if (InitialPageAccess) (A11 *> DQ4)  = tpd_A11_DQ4;\n    if (InitialPageAccess) (A11 *> DQ5)  = tpd_A11_DQ5;\n    if (InitialPageAccess) (A11 *> DQ6)  = tpd_A11_DQ6;\n    if (InitialPageAccess) (A11 *> DQ7)  = tpd_A11_DQ7;\n    if (InitialPageAccess) (A11 *> DQ8)  = tpd_A11_DQ8;\n    if (InitialPageAccess) (A11 *> DQ9)  = tpd_A11_DQ9;\n    if (InitialPageAccess) (A11 *> DQ10) = tpd_A11_DQ10;\n    if (InitialPageAccess) (A11 *> DQ11) = tpd_A11_DQ11;\n    if (InitialPageAccess) (A11 *> DQ12) = tpd_A11_DQ12;\n    if (InitialPageAccess) (A11 *> DQ13) = tpd_A11_DQ13;\n    if (InitialPageAccess) (A11 *> DQ14) = tpd_A11_DQ14;\n    if (InitialPageAccess) (A11 *> DQ15) = tpd_A11_DQ15;\n    if (InitialPageAccess) (A12 *> DQ0)  = tpd_A12_DQ0;\n    if (InitialPageAccess) (A12 *> DQ1)  = tpd_A12_DQ1;\n    if (InitialPageAccess) (A12 *> DQ2)  = tpd_A12_DQ2;\n    if (InitialPageAccess) (A12 *> DQ3)  = tpd_A12_DQ3;\n    if (InitialPageAccess) (A12 *> DQ4)  = tpd_A12_DQ4;\n    if (InitialPageAccess) (A12 *> DQ5)  = tpd_A12_DQ5;\n    if (InitialPageAccess) (A12 *> DQ6)  = tpd_A12_DQ6;\n    if (InitialPageAccess) (A12 *> DQ7)  = tpd_A12_DQ7;\n    if (InitialPageAccess) (A12 *> DQ8)  = tpd_A12_DQ8;\n    if (InitialPageAccess) (A12 *> DQ9)  = tpd_A12_DQ9;\n    if (InitialPageAccess) (A12 *> DQ10) = tpd_A12_DQ10;\n    if (InitialPageAccess) (A12 *> DQ11) = tpd_A12_DQ11;\n    if (InitialPageAccess) (A12 *> DQ12) = tpd_A12_DQ12;\n    if (InitialPageAccess) (A12 *> DQ13) = tpd_A12_DQ13;\n    if (InitialPageAccess) (A12 *> DQ14) = tpd_A12_DQ14;\n    if (InitialPageAccess) (A12 *> DQ15) = tpd_A12_DQ15;\n    if (InitialPageAccess) (A13 *> DQ0)  = tpd_A13_DQ0;\n    if (InitialPageAccess) (A13 *> DQ1)  = tpd_A13_DQ1;\n    if (InitialPageAccess) (A13 *> DQ2)  = tpd_A13_DQ2;\n    if (InitialPageAccess) (A13 *> DQ3)  = tpd_A13_DQ3;\n    if (InitialPageAccess) (A13 *> DQ4)  = tpd_A13_DQ4;\n    if (InitialPageAccess) (A13 *> DQ5)  = tpd_A13_DQ5;\n    if (InitialPageAccess) (A13 *> DQ6)  = tpd_A13_DQ6;\n    if (InitialPageAccess) (A13 *> DQ7)  = tpd_A13_DQ7;\n    if (InitialPageAccess) (A13 *> DQ8)  = tpd_A13_DQ8;\n    if (InitialPageAccess) (A13 *> DQ9)  = tpd_A13_DQ9;\n    if (InitialPageAccess) (A13 *> DQ10) = tpd_A13_DQ10;\n    if (InitialPageAccess) (A13 *> DQ11) = tpd_A13_DQ11;\n    if (InitialPageAccess) (A13 *> DQ12) = tpd_A13_DQ12;\n    if (InitialPageAccess) (A13 *> DQ13) = tpd_A13_DQ13;\n    if (InitialPageAccess) (A13 *> DQ14) = tpd_A13_DQ14;\n    if (InitialPageAccess) (A13 *> DQ15) = tpd_A13_DQ15;\n    if (InitialPageAccess) (A14 *> DQ0)  = tpd_A14_DQ0;\n    if (InitialPageAccess) (A14 *> DQ1)  = tpd_A14_DQ1;\n    if (InitialPageAccess) (A14 *> DQ2)  = tpd_A14_DQ2;\n    if (InitialPageAccess) (A14 *> DQ3)  = tpd_A14_DQ3;\n    if (InitialPageAccess) (A14 *> DQ4)  = tpd_A14_DQ4;\n    if (InitialPageAccess) (A14 *> DQ5)  = tpd_A14_DQ5;\n    if (InitialPageAccess) (A14 *> DQ6)  = tpd_A14_DQ6;\n    if (InitialPageAccess) (A14 *> DQ7)  = tpd_A14_DQ7;\n    if (InitialPageAccess) (A14 *> DQ8)  = tpd_A14_DQ8;\n    if (InitialPageAccess) (A14 *> DQ9)  = tpd_A14_DQ9;\n    if (InitialPageAccess) (A14 *> DQ10) = tpd_A14_DQ10;\n    if (InitialPageAccess) (A14 *> DQ11) = tpd_A14_DQ11;\n    if (InitialPageAccess) (A14 *> DQ12) = tpd_A14_DQ12;\n    if (InitialPageAccess) (A14 *> DQ13) = tpd_A14_DQ13;\n    if (InitialPageAccess) (A14 *> DQ14) = tpd_A14_DQ14;\n    if (InitialPageAccess) (A14 *> DQ15) = tpd_A14_DQ15;\n    if (InitialPageAccess) (A15 *> DQ0)  = tpd_A15_DQ0;\n    if (InitialPageAccess) (A15 *> DQ1)  = tpd_A15_DQ1;\n    if (InitialPageAccess) (A15 *> DQ2)  = tpd_A15_DQ2;\n    if (InitialPageAccess) (A15 *> DQ3)  = tpd_A15_DQ3;\n    if (InitialPageAccess) (A15 *> DQ4)  = tpd_A15_DQ4;\n    if (InitialPageAccess) (A15 *> DQ5)  = tpd_A15_DQ5;\n    if (InitialPageAccess) (A15 *> DQ6)  = tpd_A15_DQ6;\n    if (InitialPageAccess) (A15 *> DQ7)  = tpd_A15_DQ7;\n    if (InitialPageAccess) (A15 *> DQ8)  = tpd_A15_DQ8;\n    if (InitialPageAccess) (A15 *> DQ9)  = tpd_A15_DQ9;\n    if (InitialPageAccess) (A15 *> DQ10) = tpd_A15_DQ10;\n    if (InitialPageAccess) (A15 *> DQ11) = tpd_A15_DQ11;\n    if (InitialPageAccess) (A15 *> DQ12) = tpd_A15_DQ12;\n    if (InitialPageAccess) (A15 *> DQ13) = tpd_A15_DQ13;\n    if (InitialPageAccess) (A15 *> DQ14) = tpd_A15_DQ14;\n    if (InitialPageAccess) (A15 *> DQ15) = tpd_A15_DQ15;\n    if (InitialPageAccess) (A16 *> DQ0)  = tpd_A16_DQ0;\n    if (InitialPageAccess) (A16 *> DQ1)  = tpd_A16_DQ1;\n    if (InitialPageAccess) (A16 *> DQ2)  = tpd_A16_DQ2;\n    if (InitialPageAccess) (A16 *> DQ3)  = tpd_A16_DQ3;\n    if (InitialPageAccess) (A16 *> DQ4)  = tpd_A16_DQ4;\n    if (InitialPageAccess) (A16 *> DQ5)  = tpd_A16_DQ5;\n    if (InitialPageAccess) (A16 *> DQ6)  = tpd_A16_DQ6;\n    if (InitialPageAccess) (A16 *> DQ7)  = tpd_A16_DQ7;\n    if (InitialPageAccess) (A16 *> DQ8)  = tpd_A16_DQ8;\n    if (InitialPageAccess) (A16 *> DQ9)  = tpd_A16_DQ9;\n    if (InitialPageAccess) (A16 *> DQ10) = tpd_A16_DQ10;\n    if (InitialPageAccess) (A16 *> DQ11) = tpd_A16_DQ11;\n    if (InitialPageAccess) (A16 *> DQ12) = tpd_A16_DQ12;\n    if (InitialPageAccess) (A16 *> DQ13) = tpd_A16_DQ13;\n    if (InitialPageAccess) (A16 *> DQ14) = tpd_A16_DQ14;\n    if (InitialPageAccess) (A16 *> DQ15) = tpd_A16_DQ15;\n    if (InitialPageAccess) (A17 *> DQ0)  = tpd_A17_DQ0;\n    if (InitialPageAccess) (A17 *> DQ1)  = tpd_A17_DQ1;\n    if (InitialPageAccess) (A17 *> DQ2)  = tpd_A17_DQ2;\n    if (InitialPageAccess) (A17 *> DQ3)  = tpd_A17_DQ3;\n    if (InitialPageAccess) (A17 *> DQ4)  = tpd_A17_DQ4;\n    if (InitialPageAccess) (A17 *> DQ5)  = tpd_A17_DQ5;\n    if (InitialPageAccess) (A17 *> DQ6)  = tpd_A17_DQ6;\n    if (InitialPageAccess) (A17 *> DQ7)  = tpd_A17_DQ7;\n    if (InitialPageAccess) (A17 *> DQ8)  = tpd_A17_DQ8;\n    if (InitialPageAccess) (A17 *> DQ9)  = tpd_A17_DQ9;\n    if (InitialPageAccess) (A17 *> DQ10) = tpd_A17_DQ10;\n    if (InitialPageAccess) (A17 *> DQ11) = tpd_A17_DQ11;\n    if (InitialPageAccess) (A17 *> DQ12) = tpd_A17_DQ12;\n    if (InitialPageAccess) (A17 *> DQ13) = tpd_A17_DQ13;\n    if (InitialPageAccess) (A17 *> DQ14) = tpd_A17_DQ14;\n    if (InitialPageAccess) (A17 *> DQ15) = tpd_A17_DQ15;\n    if (InitialPageAccess) (A18 *> DQ0)  = tpd_A18_DQ0;\n    if (InitialPageAccess) (A18 *> DQ1)  = tpd_A18_DQ1;\n    if (InitialPageAccess) (A18 *> DQ2)  = tpd_A18_DQ2;\n    if (InitialPageAccess) (A18 *> DQ3)  = tpd_A18_DQ3;\n    if (InitialPageAccess) (A18 *> DQ4)  = tpd_A18_DQ4;\n    if (InitialPageAccess) (A18 *> DQ5)  = tpd_A18_DQ5;\n    if (InitialPageAccess) (A18 *> DQ6)  = tpd_A18_DQ6;\n    if (InitialPageAccess) (A18 *> DQ7)  = tpd_A18_DQ7;\n    if (InitialPageAccess) (A18 *> DQ8)  = tpd_A18_DQ8;\n    if (InitialPageAccess) (A18 *> DQ9)  = tpd_A18_DQ9;\n    if (InitialPageAccess) (A18 *> DQ10) = tpd_A18_DQ10;\n    if (InitialPageAccess) (A18 *> DQ11) = tpd_A18_DQ11;\n    if (InitialPageAccess) (A18 *> DQ12) = tpd_A18_DQ12;\n    if (InitialPageAccess) (A18 *> DQ13) = tpd_A18_DQ13;\n    if (InitialPageAccess) (A18 *> DQ14) = tpd_A18_DQ14;\n    if (InitialPageAccess) (A18 *> DQ15) = tpd_A18_DQ15;\n    if (InitialPageAccess) (A19 *> DQ0)  = tpd_A19_DQ0;\n    if (InitialPageAccess) (A19 *> DQ1)  = tpd_A19_DQ1;\n    if (InitialPageAccess) (A19 *> DQ2)  = tpd_A19_DQ2;\n    if (InitialPageAccess) (A19 *> DQ3)  = tpd_A19_DQ3;\n    if (InitialPageAccess) (A19 *> DQ4)  = tpd_A19_DQ4;\n    if (InitialPageAccess) (A19 *> DQ5)  = tpd_A19_DQ5;\n    if (InitialPageAccess) (A19 *> DQ6)  = tpd_A19_DQ6;\n    if (InitialPageAccess) (A19 *> DQ7)  = tpd_A19_DQ7;\n    if (InitialPageAccess) (A19 *> DQ8)  = tpd_A19_DQ8;\n    if (InitialPageAccess) (A19 *> DQ9)  = tpd_A19_DQ9;\n    if (InitialPageAccess) (A19 *> DQ10) = tpd_A19_DQ10;\n    if (InitialPageAccess) (A19 *> DQ11) = tpd_A19_DQ11;\n    if (InitialPageAccess) (A19 *> DQ12) = tpd_A19_DQ12;\n    if (InitialPageAccess) (A19 *> DQ13) = tpd_A19_DQ13;\n    if (InitialPageAccess) (A19 *> DQ14) = tpd_A19_DQ14;\n    if (InitialPageAccess) (A19 *> DQ15) = tpd_A19_DQ15;\n    if (InitialPageAccess) (A20 *> DQ0)  = tpd_A20_DQ0;\n    if (InitialPageAccess) (A20 *> DQ1)  = tpd_A20_DQ1;\n    if (InitialPageAccess) (A20 *> DQ2)  = tpd_A20_DQ2;\n    if (InitialPageAccess) (A20 *> DQ3)  = tpd_A20_DQ3;\n    if (InitialPageAccess) (A20 *> DQ4)  = tpd_A20_DQ4;\n    if (InitialPageAccess) (A20 *> DQ5)  = tpd_A20_DQ5;\n    if (InitialPageAccess) (A20 *> DQ6)  = tpd_A20_DQ6;\n    if (InitialPageAccess) (A20 *> DQ7)  = tpd_A20_DQ7;\n    if (InitialPageAccess) (A20 *> DQ8)  = tpd_A20_DQ8;\n    if (InitialPageAccess) (A20 *> DQ9)  = tpd_A20_DQ9;\n    if (InitialPageAccess) (A20 *> DQ10) = tpd_A20_DQ10;\n    if (InitialPageAccess) (A20 *> DQ11) = tpd_A20_DQ11;\n    if (InitialPageAccess) (A20 *> DQ12) = tpd_A20_DQ12;\n    if (InitialPageAccess) (A20 *> DQ13) = tpd_A20_DQ13;\n    if (InitialPageAccess) (A20 *> DQ14) = tpd_A20_DQ14;\n    if (InitialPageAccess) (A20 *> DQ15) = tpd_A20_DQ15;\n    if (InitialPageAccess) (A21 *> DQ0)  = tpd_A21_DQ0;\n    if (InitialPageAccess) (A21 *> DQ1)  = tpd_A21_DQ1;\n    if (InitialPageAccess) (A21 *> DQ2)  = tpd_A21_DQ2;\n    if (InitialPageAccess) (A21 *> DQ3)  = tpd_A21_DQ3;\n    if (InitialPageAccess) (A21 *> DQ4)  = tpd_A21_DQ4;\n    if (InitialPageAccess) (A21 *> DQ5)  = tpd_A21_DQ5;\n    if (InitialPageAccess) (A21 *> DQ6)  = tpd_A21_DQ6;\n    if (InitialPageAccess) (A21 *> DQ7)  = tpd_A21_DQ7;\n    if (InitialPageAccess) (A21 *> DQ8)  = tpd_A21_DQ8;\n    if (InitialPageAccess) (A21 *> DQ9)  = tpd_A21_DQ9;\n    if (InitialPageAccess) (A21 *> DQ10) = tpd_A21_DQ10;\n    if (InitialPageAccess) (A21 *> DQ11) = tpd_A21_DQ11;\n    if (InitialPageAccess) (A21 *> DQ12) = tpd_A21_DQ12;\n    if (InitialPageAccess) (A21 *> DQ13) = tpd_A21_DQ13;\n    if (InitialPageAccess) (A21 *> DQ14) = tpd_A21_DQ14;\n    if (InitialPageAccess) (A21 *> DQ15) = tpd_A21_DQ15;\n    if (InitialPageAccess) (A22 *> DQ0)  = tpd_A22_DQ0;\n    if (InitialPageAccess) (A22 *> DQ1)  = tpd_A22_DQ1;\n    if (InitialPageAccess) (A22 *> DQ2)  = tpd_A22_DQ2;\n    if (InitialPageAccess) (A22 *> DQ3)  = tpd_A22_DQ3;\n    if (InitialPageAccess) (A22 *> DQ4)  = tpd_A22_DQ4;\n    if (InitialPageAccess) (A22 *> DQ5)  = tpd_A22_DQ5;\n    if (InitialPageAccess) (A22 *> DQ6)  = tpd_A22_DQ6;\n    if (InitialPageAccess) (A22 *> DQ7)  = tpd_A22_DQ7;\n    if (InitialPageAccess) (A22 *> DQ8)  = tpd_A22_DQ8;\n    if (InitialPageAccess) (A22 *> DQ9)  = tpd_A22_DQ9;\n    if (InitialPageAccess) (A22 *> DQ10) = tpd_A22_DQ10;\n    if (InitialPageAccess) (A22 *> DQ11) = tpd_A22_DQ11;\n    if (InitialPageAccess) (A22 *> DQ12) = tpd_A22_DQ12;\n    if (InitialPageAccess) (A22 *> DQ13) = tpd_A22_DQ13;\n    if (InitialPageAccess) (A22 *> DQ14) = tpd_A22_DQ14;\n    if (InitialPageAccess) (A22 *> DQ15) = tpd_A22_DQ15;\n    if (InitialPageAccess) (A23 *> DQ0)  = tpd_A23_DQ0;\n    if (InitialPageAccess) (A23 *> DQ1)  = tpd_A23_DQ1;\n    if (InitialPageAccess) (A23 *> DQ2)  = tpd_A23_DQ2;\n    if (InitialPageAccess) (A23 *> DQ3)  = tpd_A23_DQ3;\n    if (InitialPageAccess) (A23 *> DQ4)  = tpd_A23_DQ4;\n    if (InitialPageAccess) (A23 *> DQ5)  = tpd_A23_DQ5;\n    if (InitialPageAccess) (A23 *> DQ6)  = tpd_A23_DQ6;\n    if (InitialPageAccess) (A23 *> DQ7)  = tpd_A23_DQ7;\n    if (InitialPageAccess) (A23 *> DQ8)  = tpd_A23_DQ8;\n    if (InitialPageAccess) (A23 *> DQ9)  = tpd_A23_DQ9;\n    if (InitialPageAccess) (A23 *> DQ10) = tpd_A23_DQ10;\n    if (InitialPageAccess) (A23 *> DQ11) = tpd_A23_DQ11;\n    if (InitialPageAccess) (A23 *> DQ12) = tpd_A23_DQ12;\n    if (InitialPageAccess) (A23 *> DQ13) = tpd_A23_DQ13;\n    if (InitialPageAccess) (A23 *> DQ14) = tpd_A23_DQ14;\n    if (InitialPageAccess) (A23 *> DQ15) = tpd_A23_DQ15;\n    if (InitialPageAccess) (A24 *> DQ0)  = tpd_A24_DQ0;\n    if (InitialPageAccess) (A24 *> DQ1)  = tpd_A24_DQ1;\n    if (InitialPageAccess) (A24 *> DQ2)  = tpd_A24_DQ2;\n    if (InitialPageAccess) (A24 *> DQ3)  = tpd_A24_DQ3;\n    if (InitialPageAccess) (A24 *> DQ4)  = tpd_A24_DQ4;\n    if (InitialPageAccess) (A24 *> DQ5)  = tpd_A24_DQ5;\n    if (InitialPageAccess) (A24 *> DQ6)  = tpd_A24_DQ6;\n    if (InitialPageAccess) (A24 *> DQ7)  = tpd_A24_DQ7;\n    if (InitialPageAccess) (A24 *> DQ8)  = tpd_A24_DQ8;\n    if (InitialPageAccess) (A24 *> DQ9)  = tpd_A24_DQ9;\n    if (InitialPageAccess) (A24 *> DQ10) = tpd_A24_DQ10;\n    if (InitialPageAccess) (A24 *> DQ11) = tpd_A24_DQ11;\n    if (InitialPageAccess) (A24 *> DQ12) = tpd_A24_DQ12;\n    if (InitialPageAccess) (A24 *> DQ13) = tpd_A24_DQ13;\n    if (InitialPageAccess) (A24 *> DQ14) = tpd_A24_DQ14;\n    if (InitialPageAccess) (A24 *> DQ15) = tpd_A24_DQ15;\n\n    if (SubsequentPageAccess) (A1 *> DQ0)  = tpd_A1_DQ0;\n    if (SubsequentPageAccess) (A1 *> DQ1)  = tpd_A1_DQ1;\n    if (SubsequentPageAccess) (A1 *> DQ2)  = tpd_A1_DQ2;\n    if (SubsequentPageAccess) (A1 *> DQ3)  = tpd_A1_DQ3;\n    if (SubsequentPageAccess) (A1 *> DQ4)  = tpd_A1_DQ4;\n    if (SubsequentPageAccess) (A1 *> DQ5)  = tpd_A1_DQ5;\n    if (SubsequentPageAccess) (A1 *> DQ6)  = tpd_A1_DQ6;\n    if (SubsequentPageAccess) (A1 *> DQ7)  = tpd_A1_DQ7;\n    if (SubsequentPageAccess) (A1 *> DQ8)  = tpd_A1_DQ8;\n    if (SubsequentPageAccess) (A1 *> DQ9)  = tpd_A1_DQ9;\n    if (SubsequentPageAccess) (A1 *> DQ10) = tpd_A1_DQ10;\n    if (SubsequentPageAccess) (A1 *> DQ11) = tpd_A1_DQ11;\n    if (SubsequentPageAccess) (A1 *> DQ12) = tpd_A1_DQ12;\n    if (SubsequentPageAccess) (A1 *> DQ13) = tpd_A1_DQ13;\n    if (SubsequentPageAccess) (A1 *> DQ14) = tpd_A1_DQ14;\n    if (SubsequentPageAccess) (A1 *> DQ15) = tpd_A1_DQ15;\n    if (SubsequentPageAccess) (A2 *> DQ0)  = tpd_A2_DQ0;\n    if (SubsequentPageAccess) (A2 *> DQ1)  = tpd_A2_DQ1;\n    if (SubsequentPageAccess) (A2 *> DQ2)  = tpd_A2_DQ2;\n    if (SubsequentPageAccess) (A2 *> DQ3)  = tpd_A2_DQ3;\n    if (SubsequentPageAccess) (A2 *> DQ4)  = tpd_A2_DQ4;\n    if (SubsequentPageAccess) (A2 *> DQ5)  = tpd_A2_DQ5;\n    if (SubsequentPageAccess) (A2 *> DQ6)  = tpd_A2_DQ6;\n    if (SubsequentPageAccess) (A2 *> DQ7)  = tpd_A2_DQ7;\n    if (SubsequentPageAccess) (A2 *> DQ8)  = tpd_A2_DQ8;\n    if (SubsequentPageAccess) (A2 *> DQ9)  = tpd_A2_DQ9;\n    if (SubsequentPageAccess) (A2 *> DQ10) = tpd_A2_DQ10;\n    if (SubsequentPageAccess) (A2 *> DQ11) = tpd_A2_DQ11;\n    if (SubsequentPageAccess) (A2 *> DQ12) = tpd_A2_DQ12;\n    if (SubsequentPageAccess) (A2 *> DQ13) = tpd_A2_DQ13;\n    if (SubsequentPageAccess) (A2 *> DQ14) = tpd_A2_DQ14;\n    if (SubsequentPageAccess) (A2 *> DQ15) = tpd_A2_DQ15;\n\n    if (FROMCE) (CENeg *> DQ0) = tpd_CENeg_DQ0;\n    if (FROMCE) (CENeg *> DQ1) = tpd_CENeg_DQ1;\n    if (FROMCE) (CENeg *> DQ2) = tpd_CENeg_DQ2;\n    if (FROMCE) (CENeg *> DQ3) = tpd_CENeg_DQ3;\n    if (FROMCE) (CENeg *> DQ4) = tpd_CENeg_DQ4;\n    if (FROMCE) (CENeg *> DQ5) = tpd_CENeg_DQ5;\n    if (FROMCE) (CENeg *> DQ6) = tpd_CENeg_DQ6;\n    if (FROMCE) (CENeg *> DQ7) = tpd_CENeg_DQ7;\n    if (FROMCE) (CENeg *> DQ8) = tpd_CENeg_DQ8;\n    if (FROMCE) (CENeg *> DQ9) = tpd_CENeg_DQ9;\n    if (FROMCE) (CENeg *> DQ10)= tpd_CENeg_DQ10;\n    if (FROMCE) (CENeg *> DQ11)= tpd_CENeg_DQ11;\n    if (FROMCE) (CENeg *> DQ12)= tpd_CENeg_DQ12;\n    if (FROMCE) (CENeg *> DQ13)= tpd_CENeg_DQ13;\n    if (FROMCE) (CENeg *> DQ14)= tpd_CENeg_DQ14;\n    if (FROMCE) (CENeg *> DQ15)= tpd_CENeg_DQ15;\n\n    if (FROMOE) (OENeg *> DQ0)  = tpd_OENeg_DQ0;\n    if (FROMOE) (OENeg *> DQ1)  = tpd_OENeg_DQ1;\n    if (FROMOE) (OENeg *> DQ2)  = tpd_OENeg_DQ2;\n    if (FROMOE) (OENeg *> DQ3)  = tpd_OENeg_DQ3;\n    if (FROMOE) (OENeg *> DQ4)  = tpd_OENeg_DQ4;\n    if (FROMOE) (OENeg *> DQ5)  = tpd_OENeg_DQ5;\n    if (FROMOE) (OENeg *> DQ6)  = tpd_OENeg_DQ6;\n    if (FROMOE) (OENeg *> DQ7)  = tpd_OENeg_DQ7;\n    if (FROMOE) (OENeg *> DQ8)  = tpd_OENeg_DQ8;\n    if (FROMOE) (OENeg *> DQ9)  = tpd_OENeg_DQ9;\n    if (FROMOE) (OENeg *> DQ10) = tpd_OENeg_DQ10;\n    if (FROMOE) (OENeg *> DQ11) = tpd_OENeg_DQ11;\n    if (FROMOE) (OENeg *> DQ12) = tpd_OENeg_DQ12;\n    if (FROMOE) (OENeg *> DQ13) = tpd_OENeg_DQ13;\n    if (FROMOE) (OENeg *> DQ14) = tpd_OENeg_DQ14;\n    if (FROMOE) (OENeg *> DQ15) = tpd_OENeg_DQ15;\n\n    if (RCR[15] === 1'b0) ( CLK *> DQ0 )   =  tpd_CLK_DQ0   ;\n    if (RCR[15] === 1'b0) ( CLK *> DQ1 )   =  tpd_CLK_DQ1   ;\n    if (RCR[15] === 1'b0) ( CLK *> DQ2 )   =  tpd_CLK_DQ2   ;\n    if (RCR[15] === 1'b0) ( CLK *> DQ3 )   =  tpd_CLK_DQ3   ;\n    if (RCR[15] === 1'b0) ( CLK *> DQ4 )   =  tpd_CLK_DQ4   ;\n    if (RCR[15] === 1'b0) ( CLK *> DQ5 )   =  tpd_CLK_DQ5   ;\n    if (RCR[15] === 1'b0) ( CLK *> DQ6 )   =  tpd_CLK_DQ6   ;\n    if (RCR[15] === 1'b0) ( CLK *> DQ7 )   =  tpd_CLK_DQ7   ;\n    if (RCR[15] === 1'b0) ( CLK *> DQ8 )   =  tpd_CLK_DQ8   ;\n    if (RCR[15] === 1'b0) ( CLK *> DQ9 )   =  tpd_CLK_DQ9   ;\n    if (RCR[15] === 1'b0) ( CLK *> DQ10)   =  tpd_CLK_DQ10  ;\n    if (RCR[15] === 1'b0) ( CLK *> DQ11)   =  tpd_CLK_DQ11  ;\n    if (RCR[15] === 1'b0) ( CLK *> DQ12)   =  tpd_CLK_DQ12  ;\n    if (RCR[15] === 1'b0) ( CLK *> DQ13)   =  tpd_CLK_DQ13  ;\n    if (RCR[15] === 1'b0) ( CLK *> DQ14)   =  tpd_CLK_DQ14  ;\n    if (RCR[15] === 1'b0) ( CLK *> DQ15)   =  tpd_CLK_DQ15  ;\n\n    ( CENeg *> WAITOut)         =  tpd_CE0Neg_WAITOut ;\n    ( OENeg *> WAITOut)         =  tpd_OE0Neg_WAITOut ;\n    if (RCR[15] === 1'b0) ( CLK *> WAITOut) = tpd_CLK_WAITOut;\n\n///////////////////////////////////////////////////////////////////////////////\n// Timing Violation                                                          //\n///////////////////////////////////////////////////////////////////////////////\n    $setup ( A1   , posedge ADVNeg, tsetup_A1_ADVNeg, Viol);\n    $setup ( A2   , posedge ADVNeg, tsetup_A2_ADVNeg, Viol);\n    $setup ( A3   , posedge ADVNeg, tsetup_A3_ADVNeg, Viol);\n    $setup ( A4   , posedge ADVNeg, tsetup_A4_ADVNeg, Viol);\n    $setup ( A5   , posedge ADVNeg, tsetup_A5_ADVNeg, Viol);\n    $setup ( A6   , posedge ADVNeg, tsetup_A6_ADVNeg, Viol);\n    $setup ( A7   , posedge ADVNeg, tsetup_A7_ADVNeg, Viol);\n    $setup ( A8   , posedge ADVNeg, tsetup_A8_ADVNeg, Viol);\n    $setup ( A9   , posedge ADVNeg, tsetup_A9_ADVNeg, Viol);\n    $setup ( A10  , posedge ADVNeg, tsetup_A10_ADVNeg, Viol);\n    $setup ( A11  , posedge ADVNeg, tsetup_A11_ADVNeg, Viol);\n    $setup ( A12  , posedge ADVNeg, tsetup_A12_ADVNeg, Viol);\n    $setup ( A13  , posedge ADVNeg, tsetup_A13_ADVNeg, Viol);\n    $setup ( A14  , posedge ADVNeg, tsetup_A14_ADVNeg, Viol);\n    $setup ( A15  , posedge ADVNeg, tsetup_A15_ADVNeg, Viol);\n    $setup ( A16  , posedge ADVNeg, tsetup_A16_ADVNeg, Viol);\n    $setup ( A17  , posedge ADVNeg, tsetup_A17_ADVNeg, Viol);\n    $setup ( A18  , posedge ADVNeg, tsetup_A18_ADVNeg, Viol);\n    $setup ( A19  , posedge ADVNeg, tsetup_A19_ADVNeg, Viol);\n    $setup ( A20  , posedge ADVNeg, tsetup_A20_ADVNeg, Viol);\n    $setup ( A21  , posedge ADVNeg, tsetup_A21_ADVNeg, Viol);\n    $setup ( A22  , posedge ADVNeg, tsetup_A22_ADVNeg, Viol);\n    $setup ( A23  , posedge ADVNeg, tsetup_A23_ADVNeg, Viol);\n    $setup ( A24  , posedge ADVNeg, tsetup_A24_ADVNeg, Viol);\n\n    $setup ( negedge CENeg  , posedge ADVNeg, tsetup_CENeg_ADVNeg, Viol);\n    $setup ( negedge RSTNeg , posedge ADVNeg, tsetup_RSTNeg_ADVNeg,Viol);\n    $setup ( posedge WENeg  , posedge ADVNeg, tsetup_WENeg_ADVNeg, Viol);\n\n    $setup ( A1   , posedge CLK &&& CLK_rising, tsetup_A1_CLK, Viol);\n    $setup ( A2   , posedge CLK &&& CLK_rising, tsetup_A2_CLK, Viol);\n    $setup ( A3   , posedge CLK &&& CLK_rising, tsetup_A3_CLK, Viol);\n    $setup ( A4   , posedge CLK &&& CLK_rising, tsetup_A4_CLK, Viol);\n    $setup ( A5   , posedge CLK &&& CLK_rising, tsetup_A5_CLK, Viol);\n    $setup ( A6   , posedge CLK &&& CLK_rising, tsetup_A6_CLK, Viol);\n    $setup ( A7   , posedge CLK &&& CLK_rising, tsetup_A7_CLK, Viol);\n    $setup ( A8   , posedge CLK &&& CLK_rising, tsetup_A8_CLK, Viol);\n    $setup ( A9   , posedge CLK &&& CLK_rising, tsetup_A9_CLK, Viol);\n    $setup ( A10  , posedge CLK &&& CLK_rising, tsetup_A10_CLK, Viol);\n    $setup ( A11  , posedge CLK &&& CLK_rising, tsetup_A11_CLK, Viol);\n    $setup ( A12  , posedge CLK &&& CLK_rising, tsetup_A12_CLK, Viol);\n    $setup ( A13  , posedge CLK &&& CLK_rising, tsetup_A13_CLK, Viol);\n    $setup ( A14  , posedge CLK &&& CLK_rising, tsetup_A14_CLK, Viol);\n    $setup ( A15  , posedge CLK &&& CLK_rising, tsetup_A15_CLK, Viol);\n    $setup ( A16  , posedge CLK &&& CLK_rising, tsetup_A16_CLK, Viol);\n    $setup ( A17  , posedge CLK &&& CLK_rising, tsetup_A17_CLK, Viol);\n    $setup ( A18  , posedge CLK &&& CLK_rising, tsetup_A18_CLK, Viol);\n    $setup ( A19  , posedge CLK &&& CLK_rising, tsetup_A19_CLK, Viol);\n    $setup ( A20  , posedge CLK &&& CLK_rising, tsetup_A20_CLK, Viol);\n    $setup ( A21  , posedge CLK &&& CLK_rising, tsetup_A21_CLK, Viol);\n    $setup ( A22  , posedge CLK &&& CLK_rising, tsetup_A22_CLK, Viol);\n    $setup ( A23  , posedge CLK &&& CLK_rising, tsetup_A23_CLK, Viol);\n    $setup ( A24  , posedge CLK &&& CLK_rising, tsetup_A24_CLK, Viol);\n\n    $setup ( A1   , negedge CLK &&& CLK_falling, tsetup_A1_CLK, Viol);\n    $setup ( A2   , negedge CLK &&& CLK_falling, tsetup_A2_CLK, Viol);\n    $setup ( A3   , negedge CLK &&& CLK_falling, tsetup_A3_CLK, Viol);\n    $setup ( A4   , negedge CLK &&& CLK_falling, tsetup_A4_CLK, Viol);\n    $setup ( A5   , negedge CLK &&& CLK_falling, tsetup_A5_CLK, Viol);\n    $setup ( A6   , negedge CLK &&& CLK_falling, tsetup_A6_CLK, Viol);\n    $setup ( A7   , negedge CLK &&& CLK_falling, tsetup_A7_CLK, Viol);\n    $setup ( A8   , negedge CLK &&& CLK_falling, tsetup_A8_CLK, Viol);\n    $setup ( A9   , negedge CLK &&& CLK_falling, tsetup_A9_CLK, Viol);\n    $setup ( A10  , negedge CLK &&& CLK_falling, tsetup_A10_CLK, Viol);\n    $setup ( A11  , negedge CLK &&& CLK_falling, tsetup_A11_CLK, Viol);\n    $setup ( A12  , negedge CLK &&& CLK_falling, tsetup_A12_CLK, Viol);\n    $setup ( A13  , negedge CLK &&& CLK_falling, tsetup_A13_CLK, Viol);\n    $setup ( A14  , negedge CLK &&& CLK_falling, tsetup_A14_CLK, Viol);\n    $setup ( A15  , negedge CLK &&& CLK_falling, tsetup_A15_CLK, Viol);\n    $setup ( A16  , negedge CLK &&& CLK_falling, tsetup_A16_CLK, Viol);\n    $setup ( A17  , negedge CLK &&& CLK_falling, tsetup_A17_CLK, Viol);\n    $setup ( A18  , negedge CLK &&& CLK_falling, tsetup_A18_CLK, Viol);\n    $setup ( A19  , negedge CLK &&& CLK_falling, tsetup_A19_CLK, Viol);\n    $setup ( A20  , negedge CLK &&& CLK_falling, tsetup_A20_CLK, Viol);\n    $setup ( A21  , negedge CLK &&& CLK_falling, tsetup_A21_CLK, Viol);\n    $setup ( A22  , negedge CLK &&& CLK_falling, tsetup_A22_CLK, Viol);\n    $setup ( A23  , negedge CLK &&& CLK_falling, tsetup_A23_CLK, Viol);\n    $setup ( A24  , negedge CLK &&& CLK_falling, tsetup_A24_CLK, Viol);\n\n    $setup ( negedge ADVNeg , posedge CLK &&& CLK_rising ,\n             tsetup_ADVNeg_CLK, Viol);\n    $setup ( negedge ADVNeg , negedge CLK &&& CLK_falling ,\n             tsetup_ADVNeg_CLK, Viol);\n\n    $setup ( negedge CENeg  , posedge CLK &&& CLK_rising ,\n             tsetup_CENeg_CLK, Viol);\n    $setup ( negedge CENeg  , negedge CLK &&& CLK_falling ,\n             tsetup_CENeg_CLK, Viol);\n\n    $setup ( posedge WENeg  , posedge CLK &&& CLK_rising ,\n             tsetup_WENeg_CLK, Viol);\n    $setup ( posedge WENeg  , negedge CLK &&& CLK_falling ,\n             tsetup_WENeg_CLK, Viol);\n\n    $setup ( negedge CENeg  , negedge WENeg , tsetup_CENeg_WENeg, Viol);\n\n    $setup ( DQ0   , posedge WENeg , tsetup_DQ0_WENeg, Viol);\n    $setup ( DQ1   , posedge WENeg , tsetup_DQ1_WENeg, Viol);\n    $setup ( DQ2   , posedge WENeg , tsetup_DQ2_WENeg, Viol);\n    $setup ( DQ3   , posedge WENeg , tsetup_DQ3_WENeg, Viol);\n    $setup ( DQ4   , posedge WENeg , tsetup_DQ4_WENeg, Viol);\n    $setup ( DQ5   , posedge WENeg , tsetup_DQ5_WENeg, Viol);\n    $setup ( DQ6   , posedge WENeg , tsetup_DQ6_WENeg, Viol);\n    $setup ( DQ7   , posedge WENeg , tsetup_DQ7_WENeg, Viol);\n    $setup ( DQ8   , posedge WENeg , tsetup_DQ8_WENeg, Viol);\n    $setup ( DQ9   , posedge WENeg , tsetup_DQ9_WENeg, Viol);\n    $setup ( DQ10  , posedge WENeg , tsetup_DQ10_WENeg, Viol);\n    $setup ( DQ11  , posedge WENeg , tsetup_DQ11_WENeg, Viol);\n    $setup ( DQ12  , posedge WENeg , tsetup_DQ12_WENeg, Viol);\n    $setup ( DQ13  , posedge WENeg , tsetup_DQ13_WENeg, Viol);\n    $setup ( DQ14  , posedge WENeg , tsetup_DQ14_WENeg, Viol);\n    $setup ( DQ15  , posedge WENeg , tsetup_DQ15_WENeg, Viol);\n\n    $setup ( A1   , posedge WENeg , tsetup_A1_WENeg, Viol);\n    $setup ( A2   , posedge WENeg , tsetup_A2_WENeg, Viol);\n    $setup ( A3   , posedge WENeg , tsetup_A3_WENeg, Viol);\n    $setup ( A4   , posedge WENeg , tsetup_A4_WENeg, Viol);\n    $setup ( A5   , posedge WENeg , tsetup_A5_WENeg, Viol);\n    $setup ( A6   , posedge WENeg , tsetup_A6_WENeg, Viol);\n    $setup ( A7   , posedge WENeg , tsetup_A7_WENeg, Viol);\n    $setup ( A8   , posedge WENeg , tsetup_A8_WENeg, Viol);\n    $setup ( A9   , posedge WENeg , tsetup_A9_WENeg, Viol);\n    $setup ( A10  , posedge WENeg , tsetup_A10_WENeg, Viol);\n    $setup ( A11  , posedge WENeg , tsetup_A11_WENeg, Viol);\n    $setup ( A12  , posedge WENeg , tsetup_A12_WENeg, Viol);\n    $setup ( A13  , posedge WENeg , tsetup_A13_WENeg, Viol);\n    $setup ( A14  , posedge WENeg , tsetup_A14_WENeg, Viol);\n    $setup ( A15  , posedge WENeg , tsetup_A15_WENeg, Viol);\n    $setup ( A16  , posedge WENeg , tsetup_A16_WENeg, Viol);\n    $setup ( A17  , posedge WENeg , tsetup_A17_WENeg, Viol);\n    $setup ( A18  , posedge WENeg , tsetup_A18_WENeg, Viol);\n    $setup ( A19  , posedge WENeg , tsetup_A19_WENeg, Viol);\n    $setup ( A20  , posedge WENeg , tsetup_A20_WENeg, Viol);\n    $setup ( A21  , posedge WENeg , tsetup_A21_WENeg, Viol);\n    $setup ( A22  , posedge WENeg , tsetup_A22_WENeg, Viol);\n    $setup ( A23  , posedge WENeg , tsetup_A23_WENeg, Viol);\n    $setup ( A24  , posedge WENeg , tsetup_A24_WENeg, Viol);\n\n    $setup (posedge ADVNeg, posedge WENeg , tsetup_ADVNeg_WENeg, Viol);\n    $setup (posedge WPNeg, posedge WENeg , tsetup_WPNeg_WENeg, Viol);\n\n    $setup (posedge CLK &&& CLK_rising, negedge WENeg ,\n            tsetup_CLK_WENeg, Viol);\n    $setup (negedge CLK &&& CLK_falling, negedge WENeg ,\n            tsetup_CLK_WENeg, Viol);\n\n    $setup (posedge WENeg, negedge OENeg , tsetup_WENeg_OENeg, Viol);\n\n    $hold ( posedge WENeg,  CENeg, thold_CENeg_WENeg, Viol);\n\n    $hold (  posedge WENeg ,DQ0 , thold_DQ0_WENeg, Viol);\n    $hold (  posedge WENeg ,DQ1 , thold_DQ1_WENeg, Viol);\n    $hold (  posedge WENeg ,DQ2 , thold_DQ2_WENeg, Viol);\n    $hold (  posedge WENeg ,DQ3 , thold_DQ3_WENeg, Viol);\n    $hold (  posedge WENeg ,DQ4 , thold_DQ4_WENeg, Viol);\n    $hold (  posedge WENeg ,DQ5 , thold_DQ5_WENeg, Viol);\n    $hold (  posedge WENeg ,DQ6 , thold_DQ6_WENeg, Viol);\n    $hold (  posedge WENeg ,DQ7 , thold_DQ7_WENeg, Viol);\n    $hold (  posedge WENeg ,DQ8 , thold_DQ8_WENeg, Viol);\n    $hold (  posedge WENeg ,DQ9 , thold_DQ9_WENeg, Viol);\n    $hold (  posedge WENeg ,DQ10, thold_DQ10_WENeg, Viol);\n    $hold (  posedge WENeg ,DQ11, thold_DQ11_WENeg, Viol);\n    $hold (  posedge WENeg ,DQ12, thold_DQ12_WENeg, Viol);\n    $hold (  posedge WENeg ,DQ13, thold_DQ13_WENeg, Viol);\n    $hold (  posedge WENeg ,DQ14, thold_DQ14_WENeg, Viol);\n    $hold (  posedge WENeg ,DQ15, thold_DQ15_WENeg, Viol);\n\n    $hold (  posedge WENeg ,A1, thold_A1_WENeg, Viol);\n    $hold (  posedge WENeg ,A2, thold_A2_WENeg, Viol);\n    $hold (  posedge WENeg ,A3, thold_A3_WENeg, Viol);\n    $hold (  posedge WENeg ,A4, thold_A4_WENeg, Viol);\n    $hold (  posedge WENeg ,A5, thold_A5_WENeg, Viol);\n    $hold (  posedge WENeg ,A6, thold_A6_WENeg, Viol);\n    $hold (  posedge WENeg ,A7, thold_A7_WENeg, Viol);\n    $hold (  posedge WENeg ,A8, thold_A8_WENeg, Viol);\n    $hold (  posedge WENeg ,A9, thold_A9_WENeg, Viol);\n    $hold (  posedge WENeg ,A10, thold_A10_WENeg, Viol);\n    $hold (  posedge WENeg ,A11, thold_A11_WENeg, Viol);\n    $hold (  posedge WENeg ,A12, thold_A12_WENeg, Viol);\n    $hold (  posedge WENeg ,A13, thold_A13_WENeg, Viol);\n    $hold (  posedge WENeg ,A14, thold_A14_WENeg, Viol);\n    $hold (  posedge WENeg ,A15, thold_A15_WENeg, Viol);\n    $hold (  posedge WENeg ,A16, thold_A16_WENeg, Viol);\n    $hold (  posedge WENeg ,A17, thold_A17_WENeg, Viol);\n    $hold (  posedge WENeg ,A18, thold_A18_WENeg, Viol);\n    $hold (  posedge WENeg ,A19, thold_A19_WENeg, Viol);\n    $hold (  posedge WENeg ,A20, thold_A20_WENeg, Viol);\n    $hold (  posedge WENeg ,A21, thold_A21_WENeg, Viol);\n    $hold (  posedge WENeg ,A22, thold_A22_WENeg, Viol);\n    $hold (  posedge WENeg ,A23, thold_A23_WENeg, Viol);\n    $hold (  posedge WENeg ,A24, thold_A24_WENeg, Viol);\n\n    $hold (  posedge ADVNeg ,A1, thold_A1_ADVNeg, Viol);\n    $hold (  posedge ADVNeg ,A2, thold_A2_ADVNeg, Viol);\n    $hold (  posedge ADVNeg ,A3, thold_A3_ADVNeg, Viol);\n    $hold (  posedge ADVNeg ,A4, thold_A4_ADVNeg, Viol);\n    $hold (  posedge ADVNeg ,A5, thold_A5_ADVNeg, Viol);\n    $hold (  posedge ADVNeg ,A6, thold_A6_ADVNeg, Viol);\n    $hold (  posedge ADVNeg ,A7, thold_A7_ADVNeg, Viol);\n    $hold (  posedge ADVNeg ,A8, thold_A8_ADVNeg, Viol);\n    $hold (  posedge ADVNeg ,A9, thold_A9_ADVNeg, Viol);\n    $hold (  posedge ADVNeg ,A10, thold_A10_ADVNeg, Viol);\n    $hold (  posedge ADVNeg ,A11, thold_A11_ADVNeg, Viol);\n    $hold (  posedge ADVNeg ,A12, thold_A12_ADVNeg, Viol);\n    $hold (  posedge ADVNeg ,A13, thold_A13_ADVNeg, Viol);\n    $hold (  posedge ADVNeg ,A14, thold_A14_ADVNeg, Viol);\n    $hold (  posedge ADVNeg ,A15, thold_A15_ADVNeg, Viol);\n    $hold (  posedge ADVNeg ,A16, thold_A16_ADVNeg, Viol);\n    $hold (  posedge ADVNeg ,A17, thold_A17_ADVNeg, Viol);\n    $hold (  posedge ADVNeg ,A18, thold_A18_ADVNeg, Viol);\n    $hold (  posedge ADVNeg ,A19, thold_A19_ADVNeg, Viol);\n    $hold (  posedge ADVNeg ,A20, thold_A20_ADVNeg, Viol);\n    $hold (  posedge ADVNeg ,A21, thold_A21_ADVNeg, Viol);\n    $hold (  posedge ADVNeg ,A22, thold_A22_ADVNeg, Viol);\n    $hold (  posedge ADVNeg ,A23, thold_A23_ADVNeg, Viol);\n    $hold (  posedge ADVNeg ,A24, thold_A24_ADVNeg, Viol);\n\n    $hold ( posedge CLK &&& CLK_rising, A1  , thold_A1_CLK, Viol);\n    $hold ( posedge CLK &&& CLK_rising, A2  , thold_A2_CLK, Viol);\n    $hold ( posedge CLK &&& CLK_rising, A3  , thold_A3_CLK, Viol);\n    $hold ( posedge CLK &&& CLK_rising, A4  , thold_A4_CLK, Viol);\n    $hold ( posedge CLK &&& CLK_rising, A5  , thold_A5_CLK, Viol);\n    $hold ( posedge CLK &&& CLK_rising, A6  , thold_A6_CLK, Viol);\n    $hold ( posedge CLK &&& CLK_rising, A7  , thold_A7_CLK, Viol);\n    $hold ( posedge CLK &&& CLK_rising, A8  , thold_A8_CLK, Viol);\n    $hold ( posedge CLK &&& CLK_rising, A9  , thold_A9_CLK, Viol);\n    $hold ( posedge CLK &&& CLK_rising, A10 , thold_A10_CLK, Viol);\n    $hold ( posedge CLK &&& CLK_rising, A11 , thold_A11_CLK, Viol);\n    $hold ( posedge CLK &&& CLK_rising, A12 , thold_A12_CLK, Viol);\n    $hold ( posedge CLK &&& CLK_rising, A13 , thold_A13_CLK, Viol);\n    $hold ( posedge CLK &&& CLK_rising, A14 , thold_A14_CLK, Viol);\n    $hold ( posedge CLK &&& CLK_rising, A15 , thold_A15_CLK, Viol);\n    $hold ( posedge CLK &&& CLK_rising, A16 , thold_A16_CLK, Viol);\n    $hold ( posedge CLK &&& CLK_rising, A17 , thold_A17_CLK, Viol);\n    $hold ( posedge CLK &&& CLK_rising, A18 , thold_A18_CLK, Viol);\n    $hold ( posedge CLK &&& CLK_rising, A19 , thold_A19_CLK, Viol);\n    $hold ( posedge CLK &&& CLK_rising, A20 , thold_A20_CLK, Viol);\n    $hold ( posedge CLK &&& CLK_rising, A21 , thold_A21_CLK, Viol);\n    $hold ( posedge CLK &&& CLK_rising, A22 , thold_A22_CLK, Viol);\n    $hold ( posedge CLK &&& CLK_rising, A23 , thold_A23_CLK, Viol);\n    $hold ( posedge CLK &&& CLK_rising, A24 , thold_A24_CLK, Viol);\n\n    $hold ( negedge CLK &&& CLK_falling, A1  , thold_A1_CLK, Viol);\n    $hold ( negedge CLK &&& CLK_falling, A2  , thold_A2_CLK, Viol);\n    $hold ( negedge CLK &&& CLK_falling, A3  , thold_A3_CLK, Viol);\n    $hold ( negedge CLK &&& CLK_falling, A4  , thold_A4_CLK, Viol);\n    $hold ( negedge CLK &&& CLK_falling, A5  , thold_A5_CLK, Viol);\n    $hold ( negedge CLK &&& CLK_falling, A6  , thold_A6_CLK, Viol);\n    $hold ( negedge CLK &&& CLK_falling, A7  , thold_A7_CLK, Viol);\n    $hold ( negedge CLK &&& CLK_falling, A8  , thold_A8_CLK, Viol);\n    $hold ( negedge CLK &&& CLK_falling, A9  , thold_A9_CLK, Viol);\n    $hold ( negedge CLK &&& CLK_falling, A10 , thold_A10_CLK, Viol);\n    $hold ( negedge CLK &&& CLK_falling, A11 , thold_A11_CLK, Viol);\n    $hold ( negedge CLK &&& CLK_falling, A12 , thold_A12_CLK, Viol);\n    $hold ( negedge CLK &&& CLK_falling, A13 , thold_A13_CLK, Viol);\n    $hold ( negedge CLK &&& CLK_falling, A14 , thold_A14_CLK, Viol);\n    $hold ( negedge CLK &&& CLK_falling, A15 , thold_A15_CLK, Viol);\n    $hold ( negedge CLK &&& CLK_falling, A16 , thold_A16_CLK, Viol);\n    $hold ( negedge CLK &&& CLK_falling, A17 , thold_A17_CLK, Viol);\n    $hold ( negedge CLK &&& CLK_falling, A18 , thold_A18_CLK, Viol);\n    $hold ( negedge CLK &&& CLK_falling, A19 , thold_A19_CLK, Viol);\n    $hold ( negedge CLK &&& CLK_falling, A20 , thold_A20_CLK, Viol);\n    $hold ( negedge CLK &&& CLK_falling, A21 , thold_A21_CLK, Viol);\n    $hold ( negedge CLK &&& CLK_falling, A22 , thold_A22_CLK, Viol);\n    $hold ( negedge CLK &&& CLK_falling, A23 , thold_A23_CLK, Viol);\n    $hold ( negedge CLK &&& CLK_falling, A24 , thold_A24_CLK, Viol);\n\n    $width ( posedge CENeg , tpw_CENeg_posedge );\n    $width ( posedge ADVNeg, tpw_ADVNeg_posedge );\n    $width ( negedge ADVNeg, tpw_ADVNeg_negedge );\n    $width ( posedge CLK   , tpw_CLK_posedge );\n    $width ( negedge CLK   , tpw_CLK_negedge );\n    $width ( posedge WENeg , tpw_WENeg_posedge );\n    $width ( negedge WENeg , tpw_WENeg_negedge );\n    $width ( negedge RSTNeg, tpw_RSTNeg_negedge );\n    $period( posedge CLK   , tperiod_CLK);\n    $period( negedge CLK   , tperiod_CLK);\n\nendspecify\n\n    //tdevice parameters aligned to model timescale\n\n    // Program EraseParameter\n    time tdevice_EraseParameter\n                            = tdevice_EraseParameter_td*1000; //2.5 sec;\n    // Parameter Block Erase - 12V\n    time tdevice_EraseMain = tdevice_EraseMain_td*1000; //4 sec;\n\n///////////////////////////////////////////////////////////////////////////////\n// Main Behavior Block                                                       //\n///////////////////////////////////////////////////////////////////////////////\n\n    always @(DQIn, DQOut)\n    begin\n        if (DQIn==DQOut)\n            deq=1'b1;\n        else\n            deq=1'b0;\n    end\n    // chech when data is generated from model to avoid setuphold check in\n    // those occasion\n    assign deg=deq;\n\n    // initialize memory and load preload files if any\n    initial\n    begin: InitMemory\n        integer i;\n        for (i=0;i<=MemSize;i=i+1)\n        begin\n            MemData[i]=MaxData;\n        end\n        if ((UserPreload) && !(mem_file_name == \"none\"))\n        begin\n            // File Read Section\n            //#i28f512p33_1 memory file\n            //#   /         - comment\n            //#   @aaaaa    - <aaaaa> stands for address\n            //#   dddd      - <dddd> is word to be written at Mem(aaaaa++)\n            //#                 (aaaaa is incremented at every load)\n            //#\n            //#   only first 1-6 columns are loaded. NO empty lines !\n            $readmemh(mem_file_name, MemData);\n        end\n\n        for (i=0;i<=BlockNum;i=i+1)\n        begin\n            OTP[i]=1'b0;\n        end\n        if ((UserPreload) && !(otp_blocks_file == \"none\"))\n            begin\n            // File Read Section\n            //#i28f512p33_1 memory file\n            //#   /         - comment\n            //#   @aaa      - <aaa> stands for address\n            //#   dddd      - <dddd> is word to be written at OTP(aaa++)\n            //#                 (aaa is incremented at every load)\n            //#\n            //#   only first 1-6 columns are loaded. NO empty lines !\n            $readmemh(otp_blocks_file, OTP);\n        end\n\n        PR[9'h80] = 16'hFFFE;\n        for (i=9'h81;i<=9'h109;i=i+1)\n        begin\n            PR[i]=MaxData;\n        end\n        if ((UserPreload) && !(prot_reg_file == \"none\"))\n        begin\n            // File Read Section\n            //#i28f512p33_1 memory file\n            //#   /         - comment\n            //#   @aaa      - <aaa> stands for address\n            //#   dddd      - <dddd> is word to be written at PR(aaa++)\n            //#                 (aaa is incremented at every load)\n            //#\n            //#   only first 1-6 columns are loaded. NO empty lines !\n            $readmemh(prot_reg_file, PR);\n        end\n\n        for (i=0;i<=BlockNum;i=i+1)\n        begin\n            Block_Lock[i] = LOCKED;\n            BlockLockBit[i] = 1'b1;\n            BlockLockDownBit[i] = 1'b0;\n        end\n    end\n\n    initial\n    begin\n        ///////////////////////////////////////////////////////////////////////\n        //CFI array data\n        ///////////////////////////////////////////////////////////////////////\n\n        CFI_array[9'h10]=16'h51;\n        CFI_array[9'h11]=16'h52;\n        CFI_array[9'h12]=16'h59;\n        CFI_array[9'h13]=16'h01;\n        CFI_array[9'h14]=16'h00;\n        CFI_array[9'h15]=16'h0A;\n        CFI_array[9'h16]=16'h01;\n        CFI_array[9'h17]=16'h00;\n        CFI_array[9'h18]=16'h00;\n        CFI_array[9'h19]=16'h00;\n        CFI_array[9'h1A]=16'h00;\n        // System Interface Information\n        CFI_array[9'h1B]=16'h23;\n        CFI_array[9'h1C]=16'h36;\n        CFI_array[9'h1D]=16'h85;\n        CFI_array[9'h1E]=16'h95;\n        CFI_array[9'h1F]=16'h08;\n        CFI_array[9'h20]=16'h09;\n        CFI_array[9'h21]=16'h0A;\n        CFI_array[9'h22]=16'h00;\n        CFI_array[9'h23]=16'h01;\n        CFI_array[9'h24]=16'h01;\n        CFI_array[9'h25]=16'h02;\n        CFI_array[9'h26]=16'h00;\n        // Device Geometry definition\n        CFI_array[9'h27]=16'h19;\n        CFI_array[9'h28]=16'h01;\n        CFI_array[9'h29]=16'h00;\n        CFI_array[9'h2A]=16'h06;\n        CFI_array[9'h2B]=16'h00;\n        CFI_array[9'h2C]=16'h02;\n        CFI_array[9'h2D]=16'hFE;\n        CFI_array[9'h2E]=16'h00;\n        CFI_array[9'h2F]=16'h00;\n        CFI_array[9'h30]=16'h02;\n        CFI_array[9'h31]=16'h03;\n        CFI_array[9'h32]=16'h00;\n        CFI_array[9'h33]=16'h80;\n        CFI_array[9'h34]=16'h00;\n        CFI_array[9'h35]=16'h00;\n        CFI_array[9'h36]=16'h00;\n        CFI_array[9'h37]=16'h00;\n        CFI_array[9'h38]=16'h00;\n        // Primary-vendor specific extended query\n        CFI_array[9'h10A]=16'h50;\n        CFI_array[9'h10B]=16'h52;\n        CFI_array[9'h10C]=16'h49;\n        CFI_array[9'h10D]=16'h31;\n        CFI_array[9'h10E]=16'h34;\n        CFI_array[9'h10F]=16'hE6;\n        CFI_array[9'h110]=16'h01;\n        CFI_array[9'h111]=16'h00;\n        CFI_array[9'h112]=16'h40; // TOP PARAMETER BLOCK UPPER DIE\n        CFI_array[9'h113]=16'h01;\n        CFI_array[9'h114]=16'h03;\n        CFI_array[9'h115]=16'h00;\n        CFI_array[9'h116]=16'h30;\n        CFI_array[9'h117]=16'h90;\n        // Protection register information\n        CFI_array[9'h118]=16'h02;\n        CFI_array[9'h119]=16'h80;\n        CFI_array[9'h11A]=16'h00;\n        CFI_array[9'h11B]=16'h03;\n        CFI_array[9'h11C]=16'h03;\n        CFI_array[9'h11D]=16'h89;\n        CFI_array[9'h11E]=16'h00;\n        CFI_array[9'h11F]=16'h00;\n        CFI_array[9'h120]=16'h00;\n        CFI_array[9'h121]=16'h00;\n        CFI_array[9'h122]=16'h00;\n        CFI_array[9'h123]=16'h00;\n        CFI_array[9'h124]=16'h10;\n        CFI_array[9'h125]=16'h00;\n        CFI_array[9'h126]=16'h04;\n        // Burst read information\n        CFI_array[9'h127]=16'h03;\n        CFI_array[9'h128]=16'h04;\n        CFI_array[9'h129]=16'h01;\n        CFI_array[9'h12A]=16'h02;\n        CFI_array[9'h12B]=16'h03;\n        CFI_array[9'h12C]=16'h07;\n        //Partition and Erase Block Region Information\n        CFI_array[9'h12D]=16'h01;\n        CFI_array[9'h12E]=16'h24;\n        CFI_array[9'h12F]=16'h00;\n        CFI_array[9'h130]=16'h01;\n        CFI_array[9'h131]=16'h00;\n        CFI_array[9'h132]=16'h11;\n        CFI_array[9'h133]=16'h00;\n        CFI_array[9'h134]=16'h00;\n        CFI_array[9'h135]=16'h02;\n        CFI_array[9'h136]=16'hFE;\n        CFI_array[9'h137]=16'h00;\n        CFI_array[9'h138]=16'h00;\n        CFI_array[9'h139]=16'h02;\n        CFI_array[9'h13A]=16'h64;\n        CFI_array[9'h13B]=16'h00;\n        CFI_array[9'h13C]=16'h02;\n        CFI_array[9'h13D]=16'h03;\n        CFI_array[9'h13E]=16'h00;\n        CFI_array[9'h13F]=16'h80;\n        CFI_array[9'h140]=16'h00;\n        CFI_array[9'h141]=16'h00;\n        CFI_array[9'h142]=16'h00;\n        CFI_array[9'h143]=16'h80;\n        CFI_array[9'h144]=16'h03;\n        CFI_array[9'h145]=16'h00;\n        CFI_array[9'h146]=16'h80;\n        CFI_array[9'h147]=16'h00;\n        CFI_array[9'h148]=16'h64;\n        CFI_array[9'h149]=16'h00;\n        CFI_array[9'h14A]=16'h02;\n        CFI_array[9'h14B]=16'h03;\n        CFI_array[9'h14C]=16'h00;\n        CFI_array[9'h14D]=16'h80;\n        CFI_array[9'h14E]=16'h00;\n        CFI_array[9'h14F]=16'h00;\n        CFI_array[9'h150]=16'h00;\n        CFI_array[9'h151]=16'h80;\n        CFI_array[9'h152]=16'h10;\n        CFI_array[9'h153]=16'h20;\n        CFI_array[9'h154]=16'h00;\n        CFI_array[9'h155]=16'h00;\n        CFI_array[9'h156]=16'h10;\n    end\n\n    initial\n    begin\n        current_state          = RESET_POWER_DOWN;\n        next_state             = RESET_POWER_DOWN;\n        read_state             = READ_ARRAY;\n\n        WordProgram_in         = 1'b0;\n        BuffProgram_in         = 1'b0;\n        BEFP_in                = 1'b0;\n        BEFPsetup_in           = 1'b0;\n        ParameterErase_in      = 1'b0;\n        MainErase_in           = 1'b0;\n        ProgramSuspend_in      = 1'b0;\n        EraseSuspend_in        = 1'b0;\n        RstDuringErsPrg_in     = 1'b0;\n\n        CLOCK           = 1'b0;\n        Write           = 1'b0;\n        Read            = 1'b0;\n        Pmode           = 1'b0;\n        abort           = 1'b0;\n        ExtendProgTime  = 1'b0;\n        AssertWAITOut   = 1'b0;\n        DeassertWAITOut = 1'b0;\n        read_out        = 1'b0;\n\n        SR      = 8'b10000000;\n        RCR     = 16'b1011111111001111;\n        LATCHED = 1'b0;\n        Viol    = 1'b0;\n        word_cntr = 0;\n\n    end\n\n    ///////////////////////////////////////////////////////////////////////////\n    //// Internal Delays\n    ///////////////////////////////////////////////////////////////////////////\n    always @(posedge BEFP_in)\n    begin:BEFP\n        BEFP_out = 1'b1;\n        #tdevice_BEFP BEFP_out = 1'b0;\n    end\n\n    always @(posedge BEFPsetup_in)\n    begin:BEFPsetup\n        BEFPsetup_out = 1'b1;\n        #tdevice_BEFPsetup BEFPsetup_out = 1'b0;\n    end\n\n    always @(posedge ProgramSuspend_in)\n    begin:ProgramSuspend\n        ProgramSuspend_out = 1'b1;\n        #tdevice_ProgramSuspend ProgramSuspend_out = 1'b0;\n    end\n\n    always @(posedge EraseSuspend_in)\n    begin:EraseSuspend\n        EraseSuspend_out = 1'b1;\n        #tdevice_EraseSuspend EraseSuspend_out = 1'b0;\n    end\n\n    always @(posedge RstDuringErsPrg_in)\n    begin:RstDuringErsPrg\n        RstDuringErsPrg_out = 1'b1;\n        #tdevice_RstDuringErsPrg RstDuringErsPrg_out = 1'b0;\n    end\n\n    //////////////////////////////////////////////////////////////\n    // Clock control\n    //////////////////////////////////////////////////////////////\n\n    always @ (posedge CLK_ipd)\n    begin : CLKControl1\n        if ((RSTNeg_ipd) && (~CENeg_ipd) && (WENeg_ipd) &&\n        (RCR[15] == 1'b0) && (RCR[6] == 1'b1) &&\n        (current_state != RESET_POWER_DOWN))\n        begin\n            CLOCK = 1'b1;\n            #1 CLOCK <= 1'b0;\n        end\n    end\n\n    always @ (negedge CLK_ipd)\n    begin : CLKControl2\n        if ((RSTNeg_ipd) && (~CENeg_ipd) && (WENeg_ipd) &&\n        (RCR[15] == 1'b0) && (RCR[6] == 1'b0) &&\n        (current_state != RESET_POWER_DOWN))\n        begin\n            CLOCK = 1'b1;\n            #1 CLOCK <= 1'b0;\n        end\n    end\n\n    always @ (negedge RSTNeg_ipd)\n    begin : RSTControl\n        if (WordProgram_out ||\n        BuffProgram_out ||\n        ParameterErase_out || MainErase_out || BEFP_out)\n        begin\n            RstDuringErsPrg_in = 1'b0;\n            #1 RstDuringErsPrg_in <= 1'b1;\n        end\n    end\n\n    //////////////////////////////////////////////////////////////////////////\n    //// bus cycle decode\n    //////////////////////////////////////////////////////////////////////////\n    always @ (falling_edge_ADVNeg or rising_edge_ADVNeg or rising_edge_CLOCK\n    or OENeg or RSTNeg or rising_edge_WENeg or rising_edge_CENeg or WENeg\n    or CENeg or Alow_event)\n    begin : BusCycleDecode\n        if (~RSTNeg || CENeg || falling_edge_ADVNeg)\n            LATCHED = 0;\n\n        if (RSTNeg && current_state != RESET_POWER_DOWN)\n        begin\n            if (~CENeg && ~LATCHED && ((rising_edge_ADVNeg && WENeg) ||\n            (~ADVNeg && WENeg && ~RCR[15] && rising_edge_CLOCK) ) )\n            begin\n                LatchedAddr = A;\n                ReadAddr = A;\n                LATCHED = 1'b1;\n                burst_cntr = 0;\n                BurstDelay = RCR[13:11];\n                case (RCR[2:0])\n                    3'b001: BurstLength = 4;\n                    3'b010: BurstLength = 8;\n                    3'b011: BurstLength = 16;\n                    3'b111: BurstLength = 0;\n                endcase\n                DataHold = 0;\n            end\n\n            // Write control\n            if (OENeg)\n            begin\n                if (~WENeg && ~CENeg)\n                    Write = 0;\n                else if ((~CENeg && rising_edge_WENeg) || (~WENeg &&\n                rising_edge_CENeg)||(rising_edge_CENeg && rising_edge_WENeg))\n                begin\n                    LatchedData = DQIn;\n                    LatchedAddr = A;\n                    Write = 1;\n                end\n            end\n\n            // Read control\n            if (RCR[15])\n            begin\n                if (WENeg && ~CENeg && ~OENeg)\n                begin\n                    if (~ADVNeg)\n                        ReadAddr = A;\n                    Read = 1;\n                end\n                else\n                begin\n                    Read = 0;\n                    Pmode = 0;\n                end\n                if (Read && Alow_event)\n                begin\n                    Pmode = 1;\n                    Pmode <= #2 0;\n                end\n            end\n            else\n            begin\n                if (rising_edge_CLOCK)\n                begin\n                    if (BurstDelay > 0)\n                    begin\n                        #1 BurstDelay = BurstDelay - 1;\n                        if (RCR[8] && (BurstDelay == 0 || (BurstDelay == 1\n                        && RCR[9] ) ) )\n                            DeassertWAITOut = ~(DeassertWAITOut);\n                    end\n                    else\n                    begin\n                        if (DataHold == 0)\n                        begin\n                            burst_cntr = burst_cntr + 1;\n                            if (~OENeg)\n                                Read = ~(Read);\n                            if (RCR[9])\n                                DataHold = 1;\n                            if ( (burst_cntr > (BurstLength - RCR[8]) ) &&\n                            BurstLength > 0)\n                                AssertWAITOut = ~(AssertWAITOut);\n                            else if (read_state == READ_ARRAY && ~RCR[9] &&\n                            RCR[13:11] > 4)\n                            begin\n                                if (~RCR[8])\n                                begin\n                                    if (burst_cntr > 4 || burst_cntr <= 0)\n                                        AssertWAITOut = ~(AssertWAITOut);\n                                    else\n                                        DeassertWAITOut = ~(DeassertWAITOut);\n                                end\n                                else\n                                begin\n                                    if (burst_cntr >= 4 || burst_cntr < 0)\n                                        AssertWAITOut = ~(AssertWAITOut);\n                                    else\n                                        DeassertWAITOut = ~(DeassertWAITOut);\n                                end\n                            end\n                                DeassertWAITOut = ~(DeassertWAITOut);\n                        end\n                        else\n                            DataHold = DataHold - 1;\n                    end\n                end\n            end\n        end\n    end\n\n//////////////////////////////////////////////////////////////////////////////\n//// sequential process for reset control and FSM state transition\n//////////////////////////////////////////////////////////////////////////////\n    always @(next_state)\n    begin : FSM\n        if (ExtendProgTime == 1'b0)\n            current_state = next_state;\n    end\n\n    ////////////////////////////////////////////////////////////////////////////\n    //     obtain 'LAST_EVENT information\n    ////////////////////////////////////////////////////////////////////////////\n    always @(negedge OENeg_ipd)\n    begin\n        OENeg_event = $time;\n    end\n    always @(negedge CENeg_ipd)\n    begin\n        CENeg_event = $time;\n    end\n    always @(A)\n    begin\n        ADDR_event = $time;\n    end\n\n    ///////////////////////////////////////////////////////////////////////////\n    // FSM - Combinational process for next state generation\n    ///////////////////////////////////////////////////////////////////////////\n    always @(falling_edge_RSTNeg or rising_edge_RSTNeg or rising_edge_Write or\n        RstDuringErsPrg_out_event or WordProgram_out_event or abort or\n        ProgramSuspend_out_event or BuffProgram_out_event\n        or ExtendProgTime_event or falling_edge_EraseSuspend_out or\n        ParameterErase_out_event or falling_edge_MainErase_out\n        or falling_edge_BEFPsetup_out or falling_edge_BEFP_out\n        )\n    begin : StateGen\n\n        if (falling_edge_RSTNeg)\n            next_state = RESET_POWER_DOWN;\n        else\n        begin\n            case (current_state)\n\n            RESET_POWER_DOWN :\n            begin\n                if (((rising_edge_RSTNeg && ~RstDuringErsPrg_out) ||\n                (RstDuringErsPrg_out_event && ~RstDuringErsPrg_out)) &&\n                $time > 0 )\n                begin\n                    next_state = READY;\n                end\n            end\n\n            READY:\n            begin\n                if (rising_edge_Write)\n                begin\n                    case (LatchedData)\n                        16'h10, 16'h40 : next_state = PROG_SETUP;\n                        16'hE8 : next_state = BP_SETUP;\n                        16'h20 : next_state = ERASE_SETUP;\n                        16'h80 : next_state = BEFP_SETUP;\n                        16'h60 : next_state = LOCK_SETUP;\n                        16'hC0 : next_state = OTP_SETUP;\n                        default : next_state = current_state;\n                    endcase\n                end\n            end\n\n            LOCK_SETUP  :\n            begin\n                if (rising_edge_Write)\n                    next_state = READY;\n            end\n\n            OTP_SETUP  :\n            begin\n                if (rising_edge_Write)\n                    next_state = OTP_BUSY;\n            end\n\n            OTP_BUSY :\n            begin\n                if (abort ||\n                (WordProgram_out_event && ~WordProgram_out) )\n                    next_state = READY;\n            end\n\n            PROG_SETUP :\n            begin\n                if (rising_edge_Write)\n                    next_state = PROG_BUSY;\n            end\n\n            PROG_BUSY :\n            begin\n                if (abort ||\n                (WordProgram_out_event && ~WordProgram_out) )\n                    next_state = READY;\n                else if (ProgramSuspend_out_event && ~ProgramSuspend_out)\n                    next_state = PROG_SUSP;\n            end\n\n            PROG_SUSP :\n            begin\n                if (rising_edge_Write && LatchedData == 16'hD0)\n                    next_state = PROG_BUSY;\n            end\n\n            BP_SETUP :\n            begin\n                if (rising_edge_Write)\n                begin\n                    word_cnt = LatchedData + 1;\n                    next_state = BP_LOAD;\n                end\n            end\n\n            BP_LOAD :\n            begin\n                if (rising_edge_Write)\n                begin\n                    word_cnt = word_cnt - 1;\n                    if (word_cnt == 0)\n                        next_state = BP_CONFIRM;\n                end\n            end\n\n            BP_CONFIRM :\n            begin\n                if (rising_edge_Write)\n                begin\n                    if (LatchedData == 16'hD0)\n                        next_state = BP_BUSY;\n                    else\n                        next_state = READY;\n                end\n            end\n\n            BP_BUSY :\n            begin\n                if (abort ||\n                (BuffProgram_out_event && ~BuffProgram_out && ~ExtendProgTime))\n                    next_state = READY;\n                else if (ProgramSuspend_out_event && ~ProgramSuspend_out)\n                    next_state = BP_SUSP;\n                else if (ExtendProgTime_event)\n                    next_state = current_state;\n            end\n\n            BP_SUSP :\n            begin\n                if (rising_edge_Write && LatchedData == 16'hD0)\n                    next_state = BP_BUSY;\n            end\n\n            ERASE_SETUP :\n            begin\n                if (rising_edge_Write)\n                begin\n                    if (LatchedData == 16'hD0)\n                        next_state = ERASE_BUSY;\n                    else\n                        next_state = READY;\n                end\n            end\n\n            ERASE_BUSY :\n            begin\n                if ((abort ||\n                (ParameterErase_out_event && ~ParameterErase_out) ||\n                (falling_edge_MainErase_out ) ) && ~suspended_erase)\n                    next_state = READY;\n                else if (falling_edge_EraseSuspend_out)\n                    next_state = ERS_SUSP;\n            end\n\n            ERS_SUSP :\n            begin\n                if (rising_edge_Write)\n                begin\n                    case (LatchedData)\n                        16'h10, 16'h40: next_state = PROG_SETUP_ERS_SUSP;\n                        16'hE8 : next_state = BP_SETUP_ERS_SUSP;\n                        16'hD0: next_state = ERASE_BUSY;\n                        16'h60: next_state = LOCK_SETUP_ERS_SUSP;\n                        default: next_state = current_state;\n                    endcase\n                end\n            end\n\n            PROG_SETUP_ERS_SUSP :\n            begin\n                if (rising_edge_Write)\n                    next_state = PROG_BUSY_ERS_SUSP;\n            end\n\n            PROG_BUSY_ERS_SUSP :\n            begin\n                if (abort ||\n                (WordProgram_out_event && ~WordProgram_out) )\n                    next_state = ERS_SUSP;\n                else if (ProgramSuspend_out_event && ~ProgramSuspend_out)\n                    next_state = PROG_SUSP_ERS_SUSP;\n            end\n\n            PROG_SUSP_ERS_SUSP :\n            begin\n                if (rising_edge_Write && LatchedData == 16'hD0)\n                    next_state = PROG_BUSY_ERS_SUSP;\n            end\n\n            BP_SETUP_ERS_SUSP :\n            begin\n                if (rising_edge_Write)\n                begin\n                    word_cnt = LatchedData + 1;\n                    next_state = BP_LOAD_ERS_SUSP;\n                end\n            end\n\n            BP_LOAD_ERS_SUSP :\n            begin\n                if (rising_edge_Write)\n                begin\n                    word_cnt = word_cnt - 1;\n                    if (word_cnt == 0)\n                        next_state = BP_CONFIRM_ERS_SUSP;\n                end\n            end\n\n            BP_CONFIRM_ERS_SUSP :\n            begin\n                if (rising_edge_Write)\n                begin\n                    if (LatchedData == 16'hD0)\n                        next_state = BP_BUSY_ERS_SUSP;\n                    else\n                        next_state = ERS_SUSP;\n                end\n            end\n\n            BP_BUSY_ERS_SUSP :\n            begin\n                if (abort ||\n                (BuffProgram_out_event && ~BuffProgram_out && ~ExtendProgTime))\n                    next_state = ERS_SUSP;\n                else if (ProgramSuspend_out_event && ~ProgramSuspend_out)\n                    next_state = BP_SUSP_ERS_SUSP;\n                else if (ExtendProgTime_event)\n                    next_state = current_state;\n            end\n\n            BP_SUSP_ERS_SUSP :\n            begin\n                if (rising_edge_Write && LatchedData == 16'hD0)\n                    next_state = BP_BUSY_ERS_SUSP;\n            end\n\n            LOCK_SETUP_ERS_SUSP :\n            begin\n                if (rising_edge_Write)\n                    next_state = ERS_SUSP;\n            end\n\n            BEFP_SETUP :\n            begin\n                if (rising_edge_Write)\n                begin\n                    if (LatchedData != 16'hD0)\n                        next_state = READY;\n                    else\n                    begin\n                        BEFP_block2 = BlockNumber(LatchedAddr);\n                        word_cnt = 32;\n                    end\n                end\n                else if (falling_edge_BEFPsetup_out)\n                begin\n                    if (SR[4] == 1'b0)\n                        next_state = BEFP_LOAD;\n                    else\n                        next_state = READY;\n                end\n            end\n\n            BEFP_LOAD :\n            begin\n                if (rising_edge_Write)\n                begin\n                    if ((BlockNumber(LatchedAddr) != BEFP_block2) &&\n                    LatchedData == 16'hFFFF)\n                        next_state = READY;\n                    else\n                    begin\n                        word_cnt = word_cnt - 1;\n                        if (word_cnt == 0)\n                            next_state = BEFP_BUSY;\n                    end\n                end\n            end\n\n            BEFP_BUSY :\n            begin\n                if (falling_edge_BEFP_out)\n                begin\n                    word_cnt = 32;\n                    next_state = BEFP_LOAD;\n                end\n            end\n            endcase\n        end\n    end\n\n    ////////////////////////////////////////////////////////////////////////////\n    // Functional\n    ////////////////////////////////////////////////////////////////////////////\n    always @(rising_edge_Write or WordProgram_out_event or\n             BuffProgram_out_event or falling_edge_RSTNeg or\n             ParameterErase_out_event or falling_edge_MainErase_out or\n             falling_edge_BEFPsetup_out or falling_edge_BEFP_out or\n             abort or falling_edge_EraseSuspend_out or ProgramSuspend_out_event)\n    begin\n\n        if (rising_edge_Write)\n        begin\n            if ((current_state != RESET_POWER_DOWN) &&\n            (current_state != OTP_BUSY) &&\n            (current_state != PROG_BUSY) &&\n            (current_state != BP_BUSY) &&\n            (current_state != ERASE_BUSY) &&\n            (current_state != PROG_BUSY_ERS_SUSP) &&\n            (current_state != BP_BUSY_ERS_SUSP) &&\n            (current_state != BEFP_SETUP) &&\n            (current_state != BEFP_LOAD) &&\n            (LatchedData == 8'h50))\n                SR = 8'b10000000;\n        end\n\n        case (current_state)\n\n            RESET_POWER_DOWN :\n            begin\n                SR = 8'b10000000;\n                for (i=0;i<=BlockNum;i=i+1)\n                begin\n                    Block_Lock[i] = LOCKED;\n                    BlockLockBit[i] = 1'b1;\n                    BlockLockDownBit[i] = 1'b0;\n                end\n                read_state = READ_ARRAY;\n                RCR = 16'b1011111111001111;\n            end\n\n            READY :\n            begin\n                if (rising_edge_Write)\n                begin\n                    case (LatchedData)\n                        16'hFF : read_state = READ_ARRAY;\n                        16'h70 : read_state = READ_STATUS;\n                        16'h90 : read_state = READ_ID;\n                        16'h98 : read_state = READ_QUERY;\n                    endcase\n                end\n            end\n\n            LOCK_SETUP, LOCK_SETUP_ERS_SUSP :\n            begin\n                if (rising_edge_Write)\n                begin\n                    block_number = BlockNumber(LatchedAddr);\n                    if (LatchedData == 16'h03)\n                    begin\n                        RCR = A[15:0];\n                        read_state = READ_ARRAY;\n                    end\n                    else if (LatchedData == 16'h01)\n                    begin\n                        read_state = READ_STATUS;\n                        if (Block_Lock[block_number] == UNLOCKED)\n                            Block_Lock[block_number] = LOCKED;\n                        BlockLockBit[block_number] = 1'b1;\n                    end\n                    else if (LatchedData == 16'hD0)\n                    begin\n                        read_state = READ_STATUS;\n                        if (!( (Block_Lock[block_number] == LOCKED_DOWN) &&\n                        WPNeg == 1'b0) )\n                        begin\n                            Block_Lock[block_number] = UNLOCKED;\n                            BlockLockBit[block_number] = 0;\n                        end\n                    end\n                    else if (LatchedData == 16'h2F)\n                    begin\n                        read_state = READ_STATUS;\n                        Block_Lock[block_number] = LOCKED_DOWN;\n                        BlockLockBit[block_number] = 1'b1;\n                        BlockLockDownBit[block_number] = 1'b1;\n                    end\n                    else\n                    begin\n                        read_state = READ_STATUS;\n                        SR[4] = 1'b1;\n                        SR[5] = 1'b1;\n                    end\n                end\n                else\n                    read_state = READ_STATUS;\n            end\n\n            OTP_SETUP :\n            begin\n                read_state = READ_STATUS;\n                if (rising_edge_Write)\n                begin\n                    DataBuff[0] = LatchedData;\n                    AddrBuff[0] = LatchedAddr;\n                    WordProgram_in = 1'b1;\n                    WordProgram_in <= #1 1'b0;\n                end\n            end\n\n            OTP_BUSY :\n            begin\n                if (rising_edge_Write)\n                begin\n                    case (LatchedData)\n                        16'hFF : read_state = READ_ARRAY;\n                        16'h70, 16'h90, 16'h98 : read_state = READ_STATUS;\n                    endcase\n                end\n\n                mem_bits = PR[9'h80];\n                prog_bits = PR[9'h89];\n\n                if (VPP != 1'b1)\n                begin\n                    SR[3] = 1'b1;\n                    SR[4] = 1'b1;\n                    SR[7] = 1'b1;\n                    abort = 1'b1;\n                    abort <= #1 1'b0;\n                end\n                else if ((AddrBuff[0] < 9'h80) || (AddrBuff[0] > 9'h109))\n                begin\n                    SR[4] = 1'b1;\n                    SR[7] = 1'b1;\n                    abort = 1'b1;\n                    abort <= #1 1'b0;\n                end\n                else if ((AddrBuff[0] > 9'h80) && (AddrBuff[0] < 9'h85))\n                begin\n                    SR[4] = 1'b1;\n                    SR[7] = 1'b1;\n                    abort = 1'b1;\n                    abort <= #1 1'b0;\n                end\n                else if ((AddrBuff[0] > 9'h84) && (AddrBuff[0] < 9'h89) &&\n                (mem_bits[1] != 1'b1))\n                begin\n                    SR[1] = 1'b1;\n                    SR[4] = 1'b1;\n                    SR[7] = 1'b1;\n                    abort = 1'b1;\n                    abort <= #1 1'b0;\n                end\n                else if ((AddrBuff[0] > 9'h89) && (AddrBuff[0] < 9'h10A) &&\n                (prog_bits[(AddrBuff[0]-9'h8A)/8] != 1'b1))\n                begin\n                    SR[1] = 1'b1;\n                    SR[4] = 1'b1;\n                    SR[7] = 1'b1;\n                    abort = 1'b1;\n                    abort <= #1 1'b0;\n                end\n                else\n                    SR[7] = 1'b0;\n\n                if (falling_edge_RSTNeg)\n                    PR[AddrBuff[0]] = -1;\n\n                if (WordProgram_out_event && ~WordProgram_out && ~abort)\n                begin\n                    if (PR[AddrBuff[0]] > -1)\n                    begin\n                        prog_bits = DataBuff[0];\n                        mem_bits = PR[AddrBuff[0]];\n                        for (i=0; i<= 15; i=i+1)\n                        begin\n                            if (prog_bits[i] == 0)\n                                mem_bits[i] = 0;\n                        end\n                        PR[AddrBuff[0]] = mem_bits;\n                    end\n                    SR[7] = 1;\n                end\n            end\n\n            PROG_SETUP, PROG_SETUP_ERS_SUSP :\n            begin\n                read_state = READ_STATUS;\n                if (rising_edge_Write)\n                begin\n                    DataBuff[0] = LatchedData;\n                    AddrBuff[0] = LatchedAddr;\n                    WordProgram_in = 1;\n                    WordProgram_in <= #1 0;\n                end\n            end\n\n            PROG_BUSY, PROG_BUSY_ERS_SUSP :\n            begin\n                SR[2] = 0;\n                if (rising_edge_Write)\n                begin\n                    case (LatchedData)\n                        16'hFF : read_state = READ_ARRAY;\n                        16'h70 : read_state = READ_STATUS;\n                        16'h90 : read_state = READ_ID;\n                        16'h98 : read_state = READ_QUERY;\n                        16'hB0 :\n                        begin\n                            ProgramSuspend_in = 1'b1;\n                            ProgramSuspend_in <= #1 1'b0;\n                        end\n                    endcase\n                end\n\n                block_number = BlockNumber(AddrBuff[0]);\n\n                if (VPP == 1'b0)\n                begin\n                    SR[3] = 1'b1;\n                    SR[4] = 1'b1;\n                    SR[7] = 1'b1;\n                    abort = 1'b1;\n                    abort <= #1 1'b0;\n                end\n                else if (OTP[block_number] == 1'b1)\n                begin\n                    SR[4] = 1'b1;\n                    SR[7] = 1'b1;\n                    abort = 1'b1;\n                    abort <= #1 1'b0;\n                end\n                else if (Block_Lock[block_number] != UNLOCKED)\n                begin\n                    SR[1] = 1'b1;\n                    SR[4] = 1'b1;\n                    SR[7] = 1'b1;\n                    abort = 1'b1;\n                    abort <= #1 1'b0;\n                end\n                else\n                    SR[7] = 1'b0;\n\n                if (falling_edge_RSTNeg )\n                    MemData[AddrBuff[0]] = -1;\n\n                if (WordProgram_out_event && ~WordProgram_out && ~abort)\n                begin\n                    if (MemData[AddrBuff[0]] > -1 )\n                    begin\n                        prog_bits = DataBuff[0];\n                        mem_bits = MemData[AddrBuff[0]];\n                        for (i= 0; i<= 15; i=i+1)\n                            if (prog_bits[i] == 0)\n                                mem_bits[i] = 0;\n                        MemData[AddrBuff[0]] = mem_bits;\n                    end\n                    SR[7] = 1;\n                end\n            end\n\n            PROG_SUSP, PROG_SUSP_ERS_SUSP :\n            begin\n                SR[2] = 1'b1;\n                SR[7] = 1'b1;\n\n                if (rising_edge_Write)\n                begin\n                    case (LatchedData)\n                        16'hFF : read_state = READ_ARRAY;\n                        16'h70 : read_state = READ_STATUS;\n                        16'h90 : read_state = READ_ID;\n                        16'h98 : read_state = READ_QUERY;\n                        16'hD0 :\n                        begin\n                            WordProgramResume = 1'b1;\n                            WordProgramResume <= #1 1'b0;\n                        end\n                    endcase\n                end\n            end\n\n            BP_SETUP, BP_SETUP_ERS_SUSP :\n            begin\n                read_state = READ_STATUS;\n\n                if (rising_edge_Write)\n                begin\n                    word_number = LatchedData;\n                    word_cntr   = 0;\n                end\n            end\n\n            BP_LOAD, BP_LOAD_ERS_SUSP :\n            begin\n                read_state = READ_STATUS;\n\n                if (rising_edge_Write)\n                begin\n                    DataBuff[word_cntr] = LatchedData;\n                    AddrBuff[word_cntr] = LatchedAddr;\n                    if (word_cntr == 0)\n                    begin\n                        lowest_addr = LatchedAddr;\n                        highest_addr = LatchedAddr;\n                    end\n                    else\n                    begin\n                        if (LatchedAddr < lowest_addr)\n                            lowest_addr = LatchedAddr;\n                        if (LatchedAddr > highest_addr)\n                            highest_addr = LatchedAddr;\n                    end\n                    word_cntr = word_cntr + 1;\n                end\n            end\n\n            BP_CONFIRM, BP_CONFIRM_ERS_SUSP :\n            begin\n                read_state = READ_STATUS;\n\n                if (rising_edge_Write)\n                begin\n                    if (LatchedData != 16'hD0)\n                    begin\n                        SR[7] = 1'b1;\n                        SR[5] = 1'b1;\n                        SR[4] = 1'b1;\n                    end\n                    else if (LatchedData == 16'hD0)\n                    begin\n                        BuffProgram_in = 1;\n                        BuffProgram_in <= #1 0;\n                    end\n                end\n            end\n\n            BP_BUSY, BP_BUSY_ERS_SUSP :\n            begin\n                SR[2] = 0;\n                if (rising_edge_Write)\n                begin\n                    case (LatchedData)\n                        16'hFF : read_state = READ_ARRAY;\n                        16'h70 : read_state = READ_STATUS;\n                        16'h90 : read_state = READ_ID;\n                        16'h98 : read_state = READ_QUERY;\n                        16'hB0 :\n                        begin\n                            suspended_bp = 1'b1;\n                            ProgramSuspend_in = 1'b1;\n                            ProgramSuspend_in <= #1 1'b0;\n                        end\n                    endcase\n                end\n\n                block_number = BlockNumber(AddrBuff[0]);\n\n                if (VPP == 0)\n                begin\n                    SR[3] = 1;\n                    SR[4] = 1;\n                    SR[7] = 1;\n                    abort = 1'b1;\n                    abort <= #1 1'b0;\n                end\n                else if (OTP[block_number] == 1)\n                begin\n                    SR[4] = 1;\n                    SR[7] = 1;\n                    abort = 1'b1;\n                    abort <= #1 1'b0;\n                end\n                else if (Block_Lock[block_number] != UNLOCKED)\n                begin\n                    SR[1] = 1;\n                    SR[4] = 1;\n                    SR[7] = 1;\n                    abort = 1'b1;\n                    abort <= #1 1'b0;\n                end\n                else if ((lowest_addr < AddrBuff[0]) ||\n                (highest_addr > (AddrBuff[0]+word_number)) &&\n                (word_number != -1))\n                begin\n                    SR[4] = 1;\n                    SR[7] = 1;\n                    abort = 1'b1;\n                    abort <= #1 1'b0;\n                end\n                else if (BlockNumber(highest_addr) != block_number)\n                begin\n                    SR[4] = 1;\n                    SR[5] = 1;\n                    SR[7] = 1;\n                    abort = 1'b1;\n                    abort <= #1 1'b0;\n                end\n                else\n                    SR[7] = 0;\n\n                if (falling_edge_RSTNeg)\n                begin\n                    for (j=0;j<=word_number; j=j+1)\n                        MemData[AddrBuff[j]] = -1;\n                end\n\n                if ( BuffProgram_out_event && ~BuffProgram_out\n                && ~suspended_bp && ~abort )\n                begin\n                    for (j=0; j<= word_number; j=j+1)\n                    begin\n                        if (MemData[AddrBuff[j]] > -1 )\n                        begin\n                            prog_bits = DataBuff[j];\n                            mem_bits = MemData[AddrBuff[j]];\n                            for (i=0; i<=15; i=i+1)\n                            begin\n                                if (prog_bits[i] == 1'b0)\n                                    mem_bits[i] = 1'b0;\n                            end\n                            MemData[AddrBuff[j]] = mem_bits;\n                        end\n                    end\n                    for (j=0; j<= word_number; j=j+1)\n                    begin\n                        if ((AddrBuff[j] / 32) != (AddrBuff[0]/32))\n                        begin\n                            ExtendProgTime = 1;\n                            ExtendProgTime <= #1 0;\n                            word_number = -1;\n                            BuffProgram_in = 1'b1;\n                            BuffProgram_in <= #1 1'b0;\n                        end\n                    end\n                    SR[7] = 1;\n                end\n            end\n\n            BP_SUSP, BP_SUSP_ERS_SUSP :\n            begin\n                SR[2] = 1'b1;\n                SR[7] = 1'b1;\n\n                if (rising_edge_Write)\n                begin\n                    case (LatchedData)\n                        16'hFF : read_state = READ_ARRAY;\n                        16'h70 : read_state = READ_STATUS;\n                        16'h90 : read_state = READ_ID;\n                        16'h98 : read_state = READ_QUERY;\n                        16'hD0 :\n                        begin\n                            suspended_bp = 1'b0;\n                            BP_ProgramResume = 1'b1;\n                            BP_ProgramResume <= #1 1'b0;\n                        end\n                    endcase\n                end\n            end\n\n            ERASE_SETUP :\n            begin\n                read_state = READ_STATUS;\n\n                if (rising_edge_Write)\n                begin\n                    if (LatchedData == 16'hD0)\n                    begin\n                        erasing_block = BlockNumber(LatchedAddr);\n                        if (BlockSize(erasing_block) == ParameterBlockSize)\n                        begin\n                            ParameterErase_in = 1;\n                            ParameterErase_in <= #1 0;\n                        end\n                        else\n                        begin\n                            MainErase_in = 1;\n                            MainErase_in <= #1 0;\n                        end\n                    end\n                    else\n                    begin\n                        SR[7] = 1'b1;\n                        SR[5] = 1'b1;\n                        SR[4] = 1'b1;\n                    end\n                end\n            end\n\n            ERASE_BUSY :\n            begin\n                SR[6] = 0;\n\n                if (rising_edge_Write)\n                begin\n                    case (LatchedData)\n                        16'hFF : read_state = READ_ARRAY;\n                        16'h70 : read_state = READ_STATUS;\n                        16'h90 : read_state = READ_ID;\n                        16'h98 : read_state = READ_QUERY;\n                        16'hB0 :\n                        begin\n                            suspended_erase = 1'b1;\n                            EraseSuspend_in = 1'b1;\n                            EraseSuspend_in <= #1 1'b0;\n                        end\n                    endcase\n                end\n\n                aborted = 1'b0;\n\n                if (VPP == 1'b0)\n                begin\n                    SR[3] = 1'b1;\n                    SR[5] = 1'b1;\n                    SR[7] = 1'b1;\n                    abort = 1'b1;\n                    abort <= #1 1'b0;\n                    aborted = 1'b1;\n                end\n                else if (OTP[erasing_block] == 1'b1)\n                begin\n                    SR[5] = 1'b1;\n                    SR[7] = 1'b1;\n                    abort = 1'b1;\n                    abort <= #1 1'b0;\n                    aborted = 1'b1;\n                end\n                else if (Block_Lock[erasing_block] != UNLOCKED)\n                begin\n                    SR[1] = 1'b1;\n                    SR[5] = 1'b1;\n                    SR[7] = 1'b1;\n                    abort = 1'b1;\n                    abort <= #1 1'b0;\n                    aborted = 1'b1;\n                end\n                else\n                    SR[7] = 1'b0;\n\n                block_size = BlockSize(erasing_block);\n                start_addr = StartBlockAddr(erasing_block);\n\n                if (~aborted)\n                begin\n                    for (i = 0; i< block_size; i=i+1 )\n                        MemData[start_addr + i] = -1;\n                end\n\n                if ( ( (ParameterErase_out_event && ~ParameterErase_out)\n                || (falling_edge_MainErase_out)) && ~abort && ~suspended_erase)\n                begin\n                    SR[7] = 1'b1;\n                    for (i=0;i<=block_size;i=i+1)\n                        MemData[start_addr + i] = MaxData;\n                end\n            end\n\n            ERS_SUSP :\n            begin\n                SR[6] = 1'b1;\n                SR[7] = 1'b1;\n\n                if (rising_edge_Write)\n                begin\n                    case (LatchedData)\n                        16'hFF : read_state = READ_ARRAY;\n                        16'h70 : read_state = READ_STATUS;\n                        16'h90 : read_state = READ_ID;\n                        16'h98 : read_state = READ_QUERY;\n                        16'hD0 :\n                        begin\n                            suspended_erase = 1'b0;\n                            if (BlockSize(erasing_block) == ParameterBlockSize)\n                            begin\n                                ParameterEraseResume = 1'b1;\n                                ParameterEraseResume <= #1 1'b0;\n                            end\n                            else\n                            begin\n                                MainEraseResume = 1'b1;\n                                MainEraseResume <= #1 1'b0;\n                            end\n                        end\n                    endcase\n                end\n            end\n\n            BEFP_SETUP :\n            begin\n                read_state = READ_STATUS;\n\n                if (rising_edge_Write && (LatchedData == 16'hD0))\n                begin\n                    BEFP_addr  = LatchedAddr;\n                    BEFP_block = BlockNumber(LatchedAddr);\n                    word_cntr = 0;\n                    if ((VPP != 1'b1) || (VPP_voltage != 9))\n                    begin\n                        SR[3] = 1'b1;\n                        SR[4] = 1'b1;\n                    end\n                    if (Block_Lock[BEFP_block] != UNLOCKED)\n                    begin\n                        SR[1] = 1'b1;\n                        SR[4] = 1'b1;\n                    end\n                    else if (((BEFP_addr % 32) != 0) ||\n                    (OTP[BEFP_block] == 1'b1))\n                        SR[4] = 1'b1;\n                    BEFPsetup_in = 1'b1;\n                    BEFPsetup_in <= #1 1'b0;\n                end\n                else if (falling_edge_BEFPsetup_out)\n                begin\n                    if (SR[4] == 0)\n                    begin\n                        SR[7] = 0;\n                        SR[0] = 0;\n                    end\n                end\n            end\n\n            BEFP_LOAD :\n            begin\n                if (rising_edge_Write)\n                begin\n                    if ((BlockNumber(LatchedAddr) != BEFP_block) &&\n                    (LatchedData == 16'hFFFF))\n                    begin\n                        SR[7] = 1'b1;\n                        SR[0] = 1'b0;\n                    end\n                    else\n                    begin\n                        DataBuff[word_cntr] = LatchedData;\n                        word_cntr = word_cntr + 1;\n                        if (word_cntr == 31)\n                        begin\n                            BEFP_in = 1'b1;\n                            BEFP_in <= #1 1'b0;\n                        end\n                    end\n                end\n            end\n\n            BEFP_BUSY :\n            begin\n\n                if (falling_edge_RSTNeg)\n                begin\n                    for (j = 0 ; j<= 31; j=j+1)\n                        MemData[BEFP_addr+j] = -1;\n                end\n\n                if (falling_edge_BEFP_out)\n                begin\n                    for (j=0;j<=31;j=j+1)\n                    begin\n                        if (MemData[BEFP_addr+j] > -1)\n                        begin\n                            prog_bits = DataBuff[j];\n                            mem_bits  = MemData[BEFP_addr + j];\n                            for (i=0;i<=15;i=i+1)\n                            begin\n                                if (prog_bits[i] == 1'b0)\n                                    mem_bits[i] = 1'b0;\n                            end\n                            MemData[BEFP_addr + j] = mem_bits;\n                        end\n                    end\n                    BEFP_addr = BEFP_addr + 32;\n                    if ((BEFP_addr > MemSize) ||\n                    (BlockNumber(BEFP_addr) > BEFP_block))\n                        BEFP_addr = BEFP_addr - BlockSize(BEFP_block);\n                    SR[0] = 1'b0;\n                    word_cntr = 0;\n                end\n                else\n                    SR[0] = 1'b1;\n            end\n\n        endcase\n    end\n\n    ///////////////////////////////////////////////////////////\n    // Combinatorial output generation\n    ///////////////////////////////////////////////////////////\n    always @(Ahigh_event or Alow_event or rising_edge_Read or\n        A_event or OENeg or falling_edge_Read or CENeg\n        )\n    begin : Output\n        case (read_state)\n            READ_ARRAY :\n            begin\n                if (RCR[15] == 1'b1)\n                begin\n                    if (Ahigh_event && ~ADVNeg)\n                        ReadAddr = A;\n                    else if (Alow_event)\n                        ReadAddr = ReadAddr - (ReadAddr % 4) + A[1:0];\n                end\n\n                if (current_state == PROG_BUSY ||\n                current_state == PROG_BUSY_ERS_SUSP ||\n                current_state == BP_BUSY ||\n                current_state == BP_BUSY_ERS_SUSP ||\n                current_state == ERASE_BUSY)\n                    DQOut_tmp = 16'bx;\n                else\n                begin\n                    if (MemData[ReadAddr] > -1)\n                        DQOut_tmp = MemData[ReadAddr];\n                    else\n                        DQOut_tmp = 16'bx;\n                end\n            end\n\n            READ_ID :\n            begin\n                if ( ( ( (ReadAddr-2) % MainBlockSize) == 0) ||\n                ((ReadAddr > (MemSize - MainBlockSize)) &&\n                (((ReadAddr-2) % ParameterBlockSize) == 0)))\n                begin\n                    DQOut_tmp[0] = BlockLockBit[BlockNumber(ReadAddr)];\n                    DQOut_tmp[1] = BlockLockDownBit[BlockNumber(ReadAddr)];\n                    DQOut_tmp[15:2] = 14'b0;\n                end\n                else if (ReadAddr == 0)\n                    DQOut_tmp = 16'h0089;\n                else if (ReadAddr == 1)\n                begin\n                    DQOut_tmp = DeviceID_T;\n                end\n                else if (ReadAddr == 5)\n                    DQOut_tmp = RCR;\n                else if ((ReadAddr >= 9'h80) && (ReadAddr <= 9'h109))\n                begin\n                    if (PR[ReadAddr] > -1)\n                        DQOut_tmp = PR[ReadAddr];\n                    else\n                        DQOut_tmp = 16'bx;\n                end\n            end\n\n            READ_QUERY :\n            begin\n                if (((ReadAddr >= 9'h10) && (ReadAddr <= 9'h38)) ||\n                ((ReadAddr >= 9'h10A) && (ReadAddr <= 9'h156)))\n                    DQOut_tmp = CFI_array[ReadAddr];\n                else\n                    DQOut_tmp = 16'b0;\n            end\n\n            READ_STATUS :\n            begin\n                DQOut_tmp[15:8] = 8'b0;\n                DQOut_tmp[7:0] = SR;\n            end\n        endcase\n\n        if (RCR[15] == 1'b1) // Asynchronous read\n        begin\n            if (rising_edge_Read || (Read && ((A_event && ~ADVNeg) ||\n            Alow_event)))\n                DQOut_zd = DQOut_tmp;\n            else if (falling_edge_Read)\n                DQOut_zd = 16'bz;\n        end\n        else // Burst read\n        begin\n            if (rising_edge_Read || falling_edge_Read)\n            begin\n                if ((burst_cntr > BurstLength) && (BurstLength != 0))\n                    read_out = 1'b0;\n                else if (read_state == READ_ARRAY)\n                begin\n                    if ((RCR[9] == 1'b0) && (RCR[13:11] > 4) &&\n                    ((burst_cntr >= 5) || (burst_cntr < 1)))\n                    begin\n                        read_out = 1'b0;\n                        if (burst_cntr >= 5)\n                            burst_cntr = 5 - RCR[13:11];\n                    end\n                    else\n                    begin\n                        read_out = 1'b1;\n                        if (ReadAddr < MemSize)\n                            ReadAddr = ReadAddr + 1;\n                        if ((RCR[3] == 1'b0) && (BurstLength != 0) &&\n                        ((ReadAddr % BurstLength) == 0))\n                            ReadAddr = ReadAddr - BurstLength;\n                    end\n                end\n                else\n                    read_out = 1'b1;\n\n                if (read_out)\n                begin\n                    DQOut_zd = DQOut_tmp;\n                end\n            end\n        end\n    end\n\n    always @(CENeg, OENeg)\n    begin : OutputDisable\n        if ((CENeg) || (OENeg))\n            DQOut_zd = 16'bz;\n        else if ((~CENeg) && (~OENeg) && (RCR[15] == 1'b0))\n            DQOut_zd = 16'bx;\n    end\n\n    ////////////////////////////////////////////////////////////////\n    // WAIT output control process\n    ////////////////////////////////////////////////////////////////\n    always @(AssertWAITOut_event or DeassertWAITOut_event or falling_edge_OENeg\n    or OENeg or CENeg or falling_edge_CENeg)\n    begin : WAITOut_control\n\n        if (OENeg || CENeg || ~RSTNeg || (current_state == RESET_POWER_DOWN))\n            WAITOut_zd = 1'bz;\n        else if ((falling_edge_OENeg && ~CENeg) ||\n        (falling_edge_CENeg && ~OENeg))\n        begin\n            if (RCR[15] == 1'b1)\n            begin\n                if (~RCR[10])\n                    WAITOut_zd = 1'b1;\n                else\n                    WAITOut_zd = 1'b0;\n            end\n            else\n            begin\n                if (~RCR[10])\n                    WAITOut_zd = 1'b0;\n                else\n                    WAITOut_zd = 1'b1;\n            end\n        end\n        else if (AssertWAITOut_event)\n        begin\n            if (~RCR[10])\n                WAITOut_zd = 1'b0;\n            else\n                WAITOut_zd = 1'b1;\n        end\n        else if (DeassertWAITOut_event)\n        begin\n            if (~RCR[10])\n                WAITOut_zd = 1'b1;\n            else\n                WAITOut_zd = 1'b0;\n        end\n    end\n\n    ///////////////////////////////////////////////////////////////////\n    // Timing control for erase start, suspend and resume\n    ///////////////////////////////////////////////////////////////////\n    always @(rising_edge_MainErase_in or rising_edge_ParameterErase_in or\n             RstDuringErsPrg_out_event or\n             abort_event or\n             rising_edge_ParameterEraseResume or EraseSuspend_event or\n             rising_edge_MainEraseResume )\n    begin : erase_time\n        merase_duration = tdevice_EraseMain;\n        perase_duration = tdevice_EraseParameter;\n\n        if (rising_edge_MainErase_in)\n        begin\n            melapsed = 0;\n            MainErase_out <= #1 1'b1;\n            ->merase_event;\n            mstart = $time;\n        end\n        if (rising_edge_ParameterErase_in)\n        begin\n            pelapsed = 0;\n            ParameterErase_out <= #1 1'b1;\n            ->perase_event;\n            pstart = $time;\n        end\n        if ((RstDuringErsPrg_out_event && ~RstDuringErsPrg_out) ||\n        abort_event)\n        begin\n            disable merase_process;\n            disable perase_process;\n            MainErase_out = 1'b0;\n            ParameterErase_out = 1'b0;\n        end\n\n        if (EraseSuspend_event && ~EraseSuspend_out)\n        begin\n            disable merase_process;\n            melapsed = $time - mstart;\n            merase_duration = merase_duration - melapsed;\n            disable perase_process;\n            pelapsed = $time - pstart;\n            perase_duration = perase_duration - pelapsed;\n        end\n        if (rising_edge_MainEraseResume)\n        begin\n            mstart = $time;\n            MainErase_out = 1'b1;\n            -> merase_event;\n        end\n        if (rising_edge_ParameterEraseResume)\n        begin\n            pstart = $time;\n            ParameterErase_out = 1'b1;\n            ->perase_event;\n        end\n    end\n\n    always @(merase_event)\n    begin : merase_process\n        #merase_duration MainErase_out = 1'b0;\n    end\n    always @(perase_event)\n    begin : perase_process\n        #perase_duration ParameterErase_out = 1'b0;\n    end\n\n    /////////////////////////////////////////////////////////////////\n    // Timing control for programming start, suspend and resume\n    /////////////////////////////////////////////////////////////////\n    time buffp_duration;\n    time wordp_duration;\n    time welapsed;\n    time elapsed;\n    event prog_event;\n    event buffp_event;\n    time wstart;\n    time start;\n    reg rising_edge_WordProgram_in = 1'b0;\n    reg rising_edge_BuffProgram_in = 1'b0;\n    reg rising_edge_WordProgramResume = 1'b0;\n    reg rising_edge_BP_ProgramResume = 1'b0;\n\n    always @(rising_edge_WordProgram_in or rising_edge_BuffProgram_in or\n             RstDuringErsPrg_out_event or\n             abort_event or\n             ProgramSuspend_out_event or rising_edge_WordProgramResume or\n             rising_edge_BP_ProgramResume)\n    begin\n        if (VPP_voltage != 9)\n        begin\n            buffp_duration = tdevice_BuffProgram;\n            wordp_duration = tdevice_WordProgram;\n        end\n        else\n        begin\n            buffp_duration = tdevice_BuffProgram9V;\n            wordp_duration = tdevice_WordProgram9V;\n        end\n\n        if (rising_edge_WordProgram_in)\n        begin\n            welapsed = 0;\n            WordProgram_out <= #1 1'b1;\n            -> prog_event;\n            wstart = $time;\n        end\n        if (rising_edge_BuffProgram_in)\n        begin\n            elapsed = 0;\n            BuffProgram_out = 1'b1;\n            -> buffp_event;\n            start = $time;\n        end\n        if ((RstDuringErsPrg_out_event && ~RstDuringErsPrg_out) ||\n        abort_event)\n        begin\n            disable prog_process;\n            disable buffp_process;\n            WordProgram_out = 1'b0;\n            BuffProgram_out = 1'b0;\n        end\n\n        if (ProgramSuspend_out_event && ~ProgramSuspend_out)\n        begin\n            disable prog_process;\n            disable buffp_process;\n            elapsed = $time - start;\n            welapsed = $time - wstart;\n            buffp_duration = buffp_duration - elapsed;\n            wordp_duration = wordp_duration - welapsed;\n        end\n        if (rising_edge_WordProgramResume)\n        begin\n            wstart = $time;\n            WordProgram_out = 1'b1;\n            -> prog_event;\n        end\n        if (rising_edge_BP_ProgramResume)\n        begin\n            start = $time;\n            BuffProgram_out = 1'b1;\n            -> buffp_event;\n        end\n    end\n\n    always @(prog_event)\n    begin : prog_process\n        #wordp_duration WordProgram_out = 1'b0;\n    end\n    always @(buffp_event)\n    begin : buffp_process\n        #buffp_duration BuffProgram_out = 1'b0;\n    end\n\n    ////////////////////////////////////////////////////////////////////\n    //Output timing control\n    ////////////////////////////////////////////////////////////////////\n    always @(DQOut_zd)\n    begin : OutputGen\n        if (DQOut_zd[0] !== 1'bz)\n        begin\n            CEDQ_t = CENeg_event  + CEDQ_01;\n            OEDQ_t = OENeg_event  + OEDQ_01;\n            ADDRDQ_t = ADDR_event + ADDRDQIN_01;\n            if (Pmode)\n                ADDRDQ_t = ADDR_event + ADDRDQPAGE_01;\n\n            FROMCE = ((CEDQ_t >= OEDQ_t) && (CEDQ_t >= $time));\n            FROMOE = ((OEDQ_t >= CEDQ_t) && (OEDQ_t >= $time));\n            FROMADDR = 1'b1;\n\n            DQOut_Pass = DQOut_zd;\n        end\n    end\n\n    always @(DQOut_zd)\n    begin\n        if (DQOut_zd[0] === 1'bz)\n        begin\n            disable OutputGen;\n            FROMCE = 1'b1;\n            FROMOE = 1'b1;\n            FROMADDR = 1'b0;\n            DQOut_Pass = DQOut_zd;\n        end\n    end\n\n    reg  BuffInOE, BuffInCE, BuffInADDRIN, BuffInADDRPAGE;\n    wire BuffOutOE, BuffOutCE, BuffOutADDRIN, BuffOutADDRPAGE;\n\n    BUFFER    BUFOE   (BuffOutOE, BuffInOE);\n    BUFFER    BUFCE   (BuffOutCE, BuffInCE);\n    BUFFER    BUFADDRIN (BuffOutADDRIN, BuffInADDRIN);\n    BUFFER    BUFADDRPAGE (BuffOutADDRPAGE, BuffInADDRPAGE);\n\n    initial\n    begin\n        BuffInOE   = 1'b1;\n        BuffInCE   = 1'b1;\n        BuffInADDRIN = 1'b1;\n        BuffInADDRPAGE = 1'b1;\n    end\n\n    always @(posedge BuffOutOE)\n    begin\n        OEDQ_01 = $time;\n    end\n    always @(posedge BuffOutCE)\n    begin\n        CEDQ_01 = $time;\n    end\n    always @(posedge BuffOutADDRIN)\n    begin\n        ADDRDQIN_01 = $time;\n    end\n    always @(posedge BuffOutADDRPAGE)\n    begin\n        ADDRDQPAGE_01 = $time;\n    end\n\n/////////////////////////////////////////////////////////////////////////////\n// functions & tasks\n/////////////////////////////////////////////////////////////////////////////\n    function integer BlockNumber;\n        input [HiAddrBit:0] ADDR;\n        integer block_number;\n    begin\n        block_number = ADDR / MainBlockSize;\n        if (block_number == (MemSize/MainBlockSize))\n            block_number = block_number +\n                (ADDR % MainBlockSize) / ParameterBlockSize;\n        BlockNumber = block_number;\n    end\n    endfunction\n\n    function integer StartBlockAddr;\n        input [16:0] block_number;\n        integer start_block_addr;\n    begin\n        start_block_addr = block_number * MainBlockSize;\n        if (block_number > (BlockNum - 3))\n            start_block_addr = start_block_addr\n                - (block_number + 3 - BlockNum) * MainBlockSize\n                + (block_number + 3 - BlockNum) * ParameterBlockSize;\n        StartBlockAddr = start_block_addr;\n    end\n    endfunction\n\n    function integer BlockSize;\n        input [16:0] block_number;\n        integer block_number;\n        integer block_size;\n    begin\n        if ((block_number < 4)  ||\n        (block_number > (BlockNum - 4)) )\n            block_size = ParameterBlockSize;\n        else\n            block_size = MainBlockSize;\n        BlockSize = block_size;\n    end\n    endfunction\n\n    ////////////////////////////////////////////////////////////////\n    // edge controll processes\n    ////////////////////////////////////////////////////////////////\n    always @(negedge ADVNeg)\n    begin\n        falling_edge_ADVNeg = 1;\n        #1 falling_edge_ADVNeg = 0;\n    end\n\n    always @(posedge ADVNeg)\n    begin\n        rising_edge_ADVNeg  = 1;\n        #1 rising_edge_ADVNeg = 0;\n    end\n\n    always @(posedge CLOCK)\n    begin\n        rising_edge_CLOCK = 1;\n        #1 rising_edge_CLOCK = 0;\n    end\n\n    always @(negedge RSTNeg)\n    begin\n        falling_edge_RSTNeg = 1;\n        #1 falling_edge_RSTNeg = 0;\n    end\n\n    always @(posedge RSTNeg)\n    begin\n        rising_edge_RSTNeg = 1;\n        #1 rising_edge_RSTNeg = 0;\n    end\n\n    always @(posedge Write)\n    begin\n        rising_edge_Write = 1;\n        #1 rising_edge_Write = 0;\n    end\n\n    always @(RstDuringErsPrg_out)\n    begin\n        RstDuringErsPrg_out_event = 1;\n        #1 RstDuringErsPrg_out_event = 0;\n    end\n\n    always @(WordProgram_out)\n    begin\n        WordProgram_out_event = 1;\n        #1 WordProgram_out_event = 0;\n    end\n\n    always @(ProgramSuspend_out)\n    begin\n        ProgramSuspend_out_event = 1;\n        #1 ProgramSuspend_out_event = 0;\n    end\n\n    always @(BuffProgram_out)\n    begin\n        if (~suspended_bp)\n        begin\n            BuffProgram_out_event = 1;\n            #1 BuffProgram_out_event = 0;\n        end\n    end\n\n    always @(posedge ExtendProgTime)\n    begin\n        ExtendProgTime_event = 1;\n        #1 ExtendProgTime_event = 0;\n    end\n\n    always @(ParameterErase_out)\n    begin\n        ParameterErase_out_event = 1;\n        #1 ParameterErase_out_event = 0;\n    end\n\n    always @(negedge MainErase_out)\n    begin\n        falling_edge_MainErase_out = 1;\n        #1 falling_edge_MainErase_out = 0;\n    end\n\n    always @(negedge EraseSuspend_out)\n    begin\n        falling_edge_EraseSuspend_out = 1;\n        #1 falling_edge_EraseSuspend_out = 0;\n    end\n\n    always @(negedge BEFPsetup_out)\n    begin\n        falling_edge_BEFPsetup_out = 1;\n        #1 falling_edge_BEFPsetup_out = 0;\n    end\n\n    always @(negedge BEFP_out)\n    begin\n        falling_edge_BEFP_out = 1;\n        #1 falling_edge_BEFP_out = 0;\n    end\n\n    always @(A[HiAddrBit:2])\n    begin\n        Ahigh_event = 1;\n        #1 Ahigh_event = 0;\n    end\n\n    always @(A[1:0])\n    begin\n        Alow_event = 1;\n        #1 Alow_event = 0;\n    end\n\n    always @(A)\n    begin\n        A_event = 1;\n        #1 A_event = 0;\n    end\n\n    always @(posedge Read)\n    begin\n        rising_edge_Read = 1;\n        #1 rising_edge_Read = 0;\n    end\n\n    always @(negedge Read)\n    begin\n        falling_edge_Read = 1;\n        #1 falling_edge_Read = 0;\n    end\n\n    always @(posedge CENeg)\n    begin\n        rising_edge_CENeg = 1;\n        #1 rising_edge_CENeg = 0;\n    end\n\n    always @(posedge OENeg)\n    begin\n        rising_edge_OENeg = 1;\n        #1 rising_edge_OENeg = 0;\n    end\n\n    always @(AssertWAITOut)\n    begin\n        AssertWAITOut_event = 1;\n        #1 AssertWAITOut_event = 0;\n    end\n\n    always @(DeassertWAITOut)\n    begin\n        DeassertWAITOut_event = 1;\n        #1 DeassertWAITOut_event = 0;\n    end\n\n    always @(negedge OENeg)\n    begin\n        falling_edge_OENeg = 1;\n        #1 falling_edge_OENeg = 0;\n    end\n\n    always @(negedge CENeg)\n    begin\n        falling_edge_CENeg = 1;\n        #1 falling_edge_CENeg = 0;\n    end\n\n    always @(posedge WENeg)\n    begin\n        rising_edge_WENeg = 1;\n        #1 rising_edge_WENeg = 0;\n    end\n\n    always @(posedge WordProgram_in)\n    begin\n        rising_edge_WordProgram_in = 1'b1;\n        #1 rising_edge_WordProgram_in = 1'b0;\n    end\n\n    always @(posedge BuffProgram_in)\n    begin\n        rising_edge_BuffProgram_in = 1'b1;\n        #1 rising_edge_BuffProgram_in = 1'b0;\n    end\n\n    always @(posedge BP_ProgramResume)\n    begin\n        rising_edge_BP_ProgramResume = 1'b1;\n        #1 rising_edge_BP_ProgramResume = 1'b0;\n    end\n    always @(posedge WordProgramResume)\n    begin\n        rising_edge_WordProgramResume = 1'b1;\n        #1 rising_edge_WordProgramResume = 1'b0;\n    end\n\n    always @(posedge MainErase_in)\n    begin\n        rising_edge_MainErase_in = 1'b1;\n        #1 rising_edge_MainErase_in = 1'b0;\n    end\n\n    always @(posedge ParameterErase_in)\n    begin\n        rising_edge_ParameterErase_in = 1'b1;\n        #1 rising_edge_ParameterErase_in = 1'b0;\n    end\n\n    always @(posedge MainEraseResume)\n    begin\n        rising_edge_MainEraseResume = 1'b1;\n        #1 rising_edge_MainEraseResume = 1'b0;\n    end\n\n    always @(posedge ParameterEraseResume)\n    begin\n        rising_edge_ParameterEraseResume = 1'b1;\n        #1 rising_edge_ParameterEraseResume = 1'b0;\n    end\n\n    always @(EraseSuspend_out)\n    begin\n        EraseSuspend_event = 1'b1;\n        #1 EraseSuspend_event = 1'b0;\n    end\n\nendmodule\n\n//////////////////////////////////////////////////////////////////////////////\n// MODULE DECLARATION, Bottom Parameter Block Configuration                 //\n//////////////////////////////////////////////////////////////////////////////\nmodule i28f256p33_2\n    (\n        A24             ,\n        A23             ,\n        A22             ,\n        A21             ,\n        A20             ,\n        A19             ,\n        A18             ,\n        A17             ,\n        A16             ,\n        A15             ,\n        A14             ,\n        A13             ,\n        A12             ,\n        A11             ,\n        A10             ,\n        A9              ,\n        A8              ,\n        A7              ,\n        A6              ,\n        A5              ,\n        A4              ,\n        A3              ,\n        A2              ,\n        A1              ,\n\n        DQ15            ,\n        DQ14            ,\n        DQ13            ,\n        DQ12            ,\n        DQ11            ,\n        DQ10            ,\n        DQ9             ,\n        DQ8             ,\n        DQ7             ,\n        DQ6             ,\n        DQ5             ,\n        DQ4             ,\n        DQ3             ,\n        DQ2             ,\n        DQ1             ,\n        DQ0             ,\n\n        ADVNeg          ,\n        CENeg           ,\n        CLK             ,\n        OENeg           ,\n        RSTNeg          ,\n        WENeg           ,\n        WPNeg           ,\n        VPP             ,\n\n        WAITOut\n     );\n\n////////////////////////////////////////////////////////////////////////\n// Port / Part Pin Declarations\n////////////////////////////////////////////////////////////////////////\n    input  A24             ;\n    input  A23             ;\n    input  A22             ;\n    input  A21             ;\n    input  A20             ;\n    input  A19             ;\n    input  A18             ;\n    input  A17             ;\n    input  A16             ;\n    input  A15             ;\n    input  A14             ;\n    input  A13             ;\n    input  A12             ;\n    input  A11             ;\n    input  A10             ;\n    input  A9              ;\n    input  A8              ;\n    input  A7              ;\n    input  A6              ;\n    input  A5              ;\n    input  A4              ;\n    input  A3              ;\n    input  A2              ;\n    input  A1              ;\n\n    inout  DQ15            ;\n    inout  DQ14            ;\n    inout  DQ13            ;\n    inout  DQ12            ;\n    inout  DQ11            ;\n    inout  DQ10            ;\n    inout  DQ9             ;\n    inout  DQ8             ;\n    inout  DQ7             ;\n    inout  DQ6             ;\n    inout  DQ5             ;\n    inout  DQ4             ;\n    inout  DQ3             ;\n    inout  DQ2             ;\n    inout  DQ1             ;\n    inout  DQ0             ;\n\n    input  ADVNeg          ;\n    input  CENeg           ;\n    input  CLK             ;\n    input  OENeg           ;\n    input  RSTNeg          ;\n    input  WENeg           ;\n    input  WPNeg           ;\n    input  VPP             ;\n\n    output WAITOut         ;\n\n    // interconnect path delay signals\n    wire  A24_ipd  ;\n    wire  A23_ipd  ;\n    wire  A22_ipd  ;\n    wire  A21_ipd  ;\n    wire  A20_ipd  ;\n    wire  A19_ipd  ;\n    wire  A18_ipd  ;\n    wire  A17_ipd  ;\n    wire  A16_ipd  ;\n    wire  A15_ipd  ;\n    wire  A14_ipd  ;\n    wire  A13_ipd  ;\n    wire  A12_ipd  ;\n    wire  A11_ipd  ;\n    wire  A10_ipd  ;\n    wire  A9_ipd   ;\n    wire  A8_ipd   ;\n    wire  A7_ipd   ;\n    wire  A6_ipd   ;\n    wire  A5_ipd   ;\n    wire  A4_ipd   ;\n    wire  A3_ipd   ;\n    wire  A2_ipd   ;\n    wire  A1_ipd   ;\n\n    wire [23 : 0] A;\n    assign A = {\n                A24_ipd,\n                A23_ipd,\n                A22_ipd,\n                A21_ipd,\n                A20_ipd,\n                A19_ipd,\n                A18_ipd,\n                A17_ipd,\n                A16_ipd,\n                A15_ipd,\n                A14_ipd,\n                A13_ipd,\n                A12_ipd,\n                A11_ipd,\n                A10_ipd,\n                A9_ipd,\n                A8_ipd,\n                A7_ipd,\n                A6_ipd,\n                A5_ipd,\n                A4_ipd,\n                A3_ipd,\n                A2_ipd,\n                A1_ipd };\n\n    wire  DQ15_ipd  ;\n    wire  DQ14_ipd  ;\n    wire  DQ13_ipd  ;\n    wire  DQ12_ipd  ;\n    wire  DQ11_ipd  ;\n    wire  DQ10_ipd  ;\n    wire  DQ9_ipd   ;\n    wire  DQ8_ipd   ;\n    wire  DQ7_ipd   ;\n    wire  DQ6_ipd   ;\n    wire  DQ5_ipd   ;\n    wire  DQ4_ipd   ;\n    wire  DQ3_ipd   ;\n    wire  DQ2_ipd   ;\n    wire  DQ1_ipd   ;\n    wire  DQ0_ipd   ;\n\n    wire [15 : 0 ] DQIn;\n    assign DQIn = {DQ15_ipd,\n                   DQ14_ipd,\n                   DQ13_ipd,\n                   DQ12_ipd,\n                   DQ11_ipd,\n                   DQ10_ipd,\n                   DQ9_ipd,\n                   DQ8_ipd,\n                   DQ7_ipd,\n                   DQ6_ipd,\n                   DQ5_ipd,\n                   DQ4_ipd,\n                   DQ3_ipd,\n                   DQ2_ipd,\n                   DQ1_ipd,\n                   DQ0_ipd };\n\n    wire [15 : 0 ] DQOut;\n    assign DQOut = {DQ15,\n                    DQ14,\n                    DQ13,\n                    DQ12,\n                    DQ11,\n                    DQ10,\n                    DQ9,\n                    DQ8,\n                    DQ7,\n                    DQ6,\n                    DQ5,\n                    DQ4,\n                    DQ3,\n                    DQ2,\n                    DQ1,\n                    DQ0 };\n\n    wire  ADVNeg_ipd      ;\n    wire  CENeg_ipd       ;\n    wire  CLK_ipd         ;\n    wire  OENeg_ipd       ;\n    wire  RSTNeg_ipd      ;\n    wire  WENeg_ipd       ;\n    wire  WPNeg_ipd       ;\n\n    wire  DQ15_zd  ;\n    wire  DQ14_zd  ;\n    wire  DQ13_zd  ;\n    wire  DQ12_zd  ;\n    wire  DQ11_zd  ;\n    wire  DQ10_zd  ;\n    wire  DQ9_zd   ;\n    wire  DQ8_zd   ;\n    wire  DQ7_zd   ;\n    wire  DQ6_zd   ;\n    wire  DQ5_zd   ;\n    wire  DQ4_zd   ;\n    wire  DQ3_zd   ;\n    wire  DQ2_zd   ;\n    wire  DQ1_zd   ;\n    wire  DQ0_zd   ;\n\n    wire  DQ15_Pass  ;\n    wire  DQ14_Pass  ;\n    wire  DQ13_Pass  ;\n    wire  DQ12_Pass  ;\n    wire  DQ11_Pass  ;\n    wire  DQ10_Pass  ;\n    wire  DQ9_Pass   ;\n    wire  DQ8_Pass   ;\n    wire  DQ7_Pass   ;\n    wire  DQ6_Pass   ;\n    wire  DQ5_Pass   ;\n    wire  DQ4_Pass   ;\n    wire  DQ3_Pass   ;\n    wire  DQ2_Pass   ;\n    wire  DQ1_Pass   ;\n    wire  DQ0_Pass   ;\n\n    reg [15 : 0] DQOut_zd = 16'bz;\n    reg [15 : 0] DQOut_Pass = 16'bz;\n\n    assign {DQ15_zd,\n            DQ14_zd,\n            DQ13_zd,\n            DQ12_zd,\n            DQ11_zd,\n            DQ10_zd,\n            DQ9_zd,\n            DQ8_zd,\n            DQ7_zd,\n            DQ6_zd,\n            DQ5_zd,\n            DQ4_zd,\n            DQ3_zd,\n            DQ2_zd,\n            DQ1_zd,\n            DQ0_zd  } = DQOut_zd;\n\n    assign {DQ15_Pass,\n            DQ14_Pass,\n            DQ13_Pass,\n            DQ12_Pass,\n            DQ11_Pass,\n            DQ10_Pass,\n            DQ9_Pass,\n            DQ8_Pass,\n            DQ7_Pass,\n            DQ6_Pass,\n            DQ5_Pass,\n            DQ4_Pass,\n            DQ3_Pass,\n            DQ2_Pass,\n            DQ1_Pass,\n            DQ0_Pass  } = DQOut_Pass;\n\n    reg WAITOut_zd = 1'bz;\n\n    parameter mem_file_name   = \"none\";\n    parameter otp_blocks_file = \"none\";\n    parameter prot_reg_file   = \"none\";\n    parameter UserPreload     = 1'b0;\n    parameter TimingModel     = \"DefaultTimingModel\";\n    parameter VPP_voltage = 9;    // this parameter specifies if\n                                  // 9V or 2V is applied to Vpp pin\n                                  // (when VPP pin is 1'b1)\n\n    parameter MaxData            = 16'hFFFF;\n    parameter HiAddrBit          = 23;\n    parameter MemSize            = 32'hFFFFFF;\n    parameter BlockNum           = 258;\n    parameter DeviceID_B         = 16'h8922;\n    parameter DeviceID_T         = 16'h891F;\n    parameter MainBlockSize      = 32'h10000;\n    parameter ParameterBlockSize = 32'h04000;\n\n    // If speedsimulation is needed uncomment following line\n\n//       `define SPEEDSIM;\n\n    // FSM states\n    parameter        RESET_POWER_DOWN    = 5'd0;\n    parameter        READY               = 5'd1;\n    parameter        LOCK_SETUP          = 5'd2;\n    parameter        OTP_SETUP           = 5'd3;\n    parameter        OTP_BUSY            = 5'd4;\n    parameter        PROG_SETUP          = 5'd5;\n    parameter        PROG_BUSY           = 5'd6;\n    parameter        PROG_SUSP           = 5'd7;\n    parameter        BP_SETUP            = 5'd8;\n    parameter        BP_LOAD             = 5'd9;\n    parameter        BP_CONFIRM          = 5'd10;\n    parameter        BP_BUSY             = 5'd11;\n    parameter        BP_SUSP             = 5'd12;\n    parameter        ERASE_SETUP         = 5'd13;\n    parameter        ERASE_BUSY          = 5'd14;\n    parameter        ERS_SUSP            = 5'd15;\n    parameter        PROG_SETUP_ERS_SUSP = 5'd16;\n    parameter        PROG_BUSY_ERS_SUSP  = 5'd17;\n    parameter        PROG_SUSP_ERS_SUSP  = 5'd18;\n    parameter        BP_SETUP_ERS_SUSP   = 5'd19;\n    parameter        BP_LOAD_ERS_SUSP    = 5'd20;\n    parameter        BP_CONFIRM_ERS_SUSP = 5'd21;\n    parameter        BP_BUSY_ERS_SUSP    = 5'd22;\n    parameter        BP_SUSP_ERS_SUSP    = 5'd23;\n    parameter        LOCK_SETUP_ERS_SUSP = 5'd24;\n    parameter        BEFP_SETUP          = 5'd25;\n    parameter        BEFP_LOAD           = 5'd26;\n    parameter        BEFP_BUSY           = 5'd27;\n\n    // read mode\n    parameter        READ_ARRAY   = 2'd0;\n    parameter        READ_ID      = 2'd1;\n    parameter        READ_QUERY   = 2'd2;\n    parameter        READ_STATUS  = 2'd3;\n\n    reg [5:0]      current_state;\n    reg [5:0]      next_state;\n\n    reg [1:0]      read_state;\n\n    reg            deq;\n\n    // Memory declaration\n    integer MemData[0:MemSize];\n\n    // internal delays\n    reg WordProgram_in         = 1'b0;\n    reg WordProgram_out        = 1'b0;\n    reg BuffProgram_in         = 1'b0;\n    reg BuffProgram_out        = 1'b0;\n    reg BEFP_in                = 1'b0;\n    reg BEFP_out               = 1'b0;\n    reg BEFPsetup_in           = 1'b0;\n    reg BEFPsetup_out          = 1'b0;\n    reg ParameterErase_in      = 1'b0;\n    reg MainErase_in           = 1'b0;\n    reg ParameterErase_out     = 1'b0;\n    reg MainErase_out          = 1'b0;\n    reg ProgramSuspend_in      = 1'b0;\n    reg ProgramSuspend_out     = 1'b0;\n    reg EraseSuspend_in        = 1'b0;\n    reg EraseSuspend_out       = 1'b0;\n    reg RstDuringErsPrg_in     = 1'b0;\n    reg RstDuringErsPrg_out    = 1'b0;\n\n    // event control registers\n    reg falling_edge_ADVNeg = 1'b0;\n    reg falling_edge_RSTNeg = 1'b0;\n    reg falling_edge_BEFPsetup_out = 1'b0;\n    reg falling_edge_BEFP_out = 1'b0;\n    reg falling_edge_Read  = 1'b0;\n    reg falling_edge_OENeg = 1'b0;\n    reg falling_edge_CENeg = 1'b0;\n    reg rising_edge_ADVNeg = 1'b0;\n    reg rising_edge_CLOCK  = 1'b0;\n    reg rising_edge_WENeg  = 1'b0;\n    reg rising_edge_CENeg  = 1'b0;\n    reg rising_edge_RSTNeg = 1'b0;\n    reg rising_edge_Write  = 1'b0;\n    reg rising_edge_Read   = 1'b0;\n    reg RstDuringErsPrg_out_event = 1'b0;\n    reg WordProgram_out_event    = 1'b0;\n    reg abort_event              = 1'b0;\n    reg ProgramSuspend_out_event = 1'b0;\n    reg BuffProgram_out_event    = 1'b0;\n    reg ExtendProgTime_event     = 1'b0;\n    reg ParameterErase_out_event = 1'b0;\n    reg falling_edge_MainErase_out    = 1'b0;\n    reg falling_edge_EraseSuspend_out = 1'b0;\n    reg Ahigh_event           = 1'b0;\n    reg Alow_event            = 1'b0;\n    reg A_event               = 1'b0;\n    reg rising_edge_OENeg     = 1'b0;\n    reg AssertWAITOut_event   = 1'b0;\n    reg DeassertWAITOut_event = 1'b0;\n    reg rising_edge_MainErase_in      = 1'b0;\n    reg rising_edge_ParameterErase_in = 1'b0;\n    reg EraseSuspend_event            = 1'b0;\n    reg rising_edge_MainEraseResume   = 1'b0;\n    reg rising_edge_ParameterEraseResume = 1'b0;\n\n    integer i,j;\n\n    // Bus cycle decode\n    reg CLOCK = 1'b0;\n\n    reg Write = 1'b0;\n    reg Read  = 1'b0;\n\n    reg Pmode = 1'b0;\n\n    // Functional\n    reg abort           = 1'b0;\n\n    reg ExtendProgTime  = 1'b0;\n\n    reg AssertWAITOut   = 1'b0;\n    reg DeassertWAITOut = 1'b0;\n\n    //Block Lock Status\n    parameter UNLOCKED    = 2'd0;\n    parameter LOCKED      = 2'd1;\n    parameter LOCKED_DOWN = 2'd2;\n    integer Block_Lock[BlockNum:0];\n    reg [BlockNum:0] BlockLockBit;\n    reg [BlockNum:0] BlockLockDownBit;\n    reg OTP[0:BlockNum];\n\n    // Status Register\n    reg[7:0]    SR   = 8'b10000000;\n\n    // Read Configuration Register\n    reg[15:0]   RCR   = 16'b1011111111001111;\n\n    // Protection registers\n    integer PR[9'h80:9'h109];\n\n    // CFI array\n    integer CFI_array[9'h10:9'h156];\n\n    reg LATCHED = 1'b0;\n    reg [15:0] LatchedData;\n    reg [HiAddrBit:0] LatchedAddr;\n    integer ReadAddr;\n\n    integer DataBuff[0:31];\n    integer AddrBuff[0:31];\n\n    integer burst_cntr;\n    integer BurstLength;\n    integer BurstDelay;\n    integer DataHold;\n\n    integer WCount;\n    integer word_cntr;\n    integer word_cnt;\n    integer word_number;\n    integer block_number;\n    integer erasing_block;\n\n    integer lowest_addr;\n    integer highest_addr;\n    integer start_addr;\n\n    integer BEFP_addr;\n    integer BEFP_block;\n    integer BEFP_block2;\n\n    reg [15:0] mem_bits;\n    reg [15:0] prog_bits;\n\n    reg [15:0] DQOut_tmp;\n    reg read_out = 1'b0;\n\n    reg suspended_bp = 1'b0;\n    reg suspended_erase = 1'b0;\n\n    reg aborted ;\n    integer block_size;\n\n    reg ParameterEraseResume;\n    reg MainEraseResume;\n    reg WordProgramResume;\n    reg BP_ProgramResume;\n    time merase_duration;\n    time perase_duration;\n    time melapsed;\n    time pelapsed;\n    time mstart;\n    time pstart;\n    event merase_event;\n    event perase_event;\n\n    // timing check violation\n    reg Viol = 1'b0;\n\n    //TPD_XX_DATA\n    time           OEDQ_t;\n    time           CEDQ_t;\n    time           ADDRDQ_t;\n    time           OENeg_event;\n    time           CENeg_event;\n    time           ADDR_event;\n    reg            FROMOE;\n    reg            FROMCE;\n    reg            FROMADDR;\n    reg            OPENLATCH;\n    integer        OEDQ_01;\n    integer        CEDQ_01;\n    integer        ADDRDQIN_01;\n    integer        ADDRDQPAGE_01;\n    reg [15:0]     TempData;\n\n    wire InitialPageAccess;\n    assign InitialPageAccess = FROMADDR && ~Pmode;\n\n    wire SubsequentPageAccess;\n    assign SubsequentPageAccess = FROMADDR && Pmode;\n\n    wire CLK_rising;\n    assign CLK_rising = RCR[6] && ~CENeg_ipd;\n\n    wire CLK_falling;\n    assign CLK_falling = ~(RCR[6]) && ~CENeg_ipd;\n\n///////////////////////////////////////////////////////////////////////////////\n//Interconnect Path Delay Section\n///////////////////////////////////////////////////////////////////////////////\n    buf   (A24_ipd, A24);\n    buf   (A23_ipd, A23);\n    buf   (A22_ipd, A22);\n    buf   (A21_ipd, A21);\n    buf   (A20_ipd, A20);\n    buf   (A19_ipd, A19);\n    buf   (A18_ipd, A18);\n    buf   (A17_ipd, A17);\n    buf   (A16_ipd, A16);\n    buf   (A15_ipd, A15);\n    buf   (A14_ipd, A14);\n    buf   (A13_ipd, A13);\n    buf   (A12_ipd, A12);\n    buf   (A11_ipd, A11);\n    buf   (A10_ipd, A10);\n    buf   (A9_ipd , A9 );\n    buf   (A8_ipd , A8 );\n    buf   (A7_ipd , A7 );\n    buf   (A6_ipd , A6 );\n    buf   (A5_ipd , A5 );\n    buf   (A4_ipd , A4 );\n    buf   (A3_ipd , A3 );\n    buf   (A2_ipd , A2 );\n    buf   (A1_ipd , A1 );\n\n    buf   (DQ15_ipd, DQ15);\n    buf   (DQ14_ipd, DQ14);\n    buf   (DQ13_ipd, DQ13);\n    buf   (DQ12_ipd, DQ12);\n    buf   (DQ11_ipd, DQ11);\n    buf   (DQ10_ipd, DQ10);\n    buf   (DQ9_ipd , DQ9 );\n    buf   (DQ8_ipd , DQ8 );\n    buf   (DQ7_ipd , DQ7 );\n    buf   (DQ6_ipd , DQ6 );\n    buf   (DQ5_ipd , DQ5 );\n    buf   (DQ4_ipd , DQ4 );\n    buf   (DQ3_ipd , DQ3 );\n    buf   (DQ2_ipd , DQ2 );\n    buf   (DQ1_ipd , DQ1 );\n    buf   (DQ0_ipd , DQ0 );\n\n    buf   (RSTNeg_ipd , RSTNeg );\n    buf   (ADVNeg_ipd , ADVNeg );\n    buf   (CLK_ipd    , CLK );\n    buf   (CENeg_ipd  , CENeg );\n    buf   (OENeg_ipd  , OENeg );\n    buf   (WENeg_ipd  , WENeg );\n    buf   (WPNeg_ipd  , WPNeg );\n\n///////////////////////////////////////////////////////////////////////////////\n// Propagation  delay Section\n///////////////////////////////////////////////////////////////////////////////\n    nmos   (DQ15,   DQ15_Pass , 1);\n    nmos   (DQ14,   DQ14_Pass , 1);\n    nmos   (DQ13,   DQ13_Pass , 1);\n    nmos   (DQ12,   DQ12_Pass , 1);\n    nmos   (DQ11,   DQ11_Pass , 1);\n    nmos   (DQ10,   DQ10_Pass , 1);\n    nmos   (DQ9 ,   DQ9_Pass  , 1);\n    nmos   (DQ8 ,   DQ8_Pass  , 1);\n    nmos   (DQ7 ,   DQ7_Pass  , 1);\n    nmos   (DQ6 ,   DQ6_Pass  , 1);\n    nmos   (DQ5 ,   DQ5_Pass  , 1);\n    nmos   (DQ4 ,   DQ4_Pass  , 1);\n    nmos   (DQ3 ,   DQ3_Pass  , 1);\n    nmos   (DQ2 ,   DQ2_Pass  , 1);\n    nmos   (DQ1 ,   DQ1_Pass  , 1);\n    nmos   (DQ0 ,   DQ0_Pass  , 1);\n\n    nmos   (WAITOut, WAITOut_zd, 1);\n\n    wire deg;\n\nspecify\n    // tipd delays: interconnect path delays , mapped to input port delays.\n    // In Verilog is not necessary to declare any tipd_ delay variables,\n    // they can be taken from SDF file\n    // With all the other delays real delays would be taken from SDF file\n\n    // tpd delays\n    specparam           tpd_A1_DQ0             =1;\n    specparam           tpd_A1_DQ1             =1;\n    specparam           tpd_A1_DQ2             =1;\n    specparam           tpd_A1_DQ3             =1;\n    specparam           tpd_A1_DQ4             =1;\n    specparam           tpd_A1_DQ5             =1;\n    specparam           tpd_A1_DQ6             =1;\n    specparam           tpd_A1_DQ7             =1;\n    specparam           tpd_A1_DQ8             =1;\n    specparam           tpd_A1_DQ9             =1;\n    specparam           tpd_A1_DQ10            =1;\n    specparam           tpd_A1_DQ11            =1;\n    specparam           tpd_A1_DQ12            =1;\n    specparam           tpd_A1_DQ13            =1;\n    specparam           tpd_A1_DQ14            =1;\n    specparam           tpd_A1_DQ15            =1;\n    specparam           tpd_A2_DQ0             =1;\n    specparam           tpd_A2_DQ1             =1;\n    specparam           tpd_A2_DQ2             =1;\n    specparam           tpd_A2_DQ3             =1;\n    specparam           tpd_A2_DQ4             =1;\n    specparam           tpd_A2_DQ5             =1;\n    specparam           tpd_A2_DQ6             =1;\n    specparam           tpd_A2_DQ7             =1;\n    specparam           tpd_A2_DQ8             =1;\n    specparam           tpd_A2_DQ9             =1;\n    specparam           tpd_A2_DQ10            =1;\n    specparam           tpd_A2_DQ11            =1;\n    specparam           tpd_A2_DQ12            =1;\n    specparam           tpd_A2_DQ13            =1;\n    specparam           tpd_A2_DQ14            =1;\n    specparam           tpd_A2_DQ15            =1;\n    specparam           tpd_A3_DQ0             =1;\n    specparam           tpd_A3_DQ1             =1;\n    specparam           tpd_A3_DQ2             =1;\n    specparam           tpd_A3_DQ3             =1;\n    specparam           tpd_A3_DQ4             =1;\n    specparam           tpd_A3_DQ5             =1;\n    specparam           tpd_A3_DQ6             =1;\n    specparam           tpd_A3_DQ7             =1;\n    specparam           tpd_A3_DQ8             =1;\n    specparam           tpd_A3_DQ9             =1;\n    specparam           tpd_A3_DQ10            =1;\n    specparam           tpd_A3_DQ11            =1;\n    specparam           tpd_A3_DQ12            =1;\n    specparam           tpd_A3_DQ13            =1;\n    specparam           tpd_A3_DQ14            =1;\n    specparam           tpd_A3_DQ15            =1;\n    specparam           tpd_A4_DQ0             =1;\n    specparam           tpd_A4_DQ1             =1;\n    specparam           tpd_A4_DQ2             =1;\n    specparam           tpd_A4_DQ3             =1;\n    specparam           tpd_A4_DQ4             =1;\n    specparam           tpd_A4_DQ5             =1;\n    specparam           tpd_A4_DQ6             =1;\n    specparam           tpd_A4_DQ7             =1;\n    specparam           tpd_A4_DQ8             =1;\n    specparam           tpd_A4_DQ9             =1;\n    specparam           tpd_A4_DQ10            =1;\n    specparam           tpd_A4_DQ11            =1;\n    specparam           tpd_A4_DQ12            =1;\n    specparam           tpd_A4_DQ13            =1;\n    specparam           tpd_A4_DQ14            =1;\n    specparam           tpd_A4_DQ15            =1;\n    specparam           tpd_A5_DQ0             =1;\n    specparam           tpd_A5_DQ1             =1;\n    specparam           tpd_A5_DQ2             =1;\n    specparam           tpd_A5_DQ3             =1;\n    specparam           tpd_A5_DQ4             =1;\n    specparam           tpd_A5_DQ5             =1;\n    specparam           tpd_A5_DQ6             =1;\n    specparam           tpd_A5_DQ7             =1;\n    specparam           tpd_A5_DQ8             =1;\n    specparam           tpd_A5_DQ9             =1;\n    specparam           tpd_A5_DQ10            =1;\n    specparam           tpd_A5_DQ11            =1;\n    specparam           tpd_A5_DQ12            =1;\n    specparam           tpd_A5_DQ13            =1;\n    specparam           tpd_A5_DQ14            =1;\n    specparam           tpd_A5_DQ15            =1;\n    specparam           tpd_A6_DQ0             =1;\n    specparam           tpd_A6_DQ1             =1;\n    specparam           tpd_A6_DQ2             =1;\n    specparam           tpd_A6_DQ3             =1;\n    specparam           tpd_A6_DQ4             =1;\n    specparam           tpd_A6_DQ5             =1;\n    specparam           tpd_A6_DQ6             =1;\n    specparam           tpd_A6_DQ7             =1;\n    specparam           tpd_A6_DQ8             =1;\n    specparam           tpd_A6_DQ9             =1;\n    specparam           tpd_A6_DQ10            =1;\n    specparam           tpd_A6_DQ11            =1;\n    specparam           tpd_A6_DQ12            =1;\n    specparam           tpd_A6_DQ13            =1;\n    specparam           tpd_A6_DQ14            =1;\n    specparam           tpd_A6_DQ15            =1;\n    specparam           tpd_A7_DQ0             =1;\n    specparam           tpd_A7_DQ1             =1;\n    specparam           tpd_A7_DQ2             =1;\n    specparam           tpd_A7_DQ3             =1;\n    specparam           tpd_A7_DQ4             =1;\n    specparam           tpd_A7_DQ5             =1;\n    specparam           tpd_A7_DQ6             =1;\n    specparam           tpd_A7_DQ7             =1;\n    specparam           tpd_A7_DQ8             =1;\n    specparam           tpd_A7_DQ9             =1;\n    specparam           tpd_A7_DQ10            =1;\n    specparam           tpd_A7_DQ11            =1;\n    specparam           tpd_A7_DQ12            =1;\n    specparam           tpd_A7_DQ13            =1;\n    specparam           tpd_A7_DQ14            =1;\n    specparam           tpd_A7_DQ15            =1;\n    specparam           tpd_A8_DQ0             =1;\n    specparam           tpd_A8_DQ1             =1;\n    specparam           tpd_A8_DQ2             =1;\n    specparam           tpd_A8_DQ3             =1;\n    specparam           tpd_A8_DQ4             =1;\n    specparam           tpd_A8_DQ5             =1;\n    specparam           tpd_A8_DQ6             =1;\n    specparam           tpd_A8_DQ7             =1;\n    specparam           tpd_A8_DQ8             =1;\n    specparam           tpd_A8_DQ9             =1;\n    specparam           tpd_A8_DQ10            =1;\n    specparam           tpd_A8_DQ11            =1;\n    specparam           tpd_A8_DQ12            =1;\n    specparam           tpd_A8_DQ13            =1;\n    specparam           tpd_A8_DQ14            =1;\n    specparam           tpd_A8_DQ15            =1;\n    specparam           tpd_A9_DQ0             =1;\n    specparam           tpd_A9_DQ1             =1;\n    specparam           tpd_A9_DQ2             =1;\n    specparam           tpd_A9_DQ3             =1;\n    specparam           tpd_A9_DQ4             =1;\n    specparam           tpd_A9_DQ5             =1;\n    specparam           tpd_A9_DQ6             =1;\n    specparam           tpd_A9_DQ7             =1;\n    specparam           tpd_A9_DQ8             =1;\n    specparam           tpd_A9_DQ9             =1;\n    specparam           tpd_A9_DQ10            =1;\n    specparam           tpd_A9_DQ11            =1;\n    specparam           tpd_A9_DQ12            =1;\n    specparam           tpd_A9_DQ13            =1;\n    specparam           tpd_A9_DQ14            =1;\n    specparam           tpd_A9_DQ15            =1;\n    specparam           tpd_A10_DQ0            =1;\n    specparam           tpd_A10_DQ1            =1;\n    specparam           tpd_A10_DQ2            =1;\n    specparam           tpd_A10_DQ3            =1;\n    specparam           tpd_A10_DQ4            =1;\n    specparam           tpd_A10_DQ5            =1;\n    specparam           tpd_A10_DQ6            =1;\n    specparam           tpd_A10_DQ7            =1;\n    specparam           tpd_A10_DQ8            =1;\n    specparam           tpd_A10_DQ9            =1;\n    specparam           tpd_A10_DQ10           =1;\n    specparam           tpd_A10_DQ11           =1;\n    specparam           tpd_A10_DQ12           =1;\n    specparam           tpd_A10_DQ13           =1;\n    specparam           tpd_A10_DQ14           =1;\n    specparam           tpd_A10_DQ15           =1;\n    specparam           tpd_A11_DQ0            =1;\n    specparam           tpd_A11_DQ1            =1;\n    specparam           tpd_A11_DQ2            =1;\n    specparam           tpd_A11_DQ3            =1;\n    specparam           tpd_A11_DQ4            =1;\n    specparam           tpd_A11_DQ5            =1;\n    specparam           tpd_A11_DQ6            =1;\n    specparam           tpd_A11_DQ7            =1;\n    specparam           tpd_A11_DQ8            =1;\n    specparam           tpd_A11_DQ9            =1;\n    specparam           tpd_A11_DQ10           =1;\n    specparam           tpd_A11_DQ11           =1;\n    specparam           tpd_A11_DQ12           =1;\n    specparam           tpd_A11_DQ13           =1;\n    specparam           tpd_A11_DQ14           =1;\n    specparam           tpd_A11_DQ15           =1;\n    specparam           tpd_A12_DQ0            =1;\n    specparam           tpd_A12_DQ1            =1;\n    specparam           tpd_A12_DQ2            =1;\n    specparam           tpd_A12_DQ3            =1;\n    specparam           tpd_A12_DQ4            =1;\n    specparam           tpd_A12_DQ5            =1;\n    specparam           tpd_A12_DQ6            =1;\n    specparam           tpd_A12_DQ7            =1;\n    specparam           tpd_A12_DQ8            =1;\n    specparam           tpd_A12_DQ9            =1;\n    specparam           tpd_A12_DQ10           =1;\n    specparam           tpd_A12_DQ11           =1;\n    specparam           tpd_A12_DQ12           =1;\n    specparam           tpd_A12_DQ13           =1;\n    specparam           tpd_A12_DQ14           =1;\n    specparam           tpd_A12_DQ15           =1;\n    specparam           tpd_A13_DQ0            =1;\n    specparam           tpd_A13_DQ1            =1;\n    specparam           tpd_A13_DQ2            =1;\n    specparam           tpd_A13_DQ3            =1;\n    specparam           tpd_A13_DQ4            =1;\n    specparam           tpd_A13_DQ5            =1;\n    specparam           tpd_A13_DQ6            =1;\n    specparam           tpd_A13_DQ7            =1;\n    specparam           tpd_A13_DQ8            =1;\n    specparam           tpd_A13_DQ9            =1;\n    specparam           tpd_A13_DQ10           =1;\n    specparam           tpd_A13_DQ11           =1;\n    specparam           tpd_A13_DQ12           =1;\n    specparam           tpd_A13_DQ13           =1;\n    specparam           tpd_A13_DQ14           =1;\n    specparam           tpd_A13_DQ15           =1;\n    specparam           tpd_A14_DQ0            =1;\n    specparam           tpd_A14_DQ1            =1;\n    specparam           tpd_A14_DQ2            =1;\n    specparam           tpd_A14_DQ3            =1;\n    specparam           tpd_A14_DQ4            =1;\n    specparam           tpd_A14_DQ5            =1;\n    specparam           tpd_A14_DQ6            =1;\n    specparam           tpd_A14_DQ7            =1;\n    specparam           tpd_A14_DQ8            =1;\n    specparam           tpd_A14_DQ9            =1;\n    specparam           tpd_A14_DQ10           =1;\n    specparam           tpd_A14_DQ11           =1;\n    specparam           tpd_A14_DQ12           =1;\n    specparam           tpd_A14_DQ13           =1;\n    specparam           tpd_A14_DQ14           =1;\n    specparam           tpd_A14_DQ15           =1;\n    specparam           tpd_A15_DQ0            =1;\n    specparam           tpd_A15_DQ1            =1;\n    specparam           tpd_A15_DQ2            =1;\n    specparam           tpd_A15_DQ3            =1;\n    specparam           tpd_A15_DQ4            =1;\n    specparam           tpd_A15_DQ5            =1;\n    specparam           tpd_A15_DQ6            =1;\n    specparam           tpd_A15_DQ7            =1;\n    specparam           tpd_A15_DQ8            =1;\n    specparam           tpd_A15_DQ9            =1;\n    specparam           tpd_A15_DQ10           =1;\n    specparam           tpd_A15_DQ11           =1;\n    specparam           tpd_A15_DQ12           =1;\n    specparam           tpd_A15_DQ13           =1;\n    specparam           tpd_A15_DQ14           =1;\n    specparam           tpd_A15_DQ15           =1;\n    specparam           tpd_A16_DQ0            =1;\n    specparam           tpd_A16_DQ1            =1;\n    specparam           tpd_A16_DQ2            =1;\n    specparam           tpd_A16_DQ3            =1;\n    specparam           tpd_A16_DQ4            =1;\n    specparam           tpd_A16_DQ5            =1;\n    specparam           tpd_A16_DQ6            =1;\n    specparam           tpd_A16_DQ7            =1;\n    specparam           tpd_A16_DQ8            =1;\n    specparam           tpd_A16_DQ9            =1;\n    specparam           tpd_A16_DQ10           =1;\n    specparam           tpd_A16_DQ11           =1;\n    specparam           tpd_A16_DQ12           =1;\n    specparam           tpd_A16_DQ13           =1;\n    specparam           tpd_A16_DQ14           =1;\n    specparam           tpd_A16_DQ15           =1;\n    specparam           tpd_A17_DQ0            =1;\n    specparam           tpd_A17_DQ1            =1;\n    specparam           tpd_A17_DQ2            =1;\n    specparam           tpd_A17_DQ3            =1;\n    specparam           tpd_A17_DQ4            =1;\n    specparam           tpd_A17_DQ5            =1;\n    specparam           tpd_A17_DQ6            =1;\n    specparam           tpd_A17_DQ7            =1;\n    specparam           tpd_A17_DQ8            =1;\n    specparam           tpd_A17_DQ9            =1;\n    specparam           tpd_A17_DQ10           =1;\n    specparam           tpd_A17_DQ11           =1;\n    specparam           tpd_A17_DQ12           =1;\n    specparam           tpd_A17_DQ13           =1;\n    specparam           tpd_A17_DQ14           =1;\n    specparam           tpd_A17_DQ15           =1;\n    specparam           tpd_A18_DQ0            =1;\n    specparam           tpd_A18_DQ1            =1;\n    specparam           tpd_A18_DQ2            =1;\n    specparam           tpd_A18_DQ3            =1;\n    specparam           tpd_A18_DQ4            =1;\n    specparam           tpd_A18_DQ5            =1;\n    specparam           tpd_A18_DQ6            =1;\n    specparam           tpd_A18_DQ7            =1;\n    specparam           tpd_A18_DQ8            =1;\n    specparam           tpd_A18_DQ9            =1;\n    specparam           tpd_A18_DQ10           =1;\n    specparam           tpd_A18_DQ11           =1;\n    specparam           tpd_A18_DQ12           =1;\n    specparam           tpd_A18_DQ13           =1;\n    specparam           tpd_A18_DQ14           =1;\n    specparam           tpd_A18_DQ15           =1;\n    specparam           tpd_A19_DQ0            =1;\n    specparam           tpd_A19_DQ1            =1;\n    specparam           tpd_A19_DQ2            =1;\n    specparam           tpd_A19_DQ3            =1;\n    specparam           tpd_A19_DQ4            =1;\n    specparam           tpd_A19_DQ5            =1;\n    specparam           tpd_A19_DQ6            =1;\n    specparam           tpd_A19_DQ7            =1;\n    specparam           tpd_A19_DQ8            =1;\n    specparam           tpd_A19_DQ9            =1;\n    specparam           tpd_A19_DQ10           =1;\n    specparam           tpd_A19_DQ11           =1;\n    specparam           tpd_A19_DQ12           =1;\n    specparam           tpd_A19_DQ13           =1;\n    specparam           tpd_A19_DQ14           =1;\n    specparam           tpd_A19_DQ15           =1;\n    specparam           tpd_A20_DQ0            =1;\n    specparam           tpd_A20_DQ1            =1;\n    specparam           tpd_A20_DQ2            =1;\n    specparam           tpd_A20_DQ3            =1;\n    specparam           tpd_A20_DQ4            =1;\n    specparam           tpd_A20_DQ5            =1;\n    specparam           tpd_A20_DQ6            =1;\n    specparam           tpd_A20_DQ7            =1;\n    specparam           tpd_A20_DQ8            =1;\n    specparam           tpd_A20_DQ9            =1;\n    specparam           tpd_A20_DQ10           =1;\n    specparam           tpd_A20_DQ11           =1;\n    specparam           tpd_A20_DQ12           =1;\n    specparam           tpd_A20_DQ13           =1;\n    specparam           tpd_A20_DQ14           =1;\n    specparam           tpd_A20_DQ15           =1;\n    specparam           tpd_A21_DQ0            =1;\n    specparam           tpd_A21_DQ1            =1;\n    specparam           tpd_A21_DQ2            =1;\n    specparam           tpd_A21_DQ3            =1;\n    specparam           tpd_A21_DQ4            =1;\n    specparam           tpd_A21_DQ5            =1;\n    specparam           tpd_A21_DQ6            =1;\n    specparam           tpd_A21_DQ7            =1;\n    specparam           tpd_A21_DQ8            =1;\n    specparam           tpd_A21_DQ9            =1;\n    specparam           tpd_A21_DQ10           =1;\n    specparam           tpd_A21_DQ11           =1;\n    specparam           tpd_A21_DQ12           =1;\n    specparam           tpd_A21_DQ13           =1;\n    specparam           tpd_A21_DQ14           =1;\n    specparam           tpd_A21_DQ15           =1;\n    specparam           tpd_A22_DQ0            =1;\n    specparam           tpd_A22_DQ1            =1;\n    specparam           tpd_A22_DQ2            =1;\n    specparam           tpd_A22_DQ3            =1;\n    specparam           tpd_A22_DQ4            =1;\n    specparam           tpd_A22_DQ5            =1;\n    specparam           tpd_A22_DQ6            =1;\n    specparam           tpd_A22_DQ7            =1;\n    specparam           tpd_A22_DQ8            =1;\n    specparam           tpd_A22_DQ9            =1;\n    specparam           tpd_A22_DQ10           =1;\n    specparam           tpd_A22_DQ11           =1;\n    specparam           tpd_A22_DQ12           =1;\n    specparam           tpd_A22_DQ13           =1;\n    specparam           tpd_A22_DQ14           =1;\n    specparam           tpd_A22_DQ15           =1;\n    specparam           tpd_A23_DQ0            =1;\n    specparam           tpd_A23_DQ1            =1;\n    specparam           tpd_A23_DQ2            =1;\n    specparam           tpd_A23_DQ3            =1;\n    specparam           tpd_A23_DQ4            =1;\n    specparam           tpd_A23_DQ5            =1;\n    specparam           tpd_A23_DQ6            =1;\n    specparam           tpd_A23_DQ7            =1;\n    specparam           tpd_A23_DQ8            =1;\n    specparam           tpd_A23_DQ9            =1;\n    specparam           tpd_A23_DQ10           =1;\n    specparam           tpd_A23_DQ11           =1;\n    specparam           tpd_A23_DQ12           =1;\n    specparam           tpd_A23_DQ13           =1;\n    specparam           tpd_A23_DQ14           =1;\n    specparam           tpd_A23_DQ15           =1;\n    specparam           tpd_A24_DQ0            =1;\n    specparam           tpd_A24_DQ1            =1;\n    specparam           tpd_A24_DQ2            =1;\n    specparam           tpd_A24_DQ3            =1;\n    specparam           tpd_A24_DQ4            =1;\n    specparam           tpd_A24_DQ5            =1;\n    specparam           tpd_A24_DQ6            =1;\n    specparam           tpd_A24_DQ7            =1;\n    specparam           tpd_A24_DQ8            =1;\n    specparam           tpd_A24_DQ9            =1;\n    specparam           tpd_A24_DQ10           =1;\n    specparam           tpd_A24_DQ11           =1;\n    specparam           tpd_A24_DQ12           =1;\n    specparam           tpd_A24_DQ13           =1;\n    specparam           tpd_A24_DQ14           =1;\n    specparam           tpd_A24_DQ15           =1;\n\n    specparam           tpd_CENeg_DQ0           =1;\n    specparam           tpd_CENeg_DQ1           =1;\n    specparam           tpd_CENeg_DQ2           =1;\n    specparam           tpd_CENeg_DQ3           =1;\n    specparam           tpd_CENeg_DQ4           =1;\n    specparam           tpd_CENeg_DQ5           =1;\n    specparam           tpd_CENeg_DQ6           =1;\n    specparam           tpd_CENeg_DQ7           =1;\n    specparam           tpd_CENeg_DQ8           =1;\n    specparam           tpd_CENeg_DQ9           =1;\n    specparam           tpd_CENeg_DQ10          =1;\n    specparam           tpd_CENeg_DQ11          =1;\n    specparam           tpd_CENeg_DQ12          =1;\n    specparam           tpd_CENeg_DQ13          =1;\n    specparam           tpd_CENeg_DQ14          =1;\n    specparam           tpd_CENeg_DQ15          =1;\n\n    specparam           tpd_OENeg_DQ0           =1;\n    specparam           tpd_OENeg_DQ1           =1;\n    specparam           tpd_OENeg_DQ2           =1;\n    specparam           tpd_OENeg_DQ3           =1;\n    specparam           tpd_OENeg_DQ4           =1;\n    specparam           tpd_OENeg_DQ5           =1;\n    specparam           tpd_OENeg_DQ6           =1;\n    specparam           tpd_OENeg_DQ7           =1;\n    specparam           tpd_OENeg_DQ8           =1;\n    specparam           tpd_OENeg_DQ9           =1;\n    specparam           tpd_OENeg_DQ10          =1;\n    specparam           tpd_OENeg_DQ11          =1;\n    specparam           tpd_OENeg_DQ12          =1;\n    specparam           tpd_OENeg_DQ13          =1;\n    specparam           tpd_OENeg_DQ14          =1;\n    specparam           tpd_OENeg_DQ15          =1;\n\n    specparam           tpd_CLK_DQ0              =1;\n    specparam           tpd_CLK_DQ1              =1;\n    specparam           tpd_CLK_DQ2              =1;\n    specparam           tpd_CLK_DQ3              =1;\n    specparam           tpd_CLK_DQ4              =1;\n    specparam           tpd_CLK_DQ5              =1;\n    specparam           tpd_CLK_DQ6              =1;\n    specparam           tpd_CLK_DQ7              =1;\n    specparam           tpd_CLK_DQ8              =1;\n    specparam           tpd_CLK_DQ9              =1;\n    specparam           tpd_CLK_DQ10             =1;\n    specparam           tpd_CLK_DQ11             =1;\n    specparam           tpd_CLK_DQ12             =1;\n    specparam           tpd_CLK_DQ13             =1;\n    specparam           tpd_CLK_DQ14             =1;\n    specparam           tpd_CLK_DQ15             =1;\n\n    specparam           tpd_CE0Neg_WAITOut       =1;\n    specparam           tpd_OE0Neg_WAITOut       =1;\n    specparam           tpd_CLK_WAITOut          =1;\n\n    //tsetup values\n    specparam           tsetup_A1_ADVNeg               =1;\n    specparam           tsetup_A2_ADVNeg               =1;\n    specparam           tsetup_A3_ADVNeg               =1;\n    specparam           tsetup_A4_ADVNeg               =1;\n    specparam           tsetup_A5_ADVNeg               =1;\n    specparam           tsetup_A6_ADVNeg               =1;\n    specparam           tsetup_A7_ADVNeg               =1;\n    specparam           tsetup_A8_ADVNeg               =1;\n    specparam           tsetup_A9_ADVNeg               =1;\n    specparam           tsetup_A10_ADVNeg              =1;\n    specparam           tsetup_A11_ADVNeg              =1;\n    specparam           tsetup_A12_ADVNeg              =1;\n    specparam           tsetup_A13_ADVNeg              =1;\n    specparam           tsetup_A14_ADVNeg              =1;\n    specparam           tsetup_A15_ADVNeg              =1;\n    specparam           tsetup_A16_ADVNeg              =1;\n    specparam           tsetup_A17_ADVNeg              =1;\n    specparam           tsetup_A18_ADVNeg              =1;\n    specparam           tsetup_A19_ADVNeg              =1;\n    specparam           tsetup_A20_ADVNeg              =1;\n    specparam           tsetup_A21_ADVNeg              =1;\n    specparam           tsetup_A22_ADVNeg              =1;\n    specparam           tsetup_A23_ADVNeg              =1;\n    specparam           tsetup_A24_ADVNeg              =1;\n\n    specparam           tsetup_CENeg_ADVNeg            =1;\n    specparam           tsetup_RSTNeg_ADVNeg           =1;\n    specparam           tsetup_CLK_ADVNeg              =1;\n    specparam           tsetup_WENeg_ADVNeg            =1;\n\n    specparam           tsetup_A1_CLK                  =1;\n    specparam           tsetup_A2_CLK                  =1;\n    specparam           tsetup_A3_CLK                  =1;\n    specparam           tsetup_A4_CLK                  =1;\n    specparam           tsetup_A5_CLK                  =1;\n    specparam           tsetup_A6_CLK                  =1;\n    specparam           tsetup_A7_CLK                  =1;\n    specparam           tsetup_A8_CLK                  =1;\n    specparam           tsetup_A9_CLK                  =1;\n    specparam           tsetup_A10_CLK                 =1;\n    specparam           tsetup_A11_CLK                 =1;\n    specparam           tsetup_A12_CLK                 =1;\n    specparam           tsetup_A13_CLK                 =1;\n    specparam           tsetup_A14_CLK                 =1;\n    specparam           tsetup_A15_CLK                 =1;\n    specparam           tsetup_A16_CLK                 =1;\n    specparam           tsetup_A17_CLK                 =1;\n    specparam           tsetup_A18_CLK                 =1;\n    specparam           tsetup_A19_CLK                 =1;\n    specparam           tsetup_A20_CLK                 =1;\n    specparam           tsetup_A21_CLK                 =1;\n    specparam           tsetup_A22_CLK                 =1;\n    specparam           tsetup_A23_CLK                 =1;\n    specparam           tsetup_A24_CLK                 =1;\n\n    specparam           tsetup_ADVNeg_CLK              =1;\n    specparam           tsetup_CENeg_CLK               =1;\n    specparam           tsetup_WENeg_CLK               =1;\n\n    specparam           tsetup_CENeg_WENeg             =1;\n\n    specparam           tsetup_DQ0_WENeg               =1;\n    specparam           tsetup_DQ1_WENeg               =1;\n    specparam           tsetup_DQ2_WENeg               =1;\n    specparam           tsetup_DQ3_WENeg               =1;\n    specparam           tsetup_DQ4_WENeg               =1;\n    specparam           tsetup_DQ5_WENeg               =1;\n    specparam           tsetup_DQ6_WENeg               =1;\n    specparam           tsetup_DQ7_WENeg               =1;\n    specparam           tsetup_DQ8_WENeg               =1;\n    specparam           tsetup_DQ9_WENeg               =1;\n    specparam           tsetup_DQ10_WENeg              =1;\n    specparam           tsetup_DQ11_WENeg              =1;\n    specparam           tsetup_DQ12_WENeg              =1;\n    specparam           tsetup_DQ13_WENeg              =1;\n    specparam           tsetup_DQ14_WENeg              =1;\n    specparam           tsetup_DQ15_WENeg              =1;\n\n    specparam           tsetup_A1_WENeg                =1;\n    specparam           tsetup_A2_WENeg                =1;\n    specparam           tsetup_A3_WENeg                =1;\n    specparam           tsetup_A4_WENeg                =1;\n    specparam           tsetup_A5_WENeg                =1;\n    specparam           tsetup_A6_WENeg                =1;\n    specparam           tsetup_A7_WENeg                =1;\n    specparam           tsetup_A8_WENeg                =1;\n    specparam           tsetup_A9_WENeg                =1;\n    specparam           tsetup_A10_WENeg               =1;\n    specparam           tsetup_A11_WENeg               =1;\n    specparam           tsetup_A12_WENeg               =1;\n    specparam           tsetup_A13_WENeg               =1;\n    specparam           tsetup_A14_WENeg               =1;\n    specparam           tsetup_A15_WENeg               =1;\n    specparam           tsetup_A16_WENeg               =1;\n    specparam           tsetup_A17_WENeg               =1;\n    specparam           tsetup_A18_WENeg               =1;\n    specparam           tsetup_A19_WENeg               =1;\n    specparam           tsetup_A20_WENeg               =1;\n    specparam           tsetup_A21_WENeg               =1;\n    specparam           tsetup_A22_WENeg               =1;\n    specparam           tsetup_A23_WENeg               =1;\n    specparam           tsetup_A24_WENeg               =1;\n\n    specparam           tsetup_WPNeg_WENeg             =1;\n    specparam           tsetup_ADVNeg_WENeg            =1;\n    specparam           tsetup_CLK_WENeg               =1;\n\n    specparam           tsetup_WENeg_OENeg             =1;\n\n    // thold values: hold times\n    specparam           thold_A1_ADVNeg                =1;\n    specparam           thold_A2_ADVNeg                =1;\n    specparam           thold_A3_ADVNeg                =1;\n    specparam           thold_A4_ADVNeg                =1;\n    specparam           thold_A5_ADVNeg                =1;\n    specparam           thold_A6_ADVNeg                =1;\n    specparam           thold_A7_ADVNeg                =1;\n    specparam           thold_A8_ADVNeg                =1;\n    specparam           thold_A9_ADVNeg                =1;\n    specparam           thold_A10_ADVNeg               =1;\n    specparam           thold_A11_ADVNeg               =1;\n    specparam           thold_A12_ADVNeg               =1;\n    specparam           thold_A13_ADVNeg               =1;\n    specparam           thold_A14_ADVNeg               =1;\n    specparam           thold_A15_ADVNeg               =1;\n    specparam           thold_A16_ADVNeg               =1;\n    specparam           thold_A17_ADVNeg               =1;\n    specparam           thold_A18_ADVNeg               =1;\n    specparam           thold_A19_ADVNeg               =1;\n    specparam           thold_A20_ADVNeg               =1;\n    specparam           thold_A21_ADVNeg               =1;\n    specparam           thold_A22_ADVNeg               =1;\n    specparam           thold_A23_ADVNeg               =1;\n    specparam           thold_A24_ADVNeg               =1;\n\n    specparam           thold_A1_CLK                   =1;\n    specparam           thold_A2_CLK                   =1;\n    specparam           thold_A3_CLK                   =1;\n    specparam           thold_A4_CLK                   =1;\n    specparam           thold_A5_CLK                   =1;\n    specparam           thold_A6_CLK                   =1;\n    specparam           thold_A7_CLK                   =1;\n    specparam           thold_A8_CLK                   =1;\n    specparam           thold_A9_CLK                   =1;\n    specparam           thold_A10_CLK                  =1;\n    specparam           thold_A11_CLK                  =1;\n    specparam           thold_A12_CLK                  =1;\n    specparam           thold_A13_CLK                  =1;\n    specparam           thold_A14_CLK                  =1;\n    specparam           thold_A15_CLK                  =1;\n    specparam           thold_A16_CLK                  =1;\n    specparam           thold_A17_CLK                  =1;\n    specparam           thold_A18_CLK                  =1;\n    specparam           thold_A19_CLK                  =1;\n    specparam           thold_A20_CLK                  =1;\n    specparam           thold_A21_CLK                  =1;\n    specparam           thold_A22_CLK                  =1;\n    specparam           thold_A23_CLK                  =1;\n    specparam           thold_A24_CLK                  =1;\n\n    specparam           thold_CENeg_WENeg              =1;\n\n    specparam           thold_DQ0_WENeg                =1;\n    specparam           thold_DQ1_WENeg                =1;\n    specparam           thold_DQ2_WENeg                =1;\n    specparam           thold_DQ3_WENeg                =1;\n    specparam           thold_DQ4_WENeg                =1;\n    specparam           thold_DQ5_WENeg                =1;\n    specparam           thold_DQ6_WENeg                =1;\n    specparam           thold_DQ7_WENeg                =1;\n    specparam           thold_DQ8_WENeg                =1;\n    specparam           thold_DQ9_WENeg                =1;\n    specparam           thold_DQ10_WENeg               =1;\n    specparam           thold_DQ11_WENeg               =1;\n    specparam           thold_DQ12_WENeg               =1;\n    specparam           thold_DQ13_WENeg               =1;\n    specparam           thold_DQ14_WENeg               =1;\n    specparam           thold_DQ15_WENeg               =1;\n\n    specparam           thold_A1_WENeg                 =1;\n    specparam           thold_A2_WENeg                 =1;\n    specparam           thold_A3_WENeg                 =1;\n    specparam           thold_A4_WENeg                 =1;\n    specparam           thold_A5_WENeg                 =1;\n    specparam           thold_A6_WENeg                 =1;\n    specparam           thold_A7_WENeg                 =1;\n    specparam           thold_A8_WENeg                 =1;\n    specparam           thold_A9_WENeg                 =1;\n    specparam           thold_A10_WENeg                =1;\n    specparam           thold_A11_WENeg                =1;\n    specparam           thold_A12_WENeg                =1;\n    specparam           thold_A13_WENeg                =1;\n    specparam           thold_A14_WENeg                =1;\n    specparam           thold_A15_WENeg                =1;\n    specparam           thold_A16_WENeg                =1;\n    specparam           thold_A17_WENeg                =1;\n    specparam           thold_A18_WENeg                =1;\n    specparam           thold_A19_WENeg                =1;\n    specparam           thold_A20_WENeg                =1;\n    specparam           thold_A21_WENeg                =1;\n    specparam           thold_A22_WENeg                =1;\n    specparam           thold_A23_WENeg                =1;\n    specparam           thold_A24_WENeg                =1;\n\n    //tpw values\n    specparam       tpw_CENeg_posedge    = 1;\n\n    specparam       tpw_ADVNeg_posedge   = 1;\n    specparam       tpw_ADVNeg_negedge   = 1;\n\n    specparam       tpw_WENeg_negedge    = 1;\n    specparam       tpw_WENeg_posedge    = 1;\n\n    specparam       tpw_RSTNeg_negedge   = 1;\n\n    specparam       tpw_CLK_posedge      = 1;\n    specparam       tpw_CLK_negedge      = 1;\n    specparam       tperiod_CLK          = 1;\n\n    // tdevice values: values for internal delays\n    `ifdef SPEEDSIM\n        // Program BUffProgram\n        specparam   tdevice_BuffProgram             = 88000;\n        // Program BUffProgram\n        specparam   tdevice_BuffProgram9V           = 68000;\n        // Program BEFP\n        specparam   tdevice_BEFP                    = 32000;\n        // Program EraseParameter\n        specparam   tdevice_EraseParameter_td       = 2500;\n        // Program EraseMain\n        specparam   tdevice_EraseMain_td            = 4000;\n    `else\n        // Program BUffProgram\n        specparam   tdevice_BuffProgram             = 880000;\n        // Program BUffProgram\n        specparam   tdevice_BuffProgram9V           = 680000;\n        // Program BEFP\n        specparam   tdevice_BEFP                    = 320000;\n        // Program EraseParameter\n        specparam   tdevice_EraseParameter_td       = 2500000;\n        // Program EraseMain\n        specparam   tdevice_EraseMain_td            = 4000000;\n    `endif // SPEEDSIM\n\n    // Program Word\n    specparam   tdevice_WordProgram             = 200000;\n    // Program Word\n    specparam   tdevice_WordProgram9V           = 190000;\n    // Program BEFPsetup\n    specparam   tdevice_BEFPsetup               = 5000;\n    // Program ProgramSuspend\n    specparam   tdevice_ProgramSuspend          = 25000;\n    // Program ProgramSuspend\n    specparam   tdevice_EraseSuspend            = 25000;\n    // Reset during Program or Erase\n    specparam   tdevice_RstDuringErsPrg         = 25000;\n\n///////////////////////////////////////////////////////////////////////////////\n// Input Port  Delays  don't require Verilog description\n///////////////////////////////////////////////////////////////////////////////\n// Path delays                                                               //\n///////////////////////////////////////////////////////////////////////////////\n    if (InitialPageAccess) (A1 *> DQ0)  = tpd_A1_DQ0;\n    if (InitialPageAccess) (A1 *> DQ1)  = tpd_A1_DQ1;\n    if (InitialPageAccess) (A1 *> DQ2)  = tpd_A1_DQ2;\n    if (InitialPageAccess) (A1 *> DQ3)  = tpd_A1_DQ3;\n    if (InitialPageAccess) (A1 *> DQ4)  = tpd_A1_DQ4;\n    if (InitialPageAccess) (A1 *> DQ5)  = tpd_A1_DQ5;\n    if (InitialPageAccess) (A1 *> DQ6)  = tpd_A1_DQ6;\n    if (InitialPageAccess) (A1 *> DQ7)  = tpd_A1_DQ7;\n    if (InitialPageAccess) (A1 *> DQ8)  = tpd_A1_DQ8;\n    if (InitialPageAccess) (A1 *> DQ9)  = tpd_A1_DQ9;\n    if (InitialPageAccess) (A1 *> DQ10) = tpd_A1_DQ10;\n    if (InitialPageAccess) (A1 *> DQ11) = tpd_A1_DQ11;\n    if (InitialPageAccess) (A1 *> DQ12) = tpd_A1_DQ12;\n    if (InitialPageAccess) (A1 *> DQ13) = tpd_A1_DQ13;\n    if (InitialPageAccess) (A1 *> DQ14) = tpd_A1_DQ14;\n    if (InitialPageAccess) (A1 *> DQ15) = tpd_A1_DQ15;\n    if (InitialPageAccess) (A2 *> DQ0)  = tpd_A2_DQ0;\n    if (InitialPageAccess) (A2 *> DQ1)  = tpd_A2_DQ1;\n    if (InitialPageAccess) (A2 *> DQ2)  = tpd_A2_DQ2;\n    if (InitialPageAccess) (A2 *> DQ3)  = tpd_A2_DQ3;\n    if (InitialPageAccess) (A2 *> DQ4)  = tpd_A2_DQ4;\n    if (InitialPageAccess) (A2 *> DQ5)  = tpd_A2_DQ5;\n    if (InitialPageAccess) (A2 *> DQ6)  = tpd_A2_DQ6;\n    if (InitialPageAccess) (A2 *> DQ7)  = tpd_A2_DQ7;\n    if (InitialPageAccess) (A2 *> DQ8)  = tpd_A2_DQ8;\n    if (InitialPageAccess) (A2 *> DQ9)  = tpd_A2_DQ9;\n    if (InitialPageAccess) (A2 *> DQ10) = tpd_A2_DQ10;\n    if (InitialPageAccess) (A2 *> DQ11) = tpd_A2_DQ11;\n    if (InitialPageAccess) (A2 *> DQ12) = tpd_A2_DQ12;\n    if (InitialPageAccess) (A2 *> DQ13) = tpd_A2_DQ13;\n    if (InitialPageAccess) (A2 *> DQ14) = tpd_A2_DQ14;\n    if (InitialPageAccess) (A2 *> DQ15) = tpd_A2_DQ15;\n    if (InitialPageAccess) (A3 *> DQ0)  = tpd_A3_DQ0;\n    if (InitialPageAccess) (A3 *> DQ1)  = tpd_A3_DQ1;\n    if (InitialPageAccess) (A3 *> DQ2)  = tpd_A3_DQ2;\n    if (InitialPageAccess) (A3 *> DQ3)  = tpd_A3_DQ3;\n    if (InitialPageAccess) (A3 *> DQ4)  = tpd_A3_DQ4;\n    if (InitialPageAccess) (A3 *> DQ5)  = tpd_A3_DQ5;\n    if (InitialPageAccess) (A3 *> DQ6)  = tpd_A3_DQ6;\n    if (InitialPageAccess) (A3 *> DQ7)  = tpd_A3_DQ7;\n    if (InitialPageAccess) (A3 *> DQ8)  = tpd_A3_DQ8;\n    if (InitialPageAccess) (A3 *> DQ9)  = tpd_A3_DQ9;\n    if (InitialPageAccess) (A3 *> DQ10) = tpd_A3_DQ10;\n    if (InitialPageAccess) (A3 *> DQ11) = tpd_A3_DQ11;\n    if (InitialPageAccess) (A3 *> DQ12) = tpd_A3_DQ12;\n    if (InitialPageAccess) (A3 *> DQ13) = tpd_A3_DQ13;\n    if (InitialPageAccess) (A3 *> DQ14) = tpd_A3_DQ14;\n    if (InitialPageAccess) (A3 *> DQ15) = tpd_A3_DQ15;\n    if (InitialPageAccess) (A4 *> DQ0)  = tpd_A4_DQ0;\n    if (InitialPageAccess) (A4 *> DQ1)  = tpd_A4_DQ1;\n    if (InitialPageAccess) (A4 *> DQ2)  = tpd_A4_DQ2;\n    if (InitialPageAccess) (A4 *> DQ3)  = tpd_A4_DQ3;\n    if (InitialPageAccess) (A4 *> DQ4)  = tpd_A4_DQ4;\n    if (InitialPageAccess) (A4 *> DQ5)  = tpd_A4_DQ5;\n    if (InitialPageAccess) (A4 *> DQ6)  = tpd_A4_DQ6;\n    if (InitialPageAccess) (A4 *> DQ7)  = tpd_A4_DQ7;\n    if (InitialPageAccess) (A4 *> DQ8)  = tpd_A4_DQ8;\n    if (InitialPageAccess) (A4 *> DQ9)  = tpd_A4_DQ9;\n    if (InitialPageAccess) (A4 *> DQ10) = tpd_A4_DQ10;\n    if (InitialPageAccess) (A4 *> DQ11) = tpd_A4_DQ11;\n    if (InitialPageAccess) (A4 *> DQ12) = tpd_A4_DQ12;\n    if (InitialPageAccess) (A4 *> DQ13) = tpd_A4_DQ13;\n    if (InitialPageAccess) (A4 *> DQ14) = tpd_A4_DQ14;\n    if (InitialPageAccess) (A4 *> DQ15) = tpd_A4_DQ15;\n    if (InitialPageAccess) (A5 *> DQ0)  = tpd_A5_DQ0;\n    if (InitialPageAccess) (A5 *> DQ1)  = tpd_A5_DQ1;\n    if (InitialPageAccess) (A5 *> DQ2)  = tpd_A5_DQ2;\n    if (InitialPageAccess) (A5 *> DQ3)  = tpd_A5_DQ3;\n    if (InitialPageAccess) (A5 *> DQ4)  = tpd_A5_DQ4;\n    if (InitialPageAccess) (A5 *> DQ5)  = tpd_A5_DQ5;\n    if (InitialPageAccess) (A5 *> DQ6)  = tpd_A5_DQ6;\n    if (InitialPageAccess) (A5 *> DQ7)  = tpd_A5_DQ7;\n    if (InitialPageAccess) (A5 *> DQ8)  = tpd_A5_DQ8;\n    if (InitialPageAccess) (A5 *> DQ9)  = tpd_A5_DQ9;\n    if (InitialPageAccess) (A5 *> DQ10) = tpd_A5_DQ10;\n    if (InitialPageAccess) (A5 *> DQ11) = tpd_A5_DQ11;\n    if (InitialPageAccess) (A5 *> DQ12) = tpd_A5_DQ12;\n    if (InitialPageAccess) (A5 *> DQ13) = tpd_A5_DQ13;\n    if (InitialPageAccess) (A5 *> DQ14) = tpd_A5_DQ14;\n    if (InitialPageAccess) (A5 *> DQ15) = tpd_A5_DQ15;\n    if (InitialPageAccess) (A6 *> DQ0)  = tpd_A6_DQ0;\n    if (InitialPageAccess) (A6 *> DQ1)  = tpd_A6_DQ1;\n    if (InitialPageAccess) (A6 *> DQ2)  = tpd_A6_DQ2;\n    if (InitialPageAccess) (A6 *> DQ3)  = tpd_A6_DQ3;\n    if (InitialPageAccess) (A6 *> DQ4)  = tpd_A6_DQ4;\n    if (InitialPageAccess) (A6 *> DQ5)  = tpd_A6_DQ5;\n    if (InitialPageAccess) (A6 *> DQ6)  = tpd_A6_DQ6;\n    if (InitialPageAccess) (A6 *> DQ7)  = tpd_A6_DQ7;\n    if (InitialPageAccess) (A6 *> DQ8)  = tpd_A6_DQ8;\n    if (InitialPageAccess) (A6 *> DQ9)  = tpd_A6_DQ9;\n    if (InitialPageAccess) (A6 *> DQ10) = tpd_A6_DQ10;\n    if (InitialPageAccess) (A6 *> DQ11) = tpd_A6_DQ11;\n    if (InitialPageAccess) (A6 *> DQ12) = tpd_A6_DQ12;\n    if (InitialPageAccess) (A6 *> DQ13) = tpd_A6_DQ13;\n    if (InitialPageAccess) (A6 *> DQ14) = tpd_A6_DQ14;\n    if (InitialPageAccess) (A6 *> DQ15) = tpd_A6_DQ15;\n    if (InitialPageAccess) (A7 *> DQ0)  = tpd_A7_DQ0;\n    if (InitialPageAccess) (A7 *> DQ1)  = tpd_A7_DQ1;\n    if (InitialPageAccess) (A7 *> DQ2)  = tpd_A7_DQ2;\n    if (InitialPageAccess) (A7 *> DQ3)  = tpd_A7_DQ3;\n    if (InitialPageAccess) (A7 *> DQ4)  = tpd_A7_DQ4;\n    if (InitialPageAccess) (A7 *> DQ5)  = tpd_A7_DQ5;\n    if (InitialPageAccess) (A7 *> DQ6)  = tpd_A7_DQ6;\n    if (InitialPageAccess) (A7 *> DQ7)  = tpd_A7_DQ7;\n    if (InitialPageAccess) (A7 *> DQ8)  = tpd_A7_DQ8;\n    if (InitialPageAccess) (A7 *> DQ9)  = tpd_A7_DQ9;\n    if (InitialPageAccess) (A7 *> DQ10) = tpd_A7_DQ10;\n    if (InitialPageAccess) (A7 *> DQ11) = tpd_A7_DQ11;\n    if (InitialPageAccess) (A7 *> DQ12) = tpd_A7_DQ12;\n    if (InitialPageAccess) (A7 *> DQ13) = tpd_A7_DQ13;\n    if (InitialPageAccess) (A7 *> DQ14) = tpd_A7_DQ14;\n    if (InitialPageAccess) (A7 *> DQ15) = tpd_A7_DQ15;\n    if (InitialPageAccess) (A8 *> DQ0)  = tpd_A8_DQ0;\n    if (InitialPageAccess) (A8 *> DQ1)  = tpd_A8_DQ1;\n    if (InitialPageAccess) (A8 *> DQ2)  = tpd_A8_DQ2;\n    if (InitialPageAccess) (A8 *> DQ3)  = tpd_A8_DQ3;\n    if (InitialPageAccess) (A8 *> DQ4)  = tpd_A8_DQ4;\n    if (InitialPageAccess) (A8 *> DQ5)  = tpd_A8_DQ5;\n    if (InitialPageAccess) (A8 *> DQ6)  = tpd_A8_DQ6;\n    if (InitialPageAccess) (A8 *> DQ7)  = tpd_A8_DQ7;\n    if (InitialPageAccess) (A8 *> DQ8)  = tpd_A8_DQ8;\n    if (InitialPageAccess) (A8 *> DQ9)  = tpd_A8_DQ9;\n    if (InitialPageAccess) (A8 *> DQ10) = tpd_A8_DQ10;\n    if (InitialPageAccess) (A8 *> DQ11) = tpd_A8_DQ11;\n    if (InitialPageAccess) (A8 *> DQ12) = tpd_A8_DQ12;\n    if (InitialPageAccess) (A8 *> DQ13) = tpd_A8_DQ13;\n    if (InitialPageAccess) (A8 *> DQ14) = tpd_A8_DQ14;\n    if (InitialPageAccess) (A8 *> DQ15) = tpd_A8_DQ15;\n    if (InitialPageAccess) (A9 *> DQ0)  = tpd_A9_DQ0;\n    if (InitialPageAccess) (A9 *> DQ1)  = tpd_A9_DQ1;\n    if (InitialPageAccess) (A9 *> DQ2)  = tpd_A9_DQ2;\n    if (InitialPageAccess) (A9 *> DQ3)  = tpd_A9_DQ3;\n    if (InitialPageAccess) (A9 *> DQ4)  = tpd_A9_DQ4;\n    if (InitialPageAccess) (A9 *> DQ5)  = tpd_A9_DQ5;\n    if (InitialPageAccess) (A9 *> DQ6)  = tpd_A9_DQ6;\n    if (InitialPageAccess) (A9 *> DQ7)  = tpd_A9_DQ7;\n    if (InitialPageAccess) (A9 *> DQ8)  = tpd_A9_DQ8;\n    if (InitialPageAccess) (A9 *> DQ9)  = tpd_A9_DQ9;\n    if (InitialPageAccess) (A9 *> DQ10) = tpd_A9_DQ10;\n    if (InitialPageAccess) (A9 *> DQ11) = tpd_A9_DQ11;\n    if (InitialPageAccess) (A9 *> DQ12) = tpd_A9_DQ12;\n    if (InitialPageAccess) (A9 *> DQ13) = tpd_A9_DQ13;\n    if (InitialPageAccess) (A9 *> DQ14) = tpd_A9_DQ14;\n    if (InitialPageAccess) (A9 *> DQ15) = tpd_A9_DQ15;\n    if (InitialPageAccess) (A10 *> DQ0) = tpd_A10_DQ0;\n    if (InitialPageAccess) (A10 *> DQ1) = tpd_A10_DQ1;\n    if (InitialPageAccess) (A10 *> DQ2) = tpd_A10_DQ2;\n    if (InitialPageAccess) (A10 *> DQ3) = tpd_A10_DQ3;\n    if (InitialPageAccess) (A10 *> DQ4) = tpd_A10_DQ4;\n    if (InitialPageAccess) (A10 *> DQ5) = tpd_A10_DQ5;\n    if (InitialPageAccess) (A10 *> DQ6) = tpd_A10_DQ6;\n    if (InitialPageAccess) (A10 *> DQ7) = tpd_A10_DQ7;\n    if (InitialPageAccess) (A10 *> DQ8) = tpd_A10_DQ8;\n    if (InitialPageAccess) (A10 *> DQ9) = tpd_A10_DQ9;\n    if (InitialPageAccess) (A10 *> DQ10) = tpd_A10_DQ10;\n    if (InitialPageAccess) (A10 *> DQ11) = tpd_A10_DQ11;\n    if (InitialPageAccess) (A10 *> DQ12) = tpd_A10_DQ12;\n    if (InitialPageAccess) (A10 *> DQ13) = tpd_A10_DQ13;\n    if (InitialPageAccess) (A10 *> DQ14) = tpd_A10_DQ14;\n    if (InitialPageAccess) (A10 *> DQ15) = tpd_A10_DQ15;\n    if (InitialPageAccess) (A11 *> DQ0)  = tpd_A11_DQ0;\n    if (InitialPageAccess) (A11 *> DQ1)  = tpd_A11_DQ1;\n    if (InitialPageAccess) (A11 *> DQ2)  = tpd_A11_DQ2;\n    if (InitialPageAccess) (A11 *> DQ3)  = tpd_A11_DQ3;\n    if (InitialPageAccess) (A11 *> DQ4)  = tpd_A11_DQ4;\n    if (InitialPageAccess) (A11 *> DQ5)  = tpd_A11_DQ5;\n    if (InitialPageAccess) (A11 *> DQ6)  = tpd_A11_DQ6;\n    if (InitialPageAccess) (A11 *> DQ7)  = tpd_A11_DQ7;\n    if (InitialPageAccess) (A11 *> DQ8)  = tpd_A11_DQ8;\n    if (InitialPageAccess) (A11 *> DQ9)  = tpd_A11_DQ9;\n    if (InitialPageAccess) (A11 *> DQ10) = tpd_A11_DQ10;\n    if (InitialPageAccess) (A11 *> DQ11) = tpd_A11_DQ11;\n    if (InitialPageAccess) (A11 *> DQ12) = tpd_A11_DQ12;\n    if (InitialPageAccess) (A11 *> DQ13) = tpd_A11_DQ13;\n    if (InitialPageAccess) (A11 *> DQ14) = tpd_A11_DQ14;\n    if (InitialPageAccess) (A11 *> DQ15) = tpd_A11_DQ15;\n    if (InitialPageAccess) (A12 *> DQ0)  = tpd_A12_DQ0;\n    if (InitialPageAccess) (A12 *> DQ1)  = tpd_A12_DQ1;\n    if (InitialPageAccess) (A12 *> DQ2)  = tpd_A12_DQ2;\n    if (InitialPageAccess) (A12 *> DQ3)  = tpd_A12_DQ3;\n    if (InitialPageAccess) (A12 *> DQ4)  = tpd_A12_DQ4;\n    if (InitialPageAccess) (A12 *> DQ5)  = tpd_A12_DQ5;\n    if (InitialPageAccess) (A12 *> DQ6)  = tpd_A12_DQ6;\n    if (InitialPageAccess) (A12 *> DQ7)  = tpd_A12_DQ7;\n    if (InitialPageAccess) (A12 *> DQ8)  = tpd_A12_DQ8;\n    if (InitialPageAccess) (A12 *> DQ9)  = tpd_A12_DQ9;\n    if (InitialPageAccess) (A12 *> DQ10) = tpd_A12_DQ10;\n    if (InitialPageAccess) (A12 *> DQ11) = tpd_A12_DQ11;\n    if (InitialPageAccess) (A12 *> DQ12) = tpd_A12_DQ12;\n    if (InitialPageAccess) (A12 *> DQ13) = tpd_A12_DQ13;\n    if (InitialPageAccess) (A12 *> DQ14) = tpd_A12_DQ14;\n    if (InitialPageAccess) (A12 *> DQ15) = tpd_A12_DQ15;\n    if (InitialPageAccess) (A13 *> DQ0)  = tpd_A13_DQ0;\n    if (InitialPageAccess) (A13 *> DQ1)  = tpd_A13_DQ1;\n    if (InitialPageAccess) (A13 *> DQ2)  = tpd_A13_DQ2;\n    if (InitialPageAccess) (A13 *> DQ3)  = tpd_A13_DQ3;\n    if (InitialPageAccess) (A13 *> DQ4)  = tpd_A13_DQ4;\n    if (InitialPageAccess) (A13 *> DQ5)  = tpd_A13_DQ5;\n    if (InitialPageAccess) (A13 *> DQ6)  = tpd_A13_DQ6;\n    if (InitialPageAccess) (A13 *> DQ7)  = tpd_A13_DQ7;\n    if (InitialPageAccess) (A13 *> DQ8)  = tpd_A13_DQ8;\n    if (InitialPageAccess) (A13 *> DQ9)  = tpd_A13_DQ9;\n    if (InitialPageAccess) (A13 *> DQ10) = tpd_A13_DQ10;\n    if (InitialPageAccess) (A13 *> DQ11) = tpd_A13_DQ11;\n    if (InitialPageAccess) (A13 *> DQ12) = tpd_A13_DQ12;\n    if (InitialPageAccess) (A13 *> DQ13) = tpd_A13_DQ13;\n    if (InitialPageAccess) (A13 *> DQ14) = tpd_A13_DQ14;\n    if (InitialPageAccess) (A13 *> DQ15) = tpd_A13_DQ15;\n    if (InitialPageAccess) (A14 *> DQ0)  = tpd_A14_DQ0;\n    if (InitialPageAccess) (A14 *> DQ1)  = tpd_A14_DQ1;\n    if (InitialPageAccess) (A14 *> DQ2)  = tpd_A14_DQ2;\n    if (InitialPageAccess) (A14 *> DQ3)  = tpd_A14_DQ3;\n    if (InitialPageAccess) (A14 *> DQ4)  = tpd_A14_DQ4;\n    if (InitialPageAccess) (A14 *> DQ5)  = tpd_A14_DQ5;\n    if (InitialPageAccess) (A14 *> DQ6)  = tpd_A14_DQ6;\n    if (InitialPageAccess) (A14 *> DQ7)  = tpd_A14_DQ7;\n    if (InitialPageAccess) (A14 *> DQ8)  = tpd_A14_DQ8;\n    if (InitialPageAccess) (A14 *> DQ9)  = tpd_A14_DQ9;\n    if (InitialPageAccess) (A14 *> DQ10) = tpd_A14_DQ10;\n    if (InitialPageAccess) (A14 *> DQ11) = tpd_A14_DQ11;\n    if (InitialPageAccess) (A14 *> DQ12) = tpd_A14_DQ12;\n    if (InitialPageAccess) (A14 *> DQ13) = tpd_A14_DQ13;\n    if (InitialPageAccess) (A14 *> DQ14) = tpd_A14_DQ14;\n    if (InitialPageAccess) (A14 *> DQ15) = tpd_A14_DQ15;\n    if (InitialPageAccess) (A15 *> DQ0)  = tpd_A15_DQ0;\n    if (InitialPageAccess) (A15 *> DQ1)  = tpd_A15_DQ1;\n    if (InitialPageAccess) (A15 *> DQ2)  = tpd_A15_DQ2;\n    if (InitialPageAccess) (A15 *> DQ3)  = tpd_A15_DQ3;\n    if (InitialPageAccess) (A15 *> DQ4)  = tpd_A15_DQ4;\n    if (InitialPageAccess) (A15 *> DQ5)  = tpd_A15_DQ5;\n    if (InitialPageAccess) (A15 *> DQ6)  = tpd_A15_DQ6;\n    if (InitialPageAccess) (A15 *> DQ7)  = tpd_A15_DQ7;\n    if (InitialPageAccess) (A15 *> DQ8)  = tpd_A15_DQ8;\n    if (InitialPageAccess) (A15 *> DQ9)  = tpd_A15_DQ9;\n    if (InitialPageAccess) (A15 *> DQ10) = tpd_A15_DQ10;\n    if (InitialPageAccess) (A15 *> DQ11) = tpd_A15_DQ11;\n    if (InitialPageAccess) (A15 *> DQ12) = tpd_A15_DQ12;\n    if (InitialPageAccess) (A15 *> DQ13) = tpd_A15_DQ13;\n    if (InitialPageAccess) (A15 *> DQ14) = tpd_A15_DQ14;\n    if (InitialPageAccess) (A15 *> DQ15) = tpd_A15_DQ15;\n    if (InitialPageAccess) (A16 *> DQ0)  = tpd_A16_DQ0;\n    if (InitialPageAccess) (A16 *> DQ1)  = tpd_A16_DQ1;\n    if (InitialPageAccess) (A16 *> DQ2)  = tpd_A16_DQ2;\n    if (InitialPageAccess) (A16 *> DQ3)  = tpd_A16_DQ3;\n    if (InitialPageAccess) (A16 *> DQ4)  = tpd_A16_DQ4;\n    if (InitialPageAccess) (A16 *> DQ5)  = tpd_A16_DQ5;\n    if (InitialPageAccess) (A16 *> DQ6)  = tpd_A16_DQ6;\n    if (InitialPageAccess) (A16 *> DQ7)  = tpd_A16_DQ7;\n    if (InitialPageAccess) (A16 *> DQ8)  = tpd_A16_DQ8;\n    if (InitialPageAccess) (A16 *> DQ9)  = tpd_A16_DQ9;\n    if (InitialPageAccess) (A16 *> DQ10) = tpd_A16_DQ10;\n    if (InitialPageAccess) (A16 *> DQ11) = tpd_A16_DQ11;\n    if (InitialPageAccess) (A16 *> DQ12) = tpd_A16_DQ12;\n    if (InitialPageAccess) (A16 *> DQ13) = tpd_A16_DQ13;\n    if (InitialPageAccess) (A16 *> DQ14) = tpd_A16_DQ14;\n    if (InitialPageAccess) (A16 *> DQ15) = tpd_A16_DQ15;\n    if (InitialPageAccess) (A17 *> DQ0)  = tpd_A17_DQ0;\n    if (InitialPageAccess) (A17 *> DQ1)  = tpd_A17_DQ1;\n    if (InitialPageAccess) (A17 *> DQ2)  = tpd_A17_DQ2;\n    if (InitialPageAccess) (A17 *> DQ3)  = tpd_A17_DQ3;\n    if (InitialPageAccess) (A17 *> DQ4)  = tpd_A17_DQ4;\n    if (InitialPageAccess) (A17 *> DQ5)  = tpd_A17_DQ5;\n    if (InitialPageAccess) (A17 *> DQ6)  = tpd_A17_DQ6;\n    if (InitialPageAccess) (A17 *> DQ7)  = tpd_A17_DQ7;\n    if (InitialPageAccess) (A17 *> DQ8)  = tpd_A17_DQ8;\n    if (InitialPageAccess) (A17 *> DQ9)  = tpd_A17_DQ9;\n    if (InitialPageAccess) (A17 *> DQ10) = tpd_A17_DQ10;\n    if (InitialPageAccess) (A17 *> DQ11) = tpd_A17_DQ11;\n    if (InitialPageAccess) (A17 *> DQ12) = tpd_A17_DQ12;\n    if (InitialPageAccess) (A17 *> DQ13) = tpd_A17_DQ13;\n    if (InitialPageAccess) (A17 *> DQ14) = tpd_A17_DQ14;\n    if (InitialPageAccess) (A17 *> DQ15) = tpd_A17_DQ15;\n    if (InitialPageAccess) (A18 *> DQ0)  = tpd_A18_DQ0;\n    if (InitialPageAccess) (A18 *> DQ1)  = tpd_A18_DQ1;\n    if (InitialPageAccess) (A18 *> DQ2)  = tpd_A18_DQ2;\n    if (InitialPageAccess) (A18 *> DQ3)  = tpd_A18_DQ3;\n    if (InitialPageAccess) (A18 *> DQ4)  = tpd_A18_DQ4;\n    if (InitialPageAccess) (A18 *> DQ5)  = tpd_A18_DQ5;\n    if (InitialPageAccess) (A18 *> DQ6)  = tpd_A18_DQ6;\n    if (InitialPageAccess) (A18 *> DQ7)  = tpd_A18_DQ7;\n    if (InitialPageAccess) (A18 *> DQ8)  = tpd_A18_DQ8;\n    if (InitialPageAccess) (A18 *> DQ9)  = tpd_A18_DQ9;\n    if (InitialPageAccess) (A18 *> DQ10) = tpd_A18_DQ10;\n    if (InitialPageAccess) (A18 *> DQ11) = tpd_A18_DQ11;\n    if (InitialPageAccess) (A18 *> DQ12) = tpd_A18_DQ12;\n    if (InitialPageAccess) (A18 *> DQ13) = tpd_A18_DQ13;\n    if (InitialPageAccess) (A18 *> DQ14) = tpd_A18_DQ14;\n    if (InitialPageAccess) (A18 *> DQ15) = tpd_A18_DQ15;\n    if (InitialPageAccess) (A19 *> DQ0)  = tpd_A19_DQ0;\n    if (InitialPageAccess) (A19 *> DQ1)  = tpd_A19_DQ1;\n    if (InitialPageAccess) (A19 *> DQ2)  = tpd_A19_DQ2;\n    if (InitialPageAccess) (A19 *> DQ3)  = tpd_A19_DQ3;\n    if (InitialPageAccess) (A19 *> DQ4)  = tpd_A19_DQ4;\n    if (InitialPageAccess) (A19 *> DQ5)  = tpd_A19_DQ5;\n    if (InitialPageAccess) (A19 *> DQ6)  = tpd_A19_DQ6;\n    if (InitialPageAccess) (A19 *> DQ7)  = tpd_A19_DQ7;\n    if (InitialPageAccess) (A19 *> DQ8)  = tpd_A19_DQ8;\n    if (InitialPageAccess) (A19 *> DQ9)  = tpd_A19_DQ9;\n    if (InitialPageAccess) (A19 *> DQ10) = tpd_A19_DQ10;\n    if (InitialPageAccess) (A19 *> DQ11) = tpd_A19_DQ11;\n    if (InitialPageAccess) (A19 *> DQ12) = tpd_A19_DQ12;\n    if (InitialPageAccess) (A19 *> DQ13) = tpd_A19_DQ13;\n    if (InitialPageAccess) (A19 *> DQ14) = tpd_A19_DQ14;\n    if (InitialPageAccess) (A19 *> DQ15) = tpd_A19_DQ15;\n    if (InitialPageAccess) (A20 *> DQ0)  = tpd_A20_DQ0;\n    if (InitialPageAccess) (A20 *> DQ1)  = tpd_A20_DQ1;\n    if (InitialPageAccess) (A20 *> DQ2)  = tpd_A20_DQ2;\n    if (InitialPageAccess) (A20 *> DQ3)  = tpd_A20_DQ3;\n    if (InitialPageAccess) (A20 *> DQ4)  = tpd_A20_DQ4;\n    if (InitialPageAccess) (A20 *> DQ5)  = tpd_A20_DQ5;\n    if (InitialPageAccess) (A20 *> DQ6)  = tpd_A20_DQ6;\n    if (InitialPageAccess) (A20 *> DQ7)  = tpd_A20_DQ7;\n    if (InitialPageAccess) (A20 *> DQ8)  = tpd_A20_DQ8;\n    if (InitialPageAccess) (A20 *> DQ9)  = tpd_A20_DQ9;\n    if (InitialPageAccess) (A20 *> DQ10) = tpd_A20_DQ10;\n    if (InitialPageAccess) (A20 *> DQ11) = tpd_A20_DQ11;\n    if (InitialPageAccess) (A20 *> DQ12) = tpd_A20_DQ12;\n    if (InitialPageAccess) (A20 *> DQ13) = tpd_A20_DQ13;\n    if (InitialPageAccess) (A20 *> DQ14) = tpd_A20_DQ14;\n    if (InitialPageAccess) (A20 *> DQ15) = tpd_A20_DQ15;\n    if (InitialPageAccess) (A21 *> DQ0)  = tpd_A21_DQ0;\n    if (InitialPageAccess) (A21 *> DQ1)  = tpd_A21_DQ1;\n    if (InitialPageAccess) (A21 *> DQ2)  = tpd_A21_DQ2;\n    if (InitialPageAccess) (A21 *> DQ3)  = tpd_A21_DQ3;\n    if (InitialPageAccess) (A21 *> DQ4)  = tpd_A21_DQ4;\n    if (InitialPageAccess) (A21 *> DQ5)  = tpd_A21_DQ5;\n    if (InitialPageAccess) (A21 *> DQ6)  = tpd_A21_DQ6;\n    if (InitialPageAccess) (A21 *> DQ7)  = tpd_A21_DQ7;\n    if (InitialPageAccess) (A21 *> DQ8)  = tpd_A21_DQ8;\n    if (InitialPageAccess) (A21 *> DQ9)  = tpd_A21_DQ9;\n    if (InitialPageAccess) (A21 *> DQ10) = tpd_A21_DQ10;\n    if (InitialPageAccess) (A21 *> DQ11) = tpd_A21_DQ11;\n    if (InitialPageAccess) (A21 *> DQ12) = tpd_A21_DQ12;\n    if (InitialPageAccess) (A21 *> DQ13) = tpd_A21_DQ13;\n    if (InitialPageAccess) (A21 *> DQ14) = tpd_A21_DQ14;\n    if (InitialPageAccess) (A21 *> DQ15) = tpd_A21_DQ15;\n    if (InitialPageAccess) (A22 *> DQ0)  = tpd_A22_DQ0;\n    if (InitialPageAccess) (A22 *> DQ1)  = tpd_A22_DQ1;\n    if (InitialPageAccess) (A22 *> DQ2)  = tpd_A22_DQ2;\n    if (InitialPageAccess) (A22 *> DQ3)  = tpd_A22_DQ3;\n    if (InitialPageAccess) (A22 *> DQ4)  = tpd_A22_DQ4;\n    if (InitialPageAccess) (A22 *> DQ5)  = tpd_A22_DQ5;\n    if (InitialPageAccess) (A22 *> DQ6)  = tpd_A22_DQ6;\n    if (InitialPageAccess) (A22 *> DQ7)  = tpd_A22_DQ7;\n    if (InitialPageAccess) (A22 *> DQ8)  = tpd_A22_DQ8;\n    if (InitialPageAccess) (A22 *> DQ9)  = tpd_A22_DQ9;\n    if (InitialPageAccess) (A22 *> DQ10) = tpd_A22_DQ10;\n    if (InitialPageAccess) (A22 *> DQ11) = tpd_A22_DQ11;\n    if (InitialPageAccess) (A22 *> DQ12) = tpd_A22_DQ12;\n    if (InitialPageAccess) (A22 *> DQ13) = tpd_A22_DQ13;\n    if (InitialPageAccess) (A22 *> DQ14) = tpd_A22_DQ14;\n    if (InitialPageAccess) (A22 *> DQ15) = tpd_A22_DQ15;\n    if (InitialPageAccess) (A23 *> DQ0)  = tpd_A23_DQ0;\n    if (InitialPageAccess) (A23 *> DQ1)  = tpd_A23_DQ1;\n    if (InitialPageAccess) (A23 *> DQ2)  = tpd_A23_DQ2;\n    if (InitialPageAccess) (A23 *> DQ3)  = tpd_A23_DQ3;\n    if (InitialPageAccess) (A23 *> DQ4)  = tpd_A23_DQ4;\n    if (InitialPageAccess) (A23 *> DQ5)  = tpd_A23_DQ5;\n    if (InitialPageAccess) (A23 *> DQ6)  = tpd_A23_DQ6;\n    if (InitialPageAccess) (A23 *> DQ7)  = tpd_A23_DQ7;\n    if (InitialPageAccess) (A23 *> DQ8)  = tpd_A23_DQ8;\n    if (InitialPageAccess) (A23 *> DQ9)  = tpd_A23_DQ9;\n    if (InitialPageAccess) (A23 *> DQ10) = tpd_A23_DQ10;\n    if (InitialPageAccess) (A23 *> DQ11) = tpd_A23_DQ11;\n    if (InitialPageAccess) (A23 *> DQ12) = tpd_A23_DQ12;\n    if (InitialPageAccess) (A23 *> DQ13) = tpd_A23_DQ13;\n    if (InitialPageAccess) (A23 *> DQ14) = tpd_A23_DQ14;\n    if (InitialPageAccess) (A23 *> DQ15) = tpd_A23_DQ15;\n    if (InitialPageAccess) (A24 *> DQ0)  = tpd_A24_DQ0;\n    if (InitialPageAccess) (A24 *> DQ1)  = tpd_A24_DQ1;\n    if (InitialPageAccess) (A24 *> DQ2)  = tpd_A24_DQ2;\n    if (InitialPageAccess) (A24 *> DQ3)  = tpd_A24_DQ3;\n    if (InitialPageAccess) (A24 *> DQ4)  = tpd_A24_DQ4;\n    if (InitialPageAccess) (A24 *> DQ5)  = tpd_A24_DQ5;\n    if (InitialPageAccess) (A24 *> DQ6)  = tpd_A24_DQ6;\n    if (InitialPageAccess) (A24 *> DQ7)  = tpd_A24_DQ7;\n    if (InitialPageAccess) (A24 *> DQ8)  = tpd_A24_DQ8;\n    if (InitialPageAccess) (A24 *> DQ9)  = tpd_A24_DQ9;\n    if (InitialPageAccess) (A24 *> DQ10) = tpd_A24_DQ10;\n    if (InitialPageAccess) (A24 *> DQ11) = tpd_A24_DQ11;\n    if (InitialPageAccess) (A24 *> DQ12) = tpd_A24_DQ12;\n    if (InitialPageAccess) (A24 *> DQ13) = tpd_A24_DQ13;\n    if (InitialPageAccess) (A24 *> DQ14) = tpd_A24_DQ14;\n    if (InitialPageAccess) (A24 *> DQ15) = tpd_A24_DQ15;\n\n    if (SubsequentPageAccess) (A1 *> DQ0)  = tpd_A1_DQ0;\n    if (SubsequentPageAccess) (A1 *> DQ1)  = tpd_A1_DQ1;\n    if (SubsequentPageAccess) (A1 *> DQ2)  = tpd_A1_DQ2;\n    if (SubsequentPageAccess) (A1 *> DQ3)  = tpd_A1_DQ3;\n    if (SubsequentPageAccess) (A1 *> DQ4)  = tpd_A1_DQ4;\n    if (SubsequentPageAccess) (A1 *> DQ5)  = tpd_A1_DQ5;\n    if (SubsequentPageAccess) (A1 *> DQ6)  = tpd_A1_DQ6;\n    if (SubsequentPageAccess) (A1 *> DQ7)  = tpd_A1_DQ7;\n    if (SubsequentPageAccess) (A1 *> DQ8)  = tpd_A1_DQ8;\n    if (SubsequentPageAccess) (A1 *> DQ9)  = tpd_A1_DQ9;\n    if (SubsequentPageAccess) (A1 *> DQ10) = tpd_A1_DQ10;\n    if (SubsequentPageAccess) (A1 *> DQ11) = tpd_A1_DQ11;\n    if (SubsequentPageAccess) (A1 *> DQ12) = tpd_A1_DQ12;\n    if (SubsequentPageAccess) (A1 *> DQ13) = tpd_A1_DQ13;\n    if (SubsequentPageAccess) (A1 *> DQ14) = tpd_A1_DQ14;\n    if (SubsequentPageAccess) (A1 *> DQ15) = tpd_A1_DQ15;\n    if (SubsequentPageAccess) (A2 *> DQ0)  = tpd_A2_DQ0;\n    if (SubsequentPageAccess) (A2 *> DQ1)  = tpd_A2_DQ1;\n    if (SubsequentPageAccess) (A2 *> DQ2)  = tpd_A2_DQ2;\n    if (SubsequentPageAccess) (A2 *> DQ3)  = tpd_A2_DQ3;\n    if (SubsequentPageAccess) (A2 *> DQ4)  = tpd_A2_DQ4;\n    if (SubsequentPageAccess) (A2 *> DQ5)  = tpd_A2_DQ5;\n    if (SubsequentPageAccess) (A2 *> DQ6)  = tpd_A2_DQ6;\n    if (SubsequentPageAccess) (A2 *> DQ7)  = tpd_A2_DQ7;\n    if (SubsequentPageAccess) (A2 *> DQ8)  = tpd_A2_DQ8;\n    if (SubsequentPageAccess) (A2 *> DQ9)  = tpd_A2_DQ9;\n    if (SubsequentPageAccess) (A2 *> DQ10) = tpd_A2_DQ10;\n    if (SubsequentPageAccess) (A2 *> DQ11) = tpd_A2_DQ11;\n    if (SubsequentPageAccess) (A2 *> DQ12) = tpd_A2_DQ12;\n    if (SubsequentPageAccess) (A2 *> DQ13) = tpd_A2_DQ13;\n    if (SubsequentPageAccess) (A2 *> DQ14) = tpd_A2_DQ14;\n    if (SubsequentPageAccess) (A2 *> DQ15) = tpd_A2_DQ15;\n\n    if (FROMCE) (CENeg *> DQ0) = tpd_CENeg_DQ0;\n    if (FROMCE) (CENeg *> DQ1) = tpd_CENeg_DQ1;\n    if (FROMCE) (CENeg *> DQ2) = tpd_CENeg_DQ2;\n    if (FROMCE) (CENeg *> DQ3) = tpd_CENeg_DQ3;\n    if (FROMCE) (CENeg *> DQ4) = tpd_CENeg_DQ4;\n    if (FROMCE) (CENeg *> DQ5) = tpd_CENeg_DQ5;\n    if (FROMCE) (CENeg *> DQ6) = tpd_CENeg_DQ6;\n    if (FROMCE) (CENeg *> DQ7) = tpd_CENeg_DQ7;\n    if (FROMCE) (CENeg *> DQ8) = tpd_CENeg_DQ8;\n    if (FROMCE) (CENeg *> DQ9) = tpd_CENeg_DQ9;\n    if (FROMCE) (CENeg *> DQ10)= tpd_CENeg_DQ10;\n    if (FROMCE) (CENeg *> DQ11)= tpd_CENeg_DQ11;\n    if (FROMCE) (CENeg *> DQ12)= tpd_CENeg_DQ12;\n    if (FROMCE) (CENeg *> DQ13)= tpd_CENeg_DQ13;\n    if (FROMCE) (CENeg *> DQ14)= tpd_CENeg_DQ14;\n    if (FROMCE) (CENeg *> DQ15)= tpd_CENeg_DQ15;\n\n    if (FROMOE) (OENeg *> DQ0)  = tpd_OENeg_DQ0;\n    if (FROMOE) (OENeg *> DQ1)  = tpd_OENeg_DQ1;\n    if (FROMOE) (OENeg *> DQ2)  = tpd_OENeg_DQ2;\n    if (FROMOE) (OENeg *> DQ3)  = tpd_OENeg_DQ3;\n    if (FROMOE) (OENeg *> DQ4)  = tpd_OENeg_DQ4;\n    if (FROMOE) (OENeg *> DQ5)  = tpd_OENeg_DQ5;\n    if (FROMOE) (OENeg *> DQ6)  = tpd_OENeg_DQ6;\n    if (FROMOE) (OENeg *> DQ7)  = tpd_OENeg_DQ7;\n    if (FROMOE) (OENeg *> DQ8)  = tpd_OENeg_DQ8;\n    if (FROMOE) (OENeg *> DQ9)  = tpd_OENeg_DQ9;\n    if (FROMOE) (OENeg *> DQ10) = tpd_OENeg_DQ10;\n    if (FROMOE) (OENeg *> DQ11) = tpd_OENeg_DQ11;\n    if (FROMOE) (OENeg *> DQ12) = tpd_OENeg_DQ12;\n    if (FROMOE) (OENeg *> DQ13) = tpd_OENeg_DQ13;\n    if (FROMOE) (OENeg *> DQ14) = tpd_OENeg_DQ14;\n    if (FROMOE) (OENeg *> DQ15) = tpd_OENeg_DQ15;\n\n    if (RCR[15] === 1'b0) ( CLK *> DQ0 )   =  tpd_CLK_DQ0   ;\n    if (RCR[15] === 1'b0) ( CLK *> DQ1 )   =  tpd_CLK_DQ1   ;\n    if (RCR[15] === 1'b0) ( CLK *> DQ2 )   =  tpd_CLK_DQ2   ;\n    if (RCR[15] === 1'b0) ( CLK *> DQ3 )   =  tpd_CLK_DQ3   ;\n    if (RCR[15] === 1'b0) ( CLK *> DQ4 )   =  tpd_CLK_DQ4   ;\n    if (RCR[15] === 1'b0) ( CLK *> DQ5 )   =  tpd_CLK_DQ5   ;\n    if (RCR[15] === 1'b0) ( CLK *> DQ6 )   =  tpd_CLK_DQ6   ;\n    if (RCR[15] === 1'b0) ( CLK *> DQ7 )   =  tpd_CLK_DQ7   ;\n    if (RCR[15] === 1'b0) ( CLK *> DQ8 )   =  tpd_CLK_DQ8   ;\n    if (RCR[15] === 1'b0) ( CLK *> DQ9 )   =  tpd_CLK_DQ9   ;\n    if (RCR[15] === 1'b0) ( CLK *> DQ10)   =  tpd_CLK_DQ10  ;\n    if (RCR[15] === 1'b0) ( CLK *> DQ11)   =  tpd_CLK_DQ11  ;\n    if (RCR[15] === 1'b0) ( CLK *> DQ12)   =  tpd_CLK_DQ12  ;\n    if (RCR[15] === 1'b0) ( CLK *> DQ13)   =  tpd_CLK_DQ13  ;\n    if (RCR[15] === 1'b0) ( CLK *> DQ14)   =  tpd_CLK_DQ14  ;\n    if (RCR[15] === 1'b0) ( CLK *> DQ15)   =  tpd_CLK_DQ15  ;\n\n    ( CENeg *> WAITOut)         =  tpd_CE0Neg_WAITOut ;\n    ( OENeg *> WAITOut)         =  tpd_OE0Neg_WAITOut ;\n    if (RCR[15] === 1'b0) ( CLK *> WAITOut) = tpd_CLK_WAITOut;\n\n///////////////////////////////////////////////////////////////////////////////\n// Timing Violation                                                          //\n///////////////////////////////////////////////////////////////////////////////\n    $setup ( A1   , posedge ADVNeg, tsetup_A1_ADVNeg, Viol);\n    $setup ( A2   , posedge ADVNeg, tsetup_A2_ADVNeg, Viol);\n    $setup ( A3   , posedge ADVNeg, tsetup_A3_ADVNeg, Viol);\n    $setup ( A4   , posedge ADVNeg, tsetup_A4_ADVNeg, Viol);\n    $setup ( A5   , posedge ADVNeg, tsetup_A5_ADVNeg, Viol);\n    $setup ( A6   , posedge ADVNeg, tsetup_A6_ADVNeg, Viol);\n    $setup ( A7   , posedge ADVNeg, tsetup_A7_ADVNeg, Viol);\n    $setup ( A8   , posedge ADVNeg, tsetup_A8_ADVNeg, Viol);\n    $setup ( A9   , posedge ADVNeg, tsetup_A9_ADVNeg, Viol);\n    $setup ( A10  , posedge ADVNeg, tsetup_A10_ADVNeg, Viol);\n    $setup ( A11  , posedge ADVNeg, tsetup_A11_ADVNeg, Viol);\n    $setup ( A12  , posedge ADVNeg, tsetup_A12_ADVNeg, Viol);\n    $setup ( A13  , posedge ADVNeg, tsetup_A13_ADVNeg, Viol);\n    $setup ( A14  , posedge ADVNeg, tsetup_A14_ADVNeg, Viol);\n    $setup ( A15  , posedge ADVNeg, tsetup_A15_ADVNeg, Viol);\n    $setup ( A16  , posedge ADVNeg, tsetup_A16_ADVNeg, Viol);\n    $setup ( A17  , posedge ADVNeg, tsetup_A17_ADVNeg, Viol);\n    $setup ( A18  , posedge ADVNeg, tsetup_A18_ADVNeg, Viol);\n    $setup ( A19  , posedge ADVNeg, tsetup_A19_ADVNeg, Viol);\n    $setup ( A20  , posedge ADVNeg, tsetup_A20_ADVNeg, Viol);\n    $setup ( A21  , posedge ADVNeg, tsetup_A21_ADVNeg, Viol);\n    $setup ( A22  , posedge ADVNeg, tsetup_A22_ADVNeg, Viol);\n    $setup ( A23  , posedge ADVNeg, tsetup_A23_ADVNeg, Viol);\n    $setup ( A24  , posedge ADVNeg, tsetup_A24_ADVNeg, Viol);\n\n    $setup ( negedge CENeg  , posedge ADVNeg, tsetup_CENeg_ADVNeg, Viol);\n    $setup ( negedge RSTNeg , posedge ADVNeg, tsetup_RSTNeg_ADVNeg,Viol);\n    $setup ( posedge WENeg  , posedge ADVNeg, tsetup_WENeg_ADVNeg, Viol);\n\n    $setup ( A1   , posedge CLK &&& CLK_rising, tsetup_A1_CLK, Viol);\n    $setup ( A2   , posedge CLK &&& CLK_rising, tsetup_A2_CLK, Viol);\n    $setup ( A3   , posedge CLK &&& CLK_rising, tsetup_A3_CLK, Viol);\n    $setup ( A4   , posedge CLK &&& CLK_rising, tsetup_A4_CLK, Viol);\n    $setup ( A5   , posedge CLK &&& CLK_rising, tsetup_A5_CLK, Viol);\n    $setup ( A6   , posedge CLK &&& CLK_rising, tsetup_A6_CLK, Viol);\n    $setup ( A7   , posedge CLK &&& CLK_rising, tsetup_A7_CLK, Viol);\n    $setup ( A8   , posedge CLK &&& CLK_rising, tsetup_A8_CLK, Viol);\n    $setup ( A9   , posedge CLK &&& CLK_rising, tsetup_A9_CLK, Viol);\n    $setup ( A10  , posedge CLK &&& CLK_rising, tsetup_A10_CLK, Viol);\n    $setup ( A11  , posedge CLK &&& CLK_rising, tsetup_A11_CLK, Viol);\n    $setup ( A12  , posedge CLK &&& CLK_rising, tsetup_A12_CLK, Viol);\n    $setup ( A13  , posedge CLK &&& CLK_rising, tsetup_A13_CLK, Viol);\n    $setup ( A14  , posedge CLK &&& CLK_rising, tsetup_A14_CLK, Viol);\n    $setup ( A15  , posedge CLK &&& CLK_rising, tsetup_A15_CLK, Viol);\n    $setup ( A16  , posedge CLK &&& CLK_rising, tsetup_A16_CLK, Viol);\n    $setup ( A17  , posedge CLK &&& CLK_rising, tsetup_A17_CLK, Viol);\n    $setup ( A18  , posedge CLK &&& CLK_rising, tsetup_A18_CLK, Viol);\n    $setup ( A19  , posedge CLK &&& CLK_rising, tsetup_A19_CLK, Viol);\n    $setup ( A20  , posedge CLK &&& CLK_rising, tsetup_A20_CLK, Viol);\n    $setup ( A21  , posedge CLK &&& CLK_rising, tsetup_A21_CLK, Viol);\n    $setup ( A22  , posedge CLK &&& CLK_rising, tsetup_A22_CLK, Viol);\n    $setup ( A23  , posedge CLK &&& CLK_rising, tsetup_A23_CLK, Viol);\n    $setup ( A24  , posedge CLK &&& CLK_rising, tsetup_A24_CLK, Viol);\n\n    $setup ( A1   , negedge CLK &&& CLK_falling, tsetup_A1_CLK, Viol);\n    $setup ( A2   , negedge CLK &&& CLK_falling, tsetup_A2_CLK, Viol);\n    $setup ( A3   , negedge CLK &&& CLK_falling, tsetup_A3_CLK, Viol);\n    $setup ( A4   , negedge CLK &&& CLK_falling, tsetup_A4_CLK, Viol);\n    $setup ( A5   , negedge CLK &&& CLK_falling, tsetup_A5_CLK, Viol);\n    $setup ( A6   , negedge CLK &&& CLK_falling, tsetup_A6_CLK, Viol);\n    $setup ( A7   , negedge CLK &&& CLK_falling, tsetup_A7_CLK, Viol);\n    $setup ( A8   , negedge CLK &&& CLK_falling, tsetup_A8_CLK, Viol);\n    $setup ( A9   , negedge CLK &&& CLK_falling, tsetup_A9_CLK, Viol);\n    $setup ( A10  , negedge CLK &&& CLK_falling, tsetup_A10_CLK, Viol);\n    $setup ( A11  , negedge CLK &&& CLK_falling, tsetup_A11_CLK, Viol);\n    $setup ( A12  , negedge CLK &&& CLK_falling, tsetup_A12_CLK, Viol);\n    $setup ( A13  , negedge CLK &&& CLK_falling, tsetup_A13_CLK, Viol);\n    $setup ( A14  , negedge CLK &&& CLK_falling, tsetup_A14_CLK, Viol);\n    $setup ( A15  , negedge CLK &&& CLK_falling, tsetup_A15_CLK, Viol);\n    $setup ( A16  , negedge CLK &&& CLK_falling, tsetup_A16_CLK, Viol);\n    $setup ( A17  , negedge CLK &&& CLK_falling, tsetup_A17_CLK, Viol);\n    $setup ( A18  , negedge CLK &&& CLK_falling, tsetup_A18_CLK, Viol);\n    $setup ( A19  , negedge CLK &&& CLK_falling, tsetup_A19_CLK, Viol);\n    $setup ( A20  , negedge CLK &&& CLK_falling, tsetup_A20_CLK, Viol);\n    $setup ( A21  , negedge CLK &&& CLK_falling, tsetup_A21_CLK, Viol);\n    $setup ( A22  , negedge CLK &&& CLK_falling, tsetup_A22_CLK, Viol);\n    $setup ( A23  , negedge CLK &&& CLK_falling, tsetup_A23_CLK, Viol);\n    $setup ( A24  , negedge CLK &&& CLK_falling, tsetup_A24_CLK, Viol);\n\n    $setup ( negedge ADVNeg , posedge CLK &&& CLK_rising ,\n             tsetup_ADVNeg_CLK, Viol);\n    $setup ( negedge ADVNeg , negedge CLK &&& CLK_falling ,\n             tsetup_ADVNeg_CLK, Viol);\n\n    $setup ( negedge CENeg  , posedge CLK &&& CLK_rising ,\n             tsetup_CENeg_CLK, Viol);\n    $setup ( negedge CENeg  , negedge CLK &&& CLK_falling ,\n             tsetup_CENeg_CLK, Viol);\n\n    $setup ( posedge WENeg  , posedge CLK &&& CLK_rising ,\n             tsetup_WENeg_CLK, Viol);\n    $setup ( posedge WENeg  , negedge CLK &&& CLK_falling ,\n             tsetup_WENeg_CLK, Viol);\n\n    $setup ( negedge CENeg  , negedge WENeg , tsetup_CENeg_WENeg, Viol);\n\n    $setup ( DQ0   , posedge WENeg , tsetup_DQ0_WENeg, Viol);\n    $setup ( DQ1   , posedge WENeg , tsetup_DQ1_WENeg, Viol);\n    $setup ( DQ2   , posedge WENeg , tsetup_DQ2_WENeg, Viol);\n    $setup ( DQ3   , posedge WENeg , tsetup_DQ3_WENeg, Viol);\n    $setup ( DQ4   , posedge WENeg , tsetup_DQ4_WENeg, Viol);\n    $setup ( DQ5   , posedge WENeg , tsetup_DQ5_WENeg, Viol);\n    $setup ( DQ6   , posedge WENeg , tsetup_DQ6_WENeg, Viol);\n    $setup ( DQ7   , posedge WENeg , tsetup_DQ7_WENeg, Viol);\n    $setup ( DQ8   , posedge WENeg , tsetup_DQ8_WENeg, Viol);\n    $setup ( DQ9   , posedge WENeg , tsetup_DQ9_WENeg, Viol);\n    $setup ( DQ10  , posedge WENeg , tsetup_DQ10_WENeg, Viol);\n    $setup ( DQ11  , posedge WENeg , tsetup_DQ11_WENeg, Viol);\n    $setup ( DQ12  , posedge WENeg , tsetup_DQ12_WENeg, Viol);\n    $setup ( DQ13  , posedge WENeg , tsetup_DQ13_WENeg, Viol);\n    $setup ( DQ14  , posedge WENeg , tsetup_DQ14_WENeg, Viol);\n    $setup ( DQ15  , posedge WENeg , tsetup_DQ15_WENeg, Viol);\n\n    $setup ( A1   , posedge WENeg , tsetup_A1_WENeg, Viol);\n    $setup ( A2   , posedge WENeg , tsetup_A2_WENeg, Viol);\n    $setup ( A3   , posedge WENeg , tsetup_A3_WENeg, Viol);\n    $setup ( A4   , posedge WENeg , tsetup_A4_WENeg, Viol);\n    $setup ( A5   , posedge WENeg , tsetup_A5_WENeg, Viol);\n    $setup ( A6   , posedge WENeg , tsetup_A6_WENeg, Viol);\n    $setup ( A7   , posedge WENeg , tsetup_A7_WENeg, Viol);\n    $setup ( A8   , posedge WENeg , tsetup_A8_WENeg, Viol);\n    $setup ( A9   , posedge WENeg , tsetup_A9_WENeg, Viol);\n    $setup ( A10  , posedge WENeg , tsetup_A10_WENeg, Viol);\n    $setup ( A11  , posedge WENeg , tsetup_A11_WENeg, Viol);\n    $setup ( A12  , posedge WENeg , tsetup_A12_WENeg, Viol);\n    $setup ( A13  , posedge WENeg , tsetup_A13_WENeg, Viol);\n    $setup ( A14  , posedge WENeg , tsetup_A14_WENeg, Viol);\n    $setup ( A15  , posedge WENeg , tsetup_A15_WENeg, Viol);\n    $setup ( A16  , posedge WENeg , tsetup_A16_WENeg, Viol);\n    $setup ( A17  , posedge WENeg , tsetup_A17_WENeg, Viol);\n    $setup ( A18  , posedge WENeg , tsetup_A18_WENeg, Viol);\n    $setup ( A19  , posedge WENeg , tsetup_A19_WENeg, Viol);\n    $setup ( A20  , posedge WENeg , tsetup_A20_WENeg, Viol);\n    $setup ( A21  , posedge WENeg , tsetup_A21_WENeg, Viol);\n    $setup ( A22  , posedge WENeg , tsetup_A22_WENeg, Viol);\n    $setup ( A23  , posedge WENeg , tsetup_A23_WENeg, Viol);\n    $setup ( A24  , posedge WENeg , tsetup_A24_WENeg, Viol);\n\n    $setup (posedge ADVNeg, posedge WENeg , tsetup_ADVNeg_WENeg, Viol);\n    $setup (posedge WPNeg, posedge WENeg , tsetup_WPNeg_WENeg, Viol);\n\n    $setup (posedge CLK &&& CLK_rising, negedge WENeg ,\n            tsetup_CLK_WENeg, Viol);\n    $setup (negedge CLK &&& CLK_falling, negedge WENeg ,\n            tsetup_CLK_WENeg, Viol);\n\n    $setup (posedge WENeg, negedge OENeg , tsetup_WENeg_OENeg, Viol);\n\n    $hold ( posedge WENeg,  CENeg, thold_CENeg_WENeg, Viol);\n\n    $hold (  posedge WENeg ,DQ0 , thold_DQ0_WENeg, Viol);\n    $hold (  posedge WENeg ,DQ1 , thold_DQ1_WENeg, Viol);\n    $hold (  posedge WENeg ,DQ2 , thold_DQ2_WENeg, Viol);\n    $hold (  posedge WENeg ,DQ3 , thold_DQ3_WENeg, Viol);\n    $hold (  posedge WENeg ,DQ4 , thold_DQ4_WENeg, Viol);\n    $hold (  posedge WENeg ,DQ5 , thold_DQ5_WENeg, Viol);\n    $hold (  posedge WENeg ,DQ6 , thold_DQ6_WENeg, Viol);\n    $hold (  posedge WENeg ,DQ7 , thold_DQ7_WENeg, Viol);\n    $hold (  posedge WENeg ,DQ8 , thold_DQ8_WENeg, Viol);\n    $hold (  posedge WENeg ,DQ9 , thold_DQ9_WENeg, Viol);\n    $hold (  posedge WENeg ,DQ10, thold_DQ10_WENeg, Viol);\n    $hold (  posedge WENeg ,DQ11, thold_DQ11_WENeg, Viol);\n    $hold (  posedge WENeg ,DQ12, thold_DQ12_WENeg, Viol);\n    $hold (  posedge WENeg ,DQ13, thold_DQ13_WENeg, Viol);\n    $hold (  posedge WENeg ,DQ14, thold_DQ14_WENeg, Viol);\n    $hold (  posedge WENeg ,DQ15, thold_DQ15_WENeg, Viol);\n\n    $hold (  posedge WENeg ,A1, thold_A1_WENeg, Viol);\n    $hold (  posedge WENeg ,A2, thold_A2_WENeg, Viol);\n    $hold (  posedge WENeg ,A3, thold_A3_WENeg, Viol);\n    $hold (  posedge WENeg ,A4, thold_A4_WENeg, Viol);\n    $hold (  posedge WENeg ,A5, thold_A5_WENeg, Viol);\n    $hold (  posedge WENeg ,A6, thold_A6_WENeg, Viol);\n    $hold (  posedge WENeg ,A7, thold_A7_WENeg, Viol);\n    $hold (  posedge WENeg ,A8, thold_A8_WENeg, Viol);\n    $hold (  posedge WENeg ,A9, thold_A9_WENeg, Viol);\n    $hold (  posedge WENeg ,A10, thold_A10_WENeg, Viol);\n    $hold (  posedge WENeg ,A11, thold_A11_WENeg, Viol);\n    $hold (  posedge WENeg ,A12, thold_A12_WENeg, Viol);\n    $hold (  posedge WENeg ,A13, thold_A13_WENeg, Viol);\n    $hold (  posedge WENeg ,A14, thold_A14_WENeg, Viol);\n    $hold (  posedge WENeg ,A15, thold_A15_WENeg, Viol);\n    $hold (  posedge WENeg ,A16, thold_A16_WENeg, Viol);\n    $hold (  posedge WENeg ,A17, thold_A17_WENeg, Viol);\n    $hold (  posedge WENeg ,A18, thold_A18_WENeg, Viol);\n    $hold (  posedge WENeg ,A19, thold_A19_WENeg, Viol);\n    $hold (  posedge WENeg ,A20, thold_A20_WENeg, Viol);\n    $hold (  posedge WENeg ,A21, thold_A21_WENeg, Viol);\n    $hold (  posedge WENeg ,A22, thold_A22_WENeg, Viol);\n    $hold (  posedge WENeg ,A23, thold_A23_WENeg, Viol);\n    $hold (  posedge WENeg ,A24, thold_A24_WENeg, Viol);\n\n    $hold (  posedge ADVNeg ,A1, thold_A1_ADVNeg, Viol);\n    $hold (  posedge ADVNeg ,A2, thold_A2_ADVNeg, Viol);\n    $hold (  posedge ADVNeg ,A3, thold_A3_ADVNeg, Viol);\n    $hold (  posedge ADVNeg ,A4, thold_A4_ADVNeg, Viol);\n    $hold (  posedge ADVNeg ,A5, thold_A5_ADVNeg, Viol);\n    $hold (  posedge ADVNeg ,A6, thold_A6_ADVNeg, Viol);\n    $hold (  posedge ADVNeg ,A7, thold_A7_ADVNeg, Viol);\n    $hold (  posedge ADVNeg ,A8, thold_A8_ADVNeg, Viol);\n    $hold (  posedge ADVNeg ,A9, thold_A9_ADVNeg, Viol);\n    $hold (  posedge ADVNeg ,A10, thold_A10_ADVNeg, Viol);\n    $hold (  posedge ADVNeg ,A11, thold_A11_ADVNeg, Viol);\n    $hold (  posedge ADVNeg ,A12, thold_A12_ADVNeg, Viol);\n    $hold (  posedge ADVNeg ,A13, thold_A13_ADVNeg, Viol);\n    $hold (  posedge ADVNeg ,A14, thold_A14_ADVNeg, Viol);\n    $hold (  posedge ADVNeg ,A15, thold_A15_ADVNeg, Viol);\n    $hold (  posedge ADVNeg ,A16, thold_A16_ADVNeg, Viol);\n    $hold (  posedge ADVNeg ,A17, thold_A17_ADVNeg, Viol);\n    $hold (  posedge ADVNeg ,A18, thold_A18_ADVNeg, Viol);\n    $hold (  posedge ADVNeg ,A19, thold_A19_ADVNeg, Viol);\n    $hold (  posedge ADVNeg ,A20, thold_A20_ADVNeg, Viol);\n    $hold (  posedge ADVNeg ,A21, thold_A21_ADVNeg, Viol);\n    $hold (  posedge ADVNeg ,A22, thold_A22_ADVNeg, Viol);\n    $hold (  posedge ADVNeg ,A23, thold_A23_ADVNeg, Viol);\n    $hold (  posedge ADVNeg ,A24, thold_A24_ADVNeg, Viol);\n\n    $hold ( posedge CLK &&& CLK_rising, A1  , thold_A1_CLK, Viol);\n    $hold ( posedge CLK &&& CLK_rising, A2  , thold_A2_CLK, Viol);\n    $hold ( posedge CLK &&& CLK_rising, A3  , thold_A3_CLK, Viol);\n    $hold ( posedge CLK &&& CLK_rising, A4  , thold_A4_CLK, Viol);\n    $hold ( posedge CLK &&& CLK_rising, A5  , thold_A5_CLK, Viol);\n    $hold ( posedge CLK &&& CLK_rising, A6  , thold_A6_CLK, Viol);\n    $hold ( posedge CLK &&& CLK_rising, A7  , thold_A7_CLK, Viol);\n    $hold ( posedge CLK &&& CLK_rising, A8  , thold_A8_CLK, Viol);\n    $hold ( posedge CLK &&& CLK_rising, A9  , thold_A9_CLK, Viol);\n    $hold ( posedge CLK &&& CLK_rising, A10 , thold_A10_CLK, Viol);\n    $hold ( posedge CLK &&& CLK_rising, A11 , thold_A11_CLK, Viol);\n    $hold ( posedge CLK &&& CLK_rising, A12 , thold_A12_CLK, Viol);\n    $hold ( posedge CLK &&& CLK_rising, A13 , thold_A13_CLK, Viol);\n    $hold ( posedge CLK &&& CLK_rising, A14 , thold_A14_CLK, Viol);\n    $hold ( posedge CLK &&& CLK_rising, A15 , thold_A15_CLK, Viol);\n    $hold ( posedge CLK &&& CLK_rising, A16 , thold_A16_CLK, Viol);\n    $hold ( posedge CLK &&& CLK_rising, A17 , thold_A17_CLK, Viol);\n    $hold ( posedge CLK &&& CLK_rising, A18 , thold_A18_CLK, Viol);\n    $hold ( posedge CLK &&& CLK_rising, A19 , thold_A19_CLK, Viol);\n    $hold ( posedge CLK &&& CLK_rising, A20 , thold_A20_CLK, Viol);\n    $hold ( posedge CLK &&& CLK_rising, A21 , thold_A21_CLK, Viol);\n    $hold ( posedge CLK &&& CLK_rising, A22 , thold_A22_CLK, Viol);\n    $hold ( posedge CLK &&& CLK_rising, A23 , thold_A23_CLK, Viol);\n    $hold ( posedge CLK &&& CLK_rising, A24 , thold_A24_CLK, Viol);\n\n    $hold ( negedge CLK &&& CLK_falling, A1  , thold_A1_CLK, Viol);\n    $hold ( negedge CLK &&& CLK_falling, A2  , thold_A2_CLK, Viol);\n    $hold ( negedge CLK &&& CLK_falling, A3  , thold_A3_CLK, Viol);\n    $hold ( negedge CLK &&& CLK_falling, A4  , thold_A4_CLK, Viol);\n    $hold ( negedge CLK &&& CLK_falling, A5  , thold_A5_CLK, Viol);\n    $hold ( negedge CLK &&& CLK_falling, A6  , thold_A6_CLK, Viol);\n    $hold ( negedge CLK &&& CLK_falling, A7  , thold_A7_CLK, Viol);\n    $hold ( negedge CLK &&& CLK_falling, A8  , thold_A8_CLK, Viol);\n    $hold ( negedge CLK &&& CLK_falling, A9  , thold_A9_CLK, Viol);\n    $hold ( negedge CLK &&& CLK_falling, A10 , thold_A10_CLK, Viol);\n    $hold ( negedge CLK &&& CLK_falling, A11 , thold_A11_CLK, Viol);\n    $hold ( negedge CLK &&& CLK_falling, A12 , thold_A12_CLK, Viol);\n    $hold ( negedge CLK &&& CLK_falling, A13 , thold_A13_CLK, Viol);\n    $hold ( negedge CLK &&& CLK_falling, A14 , thold_A14_CLK, Viol);\n    $hold ( negedge CLK &&& CLK_falling, A15 , thold_A15_CLK, Viol);\n    $hold ( negedge CLK &&& CLK_falling, A16 , thold_A16_CLK, Viol);\n    $hold ( negedge CLK &&& CLK_falling, A17 , thold_A17_CLK, Viol);\n    $hold ( negedge CLK &&& CLK_falling, A18 , thold_A18_CLK, Viol);\n    $hold ( negedge CLK &&& CLK_falling, A19 , thold_A19_CLK, Viol);\n    $hold ( negedge CLK &&& CLK_falling, A20 , thold_A20_CLK, Viol);\n    $hold ( negedge CLK &&& CLK_falling, A21 , thold_A21_CLK, Viol);\n    $hold ( negedge CLK &&& CLK_falling, A22 , thold_A22_CLK, Viol);\n    $hold ( negedge CLK &&& CLK_falling, A23 , thold_A23_CLK, Viol);\n    $hold ( negedge CLK &&& CLK_falling, A24 , thold_A24_CLK, Viol);\n\n    $width ( posedge CENeg , tpw_CENeg_posedge );\n    $width ( posedge ADVNeg, tpw_ADVNeg_posedge );\n    $width ( negedge ADVNeg, tpw_ADVNeg_negedge );\n    $width ( posedge CLK   , tpw_CLK_posedge );\n    $width ( negedge CLK   , tpw_CLK_negedge );\n    $width ( posedge WENeg , tpw_WENeg_posedge );\n    $width ( negedge WENeg , tpw_WENeg_negedge );\n    $width ( negedge RSTNeg, tpw_RSTNeg_negedge );\n    $period( posedge CLK   , tperiod_CLK);\n    $period( negedge CLK   , tperiod_CLK);\n\nendspecify\n\n    //tdevice parameters aligned to model timescale\n\n    // Program EraseParameter\n    time tdevice_EraseParameter\n                            = tdevice_EraseParameter_td*1000; //2.5 sec;\n    // Parameter Block Erase - 12V\n    time tdevice_EraseMain = tdevice_EraseMain_td*1000; //4 sec;\n\n///////////////////////////////////////////////////////////////////////////////\n// Main Behavior Block                                                       //\n///////////////////////////////////////////////////////////////////////////////\n\n    always @(DQIn, DQOut)\n    begin\n        if (DQIn==DQOut)\n            deq=1'b1;\n        else\n            deq=1'b0;\n    end\n    // chech when data is generated from model to avoid setuphold check in\n    // those occasion\n    assign deg=deq;\n\n    // initialize memory and load preload files if any\n    initial\n    begin: InitMemory\n        integer i;\n        for (i=0;i<=MemSize;i=i+1)\n        begin\n            MemData[i]=MaxData;\n        end\n        if ((UserPreload) && !(mem_file_name == \"none\"))\n        begin\n            // File Read Section\n            //#i28f512p33_2 memory file\n            //#   /         - comment\n            //#   @aaaaa    - <aaaaa> stands for address\n            //#   dddd      - <dddd> is word to be written at Mem(aaaaa++)\n            //#                 (aaaaa is incremented at every load)\n            //#\n            //#   only first 1-6 columns are loaded. NO empty lines !\n            $readmemh(mem_file_name, MemData);\n        end\n\n        for (i=0;i<=BlockNum;i=i+1)\n        begin\n            OTP[i]=1'b0;\n        end\n        if ((UserPreload) && !(otp_blocks_file == \"none\"))\n            begin\n            // File Read Section\n            //#i28f512p33_2 memory file\n            //#   /         - comment\n            //#   @aaa      - <aaa> stands for address\n            //#   dddd      - <dddd> is word to be written at OTP(aaa++)\n            //#                 (aaa is incremented at every load)\n            //#\n            //#   only first 1-6 columns are loaded. NO empty lines !\n            $readmemh(otp_blocks_file, OTP);\n        end\n\n        PR[9'h80] = 16'hFFFE;\n        for (i=9'h81;i<=9'h109;i=i+1)\n        begin\n            PR[i]=MaxData;\n        end\n        if ((UserPreload) && !(prot_reg_file == \"none\"))\n        begin\n            // File Read Section\n            //#i28f512p33_2 memory file\n            //#   /         - comment\n            //#   @aaa      - <aaa> stands for address\n            //#   dddd      - <dddd> is word to be written at PR(aaa++)\n            //#                 (aaa is incremented at every load)\n            //#\n            //#   only first 1-6 columns are loaded. NO empty lines !\n            $readmemh(prot_reg_file, PR);\n        end\n\n        for (i=0;i<=BlockNum;i=i+1)\n        begin\n            Block_Lock[i] = LOCKED;\n            BlockLockBit[i] = 1'b1;\n            BlockLockDownBit[i] = 1'b0;\n        end\n    end\n\n    initial\n    begin\n        ///////////////////////////////////////////////////////////////////////\n        //CFI array data\n        ///////////////////////////////////////////////////////////////////////\n\n        CFI_array[9'h10]=16'h51;\n        CFI_array[9'h11]=16'h52;\n        CFI_array[9'h12]=16'h59;\n        CFI_array[9'h13]=16'h01;\n        CFI_array[9'h14]=16'h00;\n        CFI_array[9'h15]=16'h0A;\n        CFI_array[9'h16]=16'h01;\n        CFI_array[9'h17]=16'h00;\n        CFI_array[9'h18]=16'h00;\n        CFI_array[9'h19]=16'h00;\n        CFI_array[9'h1A]=16'h00;\n        // System Interface Information\n        CFI_array[9'h1B]=16'h23;\n        CFI_array[9'h1C]=16'h36;\n        CFI_array[9'h1D]=16'h85;\n        CFI_array[9'h1E]=16'h95;\n        CFI_array[9'h1F]=16'h08;\n        CFI_array[9'h20]=16'h09;\n        CFI_array[9'h21]=16'h0A;\n        CFI_array[9'h22]=16'h00;\n        CFI_array[9'h23]=16'h01;\n        CFI_array[9'h24]=16'h01;\n        CFI_array[9'h25]=16'h02;\n        CFI_array[9'h26]=16'h00;\n        // Device Geometry definition\n        CFI_array[9'h27]=16'h19;\n        CFI_array[9'h28]=16'h01;\n        CFI_array[9'h29]=16'h00;\n        CFI_array[9'h2A]=16'h06;\n        CFI_array[9'h2B]=16'h00;\n        CFI_array[9'h2C]=16'h02;\n        CFI_array[9'h2D]=16'h03;\n        CFI_array[9'h2E]=16'h00;\n        CFI_array[9'h2F]=16'h80;\n        CFI_array[9'h30]=16'h00;\n        CFI_array[9'h31]=16'hFE;\n        CFI_array[9'h32]=16'h00;\n        CFI_array[9'h33]=16'h00;\n        CFI_array[9'h34]=16'h02;\n        CFI_array[9'h35]=16'h00;\n        CFI_array[9'h36]=16'h00;\n        CFI_array[9'h37]=16'h00;\n        CFI_array[9'h38]=16'h00;\n        // Primary-vendor specific extended query\n        CFI_array[9'h10A]=16'h50;\n        CFI_array[9'h10B]=16'h52;\n        CFI_array[9'h10C]=16'h49;\n        CFI_array[9'h10D]=16'h31;\n        CFI_array[9'h10E]=16'h34;\n        CFI_array[9'h10F]=16'hE6;\n        CFI_array[9'h110]=16'h01;\n        CFI_array[9'h111]=16'h00;\n        CFI_array[9'h112]=16'h00; // Bottom Parameter Block Lower die\n        CFI_array[9'h113]=16'h01;\n        CFI_array[9'h114]=16'h03;\n        CFI_array[9'h115]=16'h00;\n        CFI_array[9'h116]=16'h30;\n        CFI_array[9'h117]=16'h90;\n        // Protection register information\n        CFI_array[9'h118]=16'h02;\n        CFI_array[9'h119]=16'h80;\n        CFI_array[9'h11A]=16'h00;\n        CFI_array[9'h11B]=16'h03;\n        CFI_array[9'h11C]=16'h03;\n        CFI_array[9'h11D]=16'h89;\n        CFI_array[9'h11E]=16'h00;\n        CFI_array[9'h11F]=16'h00;\n        CFI_array[9'h120]=16'h00;\n        CFI_array[9'h121]=16'h00;\n        CFI_array[9'h122]=16'h00;\n        CFI_array[9'h123]=16'h00;\n        CFI_array[9'h124]=16'h10;\n        CFI_array[9'h125]=16'h00;\n        CFI_array[9'h126]=16'h04;\n        // Burst read information\n        CFI_array[9'h127]=16'h03;\n        CFI_array[9'h128]=16'h04;\n        CFI_array[9'h129]=16'h01;\n        CFI_array[9'h12A]=16'h02;\n        CFI_array[9'h12B]=16'h03;\n        CFI_array[9'h12C]=16'h07;\n        //Partition and Erase Block Region Information\n        CFI_array[9'h12D]=16'h01;\n        CFI_array[9'h12E]=16'h24;\n        CFI_array[9'h12F]=16'h00;\n        CFI_array[9'h130]=16'h01;\n        CFI_array[9'h131]=16'h00;\n        CFI_array[9'h132]=16'h11;\n        CFI_array[9'h133]=16'h00;\n        CFI_array[9'h134]=16'h00;\n        CFI_array[9'h135]=16'h02;\n        CFI_array[9'h136]=16'h03;\n        CFI_array[9'h137]=16'h00;\n        CFI_array[9'h138]=16'h80;\n        CFI_array[9'h139]=16'h00;\n        CFI_array[9'h13A]=16'h64;\n        CFI_array[9'h13B]=16'h00;\n        CFI_array[9'h13C]=16'h02;\n        CFI_array[9'h13D]=16'h03;\n        CFI_array[9'h13E]=16'h00;\n        CFI_array[9'h13F]=16'h80;\n        CFI_array[9'h140]=16'h00;\n        CFI_array[9'h141]=16'h00;\n        CFI_array[9'h142]=16'h00;\n        CFI_array[9'h143]=16'h80;\n        CFI_array[9'h144]=16'hFE;\n        CFI_array[9'h145]=16'h00;\n        CFI_array[9'h146]=16'h00;\n        CFI_array[9'h147]=16'h02;\n        CFI_array[9'h148]=16'h64;\n        CFI_array[9'h149]=16'h00;\n        CFI_array[9'h14A]=16'h02;\n        CFI_array[9'h14B]=16'h03;\n        CFI_array[9'h14C]=16'h00;\n        CFI_array[9'h14D]=16'h80;\n        CFI_array[9'h14E]=16'h00;\n        CFI_array[9'h14F]=16'h00;\n        CFI_array[9'h150]=16'h00;\n        CFI_array[9'h151]=16'h80;\n        CFI_array[9'h152]=16'hFF;\n        CFI_array[9'h153]=16'hFF;\n        CFI_array[9'h154]=16'hFF;\n        CFI_array[9'h155]=16'hFF;\n        CFI_array[9'h156]=16'hFF;\n    end\n\n    initial\n    begin\n        current_state          = RESET_POWER_DOWN;\n        next_state             = RESET_POWER_DOWN;\n        read_state             = READ_ARRAY;\n\n        WordProgram_in         = 1'b0;\n        BuffProgram_in         = 1'b0;\n        BEFP_in                = 1'b0;\n        BEFPsetup_in           = 1'b0;\n        ParameterErase_in      = 1'b0;\n        MainErase_in           = 1'b0;\n        ProgramSuspend_in      = 1'b0;\n        EraseSuspend_in        = 1'b0;\n        RstDuringErsPrg_in     = 1'b0;\n\n        CLOCK           = 1'b0;\n        Write           = 1'b0;\n        Read            = 1'b0;\n        Pmode           = 1'b0;\n        abort           = 1'b0;\n        ExtendProgTime  = 1'b0;\n        AssertWAITOut   = 1'b0;\n        DeassertWAITOut = 1'b0;\n        read_out        = 1'b0;\n\n        SR      = 8'b10000000;\n        RCR     = 16'b1011111111001111;\n        LATCHED = 1'b0;\n        Viol    = 1'b0;\n        word_cntr = 0;\n\n    end\n\n    ///////////////////////////////////////////////////////////////////////////\n    //// Internal Delays\n    ///////////////////////////////////////////////////////////////////////////\n    always @(posedge BEFP_in)\n    begin:BEFP\n        BEFP_out = 1'b1;\n        #tdevice_BEFP BEFP_out = 1'b0;\n    end\n\n    always @(posedge BEFPsetup_in)\n    begin:BEFPsetup\n        BEFPsetup_out = 1'b1;\n        #tdevice_BEFPsetup BEFPsetup_out = 1'b0;\n    end\n\n    always @(posedge ProgramSuspend_in)\n    begin:ProgramSuspend\n        ProgramSuspend_out = 1'b1;\n        #tdevice_ProgramSuspend ProgramSuspend_out = 1'b0;\n    end\n\n    always @(posedge EraseSuspend_in)\n    begin:EraseSuspend\n        EraseSuspend_out = 1'b1;\n        #tdevice_EraseSuspend EraseSuspend_out = 1'b0;\n    end\n\n    always @(posedge RstDuringErsPrg_in)\n    begin:RstDuringErsPrg\n        RstDuringErsPrg_out = 1'b1;\n        #tdevice_RstDuringErsPrg RstDuringErsPrg_out = 1'b0;\n    end\n\n    //////////////////////////////////////////////////////////////\n    // Clock control\n    //////////////////////////////////////////////////////////////\n\n    always @ (posedge CLK_ipd)\n    begin : CLKControl1\n        if ((RSTNeg_ipd) && (~CENeg_ipd) && (WENeg_ipd) &&\n        (RCR[15] == 1'b0) && (RCR[6] == 1'b1) &&\n        (current_state != RESET_POWER_DOWN))\n        begin\n            CLOCK = 1'b1;\n            #1 CLOCK <= 1'b0;\n        end\n    end\n\n    always @ (negedge CLK_ipd)\n    begin : CLKControl2\n        if ((RSTNeg_ipd) && (~CENeg_ipd) && (WENeg_ipd) &&\n        (RCR[15] == 1'b0) && (RCR[6] == 1'b0) &&\n        (current_state != RESET_POWER_DOWN))\n        begin\n            CLOCK = 1'b1;\n            #1 CLOCK <= 1'b0;\n        end\n    end\n\n    always @ (negedge RSTNeg_ipd)\n    begin : RSTControl\n        if (WordProgram_out ||\n        BuffProgram_out ||\n        ParameterErase_out || MainErase_out || BEFP_out)\n        begin\n            RstDuringErsPrg_in = 1'b0;\n            #1 RstDuringErsPrg_in <= 1'b1;\n        end\n    end\n\n    //////////////////////////////////////////////////////////////////////////\n    //// bus cycle decode\n    //////////////////////////////////////////////////////////////////////////\n    always @ (falling_edge_ADVNeg or rising_edge_ADVNeg or rising_edge_CLOCK\n    or OENeg or RSTNeg or rising_edge_WENeg or rising_edge_CENeg or WENeg\n    or CENeg or Alow_event)\n    begin : BusCycleDecode\n        if (~RSTNeg || CENeg || falling_edge_ADVNeg)\n            LATCHED = 0;\n\n        if (RSTNeg && current_state != RESET_POWER_DOWN)\n        begin\n            if (~CENeg && ~LATCHED && ((rising_edge_ADVNeg && WENeg) ||\n            (~ADVNeg && WENeg && ~RCR[15] && rising_edge_CLOCK) ) )\n            begin\n                LatchedAddr = A;\n                ReadAddr = A;\n                LATCHED = 1'b1;\n                burst_cntr = 0;\n                BurstDelay = RCR[13:11];\n                case (RCR[2:0])\n                    3'b001: BurstLength = 4;\n                    3'b010: BurstLength = 8;\n                    3'b011: BurstLength = 16;\n                    3'b111: BurstLength = 0;\n                endcase\n                DataHold = 0;\n            end\n\n            // Write control\n            if (OENeg)\n            begin\n                if (~WENeg && ~CENeg)\n                    Write = 0;\n                else if ((~CENeg && rising_edge_WENeg) || (~WENeg &&\n                rising_edge_CENeg)||(rising_edge_CENeg && rising_edge_WENeg))\n                begin\n                    LatchedData = DQIn;\n                    LatchedAddr = A;\n                    Write = 1;\n                end\n            end\n\n            // Read control\n            if (RCR[15])\n            begin\n                if (WENeg && ~CENeg && ~OENeg)\n                begin\n                    if (~ADVNeg)\n                        ReadAddr = A;\n                    Read = 1;\n                end\n                else\n                begin\n                    Read = 0;\n                    Pmode = 0;\n                end\n                if (Read && Alow_event)\n                begin\n                    Pmode = 1;\n                    Pmode <= #2 0;\n                end\n            end\n            else\n            begin\n                if (rising_edge_CLOCK)\n                begin\n                    if (BurstDelay > 0)\n                    begin\n                        #1 BurstDelay = BurstDelay - 1;\n                        if (RCR[8] && (BurstDelay == 0 || (BurstDelay == 1\n                        && RCR[9] ) ) )\n                            DeassertWAITOut = ~(DeassertWAITOut);\n                    end\n                    else\n                    begin\n                        if (DataHold == 0)\n                        begin\n                            burst_cntr = burst_cntr + 1;\n                            if (~OENeg)\n                                Read = ~(Read);\n                            if (RCR[9])\n                                DataHold = 1;\n                            if ( (burst_cntr > (BurstLength - RCR[8]) ) &&\n                            BurstLength > 0)\n                                AssertWAITOut = ~(AssertWAITOut);\n                            else if (read_state == READ_ARRAY && ~RCR[9] &&\n                            RCR[13:11] > 4)\n                            begin\n                                if (~RCR[8])\n                                begin\n                                    if (burst_cntr > 4 || burst_cntr <= 0)\n                                        AssertWAITOut = ~(AssertWAITOut);\n                                    else\n                                        DeassertWAITOut = ~(DeassertWAITOut);\n                                end\n                                else\n                                begin\n                                    if (burst_cntr >= 4 || burst_cntr < 0)\n                                        AssertWAITOut = ~(AssertWAITOut);\n                                    else\n                                        DeassertWAITOut = ~(DeassertWAITOut);\n                                end\n                            end\n                                DeassertWAITOut = ~(DeassertWAITOut);\n                        end\n                        else\n                            DataHold = DataHold - 1;\n                    end\n                end\n            end\n        end\n    end\n\n//////////////////////////////////////////////////////////////////////////////\n//// sequential process for reset control and FSM state transition\n//////////////////////////////////////////////////////////////////////////////\n    always @(next_state)\n    begin : FSM\n        if (ExtendProgTime == 1'b0)\n            current_state = next_state;\n    end\n\n    ////////////////////////////////////////////////////////////////////////////\n    //     obtain 'LAST_EVENT information\n    ////////////////////////////////////////////////////////////////////////////\n    always @(negedge OENeg_ipd)\n    begin\n        OENeg_event = $time;\n    end\n    always @(negedge CENeg_ipd)\n    begin\n        CENeg_event = $time;\n    end\n    always @(A)\n    begin\n        ADDR_event = $time;\n    end\n\n    ///////////////////////////////////////////////////////////////////////////\n    // FSM - Combinational process for next state generation\n    ///////////////////////////////////////////////////////////////////////////\n    always @(falling_edge_RSTNeg or rising_edge_RSTNeg or rising_edge_Write or\n        RstDuringErsPrg_out_event or WordProgram_out_event or abort or\n        ProgramSuspend_out_event or BuffProgram_out_event\n        or ExtendProgTime_event or falling_edge_EraseSuspend_out or\n        ParameterErase_out_event or falling_edge_MainErase_out\n        or falling_edge_BEFPsetup_out or falling_edge_BEFP_out\n        )\n    begin : StateGen\n\n        if (falling_edge_RSTNeg)\n            next_state = RESET_POWER_DOWN;\n        else\n        begin\n            case (current_state)\n\n            RESET_POWER_DOWN :\n            begin\n                if (((rising_edge_RSTNeg && ~RstDuringErsPrg_out) ||\n                (RstDuringErsPrg_out_event && ~RstDuringErsPrg_out)) &&\n                $time > 0 )\n                begin\n                    next_state = READY;\n                end\n            end\n\n            READY:\n            begin\n                if (rising_edge_Write)\n                begin\n                    case (LatchedData)\n                        16'h10, 16'h40 : next_state = PROG_SETUP;\n                        16'hE8 : next_state = BP_SETUP;\n                        16'h20 : next_state = ERASE_SETUP;\n                        16'h80 : next_state = BEFP_SETUP;\n                        16'h60 : next_state = LOCK_SETUP;\n                        16'hC0 : next_state = OTP_SETUP;\n                        default : next_state = current_state;\n                    endcase\n                end\n            end\n\n            LOCK_SETUP  :\n            begin\n                if (rising_edge_Write)\n                    next_state = READY;\n            end\n\n            OTP_SETUP  :\n            begin\n                if (rising_edge_Write)\n                    next_state = OTP_BUSY;\n            end\n\n            OTP_BUSY :\n            begin\n                if (abort ||\n                (WordProgram_out_event && ~WordProgram_out) )\n                    next_state = READY;\n            end\n\n            PROG_SETUP :\n            begin\n                if (rising_edge_Write)\n                    next_state = PROG_BUSY;\n            end\n\n            PROG_BUSY :\n            begin\n                if (abort ||\n                (WordProgram_out_event && ~WordProgram_out) )\n                    next_state = READY;\n                else if (ProgramSuspend_out_event && ~ProgramSuspend_out)\n                    next_state = PROG_SUSP;\n            end\n\n            PROG_SUSP :\n            begin\n                if (rising_edge_Write && LatchedData == 16'hD0)\n                    next_state = PROG_BUSY;\n            end\n\n            BP_SETUP :\n            begin\n                if (rising_edge_Write)\n                begin\n                    word_cnt = LatchedData + 1;\n                    next_state = BP_LOAD;\n                end\n            end\n\n            BP_LOAD :\n            begin\n                if (rising_edge_Write)\n                begin\n                    word_cnt = word_cnt - 1;\n                    if (word_cnt == 0)\n                        next_state = BP_CONFIRM;\n                end\n            end\n\n            BP_CONFIRM :\n            begin\n                if (rising_edge_Write)\n                begin\n                    if (LatchedData == 16'hD0)\n                        next_state = BP_BUSY;\n                    else\n                        next_state = READY;\n                end\n            end\n\n            BP_BUSY :\n            begin\n                if (abort ||\n                (BuffProgram_out_event && ~BuffProgram_out && ~ExtendProgTime))\n                    next_state = READY;\n                else if (ProgramSuspend_out_event && ~ProgramSuspend_out)\n                    next_state = BP_SUSP;\n                else if (ExtendProgTime_event)\n                    next_state = current_state;\n            end\n\n            BP_SUSP :\n            begin\n                if (rising_edge_Write && LatchedData == 16'hD0)\n                    next_state = BP_BUSY;\n            end\n\n            ERASE_SETUP :\n            begin\n                if (rising_edge_Write)\n                begin\n                    if (LatchedData == 16'hD0)\n                        next_state = ERASE_BUSY;\n                    else\n                        next_state = READY;\n                end\n            end\n\n            ERASE_BUSY :\n            begin\n                if ((abort ||\n                (ParameterErase_out_event && ~ParameterErase_out) ||\n                (falling_edge_MainErase_out ) ) && ~suspended_erase)\n                    next_state = READY;\n                else if (falling_edge_EraseSuspend_out)\n                    next_state = ERS_SUSP;\n            end\n\n            ERS_SUSP :\n            begin\n                if (rising_edge_Write)\n                begin\n                    case (LatchedData)\n                        16'h10, 16'h40: next_state = PROG_SETUP_ERS_SUSP;\n                        16'hE8 : next_state = BP_SETUP_ERS_SUSP;\n                        16'hD0: next_state = ERASE_BUSY;\n                        16'h60: next_state = LOCK_SETUP_ERS_SUSP;\n                        default: next_state = current_state;\n                    endcase\n                end\n            end\n\n            PROG_SETUP_ERS_SUSP :\n            begin\n                if (rising_edge_Write)\n                    next_state = PROG_BUSY_ERS_SUSP;\n            end\n\n            PROG_BUSY_ERS_SUSP :\n            begin\n                if (abort ||\n                (WordProgram_out_event && ~WordProgram_out) )\n                    next_state = ERS_SUSP;\n                else if (ProgramSuspend_out_event && ~ProgramSuspend_out)\n                    next_state = PROG_SUSP_ERS_SUSP;\n            end\n\n            PROG_SUSP_ERS_SUSP :\n            begin\n                if (rising_edge_Write && LatchedData == 16'hD0)\n                    next_state = PROG_BUSY_ERS_SUSP;\n            end\n\n            BP_SETUP_ERS_SUSP :\n            begin\n                if (rising_edge_Write)\n                begin\n                    word_cnt = LatchedData + 1;\n                    next_state = BP_LOAD_ERS_SUSP;\n                end\n            end\n\n            BP_LOAD_ERS_SUSP :\n            begin\n                if (rising_edge_Write)\n                begin\n                    word_cnt = word_cnt - 1;\n                    if (word_cnt == 0)\n                        next_state = BP_CONFIRM_ERS_SUSP;\n                end\n            end\n\n            BP_CONFIRM_ERS_SUSP :\n            begin\n                if (rising_edge_Write)\n                begin\n                    if (LatchedData == 16'hD0)\n                        next_state = BP_BUSY_ERS_SUSP;\n                    else\n                        next_state = ERS_SUSP;\n                end\n            end\n\n            BP_BUSY_ERS_SUSP :\n            begin\n                if (abort ||\n                (BuffProgram_out_event && ~BuffProgram_out && ~ExtendProgTime))\n                    next_state = ERS_SUSP;\n                else if (ProgramSuspend_out_event && ~ProgramSuspend_out)\n                    next_state = BP_SUSP_ERS_SUSP;\n                else if (ExtendProgTime_event)\n                    next_state = current_state;\n            end\n\n            BP_SUSP_ERS_SUSP :\n            begin\n                if (rising_edge_Write && LatchedData == 16'hD0)\n                    next_state = BP_BUSY_ERS_SUSP;\n            end\n\n            LOCK_SETUP_ERS_SUSP :\n            begin\n                if (rising_edge_Write)\n                    next_state = ERS_SUSP;\n            end\n\n            BEFP_SETUP :\n            begin\n                if (rising_edge_Write)\n                begin\n                    if (LatchedData != 16'hD0)\n                        next_state = READY;\n                    else\n                    begin\n                        BEFP_block2 = BlockNumber(LatchedAddr);\n                        word_cnt = 32;\n                    end\n                end\n                else if (falling_edge_BEFPsetup_out)\n                begin\n                    if (SR[4] == 1'b0)\n                        next_state = BEFP_LOAD;\n                    else\n                        next_state = READY;\n                end\n            end\n\n            BEFP_LOAD :\n            begin\n                if (rising_edge_Write)\n                begin\n                    if ((BlockNumber(LatchedAddr) != BEFP_block2) &&\n                    LatchedData == 16'hFFFF)\n                        next_state = READY;\n                    else\n                    begin\n                        word_cnt = word_cnt - 1;\n                        if (word_cnt == 0)\n                            next_state = BEFP_BUSY;\n                    end\n                end\n            end\n\n            BEFP_BUSY :\n            begin\n                if (falling_edge_BEFP_out)\n                begin\n                    word_cnt = 32;\n                    next_state = BEFP_LOAD;\n                end\n            end\n            endcase\n        end\n    end\n\n    ////////////////////////////////////////////////////////////////////////////\n    // Functional\n    ////////////////////////////////////////////////////////////////////////////\n    always @(rising_edge_Write or WordProgram_out_event or\n             BuffProgram_out_event or falling_edge_RSTNeg or\n             ParameterErase_out_event or falling_edge_MainErase_out or\n             falling_edge_BEFPsetup_out or falling_edge_BEFP_out or\n             abort or falling_edge_EraseSuspend_out or ProgramSuspend_out_event)\n    begin\n\n        if (rising_edge_Write)\n        begin\n            if ((current_state != RESET_POWER_DOWN) &&\n            (current_state != OTP_BUSY) &&\n            (current_state != PROG_BUSY) &&\n            (current_state != BP_BUSY) &&\n            (current_state != ERASE_BUSY) &&\n            (current_state != PROG_BUSY_ERS_SUSP) &&\n            (current_state != BP_BUSY_ERS_SUSP) &&\n            (current_state != BEFP_SETUP) &&\n            (current_state != BEFP_LOAD) &&\n            (LatchedData == 8'h50))\n                SR = 8'b10000000;\n        end\n\n        case (current_state)\n\n            RESET_POWER_DOWN :\n            begin\n                SR = 8'b10000000;\n                for (i=0;i<=BlockNum;i=i+1)\n                begin\n                    Block_Lock[i] = LOCKED;\n                    BlockLockBit[i] = 1'b1;\n                    BlockLockDownBit[i] = 1'b0;\n                end\n                read_state = READ_ARRAY;\n                RCR = 16'b1011111111001111;\n            end\n\n            READY :\n            begin\n                if (rising_edge_Write)\n                begin\n                    case (LatchedData)\n                        16'hFF : read_state = READ_ARRAY;\n                        16'h70 : read_state = READ_STATUS;\n                        16'h90 : read_state = READ_ID;\n                        16'h98 : read_state = READ_QUERY;\n                    endcase\n                end\n            end\n\n            LOCK_SETUP, LOCK_SETUP_ERS_SUSP :\n            begin\n                if (rising_edge_Write)\n                begin\n                    block_number = BlockNumber(LatchedAddr);\n                    if (LatchedData == 16'h03)\n                    begin\n                        RCR = A[15:0];\n                        read_state = READ_ARRAY;\n                    end\n                    else if (LatchedData == 16'h01)\n                    begin\n                        read_state = READ_STATUS;\n                        if (Block_Lock[block_number] == UNLOCKED)\n                            Block_Lock[block_number] = LOCKED;\n                        BlockLockBit[block_number] = 1'b1;\n                    end\n                    else if (LatchedData == 16'hD0)\n                    begin\n                        read_state = READ_STATUS;\n                        if (!( (Block_Lock[block_number] == LOCKED_DOWN) &&\n                        WPNeg == 1'b0) )\n                        begin\n                            Block_Lock[block_number] = UNLOCKED;\n                            BlockLockBit[block_number] = 0;\n                        end\n                    end\n                    else if (LatchedData == 16'h2F)\n                    begin\n                        read_state = READ_STATUS;\n                        Block_Lock[block_number] = LOCKED_DOWN;\n                        BlockLockBit[block_number] = 1'b1;\n                        BlockLockDownBit[block_number] = 1'b1;\n                    end\n                    else\n                    begin\n                        read_state = READ_STATUS;\n                        SR[4] = 1'b1;\n                        SR[5] = 1'b1;\n                    end\n                end\n                else\n                    read_state = READ_STATUS;\n            end\n\n            OTP_SETUP :\n            begin\n                read_state = READ_STATUS;\n                if (rising_edge_Write)\n                begin\n                    DataBuff[0] = LatchedData;\n                    AddrBuff[0] = LatchedAddr;\n                    WordProgram_in = 1'b1;\n                    WordProgram_in <= #1 1'b0;\n                end\n            end\n\n            OTP_BUSY :\n            begin\n                if (rising_edge_Write)\n                begin\n                    case (LatchedData)\n                        16'hFF : read_state = READ_ARRAY;\n                        16'h70, 16'h90, 16'h98 : read_state = READ_STATUS;\n                    endcase\n                end\n\n                mem_bits = PR[9'h80];\n                prog_bits = PR[9'h89];\n\n                if (VPP != 1'b1)\n                begin\n                    SR[3] = 1'b1;\n                    SR[4] = 1'b1;\n                    SR[7] = 1'b1;\n                    abort = 1'b1;\n                    abort <= #1 1'b0;\n                end\n                else if ((AddrBuff[0] < 9'h80) || (AddrBuff[0] > 9'h109))\n                begin\n                    SR[4] = 1'b1;\n                    SR[7] = 1'b1;\n                    abort = 1'b1;\n                    abort <= #1 1'b0;\n                end\n                else if ((AddrBuff[0] > 9'h80) && (AddrBuff[0] < 9'h85))\n                begin\n                    SR[4] = 1'b1;\n                    SR[7] = 1'b1;\n                    abort = 1'b1;\n                    abort <= #1 1'b0;\n                end\n                else if ((AddrBuff[0] > 9'h84) && (AddrBuff[0] < 9'h89) &&\n                (mem_bits[1] != 1'b1))\n                begin\n                    SR[1] = 1'b1;\n                    SR[4] = 1'b1;\n                    SR[7] = 1'b1;\n                    abort = 1'b1;\n                    abort <= #1 1'b0;\n                end\n                else if ((AddrBuff[0] > 9'h89) && (AddrBuff[0] < 9'h10A) &&\n                (prog_bits[(AddrBuff[0]-9'h8A)/8] != 1'b1))\n                begin\n                    SR[1] = 1'b1;\n                    SR[4] = 1'b1;\n                    SR[7] = 1'b1;\n                    abort = 1'b1;\n                    abort <= #1 1'b0;\n                end\n                else\n                    SR[7] = 1'b0;\n\n                if (falling_edge_RSTNeg)\n                    PR[AddrBuff[0]] = -1;\n\n                if (WordProgram_out_event && ~WordProgram_out && ~abort)\n                begin\n                    if (PR[AddrBuff[0]] > -1)\n                    begin\n                        prog_bits = DataBuff[0];\n                        mem_bits = PR[AddrBuff[0]];\n                        for (i=0; i<= 15; i=i+1)\n                        begin\n                            if (prog_bits[i] == 0)\n                                mem_bits[i] = 0;\n                        end\n                        PR[AddrBuff[0]] = mem_bits;\n                    end\n                    SR[7] = 1;\n                end\n            end\n\n            PROG_SETUP, PROG_SETUP_ERS_SUSP :\n            begin\n                read_state = READ_STATUS;\n                if (rising_edge_Write)\n                begin\n                    DataBuff[0] = LatchedData;\n                    AddrBuff[0] = LatchedAddr;\n                    WordProgram_in = 1;\n                    WordProgram_in <= #1 0;\n                end\n            end\n\n            PROG_BUSY, PROG_BUSY_ERS_SUSP :\n            begin\n                SR[2] = 0;\n                if (rising_edge_Write)\n                begin\n                    case (LatchedData)\n                        16'hFF : read_state = READ_ARRAY;\n                        16'h70 : read_state = READ_STATUS;\n                        16'h90 : read_state = READ_ID;\n                        16'h98 : read_state = READ_QUERY;\n                        16'hB0 :\n                        begin\n                            ProgramSuspend_in = 1'b1;\n                            ProgramSuspend_in <= #1 1'b0;\n                        end\n                    endcase\n                end\n\n                block_number = BlockNumber(AddrBuff[0]);\n\n                if (VPP == 1'b0)\n                begin\n                    SR[3] = 1'b1;\n                    SR[4] = 1'b1;\n                    SR[7] = 1'b1;\n                    abort = 1'b1;\n                    abort <= #1 1'b0;\n                end\n                else if (OTP[block_number] == 1'b1)\n                begin\n                    SR[4] = 1'b1;\n                    SR[7] = 1'b1;\n                    abort = 1'b1;\n                    abort <= #1 1'b0;\n                end\n                else if (Block_Lock[block_number] != UNLOCKED)\n                begin\n                    SR[1] = 1'b1;\n                    SR[4] = 1'b1;\n                    SR[7] = 1'b1;\n                    abort = 1'b1;\n                    abort <= #1 1'b0;\n                end\n                else\n                    SR[7] = 1'b0;\n\n                if (falling_edge_RSTNeg )\n                    MemData[AddrBuff[0]] = -1;\n\n                if (WordProgram_out_event && ~WordProgram_out && ~abort)\n                begin\n                    if (MemData[AddrBuff[0]] > -1 )\n                    begin\n                        prog_bits = DataBuff[0];\n                        mem_bits = MemData[AddrBuff[0]];\n                        for (i= 0; i<= 15; i=i+1)\n                            if (prog_bits[i] == 0)\n                                mem_bits[i] = 0;\n                        MemData[AddrBuff[0]] = mem_bits;\n                    end\n                    SR[7] = 1;\n                end\n            end\n\n            PROG_SUSP, PROG_SUSP_ERS_SUSP :\n            begin\n                SR[2] = 1'b1;\n                SR[7] = 1'b1;\n\n                if (rising_edge_Write)\n                begin\n                    case (LatchedData)\n                        16'hFF : read_state = READ_ARRAY;\n                        16'h70 : read_state = READ_STATUS;\n                        16'h90 : read_state = READ_ID;\n                        16'h98 : read_state = READ_QUERY;\n                        16'hD0 :\n                        begin\n                            WordProgramResume = 1'b1;\n                            WordProgramResume <= #1 1'b0;\n                        end\n                    endcase\n                end\n            end\n\n            BP_SETUP, BP_SETUP_ERS_SUSP :\n            begin\n                read_state = READ_STATUS;\n\n                if (rising_edge_Write)\n                begin\n                    word_number = LatchedData;\n                    word_cntr   = 0;\n                end\n            end\n\n            BP_LOAD, BP_LOAD_ERS_SUSP :\n            begin\n                read_state = READ_STATUS;\n\n                if (rising_edge_Write)\n                begin\n                    DataBuff[word_cntr] = LatchedData;\n                    AddrBuff[word_cntr] = LatchedAddr;\n                    if (word_cntr == 0)\n                    begin\n                        lowest_addr = LatchedAddr;\n                        highest_addr = LatchedAddr;\n                    end\n                    else\n                    begin\n                        if (LatchedAddr < lowest_addr)\n                            lowest_addr = LatchedAddr;\n                        if (LatchedAddr > highest_addr)\n                            highest_addr = LatchedAddr;\n                    end\n                    word_cntr = word_cntr + 1;\n                end\n            end\n\n            BP_CONFIRM, BP_CONFIRM_ERS_SUSP :\n            begin\n                read_state = READ_STATUS;\n\n                if (rising_edge_Write)\n                begin\n                    if (LatchedData != 16'hD0)\n                    begin\n                        SR[7] = 1'b1;\n                        SR[5] = 1'b1;\n                        SR[4] = 1'b1;\n                    end\n                    else if (LatchedData == 16'hD0)\n                    begin\n                        BuffProgram_in = 1;\n                        BuffProgram_in <= #1 0;\n                    end\n                end\n            end\n\n            BP_BUSY, BP_BUSY_ERS_SUSP :\n            begin\n                SR[2] = 0;\n                if (rising_edge_Write)\n                begin\n                    case (LatchedData)\n                        16'hFF : read_state = READ_ARRAY;\n                        16'h70 : read_state = READ_STATUS;\n                        16'h90 : read_state = READ_ID;\n                        16'h98 : read_state = READ_QUERY;\n                        16'hB0 :\n                        begin\n                            suspended_bp = 1'b1;\n                            ProgramSuspend_in = 1'b1;\n                            ProgramSuspend_in <= #1 1'b0;\n                        end\n                    endcase\n                end\n\n                block_number = BlockNumber(AddrBuff[0]);\n\n                if (VPP == 0)\n                begin\n                    SR[3] = 1;\n                    SR[4] = 1;\n                    SR[7] = 1;\n                    abort = 1'b1;\n                    abort <= #1 1'b0;\n                end\n                else if (OTP[block_number] == 1)\n                begin\n                    SR[4] = 1;\n                    SR[7] = 1;\n                    abort = 1'b1;\n                    abort <= #1 1'b0;\n                end\n                else if (Block_Lock[block_number] != UNLOCKED)\n                begin\n                    SR[1] = 1;\n                    SR[4] = 1;\n                    SR[7] = 1;\n                    abort = 1'b1;\n                    abort <= #1 1'b0;\n                end\n                else if ((lowest_addr < AddrBuff[0]) ||\n                (highest_addr > (AddrBuff[0]+word_number)) &&\n                (word_number != -1))\n                begin\n                    SR[4] = 1;\n                    SR[7] = 1;\n                    abort = 1'b1;\n                    abort <= #1 1'b0;\n                end\n                else if (BlockNumber(highest_addr) != block_number)\n                begin\n                    SR[4] = 1;\n                    SR[5] = 1;\n                    SR[7] = 1;\n                    abort = 1'b1;\n                    abort <= #1 1'b0;\n                end\n                else\n                    SR[7] = 0;\n\n                if (falling_edge_RSTNeg)\n                begin\n                    for (j=0;j<=word_number; j=j+1)\n                        MemData[AddrBuff[j]] = -1;\n                end\n\n                if ( BuffProgram_out_event && ~BuffProgram_out\n                && ~suspended_bp && ~abort )\n                begin\n                    for (j=0; j<= word_number; j=j+1)\n                    begin\n                        if (MemData[AddrBuff[j]] > -1 )\n                        begin\n                            prog_bits = DataBuff[j];\n                            mem_bits = MemData[AddrBuff[j]];\n                            for (i=0; i<=15; i=i+1)\n                            begin\n                                if (prog_bits[i] == 1'b0)\n                                    mem_bits[i] = 1'b0;\n                            end\n                            MemData[AddrBuff[j]] = mem_bits;\n                        end\n                    end\n                    for (j=0; j<= word_number; j=j+1)\n                    begin\n                        if ((AddrBuff[j] / 32) != (AddrBuff[0]/32))\n                        begin\n                            ExtendProgTime = 1;\n                            ExtendProgTime <= #1 0;\n                            word_number = -1;\n                            BuffProgram_in = 1'b1;\n                            BuffProgram_in <= #1 1'b0;\n                        end\n                    end\n                    SR[7] = 1;\n                end\n            end\n\n            BP_SUSP, BP_SUSP_ERS_SUSP :\n            begin\n                SR[2] = 1'b1;\n                SR[7] = 1'b1;\n\n                if (rising_edge_Write)\n                begin\n                    case (LatchedData)\n                        16'hFF : read_state = READ_ARRAY;\n                        16'h70 : read_state = READ_STATUS;\n                        16'h90 : read_state = READ_ID;\n                        16'h98 : read_state = READ_QUERY;\n                        16'hD0 :\n                        begin\n                            suspended_bp = 1'b0;\n                            BP_ProgramResume = 1'b1;\n                            BP_ProgramResume <= #1 1'b0;\n                        end\n                    endcase\n                end\n            end\n\n            ERASE_SETUP :\n            begin\n                read_state = READ_STATUS;\n\n                if (rising_edge_Write)\n                begin\n                    if (LatchedData == 16'hD0)\n                    begin\n                        erasing_block = BlockNumber(LatchedAddr);\n                        if (BlockSize(erasing_block) == ParameterBlockSize)\n                        begin\n                            ParameterErase_in = 1;\n                            ParameterErase_in <= #1 0;\n                        end\n                        else\n                        begin\n                            MainErase_in = 1;\n                            MainErase_in <= #1 0;\n                        end\n                    end\n                    else\n                    begin\n                        SR[7] = 1'b1;\n                        SR[5] = 1'b1;\n                        SR[4] = 1'b1;\n                    end\n                end\n            end\n\n            ERASE_BUSY :\n            begin\n                SR[6] = 0;\n\n                if (rising_edge_Write)\n                begin\n                    case (LatchedData)\n                        16'hFF : read_state = READ_ARRAY;\n                        16'h70 : read_state = READ_STATUS;\n                        16'h90 : read_state = READ_ID;\n                        16'h98 : read_state = READ_QUERY;\n                        16'hB0 :\n                        begin\n                            suspended_erase = 1'b1;\n                            EraseSuspend_in = 1'b1;\n                            EraseSuspend_in <= #1 1'b0;\n                        end\n                    endcase\n                end\n\n                aborted = 1'b0;\n\n                if (VPP == 1'b0)\n                begin\n                    SR[3] = 1'b1;\n                    SR[5] = 1'b1;\n                    SR[7] = 1'b1;\n                    abort = 1'b1;\n                    abort <= #1 1'b0;\n                    aborted = 1'b1;\n                end\n                else if (OTP[erasing_block] == 1'b1)\n                begin\n                    SR[5] = 1'b1;\n                    SR[7] = 1'b1;\n                    abort = 1'b1;\n                    abort <= #1 1'b0;\n                    aborted = 1'b1;\n                end\n                else if (Block_Lock[erasing_block] != UNLOCKED)\n                begin\n                    SR[1] = 1'b1;\n                    SR[5] = 1'b1;\n                    SR[7] = 1'b1;\n                    abort = 1'b1;\n                    abort <= #1 1'b0;\n                    aborted = 1'b1;\n                end\n                else\n                    SR[7] = 1'b0;\n\n                block_size = BlockSize(erasing_block);\n                start_addr = StartBlockAddr(erasing_block);\n\n                if (~aborted)\n                begin\n                    for (i = 0; i< block_size; i=i+1 )\n                        MemData[start_addr + i] = -1;\n                end\n\n                if ( ( (ParameterErase_out_event && ~ParameterErase_out)\n                || (falling_edge_MainErase_out)) && ~abort && ~suspended_erase)\n                begin\n                    SR[7] = 1'b1;\n                    for (i=0;i<=block_size;i=i+1)\n                        MemData[start_addr + i] = MaxData;\n                end\n            end\n\n            ERS_SUSP :\n            begin\n                SR[6] = 1'b1;\n                SR[7] = 1'b1;\n\n                if (rising_edge_Write)\n                begin\n                    case (LatchedData)\n                        16'hFF : read_state = READ_ARRAY;\n                        16'h70 : read_state = READ_STATUS;\n                        16'h90 : read_state = READ_ID;\n                        16'h98 : read_state = READ_QUERY;\n                        16'hD0 :\n                        begin\n                            suspended_erase = 1'b0;\n                            if (BlockSize(erasing_block) == ParameterBlockSize)\n                            begin\n                                ParameterEraseResume = 1'b1;\n                                ParameterEraseResume <= #1 1'b0;\n                            end\n                            else\n                            begin\n                                MainEraseResume = 1'b1;\n                                MainEraseResume <= #1 1'b0;\n                            end\n                        end\n                    endcase\n                end\n            end\n\n            BEFP_SETUP :\n            begin\n                read_state = READ_STATUS;\n\n                if (rising_edge_Write && (LatchedData == 16'hD0))\n                begin\n                    BEFP_addr  = LatchedAddr;\n                    BEFP_block = BlockNumber(LatchedAddr);\n                    word_cntr = 0;\n                    if ((VPP != 1'b1) || (VPP_voltage != 9))\n                    begin\n                        SR[3] = 1'b1;\n                        SR[4] = 1'b1;\n                    end\n                    if (Block_Lock[BEFP_block] != UNLOCKED)\n                    begin\n                        SR[1] = 1'b1;\n                        SR[4] = 1'b1;\n                    end\n                    else if (((BEFP_addr % 32) != 0) ||\n                    (OTP[BEFP_block] == 1'b1))\n                        SR[4] = 1'b1;\n                    BEFPsetup_in = 1'b1;\n                    BEFPsetup_in <= #1 1'b0;\n                end\n                else if (falling_edge_BEFPsetup_out)\n                begin\n                    if (SR[4] == 0)\n                    begin\n                        SR[7] = 0;\n                        SR[0] = 0;\n                    end\n                end\n            end\n\n            BEFP_LOAD :\n            begin\n                if (rising_edge_Write)\n                begin\n                    if ((BlockNumber(LatchedAddr) != BEFP_block) &&\n                    (LatchedData == 16'hFFFF))\n                    begin\n                        SR[7] = 1'b1;\n                        SR[0] = 1'b0;\n                    end\n                    else\n                    begin\n                        DataBuff[word_cntr] = LatchedData;\n                        word_cntr = word_cntr + 1;\n                        if (word_cntr == 31)\n                        begin\n                            BEFP_in = 1'b1;\n                            BEFP_in <= #1 1'b0;\n                        end\n                    end\n                end\n            end\n\n            BEFP_BUSY :\n            begin\n\n                if (falling_edge_RSTNeg)\n                begin\n                    for (j = 0 ; j<= 31; j=j+1)\n                        MemData[BEFP_addr+j] = -1;\n                end\n\n                if (falling_edge_BEFP_out)\n                begin\n                    for (j=0;j<=31;j=j+1)\n                    begin\n                        if (MemData[BEFP_addr+j] > -1)\n                        begin\n                            prog_bits = DataBuff[j];\n                            mem_bits  = MemData[BEFP_addr + j];\n                            for (i=0;i<=15;i=i+1)\n                            begin\n                                if (prog_bits[i] == 1'b0)\n                                    mem_bits[i] = 1'b0;\n                            end\n                            MemData[BEFP_addr + j] = mem_bits;\n                        end\n                    end\n                    BEFP_addr = BEFP_addr + 32;\n                    if ((BEFP_addr > MemSize) ||\n                    (BlockNumber(BEFP_addr) > BEFP_block))\n                        BEFP_addr = BEFP_addr - BlockSize(BEFP_block);\n                    SR[0] = 1'b0;\n                    word_cntr = 0;\n                end\n                else\n                    SR[0] = 1'b1;\n            end\n\n        endcase\n    end\n\n    ///////////////////////////////////////////////////////////\n    // Combinatorial output generation\n    ///////////////////////////////////////////////////////////\n    always @(Ahigh_event or Alow_event or rising_edge_Read or\n        A_event or OENeg or falling_edge_Read or CENeg\n        )\n    begin : Output\n        case (read_state)\n            READ_ARRAY :\n            begin\n                if (RCR[15] == 1'b1)\n                begin\n                    if (Ahigh_event && ~ADVNeg)\n                        ReadAddr = A;\n                    else if (Alow_event)\n                        ReadAddr = ReadAddr - (ReadAddr % 4) + A[1:0];\n                end\n\n                if (current_state == PROG_BUSY ||\n                current_state == PROG_BUSY_ERS_SUSP ||\n                current_state == BP_BUSY ||\n                current_state == BP_BUSY_ERS_SUSP ||\n                current_state == ERASE_BUSY)\n                    DQOut_tmp = 16'bx;\n                else\n                begin\n                    if (MemData[ReadAddr] > -1)\n                        DQOut_tmp = MemData[ReadAddr];\n                    else\n                        DQOut_tmp = 16'bx;\n                end\n            end\n\n            READ_ID :\n            begin\n                if ((((ReadAddr-2) % MainBlockSize) == 0) ||\n                ((ReadAddr < MainBlockSize) &&\n                (((ReadAddr-2) % ParameterBlockSize) == 0)))\n                begin\n                    DQOut_tmp[0] = BlockLockBit[BlockNumber(ReadAddr)];\n                    DQOut_tmp[1] = BlockLockDownBit[BlockNumber(ReadAddr)];\n                    DQOut_tmp[15:2] = 14'b0;\n                end\n                else if (ReadAddr == 0)\n                    DQOut_tmp = 16'h0089;\n                else if (ReadAddr == 1)\n                begin\n                    DQOut_tmp = DeviceID_B;\n                end\n                else if (ReadAddr == 5)\n                    DQOut_tmp = RCR;\n                else if ((ReadAddr >= 9'h80) && (ReadAddr <= 9'h109))\n                begin\n                    if (PR[ReadAddr] > -1)\n                        DQOut_tmp = PR[ReadAddr];\n                    else\n                        DQOut_tmp = 16'bx;\n                end\n            end\n\n            READ_QUERY :\n            begin\n                if (((ReadAddr >= 9'h10) && (ReadAddr <= 9'h38)) ||\n                ((ReadAddr >= 9'h10A) && (ReadAddr <= 9'h156)))\n                    DQOut_tmp = CFI_array[ReadAddr];\n                else\n                    DQOut_tmp = 16'b0;\n            end\n\n            READ_STATUS :\n            begin\n                DQOut_tmp[15:8] = 8'b0;\n                DQOut_tmp[7:0] = SR;\n            end\n        endcase\n\n        if (RCR[15] == 1'b1) // Asynchronous read\n        begin\n            if (rising_edge_Read || (Read && ((A_event && ~ADVNeg) ||\n            Alow_event)))\n                DQOut_zd = DQOut_tmp;\n            else if (falling_edge_Read)\n                DQOut_zd = 16'bz;\n        end\n        else // Burst read\n        begin\n            if (rising_edge_Read || falling_edge_Read)\n            begin\n                if ((burst_cntr > BurstLength) && (BurstLength != 0))\n                    read_out = 1'b0;\n                else if (read_state == READ_ARRAY)\n                begin\n                    if ((RCR[9] == 1'b0) && (RCR[13:11] > 4) &&\n                    ((burst_cntr >= 5) || (burst_cntr < 1)))\n                    begin\n                        read_out = 1'b0;\n                        if (burst_cntr >= 5)\n                            burst_cntr = 5 - RCR[13:11];\n                    end\n                    else\n                    begin\n                        read_out = 1'b1;\n                        if (ReadAddr < MemSize)\n                            ReadAddr = ReadAddr + 1;\n                        if ((RCR[3] == 1'b0) && (BurstLength != 0) &&\n                        ((ReadAddr % BurstLength) == 0))\n                            ReadAddr = ReadAddr - BurstLength;\n                    end\n                end\n                else\n                    read_out = 1'b1;\n\n                if (read_out)\n                begin\n                    DQOut_zd = DQOut_tmp;\n                end\n            end\n        end\n    end\n\n    always @(CENeg, OENeg)\n    begin : OutputDisable\n        if ((CENeg) || (OENeg))\n            DQOut_zd = 16'bz;\n        else if ((~CENeg) && (~OENeg) && (RCR[15] == 1'b0))\n            DQOut_zd = 16'bx;\n    end\n\n    ////////////////////////////////////////////////////////////////\n    // WAIT output control process\n    ////////////////////////////////////////////////////////////////\n    always @(AssertWAITOut_event or DeassertWAITOut_event or falling_edge_OENeg\n    or OENeg or CENeg or falling_edge_CENeg)\n    begin : WAITOut_control\n\n        if (OENeg || CENeg || ~RSTNeg || (current_state == RESET_POWER_DOWN))\n            WAITOut_zd = 1'bz;\n        else if ((falling_edge_OENeg && ~CENeg) ||\n        (falling_edge_CENeg && ~OENeg))\n        begin\n            if (RCR[15] == 1'b1)\n            begin\n                if (~RCR[10])\n                    WAITOut_zd = 1'b1;\n                else\n                    WAITOut_zd = 1'b0;\n            end\n            else\n            begin\n                if (~RCR[10])\n                    WAITOut_zd = 1'b0;\n                else\n                    WAITOut_zd = 1'b1;\n            end\n        end\n        else if (AssertWAITOut_event)\n        begin\n            if (~RCR[10])\n                WAITOut_zd = 1'b0;\n            else\n                WAITOut_zd = 1'b1;\n        end\n        else if (DeassertWAITOut_event)\n        begin\n            if (~RCR[10])\n                WAITOut_zd = 1'b1;\n            else\n                WAITOut_zd = 1'b0;\n        end\n    end\n\n    ///////////////////////////////////////////////////////////////////\n    // Timing control for erase start, suspend and resume\n    ///////////////////////////////////////////////////////////////////\n    always @(rising_edge_MainErase_in or rising_edge_ParameterErase_in or\n             RstDuringErsPrg_out_event or\n             abort_event or\n             rising_edge_ParameterEraseResume or EraseSuspend_event or\n             rising_edge_MainEraseResume )\n    begin : erase_time\n        merase_duration = tdevice_EraseMain;\n        perase_duration = tdevice_EraseParameter;\n\n        if (rising_edge_MainErase_in)\n        begin\n            melapsed = 0;\n            MainErase_out <= #1 1'b1;\n            ->merase_event;\n            mstart = $time;\n        end\n        if (rising_edge_ParameterErase_in)\n        begin\n            pelapsed = 0;\n            ParameterErase_out <= #1 1'b1;\n            ->perase_event;\n            pstart = $time;\n        end\n        if ((RstDuringErsPrg_out_event && ~RstDuringErsPrg_out) ||\n        abort_event)\n        begin\n            disable merase_process;\n            disable perase_process;\n            MainErase_out = 1'b0;\n            ParameterErase_out = 1'b0;\n        end\n\n        if (EraseSuspend_event && ~EraseSuspend_out)\n        begin\n            disable merase_process;\n            melapsed = $time - mstart;\n            merase_duration = merase_duration - melapsed;\n            disable perase_process;\n            pelapsed = $time - pstart;\n            perase_duration = perase_duration - pelapsed;\n        end\n        if (rising_edge_MainEraseResume)\n        begin\n            mstart = $time;\n            MainErase_out = 1'b1;\n            -> merase_event;\n        end\n        if (rising_edge_ParameterEraseResume)\n        begin\n            pstart = $time;\n            ParameterErase_out = 1'b1;\n            ->perase_event;\n        end\n    end\n\n    always @(merase_event)\n    begin : merase_process\n        #merase_duration MainErase_out = 1'b0;\n    end\n    always @(perase_event)\n    begin : perase_process\n        #perase_duration ParameterErase_out = 1'b0;\n    end\n\n    /////////////////////////////////////////////////////////////////\n    // Timing control for programming start, suspend and resume\n    /////////////////////////////////////////////////////////////////\n    time buffp_duration;\n    time wordp_duration;\n    time welapsed;\n    time elapsed;\n    event prog_event;\n    event buffp_event;\n    time wstart;\n    time start;\n    reg rising_edge_WordProgram_in = 1'b0;\n    reg rising_edge_BuffProgram_in = 1'b0;\n    reg rising_edge_WordProgramResume = 1'b0;\n    reg rising_edge_BP_ProgramResume = 1'b0;\n\n    always @(rising_edge_WordProgram_in or rising_edge_BuffProgram_in or\n             RstDuringErsPrg_out_event or\n             abort_event or\n             ProgramSuspend_out_event or rising_edge_WordProgramResume or\n             rising_edge_BP_ProgramResume)\n    begin\n        if (VPP_voltage != 9)\n        begin\n            buffp_duration = tdevice_BuffProgram;\n            wordp_duration = tdevice_WordProgram;\n        end\n        else\n        begin\n            buffp_duration = tdevice_BuffProgram9V;\n            wordp_duration = tdevice_WordProgram9V;\n        end\n\n        if (rising_edge_WordProgram_in)\n        begin\n            welapsed = 0;\n            WordProgram_out <= #1 1'b1;\n            -> prog_event;\n            wstart = $time;\n        end\n        if (rising_edge_BuffProgram_in)\n        begin\n            elapsed = 0;\n            BuffProgram_out = 1'b1;\n            -> buffp_event;\n            start = $time;\n        end\n        if ((RstDuringErsPrg_out_event && ~RstDuringErsPrg_out) ||\n        abort_event)\n        begin\n            disable prog_process;\n            disable buffp_process;\n            WordProgram_out = 1'b0;\n            BuffProgram_out = 1'b0;\n        end\n\n        if (ProgramSuspend_out_event && ~ProgramSuspend_out)\n        begin\n            disable prog_process;\n            disable buffp_process;\n            elapsed = $time - start;\n            welapsed = $time - wstart;\n            buffp_duration = buffp_duration - elapsed;\n            wordp_duration = wordp_duration - welapsed;\n        end\n        if (rising_edge_WordProgramResume)\n        begin\n            wstart = $time;\n            WordProgram_out = 1'b1;\n            -> prog_event;\n        end\n        if (rising_edge_BP_ProgramResume)\n        begin\n            start = $time;\n            BuffProgram_out = 1'b1;\n            -> buffp_event;\n        end\n    end\n\n    always @(prog_event)\n    begin : prog_process\n        #wordp_duration WordProgram_out = 1'b0;\n    end\n    always @(buffp_event)\n    begin : buffp_process\n        #buffp_duration BuffProgram_out = 1'b0;\n    end\n\n    ////////////////////////////////////////////////////////////////////\n    //Output timing control\n    ////////////////////////////////////////////////////////////////////\n    always @(DQOut_zd)\n    begin : OutputGen\n        if (DQOut_zd[0] !== 1'bz)\n        begin\n            CEDQ_t = CENeg_event  + CEDQ_01;\n            OEDQ_t = OENeg_event  + OEDQ_01;\n            ADDRDQ_t = ADDR_event + ADDRDQIN_01;\n            if (Pmode)\n                ADDRDQ_t = ADDR_event + ADDRDQPAGE_01;\n\n            FROMCE = ((CEDQ_t >= OEDQ_t) && (CEDQ_t >= $time));\n            FROMOE = ((OEDQ_t >= CEDQ_t) && (OEDQ_t >= $time));\n            FROMADDR = 1'b1;\n\n            DQOut_Pass = DQOut_zd;\n        end\n    end\n\n    always @(DQOut_zd)\n    begin\n        if (DQOut_zd[0] === 1'bz)\n        begin\n            disable OutputGen;\n            FROMCE = 1'b1;\n            FROMOE = 1'b1;\n            FROMADDR = 1'b0;\n            DQOut_Pass = DQOut_zd;\n        end\n    end\n\n    reg  BuffInOE, BuffInCE, BuffInADDRIN, BuffInADDRPAGE;\n    wire BuffOutOE, BuffOutCE, BuffOutADDRIN, BuffOutADDRPAGE;\n\n    BUFFER    BUFOE   (BuffOutOE, BuffInOE);\n    BUFFER    BUFCE   (BuffOutCE, BuffInCE);\n    BUFFER    BUFADDRIN (BuffOutADDRIN, BuffInADDRIN);\n    BUFFER    BUFADDRPAGE (BuffOutADDRPAGE, BuffInADDRPAGE);\n\n    initial\n    begin\n        BuffInOE   = 1'b1;\n        BuffInCE   = 1'b1;\n        BuffInADDRIN = 1'b1;\n        BuffInADDRPAGE = 1'b1;\n    end\n\n    always @(posedge BuffOutOE)\n    begin\n        OEDQ_01 = $time;\n    end\n    always @(posedge BuffOutCE)\n    begin\n        CEDQ_01 = $time;\n    end\n    always @(posedge BuffOutADDRIN)\n    begin\n        ADDRDQIN_01 = $time;\n    end\n    always @(posedge BuffOutADDRPAGE)\n    begin\n        ADDRDQPAGE_01 = $time;\n    end\n\n/////////////////////////////////////////////////////////////////////////////\n// functions & tasks\n/////////////////////////////////////////////////////////////////////////////\n    function integer BlockNumber;\n        input [HiAddrBit:0] ADDR;\n        integer block_number;\n    begin\n        block_number = ADDR / MainBlockSize;\n        if (block_number == 0)\n            block_number = block_number +\n                (ADDR % MainBlockSize) / ParameterBlockSize;\n        else\n            block_number = block_number +\n                MainBlockSize / ParameterBlockSize - 1;\n        BlockNumber = block_number;\n    end\n    endfunction\n\n    function integer StartBlockAddr;\n        input [16:0] block_number;\n        integer start_block_addr;\n    begin\n        if (block_number < 4)\n            start_block_addr = block_number * ParameterBlockSize;\n        else\n            start_block_addr = (block_number - 3) * MainBlockSize;\n        StartBlockAddr = start_block_addr;\n    end\n    endfunction\n\n    function integer BlockSize;\n        input [16:0] block_number;\n        integer block_number;\n        integer block_size;\n    begin\n        if ((block_number < 4) ||\n        (block_number > (BlockNum - 4) ))\n            block_size = ParameterBlockSize;\n        else\n            block_size = MainBlockSize;\n        BlockSize = block_size;\n    end\n    endfunction\n\n    ////////////////////////////////////////////////////////////////\n    // edge controll processes\n    ////////////////////////////////////////////////////////////////\n    always @(negedge ADVNeg)\n    begin\n        falling_edge_ADVNeg = 1;\n        #1 falling_edge_ADVNeg = 0;\n    end\n\n    always @(posedge ADVNeg)\n    begin\n        rising_edge_ADVNeg  = 1;\n        #1 rising_edge_ADVNeg = 0;\n    end\n\n    always @(posedge CLOCK)\n    begin\n        rising_edge_CLOCK = 1;\n        #1 rising_edge_CLOCK = 0;\n    end\n\n    always @(negedge RSTNeg)\n    begin\n        falling_edge_RSTNeg = 1;\n        #1 falling_edge_RSTNeg = 0;\n    end\n\n    always @(posedge RSTNeg)\n    begin\n        rising_edge_RSTNeg = 1;\n        #1 rising_edge_RSTNeg = 0;\n    end\n\n    always @(posedge Write)\n    begin\n        rising_edge_Write = 1;\n        #1 rising_edge_Write = 0;\n    end\n\n    always @(RstDuringErsPrg_out)\n    begin\n        RstDuringErsPrg_out_event = 1;\n        #1 RstDuringErsPrg_out_event = 0;\n    end\n\n    always @(WordProgram_out)\n    begin\n        WordProgram_out_event = 1;\n        #1 WordProgram_out_event = 0;\n    end\n\n    always @(ProgramSuspend_out)\n    begin\n        ProgramSuspend_out_event = 1;\n        #1 ProgramSuspend_out_event = 0;\n    end\n\n    always @(BuffProgram_out)\n    begin\n        if (~suspended_bp)\n        begin\n            BuffProgram_out_event = 1;\n            #1 BuffProgram_out_event = 0;\n        end\n    end\n\n    always @(posedge ExtendProgTime)\n    begin\n        ExtendProgTime_event = 1;\n        #1 ExtendProgTime_event = 0;\n    end\n\n    always @(ParameterErase_out)\n    begin\n        ParameterErase_out_event = 1;\n        #1 ParameterErase_out_event = 0;\n    end\n\n    always @(negedge MainErase_out)\n    begin\n        falling_edge_MainErase_out = 1;\n        #1 falling_edge_MainErase_out = 0;\n    end\n\n    always @(negedge EraseSuspend_out)\n    begin\n        falling_edge_EraseSuspend_out = 1;\n        #1 falling_edge_EraseSuspend_out = 0;\n    end\n\n    always @(negedge BEFPsetup_out)\n    begin\n        falling_edge_BEFPsetup_out = 1;\n        #1 falling_edge_BEFPsetup_out = 0;\n    end\n\n    always @(negedge BEFP_out)\n    begin\n        falling_edge_BEFP_out = 1;\n        #1 falling_edge_BEFP_out = 0;\n    end\n\n    always @(A[HiAddrBit:2])\n    begin\n        Ahigh_event = 1;\n        #1 Ahigh_event = 0;\n    end\n\n    always @(A[1:0])\n    begin\n        Alow_event = 1;\n        #1 Alow_event = 0;\n    end\n\n    always @(A)\n    begin\n        A_event = 1;\n        #1 A_event = 0;\n    end\n\n    always @(posedge Read)\n    begin\n        rising_edge_Read = 1;\n        #1 rising_edge_Read = 0;\n    end\n\n    always @(negedge Read)\n    begin\n        falling_edge_Read = 1;\n        #1 falling_edge_Read = 0;\n    end\n\n    always @(posedge CENeg)\n    begin\n        rising_edge_CENeg = 1;\n        #1 rising_edge_CENeg = 0;\n    end\n\n    always @(posedge OENeg)\n    begin\n        rising_edge_OENeg = 1;\n        #1 rising_edge_OENeg = 0;\n    end\n\n    always @(AssertWAITOut)\n    begin\n        AssertWAITOut_event = 1;\n        #1 AssertWAITOut_event = 0;\n    end\n\n    always @(DeassertWAITOut)\n    begin\n        DeassertWAITOut_event = 1;\n        #1 DeassertWAITOut_event = 0;\n    end\n\n    always @(negedge OENeg)\n    begin\n        falling_edge_OENeg = 1;\n        #1 falling_edge_OENeg = 0;\n    end\n\n    always @(negedge CENeg)\n    begin\n        falling_edge_CENeg = 1;\n        #1 falling_edge_CENeg = 0;\n    end\n\n    always @(posedge WENeg)\n    begin\n        rising_edge_WENeg = 1;\n        #1 rising_edge_WENeg = 0;\n    end\n\n    always @(posedge WordProgram_in)\n    begin\n        rising_edge_WordProgram_in = 1'b1;\n        #1 rising_edge_WordProgram_in = 1'b0;\n    end\n\n    always @(posedge BuffProgram_in)\n    begin\n        rising_edge_BuffProgram_in = 1'b1;\n        #1 rising_edge_BuffProgram_in = 1'b0;\n    end\n\n    always @(posedge BP_ProgramResume)\n    begin\n        rising_edge_BP_ProgramResume = 1'b1;\n        #1 rising_edge_BP_ProgramResume = 1'b0;\n    end\n    always @(posedge WordProgramResume)\n    begin\n        rising_edge_WordProgramResume = 1'b1;\n        #1 rising_edge_WordProgramResume = 1'b0;\n    end\n\n    always @(posedge MainErase_in)\n    begin\n        rising_edge_MainErase_in = 1'b1;\n        #1 rising_edge_MainErase_in = 1'b0;\n    end\n\n    always @(posedge ParameterErase_in)\n    begin\n        rising_edge_ParameterErase_in = 1'b1;\n        #1 rising_edge_ParameterErase_in = 1'b0;\n    end\n\n    always @(posedge MainEraseResume)\n    begin\n        rising_edge_MainEraseResume = 1'b1;\n        #1 rising_edge_MainEraseResume = 1'b0;\n    end\n\n    always @(posedge ParameterEraseResume)\n    begin\n        rising_edge_ParameterEraseResume = 1'b1;\n        #1 rising_edge_ParameterEraseResume = 1'b0;\n    end\n\n    always @(EraseSuspend_out)\n    begin\n        EraseSuspend_event = 1'b1;\n        #1 EraseSuspend_event = 1'b0;\n    end\n\nendmodule\n\nmodule BUFFER (OUT,IN);\n    input IN;\n    output OUT;\n    buf   (OUT, IN);\nendmodule\n"
  },
  {
    "path": "tests/bpiflash/testbpiflash.cpp",
    "content": "\n#include <BpiFlashTestIndication.h>\n#include <BpiFlashTestRequest.h>\n#include \"bpiflash.h\"\n\nclass BpiFlashTestIndication : public BpiFlashTestIndicationWrapper\n{\n  sem_t sem;\npublic:\n    unsigned short buf[16];\n    virtual void resetDone() {\n\tfprintf(stderr, \"reset done\\n\");\n\tsem_post(&sem);\n    }\n    virtual void readDone(uint16_t v) {\n      //fprintf(stderr, \"read %x\\n\", v);\n\tbuf[0] = v;\n\tsem_post(&sem);\n    }\n    virtual void writeDone() {\n      //fprintf(stderr, \"write done\\n\");\n\tsem_post(&sem);\n    }\n    void wait() {\n\tsem_wait(&sem);\n    }\n    BpiFlashTestIndication(unsigned int id) : BpiFlashTestIndicationWrapper(id) {\n      sem_init(&sem, 0, 0);\n    }\n};\n\n\nBpiFlashTestRequestProxy *request;\nBpiFlashTestIndication *indication;\n\n#ifdef STANDALONE\nint main(int argc, const char **argv)\n{\n    request = new BpiFlashTestRequestProxy(IfcNames_BpiFlashTestRequestS2H);\n    indication = new BpiFlashTestIndication(IfcNames_BpiFlashTestIndicationH2S);\n    request->reset();\n    indication->wait();\n    for (int i = 0; i < 20; i++) {\n      request->read(i<<1);\n      indication->wait();\n    }\n    return 0;\n}\n#else\n\nBpiFlash::BpiFlash()\n    : request(0), indication(0), didReset(false)\n{\n    request = new BpiFlashTestRequestProxy(IfcNames_BpiFlashTestRequestS2H);\n    indication = new BpiFlashTestIndication(IfcNames_BpiFlashTestIndicationH2S);\n}\n\nBpiFlash::~BpiFlash()\n{\n  //delete request;\n  //delete indication;\n  request = 0;\n  indication = 0;\n}\n\nvoid BpiFlash::maybeReset()\n{\n    if (!didReset) {\n\tfprintf(stderr, \"resetting flash\\n\");\n\trequest->reset();\n\tindication->wait();\n\trequest->setParameters(50, 0);\n\tfprintf(stderr, \"done resetting flash\\n\");\n\tdidReset = true;\n    }\n}\n\nint verbose = 0;\n\nvoid BpiFlash::read(unsigned long offset, uint8_t *buf)\n{\n    maybeReset();\n\n    //fprintf(stderr, \"BpiFlash::read offset=%lx\\n\", offset);\n    request->read(offset);\n    indication->wait();\n    if (verbose) fprintf(stderr, \"BpiFlash::read offset=%lx value=%x\\n\", offset, *(short *)indication->buf);\n    memcpy(buf, indication->buf, 2);\n}\n\nvoid BpiFlash::write(unsigned long offset, const uint8_t *buf)\n{\n    maybeReset();\n\n    if (verbose) fprintf(stderr, \"BpiFlash::write offset=%lx value=%x\\n\", offset, *(short *)buf);\n    request->write(offset, *(uint16_t *)buf);\n    indication->wait();\n}\n#endif\n\n"
  },
  {
    "path": "tests/ddr3/Ddr3Test.bsv",
    "content": "// Copyright (c) 2013 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\nimport Clocks::*;\nimport Vector::*;\nimport BuildVector::*;\nimport GetPut::*;\nimport Connectable::*;\nimport ClientServer::*;\nimport ConnectalMemory::*;\nimport ConnectalBramFifo::*;\nimport FIFOF::*;\nimport Gearbox::*;\nimport GearboxGetPut::*;\nimport ConnectalMemTypes::*;\nimport MemReadEngine::*;\nimport MemWriteEngine::*;\nimport Pipe::*;\nimport AxiDdr3Controller::*;\nimport GetPutWithClocks::*;\nimport AxiMasterSlave::*;\nimport Axi4MasterSlave::*;\nimport AxiDdr3Wrapper  ::*;\nimport AxiDma::*;\nimport ConnectalConfig::*;\nimport HostInterface::*;\nimport Probe::*;\n\ninterface Ddr3TestRequest;\n   method Action startWriteDram(Bit#(32) sglId, Bit#(32) transferBytes);\n   method Action startReadDram(Bit#(32) sglId, Bit#(32) transferBytes);\nendinterface\n\ninterface Ddr3TestIndication;\n   method Action writeDone(Bit#(32) v);\n   method Action readDone(Bit#(32) v);\nendinterface\n\ninterface Ddr3Test;\n   interface Ddr3TestRequest request;\n   interface Vector#(1, MemReadClient#(DataBusWidth)) readClient;\n   interface Vector#(1, MemWriteClient#(DataBusWidth)) writeClient;\n   interface Ddr3Pins ddr3;\nendinterface\n\ntypedef TDiv#(Ddr3DataWidth,DataBusWidth) BusRatio;\ntypedef TDiv#(Ddr3DataWidth,8) Ddr3DataBytes;\n\nmodule mkDdr3Test#(HostInterface host, Ddr3TestIndication indication)(Ddr3Test);\n\n   let clock <- exposeCurrentClock();\n   let reset <- exposeCurrentReset();\n\n   Reg#(Bit#(Ddr3AddrWidth)) transferLen <- mkReg(256);\n\n   Clock clk200 = host.tsys_clk_200mhz_buf;\n\n   let ddr3Controller <- mkDdr3(clk200);\n   MemReadEngine#(DataBusWidth,DataBusWidth,1,1)  re <- mkMemReadEngine();\n   MemWriteEngine#(DataBusWidth,DataBusWidth,1,1)  we <- mkMemWriteEngine();\n\n   FIFOF#(Bit#(32))   writeReqFifo <- mkFIFOF();\n   FIFOF#(Bit#(32))   readReqFifo <- mkFIFOF();\n\n   Probe#(Bit#(Ddr3AddrWidth)) aw_req_probe <- mkProbe();\n   Reg#(Bit#(Ddr3AddrWidth)) dramWriteLimitProbe <- mkReg(0);\n   Reg#(Bit#(Ddr3AddrWidth)) dramReadLimitProbe <- mkReg(0);\n\n   Probe#(Bit#(Ddr3AddrWidth)) awAddrProbe <- mkProbe(clocked_by ddr3Controller.uiClock, reset_by ddr3Controller.uiReset);\n   Probe#(Bit#(8)) awLenProbe <- mkProbe(clocked_by ddr3Controller.uiClock, reset_by ddr3Controller.uiReset);\n   Probe#(Bit#(3)) awSizeProbe <- mkProbe(clocked_by ddr3Controller.uiClock, reset_by ddr3Controller.uiReset);\n   Probe#(Vector#(BusRatio,Bit#(DataBusWidth))) wdataProbe <- mkProbe(clocked_by ddr3Controller.uiClock, reset_by ddr3Controller.uiReset);\n   Probe#(Axi4WriteResponse#(6)) bProbe <- mkProbe(clocked_by ddr3Controller.uiClock, reset_by ddr3Controller.uiReset);\n   Probe#(Bit#(Ddr3AddrWidth)) arAddrProbe <- mkProbe(clocked_by ddr3Controller.uiClock, reset_by ddr3Controller.uiReset);\n   Probe#(Bit#(8)) arLenProbe <- mkProbe(clocked_by ddr3Controller.uiClock, reset_by ddr3Controller.uiReset);\n   Probe#(Bit#(3)) arSizeProbe <- mkProbe(clocked_by ddr3Controller.uiClock, reset_by ddr3Controller.uiReset);\n   Probe#(Vector#(BusRatio,Bit#(DataBusWidth))) rdataProbe <- mkProbe(clocked_by ddr3Controller.uiClock, reset_by ddr3Controller.uiReset);\n   let sglWriteProbe <- mkProbe();\n   let sglReadProbe <- mkProbe();\n\n   Gearbox#(1,BusRatio,Bit#(DataBusWidth)) dramWriteGearbox <- mk1toNGearbox(clock, reset, clock, reset);\n   FIFOF#(Vector#(BusRatio,Bit#(DataBusWidth))) dramWriteFifo <- mkDualClockBramFIFOF(clock, reset, ddr3Controller.uiClock, ddr3Controller.uiReset);\n   FIFOF#(Axi4WriteRequest#(Ddr3AddrWidth,6)) awfifo <- mkDualClockBramFIFOF(clock, reset, ddr3Controller.uiClock, ddr3Controller.uiReset);\n   FIFOF#(Axi4WriteResponse#(6)) bfifo <- mkDualClockBramFIFOF(ddr3Controller.uiClock, ddr3Controller.uiReset, clock, reset);\n   //mkConnection(toGet(awfifo), ddr3Controller.slave.req_aw);\n   //mkConnection(ddr3Controller.slave.resp_b, toPut(bfifo));\n   rule rl_awfifo;\n      let req <- toGet(awfifo).get();\n      awAddrProbe <= req.address;\n      awLenProbe <= req.len;\n      awSizeProbe <= req.size;\n      ddr3Controller.slave.req_aw.put(req);\n   endrule\n   rule rl_bfifo;\n      let b <- ddr3Controller.slave.resp_b.get();\n      bProbe <= b;\n      bfifo.enq(b);\n   endrule\n\n   Reg#(Bit#(Ddr3AddrWidth)) dramWriteOffset <- mkReg(0);\n   Reg#(Bit#(Ddr3AddrWidth)) dramWriteLimit <- mkReg(0);\n   rule rl_req_aw if (dramWriteOffset < dramWriteLimit);\n      Axi4WriteRequest#(Ddr3AddrWidth,6) req = Axi4WriteRequest {\n\t address: truncate(dramWriteOffset),\n\t len: 0, // indicates 1 beat of data\n\t size: axiBusSize(valueOf(Ddr3DataWidth)),\n\t id: 0,\n\t burst: 2'b01,\n\t prot: 3'b000,   //ignored\n\t cache: 4'b0011, //ignored\n\t lock: 2'b00,    //ignored\n\t qos: 4'b0000    //ignored\n\t };\n      awfifo.enq(req);\n      aw_req_probe <= req.address;\n      dramWriteOffset <= dramWriteOffset + fromInteger(valueOf(Ddr3DataBytes));\n   endrule\n\n   rule rl_wdata_gb;\n      let rdata <- toGet(re.readServers[0].data).get();\n      dramWriteGearbox.enq(vec(rdata.data));\n   endrule\n   rule rl_wdata;\n      let mds <- toGet(dramWriteGearbox).get();\n      dramWriteFifo.enq(mds);\n   endrule\n   rule rl_writeDataFifo;\n      let mds <- toGet(dramWriteFifo).get();\n      wdataProbe <= mds;\n      ddr3Controller.slave.resp_write.put(Axi4WriteData {\n\t data: pack(mds),\n\t byteEnable: maxBound,\n\t last: 1,\n\t id: 0\n\t });\n   endrule\n\n   rule rl_b;\n      // consume the writeDone\n      let b <- toGet(bfifo).get();\n      // let's see an indication, but we should be counting how many words were sent\n      indication.writeDone(extend(b.id));\n   endrule\n\n   rule rl_write_start;\n      let sglId <- toGet(writeReqFifo).get();\n      dramWriteOffset <= 0;\n      dramWriteLimit <= transferLen;\n      dramWriteLimitProbe <= transferLen;\n      re.readServers[0].request.put(MemengineCmd { sglId: sglId,\n\t\t\t\t\t\t  base: 0,\n\t\t\t\t\t\t  burstLen: 128,\n\t\t\t\t\t\t  len: extend(transferLen),\n\t\t\t\t\t\t  tag: 0\n\t\t\t\t\t\t  });\n   endrule\n\n   Gearbox#(BusRatio,1,Bit#(DataBusWidth)) dramReadGearbox <- mkNto1Gearbox(ddr3Controller.uiClock, ddr3Controller.uiReset, ddr3Controller.uiClock, ddr3Controller.uiReset);\n   FIFOF#(Bit#(DataBusWidth)) dramReadFifo <- mkDualClockBramFIFOF(ddr3Controller.uiClock, ddr3Controller.uiReset, clock, reset);\n   FIFOF#(Axi4ReadRequest#(Ddr3AddrWidth,6)) arfifo <- mkDualClockBramFIFOF(clock, reset, ddr3Controller.uiClock, ddr3Controller.uiReset);\n   //mkConnection(toGet(arfifo), ddr3Controller.slave.req_ar);\n   rule rl_arfifo;\n      let req <- toGet(arfifo).get();\n      arAddrProbe <= req.address;\n      arLenProbe <= req.len;\n      arSizeProbe <= req.size;\n      ddr3Controller.slave.req_ar.put(req);\n   endrule\n\n   Reg#(Bit#(Ddr3AddrWidth)) dramReadOffset <- mkReg(0);\n   Reg#(Bit#(Ddr3AddrWidth)) dramReadLimit <- mkReg(0);\n   rule rl_req_ar if (dramReadOffset < dramReadLimit);\n      Axi4ReadRequest#(Ddr3AddrWidth,6) req = Axi4ReadRequest {\n\t address: truncate(dramReadOffset),\n\t len: 0, // indicates one beat of data\n\t size: axiBusSize(valueOf(Ddr3DataWidth)),\n\t id: 0,\n\t burst: 2'b01,\n\t prot: 3'b000,   //ignored\n\t cache: 4'b0011, //ignored\n\t lock: 2'b00,    //ignored\n\t qos: 4'b0000    //ignored\n\t };\n      arfifo.enq(req);\n      dramReadOffset <= dramReadOffset + fromInteger(valueOf(Ddr3DataBytes));\n   endrule\n\n   rule rl_rdata;\n      let resp <- ddr3Controller.slave.resp_read.get();\n      Vector#(BusRatio, Bit#(DataBusWidth)) data = unpack(resp.data);\n      rdataProbe <= data;\n      dramReadGearbox.enq(data);\n   endrule\n   rule rl_rdata_gb;\n      Bit#(DataBusWidth) rdata <- toGet(dramReadGearbox).get();\n      dramReadFifo.enq(rdata);\n   endrule\n   rule rl_rdata_slack;\n      let rdata <- toGet(dramReadFifo).get();\n      //fixme last field\n      we.writeServers[0].data.enq(rdata);\n   endrule\n\n   rule rl_read_start;\n      let sglId <- toGet(readReqFifo).get();\n      dramReadOffset <= 0;\n      dramReadLimit <= transferLen;\n      dramReadLimitProbe <= transferLen;\n      we.writeServers[0].request.put(MemengineCmd { sglId: sglId,\n\t\t\t\t\t\t   base: 0,\n\t\t\t\t\t\t   burstLen: 128,\n\t\t\t\t\t\t   len: extend(transferLen),\n\t\t\t\t\t\t   tag: 0\n\t\t\t\t\t\t   });\n   endrule\n\n   rule rl_read_done;\n      let done <- we.writeServers[0].done.get();\n      indication.readDone(0);\n   endrule\n\n   interface Ddr3TestRequest request;\n      method Action startWriteDram(Bit#(32) sglId, Bit#(32) transferBytes);\n\t sglWriteProbe <= sglId;\n\t transferLen <= truncate(transferBytes);\n\t writeReqFifo.enq(sglId);\n      endmethod\n      method Action startReadDram(Bit#(32) sglId, Bit#(32) transferBytes);\n\t sglReadProbe <= sglId;\n\t transferLen <= truncate(transferBytes);\n\t readReqFifo.enq(sglId);\n      endmethod\n   endinterface\n   interface MemReadClient readClient = vec(re.dmaClient);\n   interface MemWriteClient writeClient = vec(we.dmaClient);\n   interface AxiDdr3 ddr3 = ddr3Controller.ddr3;\nendmodule\n"
  },
  {
    "path": "tests/ddr3/Makefile",
    "content": "CONNECTALDIR?=../..\nS2H_INTERFACES = Ddr3TestRequest:Ddr3Test.request\nH2S_INTERFACES = Ddr3Test:Ddr3TestIndication:host\nMEM_READ_INTERFACES = lDdr3Test.readClient\nMEM_WRITE_INTERFACES = lDdr3Test.writeClient\n\nifneq ($(BOARD),zc706)\nifneq ($(BOARD),miniitx100)\nCONNECTALFLAGS += -D DataBusWidth=128\nendif\nendif\nCONNECTALFLAGS += -D IMPORT_HOSTIF -D XILINX_SYS_CLK\nCONNECTALFLAGS += --xci=$(IPDIR)/$(BOARD)/axiddr3/axiddr3.xci\n\nBSVFILES = Ddr3Test.bsv\nCPPFILES=testddr3.cpp\n\nPIN_TYPE = Ddr3Pins\nPIN_TYPE_INCLUDE = AxiDdr3Controller\nAUTOTOP = --interface pins:Ddr3Test.ddr3\n\ninclude $(CONNECTALDIR)/Makefile.connectal\n"
  },
  {
    "path": "tests/ddr3/synth-ip.tcl",
    "content": "source board.tcl\nsource $connectaldir/scripts/connectal-synth-axiddr3.tcl\n"
  },
  {
    "path": "tests/ddr3/testddr3.cpp",
    "content": "/* Copyright (c) 2013 Quanta Research Cambridge, Inc\n *\n * Permission is hereby granted, free of charge, to any person obtaining a\n * copy of this software and associated documentation files (the \"Software\"),\n * to deal in the Software without restriction, including without limitation\n * the rights to use, copy, modify, merge, publish, distribute, sublicense,\n * and/or sell copies of the Software, and to permit persons to whom the\n * Software is furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n * DEALINGS IN THE SOFTWARE.\n */\n#include \"dmaManager.h\"\n#include \"Ddr3TestIndication.h\"\n#include \"Ddr3TestRequest.h\"\n\nsem_t write_sem;\nsem_t read_sem;\nunsigned int alloc_sz = 1<<10;\n\nclass Ddr3TestIndication : public Ddr3TestIndicationWrapper\n{\npublic:\n  Ddr3TestIndication(unsigned int id) : Ddr3TestIndicationWrapper(id){}\n  virtual void writeDone(uint32_t v) {\n    fprintf(stderr, \"writeDone %d\\n\", v);\n    sem_post(&write_sem);\n  }\n  virtual void readDone(uint32_t v) {\n    fprintf(stderr, \"readDone %d\\n\", v);\n    sem_post(&read_sem);\n  }\n};\n\nint main(int argc, const char **argv)\n{\n  DmaManager *dma = platformInit();\n  Ddr3TestRequestProxy *testRequest = new Ddr3TestRequestProxy(IfcNames_Ddr3TestRequestS2H);\n  Ddr3TestIndication testIndication(IfcNames_Ddr3TestIndicationH2S);\n\n  if(sem_init(&write_sem, 1, 0)){\n    fprintf(stderr, \"failed to init write_sem\\n\");\n    return -1;\n  }\n  if(sem_init(&read_sem, 1, 0)){\n    fprintf(stderr, \"failed to init read_sem\\n\");\n    return -1;\n  }\n  int srcAlloc = portalAlloc(alloc_sz, 0);\n  int dstAlloc = portalAlloc(alloc_sz, 0);\n  int *srcBuffer = (int *)portalMmap(srcAlloc, alloc_sz);\n  int *dstBuffer = (int *)portalMmap(dstAlloc, alloc_sz);\n  for (int i = 0; i < 1024/4; i++) {\n      srcBuffer[i] = i;\n      fprintf(stderr, \"src dram[%04x]=%08x\\n\", i*4, srcBuffer[i]);\n  }\n  int ref_srcAlloc = dma->reference(srcAlloc);\n  int ref_dstAlloc = dma->reference(dstAlloc);\n\n  if (1) {\n      int transferLen = 1024;\n      testRequest->startWriteDram(ref_srcAlloc, transferLen);\n      fprintf(stderr, \"Started writing dram\\n\");\n      for (int i = 0; i < transferLen; i += DataBusWidth)\n\t  sem_wait(&write_sem);\n\n      testRequest->startReadDram(ref_dstAlloc, transferLen);\n      sem_wait(&read_sem);\n  }\n  for (int i = 0; i < 1024/4; i++) {\n      fprintf(stderr, \"dst dram[%04x]=%08x\\n\", i*4, dstBuffer[i]);\n  }\n  int mismatches = 0;\n  for (int i = 0; i < 1024/4; i++) {\n      if (i != dstBuffer[i]) {\n\t  mismatches++;\n\t  fprintf(stderr, \"mismatch dram[%04x]=%08x expected %08x\\n\", i*4, dstBuffer[i], i);\n      }\n  }\n  fprintf(stderr, \"%d mismatches\\n\", mismatches);\n  return mismatches ? 1 : 0;\n}\n"
  },
  {
    "path": "tests/ddr3_altera/Ddr3Test.bsv",
    "content": "// Copyright (c) 2013 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n`include \"ConnectalProjectConfig.bsv\"\nimport Clocks::*;\nimport Vector::*;\nimport BuildVector::*;\nimport GetPut::*;\nimport Connectable::*;\nimport ClientServer::*;\nimport ConnectalMemory::*;\nimport FIFOF::*;\nimport Gearbox::*;\nimport GearboxGetPut::*;\nimport ConnectalMemTypes::*;\nimport MemReadEngine::*;\nimport MemWriteEngine::*;\nimport Pipe::*;\nimport AvalonDdr3Controller::*;\nimport GetPutWithClocks::*;\nimport AxiMasterSlave::*;\nimport Axi4MasterSlave::*;\nimport ALTERA_DDR3_WRAPPER::*;\nimport AxiDma::*;\nimport ConnectalConfig::*;\nimport ConnectalClocks::*;\nimport HostInterface::*;\n\ninterface Ddr3TestRequest;\n   method Action startWriteDram(Bit#(32) sglId);\n   method Action startReadDram(Bit#(32) sglId);\nendinterface\n\ninterface Ddr3TestIndication;\n   method Action writeDone(Bit#(32) v);\n   method Action readDone(Bit#(32) v);\nendinterface\n\ninterface Ddr3Test;\n   interface Ddr3TestRequest request;\n   interface Vector#(1, MemReadClient#(DataBusWidth)) readClient;\n   interface Vector#(1, MemWriteClient#(DataBusWidth)) writeClient;\n   interface Ddr3Pins pins;\nendinterface\n\ntypedef TDiv#(Ddr3DataWidth,DataBusWidth) BusRatio;\n\nmodule mkDdr3Test#(HostInterface host, Ddr3TestIndication indication)(Ddr3Test);\n\n   let clock <- exposeCurrentClock();\n   let reset <- exposeCurrentReset();\n\n   B2C1 iclock_50 <- mkB2C1();\n\n   let ddr3Controller <- mkDdr3(iclock_50.c);\n//   MemReadEngine#(DataBusWidth,DataBusWidth,1,1)  re <- mkMemReadEngine();\n//   MemWriteEngine#(DataBusWidth,DataBusWidth,1,1)  ddr3we <- mkMemWriteEngine();\n//   MemWriteEngine#(DataBusWidth,DataBusWidth,1,1)  we <- mkMemWriteEngine();\n//   MemReadEngine#(DataBusWidth,DataBusWidth,1,1)  ddr3re <- mkMemReadEngine();\n//\n//   FIFOF#(Bit#(32))   writeReqFifo <- mkFIFOF();\n//   FIFOF#(Bit#(32))   readReqFifo <- mkFIFOF();\n//\n//   Gearbox#(1,BusRatio,MemData#(DataBusWidth)) dramWriteGearbox <- mk1toNGearbox(clock, reset, ddr3Controller.uiClock, ddr3Controller.uiReset);\n//   SyncFIFOIfc#(Axi4WriteRequest#(Ddr3AddrWidth,6)) awfifo <- mkSyncFIFO(4, clock, reset, ddr3Controller.uiClock);\n//   SyncFIFOIfc#(Axi4WriteResponse#(6)) bfifo <- mkSyncFIFO(4, ddr3Controller.uiClock, ddr3Controller.uiReset, clock);\n//   mkConnection(toGet(awfifo), ddr3Controller.slave.req_aw);\n//   mkConnection(ddr3Controller.slave.resp_b, toPut(bfifo));\n//\n//   rule rl_req_aw;\n//      let req <- ddr3we.dmaClient.writeReq.get();\n//      awfifo.enq(Axi4WriteRequest {\n//\t address: truncate(req.offset),\n//\t len: 1,\n//\t size: axiBusSize(valueOf(Ddr3DataWidth)),\n//\t id: req.tag,\n//\t burst: 2'b01,\n//\t prot: 3'b000,   //ignored\n//\t cache: 4'b0011, //ignored\n//\t lock: 2'b00,    //ignored\n//\t qos: 4'b0000    //ignored\n//\t });\n//   endrule\n//\n//   mkConnection(ddr3we.dmaClient.writeData, toPut(dramWriteGearbox));\n//   rule rl_wdata;\n//      let mds <- toGet(dramWriteGearbox).get();\n//      function Bit#(DataBusWidth) md_data(Integer i); return mds[i].data; endfunction\n//      Vector#(BusRatio, Bit#(DataBusWidth)) data = genWith(md_data);\n//      ddr3Controller.slave.resp_write.put(Axi4WriteData {\n//\t data: pack(data),\n//\t byteEnable: maxBound,\n//\t last: 1,\n//\t id: mds[0].tag\n//\t });\n//   endrule\n//\n//   rule rl_b;\n//      let b <- toGet(bfifo).get();\n//      ddr3we.dmaClient.writeDone.put(b.id);\n//   endrule\n//\n//   rule rl_write_start;\n//      let sglId <- toGet(writeReqFifo).get();\n//      re.readServers[0].request.put(MemengineCmd { sglId: sglId,\n//\t\t\t\t\t\t  base: 0,\n//\t\t\t\t\t\t  burstLen: fromInteger(valueOf(TDiv#(Ddr3DataWidth,8))),\n//\t\t\t\t\t\t  len: 1024,\n//\t\t\t\t\t\t  tag: 0\n//\t\t\t\t\t\t  });\n//      ddr3we.writeServers[0].request.put(MemengineCmd { sglId: 0,\n//\t\t\t\t\t\t       base: 0,\n//\t\t\t\t\t\t       burstLen: fromInteger(valueOf(TDiv#(Ddr3DataWidth,8))),\n//\t\t\t\t\t\t       len: 1024,\n//\t\t\t\t\t\t       tag: 0\n//\t\t\t\t\t\t       });\n//   endrule\n//\n//   Gearbox#(BusRatio,1,MemData#(DataBusWidth)) dramReadGearbox <- mkNto1Gearbox(ddr3Controller.uiClock, ddr3Controller.uiReset, clock, reset);\n//   SyncFIFOIfc#(Axi4ReadRequest#(Ddr3AddrWidth,6)) arfifo <- mkSyncFIFO(4, clock, reset, ddr3Controller.uiClock);\n//   mkConnection(toGet(arfifo), ddr3Controller.slave.req_ar);\n//\n//   rule rl_req_ar;\n//      let req <- ddr3re.dmaClient.readReq.get();\n//      arfifo.enq(Axi4ReadRequest {\n//\t address: truncate(req.offset),\n//\t len: 1,\n//\t size: axiBusSize(valueOf(Ddr3DataWidth)),\n//\t id: req.tag,\n//\t burst: 2'b01,\n//\t prot: 3'b000,   //ignored\n//\t cache: 4'b0011, //ignored\n//\t lock: 2'b00,    //ignored\n//\t qos: 4'b0000    //ignored\n//\t });\n//   endrule\n//\n//   rule rl_rdata;\n//      let resp <- ddr3Controller.slave.resp_read.get();\n//      Vector#(BusRatio, Bit#(DataBusWidth)) datavec = unpack(resp.data);\n//\n//      function MemData#(DataBusWidth) to_md_data(Integer i);\n//\t return MemData { data: datavec[i], last: True, tag: resp.id };\n//      endfunction\n//      Vector#(BusRatio, MemData#(DataBusWidth)) data = genWith(to_md_data);\n//      dramReadGearbox.enq(data);\n//   endrule\n//   mkConnection(toGet(dramReadGearbox), ddr3re.dmaClient.readData);\n//\n//   rule rl_read_start;\n//      let sglId <- toGet(readReqFifo).get();\n//      we.writeServers[0].request.put(MemengineCmd { sglId: sglId,\n//\t\t\t\t\t\t   base: 0,\n//\t\t\t\t\t\t   burstLen: fromInteger(valueOf(TDiv#(Ddr3DataWidth,8))),\n//\t\t\t\t\t\t   len: 1024,\n//\t\t\t\t\t\t   tag: 0\n//\t\t\t\t\t\t   });\n//      ddr3re.readServers[0].request.put(MemengineCmd { sglId: 0,\n//\t\t\t\t\t\t      base: 0,\n//\t\t\t\t\t\t      burstLen: fromInteger(valueOf(TDiv#(Ddr3DataWidth,8))),\n//\t\t\t\t\t\t      len: 1024,\n//\t\t\t\t\t\t      tag: 0\n//\t\t\t\t\t\t      });\n//   endrule\n\n//   interface Ddr3TestRequest request;\n//      method Action startWriteDram(Bit#(32) sglId);\n//\t writeReqFifo.enq(sglId);\n//      endmethod\n//      method Action startReadDram(Bit#(32) sglId);\n//\t readReqFifo.enq(sglId);\n//      endmethod\n//   endinterface\n//   interface MemReadClient readClient = vec(re.dmaClient);\n//   interface MemWriteClient writeClient = vec(we.dmaClient);\n\n   interface `PinType pins;\n      method Action osc_50(Bit#(1) b3d, Bit#(1) b4a, Bit#(1) b4d, Bit#(1) b7a, Bit#(1) b7d, Bit#(1) b8a, Bit#(1) b8d);\n         iclock_50.inputclock(b7a);\n      endmethod\n      interface ddr3 = (interface Ddr3;\n         interface rzq_4 = ddr3Controller.rzq_4;\n         interface ddr3b = ddr3Controller.ddr3b;\n         interface sysclk_deleteme_unused_clock = ddr3Controller.sysclk_deleteme_unused_clock;\n         interface sysrst_deleteme_unused_reset = ddr3Controller.sysrst_deleteme_unused_reset;\n      endinterface);\n   endinterface\nendmodule\n"
  },
  {
    "path": "tests/ddr3_altera/Makefile",
    "content": "CONNECTALDIR?=../..\nS2H_INTERFACES = Ddr3TestRequest:Ddr3Test.request\nH2S_INTERFACES = Ddr3Test:Ddr3TestIndication:host\nMEM_READ_INTERFACES = lDdr3Test.readClient\n\nifneq ($(BOARD),zc706)\nCONNECTALFLAGS += -D DataBusWidth=128\nendif\nCONNECTALFLAGS += -D IMPORT_HOSTIF -D XILINX_SYS_CLK\nCONNECTALFLAGS += --xci=$(IPDIR)/$(BOARD)/synthesis/altera_mem_if_ddr3_emif_wrapper/altera_mem_if_ddr3_emif_wrapper.qip\n\nBSVFILES = Ddr3Test.bsv\nCPPFILES=testddr3.cpp\n\nPIN_BINDINGS ?= DDR3B:DDR3B PCIE:PCIE OSC:OSC RZQ:RZQ\nPINOUT_FILE = de5.json\n\nPIN_TYPE = Ddr3Pins\nPIN_TYPE_INCLUDE = AvalonDdr3Controller\nAUTOTOP = --interface pins:Ddr3Test.pins\n\nprebuild::\n\t(cd $(BOARD); BUILDCACHE_CACHEDIR=$(BUILDCACHE_CACHEDIR) $(BUILDCACHE) $(QUARTUS_SH) -t $(CONNECTALDIR)/scripts/connectal-synth-avalonddr3.tcl)\n\ninclude $(CONNECTALDIR)/Makefile.connectal\n"
  },
  {
    "path": "tests/ddr3_altera/de5.json",
    "content": "{\n        \"PCIE_tx_p[0]\": { \"PIO_DIRECTION\": \"OUTPUT\", \"PCIE\": \"PCIE_TX_p[0]\" },\n        \"PCIE_tx_p[1]\": { \"PIO_DIRECTION\": \"OUTPUT\", \"PCIE\": \"PCIE_TX_p[1]\" },\n        \"PCIE_tx_p[2]\": { \"PIO_DIRECTION\": \"OUTPUT\", \"PCIE\": \"PCIE_TX_p[2]\" },\n        \"PCIE_tx_p[3]\": { \"PIO_DIRECTION\": \"OUTPUT\", \"PCIE\": \"PCIE_TX_p[3]\" },\n        \"PCIE_tx_p[4]\": { \"PIO_DIRECTION\": \"OUTPUT\", \"PCIE\": \"PCIE_TX_p[4]\" },\n        \"PCIE_tx_p[5]\": { \"PIO_DIRECTION\": \"OUTPUT\", \"PCIE\": \"PCIE_TX_p[5]\" },\n        \"PCIE_tx_p[6]\": { \"PIO_DIRECTION\": \"OUTPUT\", \"PCIE\": \"PCIE_TX_p[6]\" },\n        \"PCIE_tx_p[7]\": { \"PIO_DIRECTION\": \"OUTPUT\", \"PCIE\": \"PCIE_TX_p[7]\" },\n        \"PCIE_rx_p[0]\": { \"PIO_DIRECTION\": \"INPUT\", \"PCIE\": \"PCIE_RX_p[0]\" },\n        \"PCIE_rx_p[1]\": { \"PIO_DIRECTION\": \"INPUT\", \"PCIE\": \"PCIE_RX_p[1]\" },\n        \"PCIE_rx_p[2]\": { \"PIO_DIRECTION\": \"INPUT\", \"PCIE\": \"PCIE_RX_p[2]\" },\n        \"PCIE_rx_p[3]\": { \"PIO_DIRECTION\": \"INPUT\", \"PCIE\": \"PCIE_RX_p[3]\" },\n        \"PCIE_rx_p[4]\": { \"PIO_DIRECTION\": \"INPUT\", \"PCIE\": \"PCIE_RX_p[4]\" },\n        \"PCIE_rx_p[5]\": { \"PIO_DIRECTION\": \"INPUT\", \"PCIE\": \"PCIE_RX_p[5]\" },\n        \"PCIE_rx_p[6]\": { \"PIO_DIRECTION\": \"INPUT\", \"PCIE\": \"PCIE_RX_p[6]\" },\n        \"PCIE_rx_p[7]\": { \"PIO_DIRECTION\": \"INPUT\", \"PCIE\": \"PCIE_RX_p[7]\" },\n        \"pcie_refclk_p\": { \"PIO_DIRECTION\": \"INPUT\", \"PCIE\": \"PCIE_REFCLK_p\" },\n        \"pcie_perst_n\": { \"PIO_DIRECTION\": \"INPUT\", \"PCIE\": \"PCIE_PERST_n\" },\n        \"osc_50_b3b\": { \"PIO_DIRECTION\": \"INPUT\", \"OSC\": \"OSC_50_B3B\" },\n        \"osc_50_b3d\": { \"PIO_DIRECTION\": \"INPUT\", \"OSC\": \"OSC_50_B3D\" },\n        \"osc_50_b4a\": { \"PIO_DIRECTION\": \"INPUT\", \"OSC\": \"OSC_50_B4A\" },\n        \"osc_50_b4d\": { \"PIO_DIRECTION\": \"INPUT\", \"OSC\": \"OSC_50_B4D\" },\n        \"osc_50_b7a\": { \"PIO_DIRECTION\": \"INPUT\", \"OSC\": \"OSC_50_B7A\" },\n        \"osc_50_b7d\": { \"PIO_DIRECTION\": \"INPUT\", \"OSC\": \"OSC_50_B7D\" },\n        \"osc_50_b8a\": { \"PIO_DIRECTION\": \"INPUT\", \"OSC\": \"OSC_50_B8A\" },\n        \"osc_50_b8d\": { \"PIO_DIRECTION\": \"INPUT\", \"OSC\": \"OSC_50_B8D\" },\n        \"rzq_4\": { \"PIO_DIRECTION\": \"INPUT\", \"RZQ\": \"RZQ_4\" },\n        \"ddr3b_a[0]\": { \"PIO_DIRECTION\": \"OUTPUT\", \"DDR3B\": \"DDR3B_A[0]\", \"CURRENT_STRENGTH_NEW\": \"MAXIMUM CURRENT\", \"PACKAGE_SKEW_COMPENSATION\": \"ON\"   },\n        \"ddr3b_a[1]\": { \"PIO_DIRECTION\": \"OUTPUT\", \"DDR3B\": \"DDR3B_A[1]\", \"CURRENT_STRENGTH_NEW\": \"MAXIMUM CURRENT\", \"PACKAGE_SKEW_COMPENSATION\": \"ON\"   },\n        \"ddr3b_a[2]\": { \"PIO_DIRECTION\": \"OUTPUT\", \"DDR3B\": \"DDR3B_A[2]\", \"CURRENT_STRENGTH_NEW\": \"MAXIMUM CURRENT\", \"PACKAGE_SKEW_COMPENSATION\": \"ON\"   },\n        \"ddr3b_a[3]\": { \"PIO_DIRECTION\": \"OUTPUT\", \"DDR3B\": \"DDR3B_A[3]\", \"CURRENT_STRENGTH_NEW\": \"MAXIMUM CURRENT\", \"PACKAGE_SKEW_COMPENSATION\": \"ON\"   },\n        \"ddr3b_a[4]\": { \"PIO_DIRECTION\": \"OUTPUT\", \"DDR3B\": \"DDR3B_A[4]\", \"CURRENT_STRENGTH_NEW\": \"MAXIMUM CURRENT\", \"PACKAGE_SKEW_COMPENSATION\": \"ON\"   },\n        \"ddr3b_a[5]\": { \"PIO_DIRECTION\": \"OUTPUT\", \"DDR3B\": \"DDR3B_A[5]\", \"CURRENT_STRENGTH_NEW\": \"MAXIMUM CURRENT\", \"PACKAGE_SKEW_COMPENSATION\": \"ON\"   },\n        \"ddr3b_a[6]\": { \"PIO_DIRECTION\": \"OUTPUT\", \"DDR3B\": \"DDR3B_A[6]\", \"CURRENT_STRENGTH_NEW\": \"MAXIMUM CURRENT\", \"PACKAGE_SKEW_COMPENSATION\": \"ON\"   },\n        \"ddr3b_a[7]\": { \"PIO_DIRECTION\": \"OUTPUT\", \"DDR3B\": \"DDR3B_A[7]\", \"CURRENT_STRENGTH_NEW\": \"MAXIMUM CURRENT\", \"PACKAGE_SKEW_COMPENSATION\": \"ON\"   },\n        \"ddr3b_a[8]\": { \"PIO_DIRECTION\": \"OUTPUT\", \"DDR3B\": \"DDR3B_A[8]\", \"CURRENT_STRENGTH_NEW\": \"MAXIMUM CURRENT\", \"PACKAGE_SKEW_COMPENSATION\": \"ON\"   },\n        \"ddr3b_a[9]\": { \"PIO_DIRECTION\": \"OUTPUT\", \"DDR3B\": \"DDR3B_A[9]\", \"CURRENT_STRENGTH_NEW\": \"MAXIMUM CURRENT\", \"PACKAGE_SKEW_COMPENSATION\": \"ON\"   },\n        \"ddr3b_a[10]\": { \"PIO_DIRECTION\": \"OUTPUT\", \"DDR3B\": \"DDR3B_A[10]\", \"CURRENT_STRENGTH_NEW\": \"MAXIMUM CURRENT\", \"PACKAGE_SKEW_COMPENSATION\": \"ON\"   },\n        \"ddr3b_a[11]\": { \"PIO_DIRECTION\": \"OUTPUT\", \"DDR3B\": \"DDR3B_A[11]\", \"CURRENT_STRENGTH_NEW\": \"MAXIMUM CURRENT\", \"PACKAGE_SKEW_COMPENSATION\": \"ON\"   },\n        \"ddr3b_a[12]\": { \"PIO_DIRECTION\": \"OUTPUT\", \"DDR3B\": \"DDR3B_A[12]\", \"CURRENT_STRENGTH_NEW\": \"MAXIMUM CURRENT\", \"PACKAGE_SKEW_COMPENSATION\": \"ON\"   },\n        \"ddr3b_a[13]\": { \"PIO_DIRECTION\": \"OUTPUT\", \"DDR3B\": \"DDR3B_A[13]\", \"CURRENT_STRENGTH_NEW\": \"MAXIMUM CURRENT\", \"PACKAGE_SKEW_COMPENSATION\": \"ON\"   },\n        \"ddr3b_a[14]\": { \"PIO_DIRECTION\": \"OUTPUT\", \"DDR3B\": \"DDR3B_A[14]\", \"CURRENT_STRENGTH_NEW\": \"MAXIMUM CURRENT\", \"PACKAGE_SKEW_COMPENSATION\": \"ON\"   },\n        \"ddr3b_a[15]\": { \"PIO_DIRECTION\": \"OUTPUT\", \"DDR3B\": \"DDR3B_A[15]\", \"CURRENT_STRENGTH_NEW\": \"MAXIMUM CURRENT\", \"PACKAGE_SKEW_COMPENSATION\": \"ON\"   },\n        \"ddr3b_ba[0]\": { \"PIO_DIRECTION\": \"OUTPUT\", \"DDR3B\": \"DDR3B_BA[0]\", \"CURRENT_STRENGTH_NEW\": \"MAXIMUM CURRENT\", \"PACKAGE_SKEW_COMPENSATION\": \"ON\"   },\n        \"ddr3b_ba[1]\": { \"PIO_DIRECTION\": \"OUTPUT\", \"DDR3B\": \"DDR3B_BA[1]\", \"CURRENT_STRENGTH_NEW\": \"MAXIMUM CURRENT\", \"PACKAGE_SKEW_COMPENSATION\": \"ON\"   },\n        \"ddr3b_ba[2]\": { \"PIO_DIRECTION\": \"OUTPUT\", \"DDR3B\": \"DDR3B_BA[2]\", \"CURRENT_STRENGTH_NEW\": \"MAXIMUM CURRENT\", \"PACKAGE_SKEW_COMPENSATION\": \"ON\"   },\n        \"ddr3b_cas_n\": { \"PIO_DIRECTION\": \"OUTPUT\", \"DDR3B\": \"DDR3B_CAS_n\", \"CURRENT_STRENGTH_NEW\": \"MAXIMUM CURRENT\", \"PACKAGE_SKEW_COMPENSATION\": \"ON\"   },\n        \"ddr3b_cke\": { \"PIO_DIRECTION\": \"OUTPUT\", \"DDR3B\": \"DDR3B_CKE[0]\", \"CURRENT_STRENGTH_NEW\": \"MAXIMUM CURRENT\", \"PACKAGE_SKEW_COMPENSATION\": \"ON\"   },\n        \"ddr3b_ck\": { \"PIO_DIRECTION\": \"OUTPUT\", \"DDR3B\": \"DDR3B_CK[0]\", \"OUTPUT_TERMINATION\": \"SERIES 50 OHM WITH CALIBRATION\", \"PACKAGE_SKEW_COMPENSATION\": \"ON\"  },\n        \"ddr3b_ck_n\": { \"PIO_DIRECTION\": \"OUTPUT\", \"DDR3B\": \"DDR3B_CK_n[0]\", \"OUTPUT_TERMINATION\": \"SERIES 50 OHM WITH CALIBRATION\", \"PACKAGE_SKEW_COMPENSATION\": \"ON\"   },\n        \"ddr3b_cs_n\": { \"PIO_DIRECTION\": \"OUTPUT\", \"DDR3B\": \"DDR3B_CS_n[0]\", \"CURRENT_STRENGTH_NEW\": \"MAXIMUM CURRENT\", \"PACKAGE_SKEW_COMPENSATION\": \"ON\"   },\n        \"ddr3b_we_n\": { \"PIO_DIRECTION\": \"OUTPUT\", \"DDR3B\": \"DDR3B_WE_n\", \"CURRENT_STRENGTH_NEW\": \"MAXIMUM CURRENT\", \"PACKAGE_SKEW_COMPENSATION\": \"ON\"   },\n        \"ddr3b_scl\": { \"PIO_DIRECTION\": \"OUTPUT\", \"DDR3B\": \"DDR3B_SCL\" },\n        \"ddr3b_sda\": { \"PIO_DIRECTION\": \"BIDIR\", \"DDR3B\": \"DDR3B_SDA\" },\n        \"ddr3b_ras_n\": { \"PIO_DIRECTION\": \"OUTPUT\", \"DDR3B\": \"DDR3B_RAS_n\", \"CURRENT_STRENGTH_NEW\": \"MAXIMUM CURRENT\", \"PACKAGE_SKEW_COMPENSATION\": \"ON\"  },\n        \"ddr3b_reset_n\": { \"PIO_DIRECTION\": \"OUTPUT\", \"DDR3B\": \"DDR3B_RESET_n\", \"CURRENT_STRENGTH_NEW\": \"MAXIMUM CURRENT\", \"PACKAGE_SKEW_COMPENSATION\": \"ON\"   },\n        \"ddr3b_odt\": { \"PIO_DIRECTION\": \"OUTPUT\", \"DDR3B\": \"DDR3B_ODT[0]\", \"CURRENT_STRENGTH_NEW\": \"MAXIMUM CURRENT\", \"PACKAGE_SKEW_COMPENSATION\": \"ON\"   },\n        \"ddr3b_event_n\": { \"PIO_DIRECTION\": \"INPUT\", \"DDR3B\": \"DDR3B_EVENT_n\" },\n        \"ddr3b_dm[0]\": { \"PIO_DIRECTION\": \"OUTPUT\", \"DDR3B\": \"DDR3B_DM[0]\", \"OUTPUT_TERMINATION\": \"SERIES 50 OHM WITH CALIBRATION\", \"PACKAGE_SKEW_COMPENSATION\": \"ON\"   },\n        \"ddr3b_dm[1]\": { \"PIO_DIRECTION\": \"OUTPUT\", \"DDR3B\": \"DDR3B_DM[1]\", \"OUTPUT_TERMINATION\": \"SERIES 50 OHM WITH CALIBRATION\", \"PACKAGE_SKEW_COMPENSATION\": \"ON\"   },\n        \"ddr3b_dm[2]\": { \"PIO_DIRECTION\": \"OUTPUT\", \"DDR3B\": \"DDR3B_DM[2]\", \"OUTPUT_TERMINATION\": \"SERIES 50 OHM WITH CALIBRATION\", \"PACKAGE_SKEW_COMPENSATION\": \"ON\"   },\n        \"ddr3b_dm[3]\": { \"PIO_DIRECTION\": \"OUTPUT\", \"DDR3B\": \"DDR3B_DM[3]\", \"OUTPUT_TERMINATION\": \"SERIES 50 OHM WITH CALIBRATION\", \"PACKAGE_SKEW_COMPENSATION\": \"ON\"   },\n        \"ddr3b_dm[4]\": { \"PIO_DIRECTION\": \"OUTPUT\", \"DDR3B\": \"DDR3B_DM[4]\", \"OUTPUT_TERMINATION\": \"SERIES 50 OHM WITH CALIBRATION\", \"PACKAGE_SKEW_COMPENSATION\": \"ON\"   },\n        \"ddr3b_dm[5]\": { \"PIO_DIRECTION\": \"OUTPUT\", \"DDR3B\": \"DDR3B_DM[5]\", \"OUTPUT_TERMINATION\": \"SERIES 50 OHM WITH CALIBRATION\", \"PACKAGE_SKEW_COMPENSATION\": \"ON\"   },\n        \"ddr3b_dm[6]\": { \"PIO_DIRECTION\": \"OUTPUT\", \"DDR3B\": \"DDR3B_DM[6]\", \"OUTPUT_TERMINATION\": \"SERIES 50 OHM WITH CALIBRATION\", \"PACKAGE_SKEW_COMPENSATION\": \"ON\"   },\n        \"ddr3b_dm[7]\": { \"PIO_DIRECTION\": \"OUTPUT\", \"DDR3B\": \"DDR3B_DM[7]\", \"OUTPUT_TERMINATION\": \"SERIES 50 OHM WITH CALIBRATION\", \"PACKAGE_SKEW_COMPENSATION\": \"ON\"   },\n        \"ddr3b_dqs[0]\": { \"PIO_DIRECTION\": \"BIDIR\", \"DDR3B\": \"DDR3B_DQS[0]\", \"INPUT_TERMINATION\": \"PARALLEL 50 OHM WITH CALIBRATION\", \"OUTPUT_TERMINATION\": \"SERIES 50 OHM WITH CALIBRATION\", \"PACKAGE_SKEW_COMPENSATION\": \"ON\"   },\n        \"ddr3b_dqs[1]\": { \"PIO_DIRECTION\": \"BIDIR\", \"DDR3B\": \"DDR3B_DQS[1]\", \"INPUT_TERMINATION\": \"PARALLEL 50 OHM WITH CALIBRATION\", \"OUTPUT_TERMINATION\": \"SERIES 50 OHM WITH CALIBRATION\", \"PACKAGE_SKEW_COMPENSATION\": \"ON\"   },\n        \"ddr3b_dqs[2]\": { \"PIO_DIRECTION\": \"BIDIR\", \"DDR3B\": \"DDR3B_DQS[2]\", \"INPUT_TERMINATION\": \"PARALLEL 50 OHM WITH CALIBRATION\", \"OUTPUT_TERMINATION\": \"SERIES 50 OHM WITH CALIBRATION\", \"PACKAGE_SKEW_COMPENSATION\": \"ON\"   },\n        \"ddr3b_dqs[3]\": { \"PIO_DIRECTION\": \"BIDIR\", \"DDR3B\": \"DDR3B_DQS[3]\", \"INPUT_TERMINATION\": \"PARALLEL 50 OHM WITH CALIBRATION\", \"OUTPUT_TERMINATION\": \"SERIES 50 OHM WITH CALIBRATION\", \"PACKAGE_SKEW_COMPENSATION\": \"ON\"   },\n        \"ddr3b_dqs[4]\": { \"PIO_DIRECTION\": \"BIDIR\", \"DDR3B\": \"DDR3B_DQS[4]\", \"INPUT_TERMINATION\": \"PARALLEL 50 OHM WITH CALIBRATION\", \"OUTPUT_TERMINATION\": \"SERIES 50 OHM WITH CALIBRATION\", \"PACKAGE_SKEW_COMPENSATION\": \"ON\"   },\n        \"ddr3b_dqs[5]\": { \"PIO_DIRECTION\": \"BIDIR\", \"DDR3B\": \"DDR3B_DQS[5]\", \"INPUT_TERMINATION\": \"PARALLEL 50 OHM WITH CALIBRATION\", \"OUTPUT_TERMINATION\": \"SERIES 50 OHM WITH CALIBRATION\", \"PACKAGE_SKEW_COMPENSATION\": \"ON\"   },\n        \"ddr3b_dqs[6]\": { \"PIO_DIRECTION\": \"BIDIR\", \"DDR3B\": \"DDR3B_DQS[6]\", \"INPUT_TERMINATION\": \"PARALLEL 50 OHM WITH CALIBRATION\", \"OUTPUT_TERMINATION\": \"SERIES 50 OHM WITH CALIBRATION\", \"PACKAGE_SKEW_COMPENSATION\": \"ON\"   },\n        \"ddr3b_dqs[7]\": { \"PIO_DIRECTION\": \"BIDIR\", \"DDR3B\": \"DDR3B_DQS[7]\", \"INPUT_TERMINATION\": \"PARALLEL 50 OHM WITH CALIBRATION\", \"OUTPUT_TERMINATION\": \"SERIES 50 OHM WITH CALIBRATION\", \"PACKAGE_SKEW_COMPENSATION\": \"ON\"   },\n        \"ddr3b_dqs_n[0]\": { \"PIO_DIRECTION\": \"BIDIR\", \"DDR3B\": \"DDR3B_DQS_n[0]\", \"INPUT_TERMINATION\": \"PARALLEL 50 OHM WITH CALIBRATION\", \"OUTPUT_TERMINATION\": \"SERIES 50 OHM WITH CALIBRATION\", \"PACKAGE_SKEW_COMPENSATION\": \"ON\"   },\n        \"ddr3b_dqs_n[1]\": { \"PIO_DIRECTION\": \"BIDIR\", \"DDR3B\": \"DDR3B_DQS_n[1]\", \"INPUT_TERMINATION\": \"PARALLEL 50 OHM WITH CALIBRATION\", \"OUTPUT_TERMINATION\": \"SERIES 50 OHM WITH CALIBRATION\", \"PACKAGE_SKEW_COMPENSATION\": \"ON\"   },\n        \"ddr3b_dqs_n[2]\": { \"PIO_DIRECTION\": \"BIDIR\", \"DDR3B\": \"DDR3B_DQS_n[2]\", \"INPUT_TERMINATION\": \"PARALLEL 50 OHM WITH CALIBRATION\", \"OUTPUT_TERMINATION\": \"SERIES 50 OHM WITH CALIBRATION\", \"PACKAGE_SKEW_COMPENSATION\": \"ON\"   },\n        \"ddr3b_dqs_n[3]\": { \"PIO_DIRECTION\": \"BIDIR\", \"DDR3B\": \"DDR3B_DQS_n[3]\", \"INPUT_TERMINATION\": \"PARALLEL 50 OHM WITH CALIBRATION\", \"OUTPUT_TERMINATION\": \"SERIES 50 OHM WITH CALIBRATION\", \"PACKAGE_SKEW_COMPENSATION\": \"ON\"   },\n        \"ddr3b_dqs_n[4]\": { \"PIO_DIRECTION\": \"BIDIR\", \"DDR3B\": \"DDR3B_DQS_n[4]\", \"INPUT_TERMINATION\": \"PARALLEL 50 OHM WITH CALIBRATION\", \"OUTPUT_TERMINATION\": \"SERIES 50 OHM WITH CALIBRATION\", \"PACKAGE_SKEW_COMPENSATION\": \"ON\"   },\n        \"ddr3b_dqs_n[5]\": { \"PIO_DIRECTION\": \"BIDIR\", \"DDR3B\": \"DDR3B_DQS_n[5]\", \"INPUT_TERMINATION\": \"PARALLEL 50 OHM WITH CALIBRATION\", \"OUTPUT_TERMINATION\": \"SERIES 50 OHM WITH CALIBRATION\", \"PACKAGE_SKEW_COMPENSATION\": \"ON\"   },\n        \"ddr3b_dqs_n[6]\": { \"PIO_DIRECTION\": \"BIDIR\", \"DDR3B\": \"DDR3B_DQS_n[6]\", \"INPUT_TERMINATION\": \"PARALLEL 50 OHM WITH CALIBRATION\", \"OUTPUT_TERMINATION\": \"SERIES 50 OHM WITH CALIBRATION\", \"PACKAGE_SKEW_COMPENSATION\": \"ON\"   },\n        \"ddr3b_dqs_n[7]\": { \"PIO_DIRECTION\": \"BIDIR\", \"DDR3B\": \"DDR3B_DQS_n[7]\", \"INPUT_TERMINATION\": \"PARALLEL 50 OHM WITH CALIBRATION\", \"OUTPUT_TERMINATION\": \"SERIES 50 OHM WITH CALIBRATION\", \"PACKAGE_SKEW_COMPENSATION\": \"ON\"   },\n        \"ddr3b_dq[0]\": { \"PIO_DIRECTION\": \"BIDIR\", \"DDR3B\": \"DDR3B_DQ[0]\", \"INPUT_TERMINATION\": \"PARALLEL 50 OHM WITH CALIBRATION\", \"OUTPUT_TERMINATION\": \"SERIES 50 OHM WITH CALIBRATION\", \"PACKAGE_SKEW_COMPENSATION\": \"ON\" },\n        \"ddr3b_dq[1]\": { \"PIO_DIRECTION\": \"BIDIR\", \"DDR3B\": \"DDR3B_DQ[1]\", \"INPUT_TERMINATION\": \"PARALLEL 50 OHM WITH CALIBRATION\", \"OUTPUT_TERMINATION\": \"SERIES 50 OHM WITH CALIBRATION\", \"PACKAGE_SKEW_COMPENSATION\": \"ON\" },\n        \"ddr3b_dq[2]\": { \"PIO_DIRECTION\": \"BIDIR\", \"DDR3B\": \"DDR3B_DQ[2]\", \"INPUT_TERMINATION\": \"PARALLEL 50 OHM WITH CALIBRATION\", \"OUTPUT_TERMINATION\": \"SERIES 50 OHM WITH CALIBRATION\", \"PACKAGE_SKEW_COMPENSATION\": \"ON\" },\n        \"ddr3b_dq[3]\": { \"PIO_DIRECTION\": \"BIDIR\", \"DDR3B\": \"DDR3B_DQ[3]\", \"INPUT_TERMINATION\": \"PARALLEL 50 OHM WITH CALIBRATION\", \"OUTPUT_TERMINATION\": \"SERIES 50 OHM WITH CALIBRATION\", \"PACKAGE_SKEW_COMPENSATION\": \"ON\" },\n        \"ddr3b_dq[4]\": { \"PIO_DIRECTION\": \"BIDIR\", \"DDR3B\": \"DDR3B_DQ[4]\", \"INPUT_TERMINATION\": \"PARALLEL 50 OHM WITH CALIBRATION\", \"OUTPUT_TERMINATION\": \"SERIES 50 OHM WITH CALIBRATION\", \"PACKAGE_SKEW_COMPENSATION\": \"ON\" },\n        \"ddr3b_dq[5]\": { \"PIO_DIRECTION\": \"BIDIR\", \"DDR3B\": \"DDR3B_DQ[5]\", \"INPUT_TERMINATION\": \"PARALLEL 50 OHM WITH CALIBRATION\", \"OUTPUT_TERMINATION\": \"SERIES 50 OHM WITH CALIBRATION\", \"PACKAGE_SKEW_COMPENSATION\": \"ON\" },\n        \"ddr3b_dq[6]\": { \"PIO_DIRECTION\": \"BIDIR\", \"DDR3B\": \"DDR3B_DQ[6]\", \"INPUT_TERMINATION\": \"PARALLEL 50 OHM WITH CALIBRATION\", \"OUTPUT_TERMINATION\": \"SERIES 50 OHM WITH CALIBRATION\", \"PACKAGE_SKEW_COMPENSATION\": \"ON\" },\n        \"ddr3b_dq[7]\": { \"PIO_DIRECTION\": \"BIDIR\", \"DDR3B\": \"DDR3B_DQ[7]\", \"INPUT_TERMINATION\": \"PARALLEL 50 OHM WITH CALIBRATION\", \"OUTPUT_TERMINATION\": \"SERIES 50 OHM WITH CALIBRATION\", \"PACKAGE_SKEW_COMPENSATION\": \"ON\" },\n        \"ddr3b_dq[8]\": { \"PIO_DIRECTION\": \"BIDIR\", \"DDR3B\": \"DDR3B_DQ[8]\", \"INPUT_TERMINATION\": \"PARALLEL 50 OHM WITH CALIBRATION\", \"OUTPUT_TERMINATION\": \"SERIES 50 OHM WITH CALIBRATION\", \"PACKAGE_SKEW_COMPENSATION\": \"ON\" },\n        \"ddr3b_dq[9]\": { \"PIO_DIRECTION\": \"BIDIR\", \"DDR3B\": \"DDR3B_DQ[9]\", \"INPUT_TERMINATION\": \"PARALLEL 50 OHM WITH CALIBRATION\", \"OUTPUT_TERMINATION\": \"SERIES 50 OHM WITH CALIBRATION\", \"PACKAGE_SKEW_COMPENSATION\": \"ON\" },\n        \"ddr3b_dq[10]\": { \"PIO_DIRECTION\": \"BIDIR\", \"DDR3B\": \"DDR3B_DQ[10]\", \"INPUT_TERMINATION\": \"PARALLEL 50 OHM WITH CALIBRATION\", \"OUTPUT_TERMINATION\": \"SERIES 50 OHM WITH CALIBRATION\", \"PACKAGE_SKEW_COMPENSATION\": \"ON\"  },\n        \"ddr3b_dq[11]\": { \"PIO_DIRECTION\": \"BIDIR\", \"DDR3B\": \"DDR3B_DQ[11]\", \"INPUT_TERMINATION\": \"PARALLEL 50 OHM WITH CALIBRATION\", \"OUTPUT_TERMINATION\": \"SERIES 50 OHM WITH CALIBRATION\", \"PACKAGE_SKEW_COMPENSATION\": \"ON\"  },\n        \"ddr3b_dq[12]\": { \"PIO_DIRECTION\": \"BIDIR\", \"DDR3B\": \"DDR3B_DQ[12]\", \"INPUT_TERMINATION\": \"PARALLEL 50 OHM WITH CALIBRATION\", \"OUTPUT_TERMINATION\": \"SERIES 50 OHM WITH CALIBRATION\", \"PACKAGE_SKEW_COMPENSATION\": \"ON\"  },\n        \"ddr3b_dq[13]\": { \"PIO_DIRECTION\": \"BIDIR\", \"DDR3B\": \"DDR3B_DQ[13]\", \"INPUT_TERMINATION\": \"PARALLEL 50 OHM WITH CALIBRATION\", \"OUTPUT_TERMINATION\": \"SERIES 50 OHM WITH CALIBRATION\", \"PACKAGE_SKEW_COMPENSATION\": \"ON\"  },\n        \"ddr3b_dq[14]\": { \"PIO_DIRECTION\": \"BIDIR\", \"DDR3B\": \"DDR3B_DQ[14]\", \"INPUT_TERMINATION\": \"PARALLEL 50 OHM WITH CALIBRATION\", \"OUTPUT_TERMINATION\": \"SERIES 50 OHM WITH CALIBRATION\", \"PACKAGE_SKEW_COMPENSATION\": \"ON\"  },\n        \"ddr3b_dq[15]\": { \"PIO_DIRECTION\": \"BIDIR\", \"DDR3B\": \"DDR3B_DQ[15]\", \"INPUT_TERMINATION\": \"PARALLEL 50 OHM WITH CALIBRATION\", \"OUTPUT_TERMINATION\": \"SERIES 50 OHM WITH CALIBRATION\", \"PACKAGE_SKEW_COMPENSATION\": \"ON\"  },\n        \"ddr3b_dq[16]\": { \"PIO_DIRECTION\": \"BIDIR\", \"DDR3B\": \"DDR3B_DQ[16]\", \"INPUT_TERMINATION\": \"PARALLEL 50 OHM WITH CALIBRATION\", \"OUTPUT_TERMINATION\": \"SERIES 50 OHM WITH CALIBRATION\", \"PACKAGE_SKEW_COMPENSATION\": \"ON\"  },\n        \"ddr3b_dq[17]\": { \"PIO_DIRECTION\": \"BIDIR\", \"DDR3B\": \"DDR3B_DQ[17]\", \"INPUT_TERMINATION\": \"PARALLEL 50 OHM WITH CALIBRATION\", \"OUTPUT_TERMINATION\": \"SERIES 50 OHM WITH CALIBRATION\", \"PACKAGE_SKEW_COMPENSATION\": \"ON\"  },\n        \"ddr3b_dq[18]\": { \"PIO_DIRECTION\": \"BIDIR\", \"DDR3B\": \"DDR3B_DQ[18]\", \"INPUT_TERMINATION\": \"PARALLEL 50 OHM WITH CALIBRATION\", \"OUTPUT_TERMINATION\": \"SERIES 50 OHM WITH CALIBRATION\", \"PACKAGE_SKEW_COMPENSATION\": \"ON\"  },\n        \"ddr3b_dq[19]\": { \"PIO_DIRECTION\": \"BIDIR\", \"DDR3B\": \"DDR3B_DQ[19]\", \"INPUT_TERMINATION\": \"PARALLEL 50 OHM WITH CALIBRATION\", \"OUTPUT_TERMINATION\": \"SERIES 50 OHM WITH CALIBRATION\", \"PACKAGE_SKEW_COMPENSATION\": \"ON\"  },\n        \"ddr3b_dq[20]\": { \"PIO_DIRECTION\": \"BIDIR\", \"DDR3B\": \"DDR3B_DQ[20]\", \"INPUT_TERMINATION\": \"PARALLEL 50 OHM WITH CALIBRATION\", \"OUTPUT_TERMINATION\": \"SERIES 50 OHM WITH CALIBRATION\", \"PACKAGE_SKEW_COMPENSATION\": \"ON\"  },\n        \"ddr3b_dq[21]\": { \"PIO_DIRECTION\": \"BIDIR\", \"DDR3B\": \"DDR3B_DQ[21]\", \"INPUT_TERMINATION\": \"PARALLEL 50 OHM WITH CALIBRATION\", \"OUTPUT_TERMINATION\": \"SERIES 50 OHM WITH CALIBRATION\", \"PACKAGE_SKEW_COMPENSATION\": \"ON\"  },\n        \"ddr3b_dq[22]\": { \"PIO_DIRECTION\": \"BIDIR\", \"DDR3B\": \"DDR3B_DQ[22]\", \"INPUT_TERMINATION\": \"PARALLEL 50 OHM WITH CALIBRATION\", \"OUTPUT_TERMINATION\": \"SERIES 50 OHM WITH CALIBRATION\", \"PACKAGE_SKEW_COMPENSATION\": \"ON\"  },\n        \"ddr3b_dq[23]\": { \"PIO_DIRECTION\": \"BIDIR\", \"DDR3B\": \"DDR3B_DQ[23]\", \"INPUT_TERMINATION\": \"PARALLEL 50 OHM WITH CALIBRATION\", \"OUTPUT_TERMINATION\": \"SERIES 50 OHM WITH CALIBRATION\", \"PACKAGE_SKEW_COMPENSATION\": \"ON\"  },\n        \"ddr3b_dq[24]\": { \"PIO_DIRECTION\": \"BIDIR\", \"DDR3B\": \"DDR3B_DQ[24]\", \"INPUT_TERMINATION\": \"PARALLEL 50 OHM WITH CALIBRATION\", \"OUTPUT_TERMINATION\": \"SERIES 50 OHM WITH CALIBRATION\", \"PACKAGE_SKEW_COMPENSATION\": \"ON\"  },\n        \"ddr3b_dq[25]\": { \"PIO_DIRECTION\": \"BIDIR\", \"DDR3B\": \"DDR3B_DQ[25]\", \"INPUT_TERMINATION\": \"PARALLEL 50 OHM WITH CALIBRATION\", \"OUTPUT_TERMINATION\": \"SERIES 50 OHM WITH CALIBRATION\", \"PACKAGE_SKEW_COMPENSATION\": \"ON\"  },\n        \"ddr3b_dq[26]\": { \"PIO_DIRECTION\": \"BIDIR\", \"DDR3B\": \"DDR3B_DQ[26]\", \"INPUT_TERMINATION\": \"PARALLEL 50 OHM WITH CALIBRATION\", \"OUTPUT_TERMINATION\": \"SERIES 50 OHM WITH CALIBRATION\", \"PACKAGE_SKEW_COMPENSATION\": \"ON\"  },\n        \"ddr3b_dq[27]\": { \"PIO_DIRECTION\": \"BIDIR\", \"DDR3B\": \"DDR3B_DQ[27]\", \"INPUT_TERMINATION\": \"PARALLEL 50 OHM WITH CALIBRATION\", \"OUTPUT_TERMINATION\": \"SERIES 50 OHM WITH CALIBRATION\", \"PACKAGE_SKEW_COMPENSATION\": \"ON\"  },\n        \"ddr3b_dq[28]\": { \"PIO_DIRECTION\": \"BIDIR\", \"DDR3B\": \"DDR3B_DQ[28]\", \"INPUT_TERMINATION\": \"PARALLEL 50 OHM WITH CALIBRATION\", \"OUTPUT_TERMINATION\": \"SERIES 50 OHM WITH CALIBRATION\", \"PACKAGE_SKEW_COMPENSATION\": \"ON\"  },\n        \"ddr3b_dq[29]\": { \"PIO_DIRECTION\": \"BIDIR\", \"DDR3B\": \"DDR3B_DQ[29]\", \"INPUT_TERMINATION\": \"PARALLEL 50 OHM WITH CALIBRATION\", \"OUTPUT_TERMINATION\": \"SERIES 50 OHM WITH CALIBRATION\", \"PACKAGE_SKEW_COMPENSATION\": \"ON\"  },\n        \"ddr3b_dq[30]\": { \"PIO_DIRECTION\": \"BIDIR\", \"DDR3B\": \"DDR3B_DQ[30]\", \"INPUT_TERMINATION\": \"PARALLEL 50 OHM WITH CALIBRATION\", \"OUTPUT_TERMINATION\": \"SERIES 50 OHM WITH CALIBRATION\", \"PACKAGE_SKEW_COMPENSATION\": \"ON\"  },\n        \"ddr3b_dq[31]\": { \"PIO_DIRECTION\": \"BIDIR\", \"DDR3B\": \"DDR3B_DQ[31]\", \"INPUT_TERMINATION\": \"PARALLEL 50 OHM WITH CALIBRATION\", \"OUTPUT_TERMINATION\": \"SERIES 50 OHM WITH CALIBRATION\", \"PACKAGE_SKEW_COMPENSATION\": \"ON\"  },\n        \"ddr3b_dq[32]\": { \"PIO_DIRECTION\": \"BIDIR\", \"DDR3B\": \"DDR3B_DQ[32]\", \"INPUT_TERMINATION\": \"PARALLEL 50 OHM WITH CALIBRATION\", \"OUTPUT_TERMINATION\": \"SERIES 50 OHM WITH CALIBRATION\", \"PACKAGE_SKEW_COMPENSATION\": \"ON\"  },\n        \"ddr3b_dq[33]\": { \"PIO_DIRECTION\": \"BIDIR\", \"DDR3B\": \"DDR3B_DQ[33]\", \"INPUT_TERMINATION\": \"PARALLEL 50 OHM WITH CALIBRATION\", \"OUTPUT_TERMINATION\": \"SERIES 50 OHM WITH CALIBRATION\", \"PACKAGE_SKEW_COMPENSATION\": \"ON\"  },\n        \"ddr3b_dq[34]\": { \"PIO_DIRECTION\": \"BIDIR\", \"DDR3B\": \"DDR3B_DQ[34]\", \"INPUT_TERMINATION\": \"PARALLEL 50 OHM WITH CALIBRATION\", \"OUTPUT_TERMINATION\": \"SERIES 50 OHM WITH CALIBRATION\", \"PACKAGE_SKEW_COMPENSATION\": \"ON\"  },\n        \"ddr3b_dq[35]\": { \"PIO_DIRECTION\": \"BIDIR\", \"DDR3B\": \"DDR3B_DQ[35]\", \"INPUT_TERMINATION\": \"PARALLEL 50 OHM WITH CALIBRATION\", \"OUTPUT_TERMINATION\": \"SERIES 50 OHM WITH CALIBRATION\", \"PACKAGE_SKEW_COMPENSATION\": \"ON\"  },\n        \"ddr3b_dq[36]\": { \"PIO_DIRECTION\": \"BIDIR\", \"DDR3B\": \"DDR3B_DQ[36]\", \"INPUT_TERMINATION\": \"PARALLEL 50 OHM WITH CALIBRATION\", \"OUTPUT_TERMINATION\": \"SERIES 50 OHM WITH CALIBRATION\", \"PACKAGE_SKEW_COMPENSATION\": \"ON\"  },\n        \"ddr3b_dq[37]\": { \"PIO_DIRECTION\": \"BIDIR\", \"DDR3B\": \"DDR3B_DQ[37]\", \"INPUT_TERMINATION\": \"PARALLEL 50 OHM WITH CALIBRATION\", \"OUTPUT_TERMINATION\": \"SERIES 50 OHM WITH CALIBRATION\", \"PACKAGE_SKEW_COMPENSATION\": \"ON\"  },\n        \"ddr3b_dq[38]\": { \"PIO_DIRECTION\": \"BIDIR\", \"DDR3B\": \"DDR3B_DQ[38]\", \"INPUT_TERMINATION\": \"PARALLEL 50 OHM WITH CALIBRATION\", \"OUTPUT_TERMINATION\": \"SERIES 50 OHM WITH CALIBRATION\", \"PACKAGE_SKEW_COMPENSATION\": \"ON\"  },\n        \"ddr3b_dq[39]\": { \"PIO_DIRECTION\": \"BIDIR\", \"DDR3B\": \"DDR3B_DQ[39]\", \"INPUT_TERMINATION\": \"PARALLEL 50 OHM WITH CALIBRATION\", \"OUTPUT_TERMINATION\": \"SERIES 50 OHM WITH CALIBRATION\", \"PACKAGE_SKEW_COMPENSATION\": \"ON\"  },\n        \"ddr3b_dq[40]\": { \"PIO_DIRECTION\": \"BIDIR\", \"DDR3B\": \"DDR3B_DQ[40]\", \"INPUT_TERMINATION\": \"PARALLEL 50 OHM WITH CALIBRATION\", \"OUTPUT_TERMINATION\": \"SERIES 50 OHM WITH CALIBRATION\", \"PACKAGE_SKEW_COMPENSATION\": \"ON\"  },\n        \"ddr3b_dq[41]\": { \"PIO_DIRECTION\": \"BIDIR\", \"DDR3B\": \"DDR3B_DQ[41]\", \"INPUT_TERMINATION\": \"PARALLEL 50 OHM WITH CALIBRATION\", \"OUTPUT_TERMINATION\": \"SERIES 50 OHM WITH CALIBRATION\", \"PACKAGE_SKEW_COMPENSATION\": \"ON\"  },\n        \"ddr3b_dq[42]\": { \"PIO_DIRECTION\": \"BIDIR\", \"DDR3B\": \"DDR3B_DQ[42]\", \"INPUT_TERMINATION\": \"PARALLEL 50 OHM WITH CALIBRATION\", \"OUTPUT_TERMINATION\": \"SERIES 50 OHM WITH CALIBRATION\", \"PACKAGE_SKEW_COMPENSATION\": \"ON\"  },\n        \"ddr3b_dq[43]\": { \"PIO_DIRECTION\": \"BIDIR\", \"DDR3B\": \"DDR3B_DQ[43]\", \"INPUT_TERMINATION\": \"PARALLEL 50 OHM WITH CALIBRATION\", \"OUTPUT_TERMINATION\": \"SERIES 50 OHM WITH CALIBRATION\", \"PACKAGE_SKEW_COMPENSATION\": \"ON\"  },\n        \"ddr3b_dq[44]\": { \"PIO_DIRECTION\": \"BIDIR\", \"DDR3B\": \"DDR3B_DQ[44]\", \"INPUT_TERMINATION\": \"PARALLEL 50 OHM WITH CALIBRATION\", \"OUTPUT_TERMINATION\": \"SERIES 50 OHM WITH CALIBRATION\", \"PACKAGE_SKEW_COMPENSATION\": \"ON\"  },\n        \"ddr3b_dq[45]\": { \"PIO_DIRECTION\": \"BIDIR\", \"DDR3B\": \"DDR3B_DQ[45]\", \"INPUT_TERMINATION\": \"PARALLEL 50 OHM WITH CALIBRATION\", \"OUTPUT_TERMINATION\": \"SERIES 50 OHM WITH CALIBRATION\", \"PACKAGE_SKEW_COMPENSATION\": \"ON\"  },\n        \"ddr3b_dq[46]\": { \"PIO_DIRECTION\": \"BIDIR\", \"DDR3B\": \"DDR3B_DQ[46]\", \"INPUT_TERMINATION\": \"PARALLEL 50 OHM WITH CALIBRATION\", \"OUTPUT_TERMINATION\": \"SERIES 50 OHM WITH CALIBRATION\", \"PACKAGE_SKEW_COMPENSATION\": \"ON\"  },\n        \"ddr3b_dq[47]\": { \"PIO_DIRECTION\": \"BIDIR\", \"DDR3B\": \"DDR3B_DQ[47]\", \"INPUT_TERMINATION\": \"PARALLEL 50 OHM WITH CALIBRATION\", \"OUTPUT_TERMINATION\": \"SERIES 50 OHM WITH CALIBRATION\", \"PACKAGE_SKEW_COMPENSATION\": \"ON\"  },\n        \"ddr3b_dq[48]\": { \"PIO_DIRECTION\": \"BIDIR\", \"DDR3B\": \"DDR3B_DQ[48]\", \"INPUT_TERMINATION\": \"PARALLEL 50 OHM WITH CALIBRATION\", \"OUTPUT_TERMINATION\": \"SERIES 50 OHM WITH CALIBRATION\", \"PACKAGE_SKEW_COMPENSATION\": \"ON\"  },\n        \"ddr3b_dq[49]\": { \"PIO_DIRECTION\": \"BIDIR\", \"DDR3B\": \"DDR3B_DQ[49]\", \"INPUT_TERMINATION\": \"PARALLEL 50 OHM WITH CALIBRATION\", \"OUTPUT_TERMINATION\": \"SERIES 50 OHM WITH CALIBRATION\", \"PACKAGE_SKEW_COMPENSATION\": \"ON\"  },\n        \"ddr3b_dq[50]\": { \"PIO_DIRECTION\": \"BIDIR\", \"DDR3B\": \"DDR3B_DQ[50]\", \"INPUT_TERMINATION\": \"PARALLEL 50 OHM WITH CALIBRATION\", \"OUTPUT_TERMINATION\": \"SERIES 50 OHM WITH CALIBRATION\", \"PACKAGE_SKEW_COMPENSATION\": \"ON\"  },\n        \"ddr3b_dq[51]\": { \"PIO_DIRECTION\": \"BIDIR\", \"DDR3B\": \"DDR3B_DQ[51]\", \"INPUT_TERMINATION\": \"PARALLEL 50 OHM WITH CALIBRATION\", \"OUTPUT_TERMINATION\": \"SERIES 50 OHM WITH CALIBRATION\", \"PACKAGE_SKEW_COMPENSATION\": \"ON\"  },\n        \"ddr3b_dq[52]\": { \"PIO_DIRECTION\": \"BIDIR\", \"DDR3B\": \"DDR3B_DQ[52]\", \"INPUT_TERMINATION\": \"PARALLEL 50 OHM WITH CALIBRATION\", \"OUTPUT_TERMINATION\": \"SERIES 50 OHM WITH CALIBRATION\", \"PACKAGE_SKEW_COMPENSATION\": \"ON\"  },\n        \"ddr3b_dq[53]\": { \"PIO_DIRECTION\": \"BIDIR\", \"DDR3B\": \"DDR3B_DQ[53]\", \"INPUT_TERMINATION\": \"PARALLEL 50 OHM WITH CALIBRATION\", \"OUTPUT_TERMINATION\": \"SERIES 50 OHM WITH CALIBRATION\", \"PACKAGE_SKEW_COMPENSATION\": \"ON\"  },\n        \"ddr3b_dq[54]\": { \"PIO_DIRECTION\": \"BIDIR\", \"DDR3B\": \"DDR3B_DQ[54]\", \"INPUT_TERMINATION\": \"PARALLEL 50 OHM WITH CALIBRATION\", \"OUTPUT_TERMINATION\": \"SERIES 50 OHM WITH CALIBRATION\", \"PACKAGE_SKEW_COMPENSATION\": \"ON\"  },\n        \"ddr3b_dq[55]\": { \"PIO_DIRECTION\": \"BIDIR\", \"DDR3B\": \"DDR3B_DQ[55]\", \"INPUT_TERMINATION\": \"PARALLEL 50 OHM WITH CALIBRATION\", \"OUTPUT_TERMINATION\": \"SERIES 50 OHM WITH CALIBRATION\", \"PACKAGE_SKEW_COMPENSATION\": \"ON\"  },\n        \"ddr3b_dq[56]\": { \"PIO_DIRECTION\": \"BIDIR\", \"DDR3B\": \"DDR3B_DQ[56]\", \"INPUT_TERMINATION\": \"PARALLEL 50 OHM WITH CALIBRATION\", \"OUTPUT_TERMINATION\": \"SERIES 50 OHM WITH CALIBRATION\", \"PACKAGE_SKEW_COMPENSATION\": \"ON\"  },\n        \"ddr3b_dq[57]\": { \"PIO_DIRECTION\": \"BIDIR\", \"DDR3B\": \"DDR3B_DQ[57]\", \"INPUT_TERMINATION\": \"PARALLEL 50 OHM WITH CALIBRATION\", \"OUTPUT_TERMINATION\": \"SERIES 50 OHM WITH CALIBRATION\", \"PACKAGE_SKEW_COMPENSATION\": \"ON\"  },\n        \"ddr3b_dq[58]\": { \"PIO_DIRECTION\": \"BIDIR\", \"DDR3B\": \"DDR3B_DQ[58]\", \"INPUT_TERMINATION\": \"PARALLEL 50 OHM WITH CALIBRATION\", \"OUTPUT_TERMINATION\": \"SERIES 50 OHM WITH CALIBRATION\", \"PACKAGE_SKEW_COMPENSATION\": \"ON\"  },\n        \"ddr3b_dq[59]\": { \"PIO_DIRECTION\": \"BIDIR\", \"DDR3B\": \"DDR3B_DQ[59]\", \"INPUT_TERMINATION\": \"PARALLEL 50 OHM WITH CALIBRATION\", \"OUTPUT_TERMINATION\": \"SERIES 50 OHM WITH CALIBRATION\", \"PACKAGE_SKEW_COMPENSATION\": \"ON\"  },\n        \"ddr3b_dq[60]\": { \"PIO_DIRECTION\": \"BIDIR\", \"DDR3B\": \"DDR3B_DQ[60]\", \"INPUT_TERMINATION\": \"PARALLEL 50 OHM WITH CALIBRATION\", \"OUTPUT_TERMINATION\": \"SERIES 50 OHM WITH CALIBRATION\", \"PACKAGE_SKEW_COMPENSATION\": \"ON\"  },\n        \"ddr3b_dq[61]\": { \"PIO_DIRECTION\": \"BIDIR\", \"DDR3B\": \"DDR3B_DQ[61]\", \"INPUT_TERMINATION\": \"PARALLEL 50 OHM WITH CALIBRATION\", \"OUTPUT_TERMINATION\": \"SERIES 50 OHM WITH CALIBRATION\", \"PACKAGE_SKEW_COMPENSATION\": \"ON\"  },\n        \"ddr3b_dq[62]\": { \"PIO_DIRECTION\": \"BIDIR\", \"DDR3B\": \"DDR3B_DQ[62]\", \"INPUT_TERMINATION\": \"PARALLEL 50 OHM WITH CALIBRATION\", \"OUTPUT_TERMINATION\": \"SERIES 50 OHM WITH CALIBRATION\", \"PACKAGE_SKEW_COMPENSATION\": \"ON\"  },\n        \"ddr3b_dq[63]\": { \"PIO_DIRECTION\": \"BIDIR\", \"DDR3B\": \"DDR3B_DQ[63]\", \"INPUT_TERMINATION\": \"PARALLEL 50 OHM WITH CALIBRATION\", \"OUTPUT_TERMINATION\": \"SERIES 50 OHM WITH CALIBRATION\", \"PACKAGE_SKEW_COMPENSATION\": \"ON\"  }\n}\n"
  },
  {
    "path": "tests/ddr3_altera/synth-ip.tcl",
    "content": "source $connectaldir/scripts/connectal-synth-avalonddr3.tcl\n"
  },
  {
    "path": "tests/ddr3_altera/testddr3.cpp",
    "content": "/* Copyright (c) 2013 Quanta Research Cambridge, Inc\n *\n * Permission is hereby granted, free of charge, to any person obtaining a\n * copy of this software and associated documentation files (the \"Software\"),\n * to deal in the Software without restriction, including without limitation\n * the rights to use, copy, modify, merge, publish, distribute, sublicense,\n * and/or sell copies of the Software, and to permit persons to whom the\n * Software is furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n * DEALINGS IN THE SOFTWARE.\n */\n#include \"dmaManager.h\"\n#include \"Ddr3TestIndication.h\"\n#include \"Ddr3TestRequest.h\"\n\nsem_t test_sem;\nunsigned int alloc_sz = 1<<10;\n\nclass Ddr3TestIndication : public Ddr3TestIndicationWrapper\n{\npublic:\n  Ddr3TestIndication(unsigned int id) : Ddr3TestIndicationWrapper(id){}\n  virtual void writeDone(uint32_t v) {\n    fprintf(stderr, \"writeDone %d\\n\", v);\n    sem_post(&test_sem);\n  }\n  virtual void readDone(uint32_t v) {\n    fprintf(stderr, \"readDone %d\\n\", v);\n    sem_post(&test_sem);\n  }\n};\n\nint main(int argc, const char **argv)\n{\n  DmaManager *dma = platformInit();\n  Ddr3TestRequestProxy *testRequest = new Ddr3TestRequestProxy(IfcNames_Ddr3TestRequestS2H);\n  Ddr3TestIndication testIndication(IfcNames_Ddr3TestIndicationH2S);\n\n  if(sem_init(&test_sem, 1, 0)){\n    fprintf(stderr, \"failed to init test_sem\\n\");\n    return -1;\n  }\n  int srcAlloc = portalAlloc(alloc_sz, 0);\n  //unsigned int *srcBuffer = (unsigned int *)portalMmap(srcAlloc, alloc_sz);\n  int ref_srcAlloc = dma->reference(srcAlloc);\n\n  testRequest->startWriteDram(ref_srcAlloc);\n  sem_wait(&test_sem);\n  testRequest->startWriteDram(ref_srcAlloc);\n  sem_wait(&test_sem);\n  return 0;\n}\n"
  },
  {
    "path": "tests/ddr_minimal/Ddr3Test.bsv",
    "content": "// Copyright (c) 2013 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\nimport Clocks::*;\nimport Vector::*;\nimport BuildVector::*;\nimport GetPut::*;\nimport Connectable::*;\nimport ClientServer::*;\nimport ConnectalMemory::*;\nimport ConnectalBramFifo::*;\nimport FIFOF::*;\nimport ConnectalMemTypes::*;\nimport MemReadEngine::*;\nimport MemWriteEngine::*;\nimport Pipe::*;\nimport AxiDdr3Controller::*;\nimport GetPutWithClocks::*;\nimport AxiMasterSlave::*;\nimport Axi4MasterSlave::*;\nimport AxiDdr3Wrapper  ::*;\nimport AxiDma::*;\nimport ConnectalConfig::*;\nimport HostInterface::*;\n\ninterface Ddr3TestRequest;\n   method Action startWriteDram(Bit#(32) sglId, Bit#(32) transferBytes);\n   method Action startReadDram(Bit#(32) sglId, Bit#(32) transferBytes);\nendinterface\n\ninterface Ddr3TestIndication;\n   method Action writeDone(Bit#(32) v);\n   method Action readDone(Bit#(32) v);\nendinterface\n\ninterface Ddr3Test;\n   interface Ddr3TestRequest request;\n   interface Ddr3Pins ddr3;\nendinterface\n\ntypedef TDiv#(Ddr3DataWidth,8) Ddr3DataBytes;\n\n// This minimal example only have one request or response flying at a time. Ensured by software.\nmodule mkDdr3Test#(HostInterface host, Ddr3TestIndication indication)(Ddr3Test);\n\n   let clock <- exposeCurrentClock();\n   let reset <- exposeCurrentReset();\n\n   Reg#(Bit#(Ddr3AddrWidth)) transferLen <- mkReg(256);\n\n   Clock clk200 = host.tsys_clk_200mhz_buf;\n\n   let ddr3Controller <- mkDdr3(clk200);\n   let idC <- mkReg(0);\n\n   FIFOF#(Bit#(32))   writeReqFifo <- mkFIFOF();\n   FIFOF#(Bit#(32))   readReqFifo <- mkFIFOF();\n\n   // Logic to handle writes\n   Reg#(Bit#(Ddr3AddrWidth)) dramWriteOffset <- mkReg(0);\n   Reg#(Bit#(Ddr3AddrWidth)) dramWriteLimit <- mkReg(0);\n   FIFOF#(Bit#(Ddr3DataWidth)) dramWriteFifo <- mkDualClockBramFIFOF(clock, reset, ddr3Controller.uiClock, ddr3Controller.uiReset);\n   FIFOF#(Axi4WriteRequest#(Ddr3AddrWidth,6)) awfifo <- mkDualClockBramFIFOF(clock, reset, ddr3Controller.uiClock, ddr3Controller.uiReset);\n   FIFOF#(Axi4WriteResponse#(6)) bfifo <- mkDualClockBramFIFOF(ddr3Controller.uiClock, ddr3Controller.uiReset, clock, reset);\n\n   rule rl_write_start;\n      let dummy <- toGet(writeReqFifo).get();\n      dramWriteOffset <= 0;\n      dramWriteLimit <= transferLen;\n   endrule\n\n   rule rl_req_aw if (dramWriteOffset < dramWriteLimit);\n      Axi4WriteRequest#(Ddr3AddrWidth,6) req = Axi4WriteRequest {\n\t address: truncate(dramWriteOffset),\n\t len: 0, // indicates 1 beat of data\n\t size: axiBusSize(valueOf(Ddr3DataWidth)),\n\t id: idC,\n\t burst: 2'b01,\n\t prot: 3'b000,   //ignored\n\t cache: 4'b0011, //ignored\n\t lock: 2'b00,    //ignored\n\t qos: 4'b0000    //ignored\n\t };\n      idC <= idC + 1;\n      awfifo.enq(req);\n      dramWriteFifo.enq(zeroExtend(dramWriteOffset));\n      dramWriteOffset <= dramWriteOffset + fromInteger(valueOf(Ddr3DataBytes));\n   endrule\n\n////////// Begin DDR clock domain \n   rule rl_awfifo;\n      let req <- toGet(awfifo).get();\n      ddr3Controller.slave.req_aw.put(req);\n   endrule\n\n   rule rl_writeDataFifo;\n      let mds <- toGet(dramWriteFifo).get();\n      ddr3Controller.slave.resp_write.put(Axi4WriteData {\n\t data: pack(mds),\n\t byteEnable: maxBound,\n\t last: 1,\n\t id: 0\n\t });\n   endrule\n\n// Response from the DDR \n  rule rl_bfifo;\n      let b <- ddr3Controller.slave.resp_b.get();\n      bfifo.enq(b);\n   endrule\n/////////// End clock domain DDR\n\n   rule rl_b;\n      let b <- toGet(bfifo).get();\n      indication.writeDone(extend(b.id));\n   endrule\n\n   // Logic to handle read\n   Reg#(Bit#(Ddr3AddrWidth)) dramReadOffset <- mkReg(0);\n   Reg#(Bit#(Ddr3AddrWidth)) dramReadLimit <- mkReg(0);\n   FIFOF#(Bit#(Ddr3DataWidth)) dramReadFifo <- mkDualClockBramFIFOF(ddr3Controller.uiClock, ddr3Controller.uiReset, clock, reset);\n   FIFOF#(Axi4ReadRequest#(Ddr3AddrWidth,6)) arfifo <- mkDualClockBramFIFOF(clock, reset, ddr3Controller.uiClock, ddr3Controller.uiReset);\n\n   rule rl_read_start;\n      let sglId <- toGet(readReqFifo).get();\n      dramReadOffset <= 0;\n      dramReadLimit <= transferLen;\n   endrule\n\n   rule rl_req_ar if (dramReadOffset < dramReadLimit);\n      Axi4ReadRequest#(Ddr3AddrWidth,6) req = Axi4ReadRequest {\n\t address: truncate(dramReadOffset),\n\t len: 0, // indicates one beat of data\n\t size: axiBusSize(valueOf(Ddr3DataWidth)),\n\t id: idC,\n\t burst: 2'b01,\n\t prot: 3'b000,   //ignored\n\t cache: 4'b0011, //ignored\n\t lock: 2'b00,    //ignored\n\t qos: 4'b0000    //ignored\n\t };\n      arfifo.enq(req);\n      idC <= idC + 1;\n      dramReadOffset <= dramReadOffset + fromInteger(valueOf(Ddr3DataBytes));\n   endrule\n\n/////// Begin DDR clock domain \n\n   rule rl_arfifo;\n      let req <- toGet(arfifo).get();\n      ddr3Controller.slave.req_ar.put(req);\n   endrule\n\n   rule rl_rdata;\n      let resp <- ddr3Controller.slave.resp_read.get();\n      Bit#(Ddr3DataWidth) data = resp.data;\n      dramReadFifo.enq(data);\n   endrule\n\n////// End DDR clock domain \n\n   rule rl_read_done;\n      let res <- toGet(dramReadFifo).get();\n      indication.readDone(res[31:0]); // Lazy here\n   endrule\n\n   interface Ddr3TestRequest request;\n      method Action startWriteDram(Bit#(32) sglId, Bit#(32) transferBytes);\n\t transferLen <= truncate(transferBytes);\n\t writeReqFifo.enq(sglId);\n      endmethod\n      method Action startReadDram(Bit#(32) sglId, Bit#(32) transferBytes);\n\t transferLen <= truncate(transferBytes);\n\t readReqFifo.enq(sglId);\n      endmethod\n   endinterface\n   interface AxiDdr3 ddr3 = ddr3Controller.ddr3;\nendmodule\n"
  },
  {
    "path": "tests/ddr_minimal/Makefile",
    "content": "CONNECTALDIR?=../..\nS2H_INTERFACES = Ddr3TestRequest:Ddr3Test.request\nH2S_INTERFACES = Ddr3Test:Ddr3TestIndication:host\n\nifneq ($(BOARD),zc706)\nifneq ($(BOARD),miniitx100)\nCONNECTALFLAGS += -D DataBusWidth=128\nendif\nendif\nCONNECTALFLAGS += -D IMPORT_HOSTIF -D XILINX_SYS_CLK\nCONNECTALFLAGS += --xci=$(IPDIR)/$(BOARD)/axiddr3/axiddr3.xci\n\nBSVFILES = Ddr3Test.bsv\nCPPFILES=testddr3.cpp\n\nPIN_TYPE = Ddr3Pins\nPIN_TYPE_INCLUDE = AxiDdr3Controller\nAUTOTOP = --interface pins:Ddr3Test.ddr3\n\ninclude $(CONNECTALDIR)/Makefile.connectal\n"
  },
  {
    "path": "tests/ddr_minimal/synth-ip.tcl",
    "content": "source board.tcl\nsource $connectaldir/scripts/connectal-synth-axiddr3.tcl\n"
  },
  {
    "path": "tests/ddr_minimal/testddr3.cpp",
    "content": "/* Copyright (c) 2013 Quanta Research Cambridge, Inc\n *\n * Permission is hereby granted, free of charge, to any person obtaining a\n * copy of this software and associated documentation files (the \"Software\"),\n * to deal in the Software without restriction, including without limitation\n * the rights to use, copy, modify, merge, publish, distribute, sublicense,\n * and/or sell copies of the Software, and to permit persons to whom the\n * Software is furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n * DEALINGS IN THE SOFTWARE.\n */\n#include \"dmaManager.h\"\n#include \"Ddr3TestIndication.h\"\n#include \"Ddr3TestRequest.h\"\n\nsem_t write_sem;\nsem_t read_sem;\nunsigned int readExpected = 0 ;\n\nclass Ddr3TestIndication : public Ddr3TestIndicationWrapper\n{\npublic:\n  Ddr3TestIndication(unsigned int id) : Ddr3TestIndicationWrapper(id){}\n  virtual void writeDone(uint32_t v) {\n    fprintf(stderr, \"writeDone %d\\n\", (int) v*64);\n    sem_post(&write_sem);\n  }\n  virtual void readDone(uint32_t v) {\n    if(v != readExpected) { fprintf(stderr, \"read %d v expecting %d\", (int) v,(int) readExpected); exit(1);}\n    readExpected += 64; \n    fprintf(stderr, \"readDone %d\\n\", v);\n    sem_post(&read_sem);\n  }\n};\n\nint main(int argc, const char **argv)\n{\n  Ddr3TestRequestProxy *testRequest = new Ddr3TestRequestProxy(IfcNames_Ddr3TestRequestS2H);\n  Ddr3TestIndication testIndication(IfcNames_Ddr3TestIndicationH2S);\n\n  if(sem_init(&write_sem, 1, 0)){\n    fprintf(stderr, \"failed to init write_sem\\n\");\n    return -1;\n  }\n  if(sem_init(&read_sem, 1, 0)){\n    fprintf(stderr, \"failed to init read_sem\\n\");\n    return -1;\n  }\n  if (1) {\n      int transferLen = 4096;\n      fprintf(stderr, \"Start writing dram\\n\");\n      testRequest->startWriteDram(0, transferLen);\n      for (int i = 0; i < transferLen; i += 64)\n\t  sem_wait(&write_sem);\n     \n      fprintf(stderr, \"Finished writing dram\\n\");\n      testRequest->startReadDram(0, transferLen);\n\n      for (int i = 0; i < transferLen; i += 64)\n          sem_wait(&read_sem);\n  }\n  return  0;\n}\n"
  },
  {
    "path": "tests/dma2bram/Makefile",
    "content": "CONNECTALDIR?=../..\nS2H_INTERFACES = TestRequest:Test.request\nH2S_INTERFACES = Test:TestIndication\nMEM_READ_INTERFACES = lTest.dmaClient\n\nBSVFILES = Test.bsv\nCPPFILES=test.cpp\n\ninclude $(CONNECTALDIR)/Makefile.connectal\n"
  },
  {
    "path": "tests/dma2bram/Test.bsv",
    "content": "// Copyright (c) 2013 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\nimport Vector::*;\nimport BuildVector::*;\nimport ClientServer::*;\nimport BRAM::*;\nimport ConnectalMemory::*;\nimport ConnectalMemTypes::*;\nimport BlueScope::*;\nimport MemReadEngine::*;\nimport MemWriteEngine::*;\nimport Dma2BRAM::*;\nimport Pipe::*;\n\ninterface TestRequest;\n   method Action startWrite(Bit#(32) sglId);\nendinterface\n\ninterface TestIndication;\n   method Action writeDone(Bit#(32) v);\nendinterface\n\ninterface Test;\n   interface TestRequest request;\n   interface Vector#(1, MemReadClient#(64)) dmaClient;\nendinterface\n\nmodule mkTest#(TestIndication indication)(Test);\n   \n   MemReadEngine#(64,64,1,1)  re <- mkMemReadEngine;\n   BRAM1Port#(Bit#(10),Bit#(8)) bram <- mkBRAM1Server(defaultValue);\n   BRAMWriter#(10,64) bramWriter <- mkBRAMWriter(2, bram.portA, re.readServers[0]);\n      \n   rule finishWrite;\n      let rv <- bramWriter.finish;\n      indication.writeDone(0);\n   endrule\n   \n   interface TestRequest request;\n      method Action startWrite(Bit#(32) sglId);\n\t bramWriter.start(sglId, 0, minBound, maxBound);\n      endmethod\n   endinterface\n   interface dmaClient = vec(re.dmaClient);\nendmodule\n"
  },
  {
    "path": "tests/dma2bram/test.cpp",
    "content": "/* Copyright (c) 2013 Quanta Research Cambridge, Inc\n *\n * Permission is hereby granted, free of charge, to any person obtaining a\n * copy of this software and associated documentation files (the \"Software\"),\n * to deal in the Software without restriction, including without limitation\n * the rights to use, copy, modify, merge, publish, distribute, sublicense,\n * and/or sell copies of the Software, and to permit persons to whom the\n * Software is furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n * DEALINGS IN THE SOFTWARE.\n */\n#include \"dmaManager.h\"\n#include \"TestIndication.h\"\n#include \"TestRequest.h\"\n\nsem_t test_sem;\nunsigned int alloc_sz = 1<<10;\n\nclass TestIndication : public TestIndicationWrapper\n{\npublic:\n  TestIndication(unsigned int id) : TestIndicationWrapper(id){}\n  virtual void writeDone(uint32_t v) {\n    fprintf(stderr, \"writeDone %d\\n\", v);\n    sem_post(&test_sem);    \n  }\n};\n\nint main(int argc, const char **argv)\n{\n  DmaManager *dma = platformInit();\n  TestRequestProxy *testRequest = new TestRequestProxy(IfcNames_TestRequestS2H);\n  TestIndication testIndication(IfcNames_TestIndicationH2S);\n\n  if(sem_init(&test_sem, 1, 0)){\n    fprintf(stderr, \"failed to init test_sem\\n\");\n    return -1;\n  }\n  int srcAlloc = portalAlloc(alloc_sz, 0);\n  //unsigned int *srcBuffer = (unsigned int *)portalMmap(srcAlloc, alloc_sz);\n  int ref_srcAlloc = dma->reference(srcAlloc);\n\n  testRequest->startWrite(ref_srcAlloc);\n  sem_wait(&test_sem);\n  testRequest->startWrite(ref_srcAlloc);\n  sem_wait(&test_sem);\n  return 0;\n}\n"
  },
  {
    "path": "tests/dram_awsf1/Axi4.bsv",
    "content": "import AxiBits::*;\nimport Axi4MasterSlave::*;\nimport FIFOF::*;\nimport ConnectalFIFO::*;\nimport GetPut::*;\n\ntypedef 64 DdrAddrWidth;\ntypedef 16 DdrIdWidth;\ntypedef 512 DdrBusWidth;\ntypedef Axi4MasterBits#(DdrAddrWidth,DdrBusWidth,DdrIdWidth,Empty) Axi4;\n\ninterface Ddr3TestRequest;\n   method Action startWriteDram(Bit#(16) id, Bit#(64) addr,\n   \t  \t \t  Bit#(32) v1, Bit#(32) v2, Bit#(32) v3, Bit#(32) v4,\n   \t  \t          Bit#(32) v5, Bit#(32) v6,Bit#(32) v7, Bit#(32) v8,\n\t\t\t  Bit#(32) v9, Bit#(32) v10, Bit#(32) v11, Bit#(32) v12,\n   \t  \t          Bit#(32) v13, Bit#(32) v14, Bit#(32) v15, Bit#(32) v16);\n   method Action startReadDram(Bit#(16) id, Bit#(64) addr);\nendinterface\n\ninterface Ddr3TestIndication;\n   method Action writeDone(Bit#(32) v);\n   method Action readDone(Bit#(16) id, Bit#(32) v1, Bit#(32) v2, Bit#(32) v3, Bit#(32) v4,\n   \t  \t          Bit#(32) v5, Bit#(32) v6,Bit#(32) v7, Bit#(32) v8,\n\t\t\t  Bit#(32) v9, Bit#(32) v10, Bit#(32) v11, Bit#(32) v12,\n   \t  \t          Bit#(32) v13, Bit#(32) v14, Bit#(32) v15, Bit#(32) v16);\n   method Action error(Bit#(32) code, Bit#(32) data);\nendinterface\n\ninterface DdrAws;\n   interface Ddr3TestRequest request;\n   interface Axi4 ddr3;\nendinterface\n\n\nmodule mkAxi4MasterBitsEmpty#(Axi4Master#(addrWidth,dataWidth,tagWidth) m)(Axi4MasterBits#(addrWidth,busDataWidth,busTagWidth,Empty))\n    provisos (Add#(dataWidth,d__,busDataWidth),\n              Div#(dataWidth,32,dataWidthWords),\n    \t      Add#(tagWidth,t__,busTagWidth),\n    \t      Add#(a__, TDiv#(dataWidth, 8), TDiv#(busDataWidth, 8)));\n\t\n\t    let arfifo <- mkCFFIFOF();\n\t    let araddrWire <- mkDWire(0);\n\t    let arburstWire <- mkDWire(0);\n\t    let arcacheWire <- mkDWire(0);\n\t    let aridWire <- mkDWire(0);\n\t    let arreadyWire <- mkDWire(False);\n\t    let arprotWire <- mkDWire(0);\n\t    let arlenWire <- mkDWire(0);\n\t    let arsizeWire <- mkDWire(0);\n\n\t    let awfifo <- mkCFFIFOF();\n\t    let awaddrWire <- mkDWire(0);\n\t    let awburstWire <- mkDWire(0);\n\t    let awcacheWire <- mkDWire(0);\n\t    let awidWire <- mkDWire(0);\n\t    let awreadyWire <- mkDWire(False);\n\t    let awprotWire <- mkDWire(0);\n\t    let awlenWire <- mkDWire(0);\n\t    let awsizeWire <- mkDWire(0);\n\n\t    let rfifo <- mkCFFIFOF();\n\t    let rdataWire <- mkDWire(0);\n\t    let rrespWire <- mkDWire(0);\n\t    let rlastWire <- mkDWire(0);\n\t    let ridWire <- mkDWire(0);\t    \n\t    let rvalidWire <- mkDWire(False);\n\n\t    let wfifo <- mkCFFIFOF();\n\t    let wdataWire <- mkDWire(0);\n\t    let widWire <- mkDWire(0);\n\t    let wstrbWire <- mkDWire(0);\n\t    let wlastWire <- mkDWire(0);\n\t    let wreadyWire <- mkDWire(False);\n\n\t    let bfifo <- mkCFFIFOF();\n\t    let bidWire <- mkDWire(0);\n\t    let brespWire <- mkDWire(0);\n\t    let bvalidWire <- mkDWire(False);\n\n\t    rule arfifo_enq;\n\t       let req <- m.req_ar.get();\n\t       arfifo.enq(req);\n\t    endrule\n\n\t    rule arwire_rule;\n\t       araddrWire <= arfifo.first.address;\n\t       arlenWire <= arfifo.first.len;\n\t       Bit#(11) dwlen = extend(arfifo.first.len) / fromInteger(valueOf(dataWidthWords));\n\t       Bit#(8) mustbeone = 8'hf;\n\t       arsizeWire <= arfifo.first.size;\n\t       arburstWire <= 2'b01; //arfifo.first.burst;\n\t       arprotWire <= 3'b000; //arfifo.first.prot;\n\t       arcacheWire <= 4'b0011; // arfifo.first.cache;\n\t       aridWire <= arfifo.first.id;\n\t    endrule\n\n\t    rule ar_handshake if (arreadyWire);\n\t      arfifo.deq();\n\t    endrule\n\n\t    rule awfifo_enq;\n\t       let req <- m.req_aw.get();\n\t       awfifo.enq(req);\n\t    endrule\n\n\t    rule awwire_rule;\n\t       awaddrWire <= awfifo.first.address;\n\t       let lenbytes = awfifo.first.len;\n\t       awlenWire <= lenbytes;\n\t       Bit#(11) dwlen = extend(lenbytes) / fromInteger(valueOf(dataWidthWords));\n\t       Bit#(4) firstBE = 4'hf;\n\t       Bit#(4) lastBE = (lenbytes > 4) ? 4'hf : 0;\n\t       awsizeWire <= awfifo.first.size;\n\t       awburstWire <= 2'b01; //awfifo.first.burst;\n\t       awprotWire <= 3'b000; //awfifo.first.prot;\n\t       awcacheWire <= 4'b0011; // awfifo.first.cache;\n\t       awidWire <= awfifo.first.id;\n\t    endrule\n\n\t    rule aw_handshake if (awreadyWire);\n\t      awfifo.deq();\n\t    endrule\n\n\t    rule rdata_put;\n\t       let data <- toGet(rfifo).get();\n\t       m.resp_read.put(data); \n\t    endrule\n\n\t    rule r_handshake if (rvalidWire);\n\t      rfifo.enq(Axi4ReadResponse {data: truncate(rdataWire),\n\t      \t\t\t\t  resp: rrespWire,\n\t\t\t\t\t  last: rlastWire,\n\t\t\t\t\t  id: ridWire });\n\t    endrule\n\n\t    rule wdata_get;\n\t       let data <- m.resp_write.get();\n\t       wfifo.enq(data);\n\t    endrule\n\n\t    rule w_handshake if (wreadyWire);\n\t      let data <- toGet(wfifo).get();\n\t      wdataWire <= extend(data.data);\n\t      wlastWire <= pack(data.last);\n\t      wstrbWire <= data.byteEnable;\n\t      widWire <= data.id;\n\t    endrule\n\n\t    rule bresp_put;\n\t       let resp <- toGet(bfifo).get();\n\t       m.resp_b.put(resp); \n\t    endrule\n\n\t    rule b_handshake if (bvalidWire);\n\t      bfifo.enq(Axi4WriteResponse {resp: brespWire,\n\t\t\t\t\t  id: bidWire });\n\t    endrule\n\n\t    interface Empty extra;\n\t    endinterface\n\n\t    method araddr = araddrWire;\n\t    method arburst = arburstWire;\n\t    method arcache = arcacheWire;\n\t    method aresetn = 1;\n\t    method arid = extend(aridWire);\n\t    method arlen = arlenWire;\n\t    // method Bit#(2)     arlock();\n\t    method arprot = arprotWire;\n\t    // method Bit#(4)     arqos();\n\t    method Action      arready(Bit#(1) v); arreadyWire <= unpack(v); endmethod\n\t    method arsize = arsizeWire;\n\t    method arvalid = pack(arfifo.notEmpty);\n\n\t    method awaddr = awaddrWire;\n\t    method awburst = awburstWire;\n\t    method awcache = awcacheWire;\n\t    method awid = extend(awidWire);\n\t    method awlen = awlenWire;\n\t    //method awlock = awlockWire;\n\t    method awprot = awprotWire;\n\t    // method Bit#(4)     awqos();\n\t    method Action      awready(Bit#(1) v); awreadyWire <= unpack(v); endmethod\n\t    method awsize = awsizeWire;\n\t    method awvalid = pack(awfifo.notEmpty);\n\n\t    method Action      bid(Bit#(busTagWidth) v); bidWire <= truncate(v); endmethod\n\t    method bready = pack(bfifo.notFull());\n\t    method Action      bresp(Bit#(2) v); brespWire <= v; endmethod\n\t    method Action      bvalid(Bit#(1) v); bvalidWire <= unpack(v); endmethod\n\n\t    method Action      rdata(Bit#(busDataWidth) v); rdataWire <= v; endmethod\n\t    method Action      rid(Bit#(busTagWidth) v); ridWire <= truncate(v); endmethod\n\t    method Action      rlast(Bit#(1) v); rlastWire <= unpack(v); endmethod\n\t    method rready = pack(rfifo.notFull());\n\t    method Action      rresp(Bit#(2) v); rrespWire <= v; endmethod\n\t    method Action      rvalid(Bit#(1) v); rvalidWire <= unpack(v); endmethod\n\n\t    method wdata = wdataWire;\n\t    method wid = extend(widWire);\n\t    method wlast = wlastWire;\n\t    method Action      wready(Bit#(1) v); wreadyWire <= unpack(v); endmethod\n\t    method wstrb = extend(wstrbWire);\n\t    method wvalid = pack(wfifo.notEmpty);\n\nendmodule\n\n\n"
  },
  {
    "path": "tests/dram_awsf1/DdrAws.bsv",
    "content": "// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\nimport Clocks::*;\nimport Vector::*;\nimport BuildVector::*;\nimport GetPut::*;\nimport Connectable::*;\nimport ClientServer::*;\nimport ConnectalMemory::*;\nimport ConnectalBramFifo::*;\nimport FIFOF::*;\nimport ConnectalMemTypes::*;\nimport MemReadEngine::*;\nimport MemWriteEngine::*;\nimport Pipe::*;\nimport AxiDdr3Controller::*;\nimport GetPutWithClocks::*;\nimport AxiMasterSlave::*;\nimport Axi4MasterSlave::*;\nimport AxiDdr3Wrapper  ::*;\nimport AxiDma::*;\nimport ConnectalConfig::*;\nimport HostInterface::*;\nimport Probe::*;\nimport Axi4::*;\n\nmodule mkDdrAws#(Ddr3TestIndication ind)(DdrAws);\n\n   Reg#(Bool) flying <- mkReg(False);\n\n   FIFOF#(Axi4ReadRequest#(DdrAddrWidth, DdrIdWidth)) fifo_req_ar <- mkFIFOF();\n   FIFOF#(Axi4ReadResponse#(DdrBusWidth, DdrIdWidth)) fifo_resp_read <- mkFIFOF();\n   FIFOF#(Axi4WriteRequest#(DdrAddrWidth, DdrIdWidth)) fifo_req_aw <- mkFIFOF();\n   FIFOF#(Axi4WriteData#(DdrBusWidth, DdrIdWidth)) fifo_resp_write <- mkFIFOF();\n   FIFOF#(Axi4WriteResponse#(DdrIdWidth)) fifo_resp_b <- mkFIFOF();\n\n\n   let aximaster = (interface Axi4Master;\n       \t\t   \t      interface req_ar = toGet(fifo_req_ar);\n\t\t\t      interface resp_read = toPut(fifo_resp_read);\n\t\t\t      interface req_aw = toGet(fifo_req_aw);\n\t\t\t      interface resp_write = toGet(fifo_resp_write);\n\t\t\t      interface resp_b = toPut(fifo_resp_b);\n\t\tendinterface);\n\n   Axi4 ddr3bits <- mkAxi4MasterBitsEmpty(aximaster);\n\n   rule gotRead;\n   \tfifo_resp_read.deq();\n\tlet respread  = fifo_resp_read.first();\n\tlet resp = respread.data;\n\tlet id = respread.id;\n\tlet last = respread.last;\n\tlet error = respread.resp;\n\tif (error != 0 || last != 1) begin\n\t   ind.error(zeroExtend(error),zeroExtend(id));\n\tend\n\tflying <= False;\n\tind.readDone(id,resp[31:0],resp[63:32],resp[95:64],resp[127:96],\n\t\t     resp[159:128],resp[191:160],resp[223:192],resp[255:224],\n\t\t     resp[287:256],resp[319:288],resp[351:320],resp[383:352],\n\t\t     resp[415:384],resp[447:416],resp[479:448],resp[511:480]);\n   endrule\n\n   rule gotWrite;\n   \tfifo_resp_b.deq();\n\tlet resp = fifo_resp_b.first();\n\tlet error = resp.resp;\n\tlet id = resp.id;\n\tflying <= False;\n\tif (error != 0) begin\n\t   ind.error(zeroExtend(error), zeroExtend(id));\n\tend\n\tind.writeDone(zeroExtend(id));\n   endrule\n\n// len = nb pack512 -1\n// size axiBusSize\n// burst: 1\n// prot: 0\n// cache:3\n// lock: 0\n// qos: 0\n// resp: 0 if no error\n// last: 1 for the last burst.\n\n   interface Ddr3TestRequest request;\n      method Action startWriteDram(Bit#(16) id, Bit#(64) address,\n         \t  \t \t  Bit#(32) v1, Bit#(32) v2, Bit#(32) v3, Bit#(32) v4,\n\t\t\t\t  Bit#(32) v5, Bit#(32) v6,Bit#(32) v7, Bit#(32) v8,\n\t\t\t  \t  Bit#(32) v9, Bit#(32) v10, Bit#(32) v11, Bit#(32) v12,\n \t\t\t\t  Bit#(32) v13, Bit#(32) v14, Bit#(32) v15, Bit#(32) v16) if (!flying);\n      \t     flying <= True;\n\t     fifo_req_aw.enq(Axi4WriteRequest{address: address,\n\t     \t\t\t\t      len: 0,\n\t\t\t\t\t      size: 6,\n\t\t\t\t\t      burst: 1,\n\t\t\t\t\t      prot: 0,\n\t\t\t\t\t      cache: 3,\n\t\t\t\t\t      id: id,\n\t\t\t\t\t      lock: 0,\n\t\t\t\t\t      qos: 0\n\t\t\t\t\t      });\n\t     fifo_resp_write.enq(Axi4WriteData{data: {v16,v15,v14,v13,v12,v11,v10,v9,v8,v7,v6,v5,v4,v3,v2,v1},\n\t     \t\t\t\t       byteEnable: maxBound,\n\t\t\t\t\t       last: 1,\n\t\t\t\t\t       id: id});\n      endmethod\n\n      method Action startReadDram(Bit#(16) id, Bit#(64) address) if (!flying);\n      \t     flying <= True;\n\t     fifo_req_ar.enq(Axi4ReadRequest{address: address,\n\t     \t\t\t\t     len: 0,\n\t\t\t\t\t     size: 6,\n\t\t\t\t\t     burst: 1,\n\t\t\t\t\t     prot: 0,\n\t\t\t\t\t     cache: 3,\n\t\t\t\t\t     id: id,\n\t\t\t\t\t     lock: 0,\n\t\t\t\t\t     qos: 0\n\t\t\t\t\t     });\n      endmethod\n   endinterface\n\n   interface ddr3 = ddr3bits;\nendmodule\n"
  },
  {
    "path": "tests/dram_awsf1/Makefile",
    "content": "CONNECTALDIR?=../..\nS2H_INTERFACES = Ddr3TestRequest:DdrAws.request\nH2S_INTERFACES = DdrAws:Ddr3TestIndication\n\nBSVFILES= \\\n    DdrAws.bsv\\\n    Axi4.bsv\n\nCPPFILES= testddr3.cpp\n\n\nPIN_TYPE = Axi4\nPIN_TYPE_INCLUDE = Axi4\nAUTOTOP = --interface pins:DdrAws.ddr3\n\nCONNECTALFLAGS += -D AWSF1_DDR_A\n\ninclude $(CONNECTALDIR)/Makefile.connectal\n"
  },
  {
    "path": "tests/dram_awsf1/testddr3.cpp",
    "content": "/*\n * Permission is hereby granted, free of charge, to any person obtaining a\n * copy of this software and associated documentation files (the \"Software\"),\n * to deal in the Software without restriction, including without limitation\n * the rights to use, copy, modify, merge, publish, distribute, sublicense,\n * and/or sell copies of the Software, and to permit persons to whom the\n * Software is furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n * DEALINGS IN THE SOFTWARE.\n */\n\n#include \"Ddr3TestIndication.h\"\n#include \"Ddr3TestRequest.h\"\n\nsem_t write_sem;\nsem_t read_sem;\nuint32_t value = 0;\n\nclass Ddr3TestIndication : public Ddr3TestIndicationWrapper\n{\npublic:\n  Ddr3TestIndication(unsigned int id) : Ddr3TestIndicationWrapper(id){}\n  virtual void writeDone(uint32_t id) {\n   // fprintf(stderr, \"writeDone id %d\\n\", id);\n    sem_post(&write_sem);\n  }\n  virtual void readDone(uint16_t v,\n\t\t\tuint32_t v1,uint32_t v2,uint32_t v3,uint32_t v4,\n\t\t\tuint32_t v5,uint32_t v6,uint32_t v7,uint32_t v8,\n\t\t\tuint32_t v9,uint32_t v10,uint32_t v11,uint32_t v12,\n\t\t\tuint32_t v13,uint32_t v14,uint32_t v15,uint32_t v16\n\t\t\t) {\n    fprintf(stderr, \"readDone %d\\n\", v);\n    fprintf(stderr, \"    readValue %d\\n\", v1 );\n    fprintf(stderr, \"    readValue %d\\n\", v2 );\n    fprintf(stderr, \"    readValue %d\\n\", v3 );\n    fprintf(stderr, \"    readValue %d\\n\", v4 );\n    fprintf(stderr, \"    readValue %d\\n\", v5 );\n    fprintf(stderr, \"    readValue %d\\n\", v6 );\n    fprintf(stderr, \"    readValue %d\\n\", v7 );\n    fprintf(stderr, \"    readValue %d\\n\", v8 );\n    fprintf(stderr, \"    readValue %d\\n\", v9 );\n    fprintf(stderr, \"    readValue %d\\n\", v10);\n    fprintf(stderr, \"    readValue %d\\n\", v11);\n    fprintf(stderr, \"    readValue %d\\n\", v12);\n    fprintf(stderr, \"    readValue %d\\n\", v13);\n    fprintf(stderr, \"    readValue %d\\n\", v14);\n    fprintf(stderr, \"    readValue %d\\n\", v15);\n    fprintf(stderr, \"    readValue %d\\n\", v16);\n//    if (!(value == v1)) {fprintf(stderr, \"Value problem expected %d\",value); exit(1);}\n    sem_post(&read_sem);\n  }\n  virtual void error(uint32_t code, uint32_t data){\n    fprintf(stderr, \"Error code %d, data %d\", code, data);\n    exit(1);\n  }\n};\n\nint main(int argc, const char **argv)\n{\n  Ddr3TestRequestProxy *testRequest = new Ddr3TestRequestProxy(IfcNames_Ddr3TestRequestS2H);\n  Ddr3TestIndication testIndication(IfcNames_Ddr3TestIndicationH2S);\n  if(sem_init(&write_sem, 1, 0)){\n    fprintf(stderr, \"failed to init write_sem\\n\");\n    return -1;\n  }\n  if(sem_init(&read_sem, 1, 0)){\n    fprintf(stderr, \"failed to init read_sem\\n\");\n    return -1;\n  }\n\n  for (uint64_t i = 0; i< 1000000; i += 1){\n    if (i%10000 == 0) printf(\"%d\",(int) i);\n    value = 512*i;\n    uint64_t address = i;\n    uint16_t id = i;\n    fflush(stdout);\n    testRequest->startWriteDram(id, address, value,value+32,value+64, value+96,\n\t\t\t\tvalue+4*32,value+5*32,value+6*32, value+7*32,\n\t\t\t\tvalue+8*32,value+9*32,value+10*32, value+11*32,\n\t\t\t\tvalue+12*32,value+13*32,value+14*32, value+15*32);\n    sem_wait(&write_sem);\n  /*  testRequest->startReadDram(2, address);\n    sem_wait(&read_sem);*/\n  }\n  return 0;\n}\n"
  },
  {
    "path": "tests/echosoft2/EchoId.bsv",
    "content": "\n// Copyright (c) 2013 Nokia, Inc.\n// Copyright (c) 2013 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\nimport FIFO::*;\n//import Vector::*;\n\ninterface EchoIndication;\n    method Action heard(Bit#(32) id, Bit#(32) v);\n    method Action heard2(Bit#(32) id, Bit#(16) a, Bit#(16) b);\nendinterface\n\ninterface EchoRequest;\n   method Action say(Bit#(32) id, Bit#(32) v);\n   method Action say2(Bit#(32) id, Bit#(16) a, Bit#(16) b);\n   method Action setLeds(Bit#(32) id, Bit#(8) v);\nendinterface\n\ninterface EchoId;\n   interface EchoRequest request;\nendinterface\n\ntypedef struct {\n\tBit#(32) id;\n\tBit#(32) v;\n} EchoPair1 deriving (Bits);\n\ntypedef struct {\n\tBit#(32) id;\n\tBit#(16) a;\n\tBit#(16) b;\n} EchoPair2 deriving (Bits);\n\nmodule mkEchoId#(EchoIndication indication)(EchoId);\n\n    FIFO#(EchoPair1) delay1 <- mkSizedFIFO(8);\n    FIFO#(EchoPair2) delay2 <- mkSizedFIFO(8);\n\n    rule heard;\n        delay1.deq;\n        indication.heard(delay1.first.id, delay1.first.v);\n    endrule\n\n    rule heard2;\n        delay2.deq;\n        indication.heard2(delay2.first.id, delay2.first.b, delay2.first.a);\n    endrule\n   \n   interface EchoRequest request;\n      method Action say(Bit#(32) id, Bit#(32) v);\n\t delay1.enq(EchoPair1 { id: id, v: v});\n      endmethod\n      \n      method Action say2(Bit#(32) id, Bit#(16) a, Bit#(16) b);\n\t delay2.enq(EchoPair2 { id: id, a: a, b: b});\n      endmethod\n      \n      method Action setLeds(Bit#(32) id, Bit#(8) v);\n      endmethod\n   endinterface\nendmodule\n"
  },
  {
    "path": "tests/echosoft2/Makefile",
    "content": "CONNECTALDIR?=../..\nS2H_INTERFACES = EchoRequest:EchoId.request SwallowRequest:Swallow.request\nH2S_INTERFACES = EchoId:EchoIndication\n\nBSVFILES = EchoId.bsv ../../examples/echosoft/Swallow.bsv\nCPPFILES=testecho.cpp\nCPPFILES2=daemon.cpp\nAUTOTOP = --portname IfcNames_EchoIndication2H2S --portname IfcNames_EchoRequest2S2H\n\ninclude $(CONNECTALDIR)/Makefile.connectal\n"
  },
  {
    "path": "tests/echosoft2/daemon.cpp",
    "content": "/* Copyright (c) 2014 Quanta Research Cambridge, Inc\n *\n * Permission is hereby granted, free of charge, to any person obtaining a\n * copy of this software and associated documentation files (the \"Software\"),\n * to deal in the Software without restriction, including without limitation\n * the rights to use, copy, modify, merge, publish, distribute, sublicense,\n * and/or sell copies of the Software, and to permit persons to whom the\n * Software is furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n * DEALINGS IN THE SOFTWARE.\n */\n#include <stdio.h>\n#include <netdb.h>\n#include \"sock_utils.h\"\n#include \"EchoRequest.h\"\n#include \"EchoIndication.h\"\n\nEchoRequestProxy *echoRequestProxy;\nEchoIndicationProxy *sIndicationProxy;\nEchoIndicationProxy *sIndicationProxy2;\nstatic int daemon_trace = 1;\n\nclass EchoIndication : public EchoIndicationWrapper\n{\npublic:\n    void heard(uint32_t id, uint32_t v) {\n        if (daemon_trace)\n        fprintf(stderr, \"daemon: heard an echo: %u %u\\n\", id, v);\n\t\tif (id == 1) {\n        \tsIndicationProxy->heard(id, v);\n\t\t} else if (id == 2) {\n        \tsIndicationProxy2->heard(id, v);\n\t\t} else {\n\t\t\tfprintf (stderr, \"id is wrong (%u)\", id);\n\t\t}\n    }\n    void heard2(uint32_t id, uint16_t a, uint16_t b) {\n        if (daemon_trace)\n        fprintf(stderr, \"daemon: heard an echo2: %u %d %d\\n\", id, a, b);\n\t\tif (id == 1) {\n        \tsIndicationProxy->heard2(id, a, b);\n\t\t} else if (id == 2) {\n        \tsIndicationProxy2->heard2(id, a, b);\n\t\t} else {\n\t\t\tfprintf (stderr, \"id is wrong (%u)\", id);\n\t\t}\n    }\n    EchoIndication(unsigned int id, PortalTransportFunctions *item, void *param) : EchoIndicationWrapper(id, item, param) {}\n};\n\nclass EchoRequest : public EchoRequestWrapper\n{\npublic:\n    void say (const uint32_t id, const uint32_t v ) {\n        if (daemon_trace)\n        fprintf(stderr, \"daemon[%s:%d] %u %u\\n\", __FUNCTION__, __LINE__, id, v);\n        echoRequestProxy->say(id, v);\n    }\n    void say2 (const uint32_t id, const uint16_t a, const uint16_t b ) {\n        if (daemon_trace)\n        fprintf(stderr, \"daemon[%s:%d] %u %u %u\\n\", __FUNCTION__, __LINE__, id, a, b);\n        echoRequestProxy->say2(id, a, b);\n    }\n    void setLeds (const uint32_t id, const uint8_t v ) {\n        fprintf(stderr, \"daemon[%s:%d]\\n\", __FUNCTION__, __LINE__);\n        echoRequestProxy->setLeds(id, v);\n        sleep(1);\n        exit(1);\n    }\n    EchoRequest(unsigned int id, PortalTransportFunctions *item, void *param) : EchoRequestWrapper(id, item, param) {}\n};\n\nint main(int argc, const char **argv)\n{\n\n    sIndicationProxy = new EchoIndicationProxy(IfcNames_EchoIndicationH2S, &transportSocketResp, NULL);\n    sIndicationProxy2 = new EchoIndicationProxy(IfcNames_EchoIndication2H2S, &transportSocketResp, NULL);\n    EchoRequest sRequest(IfcNames_EchoRequestS2H, &transportSocketResp, NULL);\n    EchoRequest sRequest2(IfcNames_EchoRequest2S2H, &transportSocketResp, NULL);\n    EchoIndication echoIndication(IfcNames_EchoIndicationH2S, NULL, NULL);\n    echoRequestProxy = new EchoRequestProxy(IfcNames_EchoRequestS2H);\n\n    printf(\"[%s:%d] daemon sleeping...\\n\", __FUNCTION__, __LINE__);\n    while(1)\n        sleep(100);\n    return 0;\n}\n"
  },
  {
    "path": "tests/echosoft2/testecho.cpp",
    "content": "/* Copyright (c) 2014 Quanta Research Cambridge, Inc\n *\n * Permission is hereby granted, free of charge, to any person obtaining a\n * copy of this software and associated documentation files (the \"Software\"),\n * to deal in the Software without restriction, including without limitation\n * the rights to use, copy, modify, merge, publish, distribute, sublicense,\n * and/or sell copies of the Software, and to permit persons to whom the\n * Software is furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n * DEALINGS IN THE SOFTWARE.\n */\n#include <stdio.h>\n#include <netdb.h>\n#include <pthread.h>    /* POSIX Threads */\n#include \"EchoRequest.h\"\n#include \"EchoIndication.h\"\n\n\n/****************** client1 ******************/\nEchoRequestProxy *sRequestProxy;\nstatic sem_t sem_heard;\n\nclass EchoIndication : public EchoIndicationWrapper\n{\npublic:\n    void heard(uint32_t id, uint32_t v) {\n        fprintf(stderr, \"[client1] heard an s: %d\\n\", v);\n        sRequestProxy->say2(id, v, 2*v);\n    }\n    void heard2(uint32_t id, uint16_t a, uint16_t b) {\n        sem_post(&sem_heard);\n        //fprintf(stderr, \"heard an s2: %ld %ld\\n\", a, b);\n    }\n    EchoIndication(unsigned int id, PortalTransportFunctions *item, void *param) : EchoIndicationWrapper(id, item, param) {}\n};\n\nEchoIndication *sIndication;\n\nstatic void call_say(int v)\n{\n    printf(\"[client1] [%s:%d] %d\\n\", __FUNCTION__, __LINE__, v);\n    sRequestProxy->say(1, v);\n    sem_wait(&sem_heard);\n}\n\nstatic void call_say2(int v, int v2)\n{\n    printf(\"[client1] [%s:%d] %d\\n\", __FUNCTION__, __LINE__, v);\n    sRequestProxy->say2(1, v, v2);\n    sem_wait(&sem_heard);\n}\n\nvoid* client1 (void *ptr)\n{\n    int v = 42;\n    fprintf(stderr, \"[client1] Saying %d\\n\", v);\n    call_say(v);\n    call_say(v*5);\n    call_say(v*17);\n    call_say(v*93);\n    call_say2(v, v*3);\n    fprintf(stderr, \"[client1] sleeping...\\n\");\n    portal_disconnect(&sRequestProxy->pint);\n    sleep(5);\n    pthread_exit(0); /* exit */\n}\n\n\n/****************** client2 ******************/\nEchoRequestProxy *sRequestProxy2;\nstatic sem_t sem_heard2;\n\nclass EchoIndication2 : public EchoIndicationWrapper\n{\npublic:\n    void heard(uint32_t id, uint32_t v) {\n        fprintf(stderr, \"[client2] heard an s: %d\\n\", v);\n        sRequestProxy2->say2(id, v, 2*v);\n    }\n    void heard2(uint32_t id, uint16_t a, uint16_t b) {\n        sem_post(&sem_heard2);\n        //fprintf(stderr, \"heard an s2: %ld %ld\\n\", a, b);\n    }\n    EchoIndication2(unsigned int id, PortalTransportFunctions *item, void *param) : EchoIndicationWrapper(id, item, param) {}\n};\n\nEchoIndication2 *sIndication2;\n\nstatic void call2_say(int v)\n{\n    printf(\"[client2] [%s:%d] %d\\n\", __FUNCTION__, __LINE__, v);\n    sRequestProxy2->say(2, v);\n    sem_wait(&sem_heard2);\n}\n\nstatic void call2_say2(int v, int v2)\n{\n    printf(\"[client2] [%s:%d] %d\\n\", __FUNCTION__, __LINE__, v);\n    sRequestProxy2->say2(2, v, v2);\n    sem_wait(&sem_heard2);\n}\n\nvoid* client2 (void *ptr)\n{\n    int v = 42;\n    fprintf(stderr, \"[client2] Saying2 %d\\n\", v);\n    call2_say(v);\n    call2_say(v);\n    call2_say(v*5);\n    call2_say(v*17);\n    call2_say(v*93);\n    call2_say2(v, v*3);\n    fprintf(stderr, \"[client2] sleeping...\\n\");\n    portal_disconnect(&sRequestProxy2->pint);\n    sleep(5);\n    pthread_exit(0); /* exit */\n}\n\nint main(int argc, const char **argv)\n{\n    pthread_t thread1, thread2;  /* thread variables */\n\n    printf (\"*** Two clients version ***\\n\");\n    sleep(2);\n    sIndication = new EchoIndication(IfcNames_EchoIndicationH2S, &transportSocketInit, NULL);\n    sRequestProxy = new EchoRequestProxy(IfcNames_EchoRequestS2H, &transportSocketInit, NULL);\n    sIndication2 = new EchoIndication2(IfcNames_EchoIndication2H2S, &transportSocketInit, NULL);\n    sRequestProxy2 = new EchoRequestProxy(IfcNames_EchoRequest2S2H, &transportSocketInit, NULL);\n\n    pthread_create (&thread1, NULL, client1, (void*)NULL);\n    pthread_create (&thread2, NULL, client2, (void*)NULL);\n    printf (\"main: before pthread_join\\n\");\n    pthread_join (thread1, NULL);\n    pthread_join (thread2, NULL);\n    printf (\"main: done\\n\");\n    exit(0);\n}\n\n#ifdef COMMENT\nint main(int argc, const char **argv)\n{\n    PortalSocketParam param;\n\n    printf (\"*** version 2 ***\\n\");\n    // Client 1\n    EchoIndication *sIndication = new EchoIndication(IfcNames_EchoIndication, &transportSocketInit, NULL);\n    sRequestProxy = new EchoRequestProxy(IfcNames_EchoRequest, &transportSocketInit, NULL);\n    // Client 2\n    EchoIndication *sIndication2 = new EchoIndication(IfcNames_EchoIndication2, &transportSocketInit, NULL);\n    sRequestProxy2 = new EchoRequestProxy(IfcNames_EchoRequest2, &transportSocketInit, NULL);\n\n    int v = 42;\n    fprintf(stderr, \"Saying %d\\n\", v);\n    call_say(v);\n    call_say(v*5);\n    call_say(v*17);\n    call_say(v*93);\n    call_say2(v, v*3);\n    printf(\"TEST TYPE: SEM\\n\");\n    //sRequestProxy->setLeds(9);\n    printf (\"-----------------------\\n\");\n    call2_say(v);\n    call2_say(v);\n    call2_say(v*5);\n    call2_say(v*17);\n    call2_say(v*93);\n    call2_say2(v, v*3);\n    //freeaddrinfo(param.addr);\n    return 0;\n}\n#endif\n"
  },
  {
    "path": "tests/fastecho/FastEcho.bsv",
    "content": "// Copyright (c) 2017 Connectal Project\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\ninterface FastEchoIndicationA;\n    method Action indication(Bit#(64) a, Bit#(64) b, Bit#(64) c, Bit#(64) d);\nendinterface\n\ninterface FastEchoRequestA;\n    method Action request(Bit#(64) a, Bit#(64) b, Bit#(64) c, Bit#(64) d);\nendinterface\n\ninterface FastEchoIndicationB;\n    method Action indication(Bit#(64) a, Bit#(64) b, Bit#(64) c, Bit#(64) d);\nendinterface\n\ninterface FastEchoRequestB;\n    method Action request(Bit#(64) a, Bit#(64) b, Bit#(64) c, Bit#(64) d);\nendinterface\n\ninterface FastEchoIndicationC;\n    method Action indication(Bit#(64) a, Bit#(64) b, Bit#(64) c, Bit#(64) d);\nendinterface\n\ninterface FastEchoRequestC;\n    method Action request(Bit#(64) a, Bit#(64) b, Bit#(64) c, Bit#(64) d);\nendinterface\n\ninterface FastEchoIndicationD;\n    method Action indication(Bit#(64) a, Bit#(64) b, Bit#(64) c, Bit#(64) d);\nendinterface\n\ninterface FastEchoRequestD;\n    method Action request(Bit#(64) a, Bit#(64) b, Bit#(64) c, Bit#(64) d);\nendinterface\n\ninterface FastEcho;\n   interface FastEchoRequestA requestA;\n   interface FastEchoRequestB requestB;\n   interface FastEchoRequestC requestC;\n   interface FastEchoRequestD requestD;\nendinterface\n\nmodule mkFastEcho#(\n            FastEchoIndicationA indicationA,\n            FastEchoIndicationB indicationB,\n            FastEchoIndicationC indicationC,\n            FastEchoIndicationD indicationD\n        )(FastEcho);\n    Reg#(Bool)     validDataA <- mkReg(False);\n    Reg#(Bit#(64)) aRegA      <- mkReg(0);\n    Reg#(Bit#(64)) bRegA      <- mkReg(0);\n    Reg#(Bit#(64)) cRegA      <- mkReg(0);\n    Reg#(Bit#(64)) dRegA      <- mkReg(0);\n\n    Reg#(Bool)     validDataB <- mkReg(False);\n    Reg#(Bit#(64)) aRegB      <- mkReg(0);\n    Reg#(Bit#(64)) bRegB      <- mkReg(0);\n    Reg#(Bit#(64)) cRegB      <- mkReg(0);\n    Reg#(Bit#(64)) dRegB      <- mkReg(0);\n\n    Reg#(Bool)     validDataC <- mkReg(False);\n    Reg#(Bit#(64)) aRegC      <- mkReg(0);\n    Reg#(Bit#(64)) bRegC      <- mkReg(0);\n    Reg#(Bit#(64)) cRegC      <- mkReg(0);\n    Reg#(Bit#(64)) dRegC      <- mkReg(0);\n\n    Reg#(Bool)     validDataD <- mkReg(False);\n    Reg#(Bit#(64)) aRegD      <- mkReg(0);\n    Reg#(Bit#(64)) bRegD      <- mkReg(0);\n    Reg#(Bit#(64)) cRegD      <- mkReg(0);\n    Reg#(Bit#(64)) dRegD      <- mkReg(0);\n\n    rule sendIndicationA(validDataA);\n        indicationA.indication(aRegA, bRegA, cRegA, dRegA);\n        validDataA <= False;\n    endrule\n    rule sendIndicationB(validDataB);\n        indicationB.indication(aRegB, bRegB, cRegB, dRegB);\n        validDataB <= False;\n    endrule\n    rule sendIndicationC(validDataC);\n        indicationC.indication(aRegC, bRegC, cRegC, dRegC);\n        validDataC <= False;\n    endrule\n    rule sendIndicationD(validDataD);\n        indicationD.indication(aRegD, bRegD, cRegD, dRegD);\n        validDataD <= False;\n    endrule\n\n    interface FastEchoRequestA requestA;\n        method Action request(Bit#(64) a, Bit#(64) b, Bit#(64) c, Bit#(64) d) if (!validDataA);\n            validDataA <= True;\n            aRegA <= a;\n            bRegA <= b;\n            cRegA <= c;\n            dRegA <= d;\n        endmethod\n    endinterface\n    interface FastEchoRequestB requestB;\n        method Action request(Bit#(64) a, Bit#(64) b, Bit#(64) c, Bit#(64) d) if (!validDataB);\n            validDataB <= True;\n            aRegB <= a;\n            bRegB <= b;\n            cRegB <= c;\n            dRegB <= d;\n        endmethod\n    endinterface\n    interface FastEchoRequestC requestC;\n        method Action request(Bit#(64) a, Bit#(64) b, Bit#(64) c, Bit#(64) d) if (!validDataC);\n            validDataC <= True;\n            aRegC <= a;\n            bRegC <= b;\n            cRegC <= c;\n            dRegC <= d;\n        endmethod\n    endinterface\n    interface FastEchoRequestD requestD;\n        method Action request(Bit#(64) a, Bit#(64) b, Bit#(64) c, Bit#(64) d) if (!validDataD);\n            validDataD <= True;\n            aRegD <= a;\n            bRegD <= b;\n            cRegD <= c;\n            dRegD <= d;\n        endmethod\n    endinterface\nendmodule\n"
  },
  {
    "path": "tests/fastecho/Makefile",
    "content": "CONNECTALDIR?=../..\n\nS2H_INTERFACES = \\\n\tFastEchoRequestA:FastEcho.requestA \\\n\tFastEchoRequestB:FastEcho.requestB \\\n\tFastEchoRequestC:FastEcho.requestC \\\n\tFastEchoRequestD:FastEcho.requestD \\\n\nH2S_INTERFACES = \\\n\tFastEcho:FastEchoIndicationA \\\n\tFastEcho:FastEchoIndicationB \\\n\tFastEcho:FastEchoIndicationC \\\n\tFastEcho:FastEchoIndicationD \\\n\nBSVFILES = FastEcho.bsv\nCPPFILES = testfastecho.cpp\n\n# This matches the frequency of the original design where the bug was found\nCONNECTALFLAGS += --mainclockperiod=32\nCONNECTALFLAGS += -D GET_PUT_WITH_CLOCKS_USE_XILINX_FIFO\nCONNECTALFLAGS += --xci=$(IPDIR)/$(BOARD)/dual_clock_axis_fifo_32x8/dual_clock_axis_fifo_32x8.xci\n\ninclude $(CONNECTALDIR)/Makefile.connectal\n\n"
  },
  {
    "path": "tests/fastecho/about_this_test.txt",
    "content": "This test reproduces the bug reported in issue #133 on github.\n    https://github.com/cambridgehackers/connectal/issues/133\n\nWhen this design is built for kc705g2 and run on FPGA, it typically stalls\nafter a few thousand requests and indications.\n"
  },
  {
    "path": "tests/fastecho/synth-ip.tcl",
    "content": "source \"board.tcl\" \nsource \"$connectaldir/../fpgamake/tcl/ipcore.tcl\"\n\nif {[version -short] >= \"2016.1\"} {\n    set dual_clock_axis_fifo_version 13.1\n} else {\n    set dual_clock_axis_fifo_version 13.0\n}\n\nfpgamake_ipcore fifo_generator $dual_clock_axis_fifo_version dual_clock_axis_fifo_32x8 [list \\\n                           config.interface_type {axi_stream} \\\n                           config.clock_type_axi {independent_clock} \\\n                           config.tdata_num_bytes {4} \\\n                           config.tuser_width {0} \\\n                           config.enable_tlast {true} \\\n                           config.has_tkeep {true} \\\n                           config.fifo_application_type_axis {data_fifo} \\\n                           config.reset_type {asynchronous_reset} \\\n                           ]\n\n"
  },
  {
    "path": "tests/fastecho/testfastecho.cpp",
    "content": "/* Copyright (c) 2017 Connectal Project\n *\n * Permission is hereby granted, free of charge, to any person obtaining a\n * copy of this software and associated documentation files (the \"Software\"),\n * to deal in the Software without restriction, including without limitation\n * the rights to use, copy, modify, merge, publish, distribute, sublicense,\n * and/or sell copies of the Software, and to permit persons to whom the\n * Software is furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n * DEALINGS IN THE SOFTWARE.\n */\n\n#include <errno.h>\n#include <stdio.h>\n#include <iostream>\n#include \"FastEchoIndicationA.h\"\n#include \"FastEchoRequestA.h\"\n#include \"GeneratedTypes.h\"\n\nclass FastEcho : public FastEchoIndicationAWrapper\n{\n    public:\n        FastEcho(unsigned int indicationId, unsigned int requestId)\n                : FastEchoIndicationAWrapper(indicationId),\n                  fastEchoRequestProxy(requestId) {\n            sem_init(&sem, 1, 0);\n        }\n\n        virtual void indication(uint64_t a, uint64_t b, uint64_t c, uint64_t d) {\n            aResp = a;\n            bResp = b;\n            cResp = c;\n            dResp = d;\n            sem_post(&sem);\n        }\n\n        bool doEcho(uint64_t a, uint64_t b, uint64_t c, uint64_t d) {\n            fastEchoRequestProxy.request(a, b, c, d);\n            sem_wait(&sem);\n            if (aResp != a || bResp != b || cResp != c || dResp != d) {\n                std::cerr << \"ERROR: echo failed\" << std::endl;\n                return false;\n            } else {\n                return true;\n            }\n        }\n\n    private:\n        FastEchoRequestAProxy fastEchoRequestProxy;\n        sem_t sem;\n        uint64_t aResp, bResp, cResp, dResp;\n};\n\nint main(int argc, const char **argv)\n{\n    long actualFrequency = 0;\n    long requestedFrequency = 1e9 / MainClockPeriod;\n\n    int status = setClockFrequency(0, requestedFrequency, &actualFrequency);\n    fprintf(stderr, \"Requested main clock frequency %5.2f, actual clock frequency %5.2f MHz status=%d errno=%d\\n\",\n\t    (double)requestedFrequency * 1.0e-6,\n\t    (double)actualFrequency * 1.0e-6,\n\t    status, (status != 0) ? errno : 0);\n\n    FastEcho fastEcho(IfcNames_FastEchoIndicationAH2S, IfcNames_FastEchoRequestAS2H);\n\n    for (uint64_t i = 0 ; i < 100000 ; i++) {\n        if (i % 1000 == 0) {\n            std::cout << \"i = \" << i << std::endl;\n        }\n        fastEcho.doEcho(i, i + 10, i ^ 2510, i >> 32);\n    }\n\n    std::cout << \"Done\" << std::endl;\n\n    return 0;\n}\n"
  },
  {
    "path": "tests/float/FloatTest.bsv",
    "content": "// Copyright (c) 2015 The Connectal Project\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\nimport FloatingPoint::*;\nimport StmtFSM::*;\nimport FShow::*;\n\nmodule mkFloatTestBench(Empty);\n   let once <- mkOnce(action\n      Real re = 3.14159;\n      $display(\"Real 0x%x %f\", fromReal(re), re);\n      //not supported: $display(fshow(re));\n      Float fl = 3.14159;\n      //not supported: $display(\"Float 0x%x %f\", pack(fl), $bitstoreal(pack(fl)));\n      $display(\"Float 0x%x %f\", pack(fl), fl);\n      $display(fshow(fl));\n      Double doub = 3.14159;\n      $display(\"Double 0x%x %f\", pack(doub), $bitstoreal(pack(doub)));\n      $display(fshow(doub));\n      $finish;\n      endaction);\n\n   rule foobar;\n      once.start();\n   endrule\n\nendmodule\n"
  },
  {
    "path": "tests/float/Makefile",
    "content": "CONNECTALDIR?=../..\n\nrun: floatTestBench\n\t./floatTestBench\n\nctest:\n\tgcc -o ftest ftest.c\n\t./ftest\n\trm -f ftest\n\nfloatTestBench: FloatTest.bsv\n\tmkdir -p obj\n\tbsc --show-schedule -sim -info-dir obj -bdir obj -p +:$(CONNECTALDIR)/lib/bsv -g mkFloatTestBench -u $<\n\tbsc --show-schedule -sim -info-dir obj -bdir obj -e mkFloatTestBench -o floatTestBench\n\nclean:\n\trm -rf floatTestBench* mkFloatTestBench.* model_mkFloatTestBench.* dump.vcd obj\n"
  },
  {
    "path": "tests/float/ftest.c",
    "content": "#include <stdio.h>\n\nint main()\n{\n    union {\n        float f;\n        unsigned int i;\n    } dfloat;\n    union {\n        double f;\n        unsigned long i;\n    } ddouble;\n\n    printf(\"[%s:%d] sizeof(float) %ld sizeof(double) %ld\\n\", __FUNCTION__, __LINE__, sizeof(float), sizeof(double));\n    dfloat.i = 0x3f60be97;\n    printf(\"[%s:%d] f %f\\n\", __FUNCTION__, __LINE__, dfloat.f);\n    printf(\"[%s:%d] i %x\\n\", __FUNCTION__, __LINE__, dfloat.i);\n    dfloat.f = 3.14159;\n    printf(\"[%s:%d] 2f %f\\n\", __FUNCTION__, __LINE__, dfloat.f);\n    printf(\"[%s:%d] 2i %x\\n\", __FUNCTION__, __LINE__, dfloat.i);\n    ddouble.f = 3.14159;\n    printf(\"[%s:%d] 2f %f\\n\", __FUNCTION__, __LINE__, ddouble.f);\n    printf(\"[%s:%d] 2i %lx\\n\", __FUNCTION__, __LINE__, ddouble.i);\n    return 0;\n}\n"
  },
  {
    "path": "tests/fp/BviFpAdd.bsv",
    "content": "\n/*\n   ../../scripts/importbvi.py\n   -o\n   BviFpAdd.bsv\n   -c\n   aclk\n   -f\n   s_axis_a\n   -f\n   s_axis_b\n   -f\n   m_axis_result\n   -I\n   BviFpAdd\n   -P\n   BviFpAdd\n   ../../generated/xilinx/zc706/fp_add/fp_add_stub.v\n*/\n\nimport Clocks::*;\nimport DefaultValue::*;\nimport XilinxCells::*;\nimport GetPut::*;\nimport FloatingPoint::*;\n\ninterface BviFpAdd;\n   method Action s_axis_a(Float v);\n   method Action s_axis_b(Float v);\n   method Action s_axis_operation(Bit#(8) v);\n   method ActionValue#(Float) m_axis_result();\nendinterface\n\nimport \"BVI\" fp_add =\nmodule mkBviFpAdd (BviFpAdd);\n   default_clock aclk(aclk);\n   default_reset aresetn(aresetn);\n   \n   method s_axis_a (s_axis_a_tdata)\n      ready (s_axis_a_tready) enable (s_axis_a_tvalid);\n   method s_axis_b (s_axis_b_tdata)\n      ready (s_axis_b_tready) enable (s_axis_b_tvalid);\n      \n   method s_axis_operation (s_axis_operation_tdata)\n      ready (s_axis_operation_tready) enable (s_axis_operation_tvalid);\n      \n   method m_axis_result_tdata m_axis_result ()\n      ready (m_axis_result_tvalid) enable (m_axis_result_tready);\n      \n      schedule (s_axis_a, s_axis_b, s_axis_operation, m_axis_result) CF\n      (s_axis_a, s_axis_b, s_axis_operation, m_axis_result);\nendmodule\n"
  },
  {
    "path": "tests/fp/FpOps.bsv",
    "content": "\n// Copyright (c) 2014 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\n`include \"ConnectalProjectConfig.bsv\"\nimport BviFpAdd::*;\nimport Clocks::*;\nimport GetPut::*;\nimport ClientServer::*;\nimport FloatingPoint::*;\nimport FIFO::*;\n\n`ifdef SIMULATION\n\nmodule mkXilinxFPAdder(Server#(Tuple2#(Float,Float), Float));\n\n   FIFO#(Float) resultFifo <- mkFIFO();\n\n   interface Put request;\n      method Action put(Tuple2#(Float,Float) req);\n\t match { .a, .b } = req;\n\t resultFifo.enq(a+b);\n      endmethod\n   endinterface\n   interface Get response = toGet(resultFifo);\n\nendmodule: mkXilinxFPAdder\n\n`else\nmodule mkXilinxFPAdder(Server#(Tuple2#(Float,Float), Float));\n   let fpAdd <- mkBviFpAdd();\n   \n   interface Put request;\n   method Action put(Tuple2#(Float,Float) req);\n      match { .a, .b } = req;\n      fpAdd.s_axis_a(a);\n      fpAdd.s_axis_b(b);\n      fpAdd.s_axis_operation(0);\n   endmethod\n   endinterface\n   \n   interface Get response = toGet(fpAdd.m_axis_result);\nendmodule\n`endif\n"
  },
  {
    "path": "tests/fp/FpTest.bsv",
    "content": "// Copyright (c) 2014 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\nimport FloatingPoint::*;\nimport GetPut::*;\nimport ClientServer::*;\nimport FpOps::*;\n\ninterface FpRequest;\n   method Action add(Float a, Float b);\nendinterface\ninterface FpIndication;\n   method Action added(Float a);\nendinterface\n\ninterface FpTest;\n   interface FpRequest request;\nendinterface\n\nmodule mkFpTest#(FpIndication indication)(FpTest);\n   Server#(Tuple2#(Float,Float),Float) adder <- mkXilinxFPAdder();\n\n   rule result;\n      let v <- adder.response.get();\n      indication.added(v);\n   endrule\n\n   interface FpRequest request;\n   method Action add(Float a, Float b);\n      adder.request.put(tuple2(a, b));\n   endmethod\n   endinterface\nendmodule\n"
  },
  {
    "path": "tests/fp/Makefile",
    "content": "CONNECTALDIR?=../..\nS2H_INTERFACES = FpRequest:FpTest.request\nH2S_INTERFACES = FpTest:FpIndication\n\nBSVFILES = FpTest.bsv\nCPPFILES=testfp.cpp\nCONNECTALFLAGS += --xci=$(IPDIR)/$(BOARD)/fp_add/fp_add.xci --xci=$(IPDIR)/$(BOARD)/fp_mul/fp_mul.xci\n\nFP_ADD_V = $(IPDIR)/$(BOARD)/fp_add/fp_add_stub.v\n\nifeq ($(BOARD),bluesim)\n# not for bluesim\nelse\n##\n## the prebuild target will be made after the project directory is generated, e.g., by make gen.zedboard\n##\nprebuild:: $(FP_ADD_V) BviFpAdd.bsv\n\n$(FP_ADD_V): synth-ip.tcl\n\t(cd $(BOARD); vivado -mode batch -source ../synth-ip.tcl)\nendif\n\n##\n## Generate the import \"BVI\" from the generated stub for the core: fp_add_stub.v\n##   Then, hand-modified so it works\nBviFpAdd.bsv:\n\t$(CONNECTALDIR)/scripts/importbvi.py -o BviFpAdd.bsv -c aclk -f s_axis_a -f s_axis_b -f m_axis_result -I BviFpAdd -P BviFpAdd $(FP_ADD_V)\n\ninclude $(CONNECTALDIR)/Makefile.connectal\n"
  },
  {
    "path": "tests/fp/synth-ip.tcl",
    "content": "source board.tcl\nsource $connectaldir/scripts/connectal-synth-ip.tcl\n\nconnectal_synth_ip floating_point 7.0 fp_add [list CONFIG.Axi_Optimize_Goal {Performance} CONFIG.Maximum_Latency {false} CONFIG.Has_ARESETN {true}]\nconnectal_synth_ip floating_point 7.0 fp_mul [list CONFIG.Operation_Type {Multiply} CONFIG.Axi_Optimize_Goal {Resources} CONFIG.Maximum_Latency {false} CONFIG.Has_ARESETN {true}]\n"
  },
  {
    "path": "tests/fp/testfp.cpp",
    "content": "/* Copyright (c) 2014 Quanta Research Cambridge, Inc\n *\n * Permission is hereby granted, free of charge, to any person obtaining a\n * copy of this software and associated documentation files (the \"Software\"),\n * to deal in the Software without restriction, including without limitation\n * the rights to use, copy, modify, merge, publish, distribute, sublicense,\n * and/or sell copies of the Software, and to permit persons to whom the\n * Software is furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n * DEALINGS IN THE SOFTWARE.\n */\n//#include <stdio.h>\n//#include <stdlib.h>\n//#include <unistd.h>\n//#include <assert.h>\n#include \"FpIndication.h\"\n#include \"FpRequest.h\"\n\nclass FpIndication : public FpIndicationWrapper\n{  \npublic:\n  uint32_t cnt;\n  void incr_cnt(){\n    if (++cnt == 1)\n      exit(0);\n  }\n  void added ( float a ) {\n    fprintf(stderr, \"Result=%f\\n\", a);\n    incr_cnt();\n  }\n  FpIndication(unsigned int id) : FpIndicationWrapper(id), cnt(0){}\n};\n\nint main(int argc, const char **argv)\n{\n  FpIndication indication(IfcNames_FpIndicationH2S);\n  FpRequestProxy *device = new FpRequestProxy(IfcNames_FpRequestS2H);\n  float a = 1.0, b = 0.5;\n\n  device->add(a, b);\n  // wait for answer\n  sleep(10);\n}\n"
  },
  {
    "path": "tests/guard/GuardTest.bsv",
    "content": "// Copyright (c) 2015 The Connectal Project\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\nimport FIFOF          ::*;\n\ninterface MemServer;\n   method Action myMethod(Bool rc);\nendinterface\t\t\n\n// Warning: \"GuardTest.bsv\", line 34, column 9: (G0010)\n//   Rule \"dbgrRule\" was treated as more urgent than \"toprule\". Conflicts:\n//     \"dbgrRule\" cannot fire before \"toprule\":\n//       calls to myFlag.write vs. myFlag.read\n//     \"toprule\" cannot fire before \"dbgrRule\":\n//       calls to myFlag.write vs. myFlag.read\nmodule  mkGuardTestBench(Empty);\n   FIFOF#(Bool) fifo <- mkFIFOF1;\n\n   Reg#(Bool) myFlag <- mkReg(False);\n   rule dbgrRule if (myFlag);\n       myFlag <= False;\n   endrule\n   rule toprule;\n      if (fifo.first && !myFlag)\n         myFlag <= fifo.first;\n   endrule\nendmodule\n\n// this version does not generate the extra warning\nmodule  mkGuardTestBenchNonAgressive(Empty);\n   FIFOF#(Bool) fifo <- mkFIFOF1;\n\n   Reg#(Bool) myFlag <- mkReg(False);\n   rule dbgrRule if (myFlag);\n       myFlag <= False;\n   endrule\n   rule toprule if (!myFlag);\n      if (fifo.first)\n         myFlag <= fifo.first;\n   endrule\nendmodule\n"
  },
  {
    "path": "tests/guard/Makefile",
    "content": "CONNECTALDIR?=../..\n\nrun: guardTestBench\n\t#./guardTestBench\n\nguardTestBench: GuardTest.bsv\n\tmkdir -p obj\n\tbsc --show-schedule -aggressive-conditions \\\n\t   -sim -info-dir obj -bdir obj -p +:$(CONNECTALDIR)/lib/bsv -g mkGuardTestBench -u $<\n\tbsc --show-schedule -sim -info-dir obj -bdir obj -e mkGuardTestBench -o guardTestBench\n\nclean:\n\trm -rf guardTestBench* mkGuardTestBench.* model_mkGuardTestBench.* dump.vcd obj\n"
  },
  {
    "path": "tests/guard/gtest.c",
    "content": "#include <stdio.h>\n\nint main()\n{\n    return 0;\n}\n"
  },
  {
    "path": "tests/ipcperf/IpcTest.bsv",
    "content": "// Copyright (c) 2013 Nokia, Inc.\n// Copyright (c) 2013 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\nimport FIFO::*;\n\ninterface IpcTestIndication;\n    method Action heard(Bit#(32) v);\n    method Action heard2(Bit#(16) a, Bit#(16) b);\nendinterface\n\ninterface IpcTestRequest;\n   method Action say(Bit#(32) v);\n   method Action say2(Bit#(16) a, Bit#(16) b);\n   method Action setLeds(Bit#(8) v);\nendinterface\n\ninterface IpcTest;\n   interface IpcTestRequest request;\nendinterface\n\ntypedef struct {\n\tBit#(16) a;\n\tBit#(16) b;\n} IpcTestPair deriving (Bits);\n\nmodule mkIpcTest#(IpcTestIndication indication)(IpcTest);\n    FIFO#(Bit#(32)) delay <- mkSizedFIFO(8);\n    FIFO#(IpcTestPair) delay2 <- mkSizedFIFO(8);\n\n    rule heard;\n        delay.deq;\n        indication.heard(delay.first);\n    endrule\n\n    rule heard2;\n        delay2.deq;\n        indication.heard2(delay2.first.b, delay2.first.a);\n    endrule\n   \n   interface IpcTestRequest request;\n      method Action say(Bit#(32) v);\n\t delay.enq(v);\n      endmethod\n      \n      method Action say2(Bit#(16) a, Bit#(16) b);\n\t delay2.enq(IpcTestPair { a: a, b: b});\n      endmethod\n      \n      method Action setLeds(Bit#(8) v);\n      endmethod\n   endinterface\nendmodule\n"
  },
  {
    "path": "tests/ipcperf/Makefile",
    "content": "CONNECTALDIR?=../..\nS2H_INTERFACES = IpcTestRequest:IpcTest.request\nH2S_INTERFACES = IpcTest:IpcTestIndication\n\nBSVFILES = IpcTest.bsv\nCPPFILES=testipctest.cpp\n## for testing fpgamake:\nFPGAMAKE_CONNECTALFLAGS += -P mkIpcTestIndicationProxySynth -P mkIpcTestRequestWrapperMemPortalPipes\n\ninclude $(CONNECTALDIR)/Makefile.connectal\n"
  },
  {
    "path": "tests/ipcperf/testipctest.cpp",
    "content": "/* Copyright (c) 2014 Quanta Research Cambridge, Inc\n *\n * Permission is hereby granted, free of charge, to any person obtaining a\n * copy of this software and associated documentation files (the \"Software\"),\n * to deal in the Software without restriction, including without limitation\n * the rights to use, copy, modify, merge, publish, distribute, sublicense,\n * and/or sell copies of the Software, and to permit persons to whom the\n * Software is furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n * DEALINGS IN THE SOFTWARE.\n */\n\n#include <stdio.h>\n#include <stdlib.h>\n#include <pthread.h>\n#include <semaphore.h>\n#include <unistd.h>\n#include <pthread.h>\n#include <string.h>\n\n#include \"IpcTestIndication.h\"\n#include \"IpcTestRequest.h\"\n#include \"GeneratedTypes.h\"\n#include <sys/ioctl.h>\n#include \"drivers/zynqportal/zynqportal.h\"\n#include <errno.h>\n\n#define LOOP_COUNT 5\n\nIpcTestRequestProxy *ipcTestRequestProxy = 0;\n\nstatic int silent;\nstatic int flag_heard;\nstatic sem_t sem_heard;\nstatic pthread_mutex_t mutex_heard;\n\nPortalPoller *poller = 0;\nstatic int use_mutex = 0;\nstatic int use_inline = 0;\npthread_t threaddata;\n\nclass IpcTestIndication : public IpcTestIndicationWrapper\n{\npublic:\n    virtual void heard(uint32_t v) {\n        if (!silent)\n            fprintf(stderr, \"heard an ipcTest: %d\\n\", v);\n        flag_heard++;\n        if (use_mutex)\n            pthread_mutex_unlock(&mutex_heard);\n        else\n            sem_post(&sem_heard);\n    }\n    virtual void heard2(uint16_t v1, uint16_t v2) {}\n    IpcTestIndication(unsigned int id, PortalPoller *poller) : IpcTestIndicationWrapper(id, poller) {}\n};\n\nstatic void run_test(void)\n{\n#define PCYC_LEN 20\n  int i;\n  uint64_t pcyc[PCYC_LEN];\n  uint64_t lastp = 0;\n\n  memset(pcyc, 0, sizeof(pcyc));\n  pcyc[0] = portalCycleCount();\n  flag_heard = 0;\n  pcyc[3] = portalCycleCount();\n    ipcTestRequestProxy->say(22);\n  pcyc[8] = portalCycleCount();\n  if (use_inline) {\n    while (!flag_heard) {\n        poller->event();\n    }\n    pcyc[9] = pcyc[8];\n    pcyc[12] = pcyc[8];\n    pcyc[17] = pcyc[8];\n  }\n  else {\n  if (use_mutex)\n    pthread_mutex_lock(&mutex_heard);\n  else\n    sem_wait(&sem_heard);\n  if (ipcTestRequestProxy->pint.fpga_fd >= 0) {\n      PortalInterruptTime inttime;\n      ioctl(ipcTestRequestProxy->pint.fpga_fd, PORTAL_INTERRUPT_TIME, &inttime);\n      pcyc[9] = (((uint64_t)inttime.msb)<<32) | ((uint64_t)inttime.lsb);\n  }\n  pcyc[12] = poll_return_time; // time after poll() returns\n  pcyc[17] = poll_enter_time; // time poll() reentered\n  }\n  pcyc[18] = portalCycleCount();\n  for (i = 0; i < PCYC_LEN; i++)\n      if (pcyc[i]) {\n          if (i)\n              printf(\"  %d:%5lld;\", i, (long long)(pcyc[i] - lastp));\n          lastp = pcyc[i];\n      }\n  printf(\"\\n\");\n}\n\nint main(int argc, const char **argv)\n{\n    int i;\n    poller = new PortalPoller();\n    IpcTestIndication ipcTestIndication(IfcNames_IpcTestIndicationH2S, poller);\n    ipcTestRequestProxy = new IpcTestRequestProxy(IfcNames_IpcTestRequestS2H);\n    pthread_mutex_lock(&mutex_heard);\n    sem_init(&sem_heard, 0, 0);\n\n    poller->start();\n\n    run_test();\n    printf(\"turn off printf in responder\\n\");\n    silent = 1;\n    for (i = 0; i < LOOP_COUNT; i++)\n        run_test();\n    printf(\"now try as mutex\\n\");\n    use_mutex = 1;\n    for (i = 0; i < LOOP_COUNT; i++)\n        run_test();\n    use_mutex = 0;\n\n    struct sched_param sched_param;\n    int sched_policy;\n    pthread_getschedparam(pthread_self(), &sched_policy, &sched_param);\n    sched_param.sched_priority = sched_get_priority_max(SCHED_RR);\n    pthread_setschedparam(pthread_self(), SCHED_RR, &sched_param);\n    printf(\"[%s:%d] scheduling policy changed to SCHED_RR\\n\", __FUNCTION__, __LINE__);\n    for (i = 0; i < LOOP_COUNT; i++)\n        run_test();\n    printf(\"disable interrupts for ipcTestIndication\\n\");\n    poller->stop();\n    printf(\"now try inline\\n\");\n    use_inline = 1;\n    for (i = 0; i < LOOP_COUNT; i++)\n        run_test();\nprintf(\"[%s:%d] end\\n\", __FUNCTION__, __LINE__);\n    return 0;\n}\n"
  },
  {
    "path": "tests/ipcperf/vc707_floorplan.xdc",
    "content": "startgroup\ncreate_pblock pblock_ep7\nresize_pblock pblock_ep7 -add {SLICE_X184Y54:SLICE_X221Y166 DSP48_X18Y22:DSP48_X19Y65 RAMB18_X12Y22:RAMB18_X14Y65 RAMB36_X12Y11:RAMB36_X14Y32}\nadd_cells_to_pblock pblock_ep7 [get_cells [list host_ep7]] -clear_locs\nset_property HD.PARTPIN_RANGE {SLICE_X185Y54:SLICE_X186Y166} [get_pins host_ep7/*]\nset_property CONTAIN_ROUTING true [get_pblocks pblock_ep7]\nendgroup\n\nstartgroup\ncreate_pblock pblock_pciehost\nresize_pblock pblock_pciehost -add {SLICE_X112Y55:SLICE_X173Y197 DSP48_X9Y22:DSP48_X16Y77 RAMB18_X7Y22:RAMB18_X10Y77 RAMB36_X7Y11:RAMB36_X10Y38}\nadd_cells_to_pblock pblock_pciehost [get_cells [list host_pciehost]] -clear_locs\nset_property HD.PARTPIN_RANGE {SLICE_X112Y55:SLICE_X113Y197} [get_pins host_pciehost/*]\nset_property HD.PARTPIN_RANGE {SLICE_X172Y55:SLICE_X173Y197} [get_pins host_pciehost/*pci_re*]\nset_property HD.PARTPIN_RANGE {SLICE_X172Y55:SLICE_X173Y197} [get_pins host_pciehost/*pci*]\nset_property CONTAIN_ROUTING true [get_pblocks pblock_pciehost]\nendgroup\n\n# startgroup\n# create_pblock pblock_pciehost\n# resize_pblock pblock_pciehost -add {SLICE_X112Y55:SLICE_X221Y197 DSP48_X9Y22:DSP48_X19Y77 RAMB18_X7Y22:RAMB18_X14Y77 RAMB36_X7Y11:RAMB36_X14Y38}\n# add_cells_to_pblock pblock_pciehost [get_cells [list host]] -clear_locs\n# set_property HD.PARTPIN_RANGE {SLICE_X112Y55:SLICE_X113Y197} [get_pins host/*]\n# endgroup\n\n"
  },
  {
    "path": "tests/memcpy_manysglists/Makefile",
    "content": "\nCONNECTALDIR?=../..\nMEMCPYDIR=$(CONNECTALDIR)/examples/memcpy\nINTERFACES = MemcpyRequest MemcpyIndication\nBSVFILES = $(MEMCPYDIR)/Memcpy.bsv Top.bsv\nCPPFILES=testmemcpy.cpp\n\ninclude $(CONNECTALDIR)/Makefile.connectal\n"
  },
  {
    "path": "tests/memcpy_manysglists/Top.bsv",
    "content": "// Copyright (c) 2013 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\nimport SpecialFIFOs::*;\nimport Vector::*;\nimport BuildVector::*;\nimport StmtFSM::*;\nimport FIFO::*;\nimport CtrlMux::*;\nimport Portal::*;\nimport ConnectalMemory::*;\nimport ConnectalMemTypes::*;\nimport MemServer::*;\nimport ConnectalMMU::*;\nimport ConnectalConfig::*;\nimport MemcpyRequest::*;\nimport MemServerRequest::*;\nimport MMURequest::*;\nimport MemcpyIndication::*;\nimport MemServerIndication::*;\nimport MMUIndication::*;\nimport Memcpy::*;\n\ntypedef enum {IfcNames_MemcpyIndication, \n\t      IfcNames_MemcpyRequest, \n\n\t      IfcNames_MemServerIndicationH2S,\n\t      IfcNames_MemServerRequestS2H, \n\n\t      IfcNames_MMU0ConfigRequest, \n\t      IfcNames_MMU0ConfigIndication,\n\t      \n\t      IfcNames_MMU1ConfigRequest, \n\t      IfcNames_MMU1ConfigIndication,\n\t      \n\t      IfcNames_MMU2ConfigRequest, \n\t      IfcNames_MMU2ConfigIndication,\n\n\t      IfcNames_MMU3ConfigRequest, \n\t      IfcNames_MMU3ConfigIndication } IfcNames deriving (Eq,Bits);\n\nmodule mkConnectalTop(ConnectalTop);\n\n   MemcpyIndicationProxy memcpyIndicationProxy <- mkMemcpyIndicationProxy(IfcNames_MemcpyIndication);\n   Memcpy memcpy <- mkMemcpy(memcpyIndicationProxy.ifc);\n   MemcpyRequestWrapper memcpyRequestWrapper <- mkMemcpyRequestWrapper(IfcNames_MemcpyRequest,memcpy.request);\n\n\n   MMUIndicationProxy hostMMU0ConfigIndicationProxy <- mkMMUIndicationProxy(IfcNames_MMU0ConfigIndication);\n   MMU#(PhysAddrWidth) hostMMU0 <- mkMMU(0, True, hostMMU0ConfigIndicationProxy.ifc);\n   MMURequestWrapper hostMMU0ConfigRequestWrapper <- mkMMURequestWrapper(IfcNames_MMU0ConfigRequest, hostMMU0.request);\n   \n   MMUIndicationProxy hostMMU1ConfigIndicationProxy <- mkMMUIndicationProxy(IfcNames_MMU1ConfigIndication);\n   MMU#(PhysAddrWidth) hostMMU1 <- mkMMU(1, True, hostMMU1ConfigIndicationProxy.ifc);\n   MMURequestWrapper hostMMU1ConfigRequestWrapper <- mkMMURequestWrapper(IfcNames_MMU1ConfigRequest, hostMMU1.request);\n   \n   MMUIndicationProxy hostMMU2ConfigIndicationProxy <- mkMMUIndicationProxy(IfcNames_MMU2ConfigIndication);\n   MMU#(PhysAddrWidth) hostMMU2 <- mkMMU(2, True, hostMMU2ConfigIndicationProxy.ifc);\n   MMURequestWrapper hostMMU2ConfigRequestWrapper <- mkMMURequestWrapper(IfcNames_MMU2ConfigRequest, hostMMU2.request);\n\n   MMUIndicationProxy hostMMU3ConfigIndicationProxy <- mkMMUIndicationProxy(IfcNames_MMU3ConfigIndication);\n   MMU#(PhysAddrWidth) hostMMU3 <- mkMMU(3, True, hostMMU3ConfigIndicationProxy.ifc);\n   MMURequestWrapper hostMMU3ConfigRequestWrapper <- mkMMURequestWrapper(IfcNames_MMU3ConfigRequest, hostMMU3.request);\n   \n   MemServerIndicationProxy hostMemServerIndicationProxy <- mkMemServerIndicationProxy(IfcNames_MemServerIndication);\n   let sgls = vec(hostMMU0,hostMMU1,hostMMU2,hostMMU3);\n   MemServer#(PhysAddrWidth,64,1) dma <- mkMemServer(memcpy.dmaReadClient, memcpy.dmaWriteClient, sgls, hostMemServerIndicationProxy.ifc);\n   MemServerRequestWrapper hostMemServerRequestWrapper <- mkMemServerRequestWrapper(IfcNames_MemServerRequest, dma.request);\n\n   Vector#(12,StdPortal) portals;\n   portals[0] = memcpyRequestWrapper.portalIfc;\n   portals[1] = memcpyIndicationProxy.portalIfc; \n   portals[2] = hostMemServerRequestWrapper.portalIfc;\n   portals[3] = hostMemServerIndicationProxy.portalIfc; \n   \n   portals[4] = hostMMU0ConfigRequestWrapper.portalIfc;\n   portals[5] = hostMMU0ConfigIndicationProxy.portalIfc;\n   \n   portals[6] = hostMMU1ConfigRequestWrapper.portalIfc;\n   portals[7] = hostMMU1ConfigIndicationProxy.portalIfc;\n   \n   portals[8] = hostMMU2ConfigRequestWrapper.portalIfc;\n   portals[9] = hostMMU2ConfigIndicationProxy.portalIfc;\n\n   portals[10] = hostMMU3ConfigRequestWrapper.portalIfc;\n   portals[11] = hostMMU3ConfigIndicationProxy.portalIfc;\n   let ctrl_mux <- mkSlaveMux(portals);\n   \n   interface interrupt = getInterruptVector(portals);\n   interface slave = ctrl_mux;\n   interface masters = dma.masters;\nendmodule\n"
  },
  {
    "path": "tests/memcpy_manysglists/testmemcpy.cpp",
    "content": "/* Copyright (c) 2013 Quanta Research Cambridge, Inc\n *\n * Permission is hereby granted, free of charge, to any person obtaining a\n * copy of this software and associated documentation files (the \"Software\"),\n * to deal in the Software without restriction, including without limitation\n * the rights to use, copy, modify, merge, publish, distribute, sublicense,\n * and/or sell copies of the Software, and to permit persons to whom the\n * Software is furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n * DEALINGS IN THE SOFTWARE.\n */\n#include <monkit.h>\n#include \"dmaManager.h\"\n#include \"MemcpyIndication.h\"\n#include \"MemcpyRequest.h\"\n\nsem_t done_sem;\nint srcAlloc;\nint dstAlloc;\nunsigned int *srcBuffer = 0;\nunsigned int *dstBuffer = 0;\nint numWords = 16 << 2;\nsize_t alloc_sz = numWords*sizeof(unsigned int);\nbool memcmp_fail = false;\n\nvoid dump(const char *prefix, char *buf, size_t len)\n{\n    fprintf(stderr, \"%s \", prefix);\n    for (unsigned int i = 0; i < len ; i++) {\n\tfprintf(stderr, \"%02x\", (unsigned char)buf[i]);\n\tif (i % 32 == 31)\n\t  fprintf(stderr, \"\\n\");\n    }\n    fprintf(stderr, \"\\n\");\n}\n\nclass MemcpyIndication : public MemcpyIndicationWrapper\n{\n\npublic:\n  MemcpyIndication(unsigned int id) : MemcpyIndicationWrapper(id){}\n\n  virtual void started(){\n    fprintf(stderr, \"started\\n\");\n  }\n  virtual void done() {\n    sem_post(&done_sem);\n    fprintf(stderr, \"done\\n\");\n    memcmp_fail = memcmp(srcBuffer, dstBuffer, alloc_sz);\n    //dump(\"xxx \", (char*)dstBuffer, alloc_sz);\n  }\n};\n\nint do_copy(int srcAlloc, int sgl_config_request_id, int sgl_config_indication_id)\n{\n  MemcpyRequestProxy *device = new MemcpyRequestProxy(IfcNames_MemcpyRequest);\n  MemcpyIndication deviceIndication(IfcNames_MemcpyIndication);\n    DmaManager *dma = platformInit();\n  //MMURequestProxy *dmap = new MMURequestProxy(sgl_config_request_id);\n  //MMUIndication *hostMMUIndication = new MMUIndication(dma, sgl_config_indication_id);\n\n  fprintf(stderr, \"Main::allocating memory...\\n\");\n\n  size_t dstBytes = alloc_sz;\n  size_t srcBytes = dstBytes;\n  bool first = false;\n\n  int dstAlloc = portalAlloc(dstBytes, 0);\n  if(!srcAlloc) {\n    srcAlloc = portalAlloc(srcBytes, 0);\n    first = true;\n  }\n\n  int ref_dstAlloc = dma->reference(dstAlloc);\n  int ref_srcAlloc = dma->reference(srcAlloc);\n\n  srcBuffer = (unsigned int *)portalMmap(srcAlloc, srcBytes);\n  dstBuffer = (unsigned int *)portalMmap(dstAlloc, dstBytes);\n\n  \n  for (int i = 0; i < numWords; i++){\n    if (first) srcBuffer[i] = i;\n    dstBuffer[i] = 0x5a5abeef;\n  }\n\n  portalCacheFlush(srcAlloc, srcBuffer, alloc_sz, 1);\n  portalCacheFlush(dstAlloc, dstBuffer, alloc_sz, 1);\n\n  device->startCopy(ref_dstAlloc, ref_srcAlloc, numWords, 16, 1);\n  sem_wait(&done_sem);\n\n  return dstAlloc;\n}\n\nint main(int argc, const char **argv)\n{\n  if(sem_init(&done_sem, 1, 0)){\n    fprintf(stderr, \"failed to init done_sem\\n\");\n    exit(1);\n  }\n\n  bool memcmp_fails[4] = {false, false, false, false};\n\n  int dst_ref0 = do_copy(0,        IfcNames_MMU0ConfigRequest, IfcNames_MMU0ConfigIndication);\n  memcmp_fails[0] = memcmp_fail;\n  int dst_ref1 = do_copy(dst_ref0, IfcNames_MMU1ConfigRequest, IfcNames_MMU1ConfigIndication);\n  memcmp_fails[1] = memcmp_fail;\n  do_copy(dst_ref1, IfcNames_MMU2ConfigRequest, IfcNames_MMU2ConfigIndication);\n  memcmp_fails[2] = memcmp_fail;\n  int dst_ref3 = do_copy(dst_ref3, IfcNames_MMU3ConfigRequest, IfcNames_MMU3ConfigIndication);\n  memcmp_fails[3] = memcmp_fail;\n\n  fprintf(stderr, \"memcpy_manysglists: Done %d %d %d %d\\n\", memcmp_fails[0], memcmp_fails[1], memcmp_fails[2], memcmp_fails[3]);\n  sleep(2);\n\n  exit(memcmp_fails[0] | memcmp_fails[1] | memcmp_fails[2] | memcmp_fails[3] );\n}\n"
  },
  {
    "path": "tests/memread_err/Makefile",
    "content": "CONNECTALDIR ?= ../..\nS2H_INTERFACES = MemreadRequest:Memread.request\nH2S_INTERFACES = Memread:MemreadIndication\nMEM_READ_INTERFACES = cons\\(lMemread.dmaClient,nil\\)\n\nBSVFILES = Memread.bsv\nCPPFILES=testmemread.cpp\n\ninclude $(CONNECTALDIR)/Makefile.connectal\n"
  },
  {
    "path": "tests/memread_err/Memread.bsv",
    "content": "// Copyright (c) 2013 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\nimport FIFO::*;\nimport FIFOF::*;\nimport Vector::*;\nimport StmtFSM::*;\nimport GetPut::*;\nimport ClientServer::*;\nimport ConnectalMemTypes::*;\nimport MemReadEngine::*;\nimport Pipe::*;\n\ninterface MemreadRequest;\n   method Action startRead(Bit#(32) pointer, Bit#(32) offset, Bit#(32) numWords, Bit#(32) burstLen);\nendinterface\n\ninterface Memread;\n   interface MemreadRequest request;\n   interface MemReadClient#(64) dmaClient;\nendinterface\n\ninterface MemreadIndication;\n   method Action started(Bit#(32) numWords);\n   method Action readDone(Bit#(32) mismatchCount);\nendinterface\n\nmodule mkMemread#(MemreadIndication indication) (Memread);\n\n   Reg#(Bit#(32))         numWords <- mkReg(0);\n   Reg#(Bit#(32))         burstLen <- mkReg(0);\n   \n   Reg#(Bit#(32))           srcGen <- mkReg(0);\n   Reg#(Bit#(32))    mismatchCount <- mkReg(0);\n   MemReadEngine#(64,64,1,1)         re <- mkMemReadEngine;\n\n   let debug = True;\n   \n   rule check;\n      let v <- toGet(re.readServers[0].data).get;\n      let expectedV = {srcGen+1,srcGen};\n      let misMatch = v.data != expectedV;\n      if (debug && misMatch) $display(\"check %h %h\", v, expectedV);\n      mismatchCount <= mismatchCount + (misMatch ? 1 : 0);\n      if (srcGen+2 == numWords) begin\n\t srcGen <= 0;\n      end\n      else\n\t srcGen <= srcGen+2;\n      if (v.last) begin\n         if (debug) $display(\"finish\");\n         indication.readDone(mismatchCount);\n      end\n   endrule\n   \n   interface dmaClient = re.dmaClient;\n   interface MemreadRequest request;\n      method Action startRead(Bit#(32) rp, Bit#(32) off, Bit#(32) nw, Bit#(32) bl);\n\t if (debug) $display(\"startRead rdPointer=%d offset=%d numWords=%h burstLen=%d\", rp, off, nw, bl);\n\t indication.started(nw);\n\t numWords  <= nw;\n\t burstLen  <= bl;\n\t mismatchCount <= 0;\n\t srcGen <= 0;\n\t let cmd = MemengineCmd{sglId:rp, base:extend(off*4), len:nw*4, burstLen:truncate(bl*4), tag:0};\n\t re.readServers[0].request.put(cmd);\n      endmethod\n   endinterface\nendmodule\n"
  },
  {
    "path": "tests/memread_err/testmemread.cpp",
    "content": "/* Copyright (c) 2014 Quanta Research Cambridge, Inc\n *\n * Permission is hereby granted, free of charge, to any person obtaining a\n * copy of this software and associated documentation files (the \"Software\"),\n * to deal in the Software without restriction, including without limitation\n * the rights to use, copy, modify, merge, publish, distribute, sublicense,\n * and/or sell copies of the Software, and to permit persons to whom the\n * Software is furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n * DEALINGS IN THE SOFTWARE.\n */\n#include <monkit.h>\n#include \"dmaManager.h\"\n#include \"MemreadRequest.h\"\n#include \"MemreadIndication.h\"\n\nsem_t test_sem;\n\n#ifdef PCIE\nint burstLen = 32;\n#else\nint burstLen = 16;\n#endif\n\n#ifndef SIMULATION\nint numWords = 0x1240000/4; // make sure to allocate at least one entry of each size\n#else\nint numWords = 0x1240/4;\n#endif\n\nsize_t test_sz  = numWords*sizeof(unsigned int);\nsize_t alloc_sz = test_sz;\nint mismatchCount = 0;\n\nvoid dump(const char *prefix, char *buf, size_t len)\n{\n    fprintf(stderr, \"%s \", prefix);\n    for (unsigned int i = 0; i < (len > 16 ? 16 : len) ; i++)\n\tfprintf(stderr, \"%02x\", (unsigned char)buf[i]);\n    fprintf(stderr, \"\\n\");\n}\n\nclass MemreadIndication : public MemreadIndicationWrapper\n{\npublic:\n  unsigned int rDataCnt;\n  virtual void readDone(uint32_t v){\n    fprintf(stderr, \"Memread::readDone(%x)\\n\", v);\n    mismatchCount += v;\n    sem_post(&test_sem);\n  }\n  virtual void started(uint32_t words){\n    fprintf(stderr, \"Memread::started(%x)\\n\", words);\n  }\n  virtual void rData ( uint64_t v ){\n    fprintf(stderr, \"rData(%08x): \", rDataCnt++);\n    dump(\"\", (char*)&v, sizeof(v));\n  }\n  MemreadIndication(int id) : MemreadIndicationWrapper(id){}\n};\n\nint runtest(int argc, const char ** argv)\n{\n  int test_result = 0;\n  int srcAlloc;\n  unsigned int *srcBuffer = 0;\n\n  fprintf(stderr, \"Main::%s %s\\n\", __DATE__, __TIME__);\n  MemreadRequestProxy *device = new MemreadRequestProxy(IfcNames_MemreadRequestS2H);\n  MemreadIndication deviceIndication(IfcNames_MemreadIndicationH2S);\n  DmaManager *dma = platformInit();\n\n  fprintf(stderr, \"Main::allocating memory...\\n\");\n  srcAlloc = portalAlloc(alloc_sz, 0);\n  srcBuffer = (unsigned int *)portalMmap(srcAlloc, alloc_sz);\n\n#ifdef FPGA0_CLOCK_FREQ\n  long req_freq = FPGA0_CLOCK_FREQ;\n  long freq = 0;\n  setClockFrequency(0, req_freq, &freq);\n  fprintf(stderr, \"Requested FCLK[0]=%ld actually %ld\\n\", req_freq, freq);\n#endif\n\n  for (int i = 0; i < numWords; i++){\n    srcBuffer[i] = i;\n  }\n\n  portalCacheFlush(srcAlloc, srcBuffer, alloc_sz, 1);\n  fprintf(stderr, \"Main::flush and invalidate complete\\n\");\n\n  unsigned int ref_srcAlloc = dma->reference(srcAlloc);\n  fprintf(stderr, \"ref_srcAlloc=%d\\n\", ref_srcAlloc);\n\n  if(true) {\n    fprintf(stderr, \"Main::test read %08x\\n\", numWords);\n    // first attempt should get the right answer\n    device->startRead(ref_srcAlloc, 0, numWords, burstLen);\n    sem_wait(&test_sem);\n    if (mismatchCount) {\n      fprintf(stderr, \"Main::first test failed to match %d.\\n\", mismatchCount);\n      test_result++;     // failed\n    }\n  }\n\n  int err = 5;\n  switch (err){\n  case 0:\n    {\n      fprintf(stderr, \"Main: attempt to use a de-referenced sglist\\n\");\n      dma->dereference(ref_srcAlloc);\n      device->startRead(ref_srcAlloc, 0, numWords, burstLen);\n      break;\n    } \n  case 1:\n    {\n      fprintf(stderr, \"Main: attempt to use an out-of-range sglist\\n\");\n      device->startRead(ref_srcAlloc+32, 0, numWords, burstLen);\n      break;\n    }\n  case 2:\n    {\n      fprintf(stderr, \"Main: attempt to use an invalid sglist\\n\");\n      device->startRead(ref_srcAlloc+1, 0, numWords, burstLen);\n      break;\n    }\n  case 3:\n    {\n      fprintf(stderr, \"Main: attempt to use an invalid mmusel\\n\");\n      device->startRead(ref_srcAlloc | (1<<16), 0, numWords, burstLen);\n      break;\n    }\n  case 4:\n    {\n      fprintf(stderr, \"Main: attempt to read off the end of the region\\n\");\n      device->startRead(ref_srcAlloc, numWords<<2, burstLen, burstLen);\n      break;\n    }\n  default:\n    {\n      device->startRead(ref_srcAlloc, 0, numWords, burstLen);\n    }\n  }\n\n  sem_wait(&test_sem);\n  if (mismatchCount) {\n    fprintf(stderr, \"Main::first test failed to match %d.\\n\", mismatchCount);\n    test_result++;     // failed\n  }\n  return test_result;\n}\n\nint main(int argc, const char **argv)\n{\n  int ret = runtest(argc, argv);\n  exit(ret ? 1 : 0);\n}\n"
  },
  {
    "path": "tests/memread_manual/Makefile",
    "content": "CONNECTALDIR?=../..\nS2H_INTERFACES = ReadTestRequest:ReadTest.request\nH2S_INTERFACES = ReadTest:ReadTestIndication\nMEM_READ_INTERFACES = lReadTest.dmaClient\n\nBSVFILES = ReadTest.bsv\nCPPFILES=memread_manual_manager.c\n#CONNECTALFLAGS += -D NO_CPP_PORTAL_CODE -D NO_POLLER_SUPPORT\n\ninclude $(CONNECTALDIR)/Makefile.connectal\n"
  },
  {
    "path": "tests/memread_manual/ReadTest.bsv",
    "content": "// Copyright (c) 2013 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\nimport FIFO::*;\nimport FIFOF::*;\nimport Vector::*;\nimport BuildVector::*;\nimport GetPut::*;\nimport ClientServer::*;\nimport Pipe::*;\nimport ConnectalMemTypes::*;\nimport MemReadEngine::*;\nimport Pipe::*;\nimport ConnectalConfig::*;\n\ninterface ReadTestRequest;\n   method Action startRead(Bit#(32) pointer, Bit#(32) numBytes, Bit#(32) burstLen, Bit#(32) iterCnt);\nendinterface\n\ninterface ReadTest;\n   interface ReadTestRequest request;\n   interface Vector#(1,MemReadClient#(DataBusWidth)) dmaClient;\nendinterface\n\ninterface ReadTestIndication;\n   method Action readDone(Bit#(32) mismatchCount);\nendinterface\n\nmodule mkReadTest#(ReadTestIndication indication) (ReadTest);\n\n   Reg#(SGLId)   pointer <- mkReg(0);\n   Reg#(Bit#(32))       numBytes <- mkReg(0);\n   Reg#(Bit#(BurstLenSize)) burstLenBytes <- mkReg(0);\n   Reg#(Bit#(32))  itersToFinish <- mkReg(0);\n   Reg#(Bit#(32))   itersToStart <- mkReg(0);\n   Reg#(Bit#(32))        wordsRead <- mkReg(0);\n   Reg#(Bit#(32)) mismatchCounts <- mkReg(0);\n   MemReadEngine#(DataBusWidth,DataBusWidth,1,1) re <- mkMemReadEngine;\n   \n   rule start (itersToStart > 0);\n      $display(\"Test: request.put\");\n      re.readServers[0].request.put(MemengineCmd{sglId:pointer, base:0, len:numBytes, burstLen:burstLenBytes, tag:0});\n      itersToStart <= itersToStart-1;\n   endrule\n\n   rule check;\n      let v <- toGet(re.readServers[0].data).get;\n      let rval = wordsRead/4;\n      let expectedV = {rval+1,rval};\n      let misMatch = v.data != expectedV;\n      mismatchCounts <= mismatchCounts + (misMatch ? 1 : 0);\n      let new_wordsRead = wordsRead + fromInteger(valueOf(DataBusWidth))/8;\n      //$display(\"Test: check new=%x numBytes=%x wordsRead=%x misMatch=%x read=%x expect=%x\", new_wordsRead, numBytes, wordsRead, misMatch, v, expectedV);\n      if (v.last) begin\n         $display(\"Test: itersToFinish %x\", itersToFinish);\n         if (itersToFinish == 1) begin\n\t    indication.readDone(mismatchCounts);\n         end\n         itersToFinish <= itersToFinish - 1;\n\t new_wordsRead = 0;\n      end\n      wordsRead <= new_wordsRead;\n   endrule\n   \n   interface dmaClient = vec(re.dmaClient);\n   interface ReadTestRequest request;\n      method Action startRead(Bit#(32) rp, Bit#(32) nb, Bit#(32) bl, Bit#(32) ic) if (itersToStart == 0 && itersToFinish == 0);\n         $display(\"startRead pointer=%x numBytes %x burstLen %x iteration %x\", rp, nb, bl, ic);\n\t pointer <= rp;\n\t numBytes  <= nb;\n\t burstLenBytes  <= truncate(bl);\n\t itersToFinish <= ic;\n\t itersToStart <= ic;\n\t mismatchCounts <= 0;\n\t wordsRead <= 0;\n      endmethod\n   endinterface\nendmodule\n"
  },
  {
    "path": "tests/memread_manual/design_vc707.tcl",
    "content": "###############################################################\n###   Tcl Variables\n###############################################################\n#set tclParams [list <param1> <value> <param2> <value> ... <paramN> <value>]\nset tclParams [list place.closeImportedSites  1 \\\n                    hd.StrictContainRouting   1 \\\n              ]\n\n#Define location for \"Tcl\" directory. Defaults to \"../Tcl\"\nset tclHome \"../../scripts/xilinx/tcl\"\nif {[file exists $tclHome]} {\n   set tclDir $tclHome\n} elseif {[file exists \"./Tcl\"]} {\n   set tclDir  \"./Tcl\"\n} else {\n   error \"ERROR: No valid location found for required Tcl scripts. Set \\$tclDir in design.tcl to a valid location.\"\n}\n\n###############################################################\n### Part Variables - Define Device, Package, Speedgrade \n###############################################################\nset device       \"xc7vx485t\"\nset package      \"ffg1761\"\nset speed        \"-2\"\nset part         $device$package$speed\n\n###############################################################\n###  Setup Variables\n###############################################################\n####flow control\nset run.topSynth   0\nset run.oocSynth   1\nset run.tdImpl     1\nset run.oocImpl    1\nset run.topImpl    1\nset run.flatImpl   0\n\n####Report and DCP controls - values: 0-required min; 1-few extra; 2-all\nset verbose      1\nset dcpLevel     1\n\n####Output Directories\nset synthDir  \"./Synth\"\nset implDir   \"./Implement\"\nset dcpDir    \"./Checkpoint\"\n\n####Input Directories\nset srcDir     \"./vc707\"\nset rtlDir     \"$srcDir/verilog\"\nset prjDir     \"$srcDir/prj\"\nset xdcDir     \"$srcDir/constraints\"\nset coreDir    \"$srcDir/cores\"\nset netlistDir \"$srcDir/netlist\"\n\n####Source required Tcl Procs\nsource $tclDir/design_utils.tcl\nsource $tclDir/synth_utils.tcl\nsource $tclDir/impl_utils.tcl\nsource $tclDir/hd_floorplan_utils.tcl\n\n###############################################################\n### Top Definition\n###############################################################\nset top \"mkPcieTop\"\nadd_module $top\nset_attribute module $top    top_level     1\nset_attribute module $top    vlog          [concat [glob $rtlDir/top/*.v] [glob $rtlDir/lib/*.v] ]\nset_attribute module $top    ip            []\n#set_attribute module $top    vlog_headers  [glob $rtlDir/top/*Stub.v]\nset_attribute module $top    synth         ${run.topSynth}\n\nadd_implementation $top\nset_attribute impl $top      top           $top\nset_attribute impl $top      implXDC       [glob $xdcDir/vc707.xdc]\nset_attribute impl $top      impl          ${run.topImpl}\nset_attribute impl $top      hd.impl       1\n\n####################################################################\n### OOC Module Definition and OOC Implementation for each instance\n####################################################################\nset module1 \"mkPcieHost\"\nadd_module $module1\nset_attribute module $module1 vlog          [concat [glob $rtlDir/lib/*.v] [glob $rtlDir/pciehost/*.v]]\nset_attribute module $module1 ip            []\nset_attribute module $module1 synth        ${run.oocSynth}\n\nset instance \"pciehost\"\nadd_ooc_implementation $instance\nset_attribute ooc $instance   module       $module1\nset_attribute ooc $instance   inst         $instance\nset_attribute ooc $instance   hierInst     $instance\nset_attribute ooc $instance   implXDC      [list $xdcDir/${instance}_phys.xdc \\\n\t\t\t\t\t\t $xdcDir/${instance}_ooc_timing.xdc \\\n\t\t\t\t\t\t $xdcDir/${instance}_ooc_budget.xdc \\\n\t\t\t\t\t\t $xdcDir/${instance}_ooc_optimize.xdc \\\n\t\t\t\t\t\t]\nset_attribute ooc $instance   impl         ${run.oocImpl}\nset_attribute ooc $instance   preservation routing\n\nset module2 \"mkPCIExpressEndpointX7\"\nadd_module $module2\nset_attribute module $module2 vlog          [concat [glob $rtlDir/lib/*.v] [list $rtlDir/ep7/mkPCIExpressEndpointX7.v]]\nset_attribute module $module2 ip            [glob /scratch/jamey/connectal/generated/xilinx/vc707/*/*.xci]\nset_attribute module $module2 synth        ${run.oocSynth}\n\nset instance \"ep7\"\nadd_ooc_implementation $instance\nset_attribute ooc $instance   module       $module2\nset_attribute ooc $instance   inst         $instance\nset_attribute ooc $instance   hierInst     $instance\nset_attribute ooc $instance   implXDC      [list $xdcDir/${instance}_phys.xdc \\\n\t\t\t\t\t\t $xdcDir/${instance}_ooc_timing.xdc \\\n\t\t\t\t\t\t $xdcDir/${instance}_ooc_budget.xdc \\\n\t\t\t\t\t\t $xdcDir/${instance}_ooc_optimize.xdc \\\n\t\t\t\t\t\t]\nset_attribute ooc $instance   impl         ${run.oocImpl}\nset_attribute ooc $instance   preservation routing\n\n# set module3 \"mkSynthesizeableConnectalTop\"\n# add_module $module3\n# set_attribute module $module3 vlog          [concat [glob $rtlDir/lib/*.v] [list $rtlDir/portal/mkSynthesizeableConnectalTop.v]]\n# set_attribute module $module3 ip            []\n# set_attribute module $module3 synth        ${run.oocSynth}\n\n# set instance \"portalTop\"\n# add_ooc_implementation $instance\n# set_attribute ooc $instance   module       $module3\n# set_attribute ooc $instance   inst         $instance\n# set_attribute ooc $instance   hierInst     $instance\n# set_attribute ooc $instance   implXDC      [list $xdcDir/${instance}_phys.xdc \\\n# \t\t\t\t\t\t $xdcDir/${instance}_ooc_timing.xdc \\\n# \t\t\t\t\t\t $xdcDir/${instance}_ooc_budget.xdc \\\n# \t\t\t\t\t\t $xdcDir/${instance}_ooc_optimize.xdc \\\n# \t\t\t\t\t\t]\n# set_attribute ooc $instance   impl         ${run.oocImpl}\n# set_attribute ooc $instance   preservation routing\n\n####################################################################\n### Create TopDown implementation run \n####################################################################\nset module1File \"$synthDir/$module1/${module1}_synth.dcp\"\nset module2File \"$synthDir/$module2/${module2}_synth.dcp\"\n#set module3File \"$synthDir/$module3/${module3}_synth.dcp\"\nadd_implementation TopDown\nset_attribute impl TopDown      top          $top\nset_attribute impl TopDown      implXDC      [list $xdcDir/floorplan_vc707.xdc $xdcDir/vc707.xdc]\nset_attribute impl TopDown      td.impl      1\nset_attribute impl TopDown      cores        [list $module1File                          \\\n                                                   $module2File                          \\\n                                                   [get_attribute module $top cores]     \\\n                                                   [get_attribute module $module1 cores] \\\n                                                   [get_attribute module $module2 cores] \\\n                                             ] \nset_attribute impl TopDown      impl         ${run.tdImpl}\nset_attribute impl TopDown      route        0\n\n####################################################################\n### Create Flat implementation run \n####################################################################\nadd_implementation Flat\nset_attribute impl Flat         top          $top\nset_attribute impl Flat         implXDC      [list $xdcDir/${top}_flpn.xdc $xdcDir/vc707.xdc]\nset_attribute impl Flat         cores        [list $module1File                          \\\n                                                   $module2File                          \\\n                                                   [get_attribute module $top cores]     \\\n                                                   [get_attribute module $module1 cores] \\\n                                                   [get_attribute module $module2 cores] \\\n                                             ] \nset_attribute impl Flat         impl         ${run.flatImpl}\n\n########################################################################\n### Task / flow portion\n########################################################################\n\nset_property SEVERITY {Warning} [get_drc_checks HDOOC-4]\n\n# Build the designs\nsource $tclDir/run.tcl\n\nexit\n"
  },
  {
    "path": "tests/memread_manual/kernel/Makefile",
    "content": "\n# grep get_pcie_portal_descriptor /proc/kallsyms \n\n###################### Flags for using KC705   ###################\n#BOARD=kc705\n###################### Flags for using VC707   ###################\n#BOARD=vc707\n###################### Flags for using zedboard ##################\n#BOARD=zedboard\n###################### Flags for using Bluesim ###################\nBOARD=bluesim\n###################### End of target h/w flags ###################\n\nifeq ($(BOARD),bluesim)\n    HARDWARE_FLAGS=-DBSIM\nendif\n\nexport KROOT=/lib/modules/$(shell uname -r)/build\nCPPDIR=../../../cpp\nBOARDDIR=../$(BOARD)/jni\nDRIVERDIR=$(src)/../../../drivers\n\nKBUILD_EXTRA_SYMBOLS := $(DRIVERDIR)/pcieportal/Module.symvers $(DRIVERDIR)/portalmem/Module.symvers\n\nkernel_exe-y := ../memread_manual_manager.o \\\n     $(BOARDDIR)/MMURequestProxy.o \\\n     $(BOARDDIR)/MMUIndicationWrapper.o \\\n     $(BOARDDIR)/MemServerRequestProxy.o \\\n     $(BOARDDIR)/MemServerIndicationWrapper.o \\\n     $(BOARDDIR)/RtestIndicationWrapper.o \\\n     $(BOARDDIR)/RtestRequestProxy.o \\\n     $(CPPDIR)/portal.o \\\n     $(CPPDIR)/dmaManager.o \\\n     $(CPPDIR)/kernel_module.o\n\nifeq ($(BOARD),bluesim)\nkernel_exe-y += $(CPPDIR)/sock_utils.o\nendif\n\nobj-m := kernel_exe.o\n\nccflags-y := -I$(src)/.. -I$(DRIVERDIR)/pcieportal -I$(DRIVERDIR)/portalmem -I$(src)/$(CPPDIR) -I$(src)/$(BOARDDIR) $(HARDWARE_FLAGS) -DBOARD_$(BOARD)\n\ndefault:\n\t$(MAKE) -C $(KROOT) M=$(PWD) modules\n\nclean:\n\t$(MAKE) -C $(KROOT) M=$(PWD) clean\n\trm -f $(kernel_exe-y) a.out bsim_relay\n\nCURRENTMOD=$(shell lsmod | grep kernel_exe)\n\nrun: host\nifeq ($(BOARD),bluesim)\n\t@echo running bsim\n\t../bluesim/bin/bsim& echo $$! >tmp.bluesim.makefile.pid\nelse\n\tfpgajtag ../$(BOARD)/bin/mkTop.bin.gz\nendif\nifneq (\"$(CURRENTMOD)\", \"\")\n\tsudo rmmod kernel_exe\nendif\n\tsudo insmod kernel_exe.ko\nifeq ($(BOARD),bluesim)\n\t./bsim_relay\n\tkill `cat tmp.bluesim.makefile.pid`\n\t#killall bluetcl\nendif\n\tsudo rmmod kernel_exe\n\tdmesg | tail -30\n\t@rm -f tmp.bluesim.makefile.pid\n\n#\n# Target for making userspace bsim_relay program\nCPPDIR=../../../cpp\nHOSTSOURCES=$(CPPDIR)/bsim_relay.c $(CPPDIR)/sock_utils.c\n\nhost: $(HOSTSOURCES)\nifeq ($(BOARD),bluesim)\n\tgcc -o bsim_relay -g -I$(CPPDIR) $(HOSTSOURCES) -lpthread\nendif\n"
  },
  {
    "path": "tests/memread_manual/memread_manual_manager.c",
    "content": "/* Copyright (c) 2014 Quanta Research Cambridge, Inc\n *\n * Permission is hereby granted, free of charge, to any person obtaining a\n * copy of this software and associated documentation files (the \"Software\"),\n * to deal in the Software without restriction, including without limitation\n * the rights to use, copy, modify, merge, publish, distribute, sublicense,\n * and/or sell copies of the Software, and to permit persons to whom the\n * Software is furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n * DEALINGS IN THE SOFTWARE.\n */\n\n#ifdef __KERNEL__\n#include <linux/delay.h>  // msleep\n#include <linux/kthread.h>\n#else\n#include <string.h>\n#include <sys/mman.h>\n#include <pthread.h>\n#include <fcntl.h>\n#include <sys/select.h>\n#endif\n\n#include \"dmaManager.h\"\n#include \"sock_utils.h\"  // bsim_poll_interrupt()\n#include \"GeneratedTypes.h\" \n\n#define MAX_INDARRAY 4\n#if defined(BSIM) || defined(BOARD_xsim)\n#define numBytes 0x1240\n#else\n#define numBytes 0x1240000 // make sure to allocate at least one entry of each size\n#endif\n\nstatic PortalInternal intarr[MAX_INDARRAY];\nstatic sem_t test_sem;\nstatic int burstLen = 16 * sizeof(uint32_t);\nstatic DmaManagerPrivate priv;\n\nint ReadTestIndicationWrapperreadDone_cb (  struct PortalInternal *p, const uint32_t mismatchCount )\n{\n    PORTAL_PRINTF( \"ReadTest_readDone(mismatch = %x)\\n\", mismatchCount);\n    sem_post(&test_sem);\n    return 0;\n}\nint MMUIndicationWrapperconfigResp_cb (  struct PortalInternal *p, const uint32_t pointer)\n{\n    //PORTAL_PRINTF(\"configResp %x\\n\", pointer);\n    sem_post(&priv.confSem);\n    return 0;\n}\nint MMUIndicationWrapperidResponse_cb (  struct PortalInternal *p, const uint32_t sglId ) {\n    priv.sglId = sglId;\n    sem_post(&priv.sglIdSem);\n    return 0;\n};\nint MMUIndicationWrappererror_cb (  struct PortalInternal *p, const uint32_t code, const uint32_t pointer, const uint64_t offset, const uint64_t extra ) {\n    static int maxnumber = 10;\n    if (maxnumber-- > 0)\n        PORTAL_PRINTF(\"DmaIndication::dmaError(code=%x, pointer=%x, offset=%\"PRIx64\" extra=%\"PRIx64\"\\n\", code, pointer, offset, extra);\n    return 0;\n}\n\nvoid manual_event(void)\n{\n    int i;\n\n    for (i = 0; i < MAX_INDARRAY; i++)\n        intarr[i].item->event(&intarr[i]);\n}\n\n#ifdef __KERNEL__\nDECLARE_COMPLETION(worker_completion);\n#endif\nstatic void *pthread_worker(void *p)\n{\n    void *rc = NULL;\n    while (1) {\n#if defined(BSIM) && !defined(__KERNEL__)\n        if (bsim_poll_interrupt())\n#endif\n            manual_event();\n#ifdef __KERNEL__\n        msleep(10);\n        if (kthread_should_stop())\n            break;\n#else ///////////////////////// userspace version\n        struct timeval timeout;\n        timeout.tv_sec = 0;\n        timeout.tv_usec = 10000;\n        select(0, NULL, NULL, NULL, &timeout);\n#endif\n    }\n#ifdef __KERNEL__\n    complete(&worker_completion);\n#endif\n    return rc;\n}\n\nstatic MMUIndicationCb TestMMUIndication_cbTable = {\n    portal_disconnect,\n    MMUIndicationWrapperidResponse_cb,\n    MMUIndicationWrapperconfigResp_cb,\n    MMUIndicationWrappererror_cb,\n};\nstatic ReadTestIndicationCb TestReadTestIndication_cbTable = {\n    portal_disconnect,\n    ReadTestIndicationWrapperreadDone_cb,\n};\nint main(int argc, const char **argv)\n{\n    int srcAlloc;\n    unsigned int *srcBuffer;\n    unsigned int ref_srcAlloc;\n    unsigned int i;\n    pthread_t tid = 0;\n\n    init_portal_internal(&intarr[0], IfcNames_MMUIndicationH2S,     0, MMUIndication_handleMessage, &TestMMUIndication_cbTable, NULL, NULL, MMUIndication_reqinfo);// fpga1\n    init_portal_internal(&intarr[1], IfcNames_ReadTestIndicationH2S,DEFAULT_TILE, ReadTestIndication_handleMessage, &TestReadTestIndication_cbTable, NULL, NULL, ReadTestIndication_reqinfo); // fpga2\n    init_portal_internal(&intarr[2], IfcNames_MMURequestS2H,     0, NULL, NULL, NULL, NULL, MMURequest_reqinfo); // fpga3\n    init_portal_internal(&intarr[3], IfcNames_ReadTestRequestS2H,DEFAULT_TILE, NULL, NULL, NULL, NULL, ReadTestRequest_reqinfo);    // fpga4\n\n    sem_init(&test_sem, 0, 0);\n    DmaManager_init(&priv, &intarr[2]);\n    srcAlloc = portalAlloc(numBytes, 0);\n    if (srcAlloc < 0){\n        PORTAL_PRINTF(\"portal alloc failed rc=%d\\n\", srcAlloc);\n        return srcAlloc;\n    }\n    srcBuffer = (unsigned int *)portalMmap(srcAlloc, numBytes);\n    for (i = 0; i < numBytes/sizeof(srcBuffer[0]); i++)\n        srcBuffer[i] = i;\n    portalCacheFlush(srcAlloc, srcBuffer, numBytes, 1);\n\n    PORTAL_PRINTF( \"Main: creating exec thread\\n\");\n    if(pthread_create(&tid, NULL, pthread_worker, NULL)){\n       PORTAL_PRINTF( \"error creating exec thread\\n\");\n       return -1;\n    }\n\n    PORTAL_PRINTF( \"Test 1: check for match\\n\");\n    PORTAL_PRINTF( \"Main: before DmaManager_reference(%x)\\n\", srcAlloc);\n    ref_srcAlloc = DmaManager_reference(&priv, srcAlloc);\n    PORTAL_PRINTF( \"Main: starting read %08x\\n\", numBytes);\n    ReadTestRequest_startRead (&intarr[3], ref_srcAlloc, numBytes, burstLen, 1);\n    PORTAL_PRINTF( \"Main: waiting for semaphore1\\n\");\n    sem_wait(&test_sem);\n\n    PORTAL_PRINTF( \"Test 2: check that mismatch is detected\\n\");\n    srcBuffer[0] = -1;\n    srcBuffer[numBytes/sizeof(srcBuffer[0])/2] = -1;\n    srcBuffer[numBytes/sizeof(srcBuffer[0])-1] = -1;\n    portalCacheFlush(srcAlloc, srcBuffer, numBytes, 1);\n\n    ReadTestRequest_startRead (&intarr[3], ref_srcAlloc, numBytes, burstLen, 1);\n    PORTAL_PRINTF( \"Main: waiting for semaphore2\\n\");\n    sem_wait(&test_sem);\n\n    PORTAL_PRINTF( \"Main: all done\\n\");\n#ifdef __KERNEL__\n    if (tid && !kthread_stop (tid)) {\n        printk(\"kthread stops\");\n    }\n    wait_for_completion(&worker_completion);\n#endif\n\n#ifdef __KERNEL__\n    portalmem_dmabuffer_destroy(srcAlloc);\n#endif\n    return 0;\n}\n"
  },
  {
    "path": "tests/memread_manual/vc707_floorplan.xdc",
    "content": "startgroup\ncreate_pblock pblock_ep7\nresize_pblock pblock_ep7 -add {SLICE_X184Y54:SLICE_X221Y166 DSP48_X18Y22:DSP48_X19Y65 RAMB18_X12Y22:RAMB18_X14Y65 RAMB36_X12Y11:RAMB36_X14Y32}\nadd_cells_to_pblock pblock_ep7 [get_cells [list ep7]] -clear_locs\nendgroup\n\nstartgroup\ncreate_pblock pblock_pciehost\nresize_pblock pblock_pciehost -add {SLICE_X112Y55:SLICE_X171Y197 DSP48_X9Y22:DSP48_X16Y77 RAMB18_X7Y22:RAMB18_X10Y77 RAMB36_X7Y11:RAMB36_X10Y38 BUFGCTRL_X0Y16}\nadd_cells_to_pblock pblock_pciehost [get_cells [list pciehost]] -clear_locs\nendgroup\n\nstartgroup\ncreate_pblock pblock_portalTop\nresize_pblock pblock_portalTop -add {SLICE_X0Y25:SLICE_X101Y247 DSP48_X0Y10:DSP48_X7Y97 RAMB18_X0Y10:RAMB18_X6Y97 RAMB36_X0Y5:RAMB36_X6Y48}\nadd_cells_to_pblock pblock_portalTop [get_cells [list portalTop]] -clear_locs\nendgroup\n"
  },
  {
    "path": "tests/memread_manyclients/Makefile",
    "content": "CONNECTALDIR?=../..\nMEMREADDIR=$(CONNECTALDIR)/examples/memread\nS2H_INTERFACES = ReadTestRequest:ReadTest.request\nH2S_INTERFACES = ReadTest:ReadTestIndication\nMEM_READ_INTERFACES = lReadTest.dmaClient\n\nBSVFILES = $(MEMREADDIR)/ReadTest.bsv\nCPPFILES = $(MEMREADDIR)/testmemread.cpp\nCONNECTALFLAGS += -D NumEngineServers=16\nCONNECTALFLAGS += -I$(CONNECTALDIR)/examples/memread\n\ninclude $(CONNECTALDIR)/Makefile.connectal\n"
  },
  {
    "path": "tests/memread_manyclients/performance.txt",
    "content": "\nMemread Manyclients\nDataBusWidth | BufferSize | NumServers | NumRequests | Utilization | Bandwidth\n     64      |    256     |    16      | 2           | 0.944658    | 0.995 GB/s\n    128      |    256     |    16      | 2           | 0.559449    | 1.119 GB/s\n    128      |    256     |    16      | 4           | locks up\n    128      |    512     |     8      | 4           | locks up    \n    128      |    512     |     8      | 2           | stalls\n    128      |    512     |     1      | 2           | \n"
  },
  {
    "path": "tests/memread_manyclients128/Makefile",
    "content": "CONNECTALDIR?=../..\nMEMREADDIR=$(CONNECTALDIR)/examples/memread\nS2H_INTERFACES = MemreadRequest:Memread.request\nH2S_INTERFACES = Memread:MemreadIndication\nMEM_READ_INTERFACES = lMemread.dmaClient\n\nBSVFILES = $(MEMREADDIR)/Memread.bsv\nCPPFILES = $(MEMREADDIR)/testmemread.cpp\nCONNECTALFLAGS += -D NumEngineServers=8 -D DataBusWidth=128\nCONNECTALFLAGS += -I$(CONNECTALDIR)/examples/memread\n\ninclude $(CONNECTALDIR)/Makefile.connectal\n"
  },
  {
    "path": "tests/memread_manyengines/Makefile",
    "content": "CONNECTALDIR?=../..\nS2H_INTERFACES = ReadTestRequest:ReadTest.request\nH2S_INTERFACES = ReadTest\\#\\(\\`NumEngines\\):ReadTestIndication\nMEM_READ_INTERFACES = lReadTest.dmaClients\n\nBSVFILES = ReadTest.bsv\nCPPFILES = ../../examples/memread/testmemread.cpp\nCONNECTALFLAGS += --bscflags \" -D DataBusWidth=128 -D NumEngines=4\"\nCONNECTALFLAGS += -I$(CONNECTALDIR)/examples/memread\n\ninclude $(CONNECTALDIR)/Makefile.connectal\n\n"
  },
  {
    "path": "tests/memread_manyengines/ReadTest.bsv",
    "content": "// Copyright (c) 2013 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\nimport FIFO::*;\nimport FIFOF::*;\nimport Vector::*;\nimport StmtFSM::*;\nimport GetPut::*;\nimport ClientServer::*;\nimport Pipe::*;\nimport ConnectalMemTypes::*;\nimport MemReadEngine::*;\nimport ConnectalConfig::*;\n\ninterface ReadTestRequest;\n   method Action startRead(Bit#(32) pointer, Bit#(32) numBytes, Bit#(32) burstLen, Bit#(32) iterCnt);\n   method Action getStateDbg();   \nendinterface\n\ninterface ReadTest#(numeric type nClients);\n   interface ReadTestRequest request;\n   interface Vector#(nClients,MemReadClient#(DataBusWidth)) dmaClients;\nendinterface\n\ninterface ReadTestIndication;\n   method Action started(Bit#(32) numBytes);\n   method Action reportStateDbg(Bit#(32) streamRdCnt, Bit#(32) mismatchCount);\n   method Action readDone(Bit#(32) mismatchCount);\nendinterface\n\nmodule mkReadTest#(ReadTestIndication indication) (ReadTest#(4));\n\n   Reg#(SGLId)     pointer <- mkReg(0);\n   Reg#(Bit#(32))         numBytes <- mkReg(0);\n   Reg#(Bit#(BurstLenSize)) burstLenBytes <- mkReg(0);\n   Reg#(Bit#(32))          itersToStart <- mkReg(0);\n   Reg#(Bit#(32))        startBase <- mkReg(0);\n   Reg#(Bit#(3))          startPtr <- mkReg(0);\n   Reg#(Bit#(3))         finishPtr <- mkReg(0);\n   Reg#(Bit#(32))    mismatchAccum <- mkReg(0);\n   Vector#(4,MemReadEngine#(DataBusWidth,DataBusWidth,1,1))      res <- replicateM(mkMemReadEngine);\n   FIFO#(void)           startFifo <- mkFIFO;\n   \n   Vector#(4,Reg#(Bit#(32)))        srcGens <- replicateM(mkReg(0));\n   Vector#(4,Reg#(Bit#(32))) mismatchCounts <- replicateM(mkReg(0));\n   Vector#(4,FIFO#(void)) doneFifo <- replicateM(mkFIFO);\n   \n   Stmt startStmt = seq\n\t\t       startBase <= 0;\n\t\t       for(startPtr <= 0; startPtr < 4; startPtr <= startPtr+1)\n\t\t\t  (action\n\t\t\t      let cmd = MemengineCmd{sglId:pointer, base:extend(startBase), len:numBytes, burstLen:truncate(burstLenBytes), tag:0};\n\t\t\t      res[startPtr].readServers[0].request.put(cmd);\n\t\t\t      startBase <= startBase+numBytes;\n\t\t\t      //$display(\"start:%d %h %d %h (%d)\", startPtr, startBase, numBytes, burstLenBytes*4, itersToStart);\n\t\t\t   endaction);\n\t\t    endseq;\n   FSM startFSM <- mkFSM(startStmt);\n\n   Stmt finishStmt = seq\n\t\t\tmismatchAccum <= 0;\n\t\t\tfor(finishPtr <= 0; finishPtr < 4; finishPtr <= finishPtr+1)\n\t\t\t   mismatchAccum <= mismatchAccum + mismatchCounts[finishPtr];\n\t\t\tindication.readDone(mismatchAccum);\n\t\t\t//$display(\"finishStmt: %h\", mismatchAccum);\n\t\t    endseq;\n   FSM finishFSM <- mkFSM(finishStmt);\n   \n   rule start (itersToStart > 0);\n      startFifo.deq;\n      startFSM.start;\n      itersToStart <= itersToStart-1;\n   endrule\n   \n   rule finish;\n      for(Integer i = 0; i < 4; i=i+1)\n         doneFifo[i].deq;\n      //$display(\"finish: %d (%d)\", i, itersToStart);\n      if (itersToStart == 0)\n\t finishFSM.start;\n      else\n\t startFifo.enq(?);\n   endrule\n   \n   for(Integer i = 0; i < 4; i=i+1)\n      rule check;\n\t let v <- toGet(res[i].readServers[0].data).get;\n\t let expectedV = {srcGens[i]+3,srcGens[i]+2,srcGens[i]+1,srcGens[i]};\n\t let misMatch = v.data != expectedV;\n\t mismatchCounts[i] <= mismatchCounts[i] + (misMatch ? 1 : 0);\n\t if (srcGens[i]+4 == fromInteger(i+1)*(numBytes>>2)) begin\n\t    //$display(\"check %d %d\", i, srcGens[i]+1);\n\t    srcGens[i] <= fromInteger(i)*(numBytes>>2);\n\t end\n\t else\n\t    srcGens[i] <= srcGens[i]+4;\n         if (v.last)\n            doneFifo[i].enq(?);\n      endrule\n   \n   function MemReadClient#(DataBusWidth) dc(MemReadEngine#(DataBusWidth,DataBusWidth,1,1) re) = re.dmaClient;\n   interface dmaClients = map(dc,res);\n   interface ReadTestRequest request;\n      method Action startRead(Bit#(32) rp, Bit#(32) nb, Bit#(32) bl, Bit#(32) ic);\n\t //$display(\"startRead rdPointer=%d numBytes=%h burstLenBytes=%d itersToStart=%d\", rp, nb, bl, ic);\n\t indication.started(nb);\n\t pointer <= rp;\n\t numBytes  <= nb;\n\t burstLenBytes  <= truncate(bl);\n\t itersToStart <= ic;\n\t for(Integer i = 0; i < 4; i=i+1) begin\n\t    mismatchCounts[i] <= 0;\n\t    srcGens[i] <= fromInteger(i)*(nb>>2);\n\t end\n\t startFifo.enq(?);\n      endmethod\n      method Action getStateDbg();\n\t indication.reportStateDbg(itersToStart, mismatchCounts[0]);\n      endmethod\n   endinterface\nendmodule\n"
  },
  {
    "path": "tests/memserver_copy/Makefile",
    "content": "CONNECTALDIR?=../..\nS2H_INTERFACES = MemcopyRequest:Memcopy.request\nH2S_INTERFACES = Memcopy:MemcopyIndication\nMEM_READ_INTERFACES = lMemcopy.readClients\nMEM_WRITE_INTERFACES = lMemcopy.writeClients\n\nBSVFILES = ../memserver_copy/Memcopy.bsv\nCPPFILES = ../memserver_copy/testmemcopy.cpp\nCONNECTALFLAGS += -D USE_ACP -P mkConnectalTop\n\ninclude $(CONNECTALDIR)/Makefile.connectal\n"
  },
  {
    "path": "tests/memserver_copy/Memcopy.bsv",
    "content": "// Copyright (c) 2013 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\nimport Vector::*;\nimport BuildVector::*;\nimport FIFO::*;\nimport FIFOF::*;\nimport BRAMFIFO::*;\nimport ClientServer::*;\nimport GetPut::*;\nimport ConnectalConfig::*;\nimport ConnectalMemTypes::*;\nimport Pipe::*;\nimport ConfigCounter::*;\n\ntypedef TDiv#(DataBusWidth,32) WordsPerBeat;\n\ninterface MemcopyRequest;\n   method Action startCopy(Bit#(32) readPointer, Bit#(32) writePointer, Bit#(32) numWords, Bit#(32) numReqs, Bit#(32) burstLen);\nendinterface\n\ninterface MemcopyIndication;\n   method Action copyDone(Bit#(32) v);\n   method Action copyProgress(Bit#(32) v);\nendinterface\n\ninterface Memcopy;\n   interface MemcopyRequest request;\n   interface Vector#(1, MemReadClient#(DataBusWidth)) readClients;\n   interface Vector#(1, MemWriteClient#(DataBusWidth)) writeClients;\nendinterface\n\nmodule  mkMemcopy#(MemcopyIndication indication) (Memcopy);\n   Reg#(SGLId)   readPointer <- mkReg(0);\n   Reg#(SGLId)   writePointer <- mkReg(0);\n   Reg#(Bit#(32))        numReqs <- mkReg(0);\n   Reg#(Bit#(32))        numDone <- mkReg(0);\n   Reg#(Bit#(MemOffsetSize)) reqOffset <- mkReg(0);\n   Reg#(Bit#(3))                   tag <- mkReg(0);\n   Reg#(Bit#(32))             numWords <- mkReg(0);\n   Reg#(Bit#(BurstLenSize)) burstLenBytes <- mkReg(0);\n   Reg#(Bit#(32))              srcGens <- mkReg(0);\n\n   ConfigCounter#(16) counter          <- mkConfigCounter(0);\n   FIFO#(MemRequest) readReqFifo <- mkFIFO();\n   FIFO#(MemRequest) writeReqFifo <- mkFIFO();\n   FIFO#(MemData#(DataBusWidth))   dataFifo <- mkSizedBRAMFIFO(1024);\n   FIFO#(Bit#(MemTagSize)) doneFifo <- mkFIFO();\n\n   let verboseProgress = False;\n\n   rule startReqRule if (numReqs != 0 && counter.read() <= unpack(extend(burstLenBytes) << 3));\n      counter.increment(unpack(extend(burstLenBytes)));\n      readReqFifo.enq(MemRequest { sglId: readPointer, offset: reqOffset, burstLen: burstLenBytes, tag: extend(tag) });\n      writeReqFifo.enq(MemRequest { sglId: writePointer, offset: reqOffset, burstLen: burstLenBytes, tag: extend(tag) });\n\n      numReqs <= numReqs - 1;\n      reqOffset <= reqOffset + extend(burstLenBytes);\n      tag <= tag + 1;\n      $display(\"start numReqs %d offset %d\", numReqs, reqOffset);\n   endrule\n\n   rule finish;\n      let donetag <- toGet(doneFifo).get();\n      $display(\"finished num todo=%d\", numDone);\n      if (numDone == 1) begin\n         indication.copyDone(0);\n      end\n      numDone <= numDone - 1;\n      if (verboseProgress)\n\t indication.copyProgress(extend(donetag));\n   endrule\n\n   MemReadClient#(DataBusWidth) readClient = (interface MemReadClient;\n      interface Get readReq = toGet(readReqFifo);\n      interface Put readData;\n\t method Action put(MemData#(DataBusWidth) md);\n\t    dataFifo.enq(md);\n\t    counter.decrement(fromInteger(valueOf(TDiv#(DataBusWidth,8))));\n\t endmethod\n      endinterface\n   endinterface );\n   MemWriteClient#(DataBusWidth) writeClient = (interface MemWriteClient;\n      interface Get writeReq = toGet(writeReqFifo);\n      interface Get writeData = toGet(dataFifo);\n      interface Put writeDone = toPut(doneFifo);\n   endinterface );\n\n   interface MemcopyRequest request;\n       method Action startCopy(Bit#(32) rp, Bit#(32) wp, Bit#(32) nw, Bit#(32) nreq, Bit#(32) bl);\n\t  //$dumpvars();\n          $display(\"startCopy readPointer=%d writePointer=%d numWords=%d (%d) numReqs=%d burstLen=%d\", rp, wp, nw, nreq*bl, nreq, bl);\n          readPointer <= rp;\n          writePointer <= wp;\n          numWords  <= nw;\n          burstLenBytes <= truncate(bl);\n\t  numReqs <= nreq;\n\t  numDone <= nreq;\n       endmethod\n   endinterface\n   interface readClients = vec(readClient);\n   interface writeClients = vec(writeClient);\n\nendmodule\n"
  },
  {
    "path": "tests/memserver_copy/testmemcopy.cpp",
    "content": "/* Copyright (c) 2014 Quanta Research Cambridge, Inc\n *\n * Permission is hereby granted, free of charge, to any person obtaining a\n * copy of this software and associated documentation files (the \"Software\"),\n * to deal in the Software without restriction, including without limitation\n * the rights to use, copy, modify, merge, publish, distribute, sublicense,\n * and/or sell copies of the Software, and to permit persons to whom the\n * Software is furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n * DEALINGS IN THE SOFTWARE.\n */\n#include \"dmaManager.h\"\n#include \"MemcopyIndication.h\"\n#include \"MemcopyRequest.h\"\n\nstatic void memdump(unsigned char *p, int len, const char *title)\n{\nint i;\n\n    i = 0;\n    while (len > 0) {\n        if (!(i & 0xf)) {\n            if (i > 0)\n                printf(\"\\n\");\n            printf(\"%s: \",title);\n        }\n        printf(\"%02x \", *p++);\n        i++;\n        len--;\n    }\n    printf(\"\\n\");\n}\n\nstatic sem_t done_sem;\nclass MemcopyIndication : public MemcopyIndicationWrapper\n{\npublic:\n  MemcopyIndication(int id) : MemcopyIndicationWrapper(id){}\n\n  virtual void copyDone ( uint32_t srcGen ){\n    fprintf(stderr, \"Memcopy::writeDone (%08x)\\n\", srcGen);\n    sem_post(&done_sem);\n  }\n  virtual void copyProgress ( uint32_t numtodo ){\n    fprintf(stderr, \"Memcopy::writeProgress (%08x)\\n\", numtodo);\n  }\n};\n\nint main(int argc, const char **argv)\n{\n#ifdef SIMULATION\n  size_t alloc_sz = 4*1024;\n#else\n  size_t alloc_sz = 10*1024*1024;\n#endif\n  MemcopyRequestProxy *device = new MemcopyRequestProxy(IfcNames_MemcopyRequestS2H);\n  MemcopyIndication deviceIndication(IfcNames_MemcopyIndicationH2S);\n  DmaManager *dma = platformInit();\n  sem_init(&done_sem, 1, 0);\n\n  int srcAlloc = portalAlloc(alloc_sz, 0);\n  unsigned int *srcBuffer = (unsigned int *)portalMmap(srcAlloc, alloc_sz);\n  int dstAlloc = portalAlloc(alloc_sz, 0);\n  unsigned int *dstBuffer = (unsigned int *)portalMmap(dstAlloc, alloc_sz);\n\n  for (size_t i = 0; i < alloc_sz/sizeof(uint32_t); i++) {\n    srcBuffer[i] = 7*i-3;\n    dstBuffer[i] = 0xDEADBEEF;\n  }\n\n#ifndef USE_ACP\n  fprintf(stderr, \"flushing cache\\n\");\n  portalCacheFlush(dstAlloc, dstBuffer, alloc_sz, 1);\n#endif\n\n  fprintf(stderr, \"parent::starting write\\n\");\n  unsigned int ref_srcAlloc = dma->reference(srcAlloc);\n  unsigned int ref_dstAlloc = dma->reference(dstAlloc);\n  int burstLenBytes = 32*sizeof(uint32_t);\n\n  portalTimerStart(0);\n  device->startCopy(ref_srcAlloc, ref_dstAlloc, alloc_sz, alloc_sz / burstLenBytes, burstLenBytes);\n  sem_wait(&done_sem);\n  platformStatistics();\n\n  memdump((unsigned char *)dstBuffer, 32, \"MEM\");\n  int mismatchCount = 0;\n  for (size_t i = 0; i < alloc_sz/sizeof(uint32_t); i++) {\n    if (dstBuffer[i] != srcBuffer[i])\n      mismatchCount++;\n  }\n  fprintf(stderr, \"%s: done mismatchCount=%d\\n\", __FUNCTION__, mismatchCount);\n  return (mismatchCount == 0) ? 0 : 1;\n}\n"
  },
  {
    "path": "tests/memserver_copy128/Makefile",
    "content": "CONNECTALDIR?=../..\nS2H_INTERFACES = MemcopyRequest:Memcopy.request\nH2S_INTERFACES = Memcopy:MemcopyIndication\nMEM_READ_INTERFACES = lMemcopy.readClients\nMEM_WRITE_INTERFACES = lMemcopy.writeClients\n\nBSVFILES = ../memserver_copy/Memcopy.bsv\nCPPFILES = ../memserver_copy/testmemcopy.cpp\nCONNECTALFLAGS += -D USE_ACP -P mkConnectalTop -D DataBusWidth=128\n\ninclude $(CONNECTALDIR)/Makefile.connectal\n"
  },
  {
    "path": "tests/memserver_copy_slow/Makefile",
    "content": "include ../memserver_copy/Makefile\n\nCONNECTALFLAGS += --mainclockperiod=30\n"
  },
  {
    "path": "tests/memserver_write/Makefile",
    "content": "CONNECTALDIR?=../..\nS2H_INTERFACES = MemwriteRequest:Memwrite.request\nH2S_INTERFACES = Memwrite:MemwriteIndication\nMEM_WRITE_INTERFACES = lMemwrite.dmaClients\n\nBSVFILES = Memwrite.bsv\nCPPFILES = testmemwrite.cpp\nCONNECTALFLAGS += -D USE_ACP -P mkConnectalTop -D BYTE_ENABLES\n\ninclude $(CONNECTALDIR)/Makefile.connectal\n"
  },
  {
    "path": "tests/memserver_write/Memwrite.bsv",
    "content": "// Copyright (c) 2013 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\n`include \"ConnectalProjectConfig.bsv\"\nimport Vector::*;\nimport BuildVector::*;\nimport FIFO::*;\nimport FIFOF::*;\nimport BRAMFIFO::*;\nimport ClientServer::*;\nimport GetPut::*;\nimport ConnectalConfig::*;\nimport ConnectalMemTypes::*;\nimport MemWriteEngine::*;\nimport Pipe::*;\nimport AddressGenerator::*;\n\ntypedef TDiv#(DataBusWidth,32) WordsPerBeat;\n\ninterface MemwriteRequest;\n   method Action startWrite(Bit#(32) pointer, Bit#(32) numWords, Bit#(32) numReqs, Bit#(32) burstLen, Bit#(8) byteEnable);\nendinterface\n\ninterface MemwriteIndication;\n   method Action writeDone(Bit#(32) v);\n   method Action writeProgress(Bit#(32) v);\nendinterface\n\ninterface Memwrite;\n   interface MemwriteRequest request;\n   interface Vector#(1, MemWriteClient#(DataBusWidth)) dmaClients;\nendinterface\n\nmodule  mkMemwrite#(MemwriteIndication indication) (Memwrite);\n   Reg#(SGLId)   pointer <- mkReg(0);\n   Reg#(Bit#(32))        numReqs <- mkReg(0);\n   Reg#(Bit#(32))        numDone <- mkReg(0);\n   Reg#(Bit#(MemOffsetSize)) reqOffset <- mkReg(0);\n   Reg#(Bit#(3))                   tag <- mkReg(0);\n   Reg#(Bit#(32))             numWords <- mkReg(0);\n   Reg#(Bit#(BurstLenSize)) burstLenBytes <- mkReg(0);\n   Reg#(Bit#(32))              srcGens <- mkReg(3);\n   Reg#(Bit#(8))            byteEnable <- mkReg('hff);\n\n   AddressGenerator#(32, DataBusWidth) addrGenerator <- mkAddressGenerator();\n   FIFO#(MemRequest) reqFifo <- mkSizedFIFO(4);\n   FIFO#(PhysMemRequest#(32,DataBusWidth)) preqFifo <- mkSizedFIFO(4);\n   FIFO#(MemData#(DataBusWidth))   dataFifo <- mkSizedBRAMFIFO(1024);\n   FIFO#(Bit#(MemTagSize)) doneFifo <- mkSizedFIFO(4);\n\n   let verboseProgress = False;\n\n`ifdef BYTE_ENABLES\n   Bit#(TDiv#(DataBusWidth,8)) firstbe = maxBound;\n   Bit#(TDiv#(DataBusWidth,8)) lastbe = maxBound;\n   // just apply the byteEnable to the first and last 32-bit word of a burst\n   firstbe[3:0] = byteEnable[3:0];\n   lastbe[valueOf(ByteEnableSize)-1:valueOf(ByteEnableSize)-4] = byteEnable[7:4];\n`endif\n\n   rule start if (numReqs != 0);\n`ifdef BYTE_ENABLES\n      $display(\"Memwrite.start firstbe=%h lastbe=%h\", firstbe, lastbe);\n`endif\n      reqFifo.enq(MemRequest { sglId: pointer, offset: reqOffset, burstLen: burstLenBytes, tag: extend(tag)\n`ifdef BYTE_ENABLES\n\t\t\t      , firstbe: firstbe, lastbe: lastbe\n`endif\n\t\t\t      });\n      preqFifo.enq(PhysMemRequest { addr: 0, burstLen: burstLenBytes, tag: extend(tag)\n`ifdef BYTE_ENABLES\n\t\t\t\t       , firstbe: firstbe, lastbe: lastbe\n`endif\n\t\t\t\t   });\n      numReqs <= numReqs - 1;\n      reqOffset <= reqOffset + extend(burstLenBytes);\n      tag <= tag + 1;\n      //$display(\"start numReqs\", numReqs);\n   endrule\n\n   rule preq;\n      let preq <- toGet(preqFifo).get();\n      addrGenerator.request.put(preq);\n   endrule\n\n   rule finish;\n      let donetag <- toGet(doneFifo).get();\n      //$display(\"finished num todo=%d\", numDone);\n      if (numDone == 1) begin\n         indication.writeDone(0);\n      end\n      numDone <= numDone - 1;\n      if (verboseProgress)\n\t indication.writeProgress(extend(donetag));\n   endrule\n\n   rule src if (numWords != 0);\n      let b <- addrGenerator.addrBeat.get();\n\n      function Bit#(32) plusi(Integer i); return srcGens + fromInteger(i); endfunction\n      Vector#(WordsPerBeat, Bit#(32)) v = genWith(plusi);\n      dataFifo.enq(MemData { data: pack(v), tag: b.tag, last: b.last});\n      srcGens <= srcGens+fromInteger(valueOf(WordsPerBeat));\n      numWords <= numWords - fromInteger(valueOf(WordsPerBeat));\n   endrule\n\n   MemWriteClient#(DataBusWidth) dmaClient = (interface MemWriteClient;\n      interface Get writeReq = toGet(reqFifo);\n      interface Get writeData = toGet(dataFifo);\n      interface Put writeDone = toPut(doneFifo);\n   endinterface );\n\n   interface MemwriteRequest request;\n       method Action startWrite(Bit#(32) wp, Bit#(32) nw, Bit#(32) nreq, Bit#(32) bl, Bit#(8) be);\n\t  //$dumpvars();\n          $display(\"startWrite pointer=%d numWords=%d (%d) numReqs=%d burstLen=%d\", pointer, nw, nreq*bl, nreq, bl);\n          pointer <= wp;\n          numWords  <= nw;\n          burstLenBytes <= truncate(bl);\n\t  numReqs <= nreq;\n\t  numDone <= nreq;\n\n\t  reqOffset <= 0;\n\t  srcGens <= 3;\n\t  byteEnable <= be;\n       endmethod\n   endinterface\n   interface dmaClients = vec(dmaClient);\n\nendmodule\n\n"
  },
  {
    "path": "tests/memserver_write/testmemwrite.cpp",
    "content": "/* Copyright (c) 2014 Quanta Research Cambridge, Inc\n *\n * Permission is hereby granted, free of charge, to any person obtaining a\n * copy of this software and associated documentation files (the \"Software\"),\n * to deal in the Software without restriction, including without limitation\n * the rights to use, copy, modify, merge, publish, distribute, sublicense,\n * and/or sell copies of the Software, and to permit persons to whom the\n * Software is furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n * DEALINGS IN THE SOFTWARE.\n */\n#include <sys/mman.h>\n#include <errno.h>\n#include \"dmaManager.h\"\n#include \"MemwriteIndication.h\"\n#include \"MemwriteRequest.h\"\n\nstatic void memdump(unsigned char *p, int len, const char *title)\n{\nint i;\n\n    i = 0;\n    while (len > 0) {\n        if (!(i & 0xf)) {\n            if (i > 0)\n                printf(\"\\n\");\n            printf(\"%s: \",title);\n        }\n        printf(\"%02x \", *p++);\n        i++;\n        len--;\n    }\n    printf(\"\\n\");\n}\n\nstatic sem_t done_sem;\nclass MemwriteIndication : public MemwriteIndicationWrapper\n{\npublic:\n  MemwriteIndication(int id) : MemwriteIndicationWrapper(id){}\n\n  virtual void writeDone ( uint32_t srcGen ){\n    fprintf(stderr, \"Memwrite::writeDone (%08x)\\n\", srcGen);\n    sem_post(&done_sem);\n  }\n  virtual void writeProgress ( uint32_t numtodo ){\n    fprintf(stderr, \"Memwrite::writeProgress (%08x)\\n\", numtodo);\n  }\n};\n\nMemwriteIndication *deviceIndication;\nint main(int argc, const char **argv)\n{\n#ifdef SIMULATION\n  size_t alloc_sz = 4*1024;\n#else\n  size_t alloc_sz = 16*1024*1024;\n#endif\n  MemwriteRequestProxy *device = new MemwriteRequestProxy(IfcNames_MemwriteRequestS2H);\n  deviceIndication = new MemwriteIndication(IfcNames_MemwriteIndicationH2S);\n  DmaManager *dma = platformInit();\n\n  device->pint.busyType = BUSY_SPIN;   /* spin until request portal 'notFull' */\n  //dmap->pint.busyType = BUSY_SPIN;   /* spin until request portal 'notFull' */\n\n  sem_init(&done_sem, 1, 0);\n\n  int iters = 2;\n\n  uint32_t mismatchCount = 0;\n\n  for (int iter = 0; iter < iters; iter++) {\n      int dstAlloc = portalAlloc(alloc_sz, 1);\n      unsigned int *dstBuffer = (unsigned int *)portalMmap(dstAlloc, alloc_sz);\n\n      for (uint32_t i = 0; i < alloc_sz/sizeof(uint32_t); i++)\n\t  dstBuffer[i] = 0xDEADBEEF;\n\n#ifndef USE_ACP\n      fprintf(stderr, \"flushing cache\\n\");\n      portalCacheFlush(dstAlloc, dstBuffer, alloc_sz, 1);\n#endif\n\n      fprintf(stderr, \"parent::starting write\\n\");\n      mismatchCount = 0;\n      unsigned int ref_dstAlloc = dma->reference(dstAlloc);\n      fprintf(stderr, \"dma->reference %d\\n\", ref_dstAlloc);\n      int burstLenBytes = 32*sizeof(uint32_t);\n\n      int byteEnable = (iter == 0) ? 0xFF : 0x5a;\n      portalTimerStart(0);\n      device->startWrite(ref_dstAlloc, alloc_sz, alloc_sz / burstLenBytes, burstLenBytes, byteEnable);\n      sem_wait(&done_sem);\n      platformStatistics();\n\n      memdump((unsigned char *)dstBuffer, 32, \"MEM\");\n      for (uint32_t i = 0; i < alloc_sz/sizeof(uint32_t); i++) {\n\t  if (dstBuffer[i] != (i+3))\n\t      mismatchCount++;\n      }\n      uint32_t expectedMismatchCount = (byteEnable == 0xff) ? 0 : 2*(alloc_sz / burstLenBytes);\n      fprintf(stderr, \"%s: done mismatchCount=%d expected %d\\n\", __FUNCTION__, mismatchCount, expectedMismatchCount);\n      if (mismatchCount == expectedMismatchCount)\n\t  mismatchCount=0;\n\n      fprintf(stderr, \"%s: calling munmap\\n\", __FUNCTION__);\n      int unmapped = munmap(dstBuffer, alloc_sz);\n      if (unmapped != 0)\n\t  fprintf(stderr, \"Failed to unmap dstBuffer errno=%d:%s\\n\", errno, strerror(errno));\n      \n      fprintf(stderr, \"%s: close\\n\", __FUNCTION__);\n      close(dstAlloc);\n\n      fprintf(stderr, \"%s: calling dereference\\n\", __FUNCTION__);\n      dma->dereference(ref_dstAlloc);\n      fprintf(stderr, \"%s: after dereference\\n\", __FUNCTION__);\n  }\n\n  return (mismatchCount == 0) ? 0 : 1;\n}\n"
  },
  {
    "path": "tests/memserver_write128/Makefile",
    "content": "CONNECTALDIR?=../..\nMSWDIR=../memserver_write/\nS2H_INTERFACES = MemwriteRequest:Memwrite.request\nH2S_INTERFACES = Memwrite:MemwriteIndication\nMEM_WRITE_INTERFACES = lMemwrite.dmaClients\n\nBSVFILES = $(MSWDIR)/Memwrite.bsv\nCPPFILES = $(MSWDIR)/testmemwrite.cpp\nCONNECTALFLAGS += -D USE_ACP -P mkConnectalTop -D DataBusWidth=128 -D BYTE_ENABLES\n\ninclude $(CONNECTALDIR)/Makefile.connectal\n"
  },
  {
    "path": "tests/memtopcie_bluesim/Makefile",
    "content": "\nCONNECTALDIR?=../..\nMEMREADDIR=$(CONNECTALDIR)/examples/memread\nINTERFACES = MemreadRequest MemreadIndication\nBSVFILES = $(MEMREADDIR)/Memread.bsv Top.bsv\nCPPFILES = $(MEMREADDIR)/testmemread.cpp\nCONNECTALFLAGS += -D NumEngineServers=16 -D DataBusWidth=128\nCONNECTALFLAGS += -I$(CONNECTALDIR)/examples/memread\n#CONNECTALFLAGS += --bscflags \" -show-schedule\"\n\ninclude $(CONNECTALDIR)/Makefile.connectal\n"
  },
  {
    "path": "tests/memtopcie_bluesim/Top.bsv",
    "content": "// Copyright (c) 2013 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\nimport SpecialFIFOs::*;\nimport Vector::*;\nimport BuildVector::*;\nimport StmtFSM::*;\nimport FIFO::*;\nimport GetPut::*;\nimport ClientServer::*;\nimport Connectable::*;\nimport PCIE::*;\nimport DefaultValue::*;\nimport MemServer::*;\nimport ConnectalMMU::*;\nimport CtrlMux::*;\nimport Portal::*;\nimport ConnectalMemory::*;\nimport ConnectalMemTypes::*;\nimport ConnectalConfig::*;\nimport MemToPcie::*;\nimport AddressGenerator::*;\nimport MemreadRequest::*;\nimport MemServerRequest::*;\nimport MMURequest::*;\nimport MemreadIndication::*;\nimport MemServerIndication::*;\nimport MMUIndication::*;\nimport Memread::*;\n\ntypedef enum {IfcNames_MemreadIndicationH2S, IfcNames_MemreadRequestS2H, IfcNames_MemServerIndicationH2S, IfcNames_MemServerRequestS2H, IfcNames_MMURequestS2H, IfcNames_MMUIndicationH2S} IfcNames deriving (Eq,Bits);\n\nmodule mkConnectalTop(ConnectalTop);\n\n   MemreadIndicationProxy memreadIndicationProxy <- mkMemreadIndicationProxy(IfcNames_MemreadIndicationH2S);\n   Memread memread <- mkMemread(memreadIndicationProxy.ifc);\n   MemreadRequestWrapper memreadRequestWrapper <- mkMemreadRequestWrapper(IfcNames_MemreadRequestS2H,memread.request);\n\n   MMUIndicationProxy hostMMUIndicationProxy <- mkMMUIndicationProxy(IfcNames_MMUIndicationH2S);\n   MMU#(PhysAddrWidth) hostMMU <- mkMMU(0, True, hostMMUIndicationProxy.ifc);\n   MMURequestWrapper hostMMURequestWrapper <- mkMMURequestWrapper(IfcNames_MMURequestS2H, hostMMU.request);\n\n   MemServerIndicationProxy hostMemServerIndicationProxy <- mkMemServerIndicationProxy(IfcNames_MemServerIndicationH2S);\n   MemServer#(PhysAddrWidth,DataBusWidth,1) dma <- mkMemServer(memread.dmaClient, nil, vec(hostMMU), hostMemServerIndicationProxy.ifc);\n   MemServerRequestWrapper hostMemServerRequestWrapper <- mkMemServerRequestWrapper(IfcNames_MemServerRequestS2H, dma.request);\n\n   PhysMemMaster#(PhysAddrWidth,DataBusWidth) dma1 = (interface PhysMemMaster;\n\t  interface PhysMemReadClient read_client;\n\t     interface Get readReq;\n\t\tmethod ActionValue#(PhysMemRequest#(PhysAddrWidth)) get() if (False);\n\t\t   return ?;\n\t        endmethod\n\t     endinterface\n\t  endinterface\n\t  interface PhysMemWriteClient write_client;\n\t     interface Get writeReq;\n\t\tmethod ActionValue#(PhysMemRequest#(PhysAddrWidth)) get() if (False);\n\t\t   return ?;\n\t        endmethod\n\t     endinterface\n\t  endinterface\n      endinterface);\n\n   Reg#(Bit#(32)) cycles <- mkReg(0);\n   Reg#(Bit#(32)) reqCycles <- mkReg(0);\n   Reg#(Bit#(32)) lastCycle <- mkReg(0);\n   rule count;\n      cycles <= cycles + 1;\n      if (cycles == 1)\n\t //$dumpvars();\n      if (cycles == 10000)\n\t $dumpoff();\n   endrule\n\n   let my_id = PciId {bus: 4, dev: 2, func: 0};\n   MemToPcie#(DataBusWidth) memSlaveEngine <- mkMemToPcie(my_id);\n   mkConnection(dma.masters[0], memSlaveEngine.slave);\n\n   AddressGenerator#(32, DataBusWidth) addrGenerator <- mkAddressGenerator();\n\n   FIFO#(TLPData#(16)) tlpFifo <- mkSizedFIFO(1);\n   FIFO#(TLPData#(16)) tlpOutFifo <- mkSizedFIFO(16);\n\n   rule displayTlp;\n      let tlp <- memSlaveEngine.tlp.request.get();\n      TLPMemory4DWHeader hdr4dw = unpack(tlp.data);\n      TLPMemoryIO3DWHeader hdr3dw = unpack(tlp.data);\n      let newReqCycles = cycles;\n      Bit#(32) addr = extend(hdr3dw.addr);\n      TLPTag   tag  = hdr3dw.tag;\n      TLPLength burstLen = hdr3dw.length;\n\n      if (tlp.sof && hdr4dw.format == MEM_READ_4DW_NO_DATA) begin\n\t $display(\"%d 4dw req %h len=%d %d\", cycles-reqCycles, hdr4dw.addr<<2, hdr3dw.length, fromInteger(valueOf(DataBusWidth)));\n\n\t addr = truncate(hdr4dw.addr);\n\t tag = hdr4dw.tag;\n\t burstLen = hdr4dw.length;\n      end\n      else if (tlp.sof && hdr3dw.format == MEM_READ_3DW_NO_DATA) begin\n\t $display(\"%d 3dw req %h len=%h %d\", cycles-reqCycles, hdr3dw.addr<<2, hdr4dw.length, fromInteger(valueOf(DataBusWidth)));\n      end\n      else if (tlp.sof) begin\n\t $display(\"%d sof %h\", cycles-reqCycles, tlp.data);\n      end\n      else begin\n\t $display(\"unknown tlp %h\", tlp);\n      end\n\n      addrGenerator.request.put(PhysMemRequest {addr: addr, burstLen: truncate(pack(burstLen<<2)), tag: truncate(tag) });\n      reqCycles <= newReqCycles;\n      tlpFifo.enq(tlp);\n\n      TLPData#(16) resptlp;\n      resptlp.sof = True;\n      resptlp.eof = (burstLen == 1);\n      resptlp.be = 16'hffff;\n      resptlp.hit = 0;\n      Vector#(4, Bit#(32)) vec = unpack(0);\n      TLPCompletionHeader completion = defaultValue;\n      completion.format = MEM_WRITE_3DW_DATA;\n      completion.pkttype = COMPLETION;\n      completion.relaxed = hdr3dw.relaxed;\n      completion.nosnoop = hdr3dw.nosnoop;\n      completion.length = hdr3dw.length;\n      completion.tclass = hdr3dw.tclass;\n      completion.cmplid = my_id;\n      completion.tag = truncate(hdr3dw.tag);\n      completion.bytecount = extend(burstLen)*4;\n      completion.reqid = hdr3dw.reqid;\n      completion.loweraddr = getLowerAddr(hdr3dw.addr, hdr3dw.firstbe);\n      completion.data = byteSwap(0);\n\n      resptlp.data = pack(completion);\n      tlpOutFifo.enq(resptlp);\n      lastCycle <= cycles;\n      $display(\"%d: gen tlp resp %h burstLen %d\", cycles-lastCycle, resptlp, burstLen);\n   endrule\n   rule dataRule;\n      let addrBeat <- addrGenerator.addrBeat.get();\n      if (addrBeat.last)\n\t tlpFifo.deq();\n      TLPData#(16) resptlp;\n      resptlp.sof = False;\n      resptlp.eof = addrBeat.last;\n      resptlp.be = 16'hffff;\n      resptlp.hit = 0;\n      if (addrBeat.last) begin\n\t resptlp.be = 16'hfff0;\n      end\n      Vector#(4, Bit#(32)) vec = unpack(0);\n      resptlp.data = pack(vec);\n      $display(\"     addr %h\", addrBeat.addr << 2);\n      $display(\"%d: gen tlp data %h last=%d\", cycles-lastCycle, resptlp, addrBeat.last);\n      lastCycle <= cycles;\n      tlpOutFifo.enq(resptlp);\n   endrule\n   rule tlpout;\n      let resptlp <- toGet(tlpOutFifo).get();\n      memSlaveEngine.tlp.response.put(resptlp);\n   endrule\n   Vector#(6,StdPortal) portals;\n   portals[0] = hostMemServerIndicationProxy.portalIfc; \n   portals[1] = memreadIndicationProxy.portalIfc; \n   portals[2] = hostMemServerRequestWrapper.portalIfc;\n   portals[3] = memreadRequestWrapper.portalIfc;\n   portals[4] = hostMMURequestWrapper.portalIfc;\n   portals[5] = hostMMUIndicationProxy.portalIfc;\n   let ctrl_mux <- mkSlaveMux(portals);\n   \n   interface interrupt = getInterruptVector(portals);\n   interface slave = ctrl_mux;\n   interface masters = vec(dma1);\nendmodule : mkConnectalTop\n"
  },
  {
    "path": "tests/memwrite_acp/Makefile",
    "content": "CONNECTALDIR?=../..\nS2H_INTERFACES = MemwriteRequest:Memwrite.request\nH2S_INTERFACES = Memwrite:MemwriteIndication\nMEM_WRITE_INTERFACES = lMemwrite.dmaClient\n\nBSVFILES = Memwrite.bsv\nCPPFILES = testmemwrite.cpp\nCONNECTALFLAGS += -D USE_ACP\n\ninclude $(CONNECTALDIR)/Makefile.connectal\n"
  },
  {
    "path": "tests/memwrite_acp/Memwrite.bsv",
    "content": "// Copyright (c) 2013 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\nimport Vector::*;\nimport FIFOF::*;\nimport ClientServer::*;\nimport GetPut::*;\nimport ConnectalMemTypes::*;\nimport MemWriteEngine::*;\nimport Pipe::*;\nimport ConnectalConfig::*;\n\ninterface MemwriteRequest;\n   method Action startWrite(Bit#(32) pointer, Bit#(32) numWords, Bit#(32) burstLen);\nendinterface\n\ninterface MemwriteIndication;\n   method Action writeDone(Bit#(32) v);\nendinterface\n\ninterface Memwrite;\n   interface MemwriteRequest request;\n   interface Vector#(1,MemWriteClient#(DataBusWidth)) dmaClient;\nendinterface\n\nmodule  mkMemwrite#(MemwriteIndication indication) (Memwrite);\n   Reg#(SGLId)   pointer <- mkReg(0);\n   Reg#(Bit#(32))       numWords <- mkReg(0);\n   Reg#(Bit#(32))       burstLen <- mkReg(0);\n   Reg#(Bit#(32))         srcGens <- mkReg(0);\n   Reg#(Bool)              doOnce <- mkReg(False);\n   MemWriteEngine#(DataBusWidth,DataBusWidth,2,1)    we <- mkMemWriteEngine;\n\n   rule start if (doOnce);\n         we.writeServers[0].request.put(MemengineCmd{sglId:pointer, base:0, len:truncate(numWords), burstLen:truncate(burstLen), tag:0});\n         $display(\"start\");\n         doOnce <= False;\n   endrule\n   rule finish;\n         $display(\"finish\");\n         let rv <- we.writeServers[0].done.get;\n         indication.writeDone(0);\n   endrule\n   rule src if (numWords != 0);\n         let v = {srcGens+1,srcGens};\n         we.writeServers[0].data.enq(v);\n         srcGens <= srcGens+2;\n         numWords <= numWords - 8;\n   endrule\n\n   interface MemwriteRequest request;\n       method Action startWrite(Bit#(32) wp, Bit#(32) nw, Bit#(32) bl);\n          $display(\"startWrite pointer=%d numWords=%h burstLen=%d\", pointer, nw, bl);\n          pointer <= wp;\n          numWords  <= nw;\n          burstLen  <= bl;\n          doOnce <= True;\n       endmethod\n   endinterface\n   interface MemWriteClient dmaClient = cons(we.dmaClient,nil);\nendmodule\n\n"
  },
  {
    "path": "tests/memwrite_acp/testmemwrite.cpp",
    "content": "/* Copyright (c) 2014 Quanta Research Cambridge, Inc\n *\n * Permission is hereby granted, free of charge, to any person obtaining a\n * copy of this software and associated documentation files (the \"Software\"),\n * to deal in the Software without restriction, including without limitation\n * the rights to use, copy, modify, merge, publish, distribute, sublicense,\n * and/or sell copies of the Software, and to permit persons to whom the\n * Software is furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n * DEALINGS IN THE SOFTWARE.\n */\n#include \"dmaManager.h\"\n#include \"MemwriteIndication.h\"\n#include \"MemwriteRequest.h\"\n\nstatic void memdump(unsigned char *p, int len, const char *title)\n{\nint i;\n\n    i = 0;\n    while (len > 0) {\n        if (!(i & 0xf)) {\n            if (i > 0)\n                printf(\"\\n\");\n            printf(\"%s: \",title);\n        }\n        printf(\"%02x \", *p++);\n        i++;\n        len--;\n    }\n    printf(\"\\n\");\n}\n\nstatic sem_t done_sem;\nclass MemwriteIndication : public MemwriteIndicationWrapper\n{\npublic:\n  MemwriteIndication(int id) : MemwriteIndicationWrapper(id){}\n\n  virtual void writeDone ( uint32_t srcGen ){\n    fprintf(stderr, \"Memwrite::writeDone (%08x)\\n\", srcGen);\n    sem_post(&done_sem);\n  }\n};\n\nint main(int argc, const char **argv)\n{\n  size_t alloc_sz = 1024*1024;\n  MemwriteRequestProxy *device = new MemwriteRequestProxy(IfcNames_MemwriteRequestS2H);\n  MemwriteIndication deviceIndication(IfcNames_MemwriteIndicationH2S);\n  DmaManager *dma = platformInit();\n\n  sem_init(&done_sem, 1, 0);\n  int dstAlloc = portalAlloc(alloc_sz, 0);\n  unsigned int *dstBuffer = (unsigned int *)portalMmap(dstAlloc, alloc_sz);\n\n  for (unsigned int i = 0; i < alloc_sz/sizeof(uint32_t); i++)\n    dstBuffer[i] = 0xDEADBEEF;\n\n  portalCacheFlush(dstAlloc, dstBuffer, alloc_sz, 1);\n\n  fprintf(stderr, \"parent::starting write\\n\");\n  unsigned int ref_dstAlloc = dma->reference(dstAlloc);\n  device->startWrite(ref_dstAlloc, alloc_sz, 2 * sizeof(uint32_t));\n\n  sem_wait(&done_sem);\n  memdump((unsigned char *)dstBuffer, 32, \"MEM\");\n  fprintf(stderr, \"%s: done\\n\", __FUNCTION__);\n}\n"
  },
  {
    "path": "tests/memwrite_manyclients/Makefile",
    "content": "CONNECTALDIR?=../..\nMEMWRITEDIR=$(CONNECTALDIR)/examples/memwrite\nS2H_INTERFACES = MemwriteRequest:Memwrite.request\nH2S_INTERFACES = Memwrite:MemwriteIndication\nMEM_WRITE_INTERFACES = lMemwrite.dmaClient\n\nBSVFILES = $(MEMWRITEDIR)/Memwrite.bsv\nCPPFILES = $(MEMWRITEDIR)/testmemwrite.cpp\nCONNECTALFLAGS += -D NumEngineServers=16\nCONNECTALFLAGS += --bscflags \" -show-schedule\"\n#CONNECTALFLAGS += --bscflags \" -ddumpschedule\"\n\ninclude $(CONNECTALDIR)/Makefile.connectal\n"
  },
  {
    "path": "tests/memwrite_manyclients128/Makefile",
    "content": "CONNECTALDIR?=../..\nMEMWRITEDIR=$(CONNECTALDIR)/examples/memwrite\nS2H_INTERFACES = MemwriteRequest:Memwrite.request\nH2S_INTERFACES = Memwrite:MemwriteIndication\nMEM_WRITE_INTERFACES = lMemwrite.dmaClient\n\nBSVFILES = $(MEMWRITEDIR)/Memwrite.bsv\nCPPFILES = $(MEMWRITEDIR)/testmemwrite.cpp\nCONNECTALFLAGS += -D NumEngineServers=8 -D DataBusWidth=128\nCONNECTALFLAGS += --bscflags \" -show-schedule\"\n#CONNECTALFLAGS += --bscflags \" -ddumpschedule\"\n\ninclude $(CONNECTALDIR)/Makefile.connectal\n"
  },
  {
    "path": "tests/memwrite_trivial/Makefile",
    "content": "CONNECTALDIR?=../..\nS2H_INTERFACES = MemwriteRequest:Memwrite.request\nH2S_INTERFACES = Memwrite:MemwriteIndication\nMEM_WRITE_INTERFACES = lMemwrite.dmaClient\n\nBSVFILES = Memwrite.bsv\nCPPFILES = testmemwrite.cpp\n\ninclude $(CONNECTALDIR)/Makefile.connectal\n"
  },
  {
    "path": "tests/memwrite_trivial/Memwrite.bsv",
    "content": "// Copyright (c) 2013 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\nimport Vector::*;\nimport FIFOF::*;\nimport ClientServer::*;\nimport GetPut::*;\nimport ConnectalMemTypes::*;\nimport MemWriteEngine::*;\nimport Pipe::*;\nimport ConnectalConfig::*;\n\ninterface MemwriteRequest;\n   method Action startWrite(Bit#(32) pointer, Bit#(32) numWords, Bit#(32) burstLen);\nendinterface\n\ninterface MemwriteIndication;\n   method Action writeDone(Bit#(32) v);\nendinterface\n\ninterface Memwrite;\n   interface MemwriteRequest request;\n   interface Vector#(1,MemWriteClient#(DataBusWidth)) dmaClient;\nendinterface\n\nmodule  mkMemwrite#(MemwriteIndication indication) (Memwrite);\n   Reg#(SGLId)   pointer <- mkReg(0);\n   Reg#(Bit#(32))       numWords <- mkReg(0);\n   Reg#(Bit#(32))       burstLen <- mkReg(0);\n   Reg#(Bit#(32))         srcGens <- mkReg(0);\n   Reg#(Bool)              doOnce <- mkReg(False);\n   MemWriteEngine#(DataBusWidth,DataBusWidth,2,1)    we <- mkMemWriteEngine;\n\n   rule start if (doOnce);\n         we.writeServers[0].request.put(MemengineCmd{sglId:pointer, base:0, len:truncate(numWords), burstLen:truncate(burstLen)});\n         $display(\"start\");\n         doOnce <= False;\n   endrule\n   rule finish;\n         $display(\"finish\");\n         let rv <- we.writeServers[0].done.get;\n         indication.writeDone(0);\n   endrule\n   rule src if (numWords != 0);\n         let v = {srcGens+1,srcGens};\n         we.writeServers[0].data.enq(v);\n         srcGens <= srcGens+2;\n         numWords <= numWords - 8;\n   endrule\n\n   interface MemwriteRequest request;\n       method Action startWrite(Bit#(32) wp, Bit#(32) nw, Bit#(32) bl);\n          $display(\"startWrite pointer=%d numWords=%h burstLen=%d\", pointer, nw, bl);\n          pointer <= wp;\n          numWords  <= nw;\n          burstLen  <= bl;\n          doOnce <= True;\n       endmethod\n   endinterface\n   interface MemWriteClient dmaClient = cons(we.dmaClient,nil);\nendmodule\n\n"
  },
  {
    "path": "tests/memwrite_trivial/testmemwrite.cpp",
    "content": "/* Copyright (c) 2014 Quanta Research Cambridge, Inc\n *\n * Permission is hereby granted, free of charge, to any person obtaining a\n * copy of this software and associated documentation files (the \"Software\"),\n * to deal in the Software without restriction, including without limitation\n * the rights to use, copy, modify, merge, publish, distribute, sublicense,\n * and/or sell copies of the Software, and to permit persons to whom the\n * Software is furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n * DEALINGS IN THE SOFTWARE.\n */\n#include \"dmaManager.h\"\n#include \"MemwriteIndication.h\"\n#include \"MemwriteRequest.h\"\n\nstatic void memdump(unsigned char *p, int len, const char *title)\n{\nint i;\n\n    i = 0;\n    while (len > 0) {\n        if (!(i & 0xf)) {\n            if (i > 0)\n                printf(\"\\n\");\n            printf(\"%s: \",title);\n        }\n        printf(\"%02x \", *p++);\n        i++;\n        len--;\n    }\n    printf(\"\\n\");\n}\n\nstatic sem_t done_sem;\nclass MemwriteIndication : public MemwriteIndicationWrapper\n{\npublic:\n  MemwriteIndication(int id) : MemwriteIndicationWrapper(id){}\n\n  virtual void writeDone ( uint32_t srcGen ){\n    fprintf(stderr, \"Memwrite::writeDone (%08x)\\n\", srcGen);\n    sem_post(&done_sem);\n  }\n};\n\nint main(int argc, const char **argv)\n{\n  size_t alloc_sz = 0x1240;\n  MemwriteRequestProxy *device = new MemwriteRequestProxy(IfcNames_MemwriteRequestS2H);\n  MemwriteIndication deviceIndication(IfcNames_MemwriteIndicationH2S);\n  DmaManager *dma = platformInit();\n\n  sem_init(&done_sem, 1, 0);\n  int dstAlloc = portalAlloc(alloc_sz, 0);\n  unsigned int *dstBuffer = (unsigned int *)portalMmap(dstAlloc, alloc_sz);\n\n  for (unsigned int i = 0; i < alloc_sz/sizeof(uint32_t); i++)\n    dstBuffer[i] = 0xDEADBEEF;\n\n  portalCacheFlush(dstAlloc, dstBuffer, alloc_sz, 1);\n\n  fprintf(stderr, \"parent::starting write\\n\");\n  unsigned int ref_dstAlloc = dma->reference(dstAlloc);\n  device->startWrite(ref_dstAlloc, alloc_sz, 2 * sizeof(uint32_t));\n\n  sem_wait(&done_sem);\n  memdump((unsigned char *)dstBuffer, 32, \"MEM\");\n  fprintf(stderr, \"%s: done\\n\", __FUNCTION__);\n}\n"
  },
  {
    "path": "tests/memwriteengine_test/Makefile",
    "content": "CONNECTALDIR?=../..\nS2H_INTERFACES = MemwriteRequest:Memwrite.request\nH2S_INTERFACES = Memwrite:MemwriteIndication\n#MEM_WRITE_INTERFACES = lMemwrite.dmaClients\n\nBSVFILES = Memwrite.bsv\nCPPFILES = testmemwrite.cpp\n\ninclude $(CONNECTALDIR)/Makefile.connectal\n"
  },
  {
    "path": "tests/memwriteengine_test/MemWriteEngineTest.bsv",
    "content": "// Copyright (c) 2015 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\nimport FIFO::*;\nimport FIFOF::*;\nimport Vector::*;\nimport GetPut::*;\nimport Connectable::*;\nimport BRAMFIFO::*;\nimport ConnectalMemTypes::*;\nimport AddressGenerator::*;\n\ninterface MemWriteEngineTest;\n   interface MemWriteServer#(64) dmaServer; // connect this to memwrite engine\n   interface MemWriteClient#(64) dmaClient; // connect this to memserver\n   interface Get#(Bit#(32))                   req;\n   interface Get#(Bit#(MemTagSize))           done;\n   interface Get#(Tuple2#(Bit#(32),Bit#(64))) mismatch;\nendinterface\n\n(* synthesize *)\nmodule mkMemWriteEngineTest(MemWriteEngineTest);\n\n   FIFO#(MemRequest) writeReqInFifo <- mkSizedBRAMFIFO(32);\n   FIFO#(MemData#(64)) writeDataInFifo <- mkSizedBRAMFIFO(128);\n   FIFO#(Bit#(MemTagSize)) writeDoneInFifo <- mkSizedBRAMFIFO(32);\n\n   FIFO#(MemRequest) writeReqOutFifo <- mkSizedBRAMFIFO(32);\n   FIFO#(MemData#(64)) writeDataOutFifo <- mkSizedBRAMFIFO(128);\n   FIFO#(Bit#(MemTagSize)) writeDoneOutFifo <- mkSizedBRAMFIFO(32);\n\n   AddressGenerator#(32,64) addrGenerator <- mkAddressGenerator();\n   FIFOF#(Bit#(32)) addrFifo <- mkSizedBRAMFIFOF(32);\n   FIFOF#(Tuple2#(Bit#(32),Bit#(64))) mismatchFifo <- mkSizedBRAMFIFOF(32);\n   FIFOF#(Bit#(MemTagSize)) doneFifo <- mkSizedBRAMFIFOF(32);\n\n   rule reqRule;\n      let req <- toGet(writeReqInFifo).get();\n      $display(\"req: offset=%h burstLen=%d tag=%h\", req.offset, req.burstLen, req.tag);\n      //writeReqOutFifo.enq(req);\n      addrGenerator.request.put(PhysMemRequest{addr:truncate(req.offset), burstLen: req.burstLen, tag: req.tag });\n      addrFifo.enq(truncate(req.offset));\n   endrule\n\n   rule dataRule;\n      let b <- addrGenerator.addrBeat.get();\n      let data <- toGet(writeDataInFifo).get();\n      let traceAllData = False;\n      if (traceAllData)\n\t mismatchFifo.enq(tuple2(b.addr, data.data));\n\n      //writeDataOutFifo.enq(data);\n      Vector#(2, Bit#(32)) v = unpack(data.data);\n      if (v[0] != (b.addr>>2) || v[1] != ((b.addr>>2)+1)) begin\n\t $display(\"mismatch: addr=%h data=%h\", b.addr, data.data);\n\t if (!traceAllData && mismatchFifo.notFull())\n\t    mismatchFifo.enq(tuple2(b.addr, data.data));\n      end\n      if (b.last)\n\t writeDoneOutFifo.enq(b.tag);\n   endrule\n\n   rule doneRule;\n      let done <- toGet(writeDoneInFifo).get();\n      $display(\"done: tag=%h\", done);\n      writeDoneOutFifo.enq(done);\n      doneFifo.enq(done);\n   endrule\n\n   interface MemWriteServer dmaServer;\n      interface Put writeReq = toPut(writeReqInFifo);\n      interface Put writeData = toPut(writeDataInFifo);\n      interface Get writeDone = toGet(writeDoneOutFifo);\n   endinterface\n   interface MemWriteClient dmaClient;\n      interface Get writeReq = toGet(writeReqOutFifo);\n      interface Get writeData = toGet(writeDataOutFifo);\n      interface Put writeDone = toPut(writeDoneInFifo);\n   endinterface\n   interface Get req = toGet(addrFifo);\n   interface Get done = toGet(doneFifo);\n   interface Get mismatch = toGet(mismatchFifo);\nendmodule\n"
  },
  {
    "path": "tests/memwriteengine_test/Memwrite.bsv",
    "content": "// Copyright (c) 2013 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\nimport ConnectalConfig::*;\nimport CtrlMux::*;\nimport Vector::*;\nimport FIFOF::*;\nimport ClientServer::*;\nimport GetPut::*;\nimport Connectable::*;\nimport ConnectalMemTypes::*;\nimport MemWriteEngine::*;\nimport Pipe::*;\nimport MemWriteEngineTest::*;\n\ninterface MemwriteRequest;\n   method Action startWrite(Bit#(32) pointer, Bit#(32) numWords, Bit#(32) burstLen);\nendinterface\n\ninterface MemwriteIndication;\n   method Action writeDone(Bit#(32) v);\n   method Action req(Bit#(32) addr);\n   method Action done(Bit#(32) tag);\n   method Action mismatch(Bit#(32) addr, Bit#(64) data);\nendinterface\n\ninterface Memwrite;\n   interface MemwriteRequest request;\n   interface Vector#(1,MemWriteClient#(64)) dmaClients;\nendinterface\n\nmodule  mkMemwrite#(MemwriteIndication indication) (Memwrite);\n   Reg#(SGLId)   pointer <- mkReg(0);\n   Reg#(Bit#(32))       numWords <- mkReg(0);\n   Reg#(Bit#(32))       burstLen <- mkReg(0);\n   Reg#(Bit#(32))         srcGens <- mkReg(0);\n   Reg#(Bool)              doOnce <- mkReg(False);\n   MemWriteEngine#(64,64,2,1)    we <- mkMemWriteEngine;\n   MemWriteEngineTest         wet <- mkMemWriteEngineTest();\n   mkConnection(we.dmaClient, wet.dmaServer);\n\n   rule reqRule;\n      let addr <- wet.req.get();\n      indication.req(addr);\n   endrule\n   rule doneRule;\n      let tag <- wet.done.get();\n      indication.done(extend(tag));\n   endrule\n\n   rule mismatchRule;\n      match { .addr, .data } <- wet.mismatch.get();\n      indication.mismatch(addr, data);\n   endrule\n   rule start if (doOnce);\n         we.writeServers[0].request.put(MemengineCmd{sglId:pointer, base:0, len:truncate(numWords), burstLen:truncate(burstLen), tag: 7});\n         $display(\"start\");\n         doOnce <= False;\n   endrule\n   rule finish;\n         $display(\"finish\");\n         let rv <- we.writeServers[0].done.get;\n         indication.writeDone(0);\n   endrule\n   rule src if (numWords != 0);\n         let v = {srcGens+1,srcGens};\n         we.writeServers[0].data.enq(v);\n         srcGens <= srcGens+2;\n         numWords <= numWords - 8;\n   endrule\n\n   interface MemwriteRequest request;\n       method Action startWrite(Bit#(32) wp, Bit#(32) nw, Bit#(32) bl);\n          $display(\"startWrite pointer=%d numWords=%h burstLen=%d\", pointer, nw, bl);\n          pointer <= wp;\n          numWords  <= nw;\n          burstLen  <= bl;\n          doOnce <= True;\n       endmethod\n   endinterface\n   interface Vector dmaClients = cons(wet.dmaClient,nil);\nendmodule\n"
  },
  {
    "path": "tests/memwriteengine_test/testmemwrite.cpp",
    "content": "/* Copyright (c) 2014 Quanta Research Cambridge, Inc\n *\n * Permission is hereby granted, free of charge, to any person obtaining a\n * copy of this software and associated documentation files (the \"Software\"),\n * to deal in the Software without restriction, including without limitation\n * the rights to use, copy, modify, merge, publish, distribute, sublicense,\n * and/or sell copies of the Software, and to permit persons to whom the\n * Software is furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n * DEALINGS IN THE SOFTWARE.\n */\n#include \"dmaManager.h\"\n#include \"MemwriteIndication.h\"\n#include \"MemwriteRequest.h\"\n\n#define NUMBER_OF_WORDS   0x1240\n\nstatic sem_t done_sem;\nclass MemwriteIndication : public MemwriteIndicationWrapper\n{\npublic:\n  MemwriteIndication(int id) : MemwriteIndicationWrapper(id){}\n\n  virtual void writeDone ( uint32_t srcGen ){\n    fprintf(stderr, \"Memwrite::writeDone (%08x)\\n\", srcGen);\n    sem_post(&done_sem);\n  }\n  virtual void req ( uint32_t addr ){\n    fprintf(stderr, \"req.addr=%08x\\n\", addr);\n  }\n  virtual void done ( uint32_t tag ){\n    fprintf(stderr, \"done.tag=%x\\n\", tag);\n  }\n  virtual void mismatch ( const uint32_t addr, const uint64_t data ){\n    fprintf(stderr, \"mismatch: addr=%08x data = %08lx %08lx\\n\",\n\t    addr, (long)((data >> 32) & 0xFFFFFFFF), (long)(data & 0xFFFFFFFF));\n  }\n};\n\nint main(int argc, const char **argv)\n{\n  size_t alloc_sz = NUMBER_OF_WORDS;\n  MemwriteRequestProxy *device = new MemwriteRequestProxy(IfcNames_MemwriteRequestS2H);\n  MemwriteIndication deviceIndication(IfcNames_MemwriteIndicationH2S);\n#if (NumberOfMasters != 0)\n  DmaManager *dma = platformInit();\n#endif\n\n  sem_init(&done_sem, 1, 0);\n#if (NumberOfMasters != 0)\n  int dstAlloc = portalAlloc(alloc_sz, 0);\n  unsigned int *dstBuffer = (unsigned int *)portalMmap(dstAlloc, alloc_sz);\n\n  for (unsigned int i = 0; i < alloc_sz/sizeof(uint32_t); i++)\n    dstBuffer[i] = 0xDEADBEEF;\n\n  portalCacheFlush(dstAlloc, dstBuffer, alloc_sz, 1);\n\n  fprintf(stderr, \"parent::starting write\\n\");\n  unsigned int ref_dstAlloc = dma->reference(dstAlloc);\n#else\n  unsigned int ref_dstAlloc = 1;\n#endif\n  device->startWrite(ref_dstAlloc, alloc_sz, 2 * sizeof(uint32_t));\n\n  sem_wait(&done_sem);\n  fprintf(stderr, \"%s: done\\n\", __FUNCTION__);\n  sleep(2);\n  return 0;\n}\n"
  },
  {
    "path": "tests/method/Makefile",
    "content": "CONNECTALDIR?=../..\nS2H_INTERFACES = MethodRequest:Method.request\n\nBSVFILES = Method.bsv\nCPPFILES= mtest.cpp\n\ninclude $(CONNECTALDIR)/Makefile.connectal\n\n"
  },
  {
    "path": "tests/method/Method.bsv",
    "content": "// Copyright (c) 2015 The Connectal Project\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\nimport LinkerLib::*;\nimport GetPut::*;\nimport FIFO::*;\n\ninterface Inverter;\n    method Action m(Bool v);\n    method ActionValue#(Bool) mInv;\nendinterface\t\t\n\n(* synthesize *)\nmodule  mkInverter(Inverter);\n    PutInverter#(Bool) inv <- mkPutInverter();\n\n    method Action m(Bool v);\n        inv.mod.put(v);\n    endmethod\n    method ActionValue#(Bool) mInv;\n        let v <- inv.inverse.get;\n        return v;\n    endmethod\nendmodule\n\ninterface Invertm;\n    method Action actual(Bool v);\nendinterface\n\n(* synthesize *)\nmodule mkInvertm(Invertm);\n    FIFO#(Bool) fifo <- mkFIFO;\n    method Action actual(Bool v);\n        fifo.enq(v);\n    endmethod\nendmodule\n\ninterface MethodRequest;\n   method Action startme;\nendinterface\ninterface Method;\n   interface MethodRequest request;\nendinterface\n\n(* synthesize *)\nmodule mkMethod(Method);\n   Inverter einst <- mkInverter;\n   Invertm eact <- mkInvertm;\n   FIFO#(Bool) fifo <- mkFIFO;\n\n   rule invoke_rule;\n      einst.m(fifo.first);\n   endrule\n\n   PutInverter#(Bool) conn <- mkPutInverter();\n   rule connect_rule1;\n      let v <- einst.mInv;\n      conn.mod.put(v);\n   endrule\n   rule connect_rule2;\n      let v <- conn.inverse.get();\n      eact.actual(v);\n   endrule\n\n   interface MethodRequest request;\n      method Action startme;\n      endmethod\n   endinterface\nendmodule\n"
  },
  {
    "path": "tests/method/mtest.cpp",
    "content": "#include <stdio.h>\n\nint main()\n{\n    return 0;\n}\n"
  },
  {
    "path": "tests/mifo/Makefile",
    "content": "CONNECTALDIR?=../..\nS2H_INTERFACES = MifoTestRequest:MifoTest.request\nH2S_INTERFACES = MifoTest:MifoTestIndication\n\nBSVFILES = MifoTest.bsv\nCPPFILES=testmifo.cpp\n\ninclude $(CONNECTALDIR)/Makefile.connectal\n"
  },
  {
    "path": "tests/mifo/MifoTest.bsv",
    "content": "// Copyright (c) 2013 Nokia, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\nimport FIFO::*;\nimport MIFO::*;\nimport Pipe::*;\nimport Vector::*;\n\ninterface MifoTestIndication;\n    method Action mifo32(Bit#(32) v);\n    method Action mifo64(Bit#(32) v, Bit#(32) w);\n    method Action fimo64(Bit#(32) v0, Bit#(32) v1);\n    method Action fimo96(Bit#(32) v0, Bit#(32) v1, Bit#(32) v2);\n    method Action fimo128(Bit#(32) v0, Bit#(32) v1, Bit#(32) v2, Bit#(32) v3);\nendinterface\n\ninterface MifoTestRequest;\n   method Action mifo32(Bit#(32) n, Bit#(32) v0, Bit#(32) v1, Bit#(32) v2, Bit#(32) v3);\n   method Action mifo64(Bit#(32) n, Bit#(32) v0, Bit#(32) v1, Bit#(32) v2, Bit#(32) v3);\n   method Action fimo32(Bit#(32) v0);\nendinterface\n\ninterface MifoTest;\n   interface MifoTestRequest request;\nendinterface\n\nmodule mkMifoTest#(MifoTestIndication indication)(MifoTest);\n   MIFO#(4,1,4,Bit#(32)) mifo1 <- mkMIFO();\n   MIFO#(4,2,4,Bit#(32)) mifo2 <- mkMIFO();\n   FIMO#(1,4,4,Bit#(32)) fimo1 <- mkFIMO();\n   FIMO#(1,4,4,Bit#(32)) fimo2 <- mkFIMO();\n   FIMO#(1,4,4,Bit#(32)) fimo3 <- mkFIMO();\n\n   rule mifo32out if (mifo1.deqReady());\n      let v = mifo1.first();\n      mifo1.deq();\n      indication.mifo32(v[0]);\n   endrule\n   rule mifo64out if (mifo2.deqReady());\n      let v = mifo2.first();\n      mifo2.deq();\n      indication.mifo64(v[0], v[1]);\n   endrule\n\n   rule fimo64out;\n      let v = fimo1.out[2].first();\n      fimo1.out[2].deq();\n      $display(\"fimo32 value: %h\", v);\n      indication.fimo64(v[0], v[1]);\n   endrule\n   rule fimo96out;\n      let v = fimo2.out[3].first();\n      fimo2.out[3].deq();\n      $display(\"fimo96 value: %h\", v);\n      indication.fimo96(v[0], v[1], v[2]);\n   endrule\n   rule fimo128out;\n      let v = fimo3.out[4].first();\n      fimo3.out[4].deq();\n      $display(\"fimo128 value: %h\", v);\n      indication.fimo128(v[0], v[1], v[2], v[3]);\n   endrule\n\n   interface MifoTestRequest request;\n   method Action mifo32(Bit#(32) n, Bit#(32) v0, Bit#(32) v1, Bit#(32) v2, Bit#(32) v3);\n      Vector#(4, Bit#(32)) vec = newVector();\n      vec[0] = v0;\n      vec[1] = v1;\n      vec[2] = v2;\n      vec[3] = v3;\n      mifo1.enq(unpack(truncate(n)), vec);\n   endmethod\n   method Action mifo64(Bit#(32) n, Bit#(32) v0, Bit#(32) v1, Bit#(32) v2, Bit#(32) v3);\n      Vector#(4, Bit#(32)) vec = newVector();\n      vec[0] = v0;\n      vec[1] = v1;\n      vec[2] = v2;\n      vec[3] = v3;\n      mifo2.enq(unpack(truncate(n)), vec);\n   endmethod\n\n   method Action fimo32(Bit#(32) v);\n      Vector#(1, Bit#(32)) vec = replicate(v);\n      fimo1.in.enq(vec);\n      fimo2.in.enq(vec);\n      fimo3.in.enq(vec);\n   endmethod\n   endinterface\nendmodule\n"
  },
  {
    "path": "tests/mifo/testmifo.cpp",
    "content": "/* Copyright (c) 2014 Quanta Research Cambridge, Inc\n *\n * Permission is hereby granted, free of charge, to any person obtaining a\n * copy of this software and associated documentation files (the \"Software\"),\n * to deal in the Software without restriction, including without limitation\n * the rights to use, copy, modify, merge, publish, distribute, sublicense,\n * and/or sell copies of the Software, and to permit persons to whom the\n * Software is furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n * DEALINGS IN THE SOFTWARE.\n */\n#include <assert.h>\n#include \"MifoTestIndication.h\"\n#include \"MifoTestRequest.h\"\n\nstatic uint32_t vs[4] = { 22, 0, 1, 2};\n\nclass MifoTestIndication : public MifoTestIndicationWrapper\n{  \npublic:\n  uint32_t cnt;\n  void incr_cnt(){\n    if (++cnt == (32+0))\n      exit(0);\n  }\n  virtual void mifo32(uint32_t a) {\n    uint32_t ea = vs[cnt % 4];\n    fprintf(stderr, \"mifo32(%d expected %d)\\n\", a, ea);\n    assert(a == ea);\n    incr_cnt();\n  }\n  virtual void mifo64(uint32_t a, uint32_t b) {\n    uint32_t ea = vs[cnt % 4];\n    uint32_t eb = vs[(cnt+1) % 4];\n    fprintf(stderr, \"mifo64(%d,%d) expected (%d,%d)\\n\", a, b, ea, eb);\n    assert(a == ea);\n    assert(b == eb);\n    incr_cnt();\n    incr_cnt();\n  }\n  virtual void fimo64(uint32_t a, uint32_t b) {\n    uint32_t ea = 68;\n    uint32_t eb = 47;\n    fprintf(stderr, \"fimo64(%d,%d) expected (%d,%d)\\n\", a, b, ea, eb);\n    assert(a == ea);\n    assert(b == eb);\n    //incr_cnt();\n    //incr_cnt();\n  }\n  virtual void fimo96(uint32_t a, uint32_t b, uint32_t c) {\n    uint32_t ea = 68;\n    uint32_t eb = 47;\n    uint32_t ec = 22;\n    fprintf(stderr, \"fimo96(%d,%d,%d) expected (%d,%d,%d)\\n\", a, b, c, ea, eb, ec);\n    assert(a == ea);\n    assert(b == eb);\n    assert(c == ec);\n    //incr_cnt();\n    //incr_cnt();\n  }\n  virtual void fimo128(uint32_t a, uint32_t b, uint32_t c, uint32_t d) {\n    uint32_t ea = 68;\n    uint32_t eb = 47;\n    uint32_t ec = 22;\n    uint32_t ed = 23;\n    fprintf(stderr, \"fimo128(%d,%d,%d,%d) expected (%d,%d,%d,%d)\\n\", a, b, c, d, ea, eb, ec, ed);\n    assert(a == ea);\n    assert(b == eb);\n    assert(c == ec);\n    assert(d == ed);\n    //incr_cnt();\n    //incr_cnt();\n  }\n\n  MifoTestIndication(unsigned int id) : MifoTestIndicationWrapper(id), cnt(0){}\n};\n\nint main(int argc, const char **argv)\n{\n  MifoTestIndication indication(IfcNames_MifoTestIndicationH2S);\n  MifoTestRequestProxy *device = new MifoTestRequestProxy(IfcNames_MifoTestRequestS2H);\n\n  device->fimo32(68);\n  sleep(1);\n  device->fimo32(47);\n  sleep(1);\n  device->fimo32(22);\n  sleep(1);\n  device->fimo32(23);\n  sleep(1);\n\n  fprintf(stderr, \"Main::calling mifo32(%d)\\n\", 22);\n  device->mifo32(4, 22, 0, 1, 2);\n  sleep(1);\n\n  device->mifo32(1, 22, 7, 7, 7);\n  sleep(1);\n  device->mifo32(1, 0, 7, 7, 7);\n  sleep(1);\n  device->mifo32(1, 1, 7, 7, 7);\n  sleep(1);\n  device->mifo32(1, 2, 7, 7, 7);\n  sleep(1);\n\n  device->mifo32(2, 22, 0, 7, 7);\n  sleep(1);\n  device->mifo32(2, 1, 2, 7, 7);\n  sleep(1);\n  device->mifo32(1, 22, 7, 7, 7);\n  sleep(1);\n  device->mifo32(3, 0, 1, 2, 7);\n  sleep(1);\n\n  device->mifo64(4, 22, 0, 1, 2);\n  sleep(1);\n\n  device->mifo64(1, 22, 7, 7, 7);\n  sleep(1);\n  device->mifo64(1, 0, 7, 7, 7);\n  sleep(1);\n  device->mifo64(1, 1, 7, 7, 7);\n  sleep(1);\n  device->mifo64(1, 2, 7, 7, 7);\n  sleep(1);\n\n  device->mifo64(1, 22, 7, 7, 7);\n  sleep(1);\n  device->mifo64(3, 0, 1, 2, 7);\n  sleep(1);\n  device->mifo64(3, 22, 0, 1, 7);\n  sleep(1);\n  device->mifo64(1, 2, 7, 7, 7);\n  sleep(1);\n\n  fprintf(stderr, \"Main::about to go to sleep\\n\");\n  while(true){sleep(2);}\n}\n"
  },
  {
    "path": "tests/nandsim_manual/Makefile",
    "content": "CONNECTALDIR?=../..\nS2H_INTERFACES = NandCfgRequest:NandSim.request\nH2S_INTERFACES = NandSim:NandCfgIndication\nMEM_READ_INTERFACES = lNandSim.readClient\nMEM_WRITE_INTERFACES = lNandSim.writeClient\n\nNANDLIB = ../../lib/nandsim\nBSVFILES = $(NANDLIB)/bsv/NandSim.bsv\nCPPFILES=testnandsim_test.cpp\n#CPPFILES=testnandsim.cpp\n#CPPFILES=nandsim_manual.c\n\ninclude $(CONNECTALDIR)/Makefile.connectal\n"
  },
  {
    "path": "tests/nandsim_manual/kernel/Makefile",
    "content": "\n# grep get_pcie_portal_descriptor /proc/kallsyms \n\n###################### Flags for using KC705   ###################\n#BOARD=kc705\n###################### Flags for using VC707   ###################\n#BOARD=vc707\n###################### Flags for using zedboard ##################\n#BOARD=zedboard\n###################### Flags for using Bluesim ###################\nBOARD=bluesim\n###################### End of target h/w flags ###################\n\nifeq ($(BOARD),bluesim)\n    HARDWARE_FLAGS=-DBSIM\nendif\n\nexport KROOT=/lib/modules/$(shell uname -r)/build\nCPPDIR=../../../cpp\nBOARDDIR=../$(BOARD)/jni\nDRIVERDIR=$(src)/../../../drivers\n\nKBUILD_EXTRA_SYMBOLS := $(DRIVERDIR)/pcieportal/Module.symvers $(DRIVERDIR)/portalmem/Module.symvers\n\nkernel_exe-y := ../nandsim_manual.o \\\n     $(BOARDDIR)/DmaConfigProxy.o \\\n     $(BOARDDIR)/DmaIndicationWrapper.o \\\n     $(BOARDDIR)/NandSimIndicationWrapper.o \\\n     $(BOARDDIR)/NandSimRequestProxy.o \\\n     $(CPPDIR)/portal.o \\\n     $(CPPDIR)/dmaManager.o \\\n     $(CPPDIR)/kernel_module.o\n\nifeq ($(BOARD),bluesim)\nkernel_exe-y += $(CPPDIR)/sock_utils.o\nendif\n\nobj-m := kernel_exe.o\n\nccflags-y := -I$(src)/.. -I$(DRIVERDIR)/pcieportal -I$(DRIVERDIR)/portalmem -I$(src)/$(CPPDIR) -I$(src)/$(BOARDDIR) $(HARDWARE_FLAGS) -DBOARD_$(BOARD)\n\ndefault:\n\t$(MAKE) -C $(KROOT) M=$(PWD) modules\n\nclean:\n\t$(MAKE) -C $(KROOT) M=$(PWD) clean\n\trm -f $(kernel_exe-y) a.out bsim_relay\n\nCURRENTMOD=$(shell lsmod | grep kernel_exe)\n\nrun: host\nifeq ($(BOARD),bluesim)\n\t@echo running bsim\n\t../bluesim/bin/bsim& echo $$! >tmp.bluesim.makefile.pid\nelse\n\tfpgajtag ../$(BOARD)/bin/mkTop.bin.gz\nendif\nifneq (\"$(CURRENTMOD)\", \"\")\n\tsudo rmmod kernel_exe\n\t#sudo rmmod bdbm_drv\nendif\n\tsudo insmod kernel_exe.ko\n\t#sudo insmod bdbm_drv.ko\nifeq ($(BOARD),bluesim)\n\t./bsim_relay\n\tkill `cat tmp.bluesim.makefile.pid`\n\t#killall bluetcl\nendif\n\tsudo rmmod kernel_exe\n\t#sudo rmmod bdbm_drv\n\tdmesg | tail -30\n\t@rm -f tmp.bluesim.makefile.pid\n\n#\n# Target for making userspace bsim_relay program\nCPPDIR=../../../cpp\nHOSTSOURCES=$(CPPDIR)/bsim_relay.c $(CPPDIR)/sock_utils.c\n\nhost: $(HOSTSOURCES)\nifeq ($(BOARD),bluesim)\n\tgcc -o bsim_relay -g -I$(CPPDIR) $(HOSTSOURCES) -lpthread\nendif\n"
  },
  {
    "path": "tests/nandsim_manual/nandsim_manual.c",
    "content": "/* Copyright (c) 2014 Quanta Research Cambridge, Inc\n *\n * Permission is hereby granted, free of charge, to any person obtaining a\n * copy of this software and associated documentation files (the \"Software\"),\n * to deal in the Software without restriction, including without limitation\n * the rights to use, copy, modify, merge, publish, distribute, sublicense,\n * and/or sell copies of the Software, and to permit persons to whom the\n * Software is furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n * DEALINGS IN THE SOFTWARE.\n */\n#ifdef __KERNEL__\n#include <linux/delay.h>  // msleep\n#include <linux/kthread.h>\n#else\n#include <string.h>\n#include <sys/mman.h>\n#include <pthread.h>\n#include <fcntl.h>\n#include <sys/select.h>\n#endif\n#include \"dmaManager.h\"\n#include \"sock_utils.h\"  // bsim_poll_interrupt()\n#include \"GeneratedTypes.h\" \n\n#define MAX_INDARRAY 4\nstatic PortalInternal intarr[MAX_INDARRAY];\nstatic sem_t test_sem;\n#ifndef SIMULATION\n#define numWords 0x1240000/4 // make sure to allocate at least one entry of each size\n#else\n#define numWords 0x124000/4\n#endif\nstatic long alloc_sz = numWords*sizeof(unsigned int);\nstatic DmaManagerPrivate priv;\nsize_t numBytes = 1 << 12;\nsize_t nandBytes = 1 << 24;\n\nint NandCfgIndicationWrappereraseDone_cb(  struct PortalInternal *p, const uint32_t tag )\n{\n        PORTAL_PRINTF( \"NandCfg_eraseDone(tag = %x)\\n\", tag);\n        sem_post(&test_sem);\n        return 0;\n}\nint NandCfgIndicationWrapperwriteDone_cb(  struct PortalInternal *p, const uint32_t tag )\n{\n        PORTAL_PRINTF( \"NandCfg_writeDone(tag = %x)\\n\", tag);\n        sem_post(&test_sem);\n        return 0;\n}\nint NandCfgIndicationWrapperreadDone_cb(  struct PortalInternal *p, const uint32_t tag )\n{\n        PORTAL_PRINTF( \"NandCfg_readDone(tag = %x)\\n\", tag);\n        sem_post(&test_sem);\n        return 0;\n}\nint NandCfgIndicationWrapperconfigureNandDone_cb(  struct PortalInternal *p )\n{\n        PORTAL_PRINTF( \"NandCfg_NandDone\\n\");\n        sem_post(&test_sem);\n        return 0;\n}\nint DmaIndicationWrapperconfigResp_cb(  struct PortalInternal *p, const uint32_t pointer )\n{\n        PORTAL_PRINTF(\"DmaIndication_configResp(physAddr=%x)\\n\", pointer);\n        sem_post(&priv.confSem);\n        return 0;\n}\nint DmaIndicationWrapperaddrResponse_cb(  struct PortalInternal *p, const uint64_t physAddr )\n{\n        PORTAL_PRINTF(\"DmaIndication_addrResponse(physAddr=%\"PRIx64\")\\n\", physAddr);\n        return 0;\n}\nint DmaIndicationWrapperreportStateDbg_cb(  struct PortalInternal *p, const DmaDbgRec rec )\n{\n        PORTAL_PRINTF(\"reportStateDbg: {x:%08x y:%08x z:%08x w:%08x}\\n\", rec.x,rec.y,rec.z,rec.w);\n        sem_post(&priv.dbgSem);\n        return 0;\n}\nint DmaIndicationWrapperreportMemoryTraffic_cb(  struct PortalInternal *p, const uint64_t words )\n{\n        //PORTAL_PRINTF(\"reportMemoryTraffic: words=%\"PRIx64\"\\n\", words);\n        priv.mtCnt = words;\n        sem_post(&priv.mtSem);\n        return 0;\n}\nint DmaIndicationWrapperdmaError_cb(  struct PortalInternal *p, const uint32_t code, const uint32_t pointer, const uint64_t offset, const uint64_t extra ) \n{\n        PORTAL_PRINTF(\"DmaIndication::dmaError(code=%x, pointer=%x, offset=%\"PRIx64\" extra=%\"PRIx64\"\\n\", code, pointer, offset, extra);\n        return 0;\n}\n\nvoid manual_event(void)\n{\n    int i;\n    for(i = 0; i < MAX_INDARRAY; i++)\n      event_hardware(&intarr[i]);\n}\n\n#ifdef __KERNEL__\nDECLARE_COMPLETION(worker_completion);\n#endif\nstatic void *pthread_worker(void *p)\n{\n    void *rc = NULL;\n    while(1) {\n#if defined(BSIM) && !defined(__KERNEL__)\n        if(bsim_poll_interrupt())\n#endif\n        manual_event();\n#ifdef __KERNEL__\n        msleep(10);\n        if(kthread_should_stop()) {\n\t\t    PORTAL_PRINTF(\"pthread_worker ends\\n\");\n            break;\n\t\t}\n#else ///////////////////////// userspace version\n        struct timeval timeout;\n        timeout.tv_sec = 0;\n        timeout.tv_usec = 10000;\n        select(0, NULL, NULL, NULL, &timeout);\n#endif\n    }\n#ifdef __KERNEL__\n    complete(&worker_completion);\n#endif\n    return rc;\n}\n\nint main(int argc, const char **argv)\n{\n  int srcAlloc;\n  int nandAlloc;\n  unsigned int *srcBuffer;\n  unsigned int ref_srcAlloc;\n  unsigned int ref_nandAlloc;\n  int rc = 0;\n  unsigned int i;\n  pthread_t tid = 0;\n\n  init_portal_internal(&intarr[0], IfcNames_DmaIndicationH2S, DEFAULT_TILE, DmaIndication_handleMessage, NULL, NULL, NULL, DmaIndication_reqinfo);\n  init_portal_internal(&intarr[1], IfcNames_NandCfgIndicationH2S, DEFAULT_TILE, NandCfgIndication_handleMessage, NULL, NULL, NULL, NandCfgIndication_reqinfo);\n  init_portal_internal(&intarr[2], IfcNames_MMURequestS2H, DEFAULT_TILE, NULL, NULL, NULL, NULL, MMURequest_reqinfo);\n  init_portal_internal(&intarr[3], IfcNames_NandCfgRequestS2H, DEFAULT_TILE, NULL, NULL, NULL, NULL, NandCfgRequest_reqinfo);\n\n  sem_init(&test_sem, 0, 0);\n  DmaManager_init(&priv, &intarr[2]);\n  srcAlloc = portalAlloc(alloc_sz, 0);\n  if(rc){\n    PORTAL_PRINTF(\"portal alloc failed rc=%d\\n\", rc);\n    return rc;\n  }\n\n  PORTAL_PRINTF( \"Main: creating exec thread\\n\");\n  if(pthread_create(&tid, NULL, pthread_worker, NULL)){\n   PORTAL_PRINTF( \"error creating exec thread\\n\");\n   return -1;\n  }\n  srcBuffer = (unsigned int *)portalMmap(srcAlloc, alloc_sz);\n\n  for(i = 0; i < numWords; i++) {\n    srcBuffer[i] = i;\n  }\n\n  PORTAL_PRINTF(\"Test 1: check for operations\\n\");\n  portalCacheFlush(srcAlloc, srcBuffer, alloc_sz, 1);\n  PORTAL_PRINTF(\"Main: before DmaManager_reference(%u)\\n\", srcAlloc);\n  ref_srcAlloc = DmaManager_reference(&priv, srcAlloc);\n\n\n  nandAlloc = portalAlloc(nandBytes, 0);\n  ref_nandAlloc = DmaManager_reference(&priv, nandAlloc);\n  PORTAL_PRINTF(\"Main::configure NAND fd=%d ref=%d\\n\", nandAlloc, ref_nandAlloc);\n  NandCfgRequest_configureNand(&intarr[3], ref_nandAlloc, nandBytes);\n  sem_wait(&test_sem);\n\n\n  PORTAL_PRINTF( \"Main::starting write - begin %08lx\\n\", (long)numBytes);\n  NandCfgRequest_startWrite(&intarr[3], ref_srcAlloc, 0, 0, numBytes, 16);\n  PORTAL_PRINTF( \"Main:: wait for semaphore\\n\");\n  sem_wait(&test_sem);\n\n  for(i = 0; i < numWords; i++) {\n    srcBuffer[i] = 0;\n  }\n  PORTAL_PRINTF( \"Main::starting read %08lx\\n\", (long)numBytes);\n  NandCfgRequest_startRead(&intarr[3], ref_srcAlloc, 0, 0, numBytes, 16);\n  sem_wait(&test_sem);\n  PORTAL_PRINTF(\"read: %u %u %u %u\\n\", srcBuffer[0], srcBuffer[1], srcBuffer[2], srcBuffer[3]);\n\n  PORTAL_PRINTF( \"Main::starting erase %08lx\\n\", (long)numBytes);\n  NandCfgRequest_startErase(&intarr[3], 0, numBytes);\n  sem_wait(&test_sem);\n\n  PORTAL_PRINTF( \"Main::starting read %08lx\\n\", (long)numBytes);\n  NandCfgRequest_startRead(&intarr[3], ref_srcAlloc, 0, 0, numBytes, 16);\n  sem_wait(&test_sem);\n  PORTAL_PRINTF(\"read: %u %u %u %u\\n\", srcBuffer[0], srcBuffer[1], srcBuffer[2], srcBuffer[3]);\n\n\n  PORTAL_PRINTF(\"\\n\\nTest 2: check for match\\n\");\n  {\n  unsigned long loop = 0;\n  unsigned long match = 0, mismatch = 0;\n  while(loop < nandBytes) {\n\t  unsigned int i;\n\t  for(i = 0; i < numBytes/sizeof(srcBuffer[0]); i++) {\n\t\t  srcBuffer[i] = loop+i;\n\t  }\n\n\t  /*PORTAL_PRINTF(\"Main::starting write ref=%d, len=%08lx (%lu)\\n\", ref_srcAlloc, (long)numBytes, loop);*/\n  \t  NandCfgRequest_startWrite(&intarr[3], ref_srcAlloc, 0, loop, numBytes, 16);\n      sem_wait(&test_sem);\n\n\t  loop+=numBytes;\n  }\n\n  loop = 0;\n  while(loop < nandBytes) {\n\t  unsigned int i;\n\t  /*PORTAL_PRINTF(\"Main::starting read %08lx (%lu)\\n\", (long)numBytes, loop);*/\n\t  NandCfgRequest_startRead(&intarr[3], ref_srcAlloc, 0, loop, numBytes, 16);\n\t  sem_wait(&test_sem);\n\n\t  for(i = 0; i < numBytes/sizeof(srcBuffer[0]); i++) {\n\t\t  if(srcBuffer[i] != loop+i) {\n\t\t\t  PORTAL_PRINTF(\"Main::mismatch [%08lx] != [%08lx]\\n\", (long)loop+i, (long)srcBuffer[i]);\n\t\t\t  mismatch++;\n\t\t  } else {\n\t\t\t  match++;\n\t\t  }\n\t  }\n\n\t  loop+=numBytes;\n  }\n\n  PORTAL_PRINTF(\"Main::Summary: match=%lu mismatch:%lu (%lu) (%f percent)\\n\", \n\t\tmatch, mismatch, match+mismatch, (float)mismatch/(float)(match+mismatch)*100.0);\n  }\n\n  PORTAL_PRINTF( \"Main: all done\\n\");\n#ifdef __KERNEL__\n  if(tid && !kthread_stop(tid)) {\n    PORTAL_PRINTF(\"kthread stops\\n\");\n  }\n  wait_for_completion(&worker_completion);\n#endif\n  PORTAL_PRINTF(\"Main: ends\\n\");\n  return 0;\n}\n"
  },
  {
    "path": "tests/nandsim_manual/testnandsim.cpp",
    "content": "/* Copyright (c) 2014 Quanta Research Cambridge, Inc\n *\n * Permission is hereby granted, free of charge, to any person obtaining a\n * copy of this software and associated documentation files (the \"Software\"),\n * to deal in the Software without restriction, including without limitation\n * the rights to use, copy, modify, merge, publish, distribute, sublicense,\n * and/or sell copies of the Software, and to permit persons to whom the\n * Software is furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n * DEALINGS IN THE SOFTWARE.\n */\n#include \"dmaManager.h\"\n#include \"NandCfgIndication.h\"\n#include \"NandCfgRequest.h\"\n\nint srcAlloc, nandAlloc;\nunsigned int *srcBuffer = 0;\nsize_t numBytes = 1 << 12;\nsize_t nandBytes = 1 << 24;\n\nclass NandCfgIndication : public NandCfgIndicationWrapper\n{\npublic:\n  unsigned int rDataCnt;\n  virtual void readDone(uint32_t v){\n    fprintf(stderr, \"NandCfg::readDone v=%x\\n\", v);\n    sem_post(&sem);\n  }\n  virtual void writeDone(uint32_t v){\n    fprintf(stderr, \"NandCfg::writeDone v=%x\\n\", v);\n    sem_post(&sem);\n  }\n  virtual void eraseDone(uint32_t v){\n    fprintf(stderr, \"NandCfg::eraseDone v=%x\\n\", v);\n    sem_post(&sem);\n  }\n  virtual void configureNandDone(){\n    fprintf(stderr, \"NandCfg::configureNandDone\\n\");\n    sem_post(&sem);\n  }\n\n  NandCfgIndication(int id) : NandCfgIndicationWrapper(id) {\n    sem_init(&sem, 0, 0);\n  }\n  void wait() {\n    fprintf(stderr, \"NandCfg::wait for semaphore\\n\");\n    sem_wait(&sem);\n  }\nprivate:\n  sem_t sem;\n};\n\nint main(int argc, const char **argv)\n{\n  unsigned int srcGen = 0;\n  NandCfgRequestProxy *device = 0;\n  NandCfgIndication *deviceIndication = 0;\n\n  fprintf(stderr, \"Main::%s %s\\n\", __DATE__, __TIME__);\n\n  device = new NandCfgRequestProxy(IfcNames_NandCfgRequestS2H);\n  deviceIndication = new NandCfgIndication(IfcNames_NandCfgIndicationH2S);\n  DmaManager *dma = platformInit();\n\n  fprintf(stderr, \"Main::allocating memory...\\n\");\n\n  srcAlloc = portalAlloc(numBytes, 0);\n  srcBuffer = (unsigned int *)portalMmap(srcAlloc, numBytes);\n  fprintf(stderr, \"fd=%d, srcBuffer=%p\\n\", srcAlloc, srcBuffer);\n\n  for (unsigned int i = 0; i < numBytes/sizeof(srcBuffer[0]); i++)\n    srcBuffer[i] = srcGen++;\n    \n  portalCacheFlush(srcAlloc, srcBuffer, numBytes, 1);\n  fprintf(stderr, \"Main::flush and invalidate complete\\n\");\n  sleep(1);\n\n  unsigned int ref_srcAlloc = dma->reference(srcAlloc);\n\n  nandAlloc = portalAlloc(nandBytes, 0);\n  int ref_nandAlloc = dma->reference(nandAlloc);\n  fprintf(stderr, \"NAND alloc fd=%d ref=%d\\n\", nandAlloc, ref_nandAlloc);\n  device->configureNand(ref_nandAlloc, nandBytes);\n  deviceIndication->wait();\n\n  fprintf(stderr, \"Main::starting write ref=%d, len=%08lx\\n\", ref_srcAlloc, (long)numBytes);\n  device->startWrite(ref_srcAlloc, 0, 0, numBytes, 16);\n  deviceIndication->wait();\n\n  fprintf(stderr, \"Main::starting read %08lx\\n\", (long)numBytes);\n  device->startRead(ref_srcAlloc, 0, 0, numBytes, 16);\n  deviceIndication->wait();\n\n  fprintf(stderr, \"Main::starting erase %08lx\\n\", (long)numBytes);\n  device->startErase(0, numBytes);\n  deviceIndication->wait();\n\n  fprintf(stderr, \"Main::starting read %08lx\\n\", (long)numBytes);\n  device->startRead(ref_srcAlloc, 0, 0, numBytes, 16);\n  deviceIndication->wait();\n  return 0;\n}\n"
  },
  {
    "path": "tests/nandsim_manual/testnandsim_test.cpp",
    "content": "/* Copyright (c) 2014 Quanta Research Cambridge, Inc\n *\n * Permission is hereby granted, free of charge, to any person obtaining a\n * copy of this software and associated documentation files (the \"Software\"),\n * to deal in the Software without restriction, including without limitation\n * the rights to use, copy, modify, merge, publish, distribute, sublicense,\n * and/or sell copies of the Software, and to permit persons to whom the\n * Software is furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n * DEALINGS IN THE SOFTWARE.\n */\n#include \"dmaManager.h\"\n#include \"NandCfgIndication.h\"\n#include \"NandCfgRequest.h\"\n\nint srcAlloc, nandAlloc;\nunsigned int *srcBuffer = 0;\nsize_t numBytes = 1 << 12;\n#ifndef BOARD_bluesim\nsize_t nandBytes = 1 << 24;\n#else\nsize_t nandBytes = 1 << 14;\n#endif\n\nclass NandCfgIndication : public NandCfgIndicationWrapper\n{\npublic:\n  unsigned int rDataCnt;\n  virtual void readDone(uint32_t v){\n    fprintf(stderr, \"NandCfg::readDone v=%x\\n\", v);\n    sem_post(&sem);\n  }\n  virtual void writeDone(uint32_t v){\n    fprintf(stderr, \"NandCfg::writeDone v=%x\\n\", v);\n    sem_post(&sem);\n  }\n  virtual void eraseDone(uint32_t v){\n    fprintf(stderr, \"NandCfg::eraseDone v=%x\\n\", v);\n    sem_post(&sem);\n  }\n  virtual void configureNandDone(){\n    fprintf(stderr, \"NandCfg::configureNandDone\\n\");\n    sem_post(&sem);\n  }\n\n  NandCfgIndication(int id) : NandCfgIndicationWrapper(id) {\n    sem_init(&sem, 0, 0);\n  }\n  void wait() {\n    fprintf(stderr, \"NandCfg::wait for semaphore\\n\");\n    sem_wait(&sem);\n  }\nprivate:\n  sem_t sem;\n};\n\nint main(int argc, const char **argv)\n{\n  unsigned int srcGen = 0;\n  NandCfgRequestProxy *device = 0;\n  NandCfgIndication *deviceIndication = 0;\n\n  fprintf(stderr, \"chamdoo-test\\n\");\n  fprintf(stderr, \"Main::%s %s\\n\", __DATE__, __TIME__);\n\n  device = new NandCfgRequestProxy(IfcNames_NandCfgRequestS2H);\n  deviceIndication = new NandCfgIndication(IfcNames_NandCfgIndicationH2S);\n  DmaManager *dma = platformInit();\n\n  fprintf(stderr, \"Main::allocating memory...\\n\");\n\n  srcAlloc = portalAlloc(numBytes, 0);\n  srcBuffer = (unsigned int *)portalMmap(srcAlloc, numBytes);\n  fprintf(stderr, \"fd=%d, srcBuffer=%p\\n\", srcAlloc, srcBuffer);\n\n  for (unsigned int i = 0; i < numBytes/sizeof(srcBuffer[0]); i++)\n    srcBuffer[i] = srcGen++;\n    \n  portalCacheFlush(srcAlloc, srcBuffer, numBytes, 1);\n  fprintf(stderr, \"Main::flush and invalidate complete\\n\");\n  sleep(1);\n\n  unsigned int ref_srcAlloc = dma->reference(srcAlloc);\n\n  nandAlloc = portalAlloc(nandBytes, 0);\n  int ref_nandAlloc = dma->reference(nandAlloc);\n  fprintf(stderr, \"NAND alloc fd=%d ref=%d\\n\", nandAlloc, ref_nandAlloc);\n  device->configureNand(ref_nandAlloc, nandBytes);\n  deviceIndication->wait();\n\n  /* do tests */\n  unsigned long loop = 0;\n  unsigned long match = 0, mismatch = 0;\n  while (loop < nandBytes) {\n\t  unsigned int i;\n\t  for (i = 0; i < numBytes/sizeof(srcBuffer[0]); i++) {\n\t\t  srcBuffer[i] = loop+i;\n\t  }\n\n\t  fprintf(stderr, \"Main::starting write ref=%d, len=%08lx (%lu)\\n\", ref_srcAlloc, (long)numBytes, loop);\n\t  device->startWrite(ref_srcAlloc, 0, loop, numBytes, 16);\n\t  deviceIndication->wait();\n\n\t  loop+=numBytes;\n  }\n\n  loop = 0;\n  while (loop < nandBytes) {\n\t  unsigned int i;\n\t  fprintf(stderr, \"Main::starting read %08lx (%lu)\\n\", (long)numBytes, loop);\n\t  device->startRead(ref_srcAlloc, 0, loop, numBytes, 16);\n\t  deviceIndication->wait();\n\n\t  for (i = 0; i < numBytes/sizeof(srcBuffer[0]); i++) {\n\t\t  if (srcBuffer[i] != loop+i) {\n\t\t\t  fprintf(stderr, \"Main::mismatch [%08lx] != [%08lx]\\n\", (long)loop+i, (long)srcBuffer[i]);\n\t\t\t  mismatch++;\n\t\t  } else {\n\t\t\t  match++;\n\t\t  }\n\t  }\n\n\t  loop+=numBytes;\n  }\n  /* end */\n\n  fprintf(stderr, \"Main::Summary: match=%lu mismatch:%lu (%lu) (%f percent)\\n\", \n\t\tmatch, mismatch, match+mismatch, (float)mismatch/(float)(match+mismatch)*100.0);\n\n  return (mismatch > 0);\n}\n"
  },
  {
    "path": "tests/nvme_core/string_search.cpp",
    "content": "#include <stdio.h>\n//#include \"jsoncpp/json/json.h\"\n#include <map>\n#include <errno.h>\n#include <fcntl.h>\n#include <string>\n#include <sys/types.h>\n#include <sys/stat.h>\n#include <unistd.h>\n\n#include <ConnectalProjectConfig.h> // BlocksPerRequest\n\n#include \"nvme.h\"\n#include \"mp.h\"\n\nenum MsgFromSoftwareTag {\n   REQ_Loopback,\n   REQ_Needle,\n   REQ_MpNext,\n   REQ_Clear,\n   REQ_Opcode,\n   REQ_StartBlock,\n   REQ_NumBlocks,\n   REQ_Start\n};\n\nstruct MsgFromSoftware {\n  int data : 24;\n  MsgFromSoftwareTag tag : 8;\n};\n\nenum MsgToSoftwareTag {\n   RESP_Loopback=1,\n   RESP_LocDone=2,\n   RESP_TransferDone=3\n};\n\nstruct MsgToSoftware {\n  int data : 24;\n  MsgToSoftwareTag tag : 8;\n};\n\nunion Msg {\n  MsgToSoftware to;\n  MsgFromSoftware from;\n  int bits;\n};\n\nstatic Nvme *nvme;\n\nvoid sendMessage(MsgFromSoftwareTag tag, int data, bool last=false)\n{\n    Msg msg;\n    msg.from.tag = tag;\n    msg.from.data = data;\n    fprintf(stderr, \"%s:%d tag=%x data=%06x last=%d msg=%08x\\n\", __FUNCTION__, __LINE__, tag, data, last, msg.bits);\n    nvme->messageFromSoftware(msg.bits, last);\n}\n\nint main(int argc, char * const *argv)\n{\n    nvme = new Nvme();\n\n    int opt;\n    const char *filename = 0;\n    int source_fd = -1;\n\n    const char *needle = \"needle\";\n\n    int dotrace = 0;\n    int dowrite = 0;\n    while ((opt = getopt(argc, argv, \"n:w:t\")) != -1) {\n\tswitch (opt) {\n\tcase 'n':\n\t    needle = optarg;\n\t    break;\n\tcase 't':\n\t    dotrace = 1;\n\t    break;\n\tcase 'w':\n\t    filename = optarg;\n\t    dowrite = 1;\n\t    break;\n\t}\n    }\n\n    if (dowrite) {\n\tstruct stat statbuf;\n\tint rc = stat(filename, &statbuf);\n\tif (rc < 0) {\n\t    fprintf(stderr, \"%s:%d File %s does not exist %d:%s\\n\", __FILE__, __LINE__, filename, errno, strerror(errno));\n\t    return rc;\n\t}\n    }\n\n    sleep(1);\n    nvme->setup();\n    sleep(1);\n    nvme->allocIOQueues(0);\n\n    int needle_len = strlen(needle);\n    int border[needle_len+1];\n\n    compute_borders(nvme->needleBuffer.buffer(), border, needle_len);\n    compute_MP_next(nvme->needleBuffer.buffer(), (struct MP *)nvme->mpNextBuffer.buffer(), needle_len);\n    nvme->needleBuffer.cacheInvalidate(0, 1); // flush the whole thing\n    nvme->mpNextBuffer.cacheInvalidate(0, 1); // flush the whole thing\n\n    fprintf(stderr, \"CSTS %08x\\n\", nvme->read32( 0x1c));\n    int startBlock = 100000; // base and extent of test file in SSD\n    int blocksPerRequest = BlocksPerRequest; //12*BlocksPerRequest;\n    int numBlocks = 1*blocksPerRequest; // 55; //8177;\n\n    sendMessage(REQ_Loopback, 22);\n\n    // send needle and mpNext\n    for (int i = 0; i < needle_len; i++) {\n\tstruct MP *mpNext = (struct MP *)nvme->mpNextBuffer.buffer();\n\tbool last = ((i + 1) == needle_len);\n\tfprintf(stderr, \"needle[%d]=%02x mpNext[%d]=%2x.%02x\\n\", i, needle[i], i, mpNext[i].index, mpNext[i].x);\n\tsendMessage(REQ_Needle, needle[i], last);\n\tsendMessage(REQ_MpNext, *(int *)&mpNext[i], last);\n    }\n\n    // send search command\n    sendMessage(REQ_Opcode, nvme_read);\n    sendMessage(REQ_StartBlock, startBlock);\n    sendMessage(REQ_NumBlocks, numBlocks);\n    sendMessage(REQ_Start, needle_len);\n\n    sleep(10);\n\n    nvme->dumpTrace();\n\n    return 0;\n}\n"
  },
  {
    "path": "tests/nvme_strstr/Makefile",
    "content": "CONNECTALDIR?=../..\n\nS2H_INTERFACES = NvmeRequest:NvmeSearch.request NvmeDriverRequest:NvmeSearch.driverRequest MemServerPortalRequest:NvmeSearch.bramRequest StringSearchRequest:NvmeSearch.searchRequest\nH2S_INTERFACES = NvmeSearch:NvmeIndication,NvmeDriverIndication,NvmeTrace,MemServerPortalIndication,StringSearchResponse\n\nMEM_READ_INTERFACES = lNvmeSearch.dmaReadClient\nMEM_WRITE_INTERFACES = lNvmeSearch.dmaWriteClient\n\nBSVPATH = $(CONNECTALDIR)/lib/strstr/bsv\nBSVFILES = $(CONNECTALDIR)/lib/nvme/bsv/NvmeIfc.bsv StringSearchIfc.bsv $(CONNECTALDIR)/bsv/ConnectalConfig.bsv\nCPPFILES += $(CONNECTALDIR)/lib/nvme/cpp/nvme.cpp main.cpp\nCPPFILES += $(CONNECTALDIR)/cpp/DmaBuffer.cpp\n\nCONNECTALFLAGS += -I$(CONNECTALDIR)/lib/nvme/cpp\n\nifeq ($(BOARD),miniitx100)\nPINOUT_FILE += nvme.json\nCONNECTALFLAGS += -D PcieDataBusWidth=128\nCONNECTALFLAGS += -D USE_ACP\nCONNECTALFLAGS += -D TOP_SOURCES_PORTAL_CLOCK\nCONNECTALFLAGS +=  --mainclockperiod=8\nelse\nPINOUT_FILE += fmc.json\nCONNECTALFLAGS += -D PcieDataBusWidth=128\nendif\nCONNECTALFLAGS += -D BlocksPerRequest=8\nPIN_TYPE = NvmePins\nPIN_TYPE_INCLUDE = NvmePins\nAUTOTOP = --interface pins:NvmeSearch.pins\n\nAUTOTOP += --portalclock=lNvmeSearch.portalClockSource\nCONNECTALFLAGS += --cxxflags=-std=c++11\nCONNECTALFLAGS += --stl=c++_static\n\nCONNECTALFLAGS += -I $(CONNECTALDIR)/lib/strstr/cpp\nCONNECTALFLAGS += --bsvpath=../spikehw\nCONNECTALFLAGS += --xci=$(IPDIR)/$(BOARD)/axi_pcie_rp/axi_pcie_rp.xci\nCONNECTALFLAGS += --implconstraint=nvme.xdc\n\n#CONNECTALFLAGS += -DNVME_ACCELERATOR_INTERFACE=1\n\ninclude $(CONNECTALDIR)/Makefile.connectal\n"
  },
  {
    "path": "tests/nvme_strstr/NvmeSearch.bsv",
    "content": "// Copyright (c) 2016 Connectal Project\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\n`include \"ConnectalProjectConfig.bsv\"\nimport Arbitrate::*;\nimport BRAM::*;\nimport BuildVector::*;\nimport Clocks::*;\nimport Connectable::*;\nimport FIFOF::*;\nimport Gearbox::*;\nimport GetPut::*;\nimport Probe::*;\nimport StmtFSM::*;\nimport Vector::*;\n\nimport AddressGenerator::*;\nimport AxiBits::*;\nimport AxiStream::*;\nimport ConnectalClocks::*;\nimport ConnectalConfig::*;\nimport DefaultValue::*;\nimport GearboxGetPut::*;\nimport HostInterface::*;\nimport MemReadEngine::*;\nimport ConnectalMemTypes::*;\nimport PhysMemSlaveFromBram::*;\nimport Pipe::*;\nimport TraceMemClient::*;\nimport XilinxCells::*;\nimport MPEngine::*;\n\nimport Nvme::*;\nimport NvmeIfc::*;\nimport NvmePins::*;\nimport StringSearchIfc::*;\n\ninterface NvmeSearch;\n   interface NvmeRequest request;\n   interface NvmeDriverRequest driverRequest;\n   interface MemServerPortalRequest bramRequest;\n   interface StringSearchRequest searchRequest;\n   interface NvmeTrace trace;\n   interface NvmePins pins;\n   interface Vector#(2, MemReadClient#(DataBusWidth)) dmaReadClient;\n   interface Vector#(1, MemWriteClient#(DataBusWidth)) dmaWriteClient;\n`ifdef TOP_SOURCES_PORTAL_CLOCK\n   interface Clock portalClockSource;\n`endif\nendinterface\n\ntypedef enum {\n   Loopback,\n   Needle,\n   MpNext,\n   Clear,\n   Opcode,\n   StartBlock,\n   NumBlocks,\n   Start\n   } MsgFromSoftwareTag deriving (Bits,Eq);\n\ntypedef struct {\n   MsgFromSoftwareTag tag;\n   Bit#(24)  data;\n   } MsgFromSoftware deriving (Bits);\n\ntypedef enum {\n   Loopback=1,\n   LocDone=2,\n   TransferDone=3\n   } MsgToSoftwareTag deriving (Bits,Eq);\n\ntypedef struct {\n   MsgToSoftwareTag tag;\n   Bit#(24)  data;\n   } MsgToSoftware deriving (Bits);\n\n\n(* synthesize *)\nmodule mkSearchAcceleratorClient(NvmeAcceleratorClient);\n   Reg#(Bit#(32))                       dataCounter <- mkReg(0);\n   FIFOF#(Bit#(32))                  dataLengthFifo <- mkFIFOF();\n   Reg#(Bit#(24))                      needleLenReg <- mkReg(0);\n   MPStreamEngine#(PcieDataBusWidth,DataBusWidth)    mpEngine <- mkMPStreamEngine();\n\n   FIFOF#(MemData#(32)) msgFromSoftwareFifo <- mkFIFOF();\n   FIFOF#(MemData#(32)) msgToSoftwareFifo <- mkFIFOF();\n   FIFOF#(MemDataF#(PcieDataBusWidth)) dataFromNvmeFifo <- mkFIFOF();\n   FIFOF#(MemDataF#(PcieDataBusWidth)) dataToNvmeFifo <- mkFIFOF();\n   FIFOF#(Bit#(SizeOf#(NvmeIoCommand))) requestFifo <- mkFIFOF();\n   FIFOF#(Bit#(SizeOf#(NvmeIoResponse))) responseFifo <- mkFIFOF();\n\n   mkConnection(toPipeOut(dataFromNvmeFifo), mpEngine.haystack);\n\n   Reg#(Bit#(8)) opcode <- mkReg(extend(pack(NvmeRead)));\n   Reg#(Bit#(32)) startBlock <- mkReg(0);\n   Reg#(Bit#(32))  numBlocks <- mkReg(0);\n   Reg#(Bit#(16)) requestId <- mkReg(0);\n\n   let inmsgTagProbe <- mkProbe();\n   let inmsgDataProbe <- mkProbe();\n   let outmsgTagProbe <- mkProbe();\n   let outmsgDataProbe <- mkProbe();\n   let responseProbe <- mkProbe();\n   rule rl_msg_from_software;\n      let md <- toGet(msgFromSoftwareFifo).get();\n      MsgFromSoftware msg = unpack(truncate(md.data));\n      inmsgTagProbe <= msg.tag;\n      inmsgDataProbe <= msg.data;\n      case (msg.tag) matches\n\t Loopback: begin\n\t\t      MsgToSoftware outmsg = MsgToSoftware { tag: Loopback, data: msg.data };\n\t\t      outmsgTagProbe <= outmsg.tag;\n\t\t      outmsgDataProbe <= outmsg.data;\n\t\t      msgToSoftwareFifo.enq(MemData { data: extend(pack(outmsg)), last: md.last });\n\t\t   end\n\t Needle: mpEngine.needle.enq(MemDataF { data: extend(msg.data), first: False, last: md.last, tag: 0 });\n\t MpNext: mpEngine.mpNext.enq(MemDataF { data: extend(msg.data), first: False, last: md.last, tag: 0 });\n\t Clear:  mpEngine.clear();\n\t Opcode:         opcode <= truncate(msg.data);\n\t StartBlock: startBlock <= extend(msg.data);\n\t NumBlocks:   numBlocks <= extend(msg.data);\n\t Start: begin\n\t\t   mpEngine.start(extend(msg.data));\n\t\t   needleLenReg <= msg.data;\n\t\t   requestFifo.enq(pack(NvmeIoCommand {\n\t\t      opcode: opcode,\n\t\t      flags: 0,\n\t\t      requestId: requestId,\n\t\t      startBlock: extend(startBlock),\n\t\t      numBlocks: numBlocks,\n\t\t      dsm: 'h71 // FIXME copied value from nvme.cpp, but where did this come from?\n\t\t      }));\n\t\t   requestId <= requestId + 1;\n\t\tend\n      endcase\n   endrule\n   rule rl_response;\n      let r <- toGet(responseFifo).get();\n      NvmeIoResponse response = unpack(r);\n      Bit#(8) sct = truncate(response.statusCodeType);\n      responseProbe <= response.statusCode;\n      \n      MsgToSoftware outmsg = MsgToSoftware { tag: TransferDone, data: { sct, response.statusCode }};\n      outmsgTagProbe <= outmsg.tag;\n      outmsgDataProbe <= outmsg.data;\n      msgToSoftwareFifo.enq(MemData { data: extend(pack(outmsg)), last: True });\n   endrule\n   rule rl_match;\n      let loc <- toGet(mpEngine.locdone).get();\n      MsgToSoftware outmsg = MsgToSoftware { tag: LocDone, data: truncate(pack(loc)) };\n      outmsgTagProbe <= outmsg.tag;\n      outmsgDataProbe <= outmsg.data;\n      msgToSoftwareFifo.enq(MemData { data: extend(pack(outmsg)), last: (loc == -1) });\n   endrule\n\n   AxiStreamSlave#(32) msgFromSoftwareStream <- mkAxiStream(msgFromSoftwareFifo);\n   AxiStreamMaster#(32) msgToSoftwareStream <- mkAxiStream(msgToSoftwareFifo);\n   AxiStreamSlave#(PcieDataBusWidth) dataFromNvmeStream <- mkAxiStream(dataFromNvmeFifo);\n   AxiStreamMaster#(PcieDataBusWidth) dataToNvmeStream <- mkAxiStream(dataToNvmeFifo);\n   AxiStreamMaster#(SizeOf#(NvmeIoCommand)) requestStream <- mkAxiStream(requestFifo);\n   AxiStreamSlave#(SizeOf#(NvmeIoResponse)) responseStream <- mkAxiStream(responseFifo);\n\n   interface AxiStreamSlave msgFromSoftware = msgFromSoftwareStream;\n   interface AxiStreamMaster msgToSoftware = msgToSoftwareStream;\n   interface AxiStreamSlave dataFromNvme = dataFromNvmeStream;\n   interface AxiStreamMaster dataToNvme = dataToNvmeStream;\n   interface AxiStreamMaster request = requestStream;\n   interface AxiStreamSlave response = responseStream;\n\nendmodule\n\nmodule mkNvmeSearch#(NvmeIndication ind, NvmeDriverIndication driverInd, NvmeTrace trace, MemServerPortalIndication bramIndication,\n\t       StringSearchResponse searchIndication)(NvmeSearch);\n\n   let nvme <- mkNvme(ind, driverInd, trace, bramIndication);\n\n   MemReadEngine#(DataBusWidth,DataBusWidth,2,3) re <- mkMemReadEngine();\n\n`ifndef NVME_ACCELERATOR_INTERFACE\n   Reg#(Bit#(32))                       dataCounter <- mkReg(0);\n   FIFOF#(Bit#(32))                  dataLengthFifo <- mkFIFOF();\n   FIFOF#(MemDataF#(PcieDataBusWidth))     fifoToMp <- mkFIFOF();\n   let                                 needleLenReg <- mkReg(0);\n   MPStreamEngine#(PcieDataBusWidth,DataBusWidth)    mpEngine <- mkMPStreamEngine();\n   mkConnection(re.readServers[0].data, mpEngine.needle);\n   mkConnection(re.readServers[1].data, mpEngine.mpNext);\n   mkConnection(toPipeOut(fifoToMp), mpEngine.haystack);\n\n   Reg#(Bool) firstReg <- mkReg(True);\n   rule rl_count_data_to_mp;\n      let data <- toGet(nvme.dataFromNvme).get();\n      if (dataLengthFifo.notEmpty()) begin\n\t data.last = (dataCounter+fromInteger(valueOf(PcieDataBusWidth)/8)) >= dataLengthFifo.first;\n\t let md = MemDataF {data: data.data, last: data.last, first: firstReg, tag: 0};\n\t firstReg <= data.last;\n\t fifoToMp.enq(md);\n      end\n      dataCounter <= dataCounter + 1;\n   endrule\n\t \n   rule rl_locdone;\n      let loc <- toGet(mpEngine.locdone).get();\n      searchIndication.strstrLoc(pack(loc));\n   endrule\n`endif\n\n   interface NvmeRequest                request = nvme.request;\n   interface NvmeDriverRequest    driverRequest = nvme.driverRequest;\n   interface MemServerPortalRequest bramRequest = nvme.bramRequest;\n   interface NvmeTrace                    trace = nvme.trace;\n   interface NvmePins                      pins = nvme.pins;\n   interface StringSearchRequest searchRequest;\n      method Action setSearchString(Bit#(32) needleSglId, Bit#(32) mpNextSglId, Bit#(32) needleLen);\n`ifndef NVME_ACCELERATOR_INTERFACE\n\t mpEngine.clear();\n\t needleLenReg <= needleLen;\n   \n\t let burstLen = fromInteger(valueOf(DataBusWidth)/8);\n\t let mask = burstLen - 1;\n\t needleLen = (needleLen + mask) & ~mask;\n\t re.readServers[0].request.put(MemengineCmd {sglId: needleSglId, base: 0, burstLen: burstLen, len: needleLen, tag: 0});\n\t re.readServers[1].request.put(MemengineCmd {sglId: mpNextSglId, base: 0, burstLen: burstLen, len: needleLen*4, tag: 0});\n`endif\n      endmethod\n      method Action startSearch(Bit#(32) haystackLen);\n`ifndef NVME_ACCELERATOR_INTERFACE\n\t mpEngine.start(needleLenReg);\n\t dataLengthFifo.enq(haystackLen);\n`endif\n      endmethod\n   endinterface\n`ifdef TOP_SOURCES_PORTAL_CLOCK\n   interface Clock portalClockSource = nvme.portalClockSource;\n`endif\n   interface Vector dmaReadClient = append(nvme.dmaReadClient, vec(re.dmaClient));\n   interface Vector dmaWriteClient = nvme.dmaWriteClient;\nendmodule\n"
  },
  {
    "path": "tests/nvme_strstr/StringSearchIfc.bsv",
    "content": "// Copyright (c) 2016 Connectal Project\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\ninterface StringSearchRequest;\n   method Action setSearchString(Bit#(32) needleSglId, Bit#(32) mpNextSglId, Bit#(32) needleLen);\n   method Action startSearch(Bit#(32) searchLen);\nendinterface\n\ninterface StringSearchResponse;\n   method Action strstrLoc(Bit#(32) loc);\nendinterface\n"
  },
  {
    "path": "tests/nvme_strstr/fmc.json",
    "content": "{\n    \"pcie_refclk_p\": {\n\t\"FMC\": \"FMC_GBTCLK_P[00]\"\n    },\n    \"pcie_refclk_n\": {\n\t\"FMC\": \"FMC_GBTCLK_N[00]\"\n    },\n    \"RST_N_pcie_sys_reset_n\": {\n\t\"FMC\": \"FMC_LA_P[00]\",\n\t\"IOSTANDARD\": \"LVCMOS18\",\n\t\"PIO_DIRECTION\": \"OUTPUT\"\n    }\n}\n"
  },
  {
    "path": "tests/nvme_strstr/main.cpp",
    "content": "#include <stdio.h>\n//#include \"jsoncpp/json/json.h\"\n#include <map>\n#include <errno.h>\n#include <fcntl.h>\n#include <string>\n#include <sys/types.h>\n#include <sys/stat.h>\n#include <unistd.h>\n\n#include \"ConnectalProjectConfig.h\"\n\n#include \"nvme.h\"\n#include \"mp.h\"\n\nclass StringSearchResponse : public StringSearchResponseWrapper {\npublic:\n    virtual void strstrLoc ( const uint32_t pos ) {\n\tif (pos != (uint32_t)-1)\n\t    fprintf(stderr, \"string search at character pos=%d\\n\", pos);\n    }\n    StringSearchResponse(int id, PortalPoller *poller = 0) : StringSearchResponseWrapper(id, poller) {\n    }\n};\n\nint main(int argc, char * const *argv)\n{\n    Nvme nvme;\n    StringSearchRequestProxy search(IfcNames_StringSearchRequestS2H);\n    StringSearchResponse     searchResponse(IfcNames_StringSearchResponseH2S);\n\n    int opt;\n    const char *filename = NULL;\n    const char *needle = \"needle\";\n    int source_fd = -1;\n\n    int doidentify;\n    int dosearch = 0;\n    int dotrace = 0;\n    int dowrite = 0;\n    while ((opt = getopt(argc, argv, \"iw:s:t\")) != -1) {\n\tswitch (opt) {\n\tcase 'i':\n\t    doidentify = 1;\n\t    break;\n\tcase 's':\n\t    needle = optarg;\n\t    dosearch = 1;\n\t    break;\n\tcase 't':\n\t    dotrace = 1;\n\t    break;\n\tcase 'w':\n\t    filename = optarg;\n\t    dowrite = 1;\n\t    break;\n\t}\n    }\n\n    if (dowrite) {\n\tstruct stat statbuf;\n\tint rc = stat(filename, &statbuf);\n\tif (rc < 0) {\n\t    fprintf(stderr, \"%s:%d File %s does not exist %d:%s\\n\", __FILE__, __LINE__, filename, errno, strerror(errno));\n\t    return rc;\n\t}\n    }\n\n    sleep(1);\n\n    nvme.setup();\n\n    if (dosearch) {\n\tint needle_len = strlen(needle);\n\tint border[needle_len+1];\n\n\tcompute_borders(nvme.needleBuffer.buffer(), border, needle_len);\n\tcompute_MP_next(nvme.needleBuffer.buffer(), (struct MP *)nvme.mpNextBuffer.buffer(), needle_len);\n\tnvme.needleBuffer.cacheInvalidate(0, 1); // flush the whole thing\n\tnvme.mpNextBuffer.cacheInvalidate(0, 1); // flush the whole thing\n\n\t//FIXME: read the text from NVME storage\n\t//MP(needle, haystack, mpNext, needle_len, haystack_len, &sw_match_cnt);\n\n\t// the MPEngine will read in the needle and mpNext\n\tsearch.setSearchString(nvme.needleRef, nvme.mpNextRef, needle_len);\n    }\n\n    if (doidentify)\n\tnvme.identify();\n    nvme.getFeatures();\n    nvme.allocIOQueues(0);\n\n    fprintf(stderr, \"CSTS %08x\\n\", nvme.read32( 0x1c));\n    int startBlock = 100000; // base and extent of test file in SSD\n    int blocksPerRequest = 8; //12*BlocksPerRequest;\n    int numBlocks = 1*blocksPerRequest; // 55; //8177;\n    if (dosearch) {\n\tsearch.startSearch(numBlocks*512);\n    } else {\n      // if search is not running, then data read below will be discarded\n    }\n    if (dowrite) {\n\tstruct stat statbuf;\n\tint rc = stat(filename, &statbuf);\n\tif (rc < 0) {\n\t    fprintf(stderr, \"%s:%d File %s does not exist %d:%s\\n\", __FILE__, __LINE__, filename, errno, strerror(errno));\n\t    return rc;\n\t}\n\tnumBlocks = statbuf.st_blocks;\n\tnumBlocks -= (numBlocks % blocksPerRequest);\n\tfprintf(stderr, \"Writing %d blocks from file %s to flash at block %d\\n\", numBlocks, filename, startBlock);\n\tsource_fd = open(filename, O_RDONLY);\n    }\n\n    for (int block = 0; block < numBlocks; block += blocksPerRequest) {\n\tnvme_io_opcode opcode = (dowrite) ? nvme_write : nvme_read;\n\tfprintf(stderr, \"starting transfer dowrite=%d opcode=%d\\n\", dowrite, opcode);\n\tif (opcode == nvme_write) {\n\t    if (filename) {\n\t\tsize_t bytesToRead = 512*blocksPerRequest;\n\t\tchar *buffer = (char *)nvme.transferBuffer.buffer();\n\t\tdo {\n\t\t    size_t bytesRead = read(source_fd, buffer, bytesToRead);\n\t\t    if (bytesRead <= 0) {\n\t\t\tfprintf(stderr, \"%s:%d Requested %ld bytes, received %ld bytes errno=%d:%s\\n\",\n\t\t\t\t__FUNCTION__, __LINE__, bytesToRead, bytesRead, errno, strerror(errno));\n\t\t\tbreak;\n\t\t    }\n\t\t    bytesToRead -= bytesRead;\n\t\t    buffer += bytesRead;\n\t\t} while (bytesToRead);\n\t    } else {\n\t\t    int *buffer = (int *)nvme.transferBuffer.buffer();\n\t\tfor (int i = 0; i < numBlocks*512/4; i ++)\n\t\t    buffer[i] = i;\n\t    }\n\t}\n\tint sc = nvme.doIO(opcode, startBlock, blocksPerRequest, (opcode == nvme_read ? 2 : 1), dotrace);\n\tnvme.status();\n\tif (sc != 0)\n\t    break;\n\tstartBlock += blocksPerRequest;\n    }\n\n    nvme.dumpTrace();\n    //nvme.transferStats();\n    fprintf(stderr, \"CSTS %08x\\n\", nvme.read32( 0x1c));\n\n    return 0;\n}\n"
  },
  {
    "path": "tests/nvme_strstr/nfsume.json",
    "content": "{\n    \"pcie_refclk_p\": {\n\t\"FMC\": \"FMC_GBTCLK_P[00]\"\n    },\n    \"pcie_refclk_n\": {\n\t\"FMC\": \"FMC_GBTCLK_N[00]\"\n    },\n    \"RST_N_pcie_sys_reset_n\": {\n\t\"FMC\": \"FMC_LA_P[00]\",\n\t\"IOSTANDARD\": \"LVCMOS18\",\n\t\"PIO_DIRECTION\": \"OUTPUT\"\n    }\n}\n"
  },
  {
    "path": "tests/nvme_strstr/nvme.json",
    "content": "{\n    \"pcie_refclk_p\": {\n\t\"pcie\": \"sys_clk_p\"\n    },\n    \"pcie_refclk_n\": {\n\t\"pcie\": \"sys_clk_n\"\n    },\n    \"RST_N_pcie_sys_reset_n\": {\n\t\"pcie\": \"sys_reset_n\"\n    }\n}\n"
  },
  {
    "path": "tests/nvme_strstr/nvme.xdc",
    "content": "create_clock -name root_pci_refclk -period 10 [get_ports pcie_refclk_p]\n\nset_max_delay -from [get_clocks {userclk2}] -to   [get_clocks {userclk1}] 4.0 -datapath_only\nset_max_delay -to   [get_clocks {userclk2}] -from [get_clocks {userclk1}] 4.0 -datapath_only\n\nset_max_delay -from [get_clocks {userclk2}] -to   [get_clocks {clk_125mhz_mux_*}] 4.0 -datapath_only\nset_max_delay -to   [get_clocks {userclk2}] -from [get_clocks {clk_125mhz_mux_*}] 4.0 -datapath_only\n\nset_max_delay -from [get_clocks {userclk2}] -to   [get_clocks {clk_250mhz_mux_*}] 4.0 -datapath_only\nset_max_delay -to   [get_clocks {userclk2}] -from [get_clocks {clk_250mhz_mux_*}] 4.0 -datapath_only\n"
  },
  {
    "path": "tests/nvme_strstr/package100.tcl",
    "content": "#-----------------------------------------------------------\n# Vivado v2016.2 (64-bit)\n# SW Build 1577090 on Thu Jun  2 16:32:35 MDT 2016\n# IP Build 1577682 on Fri Jun  3 12:00:54 MDT 2016\n# Start of session at: Tue Aug 16 11:26:40 2016\n# Process ID: 16256\n# Current directory: /home/jamey/connectal/tests/nvme_strstr/miniitx100\n# Command line: vivado\n# Log file: /home/jamey/connectal/tests/nvme_strstr/miniitx100/vivado.log\n# Journal file: /home/jamey/connectal/tests/nvme_strstr/miniitx100/vivado.jou\n#-----------------------------------------------------------\nfile delete -force -- nvmecore\ncreate_project nvmecore nvmecore -part xc7z100ffg900-2\n#set_property board_part xilinx.com:zc706:part0:1.3 [current_project]\nadd_files ../miniitx100/verilog\nadd_files -norecurse ../cores/miniitx100/axi_pcie_rp/axi_pcie_rp.xci\nexport_ip_user_files -of_objects  [get_files  /home/jamey/connectal/tests/nvme_strstr/cores/miniitx100/axi_pcie_rp/axi_pcie_rp.xci] -force -quiet\nupdate_compile_order -fileset sources_1\nupdate_compile_order -fileset sim_1\nupdate_compile_order -fileset sources_1\nipx::package_project -root_dir . -vendor user.org -library user -taxonomy /UserIP\nset_property library {} [ipx::current_core]\nset_property vendor accelerated.tech [ipx::current_core]\nset_property library user [ipx::current_core]\nset_property name nvme100 [ipx::current_core]\nset_property display_name nvme100 [ipx::current_core]\nset_property description {nvme for avnet mini-itx 100} [ipx::current_core]\nipx::add_bus_interface ddr3 [ipx::current_core]\nset_property abstraction_type_vlnv xilinx.com:interface:ddrx_rtl:1.0 [ipx::get_bus_interfaces ddr3 -of_objects [ipx::current_core]]\nset_property bus_type_vlnv xilinx.com:interface:ddrx:1.0 [ipx::get_bus_interfaces ddr3 -of_objects [ipx::current_core]]\nset_property interface_mode master [ipx::get_bus_interfaces ddr3 -of_objects [ipx::current_core]]\nipx::add_port_map CS_N [ipx::get_bus_interfaces ddr3 -of_objects [ipx::current_core]]\nset_property physical_name DDR_CS_n [ipx::get_port_maps CS_N -of_objects [ipx::get_bus_interfaces ddr3 -of_objects [ipx::current_core]]]\nipx::add_port_map CK_P [ipx::get_bus_interfaces ddr3 -of_objects [ipx::current_core]]\nset_property physical_name DDR_Clk_p [ipx::get_port_maps CK_P -of_objects [ipx::get_bus_interfaces ddr3 -of_objects [ipx::current_core]]]\nipx::add_port_map CK_N [ipx::get_bus_interfaces ddr3 -of_objects [ipx::current_core]]\nset_property physical_name DDR_Clk_n [ipx::get_port_maps CK_N -of_objects [ipx::get_bus_interfaces ddr3 -of_objects [ipx::current_core]]]\nipx::add_port_map DM [ipx::get_bus_interfaces ddr3 -of_objects [ipx::current_core]]\nset_property physical_name DDR_DM [ipx::get_port_maps DM -of_objects [ipx::get_bus_interfaces ddr3 -of_objects [ipx::current_core]]]\nipx::add_port_map CAS_N [ipx::get_bus_interfaces ddr3 -of_objects [ipx::current_core]]\nset_property physical_name DDR_CAS_n [ipx::get_port_maps CAS_N -of_objects [ipx::get_bus_interfaces ddr3 -of_objects [ipx::current_core]]]\nipx::add_port_map DQ [ipx::get_bus_interfaces ddr3 -of_objects [ipx::current_core]]\nset_property physical_name DDR_DQ [ipx::get_port_maps DQ -of_objects [ipx::get_bus_interfaces ddr3 -of_objects [ipx::current_core]]]\nipx::add_port_map ADDR [ipx::get_bus_interfaces ddr3 -of_objects [ipx::current_core]]\nset_property physical_name DDR_Addr [ipx::get_port_maps ADDR -of_objects [ipx::get_bus_interfaces ddr3 -of_objects [ipx::current_core]]]\nipx::add_port_map RAS_N [ipx::get_bus_interfaces ddr3 -of_objects [ipx::current_core]]\nset_property physical_name DDR_RAS_n [ipx::get_port_maps RAS_N -of_objects [ipx::get_bus_interfaces ddr3 -of_objects [ipx::current_core]]]\nipx::add_port_map RESET_N [ipx::get_bus_interfaces ddr3 -of_objects [ipx::current_core]]\nset_property physical_name DDR_DRSTB [ipx::get_port_maps RESET_N -of_objects [ipx::get_bus_interfaces ddr3 -of_objects [ipx::current_core]]]\nipx::add_port_map DQS_N [ipx::get_bus_interfaces ddr3 -of_objects [ipx::current_core]]\nset_property physical_name DDR_DQS_n [ipx::get_port_maps DQS_N -of_objects [ipx::get_bus_interfaces ddr3 -of_objects [ipx::current_core]]]\nipx::add_port_map DQS_P [ipx::get_bus_interfaces ddr3 -of_objects [ipx::current_core]]\nset_property physical_name DDR_DQS_p [ipx::get_port_maps DQS_P -of_objects [ipx::get_bus_interfaces ddr3 -of_objects [ipx::current_core]]]\nipx::add_port_map WE_N [ipx::get_bus_interfaces ddr3 -of_objects [ipx::current_core]]\nset_property physical_name DDR_WEB [ipx::get_port_maps WE_N -of_objects [ipx::get_bus_interfaces ddr3 -of_objects [ipx::current_core]]]\nipx::add_port_map CKE [ipx::get_bus_interfaces ddr3 -of_objects [ipx::current_core]]\nset_property physical_name DDR_CKE [ipx::get_port_maps CKE -of_objects [ipx::get_bus_interfaces ddr3 -of_objects [ipx::current_core]]]\nipx::add_port_map ODT [ipx::get_bus_interfaces ddr3 -of_objects [ipx::current_core]]\nset_property physical_name DDR_ODT [ipx::get_port_maps ODT -of_objects [ipx::get_bus_interfaces ddr3 -of_objects [ipx::current_core]]]\nipx::add_port_map BA [ipx::get_bus_interfaces ddr3 -of_objects [ipx::current_core]]\nset_property physical_name DDR_BankAddr [ipx::get_port_maps BA -of_objects [ipx::get_bus_interfaces ddr3 -of_objects [ipx::current_core]]]\nipx::add_bus_interface pcie_mgt [ipx::current_core]\nset_property abstraction_type_vlnv xilinx.com:interface:pcie_7x_mgt_rtl:1.0 [ipx::get_bus_interfaces pcie_mgt -of_objects [ipx::current_core]]\nset_property bus_type_vlnv xilinx.com:interface:pcie_7x_mgt:1.0 [ipx::get_bus_interfaces pcie_mgt -of_objects [ipx::current_core]]\nset_property interface_mode master [ipx::get_bus_interfaces pcie_mgt -of_objects [ipx::current_core]]\nipx::add_port_map rxn [ipx::get_bus_interfaces pcie_mgt -of_objects [ipx::current_core]]\nset_property physical_name pcie_exp_rxn_v [ipx::get_port_maps rxn -of_objects [ipx::get_bus_interfaces pcie_mgt -of_objects [ipx::current_core]]]\nipx::add_port_map txn [ipx::get_bus_interfaces pcie_mgt -of_objects [ipx::current_core]]\nset_property physical_name pcie_exp_txn [ipx::get_port_maps txn -of_objects [ipx::get_bus_interfaces pcie_mgt -of_objects [ipx::current_core]]]\nipx::add_port_map rxp [ipx::get_bus_interfaces pcie_mgt -of_objects [ipx::current_core]]\nset_property physical_name pcie_exp_rxp_v [ipx::get_port_maps rxp -of_objects [ipx::get_bus_interfaces pcie_mgt -of_objects [ipx::current_core]]]\nipx::add_port_map txp [ipx::get_bus_interfaces pcie_mgt -of_objects [ipx::current_core]]\nset_property physical_name pcie_exp_txp [ipx::get_port_maps txp -of_objects [ipx::get_bus_interfaces pcie_mgt -of_objects [ipx::current_core]]]\nipx::add_bus_interface pcie_refclk [ipx::current_core]\nset_property abstraction_type_vlnv xilinx.com:interface:diff_clock_rtl:1.0 [ipx::get_bus_interfaces pcie_refclk -of_objects [ipx::current_core]]\nset_property bus_type_vlnv xilinx.com:interface:diff_clock:1.0 [ipx::get_bus_interfaces pcie_refclk -of_objects [ipx::current_core]]\nset_property interface_mode master [ipx::get_bus_interfaces pcie_refclk -of_objects [ipx::current_core]]\nset_property interface_mode slave [ipx::get_bus_interfaces pcie_refclk -of_objects [ipx::current_core]]\nipx::add_port_map CLK_P [ipx::get_bus_interfaces pcie_refclk -of_objects [ipx::current_core]]\nset_property physical_name pcie_refclk_p [ipx::get_port_maps CLK_P -of_objects [ipx::get_bus_interfaces pcie_refclk -of_objects [ipx::current_core]]]\nipx::add_port_map CLK_N [ipx::get_bus_interfaces pcie_refclk -of_objects [ipx::current_core]]\nset_property physical_name pcie_refclk_n [ipx::get_port_maps CLK_N -of_objects [ipx::get_bus_interfaces pcie_refclk -of_objects [ipx::current_core]]]\nipx::remove_bus_interface CLK_deleteme_unused_clock [ipx::current_core]\nipx::remove_bus_interface CLK_GATE_deleteme_unused_clock [ipx::current_core]\nipx::remove_port CLK_deleteme_unused_clock [ipx::current_core]\nipx::remove_port CLK_GATE_deleteme_unused_clock [ipx::current_core]\nipx::remove_port CLK_deleteme_unused_clock_0 [ipx::current_core]\nipx::remove_port CLK_GATE_deleteme_unused_clock_0 [ipx::current_core]\nipx::remove_port CLK_deleteme_unused_clock_1 [ipx::current_core]\nipx::remove_port CLK_GATE_deleteme_unused_clock_1 [ipx::current_core]\nipx::remove_port CLK_deleteme_unused_clock_2 [ipx::current_core]\nipx::remove_port CLK_GATE_deleteme_unused_clock_2 [ipx::current_core]\nipx::remove_port CLK_deleteme_unused_clock_3 [ipx::current_core]\nipx::remove_port CLK_GATE_deleteme_unused_clock_3 [ipx::current_core]\nipx::remove_port RST_N_deleteme_unused_reset_0 [ipx::current_core]\nipx::remove_port RST_N_deleteme_unused_reset_1 [ipx::current_core]\nipx::remove_port RST_N_deleteme_unused_reset_2 [ipx::current_core]\nipx::remove_port RST_N_deleteme_unused_reset_3 [ipx::current_core]\nipx::associate_bus_interfaces -busif ddr3 -clock DDR_Clk_p [ipx::current_core]\nipx::associate_bus_interfaces -busif ddr3 -clock DDR_Clk_n [ipx::current_core]\nipx::remove_bus_interface CLK [ipx::current_core]\nipx::remove_port CLK [ipx::current_core]\nipx::remove_port RST_N [ipx::current_core]\nipx::add_bus_interface pcie_sys_reset_n [ipx::current_core]\nset_property abstraction_type_vlnv xilinx.com:signal:reset_rtl:1.0 [ipx::get_bus_interfaces pcie_sys_reset_n -of_objects [ipx::current_core]]\nset_property bus_type_vlnv xilinx.com:signal:reset:1.0 [ipx::get_bus_interfaces pcie_sys_reset_n -of_objects [ipx::current_core]]\nset_property interface_mode master [ipx::get_bus_interfaces pcie_sys_reset_n -of_objects [ipx::current_core]]\nset_property interface_mode slave [ipx::get_bus_interfaces pcie_sys_reset_n -of_objects [ipx::current_core]]\nset_property interface_mode master [ipx::get_bus_interfaces pcie_sys_reset_n -of_objects [ipx::current_core]]\nipx::add_port_map RST [ipx::get_bus_interfaces pcie_sys_reset_n -of_objects [ipx::current_core]]\nset_property physical_name RST_N_pcie_sys_reset_n [ipx::get_port_maps RST -of_objects [ipx::get_bus_interfaces pcie_sys_reset_n -of_objects [ipx::current_core]]]\nipx::infer_bus_interface FIXED_IO_ddr_vrn xilinx.com:signal:data_rtl:1.0 [ipx::current_core]\nipx::infer_bus_interface {FIXED_IO_ddr_vrp MIO FIXED_IO_ps_porb FIXED_IO_ps_srstb} xilinx.com:signal:data_rtl:1.0 [ipx::current_core]\nipx::infer_bus_interface FIXED_IO_ddr_vrp xilinx.com:signal:data_rtl:1.0 [ipx::current_core]\nipx::infer_bus_interface FIXED_IO_ps_porb xilinx.com:signal:data_rtl:1.0 [ipx::current_core]\nipx::infer_bus_interface FIXED_IO_ps_srstb xilinx.com:signal:data_rtl:1.0 [ipx::current_core]\nipx::infer_bus_interface MIO xilinx.com:signal:data_rtl:1.0 [ipx::current_core]\nset_property core_revision 2 [ipx::current_core]\nipx::create_xgui_files [ipx::current_core]\nipx::update_checksums [ipx::current_core]\nipx::save_core [ipx::current_core]\nset_property  ip_repo_paths  /home/jamey/connectal/tests/nvme_strstr [current_project]\nupdate_ip_catalog\nipx::check_integrity -quiet [ipx::current_core]\nipx::archive_core /home/jamey/connectal/tests/nvme_strstr/accelerated.tech_user_nvme_strstr_1.0.zip [ipx::current_core]\nset_property core_revision 3 [ipx::current_core]\nipx::create_xgui_files [ipx::current_core]\nipx::update_checksums [ipx::current_core]\nipx::save_core [ipx::current_core]\nupdate_ip_catalog -rebuild -repo_path /home/jamey/connectal/tests/nvme_strstr\nipx::check_integrity -quiet [ipx::current_core]\nipx::archive_core /home/jamey/connectal/tests/nvme_strstr/accelerated.tech_user_nvme_strstr_1.0.zip [ipx::current_core]\nlaunch_runs synth_1 -jobs 12\nwait_on_run synth_1\nipx::remove_bus_interface FIXED_IO_ddr_vrn [ipx::current_core]\nipx::remove_bus_interface FIXED_IO_ddr_vrp [ipx::current_core]\nipx::remove_bus_interface FIXED_IO_ps_porb [ipx::current_core]\nipx::remove_bus_interface FIXED_IO_ps_srstb [ipx::current_core]\nipx::remove_bus_interface MIO [ipx::current_core]\nipx::remove_bus_interface FIXED_IO_ps_clk [ipx::current_core]\nipx::create_abstraction_definition xilinx zynq7 FIXED_IO_rtl 1.0\nipx::create_bus_definition xilinx zynq7 FIXED_IO 1.0\nset_property xml_file_name /home/jamey/connectal/tests/nvme_strstr/ip_repo/FIXED_IO_rtl.xml [ipx::current_busabs]\nset_property xml_file_name /home/jamey/connectal/tests/nvme_strstr/ip_repo/FIXED_IO.xml [ipx::current_busdef]\nset_property bus_type_vlnv xilinx:zynq7:FIXED_IO:1.0 [ipx::current_busabs]\nipx::save_abstraction_definition [ipx::current_busabs]\nipx::save_bus_definition [ipx::current_busdef]\nipx::add_bus_abstraction_port FIXED_IO_ddr_vrn [ipx::current_busabs]\nipx::add_bus_abstraction_port FIXED_IO_ddr_vrp [ipx::current_busabs]\nipx::add_bus_abstraction_port MIO [ipx::current_busabs]\nipx::add_bus_abstraction_port FIXED_IO_ps_clk [ipx::current_busabs]\nipx::add_bus_abstraction_port FIXED_IO_ps_porb [ipx::current_busabs]\nipx::add_bus_abstraction_port FIXED_IO_ps_srstb [ipx::current_busabs]\nipx::save_bus_definition [ipx::current_busdef]\nipx::save_abstraction_definition [ipx::current_busabs]\nupdate_ip_catalog -rebuild\nupdate_ip_catalog -rebuild -repo_path /home/jamey/connectal/tests/nvme_strstr\nipx::infer_bus_interface {FIXED_IO_ddr_vrn FIXED_IO_ddr_vrp MIO FIXED_IO_ps_clk FIXED_IO_ps_porb FIXED_IO_ps_srstb} xilinx:zynq7:FIXED_IO:1.0 [ipx::current_core]\nset_property name FIXED_IO [ipx::get_bus_interfaces FIXED_IO_1 -of_objects [ipx::current_core]]\nipx::remove_bus_interface FIXED_IO_ddr_vrn [ipx::current_core]\nipx::remove_bus_interface FIXED_IO_ps_clk [ipx::current_core]\nipx::create_abstraction_definition accelerated.tech zynq7 FIXED_IO_rtl 1.0\nipx::create_bus_definition accelerated.tech zynq7 FIXED_IO 1.0\nset_property xml_file_name /home/jamey/connectal/tests/nvme_strstr/ip_repo/FIXED_IO_rtl.xml [ipx::current_busabs]\nset_property xml_file_name /home/jamey/connectal/tests/nvme_strstr/ip_repo/FIXED_IO.xml [ipx::current_busdef]\nset_property bus_type_vlnv accelerated.tech:zynq7:FIXED_IO:1.0 [ipx::current_busabs]\nipx::save_abstraction_definition [ipx::current_busabs]\nipx::save_bus_definition [ipx::current_busdef]\nset_property  ip_repo_paths  /home/jamey/connectal/tests/nvme_strstr/ip_repo [current_project]\nipx::add_bus_abstraction_port FIXED_IO_ddr_vrn [ipx::current_busabs]\nipx::add_bus_abstraction_port FIXED_IO_ddr_vrp [ipx::current_busabs]\nipx::add_bus_abstraction_port MIO [ipx::current_busabs]\nipx::add_bus_abstraction_port FIXED_IO_ps_clk [ipx::current_busabs]\nipx::add_bus_abstraction_port FIXED_IO_ps_porb [ipx::current_busabs]\nipx::add_bus_abstraction_port FIXED_IO_ps_srstb [ipx::current_busabs]\nipx::save_bus_definition [ipx::current_busdef]\nipx::save_abstraction_definition [ipx::current_busabs]\nupdate_ip_catalog -rebuild\nupdate_ip_catalog\nipx::infer_bus_interface {FIXED_IO_ddr_vrn FIXED_IO_ddr_vrp MIO FIXED_IO_ps_clk FIXED_IO_ps_porb FIXED_IO_ps_srstb} accelerated.tech:zynq7:FIXED_IO:1.0 [ipx::current_core]\nset_property name FIXED_IO [ipx::get_bus_interfaces FIXED_IO_1 -of_objects [ipx::current_core]]\nset_property core_revision 2 [ipx::current_core]\nipx::create_xgui_files [ipx::current_core]\nipx::update_checksums [ipx::current_core]\nipx::save_core [ipx::current_core]\nset_property  ip_repo_paths  {/home/jamey/connectal/tests/nvme_strstr /home/jamey/connectal/tests/nvme_strstr/ip_repo} [current_project]\nupdate_ip_catalog\nipx::check_integrity -quiet [ipx::current_core]\nipx::archive_core /home/jamey/connectal/tests/nvme_strstr/accelerated.tech_user_nvme100_1.0.zip [ipx::current_core]\nupdate_compile_order -fileset sources_1\nipx::infer_bus_interface FIXED_IO_ddr_vrp xilinx.com:signal:data_rtl:1.0 [ipx::current_core]\nipx::infer_bus_interface FIXED_IO_ps_porb xilinx.com:signal:data_rtl:1.0 [ipx::current_core]\nipx::infer_bus_interface FIXED_IO_ps_srstb xilinx.com:signal:data_rtl:1.0 [ipx::current_core]\nipx::infer_bus_interface MIO xilinx.com:signal:video_frame_sync_rtl:1.0 [ipx::current_core]\nipx::add_bus_interface accel_request [ipx::current_core]\nset_property abstraction_type_vlnv xilinx.com:interface:axis_rtl:1.0 [ipx::get_bus_interfaces accel_request -of_objects [ipx::current_core]]\nset_property bus_type_vlnv xilinx.com:interface:axis:1.0 [ipx::get_bus_interfaces accel_request -of_objects [ipx::current_core]]\nipx::add_port_map TDATA [ipx::get_bus_interfaces accel_request -of_objects [ipx::current_core]]\nset_property physical_name accel_request_tdata_v [ipx::get_port_maps TDATA -of_objects [ipx::get_bus_interfaces accel_request -of_objects [ipx::current_core]]]\nipx::add_port_map TLAST [ipx::get_bus_interfaces accel_request -of_objects [ipx::current_core]]\nset_property physical_name accel_request_tlast_v [ipx::get_port_maps TLAST -of_objects [ipx::get_bus_interfaces accel_request -of_objects [ipx::current_core]]]\nipx::add_port_map TVALID [ipx::get_bus_interfaces accel_request -of_objects [ipx::current_core]]\nset_property physical_name accel_request_tvalid_v [ipx::get_port_maps TVALID -of_objects [ipx::get_bus_interfaces accel_request -of_objects [ipx::current_core]]]\nipx::add_port_map TKEEP [ipx::get_bus_interfaces accel_request -of_objects [ipx::current_core]]\nset_property physical_name accel_request_tkeep_v [ipx::get_port_maps TKEEP -of_objects [ipx::get_bus_interfaces accel_request -of_objects [ipx::current_core]]]\nipx::add_port_map TREADY [ipx::get_bus_interfaces accel_request -of_objects [ipx::current_core]]\nset_property physical_name accel_request_tready [ipx::get_port_maps TREADY -of_objects [ipx::get_bus_interfaces accel_request -of_objects [ipx::current_core]]]\nipx::infer_bus_interface {accel_msgIn_tdata_v accel_msgIn_tkeep_v accel_msgIn_tlast_v accel_msgIn_tready accel_msgIn_tvalid_v} xilinx.com:interface:axis_rtl:1.0 [ipx::current_core]\nipx::infer_bus_interface {accel_dataIn_tdata_v accel_dataIn_tkeep_v accel_dataIn_tlast_v accel_dataIn_tready accel_dataIn_tvalid_v} xilinx.com:interface:axis_rtl:1.0 [ipx::current_core]\nset_property name MIO [ipx::get_bus_interfaces video_frame_sync_1 -of_objects [ipx::current_core]]\nipx::add_port_map TREADY [ipx::get_bus_interfaces accel_msgOut -of_objects [ipx::current_core]]\nset_property physical_name accel_msgOut_tready_v [ipx::get_port_maps TREADY -of_objects [ipx::get_bus_interfaces accel_msgOut -of_objects [ipx::current_core]]]\nipx::add_port_map TREADY [ipx::get_bus_interfaces accel_dataOut -of_objects [ipx::current_core]]\nset_property physical_name accel_dataOut_tready_v [ipx::get_port_maps TREADY -of_objects [ipx::get_bus_interfaces accel_dataOut -of_objects [ipx::current_core]]]\nipx::add_port_map TREADY [ipx::get_bus_interfaces accel_response -of_objects [ipx::current_core]]\nset_property physical_name accel_response_tready_v [ipx::get_port_maps TREADY -of_objects [ipx::get_bus_interfaces accel_response -of_objects [ipx::current_core]]]\nset_property core_revision 3 [ipx::current_core]\nipx::create_xgui_files [ipx::current_core]\nipx::update_checksums [ipx::current_core]\nipx::save_core [ipx::current_core]\nset_property  ip_repo_paths  /home/jamey/connectal.bisect/tests/nvme_strstr/miniitx100 [current_project]\nupdate_ip_catalog\n"
  },
  {
    "path": "tests/nvme_strstr/synth-ip.tcl",
    "content": "source \"board.tcl\"\n\nif {$boardname == {nfsume}} {\n    set partname {xc7vx690tffg1761-3}\n    set databuswidth 128\n    set pcie_blk_locn {X0Y0}\n}\nif {$boardname == {vc709}} {\n    set partname {xc7vx690tffg1761-2}\n    set databuswidth 128\n    set pcie_blk_locn {X0Y2}\n}\nif {$boardname == {miniitx100}} {\n    set partname {xc7z100ffg900-2}\n    set databuswidth 128\n}\nif {$boardname == {zc706}} {\n    set partname {xc7z045ffg900-2}\n    set databuswidth 128\n}\nputs \"partname=$partname\"\nputs \"databuswidth=$databuswidth\"\n\ncreate_project -name local_synthesized_ip -in_memory -part $partname\nif {$boardname == {nfsume}} {\n    set_property board_part xilinx.com:vc709:part0:1.0 [current_project]\n}\nproc fpgamake_ipcore {core_name core_version ip_name params} {\n    global ipdir boardname\n\n    set generate_ip 0\n\n    if [file exists $ipdir/$boardname/$ip_name/$ip_name.xci] {\n    } else {\n\tputs \"no xci file $ip_name.xci\"\n\tset generate_ip 1\n    }\n    if [file exists $ipdir/$boardname/$ip_name/vivadoversion.txt] {\n\tgets [open $ipdir/$boardname/$ip_name/vivadoversion.txt r] generated_version\n\tset current_version [version -short]\n\tputs \"core was generated by vivado $generated_version, currently running vivado $current_version\"\n\tif {$current_version != $generated_version} {\n\t    puts \"vivado version does not match\"\n\t    set generate_ip 1\n\t}\n    } else {\n\tputs \"no vivado version recorded\"\n\tset generate_ip 1\n    }\n\n    ## check requested core version and parameters\n    if [file exists $ipdir/$boardname/$ip_name/coreversion.txt] {\n\tgets [open $ipdir/$boardname/$ip_name/coreversion.txt r] generated_version\n\tset current_version \"$core_name $core_version $params\"\n\tputs \"Core generated: $generated_version\"\n\tputs \"Core requested: $current_version\"\n\tif {$current_version != $generated_version} {\n\t    puts \"core version or params does not match\"\n\t    set generate_ip 1\n\t}\n    } else {\n\tputs \"no core version recorded\"\n\tset generate_ip 1\n    }\n\n    if $generate_ip {\n\tfile delete -force $ipdir/$boardname/$ip_name\n\tfile mkdir $ipdir/$boardname\n\tcreate_ip -name $core_name -version $core_version -vendor xilinx.com -library ip -module_name $ip_name -dir $ipdir/$boardname\n\tif [llength $params] {\n\t    set_property -dict $params [get_ips $ip_name]\n\t}\n        report_property -file $ipdir/$boardname/$ip_name.properties.log [get_ips $ip_name]\n\t\n\tgenerate_target all [get_files $ipdir/$boardname/$ip_name/$ip_name.xci]\n\n\tset versionfd [open $ipdir/$boardname/$ip_name/vivadoversion.txt w]\n\tputs $versionfd [version -short]\n\tclose $versionfd\n\n\tset corefd [open $ipdir/$boardname/$ip_name/coreversion.txt w]\n\tputs $corefd \"$core_name $core_version $params\"\n\tclose $corefd\n    } else {\n\tread_ip $ipdir/$boardname/$ip_name/$ip_name.xci\n    }\n    if [file exists $ipdir/$boardname/$ip_name/$ip_name.dcp] {\n    } else {\n\tsynth_ip [get_ips $ip_name]\n    }\n}\n\nif {$partname != {xc7vx690tffg1761-2} && $partname != {xc7vx690tffg1761-3}} {\n    fpgamake_ipcore axi_pcie 2.8 axi_pcie_rp [list \\\n\t\t\t\t\t\t  CONFIG.AXIBAR2PCIEBAR_0 {0x00000000} \\\n\t\t\t\t\t\t  CONFIG.AXIBAR_0 {0x00000000} \\\n\t\t\t\t\t\t  CONFIG.AXIBAR_HIGHADDR_0 {0xfFFFFFFF} \\\n\t\t\t\t\t\t  CONFIG.BAR0_SCALE {Gigabytes} \\\n\t\t\t\t\t\t  CONFIG.BAR0_SIZE {1} \\\n\t\t\t\t\t\t  CONFIG.BASEADDR {0x00000000} \\\n\t\t\t\t\t\t  CONFIG.BASE_CLASS_MENU {Bridge_device} \\\n\t\t\t\t\t\t  CONFIG.DEVICE_ID {0x7022} \\\n\t\t\t\t\t\t  CONFIG.HIGHADDR {0xffffffff} \\\n\t\t\t\t\t\t  CONFIG.INCLUDE_BAROFFSET_REG {false} \\\n\t\t\t\t\t\t  CONFIG.INCLUDE_RC {Root_Port_of_PCI_Express_Root_Complex} \\\n\t\t\t\t\t\t  CONFIG.MAX_LINK_SPEED {5.0_GT/s} \\\n\t\t\t\t\t\t  CONFIG.M_AXI_DATA_WIDTH {128} \\\n\t\t\t\t\t\t  CONFIG.NO_OF_LANES {X4} \\\n\t\t\t\t\t\t  CONFIG.NUM_MSI_REQ {5} \\\n\t\t\t\t\t\t  CONFIG.SUB_CLASS_INTERFACE_MENU {InfiniBand_to_PCI_host_bridge} \\\n\t\t\t\t\t\t  CONFIG.S_AXI_DATA_WIDTH {128} \\\n\t\t\t\t\t\t  CONFIG.S_AXI_SUPPORTS_NARROW_BURST {true} \\\n\t\t\t\t\t\t  CONFIG.XLNX_REF_BOARD {ZC706} \\\n\t\t\t\t\t\t  CONFIG.shared_logic_in_core {true} \\\n\t\t\t\t\t\t ]\n} else {\n    fpgamake_ipcore axi_pcie3 2.1 axi_pcie_rp [list \\\n\t\t\t\t\t           CONFIG.pcie_blk_locn $pcie_blk_locn \\\n\t\t\t\t\t\t   CONFIG.axi_data_width {128_bit} \\\n\t\t\t\t\t\t   CONFIG.axibar_highaddr_0 {0xffffffffffffffff} \\\n\t\t\t\t\t\t   CONFIG.axisten_freq {125} \\\n\t\t\t\t\t\t   CONFIG.dedicate_perst {false} \\\n\t\t\t\t\t\t   CONFIG.device_port_type {Root_Port_of_PCI_Express_Root_Complex} \\\n\t\t\t\t\t\t   CONFIG.mode_selection {Advanced} \\\n\t\t\t\t\t\t   CONFIG.pcie_blk_locn $pcie_blk_locn \\\n\t\t\t\t\t\t   CONFIG.pf0_bar0_scale {Gigabytes} \\\n\t\t\t\t\t\t   CONFIG.pf0_bar0_size {2} \\\n\t\t\t\t\t\t   CONFIG.pf0_base_class_menu {Bridge_device} \\\n\t\t\t\t\t\t   CONFIG.pf0_class_code {060700} \\\n\t\t\t\t\t\t   CONFIG.pf0_class_code_base {06} \\\n\t\t\t\t\t\t   CONFIG.pf0_class_code_sub {07} \\\n\t\t\t\t\t\t   CONFIG.pf0_device_id {7131} \\\n\t\t\t\t\t\t   CONFIG.pf0_link_status_slot_clock_config {true} \\\n\t\t\t\t\t\t   CONFIG.pf0_sub_class_interface_menu {CardBus_bridge} \\\n\t\t\t\t\t\t   CONFIG.pl_link_cap_max_link_speed {5.0_GT/s} \\\n\t\t\t\t\t\t   CONFIG.pl_link_cap_max_link_width {X4} \\\n\t\t\t\t\t\t   CONFIG.plltype {QPLL1} \\\n\t\t\t\t\t\t   CONFIG.s_axi_id_width {4} \\\n\t\t\t\t\t\t  ]\n}\n\n"
  },
  {
    "path": "tests/nvme_test/Makefile",
    "content": "CONNECTALDIR?=../..\n\nS2H_INTERFACES = NvmeRequest:NvmeTest.request NvmeDriverRequest:NvmeTest.driverRequest MemServerPortalRequest:NvmeTest.bramRequest\nH2S_INTERFACES = NvmeTest:NvmeIndication,NvmeDriverIndication,NvmeTrace,MemServerPortalIndication\n\nMEM_READ_INTERFACES = lNvmeTest.dmaReadClient\nMEM_WRITE_INTERFACES = lNvmeTest.dmaWriteClient\n\nBSVPATH = $(CONNECTALDIR)/lib/strstr/bsv\nBSVFILES = $(CONNECTALDIR)/lib/nvme/bsv/NvmeIfc.bsv $(CONNECTALDIR)/bsv/ConnectalConfig.bsv\nCPPFILES += $(CONNECTALDIR)/lib/nvme/cpp/nvme.cpp main.cpp\nCPPFILES += $(CONNECTALDIR)/cpp/DmaBuffer.cpp\n\nCONNECTALFLAGS += -I$(CONNECTALDIR)/lib/nvme/cpp\n\nCONNECTALFLAGS += -DTRACE_PORTAL\n\nifeq ($(BOARD),miniitx100)\nPINOUT_FILE += nvme.json\nCONNECTALFLAGS += -D PcieDataBusWidth=128\nCONNECTALFLAGS += -D USE_ACP\nCONNECTALFLAGS += -D TOP_SOURCES_PORTAL_CLOCK\nCONNECTALFLAGS +=  --mainclockperiod=8\nelse\nifeq ($(BOARD),kc705g2)\nCONNECTALFLAGS += --pin-binding FMC:fmc1\nendif\nifeq ($(BOARD),nfsume)\nCONNECTALFLAGS += --implconstraint=nfsume.xdc\nendif\n#PINOUT_FILE += fmc.json\nCONNECTALFLAGS += -D PcieDataBusWidth=128\nendif\nCONNECTALFLAGS += -D BlocksPerRequest=8\nPIN_TYPE = NvmePins\nPIN_TYPE_INCLUDE = NvmePins\nAUTOTOP = --interface pins:NvmeTest.pins\n\nAUTOTOP += --portalclock=lNvmeTest.portalClockSource\nCONNECTALFLAGS += --cxxflags=-std=c++11\nCONNECTALFLAGS += --stl=c++_static\n\nCONNECTALFLAGS += -I $(CONNECTALDIR)/lib/strstr/cpp\nCONNECTALFLAGS += --bsvpath=../spikehw\nCONNECTALFLAGS += --xci=$(IPDIR)/$(BOARD)/axi_pcie_rp/axi_pcie_rp.xci\nCONNECTALFLAGS += -D GET_PUT_WITH_CLOCKS_USE_XILINX_FIFO\nCONNECTALFLAGS += --xci=$(IPDIR)/$(BOARD)/dual_clock_axis_fifo_32x8/dual_clock_axis_fifo_32x8.xci\nCONNECTALFLAGS += --implconstraint=nvme.xdc\n\n#CONNECTALFLAGS += -DNVME_ACCELERATOR_INTERFACE=1\n\ninclude $(CONNECTALDIR)/Makefile.connectal\n"
  },
  {
    "path": "tests/nvme_test/NvmeTest.bsv",
    "content": "// Copyright (c) 2016 Connectal Project\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\n`include \"ConnectalProjectConfig.bsv\"\nimport Arbitrate::*;\nimport BRAM::*;\nimport BuildVector::*;\nimport Clocks::*;\nimport Connectable::*;\nimport FIFOF::*;\nimport Gearbox::*;\nimport GetPut::*;\nimport Probe::*;\nimport StmtFSM::*;\nimport Vector::*;\n\nimport AddressGenerator::*;\nimport AxiBits::*;\nimport AxiStream::*;\nimport ConnectalClocks::*;\nimport ConnectalConfig::*;\nimport DefaultValue::*;\nimport GearboxGetPut::*;\nimport HostInterface::*;\nimport MemReadEngine::*;\nimport ConnectalMemTypes::*;\nimport PhysMemSlaveFromBram::*;\nimport Pipe::*;\nimport TraceMemClient::*;\nimport XilinxCells::*;\nimport MPEngine::*;\n\nimport Nvme::*;\nimport NvmeIfc::*;\nimport NvmePins::*;\n\ninterface NvmeTest;\n   interface NvmeRequest request;\n   interface NvmeDriverRequest driverRequest;\n   interface MemServerPortalRequest bramRequest;\n   interface NvmeTrace trace;\n   interface NvmePins pins;\n   interface Vector#(1, MemReadClient#(DataBusWidth)) dmaReadClient;\n   interface Vector#(1, MemWriteClient#(DataBusWidth)) dmaWriteClient;\n`ifdef TOP_SOURCES_PORTAL_CLOCK\n   interface Clock portalClockSource;\n`endif\nendinterface\n\ntypedef enum {\n   Loopback,\n   Needle,\n   MpNext,\n   Clear,\n   Opcode,\n   StartBlock,\n   NumBlocks,\n   Start\n   } MsgFromSoftwareTag deriving (Bits,Eq);\n\ntypedef struct {\n   MsgFromSoftwareTag tag;\n   Bit#(24)  data;\n   } MsgFromSoftware deriving (Bits);\n\ntypedef enum {\n   Loopback=1,\n   LocDone=2,\n   TransferDone=3\n   } MsgToSoftwareTag deriving (Bits,Eq);\n\ntypedef struct {\n   MsgToSoftwareTag tag;\n   Bit#(24)  data;\n   } MsgToSoftware deriving (Bits);\n\n\nmodule mkNvmeTest#(NvmeIndication ind, NvmeDriverIndication driverInd, NvmeTrace trace, MemServerPortalIndication bramIndication)(NvmeTest);\n\n   let nvme <- mkNvme(ind, driverInd, trace, bramIndication);\n\n`ifndef NVME_ACCELERATOR_INTERFACE\n   Reg#(Bit#(32))                       dataCounter <- mkReg(0);\n   FIFOF#(Bit#(32))                  dataLengthFifo <- mkFIFOF();\n   FIFOF#(MemDataF#(PcieDataBusWidth))     fifoToMp <- mkFIFOF();\n   let                                 needleLenReg <- mkReg(0);\n\n   Reg#(Bool) firstReg <- mkReg(True);\n   rule rl_count_data_to_mp;\n      let data <- toGet(nvme.dataFromNvme).get();\n      if (dataLengthFifo.notEmpty()) begin\n\t data.last = (dataCounter+fromInteger(valueOf(PcieDataBusWidth)/8)) >= dataLengthFifo.first;\n\t let md = MemDataF {data: data.data, last: data.last, first: firstReg, tag: 0};\n\t firstReg <= data.last;\n\t fifoToMp.enq(md);\n      end\n      dataCounter <= dataCounter + 1;\n   endrule\n`endif\n\n   \n   interface NvmeRequest                request = nvme.request;\n   interface NvmeDriverRequest    driverRequest = nvme.driverRequest;\n   interface MemServerPortalRequest bramRequest = nvme.bramRequest;\n   interface NvmeTrace                    trace = nvme.trace;\n   interface NvmePins                      pins = nvme.pins;\n`ifdef TOP_SOURCES_PORTAL_CLOCK\n   interface Clock portalClockSource = nvme.portalClockSource;\n`endif\n   interface Vector dmaReadClient = nvme.dmaReadClient;\n   interface Vector dmaWriteClient = nvme.dmaWriteClient;\nendmodule\n"
  },
  {
    "path": "tests/nvme_test/fmc.json",
    "content": "{\n    \"pcie_refclk_p\": {\n\t\"FMC\": \"FMC_GBTCLK_P[00]\"\n    },\n    \"pcie_refclk_n\": {\n\t\"FMC\": \"FMC_GBTCLK_N[00]\"\n    },\n    \"RST_N_pcie_sys_reset_n\": {\n\t\"FMC\": \"FMC_LA_P[00]\",\n\t\"IOSTANDARD\": \"LVCMOS18\",\n\t\"PIO_DIRECTION\": \"OUTPUT\"\n    }\n}\n"
  },
  {
    "path": "tests/nvme_test/impl.tcl",
    "content": "set dbgs [get_nets -hierarchical -filter {MARK_DEBUG}]\nif {[llength $dbgs] > 0} {\n    set_property mark_debug false $dbgs\n}\n\nopt_design\nplace_design\nphys_opt_design\nroute_design\nwrite_bitstream -force debug.bit\nwrite_debug_probes -force debug.ltx\nreport_timing_summary -file debug_timing_summary.txt\n"
  },
  {
    "path": "tests/nvme_test/main.cpp",
    "content": "#include <stdio.h>\n//#include \"jsoncpp/json/json.h\"\n#include <map>\n#include <errno.h>\n#include <fcntl.h>\n#include <string>\n#include <sys/types.h>\n#include <sys/stat.h>\n#include <unistd.h>\n\n#include \"ConnectalProjectConfig.h\"\n\n#include \"nvme.h\"\n\nint main(int argc, char * const *argv)\n{\n    int opt;\n    const char *filename = NULL;\n    int source_fd = -1;\n\n    int doidentify;\n    int dotrace = 0;\n    int dowrite = 0;\n    bool verbose = false;\n    while ((opt = getopt(argc, argv, \"iw:tv\")) != -1) {\n\tswitch (opt) {\n\tcase 'i':\n\t    doidentify = 1;\n\t    break;\n\tcase 't':\n\t    dotrace = 1;\n\t    break;\n\tcase 'v':\n\t    verbose = true;\n\t    break;\n\tcase 'w':\n\t    filename = optarg;\n\t    dowrite = 1;\n\t    break;\n\t}\n    }\n\n    if (dowrite) {\n\tstruct stat statbuf;\n\tint rc = stat(filename, &statbuf);\n\tif (rc < 0) {\n\t    fprintf(stderr, \"%s:%d File %s does not exist %d:%s\\n\", __FILE__, __LINE__, filename, errno, strerror(errno));\n\t    return rc;\n\t}\n    }\n\n    Nvme nvme(verbose);\n\n    sleep(1);\n\n    nvme.setup();\n\n    if (doidentify)\n\tnvme.identify();\n    nvme.getFeatures();\n    nvme.allocIOQueues(0);\n\n    fprintf(stderr, \"CSTS %08x\\n\", nvme.read32( 0x1c));\n    int startBlock = 100000; // base and extent of test file in SSD\n    int blocksPerRequest = 8; //12*BlocksPerRequest;\n    int numBlocks = 1*blocksPerRequest; // 55; //8177;\n    if (dowrite) {\n\tstruct stat statbuf;\n\tint rc = stat(filename, &statbuf);\n\tif (rc < 0) {\n\t    fprintf(stderr, \"%s:%d File %s does not exist %d:%s\\n\", __FILE__, __LINE__, filename, errno, strerror(errno));\n\t    return rc;\n\t}\n\tnumBlocks = statbuf.st_blocks;\n\tnumBlocks -= (numBlocks % blocksPerRequest);\n\tfprintf(stderr, \"Writing %d blocks from file %s to flash at block %d\\n\", numBlocks, filename, startBlock);\n\tsource_fd = open(filename, O_RDONLY);\n    }\n\n    for (int block = 0; block < numBlocks; block += blocksPerRequest) {\n\tnvme_io_opcode opcode = (dowrite) ? nvme_write : nvme_read;\n\tfprintf(stderr, \"starting transfer dowrite=%d opcode=%d\\n\", dowrite, opcode);\n\tif (opcode == nvme_write) {\n\t    if (filename) {\n\t\tsize_t bytesToRead = 512*blocksPerRequest;\n\t\tchar *buffer = (char *)nvme.transferBuffer.buffer();\n\t\tdo {\n\t\t    size_t bytesRead = read(source_fd, buffer, bytesToRead);\n\t\t    if (bytesRead <= 0) {\n\t\t\tfprintf(stderr, \"%s:%d Requested %ld bytes, received %ld bytes errno=%d:%s\\n\",\n\t\t\t\t__FUNCTION__, __LINE__, bytesToRead, bytesRead, errno, strerror(errno));\n\t\t\tbreak;\n\t\t    }\n\t\t    bytesToRead -= bytesRead;\n\t\t    buffer += bytesRead;\n\t\t} while (bytesToRead);\n\t    } else {\n\t\t    int *buffer = (int *)nvme.transferBuffer.buffer();\n\t\tfor (int i = 0; i < numBlocks*512/4; i ++)\n\t\t    buffer[i] = i;\n\t    }\n\t}\n\tint sc = nvme.doIO(opcode, startBlock, blocksPerRequest, (opcode == nvme_read ? 2 : 1), dotrace);\n\tnvme.status();\n\tif (sc != 0)\n\t    break;\n\tstartBlock += blocksPerRequest;\n    }\n\n    nvme.dumpTrace();\n    //nvme.transferStats();\n    fprintf(stderr, \"CSTS %08x\\n\", nvme.read32( 0x1c));\n\n    return 0;\n}\n"
  },
  {
    "path": "tests/nvme_test/miniitx100.json",
    "content": "{\n    \"pcie_refclk_p\": {\n\t\"pcie\": \"sys_clk_p\"\n    },\n    \"pcie_refclk_n\": {\n\t\"pcie\": \"sys_clk_n\"\n    },\n    \"RST_N_pcie_sys_reset_n\": {\n\t\"pcie\": \"sys_reset_n\"\n    }\n}\n"
  },
  {
    "path": "tests/nvme_test/nfsume.json",
    "content": "{\n    \"pcie_refclk_p\": {\n\t\"FMC\": \"FMC_GBTCLK_P[00]\"\n    },\n    \"pcie_refclk_n\": {\n\t\"FMC\": \"FMC_GBTCLK_N[00]\"\n    },\n    \"RST_N_pcie_sys_reset_n\": {\n\t\"FMC\": \"FMC_LA_P[00]\",\n\t\"IOSTANDARD\": \"LVCMOS18\",\n\t\"PIO_DIRECTION\": \"OUTPUT\"\n    }\n}\n"
  },
  {
    "path": "tests/nvme_test/nfsume.xdc",
    "content": "set_property PACKAGE_PIN \"AT8\" [get_ports \"pcie_refclk_p\"]\nset_property DIFF_TERM \"TRUE\" [get_ports \"pcie_refclk_p\"]\nset_property PACKAGE_PIN \"AT7\" [get_ports \"pcie_refclk_n\"]\nset_property DIFF_TERM \"TRUE\" [get_ports \"pcie_refclk_n\"]\nset_property PACKAGE_PIN \"AU28\" [get_ports \"RST_N_pcie_sys_reset_n\"]\nset_property IOSTANDARD \"LVCMOS18\" [get_ports \"RST_N_pcie_sys_reset_n\"]\nset_property PIO_DIRECTION \"OUTPUT\" [get_ports \"RST_N_pcie_sys_reset_n\"]\n        \n"
  },
  {
    "path": "tests/nvme_test/nvme.xdc",
    "content": "create_clock -name root_pci_refclk -period 10 [get_ports pcie_refclk_p]\n\nset_max_delay -from [get_clocks {userclk2}] -to   [get_clocks {userclk1}] 4.0 -datapath_only\nset_max_delay -to   [get_clocks {userclk2}] -from [get_clocks {userclk1}] 4.0 -datapath_only\n\nset_max_delay -from [get_clocks {userclk2}] -to   [get_clocks {userclk2_1}] 4.0 -datapath_only\nset_max_delay -to   [get_clocks {userclk2}] -from [get_clocks {userclk2_1}] 4.0 -datapath_only\n\nset_max_delay -from [get_clocks {userclk2}] -to   [get_clocks {clk_125mhz_mux_*}] 4.0 -datapath_only\nset_max_delay -to   [get_clocks {userclk2}] -from [get_clocks {clk_125mhz_mux_*}] 4.0 -datapath_only\n\nset_max_delay -from [get_clocks {userclk2}] -to   [get_clocks {clk_250mhz_mux_*}] 4.0 -datapath_only\nset_max_delay -to   [get_clocks {userclk2}] -from [get_clocks {clk_250mhz_mux_*}] 4.0 -datapath_only\n\nset_property LOC GTHE2_CHANNEL_X1Y7 [get_cells {tile_0/*axiRootPort/inst/pcie3_ip_i/inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/gth_channel.gthe2_channel_i}]\n# PCIe Lane 1\nset_property LOC GTHE2_CHANNEL_X1Y6 [get_cells {tile_0/*axiRootPort/inst/pcie3_ip_i/inst/gt_top_i/pipe_wrapper_i/pipe_lane[1].gt_wrapper_i/gth_channel.gthe2_channel_i}]\n# PCIe Lane 2\nset_property LOC GTHE2_CHANNEL_X1Y5 [get_cells {tile_0/*axiRootPort/inst/pcie3_ip_i/inst/gt_top_i/pipe_wrapper_i/pipe_lane[2].gt_wrapper_i/gth_channel.gthe2_channel_i}]\n# PCIe Lane 3\nset_property LOC GTHE2_CHANNEL_X1Y4 [get_cells {tile_0/*axiRootPort/inst/pcie3_ip_i/inst/gt_top_i/pipe_wrapper_i/pipe_lane[3].gt_wrapper_i/gth_channel.gthe2_channel_i}]\n"
  },
  {
    "path": "tests/nvme_test/synth-ip.tcl",
    "content": "source \"board.tcl\"\n\nif {$boardname == {nfsume}} {\n    set partname {xc7vx690tffg1761-3}\n    set databuswidth 128\n    set pcie_blk_locn {X0Y0}\n}\nif {$boardname == {vc709}} {\n    set partname {xc7vx690tffg1761-2}\n    set databuswidth 128\n    set pcie_blk_locn {X0Y2}\n}\nif {$boardname == {miniitx100}} {\n    set databuswidth 128\n    set pcie_blk_locn {X1Y0}\n}\nif {$boardname == {zc706}} {\n    set databuswidth 128\n    set pcie_blk_locn {X1Y0}\n}\nif {$boardname == {vc707g2}} {\n    set databuswidth 128\n    set pcie_blk_locn {X1Y1}\n}\nputs \"partname=$partname\"\nputs \"databuswidth=$databuswidth\"\n\ncreate_project -name local_synthesized_ip -in_memory -part $partname\nif {$boardname == {nfsume}} {\n    set_property board_part xilinx.com:vc709:part0:1.0 [current_project]\n}\nproc fpgamake_ipcore {core_name core_version ip_name params} {\n    global ipdir boardname\n\n    set generate_ip 0\n\n    if [file exists $ipdir/$boardname/$ip_name/$ip_name.xci] {\n    } else {\n\tputs \"no xci file $ip_name.xci\"\n\tset generate_ip 1\n    }\n    if [file exists $ipdir/$boardname/$ip_name/vivadoversion.txt] {\n\tgets [open $ipdir/$boardname/$ip_name/vivadoversion.txt r] generated_version\n\tset current_version [version -short]\n\tputs \"core was generated by vivado $generated_version, currently running vivado $current_version\"\n\tif {$current_version != $generated_version} {\n\t    puts \"vivado version does not match\"\n\t    set generate_ip 1\n\t}\n    } else {\n\tputs \"no vivado version recorded\"\n\tset generate_ip 1\n    }\n\n    ## check requested core version and parameters\n    if [file exists $ipdir/$boardname/$ip_name/coreversion.txt] {\n\tgets [open $ipdir/$boardname/$ip_name/coreversion.txt r] generated_version\n\tset current_version \"$core_name $core_version $params\"\n\tputs \"Core generated: $generated_version\"\n\tputs \"Core requested: $current_version\"\n\tif {$current_version != $generated_version} {\n\t    puts \"core version or params does not match\"\n\t    set generate_ip 1\n\t}\n    } else {\n\tputs \"no core version recorded\"\n\tset generate_ip 1\n    }\n\n    if $generate_ip {\n\tfile delete -force $ipdir/$boardname/$ip_name\n\tfile mkdir $ipdir/$boardname\n\tcreate_ip -name $core_name -version $core_version -vendor xilinx.com -library ip -module_name $ip_name -dir $ipdir/$boardname\n\tif [llength $params] {\n\t    set_property -dict $params [get_ips $ip_name]\n\t}\n        report_property -file $ipdir/$boardname/$ip_name.properties.log [get_ips $ip_name]\n\t\n\tgenerate_target all [get_files $ipdir/$boardname/$ip_name/$ip_name.xci]\n\n\tset versionfd [open $ipdir/$boardname/$ip_name/vivadoversion.txt w]\n\tputs $versionfd [version -short]\n\tclose $versionfd\n\n\tset corefd [open $ipdir/$boardname/$ip_name/coreversion.txt w]\n\tputs $corefd \"$core_name $core_version $params\"\n\tclose $corefd\n    } else {\n\tread_ip $ipdir/$boardname/$ip_name/$ip_name.xci\n    }\n    if [file exists $ipdir/$boardname/$ip_name/$ip_name.dcp] {\n    } else {\n\tsynth_ip [get_ips $ip_name]\n    }\n}\n\nif {$partname != {xc7vx690tffg1761-2} && $partname != {xc7vx690tffg1761-3}} {\n    fpgamake_ipcore axi_pcie 2.8 axi_pcie_rp [list \\\n\t\t\t\t\t\t  CONFIG.AXIBAR2PCIEBAR_0 {0x00000000} \\\n\t\t\t\t\t\t  CONFIG.AXIBAR_0 {0x00000000} \\\n\t\t\t\t\t\t  CONFIG.AXIBAR_HIGHADDR_0 {0xfFFFFFFF} \\\n\t\t\t\t\t\t  CONFIG.BAR0_SCALE {Gigabytes} \\\n\t\t\t\t\t\t  CONFIG.BAR0_SIZE {1} \\\n\t\t\t\t\t\t  CONFIG.BASEADDR {0x00000000} \\\n\t\t\t\t\t\t  CONFIG.BASE_CLASS_MENU {Bridge_device} \\\n\t\t\t\t\t\t  CONFIG.DEVICE_ID {0x7022} \\\n\t\t\t\t\t\t  CONFIG.HIGHADDR {0xffffffff} \\\n\t\t\t\t\t\t  CONFIG.INCLUDE_BAROFFSET_REG {false} \\\n\t\t\t\t\t\t  CONFIG.INCLUDE_RC {Root_Port_of_PCI_Express_Root_Complex} \\\n\t\t\t\t\t\t  CONFIG.MAX_LINK_SPEED {5.0_GT/s} \\\n\t\t\t\t\t\t  CONFIG.M_AXI_DATA_WIDTH {128} \\\n\t\t\t\t\t\t  CONFIG.NO_OF_LANES {X4} \\\n\t\t\t\t\t\t  CONFIG.NUM_MSI_REQ {5} \\\n\t\t\t\t\t\t  CONFIG.PCIE_BLK_LOCN $pcie_blk_locn \\\n\t\t\t\t\t\t  CONFIG.SUB_CLASS_INTERFACE_MENU {InfiniBand_to_PCI_host_bridge} \\\n\t\t\t\t\t\t  CONFIG.S_AXI_DATA_WIDTH {128} \\\n\t\t\t\t\t\t  CONFIG.S_AXI_SUPPORTS_NARROW_BURST {true} \\\n\t\t\t\t\t\t  CONFIG.shared_logic_in_core {true} \\\n\t\t\t\t\t\t ]\n} else {\n    if {[version -short] >= \"2016.1\"} {\n\tset axi_pcie3_version 2.1\n    } else {\n\tset axi_pcie3_version 2.0\n    }\n    fpgamake_ipcore axi_pcie3 $axi_pcie3_version axi_pcie_rp [list \\\n\t\t\t\t\t\t   CONFIG.axi_data_width {128_bit} \\\n\t\t\t\t\t\t   CONFIG.axibar_highaddr_0 {0xffffffffffffffff} \\\n\t\t\t\t\t\t   CONFIG.dedicate_perst {false} \\\n\t\t\t\t\t\t   CONFIG.device_port_type {Root_Port_of_PCI_Express_Root_Complex} \\\n\t\t\t\t\t\t   CONFIG.mode_selection {Advanced} \\\n\t\t\t\t\t\t   CONFIG.pcie_blk_locn $pcie_blk_locn \\\n\t\t\t\t\t\t   CONFIG.pf0_bar0_scale {Gigabytes} \\\n\t\t\t\t\t\t   CONFIG.pf0_bar0_size {2} \\\n\t\t\t\t\t\t   CONFIG.pf0_base_class_menu {Bridge_device} \\\n\t\t\t\t\t\t   CONFIG.pf0_class_code {060700} \\\n\t\t\t\t\t\t   CONFIG.pf0_class_code_base {06} \\\n\t\t\t\t\t\t   CONFIG.pf0_class_code_sub {07} \\\n\t\t\t\t\t\t   CONFIG.pf0_device_id {7131} \\\n\t\t\t\t\t\t   CONFIG.pf0_sub_class_interface_menu {CardBus_bridge} \\\n\t\t\t\t\t\t   CONFIG.pl_link_cap_max_link_speed {5.0_GT/s} \\\n\t\t\t\t\t\t   CONFIG.pl_link_cap_max_link_width {X4} \\\n\t\t\t\t\t\t   CONFIG.s_axi_id_width {4} \\\n\t\t\t\t\t\t  ]\n}\n\nif {[version -short] >= \"2016.1\"} {\n    set dual_clock_axis_fifo_version 13.1\n} else {\n    set dual_clock_axis_fifo_version 13.0\n}\nfpgamake_ipcore fifo_generator $dual_clock_axis_fifo_version dual_clock_axis_fifo_32x8 [list \\\n                           CONFIG.INTERFACE_TYPE {AXI_STREAM} \\\n                           CONFIG.Clock_Type_AXI {Independent_Clock} \\\n                           CONFIG.TDATA_NUM_BYTES {4} \\\n                           CONFIG.TUSER_WIDTH {0} \\\n                           CONFIG.Enable_TLAST {true} \\\n                           CONFIG.HAS_TKEEP {true} \\\n                           CONFIG.FIFO_Application_Type_axis {Data_FIFO} \\\n                           CONFIG.Reset_Type {Asynchronous_Reset} \\\n                           ]\n\n"
  },
  {
    "path": "tests/ov7670/Makefile",
    "content": "CONNECTALDIR?=../..\nS2H_INTERFACES = Ov7670ControllerRequest:Ov7670Controller.request\nH2S_INTERFACES = Ov7670Controller:Ov7670ControllerIndication\nMEM_WRITE_INTERFACES = lOv7670Controller.dmaClient\n\nBSVFILES = Ov7670Interface.bsv\nCPPFILES= testcam.cpp\n\nPIN_TYPE = Ov7670Pins\nPIN_TYPE_INCLUDE = Ov7670Interface\nPINOUT_FILE = pinout.json\nAUTOTOP = --interface pins:Ov7670Controller.pins\n\ninclude $(CONNECTALDIR)/Makefile.connectal\n"
  },
  {
    "path": "tests/ov7670/Ov7670Controller.bsv",
    "content": "\n// Copyright (c) 2015 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\nimport Vector::*;\nimport BuildVector::*;\nimport Clocks::*;\nimport GetPut::*;\nimport ClientServer::*;\nimport SCCB::*;\nimport FIFOF::*;\nimport BRAMFIFO::*;\nimport Gearbox::*;\nimport ConnectalMemTypes::*;\nimport ConnectalConfig::*;\nimport MemWriteEngine::*;\nimport Pipe::*;\nimport ConnectalClocks::*;\nimport ConnectalXilinxCells::*;\nimport Ov7670Interface::*;\n\ninterface Ov7670Controller;\n   interface Ov7670ControllerRequest request;\n   interface Ov7670Pins pins;\n   interface Vector#(1,MemWriteClient#(DataBusWidth)) dmaClient;\nendinterface\n\nmodule mkOv7670Controller#(Ov7670ControllerIndication ind)(Ov7670Controller);\n\n   Integer divisor = 12;\n   Clock defaultClock <- exposeCurrentClock;\n   Reset defaultReset <- exposeCurrentReset;\n   ClockDividerIfc clockDivider <- mkClockDivider(divisor);\n   B2C1 b2c <- mkB2C1;\n   let pclk = b2c.c;\n   Reset preset <- mkAsyncReset(2, defaultReset, pclk);\n   SyncFIFOIfc#(Tuple2#(Bit#(32),Bit#(1))) vsyncFifo <- mkSyncFIFO(32, pclk, preset, defaultClock);\n   SyncFIFOIfc#(Tuple3#(Bool, Bool, Bit#(8))) dataFifo <- mkSyncBRAMFIFO(16384, pclk, preset, defaultClock, defaultReset);\n   Gearbox#(1, 8, Bit#(8))                  dataGearbox <- mk1toNGearbox(defaultClock, defaultReset, defaultClock, defaultReset);\n\n   MemWriteEngine#(DataBusWidth,DataBusWidth,8,1) writeEngine <- mkMemWriteEngineBuff(2048);\n   FIFOF#(Bool)        sofFifo    <- mkFIFOF();\n   Reg#(Bit#(32))      pointerReg <- mkReg(0);\n   Reg#(Bool)     transferDoneReg <- mkReg(False);\n\n   Reg#(Bit#(32)) cycleReg     <- mkReg(0, clocked_by pclk, reset_by preset);\n   Reg#(Bit#(32)) lastVsyncReg <- mkReg(0, clocked_by pclk, reset_by preset);\n   Reg#(Bit#(32)) lastDataReg  <- mkReg(0, clocked_by pclk, reset_by preset);\n   Reg#(Bit#(1)) vsyncReg      <- mkReg(0, clocked_by pclk, reset_by preset);\n   Reg#(Bit#(1)) hrefReg       <- mkReg(0, clocked_by pclk, reset_by preset);\n   Reg#(Bit#(8)) dataReg       <- mkReg(0, clocked_by pclk, reset_by preset);\n   Reg#(Bool)    firstReg      <- mkReg(False, clocked_by pclk, reset_by preset);\n   Reg#(Bool)    lastReg       <- mkReg(False, clocked_by pclk, reset_by preset);\n   Reg#(Bit#(16)) dataGapCycles <- mkReg(0, clocked_by pclk, reset_by preset);\n   Wire#(Bool)    dataRuleFired <- mkDWire(False, clocked_by pclk, reset_by preset);\n\n   Vector#(3, SCCB) i2c <- replicateM(mkSCCB(1000));\n   Reg#(bit) resetReg <- mkReg(0);\n   Reg#(bit) pwdnReg <- mkReg(0);\n\n   Reg#(Bit#(1))                   rSCL                <- mkReg(1);\n   Reg#(Bit#(1))                   rSDA                <- mkReg(1);\n   Reg#(Bool)                      rOutEn              <- mkReg(True);\n\n   for (Integer i = 0; i < 3; i = i + 1)\n      rule i2c_response_rule;\n\t let response <- i2c[i].user.response.get();\n\t ind.i2cResponse(fromInteger(i), response.data);\n      endrule\n\n   rule cycleRule;\n      cycleReg <= cycleReg + 1;\n   endrule\n\n   rule vsyncRule;\n      if (vsyncReg == 1) begin\n\t vsyncFifo.enq(tuple2(cycleReg - lastVsyncReg, hrefReg));\n\t lastVsyncReg <= cycleReg;\n      end\n   endrule\n\n   rule vsyncSyncRule;\n      match { .cycles, .href } <- toGet(vsyncFifo).get();\n      ind.vsync(cycles, href);\n      if (sofFifo.notFull())\n\t sofFifo.enq(True);\n   endrule\n\n   rule dataRule;\n      if (hrefReg == 1) begin\n\t dataRuleFired <= True;\n\t let gap = dataGapCycles != 0;\n\t dataFifo.enq(tuple3(firstReg, (firstReg ? False : gap), dataReg));\n\t lastDataReg <= cycleReg;\n\t firstReg <= False;\n      end\n      else begin\n\t firstReg <= True;\n      end\n   endrule\n\n   rule dataRuleGap if (hrefReg == 1);\n      if (!dataRuleFired)\n\t dataGapCycles <= dataGapCycles + 1;\n      else\n\t dataGapCycles <= 0;\n   endrule\n\n   rule dataSyncRule;\n      match { .first, .gap, .pxl } <- toGet(dataFifo).get();\n\n      if (sofFifo.notEmpty() && transferDoneReg) begin\n\t sofFifo.deq();\n\t transferDoneReg <= False;\n\t writeEngine.writeServers[0].request.put(MemengineCmd { sglId: pointerReg, base: 0, burstLen: 8*8, len: 640*480, tag: 0});\n\t ind.frameStarted(pack(first));\n      end\n\n      dataGearbox.enq(unpack(pxl));\n      if (gap)\n\t ind.data(pack(first), pack(gap), pxl);\n   endrule\n\n   rule dataIndRule;\n      let d = dataGearbox.first();\n      dataGearbox.deq();\n      //ind.data8(pack(d));\n      if (pointerReg != 0)\n\t writeEngine.writeServers[0].data.enq(pack(d));\n   endrule\n\n   rule transferDoneRule;\n      let d <- writeEngine.writeServers[0].done.get();\n      transferDoneReg <= True;\n      ind.frameTransferred();\n   endrule\n\n   interface Ov7670ControllerRequest request;\n      method Action setFramePointer(Bit#(32) frameId);\n\t pointerReg <= frameId;\n\t transferDoneReg <= True; // prime the pump\n      endmethod\n      method Action i2cRequest(Bit#(8) bus, Bool write, Bit#(7) slaveaddr, Bit#(8) address, Bit#(8) data);\n\t i2c[bus].user.request.put(SCCBRequest {write: write, slaveaddr: slaveaddr, address: address, data: data});\n      endmethod\n      method Action setReset(Bit#(1) rval);\n\t resetReg <= rval;\n      endmethod\n      method Action setPowerDown(Bit#(1) pwdn);\n\t pwdnReg <= pwdn;\n      endmethod\n   endinterface\n   interface Ov7670Pins pins;\n      interface SCCB_Pins i2c0 = i2c[0].i2c;\n      interface SCCB_Pins i2c1 = i2c[1].i2c;\n      interface SCCB_Pins i2c2 = i2c[2].i2c;\n      interface Clock xclk = clockDivider.slowClock;\n      interface Clock pclk_deleteme_unused_clock = pclk;\n      method bit reset() = resetReg;\n      method bit pwdn() = pwdnReg;\n      method Action pclk(Bit#(1) v);\n\t b2c.inputclock(v);\n      endmethod\n      method Action pxl(Bit#(1) vsync, Bit#(1) href, Bit#(8) data);\n\t vsyncReg <= vsync;\n\t hrefReg  <= href;\n\t dataReg <= data;\n      endmethod\n   endinterface\n   interface Vector dmaClient = vec(writeEngine.dmaClient);\nendmodule\n"
  },
  {
    "path": "tests/ov7670/Ov7670Interface.bsv",
    "content": "\n// Copyright (c) 2015 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\nimport SCCB::*;\n\ninterface Ov7670ControllerRequest;\n   method Action setFramePointer(Bit#(32) frameId);\n   method Action i2cRequest(Bit#(8) bus, Bool write, Bit#(7) slaveaddr, Bit#(8) address, Bit#(8) data);\n   method Action setReset(Bit#(1) rval);\n   method Action setPowerDown(Bit#(1) pwdn);\nendinterface\n\ninterface Ov7670ControllerIndication;\n   method Action i2cResponse(Bit#(8) bus, Bit#(8) data);\n   method Action vsync(Bit#(32) cycles, Bit#(1) href);\n   method Action data(Bit#(1) first, Bit#(1) gap, Bit#(8) pxl);\n   method Action data4(Bit#(32) pxls);\n   method Action frameStarted(Bit#(1) first);\n   method Action frameTransferred();\nendinterface\n\ninterface Ov7670Pins;\n   interface SCCB_Pins i2c0;\n   interface SCCB_Pins i2c1;\n   interface SCCB_Pins i2c2;\n   interface Clock xclk;\n   interface Clock pclk_deleteme_unused_clock;\n   method bit reset();\n   method bit pwdn();\n   method Action pclk(Bit#(1) v);\n   method Action pxl(Bit#(1) vsync, Bit#(1) href, Bit#(8) data);\nendinterface\n"
  },
  {
    "path": "tests/ov7670/SCCB.bsv",
    "content": "////////////////////////////////////////////////////////////////////////////////\n// Copyright (c) 2011  Bluespec, Inc.   ALL RIGHTS RESERVED.\n//  $Revision     : $\n//  $Date         : $\n////////////////////////////////////////////////////////////////////////////////\n//  Filename      : SCCB.bsv\n//  Description   : SCCB master read/write controller \n////////////////////////////////////////////////////////////////////////////////\npackage SCCB;\n\n// Notes :\n\n////////////////////////////////////////////////////////////////////////////////\n/// Imports\n////////////////////////////////////////////////////////////////////////////////\nimport Vector            ::*;\nimport FIFO              ::*;\nimport FIFOF             ::*;\nimport Counter           ::*;\nimport TriState          ::*;\nimport BUtils            ::*;\nimport Arbitrate         ::*;\nimport Connectable       ::*;\nimport GetPut            ::*;\nimport ClientServer      ::*;\n\nimport ConnectalXilinxCells::*;\n\n////////////////////////////////////////////////////////////////////////////////\n/// Exports\n////////////////////////////////////////////////////////////////////////////////\nexport SCCB_Pins(..);\nexport SCCB(..);\nexport SCCBController(..);\nexport SCCBRequest(..);\nexport SCCBResponse(..);\n\nexport mkSCCB;\nexport mkSCCBController;\n\n////////////////////////////////////////////////////////////////////////////////\n/// Types\n////////////////////////////////////////////////////////////////////////////////\ntypedef struct {\n   Bool     write;\n   Bit#(7)  slaveaddr;\n   Bit#(8)  address;\n   Bit#(8)  data;\n} SCCBRequest deriving (Bits, Eq);\n\ntypedef struct {\n   Bit#(8)  data;\n} SCCBResponse deriving (Bits, Eq);\n\ninstance ArbRequestTC#(SCCBRequest);\n   function Bool isReadRequest(SCCBRequest a) = !a.write;\n   function Bool isWriteRequest(SCCBRequest a) = a.write;\nendinstance\n\ntypedef enum {\n   Idle,\n   Running\n} State deriving (Bits, Eq);\n\n////////////////////////////////////////////////////////////////////////////////\n/// Interfaces\n////////////////////////////////////////////////////////////////////////////////\n(* always_enabled, always_ready *)\ninterface SCCB_Pins;\n   (* prefix = \"SDA\" *)\n   interface Inout#(Bit#(1)) sda;\n   (* prefix = \"SCL\" *)\n   interface Inout#(Bit#(1)) scl;\nendinterface\n\ninterface SCCB;\n   (* prefix = \"\" *)\n   interface SCCB_Pins i2c;\n   interface Server#(SCCBRequest, SCCBResponse) user;\nendinterface\n\ninterface SCCBController#(numeric type n);\n   (* prefix = \"\" *)\n   interface SCCB_Pins i2c;\n   interface Vector#(n, Server#(SCCBRequest, SCCBResponse)) users;\nendinterface      \n\n////////////////////////////////////////////////////////////////////////////////\n////////////////////////////////////////////////////////////////////////////////\n/// \n/// Implementation\n/// \n////////////////////////////////////////////////////////////////////////////////\n////////////////////////////////////////////////////////////////////////////////\nmodule mkSCCB#(Integer prescale)(SCCB);\n   \n   ////////////////////////////////////////////////////////////////////////////////\n   /// Design Elements\n   ////////////////////////////////////////////////////////////////////////////////\n   FIFOF#(SCCBRequest)              fRequest            <- mkSizedFIFOF(16);\n   FIFO#(SCCBResponse)              fResponse           <- mkSizedFIFO(16);\n   \n   Reg#(Bit#(1))                   rSCL                <- mkReg(1);\n   Reg#(Bit#(1))                   rSDA                <- mkReg(1);\n   Reg#(Bool)                      rOutEn              <- mkReg(True);\n   TriState#(Bit#(1))              tSCL                <- mkTriState(True, rSCL);\n   //TriState#(Bit#(1))              tSDA                <- mkTriState(rOutEn, rSDA);\n   //IOBUF                           ioSCL               <- mkIOBUF(pack(True), rSCL);\n   IOBUF                           ioSDA               <- mkIOBUF(rOutEn ? 0 : 1, rSDA);\n\n   Counter#(32)                    rPrescaler          <- mkCounter(fromInteger(prescale));\n   PulseWire                       pwTick              <- mkPulseWire;\n   Counter#(10)                    rPlayIndex          <- mkCounter(0);\n   \n   Reg#(State)                     rState              <- mkReg(Idle);\n   Reg#(Bool)                      rWrite              <- mkRegU;\n   Reg#(Bit#(7))                   rSlaveAddr          <- mkRegU;\n   Reg#(Bit#(8))                   rAddress            <- mkRegU;\n   Reg#(Bit#(8))                   rWriteData          <- mkRegU;\n   Vector#(8, Reg#(Bit#(1)))       vrReadData          <- replicateM(mkRegU);\n   \n   Bit#(7)                         slv                  = rSlaveAddr;\n   Bit#(3)                         s6                   = duplicate(slv[6]);\n   Bit#(3)                         s5                   = duplicate(slv[5]);\n   Bit#(3)                         s4                   = duplicate(slv[4]);\n   Bit#(3)                         s3                   = duplicate(slv[3]);\n   Bit#(3)                         s2                   = duplicate(slv[2]);\n   Bit#(3)                         s1                   = duplicate(slv[1]);\n   Bit#(3)                         s0                   = duplicate(slv[0]);\n   \n   Bit#(8)                         adr                  = rAddress;\n   Bit#(3)                         a7                   = duplicate(adr[7]);\n   Bit#(3)                         a6                   = duplicate(adr[6]);\n   Bit#(3)                         a5                   = duplicate(adr[5]);\n   Bit#(3)                         a4                   = duplicate(adr[4]);\n   Bit#(3)                         a3                   = duplicate(adr[3]);\n   Bit#(3)                         a2                   = duplicate(adr[2]);\n   Bit#(3)                         a1                   = duplicate(adr[1]);\n   Bit#(3)                         a0                   = duplicate(adr[0]);\n   \n   Bit#(8)                         dat                  = rWriteData;\n   Bit#(3)                         d7                   = duplicate(dat[7]);\n   Bit#(3)                         d6                   = duplicate(dat[6]);\n   Bit#(3)                         d5                   = duplicate(dat[5]);\n   Bit#(3)                         d4                   = duplicate(dat[4]);\n   Bit#(3)                         d3                   = duplicate(dat[3]);\n   Bit#(3)                         d2                   = duplicate(dat[2]);\n   Bit#(3)                         d1                   = duplicate(dat[1]);\n   Bit#(3)                         d0                   = duplicate(dat[0]);\n   \n   ////////////////////////////////////////////////////////////////////////////////\n   /// Reads\n   ////////////////////////////////////////////////////////////////////////////////\n   Integer                         readLength           = 120;\n   //                start   slv[6]  slv[5]  slv[4]  slv[3]  slv[2]  slv[1]  slv[0]  write    ack    adr[7]  adr[6]  adr[5]  adr[4]  adr[3]  adr[2]  adr[1]  adr[0]   ack    stop    start   slv[6]  slv[5]  slv[4]  slv[3]  slv[2]  slv[1]  slv[0]   read    ack    dat[7]  dat[6]  dat[5]  dat[4]  dat[3]  dat[2]  dat[1]  dat[0]   ack     stop\n   let wRdClock  = { 3'b110, 3'b010, 3'b010, 3'b010, 3'b010, 3'b010, 3'b010, 3'b010, 3'b010, 3'b010, 3'b010, 3'b010, 3'b010, 3'b010, 3'b010, 3'b010, 3'b010, 3'b010, 3'b010, 3'b011, 3'b111, 3'b010, 3'b010, 3'b010, 3'b010, 3'b010, 3'b010, 3'b010, 3'b010, 3'b010, 3'b010, 3'b010, 3'b010, 3'b010, 3'b010, 3'b010, 3'b010, 3'b010, 3'b010, 3'b011 };\n   let wRdData   = { 3'b100, s6,     s5,     s4,     s3,     s2,     s1,     s0,     3'b000, 3'b000, a7,     a6,     a5,     a4,     a3,     a2,     a1,     a0,     3'b000, 3'b001, 3'b110, s6,     s5,     s4,     s3,     s2,     s1,     s0,     3'b111, 3'b000, 3'b000, 3'b000, 3'b000, 3'b000, 3'b000, 3'b000, 3'b000, 3'b000, 3'b000, 3'b001 };\n   let wRdOutEn  = { 3'b111, 3'b111, 3'b111, 3'b111, 3'b111, 3'b111, 3'b111, 3'b111, 3'b111, 3'b000, 3'b111, 3'b111, 3'b111, 3'b111, 3'b111, 3'b111, 3'b111, 3'b111, 3'b000, 3'b111, 3'b111, 3'b111, 3'b111, 3'b111, 3'b111, 3'b111, 3'b111, 3'b111, 3'b111, 3'b000, 3'b000, 3'b000, 3'b000, 3'b000, 3'b000, 3'b000, 3'b000, 3'b000, 3'b000, 3'b111 };\n   let wRdSample = { 3'b000, 3'b000, 3'b000, 3'b000, 3'b000, 3'b000, 3'b000, 3'b000, 3'b000, 3'b000, 3'b000, 3'b000, 3'b000, 3'b000, 3'b000, 3'b000, 3'b000, 3'b000, 3'b000, 3'b000, 3'b000, 3'b000, 3'b000, 3'b000, 3'b000, 3'b000, 3'b000, 3'b000, 3'b000, 3'b000, 3'b010, 3'b010, 3'b010, 3'b010, 3'b010, 3'b010, 3'b010, 3'b010, 3'b000, 3'b000 };\n   \n   ////////////////////////////////////////////////////////////////////////////////\n   /// Writes\n   ////////////////////////////////////////////////////////////////////////////////\n   Integer                         writeLength          = 87;\n   //                start   slv[6]  slv[5]  slv[4]  slv[3]  slv[2]  slv[1]  slv[0]  write    ack    adr[7]  adr[6]  adr[5]  adr[4]  adr[3]  adr[2]  adr[1]  adr[0]   ack    dat[7]  dat[6]  dat[5]  dat[4]  dat[3]  dat[2]  dat[1]  dat[0]   ack     stop\n   let wWrClock  = { 3'b110, 3'b010, 3'b010, 3'b010, 3'b010, 3'b010, 3'b010, 3'b010, 3'b010, 3'b010, 3'b010, 3'b010, 3'b010, 3'b010, 3'b010, 3'b010, 3'b010, 3'b010, 3'b010, 3'b010, 3'b010, 3'b010, 3'b010, 3'b010, 3'b010, 3'b010, 3'b010, 3'b010, 3'b011 };\n   let wWrData   = { 3'b100, s6,     s5,     s4,     s3,     s2,     s1,     s0,     3'b000, 3'b000, a7,     a6,     a5,     a4,     a3,     a2,     a1,     a0,     3'b000, d7,     d6,     d5,     d4,     d3,     d2,     d1,     d0,     3'b000, 3'b001 };\n   let wWrOutEn  = { 3'b111, 3'b111, 3'b111, 3'b111, 3'b111, 3'b111, 3'b111, 3'b111, 3'b111, 3'b000, 3'b111, 3'b111, 3'b111, 3'b111, 3'b111, 3'b111, 3'b111, 3'b111, 3'b000, 3'b111, 3'b111, 3'b111, 3'b111, 3'b111, 3'b111, 3'b111, 3'b111, 3'b000, 3'b111 };\n\n   ////////////////////////////////////////////////////////////////////////////////\n   /// Rules\n   ////////////////////////////////////////////////////////////////////////////////\n   (* fire_when_enabled, no_implicit_conditions *)\n   rule update_prescaler(rPrescaler.value > 0);\n      rPrescaler.down;\n   endrule\n\n   (* fire_when_enabled, no_implicit_conditions *)\n   rule reset_prescaler(rPrescaler.value == 0);\n      rPrescaler.setF(fromInteger(prescale));\n      pwTick.send;\n   endrule\n   \n   rule start(rState == Idle);\n      let request = fRequest.first; fRequest.deq;\n      rSlaveAddr <= request.slaveaddr;\n      rAddress   <= request.address;\n      rWriteData <= request.data;\n      rWrite     <= request.write;\n      rState     <= Running;\n      if (request.write)\n\t rPlayIndex.setF(fromInteger(writeLength-1));\n      else\n\t rPlayIndex.setF(fromInteger(readLength-1));\n   endrule\n   \n   rule running_write(rState == Running && rWrite && pwTick && rPlayIndex.value > 0);\n      rPlayIndex.down;\n      rOutEn     <= wWrOutEn[rPlayIndex.value] == 1;\n      rSDA       <= wWrData[rPlayIndex.value];\n      rSCL       <= wWrClock[rPlayIndex.value];\n   endrule\n\n   rule running_read(rState == Running && !rWrite && pwTick && rPlayIndex.value > 0);\n      rPlayIndex.down;\n      rOutEn     <= wRdOutEn[rPlayIndex.value] == 1;\n      rSDA       <= wRdData[rPlayIndex.value];\n      rSCL       <= wRdClock[rPlayIndex.value];\n      if (wRdSample[rPlayIndex.value] == 1) writeVReg(vrReadData, shiftInAt0(readVReg(vrReadData), ioSDA.o()));\n   endrule\n            \n   rule done_write(rState == Running && rWrite && pwTick && rPlayIndex.value == 0);\n      rPlayIndex.down;\n      rOutEn     <= wWrOutEn[rPlayIndex.value] == 1;\n      rSDA       <= wWrData[rPlayIndex.value];\n      rSCL       <= wWrClock[rPlayIndex.value];\n      rState     <= Idle;\n   endrule\n\n   rule done_read(rState == Running && !rWrite && pwTick && rPlayIndex.value == 0);\n      rOutEn     <= wRdOutEn[rPlayIndex.value] == 1;\n      rSDA       <= wRdData[rPlayIndex.value];\n      rSCL       <= wRdClock[rPlayIndex.value];\n      rState     <= Idle;\n      fResponse.enq(unpack(pack(readVReg(vrReadData))));\n   endrule\n   \n   ////////////////////////////////////////////////////////////////////////////////\n   /// Interface Connections / Methods\n   ////////////////////////////////////////////////////////////////////////////////\n   interface SCCB_Pins i2c;\n      interface sda    = ioSDA.io;\n      interface scl    = tSCL.io;\n   endinterface\n  \n   interface Server user;\n      interface request  = toPut(fRequest);\n      interface response = toGet(fResponse);\n   endinterface\n \nendmodule\n\n////////////////////////////////////////////////////////////////////////////////\n////////////////////////////////////////////////////////////////////////////////\n///\n/// Implementation of SCCB Controller\n///\n////////////////////////////////////////////////////////////////////////////////\n////////////////////////////////////////////////////////////////////////////////\nmodule mkSCCBController(SCCBController#(n))\n   provisos(\n\t    Add#(1, _1, n)\n\t    );\n   \n   ////////////////////////////////////////////////////////////////////////////////\n   /// Design Elements\n   ////////////////////////////////////////////////////////////////////////////////\n   Arbitrate#(n)                             mRoundRobin         <- mkRoundRobin;\n   Arbiter#(n, SCCBRequest, SCCBResponse)      mArbiter            <- mkArbiter(mRoundRobin, 16);\n   SCCB                                       mSCCB                <- mkSCCB(1024);\n   \n   ////////////////////////////////////////////////////////////////////////////////\n   /// Submodule Connections\n   ////////////////////////////////////////////////////////////////////////////////\n   mkConnection(mArbiter.master, mSCCB.user);\n   \n   ////////////////////////////////////////////////////////////////////////////////\n   /// Interface Connections / Methods\n   ////////////////////////////////////////////////////////////////////////////////\n   interface i2c   = mSCCB.i2c;\n   interface users = mArbiter.users;   \nendmodule\n\nendpackage: SCCB\n\n"
  },
  {
    "path": "tests/ov7670/pinout.json",
    "content": "{\n    \"i2c0_SCL\" : {\n\t\"PIO_DIRECTION\": \"OUTPUT\",\n\t\"pmodb\" : \"J4\"\n    },\n    \"i2c0_SDA\" : {\n\t\"PIO_DIRECTION\": \"BIDIR\",\n\t\"PULLTYPE\": \"PULLUP\",\n\t\"pmodb\" : \"J10\"\n    },\n    \"pxl_vsync\" : {\n\t\"PIO_DIRECTION\": \"INPUT\",\n\t\"pmodb\" : \"J3\"\n    },\n    \"pxl_href\" : {\n\t\"PIO_DIRECTION\": \"INPUT\",\n\t\"pmodb\" : \"J9\"\n    },\n    \"CLK_xclk\" : {\n\t\"PIO_DIRECTION\": \"OUTPUT\",\n\t\"pmodb\" : \"J2\"\n    },\n    \"pclk_v\" : {\n\t\"PIO_DIRECTION\": \"INPUT\",\n\t\"pmodb\" : \"J8\"\n    },\n    \"pxl_data[6]\": {\n\t\"PIO_DIRECTION\": \"INPUT\",\n\t\"pmodb\" : \"J1\"\n    },\n    \"pxl_data[7]\": {\n\t\"PIO_DIRECTION\": \"INPUT\",\n\t\"pmodb\" : \"J7\"\n    },\n\n\n    \"pxl_data[4]\": {\n\t\"PIO_DIRECTION\": \"INPUT\",\n\t\"pmoda\" : \"J4\"\n    },\n    \"pxl_data[5]\": {\n\t\"PIO_DIRECTION\": \"INPUT\",\n\t\"pmoda\" : \"J10\"\n    },\n    \"pxl_data[2]\": {\n\t\"PIO_DIRECTION\": \"INPUT\",\n\t\"pmoda\" : \"J3\"\n    },\n    \"pxl_data[3]\": {\n\t\"PIO_DIRECTION\": \"INPUT\",\n\t\"pmoda\" : \"J9\"\n    },\n    \"pxl_data[0]\": {\n\t\"PIO_DIRECTION\": \"INPUT\",\n\t\"pmoda\" : \"J2\"\n    },\n    \"pxl_data[1]\": {\n\t\"PIO_DIRECTION\": \"INPUT\",\n\t\"pmoda\" : \"J8\"\n    },\n    \"pwdn\" : {\n\t\"PIO_DIRECTION\": \"OUTPUT\",\n\t\"pmoda\" : \"J1\"\n    },\n    \"reset\" : {\n\t\"PIO_DIRECTION\": \"OUTPUT\",\n\t\"pmoda\" : \"J7\"\n    },\n    \"i2c1_SCL\" : {\n\t\"PIO_DIRECTION\": \"OUTPUT\",\n\t\"pmodc\" : \"J3\"\n    },\n    \"i2c1_SDA\" : {\n\t\"PIO_DIRECTION\": \"BIDIR\",\n\t\"PULLTYPE\": \"PULLUP\",\n\t\"pmodc\" : \"J4\"\n    },\n    \"i2c2_SCL\" : {\n\t\"PIO_DIRECTION\": \"OUTPUT\",\n\t\"pmodd\" : \"J3\"\n    },\n    \"i2c2_SDA\" : {\n\t\"PIO_DIRECTION\": \"BIDIR\",\n\t\"PULLTYPE\": \"PULLUP\",\n\t\"pmodd\" : \"J4\"\n    }\n}\n"
  },
  {
    "path": "tests/ov7670/testcam.cpp",
    "content": "/* Copyright (c) 2014 Quanta Research Cambridge, Inc\n *\n * Permission is hereby granted, free of charge, to any person obtaining a\n * copy of this software and associated documentation files (the \"Software\"),\n * to deal in the Software without restriction, including without limitation\n * the rights to use, copy, modify, merge, publish, distribute, sublicense,\n * and/or sell copies of the Software, and to permit persons to whom the\n * Software is furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n * DEALINGS IN THE SOFTWARE.\n */\n#include \"dmaManager.h\"\n#include \"Ov7670ControllerRequest.h\"\n#include \"Ov7670ControllerIndication.h\"\n\nint slaveaddr[3];\nint addr;\n\nsem_t bit_sem;\n\nclass Ov7670ControllerIndication : public Ov7670ControllerIndicationWrapper {\n  int datacount;\n  int gapcount;\npublic:\n  Ov7670ControllerIndication(unsigned int id) : Ov7670ControllerIndicationWrapper(id), datacount(0), gapcount(0) {}\n  ~Ov7670ControllerIndication() {}\n  virtual void i2cResponse(uint8_t bus, uint8_t data) {\n    fprintf(stderr, \"i2c bus %d device %d addr %x response %02x\\n\", bus, slaveaddr[bus], addr, data);\n    sem_post(&bit_sem);\n  }\n  virtual void vsync(uint32_t cycles, uint8_t href) {\n    //fprintf(stderr, \"vsync %8d href %d\\n\", cycles, href);\n    if (datacount) {\n      fprintf(stderr, \"vsync datacount=%8d gapcount=%8d\\n\", datacount, gapcount);\n      datacount = 0;\n      gapcount = 0;\n    }\n  }\n  virtual void data(uint8_t first, uint8_t gap, uint8_t data) {\n    //if (gap) fprintf(stderr, \"data %8x first %d gap %d\\n\", data, first, gap);\n    datacount++;\n    if (gap) gapcount++;\n  }\n  virtual void frameStarted(uint8_t first) {\n    //if (first) fprintf(stderr, \"frameStarted %d\\n\", first);\n  }\n  virtual void frameTransferred() {\n    //fprintf(stderr, \"frameTransferred\\n\");\n  }\n  virtual void data4(uint32_t data) {\n  }\n};\n\nint main(int argc, const char **argv)\n{\n  DmaManager *dma = platformInit();\n  Ov7670ControllerRequestProxy device(IfcNames_Ov7670ControllerRequestS2H);\n  Ov7670ControllerIndication deviceResponse(IfcNames_Ov7670ControllerIndicationH2S);\n\n  int len = 640*480*4;\n  int nfbAlloc = portalAlloc(4096, 0);\n  unsigned int *nfbBuffer = (unsigned int *)portalMmap(nfbAlloc, 4096);\n  unsigned int ref_nfbAlloc = dma->reference(nfbAlloc);\n  int fbAlloc = portalAlloc(len, 0);\n  unsigned int *fbBuffer = (unsigned int *)portalMmap(fbAlloc, len);\n  unsigned int ref_fbAlloc = dma->reference(fbAlloc);\n\n  sem_init(&bit_sem, 0, 0);\n\n  device.setPowerDown(0);\n  device.setReset(0);\n  sleep(1);\n  device.setReset(1);\n  sleep(1);\n  fprintf(stderr, \"ref_fbAlloc=%d\\n\", ref_fbAlloc);\n  device.setFramePointer(ref_fbAlloc);\n\n  // register reset\n  device.i2cRequest(0, 1, 0x21, 0x12, 0x80);\n\n  // hsync instead of href\n  //device.i2cRequest(0, 1, 0x21, 0x15, 0x40);\n  // always has href\n  // device.i2cRequest(0, 1, slaveaddr[0], 0x3c, 0x80);\n\n  slaveaddr[0] = 0x21;\n  slaveaddr[1] = 0x1e;\n  slaveaddr[2] = 0x69;\n  addr = 0x5a;\n\n  for (int i = 0; i < 128; i++) {\n    int write = 0;\n    int val = 0x33;\n    addr = i;\n    device.i2cRequest(0, write, slaveaddr[0], addr, val);\n    if (!write) sem_wait(&bit_sem);\n\n    device.i2cRequest(1, write, slaveaddr[1], addr, val);\n    if (!write) sem_wait(&bit_sem);\n\n    device.i2cRequest(2, write, slaveaddr[2], addr, val);\n    if (!write) sem_wait(&bit_sem);\n\n  }\n  if (1) {\n    // product ID: 0x76\n    device.i2cRequest(0, 0, slaveaddr[0], 0x0a, 0);\n    sem_wait(&bit_sem);\n\n    // product VER: 0x70\n    device.i2cRequest(0, 0, slaveaddr[0], 0x0b, 0);\n    sem_wait(&bit_sem);\n\n    // mfg id: 0x7F\n    device.i2cRequest(0, 0, slaveaddr[0], 0x1c, 0);\n    sem_wait(&bit_sem);\n\n    // mfg id: 0xA2\n    device.i2cRequest(0, 0, slaveaddr[0], 0x1d, 0);\n    sem_wait(&bit_sem);\n  }\n  for (int i = 0; i < 64; i++)\n    fprintf(stderr, \" %02x\", fbBuffer[i] & 0xff);\n  fprintf(stderr, \"\\n\");\n  return 0;\n}\n"
  },
  {
    "path": "tests/partial/Bounce.bsv",
    "content": "// Copyright (c) 2015 The Connectal Project\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\nimport Pipe::*;\ntypedef struct {\n\tBit#(16) a;\n\tBit#(16) b;\n} EchoPair deriving (Bits);\n\ninterface Bounce;\n    interface PipeOut#(Bit#(32)) outDelay;\n    interface PipeIn#(Bit#(32))  inDelay;\n    interface PipeOut#(EchoPair) outPair;\n    interface PipeIn#(EchoPair)  inPair;\nendinterface\n"
  },
  {
    "path": "tests/partial/Bounce1.bsv",
    "content": "// Copyright (c) 2015 The Connectal Project\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\nimport FIFOF::*;\nimport Pipe::*;\nimport Bounce::*;\n\n(* synthesize *)\nmodule mkBounce(Bounce);\n    FIFOF#(Bit#(32)) delay <- mkSizedFIFOF(8);\n    FIFOF#(EchoPair) delay2 <- mkSizedFIFOF(8);\n\n    interface outDelay = toPipeOut(delay);\n    interface inDelay = toPipeIn(delay);\n    interface outPair = toPipeOut(delay2);\n    interface inPair = toPipeIn(delay2);\nendmodule\n"
  },
  {
    "path": "tests/partial/Bounce2.bsv",
    "content": "// Copyright (c) 2015 The Connectal Project\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\nimport FIFOF::*;\nimport Pipe::*;\nimport Bounce::*;\n\n(* synthesize *)\nmodule mkBounce(Bounce);\n    FIFOF#(Bit#(32)) delay <- mkSizedFIFOF(8);\n    FIFOF#(EchoPair) delay2 <- mkSizedFIFOF(8);\n\n    interface outDelay = toPipeOut(delay);\n    interface PipeIn inDelay;\n        method Action enq(Bit#(32) v);\n            delay.enq(v + 32);\n        endmethod\n        method Bool notFull();\n            return delay.notFull;\n        endmethod\n    endinterface\n    interface outPair = toPipeOut(delay2);\n    interface PipeIn inPair;\n        method Action enq(EchoPair v);\n            delay2.enq(EchoPair {b:v.a, a:v.b});\n        endmethod\n        method Bool notFull();\n            return delay2.notFull;\n        endmethod\n    endinterface\nendmodule\n"
  },
  {
    "path": "tests/partial/Bounce3.bsv",
    "content": "// Copyright (c) 2015 The Connectal Project\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\nimport FIFOF::*;\nimport Pipe::*;\nimport Bounce::*;\n\n(* synthesize *)\nmodule mkBounce(Bounce);\n    FIFOF#(Bit#(32)) delay <- mkSizedFIFOF(8);\n    FIFOF#(EchoPair) delay2 <- mkSizedFIFOF(8);\n\n    interface outDelay = toPipeOut(delay);\n    interface PipeIn inDelay;\n        method Action enq(Bit#(32) v);\n            delay.enq(v * 2);\n        endmethod\n        method Bool notFull();\n            return delay.notFull;\n        endmethod\n    endinterface\n    interface outPair = toPipeOut(delay2);\n    interface PipeIn inPair;\n        method Action enq(EchoPair v);\n            delay2.enq(EchoPair {b:v.a + 2, a:v.b - 2});\n        endmethod\n        method Bool notFull();\n            return delay2.notFull;\n        endmethod\n    endinterface\nendmodule\n"
  },
  {
    "path": "tests/partial/Echo.bsv",
    "content": "// Copyright (c) 2013 Nokia, Inc.\n// Copyright (c) 2013 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\nimport Bounce::*;\n`ifdef RedefInstance\nimport `RedefInstance::*;\n`endif\nimport Pipe::*;\n\ninterface EchoIndication;\n    method Action heard(Bit#(32) v);\n    method Action heard2(Bit#(16) a, Bit#(16) b);\nendinterface\n\ninterface EchoRequest;\n   method Action say(Bit#(32) v);\n   method Action say2(Bit#(16) a, Bit#(16) b);\n   method Action setLeds(Bit#(8) v);\nendinterface\n\ninterface Echo;\n   interface EchoRequest request;\nendinterface\n\nmodule mkEcho#(EchoIndication indication)(Echo);\n    Bounce bounce <- mkBounce();\n\n    rule heard;\n        bounce.outDelay.deq();\n        indication.heard(bounce.outDelay.first);\n    endrule\n\n    rule heard2;\n        bounce.outPair.deq();\n        indication.heard2(bounce.outPair.first.b, bounce.outPair.first.a);\n    endrule\n   \n   interface EchoRequest request;\n      method Action say(Bit#(32) v);\n\t bounce.inDelay.enq(v);\n      endmethod\n      \n      method Action say2(Bit#(16) a, Bit#(16) b);\n\t bounce.inPair.enq(EchoPair { a: a, b: b});\n      endmethod\n      \n      method Action setLeds(Bit#(8) v);\n      endmethod\n   endinterface\nendmodule\n"
  },
  {
    "path": "tests/partial/Makefile",
    "content": "CONNECTALDIR?=../..\nS2H_INTERFACES = EchoRequest:Echo.request\nH2S_INTERFACES = Echo:EchoIndication\n\nBSVFILES = Echo.bsv\nCPPFILES= testecho.cpp\n\nVARIANT?=1\nVARIANT_LIST = 2 3\nPARTIAL_MODULE = Bounce\nRECONFIG_MODULE = lEcho_bounce\nCONNECTALFLAGS += -P mk$(PARTIAL_MODULE) --implconstraint=floorplan-$(BOARD).xdc -DRedefInstance=$(PARTIAL_MODULE)$(VARIANT)\n\ninclude $(CONNECTALDIR)/Makefile.connectal\n"
  },
  {
    "path": "tests/partial/README",
    "content": "\nTo program PR bitfile:\n\necho 1 /sys/devices/amba.2/f8007000.devcfg/is_partial_bitstream\ncat variant2/Impl/ReTop/mkTop_pblock_lEcho_bounce_partial.bin >/dev/xdevcfg\ncat variant2/Impl/ReTop/mkTop_pblock_lEcho_bounce_partial.bin >/dev/xdevcfg\n./android.exe\n\nNote:\n    is_partial_bitstream is persistent\n"
  },
  {
    "path": "tests/partial/floorplan-zc702.xdc",
    "content": "\ncreate_pblock pblock_lEcho_bounce\nadd_cells_to_pblock [get_pblocks pblock_lEcho_bounce] [get_cells -quiet [list top/lEcho_bounce]]\nresize_pblock [get_pblocks pblock_lEcho_bounce] -add {SLICE_X34Y100:SLICE_X47Y149}\nresize_pblock [get_pblocks pblock_lEcho_bounce] -add {DSP48_X2Y40:DSP48_X2Y59}\nset_property SNAPPING_MODE ON [get_pblocks pblock_lEcho_bounce]\n"
  },
  {
    "path": "tests/partial/testecho.cpp",
    "content": "/* Copyright (c) 2014 Quanta Research Cambridge, Inc\n *\n * Permission is hereby granted, free of charge, to any person obtaining a\n * copy of this software and associated documentation files (the \"Software\"),\n * to deal in the Software without restriction, including without limitation\n * the rights to use, copy, modify, merge, publish, distribute, sublicense,\n * and/or sell copies of the Software, and to permit persons to whom the\n * Software is furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n * DEALINGS IN THE SOFTWARE.\n */\n\n#include <errno.h>\n#include <stdio.h>\n#include \"EchoIndication.h\"\n#include \"EchoRequest.h\"\n#include \"GeneratedTypes.h\"\n\nstatic EchoRequestProxy *echoRequestProxy = 0;\nstatic sem_t sem_heard2;\n\nclass EchoIndication : public EchoIndicationWrapper\n{\npublic:\n    virtual void heard(uint32_t v) {\n        printf(\"heard an echo: %d\\n\", v);\n\techoRequestProxy->say2(v, 2*v);\n    }\n    virtual void heard2(uint16_t a, uint16_t b) {\n        sem_post(&sem_heard2);\n        //printf(\"heard an echo2: %ld %ld\\n\", a, b);\n    }\n    EchoIndication(unsigned int id) : EchoIndicationWrapper(id) {}\n};\n\nstatic void call_say(int v)\n{\n    printf(\"[%s:%d] %d\\n\", __FUNCTION__, __LINE__, v);\n    echoRequestProxy->say(v);\n    sem_wait(&sem_heard2);\n}\n\nstatic void call_say2(int v, int v2)\n{\n    echoRequestProxy->say2(v, v2);\n    sem_wait(&sem_heard2);\n}\n\nint main(int argc, const char **argv)\n{\n    long actualFrequency = 0;\n    long requestedFrequency = 1e9 / MainClockPeriod;\n\n    EchoIndication echoIndication(IfcNames_EchoIndicationH2S);\n    echoRequestProxy = new EchoRequestProxy(IfcNames_EchoRequestS2H);\n\n    int status = setClockFrequency(0, requestedFrequency, &actualFrequency);\n    fprintf(stderr, \"Requested main clock frequency %5.2f, actual clock frequency %5.2f MHz status=%d errno=%d\\n\",\n\t    (double)requestedFrequency * 1.0e-6,\n\t    (double)actualFrequency * 1.0e-6,\n\t    status, (status != 0) ? errno : 0);\n\n    int v = 42;\n    printf(\"Saying %d\\n\", v);\n    call_say(v);\n    call_say(v*5);\n    call_say(v*17);\n    call_say(v*93);\n    call_say2(v, v*3);\n    printf(\"TEST TYPE: SEM\\n\");\n    echoRequestProxy->setLeds(9);\n    return 0;\n}\n"
  },
  {
    "path": "tests/pcie-debug/Makefile",
    "content": "CONNECTALDIR?=../..\nS2H_INTERFACES = EchoRequest:TracePcie.request ChangeRequest:TracePcie.changeRequest\nH2S_INTERFACES = TracePcie:ChangeIndication:host TracePcie:EchoIndication \n\nBSVFILES = TracePcie.bsv\nCPPFILES= tracepcie.cpp\n\nCONNECTALFLAGS += -D TRACE_PORTAL\n\nCONNECTALFLAGS += -D IMPORT_HOSTIF -D PCIE_CHANGES_HOSTIF -D TracePcieStateMachine\nCONNECTALFLAGS += -D PCIE_CHANGES_SERIAL \nCONNECTALFLAGS += -D PCIE_CHANGES_UART\nCONNECTALFLAGS += -D PCIE_ALT_BRAM_SERVER -D PCIE_TRACE_PORT\nPINOUT_FILE += pin_translation.json\nPIN_TYPE = TestPins\nPIN_TYPE_INCLUDE = TestPins\nAUTOTOP = --interface pins:TracePcie.pins\n\ninclude $(CONNECTALDIR)/Makefile.connectal\n\n"
  },
  {
    "path": "tests/pcie-debug/TestPins.bsv",
    "content": "import Clocks::*;\n\n(* always_ready, always_enabled *)\ninterface UartPins;\n   method Bit#(1) sout();\n   method Action sin(Bit#(1) v);\n   interface Clock deleteme_unused_clock;\nendinterface\ninterface TestPins;\n   interface UartPins uart;\nendinterface\n"
  },
  {
    "path": "tests/pcie-debug/TracePcie.bsv",
    "content": "// Copyright (c) 2013 Nokia, Inc.\n// Copyright (c) 2013 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\n`include \"ConnectalProjectConfig.bsv\"\n\nimport FIFO::*;\nimport FIFOF::*;\nimport Vector::*;\n`ifdef PCIE_CHANGES_HOSTIF\nimport BuildVector::*;\nimport ClientServer::*;\nimport BRAM::*;\nimport Clocks::*;\nimport GetPut::*;\nimport Pipe::*;\nimport Probe::*;\nimport HostInterface::*;\nimport Gearbox::*;\nimport RS232::*;\nimport TestPins::*;\nimport PcieTracer::*;\n`ifdef PCIE3\nimport Pcie3EndpointX7::*;\n`else\nimport PcieStateChanges::*;\n`endif\n\ninterface ChangeRequest;\n   method Action setDivisor(Bit#(16) v);\n   method Action putchar(Bit#(8) c);\nendinterface\n\ninterface ChangeIndication;\n   method Action change(Bit#(32) timestamp, Bit#(8) src, Bit#(24) value);\n   method Action changeByte(Bit#(8) c);\nendinterface\n`endif\n\n// these are here so the app can drive some traffic\ninterface EchoIndication;\n    method Action heard(Bit#(32) v);\n    method Action heard2(Bit#(16) a, Bit#(16) b);\nendinterface\n\ninterface EchoRequest;\n   method Action say(Bit#(32) v);\n   method Action say2(Bit#(16) a, Bit#(16) b);\n   method Action setLeds(Bit#(8) v);\nendinterface\n\ninterface TracePcie;\n   interface EchoRequest request;\n   interface ChangeRequest changeRequest;\n`ifdef PCIE_CHANGES_UART\n   interface TestPins pins;\n`endif\nendinterface\n\ntypedef struct {\n\tBit#(16) a;\n\tBit#(16) b;\n} EchoPair deriving (Bits);\n\n\n(* synthesize *)\nmodule mkTraceGearbox(Gearbox#(TAdd#(TMul#(2,TDiv#(SizeOf#(TimestampedTlpData),8)),2), 1, Bit#(8)));\n   let clock <- exposeCurrentClock;\n   let reset <- exposeCurrentReset;\n   let gb <- mkNto1Gearbox(clock, reset, clock, reset);\n   return gb;\nendmodule\n\n\nmodule mkTracePcie#(\n`ifdef PCIE_CHANGES_HOSTIF\n   HostInterface host, ChangeIndication changeIndication,\n`endif\n   EchoIndication indication\n)(TracePcie);\n    FIFO#(Bit#(32)) delay <- mkSizedFIFO(8);\n    FIFO#(EchoPair) delay2 <- mkSizedFIFO(8);\n\n    rule heard;\n        delay.deq;\n        indication.heard(delay.first);\n    endrule\n\n    rule heard2;\n        delay2.deq;\n        indication.heard2(delay2.first.b, delay2.first.a);\n    endrule\n   \n`ifdef PCIE_CHANGES_HOSTIF\n`ifdef PCIE_CHANGES_SERIAL\n   let clock <- exposeCurrentClock;\n   let reset <- exposeCurrentReset;\n   Gearbox#(18, 1, Bit#(8)) serializeGearbox <- mkNto1Gearbox(clock, reset, clock, reset); \n\n`ifdef PCIE_CHANGES_UART\n    Reg#(Bit#(16)) uartDivisor <- mkReg(136);\n    UART#(128) uart <- mkUART(8, NONE, STOP_1, uartDivisor);\n`endif\n\n   function Bit#(8) toHex(Bit#(4) v);\n       if (v >= 0 && v <= 9)\n\t  return 48 + zeroExtend(v);\n       else\n\t  return 97 + zeroExtend(v) - 10;\n   endfunction\n\n   function Vector#(TMul#(2,len),Bit#(8)) toHexVector(Vector#(len, Bit#(8)) bytes);\n      Vector#(TMul#(2,len),Bit#(8)) chars;\n      for (Integer i = 0; i < valueOf(len); i = i + 1) begin\n\t chars[2 * i + 0] = toHex(bytes[i][3:0]);\n\t chars[2 * i + 1] = toHex(bytes[i][7:4]);\n      end\n      return chars;\n   endfunction\n\n   Vector#(2, Bit#(8)) endl = vec(10, 13);\n\n   rule rl_changes;\n      Bit#(64) bits <- toGet(host.tchanges).get();\n      Vector#(8, Bit#(8)) bytes = unpack(bits);\n      Vector#(18, Bit#(8)) chars = append(reverse(toHexVector(bytes)), endl);\n      serializeGearbox.enq(chars);\n   endrule\n\n`ifdef DISABLE\n   rule rl_serial;\n      Bit#(8) char = serializeGearbox.first()[0];\n      serializeGearbox.deq();\n`ifndef PCIE_CHANGES_UART\n      changeIndication.changeByte(char);\n`else\n\t uart.rx.put(char);\n`endif\n   endrule\n`endif\n\n   Reg#(Bit#(12)) traceAddrReg <- mkReg(0);\n   Reg#(Bool) requested <- mkReg(False);\n   Gearbox#(TAdd#(TMul#(2,TDiv#(SizeOf#(TimestampedTlpData),8)),2), 1, Bit#(8)) testGearbox <- mkTraceGearbox();\n   Gearbox#(TAdd#(TMul#(2,TDiv#(SizeOf#(TimestampedTlpData),8)),2), 1, Bit#(8)) traceGearbox <- mkTraceGearbox();\n   FIFOF#(Bit#(8)) testFifo <- mkFIFOF();\n   FIFOF#(Bit#(8)) traceFifo <- mkFIFOF();\n\n   Reg#(Bool) testPattern <- mkReg(False);\n   rule rl_testpattern if (!testPattern);\n      testPattern <= True;\n      Vector#(TDiv#(SizeOf#(TimestampedTlpData),8), Bit#(8)) tracebytes;\n      for (Integer i = 0; i < valueOf(TDiv#(SizeOf#(TimestampedTlpData),8)); i = i + 1) begin\n\t tracebytes[i]= fromInteger(i);\n      end\n      let bytes = append(reverse(toHexVector(tracebytes)), endl);\n      testGearbox.enq(bytes);\n   endrule\n   rule rl_test_pipeline;\n      let char = testGearbox.first()[0];\n      testGearbox.deq();\n      testFifo.enq(char);\n   endrule\n\n   rule rl_trace_from_pcie_req if (!requested && testPattern);\n      if (traceAddrReg < extend(host.tpciehost.tlpTraceBramWrAddr)) begin\n\t host.tpciehost.traceBramServer.request.put(BRAMRequest {\n\t\t\t\t\t\t\t\t write: False,\n\t\t\t\t\t\t\t\t responseOnWrite: False,\n\t\t\t\t\t\t\t\t address: traceAddrReg,\n\t\t\t\t\t\t\t\t datain: ? });\n\t requested <= True;\n      end\n   endrule\n   rule rl_trace_from_pcie_resp if (requested);\n      let resp <- host.tpciehost.traceBramServer.response.get();\n      Bit#(SizeOf#(TimestampedTlpData)) tracebits = pack(resp);\n      Vector#(TDiv#(SizeOf#(TimestampedTlpData),8), Bit#(8)) tracebytes = unpack(tracebits);\n      let bytes = append(reverse(toHexVector(tracebytes)), endl);\n      // wait until there is a valid entry\n      if (True) begin\n\t traceGearbox.enq(bytes);\n\t traceAddrReg <= traceAddrReg + 1;\n      end\n      requested <= False;\n   endrule\n   rule rl_trace_pipeline;\n      let char = traceGearbox.first()[0];\n      traceGearbox.deq();\n      traceFifo.enq(char);\n   endrule\n   rule rl_trace_serial;\n      if (testFifo.notEmpty()) begin\n\t Bit#(8) char = testFifo.first();\n\t testFifo.deq();\n\t uart.rx.put(char);\n      end\n      else if (traceFifo.notEmpty()) begin\n\t Bit#(8) char = traceFifo.first();\n\t traceFifo.deq();\n\t uart.rx.put(char);\n      end\n   endrule\n\n`else\n   rule rl_changes;\n      Bit#(64) bits <- toGet(host.tchanges).get();\n      RegChange change = unpack(bits);\n      changeIndication.change(change.timestamp, change.src, change.value);\n   endrule\n`endif\n\n\n`endif\n\n`ifdef PCIE_CHANGES_UART\n   interface TestPins pins;\n      interface UartPins uart;\n\t method sin = uart.rs232.sin;\n\t method sout = uart.rs232.sout;\n\t interface Clock deleteme_unused_clock = clock;\n      endinterface\n   endinterface\n\n   interface ChangeRequest changeRequest;\n      method Action setDivisor(Bit#(16) v);\n         uartDivisor <= v;\n      endmethod\n      method Action putchar(Bit#(8) c);\n\t uart.rx.put(c);\n      endmethod\n   endinterface\n\n`endif\n\n   interface EchoRequest request;\n      method Action say(Bit#(32) v);\n\t delay.enq(v);\n      endmethod\n      \n      method Action say2(Bit#(16) a, Bit#(16) b);\n\t delay2.enq(EchoPair { a: a, b: b});\n      endmethod\n      \n      method Action setLeds(Bit#(8) v);\n      endmethod\n   endinterface\nendmodule\n"
  },
  {
    "path": "tests/pcie-debug/pin_translation.json",
    "content": "{\n    \"uart_sout\": {\n        \"uart\": \"d_out\"\n    },\n    \"uart_sin_v\": {\n        \"uart\": \"d_in\"\n    }\n}\n"
  },
  {
    "path": "tests/pcie-debug/tracepcie.cpp",
    "content": "/* Copyright (c) 2014 Quanta Research Cambridge, Inc\n *\n * Permission is hereby granted, free of charge, to any person obtaining a\n * copy of this software and associated documentation files (the \"Software\"),\n * to deal in the Software without restriction, including without limitation\n * the rights to use, copy, modify, merge, publish, distribute, sublicense,\n * and/or sell copies of the Software, and to permit persons to whom the\n * Software is furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n * DEALINGS IN THE SOFTWARE.\n */\n\n#include <errno.h>\n#include <stdio.h>\n#include \"ChangeRequest.h\"\n#include \"ChangeIndication.h\"\n#include \"EchoIndication.h\"\n#include \"EchoRequest.h\"\n#include \"GeneratedTypes.h\"\n\nstatic EchoRequestProxy *echoRequestProxy = 0;\nstatic ChangeRequestProxy *changeRequestProxy = 0;\nstatic sem_t sem_heard2;\n\nclass EchoIndication : public EchoIndicationWrapper\n{\npublic:\n    virtual void heard(uint32_t v) {\n        printf(\"heard an echo: %d\\n\", v);\n\techoRequestProxy->say2(v, 2*v);\n    }\n    virtual void heard2(uint16_t a, uint16_t b) {\n        sem_post(&sem_heard2);\n        //printf(\"heard an echo2: %ld %ld\\n\", a, b);\n    }\n    EchoIndication(unsigned int id) : EchoIndicationWrapper(id) {}\n};\n\nclass ChangeIndication : public ChangeIndicationWrapper\n{\npublic:\n    virtual void change(uint32_t timestamp, uint8_t src, uint32_t value) {\n      fprintf(stderr, \"PCIE change at %08d: src=%#x value=%#04x\\n\", timestamp, src, value);\n    }\n    virtual void changeByte(uint8_t c) {\n      fputc(c, stderr);\n    }\n    ChangeIndication(unsigned int id) : ChangeIndicationWrapper(id) {}\n};\n\nstatic void call_say(int v)\n{\n    printf(\"[%s:%d] %d\\n\", __FUNCTION__, __LINE__, v);\n    echoRequestProxy->say(v);\n    sem_wait(&sem_heard2);\n}\n\nstatic void call_say2(int v, int v2)\n{\n    echoRequestProxy->say2(v, v2);\n    sem_wait(&sem_heard2);\n}\n\nint main(int argc, const char **argv)\n{\n    long actualFrequency = 0;\n    long requestedFrequency = 1e9 / MainClockPeriod;\n\n    EchoIndication echoIndication(IfcNames_EchoIndicationH2S);\n    echoRequestProxy = new EchoRequestProxy(IfcNames_EchoRequestS2H);\n    changeRequestProxy = new ChangeRequestProxy(IfcNames_ChangeRequestS2H);\n\n    ChangeIndication changeIndication(IfcNames_ChangeIndicationH2S);\n\n    int status = setClockFrequency(0, requestedFrequency, &actualFrequency);\n    fprintf(stderr, \"Requested main clock frequency %5.2f, actual clock frequency %5.2f MHz status=%d errno=%d\\n\",\n\t    (double)requestedFrequency * 1.0e-6,\n\t    (double)actualFrequency * 1.0e-6,\n\t    status, (status != 0) ? errno : 0);\n\n    int v = 42;\n    const char *msg = \"Hello World\\n\";\n    for (unsigned int i = 0; i < strlen(msg); i++) {\n      changeRequestProxy->putchar(msg[i]);\n    }\n    printf(\"Saying %d\\n\", v);\n    call_say(v);\n    call_say(v*5);\n    call_say(v*17);\n    call_say(v*93);\n    call_say2(v, v*3);\n    printf(\"TEST TYPE: SEM\\n\");\n    echoRequestProxy->setLeds(9);\n    return 0;\n}\n"
  },
  {
    "path": "tests/pciememcheck/CheckMPM.bsv",
    "content": "\nimport BRAM         :: *;\nimport Connectable  :: *;\nimport DefaultValue :: *;\nimport FIFO         :: *;\nimport GetPut       :: *;\nimport PCIE         :: *;\nimport StmtFSM      :: *;\nimport Vector       :: *;\n\nimport BlueCheck         :: *;\nimport ConnectalMemTypes :: *;\nimport PcieToMem         :: *;\nimport PcieTracer        :: *;\nimport PhysMemSlaveFromBram :: *;\nimport MemToPcie         :: *;\n\nmodule mkRefMem(PhysMemSlave#(32, 32));\n   BRAM_Configure cfg = defaultValue;\n   cfg.memorySize = 32*1024;\n   BRAM1Port#(Bit#(32), Bit#(32)) bramPort <- mkBRAM1Server(cfg);\n   BRAMServer#(Bit#(32), Bit#(32)) br = bramPort.portA;\n   PhysMemSlave#(32, 32) bramPhysMem <- mkPhysMemSlaveFromBram(br);\n   return bramPhysMem;\nendmodule\n\nmodule mkMemToPcieToMem(PhysMemSlave#(40, 32));\n   PciId my_id = defaultValue;\n   MemToPcie#(32) memToPcie <- mkMemToPcie(my_id);\n   PcieToMem pcieToMem <- mkPcieToMem(my_id);\n   BRAM_Configure cfg = defaultValue;\n   cfg.memorySize = 32*1024;\n   BRAM1Port#(Bit#(32), Bit#(32)) bramPort <- mkBRAM1Server(cfg);\n   BRAMServer#(Bit#(32), Bit#(32)) br = bramPort.portA;\n   PhysMemSlave#(32, 32) bramPhysMem <- mkPhysMemSlaveFromBram(br);\n   //mkConnection(memToPcie.tlp.request, pcieToMem.tlp.response);\n   //mkConnection(memToPcie.tlp.response, pcieToMem.tlp.request);\n   //mkConnection(pcieToMem.master, bramPhysMem);\n\n   let fhandle <- mkReg(InvalidFile);\n   let didOnce <- mkReg(False);\n   rule once if (!didOnce);\n      //let mcd <- $fopen(\"pcielog.txt\", \"w\");\n      //fhandle <= mcd;\n      didOnce <= True;\n   endrule\n\n   Reg#(Bit#(32)) cycles <- mkReg(0);\n   rule rl_cycles;\n      cycles <= cycles + 1;\n   endrule\n   rule rl_to_bram;\n      let tlp <- memToPcie.tlp.request.get();\n      pcieToMem.tlp.response.put(tlp);\n      TimestampedTlpData ttd = TimestampedTlpData { tlp: tlp, source: 4, timestamp: cycles };\n      //$fwriteh(fhandle, ttd);\n      $display(\"tracetb %h\", ttd);\n   endrule\n   rule rl_from_bram;\n      let tlp <- pcieToMem.tlp.request.get();\n      memToPcie.tlp.response.put(tlp);\n      TimestampedTlpData ttd = TimestampedTlpData { tlp: tlp, source: 8, timestamp: cycles };\n      //$fwriteh(fhandle, ttd);\n      $display(\"tracefb %h\", ttd);\n   endrule\n\n   rule rl_rd_addr;\n      let req <- pcieToMem.master.read_client.readReq.get();\n      bramPhysMem.read_server.readReq.put(req);\n      $display(\"impl read %x tag %x\", req.addr[5:2], req.tag);\n   endrule\n   rule rl_wr_addr;\n      let req <- pcieToMem.master.write_client.writeReq.get();\n      bramPhysMem.write_server.writeReq.put(req);\n      $display(\"impl write %x tag %x\", req.addr[5:2], req.tag);\n   endrule\n   rule rl_rd_data;\n      let md <- bramPhysMem.read_server.readData.get();\n      pcieToMem.master.read_client.readData.put(md);\n      $display(\"impl read data %x tag %x\", md.data, md.tag);\n   endrule\n   rule rl_wr_data;\n      let md <- pcieToMem.master.write_client.writeData.get();\n      bramPhysMem.write_server.writeData.put(md);\n      $display(\"impl write data %x tag %x\", md.data, md.tag);\n   endrule\n   rule rl_wr_done;\n      let tag <- bramPhysMem.write_server.writeDone.get();\n      pcieToMem.master.write_client.writeDone.put(tag);\n      $display(\"impl write done tag %x\", tag);\n   endrule\n   return memToPcie.slave;\nendmodule\n\ntypedef struct {\n   Bool write;\n   Bit#(12) address;\n   Bit#(32) data;\n   Bit#(MemTagSize) tag;\n   } Req deriving (Bits, Eq, FShow);\n\nmodule [BlueCheck] checkMPM(Empty);\n   let verbose = True;\n   PhysMemSlave#(32, 32) refmem  <- mkRefMem();\n   PhysMemSlave#(40, 32) pciemem <- mkMemToPcieToMem();\n   FIFO#(Bool) isWriteFifo <- mkSizedFIFO(128);\n   FIFO#(Bit#(4)) doneFifo <- mkSizedFIFO(128);\n   FIFO#(Bit#(4)) addrFifo <- mkSizedFIFO(128);\n   Vector#(16, FIFO#(Bool)) scoreboard <- replicateM(mkFIFO1);\n   Vector#(16, FIFO#(Bool)) tagscoreboard <- replicateM(mkFIFO1);\n\n   let writeDataFifo <- mkSizedFIFO(128);\n   rule rl_write_data;\n      let writeData <- toGet(writeDataFifo).get();\n      refmem.write_server.writeData.put(writeData);\n      pciemem.write_server.writeData.put(writeData);\n      if (verbose) $display(\"rl_write_data %h tag %h\", writeData.data, writeData.tag);\n   endrule\n\n   rule rl_write_done;\n      let address <- toGet(doneFifo).get();\n      let reftag <- refmem.write_server.writeDone.get();\n      let pcietag <- pciemem.write_server.writeDone.get();\n      scoreboard[address].deq();\n      tagscoreboard[reftag].deq();\n      if (verbose) $display(\"reftag %x\", reftag);\n   endrule\n\n   function Action sendPhysMemReq(Bool write, Bit#(4) address, Bit#(32) data, Bit#(4) tag);\n      return (action\n\t PhysMemRequest#(32, 32) refreq = PhysMemRequest { addr: zeroExtend(address) << 2, burstLen: 4, tag: zeroExtend(tag) };\n\t PhysMemRequest#(40, 32) pciereq = PhysMemRequest { addr: zeroExtend(address) << 2, burstLen: 4, tag: zeroExtend(tag) };\n\n\t $display((write ? \"write \" : \"read \"), address, \" data \", data, \" tag \", tag);\n\n         isWriteFifo.enq(write);\n\n\tscoreboard[address].enq(True);\n\ttagscoreboard[tag].enq(True);\n\tif (write) begin\n\t   MemData#(32) writeData = MemData {data: data, tag: zeroExtend(tag), last: True };\n\t   refmem.write_server.writeReq.put(refreq);\n\t   pciemem.write_server.writeReq.put(pciereq);\n\t   writeDataFifo.enq(writeData);\n\t   doneFifo.enq(address);\n\tend\n\telse begin\n\t   refmem.read_server.readReq.put(refreq);\n\t   pciemem.read_server.readReq.put(pciereq);\n           addrFifo.enq(address);\n\tend\n   endaction);\n   endfunction\n\n   ActionValue#(Bool) checkPhysMemResp = (actionvalue\n      let isWrite <- toGet(isWriteFifo).get();\n      if (isWrite) begin\n         return True;\n      end\n      else begin\n         let address <- toGet(addrFifo).get();\n         let refresp <- refmem.read_server.readData.get();\n         let pcieresp <- pciemem.read_server.readData.get();\n         if (verbose) $display(\"refresp \", address, \" data \", refresp.data, \" tag \", refresp.tag, \" pcieresp \", pcieresp.data, \" tag \", pcieresp.tag);\n\t scoreboard[address].deq();\n         tagscoreboard[refresp.tag].deq();\n         return refresp == pcieresp;\n      end\n      endactionvalue);\n\n   prop(\"read\", sendPhysMemReq(False));\n   prop(\"write\", sendPhysMemReq(True));\n   prop(\"check\", checkPhysMemResp);\n\nendmodule\n\ninterface PcieMemChecker;\n   interface FSM fsm;\n   method Action start(Bit#(32) numIterations, Bool verbose);\n   method ActionValue#(Bool) done();\nendinterface \n\n(* synthesize *)\nmodule [Module] mkPcieMemChecker(PcieMemChecker);\n   BlueCheck_Params params = bcParams;\n   Reg#(Bit#(32)) numIterations <- mkReg(100000);\n   params.numIterations = numIterations;\n   params.verbose = True;\n   let test <- mkModelChecker(checkMPM, params);\n\n   Reg#(Bool) started <- mkReg(False);\n   let _fsm <- mkFSM(test);\n   interface fsm = _fsm;\n   method Action start(Bit#(32) numiters, Bool v) if (!started);\n      numIterations <= numiters;\n      _fsm.start();\n      started <= True;\n   endmethod\n   method ActionValue#(Bool) done() if (started && _fsm.done);\n      started <= False;\n      return True;\n   endmethod\nendmodule\n"
  },
  {
    "path": "tests/pciememcheck/Makefile",
    "content": "CONNECTALDIR?=../..\nS2H_INTERFACES = PcieMemCheckRequest:PcieMemCheck.request\nH2S_INTERFACES = PcieMemCheck:PcieMemCheckIndication\n\nBSVFILES = PcieMemCheck.bsv \nCPPFILES = pciememcheck.cpp\nCONNECTALFLAGS += -D USE_ACP -P mkConnectalTop\n\ninclude $(CONNECTALDIR)/Makefile.connectal\n"
  },
  {
    "path": "tests/pciememcheck/PcieMemCheck.bsv",
    "content": "\nimport BRAM         :: *;\nimport Connectable  :: *;\nimport GetPut       :: *;\nimport DefaultValue :: *;\nimport PCIE         :: *;\nimport StmtFSM      :: *;\n\nimport BlueCheck         :: *;\nimport CheckMPM          :: *;\nimport ConnectalMemTypes :: *;\nimport PcieToMem         :: *;\nimport PhysMemSlaveFromBram :: *;\nimport MemToPcie         :: *;\n\ninterface PcieMemCheckRequest;\n   method Action startCheck(Bit#(32) numIterations, Bool verbose);\nendinterface\ninterface PcieMemCheckIndication;\n   method Action checkFinished();\nendinterface\n\ninterface PcieMemCheck;\n   interface PcieMemCheckRequest request;\nendinterface\n\nmodule [Module] mkPcieMemCheck#(PcieMemCheckIndication ind)(PcieMemCheck);\n   PcieMemChecker checker <- mkPcieMemChecker();\n\n   rule rl_done;\n      let done <- checker.done();\n      ind.checkFinished();\n   endrule\n\n   interface PcieMemCheckRequest request;\n      method Action startCheck(Bit#(32) numIterations, Bool verbose);\n\t checker.start(numIterations, verbose);\n      endmethod\n   endinterface\nendmodule\n"
  },
  {
    "path": "tests/pciememcheck/pciememcheck.cpp",
    "content": "\n#include <getopt.h>\n#include <stdlib.h>\n\n#include <GeneratedTypes.h>\n#include <PcieMemCheckIndication.h>\n#include <PcieMemCheckRequest.h>\n\nvolatile int done = 0;\nclass PcieMemCheckIndication : public PcieMemCheckIndicationWrapper {\npublic:\n    virtual void checkFinished() {\n\tfprintf(stderr, \"finished\\n\");\n\tdone = 1;\n    }\n    PcieMemCheckIndication(unsigned int id) : PcieMemCheckIndicationWrapper(id) {}\n};\n\nint main(int argc, char* const*argv)\n{\n    int opt;\n    int numIterations = 100000;\n    int verbose = 0;\n    while ((opt = getopt(argc, argv, \"n:v\")) != -1) {\n        switch (opt) {\n\tcase 'n':\n\t    numIterations = strtoul(optarg, 0, 0);\n\t    break;\n\tcase 'v':\n            verbose = 1;\n\t    break;\n        }\n    }\n    fprintf(stderr, \"numIterations=%d\\n\", numIterations);\n    PcieMemCheckRequestProxy *request = new PcieMemCheckRequestProxy(IfcNames_PcieMemCheckRequestS2H);\n    request->startCheck(numIterations, verbose);\n    while (!done) {\n        sleep(1);\n    }\n    return 0;\n}\n"
  },
  {
    "path": "tests/physmaster/Echo.bsv",
    "content": "\n// Copyright (c) 2013 Nokia, Inc.\n// Copyright (c) 2013 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\ninterface EchoIndication;\n    method Action heard(Bit#(32) v);\n    method Action heard2(Bit#(16) a, Bit#(16) b);\nendinterface\n\ninterface EchoRequest;\n   method Action say(Bit#(32) v);\n   method Action say2(Bit#(16) a, Bit#(16) b);\n   method Action setLeds(Bit#(8) v);\nendinterface\n"
  },
  {
    "path": "tests/physmaster/Makefile",
    "content": "CONNECTALDIR?=../..\nINTERFACES = EchoRequest EchoIndication PhysMemMasterRequest PhysMemMasterIndication\n\nBSVFILES = Echo.bsv PhysReq.bsv\nCPPFILES=daemon.cpp\nCPPFILES2=testecho.cpp\nCONNECTALFLAGS += --nohardware\nAUTOTOP= --portname IfcNames_PhysMemMasterIndication --portname IfcNames_PhysMemMasterRequest\n\ninclude $(CONNECTALDIR)/Makefile.connectal\n"
  },
  {
    "path": "tests/physmaster/PhysReq.bsv",
    "content": "/* Copyright (c) 2014 Quanta Research Cambridge, Inc\n *\n * Permission is hereby granted, free of charge, to any person obtaining a\n * copy of this software and associated documentation files (the \"Software\"),\n * to deal in the Software without restriction, including without limitation\n * the rights to use, copy, modify, merge, publish, distribute, sublicense,\n * and/or sell copies of the Software, and to permit persons to whom the\n * Software is furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n * DEALINGS IN THE SOFTWARE.\n */\n\nimport ConnectalMemTypes::*;\n\ntypedef 6 MemTagSize;\ntypedef 40 PhysAddrWidth;\ntypedef 10 BurstLenSize;\ntypedef 64 DataBusWidth;\n\ntypedef struct {\n   Bit#(addrWidth) addr;\n   Bit#(BurstLenSize) burstLen;\n   Bit#(MemTagSize) tag;\n   } PhysMemRequest#(numeric type addrWidth) deriving (Bits);\n\ntypedef struct {\n   Bit#(dsz) data;\n   Bit#(MemTagSize) tag;\n   Bool last;\n   } MemData#(numeric type dsz) deriving (Bits);\n\ninterface PhysMemMasterRequest;\n   method Action readReq(PhysMemRequest#(PhysAddrWidth) v);\n   method Action writeReq(PhysMemRequest#(PhysAddrWidth) v);\n   method Action writeData(MemData#(DataBusWidth) v);\nendinterface\n\ninterface PhysMemMasterIndication;\n   method Action readData(MemData#(DataBusWidth) v);\n   method Action writeDone(Bit#(MemTagSize) v);\nendinterface\n"
  },
  {
    "path": "tests/physmaster/daemon.cpp",
    "content": "/* Copyright (c) 2014 Quanta Research Cambridge, Inc\n *\n * Permission is hereby granted, free of charge, to any person obtaining a\n * copy of this software and associated documentation files (the \"Software\"),\n * to deal in the Software without restriction, including without limitation\n * the rights to use, copy, modify, merge, publish, distribute, sublicense,\n * and/or sell copies of the Software, and to permit persons to whom the\n * Software is furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n * DEALINGS IN THE SOFTWARE.\n */\n#include \"PhysMemMasterRequest.h\"\n#include \"PhysMemMasterIndication.h\"\n\nPhysMemMasterIndicationProxy *sIndicationProxy;\nstatic int daemon_trace = 1;\n\nclass PhysMemMasterRequest : public PhysMemMasterRequestWrapper\n{\npublic:\n    void readReq (  const PhysMemRequestL_PhysAddrWidth_P v ) {\n        if (daemon_trace)\n        fprintf(stderr, \"daemon[%s:%d]\\n\", __FUNCTION__, __LINE__);\n        //sIndicationProxy->heard(v);\n    }\n    void writeReq (  const PhysMemRequestL_PhysAddrWidth_P v ) {\n        if (daemon_trace)\n        fprintf(stderr, \"daemon[%s:%d]\\n\", __FUNCTION__, __LINE__);\n        //sIndicationProxy->heard2(a, b);\n    }\n    void writeData (  const MemDataL_DataBusWidth_P v ) {\n        fprintf(stderr, \"daemon[%s:%d]\\n\", __FUNCTION__, __LINE__);\n        sleep(1);\n        exit(1);\n    }\n    void disconnect (void) {\n        fprintf(stderr, \"daemon[%s:%d]\\n\", __FUNCTION__, __LINE__);\n        sleep(1);\n        exit(1);\n    }\n    PhysMemMasterRequest(unsigned int id, PortalTransportFunctions *item, void *param) : PhysMemMasterRequestWrapper(id, item, param) {}\n};\n\nint main(int argc, const char **argv)\n{\n    sIndicationProxy = new PhysMemMasterIndicationProxy(IfcNames_PhysMemMasterIndication, &transportSocketResp, NULL);\n    PhysMemMasterRequest sRequest(IfcNames_PhysMemMasterRequest, &transportSocketResp, NULL);\n\n    printf(\"[%s:%d] daemon sleeping...\\n\", __FUNCTION__, __LINE__);\n    while(1)\n        sleep(100);\n    return 0;\n}\n"
  },
  {
    "path": "tests/physmaster/testecho.cpp",
    "content": "/* Copyright (c) 2014 Quanta Research Cambridge, Inc\n *\n * Permission is hereby granted, free of charge, to any person obtaining a\n * copy of this software and associated documentation files (the \"Software\"),\n * to deal in the Software without restriction, including without limitation\n * the rights to use, copy, modify, merge, publish, distribute, sublicense,\n * and/or sell copies of the Software, and to permit persons to whom the\n * Software is furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n * DEALINGS IN THE SOFTWARE.\n */\n#include \"PhysMemMasterRequest.h\"\n#include \"PhysMemMasterIndication.h\"\n\nPhysMemMasterRequestProxy *sRequestProxy;\nstatic sem_t sem_heard2;\n\nclass PhysMemMasterIndication : public PhysMemMasterIndicationWrapper\n{\npublic:\n    void readData (  const MemDataL_DataBusWidth_P v ) {\n        fprintf(stderr, \"heard an s: %lld\\n\", (long long)v.data);\n\t//sRequestProxy->say2(v, 2*v);\n    }\n    void writeDone (  const uint8_t v ) {\n        sem_post(&sem_heard2);\n        //fprintf(stderr, \"heard an s2: %ld %ld\\n\", a, b);\n    }\n    PhysMemMasterIndication(unsigned int id, PortalTransportFunctions *item, void *param) : PhysMemMasterIndicationWrapper(id, item, param) {}\n};\n\n    //sem_wait(&sem_heard2);\n\nint main(int argc, const char **argv)\n{\n    PhysMemMasterIndication sIndication(IfcNames_PhysMemMasterIndication, &transportSocketInit, NULL);\n    sRequestProxy = new PhysMemMasterRequestProxy(IfcNames_PhysMemMasterRequest, &transportSocketInit, NULL);\n\n    int v = 42;\n    fprintf(stderr, \"Saying %d\\n\", v);\n    //call_say(v);\n    portal_disconnect(&sRequestProxy->pint);\n    return 0;\n}\n"
  },
  {
    "path": "tests/qemuaccel/AccelIfcNames.bsv",
    "content": "\ntypedef enum {AccelIfcNamesNone=0,\nPlatformAccelIfcNames_MemServerRequestS2H=1,\nPlatformAccelIfcNames_MMURequestS2H=2,\nPlatformAccelIfcNames_MemServerIndicationH2S=3,\nPlatformAccelIfcNames_MMUIndicationH2S=4,\nAccelIfcNames_SerialIndicationH2S=5,\nAccelIfcNames_SimpleRequestH2S=6,\nAccelIfcNames_BlockDevResponseH2S=7,\nAccelIfcNames_SerialRequestS2H=8,\nAccelIfcNames_SimpleRequestS2H=9,\nAccelIfcNames_BlockDevRequestS2H=10\n} AccelIfcNames deriving (Eq,Bits);\n"
  },
  {
    "path": "tests/qemuaccel/AccelTop.bsv",
    "content": "`include \"ConnectalProjectConfig.bsv\"\n\nimport ConnectalConfig::*;\nimport Vector::*;\nimport BuildVector::*;\nimport Portal::*;\nimport CtrlMux::*;\nimport HostInterface::*;\nimport Connectable::*;\nimport MemReadEngine::*;\nimport MemWriteEngine::*;\nimport ConnectalMemTypes::*;\nimport MemServer::*;\nimport AccelIfcNames::*;\n`ifdef PinTypeInclude\nimport `PinTypeInclude::*;\n`endif\nimport SerialIndication::*;\nimport Serial::*;\nimport SimpleRequest::*;\nimport Simple::*;\nimport BlockDevResponse::*;\nimport BlockDev::*;\nimport SerialRequest::*;\nimport SimpleRequest::*;\nimport BlockDevRequest::*;\n\ninterface Pins;\n     interface SerialPort pins0;\n\n    interface BlockDevClient pins1;\n endinterface\n\n\n`ifndef IMPORT_HOSTIF\n(* synthesize *)\n`endif\nmodule mkAccelTop\n`ifdef IMPORT_HOSTIF // no synthesis boundary\n      #(HostInterface host)\n`else\n`ifdef IMPORT_HOST_CLOCKS // enables synthesis boundary\n       #(Clock derivedClockIn, Reset derivedResetIn)\n`else\n// otherwise no params\n`endif\n`endif\n       (ConnectalTop#(Pins));\n   Clock defaultClock <- exposeCurrentClock();\n   Reset defaultReset <- exposeCurrentReset();\n`ifdef IMPORT_HOST_CLOCKS // enables synthesis boundary\n   HostInterface host = (interface HostInterface;\n                           interface Clock derivedClock = derivedClockIn;\n                           interface Reset derivedReset = derivedResetIn;\n                         endinterface);\n`endif\n   BlockDevRequestInput lBlockDevRequestInput <- mkBlockDevRequestInput;\n   BlockDevResponseOutput lBlockDevResponseOutput <- mkBlockDevResponseOutput;\n   SerialIndicationOutput lSerialIndicationOutput <- mkSerialIndicationOutput;\n   SerialRequestInput lSerialRequestInput <- mkSerialRequestInput;\n   SimpleRequestInput lSimpleRequestInput <- mkSimpleRequestInput;\n   SimpleRequestOutput lSimpleRequestOutput <- mkSimpleRequestOutput;\n\n   Serial lSerial <- mkSerial(lSerialIndicationOutput.ifc);\n\n   Simple lSimple <- mkSimple(lSimpleRequestOutput.ifc);\n\n   BlockDev lBlockDev <- mkBlockDev(lBlockDevResponseOutput.ifc);\n\n   mkConnection(lBlockDevRequestInput.pipes, lBlockDev.request);\n   mkConnection(lSerialRequestInput.pipes, lSerial.request);\n   mkConnection(lSimpleRequestInput.pipes, lSimple.request);\n\n   Vector#(6,StdPortal) portals;\n   PortalCtrlMemSlave#(SlaveControlAddrWidth,SlaveDataBusWidth) ctrlPort_0 <- mkPortalCtrlMemSlave(extend(pack(AccelIfcNames_SerialIndicationH2S)), lSerialIndicationOutput.portalIfc.intr);\n   let memslave_0 <- mkMemMethodMuxOut(ctrlPort_0.memSlave,lSerialIndicationOutput.portalIfc.indications);\n   portals[0] = (interface MemPortal;\n       interface PhysMemSlave slave = memslave_0;\n       interface ReadOnly interrupt = ctrlPort_0.interrupt;\n       interface WriteOnly num_portals = ctrlPort_0.num_portals;\n       endinterface);\n   PortalCtrlMemSlave#(SlaveControlAddrWidth,SlaveDataBusWidth) ctrlPort_1 <- mkPortalCtrlMemSlave(extend(pack(AccelIfcNames_SimpleRequestH2S)), lSimpleRequestOutput.portalIfc.intr);\n   let memslave_1 <- mkMemMethodMuxOut(ctrlPort_1.memSlave,lSimpleRequestOutput.portalIfc.indications);\n   portals[1] = (interface MemPortal;\n       interface PhysMemSlave slave = memslave_1;\n       interface ReadOnly interrupt = ctrlPort_1.interrupt;\n       interface WriteOnly num_portals = ctrlPort_1.num_portals;\n       endinterface);\n   PortalCtrlMemSlave#(SlaveControlAddrWidth,SlaveDataBusWidth) ctrlPort_2 <- mkPortalCtrlMemSlave(extend(pack(AccelIfcNames_BlockDevResponseH2S)), lBlockDevResponseOutput.portalIfc.intr);\n   let memslave_2 <- mkMemMethodMuxOut(ctrlPort_2.memSlave,lBlockDevResponseOutput.portalIfc.indications);\n   portals[2] = (interface MemPortal;\n       interface PhysMemSlave slave = memslave_2;\n       interface ReadOnly interrupt = ctrlPort_2.interrupt;\n       interface WriteOnly num_portals = ctrlPort_2.num_portals;\n       endinterface);\n   PortalCtrlMemSlave#(SlaveControlAddrWidth,SlaveDataBusWidth) ctrlPort_3 <- mkPortalCtrlMemSlave(extend(pack(AccelIfcNames_SerialRequestS2H)), lSerialRequestInput.portalIfc.intr);\n   let memslave_3 <- mkMemMethodMuxIn(ctrlPort_3.memSlave,lSerialRequestInput.portalIfc.requests);\n   portals[3] = (interface MemPortal;\n       interface PhysMemSlave slave = memslave_3;\n       interface ReadOnly interrupt = ctrlPort_3.interrupt;\n       interface WriteOnly num_portals = ctrlPort_3.num_portals;\n       endinterface);\n   PortalCtrlMemSlave#(SlaveControlAddrWidth,SlaveDataBusWidth) ctrlPort_4 <- mkPortalCtrlMemSlave(extend(pack(AccelIfcNames_SimpleRequestS2H)), lSimpleRequestInput.portalIfc.intr);\n   let memslave_4 <- mkMemMethodMuxIn(ctrlPort_4.memSlave,lSimpleRequestInput.portalIfc.requests);\n   portals[4] = (interface MemPortal;\n       interface PhysMemSlave slave = memslave_4;\n       interface ReadOnly interrupt = ctrlPort_4.interrupt;\n       interface WriteOnly num_portals = ctrlPort_4.num_portals;\n       endinterface);\n   PortalCtrlMemSlave#(SlaveControlAddrWidth,SlaveDataBusWidth) ctrlPort_5 <- mkPortalCtrlMemSlave(extend(pack(AccelIfcNames_BlockDevRequestS2H)), lBlockDevRequestInput.portalIfc.intr);\n   let memslave_5 <- mkMemMethodMuxIn(ctrlPort_5.memSlave,lBlockDevRequestInput.portalIfc.requests);\n   portals[5] = (interface MemPortal;\n       interface PhysMemSlave slave = memslave_5;\n       interface ReadOnly interrupt = ctrlPort_5.interrupt;\n       interface WriteOnly num_portals = ctrlPort_5.num_portals;\n       endinterface);\n   let ctrl_mux <- mkSlaveMux(portals);\n   Vector#(NumWriteClients,MemWriteClient#(DataBusWidth)) nullWriters = replicate(null_mem_write_client());\n   Vector#(NumReadClients,MemReadClient#(DataBusWidth)) nullReaders = replicate(null_mem_read_client());\n   interface interrupt = getInterruptVector(portals);\n   interface slave = ctrl_mux;\n   interface readers = take(nullReaders);\n   interface writers = take(nullWriters);\n`ifdef TOP_SOURCES_PORTAL_CLOCK\n   interface portalClockSource = None;\n`endif\n\n   interface Pins pins;\n      interface pins0 = lSerial.port;\n      interface pins1 = lBlockDev.client;\n   endinterface \nendmodule : mkAccelTop\nexport mkAccelTop;\nexport `PinTypeInclude::*;\nexport Pins(..);\n"
  },
  {
    "path": "tests/qemuaccel/BlockDev.bsv",
    "content": "// Copyright (c) 2016 Connectal Project\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\ntypedef enum { BlockDevRead, BlockDevWrite } BlockDevOp deriving (Bits,Eq,FShow);\n\nimport BuildVector::*;\nimport ClientServer::*;\nimport FIFOF::*;\nimport GetPut::*;\nimport Vector::*;\n\nimport ConnectalConfig::*;\nimport ConnectalMemory::*;\nimport ConnectalMemTypes::*;\nimport MemReadEngine::*;\nimport MemWriteEngine::*;\nimport Pipe::*;\n\ninterface PortPair#(type ifc1, type ifc2);\n   interface ifc1 port1;\n   interface ifc2 port2;\nendinterface\nfunction PortPair#(ifc1, ifc2) portPair(ifc1 p1, ifc2 p2);\n   return (interface PortPair#(ifc1,ifc2);\n\t      interface port1 = p1;\n\t      interface port2 = p2;\n\t   endinterface);\nendfunction\n\ninterface BlockDevRequest;\n   method Action transfer(BlockDevOp op, Bit#(32) dramaddr, Bit#(32) offset, Bit#(32) size, Bit#(32) tag);\nendinterface\n\ninterface BlockDevResponse;\n   method Action transferDone(Bit#(32) tag);\nendinterface\n\ntypedef struct {\n   BlockDevOp op;\n   Bit#(32) dramaddr;\n   Bit#(32) offset;\n   Bit#(32) size;\n   Bit#(32) tag;\n   } BlockDevTransfer deriving (Bits,Eq,FShow);\n\ntypedef Client#(BlockDevTransfer,Bit#(32)) BlockDevClient;\n\ninterface BlockDev;\n   interface BlockDevRequest request;\n   interface BlockDevClient client;\nendinterface\n\ntypedef 1 CmdQDepth;\n\nmodule mkBlockDev#(BlockDevResponse ind)(BlockDev);\n   FIFOF#(BlockDevTransfer) requestFifo <- mkFIFOF();\n   FIFOF#(Bit#(32))        responseFifo <- mkFIFOF();\n\n   rule rl_response;\n      let response <- toGet(responseFifo).get();\n      ind.transferDone(response);\n   endrule\n\n   interface BlockDevRequest request;\n      method Action transfer(BlockDevOp op, Bit#(32) dramaddr, Bit#(32) offset, Bit#(32) size, Bit#(32) tag);\n\t requestFifo.enq(BlockDevTransfer { op: op, dramaddr: dramaddr, offset: offset, size: size, tag: tag });\n      endmethod\n   endinterface\n   interface Client client;\n      interface Get request = toGet(requestFifo);\n      interface Put response = toPut(responseFifo);\n   endinterface\nendmodule\n"
  },
  {
    "path": "tests/qemuaccel/Devices.bsv",
    "content": "import BlockDev::*;\nimport Serial::*;\nimport Simple::*;\n\ninterface DevicesPorts;\n   interface SerialPort serial;\n   interface Client#(BlockDevTransfer,Bit#(32)) blockDev;\nendinterface\n\ninterface Devices;\n   interface SimpleRequest simple;\n   interface SerialPort   serial;\n   interface BlockDevPort blockDev;\n   interface DevicesPorts ports;\nendinterface\n\nmodule mkDevices#(SimpleIndication simpleIndication,\n\t\t  SerialIndication serialIndication,\n\t\t  BlockDevResponse blockDevResponse)(Devices);\n   let simple <- mksimple(simpleIndication);\n   let serial <- mkSerial(serialIndication);\n   let blockDev <- mkBlockDev(blockDevResponse);\n\n   interface SimpleRequest simple= simple.request;\n   interface SerialPort   serial = serial.request;\n   interface BlockDevPort blockDev = blockDev.request;\n\n   interface DevicesPorts ports;\n      interface SerialPort serial = serial.port;\n      interface Client client = blockDev.client;\n   endinterface\nendmodule\n"
  },
  {
    "path": "tests/qemuaccel/Makefile",
    "content": "CONNECTALDIR?=../..\n\nINTERFACES = SimpleRequest SerialRequest SerialIndication BlockDevRequest BlockDevResponse\n\nS2H_INTERFACES = QemuAccelRequest:QemuAccel.request MemServerPortalRequest:QemuAccel.memServerPortalRequest SerialRequest:QemuAccel.uartRequest BlockDevResponse:QemuAccel.blockDevResponse\nH2S_INTERFACES = QemuAccel:QemuAccelIndication,MemServerPortalResponse,SerialIndication,BlockDevRequest\n\n#MEM_READ_INTERFACES = lQemuAccel.dmaReadClient\n#MEM_WRITE_INTERFACES = lQemuAccel.dmaWriteClient\n\nBSVFILES = $(CONNECTALDIR)/bsv/ConnectalConfig.bsv  $(CONNECTALDIR)/examples/simple/Simple.bsv $(CONNECTALDIR)/bsv/MemServerPortal.bsv AccelIfcNames.bsv QemuAccelIfc.bsv Serial.bsv BlockDev.bsv\nCPPFILES = $(CONNECTALDIR)/lib/qemu/fpgadev.cpp\n\nCONNECTALFLAGS += --bsvpath $(CONNECTALDIR)/examples/simple\nCONNECTALFLAGS += --shared\nCONNECTALFLAGS += --cxxflags=-std=c++11\n\nprebuild::\n\t$(CONNECTALDIR)/scripts/topgen.py --project-dir . --filename 'AccelTop.bsv' --topname mkAccelTop --ifcnames 'AccelIfcNames' --wrapper SerialRequest:Serial.request --wrapper SimpleRequest:Simple.request --proxy Serial:SerialIndication --proxy Simple:SimpleRequest --interface pins:Serial.port --interface pins:BlockDev.client --wrapper BlockDevRequest:BlockDev.request --proxy BlockDev:BlockDevResponse --pintype 'SerialPort' --pintype BlockDevClient\n\ninclude $(CONNECTALDIR)/Makefile.connectal\n\n"
  },
  {
    "path": "tests/qemuaccel/QemuAccel.bsv",
    "content": "\nimport GetPut::*;\nimport ClientServer::*;\n\nimport MemServerPortal::*;\nimport Pipe::*;\nimport Portal::*;\nimport Simple::*;\nimport AccelTop::*;\nimport QemuAccelIfc::*;\nimport BlockDev::*;\nimport Serial::*;\n\n\ninterface QemuAccel;\n   interface QemuAccelRequest request;\n   interface MemServerPortalRequest memServerPortalRequest;\n   interface SerialRequest uartRequest;\n   interface BlockDevResponse blockDevResponse;\nendinterface\n\nmodule mkQemuAccel#(QemuAccelIndication ind, MemServerPortalResponse memServerPortalIndication, SerialIndication uartIndication, BlockDevRequest blockDevRequest)(QemuAccel);\n\n   let accel <- AccelTop::mkAccelTop();\n   let physMemSlavePortal <- mkPhysMemSlavePortal(accel.slave, memServerPortalIndication);\n\n   rule rl_rx;\n      let ch <- toGet(accel.pins.pins0.out).get();\n      uartIndication.rx(ch);\n   endrule\n   rule rl_blockdev;\n      let req <- accel.pins.pins1.request.get();\n      blockDevRequest.transfer(req.op, req.dramaddr, req.offset, req.size, req.tag);\n   endrule\n\n   interface MemServerPortalRequest memServerPortalRequest = physMemSlavePortal.request;\n\n   interface QemuAccelRequest request;\n      method Action start();\n\t ind.started();\n      endmethod\n   endinterface\n   interface SerialRequest uartRequest;\n      method Action tx(Bit#(8) ch);\n\t accel.pins.pins0.in.enq(ch);\n      endmethod\n   endinterface\n   interface BlockDevResponse blockDevResponse;\n      method Action transferDone(Bit#(32) tag);\n\t accel.pins.pins1.response.put(tag);\n      endmethod\n   endinterface\nendmodule\n\n"
  },
  {
    "path": "tests/qemuaccel/QemuAccelIfc.bsv",
    "content": "// Copyright (c) 2016 Connectal Project\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\ninterface QemuAccelRequest;\n   method Action start();\n   method Action reset();\n   method Action status();\n   method Action setupDma(Bit#(32) objId);\nendinterface\n\ninterface QemuAccelIndication;\n   method Action started();\nendinterface\n"
  },
  {
    "path": "tests/qemuaccel/Serial.bsv",
    "content": "\nimport GetPut::*;\nimport FIFOF::*;\nimport Pipe::*;\n\ninterface SerialRequest;\n   method Action tx(Bit#(8) c);\nendinterface\n\ninterface SerialIndication;\n   method Action rx(Bit#(8) c);\nendinterface\n\ninterface SerialPort;\n   interface PipeOut#(Bit#(8)) out;\n   interface PipeIn#(Bit#(8)) in;\nendinterface   \ninterface Serial;\n   interface SerialRequest request;\n   interface SerialPort port;\nendinterface\n\nmodule mkSerial#(SerialIndication indication)(Serial);\n   FIFOF#(Bit#(8)) infifo <- mkSizedFIFOF(16);\n   FIFOF#(Bit#(8)) outfifo <- mkSizedFIFOF(16);\n   rule rl_in;\n      let ch <- toGet(infifo).get();\n      indication.rx(ch);\n   endrule\n   interface SerialRequest request;\n      method Action tx(Bit#(8) c);\n\t //$display(\"%h\", c);\n\t outfifo.enq(c);\n      endmethod\n   endinterface\n   interface SerialPort port;\n      interface PipeOut out = toPipeOut(outfifo);\n      interface PipeIn  in  = toPipeIn(infifo);\n   endinterface\nendmodule\n"
  },
  {
    "path": "tests/qemuaccel/qemuaccel.cpp",
    "content": "\n\n\nint main(int argc, const char **argv)\n{\n  return 0;\n}\n"
  },
  {
    "path": "tests/rootport/AxiPcieRootPort.bsv",
    "content": "\n/*\n   ../../generated/scripts/importbvi.py\n   -I\n   APRP\n   -P\n   APRP\n   -r\n   axi_aresetn\n   -c\n   axi_aclk_out\n   -c\n   axi_ctl_aclk_out\n   -c\n   REFCLK\n   -o\n   AxiPcieRootPort.bsv\n   /home/jamey/miniitx100/miniitx100.srcs/sources_1/ip/axi_pcie_0/axi_pcie_0_stub.v\n*/\n\nimport Clocks::*;\nimport DefaultValue::*;\nimport XilinxCells::*;\nimport GetPut::*;\nimport AxiBits::*;\n\n(* always_ready, always_enabled *)\ninterface AprpAxi;\n    interface Clock     aclk_out;\n    interface Clock     ctl_aclk_out;\nendinterface\n(* always_ready, always_enabled *)\ninterface AprpInterrupt;\n    method Bit#(1)     out();\nendinterface\n(* always_ready, always_enabled *)\ninterface AprpIntx;\n    method Bit#(1)     msi_grant();\n    method Action      msi_request(Bit#(1) v);\nendinterface\n(* always_ready, always_enabled *)\ninterface AprpM_axi;\n    method Bit#(32)     araddr();\n    method Bit#(2)     arburst();\n    method Bit#(4)     arcache();\n    method Bit#(8)     arlen();\n    method Bit#(1)     arlock();\n    method Bit#(3)     arprot();\n    method Action      arready(Bit#(1) v);\n    method Bit#(3)     arsize();\n    method Bit#(1)     arvalid();\n    method Bit#(32)     awaddr();\n    method Bit#(2)     awburst();\n    method Bit#(4)     awcache();\n    method Bit#(8)     awlen();\n    method Bit#(1)     awlock();\n    method Bit#(3)     awprot();\n    method Action      awready(Bit#(1) v);\n    method Bit#(3)     awsize();\n    method Bit#(1)     awvalid();\n    method Bit#(1)     bready();\n    method Action      bresp(Bit#(2) v);\n    method Action      bvalid(Bit#(1) v);\n    method Action      rdata(Bit#(64) v);\n    method Action      rlast(Bit#(1) v);\n    method Bit#(1)     rready();\n    method Action      rresp(Bit#(2) v);\n    method Action      rvalid(Bit#(1) v);\n    method Bit#(64)     wdata();\n    method Bit#(1)     wlast();\n    method Action      wready(Bit#(1) v);\n    method Bit#(8)     wstrb();\n    method Bit#(1)     wvalid();\nendinterface\n(* always_ready, always_enabled *)\ninterface AprpMmcm;\n    method Bit#(1)     lock();\nendinterface\n(* always_ready, always_enabled *)\ninterface AprpMsi;\n    method Bit#(1)     enable();\n    method Action      vector_num(Bit#(5) v);\n    method Bit#(3)     vector_width();\nendinterface\n(* always_ready, always_enabled *)\ninterface AprpPci;\n    method Action      exp_rxn(Bit#(4) v);\n    method Action      exp_rxp(Bit#(4) v);\n    method Bit#(4)     exp_txn();\n    method Bit#(4)     exp_txp();\nendinterface\n(* always_ready, always_enabled *)\ninterface AprpS_axi;\n    method Action      araddr(Bit#(32) v);\n    method Action      arburst(Bit#(2) v);\n    method Action      arid(Bit#(4) v);\n    method Action      arlen(Bit#(8) v);\n    method Bit#(1)     arready();\n    method Action      arregion(Bit#(4) v);\n    method Action      arsize(Bit#(3) v);\n    method Action      arvalid(Bit#(1) v);\n    method Action      awaddr(Bit#(32) v);\n    method Action      awburst(Bit#(2) v);\n    method Action      awid(Bit#(4) v);\n    method Action      awlen(Bit#(8) v);\n    method Bit#(1)     awready();\n    method Action      awregion(Bit#(4) v);\n    method Action      awsize(Bit#(3) v);\n    method Action      awvalid(Bit#(1) v);\n    method Bit#(4)     bid();\n    method Action      bready(Bit#(1) v);\n    method Bit#(2)     bresp();\n    method Bit#(1)     bvalid();\n    method Bit#(64)     rdata();\n    method Bit#(4)     rid();\n    method Bit#(1)     rlast();\n    method Action      rready(Bit#(1) v);\n    method Bit#(2)     rresp();\n    method Bit#(1)     rvalid();\n    method Action      wdata(Bit#(64) v);\n    method Action      wlast(Bit#(1) v);\n    method Bit#(1)     wready();\n    method Action      wstrb(Bit#(8) v);\n    method Action      wvalid(Bit#(1) v);\nendinterface\n(* always_ready, always_enabled *)\ninterface AprpS_axi_ctl;\n    method Action      araddr(Bit#(32) v);\n    method Bit#(1)     arready();\n    method Action      arvalid(Bit#(1) v);\n    method Action      awaddr(Bit#(32) v);\n    method Bit#(1)     awready();\n    method Action      awvalid(Bit#(1) v);\n    method Action      bready(Bit#(1) v);\n    method Bit#(2)     bresp();\n    method Bit#(1)     bvalid();\n    method Bit#(32)     rdata();\n    method Action      rready(Bit#(1) v);\n    method Bit#(2)     rresp();\n    method Bit#(1)     rvalid();\n    method Action      wdata(Bit#(32) v);\n    method Bit#(1)     wready();\n    method Action      wstrb(Bit#(4) v);\n    method Action      wvalid(Bit#(1) v);\nendinterface\n(* always_ready, always_enabled *)\ninterface APRP;\n    interface AprpAxi     axi;\n    interface AprpInterrupt     interrupt;\n    interface AprpIntx     intx;\n    interface AprpM_axi     m_axi;\n    interface AprpMmcm     mmcm;\n    interface AprpMsi     msi;\n    interface AprpPci     pci;\n    interface AprpS_axi     s_axi;\n    interface AprpS_axi_ctl     s_axi_ctl;\nendinterface\nimport \"BVI\" axi_pcie_rp =\nmodule mkAPRP#(Clock refclk, Reset reset, Clock axi_aclk, Reset axi_aresetn, Clock axi_ctl_aclk, Reset axi_ctl_aresetn)(APRP);\n    default_clock clk();\n    default_reset rst();\n    input_clock axi_aclk() = axi_aclk;\n    input_clock axi_ctl_aclk() = axi_ctl_aclk;\n        input_reset reset(axi_aresetn) = reset;\n        input_reset axi_aresetn() clocked_by (axi_aclk) = axi_aresetn;\n\tinput_reset axi_ctl_aresetn() clocked_by (axi_ctl_aclk) = axi_ctl_aresetn;\n    input_clock refclk(REFCLK) = refclk;\n    interface AprpAxi     axi;\n        output_clock aclk_out(axi_aclk_out);\n        output_clock ctl_aclk_out(axi_ctl_aclk_out);\n    endinterface\n    interface AprpInterrupt     interrupt;\n        method interrupt_out out();\n    endinterface\n    interface AprpIntx     intx;\n        method INTX_MSI_Grant msi_grant();\n        method msi_request(INTX_MSI_Request) enable((*inhigh*) EN_INTX_MSI_Request);\n    endinterface\n    interface AprpM_axi     m_axi;\n        method m_axi_araddr araddr();\n        method m_axi_arburst arburst();\n        method m_axi_arcache arcache();\n        method m_axi_arlen arlen();\n        method m_axi_arlock arlock();\n        method m_axi_arprot arprot();\n        method arready(m_axi_arready) enable((*inhigh*) EN_m_axi_arready);\n        method m_axi_arsize arsize();\n        method m_axi_arvalid arvalid();\n        method m_axi_awaddr awaddr();\n        method m_axi_awburst awburst();\n        method m_axi_awcache awcache();\n        method m_axi_awlen awlen();\n        method m_axi_awlock awlock();\n        method m_axi_awprot awprot();\n        method awready(m_axi_awready) enable((*inhigh*) EN_m_axi_awready);\n        method m_axi_awsize awsize();\n        method m_axi_awvalid awvalid();\n        method m_axi_bready bready();\n        method bresp(m_axi_bresp) enable((*inhigh*) EN_m_axi_bresp);\n        method bvalid(m_axi_bvalid) enable((*inhigh*) EN_m_axi_bvalid);\n        method rdata(m_axi_rdata) enable((*inhigh*) EN_m_axi_rdata);\n        method rlast(m_axi_rlast) enable((*inhigh*) EN_m_axi_rlast);\n        method m_axi_rready rready();\n        method rresp(m_axi_rresp) enable((*inhigh*) EN_m_axi_rresp);\n        method rvalid(m_axi_rvalid) enable((*inhigh*) EN_m_axi_rvalid);\n        method m_axi_wdata wdata();\n        method m_axi_wlast wlast();\n        method wready(m_axi_wready) enable((*inhigh*) EN_m_axi_wready);\n        method m_axi_wstrb wstrb();\n        method m_axi_wvalid wvalid();\n    endinterface\n    interface AprpMmcm     mmcm;\n        method mmcm_lock lock();\n    endinterface\n    interface AprpMsi     msi;\n        method MSI_enable enable();\n        method vector_num(MSI_Vector_Num) enable((*inhigh*) EN_MSI_Vector_Num);\n        method MSI_Vector_Width vector_width();\n    endinterface\n    interface AprpPci     pci;\n        method exp_rxn(pci_exp_rxn) enable((*inhigh*) EN_pci_exp_rxn);\n        method exp_rxp(pci_exp_rxp) enable((*inhigh*) EN_pci_exp_rxp);\n        method pci_exp_txn exp_txn();\n        method pci_exp_txp exp_txp();\n    endinterface\n    interface AprpS_axi     s_axi;\n        method araddr(s_axi_araddr) enable((*inhigh*) EN_s_axi_araddr) clocked_by(axi_aclk) reset_by (axi_aresetn);\n        method arburst(s_axi_arburst) enable((*inhigh*) EN_s_axi_arburst) clocked_by(axi_aclk) reset_by (axi_aresetn);\n        method arid(s_axi_arid) enable((*inhigh*) EN_s_axi_arid) clocked_by(axi_aclk) reset_by (axi_aresetn);\n        method arlen(s_axi_arlen) enable((*inhigh*) EN_s_axi_arlen) clocked_by(axi_aclk) reset_by (axi_aresetn);\n        method s_axi_arready arready() clocked_by(axi_aclk) reset_by (axi_aresetn);\n        method arregion(s_axi_arregion) enable((*inhigh*) EN_s_axi_arregion) clocked_by(axi_aclk) reset_by (axi_aresetn);\n        method arsize(s_axi_arsize) enable((*inhigh*) EN_s_axi_arsize) clocked_by(axi_aclk) reset_by (axi_aresetn);\n        method arvalid(s_axi_arvalid) enable((*inhigh*) EN_s_axi_arvalid) clocked_by(axi_aclk) reset_by (axi_aresetn);\n        method awaddr(s_axi_awaddr) enable((*inhigh*) EN_s_axi_awaddr) clocked_by(axi_aclk) reset_by (axi_aresetn);\n        method awburst(s_axi_awburst) enable((*inhigh*) EN_s_axi_awburst) clocked_by(axi_aclk) reset_by (axi_aresetn);\n        method awid(s_axi_awid) enable((*inhigh*) EN_s_axi_awid) clocked_by(axi_aclk) reset_by (axi_aresetn);\n        method awlen(s_axi_awlen) enable((*inhigh*) EN_s_axi_awlen) clocked_by(axi_aclk) reset_by (axi_aresetn);\n        method s_axi_awready awready() clocked_by(axi_aclk) reset_by (axi_aresetn);\n        method awregion(s_axi_awregion) enable((*inhigh*) EN_s_axi_awregion) clocked_by(axi_aclk) reset_by (axi_aresetn);\n        method awsize(s_axi_awsize) enable((*inhigh*) EN_s_axi_awsize) clocked_by(axi_aclk) reset_by (axi_aresetn);\n        method awvalid(s_axi_awvalid) enable((*inhigh*) EN_s_axi_awvalid) clocked_by(axi_aclk) reset_by (axi_aresetn);\n        method s_axi_bid bid() clocked_by(axi_aclk) reset_by (axi_aresetn);\n        method bready(s_axi_bready) enable((*inhigh*) EN_s_axi_bready) clocked_by(axi_aclk) reset_by (axi_aresetn);\n        method s_axi_bresp bresp() clocked_by(axi_aclk) reset_by (axi_aresetn);\n        method s_axi_bvalid bvalid() clocked_by(axi_aclk) reset_by (axi_aresetn);\n        method s_axi_rdata rdata() clocked_by(axi_aclk) reset_by (axi_aresetn);\n        method s_axi_rid rid() clocked_by(axi_aclk) reset_by (axi_aresetn);\n        method s_axi_rlast rlast() clocked_by(axi_aclk) reset_by (axi_aresetn);\n        method rready(s_axi_rready) enable((*inhigh*) EN_s_axi_rready) clocked_by(axi_aclk) reset_by (axi_aresetn);\n        method s_axi_rresp rresp() clocked_by(axi_aclk) reset_by (axi_aresetn);\n        method s_axi_rvalid rvalid() clocked_by(axi_aclk) reset_by (axi_aresetn);\n        method wdata(s_axi_wdata) enable((*inhigh*) EN_s_axi_wdata) clocked_by(axi_aclk) reset_by (axi_aresetn);\n        method wlast(s_axi_wlast) enable((*inhigh*) EN_s_axi_wlast) clocked_by(axi_aclk) reset_by (axi_aresetn);\n        method s_axi_wready wready() clocked_by(axi_aclk) reset_by (axi_aresetn);\n        method wstrb(s_axi_wstrb) enable((*inhigh*) EN_s_axi_wstrb) clocked_by(axi_aclk) reset_by (axi_aresetn);\n        method wvalid(s_axi_wvalid) enable((*inhigh*) EN_s_axi_wvalid) clocked_by(axi_aclk) reset_by (axi_aresetn);\n    endinterface\n    interface AprpS_axi_ctl     s_axi_ctl;\n        method araddr(s_axi_ctl_araddr) enable((*inhigh*) EN_s_axi_ctl_araddr) clocked_by(axi_ctl_aclk) reset_by(axi_ctl_aresetn);\n        method s_axi_ctl_arready arready() clocked_by(axi_ctl_aclk) reset_by(axi_ctl_aresetn);\n        method arvalid(s_axi_ctl_arvalid) enable((*inhigh*) EN_s_axi_ctl_arvalid) clocked_by(axi_ctl_aclk) reset_by(axi_ctl_aresetn);\n        method awaddr(s_axi_ctl_awaddr) enable((*inhigh*) EN_s_axi_ctl_awaddr) clocked_by(axi_ctl_aclk) reset_by(axi_ctl_aresetn);\n        method s_axi_ctl_awready awready() clocked_by(axi_ctl_aclk) reset_by(axi_ctl_aresetn);\n        method awvalid(s_axi_ctl_awvalid) enable((*inhigh*) EN_s_axi_ctl_awvalid) clocked_by(axi_ctl_aclk) reset_by(axi_ctl_aresetn);\n        method bready(s_axi_ctl_bready) enable((*inhigh*) EN_s_axi_ctl_bready) clocked_by(axi_ctl_aclk) reset_by(axi_ctl_aresetn);\n        method s_axi_ctl_bresp bresp() clocked_by(axi_ctl_aclk) reset_by(axi_ctl_aresetn);\n        method s_axi_ctl_bvalid bvalid() clocked_by(axi_ctl_aclk) reset_by(axi_ctl_aresetn);\n        method s_axi_ctl_rdata rdata() clocked_by(axi_ctl_aclk) reset_by(axi_ctl_aresetn);\n        method rready(s_axi_ctl_rready) enable((*inhigh*) EN_s_axi_ctl_rready) clocked_by(axi_ctl_aclk) reset_by(axi_ctl_aresetn);\n        method s_axi_ctl_rresp rresp() clocked_by(axi_ctl_aclk) reset_by(axi_ctl_aresetn);\n        method s_axi_ctl_rvalid rvalid() clocked_by(axi_ctl_aclk) reset_by(axi_ctl_aresetn);\n        method wdata(s_axi_ctl_wdata) enable((*inhigh*) EN_s_axi_ctl_wdata) clocked_by(axi_ctl_aclk) reset_by(axi_ctl_aresetn);\n        method s_axi_ctl_wready wready() clocked_by(axi_ctl_aclk) reset_by(axi_ctl_aresetn);\n        method wstrb(s_axi_ctl_wstrb) enable((*inhigh*) EN_s_axi_ctl_wstrb) clocked_by(axi_ctl_aclk) reset_by(axi_ctl_aresetn);\n        method wvalid(s_axi_ctl_wvalid) enable((*inhigh*) EN_s_axi_ctl_wvalid) clocked_by(axi_ctl_aclk) reset_by(axi_ctl_aresetn);\n    endinterface\n    schedule (interrupt.out, intx.msi_grant, intx.msi_request, m_axi.araddr, m_axi.arburst, m_axi.arcache, m_axi.arlen, m_axi.arlock, m_axi.arprot, m_axi.arready, m_axi.arsize, m_axi.arvalid, m_axi.awaddr, m_axi.awburst, m_axi.awcache, m_axi.awlen, m_axi.awlock, m_axi.awprot, m_axi.awready, m_axi.awsize, m_axi.awvalid, m_axi.bready, m_axi.bresp, m_axi.bvalid, m_axi.rdata, m_axi.rlast, m_axi.rready, m_axi.rresp, m_axi.rvalid, m_axi.wdata, m_axi.wlast, m_axi.wready, m_axi.wstrb, m_axi.wvalid, mmcm.lock, msi.enable, msi.vector_num, msi.vector_width, pci.exp_rxn, pci.exp_rxp, pci.exp_txn, pci.exp_txp, s_axi.araddr, s_axi.arburst, s_axi.arid, s_axi.arlen, s_axi.arready, s_axi.arregion, s_axi.arsize, s_axi.arvalid, s_axi.awaddr, s_axi.awburst, s_axi.awid, s_axi.awlen, s_axi.awready, s_axi.awregion, s_axi.awsize, s_axi.awvalid, s_axi.bid, s_axi.bready, s_axi.bresp, s_axi.bvalid, s_axi.rdata, s_axi.rid, s_axi.rlast, s_axi.rready, s_axi.rresp, s_axi.rvalid, s_axi.wdata, s_axi.wlast, s_axi.wready, s_axi.wstrb, s_axi.wvalid, s_axi_ctl.araddr, s_axi_ctl.arready, s_axi_ctl.arvalid, s_axi_ctl.awaddr, s_axi_ctl.awready, s_axi_ctl.awvalid, s_axi_ctl.bready, s_axi_ctl.bresp, s_axi_ctl.bvalid, s_axi_ctl.rdata, s_axi_ctl.rready, s_axi_ctl.rresp, s_axi_ctl.rvalid, s_axi_ctl.wdata, s_axi_ctl.wready, s_axi_ctl.wstrb, s_axi_ctl.wvalid) CF (interrupt.out, intx.msi_grant, intx.msi_request, m_axi.araddr, m_axi.arburst, m_axi.arcache, m_axi.arlen, m_axi.arlock, m_axi.arprot, m_axi.arready, m_axi.arsize, m_axi.arvalid, m_axi.awaddr, m_axi.awburst, m_axi.awcache, m_axi.awlen, m_axi.awlock, m_axi.awprot, m_axi.awready, m_axi.awsize, m_axi.awvalid, m_axi.bready, m_axi.bresp, m_axi.bvalid, m_axi.rdata, m_axi.rlast, m_axi.rready, m_axi.rresp, m_axi.rvalid, m_axi.wdata, m_axi.wlast, m_axi.wready, m_axi.wstrb, m_axi.wvalid, mmcm.lock, msi.enable, msi.vector_num, msi.vector_width, pci.exp_rxn, pci.exp_rxp, pci.exp_txn, pci.exp_txp, s_axi.araddr, s_axi.arburst, s_axi.arid, s_axi.arlen, s_axi.arready, s_axi.arregion, s_axi.arsize, s_axi.arvalid, s_axi.awaddr, s_axi.awburst, s_axi.awid, s_axi.awlen, s_axi.awready, s_axi.awregion, s_axi.awsize, s_axi.awvalid, s_axi.bid, s_axi.bready, s_axi.bresp, s_axi.bvalid, s_axi.rdata, s_axi.rid, s_axi.rlast, s_axi.rready, s_axi.rresp, s_axi.rvalid, s_axi.wdata, s_axi.wlast, s_axi.wready, s_axi.wstrb, s_axi.wvalid, s_axi_ctl.araddr, s_axi_ctl.arready, s_axi_ctl.arvalid, s_axi_ctl.awaddr, s_axi_ctl.awready, s_axi_ctl.awvalid, s_axi_ctl.bready, s_axi_ctl.bresp, s_axi_ctl.bvalid, s_axi_ctl.rdata, s_axi_ctl.rready, s_axi_ctl.rresp, s_axi_ctl.rvalid, s_axi_ctl.wdata, s_axi_ctl.wready, s_axi_ctl.wstrb, s_axi_ctl.wvalid);\nendmodule\n"
  },
  {
    "path": "tests/rootport/Makefile",
    "content": "CONNECTALDIR?=../..\n\nS2H_INTERFACES = RootPortRequest:RootPort.request\nH2S_INTERFACES = RootPort:RootPortIndication,RootPortTrace:host\n\nMEM_READ_INTERFACES = lRootPort.dmaReadClient\nMEM_WRITE_INTERFACES = lRootPort.dmaWriteClient\n\nBSVFILES = RootPortIfc.bsv $(CONNECTALDIR)/bsv/ConnectalConfig.bsv\nCPPFILES= rootport.cpp\n\nPINOUT_FILE += rootport.json\nPIN_TYPE = RootPortPins\nPIN_TYPE_INCLUDE = RootPortPins\nAUTOTOP = --interface pins:RootPort.pins\n\nAUTOTOP += --portalclock=lRootPort.portalClockSource\nCONNECTALFLAGS += -D USE_ACP\nCONNECTALFLAGS += -D TOP_SOURCES_PORTAL_CLOCK --mainclockperiod=8\n\nCONNECTALFLAGS += -D IMPORT_HOSTIF --bsvpath=../spikehw\nCONNECTALFLAGS += --xci=cores/$(BOARD)/axi_pcie_rp/axi_pcie_rp.xci\nCONNECTALFLAGS += --implconstraint=rootport.xdc\n\ninclude $(CONNECTALDIR)/Makefile.connectal\n"
  },
  {
    "path": "tests/rootport/RootPort.bsv",
    "content": "// Copyright (c) 2016 Connectal Project\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\n`include \"ConnectalProjectConfig.bsv\"\nimport BuildVector::*;\nimport Clocks::*;\nimport Connectable::*;\nimport FIFOF::*;\nimport GetPut::*;\nimport Vector::*;\n\nimport AxiBits::*;\nimport ConnectalClocks::*;\nimport ConnectalConfig::*;\nimport DefaultValue::*;\nimport HostInterface::*;\nimport ConnectalMemTypes::*;\nimport Pipe::*;\nimport TraceMemClient::*;\nimport XilinxCells::*;\n\nimport AxiPcieRootPort::*;\nimport RootPortIfc::*;\nimport RootPortPins::*;\n\n`ifndef TOP_SOURCES_PORTAL_CLOCK\nimport ConnectalBramFifo::*;\n`else\nimport BRAMFIFO::*;\nmodule mkDualClockBramFIFOF#(Clock clock1, Reset reset1, Clock clock2, Reset reset2)(FIFOF#(a))\n   provisos (Bits#(a, asz), Add#(1, a__, asz));\n   FIFOF#(a) fifo <- mkSizedBRAMFIFOF(512, clocked_by clock1, reset_by reset1);\n   return fifo;\nendmodule\n`endif\n\n\ninterface RootPort;\n   interface RootPortRequest request;\n   interface RootPortTrace trace;\n   interface RootPortPins pins;\n   interface Vector#(1, MemReadClient#(DataBusWidth)) dmaReadClient;\n   interface Vector#(1, MemWriteClient#(DataBusWidth)) dmaWriteClient;\n`ifdef TOP_SOURCES_PORTAL_CLOCK\n   interface Clock portalClockSource;\n`endif\nendinterface\n\nmodule mkRootPort#(HostInterface host, RootPortIndication ind, RootPortTrace trace)(RootPort);\n   let clock <- exposeCurrentClock;\n   let reset <- exposeCurrentReset;\n   let refclk_p <- mkB2C1();\n   let refclk_n <- mkB2C1();\n   let pcie_clk_100mhz_buf <- mkClockIBUFDS_GTE2(\n`ifdef ClockDefaultParam\n       defaultValue,\n`endif\n      True, refclk_p.c, refclk_n.c);\n`ifndef TOP_SOURCES_PORTAL_CLOCK\n   let axiClockB2C    <- mkB2C1();\n   let axiCtlClockB2C <- mkB2C1();\n   let axiClock = axiClockB2C.c;\n   let axiCtlClock = axiCtlClockB2C.c;\n   let axiReset <- mkSyncReset(10, reset, axiClock);\n   let axiCtlReset <- mkSyncReset(10, reset, axiCtlClock);\n`else\n   let axiClock = clock;\n   let axiCtlClock = clock;\n   let axiReset = reset;\n   let axiCtlReset = reset;\n`endif\n\n   let axiRootPort <- mkAPRP(pcie_clk_100mhz_buf, reset, axiClock, axiReset, axiCtlClock, axiCtlReset);\n`ifndef TOP_SOURCES_PORTAL_CLOCK\n   let axiClockC2B <- mkC2B(axiRootPort.axi.aclk_out);\n   let axiCtlClockC2B <- mkC2B(axiRootPort.axi.ctl_aclk_out);\n   rule rl_connect_clocks;\n      axiClockB2C.inputclock(axiClockC2B.o);\n      axiCtlClockB2C.inputclock(axiClockC2B.o);\n   endrule\n`endif\n\n   FIFOF#(Bit#(32)) dfifoCtl <- mkFIFOF();\n   Axi4SlaveBits#(32,DataBusWidth,4,Empty) axiRootPortSlave    = toAxi4SlaveBits(axiRootPort.s_axi);\n   Axi4SlaveLiteBits#(32,32)     axiRootPortSlaveCtl = toAxi4SlaveBits(axiRootPort.s_axi_ctl);\n   PhysMemSlave#(32,DataBusWidth)          axiRootPortMemSlave    <- mkPhysMemSlave(axiRootPortSlave, clocked_by axiClock, reset_by axiReset);\n   PhysMemSlave#(32,32)          axiRootPortMemSlaveCtl <- mkPhysMemSlave(axiRootPortSlaveCtl, clocked_by axiCtlClock, reset_by axiCtlReset);\n\n   FIFOF#(PhysMemRequest#(32,DataBusWidth)) araddrFifo <- mkDualClockBramFIFOF(clock, reset, axiClock, axiReset);\n   FIFOF#(PhysMemRequest#(32,DataBusWidth)) awaddrFifo <- mkDualClockBramFIFOF(clock, reset, axiClock, axiReset);\n   FIFOF#(MemData#(DataBusWidth))           rdataFifo <- mkDualClockBramFIFOF(axiClock, axiReset, clock, reset);\n   FIFOF#(MemData#(DataBusWidth))           wdataFifo <- mkDualClockBramFIFOF(clock, reset, axiClock, axiReset);\n   FIFOF#(Bit#(6))                doneFifo <- mkDualClockBramFIFOF(axiClock, axiReset, clock, reset);\n\n   let araddrCnx <- mkConnection(toGet(araddrFifo), axiRootPortMemSlave.read_server.readReq);\n   let awaddrCnx <- mkConnection(toGet(awaddrFifo), axiRootPortMemSlave.write_server.writeReq);\n   let rdataCnx  <- mkConnection(axiRootPortMemSlave.read_server.readData, toPut(rdataFifo));\n   let wdataCnx  <- mkConnection(toGet(wdataFifo), axiRootPortMemSlave.write_server.writeData);\n   let doneCnx   <- mkConnection(axiRootPortMemSlave.write_server.writeDone, toPut(doneFifo));\n\n   rule rl_rdata;\n      let rdata <- toGet(rdataFifo).get();\n      ind.readDone(rdata.data);\n   endrule\n\n   rule rl_writeDone;\n      let tag <- toGet(doneFifo).get();\n      ind.writeDone();\n   endrule\n\n   FIFOF#(PhysMemRequest#(32,32)) araddrFifoCtl <- mkDualClockBramFIFOF(clock, reset, axiCtlClock, axiCtlReset);\n   FIFOF#(PhysMemRequest#(32,32)) awaddrFifoCtl <- mkDualClockBramFIFOF(clock, reset, axiCtlClock, axiCtlReset);\n   FIFOF#(MemData#(32))           rdataFifoCtl <- mkDualClockBramFIFOF(axiCtlClock, axiCtlReset, clock, reset);\n   FIFOF#(MemData#(32))           wdataFifoCtl <- mkDualClockBramFIFOF(clock, reset, axiCtlClock, axiCtlReset);\n   FIFOF#(Bit#(6))                doneFifoCtl <- mkDualClockBramFIFOF(axiCtlClock, axiCtlReset, clock, reset);\n\n   let araddrCtlCnx <- mkConnection(toGet(araddrFifoCtl), axiRootPortMemSlaveCtl.read_server.readReq);\n   let awaddrCtlCnx <- mkConnection(toGet(awaddrFifoCtl), axiRootPortMemSlaveCtl.write_server.writeReq);\n   let rdataCtlCnx  <- mkConnection(axiRootPortMemSlaveCtl.read_server.readData, toPut(rdataFifoCtl));\n   let wdataCtlCnx  <- mkConnection(toGet(wdataFifoCtl), axiRootPortMemSlaveCtl.write_server.writeData);\n   let doneCtlCnx   <- mkConnection(axiRootPortMemSlaveCtl.write_server.writeDone, toPut(doneFifoCtl));\n\n   rule rl_rdata_ctl;\n      let rdata <- toGet(rdataFifoCtl).get();\n      ind.readDone(extend(rdata.data));\n   endrule\n\n   rule rl_writeDone_ctl;\n      let tag <- toGet(doneFifoCtl).get();\n      ind.writeDone();\n   endrule\n\n   Axi4MasterBits#(32,DataBusWidth,MemTagSize,Empty) m_axi_mm = toAxi4MasterBits(axiRootPort.m_axi);\n   let getObjId = (interface GetObjId;\n\t\t   method SGLId objId(Bit#(32) addr); return extend(addr[31:24]); endmethod\n\t\t   method Bit#(MemOffsetSize) addr(Bit#(32) axiAddr); return extend(axiAddr[23:0]); endmethod\n\t\t   endinterface);\n   let memReadClients  <- mapM(mkMemReadClient(getObjId), vec(m_axi_mm));\n   let memWriteClients <- mapM(mkMemWriteClient(getObjId), vec(m_axi_mm));\n\n   FIFOF#(Tuple4#(DmaChannel,Bool,MemRequest,Bit#(32))) traceFifo <- mkDualClockBramFIFOF(clock, reset, clock, reset);\n   FIFOF#(Tuple4#(DmaChannel,Bool,MemRequest,Bit#(32))) traceFifo0 <- mkFIFOF();\n   FIFOF#(Tuple4#(DmaChannel,Bool,MemRequest,Bit#(32))) traceFifo1 <- mkFIFOF();\n   PipeIn#(Tuple4#(DmaChannel,Bool,MemRequest,Bit#(32))) tracePipe = toPipeIn(traceFifo0);\n   FIFOF#(Tuple4#(DmaChannel,Bool,MemData#(DataBusWidth),Bit#(32))) traceDataFifo <- mkDualClockBramFIFOF(clock, reset, clock, reset);\n   FIFOF#(Tuple4#(DmaChannel,Bool,MemData#(DataBusWidth),Bit#(32))) traceDataFifo0 <- mkFIFOF();\n   FIFOF#(Tuple4#(DmaChannel,Bool,MemData#(DataBusWidth),Bit#(32))) traceDataFifo1 <- mkFIFOF();\n   PipeIn#(Tuple4#(DmaChannel,Bool,MemData#(DataBusWidth),Bit#(32))) traceDataPipe = toPipeIn(traceDataFifo0);\n   let trace0Cnx <- mkConnection(toGet(traceFifo0), toPut(traceFifo));\n   let trace1Cnx <- mkConnection(toGet(traceFifo), toPut(traceFifo1));\n   rule rl_trace1;\n      match { .chan, .write, .req, .timestamp } <- toGet(traceFifo1).get();\n      trace.traceDmaRequest(chan, write, truncate(req.sglId), extend(req.offset), extend(req.burstLen), extend(req.tag), timestamp);\n   endrule\n   let traceData0Cnx <- mkConnection(toGet(traceDataFifo0), toPut(traceDataFifo));\n   let traceData1Cnx <- mkConnection(toGet(traceDataFifo), toPut(traceDataFifo1));\n   rule rl_trace_data;\n      match { .chan, .write, .md, .timestamp } <- toGet(traceDataFifo1).get();\n      trace.traceDmaData(chan, write, md.data, md.last, extend(md.tag), timestamp);\n   endrule\n\n   let traceReadClients <- mapM(uncurry(mkTraceReadClient(tracePipe,traceDataPipe)),\n\t\t\t\tzip(vec(DMA_TX),\n\t\t\t\t    memReadClients));\n   let traceWriteClients <- mapM(uncurry(mkTraceWriteClient(tracePipe,traceDataPipe)),\n\t\t\t\t zip(vec(DMA_RX),\n\t\t\t\t     memWriteClients));\n\n   interface RootPortRequest request;\n\n      method Action status();\n        ind.status(axiRootPort.mmcm.lock());\n      endmethod\n\n      method Action read32(Bit#(32) addr);\n\t araddrFifo.enq(PhysMemRequest { addr: addr, burstLen: 4, tag: 0 });\n      endmethod\n      method Action write32(Bit#(32) addr, Bit#(32) value);\n\t awaddrFifo.enq(PhysMemRequest { addr: addr, burstLen: 4, tag: 0 });\n\t wdataFifo.enq(MemData {data: extend(value), tag: 0, last: True});\n      endmethod\n      method Action read(Bit#(32) addr);\n\t araddrFifo.enq(PhysMemRequest { addr: addr, burstLen: fromInteger(valueOf(TDiv#(DataBusWidth,8))), tag: 0 });\n      endmethod\n      method Action write(Bit#(32) addr, Bit#(DataBusWidth) value);\n\t awaddrFifo.enq(PhysMemRequest { addr: addr, burstLen: fromInteger(valueOf(TDiv#(DataBusWidth,8))), tag: 0 });\n\t wdataFifo.enq(MemData {data: value, tag: 0, last: True});\n      endmethod\n\n      method Action readCtl(Bit#(32) addr);\n\t araddrFifoCtl.enq(PhysMemRequest { addr: addr, burstLen: 4, tag: 0 });\n      endmethod\n      method Action writeCtl(Bit#(32) addr, Bit#(DataBusWidth) value);\n\t awaddrFifoCtl.enq(PhysMemRequest { addr: addr, burstLen: 4, tag: 0 });\n\t wdataFifoCtl.enq(MemData {data: truncate(value), tag: 0, last: True});\n      endmethod\n   endinterface\n   interface Clock portalClockSource = axiRootPort.axi.aclk_out;\n   interface RootPortPins pins;\n      interface deleteme_unused_clock = clock;\n      interface pcie_sys_reset_n = reset;\n      interface pcie = axiRootPort.pci;\n      method Action pcie_refclk(Bit#(1) p, Bit#(1) n);\n         refclk_p.inputclock(p);\n         refclk_n.inputclock(n);\n      endmethod\n   endinterface\n   interface Vector dmaReadClient = traceReadClients;\n   interface Vector dmaWriteClient = traceWriteClients;\nendmodule\n\ninstance ToAxi4SlaveBits#(Axi4SlaveBits#(32,DataBusWidth,4,Empty), AprpS_axi);\n   function Axi4SlaveBits#(32,DataBusWidth,4,Empty) toAxi4SlaveBits(AprpS_axi s);\n      return (interface Axi4SlaveBits#(32,DataBusWidth,4,Empty);\n\t method araddr = compose(s.araddr, extend);\n\t method arburst = s.arburst;\n\t //method arcache = s.arcache;\n\t method arid = s.arid;\n\t method arlen = s.arlen;\n\t //method arlock = s.arlock;\n\t //method arprot = s.arprot;\n\t //method arqos = s.arqos;\n\t method arready = s.arready;\n\t method arsize = s.arsize;\n\t method arvalid = s.arvalid;\n\t \n\t method awaddr = compose(s.awaddr, extend);\n\t method awburst = s.awburst;\n\t //method awcache = s.awcache;\n\t method awid = s.awid;\n\t method awlen = s.awlen;\n\t //method awlock = s.awlock;\n\t //method awprot = s.awprot;\n\t //method awqos = s.awqos;\n\t method awready = s.awready;\n\t method awsize = s.awsize;\n\t method awvalid = s.awvalid;\n\n\t method bid = s.bid;\n\t method bready = s.bready;\n\t method bresp = s.bresp;\n\t method bvalid = s.bvalid;\n\t method rdata = s.rdata;\n\t method rid = s.rid;\n\t method rlast = s.rlast;\n\t method rready = s.rready;\n\t method rresp = s.rresp;\n\t method rvalid = s.rvalid;\n\t method wdata = s.wdata;\n\t method wlast = s.wlast;\n\t method wready = s.wready;\n\t method wvalid = s.wvalid;\n\t method wstrb = s.wstrb;\n\t endinterface);\n   endfunction\nendinstance\n\ninstance ToAxi4SlaveBits#(Axi4SlaveLiteBits#(32,32), AprpS_axi_ctl);\n   function Axi4SlaveLiteBits#(32,32) toAxi4SlaveBits(AprpS_axi_ctl s);\n      return (interface Axi4SlaveLiteBits#(32,32);\n\t method araddr = compose(s.araddr, extend);\n\t method arready = s.arready;\n\t method arvalid = s.arvalid;\n\n\t method awaddr = compose(s.awaddr, extend);\n\t method awready = s.awready;\n\t method awvalid = s.awvalid;\n\n\t method bready = s.bready;\n\t method bresp = s.bresp;\n\t method bvalid = s.bvalid;\n\t method rdata = s.rdata;\n\t method rready = s.rready;\n\t method rresp = s.rresp;\n\t method rvalid = s.rvalid;\n\t method wdata = s.wdata;\n\t method wready = s.wready;\n\t method Action      wvalid(Bit#(1) v);\n\t    s.wvalid(v);\n\t    s.wstrb(pack(replicate(v)));\n\t endmethod\n\t endinterface);\n   endfunction\nendinstance\n\ninstance ToAxi4MasterBits#(Axi4MasterBits#(32,DataBusWidth,tagWidth,Empty), AprpM_axi);\nfunction Axi4MasterBits#(32,DataBusWidth,tagWidth,Empty) toAxi4MasterBits(AprpM_axi m);\n   return (interface Axi4MasterBits#(32,DataBusWidth,tagWidth,Empty);\n\t   method araddr = m.araddr;\n\t   method arburst = m.arburst;\n\t   method arcache = m.arcache;\n\t   method arlen = m.arlen;\n\t   method arlock = extend(m.arlock);\n\t   method arready = m.arready;\n\t   method arsize = m.arsize;\n\t   method arvalid = m.arvalid;\n\t   method Bit#(1) aresetn(); return 1; endmethod\n\t   method Bit#(tagWidth)     arid(); return 0; endmethod\n\t   method arprot = m.arprot;\n\t   method arqos = 0;\n\t   method awaddr = m.awaddr;\n\t   method awburst = m.awburst;\n\t   method awcache = m.awcache;\n\t   method Bit#(tagWidth)     awid(); return 0; endmethod\n\t   method awlen = m.awlen;\n\t   method awlock = extend(m.awlock);\n\t   method awprot = m.awprot;\n\t   method awready = m.awready;\n\t   method Bit#(4)     awqos(); return 0; endmethod\n\t   method awsize = m.awsize;\n\t   method awvalid = m.awvalid;\n\t   method Action      bid(Bit#(tagWidth) v); endmethod\n\t   method bready = m.bready;\n\t   method bresp = m.bresp;\n\t   method bvalid = m.bvalid;\n\t   method rdata = m.rdata;\n\t   method Action      rid(Bit#(tagWidth) v); endmethod\n\t   method rlast = m.rlast;\n\t   method rready = m.rready;\n\t   method rresp = m.rresp;\n\t   method rvalid = m.rvalid;\n\t   method wdata = m.wdata;\n\t   method Bit#(tagWidth)     wid(); return 0; endmethod\n\t   method wlast = m.wlast;\n\t   method wready = m.wready;\n\t   method wstrb = m.wstrb;\n\t   method wvalid = m.wvalid;\n\t interface extra = ?;   \n\t endinterface);\n   endfunction\nendinstance\n"
  },
  {
    "path": "tests/rootport/RootPortIfc.bsv",
    "content": "// Copyright (c) 2016 Connectal Project\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\nimport ConnectalConfig::*;\n\ntypedef enum { DMA_RX, DMA_TX, DMA_SG } DmaChannel deriving (Bits,Eq);\n\ninterface RootPortRequest;\n   method Action read32(Bit#(32) addr);\n   method Action write32(Bit#(32) addr, Bit#(32) data);\n   method Action read(Bit#(32) addr);\n   method Action write(Bit#(32) addr, Bit#(DataBusWidth) data);\n   method Action readCtl(Bit#(32) addr);\n   method Action writeCtl(Bit#(32) addr, Bit#(DataBusWidth) data);\n   method Action status();\nendinterface\n\ninterface RootPortIndication;\n   method Action readDone(Bit#(DataBusWidth) data);\n   method Action writeDone();\n   method Action status(Bit#(1) mmcm_lock);\nendinterface\n\ninterface RootPortTrace;\n   method Action traceDmaRequest(DmaChannel channel, Bool write, Bit#(16) objId, Bit#(DataBusWidth) offset, Bit#(16) burstLen, Bit#(8) tag, Bit#(32) timestamp);\n   method Action traceDmaData(DmaChannel channel, Bool write, Bit#(DataBusWidth) data, Bool last, Bit#(8) tag, Bit#(32) timestamp);\nendinterface\n"
  },
  {
    "path": "tests/rootport/RootPortPins.bsv",
    "content": "\n// Copyright (c) 2016 Connectal Project\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\n`include \"ConnectalProjectConfig.bsv\"\n\nimport AxiPcieRootPort::*;\n\ninterface RootPortPins;\n   interface AprpPci pcie;\n   method Action pcie_refclk(Bit#(1) p, Bit#(1) n);\n   interface Clock deleteme_unused_clock;\n   interface Reset pcie_sys_reset_n;\nendinterface\n\nexport RootPortPins(..);\n"
  },
  {
    "path": "tests/rootport/gencores.tcl",
    "content": "set ipdir {cores}\nset boardname {miniitx100}\n\nif {$boardname == {nfsume}} {\n    set partname {xc7vx690tffg1761-2}\n    set databuswidth 32\n}\nif {$boardname == {miniitx100}} {\n    set partname {xc7z100ffg900-2}\n    set databuswidth 64\n}\nputs \"partname=$partname\"\n\ncreate_project -name local_synthesized_ip -in_memory -part $partname\nif {$boardname == {nfsume}} {\n    set_property board_part xilinx.com:vc709:part0:1.0 [current_project]\n}\nproc fpgamake_ipcore {core_name core_version ip_name params} {\n    global ipdir boardname\n\n    set generate_ip 0\n\n    if [file exists $ipdir/$boardname/$ip_name/$ip_name.xci] {\n    } else {\n\tputs \"no xci file $ip_name.xci\"\n\tset generate_ip 1\n    }\n    if [file exists $ipdir/$boardname/$ip_name/vivadoversion.txt] {\n\tgets [open $ipdir/$boardname/$ip_name/vivadoversion.txt r] generated_version\n\tset current_version [version -short]\n\tputs \"core was generated by vivado $generated_version, currently running vivado $current_version\"\n\tif {$current_version != $generated_version} {\n\t    puts \"vivado version does not match\"\n\t    set generate_ip 1\n\t}\n    } else {\n\tputs \"no vivado version recorded\"\n\tset generate_ip 1\n    }\n\n    ## check requested core version and parameters\n    if [file exists $ipdir/$boardname/$ip_name/coreversion.txt] {\n\tgets [open $ipdir/$boardname/$ip_name/coreversion.txt r] generated_version\n\tset current_version \"$core_name $core_version $params\"\n\tputs \"Core generated: $generated_version\"\n\tputs \"Core requested: $current_version\"\n\tif {$current_version != $generated_version} {\n\t    puts \"core version or params does not match\"\n\t    set generate_ip 1\n\t}\n    } else {\n\tputs \"no core version recorded\"\n\tset generate_ip 1\n    }\n\n    if $generate_ip {\n\tfile delete -force $ipdir/$boardname/$ip_name\n\tfile mkdir $ipdir/$boardname\n\tcreate_ip -name $core_name -version $core_version -vendor xilinx.com -library ip -module_name $ip_name -dir $ipdir/$boardname\n\tif [llength $params] {\n\t    set_property -dict $params [get_ips $ip_name]\n\t}\n        report_property -file $ipdir/$boardname/$ip_name.properties.log [get_ips $ip_name]\n\t\n\tgenerate_target all [get_files $ipdir/$boardname/$ip_name/$ip_name.xci]\n\n\tset versionfd [open $ipdir/$boardname/$ip_name/vivadoversion.txt w]\n\tputs $versionfd [version -short]\n\tclose $versionfd\n\n\tset corefd [open $ipdir/$boardname/$ip_name/coreversion.txt w]\n\tputs $corefd \"$core_name $core_version $params\"\n\tclose $corefd\n    } else {\n\tread_ip $ipdir/$boardname/$ip_name/$ip_name.xci\n    }\n    if [file exists $ipdir/$boardname/$ip_name/$ip_name.dcp] {\n    } else {\n\tsynth_ip [get_ips $ip_name]\n    }\n}\n\nfpgamake_ipcore axi_pcie 2.7 axi_pcie_rp [list CONFIG.INCLUDE_RC {Root_Port_of_PCI_Express_Root_Complex} CONFIG.NO_OF_LANES {X4} CONFIG.BAR0_SCALE {Gigabytes} CONFIG.INCLUDE_BAROFFSET_REG {false} CONFIG.AXIBAR_0 {0x00000000} CONFIG.AXIBAR_HIGHADDR_0 {0xfFFFFFFF} CONFIG.AXIBAR2PCIEBAR_0 {0x00000000} CONFIG.BASEADDR {0x00000000} CONFIG.HIGHADDR {0xffffffff} CONFIG.XLNX_REF_BOARD {ZC706} CONFIG.shared_logic_in_core {true} CONFIG.MAX_LINK_SPEED {2.5_GT/s} CONFIG.DEVICE_ID {0x7022} CONFIG.BASE_CLASS_MENU {Bridge_device} CONFIG.SUB_CLASS_INTERFACE_MENU {InfiniBand_to_PCI_host_bridge} CONFIG.BAR0_SIZE {1} CONFIG.S_AXI_DATA_WIDTH {64} CONFIG.M_AXI_DATA_WIDTH {64} CONFIG.NUM_MSI_REQ {5} CONFIG.S_AXI_SUPPORTS_NARROW_BURST {true}]\n\n\n"
  },
  {
    "path": "tests/rootport/rootport.cpp",
    "content": "#include <stdio.h>\n\n#include \"portal.h\"\n#include \"dmaManager.h\"\n#include \"RootPortIndication.h\"\n#include \"RootPortRequest.h\"\n#include \"RootPortTrace.h\"\n\nenum nvme_admin_opcode {\n    nvme_identify = 0xe2 // 6?\n};\n\nstruct nvme_admin_cmd {\n    uint8_t opcode;\n    uint8_t flags;\n    uint16_t cid;\n    uint32_t nsid;\n    uint32_t reserved0;\n    uint32_t reserved1;\n    uint64_t mptr;\n    uint64_t prp1;\n    uint64_t prp2;\n    uint32_t cdw10;\n    uint32_t cdw11;\n    uint32_t cdw12;\n    uint32_t cdw13;\n    uint32_t cdw14;\n    uint32_t cdw15;\n};\n\nstruct nvme_io_cmd {\n    uint8_t opcode;\n    uint8_t flags;\n    uint16_t cid;\n    uint32_t nsid;\n    uint32_t reserved0;\n    uint32_t reserved1;\n    uint64_t mptr;\n    uint64_t prp1;\n    uint64_t prp2;\n    uint32_t cdw10;\n    uint32_t cdw11;\n    uint32_t cdw12;\n    uint32_t cdw13;\n    uint32_t cdw14;\n    uint32_t cdw15;\n};\n\nclass RootPortTrace : public RootPortTraceWrapper {\npublic:\n    void traceDmaRequest(const DmaChannel chan, const int write, const uint16_t objId, const uint64_t offset, const uint16_t burstLen, const uint8_t tag, const uint32_t timestamp) {\n\tfprintf(stderr, \"%08x: traceDmaRequest chan=%d write=%d objId=%d offset=%08lx burstLen=%d tag=%x\\n\", timestamp, chan, write, objId, (long)offset, burstLen, tag);\n    }\n    void traceDmaData ( const DmaChannel chan, const int write, const uint64_t data, const int last, const uint8_t tag, const uint32_t timestamp ) {\n\tfprintf(stderr, \"%08x: traceDmaData chan=%d write=%d data=%08llx last=%d tag=%x\\n\", timestamp, chan, write, (long long)data, last, tag);\n    }\n\n    RootPortTrace(int id, PortalPoller *poller = 0) : RootPortTraceWrapper(id, poller) {\n    }\n};\n\nclass RootPortIndication : public RootPortIndicationWrapper {\n    sem_t sem, wsem;\n    \npublic:\n    uint64_t value;\n    virtual void readDone ( const uint64_t data ) {\n\t//fprintf(stderr, \"%s:%d data=%08llx\\n\", __FUNCTION__, __LINE__, (long long)data);\n\tvalue = data;\n\tsem_post(&sem);\n    }\n    virtual void writeDone (  ) {\n\t//fprintf(stderr, \"%s:%d\\n\", __FUNCTION__, __LINE__);\n\tsem_post(&wsem);\n    }\n    virtual void status ( const uint8_t mmcm_lock ) {\n\tfprintf(stderr, \"%s:%d mmcm_lock=%d\\n\", __FUNCTION__, __LINE__, mmcm_lock);\n\tsem_post(&sem);\n    }\t\n\n    void wait() {\n\tsem_wait(&sem);\n    }\n    void waitwrite() {\n\tsem_wait(&wsem);\n    }\n    RootPortIndication(int id, PortalPoller *poller = 0) : RootPortIndicationWrapper(id, poller) {\n\tsem_init(&sem, 0, 0);\n\tsem_init(&wsem, 0, 0);\n    }\n  \n};\n\nclass DmaBuffer {\n    const int size;\n    int fd;\n    char *buf;\n    int ref;\n    static DmaManager *mgr;\n    static void initDmaManager();\npublic:\n    // Allocates a portal memory object of specified size and maps it into user process\n    DmaBuffer(int size);\n    // Dereferences and deallocates the portal memory object\n    // if destructor is not called, the object is automatically\n    // unreferenced and freed when the process exits\n    ~DmaBuffer();\n    // returns the address of the mapped buffer\n    char *buffer() {\n\treturn buf;\n    }\n    // returns the reference to the object\n    //\n    // Sends the address translation table to hardware MMU if necessary.\n    uint32_t reference();\n    // Removes the address translation table from the hardware MMU\n    void dereference();\n    // invalidate and optionally flush from the dcache\n    void cacheFlush(int size=0, int flush=0);\n};\n\nDmaManager *DmaBuffer::mgr;\n\nvoid DmaBuffer::initDmaManager()\n{\n    if (!mgr)\n\tmgr = platformInit();\n}\n\n\nDmaBuffer::DmaBuffer(int size)\n  : size(size), ref(-1)\n{\n    fd = portalAlloc(size, 1);\n    buf = (char *)portalMmap(fd, size);\n}\n\nDmaBuffer::~DmaBuffer()\n{\n    dereference();\n    portalMunmap(buf, size);\n    close(fd);\n}\n\nuint32_t DmaBuffer::reference()\n{\n    initDmaManager();\n    if (ref == -1)\n\tref = mgr->reference(fd);\n    return ref;\n}\n\nvoid DmaBuffer::dereference()\n{\n    if (ref != -1 && mgr)\n\tmgr->dereference(ref);\n    ref = -1;\n}\n\nvoid DmaBuffer::cacheFlush(int size, int flush)\n{\n    if (size == 0)\n\tsize = this->size;\n    portalCacheFlush(fd, buf, size, flush);\n}\n\n\nclass RootPort {\n    RootPortRequestProxy device;\n    RootPortIndication  indication;\n    RootPortTrace       trace;\npublic:\n    DmaBuffer dummy;\n    DmaBuffer transferBuffer;\n    DmaBuffer adminSubmissionQueue;\n    DmaBuffer adminCompletionQueue;\n    DmaBuffer ioSubmissionQueue;\n    DmaBuffer ioCompletionQueue;\n    int transferBufferRef;\n    int adminSubmissionQueueRef;\n    int adminCompletionQueueRef;\n    int ioSubmissionQueueRef;\n    int ioCompletionQueueRef;\n\n    RootPort()\n\t: device(IfcNames_RootPortRequestS2H)\n\t, indication(IfcNames_RootPortIndicationH2S)\n\t, trace(IfcNames_RootPortTraceH2S)\n\t, dummy(4096)\n\t, transferBuffer(10*4096)\n\t, adminSubmissionQueue(64*64)\n\t, adminCompletionQueue(4096)\n\t, ioSubmissionQueue(8192)\n\t, ioCompletionQueue(8192) {\n\t\n\tdummy.reference();\n\ttransferBufferRef = transferBuffer.reference();\n\tadminSubmissionQueueRef = adminSubmissionQueue.reference();\n\tadminCompletionQueueRef = adminCompletionQueue.reference();\n\tfprintf(stderr, \"adminSubmissionQueue %d\\n\", adminSubmissionQueue.reference());\n\tfprintf(stderr, \"adminCompletionQueue %d\\n\", adminCompletionQueue.reference());\n\tioSubmissionQueueRef = ioSubmissionQueue.reference();\n\tioCompletionQueueRef = ioCompletionQueue.reference();\n\tfprintf(stderr, \"ioSubmissionQueue %d\\n\", ioSubmissionQueue.reference());\n\tfprintf(stderr, \"ioCompletionQueue %d\\n\", ioCompletionQueue.reference());\n\tdevice.status();\n\tindication.wait();\n    }\n    uint32_t readCtl(uint32_t addr);\n    void writeCtl(uint32_t addr, uint32_t data);\n    uint64_t read(uint32_t addr);\n    void write(uint32_t addr, uint64_t data);\n    uint32_t read32(uint32_t addr);\n    void write32(uint32_t addr, uint32_t data);\n};\n\nuint32_t RootPort::readCtl(uint32_t addr)\n{\n    device.readCtl(addr);\n    indication.wait();\n    return (uint32_t)indication.value;\n}\nvoid RootPort::writeCtl(uint32_t addr, uint32_t data)\n{\n    device.writeCtl(addr, data);\n    indication.waitwrite();\n}\nuint64_t RootPort::read(uint32_t addr)\n{\n    device.read(addr);\n    indication.wait();\n    return indication.value;\n}\nvoid RootPort::write(uint32_t addr, uint64_t data)\n{\n    device.write(addr, data);\n    //indication.wait();\n}\nuint32_t RootPort::read32(uint32_t addr)\n{\n    device.read32(addr);\n    indication.wait();\n    uint64_t v = indication.value;\n    return (uint32_t)(v >> ((addr & 4) ? 32 : 0));\n    //return v;\n}\nvoid RootPort::write32(uint32_t addr, uint32_t data)\n{\n    uint64_t v = data;\n    //fixme byte enables\n    //device.write(addr & ~7, v << ((addr & 4) ? 32 : 0));\n    device.write32(addr, v);\n    //indication.wait();\n}\n\nvoid memserverWrite(RootPort *rootPort)\n{\n    // identify portals\n    int numTiles = rootPort->read32(0x02200000 + 0x08);\n    int numPortals = rootPort->read32(0x02200000 + 0x14);\n    fprintf(stderr, \"numTiles=%x numPortals=%x\\n\", numTiles, numPortals);\n    for (int p = 0; p < numPortals; p++) {\n\tfprintf(stderr, \"Platform Portal[%d].id=%x\\n\", p, rootPort->read32(0x02200000 + p*0x1000 + 0x10));\n    }\n\n    numTiles = rootPort->read32(0x02200000 + 0x40000 + 0x08);\n    numPortals = rootPort->read32(0x02200000 + 0x40000 + 0x14);\n    fprintf(stderr, \"numTiles=%x numPortals=%x\\n\", numTiles, numPortals);\n    for (int p = 0; p < numPortals; p++) {\n\tfprintf(stderr, \"Portal[%d].id=%x\\n\", p, rootPort->read32(0x02200000 + 0x40000 + p*0x1000 + 0x10));\n    }\n\n    if (1) {\n\t// pause for vivado to connect\n\tfprintf(stderr, \"type enter to continue:\\n\");\n\tchar line[100];\n\tfgets(line, sizeof(line), stdin);\n    }\n\n    // start write test\n    int pointer = 1;\n    int numWords = 0x1000;\n    int burstLen = 64;\n    int numReqs = numWords / burstLen;\n    int byteEnable = 0xff;\n    rootPort->write32(0x02200000 + 0x41000 + 0x20, (pointer>>24));\n    rootPort->write32(0x02200000 + 0x41000 + 0x20, (numWords>>24)|(((unsigned long)pointer)<<8));\n    rootPort->write32(0x02200000 + 0x41000 + 0x20, (numReqs>>24)|(((unsigned long)numWords)<<8));\n    rootPort->write32(0x02200000 + 0x41000 + 0x20, (burstLen>>24)|(((unsigned long)numReqs)<<8));\n    rootPort->write32(0x02200000 + 0x41000 + 0x20, byteEnable|(((unsigned long)burstLen)<<8));\n}\n\nvoid identify(RootPort *rootPort)\n{\n    memset(rootPort->adminCompletionQueue.buffer(), 0xbf, 4096);\n\n    fprintf(stderr, \"sizeof(nvmd_id_cmd)=%d\\n\", sizeof(nvme_admin_cmd));\n    // write an identify command\n    nvme_admin_cmd *cmd = (nvme_admin_cmd *)rootPort->adminSubmissionQueue.buffer();\n    memset(cmd, 0, 64);\n    cmd->opcode = 6; //nvme_identify;\n    cmd->cid = 22;\n    cmd->nsid = 0;\n    cmd->prp1 = (rootPort->transferBufferRef << 24) + 0;\n    cmd->prp2 = (rootPort->transferBufferRef << 24) + 4096;\n    cmd->cdw10 = 1;\n\n    //rootPort->adminSubmissionQueue.cacheFlush(4096, 1);\n    //rootPort->adminCompletionQueue.cacheFlush(4096, 0);\n\n    // update submission queue tail\n    rootPort->write32(0x1000, 1);\n    //rootPort->write32(0x1000, 64);\n    fprintf(stderr, \"CTS %08x\\n\", rootPort->read32( 0x1c));\n    fprintf(stderr, \"CMDSTATUS: %08x\\n\", rootPort->readCtl((1 << 20) + 0x4));\n    sleep(1);\n    fprintf(stderr, \"CTS %08x\\n\", rootPort->read32( 0x1c));\n    fprintf(stderr, \"CMDSTATUS: %08x\\n\", rootPort->readCtl((1 << 20) + 0x4));\n    {\n\tint *buffer = (int *)rootPort->adminCompletionQueue.buffer();\n\tfor (int i = 0; i < 16; i++) {\n\t    fprintf(stderr, \"response[%02x]=%08x\\n\", i*4, buffer[i]);\n\t}\n\tint status = buffer[3];\n\tint more = (status >> 30) & 1;\n\tint sc = (status >> 17) & 0xff;\n\tint sct = (status >> 25) & 0x7;\n\tfprintf(stderr, \"status=%08x more=%d sc=%x sct=%x\\n\", status, more, sc, sct);\n    }\n    {\n\tchar *cbuffer = (char *)(rootPort->transferBuffer.buffer() + 0);\n\tint *buffer = (int *)(rootPort->transferBuffer.buffer() + 0);\n\tfor (int i = 0; i < 16; i++) {\n\t    fprintf(stderr, \"identity[%02x]=%08x\\n\", i*4, buffer[i]);\n\t}\n\tfprintf(stderr, \"error log page entries %d\\n\", cbuffer[262]);\n\tfprintf(stderr, \"host buffer preferred size %x\\n\", *(int *)&cbuffer[272]);\n\tfprintf(stderr, \"host buffer min size       %x\\n\", *(int *)&cbuffer[276]);\n\tfprintf(stderr, \"nvm submission queue entry size %d\\n\", cbuffer[512]);\n\tfprintf(stderr, \"nvm completion queue entry size %d\\n\", cbuffer[513]);\n\tfprintf(stderr, \"nvm capacity: %08llx %08llx\\n\", *(long long *)&cbuffer[288], *(long long *)&cbuffer[280]);\n\n    }\n}\n\nvoid allocIOQueues(RootPort *rootPort, int entry=0)\n{\n    nvme_admin_cmd *cmd = 0;\n\n    // create I/O completion queue\n    cmd = (nvme_admin_cmd *)(rootPort->adminSubmissionQueue.buffer() + (entry+0)*64);\n    memset(cmd, 0, 64);\n    cmd->opcode = 5; //create I/O completion queue\n    cmd->cid = 18;\n    cmd->nsid = 0;\n    cmd->prp1 = (rootPort->ioCompletionQueueRef << 24) + 0;\n    cmd->cdw10 = ((8192 / 16 - 1) << 16) | 1; // size, completion queue 1\n    cmd->cdw11 = 1; // physically contiguous\n\n    // create I/O submission queue\n    cmd = (nvme_admin_cmd *)(rootPort->adminSubmissionQueue.buffer() + (entry+1)*64);\n    memset(cmd, 0, 64);\n    cmd->opcode = 1; //create I/O submission queue\n    cmd->cid = 17;\n    cmd->nsid = 0;\n    cmd->prp1 = (rootPort->ioSubmissionQueueRef << 24) + 0;\n    cmd->cdw10 = ((8192 / 64 - 1) << 16) + 1; // submission queue 1\n    cmd->cdw11 = (1 << 16) | 1; // completion queue 1, physically contiguous\n\n\n    fprintf(stderr, \"allocating IO submission queue\\n\");\n    // update submission queue tail\n    rootPort->write32(0x1000, entry+2);\n\n    sleep(1);\n    {\n\tint *buffer = (int *)(rootPort->adminCompletionQueue.buffer() + (entry+0)*16);\n\tfor (int i = 0; i < 16; i++) {\n\t    fprintf(stderr, \"response[%02x]=%08x\\n\", i*4, buffer[i]);\n\t}\n\tint status = buffer[3];\n\tint more = (status >> 30) & 1;\n\tint sc = (status >> 17) & 0xff;\n\tint sct = (status >> 25) & 0x7;\n\tfprintf(stderr, \"status=%08x more=%d sc=%x sct=%x\\n\", status, more, sc, sct);\n    }\n    {\n\tint *buffer = (int *)(rootPort->adminCompletionQueue.buffer() + (entry+1)*16);\n\tfor (int i = 0; i < 16; i++) {\n\t    fprintf(stderr, \"response[%02x]=%08x\\n\", i*4, buffer[i]);\n\t}\n\tint status = buffer[3];\n\tint more = (status >> 30) & 1;\n\tint sc = (status >> 17) & 0xff;\n\tint sct = (status >> 25) & 0x7;\n\tfprintf(stderr, \"status=%08x more=%d sc=%x sct=%x\\n\", status, more, sc, sct);\n    }\n    \n    {\n\t// let's do a read\n\tnvme_io_cmd *cmd = (nvme_io_cmd *)(rootPort->ioSubmissionQueue.buffer() + (entry+0)*64);\n\tmemset(cmd, 0, 64);\n\tcmd->opcode = 2; // read\n\tcmd->cid = 42;\n\tcmd->nsid = 1;\n\tcmd->prp1 = (rootPort->transferBufferRef << 24) + 0;\n\tcmd->cdw10 = 0; // starting LBA.lower\n\tcmd->cdw11 = 0; // starting LBA.upper\n\tcmd->cdw12 = 7; // read 8 blocks\n\n\tfprintf(stderr, \"enqueueing IO read request\\n\");\n\t// update submission queue tail\n\trootPort->write32(0x1000+(2*1*(4 << 0)), 1);\n\tsleep(1);\n\t{\n\t    int *buffer = (int *)(rootPort->ioCompletionQueue.buffer() + (entry+0)*16);\n\t    for (int i = 0; i < 16; i++) {\n\t\tfprintf(stderr, \"response[%02x]=%08x\\n\", i*4, buffer[i]);\n\t    }\n\t    int status = buffer[3];\n\t    int more = (status >> 30) & 1;\n\t    int sc = (status >> 17) & 0xff;\n\t    int sct = (status >> 25) & 0x7;\n\t    fprintf(stderr, \"status=%08x more=%d sc=%x sct=%x\\n\", status, more, sc, sct);\n\t}\n\t{\n\t    int *buffer = (int *)(rootPort->transferBuffer.buffer() + (entry+0)*16);\n\t    for (int i = 0; i < 8*512/4; i++) {\n\t\tfprintf(stderr, \"data read [%02x]=%08x\\n\", i*4, buffer[i]);\n\t    }\n\t}\n    }\n\n}\n\nint main(int argc, const char **argv)\n{\n    RootPort rootPort;\n\n    sleep(1);\n    fprintf(stderr, \"Enabling I/O and Memory, bus master, parity and SERR\\n\");\n    rootPort.writeCtl(0x004, 0x147);\n    rootPort.readCtl(0x004);\n    rootPort.readCtl(0x130);\n    rootPort.readCtl(0x134);\n    rootPort.readCtl(0x18);\n    // required\n    rootPort.writeCtl(0x18, 0x00070100);\n    rootPort.readCtl(0x18);\n    rootPort.writeCtl(0x10, 0xFFFFFFFF);\n    rootPort.writeCtl(0x14, 0xFFFFFFFF);\n    fprintf(stderr, \"Root Port BAR0: %08x\\n\", rootPort.readCtl((0 << 20) + 0x10));\n    fprintf(stderr, \"Root Port BAR1: %08x\\n\", rootPort.readCtl((0 << 20) + 0x14));\n    rootPort.writeCtl(0x10, 0x0);\n    rootPort.writeCtl(0x14, 0x0);\n    fprintf(stderr, \"Enabling card I/O and Memory, bus master, parity and SERR\\n\");\n    rootPort.writeCtl((1 << 20) + 4, 0x147);\n    fprintf(stderr, \"reading config regs\\n\");\n    rootPort.readCtl((1 << 20) + 0);\n    rootPort.readCtl((1 << 20) + 4);\n    rootPort.readCtl((1 << 20) + 8);\n    fprintf(stderr, \"Card BAR0: %08x\\n\", rootPort.readCtl((1 << 20) + 0x10));\n    fprintf(stderr, \"reading AXI BAR\\n\");\n    rootPort.readCtl(0x208);\n    rootPort.readCtl(0x20C);\n    rootPort.readCtl(0x210);\n    fprintf(stderr, \"writing card BAR0\\n\");\n    for (int i = 0; i < 6; i++) {\n\trootPort.writeCtl((1 << 20) + 0x10 + 4*i, 0xffffffff);\n\trootPort.readCtl((1 << 20) + 0x10 + 4*i);\n    }\n    rootPort.writeCtl((1 << 20) + 0x10, 0);\n    rootPort.writeCtl((1 << 20) + 0x14, 0x0000);\n    rootPort.writeCtl((1 << 20) + 0x18, 0x02200000); // BAR1\n    rootPort.writeCtl((1 << 20) + 0x1c, 0x00000000);\n    rootPort.writeCtl((1 << 20) + 0x10+5*4, 0); // sata card\n    fprintf(stderr, \"reading card BARs\\n\");\n    for (int i = 0; i < 6; i++) {\n\tfprintf(stderr, \"BAR%d: %08x\\n\", i, rootPort.readCtl((1 << 20) + 0x10 + 4*i));\n    }\n\n    rootPort.readCtl((1 << 20) + 0x10);\n    rootPort.readCtl((1 << 20) + 0x14);\n    fprintf(stderr, \"Enabling bridge\\n\");\n    rootPort.readCtl(0x148);\n    rootPort.writeCtl(0x148, 1);\n    rootPort.readCtl(0x148);\n    rootPort.readCtl(0x140);\n    rootPort.writeCtl(0x140, 0x00010000);\n    rootPort.readCtl(0x140);\n\n    if (1) {\n\tfprintf(stderr, \"Reading card memory space BAR0\\n\");\n\tfor (int i = 0; i < 8; i++)\n\t    fprintf(stderr, \"BAR0[%02x]=%08x\\n\", i*4, rootPort.read32(0 + i*4));\n    }\n    if (0) {\n\tfprintf(stderr, \"Reading card memory space BAR2\\n\");\n\tfor (int i = 0; i < 8; i++)\n\t    fprintf(stderr, \"BAR1[%02x]=%08x\\n\", i*4, rootPort.read32(0x02200000 + i*4));\n    }\n\n    fprintf(stderr, \"CTS %08x\\n\", rootPort.read32( 0x1c));\n    rootPort.write32(0x1c, 0x10); // clear reset bit\n    fprintf(stderr, \"CTS %08x\\n\", rootPort.read32( 0x1c));\n\n    // disable\n    rootPort.write32(0x14, 0);\n    // reset\n    rootPort.write32(0x20, 0x4e564d65);\n    sleep(1);\n    fprintf(stderr, \"Reset reg %08x\\n\", rootPort.read32(0x20));\n    fprintf(stderr, \"CTS %08x\\n\", rootPort.read32( 0x1c));\n\n    fprintf(stderr, \"CMB size     %08x\\n\", rootPort.read32(0x38));\n    fprintf(stderr, \"CMB location %08x\\n\", rootPort.read32(0x3c));\n    uint64_t adminCompletionBaseAddress = rootPort.adminCompletionQueueRef << 24;\n    uint64_t adminSubmissionBaseAddress = rootPort.adminSubmissionQueueRef << 24;\n    fprintf(stderr, \"Setting up Admin submission and completion queues %llx %llx\\n\",\n\t    (long long)adminCompletionBaseAddress, (long long)adminSubmissionBaseAddress);\n    rootPort.write(0x28, adminSubmissionBaseAddress);\n    fprintf(stderr, \"AdminSubmissionBaseAddress %08llx\\n\", (long long)rootPort.read(0x28));\n    rootPort.write(0x30, adminCompletionBaseAddress);\n    fprintf(stderr, \"AdminCompletionBaseAddress %08llx\\n\", (long long)rootPort.read(0x30));\n    rootPort.write32(0x24, 0x003f003f);\n    fprintf(stderr, \"register 0x20 %x\\n\", rootPort.read32(0x20));\n\n    fprintf(stderr, \"CTS %08x\\n\", rootPort.read32( 0x1c));\n    // CC.enable\n    rootPort.write32(0x14, 1);\n    fprintf(stderr, \"CTS %08x\\n\", rootPort.read32( 0x1c));\n\n    //identify(&rootPort);\n    allocIOQueues(&rootPort, 0);\n\n    fprintf(stderr, \"CTS %08x\\n\", rootPort.read32( 0x1c));\n\n    return 0;\n}\n\n"
  },
  {
    "path": "tests/rootport/rootport.json",
    "content": "{\n    \"pcie_refclk_p\": {\n\t\"pcie\": \"sys_clk_p\"\n    },\n    \"pcie_refclk_n\": {\n\t\"pcie\": \"sys_clk_n\"\n    },\n    \"RST_N_pcie_sys_reset_n\": {\n\t\"pcie\": \"sys_reset_n\"\n    }\n}\n"
  },
  {
    "path": "tests/rootport/rootport.xdc",
    "content": "create_clock -name root_pci_refclk -period 10 [get_ports pcie_refclk_p]\n"
  },
  {
    "path": "tests/serialportal/Makefile",
    "content": "CONNECTALDIR?=../..\nS2H_INTERFACES = SerialPortalRequest:SerialPortalTest.request EchoIndication:SerialPortalTest.echoIndication SimpleRequest:SerialPortalTest.simpleRequest\nH2S_INTERFACES = SerialPortalTest:SerialPortalIndication,EchoRequest,SimpleRequest\n\nINTERFACES = EchoRequest EchoIndication\n\nBSVFILES = SerialPortalIfc.bsv $(CONNECTALDIR)/examples/echo/Echo.bsv $(CONNECTALDIR)/examples/simple/Simple.bsv\nCPPFILES= serialportal.cpp\n\nCONNECTALFLAGS += -I $(CONNECTALDIR)/examples/simple\n\nPINOUT_FILE += rs232.json\nPIN_TYPE = SerialPortalPins\nPIN_TYPE_INCLUDE = SerialPortalIfc\nAUTOTOP = --interface pins:SerialPortalTest.pins\ninclude $(CONNECTALDIR)/Makefile.connectal\n"
  },
  {
    "path": "tests/serialportal/SerialPortalIfc.bsv",
    "content": "// Copyright (c) 2016 Connectal Project\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\nimport RS232::*;\n\ninterface SerialPortalRequest;\n   method Action setDivisor(Bit#(16) d);\nendinterface\n\ninterface SerialPortalIndication;\n   method Action rx(Bit#(8) c);\nendinterface\n\ninterface SerialPortalPins;\n   interface RS232 uart;\n   interface Clock deleteme_unused_clock;\nendinterface\n   \nexport RS232(..);\nexport SerialPortalRequest(..);\nexport SerialPortalIndication(..);\nexport SerialPortalPins(..);\n"
  },
  {
    "path": "tests/serialportal/SerialPortalTest.bsv",
    "content": "// Copyright (c) 2016 Connectal Project\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\nimport BuildVector::*;\nimport Clocks::*;\nimport ClientServer::*;\nimport Connectable::*;\nimport Gearbox::*;\nimport GetPut::*;\nimport RS232::*;\nimport Vector::*;\n\nimport Pipe::*;\nimport Portal::*;\nimport SharedMemoryPortal::*;\n\nimport SerialPortalIfc::*;\nimport Echo::*;\nimport EchoRequest::*;\nimport EchoIndication::*;\nimport Simple::*;\nimport SimpleRequest::*;\n\ninterface SerialPortalTest;\n   interface SerialPortalRequest request;\n   interface EchoIndication echoIndication;\n   interface SimpleRequest  simpleRequest;\n   interface SerialPortalPins    pins;\nendinterface\n\nmodule mkSerialPortalTest#(SerialPortalIndication indication, EchoRequest echoRequest, SimpleRequest simpleRequest)(SerialPortalTest);\n\n   let clock <- exposeCurrentClock();\n   let reset <- exposeCurrentReset();\n\n   // 250MHz clock\n   //   9600 baud: divisor=26042\n   // 115200 baud: divisor=134\n   Reg#(Bit#(16)) divisor <- mkReg(134);\n   UART#(16) uart <- mkUART(8, EVEN, STOP_1, divisor);\n\n   SerialPortalDemux#(3) serialEchoRequestDemux <- mkSerialPortalDemux(Method); // why the asymmetry?\n   let echoRequestInput <- mkEchoRequestInput();\n   mkConnection(echoRequestInput.pipes, echoRequest);\n   mkConnection(serialEchoRequestDemux.data, echoRequestInput.portalIfc.requests);\n\n   SerialPortalDemux#(12) serialSimpleRequestDemux <- mkSerialPortalDemux(Method); // why the asymmetry?\n   let simpleRequestInput <- mkSimpleRequestInput();\n   mkConnection(simpleRequestInput.pipes, simpleRequest);\n   mkConnection(serialSimpleRequestDemux.data, simpleRequestInput.portalIfc.requests);\n\n   SerialPortalDemux#(2) portalDemux <- mkSerialPortalDemux(Portal);\n   mkConnection(portalDemux.data[0], serialEchoRequestDemux.inputPipe);\n   mkConnection(portalDemux.data[1], serialSimpleRequestDemux.inputPipe);\n\n   Gearbox#(1,4,Bit#(8)) tx_gb <- mk1toNGearbox(clock,reset,clock,reset);\n   mkConnection(uart.tx, toPut(toPipeIn(tx_gb)));\n   mkConnection(mapPipe(pack,toPipeOut(tx_gb)), portalDemux.inputPipe);\n\n   let echoIndicationOutput <- mkEchoIndicationOutput;\n   Vector#(2,PipeOut#(Bit#(32))) echoMethodPipes <- genWithM(mkFramedMessagePipe(0, echoIndicationOutput.portalIfc, getEchoIndicationMessageSize));\n   PipeOut#(Bit#(32)) serialEchoPortalPipe <- mkSerialPortalMux(echoMethodPipes);\n\n   let simpleRequestOutput <- mkSimpleRequestOutput;\n   Vector#(12,PipeOut#(Bit#(32))) simpleMethodPipes <- genWithM(mkFramedMessagePipe(1, simpleRequestOutput.portalIfc, getSimpleRequestMessageSize));\n   PipeOut#(Bit#(32)) serialSimplePortalPipe <- mkSerialPortalMux(simpleMethodPipes);\n\n   PipeOut#(Bit#(32)) portalMux <- mkSerialPortalMux(vec(serialEchoPortalPipe, serialSimplePortalPipe));\n\n   Gearbox#(4,1,Bit#(8)) rx_gb <- mkNto1Gearbox(clock,reset,clock,reset);\n   rule rl_rx_gb;\n      let v <- toGet(portalMux).get();\n      rx_gb.enq(unpack(v));\n   endrule\n   rule rl_rx;\n      let char = rx_gb.first()[0]; rx_gb.deq();\n      uart.rx.put(char);\n      indication.rx(char);\n   endrule\n\n   interface SerialPortalRequest request;\n      method Action setDivisor(Bit#(16) d);\n\t divisor <= d;\n      endmethod\n   endinterface\n   interface EchoIndication echoIndication = echoIndicationOutput.ifc;\n   interface SimpleRequest  simpleRequest  = simpleRequestOutput.ifc;\n   interface SerialPortalPins pins;\n      interface uart = uart.rs232;\n      interface deleteme_unused_clock = clock;\n   endinterface\nendmodule\n"
  },
  {
    "path": "tests/serialportal/rs232.json",
    "content": "{\n    \"uart_SOUT\": {\n\t\"uart\": \"d_out\"\n    },\n    \"uart_SIN\": {\n\t\"uart\": \"d_in\"\n    }\n}\n"
  },
  {
    "path": "tests/serialportal/serialportal.cpp",
    "content": "/* Copyright (c) 2016 Connectal Project\n *\n * Permission is hereby granted, free of charge, to any person obtaining a\n * copy of this software and associated documentation files (the \"Software\"),\n * to deal in the Software without restriction, including without limitation\n * the rights to use, copy, modify, merge, publish, distribute, sublicense,\n * and/or sell copies of the Software, and to permit persons to whom the\n * Software is furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n * DEALINGS IN THE SOFTWARE.\n */\n#include <errno.h>\n#include <fcntl.h>\n#include <stdio.h>\n#include <stdlib.h>\n#include <termios.h>\n#include <unistd.h>\n#include <sys/types.h>\n#include <sys/stat.h>\n\n#include \"portal.h\"\n#include \"SerialPortalIndication.h\"\n#include \"SerialPortalRequest.h\"\n#include \"EchoRequest.h\"\n#include \"EchoIndication.h\"\n#include \"SimpleRequest.h\"\n\n#include <assert.h>\n\n#if 1\n#define TEST_ASSERT(A) assert(A)\n#else\n#define TEST_ASSERT(A) {}\n#endif\n\n#define NUMBER_OF_TESTS 12\n\nuint32_t v1a = 42;\nuint32_t v2a = 2;\nuint32_t v2b = 4;\n\nclass Simple : public SimpleRequestWrapper\n{  \npublic:\n  uint32_t cnt;\n  uint32_t times;\n  void incr_cnt(){\n    if (++cnt == NUMBER_OF_TESTS)\n      exit(0);\n  }\n  void say1(uint32_t a) {\n    fprintf(stderr, \"received Simple.say1(%d)\\n\", a);\n    TEST_ASSERT(a == v1a);\n    incr_cnt();\n  }\n  void say2(uint16_t a, uint16_t b) {\n    fprintf(stderr, \"received Simple.say2(%d %d)\\n\", a, b);\n    TEST_ASSERT(a == v2a);\n    TEST_ASSERT(b == v2b);\n    incr_cnt();\n  }\n  Simple(unsigned int id, PortalTransportFunctions *transport = 0, void *param = 0, PortalPoller *poller = 0)\n    : SimpleRequestWrapper(id, transport, param, poller), cnt(0){}\n};\n\nclass SerialPortalIndication : public SerialPortalIndicationWrapper\n{  \npublic:\n  void rx ( uint8_t c ) {\n    fprintf(stderr, \"rx=%x:%c\\n\", c, c);\n  }\n  SerialPortalIndication(unsigned int id) : SerialPortalIndicationWrapper(id) {}\n};\n\nclass EchoRequest : public EchoRequestWrapper\n{\npublic:\n    virtual void say(uint32_t v) {\n      fprintf(stderr, \"received EchoRequest.say: %x\\n\", v);\n    }\n    virtual void say2(uint16_t a, uint16_t b) {\n      fprintf(stderr, \"received EchoRequest.say2: %d %d\\n\", a, b);\n    }\n    virtual void setLeds ( const uint8_t v ) {}\n    EchoRequest(unsigned int id) : EchoRequestWrapper(id) {}\n};\n\nclass EchoIndication : public EchoIndicationWrapper\n{\npublic:\n    virtual void heard ( const uint32_t v ) {\n\tfprintf(stderr, \"EchoIndication.heard v=%x\\n\", v);\n    }\n    virtual void heard2 ( const uint16_t a, const uint16_t b ) {\n\tfprintf(stderr, \"EchoIndication.heard2 a=%#x b=%#x\\n\", a, b);\n    }\n    EchoIndication(int id, PortalTransportFunctions *item = 0, void *param = 0, PortalPoller *poller = 0)\n\t: EchoIndicationWrapper(id, item, param, poller) {\n    }\n};\n\n\nint initSerial(const char *dev)\n{\n\n  struct termios terminfo;\n  int rc;\n  int fd = open(dev, O_RDWR | O_NONBLOCK);\n  tcflush(fd, TCIOFLUSH);\n  tcgetattr(fd, &terminfo);\n  terminfo.c_cflag = CS8 | CLOCAL | CREAD | PARENB;\n  terminfo.c_cflag &= ~CRTSCTS; // needed for /dev/tty.SLAB_USBtoUART\n  terminfo.c_iflag = IGNCR;\n  terminfo.c_lflag &= ~(ICANON | ECHO | ISIG);\n  cfsetspeed(&terminfo, B115200);\n  rc = tcsetattr(fd, TCSANOW, &terminfo);\n  if (rc != 0)\n      fprintf(stderr, \"tcsetattr rc=%d errno=%d\\n\", rc, errno);\n\n  return fd;\n}\n\nint main(int argc, const char **argv)\n{\n  SerialPortalIndication indication(IfcNames_SerialPortalIndicationH2S);\n  EchoRequest echo(IfcNames_EchoRequestH2S);\n  Simple simple(IfcNames_SimpleRequestH2S);\n\n  SerialPortalRequestProxy *device = new SerialPortalRequestProxy(IfcNames_SerialPortalRequestS2H);\n  EchoIndicationProxy *echoIndication = new EchoIndicationProxy(IfcNames_EchoIndicationS2H);\n  SimpleRequestProxy *simpleRequest = new SimpleRequestProxy(IfcNames_SimpleRequestS2H);\n\n  if (!argv[1]) {\n      //realpath(\"/sys/class/tty/ttyUSB0/device/driver/\");\n      fprintf(stderr, \"usage: %s /dev/ttyUSBn\\n\", argv[0]);\n      return -EINVAL;\n  }\n\n  int serial_fd = initSerial(argv[1]);\n  PortalSharedParam paramSerial;\n  paramSerial.serial.serial_fd = serial_fd;\n\n  Portal *mcommon = new Portal(0, 0, sizeof(uint32_t), portal_serialmux_handler, NULL, &transportSerial, &paramSerial, 0);\n  PortalMuxParam param = {};\n  param.pint = &mcommon->pint;\n\n  EchoRequestProxy   echoSerial(0, &transportSerialMux, &param);\n  SimpleRequestProxy simpleSerial(1, &transportSerialMux, &param);\n\n  EchoIndication serialEchoIndication(0, &transportSerialMux, &param);\n  Simple         serialSimple(1, &transportSerialMux, &param);\n\n  device->setDivisor(134);\n  sleep(2);\n\n  echoSerial.say(0x6789);\n  echoSerial.say2(0x22, 0x23);\n\n  sleep(2);\n  simpleSerial.say1(v1a);\n  simpleSerial.say2(v2a, v2b);\n\n  sleep(2);\n  echoIndication->heard2(0x68,0x47);\n  echoIndication->heard(0x22);\n\n  sleep(2);\n  simpleRequest->say1(19);\n\n  while (1) {\n    // wait\n  }\n}\n"
  },
  {
    "path": "tests/simmethodtime/Makefile",
    "content": "CONNECTALDIR?=../..\nS2H_INTERFACES = SimmRequest:Simm.request\nH2S_INTERFACES = Simm:SimmIndication\n\nBSVFILES = Simm.bsv\nCPPFILES= test.cpp\nCONNECTALFLAGS += -lpapi\n\ninclude $(CONNECTALDIR)/Makefile.connectal\n"
  },
  {
    "path": "tests/simmethodtime/Simm.bsv",
    "content": "// Copyright (c) 2015 The Connectal Project\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\nimport Vector::*;\n\ninterface SimmIndication;\n   method Action resp(Bit#(32) v);\nendinterface\n\ninterface SimmRequest;\n   method Action shortreq(Bit#(32) v);\n   method Action longreq(Vector#(100, Bit#(32)) v);\nendinterface\n\ninterface Simm;\n   interface SimmRequest request;\nendinterface\n\nmodule mkSimm#(SimmIndication indication)(Simm);\n   interface SimmRequest request;\n      method Action shortreq(Bit#(32) v);\n      endmethod\n      method Action longreq(Vector#(100, Bit#(32)) v);\n      endmethod\n   endinterface\nendmodule\n"
  },
  {
    "path": "tests/simmethodtime/test.cpp",
    "content": "/* Copyright (c) 2014 Quanta Research Cambridge, Inc\n *\n * Permission is hereby granted, free of charge, to any person obtaining a\n * copy of this software and associated documentation files (the \"Software\"),\n * to deal in the Software without restriction, including without limitation\n * the rights to use, copy, modify, merge, publish, distribute, sublicense,\n * and/or sell copies of the Software, and to permit persons to whom the\n * Software is furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n * DEALINGS IN THE SOFTWARE.\n */\n#include \"SimmRequest.h\"\n\n#include \"papi.h\"\n\n#define NUM_EVENTS 4\nstatic void perfinit(void)\n{\n  static int once = 1;\n  int event[NUM_EVENTS] = {PAPI_TOT_INS, PAPI_TOT_CYC, PAPI_BR_MSP, PAPI_L1_DCM };\n  if (once) {\n    once = 0;\n    /* Start counting events */\n    if (PAPI_start_counters(event, NUM_EVENTS) != PAPI_OK) {\n        fprintf(stderr, \"PAPI_start_counters - FAILED\\n\");\n        exit(1);\n    }\n  }\n}\nstatic void perfprint(long long *perfvalues, const char *name)\n{\n    printf(\"%s: Total instructions: %6lld;\", name, perfvalues[0]);\n    printf(\"Total cycles: %6lld;\", perfvalues[1]);\n    //printf(\"Instr per cycle: %2.3f;\", (double)perfvalues[0] / (double) perfvalues[1]);\n    //printf(\"Branches mispredicted: %6lld;\", perfvalues[2]);\n    //printf(\"L1 Cache misses: %6lld;\", perfvalues[3]);\n    printf(\"\\n\");\n}\n\nint main(int argc, const char **argv)\n{\n    long long perfvalues1[NUM_EVENTS], perfvalues2[NUM_EVENTS];\n    bsvvector_Luint32_t_L100 testvec = {0};\n    SimmRequestProxy *req = new SimmRequestProxy(IfcNames_SimmRequestS2H);\n    perfinit();\n    for (int i = 0; i < 10; i++) {\n        if (PAPI_read_counters(perfvalues1, NUM_EVENTS) != PAPI_OK) {\n            fprintf(stderr, \"PAPI_read_counters - FAILED\\n\");\n            exit(1);\n        }\n        req->shortreq(1);\n        if (PAPI_read_counters(perfvalues1, NUM_EVENTS) != PAPI_OK) {\n            fprintf(stderr, \"PAPI_read_counters - FAILED\\n\");\n            exit(1);\n        }\n        req->longreq(testvec);\n        if (PAPI_read_counters(perfvalues2, NUM_EVENTS) != PAPI_OK) {\n            fprintf(stderr, \"PAPI_read_counters - FAILED\\n\");\n            exit(1);\n        }\n        perfprint(perfvalues1, \"short\");\n        perfprint(perfvalues2, \"long\");\n    }\n    return 0;\n}\n"
  },
  {
    "path": "tests/simple_manual/Makefile",
    "content": "CONNECTALDIR?=../..\nS2H_INTERFACES = SimpleRequest:Simple.request\nH2S_INTERFACES = Simple:SimpleRequest\n\nBSVFILES = Simple.bsv\n#original user program CPPFILES=testsimple.cpp\nCPPFILES=simple_manual.c\nCONNECTALFLAGS += -D NO_CPP_PORTAL_CODE\n\ninclude $(CONNECTALDIR)/Makefile.connectal\n"
  },
  {
    "path": "tests/simple_manual/Simple.bsv",
    "content": "\n// Copyright (c) 2014 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\ninterface SimpleRequest;\n    method Action say1(Bit#(32) v);\n    method Action say2(Bit#(32) a, Bit#(32) b);\nendinterface\ninterface Simple;\n    interface SimpleRequest request;\nendinterface\n\nmodule mkSimple#(SimpleRequest indication)(Simple);\n   let verbose = False;\n\n   interface SimpleRequest request;\n   method Action say1(Bit#(32) v);\n      indication.say1(v);\n   endmethod\n   \n   method Action say2(Bit#(32) a, Bit#(32) b);\n      indication.say2(a,b);\n   endmethod\n   endinterface\nendmodule\n"
  },
  {
    "path": "tests/simple_manual/kernel/Makefile",
    "content": "\n# grep get_pcie_portal_descriptor /proc/kallsyms \n\n###################### Flags for using KC705   ###################\n#BOARD=kc705\n###################### Flags for using VC707   ###################\n#BOARD=vc707\n###################### Flags for using zedboard ##################\n#BOARD=zedboard\n###################### Flags for using Bluesim ###################\nBOARD=bluesim\n###################### End of target h/w flags ###################\n\nifeq ($(BOARD),bluesim)\n    HARDWARE_FLAGS=-DBSIM\nendif\n\nexport KROOT=/lib/modules/$(shell uname -r)/build\nCPPDIR=../../../cpp\nBOARDDIR=../$(BOARD)/jni\nDRIVERDIR=$(src)/../../../\nCONNECTAL_MODULE_NAME:=connectaluser_$(USER)\n\nKBUILD_EXTRA_SYMBOLS := $(DRIVERDIR)/drivers/pcieportal/Module.symvers \\\n      $(DRIVERDIR)/drivers/portalmem/Module.symvers\n\n$(CONNECTAL_MODULE_NAME)-y := ../simple_manual.o \\\n     $(BOARDDIR)/SimpleIndication.o \\\n     $(BOARDDIR)/SimpleRequest.o \\\n     $(CPPDIR)/portal.o \\\n     $(CPPDIR)/transportSocket.o \\\n     $(CPPDIR)/kernel_module.o\n\n$(CONNECTAL_MODULE_NAME)-n := $(CPPDIR)/dmaManager.o\n\nobj-m := $(CONNECTAL_MODULE_NAME).o\n\nccflags-y := -I$(src)/.. -I$(DRIVERDIR) -I$(src)/$(CPPDIR) -I$(src)/$(BOARDDIR) $(HARDWARE_FLAGS)\n\ndefault:\n\t$(MAKE) -C $(KROOT) M=$(PWD) modules\n\nclean:\n\t$(MAKE) -C $(KROOT) M=$(PWD) clean\n\trm -f a.out bsim_relay socket_for_bluesim tmp.bluesim.makefile.pid\n\nCURRENTMOD=$(shell lsmod | grep $(CONNECTAL_MODULE_NAME))\n\nrun: host\nifeq ($(BOARD),bluesim)\n\t@echo running bsim\n\t../bluesim/bin/bsim& echo $$! >tmp.bluesim.makefile.pid\nelse\n\tfpgajtag ../$(BOARD)/bin/mkTop.bin.gz\nendif\nifneq (\"$(CURRENTMOD)\", \"\")\n\tsudo rmmod $(CONNECTAL_MODULE_NAME)\n\t#sudo rmmod bdbm_drv\nendif\n\tsudo modprobe pcieportal\n\tsudo modprobe portalmem\n\tsudo insmod $(CONNECTAL_MODULE_NAME).ko\n\t#sudo insmod bdbm_drv.ko\nifeq ($(BOARD),bluesim)\n\tCONNECTAL_MODULE_NAME=$(CONNECTAL_MODULE_NAME) ./bsim_relay\n\tkill `cat tmp.bluesim.makefile.pid`\n\t#killall bluetcl\nendif\n\tsudo rmmod $(CONNECTAL_MODULE_NAME)\n\t#sudo rmmod bdbm_drv\n\tdmesg | tail -30\n\t@rm -f tmp.bluesim.makefile.pid\n\n#\n# Target for making userspace bsim_relay program\nCINCL=../../..\nHOSTSOURCES=$(CPPDIR)/bsim_relay.c $(CPPDIR)/sock_utils.c $(CPPDIR)/portalSocket.c $(CPPDIR)/portal.c\n\nhost: $(HOSTSOURCES)\nifeq ($(BOARD),bluesim)\n\tgcc -o bsim_relay -g -I$(CINCL)/cpp -I$(CINCL) -DNO_CPP_PORTAL_CODE -DNO_POLLER_SUPPORT $(HOSTSOURCES) -lpthread\nendif\n"
  },
  {
    "path": "tests/simple_manual/simple_manual.c",
    "content": "// Copyright (c) 2014 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\n#include \"GeneratedTypes.h\"\n\nstatic int v1a = 42;\nstatic int v2a = 2;\nstatic int v2b = 4;\n#define MAX_INDARRAY 2\nstatic PortalInternal intarr[MAX_INDARRAY];\n//static PORTAL_INDFUNC indfn[MAX_INDARRAY];\n\nint SimpleIndicationWrapperheard1_cb (  struct PortalInternal *p, const uint32_t v )\n{\n    PORTAL_PRINTF(\"heard1(%d)\\n\", v);\n    return 0;\n}\nint SimpleIndicationWrapperheard2_cb (  struct PortalInternal *p, const uint32_t a, const uint32_t b )\n{\n    PORTAL_PRINTF(\"heard2(%d %d)\\n\", a, b);\n    return 0;\n}\n\nstatic void manual_event(void)\n{\n    int i;\n    for (i = 0; i < MAX_INDARRAY; i++)\n      event_hardware(&intarr[i]);\n}\n\nSimpleRequestCb simple_cbTable = {\n   portal_disconnect,\n   SimpleIndicationWrapperheard1_cb,\n   SimpleIndicationWrapperheard2_cb,\n};\nint main(int argc, const char **argv)\n{\n   init_portal_internal(&intarr[0], IfcNames_SimpleRequestS2H, DEFAULT_TILE, NULL, NULL, NULL, NULL, SimpleRequest_reqinfo); // portal 1\n   init_portal_internal(&intarr[1], IfcNames_SimpleRequestH2S, DEFAULT_TILE, SimpleRequest_handleMessage, &simple_cbTable, NULL, NULL, SimpleRequest_reqinfo); // portal 2\n\n   intarr[0].item->enableint(&intarr[0], 0);\n   intarr[1].item->enableint(&intarr[1], 0);\n   PORTAL_PRINTF(\"Main::calling say1(%d)\\n\", v1a);\n   //device->say1(v1a);  \n   SimpleRequest_say1 (&intarr[0], v1a);\n   manual_event();\n\n   PORTAL_PRINTF(\"Main::calling say2(%d, %d)\\n\", v2a,v2b);\n   //device->say2(v2a,v2b);\n   SimpleRequest_say2 (&intarr[0], v2a, v2b);\n   manual_event();\n   return 0;\n}\n"
  },
  {
    "path": "tests/simple_manual/testsimple.cpp",
    "content": "\n// Copyright (c) 2014 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\n#include <stdio.h>\n#include <unistd.h>\n#include \"SimpleIndication.h\"\n#include \"SimpleRequest.h\"\n\nint v1a = 42;\nint v2a = 2;\nint v2b = 4;\n\nclass SimpleIndication : public SimpleIndicationWrapper\n{  \npublic:\n  virtual void heard1(uint32_t a) {\n    fprintf(stderr, \"heard1(%d)\\n\", a);\n  }\n  virtual void heard2(uint32_t a, uint32_t b) {\n    fprintf(stderr, \"heard2(%d %d)\\n\", a, b);\n  }\n  SimpleIndication(unsigned int id) : SimpleIndicationWrapper(id) {}\n};\n\nint main(int argc, const char **argv)\n{\n  SimpleIndication *indication = new SimpleIndication(IfcNames_SimpleIndication);\n  SimpleRequestProxy *device = new SimpleRequestProxy(IfcNames_SimpleRequest);\n\n  fprintf(stderr, \"Main::calling say1(%d)\\n\", v1a);\n  device->say1(v1a);  \n\n  fprintf(stderr, \"Main::calling say2(%d, %d)\\n\", v2a,v2b);\n  device->say2(v2a,v2b);\n\n  fprintf(stderr, \"Main::about to go to sleep\\n\");\n  sleep(5);\n  exit(0);\n}\n"
  },
  {
    "path": "tests/spi/ConnectalProjectConfig.bsv",
    "content": "`define ConnectalVersion 15.11.1\n`define NumberOfMasters 1\n`define PinType Empty\n`define PinTypeInclude Misc\n`define NumberOfUserTiles 1\n`define SlaveDataBusWidth 32\n`define SlaveControlAddrWidth 5\n`define BurstLenSize 10\n`define project_dir $(DTOP)\n`define MainClockPeriod 20\n`define DerivedClockPeriod 10.000000\n`define BsimHostInterface \n`define PhysAddrWidth 40\n`define SIMULATION \n`define BOARD_bluesim \n"
  },
  {
    "path": "tests/spi/Makefile",
    "content": "CONNECTALDIR?=../..\n\nrun: spiTestBench\n\t./spiTestBench\n\tgtkwave dump.vcd spitest.gtkw\n\nspiTestBench: $(CONNECTALDIR)/lib/bsv/ConnectalSpi.bsv\n\tmkdir -p obj\n\tbsc --show-schedule -sim -info-dir obj -bdir obj -p +:$(CONNECTALDIR)/lib/bsv:$(CONNECTALDIR)/bsv -g mkSpiTestBench -u $(CONNECTALDIR)/lib/bsv/ConnectalSpi.bsv\n\tbsc --show-schedule -sim -info-dir obj -bdir obj -e mkSpiTestBench -o spiTestBench\n\nclean:\n\trm -rf spiTestBench* mkSpiTestBench.* model_mkSpiTestBench.* dump.vcd obj\n"
  },
  {
    "path": "tests/spi/spitest.gtkw",
    "content": "[*]\n[*] GTKWave Analyzer v3.3.58 (w)1999-2014 BSI\n[*] Wed Apr  1 15:21:05 2015\n[*]\n[dumpfile] \"/scratch/jamey/connectal/tests/spi/dump.vcd\"\n[dumpfile_mtime] \"Wed Apr  1 15:19:07 2015\"\n[dumpfile_size] 10945\n[savefile] \"/scratch/jamey/connectal/tests/spi/spitest.gtkw\"\n[timestart] 0\n[size] 1302 874\n[pos] -1 -1\n*-8.000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1\n[treeopen] main.\n[sst_width] 224\n[signals_width] 150\n[sst_expanded] 1\n[sst_vpaned_height] 248\n@28\nmain.top.probeMiso$PROBE\nmain.top.probeMosi$PROBE\nmain.top.probeSelN$PROBE\n[pattern_trace] 1\n[pattern_trace] 0\n"
  },
  {
    "path": "tests/spikehw/AxiEthBufferBvi.bsv",
    "content": "\n/*\n   ../../generated/scripts/importbvi.py\n   -o\n   AxiEthBufferBvi.bsv\n   -I\n   AxiEthBuffer\n   -P\n   AxiEthBuffer\n   -c\n   S_AXI_ACLK\n   -r\n   S_AXI_ARESETN\n   -c\n   AXI_STR_TXD_ACLK\n   -r\n   AXI_STR_TXD_ARESETN\n   -c\n   AXI_STR_TXC_ACLK\n   -r\n   AXI_STR_TXC_ARESETN\n   -c\n   AXI_STR_RXD_ACLK\n   -r\n   AXI_STR_RXD_ARESETN\n   -c\n   AXI_STR_RXS_ACLK\n   -r\n   AXI_STR_RXS_ARESETN\n   -c\n   rx_mac_aclk\n   -r\n   rx_reset\n   -c\n   tx_mac_aclk\n   -r\n   tx_reset\n   -r\n   PHY_RST_N\n   -c\n   GTX_CLK\n   -n\n   speed_is_10_100\n   -f\n   S_AXI_2TEMAC\n   -n\n   RESET2PCSPMA\n   -n\n   RESET2TEMACn\n   -f\n   AXI_STR_RXD\n   -f\n   AXI_STR_RXS\n   -f\n   AXI_STR_TXC\n   -f\n   AXI_STR_TXD\n   cores/nfsume/eth_buf/eth_buf_stub.v\n*/\n\nimport Clocks::*;\nimport DefaultValue::*;\nimport XilinxCells::*;\nimport GetPut::*;\nimport Vector::*;\nimport AxiBits::*;\nimport AxiStream::*;\n\ninterface AxiEthBufferClocks;\n   interface Clock axi_str_rxd_aclk;\n   interface Clock axi_str_rxs_aclk;\n   interface Clock axi_str_txc_aclk;\n   interface Clock axi_str_txd_aclk;\n   interface Clock gtx_clk;\n   interface Clock rx_mac_aclk;\n   interface Clock s_axi_aclk;\n   interface Clock tx_mac_aclk;\n   interface Reset axi_str_rxd_aresetn;\n   interface Reset axi_str_rxs_aresetn;\n   interface Reset axi_str_txc_aresetn;\n   interface Reset axi_str_txd_aresetn;\n   interface Reset rx_reset;\n   interface Reset s_axi_aresetn;\n   interface Reset tx_reset;\nendinterface\n\n(* always_ready, always_enabled *)\ninterface AxiethbufferAxi_str_rxd;\n    method Bit#(32)    tdata();\n    method Bit#(4)     tkeep();\n    method Bit#(1)     tlast();\n    method Action      tready(Bit#(1) v);\n    method Bit#(1)     tvalid();\nendinterface\n(* always_ready, always_enabled *)\ninterface AxiethbufferAxi_str_rxs;\n    method Bit#(32)    tdata();\n    method Bit#(4)     tkeep();\n    method Bit#(1)     tlast();\n    method Action      tready(Bit#(1) v);\n    method Bit#(1)     tvalid();\nendinterface\n(* always_ready, always_enabled *)\ninterface AxiethbufferAxi_str_txc;\n    method Action      tdata(Bit#(32) v);\n    method Action      tkeep(Bit#(4) v);\n    method Action      tlast(Bit#(1) v);\n    method Bit#(1)     tready();\n    method Action      tvalid(Bit#(1) v);\nendinterface\n(* always_ready, always_enabled *)\ninterface AxiethbufferAxi_str_txd;\n    method Action      tdata(Bit#(32) v);\n    method Action      tkeep(Bit#(4) v);\n    method Action      tlast(Bit#(1) v);\n    method Bit#(1)     tready();\n    method Action      tvalid(Bit#(1) v);\nendinterface\n(* always_ready, always_enabled *)\ninterface AxiethbufferEmac;\n    method Action      client_autoneg_int(Bit#(1) v);\n    method Action      reset_done_int(Bit#(1) v);\n    method Action      rx_dcm_locked_int(Bit#(1) v);\nendinterface\n(* always_ready, always_enabled *)\n(* always_ready, always_enabled *)\ninterface AxiethbufferMdc;\n    method Action      temac(Bit#(1) v);\n    method Bit#(1)     top();\nendinterface\n(* always_ready, always_enabled *)\ninterface AxiethbufferMdio;\n    method Bit#(1)     i_temac();\n    method Action      i_top(Bit#(1) v);\n    method Action      o_pcspma(Bit#(1) v);\n    method Action      o_temac(Bit#(1) v);\n    method Bit#(1)     o_top();\n    method Action      t_pcspma(Bit#(1) v);\n    method Action      t_temac(Bit#(1) v);\n    method Bit#(1)     t_top();\nendinterface\n(* always_ready, always_enabled *)\ninterface AxiethbufferPause;\n    method Bit#(1)     req();\n    method Bit#(16)     val();\nendinterface\n(* always_ready, always_enabled *)\ninterface AxiethbufferPcspma;\n    method Action      status_vector(Bit#(16) v);\nendinterface\n(* always_ready, always_enabled *)\ninterface AxiethbufferPhy;\n    method Reset     rst_n();\nendinterface\n(* always_ready, always_enabled *)\ninterface AxiethbufferRx;\n    method Action      axis_mac_tdata(Bit#(8) v);\n    method Action      axis_mac_tlast(Bit#(1) v);\n    method Action      axis_mac_tuser(Bit#(1) v);\n    method Action      axis_mac_tvalid(Bit#(1) v);\n    method Action      clk_enable_in(Bit#(1) v);\n    method Action      statistics_valid(Bit#(1) v);\n    method Action      statistics_vector(Bit#(28) v);\nendinterface\n(* always_ready, always_enabled *)\ninterface AxiethbufferS_axi;\n    method Action      araddr(Bit#(18) v);\n    method Bit#(1)     arready();\n    method Action      arvalid(Bit#(1) v);\n    method Action      awaddr(Bit#(18) v);\n    method Bit#(1)     awready();\n    method Action      awvalid(Bit#(1) v);\n    method Action      bready(Bit#(1) v);\n    method Bit#(2)     bresp();\n    method Bit#(1)     bvalid();\n    method Bit#(32)     rdata();\n    method Action      rready(Bit#(1) v);\n    method Bit#(2)     rresp();\n    method Bit#(1)     rvalid();\n    method Action      wdata(Bit#(32) v);\n    method Bit#(1)     wready();\n    method Action      wstrb(Bit#(4) v);\n    method Action      wvalid(Bit#(1) v);\nendinterface\n(* always_ready, always_enabled *)\ninterface AxiethbufferS_axi_2temac;\n    method Bit#(12)     araddr();\n    method Action      arready(Bit#(1) v);\n    method Bit#(1)     arvalid();\n    method Bit#(12)     awaddr();\n    method Action      awready(Bit#(1) v);\n    method Bit#(1)     awvalid();\n    method Bit#(1)     bready();\n    method Action      bresp(Bit#(2) v);\n    method Action      bvalid(Bit#(1) v);\n    method Action      rdata(Bit#(32) v);\n    method Bit#(1)     rready();\n    method Action      rresp(Bit#(2) v);\n    method Action      rvalid(Bit#(1) v);\n    method Bit#(32)     wdata();\n    method Action      wready(Bit#(1) v);\n    method Bit#(1)     wvalid();\nendinterface\n(* always_ready, always_enabled *)\ninterface AxiethbufferTx;\n    method Bit#(8)     axis_mac_tdata();\n    method Bit#(1)     axis_mac_tlast();\n    method Action      axis_mac_tready(Bit#(1) v);\n    method Bit#(1)     axis_mac_tuser();\n    method Bit#(1)     axis_mac_tvalid();\n    method Bit#(9)     ifg_delay();\nendinterface\n(* always_ready, always_enabled *)\ninterface AxiEthBuffer;\n    interface AxiStreamMaster#(32)     axi_str_rxd;\n    interface AxiStreamMaster#(32)     axi_str_rxs;\n    interface AxiStreamSlave#(32)     axi_str_txc;\n    interface AxiStreamSlave#(32)     axi_str_txd;\n    interface AxiethbufferEmac     emac;\n    method Bit#(1)     interrupt();\n    interface AxiethbufferMdc     mdc;\n    interface AxiethbufferMdio     mdio;\n    interface AxiethbufferPause     pause;\n    interface AxiethbufferPcspma     pcspma;\n    interface AxiethbufferPhy     phy;\n    method Bit#(1) reset2pcspma();\n    method Bit#(1) reset2temacn();\n    interface AxiethbufferRx     rx;\n    interface AxiethbufferS_axi_2temac     s_axi_2temac;\n    interface AxiethbufferS_axi     s_axi;\n    method Action      speed_is_10_100(Bit#(1) v);\n    interface AxiethbufferTx     tx;\nendinterface\nimport \"BVI\" eth_buf =\nmodule mkAxiEthBuffer#(AxiEthBufferClocks clks)(AxiEthBuffer);\n    default_clock clk();\n    default_reset rst();\n        input_clock axi_str_rxd_aclk(AXI_STR_RXD_ACLK) = clks.axi_str_rxd_aclk;\n        input_reset axi_str_rxd_aresetn(AXI_STR_RXD_ARESETN) = clks.axi_str_rxd_aresetn;\n        input_clock axi_str_rxs_aclk(AXI_STR_RXS_ACLK) = clks.axi_str_rxs_aclk;\n        input_reset axi_str_rxs_aresetn(AXI_STR_RXS_ARESETN) = clks.axi_str_rxs_aresetn;\n        input_clock axi_str_txc_aclk(AXI_STR_TXC_ACLK) = clks.axi_str_txc_aclk;\n        input_reset axi_str_txc_aresetn(AXI_STR_TXC_ARESETN) = clks.axi_str_txc_aresetn;\n        input_clock axi_str_txd_aclk(AXI_STR_TXD_ACLK) = clks.axi_str_txd_aclk;\n        input_reset axi_str_txd_aresetn(AXI_STR_TXD_ARESETN) = clks.axi_str_txd_aresetn;\n        input_clock gtx_clk(GTX_CLK) = clks.gtx_clk;\n        input_clock rx_mac_aclk(rx_mac_aclk) = clks.rx_mac_aclk;\n        input_reset rx_reset(rx_reset) clocked_by (rx_mac_aclk) = clks.rx_reset;\n        input_clock s_axi_aclk(S_AXI_ACLK) = clks.s_axi_aclk;\n        input_reset s_axi_aresetn(S_AXI_ARESETN) clocked_by (s_axi_aclk) = clks.s_axi_aresetn;\n        input_clock tx_mac_aclk(tx_mac_aclk) = clks.tx_mac_aclk;\n        input_reset tx_reset(tx_reset) clocked_by (tx_mac_aclk) = clks.tx_reset;\n    interface AxiStreamMaster     axi_str_rxd;\n        method AXI_STR_RXD_DATA tdata() clocked_by (axi_str_rxd_aclk) reset_by (axi_str_rxd_aresetn);\n        method AXI_STR_RXD_KEEP tkeep() clocked_by (axi_str_rxd_aclk) reset_by (axi_str_rxd_aresetn);\n        method AXI_STR_RXD_LAST tlast() clocked_by (axi_str_rxd_aclk) reset_by (axi_str_rxd_aresetn);\n        method tready(AXI_STR_RXD_READY) clocked_by (axi_str_rxd_aclk) reset_by (axi_str_rxd_aresetn) enable((*inhigh*) EN_AXI_STR_RXD_READY);\n        method AXI_STR_RXD_VALID tvalid() clocked_by (axi_str_rxd_aclk) reset_by (axi_str_rxd_aresetn);\n    endinterface\n    interface AxiStreamMaster     axi_str_rxs;\n        method AXI_STR_RXS_DATA tdata() clocked_by (axi_str_rxs_aclk) reset_by (axi_str_rxs_aresetn);\n        method AXI_STR_RXS_KEEP tkeep() clocked_by (axi_str_rxs_aclk) reset_by (axi_str_rxs_aresetn);\n        method AXI_STR_RXS_LAST tlast() clocked_by (axi_str_rxs_aclk) reset_by (axi_str_rxs_aresetn);\n        method tready(AXI_STR_RXS_READY) clocked_by (axi_str_rxs_aclk) reset_by (axi_str_rxs_aresetn) enable((*inhigh*) EN_AXI_STR_RXS_READY);\n        method AXI_STR_RXS_VALID tvalid() clocked_by (axi_str_rxs_aclk) reset_by (axi_str_rxs_aresetn);\n    endinterface\n    interface AxiStreamSlave     axi_str_txc;\n        method tdata(AXI_STR_TXC_TDATA) clocked_by (axi_str_txc_aclk) reset_by (axi_str_txc_aresetn) enable((*inhigh*) EN_AXI_STR_TXC_TDATA);\n        method tkeep(AXI_STR_TXC_TKEEP) clocked_by (axi_str_txc_aclk) reset_by (axi_str_txc_aresetn) enable((*inhigh*) EN_AXI_STR_TXC_TKEEP);\n        method tlast(AXI_STR_TXC_TLAST) clocked_by (axi_str_txc_aclk) reset_by (axi_str_txc_aresetn) enable((*inhigh*) EN_AXI_STR_TXC_TLAST);\n        method AXI_STR_TXC_TREADY tready() clocked_by (axi_str_txc_aclk) reset_by (axi_str_txc_aresetn);\n        method tvalid(AXI_STR_TXC_TVALID) clocked_by (axi_str_txc_aclk) reset_by (axi_str_txc_aresetn) enable((*inhigh*) EN_AXI_STR_TXC_TVALID);\n    endinterface\n    interface AxiStreamSlave     axi_str_txd;\n        method tdata(AXI_STR_TXD_TDATA) clocked_by (axi_str_txd_aclk) reset_by (axi_str_txd_aresetn) enable((*inhigh*) EN_AXI_STR_TXD_TDATA);\n        method tkeep(AXI_STR_TXD_TKEEP) clocked_by (axi_str_txd_aclk) reset_by (axi_str_txd_aresetn) enable((*inhigh*) EN_AXI_STR_TXD_TKEEP);\n        method tlast(AXI_STR_TXD_TLAST) clocked_by (axi_str_txd_aclk) reset_by (axi_str_txd_aresetn) enable((*inhigh*) EN_AXI_STR_TXD_TLAST);\n        method AXI_STR_TXD_TREADY tready() clocked_by (axi_str_txd_aclk) reset_by (axi_str_txd_aresetn);\n        method tvalid(AXI_STR_TXD_TVALID) clocked_by (axi_str_txd_aclk) reset_by (axi_str_txd_aresetn) enable((*inhigh*) EN_AXI_STR_TXD_TVALID);\n    endinterface\n    interface AxiethbufferEmac     emac;\n        method client_autoneg_int(EMAC_CLIENT_AUTONEG_INT) enable((*inhigh*) EN_EMAC_CLIENT_AUTONEG_INT);\n        method reset_done_int(EMAC_RESET_DONE_INT) enable((*inhigh*) EN_EMAC_RESET_DONE_INT);\n        method rx_dcm_locked_int(EMAC_RX_DCM_LOCKED_INT) enable((*inhigh*) EN_EMAC_RX_DCM_LOCKED_INT);\n    endinterface\n    method INTERRUPT interrupt();\n    interface AxiethbufferMdc     mdc;\n        method temac(mdc_temac) enable((*inhigh*) EN_mdc_temac);\n        method mdc_top top();\n    endinterface\n    interface AxiethbufferMdio     mdio;\n        method mdio_i_temac i_temac();\n        method i_top(mdio_i_top) enable((*inhigh*) EN_mdio_i_top);\n        method o_pcspma(mdio_o_pcspma) enable((*inhigh*) EN_mdio_o_pcspma);\n        method o_temac(mdio_o_temac) enable((*inhigh*) EN_mdio_o_temac);\n        method mdio_o_top o_top();\n        method t_pcspma(mdio_t_pcspma) enable((*inhigh*) EN_mdio_t_pcspma);\n        method t_temac(mdio_t_temac) enable((*inhigh*) EN_mdio_t_temac);\n        method mdio_t_top t_top();\n    endinterface\n    interface AxiethbufferPause     pause;\n        method pause_req req();\n        method pause_val val();\n    endinterface\n    interface AxiethbufferPcspma     pcspma;\n        method status_vector(PCSPMA_STATUS_VECTOR) enable((*inhigh*) EN_PCSPMA_STATUS_VECTOR);\n    endinterface\n    interface AxiethbufferPhy     phy;\n        output_reset rst_n(PHY_RST_N);\n    endinterface\n    method RESET2PCSPMA reset2pcspma();\n    method RESET2TEMACn reset2temacn();\n    interface AxiethbufferRx     rx;\n        method axis_mac_tdata(rx_axis_mac_tdata) clocked_by (rx_mac_aclk) reset_by (rx_reset) enable((*inhigh*) EN_rx_axis_mac_tdata);\n        method axis_mac_tlast(rx_axis_mac_tlast) clocked_by (rx_mac_aclk) reset_by (rx_reset) enable((*inhigh*) EN_rx_axis_mac_tlast);\n        method axis_mac_tuser(rx_axis_mac_tuser) clocked_by (rx_mac_aclk) reset_by (rx_reset) enable((*inhigh*) EN_rx_axis_mac_tuser);\n        method axis_mac_tvalid(rx_axis_mac_tvalid) clocked_by (rx_mac_aclk) reset_by (rx_reset) enable((*inhigh*) EN_rx_axis_mac_tvalid);\n        method clk_enable_in(RX_CLK_ENABLE_IN) clocked_by (rx_mac_aclk) reset_by (rx_reset) enable((*inhigh*) EN_rx_CLK_ENABLE_IN);\n        method statistics_valid(rx_statistics_valid) clocked_by (rx_mac_aclk) reset_by (rx_reset) enable((*inhigh*) EN_rx_statistics_valid);\n        method statistics_vector(rx_statistics_vector) clocked_by (rx_mac_aclk) reset_by (rx_reset) enable((*inhigh*) EN_rx_statistics_vector);\n    endinterface\n    interface AxiethbufferS_axi_2temac     s_axi_2temac;\n        method S_AXI_2TEMAC_ARADDR araddr();\n        method arready(S_AXI_2TEMAC_ARREADY) enable((*inhigh*) EN_S_AXI_2TEMAC_ARREADY);\n        method S_AXI_2TEMAC_ARVALID arvalid();\n        method S_AXI_2TEMAC_AWADDR awaddr();\n        method awready(S_AXI_2TEMAC_AWREADY) enable((*inhigh*) EN_S_AXI_2TEMAC_AWREADY);\n        method S_AXI_2TEMAC_AWVALID awvalid();\n        method S_AXI_2TEMAC_BREADY bready();\n        method bresp(S_AXI_2TEMAC_BRESP) enable((*inhigh*) EN_S_AXI_2TEMAC_BRESP);\n        method bvalid(S_AXI_2TEMAC_BVALID) enable((*inhigh*) EN_S_AXI_2TEMAC_BVALID);\n        method rdata(S_AXI_2TEMAC_RDATA) enable((*inhigh*) EN_S_AXI_2TEMAC_RDATA);\n        method S_AXI_2TEMAC_RREADY rready();\n        method rresp(S_AXI_2TEMAC_RRESP) enable((*inhigh*) EN_S_AXI_2TEMAC_RRESP);\n        method rvalid(S_AXI_2TEMAC_RVALID) enable((*inhigh*) EN_S_AXI_2TEMAC_RVALID);\n        method S_AXI_2TEMAC_WDATA wdata();\n        method wready(S_AXI_2TEMAC_WREADY) enable((*inhigh*) EN_S_AXI_2TEMAC_WREADY);\n        method S_AXI_2TEMAC_WVALID wvalid();\n    endinterface\n    interface AxiethbufferS_axi     s_axi;\n        method araddr(S_AXI_ARADDR) clocked_by (s_axi_aclk) reset_by (s_axi_aresetn) enable((*inhigh*) EN_S_AXI_ARADDR);\n        method S_AXI_ARREADY arready() clocked_by (s_axi_aclk) reset_by (s_axi_aresetn);\n        method arvalid(S_AXI_ARVALID) clocked_by (s_axi_aclk) reset_by (s_axi_aresetn) enable((*inhigh*) EN_S_AXI_ARVALID);\n        method awaddr(S_AXI_AWADDR) clocked_by (s_axi_aclk) reset_by (s_axi_aresetn) enable((*inhigh*) EN_S_AXI_AWADDR);\n        method S_AXI_AWREADY awready() clocked_by (s_axi_aclk) reset_by (s_axi_aresetn);\n        method awvalid(S_AXI_AWVALID) clocked_by (s_axi_aclk) reset_by (s_axi_aresetn) enable((*inhigh*) EN_S_AXI_AWVALID);\n        method bready(S_AXI_BREADY) clocked_by (s_axi_aclk) reset_by (s_axi_aresetn) enable((*inhigh*) EN_S_AXI_BREADY);\n        method S_AXI_BRESP bresp() clocked_by (s_axi_aclk) reset_by (s_axi_aresetn);\n        method S_AXI_BVALID bvalid() clocked_by (s_axi_aclk) reset_by (s_axi_aresetn);\n        method S_AXI_RDATA rdata() clocked_by (s_axi_aclk) reset_by (s_axi_aresetn);\n        method rready(S_AXI_RREADY) clocked_by (s_axi_aclk) reset_by (s_axi_aresetn) enable((*inhigh*) EN_S_AXI_RREADY);\n        method S_AXI_RRESP rresp() clocked_by (s_axi_aclk) reset_by (s_axi_aresetn);\n        method S_AXI_RVALID rvalid() clocked_by (s_axi_aclk) reset_by (s_axi_aresetn);\n        method wdata(S_AXI_WDATA) clocked_by (s_axi_aclk) reset_by (s_axi_aresetn) enable((*inhigh*) EN_S_AXI_WDATA);\n        method S_AXI_WREADY wready() clocked_by (s_axi_aclk) reset_by (s_axi_aresetn);\n        method wstrb(S_AXI_WSTRB) clocked_by (s_axi_aclk) reset_by (s_axi_aresetn) enable((*inhigh*) EN_S_AXI_WSTRB);\n        method wvalid(S_AXI_WVALID) clocked_by (s_axi_aclk) reset_by (s_axi_aresetn) enable((*inhigh*) EN_S_AXI_WVALID);\n    endinterface\n    method speed_is_10_100(speed_is_10_100) enable((*inhigh*) EN_speed_is_10_100);\n    interface AxiethbufferTx     tx;\n        method tx_axis_mac_tdata axis_mac_tdata() clocked_by (tx_mac_aclk) reset_by (tx_reset);\n        method tx_axis_mac_tlast axis_mac_tlast() clocked_by (tx_mac_aclk) reset_by (tx_reset);\n        method axis_mac_tready(tx_axis_mac_tready) clocked_by (tx_mac_aclk) reset_by (tx_reset) enable((*inhigh*) EN_tx_axis_mac_tready);\n        method tx_axis_mac_tuser axis_mac_tuser() clocked_by (tx_mac_aclk) reset_by (tx_reset);\n        method tx_axis_mac_tvalid axis_mac_tvalid() clocked_by (tx_mac_aclk) reset_by (tx_reset);\n        method tx_ifg_delay ifg_delay() clocked_by (tx_mac_aclk) reset_by (tx_reset);\n    endinterface\n    schedule (axi_str_rxd.tdata, axi_str_rxd.tkeep, axi_str_rxd.tlast, axi_str_rxd.tready, axi_str_rxd.tvalid, axi_str_rxs.tdata, axi_str_rxs.tkeep, axi_str_rxs.tlast, axi_str_rxs.tready, axi_str_rxs.tvalid, axi_str_txc.tdata, axi_str_txc.tkeep, axi_str_txc.tlast, axi_str_txc.tready, axi_str_txc.tvalid, axi_str_txd.tdata, axi_str_txd.tkeep, axi_str_txd.tlast, axi_str_txd.tready, axi_str_txd.tvalid, emac.client_autoneg_int, emac.reset_done_int, emac.rx_dcm_locked_int, interrupt, mdc.temac, mdc.top, mdio.i_temac, mdio.i_top, mdio.o_pcspma, mdio.o_temac, mdio.o_top, mdio.t_pcspma, mdio.t_temac, mdio.t_top, pause.req, pause.val, pcspma.status_vector, rx.axis_mac_tdata, rx.axis_mac_tlast, rx.axis_mac_tuser, rx.axis_mac_tvalid, rx.clk_enable_in, rx.statistics_valid, rx.statistics_vector, s_axi_2temac.araddr, s_axi_2temac.arready, s_axi_2temac.arvalid, s_axi_2temac.awaddr, s_axi_2temac.awready, s_axi_2temac.awvalid, s_axi_2temac.bready, s_axi_2temac.bresp, s_axi_2temac.bvalid, s_axi_2temac.rdata, s_axi_2temac.rready, s_axi_2temac.rresp, s_axi_2temac.rvalid, s_axi_2temac.wdata, s_axi_2temac.wready, s_axi_2temac.wvalid, s_axi.araddr, s_axi.arready, s_axi.arvalid, s_axi.awaddr, s_axi.awready, s_axi.awvalid, s_axi.bready, s_axi.bresp, s_axi.bvalid, s_axi.rdata, s_axi.rready, s_axi.rresp, s_axi.rvalid, s_axi.wdata, s_axi.wready, s_axi.wstrb, s_axi.wvalid, speed_is_10_100, tx.axis_mac_tdata, tx.axis_mac_tlast, tx.axis_mac_tready, tx.axis_mac_tuser, tx.axis_mac_tvalid, tx.ifg_delay, reset2pcspma, reset2temacn) CF (axi_str_rxd.tdata, axi_str_rxd.tkeep, axi_str_rxd.tlast, axi_str_rxd.tready, axi_str_rxd.tvalid, axi_str_rxs.tdata, axi_str_rxs.tkeep, axi_str_rxs.tlast, axi_str_rxs.tready, axi_str_rxs.tvalid, axi_str_txc.tdata, axi_str_txc.tkeep, axi_str_txc.tlast, axi_str_txc.tready, axi_str_txc.tvalid, axi_str_txd.tdata, axi_str_txd.tkeep, axi_str_txd.tlast, axi_str_txd.tready, axi_str_txd.tvalid, emac.client_autoneg_int, emac.reset_done_int, emac.rx_dcm_locked_int, interrupt, mdc.temac, mdc.top, mdio.i_temac, mdio.i_top, mdio.o_pcspma, mdio.o_temac, mdio.o_top, mdio.t_pcspma, mdio.t_temac, mdio.t_top, pause.req, pause.val, pcspma.status_vector, rx.axis_mac_tdata, rx.axis_mac_tlast, rx.axis_mac_tuser, rx.axis_mac_tvalid, rx.clk_enable_in, rx.statistics_valid, rx.statistics_vector, s_axi_2temac.araddr, s_axi_2temac.arready, s_axi_2temac.arvalid, s_axi_2temac.awaddr, s_axi_2temac.awready, s_axi_2temac.awvalid, s_axi_2temac.bready, s_axi_2temac.bresp, s_axi_2temac.bvalid, s_axi_2temac.rdata, s_axi_2temac.rready, s_axi_2temac.rresp, s_axi_2temac.rvalid, s_axi_2temac.wdata, s_axi_2temac.wready, s_axi_2temac.wvalid, s_axi.araddr, s_axi.arready, s_axi.arvalid, s_axi.awaddr, s_axi.awready, s_axi.awvalid, s_axi.bready, s_axi.bresp, s_axi.bvalid, s_axi.rdata, s_axi.rready, s_axi.rresp, s_axi.rvalid, s_axi.wdata, s_axi.wready, s_axi.wstrb, s_axi.wvalid, speed_is_10_100, tx.axis_mac_tdata, tx.axis_mac_tlast, tx.axis_mac_tready, tx.axis_mac_tuser, tx.axis_mac_tvalid, tx.ifg_delay, reset2pcspma, reset2temacn);\nendmodule\n\ninstance ToAxi4SlaveBits#(Axi4SlaveLiteBits#(12,32), AxiethbufferS_axi);\n   function Axi4SlaveLiteBits#(12,32) toAxi4SlaveBits(AxiethbufferS_axi s);\n      return (interface Axi4SlaveLiteBits#(12,32);\n\t method araddr = compose(s.araddr, extend);\n\t method arready = s.arready;\n\t method arvalid = s.arvalid;\n\t method awaddr = compose(s.awaddr, extend);\n\t method awready = s.awready;\n\t method awvalid = s.awvalid;\n\t method bready = s.bready;\n\t method bresp = s.bresp;\n\t method bvalid = s.bvalid;\n\t method rdata = s.rdata;\n\t method rready = s.rready;\n\t method rresp = s.rresp;\n\t method rvalid = s.rvalid;\n\t method wdata = s.wdata;\n\t method wready = s.wready;\n\t method Action      wvalid(Bit#(1) v);\n\t    s.wvalid(v);\n\t    s.wstrb(pack(replicate(v)));\n\t endmethod\n\t endinterface);\n   endfunction\nendinstance\n"
  },
  {
    "path": "tests/spikehw/AxiEthSubsystem.bsv",
    "content": "// Copyright (c) 2016 Connectal Project\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\n`include \"ConnectalProjectConfig.bsv\"\nimport FIFOF::*;\nimport BRAMFIFO::*;\nimport GetPut::*;\nimport Clocks::*;\nimport Connectable::*;\nimport StmtFSM::*;\n`define PROBE_ME\n`ifdef PROBE_ME\nimport Probe::*;\n`else\ninterface Probe#(type a);\n   method Action _write(a v);\nendinterface   \nmodule mkProbe(Probe#(a));\n   method Action _write(a v);\n   endmethod\nendmodule\n`endif\nimport Vector::*;\n\nimport AxiBits::*;\nimport AxiStream::*;\nimport AxiEthBufferBvi::*;\nimport TriModeMacBvi::*;\nimport GigEthPcsPmaBvi::*;\nimport AxiEth1000BaseX::*;\nimport SyncAxisFifo32x1024::*;\nimport AxiDmaBvi::*;\n\ninterface AxiEthSubsystem;\n   interface AxidmabviMm2s     mm2s_dma;\n   interface AxidmabviS2mm     s2mm_dma;\n   interface AxidmabviM_axi_mm2s     m_axi_mm2s;\n   interface AxidmabviM_axi_s2mm     m_axi_s2mm;\n   interface AxidmabviM_axi_sg       m_axi_sg;\n\n   interface Axi4SlaveLiteBits#(10,32) s_axi_dma;\n\n   interface TrimodemacS_axi s_axi_mac;\n   interface TrimodemacMac mac;\n   interface AxiethbviSfp sfp;\n   interface AxiethbviMgt mgt;\n   interface GigethpcspmabviSignal signal;\n   interface GigethpcspmabviMmcm mmcm;\nendinterface\n\ninstance Connectable#(TrimodemacGmii,GigethpcspmabviGmii);\n   module mkConnection#(TrimodemacGmii mac, GigethpcspmabviGmii phy)(Empty);\n      rule rx;\n\t mac.rx_dv(phy.rx_dv());\n\t mac.rx_er(phy.rx_er());\n\t mac.rxd(phy.rxd());\n      endrule\n      rule tx;\n\t phy.tx_en(mac.tx_en());\n\t phy.tx_er(mac.tx_er());\n\t phy.txd(mac.txd());\n      endrule\n   endmodule\nendinstance\n\ninstance Connectable#(TrimodemacMdio,GigethpcspmabviMdio);\n   module mkConnection#(TrimodemacMdio macMdio, GigethpcspmabviMdio phyMdio)(Empty);\n      rule rl_mdio;\n\t macMdio.i(phyMdio.o());\n\t phyMdio.i(macMdio.o());\n      endrule\n   endmodule\nendinstance\n\ninstance Connectable#(TriModeMac,GigEthPcsPma);\n   module mkConnection#(TriModeMac mac, GigEthPcsPma phy)(Empty);\n      let mdcCnx  <- mkConnection(phy.mdc,  mac.mdc); // should be a clock, but PHY is providing a clock to MAC and this would make a cycle\n      let mdioCnx <- mkConnection(mac.mdio, phy.mdio);\n      let gmiiCnx <- mkConnection(mac.gmii, phy.gmii);\n   endmodule\nendinstance\n\nmodule mkStreamControlConnection#(AxiStreamMaster#(32) from, AxiStreamMaster#(32) cntrl,\n\t\t\t\t  TrimodemacTx_axis_mac to,\n\t\t\t\t  Clock fromClock, Reset fromReset, Clock toClock, Reset toReset)(Empty);\n   let sfifo <- mkSyncAxisFifo32x1024(fromClock, fromReset, toClock, toReset);\n\n   Reg#(Bit#(2)) phaseReg <- mkReg(0, clocked_by toClock, reset_by toReset);\n\n   Probe#(Bit#(32)) fromControlDataProbe <- mkProbe(clocked_by fromClock, reset_by fromReset);\n   Probe#(Bit#(1)) fromControlValidProbe <- mkProbe(clocked_by fromClock, reset_by fromReset);\n\n   Probe#(Bit#(32)) fromDataProbe <- mkProbe(clocked_by toClock, reset_by toReset);\n   Probe#(Bit#(4)) fromKeepProbe <- mkProbe(clocked_by toClock, reset_by toReset);\n   Probe#(Bit#(1)) fromLastProbe <- mkProbe(clocked_by toClock, reset_by toReset);\n\n   Probe#(Bit#(8)) toDataProbe <- mkProbe(clocked_by toClock, reset_by toReset);\n   Probe#(Bit#(4)) toKeepProbe <- mkProbe(clocked_by toClock, reset_by toReset);\n   Probe#(Bit#(1)) toLastProbe <- mkProbe(clocked_by toClock, reset_by toReset);\n   Probe#(Bit#(1)) toValidProbe <- mkProbe(clocked_by toClock, reset_by toReset);\n\n   Probe#(Bit#(2)) phaseProbe    <- mkProbe(clocked_by toClock, reset_by toReset);\n   Probe#(Bit#(4)) moreDataProbe <- mkProbe(clocked_by toClock, reset_by toReset);\n\n   rule rl_control if (cntrl.tvalid() == 1);\n      fromControlDataProbe <= cntrl.tdata();\n      fromControlValidProbe <= cntrl.tvalid();\n   endrule\n\n   let fromCnx <- mkConnection(from, sfifo.s_axis);\n\n   Wire#(Bool) doDeq <- mkDWire(False, clocked_by toClock, reset_by toReset);\n   rule rl_expand if (to.tready() == 1 && sfifo.m_axis.tvalid() == 1);\n\n      fromDataProbe <= sfifo.m_axis.tdata();\n      fromKeepProbe <= sfifo.m_axis.tkeep();\n      fromLastProbe <= sfifo.m_axis.tlast();\n\n      Vector#(4,Bit#(8)) data = unpack(sfifo.m_axis.tdata());\n      let keep = sfifo.m_axis.tkeep();\n      let last = sfifo.m_axis.tlast();\n      //match { .data, .keep, .last } = sfifo.first();\n      let phase = phaseReg;\n      Bool lastPhase = (phaseReg == 3);\n      Bit#(4) moreData = keep[3:phase+1];\n      if (!lastPhase)\n\t lastPhase = (moreData == 0);\n\n      to.tdata(data[phase]);\n      //to.tkeep(keep[phase]);\n      to.tlast(pack(last == 1 && lastPhase));\n\n      toDataProbe <= data[phase];\n      toLastProbe <= pack(last == 1 && lastPhase);\n\n      if (lastPhase) begin\n\t //sfifo.deq();\n\t doDeq <= True;\n\t phase = 0;\n      end\n      else begin\n\t phase = phase + 1;\n      end\n      phaseReg <= phase;\n\n      phaseProbe <= phase;\n      moreDataProbe <= moreData;\n   endrule\n\n   rule rl_to_handshake;\n      to.tvalid(sfifo.m_axis.tvalid());\n      toValidProbe <= sfifo.m_axis.tvalid();\n      sfifo.m_axis.tready(pack(doDeq));\n   endrule\nendmodule\n\nmodule mkStreamStatusConnection#(TrimodemacRx_axis_mac from,\n\t\t\t\t AxiStreamSlave#(32) to, AxiStreamSlave#(32) status,\n\t\t\t\t Clock fromClock, Reset fromReset, Clock toClock, Reset toReset)(Empty);\n\n   Reg#(Bit#(16)) byteCountReg <- mkReg(0, clocked_by fromClock, reset_by fromReset);\n   Reg#(Bit#(2)) phaseReg <- mkReg(0, clocked_by fromClock, reset_by fromReset);\n   Vector#(4,Reg#(Bit#(8))) dataReg <- replicateM(mkReg(0), clocked_by fromClock, reset_by fromReset);\n   Reg#(Bit#(4)) keepReg <- mkReg(0, clocked_by fromClock, reset_by fromReset);\n   let sfifo <- mkSyncAxisFifo32x1024(fromClock, fromReset, toClock, toReset);\n   let stsfifo <- mkSyncAxisFifo32x1024(fromClock, fromReset, toClock, toReset);\n\n   Wire#(Bool) doEnq <- mkDWire(False, clocked_by fromClock, reset_by fromReset);\n\n   Probe#(Bool) probeOverrun <- mkProbe(clocked_by fromClock, reset_by fromReset);\n   Probe#(Bit#(1)) fromValidProbe <- mkProbe(clocked_by fromClock, reset_by fromReset);\n   Probe#(Bit#(8)) fromDataProbe <- mkProbe(clocked_by fromClock, reset_by fromReset);\n   Probe#(Bit#(1)) fromLastProbe <- mkProbe(clocked_by fromClock, reset_by fromReset);\n   Probe#(Bit#(32)) toDataProbe <- mkProbe(clocked_by fromClock, reset_by fromReset);\n   Probe#(Bit#(4)) toKeepProbe <- mkProbe(clocked_by fromClock, reset_by fromReset);\n   Probe#(Bit#(2)) phaseProbe    <- mkProbe(clocked_by fromClock, reset_by fromReset);\n   Probe#(Bit#(1)) toReadyProbe <- mkProbe(clocked_by toClock, reset_by toReset);\n   Probe#(Bit#(16)) byteCountProbe    <- mkProbe(clocked_by fromClock, reset_by fromReset);\n\n   FIFOF#(Bit#(16)) lengthFifo <- mkFIFOF(clocked_by fromClock, reset_by fromReset);\n   Wire#(Bit#(32)) statusDataWire <- mkDWire(0, clocked_by fromClock, reset_by fromReset);\n   Wire#(Bit#(1))  statusLastWire <- mkDWire(0, clocked_by fromClock, reset_by fromReset);\n   Wire#(Bit#(1))  statusValidWire <- mkDWire(0, clocked_by fromClock, reset_by fromReset);\n\n   Probe#(Bit#(32)) statusDataProbe <- mkProbe(clocked_by fromClock, reset_by fromReset);\n   Probe#(Bit#(1))  statusLastProbe <- mkProbe(clocked_by fromClock, reset_by fromReset);\n   Probe#(Bit#(1))  statusValidProbe <- mkProbe(clocked_by fromClock, reset_by fromReset);\n   let stsFsm <- mkAutoFSM((seq\n\t\t\t    while (True) seq\n\t\t\t      await (lengthFifo.notEmpty && stsfifo.s_axis.tready==1);\n\t\t\t      action // status word\n\t\t\t\t statusDataWire <= 32'h80000000 | extend(lengthFifo.first);\n\t\t\t\t statusLastWire <= 0;\n\t\t\t\t statusValidWire <= 1;\n\t\t\t      endaction\n\t\t\t      await (stsfifo.s_axis.tready==1);\n\t\t\t      action // app0\n\t\t\t\t statusDataWire <= 0;\n\t\t\t\t statusLastWire <= 0;\n\t\t\t\t statusValidWire <= 1;\n\t\t\t      endaction\n\t\t\t      await (stsfifo.s_axis.tready==1);\n\t\t\t      action // app1\n\t\t\t\t statusDataWire <= 1;\n\t\t\t\t statusLastWire <= 0;\n\t\t\t\t statusValidWire <= 1;\n\t\t\t      endaction\n\t\t\t      await (stsfifo.s_axis.tready==1);\n\t\t\t      action // app2\n\t\t\t\t statusDataWire <= 2;\n\t\t\t\t statusLastWire <= 0;\n\t\t\t\t statusValidWire <= 1;\n\t\t\t      endaction\n\t\t\t      await (stsfifo.s_axis.tready==1);\n\t\t\t      action // app3\n\t\t\t\t statusDataWire <= 3;\n\t\t\t\t statusLastWire <= 0;\n\t\t\t\t statusValidWire <= 1;\n\t\t\t      endaction\n\t\t\t      await (stsfifo.s_axis.tready==1);\n\t\t\t      action // app4\n\t\t\t\t statusDataWire <= extend(lengthFifo.first);\n\t\t\t\t statusLastWire <= 0;\n\t\t\t\t statusValidWire <= 1;\n\t\t\t\t lengthFifo.deq();\n\t\t\t      endaction\n\t\t\t    endseq // while\n\t\t\t   endseq),\n\t\t\t   clocked_by fromClock, reset_by fromReset);\n   rule rl_status_handshake;\n\n      if (statusValidWire == 1) begin\n\t statusValidProbe <= 1;\n\t statusDataProbe <= statusDataWire;\n\t statusLastProbe <= statusLastWire;\n      end\n\n      stsfifo.s_axis.tvalid(statusValidWire);\n      stsfifo.s_axis.tdata(statusDataWire);\n      stsfifo.s_axis.tlast(statusLastWire);\n      stsfifo.s_axis.tkeep(maxBound);\n   endrule\n\n   rule rl_overrun if (from.tvalid() == 1 && sfifo.s_axis.tready() == 0);\n      probeOverrun <= True;\n   endrule\n\n   rule rl_from_valid;\n      fromValidProbe <= from.tvalid();\n   endrule\n\n   rule rl_combine if (unpack(from.tvalid()));\n      phaseProbe <= phaseReg;\n\n      Bool last = unpack(from.tlast());\n      let byteCount = byteCountReg + 1;\n      let phase = phaseReg;\n      Vector#(4,Bit#(8)) data = readVReg(dataReg);\n      let keep = keepReg;\n      keep[phase] = 1; //from.tkeep();\n      data[phase] = from.tdata();\n\n      sfifo.s_axis.tdata(pack(data));\n      sfifo.s_axis.tkeep(keep);\n      sfifo.s_axis.tlast(pack(last));\n\n      byteCountProbe <= byteCount;\n\n      if (last || (phaseReg == 3)) begin\n\n\t toKeepProbe <= keep;\n\t toDataProbe <= pack(data);\n\t fromLastProbe <= pack(last); //from.tlast();\n\n\t phase = 0;\n\t data  = unpack(0);\n\t keep  = 0;\n\t doEnq <= True;\n\t //sfifo.enq(tuple3(pack(data), keep, pack(last)));\n      end\n      else begin\n\t phase = phase + 1;\n      end\n\n      if (last) begin\n\t byteCount = 0;\n\t lengthFifo.enq(byteCount);\n      end\n\n      byteCountReg <= byteCount;\n      phaseReg <= phase;\n      writeVReg(dataReg, data);\n      keepReg  <= keep;\n\n      fromDataProbe <= from.tdata();\n\n   endrule\n\n   rule rl_from_handshake;\n      //from.tready(pack(sfifo.s_axis.tready())); // scary -- no backpressure\n      sfifo.s_axis.tvalid(pack(doEnq));\n   endrule\n\n   rule rl_to_ready_probe;\n      toReadyProbe <= to.tready();\n   endrule\t \n\n   let toCnx <- mkConnection(sfifo.m_axis, to);\n   let stsCnx <- mkConnection(stsfifo.m_axis, status);\nendmodule\n\n(* synthesize *)\nmodule mkAxiEthBvi#(Clock axis_clk, Clock ref_clk)(AxiEthSubsystem);\n   let clock <- exposeCurrentClock;\n   let reset <- exposeCurrentReset;\n\n  // connect_bd_net -net eth_buf_RESET2PCSPMA [get_bd_pins eth_buf/RESET2PCSPMA] [get_bd_pins pcs_pma/reset] //FIXME\n//   let resetToPcsPma <- mkReset(10, True, ref_clk);\n\n   let pcs <- mkGigEthPcsPmaBvi(ref_clk, reset);\n  // connect_bd_net -net pcs_pma_userclk2_out [get_bd_ports userclk2_out] [get_bd_pins eth_buf/GTX_CLK] [get_bd_pins eth_mac/gtx_clk] [get_bd_pins pcs_pma/userclk2_out]\n   Clock gtx_clk = pcs.userclk2.out;\n\n   let trimodemac <- mkTriModeMacBvi(gtx_clk, axis_clk, reset, reset, reset, reset);\n\n  // connect_bd_intf_net -intf_net eth_mac_gmii [get_bd_intf_pins eth_mac/gmii] [get_bd_intf_pins pcs_pma/gmii_pcs_pma]\n   let gmiiConnection <- mkConnection(trimodemac.gmii, pcs.gmii);\n\n  // connect_bd_net -net eth_mac_mdc [get_bd_pins eth_mac/mdc] [get_bd_pins pcs_pma/mdc]\n   rule rl_misc;\n      pcs.mdc(trimodemac.mdc()); // actually a clock\n   endrule\n  // connect_bd_net -net eth_mac_mdio_o [get_bd_pins eth_mac/mdio_o] [get_bd_pins pcs_pma/mdio_i]\n  // connect_bd_net -net pcs_pma_mdio_o [get_bd_pins eth_mac/mdio_i] [get_bd_pins pcs_pma/mdio_o]\n  let mdioConnection <- mkConnection(trimodemac.mdio, pcs.mdio);\n\n  // connect_bd_net -net reset_inv_Res [get_bd_pins eth_mac/glbl_rstn] [get_bd_pins eth_mac/rx_axi_rstn] [get_bd_pins eth_mac/tx_axi_rstn] [get_bd_pins reset_inv/Res]\n\n\n   // ports:\n   // connect_bd_intf_net -intf_net eth_mac_rx_statistics [get_bd_intf_ports rx_statistics] [get_bd_intf_pins eth_mac/rx_statistics]\n   // connect_bd_intf_net -intf_net eth_mac_tx_statistics [get_bd_intf_ports tx_statistics] [get_bd_intf_pins eth_mac/tx_statistics]\n   // connect_bd_intf_net -intf_net mgt_clk_1 [get_bd_intf_ports mgt_clk] [get_bd_intf_pins pcs_pma/gtrefclk_in]\n   // connect_bd_intf_net -intf_net pcs_pma_sfp [get_bd_intf_ports sfp] [get_bd_intf_pins pcs_pma/sfp]\n   // connect_bd_intf_net -intf_net s_axi_1 [get_bd_intf_ports s_axi] [get_bd_intf_pins eth_mac/s_axi]\n   // connect_bd_intf_net -intf_net s_axis_pause_1 [get_bd_intf_ports s_axis_pause] [get_bd_intf_pins eth_mac/s_axis_pause]\n   // connect_bd_intf_net -intf_net s_axis_tx_1 [get_bd_intf_ports s_axis_tx] [get_bd_intf_pins eth_mac/s_axis_tx]\n   // connect_bd_net -net eth_mac_mac_irq [get_bd_ports mac_irq] [get_bd_pins eth_mac/mac_irq]\n   // connect_bd_net -net eth_mac_rx_axis_filter_tuser [get_bd_ports rx_axis_filter_tuser] [get_bd_pins eth_mac/rx_axis_filter_tuser]\n   // connect_bd_net -net eth_mac_rx_mac_aclk [get_bd_ports rx_mac_aclk] [get_bd_pins eth_mac/rx_mac_aclk]\n   // connect_bd_net -net eth_mac_rx_reset [get_bd_ports rx_reset] [get_bd_pins eth_mac/rx_reset]\n   // connect_bd_net -net eth_mac_tx_mac_aclk [get_bd_ports tx_mac_aclk] [get_bd_pins eth_mac/tx_mac_aclk]\n   // connect_bd_net -net eth_mac_tx_reset [get_bd_ports tx_reset] [get_bd_pins eth_mac/tx_reset]\n   // connect_bd_net -net glbl_rst_1 [get_bd_ports glbl_rst] [get_bd_pins pcs_pma/reset] [get_bd_pins reset_inv/Op1]\n   // connect_bd_net -net pcs_pma_gt0_qplloutclk_out [get_bd_ports gt0_qplloutclk_out] [get_bd_pins pcs_pma/gt0_qplloutclk_out]\n   // connect_bd_net -net pcs_pma_gt0_qplloutrefclk_out [get_bd_ports gt0_qplloutrefclk_out] [get_bd_pins pcs_pma/gt0_qplloutrefclk_out]\n   // connect_bd_net -net pcs_pma_gtrefclk_bufg_out [get_bd_ports gtref_clk_buf_out] [get_bd_pins pcs_pma/gtrefclk_bufg_out]\n   // connect_bd_net -net pcs_pma_gtrefclk_out [get_bd_ports gtref_clk_out] [get_bd_pins pcs_pma/gtrefclk_out]\n   // connect_bd_net -net pcs_pma_mmcm_locked_out [get_bd_ports mmcm_locked_out] [get_bd_pins pcs_pma/mmcm_locked_out]\n   // connect_bd_net -net pcs_pma_pma_reset_out [get_bd_ports pma_reset_out] [get_bd_pins pcs_pma/pma_reset_out]\n   // connect_bd_net -net pcs_pma_rxuserclk2_out [get_bd_ports rxuserclk2_out] [get_bd_pins pcs_pma/rxuserclk2_out]\n   // connect_bd_net -net pcs_pma_rxuserclk_out [get_bd_ports rxuserclk_out] [get_bd_pins pcs_pma/rxuserclk_out]\n   // connect_bd_net -net pcs_pma_status_vector [get_bd_ports status_vector] [get_bd_pins pcs_pma/status_vector]\n   // connect_bd_net -net pcs_pma_userclk2_out [get_bd_ports userclk2_out] [get_bd_pins eth_mac/gtx_clk] [get_bd_pins pcs_pma/userclk2_out]\n   // connect_bd_net -net pcs_pma_userclk_out [get_bd_ports userclk_out] [get_bd_pins pcs_pma/userclk_out]\n   // connect_bd_net -net ref_clk_1 [get_bd_ports ref_clk] [get_bd_pins pcs_pma/independent_clock_bufg]\n   // connect_bd_intf_net -intf_net eth_mac_m_axis_rx [get_bd_intf_ports m_axis_rx] [get_bd_intf_pins eth_mac/m_axis_rx]\n   // connect_bd_net -net s_axi_lite_clk_1 [get_bd_ports s_axi_lite_clk] [get_bd_pins eth_mac/s_axi_aclk]\n   // connect_bd_net -net s_axi_lite_resetn_1 [get_bd_ports s_axi_lite_resetn] [get_bd_pins eth_mac/s_axi_resetn]\n   // connect_bd_net -net signal_detect_1 [get_bd_ports signal_detect] [get_bd_pins pcs_pma/signal_detect]\n   // connect_bd_net -net tx_ifg_delay_1 [get_bd_ports tx_ifg_delay] [get_bd_pins eth_mac/tx_ifg_delay]\n\n   let axiDmaBvi <- mkAxiDmaBvi(clock,clock,clock,clock,reset);\n\n   // packet data and status from the ethernet\n   let rxResetInverted <- mkResetInverter(trimodemac.rx.reset, clocked_by trimodemac.rx.mac_aclk);\n   let rxCnx <- mkStreamStatusConnection(trimodemac.rx_axis_mac, axiDmaBvi.s_axis_s2mm, axiDmaBvi.s_axis_s2mm_sts,\n\t\t\t\t\t trimodemac.rx.mac_aclk, rxResetInverted, clock, reset);\n   //mkConnection(axiEthBvi.m_axis_rxs, axiDmaBvi.s_axis_s2mm_sts);\n\n   // packet data and control to the ethernet\n   let txResetInverted <- mkResetInverter(trimodemac.tx.reset, clocked_by trimodemac.tx.mac_aclk);\n   let txCnx <- mkStreamControlConnection(axiDmaBvi.m_axis_mm2s, axiDmaBvi.m_axis_mm2s_cntrl,\n\t\t\t\t\t  trimodemac.tx_axis_mac,\n\t\t\t\t\t  clock, reset, trimodemac.tx.mac_aclk, txResetInverted);\n   //mkConnection(axiDmaBvi.m_axis_mm2s_cntrl, axiEthBvi.s_axis_txc);\n   interface   mm2s_dma = axiDmaBvi.mm2s;\n   interface   s2mm_dma = axiDmaBvi.s2mm;\n   interface m_axi_mm2s = axiDmaBvi.m_axi_mm2s;\n   interface m_axi_s2mm = axiDmaBvi.m_axi_s2mm;\n   interface m_axi_sg   = axiDmaBvi.m_axi_sg;\n\n   interface  s_axi_dma = axiDmaBvi.s_axi_lite;\n\n   interface  s_axi_mac = trimodemac.s_axi;\n   interface        mac = trimodemac.mac;\n\n   interface signal = pcs.signal;\n   interface mmcm = pcs.mmcm;\n   interface AxiethbviMgt mgt;\n      method clk_clk_p = pcs.gtrefclk.p;\n      method clk_clk_n = pcs.gtrefclk.n;\n   endinterface\n   interface AxiethbviSfp sfp;\n      method txp = pcs.txp;\n      method txn = pcs.txn;\n      method rxp = pcs.rxp;\n      method rxn = pcs.rxn;\n   endinterface\nendmodule\n"
  },
  {
    "path": "tests/spikehw/AxiIic.bsv",
    "content": "\n/*\n   /home/jamey/connectal.clean/generated/scripts/importbvi.py\n   -P\n   AxiIic\n   -I\n   AxiIic\n   -c\n   s_axi_aclk\n   -r\n   s_axi_aresetn\n   -n\n   iic2intc_irpt\n   -o\n   AxiIic.bsv\n   cores/vc709/axi_iic_0/axi_iic_0_stub.v\n*/\n\nimport Clocks::*;\nimport DefaultValue::*;\nimport XilinxCells::*;\nimport GetPut::*;\nimport AxiBits::*;\nimport Vector::*;\n\n(* always_ready, always_enabled *)\ninterface AxiiicS_axi;\n    method Action      araddr(Bit#(9) v);\n    method Bit#(1)     arready();\n    method Action      arvalid(Bit#(1) v);\n    method Action      awaddr(Bit#(9) v);\n    method Bit#(1)     awready();\n    method Action      awvalid(Bit#(1) v);\n    method Action      bready(Bit#(1) v);\n    method Bit#(2)     bresp();\n    method Bit#(1)     bvalid();\n    method Bit#(32)     rdata();\n    method Action      rready(Bit#(1) v);\n    method Bit#(2)     rresp();\n    method Bit#(1)     rvalid();\n    method Action      wdata(Bit#(32) v);\n    method Bit#(1)     wready();\n    method Action      wstrb(Bit#(4) v);\n    method Action      wvalid(Bit#(1) v);\nendinterface\n(* always_ready, always_enabled *)\ninterface AxiiicScl;\n    method Action      i(Bit#(1) v);\n    method Bit#(1)     o();\n    method Bit#(1)     t();\nendinterface\n(* always_ready, always_enabled *)\ninterface AxiiicSda;\n    method Action      i(Bit#(1) v);\n    method Bit#(1)     o();\n    method Bit#(1)     t();\nendinterface\n(* always_ready, always_enabled *)\ninterface AxiIic;\n    method Bit#(8)     gpo();\n    method Bit#(1)     iic2intc_irpt();\n    interface AxiiicS_axi     s_axi;\n    interface AxiiicScl     scl;\n    interface AxiiicSda     sda;\nendinterface\nimport \"BVI\" axi_iic_0 =\nmodule mkAxiIicBvi#(Clock s_axi_aclk, Reset s_axi_aresetn)(AxiIic);\n    default_clock clk();\n    default_reset rst();\n        input_clock s_axi_aclk(s_axi_aclk) = s_axi_aclk;\n        input_reset s_axi_aresetn(s_axi_aresetn) = s_axi_aresetn;\n    method gpo gpo();\n    method iic2intc_irpt iic2intc_irpt();\n    interface AxiiicS_axi     s_axi;\n        method araddr(s_axi_araddr) clocked_by (s_axi_aclk) reset_by (s_axi_aresetn) enable((*inhigh*) EN_s_axi_araddr);\n        method s_axi_arready arready() clocked_by (s_axi_aclk) reset_by (s_axi_aresetn);\n        method arvalid(s_axi_arvalid) clocked_by (s_axi_aclk) reset_by (s_axi_aresetn) enable((*inhigh*) EN_s_axi_arvalid);\n        method awaddr(s_axi_awaddr) clocked_by (s_axi_aclk) reset_by (s_axi_aresetn) enable((*inhigh*) EN_s_axi_awaddr);\n        method s_axi_awready awready() clocked_by (s_axi_aclk) reset_by (s_axi_aresetn);\n        method awvalid(s_axi_awvalid) clocked_by (s_axi_aclk) reset_by (s_axi_aresetn) enable((*inhigh*) EN_s_axi_awvalid);\n        method bready(s_axi_bready) clocked_by (s_axi_aclk) reset_by (s_axi_aresetn) enable((*inhigh*) EN_s_axi_bready);\n        method s_axi_bresp bresp() clocked_by (s_axi_aclk) reset_by (s_axi_aresetn);\n        method s_axi_bvalid bvalid() clocked_by (s_axi_aclk) reset_by (s_axi_aresetn);\n        method s_axi_rdata rdata() clocked_by (s_axi_aclk) reset_by (s_axi_aresetn);\n        method rready(s_axi_rready) clocked_by (s_axi_aclk) reset_by (s_axi_aresetn) enable((*inhigh*) EN_s_axi_rready);\n        method s_axi_rresp rresp() clocked_by (s_axi_aclk) reset_by (s_axi_aresetn);\n        method s_axi_rvalid rvalid() clocked_by (s_axi_aclk) reset_by (s_axi_aresetn);\n        method wdata(s_axi_wdata) clocked_by (s_axi_aclk) reset_by (s_axi_aresetn) enable((*inhigh*) EN_s_axi_wdata);\n        method s_axi_wready wready() clocked_by (s_axi_aclk) reset_by (s_axi_aresetn);\n        method wstrb(s_axi_wstrb) clocked_by (s_axi_aclk) reset_by (s_axi_aresetn) enable((*inhigh*) EN_s_axi_wstrb);\n        method wvalid(s_axi_wvalid) clocked_by (s_axi_aclk) reset_by (s_axi_aresetn) enable((*inhigh*) EN_s_axi_wvalid);\n    endinterface\n    interface AxiiicScl     scl;\n        method i(scl_i) enable((*inhigh*) EN_scl_i);\n        method scl_o o();\n        method scl_t t();\n    endinterface\n    interface AxiiicSda     sda;\n        method i(sda_i) enable((*inhigh*) EN_sda_i);\n        method sda_o o();\n        method sda_t t();\n    endinterface\n    schedule (gpo, iic2intc_irpt, s_axi.araddr, s_axi.arready, s_axi.arvalid, s_axi.awaddr, s_axi.awready, s_axi.awvalid, s_axi.bready, s_axi.bresp, s_axi.bvalid, s_axi.rdata, s_axi.rready, s_axi.rresp, s_axi.rvalid, s_axi.wdata, s_axi.wready, s_axi.wstrb, s_axi.wvalid, scl.i, scl.o, scl.t, sda.i, sda.o, sda.t) CF (gpo, iic2intc_irpt, s_axi.araddr, s_axi.arready, s_axi.arvalid, s_axi.awaddr, s_axi.awready, s_axi.awvalid, s_axi.bready, s_axi.bresp, s_axi.bvalid, s_axi.rdata, s_axi.rready, s_axi.rresp, s_axi.rvalid, s_axi.wdata, s_axi.wready, s_axi.wstrb, s_axi.wvalid, scl.i, scl.o, scl.t, sda.i, sda.o, sda.t);\nendmodule\n\ninstance ToAxi4SlaveBits#(Axi4SlaveLiteBits#(9,32), AxiiicS_axi);\n   function Axi4SlaveLiteBits#(9,32) toAxi4SlaveBits(AxiiicS_axi s);\n      return (interface Axi4SlaveLiteBits#(9,32);\n\t method araddr = s.araddr;\n\t method arready = s.arready;\n\t method arvalid = s.arvalid;\n\t method awaddr = s.awaddr;\n\t method awready = s.awready;\n\t method awvalid = s.awvalid;\n\t method bready = s.bready;\n\t method bresp = s.bresp;\n\t method bvalid = s.bvalid;\n\t method rdata = s.rdata;\n\t method rready = s.rready;\n\t method rresp = s.rresp;\n\t method rvalid = s.rvalid;\n\t method wdata = s.wdata;\n\t method wready = s.wready;\n\t method Action      wvalid(Bit#(1) v);\n\t    s.wvalid(v);\n\t    s.wstrb(pack(replicate(v)));\n\t endmethod\n\t endinterface);\n   endfunction\nendinstance\n"
  },
  {
    "path": "tests/spikehw/AxiSpiBvi.bsv",
    "content": "\n/*\n   ../../generated/scripts/importbvi.py\n   -I\n   AxiSpiBvi\n   -P\n   AxiSpi\n   -c\n   ext_spi_clk\n   -c\n   s_axi_aclk\n   -r\n   s_axi_aresetn\n   -n\n   ip2intc_irpt\n   -o\n   AxiSpiBvi.bsv\n   cores/nfsume/axi_spi_0/axi_spi_0_stub.v\n*/\n\nimport Clocks::*;\nimport DefaultValue::*;\nimport XilinxCells::*;\nimport GetPut::*;\nimport Vector::*;\nimport AxiBits::*;\n\n(* always_ready, always_enabled *)\n(* always_ready, always_enabled *)\ninterface AxispiIo;\n    method Action      i(Bit#(1) v);\n    method Bit#(1)     o();\n    method Bit#(1)     t();\nendinterface\n(* always_ready, always_enabled *)\ninterface AxispiS_axi;\n    method Action      araddr(Bit#(7) v);\n    method Bit#(1)     arready();\n    method Action      arvalid(Bit#(1) v);\n    method Action      awaddr(Bit#(7) v);\n    method Bit#(1)     awready();\n    method Action      awvalid(Bit#(1) v);\n    method Action      bready(Bit#(1) v);\n    method Bit#(2)     bresp();\n    method Bit#(1)     bvalid();\n    method Bit#(32)     rdata();\n    method Action      rready(Bit#(1) v);\n    method Bit#(2)     rresp();\n    method Bit#(1)     rvalid();\n    method Action      wdata(Bit#(32) v);\n    method Bit#(1)     wready();\n    method Action      wstrb(Bit#(4) v);\n    method Action      wvalid(Bit#(1) v);\nendinterface\n(* always_ready, always_enabled *)\ninterface AxispiSck;\n    method Action      i(Bit#(1) v);\n    method Bit#(1)     o();\n    method Bit#(1)     t();\nendinterface\n(* always_ready, always_enabled *)\ninterface AxispiSs;\n    method Action      i(Bit#(1) v);\n    method Bit#(1)     o();\n    method Bit#(1)     t();\nendinterface\n(* always_ready, always_enabled *)\ninterface AxiSpiBvi;\n    interface AxispiIo     io0;\n    interface AxispiIo     io1;\n    method Bit#(1)     ip2intc_irpt();\n    interface AxispiS_axi     s_axi;\n    interface AxispiSck     sck;\n    interface AxispiSs     ss;\nendinterface\nimport \"BVI\" axi_spi_0 =\nmodule mkAxiSpiBvi#(Clock ext_spi_clk, Clock s_axi_aclk, Reset s_axi_aresetn)(AxiSpiBvi);\n    default_clock clk();\n    default_reset rst();\n        input_clock ext_spi_clk(ext_spi_clk) = ext_spi_clk;\n        input_clock s_axi_aclk(s_axi_aclk) = s_axi_aclk;\n        input_reset s_axi_aresetn(s_axi_aresetn) = s_axi_aresetn;\n    interface AxispiIo     io0;\n        method i(io0_i) enable((*inhigh*) EN_io0_i);\n        method io0_o o();\n        method io0_t t();\n    endinterface\n    interface AxispiIo     io1;\n        method i(io1_i) enable((*inhigh*) EN_io1_i);\n        method io1_o o();\n        method io1_t t();\n    endinterface\n    method ip2intc_irpt ip2intc_irpt();\n    interface AxispiS_axi     s_axi;\n        method araddr(s_axi_araddr) clocked_by (s_axi_aclk) reset_by (s_axi_aresetn) enable((*inhigh*) EN_s_axi_araddr);\n        method s_axi_arready arready() clocked_by (s_axi_aclk) reset_by (s_axi_aresetn);\n        method arvalid(s_axi_arvalid) clocked_by (s_axi_aclk) reset_by (s_axi_aresetn) enable((*inhigh*) EN_s_axi_arvalid);\n        method awaddr(s_axi_awaddr) clocked_by (s_axi_aclk) reset_by (s_axi_aresetn) enable((*inhigh*) EN_s_axi_awaddr);\n        method s_axi_awready awready() clocked_by (s_axi_aclk) reset_by (s_axi_aresetn);\n        method awvalid(s_axi_awvalid) clocked_by (s_axi_aclk) reset_by (s_axi_aresetn) enable((*inhigh*) EN_s_axi_awvalid);\n        method bready(s_axi_bready) clocked_by (s_axi_aclk) reset_by (s_axi_aresetn) enable((*inhigh*) EN_s_axi_bready);\n        method s_axi_bresp bresp() clocked_by (s_axi_aclk) reset_by (s_axi_aresetn);\n        method s_axi_bvalid bvalid() clocked_by (s_axi_aclk) reset_by (s_axi_aresetn);\n        method s_axi_rdata rdata() clocked_by (s_axi_aclk) reset_by (s_axi_aresetn);\n        method rready(s_axi_rready) clocked_by (s_axi_aclk) reset_by (s_axi_aresetn) enable((*inhigh*) EN_s_axi_rready);\n        method s_axi_rresp rresp() clocked_by (s_axi_aclk) reset_by (s_axi_aresetn);\n        method s_axi_rvalid rvalid() clocked_by (s_axi_aclk) reset_by (s_axi_aresetn);\n        method wdata(s_axi_wdata) clocked_by (s_axi_aclk) reset_by (s_axi_aresetn) enable((*inhigh*) EN_s_axi_wdata);\n        method s_axi_wready wready() clocked_by (s_axi_aclk) reset_by (s_axi_aresetn);\n        method wstrb(s_axi_wstrb) clocked_by (s_axi_aclk) reset_by (s_axi_aresetn) enable((*inhigh*) EN_s_axi_wstrb);\n        method wvalid(s_axi_wvalid) clocked_by (s_axi_aclk) reset_by (s_axi_aresetn) enable((*inhigh*) EN_s_axi_wvalid);\n    endinterface\n    interface AxispiSck     sck;\n        method i(sck_i) enable((*inhigh*) EN_sck_i);\n        method sck_o o();\n        method sck_t t();\n    endinterface\n    interface AxispiSs     ss;\n        method i(ss_i) enable((*inhigh*) EN_ss_i);\n        method ss_o o();\n        method ss_t t();\n    endinterface\n    schedule (io0.i, io0.o, io0.t, io1.i, io1.o, io1.t, ip2intc_irpt, s_axi.araddr, s_axi.arready, s_axi.arvalid, s_axi.awaddr, s_axi.awready, s_axi.awvalid, s_axi.bready, s_axi.bresp, s_axi.bvalid, s_axi.rdata, s_axi.rready, s_axi.rresp, s_axi.rvalid, s_axi.wdata, s_axi.wready, s_axi.wstrb, s_axi.wvalid, sck.i, sck.o, sck.t, ss.i, ss.o, ss.t) CF (io0.i, io0.o, io0.t, io1.i, io1.o, io1.t, ip2intc_irpt, s_axi.araddr, s_axi.arready, s_axi.arvalid, s_axi.awaddr, s_axi.awready, s_axi.awvalid, s_axi.bready, s_axi.bresp, s_axi.bvalid, s_axi.rdata, s_axi.rready, s_axi.rresp, s_axi.rvalid, s_axi.wdata, s_axi.wready, s_axi.wstrb, s_axi.wvalid, sck.i, sck.o, sck.t, ss.i, ss.o, ss.t);\nendmodule\n\ninstance ToAxi4SlaveBits#(Axi4SlaveLiteBits#(7,32), AxispiS_axi);\n   function Axi4SlaveLiteBits#(7,32) toAxi4SlaveBits(AxispiS_axi s);\n      return (interface Axi4SlaveLiteBits#(7,32);\n\t method araddr = s.araddr;\n\t method arready = s.arready;\n\t method arvalid = s.arvalid;\n\t method awaddr = s.awaddr;\n\t method awready = s.awready;\n\t method awvalid = s.awvalid;\n\t method bready = s.bready;\n\t method bresp = s.bresp;\n\t method bvalid = s.bvalid;\n\t method rdata = s.rdata;\n\t method rready = s.rready;\n\t method rresp = s.rresp;\n\t method rvalid = s.rvalid;\n\t method wdata = s.wdata;\n\t method wready = s.wready;\n\t method Action      wvalid(Bit#(1) v);\n\t    s.wvalid(v);\n\t    s.wstrb(pack(replicate(v)));\n\t endmethod\n\t endinterface);\n   endfunction\nendinstance\n"
  },
  {
    "path": "tests/spikehw/AxiUart.bsv",
    "content": "\n/*\n   /home/jamey/connectal.clean/generated/scripts/importbvi.py\n   -P\n   AxiUart\n   -I\n   AxiUart\n   -c\n   s_axi_aclk\n   -r\n   s_axi_aresetn\n   -n\n   ip2intc_irpt\n   -n\n   out1n\n   -n\n   out2n\n   -o\n   AxiUart.bsv\n   cores/vc709/axi_uart16550_1/axi_uart16550_1_stub.v\n*/\n\nimport Clocks::*;\nimport DefaultValue::*;\nimport XilinxCells::*;\nimport GetPut::*;\nimport AxiBits::*;\nimport Vector::*;\n\n(* always_ready, always_enabled *)\ninterface AxiuartS_axi;\n    method Action      araddr(Bit#(13) v);\n    method Bit#(1)     arready();\n    method Action      arvalid(Bit#(1) v);\n    method Action      awaddr(Bit#(13) v);\n    method Bit#(1)     awready();\n    method Action      awvalid(Bit#(1) v);\n    method Action      bready(Bit#(1) v);\n    method Bit#(2)     bresp();\n    method Bit#(1)     bvalid();\n    method Bit#(32)     rdata();\n    method Action      rready(Bit#(1) v);\n    method Bit#(2)     rresp();\n    method Bit#(1)     rvalid();\n    method Action      wdata(Bit#(32) v);\n    method Bit#(1)     wready();\n    method Action      wstrb(Bit#(4) v);\n    method Action      wvalid(Bit#(1) v);\nendinterface\n(* always_ready, always_enabled *)\ninterface AxiUart;\n    method Bit#(1)     baudoutn();\n    method Action      ctsn(Bit#(1) v);\n    method Action      dcdn(Bit#(1) v);\n    method Bit#(1)     ddis();\n    method Action      dsrn(Bit#(1) v);\n    method Bit#(1)     dtrn();\n    method Action      freeze(Bit#(1) v);\n    method Bit#(1)     ip2intc_irpt();\n    method Bit#(1)     out1n();\n    method Bit#(1)     out2n();\n    method Action      rin(Bit#(1) v);\n    method Bit#(1)     rtsn();\n    method Bit#(1)     rxrdyn();\n    interface AxiuartS_axi     s_axi;\n    method Action      sin(Bit#(1) v);\n    method Bit#(1)     sout();\n    method Bit#(1)     txrdyn();\n    method Bit#(1)     xout();\nendinterface\nimport \"BVI\" axi_uart16550_1 =\nmodule mkAxiUartBvi#(Clock s_axi_aclk, Reset s_axi_aresetn, Clock uartClk)(AxiUart);\n    default_clock clk();\n    default_reset rst();\n        input_clock s_axi_aclk(s_axi_aclk) = s_axi_aclk;\n        input_reset s_axi_aresetn(s_axi_aresetn) = s_axi_aresetn;\n    input_clock xin(xin) = uartClk;\n    method baudoutn baudoutn();\n    method ctsn(ctsn) enable((*inhigh*) EN_ctsn);\n    method dcdn(dcdn) enable((*inhigh*) EN_dcdn);\n    method ddis ddis();\n    method dsrn(dsrn) enable((*inhigh*) EN_dsrn);\n    method dtrn dtrn();\n    method freeze(freeze) enable((*inhigh*) EN_freeze);\n    method ip2intc_irpt ip2intc_irpt();\n    method out1n out1n();\n    method out2n out2n();\n    method rin(rin) enable((*inhigh*) EN_rin);\n    method rtsn rtsn();\n    method rxrdyn rxrdyn();\n    interface AxiuartS_axi     s_axi;\n        method araddr(s_axi_araddr) clocked_by (s_axi_aclk) reset_by (s_axi_aresetn) enable((*inhigh*) EN_s_axi_araddr);\n        method s_axi_arready arready() clocked_by (s_axi_aclk) reset_by (s_axi_aresetn);\n        method arvalid(s_axi_arvalid) clocked_by (s_axi_aclk) reset_by (s_axi_aresetn) enable((*inhigh*) EN_s_axi_arvalid);\n        method awaddr(s_axi_awaddr) clocked_by (s_axi_aclk) reset_by (s_axi_aresetn) enable((*inhigh*) EN_s_axi_awaddr);\n        method s_axi_awready awready() clocked_by (s_axi_aclk) reset_by (s_axi_aresetn);\n        method awvalid(s_axi_awvalid) clocked_by (s_axi_aclk) reset_by (s_axi_aresetn) enable((*inhigh*) EN_s_axi_awvalid);\n        method bready(s_axi_bready) clocked_by (s_axi_aclk) reset_by (s_axi_aresetn) enable((*inhigh*) EN_s_axi_bready);\n        method s_axi_bresp bresp() clocked_by (s_axi_aclk) reset_by (s_axi_aresetn);\n        method s_axi_bvalid bvalid() clocked_by (s_axi_aclk) reset_by (s_axi_aresetn);\n        method s_axi_rdata rdata() clocked_by (s_axi_aclk) reset_by (s_axi_aresetn);\n        method rready(s_axi_rready) clocked_by (s_axi_aclk) reset_by (s_axi_aresetn) enable((*inhigh*) EN_s_axi_rready);\n        method s_axi_rresp rresp() clocked_by (s_axi_aclk) reset_by (s_axi_aresetn);\n        method s_axi_rvalid rvalid() clocked_by (s_axi_aclk) reset_by (s_axi_aresetn);\n        method wdata(s_axi_wdata) clocked_by (s_axi_aclk) reset_by (s_axi_aresetn) enable((*inhigh*) EN_s_axi_wdata);\n        method s_axi_wready wready() clocked_by (s_axi_aclk) reset_by (s_axi_aresetn);\n        method wstrb(s_axi_wstrb) clocked_by (s_axi_aclk) reset_by (s_axi_aresetn) enable((*inhigh*) EN_s_axi_wstrb);\n        method wvalid(s_axi_wvalid) clocked_by (s_axi_aclk) reset_by (s_axi_aresetn) enable((*inhigh*) EN_s_axi_wvalid);\n    endinterface\n    method sin(sin) enable((*inhigh*) EN_sin);\n    method sout sout();\n    method txrdyn txrdyn();\n    method xout xout();\n    schedule (baudoutn, ctsn, dcdn, ddis, dsrn, dtrn, freeze, ip2intc_irpt, out1n, out2n, rin, rtsn, rxrdyn, s_axi.araddr, s_axi.arready, s_axi.arvalid, s_axi.awaddr, s_axi.awready, s_axi.awvalid, s_axi.bready, s_axi.bresp, s_axi.bvalid, s_axi.rdata, s_axi.rready, s_axi.rresp, s_axi.rvalid, s_axi.wdata, s_axi.wready, s_axi.wstrb, s_axi.wvalid, sin, sout, txrdyn, xout) CF (baudoutn, ctsn, dcdn, ddis, dsrn, dtrn, freeze, ip2intc_irpt, out1n, out2n, rin, rtsn, rxrdyn, s_axi.araddr, s_axi.arready, s_axi.arvalid, s_axi.awaddr, s_axi.awready, s_axi.awvalid, s_axi.bready, s_axi.bresp, s_axi.bvalid, s_axi.rdata, s_axi.rready, s_axi.rresp, s_axi.rvalid, s_axi.wdata, s_axi.wready, s_axi.wstrb, s_axi.wvalid, sin, sout, txrdyn, xout);\nendmodule\n\ninstance ToAxi4SlaveBits#(Axi4SlaveLiteBits#(12,32), AxiuartS_axi);\n   function Axi4SlaveLiteBits#(12,32) toAxi4SlaveBits(AxiuartS_axi s);\n      return (interface Axi4SlaveLiteBits#(12,32);\n\t method Action araddr(Bit#(12) addr); s.araddr(extend(addr)); endmethod\n\t method arready = s.arready;\n\t method arvalid = s.arvalid;\n\t method Action awaddr(Bit#(12) addr); s.awaddr(extend(addr)); endmethod\n\t method awready = s.awready;\n\t method awvalid = s.awvalid;\n\t method bready = s.bready;\n\t method bresp = s.bresp;\n\t method bvalid = s.bvalid;\n\t method rdata = s.rdata;\n\t method rready = s.rready;\n\t method rresp = s.rresp;\n\t method rvalid = s.rvalid;\n\t method wdata = s.wdata;\n\t method wready = s.wready;\n\t method Action      wvalid(Bit#(1) v);\n\t    s.wvalid(v);\n\t    s.wstrb(pack(replicate(v)));\n\t endmethod\n\t endinterface);\n   endfunction\nendinstance\n"
  },
  {
    "path": "tests/spikehw/GigEthPcsPmaBvi.bsv",
    "content": "\n/*\n   /home/jamey/connectal.clean/generated/scripts/importbvi.py\n   -o\n   GigEthPcsPma.bsv\n   -P\n   GigEthPcsPmaBvi\n   -I\n   GigEthPcsPmaBvi\n   -c\n   gtrefclk_out\n   -c\n   userclk_out\n   -c\n   userclk2_out\n   -c\n   rxuserclk_out\n   -c\n   rxuserclk2_out\n   -c\n   independent_clock_bufg\n   -r\n   pma_reset_out\n   -r\n   reset\n   -c\n   gt0_qplloutclk_out\n   -c\n   gt0_qplloutrefclk_out\n   ../FPGA/rtl/vc709/gig_ethernet_pcs_pma_0/gig_ethernet_pcs_pma_0_stub.v\n*/\n\nimport Clocks::*;\nimport DefaultValue::*;\nimport XilinxCells::*;\nimport GetPut::*;\n\n(* always_ready, always_enabled *)\ninterface GigethpcspmabviAn;\n    method Action      adv_config_val(Bit#(1) v);\n    method Action      adv_config_vector(Bit#(16) v);\n    method Bit#(1)     interrupt();\n    method Action      restart_config(Bit#(1) v);\nendinterface\n(* always_ready, always_enabled *)\ninterface GigethpcspmabviConfiguration;\n    method Action      valid(Bit#(1) v);\n    method Action      vector(Bit#(5) v);\nendinterface\n(* always_ready, always_enabled *)\ninterface GigethpcspmabviGmii;\n    method Bit#(1)     isolate();\n    method Bit#(1)     rx_dv();\n    method Bit#(1)     rx_er();\n    method Bit#(8)     rxd();\n    method Action      tx_en(Bit#(1) v);\n    method Action      tx_er(Bit#(1) v);\n    method Action      txd(Bit#(8) v);\nendinterface\n(* always_ready, always_enabled *)\ninterface GigethpcspmabviGt;\n    interface Clock     qplloutclk_out;\n    interface Clock     qplloutrefclk_out;\nendinterface\n(* always_ready, always_enabled *)\ninterface GigethpcspmabviGtrefclk;\n    method Action      n(Bit#(1) v);\n    interface Clock     out;\n    method Action      p(Bit#(1) v);\nendinterface\n(* always_ready, always_enabled *)\n(* always_ready, always_enabled *)\ninterface GigethpcspmabviMdio;\n    method Action      i(Bit#(1) v);\n    method Bit#(1)     o();\n    method Bit#(1)     t();\nendinterface\n(* always_ready, always_enabled *)\ninterface GigethpcspmabviMmcm;\n    method Bit#(1)     locked_out();\nendinterface\n(* always_ready, always_enabled *)\ninterface GigethpcspmabviPma;\n    method Reset     reset_out();\nendinterface\n(* always_ready, always_enabled *)\ninterface GigethpcspmabviRxuserclk;\n    interface Clock     out;\nendinterface\n(* always_ready, always_enabled *)\ninterface GigethpcspmabviSignal;\n    method Action      detect(Bit#(1) v);\nendinterface\n(* always_ready, always_enabled *)\ninterface GigethpcspmabviStatus;\n    method Bit#(16)     vector();\nendinterface\n(* always_ready, always_enabled *)\ninterface GigethpcspmabviUserclk;\n    interface Clock     out;\nendinterface\n(* always_ready, always_enabled *)\ninterface GigEthPcsPmaBvi;\n    interface GigethpcspmabviAn     an;\n    interface GigethpcspmabviConfiguration     configuration;\n    interface GigethpcspmabviGmii     gmii;\n    interface GigethpcspmabviGt     gt0;\n    interface GigethpcspmabviGtrefclk     gtrefclk;\n    method Action      mdc(Bit#(1) v);\n    interface GigethpcspmabviMdio     mdio;\n    interface GigethpcspmabviMmcm     mmcm;\n    interface GigethpcspmabviPma     pma;\n    method Bit#(1)     resetdone();\n    method Action      rxn(Bit#(1) v);\n    method Action      rxp(Bit#(1) v);\n    interface GigethpcspmabviRxuserclk     rxuserclk2;\n    interface GigethpcspmabviRxuserclk     rxuserclk;\n    interface GigethpcspmabviSignal     signal;\n    interface GigethpcspmabviStatus     status;\n    method Bit#(1)     txn();\n    method Bit#(1)     txp();\n    interface GigethpcspmabviUserclk     userclk2;\n    interface GigethpcspmabviUserclk     userclk;\nendinterface\nimport \"BVI\" gig_ethernet_pcs_pma_0 =\nmodule mkGigEthPcsPmaBvi#(Clock independent_clock_bufg, Reset reset_n)(GigEthPcsPmaBvi);\n   let invertedReset <- mkResetInverter(reset_n, clocked_by independent_clock_bufg);\n   default_clock clk();\n   default_reset rst_n();\n   input_clock independent_clock_bufg(independent_clock_bufg) = independent_clock_bufg;\n   input_reset reset(reset) clocked_by (independent_clock_bufg) = invertedReset;\n    interface GigethpcspmabviAn     an;\n        method adv_config_val(an_adv_config_val) enable((*inhigh*) EN_an_adv_config_val);\n        method adv_config_vector(an_adv_config_vector) enable((*inhigh*) EN_an_adv_config_vector);\n        method an_interrupt interrupt();\n        method restart_config(an_restart_config) enable((*inhigh*) EN_an_restart_config);\n    endinterface\n    interface GigethpcspmabviConfiguration     configuration;\n        method valid(configuration_valid) enable((*inhigh*) EN_configuration_valid);\n        method vector(configuration_vector) enable((*inhigh*) EN_configuration_vector);\n    endinterface\n    interface GigethpcspmabviGmii     gmii;\n        method gmii_isolate isolate();\n        method gmii_rx_dv rx_dv();\n        method gmii_rx_er rx_er();\n        method gmii_rxd rxd();\n        method tx_en(gmii_tx_en) enable((*inhigh*) EN_gmii_tx_en);\n        method tx_er(gmii_tx_er) enable((*inhigh*) EN_gmii_tx_er);\n        method txd(gmii_txd) enable((*inhigh*) EN_gmii_txd);\n    endinterface\n    interface GigethpcspmabviGt     gt0;\n        output_clock qplloutclk_out(gt0_qplloutclk_out);\n        output_clock qplloutrefclk_out(gt0_qplloutrefclk_out);\n    endinterface\n    interface GigethpcspmabviGtrefclk     gtrefclk;\n        method n(gtrefclk_n) enable((*inhigh*) EN_gtrefclk_n);\n        output_clock out(gtrefclk_out);\n        method p(gtrefclk_p) enable((*inhigh*) EN_gtrefclk_p);\n    endinterface\n    method mdc(mdc) enable((*inhigh*) EN_mdc);\n    interface GigethpcspmabviMdio     mdio;\n        method i(mdio_i) enable((*inhigh*) EN_mdio_i);\n        method mdio_o o();\n        method mdio_t t();\n    endinterface\n    interface GigethpcspmabviMmcm     mmcm;\n        method mmcm_locked_out locked_out();\n    endinterface\n    interface GigethpcspmabviPma     pma;\n        output_reset reset_out(pma_reset_out);\n    endinterface\n    method resetdone resetdone();\n    method rxn(rxn) enable((*inhigh*) EN_rxn);\n    method rxp(rxp) enable((*inhigh*) EN_rxp);\n    interface GigethpcspmabviRxuserclk     rxuserclk2;\n        output_clock out(rxuserclk2_out);\n    endinterface\n    interface GigethpcspmabviRxuserclk     rxuserclk;\n        output_clock out(rxuserclk_out);\n    endinterface\n    interface GigethpcspmabviSignal     signal;\n        method detect(signal_detect) enable((*inhigh*) EN_signal_detect);\n    endinterface\n    interface GigethpcspmabviStatus     status;\n        method status_vector vector();\n    endinterface\n    method txn txn();\n    method txp txp();\n    interface GigethpcspmabviUserclk     userclk2;\n        output_clock out(userclk2_out);\n    endinterface\n    interface GigethpcspmabviUserclk     userclk;\n        output_clock out(userclk_out);\n    endinterface\n    schedule (an.adv_config_val, an.adv_config_vector, an.interrupt, an.restart_config, configuration.valid, configuration.vector, gmii.isolate, gmii.rx_dv, gmii.rx_er, gmii.rxd, gmii.tx_en, gmii.tx_er, gmii.txd, gtrefclk.n, gtrefclk.p, mdc, mdio.i, mdio.o, mdio.t, mmcm.locked_out, resetdone, rxn, rxp, signal.detect, status.vector, txn, txp) CF (an.adv_config_val, an.adv_config_vector, an.interrupt, an.restart_config, configuration.valid, configuration.vector, gmii.isolate, gmii.rx_dv, gmii.rx_er, gmii.rxd, gmii.tx_en, gmii.tx_er, gmii.txd, gtrefclk.n, gtrefclk.p, mdc, mdio.i, mdio.o, mdio.t, mmcm.locked_out, resetdone, rxn, rxp, signal.detect, status.vector, txn, txp);\nendmodule\n\n(* always_ready, always_enabled *)\ninterface GigEthPcsPmaPins;\n    method Action      rxn(Bit#(1) v);\n    method Action      rxp(Bit#(1) v);\n    method Bit#(1)     txn();\n    method Bit#(1)     txp();\n    method Action      gtrefclkp(Bit#(1) v);\n    method Action      gtrefclkn(Bit#(1) v);\nendinterface\n\n(* always_ready, always_enabled *)\ninterface GigEthPcsPmaTxPins;\n    method Bit#(1)     txn();\n    method Bit#(1)     txp();\nendinterface\n\ninterface GigEthPcsPmaDebug;\n    method Bit#(1)     locked_out();\n    method Bit#(16)    status();\n    method Bit#(1)     resetdone();\nendinterface\n\ninterface GigEthPcsPma;\n   method Action      mdc(Bit#(1) v);\n   interface GigethpcspmabviMdio     mdio;\n   interface GigethpcspmabviGmii     gmii;\n   interface GigEthPcsPmaPins        pins;\n   interface GigEthPcsPmaDebug       debug;\n   interface Clock                   gtrefclk;\n   method Bit#(1) interrupt();\nendinterface\n\nmodule mkGigEthPcsPma#(Clock independent_clock_bufg, Reset reset)(GigEthPcsPma);\n   GigEthPcsPmaBvi bvi <- mkGigEthPcsPmaBvi(independent_clock_bufg, reset);\n\n   rule rl_detect;\n      bvi.signal.detect(1);\n   endrule\n\n   method      mdc = bvi.mdc;\n   interface mdio = bvi.mdio;\n   interface gmii = bvi.gmii;\n   interface gtrefclk = bvi.gtrefclk.out;\n   interface GigEthPcsPmaPins pins;\n      method rxn = bvi.rxn;\n      method rxp = bvi.rxp;\n      method txn = bvi.txn;\n      method txp = bvi.txp;\n      method gtrefclkp = bvi.gtrefclk.p;\n      method gtrefclkn = bvi.gtrefclk.n;\n   endinterface\n   method interrupt = bvi.an.interrupt;\n   interface GigEthPcsPmaDebug debug;\n      method locked_out = bvi.mmcm.locked_out;\n      method status = bvi.status.vector();\n      method resetdone  = bvi.resetdone;\n   endinterface\n\nendmodule\n"
  },
  {
    "path": "tests/spikehw/Makefile",
    "content": "\nINCLUDE_ETHERNET=1\n\nSPIKE_DIR=/home/jamey/riscv-isa-sim\nCONNECTALDIR?=../..\n\nS2H_INTERFACES = SpikeHwRequest:SpikeHw.request\nH2S_INTERFACES = SpikeHw:SpikeHwIndication:host\n\nMEM_READ_INTERFACES = lSpikeHw.dmaReadClient\nMEM_WRITE_INTERFACES = lSpikeHw.dmaWriteClient\n\nCONNECTALFLAGS+= -P mkConnectalTop\nCONNECTALFLAGS += --derivedclockperiod=67.81684027\n\nRISCV_INCLUDES = -I$(SPIKE_DIR) -I$(SPIKE_DIR)/build\nCONNECTALFLAGS += $(RISCV_INCLUDES) --cxxflags=-std=c++11\n\nBSVFILES =  $(CONNECTALDIR)/bsv/MemTypes.bsv $(CONNECTALDIR)/bsv/ConnectalConfig.bsv SpikeHwIfc.bsv\nCPPFILES= spikehw.cpp\nifeq ($(BOARD),miniitx100)\nCPPFILES += test-spikehw.cpp\nelse\nCONNECTALFLAGS+= --shared\nendif\n\n# ifneq ($(BOARD),vc709)\n# CONNECTALFLAGS+= --verilog=i28f512p33.v\n# endif\n\nifneq ($(BOARD),xsim)\nifeq ($(BOARD),nfsume)\nPINOUT_FILE += nfsume.json\nelse\nPINOUT_FILE += spikehw.json\n#PINOUT_FILE += rtscts.json\n#PINOUT_FILE += eth.json\nPINOUT_FILE += spikehw-$(BOARD).json\nifneq ($(BOARD),miniitx100)\nPINOUT_FILE += i2c-standard.json\nendif # not minitx100\nendif # not nfsume\nendif # not xsim\n\nifeq ($(BOARD),vc707g2)\nCONNECTALFLAGS += -D IncludeFlash\nendif\n\nPIN_TYPE = SpikeHwPins\nPIN_TYPE_INCLUDE = SpikeHwPins\nAUTOTOP = --interface pins:SpikeHw.pins\n\nCONNECTALFLAGS+= -DDataBusWidth=32\n## ethernet uses the 200MHz SYS clock\nCONNECTALFLAGS += -D XILINX_SYS_CLK -D IMPORT_HOSTIF\nIPDIR=cores\nCONNECTALFLAGS+= --xci=$(IPDIR)/$(BOARD)/axi_intc_0/axi_intc_0.xci\nCONNECTALFLAGS+= --xci=$(IPDIR)/$(BOARD)/axi_iic_0/axi_iic_0.xci\nCONNECTALFLAGS+= --xci=$(IPDIR)/$(BOARD)/axi_spi_0/axi_spi_0.xci\nCONNECTALFLAGS+= --xci=$(IPDIR)/$(BOARD)/axi_uart16550_1/axi_uart16550_1.xci\nCONNECTALFLAGS+= --xci=$(IPDIR)/$(BOARD)/axi_dma_0/axi_dma_0.xci\nCONNECTALFLAGS+= --xci=$(IPDIR)/$(BOARD)/dual_clock_axis_fifo_32x1024/dual_clock_axis_fifo_32x1024.xci\n\nCONNECTALFLAGS += --constraint=spikehw.xdc --implconstraint=spikehw.xdc\n\n##PREBUILD_DEPS = $(IPDIR)/$(BOARD)/axi_dma_0/axi_dma_0.xci $(IPDIR)/$(BOARD)/axi_intc_0/axi_intc_0.xci\n\nifeq ($(INCLUDE_ETHERNET),1)\n#CONNECTALFLAGS+= --xci=$(IPDIR)/$(BOARD)/axi_ethernet_1000basex/axi_ethernet_1000basex.xci\nCONNECTALFLAGS+= --xci=$(IPDIR)/$(BOARD)/tri_mode_ethernet_mac_0/tri_mode_ethernet_mac_0.xci\nCONNECTALFLAGS+= --xci=$(IPDIR)/$(BOARD)/gig_ethernet_pcs_pma_0/gig_ethernet_pcs_pma_0.xci\nCONNECTALFLAGS+= -D IncludeEthernet\n##PREBUILD_DEPS += $(IPDIR)/$(BOARD)/axi_ethernet_0/axi_ethernet_0.xci\nendif\n\nprebuild:: $(PREBUILD_DEPS)\n\tln -sf $(PWD)/bootromx4.hex $(BOARD)\n\n$(IPDIR)/$(BOARD)/axi_intc_0/axi_intc_0.xci: ../../scripts/connectal-synth-axidma.tcl\n\tcd $(BOARD); vivado -mode batch -source $(CONNECTALDIR)/scripts/connectal-synth-axiintc.tcl\n\n$(IPDIR)/$(BOARD)/axi_ethernet_0/axi_ethernet_0.xci: ../../scripts/connectal-synth-axieth.tcl\n\tcd $(BOARD); vivado -mode batch -source $(CONNECTALDIR)/scripts/connectal-synth-axieth.tcl\n\n$(IPDIR)/$(BOARD)/axi_dma_0/axi_dma_0.xci: ../../scripts/connectal-synth-axidma.tcl\n\tcd $(BOARD); vivado -mode batch -source $(CONNECTALDIR)/scripts/connectal-synth-axidma.tcl\n\ntest-spikehw.o: test-spikehw.cpp spikehw.h\n\tg++ $(RISCV_INCLUDES) -std=c++11 -g -O -pthread -c -I. test-spikehw.cpp\n\ntest-spikehw.%: test-spikehw.o\n\t#$(MAKE) build.$(*)\n\tg++ $(RISCV_INCLUDES) -g -O -pthread -o test-spikehw.$(*) test-spikehw.o $(*)/bin/connectal.so -lc \n\ninclude $(CONNECTALDIR)/Makefile.connectal\n\n"
  },
  {
    "path": "tests/spikehw/README.md",
    "content": "Spike Hardware\n==============\n\nThis project provides hardware peripherals to spike, the RISC-V ISA\nsimulator.\n\nTODO\n----\n\n * device tree partitioning of flash\n   * added to riscv_spikehw_defconfig (DONE)\n   * device tree entry for flash works (DONE)\n   * device tree entry for partitions works (registers)\n   * vmlinux partition (DONE)\n   * root partition (DONE)\n * spikehw registering a flash device with spike (DONE)\n * restore console input (wtf)\n * copy vmlinux to flash (via /etc/init.d/rc) (DONE?)\n * pass address of vmlinux in flash to bbl (in riscy version of riscv-pk)\n * boot vmlinux from flash to login prompt (DONE) (AGAIN)\n * copy root fs image to flash (DONE) (AGAIN)\n * boot linux to command prompt using flash root filesystem (DONE)\n * change /etc/default/rcS ROOTFS_READ_ONLY=yes (DONE)\n * boot linux to command prompt using flash for vmlinux and root filesystem (almost done)\n * modify spike to use portalmem for dram so DMA from FPGA works (via register_mem_allocator) (DONE)\n\n * modify spike so devices can raise interrupts (IMPLEMENTED)\n\n * enable boot loader to pass command line to linux\n * modify spike to boot from boot ROM if no executable passed as an argument\n * copy bbl from boot ROM to DRAM (see code in tests/spikehw/boot/ )\n * fix ioremap() so that all 128MB of flash can be mapped\n * switch to coreboot instead of bbl\n * ...\n\nBuilding SpikeHW\n----------------\n\nTo get the sources:\n\n    git clone git://github.com/cambridgehackers/fpgamake\n    git clone git://github.com/cambridgehackers/buildcache\n    git clone git://github.com/cambridgehackers/connectal\n\nI extended spike to enable devices to be registered from extlib's.\n\n    git clone git://github.com/cambridgehackers/cambridgehackers/riscv-isa-sim\n\n    cd connectal/tests/spikehw\n    make build.vc707g2 test-spikehw.vc707g2\n\nTo test it, assuming connectal is installed:\n\n    cd connectal/tests/spikehw\n    ./test-spikehw.vc707g2\n\nYou should see output like the following:\n\n    jamey@bdbm07:~/connectal/tests/spikehw$ ./test-spikehw.vc707g2\n    buffer /home/jamey/connectal/tests/spikehw/vc707g2/bin/connectal.so\n    fpgajtag: elf input file, len 1459190 class 2\n    fpgajtag: unzip input file, len 1040655\n    fpgajtag: Digilent:Digilent Adept USB Device:210203860922; bcd:700\n    count 2/3 cortex -1 dcount 2 trail 0\n    STATUS 00500018 done 0 release_done 0 eos 10 startup_state 4\n    STATUS 00500018 done 0 release_done 0 eos 10 startup_state 4\n    STATUS 0002107a done 0 release_done 0 eos 10 startup_state 0\n    fpgajtag: Starting to send file\n    fpgajtag: Done sending file\n    fpgajtag: bypass already programmed ae\n    STATUS 0002107a done 0 release_done 0 eos 10 startup_state 0\n    Running /usr/bin/pciescan.sh\n    + PATH=/home/jamey/work/build/tools/bin:/home/jamey/work/vendor/android-ndk-r10e:/home/jamey/work/build/tools/bin:/home/jamey/work/vendor/android-ndk-r10e:/home/jamey/bin:/usr/local/sbin:/usr/local/bin:/usr/sbin:/usr/bin:/sbin:/bin:/usr/games:/usr/local/games:/scratch/Xilinx/Vivado/2015.4/bin:/scratch/bluespec/Bluespec-2015.05.beta1/bin:/scratch/android-ndk-r10e:/home/jamey/bin:/sbin\n    ++ lspci -d 1be7:c100\n    ++ sed -e 's/ .*//'\n    + BLUEDEVICE=03:00.0\n    + '[' 03:00.0 '!=' '' ']'\n    + sh -c 'echo 1 >/sys/bus/pci/devices/0000:03:00.0/remove'\n    + sleep 1\n    + rmmod pcieportal\n    + sleep 1\n    + sh -c 'echo 1 >/sys/bus/pci/rescan'\n    + sleep 1\n    subprocess pid 16080 completed status=0 0\n    [initPortalHardwareOnce:256] fd 6 len 0\n    [checkSignature:154] read status from '/dev/connectal' was only 0 bytes long\n    [dmaManagerOnce:44]\n    axi eth status mmcm_locked=1 irq=0 intr sources=0\n    word 0000 of boot ROM 00001137 (expected 00001137)\n    word 0004 of boot ROM 010000ef (expected 010000ef)\n    word 0008 of boot ROM 20000513 (expected 20000513)\n    word 000c of boot ROM 00050067 (expected 00050067)\n    word 0010 of boot ROM 0000006f (expected 0000006f)\n    word 0014 of boot ROM 040007b7 (expected 040007b7)\n    word 0018 of boot ROM 40078793 (expected 40078793)\n    word 001c of boot ROM fc0005b7 (expected fc0005b7)\n    AXI Ethernet Identification 09000000 (expected 09000000)\n    SpikeHw::writeFlash offset=55 value=98\n    Query flash 51.52.59 QRY (expected QRY)\n\nThe last five lines are the actual test output.\n\nIf the first word of the boot ROM is 0, then it is because bootromx4.hex is missing.\n\nLinux Kernel\n------------\n\nThe corresponding RISC-V Linux kernel is available here:\n    git clone git://github.com/cambridgehackers/cambridgehackers/riscv-linux-4.1.y linux\n    cd linux\n\n    ## configure the kernel\n    make ARCH=riscv riscv64_spikehw_defconfig\n\n    ## build the kernel\n    make ARCH=riscv\n\n    ## build the device tree .dtb files\n    make ARCH=riscv dtbs\n\nBBL (in riscv-pk)\n-----------------\n\nI modified BBL to load an ELF file from physical memory (DRAM, boot\nROM, or NOR FLASH) when passed an address instead of a filename.\n\n   git clone git://github.com/cambridgehackers/cambridgehackers/riscv-pk\n\n\n\nUsing Spike HW with Spike\n-------------------------\n\nSpike updated with register_device() available to extlibs:\n\n    git clone git://github.com/cambridgehackers/cambridgehackers/riscv-isa-sim\n\nSee also the pull request: https://github.com/riscv/riscv-isa-sim/pull/37\n\nTo connect spikehw to the hardware:\n\n    spike -extlib=/path/to/vc707g2/bin/connectal.so -m64 ...\n\n\n"
  },
  {
    "path": "tests/spikehw/SpikeHw.bsv",
    "content": "\nimport BuildVector::*;\nimport Clocks::*;\nimport Connectable::*;\nimport GetPut::*;\nimport FIFOF::*;\nimport BRAM::*;\nimport BRAMFIFO::*;\nimport Probe::*;\nimport StmtFSM::*;\nimport TriState::*;\nimport Vector::*;\nimport XilinxCells::*;\nimport Probe::*;\n\nimport ConnectalXilinxCells::*;\nimport ConnectalBramFifo::*;\nimport ConnectalConfig::*;\nimport GetPutWithClocks::*;\nimport CtrlMux::*;\nimport HostInterface::*;\nimport ConnectalMemTypes::*;\nimport Pipe::*;\nimport AxiBits::*;\nimport PhysMemSlaveFromBram::*;\nimport TraceMemClient::*;\n\nimport BpiFlash::*;\nimport AxiIntcBvi::*;\nimport AxiIic::*;\nimport AxiSpiBvi::*;\nimport AxiUart::*;\n`ifdef EthernetSgmii\nimport AxiEthBvi::*;\n`else\n//import AxiEth1000BaseX::*;\nimport AxiEthSubsystem::*;\nimport TriModeMacBvi::*;\nimport GigEthPcsPmaBvi::*;\nimport AxiEthBufferBvi::*;\nimport AxiEth1000BaseX::*; // for interfaces\n`endif\nimport AxiDmaBvi::*;\nimport SpikeHwPins::*;\nimport SpikeHwIfc::*;\n\n`include \"ConnectalProjectConfig.bsv\"\n\ninterface SpikeHw;\n   interface SpikeHwRequest request;\n   interface Vector#(2, MemReadClient#(DataBusWidth)) dmaReadClient;\n   interface Vector#(2, MemWriteClient#(DataBusWidth)) dmaWriteClient;\n   interface SpikeHwPins pins;\nendinterface\n\ntypedef 65536 BootRomBytes;\ntypedef TDiv#(BootRomBytes,4) BootRomEntries;\n\nmodule mkBramBootRom(Server#(BRAMRequest#(Bit#(TLog#(BootRomEntries)),Bit#(32)),Bit#(32)));\n   BRAM_Configure cfg = defaultValue;\n   cfg.memorySize = valueOf(BootRomEntries); // 128KB (32K x 4bytes)\n   cfg.latency = 2;\n   cfg.loadFormat = tagged Hex \"bootromx4.hex\";\n\n   BRAM1Port#(Bit#(TLog#(BootRomEntries)), Bit#(32)) bram <- mkBRAM1Server(cfg);\n   return bram.portA;\nendmodule\n\nmodule mkSpikeHw#(HostInterface host, SpikeHwIndication ind)(SpikeHw);\n\n   let clock <- exposeCurrentClock();\n   let reset <- exposeCurrentReset();\n\n   let newReset <- mkReset(10, True, clock);\n\n   BUFRParams bufrParams = defaultValue;\n`ifndef BOARD_miniitx100\n   bufrParams.bufr_divide = \"2\";\n   Clock clk_125mhz <- mkClockBUFR(bufrParams, clocked_by clock);\n`endif\n   bufrParams.bufr_divide = \"4\";\n   Clock uartClk <- mkClockBUFR(bufrParams, clocked_by host.derivedClock);\n\n   let bootRom    <- mkBramBootRom();\n`ifdef IncludeFlash\n   let bpiFlash   <- mkBpiFlash();\n`endif\n   let axiIntcBvi <- mkAxiIntcBvi(clock, newReset.new_rst);\n   let axiIicBvi  <- mkAxiIicBvi(clock, newReset.new_rst);\n//   let axiSpiBvi  <- mkAxiSpiBvi(clock, clock, newReset.new_rst);\n   let axiUartBvi <- mkAxiUartBvi(clock, newReset.new_rst, uartClk);\n`ifdef IncludeEthernet\n//   let axiEthBvi <- mkAxiEthBvi(clock, host.tsys_clk_200mhz_buf, clock,\n//\t\t\t\tnewReset.new_rst, newReset.new_rst, newReset.new_rst, newReset.new_rst, newReset.new_rst);\n   let axiEthBvi <- AxiEthSubsystem::mkAxiEthBvi(clock, host.tsys_clk_200mhz_buf, reset_by newReset.new_rst);\n\n`endif\n\n   Reg#(Bit#(32)) objId <- mkReg(0);\n   Reg#(Bit#(1))  iicResetReg <- mkReg(0);\n   Reg#(Bit#(1))  eth_los <- mkReg(0);\n\n   let irqLevel <- mkReg(0);\n   let intrLevel <- mkReg(0);\n\n   function Bit#(16) intr();\n      Bit#(16) _intr = 0;\n      _intr[0] = axiUartBvi.ip2intc_irpt();\n      _intr[1] = axiEthBvi.s2mm_dma.introut(); // rx\n      _intr[2] = axiEthBvi.mm2s_dma.introut(); // tx\n`ifdef IncludeEthernet\n      _intr[3] = axiEthBvi.mac.irq();\n//      _intr[4] = axiEthBvi.interrupt();\n`endif\n      _intr[5] = axiIicBvi.iic2intc_irpt();\n//      _intr[6] = axiSpiBvi.ip2intc_irpt();\n      return _intr;\n   endfunction\n\n   rule rl_intr;\n\n      axiIntcBvi.intr(intr());\n   endrule\n\n   FIFOF#(Tuple2#(Bit#(1),Bit#(16))) irqChangeFifo <- mkSizedFIFOF(8);\n   rule rl_irq_levels_changed;\n      let irq = axiIntcBvi.irq;\n      let levels = intr();\n\n      if (irq != irqLevel) begin\n\t $display(\"irq changed irq=%h intr sources %h\", irq, levels);\n\t irqLevel <= irq;\n\t intrLevel <= levels;\n\t irqChangeFifo.enq(tuple2(irq, levels));\n      end\n   endrule\n\n   rule rl_intr_indication;\n      match { .irq, .levels } <- toGet(irqChangeFifo).get();\n      ind.irqChanged(irq, levels);\n   endrule\n\n   Reg#(Bit#(32)) cycles <- mkReg(0);\n   Reg#(Bool)     mmcm_lock <- mkReg(False);\n   rule rl_cycles;\n      cycles <= cycles+1;\n   endrule\n\n   FIFOF#(BRAMRequest#(Bit#(32),Bit#(32))) reqFifo <- mkSizedFIFOF(4);\n   FIFOF#(Bit#(32))                       dataFifo <- mkSizedFIFOF(16);\n\n   Axi4MasterBits#(32,DataBusWidth,MemTagSize,Empty) m_axi_mm2s = toAxi4MasterBits(axiEthBvi.m_axi_mm2s);\n   Axi4MasterBits#(32,DataBusWidth,MemTagSize,Empty) m_axi_s2mm = toAxi4MasterBits(axiEthBvi.m_axi_s2mm);\n   Axi4MasterBits#(32,DataBusWidth,MemTagSize,Empty) m_axi_sg = toAxi4MasterBits(axiEthBvi.m_axi_sg);\n\n   Axi4SlaveLiteBits#(12,32) axiUartSlaveLite = toAxi4SlaveBits(axiUartBvi.s_axi);\n   PhysMemSlave#(12,32) axiUartMemSlave      <- mkPhysMemSlave(axiUartSlaveLite);\n\n   Axi4SlaveLiteBits#(9,32) axiIntcSlaveLite = toAxi4SlaveBits(axiIntcBvi.s_axi);\n   PhysMemSlave#(12,32) axiIntcMemSlave      <- mkPhysMemSlave(axiIntcSlaveLite);\n\n   Axi4SlaveLiteBits#(9,32) axiIicSlaveLite  = toAxi4SlaveBits(axiIicBvi.s_axi);\n   PhysMemSlave#(12,32) axiIicMemSlave       <- mkPhysMemSlave(axiIicSlaveLite);\n\n//   Axi4SlaveLiteBits#(7,32) axiSpiSlaveLite  = toAxi4SlaveBits(axiSpiBvi.s_axi);\n//   PhysMemSlave#(12,32) axiSpiMemSlave       <- mkPhysMemSlave(axiSpiSlaveLite);\n\n`ifdef IncludeEthernet\n   PhysMemSlave#(12,32) axiDmaMemSlave       <- mkPhysMemSlave(axiEthBvi.s_axi_dma);\n\n   Axi4SlaveLiteBits#(12,32) axiEthSlaveLite = toAxi4SlaveBits(axiEthBvi.s_axi_mac);\n   PhysMemSlave#(12,32) axiEthMemSlave       <- mkPhysMemSlave(axiEthSlaveLite);\n   PhysMemSlave#(20,32) deviceSlaveMux       <- mkPhysMemSlaveMux(vec(axiUartMemSlave, axiIntcMemSlave, axiIicMemSlave,\n\t\t\t\t\t\t\t\t      axiDmaMemSlave, axiEthMemSlave)); // , axiSpiMemSlave\n`else\n   PhysMemSlave#(20,32) deviceSlaveMux       <- mkPhysMemSlaveMux(vec(axiUartMemSlave, axiIntcMemSlave, axiIicMemSlave));\n`endif\n\n   PhysMemSlave#(20,32) bootRomMemSlave      <- mkPhysMemSlaveFromBram(bootRom);\n   PhysMemSlave#(21,32) memSlaveMux          <- mkPhysMemSlaveMux(vec(bootRomMemSlave, deviceSlaveMux));\n\n   let memReadClients  <- mapM(mkMemReadClient(objId), vec(m_axi_mm2s, m_axi_sg));\n   let memWriteClients <- mapM(mkMemWriteClient(objId), vec(m_axi_s2mm, m_axi_sg));\n\n`ifdef IncludeFlash\n   PhysMemSlave#(26,16) bpiFlashSlave <- mkPhysMemSlaveFromBram(bpiFlash.server);\n`endif\n   FIFOF#(Bit#(32)) dfifo <- mkFIFOF();\n   FIFOF#(Bit#(32)) flashdfifo <- mkFIFOF();\n\n`ifdef IncludeEthernet\n   rule rl_axieth;\n      axiEthBvi.signal.detect(1); // drive to 1 if not using optical transceiver, else use signal from transceiver\n   endrule\n`endif\n\n   rule rl_rdata;\n      let rdata <- memSlaveMux.read_server.readData.get();\n      ind.readDone(rdata.data);\n   endrule\n\n   rule rl_wdata;\n      let wdata <- toGet(dfifo).get();\n       memSlaveMux.write_server.writeData.put(MemData {data: wdata, tag: 0, last: True});\n   endrule\n\n   rule rl_writeDone;\n      let tag <- memSlaveMux.write_server.writeDone.get();\n      ind.writeDone();\n   endrule\n\n   rule rl_bpiflash_rdata;\n`ifdef IncludeFlash\n      let rdata <- bpiFlashSlave.read_server.readData.get();\n      ind.readFlashDone(extend(rdata.data));\n`endif\n   endrule\n\n   rule rl_bpiflash_wdata;\n`ifdef IncludeFlash\n      let wdata <- toGet(flashdfifo).get();\n       bpiFlashSlave.write_server.writeData.put(MemData {data: truncate(wdata), tag: 0, last: True});\n`endif\n   endrule\n\n   rule rl_bpiflash_writeDone;\n`ifdef IncludeFlash\n      let tag <- bpiFlashSlave.write_server.writeDone.get();\n      ind.writeFlashDone();\n`endif\n   endrule\n\n`ifndef BOARD_miniitx100\n   DiffClock sfp_rec_clk_buf <- mkClockOBUFDS(defaultValue, clocked_by clk_125mhz);\n`endif\n   IOBUF sdaIOBuf <- mkIOBUF(axiIicBvi.sda.t, axiIicBvi.sda.o);\n   IOBUF sclIOBuf <- mkIOBUF(axiIicBvi.scl.t, axiIicBvi.scl.o);\n   // No probe for .o because they are tied to ground -- I2C operates open collector\n   Probe#(Bit#(1)) sda_i_probe <- mkProbe();\n   Probe#(Bit#(1)) sda_t_probe <- mkProbe();\n   Probe#(Bit#(1)) scl_i_probe <- mkProbe();\n   Probe#(Bit#(1)) scl_t_probe <- mkProbe();\n\n   rule iic_o;\n      sda_i_probe <= sdaIOBuf.o;\n      sda_t_probe <= axiIicBvi.sda.t;\n      scl_i_probe <= sclIOBuf.o;\n      scl_t_probe <= axiIicBvi.scl.t;\n\n      axiIicBvi.sda.i(sdaIOBuf.o);\n      axiIicBvi.scl.i(sclIOBuf.o);\n   endrule\n\n   // IOBUF spiSckIOBuf  <- mkIOBUF(axiSpiBvi.sck.t, axiSpiBvi.sck.o);\n   // IOBUF spiSsIOBuf   <- mkIOBUF(axiSpiBvi.ss.t, axiSpiBvi.ss.o);\n   // IOBUF spiMosiIOBuf <- mkIOBUF(axiSpiBvi.io0.t, axiSpiBvi.io0.o);\n   // IOBUF spiMisoIOBuf <- mkIOBUF(axiSpiBvi.io1.t, axiSpiBvi.io1.o);\n   // rule spi_o;\n   //    axiSpiBvi.sck.i(spiSckIOBuf.o);\n   //    axiSpiBvi.ss.i(spiSsIOBuf.o);\n   //    axiSpiBvi.io0.i(spiMosiIOBuf.o);\n   //    axiSpiBvi.io1.i(spiMisoIOBuf.o);\n   // endrule\n\n   // Probe#(Bit#(1)) spi_sck_i_probe <- mkProbe();\n   // Probe#(Bit#(1)) spi_sck_o_probe <- mkProbe();\n   // Probe#(Bit#(1)) spi_sck_t_probe <- mkProbe();\n   // Probe#(Bit#(1)) spi_ss_i_probe <- mkProbe();\n   // Probe#(Bit#(1)) spi_ss_o_probe <- mkProbe();\n   // Probe#(Bit#(1)) spi_ss_t_probe <- mkProbe();\n   // Probe#(Bit#(1)) spi_miso_i_probe <- mkProbe();\n   // Probe#(Bit#(1)) spi_miso_o_probe <- mkProbe();\n   // Probe#(Bit#(1)) spi_miso_t_probe <- mkProbe();\n   // Probe#(Bit#(1)) spi_mosi_i_probe <- mkProbe();\n   // Probe#(Bit#(1)) spi_mosi_o_probe <- mkProbe();\n   // Probe#(Bit#(1)) spi_mosi_t_probe <- mkProbe();\n   // rule rl_spi_trace;\n   //    spi_sck_i_probe <= spiSckIOBuf.o;\n   //    spi_sck_o_probe <= axiSpiBvi.sck.o;\n   //    spi_sck_t_probe <= axiSpiBvi.sck.t;\n   //    spi_ss_i_probe <= spiSsIOBuf.o;\n   //    spi_ss_o_probe <= axiSpiBvi.ss.o;\n   //    spi_ss_t_probe <= axiSpiBvi.ss.t;\n   //    spi_miso_i_probe <= spiMisoIOBuf.o;\n   //    spi_miso_o_probe <= axiSpiBvi.io1.o;\n   //    spi_miso_t_probe <= axiSpiBvi.io1.t;\n   //    spi_mosi_i_probe <= spiMosiIOBuf.o;\n   //    spi_mosi_o_probe <= axiSpiBvi.io0.o;\n   //    spi_mosi_t_probe <= axiSpiBvi.io0.t;\n   // endrule\n\n\n   FIFOF#(Tuple3#(DmaChannel,Bool,MemRequest)) traceFifo <- mkDualClockBramFIFOF(clock, reset, clock, reset);\n   FIFOF#(Tuple3#(DmaChannel,Bool,MemRequest)) traceFifo0 <- mkFIFOF();\n   FIFOF#(Tuple3#(DmaChannel,Bool,MemRequest)) traceFifo1 <- mkFIFOF();\n   PipeIn#(Tuple3#(DmaChannel,Bool,MemRequest)) tracePipe = toPipeIn(traceFifo0);\n   FIFOF#(Tuple3#(DmaChannel,Bool,MemData#(DataBusWidth))) traceDataFifo <- mkDualClockBramFIFOF(clock, reset, clock, reset);\n   FIFOF#(Tuple3#(DmaChannel,Bool,MemData#(DataBusWidth))) traceDataFifo0 <- mkFIFOF();\n   FIFOF#(Tuple3#(DmaChannel,Bool,MemData#(DataBusWidth))) traceDataFifo1 <- mkFIFOF();\n   PipeIn#(Tuple3#(DmaChannel,Bool,MemData#(DataBusWidth))) traceDataPipe = toPipeIn(traceDataFifo0);\n   let trace0Cnx <- mkConnection(toGet(traceFifo0), toPut(traceFifo));\n   let trace1Cnx <- mkConnection(toGet(traceFifo), toPut(traceFifo1));\n   rule rl_trace1;\n      match { .chan, .write, .req } <- toGet(traceFifo1).get();\n      ind.traceDmaRequest(chan, write, truncate(req.sglId), truncate(req.offset), extend(req.burstLen));\n   endrule\n   let traceData0Cnx <- mkConnection(toGet(traceDataFifo0), toPut(traceDataFifo));\n   let traceData1Cnx <- mkConnection(toGet(traceDataFifo), toPut(traceDataFifo1));\n   rule rl_trace_data;\n      match { .chan, .write, .md } <- toGet(traceDataFifo1).get();\n      ind.traceDmaData(chan, write, md.data, md.last);\n   endrule\n\n   let traceReadClients <- mapM(uncurry(mkTraceReadClient(tracePipe,traceDataPipe)),\n\t\t\t\tzip(vec(DMA_TX, DMA_SG),\n\t\t\t\t    memReadClients));\n   let traceWriteClients <- mapM(uncurry(mkTraceWriteClient(tracePipe,traceDataPipe)),\n\t\t\t\t zip(vec(DMA_RX, DMA_SG),\n\t\t\t\t     memWriteClients));\n\n   interface SpikeHwRequest request;\n      method Action reset();\n\t newReset.assertReset();\n      endmethod\n      method Action setupDma(Bit#(32) memref);\n\t objId <= memref;\n      endmethod\n      method Action read(Bit#(32) addr);\n\t memSlaveMux.read_server.readReq.put(PhysMemRequest { addr: truncate(addr), burstLen: 4, tag: 0 });\n      endmethod\n      method Action write(Bit#(32) addr, Bit#(32) value);\n\t memSlaveMux.write_server.writeReq.put(PhysMemRequest { addr: truncate(addr), burstLen: 4, tag: 0 });\n\t dfifo.enq(value);\n      endmethod\n      method Action setFlashParameters(Bit#(16) cycles);\n`ifdef IncludeFlash\n\t bpiFlash.setParameters(cycles, False);\n`endif\n      endmethod\n      method Action readFlash(Bit#(32) addr);\n`ifdef IncludeFlash\n\t bpiFlashSlave.read_server.readReq.put(PhysMemRequest { addr: truncate(addr), burstLen: 2, tag: 0 });\n`endif\n      endmethod\n      method Action writeFlash(Bit#(32) addr, Bit#(32) value);\n`ifdef IncludeFlash\n\t bpiFlashSlave.write_server.writeReq.put(PhysMemRequest { addr: truncate(addr), burstLen: 2, tag: 0 });\n\t flashdfifo.enq(value);\n`endif\n      endmethod\n      method Action status();\n\t ind.status(\n\t\t    pack(newReset.isAsserted),\n`ifdef IncludeEthernet\n\t\t    axiEthBvi.mmcm.locked_out(), eth_los,\n`else\n\t\t    0, eth_los,\n`endif\n\n\t    axiIntcBvi.irq, intr());\n      endmethod\n      method Action iicReset(Bit#(1) rst);\n\t iicResetReg <= rst;\n      endmethod\n   endinterface\n   interface SpikeHwPins pins;\n`ifdef IncludeEthernet\n      interface EthPins eth;\n\t interface AxiethbviMgt mgt   = axiEthBvi.mgt;\n`ifdef EthernetSgmii\n\t interface AxiethbviSgmii sgmii = axiEthBvi.sgmii;\n`else\n\t interface AxiethbviSfp sfp = axiEthBvi.sfp;\n`endif\n         method Bit#(1) tx_disable();\n\t    return 0;\n\t endmethod\n         method Action rx_los(Bit#(1) v);\n            eth_los <= v;\n\t endmethod\n      endinterface\n`else\n      interface EthPins eth;\n         method Bit#(1) tx_disable();\n\t    return 0;\n\t endmethod\n         method Action rx_los(Bit#(1) v);\n            eth_los <= v;\n\t endmethod\n      endinterface\n`endif\n`ifdef IncludeFlash\n      interface flash = bpiFlash.flash;\n`endif\n      interface SpikeUartPins uart;\n`ifndef BOARD_miniitx100\n\t method tx  = axiUartBvi.sout;\n\t method rx  = axiUartBvi.sin;\n`endif\n`ifdef UART_HAX_RTS_CTS\n\t method rts = axiUartBvi.rtsn;\n\t method cts = axiUartBvi.ctsn;\n`endif\n      endinterface   \n      interface SpikeIicPins iic;\n         interface scl = sclIOBuf.io;\n         interface sda = sdaIOBuf.io;\n\t method mux_reset = iicResetReg;\n      endinterface\n      // interface SpikeSpiPins spi;\n      //    interface sck  = spiSckIOBuf.io;\n      //    interface ss   = spiSsIOBuf.io;\n      //    interface miso = spiMisoIOBuf.io;\n      //    interface mosi = spiMosiIOBuf.io;\n      // endinterface\n      interface Clock deleteme_unused_clock = clock;\n      interface Reset deleteme_unused_reset = reset;\n`ifndef BOARD_miniitx100\n      interface Clock sfp_rec_clk_p = sfp_rec_clk_buf.p;\n      interface Clock sfp_rec_clk_n = sfp_rec_clk_buf.n;\n`endif\n   endinterface\n\n   interface Vector dmaReadClient = traceReadClients;\n   interface Vector dmaWriteClient = traceWriteClients;\nendmodule\n"
  },
  {
    "path": "tests/spikehw/SpikeHwIfc.bsv",
    "content": "\nimport BuildVector::*;\nimport Clocks::*;\nimport Connectable::*;\nimport GetPut::*;\nimport FIFOF::*;\nimport BRAM::*;\nimport Probe::*;\nimport StmtFSM::*;\nimport TriState::*;\nimport Vector::*;\nimport XilinxCells::*;\nimport Probe::*;\n\nimport ConnectalXilinxCells::*;\nimport ConnectalConfig::*;\nimport CtrlMux::*;\nimport HostInterface::*;\nimport ConnectalMemTypes::*;\nimport Pipe::*;\nimport AxiBits::*;\nimport PhysMemSlaveFromBram::*;\n\nimport BpiFlash::*;\nimport AxiIntcBvi::*;\nimport AxiIic::*;\nimport AxiUart::*;\n`ifdef EthernetSgmii\nimport AxiEthBvi::*;\n`else\nimport AxiEth1000BaseX::*;\n`endif\nimport AxiDmaBvi::*;\nimport SpikeHwPins::*;\n\n`include \"ConnectalProjectConfig.bsv\"\n\ntypedef enum { DMA_RX, DMA_TX, DMA_SG } DmaChannel deriving (Bits,Eq);\n\ninterface SpikeHwRequest;\n   method Action reset();\n   method Action setupDma(Bit#(32) memref);\n   method Action status();\n   method Action read(Bit#(32) addr);\n   method Action write(Bit#(32) addr, Bit#(32) value);\n   method Action setFlashParameters(Bit#(16) cycles);\n   method Action readFlash(Bit#(32) addr);\n   method Action writeFlash(Bit#(32) addr, Bit#(32) value);\n   method Action iicReset(Bit#(1) rst);\nendinterface\n\ninterface SpikeHwIndication;\n   method Action irqChanged(Bit#(1) newIrq, Bit#(16) intrSources);\n   method Action readDone(Bit#(32) value); \n   method Action writeDone(); \n   method Action readFlashDone(Bit#(32) value); \n   method Action writeFlashDone(); \n   method Action resetDone();\n   method Action status(Bit#(1) reset_asserted, Bit#(1) mmcm_locked, Bit#(1) rx_los, Bit#(1) irq, Bit#(16) intrSources);\n   method Action traceDmaRequest(DmaChannel channel, Bool write, Bit#(16) objId, Bit#(32) offset, Bit#(16) burstLen);\n   method Action traceDmaData(DmaChannel channel, Bool write, Bit#(32) data, Bool last);\nendinterface\n"
  },
  {
    "path": "tests/spikehw/SpikeHwPins.bsv",
    "content": "\n`ifdef EthernetSgmii\nimport AxiEthBvi::*;\n`else\nimport AxiEth1000BaseX::*;\n`endif\nimport BpiFlash::*;\n\n`include \"ConnectalProjectConfig.bsv\"\n\ninterface EthPins;\n`ifdef IncludeEthernet\n`ifdef EthernetSgmii\n   interface AxiethbviSgmii sgmii;\n`else\n   interface AxiethbviSfp sfp;\n`endif\n   interface AxiethbviMgt mgt;\n`endif\n   method Bit#(1) tx_disable();\n   method Action rx_los(Bit#(1) v);\nendinterface\n\n(* always_ready, always_enabled *)\ninterface SpikeIicPins;\n   interface Inout#(Bit#(1)) scl;\n   interface Inout#(Bit#(1)) sda;\n   method Bit#(1) mux_reset();\nendinterface\n\n(* always_ready, always_enabled *)\ninterface SpikeSpiPins;\n   interface Inout#(Bit#(1)) miso;\n   interface Inout#(Bit#(1)) mosi;\n   interface Inout#(Bit#(1)) sck;\n   interface Inout#(Bit#(1)) ss;\nendinterface\n\n(* always_ready, always_enabled *)\ninterface SpikeUartPins;\n`ifndef BOARD_miniitx100\n   method Bit#(1) tx;\n   method Action  rx (Bit#(1) x);\n`endif\n`ifdef UART_HAX_RTS_CTS\n   method Bit#(1) rts;\n   method Action  cts(Bit#(1) x);\n`endif\nendinterface\n\n(* always_ready, always_enabled *)\ninterface SpikeHwPins;\n   interface EthPins eth;\n   interface SpikeUartPins uart;\n   interface SpikeIicPins iic;\n   interface SpikeSpiPins spi;\n`ifdef IncludeFlash\n   interface BpiFlashPins flash;\n`endif\n   interface Clock deleteme_unused_clock;\n   interface Reset deleteme_unused_reset;\n`ifndef BOARD_miniitx100\n   interface Clock sfp_rec_clk_p;\n   interface Clock sfp_rec_clk_n;\n`endif\nendinterface\n"
  },
  {
    "path": "tests/spikehw/SyncAxisFifo32x1024.bsv",
    "content": "\n/*\n   ../../generated/scripts/importbvi.py\n   -I\n   SyncAxisFifo32x1024\n   -P\n   SyncAxisFifo32x1024\n   -c\n   m_aclk\n   -c\n   s_aclk\n   -r\n   s_aresetn\n   -o\n   SyncAxisFifo32x1024.bsv\n   cores/nfsume/dual_clock_axis_fifo_32x1024/dual_clock_axis_fifo_32x1024_stub.v\n*/\n\nimport Clocks::*;\nimport ConnectalFIFO::*;\nimport DefaultValue::*;\nimport FIFOF::*;\nimport XilinxCells::*;\nimport GetPut::*;\nimport AxiBits::*;\nimport AxiStream::*;\n\n(* always_ready, always_enabled *)\n(* always_ready, always_enabled *)\ninterface Syncaxisfifo32x1024M_axis;\n    method Bit#(32)     tdata();\n    method Bit#(4)     tkeep();\n    method Bit#(1)     tlast();\n    method Action      tready(Bit#(1) v);\n    method Bit#(1)     tvalid();\nendinterface\n(* always_ready, always_enabled *)\n(* always_ready, always_enabled *)\ninterface Syncaxisfifo32x1024S_axis;\n    method Action      tdata(Bit#(32) v);\n    method Action      tkeep(Bit#(4) v);\n    method Action      tlast(Bit#(1) v);\n    method Bit#(1)     tready();\n    method Action      tvalid(Bit#(1) v);\nendinterface\n(* always_ready, always_enabled *)\ninterface SyncAxisFifo32x1024;\n    interface AxiStreamMaster#(32) m_axis;\n    interface AxiStreamSlave#(32)  s_axis;\nendinterface\nimport \"BVI\" dual_clock_axis_fifo_32x1024 =\nmodule mkSyncAxisFifo32x1024#(Clock s_aclk, Reset s_aresetn, Clock m_aclk, Reset m_aresetn)(SyncAxisFifo32x1024);\n    default_clock clk();\n    default_reset rst();\n        input_clock m_aclk(m_aclk) = m_aclk;\n        input_clock s_aclk(s_aclk) = s_aclk;\n        input_reset s_aresetn(s_aresetn) clocked_by (s_aclk) = s_aresetn;\n        input_reset m_aresetn_foo() clocked_by (m_aclk) = m_aresetn;\n    interface AxiStreamMaster     m_axis;\n        method m_axis_tdata tdata() clocked_by (m_aclk) reset_by (m_aresetn_foo);\n        method m_axis_tkeep tkeep() clocked_by (m_aclk) reset_by (m_aresetn_foo);\n        method m_axis_tlast tlast() clocked_by (m_aclk) reset_by (m_aresetn_foo);\n        method tready(m_axis_tready) enable((*inhigh*) EN_m_axis_tready) clocked_by (m_aclk) reset_by (m_aresetn_foo);\n        method m_axis_tvalid tvalid() clocked_by (m_aclk) reset_by (m_aresetn_foo);\n    endinterface\n    interface AxiStreamSlave     s_axis;\n        method tdata(s_axis_tdata) enable((*inhigh*) EN_s_axis_tdata) clocked_by (s_aclk) reset_by (s_aresetn);\n        method tkeep(s_axis_tkeep) enable((*inhigh*) EN_s_axis_tkeep) clocked_by (s_aclk) reset_by (s_aresetn);\n        method tlast(s_axis_tlast) enable((*inhigh*) EN_s_axis_tlast) clocked_by (s_aclk) reset_by (s_aresetn);\n        method s_axis_tready tready() clocked_by (s_aclk) reset_by (s_aresetn);\n        method tvalid(s_axis_tvalid) enable((*inhigh*) EN_s_axis_tvalid) clocked_by (s_aclk) reset_by (s_aresetn);\n    endinterface\n    schedule (m_axis.tdata, m_axis.tkeep, m_axis.tlast, m_axis.tready, m_axis.tvalid, s_axis.tdata, s_axis.tkeep, s_axis.tlast, s_axis.tready, s_axis.tvalid) CF (m_axis.tdata, m_axis.tkeep, m_axis.tlast, m_axis.tready, m_axis.tvalid, s_axis.tdata, s_axis.tkeep, s_axis.tlast, s_axis.tready, s_axis.tvalid);\nendmodule\n\nmodule mkSyncAxisFifo32x1024FIFOF#(Clock fromClock, Reset fromReset, Clock toClock, Reset toReset)(FIFOF#(a)) provisos (Bits#(a, asz), Add#(asz, a__, 32));\n   let fromFIFOF <- mkCFFIFOF(clocked_by fromClock, reset_by fromReset);\n   let syncFIFOF <- mkSyncAxisFifo32x1024(fromClock, fromReset, toClock, toReset);\n   let   toFIFOF <- mkCFFIFOF(clocked_by toClock, reset_by toReset);\n\n   rule rl_from if (syncFIFOF.s_axis.tready() == 1);\n      syncFIFOF.s_axis.tdata(extend(pack(fromFIFOF.first())));\n      fromFIFOF.deq();\n   endrule\n   rule rl_from_handshake;\n      syncFIFOF.s_axis.tvalid(pack(fromFIFOF.notEmpty()));\n      syncFIFOF.s_axis.tkeep(maxBound);\n      syncFIFOF.s_axis.tlast(1);\n   endrule\n\n   rule rl_to if (syncFIFOF.m_axis.tvalid() == 1);\n      toFIFOF.enq(unpack(truncate(syncFIFOF.m_axis.tdata)));\n   endrule\n   rule rl_to_handshake;\n      syncFIFOF.m_axis.tready(pack(toFIFOF.notFull()));\n   endrule\n\n   method notEmpty = toFIFOF.notEmpty;\n   method first    = toFIFOF.first;\n   method deq      = toFIFOF.deq;\n   method enq      = fromFIFOF.enq;\n   method notFull  = fromFIFOF.notFull;\nendmodule\n   \n"
  },
  {
    "path": "tests/spikehw/TriModeMacBvi.bsv",
    "content": "\n/*\n   /home/jamey/connectal.clean/generated/scripts/importbvi.py\n   -o\n   TriModeMacBvi.bsv\n   -P\n   TriModeMac\n   -I\n   TriModeMacBvi\n   -c\n   gtx_clk\n   -r\n   glbl_rstn\n   -r\n   rx_axi_rstn\n   -r\n   tx_axi_rstn\n   -c\n   rx_mac_aclk\n   -r\n   rx_reset\n   -c\n   tx_mac_aclk\n   -r\n   tx_reset\n   -c\n   s_axi_aclk\n   -r\n   s_axi_resetn\n   -f\n   rx_axis_mac\n   -f\n   tx_axis_mac\n   -n\n   speedis100\n   -n\n   speedis10100\n   cores/nfsume/tri_mode_ethernet_mac_0/tri_mode_ethernet_mac_0_stub.v\n*/\n\n`include \"ConnectalProjectConfig.bsv\"\nimport Clocks::*;\nimport DefaultValue::*;\nimport XilinxCells::*;\nimport GetPut::*;\nimport AxiBits::*;\nimport AxiStream::*;\n\n(* always_ready, always_enabled *)\ninterface TrimodemacGmii;\n    method Action      rx_dv(Bit#(1) v);\n    method Action      rx_er(Bit#(1) v);\n    method Action      rxd(Bit#(8) v);\n    method Bit#(1)     tx_en();\n    method Bit#(1)     tx_er();\n    method Bit#(8)     txd();\nendinterface\n(* always_ready, always_enabled *)\n(* always_ready, always_enabled *)\ninterface TrimodemacMac;\n    method Bit#(1)     irq();\nendinterface\n(* always_ready, always_enabled *)\ninterface TrimodemacMdio;\n    method Action      i(Bit#(1) v);\n    method Bit#(1)     o();\n    method Bit#(1)     t();\nendinterface\n(* always_ready, always_enabled *)\ninterface TrimodemacPause;\n    method Action      req(Bit#(1) v);\n    method Action      val(Bit#(16) v);\nendinterface\n(* always_ready, always_enabled *)\ninterface TrimodemacRx;\n    method Bit#(5)     axis_filter_tuser();\n    interface Clock     mac_aclk;\n    method Reset     reset();\n    method Bit#(1)     statistics_valid();\n    method Bit#(28)     statistics_vector();\nendinterface\n(* always_ready, always_enabled *)\ninterface TrimodemacRx_axis_mac;\n    method Bit#(8)     tdata();\n    method Bit#(1)     tlast();\n    method Bit#(1)     tuser();\n    method Bit#(1)     tvalid();\nendinterface\n(* always_ready, always_enabled *)\ninterface TrimodemacS_axi;\n    method Action      araddr(Bit#(12) v);\n    method Bit#(1)     arready();\n    method Action      arvalid(Bit#(1) v);\n    method Action      awaddr(Bit#(12) v);\n    method Bit#(1)     awready();\n    method Action      awvalid(Bit#(1) v);\n    method Action      bready(Bit#(1) v);\n    method Bit#(2)     bresp();\n    method Bit#(1)     bvalid();\n    method Bit#(32)     rdata();\n    method Action      rready(Bit#(1) v);\n    method Bit#(2)     rresp();\n    method Bit#(1)     rvalid();\n    method Action      wdata(Bit#(32) v);\n    method Bit#(1)     wready();\n    method Action      wvalid(Bit#(1) v);\nendinterface\n(* always_ready, always_enabled *)\ninterface TrimodemacTx;\n    method Action      ifg_delay(Bit#(8) v);\n    interface Clock     mac_aclk;\n    method Reset     reset();\n    method Bit#(1)     statistics_valid();\n    method Bit#(32)     statistics_vector();\nendinterface\n(* always_ready, always_enabled *)\ninterface TrimodemacTx_axis_mac;\n    method Action      tdata(Bit#(8) v);\n    method Action      tlast(Bit#(1) v);\n    method Bit#(1)     tready();\n    method Action      tuser(Bit#(1) v);\n    method Action      tvalid(Bit#(1) v);\nendinterface\n(* always_ready, always_enabled *)\ninterface TriModeMac;\n    interface TrimodemacGmii     gmii;\n    interface TrimodemacMac     mac;\n    method Bit#(1)     mdc();\n    interface TrimodemacMdio     mdio;\n    interface TrimodemacPause     pause;\n    interface TrimodemacRx     rx;\n    interface TrimodemacRx_axis_mac    rx_axis_mac;\n    interface TrimodemacS_axi     s_axi;\n    method Bit#(1)     speedis100();\n    method Bit#(1)     speedis10100();\n    interface TrimodemacTx     tx;\n    interface TrimodemacTx_axis_mac     tx_axis_mac;\nendinterface\nimport \"BVI\" tri_mode_ethernet_mac_0 =\nmodule mkTriModeMacBvi#(Clock gtx_clk, Clock s_axi_aclk, Reset glbl_rstn, Reset rx_axi_rstn, Reset s_axi_resetn, Reset tx_axi_rstn)(TriModeMac);\n    default_clock clk();\n    default_reset rst();\n        input_reset glbl_rstn(glbl_rstn) = glbl_rstn;\n        input_clock gtx_clk(gtx_clk) = gtx_clk;\n        input_reset rx_axi_rstn(rx_axi_rstn) = rx_axi_rstn;\n        input_clock s_axi_aclk(s_axi_aclk) = s_axi_aclk;\n        input_reset s_axi_resetn(s_axi_resetn) = s_axi_resetn;\n        input_reset tx_axi_rstn(tx_axi_rstn) = tx_axi_rstn;\n    interface TrimodemacGmii     gmii;\n        method rx_dv(gmii_rx_dv) enable((*inhigh*) EN_gmii_rx_dv);\n        method rx_er(gmii_rx_er) enable((*inhigh*) EN_gmii_rx_er);\n        method rxd(gmii_rxd) enable((*inhigh*) EN_gmii_rxd);\n        method gmii_tx_en tx_en();\n        method gmii_tx_er tx_er();\n        method gmii_txd txd();\n    endinterface\n    interface TrimodemacMac     mac;\n        method mac_irq irq() clocked_by (s_axi_aclk) reset_by (s_axi_resetn);\n    endinterface\n    method mdc mdc();\n    interface TrimodemacMdio     mdio;\n        method i(mdio_i) enable((*inhigh*) EN_mdio_i);\n        method mdio_o o();\n        method mdio_t t();\n    endinterface\n    interface TrimodemacRx     rx;\n        output_clock mac_aclk(rx_mac_aclk);\n        output_reset reset(rx_reset) clocked_by (rx_mac_aclk);\n        method rx_axis_filter_tuser axis_filter_tuser() clocked_by (rx_mac_aclk) reset_by (rx_reset);\n        method rx_statistics_valid statistics_valid() clocked_by (rx_mac_aclk) reset_by (rx_reset);\n        method rx_statistics_vector statistics_vector() clocked_by (rx_mac_aclk) reset_by (rx_reset);\n    endinterface\n    interface TrimodemacRx_axis_mac rx_axis_mac;\n       method rx_axis_mac_tdata tdata() clocked_by (rx_mac_aclk) reset_by (rx_reset);\n       method rx_axis_mac_tlast tlast() clocked_by (rx_mac_aclk) reset_by (rx_reset);\n       method rx_axis_mac_tuser tuser() clocked_by (rx_mac_aclk) reset_by (rx_reset);\n       method rx_axis_mac_tvalid tvalid() clocked_by (rx_mac_aclk) reset_by (rx_reset);\n    endinterface\n    interface TrimodemacS_axi     s_axi;\n        method araddr(s_axi_araddr) clocked_by (s_axi_aclk) reset_by (s_axi_resetn) enable((*inhigh*) EN_s_axi_araddr);\n        method s_axi_arready arready() clocked_by (s_axi_aclk) reset_by (s_axi_resetn);\n        method arvalid(s_axi_arvalid) clocked_by (s_axi_aclk) reset_by (s_axi_resetn) enable((*inhigh*) EN_s_axi_arvalid);\n        method awaddr(s_axi_awaddr) clocked_by (s_axi_aclk) reset_by (s_axi_resetn) enable((*inhigh*) EN_s_axi_awaddr);\n        method s_axi_awready awready() clocked_by (s_axi_aclk) reset_by (s_axi_resetn);\n        method awvalid(s_axi_awvalid) clocked_by (s_axi_aclk) reset_by (s_axi_resetn) enable((*inhigh*) EN_s_axi_awvalid);\n        method bready(s_axi_bready) clocked_by (s_axi_aclk) reset_by (s_axi_resetn) enable((*inhigh*) EN_s_axi_bready);\n        method s_axi_bresp bresp() clocked_by (s_axi_aclk) reset_by (s_axi_resetn);\n        method s_axi_bvalid bvalid() clocked_by (s_axi_aclk) reset_by (s_axi_resetn);\n        method s_axi_rdata rdata() clocked_by (s_axi_aclk) reset_by (s_axi_resetn);\n        method rready(s_axi_rready) clocked_by (s_axi_aclk) reset_by (s_axi_resetn) enable((*inhigh*) EN_s_axi_rready);\n        method s_axi_rresp rresp() clocked_by (s_axi_aclk) reset_by (s_axi_resetn);\n        method s_axi_rvalid rvalid() clocked_by (s_axi_aclk) reset_by (s_axi_resetn);\n        method wdata(s_axi_wdata) clocked_by (s_axi_aclk) reset_by (s_axi_resetn) enable((*inhigh*) EN_s_axi_wdata);\n        method s_axi_wready wready() clocked_by (s_axi_aclk) reset_by (s_axi_resetn);\n        method wvalid(s_axi_wvalid) clocked_by (s_axi_aclk) reset_by (s_axi_resetn) enable((*inhigh*) EN_s_axi_wvalid);\n    endinterface\n    method speedis100 speedis100();\n    method speedis10100 speedis10100();\n    interface TrimodemacTx     tx;\n        output_clock mac_aclk(tx_mac_aclk);\n        output_reset reset(tx_reset) clocked_by (tx_mac_aclk);\n        method ifg_delay(tx_ifg_delay) enable((*inhigh*) EN_tx_ifg_delay) clocked_by (tx_mac_aclk) reset_by (tx_reset);\n        method tx_statistics_valid statistics_valid() clocked_by (tx_mac_aclk) reset_by (tx_reset);\n        method tx_statistics_vector statistics_vector() clocked_by (tx_mac_aclk) reset_by (tx_reset);\n    endinterface\n    interface TrimodemacTx_axis_mac     tx_axis_mac;\n        method tdata(tx_axis_mac_tdata) enable((*inhigh*) EN_tx_axis_mac_tdata) clocked_by (tx_mac_aclk) reset_by (tx_reset);\n        method tlast(tx_axis_mac_tlast) enable((*inhigh*) EN_tx_axis_mac_tlast) clocked_by (tx_mac_aclk) reset_by (tx_reset);\n        method tx_axis_mac_tready tready() clocked_by (tx_mac_aclk) reset_by (tx_reset);\n        method tuser(tx_axis_mac_tuser) enable((*inhigh*) EN_tx_axis_mac_tuser) clocked_by (tx_mac_aclk) reset_by (tx_reset);\n        method tvalid(tx_axis_mac_tvalid) enable((*inhigh*) EN_tx_axis_mac_tvalid) clocked_by (tx_mac_aclk) reset_by (tx_reset);\n    endinterface\n    interface TrimodemacPause     pause;\n        method req(pause_req) enable((*inhigh*) EN_pause_req) clocked_by (tx_mac_aclk) reset_by (tx_reset);\n        method val(pause_val) enable((*inhigh*) EN_pause_val) clocked_by (tx_mac_aclk) reset_by (tx_reset);\n    endinterface\n    schedule (gmii.rx_dv, gmii.rx_er, gmii.rxd, gmii.tx_en, gmii.tx_er, gmii.txd, mac.irq, mdc, mdio.i, mdio.o, mdio.t, pause.req, pause.val, rx.axis_filter_tuser, rx.statistics_valid, rx.statistics_vector, rx_axis_mac.tdata, rx_axis_mac.tlast, rx_axis_mac.tuser, rx_axis_mac.tvalid, s_axi.araddr, s_axi.arready, s_axi.arvalid, s_axi.awaddr, s_axi.awready, s_axi.awvalid, s_axi.bready, s_axi.bresp, s_axi.bvalid, s_axi.rdata, s_axi.rready, s_axi.rresp, s_axi.rvalid, s_axi.wdata, s_axi.wready, s_axi.wvalid, speedis100, speedis10100, tx.ifg_delay, tx.statistics_valid, tx.statistics_vector, tx_axis_mac.tdata, tx_axis_mac.tlast, tx_axis_mac.tready, tx_axis_mac.tuser, tx_axis_mac.tvalid) CF (gmii.rx_dv, gmii.rx_er, gmii.rxd, gmii.tx_en, gmii.tx_er, gmii.txd, mac.irq, mdc, mdio.i, mdio.o, mdio.t, pause.req, pause.val, rx.axis_filter_tuser, rx.statistics_valid, rx.statistics_vector, rx_axis_mac.tdata, rx_axis_mac.tlast, rx_axis_mac.tuser, rx_axis_mac.tvalid, s_axi.araddr, s_axi.arready, s_axi.arvalid, s_axi.awaddr, s_axi.awready, s_axi.awvalid, s_axi.bready, s_axi.bresp, s_axi.bvalid, s_axi.rdata, s_axi.rready, s_axi.rresp, s_axi.rvalid, s_axi.wdata, s_axi.wready, s_axi.wvalid, speedis100, speedis10100, tx.ifg_delay, tx.statistics_valid, tx.statistics_vector, tx_axis_mac.tdata, tx_axis_mac.tlast, tx_axis_mac.tready, tx_axis_mac.tuser, tx_axis_mac.tvalid);\nendmodule\n\n`ifdef FLUTE\nimport TLM3         :: *;\nimport Axi4         :: *;\nimport AxiDefines   ::*;\n\ninstance ToAxi4LRdWrSlave#(TrimodemacS_axi);\n   function Axi4LRdWrSlave#(`SoC_PRM) toAxi4LRdWrSlave(TrimodemacS_axi s);\n      return (interface Axi4LRdWrSlave#(`SoC_PRM);\n         interface Axi4LRdSlave read;\n\t    method Action arADDR(AxiAddr#(`SoC_PRM) addr); s.araddr(truncate(addr)); endmethod\n\t    method arREADY = unpack(s.arready());\n\t    method Action arVALID(Bool v); s.arvalid(pack(v)); endmethod\n\t     method rDATA = extend(s.rdata);\n\t     method Action rREADY(Bool r); s.rready(pack(r)); endmethod\n\t     method rRESP = unpack(s.rresp);\n\t     method rVALID = unpack(s.rvalid);\n\t endinterface: read\n         interface Axi4LWrSlave write;\n\t     method Action awADDR(AxiAddr#(`SoC_PRM) addr); s.awaddr(truncate(addr)); endmethod\n\t     method awREADY = unpack(s.awready);\n\t     method Action awVALID(Bool v); s.awvalid(pack(v)); endmethod\n\t     method Action bREADY(Bool r); s.bready(pack(r)); endmethod\n\t     method bRESP = unpack(s.bresp);\n\t     method bVALID = unpack(s.bvalid);\n\t     method Action wDATA(AxiData#(`SoC_PRM) d); s.wdata(truncate(d)); endmethod\n\t     method wREADY = unpack(s.wready);\n\t     method Action wVALID(Bool v); s.wvalid(pack(v)); endmethod\n\t endinterface: write\n\t endinterface);\n   endfunction\nendinstance\n\ninterface TriModeMacMac;\n    method Bit#(1)     mdc();\n   interface TrimodemacMdio          mdio;\n   interface TrimodemacGmii          gmii;\n   interface Server #(SoC_Req, SoC_Rsp) bus_ifc;\n   interface TrimodemacTx            s_axis_tx;\n   interface TrimodemacRx            m_axis_rx;\n   interface Clock     mm2s_aclk;\n   interface Clock     s2mm_aclk;\n   method Bit#(1) interrupt();\nendinterface\n\n(* synthesize *)\nmodule mkTriModeMacMac#(Clock gtx_clock)(TriModeMacMac);\n   let clock <- exposeCurrentClock;\n   let reset <- exposeCurrentReset;\n\n   let gtx_reset = reset;\n\n   let axiEth <- mkTriModeMacBvi(gtx_clock, clock, reset, reset, reset, reset);\n   Axi4LRdWrSlave#(`SoC_PRM) axiRdWrSlave = toAxi4LRdWrSlave(axiEth.s_axi);\n   let tlmRecv <- mkTLMRecvFromAxi4LSlave(axiRdWrSlave);\n\n   method    mdc     = axiEth.mdc;\n   interface mdio    = axiEth.mdio;\n   interface bus_ifc = tlmRecv;\n   interface gmii    = axiEth.gmii;\n   method interrupt  = axiEth.mac.irq;\n   interface s_axis_tx = axiEth.tx;\n   interface m_axis_rx = axiEth.rx;\n   interface mm2s_aclk = axiEth.rx.mac_aclk;\n   interface s2mm_aclk = axiEth.tx.mac_aclk;\nendmodule\n`endif //FLUTE\n\ninstance ToAxi4SlaveBits#(Axi4SlaveLiteBits#(12,32), TrimodemacS_axi);\n   function Axi4SlaveLiteBits#(12,32) toAxi4SlaveBits(TrimodemacS_axi s);\n      return (interface Axi4SlaveLiteBits#(12,32);\n\t method araddr = compose(s.araddr, extend);\n\t method arready = s.arready;\n\t method arvalid = s.arvalid;\n\t method awaddr = compose(s.awaddr, extend);\n\t method awready = s.awready;\n\t method awvalid = s.awvalid;\n\t method bready = s.bready;\n\t method bresp = s.bresp;\n\t method bvalid = s.bvalid;\n\t method rdata = s.rdata;\n\t method rready = s.rready;\n\t method rresp = s.rresp;\n\t method rvalid = s.rvalid;\n\t method wdata = s.wdata;\n\t method wready = s.wready;\n\t method Action      wvalid(Bit#(1) v);\n\t    s.wvalid(v);\n\t    //s.wstrb(pack(replicate(v)));\n\t endmethod\n\t endinterface);\n   endfunction\nendinstance\n"
  },
  {
    "path": "tests/spikehw/boot/Makefile",
    "content": "\nall: bootrom.bin bootrom.hex bootromx4.hex\n\nclean:\n\trm -f *.o *.elf *.bin *.hex\n\nentry.o: entry.S\n\triscv64-unknown-elf-gcc -O -c entry.S\n\triscv64-unknown-elf-objdump -d -S entry.o > entry.dump\n\ncopybbl.o: copybbl.c\n\triscv64-unknown-elf-gcc -O -c copybbl.c\n\ncopybbl.elf: entry.o copybbl.o bbl.o vmlinux.o Makefile\n\triscv64-unknown-elf-ld -o copybbl.elf -Ttext 0x0000000 -Tdata 400 --entry=0000000 entry.o copybbl.o bbl.o\n\triscv64-unknown-elf-objdump -D copybbl.elf | head -1000 > copybbl.dump\n\nbootrom.hex: copybbl.elf\n\trm -f copybbl.hex\n\t#elf2hex 8 1048576 copybbl.elf > bootrom.hex\n\telf2hex 8 524288 copybbl.elf > bootrom.hex\n\t#elf2hex 8 16384 copybbl.elf > bootrom.hex\n\nbootromx4.hex: copybbl.elf\n\trm -f copybbl.hex\n\t#elf2hex 8 1048576 copybbl.elf > bootrom.hex\n\telf2hex 4 16384 copybbl.elf > bootromx4.hex\n\t#elf2hex 8 16384 copybbl.elf > bootrom.hex\n\nbootrom.bin: copybbl.elf\n\triscv64-unknown-elf-objcopy -O binary copybbl.elf bootrom.bin\n\thexdump -C bootrom.bin > bootrom.txt\n\nbbl.o: bbl.elf Makefile\n\triscv64-unknown-elf-objcopy -O binary bbl.elf bbl.bin\n\triscv64-unknown-elf-objcopy -I binary -O elf64-littleriscv -B riscv bbl.bin bbl.o\n\triscv64-unknown-elf-objdump -D bbl.elf > bbl.dump\n\triscv64-unknown-elf-objdump -b binary -m riscv -D bbl.bin > bbl2.dump\n\thexdump -C bbl.elf > bbl.txt\n\thexdump -C bbl.bin > bbl2.txt\n\nLINUX_DIR = ../../../../linux\n\nvmlinux.o: $(LINUX_DIR)/vmlinux Makefile\n\tcp -f $(LINUX_DIR)/vmlinux vmlinux.elf\n\triscv64-unknown-elf-objcopy -I binary -O elf64-littleriscv -B riscv vmlinux.elf vmlinux.o\n\n\nBBL_FILE = ../../../../riscv-pk/build/bbl\n\nbbl.elf: $(BBL_FILE)\n\tcp -fv $(BBL_FILE) bbl.elf\n\nbbl.hex: $(BBL_FILE)\n\telf2hex 8 8192 $(BBL_FILE) > bbl.hex\n\ndump: copybbl.elf\n\triscv64-unknown-elf-objdump -D copybbl.elf\n"
  },
  {
    "path": "tests/spikehw/boot/copybbl.c",
    "content": "\n\n#define DRAM_BASE 0\n#define DRAM_SIZE 64*1024*1024\n#define BOOT_SIZE 0x400\n#define BBL_BASE (DRAM_SIZE+BOOT_SIZE)\n#define BBL_LEN  (64*1024)\n\nint copybbl()\n{\n    volatile long *src = (long *)BBL_BASE;\n    volatile long *dst = (long*)(DRAM_BASE+0x100);\n    int i;\n    for (i = 0; i < BBL_LEN/sizeof(*dst); i++)\n\t*dst++ = *src++;\n}\n"
  },
  {
    "path": "tests/spikehw/boot/entry.S",
    "content": "\n\nentry:\n\tlui\tsp,1\n\tjal     copybbl\n\tli      a0, 0x200\n\tjr      a0\nstuck:\tj\tstuck\ncopybbl:\t"
  },
  {
    "path": "tests/spikehw/bootromx4.hex",
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    "path": "tests/spikehw/eth.json",
    "content": "{\n    \"eth_sfp_rxp_v\": {\n\t\"sfp1\": \"rxp\"\n    },\n    \"eth_sfp_rxn_v\": {\n\t\"sfp1\": \"rxn\"\n    },\n    \"eth_sfp_txp\": {\n\t\"sfp1\": \"txp\"\n    },\n    \"eth_sfp_txn\": {\n\t\"sfp1\": \"txn\"\n    }\n}\n"
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  {
    "path": "tests/spikehw/flash.json",
    "content": "{\n    \"flash_data_0\": {\n\t\"bpi_flash\": \"data[0]\"\n    },\n    \"flash_data_1\": {\n\t\"bpi_flash\": \"data[1]\"\n    },\n    \"flash_data_2\": {\n\t\"bpi_flash\": \"data[2]\"\n    },\n    \"flash_data_3\": {\n\t\"bpi_flash\": \"data[3]\"\n    },\n    \"flash_data_4\": {\n\t\"bpi_flash\": \"data[4]\"\n    },\n    \"flash_data_5\": {\n\t\"bpi_flash\": \"data[5]\"\n    },\n    \"flash_data_6\": {\n\t\"bpi_flash\": \"data[6]\"\n    },\n    \"flash_data_7\": {\n\t\"bpi_flash\": \"data[7]\"\n    },\n    \"flash_data_8\": {\n\t\"bpi_flash\": \"data[8]\"\n    },\n    \"flash_data_9\": {\n\t\"bpi_flash\": \"data[9]\"\n    },\n    \"flash_data_10\": {\n\t\"bpi_flash\": \"data[10]\"\n    },\n    \"flash_data_11\": {\n\t\"bpi_flash\": \"data[11]\"\n    },\n    \"flash_data_12\": {\n\t\"bpi_flash\": \"data[12]\"\n    },\n    \"flash_data_13\": {\n\t\"bpi_flash\": \"data[13]\"\n    },\n    \"flash_data_14\": {\n\t\"bpi_flash\": \"data[14]\"\n    },\n    \"flash_data_15\": {\n\t\"bpi_flash\": \"data[15]\"\n    },\n    \"flash_addr[0]\": {\n\t\"bpi_flash\": \"addr[0]\"\n    },\n    \"flash_addr[1]\": {\n\t\"bpi_flash\": \"addr[1]\"\n    },\n    \"flash_addr[2]\": {\n\t\"bpi_flash\": \"addr[2]\"\n    },\n    \"flash_addr[3]\": {\n\t\"bpi_flash\": \"addr[3]\"\n    },\n    \"flash_addr[4]\": {\n\t\"bpi_flash\": \"addr[4]\"\n    },\n    \"flash_addr[5]\": {\n\t\"bpi_flash\": \"addr[5]\"\n    },\n    \"flash_addr[6]\": {\n\t\"bpi_flash\": \"addr[6]\"\n    },\n    \"flash_addr[7]\": {\n\t\"bpi_flash\": \"addr[7]\"\n    },\n    \"flash_addr[8]\": {\n\t\"bpi_flash\": \"addr[8]\"\n    },\n    \"flash_addr[9]\": {\n\t\"bpi_flash\": \"addr[9]\"\n    },\n    \"flash_addr[10]\": {\n\t\"bpi_flash\": \"addr[10]\"\n    },\n    \"flash_addr[11]\": {\n\t\"bpi_flash\": \"addr[11]\"\n    },\n    \"flash_addr[12]\": {\n\t\"bpi_flash\": \"addr[12]\"\n    },\n    \"flash_addr[13]\": {\n\t\"bpi_flash\": \"addr[13]\"\n    },\n    \"flash_addr[14]\": {\n\t\"bpi_flash\": \"addr[14]\"\n    },\n    \"flash_addr[15]\": {\n\t\"bpi_flash\": \"addr[15]\"\n    },\n    \"flash_addr[16]\": {\n\t\"bpi_flash\": \"addr[16]\"\n    },\n    \"flash_addr[17]\": {\n\t\"bpi_flash\": \"addr[17]\"\n    },\n    \"flash_addr[18]\": {\n\t\"bpi_flash\": \"addr[18]\"\n    },\n    \"flash_addr[19]\": {\n\t\"bpi_flash\": \"addr[19]\"\n    },\n    \"flash_addr[20]\": {\n\t\"bpi_flash\": \"addr[20]\"\n    },\n    \"flash_addr[21]\": {\n\t\"bpi_flash\": \"addr[21]\"\n    },\n    \"flash_addr[22]\": {\n\t\"bpi_flash\": \"addr[22]\"\n    },\n    \"flash_addr[23]\": {\n\t\"bpi_flash\": \"addr[23]\"\n    },\n    \"flash_addr[24]\": {\n\t\"bpi_flash\": \"addr[24]\"\n    },\n    \"flash_addr[25]\": {\n\t\"bpi_flash\": \"addr[25]\"\n    },\n    \"flash_oe_b\": {\n\t\"bpi_flash\": \"oe_b\"\n    },\n    \"flash_ce_b\": {\n\t\"bpi_flash\": \"ce_b\"\n    },\n    \"flash_adv_b\": {\n\t\"bpi_flash\": \"adv_b\"\n    },\n    \"flash_we_b\": {\n\t\"bpi_flash\": \"we_b\"\n    },\n    \"flash_wait_in_b\": {\n\t\"bpi_flash\": \"wait_in_b\"\n    }\n}\n"
  },
  {
    "path": "tests/spikehw/gencores.tcl",
    "content": "\nset ipdir {cores}\n\nset boardname {nfsume}\n#set boardname {miniitx100}\n\nif {$boardname == {nfsume}} {\n    set partname {xc7vx690tffg1761-2}\n    set databuswidth 32\n}\nif {$boardname == {miniitx100}} {\n    set partname {xc7z100ffg900-2}\n    set databuswidth 64\n}\n\nfile mkdir $ipdir/$boardname\n\ncreate_project -name local_synthesized_ip -in_memory -part $partname\nset_property board_part xilinx.com:vc709:part0:1.0 [current_project]\n\nproc fpgamake_ipcore {core_name core_version ip_name params} {\n    global ipdir boardname\n\n    set generate_ip 0\n\n    if [file exists $ipdir/$boardname/$ip_name/$ip_name.xci] {\n    } else {\n\tputs \"no xci file $ip_name.xci\"\n\tset generate_ip 1\n    }\n    if [file exists $ipdir/$boardname/$ip_name/vivadoversion.txt] {\n\tgets [open $ipdir/$boardname/$ip_name/vivadoversion.txt r] generated_version\n\tset current_version [version -short]\n\tputs \"core was generated by vivado $generated_version, currently running vivado $current_version\"\n\tif {$current_version != $generated_version} {\n\t    puts \"vivado version does not match\"\n\t    set generate_ip 1\n\t}\n    } else {\n\tputs \"no vivado version recorded\"\n\tset generate_ip 1\n    }\n\n    ## check requested core version and parameters\n    if [file exists $ipdir/$boardname/$ip_name/coreversion.txt] {\n\tgets [open $ipdir/$boardname/$ip_name/coreversion.txt r] generated_version\n\tset current_version \"$core_name $core_version $params\"\n\tputs \"Core generated: $generated_version\"\n\tputs \"Core requested: $current_version\"\n\tif {$current_version != $generated_version} {\n\t    puts \"core version or params does not match\"\n\t    set generate_ip 1\n\t}\n    } else {\n\tputs \"no core version recorded\"\n\tset generate_ip 1\n    }\n\n    if $generate_ip {\n\tfile delete -force $ipdir/$boardname/$ip_name\n\tfile mkdir $ipdir/$boardname\n\tcreate_ip -name $core_name -version $core_version -vendor xilinx.com -library ip -module_name $ip_name -dir $ipdir/$boardname\n\tif [llength $params] {\n\t    set_property -dict $params [get_ips $ip_name]\n\t}\n        report_property -file $ipdir/$boardname/$ip_name.properties.log [get_ips $ip_name]\n\t\n\tgenerate_target all [get_files $ipdir/$boardname/$ip_name/$ip_name.xci]\n\n\tset versionfd [open $ipdir/$boardname/$ip_name/vivadoversion.txt w]\n\tputs $versionfd [version -short]\n\tclose $versionfd\n\n\tset corefd [open $ipdir/$boardname/$ip_name/coreversion.txt w]\n\tputs $corefd \"$core_name $core_version $params\"\n\tclose $corefd\n    } else {\n\tread_ip $ipdir/$boardname/$ip_name/$ip_name.xci\n    }\n    if [file exists $ipdir/$boardname/$ip_name/$ip_name.dcp] {\n    } else {\n\tsynth_ip [get_ips $ip_name]\n    }\n}\n\nif {[version -short] == \"2014.2\"} {\n    fpgamake_ipcore axi_ethernet_buffer 2.0 eth_buf [ list CONFIG.C_AVB {0} CONFIG.C_PHYADDR {1} CONFIG.C_PHY_TYPE {5} CONFIG.C_STATS {1} CONFIG.C_TYPE {1} CONFIG.ENABLE_LVDS {0} CONFIG.HAS_SGMII {true} CONFIG.MCAST_EXTEND {false} CONFIG.RXCSUM {None} CONFIG.RXMEM {4k} CONFIG.RXVLAN_STRP {false} CONFIG.RXVLAN_TAG {false} CONFIG.RXVLAN_TRAN {false} CONFIG.SIMULATION_MODE {false} CONFIG.TXCSUM {None} CONFIG.TXMEM {4k} CONFIG.TXVLAN_STRP {false} CONFIG.TXVLAN_TAG {false} CONFIG.TXVLAN_TRAN {false} CONFIG.USE_BOARD_FLOW {true}  ]\n}\n\nfpgamake_ipcore axi_uart16550 2.0  axi_uart16550_1 [list CONFIG.USE_BOARD_FLOW {true} CONFIG.UART_BOARD_INTERFACE {rs232_uart} CONFIG.C_HAS_EXTERNAL_XIN {1} CONFIG.C_HAS_EXTERNAL_RCLK {0} CONFIG.C_EXTERNAL_XIN_CLK_HZ_d {3.686400}  CONFIG.C_EXTERNAL_XIN_CLK_HZ {3686400}]\n\nif {[version -short] == \"2014.2\"} {\n    fpgamake_ipcore axi_intc 4.1 axi_intc_0 [list CONFIG.C_NUM_INTR_INPUTS {16} CONFIG.C_NUM_SW_INTR {0} CONFIG.C_HAS_ILR {1}]\n} else {\n    fpgamake_ipcore axi_intc 4.1 axi_intc_0 [list CONFIG.C_NUM_INTR_INPUTS {16} CONFIG.C_NUM_SW_INTR {0} CONFIG.C_HAS_ILR {1} CONFIG.C_S_AXI_ACLK_FREQ_MHZ  {250}]\n}\n\nfpgamake_ipcore fifo_generator 13.0 dual_clock_axis_fifo_32x1024 [list CONFIG.INTERFACE_TYPE {AXI_STREAM} CONFIG.Clock_Type_AXI {Independent_Clock} CONFIG.TDATA_NUM_BYTES {4} CONFIG.TUSER_WIDTH {0} CONFIG.Enable_TLAST {true} CONFIG.HAS_TKEEP {true} CONFIG.FIFO_Application_Type_axis {Data_FIFO} CONFIG.Reset_Type {Asynchronous_Reset} CONFIG.Full_Flags_Reset_Value {1} CONFIG.TSTRB_WIDTH {4} CONFIG.TKEEP_WIDTH {4} CONFIG.FIFO_Implementation_wach {Independent_Clocks_Distributed_RAM} CONFIG.Full_Threshold_Assert_Value_wach {15} CONFIG.Empty_Threshold_Assert_Value_wach {13} CONFIG.FIFO_Implementation_wdch {Independent_Clocks_Block_RAM} CONFIG.Empty_Threshold_Assert_Value_wdch {1021} CONFIG.FIFO_Implementation_wrch {Independent_Clocks_Distributed_RAM} CONFIG.Full_Threshold_Assert_Value_wrch {15} CONFIG.Empty_Threshold_Assert_Value_wrch {13} CONFIG.FIFO_Implementation_rach {Independent_Clocks_Distributed_RAM} CONFIG.Full_Threshold_Assert_Value_rach {15} CONFIG.Empty_Threshold_Assert_Value_rach {13} CONFIG.FIFO_Implementation_rdch {Independent_Clocks_Block_RAM} CONFIG.Empty_Threshold_Assert_Value_rdch {1021} CONFIG.FIFO_Implementation_axis {Independent_Clocks_Block_RAM} CONFIG.Empty_Threshold_Assert_Value_axis {1021}]\n\nfpgamake_ipcore axi_dma 7.1 axi_dma_0 [list CONFIG.c_sg_include_stscntrl_strm {1} CONFIG.c_m_axi_mm2s_data_width $databuswidth CONFIG.c_m_axi_s2mm_data_width $databuswidth CONFIG.c_mm2s_burst_size {8} CONFIG.c_s2mm_burst_size {8} CONFIG.c_include_mm2s_dre {1} CONFIG.c_sg_use_stsapp_length {1} CONFIG.c_include_s2mm_dre {1}]\n\nfpgamake_ipcore axi_iic 2.0 axi_iic_0 [list CONFIG.AXI_ACLK_FREQ_MHZ {250} CONFIG.C_GPO_WIDTH {8}]\n\nfpgamake_ipcore axi_quad_spi 3.2 axi_spi_0 [list CONFIG.C_USE_STARTUP {0} CONFIG.C_SPI_MODE {0} CONFIG.C_XIP_MODE {0} CONFIG.C_USE_STARTUP_INT {0} CONFIG.C_SCK_RATIO {16} CONFIG.C_FIFO_DEPTH {16} CONFIG.C_TYPE_OF_AXI4_INTERFACE {0}]\n\n## does not exist with vivado 2014.2\nif {[version -short] > \"2014.2\"} {\n    fpgamake_ipcore axi_ethernet 7.0 axi_ethernet_1000basex [list CONFIG.ETHERNET_BOARD_INTERFACE {sfp1} CONFIG.processor_mode {true} CONFIG.DIFFCLK_BOARD_INTERFACE {sfp_mgt_clk} CONFIG.axiliteclkrate {250.0} CONFIG.PHY_TYPE {1000BaseX}]\n\n    fpgamake_ipcore tri_mode_ethernet_mac 9.0 tri_mode_ethernet_mac_0 [list CONFIG.Physical_Interface {Internal}  CONFIG.MAC_Speed {1000_Mbps} CONFIG.SupportLevel {1}]\n\n    ## 2014.2: 14.2\n    ## 2015.4: 15.1\n    fpgamake_ipcore gig_ethernet_pcs_pma 15.1 gig_ethernet_pcs_pma_0 [list  CONFIG.USE_BOARD_FLOW {true} CONFIG.Management_Interface {true} CONFIG.ETHERNET_BOARD_INTERFACE {sfp1} CONFIG.DIFFCLK_BOARD_INTERFACE {sfp_mgt_clk} CONFIG.Standard {1000BASEX} CONFIG.SupportLevel {Include_Shared_Logic_in_Core}]\n\n} else {\n    ## 2014.2: 8.2\n    ## 2015.4: 9.0\n    fpgamake_ipcore tri_mode_ethernet_mac 8.2 tri_mode_ethernet_mac_0 [list CONFIG.Physical_Interface {Internal}  CONFIG.MAC_Speed {1000_Mbps} CONFIG.SupportLevel {1}]\n\n    ## 2014.2: 14.2\n    ## 2015.4: 15.1\n    fpgamake_ipcore gig_ethernet_pcs_pma 14.2 gig_ethernet_pcs_pma_0 [list  CONFIG.USE_BOARD_FLOW {true} CONFIG.Management_Interface {true} CONFIG.ETHERNET_BOARD_INTERFACE {sfp1} CONFIG.DIFFCLK_BOARD_INTERFACE {sfp_mgt_clk} CONFIG.Standard {1000BASEX} CONFIG.SupportLevel {Include_Shared_Logic_in_Core}]\n}\n\nif {[version -short] > \"2014.2\"} {\n    fpgamake_ipcore mig_7series 2.1 ddr3_v2_1 [list CONFIG.XML_INPUT_FILE [pwd]/mig_a.prj CONFIG.RESET_BOARD_INTERFACE {Custom} CONFIG.MIG_DONT_TOUCH_PARAM {Custom} CONFIG.BOARD_MIG_PARAM {Custom}]\n}\n\n"
  },
  {
    "path": "tests/spikehw/geneth.tcl",
    "content": "\nset ipdir {cores}\n\nset boardname {nfsume}\n#set boardname {miniitx100}\n\nif {$boardname == {nfsume}} {\n    set partname {xc7vx690tffg1761-2}\n    set databuswidth 32\n}\nif {$boardname == {miniitx100}} {\n    set partname {xc7z100ffg900-2}\n    set databuswidth 64\n}\n\nfile mkdir $ipdir/$boardname\n\ncreate_project -name local_synthesized_ip -in_memory -part $partname\nset_property board_part xilinx.com:vc709:part0:1.0 [current_project]\n\n################################################################\n# This is a generated script based on design: bd_0\n#\n# Though there are limitations about the generated script,\n# the main purpose of this utility is to make learning\n# IP Integrator Tcl commands easier.\n################################################################\n\n\n################################################################\n# START\n################################################################\n\n# To test this script, run the following commands from Vivado Tcl console:\n# source bd_0_script.tcl\n\n# If you do not already have a project created,\n# you can create a project using the following command:\n#    create_project project_1 myproj -part xc7vx690tffg1761-2\n#    set_property BOARD_PART xilinx.com:vc709:part0:1.0 [current_project]\n\n# CHECKING IF PROJECT EXISTS\nif { [get_projects -quiet] eq \"\" } {\n   puts \"ERROR: Please open or create a project!\"\n   return 1\n}\n\n\n\n# CHANGE DESIGN NAME HERE\nset design_name bd_0\n\n# This script was generated for a remote BD.\nset str_bd_folder /home/jamey/connectal.clean/tests/spikehw/cores/nfsume/foo_eth\nset str_bd_filepath ${str_bd_folder}/${design_name}/${design_name}.bd\n\n# Check if remote design exists on disk\nif { [file exists $str_bd_filepath ] == 1 } {\n   puts \"ERROR: The remote BD file path <$str_bd_filepath> already exists!\\n\"\n\n   puts \"INFO: Please modify the variable <str_bd_folder> to another path or modify the variable <design_name>.\"\n\n   return 1\n}\n\n# Check if design exists in memory\nset list_existing_designs [get_bd_designs -quiet $design_name]\nif { $list_existing_designs ne \"\" } {\n   puts \"ERROR: The design <$design_name> already exists in this project!\"\n   puts \"ERROR: Will not create the remote BD <$design_name> at the folder <$str_bd_folder>.\\n\"\n\n   puts \"INFO: Please modify the variable <design_name>.\"\n\n   return 1\n}\n\n# Check if design exists on disk within project\nset list_existing_designs [get_files */${design_name}.bd]\nif { $list_existing_designs ne \"\" } {\n   puts \"ERROR: The design <$design_name> already exists in this project at location:\"\n   puts \"   $list_existing_designs\"\n   puts \"ERROR: Will not create the remote BD <$design_name> at the folder <$str_bd_folder>.\\n\"\n\n   puts \"INFO: Please modify the variable <design_name>.\"\n\n   return 1\n}\n\n# Now can create the remote BD\ncreate_bd_design -dir $str_bd_folder $design_name\ncurrent_bd_design $design_name\n\n##################################################################\n# DESIGN PROCs\n##################################################################\n\n\n\n# Procedure to create entire design; Provide argument to make\n# procedure reusable. If parentCell is \"\", will use root.\nproc create_root_design { parentCell } {\n\n  if { $parentCell eq \"\" } {\n     set parentCell [get_bd_cells /]\n  }\n\n  # Get object for parentCell\n  set parentObj [get_bd_cells $parentCell]\n  if { $parentObj == \"\" } {\n     puts \"ERROR: Unable to find parent cell <$parentCell>!\"\n     return\n  }\n\n  # Make sure parentObj is hier blk\n  set parentType [get_property TYPE $parentObj]\n  if { $parentType ne \"hier\" } {\n     puts \"ERROR: Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>.\"\n     return\n  }\n\n  # Save current instance; Restore later\n  set oldCurInst [current_bd_instance .]\n\n  # Set parent object as current\n  current_bd_instance $parentObj\n\n\n  # Create interface ports\n  set m_axis_rxd [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 m_axis_rxd ]\n  set m_axis_rxs [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 m_axis_rxs ]\n  set mgt_clk [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 mgt_clk ]\n  set_property -dict [ list \\\nCONFIG.BOARD.ASSOCIATED_PARAM {DIFFCLK_BOARD_INTERFACE} \\\n ] $mgt_clk\n  set s_axi [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi ]\n  set_property -dict [ list \\\nCONFIG.PROTOCOL {AXI4LITE} \\\n ] $s_axi\n  set s_axis_txc [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 s_axis_txc ]\n  set s_axis_txd [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 s_axis_txd ]\n  set sfp [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:sfp_rtl:1.0 sfp ]\n  set_property -dict [ list \\\nCONFIG.BOARD.ASSOCIATED_PARAM {ETHERNET_BOARD_INTERFACE} \\\n ] $sfp\n\n  # Create ports\n  set axi_rxd_arstn [ create_bd_port -dir I -type rst axi_rxd_arstn ]\n  set_property -dict [ list \\\nCONFIG.POLARITY {ACTIVE_LOW} \\\n ] $axi_rxd_arstn\n  set axi_rxs_arstn [ create_bd_port -dir I -type rst axi_rxs_arstn ]\n  set_property -dict [ list \\\nCONFIG.POLARITY {ACTIVE_LOW} \\\n ] $axi_rxs_arstn\n  set axi_txc_arstn [ create_bd_port -dir I -type rst axi_txc_arstn ]\n  set_property -dict [ list \\\nCONFIG.POLARITY {ACTIVE_LOW} \\\n ] $axi_txc_arstn\n  set axi_txd_arstn [ create_bd_port -dir I -type rst axi_txd_arstn ]\n  set_property -dict [ list \\\nCONFIG.POLARITY {ACTIVE_LOW} \\\n ] $axi_txd_arstn\n  set axis_clk [ create_bd_port -dir I -type clk axis_clk ]\n  set gt0_qplloutclk_out [ create_bd_port -dir O -type clk gt0_qplloutclk_out ]\n  set gt0_qplloutrefclk_out [ create_bd_port -dir O -type clk gt0_qplloutrefclk_out ]\n  set gtref_clk_buf_out [ create_bd_port -dir O -type clk gtref_clk_buf_out ]\n  set_property -dict [ list \\\nCONFIG.FREQ_HZ {125000000} \\\n ] $gtref_clk_buf_out\n  set gtref_clk_out [ create_bd_port -dir O -type clk gtref_clk_out ]\n  set_property -dict [ list \\\nCONFIG.FREQ_HZ {125000000} \\\n ] $gtref_clk_out\n  set interrupt [ create_bd_port -dir O -type intr interrupt ]\n  set_property -dict [ list \\\nCONFIG.SENSITIVITY {LEVEL_HIGH} \\\n ] $interrupt\n  set mac_irq [ create_bd_port -dir O -type intr mac_irq ]\n  set_property -dict [ list \\\nCONFIG.SENSITIVITY {EDGE_RISING} \\\n ] $mac_irq\n  set mmcm_locked_out [ create_bd_port -dir O mmcm_locked_out ]\n  set pma_reset_out [ create_bd_port -dir O -type rst pma_reset_out ]\n  set_property -dict [ list \\\nCONFIG.POLARITY {ACTIVE_HIGH} \\\n ] $pma_reset_out\n  set ref_clk [ create_bd_port -dir I -type clk ref_clk ]\n  set rxuserclk2_out [ create_bd_port -dir O -type clk rxuserclk2_out ]\n  set_property -dict [ list \\\nCONFIG.FREQ_HZ {62500000} \\\n ] $rxuserclk2_out\n  set rxuserclk_out [ create_bd_port -dir O -type clk rxuserclk_out ]\n  set_property -dict [ list \\\nCONFIG.FREQ_HZ {62500000} \\\n ] $rxuserclk_out\n  set s_axi_lite_clk [ create_bd_port -dir I -type clk s_axi_lite_clk ]\n  set s_axi_lite_resetn [ create_bd_port -dir I -type rst s_axi_lite_resetn ]\n  set_property -dict [ list \\\nCONFIG.POLARITY {ACTIVE_LOW} \\\n ] $s_axi_lite_resetn\n  set signal_detect [ create_bd_port -dir I signal_detect ]\n  set userclk2_out [ create_bd_port -dir O -type clk userclk2_out ]\n  set_property -dict [ list \\\nCONFIG.FREQ_HZ {125000000} \\\n ] $userclk2_out\n  set userclk_out [ create_bd_port -dir O -type clk userclk_out ]\n  set_property -dict [ list \\\nCONFIG.FREQ_HZ {62500000} \\\n ] $userclk_out\n\n  # Create instance: eth_buf, and set properties\n  set eth_buf [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_ethernet_buffer:2.0 eth_buf ]\n  set_property -dict [ list \\\nCONFIG.C_AVB {0} \\\nCONFIG.C_PHYADDR {1} \\\nCONFIG.C_PHY_TYPE {5} \\\nCONFIG.C_STATS {1} \\\nCONFIG.C_TYPE {1} \\\nCONFIG.ENABLE_LVDS {0} \\\nCONFIG.HAS_SGMII {true} \\\nCONFIG.MCAST_EXTEND {false} \\\nCONFIG.RXCSUM {None} \\\nCONFIG.RXMEM {4k} \\\nCONFIG.RXVLAN_STRP {false} \\\nCONFIG.RXVLAN_TAG {false} \\\nCONFIG.RXVLAN_TRAN {false} \\\nCONFIG.SIMULATION_MODE {false} \\\nCONFIG.TXCSUM {None} \\\nCONFIG.TXMEM {4k} \\\nCONFIG.TXVLAN_STRP {false} \\\nCONFIG.TXVLAN_TAG {false} \\\nCONFIG.TXVLAN_TRAN {false} \\\nCONFIG.USE_BOARD_FLOW {true} \\\nCONFIG.enable_1588 {0} \\\n ] $eth_buf\n\n  # Create instance: eth_mac, and set properties\n  set eth_mac [ create_bd_cell -type ip -vlnv xilinx.com:ip:tri_mode_ethernet_mac:9.0 eth_mac ]\n  set_property -dict [ list \\\nCONFIG.Data_Rate {1_Gbps} \\\nCONFIG.ETHERNET_BOARD_INTERFACE {Custom} \\\nCONFIG.Enable_1588 {false} \\\nCONFIG.Enable_1588_1step {false} \\\nCONFIG.Enable_AVB {false} \\\nCONFIG.Enable_MDIO {true} \\\nCONFIG.Enable_Priority_Flow_Control {false} \\\nCONFIG.Frame_Filter {true} \\\nCONFIG.Half_Duplex {false} \\\nCONFIG.MAC_Speed {1000_Mbps} \\\nCONFIG.MDIO_BOARD_INTERFACE {Custom} \\\nCONFIG.Make_MDIO_External {false} \\\nCONFIG.Management_Interface {true} \\\nCONFIG.Number_of_Table_Entries {4} \\\nCONFIG.Physical_Interface {Internal} \\\nCONFIG.RX_Inband_TS_Enable {false} \\\nCONFIG.Statistics_Counters {true} \\\nCONFIG.Statistics_Reset {false} \\\nCONFIG.Statistics_Width {64bit} \\\nCONFIG.SupportLevel {0} \\\nCONFIG.TX_Inband_CF_Enable {false} \\\nCONFIG.Timer_Format {Time_of_day} \\\nCONFIG.USE_BOARD_FLOW {false} \\\n ] $eth_mac\n\n  # Create instance: pcs_pma, and set properties\n  set pcs_pma [ create_bd_cell -type ip -vlnv xilinx.com:ip:gig_ethernet_pcs_pma:15.1 pcs_pma ]\n  set_property -dict [ list \\\nCONFIG.Auto_Negotiation {true} \\\nCONFIG.C_PHYADDR {1} \\\nCONFIG.DIFFCLK_BOARD_INTERFACE {sfp_mgt_clk} \\\nCONFIG.DrpClkRate {50.0} \\\nCONFIG.ETHERNET_BOARD_INTERFACE {sfp1} \\\nCONFIG.EXAMPLE_SIMULATION {0} \\\nCONFIG.Enable_1588 {false} \\\nCONFIG.Ext_Management_Interface {false} \\\nCONFIG.LvdsRefClk {125} \\\nCONFIG.MDIO_BOARD_INTERFACE {Custom} \\\nCONFIG.Management_Interface {true} \\\nCONFIG.MaxDataRate {1G} \\\nCONFIG.Physical_Interface {Transceiver} \\\nCONFIG.RefClkRate {125} \\\nCONFIG.SGMII_Mode {10_100_1000} \\\nCONFIG.SGMII_PHY_Mode {false} \\\nCONFIG.Standard {1000BASEX} \\\nCONFIG.SupportLevel {Include_Shared_Logic_in_Core} \\\nCONFIG.Timer_Format {Time_of_day} \\\nCONFIG.TransceiverControl {false} \\\nCONFIG.USE_BOARD_FLOW {true} \\\n ] $pcs_pma\n\n  # Create interface connections\n  connect_bd_intf_net -intf_net eth_buf_AXI_STR_RXD [get_bd_intf_ports m_axis_rxd] [get_bd_intf_pins eth_buf/AXI_STR_RXD]\n  connect_bd_intf_net -intf_net eth_buf_AXI_STR_RXS [get_bd_intf_ports m_axis_rxs] [get_bd_intf_pins eth_buf/AXI_STR_RXS]\n  connect_bd_intf_net -intf_net eth_buf_S_AXI_2TEMAC [get_bd_intf_pins eth_buf/S_AXI_2TEMAC] [get_bd_intf_pins eth_mac/s_axi]\n  connect_bd_intf_net -intf_net eth_buf_TX_AXIS_MAC [get_bd_intf_pins eth_buf/TX_AXIS_MAC] [get_bd_intf_pins eth_mac/s_axis_tx]\n  connect_bd_intf_net -intf_net eth_mac_gmii [get_bd_intf_pins eth_mac/gmii] [get_bd_intf_pins pcs_pma/gmii_pcs_pma]\n  connect_bd_intf_net -intf_net eth_mac_m_axis_rx [get_bd_intf_pins eth_buf/RX_AXIS_MAC] [get_bd_intf_pins eth_mac/m_axis_rx]\n  connect_bd_intf_net -intf_net mgt_clk_1 [get_bd_intf_ports mgt_clk] [get_bd_intf_pins pcs_pma/gtrefclk_in]\n  connect_bd_intf_net -intf_net pcs_pma_sfp [get_bd_intf_ports sfp] [get_bd_intf_pins pcs_pma/sfp]\n  connect_bd_intf_net -intf_net s_axi_1 [get_bd_intf_ports s_axi] [get_bd_intf_pins eth_buf/S_AXI]\n  connect_bd_intf_net -intf_net s_axis_txc_1 [get_bd_intf_ports s_axis_txc] [get_bd_intf_pins eth_buf/AXI_STR_TXC]\n  connect_bd_intf_net -intf_net s_axis_txd_1 [get_bd_intf_ports s_axis_txd] [get_bd_intf_pins eth_buf/AXI_STR_TXD]\n\n  # Create port connections\n  connect_bd_net -net axi_rxd_arstn_1 [get_bd_ports axi_rxd_arstn] [get_bd_pins eth_buf/AXI_STR_RXD_ARESETN]\n  connect_bd_net -net axi_rxs_arstn_1 [get_bd_ports axi_rxs_arstn] [get_bd_pins eth_buf/AXI_STR_RXS_ARESETN]\n  connect_bd_net -net axi_txc_arstn_1 [get_bd_ports axi_txc_arstn] [get_bd_pins eth_buf/AXI_STR_TXC_ARESETN]\n  connect_bd_net -net axi_txd_arstn_1 [get_bd_ports axi_txd_arstn] [get_bd_pins eth_buf/AXI_STR_TXD_ARESETN]\n  connect_bd_net -net axis_clk_1 [get_bd_ports axis_clk] [get_bd_pins eth_buf/AXI_STR_RXD_ACLK] [get_bd_pins eth_buf/AXI_STR_RXS_ACLK] [get_bd_pins eth_buf/AXI_STR_TXC_ACLK] [get_bd_pins eth_buf/AXI_STR_TXD_ACLK]\n  connect_bd_net -net eth_buf_INTERRUPT [get_bd_ports interrupt] [get_bd_pins eth_buf/INTERRUPT]\n  connect_bd_net -net eth_buf_RESET2PCSPMA [get_bd_pins eth_buf/RESET2PCSPMA] [get_bd_pins pcs_pma/reset]\n  connect_bd_net -net eth_buf_RESET2TEMACn [get_bd_pins eth_buf/RESET2TEMACn] [get_bd_pins eth_mac/glbl_rstn] [get_bd_pins eth_mac/rx_axi_rstn] [get_bd_pins eth_mac/tx_axi_rstn]\n  connect_bd_net -net eth_buf_pause_req [get_bd_pins eth_buf/pause_req] [get_bd_pins eth_mac/pause_req]\n  connect_bd_net -net eth_buf_pause_val [get_bd_pins eth_buf/pause_val] [get_bd_pins eth_mac/pause_val]\n  connect_bd_net -net eth_buf_tx_ifg_delay [get_bd_pins eth_buf/tx_ifg_delay] [get_bd_pins eth_mac/tx_ifg_delay]\n  connect_bd_net -net eth_mac_mac_irq [get_bd_ports mac_irq] [get_bd_pins eth_mac/mac_irq]\n  connect_bd_net -net eth_mac_mdc [get_bd_pins eth_mac/mdc] [get_bd_pins pcs_pma/mdc]\n  connect_bd_net -net eth_mac_mdio_o [get_bd_pins eth_mac/mdio_o] [get_bd_pins pcs_pma/mdio_i]\n  connect_bd_net -net eth_mac_rx_mac_aclk [get_bd_pins eth_buf/rx_mac_aclk] [get_bd_pins eth_mac/rx_mac_aclk]\n  connect_bd_net -net eth_mac_rx_reset [get_bd_pins eth_buf/rx_reset] [get_bd_pins eth_mac/rx_reset]\n  connect_bd_net -net eth_mac_rx_statistics_valid [get_bd_pins eth_buf/rx_statistics_valid] [get_bd_pins eth_mac/rx_statistics_valid]\n  connect_bd_net -net eth_mac_rx_statistics_vector [get_bd_pins eth_buf/rx_statistics_vector] [get_bd_pins eth_mac/rx_statistics_vector]\n  connect_bd_net -net eth_mac_speedis10100 [get_bd_pins eth_buf/speed_is_10_100] [get_bd_pins eth_mac/speedis10100]\n  connect_bd_net -net eth_mac_tx_mac_aclk [get_bd_pins eth_buf/tx_mac_aclk] [get_bd_pins eth_mac/tx_mac_aclk]\n  connect_bd_net -net eth_mac_tx_reset [get_bd_pins eth_buf/tx_reset] [get_bd_pins eth_mac/tx_reset]\n  connect_bd_net -net pcs_pma_an_interrupt [get_bd_pins eth_buf/EMAC_CLIENT_AUTONEG_INT] [get_bd_pins pcs_pma/an_interrupt]\n  connect_bd_net -net pcs_pma_gt0_qplloutclk_out [get_bd_ports gt0_qplloutclk_out] [get_bd_pins pcs_pma/gt0_qplloutclk_out]\n  connect_bd_net -net pcs_pma_gt0_qplloutrefclk_out [get_bd_ports gt0_qplloutrefclk_out] [get_bd_pins pcs_pma/gt0_qplloutrefclk_out]\n  connect_bd_net -net pcs_pma_gtrefclk_bufg_out [get_bd_ports gtref_clk_buf_out] [get_bd_pins pcs_pma/gtrefclk_bufg_out]\n  connect_bd_net -net pcs_pma_gtrefclk_out [get_bd_ports gtref_clk_out] [get_bd_pins pcs_pma/gtrefclk_out]\n  connect_bd_net -net pcs_pma_mdio_o [get_bd_pins eth_mac/mdio_i] [get_bd_pins pcs_pma/mdio_o]\n  connect_bd_net -net pcs_pma_mmcm_locked_out [get_bd_ports mmcm_locked_out] [get_bd_pins eth_buf/EMAC_RX_DCM_LOCKED_INT] [get_bd_pins pcs_pma/mmcm_locked_out]\n  connect_bd_net -net pcs_pma_pma_reset_out [get_bd_ports pma_reset_out] [get_bd_pins pcs_pma/pma_reset_out]\n  connect_bd_net -net pcs_pma_resetdone [get_bd_pins eth_buf/EMAC_RESET_DONE_INT] [get_bd_pins pcs_pma/resetdone]\n  connect_bd_net -net pcs_pma_rxuserclk2_out [get_bd_ports rxuserclk2_out] [get_bd_pins pcs_pma/rxuserclk2_out]\n  connect_bd_net -net pcs_pma_rxuserclk_out [get_bd_ports rxuserclk_out] [get_bd_pins pcs_pma/rxuserclk_out]\n  connect_bd_net -net pcs_pma_status_vector [get_bd_pins eth_buf/PCSPMA_STATUS_VECTOR] [get_bd_pins pcs_pma/status_vector]\n  connect_bd_net -net pcs_pma_userclk2_out [get_bd_ports userclk2_out] [get_bd_pins eth_buf/GTX_CLK] [get_bd_pins eth_mac/gtx_clk] [get_bd_pins pcs_pma/userclk2_out]\n  connect_bd_net -net pcs_pma_userclk_out [get_bd_ports userclk_out] [get_bd_pins pcs_pma/userclk_out]\n  connect_bd_net -net ref_clk_1 [get_bd_ports ref_clk] [get_bd_pins pcs_pma/independent_clock_bufg]\n  connect_bd_net -net s_axi_lite_clk_1 [get_bd_ports s_axi_lite_clk] [get_bd_pins eth_buf/S_AXI_ACLK] [get_bd_pins eth_mac/s_axi_aclk]\n  connect_bd_net -net s_axi_lite_resetn_1 [get_bd_ports s_axi_lite_resetn] [get_bd_pins eth_buf/S_AXI_ARESETN] [get_bd_pins eth_mac/s_axi_resetn]\n  connect_bd_net -net signal_detect_1 [get_bd_ports signal_detect] [get_bd_pins pcs_pma/signal_detect]\n\n  # Create address segments\n  create_bd_addr_seg -range 0x20000 -offset 0x0 [get_bd_addr_spaces eth_buf/S_AXI_2TEMAC] [get_bd_addr_segs eth_mac/s_axi/Reg] SEG_eth_mac_Reg\n  create_bd_addr_seg -range 0x40000 -offset 0x0 [get_bd_addr_spaces s_axi] [get_bd_addr_segs eth_buf/S_AXI/Reg] SEG_eth_buf_REG\n\n\n  # Restore current instance\n  current_bd_instance $oldCurInst\n\n  save_bd_design\n\n#  generate_target -force synthesis [get_ips]\n\n}\n# End of create_root_design()\n\n\n##################################################################\n# MAIN FLOW\n##################################################################\n\ncreate_root_design \"\"\nmake_wrapper -import -top [get_files $str_bd_filepath]\n\n\n"
  },
  {
    "path": "tests/spikehw/i2c-standard.json",
    "content": "{\n    \"iic_gpo\": {\n\t\"pins\": \"si5324_rst_n\"\n    },\n    \"iic_sda\": {\n\t\"iic_main\": \"sda\"\n    },\n    \"iic_scl\": {\n\t\"iic_main\": \"scl\"\n    }\n}    \n"
  },
  {
    "path": "tests/spikehw/nfsume.json",
    "content": "{\n    \"eth_sgmii_rxp_v\": {\n\t\"sfp1\": \"rxp\"\n    },\n    \"eth_sgmii_rxn_v\": {\n\t\"sfp1\": \"rxn\"\n    },\n    \"eth_sgmii_txp\": {\n\t\"sfp1\": \"txp\"\n    },\n    \"eth_sgmii_txn\": {\n\t\"sfp1\": \"txn\"\n    },\n    \"eth_sfp_rxp_v\": {\n\t\"sfp1\": \"rxp\"\n    },\n    \"eth_sfp_rxn_v\": {\n\t\"sfp1\": \"rxn\"\n    },\n    \"eth_sfp_txp\": {\n\t\"sfp1\": \"txp\"\n    },\n    \"eth_sfp_txn\": {\n\t\"sfp1\": \"txn\"\n    },\n    \"eth_rx_los_v\": {\n\t\"sfp1\": \"rx_los\"\n    },\n    \"eth_tx_disable\": {\n\t\"sfp1\": \"tx_disable\"\n    },\n    \"uart_tx\": {\n\t\"uart\": \"d_out\"\n    },\n    \"uart_rx_x\": {\n\t\"uart\": \"d_in\"\n    },\n    \"uart_rts\": {\n\t\"uart\": \"rts\"\n    },\n    \"uart_cts_x\": {\n\t\"uart\": \"cts\"\n    },\n    \"iic_sda\": {\n\t\"i2c_main\": \"sda\"\n    },\n    \"iic_scl\": {\n\t\"i2c_main\": \"scl\"\n    },\n    \"iic_mux_reset\": {\n\t\"i2c_main\": \"mux_reset\"\n    },\n    \"spi_sck\": {\n\t\"sdio\": \"clk\"\n    },\n    \"spi_ss\": {\n\t\"sdio\": \"d3\"\n    },\n    \"spi_mosi\": {\n\t\"sdio\": \"cmd\"\n    },\n    \"spi_miso\": {\n\t\"sdio\": \"d0\"\n    },\n    \"eth_mgt_clk_clk_p_v\": {\n\t\"pins\": \"si5324_clk_p\",\n\t\"DIFF_TERM\": \"TRUE\",\n\t\"PIO_DIRECTION\": \"INPUT\"\n    },\n    \"eth_mgt_clk_clk_n_v\": {\n\t\"pins\": \"si5324_clk_n\",\n\t\"DIFF_TERM\": \"TRUE\",\n\t\"PIO_DIRECTION\": \"INPUT\"\n    },\n    \"CLK_sfp_rec_clk_p\": {\n\t\"pins\": \"sfp_rec_clk_p\",\n        \"IOSTANDARD\": \"DIFF_HSTL_II_18\",\n        \"DIFF_TERM\": \"TRUE\",\n        \"PIO_DIRECTION\": \"OUTPUT\"\n    },\n    \"CLK_sfp_rec_clk_n\": {\n\t\"pins\": \"sfp_rec_clk_n\",\n        \"IOSTANDARD\": \"DIFF_HSTL_II_18\",\n        \"DIFF_TERM\": \"TRUE\",\n        \"PIO_DIRECTION\": \"OUTPUT\"\n    }\n}\n"
  },
  {
    "path": "tests/spikehw/program.tcl",
    "content": "open_hw\nconnect_hw_server\nopen_hw_target\ncurrent_hw_device [lindex [get_hw_devices] 0]\nset_property PROBES.FILE {/home/jamey/connectal.clean/tests/spikehw/debug.ltx} [lindex [get_hw_devices] 0]\nset_property PROGRAM.FILE {/home/jamey/connectal.clean/tests/spikehw/debug.bit} [lindex [get_hw_devices] 0]\nprogram_hw_devices [lindex [get_hw_devices] 0]\nquit\n"
  },
  {
    "path": "tests/spikehw/rtscts.json",
    "content": "{\n    \"uart_rts\": {\n\t\"uart\": \"rts\"\n    },\n    \"uart_cts_x\": {\n\t\"uart\": \"cts\"\n    }\n}\n"
  },
  {
    "path": "tests/spikehw/spikehw-miniitx100.json",
    "content": "{\n    \"eth_rx_los_v\": {\n\t\"sfp1\": \"rx_los\"\n    },\n    \"eth_tx_disable\": {\n\t\"sfp1\": \"tx_disable\"\n    },\n    \"iic_sda\": {\n\t\"sfp1\": \"mod_def2\",\n        \"PIO_DIRECTION\": \"BIDIR\"\n    },\n    \"iic_scl\": {\n\t\"sfp1\": \"mod_def1\",\n        \"PIO_DIRECTION\": \"BIDIR\"\n    },\n    \"iic_mux_reset\": {\n\t\"sfp1\": \"mod_def0\",\n        \"PIO_DIRECTION\": \"OUTPUT\",\n\t\"comment\": \"not connected\"\n    }\n}\n"
  },
  {
    "path": "tests/spikehw/spikehw-vc707g2.json",
    "content": "{\n    \"eth_mgt_clk_clk_p_v\": {\n\t\"pins\": \"sgmii_clk_p\"\n    },\n    \"eth_mgt_clk_clk_n_v\": {\n\t\"pins\": \"sgmii_clk_n\"\n    }\n}\n"
  },
  {
    "path": "tests/spikehw/spikehw-vc709.json",
    "content": "{\n    \"eth_mgt_clk_clk_p_v\": {\n\t\"pins\": \"si5324_clk_p\"\n    },\n    \"eth_mgt_clk_clk_n_v\": {\n\t\"pins\": \"si5324_clk_n\"\n    }\n}\n"
  },
  {
    "path": "tests/spikehw/spikehw.cpp",
    "content": "\n#include <fcntl.h>\n#include <sys/mman.h>\n#include <sys/types.h>\n#include <sys/stat.h>\n#include <unistd.h>\n#include <errno.h>\n\n#include <SpikeHwIndication.h>\n#include <SpikeHwRequest.h>\n#include \"dmaManager.h\"\n#include \"spikehw.h\"\n#ifdef REGISTER_SPIKE_DEVICES\n#include <functional>\n#include <riscv/sim.h>\n#include <riscv/devices.h>\n#endif\n\n\nint verbose = 0;\n\nclass SpikeHwIndication : public SpikeHwIndicationWrapper\n{\n    sem_t sem;\npublic:\n    int irq;\n    uint32_t buf[16];\n    IrqCallback irqCallback;\n\n  void traceDmaRequest(DmaChannel chan, int write, uint16_t objId, uint32_t offset, uint16_t burstLen)\n  {\n    fprintf(stderr, \"traceDmaRequest chan=%d write=%d objId=%d offset=%08x burstLen=%d\\n\", chan, write, objId, offset, burstLen);\n  }\n  void traceDmaData ( const DmaChannel chan, const int write, const uint32_t data, const int last )\n  {\n    fprintf(stderr, \"traceDmaData chan=%d write=%d data=%08x last=%d\\n\", chan, write, data, last);\n  }\n\n  void irqChanged( const uint8_t irq, const uint16_t intrSources ) {\n    if (intrSources & 0xe) fprintf(stderr, \"iic intr=%d %04x\\n\", irq, intrSources);\n      if (verbose) fprintf(stderr, \"SpikeHw::irqChanged %d intr sources %x\\n\", irq, intrSources);\n      this->irq = irq;\n      if (irqCallback)\n\tirqCallback(irq);\n    }\n    virtual void resetDone() {\n\tfprintf(stderr, \"reset done\\n\");\n\tsem_post(&sem);\n    }\n    virtual void status ( const uint8_t reset_asserted, const uint8_t mmcm_locked, const uint8_t rx_los, const uint8_t irq, const uint16_t intrSources ) {\n\tfprintf(stderr, \"spikehw status reset_asserted=%d mmcm_locked=%d rx_los=%d irq=%d intr sources=%x\\n\",\n\t\treset_asserted, mmcm_locked, rx_los, irq, intrSources);\n\tsem_post(&sem);\n    }\n\n    void wait() {\n\tstruct timespec timeout;\n\ttimeout.tv_sec = 1000;\n\ttimeout.tv_nsec = 0;\n\tif (0) {\n\t  for (int tries = 0; tries < 10; tries++) {\n\t    int status = sem_timedwait(&sem, &timeout);\n\t    if (status != 0 && errno == ETIMEDOUT) {\n\t      if (tries > 5)\n\t\tfprintf(stderr, \"%s:%d: try %d timed out waiting for response status=%d errno=%d\\n\", __FILE__, __LINE__, tries, status, errno);\n\t    } else {\n\t      break;\n\t    }\n\t  }\n\t} else {\n\t  sem_wait(&sem);\n\t}\n    }\n\n    void readDone ( const uint32_t value ) {\n\tbuf[0] = value;\n\tif (verbose) fprintf(stderr, \"readDone value=%08x\\n\", value);\n\tsem_post(&sem);\n    }\n\n    void writeDone (  ) {\n\tif (verbose) fprintf(stderr, \"writeDone\\n\");\n\tsem_post(&sem);\n    }\n\n    void readFlashDone ( const uint32_t value ) {\n\tbuf[0] = value;\n\tif (verbose) fprintf(stderr, \"readFlashDone value=%08x\\n\", value);\n\tsem_post(&sem);\n    }\n\n    void writeFlashDone (  ) {\n\tif (verbose) fprintf(stderr, \"writeFlashDone\\n\");\n\tsem_post(&sem);\n    }\n\n    SpikeHwIndication(unsigned int id, IrqCallback callback=0) : SpikeHwIndicationWrapper(id), irq(0), irqCallback(callback) {\n      sem_init(&sem, 0, 0);\n    }\n};\n\n\nSpikeHwRequestProxy *request;\nSpikeHwIndication *indication;\n\nSpikeHw::SpikeHw(IrqCallback callback)\n    : request(0), indication(0), dmaManager(0), didReset(false), mainMemFd(0)\n{\n    request = new SpikeHwRequestProxy(IfcNames_SpikeHwRequestS2H);\n    indication = new SpikeHwIndication(IfcNames_SpikeHwIndicationH2S, callback);\n    dmaManager = platformInit();\n    request->reset();\n    request->setFlashParameters(100);\n    request->iicReset(0); // de-assert reset\n}\n\nSpikeHw::~SpikeHw()\n{\n  //delete request;\n  //delete indication;\n  request = 0;\n  indication = 0;\n}\n\nvoid SpikeHw::maybeReset()\n{\n    if (0)\n    if (!didReset) {\n\tfprintf(stderr, \"resetting flash\\n\");\n\trequest->reset();\n\tindication->wait();\n\t//request->setParameters(50, 0);\n\tfprintf(stderr, \"done resetting flash\\n\");\n\tdidReset = true;\n    }\n}\n\nvoid SpikeHw::status()\n{\n    request->status();\n    indication->wait();\n}\n\nvoid SpikeHw::setupDma(uint32_t memfd)\n{\n    int memref = dmaManager->reference(memfd);\n    fprintf(stderr, \"SpikeHw::setupDma memfd=%d memref=%d\\n\", memfd, memref);\n    request->setupDma(memref);\n}\n\nvoid SpikeHw::read(unsigned long offset, uint8_t *buf)\n{\n    maybeReset();\n\n    if (verbose) fprintf(stderr, \"SpikeHw::read offset=%lx\\n\", offset);\n    request->read(offset);\n    indication->wait();\n    if (verbose) fprintf(stderr, \"SpikeHw::read offset=%lx value=%x\\n\", offset, *(uint32_t *)indication->buf);\n    memcpy(buf, indication->buf, 4);\n}\n\nvoid SpikeHw::write(unsigned long offset, const uint8_t *buf)\n{\n    maybeReset();\n\n    if (verbose) fprintf(stderr, \"SpikeHw::write offset=%lx value=%x\\n\", offset, *(uint32_t *)buf);\n    request->write(offset, *(uint32_t *)buf);\n    indication->wait();\n    //request->status();\n    //indication->wait();\n}\n\nuint32_t SpikeHw::read(unsigned long offset)\n{\n    maybeReset();\n\n    if (verbose) fprintf(stderr, \"SpikeHw::read offset=%08lx\\n\", offset);\n    request->read(offset);\n    indication->wait();\n    if (verbose) fprintf(stderr, \"SpikeHw::read done value=%x\\n\", *(uint32_t *)indication->buf);\n    return *(uint32_t *)indication->buf;\n}\n\nvoid SpikeHw::write(unsigned long offset, const uint32_t value)\n{\n    maybeReset();\n\n    if (verbose) fprintf(stderr, \"SpikeHw::write offset=%08lx value=%x\\n\", offset, value);\n    request->write(offset, value);\n    indication->wait();\n    if (verbose) fprintf(stderr, \"SpikeHw::write done\\n\");\n}\n\nvoid SpikeHw::setFlashParameters(unsigned long cycles)\n{\n    request->setFlashParameters(cycles);\n}\n\nvoid SpikeHw::readFlash(unsigned long offset, uint8_t *buf)\n{\n    maybeReset();\n\n    if (verbose) fprintf(stderr, \"SpikeHw::readFlash offset=%lx\\n\", offset);\n    request->readFlash(offset);\n    indication->wait();\n    if (verbose) fprintf(stderr, \"SpikeHw::readFlash offset=%lx value=%x\\n\", offset, *(uint32_t *)indication->buf);\n    memcpy(buf, indication->buf, 4);\n}\n\nvoid SpikeHw::writeFlash(unsigned long offset, const uint8_t *buf)\n{\n    maybeReset();\n\n    if (verbose) fprintf(stderr, \"SpikeHw::writeFlash offset=%lx value=%x\\n\", offset, *(uint32_t *)buf);\n    request->writeFlash(offset, *(uint32_t *)buf);\n    indication->wait();\n}\n\nbool SpikeHw::hasInterrupt()\n{\n    return indication->irq; \n}\nvoid SpikeHw::clearInterrupt()\n{\n    indication->irq = 0;\n}\n\nchar *SpikeHw::allocate_mem(size_t memsz)\n{\n    int memfd = portalAlloc(memsz, 1);\n    if (memfd < 0)\n\treturn 0;\n    char *buf = (char *)portalMmap(memfd, memsz);\n    if (buf == MAP_FAILED) {\n\tclose(memfd);\n\treturn 0;\n    }\n    fprintf(stderr, \"SpikeHw::allocate_mem memsz=%lx memfd=%d buf=%p\\n\", memsz, memfd, buf);\n    if (!mainMemFd) {\n\tsetupDma(memfd);\n\tmainMemFd = memfd;\n\tfprintf(stderr, \"SpikeHw::allocate_mem mainMemFd=%d\\n\", memfd);\n    }\n    return buf;\n}\n\nSpikeHw *spikeHw;\n\n#ifdef REGISTER_SPIKE_DEVICES\nclass spikehw_device_t : public abstract_device_t {\npublic:\n  spikehw_device_t();\n  bool has_interrupt();\n  bool load(reg_t addr, size_t len, uint8_t* bytes);\n  bool store(reg_t addr, size_t len, const uint8_t* bytes);\n  static abstract_device_t *make_device();\n};\n\nspikehw_device_t::spikehw_device_t()\n{\n  if (!spikeHw)\n    spikeHw = new SpikeHw();\n}\n\nbool spikehw_device_t::has_interrupt()\n{\n    if (spikeHw->hasInterrupt()) {\n\tspikeHw->clearInterrupt();\n\treturn true;\n    }\n    return false;\n}\n\nbool spikehw_device_t::load(reg_t addr, size_t len, uint8_t* bytes)\n{\n    spikeHw->read(addr, bytes); // always reads 4 bytes\n    return true;\n}\n\nbool spikehw_device_t::store(reg_t addr, size_t len, const uint8_t* bytes)\n{\n    spikeHw->write(addr, bytes);\n    return true;\n}\n\nabstract_device_t *spikehw_device_t::make_device()\n{\n    std::cerr << \"make_device called\" << std::endl;\n    return new spikehw_device_t();\n}\n\nclass spikeflash_device_t : public abstract_device_t {\npublic:\n  spikeflash_device_t();\n  bool load(reg_t addr, size_t len, uint8_t* bytes);\n  bool store(reg_t addr, size_t len, const uint8_t* bytes);\n  static abstract_device_t *make_device();\n};\n\nspikeflash_device_t::spikeflash_device_t()\n{\n  if (!spikeHw)\n    spikeHw = new SpikeHw();\n}\n\nbool spikeflash_device_t::load(reg_t addr, size_t len, uint8_t* bytes)\n{\n    if (addr & 1 && len != 1) fprintf(stderr, \"spikeflash::load addr=%08lx len=%ld\\n\", addr, len);\n    if (addr & 1) {\n\tuint8_t data[2];\n\tspikeHw->readFlash(addr, data); // always reads 4 bytes\n\tbytes[0] = data[1];\n\tif (len > 1)\n\t    return false;\n\telse\n\t    return true;\n    }\n\n    while (len) {\n\tspikeHw->readFlash(addr, bytes); // always reads 4 bytes\n\tif (len < 2)\n\t    break;\n\taddr  += 2;\n\tbytes += 2;\n\tlen   -= 2;\n    }\n    return true;\n}\n\nbool spikeflash_device_t::store(reg_t addr, size_t len, const uint8_t* bytes)\n{\n    //fprintf(stderr, \"spikeflash::store addr=%08lx len=%ld bytes=%02x\\n\", addr, len, *(uint16_t *)bytes);\n    if (len != 2)\n      return false;\n    spikeHw->writeFlash(addr, bytes);\n    return true;\n}\n\nabstract_device_t *spikeflash_device_t::make_device()\n{\n    std::cerr << \"spikeflash_device_t::make_device called\" << std::endl;\n    return new spikeflash_device_t();\n}\n\nclass devicetree_device_t : public abstract_device_t {\npublic:\n    devicetree_device_t();\n    bool load(reg_t addr, size_t len, uint8_t* bytes);\n    bool store(reg_t addr, size_t len, const uint8_t* bytes);\n    static abstract_device_t *make_device();\nprivate:\n    const char *dtb;\n    size_t dtbsz;\n};\n\ndevicetree_device_t::devicetree_device_t()\n{\n    int fd = open(\"devicetree.dtb\", O_RDONLY);\n    if (fd > 0) {\n\tstruct stat statbuf;\n\tint status = fstat(fd, &statbuf);\n\tfprintf(stderr, \"fstat status %d size %ld\\n\", status, statbuf.st_size);\n\tif (status == 0) {\n\t    dtb = (const char *)mmap(0, statbuf.st_size, PROT_READ, MAP_SHARED, fd, 0);\n\t    dtbsz = statbuf.st_size;\n\t    fprintf(stderr, \"mapped dtb at %p (%ld bytes)\\n\", dtb, dtbsz);\n\t}\n\tclose(fd);\n    } else {\n\tfprintf(stderr, \"Could not open devicetree.dtb\\n\");\n    }\n}\n\nbool devicetree_device_t::load(reg_t addr, size_t len, uint8_t* bytes)\n{\n    if (dtb && dtb != MAP_FAILED) {\n\tif ((addr < dtbsz) && (bytes != 0)) {\n\t    memcpy(bytes, dtb + addr, len);\n\t    return true;\n\t}\n    }\n    return false;\n}\n\nbool devicetree_device_t::store(reg_t addr, size_t len, const uint8_t* bytes)\n{\n    return true;\n}\n\nabstract_device_t *devicetree_device_t::make_device()\n{\n    std::cerr << \"devicetree_device_t::make_device called\" << std::endl;\n    return new devicetree_device_t();\n}\n\n//REGISTER_MEM_ALLOCATOR(SpikeHw::allocate_mem);\nREGISTER_DEVICE(devicetree, 0x04080000, devicetree_device_t::make_device);\nREGISTER_DEVICE(spikehw,    0x04100000, spikehw_device_t::make_device);\nREGISTER_DEVICE(spikeflash, 0x08000000, spikeflash_device_t::make_device);\n#endif\n\n#ifndef REGISTER_SPIKE_DEVICES\nextern \"C\" {\n\n    struct FpgaOps {\n\tuint64_t (*read)(uint64_t addr);\n\tvoid (*write)(uint64_t addr, uint64_t value);\n\tvoid (*close)();\n        void *(*alloc_mem)(size_t size);\n    };\n\n    uint64_t fpga_read(uint64_t addr)\n    {\n      uint64_t val = spikeHw->read(0x100000 + addr);\n      return val;\n    }\n\n    void fpga_write(uint64_t addr, uint64_t value)\n    {\n\tspikeHw->write(0x100000 + addr, value);\n    }\n\n    void fpga_close()\n    {\n    }\n\n    void *fpga_alloc_mem(size_t size)\n    {\n\treturn (void *)spikeHw->allocate_mem(size);;\n    }\n\n    void *fpgadev_init(void (*irqCallback)(int irq)) {\n\tfprintf(stderr, \"connectal.so init called\\n\");\n\tif (!spikeHw)\n\t    spikeHw = new SpikeHw(irqCallback);\n\tstruct FpgaOps *ops = (struct FpgaOps *)malloc(sizeof(struct FpgaOps));\n\tops->read = fpga_read;\n\tops->write = fpga_write;\n\tops->close = fpga_close;\n\tops->alloc_mem = fpga_alloc_mem;\n\treturn ops;\n    }\n}\n#endif\n"
  },
  {
    "path": "tests/spikehw/spikehw.h",
    "content": "#ifndef SPIKEHW_H\n#define SPIKEHW_H\n\n#include <stdint.h>\n\nclass SpikeHwRequestProxy;\nclass SpikeHwIndication;\nclass DmaManager;\n\ntypedef void (*IrqCallback)(int irq);\n\n\nclass SpikeHw {\n public:\n  SpikeHw(IrqCallback callback=0);\n  ~SpikeHw();\n  int irq ( const uint8_t newLevel );\n  void status();\n  void read(unsigned long offset, uint8_t *buf);\n  void write(unsigned long offset, const uint8_t *buf);\n  uint32_t read(unsigned long offset);\n  void write(unsigned long offset, const uint32_t value);\n  void setFlashParameters(unsigned long cycles);\n  void readFlash(unsigned long offset, uint8_t *buf);\n  void writeFlash(unsigned long offset, const uint8_t *buf);\n  bool hasInterrupt();\n  void clearInterrupt();\n  char *allocate_mem(size_t memsz);\n private:\n  void setupDma( uint32_t memfd );\n  SpikeHwRequestProxy *request;\n  SpikeHwIndication *indication;\n  DmaManager           *dmaManager;\n  bool didReset;\n  int mainMemFd;\n\n  void maybeReset();\n};\n\n#endif\n"
  },
  {
    "path": "tests/spikehw/spikehw.json",
    "content": "{\n    \"eth_sfp_rxp_v\": {\n\t\"sfp1\": \"rxp\"\n    },\n    \"eth_sfp_rxn_v\": {\n\t\"sfp1\": \"rxn\"\n    },\n    \"eth_sfp_txp\": {\n\t\"sfp1\": \"txp\"\n    },\n    \"eth_sfp_txn\": {\n\t\"sfp1\": \"txn\"\n    },\n\n    \"flash_data_0\": {\n\t\"bpi_flash\": \"data[0]\"\n    },\n    \"flash_data_1\": {\n\t\"bpi_flash\": \"data[1]\"\n    },\n    \"flash_data_2\": {\n\t\"bpi_flash\": \"data[2]\"\n    },\n    \"flash_data_3\": {\n\t\"bpi_flash\": \"data[3]\"\n    },\n    \"flash_data_4\": {\n\t\"bpi_flash\": \"data[4]\"\n    },\n    \"flash_data_5\": {\n\t\"bpi_flash\": \"data[5]\"\n    },\n    \"flash_data_6\": {\n\t\"bpi_flash\": \"data[6]\"\n    },\n    \"flash_data_7\": {\n\t\"bpi_flash\": \"data[7]\"\n    },\n    \"flash_data_8\": {\n\t\"bpi_flash\": \"data[8]\"\n    },\n    \"flash_data_9\": {\n\t\"bpi_flash\": \"data[9]\"\n    },\n    \"flash_data_10\": {\n\t\"bpi_flash\": \"data[10]\"\n    },\n    \"flash_data_11\": {\n\t\"bpi_flash\": \"data[11]\"\n    },\n    \"flash_data_12\": {\n\t\"bpi_flash\": \"data[12]\"\n    },\n    \"flash_data_13\": {\n\t\"bpi_flash\": \"data[13]\"\n    },\n    \"flash_data_14\": {\n\t\"bpi_flash\": \"data[14]\"\n    },\n    \"flash_data_15\": {\n\t\"bpi_flash\": \"data[15]\"\n    },\n    \"flash_addr[0]\": {\n\t\"bpi_flash\": \"addr[0]\"\n    },\n    \"flash_addr[1]\": {\n\t\"bpi_flash\": \"addr[1]\"\n    },\n    \"flash_addr[2]\": {\n\t\"bpi_flash\": \"addr[2]\"\n    },\n    \"flash_addr[3]\": {\n\t\"bpi_flash\": \"addr[3]\"\n    },\n    \"flash_addr[4]\": {\n\t\"bpi_flash\": \"addr[4]\"\n    },\n    \"flash_addr[5]\": {\n\t\"bpi_flash\": \"addr[5]\"\n    },\n    \"flash_addr[6]\": {\n\t\"bpi_flash\": \"addr[6]\"\n    },\n    \"flash_addr[7]\": {\n\t\"bpi_flash\": \"addr[7]\"\n    },\n    \"flash_addr[8]\": {\n\t\"bpi_flash\": \"addr[8]\"\n    },\n    \"flash_addr[9]\": {\n\t\"bpi_flash\": \"addr[9]\"\n    },\n    \"flash_addr[10]\": {\n\t\"bpi_flash\": \"addr[10]\"\n    },\n    \"flash_addr[11]\": {\n\t\"bpi_flash\": \"addr[11]\"\n    },\n    \"flash_addr[12]\": {\n\t\"bpi_flash\": \"addr[12]\"\n    },\n    \"flash_addr[13]\": {\n\t\"bpi_flash\": \"addr[13]\"\n    },\n    \"flash_addr[14]\": {\n\t\"bpi_flash\": \"addr[14]\"\n    },\n    \"flash_addr[15]\": {\n\t\"bpi_flash\": \"addr[15]\"\n    },\n    \"flash_addr[16]\": {\n\t\"bpi_flash\": \"addr[16]\"\n    },\n    \"flash_addr[17]\": {\n\t\"bpi_flash\": \"addr[17]\"\n    },\n    \"flash_addr[18]\": {\n\t\"bpi_flash\": \"addr[18]\"\n    },\n    \"flash_addr[19]\": {\n\t\"bpi_flash\": \"addr[19]\"\n    },\n    \"flash_addr[20]\": {\n\t\"bpi_flash\": \"addr[20]\"\n    },\n    \"flash_addr[21]\": {\n\t\"bpi_flash\": \"addr[21]\"\n    },\n    \"flash_addr[22]\": {\n\t\"bpi_flash\": \"addr[22]\"\n    },\n    \"flash_addr[23]\": {\n\t\"bpi_flash\": \"addr[23]\"\n    },\n    \"flash_addr[24]\": {\n\t\"bpi_flash\": \"addr[24]\"\n    },\n    \"flash_addr[25]\": {\n\t\"bpi_flash\": \"addr[25]\"\n    },\n    \"flash_oe_b\": {\n\t\"bpi_flash\": \"oe_b\"\n    },\n    \"flash_ce_b\": {\n\t\"bpi_flash\": \"ce_b\"\n    },\n    \"flash_adv_b\": {\n\t\"bpi_flash\": \"adv_b\"\n    },\n    \"flash_we_b\": {\n\t\"bpi_flash\": \"we_b\"\n    },\n    \"flash_wait_in_b\": {\n\t\"bpi_flash\": \"wait_in_b\"\n    },\n    \"uart_tx\": {\n\t\"uart\": \"d_out\"\n    },\n    \"uart_rx_x\": {\n\t\"uart\": \"d_in\"\n    },\n    \"uart_rts\": {\n\t\"uart\": \"rts\"\n    },\n    \"uart_cts_x\": {\n\t\"uart\": \"cts\"\n    },\n    \"iic_gpo\": {\n\t\"pins\": \"si5324_rst_n\"\n    },\n    \"iic_sda\": {\n\t\"iic_main\": \"sda\"\n    },\n    \"iic_scl\": {\n\t\"iic_main\": \"scl\"\n    }\n}\n"
  },
  {
    "path": "tests/spikehw/spikehw.xdc",
    "content": "create_clock -name eth_mgt_clk_clk -period 8.000 [get_ports eth_mgt_clk_clk_p_v]\n"
  },
  {
    "path": "tests/spikehw/test-spikehw.cpp",
    "content": "#include <stdio.h>\n\n#include \"spikehw.h\"\n\n#ifdef REGISTER_SPIKE_DEVICES\n#include <riscv/decode.h>\n#include <riscv/devices.h>\n#include <map>\n#include <vector>\n#include <functional>\n#endif\n\nstatic SpikeHw *spikeHw;\n\n#ifdef REGISTER_SPIKE_DEVICES\n// spike stubs\nstd::map<reg_t, std::function<abstract_device_t*()>>& devices()\n{\n    static std::map<reg_t, std::function<abstract_device_t*()>> v;\n    return v;\n}\nvoid register_device(reg_t addr, std::function<abstract_device_t*()> f)\n{\n}\nvoid register_mem_allocator(std::function<char *(size_t)> f)\n{\n}\n#endif\n\nconst char *regnames[] = {\n  \"CR\",\n  \"SR\",\n  \"TX_FIFO\",\n  \"RX_FIFO\",\n  \"ADR\",\n  \"TX_FIFO_OCY\",\n  \"RX_FIFO_OCY\",\n  \"TBA\",\n  \"RX_FIFO_DEPTH\",\n  \"GPO\"  \n};\n\nstatic void dumpI2cRegs()\n{\n    fprintf(stderr, \"------------------------------------------------------------\\n\");\n    fprintf(stderr, \"I2C GIE %04x\\n\", spikeHw->read(0x10301c));\n    fprintf(stderr, \"I2C ISR %04x\\n\", spikeHw->read(0x103020));\n    fprintf(stderr, \"I2C IER %04x\\n\", spikeHw->read(0x103028));\n\n    for (int i = 0; i < 10; i++)\n\tfprintf(stderr, \"I2C REG%d %s %04x\\n\", i, regnames[i], spikeHw->read(0x103100 + 4*i));\n    fprintf(stderr, \"------------------------------------------------------------\\n\");\n}\n\nint main(int argc, const char **argv)\n{\n    spikeHw = new SpikeHw();\n    // not needed yet\n    //spikeHw->setupDma(memfd);\n\n    // query mmcm and interrupt status\n    spikeHw->status();\n\n    fprintf(stderr, \"boot rom[0] %x\\n\", spikeHw->read(0));\n\n    fprintf(stderr, \"scratch register %x\\n\", spikeHw->read(0x10001c));\n    spikeHw->write(0x10001c, 0x22);\n    fprintf(stderr, \"scratch register %x\\n\", spikeHw->read(0x10001c));\n    fprintf(stderr, \"scratch register %x\\n\", spikeHw->read(0x10001c));\n    fprintf(stderr, \"scratch register %x\\n\", spikeHw->read(0x10001c));\n    fprintf(stderr, \"scratch register %x\\n\", spikeHw->read(0x10001c));\n\n    spikeHw->read(0x100000);\n    spikeHw->write(0x100000, 'h');\n\n    spikeHw->write(0x103040, 0xa); // SOFTR\n\n    dumpI2cRegs();\n\n    // let's read i2c 0x50\n    spikeHw->write(0x103108, 0x100 | (0x56 << 1) | 1); // TX_FIFO\n    spikeHw->write(0x103120, 1); // RX_FIFO_DEPTH\n    spikeHw->write(0x103100, 5); // CR enable\n    spikeHw->write(0x103108, (uint32_t)1); // TX_FIFO\n    spikeHw->write(0x103108, 0x200 | 2); // TX_FIFO\n    fprintf(stderr, \"I2C RX_FIFO_OCY %04x\\n\", spikeHw->read(0x103118));\n\n    dumpI2cRegs();\n    dumpI2cRegs();\n    dumpI2cRegs();\n    dumpI2cRegs();\n\n    return 0;\n\n    // let's write 1 to 0x50\n    spikeHw->write(0x103108, 0x100 | (0x56 << 1) | 0); // TX_FIFO\n    spikeHw->write(0x103100, 5); // CR enable\n    spikeHw->write(0x103108, 0x200 | 1); // TX_FIFO\n\n    dumpI2cRegs();\n\n\n    // let's read i2c 0x50\n    spikeHw->write(0x103108, 0x100 | (0x56 << 1) | 1); // TX_FIFO\n    spikeHw->write(0x103120, 2); // RX_FIFO_DEPTH\n    spikeHw->write(0x103100, 5); // CR enable\n    spikeHw->write(0x103108, 0x200 | 1); // TX_FIFO\n    fprintf(stderr, \"I2C RX_FIFO_OCY %04x\\n\", spikeHw->read(0x103118));\n\n    dumpI2cRegs();\n    return 0;\n\n    // read boot rom\n    uint32_t word = 0;\n    uint32_t expected[] = {\n\t0x00001137,\n\t0x010000ef,\n\t0x20000513,\n\t0x00050067,\n\t0x0000006f,\n\t0x040007b7,\n\t0x40078793,\n\t0xfc0005b7\n    };\n    for (int i = 0; i < 8; i++){\n\tspikeHw->read(0x000000 + i*4, (uint8_t *)&word);\n\tfprintf(stderr, \"word %04x of boot ROM %08x (expected %08x)\\n\", i*4, word, expected[i]);\n    }\n\n    // read ethernet identification register\n    uint32_t id;\n    spikeHw->read(0x180000 + 0x4f8, (uint8_t *)&id);\n    fprintf(stderr, \"AXI Ethernet Identification %08x (expected %08x)\\n\", id, 0x09000000);\n\n    // put flash in query mode\n    spikeHw->setFlashParameters(50); // divides clock by 50\n    uint32_t values[4] = { 0x98 };\n    spikeHw->writeFlash(0x00aa, (uint8_t *)&values[0]);\n    spikeHw->readFlash(0x0020, (uint8_t *)&values[1]);\n    spikeHw->readFlash(0x0022, (uint8_t *)&values[2]);\n    spikeHw->readFlash(0x0024, (uint8_t *)&values[3]);\n    fprintf(stderr, \"Query flash %02x.%02x.%02x %c%c%c (expected QRY)\\n\", values[1], values[2], values[3], values[1], values[2], values[3]);\n\n    return 0;\n}\n"
  },
  {
    "path": "tests/spikehw/trace.tcl",
    "content": "open_hw\nconnect_hw_server\nopen_hw_target\ncurrent_hw_device [lindex [get_hw_devices] 0]\nset_property PROBES.FILE {/home/jamey/connectal.clean/tests/spikehw/debug.ltx} [lindex [get_hw_devices] 0]\nset_property PROGRAM.FILE {/home/jamey/connectal.clean/tests/spikehw/debug.bit} [lindex [get_hw_devices] 0]\nrefresh_hw_device [lindex [get_hw_devices] 0]\n\n\nset_property TRIGGER_COMPARE_VALUE eq1'h0 [get_hw_probes tile_0_lSpikeHw_sda_t_probe_PROBE -of_objects [get_hw_ilas -of_objects [get_hw_devices xc7vx690t_0] -filter {CELL_NAME=~\"u_ila_0\"}]]\nset_property CONTROL.TRIGGER_MODE BASIC_ONLY [get_hw_ilas -of_objects [get_hw_devices xc7vx690t_0] -filter {CELL_NAME=~\"u_ila_0\"}]\nset_property CONTROL.TRIGGER_POSITION 1000 [get_hw_ilas -of_objects [get_hw_devices xc7vx690t_0] -filter {CELL_NAME=~\"u_ila_0\"}]\n#set_property CONTROL.DATA_DEPTH 131072 [get_hw_ilas -of_objects [get_hw_devices xc7vx690t_0] -filter {CELL_NAME=~\"u_ila_0\"}]\nrun_hw_ila [get_hw_ilas -of_objects [get_hw_devices xc7vx690t_0] -filter {CELL_NAME=~\"u_ila_0\"}]\nwait_on_hw_ila [get_hw_ilas -of_objects [get_hw_devices xc7vx690t_0] -filter {CELL_NAME=~\"u_ila_0\"}]\nupload_hw_ila_data [get_hw_ilas -of_objects [get_hw_devices xc7vx690t_0] -filter {CELL_NAME=~\"u_ila_0\"}]\nwrite_hw_ila_data -force debug.vcd -vcd_file [current_hw_ila_data]\n"
  },
  {
    "path": "tests/test_pmod/Controller.bsv",
    "content": "\n// Copyright (c) 2014 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\nimport Leds::*;\n\ninterface PmodPins;\n   method Bit#(8) pmod();\nendinterface\n\ninterface PmodControllerRequest;\n   method Action rst(Bit#(32) v);\nendinterface\n\ninterface PmodControllerIndication;\n   method Action rst(Bit#(32) v);\nendinterface\n\ninterface Controller;\n   interface PmodControllerRequest req;\n   interface PmodPins pins;\n   interface LEDS leds;\nendinterface\n\nmodule mkController#(PmodControllerIndication ind)(Controller);\n   \n   Reg#(Bit#(8)) data_reg <- mkReg(0);\n   Reg#(Bit#(8)) leds_reg <- mkReg(0);\n   Reg#(Bool)     rst_reg <- mkReg(False);\n   \n   rule count;\n      if (rst_reg) begin\n\t rst_reg <= False;\n\t data_reg <= 0;\n\t leds_reg <= data_reg;\n      end\n      else begin\n\t data_reg <= data_reg+1;\n      end\n   endrule\n   \n   interface PmodControllerRequest req;\n      method Action rst(Bit#(32) v);\n\t rst_reg <= True;\n\t ind.rst(v);\n      endmethod\n   endinterface\n   \n   interface PmodPins pins;\n      method Bit#(8) pmod() = data_reg._read;\n   endinterface\n   \n   interface LEDS leds;\n      method Bit#(LedsWidth) leds() = truncate(leds_reg);\n   endinterface\n\nendmodule\n"
  },
  {
    "path": "tests/test_pmod/Makefile",
    "content": "CONNECTALDIR ?= ../..\nINTERFACES = PmodControllerRequest PmodControllerIndication\n\nBSVFILES = Controller.bsv Top.bsv \nCPPFILES= testpmod.cpp\nPIN_TYPE = PmodPins\nPIN_TYPE_INCLUDE = Controller\nCONNECTALFLAGS = -C $(BOARD)/sources/pinout-$(BOARD).xdc\n\nPIN_BINDING ?= -b pmod:pmoda\n\ngentarget:: $(BOARD)/sources/pinout-$(BOARD).xdc\n$(BOARD)/sources/pinout-$(BOARD).xdc: pinout.json $(CONNECTALDIR)/boardinfo/$(BOARD).json\n\tmkdir -p $(BOARD)/sources\n\t$(CONNECTALDIR)/scripts/generate-constraints.py $(PIN_BINDING) -o $(BOARD)/sources/pinout-$(BOARD).xdc --boardfile $(CONNECTALDIR)/boardinfo/$(BOARD).json --pinoutfile pinout.json\n\ninclude $(CONNECTALDIR)/Makefile.connectal\n"
  },
  {
    "path": "tests/test_pmod/Top.bsv",
    "content": "\n// Copyright (c) 2014 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\nimport Vector::*;\nimport CtrlMux::*;\nimport Portal::*;\nimport ConnectalMemTypes::*;\nimport ConnectalConfig::*;\nimport PmodControllerRequest::*;\nimport PmodControllerIndication::*;\nimport Controller::*;\n\ntypedef enum {IfcNames_ControllerRequest, IfcNames_ControllerIndication} IfcNames deriving (Eq,Bits);\n\nmodule mkConnectalTop(ConnectalTop);\n   PmodControllerIndicationProxy cp <- mkPmodControllerIndicationProxy(IfcNames_ControllerIndication);\n   Controller controller <- mkController(cp.ifc);\n   PmodControllerRequestWrapper cw <- mkPmodControllerRequestWrapper(IfcNames_ControllerRequest, controller.req);\n   \n   Vector#(2,StdPortal) portals;\n   portals[0] = cp.portalIfc;\n   portals[1] = cw.portalIfc;\n   let ctrl_mux <- mkSlaveMux(portals);\n   \n   interface interrupt = getInterruptVector(portals);\n   interface slave = ctrl_mux;\n   interface masters = nil;\n   interface pins = controller.pins;\nendmodule : mkConnectalTop\n\nexport Controller::*;\nexport mkConnectalTop;\n"
  },
  {
    "path": "tests/test_pmod/pinout.json",
    "content": "{\n    \"pmod[0]\" : {\n\t\"PIO_DIRECTION\": \"OUTPUT\",\n\t\"pmod\" : \"J1\"\n    },\n    \"pmod[1]\" : {\n\t\"PIO_DIRECTION\": \"OUTPUT\",\n\t\"pmod\" : \"J2\"\n    },\n    \"pmod[2]\" : {\n\t\"PIO_DIRECTION\": \"OUTPUT\",\n\t\"pmod\" : \"J3\"\n    },\n    \"pmod[3]\" : {\n\t\"PIO_DIRECTION\": \"OUTPUT\",\n\t\"pmod\" : \"J4\"\n    },\n    \"pmod[4]\" : {\n\t\"PIO_DIRECTION\": \"OUTPUT\",\n\t\"pmod\" : \"J7\"\n    },\n    \"pmod[5]\" : {\n\t\"PIO_DIRECTION\": \"OUTPUT\",\n\t\"pmod\" : \"J8\"\n    },\n    \"pmod[6]\" : {\n\t\"PIO_DIRECTION\": \"OUTPUT\",\n\t\"pmod\" : \"J9\"\n    },\n    \"pmod[7]\" : {\n\t\"PIO_DIRECTION\": \"OUTPUT\",\n\t\"pmod\" : \"J10\"\n    }\n  }\n\n\n"
  },
  {
    "path": "tests/test_pmod/testpmod.cpp",
    "content": "\n#include <stdio.h>\n#include <stdlib.h>\n#include <unistd.h>\n#include <assert.h>\n#include <string.h>\n\n#include \"PmodControllerRequest.h\"\n#include \"PmodControllerIndication.h\"\n#include \"GeneratedTypes.h\"\n\n\nclass PmodControllerIndication : public PmodControllerIndicationWrapper\n{\npublic:\n  PmodControllerIndication(int id) : PmodControllerIndicationWrapper(id) {}\n  virtual void rst ( const uint32_t v ) {\n    fprintf(stderr, \"PmodControllerIndication::rst(%08x)\\n\", v);\n  }\n};\n\n\nint main(int argc, const char **argv)\n{\n  PmodControllerIndication *ind = new PmodControllerIndication(IfcNames_ControllerIndication);\n  PmodControllerRequestProxy *device = new PmodControllerRequestProxy(IfcNames_ControllerRequest);\n\n  for(int i = 0; i < 10; i++) {\n    device->rst(i);\n    sleep(1);\n  }\n}\n"
  },
  {
    "path": "tests/test_sdio1/Makefile",
    "content": "CONNECTALDIR ?= ../..\nINTERFACES = SDIORequest SDIOResponse\n\nBSVFILES = Top.bsv SDIO.bsv\nCPPFILES= test_sdio1.cpp\nCONNECTALFLAGS += -D PS7EXTENDED -D IMPORT_HOSTIF\n\nPIN_TYPE = TestSDIO1Pins\nPIN_TYPE_INCLUDE = SDIO\nPINOUT_FILE = pinout.json\nPIN_BINDINGS = pmod:pmodd\n\ninclude $(CONNECTALDIR)/Makefile.connectal\n"
  },
  {
    "path": "tests/test_sdio1/SDIO.bsv",
    "content": "\n// Copyright (c) 2014 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\nimport Vector::*;\nimport ConnectalXilinxCells::*;\nimport PPS7LIB::*;\nimport FrequencyCounter::*;\nimport ConnectalClocks::*;\nimport XilinxCells::*;\nimport Clocks::*;\n\n(* always_ready, always_enabled *)\ninterface SDIOPins;\n   method Bit#(1) clk;\n   interface Inout#(Bit#(1)) cmd;\n   interface Inout#(Bit#(1)) d0;\n   interface Inout#(Bit#(1)) d1;\n   interface Inout#(Bit#(1)) d2;\n   interface Inout#(Bit#(1)) d3;\n   method Action cdn(Bit#(1) v);\n   method Action wp(Bit#(1) v);\nendinterface\n\ninterface SDIORequest;\n   method Action cnt_cycle_req(Bit#(32) v);\n   method Action set_spew_en(Bit#(1) v);\n   method Action toggle_cd(Bit#(32) v);\nendinterface\n\ninterface SDIOResponse;\n   method Action cnt_cycle_resp(Bit#(32) v);\n   method Action emio_sample(Bit#(32) v);\nendinterface\n\ninterface Controller;\n   interface SDIOPins pins;\n   interface SDIORequest req;\nendinterface\n\nmodule mkController#(SDIOResponse ind, Pps7Emiosdio sdio)(Controller);\n   \n   B2C1 b2c <- mkB2C1();\n   Clock sdio_clk <- mkClockBUFG(clocked_by b2c.c);\n   rule tx_sdio_clk;\n      b2c.inputclock(sdio.clk);\n   endrule\n   Reset def_rst <- exposeCurrentReset();\n   Reset sdio_rst <- mkAsyncReset(2, def_rst, sdio_clk);\n   FrequencyCounter fc <- mkFrequencyCounter(sdio_clk, sdio_rst);\n\n   Reg#(Bit#(1)) spew_en <- mkReg(0);\n   let cmdb <- mkIOBUF(sdio.cmdtn,     sdio.cmdo);\n   let d0b  <- mkIOBUF(sdio.datatn[0], sdio.datao[0]);\n   let d1b  <- mkIOBUF(sdio.datatn[1], sdio.datao[1]);\n   let d2b  <- mkIOBUF(sdio.datatn[2], sdio.datao[2]);\n   let d3b  <- mkIOBUF(sdio.datatn[3], sdio.datao[3]);\n   Reg#(Bit#(32)) toggle_cd_reg <- mkReg(0);\n   \n   Bit#(4) db_o = {d3b.o,d2b.o,d1b.o,d0b.o};\n   Bit#(1) cmdb_o = cmdb.o;\n   \n   (* fire_when_enabled, no_implicit_conditions *)\n   rule xxx;\n      sdio.cmdi(cmdb_o);\n      sdio.datai(db_o);\n      sdio.clkfb(sdio.clk);\n   endrule\n   \n   rule emio_sample_rule if (spew_en == 1);\n      ind.emio_sample({0, db_o, sdio.datatn, sdio.datao, cmdb_o, sdio.cmdtn, sdio.cmdo, sdio.clk});\n   endrule\n   \n   rule cnt_cycle_resp_rule;\n      let v <- fc.elapsedCycles;\n      ind.cnt_cycle_resp(v);\n   endrule\n   \n   rule decr_toggle_cd_reg (toggle_cd_reg > 0);\n\t toggle_cd_reg <= toggle_cd_reg-1;\n   endrule\n   \n   interface SDIORequest req;\n      method Action cnt_cycle_req(Bit#(32) v);\n\t fc.start(v);\n      endmethod\n      method Action set_spew_en(Bit#(1) v);\n\t spew_en <= v;\n      endmethod\n      method Action toggle_cd(Bit#(32) v);\n\t toggle_cd_reg <= v;\n      endmethod\n   endinterface\n   \n   interface SDIOPins pins;\n      method Bit#(1) clk = sdio.clk;\n      interface cmd = cmdb.io;\n      interface d0 = d0b.io;\n      interface d1 = d1b.io;\n      interface d2 = d2b.io;\n      interface d3 = d3b.io;\n      method Action cdn(Bit#(1) v) = sdio.cdn((toggle_cd_reg > 0) ? ~v : v);\n      method Action wp(Bit#(1) v) = sdio.wp(v);\n   endinterface\n\nendmodule\n\n\n"
  },
  {
    "path": "tests/test_sdio1/Top.bsv",
    "content": "\n// Copyright (c) 2014 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\nimport ConnectalConfig::*;\nimport HostInterface::*;\nimport Vector::*;\nimport CtrlMux::*;\nimport Portal::*;\nimport ConnectalMemTypes::*;\nimport SDIORequest::*;\nimport SDIOResponse::*;\nimport SDIO::*;\nimport Leds::*;\nimport PS7LIB::*;\n\ntypedef enum {IfcNames_ControllerRequest, IfcNames_ControllerResponse} IfcNames deriving (Eq,Bits);\n\ninterface TestSDIO1Pins;\n   interface SDIOPins sdio;\n   interface LEDS leds;\nendinterface\n\nmodule mkConnectalTop#(HostInterface host)(ConnectalTop);\n\n   SDIOResponseProxy cp <- mkSDIOResponseProxy(IfcNames_ControllerResponse);\n   Controller controller <- mkController(cp.ifc, host.ps7.emiosdio1);\n   SDIORequestWrapper cw <- mkSDIORequestWrapper(IfcNames_ControllerRequest, controller.req);\n   \n   Vector#(2,StdPortal) portals;\n   portals[0] = cp.portalIfc;\n   portals[1] = cw.portalIfc;\n   let ctrl_mux <- mkSlaveMux(portals);\n   \n   interface interrupt = getInterruptVector(portals);\n   interface slave = ctrl_mux;\n   interface masters = nil;\n   interface TestSDIO1Pins pins;\n      interface sdio = controller.pins;\n      interface leds = ?;\n   endinterface\n\nendmodule : mkConnectalTop\n\nexport TestSDIO1Pins;\nexport mkConnectalTop;\n\n"
  },
  {
    "path": "tests/test_sdio1/pinout.json",
    "content": "{\n    \"sdio_clk\" : { \n\t\"PIO_DIRECTION\": \"OUTPUT\",\n\t\"pmod\" : \"J4\"\n    },\n    \"sdio_cdn_v\" : { \n\t\"PIO_DIRECTION\": \"INPUT\",\n\t\"pmod\" : \"J9\"\n    },\n    \"sdio_wp_v\" : { \n\t\"PIO_DIRECTION\": \"INPUT\",\n\t\"pmod\" : \"J10\"\n    },\n    \"sdio_cmd\" : { \n\t\"PIO_DIRECTION\": \"BIDIR\",\n\t\"pmod\" : \"J2\"\n    },\n    \"sdio_d0\" : { \n\t\"PIO_DIRECTION\": \"BIDIR\",\n\t\"pmod\" : \"J3\"\n    },\n    \"sdio_d1\" : { \n\t\"PIO_DIRECTION\": \"BIDIR\",\n\t\"pmod\" : \"J7\"\n    },\n    \"sdio_d2\" : { \n\t\"PIO_DIRECTION\": \"BIDIR\",\n\t\"pmod\" : \"J8\"\n    },\n    \"sdio_d3\" : { \n\t\"PIO_DIRECTION\": \"BIDIR\",\n\t\"pmod\" : \"J1\"\n    },\n    \"leds_leds[0]\" : {\n\t\"PIO_DIRECTION\": \"OUTPUT\",\n\t\"leds\" : \"L0\"\n    },\n    \"leds_leds[1]\" : {\n\t\"PIO_DIRECTION\": \"OUTPUT\",\n\t\"leds\" : \"L1\"\n    },\n    \"leds_leds[2]\" : {\n\t\"PIO_DIRECTION\": \"OUTPUT\",\n\t\"leds\" : \"L2\"\n    },\n    \"leds_leds[3]\" : {\n\t\"PIO_DIRECTION\": \"OUTPUT\",\n\t\"leds\" : \"L3\"\n    },\n    \"leds_leds[4]\" : {\n\t\"PIO_DIRECTION\": \"OUTPUT\",\n\t\"leds\" : \"L4\"\n    },\n    \"leds_leds[5]\" : {\n\t\"PIO_DIRECTION\": \"OUTPUT\",\n\t\"leds\" : \"L5\"\n    },\n    \"leds_leds[6]\" : {\n\t\"PIO_DIRECTION\": \"OUTPUT\",\n\t\"leds\" : \"L6\"\n    },\n    \"leds_leds[7]\" : {\n\t\"PIO_DIRECTION\": \"OUTPUT\",\n\t\"leds\" : \"L7\"\n    }\n\n}\n\n\n"
  },
  {
    "path": "tests/test_sdio1/test_sdio1.cpp",
    "content": "\n// Copyright (c) 2014 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\n\n#include <stdio.h>\n#include <stdlib.h>\n#include <unistd.h>\n#include <assert.h>\n#include <string.h>\n\n#include \"SDIORequest.h\"\n#include \"SDIOResponse.h\"\n\n\nuint32_t bit_sel(uint32_t lsb, uint32_t msb, uint32_t v)\n{\n  return (v >> lsb) & ~(~0 << (msb-lsb+1));\n}\n\nclass SDIOResponse : public SDIOResponseWrapper\n{\npublic:\n  virtual void read_resp(uint8_t v){\n    fprintf(stderr, \"read_resp cd:%d wp:%d\\n\", (v&2)>>1, v&1);\n  }\n  virtual void emio_sample(uint32_t v){\n    int clk = bit_sel(0,0,v);\n    int cmdo = bit_sel(1,1,v);\n    int cmdtn = bit_sel(2,2,v);\n    int cmdi = bit_sel(3,3,v);\n    int datao = bit_sel(4,7,v);\n    int datatn = bit_sel(8,11,v);\n    int datai = bit_sel(12,15,v);\n    fprintf(stderr, \"emio_sample(%08x): datai:%X datatn:%X datao:%X cmdi:%X, cmdtn:%X, cmdo:%X, clk:%X\\n\", v, datai, datatn, datao, cmdi, cmdtn, cmdo, clk);\n  }\n  virtual void cnt_cycle_resp(uint32_t v){\n    fprintf(stderr, \"cnt_cycle_resp %d\\n\", v);\n  } \n  SDIOResponse(unsigned int id) : SDIOResponseWrapper(id){}\n};\n\n\nint main(int argc, const char **argv)\n{\n  SDIORequestProxy *device = new SDIORequestProxy(IfcNames_ControllerRequest);\n  SDIOResponse *ind = new SDIOResponse(IfcNames_ControllerResponse);\n\n  //sleep(2);\n  // device->toggle_cd(1000);\n  // device->set_spew_en(1);\n  // while(true){\n  //   device->cnt_cycle_req(100);\n  //   sleep(2);\n  // }\n\n}\n"
  },
  {
    "path": "tests/test_spi0/Makefile",
    "content": "CONNECTALDIR ?= ../..\nINTERFACES = SPIRequest SPIResponse\n\nBSVFILES = Top.bsv SPI.bsv\nCPPFILES= test_spi0.cpp\nCONNECTALFLAGS += -D PS7EXTENDED -D IMPORT_HOSTIF\n\ninclude $(CONNECTALDIR)/Makefile.connectal\n"
  },
  {
    "path": "tests/test_spi0/SPI.bsv",
    "content": "\n// Copyright (c) 2015 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\nimport Vector::*;\nimport ConnectalXilinxCells::*;\nimport PPS7LIB::*;\nimport FrequencyCounter::*;\nimport ConnectalClocks::*;\nimport XilinxCells::*;\nimport Clocks::*;\nimport BRAMFIFO::*;\nimport FIFOF::*;\n\n\ntypedef struct {\n   Bit#(1)  mo;\n   Bit#(1)  motn;\n   Bit#(3)  sson;\n   Bit#(1)  ssntn;\n   Bit#(1)  sclko;\n   Bit#(1)  sclktn;\n   Bit#(16) cnt;   \n   } Spew deriving (Eq,Bits);\n\ntypedef struct {\n   Bit#(1)  clk_sel;\n   Bit#(32) clk_cnt;\n   } CycleReq deriving (Eq,Bits);\n\ninterface SPIRequest;\n   method Action cnt_cycle_req(CycleReq v);\n   method Action set_spew_en(Bit#(32) v);\n   method Action set_clk_inv(Bit#(1) v);\n   method Action set_spew_src(Bit#(1) v);\nendinterface\n\ninterface SPIResponse;\n   method Action cnt_cycle_resp(Bit#(32) v);\n   method Action emio_sample(Spew v);\n   method Action spi_word(Bit#(32) v);\nendinterface\n\ninterface Controller;\n   interface SPIRequest req;\nendinterface\n\nmodule mkController#(SPIResponse ind, Pps7Emiospi spi)(Controller);\n   \n   B2C1 sclko_b2c <- mkB2C1();\n   Clock def_clk <- exposeCurrentClock;\n   Clock spi_clk <- mkClockBUFG(clocked_by sclko_b2c.c);\n   Reset spi_rst <- mkAsyncResetFromCR(2, spi_clk);   \n\n   Reg#(Bit#(32)) shift_reg <- mkReg(0, clocked_by spi_clk, reset_by spi_rst);\n   Reg#(Bit#(5))  spi_cnt_reg <- mkReg(0, clocked_by spi_clk, reset_by spi_rst);\n\n   ReadOnly#(Bit#(1)) mo_sync     <- mkNullCrossingWire(spi_clk, spi.mo);\n   ReadOnly#(Bit#(1)) motn_sync   <- mkNullCrossingWire(spi_clk, spi.motn);\n   ReadOnly#(Bit#(3)) sson_sync   <- mkNullCrossingWire(spi_clk, spi.sson);\n   ReadOnly#(Bit#(1)) ssntn_sync  <- mkNullCrossingWire(spi_clk, spi.ssntn);\n   ReadOnly#(Bit#(1)) sclko_sync  <- mkNullCrossingWire(spi_clk, spi.sclko);\n   ReadOnly#(Bit#(1)) sclktn_sync <- mkNullCrossingWire(spi_clk, spi.sclktn);\n   ReadOnly#(Bit#(1)) miso_sync   <- mkNullCrossingWire(def_clk, shift_reg[31]);\n   \n   Reg#(Bit#(1)) spew_src <- mkReg(0);\n   Reg#(Bit#(1)) clk_inv <- mkReg(0);\n   Reg#(Bit#(16)) def_cnt_reg <- mkReg(0);\n   Reg#(Bit#(32)) spew_en <- mkReg(0);\n   Reg#(Bit#(32)) spew_cyc <- mkReg(0);\n   FrequencyCounter spi_clk_fc <- mkFrequencyCounter(spi_clk, spi_rst);\n   SyncFIFOIfc#(Bit#(32)) req_fifo <- mkSyncFIFOToCC(2, spi_clk, spi_rst);\n   SyncFIFOIfc#(Spew) spew_fifo <- mkSyncBRAMFIFOToCC(128, spi_clk, spi_rst);\n\n   (* fire_when_enabled *)\n   rule connect_to_ps7;\n      sclko_b2c.inputclock(clk_inv ^ spi.sclko);\n      spi.mi(miso_sync);\n      spi.sclki(0);\n      spi.si(0);\n      spi.ssin(1);\n   endrule\n   \n   (* fire_when_enabled *)\n   rule def_cnt_rule if (~spi.sclktn==1 && ~spi.motn==1);\n      def_cnt_reg <= def_cnt_reg+1;\n   endrule\n      \n   rule mosi_rule if (sson_sync[0] == 0);\n      shift_reg <= {shift_reg[30:0],mo_sync};\n      spi_cnt_reg <= spi_cnt_reg+1;\n      if (spi_cnt_reg == 0) req_fifo.enq(shift_reg);\n   endrule\n\n   rule cnt_cycle_resp_rule_a;\n      let v <- spi_clk_fc.elapsedCycles;\n      ind.cnt_cycle_resp(v);\n   endrule\n\n   rule drain_req_fifo;\n      ind.spi_word(req_fifo.first);\n      req_fifo.deq;\n   endrule\n   \n   rule emio_sample_rule_a;\n      spew_fifo.enq(Spew{mo:mo_sync,\n\t\t\t motn:motn_sync,\n\t\t\t sson:sson_sync,\n\t\t\t ssntn:ssntn_sync, \n\t\t\t sclko:sclko_sync,\n\t\t\t sclktn:sclktn_sync, \n\t\t\t cnt:extend(spi_cnt_reg)});\n   endrule\n\n   rule emio_sample_rule_b if (spew_en > 0);\n      if (spew_cyc+1 == spew_en) begin\n\t spew_cyc <= 0;\n\t if (spew_src == 1) begin\n\t    ind.emio_sample(Spew{mo:spi.mo, \n\t\t\t\t motn:spi.motn, \n\t\t\t\t sson:spi.sson, \n\t\t\t\t ssntn:spi.ssntn, \n\t\t\t\t sclko:spi.sclko, \n\t\t\t\t sclktn:spi.sclktn, \n\t\t\t\t cnt:def_cnt_reg});\n\t end\n\t else begin\n\t    ind.emio_sample(spew_fifo.first);\n\t    spew_fifo.deq;\n\t end\n      end\n      else begin\n\t spew_cyc <= spew_cyc+1;\n      end\n   endrule\n   \n   interface SPIRequest req;\n      method Action cnt_cycle_req(CycleReq v);\n\t spi_clk_fc.start(v.clk_cnt);\n      endmethod\n      method Action set_spew_en(Bit#(32) v);\n\t spew_en <= v;\n      endmethod\n      method Action set_clk_inv(Bit#(1) v);\n\t clk_inv <= v;\n      endmethod\n      method Action set_spew_src(Bit#(1) v);\n\t spew_src <= v;\n      endmethod\n   endinterface\n\nendmodule\n\n\n"
  },
  {
    "path": "tests/test_spi0/Top.bsv",
    "content": "\n// Copyright (c) 2015 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\nimport ConnectalConfig::*;\nimport HostInterface::*;\nimport Vector::*;\nimport CtrlMux::*;\nimport Portal::*;\nimport ConnectalMemTypes::*;\nimport Leds::*;\nimport PS7LIB::*;\nimport SPI::*;\nimport SPIRequest::*;\nimport SPIResponse::*;\n\ntypedef enum {IfcNames_ControllerRequest, IfcNames_ControllerResponse} IfcNames deriving (Eq,Bits);\n\nmodule mkConnectalTop#(HostInterface host)(ConnectalTop);\n\n   SPIResponseProxy cp <- mkSPIResponseProxy(IfcNames_ControllerResponse);\n   Controller controller <- mkController(cp.ifc, host.ps7.emiospi0);\n   SPIRequestWrapper cw <- mkSPIRequestWrapper(IfcNames_ControllerRequest, controller.req);\n   \n   Vector#(2,StdPortal) portals;\n   portals[0] = cp.portalIfc;\n   portals[1] = cw.portalIfc;\n   let ctrl_mux <- mkSlaveMux(portals);\n   \n   interface interrupt = getInterruptVector(portals);\n   interface slave = ctrl_mux;\n   interface masters = nil;\nendmodule : mkConnectalTop\nexport mkConnectalTop;\n"
  },
  {
    "path": "tests/test_spi0/foo.cpp",
    "content": "\n#include \"ImageCapture.h\"\n#include <stdio.h>\n#include <sys/mman.h>\n#include <stdlib.h>\n#include <string.h>\n#include <stdarg.h>\n#include <unistd.h>\n#include <stdint.h>\n#include <fcntl.h>\n#include <pthread.h>\n#include <semaphore.h>\n#include \"i2chdmi.h\"\n#include \"i2ccamera.h\"\n#include \"/usr/include/linux/spi/spidev.h\"\n\n#define SPIDEVICENAME \"/dev/spidev2.0\"\n\nstatic ImageCapture *device = 0;\n\n#define DECL(A) \\\n    static sem_t sem_ ## A; \\\n    static unsigned long cv_ ## A;\n\nDECL(iserdes_control)\nDECL(decoder_control)\nDECL(crc_control)\nDECL(crc_status)\nDECL(remapper_control)\nDECL(triggen_control)\nDECL(clock_gen_locked)\n\n#define RXFN(A) \\\n    virtual void A ## _value ( unsigned long v ){ \\\n        cv_ ## A = v; \\\n        sem_post(&sem_ ## A); \\\n    }\n\n#define GETFN(A) \\\n    static unsigned long read_ ## A (void) \\\n    { \\\n        device->get_ ## A(); \\\n        sem_wait(&sem_ ## A); \\\n        return cv_ ## A; \\\n    }\n\nclass TestImageCaptureIndications : public ImageCaptureIndications {\n    void spi_trace_sample_count_value(long unsigned int) {\nprintf(\"[%s:%d]\\n\", __FUNCTION__, __LINE__);\n    }\n    void spi_trace_sample_value(long long unsigned int) {\nprintf(\"[%s:%d]\\n\", __FUNCTION__, __LINE__);\n    }\n    void spi_control_value(long unsigned int) {\nprintf(\"[%s:%d]\\n\", __FUNCTION__, __LINE__);\n    }\n    void spi_rxfifo_value(long unsigned int) {\nprintf(\"[%s:%d]\\n\", __FUNCTION__, __LINE__);\n    }\n    RXFN(iserdes_control)\n    RXFN(decoder_control)\n    RXFN(crc_control)\n    RXFN(crc_status)\n    RXFN(remapper_control)\n    RXFN(triggen_control)\n    RXFN(clock_gen_locked)\n    void putFailed(unsigned long v){\n      fprintf(stderr, \"putFailed: %x\\n\", v);\n      exit(1);\n    }\n    void debugind(long unsigned int v) {\nprintf(\"[%s:%d] valu %lx\\n\", __FUNCTION__, __LINE__, v);\n    }\n};\n\nstatic void init_local_semaphores(void)\n{\n    sem_init(&sem_iserdes_control, 0, 0);\n    sem_init(&sem_decoder_control, 0, 0);\n    sem_init(&sem_crc_control, 0, 0);\n    sem_init(&sem_remapper_control, 0, 0);\n    sem_init(&sem_triggen_control, 0, 0);\n    sem_init(&sem_crc_status, 0, 0);\n    sem_init(&sem_clock_gen_locked, 0, 0);\n}\nGETFN(iserdes_control)\nGETFN(decoder_control)\nGETFN(crc_control)\nGETFN(crc_status)\nGETFN(remapper_control)\nGETFN(triggen_control)\nGETFN(clock_gen_locked)\n\n//#define VITA_ISERDES_CONTROL_REG     0x0010\n   #define VITA_ISERDES_RESET_BIT       0x0001\n   #define VITA_ISERDES_AUTO_ALIGN_BIT  0x0002\n   #define VITA_ISERDES_ALIGN_START_BIT 0x0004\n   #define VITA_ISERDES_FIFO_ENABLE_BIT 0x0008\n//#define VITA_DECODER_CONTROL_REG           0x0020\n   #define VITA_DECODER_RESET_BIT            0x0001\n   #define VITA_DECODER_ENABLE_BIT           0x0002\n//#define VITA_CRC_CONTROL_REG               0x0070\n   #define VITA_CRC_RESET_BIT              0x0001\n   #define VITA_CRC_INITVALUE_BIT          0x0002\n//#define VITA_CRC_STATUS_REG                0x0074\n\nstatic uint32_t uManualTap;\nstatic struct {\n   // Sync Channel Decoder status\n   uint32_t cntBlackLines;\n   uint32_t cntImageLines;\n   uint32_t cntBlackPixels;\n   uint32_t cntImagePixels;\n   uint32_t cntFrames;\n   uint32_t cntWindows;\n   uint32_t cntStartLines;\n   uint32_t cntEndLines;\n   uint32_t cntClocks;\n   uint32_t crcStatus;\n} vita_status_t2;\n\n#define VITA_SPI_SEQ1_QTY  8\n/* Table 6. enable clock management register upload - part 1 */\nstatic uint16_t vita_spi_seq1[VITA_SPI_SEQ1_QTY][3] = {\n   // Enable Clock Management - Part 1\n   //    V1/SN/SE 10-bit mode with PLL\n   {  2, 0xFFFF,      0}, // Monochrome Sensor\n// {  2, 0xFFFF, 0x0001}, // Color Sensor\n   { 32, 0xFFFF, 0x2004}, // Configure clock management\n   { 20, 0xFFFF,      0}, // Configure clock management\n   { 17, 0xFFFF, 0x2113}, // Configure PLL\n   { 26, 0xFFFF, 0x2280}, // Configure PLL lock detector\n   { 27, 0xFFFF, 0x3D2D}, // Configure PLL lock detector\n   {  8, 0xFFFF,      0}, // Release PLL soft reset\n   { 16, 0xFFFF, 0x0003}  // Enable PLL\n};\n\n#define VITA_SPI_SEQ3_QTY  3\n/* Table 7. enable clock management register upload - part 2 */\nstatic uint16_t vita_spi_seq3[VITA_SPI_SEQ3_QTY][3] = {\n   // Enable Clock Management - Part 2\n   //    V1/SN/SE 10-bit mode with PLL\n   {  9, 0xFFFF,      0}, // Release clock generator soft reset\n   { 32, 0xFFFF, 0x2006}, // Enable logic clock\n   { 34, 0xFFFF, 0x0001}  // Enable logic blocks\n};\n\n#define VITA_SPI_SEQ4_QTY  17\n/* Table 8. required register upload */\nstatic uint16_t vita_spi_seq4[VITA_SPI_SEQ4_QTY][3] = {\n   // Required Register Upload\n   //    V1/SN/SE 10-bit mode with PLL\n   { 41, 0xFFFF,      0}, // Configure image core\n   {129, 0x2000,      0}, // [13] 10-bit mode\n   { 65, 0xFFFF, 0x288B}, // Configure CP biasing\n   { 66, 0xFFFF, 0x53C6}, // Configure AFE biasing\n   { 67, 0xFFFF, 0x0344}, // Configure MUX biasing\n   { 68, 0xFFFF, 0x0085}, // Configure LVDS biasing\n   { 70, 0xFFFF, 0x4888}, // Configure reserved register\n   { 81, 0xFFFF, 0x86A1}, // Configure reserved register\n   {128, 0xFFFF, 0x460F}, // Configure  calibration\n   {176, 0xFFFF, 0x00F5}, // Configure AEC\n   {180, 0xFFFF, 0x00FD}, // Configure AEC\n   {181, 0xFFFF, 0x0144}, // Configure AEC\n   {194, 0xFFFF, 0x0404}, // Configure sequencer\n   {218, 0xFFFF, 0x160B}, // Configure sequencer\n   {224, 0xFFFF, 0x3E13}, // Configure sequencer\n   {391, 0xFFFF, 0x1010}, // Configure sequencer\n   {456, 0xFFFF, 0x0386}  // Configure sequencer\n};\n\n#define VITA_SPI_SEQ5_QTY  7\n/* Table 9. soft power up register uploads for mode dependent registers */\nstatic uint16_t vita_spi_seq5[VITA_SPI_SEQ5_QTY][3] = {\n   // Soft Power-Up\n   //    V1/SN/SE 10-bit mode with PLL\n   { 32, 0xFFFF, 0x2007}, // Enable analog clock distribution\n   { 10, 0xFFFF,      0}, // Release soft reset state\n   { 64, 0xFFFF, 0x0001}, // Enable biasing block\n   { 72, 0xFFFF, 0x0203}, // Enable charge pump\n   { 40, 0xFFFF, 0x0003}, // Enable column multiplexer\n   { 48, 0xFFFF, 0x0001}, // Enable AFE\n   {112, 0xFFFF, 0x0007}  // Enable LVDS transmitters\n};\n\n//#define VITA_SPI_SEQ6_QTY  1\n#define VITA_SPI_SEQ6_QTY  2\n/* Table 10. enable sequencer register upload */\nstatic uint16_t vita_spi_seq6[VITA_SPI_SEQ6_QTY][3] = {\n// {192, 0x0001, 0x0001}  // [0] Enable Sequencer\n#if defined(TRIGGERED_MASTER_MODE)\n   {192, 0x0051, 0x0011}, // [0] Enable Sequencer\n                          // [4] triggered_mode = on\n                          // [6] xsm_delay_enable = off\n   {193, 0xFF00,      0}  // [15:8] xsm_delay = 0x00\n#elif defined(STRETCH_VITA_HTIMING)\n   {192, 0x3841, 0x3841},\n// {192, 0x0041, 0x0041}, // [0] Enable Sequencer\n                          // [6] xsm_delay_enable = on\n   {193, 0xFF00, 0x0400}  // [15:8] xsm_delay = 0x04\n#else\n   {192, 0x0001, 0x0001}, // [0] Enable Sequencer\n                        // [6] xsm_delay_enable = off\n   {193, 0xFF00,      0}  // [15:8] xsm_delay = 0x00\n#endif\n};\n\n#define VITA_AUTOEXP_ON_QTY  1\nstatic uint16_t vita_autoexp_on_seq[VITA_AUTOEXP_ON_QTY][3] = {\n   // Auto-Exposure ON\n   {160, 0x0001, 0x0001} // [4] Auto Exposure enable\n   };\n\n#define VITA_ROI0_CROP_1080P_QTY  2\nstatic uint16_t vita_roi0_crop_1080p_seq[VITA_ROI0_CROP_1080P_QTY][3] = {\n   // Crop ROI0 from 1920x1200 to 1920x1080\n   //   R257[10:0] y_start = 60 (0x3C)\n   //   R258[10:0] y_end   = 60+1080 = 1140 (0x474)\n   {257, 0xFFFF, 0x003C},\n   {258, 0xFFFF, 0x0474} };\n\n#define VITA_MULT_TIMER_LINE_RESOLUTION_QTY  1\nstatic uint16_t vita_mult_timer_line_resolution_seq[VITA_MULT_TIMER_LINE_RESOLUTION_QTY][3] = {\n   // R199[15:0] mult_timer = (1920+88+44+148)/4 = 2200/4 = 550 (0x0226)\n   //199, 0xFFFF, 0x0226\n   // R199[15:0] mult_timer = (1920+88+44+132)/4 = 2184/4 = 546 (0x0222)\n   {199, 0xFFFF, 0x0222} };\n\n/************************ SPI ******************************/\nstatic int spidevicefd;\nstatic uint8_t spimode = 0;\nstatic uint8_t spibits = 8;\nstatic uint32_t speed = 50000;\nstatic uint16_t delay = 100;\nstatic uint16_t zynq_spi(uint32_t addr, uint32_t data)\n{\n    unsigned int ii;\n    uint8_t tx[sizeof(uint32_t)], rx[sizeof(uint32_t)];\n    uint32_t retval = 0;\n    static struct spi_ioc_transfer tr;\n    uint32_t command = addr << 23 | (data << 6);\n//printf(\"[%s:%d] addr %x data %x command %x\\n\", __FUNCTION__, __LINE__, addr, data, command);\n\n    for (ii = 0; ii < sizeof(uint32_t); ii++) {\n        tx[3-ii] = command;\n        command >>= 8;\n    }\n    tr.tx_buf = (unsigned long)tx;\n    tr.rx_buf = (unsigned long)rx;\n    tr.len = sizeof(tx);\n    tr.delay_usecs = delay;\n    tr.speed_hz = speed;\n    tr.bits_per_word = spibits;\n    if (ioctl(spidevicefd, SPI_IOC_MESSAGE(1), &tr) < 1)\n        printf(\"can't send spi message\\n\");\n    for (ii = 0; ii < sizeof(uint32_t); ii++)\n        retval = retval << 8 | rx[ii];\n    return (retval >> 5) & 0xffff;\n}\nstatic uint16_t vita_spi_read(uint32_t uAddr)\n{\n    return zynq_spi(uAddr, 0);\n}\nstatic int vita_spi_write(uint32_t uAddr, uint16_t uData)\n{\n    zynq_spi(uAddr, 0x10000 | uData);\n    return 0;\n}\n\n/******************************************************************************\n* This function performs a sequence of SPI write transactions.\n******************************************************************************/\nstatic void vita_spi_write_sequence(uint16_t pConfig[][3], uint32_t uLength)\n{\n   uint16_t uData;\n   int i;\n\n   for ( i = 0; i < (int)uLength; i++) {\n      if ( pConfig[i][1] != 0xFFFF) {\n         uData = vita_spi_read(pConfig[i][0]) & ~pConfig[i][1];\n         printf( \"\\t                    0x%04X\\n\\r\", pConfig[i][1]);\n     }\n   }\n   for ( i = 0; i < (int)uLength; i++) {\n      if ( pConfig[i][1] == 0xFFFF)\n         uData = pConfig[i][2];\n      else {\n         uData = vita_spi_read(pConfig[i][0]) & ~pConfig[i][1];\n         uData |=  pConfig[i][2];\n      }\n      vita_spi_write(pConfig[i][0], uData); usleep(100); // 100 usec\n   }\n}\n\nstatic int fmc_imageon_vita_receiver_get_status(void)\n{\n   sleep(1);\n   //vita_status_t2.cntBlackLines  = vita_reg_read(VITA_DECODER_CNT_BLACK_LINES_REG);\n   //vita_status_t2.cntImageLines  = vita_reg_read(VITA_DECODER_CNT_IMAGE_LINES_REG);\n   //vita_status_t2.cntBlackPixels = vita_reg_read(VITA_DECODER_CNT_BLACK_PIXELS_REG);\n   //vita_status_t2.cntImagePixels = vita_reg_read(VITA_DECODER_CNT_IMAGE_PIXELS_REG);\n   //vita_status_t2.cntFrames      = vita_reg_read(VITA_DECODER_CNT_FRAMES_REG);\n   //vita_status_t2.cntWindows     = vita_reg_read(VITA_DECODER_CNT_WINDOWS_REG);\n   //vita_status_t2.cntStartLines  = vita_reg_read(VITA_DECODER_CNT_START_LINES_REG);\n   //vita_status_t2.cntEndLines    = vita_reg_read(VITA_DECODER_CNT_END_LINES_REG);\n   //vita_status_t2.cntClocks      = vita_reg_read(VITA_DECODER_CNT_CLOCKS_REG);\n   //vita_status_t2.crcStatus = read_crc_status();\n   return 0;\n}\n\nstatic struct {\n    const char *pName;\n    uint32_t VActiveVideo;\n    uint32_t VFrontPorch;\n    uint32_t VSyncWidth;\n    uint32_t VBackPorch;\n    uint32_t VSyncPolarity;\n    uint32_t HActiveVideo;\n    uint32_t HFrontPorch;\n    uint32_t HSyncWidth;\n    uint32_t HBackPorch;\n    uint32_t HSyncPolarity;\n} vres = {\n   \"1080P\", 1080,    4,    5,   36,    1, 1920,   88,   44,  148,    1 // VIDEO_RESOLUTION_1080P\n};\n\nstatic void fmc_imageon_demo_enable_ipipe( void)\n{\n   // VITA-2000 Initialization\n   printf( \"FMC-IMAGEON VITA Initialization ...\\n\\r\");\n   uint16_t uData;\n   uint32_t uStatus;\n   int timeout;\n   uint32_t h_active    = 1920;\n   uint32_t h_fporch    =   88;\n   uint32_t h_syncwidth =   44;\n #if defined(STRETCH_VITA_HTIMING)\n   uint32_t h_bporch    =  148;\n #else\n   uint32_t h_bporch    =  132;\n #endif\n   uint32_t h_syncpol   =    1;\n   //v_active    = 1080;\n   uint32_t v_active    = 1080+1;\n   uint32_t v_fporch    =    4;\n   uint32_t v_syncwidth =    5;\n   //v_bporch    =   36;\n   uint32_t v_bporch    =  300;\n   uint32_t v_syncpol   =    1;\n   // Horizontal settings\n   device->set_syncgen_delay(((1920+88+44+148)>>2)*6); // approx. 6 lines of delay\n   device->set_syncgen_hactive(h_active);\n   device->set_syncgen_hfporch(h_fporch);\n   device->set_syncgen_hsync((h_syncpol)<<15 | (h_syncwidth)<<0);\n   device->set_syncgen_hbporch(h_bporch);\n   // Vertical settings\n   device->set_syncgen_vactive(v_active);\n   device->set_syncgen_vfporch(v_fporch);\n   device->set_syncgen_vsync ((v_syncpol)<<15 | (v_syncwidth)<<0);\n   device->set_syncgen_vbporch(v_bporch);\n   printf( \"VITA ISERDES - Setting Training Sequence to 0x03A6\\n\\r\");\n   device->set_serdes_training(0x03A6);\n   printf( \"VITA ISERDES - Setting Manual Tap to 0x%08X\\n\\r\", uManualTap);\n   device->set_serdes_manual_tap(uManualTap);\n   device->set_decoder_startoddeven(0);\n   device->set_decoder_code_ls(0x00AA);\n   device->set_decoder_code_le(0x012A);\n   device->set_decoder_code_fs(0x02AA);\n   device->set_decoder_code_fe(0x032A);\n   device->set_decoder_code_bl(0x0015);\n   device->set_decoder_code_img(0x0035);\n   device->set_decoder_code_tr(0x03A6);\n   device->set_decoder_code_crc(0x0059);\n\n   printf( \"VITA REMAPPER - Configuring for image lines in normal mode\\n\\r\");\n   device->set_remapper_control( 1);\n   uint32_t uControl = read_remapper_control();\n   printf( \"VITA REMAPPER - Control = 0x%08X\\n\\r\", uControl);\n   device->set_iserdes_control( VITA_ISERDES_RESET_BIT);\n   device->set_decoder_control( VITA_DECODER_RESET_BIT);\n   device->set_crc_control( VITA_CRC_INITVALUE_BIT | VITA_CRC_RESET_BIT);\n\n   usleep(10); // 10 usec\n#if 0\n   printf(\"VITA SPI Sequence 0 - Assert RESET_N pin\\n\\r\");\n   device->set_spi_control( VITA_VITA_RESET_BIT);\n#endif\n   usleep(10); // 10 usec\n   printf( \"VITA ISERDES - Releasing Reset\\n\\r\");\n   device->set_iserdes_control( 0);\n   printf( \"VITA DECODER - Releasing Reset\\n\\r\");\n   device->set_decoder_control( 0);\n   printf( \"VITA CRC - Releasing Reset\\n\\r\");\n   device->set_crc_control( VITA_CRC_INITVALUE_BIT);\n   sleep(1); // 1 sec (time to get clocks to lock)\n#if 0\n   printf(\"VITA SPI Sequence 0 - Releasing RESET_N pin\\n\\r\");\n   device->set_spi_control( 0);\n#endif\n   usleep(20); // 20 usec\n   uData = vita_spi_read(0);\nprintf(\"[%s:%d] %x\\n\", __FUNCTION__, __LINE__, uData);\n   switch ( uData) {\n   case 0:\n       printf( \"\\tVITA Sensor absent\\n\\r\");\n       break;\n   case 0x560D:\n       printf( \"\\tVITA-1300 Sensor detected\\n\\r\");\n       break;\n   case 0x5614:\n       printf( \"\\tVITA-2000 Sensor detected\\n\\r\");\n       break;\n   case 0x5632:\n       printf( \"\\tVITA-5000 Sensor detected\\n\\r\");\n       break;\n   case 0x56FA:\n       printf( \"\\tVITA-25K Sensor detected\\n\\r\");\n       break;\n   default:\n       printf( \"\\tERROR: Unknown CHIP_ID !!!\\n\\r\");\n       break;\n   }\n   if ( uData != 0x5614) {\n      printf( \"\\tERROR: Absent or unsupported VITA sensor !!!\\n\\r\");\n      return;\n   }\n   printf(\"VITA SPI Sequence 1 - Enable Clock Management - Part 1\\n\\r\");\n   vita_spi_write_sequence(vita_spi_seq1, VITA_SPI_SEQ1_QTY);\n   {\n   uint16_t uLock = 0;\n   printf(\"VITA SPI Sequence 2 - Verify PLL Lock Indicator\\n\\r\");\n   timeout = 10;\n   while ( !(uLock) && --timeout) {\n      usleep(100000);\n      uLock = vita_spi_read(24);\n   }\n   if ( !timeout) {\n       printf( \"\\tERROR: Timed Out while waiting for PLL lock to assert !!!\\n\\r\");\n      return;\n   }\n   }\n   printf(\"VITA SPI Sequence 3 - Enable Clock Management - Part 2\\n\\r\");\n   vita_spi_write_sequence(vita_spi_seq3, VITA_SPI_SEQ3_QTY);\n   printf(\"VITA SPI Sequence 4 - Required Register Upload\\n\\r\");\n   vita_spi_write_sequence(vita_spi_seq4, VITA_SPI_SEQ4_QTY);\n   printf(\"VITA SPI Sequence 5 - Soft Power-Up\\n\\r\");\n   vita_spi_write_sequence(vita_spi_seq5, VITA_SPI_SEQ5_QTY);\n   uStatus = read_iserdes_control();\n   printf( \"VITA ISERDES - Status = 0x%08X\\n\\r\", uStatus);\n   uStatus = read_iserdes_control();\n   printf( \"VITA ISERDES - Status = 0x%08X\\n\\r\", uStatus);\n   uStatus = read_iserdes_control();\n   printf( \"VITA ISERDES - Status = 0x%08X\\n\\r\", uStatus);\n   timeout = 9;\n   while ( !(uStatus & 0x0100) && --timeout) {\n      uStatus = read_iserdes_control();\n      printf( \"VITA ISERDES - Status = 0x%08X\\n\\r\", uStatus);\n      usleep(1);\n   }\n   if ( !timeout) {\n      printf( \"\\tTimed Out !!!\\n\\r\");\n      return;\n   }\n   printf( \"VITA ISERDES - Align Start\\n\\r\");\n   device->set_iserdes_control( VITA_ISERDES_ALIGN_START_BIT);\n   printf( \"VITA ISERDES - Waiting for ALIGN_BUSY to assert\\n\\r\");\n   uStatus = read_iserdes_control();\n   printf( \"VITA ISERDES - Status = 0x%08X\\n\\r\", uStatus);\n   timeout = 9;\n   while ( !(uStatus & 0x0200) && --timeout) {\n      uStatus = read_iserdes_control();\n      printf( \"VITA ISERDES - Status = 0x%08X\\n\\r\", uStatus);\n      usleep(1);\n   }\n   if ( !timeout) {\n      printf( \"\\tTimed Out !!!\\n\\r\");\n      return;\n   }\n   device->set_iserdes_control( 0);\n   printf( \"VITA ISERDES - Waiting for ALIGN_BUSY to de-assert\\n\\r\");\n   uStatus = read_iserdes_control();\n   printf( \"VITA ISERDES - Status = 0x%08X\\n\\r\", uStatus);\n   timeout = 9;\n   while ( (uStatus & 0x0200) && --timeout) {\n      uStatus = read_iserdes_control();\n      printf( \"VITA ISERDES - Status = 0x%08X\\n\\r\", uStatus);\n      usleep(1);\n   }\n   if ( !timeout)\n      printf( \"\\tTimed Out !!!\\n\\r\");\n   uStatus = read_iserdes_control();\n   printf( \"VITA ISERDES - Status = 0x%08X\\n\\r\", uStatus);\n   printf(\"VITA SPI Sequence   - Crop ROI0 to 1920x1080\\n\\r\");\n   vita_spi_write_sequence(vita_roi0_crop_1080p_seq, VITA_ROI0_CROP_1080P_QTY);\n   printf(\"VITA SPI Sequence   - Set mult_timer to line resolution\\n\\r\");\n   vita_spi_write_sequence(vita_mult_timer_line_resolution_seq, VITA_MULT_TIMER_LINE_RESOLUTION_QTY);\n   printf(\"VITA SPI Sequence   - Set auto-exposure to ON\\n\\r\");\n   vita_spi_write_sequence(vita_autoexp_on_seq, VITA_AUTOEXP_ON_QTY);\n   printf(\"VITA SPI Sequence 6 - Enable Sequencer\\n\\r\");\n   vita_spi_write_sequence(vita_spi_seq6, VITA_SPI_SEQ6_QTY);\n   device->set_iserdes_control( VITA_ISERDES_FIFO_ENABLE_BIT);\n   device->set_decoder_control(VITA_DECODER_ENABLE_BIT);\n   uControl = read_decoder_control();\n   printf( \"VITA DECODER - Control = 0x%08X\\n\\r\", uControl);\n   uStatus = read_crc_status();\n   printf( \"VITA CRC - Status = 0x%08X\\n\\r\", uStatus);\n   usleep(100);\n   uStatus = read_crc_status();\n   printf( \"VITA CRC - Status = 0x%08X\\n\\r\", uStatus);\n   sleep(1);\n   printf( \"VITA 1080P60 - Disable Sequencer\\n\\r\");\n   vita_spi_write(192, 0); usleep(100); // 100 usec\n   printf( \"VITA 1080P60 - Adjust line spacing in VITA\\n\\r\");\n   vita_spi_write(193, 0x0400); usleep(100); // 100 usec\n   vita_spi_write(192, 0x0040); usleep(100); // 100 usec\n   printf( \"VITA 1080P60 - Tolerate 6 lines of jitter (required for programmable exposure)\\n\\r\");\n   device->set_syncgen_delay(0x0CE4);\n   printf( \"VITA 1080P60 - Adjust line spacing in sync generator\\n\\r\");\n   device->set_syncgen_hactive(0x0780);\n   device->set_syncgen_hfporch(0x0058);\n   device->set_syncgen_hsync(0x802C);\n   device->set_syncgen_hbporch(0x0094);\n   printf( \"VITA 1080P60 - Adjust frame spacing in VITA\\n\\r\");\n   vita_spi_write(199, 0x0001); usleep(100); // 100 usec\n   vita_spi_write(200, 0); usleep(100); // 100 usec\n   vita_spi_write(194, 0); usleep(100); // 100 usec\n   printf( \"VITA 1080P60 - Adjust frame spacing in sync generator\\n\\r\");\n   device->set_syncgen_vactive (0x0438);\n   device->set_syncgen_vfporch (0x0004);\n   device->set_syncgen_vsync(0x8005);\n   device->set_syncgen_vbporch(0x0024);\n   printf( \"VITA 1080P60 - Crop ROI0 from 1920x1200 to 1920x1080\\n\\r\");\n   vita_spi_write(257, 0x003C); usleep(100); // 100 usec\n   vita_spi_write(258, 0x0474); usleep(100); // 100 usec\n\n   printf( \"VITA 1080P60 - Disable auto-exposure\\n\\r\");\n   vita_spi_write(160, 0x0010); usleep(100); // 100 usec\n\n   printf( \"VITA 1080P60 - Enable trig generator\\n\\r\");\n   uint32_t trigDutyCycle    = 90; // exposure time is 90% of frame time (ie. 15msec)\n   uint32_t vitaTrigGenDefaultFreq = (((1920+88+44+148)*(1080+4+5+36))>>2) - 2;\n   device->set_trigger_default_freq(vitaTrigGenDefaultFreq);\n   device->set_trigger_cnt_trigger0high((vitaTrigGenDefaultFreq * (100-trigDutyCycle))/100); // negative polarity\n   device->set_trigger_cnt_trigger0low(1);\n   device->set_triggen_control(0x31000011); // invert trigger[2:0], internal trigger, enable trigger[0], update triggen_cnt registers\n   device->set_triggen_control(0x30000011); // invert trigger[2:0], internal trigger, enable trigger[0]\n   printf(\"VITA 1080P60 - Exposure related settings\\n\\r\");\n   vita_spi_write(194, 0x0400);\n   vita_spi_write(0x29, 0x0700);\n   uint16_t vspi_data = vita_spi_read(192) | 0x0071; usleep(100); // 100 usec\n   vita_spi_write(192, vspi_data); usleep(100); // 100 usec\n   fmc_imageon_vita_receiver_get_status();\n   uint32_t lastframes = vita_status_t2.cntFrames;\n   fmc_imageon_vita_receiver_get_status();\n   printf(\"VITA Status = \\n\\r\");\n   printf(\"\\tImage Width  = %d\\n\\r\", vita_status_t2.cntImagePixels * 4);\n   printf(\"\\tImage Height = %d\\n\\r\", vita_status_t2.cntImageLines);\n   printf(\"\\tFrame Rate   = %d frames/sec\\n\\r\", vita_status_t2.cntFrames - lastframes);\n   printf(\"Initializing iPipe cores ... done!\\r\\n\");\n   usleep(10000);\n}\n\nstatic void fmc_imageon_demo_init(int argc, const char **argv)\n{\n    int ret;\nprintf(\"[%s:%d]\\n\", __FUNCTION__, __LINE__);\n    //ret = fmc_iic_axi_init(uBaseAddr_IIC_FmcImageon);\n    //fmc_iic_axi_GpoWrite(uBaseAddr_IIC_FmcImageon, fmc_iic_axi_GpoRead(uBaseAddr_IIC_FmcImageon) | 2);\n    device->set_host_oe(1);\nprintf(\"[%s:%d]\\n\", __FUNCTION__, __LINE__);\n\n    spidevicefd = open(SPIDEVICENAME, O_RDWR);\n    if (spidevicefd < 0\n     || ioctl(spidevicefd, SPI_IOC_WR_MODE, &spimode) == -1\n     || ioctl(spidevicefd, SPI_IOC_RD_MODE, &spimode) == -1\n     || ioctl(spidevicefd, SPI_IOC_WR_BITS_PER_WORD, &spibits) == -1\n     || ioctl(spidevicefd, SPI_IOC_RD_BITS_PER_WORD, &spibits) == -1\n     || ioctl(spidevicefd, SPI_IOC_WR_MAX_SPEED_HZ, &speed) == -1\n     || ioctl(spidevicefd, SPI_IOC_RD_MAX_SPEED_HZ, &speed) == -1)\n        printf(\"Error: cannot open SPI device\\n\");\n\n    device->set_iic_reset(0);\n    device->set_iic_reset(1);\n    init_i2c_camera();\n    init_i2c_hdmi();\n    //init_vclk();\n\n    // Reset DCMs\n    /* puts the DCM_0 PCORE into reset */\n    //fmc_iic_axi_GpoWrite(uBaseAddr_IIC_FmcImageon, fmc_iic_axi_GpoRead(uBaseAddr_IIC_FmcImageon) | 4);\n    device->set_clock_gen_reset(1);\nprintf(\"[%s:%d]\\n\", __FUNCTION__, __LINE__);\n    usleep(200000);\n    /* releases the DCM_0 PCORE from reset */\n    //fmc_iic_axi_GpoWrite(uBaseAddr_IIC_FmcImageon, fmc_iic_axi_GpoRead(uBaseAddr_IIC_FmcImageon) & ~4);\n    device->set_clock_gen_reset(0);\nprintf(\"[%s:%d]\\n\", __FUNCTION__, __LINE__);\n\n    usleep(500000);\nprintf(\"[%s:%d]\\n\", __FUNCTION__, __LINE__);\nprintf(\"[%s:%d] locked %ld\\n\", __FUNCTION__, __LINE__, read_clock_gen_locked());\n    // FMC-IMAGEON VITA Receiver Initialization\n    printf( \"FMC-IMAGEON VITA Receiver Initialization ...\\n\\r\");\n    uManualTap = 25;\n    device->set_spi_timing((100/10));\n    fmc_imageon_demo_enable_ipipe();\n}\n\nstatic void *pthread_worker(void *ptr)\n{\n    portalExec(NULL);\n    return NULL;\n}\n\nint main(int argc, const char **argv)\n{\n    pthread_t threaddata;\n    init_local_semaphores();\n    device = ImageCapture::createImageCapture(\"fpga0\", new TestImageCaptureIndications);\n\n    int rc = pthread_create(&threaddata, NULL, &pthread_worker, (void *)device);\n    fmc_imageon_demo_init(argc, argv);\n    usleep(200000);\n    while (getchar() != EOF) {\ndevice->set_debugreq(1);\ndevice->get_debugind();\nprintf(\"[%s:%d] iserdes %lx\\n\", __FUNCTION__, __LINE__, read_iserdes_control());\nprintf(\"[%s:%d] decode %lx\\n\", __FUNCTION__, __LINE__, read_decoder_control());\nprintf(\"[%s:%d] crccontrol %lx\\n\", __FUNCTION__, __LINE__, read_crc_control());\nprintf(\"[%s:%d] crcstatus %lx\\n\", __FUNCTION__, __LINE__, read_crc_status());\nprintf(\"[%s:%d] remapper %lx\\n\", __FUNCTION__, __LINE__, read_remapper_control());\nprintf(\"[%s:%d] triggen %lx\\n\", __FUNCTION__, __LINE__, read_triggen_control());\nstatic int regids[] = {24, 97, 186, 0};\nint i;\nfor (i = 0; regids[i]; i++)\n    printf(\"[%s:%d] spi %d. %x\\n\", __FUNCTION__, __LINE__, regids[i], vita_spi_read(regids[i]));\n    }\nreturn 0;\n}\n"
  },
  {
    "path": "tests/test_spi0/test_spi0.cpp",
    "content": "\n// Copyright (c) 2014 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n#include <stdio.h>\n#include <stdlib.h>\n#include <unistd.h>\n#include <assert.h>\n#include <string.h>\n#include <fcntl.h>\n#include <sys/ioctl.h>\n#include <linux/types.h>\n#include \"linux/spi/spidev.h\"\n\n#include \"SPIRequest.h\"\n#include \"SPIResponse.h\"\n\n#define SPIDEVICENAME \"/dev/spidev2.0\"\n\nstatic int spidevicefd;\nstatic uint8_t spimode = 0;\nstatic uint8_t spibits = 8;\nstatic uint32_t speed = 16666666;\nstatic uint16_t delay = 100;\n\nuint32_t bit_sel(uint32_t lsb, uint32_t msb, uint32_t v)\n{\n  return (v >> lsb) & ~(~0 << (msb-lsb+1));\n}\n\nclass SPIResponse : public SPIResponseWrapper\n{\npublic:\n  virtual void read_resp(uint8_t v){\n    fprintf(stderr, \"read_resp cd:%d wp:%d\\n\", (v&2)>>1, v&1);\n  }\n  virtual void emio_sample(const Spew v){\n    fprintf(stderr, \"emio_sample{mo:%d, motn:%d, sson:%d, ssntn:%d, sclko:%d, sclktn:%d, cnt:%d}\\n\", \n\t                       v.mo,  v.motn,  v.sson,  v.ssntn,  v.sclko,  v.sclktn,  v.cnt);\n  }\n  virtual void cnt_cycle_resp(uint32_t v){\n    fprintf(stderr, \"cnt_cycle_resp %d\\n\", v);\n  } \n  virtual void spi_word(uint32_t v){\n    fprintf(stderr, \"spi_word %08x\\n\", v);\n  }\n  SPIResponse(unsigned int id) : SPIResponseWrapper(id){}\n};\n\n\nint main(int argc, const char **argv)\n{\n  SPIRequestProxy *device = new SPIRequestProxy(IfcNames_ControllerRequest);\n  SPIResponse ind(IfcNames_ControllerResponse);\n  uint8_t iter = 1;\n\n  device->set_clk_inv(0);\n  device->set_spew_en(0);\n  device->set_spew_src(0);\n  spidevicefd = open(SPIDEVICENAME, O_RDWR);\n  if (spidevicefd < 0){\n    printf(\"Error: cannot open SPI device\\n\");\n    goto finish;\n  } else if (ioctl(spidevicefd, SPI_IOC_WR_MODE, &spimode) == -1\n\t     || ioctl(spidevicefd, SPI_IOC_RD_MODE, &spimode) == -1\n\t     || ioctl(spidevicefd, SPI_IOC_WR_BITS_PER_WORD, &spibits) == -1\n\t     || ioctl(spidevicefd, SPI_IOC_RD_BITS_PER_WORD, &spibits) == -1\n\t     || ioctl(spidevicefd, SPI_IOC_WR_MAX_SPEED_HZ, &speed) == -1\n\t     || ioctl(spidevicefd, SPI_IOC_RD_MAX_SPEED_HZ, &speed) == -1){\n    printf(\"Error: cannot configure SPI device\\n\");\n    goto finish;\n  } else {\n    printf(\"Successfully opened spi %x\\n\", spidevicefd);\n  }\n\n  while(iter < 4){\n    uint8_t tx[sizeof(uint32_t)], rx[sizeof(uint32_t)];\n    for(unsigned int i = 0; i < sizeof(uint32_t); i++)\n      tx[i] = 1;\n    struct spi_ioc_transfer tr;\n    tr.tx_buf = (unsigned long)tx;\n    tr.rx_buf = (unsigned long)rx;\n    tr.len = sizeof(tx);\n    tr.delay_usecs = delay;\n    tr.speed_hz = speed;\n    tr.bits_per_word = spibits;\n    {\n      struct CycleReq cr;\n      cr.clk_sel = 0;\n      cr.clk_cnt = 10000;\n      device->cnt_cycle_req(cr);\n    }\n    if (ioctl(spidevicefd, SPI_IOC_MESSAGE(1), &tr) < 1)\n      printf(\"can't send spi message\\n\");\n    else\n      printf(\"successfully sent spi message\\n\");\n    iter++;\n    sleep(1);\n  }\n finish:\n  if (spidevicefd >= 0) \n    close(spidevicefd);\n  return 0;\n}\n"
  },
  {
    "path": "tests/testfpmul/Makefile",
    "content": "CONNECTALDIR?=../..\n\nMMDIR=../../examples/matmul\nTESTCPPFILES=  testfpmul.cpp\nBSCFLAGS=-aggressive-conditions -show-schedule -keep-fires -p +:../paclib\nCONNECTALFLAGS = -D J_VALUE=2 -D K_VALUE=2 -D N_VALUE=2\n\ninclude $(MMDIR)/Makefile.mm\ninclude $(MMDIR)/Makefile.mmif\ninclude $(CONNECTALDIR)/Makefile.connectal\n"
  },
  {
    "path": "tests/testfpmul/Top.bsv",
    "content": "/* Copyright (c) 2014 Quanta Research Cambridge, Inc\n *\n * Permission is hereby granted, free of charge, to any person obtaining a\n * copy of this software and associated documentation files (the \"Software\"),\n * to deal in the Software without restriction, including without limitation\n * the rights to use, copy, modify, merge, publish, distribute, sublicense,\n * and/or sell copies of the Software, and to permit persons to whom the\n * Software is furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n * DEALINGS IN THE SOFTWARE.\n */\nimport ConnectalConfig::*;\nimport Vector::*;\nimport FIFO::*;\nimport Connectable::*;\nimport Portal::*;\nimport CtrlMux::*;\nimport ConnectalMemTypes::*;\nimport FpMulIndication::*;\nimport FpMulRequest::*;\nimport RbmTypes::*;\nimport FpMacTb::*;\n\nmodule  mkConnectalTop(ConnectalTop);\n\n   FpMulIndicationProxy ind <- mkFpMulIndicationProxy(IfcNames_FpMulIndicationPortal);\n   FpMulRequest req <- mkFpMulRequest(ind.ifc);\n   FpMulRequestWrapper reqW <- mkFpMulRequestWrapper(IfcNames_FpMulRequestPortal,req);\n\n   Vector#(2,StdPortal) portals;\n   portals[0] = ind.portalIfc;\n   portals[1] = reqW.portalIfc; \n   let ctrl_mux <- mkSlaveMux(portals);\n   \n   interface interrupt = getInterruptVector(portals);\n   interface slave = ctrl_mux;\n   interface masters = replicate(?);\nendmodule : mkConnectalTop\n"
  },
  {
    "path": "tests/testfpmul/testfpmul.cpp",
    "content": "\n// Copyright (c) 2014 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\n#include <stdio.h>\n#include <sys/mman.h>\n#include <string.h>\n#include <stdlib.h>\n#include <unistd.h>\n#include <semaphore.h>\n#include <errno.h>\n#include <math.h>\n#include <assert.h>\n\n#include <GeneratedTypes.h>\n#include <FpMulRequest.h>\n#include <FpMulIndication.h>\n\n////////////////////////////////////////////\n// \n\nclass RbmRequestProxy;\nclass MmRequestProxy;\nclass SigmoidRequestProxy;\nclass TimerRequestProxy;\nclass SigmoidIndication;\n\nRbmRequestProxy *rbmdevice = 0;\nMmRequestProxy *mmdevice = 0;\nSigmoidIndication *sigmoidindication = 0;\nSigmoidRequestProxy *sigmoiddevice = 0;\nTimerRequestProxy *timerdevice = 0;\n\n// \n////////////////////////////////////////////\n\nclass FpMulIndication : public FpMulIndicationWrapper\n{\npublic:\n  virtual void mul_resp(uint32_t v) {\n    fprintf(stderr, \"res: %d\\n\", v);\n\texit(0);\n    }\n    FpMulIndication(unsigned int id) : FpMulIndicationWrapper(id) {}\n};\n\n\nint main(int argc, const char **argv)\n{\n  unsigned int srcGen = 0;\n\n  fprintf(stderr, \"%s %s\\n\", __DATE__, __TIME__);\n  FpMulRequestProxy *dev = new FpMulRequestProxy(IfcNames_FpMulRequestPortal);\n  FpMulIndication   *ind = new FpMulIndication(IfcNames_FpMulIndicationPortal);\n\n  dev->mul_req(0,0);\n  while(1);\n}\n"
  },
  {
    "path": "tests/testldstrex/Makefile",
    "content": "CONNECTALDIR?=../..\n\nTOOLCHAIN ?= /afs/csail.mit.edu/group/csg/tools/tools_lx86/android-ndk-r9d/sources/cxx-stl/gnu-libstdc++/4.6\nCPPFILES= testldstrex.cpp\nCONNECTALFLAGS += -I $(TOOLCHAIN)/include -I $(TOOLCHAIN)/libs/armeabi-v7a/include\n\ninclude $(CONNECTALDIR)/Makefile.connectal\n"
  },
  {
    "path": "tests/testldstrex/testldstrex.cpp",
    "content": "// Copyright (c) 2014 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n//#include <stdio.h>\n//#include <sys/mman.h>\n//#include <string.h>\n//#include <stdlib.h>\n//#include <unistd.h>\n//#include <semaphore.h>\n//#include <pthread.h>\n//#include <errno.h>\n//#include <math.h> // frexp(), fabs()\n//#include <assert.h>\n//#include <stdio.h>\n//#include <errno.h>\n#include <ext/atomicity.h>\n#include \"portal.h\"\n#define CV_XADD __gnu_cxx::__exchange_and_add\n\nint main(int argc, const char **argv)\n{\n  int totalsize = 4096;\n  int fd = portalAlloc(totalsize, 0);\n  if (fd < 0) {\n    fprintf(stderr, \"memory alloc failed\\n\");\n    exit(-1);\n  }\n  fprintf(stderr, \"allocated %d bytes, fd=%d\\n\", totalsize, fd);\n  int *mem = (int*)portalMmap(fd, totalsize);\n  *mem = 1;\n  fprintf(stderr, \"Before CV_XADD: mem=%p *mem=%d\\n\", mem, *mem);\n  CV_XADD(mem, -1);\n  fprintf(stderr, \"Before CV_XADD: *mem=%d\\n\", *mem);\n  exit(0);\n}\n"
  },
  {
    "path": "tests/testmm16.16.2/Makefile",
    "content": "CONNECTALDIR?=../..\nBSCFLAGS=-aggressive-conditions -show-schedule -keep-fires -p +:../paclib\n\nMMDIR=$(CONNECTALDIR)/examples/matmul\nRBMDIR=$(CONNECTALDIR)/examples/rbm\nTESTCPPFILES= $(MMDIR)/testmm.cpp\nCONNECTALFLAGS = -D J_VALUE=16 -D K_VALUE=16 -D N_VALUE=2\n\ninclude $(MMDIR)/Makefile.mm\ninclude $(MMDIR)/Makefile.mmif\ninclude $(CONNECTALDIR)/Makefile.connectal\n"
  },
  {
    "path": "tests/testmm16.16.4/Makefile",
    "content": "CONNECTALDIR?=../..\nBSCFLAGS=-aggressive-conditions -show-schedule -keep-fires -p +:../paclib\n\nMMDIR=$(CONNECTALDIR)/examples/matmul\nRBMDIR=$(CONNECTALDIR)/examples/rbm\nTESTCPPFILES= $(MMDIR)/testmm.cpp\nCONNECTALFLAGS = -D J_VALUE=16 -D K_VALUE=16 -D N_VALUE=4  -D DataBusWidth=128\n\ninclude $(MMDIR)/Makefile.mm\ninclude $(MMDIR)/Makefile.mmif\ninclude $(CONNECTALDIR)/Makefile.connectal\n"
  },
  {
    "path": "tests/testmm2.4.2/Makefile",
    "content": "CONNECTALDIR?=../..\nBSCFLAGS=-aggressive-conditions -show-schedule -keep-fires -p +:../paclib\n\nMMDIR=$(CONNECTALDIR)/examples/matmul\nRBMDIR=$(CONNECTALDIR)/examples/rbm\nTESTCPPFILES= $(MMDIR)/testmm.cpp\nCONNECTALFLAGS = -D J_VALUE=2 -D K_VALUE=4 -D N_VALUE=2\n\ninclude $(MMDIR)/Makefile.mm\ninclude $(MMDIR)/Makefile.mmif\ninclude $(CONNECTALDIR)/Makefile.connectal\n"
  },
  {
    "path": "tests/testmm2.4.2/zc706_floorplan.xdc",
    "content": "create_pblock mmtile_0\nresize_pblock mmtile_0 -add {SLICE_X92Y150:SLICE_X96Y250 SLICE_X97Y150:SLICE_X161Y250 DSP48_X4Y62:DSP48_X6Y99 RAMB18_X5Y62:RAMB18_X7Y99 RAMB36_X5Y31:RAMB36_X7Y49}\nadd_cells_to_pblock mmtile_0 [get_cells [list top_mm_dmaMMF_dmaMMF_mmTiles_0]] -clear_locs\nset_property CONTAIN_ROUTING true [get_pblocks mmtile_0]\nset_property HD.PARTPIN_RANGE {SLICE_X92Y150:SLICE_X96Y250} [get_pins top_mm_dmaMMF_dmaMMF_mmTiles_0/*]\n\ncreate_pblock mmtile_1\nresize_pblock mmtile_1 -add {SLICE_X92Y52:SLICE_X96Y151 SLICE_X97Y52:SLICE_X159Y151 DSP48_X4Y22:DSP48_X6Y59 RAMB18_X4Y22:RAMB18_X7Y59 RAMB36_X4Y11:RAMB36_X7Y29}\nadd_cells_to_pblock mmtile_1 [get_cells [list top_mm_dmaMMF_dmaMMF_mmTiles_1]] -clear_locs\nset_property CONTAIN_ROUTING true [get_pblocks mmtile_1]\nset_property HD.PARTPIN_RANGE {SLICE_X92Y52:SLICE_X96Y151} [get_pins top_mm_dmaMMF_dmaMMF_mmTiles_1/*]\n"
  },
  {
    "path": "tests/testmm32.16.2/Makefile",
    "content": "CONNECTALDIR?=../..\nBSCFLAGS=-aggressive-conditions -show-schedule -keep-fires -p +:../paclib\n\nMMDIR=$(CONNECTALDIR)/examples/matmul\nRBMDIR=$(CONNECTALDIR)/examples/rbm\nTESTCPPFILES=$(MMDIR)/testmm.cpp\nCONNECTALFLAGS = -D J_VALUE=32 -D K_VALUE=16 -D N_VALUE=2\n\ninclude $(MMDIR)/Makefile.mm\ninclude $(MMDIR)/Makefile.mmif\ninclude $(CONNECTALDIR)/Makefile.connectal\n"
  },
  {
    "path": "tests/testmm32.32.2/Makefile",
    "content": "CONNECTALDIR?=../..\nBSCFLAGS=-aggressive-conditions -show-schedule -keep-fires -p +:../paclib\n\nMMDIR=$(CONNECTALDIR)/examples/matmul\nRBMDIR=$(CONNECTALDIR)/examples/rbm\nTESTCPPFILES= $(MMDIR)/testmm.cpp\nCONNECTALFLAGS = -D J_VALUE=32 -D K_VALUE=32 -D N_VALUE=2\n\ninclude $(MMDIR)/Makefile.mm\ninclude $(MMDIR)/Makefile.mmif\ninclude $(CONNECTALDIR)/Makefile.connectal\n"
  },
  {
    "path": "tests/testmm4.2.2/Makefile",
    "content": "CONNECTALDIR?=../..\nBSCFLAGS=-aggressive-conditions -show-schedule -keep-fires -p +:../paclib\n\nMMDIR=$(CONNECTALDIR)/examples/matmul\nRBMDIR=$(CONNECTALDIR)/examples/rbm\nTESTCPPFILES= $(MMDIR)/testmm.cpp\nCONNECTALFLAGS = -D J_VALUE=4 -D K_VALUE=2 -D N_VALUE=2\n\ninclude $(MMDIR)/Makefile.mm\ninclude $(MMDIR)/Makefile.mmif\ninclude $(CONNECTALDIR)/Makefile.connectal\n"
  },
  {
    "path": "tests/testmm4.4.2/Makefile",
    "content": "\nCONNECTALDIR?=../..\nBSCFLAGS=-aggressive-conditions -show-schedule -keep-fires -p +:../paclib\n\nMMDIR=$(CONNECTALDIR)/examples/matmul\nRBMDIR=$(CONNECTALDIR)/examples/rbm\nTESTCPPFILES= $(MMDIR)/testmm.cpp\nCONNECTALFLAGS = -D J_VALUE=4 -D K_VALUE=4 -D N_VALUE=2\n\ninclude $(MMDIR)/Makefile.mm\ninclude $(MMDIR)/Makefile.mmif\ninclude $(CONNECTALDIR)/Makefile.connectal\n"
  },
  {
    "path": "tests/testmm4.4.4/Makefile",
    "content": "CONNECTALDIR?=../..\nBSCFLAGS=-aggressive-conditions -show-schedule -keep-fires -p +:../paclib\n\nMMDIR=$(CONNECTALDIR)/examples/matmul\nRBMDIR=$(CONNECTALDIR)/examples/rbm\nTESTCPPFILES= $(MMDIR)/testmm.cpp\nCONNECTALFLAGS = -D J_VALUE=4 -D K_VALUE=4 -D N_VALUE=4 -D DataBusWidth=128\n\ninclude $(MMDIR)/Makefile.mm\ninclude $(MMDIR)/Makefile.mmif\ninclude $(CONNECTALDIR)/Makefile.connectal\n"
  },
  {
    "path": "tests/testmm8.8.2/Makefile",
    "content": "CONNECTALDIR?=../..\nBSCFLAGS=-aggressive-conditions -show-schedule -keep-fires -p +:../paclib\n\nMMDIR=$(CONNECTALDIR)/examples/matmul\nRBMDIR=$(CONNECTALDIR)/examples/rbm\nTESTCPPFILES= $(MMDIR)/testmm.cpp\nCONNECTALFLAGS = -D J_VALUE=8 -D K_VALUE=8 -D N_VALUE=2\n\ninclude $(MMDIR)/Makefile.mm\ninclude $(MMDIR)/Makefile.mmif\ninclude $(CONNECTALDIR)/Makefile.connectal\n"
  },
  {
    "path": "tests/testmm8.8.2/zc706_floorplan.xdc",
    "content": "create_pblock mmtile_0\nresize_pblock [get_pblocks mmtile_0] -add {SLICE_X56Y154:SLICE_X163Y274}\nresize_pblock [get_pblocks mmtile_0] -add {DSP48_X4Y62:DSP48_X6Y109}\nresize_pblock [get_pblocks mmtile_0] -add {RAMB18_X4Y62:RAMB18_X7Y109}\nresize_pblock [get_pblocks mmtile_0] -add {RAMB36_X4Y31:RAMB36_X7Y54}\nadd_cells_to_pblock mmtile_0 [get_cells [list top_mm_dmaMMF_dmaMMF_mmTiles_0]] -clear_locs\nset_property CONTAIN_ROUTING true [get_pblocks mmtile_0]\nset_property HD.PARTPIN_RANGE {SLICE_X56Y154:SLICE_X60Y274} [get_pins top_mm_dmaMMF_dmaMMF_mmTiles_0/*]\n\ncreate_pblock mmtile_1\nresize_pblock [get_pblocks mmtile_1] -add {SLICE_X56Y6:SLICE_X159Y151}\nresize_pblock [get_pblocks mmtile_1] -add {DSP48_X4Y4:DSP48_X6Y59}\nresize_pblock [get_pblocks mmtile_1] -add {RAMB18_X4Y4:RAMB18_X7Y59}\nresize_pblock [get_pblocks mmtile_1] -add {RAMB36_X4Y2:RAMB36_X7Y29}\nadd_cells_to_pblock mmtile_1 [get_cells [list top_mm_dmaMMF_dmaMMF_mmTiles_1]] -clear_locs\nset_property CONTAIN_ROUTING true [get_pblocks mmtile_1]\nset_property HD.PARTPIN_RANGE {SLICE_X56Y6:SLICE_X60Y151} [get_pins top_mm_dmaMMF_dmaMMF_mmTiles_1/*]\n"
  },
  {
    "path": "tests/testmm8.8.4/Makefile",
    "content": "CONNECTALDIR?=../..\nBSCFLAGS=-aggressive-conditions -show-schedule -keep-fires -p +:../paclib\n\nMMDIR=$(CONNECTALDIR)/examples/matmul\nRBMDIR=$(CONNECTALDIR)/examples/rbm\nTESTCPPFILES= $(MMDIR)/testmm.cpp\nCONNECTALFLAGS = -D J_VALUE=8 -D K_VALUE=8 -D N_VALUE=4 -D DataBusWidth=128\n\ninclude $(MMDIR)/Makefile.mm\ninclude $(MMDIR)/Makefile.mmif\ninclude $(CONNECTALDIR)/Makefile.connectal\n"
  },
  {
    "path": "tests/testmm_cuda_perf/Makefile",
    "content": "CONNECTALDIR?=../..\nBSCFLAGS=-aggressive-conditions -show-schedule -keep-fires -p +:../paclib\n\nCUDA_PERF_TEST = 1\n\nMMDIR=$(CONNECTALDIR)/examples/matmul\nRBMDIR=$(CONNECTALDIR)/examples/rbm\nTESTCPPFILES= $(MMDIR)/testmm.cpp\nCONNECTALFLAGS = -D J_VALUE=8 -D K_VALUE=8 -D N_VALUE=2\nCONNECTALFLAGS += -D CUDA_PERF_TEST=$(CUDA_PERF_TEST)\n\ninclude $(MMDIR)/Makefile.mm\ninclude $(MMDIR)/Makefile.mmif\ninclude $(CONNECTALDIR)/Makefile.connectal\n"
  },
  {
    "path": "tests/testmm_cuda_perf/Readme.md",
    "content": "Running on vangogh:\n\n1) download opencv 2.4.9 to /scratch/opencv-cuda/\n\n   http://downloads.sourceforge.net/project/opencvlibrary/opencv-unix/2.4.9/opencv-2.4.9.zip\n\n2) install it using the following commands (I used cmake version 2.8.11.2):\n        cd opencv-2.9.4\n\tmkdir install\n        cmake -G 'Unix Makefiles' -D WITH_CUDA=ON -D CMAKE_BUILD_TYPE=DEBUG -D BUILD_SHARED_LIBS=NO -D WITH_CUBLAS=YES -D CMAKE_INSTALL_PREFIX=./install .\n\tmake -j 8  \n\tmake install\n\n\n3)  nm -A *.a | c++filt | grep -w T \n\n"
  },
  {
    "path": "tests/testmm_cuda_perf/cuda_opencv_example/Makefile",
    "content": "NVCC = /usr/local/cuda-5.5/bin/nvcc\n\ndefault: cuda_opencv_example\n\nmain.o: main.cu\n\t$(NVCC) -I/usr/local/cuda-5.5/targets/x86_64-linux/include/ -I/scratch/opencv-cuda/opencv-2.4.9/install/include -c main.cu\n\ncuda_opencv_example: main.o main.cpp\n\tg++ -I/usr/local/cuda-5.5/targets/x86_64-linux/include/ -I/scratch/opencv-cuda/opencv-2.4.9/install/include -o cuda_opencv_example main.o main.cpp \\\n\t-L/scratch/opencv-cuda/opencv-2.4.9/install/lib -L/usr/local/cuda-5.5/lib64 \\\n\t-lcuda -lopencv_core  -lopencv_gpu -lcudart -lopencv_core \n\nrun:\n\tLD_LIBRARY_PATH=/usr/local/cuda-5.5/lib64 ./cuda_opencv_example\n\nclean:\n\trm -f main.o cuda_opencv_example"
  },
  {
    "path": "tests/testmm_cuda_perf/cuda_opencv_example/main.cpp",
    "content": "/* Copyright (c) 2014 Quanta Research Cambridge, Inc\r\n *\r\n * Permission is hereby granted, free of charge, to any person obtaining a\r\n * copy of this software and associated documentation files (the \"Software\"),\r\n * to deal in the Software without restriction, including without limitation\r\n * the rights to use, copy, modify, merge, publish, distribute, sublicense,\r\n * and/or sell copies of the Software, and to permit persons to whom the\r\n * Software is furnished to do so, subject to the following conditions:\r\n *\r\n * The above copyright notice and this permission notice shall be included\r\n * in all copies or substantial portions of the Software.\r\n *\r\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\r\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\r\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\r\n * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\r\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\r\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\r\n * DEALINGS IN THE SOFTWARE.\r\n */\r\n#include<iostream>\r\n#include<cstdio>\r\n#include<opencv2/core/core.hpp>\r\n#include<opencv2/highgui/highgui.hpp>\r\n#include<cuda_runtime.h>\r\n#include<cuda_runtime_api.h>\r\n\r\nusing std::cout;\r\nusing std::endl;\r\n\r\nvoid convert_to_gray(const cv::Mat& input, cv::Mat& output);\r\nvoid map_sigmoid(const cv::Mat& input, cv::Mat& output);\r\nfloat sigmoid(float x);\r\n\r\n\r\n#define SIGMOID\r\n#ifdef SIGMOID\r\n\r\nint main()\r\n{\r\n  int A = 128;\r\n  int B = 128;\r\n\r\n  srand(A*B);\r\n\r\n  cv::Mat input(A,B,CV_32F);\r\n  cv::Mat output(A,B,CV_32F);\r\n\r\n  for(int a = 0; a < A; a++)\r\n    for(int b = 0; b < B; b++)\r\n      input.at<float>(a,b) = (float)(rand() % 10);\r\n\r\n  fprintf(stderr, \"about to call kernel\\n\");\r\n  map_sigmoid(input,output);\r\n  fprintf(stderr, \"successfully called kernel\\n\");\r\n  \r\n  bool match = true;\r\n  float epsilon = 0.00001;\r\n  for(int a = 0; a < A; a++) {\r\n    for(int b = 0; b < B; b++) {\r\n      float ref = sigmoid(input.at<float>(a,b));\r\n      float gpuv = output.at<float>(a,b);\r\n      float err = fabs(ref - gpuv);//ref;\r\n      bool eq = (epsilon > err);\r\n      match &= eq;\r\n      if (!eq) fprintf(stderr, \"(%d,%d) %f %f\\n\", a,b,ref,gpuv);\r\n    }\r\n  }\r\n  return !match;\r\n}\r\n\r\n#else // SIGMOID\r\nint main()\r\n{\r\n\tstd::string imagePath = \"image.jpg\";\r\n\r\n\t//Read input image from the disk\r\n\tcv::Mat input = cv::Mat::zeros(100,100,CV_LOAD_IMAGE_COLOR); //cv::imread(imagePath,CV_LOAD_IMAGE_COLOR);\r\n\r\n\tif(input.empty())\r\n\t{\r\n\t\tstd::cout<<\"Image Not Found!\"<<std::endl;\r\n\t\tstd::cin.get();\r\n\t\treturn -1;\r\n\t}\r\n\r\n\t//Create output image\r\n\tcv::Mat output(input.rows,input.cols,CV_8UC1);\r\n\r\n\tfprintf(stderr, \"about to call kernel\\n\");\r\n\r\n\t//Call the wrapper function\r\n\tconvert_to_gray(input,output);\r\n\r\n\t//Show the input and output\r\n\t//cv::imshow(\"Input\",input);\r\n\t//cv::imshow(\"Output\",output);\r\n\t\r\n\t//Wait for key press\r\n\t//cv::waitKey();\r\n\r\n\tfprintf(stderr, \"successfully called kernel\\n\");\r\n\r\n\treturn 0;\r\n}\r\n#endif // SIGMOID\r\n"
  },
  {
    "path": "tests/testmm_cuda_perf/cuda_opencv_example/main.cu",
    "content": "/* Copyright (c) 2014 Quanta Research Cambridge, Inc\n *\n * Permission is hereby granted, free of charge, to any person obtaining a\n * copy of this software and associated documentation files (the \"Software\"),\n * to deal in the Software without restriction, including without limitation\n * the rights to use, copy, modify, merge, publish, distribute, sublicense,\n * and/or sell copies of the Software, and to permit persons to whom the\n * Software is furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included\n * in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS\n * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n * DEALINGS IN THE SOFTWARE.\n */\n#include<iostream>\n#include<cstdio>\n#include<opencv2/core/core.hpp>\n#include<opencv2/highgui/highgui.hpp>\n#include<cuda_runtime.h>\n#include<cuda_runtime_api.h>\n\nusing std::cout;\nusing std::endl;\n\nstatic inline void _safe_cuda_call(cudaError err, const char* msg, const char* file_name, const int line_number)\n{\n\tif(err!=cudaSuccess)\n\t{\n\t\tfprintf(stderr,\"%s\\n\\nFile: %s\\n\\nLine Number: %d\\n\\nReason: %s\\n\",msg,file_name,line_number,cudaGetErrorString(err));\n\t\tstd::cin.get();\n\t\texit(EXIT_FAILURE);\n\t}\n}\n\n#define SAFE_CALL(call,msg) _safe_cuda_call((call),(msg),__FILE__,__LINE__)\n\n\n__global__ void bgr_to_gray_kernel( unsigned char* input, \n\t\t\t\t    unsigned char* output, \n\t\t\t\t    int width,\n\t\t\t\t    int height,\n\t\t\t\t    int colorWidthStep,\n\t\t\t\t    int grayWidthStep)\n{\n\t//2D Index of current thread\n\tconst int xIndex = blockIdx.x * blockDim.x + threadIdx.x;\n\tconst int yIndex = blockIdx.y * blockDim.y + threadIdx.y;\n\n\t//Only valid threads perform memory I/O\n\tif((xIndex<width) && (yIndex<height))\n\t{\n\t\t//Location of colored pixel in input\n\t\tconst int color_tid = yIndex * colorWidthStep + (3 * xIndex);\n\t\t\n\t\t//Location of gray pixel in output\n\t\tconst int gray_tid  = yIndex * grayWidthStep + xIndex;\n\n\t\tconst unsigned char blue\t= input[color_tid];\n\t\tconst unsigned char green\t= input[color_tid + 1];\n\t\tconst unsigned char red\t\t= input[color_tid + 2];\n\n\t\tconst float gray = red * 0.3f + green * 0.59f + blue * 0.11f;\n\n\t\toutput[gray_tid] = static_cast<unsigned char>(gray);\n\t}\n}\n\nvoid convert_to_gray(const cv::Mat& input, cv::Mat& output)\n{\n\t//Calculate total number of bytes of input and output image\n\tconst int colorBytes = input.step * input.rows;\n\tconst int grayBytes = output.step * output.rows;\n\n\tunsigned char *d_input, *d_output;\n\n\t//Allocate device memory\n\tSAFE_CALL(cudaMalloc<unsigned char>(&d_input,colorBytes),\"CUDA Malloc Failed\");\n\tSAFE_CALL(cudaMalloc<unsigned char>(&d_output,grayBytes),\"CUDA Malloc Failed\");\n\n\t//Copy data from OpenCV input image to device memory\n\tSAFE_CALL(cudaMemcpy(d_input,input.ptr(),colorBytes,cudaMemcpyHostToDevice),\"CUDA Memcpy Host To Device Failed\");\n\n\t//Specify a reasonable block size\n\tconst dim3 block(16,16);\n\n\t//Calculate grid size to cover the whole image\n\tconst dim3 grid((input.cols + block.x - 1)/block.x, (input.rows + block.y - 1)/block.y);\n\n\t//Launch the color conversion kernel\n\tbgr_to_gray_kernel<<<grid,block>>>(d_input,d_output,input.cols,input.rows,input.step,output.step);\n\n\t//Synchronize to check for any kernel launch errors\n\tSAFE_CALL(cudaDeviceSynchronize(),\"Kernel Launch Failed\");\n\n\t//Copy back data from destination device meory to OpenCV output image\n\tSAFE_CALL(cudaMemcpy(output.ptr(),d_output,grayBytes,cudaMemcpyDeviceToHost),\"CUDA Memcpy Host To Device Failed\");\n\n\t//Free the device memory\n\tSAFE_CALL(cudaFree(d_input),\"CUDA Free Failed\");\n\tSAFE_CALL(cudaFree(d_output),\"CUDA Free Failed\");\n}\n\n#define SIGMOID(x) ((x < -8.0) ? -8.0 : ((x > 8.0) ? 8.0 : (1 / (1 + expf(-x)))))\n\nfloat sigmoid(float x)\n{\n  return SIGMOID(x);\n}\n\n__global__ void ssigmoid( float* input, \n\t\t\t  float* output, \n\t\t\t  int width,\n\t\t\t  int height)\n{\n  //2D Index of current thread\n  const int xIndex = blockIdx.x * blockDim.x + threadIdx.x;\n  const int yIndex = blockIdx.y * blockDim.y + threadIdx.y;\n  \n  //Only valid threads perform memory I/O\n  if((xIndex<width) && (yIndex<height)) {\n    int offs = (yIndex*width)+xIndex;\n    output[offs] = SIGMOID(input[offs]);\n  }\n}\n\n\nvoid map_sigmoid(const cv::Mat& input, cv::Mat& output)\n{\n  //Calculate total number of bytes of input and output image\n  const int inputBytes = input.step * input.rows;\n  const int outputBytes = output.step * output.rows;\n  \n  float *d_input, *d_output;\n  \n  //Allocate device memory\n  SAFE_CALL(cudaMalloc<float>(&d_input,inputBytes),\"CUDA Malloc Failed\");\n  SAFE_CALL(cudaMalloc<float>(&d_output,outputBytes),\"CUDA Malloc Failed\");\n  \n  //Copy data from OpenCV input image to device memory\n  SAFE_CALL(cudaMemcpy(d_input,input.ptr(),inputBytes,cudaMemcpyHostToDevice),\"CUDA Memcpy Host To Device Failed\");\n  \n  //Specify a reasonable block size\n  const dim3 block(16,16);\n  \n  //Calculate grid size to cover the whole image\n  const dim3 grid((input.cols + block.x - 1)/block.x, (input.rows + block.y - 1)/block.y);\n  \n  //Launch the input conversion kernel\n  ssigmoid<<<grid,block>>>(d_input,d_output,input.cols,input.rows);\n  \n  //Synchronize to check for any kernel launch errors\n  SAFE_CALL(cudaDeviceSynchronize(),\"Kernel Launch Failed\");\n  \n  //Copy back data from destination device meory to OpenCV output image\n  SAFE_CALL(cudaMemcpy(output.ptr(),d_output,outputBytes,cudaMemcpyDeviceToHost),\"CUDA Memcpy Host To Device Failed\");\n  \n  //Free the device memory\n  SAFE_CALL(cudaFree(d_input),\"CUDA Free Failed\");\n  SAFE_CALL(cudaFree(d_output),\"CUDA Free Failed\");\n}\n\n"
  },
  {
    "path": "tests/testmm_cuda_perf/run_exe",
    "content": "#!/bin/bash\nset -x \nLD_LIBRARY_PATH=/usr/local/cuda-5.5/lib64 ./bin/bsim_exe \n"
  },
  {
    "path": "tests/testmm_cuda_perf/synth-ip.tcl",
    "content": "source \"board.tcl\"\nsource \"$connectaldir/scripts/connectal-synth-ip.tcl\"\n\nconnectal_synth_ip floating_point 7.0 fp_add [list CONFIG.Axi_Optimize_Goal {Performance} CONFIG.Maximum_Latency {false} CONFIG.Has_ARESETN {true}]\nconnectal_synth_ip floating_point 7.0 fp_mul [list CONFIG.Operation_Type {Multiply} CONFIG.Axi_Optimize_Goal {Resources} CONFIG.Maximum_Latency {false} CONFIG.Has_ARESETN {true}]\n"
  },
  {
    "path": "tests/testmm_cuda_perf/zc706_floorplan.xdc",
    "content": "create_pblock mmtile_0\nresize_pblock mmtile_0 -add {SLICE_X92Y150:SLICE_X96Y250 SLICE_X97Y150:SLICE_X161Y250 DSP48_X4Y62:DSP48_X6Y99 RAMB18_X5Y62:RAMB18_X7Y99 RAMB36_X5Y31:RAMB36_X7Y49}\nadd_cells_to_pblock mmtile_0 [get_cells [list top_mm_dmaMMF_dmaMMF_mmTiles_0]] -clear_locs\nset_property CONTAIN_ROUTING true [get_pblocks mmtile_0]\nset_property HD.PARTPIN_RANGE {SLICE_X92Y150:SLICE_X96Y250} [get_pins top_mm_dmaMMF_dmaMMF_mmTiles_0/*]\n\ncreate_pblock mmtile_1\nresize_pblock mmtile_1 -add {SLICE_X92Y52:SLICE_X96Y151 SLICE_X97Y52:SLICE_X159Y151 DSP48_X4Y22:DSP48_X6Y59 RAMB18_X4Y22:RAMB18_X7Y59 RAMB36_X4Y11:RAMB36_X7Y29}\nadd_cells_to_pblock mmtile_1 [get_cells [list top_mm_dmaMMF_dmaMMF_mmTiles_1]] -clear_locs\nset_property CONTAIN_ROUTING true [get_pblocks mmtile_1]\nset_property HD.PARTPIN_RANGE {SLICE_X92Y52:SLICE_X96Y151} [get_pins top_mm_dmaMMF_dmaMMF_mmTiles_1/*]\n"
  },
  {
    "path": "tests/testrbm16.16.2/Makefile",
    "content": "CONNECTALDIR?=../..\nBSCFLAGS=-aggressive-conditions -show-schedule -keep-fires -p +:../paclib\n\nMMDIR=$(CONNECTALDIR)/examples/matmul\nRBMDIR=$(CONNECTALDIR)/examples/rbm\nTESTCPPFILES= $(RBMDIR)/testrbm.cpp\nCONNECTALFLAGS = -D J_VALUE=16 -D K_VALUE=16 -D N_VALUE=2 -D DataBusWidth=64\n\ninclude $(MMDIR)/Makefile.mm\ninclude $(RBMDIR)/Makefile.rbm\ninclude $(CONNECTALDIR)/Makefile.connectal\n\n"
  },
  {
    "path": "tests/testrbm16.16.2/synth-ip.tcl",
    "content": "source \"board.tcl\"\nsource \"$connectaldir/scripts/connectal-synth-ip.tcl\"\n\nconnectal_synth_ip floating_point 7.0 fp_add [list CONFIG.Axi_Optimize_Goal {Performance} CONFIG.Maximum_Latency {false} CONFIG.Has_ARESETN {true}]\nconnectal_synth_ip floating_point 7.0 fp_mul [list CONFIG.Operation_Type {Multiply} CONFIG.Axi_Optimize_Goal {Resources} CONFIG.Maximum_Latency {false} CONFIG.Has_ARESETN {true}]\n"
  },
  {
    "path": "tests/testrbm8.8.2/Makefile",
    "content": "CONNECTALDIR?=../..\nBSCFLAGS=-aggressive-conditions -show-schedule -keep-fires -p +:../paclib\n\nMMDIR=$(CONNECTALDIR)/examples/matmul\nRBMDIR=$(CONNECTALDIR)/examples/rbm\nTESTCPPFILES= $(RBMDIR)/testrbm.cpp\nCONNECTALFLAGS = -D J_VALUE=8 -D K_VALUE=8 -D N_VALUE=2 -D DataBusWidth=64\n\ninclude $(MMDIR)/Makefile.mm\ninclude $(RBMDIR)/Makefile.rbm\ninclude $(CONNECTALDIR)/Makefile.connectal\n"
  },
  {
    "path": "tests/testrbm8.8.2/synth-ip.tcl",
    "content": "source \"board.tcl\"\nsource \"$connectaldir/scripts/connectal-synth-ip.tcl\"\n\nconnectal_synth_ip floating_point 7.0 fp_add [list CONFIG.Axi_Optimize_Goal {Performance} CONFIG.Maximum_Latency {false} CONFIG.Has_ARESETN {true}]\nconnectal_synth_ip floating_point 7.0 fp_mul [list CONFIG.Operation_Type {Multiply} CONFIG.Axi_Optimize_Goal {Resources} CONFIG.Maximum_Latency {false} CONFIG.Has_ARESETN {true}]\n"
  },
  {
    "path": "tests/yuv/Makefile",
    "content": "CONNECTALDIR?=../..\nS2H_INTERFACES = YuvRequest:YuvIF.request\nH2S_INTERFACES = YuvIF:YuvIndication\n\nBSVFILES = YuvIF.bsv\nCPPFILES= testyuv.cpp\n\ninclude $(CONNECTALDIR)/Makefile.connectal\n"
  },
  {
    "path": "tests/yuv/YuvIF.bsv",
    "content": "\n// Copyright (c) 2014 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\nimport GetPut::*;\nimport HDMI::*;\nimport Vector::*;\nimport Arith::*;\nimport YUV::*;\n\ninterface YuvRequest;\n   method Action toRgb(Bit#(8) r, Bit#(8) g, Bit#(8) b);\n   method Action toYuv(Bit#(8) r, Bit#(8) g, Bit#(8) b);\n   method Action toYyuv(Bit#(8) r, Bit#(8) g, Bit#(8) b);\nendinterface\n\ninterface YuvIndication;\n   method Action rgb(Bit#(8) y, Bit#(8) u, Bit#(8) v);\n   method Action yuv(Bit#(8) y, Bit#(8) u, Bit#(8) v);\n   method Action yyuv(Bit#(8) yy, Bit#(8) uv);\nendinterface\n\ninterface YuvIF;\n  interface YuvRequest request;\nendinterface\n\nmodule mkYuvIF#(YuvIndication indication)(YuvIF);\n   let rgb888ToYyuv <- mkRgb888ToYyuv();\n   \n    Wire#(VideoData#(Rgb888))                    yyuvInputWire <- mkDWire(unpack(0));\n    Wire#(VideoData#(Rgb888))                        stage0Reg <- mkDWire(unpack(0));\n    Reg#(VideoData#(Yuv444Intermediates))            stage1Reg <- mkReg(unpack(0));\n    Reg#(VideoData#(Vector#(2,Vector#(3,Bit#(16))))) stage2Reg <- mkReg(unpack(0));\n    Reg#(VideoData#(Yuv444))                         stage3Reg <- mkReg(unpack(0));\n    Reg#(VideoData#(Yyuv))                           stage4Reg <- mkReg(unpack(0));\n    Reg#(Bool) evenOddPixelReg <- mkReg(False);\n   \n    rule stage1_rule;\n        let previous = stage0Reg;\n        let pixel = previous.pixel;\n        stage1Reg <= VideoData {\n            vsync: previous.vsync, hsync: previous.hsync, de: previous.de,\n            pixel: (previous.de != 0) ? rgbToYuvIntermediates(pixel) : unpack(0)\n        };\n    endrule\n\n    rule stage2_rule;\n        let previous = stage1Reg;\n       Vector#(4, Vector#(3, Bit#(16))) vprev = previous.pixel;\n       Vector#(2, Vector#(3, Bit#(16))) vnext;\n       vnext[0] = vadd(vprev[0], vprev[1]);\n       vnext[1] = vadd(vprev[2], vprev[3]);\n\n       stage2Reg <= VideoData {\n            vsync: previous.vsync, hsync: previous.hsync, de: previous.de,\n\t    pixel: (previous.de != 0) ? vnext : unpack(0)\n        };\n    endrule\n\n   rule stage3_rule;\n      let previous = stage2Reg;\n       Vector#(2, Vector#(3, Bit#(16))) vprev = previous.pixel;\n      Yuv444 pixel = yuv444FromVector(vrshift(vadd(vprev[0], vprev[1]), 8));\n\n      stage3Reg <= VideoData {\n            vsync: previous.vsync, hsync: previous.hsync, de: previous.de,\n\t pixel: (previous.de != 0) ? pixel : unpack(0) };\n   endrule\n\n   rule yuv_rule;\n      let v = stage3Reg;\n      if (v.de == 1)\n\t indication.yuv(v.pixel.y, v.pixel.u, v.pixel.v);\n   endrule\n\n   rule yyuv_input_rule;\n      rgb888ToYyuv.rgb888.put(yyuvInputWire);\n   endrule\n   rule yyuv_rule;\n      let v <- rgb888ToYyuv.yyuv.get();\n      if (v.de == 1)\n\t indication.yyuv(v.pixel.yy, v.pixel.uv);\n   endrule\n\n   interface YuvRequest request;\n   method Action toRgb(Bit#(8) r, Bit#(8) g, Bit#(8) b);\n      indication.rgb(r, g, b);\n   endmethod\n   method Action toYuv(Bit#(8) r, Bit#(8) g, Bit#(8) b);\n      stage0Reg <= VideoData { de: 1, vsync: 0, hsync: 0, pixel: Rgb888 { r:r, g:g, b:b } };\n   endmethod\n   \n   method Action toYyuv(Bit#(8) r, Bit#(8) g, Bit#(8) b);\n      yyuvInputWire <= VideoData { de: 1, vsync: 0, hsync: 0, pixel: Rgb888 { r:r, g:g, b:b } };\n   endmethod\n   endinterface\n\nendmodule\n"
  },
  {
    "path": "tests/yuv/testyuv.cpp",
    "content": "\n// Copyright (c) 2014 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\n#include <stdio.h>\n#include <stdlib.h>\n#include <unistd.h>\n#include <assert.h>\n#include <pthread.h>\n\n#include \"YuvIndication.h\"\n#include \"YuvRequest.h\"\n#include \"GeneratedTypes.h\"\n\nstruct rgb {\n  unsigned char r;\n  unsigned char g;\n  unsigned char b;\n  int operator==(const struct rgb &o) { return r == o.r && g == o.g && b == o.b; }\n};\nstruct yuv {\n  unsigned char y;\n  unsigned char u;\n  unsigned char v;\n  int operator==(const struct yuv &o) { return y == o.y && u == o.u && v == o.v; }\n};\n\nstruct rgb expected_rgb;\nstruct yuv expected_yuv;\n\nstatic int numTests = 0;\nclass YuvIndication : public YuvIndicationWrapper\n{  \npublic:\n  int cnt;\n  void incr_cnt(){\n    if (++cnt >= numTests)\n      exit(0);\n  }\n  void rgb(uint8_t r, uint8_t g, uint8_t b) {\n    fprintf(stderr, \"rgb(%d,%d,%d)\\n\", r, g, b);\n    struct rgb answer = {r, g, b};\n    assert(expected_rgb == answer);\n    incr_cnt();\n  }\n  void yuv(uint8_t y, uint8_t u, uint8_t v) {\n    fprintf(stderr, \"yuv(%d,%d,%d)\\n\", y, u, v);\n    struct yuv answer = {y,u,v};\n    assert(expected_yuv == answer);\n    incr_cnt();\n  }\n  void yyuv(uint8_t yy, uint8_t uv) {\n    fprintf(stderr, \"yyuv(%d,%d)\\n\", yy, uv);\n    //    assert(a == v1a);\n    incr_cnt();\n  }\n\n  YuvIndication(unsigned int id) : YuvIndicationWrapper(id), cnt(0){}\n};\n\nstruct yuv rgbtoyuv(unsigned short r, unsigned short g, unsigned short b)\n{\n  unsigned char y = ( 77*r + 150*g +  29*b + 0) >> 8;\n  unsigned char u = (-43*r -  85*g + 128*b + 128) >> 8;\n  unsigned char v = (128*r - 107*g -  21*b + 128) >> 8;\n  fprintf(stderr, \"rgb %d,%d,%d -> yuv %d,%d,%d\\n\", r, g, b, y, u, v);\n  struct yuv yuvret;\n  yuvret.y = y;\n  yuvret.u = u;\n  yuvret.v = v;\n  return yuvret;\n}\n\nint main(int argc, const char **argv)\n{\n  YuvIndication indication(IfcNames_YuvIndicationH2S);\n  YuvRequestProxy *device = new YuvRequestProxy(IfcNames_YuvRequestS2H);\n\n  struct rgb tests[] = {\n    { 0, 0, 0 },\n    { 1, 2, 3 },\n    { 128, 0, 0 },\n    { 0, 128, 0 },\n    { 0, 0, 128 },\n    { 255, 0, 0 },\n    { 0, 255, 0 },\n    { 0, 0, 255 },\n    { 255, 255, 255 },\n  };\n\n  numTests++;\n\n  for (unsigned int i = 0; i < sizeof(tests)/sizeof(struct rgb); i++) {\n    expected_rgb = tests[i];\n    expected_yuv = rgbtoyuv(tests[i].r, tests[i].g, tests[i].b);\n    numTests++; device->toRgb(tests[i].r, tests[i].g, tests[i].b);\n    numTests++; device->toYuv(tests[i].r, tests[i].g, tests[i].b);\n    numTests++; device->toYyuv(tests[i].r, tests[i].g, tests[i].b);\n    sleep(1);\n  }\n\n  expected_rgb = tests[0];\n  device->toRgb(tests[0].r, tests[0].g, tests[0].b); // now we're done\n\n  fprintf(stderr, \"Main::about to go to sleep\\n\");\n  while(true){sleep(2);}\n}\n"
  },
  {
    "path": "verilog/CONNECTNET.v",
    "content": "\n// Copyright (c) 2013-2014 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\n\nmodule CONNECTNET(IN, OUT);\noutput OUT;\ninput IN;\nassign OUT = IN;\nendmodule\n"
  },
  {
    "path": "verilog/CONNECTNET2.v",
    "content": "\n// Copyright (c) 2013-2014 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\nmodule CONNECTNET2(OUT1, OUT2, IN1, IN2);\noutput OUT1;\noutput OUT2;\ninput IN1;\ninput IN2;\nassign OUT1 = IN1;\nassign OUT2 = IN2;\nendmodule\n"
  },
  {
    "path": "verilog/FpgaReset.v",
    "content": "\n// Copyright (c) 2000-2012 Bluespec, Inc.\n\n// Permission is hereby granted, free of charge, to any person obtaining a copy\n// of this software and associated documentation files (the \"Software\"), to deal\n// in the Software without restriction, including without limitation the rights\n// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell\n// copies of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be included in\n// all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\n// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN\n// THE SOFTWARE.\n//\n// $Revision: 29455 $\n// $Date: 2012-08-27 22:02:09 +0000 (Mon, 27 Aug 2012) $\n\n`ifdef BSV_ASSIGNMENT_DELAY\n`else\n  `define BSV_ASSIGNMENT_DELAY\n`endif\n\n`ifdef BSV_POSITIVE_RESET\n  `define BSV_RESET_VALUE 1'b1\n  `define BSV_RESET_EDGE posedge\n`else\n  `define BSV_RESET_VALUE 1'b0\n  `define BSV_RESET_EDGE negedge\n`endif\n\n\n\n// Exposes FPGA GSR reset\nmodule FpgaReset (\n                  CLK,\n                  OUT_RST\n                  );\n\n   parameter          RSTDELAY = 1  ; // Width of reset shift reg\n\n   input              CLK ;\n   output             OUT_RST ;\n\n   reg [RSTDELAY:0]   reset_hold ;\n   wire [RSTDELAY+1:0] next_reset = {reset_hold, ~ `BSV_RESET_VALUE} ;\n\n   assign  OUT_RST = reset_hold[RSTDELAY] ;\n\n   always @( posedge CLK )      // reset is read synchronous with clock\n     begin\n        reset_hold <= `BSV_ASSIGNMENT_DELAY next_reset[RSTDELAY:0];\n     end // always @ ( posedge CLK )\n\n`ifdef BSV_NO_INITIAL_BLOCKS\n`else // not BSV_NO_INITIAL_BLOCKS\n   // synopsys translate_off\n   initial\n     begin\n        #0 ;\n        // initialize to reset\n        reset_hold = {(RSTDELAY + 1) {`BSV_RESET_VALUE }} ;\n     end\n   // synopsys translate_on\n`endif // BSV_NO_INITIAL_BLOCKS\n\nendmodule // PositiveReset\n"
  },
  {
    "path": "verilog/GenBIBUF.v",
    "content": "\n// Copyright (c) 2013-2014 Quanta Research Cambridge, Inc.\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\n\nmodule GenBIBUF(IO, PAD);\n\nparameter SIZE = 1;\ninout [SIZE-1:0]IO;\ninout [SIZE-1:0]PAD;\n\ngenvar i;\ngenerate\n    for(i = 0; i < SIZE; i = i + 1) begin\n        BIBUF(.PAD(PAD[i]), .IO(IO[i]));\n    end\nendgenerate\nendmodule\n"
  },
  {
    "path": "verilog/LinkInverter.v",
    "content": "// Copyright (c) 2015 The Connectal Project\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\n`ifdef BSV_ASSIGNMENT_DELAY\n`else\n  `define BSV_ASSIGNMENT_DELAY\n`endif\n\n`ifdef BSV_POSITIVE_RESET\n  `define BSV_RESET_VALUE 1'b1\n  `define BSV_RESET_EDGE posedge\n`else\n  `define BSV_RESET_VALUE 1'b0\n  `define BSV_RESET_EDGE negedge\n`endif\n\nmodule LinkInverter(CLK,\n\t\t  RST,\n\n\t\t  put,\n\t\t  EN_put,\n\t\t  RDY_put,\n\n\t\t  get,\n\t\t  EN_get,\n\t\t  RDY_get,\n                  modReady,\n                  inverseReady\n\t\t  );\n   parameter DATA_WIDTH = 1;\n\n   input CLK;\n   input RST;\n   output [DATA_WIDTH-1 : 0] get;\n   input  [DATA_WIDTH-1 : 0] put;\n   input \t\t   EN_get;\n   input \t\t   EN_put;\n   output \t\t   RDY_get;\n   output \t\t   RDY_put;\n   output \t\t   modReady;\n   output \t\t   inverseReady;\n\n   // will this work?\n   assign get = put;\n   assign RDY_get = 1;\n   assign RDY_put = 1;\n   assign modReady = EN_get;\n   assign inverseReady = EN_put;\nendmodule // LinkInverter\n"
  },
  {
    "path": "verilog/PositiveReset.v",
    "content": "\n// Copyright (c) 2000-2012 Bluespec, Inc.\n\n// Permission is hereby granted, free of charge, to any person obtaining a copy\n// of this software and associated documentation files (the \"Software\"), to deal\n// in the Software without restriction, including without limitation the rights\n// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell\n// copies of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be included in\n// all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\n// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN\n// THE SOFTWARE.\n//\n// $Revision: 29455 $\n// $Date: 2012-08-27 22:02:09 +0000 (Mon, 27 Aug 2012) $\n\n`ifdef BSV_ASSIGNMENT_DELAY\n`else\n  `define BSV_ASSIGNMENT_DELAY\n`endif\n\n`ifdef BSV_POSITIVE_RESET\n  `define BSV_RESET_VALUE 1'b1\n  `define BSV_RESET_EDGE posedge\n`else\n  `define BSV_RESET_VALUE 1'b0\n  `define BSV_RESET_EDGE negedge\n`endif\n\n\n\n// A synchronization module for resets.   Output resets are held for\n// RSTDELAY+1 cycles, RSTDELAY >= 0.   Both assertion and deassertions is\n// synchronized to the clock.\nmodule PositiveReset (\n                  IN_RST,\n                  CLK,\n                  OUT_RST\n                  );\n\n   parameter          RSTDELAY = 1  ; // Width of reset shift reg\n\n   input              CLK ;\n   input              IN_RST ;\n   output             OUT_RST ;\n\n   (* ASYNC_REG = \"true\" *)\n   reg                reset_meta ;\n   reg [RSTDELAY:1]   reset_hold ;\n   wire [RSTDELAY+1:0] next_reset = {reset_hold, reset_meta, 1'b0} ;\n\n   assign  OUT_RST = reset_hold[RSTDELAY] ;\n\n   always @( posedge CLK )      // reset is read synchronous with clock\n     begin\n        if (IN_RST == `BSV_RESET_VALUE)\n           begin\n              reset_meta <= 1;\n           end\n        else\n          begin\n              reset_meta <= 0;\n          end\n\n        if (reset_meta == 1)\n          begin\n              reset_hold <= `BSV_ASSIGNMENT_DELAY -1 ;\n          end\n        else\n          begin\n              reset_hold <= `BSV_ASSIGNMENT_DELAY next_reset[RSTDELAY:1];\n          end\n     end // always @ ( posedge CLK )\n\n`ifdef BSV_NO_INITIAL_BLOCKS\n`else // not BSV_NO_INITIAL_BLOCKS\n   // synopsys translate_off\n   initial\n     begin\n        #0 ;\n        // initialize out of reset forcing the designer to do one\n        reset_hold = 0 ;\n     end\n   // synopsys translate_on\n`endif // BSV_NO_INITIAL_BLOCKS\n\nendmodule // PositiveReset\n"
  },
  {
    "path": "verilog/PutInverter.v",
    "content": "// Copyright (c) 2015 The Connectal Project\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\n`ifdef BSV_ASSIGNMENT_DELAY\n`else\n  `define BSV_ASSIGNMENT_DELAY\n`endif\n\n`ifdef BSV_POSITIVE_RESET\n  `define BSV_RESET_VALUE 1'b1\n  `define BSV_RESET_EDGE posedge\n`else\n  `define BSV_RESET_VALUE 1'b0\n  `define BSV_RESET_EDGE negedge\n`endif\n\nmodule PutInverter(CLK,\n\t\t  RST,\n\n\t\t  put,\n\t\t  EN_put,\n\t\t  RDY_put,\n\n\t\t  get,\n\t\t  EN_get,\n\t\t  RDY_get\n\t\t  );\n   parameter DATA_WIDTH = 1;\n\n   input CLK;\n   input RST;\n   output [DATA_WIDTH-1 : 0] get;\n   input  [DATA_WIDTH-1 : 0] put;\n   input \t\t   EN_get;\n   input \t\t   EN_put;\n   output \t\t   RDY_get;\n   output \t\t   RDY_put;\n\n   // will this work?\n   assign get = put;\n   assign RDY_get = EN_put;\n   assign RDY_put = EN_get;\nendmodule // PutInverter\n"
  },
  {
    "path": "verilog/SyncFIFO.v",
    "content": "\n// Copyright (c) 2000-2012 Bluespec, Inc.\n\n// Permission is hereby granted, free of charge, to any person obtaining a copy\n// of this software and associated documentation files (the \"Software\"), to deal\n// in the Software without restriction, including without limitation the rights\n// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell\n// copies of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be included in\n// all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\n// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN\n// THE SOFTWARE.\n//\n// $Revision: 33367 $\n// $Date: 2014-02-18 17:46:14 +0000 (Tue, 18 Feb 2014) $\n\n`ifdef BSV_ASSIGNMENT_DELAY\n`else\n  `define BSV_ASSIGNMENT_DELAY\n`endif\n\n`ifdef BSV_POSITIVE_RESET\n  `define BSV_RESET_VALUE 1'b1\n  `define BSV_RESET_EDGE posedge\n`else\n  `define BSV_RESET_VALUE 1'b0\n  `define BSV_RESET_EDGE negedge\n`endif\n\n`ifdef BSV_RESET_FIFO_HEAD\n `define BSV_RESET_EDGE_HEAD or `BSV_RESET_EDGE dRST\n`else\n `define BSV_RESET_EDGE_HEAD\n`endif\n\n\n// A clock synchronization FIFO where the enqueue and dequeue sides are in\n// different clock domains.\n// There are no restrictions w.r.t. clock frequencies\n// The depth of the FIFO must be a power of 2 (2,4,8,...) since the\n// indexing uses a Gray code counter.\n// FULL and EMPTY signal are pessimistic, that is, they are asserted\n// immediately when the FIFO becomes FULL or EMPTY, but their deassertion\n// is delayed due to synchronization latency.\nmodule SyncFIFO(\n                sCLK,\n                sRST,\n                dCLK,\n                sENQ,\n                sD_IN,\n                sFULL_N,\n                dDEQ,\n                dD_OUT,\n                dEMPTY_N\n                ) ;\n\n\n   parameter                 dataWidth = 1 ;\n   parameter                 depth = 2 ; // minimum 2\n   parameter                 indxWidth = 1 ; // minimum 1\n\n   // input clock domain ports\n   input                     sCLK ;\n   input                     sRST ;\n   input                     sENQ ;\n   input [dataWidth -1 : 0]  sD_IN ;\n   output                    sFULL_N ;\n\n   // destination clock domain ports\n   input                     dCLK ;\n   input                     dDEQ ;\n   output                    dEMPTY_N ;\n   output [dataWidth -1 : 0] dD_OUT ;\n\n   // constants for bit masking of the gray code\n   wire [indxWidth : 0]      msbset  = ~({(indxWidth + 1){1'b1}} >> 1) ;\n   wire [indxWidth - 1 : 0]  msb2set = ~({(indxWidth + 0){1'b1}} >> 1) ;\n   wire [indxWidth : 0]      msb12set = msbset | {1'b0, msb2set} ; // 'b11000...\n\n   // FIFO Memory\n   (* ASYNC_REG = \"TRUE\" *)\n   reg [dataWidth -1 : 0]    fifoMem [0: depth -1 ] ;\n   (* ASYNC_REG = \"TRUE\" *)\n   reg [dataWidth -1 : 0]    dDoutReg ;\n\n   // Enqueue Pointer support\n   reg [indxWidth +1 : 0]    sGEnqPtr, sGEnqPtr1 ; // Flops\n   reg                       sNotFullReg ;\n   wire                      sNextNotFull, sFutureNotFull ;\n\n   // Dequeue Pointer support\n   reg [indxWidth+1 : 0]       dGDeqPtr, dGDeqPtr1 ; // Flops\n   reg                       dNotEmptyReg ;\n   wire                      dNextNotEmpty;\n\n   // Reset generation\n   wire                      dRST ;\n\n   // flops to sychronize enqueue and dequeue point across domains\n   (* ASYNC_REG = \"TRUE\" *)\n   reg [indxWidth : 0]       dSyncReg1, dEnqPtr ;\n   (* ASYNC_REG = \"TRUE\" *)\n   reg [indxWidth : 0]       sSyncReg1, sDeqPtr ;\n\n   wire [indxWidth - 1 :0]   sEnqPtrIndx, dDeqPtrIndx ;\n\n   // Resets\n   assign                    dRST = sRST ;\n\n   // Outputs\n   assign                    dD_OUT   = dDoutReg     ;\n   assign                    dEMPTY_N = dNotEmptyReg ;\n   assign                    sFULL_N  = sNotFullReg  ;\n\n   // Indexes are truncated from the Gray counter with parity\n   assign                    sEnqPtrIndx  = sGEnqPtr[indxWidth-1:0];\n   assign                    dDeqPtrIndx  = dGDeqPtr[indxWidth-1:0];\n\n   // Fifo memory write\n   always @(posedge sCLK)\n     begin\n        if ( sENQ )\n          fifoMem[sEnqPtrIndx] <= `BSV_ASSIGNMENT_DELAY sD_IN ;\n     end // always @ (posedge sCLK)\n\n   ////////////////////////////////////////////////////////////////////////\n   // Enqueue Pointer and increment logic\n   assign sNextNotFull   = (sGEnqPtr [indxWidth+1:1] ^ msb12set) != sDeqPtr ;\n   assign sFutureNotFull = (sGEnqPtr1[indxWidth+1:1] ^ msb12set) != sDeqPtr ;\n\n   always @(posedge sCLK or `BSV_RESET_EDGE sRST)\n     begin\n        if (sRST == `BSV_RESET_VALUE)\n          begin\n             sGEnqPtr    <= `BSV_ASSIGNMENT_DELAY {(indxWidth +2 ) {1'b0}} ;\n             sGEnqPtr1   <= `BSV_ASSIGNMENT_DELAY { {indxWidth {1'b0}}, 2'b11} ;\n             sNotFullReg <= `BSV_ASSIGNMENT_DELAY 1'b0 ; // Mark as full during reset to avoid spurious loads\n          end // if (sRST == `BSV_RESET_VALUE)\n        else\n           begin\n              if ( sENQ )\n                begin\n                   sGEnqPtr1   <= `BSV_ASSIGNMENT_DELAY incrGrayP( sGEnqPtr1 ) ;\n                   sGEnqPtr    <= `BSV_ASSIGNMENT_DELAY sGEnqPtr1 ;\n                   sNotFullReg <= `BSV_ASSIGNMENT_DELAY sFutureNotFull ;\n                end // if ( sENQ )\n              else\n                begin\n                   sNotFullReg <= `BSV_ASSIGNMENT_DELAY  sNextNotFull ;\n                end // else: !if( sENQ )\n           end // else: !if(sRST == `BSV_RESET_VALUE)\n     end // always @ (posedge sCLK or `BSV_RESET_EDGE sRST)\n\n\n   // Enqueue pointer synchronizer to dCLK\n   always @(posedge dCLK  or `BSV_RESET_EDGE dRST)\n     begin\n        if (dRST == `BSV_RESET_VALUE)\n          begin\n             dSyncReg1 <= `BSV_ASSIGNMENT_DELAY {(indxWidth + 1) {1'b0}} ;\n             dEnqPtr   <= `BSV_ASSIGNMENT_DELAY {(indxWidth + 1) {1'b0}} ;\n          end // if (dRST == `BSV_RESET_VALUE)\n        else\n          begin\n             dSyncReg1 <= `BSV_ASSIGNMENT_DELAY sGEnqPtr[indxWidth+1:1] ; // Clock domain crossing\n             dEnqPtr   <= `BSV_ASSIGNMENT_DELAY dSyncReg1 ;\n          end // else: !if(dRST == `BSV_RESET_VALUE)\n     end // always @ (posedge dCLK  or `BSV_RESET_EDGE dRST)\n   ////////////////////////////////////////////////////////////////////////\n\n\n   ////////////////////////////////////////////////////////////////////////\n   // Enqueue Pointer and increment logic\n   assign dNextNotEmpty   = dGDeqPtr[indxWidth+1:1]  != dEnqPtr ;\n\n   always @(posedge dCLK or `BSV_RESET_EDGE dRST)\n     begin\n        if (dRST == `BSV_RESET_VALUE)\n          begin\n             dGDeqPtr     <= `BSV_ASSIGNMENT_DELAY {(indxWidth + 2) {1'b0}} ;\n             dGDeqPtr1    <= `BSV_ASSIGNMENT_DELAY {{indxWidth {1'b0}}, 2'b11 } ;\n             dNotEmptyReg <= `BSV_ASSIGNMENT_DELAY 1'b0 ;\n          end // if (dRST == `BSV_RESET_VALUE)\n        else\n           begin\n              if ((!dNotEmptyReg || dDEQ) && dNextNotEmpty) begin\n                 dGDeqPtr     <= `BSV_ASSIGNMENT_DELAY dGDeqPtr1 ;\n                 dGDeqPtr1    <= `BSV_ASSIGNMENT_DELAY incrGrayP( dGDeqPtr1 );\n                 dNotEmptyReg <= `BSV_ASSIGNMENT_DELAY 1'b1;\n              end\n              else if (dDEQ && !dNextNotEmpty) begin\n                 dNotEmptyReg <= `BSV_ASSIGNMENT_DELAY 1'b0;\n              end\n           end // else: !if(dRST == `BSV_RESET_VALUE)\n     end // always @ (posedge dCLK or `BSV_RESET_EDGE dRST)\n\n\n   always @(posedge dCLK `BSV_RESET_EDGE_HEAD)\n     begin\n`ifdef  BSV_RESET_FIFO_HEAD\n        if (dRST == `BSV_RESET_VALUE)\n          begin\n             dDoutReg    <= `BSV_ASSIGNMENT_DELAY {dataWidth {1'b0}} ;\n          end // if (dRST == `BSV_RESET_VALUE)\n        else\n`endif\n          begin\n             if ((!dNotEmptyReg || dDEQ) && dNextNotEmpty) begin\n                dDoutReg     <= `BSV_ASSIGNMENT_DELAY fifoMem[dDeqPtrIndx] ;\n             end\n          end\n     end\n\n    // Dequeue pointer synchronized to sCLK\n    always @(posedge sCLK  or `BSV_RESET_EDGE sRST)\n      begin\n         if (sRST == `BSV_RESET_VALUE)\n           begin\n              sSyncReg1 <= `BSV_ASSIGNMENT_DELAY {(indxWidth + 1) {1'b0}} ;\n              sDeqPtr   <= `BSV_ASSIGNMENT_DELAY {(indxWidth + 1) {1'b0}} ; // When reset mark as not empty\n           end // if (sRST == `BSV_RESET_VALUE)\n         else\n           begin\n              sSyncReg1 <= `BSV_ASSIGNMENT_DELAY dGDeqPtr[indxWidth+1:1] ; // clock domain crossing\n              sDeqPtr   <= `BSV_ASSIGNMENT_DELAY sSyncReg1 ;\n           end // else: !if(sRST == `BSV_RESET_VALUE)\n      end // always @ (posedge sCLK  or `BSV_RESET_EDGE sRST)\n   ////////////////////////////////////////////////////////////////////////\n\n`ifdef BSV_NO_INITIAL_BLOCKS\n`else // not BSV_NO_INITIAL_BLOCKS\n   // synopsys translate_off\n   initial\n     begin : initBlock\n        integer i ;\n\n        // initialize the FIFO memory with aa's\n        for (i = 0; i < depth; i = i + 1)\n          begin\n             fifoMem[i] = {((dataWidth + 1)/2){2'b10}} ;\n          end\n        dDoutReg     = {((dataWidth + 1)/2){2'b10}} ;\n\n        // initialize the pointer\n        sGEnqPtr = {((indxWidth + 2)/2){2'b10}} ;\n        sGEnqPtr1 = sGEnqPtr ;\n        sNotFullReg = 1'b0 ;\n\n        dGDeqPtr = sGEnqPtr ;\n        dGDeqPtr1 = sGEnqPtr ;\n        dNotEmptyReg = 1'b0;\n\n\n        // initialize other registers\n        sSyncReg1 = sGEnqPtr ;\n        sDeqPtr   = sGEnqPtr ;\n        dSyncReg1 = sGEnqPtr ;\n        dEnqPtr   = sGEnqPtr ;\n     end // block: initBlock\n   // synopsys translate_on\n\n\n\n   // synopsys translate_off\n   initial\n     begin : parameter_assertions\n        integer ok ;\n        integer i, expDepth ;\n\n        ok = 1;\n        expDepth = 1 ;\n\n        // calculate x = 2 ** (indxWidth - 1)\n        for( i = 0 ; i < indxWidth ; i = i + 1 )\n          begin\n             expDepth = expDepth * 2 ;\n          end // for ( i = 0 ; i < indxWidth ; i = i + 1 )\n\n        if ( expDepth != depth )\n          begin\n             ok = 0;\n             $display ( \"ERROR SyncFiFO.v: index size and depth do not match;\" ) ;\n             $display ( \"\\tdepth must equal 2 ** index size. expected %0d\", expDepth );\n          end\n\n        #0\n        if ( ok == 0 ) $finish ;\n\n      end // initial begin\n   // synopsys translate_on\n`endif // BSV_NO_INITIAL_BLOCKS\n\n   function [indxWidth+1:0] incrGrayP ;\n      input [indxWidth+1:0] grayPin;\n\n      begin: incrGrayPBlock\n         reg [indxWidth :0] g;\n         reg                p ;\n         reg [indxWidth :0] i;\n\n         g = grayPin[indxWidth+1:1];\n         p = grayPin[0];\n         i = incrGray (g,p);\n         incrGrayP = {i,~p};\n      end\n   endfunction\n   function [indxWidth:0] incrGray ;\n      input [indxWidth:0] grayin;\n      input parity ;\n\n      begin: incrGrayBlock\n         integer               i;\n         reg [indxWidth: 0]    tempshift;\n         reg [indxWidth: 0]    flips;\n\n         flips[0] = ! parity ;\n         for ( i = 1 ; i < indxWidth ; i = i+1 )\n           begin\n              tempshift = grayin << (2 + indxWidth - i ) ;\n              flips[i]  = parity & grayin[i-1] & ~(| tempshift ) ;\n           end\n         tempshift = grayin << 2 ;\n         flips[indxWidth] = parity & ~(| tempshift ) ;\n\n         incrGray = flips ^ grayin ;\n      end\n   endfunction\n\nendmodule // FIFOSync\n\n\n`ifdef testBluespec\nmodule testSyncFIFO() ;\n   parameter dsize = 8;\n   parameter fifodepth = 32;\n   parameter fifoidx = 5;\n\n   wire      sCLK,  dCLK, dRST ;\n   wire      sENQ, dDEQ;\n   wire      sFULL_N, dEMPTY_N ;\n   wire [dsize -1:0] sDIN, dDOUT ;\n\n   reg [dsize -1:0]  sCNT, dCNT ;\n   reg sRST, sCLR ;\n\n   ClockGen#(15,14,10)  sc( sCLK );\n   ClockGen#(11,12,2600)  dc( dCLK );\n\n   initial\n     begin\n        sCNT = 0;\n        dCNT = 0;\n        sCLR = 1'b0 ;\n\n        sRST = `BSV_RESET_VALUE ;\n        $display( \"running test\" ) ;\n\n        $dumpfile(\"SyncFIFO.vcd\");\n        $dumpvars(5,testSyncFIFO) ;\n        $dumpon ;\n        #200 ;\n        sRST = !`BSV_RESET_VALUE ;\n\n\n        #100000 $finish ;\n     end // initial begin\n   initial\n     begin\n        #50000 ;\n        @(posedge sCLK ) ;\n        sCLR <= `BSV_ASSIGNMENT_DELAY 1'b1 ;\n        @(posedge sCLK ) ;\n        sCLR <= `BSV_ASSIGNMENT_DELAY 1'b0 ;\n\n      end\n\n   SyncFIFO #(dsize,fifodepth,fifoidx)\n     dut( sCLK, sRST, dCLK, sENQ, sDIN,\n          sFULL_N, // sCLR,\n          dDEQ, dDOUT, dEMPTY_N );\n\n   assign sDIN = sCNT ;\n   assign sENQ = sFULL_N ;\n\n\n   always @(posedge sCLK)\n     begin\n        if (sENQ )\n          begin\n             sCNT <= `BSV_ASSIGNMENT_DELAY sCNT + 1;\n          end\n      end // always @ (posedge sCLK)\n\n   assign dDEQ = dEMPTY_N ;\n\n   always @(posedge dCLK)\n     begin\n        if (dDEQ )\n           begin\n              $display( \"dequeing %d\", dDOUT ) ;\n           end\n     end // always @ (posedge dCLK)\n\nendmodule // testSyncFIFO\n`endif\n"
  },
  {
    "path": "verilog/SyncFIFO1.v",
    "content": "\n// Copyright (c) 2000-2012 Bluespec, Inc.\n\n// Permission is hereby granted, free of charge, to any person obtaining a copy\n// of this software and associated documentation files (the \"Software\"), to deal\n// in the Software without restriction, including without limitation the rights\n// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell\n// copies of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be included in\n// all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\n// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN\n// THE SOFTWARE.\n//\n// $Revision: 29441 $\n// $Date: 2012-08-27 21:58:03 +0000 (Mon, 27 Aug 2012) $\n\n`ifdef BSV_ASSIGNMENT_DELAY\n`else\n  `define BSV_ASSIGNMENT_DELAY\n`endif\n\n`ifdef BSV_POSITIVE_RESET\n  `define BSV_RESET_VALUE 1'b1\n  `define BSV_RESET_EDGE posedge\n`else\n  `define BSV_RESET_VALUE 1'b0\n  `define BSV_RESET_EDGE negedge\n`endif\n\n\n// A clock synchronization FIFO where the enqueue and dequeue sides are in\n// different clock domains.\n// The depth of the FIFO is strictly 1 element.   Implementation uses only\n// 1 register to minimize hardware\n// There are no restrictions w.r.t. clock frequencies\n// FULL and EMPTY signal are pessimistic, that is, they are asserted\n// immediately when the FIFO becomes FULL or EMPTY, but their deassertion\n// is delayed due to synchronization latency.\nmodule SyncFIFO1(\n                 sCLK,\n                 sRST,\n                 dCLK,\n                 sENQ,\n                 sD_IN,\n                 sFULL_N,\n                 dDEQ,\n                 dD_OUT,\n                 dEMPTY_N\n                 ) ;\n\n   parameter                 dataWidth = 1 ;\n\n   // input clock domain ports\n   input                     sCLK ;\n   input                     sRST ;\n   input                     sENQ ;\n   input [dataWidth -1 : 0]  sD_IN ;\n   output                    sFULL_N ;\n\n   // destination clock domain ports\n   input                     dCLK ;\n   input                     dDEQ ;\n   output                    dEMPTY_N ;\n   output [dataWidth -1 : 0] dD_OUT ;\n\n   // FIFO DATA\n   (* ASYNC_REG = \"TRUE\" *)\n   reg [dataWidth -1 : 0]    syncFIFO1Data ;\n\n   // Reset generation\n   wire                      dRST = sRST;\n\n   // sCLK registers\n   reg                       sEnqToggle,  sDeqToggle, sSyncReg1;\n   // dCLK registers\n   reg                       dEnqToggle,  dDeqToggle, dSyncReg1;\n\n   // output assignment\n   assign dD_OUT = syncFIFO1Data;\n   assign dEMPTY_N = dEnqToggle != dDeqToggle;\n   assign sFULL_N  = sEnqToggle == sDeqToggle;\n\n   always @(posedge sCLK or `BSV_RESET_EDGE sRST) begin\n      if (sRST == `BSV_RESET_VALUE) begin\n         syncFIFO1Data <= `BSV_ASSIGNMENT_DELAY  {dataWidth {1'b0}};\n         sEnqToggle    <= `BSV_ASSIGNMENT_DELAY  1'b0;\n         sSyncReg1     <= `BSV_ASSIGNMENT_DELAY  1'b0;\n         sDeqToggle    <= `BSV_ASSIGNMENT_DELAY  1'b1; // FIFO marked as full during reset\n      end\n      else begin\n         if (sENQ && (sEnqToggle == sDeqToggle)) begin\n            syncFIFO1Data <= `BSV_ASSIGNMENT_DELAY sD_IN;\n            sEnqToggle    <= `BSV_ASSIGNMENT_DELAY ! sEnqToggle;\n         end\n         sSyncReg1  <= `BSV_ASSIGNMENT_DELAY dDeqToggle; // clock domain crossing\n         sDeqToggle <= `BSV_ASSIGNMENT_DELAY sSyncReg1;\n      end\n   end\n\n   always @(posedge dCLK or `BSV_RESET_EDGE dRST) begin\n      if (dRST == `BSV_RESET_VALUE) begin\n         dEnqToggle    <= `BSV_ASSIGNMENT_DELAY  1'b0;\n         dSyncReg1     <= `BSV_ASSIGNMENT_DELAY  1'b0;\n         dDeqToggle    <= `BSV_ASSIGNMENT_DELAY  1'b0;\n      end\n      else begin\n         if (dDEQ && (dEnqToggle != dDeqToggle)) begin\n            dDeqToggle    <= `BSV_ASSIGNMENT_DELAY ! dDeqToggle;\n         end\n         dSyncReg1  <= `BSV_ASSIGNMENT_DELAY sEnqToggle; // clock domain crossing\n         dEnqToggle <= `BSV_ASSIGNMENT_DELAY dSyncReg1;\n      end\n   end\n\n`ifdef BSV_NO_INITIAL_BLOCKS\n`else // not BSV_NO_INITIAL_BLOCKS\n   // synopsys translate_off\n   initial begin : initBlock\n      syncFIFO1Data = {((dataWidth + 1)/2){2'b10}} ;\n      sEnqToggle = 1'b0;\n      sDeqToggle = 1'b0;\n      sSyncReg1 = 1'b0;\n\n      dEnqToggle = 1'b0;\n      dDeqToggle = 1'b0;\n      dSyncReg1 = 1'b0;\n   end\n   // synopsys translate_on\n`endif // !`ifdef BSV_NO_INITIAL_BLOCKS\n\n   // synopsys translate_off\n   always@(posedge sCLK)\n     begin: error_checks1\n        reg enqerror ;\n        enqerror = 0;\n        if (sRST == ! `BSV_RESET_VALUE)\n          begin\n             if ( sENQ && (sEnqToggle != sDeqToggle)) begin\n                enqerror = 1;\n                $display( \"Warning: SyncFIFO1: %m -- Enqueuing to a full fifo\" ) ;\n             end\n          end\n     end\n\n   always@(posedge dCLK)\n     begin: error_checks2\n        reg deqerror ;\n        deqerror = 0;\n        if (dRST == ! `BSV_RESET_VALUE)\n          begin\n             if ( dDEQ && (dEnqToggle == dDeqToggle)) begin\n                deqerror = 1;\n                $display( \"Warning: SyncFIFO1: %m -- Dequeuing from an empty full fifo\" ) ;\n             end\n          end\n     end // block: error_checks\n   // synopsys translate_on\n\nendmodule\n"
  },
  {
    "path": "verilog/SyncReset.v",
    "content": "\n// Copyright (c) 2000-2012 Bluespec, Inc.\n\n// Permission is hereby granted, free of charge, to any person obtaining a copy\n// of this software and associated documentation files (the \"Software\"), to deal\n// in the Software without restriction, including without limitation the rights\n// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell\n// copies of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be included in\n// all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\n// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN\n// THE SOFTWARE.\n//\n// $Revision: 29455 $\n// $Date: 2012-08-27 22:02:09 +0000 (Mon, 27 Aug 2012) $\n\n`ifdef BSV_ASSIGNMENT_DELAY\n`else\n  `define BSV_ASSIGNMENT_DELAY\n`endif\n\n`ifdef BSV_POSITIVE_RESET\n  `define BSV_RESET_VALUE 1'b1\n  `define BSV_RESET_EDGE posedge\n`else\n  `define BSV_RESET_VALUE 1'b0\n  `define BSV_RESET_EDGE negedge\n`endif\n\n\n\n// A synchronization module for resets.   Output resets are held for\n// RSTDELAY+1 cycles, RSTDELAY >= 0.   Both assertion and deassertions is\n// synchronized to the clock.\nmodule SyncReset (\n                  IN_RST,\n                  CLK,\n                  OUT_RST\n                  );\n\n   parameter          RSTDELAY = 1  ; // Width of reset shift reg\n\n   input              CLK ;\n   input              IN_RST ;\n   output             OUT_RST ;\n\n   (* ASYNC_REG = \"TRUE\" *)\n   reg                reset_meta;\n   reg [RSTDELAY:1]   reset_hold ;\n   wire [RSTDELAY+1:0] next_reset = {reset_hold, reset_meta, ~ `BSV_RESET_VALUE};\n   \n   assign  OUT_RST = reset_hold[RSTDELAY] ;\n\n   always @( posedge CLK )      // reset is read synchronous with clock\n     begin\n        if (IN_RST == `BSV_RESET_VALUE)\n           begin\n              reset_meta <= `BSV_ASSIGNMENT_DELAY `BSV_RESET_VALUE ;\n           end\n        else\n           begin\n              reset_meta <= `BSV_ASSIGNMENT_DELAY ~ `BSV_RESET_VALUE ;\n           end\n        if (reset_meta == `BSV_RESET_VALUE)\n          begin\n            reset_hold <= `BSV_ASSIGNMENT_DELAY {(RSTDELAY) {`BSV_RESET_VALUE}} ;\n          end\n        else\n          begin\n            reset_hold <= `BSV_ASSIGNMENT_DELAY next_reset[RSTDELAY:1];\n          end\n     end // always @ ( posedge CLK )\n\n`ifdef BSV_NO_INITIAL_BLOCKS\n`else // not BSV_NO_INITIAL_BLOCKS\n   // synopsys translate_off\n   initial\n     begin\n        #0 ;\n        // initialize out of reset forcing the designer to do one\n        reset_hold = {(RSTDELAY + 1) {~ `BSV_RESET_VALUE }} ;\n     end\n   // synopsys translate_on\n`endif // BSV_NO_INITIAL_BLOCKS\n\nendmodule // SyncReset\n"
  },
  {
    "path": "verilog/XsimDmaReadWrite.sv",
    "content": "// Copyright (c) 2015 The Connectal Project\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n//`timescale 1ns / 1ps\n\n`ifdef BSV_POSITIVE_RESET\n  `define BSV_RESET_VALUE 1'b1\n  `define BSV_RESET_EDGE posedge\n`else\n  `define BSV_RESET_VALUE 1'b0\n  `define BSV_RESET_EDGE negedge\n`endif\n\nmodule XsimDmaReadWrite(input CLK,\n\t\t\tinput \t\t  CLK_GATE,\n\t\t\tinput \t\t  RST,\n\n\t\t\tinput \t\t  en_init,\n\t\t\tinput [31:0] \t  init_id,\n\t\t\tinput [31:0] \t  init_handle,\n\t\t\tinput [31:0] \t  init_size,\n\n\t\t\tinput \t\t  en_initfd,\n\t\t\tinput [31:0] \t  initfd_id,\n\t\t\tinput [31:0] \t  initfd_fd,\n\n\t\t\tinput \t\t  en_idreturn,\n\t\t\tinput [31:0] \t  idreturn_id,\n\n\t\t\toutput \t\t  rdy_readrequest,\n\t\t\tinput \t\t  en_readrequest,\n\t\t\tinput [31:0] \t  readrequest_addr,\n\t\t\tinput [31:0] \t  readrequest_handle,\n\n\t\t\tinput \t\t  en_readresponse,\n\t\t\toutput \t\t  rdy_readresponse,\n\t\t\toutput [31:0] \t  readresponse_data,\n\n\t\t\tinput \t\t  en_write32,\n\t\t\tinput [31:0] \t  write32_addr,\n\t\t\tinput [31:0] \t  write32_handle,\n\t\t\tinput [31:0] \t  write32_data,\n\t\t\tinput [3:0]       write32_byteenable\n\t\t\t);\n\n   reg \t\t\t\t\t  readresponse_valid_reg;\n   reg [31:0] \t\t\t\t  readresponse_data_reg;\n\t\t\t\t  \n   import \"DPI-C\" function void simDma_init(input int id, input int handle, input int size);\n   import \"DPI-C\" function void simDma_initfd(input int id, input int fd);\n   import \"DPI-C\" function void simDma_idreturn(input int aid);\n   import \"DPI-C\" function void write_simDma32(input int handle, input int addr, input int data, input int byteenable);\n   import \"DPI-C\" function int read_simDma32(input int handle, input int addr);\n\n   assign rdy_readresponse = readresponse_valid_reg;\n   assign rdy_readrequest = !readresponse_valid_reg || en_readresponse;\n   assign readresponse_data = readresponse_data_reg;\n\n   always @(posedge CLK) begin\n      if (RST == `BSV_RESET_VALUE) begin\n\t readresponse_data_reg <= 32'haaaaaaaa;\n\t readresponse_valid_reg <= 0;\n      end\n      else begin\n\t if (en_init == 1)\n\t   simDma_init(init_id, init_handle, init_size);\n\t if (en_initfd == 1)\n\t   simDma_initfd(initfd_id, initfd_fd);\n\n\t if (en_idreturn == 1)\n\t   simDma_idreturn(idreturn_id);\n\t \n\t //if (en_readresponse) $display(\"xsimtop.readresponse data=%h\", readresponse_data_reg);\n\t if (en_readrequest == 1) begin\n\t    readresponse_data_reg <= read_simDma32(readrequest_handle, readrequest_addr);\n\t    //$display(\"xsimtop.readrequest handle=%h addr=%h\", readrequest_handle, readrequest_addr);\n\t    readresponse_valid_reg <= 1;\n\t end\n\t else if (en_readresponse) begin\n\t    readresponse_valid_reg <= 0;\n\t    readresponse_data_reg <= 32'hbbbbbbbb;\n\t end\n\t if (en_write32 == 1)\n\t   write_simDma32(write32_handle, write32_addr, write32_data, write32_byteenable);\n      end // else: !if(RST == BSV_RESET_VALUE)\n   end // always @ (posedge CLK)\nendmodule\n"
  },
  {
    "path": "verilog/XsimFinish.sv",
    "content": "// Copyright (c) 2015 The Connectal Project\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n//`timescale 1ns / 1ps\n\n`ifdef BSV_POSITIVE_RESET\n  `define BSV_RESET_VALUE 1'b1\n  `define BSV_RESET_EDGE posedge\n`else\n  `define BSV_RESET_VALUE 1'b0\n  `define BSV_RESET_EDGE negedge\n`endif\n"
  },
  {
    "path": "verilog/XsimLink.sv",
    "content": "// Copyright (c) 2015 The Connectal Project\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n//`timescale 1ns / 1ps\n\n`ifdef BSV_POSITIVE_RESET\n  `define BSV_RESET_VALUE 1'b1\n  `define BSV_RESET_EDGE posedge\n`else\n  `define BSV_RESET_VALUE 1'b0\n  `define BSV_RESET_EDGE negedge\n`endif\n\nmodule XsimLink #(parameter DATAWIDTH=32) (\n\t\t input RST,\n\t\t input CLK,\n\t\t input CLK_GATE,\n\t\t input start_listening,\n\t\t input en_start,\n\t\t input [31:0] start_linknumber,\n\t\t input [DATAWIDTH-1:0] tx_enq_v,\n\t\t input en_rx_deq,\n\t\t input en_tx_enq,\n\t\t output [DATAWIDTH-1:0] rx_first,\n\t\t output rdy_rx_first,\n\t\t output rdy_rx_deq,\n\t\t output rdy_tx_enq,\n\t\t output tx_not_full,\n\t\t output rx_not_empty,\n\t\t output link_up\n\t\t );\n   \n   reg \t\t\t[31:0] linknumber_reg;\n   reg \t\t\tstarted;\n   reg \t\t\tlisteningreg;\n   reg                  link_up_reg;\n   reg \t\t\trx_valid;\n   reg \t\t\ttx_valid;\n   reg \t\t\t[DATAWIDTH-1:0] rx_reg;\n   reg \t\t\t[DATAWIDTH-1:0] tx_reg;\n   int   \t\t       rx_val;\n   longint   \t\t       rx_val64;\n\n   import \"DPI-C\" function int  bsimLinkUp(input int linknumber, input bit listening);\n   import \"DPI-C\" function void bsimLinkOpen(input int linknumber, input bit listening);\n   import \"DPI-C\" function int bsimLinkCanReceive(input int linknumber, input bit listening);\n   import \"DPI-C\" function int bsimLinkCanTransmit(input int linknumber, input bit listening);\n   import \"DPI-C\" function int bsimLinkReceive32(input int linknumber, input bit listening);\n   import \"DPI-C\" function void bsimLinkTransmit32(input int linknumber, input bit listening, input int val);\n   import \"DPI-C\" function longint bsimLinkReceive64(input int linknumber, input bit listening);\n   import \"DPI-C\" function void bsimLinkTransmit64(input int linknumber, input bit listening, input longint val);\n\n   assign rx_first     = rx_reg;\n   assign rdy_rx_first = rx_valid && started;\n   assign rdy_rx_deq   = rx_valid && started;\n   assign rdy_tx_enq   = !tx_valid && started;\n   assign tx_not_full  = !tx_valid;\n   assign rx_not_empty = rx_valid;\n   assign link_up      = link_up_reg;\n\n   always @(posedge CLK) begin\n      if (RST == `BSV_RESET_VALUE) begin\n\t started <= 0;\n\t linknumber_reg <= 0;\n\t link_up_reg <= 0;\n\t listeningreg <= 0;\n\t rx_valid <= 0;\n\t tx_valid  <= 0;\n\t rx_reg <= 32'haaaaaaaa;\n\t tx_reg <= 32'haaaaaaaa;\n      end\n      else begin\n\t if (en_start == 1 && started == 0) begin\n\t    //$display(\"start linknumber=%d listening=%d\", start_linknumber, start_listening);\n\t    bsimLinkOpen(start_linknumber, start_listening);\n\t    linknumber_reg <= start_linknumber;\n\t    listeningreg <= start_listening;\n\t    started <= 1;\n\t end\n\t \n\t if (started && !rx_valid && bsimLinkCanReceive(linknumber_reg, listeningreg)) begin\n\t    if (DATAWIDTH == 32) begin\n\t       rx_val = bsimLinkReceive32(linknumber_reg, listeningreg);\n\t       rx_reg <= rx_val;\n\t    end\n\t    else begin\n\t       rx_val64 = bsimLinkReceive64(linknumber_reg, listeningreg);\n\t       rx_reg <= rx_val64;\n\t    end\n\t    rx_valid <= 1;\n\t    //$display(\"link %d.%d received %d %h\", linknumber_reg, listeningreg, rx_valid, rx_val);\n\t end\n\t if (started && tx_valid && bsimLinkCanTransmit(linknumber_reg, listeningreg)) begin\n\t    //$display(\"link %d.%d transmitting %d %h\", linknumber_reg, listeningreg, tx_valid, tx_reg);\n\t    if (DATAWIDTH == 32)\n\t      bsimLinkTransmit32(linknumber_reg, listeningreg, tx_reg);\n\t    else\n\t      bsimLinkTransmit64(linknumber_reg, listeningreg, tx_reg);\n\t    tx_valid <= 0;\n\t end\n\t if (started && en_rx_deq) begin\n\t    rx_valid <= 0;\n\t    //$display(\"%d.%d rx_deq %d %h\", linknumber_reg, listeningreg, rx_valid, rx_reg);\n\t end\n\t if (started && en_tx_enq && !tx_valid) begin\n\t    tx_valid <= 1;\n\t    tx_reg <= tx_enq_v;\n\t    //$display(\"%d.%d tx_enq %h\", linknumber_reg, listeningreg, tx_enq_v);\n\t end\n\t link_up_reg <= bsimLinkUp(linknumber_reg, listeningreg);\n      end\n   end\n\nendmodule\n"
  },
  {
    "path": "verilog/XsimSink.sv",
    "content": "// Copyright (c) 2015 The Connectal Project\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n//`timescale 1ns / 1ps\n\n`ifdef BSV_POSITIVE_RESET\n  `define BSV_RESET_VALUE 1'b1\n  `define BSV_RESET_EDGE posedge\n`else\n  `define BSV_RESET_VALUE 1'b0\n  `define BSV_RESET_EDGE negedge\n`endif\n\nmodule XsimSink(input CLK, input CLK_GATE, input RST, input [31:0] portal, output RDY_beat, input EN_beat, output [31:0] beat);\n   reg     valid_reg;\n   reg \t   [31:0] beat_reg;\n   \n   import \"DPI-C\" function longint dpi_msgSink_beat(input int portal);\n\n   assign RDY_beat = valid_reg;\n   assign beat = beat_reg;\n   \n   always @(posedge CLK) begin\n      if (RST == `BSV_RESET_VALUE) begin\n\t valid_reg <= 0;\n\t beat_reg <= 32'haaaaaaaa;\n      end\n      else if (EN_beat == 1 || valid_reg == 0) begin\n`ifndef BOARD_cvc\n\t automatic longint v = dpi_msgSink_beat(portal);\n\t valid_reg <= v[32];\n\t beat_reg <= v[31:0];\n`else\n\t { valid_reg, beat_reg } <= dpi_msgSink_beat(portal);\n`endif\n      end\n   end\nendmodule\n"
  },
  {
    "path": "verilog/XsimSource.sv",
    "content": "// Copyright (c) 2015 The Connectal Project\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n//`timescale 1ns / 1ps\n\n`ifdef BSV_POSITIVE_RESET\n  `define BSV_RESET_VALUE 1'b1\n  `define BSV_RESET_EDGE posedge\n`else\n  `define BSV_RESET_VALUE 1'b0\n  `define BSV_RESET_EDGE negedge\n`endif\n\nmodule XsimSource( input CLK, input CLK_GATE, input RST, input [31:0] portal, input en_beat, input [31:0] beat);\n\n   import \"DPI-C\" function void dpi_msgSource_beat(input int portal, input int beat);\n\n   always @(posedge CLK) begin\n      if (en_beat)\n          dpi_msgSource_beat(portal, beat);\n   end\nendmodule\n"
  },
  {
    "path": "verilog/altera/BRAM1.v",
    "content": "// Copyright (c) 2000-2011 Bluespec, Inc.\n\n// Permission is hereby granted, free of charge, to any person obtaining a copy\n// of this software and associated documentation files (the \"Software\"), to deal\n// in the Software without restriction, including without limitation the rights\n// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell\n// copies of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be included in\n// all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\n// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN\n// THE SOFTWARE.\n//\n// $Revision$\n// $Date$\n\n`ifdef BSV_ASSIGNMENT_DELAY\n`else\n `define BSV_ASSIGNMENT_DELAY\n`endif\n\n// Single-Ported BRAM\nmodule BRAM1(CLK,\n             EN,\n             WE,\n             ADDR,\n             DI,\n             DO\n             );\n\n   parameter                      PIPELINED  = 0;\n   parameter                      ADDR_WIDTH = 1;\n   parameter                      DATA_WIDTH = 1;\n   parameter                      MEMSIZE    = 1;\n\n   input                          CLK;\n   input                          EN;\n   input                          WE;\n   input [ADDR_WIDTH-1:0]         ADDR;\n   input [DATA_WIDTH-1:0]         DI;\n   output [DATA_WIDTH-1:0]        DO;\n\n   wire                           REN = EN & !WE;\n   wire                           WEN = EN & WE;\n      \n   altsyncram\n     #(\n       .width_a                            (DATA_WIDTH),\n       .widthad_a                          (ADDR_WIDTH),\n       .numwords_a                         (MEMSIZE),\n       .outdata_reg_a                      ((PIPELINED) ? \"CLOCK0\" : \"UNREGISTERED\"),\n       .address_aclr_a                     (\"NONE\"),\n       .outdata_aclr_a                     (\"NONE\"),\n       .indata_aclr_a                      (\"NONE\"),\n       .wrcontrol_aclr_a                   (\"NONE\"),\n       .byteena_aclr_a                     (\"NONE\"),\n       .width_byteena_a                    (1),\n\n       .width_b                            (1),//\n       .widthad_b                          (1),//\n       .numwords_b                         (0),//\n       .rdcontrol_reg_b                    (\"CLOCK1\"),//\n       .address_reg_b                      (\"CLOCK1\"),//\n       .outdata_reg_b                      (\"UNREGISTERED\"),//\n       .outdata_aclr_b                     (\"NONE\"),//\n       .rdcontrol_aclr_b                   (\"NONE\"),//\n       .indata_reg_b                       (\"CLOCK1\"),//\n       .wrcontrol_wraddress_reg_b          (\"CLOCK1\"),//\n       .byteena_reg_b                      (\"CLOCK1\"),//\n       .indata_aclr_b                      (\"NONE\"),//\n       .wrcontrol_aclr_b                   (\"NONE\"),//\n       .address_aclr_b                     (\"NONE\"),//\n       .byteena_aclr_b                     (\"NONE\"),//\n       .width_byteena_b                    (1),//\n\n       .clock_enable_input_a               (\"BYPASS\"),\n       .clock_enable_output_a              (\"BYPASS\"),\n       .clock_enable_input_b               (\"NORMAL\"),//\n       .clock_enable_output_b              (\"NORMAL\"),//\n\n       .clock_enable_core_a                (\"USE_INPUT_CLKEN\"),//\n       .clock_enable_core_b                (\"USE_INPUT_CLKEN\"),//\n       .read_during_write_mode_port_a      (\"NEW_DATA_NO_NBE_READ\"),\n       .read_during_write_mode_port_b      (\"NEW_DATA_NO_NBE_READ\"),\n\n       .enable_ecc                         (\"FALSE\"),//\n       .width_eccstatus                    (3),//\n       .ecc_pipeline_stage_enabled         (\"FALSE\"),//\n\n       .operation_mode                     (\"SINGLE_PORT\"),\n       .byte_size                          (8),//\n       .read_during_write_mode_mixed_ports (\"DONT_CARE\"),//\n       .ram_block_type                     (\"AUTO\"),//\n       .init_file                          (\"UNUSED\"),//\n       .init_file_layout                   (\"UNUSED\"),//\n       .maximum_depth                      (MEMSIZE), // number of elements in memory\n       .intended_device_family             (\"Stratix\"),//\n       .lpm_hint                           (\"ENABLE_RUNTIME_MOD=NO\"),\n       .lpm_type                           (\"altsyncram\"),//\n       .implement_in_les                   (\"OFF\"), //\n       .power_up_uninitialized             (\"FALSE\")\n       )\n   RAM\n     (\n      .wren_a                              (WEN),\n      .rden_a                              (REN),\n      .data_a                              (DI),\n      .address_a                           (ADDR),\n      .clock0                              (CLK),\n      .clocken0                            (1'b1),\n      .clocken1                            (1'b1),\n      .aclr0                               (1'b0),\n      .byteena_a                           (1'b1),\n      .addressstall_a                      (1'b0),\n      .q_a                                 (DO),\n\n      .wren_b                              (1'b0),\n      .rden_b                              (1'b1),\n      .data_b                              (1'b1),\n      .address_b                           (1'b1),\n      .clock1                              (1'b1),\n      .clocken2                            (1'b1),\n      .clocken3                            (1'b1),\n      .aclr1                               (1'b0),\n      .byteena_b                           (1'b1),\n      .addressstall_b                      (1'b0),\n      .q_b                                 (),\n\n      .eccstatus                           ()\n      );\n   \n\nendmodule // BRAM1\n"
  },
  {
    "path": "verilog/altera/BRAM1BE.v",
    "content": "// Copyright (c) 2000-2011 Bluespec, Inc.\n\n// Permission is hereby granted, free of charge, to any person obtaining a copy\n// of this software and associated documentation files (the \"Software\"), to deal\n// in the Software without restriction, including without limitation the rights\n// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell\n// copies of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be included in\n// all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\n// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN\n// THE SOFTWARE.\n//\n// $Revision: 31023 $\n// $Date: 2013-04-15 16:20:17 +0000 (Mon, 15 Apr 2013) $\n\n`ifdef BSV_ASSIGNMENT_DELAY\n`else\n `define BSV_ASSIGNMENT_DELAY\n`endif\n\n// Single-Ported BRAM with byte enables\nmodule BRAM1BE(CLK,\n               EN,\n               WE,\n               ADDR,\n               DI,\n               DO\n              );\n\n   parameter                      PIPELINED  = 0;\n   parameter                      ADDR_WIDTH = 1;\n   parameter                      DATA_WIDTH = 1;\n   parameter                      CHUNKSIZE  = 1;\n   parameter                      WE_WIDTH   = 1;\n   parameter                      MEMSIZE    = 1;\n\n   input                          CLK;\n   input                          EN;\n   input [WE_WIDTH-1:0]           WE;\n   input [ADDR_WIDTH-1:0]         ADDR;\n   input [DATA_WIDTH-1:0]         DI;\n   output [DATA_WIDTH-1:0]        DO;\n\n   reg [DATA_WIDTH-1:0]           RAM[0:MEMSIZE-1];\n   reg [DATA_WIDTH-1:0]           DO_R;\n   reg [DATA_WIDTH-1:0]           DO_R2;\n\n\n`ifdef BSV_NO_INITIAL_BLOCKS\n`else\n   // synopsys translate_off\n   initial\n   begin : init_block\n      integer   i;\n      for (i = 0; i < MEMSIZE; i = i + 1) begin\n         RAM[i] = { ((DATA_WIDTH+1)/2) { 2'b10 } };\n      end\n      DO_R  = { ((DATA_WIDTH+1)/2) { 2'b10 } };\n      DO_R2 = { ((DATA_WIDTH+1)/2) { 2'b10 } };\n   end\n   // synopsys translate_on\n`endif // !`ifdef BSV_NO_INITIAL_BLOCKS\n\n   // iverilog does not support the full verilog-2001 language.  This fixes that for simulation.\n`ifdef __ICARUS__\n   reg [DATA_WIDTH-1:0]  MASK, IMASK;\n   reg [DATA_WIDTH-1:0]  DATA;\n   wire [DATA_WIDTH-1:0] DATAwr;\n\n   assign DATAwr = RAM[ADDR] ;\n\n   always @(WE or DI or DATAwr) begin : combo1\n      integer j;\n      MASK  = 0;\n      IMASK = 0;\n\n      for(j = WE_WIDTH-1; j >= 0; j = j - 1) begin\n         if (WE[j]) MASK = (MASK << 8) | { { DATA_WIDTH-CHUNKSIZE { 1'b0 } }, { CHUNKSIZE { 1'b1 } } };\n         else       MASK = (MASK << 8);\n      end\n      IMASK = ~MASK;\n\n      DATA = (DATAwr & IMASK) | (DI & MASK);\n   end\n\n   always @(posedge CLK) begin\n      if (EN) begin\n         if (WE) begin\n            RAM[ADDR] <= `BSV_ASSIGNMENT_DELAY DATA;\n            DO_R      <= `BSV_ASSIGNMENT_DELAY DATA;\n         end\n         else begin\n            DO_R      <= `BSV_ASSIGNMENT_DELAY RAM[ADDR];\n         end\n      end\n   end\n`else\n   generate\n      genvar i;\n      for(i = 0; i < WE_WIDTH; i = i + 1) begin: porta_we\n         always @(posedge CLK) begin\n            if (EN) begin\n               if (WE[i]) begin\n                  RAM[ADDR][((i+1)*CHUNKSIZE)-1 : i*CHUNKSIZE] <= `BSV_ASSIGNMENT_DELAY DI[((i+1)*CHUNKSIZE)-1 : i*CHUNKSIZE];\n                  DO_R[((i+1)*CHUNKSIZE)-1 : i*CHUNKSIZE]      <= `BSV_ASSIGNMENT_DELAY DI[((i+1)*CHUNKSIZE)-1 : i*CHUNKSIZE];\n               end\n               else begin\n                  DO_R[((i+1)*CHUNKSIZE)-1 : i*CHUNKSIZE]      <= `BSV_ASSIGNMENT_DELAY RAM[ADDR][((i+1)*CHUNKSIZE)-1 : i*CHUNKSIZE];\n               end\n            end\n         end\n      end      \n   endgenerate\n\n`endif // !`ifdef __ICARUS__\n\n   // Output driver\n   always @(posedge CLK) begin\n      DO_R2 <= `BSV_ASSIGNMENT_DELAY DO_R;\n   end\n   \n   assign DO = (PIPELINED) ? DO_R2 : DO_R;\n\nendmodule // BRAM1BE\n"
  },
  {
    "path": "verilog/altera/BRAM2.v",
    "content": "\n// Copyright (c) 2000-2009 Bluespec, Inc.\n\n// Permission is hereby granted, free of charge, to any person obtaining a copy\n// of this software and associated documentation files (the \"Software\"), to deal\n// in the Software without restriction, including without limitation the rights\n// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell\n// copies of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be included in\n// all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\n// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN\n// THE SOFTWARE.\n//\n// $Revision: 24080 $\n// $Date: 2011-05-18 19:32:52 +0000 (Wed, 18 May 2011) $\n\n`ifdef BSV_ASSIGNMENT_DELAY\n`else\n `define BSV_ASSIGNMENT_DELAY\n`endif\n\n// Dual-Ported BRAM (READ FIRST)\nmodule BRAM2(CLKA,\n             ENA,\n             WEA,\n             ADDRA,\n             DIA,\n             DOA,\n             CLKB,\n             ENB,\n             WEB,\n             ADDRB,\n             DIB,\n             DOB\n             );\n\n   parameter                      PIPELINED  = 0;\n   parameter                      ADDR_WIDTH = 1;\n   parameter                      DATA_WIDTH = 1;\n   parameter                      MEMSIZE    = 1;\n\n   input                          CLKA;\n   input                          ENA;\n   input                          WEA;\n   input [ADDR_WIDTH-1:0]         ADDRA;\n   input [DATA_WIDTH-1:0]         DIA;\n   output [DATA_WIDTH-1:0]        DOA;\n\n   input                          CLKB;\n   input                          ENB;\n   input                          WEB;\n   input [ADDR_WIDTH-1:0]         ADDRB;\n   input [DATA_WIDTH-1:0]         DIB;\n   output [DATA_WIDTH-1:0]        DOB;\n\n   reg [DATA_WIDTH-1:0]           RAM[0:MEMSIZE-1] /* synthesis syn_ramstyle=\"no_rw_check\" */ ;\n   reg [DATA_WIDTH-1:0]           DOA_R;\n   reg [DATA_WIDTH-1:0]           DOB_R;\n   reg [DATA_WIDTH-1:0]           DOA_D1_R;\n   reg [DATA_WIDTH-1:0]           DOB_D1_R;\n\n`ifdef BSV_NO_INITIAL_BLOCKS\n`else\n   // synopsys translate_off\n   integer                        i;\n   initial\n   begin : init_block\n      for (i = 0; i < MEMSIZE; i = i + 1) begin\n         RAM[i] = { ((DATA_WIDTH+1)/2) { 2'b10 } };\n      end\n      DOA_R = { ((DATA_WIDTH+1)/2) { 2'b10 } };\n      DOB_R = { ((DATA_WIDTH+1)/2) { 2'b10 } };\n      DOA_D1_R = { ((DATA_WIDTH+1)/2) { 2'b10 } };\n      DOB_D1_R = { ((DATA_WIDTH+1)/2) { 2'b10 } };\n   end\n   // synopsys translate_on\n`endif // !`ifdef BSV_NO_INITIAL_BLOCKS\n\n   always @(posedge CLKA) begin\n      DOA_R <= `BSV_ASSIGNMENT_DELAY RAM[ADDRA];\n      if (ENA) begin\n         if (WEA) begin\n           RAM[ADDRA] <= `BSV_ASSIGNMENT_DELAY DIA;\n\t end\n      end\n   end\n\n   always @(posedge CLKB) begin\n      DOB_R <= `BSV_ASSIGNMENT_DELAY RAM[ADDRB];\n      if (ENB) begin\n         if (WEB) begin\n           RAM[ADDRB] <= `BSV_ASSIGNMENT_DELAY DIB;\n\t end\n      end\n   end\n\n   // Pipeline\n   always @(posedge CLKA)\n      DOA_D1_R <= DOA_R;\n\n   always @(posedge CLKB)\n      DOB_D1_R <= DOB_R;\n\n   // Output drivers\n   assign DOA = (PIPELINED) ? DOA_D1_R : DOA_R;\n   assign DOB = (PIPELINED) ? DOB_D1_R : DOB_R;\n\nendmodule // BRAM2\n"
  },
  {
    "path": "verilog/altera/siv_gen2x8/siv_gen2x8.v",
    "content": "// megafunction wizard: %IP Compiler for PCI Express v14.0%\n// GENERATION: XML\n// ============================================================\n// Megafunction Name(s):\n// ============================================================\n\n//Legal Notice: (C)2015 Altera Corporation. All rights reserved.  Your\n//use of Altera Corporation's design tools, logic functions and other\n//software and tools, and its AMPP partner logic functions, and any\n//output files any of the foregoing (including device programming or\n//simulation files), and any associated documentation or information are\n//expressly subject to the terms and conditions of the Altera Program\n//License Subscription Agreement or other applicable license agreement,\n//including, without limitation, that your use is for the sole purpose\n//of programming logic devices manufactured by Altera and sold by Altera\n//or its authorized distributors.  Please refer to the applicable\n//agreement for further details.\n\n\n// =========================================================\n// IP Compiler for PCI Express Wizard Data\n// ===============================\n// DO NOT EDIT FOLLOWING DATA\n// @Altera, IP Toolbench@\n// Warning: If you modify this section, IP Compiler for PCI Express Wizard may not be able to reproduce your chosen configuration.\n// \n// Retrieval info: <?xml version=\"1.0\"?>\n// Retrieval info: <MEGACORE title=\"IP Compiler for PCI Express\"  version=\"14.0\"  build=\"200\"  iptb_version=\"1.3.0 Build 200\"  format_version=\"120\" >\n// Retrieval info:  <NETLIST_SECTION class=\"altera.ipbu.flowbase.netlist.model.MVCModel\"  active_core=\"altpcie_hip_pipen1b\" >\n// Retrieval info:   <STATIC_SECTION>\n// Retrieval info:    <PRIVATES>\n// Retrieval info:     <NAMESPACE name = \"parameterization\">\n// Retrieval info:      <PRIVATE name = \"p_pcie_phy\" value=\"Stratix IV GX\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pcie_port_type\" value=\"Native Endpoint\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pcie_tag_supported\" value=\"64\"  type=\"INTEGER\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pcie_msi_message_requested\" value=\"4\"  type=\"INTEGER\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pcie_low_priority_virtual_channels\" value=\"0\"  type=\"INTEGER\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pcie_retry_fifo_depth\" value=\"64\"  type=\"INTEGER\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pcie_nfts_common_clock\" value=\"255\"  type=\"INTEGER\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pcie_nfts_separate_clock\" value=\"255\"  type=\"INTEGER\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pcie_exp_rom_bar_used\" value=\"0\"  type=\"BOOLEAN\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pcie_link_common_clock\" value=\"1\"  type=\"BOOLEAN\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pcie_advanced_error_reporting\" value=\"0\"  type=\"BOOLEAN\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pcie_ecrc_check\" value=\"0\"  type=\"BOOLEAN\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pcie_ecrc_generation\" value=\"0\"  type=\"BOOLEAN\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pcie_power_indicator\" value=\"0\"  type=\"BOOLEAN\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pcie_attention_indicator\" value=\"0\"  type=\"BOOLEAN\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pcie_attention_button\" value=\"0\"  type=\"BOOLEAN\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pcie_msi_message_64bits_address_capable\" value=\"1\"  type=\"BOOLEAN\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pcie_auto_configure_retry_buffer\" value=\"1\"  type=\"BOOLEAN\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pcie_implement_data_register\" value=\"0\"  type=\"BOOLEAN\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pcie_device_init_required\" value=\"0\"  type=\"BOOLEAN\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pcie_enable_L1_aspm\" value=\"0\"  type=\"BOOLEAN\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pcie_rate_match_fifo\" value=\"1\"  type=\"BOOLEAN\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pcie_enable_fast_recovery\" value=\"1\"  type=\"BOOLEAN\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"SOPCSystemName\" value=\"N/A\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"actualBAR0AvalonAddress\" value=\"0\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"actualBAR0Size\" value=\"0\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"actualBAR1AvalonAddress\" value=\"0\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"actualBAR1Size\" value=\"0\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"actualBAR2AvalonAddress\" value=\"0\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"actualBAR2Size\" value=\"0\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"actualBAR3AvalonAddress\" value=\"0\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"actualBAR3Size\" value=\"0\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"actualBAR4AvalonAddress\" value=\"0\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"actualBAR4Size\" value=\"0\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"actualBAR5AvalonAddress\" value=\"0\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"actualBAR5Size\" value=\"0\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"allowedDeviceFamilies\" value=\"[Arria II GX, Arria II GZ, Arria V, Arria V GZ, Cyclone IV E, Cyclone IV GX, Cyclone V, MAX II, MAX V, Stratix IV, Stratix V]\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"altgx_generated\" value=\"0\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"clockSource\" value=\"N/A\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"contextState\" value=\"NativeContext\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"deviceFamily\" value=\"Stratix IV\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"ordering_code\" value=\"IP-PCIE/4\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_avalon_hardwired_address_map\" value=\"true\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_avalon_hw_pci_address_00\" value=\"0x0000000000000000\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_avalon_hw_pci_address_00_type\" value=\"Memory32Bit\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_avalon_hw_pci_address_01\" value=\"0x0000000000000000\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_avalon_hw_pci_address_01_type\" value=\"Memory32Bit\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_avalon_hw_pci_address_02\" value=\"0x0000000000000000\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_avalon_hw_pci_address_02_type\" value=\"Memory32Bit\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_avalon_hw_pci_address_03\" value=\"0x0000000000000000\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_avalon_hw_pci_address_03_type\" value=\"Memory32Bit\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_avalon_hw_pci_address_04\" value=\"0x0000000000000000\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_avalon_hw_pci_address_04_type\" value=\"Memory32Bit\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_avalon_hw_pci_address_05\" value=\"0x0000000000000000\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_avalon_hw_pci_address_05_type\" value=\"Memory32Bit\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_avalon_hw_pci_address_06\" value=\"0x0000000000000000\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_avalon_hw_pci_address_06_type\" value=\"Memory32Bit\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_avalon_hw_pci_address_07\" value=\"0x0000000000000000\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_avalon_hw_pci_address_07_type\" value=\"Memory32Bit\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_avalon_hw_pci_address_08\" value=\"0x0000000000000000\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_avalon_hw_pci_address_08_type\" value=\"Memory32Bit\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_avalon_hw_pci_address_09\" value=\"0x0000000000000000\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_avalon_hw_pci_address_09_type\" value=\"Memory32Bit\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_avalon_hw_pci_address_10\" value=\"0x0000000000000000\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_avalon_hw_pci_address_10_type\" value=\"Memory32Bit\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_avalon_hw_pci_address_11\" value=\"0x0000000000000000\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_avalon_hw_pci_address_11_type\" value=\"Memory32Bit\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_avalon_hw_pci_address_12\" value=\"0x0000000000000000\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_avalon_hw_pci_address_12_type\" value=\"Memory32Bit\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_avalon_hw_pci_address_13\" value=\"0x0000000000000000\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_avalon_hw_pci_address_13_type\" value=\"Memory32Bit\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_avalon_hw_pci_address_14\" value=\"0x0000000000000000\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_avalon_hw_pci_address_14_type\" value=\"Memory32Bit\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_avalon_hw_pci_address_15\" value=\"0x0000000000000000\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_avalon_hw_pci_address_15_type\" value=\"Memory32Bit\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_avalon_pane_count\" value=\"1\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_avalon_pane_size\" value=\"20\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_enable_pcie_hip_dprio\" value=\"Disable\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pci_64bit_bar\" value=\"false\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pci_64bit_bus\" value=\"true\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pci_66mhz\" value=\"true\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pci_allow_param_readback\" value=\"false\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pci_altera_arbiter\" value=\"false\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pci_arbited_devices\" value=\"2\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pci_arbiter\" value=\"false\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pci_bar_0_auto_avalon_address\" value=\"false\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pci_bar_0_auto_sized\" value=\"false\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pci_bar_0_avalon_address\" value=\"0\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pci_bar_0_hardwired\" value=\"false\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pci_bar_0_pci_address\" value=\"0\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pci_bar_0_prefetchable\" value=\"true\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pci_bar_1_auto_avalon_address\" value=\"false\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pci_bar_1_auto_sized\" value=\"false\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pci_bar_1_avalon_address\" value=\"0\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pci_bar_1_hardwired\" value=\"false\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pci_bar_1_pci_address\" value=\"0\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pci_bar_1_prefetchable\" value=\"true\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pci_bar_2_auto_avalon_address\" value=\"false\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pci_bar_2_auto_sized\" value=\"false\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pci_bar_2_avalon_address\" value=\"0\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pci_bar_2_hardwired\" value=\"false\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pci_bar_2_pci_address\" value=\"0\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pci_bar_2_prefetchable\" value=\"true\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pci_bar_3_auto_avalon_address\" value=\"false\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pci_bar_3_auto_sized\" value=\"false\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pci_bar_3_avalon_address\" value=\"0\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pci_bar_3_hardwired\" value=\"false\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pci_bar_3_pci_address\" value=\"0\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pci_bar_3_prefetchable\" value=\"false\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pci_bar_4_auto_avalon_address\" value=\"false\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pci_bar_4_auto_sized\" value=\"false\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pci_bar_4_avalon_address\" value=\"0\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pci_bar_4_hardwired\" value=\"false\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pci_bar_4_pci_address\" value=\"0\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pci_bar_4_prefetchable\" value=\"true\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pci_bar_5_auto_avalon_address\" value=\"false\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pci_bar_5_auto_sized\" value=\"false\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pci_bar_5_avalon_address\" value=\"0\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pci_bar_5_hardwired\" value=\"false\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pci_bar_5_pci_address\" value=\"0\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pci_bar_5_prefetchable\" value=\"true\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pci_bus_access_address_width\" value=\"18\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pci_global_reset\" value=\"false\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pci_host_bridge\" value=\"false\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pci_impl_cra_av_slave_port\" value=\"true\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pci_master\" value=\"true\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pci_master_bursts\" value=\"true\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pci_master_concurrent_reads\" value=\"false\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pci_master_data_width\" value=\"64\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pci_maximum_burst_size\" value=\"128\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pci_maximum_burst_size_a2p\" value=\"128\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pci_maximum_pending_read_transactions_a2p\" value=\"8\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pci_non_pref_av_master_port\" value=\"true\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pci_not_target_only_port\" value=\"true\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pci_pref_av_master_port\" value=\"true\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pci_reqn_gntn_pins\" value=\"true\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pci_single_clock\" value=\"false\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pci_target_bursts\" value=\"true\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pci_target_concurrent_reads\" value=\"false\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pci_user_specified_bars\" value=\"false\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pcie_L1_exit_latency_common_clock\" value=\"&gt;64 us\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pcie_L1_exit_latency_separate_clock\" value=\"&gt;64 us\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pcie_advanced_error_int_num\" value=\"0x00000000\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pcie_alt2gxb\" value=\"0\"  type=\"BOOLEAN\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pcie_altgx_keyParameters_used\" value=\"{p_pcie_enable_hip=1, p_pcie_number_of_lanes=x8, p_pcie_phy=Stratix IV GX, p_pcie_rate=Gen2 (5.0 Gbps), p_pcie_txrx_clock=100 MHz}\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pcie_app_signal_interface\" value=\"AvalonST128\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pcie_avalon_mm_lite\" value=\"0\"  type=\"INTEGER\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pcie_bar_size_bar_0\" value=\"16 KBytes - 14 bits\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pcie_bar_size_bar_1\" value=\"N/A\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pcie_bar_size_bar_2\" value=\"1 MByte - 20 bits\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pcie_bar_size_bar_3\" value=\"N/A\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pcie_bar_size_bar_4\" value=\"N/A\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pcie_bar_size_bar_5\" value=\"N/A\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pcie_bar_type_bar_0\" value=\"64-bit Prefetchable Memory\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pcie_bar_type_bar_1\" value=\"N/A\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pcie_bar_type_bar_2\" value=\"64-bit Prefetchable Memory\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pcie_bar_type_bar_3\" value=\"N/A\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pcie_bar_type_bar_4\" value=\"Disable this and all higher BARs\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pcie_bar_type_bar_5\" value=\"Disable this and all higher BARs\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pcie_bar_used_bar_0\" value=\"1\"  type=\"BOOLEAN\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pcie_bar_used_bar_1\" value=\"1\"  type=\"BOOLEAN\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pcie_bar_used_bar_2\" value=\"1\"  type=\"BOOLEAN\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pcie_bar_used_bar_3\" value=\"1\"  type=\"BOOLEAN\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pcie_bar_used_bar_4\" value=\"0\"  type=\"BOOLEAN\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pcie_bar_used_bar_5\" value=\"0\"  type=\"BOOLEAN\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pcie_channel_number\" value=\"0\"  type=\"INTEGER\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pcie_chk_io\" value=\"0\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pcie_class_code\" value=\"0xFF0000\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pcie_completion_data_credit_vc0\" value=\"448\"  type=\"INTEGER\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pcie_completion_data_credit_vc1\" value=\"0\"  type=\"INTEGER\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pcie_completion_data_credit_vc2\" value=\"0\"  type=\"INTEGER\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pcie_completion_data_credit_vc3\" value=\"0\"  type=\"INTEGER\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pcie_completion_data_used_space_vc0\" value=\"7168\"  type=\"INTEGER\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pcie_completion_data_used_space_vc1\" value=\"0\"  type=\"INTEGER\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pcie_completion_data_used_space_vc2\" value=\"0\"  type=\"INTEGER\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pcie_completion_data_used_space_vc3\" value=\"0\"  type=\"INTEGER\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pcie_completion_header_credit_vc0\" value=\"112\"  type=\"INTEGER\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pcie_completion_header_credit_vc1\" value=\"0\"  type=\"INTEGER\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pcie_completion_header_credit_vc2\" value=\"0\"  type=\"INTEGER\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pcie_completion_header_credit_vc3\" value=\"0\"  type=\"INTEGER\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pcie_completion_header_used_space_vc0\" value=\"1792\"  type=\"INTEGER\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pcie_completion_header_used_space_vc1\" value=\"0\"  type=\"INTEGER\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pcie_completion_header_used_space_vc2\" value=\"0\"  type=\"INTEGER\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pcie_completion_header_used_space_vc3\" value=\"0\"  type=\"INTEGER\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pcie_completion_timeout\" value=\"ABCD\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pcie_custom_phy_x8\" value=\"0\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pcie_custom_rx_buffer_xml\" value=\"0\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pcie_device_id\" value=\"0x1BE7\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pcie_disable_L0s\" value=\"false\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pcie_dll_active_report_support\" value=\"0\"  type=\"BOOLEAN\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pcie_eie_b4_nfts_count\" value=\"4\"  type=\"INTEGER\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pcie_enable_completion_timeout_disable\" value=\"1\"  type=\"BOOLEAN\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pcie_enable_function_msix_support\" value=\"1\"  type=\"BOOLEAN\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pcie_enable_hip\" value=\"1\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pcie_enable_hip_core_clk\" value=\"0\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pcie_enable_pcie_gen2_x8_es\" value=\"0\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pcie_enable_pcie_gen2_x8_s5gx\" value=\"0\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pcie_enable_root_port_endpoint_mode\" value=\"0\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pcie_enable_simple_dma\" value=\"0\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pcie_enable_slot_capability\" value=\"0\"  type=\"BOOLEAN\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pcie_enable_tl_bypass_mode\" value=\"0\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pcie_endpoint_L0s_acceptable_latency\" value=\"&lt;64 ns\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pcie_endpoint_L1_acceptable_latency\" value=\"&lt;1 us\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pcie_exp_rom_bar_size\" value=\"N/A\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pcie_gen2_nfts_diff_clock\" value=\"255\"  type=\"INTEGER\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pcie_gen2_nfts_same_clock\" value=\"255\"  type=\"INTEGER\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pcie_initiator_performance_preset\" value=\"Maximum\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pcie_internal_clock\" value=\"125 MHz\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pcie_io_base_and_limit_register\" value=\"IODisable\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pcie_lanerev\" value=\"0\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pcie_link_port_number\" value=\"0x01\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pcie_max_payload_size\" value=\"512 Bytes\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pcie_mem_base_and_limit_register\" value=\"MemDisable\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pcie_msix_pba_bir\" value=\"0\"  type=\"INTEGER\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pcie_msix_pba_offset\" value=\"62\"  type=\"INTEGER\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pcie_msix_table_bir\" value=\"0\"  type=\"INTEGER\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pcie_msix_table_offset\" value=\"64\"  type=\"INTEGER\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pcie_msix_table_size\" value=\"16\"  type=\"INTEGER\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pcie_nonposted_data_credit_vc0\" value=\"0\"  type=\"INTEGER\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pcie_nonposted_data_credit_vc1\" value=\"0\"  type=\"INTEGER\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pcie_nonposted_data_credit_vc2\" value=\"0\"  type=\"INTEGER\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pcie_nonposted_data_credit_vc3\" value=\"0\"  type=\"INTEGER\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pcie_nonposted_data_used_space_vc0\" value=\"0\"  type=\"INTEGER\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pcie_nonposted_data_used_space_vc1\" value=\"0\"  type=\"INTEGER\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pcie_nonposted_data_used_space_vc2\" value=\"0\"  type=\"INTEGER\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pcie_nonposted_data_used_space_vc3\" value=\"0\"  type=\"INTEGER\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pcie_nonposted_header_credit_vc0\" value=\"54\"  type=\"INTEGER\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pcie_nonposted_header_credit_vc1\" value=\"0\"  type=\"INTEGER\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pcie_nonposted_header_credit_vc2\" value=\"0\"  type=\"INTEGER\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pcie_nonposted_header_credit_vc3\" value=\"0\"  type=\"INTEGER\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pcie_nonposted_header_used_space_vc0\" value=\"864\"  type=\"INTEGER\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pcie_nonposted_header_used_space_vc1\" value=\"0\"  type=\"INTEGER\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pcie_nonposted_header_used_space_vc2\" value=\"0\"  type=\"INTEGER\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pcie_nonposted_header_used_space_vc3\" value=\"0\"  type=\"INTEGER\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pcie_number_of_lanes\" value=\"x8\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pcie_phy_interface\" value=\"Serial\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pcie_pme_pending\" value=\"0\"  type=\"BOOLEAN\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pcie_pme_reg_id\" value=\"0x0000\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pcie_posted_data_credit_vc0\" value=\"360\"  type=\"INTEGER\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pcie_posted_data_credit_vc1\" value=\"0\"  type=\"INTEGER\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pcie_posted_data_credit_vc2\" value=\"0\"  type=\"INTEGER\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pcie_posted_data_credit_vc3\" value=\"0\"  type=\"INTEGER\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pcie_posted_data_used_space_vc0\" value=\"5760\"  type=\"INTEGER\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pcie_posted_data_used_space_vc1\" value=\"0\"  type=\"INTEGER\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pcie_posted_data_used_space_vc2\" value=\"0\"  type=\"INTEGER\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pcie_posted_data_used_space_vc3\" value=\"0\"  type=\"INTEGER\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pcie_posted_header_credit_vc0\" value=\"50\"  type=\"INTEGER\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pcie_posted_header_credit_vc1\" value=\"0\"  type=\"INTEGER\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pcie_posted_header_credit_vc2\" value=\"0\"  type=\"INTEGER\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pcie_posted_header_credit_vc3\" value=\"0\"  type=\"INTEGER\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pcie_posted_header_used_space_vc0\" value=\"800\"  type=\"INTEGER\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pcie_posted_header_used_space_vc1\" value=\"0\"  type=\"INTEGER\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pcie_posted_header_used_space_vc2\" value=\"0\"  type=\"INTEGER\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pcie_posted_header_used_space_vc3\" value=\"0\"  type=\"INTEGER\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pcie_rate\" value=\"Gen2 (5.0 Gbps)\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pcie_retry_buffer_size\" value=\"16 KBytes\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pcie_revision_id\" value=\"0x01\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pcie_rx_buffer_preset\" value=\"Default\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pcie_rx_buffer_size_string_vc0\" value=\"16 KBytes\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pcie_rx_buffer_size_string_vc1\" value=\"0\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pcie_rx_buffer_size_string_vc2\" value=\"0\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pcie_rx_buffer_size_string_vc3\" value=\"0\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pcie_rx_buffer_size_vc0\" value=\"16384\"  type=\"INTEGER\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pcie_rx_buffer_size_vc1\" value=\"0\"  type=\"INTEGER\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pcie_rx_buffer_size_vc2\" value=\"0\"  type=\"INTEGER\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pcie_rx_buffer_size_vc3\" value=\"0\"  type=\"INTEGER\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pcie_slot_capabilities\" value=\"0x00000000\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pcie_special_phy_gl\" value=\"0\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pcie_special_phy_px\" value=\"1\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pcie_subsystem_device_id\" value=\"0x1BE7\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pcie_subsystem_vendor_id\" value=\"0xC100\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pcie_surprise_down_error_support\" value=\"0\"  type=\"BOOLEAN\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pcie_target_performance_preset\" value=\"Maximum\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pcie_test_out_width\" value=\"None\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pcie_threshold_for_L0s_entry\" value=\"8192 ns\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pcie_total_header_credit_vc0\" value=\"216\"  type=\"INTEGER\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pcie_total_header_credit_vc1\" value=\"0\"  type=\"INTEGER\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pcie_total_header_credit_vc2\" value=\"0\"  type=\"INTEGER\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pcie_total_header_credit_vc3\" value=\"0\"  type=\"INTEGER\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pcie_txrx_clock\" value=\"100 MHz\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pcie_underSOPCBuilder\" value=\"false\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pcie_use_crc_forwarding\" value=\"0\"  type=\"BOOLEAN\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pcie_use_parity\" value=\"false\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pcie_variation_name\" value=\"siv_gen2x8_core\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pcie_vendor_id\" value=\"0xC100\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pcie_version\" value=\"2.0\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_pcie_virutal_channels\" value=\"1\"  type=\"INTEGER\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"pref_nonp_independent\" value=\"false\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"translationTableSizeInfo\" value=\"The bridge reserves a contiguous Avalon address range to access\n// Retrieval info: PCIe devices. This Avalon address range is segmented into one or\n// Retrieval info: more equal-sized pages that are individually mapped to PCIe\n// Retrieval info: addresses. Select the number and size of the address pages.\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"uiAvalonHWAddress0\" value=\"0x00000000\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"uiAvalonHWAddress1\" value=\"0x00000000\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"uiAvalonHWAddress10\" value=\"0x00000000\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"uiAvalonHWAddress11\" value=\"0x00000000\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"uiAvalonHWAddress12\" value=\"0x00000000\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"uiAvalonHWAddress13\" value=\"0x00000000\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"uiAvalonHWAddress14\" value=\"0x00000000\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"uiAvalonHWAddress15\" value=\"0x00000000\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"uiAvalonHWAddress2\" value=\"0x00000000\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"uiAvalonHWAddress3\" value=\"0x00000000\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"uiAvalonHWAddress4\" value=\"0x00000000\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"uiAvalonHWAddress5\" value=\"0x00000000\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"uiAvalonHWAddress6\" value=\"0x00000000\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"uiAvalonHWAddress7\" value=\"0x00000000\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"uiAvalonHWAddress8\" value=\"0x00000000\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"uiAvalonHWAddress9\" value=\"0x00000000\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"uiAvalonHWPCIAddress0\" value=\"0x00000000\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"uiAvalonHWPCIAddress1\" value=\"0x00000000\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"uiAvalonHWPCIAddress10\" value=\"0x00000000\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"uiAvalonHWPCIAddress11\" value=\"0x00000000\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"uiAvalonHWPCIAddress12\" value=\"0x00000000\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"uiAvalonHWPCIAddress13\" value=\"0x00000000\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"uiAvalonHWPCIAddress14\" value=\"0x00000000\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"uiAvalonHWPCIAddress15\" value=\"0x00000000\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"uiAvalonHWPCIAddress2\" value=\"0x00000000\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"uiAvalonHWPCIAddress3\" value=\"0x00000000\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"uiAvalonHWPCIAddress4\" value=\"0x00000000\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"uiAvalonHWPCIAddress5\" value=\"0x00000000\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"uiAvalonHWPCIAddress6\" value=\"0x00000000\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"uiAvalonHWPCIAddress7\" value=\"0x00000000\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"uiAvalonHWPCIAddress8\" value=\"0x00000000\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"uiAvalonHWPCIAddress9\" value=\"0x00000000\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"uiAvalonTranslationTable\" value=\"false\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"uiBar0PCIAddress\" value=\"0x00000000\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"uiBar0Prefetchable\" value=\"true\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"uiBar1PCIAddress\" value=\"0x00000000\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"uiBar1Prefetchable\" value=\"true\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"uiBar2PCIAddress\" value=\"0x00000000\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"uiBar2Prefetchable\" value=\"true\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"uiBar3PCIAddress\" value=\"0x00000000\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"uiBar3Prefetchable\" value=\"false\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"uiBar4PCIAddress\" value=\"0x00000000\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"uiBar4Prefetchable\" value=\"true\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"uiBar5PCIAddress\" value=\"0x00000000\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"uiBar5Prefetchable\" value=\"true\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"uiCRAInfoPanel\" value=\"other\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"uiExpROMType\" value=\"Select to Enable\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"uiFixedTable\" value=\"true\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"uiPCIBar0Type\" value=\"64-bit Prefetchable Memory\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"uiPCIBar1Type\" value=\"N/A\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"uiPCIBar2Type\" value=\"64-bit Prefetchable Memory\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"uiPCIBar3Type\" value=\"N/A\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"uiPCIBar4Type\" value=\"Disable this and all higher BARs\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"uiPCIBar5Type\" value=\"Disable this and all higher BARs\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"uiPCIBarTable\" value=\"false\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"uiPCIBusArbiter\" value=\"external\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"uiPCIDeviceMode\" value=\"masterTarget\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"uiPCIMasterPerformance\" value=\"burstSinglePending\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"uiPCITargetPerformance\" value=\"burstSinglePending\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"uiPaneCount\" value=\"1\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"uiPaneSize\" value=\"20\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"ui_pcie_msix_pba_bir\" value=\"1:0\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"ui_pcie_msix_table_bir\" value=\"1:0\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"p_tx_cdc_full_value\" value=\"12\"  type=\"INTEGER\"  enable=\"1\" />\n// Retrieval info:     </NAMESPACE>\n// Retrieval info:     <NAMESPACE name = \"simgen_enable\">\n// Retrieval info:      <PRIVATE name = \"language\" value=\"VERILOG\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"enabled\" value=\"0\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:     </NAMESPACE>\n// Retrieval info:     <NAMESPACE name = \"greybox\">\n// Retrieval info:      <PRIVATE name = \"gb_enabled\" value=\"0\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:      <PRIVATE name = \"filename\" value=\"siv_gen2x8_syn.v\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:     </NAMESPACE>\n// Retrieval info:     <NAMESPACE name = \"testbench\">\n// Retrieval info:      <PRIVATE name = \"plugin_worker\" value=\"1\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:     </NAMESPACE>\n// Retrieval info:     <NAMESPACE name = \"simgen\">\n// Retrieval info:      <PRIVATE name = \"filename\" value=\"siv_gen2x8_core.v\"  type=\"STRING\"  enable=\"1\" />\n// Retrieval info:     </NAMESPACE>\n// Retrieval info:     <NAMESPACE name = \"serializer\"/>\n// Retrieval info:    </PRIVATES>\n// Retrieval info:    <FILES/>\n// Retrieval info:    <PORTS/>\n// Retrieval info:    <LIBRARIES/>\n// Retrieval info:   </STATIC_SECTION>\n// Retrieval info:  </NETLIST_SECTION>\n// Retrieval info: </MEGACORE>\n// =========================================================\n"
  },
  {
    "path": "verilog/awsf1.sv",
    "content": "\n`include \"ConnectalProjectConfig.bsv\"\n\nmodule awsf1(\n\t     `include \"cl_ports.vh\"\n\t     );\n\n//`include \"cl_common_defines.vh\"      // CL Defines for all examples\n`include \"cl_id_defines.vh\"          // Defines for ID0 and ID1 (PCI ID's)\n\n   assign cl_sh_id0 = `CL_SH_ID0;\n   assign cl_sh_id1 = `CL_SH_ID1;\n\n//Put module name of the CL design here.  This is used to instantiate in top.sv\n`define CL_NAME awsf1\n\n//Highly recommeneded.  For lib FIFO block, uses less async reset (take advantage of\n// FPGA flop init capability).  This will help with routing resources.\n`define FPGA_LESS_RST\n\n`define SH_SDA // Not sure what that does\n//uncomment below to make SH and CL async\n`define SH_CL_ASYNC\n\n   `include \"unused_flr_template.inc\"\n`ifndef AWSF1_DDR_A\n`include \"unused_ddr_a_b_d_template.inc\"\n`endif //  AWSF1_DDR_A\n`include \"unused_ddr_c_template.inc\"\n//`include \"unused_pcim_template.inc\"\n`ifndef AWSF1_DMA_PCIS\n`include \"unused_dma_pcis_template.inc\"\n`endif\n`include \"unused_cl_sda_template.inc\"\n`include \"unused_sh_bar1_template.inc\"\n//`include \"unused_apppf_irq_template.inc\"\n//`include \"unused_sh_ocl_template.inc\"\n\n\n`ifdef AWSF1_DDR_A\n   localparam DDR_A_PRESENT=1;\n   // DDR B and D are not used, disable them\n`ifdef AWSF1_DDR_B\n   localparam DDR_B_PRESENT=1;\n`else\n   localparam DDR_B_PRESENT=0;\n`endif\n   localparam DDR_D_PRESENT=0;\n\n//   localparam DDR_SCRB_MAX_ADDR = 64'h3FFFFFFFF; //16GB \n//   localparam DDR_SCRB_BURST_LEN_MINUS1 = 15;\n\n\n   //---------------------------- \n   // Internal signals\n   //---------------------------- \n   //axi_bus_t lcl_cl_sh_ddra();\n   //axi_bus_t lcl_cl_sh_ddrb();\n   //axi_bus_t lcl_cl_sh_ddrd();\n\n   //axi_bus_t sh_cl_dma_pcis_bus();\n   //axi_bus_t sh_cl_dma_pcis_q();\n   //\n   //axi_bus_t cl_sh_pcim_bus();\n   //axi_bus_t cl_sh_ddr_bus();\n\n   //axi_bus_t sda_cl_bus();\n   //axi_bus_t sh_ocl_bus();\n\n   //cfg_bus_t pcim_tst_cfg_bus();\n   //cfg_bus_t ddra_tst_cfg_bus();\n   //cfg_bus_t ddrb_tst_cfg_bus();\n   //cfg_bus_t ddrc_tst_cfg_bus();\n   //cfg_bus_t ddrd_tst_cfg_bus();\n   //cfg_bus_t int_tst_cfg_bus();\n\n   // scrb_bus_t ddra_scrb_bus();\n   // scrb_bus_t ddrb_scrb_bus();\n   // scrb_bus_t ddrc_scrb_bus();\n   // scrb_bus_t ddrd_scrb_bus();\n\n\n   logic clk;\n   (* dont_touch = \"true\" *) logic pipe_rst_n;\n   logic pre_sync_rst_n;\n   (* dont_touch = \"true\" *) logic sync_rst_n;\n   //logic sh_cl_flr_assert_q;\n\n   //logic [3:0] all_ddr_scrb_done;\n   logic [3:0] all_ddr_is_ready;\n   logic [2:0] lcl_sh_cl_ddr_is_ready;\n\n   //logic dbg_scrb_en;\n   //logic [2:0] dbg_scrb_mem_sel;\n\n   //---------------------------- \n   // End Internal signals\n   //----------------------------\n\n\n   assign clk = clk_main_a0;\n\n   //reset synchronizer\n   lib_pipe #(.WIDTH(1), .STAGES(4)) PIPE_RST_N (.clk(clk), .rst_n(1'b1), .in_bus(rst_main_n), .out_bus(pipe_rst_n));\n   \n   always_ff @(negedge pipe_rst_n or posedge clk)\n     if (!pipe_rst_n)\n       begin\n\t  pre_sync_rst_n <= 0;\n\t  sync_rst_n <= 0;\n       end\n     else\n       begin\n\t  pre_sync_rst_n <= 1;\n\t  sync_rst_n <= pre_sync_rst_n;\n       end\n\n\n\n   //----------------------------------------- \n   // DDR controller instantiation   \n   //-----------------------------------------\n   logic [7:0] sh_ddr_stat_addr_q[2:0];\n   logic [2:0] sh_ddr_stat_wr_q;\n   logic [2:0] sh_ddr_stat_rd_q; \n   logic [31:0] sh_ddr_stat_wdata_q[2:0];\n   logic [2:0] \tddr_sh_stat_ack_q;\n   logic [31:0] ddr_sh_stat_rdata_q[2:0];\n   logic [7:0] \tddr_sh_stat_int_q[2:0];\n\n   localparam NUM_CFG_STGS_CL_DDR_ATG = 8;\n   localparam NUM_CFG_STGS_SH_DDR_ATG = 4;\n\n   lib_pipe #(.WIDTH(1+1+8+32), .STAGES(NUM_CFG_STGS_CL_DDR_ATG)) PIPE_DDR_STAT0 (.clk(clk), .rst_n(sync_rst_n),\n\t\t\t\t\t\t\t\t\t\t  .in_bus({sh_ddr_stat_wr0, sh_ddr_stat_rd0, sh_ddr_stat_addr0, sh_ddr_stat_wdata0}),\n\t\t\t\t\t\t\t\t\t\t  .out_bus({sh_ddr_stat_wr_q[0], sh_ddr_stat_rd_q[0], sh_ddr_stat_addr_q[0], sh_ddr_stat_wdata_q[0]})\n\t\t\t\t\t\t\t\t\t\t  );\n\n\n   lib_pipe #(.WIDTH(1+8+32), .STAGES(NUM_CFG_STGS_CL_DDR_ATG)) PIPE_DDR_STAT_ACK0 (.clk(clk), .rst_n(sync_rst_n),\n\t\t\t\t\t\t\t\t\t\t    .in_bus({ddr_sh_stat_ack_q[0], ddr_sh_stat_int_q[0], ddr_sh_stat_rdata_q[0]}),\n\t\t\t\t\t\t\t\t\t\t    .out_bus({ddr_sh_stat_ack0, ddr_sh_stat_int0, ddr_sh_stat_rdata0})\n\t\t\t\t\t\t\t\t\t\t    );\n\n\n   // tie DRAM B to 0\n   //lib_pipe #(.WIDTH(1+1+8+32), .STAGES(NUM_CFG_STGS_CL_DDR_ATG)) PIPE_DDR_STAT1 (.clk(clk), .rst_n(sync_rst_n),\n   //                                     .in_bus({sh_ddr_stat_wr1, sh_ddr_stat_rd1, sh_ddr_stat_addr1, sh_ddr_stat_wdata1}),\n   //                                     .out_bus({sh_ddr_stat_wr_q[1], sh_ddr_stat_rd_q[1], sh_ddr_stat_addr_q[1], sh_ddr_stat_wdata_q[1]})\n   //                                     );\n   //lib_pipe #(.WIDTH(1+8+32), .STAGES(NUM_CFG_STGS_CL_DDR_ATG)) PIPE_DDR_STAT_ACK1 (.clk(clk), .rst_n(sync_rst_n),\n   //                                   .in_bus({ddr_sh_stat_ack_q[1], ddr_sh_stat_int_q[1], ddr_sh_stat_rdata_q[1]}),\n   //                                   .out_bus({ddr_sh_stat_ack1, ddr_sh_stat_int1, ddr_sh_stat_rdata1})\n   //                                   );\n   assign {sh_ddr_stat_wr_q[   1],\n           sh_ddr_stat_rd_q[   1],\n           sh_ddr_stat_addr_q[ 1],\n           sh_ddr_stat_wdata_q[1]} = '0;\n   assign ddr_sh_stat_ack1 = 1'b1; // Needed in order not to hang the interface\n   assign {ddr_sh_stat_int1,\n           ddr_sh_stat_rddata1} = '0;\n\n   // tie DRAM D to 0\n   //lib_pipe #(.WIDTH(1+1+8+32), .STAGES(NUM_CFG_STGS_CL_DDR_ATG)) PIPE_DDR_STAT2 (.clk(clk), .rst_n(sync_rst_n),\n   //                                     .in_bus({sh_ddr_stat_wr2, sh_ddr_stat_rd2, sh_ddr_stat_addr2, sh_ddr_stat_wdata2}),\n   //                                     .out_bus({sh_ddr_stat_wr_q[2], sh_ddr_stat_rd_q[2], sh_ddr_stat_addr_q[2], sh_ddr_stat_wdata_q[2]})\n   //                                     );\n   //lib_pipe #(.WIDTH(1+8+32), .STAGES(NUM_CFG_STGS_CL_DDR_ATG)) PIPE_DDR_STAT_ACK2 (.clk(clk), .rst_n(sync_rst_n),\n   //                                   .in_bus({ddr_sh_stat_ack_q[2], ddr_sh_stat_int_q[2], ddr_sh_stat_rdata_q[2]}),\n   //                                   .out_bus({ddr_sh_stat_ack2, ddr_sh_stat_int2, ddr_sh_stat_rdata2})\n   //                                   ); \n   assign {sh_ddr_stat_wr_q[   2],\n           sh_ddr_stat_rd_q[   2],\n           sh_ddr_stat_addr_q[ 2],\n           sh_ddr_stat_wdata_q[2]} = '0;\n   assign ddr_sh_stat_ack2 = 1'b1; // Needed in order not to hang the interface\n   assign {ddr_sh_stat_int2,\n           ddr_sh_stat_rddata2} = '0;\n\n   //convert to 2D \n   logic [15:0] cl_sh_ddr_awid_2d[2:0];\n   logic [63:0] cl_sh_ddr_awaddr_2d[2:0];\n   logic [7:0] \tcl_sh_ddr_awlen_2d[2:0];\n   logic [2:0] \tcl_sh_ddr_awsize_2d[2:0];\n   logic [1:0] \tcl_sh_ddr_awburst_2d[2:0];\n   logic \tcl_sh_ddr_awvalid_2d [2:0];\n   logic [2:0] \tsh_cl_ddr_awready_2d;\n\n   logic [15:0] cl_sh_ddr_wid_2d[2:0];\n   logic [511:0] cl_sh_ddr_wdata_2d[2:0];\n   logic [63:0]  cl_sh_ddr_wstrb_2d[2:0];\n   logic [2:0] \t cl_sh_ddr_wlast_2d;\n   logic [2:0] \t cl_sh_ddr_wvalid_2d;\n   logic [2:0] \t sh_cl_ddr_wready_2d;\n\n   logic [15:0]  sh_cl_ddr_bid_2d[2:0];\n   logic [1:0] \t sh_cl_ddr_bresp_2d[2:0];\n   logic [2:0] \t sh_cl_ddr_bvalid_2d;\n   logic [2:0] \t cl_sh_ddr_bready_2d;\n\n   logic [15:0]  cl_sh_ddr_arid_2d[2:0];\n   logic [63:0]  cl_sh_ddr_araddr_2d[2:0];\n   logic [7:0] \t cl_sh_ddr_arlen_2d[2:0];\n   logic [2:0] \t cl_sh_ddr_arsize_2d[2:0];\n   logic [1:0] \t cl_sh_ddr_arburst_2d[2:0];\n   logic [2:0] \t cl_sh_ddr_arvalid_2d;\n   logic [2:0] \t sh_cl_ddr_arready_2d;\n\n   logic [15:0]  sh_cl_ddr_rid_2d[2:0];\n   logic [511:0] sh_cl_ddr_rdata_2d[2:0];\n   logic [1:0] \t sh_cl_ddr_rresp_2d[2:0];\n   logic [2:0] \t sh_cl_ddr_rlast_2d;\n   logic [2:0] \t sh_cl_ddr_rvalid_2d;\n   logic [2:0] \t cl_sh_ddr_rready_2d;\n\n   // tie DRAM B to 0\n   assign {cl_sh_ddr_awid_2d[   1],\n           cl_sh_ddr_awaddr_2d[ 1],\n           cl_sh_ddr_awlen_2d[  1],\n           cl_sh_ddr_awsize_2d[ 1],\n           cl_sh_ddr_awvalid_2d[1],\n           cl_sh_ddr_wid_2d[    1],\n           cl_sh_ddr_wdata_2d[  1],\n           cl_sh_ddr_wstrb_2d[  1],\n           cl_sh_ddr_wlast_2d[  1],\n           cl_sh_ddr_wvalid_2d[ 1],\n           cl_sh_ddr_bready_2d[ 1],\n           cl_sh_ddr_arid_2d[   1],\n           cl_sh_ddr_araddr_2d[ 1],\n           cl_sh_ddr_arlen_2d[  1],\n           cl_sh_ddr_arsize_2d[ 1],\n           cl_sh_ddr_arvalid_2d[1],\n           cl_sh_ddr_rready_2d[ 1]} = '0;\n\n   // tie DRAM D to 0\n   assign {cl_sh_ddr_awid_2d[   2],\n           cl_sh_ddr_awaddr_2d[ 2],\n           cl_sh_ddr_awlen_2d[  2],\n           cl_sh_ddr_awsize_2d[ 2],\n           cl_sh_ddr_awvalid_2d[2],\n           cl_sh_ddr_wid_2d[    2],\n           cl_sh_ddr_wdata_2d[  2],\n           cl_sh_ddr_wstrb_2d[  2],\n           cl_sh_ddr_wlast_2d[  2],\n           cl_sh_ddr_wvalid_2d[ 2],\n           cl_sh_ddr_bready_2d[ 2],\n           cl_sh_ddr_arid_2d[   2],\n           cl_sh_ddr_araddr_2d[ 2],\n           cl_sh_ddr_arlen_2d[  2],\n           cl_sh_ddr_arsize_2d[ 2],\n           cl_sh_ddr_arvalid_2d[2],\n           cl_sh_ddr_rready_2d[ 2]} = '0;\n\n   assign cl_sh_pcim_araddr[63:40] = 24'd0;\n   assign cl_sh_pcim_awaddr[63:40] = 24'd0;\n\n   (* dont_touch = \"true\" *) logic sh_ddr_sync_rst_n;\n   lib_pipe #(.WIDTH(1), .STAGES(4)) SH_DDR_SLC_RST_N (.clk(clk), .rst_n(1'b1), .in_bus(sync_rst_n), .out_bus(sh_ddr_sync_rst_n));\n   sh_ddr #(\n            .DDR_A_PRESENT(DDR_A_PRESENT),\n            .DDR_B_PRESENT(DDR_B_PRESENT),\n            .DDR_D_PRESENT(DDR_D_PRESENT)\n\t    ) SH_DDR\n     (\n      .clk(clk),\n      .rst_n(sh_ddr_sync_rst_n),\n\n      .stat_clk(clk),\n      .stat_rst_n(sh_ddr_sync_rst_n),\n\n\n      .CLK_300M_DIMM0_DP(CLK_300M_DIMM0_DP),\n      .CLK_300M_DIMM0_DN(CLK_300M_DIMM0_DN),\n      .M_A_ACT_N(M_A_ACT_N),\n      .M_A_MA(M_A_MA),\n      .M_A_BA(M_A_BA),\n      .M_A_BG(M_A_BG),\n      .M_A_CKE(M_A_CKE),\n      .M_A_ODT(M_A_ODT),\n      .M_A_CS_N(M_A_CS_N),\n      .M_A_CLK_DN(M_A_CLK_DN),\n      .M_A_CLK_DP(M_A_CLK_DP),\n      .M_A_PAR(M_A_PAR),\n      .M_A_DQ(M_A_DQ),\n      .M_A_ECC(M_A_ECC),\n      .M_A_DQS_DP(M_A_DQS_DP),\n      .M_A_DQS_DN(M_A_DQS_DN),\n      .cl_RST_DIMM_A_N(cl_RST_DIMM_A_N),\n      \n      \n      .CLK_300M_DIMM1_DP(CLK_300M_DIMM1_DP),\n      .CLK_300M_DIMM1_DN(CLK_300M_DIMM1_DN),\n      .M_B_ACT_N(M_B_ACT_N),\n      .M_B_MA(M_B_MA),\n      .M_B_BA(M_B_BA),\n      .M_B_BG(M_B_BG),\n      .M_B_CKE(M_B_CKE),\n      .M_B_ODT(M_B_ODT),\n      .M_B_CS_N(M_B_CS_N),\n      .M_B_CLK_DN(M_B_CLK_DN),\n      .M_B_CLK_DP(M_B_CLK_DP),\n      .M_B_PAR(M_B_PAR),\n      .M_B_DQ(M_B_DQ),\n      .M_B_ECC(M_B_ECC),\n      .M_B_DQS_DP(M_B_DQS_DP),\n      .M_B_DQS_DN(M_B_DQS_DN),\n      .cl_RST_DIMM_B_N(cl_RST_DIMM_B_N),\n\n      .CLK_300M_DIMM3_DP(CLK_300M_DIMM3_DP),\n      .CLK_300M_DIMM3_DN(CLK_300M_DIMM3_DN),\n      .M_D_ACT_N(M_D_ACT_N),\n      .M_D_MA(M_D_MA),\n      .M_D_BA(M_D_BA),\n      .M_D_BG(M_D_BG),\n      .M_D_CKE(M_D_CKE),\n      .M_D_ODT(M_D_ODT),\n      .M_D_CS_N(M_D_CS_N),\n      .M_D_CLK_DN(M_D_CLK_DN),\n      .M_D_CLK_DP(M_D_CLK_DP),\n      .M_D_PAR(M_D_PAR),\n      .M_D_DQ(M_D_DQ),\n      .M_D_ECC(M_D_ECC),\n      .M_D_DQS_DP(M_D_DQS_DP),\n      .M_D_DQS_DN(M_D_DQS_DN),\n      .cl_RST_DIMM_D_N(cl_RST_DIMM_D_N),\n\n      //------------------------------------------------------\n      // DDR-4 Interface from CL (AXI-4)\n      //------------------------------------------------------\n      .cl_sh_ddr_awid(cl_sh_ddr_awid_2d),\n      .cl_sh_ddr_awaddr(cl_sh_ddr_awaddr_2d),\n      .cl_sh_ddr_awlen(cl_sh_ddr_awlen_2d),\n      .cl_sh_ddr_awsize(cl_sh_ddr_awsize_2d),\n      .cl_sh_ddr_awburst(cl_sh_ddr_awburst_2d),\n      .cl_sh_ddr_awvalid(cl_sh_ddr_awvalid_2d),\n      .sh_cl_ddr_awready(sh_cl_ddr_awready_2d),\n\n      .cl_sh_ddr_wid(cl_sh_ddr_wid_2d),\n      .cl_sh_ddr_wdata(cl_sh_ddr_wdata_2d),\n      .cl_sh_ddr_wstrb(cl_sh_ddr_wstrb_2d),\n      .cl_sh_ddr_wlast(cl_sh_ddr_wlast_2d),\n      .cl_sh_ddr_wvalid(cl_sh_ddr_wvalid_2d),\n      .sh_cl_ddr_wready(sh_cl_ddr_wready_2d),\n\n      .sh_cl_ddr_bid(sh_cl_ddr_bid_2d),\n      .sh_cl_ddr_bresp(sh_cl_ddr_bresp_2d),\n      .sh_cl_ddr_bvalid(sh_cl_ddr_bvalid_2d),\n      .cl_sh_ddr_bready(cl_sh_ddr_bready_2d),\n\n      .cl_sh_ddr_arid(cl_sh_ddr_arid_2d),\n      .cl_sh_ddr_araddr(cl_sh_ddr_araddr_2d),\n      .cl_sh_ddr_arlen(cl_sh_ddr_arlen_2d),\n      .cl_sh_ddr_arsize(cl_sh_ddr_arsize_2d),\n      .cl_sh_ddr_arburst(cl_sh_ddr_arburst_2d),\n      .cl_sh_ddr_arvalid(cl_sh_ddr_arvalid_2d),\n      .sh_cl_ddr_arready(sh_cl_ddr_arready_2d),\n\n      .sh_cl_ddr_rid(sh_cl_ddr_rid_2d),\n      .sh_cl_ddr_rdata(sh_cl_ddr_rdata_2d),\n      .sh_cl_ddr_rresp(sh_cl_ddr_rresp_2d),\n      .sh_cl_ddr_rlast(sh_cl_ddr_rlast_2d),\n      .sh_cl_ddr_rvalid(sh_cl_ddr_rvalid_2d),\n      .cl_sh_ddr_rready(cl_sh_ddr_rready_2d),\n\n      .sh_cl_ddr_is_ready(lcl_sh_cl_ddr_is_ready),\n\n      .sh_ddr_stat_addr0  (sh_ddr_stat_addr_q[0]) ,\n      .sh_ddr_stat_wr0    (sh_ddr_stat_wr_q[0]     ) , \n      .sh_ddr_stat_rd0    (sh_ddr_stat_rd_q[0]     ) , \n      .sh_ddr_stat_wdata0 (sh_ddr_stat_wdata_q[0]  ) , \n      .ddr_sh_stat_ack0   (ddr_sh_stat_ack_q[0]    ) ,\n      .ddr_sh_stat_rdata0 (ddr_sh_stat_rdata_q[0]  ),\n      .ddr_sh_stat_int0   (ddr_sh_stat_int_q[0]    ),\n\n      .sh_ddr_stat_addr1  (sh_ddr_stat_addr_q[1]) ,\n      .sh_ddr_stat_wr1    (sh_ddr_stat_wr_q[1]     ) , \n      .sh_ddr_stat_rd1    (sh_ddr_stat_rd_q[1]     ) , \n      .sh_ddr_stat_wdata1 (sh_ddr_stat_wdata_q[1]  ) , \n      .ddr_sh_stat_ack1   (ddr_sh_stat_ack_q[1]    ) ,\n      .ddr_sh_stat_rdata1 (ddr_sh_stat_rdata_q[1]  ),\n      .ddr_sh_stat_int1   (ddr_sh_stat_int_q[1]    ),\n\n      .sh_ddr_stat_addr2  (sh_ddr_stat_addr_q[2]) ,\n      .sh_ddr_stat_wr2    (sh_ddr_stat_wr_q[2]     ) , \n      .sh_ddr_stat_rd2    (sh_ddr_stat_rd_q[2]     ) , \n      .sh_ddr_stat_wdata2 (sh_ddr_stat_wdata_q[2]  ) , \n      .ddr_sh_stat_ack2   (ddr_sh_stat_ack_q[2]    ) ,\n      .ddr_sh_stat_rdata2 (ddr_sh_stat_rdata_q[2]  ),\n      .ddr_sh_stat_int2   (ddr_sh_stat_int_q[2]    ) \n      );\n\n   //----------------------------------------- \n   // DDR controller instantiation   \n   //-----------------------------------------\n`endif //  AWSF1_DDR_A\n\n\n`ifdef AWSF1_CL_DEBUG_BRIDGE\n   ila_connectal_1 cl_ila_slave (\n                   .clk    (clk_main_a0),\n                   .probe0 (sh_ocl_awvalid),\n                   .probe1 (sh_ocl_awaddr),\n                   .probe2 (ocl_sh_awready),\n                   .probe3 (sh_ocl_arvalid),\n                   .probe4 (sh_ocl_araddr),\n                   .probe5 (ocl_sh_arready),\n\n                   .probe6 (sh_ocl_wvalid),\n                   .probe7 (sh_ocl_wdata),\n                   .probe8 (ocl_sh_wready),\n                   .probe9 (ocl_sh_rvalid),\n                   .probe10 (ocl_sh_rdata),\n                   .probe11 (sh_ocl_rready),\n                   .probe12 (cl_sh_apppf_irq_req),\n                   .probe13 (sh_cl_apppf_irq_ack)\n                   );\n`ifndef AWSF1_DMA_PCIS\n\n   ila_connectal_2 cl_ila_master  (\n                   .clk    (clk_main_a0),\n                   .probe0 (cl_sh_pcim_awvalid),\n                   .probe1 (cl_sh_pcim_awaddr),\n                   .probe2 (sh_cl_pcim_awready),\n                   .probe3 (cl_sh_pcim_arvalid),\n                   .probe4 (cl_sh_pcim_araddr),\n                   .probe5 (sh_cl_pcim_arready),\n\n                   .probe6 (cl_sh_pcim_wvalid),\n                   .probe7 (cl_sh_pcim_wdata),\n                   .probe8 (sh_cl_pcim_wready),\n                   .probe9 (sh_cl_pcim_rvalid),\n                   .probe10 (sh_cl_pcim_rdata),\n                   .probe11 (cl_sh_pcim_rready),\n                   .probe12(cl_sh_pcim_wstrb),\n                   .probe13 (cl_sh_pcim_aruser),\n                   .probe14 (cl_sh_pcim_awuser),\n                   .probe15 (cl_sh_pcim_arlen),\n                   .probe16 (cl_sh_pcim_awlen),\n                   .probe17 (cl_sh_pcim_arid),\n                   .probe18 (cl_sh_pcim_awid),\n                   .probe19 (cl_sh_pcim_arsize),\n                   .probe20 (cl_sh_pcim_awsize),\n                   .probe21 (sh_cl_pcim_bid),\n                   .probe22 (sh_cl_pcim_bresp),\n                   .probe23 (cl_sh_pcim_bready),\n                   .probe24 (sh_cl_pcim_bvalid)\n                   );\n`else\n   wire [159:0] pc_status;\n   wire \tpc_asserted;\n\n      ila_connectal_3 cl_ila_pcis  (\n                   .clk    (clk_main_a0),\n                   .probe0 (sh_cl_dma_pcis_awvalid),\n                   .probe1 (sh_cl_dma_pcis_awaddr),\n                   .probe2 (cl_sh_dma_pcis_awready),\n                   .probe3 (sh_cl_dma_pcis_arvalid),\n                   .probe4 (sh_cl_dma_pcis_araddr),\n                   .probe5 (cl_sh_dma_pcis_arready),\n\n                   .probe6 (sh_cl_dma_pcis_wvalid),\n                   .probe7 (sh_cl_dma_pcis_wdata),\n                   .probe8 (cl_sh_dma_pcis_wready),\n                   .probe9 (cl_sh_dma_pcis_rvalid),\n                   .probe10 (cl_sh_dma_pcis_rdata),\n                   .probe11 (sh_cl_dma_pcis_rready),\n                   .probe12(sh_cl_dma_pcis_wstrb),\n                   .probe13 (sh_cl_dma_pcis_aruser),\n                   .probe14 ({sh_cl_dma_pcis_wlast, cl_sh_dma_pcis_rid, cl_sh_dma_pcis_rresp, cl_sh_dma_pcis_rlast, pc_asserted}),\n                   .probe15 (sh_cl_dma_pcis_arlen),\n                   .probe16 (sh_cl_dma_pcis_awlen),\n                   .probe17 (sh_cl_dma_pcis_arid),\n                   .probe18 (sh_cl_dma_pcis_awid),\n                   .probe19 (sh_cl_dma_pcis_arsize),\n                   .probe20 (sh_cl_dma_pcis_awsize),\n                   .probe21 (cl_sh_dma_pcis_bid),\n                   .probe22 (cl_sh_dma_pcis_bresp),\n                   .probe23 (sh_cl_dma_pcis_bready),\n                   .probe24 (cl_sh_dma_pcis_bvalid),\n                   .probe25 (pc_status)\n                   );\n`endif\n`ifdef AWSF1_DDR_A\n   ila_connectal_2 cl_ila_mem  (\n                   .clk    (clk_main_a0),\n                   .probe0 (cl_sh_ddr_awvalid_2d[0]),\n                   .probe1 (cl_sh_ddr_awaddr_2d[0]), // 64\n                   .probe2 (sh_cl_ddr_awready_2d[0]),\n                   .probe3 (cl_sh_ddr_arvalid_2d[0]),\n                   .probe4 (cl_sh_ddr_araddr_2d[0]), // 64\n                   .probe5 (sh_cl_ddr_arready_2d[0]),\n\n                   .probe6 (cl_sh_ddr_wvalid_2d[0]),\n                   .probe7 (cl_sh_ddr_wdata_2d[0]), // 512\n                   .probe8 (sh_cl_ddr_wready_2d[0]),\n                   .probe9 (sh_cl_ddr_rvalid_2d[0]),\n                   .probe10 (sh_cl_ddr_rdata_2d[0]), // 512\n                   .probe11 (cl_sh_ddr_rready_2d[0]),\n                   .probe12 (cl_sh_ddr_wstrb_2d[0]), // 64\n                   .probe13 (cl_sh_pcim_aruser), // 19\n                   .probe14 (cl_sh_pcim_awuser), // 19\n                   .probe15 (cl_sh_ddr_arlen_2d[0]),  // 8\n                   .probe16 (cl_sh_ddr_awlen_2d[0]), // 8\n                   .probe17 (cl_sh_ddr_arsize_2d[0]), // 3\n                   .probe18 (cl_sh_ddr_awsize_2d[0]), // 3\n                   .probe19 (cl_sh_ddr_awid_2d[0]), // 16\n                   .probe20 (cl_sh_ddr_arid_2d[0]), // 16\n                   .probe21 (sh_cl_ddr_bid_2d[0]), // 16\n                   .probe22 (sh_cl_ddr_bresp_2d[0]), // 2\n                   .probe23 (cl_sh_ddr_bready_2d[0]),\n                   .probe24 (sh_cl_ddr_bvalid_2d[0])\n                   );\n`endif\n`ifdef AWSF1_DDR_B\n   ila_connectal_2 cl_ila_mem  (\n                   .clk    (clk_main_a0),\n                   .probe0 (cl_sh_ddr_awvalid_2d[1]),\n                   .probe1 (cl_sh_ddr_awaddr_2d[1]), // 64\n                   .probe2 (sh_cl_ddr_awready_2d[1]),\n                   .probe3 (cl_sh_ddr_arvalid_2d[1]),\n                   .probe4 (cl_sh_ddr_araddr_2d[1]), // 64\n                   .probe5 (sh_cl_ddr_arready_2d[1]),\n\n                   .probe6 (cl_sh_ddr_wvalid_2d[1]),\n                   .probe7 (cl_sh_ddr_wdata_2d[1]), // 512\n                   .probe8 (sh_cl_ddr_wready_2d[1]),\n                   .probe9 (sh_cl_ddr_rvalid_2d[1]),\n                   .probe10 (sh_cl_ddr_rdata_2d[1]), // 512\n                   .probe11 (cl_sh_ddr_rready_2d[1]),\n                   .probe12 (cl_sh_ddr_wstrb_2d[1]), // 64\n                   .probe13 (0), // 19\n                   .probe14 (0), // 19\n                   .probe15 (cl_sh_ddr_arlen_2d[1]),  // 8\n                   .probe16 (cl_sh_ddr_awlen_2d[1]), // 8\n                   .probe17 (cl_sh_ddr_arsize_2d[1]), // 3\n                   .probe18 (cl_sh_ddr_awsize_2d[1]), // 3\n                   .probe19 (cl_sh_ddr_awid_2d[1]), // 16\n                   .probe20 (cl_sh_ddr_arid_2d[1]), // 16\n                   .probe21 (sh_cl_ddr_bid_2d[1]), // 16\n                   .probe22 (sh_cl_ddr_bresp_2d[1]), // 2\n                   .probe23 (cl_sh_ddr_bready_2d[1]),\n                   .probe24 (sh_cl_ddr_bvalid_2d[1])\n                   );\n`endif\n\n// Debug Bridge \n cl_debug_bridge CL_DEBUG_BRIDGE (\n      .clk(clk_main_a0),\n      .S_BSCAN_drck(drck),\n      .S_BSCAN_shift(shift),\n      .S_BSCAN_tdi(tdi),\n      .S_BSCAN_update(update),\n      .S_BSCAN_sel(sel),\n      .S_BSCAN_tdo(tdo),\n      .S_BSCAN_tms(tms),\n      .S_BSCAN_tck(tck),\n      .S_BSCAN_runtest(runtest),\n      .S_BSCAN_reset(reset),\n      .S_BSCAN_capture(capture),\n      .S_BSCAN_bscanid_en(bscanid_en)\n   );\n`endif // AWSF1_CL_DEBUG_BRIDGE\n\n   assign cl_sh_pcim_awuser = 0;\n   assign cl_sh_pcim_aruser = 0;\n\n   mkAwsF1Top awsF1Top(\n\t      .clk_main_a0(clk_main_a0),\t//Main clock.  This is the clock for all of the interfaces to the SH\n\t      .clk_extra_a1(clk_extra_a1),\t//Extra clock A1 (phase aligned to \"A\" clock group)\n\t      .clk_extra_a2(clk_extra_a2),\t//Extra clock A2 (phase aligned to \"A\" clock group)\n\t      .clk_extra_a3(clk_extra_a3),\t//Extra clock A3 (phase aligned to \"A\" clock group)\n   \n\t      .clk_extra_b0(clk_extra_b0),\t//Extra clock B0 (phase aligned to \"B\" clock group)\n\t      .clk_extra_b1(clk_extra_b1),\t//Extra clock B1 (phase aligned to \"B\" clock group)\n   \n\t      .clk_extra_c0(clk_extra_c0),\t//Extra clock C0 (phase aligned to \"B\" clock group)\n\t      .clk_extra_c1(clk_extra_c1),\t//Extra clock C1 (phase aligned to \"B\" clock group)\n\t      .kernel_rst_n(kernel_rst_n),\t//Kernel reset (for SDA platform)\n     \n\t      .rst_main_n(rst_main_n),\t//Reset sync to main clock.\n\n\t      .sh_cl_flr_assert(sh_cl_flr_assert), //Function level reset assertion.  Level signal that indicates PCIe function level reset is asserted\n\t      // remove import  \"unused_flr_template.inc\" if the flr_done signal is needed\n\t      //.cl_sh_flr_done(cl_sh_flr_done),\t//Function level reset done indication.  Must be asserted by CL when done processing functional\n\t      .cl_sh_status0(cl_sh_status0),\t//Functionality TBD\n\t      .cl_sh_status1(cl_sh_status1),\t//Functionality TBD\n\t      //.cl_sh_id0(cl_sh_id0),\t\n\t      //.cl_sh_id1(cl_sh_id1),\t\n\n\t      .sh_cl_ctl0(sh_cl_ctl0),\t//Functionality TBD\n\t      .sh_cl_ctl1(sh_cl_ctl1),\t//Functionality TBD\n\n\t      .sh_cl_status_vdip(sh_cl_status_vdip),\t//Virtual DIP switches.  Controlled through FPGA management PF and tools.\n\t      .cl_sh_status_vled(cl_sh_status_vled),\t//Virtual LEDs, monitored through FPGA management PF and tools\n\n\t      .sh_cl_pwr_state(sh_cl_pwr_state),\t//Power state, 2'b00: Normal, 2'b11: Critical\n\n\t      .interrupt_apppf_irq_req(cl_sh_apppf_irq_req),\n\t      .interrupt_apppf_irq_ack_ack(sh_cl_apppf_irq_ack),\n\n   //------------------------------------------------------------------------------------------\n   // AXI-L maps to any inbound PCIe access through ManagementPF BAR4 for developer's use\n   // If the CL is created through  Xilinx’s SDAccel, then this configuration bus\n   // would be connected automatically to SDAccel generic logic (SmartConnect, APM etc)\n   //------------------------------------------------------------------------------------------\n\n\t      .ocl_awvalid_v(sh_ocl_awvalid),\n\t      .ocl_awaddr_v(sh_ocl_awaddr),\n\t      .ocl_awready(ocl_sh_awready),\n\n\t      //Write data\n\t      .ocl_wvalid_v(sh_ocl_wvalid),\n\t      .ocl_wdata_v(sh_ocl_wdata),\n\t      //.(sh_ocl_wstrb),\n\t      .ocl_wready(ocl_sh_wready),\n\n\t      //Write response\n\t      .ocl_bvalid(ocl_sh_bvalid),\n\t      .ocl_bresp(ocl_sh_bresp),\n\t      .ocl_bready_v(sh_ocl_bready),\n\n   //Read address\n\t      .ocl_arvalid_v(sh_ocl_arvalid),\n\t      .ocl_araddr_v(sh_ocl_araddr),\n\t      .ocl_arready(ocl_sh_arready),\n\n   //Read data/response\n\t      .ocl_rvalid(ocl_sh_rvalid),\n\t      .ocl_rdata(ocl_sh_rdata),\n\t      .ocl_rresp(ocl_sh_rresp),\n\n\t      .ocl_rready_v(sh_ocl_rready),\n\n// DDR 3 through connectal AXI\n\n`ifdef AWSF1_DDR_A\n              .pins_araddr(cl_sh_ddr_araddr_2d[0]),\n\t      .pins_arid(cl_sh_ddr_arid_2d[0]),\n\t      .pins_arlen(cl_sh_ddr_arlen_2d[0]),\n\t      .pins_arready(sh_cl_ddr_arready_2d[0]),\n\t      .pins_arsize(cl_sh_ddr_arsize_2d[0]),\n\t      .pins_arburst(cl_sh_ddr_arburst_2d[0]),\n\t      .pins_arvalid(cl_sh_ddr_arvalid_2d[0]),\n\n\t      .pins_awaddr(cl_sh_ddr_awaddr_2d[0]),\n\t      .pins_awid(cl_sh_ddr_awid_2d[0]),\n\t      .pins_awlen(cl_sh_ddr_awlen_2d[0]),\n\t      .pins_awready(sh_cl_ddr_awready_2d[0]),\n\t      .pins_awsize(cl_sh_ddr_awsize_2d[0]),\n\t      .pins_awburst(cl_sh_ddr_awburst_2d[0]),\n\t      .pins_awvalid(cl_sh_ddr_awvalid_2d[0]),\n\t      //.pins_awlock(),\n\n\t      .pins_bid(sh_cl_ddr_bid_2d[0]),\n\t      .pins_bready(cl_sh_ddr_bready_2d[0]),\n\t      .pins_bresp(sh_cl_ddr_bresp_2d[0]),\n\t      .pins_bvalid(sh_cl_ddr_bvalid_2d[0]),\n\n\t      .pins_rdata(sh_cl_ddr_rdata_2d[0]),\n\t      .pins_rid(sh_cl_ddr_rid_2d[0]),\n\t      .pins_rlast(sh_cl_ddr_rlast_2d[0]),\n\t      .pins_rready(cl_sh_ddr_rready_2d[0]),\n\t      .pins_rresp(sh_cl_ddr_rresp_2d[0]),\n\t      .pins_rvalid(sh_cl_ddr_rvalid_2d[0]),\n\n\t      .pins_wdata(cl_sh_ddr_wdata_2d[0]),\n\t      //.pins_wid(cl_sh_ddr_wid_2d[0]),\n\t      .pins_wlast(cl_sh_ddr_wlast_2d[0]),\n\t      .pins_wready(sh_cl_ddr_wready_2d[0]),\n\t      .pins_wstrb(cl_sh_ddr_wstrb_2d[0]),\n\t      .pins_wvalid(cl_sh_ddr_wvalid_2d[0]),\n\n`endif // AWSF1_DDR_A\n\n`ifdef AWSF1_DDR_B\n              .pins_ddr_b_araddr(cl_sh_ddr_araddr_2d[1]),\n\t      .pins_ddr_b_arid(cl_sh_ddr_arid_2d[1]),\n\t      .pins_ddr_b_arlen(cl_sh_ddr_arlen_2d[1]),\n\t      .pins_ddr_b_arready(sh_cl_ddr_arready_2d[1]),\n\t      .pins_ddr_b_arsize(cl_sh_ddr_arsize_2d[1]),\n\t      .pins_ddr_b_arburst(cl_sh_ddr_arburst_2d[1]),\n\t      .pins_ddr_b_arvalid(cl_sh_ddr_arvalid_2d[1]),\n\n\t      .pins_ddr_b_awaddr(cl_sh_ddr_awaddr_2d[1]),\n\t      .pins_ddr_b_awid(cl_sh_ddr_awid_2d[1]),\n\t      .pins_ddr_b_awlen(cl_sh_ddr_awlen_2d[1]),\n\t      .pins_ddr_b_awready(sh_cl_ddr_awready_2d[1]),\n\t      .pins_ddr_b_awsize(cl_sh_ddr_awsize_2d[1]),\n\t      .pins_ddr_b_awburst(cl_sh_ddr_awburst_2d[1]),\n\t      .pins_ddr_b_awvalid(cl_sh_ddr_awvalid_2d[1]),\n\t      //.pins_ddr_b_awlock(),\n\n\t      .pins_ddr_b_bid(sh_cl_ddr_bid_2d[1]),\n\t      .pins_ddr_b_bready(cl_sh_ddr_bready_2d[1]),\n\t      .pins_ddr_b_bresp(sh_cl_ddr_bresp_2d[1]),\n\t      .pins_ddr_b_bvalid(sh_cl_ddr_bvalid_2d[1]),\n\n\t      .pins_ddr_b_rdata(sh_cl_ddr_rdata_2d[1]),\n\t      .pins_ddr_b_rid(sh_cl_ddr_rid_2d[1]),\n\t      .pins_ddr_b_rlast(sh_cl_ddr_rlast_2d[1]),\n\t      .pins_ddr_b_rready(cl_sh_ddr_rready_2d[1]),\n\t      .pins_ddr_b_rresp(sh_cl_ddr_rresp_2d[1]),\n\t      .pins_ddr_b_rvalid(sh_cl_ddr_rvalid_2d[1]),\n\n\t      .pins_ddr_b_wdata(cl_sh_ddr_wdata_2d[1]),\n\t      //.pins_ddr_b_wid(cl_sh_ddr_wid_2d[1]),\n\t      .pins_ddr_b_wlast(cl_sh_ddr_wlast_2d[1]),\n\t      .pins_ddr_b_wready(sh_cl_ddr_wready_2d[1]),\n\t      .pins_ddr_b_wstrb(cl_sh_ddr_wstrb_2d[1]),\n\t      .pins_ddr_b_wvalid(cl_sh_ddr_wvalid_2d[1]),\n\n`endif // AWSF1_DDR_B\n\n// DDR3 END\n\n `ifdef AWSF1_DMA_PCIS\n\t      .pins_pcis_araddr(sh_cl_dma_pcis_araddr[39:0]),\n\t      .pins_pcis_arburst(1),\n\t      .pins_pcis_arcache(0),\n\t      .pins_pcis_arid(sh_cl_dma_pcis_arid),\n\t      .pins_pcis_arlen(sh_cl_dma_pcis_arlen),\n\t      .pins_pcis_arlock(0),\n\t      .pins_pcis_arprot(0),\n\t      .pins_pcis_arqos(0),\n\t      .pins_pcis_arready(cl_sh_dma_pcis_arready),\n\t      .pins_pcis_arsize(sh_cl_dma_pcis_arsize),\n\t      .pins_pcis_arvalid(sh_cl_dma_pcis_arvalid),\n\n\t      .pins_pcis_awaddr(sh_cl_dma_pcis_awaddr[39:0]),\n\t      .pins_pcis_awburst(1),\n\t      .pins_pcis_awcache(0),\n\t      .pins_pcis_awid(sh_cl_dma_pcis_awid),\n\t      .pins_pcis_awlen(sh_cl_dma_pcis_awlen),\n\t      .pins_pcis_awlock(0),\n\t      .pins_pcis_awprot(0),\n\t      .pins_pcis_awqos(0),\n\t      .pins_pcis_awready(cl_sh_dma_pcis_awready),\n\t      .pins_pcis_awsize(sh_cl_dma_pcis_awsize),\n\t      .pins_pcis_awvalid(sh_cl_dma_pcis_awvalid),\n\n\t      .pins_pcis_bid(cl_sh_dma_pcis_bid),\n\t      .pins_pcis_bready(sh_cl_dma_pcis_bready),\n\t      .pins_pcis_bresp(cl_sh_dma_pcis_bresp),\n\t      .pins_pcis_bvalid(cl_sh_dma_pcis_bvalid),\n\n\t      .pins_pcis_rdata(cl_sh_dma_pcis_rdata),\n\t      .pins_pcis_rid(cl_sh_dma_pcis_rid),\n\t      .pins_pcis_rlast(cl_sh_dma_pcis_rlast),\n\t      .pins_pcis_rready(sh_cl_dma_pcis_rready),\n\t      .pins_pcis_rresp(cl_sh_dma_pcis_rresp),\n\t      .pins_pcis_rvalid(cl_sh_dma_pcis_rvalid),\n\n\t      .pins_pcis_wdata(sh_cl_dma_pcis_wdata),\n\t      .pins_pcis_wlast(sh_cl_dma_pcis_wlast),\n\t      .pins_pcis_wready(cl_sh_dma_pcis_wready),\n\t      .pins_pcis_wstrb(sh_cl_dma_pcis_wstrb),\n\t      .pins_pcis_wvalid(sh_cl_dma_pcis_wvalid),\n`endif\n\t      .pcim_araddr(cl_sh_pcim_araddr[39:0]),\n\t      //.pcim_arburst(pcim_arburst),\n\t      //.pcim_arcache(pcim_arcache),\n\t      //.pcim_aresetn(pcim_aresetn),\n\t      .pcim_arid(cl_sh_pcim_arid),\n\t      .pcim_arlen(cl_sh_pcim_arlen),\n\t      //.pcim_arlock(pcim_arlock),\n\t      //.pcim_arprot(pcim_arprot),\n\t      //.pcim_arqos(pcim_arqos),\n\t      .pcim_arready_v(sh_cl_pcim_arready),\n\t      .pcim_arsize(cl_sh_pcim_arsize),\n\t      .pcim_arvalid(cl_sh_pcim_arvalid),\n\t      //RESERVED: .pcim_extra_aruser(cl_sh_pcim_aruser),\n\n\t      .pcim_awaddr(cl_sh_pcim_awaddr[39:0]),\n\t      //.pcim_awburst(pcim_awburst),\n\t      //.pcim_awcache(pcim_awcache),\n\t      .pcim_awid(cl_sh_pcim_awid),\n\t      .pcim_awlen(cl_sh_pcim_awlen),\n\t      //.pcim_awlock(pcim_awlock),\n\t      //.pcim_awprot(pcim_awprot),\n\t      //.pcim_awqos(pcim_awqos),\n\t      .pcim_awready_v(sh_cl_pcim_awready),\n\t      .pcim_awsize(cl_sh_pcim_awsize),\n\t      .pcim_awvalid(cl_sh_pcim_awvalid),\n\t      //RESERVED: .pcim_extra_awuser(cl_sh_pcim_awuser),\n\n\t      .pcim_bid_v(sh_cl_pcim_bid),\n\t      .pcim_bready(cl_sh_pcim_bready),\n\t      .pcim_bresp_v(sh_cl_pcim_bresp),\n\t      .pcim_bvalid_v(sh_cl_pcim_bvalid),\n\n\t      .pcim_rdata_v(sh_cl_pcim_rdata),\n\t      .pcim_rid_v(sh_cl_pcim_rid),\n\t      .pcim_rlast_v(sh_cl_pcim_rlast),\n\t      .pcim_rready(cl_sh_pcim_rready),\n\t      .pcim_rresp_v(sh_cl_pcim_rresp),\n\t      .pcim_rvalid_v(sh_cl_pcim_rvalid),\n\n\t      .pcim_wdata(cl_sh_pcim_wdata),\n\t      //.pcim_wid(cl_sh_pcim_wid), // No longer part of AXI4 spec\n\t      .pcim_wlast(cl_sh_pcim_wlast),\n\t      .pcim_wready_v(sh_cl_pcim_wready),\n\t      .pcim_wstrb(cl_sh_pcim_wstrb),\n\t      .pcim_wvalid(cl_sh_pcim_wvalid)\n);\n\n\n`ifdef AWSF1_CL_DEBUG_BRIDGE\n`ifdef AWSF1_DMA_PCIS\n`ifdef AWSF1_AXI_PROTOCOL_CHECKER\naxi_protocol_checker_0 axi_protocol_checker_i (\n  .pc_status(pc_status),              // output wire [159 : 0] pc_status\n  .pc_asserted(pc_asserted),          // output wire pc_asserted\n  .aclk(clk_main_a0),                        // input wire aclk\n  .aresetn(rst_main_n),                  // input wire aresetn\n  .pc_axi_awid(sh_cl_dma_pcis_awid),          // input wire [5 : 0] pc_axi_awid\n  .pc_axi_awaddr(sh_cl_dma_pcis_awaddr),      // input wire [63 : 0] pc_axi_awaddr\n  .pc_axi_awlen(sh_cl_dma_pcis_awlen),        // input wire [7 : 0] pc_axi_awlen\n  .pc_axi_awsize(sh_cl_dma_pcis_awsize),      // input wire [2 : 0] pc_axi_awsize\n  .pc_axi_awburst(1),    // input wire [1 : 0] pc_axi_awburst\n  .pc_axi_awlock(0),      // input wire [0 : 0] pc_axi_awlock\n  .pc_axi_awcache(0),    // input wire [3 : 0] pc_axi_awcache\n  .pc_axi_awprot(0),      // input wire [2 : 0] pc_axi_awprot\n  .pc_axi_awqos(0),        // input wire [3 : 0] pc_axi_awqos\n  .pc_axi_awregion(0),  // input wire [3 : 0] pc_axi_awregion\n  .pc_axi_awvalid(sh_cl_dma_pcis_awvalid),    // input wire pc_axi_awvalid\n  .pc_axi_awready(cl_sh_dma_pcis_awready),    // input wire pc_axi_awready\n  .pc_axi_wlast(sh_cl_dma_pcis_wlast),        // input wire pc_axi_wlast\n  .pc_axi_wdata(sh_cl_dma_pcis_wdata),        // input wire [511 : 0] pc_axi_wdata\n  .pc_axi_wstrb(sh_cl_dma_pcis_wstrb),        // input wire [63 : 0] pc_axi_wstrb\n  .pc_axi_wvalid(sh_cl_dma_pcis_wvalid),      // input wire pc_axi_wvalid\n  .pc_axi_wready(cl_sh_dma_pcis_wready),      // input wire pc_axi_wready\n  .pc_axi_bid(cl_sh_dma_pcis_bid),            // input wire [5 : 0] pc_axi_bid\n  .pc_axi_bresp(cl_sh_dma_pcis_bresp),        // input wire [1 : 0] pc_axi_bresp\n  .pc_axi_bvalid(cl_sh_dma_pcis_bvalid),      // input wire pc_axi_bvalid\n  .pc_axi_bready(sh_cl_dma_pcis_bready),      // input wire pc_axi_bready\n  .pc_axi_arid(sh_cl_dma_pcis_arid),          // input wire [5 : 0] pc_axi_arid\n  .pc_axi_araddr(sh_cl_dma_pcis_araddr),      // input wire [63 : 0] pc_axi_araddr\n  .pc_axi_arlen(sh_cl_dma_pcis_arlen),        // input wire [7 : 0] pc_axi_arlen\n  .pc_axi_arsize(sh_cl_dma_pcis_arsize),      // input wire [2 : 0] pc_axi_arsize\n  .pc_axi_arburst(1),    // input wire [1 : 0] pc_axi_arburst\n  .pc_axi_arlock(0),      // input wire [0 : 0] pc_axi_arlock\n  .pc_axi_arcache(0),    // input wire [3 : 0] pc_axi_arcache\n  .pc_axi_arprot(0),      // input wire [2 : 0] pc_axi_arprot\n  .pc_axi_arqos(0),        // input wire [3 : 0] pc_axi_arqos\n  .pc_axi_arregion(0),  // input wire [3 : 0] pc_axi_arregion\n  .pc_axi_arvalid(sh_cl_dma_pcis_arvalid),    // input wire pc_axi_arvalid\n  .pc_axi_arready(cl_sh_dma_pcis_arready),    // input wire pc_axi_arready\n  .pc_axi_rid(cl_sh_dma_pcis_rid),            // input wire [5 : 0] pc_axi_rid\n  .pc_axi_rlast(cl_sh_dma_pcis_rlast),        // input wire pc_axi_rlast\n  .pc_axi_rdata(cl_sh_dma_pcis_rdata),        // input wire [511 : 0] pc_axi_rdata\n  .pc_axi_rresp(cl_sh_dma_pcis_rresp),        // input wire [1 : 0] pc_axi_rresp\n  .pc_axi_rvalid(cl_sh_dma_pcis_rvalid),      // input wire pc_axi_rvalid\n  .pc_axi_rready(sh_cl_dma_pcis_rready)      // input wire pc_axi_rready\n);\n`endif // AWSF1_AXI_PROTOCOL_CHECKER\n`endif //  `ifdef AWSF1_DMA_PCIS\n`endif //  `ifdef AWSF1_CL_DEBUG_BRIDGE\n\n   endmodule\n"
  },
  {
    "path": "verilog/cl_id_defines.vh",
    "content": "// Amazon FPGA Hardware Development Kit\n//\n// Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved.\n//\n// Licensed under the Amazon Software License (the \"License\"). You may not use\n// this file except in compliance with the License. A copy of the License is\n// located at\n//\n//    http://aws.amazon.com/asl/\n//\n// or in the \"license\" file accompanying this file. This file is distributed on\n// an \"AS IS\" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or\n// implied. See the License for the specific language governing permissions and\n// limitations under the License.\n\n// CL_SH_ID0\n// - PCIe Vendor/Device ID Values\n//    31:16: PCIe Device ID\n//    15: 0: PCIe Vendor ID\n//    - A Vendor ID value of 0x8086 is not valid.\n//    - If using a Vendor ID value of 0x1D0F (Amazon) then valid\n//      values for Device ID's are in the range of 0xF000 - 0xF0FF.\n//    - A Vendor/Device ID of 0 (zero) is not valid.\n`define CL_SH_ID0       32'hF000_1D0F\n\n// CL_SH_ID1\n// - PCIe Subsystem/Subsystem Vendor ID Values\n//    31:16: PCIe Subsystem ID\n//    15: 0: PCIe Subsystem Vendor ID\n// - A PCIe Subsystem/Subsystem Vendor ID of 0 (zero) is not valid\n`define CL_SH_ID1       32'h1D51_FEDD\n"
  },
  {
    "path": "verilog/xsimtop.sv",
    "content": "// Copyright (c) 2015 The Connectal Project\n\n// Permission is hereby granted, free of charge, to any person\n// obtaining a copy of this software and associated documentation\n// files (the \"Software\"), to deal in the Software without\n// restriction, including without limitation the rights to use, copy,\n// modify, merge, publish, distribute, sublicense, and/or sell copies\n// of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be\n// included in all copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n`timescale 1ns / 1ps\n\n\n`ifdef BSV_POSITIVE_RESET\n  `define BSV_RESET_VALUE 1'b1\n  `define BSV_RESET_EDGE posedge\n`else\n  `define BSV_RESET_VALUE 1'b0\n  `define BSV_RESET_EDGE negedge\n`endif\n\n`ifndef MainClockPeriod\n   `define MainClockPeriod 4\n`endif\n`ifndef DerivedClockPeriod\n   `define DerivedClockPeriod 4\n`endif\n`define XSIM\n\nmodule xsimtop(\n`ifndef XSIM\n\t       CLK, DERIVED_CLK, sys_clk\n`endif\n);\n`ifndef XSIM\n   input CLK;\n   input DERIVED_CLK;\n   input sys_clk;\n`else\n   reg \t CLK;\n   reg DERIVED_CLK;\n   reg sys_clk;\n`endif\n   reg RST_N;\n   reg DERIVED_RST_N;\n   reg [31:0] count;\n   reg [31:0] count_derived;\n   reg finish;\n\n   import \"DPI-C\" function void dpi_init(input int unused);\n   import \"DPI-C\" function bit dpi_cycle(input int returns); // unused non-zero if verilog should $finish().\n\n`ifdef __ATOMICC__\n   VsimTop connectalTop(.CLK(CLK), .nRST(RST_N),\n\t\t\t  .CLK_derivedClock(DERIVED_CLK), .nRST_derivedReset(DERIVED_RST_N),\n\t\t\t  .CLK_sys_clk(sys_clk));\n`else\n   mkXsimTop connectalTop(.CLK(CLK), .RST_N(RST_N),\n\t\t\t  .CLK_derivedClock(DERIVED_CLK), .RST_N_derivedReset(DERIVED_RST_N),\n\t\t\t  .CLK_sys_clk(sys_clk));\n`endif\n   initial begin\n`ifdef XSIM\n      CLK = 1'b0;\n      DERIVED_CLK = 1'b0;\n      sys_clk = 1'b0;\n`endif\n      RST_N = `BSV_RESET_VALUE;\n      DERIVED_RST_N = `BSV_RESET_VALUE;\n      count = 0;\n      count_derived = 0;\n      finish = 1'b0;\n      dpi_init(0);\n   end\n\n`ifdef XSIM\n   always begin\n      #(`MainClockPeriod/2)\n\tCLK = !CLK;\n   end\n   always begin\n      #(`DerivedClockPeriod/2)\n\tDERIVED_CLK = !DERIVED_CLK;\n   end\n   always begin\n      #2.5\n\tsys_clk = !sys_clk;\n   end\n`endif\n   \n   always @(posedge CLK) begin\n      count <= count + 1;\n      finish <= dpi_cycle(0);\n      if (finish) begin\n\t $display(\"simulator calling $finish\");\n\t $finish();\n      end\n   end\n   always @(`BSV_RESET_EDGE CLK) begin\n      if (count == 20) begin\n\t RST_N <= !`BSV_RESET_VALUE;\n      end\n   end\n   always @(`BSV_RESET_EDGE DERIVED_CLK) begin\n      count_derived <= count_derived + 1;\n      if (count_derived == 20) begin\n\t DERIVED_RST_N <= !`BSV_RESET_VALUE;\n      end\n   end\nendmodule\n\n\n"
  }
]